Index: stable/12/lib/libpmc/pmu-events/arch/x86/amdfam17h/core.json
===================================================================
--- stable/12/lib/libpmc/pmu-events/arch/x86/amdfam17h/core.json	(revision 363587)
+++ stable/12/lib/libpmc/pmu-events/arch/x86/amdfam17h/core.json	(revision 363588)
@@ -1,127 +1,127 @@
 [
  {
  "EventName": "ex_ret_instr",
  "EventCode": "0xc0",
+ "SampleAfterValue": "2000003",
  "BriefDescription": "Retired Instructions."
-  "SampleAfterValue": "2000003",
  },
  {
  "EventName": "ex_ret_cops",
  "EventCode": "0xc1",
+ "SampleAfterValue": "2000003",
  "BriefDescription": "The number of uOps retired. This includes all processor activity (instructions, exceptions, interrupts, microcode assists, etc.). The number of events logged per cycle can vary from 0 to 4."
-  "SampleAfterValue": "2000003",
  },
  {
  "EventName": "ex_ret_brn",
  "EventCode": "0xc2",
+ "SampleAfterValue": "2000003",
  "BriefDescription": "The number of branch instructions retired. This includes all types of architectural control flow changes, including exceptions and interrupts."
-  "SampleAfterValue": "2000003",
  },
  {
  "EventName": "ex_ret_brn_misp",
  "EventCode": "0xc3",
  "BriefDescription": "The number of branch instructions retired, of any type, that were not correctly predicted. This includes those for which prediction is not attempted (far control transfers, exceptions and interrupts)."
  },
  {
  "EventName": "ex_ret_brn_tkn",
  "EventCode": "0xc4",
  "BriefDescription": "The number of taken branches that were retired. This includes all types of architectural control flow changes, including exceptions and interrupts."
  },
  {
  "EventName": "ex_ret_brn_tkn_misp",
  "EventCode": "0xc5",
  "BriefDescription": "The number of retired taken branch instructions that were mispredicted."
  },
  {
  "EventName": "ex_ret_brn_far",
  "EventCode": "0xc6",
  "BriefDescription": "The number of far control transfers retired including far call/jump/return, IRET, SYSCALL and SYSRET, plus exceptions and interrupts. Far control transfers are not subject to branch prediction."
  },
  {
  "EventName": "ex_ret_brn_resync",
  "EventCode": "0xc7",
  "BriefDescription": "The number of resync branches. These reflect pipeline restarts due to certain microcode assists and events such as writes to the active instruction stream, among other things. Each occurrence reflects a restart penalty similar to a branch mispredict. This is relatively rare."
  },
  {
  "EventName": "ex_ret_near_ret",
  "EventCode": "0xc8",
  "BriefDescription": "The number of near return instructions (RET or RET Iw) retired."
  },
  {
  "EventName": "ex_ret_near_ret_mispred",
  "EventCode": "0xc9",
  "BriefDescription": "The number of near returns retired that were not correctly predicted by the return address predictor. Each such mispredict incurs the same penalty as a mispredicted conditional branch instruction."
  },
  {
  "EventName": "ex_ret_brn_ind_misp",
  "EventCode": "0xca",
  "BriefDescription": "Retired Indirect Branch Instructions Mispredicted."
  },
  {
  "EventName": "ex_ret_mmx_fp_instr.sse_instr",
  "EventCode": "0xcb",
  "BriefDescription": "SSE instructions (SSE, SSE2, SSE3, SSSE3, SSE4A, SSE41, SSE42, AVX).",
  "PublicDescription": "The number of MMX, SSE or x87 instructions retired. The UnitMask allows the selection of the individual classes of instructions as given in the table. Each increment represents one complete instruction. Since this event includes non-numeric instructions it is not suitable for measuring MFLOPS. SSE instructions (SSE, SSE2, SSE3, SSSE3, SSE4A, SSE41, SSE42, AVX).",
  "UMask": "0x4"
  },
  {
  "EventName": "ex_ret_mmx_fp_instr.mmx_instr",
  "EventCode": "0xcb",
  "BriefDescription": "MMX instructions.",
  "PublicDescription": "The number of MMX, SSE or x87 instructions retired. The UnitMask allows the selection of the individual classes of instructions as given in the table. Each increment represents one complete instruction. Since this event includes non-numeric instructions it is not suitable for measuring MFLOPS. MMX instructions.",
  "UMask": "0x2"
  },
  {
  "EventName": "ex_ret_mmx_fp_instr.x87_instr",
  "EventCode": "0xcb",
  "BriefDescription": "x87 instructions.",
  "PublicDescription": "The number of MMX, SSE or x87 instructions retired. The UnitMask allows the selection of the individual classes of instructions as given in the table. Each increment represents one complete instruction. Since this event includes non-numeric instructions it is not suitable for measuring MFLOPS. x87 instructions.",
  "UMask": "0x1"
  },
  {
  "EventName": "ex_ret_cond",
  "EventCode": "0xd1",
  "BriefDescription": "Retired Conditional Branch Instructions."
  },
  {
  "EventName": "ex_ret_cond_misp",
  "EventCode": "0xd2",
  "BriefDescription": "Retired Conditional Branch Instructions Mispredicted."
  },
  {
  "EventName": "ex_div_busy",
  "EventCode": "0xd3",
  "BriefDescription": "Div Cycles Busy count."
  },
  {
  "EventName": "ex_div_count",
  "EventCode": "0xd4",
  "BriefDescription": "Div Op Count."
  },
  {
  "EventName": "ex_tagged_ibs_ops.ibs_count_rollover",
  "EventCode": "0x1cf",
  "BriefDescription": "Number of times an op could not be tagged by IBS because of a previous tagged op that has not retired.",
  "PublicDescription": "Tagged IBS Ops. Number of times an op could not be tagged by IBS because of a previous tagged op that has not retired.",
  "UMask": "0x4"
  },
  {
  "EventName": "ex_tagged_ibs_ops.ibs_tagged_ops_ret",
  "EventCode": "0x1cf",
  "BriefDescription": "Number of Ops tagged by IBS that retired.",
  "PublicDescription": "Tagged IBS Ops. Number of Ops tagged by IBS that retired.",
  "UMask": "0x2"
  },
  {
  "EventName": "ex_tagged_ibs_ops.ibs_tagged_ops",
  "EventCode": "0x1cf",
  "BriefDescription": "Number of Ops tagged by IBS.",
  "PublicDescription": "Tagged IBS Ops. Number of Ops tagged by IBS.",
  "UMask": "0x1"
  },
  {
  "EventName": "ex_ret_fus_brnch_inst",
  "EventCode": "0x1d0",
  "BriefDescription": "The number of fused retired branch instructions retired per cycle. The number of events logged per cycle can vary from 0 to 3."
  }
 ]
Index: stable/12/lib/libpmc/pmu-events/arch/x86/amdfam17h/memory.json
===================================================================
--- stable/12/lib/libpmc/pmu-events/arch/x86/amdfam17h/memory.json	(revision 363587)
+++ stable/12/lib/libpmc/pmu-events/arch/x86/amdfam17h/memory.json	(revision 363588)
@@ -1,226 +1,226 @@
 [
  {
  "EventName": "ls_locks.spec_lock_map_commit",
  "EventCode": "0x25",
  "BriefDescription": "Unit Masks ORed.",
  "PublicDescription": "Unit Masks ORed.",
  "UMask": "0x8"
  },
  {
  "EventName": "ls_locks.spec_lock",
  "EventCode": "0x25",
  "BriefDescription": "Unit Masks ORed.",
  "PublicDescription": "Unit Masks ORed.",
  "UMask": "0x4"
  },
  {
  "EventName": "ls_locks.non_spec_lock",
  "EventCode": "0x25",
  "BriefDescription": "Unit Masks ORed.",
  "PublicDescription": "Unit Masks ORed.",
  "UMask": "0x2"
  },
  {
  "EventName": "ls_locks.bus_lock",
  "EventCode": "0x25",
  "BriefDescription": "Unit Masks ORed.",
  "PublicDescription": "Unit Masks ORed.",
  "UMask": "0x1"
  },
  {
  "EventName": "ls_dispatch.ld_st_dispatch",
  "EventCode": "0x29",
  "BriefDescription": "Load-op-Stores.",
  "PublicDescription": "Counts the number of operations dispatched to the LS unit. Unit Masks ADDed. Load-op-Stores.",
  "UMask": "0x4"
  },
  {
  "EventName": "ls_dispatch.store_dispatch",
  "EventCode": "0x29",
  "BriefDescription": "Counts the number of operations dispatched to the LS unit. Unit Masks ADDed.",
  "PublicDescription": "Counts the number of operations dispatched to the LS unit. Unit Masks ADDed.",
  "UMask": "0x2"
  },
  {
  "EventName": "ls_dispatch.ld_dispatch",
  "EventCode": "0x29",
  "BriefDescription": "Counts the number of operations dispatched to the LS unit. Unit Masks ADDed.",
  "PublicDescription": "Counts the number of operations dispatched to the LS unit. Unit Masks ADDed.",
  "UMask": "0x1"
  },
  {
  "EventName": "ls_stlf",
  "EventCode": "0x35",
  "BriefDescription": "Number of STLF hits."
  },
  {
  "EventName": "ls_dc_accesses",
  "EventCode": "0x40",
  "BriefDescription": "The number of accesses to the data cache for load and store references. This may include certain microcode scratchpad accesses, although these are generally rare. Each increment represents an eight-byte access, although the instruction may only be accessing a portion of that. This event is a speculative event."
  },
  {
  "EventName": "ls_mab_alloc_pipe.tlb_pipe_early",
  "EventCode": "0x41",
  "BriefDescription": "MAB Allocation by Pipe.",
  "PublicDescription": "MAB Allocation by Pipe.",
  "UMask": "0x10"
  },
  {
  "EventName": "ls_mab_alloc_pipe.hw_pf",
  "EventCode": "0x41",
  "BriefDescription": "MAB Allocation by Pipe.",
  "PublicDescription": "MAB Allocation by Pipe.",
  "UMask": "0x8"
  },
  {
  "EventName": "ls_mab_alloc_pipe.tlb_pipe_late",
  "EventCode": "0x41",
  "BriefDescription": "MAB Allocation by Pipe.",
  "PublicDescription": "MAB Allocation by Pipe.",
  "UMask": "0x4"
  },
  {
  "EventName": "ls_mab_alloc_pipe.st_pipe",
  "EventCode": "0x41",
  "BriefDescription": "MAB Allocation by Pipe.",
  "PublicDescription": "MAB Allocation by Pipe.",
  "UMask": "0x2"
  },
  {
  "EventName": "ls_mab_alloc_pipe.data_pipe",
  "EventCode": "0x41",
  "BriefDescription": "MAB Allocation by Pipe.",
  "PublicDescription": "MAB Allocation by Pipe.",
  "UMask": "0x1"
  },
  {
  "EventName": "ls_l1_d_tlb_miss.tlb_reload1_gl2_miss",
  "EventCode": "0x45",
  "BriefDescription": "L1 DTLB Miss.",
  "PublicDescription": "L1 DTLB Miss.",
  "UMask": "0x80"
  },
  {
  "EventName": "ls_l1_d_tlb_miss.tlb_reload2_ml2_miss",
  "EventCode": "0x45",
  "BriefDescription": "L1 DTLB Miss.",
  "PublicDescription": "L1 DTLB Miss.",
  "UMask": "0x40"
  },
  {
  "EventName": "ls_l1_d_tlb_miss.tlb_reload32_kl2_miss",
  "EventCode": "0x45",
  "BriefDescription": "L1 DTLB Miss.",
  "PublicDescription": "L1 DTLB Miss.",
  "UMask": "0x20"
  },
  {
  "EventName": "ls_l1_d_tlb_miss.tlb_reload4_kl2_miss",
  "EventCode": "0x45",
  "BriefDescription": "L1 DTLB Miss.",
  "PublicDescription": "L1 DTLB Miss.",
  "UMask": "0x10"
  },
  {
  "EventName": "ls_l1_d_tlb_miss.tlb_reload1_gl2_hit",
  "EventCode": "0x45",
  "BriefDescription": "L1 DTLB Miss.",
  "PublicDescription": "L1 DTLB Miss.",
  "UMask": "0x8"
  },
  {
  "EventName": "ls_l1_d_tlb_miss.tlb_reload2_ml2_hit",
  "EventCode": "0x45",
  "BriefDescription": "L1 DTLB Miss.",
  "PublicDescription": "L1 DTLB Miss.",
  "UMask": "0x4"
  },
  {
  "EventName": "ls_l1_d_tlb_miss.tlb_reload32_kl2_hit",
  "EventCode": "0x45",
  "BriefDescription": "L1 DTLB Miss.",
  "PublicDescription": "L1 DTLB Miss.",
  "UMask": "0x2"
  },
  {
  "EventName": "ls_l1_d_tlb_miss.tlb_reload4_kl2_hit",
  "EventCode": "0x45",
  "BriefDescription": "L1 DTLB Miss.",
  "PublicDescription": "L1 DTLB Miss.",
  "UMask": "0x1"
  },
  {
  "EventName": "ls_tablewalker.perf_mon_tablewalk_alloc_iside1",
  "EventCode": "0x46",
  "BriefDescription": "Tablewalker allocation.",
  "PublicDescription": "Tablewalker allocation.",
  "UMask": "0x8"
  },
  {
  "EventName": "ls_tablewalker.perf_mon_tablewalk_alloc_iside0",
  "EventCode": "0x46",
  "BriefDescription": "Tablewalker allocation.",
  "PublicDescription": "Tablewalker allocation.",
  "UMask": "0x4"
  },
  {
  "EventName": "ls_tablewalker.perf_mon_tablewalk_alloc_dside1",
  "EventCode": "0x46",
  "BriefDescription": "Tablewalker allocation.",
  "PublicDescription": "Tablewalker allocation.",
  "UMask": "0x2"
  },
  {
  "EventName": "ls_tablewalker.perf_mon_tablewalk_alloc_dside0",
  "EventCode": "0x46",
  "BriefDescription": "Tablewalker allocation.",
  "PublicDescription": "Tablewalker allocation.",
  "UMask": "0x1"
  },
  {
  "EventName": "ls_misal_accesses",
  "EventCode": "0x47",
  "BriefDescription": "Misaligned loads."
  },
  {
  "EventName": "ls_pref_instr_disp.prefetch_nta",
  "EventCode": "0x4b",
  "BriefDescription": "Software Prefetch Instructions Dispatched.",
  "PublicDescription": "Software Prefetch Instructions Dispatched.",
  "UMask": "0x4"
  },
  {
  "EventName": "ls_pref_instr_disp.store_prefetch_w",
  "EventCode": "0x4b",
  "BriefDescription": "Software Prefetch Instructions Dispatched.",
  "PublicDescription": "Software Prefetch Instructions Dispatched.",
  "UMask": "0x2"
  },
  {
  "EventName": "ls_pref_instr_disp.load_prefetch_w",
  "EventCode": "0x4b",
  "BriefDescription": "Prefetch, Prefetch_T0_T1_T2.",
  "PublicDescription": "Software Prefetch Instructions Dispatched. Prefetch, Prefetch_T0_T1_T2.",
  "UMask": "0x1"
  },
  {
  "EventName": "ls_inef_sw_pref.mab_mch_cnt",
  "EventCode": "0x52",
  "BriefDescription": "The number of software prefetches that did not fetch data outside of the processor core.",
  "PublicDescription": "The number of software prefetches that did not fetch data outside of the processor core.",
  "UMask": "0x2"
  },
  {
  "EventName": "ls_inef_sw_pref.data_pipe_sw_pf_dc_hit",
  "EventCode": "0x52",
  "BriefDescription": "The number of software prefetches that did not fetch data outside of the processor core.",
  "PublicDescription": "The number of software prefetches that did not fetch data outside of the processor core.",
  "UMask": "0x1"
  },
  {
  "EventName": "ls_not_halted_cyc",
  "EventCode": "0x76",
- "BriefDescription": "Cycles not in Halt."
  "SampleAfterValue": "2000003",
+ "BriefDescription": "Cycles not in Halt."
  }
 ]
Index: stable/12
===================================================================
--- stable/12	(revision 363587)
+++ stable/12	(revision 363588)

Property changes on: stable/12
___________________________________________________________________
Modified: svn:mergeinfo
## -0,0 +0,1 ##
   Merged /head:r355666