Index: head/share/man/man4/Makefile =================================================================== --- head/share/man/man4/Makefile (revision 363179) +++ head/share/man/man4/Makefile (revision 363180) @@ -1,1027 +1,1028 @@ # @(#)Makefile 8.1 (Berkeley) 6/18/93 # $FreeBSD$ .include MAN= aac.4 \ aacraid.4 \ acpi.4 \ ${_acpi_asus.4} \ ${_acpi_asus_wmi.4} \ ${_acpi_dock.4} \ ${_acpi_fujitsu.4} \ ${_acpi_hp.4} \ ${_acpi_ibm.4} \ ${_acpi_panasonic.4} \ ${_acpi_rapidstart.4} \ ${_acpi_sony.4} \ acpi_thermal.4 \ acpi_battery.4 \ ${_acpi_toshiba.4} \ acpi_video.4 \ ${_acpi_wmi.4} \ ada.4 \ adm6996fc.4 \ ads111x.4 \ ae.4 \ ${_aesni.4} \ age.4 \ agp.4 \ ahc.4 \ ahci.4 \ ahd.4 \ ${_aibs.4} \ aio.4 \ alc.4 \ ale.4 \ alpm.4 \ altera_atse.4 \ altera_avgen.4 \ altera_jtag_uart.4 \ altera_sdcard.4 \ altq.4 \ amdpm.4 \ ${_amdsbwd.4} \ ${_amdsmb.4} \ ${_amdsmn.4} \ ${_amdtemp.4} \ ${_bxe.4} \ amr.4 \ an.4 \ ${_aout.4} \ ${_apic.4} \ arcmsr.4 \ ${_asmc.4} \ at45d.4 \ ata.4 \ ath.4 \ ath_ahb.4 \ ath_hal.4 \ ath_pci.4 \ atkbd.4 \ atkbdc.4 \ atp.4 \ ${_atf_test_case.4} \ ${_atrtc.4} \ ${_attimer.4} \ audit.4 \ auditpipe.4 \ aue.4 \ axe.4 \ axge.4 \ bce.4 \ bcma.4 \ bfe.4 \ bge.4 \ ${_bhyve.4} \ bhnd.4 \ bhnd_chipc.4 \ bhnd_pmu.4 \ bhndb.4 \ bhndb_pci.4 \ blackhole.4 \ bnxt.4 \ bpf.4 \ bridge.4 \ bt.4 \ bwi.4 \ bwn.4 \ ${_bytgpio.4} \ capsicum.4 \ cardbus.4 \ carp.4 \ cas.4 \ cc_cdg.4 \ cc_chd.4 \ cc_cubic.4 \ cc_dctcp.4 \ cc_hd.4 \ cc_htcp.4 \ cc_newreno.4 \ cc_vegas.4 \ ${_ccd.4} \ ccr.4 \ cd.4 \ cdce.4 \ cdceem.4 \ cfi.4 \ cfumass.4 \ ch.4 \ chromebook_platform.4 \ ${_chvgpio.4} \ ciss.4 \ cloudabi.4 \ cmx.4 \ ${_coretemp.4} \ ${_cpuctl.4} \ cpufreq.4 \ crypto.4 \ ctl.4 \ cue.4 \ cxgb.4 \ cxgbe.4 \ cxgbev.4 \ cy.4 \ cyapa.4 \ da.4 \ dc.4 \ dcons.4 \ dcons_crom.4 \ ddb.4 \ devctl.4 \ disc.4 \ divert.4 \ ${_dpms.4} \ ds1307.4 \ ds3231.4 \ ${_dtrace_provs} \ dummynet.4 \ edsc.4 \ ehci.4 \ em.4 \ ena.4 \ enc.4 \ epair.4 \ esp.4 \ est.4 \ et.4 \ etherswitch.4 \ eventtimers.4 \ exca.4 \ e6060sw.4 \ fd.4 \ fdc.4 \ fdt.4 \ fdt_pinctrl.4 \ fdtbus.4 \ ffclock.4 \ filemon.4 \ firewire.4 \ full.4 \ fwe.4 \ fwip.4 \ fwohci.4 \ fxp.4 \ gbde.4 \ gdb.4 \ gem.4 \ geom.4 \ geom_linux_lvm.4 \ geom_map.4 \ geom_uzip.4 \ gif.4 \ gpio.4 \ gpioiic.4 \ gpioled.4 \ gpioths.4 \ gre.4 \ h_ertt.4 \ hifn.4 \ hme.4 \ hpet.4 \ ${_hpt27xx.4} \ ${_hptiop.4} \ ${_hptmv.4} \ ${_hptnr.4} \ ${_hptrr.4} \ ${_hv_kvp.4} \ ${_hv_netvsc.4} \ ${_hv_storvsc.4} \ ${_hv_utils.4} \ ${_hv_vmbus.4} \ ${_hv_vss.4} \ hwpmc.4 \ ${_hwpstate_intel.4} \ iavf.4 \ ichsmb.4 \ ${_ichwd.4} \ icmp.4 \ icmp6.4 \ ida.4 \ if_ipsec.4 \ iflib.4 \ ifmib.4 \ ig4.4 \ igmp.4 \ iic.4 \ iic_gpiomux.4 \ iicbb.4 \ iicbus.4 \ iicmux.4 \ iicsmb.4 \ iir.4 \ ${_imcsmb.4} \ inet.4 \ inet6.4 \ intpm.4 \ intro.4 \ ${_io.4} \ ${_ioat.4} \ ip.4 \ ip6.4 \ ipfirewall.4 \ ipheth.4 \ ${_ipmi.4} \ ips.4 \ ipsec.4 \ ipw.4 \ ipwfw.4 \ isci.4 \ isl.4 \ ismt.4 \ isp.4 \ ispfw.4 \ ${_itwd.4} \ iwi.4 \ iwifw.4 \ iwm.4 \ iwmfw.4 \ iwn.4 \ iwnfw.4 \ ixgbe.4 \ ixl.4 \ jedec_dimm.4 \ jme.4 \ kbdmux.4 \ keyboard.4 \ kld.4 \ ksyms.4 \ ksz8995ma.4 \ ktr.4 \ kue.4 \ lagg.4 \ le.4 \ led.4 \ lge.4 \ ${_linux.4} \ liquidio.4 \ lm75.4 \ lo.4 \ lp.4 \ lpbb.4 \ lpt.4 \ ltc430x.4 \ mac.4 \ mac_biba.4 \ mac_bsdextended.4 \ mac_ifoff.4 \ mac_lomac.4 \ mac_mls.4 \ mac_none.4 \ mac_ntpd.4 \ mac_partition.4 \ mac_portacl.4 \ mac_seeotheruids.4 \ mac_stub.4 \ mac_test.4 \ malo.4 \ md.4 \ mdio.4 \ me.4 \ mem.4 \ meteor.4 \ mfi.4 \ miibus.4 \ mk48txx.4 \ mld.4 \ mlx.4 \ mlx4en.4 \ mlx5en.4 \ mly.4 \ mmc.4 \ mmcsd.4 \ mn.4 \ mod_cc.4 \ mos.4 \ mouse.4 \ mpr.4 \ mps.4 \ mpt.4 \ mrsas.4 \ msk.4 \ mtio.4 \ multicast.4 \ muge.4 \ mvs.4 \ mwl.4 \ mwlfw.4 \ mx25l.4 \ mxge.4 \ my.4 \ ${_ndis.4} \ net80211.4 \ netdump.4 \ netfpga10g_nf10bmac.4 \ netgdb.4 \ netgraph.4 \ netintro.4 \ netmap.4 \ ${_nfe.4} \ ${_nfsmb.4} \ ng_async.4 \ ngatmbase.4 \ ng_atmllc.4 \ ng_bpf.4 \ ng_bridge.4 \ ng_bt3c.4 \ ng_btsocket.4 \ ng_car.4 \ ng_ccatm.4 \ ng_checksum.4 \ ng_cisco.4 \ ng_deflate.4 \ ng_device.4 \ nge.4 \ ng_echo.4 \ ng_eiface.4 \ ng_etf.4 \ ng_ether.4 \ ng_ether_echo.4 \ ng_frame_relay.4 \ ng_gif.4 \ ng_gif_demux.4 \ ng_h4.4 \ ng_hci.4 \ ng_hole.4 \ ng_hub.4 \ ng_iface.4 \ ng_ipfw.4 \ ng_ip_input.4 \ ng_ksocket.4 \ ng_l2cap.4 \ ng_l2tp.4 \ ng_lmi.4 \ ng_mppc.4 \ ng_nat.4 \ ng_netflow.4 \ ng_one2many.4 \ ng_patch.4 \ ng_pipe.4 \ ng_ppp.4 \ ng_pppoe.4 \ ng_pptpgre.4 \ ng_pred1.4 \ ng_rfc1490.4 \ ng_socket.4 \ ng_source.4 \ ng_split.4 \ ng_sppp.4 \ ng_sscfu.4 \ ng_sscop.4 \ ng_tag.4 \ ng_tcpmss.4 \ ng_tee.4 \ ng_tty.4 \ ng_ubt.4 \ ng_UI.4 \ ng_uni.4 \ ng_vjc.4 \ ng_vlan.4 \ nmdm.4 \ ${_ntb.4} \ ${_ntb_hw_amd.4} \ ${_ntb_hw_intel.4} \ ${_ntb_hw_plx.4} \ ${_ntb_transport.4} \ ${_nda.4} \ ${_if_ntb.4} \ null.4 \ numa.4 \ ${_nvd.4} \ ${_nvdimm.4} \ ${_nvme.4} \ ${_nvram.4} \ ${_nvram2env.4} \ oce.4 \ ocs_fc.4\ ohci.4 \ orm.4 \ ow.4 \ ow_temp.4 \ owc.4 \ ${_padlock.4} \ pass.4 \ pccard.4 \ pccbb.4 \ pcf.4 \ ${_pchtherm.4} \ pci.4 \ pcib.4 \ pcic.4 \ pcm.4 \ ${_pf.4} \ ${_pflog.4} \ ${_pfsync.4} \ pim.4 \ pms.4 \ polling.4 \ ppbus.4 \ ppc.4 \ ppi.4 \ procdesc.4 \ proto.4 \ psm.4 \ pst.4 \ pt.4 \ ptnet.4 \ pts.4 \ pty.4 \ puc.4 \ pwmc.4 \ ${_qlxge.4} \ ${_qlxgb.4} \ ${_qlxgbe.4} \ ${_qlnxe.4} \ ral.4 \ random.4 \ rc.4 \ rctl.4 \ re.4 \ rgephy.4 \ rights.4 \ rl.4 \ rndtest.4 \ route.4 \ rp.4 \ rtwn.4 \ rtwnfw.4 \ rtwn_pci.4 \ rue.4 \ sa.4 \ safe.4 \ + safexcel.4 \ sbp.4 \ sbp_targ.4 \ scc.4 \ sched_4bsd.4 \ sched_ule.4 \ screen.4 \ scsi.4 \ sctp.4 \ sdhci.4 \ sem.4 \ send.4 \ ses.4 \ ${_sfxge.4} \ sge.4 \ siba.4 \ siftr.4 \ siis.4 \ simplebus.4 \ sis.4 \ sk.4 \ ${_smartpqi.4} \ smb.4 \ smbios.4 \ smbus.4 \ smp.4 \ smsc.4 \ snd_ad1816.4 \ snd_als4000.4 \ snd_atiixp.4 \ snd_cmi.4 \ snd_cs4281.4 \ snd_csa.4 \ snd_ds1.4 \ snd_emu10k1.4 \ snd_emu10kx.4 \ snd_envy24.4 \ snd_envy24ht.4 \ snd_es137x.4 \ snd_ess.4 \ snd_fm801.4 \ snd_gusc.4 \ snd_hda.4 \ snd_hdspe.4 \ snd_ich.4 \ snd_maestro3.4 \ snd_maestro.4 \ snd_mss.4 \ snd_neomagic.4 \ snd_sbc.4 \ snd_solo.4 \ snd_spicds.4 \ snd_t4dwave.4 \ snd_uaudio.4 \ snd_via8233.4 \ snd_via82c686.4 \ snd_vibes.4 \ snp.4 \ spigen.4 \ ${_spkr.4} \ splash.4 \ sppp.4 \ ste.4 \ stf.4 \ stge.4 \ ${_superio.4} \ sym.4 \ syncache.4 \ syncer.4 \ syscons.4 \ sysmouse.4 \ tap.4 \ targ.4 \ tcp.4 \ tdfx.4 \ terasic_mtl.4 \ termios.4 \ textdump.4 \ ti.4 \ timecounters.4 \ ${_tpm.4} \ tty.4 \ tun.4 \ twa.4 \ twe.4 \ tws.4 \ udp.4 \ udplite.4 \ ure.4 \ vale.4 \ vga.4 \ vge.4 \ viapm.4 \ ${_viawd.4} \ ${_virtio.4} \ ${_virtio_balloon.4} \ ${_virtio_blk.4} \ ${_virtio_console.4} \ ${_virtio_random.4} \ ${_virtio_scsi.4} \ ${_vmci.4} \ vkbd.4 \ vlan.4 \ vxlan.4 \ ${_vmd.4} \ ${_vmm.4} \ ${_vmx.4} \ vr.4 \ vt.4 \ vte.4 \ ${_vtnet.4} \ watchdog.4 \ ${_wbwd.4} \ wi.4 \ witness.4 \ wlan.4 \ wlan_acl.4 \ wlan_amrr.4 \ wlan_ccmp.4 \ wlan_tkip.4 \ wlan_wep.4 \ wlan_xauth.4 \ wmt.4 \ ${_wpi.4} \ wsp.4 \ ${_xen.4} \ xhci.4 \ xl.4 \ ${_xnb.4} \ xpt.4 \ zero.4 MLINKS= ads111x.4 ads1013.4 \ ads111x.4 ads1014.4 \ ads111x.4 ads1015.4 \ ads111x.4 ads1113.4 \ ads111x.4 ads1114.4 \ ads111x.4 ads1115.4 MLINKS+=ae.4 if_ae.4 MLINKS+=age.4 if_age.4 MLINKS+=agp.4 agpgart.4 MLINKS+=alc.4 if_alc.4 MLINKS+=ale.4 if_ale.4 MLINKS+=altera_atse.4 atse.4 MLINKS+=altera_sdcard.4 altera_sdcardc.4 MLINKS+=altq.4 ALTQ.4 MLINKS+=ath.4 if_ath.4 MLINKS+=ath_pci.4 if_ath_pci.4 MLINKS+=an.4 if_an.4 MLINKS+=aue.4 if_aue.4 MLINKS+=axe.4 if_axe.4 MLINKS+=bce.4 if_bce.4 MLINKS+=bfe.4 if_bfe.4 MLINKS+=bge.4 if_bge.4 MLINKS+=bnxt.4 if_bnxt.4 MLINKS+=bridge.4 if_bridge.4 MLINKS+=bwi.4 if_bwi.4 MLINKS+=bwn.4 if_bwn.4 MLINKS+=${_bxe.4} ${_if_bxe.4} MLINKS+=cas.4 if_cas.4 MLINKS+=cdce.4 if_cdce.4 MLINKS+=cfi.4 cfid.4 MLINKS+=cloudabi.4 cloudabi32.4 \ cloudabi.4 cloudabi64.4 MLINKS+=crypto.4 cryptodev.4 MLINKS+=cue.4 if_cue.4 MLINKS+=cxgb.4 if_cxgb.4 MLINKS+=cxgbe.4 if_cxgbe.4 \ cxgbe.4 vcxgbe.4 \ cxgbe.4 if_vcxgbe.4 \ cxgbe.4 cxl.4 \ cxgbe.4 if_cxl.4 \ cxgbe.4 vcxl.4 \ cxgbe.4 if_vcxl.4 \ cxgbe.4 cc.4 \ cxgbe.4 if_cc.4 \ cxgbe.4 vcc.4 \ cxgbe.4 if_vcc.4 MLINKS+=cxgbev.4 if_cxgbev.4 \ cxgbev.4 cxlv.4 \ cxgbev.4 if_cxlv.4 \ cxgbev.4 ccv.4 \ cxgbev.4 if_ccv.4 MLINKS+=dc.4 if_dc.4 MLINKS+=disc.4 if_disc.4 MLINKS+=edsc.4 if_edsc.4 MLINKS+=em.4 if_em.4 \ em.4 igb.4 \ em.4 if_igb.4 MLINKS+=enc.4 if_enc.4 MLINKS+=epair.4 if_epair.4 MLINKS+=et.4 if_et.4 MLINKS+=fd.4 stderr.4 \ fd.4 stdin.4 \ fd.4 stdout.4 MLINKS+=fdt.4 FDT.4 MLINKS+=firewire.4 ieee1394.4 MLINKS+=fwe.4 if_fwe.4 MLINKS+=fwip.4 if_fwip.4 MLINKS+=fxp.4 if_fxp.4 MLINKS+=gem.4 if_gem.4 MLINKS+=geom.4 GEOM.4 MLINKS+=gif.4 if_gif.4 MLINKS+=gpio.4 gpiobus.4 MLINKS+=gpioths.4 dht11.4 MLINKS+=gpioths.4 dht22.4 MLINKS+=gre.4 if_gre.4 MLINKS+=hme.4 if_hme.4 MLINKS+=hpet.4 acpi_hpet.4 MLINKS+=${_hptrr.4} ${_rr232x.4} MLINKS+=${_attimer.4} ${_i8254.4} MLINKS+=ip.4 rawip.4 MLINKS+=ipfirewall.4 ipaccounting.4 \ ipfirewall.4 ipacct.4 \ ipfirewall.4 ipfw.4 MLINKS+=ipheth.4 if_ipheth.4 MLINKS+=ipw.4 if_ipw.4 MLINKS+=iwi.4 if_iwi.4 MLINKS+=iwm.4 if_iwm.4 MLINKS+=iwn.4 if_iwn.4 MLINKS+=ixgbe.4 ix.4 MLINKS+=ixgbe.4 if_ix.4 MLINKS+=ixgbe.4 if_ixgbe.4 MLINKS+=ixl.4 if_ixl.4 MLINKS+=iavf.4 if_iavf.4 MLINKS+=jme.4 if_jme.4 MLINKS+=kue.4 if_kue.4 MLINKS+=lagg.4 trunk.4 MLINKS+=lagg.4 if_lagg.4 MLINKS+=le.4 if_le.4 MLINKS+=lge.4 if_lge.4 MLINKS+=lo.4 loop.4 MLINKS+=lp.4 plip.4 MLINKS+=malo.4 if_malo.4 MLINKS+=md.4 vn.4 MLINKS+=mem.4 kmem.4 MLINKS+=mfi.4 mfi_linux.4 \ mfi.4 mfip.4 MLINKS+=mlx5en.4 mce.4 MLINKS+=mn.4 if_mn.4 MLINKS+=mos.4 if_mos.4 MLINKS+=msk.4 if_msk.4 MLINKS+=mwl.4 if_mwl.4 MLINKS+=mxge.4 if_mxge.4 MLINKS+=my.4 if_my.4 MLINKS+=${_ndis.4} ${_if_ndis.4} MLINKS+=netfpga10g_nf10bmac.4 if_nf10bmac.4 MLINKS+=netintro.4 net.4 \ netintro.4 networking.4 MLINKS+=${_nfe.4} ${_if_nfe.4} MLINKS+=nge.4 if_nge.4 MLINKS+=ow.4 onewire.4 MLINKS+=pccbb.4 cbb.4 MLINKS+=pcm.4 snd.4 \ pcm.4 sound.4 MLINKS+=pms.4 pmspcv.4 MLINKS+=ptnet.4 if_ptnet.4 MLINKS+=ral.4 if_ral.4 MLINKS+=re.4 if_re.4 MLINKS+=rl.4 if_rl.4 MLINKS+=rtwn_pci.4 if_rtwn_pci.4 MLINKS+=rue.4 if_rue.4 MLINKS+=scsi.4 CAM.4 \ scsi.4 cam.4 \ scsi.4 scbus.4 \ scsi.4 SCSI.4 MLINKS+=sge.4 if_sge.4 MLINKS+=sis.4 if_sis.4 MLINKS+=sk.4 if_sk.4 MLINKS+=smp.4 SMP.4 MLINKS+=smsc.4 if_smsc.4 MLINKS+=snd_envy24.4 snd_ak452x.4 MLINKS+=snd_sbc.4 snd_sb16.4 \ snd_sbc.4 snd_sb8.4 MLINKS+=${_spkr.4} ${_speaker.4} MLINKS+=splash.4 screensaver.4 MLINKS+=ste.4 if_ste.4 MLINKS+=stf.4 if_stf.4 MLINKS+=stge.4 if_stge.4 MLINKS+=syncache.4 syncookies.4 MLINKS+=syscons.4 sc.4 MLINKS+=tap.4 if_tap.4 \ tap.4 vmnet.4 \ tap.4 if_vmnet.4 MLINKS+=tdfx.4 tdfx_linux.4 MLINKS+=ti.4 if_ti.4 MLINKS+=tun.4 if_tun.4 MLINKS+=ure.4 if_ure.4 MLINKS+=vge.4 if_vge.4 MLINKS+=vlan.4 if_vlan.4 MLINKS+=vxlan.4 if_vxlan.4 MLINKS+=${_vmx.4} ${_if_vmx.4} MLINKS+=vr.4 if_vr.4 MLINKS+=vte.4 if_vte.4 MLINKS+=${_vtnet.4} ${_if_vtnet.4} MLINKS+=watchdog.4 SW_WATCHDOG.4 MLINKS+=wi.4 if_wi.4 MLINKS+=${_wpi.4} ${_if_wpi.4} MLINKS+=xl.4 if_xl.4 .if ${MACHINE_CPUARCH} == "amd64" || ${MACHINE_CPUARCH} == "i386" _acpi_asus.4= acpi_asus.4 _acpi_asus_wmi.4= acpi_asus_wmi.4 _acpi_dock.4= acpi_dock.4 _acpi_fujitsu.4=acpi_fujitsu.4 _acpi_hp.4= acpi_hp.4 _acpi_ibm.4= acpi_ibm.4 _acpi_panasonic.4=acpi_panasonic.4 _acpi_rapidstart.4=acpi_rapidstart.4 _acpi_sony.4= acpi_sony.4 _acpi_toshiba.4=acpi_toshiba.4 _acpi_wmi.4= acpi_wmi.4 _aesni.4= aesni.4 _aout.4= aout.4 _apic.4= apic.4 _atrtc.4= atrtc.4 _attimer.4= attimer.4 _aibs.4= aibs.4 _amdsbwd.4= amdsbwd.4 _amdsmb.4= amdsmb.4 _amdsmn.4= amdsmn.4 _amdtemp.4= amdtemp.4 _asmc.4= asmc.4 _bxe.4= bxe.4 _bytgpio.4= bytgpio.4 _chvgpio.4= chvgpio.4 _coretemp.4= coretemp.4 _cpuctl.4= cpuctl.4 _dpms.4= dpms.4 _hpt27xx.4= hpt27xx.4 _hptiop.4= hptiop.4 _hptmv.4= hptmv.4 _hptnr.4= hptnr.4 _hptrr.4= hptrr.4 _hv_kvp.4= hv_kvp.4 _hv_netvsc.4= hv_netvsc.4 _hv_storvsc.4= hv_storvsc.4 _hv_utils.4= hv_utils.4 _hv_vmbus.4= hv_vmbus.4 _hv_vss.4= hv_vss.4 _hwpstate_intel.4= hwpstate_intel.4 _i8254.4= i8254.4 _ichwd.4= ichwd.4 _if_bxe.4= if_bxe.4 _if_ndis.4= if_ndis.4 _if_nfe.4= if_nfe.4 _if_urtw.4= if_urtw.4 _if_vmx.4= if_vmx.4 _if_vtnet.4= if_vtnet.4 _if_wpi.4= if_wpi.4 _imcsmb.4= imcsmb.4 _ipmi.4= ipmi.4 _io.4= io.4 _itwd.4= itwd.4 _linux.4= linux.4 _nda.4= nda.4 _ndis.4= ndis.4 _nfe.4= nfe.4 _nfsmb.4= nfsmb.4 _if_ntb.4= if_ntb.4 _ntb.4= ntb.4 _ntb_hw_amd.4= ntb_hw_amd.4 _ntb_hw_intel.4= ntb_hw_intel.4 _ntb_hw_plx.4= ntb_hw_plx.4 _ntb_transport.4=ntb_transport.4 _nvd.4= nvd.4 _nvme.4= nvme.4 _nvram.4= nvram.4 _padlock.4= padlock.4 _pchtherm.4= pchtherm.4 _rr232x.4= rr232x.4 _speaker.4= speaker.4 _spkr.4= spkr.4 _superio.4= superio.4 _tpm.4= tpm.4 _urtw.4= urtw.4 _viawd.4= viawd.4 _virtio.4= virtio.4 _virtio_balloon.4=virtio_balloon.4 _virtio_blk.4= virtio_blk.4 _virtio_console.4=virtio_console.4 _virtio_random.4= virtio_random.4 _virtio_scsi.4= virtio_scsi.4 _vmci.4= vmci.4 _vmx.4= vmx.4 _vtnet.4= vtnet.4 _wbwd.4= wbwd.4 _wpi.4= wpi.4 _xen.4= xen.4 _xnb.4= xnb.4 .endif .if ${MACHINE_CPUARCH} == "amd64" _ioat.4= ioat.4 _nvdimm.4= nvdimm.4 _qlxge.4= qlxge.4 _qlxgb.4= qlxgb.4 _qlxgbe.4= qlxgbe.4 _qlnxe.4= qlnxe.4 _sfxge.4= sfxge.4 _smartpqi.4= smartpqi.4 _vmd.4= vmd.4 MLINKS+=qlxge.4 if_qlxge.4 MLINKS+=qlxgb.4 if_qlxgb.4 MLINKS+=qlxgbe.4 if_qlxgbe.4 MLINKS+=qlnxe.4 if_qlnxe.4 MLINKS+=sfxge.4 if_sfxge.4 .if ${MK_BHYVE} != "no" _bhyve.4= bhyve.4 _vmm.4= vmm.4 .endif .endif .if ${MACHINE_CPUARCH} == "mips" _nvram2env.4= nvram2env.4 .endif .if ${MACHINE_CPUARCH} == "powerpc" _if_vtnet.4= if_vtnet.4 _nvd.4= nvd.4 _nvme.4= nvme.4 _virtio.4= virtio.4 _virtio_balloon.4=virtio_balloon.4 _virtio_blk.4= virtio_blk.4 _virtio_console.4=virtio_console.4 _virtio_random.4= virtio_random.4 _virtio_scsi.4= virtio_scsi.4 _vtnet.4= vtnet.4 .endif .if empty(MAN_ARCH) __arches= ${MACHINE} ${MACHINE_ARCH} ${MACHINE_CPUARCH} .elif ${MAN_ARCH} == "all" __arches= ${:!/bin/sh -c "/bin/ls -d ${.CURDIR}/man4.*"!:E} .else __arches= ${MAN_ARCH} .endif .for __arch in ${__arches:O:u} .if exists(${.CURDIR}/man4.${__arch}) SUBDIR+= man4.${__arch} .endif .endfor .if ${MK_BLUETOOTH} != "no" MAN+= ng_bluetooth.4 .endif .if ${MK_CCD} != "no" _ccd.4= ccd.4 .endif .if ${MK_CDDL} != "no" _dtrace_provs= dtrace_audit.4 \ dtrace_io.4 \ dtrace_ip.4 \ dtrace_lockstat.4 \ dtrace_proc.4 \ dtrace_sched.4 \ dtrace_sctp.4 \ dtrace_tcp.4 \ dtrace_udp.4 \ dtrace_udplite.4 MLINKS+= dtrace_audit.4 dtaudit.4 .endif .if ${MK_EFI} != "no" MAN+= efidev.4 MLINKS+= efidev.4 efirtc.4 .endif .if ${MK_ISCSI} != "no" MAN+= cfiscsi.4 MAN+= iscsi.4 MAN+= iscsi_initiator.4 MAN+= iser.4 .endif .if ${MK_OFED} != "no" MAN+= mlx4ib.4 MAN+= mlx5ib.4 .endif .if ${MK_MLX5TOOL} != "no" MAN+= mlx5io.4 .endif .if ${MK_TESTS} != "no" ATF= ${SRCTOP}/contrib/atf .PATH: ${ATF}/doc _atf_test_case.4= atf-test-case.4 .endif .if ${MK_PF} != "no" _pf.4= pf.4 _pflog.4= pflog.4 _pfsync.4= pfsync.4 .endif .if ${MK_USB} != "no" MAN+= \ otus.4 \ otusfw.4 \ rsu.4 \ rsufw.4 \ rtwn_usb.4 \ rum.4 \ run.4 \ runfw.4 \ u3g.4 \ uark.4 \ uart.4 \ uath.4 \ ubsa.4 \ ubser.4 \ ubtbcmfw.4 \ uchcom.4 \ ucom.4 \ ucycom.4 \ udav.4 \ udbp.4 \ udl.4 \ uep.4 \ ufm.4 \ ufoma.4 \ uftdi.4 \ ugen.4 \ ugold.4 \ uhci.4 \ uhid.4 \ uhso.4 \ uipaq.4 \ ukbd.4 \ uled.4 \ ulpt.4 \ umass.4 \ umcs.4 \ umct.4 \ umodem.4 \ umoscom.4 \ ums.4 \ unix.4 \ upgt.4 \ uplcom.4 \ ural.4 \ urio.4 \ urndis.4 \ ${_urtw.4} \ usb.4 \ usb_quirk.4 \ usb_template.4 \ usfs.4 \ uslcom.4 \ uvisor.4 \ uvscom.4 \ zyd.4 MLINKS+=otus.4 if_otus.4 MLINKS+=rsu.4 if_rsu.4 MLINKS+=rtwn_usb.4 if_rtwn_usb.4 MLINKS+=rum.4 if_rum.4 MLINKS+=run.4 if_run.4 MLINKS+=u3g.4 u3gstub.4 MLINKS+=uath.4 if_uath.4 MLINKS+=udav.4 if_udav.4 MLINKS+=upgt.4 if_upgt.4 MLINKS+=ural.4 if_ural.4 MLINKS+=urndis.4 if_urndis.4 MLINKS+=${_urtw.4} ${_if_urtw.4} MLINKS+=zyd.4 if_zyd.4 .endif .include Index: head/share/man/man4/safexcel.4 =================================================================== --- head/share/man/man4/safexcel.4 (nonexistent) +++ head/share/man/man4/safexcel.4 (revision 363180) @@ -0,0 +1,84 @@ +.\"- +.\" Copyright (c) 2020 Rubicon Communications, LLC (Netgate) +.\" +.\" Redistribution and use in source and binary forms, with or without +.\" modification, are permitted provided that the following conditions +.\" are met: +.\" 1. Redistributions of source code must retain the above copyright +.\" notice, this list of conditions and the following disclaimer. +.\" 2. Redistributions in binary form must reproduce the above copyright +.\" notice, this list of conditions and the following disclaimer in the +.\" documentation and/or other materials provided with the distribution. +.\" +.\" THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND +.\" ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +.\" IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +.\" ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE +.\" FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +.\" DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS +.\" OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) +.\" HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +.\" LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY +.\" OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF +.\" SUCH DAMAGE. +.\" +.\" $FreeBSD$ +.\" +.Dd June 23, 2020 +.Dt SAFEXCEL 4 +.Os +.Sh NAME +.Nm safexcel +.Nd Inside Secure SafeXcel-IP-97 security packet engine +.Sh SYNOPSIS +To compile this driver into the kernel, +place the following lines in your +kernel configuration file: +.Bd -ragged -offset indent +.Cd "device crypto" +.Cd "device cryptodev" +.Cd "device safexcel" +.Ed +.Pp +Alternatively, to load the driver as a +module at boot time, place the following line in +.Xr loader.conf 5 : +.Bd -literal -offset indent +safexcel_load="YES" +.Ed +.Sh DESCRIPTION +The +.Nm +driver implements +.Xr crypto 4 +support for the cryptographic acceleration functions of the EIP-97 device +found on some Marvell systems-on-chip. +The driver can accelerate the following AES modes: +.Pp +.Bl -bullet -compact +.It +AES-CBC +.It +AES-CTR +.It +AES-XTS +.It +AES-GCM +.It +AES-CCM +.El +.Pp +.Nm +also implements SHA1 and SHA2 transforms, and can combine AES-CBC and AES-CTR +with SHA1-HMAC and SHA2-HMAC for encrypt-then-authenticate operations. +.Sh SEE ALSO +.Xr crypto 4 , +.Xr ipsec 4 , +.Xr random 4 , +.Xr geli 8 , +.Xr crypto 9 +.Sh HISTORY +The +.Nm +driver first appeared in +.Fx 13.0 . Property changes on: head/share/man/man4/safexcel.4 ___________________________________________________________________ Added: svn:keywords ## -0,0 +1 ## +FreeBSD=%H \ No newline at end of property Index: head/sys/arm64/conf/GENERIC =================================================================== --- head/sys/arm64/conf/GENERIC (revision 363179) +++ head/sys/arm64/conf/GENERIC (revision 363180) @@ -1,359 +1,362 @@ # # GENERIC -- Generic kernel configuration file for FreeBSD/arm64 # # For more information on this file, please read the config(5) manual page, # and/or the handbook section on Kernel Configuration Files: # # https://www.FreeBSD.org/doc/en_US.ISO8859-1/books/handbook/kernelconfig-config.html # # The handbook is also available locally in /usr/share/doc/handbook # if you've installed the doc distribution, otherwise always see the # FreeBSD World Wide Web server (https://www.FreeBSD.org/) for the # latest information. # # An exhaustive list of options and more detailed explanations of the # device lines is also present in the ../../conf/NOTES and NOTES files. # If you are in doubt as to the purpose or necessity of a line, check first # in NOTES. # # $FreeBSD$ cpu ARM64 ident GENERIC makeoptions DEBUG=-g # Build kernel with gdb(1) debug symbols makeoptions WITH_CTF=1 # Run ctfconvert(1) for DTrace support options SCHED_ULE # ULE scheduler options NUMA # Non-Uniform Memory Architecture support options PREEMPTION # Enable kernel thread preemption options VIMAGE # Subsystem virtualization, e.g. VNET options INET # InterNETworking options INET6 # IPv6 communications protocols options IPSEC_SUPPORT # Allow kldload of ipsec and tcpmd5 options TCP_HHOOK # hhook(9) framework for TCP options TCP_OFFLOAD # TCP offload options TCP_RFC7413 # TCP Fast Open options SCTP # Stream Control Transmission Protocol options FFS # Berkeley Fast Filesystem options SOFTUPDATES # Enable FFS soft updates support options UFS_ACL # Support for access control lists options UFS_DIRHASH # Improve performance on big directories options UFS_GJOURNAL # Enable gjournal-based UFS journaling options QUOTA # Enable disk quotas for UFS options MD_ROOT # MD is a potential root device options NFSCL # Network Filesystem Client options NFSD # Network Filesystem Server options NFSLOCKD # Network Lock Manager options NFS_ROOT # NFS usable as /, requires NFSCL options MSDOSFS # MSDOS Filesystem options CD9660 # ISO 9660 Filesystem options PROCFS # Process filesystem (requires PSEUDOFS) options PSEUDOFS # Pseudo-filesystem framework options GEOM_RAID # Soft RAID functionality. options GEOM_LABEL # Provides labelization options COMPAT_FREEBSD32 # Compatible with FreeBSD/arm options COMPAT_FREEBSD11 # Compatible with FreeBSD11 options COMPAT_FREEBSD12 # Compatible with FreeBSD12 options SCSI_DELAY=5000 # Delay (in ms) before probing SCSI options KTRACE # ktrace(1) support options STACK # stack(9) support options SYSVSHM # SYSV-style shared memory options SYSVMSG # SYSV-style message queues options SYSVSEM # SYSV-style semaphores options _KPOSIX_PRIORITY_SCHEDULING # POSIX P1003_1B real-time extensions options PRINTF_BUFR_SIZE=128 # Prevent printf output being interspersed. options KBD_INSTALL_CDEV # install a CDEV entry in /dev options HWPMC_HOOKS # Necessary kernel hooks for hwpmc(4) options AUDIT # Security event auditing options CAPABILITY_MODE # Capsicum capability mode options CAPABILITIES # Capsicum capabilities options MAC # TrustedBSD MAC Framework options KDTRACE_FRAME # Ensure frames are compiled in options KDTRACE_HOOKS # Kernel DTrace hooks options VFP # Floating-point support options RACCT # Resource accounting framework options RACCT_DEFAULT_TO_DISABLED # Set kern.racct.enable=0 by default options RCTL # Resource limits options SMP options INTRNG # Debugging support. Always need this: options KDB # Enable kernel debugger support. options KDB_TRACE # Print a stack trace for a panic. # For full debugger support use (turn off in stable branch): options DDB # Support DDB. #options GDB # Support remote GDB. options DEADLKRES # Enable the deadlock resolver options INVARIANTS # Enable calls of extra sanity checking options INVARIANT_SUPPORT # Extra sanity checks of internal structures, required by INVARIANTS options WITNESS # Enable checks to detect deadlocks and cycles options WITNESS_SKIPSPIN # Don't run witness on spinlocks for speed options MALLOC_DEBUG_MAXZONES=8 # Separate malloc(9) zones options ALT_BREAK_TO_DEBUGGER # Enter debugger on keyboard escape sequence options USB_DEBUG # enable debug msgs options VERBOSE_SYSINIT=0 # Support debug.verbose_sysinit, off by default # Kernel Sanitizers #options COVERAGE # Generic kernel coverage. Used by KCOV #options KCOV # Kernel Coverage Sanitizer # Warning: KUBSAN can result in a kernel too large for loader to load #options KUBSAN # Kernel Undefined Behavior Sanitizer #options KCSAN # Kernel Concurrency Sanitizer # Kernel dump features. options EKCD # Support for encrypted kernel dumps options GZIO # gzip-compressed kernel and user dumps options ZSTDIO # zstd-compressed kernel and user dumps options DEBUGNET # debugnet networking options NETDUMP # netdump(4) client support # SoC support options SOC_ALLWINNER_A64 options SOC_ALLWINNER_H5 options SOC_ALLWINNER_H6 options SOC_CAVM_THUNDERX options SOC_FREESCALE_IMX8 options SOC_HISI_HI6220 options SOC_INTEL_STRATIX10 options SOC_BRCM_BCM2837 options SOC_BRCM_BCM2838 options SOC_MARVELL_8K options SOC_NXP_LS options SOC_ROCKCHIP_RK3328 options SOC_ROCKCHIP_RK3399 options SOC_XILINX_ZYNQ # Timer drivers device a10_timer # Annapurna Alpine drivers device al_ccu # Alpine Cache Coherency Unit device al_nb_service # Alpine North Bridge Service device al_iofic # I/O Fabric Interrupt Controller device al_serdes # Serializer/Deserializer device al_udma # Universal DMA # Qualcomm Snapdragon drivers device qcom_gcc # Global Clock Controller # VirtIO support device virtio device virtio_pci device virtio_mmio device virtio_blk device vtnet # CPU frequency control device cpufreq # Bus drivers device pci device pci_n1sdp # ARM Neoverse N1 SDP PCI device al_pci # Annapurna Alpine PCI-E options PCI_HP # PCI-Express native HotPlug options PCI_IOV # PCI SR-IOV support # PCI/PCI-X/PCIe Ethernet NICs that use iflib infrastructure device iflib device em # Intel PRO/1000 Gigabit Ethernet Family device ix # Intel 10Gb Ethernet Family # Ethernet NICs device mdio device mii device miibus # MII bus support device awg # Allwinner EMAC Gigabit Ethernet device axgbe # AMD Opteron A1100 integrated NIC device msk # Marvell/SysKonnect Yukon II Gigabit Ethernet device neta # Marvell Armada 370/38x/XP/3700 NIC device smc # SMSC LAN91C111 device vnic # Cavium ThunderX NIC device al_eth # Annapurna Alpine Ethernet NIC device dwc_rk # Rockchip Designware device dwc_socfpga # Altera SOCFPGA Ethernet MAC device genet # Broadcom on RPi4 device ffec # iMX FFEC # Etherswitch devices device etherswitch # Enable etherswitch support device miiproxy # Required for etherswitch device e6000sw # Marvell mv88e6085 based switches # Block devices device ahci device scbus device da # ATA/SCSI peripherals device pass # Passthrough device (direct ATA/SCSI access) # NVM Express (NVMe) support device nvme # base NVMe driver options NVME_USE_NVD=0 # prefer the cam(4) based nda(4) driver device nvd # expose NVMe namespaces as disks, depends on nvme # MMC/SD/SDIO Card slot support device sdhci device sdhci_xenon # Marvell Xenon SD/MMC controller device aw_mmc # Allwinner SD/MMC controller device mmc # mmc/sd bus device mmcsd # mmc/sd flash cards device dwmmc device dwmmc_altera device dwmmc_hisi device rk_dwmmc device rk_emmcphy # Serial (COM) ports device uart # Generic UART driver device uart_imx # iMX8 UART device uart_msm # Qualcomm MSM UART driver device uart_mu # RPI3 aux port device uart_mvebu # Armada 3700 UART driver device uart_ns8250 # ns8250-type UART driver device uart_snps device pl011 # USB support device aw_usbphy # Allwinner USB PHY device rk_usb2phy # Rockchip USB2PHY device rk_typec_phy # Rockchip TypeC PHY device dwcotg # DWC OTG controller device ohci # OHCI USB interface device ehci # EHCI USB interface (USB 2.0) device ehci_mv # Marvell EHCI USB interface device xhci # XHCI USB interface (USB 3.0) device dwc3 # Synopsys DWC controller device aw_dwc3 # Allwinner DWC3 controller device rk_dwc3 # Rockchip DWC3 controller device usb # USB Bus (required) device ukbd # Keyboard device umass # Disks/Mass storage - Requires scbus and da # USB ethernet support device muge device smcphy device smsc # Sound support device sound device a10_codec # DMA controller device a31_dmac # GPIO / PINCTRL device a37x0_gpio # Marvell Armada 37x0 GPIO controller device aw_gpio # Allwinner GPIO controller device dwgpio # Synopsys DesignWare APB GPIO Controller device gpio device gpioled device fdt_pinctrl device gpioregulator device ls1046_gpio # LS1046A GPIO controller device mv_gpio # Marvell GPIO controller device mvebu_pinctrl # Marvell Pinmux Controller device rk_gpio # RockChip GPIO Controller device rk_pinctrl # RockChip Pinmux Controller # I2C device a37x0_iic # Armada 37x0 I2C controller device aw_rsb # Allwinner Reduced Serial Bus device bcm2835_bsc # Broadcom BCM283x I2C bus device iicbus device iic device twsi # Allwinner I2C controller device rk_i2c # RockChip I2C controller device syr827 # Silergy SYR827 PMIC device sy8106a # SY8106A Buck Regulator device vf_i2c # Freescale Vybrid I2C controller device fsliic # Freescale iMX I2C controller # Clock and reset controllers device aw_ccu # Allwinner clock controller # Interrupt controllers device aw_nmi # Allwinner NMI support device mv_cp110_icu # Marvell CP110 ICU device mv_ap806_gicp # Marvell AP806 GICP device mv_ap806_sei # Marvell AP806 SEI # Real-time clock support device aw_rtc # Allwinner Real-time Clock device mv_rtc # Marvell Real-time Clock +# Crypto accelerators +device safexcel # Inside Secure EIP-97 + # Watchdog controllers device aw_wdog # Allwinner Watchdog # Power management controllers device axp81x # X-Powers AXP81x PMIC device rk805 # RockChip RK805 PMIC # EFUSE device aw_sid # Allwinner Secure ID EFUSE # Thermal sensors device aw_thermal # Allwinner Thermal Sensor Controller device mv_thermal # Marvell Thermal Sensor Controller # SPI device spibus device a37x0_spi # Marvell Armada 37x0 SPI Controller device bcm2835_spi # Broadcom BCM283x SPI bus device rk_spi # RockChip SPI controller # PWM device pwm device aw_pwm device rk_pwm # Console device vt device kbdmux device vt_efifb # EVDEV support device evdev # input event device support options EVDEV_SUPPORT # evdev support in legacy drivers device uinput # install /dev/uinput cdev device aw_cir # Pseudo devices. device crypto # core crypto support device loop # Network loopback device ether # Ethernet support device vlan # 802.1Q VLAN support device tuntap # Packet tunnel. device md # Memory "disks" device gif # IPv6 and IPv4 tunneling device firmware # firmware assist module options EFIRT # EFI Runtime Services # EXT_RESOURCES pseudo devices options EXT_RESOURCES device clk device phy device hwreset device nvmem device regulator device syscon device aw_syscon # IO Domains device rk_iodomain # The `bpf' device enables the Berkeley Packet Filter. # Be aware of the administrative consequences of enabling this! # Note that 'bpf' is required for DHCP. device bpf # Berkeley packet filter # Chip-specific errata options THUNDERX_PASS_1_1_ERRATA options FDT device acpi # DTBs makeoptions MODULES_EXTRA="dtb/allwinner dtb/imx8 dtb/mv dtb/rockchip dtb/rpi" Index: head/sys/conf/files.arm64 =================================================================== --- head/sys/conf/files.arm64 (revision 363179) +++ head/sys/conf/files.arm64 (revision 363180) @@ -1,414 +1,415 @@ # $FreeBSD$ cloudabi32_vdso.o optional compat_cloudabi32 \ dependency "$S/contrib/cloudabi/cloudabi_vdso_armv6_on_64bit.S" \ compile-with "${CC} -x assembler-with-cpp -m32 -shared -nostdinc -nostdlib -Wl,-T$S/compat/cloudabi/cloudabi_vdso.lds $S/contrib/cloudabi/cloudabi_vdso_armv6_on_64bit.S -o ${.TARGET}" \ no-obj no-implicit-rule \ clean "cloudabi32_vdso.o" # cloudabi32_vdso_blob.o optional compat_cloudabi32 \ dependency "cloudabi32_vdso.o" \ compile-with "${OBJCOPY} --input-target binary --output-target elf64-littleaarch64 --binary-architecture aarch64 cloudabi32_vdso.o ${.TARGET}" \ no-implicit-rule \ clean "cloudabi32_vdso_blob.o" # cloudabi64_vdso.o optional compat_cloudabi64 \ dependency "$S/contrib/cloudabi/cloudabi_vdso_aarch64.S" \ compile-with "${CC} -x assembler-with-cpp -shared -nostdinc -nostdlib -Wl,-T$S/compat/cloudabi/cloudabi_vdso.lds $S/contrib/cloudabi/cloudabi_vdso_aarch64.S -o ${.TARGET}" \ no-obj no-implicit-rule \ clean "cloudabi64_vdso.o" # cloudabi64_vdso_blob.o optional compat_cloudabi64 \ dependency "cloudabi64_vdso.o" \ compile-with "${OBJCOPY} --input-target binary --output-target elf64-littleaarch64 --binary-architecture aarch64 cloudabi64_vdso.o ${.TARGET}" \ no-implicit-rule \ clean "cloudabi64_vdso_blob.o" # # Allwinner common files arm/allwinner/a10_timer.c optional a10_timer fdt arm/allwinner/a10_codec.c optional sound a10_codec arm/allwinner/a31_dmac.c optional a31_dmac arm/allwinner/sunxi_dma_if.m optional a31_dmac arm/allwinner/aw_cir.c optional evdev aw_cir fdt arm/allwinner/aw_dwc3.c optional aw_dwc3 fdt arm/allwinner/aw_gpio.c optional gpio aw_gpio fdt arm/allwinner/aw_mmc.c optional mmc aw_mmc fdt | mmccam aw_mmc fdt arm/allwinner/aw_nmi.c optional aw_nmi fdt \ compile-with "${NORMAL_C} -I$S/gnu/dts/include" arm/allwinner/aw_pwm.c optional aw_pwm fdt arm/allwinner/aw_rsb.c optional aw_rsb fdt arm/allwinner/aw_rtc.c optional aw_rtc fdt arm/allwinner/aw_sid.c optional aw_sid nvmem fdt arm/allwinner/aw_spi.c optional aw_spi fdt arm/allwinner/aw_syscon.c optional aw_syscon ext_resources syscon fdt arm/allwinner/aw_thermal.c optional aw_thermal nvmem fdt arm/allwinner/aw_usbphy.c optional ehci aw_usbphy fdt arm/allwinner/aw_usb3phy.c optional xhci aw_usbphy fdt arm/allwinner/aw_wdog.c optional aw_wdog fdt arm/allwinner/axp81x.c optional axp81x fdt arm/allwinner/if_awg.c optional awg ext_resources syscon aw_sid nvmem fdt # Allwinner clock driver arm/allwinner/clkng/aw_ccung.c optional aw_ccu fdt arm/allwinner/clkng/aw_clk_frac.c optional aw_ccu fdt arm/allwinner/clkng/aw_clk_m.c optional aw_ccu fdt arm/allwinner/clkng/aw_clk_mipi.c optional aw_ccu fdt arm/allwinner/clkng/aw_clk_nkmp.c optional aw_ccu fdt arm/allwinner/clkng/aw_clk_nm.c optional aw_ccu fdt arm/allwinner/clkng/aw_clk_nmm.c optional aw_ccu fdt arm/allwinner/clkng/aw_clk_np.c optional aw_ccu fdt arm/allwinner/clkng/aw_clk_prediv_mux.c optional aw_ccu fdt arm/allwinner/clkng/ccu_a64.c optional soc_allwinner_a64 aw_ccu fdt arm/allwinner/clkng/ccu_h3.c optional soc_allwinner_h5 aw_ccu fdt arm/allwinner/clkng/ccu_h6.c optional soc_allwinner_h6 aw_ccu fdt arm/allwinner/clkng/ccu_h6_r.c optional soc_allwinner_h6 aw_ccu fdt arm/allwinner/clkng/ccu_sun8i_r.c optional aw_ccu fdt arm/allwinner/clkng/ccu_de2.c optional aw_ccu fdt # Allwinner padconf files arm/allwinner/a64/a64_padconf.c optional soc_allwinner_a64 fdt arm/allwinner/a64/a64_r_padconf.c optional soc_allwinner_a64 fdt arm/allwinner/h3/h3_padconf.c optional soc_allwinner_h5 fdt arm/allwinner/h3/h3_r_padconf.c optional soc_allwinner_h5 fdt arm/allwinner/h6/h6_padconf.c optional soc_allwinner_h6 fdt arm/allwinner/h6/h6_r_padconf.c optional soc_allwinner_h6 fdt arm/annapurna/alpine/alpine_ccu.c optional al_ccu fdt arm/annapurna/alpine/alpine_nb_service.c optional al_nb_service fdt arm/annapurna/alpine/alpine_pci.c optional al_pci fdt arm/annapurna/alpine/alpine_pci_msix.c optional al_pci fdt arm/annapurna/alpine/alpine_serdes.c optional al_serdes fdt \ no-depend \ compile-with "${CC} -c -o ${.TARGET} ${CFLAGS} -I$S/contrib/alpine-hal -I$S/contrib/alpine-hal/eth ${PROF} ${.IMPSRC}" arm/arm/generic_timer.c standard arm/arm/gic.c standard arm/arm/gic_acpi.c optional acpi arm/arm/gic_fdt.c optional fdt arm/arm/pmu.c standard arm/broadcom/bcm2835/bcm2835_audio.c optional sound vchiq fdt \ compile-with "${NORMAL_C} -DUSE_VCHIQ_ARM -D__VCCOREVER__=0x04000000 -I$S/contrib/vchiq" arm/broadcom/bcm2835/bcm2835_bsc.c optional bcm2835_bsc fdt arm/broadcom/bcm2835/bcm2835_clkman.c optional soc_brcm_bcm2837 fdt | soc_brcm_bcm2838 fdt arm/broadcom/bcm2835/bcm2835_cpufreq.c optional soc_brcm_bcm2837 fdt | soc_brcm_bcm2838 fdt arm/broadcom/bcm2835/bcm2835_dma.c optional soc_brcm_bcm2837 fdt | soc_brcm_bcm2838 fdt arm/broadcom/bcm2835/bcm2835_fbd.c optional vt soc_brcm_bcm2837 fdt | vt soc_brcm_bcm2838 fdt arm/broadcom/bcm2835/bcm2835_firmware.c optional soc_brcm_bcm2837 fdt | soc_brcm_bcm2838 fdt arm/broadcom/bcm2835/bcm2835_ft5406.c optional evdev bcm2835_ft5406 fdt arm/broadcom/bcm2835/bcm2835_gpio.c optional gpio soc_brcm_bcm2837 fdt | gpio soc_brcm_bcm2838 fdt arm/broadcom/bcm2835/bcm2835_intr.c optional soc_brcm_bcm2837 fdt | soc_brcm_bcm2838 fdt arm/broadcom/bcm2835/bcm2835_mbox.c optional soc_brcm_bcm2837 fdt | soc_brcm_bcm2838 fdt arm/broadcom/bcm2835/bcm2835_rng.c optional !random_loadable soc_brcm_bcm2837 fdt | !random_loadable soc_brcm_bcm2838 fdt arm/broadcom/bcm2835/bcm2835_sdhci.c optional sdhci soc_brcm_bcm2837 fdt | sdhci soc_brcm_bcm2838 fdt arm/broadcom/bcm2835/bcm2835_sdhost.c optional sdhci soc_brcm_bcm2837 fdt | sdhci soc_brcm_bcm2838 fdt arm/broadcom/bcm2835/bcm2835_spi.c optional bcm2835_spi fdt arm/broadcom/bcm2835/bcm2835_vcbus.c optional soc_brcm_bcm2837 fdt | soc_brcm_bcm2838 fdt arm/broadcom/bcm2835/bcm2835_vcio.c optional soc_brcm_bcm2837 fdt | soc_brcm_bcm2838 fdt arm/broadcom/bcm2835/bcm2835_wdog.c optional soc_brcm_bcm2837 fdt | soc_brcm_bcm2838 fdt arm/broadcom/bcm2835/bcm2836.c optional soc_brcm_bcm2837 fdt | soc_brcm_bcm2838 fdt arm/broadcom/bcm2835/bcm283x_dwc_fdt.c optional dwcotg fdt soc_brcm_bcm2837 | dwcotg fdt soc_brcm_bcm2838 arm/broadcom/bcm2835/bcm2838_pci.c optional soc_brcm_bcm2838 fdt pci arm/freescale/vybrid/vf_i2c.c optional vf_i2c iicbus SOC_NXP_LS arm/mv/a37x0_gpio.c optional a37x0_gpio gpio fdt arm/mv/a37x0_iic.c optional a37x0_iic iicbus fdt arm/mv/a37x0_spi.c optional a37x0_spi spibus fdt arm/mv/armada38x/armada38x_rtc.c optional mv_rtc fdt arm/mv/gpio.c optional mv_gpio fdt arm/mv/mvebu_gpio.c optional mv_gpio fdt arm/mv/mvebu_pinctrl.c optional mvebu_pinctrl fdt arm/mv/mv_ap806_clock.c optional SOC_MARVELL_8K fdt arm/mv/mv_ap806_gicp.c optional mv_ap806_gicp fdt arm/mv/mv_ap806_sei.c optional mv_ap806_sei fdt arm/mv/mv_cp110_clock.c optional SOC_MARVELL_8K fdt arm/mv/mv_cp110_icu.c optional mv_cp110_icu fdt arm/mv/mv_cp110_icu_bus.c optional mv_cp110_icu fdt arm/mv/mv_thermal.c optional SOC_MARVELL_8K mv_thermal fdt arm/mv/armada38x/armada38x_rtc.c optional mv_rtc fdt arm/xilinx/uart_dev_cdnc.c optional uart soc_xilinx_zynq arm64/acpica/acpi_iort.c optional acpi arm64/acpica/acpi_machdep.c optional acpi arm64/acpica/OsdEnvironment.c optional acpi arm64/acpica/acpi_wakeup.c optional acpi arm64/acpica/pci_cfgreg.c optional acpi pci arm64/arm64/autoconf.c standard arm64/arm64/bus_machdep.c standard arm64/arm64/bus_space_asm.S standard arm64/arm64/busdma_bounce.c standard arm64/arm64/busdma_machdep.c standard arm64/arm64/bzero.S standard arm64/arm64/clock.c standard arm64/arm64/copyinout.S standard arm64/arm64/cpu_errata.c standard arm64/arm64/cpufunc_asm.S standard arm64/arm64/db_disasm.c optional ddb arm64/arm64/db_interface.c optional ddb arm64/arm64/db_trace.c optional ddb arm64/arm64/debug_monitor.c standard arm64/arm64/disassem.c optional ddb arm64/arm64/dump_machdep.c standard arm64/arm64/efirt_machdep.c optional efirt arm64/arm64/elf32_machdep.c optional compat_freebsd32 arm64/arm64/elf_machdep.c standard arm64/arm64/exception.S standard arm64/arm64/freebsd32_machdep.c optional compat_freebsd32 arm64/arm64/gicv3_its.c optional intrng fdt arm64/arm64/gic_v3.c standard arm64/arm64/gic_v3_acpi.c optional acpi arm64/arm64/gic_v3_fdt.c optional fdt arm64/arm64/identcpu.c standard arm64/arm64/in_cksum.c optional inet | inet6 arm64/arm64/locore.S standard no-obj arm64/arm64/machdep.c standard arm64/arm64/machdep_boot.c standard arm64/arm64/mem.c standard arm64/arm64/memcpy.S standard arm64/arm64/memmove.S standard arm64/arm64/minidump_machdep.c standard arm64/arm64/mp_machdep.c optional smp arm64/arm64/nexus.c standard arm64/arm64/ofw_machdep.c optional fdt arm64/arm64/pmap.c standard arm64/arm64/stack_machdep.c optional ddb | stack arm64/arm64/support.S standard arm64/arm64/swtch.S standard arm64/arm64/sys_machdep.c standard arm64/arm64/trap.c standard arm64/arm64/uio_machdep.c standard arm64/arm64/uma_machdep.c standard arm64/arm64/undefined.c standard arm64/arm64/unwind.c optional ddb | kdtrace_hooks | stack arm64/arm64/vfp.c standard arm64/arm64/vm_machdep.c standard arm64/broadcom/brcmmdio/mdio_mux_iproc.c optional fdt arm64/broadcom/brcmmdio/mdio_nexus_iproc.c optional fdt arm64/broadcom/brcmmdio/mdio_ns2_pcie_phy.c optional fdt pci arm64/broadcom/genet/if_genet.c optional SOC_BRCM_BCM2838 fdt genet arm64/cavium/thunder_pcie_fdt.c optional soc_cavm_thunderx pci fdt arm64/cavium/thunder_pcie_pem.c optional soc_cavm_thunderx pci arm64/cavium/thunder_pcie_pem_fdt.c optional soc_cavm_thunderx pci fdt arm64/cavium/thunder_pcie_common.c optional soc_cavm_thunderx pci arm64/cloudabi32/cloudabi32_sysvec.c optional compat_cloudabi32 arm64/cloudabi64/cloudabi64_sysvec.c optional compat_cloudabi64 arm64/coresight/coresight.c standard arm64/coresight/coresight_acpi.c optional acpi arm64/coresight/coresight_fdt.c optional fdt arm64/coresight/coresight_if.m standard arm64/coresight/coresight_cmd.c standard arm64/coresight/coresight_cpu_debug.c standard arm64/coresight/coresight_etm4x.c standard arm64/coresight/coresight_etm4x_acpi.c optional acpi arm64/coresight/coresight_etm4x_fdt.c optional fdt arm64/coresight/coresight_funnel.c standard arm64/coresight/coresight_funnel_acpi.c optional acpi arm64/coresight/coresight_funnel_fdt.c optional fdt arm64/coresight/coresight_replicator.c standard arm64/coresight/coresight_replicator_acpi.c optional acpi arm64/coresight/coresight_replicator_fdt.c optional fdt arm64/coresight/coresight_tmc.c standard arm64/coresight/coresight_tmc_acpi.c optional acpi arm64/coresight/coresight_tmc_fdt.c optional fdt arm64/intel/firmware.c optional soc_intel_stratix10 arm64/intel/stratix10-soc-fpga-mgr.c optional soc_intel_stratix10 arm64/intel/stratix10-svc.c optional soc_intel_stratix10 arm64/qoriq/ls1046_gpio.c optional ls1046_gpio gpio fdt SOC_NXP_LS arm64/qoriq/clk/ls1046a_clkgen.c optional clk SOC_NXP_LS arm64/qoriq/clk/qoriq_clk_pll.c optional clk SOC_NXP_LS arm64/qoriq/clk/qoriq_clkgen.c optional clk SOC_NXP_LS arm64/qualcomm/qcom_gcc.c optional qcom_gcc fdt contrib/vchiq/interface/compat/vchi_bsd.c optional vchiq soc_brcm_bcm2837 \ compile-with "${NORMAL_C} -DUSE_VCHIQ_ARM -D__VCCOREVER__=0x04000000 -I$S/contrib/vchiq" contrib/vchiq/interface/vchiq_arm/vchiq_2835_arm.c optional vchiq soc_brcm_bcm2837 \ compile-with "${NORMAL_C} -Wno-unused -DUSE_VCHIQ_ARM -D__VCCOREVER__=0x04000000 -I$S/contrib/vchiq" contrib/vchiq/interface/vchiq_arm/vchiq_arm.c optional vchiq soc_brcm_bcm2837 \ compile-with "${NORMAL_C} -Wno-unused -DUSE_VCHIQ_ARM -D__VCCOREVER__=0x04000000 -I$S/contrib/vchiq" contrib/vchiq/interface/vchiq_arm/vchiq_connected.c optional vchiq soc_brcm_bcm2837 \ compile-with "${NORMAL_C} -DUSE_VCHIQ_ARM -D__VCCOREVER__=0x04000000 -I$S/contrib/vchiq" contrib/vchiq/interface/vchiq_arm/vchiq_core.c optional vchiq soc_brcm_bcm2837 \ compile-with "${NORMAL_C} -DUSE_VCHIQ_ARM -D__VCCOREVER__=0x04000000 -I$S/contrib/vchiq" contrib/vchiq/interface/vchiq_arm/vchiq_kern_lib.c optional vchiq soc_brcm_bcm2837 \ compile-with "${NORMAL_C} -DUSE_VCHIQ_ARM -D__VCCOREVER__=0x04000000 -I$S/contrib/vchiq" contrib/vchiq/interface/vchiq_arm/vchiq_kmod.c optional vchiq soc_brcm_bcm2837 \ compile-with "${NORMAL_C} -DUSE_VCHIQ_ARM -D__VCCOREVER__=0x04000000 -I$S/contrib/vchiq" contrib/vchiq/interface/vchiq_arm/vchiq_shim.c optional vchiq soc_brcm_bcm2837 \ compile-with "${NORMAL_C} -DUSE_VCHIQ_ARM -D__VCCOREVER__=0x04000000 -I$S/contrib/vchiq" contrib/vchiq/interface/vchiq_arm/vchiq_util.c optional vchiq soc_brcm_bcm2837 \ compile-with "${NORMAL_C} -DUSE_VCHIQ_ARM -D__VCCOREVER__=0x04000000 -I$S/contrib/vchiq" crypto/armv8/armv8_crypto.c optional armv8crypto armv8_crypto_wrap.o optional armv8crypto \ dependency "$S/crypto/armv8/armv8_crypto_wrap.c" \ compile-with "${CC} -c ${CFLAGS:C/^-O2$/-O3/:N-nostdinc:N-mgeneral-regs-only} -I$S/crypto/armv8/ ${WERROR} ${NO_WCAST_QUAL} ${PROF} -march=armv8-a+crypto ${.IMPSRC}" \ no-implicit-rule \ clean "armv8_crypto_wrap.o" crypto/des/des_enc.c optional netsmb dev/acpica/acpi_bus_if.m optional acpi dev/acpica/acpi_if.m optional acpi dev/acpica/acpi_pci_link.c optional acpi pci dev/acpica/acpi_pcib.c optional acpi pci dev/acpica/acpi_pxm.c optional acpi dev/ahci/ahci_fsl_fdt.c optional SOC_NXP_LS ahci fdt dev/ahci/ahci_generic.c optional ahci dev/altera/dwc/if_dwc_socfpga.c optional fdt dwc_socfpga dev/axgbe/if_axgbe.c optional axgbe dev/axgbe/xgbe-desc.c optional axgbe dev/axgbe/xgbe-dev.c optional axgbe dev/axgbe/xgbe-drv.c optional axgbe dev/axgbe/xgbe-mdio.c optional axgbe dev/cpufreq/cpufreq_dt.c optional cpufreq fdt dev/ice/if_ice_iflib.c optional ice pci \ compile-with "${NORMAL_C} -I$S/dev/ice" dev/ice/ice_lib.c optional ice pci \ compile-with "${NORMAL_C} -I$S/dev/ice" dev/ice/ice_osdep.c optional ice pci \ compile-with "${NORMAL_C} -I$S/dev/ice" dev/ice/ice_resmgr.c optional ice pci \ compile-with "${NORMAL_C} -I$S/dev/ice" dev/ice/ice_strings.c optional ice pci \ compile-with "${NORMAL_C} -I$S/dev/ice" dev/ice/ice_iflib_recovery_txrx.c optional ice pci \ compile-with "${NORMAL_C} -I$S/dev/ice" dev/ice/ice_iflib_txrx.c optional ice pci \ compile-with "${NORMAL_C} -I$S/dev/ice" dev/ice/ice_common.c optional ice pci \ compile-with "${NORMAL_C} -I$S/dev/ice" dev/ice/ice_controlq.c optional ice pci \ compile-with "${NORMAL_C} -I$S/dev/ice" dev/ice/ice_dcb.c optional ice pci \ compile-with "${NORMAL_C} -I$S/dev/ice" dev/ice/ice_flex_pipe.c optional ice pci \ compile-with "${NORMAL_C} -I$S/dev/ice" dev/ice/ice_flow.c optional ice pci \ compile-with "${NORMAL_C} -I$S/dev/ice" dev/ice/ice_nvm.c optional ice pci \ compile-with "${NORMAL_C} -I$S/dev/ice" dev/ice/ice_sched.c optional ice pci \ compile-with "${NORMAL_C} -I$S/dev/ice" dev/ice/ice_sriov.c optional ice pci \ compile-with "${NORMAL_C} -I$S/dev/ice" dev/ice/ice_switch.c optional ice pci \ compile-with "${NORMAL_C} -I$S/dev/ice" ice_ddp.c optional ice_ddp \ compile-with "${AWK} -f $S/tools/fw_stub.awk ice_ddp.fw:ice_ddp:0x01030900 -mice_ddp -c${.TARGET}" \ no-implicit-rule before-depend local \ clean "ice_ddp.c" ice_ddp.fwo optional ice_ddp \ dependency "ice_ddp.fw" \ compile-with "${NORMAL_FWO}" \ no-implicit-rule \ clean "ice_ddp.fwo" ice_ddp.fw optional ice_ddp \ dependency "$S/contrib/dev/ice/ice-1.3.9.0.pkg" \ compile-with "${CP} $S/contrib/dev/ice/ice-1.3.9.0.pkg ice_ddp.fw" \ no-obj no-implicit-rule \ clean "ice_ddp.fw" dev/iicbus/sy8106a.c optional sy8106a fdt dev/iicbus/twsi/mv_twsi.c optional twsi fdt dev/iicbus/twsi/a10_twsi.c optional twsi fdt dev/iicbus/twsi/twsi.c optional twsi fdt dev/hwpmc/hwpmc_arm64.c optional hwpmc dev/hwpmc/hwpmc_arm64_md.c optional hwpmc dev/mbox/mbox_if.m optional soc_brcm_bcm2837 dev/mmc/host/dwmmc.c optional dwmmc fdt dev/mmc/host/dwmmc_altera.c optional dwmmc dwmmc_altera fdt dev/mmc/host/dwmmc_hisi.c optional dwmmc dwmmc_hisi fdt dev/mmc/host/dwmmc_rockchip.c optional dwmmc rk_dwmmc fdt dev/neta/if_mvneta_fdt.c optional neta fdt dev/neta/if_mvneta.c optional neta mdio mii dev/ofw/ofw_cpu.c optional fdt dev/ofw/ofwpci.c optional fdt pci dev/pci/controller/pci_n1sdp.c optional pci_n1sdp acpi dev/pci/pci_host_generic.c optional pci dev/pci/pci_host_generic_acpi.c optional pci acpi dev/pci/pci_host_generic_fdt.c optional pci fdt dev/pci/pci_dw_mv.c optional pci fdt dev/pci/pci_dw.c optional pci fdt dev/pci/pci_dw_if.m optional pci fdt dev/psci/psci.c standard dev/psci/smccc_arm64.S standard dev/psci/smccc.c standard +dev/safexcel/safexcel.c optional safexcel fdt dev/sdhci/sdhci_xenon.c optional sdhci_xenon sdhci fdt dev/uart/uart_cpu_arm64.c optional uart dev/uart/uart_dev_mu.c optional uart uart_mu dev/uart/uart_dev_pl011.c optional uart pl011 dev/usb/controller/dwc_otg_hisi.c optional dwcotg fdt soc_hisi_hi6220 dev/usb/controller/dwc3.c optional fdt dwc3 dev/usb/controller/ehci_mv.c optional ehci_mv fdt dev/usb/controller/generic_ehci.c optional ehci dev/usb/controller/generic_ehci_acpi.c optional ehci acpi dev/usb/controller/generic_ehci_fdt.c optional ehci fdt dev/usb/controller/generic_ohci.c optional ohci fdt dev/usb/controller/generic_usb_if.m optional ohci fdt dev/usb/controller/usb_nop_xceiv.c optional fdt ext_resources dev/usb/controller/generic_xhci.c optional xhci dev/usb/controller/generic_xhci_acpi.c optional xhci acpi dev/usb/controller/generic_xhci_fdt.c optional xhci fdt dev/vnic/mrml_bridge.c optional vnic fdt dev/vnic/nic_main.c optional vnic pci dev/vnic/nicvf_main.c optional vnic pci pci_iov dev/vnic/nicvf_queues.c optional vnic pci pci_iov dev/vnic/thunder_bgx_fdt.c optional vnic fdt dev/vnic/thunder_bgx.c optional vnic pci dev/vnic/thunder_mdio_fdt.c optional vnic fdt dev/vnic/thunder_mdio.c optional vnic dev/vnic/lmac_if.m optional inet | inet6 | vnic kern/kern_clocksource.c standard kern/msi_if.m optional intrng kern/pic_if.m optional intrng kern/subr_devmap.c standard kern/subr_intr.c optional intrng kern/subr_physmem.c standard libkern/bcmp.c standard libkern/memcmp.c standard \ compile-with "${NORMAL_C:N-fsanitize*}" libkern/memset.c standard \ compile-with "${NORMAL_C:N-fsanitize*}" libkern/arm64/crc32c_armv8.S standard cddl/dev/dtrace/aarch64/dtrace_asm.S optional dtrace compile-with "${DTRACE_S}" cddl/dev/dtrace/aarch64/dtrace_subr.c optional dtrace compile-with "${DTRACE_C}" cddl/dev/fbt/aarch64/fbt_isa.c optional dtrace_fbt | dtraceall compile-with "${FBT_C}" # RockChip Drivers arm64/rockchip/rk3399_emmcphy.c optional fdt rk_emmcphy soc_rockchip_rk3399 arm64/rockchip/rk_dwc3.c optional fdt rk_dwc3 soc_rockchip_rk3399 arm64/rockchip/rk_i2c.c optional fdt rk_i2c soc_rockchip_rk3328 | fdt rk_i2c soc_rockchip_rk3399 arm64/rockchip/rk805.c optional fdt rk805 soc_rockchip_rk3328 | fdt rk805 soc_rockchip_rk3399 arm64/rockchip/rk_grf.c optional fdt soc_rockchip_rk3328 | fdt soc_rockchip_rk3399 arm64/rockchip/rk_pinctrl.c optional fdt rk_pinctrl soc_rockchip_rk3328 | fdt rk_pinctrl soc_rockchip_rk3399 arm64/rockchip/rk_gpio.c optional fdt rk_gpio soc_rockchip_rk3328 | fdt rk_gpio soc_rockchip_rk3399 arm64/rockchip/rk_iodomain.c optional fdt rk_iodomain arm64/rockchip/rk_spi.c optional fdt rk_spi arm64/rockchip/rk_usb2phy.c optional fdt rk_usb2phy soc_rockchip_rk3328 | soc_rockchip_rk3399 arm64/rockchip/rk_typec_phy.c optional fdt rk_typec_phy soc_rockchip_rk3399 arm64/rockchip/if_dwc_rk.c optional fdt dwc_rk soc_rockchip_rk3328 | fdt dwc_rk soc_rockchip_rk3399 arm64/rockchip/rk_tsadc_if.m optional fdt soc_rockchip_rk3399 arm64/rockchip/rk_tsadc.c optional fdt soc_rockchip_rk3399 arm64/rockchip/rk_pwm.c optional fdt rk_pwm arm64/rockchip/rk_pcie.c optional fdt pci soc_rockchip_rk3399 arm64/rockchip/rk_pcie_phy.c optional fdt pci soc_rockchip_rk3399 dev/dwc/if_dwc.c optional fdt dwc_rk soc_rockchip_rk3328 | fdt dwc_rk soc_rockchip_rk3399 dev/dwc/if_dwc_if.m optional fdt dwc_rk soc_rockchip_rk3328 | fdt dwc_rk soc_rockchip_rk3399 # RockChip Clock support arm64/rockchip/clk/rk_cru.c optional fdt soc_rockchip_rk3328 | fdt soc_rockchip_rk3399 arm64/rockchip/clk/rk_clk_armclk.c optional fdt soc_rockchip_rk3328 | fdt soc_rockchip_rk3399 arm64/rockchip/clk/rk_clk_composite.c optional fdt soc_rockchip_rk3328 | fdt soc_rockchip_rk3399 arm64/rockchip/clk/rk_clk_fract.c optional fdt soc_rockchip_rk3328 | fdt soc_rockchip_rk3399 arm64/rockchip/clk/rk_clk_gate.c optional fdt soc_rockchip_rk3328 | fdt soc_rockchip_rk3399 arm64/rockchip/clk/rk_clk_mux.c optional fdt soc_rockchip_rk3328 | fdt soc_rockchip_rk3399 arm64/rockchip/clk/rk_clk_pll.c optional fdt soc_rockchip_rk3328 | fdt soc_rockchip_rk3399 arm64/rockchip/clk/rk3328_cru.c optional fdt soc_rockchip_rk3328 arm64/rockchip/clk/rk3399_cru.c optional fdt soc_rockchip_rk3399 arm64/rockchip/clk/rk3399_pmucru.c optional fdt soc_rockchip_rk3399 # i.MX8 Clock support arm64/freescale/imx/imx8mq_ccm.c optional fdt soc_freescale_imx8 arm64/freescale/imx/clk/imx_clk_gate.c optional fdt soc_freescale_imx8 arm64/freescale/imx/clk/imx_clk_mux.c optional fdt soc_freescale_imx8 arm64/freescale/imx/clk/imx_clk_composite.c optional fdt soc_freescale_imx8 arm64/freescale/imx/clk/imx_clk_sscg_pll.c optional fdt soc_freescale_imx8 arm64/freescale/imx/clk/imx_clk_frac_pll.c optional fdt soc_freescale_imx8 # iMX drivers arm/freescale/imx/imx_gpio.c optional gpio arm/freescale/imx/imx_i2c.c optional fsliic arm/freescale/imx/imx_machdep.c standard arm64/freescale/imx/imx7gpc.c optional fdt soc_freescale_imx8 dev/ffec/if_ffec.c optional ffec Index: head/sys/dev/safexcel/safexcel.c =================================================================== --- head/sys/dev/safexcel/safexcel.c (nonexistent) +++ head/sys/dev/safexcel/safexcel.c (revision 363180) @@ -0,0 +1,2637 @@ +/*- + * SPDX-License-Identifier: BSD-2-Clause-FreeBSD + * + * Copyright (c) 2020 Rubicon Communications, LLC (Netgate) + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include +__FBSDID("$FreeBSD$"); + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include + +#include +#include +#include + +#include +#include + +#include "cryptodev_if.h" + +#include "safexcel_reg.h" +#include "safexcel_var.h" + +static MALLOC_DEFINE(M_SAFEXCEL, "safexcel_req", "safexcel request buffers"); + +/* + * We only support the EIP97 for now. + */ +static struct ofw_compat_data safexcel_compat[] = { + { "inside-secure,safexcel-eip97ies", (uintptr_t)97 }, + { "inside-secure,safexcel-eip97", (uintptr_t)97 }, + { NULL, 0 } +}; + +const struct safexcel_reg_offsets eip97_regs_offset = { + .hia_aic = SAFEXCEL_EIP97_HIA_AIC_BASE, + .hia_aic_g = SAFEXCEL_EIP97_HIA_AIC_G_BASE, + .hia_aic_r = SAFEXCEL_EIP97_HIA_AIC_R_BASE, + .hia_aic_xdr = SAFEXCEL_EIP97_HIA_AIC_xDR_BASE, + .hia_dfe = SAFEXCEL_EIP97_HIA_DFE_BASE, + .hia_dfe_thr = SAFEXCEL_EIP97_HIA_DFE_THR_BASE, + .hia_dse = SAFEXCEL_EIP97_HIA_DSE_BASE, + .hia_dse_thr = SAFEXCEL_EIP97_HIA_DSE_THR_BASE, + .hia_gen_cfg = SAFEXCEL_EIP97_HIA_GEN_CFG_BASE, + .pe = SAFEXCEL_EIP97_PE_BASE, +}; + +const struct safexcel_reg_offsets eip197_regs_offset = { + .hia_aic = SAFEXCEL_EIP197_HIA_AIC_BASE, + .hia_aic_g = SAFEXCEL_EIP197_HIA_AIC_G_BASE, + .hia_aic_r = SAFEXCEL_EIP197_HIA_AIC_R_BASE, + .hia_aic_xdr = SAFEXCEL_EIP197_HIA_AIC_xDR_BASE, + .hia_dfe = SAFEXCEL_EIP197_HIA_DFE_BASE, + .hia_dfe_thr = SAFEXCEL_EIP197_HIA_DFE_THR_BASE, + .hia_dse = SAFEXCEL_EIP197_HIA_DSE_BASE, + .hia_dse_thr = SAFEXCEL_EIP197_HIA_DSE_THR_BASE, + .hia_gen_cfg = SAFEXCEL_EIP197_HIA_GEN_CFG_BASE, + .pe = SAFEXCEL_EIP197_PE_BASE, +}; + +static struct safexcel_cmd_descr * +safexcel_cmd_descr_next(struct safexcel_cmd_descr_ring *ring) +{ + struct safexcel_cmd_descr *cdesc; + + if (ring->write == ring->read) + return (NULL); + cdesc = &ring->desc[ring->read]; + ring->read = (ring->read + 1) % SAFEXCEL_RING_SIZE; + return (cdesc); +} + +static struct safexcel_res_descr * +safexcel_res_descr_next(struct safexcel_res_descr_ring *ring) +{ + struct safexcel_res_descr *rdesc; + + if (ring->write == ring->read) + return (NULL); + rdesc = &ring->desc[ring->read]; + ring->read = (ring->read + 1) % SAFEXCEL_RING_SIZE; + return (rdesc); +} + +static struct safexcel_request * +safexcel_alloc_request(struct safexcel_softc *sc, struct safexcel_ring *ring) +{ + struct safexcel_request *req; + + mtx_assert(&ring->mtx, MA_OWNED); + + if ((req = STAILQ_FIRST(&ring->free_requests)) != NULL) + STAILQ_REMOVE_HEAD(&ring->free_requests, link); + return (req); +} + +static void +safexcel_free_request(struct safexcel_ring *ring, struct safexcel_request *req) +{ + struct safexcel_context_record *ctx; + + mtx_assert(&ring->mtx, MA_OWNED); + + if (req->dmap_loaded) { + bus_dmamap_unload(ring->data_dtag, req->dmap); + req->dmap_loaded = false; + } + ctx = (struct safexcel_context_record *)req->ctx.vaddr; + explicit_bzero(ctx->data, sizeof(ctx->data)); + explicit_bzero(req->iv, sizeof(req->iv)); + STAILQ_INSERT_TAIL(&ring->free_requests, req, link); +} + +static void +safexcel_enqueue_request(struct safexcel_softc *sc, struct safexcel_ring *ring, + struct safexcel_request *req) +{ + mtx_assert(&ring->mtx, MA_OWNED); + + STAILQ_INSERT_TAIL(&ring->ready_requests, req, link); +} + +static void +safexcel_rdr_intr(struct safexcel_softc *sc, int ringidx) +{ + struct safexcel_cmd_descr *cdesc; + struct safexcel_res_descr *rdesc; + struct safexcel_request *req; + struct safexcel_ring *ring; + uint32_t error, i, ncdescs, nrdescs, nreqs; + + ring = &sc->sc_ring[ringidx]; + + mtx_lock(&ring->mtx); + nreqs = SAFEXCEL_READ(sc, + SAFEXCEL_HIA_RDR(sc, ringidx) + SAFEXCEL_HIA_xDR_PROC_COUNT); + nreqs >>= SAFEXCEL_xDR_PROC_xD_PKT_OFFSET; + nreqs &= SAFEXCEL_xDR_PROC_xD_PKT_MASK; + if (nreqs == 0) { + SAFEXCEL_DPRINTF(sc, 1, + "zero pending requests on ring %d\n", ringidx); + goto out; + } + + ring = &sc->sc_ring[ringidx]; + bus_dmamap_sync(ring->rdr.dma.tag, ring->rdr.dma.map, + BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); + bus_dmamap_sync(ring->cdr.dma.tag, ring->cdr.dma.map, + BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); + bus_dmamap_sync(ring->dma_atok.tag, ring->dma_atok.map, + BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); + + ncdescs = nrdescs = 0; + for (i = 0; i < nreqs; i++) { + req = STAILQ_FIRST(&ring->queued_requests); + KASSERT(req != NULL, ("%s: expected %d pending requests", + __func__, nreqs)); + STAILQ_REMOVE_HEAD(&ring->queued_requests, link); + mtx_unlock(&ring->mtx); + + bus_dmamap_sync(req->ctx.tag, req->ctx.map, + BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); + bus_dmamap_sync(ring->data_dtag, req->dmap, + BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); + + ncdescs += req->cdescs; + while (req->cdescs-- > 0) { + cdesc = safexcel_cmd_descr_next(&ring->cdr); + KASSERT(cdesc != NULL, + ("%s: missing control descriptor", __func__)); + if (req->cdescs == 0) + KASSERT(cdesc->last_seg, + ("%s: chain is not terminated", __func__)); + } + nrdescs += req->rdescs; + while (req->rdescs-- > 0) { + rdesc = safexcel_res_descr_next(&ring->rdr); + error = rdesc->result_data.error_code; + if (error != 0) { + if (error == SAFEXCEL_RESULT_ERR_AUTH_FAILED && + req->crp->crp_etype == 0) { + req->crp->crp_etype = EBADMSG; + } else { + SAFEXCEL_DPRINTF(sc, 1, + "error code %#x\n", error); + req->crp->crp_etype = EIO; + } + } + } + + crypto_done(req->crp); + mtx_lock(&ring->mtx); + safexcel_free_request(ring, req); + } + + if (nreqs != 0) { + SAFEXCEL_WRITE(sc, + SAFEXCEL_HIA_RDR(sc, ringidx) + SAFEXCEL_HIA_xDR_PROC_COUNT, + SAFEXCEL_xDR_PROC_xD_PKT(nreqs) | + (sc->sc_config.rd_offset * nrdescs * sizeof(uint32_t))); + } +out: + if (!STAILQ_EMPTY(&ring->queued_requests)) { + SAFEXCEL_WRITE(sc, + SAFEXCEL_HIA_RDR(sc, ringidx) + SAFEXCEL_HIA_xDR_THRESH, + SAFEXCEL_HIA_CDR_THRESH_PKT_MODE | 1); + } + mtx_unlock(&ring->mtx); +} + +static void +safexcel_ring_intr(void *arg) +{ + struct safexcel_softc *sc; + struct safexcel_intr_handle *ih; + uint32_t status, stat; + int ring; + bool blocked, rdrpending; + + ih = arg; + sc = ih->sc; + ring = ih->ring; + + status = SAFEXCEL_READ(sc, SAFEXCEL_HIA_AIC_R(sc) + + SAFEXCEL_HIA_AIC_R_ENABLED_STAT(ring)); + /* CDR interrupts */ + if (status & SAFEXCEL_CDR_IRQ(ring)) { + stat = SAFEXCEL_READ(sc, + SAFEXCEL_HIA_CDR(sc, ring) + SAFEXCEL_HIA_xDR_STAT); + SAFEXCEL_WRITE(sc, + SAFEXCEL_HIA_CDR(sc, ring) + SAFEXCEL_HIA_xDR_STAT, + stat & SAFEXCEL_CDR_INTR_MASK); + } + /* RDR interrupts */ + rdrpending = false; + if (status & SAFEXCEL_RDR_IRQ(ring)) { + stat = SAFEXCEL_READ(sc, + SAFEXCEL_HIA_RDR(sc, ring) + SAFEXCEL_HIA_xDR_STAT); + if ((stat & SAFEXCEL_xDR_ERR) == 0) + rdrpending = true; + SAFEXCEL_WRITE(sc, + SAFEXCEL_HIA_RDR(sc, ring) + SAFEXCEL_HIA_xDR_STAT, + stat & SAFEXCEL_RDR_INTR_MASK); + } + SAFEXCEL_WRITE(sc, + SAFEXCEL_HIA_AIC_R(sc) + SAFEXCEL_HIA_AIC_R_ACK(ring), + status); + + if (rdrpending) + safexcel_rdr_intr(sc, ring); + + mtx_lock(&sc->sc_mtx); + blocked = sc->sc_blocked; + sc->sc_blocked = 0; + mtx_unlock(&sc->sc_mtx); + + if (blocked) + crypto_unblock(sc->sc_cid, blocked); +} + +static int +safexcel_configure(struct safexcel_softc *sc) +{ + uint32_t i, mask, pemask, reg; + device_t dev; + + if (sc->sc_type == 197) { + sc->sc_offsets = eip197_regs_offset; + pemask = SAFEXCEL_N_PES_MASK; + } else { + sc->sc_offsets = eip97_regs_offset; + pemask = EIP97_N_PES_MASK; + } + + dev = sc->sc_dev; + + /* Scan for valid ring interrupt controllers. */ + for (i = 0; i < SAFEXCEL_MAX_RING_AIC; i++) { + reg = SAFEXCEL_READ(sc, SAFEXCEL_HIA_AIC_R(sc) + + SAFEXCEL_HIA_AIC_R_VERSION(i)); + if (SAFEXCEL_REG_LO16(reg) != EIP201_VERSION_LE) + break; + } + sc->sc_config.aic_rings = i; + if (sc->sc_config.aic_rings == 0) + return (-1); + + reg = SAFEXCEL_READ(sc, SAFEXCEL_HIA_AIC_G(sc) + SAFEXCEL_HIA_OPTIONS); + /* Check for 64bit addressing. */ + if ((reg & SAFEXCEL_OPT_ADDR_64) == 0) + return (-1); + /* Check alignment constraints (which we do not support). */ + if (((reg & SAFEXCEL_OPT_TGT_ALIGN_MASK) >> + SAFEXCEL_OPT_TGT_ALIGN_OFFSET) != 0) + return (-1); + + sc->sc_config.hdw = + (reg & SAFEXCEL_xDR_HDW_MASK) >> SAFEXCEL_xDR_HDW_OFFSET; + mask = (1 << sc->sc_config.hdw) - 1; + + sc->sc_config.rings = reg & SAFEXCEL_N_RINGS_MASK; + /* Limit the number of rings to the number of the AIC Rings. */ + sc->sc_config.rings = MIN(sc->sc_config.rings, sc->sc_config.aic_rings); + + sc->sc_config.pes = (reg & pemask) >> SAFEXCEL_N_PES_OFFSET; + + sc->sc_config.cd_size = + sizeof(struct safexcel_cmd_descr) / sizeof(uint32_t); + sc->sc_config.cd_offset = (sc->sc_config.cd_size + mask) & ~mask; + + sc->sc_config.rd_size = + sizeof(struct safexcel_res_descr) / sizeof(uint32_t); + sc->sc_config.rd_offset = (sc->sc_config.rd_size + mask) & ~mask; + + sc->sc_config.atok_offset = + (SAFEXCEL_MAX_ATOKENS * sizeof(struct safexcel_instr) + mask) & + ~mask; + + return (0); +} + +static void +safexcel_init_hia_bus_access(struct safexcel_softc *sc) +{ + uint32_t version, val; + + /* Determine endianness and configure byte swap. */ + version = SAFEXCEL_READ(sc, + SAFEXCEL_HIA_AIC(sc) + SAFEXCEL_HIA_VERSION); + val = SAFEXCEL_READ(sc, SAFEXCEL_HIA_AIC(sc) + SAFEXCEL_HIA_MST_CTRL); + if (SAFEXCEL_REG_HI16(version) == SAFEXCEL_HIA_VERSION_BE) { + val = SAFEXCEL_READ(sc, + SAFEXCEL_HIA_AIC(sc) + SAFEXCEL_HIA_MST_CTRL); + val = val ^ (SAFEXCEL_MST_CTRL_NO_BYTE_SWAP >> 24); + SAFEXCEL_WRITE(sc, + SAFEXCEL_HIA_AIC(sc) + SAFEXCEL_HIA_MST_CTRL, + val); + } + + /* Configure wr/rd cache values. */ + SAFEXCEL_WRITE(sc, SAFEXCEL_HIA_GEN_CFG(sc) + SAFEXCEL_HIA_MST_CTRL, + SAFEXCEL_MST_CTRL_RD_CACHE(RD_CACHE_4BITS) | + SAFEXCEL_MST_CTRL_WD_CACHE(WR_CACHE_4BITS)); +} + +static void +safexcel_disable_global_interrupts(struct safexcel_softc *sc) +{ + /* Disable and clear pending interrupts. */ + SAFEXCEL_WRITE(sc, + SAFEXCEL_HIA_AIC_G(sc) + SAFEXCEL_HIA_AIC_G_ENABLE_CTRL, 0); + SAFEXCEL_WRITE(sc, + SAFEXCEL_HIA_AIC_G(sc) + SAFEXCEL_HIA_AIC_G_ACK, + SAFEXCEL_AIC_G_ACK_ALL_MASK); +} + +/* + * Configure the data fetch engine. This component parses command descriptors + * and sets up DMA transfers from host memory to the corresponding processing + * engine. + */ +static void +safexcel_configure_dfe_engine(struct safexcel_softc *sc, int pe) +{ + /* Reset all DFE threads. */ + SAFEXCEL_WRITE(sc, + SAFEXCEL_HIA_DFE_THR(sc) + SAFEXCEL_HIA_DFE_THR_CTRL(pe), + SAFEXCEL_DxE_THR_CTRL_RESET_PE); + + /* Deassert the DFE reset. */ + SAFEXCEL_WRITE(sc, + SAFEXCEL_HIA_DFE_THR(sc) + SAFEXCEL_HIA_DFE_THR_CTRL(pe), 0); + + /* DMA transfer size to use. */ + SAFEXCEL_WRITE(sc, SAFEXCEL_HIA_DFE(sc) + SAFEXCEL_HIA_DFE_CFG(pe), + SAFEXCEL_HIA_DFE_CFG_DIS_DEBUG | + SAFEXCEL_HIA_DxE_CFG_MIN_DATA_SIZE(6) | + SAFEXCEL_HIA_DxE_CFG_MAX_DATA_SIZE(9) | + SAFEXCEL_HIA_DxE_CFG_MIN_CTRL_SIZE(6) | + SAFEXCEL_HIA_DxE_CFG_MAX_CTRL_SIZE(7) | + SAFEXCEL_HIA_DxE_CFG_DATA_CACHE_CTRL(RD_CACHE_3BITS) | + SAFEXCEL_HIA_DxE_CFG_CTRL_CACHE_CTRL(RD_CACHE_3BITS)); + + /* Configure the PE DMA transfer thresholds. */ + SAFEXCEL_WRITE(sc, SAFEXCEL_PE(sc) + SAFEXCEL_PE_IN_DBUF_THRES(pe), + SAFEXCEL_PE_IN_xBUF_THRES_MIN(6) | + SAFEXCEL_PE_IN_xBUF_THRES_MAX(9)); + SAFEXCEL_WRITE(sc, SAFEXCEL_PE(sc) + SAFEXCEL_PE_IN_TBUF_THRES(pe), + SAFEXCEL_PE_IN_xBUF_THRES_MIN(6) | + SAFEXCEL_PE_IN_xBUF_THRES_MAX(7)); +} + +/* + * Configure the data store engine. This component parses result descriptors + * and sets up DMA transfers from the processing engine to host memory. + */ +static int +safexcel_configure_dse(struct safexcel_softc *sc, int pe) +{ + uint32_t val; + int count; + + /* Disable and reset all DSE threads. */ + SAFEXCEL_WRITE(sc, + SAFEXCEL_HIA_DSE_THR(sc) + SAFEXCEL_HIA_DSE_THR_CTRL(pe), + SAFEXCEL_DxE_THR_CTRL_RESET_PE); + + /* Wait for a second for threads to go idle. */ + for (count = 0;;) { + val = SAFEXCEL_READ(sc, + SAFEXCEL_HIA_DSE_THR(sc) + SAFEXCEL_HIA_DSE_THR_STAT(pe)); + if ((val & SAFEXCEL_DSE_THR_RDR_ID_MASK) == + SAFEXCEL_DSE_THR_RDR_ID_MASK) + break; + if (count++ > 10000) { + device_printf(sc->sc_dev, "DSE reset timeout\n"); + return (-1); + } + DELAY(100); + } + + /* Exit the reset state. */ + SAFEXCEL_WRITE(sc, + SAFEXCEL_HIA_DSE_THR(sc) + SAFEXCEL_HIA_DSE_THR_CTRL(pe), 0); + + /* DMA transfer size to use */ + SAFEXCEL_WRITE(sc, SAFEXCEL_HIA_DSE(sc) + SAFEXCEL_HIA_DSE_CFG(pe), + SAFEXCEL_HIA_DSE_CFG_DIS_DEBUG | + SAFEXCEL_HIA_DxE_CFG_MIN_DATA_SIZE(7) | + SAFEXCEL_HIA_DxE_CFG_MAX_DATA_SIZE(8) | + SAFEXCEL_HIA_DxE_CFG_DATA_CACHE_CTRL(WR_CACHE_3BITS) | + SAFEXCEL_HIA_DSE_CFG_ALLWAYS_BUFFERABLE); + + /* Configure the procesing engine thresholds */ + SAFEXCEL_WRITE(sc, + SAFEXCEL_PE(sc) + SAFEXCEL_PE_OUT_DBUF_THRES(pe), + SAFEXCEL_PE_OUT_DBUF_THRES_MIN(7) | + SAFEXCEL_PE_OUT_DBUF_THRES_MAX(8)); + + return (0); +} + +static void +safexcel_hw_prepare_rings(struct safexcel_softc *sc) +{ + int i; + + for (i = 0; i < sc->sc_config.rings; i++) { + /* + * Command descriptors. + */ + + /* Clear interrupts for this ring. */ + SAFEXCEL_WRITE(sc, + SAFEXCEL_HIA_AIC_R(sc) + SAFEXCEL_HIA_AIC_R_ENABLE_CLR(i), + SAFEXCEL_HIA_AIC_R_ENABLE_CLR_ALL_MASK); + + /* Disable external triggering. */ + SAFEXCEL_WRITE(sc, + SAFEXCEL_HIA_CDR(sc, i) + SAFEXCEL_HIA_xDR_CFG, 0); + + /* Clear the pending prepared counter. */ + SAFEXCEL_WRITE(sc, + SAFEXCEL_HIA_CDR(sc, i) + SAFEXCEL_HIA_xDR_PREP_COUNT, + SAFEXCEL_xDR_PREP_CLR_COUNT); + + /* Clear the pending processed counter. */ + SAFEXCEL_WRITE(sc, + SAFEXCEL_HIA_CDR(sc, i) + SAFEXCEL_HIA_xDR_PROC_COUNT, + SAFEXCEL_xDR_PROC_CLR_COUNT); + + SAFEXCEL_WRITE(sc, + SAFEXCEL_HIA_CDR(sc, i) + SAFEXCEL_HIA_xDR_PREP_PNTR, 0); + SAFEXCEL_WRITE(sc, + SAFEXCEL_HIA_CDR(sc, i) + SAFEXCEL_HIA_xDR_PROC_PNTR, 0); + + SAFEXCEL_WRITE(sc, + SAFEXCEL_HIA_CDR(sc, i) + SAFEXCEL_HIA_xDR_RING_SIZE, + SAFEXCEL_RING_SIZE * sc->sc_config.cd_offset * + sizeof(uint32_t)); + + /* + * Result descriptors. + */ + + /* Disable external triggering. */ + SAFEXCEL_WRITE(sc, + SAFEXCEL_HIA_RDR(sc, i) + SAFEXCEL_HIA_xDR_CFG, 0); + + /* Clear the pending prepared counter. */ + SAFEXCEL_WRITE(sc, + SAFEXCEL_HIA_RDR(sc, i) + SAFEXCEL_HIA_xDR_PREP_COUNT, + SAFEXCEL_xDR_PREP_CLR_COUNT); + + /* Clear the pending processed counter. */ + SAFEXCEL_WRITE(sc, + SAFEXCEL_HIA_RDR(sc, i) + SAFEXCEL_HIA_xDR_PROC_COUNT, + SAFEXCEL_xDR_PROC_CLR_COUNT); + + SAFEXCEL_WRITE(sc, + SAFEXCEL_HIA_RDR(sc, i) + SAFEXCEL_HIA_xDR_PREP_PNTR, 0); + SAFEXCEL_WRITE(sc, + SAFEXCEL_HIA_RDR(sc, i) + SAFEXCEL_HIA_xDR_PROC_PNTR, 0); + + /* Ring size. */ + SAFEXCEL_WRITE(sc, + SAFEXCEL_HIA_RDR(sc, i) + SAFEXCEL_HIA_xDR_RING_SIZE, + SAFEXCEL_RING_SIZE * sc->sc_config.rd_offset * + sizeof(uint32_t)); + } +} + +static void +safexcel_hw_setup_rings(struct safexcel_softc *sc) +{ + struct safexcel_ring *ring; + uint32_t cd_size_rnd, mask, rd_size_rnd, val; + int i; + + mask = (1 << sc->sc_config.hdw) - 1; + cd_size_rnd = (sc->sc_config.cd_size + mask) >> sc->sc_config.hdw; + val = (sizeof(struct safexcel_res_descr) - + sizeof(struct safexcel_res_data)) / sizeof(uint32_t); + rd_size_rnd = (val + mask) >> sc->sc_config.hdw; + + for (i = 0; i < sc->sc_config.rings; i++) { + ring = &sc->sc_ring[i]; + + /* + * Command descriptors. + */ + + /* Ring base address. */ + SAFEXCEL_WRITE(sc, SAFEXCEL_HIA_CDR(sc, i) + + SAFEXCEL_HIA_xDR_RING_BASE_ADDR_LO, + SAFEXCEL_ADDR_LO(ring->cdr.dma.paddr)); + SAFEXCEL_WRITE(sc, SAFEXCEL_HIA_CDR(sc, i) + + SAFEXCEL_HIA_xDR_RING_BASE_ADDR_HI, + SAFEXCEL_ADDR_HI(ring->cdr.dma.paddr)); + + SAFEXCEL_WRITE(sc, + SAFEXCEL_HIA_CDR(sc, i) + SAFEXCEL_HIA_xDR_DESC_SIZE, + SAFEXCEL_xDR_DESC_MODE_64BIT | SAFEXCEL_CDR_DESC_MODE_ADCP | + (sc->sc_config.cd_offset << SAFEXCEL_xDR_DESC_xD_OFFSET) | + sc->sc_config.cd_size); + + SAFEXCEL_WRITE(sc, + SAFEXCEL_HIA_CDR(sc, i) + SAFEXCEL_HIA_xDR_CFG, + ((SAFEXCEL_FETCH_COUNT * (cd_size_rnd << sc->sc_config.hdw)) << + SAFEXCEL_xDR_xD_FETCH_THRESH) | + (SAFEXCEL_FETCH_COUNT * sc->sc_config.cd_offset)); + + /* Configure DMA tx control. */ + SAFEXCEL_WRITE(sc, + SAFEXCEL_HIA_CDR(sc, i) + SAFEXCEL_HIA_xDR_DMA_CFG, + SAFEXCEL_HIA_xDR_CFG_WR_CACHE(WR_CACHE_3BITS) | + SAFEXCEL_HIA_xDR_CFG_RD_CACHE(RD_CACHE_3BITS)); + + /* Clear any pending interrupt. */ + SAFEXCEL_WRITE(sc, + SAFEXCEL_HIA_CDR(sc, i) + SAFEXCEL_HIA_xDR_STAT, + SAFEXCEL_CDR_INTR_MASK); + + /* + * Result descriptors. + */ + + /* Ring base address. */ + SAFEXCEL_WRITE(sc, SAFEXCEL_HIA_RDR(sc, i) + + SAFEXCEL_HIA_xDR_RING_BASE_ADDR_LO, + SAFEXCEL_ADDR_LO(ring->rdr.dma.paddr)); + SAFEXCEL_WRITE(sc, SAFEXCEL_HIA_RDR(sc, i) + + SAFEXCEL_HIA_xDR_RING_BASE_ADDR_HI, + SAFEXCEL_ADDR_HI(ring->rdr.dma.paddr)); + + SAFEXCEL_WRITE(sc, + SAFEXCEL_HIA_RDR(sc, i) + SAFEXCEL_HIA_xDR_DESC_SIZE, + SAFEXCEL_xDR_DESC_MODE_64BIT | + (sc->sc_config.rd_offset << SAFEXCEL_xDR_DESC_xD_OFFSET) | + sc->sc_config.rd_size); + + SAFEXCEL_WRITE(sc, + SAFEXCEL_HIA_RDR(sc, i) + SAFEXCEL_HIA_xDR_CFG, + ((SAFEXCEL_FETCH_COUNT * (rd_size_rnd << sc->sc_config.hdw)) << + SAFEXCEL_xDR_xD_FETCH_THRESH) | + (SAFEXCEL_FETCH_COUNT * sc->sc_config.rd_offset)); + + /* Configure DMA tx control. */ + SAFEXCEL_WRITE(sc, + SAFEXCEL_HIA_RDR(sc, i) + SAFEXCEL_HIA_xDR_DMA_CFG, + SAFEXCEL_HIA_xDR_CFG_WR_CACHE(WR_CACHE_3BITS) | + SAFEXCEL_HIA_xDR_CFG_RD_CACHE(RD_CACHE_3BITS) | + SAFEXCEL_HIA_xDR_WR_RES_BUF | SAFEXCEL_HIA_xDR_WR_CTRL_BUF); + + /* Clear any pending interrupt. */ + SAFEXCEL_WRITE(sc, + SAFEXCEL_HIA_RDR(sc, i) + SAFEXCEL_HIA_xDR_STAT, + SAFEXCEL_RDR_INTR_MASK); + + /* Enable ring interrupt. */ + SAFEXCEL_WRITE(sc, + SAFEXCEL_HIA_AIC_R(sc) + SAFEXCEL_HIA_AIC_R_ENABLE_CTRL(i), + SAFEXCEL_RDR_IRQ(i)); + } +} + +/* Reset the command and result descriptor rings. */ +static void +safexcel_hw_reset_rings(struct safexcel_softc *sc) +{ + int i; + + for (i = 0; i < sc->sc_config.rings; i++) { + /* + * Result descriptor ring operations. + */ + + /* Reset ring base address. */ + SAFEXCEL_WRITE(sc, SAFEXCEL_HIA_RDR(sc, i) + + SAFEXCEL_HIA_xDR_RING_BASE_ADDR_LO, 0); + SAFEXCEL_WRITE(sc, SAFEXCEL_HIA_RDR(sc, i) + + SAFEXCEL_HIA_xDR_RING_BASE_ADDR_HI, 0); + + /* Clear the pending prepared counter. */ + SAFEXCEL_WRITE(sc, + SAFEXCEL_HIA_RDR(sc, i) + SAFEXCEL_HIA_xDR_PREP_COUNT, + SAFEXCEL_xDR_PREP_CLR_COUNT); + + /* Clear the pending processed counter. */ + SAFEXCEL_WRITE(sc, + SAFEXCEL_HIA_RDR(sc, i) + SAFEXCEL_HIA_xDR_PROC_COUNT, + SAFEXCEL_xDR_PROC_CLR_COUNT); + + SAFEXCEL_WRITE(sc, + SAFEXCEL_HIA_RDR(sc, i) + SAFEXCEL_HIA_xDR_PREP_PNTR, 0); + SAFEXCEL_WRITE(sc, + SAFEXCEL_HIA_RDR(sc, i) + SAFEXCEL_HIA_xDR_PROC_PNTR, 0); + + SAFEXCEL_WRITE(sc, + SAFEXCEL_HIA_RDR(sc, i) + SAFEXCEL_HIA_xDR_RING_SIZE, 0); + + /* Clear any pending interrupt. */ + SAFEXCEL_WRITE(sc, + SAFEXCEL_HIA_RDR(sc, i) + SAFEXCEL_HIA_xDR_STAT, + SAFEXCEL_RDR_INTR_MASK); + + /* Disable ring interrupt. */ + SAFEXCEL_WRITE(sc, + SAFEXCEL_HIA_AIC_R(sc) + SAFEXCEL_HIA_AIC_R_ENABLE_CLR(i), + SAFEXCEL_RDR_IRQ(i)); + + /* + * Command descriptor ring operations. + */ + + /* Reset ring base address. */ + SAFEXCEL_WRITE(sc, SAFEXCEL_HIA_CDR(sc, i) + + SAFEXCEL_HIA_xDR_RING_BASE_ADDR_LO, 0); + SAFEXCEL_WRITE(sc, SAFEXCEL_HIA_CDR(sc, i) + + SAFEXCEL_HIA_xDR_RING_BASE_ADDR_HI, 0); + + /* Clear the pending prepared counter. */ + SAFEXCEL_WRITE(sc, + SAFEXCEL_HIA_CDR(sc, i) + SAFEXCEL_HIA_xDR_PREP_COUNT, + SAFEXCEL_xDR_PREP_CLR_COUNT); + + /* Clear the pending processed counter. */ + SAFEXCEL_WRITE(sc, + SAFEXCEL_HIA_CDR(sc, i) + SAFEXCEL_HIA_xDR_PROC_COUNT, + SAFEXCEL_xDR_PROC_CLR_COUNT); + + SAFEXCEL_WRITE(sc, + SAFEXCEL_HIA_CDR(sc, i) + SAFEXCEL_HIA_xDR_PREP_PNTR, 0); + SAFEXCEL_WRITE(sc, + SAFEXCEL_HIA_CDR(sc, i) + SAFEXCEL_HIA_xDR_PROC_PNTR, 0); + + SAFEXCEL_WRITE(sc, + SAFEXCEL_HIA_CDR(sc, i) + SAFEXCEL_HIA_xDR_RING_SIZE, 0); + + /* Clear any pending interrupt. */ + SAFEXCEL_WRITE(sc, + SAFEXCEL_HIA_CDR(sc, i) + SAFEXCEL_HIA_xDR_STAT, + SAFEXCEL_CDR_INTR_MASK); + } +} + +static void +safexcel_enable_pe_engine(struct safexcel_softc *sc, int pe) +{ + int i, ring_mask; + + for (ring_mask = 0, i = 0; i < sc->sc_config.rings; i++) { + ring_mask <<= 1; + ring_mask |= 1; + } + + /* Enable command descriptor rings. */ + SAFEXCEL_WRITE(sc, SAFEXCEL_HIA_DFE_THR(sc) + SAFEXCEL_HIA_DFE_THR_CTRL(pe), + SAFEXCEL_DxE_THR_CTRL_EN | ring_mask); + + /* Enable result descriptor rings. */ + SAFEXCEL_WRITE(sc, SAFEXCEL_HIA_DSE_THR(sc) + SAFEXCEL_HIA_DSE_THR_CTRL(pe), + SAFEXCEL_DxE_THR_CTRL_EN | ring_mask); + + /* Clear any HIA interrupt. */ + SAFEXCEL_WRITE(sc, SAFEXCEL_HIA_AIC_G(sc) + SAFEXCEL_HIA_AIC_G_ACK, + SAFEXCEL_AIC_G_ACK_HIA_MASK); +} + +static void +safexcel_execute(struct safexcel_softc *sc, struct safexcel_ring *ring, + struct safexcel_request *req) +{ + uint32_t ncdescs, nrdescs, nreqs; + int ringidx; + bool busy; + + mtx_assert(&ring->mtx, MA_OWNED); + + ringidx = req->sess->ringidx; + if (STAILQ_EMPTY(&ring->ready_requests)) + return; + busy = !STAILQ_EMPTY(&ring->queued_requests); + ncdescs = nrdescs = nreqs = 0; + while ((req = STAILQ_FIRST(&ring->ready_requests)) != NULL && + req->cdescs + ncdescs <= SAFEXCEL_MAX_BATCH_SIZE && + req->rdescs + nrdescs <= SAFEXCEL_MAX_BATCH_SIZE) { + STAILQ_REMOVE_HEAD(&ring->ready_requests, link); + STAILQ_INSERT_TAIL(&ring->queued_requests, req, link); + ncdescs += req->cdescs; + nrdescs += req->rdescs; + nreqs++; + } + + if (!busy) { + SAFEXCEL_WRITE(sc, + SAFEXCEL_HIA_RDR(sc, ringidx) + SAFEXCEL_HIA_xDR_THRESH, + SAFEXCEL_HIA_CDR_THRESH_PKT_MODE | nreqs); + } + SAFEXCEL_WRITE(sc, + SAFEXCEL_HIA_RDR(sc, ringidx) + SAFEXCEL_HIA_xDR_PREP_COUNT, + nrdescs * sc->sc_config.rd_offset * sizeof(uint32_t)); + SAFEXCEL_WRITE(sc, + SAFEXCEL_HIA_CDR(sc, ringidx) + SAFEXCEL_HIA_xDR_PREP_COUNT, + ncdescs * sc->sc_config.cd_offset * sizeof(uint32_t)); +} + +static void +safexcel_init_rings(struct safexcel_softc *sc) +{ + struct safexcel_cmd_descr *cdesc; + struct safexcel_ring *ring; + char buf[32]; + uint64_t atok; + int i, j; + + for (i = 0; i < sc->sc_config.rings; i++) { + ring = &sc->sc_ring[i]; + + snprintf(buf, sizeof(buf), "safexcel_ring%d", i); + mtx_init(&ring->mtx, buf, NULL, MTX_DEF); + STAILQ_INIT(&ring->free_requests); + STAILQ_INIT(&ring->ready_requests); + STAILQ_INIT(&ring->queued_requests); + + ring->cdr.read = ring->cdr.write = 0; + ring->rdr.read = ring->rdr.write = 0; + for (j = 0; j < SAFEXCEL_RING_SIZE; j++) { + cdesc = &ring->cdr.desc[j]; + atok = ring->dma_atok.paddr + + sc->sc_config.atok_offset * j; + cdesc->atok_lo = SAFEXCEL_ADDR_LO(atok); + cdesc->atok_hi = SAFEXCEL_ADDR_HI(atok); + } + } +} + +static void +safexcel_dma_alloc_mem_cb(void *arg, bus_dma_segment_t *segs, int nseg, + int error) +{ + struct safexcel_dma_mem *sdm; + + if (error != 0) + return; + + KASSERT(nseg == 1, ("%s: nsegs is %d", __func__, nseg)); + sdm = arg; + sdm->paddr = segs->ds_addr; +} + +static int +safexcel_dma_alloc_mem(struct safexcel_softc *sc, struct safexcel_dma_mem *sdm, + bus_size_t size) +{ + int error; + + KASSERT(sdm->vaddr == NULL, + ("%s: DMA memory descriptor in use.", __func__)); + + error = bus_dma_tag_create(bus_get_dma_tag(sc->sc_dev), /* parent */ + PAGE_SIZE, 0, /* alignment, boundary */ + BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ + BUS_SPACE_MAXADDR, /* highaddr */ + NULL, NULL, /* filtfunc, filtfuncarg */ + size, 1, /* maxsize, nsegments */ + size, BUS_DMA_COHERENT, /* maxsegsz, flags */ + NULL, NULL, /* lockfunc, lockfuncarg */ + &sdm->tag); /* dmat */ + if (error != 0) { + device_printf(sc->sc_dev, + "failed to allocate busdma tag, error %d\n", error); + goto err1; + } + + error = bus_dmamem_alloc(sdm->tag, (void **)&sdm->vaddr, + BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT, &sdm->map); + if (error != 0) { + device_printf(sc->sc_dev, + "failed to allocate DMA safe memory, error %d\n", error); + goto err2; + } + + error = bus_dmamap_load(sdm->tag, sdm->map, sdm->vaddr, size, + safexcel_dma_alloc_mem_cb, sdm, BUS_DMA_NOWAIT); + if (error != 0) { + device_printf(sc->sc_dev, + "cannot get address of the DMA memory, error %d\n", error); + goto err3; + } + + return (0); +err3: + bus_dmamem_free(sdm->tag, sdm->vaddr, sdm->map); +err2: + bus_dma_tag_destroy(sdm->tag); +err1: + sdm->vaddr = NULL; + + return (error); +} + +static void +safexcel_dma_free_mem(struct safexcel_dma_mem *sdm) +{ + bus_dmamap_unload(sdm->tag, sdm->map); + bus_dmamem_free(sdm->tag, sdm->vaddr, sdm->map); + bus_dma_tag_destroy(sdm->tag); +} + +static void +safexcel_dma_free_rings(struct safexcel_softc *sc) +{ + struct safexcel_ring *ring; + int i; + + for (i = 0; i < sc->sc_config.rings; i++) { + ring = &sc->sc_ring[i]; + safexcel_dma_free_mem(&ring->cdr.dma); + safexcel_dma_free_mem(&ring->dma_atok); + safexcel_dma_free_mem(&ring->rdr.dma); + bus_dma_tag_destroy(ring->data_dtag); + mtx_destroy(&ring->mtx); + } +} + +static int +safexcel_dma_init(struct safexcel_softc *sc) +{ + struct safexcel_ring *ring; + int error, i, size; + + for (i = 0; i < sc->sc_config.rings; i++) { + ring = &sc->sc_ring[i]; + + error = bus_dma_tag_create( + bus_get_dma_tag(sc->sc_dev),/* parent */ + 1, 0, /* alignment, boundary */ + BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ + BUS_SPACE_MAXADDR, /* highaddr */ + NULL, NULL, /* filtfunc, filtfuncarg */ + SAFEXCEL_MAX_REQUEST_SIZE, /* maxsize */ + SAFEXCEL_MAX_FRAGMENTS, /* nsegments */ + SAFEXCEL_MAX_REQUEST_SIZE, /* maxsegsz */ + BUS_DMA_COHERENT, /* flags */ + NULL, NULL, /* lockfunc, lockfuncarg */ + &ring->data_dtag); /* dmat */ + if (error != 0) { + device_printf(sc->sc_dev, + "bus_dma_tag_create main failed; error %d\n", error); + return (error); + } + + size = sizeof(uint32_t) * sc->sc_config.cd_offset * + SAFEXCEL_RING_SIZE; + error = safexcel_dma_alloc_mem(sc, &ring->cdr.dma, size); + if (error != 0) { + device_printf(sc->sc_dev, + "failed to allocate CDR DMA memory, error %d\n", + error); + goto err; + } + ring->cdr.desc = + (struct safexcel_cmd_descr *)ring->cdr.dma.vaddr; + + /* Allocate additional CDR token memory. */ + error = safexcel_dma_alloc_mem(sc, &ring->dma_atok, + sc->sc_config.atok_offset * SAFEXCEL_RING_SIZE); + if (error != 0) { + device_printf(sc->sc_dev, + "failed to allocate atoken DMA memory, error %d\n", + error); + goto err; + } + + size = sizeof(uint32_t) * sc->sc_config.rd_offset * + SAFEXCEL_RING_SIZE; + error = safexcel_dma_alloc_mem(sc, &ring->rdr.dma, size); + if (error) { + device_printf(sc->sc_dev, + "failed to allocate RDR DMA memory, error %d\n", + error); + goto err; + } + ring->rdr.desc = + (struct safexcel_res_descr *)ring->rdr.dma.vaddr; + } + + return (0); +err: + safexcel_dma_free_rings(sc); + return (error); +} + +static void +safexcel_deinit_hw(struct safexcel_softc *sc) +{ + safexcel_hw_reset_rings(sc); + safexcel_dma_free_rings(sc); +} + +static int +safexcel_init_hw(struct safexcel_softc *sc) +{ + int pe; + + /* 23.3.7 Initialization */ + if (safexcel_configure(sc) != 0) + return (EINVAL); + + if (safexcel_dma_init(sc) != 0) + return (ENOMEM); + + safexcel_init_rings(sc); + + safexcel_init_hia_bus_access(sc); + + /* 23.3.7.2 Disable EIP-97 global Interrupts */ + safexcel_disable_global_interrupts(sc); + + for (pe = 0; pe < sc->sc_config.pes; pe++) { + /* 23.3.7.3 Configure Data Fetch Engine */ + safexcel_configure_dfe_engine(sc, pe); + + /* 23.3.7.4 Configure Data Store Engine */ + if (safexcel_configure_dse(sc, pe)) { + safexcel_deinit_hw(sc); + return (-1); + } + + /* 23.3.7.5 1. Protocol enables */ + SAFEXCEL_WRITE(sc, + SAFEXCEL_PE(sc) + SAFEXCEL_PE_EIP96_FUNCTION_EN(pe), + 0xffffffff); + SAFEXCEL_WRITE(sc, + SAFEXCEL_PE(sc) + SAFEXCEL_PE_EIP96_FUNCTION2_EN(pe), + 0xffffffff); + } + + safexcel_hw_prepare_rings(sc); + + /* 23.3.7.5 Configure the Processing Engine(s). */ + for (pe = 0; pe < sc->sc_config.pes; pe++) + safexcel_enable_pe_engine(sc, pe); + + safexcel_hw_setup_rings(sc); + + return (0); +} + +static int +safexcel_setup_dev_interrupts(struct safexcel_softc *sc) +{ + int i, j; + + for (i = 0; i < SAFEXCEL_MAX_RINGS && sc->sc_intr[i] != NULL; i++) { + sc->sc_ih[i].sc = sc; + sc->sc_ih[i].ring = i; + + if (bus_setup_intr(sc->sc_dev, sc->sc_intr[i], + INTR_TYPE_NET | INTR_MPSAFE, NULL, safexcel_ring_intr, + &sc->sc_ih[i], &sc->sc_ih[i].handle)) { + device_printf(sc->sc_dev, + "couldn't setup interrupt %d\n", i); + goto err; + } + } + + return (0); + +err: + for (j = 0; j < i; j++) + bus_teardown_intr(sc->sc_dev, sc->sc_intr[j], + sc->sc_ih[j].handle); + + return (ENXIO); +} + +static void +safexcel_teardown_dev_interrupts(struct safexcel_softc *sc) +{ + int i; + + for (i = 0; i < SAFEXCEL_MAX_RINGS; i++) + bus_teardown_intr(sc->sc_dev, sc->sc_intr[i], + sc->sc_ih[i].handle); +} + +static int +safexcel_alloc_dev_resources(struct safexcel_softc *sc) +{ + char name[16]; + device_t dev; + phandle_t node; + int error, i, rid; + + dev = sc->sc_dev; + node = ofw_bus_get_node(dev); + + rid = 0; + sc->sc_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, + RF_ACTIVE); + if (sc->sc_res == NULL) { + device_printf(dev, "couldn't allocate memory resources\n"); + return (ENXIO); + } + + for (i = 0; i < SAFEXCEL_MAX_RINGS; i++) { + (void)snprintf(name, sizeof(name), "ring%d", i); + error = ofw_bus_find_string_index(node, "interrupt-names", name, + &rid); + if (error != 0) + break; + + sc->sc_intr[i] = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, + RF_ACTIVE | RF_SHAREABLE); + if (sc->sc_intr[i] == NULL) { + error = ENXIO; + goto out; + } + } + if (i == 0) { + device_printf(dev, "couldn't allocate interrupt resources\n"); + error = ENXIO; + goto out; + } + + mtx_init(&sc->sc_mtx, "safexcel softc", NULL, MTX_DEF); + + return (0); + +out: + for (i = 0; i < SAFEXCEL_MAX_RINGS && sc->sc_intr[i] != NULL; i++) + bus_release_resource(dev, SYS_RES_IRQ, + rman_get_rid(sc->sc_intr[i]), sc->sc_intr[i]); + bus_release_resource(dev, SYS_RES_MEMORY, rman_get_rid(sc->sc_res), + sc->sc_res); + return (error); +} + +static void +safexcel_free_dev_resources(struct safexcel_softc *sc) +{ + int i; + + mtx_destroy(&sc->sc_mtx); + + for (i = 0; i < SAFEXCEL_MAX_RINGS && sc->sc_intr[i] != NULL; i++) + bus_release_resource(sc->sc_dev, SYS_RES_IRQ, + rman_get_rid(sc->sc_intr[i]), sc->sc_intr[i]); + if (sc->sc_res != NULL) + bus_release_resource(sc->sc_dev, SYS_RES_MEMORY, + rman_get_rid(sc->sc_res), sc->sc_res); +} + +static int +safexcel_probe(device_t dev) +{ + struct safexcel_softc *sc; + + if (!ofw_bus_status_okay(dev)) + return (ENXIO); + + sc = device_get_softc(dev); + sc->sc_type = ofw_bus_search_compatible(dev, safexcel_compat)->ocd_data; + if (sc->sc_type == 0) + return (ENXIO); + + device_set_desc(dev, "SafeXcel EIP-97 crypto accelerator"); + + return (BUS_PROBE_DEFAULT); +} + +static int +safexcel_attach(device_t dev) +{ + struct sysctl_ctx_list *sctx; + struct safexcel_softc *sc; + struct safexcel_request *req; + struct safexcel_ring *ring; + int i, j, ringidx; + + sc = device_get_softc(dev); + sc->sc_dev = dev; + sc->sc_blocked = 0; + sc->sc_cid = -1; + + if (safexcel_alloc_dev_resources(sc)) + goto err; + + if (safexcel_setup_dev_interrupts(sc)) + goto err1; + + if (safexcel_init_hw(sc)) + goto err2; + + for (ringidx = 0; ringidx < sc->sc_config.rings; ringidx++) { + ring = &sc->sc_ring[ringidx]; + + ring->cmd_data = sglist_alloc(SAFEXCEL_MAX_FRAGMENTS, M_WAITOK); + ring->res_data = sglist_alloc(SAFEXCEL_MAX_FRAGMENTS, M_WAITOK); + + ring->requests = mallocarray(SAFEXCEL_REQUESTS_PER_RING, + sizeof(struct safexcel_request), M_SAFEXCEL, + M_WAITOK | M_ZERO); + + for (i = 0; i < SAFEXCEL_REQUESTS_PER_RING; i++) { + req = &ring->requests[i]; + req->sc = sc; + if (bus_dmamap_create(ring->data_dtag, + BUS_DMA_COHERENT, &req->dmap) != 0) { + for (j = 0; j < i; j++) + bus_dmamap_destroy(ring->data_dtag, + ring->requests[j].dmap); + goto err2; + } + if (safexcel_dma_alloc_mem(sc, &req->ctx, + sizeof(struct safexcel_context_record)) != 0) { + for (j = 0; j < i; j++) { + bus_dmamap_destroy(ring->data_dtag, + ring->requests[j].dmap); + safexcel_dma_free_mem( + &ring->requests[j].ctx); + } + goto err2; + } + STAILQ_INSERT_TAIL(&ring->free_requests, req, link); + } + } + + sctx = device_get_sysctl_ctx(dev); + SYSCTL_ADD_INT(sctx, SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), + OID_AUTO, "debug", CTLFLAG_RWTUN, &sc->sc_debug, 0, + "Debug message verbosity"); + + sc->sc_cid = crypto_get_driverid(dev, sizeof(struct safexcel_session), + CRYPTOCAP_F_HARDWARE); + if (sc->sc_cid < 0) + goto err2; + + return (0); + +err2: + safexcel_teardown_dev_interrupts(sc); +err1: + safexcel_free_dev_resources(sc); +err: + return (ENXIO); +} + +static int +safexcel_detach(device_t dev) +{ + struct safexcel_ring *ring; + struct safexcel_softc *sc; + int i, ringidx; + + sc = device_get_softc(dev); + + if (sc->sc_cid >= 0) + crypto_unregister_all(sc->sc_cid); + for (ringidx = 0; ringidx < sc->sc_config.rings; ringidx++) { + ring = &sc->sc_ring[ringidx]; + for (i = 0; i < SAFEXCEL_REQUESTS_PER_RING; i++) { + bus_dmamap_destroy(ring->data_dtag, + ring->requests[i].dmap); + safexcel_dma_free_mem(&ring->requests[i].ctx); + } + free(ring->requests, M_SAFEXCEL); + sglist_free(ring->cmd_data); + sglist_free(ring->res_data); + } + safexcel_deinit_hw(sc); + safexcel_teardown_dev_interrupts(sc); + safexcel_free_dev_resources(sc); + + return (0); +} + +/* + * Populate the request's context record with pre-computed key material. + */ +static int +safexcel_set_context(struct safexcel_request *req) +{ + const struct crypto_session_params *csp; + struct cryptop *crp; + struct safexcel_context_record *ctx; + struct safexcel_session *sess; + uint8_t *data; + int off; + + crp = req->crp; + csp = crypto_get_params(crp->crp_session); + sess = req->sess; + + ctx = (struct safexcel_context_record *)req->ctx.vaddr; + data = (uint8_t *)ctx->data; + if (csp->csp_cipher_alg != 0) { + if (crp->crp_cipher_key != NULL) + memcpy(data, crp->crp_cipher_key, sess->klen); + else + memcpy(data, csp->csp_cipher_key, sess->klen); + off = sess->klen; + } else if (csp->csp_auth_alg == CRYPTO_AES_NIST_GMAC) { + if (crp->crp_auth_key != NULL) + memcpy(data, crp->crp_auth_key, sess->klen); + else + memcpy(data, csp->csp_auth_key, sess->klen); + off = sess->klen; + } else { + off = 0; + } + + switch (csp->csp_cipher_alg) { + case CRYPTO_AES_NIST_GCM_16: + memcpy(data + off, sess->ghash_key, GMAC_BLOCK_LEN); + off += GMAC_BLOCK_LEN; + break; + case CRYPTO_AES_CCM_16: + memcpy(data + off, sess->xcbc_key, + AES_BLOCK_LEN * 2 + sess->klen); + off += AES_BLOCK_LEN * 2 + sess->klen; + break; + case CRYPTO_AES_XTS: + memcpy(data + off, sess->tweak_key, sess->klen); + off += sess->klen; + break; + } + + switch (csp->csp_auth_alg) { + case CRYPTO_AES_NIST_GMAC: + memcpy(data + off, sess->ghash_key, GMAC_BLOCK_LEN); + off += GMAC_BLOCK_LEN; + break; + case CRYPTO_SHA1_HMAC: + case CRYPTO_SHA2_224_HMAC: + case CRYPTO_SHA2_256_HMAC: + case CRYPTO_SHA2_384_HMAC: + case CRYPTO_SHA2_512_HMAC: + memcpy(data + off, sess->hmac_ipad, sess->statelen); + off += sess->statelen; + memcpy(data + off, sess->hmac_opad, sess->statelen); + off += sess->statelen; + break; + } + + return (off); +} + +/* + * Populate fields in the first command descriptor of the chain used to encode + * the specified request. These fields indicate the algorithms used, the size + * of the key material stored in the associated context record, the primitive + * operations to be performed on input data, and the location of the IV if any. + */ +static void +safexcel_set_command(struct safexcel_request *req, + struct safexcel_cmd_descr *cdesc) +{ + const struct crypto_session_params *csp; + struct cryptop *crp; + struct safexcel_session *sess; + uint32_t ctrl0, ctrl1, ctxr_len; + int alg; + + crp = req->crp; + csp = crypto_get_params(crp->crp_session); + sess = req->sess; + + ctrl0 = sess->alg | sess->digest | sess->hash; + ctrl1 = sess->mode; + + ctxr_len = safexcel_set_context(req) / sizeof(uint32_t); + ctrl0 |= SAFEXCEL_CONTROL0_SIZE(ctxr_len); + + alg = csp->csp_cipher_alg; + if (alg == 0) + alg = csp->csp_auth_alg; + + switch (alg) { + case CRYPTO_AES_CCM_16: + if (CRYPTO_OP_IS_ENCRYPT(crp->crp_op)) { + ctrl0 |= SAFEXCEL_CONTROL0_TYPE_HASH_ENCRYPT_OUT | + SAFEXCEL_CONTROL0_KEY_EN; + } else { + ctrl0 |= SAFEXCEL_CONTROL0_TYPE_DECRYPT_HASH_IN | + SAFEXCEL_CONTROL0_KEY_EN; + } + ctrl1 |= SAFEXCEL_CONTROL1_IV0 | SAFEXCEL_CONTROL1_IV1 | + SAFEXCEL_CONTROL1_IV2 | SAFEXCEL_CONTROL1_IV3; + break; + case CRYPTO_AES_CBC: + case CRYPTO_AES_ICM: + case CRYPTO_AES_XTS: + if (CRYPTO_OP_IS_ENCRYPT(crp->crp_op)) { + ctrl0 |= SAFEXCEL_CONTROL0_TYPE_CRYPTO_OUT | + SAFEXCEL_CONTROL0_KEY_EN; + if (csp->csp_auth_alg != 0) + ctrl0 |= + SAFEXCEL_CONTROL0_TYPE_ENCRYPT_HASH_OUT; + } else { + ctrl0 |= SAFEXCEL_CONTROL0_TYPE_CRYPTO_IN | + SAFEXCEL_CONTROL0_KEY_EN; + if (csp->csp_auth_alg != 0) + ctrl0 |= SAFEXCEL_CONTROL0_TYPE_HASH_DECRYPT_IN; + } + break; + case CRYPTO_AES_NIST_GCM_16: + case CRYPTO_AES_NIST_GMAC: + if (CRYPTO_OP_IS_ENCRYPT(crp->crp_op) || + csp->csp_auth_alg != 0) { + ctrl0 |= SAFEXCEL_CONTROL0_TYPE_CRYPTO_OUT | + SAFEXCEL_CONTROL0_KEY_EN | + SAFEXCEL_CONTROL0_TYPE_HASH_OUT; + } else { + ctrl0 |= SAFEXCEL_CONTROL0_TYPE_CRYPTO_IN | + SAFEXCEL_CONTROL0_KEY_EN | + SAFEXCEL_CONTROL0_TYPE_HASH_DECRYPT_IN; + } + if (csp->csp_cipher_alg == CRYPTO_AES_NIST_GCM_16) { + ctrl1 |= SAFEXCEL_CONTROL1_COUNTER_MODE | + SAFEXCEL_CONTROL1_IV0 | SAFEXCEL_CONTROL1_IV1 | + SAFEXCEL_CONTROL1_IV2; + } + break; + case CRYPTO_SHA1: + case CRYPTO_SHA2_224: + case CRYPTO_SHA2_256: + case CRYPTO_SHA2_384: + case CRYPTO_SHA2_512: + ctrl0 |= SAFEXCEL_CONTROL0_RESTART_HASH; + /* FALLTHROUGH */ + case CRYPTO_SHA1_HMAC: + case CRYPTO_SHA2_224_HMAC: + case CRYPTO_SHA2_256_HMAC: + case CRYPTO_SHA2_384_HMAC: + case CRYPTO_SHA2_512_HMAC: + ctrl0 |= SAFEXCEL_CONTROL0_TYPE_HASH_OUT; + break; + } + + cdesc->control_data.control0 = ctrl0; + cdesc->control_data.control1 = ctrl1; +} + +/* + * Construct a no-op instruction, used to pad input tokens. + */ +static void +safexcel_instr_nop(struct safexcel_instr **instrp) +{ + struct safexcel_instr *instr; + + instr = *instrp; + instr->opcode = SAFEXCEL_INSTR_OPCODE_INSERT; + instr->length = (1 << 2); + instr->status = 0; + instr->instructions = 0; + + *instrp = instr + 1; +} + +/* + * Insert the digest of the input payload. This is typically the last + * instruction of a sequence. + */ +static void +safexcel_instr_insert_digest(struct safexcel_instr **instrp, int len) +{ + struct safexcel_instr *instr; + + instr = *instrp; + instr->opcode = SAFEXCEL_INSTR_OPCODE_INSERT; + instr->length = len; + instr->status = SAFEXCEL_INSTR_STATUS_LAST_HASH | + SAFEXCEL_INSTR_STATUS_LAST_PACKET; + instr->instructions = SAFEXCEL_INSTR_DEST_OUTPUT | + SAFEXCEL_INSTR_INSERT_HASH_DIGEST; + + *instrp = instr + 1; +} + +/* + * Retrieve and verify a digest. + */ +static void +safexcel_instr_retrieve_digest(struct safexcel_instr **instrp, int len) +{ + struct safexcel_instr *instr; + + instr = *instrp; + instr->opcode = SAFEXCEL_INSTR_OPCODE_RETRIEVE; + instr->length = len; + instr->status = SAFEXCEL_INSTR_STATUS_LAST_HASH | + SAFEXCEL_INSTR_STATUS_LAST_PACKET; + instr->instructions = SAFEXCEL_INSTR_INSERT_HASH_DIGEST; + instr++; + + instr->opcode = SAFEXCEL_INSTR_OPCODE_VERIFY_FIELDS; + instr->length = len | SAFEXCEL_INSTR_VERIFY_HASH; + instr->status = SAFEXCEL_INSTR_STATUS_LAST_HASH | + SAFEXCEL_INSTR_STATUS_LAST_PACKET; + instr->instructions = SAFEXCEL_INSTR_VERIFY_PADDING; + + *instrp = instr + 1; +} + +static void +safexcel_instr_temp_aes_block(struct safexcel_instr **instrp) +{ + struct safexcel_instr *instr; + + instr = *instrp; + instr->opcode = SAFEXCEL_INSTR_OPCODE_INSERT_REMOVE_RESULT; + instr->length = 0; + instr->status = 0; + instr->instructions = AES_BLOCK_LEN; + instr++; + + instr->opcode = SAFEXCEL_INSTR_OPCODE_INSERT; + instr->length = AES_BLOCK_LEN; + instr->status = 0; + instr->instructions = SAFEXCEL_INSTR_DEST_OUTPUT | + SAFEXCEL_INSTR_DEST_CRYPTO; + + *instrp = instr + 1; +} + +/* + * Handle a request for an unauthenticated block cipher. + */ +static void +safexcel_instr_cipher(struct safexcel_request *req, + struct safexcel_instr *instr, struct safexcel_cmd_descr *cdesc) +{ + struct cryptop *crp; + + crp = req->crp; + + /* Insert the payload. */ + instr->opcode = SAFEXCEL_INSTR_OPCODE_DIRECTION; + instr->length = crp->crp_payload_length; + instr->status = SAFEXCEL_INSTR_STATUS_LAST_PACKET | + SAFEXCEL_INSTR_STATUS_LAST_HASH; + instr->instructions = SAFEXCEL_INSTR_INS_LAST | + SAFEXCEL_INSTR_DEST_CRYPTO | SAFEXCEL_INSTR_DEST_OUTPUT; + + cdesc->additional_cdata_size = 1; +} + +static void +safexcel_instr_eta(struct safexcel_request *req, struct safexcel_instr *instr, + struct safexcel_cmd_descr *cdesc) +{ + const struct crypto_session_params *csp; + struct cryptop *crp; + struct safexcel_instr *start; + + crp = req->crp; + csp = crypto_get_params(crp->crp_session); + start = instr; + + /* Insert the AAD. */ + instr->opcode = SAFEXCEL_INSTR_OPCODE_DIRECTION; + instr->length = crp->crp_aad_length; + instr->status = crp->crp_payload_length == 0 ? + SAFEXCEL_INSTR_STATUS_LAST_HASH : 0; + instr->instructions = SAFEXCEL_INSTR_INS_LAST | + SAFEXCEL_INSTR_DEST_HASH; + instr++; + + /* Encrypt any data left in the request. */ + if (crp->crp_payload_length > 0) { + instr->opcode = SAFEXCEL_INSTR_OPCODE_DIRECTION; + instr->length = crp->crp_payload_length; + instr->status = SAFEXCEL_INSTR_STATUS_LAST_HASH; + instr->instructions = SAFEXCEL_INSTR_INS_LAST | + SAFEXCEL_INSTR_DEST_CRYPTO | + SAFEXCEL_INSTR_DEST_HASH | + SAFEXCEL_INSTR_DEST_OUTPUT; + instr++; + } + + /* + * Compute the digest, or extract it and place it in the output stream. + */ + if (CRYPTO_OP_IS_ENCRYPT(crp->crp_op)) + safexcel_instr_insert_digest(&instr, req->sess->digestlen); + else + safexcel_instr_retrieve_digest(&instr, req->sess->digestlen); + cdesc->additional_cdata_size = instr - start; +} + +static void +safexcel_instr_sha_hash(struct safexcel_request *req, + struct safexcel_instr *instr) +{ + struct cryptop *crp; + struct safexcel_instr *start; + + crp = req->crp; + start = instr; + + /* Pass the input data to the hash engine. */ + instr->opcode = SAFEXCEL_INSTR_OPCODE_DIRECTION; + instr->length = crp->crp_payload_length; + instr->status = SAFEXCEL_INSTR_STATUS_LAST_HASH; + instr->instructions = SAFEXCEL_INSTR_DEST_HASH; + instr++; + + /* Insert the hash result into the output stream. */ + safexcel_instr_insert_digest(&instr, req->sess->digestlen); + + /* Pad the rest of the inline instruction space. */ + while (instr != start + SAFEXCEL_MAX_ITOKENS) + safexcel_instr_nop(&instr); +} + +static void +safexcel_instr_ccm(struct safexcel_request *req, struct safexcel_instr *instr, + struct safexcel_cmd_descr *cdesc) +{ + struct cryptop *crp; + struct safexcel_instr *start; + uint8_t *a0, *b0, *alenp, L; + int aalign, blen; + + crp = req->crp; + start = instr; + + /* + * Construct two blocks, A0 and B0, used in encryption and + * authentication, respectively. A0 is embedded in the token + * descriptor, and B0 is inserted directly into the data stream using + * instructions below. + * + * OCF seems to assume a 12-byte IV, fixing L (the payload length size) + * at 3 bytes due to the layout of B0. This is fine since the driver + * has a maximum of 65535 bytes anyway. + */ + blen = AES_BLOCK_LEN; + L = 3; + + a0 = (uint8_t *)&cdesc->control_data.token[0]; + memset(a0, 0, blen); + a0[0] = L - 1; + memcpy(&a0[1], req->iv, AES_CCM_IV_LEN); + + /* + * Insert B0 and the AAD length into the input stream. + */ + instr->opcode = SAFEXCEL_INSTR_OPCODE_INSERT; + instr->length = blen + (crp->crp_aad_length > 0 ? 2 : 0); + instr->status = 0; + instr->instructions = SAFEXCEL_INSTR_DEST_HASH | + SAFEXCEL_INSTR_INSERT_IMMEDIATE; + instr++; + + b0 = (uint8_t *)instr; + memset(b0, 0, blen); + b0[0] = + L - 1 | /* payload length size */ + ((CCM_CBC_MAX_DIGEST_LEN - 2) / 2) << 3 /* digest length */ | + (crp->crp_aad_length > 0 ? 1 : 0) << 6 /* AAD present bit */; + memcpy(&b0[1], req->iv, AES_CCM_IV_LEN); + b0[14] = crp->crp_payload_length >> 8; + b0[15] = crp->crp_payload_length & 0xff; + instr += blen / sizeof(*instr); + + /* Insert the AAD length and data into the input stream. */ + if (crp->crp_aad_length > 0) { + alenp = (uint8_t *)instr; + alenp[0] = crp->crp_aad_length >> 8; + alenp[1] = crp->crp_aad_length & 0xff; + alenp[2] = 0; + alenp[3] = 0; + instr++; + + instr->opcode = SAFEXCEL_INSTR_OPCODE_DIRECTION; + instr->length = crp->crp_aad_length; + instr->status = 0; + instr->instructions = SAFEXCEL_INSTR_DEST_HASH; + instr++; + + /* Insert zero padding. */ + aalign = (crp->crp_aad_length + 2) & (blen - 1); + instr->opcode = SAFEXCEL_INSTR_OPCODE_INSERT; + instr->length = aalign == 0 ? 0 : + blen - ((crp->crp_aad_length + 2) & (blen - 1)); + instr->status = crp->crp_payload_length == 0 ? + SAFEXCEL_INSTR_STATUS_LAST_HASH : 0; + instr->instructions = SAFEXCEL_INSTR_DEST_HASH; + instr++; + } + + safexcel_instr_temp_aes_block(&instr); + + /* Insert the cipher payload into the input stream. */ + if (crp->crp_payload_length > 0) { + instr->opcode = SAFEXCEL_INSTR_OPCODE_DIRECTION; + instr->length = crp->crp_payload_length; + instr->status = (crp->crp_payload_length & (blen - 1)) == 0 ? + SAFEXCEL_INSTR_STATUS_LAST_HASH : 0; + instr->instructions = SAFEXCEL_INSTR_DEST_OUTPUT | + SAFEXCEL_INSTR_DEST_CRYPTO | + SAFEXCEL_INSTR_DEST_HASH | + SAFEXCEL_INSTR_INS_LAST; + instr++; + + /* Insert zero padding. */ + if (crp->crp_payload_length & (blen - 1)) { + instr->opcode = SAFEXCEL_INSTR_OPCODE_INSERT; + instr->length = blen - + (crp->crp_payload_length & (blen - 1)); + instr->status = SAFEXCEL_INSTR_STATUS_LAST_HASH; + instr->instructions = SAFEXCEL_INSTR_DEST_HASH; + instr++; + } + } + + /* + * Compute the digest, or extract it and place it in the output stream. + */ + if (CRYPTO_OP_IS_ENCRYPT(crp->crp_op)) + safexcel_instr_insert_digest(&instr, req->sess->digestlen); + else + safexcel_instr_retrieve_digest(&instr, req->sess->digestlen); + + cdesc->additional_cdata_size = instr - start; +} + +static void +safexcel_instr_gcm(struct safexcel_request *req, struct safexcel_instr *instr, + struct safexcel_cmd_descr *cdesc) +{ + struct cryptop *crp; + struct safexcel_instr *start; + + memcpy(cdesc->control_data.token, req->iv, AES_GCM_IV_LEN); + cdesc->control_data.token[3] = htobe32(1); + + crp = req->crp; + start = instr; + + /* Insert the AAD into the input stream. */ + instr->opcode = SAFEXCEL_INSTR_OPCODE_DIRECTION; + instr->length = crp->crp_aad_length; + instr->status = crp->crp_payload_length == 0 ? + SAFEXCEL_INSTR_STATUS_LAST_HASH : 0; + instr->instructions = SAFEXCEL_INSTR_INS_LAST | + SAFEXCEL_INSTR_DEST_HASH; + instr++; + + safexcel_instr_temp_aes_block(&instr); + + /* Insert the cipher payload into the input stream. */ + if (crp->crp_payload_length > 0) { + instr->opcode = SAFEXCEL_INSTR_OPCODE_DIRECTION; + instr->length = crp->crp_payload_length; + instr->status = SAFEXCEL_INSTR_STATUS_LAST_HASH; + instr->instructions = SAFEXCEL_INSTR_DEST_OUTPUT | + SAFEXCEL_INSTR_DEST_CRYPTO | SAFEXCEL_INSTR_DEST_HASH | + SAFEXCEL_INSTR_INS_LAST; + instr++; + } + + /* + * Compute the digest, or extract it and place it in the output stream. + */ + if (CRYPTO_OP_IS_ENCRYPT(crp->crp_op)) + safexcel_instr_insert_digest(&instr, req->sess->digestlen); + else + safexcel_instr_retrieve_digest(&instr, req->sess->digestlen); + + cdesc->additional_cdata_size = instr - start; +} + +static void +safexcel_instr_gmac(struct safexcel_request *req, struct safexcel_instr *instr, + struct safexcel_cmd_descr *cdesc) +{ + struct cryptop *crp; + struct safexcel_instr *start; + + memcpy(cdesc->control_data.token, req->iv, AES_GCM_IV_LEN); + cdesc->control_data.token[3] = htobe32(1); + + crp = req->crp; + start = instr; + + instr->opcode = SAFEXCEL_INSTR_OPCODE_DIRECTION; + instr->length = crp->crp_payload_length; + instr->status = SAFEXCEL_INSTR_STATUS_LAST_HASH; + instr->instructions = SAFEXCEL_INSTR_INS_LAST | + SAFEXCEL_INSTR_DEST_HASH; + instr++; + + safexcel_instr_temp_aes_block(&instr); + + safexcel_instr_insert_digest(&instr, req->sess->digestlen); + + cdesc->additional_cdata_size = instr - start; +} + +static void +safexcel_set_token(struct safexcel_request *req) +{ + const struct crypto_session_params *csp; + struct safexcel_cmd_descr *cdesc; + struct safexcel_instr *instr; + struct safexcel_softc *sc; + int ringidx; + + csp = crypto_get_params(req->crp->crp_session); + cdesc = req->cdesc; + sc = req->sc; + ringidx = req->sess->ringidx; + + safexcel_set_command(req, cdesc); + + /* + * For keyless hash operations, the token instructions can be embedded + * in the token itself. Otherwise we use an additional token descriptor + * and the embedded instruction space is used to store the IV. + */ + if (csp->csp_cipher_alg == 0 && + csp->csp_auth_alg != CRYPTO_AES_NIST_GMAC) { + instr = (void *)cdesc->control_data.token; + } else { + instr = (void *)(sc->sc_ring[ringidx].dma_atok.vaddr + + sc->sc_config.atok_offset * + (cdesc - sc->sc_ring[ringidx].cdr.desc)); + cdesc->control_data.options |= SAFEXCEL_OPTION_4_TOKEN_IV_CMD; + } + + switch (csp->csp_cipher_alg) { + case CRYPTO_AES_NIST_GCM_16: + safexcel_instr_gcm(req, instr, cdesc); + break; + case CRYPTO_AES_CCM_16: + safexcel_instr_ccm(req, instr, cdesc); + break; + case CRYPTO_AES_XTS: + memcpy(cdesc->control_data.token, req->iv, AES_XTS_IV_LEN); + memset(cdesc->control_data.token + + AES_XTS_IV_LEN / sizeof(uint32_t), 0, AES_XTS_IV_LEN); + + safexcel_instr_cipher(req, instr, cdesc); + break; + case CRYPTO_AES_CBC: + case CRYPTO_AES_ICM: + memcpy(cdesc->control_data.token, req->iv, AES_BLOCK_LEN); + if (csp->csp_auth_alg != 0) + safexcel_instr_eta(req, instr, cdesc); + else + safexcel_instr_cipher(req, instr, cdesc); + break; + default: + switch (csp->csp_auth_alg) { + case CRYPTO_SHA1: + case CRYPTO_SHA1_HMAC: + case CRYPTO_SHA2_224: + case CRYPTO_SHA2_224_HMAC: + case CRYPTO_SHA2_256: + case CRYPTO_SHA2_256_HMAC: + case CRYPTO_SHA2_384: + case CRYPTO_SHA2_384_HMAC: + case CRYPTO_SHA2_512: + case CRYPTO_SHA2_512_HMAC: + safexcel_instr_sha_hash(req, instr); + break; + case CRYPTO_AES_NIST_GMAC: + safexcel_instr_gmac(req, instr, cdesc); + break; + default: + panic("unhandled auth request %d", csp->csp_auth_alg); + } + break; + } +} + +static struct safexcel_res_descr * +safexcel_res_descr_add(struct safexcel_ring *ring, bool first, bool last, + bus_addr_t data, uint32_t len) +{ + struct safexcel_res_descr *rdesc; + struct safexcel_res_descr_ring *rring; + + mtx_assert(&ring->mtx, MA_OWNED); + + rring = &ring->rdr; + if ((rring->write + 1) % SAFEXCEL_RING_SIZE == rring->read) + return (NULL); + + rdesc = &rring->desc[rring->write]; + rring->write = (rring->write + 1) % SAFEXCEL_RING_SIZE; + + rdesc->particle_size = len; + rdesc->rsvd0 = 0; + rdesc->descriptor_overflow = 0; + rdesc->buffer_overflow = 0; + rdesc->last_seg = last; + rdesc->first_seg = first; + rdesc->result_size = + sizeof(struct safexcel_res_data) / sizeof(uint32_t); + rdesc->rsvd1 = 0; + rdesc->data_lo = SAFEXCEL_ADDR_LO(data); + rdesc->data_hi = SAFEXCEL_ADDR_HI(data); + + if (first) { + rdesc->result_data.packet_length = 0; + rdesc->result_data.error_code = 0; + } + + return (rdesc); +} + +static struct safexcel_cmd_descr * +safexcel_cmd_descr_add(struct safexcel_ring *ring, bool first, bool last, + bus_addr_t data, uint32_t seglen, uint32_t reqlen, bus_addr_t context) +{ + struct safexcel_cmd_descr *cdesc; + struct safexcel_cmd_descr_ring *cring; + + KASSERT(full_data_len <= SAFEXCEL_MAX_REQUEST_SIZE, + ("%s: request length %u too long", __func__, full_data_len)); + mtx_assert(&ring->mtx, MA_OWNED); + + cring = &ring->cdr; + if ((cring->write + 1) % SAFEXCEL_RING_SIZE == cring->read) + return (NULL); + + cdesc = &cring->desc[cring->write]; + cring->write = (cring->write + 1) % SAFEXCEL_RING_SIZE; + + cdesc->particle_size = seglen; + cdesc->rsvd0 = 0; + cdesc->last_seg = last; + cdesc->first_seg = first; + cdesc->additional_cdata_size = 0; + cdesc->rsvd1 = 0; + cdesc->data_lo = SAFEXCEL_ADDR_LO(data); + cdesc->data_hi = SAFEXCEL_ADDR_HI(data); + if (first) { + cdesc->control_data.packet_length = reqlen; + cdesc->control_data.options = SAFEXCEL_OPTION_IP | + SAFEXCEL_OPTION_CP | SAFEXCEL_OPTION_CTX_CTRL_IN_CMD | + SAFEXCEL_OPTION_RC_AUTO; + cdesc->control_data.type = SAFEXCEL_TOKEN_TYPE_BYPASS; + cdesc->control_data.context_lo = SAFEXCEL_ADDR_LO(context) | + SAFEXCEL_CONTEXT_SMALL; + cdesc->control_data.context_hi = SAFEXCEL_ADDR_HI(context); + } + + return (cdesc); +} + +static void +safexcel_cmd_descr_rollback(struct safexcel_ring *ring, int count) +{ + struct safexcel_cmd_descr_ring *cring; + + mtx_assert(&ring->mtx, MA_OWNED); + + cring = &ring->cdr; + cring->write -= count; + if (cring->write < 0) + cring->write += SAFEXCEL_RING_SIZE; +} + +static void +safexcel_res_descr_rollback(struct safexcel_ring *ring, int count) +{ + struct safexcel_res_descr_ring *rring; + + mtx_assert(&ring->mtx, MA_OWNED); + + rring = &ring->rdr; + rring->write -= count; + if (rring->write < 0) + rring->write += SAFEXCEL_RING_SIZE; +} + +static void +safexcel_append_segs(bus_dma_segment_t *segs, int nseg, struct sglist *sg, + int start, int len) +{ + bus_dma_segment_t *seg; + size_t seglen; + int error, i; + + for (i = 0; i < nseg && len > 0; i++) { + seg = &segs[i]; + + if (seg->ds_len <= start) { + start -= seg->ds_len; + continue; + } + + seglen = MIN(len, seg->ds_len - start); + error = sglist_append_phys(sg, seg->ds_addr + start, seglen); + if (error != 0) + panic("%s: ran out of segments: %d", __func__, error); + len -= seglen; + start = 0; + } +} + +static void +safexcel_create_chain_cb(void *arg, bus_dma_segment_t *segs, int nseg, + int error) +{ + const struct crypto_session_params *csp; + struct cryptop *crp; + struct safexcel_cmd_descr *cdesc; + struct safexcel_request *req; + struct safexcel_ring *ring; + struct safexcel_session *sess; + struct sglist *sg; + size_t inlen; + int i; + bool first, last; + + req = arg; + if (error != 0) { + req->error = error; + return; + } + + crp = req->crp; + csp = crypto_get_params(crp->crp_session); + sess = req->sess; + ring = &req->sc->sc_ring[sess->ringidx]; + + mtx_assert(&ring->mtx, MA_OWNED); + + /* + * Set up descriptors for input and output data. + * + * The processing engine programs require that any AAD comes first, + * followed by the cipher plaintext, followed by the digest. Some + * consumers place the digest first in the input buffer, in which case + * we have to create an extra descriptor. + * + * As an optimization, unmodified data is not passed to the output + * stream. + */ + sglist_reset(ring->cmd_data); + sglist_reset(ring->res_data); + if (crp->crp_aad_length != 0) { + safexcel_append_segs(segs, nseg, ring->cmd_data, + crp->crp_aad_start, crp->crp_aad_length); + } + safexcel_append_segs(segs, nseg, ring->cmd_data, + crp->crp_payload_start, crp->crp_payload_length); + if (csp->csp_cipher_alg != 0) { + safexcel_append_segs(segs, nseg, ring->res_data, + crp->crp_payload_start, crp->crp_payload_length); + } + if (sess->digestlen > 0) { + if ((crp->crp_op & CRYPTO_OP_VERIFY_DIGEST) != 0) { + safexcel_append_segs(segs, nseg, ring->cmd_data, + crp->crp_digest_start, sess->digestlen); + } else { + safexcel_append_segs(segs, nseg, ring->res_data, + crp->crp_digest_start, sess->digestlen); + } + } + + sg = ring->cmd_data; + if (sg->sg_nseg == 0) { + /* + * Fake a segment for the command descriptor if the input has + * length zero. The EIP97 apparently does not handle + * zero-length packets properly since subsequent requests return + * bogus errors, so provide a dummy segment using the context + * descriptor. + */ + (void)sglist_append_phys(sg, req->ctx.paddr, 1); + } + for (i = 0, inlen = 0; i < sg->sg_nseg; i++) + inlen += sg->sg_segs[i].ss_len; + for (i = 0; i < sg->sg_nseg; i++) { + first = i == 0; + last = i == sg->sg_nseg - 1; + + cdesc = safexcel_cmd_descr_add(ring, first, last, + sg->sg_segs[i].ss_paddr, sg->sg_segs[i].ss_len, + (uint32_t)inlen, req->ctx.paddr); + if (cdesc == NULL) { + safexcel_cmd_descr_rollback(ring, i); + req->error = EAGAIN; + return; + } + if (i == 0) + req->cdesc = cdesc; + } + req->cdescs = sg->sg_nseg; + + sg = ring->res_data; + if (sg->sg_nseg == 0) { + /* + * We need a result descriptor even if the output stream will be + * empty, for example when verifying an AAD digest. + */ + sg->sg_segs[0].ss_paddr = 0; + sg->sg_segs[0].ss_len = 0; + sg->sg_nseg = 1; + } + for (i = 0; i < sg->sg_nseg; i++) { + first = i == 0; + last = i == sg->sg_nseg - 1; + + if (safexcel_res_descr_add(ring, first, last, + sg->sg_segs[i].ss_paddr, sg->sg_segs[i].ss_len) == NULL) { + safexcel_cmd_descr_rollback(ring, + ring->cmd_data->sg_nseg); + safexcel_res_descr_rollback(ring, i); + req->error = EAGAIN; + return; + } + } + req->rdescs = sg->sg_nseg; +} + +static int +safexcel_create_chain(struct safexcel_ring *ring, struct safexcel_request *req) +{ + int error; + + req->error = 0; + req->cdescs = req->rdescs = 0; + + error = bus_dmamap_load_crp(ring->data_dtag, req->dmap, req->crp, + safexcel_create_chain_cb, req, BUS_DMA_NOWAIT); + if (error == 0) + req->dmap_loaded = true; + + if (req->error != 0) + error = req->error; + + return (error); +} + +static bool +safexcel_probe_cipher(const struct crypto_session_params *csp) +{ + switch (csp->csp_cipher_alg) { + case CRYPTO_AES_CBC: + case CRYPTO_AES_ICM: + if (csp->csp_ivlen != AES_BLOCK_LEN) + return (false); + break; + case CRYPTO_AES_XTS: + if (csp->csp_ivlen != AES_XTS_IV_LEN) + return (false); + break; + default: + return (false); + } + + return (true); +} + +/* + * Determine whether the driver can implement a session with the requested + * parameters. + */ +static int +safexcel_probesession(device_t dev, const struct crypto_session_params *csp) +{ + switch (csp->csp_mode) { + case CSP_MODE_CIPHER: + if (!safexcel_probe_cipher(csp)) + return (EINVAL); + break; + case CSP_MODE_DIGEST: + switch (csp->csp_auth_alg) { + case CRYPTO_AES_NIST_GMAC: + if (csp->csp_ivlen != AES_GCM_IV_LEN) + return (EINVAL); + break; + case CRYPTO_SHA1: + case CRYPTO_SHA1_HMAC: + case CRYPTO_SHA2_224: + case CRYPTO_SHA2_224_HMAC: + case CRYPTO_SHA2_256: + case CRYPTO_SHA2_256_HMAC: + case CRYPTO_SHA2_384: + case CRYPTO_SHA2_384_HMAC: + case CRYPTO_SHA2_512: + case CRYPTO_SHA2_512_HMAC: + break; + default: + return (EINVAL); + } + break; + case CSP_MODE_AEAD: + switch (csp->csp_cipher_alg) { + case CRYPTO_AES_NIST_GCM_16: + if (csp->csp_ivlen != AES_GCM_IV_LEN) + return (EINVAL); + break; + case CRYPTO_AES_CCM_16: + if (csp->csp_ivlen != AES_CCM_IV_LEN) + return (EINVAL); + break; + default: + return (EINVAL); + } + break; + case CSP_MODE_ETA: + if (!safexcel_probe_cipher(csp)) + return (EINVAL); + switch (csp->csp_cipher_alg) { + case CRYPTO_AES_CBC: + case CRYPTO_AES_ICM: + /* + * The EIP-97 does not support combining AES-XTS with + * hash operations. + */ + if (csp->csp_auth_alg != CRYPTO_SHA1_HMAC && + csp->csp_auth_alg != CRYPTO_SHA2_224_HMAC && + csp->csp_auth_alg != CRYPTO_SHA2_256_HMAC && + csp->csp_auth_alg != CRYPTO_SHA2_384_HMAC && + csp->csp_auth_alg != CRYPTO_SHA2_512_HMAC) + return (EINVAL); + break; + default: + return (EINVAL); + } + break; + default: + return (EINVAL); + } + + return (CRYPTODEV_PROBE_HARDWARE); +} + +/* + * Pre-compute the hash key used in GHASH, which is a block of zeroes encrypted + * using the cipher key. + */ +static void +safexcel_setkey_ghash(struct safexcel_session *sess, const uint8_t *key, + int klen) +{ + uint32_t ks[4 * (RIJNDAEL_MAXNR + 1)]; + uint8_t zeros[AES_BLOCK_LEN]; + int i, rounds; + + memset(zeros, 0, sizeof(zeros)); + + rounds = rijndaelKeySetupEnc(ks, key, klen * NBBY); + rijndaelEncrypt(ks, rounds, zeros, (uint8_t *)sess->ghash_key); + for (i = 0; i < GMAC_BLOCK_LEN / sizeof(uint32_t); i++) + sess->ghash_key[i] = htobe32(sess->ghash_key[i]); + + explicit_bzero(ks, sizeof(ks)); +} + +/* + * Pre-compute the combined CBC-MAC key, which consists of three keys K1, K2, K3 + * in the hardware implementation. K1 is the cipher key and comes last in the + * buffer since K2 and K3 have a fixed size of AES_BLOCK_LEN. For now XCBC-MAC + * is not implemented so K2 and K3 are fixed. + */ +static void +safexcel_setkey_xcbcmac(struct safexcel_session *sess, const uint8_t *key, + int klen) +{ + int i, off; + + memset(sess->xcbc_key, 0, sizeof(sess->xcbc_key)); + off = 2 * AES_BLOCK_LEN / sizeof(uint32_t); + for (i = 0; i < klen / sizeof(uint32_t); i++, key += 4) + sess->xcbc_key[i + off] = htobe32(le32dec(key)); +} + +static void +safexcel_setkey_hmac_digest(struct auth_hash *ahash, union authctx *ctx, + char *buf) +{ + int hashwords, i; + + switch (ahash->type) { + case CRYPTO_SHA1_HMAC: + hashwords = ahash->hashsize / sizeof(uint32_t); + for (i = 0; i < hashwords; i++) + ((uint32_t *)buf)[i] = htobe32(ctx->sha1ctx.h.b32[i]); + break; + case CRYPTO_SHA2_224_HMAC: + hashwords = auth_hash_hmac_sha2_256.hashsize / sizeof(uint32_t); + for (i = 0; i < hashwords; i++) + ((uint32_t *)buf)[i] = htobe32(ctx->sha224ctx.state[i]); + break; + case CRYPTO_SHA2_256_HMAC: + hashwords = ahash->hashsize / sizeof(uint32_t); + for (i = 0; i < hashwords; i++) + ((uint32_t *)buf)[i] = htobe32(ctx->sha256ctx.state[i]); + break; + case CRYPTO_SHA2_384_HMAC: + hashwords = auth_hash_hmac_sha2_512.hashsize / sizeof(uint64_t); + for (i = 0; i < hashwords; i++) + ((uint64_t *)buf)[i] = htobe64(ctx->sha384ctx.state[i]); + break; + case CRYPTO_SHA2_512_HMAC: + hashwords = ahash->hashsize / sizeof(uint64_t); + for (i = 0; i < hashwords; i++) + ((uint64_t *)buf)[i] = htobe64(ctx->sha512ctx.state[i]); + break; + } +} + +/* + * Pre-compute the inner and outer digests used in the HMAC algorithm. + */ +static void +safexcel_setkey_hmac(const struct crypto_session_params *csp, + struct safexcel_session *sess, const uint8_t *key, int klen) +{ + union authctx ctx; + struct auth_hash *ahash; + + ahash = crypto_auth_hash(csp); + hmac_init_ipad(ahash, key, klen, &ctx); + safexcel_setkey_hmac_digest(ahash, &ctx, sess->hmac_ipad); + hmac_init_opad(ahash, key, klen, &ctx); + safexcel_setkey_hmac_digest(ahash, &ctx, sess->hmac_opad); + explicit_bzero(&ctx, ahash->ctxsize); +} + +static void +safexcel_setkey_xts(struct safexcel_session *sess, const uint8_t *key, int klen) +{ + memcpy(sess->tweak_key, key + klen / 2, klen / 2); +} + +static void +safexcel_setkey(struct safexcel_session *sess, + const struct crypto_session_params *csp, struct cryptop *crp) +{ + const uint8_t *akey, *ckey; + int aklen, cklen; + + aklen = csp->csp_auth_klen; + cklen = csp->csp_cipher_klen; + akey = ckey = NULL; + if (crp != NULL) { + akey = crp->crp_auth_key; + ckey = crp->crp_cipher_key; + } + if (akey == NULL) + akey = csp->csp_auth_key; + if (ckey == NULL) + ckey = csp->csp_cipher_key; + + sess->klen = cklen; + switch (csp->csp_cipher_alg) { + case CRYPTO_AES_NIST_GCM_16: + safexcel_setkey_ghash(sess, ckey, cklen); + break; + case CRYPTO_AES_CCM_16: + safexcel_setkey_xcbcmac(sess, ckey, cklen); + break; + case CRYPTO_AES_XTS: + safexcel_setkey_xts(sess, ckey, cklen); + sess->klen /= 2; + break; + } + + switch (csp->csp_auth_alg) { + case CRYPTO_SHA1_HMAC: + case CRYPTO_SHA2_224_HMAC: + case CRYPTO_SHA2_256_HMAC: + case CRYPTO_SHA2_384_HMAC: + case CRYPTO_SHA2_512_HMAC: + safexcel_setkey_hmac(csp, sess, akey, aklen); + break; + case CRYPTO_AES_NIST_GMAC: + sess->klen = aklen; + safexcel_setkey_ghash(sess, akey, aklen); + break; + } +} + +static uint32_t +safexcel_aes_algid(int keylen) +{ + switch (keylen) { + case 16: + return (SAFEXCEL_CONTROL0_CRYPTO_ALG_AES128); + case 24: + return (SAFEXCEL_CONTROL0_CRYPTO_ALG_AES192); + case 32: + return (SAFEXCEL_CONTROL0_CRYPTO_ALG_AES256); + default: + panic("invalid AES key length %d", keylen); + } +} + +static uint32_t +safexcel_aes_ccm_hashid(int keylen) +{ + switch (keylen) { + case 16: + return (SAFEXCEL_CONTROL0_HASH_ALG_XCBC128); + case 24: + return (SAFEXCEL_CONTROL0_HASH_ALG_XCBC192); + case 32: + return (SAFEXCEL_CONTROL0_HASH_ALG_XCBC256); + default: + panic("invalid AES key length %d", keylen); + } +} + +static uint32_t +safexcel_sha_hashid(int alg) +{ + switch (alg) { + case CRYPTO_SHA1: + case CRYPTO_SHA1_HMAC: + return (SAFEXCEL_CONTROL0_HASH_ALG_SHA1); + case CRYPTO_SHA2_224: + case CRYPTO_SHA2_224_HMAC: + return (SAFEXCEL_CONTROL0_HASH_ALG_SHA224); + case CRYPTO_SHA2_256: + case CRYPTO_SHA2_256_HMAC: + return (SAFEXCEL_CONTROL0_HASH_ALG_SHA256); + case CRYPTO_SHA2_384: + case CRYPTO_SHA2_384_HMAC: + return (SAFEXCEL_CONTROL0_HASH_ALG_SHA384); + case CRYPTO_SHA2_512: + case CRYPTO_SHA2_512_HMAC: + return (SAFEXCEL_CONTROL0_HASH_ALG_SHA512); + default: + __assert_unreachable(); + } +} + +static int +safexcel_sha_hashlen(int alg) +{ + switch (alg) { + case CRYPTO_SHA1: + case CRYPTO_SHA1_HMAC: + return (SHA1_HASH_LEN); + case CRYPTO_SHA2_224: + case CRYPTO_SHA2_224_HMAC: + return (SHA2_224_HASH_LEN); + case CRYPTO_SHA2_256: + case CRYPTO_SHA2_256_HMAC: + return (SHA2_256_HASH_LEN); + case CRYPTO_SHA2_384: + case CRYPTO_SHA2_384_HMAC: + return (SHA2_384_HASH_LEN); + case CRYPTO_SHA2_512: + case CRYPTO_SHA2_512_HMAC: + return (SHA2_512_HASH_LEN); + default: + __assert_unreachable(); + } +} + +static int +safexcel_sha_statelen(int alg) +{ + switch (alg) { + case CRYPTO_SHA1: + case CRYPTO_SHA1_HMAC: + return (SHA1_HASH_LEN); + case CRYPTO_SHA2_224: + case CRYPTO_SHA2_224_HMAC: + case CRYPTO_SHA2_256: + case CRYPTO_SHA2_256_HMAC: + return (SHA2_256_HASH_LEN); + case CRYPTO_SHA2_384: + case CRYPTO_SHA2_384_HMAC: + case CRYPTO_SHA2_512: + case CRYPTO_SHA2_512_HMAC: + return (SHA2_512_HASH_LEN); + default: + __assert_unreachable(); + } +} + +static int +safexcel_newsession(device_t dev, crypto_session_t cses, + const struct crypto_session_params *csp) +{ + struct safexcel_session *sess; + struct safexcel_softc *sc; + + sc = device_get_softc(dev); + sess = crypto_get_driver_session(cses); + + switch (csp->csp_auth_alg) { + case CRYPTO_SHA1: + case CRYPTO_SHA2_224: + case CRYPTO_SHA2_256: + case CRYPTO_SHA2_384: + case CRYPTO_SHA2_512: + sess->digest = SAFEXCEL_CONTROL0_DIGEST_PRECOMPUTED; + sess->hash = safexcel_sha_hashid(csp->csp_auth_alg); + sess->digestlen = safexcel_sha_hashlen(csp->csp_auth_alg); + sess->statelen = safexcel_sha_statelen(csp->csp_auth_alg); + break; + case CRYPTO_SHA1_HMAC: + case CRYPTO_SHA2_224_HMAC: + case CRYPTO_SHA2_256_HMAC: + case CRYPTO_SHA2_384_HMAC: + case CRYPTO_SHA2_512_HMAC: + sess->digest = SAFEXCEL_CONTROL0_DIGEST_HMAC; + sess->hash = safexcel_sha_hashid(csp->csp_auth_alg); + sess->digestlen = safexcel_sha_hashlen(csp->csp_auth_alg); + sess->statelen = safexcel_sha_statelen(csp->csp_auth_alg); + break; + case CRYPTO_AES_NIST_GMAC: + sess->digest = SAFEXCEL_CONTROL0_DIGEST_GMAC; + sess->digestlen = GMAC_DIGEST_LEN; + sess->hash = SAFEXCEL_CONTROL0_HASH_ALG_GHASH; + sess->alg = safexcel_aes_algid(csp->csp_auth_klen); + sess->mode = SAFEXCEL_CONTROL1_CRYPTO_MODE_GCM; + break; + } + + switch (csp->csp_cipher_alg) { + case CRYPTO_AES_NIST_GCM_16: + sess->digest = SAFEXCEL_CONTROL0_DIGEST_GMAC; + sess->digestlen = GMAC_DIGEST_LEN; + sess->hash = SAFEXCEL_CONTROL0_HASH_ALG_GHASH; + sess->alg = safexcel_aes_algid(csp->csp_cipher_klen); + sess->mode = SAFEXCEL_CONTROL1_CRYPTO_MODE_GCM; + break; + case CRYPTO_AES_CCM_16: + sess->hash = safexcel_aes_ccm_hashid(csp->csp_cipher_klen); + sess->digest = SAFEXCEL_CONTROL0_DIGEST_CCM; + sess->digestlen = CCM_CBC_MAX_DIGEST_LEN; + sess->alg = safexcel_aes_algid(csp->csp_cipher_klen); + sess->mode = SAFEXCEL_CONTROL1_CRYPTO_MODE_CCM; + break; + case CRYPTO_AES_CBC: + sess->alg = safexcel_aes_algid(csp->csp_cipher_klen); + sess->mode = SAFEXCEL_CONTROL1_CRYPTO_MODE_CBC; + break; + case CRYPTO_AES_ICM: + sess->alg = safexcel_aes_algid(csp->csp_cipher_klen); + sess->mode = SAFEXCEL_CONTROL1_CRYPTO_MODE_CTR; + break; + case CRYPTO_AES_XTS: + sess->alg = safexcel_aes_algid(csp->csp_cipher_klen / 2); + sess->mode = SAFEXCEL_CONTROL1_CRYPTO_MODE_XTS; + break; + } + + if (csp->csp_auth_mlen != 0) + sess->digestlen = csp->csp_auth_mlen; + + safexcel_setkey(sess, csp, NULL); + + /* Bind each session to a fixed ring to minimize lock contention. */ + sess->ringidx = atomic_fetchadd_int(&sc->sc_ringidx, 1); + sess->ringidx %= sc->sc_config.rings; + + return (0); +} + +static int +safexcel_process(device_t dev, struct cryptop *crp, int hint) +{ + const struct crypto_session_params *csp; + struct safexcel_request *req; + struct safexcel_ring *ring; + struct safexcel_session *sess; + struct safexcel_softc *sc; + int error; + + sc = device_get_softc(dev); + sess = crypto_get_driver_session(crp->crp_session); + csp = crypto_get_params(crp->crp_session); + + if (__predict_false(crypto_buffer_len(&crp->crp_buf) > + SAFEXCEL_MAX_REQUEST_SIZE)) { + crp->crp_etype = E2BIG; + crypto_done(crp); + return (0); + } + + if (crp->crp_cipher_key != NULL || crp->crp_auth_key != NULL) + safexcel_setkey(sess, csp, crp); + + ring = &sc->sc_ring[sess->ringidx]; + mtx_lock(&ring->mtx); + req = safexcel_alloc_request(sc, ring); + if (__predict_false(req == NULL)) { + mtx_lock(&sc->sc_mtx); + mtx_unlock(&ring->mtx); + sc->sc_blocked = CRYPTO_SYMQ; + mtx_unlock(&sc->sc_mtx); + return (ERESTART); + } + + req->crp = crp; + req->sess = sess; + + crypto_read_iv(crp, req->iv); + + error = safexcel_create_chain(ring, req); + if (__predict_false(error != 0)) { + safexcel_free_request(ring, req); + mtx_unlock(&ring->mtx); + crp->crp_etype = error; + crypto_done(crp); + return (0); + } + + safexcel_set_token(req); + + bus_dmamap_sync(ring->data_dtag, req->dmap, + BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); + bus_dmamap_sync(req->ctx.tag, req->ctx.map, + BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); + bus_dmamap_sync(ring->cdr.dma.tag, ring->cdr.dma.map, + BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); + bus_dmamap_sync(ring->dma_atok.tag, ring->dma_atok.map, + BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); + bus_dmamap_sync(ring->rdr.dma.tag, ring->rdr.dma.map, + BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); + + safexcel_enqueue_request(sc, ring, req); + + if ((hint & CRYPTO_HINT_MORE) == 0) + safexcel_execute(sc, ring, req); + mtx_unlock(&ring->mtx); + + return (0); +} + +static device_method_t safexcel_methods[] = { + /* Device interface */ + DEVMETHOD(device_probe, safexcel_probe), + DEVMETHOD(device_attach, safexcel_attach), + DEVMETHOD(device_detach, safexcel_detach), + + /* Cryptodev interface */ + DEVMETHOD(cryptodev_probesession, safexcel_probesession), + DEVMETHOD(cryptodev_newsession, safexcel_newsession), + DEVMETHOD(cryptodev_process, safexcel_process), + + DEVMETHOD_END +}; + +static devclass_t safexcel_devclass; + +static driver_t safexcel_driver = { + .name = "safexcel", + .methods = safexcel_methods, + .size = sizeof(struct safexcel_softc), +}; + +DRIVER_MODULE(safexcel, simplebus, safexcel_driver, safexcel_devclass, 0, 0); +MODULE_VERSION(safexcel, 1); +MODULE_DEPEND(safexcel, crypto, 1, 1, 1); Property changes on: head/sys/dev/safexcel/safexcel.c ___________________________________________________________________ Added: svn:keywords ## -0,0 +1 ## +FreeBSD=%H \ No newline at end of property Index: head/sys/dev/safexcel/safexcel_reg.h =================================================================== --- head/sys/dev/safexcel/safexcel_reg.h (nonexistent) +++ head/sys/dev/safexcel/safexcel_reg.h (revision 363180) @@ -0,0 +1,457 @@ +/*- + * SPDX-License-Identifier: BSD-2-Clause-FreeBSD + * + * Copyright (c) 2020 Rubicon Communications, LLC (Netgate) + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * $FreeBSD$ + */ + +#ifndef _SAFEXCEL_REGS_H_ +#define _SAFEXCEL_REGS_H_ + +#define SAFEXCEL_HIA_VERSION_LE 0x35ca +#define SAFEXCEL_HIA_VERSION_BE 0xca35 +#define EIP201_VERSION_LE 0x36c9 +#define SAFEXCEL_REG_LO16(_reg) ((_reg) & 0xffff) +#define SAFEXCEL_REG_HI16(_reg) (((_reg) >> 16) & 0xffff) + + +/* HIA, Command Descriptor Ring Manager */ +#define CDR_BASE_ADDR_LO(x) (0x0 + ((x) << 12)) +#define CDR_BASE_ADDR_HI(x) (0x4 + ((x) << 12)) +#define CDR_DATA_BASE_ADDR_LO(x) (0x8 + ((x) << 12)) +#define CDR_DATA_BASE_ADDR_HI(x) (0xC + ((x) << 12)) +#define CDR_ACD_BASE_ADDR_LO(x) (0x10 + ((x) << 12)) +#define CDR_ACD_BASE_ADDR_HI(x) (0x14 + ((x) << 12)) +#define CDR_RING_SIZE(x) (0x18 + ((x) << 12)) +#define CDR_DESC_SIZE(x) (0x1C + ((x) << 12)) +#define CDR_CFG(x) (0x20 + ((x) << 12)) +#define CDR_DMA_CFG(x) (0x24 + ((x) << 12)) +#define CDR_THR(x) (0x28 + ((x) << 12)) +#define CDR_PREP_COUNT(x) (0x2C + ((x) << 12)) +#define CDR_PROC_COUNT(x) (0x30 + ((x) << 12)) +#define CDR_PREP_PNTR(x) (0x34 + ((x) << 12)) +#define CDR_PROC_PNTR(x) (0x38 + ((x) << 12)) +#define CDR_STAT(x) (0x3C + ((x) << 12)) + +/* HIA, Result Descriptor Ring Manager */ +#define RDR_BASE_ADDR_LO(x) (0x800 + ((x) << 12)) +#define RDR_BASE_ADDR_HI(x) (0x804 + ((x) << 12)) +#define RDR_DATA_BASE_ADDR_LO(x) (0x808 + ((x) << 12)) +#define RDR_DATA_BASE_ADDR_HI(x) (0x80C + ((x) << 12)) +#define RDR_ACD_BASE_ADDR_LO(x) (0x810 + ((x) << 12)) +#define RDR_ACD_BASE_ADDR_HI(x) (0x814 + ((x) << 12)) +#define RDR_RING_SIZE(x) (0x818 + ((x) << 12)) +#define RDR_DESC_SIZE(x) (0x81C + ((x) << 12)) +#define RDR_CFG(x) (0x820 + ((x) << 12)) +#define RDR_DMA_CFG(x) (0x824 + ((x) << 12)) +#define RDR_THR(x) (0x828 + ((x) << 12)) +#define RDR_PREP_COUNT(x) (0x82C + ((x) << 12)) +#define RDR_PROC_COUNT(x) (0x830 + ((x) << 12)) +#define RDR_PREP_PNTR(x) (0x834 + ((x) << 12)) +#define RDR_PROC_PNTR(x) (0x838 + ((x) << 12)) +#define RDR_STAT(x) (0x83C + ((x) << 12)) + +/* HIA, Ring AIC */ +#define AIC_POL_CTRL(x) (0xE000 - ((x) << 12)) +#define AIC_TYPE_CTRL(x) (0xE004 - ((x) << 12)) +#define AIC_ENABLE_CTRL(x) (0xE008 - ((x) << 12)) +#define AIC_RAW_STAL(x) (0xE00C - ((x) << 12)) +#define AIC_ENABLE_SET(x) (0xE00C - ((x) << 12)) +#define AIC_ENABLED_STAT(x) (0xE010 - ((x) << 12)) +#define AIC_ACK(x) (0xE010 - ((x) << 12)) +#define AIC_ENABLE_CLR(x) (0xE014 - ((x) << 12)) +#define AIC_OPTIONS(x) (0xE018 - ((x) << 12)) +#define AIC_VERSION(x) (0xE01C - ((x) << 12)) + +/* HIA, Global AIC */ +#define AIC_G_POL_CTRL 0xF800 +#define AIC_G_TYPE_CTRL 0xF804 +#define AIC_G_ENABLE_CTRL 0xF808 +#define AIC_G_RAW_STAT 0xF80C +#define AIC_G_ENABLE_SET 0xF80C +#define AIC_G_ENABLED_STAT 0xF810 +#define AIC_G_ACK 0xF810 +#define AIC_G_ENABLE_CLR 0xF814 +#define AIC_G_OPTIONS 0xF818 +#define AIC_G_VERSION 0xF81C + +/* HIA, Data Fetch Engine */ +#define DFE_CFG 0xF000 +#define DFE_PRIO_0 0xF010 +#define DFE_PRIO_1 0xF014 +#define DFE_PRIO_2 0xF018 +#define DFE_PRIO_3 0xF01C + +/* HIA, Data Fetch Engine access monitoring for CDR */ +#define DFE_RING_REGION_LO(x) (0xF080 + ((x) << 3)) +#define DFE_RING_REGION_HI(x) (0xF084 + ((x) << 3)) + +/* HIA, Data Fetch Engine thread control and status for thread */ +#define DFE_THR_CTRL 0xF200 +#define DFE_THR_STAT 0xF204 +#define DFE_THR_DESC_CTRL 0xF208 +#define DFE_THR_DESC_DPTR_LO 0xF210 +#define DFE_THR_DESC_DPTR_HI 0xF214 +#define DFE_THR_DESC_ACDPTR_LO 0xF218 +#define DFE_THR_DESC_ACDPTR_HI 0xF21C + +/* HIA, Data Store Engine */ +#define DSE_CFG 0xF400 +#define DSE_PRIO_0 0xF410 +#define DSE_PRIO_1 0xF414 +#define DSE_PRIO_2 0xF418 +#define DSE_PRIO_3 0xF41C + +/* HIA, Data Store Engine access monitoring for RDR */ +#define DSE_RING_REGION_LO(x) (0xF480 + ((x) << 3)) +#define DSE_RING_REGION_HI(x) (0xF484 + ((x) << 3)) + +/* HIA, Data Store Engine thread control and status for thread */ +#define DSE_THR_CTRL 0xF600 +#define DSE_THR_STAT 0xF604 +#define DSE_THR_DESC_CTRL 0xF608 +#define DSE_THR_DESC_DPTR_LO 0xF610 +#define DSE_THR_DESC_DPTR_HI 0xF614 +#define DSE_THR_DESC_S_DPTR_LO 0xF618 +#define DSE_THR_DESC_S_DPTR_HI 0xF61C +#define DSE_THR_ERROR_STAT 0xF620 + +/* HIA Global */ +#define HIA_MST_CTRL 0xFFF4 +#define HIA_OPTIONS 0xFFF8 +#define HIA_VERSION 0xFFFC + +/* Processing Engine Input Side, Processing Engine */ +#define PE_IN_DBUF_THRESH 0x10000 +#define PE_IN_TBUF_THRESH 0x10100 + +/* Packet Engine Configuration / Status Registers */ +#define PE_TOKEN_CTRL_STAT 0x11000 +#define PE_FUNCTION_EN 0x11004 +#define PE_CONTEXT_CTRL 0x11008 +#define PE_INTERRUPT_CTRL_STAT 0x11010 +#define PE_CONTEXT_STAT 0x1100C +#define PE_OUT_TRANS_CTRL_STAT 0x11018 +#define PE_OUT_BUF_CTRL 0x1101C + +/* Packet Engine AIC */ +#define PE_EIP96_AIC_POL_CTRL 0x113C0 +#define PE_EIP96_AIC_TYPE_CTRL 0x113C4 +#define PE_EIP96_AIC_ENABLE_CTRL 0x113C8 +#define PE_EIP96_AIC_RAW_STAT 0x113CC +#define PE_EIP96_AIC_ENABLE_SET 0x113CC +#define PE_EIP96_AIC_ENABLED_STAT 0x113D0 +#define PE_EIP96_AIC_ACK 0x113D0 +#define PE_EIP96_AIC_ENABLE_CLR 0x113D4 +#define PE_EIP96_AIC_OPTIONS 0x113D8 +#define PE_EIP96_AIC_VERSION 0x113DC + +/* Packet Engine Options & Version Registers */ +#define PE_EIP96_OPTIONS 0x113F8 +#define PE_EIP96_VERSION 0x113FC + +#define SAFEXCEL_OPT + +/* Processing Engine Output Side */ +#define PE_OUT_DBUF_THRESH 0x11C00 +#define PE_OUT_TBUF_THRESH 0x11D00 + +/* Processing Engine Local AIC */ +#define PE_AIC_POL_CTRL 0x11F00 +#define PE_AIC_TYPE_CTRL 0x11F04 +#define PE_AIC_ENABLE_CTRL 0x11F08 +#define PE_AIC_RAW_STAT 0x11F0C +#define PE_AIC_ENABLE_SET 0x11F0C +#define PE_AIC_ENABLED_STAT 0x11F10 +#define PE_AIC_ENABLE_CLR 0x11F14 +#define PE_AIC_OPTIONS 0x11F18 +#define PE_AIC_VERSION 0x11F1C + +/* Processing Engine General Configuration and Version */ +#define PE_IN_FLIGHT 0x11FF0 +#define PE_OPTIONS 0x11FF8 +#define PE_VERSION 0x11FFC + +/* EIP-97 - Global */ +#define EIP97_CLOCK_STATE 0x1FFE4 +#define EIP97_FORCE_CLOCK_ON 0x1FFE8 +#define EIP97_FORCE_CLOCK_OFF 0x1FFEC +#define EIP97_MST_CTRL 0x1FFF4 +#define EIP97_OPTIONS 0x1FFF8 +#define EIP97_VERSION 0x1FFFC + +/* Register base offsets */ +#define SAFEXCEL_HIA_AIC(_sc) ((_sc)->sc_offsets.hia_aic) +#define SAFEXCEL_HIA_AIC_G(_sc) ((_sc)->sc_offsets.hia_aic_g) +#define SAFEXCEL_HIA_AIC_R(_sc) ((_sc)->sc_offsets.hia_aic_r) +#define SAFEXCEL_HIA_AIC_xDR(_sc) ((_sc)->sc_offsets.hia_aic_xdr) +#define SAFEXCEL_HIA_DFE(_sc) ((_sc)->sc_offsets.hia_dfe) +#define SAFEXCEL_HIA_DFE_THR(_sc) ((_sc)->sc_offsets.hia_dfe_thr) +#define SAFEXCEL_HIA_DSE(_sc) ((_sc)->sc_offsets.hia_dse) +#define SAFEXCEL_HIA_DSE_THR(_sc) ((_sc)->sc_offsets.hia_dse_thr) +#define SAFEXCEL_HIA_GEN_CFG(_sc) ((_sc)->sc_offsets.hia_gen_cfg) +#define SAFEXCEL_PE(_sc) ((_sc)->sc_offsets.pe) + +/* EIP197 base offsets */ +#define SAFEXCEL_EIP197_HIA_AIC_BASE 0x90000 +#define SAFEXCEL_EIP197_HIA_AIC_G_BASE 0x90000 +#define SAFEXCEL_EIP197_HIA_AIC_R_BASE 0x90800 +#define SAFEXCEL_EIP197_HIA_AIC_xDR_BASE 0x80000 +#define SAFEXCEL_EIP197_HIA_DFE_BASE 0x8c000 +#define SAFEXCEL_EIP197_HIA_DFE_THR_BASE 0x8c040 +#define SAFEXCEL_EIP197_HIA_DSE_BASE 0x8d000 +#define SAFEXCEL_EIP197_HIA_DSE_THR_BASE 0x8d040 +#define SAFEXCEL_EIP197_HIA_GEN_CFG_BASE 0xf0000 +#define SAFEXCEL_EIP197_PE_BASE 0xa0000 + +/* EIP97 base offsets */ +#define SAFEXCEL_EIP97_HIA_AIC_BASE 0x0 +#define SAFEXCEL_EIP97_HIA_AIC_G_BASE 0x0 +#define SAFEXCEL_EIP97_HIA_AIC_R_BASE 0x0 +#define SAFEXCEL_EIP97_HIA_AIC_xDR_BASE 0x0 +#define SAFEXCEL_EIP97_HIA_DFE_BASE 0xf000 +#define SAFEXCEL_EIP97_HIA_DFE_THR_BASE 0xf200 +#define SAFEXCEL_EIP97_HIA_DSE_BASE 0xf400 +#define SAFEXCEL_EIP97_HIA_DSE_THR_BASE 0xf600 +#define SAFEXCEL_EIP97_HIA_GEN_CFG_BASE 0x10000 +#define SAFEXCEL_EIP97_PE_BASE 0x10000 + +/* CDR/RDR register offsets */ +#define SAFEXCEL_HIA_xDR_OFF(priv, r) (SAFEXCEL_HIA_AIC_xDR(priv) + (r) * 0x1000) +#define SAFEXCEL_HIA_CDR(priv, r) (SAFEXCEL_HIA_xDR_OFF(priv, r)) +#define SAFEXCEL_HIA_RDR(priv, r) (SAFEXCEL_HIA_xDR_OFF(priv, r) + 0x800) +#define SAFEXCEL_HIA_xDR_RING_BASE_ADDR_LO 0x0000 +#define SAFEXCEL_HIA_xDR_RING_BASE_ADDR_HI 0x0004 +#define SAFEXCEL_HIA_xDR_RING_SIZE 0x0018 +#define SAFEXCEL_HIA_xDR_DESC_SIZE 0x001c +#define SAFEXCEL_HIA_xDR_CFG 0x0020 +#define SAFEXCEL_HIA_xDR_DMA_CFG 0x0024 +#define SAFEXCEL_HIA_xDR_THRESH 0x0028 +#define SAFEXCEL_HIA_xDR_PREP_COUNT 0x002c +#define SAFEXCEL_HIA_xDR_PROC_COUNT 0x0030 +#define SAFEXCEL_HIA_xDR_PREP_PNTR 0x0034 +#define SAFEXCEL_HIA_xDR_PROC_PNTR 0x0038 +#define SAFEXCEL_HIA_xDR_STAT 0x003c + +/* register offsets */ +#define SAFEXCEL_HIA_DFE_CFG(n) (0x000 + (128 * (n))) +#define SAFEXCEL_HIA_DFE_THR_CTRL(n) (0x000 + (128 * (n))) +#define SAFEXCEL_HIA_DFE_THR_STAT(n) (0x004 + (128 * (n))) +#define SAFEXCEL_HIA_DSE_CFG(n) (0x000 + (128 * (n))) +#define SAFEXCEL_HIA_DSE_THR_CTRL(n) (0x000 + (128 * (n))) +#define SAFEXCEL_HIA_DSE_THR_STAT(n) (0x004 + (128 * (n))) +#define SAFEXCEL_HIA_RA_PE_CTRL(n) (0x010 + (8 * (n))) +#define SAFEXCEL_HIA_RA_PE_STAT 0x0014 +#define SAFEXCEL_HIA_AIC_R_OFF(r) ((r) * 0x1000) +#define SAFEXCEL_HIA_AIC_R_ENABLE_CTRL(r) (0xe008 - SAFEXCEL_HIA_AIC_R_OFF(r)) +#define SAFEXCEL_HIA_AIC_R_ENABLED_STAT(r) (0xe010 - SAFEXCEL_HIA_AIC_R_OFF(r)) +#define SAFEXCEL_HIA_AIC_R_ACK(r) (0xe010 - SAFEXCEL_HIA_AIC_R_OFF(r)) +#define SAFEXCEL_HIA_AIC_R_ENABLE_CLR(r) (0xe014 - SAFEXCEL_HIA_AIC_R_OFF(r)) +#define SAFEXCEL_HIA_AIC_R_VERSION(r) (0xe01c - SAFEXCEL_HIA_AIC_R_OFF(r)) +#define SAFEXCEL_HIA_AIC_G_ENABLE_CTRL 0xf808 +#define SAFEXCEL_HIA_AIC_G_ENABLED_STAT 0xf810 +#define SAFEXCEL_HIA_AIC_G_ACK 0xf810 +#define SAFEXCEL_HIA_MST_CTRL 0xfff4 +#define SAFEXCEL_HIA_OPTIONS 0xfff8 +#define SAFEXCEL_HIA_VERSION 0xfffc +#define SAFEXCEL_PE_IN_DBUF_THRES(n) (0x0000 + (0x2000 * (n))) +#define SAFEXCEL_PE_IN_TBUF_THRES(n) (0x0100 + (0x2000 * (n))) +#define SAFEXCEL_PE_ICE_SCRATCH_RAM(x, n) ((0x800 + (x) * 4) + 0x2000 * (n)) +#define SAFEXCEL_PE_ICE_PUE_CTRL(n) (0xc80 + (0x2000 * (n))) +#define SAFEXCEL_PE_ICE_SCRATCH_CTRL 0x0d04 +#define SAFEXCEL_PE_ICE_FPP_CTRL(n) (0xd80 + (0x2000 * (n))) +#define SAFEXCEL_PE_ICE_RAM_CTRL(n) (0xff0 + (0x2000 * (n))) +#define SAFEXCEL_PE_EIP96_FUNCTION_EN(n) (0x1004 + (0x2000 * (n))) +#define SAFEXCEL_PE_EIP96_CONTEXT_CTRL(n) (0x1008 + (0x2000 * (n))) +#define SAFEXCEL_PE_EIP96_CONTEXT_STAT(n) (0x100c + (0x2000 * (n))) +#define SAFEXCEL_PE_EIP96_FUNCTION2_EN(n) (0x1030 + (0x2000 * (n))) +#define SAFEXCEL_PE_OUT_DBUF_THRES(n) (0x1c00 + (0x2000 * (n))) +#define SAFEXCEL_PE_OUT_TBUF_THRES(n) (0x1d00 + (0x2000 * (n))) + +/* EIP-197 Classification Engine */ + +/* Classification regs */ +#define SAFEXCEL_CS_RAM_CTRL 0xf7ff0 + +/* SAFEXCEL_HIA_xDR_DESC_SIZE */ +#define SAFEXCEL_xDR_DESC_MODE_64BIT (1U << 31) +#define SAFEXCEL_CDR_DESC_MODE_ADCP (1 << 30) +#define SAFEXCEL_xDR_DESC_xD_OFFSET 16 + +/* SAFEXCEL_DIA_xDR_CFG */ +#define SAFEXCEL_xDR_xD_FETCH_THRESH 16 + +/* SAFEXCEL_HIA_xDR_DMA_CFG */ +#define SAFEXCEL_HIA_xDR_WR_RES_BUF (1 << 22) +#define SAFEXCEL_HIA_xDR_WR_CTRL_BUF (1 << 23) +#define SAFEXCEL_HIA_xDR_WR_OWN_BUF (1 << 24) +#define SAFEXCEL_HIA_xDR_CFG_xD_PROT(n) (((n) & 0xf) << 4) +#define SAFEXCEL_HIA_xDR_CFG_DATA_PROT(n) (((n) & 0xf) << 12) +#define SAFEXCEL_HIA_xDR_CFG_ACD_PROT(n) (((n) & 0xf) << 20) +#define SAFEXCEL_HIA_xDR_CFG_WR_CACHE(n) (((n) & 0x7) << 25) +#define SAFEXCEL_HIA_xDR_CFG_RD_CACHE(n) (((n) & 0x7) << 29) + +/* SAFEXCEL_HIA_CDR_THRESH */ +#define SAFEXCEL_HIA_CDR_THRESH_PROC_PKT(n) ((n) & 0xffff) +#define SAFEXCEL_HIA_CDR_THRESH_PROC_MODE (1 << 22) +#define SAFEXCEL_HIA_CDR_THRESH_PKT_MODE (1 << 23) + /* x256 clk cycles */ +#define SAFEXCEL_HIA_CDR_THRESH_TIMEOUT(n) (((n) & 0xff) << 24) + +/* SAFEXCEL_HIA_RDR_THRESH */ +#define SAFEXCEL_HIA_RDR_THRESH_PROC_PKT(n) ((n) & 0xffff) +#define SAFEXCEL_HIA_RDR_THRESH_PKT_MODE (1 << 23) + /* x256 clk cycles */ +#define SAFEXCEL_HIA_RDR_THRESH_TIMEOUT(n) (((n) & 0xff) << 24) + +/* SAFEXCEL_HIA_xDR_PREP_COUNT */ +#define SAFEXCEL_xDR_PREP_CLR_COUNT (1U << 31) +#define SAFEXCEL_xDR_PREP_xD_COUNT_INCR_OFFSET 2 +#define SAFEXCEL_xDR_PREP_RD_COUNT_INCR_MASK 0x3fff + +/* SAFEXCEL_HIA_xDR_PROC_COUNT */ +#define SAFEXCEL_xDR_PROC_xD_PKT_OFFSET 24 +#define SAFEXCEL_xDR_PROC_xD_PKT_MASK 0x7f +#define SAFEXCEL_xDR_PROC_xD_COUNT(n) ((n) << 2) +#define SAFEXCEL_xDR_PROC_xD_PKT(n) \ + (((n) & SAFEXCEL_xDR_PROC_xD_PKT_MASK) << SAFEXCEL_xDR_PROC_xD_PKT_OFFSET) +#define SAFEXCEL_xDR_PROC_CLR_COUNT (1U << 31) + +/* SAFEXCEL_HIA_xDR_STAT */ +#define SAFEXCEL_xDR_DMA_ERR (1 << 0) +#define SAFEXCEL_xDR_PREP_CMD_THRES (1 << 1) +#define SAFEXCEL_xDR_ERR (1 << 2) +#define SAFEXCEL_xDR_THRESH (1 << 4) +#define SAFEXCEL_xDR_TIMEOUT (1 << 5) +#define SAFEXCEL_CDR_INTR_MASK 0x3f +#define SAFEXCEL_RDR_INTR_MASK 0xff + +#define SAFEXCEL_HIA_RA_PE_CTRL_RESET (1U << 31) +#define SAFEXCEL_HIA_RA_PE_CTRL_EN (1 << 30) + +/* Register offsets */ + +/* SAFEXCEL_HIA_DSE_THR_STAT */ +#define SAFEXCEL_DSE_THR_RDR_ID_MASK 0xf000 + +/* SAFEXCEL_HIA_OPTIONS */ +#define SAFEXCEL_OPT_ADDR_64 (1U << 31) +#define SAFEXCEL_OPT_TGT_ALIGN_OFFSET 28 +#define SAFEXCEL_OPT_TGT_ALIGN_MASK 0x70000000 +#define SAFEXCEL_xDR_HDW_OFFSET 25 +#define SAFEXCEL_xDR_HDW_MASK 0x6000000 +#define SAFEXCEL_N_RINGS_MASK 0xf +#define SAFEXCEL_N_PES_OFFSET 4 +#define SAFEXCEL_N_PES_MASK 0x1f0 +#define EIP97_N_PES_MASK 0x70 + +/* SAFEXCEL_HIA_AIC_R_ENABLE_CTRL */ +#define SAFEXCEL_CDR_IRQ(n) (1 << ((n) * 2)) +#define SAFEXCEL_RDR_IRQ(n) (1 << ((n) * 2 + 1)) + +/* SAFEXCEL_HIA_DFE/DSE_CFG */ +#define SAFEXCEL_HIA_DxE_CFG_MIN_DATA_SIZE(n) ((n) << 0) +#define SAFEXCEL_HIA_DxE_CFG_DATA_CACHE_CTRL(n) (((n) & 0x7) << 4) +#define SAFEXCEL_HIA_DxE_CFG_MAX_DATA_SIZE(n) ((n) << 8) +#define SAFEXCEL_HIA_DSE_CFG_ALLWAYS_BUFFERABLE 0xc000 +#define SAFEXCEL_HIA_DxE_CFG_MIN_CTRL_SIZE(n) ((n) << 16) +#define SAFEXCEL_HIA_DxE_CFG_CTRL_CACHE_CTRL(n) (((n) & 0x7) << 20) +#define SAFEXCEL_HIA_DxE_CFG_MAX_CTRL_SIZE(n) ((n) << 24) +#define SAFEXCEL_HIA_DFE_CFG_DIS_DEBUG 0xe0000000 +#define SAFEXCEL_HIA_DSE_CFG_EN_SINGLE_WR (1 << 29) +#define SAFEXCEL_HIA_DSE_CFG_DIS_DEBUG 0xc0000000 + +/* SAFEXCEL_HIA_DFE/DSE_THR_CTRL */ +#define SAFEXCEL_DxE_THR_CTRL_EN (1 << 30) +#define SAFEXCEL_DxE_THR_CTRL_RESET_PE (1U << 31) + +/* SAFEXCEL_HIA_AIC_G_ENABLED_STAT */ +#define SAFEXCEL_G_IRQ_DFE(n) (1 << ((n) << 1)) +#define SAFEXCEL_G_IRQ_DSE(n) (1 << (((n) << 1) + 1)) +#define SAFEXCEL_G_IRQ_RING (1 << 16) +#define SAFEXCEL_G_IRQ_PE(n) (1 << ((n) + 20)) + +/* SAFEXCEL_HIA_MST_CTRL */ +#define RD_CACHE_3BITS 0x5U +#define WR_CACHE_3BITS 0x3U +#define RD_CACHE_4BITS (RD_CACHE_3BITS << 1 | (1 << 0)) +#define WR_CACHE_4BITS (WR_CACHE_3BITS << 1 | (1 << 0)) +#define SAFEXCEL_MST_CTRL_RD_CACHE(n) (((n) & 0xf) << 0) +#define SAFEXCEL_MST_CTRL_WD_CACHE(n) (((n) & 0xf) << 4) +#define MST_CTRL_SUPPORT_PROT(n) (((n) & 0xf) << 12) +#define SAFEXCEL_MST_CTRL_BYTE_SWAP (1 << 24) +#define SAFEXCEL_MST_CTRL_NO_BYTE_SWAP (1 << 25) + +/* SAFEXCEL_PE_IN_DBUF/TBUF_THRES */ +#define SAFEXCEL_PE_IN_xBUF_THRES_MIN(n) ((n) << 8) +#define SAFEXCEL_PE_IN_xBUF_THRES_MAX(n) ((n) << 12) + +/* SAFEXCEL_PE_OUT_DBUF_THRES */ +#define SAFEXCEL_PE_OUT_DBUF_THRES_MIN(n) ((n) << 0) +#define SAFEXCEL_PE_OUT_DBUF_THRES_MAX(n) ((n) << 4) + +/* SAFEXCEL_HIA_AIC_G_ACK */ +#define SAFEXCEL_AIC_G_ACK_ALL_MASK 0xffffffff +#define SAFEXCEL_AIC_G_ACK_HIA_MASK 0x7ff00000 + +/* SAFEXCEL_HIA_AIC_R_ENABLE_CLR */ +#define SAFEXCEL_HIA_AIC_R_ENABLE_CLR_ALL_MASK 0xffffffff + +/* SAFEXCEL_PE_EIP96_CONTEXT_CTRL */ +#define SAFEXCEL_CONTEXT_SIZE(n) (n) +#define SAFEXCEL_ADDRESS_MODE (1 << 8) +#define SAFEXCEL_CONTROL_MODE (1 << 9) + +/* SAFEXCEL_PE_EIP96_FUNCTION_EN */ +#define SAFEXCEL_FUNCTION_RSVD ((1U << 6) | (1U << 15) | (1U << 20) | (1U << 23)) +#define SAFEXCEL_PROTOCOL_HASH_ONLY (1U << 0) +#define SAFEXCEL_PROTOCOL_ENCRYPT_ONLY (1U << 1) +#define SAFEXCEL_PROTOCOL_HASH_ENCRYPT (1U << 2) +#define SAFEXCEL_PROTOCOL_HASH_DECRYPT (1U << 3) +#define SAFEXCEL_PROTOCOL_ENCRYPT_HASH (1U << 4) +#define SAFEXCEL_PROTOCOL_DECRYPT_HASH (1U << 5) +#define SAFEXCEL_ALG_ARC4 (1U << 7) +#define SAFEXCEL_ALG_AES_ECB (1U << 8) +#define SAFEXCEL_ALG_AES_CBC (1U << 9) +#define SAFEXCEL_ALG_AES_CTR_ICM (1U << 10) +#define SAFEXCEL_ALG_AES_OFB (1U << 11) +#define SAFEXCEL_ALG_AES_CFB (1U << 12) +#define SAFEXCEL_ALG_DES_ECB (1U << 13) +#define SAFEXCEL_ALG_DES_CBC (1U << 14) +#define SAFEXCEL_ALG_DES_OFB (1U << 16) +#define SAFEXCEL_ALG_DES_CFB (1U << 17) +#define SAFEXCEL_ALG_3DES_ECB (1U << 18) +#define SAFEXCEL_ALG_3DES_CBC (1U << 19) +#define SAFEXCEL_ALG_3DES_OFB (1U << 21) +#define SAFEXCEL_ALG_3DES_CFB (1U << 22) +#define SAFEXCEL_ALG_MD5 (1U << 24) +#define SAFEXCEL_ALG_HMAC_MD5 (1U << 25) +#define SAFEXCEL_ALG_SHA1 (1U << 26) +#define SAFEXCEL_ALG_HMAC_SHA1 (1U << 27) +#define SAFEXCEL_ALG_SHA2 (1U << 28) +#define SAFEXCEL_ALG_HMAC_SHA2 (1U << 29) +#define SAFEXCEL_ALG_AES_XCBC_MAC (1U << 30) +#define SAFEXCEL_ALG_GCM_HASH (1U << 31) + +#endif /* _SAFEXCEL_REGS_H_ */ Property changes on: head/sys/dev/safexcel/safexcel_reg.h ___________________________________________________________________ Added: svn:keywords ## -0,0 +1 ## +FreeBSD=%H \ No newline at end of property Index: head/sys/dev/safexcel/safexcel_var.h =================================================================== --- head/sys/dev/safexcel/safexcel_var.h (nonexistent) +++ head/sys/dev/safexcel/safexcel_var.h (revision 363180) @@ -0,0 +1,420 @@ +/*- + * SPDX-License-Identifier: BSD-2-Clause-FreeBSD + * + * Copyright (c) 2020 Rubicon Communications, LLC (Netgate) + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * $FreeBSD$ + */ + +#ifndef _SAFEXCEL_VAR_H_ +#define _SAFEXCEL_VAR_H_ + +#define SAFEXCEL_MAX_RINGS 4 +#define SAFEXCEL_MAX_BATCH_SIZE 64 +#define SAFEXCEL_MAX_FRAGMENTS 64 +#define SAFEXCEL_MAX_IV_LEN 16 +#define SAFEXCEL_MAX_REQUEST_SIZE 65535 + +#define SAFEXCEL_RING_SIZE 512 +#define SAFEXCEL_REQUESTS_PER_RING 64 +#define SAFEXCEL_MAX_ITOKENS 4 +#define SAFEXCEL_MAX_ATOKENS 16 +#define SAFEXCEL_FETCH_COUNT 1 +#define SAFEXCEL_MAX_KEY_LEN 32 +#define SAFEXCEL_MAX_RING_AIC 14 + +/* + * Context Record format. + * + * In this driver the context control words are always set in the control data. + * This is configured by setting SAFEXCEL_OPTION_CTX_CTRL_IN_CMD. + */ +struct safexcel_context_record { + uint32_t control0; /* Unused. */ + uint32_t control1; /* Unused. */ + uint32_t data[40]; /* Key material. */ +} __packed; + +/* Processing Engine Control Data format. */ +struct safexcel_control_data { + uint32_t packet_length : 17; + uint32_t options : 13; + uint32_t type : 2; + + uint16_t application_id; + uint16_t rsvd; + + uint32_t context_lo; + uint32_t context_hi; + + uint32_t control0; + uint32_t control1; + + /* Inline instructions or IV. */ + uint32_t token[SAFEXCEL_MAX_ITOKENS]; +} __packed; + +/* + * Basic Command Descriptor. + * + * The Processing Engine and driver cooperate to maintain a set of command + * rings, representing outstanding crypto operation requests. Each descriptor + * corresponds to an input data segment, and thus a single crypto(9) request may + * span several contiguous command descriptors. + * + * The first command descriptor for a request stores the input token, which + * encodes data specific to the requested operation, such as the encryption + * mode. For some operations data is passed outside the descriptor, in a + * context record (e.g., encryption keys), or in an "additional token data" + * region (e.g., instructions). + */ +struct safexcel_cmd_descr { + uint32_t particle_size : 17; + uint32_t rsvd0 : 5; + uint32_t last_seg : 1; + uint32_t first_seg : 1; + uint32_t additional_cdata_size : 8; + uint32_t rsvd1; + + uint32_t data_lo; + uint32_t data_hi; + + uint32_t atok_lo; + uint32_t atok_hi; + + struct safexcel_control_data control_data; +} __packed; + +/* Context control word 0 fields. */ +#define SAFEXCEL_CONTROL0_TYPE_NULL_OUT 0x0 +#define SAFEXCEL_CONTROL0_TYPE_NULL_IN 0x1 +#define SAFEXCEL_CONTROL0_TYPE_HASH_OUT 0x2 +#define SAFEXCEL_CONTROL0_TYPE_HASH_IN 0x3 +#define SAFEXCEL_CONTROL0_TYPE_CRYPTO_OUT 0x4 +#define SAFEXCEL_CONTROL0_TYPE_CRYPTO_IN 0x5 +#define SAFEXCEL_CONTROL0_TYPE_ENCRYPT_HASH_OUT 0x6 +#define SAFEXCEL_CONTROL0_TYPE_DECRYPT_HASH_IN 0x7 +#define SAFEXCEL_CONTROL0_TYPE_HASH_ENCRYPT_OUT 0xe +#define SAFEXCEL_CONTROL0_TYPE_HASH_DECRYPT_IN 0xf +#define SAFEXCEL_CONTROL0_RESTART_HASH (1 << 4) +#define SAFEXCEL_CONTROL0_NO_FINISH_HASH (1 << 5) +#define SAFEXCEL_CONTROL0_SIZE(n) (((n) & 0xff) << 8) +#define SAFEXCEL_CONTROL0_KEY_EN (1 << 16) +#define SAFEXCEL_CONTROL0_CRYPTO_ALG_AES128 (0x5 << 17) +#define SAFEXCEL_CONTROL0_CRYPTO_ALG_AES192 (0x6 << 17) +#define SAFEXCEL_CONTROL0_CRYPTO_ALG_AES256 (0x7 << 17) +#define SAFEXCEL_CONTROL0_DIGEST_PRECOMPUTED (0x1 << 21) +#define SAFEXCEL_CONTROL0_DIGEST_CCM (0x2 << 21) +#define SAFEXCEL_CONTROL0_DIGEST_GMAC (0x2 << 21) +#define SAFEXCEL_CONTROL0_DIGEST_HMAC (0x3 << 21) +#define SAFEXCEL_CONTROL0_HASH_ALG_SHA1 (0x2 << 23) +#define SAFEXCEL_CONTROL0_HASH_ALG_SHA224 (0x4 << 23) +#define SAFEXCEL_CONTROL0_HASH_ALG_SHA256 (0x3 << 23) +#define SAFEXCEL_CONTROL0_HASH_ALG_SHA384 (0x6 << 23) +#define SAFEXCEL_CONTROL0_HASH_ALG_SHA512 (0x5 << 23) +#define SAFEXCEL_CONTROL0_HASH_ALG_XCBC128 (0x1 << 23) +#define SAFEXCEL_CONTROL0_HASH_ALG_XCBC192 (0x2 << 23) +#define SAFEXCEL_CONTROL0_HASH_ALG_XCBC256 (0x3 << 23) +#define SAFEXCEL_CONTROL0_HASH_ALG_GHASH (0x4 << 23) +#define SAFEXCEL_CONTROL0_INV_FR (0x5 << 24) +#define SAFEXCEL_CONTROL0_INV_TR (0x6 << 24) + +/* Context control word 1 fields. */ +#define SAFEXCEL_CONTROL1_CRYPTO_MODE_ECB 0x0 +#define SAFEXCEL_CONTROL1_CRYPTO_MODE_CBC 0x1 +#define SAFEXCEL_CONTROL1_CRYPTO_MODE_ICM 0x3 +#define SAFEXCEL_CONTROL1_CRYPTO_MODE_OFB 0x4 +#define SAFEXCEL_CONTROL1_CRYPTO_MODE_CFB128 0x5 +#define SAFEXCEL_CONTROL1_CRYPTO_MODE_CTR 0x6 +#define SAFEXCEL_CONTROL1_CRYPTO_MODE_XTS 0x7 +#define SAFEXCEL_CONTROL1_CRYPTO_MODE_CCM (0x6 | (1 << 17)) +#define SAFEXCEL_CONTROL1_CRYPTO_MODE_GCM (0x6 | (1 << 17)) +#define SAFEXCEL_CONTROL1_IV0 (1u << 5) +#define SAFEXCEL_CONTROL1_IV1 (1u << 6) +#define SAFEXCEL_CONTROL1_IV2 (1u << 7) +#define SAFEXCEL_CONTROL1_IV3 (1u << 8) +#define SAFEXCEL_CONTROL1_DIGEST_CNT (1u << 9) +#define SAFEXCEL_CONTROL1_COUNTER_MODE (1u << 10) +#define SAFEXCEL_CONTROL1_ENCRYPT_HASH_RES (1u << 17) +#define SAFEXCEL_CONTROL1_HASH_STORE (1u << 19) + +/* Control options. */ +#define SAFEXCEL_OPTION_IP (1u << 0) /* must be set */ +#define SAFEXCEL_OPTION_CP (1u << 1) /* 64-bit ctx addr */ +#define SAFEXCEL_OPTION_RC_AUTO (2u << 3) /* auto ctx reuse */ +#define SAFEXCEL_OPTION_CTX_CTRL_IN_CMD (1u << 8) /* ctx ctrl */ +#define SAFEXCEL_OPTION_4_TOKEN_IV_CMD 0xe00 /* IV in bypass */ + +struct safexcel_res_data { + uint32_t packet_length : 17; + uint32_t error_code : 15; + + uint32_t bypass_length : 4; + uint32_t e15 : 1; + uint32_t rsvd0 : 16; + uint32_t hash_bytes : 1; + uint32_t hash_length : 6; + uint32_t generic_bytes : 1; + uint32_t checksum : 1; + uint32_t next_header : 1; + uint32_t length : 1; + + uint16_t application_id; + uint16_t rsvd1; + + uint32_t rsvd2; +}; + +/* Basic Result Descriptor format */ +struct safexcel_res_descr { + uint32_t particle_size : 17; + uint32_t rsvd0 : 3; + uint32_t descriptor_overflow : 1; + uint32_t buffer_overflow : 1; + uint32_t last_seg : 1; + uint32_t first_seg : 1; + uint32_t result_size : 8; + + uint32_t rsvd1; + + uint32_t data_lo; + uint32_t data_hi; + + struct safexcel_res_data result_data; +} __packed; + +/* Result data error codes. */ +#define SAFEXCEL_RESULT_ERR_PACKET_LEN (1u << 0) +#define SAFEXCEL_RESULT_ERR_TOKEN_ERROR (1u << 1) +#define SAFEXCEL_RESULT_ERR_BYPASS (1u << 2) +#define SAFEXCEL_RESULT_ERR_CRYPTO_BLOCK_SIZE (1u << 3) +#define SAFEXCEL_RESULT_ERR_HASH_BLOCK_SIZE (1u << 4) +#define SAFEXCEL_RESULT_ERR_INVALID_CMD (1u << 5) +#define SAFEXCEL_RESULT_ERR_PROHIBITED_ALGO (1u << 6) +#define SAFEXCEL_RESULT_ERR_HASH_INPUT_OVERFLOW (1u << 7) +#define SAFEXCEL_RESULT_ERR_TTL_UNDERFLOW (1u << 8) +#define SAFEXCEL_RESULT_ERR_AUTH_FAILED (1u << 9) +#define SAFEXCEL_RESULT_ERR_SEQNO_CHECK_FAILED (1u << 10) +#define SAFEXCEL_RESULT_ERR_SPI_CHECK (1u << 11) +#define SAFEXCEL_RESULT_ERR_CHECKSUM (1u << 12) +#define SAFEXCEL_RESULT_ERR_PAD_VERIFICATION (1u << 13) +#define SAFEXCEL_RESULT_ERR_TIMEOUT (1u << 14) +#define SAFEXCEL_RESULT_ERR_OUTPUT_DMA (1u << 15) + +/* + * The EIP-96 (crypto transform engine) is programmed using a set of + * data processing instructions with the encodings defined below. + */ +struct safexcel_instr { + uint32_t length : 17; /* bytes to be processed */ + uint32_t status : 2; /* stream status */ + uint32_t instructions : 9; + uint32_t opcode : 4; +} __packed; + +/* Type 1, operational data instructions. */ +#define SAFEXCEL_INSTR_OPCODE_DIRECTION 0x0 +#define SAFEXCEL_INSTR_OPCODE_PRE_CHECKSUM 0x1 +#define SAFEXCEL_INSTR_OPCODE_INSERT 0x2 +#define SAFEXCEL_INSTR_OPCODE_INSERT_CTX 0x9 +#define SAFEXCEL_INSTR_OPCODE_REPLACE 0x3 +#define SAFEXCEL_INSTR_OPCODE_RETRIEVE 0x4 +#define SAFEXCEL_INSTR_OPCODE_MUTE 0x5 +/* Type 2, IP header instructions. */ +#define SAFEXCEL_INSTR_OPCODE_IPV4 0x7 +#define SAFEXCEL_INSTR_OPCODE_IPV4_CHECKSUM 0x6 +#define SAFEXCEL_INSTR_OPCODE_IPV6 0x8 +/* Type 3, postprocessing instructions. */ +#define SAFEXCEL_INSTR_OPCODE_INSERT_REMOVE_RESULT 0xa +#define SAFEXCEL_INSTR_OPCODE_REPLACE_BYTE 0xb +/* Type 4, result instructions. */ +#define SAFEXCEL_INSTR_OPCODE_VERIFY_FIELDS 0xd +/* Type 5, context control instructions. */ +#define SAFEXCEL_INSTR_OPCODE_CONTEXT_ACCESS 0xe +/* Type 6, context control instructions. */ +#define SAFEXCEL_INSTR_OPCODE_BYPASS_TOKEN_DATA 0xf + +/* Status bits for type 1 and 2 instructions. */ +#define SAFEXCEL_INSTR_STATUS_LAST_HASH (1u << 0) +#define SAFEXCEL_INSTR_STATUS_LAST_PACKET (1u << 1) +/* Status bits for type 3 instructions. */ +#define SAFEXCEL_INSTR_STATUS_NO_CKSUM_MOD (1u << 0) + +/* Instruction-dependent flags. */ +#define SAFEXCEL_INSTR_INSERT_HASH_DIGEST 0x1c +#define SAFEXCEL_INSTR_INSERT_IMMEDIATE 0x1b +#define SAFEXCEL_INSTR_DEST_OUTPUT (1u << 5) +#define SAFEXCEL_INSTR_DEST_HASH (1u << 6) +#define SAFEXCEL_INSTR_DEST_CRYPTO (1u << 7) +#define SAFEXCEL_INSTR_INS_LAST (1u << 8) + +#define SAFEXCEL_INSTR_VERIFY_HASH (1u << 16) +#define SAFEXCEL_INSTR_VERIFY_PADDING (1u << 5) + +#define SAFEXCEL_TOKEN_TYPE_BYPASS 0x0 +#define SAFEXCEL_TOKEN_TYPE_AUTONOMOUS 0x3 + +#define SAFEXCEL_CONTEXT_SMALL 0x2 +#define SAFEXCEL_CONTEXT_LARGE 0x3 + +struct safexcel_reg_offsets { + uint32_t hia_aic; + uint32_t hia_aic_g; + uint32_t hia_aic_r; + uint32_t hia_aic_xdr; + uint32_t hia_dfe; + uint32_t hia_dfe_thr; + uint32_t hia_dse; + uint32_t hia_dse_thr; + uint32_t hia_gen_cfg; + uint32_t pe; +}; + +struct safexcel_config { + uint32_t hdw; /* Host interface Data Width. */ + uint32_t aic_rings; /* Number of AIC rings. */ + uint32_t pes; /* Number of PEs. */ + uint32_t rings; /* Number of rings. */ + + uint32_t cd_size; /* CDR descriptor size. */ + uint32_t cd_offset; /* CDR offset (size + alignment). */ + + uint32_t rd_size; /* RDR descriptor size. */ + uint32_t rd_offset; /* RDR offset. */ + + uint32_t atok_offset; /* Additional token offset. */ + + uint32_t caps; /* Device capabilities. */ +}; + +#define SAFEXCEL_DPRINTF(sc, lvl, ...) do { \ + if ((sc)->sc_debug >= (lvl)) \ + device_printf((sc)->sc_dev, __VA_ARGS__); \ +} while (0) + +struct safexcel_dma_mem { + caddr_t vaddr; + bus_addr_t paddr; + bus_dma_tag_t tag; + bus_dmamap_t map; +}; + +struct safexcel_cmd_descr_ring { + struct safexcel_dma_mem dma; + struct safexcel_cmd_descr *desc; + int write; + int read; +}; + +struct safexcel_res_descr_ring { + struct safexcel_dma_mem dma; + struct safexcel_res_descr *desc; + int write; + int read; +}; + +struct safexcel_session { + int ringidx; + uint32_t alg; /* cipher algorithm */ + uint32_t digest; /* digest type */ + uint32_t hash; /* hash algorithm */ + uint32_t mode; /* cipher mode of operation */ + unsigned int digestlen; /* digest length */ + unsigned int statelen; /* HMAC hash state length */ + unsigned int klen; /* cipher key length */ + union { + uint32_t ghash_key[AES_BLOCK_LEN / sizeof(uint32_t)]; + uint32_t xcbc_key[(AES_BLOCK_LEN * 2 + AES_MAX_KEY) / + sizeof(uint32_t)]; + uint8_t tweak_key[AES_MAX_KEY]; + }; + struct { + uint8_t hmac_ipad[HMAC_MAX_BLOCK_LEN]; + uint8_t hmac_opad[HMAC_MAX_BLOCK_LEN]; + }; +}; + +struct safexcel_softc; + +struct safexcel_request { + STAILQ_ENTRY(safexcel_request) link; + bool dmap_loaded; + bus_dmamap_t dmap; + int error; + int cdescs, rdescs; + uint8_t iv[SAFEXCEL_MAX_IV_LEN]; + struct safexcel_cmd_descr *cdesc; + struct safexcel_dma_mem ctx; + struct safexcel_session *sess; + struct cryptop *crp; + struct safexcel_softc *sc; +}; + +struct safexcel_ring { + struct mtx mtx; + struct sglist *cmd_data; + struct safexcel_cmd_descr_ring cdr; + struct sglist *res_data; + struct safexcel_res_descr_ring rdr; + + struct safexcel_request *requests; + STAILQ_HEAD(, safexcel_request) ready_requests; + STAILQ_HEAD(, safexcel_request) queued_requests; + STAILQ_HEAD(, safexcel_request) free_requests; + + struct safexcel_dma_mem dma_atok; + bus_dma_tag_t data_dtag; +}; + +struct safexcel_intr_handle { + struct safexcel_softc *sc; + void *handle; + int ring; +}; + +struct safexcel_softc { + device_t sc_dev; + uint32_t sc_type; /* EIP-97 or 197 */ + int sc_debug; + + struct resource *sc_res; + struct resource *sc_intr[SAFEXCEL_MAX_RINGS]; + struct safexcel_intr_handle sc_ih[SAFEXCEL_MAX_RINGS]; + + struct safexcel_ring sc_ring[SAFEXCEL_MAX_RINGS]; + int sc_ringidx; + struct mtx sc_mtx; + + int sc_blocked; + int32_t sc_cid; + struct safexcel_reg_offsets sc_offsets; + struct safexcel_config sc_config; +}; + +#define SAFEXCEL_WRITE(sc, off, val) bus_write_4((sc)->sc_res, (off), (val)) +#define SAFEXCEL_READ(sc, off) bus_read_4((sc)->sc_res, (off)) + +#define SAFEXCEL_ADDR_LO(addr) ((uint64_t)(addr) & 0xffffffffu) +#define SAFEXCEL_ADDR_HI(addr) (((uint64_t)(addr) >> 32) & 0xffffffffu) + +#endif /* _SAFEXCEL_VAR_H_ */ Property changes on: head/sys/dev/safexcel/safexcel_var.h ___________________________________________________________________ Added: svn:keywords ## -0,0 +1 ## +FreeBSD=%H \ No newline at end of property Index: head/sys/modules/Makefile =================================================================== --- head/sys/modules/Makefile (revision 363179) +++ head/sys/modules/Makefile (revision 363180) @@ -1,818 +1,819 @@ # $FreeBSD$ SYSDIR?=${SRCTOP}/sys .include "${SYSDIR}/conf/kern.opts.mk" SUBDIR_PARALLEL= # Modules that include binary-only blobs of microcode should be selectable by # MK_SOURCELESS_UCODE option (see below). .include "${SYSDIR}/conf/config.mk" .if defined(MODULES_OVERRIDE) && !defined(ALL_MODULES) SUBDIR=${MODULES_OVERRIDE} .else SUBDIR= \ ${_3dfx} \ ${_3dfx_linux} \ ${_aac} \ ${_aacraid} \ accf_data \ accf_dns \ accf_http \ acl_nfs4 \ acl_posix1e \ ${_acpi} \ ae \ ${_aesni} \ age \ ${_agp} \ ahci \ aic7xxx \ alc \ ale \ alq \ ${_amd_ecc_inject} \ ${_amdgpio} \ ${_amdsbwd} \ ${_amdsmn} \ ${_amdtemp} \ amr \ ${_an} \ ${_aout} \ ${_apm} \ ${_arcmsr} \ ${_allwinner} \ ${_armv8crypto} \ ${_asmc} \ ata \ ath \ ath_dfs \ ath_hal \ ath_hal_ar5210 \ ath_hal_ar5211 \ ath_hal_ar5212 \ ath_hal_ar5416 \ ath_hal_ar9300 \ ath_main \ ath_rate \ ath_pci \ ${_autofs} \ ${_bce} \ ${_bcm283x_clkman} \ ${_bcm283x_pwm} \ bfe \ bge \ bhnd \ ${_bxe} \ ${_bios} \ ${_blake2} \ bnxt \ bridgestp \ bwi \ bwn \ ${_bytgpio} \ ${_chvgpio} \ cam \ ${_cardbus} \ ${_carp} \ cas \ ${_cbb} \ cc \ ${_ccp} \ cd9660 \ cd9660_iconv \ ${_ce} \ ${_cfi} \ ${_chromebook_platform} \ ${_ciss} \ cloudabi \ ${_cloudabi32} \ ${_cloudabi64} \ ${_cmx} \ ${_coretemp} \ ${_cp} \ ${_cpsw} \ ${_cpuctl} \ ${_cpufreq} \ ${_crypto} \ ${_cryptodev} \ ctl \ ${_cxgb} \ ${_cxgbe} \ dc \ dcons \ dcons_crom \ ${_dpms} \ dummynet \ ${_efirt} \ ${_em} \ ${_ena} \ esp \ ${_et} \ evdev \ ${_exca} \ ext2fs \ fdc \ fdescfs \ ${_ffec} \ filemon \ firewire \ firmware \ fusefs \ ${_fxp} \ gem \ geom \ ${_glxiic} \ ${_glxsb} \ gpio \ hifn \ hme \ ${_hpt27xx} \ ${_hptiop} \ ${_hptmv} \ ${_hptnr} \ ${_hptrr} \ hwpmc \ ${_hwpmc_mips24k} \ ${_hwpmc_mips74k} \ ${_hyperv} \ i2c \ ${_iavf} \ ${_ibcore} \ ${_ichwd} \ ${_ice} \ ${_ice_ddp} \ ${_ida} \ if_bridge \ if_disc \ if_edsc \ ${_if_enc} \ if_epair \ ${_if_gif} \ ${_if_gre} \ ${_if_me} \ if_lagg \ ${_if_ndis} \ ${_if_stf} \ if_tuntap \ if_vlan \ if_vxlan \ iflib \ ${_iir} \ imgact_binmisc \ ${_intelspi} \ ${_io} \ ${_ioat} \ ${_ipoib} \ ${_ipdivert} \ ${_ipfilter} \ ${_ipfw} \ ipfw_nat \ ${_ipfw_nat64} \ ${_ipfw_nptv6} \ ${_ipfw_pmod} \ ${_ipmi} \ ip6_mroute_mod \ ip_mroute_mod \ ${_ips} \ ${_ipsec} \ ${_ipw} \ ${_ipwfw} \ ${_isci} \ ${_iser} \ isp \ ${_ispfw} \ ${_itwd} \ ${_iwi} \ ${_iwifw} \ ${_iwm} \ ${_iwmfw} \ ${_iwn} \ ${_iwnfw} \ ${_ix} \ ${_ixv} \ ${_ixl} \ jme \ kbdmux \ kgssapi \ kgssapi_krb5 \ khelp \ krpc \ ksyms \ ${_ktls_ocf} \ le \ lge \ libalias \ libiconv \ libmchain \ lindebugfs \ linuxkpi \ ${_lio} \ lpt \ mac_biba \ mac_bsdextended \ mac_ifoff \ mac_lomac \ mac_mls \ mac_none \ mac_ntpd \ mac_partition \ mac_portacl \ mac_seeotheruids \ mac_stub \ mac_test \ malo \ md \ mdio \ mem \ mfi \ mii \ mlx \ mlxfw \ ${_mlx4} \ ${_mlx4ib} \ ${_mlx4en} \ ${_mlx5} \ ${_mlx5en} \ ${_mlx5ib} \ ${_mly} \ mmc \ mmcsd \ ${_mpr} \ ${_mps} \ mpt \ mqueue \ mrsas \ msdosfs \ msdosfs_iconv \ msk \ ${_mthca} \ mvs \ mwl \ ${_mwlfw} \ mxge \ my \ ${_nctgpio} \ ${_ndis} \ ${_netgraph} \ ${_nfe} \ nfscl \ nfscommon \ nfsd \ nfslockd \ nfssvc \ nge \ nmdm \ nullfs \ ${_ntb} \ ${_nvd} \ ${_nvdimm} \ ${_nvme} \ ${_nvram} \ oce \ ${_ocs_fc} \ otus \ ${_otusfw} \ ow \ ${_padlock} \ ${_padlock_rng} \ ${_pccard} \ ${_pchtherm} \ ${_pcfclock} \ ${_pf} \ ${_pflog} \ ${_pfsync} \ plip \ ${_pms} \ ppbus \ ppc \ ppi \ pps \ procfs \ proto \ pseudofs \ ${_pst} \ pty \ puc \ pwm \ ${_qlxge} \ ${_qlxgb} \ ${_qlxgbe} \ ${_qlnx} \ ral \ ${_ralfw} \ ${_random_fortuna} \ ${_random_other} \ rc4 \ ${_rdma} \ ${_rdrand_rng} \ re \ rl \ ${_rockchip} \ rtwn \ rtwn_pci \ rtwn_usb \ ${_rtwnfw} \ ${_s3} \ ${_safe} \ + safexcel \ ${_sbni} \ scc \ ${_sctp} \ sdhci \ ${_sdhci_acpi} \ sdhci_pci \ sdio \ sem \ send \ ${_sfxge} \ sge \ ${_sgx} \ ${_sgx_linux} \ siftr \ siis \ sis \ sk \ ${_smartpqi} \ smbfs \ snp \ sound \ ${_speaker} \ spi \ ${_splash} \ ${_sppp} \ ste \ stge \ ${_superio} \ ${_sym} \ ${_syscons} \ sysvipc \ tcp \ ${_ti} \ tmpfs \ ${_toecore} \ ${_tpm} \ ${_twa} \ twe \ tws \ uart \ udf \ udf_iconv \ ufs \ uinput \ unionfs \ usb \ ${_vesa} \ ${_virtio} \ vge \ ${_viawd} \ videomode \ vkbd \ ${_vmd} \ ${_vmm} \ ${_vmware} \ vr \ vte \ ${_wbwd} \ ${_wi} \ wlan \ wlan_acl \ wlan_amrr \ wlan_ccmp \ wlan_rssadapt \ wlan_tkip \ wlan_wep \ wlan_xauth \ ${_wpi} \ ${_wpifw} \ ${_x86bios} \ xdr \ xl \ xz \ zlib .if ${MK_AUTOFS} != "no" || defined(ALL_MODULES) _autofs= autofs .endif .if ${MK_CDDL} != "no" || defined(ALL_MODULES) .if (${MACHINE_CPUARCH} != "arm" || ${MACHINE_ARCH:Marmv[67]*} != "") && \ ${MACHINE_CPUARCH} != "mips" .if ${KERN_OPTS:MKDTRACE_HOOKS} SUBDIR+= dtrace .endif .endif SUBDIR+= opensolaris .endif .if ${MK_CRYPT} != "no" || defined(ALL_MODULES) .if exists(${SRCTOP}/sys/opencrypto) _crypto= crypto _cryptodev= cryptodev _random_fortuna=random_fortuna _random_other= random_other _ktls_ocf= ktls_ocf .endif .endif .if ${MK_CUSE} != "no" || defined(ALL_MODULES) SUBDIR+= cuse .endif .if (${MK_INET_SUPPORT} != "no" || ${MK_INET6_SUPPORT} != "no") || \ defined(ALL_MODULES) _carp= carp _toecore= toecore _if_enc= if_enc _if_gif= if_gif _if_gre= if_gre _ipfw_pmod= ipfw_pmod .if ${KERN_OPTS:MIPSEC_SUPPORT} && !${KERN_OPTS:MIPSEC} _ipsec= ipsec .endif .if ${KERN_OPTS:MSCTP_SUPPORT} || ${KERN_OPTS:MSCTP} _sctp= sctp .endif .endif .if (${MK_INET_SUPPORT} != "no" && ${MK_INET6_SUPPORT} != "no") || \ defined(ALL_MODULES) _if_stf= if_stf .endif .if ${MK_INET_SUPPORT} != "no" || defined(ALL_MODULES) _if_me= if_me _ipdivert= ipdivert _ipfw= ipfw .if ${MK_INET6_SUPPORT} != "no" || defined(ALL_MODULES) _ipfw_nat64= ipfw_nat64 .endif .endif .if ${MK_INET6_SUPPORT} != "no" || defined(ALL_MODULES) _ipfw_nptv6= ipfw_nptv6 .endif .if ${MK_IPFILTER} != "no" || defined(ALL_MODULES) _ipfilter= ipfilter .endif .if ${MK_ISCSI} != "no" || defined(ALL_MODULES) SUBDIR+= cfiscsi SUBDIR+= iscsi SUBDIR+= iscsi_initiator .endif .if !empty(OPT_FDT) SUBDIR+= fdt .endif # Linuxulator .if ${MACHINE_CPUARCH} == "aarch64" || ${MACHINE_CPUARCH} == "amd64" || \ ${MACHINE_CPUARCH} == "i386" SUBDIR+= linprocfs SUBDIR+= linsysfs .endif .if ${MACHINE_CPUARCH} == "amd64" || ${MACHINE_CPUARCH} == "i386" SUBDIR+= linux .endif .if ${MACHINE_CPUARCH} == "aarch64" || ${MACHINE_CPUARCH} == "amd64" SUBDIR+= linux64 SUBDIR+= linux_common .endif .if ${MACHINE_CPUARCH} == "aarch64" || ${MACHINE_CPUARCH} == "amd64" || \ ${MACHINE_CPUARCH} == "i386" _ena= ena .if ${MK_OFED} != "no" || defined(ALL_MODULES) _ibcore= ibcore _ipoib= ipoib _iser= iser .endif _mlx4= mlx4 _mlx5= mlx5 .if (${MK_INET_SUPPORT} != "no" && ${MK_INET6_SUPPORT} != "no") || \ defined(ALL_MODULES) _mlx4en= mlx4en _mlx5en= mlx5en .endif .if ${MK_OFED} != "no" || defined(ALL_MODULES) _mthca= mthca _mlx4ib= mlx4ib _mlx5ib= mlx5ib .endif .endif .if ${MK_NETGRAPH} != "no" || defined(ALL_MODULES) _netgraph= netgraph .endif .if (${MK_PF} != "no" && (${MK_INET_SUPPORT} != "no" || \ ${MK_INET6_SUPPORT} != "no")) || defined(ALL_MODULES) _pf= pf _pflog= pflog .if ${MK_INET_SUPPORT} != "no" _pfsync= pfsync .endif .endif .if ${MK_SOURCELESS_UCODE} != "no" _bce= bce _fxp= fxp _ispfw= ispfw _ti= ti .if ${MACHINE_CPUARCH} != "mips" _mwlfw= mwlfw _otusfw= otusfw _ralfw= ralfw _rtwnfw= rtwnfw .endif .endif .if ${MK_SOURCELESS_UCODE} != "no" && ${MACHINE_CPUARCH} != "arm" && \ ${MACHINE_CPUARCH} != "mips" && \ ${MACHINE_ARCH} != "powerpc" && ${MACHINE_ARCH} != "powerpcspe" && \ ${MACHINE_CPUARCH} != "riscv" _cxgbe= cxgbe .endif .if ${MACHINE_ARCH} == "amd64" || ${MACHINE_ARCH} == "arm64" _ice= ice .if ${MK_SOURCELESS_UCODE} != "no" _ice_ddp= ice_ddp .endif .endif # These rely on 64bit atomics .if ${MACHINE_ARCH} != "powerpc" && ${MACHINE_ARCH} != "powerpcspe" && \ ${MACHINE_CPUARCH} != "mips" _mps= mps _mpr= mpr .endif .if ${MK_TESTS} != "no" || defined(ALL_MODULES) SUBDIR+= tests .endif .if ${MK_ZFS} != "no" || defined(ALL_MODULES) SUBDIR+= zfs .endif .if (${MACHINE_CPUARCH} == "mips" && ${MACHINE_ARCH:Mmips64} == "") _hwpmc_mips24k= hwpmc_mips24k _hwpmc_mips74k= hwpmc_mips74k .endif .if ${MACHINE_CPUARCH} != "aarch64" && ${MACHINE_CPUARCH} != "arm" && \ ${MACHINE_CPUARCH} != "mips" && ${MACHINE_CPUARCH} != "powerpc" && \ ${MACHINE_CPUARCH} != "riscv" _syscons= syscons .endif .if ${MACHINE_CPUARCH} != "mips" # no BUS_SPACE_UNSPECIFIED # No barrier instruction support (specific to this driver) _sym= sym # intr_disable() is a macro, causes problems .if ${MK_SOURCELESS_UCODE} != "no" _cxgb= cxgb .endif .endif .if ${MACHINE_CPUARCH} == "aarch64" _allwinner= allwinner _armv8crypto= armv8crypto _efirt= efirt _em= em _rockchip= rockchip .endif .if ${MACHINE_CPUARCH} == "i386" || ${MACHINE_CPUARCH} == "amd64" _agp= agp _an= an _aout= aout _bios= bios .if ${MK_SOURCELESS_UCODE} != "no" _bxe= bxe .endif _cardbus= cardbus _cbb= cbb _cpuctl= cpuctl _cpufreq= cpufreq _dpms= dpms _em= em _et= et _exca= exca _if_ndis= if_ndis _io= io _itwd= itwd _ix= ix _ixv= ixv .if ${MK_SOURCELESS_UCODE} != "no" _lio= lio .endif _nctgpio= nctgpio _ndis= ndis _ntb= ntb _ocs_fc= ocs_fc _pccard= pccard .if ${MK_OFED} != "no" || defined(ALL_MODULES) _rdma= rdma .endif _safe= safe _speaker= speaker _splash= splash _sppp= sppp _vmware= vmware _wbwd= wbwd _wi= wi _aac= aac _aacraid= aacraid _acpi= acpi .if ${MK_CRYPT} != "no" || defined(ALL_MODULES) _aesni= aesni .endif _amd_ecc_inject=amd_ecc_inject _amdsbwd= amdsbwd _amdsmn= amdsmn _amdtemp= amdtemp _arcmsr= arcmsr _asmc= asmc .if ${MK_CRYPT} != "no" || defined(ALL_MODULES) _blake2= blake2 .endif _bytgpio= bytgpio _chvgpio= chvgpio _ciss= ciss _chromebook_platform= chromebook_platform _cmx= cmx _coretemp= coretemp .if ${MK_SOURCELESS_HOST} != "no" && empty(KCSAN_ENABLED) _hpt27xx= hpt27xx .endif _hptiop= hptiop .if ${MK_SOURCELESS_HOST} != "no" && empty(KCSAN_ENABLED) _hptmv= hptmv _hptnr= hptnr _hptrr= hptrr .endif _hyperv= hyperv _ichwd= ichwd _ida= ida _iir= iir _intelspi= intelspi _ipmi= ipmi _ips= ips _isci= isci _ipw= ipw _iwi= iwi _iwm= iwm _iwn= iwn .if ${MK_SOURCELESS_UCODE} != "no" _ipwfw= ipwfw _iwifw= iwifw _iwmfw= iwmfw _iwnfw= iwnfw .endif _mly= mly _nfe= nfe _nvd= nvd _nvme= nvme _nvram= nvram .if ${MK_CRYPT} != "no" || defined(ALL_MODULES) _padlock= padlock _padlock_rng= padlock_rng _rdrand_rng= rdrand_rng .endif _pchtherm = pchtherm _s3= s3 _sdhci_acpi= sdhci_acpi _superio= superio _tpm= tpm _twa= twa _vesa= vesa _viawd= viawd _virtio= virtio _wpi= wpi .if ${MK_SOURCELESS_UCODE} != "no" _wpifw= wpifw .endif _x86bios= x86bios .endif .if ${MACHINE_CPUARCH} == "amd64" _amdgpio= amdgpio _ccp= ccp _efirt= efirt _iavf= iavf _ioat= ioat _ixl= ixl _nvdimm= nvdimm _pms= pms _qlxge= qlxge _qlxgb= qlxgb _vmd= vmd .if ${MK_SOURCELESS_UCODE} != "no" _qlxgbe= qlxgbe _qlnx= qlnx .endif _sfxge= sfxge _sgx= sgx _sgx_linux= sgx_linux _smartpqi= smartpqi .if ${MK_BHYVE} != "no" || defined(ALL_MODULES) .if ${KERN_OPTS:MSMP} _vmm= vmm .endif .endif .endif .if ${MACHINE_CPUARCH} == "i386" # XXX some of these can move to the general case when de-i386'ed # XXX some of these can move now, but are untested on other architectures. _3dfx= 3dfx _3dfx_linux= 3dfx_linux _apm= apm .if ${MK_SOURCELESS_HOST} != "no" _ce= ce .endif .if ${MK_SOURCELESS_UCODE} != "no" _cp= cp .endif _glxiic= glxiic _glxsb= glxsb _pcfclock= pcfclock _pst= pst _sbni= sbni .endif .if ${MACHINE_CPUARCH} == "arm" _cfi= cfi _cpsw= cpsw .endif .if ${MACHINE_CPUARCH} == "powerpc" _aacraid= aacraid _agp= agp _an= an _cardbus= cardbus _cbb= cbb _cfi= cfi _cpufreq= cpufreq _exca= exca _ffec= ffec _nvd= nvd _nvme= nvme _pccard= pccard _wi= wi _virtio= virtio .endif .if ${MACHINE_ARCH} == "powerpc64" _ipmi= ipmi _ixl= ixl _nvram= opal_nvram .endif .if ${MACHINE_ARCH} == "powerpc64" || ${MACHINE_ARCH} == "powerpc" # Don't build powermac_nvram for powerpcspe, it's never supported. _nvram+= powermac_nvram .endif .if (${MACHINE_CPUARCH} == "aarch64" || ${MACHINE_CPUARCH} == "amd64" || \ ${MACHINE_ARCH:Marmv[67]*} != "" || ${MACHINE_CPUARCH} == "i386") _cloudabi32= cloudabi32 .endif .if ${MACHINE_CPUARCH} == "aarch64" || ${MACHINE_CPUARCH} == "amd64" _cloudabi64= cloudabi64 .endif .endif .if ${MACHINE_ARCH:Marmv[67]*} != "" || ${MACHINE_CPUARCH} == "aarch64" _bcm283x_clkman= bcm283x_clkman _bcm283x_pwm= bcm283x_pwm .endif SUBDIR+=${MODULES_EXTRA} .for reject in ${WITHOUT_MODULES} SUBDIR:= ${SUBDIR:N${reject}} .endfor # Calling kldxref(8) for each module is expensive. .if !defined(NO_XREF) .MAKEFLAGS+= -DNO_XREF afterinstall: .PHONY @if type kldxref >/dev/null 2>&1; then \ ${ECHO} ${KLDXREF_CMD} ${DESTDIR}${KMODDIR}; \ ${KLDXREF_CMD} ${DESTDIR}${KMODDIR}; \ fi .endif SUBDIR:= ${SUBDIR:u:O} .include Index: head/sys/modules/safexcel/Makefile =================================================================== --- head/sys/modules/safexcel/Makefile (nonexistent) +++ head/sys/modules/safexcel/Makefile (revision 363180) @@ -0,0 +1,9 @@ +# $FreeBSD$ +.PATH: ${SRCTOP}/sys/dev/safexcel + +KMOD= safexcel +SRCS= safexcel.c + +SRCS+= bus_if.h cryptodev_if.h device_if.h ofw_bus_if.h + +.include Property changes on: head/sys/modules/safexcel/Makefile ___________________________________________________________________ Added: svn:keywords ## -0,0 +1 ## +FreeBSD=%H \ No newline at end of property