Index: head/sys/arm/broadcom/bcm2835/bcm2838_pci.c =================================================================== --- head/sys/arm/broadcom/bcm2835/bcm2838_pci.c (nonexistent) +++ head/sys/arm/broadcom/bcm2835/bcm2838_pci.c (revision 362954) @@ -0,0 +1,743 @@ +/*- + * SPDX-License-Identifier: ISC + * + * Copyright (c) 2020 Dr Robert Harvey Crowston + * + * Permission to use, copy, modify, and distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + * + * + * $FreeBSD$ + * + */ + +/* + * BCM2838-compatible PCI-express controller. + * + * Broadcom likes to give the same chip lots of different names. The name of + * this driver is taken from the Raspberry Pi 4 Broadcom 2838 chip. + */ + +#include +__FBSDID("$FreeBSD$"); + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include + +#include +#include +#include +#include +#include + +#include +#include + +#include "pcib_if.h" +#include "msi_if.h" + +extern struct bus_space memmap_bus; + +#define BUS_SPACE_3G_MAXADDR 0xc0000000 +#define PCI_ID_VAL3 0x43c +#define CLASS_SHIFT 0x10 +#define SUBCLASS_SHIFT 0x8 + +#define REG_CONTROLLER_HW_REV 0x406c +#define REG_BRIDGE_CTRL 0x9210 +#define BRIDGE_DISABLE_FLAG 0x1 +#define BRIDGE_RESET_FLAG 0x2 +#define REG_BRIDGE_SERDES_MODE 0x4204 +#define REG_BRIDGE_CONFIG 0x4008 +#define REG_BRIDGE_MEM_WINDOW_LOW 0x4034 +#define REG_BRIDGE_MEM_WINDOW_HIGH 0x4038 +#define REG_BRIDGE_MEM_WINDOW_1 0x403c +#define REG_BRIDGE_GISB_WINDOW 0x402c +#define REG_BRIDGE_STATE 0x4068 +#define REG_BRIDGE_LINK_STATE 0x00bc +#define REG_BRIDGE_BUS_WINDOW_LOW 0x400c +#define REG_BRIDGE_BUS_WINDOW_HIGH 0x4010 +#define REG_BRIDGE_CPU_WINDOW_LOW 0x4070 +#define REG_BRIDGE_CPU_WINDOW_START_HIGH 0x4080 +#define REG_BRIDGE_CPU_WINDOW_END_HIGH 0x4084 + +#define REG_MSI_ADDR_LOW 0x4044 +#define REG_MSI_ADDR_HIGH 0x4048 +#define REG_MSI_CONFIG 0x404c +#define REG_MSI_CLR 0x4508 +#define REG_MSI_MASK_CLR 0x4514 +#define REG_MSI_RAISED 0x4500 +#define REG_MSI_EOI 0x4060 +#define NUM_MSI 32 + +#define REG_EP_CONFIG_CHOICE 0x9000 +#define REG_EP_CONFIG_DATA 0x8000 + +/* + * These values were obtained from runtime inspection of a Linux system using a + * JTAG. The very limited documentation I have obtained from Broadcom does not + * explain how to compute them. + */ +#define REG_VALUE_4GB_WINDOW 0x11 +#define REG_VALUE_4GB_CONFIG 0x88003000 +#define REG_VALUE_MSI_CONFIG 0xffe06540 + +struct bcm_pcib_irqsrc { + struct intr_irqsrc isrc; + u_int irq; + bool allocated; +}; + +struct bcm_pcib_softc { + struct generic_pcie_fdt_softc base; + device_t dev; + struct mtx config_mtx; + struct mtx msi_mtx; + struct resource *msi_irq_res; + void *msi_intr_cookie; + struct bcm_pcib_irqsrc *msi_isrcs; + pci_addr_t msi_addr; +}; + +static struct ofw_compat_data compat_data[] = { + {"brcm,bcm2711-pcie", 1}, + {"brcm,bcm7211-pcie", 1}, + {"brcm,bcm7445-pcie", 1}, + + {NULL, 0} +}; + +static int +bcm_pcib_probe(device_t dev) +{ + + if (!ofw_bus_status_okay(dev)) + return (ENXIO); + + if (!ofw_bus_search_compatible(dev, compat_data)->ocd_data) + return (ENXIO); + + device_set_desc(dev, + "BCM2838-compatible PCI-express controller"); + return (BUS_PROBE_DEFAULT); +} + +static void +bcm_pcib_set_reg(struct bcm_pcib_softc *sc, uint32_t reg, uint32_t val) +{ + + bus_space_write_4(sc->base.base.bst, sc->base.base.bsh, reg, + htole32(val)); +} + +static uint32_t +bcm_pcib_read_reg(struct bcm_pcib_softc *sc, uint32_t reg) +{ + + return (le32toh(bus_space_read_4(sc->base.base.bst, sc->base.base.bsh, + reg))); +} + +static void +bcm_pcib_reset_controller(struct bcm_pcib_softc *sc) +{ + uint32_t val; + + val = bcm_pcib_read_reg(sc, REG_BRIDGE_CTRL); + val = val | BRIDGE_RESET_FLAG | BRIDGE_DISABLE_FLAG; + bcm_pcib_set_reg(sc, REG_BRIDGE_CTRL, val); + + DELAY(100); + + val = bcm_pcib_read_reg(sc, REG_BRIDGE_CTRL); + val = val & ~BRIDGE_RESET_FLAG; + bcm_pcib_set_reg(sc, REG_BRIDGE_CTRL, val); + + DELAY(100); + + bcm_pcib_set_reg(sc, REG_BRIDGE_SERDES_MODE, 0); + + DELAY(100); +} + +static void +bcm_pcib_enable_controller(struct bcm_pcib_softc *sc) +{ + uint32_t val; + + val = bcm_pcib_read_reg(sc, REG_BRIDGE_CTRL); + val = val & ~BRIDGE_DISABLE_FLAG; + bcm_pcib_set_reg(sc, REG_BRIDGE_CTRL, val); + + DELAY(100); +} + +static int +bcm_pcib_check_ranges(device_t dev) +{ + struct bcm_pcib_softc *sc; + struct pcie_range *ranges; + int error = 0, i; + + sc = device_get_softc(dev); + ranges = &sc->base.base.ranges[0]; + + /* The first range needs to be non-zero. */ + if (ranges[0].size == 0) { + device_printf(dev, "error: first outbound memory range " + "(pci addr: 0x%jx, cpu addr: 0x%jx) has zero size.\n", + ranges[0].pci_base, ranges[0].phys_base); + error = ENXIO; + } + + /* + * The controller can actually handle three distinct ranges, but we + * only implement support for one. + */ + for (i = 1; (bootverbose || error) && i < MAX_RANGES_TUPLES; ++i) { + if (ranges[i].size > 0) + device_printf(dev, + "note: outbound memory range %d (pci addr: 0x%jx, " + "cpu addr: 0x%jx, size: 0x%jx) will be ignored.\n", + i, ranges[i].pci_base, ranges[i].phys_base, + ranges[i].size); + } + + return (error); +} + +static const char * +bcm_pcib_link_state_string(uint32_t mode) +{ + + switch(mode & PCIEM_LINK_STA_SPEED) { + case 0: + return ("not up"); + case 1: + return ("2.5 GT/s"); + case 2: + return ("5.0 GT/s"); + case 4: + return ("8.0 GT/s"); + default: + return ("unknown"); + } +} + +static bus_addr_t +bcm_get_offset_and_prepare_config(struct bcm_pcib_softc *sc, u_int bus, + u_int slot, u_int func, u_int reg) +{ + /* + * Config for an end point is only available through a narrow window for + * one end point at a time. We first tell the controller which end point + * we want, then access it through the window. + */ + uint32_t func_index; + + if (bus == 0 && slot == 0 && func == 0) + /* + * Special case for root device; its config is always available + * through the zero-offset. + */ + return (reg); + + /* Tell the controller to show us the config in question. */ + func_index = PCIE_ADDR_OFFSET(bus, slot, func, 0); + bcm_pcib_set_reg(sc, REG_EP_CONFIG_CHOICE, func_index); + + return (REG_EP_CONFIG_DATA + reg); +} + +static bool +bcm_pcib_is_valid_quad(struct bcm_pcib_softc *sc, u_int bus, u_int slot, + u_int func, u_int reg) +{ + + if ((bus < sc->base.base.bus_start) || (bus > sc->base.base.bus_end)) + return (false); + if ((slot > PCI_SLOTMAX) || (func > PCI_FUNCMAX) || (reg > PCIE_REGMAX)) + return (false); + + if (bus == 0 && slot == 0 && func == 0) + return (true); + if (bus == 0) + /* + * Probing other slots and funcs on bus 0 will lock up the + * memory controller. + */ + return (false); + + return (true); +} + +static uint32_t +bcm_pcib_read_config(device_t dev, u_int bus, u_int slot, u_int func, u_int reg, + int bytes) +{ + struct bcm_pcib_softc *sc; + bus_space_handle_t h; + bus_space_tag_t t; + bus_addr_t offset; + uint32_t data; + + sc = device_get_softc(dev); + if (!bcm_pcib_is_valid_quad(sc, bus, slot, func, reg)) + return (~0U); + + mtx_lock(&sc->config_mtx); + offset = bcm_get_offset_and_prepare_config(sc, bus, slot, func, reg); + + t = sc->base.base.bst; + h = sc->base.base.bsh; + + switch (bytes) { + case 1: + data = bus_space_read_1(t, h, offset); + break; + case 2: + data = le16toh(bus_space_read_2(t, h, offset)); + break; + case 4: + data = le32toh(bus_space_read_4(t, h, offset)); + break; + default: + data = ~0U; + break; + } + + mtx_unlock(&sc->config_mtx); + return (data); +} + +static void +bcm_pcib_write_config(device_t dev, u_int bus, u_int slot, + u_int func, u_int reg, uint32_t val, int bytes) +{ + struct bcm_pcib_softc *sc; + bus_space_handle_t h; + bus_space_tag_t t; + uint32_t offset; + + sc = device_get_softc(dev); + if (!bcm_pcib_is_valid_quad(sc, bus, slot, func, reg)) + return; + + mtx_lock(&sc->config_mtx); + offset = bcm_get_offset_and_prepare_config(sc, bus, slot, func, reg); + + t = sc->base.base.bst; + h = sc->base.base.bsh; + + switch (bytes) { + case 1: + bus_space_write_1(t, h, offset, val); + break; + case 2: + bus_space_write_2(t, h, offset, htole16(val)); + break; + case 4: + bus_space_write_4(t, h, offset, htole32(val)); + break; + default: + break; + } + + mtx_unlock(&sc->config_mtx); +} + +static void +bcm_pcib_msi_intr_process(struct bcm_pcib_softc *sc, uint32_t interrupt_bitmap, + struct trapframe *tf) +{ + struct bcm_pcib_irqsrc *irqsrc; + uint32_t bit, irq; + + while ((bit = ffs(interrupt_bitmap))) { + irq = bit - 1; + + /* Acknowledge interrupt. */ + bcm_pcib_set_reg(sc, REG_MSI_CLR, 1 << irq); + + /* Send EOI. */ + bcm_pcib_set_reg(sc, REG_MSI_EOI, 1); + + /* Despatch to handler. */ + irqsrc = &sc->msi_isrcs[irq]; + if (intr_isrc_dispatch(&irqsrc->isrc, tf)) + device_printf(sc->dev, + "note: unexpected interrupt (%d) triggered.\n", + irq); + + /* Done with this interrupt. */ + interrupt_bitmap = interrupt_bitmap & ~(1 << irq); + } +} + +static int +bcm_pcib_msi_intr(void *arg) +{ + struct bcm_pcib_softc *sc; + struct trapframe *tf; + uint32_t interrupt_bitmap; + + sc = (struct bcm_pcib_softc *) arg; + tf = curthread->td_intr_frame; + + while ((interrupt_bitmap = bcm_pcib_read_reg(sc, REG_MSI_RAISED))) + bcm_pcib_msi_intr_process(sc, interrupt_bitmap, tf); + + return (FILTER_HANDLED); +} + +static int +bcm_pcib_alloc_msi(device_t dev, device_t child, int count, int maxcount, + device_t *pic, struct intr_irqsrc **srcs) +{ + struct bcm_pcib_softc *sc; + int first_int, i; + + sc = device_get_softc(dev); + mtx_lock(&sc->msi_mtx); + + /* Find a continguous region of free message-signalled interrupts. */ + for (first_int = 0; first_int + count < NUM_MSI; ) { + for (i = first_int; i < first_int + count; ++i) { + if (sc->msi_isrcs[i].allocated) + goto next; + } + goto found; +next: + first_int = i + 1; + } + + /* No appropriate region available. */ + mtx_unlock(&sc->msi_mtx); + device_printf(dev, "warning: failed to allocate %d MSI messages.\n", + count); + return (ENXIO); + +found: + /* Mark the messages as in use. */ + for (i = 0; i < count; ++i) { + sc->msi_isrcs[i + first_int].allocated = true; + srcs[i] = &(sc->msi_isrcs[i + first_int].isrc); + } + + mtx_unlock(&sc->msi_mtx); + *pic = device_get_parent(dev); + + return (0); +} + +static int +bcm_pcib_map_msi(device_t dev, device_t child, struct intr_irqsrc *isrc, + uint64_t *addr, uint32_t *data) +{ + struct bcm_pcib_softc *sc; + struct bcm_pcib_irqsrc *msi_msg; + + sc = device_get_softc(dev); + msi_msg = (struct bcm_pcib_irqsrc *) isrc; + + *addr = sc->msi_addr; + *data = (REG_VALUE_MSI_CONFIG & 0xffff) | msi_msg->irq; + return (0); +} + +static int +bcm_pcib_release_msi(device_t dev, device_t child, int count, + struct intr_irqsrc **isrc) +{ + struct bcm_pcib_softc *sc; + struct bcm_pcib_irqsrc *msi_isrc; + int i; + + sc = device_get_softc(dev); + mtx_lock(&sc->msi_mtx); + + for (i = 0; i < count; i++) { + msi_isrc = (struct bcm_pcib_irqsrc *) isrc[i]; + msi_isrc->allocated = false; + } + + mtx_unlock(&sc->msi_mtx); + return (0); +} + +static int +bcm_pcib_msi_attach(device_t dev) +{ + struct bcm_pcib_softc *sc; + phandle_t node, xref; + char const *bcm_name; + int i, rid; + + sc = device_get_softc(dev); + sc->msi_addr = 0xffffffffc; + + /* Clear any pending interrupts. */ + bcm_pcib_set_reg(sc, REG_MSI_CLR, 0xffffffff); + + rid = 1; + sc->msi_irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, + RF_ACTIVE); + if (sc->msi_irq_res == NULL) { + device_printf(dev, "could not allocate MSI irq resource.\n"); + return (ENXIO); + } + + sc->msi_isrcs = malloc(sizeof(*sc->msi_isrcs) * NUM_MSI, M_DEVBUF, + M_WAITOK | M_ZERO); + + int error = bus_setup_intr(dev, sc->msi_irq_res, INTR_TYPE_BIO | + INTR_MPSAFE, bcm_pcib_msi_intr, NULL, sc, &sc->msi_intr_cookie); + if (error) { + device_printf(dev, "error: failed to setup MSI handler.\n"); + return (ENXIO); + } + + bcm_name = device_get_nameunit(dev); + for (i = 0; i < NUM_MSI; i++) { + sc->msi_isrcs[i].irq = i; + error = intr_isrc_register(&sc->msi_isrcs[i].isrc, dev, 0, + "%s,%u", bcm_name, i); + if (error) { + device_printf(dev, + "error: failed to register interrupt %d.\n", i); + return (ENXIO); + } + } + + node = ofw_bus_get_node(dev); + xref = OF_xref_from_node(node); + OF_device_register_xref(xref, dev); + + error = intr_msi_register(dev, xref); + if (error) + return (ENXIO); + + mtx_init(&sc->msi_mtx, "bcm_pcib: msi_mtx", NULL, MTX_DEF); + + bcm_pcib_set_reg(sc, REG_MSI_MASK_CLR, 0xffffffff); + bcm_pcib_set_reg(sc, REG_MSI_ADDR_LOW, (sc->msi_addr & 0xffffffff) | 1); + bcm_pcib_set_reg(sc, REG_MSI_ADDR_HIGH, (sc->msi_addr >> 32)); + bcm_pcib_set_reg(sc, REG_MSI_CONFIG, REG_VALUE_MSI_CONFIG); + + return (0); +} + +static void +bcm_pcib_relocate_bridge_window(device_t dev) +{ + /* + * In principle an out-of-bounds bridge window could be automatically + * adjusted at resource-activation time to lie within the bus address + * space by pcib_grow_window(), but that is not possible because the + * out-of-bounds resource allocation fails at allocation time. Instead, + * we will just fix up the window on the controller here, before it is + * re-discovered by pcib_probe_windows(). + */ + + struct bcm_pcib_softc *sc; + pci_addr_t base, size, new_base, new_limit; + uint16_t val; + + sc = device_get_softc(dev); + + val = bcm_pcib_read_config(dev, 0, 0, 0, PCIR_MEMBASE_1, 2); + base = PCI_PPBMEMBASE(0, val); + + val = bcm_pcib_read_config(dev, 0, 0, 0, PCIR_MEMLIMIT_1, 2); + size = PCI_PPBMEMLIMIT(0, val) - base; + + new_base = sc->base.base.ranges[0].pci_base; + val = (uint16_t) (new_base >> 16); + bcm_pcib_write_config(dev, 0, 0, 0, PCIR_MEMBASE_1, val, 2); + + new_limit = new_base + size; + val = (uint16_t) (new_limit >> 16); + bcm_pcib_write_config(dev, 0, 0, 0, PCIR_MEMLIMIT_1, val, 2); +} + +static uint32_t +encode_cpu_window_low(pci_addr_t phys_base, bus_size_t size) +{ + + return (((phys_base >> 0x10) & 0xfff0) | + ((phys_base + size - 1) & 0xfff00000)); +} + +static uint32_t +encode_cpu_window_start_high(pci_addr_t phys_base) +{ + + return ((phys_base >> 0x20) & 0xff); +} + +static uint32_t +encode_cpu_window_end_high(pci_addr_t phys_base, bus_size_t size) +{ + + return (((phys_base + size - 1) >> 0x20) & 0xff); +} + +static int +bcm_pcib_attach(device_t dev) +{ + struct bcm_pcib_softc *sc; + pci_addr_t phys_base, pci_base; + bus_size_t size; + uint32_t hardware_rev, bridge_state, link_state; + int error, tries; + + sc = device_get_softc(dev); + sc->dev = dev; + + error = pci_host_generic_setup_fdt(dev); + if (error) + return (error); + + error = bcm_pcib_check_ranges(dev); + if (error) + return (error); + + mtx_init(&sc->config_mtx, "bcm_pcib: config_mtx", NULL, MTX_DEF); + + bcm_pcib_reset_controller(sc); + + hardware_rev = bcm_pcib_read_reg(sc, REG_CONTROLLER_HW_REV) & 0xffff; + device_printf(dev, "hardware identifies as revision 0x%x.\n", + hardware_rev); + + /* + * Set PCI->CPU memory window. This encodes the inbound window showing + * up to 4 GiB of system memory to the controller, with zero offset. + * Thus, from the perspective of a device on the PCI-E bus, there is a + * 1:1 map from PCI-E bus addresses to system memory addresses. However, + * a hardware limitation means that the controller can only perform DMA + * on the lower 3 GiB of system memory. + */ + bcm_pcib_set_reg(sc, REG_BRIDGE_MEM_WINDOW_LOW, REG_VALUE_4GB_WINDOW); + bcm_pcib_set_reg(sc, REG_BRIDGE_MEM_WINDOW_HIGH, 0); + bcm_pcib_set_reg(sc, REG_BRIDGE_CONFIG, REG_VALUE_4GB_CONFIG); + bcm_pcib_set_reg(sc, REG_BRIDGE_GISB_WINDOW, 0); + bcm_pcib_set_reg(sc, REG_BRIDGE_MEM_WINDOW_1, 0); + + bcm_pcib_enable_controller(sc); + + /* Wait for controller to start. */ + for(tries = 0; ; ++tries) { + bridge_state = bcm_pcib_read_reg(sc, REG_BRIDGE_STATE); + + if ((bridge_state & 0x30) == 0x30) + /* Controller ready. */ + break; + + if (tries > 100) { + device_printf(dev, + "error: controller failed to start.\n"); + return (ENXIO); + } + + DELAY(1000); + } + + link_state = bcm_pcib_read_reg(sc, REG_BRIDGE_LINK_STATE) >> 0x10; + if (!link_state) { + device_printf(dev, "error: controller started but link is not " + "up.\n"); + return (ENXIO); + } + if (bootverbose) + device_printf(dev, "note: reported link speed is %s.\n", + bcm_pcib_link_state_string(link_state)); + + /* + * Set the CPU->PCI memory window. The map in this direction is not 1:1. + * Addresses seen by the CPU need to be adjusted to make sense to the + * controller as they pass through the window. + */ + pci_base = sc->base.base.ranges[0].pci_base; + phys_base = sc->base.base.ranges[0].phys_base; + size = sc->base.base.ranges[0].size; + + bcm_pcib_set_reg(sc, REG_BRIDGE_BUS_WINDOW_LOW, pci_base & 0xffffffff); + bcm_pcib_set_reg(sc, REG_BRIDGE_BUS_WINDOW_HIGH, pci_base >> 32); + + bcm_pcib_set_reg(sc, REG_BRIDGE_CPU_WINDOW_LOW, + encode_cpu_window_low(phys_base, size)); + bcm_pcib_set_reg(sc, REG_BRIDGE_CPU_WINDOW_START_HIGH, + encode_cpu_window_start_high(phys_base)); + bcm_pcib_set_reg(sc, REG_BRIDGE_CPU_WINDOW_END_HIGH, + encode_cpu_window_end_high(phys_base, size)); + + /* + * The controller starts up declaring itself an endpoint; readvertise it + * as a bridge. + */ + bcm_pcib_set_reg(sc, PCI_ID_VAL3, + PCIC_BRIDGE << CLASS_SHIFT | PCIS_BRIDGE_PCI << SUBCLASS_SHIFT); + + bcm_pcib_set_reg(sc, REG_BRIDGE_SERDES_MODE, 0x2); + DELAY(100); + + bcm_pcib_relocate_bridge_window(dev); + + /* Configure interrupts. */ + error = bcm_pcib_msi_attach(dev); + if (error) + return (error); + + /* Done. */ + device_add_child(dev, "pci", -1); + return (bus_generic_attach(dev)); +} + +/* + * Device method table. + */ +static device_method_t bcm_pcib_methods[] = { + /* Device interface. */ + DEVMETHOD(device_probe, bcm_pcib_probe), + DEVMETHOD(device_attach, bcm_pcib_attach), + + /* PCIB interface. */ + DEVMETHOD(pcib_read_config, bcm_pcib_read_config), + DEVMETHOD(pcib_write_config, bcm_pcib_write_config), + + /* MSI interface. */ + DEVMETHOD(msi_alloc_msi, bcm_pcib_alloc_msi), + DEVMETHOD(msi_release_msi, bcm_pcib_release_msi), + DEVMETHOD(msi_map_msi, bcm_pcib_map_msi), + + DEVMETHOD_END +}; + +DEFINE_CLASS_1(pcib, bcm_pcib_driver, bcm_pcib_methods, + sizeof(struct bcm_pcib_softc), generic_pcie_fdt_driver); + +static devclass_t bcm_pcib_devclass; +DRIVER_MODULE(pcib, simplebus, bcm_pcib_driver, bcm_pcib_devclass, 0, 0); + Property changes on: head/sys/arm/broadcom/bcm2835/bcm2838_pci.c ___________________________________________________________________ Added: svn:keywords ## -0,0 +1 ## +FreeBSD=%H \ No newline at end of property Index: head/sys/arm/broadcom/bcm2835/files.bcm283x =================================================================== --- head/sys/arm/broadcom/bcm2835/files.bcm283x (revision 362953) +++ head/sys/arm/broadcom/bcm2835/files.bcm283x (revision 362954) @@ -1,45 +1,46 @@ # $FreeBSD$ arm/broadcom/bcm2835/bcm2835_bsc.c optional bcm2835_bsc arm/broadcom/bcm2835/bcm2835_cpufreq.c standard arm/broadcom/bcm2835/bcm2835_dma.c standard arm/broadcom/bcm2835/bcm2835_fb.c optional sc arm/broadcom/bcm2835/bcm2835_fbd.c optional vt arm/broadcom/bcm2835/bcm2835_ft5406.c optional evdev bcm2835_ft5406 arm/broadcom/bcm2835/bcm2835_gpio.c optional gpio arm/broadcom/bcm2835/bcm2835_intr.c standard arm/broadcom/bcm2835/bcm2835_machdep.c optional platform arm/broadcom/bcm2835/bcm2835_mbox.c standard arm/broadcom/bcm2835/bcm2835_rng.c optional random arm/broadcom/bcm2835/bcm2835_sdhci.c optional sdhci arm/broadcom/bcm2835/bcm2835_sdhost.c optional sdhci arm/broadcom/bcm2835/bcm2835_spi.c optional bcm2835_spi arm/broadcom/bcm2835/bcm2835_vcbus.c standard arm/broadcom/bcm2835/bcm2835_vcio.c standard arm/broadcom/bcm2835/bcm2835_wdog.c standard +arm/broadcom/bcm2835/bcm2838_pci.c optional pci arm/broadcom/bcm2835/bcm283x_dwc_fdt.c optional dwcotg fdt dev/mbox/mbox_if.m standard arm/broadcom/bcm2835/bcm2835_audio.c optional sound vchiq \ compile-with "${NORMAL_C} -DUSE_VCHIQ_ARM -D__VCCOREVER__=0x04000000 -I$S/contrib/vchiq" # VideoCore driver contrib/vchiq/interface/compat/vchi_bsd.c optional vchiq \ compile-with "${NORMAL_C} -DUSE_VCHIQ_ARM -D__VCCOREVER__=0x04000000 -I$S/contrib/vchiq" contrib/vchiq/interface/vchiq_arm/vchiq_2835_arm.c optional vchiq \ compile-with "${NORMAL_C} -Wno-unused -DUSE_VCHIQ_ARM -D__VCCOREVER__=0x04000000 -I$S/contrib/vchiq" contrib/vchiq/interface/vchiq_arm/vchiq_arm.c optional vchiq \ compile-with "${NORMAL_C} -Wno-unused -DUSE_VCHIQ_ARM -D__VCCOREVER__=0x04000000 -I$S/contrib/vchiq" contrib/vchiq/interface/vchiq_arm/vchiq_connected.c optional vchiq \ compile-with "${NORMAL_C} -DUSE_VCHIQ_ARM -D__VCCOREVER__=0x04000000 -I$S/contrib/vchiq" contrib/vchiq/interface/vchiq_arm/vchiq_core.c optional vchiq \ compile-with "${NORMAL_C} -DUSE_VCHIQ_ARM -D__VCCOREVER__=0x04000000 -I$S/contrib/vchiq" contrib/vchiq/interface/vchiq_arm/vchiq_kern_lib.c optional vchiq \ compile-with "${NORMAL_C} -DUSE_VCHIQ_ARM -D__VCCOREVER__=0x04000000 -I$S/contrib/vchiq" contrib/vchiq/interface/vchiq_arm/vchiq_kmod.c optional vchiq \ compile-with "${NORMAL_C} -DUSE_VCHIQ_ARM -D__VCCOREVER__=0x04000000 -I$S/contrib/vchiq" contrib/vchiq/interface/vchiq_arm/vchiq_shim.c optional vchiq \ compile-with "${NORMAL_C} -DUSE_VCHIQ_ARM -D__VCCOREVER__=0x04000000 -I$S/contrib/vchiq" contrib/vchiq/interface/vchiq_arm/vchiq_util.c optional vchiq \ compile-with "${NORMAL_C} -DUSE_VCHIQ_ARM -D__VCCOREVER__=0x04000000 -I$S/contrib/vchiq" Index: head/sys/conf/files.arm64 =================================================================== --- head/sys/conf/files.arm64 (revision 362953) +++ head/sys/conf/files.arm64 (revision 362954) @@ -1,412 +1,413 @@ # $FreeBSD$ cloudabi32_vdso.o optional compat_cloudabi32 \ dependency "$S/contrib/cloudabi/cloudabi_vdso_armv6_on_64bit.S" \ compile-with "${CC} -x assembler-with-cpp -m32 -shared -nostdinc -nostdlib -Wl,-T$S/compat/cloudabi/cloudabi_vdso.lds $S/contrib/cloudabi/cloudabi_vdso_armv6_on_64bit.S -o ${.TARGET}" \ no-obj no-implicit-rule \ clean "cloudabi32_vdso.o" # cloudabi32_vdso_blob.o optional compat_cloudabi32 \ dependency "cloudabi32_vdso.o" \ compile-with "${OBJCOPY} --input-target binary --output-target elf64-littleaarch64 --binary-architecture aarch64 cloudabi32_vdso.o ${.TARGET}" \ no-implicit-rule \ clean "cloudabi32_vdso_blob.o" # cloudabi64_vdso.o optional compat_cloudabi64 \ dependency "$S/contrib/cloudabi/cloudabi_vdso_aarch64.S" \ compile-with "${CC} -x assembler-with-cpp -shared -nostdinc -nostdlib -Wl,-T$S/compat/cloudabi/cloudabi_vdso.lds $S/contrib/cloudabi/cloudabi_vdso_aarch64.S -o ${.TARGET}" \ no-obj no-implicit-rule \ clean "cloudabi64_vdso.o" # cloudabi64_vdso_blob.o optional compat_cloudabi64 \ dependency "cloudabi64_vdso.o" \ compile-with "${OBJCOPY} --input-target binary --output-target elf64-littleaarch64 --binary-architecture aarch64 cloudabi64_vdso.o ${.TARGET}" \ no-implicit-rule \ clean "cloudabi64_vdso_blob.o" # # Allwinner common files arm/allwinner/a10_timer.c optional a10_timer fdt arm/allwinner/a10_codec.c optional sound a10_codec arm/allwinner/a31_dmac.c optional a31_dmac arm/allwinner/sunxi_dma_if.m optional a31_dmac arm/allwinner/aw_cir.c optional evdev aw_cir fdt arm/allwinner/aw_dwc3.c optional aw_dwc3 fdt arm/allwinner/aw_gpio.c optional gpio aw_gpio fdt arm/allwinner/aw_mmc.c optional mmc aw_mmc fdt | mmccam aw_mmc fdt arm/allwinner/aw_nmi.c optional aw_nmi fdt \ compile-with "${NORMAL_C} -I$S/gnu/dts/include" arm/allwinner/aw_pwm.c optional aw_pwm fdt arm/allwinner/aw_rsb.c optional aw_rsb fdt arm/allwinner/aw_rtc.c optional aw_rtc fdt arm/allwinner/aw_sid.c optional aw_sid nvmem fdt arm/allwinner/aw_spi.c optional aw_spi fdt arm/allwinner/aw_syscon.c optional aw_syscon ext_resources syscon fdt arm/allwinner/aw_thermal.c optional aw_thermal nvmem fdt arm/allwinner/aw_usbphy.c optional ehci aw_usbphy fdt arm/allwinner/aw_usb3phy.c optional xhci aw_usbphy fdt arm/allwinner/aw_wdog.c optional aw_wdog fdt arm/allwinner/axp81x.c optional axp81x fdt arm/allwinner/if_awg.c optional awg ext_resources syscon aw_sid nvmem fdt # Allwinner clock driver arm/allwinner/clkng/aw_ccung.c optional aw_ccu fdt arm/allwinner/clkng/aw_clk_frac.c optional aw_ccu fdt arm/allwinner/clkng/aw_clk_m.c optional aw_ccu fdt arm/allwinner/clkng/aw_clk_mipi.c optional aw_ccu fdt arm/allwinner/clkng/aw_clk_nkmp.c optional aw_ccu fdt arm/allwinner/clkng/aw_clk_nm.c optional aw_ccu fdt arm/allwinner/clkng/aw_clk_nmm.c optional aw_ccu fdt arm/allwinner/clkng/aw_clk_np.c optional aw_ccu fdt arm/allwinner/clkng/aw_clk_prediv_mux.c optional aw_ccu fdt arm/allwinner/clkng/ccu_a64.c optional soc_allwinner_a64 aw_ccu fdt arm/allwinner/clkng/ccu_h3.c optional soc_allwinner_h5 aw_ccu fdt arm/allwinner/clkng/ccu_h6.c optional soc_allwinner_h6 aw_ccu fdt arm/allwinner/clkng/ccu_h6_r.c optional soc_allwinner_h6 aw_ccu fdt arm/allwinner/clkng/ccu_sun8i_r.c optional aw_ccu fdt arm/allwinner/clkng/ccu_de2.c optional aw_ccu fdt # Allwinner padconf files arm/allwinner/a64/a64_padconf.c optional soc_allwinner_a64 fdt arm/allwinner/a64/a64_r_padconf.c optional soc_allwinner_a64 fdt arm/allwinner/h3/h3_padconf.c optional soc_allwinner_h5 fdt arm/allwinner/h3/h3_r_padconf.c optional soc_allwinner_h5 fdt arm/allwinner/h6/h6_padconf.c optional soc_allwinner_h6 fdt arm/allwinner/h6/h6_r_padconf.c optional soc_allwinner_h6 fdt arm/annapurna/alpine/alpine_ccu.c optional al_ccu fdt arm/annapurna/alpine/alpine_nb_service.c optional al_nb_service fdt arm/annapurna/alpine/alpine_pci.c optional al_pci fdt arm/annapurna/alpine/alpine_pci_msix.c optional al_pci fdt arm/annapurna/alpine/alpine_serdes.c optional al_serdes fdt \ no-depend \ compile-with "${CC} -c -o ${.TARGET} ${CFLAGS} -I$S/contrib/alpine-hal -I$S/contrib/alpine-hal/eth ${PROF} ${.IMPSRC}" arm/arm/generic_timer.c standard arm/arm/gic.c standard arm/arm/gic_acpi.c optional acpi arm/arm/gic_fdt.c optional fdt arm/arm/pmu.c standard arm/broadcom/bcm2835/bcm2835_audio.c optional sound vchiq fdt \ compile-with "${NORMAL_C} -DUSE_VCHIQ_ARM -D__VCCOREVER__=0x04000000 -I$S/contrib/vchiq" arm/broadcom/bcm2835/bcm2835_bsc.c optional bcm2835_bsc fdt arm/broadcom/bcm2835/bcm2835_clkman.c optional soc_brcm_bcm2837 fdt | soc_brcm_bcm2838 fdt arm/broadcom/bcm2835/bcm2835_cpufreq.c optional soc_brcm_bcm2837 fdt | soc_brcm_bcm2838 fdt arm/broadcom/bcm2835/bcm2835_dma.c optional soc_brcm_bcm2837 fdt | soc_brcm_bcm2838 fdt arm/broadcom/bcm2835/bcm2835_fbd.c optional vt soc_brcm_bcm2837 fdt | vt soc_brcm_bcm2838 fdt arm/broadcom/bcm2835/bcm2835_ft5406.c optional evdev bcm2835_ft5406 fdt arm/broadcom/bcm2835/bcm2835_gpio.c optional gpio soc_brcm_bcm2837 fdt | gpio soc_brcm_bcm2838 fdt arm/broadcom/bcm2835/bcm2835_intr.c optional soc_brcm_bcm2837 fdt | soc_brcm_bcm2838 fdt arm/broadcom/bcm2835/bcm2835_mbox.c optional soc_brcm_bcm2837 fdt | soc_brcm_bcm2838 fdt arm/broadcom/bcm2835/bcm2835_rng.c optional !random_loadable soc_brcm_bcm2837 fdt | !random_loadable soc_brcm_bcm2838 fdt arm/broadcom/bcm2835/bcm2835_sdhci.c optional sdhci soc_brcm_bcm2837 fdt | sdhci soc_brcm_bcm2838 fdt arm/broadcom/bcm2835/bcm2835_sdhost.c optional sdhci soc_brcm_bcm2837 fdt | sdhci soc_brcm_bcm2838 fdt arm/broadcom/bcm2835/bcm2835_spi.c optional bcm2835_spi fdt arm/broadcom/bcm2835/bcm2835_vcbus.c optional soc_brcm_bcm2837 fdt | soc_brcm_bcm2838 fdt arm/broadcom/bcm2835/bcm2835_vcio.c optional soc_brcm_bcm2837 fdt | soc_brcm_bcm2838 fdt arm/broadcom/bcm2835/bcm2835_wdog.c optional soc_brcm_bcm2837 fdt | soc_brcm_bcm2838 fdt arm/broadcom/bcm2835/bcm2836.c optional soc_brcm_bcm2837 fdt | soc_brcm_bcm2838 fdt arm/broadcom/bcm2835/bcm283x_dwc_fdt.c optional dwcotg fdt soc_brcm_bcm2837 | dwcotg fdt soc_brcm_bcm2838 +arm/broadcom/bcm2835/bcm2838_pci.c optional soc_brcm_bcm2838 fdt pci arm/freescale/vybrid/vf_i2c.c optional vf_i2c iicbus SOC_NXP_LS arm/mv/a37x0_gpio.c optional a37x0_gpio gpio fdt arm/mv/a37x0_iic.c optional a37x0_iic iicbus fdt arm/mv/a37x0_spi.c optional a37x0_spi spibus fdt arm/mv/armada38x/armada38x_rtc.c optional mv_rtc fdt arm/mv/gpio.c optional mv_gpio fdt arm/mv/mvebu_gpio.c optional mv_gpio fdt arm/mv/mvebu_pinctrl.c optional mvebu_pinctrl fdt arm/mv/mv_ap806_clock.c optional SOC_MARVELL_8K fdt arm/mv/mv_ap806_gicp.c optional mv_ap806_gicp fdt arm/mv/mv_ap806_sei.c optional mv_ap806_sei fdt arm/mv/mv_cp110_clock.c optional SOC_MARVELL_8K fdt arm/mv/mv_cp110_icu.c optional mv_cp110_icu fdt arm/mv/mv_cp110_icu_bus.c optional mv_cp110_icu fdt arm/mv/mv_thermal.c optional SOC_MARVELL_8K mv_thermal fdt arm/mv/armada38x/armada38x_rtc.c optional mv_rtc fdt arm/xilinx/uart_dev_cdnc.c optional uart soc_xilinx_zynq arm64/acpica/acpi_iort.c optional acpi arm64/acpica/acpi_machdep.c optional acpi arm64/acpica/OsdEnvironment.c optional acpi arm64/acpica/acpi_wakeup.c optional acpi arm64/acpica/pci_cfgreg.c optional acpi pci arm64/arm64/autoconf.c standard arm64/arm64/bus_machdep.c standard arm64/arm64/bus_space_asm.S standard arm64/arm64/busdma_bounce.c standard arm64/arm64/busdma_machdep.c standard arm64/arm64/bzero.S standard arm64/arm64/clock.c standard arm64/arm64/copyinout.S standard arm64/arm64/cpu_errata.c standard arm64/arm64/cpufunc_asm.S standard arm64/arm64/db_disasm.c optional ddb arm64/arm64/db_interface.c optional ddb arm64/arm64/db_trace.c optional ddb arm64/arm64/debug_monitor.c standard arm64/arm64/disassem.c optional ddb arm64/arm64/dump_machdep.c standard arm64/arm64/efirt_machdep.c optional efirt arm64/arm64/elf32_machdep.c optional compat_freebsd32 arm64/arm64/elf_machdep.c standard arm64/arm64/exception.S standard arm64/arm64/freebsd32_machdep.c optional compat_freebsd32 arm64/arm64/gicv3_its.c optional intrng fdt arm64/arm64/gic_v3.c standard arm64/arm64/gic_v3_acpi.c optional acpi arm64/arm64/gic_v3_fdt.c optional fdt arm64/arm64/identcpu.c standard arm64/arm64/in_cksum.c optional inet | inet6 arm64/arm64/locore.S standard no-obj arm64/arm64/machdep.c standard arm64/arm64/machdep_boot.c standard arm64/arm64/mem.c standard arm64/arm64/memcpy.S standard arm64/arm64/memmove.S standard arm64/arm64/minidump_machdep.c standard arm64/arm64/mp_machdep.c optional smp arm64/arm64/nexus.c standard arm64/arm64/ofw_machdep.c optional fdt arm64/arm64/pmap.c standard arm64/arm64/stack_machdep.c optional ddb | stack arm64/arm64/support.S standard arm64/arm64/swtch.S standard arm64/arm64/sys_machdep.c standard arm64/arm64/trap.c standard arm64/arm64/uio_machdep.c standard arm64/arm64/uma_machdep.c standard arm64/arm64/undefined.c standard arm64/arm64/unwind.c optional ddb | kdtrace_hooks | stack arm64/arm64/vfp.c standard arm64/arm64/vm_machdep.c standard arm64/broadcom/brcmmdio/mdio_mux_iproc.c optional fdt arm64/broadcom/brcmmdio/mdio_nexus_iproc.c optional fdt arm64/broadcom/brcmmdio/mdio_ns2_pcie_phy.c optional fdt pci arm64/broadcom/genet/if_genet.c optional SOC_BRCM_BCM2838 fdt genet arm64/cavium/thunder_pcie_fdt.c optional soc_cavm_thunderx pci fdt arm64/cavium/thunder_pcie_pem.c optional soc_cavm_thunderx pci arm64/cavium/thunder_pcie_pem_fdt.c optional soc_cavm_thunderx pci fdt arm64/cavium/thunder_pcie_common.c optional soc_cavm_thunderx pci arm64/cloudabi32/cloudabi32_sysvec.c optional compat_cloudabi32 arm64/cloudabi64/cloudabi64_sysvec.c optional compat_cloudabi64 arm64/coresight/coresight.c standard arm64/coresight/coresight_acpi.c optional acpi arm64/coresight/coresight_fdt.c optional fdt arm64/coresight/coresight_if.m standard arm64/coresight/coresight_cmd.c standard arm64/coresight/coresight_cpu_debug.c standard arm64/coresight/coresight_etm4x.c standard arm64/coresight/coresight_etm4x_acpi.c optional acpi arm64/coresight/coresight_etm4x_fdt.c optional fdt arm64/coresight/coresight_funnel.c standard arm64/coresight/coresight_funnel_acpi.c optional acpi arm64/coresight/coresight_funnel_fdt.c optional fdt arm64/coresight/coresight_replicator.c standard arm64/coresight/coresight_replicator_acpi.c optional acpi arm64/coresight/coresight_replicator_fdt.c optional fdt arm64/coresight/coresight_tmc.c standard arm64/coresight/coresight_tmc_acpi.c optional acpi arm64/coresight/coresight_tmc_fdt.c optional fdt arm64/intel/firmware.c optional soc_intel_stratix10 arm64/intel/stratix10-soc-fpga-mgr.c optional soc_intel_stratix10 arm64/intel/stratix10-svc.c optional soc_intel_stratix10 arm64/qoriq/ls1046_gpio.c optional ls1046_gpio gpio fdt SOC_NXP_LS arm64/qoriq/clk/ls1046a_clkgen.c optional clk SOC_NXP_LS arm64/qoriq/clk/qoriq_clk_pll.c optional clk SOC_NXP_LS arm64/qoriq/clk/qoriq_clkgen.c optional clk SOC_NXP_LS arm64/qualcomm/qcom_gcc.c optional qcom_gcc fdt contrib/vchiq/interface/compat/vchi_bsd.c optional vchiq soc_brcm_bcm2837 \ compile-with "${NORMAL_C} -DUSE_VCHIQ_ARM -D__VCCOREVER__=0x04000000 -I$S/contrib/vchiq" contrib/vchiq/interface/vchiq_arm/vchiq_2835_arm.c optional vchiq soc_brcm_bcm2837 \ compile-with "${NORMAL_C} -Wno-unused -DUSE_VCHIQ_ARM -D__VCCOREVER__=0x04000000 -I$S/contrib/vchiq" contrib/vchiq/interface/vchiq_arm/vchiq_arm.c optional vchiq soc_brcm_bcm2837 \ compile-with "${NORMAL_C} -Wno-unused -DUSE_VCHIQ_ARM -D__VCCOREVER__=0x04000000 -I$S/contrib/vchiq" contrib/vchiq/interface/vchiq_arm/vchiq_connected.c optional vchiq soc_brcm_bcm2837 \ compile-with "${NORMAL_C} -DUSE_VCHIQ_ARM -D__VCCOREVER__=0x04000000 -I$S/contrib/vchiq" contrib/vchiq/interface/vchiq_arm/vchiq_core.c optional vchiq soc_brcm_bcm2837 \ compile-with "${NORMAL_C} -DUSE_VCHIQ_ARM -D__VCCOREVER__=0x04000000 -I$S/contrib/vchiq" contrib/vchiq/interface/vchiq_arm/vchiq_kern_lib.c optional vchiq soc_brcm_bcm2837 \ compile-with "${NORMAL_C} -DUSE_VCHIQ_ARM -D__VCCOREVER__=0x04000000 -I$S/contrib/vchiq" contrib/vchiq/interface/vchiq_arm/vchiq_kmod.c optional vchiq soc_brcm_bcm2837 \ compile-with "${NORMAL_C} -DUSE_VCHIQ_ARM -D__VCCOREVER__=0x04000000 -I$S/contrib/vchiq" contrib/vchiq/interface/vchiq_arm/vchiq_shim.c optional vchiq soc_brcm_bcm2837 \ compile-with "${NORMAL_C} -DUSE_VCHIQ_ARM -D__VCCOREVER__=0x04000000 -I$S/contrib/vchiq" contrib/vchiq/interface/vchiq_arm/vchiq_util.c optional vchiq soc_brcm_bcm2837 \ compile-with "${NORMAL_C} -DUSE_VCHIQ_ARM -D__VCCOREVER__=0x04000000 -I$S/contrib/vchiq" crypto/armv8/armv8_crypto.c optional armv8crypto armv8_crypto_wrap.o optional armv8crypto \ dependency "$S/crypto/armv8/armv8_crypto_wrap.c" \ compile-with "${CC} -c ${CFLAGS:C/^-O2$/-O3/:N-nostdinc:N-mgeneral-regs-only} -I$S/crypto/armv8/ ${WERROR} ${NO_WCAST_QUAL} ${PROF} -march=armv8-a+crypto ${.IMPSRC}" \ no-implicit-rule \ clean "armv8_crypto_wrap.o" crypto/des/des_enc.c optional netsmb dev/acpica/acpi_bus_if.m optional acpi dev/acpica/acpi_if.m optional acpi dev/acpica/acpi_pci_link.c optional acpi pci dev/acpica/acpi_pcib.c optional acpi pci dev/acpica/acpi_pxm.c optional acpi dev/ahci/ahci_fsl_fdt.c optional SOC_NXP_LS ahci fdt dev/ahci/ahci_generic.c optional ahci dev/altera/dwc/if_dwc_socfpga.c optional fdt dwc_socfpga dev/axgbe/if_axgbe.c optional axgbe dev/axgbe/xgbe-desc.c optional axgbe dev/axgbe/xgbe-dev.c optional axgbe dev/axgbe/xgbe-drv.c optional axgbe dev/axgbe/xgbe-mdio.c optional axgbe dev/cpufreq/cpufreq_dt.c optional cpufreq fdt dev/ice/if_ice_iflib.c optional ice pci \ compile-with "${NORMAL_C} -I$S/dev/ice" dev/ice/ice_lib.c optional ice pci \ compile-with "${NORMAL_C} -I$S/dev/ice" dev/ice/ice_osdep.c optional ice pci \ compile-with "${NORMAL_C} -I$S/dev/ice" dev/ice/ice_resmgr.c optional ice pci \ compile-with "${NORMAL_C} -I$S/dev/ice" dev/ice/ice_strings.c optional ice pci \ compile-with "${NORMAL_C} -I$S/dev/ice" dev/ice/ice_iflib_recovery_txrx.c optional ice pci \ compile-with "${NORMAL_C} -I$S/dev/ice" dev/ice/ice_iflib_txrx.c optional ice pci \ compile-with "${NORMAL_C} -I$S/dev/ice" dev/ice/ice_common.c optional ice pci \ compile-with "${NORMAL_C} -I$S/dev/ice" dev/ice/ice_controlq.c optional ice pci \ compile-with "${NORMAL_C} -I$S/dev/ice" dev/ice/ice_dcb.c optional ice pci \ compile-with "${NORMAL_C} -I$S/dev/ice" dev/ice/ice_flex_pipe.c optional ice pci \ compile-with "${NORMAL_C} -I$S/dev/ice" dev/ice/ice_flow.c optional ice pci \ compile-with "${NORMAL_C} -I$S/dev/ice" dev/ice/ice_nvm.c optional ice pci \ compile-with "${NORMAL_C} -I$S/dev/ice" dev/ice/ice_sched.c optional ice pci \ compile-with "${NORMAL_C} -I$S/dev/ice" dev/ice/ice_sriov.c optional ice pci \ compile-with "${NORMAL_C} -I$S/dev/ice" dev/ice/ice_switch.c optional ice pci \ compile-with "${NORMAL_C} -I$S/dev/ice" ice_ddp.c optional ice_ddp \ compile-with "${AWK} -f $S/tools/fw_stub.awk ice_ddp.fw:ice_ddp:0x01030900 -mice_ddp -c${.TARGET}" \ no-implicit-rule before-depend local \ clean "ice_ddp.c" ice_ddp.fwo optional ice_ddp \ dependency "ice_ddp.fw" \ compile-with "${NORMAL_FWO}" \ no-implicit-rule \ clean "ice_ddp.fwo" ice_ddp.fw optional ice_ddp \ dependency "$S/contrib/dev/ice/ice-1.3.9.0.pkg" \ compile-with "${CP} $S/contrib/dev/ice/ice-1.3.9.0.pkg ice_ddp.fw" \ no-obj no-implicit-rule \ clean "ice_ddp.fw" dev/iicbus/sy8106a.c optional sy8106a fdt dev/iicbus/twsi/mv_twsi.c optional twsi fdt dev/iicbus/twsi/a10_twsi.c optional twsi fdt dev/iicbus/twsi/twsi.c optional twsi fdt dev/hwpmc/hwpmc_arm64.c optional hwpmc dev/hwpmc/hwpmc_arm64_md.c optional hwpmc dev/mbox/mbox_if.m optional soc_brcm_bcm2837 dev/mmc/host/dwmmc.c optional dwmmc fdt dev/mmc/host/dwmmc_altera.c optional dwmmc dwmmc_altera fdt dev/mmc/host/dwmmc_hisi.c optional dwmmc dwmmc_hisi fdt dev/mmc/host/dwmmc_rockchip.c optional dwmmc rk_dwmmc fdt dev/neta/if_mvneta_fdt.c optional neta fdt dev/neta/if_mvneta.c optional neta mdio mii dev/ofw/ofw_cpu.c optional fdt dev/ofw/ofwpci.c optional fdt pci dev/pci/controller/pci_n1sdp.c optional pci_n1sdp acpi dev/pci/pci_host_generic.c optional pci dev/pci/pci_host_generic_acpi.c optional pci acpi dev/pci/pci_host_generic_fdt.c optional pci fdt dev/pci/pci_dw_mv.c optional pci fdt dev/pci/pci_dw.c optional pci fdt dev/pci/pci_dw_if.m optional pci fdt dev/psci/psci.c standard dev/psci/smccc_arm64.S standard dev/psci/smccc.c standard dev/sdhci/sdhci_xenon.c optional sdhci_xenon sdhci fdt dev/uart/uart_cpu_arm64.c optional uart dev/uart/uart_dev_mu.c optional uart uart_mu dev/uart/uart_dev_pl011.c optional uart pl011 dev/usb/controller/dwc_otg_hisi.c optional dwcotg fdt soc_hisi_hi6220 dev/usb/controller/dwc3.c optional fdt dwc3 dev/usb/controller/ehci_mv.c optional ehci_mv fdt dev/usb/controller/generic_ehci.c optional ehci dev/usb/controller/generic_ehci_acpi.c optional ehci acpi dev/usb/controller/generic_ehci_fdt.c optional ehci fdt dev/usb/controller/generic_ohci.c optional ohci fdt dev/usb/controller/generic_usb_if.m optional ohci fdt dev/usb/controller/usb_nop_xceiv.c optional fdt ext_resources dev/usb/controller/generic_xhci.c optional xhci dev/usb/controller/generic_xhci_acpi.c optional xhci acpi dev/usb/controller/generic_xhci_fdt.c optional xhci fdt dev/vnic/mrml_bridge.c optional vnic fdt dev/vnic/nic_main.c optional vnic pci dev/vnic/nicvf_main.c optional vnic pci pci_iov dev/vnic/nicvf_queues.c optional vnic pci pci_iov dev/vnic/thunder_bgx_fdt.c optional vnic fdt dev/vnic/thunder_bgx.c optional vnic pci dev/vnic/thunder_mdio_fdt.c optional vnic fdt dev/vnic/thunder_mdio.c optional vnic dev/vnic/lmac_if.m optional inet | inet6 | vnic kern/kern_clocksource.c standard kern/msi_if.m optional intrng kern/pic_if.m optional intrng kern/subr_devmap.c standard kern/subr_intr.c optional intrng kern/subr_physmem.c standard libkern/bcmp.c standard libkern/memcmp.c standard \ compile-with "${NORMAL_C:N-fsanitize*}" libkern/memset.c standard \ compile-with "${NORMAL_C:N-fsanitize*}" libkern/arm64/crc32c_armv8.S standard cddl/dev/dtrace/aarch64/dtrace_asm.S optional dtrace compile-with "${DTRACE_S}" cddl/dev/dtrace/aarch64/dtrace_subr.c optional dtrace compile-with "${DTRACE_C}" cddl/dev/fbt/aarch64/fbt_isa.c optional dtrace_fbt | dtraceall compile-with "${FBT_C}" # RockChip Drivers arm64/rockchip/rk3399_emmcphy.c optional fdt rk_emmcphy soc_rockchip_rk3399 arm64/rockchip/rk_dwc3.c optional fdt rk_dwc3 soc_rockchip_rk3399 arm64/rockchip/rk_i2c.c optional fdt rk_i2c soc_rockchip_rk3328 | fdt rk_i2c soc_rockchip_rk3399 arm64/rockchip/rk805.c optional fdt rk805 soc_rockchip_rk3328 | fdt rk805 soc_rockchip_rk3399 arm64/rockchip/rk_grf.c optional fdt soc_rockchip_rk3328 | fdt soc_rockchip_rk3399 arm64/rockchip/rk_pinctrl.c optional fdt rk_pinctrl soc_rockchip_rk3328 | fdt rk_pinctrl soc_rockchip_rk3399 arm64/rockchip/rk_gpio.c optional fdt rk_gpio soc_rockchip_rk3328 | fdt rk_gpio soc_rockchip_rk3399 arm64/rockchip/rk_iodomain.c optional fdt rk_iodomain arm64/rockchip/rk_spi.c optional fdt rk_spi arm64/rockchip/rk_usb2phy.c optional fdt rk_usb2phy soc_rockchip_rk3328 | soc_rockchip_rk3399 arm64/rockchip/rk_typec_phy.c optional fdt rk_typec_phy soc_rockchip_rk3399 arm64/rockchip/if_dwc_rk.c optional fdt dwc_rk soc_rockchip_rk3328 | fdt dwc_rk soc_rockchip_rk3399 arm64/rockchip/rk_tsadc_if.m optional fdt soc_rockchip_rk3399 arm64/rockchip/rk_tsadc.c optional fdt soc_rockchip_rk3399 arm64/rockchip/rk_pwm.c optional fdt rk_pwm arm64/rockchip/rk_pcie.c optional fdt pci soc_rockchip_rk3399 arm64/rockchip/rk_pcie_phy.c optional fdt pci soc_rockchip_rk3399 dev/dwc/if_dwc.c optional fdt dwc_rk soc_rockchip_rk3328 | fdt dwc_rk soc_rockchip_rk3399 dev/dwc/if_dwc_if.m optional fdt dwc_rk soc_rockchip_rk3328 | fdt dwc_rk soc_rockchip_rk3399 # RockChip Clock support arm64/rockchip/clk/rk_cru.c optional fdt soc_rockchip_rk3328 | fdt soc_rockchip_rk3399 arm64/rockchip/clk/rk_clk_armclk.c optional fdt soc_rockchip_rk3328 | fdt soc_rockchip_rk3399 arm64/rockchip/clk/rk_clk_composite.c optional fdt soc_rockchip_rk3328 | fdt soc_rockchip_rk3399 arm64/rockchip/clk/rk_clk_fract.c optional fdt soc_rockchip_rk3328 | fdt soc_rockchip_rk3399 arm64/rockchip/clk/rk_clk_gate.c optional fdt soc_rockchip_rk3328 | fdt soc_rockchip_rk3399 arm64/rockchip/clk/rk_clk_mux.c optional fdt soc_rockchip_rk3328 | fdt soc_rockchip_rk3399 arm64/rockchip/clk/rk_clk_pll.c optional fdt soc_rockchip_rk3328 | fdt soc_rockchip_rk3399 arm64/rockchip/clk/rk3328_cru.c optional fdt soc_rockchip_rk3328 arm64/rockchip/clk/rk3399_cru.c optional fdt soc_rockchip_rk3399 arm64/rockchip/clk/rk3399_pmucru.c optional fdt soc_rockchip_rk3399 # i.MX8 Clock support arm64/freescale/imx/imx8mq_ccm.c optional fdt soc_freescale_imx8 arm64/freescale/imx/clk/imx_clk_gate.c optional fdt soc_freescale_imx8 arm64/freescale/imx/clk/imx_clk_mux.c optional fdt soc_freescale_imx8 arm64/freescale/imx/clk/imx_clk_composite.c optional fdt soc_freescale_imx8 arm64/freescale/imx/clk/imx_clk_sscg_pll.c optional fdt soc_freescale_imx8 arm64/freescale/imx/clk/imx_clk_frac_pll.c optional fdt soc_freescale_imx8 # iMX drivers arm/freescale/imx/imx_gpio.c optional gpio arm/freescale/imx/imx_i2c.c optional fsliic arm/freescale/imx/imx_machdep.c standard arm64/freescale/imx/imx7gpc.c optional fdt soc_freescale_imx8 dev/ffec/if_ffec.c optional ffec Index: head/sys/dev/pci/pci_host_generic_fdt.c =================================================================== --- head/sys/dev/pci/pci_host_generic_fdt.c (revision 362953) +++ head/sys/dev/pci/pci_host_generic_fdt.c (revision 362954) @@ -1,558 +1,574 @@ /*- * Copyright (c) 2015 Ruslan Bukin * Copyright (c) 2014,2016 The FreeBSD Foundation * All rights reserved. * * This software was developed by Andrew Turner under * the sponsorship of the FreeBSD Foundation. * * This software was developed by Semihalf under * the sponsorship of the FreeBSD Foundation. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. */ /* Generic ECAM PCIe driver FDT attachment */ #include __FBSDID("$FreeBSD$"); #include "opt_platform.h" #include #include #include #include #include #include #include #if defined(INTRNG) #include #endif #include #include #include #include #include #include #include #include #include #include #include "pcib_if.h" #define SPACE_CODE_SHIFT 24 #define SPACE_CODE_MASK 0x3 #define SPACE_CODE_IO_SPACE 0x1 #define PROPS_CELL_SIZE 1 #define PCI_ADDR_CELL_SIZE 2 /* OFW bus interface */ struct generic_pcie_ofw_devinfo { struct ofw_bus_devinfo di_dinfo; struct resource_list di_rl; }; /* Forward prototypes */ static int generic_pcie_fdt_probe(device_t dev); static int parse_pci_mem_ranges(device_t, struct generic_pcie_core_softc *); static int generic_pcie_fdt_release_resource(device_t dev, device_t child, int type, int rid, struct resource *res); static int generic_pcie_ofw_bus_attach(device_t); static const struct ofw_bus_devinfo *generic_pcie_ofw_get_devinfo(device_t, device_t); static __inline void get_addr_size_cells(phandle_t node, pcell_t *addr_cells, pcell_t *size_cells) { *addr_cells = 2; /* Find address cells if present */ OF_getencprop(node, "#address-cells", addr_cells, sizeof(*addr_cells)); *size_cells = 2; /* Find size cells if present */ OF_getencprop(node, "#size-cells", size_cells, sizeof(*size_cells)); } static int generic_pcie_fdt_probe(device_t dev) { if (!ofw_bus_status_okay(dev)) return (ENXIO); if (ofw_bus_is_compatible(dev, "pci-host-ecam-generic")) { device_set_desc(dev, "Generic PCI host controller"); return (BUS_PROBE_GENERIC); } if (ofw_bus_is_compatible(dev, "arm,gem5_pcie")) { device_set_desc(dev, "GEM5 PCIe host controller"); return (BUS_PROBE_DEFAULT); } return (ENXIO); } int -pci_host_generic_attach(device_t dev) +pci_host_generic_setup_fdt(device_t dev) { struct generic_pcie_fdt_softc *sc; phandle_t node; int error; sc = device_get_softc(dev); /* Retrieve 'ranges' property from FDT */ if (bootverbose) device_printf(dev, "parsing FDT for ECAM%d:\n", sc->base.ecam); if (parse_pci_mem_ranges(dev, &sc->base)) return (ENXIO); /* Attach OFW bus */ if (generic_pcie_ofw_bus_attach(dev) != 0) return (ENXIO); node = ofw_bus_get_node(dev); if (sc->base.coherent == 0) { sc->base.coherent = OF_hasprop(node, "dma-coherent"); } if (bootverbose) device_printf(dev, "Bus is%s cache-coherent\n", sc->base.coherent ? "" : " not"); /* TODO parse FDT bus ranges */ sc->base.bus_start = 0; sc->base.bus_end = 0xFF; + error = pci_host_generic_core_attach(dev); if (error != 0) return (error); ofw_bus_setup_iinfo(node, &sc->pci_iinfo, sizeof(cell_t)); + + return (0); +} + +int +pci_host_generic_attach(device_t dev) +{ + struct generic_pcie_fdt_softc *sc; + int error; + + sc = device_get_softc(dev); + + error = pci_host_generic_setup_fdt(dev); + if (error != 0) + return (error); device_add_child(dev, "pci", -1); return (bus_generic_attach(dev)); } static int parse_pci_mem_ranges(device_t dev, struct generic_pcie_core_softc *sc) { pcell_t pci_addr_cells, parent_addr_cells; pcell_t attributes, size_cells; cell_t *base_ranges; int nbase_ranges; phandle_t node; int i, j, k; int tuple; node = ofw_bus_get_node(dev); OF_getencprop(node, "#address-cells", &pci_addr_cells, sizeof(pci_addr_cells)); OF_getencprop(node, "#size-cells", &size_cells, sizeof(size_cells)); OF_getencprop(OF_parent(node), "#address-cells", &parent_addr_cells, sizeof(parent_addr_cells)); if (parent_addr_cells > 2 || pci_addr_cells != 3 || size_cells > 2) { device_printf(dev, "Unexpected number of address or size cells in FDT\n"); return (ENXIO); } nbase_ranges = OF_getproplen(node, "ranges"); sc->nranges = nbase_ranges / sizeof(cell_t) / (parent_addr_cells + pci_addr_cells + size_cells); base_ranges = malloc(nbase_ranges, M_DEVBUF, M_WAITOK); OF_getencprop(node, "ranges", base_ranges, nbase_ranges); for (i = 0, j = 0; i < sc->nranges; i++) { attributes = (base_ranges[j++] >> SPACE_CODE_SHIFT) & \ SPACE_CODE_MASK; if (attributes == SPACE_CODE_IO_SPACE) { sc->ranges[i].flags |= FLAG_TYPE_IO; } else { sc->ranges[i].flags |= FLAG_TYPE_MEM; } sc->ranges[i].pci_base = 0; for (k = 0; k < (pci_addr_cells - 1); k++) { sc->ranges[i].pci_base <<= 32; sc->ranges[i].pci_base |= base_ranges[j++]; } sc->ranges[i].phys_base = 0; for (k = 0; k < parent_addr_cells; k++) { sc->ranges[i].phys_base <<= 32; sc->ranges[i].phys_base |= base_ranges[j++]; } sc->ranges[i].size = 0; for (k = 0; k < size_cells; k++) { sc->ranges[i].size <<= 32; sc->ranges[i].size |= base_ranges[j++]; } } for (; i < MAX_RANGES_TUPLES; i++) { /* zero-fill remaining tuples to mark empty elements in array */ sc->ranges[i].pci_base = 0; sc->ranges[i].phys_base = 0; sc->ranges[i].size = 0; } if (bootverbose) { for (tuple = 0; tuple < MAX_RANGES_TUPLES; tuple++) { device_printf(dev, "\tPCI addr: 0x%jx, CPU addr: 0x%jx, Size: 0x%jx\n", sc->ranges[tuple].pci_base, sc->ranges[tuple].phys_base, sc->ranges[tuple].size); } } free(base_ranges, M_DEVBUF); return (0); } static int generic_pcie_fdt_route_interrupt(device_t bus, device_t dev, int pin) { struct generic_pcie_fdt_softc *sc; struct ofw_pci_register reg; uint32_t pintr, mintr[4]; phandle_t iparent; int intrcells; sc = device_get_softc(bus); pintr = pin; bzero(®, sizeof(reg)); reg.phys_hi = (pci_get_bus(dev) << OFW_PCI_PHYS_HI_BUSSHIFT) | (pci_get_slot(dev) << OFW_PCI_PHYS_HI_DEVICESHIFT) | (pci_get_function(dev) << OFW_PCI_PHYS_HI_FUNCTIONSHIFT); intrcells = ofw_bus_lookup_imap(ofw_bus_get_node(dev), &sc->pci_iinfo, ®, sizeof(reg), &pintr, sizeof(pintr), mintr, sizeof(mintr), &iparent); if (intrcells) { pintr = ofw_bus_map_intr(dev, iparent, intrcells, mintr); return (pintr); } device_printf(bus, "could not route pin %d for device %d.%d\n", pin, pci_get_slot(dev), pci_get_function(dev)); return (PCI_INVALID_IRQ); } static int generic_pcie_fdt_release_resource(device_t dev, device_t child, int type, int rid, struct resource *res) { #if defined(NEW_PCIB) && defined(PCI_RES_BUS) if (type == PCI_RES_BUS) { return (pci_host_generic_core_release_resource(dev, child, type, rid, res)); } #endif /* For PCIe devices that do not have FDT nodes, use PCIB method */ if ((int)ofw_bus_get_node(child) <= 0) { return (pci_host_generic_core_release_resource(dev, child, type, rid, res)); } /* For other devices use OFW method */ return (bus_generic_release_resource(dev, child, type, rid, res)); } struct resource * pci_host_generic_alloc_resource(device_t dev, device_t child, int type, int *rid, rman_res_t start, rman_res_t end, rman_res_t count, u_int flags) { struct generic_pcie_fdt_softc *sc; struct generic_pcie_ofw_devinfo *di; struct resource_list_entry *rle; int i; #if defined(NEW_PCIB) && defined(PCI_RES_BUS) if (type == PCI_RES_BUS) { return (pci_host_generic_core_alloc_resource(dev, child, type, rid, start, end, count, flags)); } #endif /* For PCIe devices that do not have FDT nodes, use PCIB method */ if ((int)ofw_bus_get_node(child) <= 0) return (pci_host_generic_core_alloc_resource(dev, child, type, rid, start, end, count, flags)); /* For other devices use OFW method */ sc = device_get_softc(dev); if (RMAN_IS_DEFAULT_RANGE(start, end)) { if ((di = device_get_ivars(child)) == NULL) return (NULL); if (type == SYS_RES_IOPORT) type = SYS_RES_MEMORY; /* Find defaults for this rid */ rle = resource_list_find(&di->di_rl, type, *rid); if (rle == NULL) return (NULL); start = rle->start; end = rle->end; count = rle->count; } if (type == SYS_RES_MEMORY) { /* Remap through ranges property */ for (i = 0; i < MAX_RANGES_TUPLES; i++) { if (start >= sc->base.ranges[i].phys_base && end < (sc->base.ranges[i].pci_base + sc->base.ranges[i].size)) { start -= sc->base.ranges[i].phys_base; start += sc->base.ranges[i].pci_base; end -= sc->base.ranges[i].phys_base; end += sc->base.ranges[i].pci_base; break; } } if (i == MAX_RANGES_TUPLES) { device_printf(dev, "Could not map resource " "%#jx-%#jx\n", start, end); return (NULL); } } return (bus_generic_alloc_resource(dev, child, type, rid, start, end, count, flags)); } static int generic_pcie_fdt_alloc_msi(device_t pci, device_t child, int count, int maxcount, int *irqs) { #if defined(INTRNG) phandle_t msi_parent; int err; err = ofw_bus_msimap(ofw_bus_get_node(pci), pci_get_rid(child), &msi_parent, NULL); if (err != 0) return (err); return (intr_alloc_msi(pci, child, msi_parent, count, maxcount, irqs)); #else return (ENXIO); #endif } static int generic_pcie_fdt_release_msi(device_t pci, device_t child, int count, int *irqs) { #if defined(INTRNG) phandle_t msi_parent; int err; err = ofw_bus_msimap(ofw_bus_get_node(pci), pci_get_rid(child), &msi_parent, NULL); if (err != 0) return (err); return (intr_release_msi(pci, child, msi_parent, count, irqs)); #else return (ENXIO); #endif } static int generic_pcie_fdt_map_msi(device_t pci, device_t child, int irq, uint64_t *addr, uint32_t *data) { #if defined(INTRNG) phandle_t msi_parent; int err; err = ofw_bus_msimap(ofw_bus_get_node(pci), pci_get_rid(child), &msi_parent, NULL); if (err != 0) return (err); return (intr_map_msi(pci, child, msi_parent, irq, addr, data)); #else return (ENXIO); #endif } static int generic_pcie_fdt_alloc_msix(device_t pci, device_t child, int *irq) { #if defined(INTRNG) phandle_t msi_parent; int err; err = ofw_bus_msimap(ofw_bus_get_node(pci), pci_get_rid(child), &msi_parent, NULL); if (err != 0) return (err); return (intr_alloc_msix(pci, child, msi_parent, irq)); #else return (ENXIO); #endif } static int generic_pcie_fdt_release_msix(device_t pci, device_t child, int irq) { #if defined(INTRNG) phandle_t msi_parent; int err; err = ofw_bus_msimap(ofw_bus_get_node(pci), pci_get_rid(child), &msi_parent, NULL); if (err != 0) return (err); return (intr_release_msix(pci, child, msi_parent, irq)); #else return (ENXIO); #endif } int generic_pcie_get_id(device_t pci, device_t child, enum pci_id_type type, uintptr_t *id) { phandle_t node; int err; uint32_t rid; uint16_t pci_rid; if (type != PCI_ID_MSI) return (pcib_get_id(pci, child, type, id)); node = ofw_bus_get_node(pci); pci_rid = pci_get_rid(child); err = ofw_bus_msimap(node, pci_rid, NULL, &rid); if (err != 0) return (err); *id = rid; return (0); } static const struct ofw_bus_devinfo * generic_pcie_ofw_get_devinfo(device_t bus __unused, device_t child) { struct generic_pcie_ofw_devinfo *di; di = device_get_ivars(child); return (&di->di_dinfo); } /* Helper functions */ static int generic_pcie_ofw_bus_attach(device_t dev) { struct generic_pcie_ofw_devinfo *di; device_t child; phandle_t parent, node; pcell_t addr_cells, size_cells; parent = ofw_bus_get_node(dev); if (parent > 0) { get_addr_size_cells(parent, &addr_cells, &size_cells); /* Iterate through all bus subordinates */ for (node = OF_child(parent); node > 0; node = OF_peer(node)) { /* Allocate and populate devinfo. */ di = malloc(sizeof(*di), M_DEVBUF, M_WAITOK | M_ZERO); if (ofw_bus_gen_setup_devinfo(&di->di_dinfo, node) != 0) { free(di, M_DEVBUF); continue; } /* Initialize and populate resource list. */ resource_list_init(&di->di_rl); ofw_bus_reg_to_rl(dev, node, addr_cells, size_cells, &di->di_rl); ofw_bus_intr_to_rl(dev, node, &di->di_rl, NULL); /* Add newbus device for this FDT node */ child = device_add_child(dev, NULL, -1); if (child == NULL) { resource_list_free(&di->di_rl); ofw_bus_gen_destroy_devinfo(&di->di_dinfo); free(di, M_DEVBUF); continue; } device_set_ivars(child, di); } } return (0); } static device_method_t generic_pcie_fdt_methods[] = { DEVMETHOD(device_probe, generic_pcie_fdt_probe), DEVMETHOD(device_attach, pci_host_generic_attach), DEVMETHOD(bus_alloc_resource, pci_host_generic_alloc_resource), DEVMETHOD(bus_release_resource, generic_pcie_fdt_release_resource), /* pcib interface */ DEVMETHOD(pcib_route_interrupt, generic_pcie_fdt_route_interrupt), DEVMETHOD(pcib_alloc_msi, generic_pcie_fdt_alloc_msi), DEVMETHOD(pcib_release_msi, generic_pcie_fdt_release_msi), DEVMETHOD(pcib_alloc_msix, generic_pcie_fdt_alloc_msix), DEVMETHOD(pcib_release_msix, generic_pcie_fdt_release_msix), DEVMETHOD(pcib_map_msi, generic_pcie_fdt_map_msi), DEVMETHOD(pcib_get_id, generic_pcie_get_id), DEVMETHOD(pcib_request_feature, pcib_request_feature_allow), /* ofw_bus interface */ DEVMETHOD(ofw_bus_get_devinfo, generic_pcie_ofw_get_devinfo), DEVMETHOD(ofw_bus_get_compat, ofw_bus_gen_get_compat), DEVMETHOD(ofw_bus_get_model, ofw_bus_gen_get_model), DEVMETHOD(ofw_bus_get_name, ofw_bus_gen_get_name), DEVMETHOD(ofw_bus_get_node, ofw_bus_gen_get_node), DEVMETHOD(ofw_bus_get_type, ofw_bus_gen_get_type), DEVMETHOD_END }; DEFINE_CLASS_1(pcib, generic_pcie_fdt_driver, generic_pcie_fdt_methods, sizeof(struct generic_pcie_fdt_softc), generic_pcie_core_driver); static devclass_t generic_pcie_fdt_devclass; DRIVER_MODULE(pcib, simplebus, generic_pcie_fdt_driver, generic_pcie_fdt_devclass, 0, 0); DRIVER_MODULE(pcib, ofwbus, generic_pcie_fdt_driver, generic_pcie_fdt_devclass, 0, 0); Index: head/sys/dev/pci/pci_host_generic_fdt.h =================================================================== --- head/sys/dev/pci/pci_host_generic_fdt.h (revision 362953) +++ head/sys/dev/pci/pci_host_generic_fdt.h (revision 362954) @@ -1,49 +1,50 @@ /* * Copyright (c) 2015 Ruslan Bukin * Copyright (c) 2015 The FreeBSD Foundation * All rights reserved. * * This software was developed by Semihalf. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. * * * $FreeBSD$ * */ #ifndef __PCI_HOST_GENERIC_FDT_H_ #define __PCI_HOST_GENERIC_FDT_H_ struct generic_pcie_fdt_softc { struct generic_pcie_core_softc base; struct ofw_bus_iinfo pci_iinfo; }; DECLARE_CLASS(generic_pcie_fdt_driver); struct resource *pci_host_generic_alloc_resource(device_t, device_t, int, int *, rman_res_t, rman_res_t, rman_res_t, u_int); +int pci_host_generic_setup_fdt(device_t); int pci_host_generic_attach(device_t); int generic_pcie_get_id(device_t, device_t, enum pci_id_type, uintptr_t *); #endif /* __PCI_HOST_GENERIC_FDT_H_ */