Index: head/sys/dev/ic/z8530.h =================================================================== --- head/sys/dev/ic/z8530.h (revision 362178) +++ head/sys/dev/ic/z8530.h (revision 362179) @@ -1,257 +1,256 @@ /*- * SPDX-License-Identifier: BSD-2-Clause-FreeBSD * * Copyright (c) 2003 Marcel Moolenaar * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * * $FreeBSD$ */ #ifndef _DEV_IC_Z8530_H_ #define _DEV_IC_Z8530_H_ /* - * Channel B control: 0 - * Channel B data: 1 - * Channel A control: 2 - * Channel A data: 3 + * legacy: SUN compatible + * escc: Macintosh + * legacy escc + * Channel B control: 0 0 + * Channel B data: 1 1 + * Channel A control: 2 16 + * Channel A data: 3 17 */ - -/* The following apply when using a device-scoped bus handle */ -#define CHAN_A 2 -#define CHAN_B 0 #define REG_CTRL 0 #define REG_DATA 1 /* Write registers. */ #define WR_CR 0 /* Command Register. */ #define WR_IDT 1 /* Interrupt and Data Transfer Mode. */ #define WR_IV 2 /* Interrupt Vector (shared). */ #define WR_RPC 3 /* Receive Parameters and Control. */ #define WR_MPM 4 /* Miscellaneous Parameters and Modes. */ #define WR_TPC 5 /* Transmit Parameters and Control. */ #define WR_SCAF 6 /* Sync Character or (SDLC) Address Field. */ #define WR_SCF 7 /* Sync Character or (SDCL) Flag. */ #define WR_EFC 7 /* Extended Feature and FIFO Control. */ #define WR_TB 8 /* Transmit Buffer. */ #define WR_MIC 9 /* Master Interrupt Control (shared). */ #define WR_MCB1 10 /* Miscellaneous Control Bits (part 1 :-). */ #define WR_CMC 11 /* Clock Mode Control. */ #define WR_TCL 12 /* BRG Time Constant Low. */ #define WR_TCH 13 /* BRG Time Constant High. */ #define WR_MCB2 14 /* Miscellaneous Control Bits (part 2 :-). */ #define WR_IC 15 /* Interrupt Control. */ /* Read registers. */ #define RR_BES 0 /* Buffer and External Status. */ #define RR_SRC 1 /* Special Receive Condition. */ #define RR_IV 2 /* Interrupt Vector. */ #define RR_IP 3 /* Interrupt Pending (ch A only). */ #define RR_MPM 4 /* Miscellaneous Parameters and Modes. */ #define RR_TPC 5 /* Transmit Parameters and Control. */ #define RR_BCL 6 /* Byte Count Low. */ #define RR_BCH 7 /* Byte Count High. */ #define RR_RB 8 /* Receive Buffer. */ #define RR_RPC 9 /* Receive Parameters and Control. */ #define RR_MSB 10 /* Miscellaneous Status Bits. */ #define RR_MCB1 11 /* Miscellaneous Control Bits (part 1). */ #define RR_TCL 12 /* BRG Time Constant Low. */ #define RR_TCH 13 /* BRG Time Constant High. */ #define RR_EFC 14 /* Extended Feature and FIFO Control. */ #define RR_IC 15 /* Interrupt Control. */ /* Buffer and External Status (RR0). */ #define BES_BRK 0x80 /* Break (Abort). */ #define BES_TXU 0x40 /* Tx Underrun (EOM). */ #define BES_CTS 0x20 /* CTS. */ #define BES_SYNC 0x10 /* Sync. */ #define BES_DCD 0x08 /* DCD. */ #define BES_TXE 0x04 /* Tx Empty. */ #define BES_ZC 0x02 /* Zero Count. */ #define BES_RXA 0x01 /* Rx Available. */ /* Clock Mode Control (WR11). */ #define CMC_XTAL 0x80 /* -RTxC connects to quartz crystal. */ #define CMC_RC_DPLL 0x60 /* Rx Clock from DPLL. */ #define CMC_RC_BRG 0x40 /* Rx Clock from BRG. */ #define CMC_RC_TRXC 0x20 /* Rx Clock from -TRxC. */ #define CMC_RC_RTXC 0x00 /* Rx Clock from -RTxC. */ #define CMC_TC_DPLL 0x18 /* Tx Clock from DPLL */ #define CMC_TC_BRG 0x10 /* Tx Clock from BRG */ #define CMC_TC_TRXC 0x08 /* Tx Clock from -TRxC. */ #define CMC_TC_RTXC 0x00 /* Tx Clock from -RTxC. */ #define CMC_TRXC_OUT 0x04 /* -TRxC is output. */ #define CMC_TRXC_DPLL 0x03 /* -TRxC from DPLL */ #define CMC_TRXC_BRG 0x02 /* -TRxC from BRG */ #define CMC_TRXC_XMIT 0x01 /* -TRxC from Tx clock. */ #define CMC_TRXC_XTAL 0x00 /* -TRxC from XTAL. */ /* Command Register (WR0). */ #define CR_RSTTXU 0xc0 /* Reset Tx. Underrun/EOM. */ #define CR_RSTTXCRC 0x80 /* Reset Tx. CRC. */ #define CR_RSTRXCRC 0x40 /* Reset Rx. CRC. */ #define CR_RSTIUS 0x38 /* Reset Int. Under Service. */ #define CR_RSTERR 0x30 /* Error Reset. */ #define CR_RSTTXI 0x28 /* Reset Tx. Int. */ #define CR_ENARXI 0x20 /* Enable Rx. Int. */ #define CR_ABORT 0x18 /* Send Abort. */ #define CR_RSTXSI 0x10 /* Reset Ext/Status Int. */ /* Extended Feature and FIFO Control (WR7 prime). */ #define EFC_ERE 0x40 /* Extended Read Enable. */ #define EFC_FE 0x20 /* Transmit FIFO Empty. */ #define EFC_RQT 0x10 /* Request Timing. */ #define EFC_FHF 0x08 /* Receive FIFO Half Full. */ #define EFC_RTS 0x04 /* Auto RTS Deactivation. */ #define EFC_EOM 0x02 /* Auto EOM Reset. */ #define EFC_FLAG 0x01 /* Auto SDLC Flag on Tx. */ /* Interrupt Control (WR15). */ #define IC_BRK 0x80 /* Break (Abort) IE. */ #define IC_TXU 0x40 /* Tx Underrun IE. */ #define IC_CTS 0x20 /* CTS IE. */ #define IC_SYNC 0x10 /* Sync IE. */ #define IC_DCD 0x08 /* DCD IE. */ #define IC_FIFO 0x04 /* SDLC FIFO Enable. */ #define IC_ZC 0x02 /* Zero Count IE. */ #define IC_EF 0x01 /* Extended Feature Enable. */ /* Interrupt and Data Transfer Mode (WR1). */ #define IDT_WRE 0x80 /* Wait/DMA Request Enable. */ #define IDT_REQ 0x40 /* DMA Request. */ #define IDT_WRR 0x20 /* Wait/DMA Reuest on Receive. */ #define IDT_RISC 0x18 /* Rx Int. on Special Condition Only. */ #define IDT_RIA 0x10 /* Rx Int. on All Characters. */ #define IDT_RIF 0x08 /* Rx Int. on First Character. */ #define IDT_PSC 0x04 /* Parity is Special Condition. */ #define IDT_TIE 0x02 /* Tx Int. Enable. */ #define IDT_XIE 0x01 /* Ext. Int. Enable. */ /* Interrupt Pending (RR3). */ #define IP_RIA 0x20 /* Rx. Int. ch. A. */ #define IP_TIA 0x10 /* Tx. Int. ch. A. */ #define IP_SIA 0x08 /* Ext/Status Int. ch. A. */ #define IP_RIB 0x04 /* Rx. Int. ch. B. */ #define IP_TIB 0x02 /* Tx. Int. ch. B. */ #define IP_SIB 0x01 /* Ext/Status Int. ch. B. */ /* Interrupt Vector Status Low (RR2). */ #define IV_SCA 0x0e /* Special Condition ch. A. */ #define IV_RAA 0x0c /* Receive Available ch. A. */ #define IV_XSA 0x0a /* External/Status Change ch. A. */ #define IV_TEA 0x08 /* Transmitter Empty ch. A. */ #define IV_SCB 0x06 /* Special Condition ch. B. */ #define IV_RAB 0x04 /* Receive Available ch. B. */ #define IV_XSB 0x02 /* External/Status Change ch. B. */ #define IV_TEB 0x00 /* Transmitter Empty ch. B. */ /* Miscellaneous Control Bits part 1 (WR10). */ #define MCB1_CRC1 0x80 /* CRC presets to 1. */ #define MCB1_FM0 0x60 /* FM0 Encoding. */ #define MCB1_FM1 0x40 /* FM1 Encoding. */ #define MCB1_NRZI 0x20 /* NRZI Encoding. */ #define MCB1_NRZ 0x00 /* NRZ Encoding. */ #define MCB1_AOP 0x10 /* Active On Poll. */ #define MCB1_MI 0x08 /* Mark Idle. */ #define MCB1_AOU 0x04 /* Abort On Underrun. */ #define MCB1_LM 0x02 /* Loop Mode. */ #define MCB1_SIX 0x01 /* 6 or 12 bit SYNC. */ /* Miscellaneous Control Bits part 2 (WR14). */ #define MCB2_NRZI 0xe0 /* DPLL - NRZI mode. */ #define MCB2_FM 0xc0 /* DPLL - FM mode. */ #define MCB2_RTXC 0xa0 /* DPLL - Clock from -RTxC. */ #define MCB2_BRG 0x80 /* DPLL - Clock from BRG. */ #define MCB2_OFF 0x60 /* DPLL - Disable. */ #define MCB2_RMC 0x40 /* DPLL - Reset Missing Clock. */ #define MCB2_ESM 0x20 /* DPLL - Enter Search Mode. */ #define MCB2_LL 0x10 /* Local Loopback. */ #define MCB2_AE 0x08 /* Auto Echo. */ #define MCB2_REQ 0x04 /* Request Function. */ #define MCB2_PCLK 0x02 /* BRG source is PCLK. */ #define MCB2_BRGE 0x01 /* BRG enable. */ /* Master Interrupt Control (WR9). */ #define MIC_FHR 0xc0 /* Force Hardware Reset. */ #define MIC_CRA 0x80 /* Channel Reset A. */ #define MIC_CRB 0x40 /* Channel Reset B. */ #define MIC_SIE 0x20 /* Software INTACK Enable. */ #define MIC_SH 0x10 /* Status High. */ #define MIC_MIE 0x08 /* Master Interrupt Enable. */ #define MIC_DLC 0x04 /* Disable Lower Chain. */ #define MIC_NV 0x02 /* No Vector. */ #define MIC_VIS 0x01 /* Vector Includes Status. */ /* Transmit/Receive Miscellaneous Parameters and Modes (WR4). */ #define MPM_CM64 0xc0 /* X64 Clock Mode. */ #define MPM_CM32 0x80 /* X32 Clock Mode. */ #define MPM_CM16 0x40 /* X16 Clock Mode. */ #define MPM_CM1 0x00 /* X1 Clock Mode. */ #define MPM_EXT 0x30 /* External Sync Mode. */ #define MPM_SDLC 0x20 /* SDLC mode. */ #define MPM_BI 0x10 /* 16-bit Sync (bi-sync). */ #define MPM_MONO 0x00 /* 8-bit Sync (mono-sync). */ #define MPM_SB2 0x0c /* Async mode: 2 stopbits. */ #define MPM_SB15 0x08 /* Async mode: 1.5 stopbits. */ #define MPM_SB1 0x04 /* Async mode: 1 stopbit. */ #define MPM_SYNC 0x00 /* Sync Mode Enable. */ #define MPM_EVEN 0x02 /* Async mode: even parity. */ #define MPM_PE 0x01 /* Async mode: parity enable. */ /* Receive Parameters and Control (WR3). */ #define RPC_RB8 0xc0 /* 8 databits. */ #define RPC_RB6 0x80 /* 6 databits. */ #define RPC_RB7 0x40 /* 7 databits. */ #define RPC_RB5 0x00 /* 5 databits. */ #define RPC_AE 0x20 /* Auto Enable. */ #define RPC_EHM 0x10 /* Enter Hunt Mode. */ #define RPC_CRC 0x08 /* CRC Enable. */ #define RPC_ASM 0x04 /* Address Search Mode. */ #define RPC_LI 0x02 /* SYNC Character Load Inhibit */ #define RPC_RXE 0x01 /* Receiver Enable */ /* Special Receive Condition (RR1). */ #define SRC_EOF 0x80 /* End Of Frame. */ #define SRC_FE 0x40 /* Framing Error. */ #define SRC_OVR 0x20 /* Rx. Overrun. */ #define SRC_PE 0x10 /* Parity Error. */ #define SRC_RC0 0x08 /* Residue Code 0. */ #define SRC_RC1 0x04 /* Residue Code 1. */ #define SRC_RC2 0x02 /* Residue Code 2. */ #define SRC_AS 0x01 /* All Sent. */ /* Transmit Parameter and Control (WR5). */ #define TPC_DTR 0x80 /* DTR. */ #define TPC_TB8 0x60 /* 8 databits. */ #define TPC_TB6 0x40 /* 6 databits. */ #define TPC_TB7 0x20 /* 7 databits. */ #define TPC_TB5 0x00 /* 5 or fewer databits. */ #define TPC_BRK 0x10 /* Send break. */ #define TPC_TXE 0x08 /* Transmitter Enable. */ #define TPC_CRC16 0x04 /* CRC16. */ #define TPC_RTS 0x02 /* RTS. */ #define TPC_CRC 0x01 /* CRC Enable. */ #endif /* _DEV_IC_Z8530_H_ */ Index: head/sys/dev/scc/scc_bfe.h =================================================================== --- head/sys/dev/scc/scc_bfe.h (revision 362178) +++ head/sys/dev/scc/scc_bfe.h (revision 362179) @@ -1,156 +1,157 @@ /*- * SPDX-License-Identifier: BSD-2-Clause-FreeBSD * * Copyright (c) 2004-2006 Marcel Moolenaar * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * * $FreeBSD$ */ #ifndef _DEV_SCC_BFE_H_ #define _DEV_SCC_BFE_H_ #include /* * Bus access structure. This structure holds the minimum information needed * to access the SCC. The rclk field, although not important to actually * access the SCC, is important for baudrate programming, delay loops and * other timing related computations. */ struct scc_bas { bus_space_tag_t bst; bus_space_handle_t bsh; u_int range; u_int rclk; u_int regshft; }; #define scc_regofs(bas, reg) ((reg) << (bas)->regshft) #define scc_getreg(bas, reg) \ bus_space_read_1((bas)->bst, (bas)->bsh, scc_regofs(bas, reg)) #define scc_setreg(bas, reg, value) \ bus_space_write_1((bas)->bst, (bas)->bsh, scc_regofs(bas, reg), value) #define scc_barrier(bas) \ bus_space_barrier((bas)->bst, (bas)->bsh, 0, (bas)->range, \ BUS_SPACE_BARRIER_READ|BUS_SPACE_BARRIER_WRITE) /* * SCC mode (child) and channel control structures. */ #define SCC_NMODES 3 #define SCC_ISRCCNT 5 struct scc_chan; struct scc_mode { struct scc_chan *m_chan; device_t m_dev; u_int m_mode; int m_attached:1; int m_fastintr:1; int m_hasintr:1; int m_probed:1; int m_sysdev:1; driver_filter_t *ih; serdev_intr_t *ih_src[SCC_ISRCCNT]; void *ih_arg; }; struct scc_chan { struct resource ch_rres; struct resource_list ch_rlist; struct resource *ch_ires; /* Interrupt resource. */ void *ch_icookie; int ch_irid; struct scc_mode ch_mode[SCC_NMODES]; u_int ch_nr; int ch_enabled:1; int ch_sysdev:1; uint32_t ch_ipend; uint32_t ch_hwsig; }; /* * SCC class & instance (=softc) */ struct scc_class { KOBJ_CLASS_FIELDS; u_int cl_channels; /* Number of independent channels. */ u_int cl_class; /* SCC bus class ID. */ u_int cl_modes; /* Supported modes (bitset). */ int cl_range; }; extern struct scc_class scc_quicc_class; extern struct scc_class scc_sab82532_class; -extern struct scc_class scc_z8530_class; +extern struct scc_class scc_z8530_escc_class; +extern struct scc_class scc_z8530_legacy_class; struct scc_softc { KOBJ_FIELDS; struct scc_class *sc_class; struct scc_bas sc_bas; device_t sc_dev; struct mtx sc_hwmtx; /* Spinlock protecting hardware. */ struct resource *sc_rres; /* Register resource. */ int sc_rrid; int sc_rtype; /* SYS_RES_{IOPORT|MEMORY}. */ struct scc_chan *sc_chan; int sc_fastintr:1; int sc_leaving:1; int sc_polled:1; uint32_t sc_hwsig; /* Signal state. Used by HW driver. */ }; extern devclass_t scc_devclass; extern const char scc_driver_name[]; int scc_bfe_attach(device_t dev, u_int ipc); int scc_bfe_detach(device_t dev); int scc_bfe_probe(device_t dev, u_int regshft, u_int rclk, u_int rid); struct resource *scc_bus_alloc_resource(device_t, device_t, int, int *, rman_res_t, rman_res_t, rman_res_t, u_int); int scc_bus_get_resource(device_t, device_t, int, int, rman_res_t *, rman_res_t *); int scc_bus_read_ivar(device_t, device_t, int, uintptr_t *); int scc_bus_release_resource(device_t, device_t, int, int, struct resource *); int scc_bus_setup_intr(device_t, device_t, struct resource *, int, driver_filter_t *, void (*)(void *), void *, void **); int scc_bus_teardown_intr(device_t, device_t, struct resource *, void *); #endif /* _DEV_SCC_BFE_H_ */ Index: head/sys/dev/scc/scc_bfe_macio.c =================================================================== --- head/sys/dev/scc/scc_bfe_macio.c (revision 362178) +++ head/sys/dev/scc/scc_bfe_macio.c (revision 362179) @@ -1,95 +1,96 @@ /*- * SPDX-License-Identifier: BSD-2-Clause-FreeBSD * * Copyright (c) 2006 Marcel Moolenaar * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ #include __FBSDID("$FreeBSD$"); #include #include #include #include #include #include #include #include #include #include #include #define MACIO_REGSHFT 4 #define MACIO_RCLK 230400 static int scc_macio_probe(device_t dev) { struct scc_softc *sc; const char *nm; sc = device_get_softc(dev); nm = ofw_bus_get_name(dev); + /* Attach to modern escc (channel shift 4 bits) */ if (!strcmp(nm, "escc")) { device_set_desc(dev, "Zilog Z8530 dual channel SCC"); - sc->sc_class = &scc_z8530_class; + sc->sc_class = &scc_z8530_escc_class; return (scc_bfe_probe(dev, MACIO_REGSHFT, MACIO_RCLK, 0)); } return (ENXIO); } static int scc_macio_attach(device_t dev) { return (scc_bfe_attach(dev, 3)); } static device_method_t scc_macio_methods[] = { /* Device interface */ DEVMETHOD(device_probe, scc_macio_probe), DEVMETHOD(device_attach, scc_macio_attach), DEVMETHOD(device_detach, scc_bfe_detach), DEVMETHOD(bus_alloc_resource, scc_bus_alloc_resource), DEVMETHOD(bus_release_resource, scc_bus_release_resource), DEVMETHOD(bus_get_resource, scc_bus_get_resource), DEVMETHOD(bus_read_ivar, scc_bus_read_ivar), DEVMETHOD(bus_setup_intr, scc_bus_setup_intr), DEVMETHOD(bus_teardown_intr, scc_bus_teardown_intr), DEVMETHOD_END }; static driver_t scc_macio_driver = { scc_driver_name, scc_macio_methods, sizeof(struct scc_softc), }; DRIVER_MODULE(scc, macio, scc_macio_driver, scc_devclass, NULL, NULL); Index: head/sys/dev/scc/scc_dev_z8530.c =================================================================== --- head/sys/dev/scc/scc_dev_z8530.c (revision 362178) +++ head/sys/dev/scc/scc_dev_z8530.c (revision 362179) @@ -1,185 +1,207 @@ /*- * SPDX-License-Identifier: BSD-2-Clause-FreeBSD * * Copyright (c) 2004-2006 Marcel Moolenaar * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ #include __FBSDID("$FreeBSD$"); #include #include #include #include #include #include #include #include #include #include #include #include #include "scc_if.h" static int z8530_bfe_attach(struct scc_softc *, int); static int z8530_bfe_iclear(struct scc_softc *, struct scc_chan *); static int z8530_bfe_ipend(struct scc_softc *); static int z8530_bfe_probe(struct scc_softc *); +/* Channel B is always at 0 offset. */ +#define CHAN_A (-(sc->sc_class->cl_range)) +#define CHAN_B 0 + static kobj_method_t z8530_methods[] = { KOBJMETHOD(scc_attach, z8530_bfe_attach), KOBJMETHOD(scc_iclear, z8530_bfe_iclear), KOBJMETHOD(scc_ipend, z8530_bfe_ipend), KOBJMETHOD(scc_probe, z8530_bfe_probe), KOBJMETHOD_END }; -struct scc_class scc_z8530_class = { - "z8530 class", +/* + * escc (macio) spacing. + */ +struct scc_class scc_z8530_escc_class = { + "z8530 escc class", z8530_methods, sizeof(struct scc_softc), .cl_channels = 2, .cl_class = SCC_CLASS_Z8530, .cl_modes = SCC_MODE_ASYNC | SCC_MODE_BISYNC | SCC_MODE_HDLC, - .cl_range = CHAN_B - CHAN_A, + /* Negative .cl_range signifies this is channel spacing. */ + .cl_range = (CHAN_B - 16), +}; + +/* + * SUN compatible channel spacing. + */ +struct scc_class scc_z8530_legacy_class = { + "z8530 legacy class", + z8530_methods, + sizeof(struct scc_softc), + .cl_channels = 2, + .cl_class = SCC_CLASS_Z8530, + .cl_modes = SCC_MODE_ASYNC | SCC_MODE_BISYNC | SCC_MODE_HDLC, + /* Negative .cl_range signifies this is channel spacing. */ + .cl_range = (CHAN_B - 2), }; /* Multiplexed I/O. */ static __inline uint8_t scc_getmreg(struct scc_bas *bas, int ch, int reg) { scc_setreg(bas, ch + REG_CTRL, reg); scc_barrier(bas); return (scc_getreg(bas, ch + REG_CTRL)); } static int z8530_bfe_attach(struct scc_softc *sc __unused, int reset __unused) { return (0); } static int z8530_bfe_iclear(struct scc_softc *sc, struct scc_chan *ch) { struct scc_bas *bas; int c; bas = &sc->sc_bas; c = (ch->ch_nr == 1) ? CHAN_A : CHAN_B; mtx_lock_spin(&sc->sc_hwmtx); if (ch->ch_ipend & SER_INT_TXIDLE) { scc_setreg(bas, c + REG_CTRL, CR_RSTTXI); scc_barrier(bas); } if (ch->ch_ipend & SER_INT_RXREADY) { scc_getreg(bas, c + REG_DATA); scc_barrier(bas); } if (ch->ch_ipend & (SER_INT_OVERRUN|SER_INT_BREAK)) scc_setreg(bas, c + REG_CTRL, CR_RSTERR); mtx_unlock_spin(&sc->sc_hwmtx); return (0); } #define SIGCHG(c, i, s, d) \ if (c) { \ i |= (i & s) ? s : s | d; \ } else { \ i = (i & s) ? (i & ~s) | d : i; \ } static int z8530_bfe_ipend(struct scc_softc *sc) { struct scc_bas *bas; struct scc_chan *ch[2]; uint32_t sig; uint8_t bes, ip, src; bas = &sc->sc_bas; ch[0] = &sc->sc_chan[0]; ch[1] = &sc->sc_chan[1]; ch[0]->ch_ipend = 0; ch[1]->ch_ipend = 0; mtx_lock_spin(&sc->sc_hwmtx); ip = scc_getmreg(bas, CHAN_A, RR_IP); if (ip & IP_RIA) ch[0]->ch_ipend |= SER_INT_RXREADY; if (ip & IP_RIB) ch[1]->ch_ipend |= SER_INT_RXREADY; if (ip & IP_TIA) ch[0]->ch_ipend |= SER_INT_TXIDLE; if (ip & IP_TIB) ch[1]->ch_ipend |= SER_INT_TXIDLE; if (ip & IP_SIA) { bes = scc_getmreg(bas, CHAN_A, CR_RSTXSI); if (bes & BES_BRK) ch[0]->ch_ipend |= SER_INT_BREAK; sig = ch[0]->ch_hwsig; SIGCHG(bes & BES_CTS, sig, SER_CTS, SER_DCTS); SIGCHG(bes & BES_DCD, sig, SER_DCD, SER_DDCD); SIGCHG(bes & BES_SYNC, sig, SER_DSR, SER_DDSR); if (sig & SER_MASK_DELTA) { ch[0]->ch_hwsig = sig; ch[0]->ch_ipend |= SER_INT_SIGCHG; } src = scc_getmreg(bas, CHAN_A, RR_SRC); if (src & SRC_OVR) ch[0]->ch_ipend |= SER_INT_OVERRUN; } if (ip & IP_SIB) { bes = scc_getmreg(bas, CHAN_B, CR_RSTXSI); if (bes & BES_BRK) ch[1]->ch_ipend |= SER_INT_BREAK; sig = ch[1]->ch_hwsig; SIGCHG(bes & BES_CTS, sig, SER_CTS, SER_DCTS); SIGCHG(bes & BES_DCD, sig, SER_DCD, SER_DDCD); SIGCHG(bes & BES_SYNC, sig, SER_DSR, SER_DDSR); if (sig & SER_MASK_DELTA) { ch[1]->ch_hwsig = sig; ch[1]->ch_ipend |= SER_INT_SIGCHG; } src = scc_getmreg(bas, CHAN_B, RR_SRC); if (src & SRC_OVR) ch[1]->ch_ipend |= SER_INT_OVERRUN; } mtx_unlock_spin(&sc->sc_hwmtx); return (ch[0]->ch_ipend | ch[1]->ch_ipend); } static int z8530_bfe_probe(struct scc_softc *sc __unused) { return (0); }