Index: head/sys/arm64/coresight/coresight_tmc.c =================================================================== --- head/sys/arm64/coresight/coresight_tmc.c (revision 362098) +++ head/sys/arm64/coresight/coresight_tmc.c (revision 362099) @@ -1,398 +1,351 @@ /*- * Copyright (c) 2018 Ruslan Bukin * All rights reserved. * * This software was developed by SRI International and the University of * Cambridge Computer Laboratory under DARPA/AFRL contract FA8750-10-C-0237 * ("CTSRD"), as part of the DARPA CRASH research programme. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. */ #include __FBSDID("$FreeBSD$"); #include #include #include #include #include #include #include #include #include -#include -#include - #include "coresight_if.h" #define TMC_DEBUG #undef TMC_DEBUG #ifdef TMC_DEBUG #define dprintf(fmt, ...) printf(fmt, ##__VA_ARGS__) #else #define dprintf(fmt, ...) #endif -static struct ofw_compat_data compat_data[] = { - { "arm,coresight-tmc", 1 }, - { NULL, 0 } -}; - -struct tmc_softc { - struct resource *res; - device_t dev; - uint64_t cycle; - struct coresight_platform_data *pdata; - uint32_t dev_type; -#define CORESIGHT_UNKNOWN 0 -#define CORESIGHT_ETR 1 -#define CORESIGHT_ETF 2 - uint32_t nev; - struct coresight_event *event; - boolean_t etf_configured; -}; - static struct resource_spec tmc_spec[] = { { SYS_RES_MEMORY, 0, RF_ACTIVE }, { -1, 0 } }; static int tmc_start(device_t dev) { struct tmc_softc *sc; uint32_t reg; sc = device_get_softc(dev); if (bus_read_4(sc->res, TMC_CTL) & CTL_TRACECAPTEN) return (-1); /* Enable TMC */ bus_write_4(sc->res, TMC_CTL, CTL_TRACECAPTEN); if ((bus_read_4(sc->res, TMC_CTL) & CTL_TRACECAPTEN) == 0) panic("Not enabled\n"); do { reg = bus_read_4(sc->res, TMC_STS); } while ((reg & STS_TMCREADY) == 1); if ((bus_read_4(sc->res, TMC_CTL) & CTL_TRACECAPTEN) == 0) panic("Not enabled\n"); return (0); } static int tmc_stop(device_t dev) { struct tmc_softc *sc; uint32_t reg; sc = device_get_softc(dev); reg = bus_read_4(sc->res, TMC_CTL); reg &= ~CTL_TRACECAPTEN; bus_write_4(sc->res, TMC_CTL, reg); do { reg = bus_read_4(sc->res, TMC_STS); } while ((reg & STS_TMCREADY) == 1); return (0); } static int tmc_configure_etf(device_t dev) { struct tmc_softc *sc; uint32_t reg; sc = device_get_softc(dev); do { reg = bus_read_4(sc->res, TMC_STS); } while ((reg & STS_TMCREADY) == 0); bus_write_4(sc->res, TMC_MODE, MODE_HW_FIFO); bus_write_4(sc->res, TMC_FFCR, FFCR_EN_FMT | FFCR_EN_TI); tmc_start(dev); dprintf("%s: STS %x, CTL %x, RSZ %x, RRP %x, RWP %x, " "LBUFLEVEL %x, CBUFLEVEL %x\n", __func__, bus_read_4(sc->res, TMC_STS), bus_read_4(sc->res, TMC_CTL), bus_read_4(sc->res, TMC_RSZ), bus_read_4(sc->res, TMC_RRP), bus_read_4(sc->res, TMC_RWP), bus_read_4(sc->res, TMC_CBUFLEVEL), bus_read_4(sc->res, TMC_LBUFLEVEL)); return (0); } static int tmc_configure_etr(device_t dev, struct endpoint *endp, struct coresight_event *event) { struct tmc_softc *sc; uint32_t reg; sc = device_get_softc(dev); tmc_stop(dev); do { reg = bus_read_4(sc->res, TMC_STS); } while ((reg & STS_TMCREADY) == 0); /* Configure TMC */ bus_write_4(sc->res, TMC_MODE, MODE_CIRCULAR_BUFFER); reg = AXICTL_PROT_CTRL_BIT1; reg |= AXICTL_WRBURSTLEN_16; /* * SG operation is broken on DragonBoard 410c * reg |= AXICTL_SG_MODE; */ reg |= AXICTL_AXCACHE_OS; bus_write_4(sc->res, TMC_AXICTL, reg); reg = FFCR_EN_FMT | FFCR_EN_TI | FFCR_FON_FLIN | FFCR_FON_TRIG_EVT | FFCR_TRIGON_TRIGIN; bus_write_4(sc->res, TMC_FFCR, reg); bus_write_4(sc->res, TMC_TRG, 8); bus_write_4(sc->res, TMC_DBALO, event->etr.low); bus_write_4(sc->res, TMC_DBAHI, event->etr.high); bus_write_4(sc->res, TMC_RSZ, event->etr.bufsize / 4); bus_write_4(sc->res, TMC_RRP, event->etr.low); bus_write_4(sc->res, TMC_RWP, event->etr.low); reg = bus_read_4(sc->res, TMC_STS); reg &= ~STS_FULL; bus_write_4(sc->res, TMC_STS, reg); tmc_start(dev); return (0); } static int tmc_init(device_t dev) { struct tmc_softc *sc; uint32_t reg; sc = device_get_softc(dev); /* Unlock Coresight */ bus_write_4(sc->res, CORESIGHT_LAR, CORESIGHT_UNLOCK); /* Unlock TMC */ bus_write_4(sc->res, TMC_LAR, CORESIGHT_UNLOCK); reg = bus_read_4(sc->res, TMC_DEVID); reg &= DEVID_CONFIGTYPE_M; switch (reg) { case DEVID_CONFIGTYPE_ETR: sc->dev_type = CORESIGHT_ETR; dprintf(dev, "ETR configuration found\n"); break; case DEVID_CONFIGTYPE_ETF: sc->dev_type = CORESIGHT_ETF; dprintf(dev, "ETF configuration found\n"); if (sc->etf_configured == false) { tmc_configure_etf(dev); sc->etf_configured = true; } break; default: sc->dev_type = CORESIGHT_UNKNOWN; break; } return (0); } static int tmc_enable(device_t dev, struct endpoint *endp, struct coresight_event *event) { struct tmc_softc *sc; uint32_t nev; sc = device_get_softc(dev); if (sc->dev_type == CORESIGHT_ETF) return (0); KASSERT(sc->dev_type == CORESIGHT_ETR, ("Wrong dev_type")); /* * Multiple CPUs can call this same time. * We allow only one running configuration. */ if (event->etr.flags & ETR_FLAG_ALLOCATE) { event->etr.flags &= ~ETR_FLAG_ALLOCATE; nev = atomic_fetchadd_int(&sc->nev, 1); if (nev == 0) { sc->event = event; tmc_stop(dev); tmc_configure_etr(dev, endp, event); tmc_start(dev); } } return (0); } static void tmc_disable(device_t dev, struct endpoint *endp, struct coresight_event *event) { struct tmc_softc *sc; uint32_t nev; sc = device_get_softc(dev); /* ETF configuration is static */ if (sc->dev_type == CORESIGHT_ETF) return; KASSERT(sc->dev_type == CORESIGHT_ETR, ("Wrong dev_type")); if (event->etr.flags & ETR_FLAG_RELEASE) { event->etr.flags &= ~ETR_FLAG_RELEASE; nev = atomic_fetchadd_int(&sc->nev, -1); if (nev == 1) { tmc_stop(dev); sc->event = NULL; } } } static int tmc_read(device_t dev, struct endpoint *endp, struct coresight_event *event) { struct tmc_softc *sc; uint32_t cur_ptr; sc = device_get_softc(dev); if (sc->dev_type == CORESIGHT_ETF) return (0); /* * Ensure the event we are reading information for * is currently configured one. */ if (sc->event != event) return (0); if (bus_read_4(sc->res, TMC_STS) & STS_FULL) { event->etr.offset = 0; event->etr.cycle++; tmc_stop(dev); tmc_start(dev); } else { cur_ptr = bus_read_4(sc->res, TMC_RWP); event->etr.offset = (cur_ptr - event->etr.low); } return (0); } static int -tmc_probe(device_t dev) -{ - - if (!ofw_bus_status_okay(dev)) - return (ENXIO); - - if (ofw_bus_search_compatible(dev, compat_data)->ocd_data == 0) - return (ENXIO); - - device_set_desc(dev, "Coresight Trace Memory Controller (TMC)"); - - return (BUS_PROBE_DEFAULT); -} - -static int tmc_attach(device_t dev) { struct coresight_desc desc; struct tmc_softc *sc; sc = device_get_softc(dev); sc->dev = dev; if (bus_alloc_resources(dev, tmc_spec, &sc->res) != 0) { device_printf(dev, "cannot allocate resources for device\n"); return (ENXIO); } sc->pdata = coresight_get_platform_data(dev); desc.pdata = sc->pdata; desc.dev = dev; desc.dev_type = CORESIGHT_TMC; coresight_register(&desc); return (0); } static device_method_t tmc_methods[] = { /* Device interface */ - DEVMETHOD(device_probe, tmc_probe), DEVMETHOD(device_attach, tmc_attach), /* Coresight interface */ DEVMETHOD(coresight_init, tmc_init), DEVMETHOD(coresight_enable, tmc_enable), DEVMETHOD(coresight_disable, tmc_disable), DEVMETHOD(coresight_read, tmc_read), DEVMETHOD_END }; -static driver_t tmc_driver = { - "tmc", - tmc_methods, - sizeof(struct tmc_softc), -}; - -static devclass_t tmc_devclass; - -DRIVER_MODULE(tmc, simplebus, tmc_driver, tmc_devclass, 0, 0); -MODULE_VERSION(tmc, 1); +DEFINE_CLASS_0(tmc, tmc_driver, tmc_methods, sizeof(struct tmc_softc)); Index: head/sys/arm64/coresight/coresight_tmc.h =================================================================== --- head/sys/arm64/coresight/coresight_tmc.h (revision 362098) +++ head/sys/arm64/coresight/coresight_tmc.h (revision 362099) @@ -1,119 +1,135 @@ /*- * Copyright (c) 2018 Ruslan Bukin * All rights reserved. * * This software was developed by SRI International and the University of * Cambridge Computer Laboratory under DARPA/AFRL contract FA8750-10-C-0237 * ("CTSRD"), as part of the DARPA CRASH research programme. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. * * $FreeBSD$ */ #ifndef _ARM64_CORESIGHT_CORESIGHT_TMC_H_ #define _ARM64_CORESIGHT_CORESIGHT_TMC_H_ #define TMC_RSZ 0x004 /* RAM Size Register */ #define TMC_STS 0x00C /* Status Register */ #define STS_MEMERR (1 << 5) #define STS_EMPTY (1 << 4) #define STS_FTEMPTY (1 << 3) #define STS_TMCREADY (1 << 2) #define STS_TRIGGERED (1 << 1) #define STS_FULL (1 << 0) #define TMC_RRD 0x010 /* RAM Read Data Register */ #define TMC_RRP 0x014 /* RAM Read Pointer Register */ #define TMC_RWP 0x018 /* RAM Write Pointer Register */ #define TMC_TRG 0x01C /* Trigger Counter Register */ #define TMC_CTL 0x020 /* Control Register */ #define CTL_TRACECAPTEN (1 << 0) /* Controls trace capture. */ #define TMC_RWD 0x024 /* RAM Write Data Register */ #define TMC_MODE 0x028 /* Mode Register */ #define MODE_HW_FIFO 2 #define MODE_SW_FIFO 1 #define MODE_CIRCULAR_BUFFER 0 #define TMC_LBUFLEVEL 0x02C /* Latched Buffer Fill Level */ #define TMC_CBUFLEVEL 0x030 /* Current Buffer Fill Level */ #define TMC_BUFWM 0x034 /* Buffer Level Water Mark */ #define TMC_RRPHI 0x038 /* RAM Read Pointer High Register */ #define TMC_RWPHI 0x03C /* RAM Write Pointer High Register */ #define TMC_AXICTL 0x110 /* AXI Control Register */ #define AXICTL_WRBURSTLEN_S 8 #define AXICTL_WRBURSTLEN_M (0xf << AXICTL_WRBURSTLEN_S) #define AXICTL_WRBURSTLEN_16 (0xf << AXICTL_WRBURSTLEN_S) #define AXICTL_SG_MODE (1 << 7) /* Scatter Gather Mode */ #define AXICTL_CACHE_CTRL_BIT3 (1 << 5) #define AXICTL_CACHE_CTRL_BIT2 (1 << 4) #define AXICTL_CACHE_CTRL_BIT1 (1 << 3) #define AXICTL_CACHE_CTRL_BIT0 (1 << 2) #define AXICTL_AXCACHE_OS (0xf << 2) #define AXICTL_PROT_CTRL_BIT1 (1 << 1) #define AXICTL_PROT_CTRL_BIT0 (1 << 0) #define TMC_DBALO 0x118 /* Data Buffer Address Low Register */ #define TMC_DBAHI 0x11C /* Data Buffer Address High Register */ #define TMC_FFSR 0x300 /* Formatter and Flush Status Register */ #define TMC_FFCR 0x304 /* Formatter and Flush Control Register */ #define FFCR_EN_FMT (1 << 0) #define FFCR_EN_TI (1 << 1) #define FFCR_FON_FLIN (1 << 4) #define FFCR_FON_TRIG_EVT (1 << 5) #define FFCR_FLUSH_MAN (1 << 6) #define FFCR_TRIGON_TRIGIN (1 << 8) #define TMC_PSCR 0x308 /* Periodic Synchronization Counter Register */ #define TMC_ITATBMDATA0 0xED0 /* Integration Test ATB Master Data Register 0 */ #define TMC_ITATBMCTR2 0xED4 /* Integration Test ATB Master Interface Control 2 Register */ #define TMC_ITATBMCTR1 0xED8 /* Integration Test ATB Master Control Register 1 */ #define TMC_ITATBMCTR0 0xEDC /* Integration Test ATB Master Interface Control 0 Register */ #define TMC_ITMISCOP0 0xEE0 /* Integration Test Miscellaneous Output Register 0 */ #define TMC_ITTRFLIN 0xEE8 /* Integration Test Trigger In and Flush In Register */ #define TMC_ITATBDATA0 0xEEC /* Integration Test ATB Data Register 0 */ #define TMC_ITATBCTR2 0xEF0 /* Integration Test ATB Control 2 Register */ #define TMC_ITATBCTR1 0xEF4 /* Integration Test ATB Control 1 Register */ #define TMC_ITATBCTR0 0xEF8 /* Integration Test ATB Control 0 Register */ #define TMC_ITCTRL 0xF00 /* Integration Mode Control Register */ #define TMC_CLAIMSET 0xFA0 /* Claim Tag Set Register */ #define TMC_CLAIMCLR 0xFA4 /* Claim Tag Clear Register */ #define TMC_LAR 0xFB0 /* Lock Access Register */ #define TMC_LSR 0xFB4 /* Lock Status Register */ #define TMC_AUTHSTATUS 0xFB8 /* Authentication Status Register */ #define TMC_DEVID 0xFC8 /* Device Configuration Register */ #define DEVID_CONFIGTYPE_S 6 #define DEVID_CONFIGTYPE_M (0x3 << DEVID_CONFIGTYPE_S) #define DEVID_CONFIGTYPE_ETB (0 << DEVID_CONFIGTYPE_S) #define DEVID_CONFIGTYPE_ETR (1 << DEVID_CONFIGTYPE_S) #define DEVID_CONFIGTYPE_ETF (2 << DEVID_CONFIGTYPE_S) #define TMC_DEVTYPE 0xFCC /* Device Type Identifier Register */ #define TMC_PERIPHID4 0xFD0 /* Peripheral ID4 Register */ #define TMC_PERIPHID5 0xFD4 /* Peripheral ID5 Register */ #define TMC_PERIPHID6 0xFD8 /* Peripheral ID6 Register */ #define TMC_PERIPHID7 0xFDC /* Peripheral ID7 Register */ #define TMC_PERIPHID0 0xFE0 /* Peripheral ID0 Register */ #define TMC_PERIPHID1 0xFE4 /* Peripheral ID1 Register */ #define TMC_PERIPHID2 0xFE8 /* Peripheral ID2 Register */ #define TMC_PERIPHID3 0xFEC /* Peripheral ID3 Register */ #define TMC_COMPID0 0xFF0 /* Component ID0 Register */ #define TMC_COMPID1 0xFF4 /* Component ID1 Register */ #define TMC_COMPID2 0xFF8 /* Component ID2 Register */ #define TMC_COMPID3 0xFFC /* Component ID3 Register */ +DECLARE_CLASS(tmc_driver); + +struct tmc_softc { + struct resource *res; + device_t dev; + uint64_t cycle; + struct coresight_platform_data *pdata; + uint32_t dev_type; +#define CORESIGHT_UNKNOWN 0 +#define CORESIGHT_ETR 1 +#define CORESIGHT_ETF 2 + uint32_t nev; + struct coresight_event *event; + boolean_t etf_configured; +}; + #endif /* !_ARM64_CORESIGHT_CORESIGHT_TMC_H_ */ Index: head/sys/arm64/coresight/coresight_tmc_acpi.c =================================================================== --- head/sys/arm64/coresight/coresight_tmc_acpi.c (nonexistent) +++ head/sys/arm64/coresight/coresight_tmc_acpi.c (revision 362099) @@ -0,0 +1,79 @@ +/*- + * SPDX-License-Identifier: BSD-2-Clause + * + * Copyright (c) 2020 Ruslan Bukin + * + * This software was developed by SRI International and the University of + * Cambridge Computer Laboratory (Department of Computer Science and + * Technology) under DARPA contract HR0011-18-C-0016 ("ECATS"), as part of the + * DARPA SSITH research programme. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + +#include "opt_acpi.h" + +#include +__FBSDID("$FreeBSD$"); + +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include + +#include + +static int +tmc_acpi_probe(device_t dev) +{ + static char *tmc_ids[] = { "ARMHC97C", NULL }; + int error; + + error = ACPI_ID_PROBE(device_get_parent(dev), dev, tmc_ids, NULL); + if (error <= 0) + device_set_desc(dev, "ARM Coresight TMC"); + + return (error); +} + +static device_method_t tmc_acpi_methods[] = { + /* Device interface */ + DEVMETHOD(device_probe, tmc_acpi_probe), + + /* End */ + DEVMETHOD_END +}; + +DEFINE_CLASS_1(tmc, tmc_acpi_driver, tmc_acpi_methods, + sizeof(struct tmc_softc), tmc_driver); + +static devclass_t tmc_acpi_devclass; + +EARLY_DRIVER_MODULE(tmc, acpi, tmc_acpi_driver, tmc_acpi_devclass, + 0, 0, BUS_PASS_INTERRUPT + BUS_PASS_ORDER_MIDDLE); Property changes on: head/sys/arm64/coresight/coresight_tmc_acpi.c ___________________________________________________________________ Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:keywords ## -0,0 +1 ## +FreeBSD=%H \ No newline at end of property Added: svn:mime-type ## -0,0 +1 ## +text/plain \ No newline at end of property Index: head/sys/arm64/coresight/coresight_tmc_fdt.c =================================================================== --- head/sys/arm64/coresight/coresight_tmc_fdt.c (nonexistent) +++ head/sys/arm64/coresight/coresight_tmc_fdt.c (revision 362099) @@ -0,0 +1,82 @@ +/*- + * Copyright (c) 2018-2020 Ruslan Bukin + * All rights reserved. + * + * This software was developed by BAE Systems, the University of Cambridge + * Computer Laboratory, and Memorial University under DARPA/AFRL contract + * FA8650-15-C-7558 ("CADETS"), as part of the DARPA Transparent Computing + * (TC) research program. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + +#include +__FBSDID("$FreeBSD$"); + +#include +#include +#include +#include +#include +#include +#include + +#include +#include + +#include +#include + +#include "coresight_if.h" + +static struct ofw_compat_data compat_data[] = { + { "arm,coresight-tmc", 1 }, + { NULL, 0 } +}; + +static int +tmc_fdt_probe(device_t dev) +{ + if (!ofw_bus_status_okay(dev)) + return (ENXIO); + + if (ofw_bus_search_compatible(dev, compat_data)->ocd_data == 0) + return (ENXIO); + + device_set_desc(dev, "ARM Coresight TMC"); + + return (BUS_PROBE_DEFAULT); +} + +static device_method_t tmc_fdt_methods[] = { + /* Device interface */ + DEVMETHOD(device_probe, tmc_fdt_probe), + DEVMETHOD_END +}; + +DEFINE_CLASS_1(tmc, tmc_fdt_driver, tmc_fdt_methods, + sizeof(struct tmc_softc), tmc_driver); + +static devclass_t tmc_fdt_devclass; + +EARLY_DRIVER_MODULE(tmc, simplebus, tmc_fdt_driver, tmc_fdt_devclass, + 0, 0, BUS_PASS_INTERRUPT + BUS_PASS_ORDER_MIDDLE); Property changes on: head/sys/arm64/coresight/coresight_tmc_fdt.c ___________________________________________________________________ Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:keywords ## -0,0 +1 ## +FreeBSD=%H \ No newline at end of property Added: svn:mime-type ## -0,0 +1 ## +text/plain \ No newline at end of property Index: head/sys/conf/files.arm64 =================================================================== --- head/sys/conf/files.arm64 (revision 362098) +++ head/sys/conf/files.arm64 (revision 362099) @@ -1,390 +1,392 @@ # $FreeBSD$ cloudabi32_vdso.o optional compat_cloudabi32 \ dependency "$S/contrib/cloudabi/cloudabi_vdso_armv6_on_64bit.S" \ compile-with "${CC} -x assembler-with-cpp -m32 -shared -nostdinc -nostdlib -Wl,-T$S/compat/cloudabi/cloudabi_vdso.lds $S/contrib/cloudabi/cloudabi_vdso_armv6_on_64bit.S -o ${.TARGET}" \ no-obj no-implicit-rule \ clean "cloudabi32_vdso.o" # cloudabi32_vdso_blob.o optional compat_cloudabi32 \ dependency "cloudabi32_vdso.o" \ compile-with "${OBJCOPY} --input-target binary --output-target elf64-littleaarch64 --binary-architecture aarch64 cloudabi32_vdso.o ${.TARGET}" \ no-implicit-rule \ clean "cloudabi32_vdso_blob.o" # cloudabi64_vdso.o optional compat_cloudabi64 \ dependency "$S/contrib/cloudabi/cloudabi_vdso_aarch64.S" \ compile-with "${CC} -x assembler-with-cpp -shared -nostdinc -nostdlib -Wl,-T$S/compat/cloudabi/cloudabi_vdso.lds $S/contrib/cloudabi/cloudabi_vdso_aarch64.S -o ${.TARGET}" \ no-obj no-implicit-rule \ clean "cloudabi64_vdso.o" # cloudabi64_vdso_blob.o optional compat_cloudabi64 \ dependency "cloudabi64_vdso.o" \ compile-with "${OBJCOPY} --input-target binary --output-target elf64-littleaarch64 --binary-architecture aarch64 cloudabi64_vdso.o ${.TARGET}" \ no-implicit-rule \ clean "cloudabi64_vdso_blob.o" # # Allwinner common files arm/allwinner/a10_timer.c optional a10_timer fdt arm/allwinner/a10_codec.c optional sound a10_codec arm/allwinner/a31_dmac.c optional a31_dmac arm/allwinner/sunxi_dma_if.m optional a31_dmac arm/allwinner/aw_cir.c optional evdev aw_cir fdt arm/allwinner/aw_dwc3.c optional aw_dwc3 fdt arm/allwinner/aw_gpio.c optional gpio aw_gpio fdt arm/allwinner/aw_mmc.c optional mmc aw_mmc fdt | mmccam aw_mmc fdt arm/allwinner/aw_nmi.c optional aw_nmi fdt \ compile-with "${NORMAL_C} -I$S/gnu/dts/include" arm/allwinner/aw_pwm.c optional aw_pwm fdt arm/allwinner/aw_rsb.c optional aw_rsb fdt arm/allwinner/aw_rtc.c optional aw_rtc fdt arm/allwinner/aw_sid.c optional aw_sid nvmem fdt arm/allwinner/aw_spi.c optional aw_spi fdt arm/allwinner/aw_syscon.c optional aw_syscon ext_resources syscon fdt arm/allwinner/aw_thermal.c optional aw_thermal nvmem fdt arm/allwinner/aw_usbphy.c optional ehci aw_usbphy fdt arm/allwinner/aw_usb3phy.c optional xhci aw_usbphy fdt arm/allwinner/aw_wdog.c optional aw_wdog fdt arm/allwinner/axp81x.c optional axp81x fdt arm/allwinner/if_awg.c optional awg ext_resources syscon aw_sid nvmem fdt # Allwinner clock driver arm/allwinner/clkng/aw_ccung.c optional aw_ccu fdt arm/allwinner/clkng/aw_clk_frac.c optional aw_ccu fdt arm/allwinner/clkng/aw_clk_m.c optional aw_ccu fdt arm/allwinner/clkng/aw_clk_mipi.c optional aw_ccu fdt arm/allwinner/clkng/aw_clk_nkmp.c optional aw_ccu fdt arm/allwinner/clkng/aw_clk_nm.c optional aw_ccu fdt arm/allwinner/clkng/aw_clk_nmm.c optional aw_ccu fdt arm/allwinner/clkng/aw_clk_np.c optional aw_ccu fdt arm/allwinner/clkng/aw_clk_prediv_mux.c optional aw_ccu fdt arm/allwinner/clkng/ccu_a64.c optional soc_allwinner_a64 aw_ccu fdt arm/allwinner/clkng/ccu_h3.c optional soc_allwinner_h5 aw_ccu fdt arm/allwinner/clkng/ccu_h6.c optional soc_allwinner_h6 aw_ccu fdt arm/allwinner/clkng/ccu_h6_r.c optional soc_allwinner_h6 aw_ccu fdt arm/allwinner/clkng/ccu_sun8i_r.c optional aw_ccu fdt arm/allwinner/clkng/ccu_de2.c optional aw_ccu fdt # Allwinner padconf files arm/allwinner/a64/a64_padconf.c optional soc_allwinner_a64 fdt arm/allwinner/a64/a64_r_padconf.c optional soc_allwinner_a64 fdt arm/allwinner/h3/h3_padconf.c optional soc_allwinner_h5 fdt arm/allwinner/h3/h3_r_padconf.c optional soc_allwinner_h5 fdt arm/allwinner/h6/h6_padconf.c optional soc_allwinner_h6 fdt arm/allwinner/h6/h6_r_padconf.c optional soc_allwinner_h6 fdt arm/annapurna/alpine/alpine_ccu.c optional al_ccu fdt arm/annapurna/alpine/alpine_nb_service.c optional al_nb_service fdt arm/annapurna/alpine/alpine_pci.c optional al_pci fdt arm/annapurna/alpine/alpine_pci_msix.c optional al_pci fdt arm/annapurna/alpine/alpine_serdes.c optional al_serdes fdt \ no-depend \ compile-with "${CC} -c -o ${.TARGET} ${CFLAGS} -I$S/contrib/alpine-hal -I$S/contrib/alpine-hal/eth ${PROF} ${.IMPSRC}" arm/arm/generic_timer.c standard arm/arm/gic.c standard arm/arm/gic_acpi.c optional acpi arm/arm/gic_fdt.c optional fdt arm/arm/pmu.c standard arm/broadcom/bcm2835/bcm2835_audio.c optional sound vchiq fdt \ compile-with "${NORMAL_C} -DUSE_VCHIQ_ARM -D__VCCOREVER__=0x04000000 -I$S/contrib/vchiq" arm/broadcom/bcm2835/bcm2835_bsc.c optional bcm2835_bsc fdt arm/broadcom/bcm2835/bcm2835_clkman.c optional soc_brcm_bcm2837 fdt | soc_brcm_bcm2838 fdt arm/broadcom/bcm2835/bcm2835_cpufreq.c optional soc_brcm_bcm2837 fdt | soc_brcm_bcm2838 fdt arm/broadcom/bcm2835/bcm2835_dma.c optional soc_brcm_bcm2837 fdt | soc_brcm_bcm2838 fdt arm/broadcom/bcm2835/bcm2835_fbd.c optional vt soc_brcm_bcm2837 fdt | vt soc_brcm_bcm2838 fdt arm/broadcom/bcm2835/bcm2835_ft5406.c optional evdev bcm2835_ft5406 fdt arm/broadcom/bcm2835/bcm2835_gpio.c optional gpio soc_brcm_bcm2837 fdt | gpio soc_brcm_bcm2838 fdt arm/broadcom/bcm2835/bcm2835_intr.c optional soc_brcm_bcm2837 fdt | soc_brcm_bcm2838 fdt arm/broadcom/bcm2835/bcm2835_mbox.c optional soc_brcm_bcm2837 fdt | soc_brcm_bcm2838 fdt arm/broadcom/bcm2835/bcm2835_rng.c optional !random_loadable soc_brcm_bcm2837 fdt | !random_loadable soc_brcm_bcm2838 fdt arm/broadcom/bcm2835/bcm2835_sdhci.c optional sdhci soc_brcm_bcm2837 fdt | sdhci soc_brcm_bcm2838 fdt arm/broadcom/bcm2835/bcm2835_sdhost.c optional sdhci soc_brcm_bcm2837 fdt | sdhci soc_brcm_bcm2838 fdt arm/broadcom/bcm2835/bcm2835_spi.c optional bcm2835_spi fdt arm/broadcom/bcm2835/bcm2835_vcbus.c optional soc_brcm_bcm2837 fdt | soc_brcm_bcm2838 fdt arm/broadcom/bcm2835/bcm2835_vcio.c optional soc_brcm_bcm2837 fdt | soc_brcm_bcm2838 fdt arm/broadcom/bcm2835/bcm2835_wdog.c optional soc_brcm_bcm2837 fdt | soc_brcm_bcm2838 fdt arm/broadcom/bcm2835/bcm2836.c optional soc_brcm_bcm2837 fdt | soc_brcm_bcm2838 fdt arm/broadcom/bcm2835/bcm283x_dwc_fdt.c optional dwcotg fdt soc_brcm_bcm2837 | dwcotg fdt soc_brcm_bcm2838 arm/freescale/vybrid/vf_i2c.c optional vf_i2c iicbus SOC_NXP_LS arm/mv/a37x0_gpio.c optional a37x0_gpio gpio fdt arm/mv/a37x0_iic.c optional a37x0_iic iicbus fdt arm/mv/a37x0_spi.c optional a37x0_spi spibus fdt arm/mv/armada38x/armada38x_rtc.c optional mv_rtc fdt arm/mv/gpio.c optional mv_gpio fdt arm/mv/mvebu_pinctrl.c optional mvebu_pinctrl fdt arm/mv/mv_ap806_clock.c optional SOC_MARVELL_8K fdt arm/mv/mv_ap806_gicp.c optional mv_ap806_gicp fdt arm/mv/mv_ap806_sei.c optional mv_ap806_sei fdt arm/mv/mv_cp110_clock.c optional SOC_MARVELL_8K fdt arm/mv/mv_cp110_icu.c optional mv_cp110_icu fdt arm/mv/mv_cp110_icu_bus.c optional mv_cp110_icu fdt arm/mv/mv_thermal.c optional SOC_MARVELL_8K mv_thermal fdt arm/mv/armada38x/armada38x_rtc.c optional mv_rtc fdt arm/xilinx/uart_dev_cdnc.c optional uart soc_xilinx_zynq arm64/acpica/acpi_iort.c optional acpi arm64/acpica/acpi_machdep.c optional acpi arm64/acpica/OsdEnvironment.c optional acpi arm64/acpica/acpi_wakeup.c optional acpi arm64/acpica/pci_cfgreg.c optional acpi pci arm64/arm64/autoconf.c standard arm64/arm64/bus_machdep.c standard arm64/arm64/bus_space_asm.S standard arm64/arm64/busdma_bounce.c standard arm64/arm64/busdma_machdep.c standard arm64/arm64/bzero.S standard arm64/arm64/clock.c standard arm64/arm64/copyinout.S standard arm64/arm64/cpu_errata.c standard arm64/arm64/cpufunc_asm.S standard arm64/arm64/db_disasm.c optional ddb arm64/arm64/db_interface.c optional ddb arm64/arm64/db_trace.c optional ddb arm64/arm64/debug_monitor.c standard arm64/arm64/disassem.c optional ddb arm64/arm64/dump_machdep.c standard arm64/arm64/efirt_machdep.c optional efirt arm64/arm64/elf32_machdep.c optional compat_freebsd32 arm64/arm64/elf_machdep.c standard arm64/arm64/exception.S standard arm64/arm64/freebsd32_machdep.c optional compat_freebsd32 arm64/arm64/gicv3_its.c optional intrng fdt arm64/arm64/gic_v3.c standard arm64/arm64/gic_v3_acpi.c optional acpi arm64/arm64/gic_v3_fdt.c optional fdt arm64/arm64/identcpu.c standard arm64/arm64/in_cksum.c optional inet | inet6 arm64/arm64/locore.S standard no-obj arm64/arm64/machdep.c standard arm64/arm64/machdep_boot.c standard arm64/arm64/mem.c standard arm64/arm64/memcpy.S standard arm64/arm64/memmove.S standard arm64/arm64/minidump_machdep.c standard arm64/arm64/mp_machdep.c optional smp arm64/arm64/nexus.c standard arm64/arm64/ofw_machdep.c optional fdt arm64/arm64/pmap.c standard arm64/arm64/stack_machdep.c optional ddb | stack arm64/arm64/support.S standard arm64/arm64/swtch.S standard arm64/arm64/sys_machdep.c standard arm64/arm64/trap.c standard arm64/arm64/uio_machdep.c standard arm64/arm64/uma_machdep.c standard arm64/arm64/undefined.c standard arm64/arm64/unwind.c optional ddb | kdtrace_hooks | stack arm64/arm64/vfp.c standard arm64/arm64/vm_machdep.c standard arm64/broadcom/brcmmdio/mdio_mux_iproc.c optional fdt arm64/broadcom/brcmmdio/mdio_nexus_iproc.c optional fdt arm64/broadcom/brcmmdio/mdio_ns2_pcie_phy.c optional fdt pci arm64/broadcom/genet/if_genet.c optional SOC_BRCM_BCM2838 fdt genet arm64/cavium/thunder_pcie_fdt.c optional soc_cavm_thunderx pci fdt arm64/cavium/thunder_pcie_pem.c optional soc_cavm_thunderx pci arm64/cavium/thunder_pcie_pem_fdt.c optional soc_cavm_thunderx pci fdt arm64/cavium/thunder_pcie_common.c optional soc_cavm_thunderx pci arm64/cloudabi32/cloudabi32_sysvec.c optional compat_cloudabi32 arm64/cloudabi64/cloudabi64_sysvec.c optional compat_cloudabi64 arm64/coresight/coresight.c standard arm64/coresight/coresight_if.m standard arm64/coresight/coresight_cmd.c standard arm64/coresight/coresight_cpu_debug.c standard arm64/coresight/coresight_replicator.c standard arm64/coresight/coresight_etm4x.c standard arm64/coresight/coresight_etm4x_acpi.c optional acpi arm64/coresight/coresight_etm4x_fdt.c optional fdt arm64/coresight/coresight_funnel.c standard arm64/coresight/coresight_funnel_acpi.c optional acpi arm64/coresight/coresight_funnel_fdt.c optional fdt arm64/coresight/coresight_tmc.c standard +arm64/coresight/coresight_tmc_acpi.c optional acpi +arm64/coresight/coresight_tmc_fdt.c optional fdt arm64/intel/firmware.c optional soc_intel_stratix10 arm64/intel/stratix10-soc-fpga-mgr.c optional soc_intel_stratix10 arm64/intel/stratix10-svc.c optional soc_intel_stratix10 arm64/qoriq/ls1046_gpio.c optional ls1046_gpio gpio fdt SOC_NXP_LS arm64/qoriq/clk/ls1046a_clkgen.c optional clk SOC_NXP_LS arm64/qoriq/clk/qoriq_clk_pll.c optional clk SOC_NXP_LS arm64/qoriq/clk/qoriq_clkgen.c optional clk SOC_NXP_LS arm64/qualcomm/qcom_gcc.c optional qcom_gcc fdt contrib/vchiq/interface/compat/vchi_bsd.c optional vchiq soc_brcm_bcm2837 \ compile-with "${NORMAL_C} -DUSE_VCHIQ_ARM -D__VCCOREVER__=0x04000000 -I$S/contrib/vchiq" contrib/vchiq/interface/vchiq_arm/vchiq_2835_arm.c optional vchiq soc_brcm_bcm2837 \ compile-with "${NORMAL_C} -Wno-unused -DUSE_VCHIQ_ARM -D__VCCOREVER__=0x04000000 -I$S/contrib/vchiq" contrib/vchiq/interface/vchiq_arm/vchiq_arm.c optional vchiq soc_brcm_bcm2837 \ compile-with "${NORMAL_C} -Wno-unused -DUSE_VCHIQ_ARM -D__VCCOREVER__=0x04000000 -I$S/contrib/vchiq" contrib/vchiq/interface/vchiq_arm/vchiq_connected.c optional vchiq soc_brcm_bcm2837 \ compile-with "${NORMAL_C} -DUSE_VCHIQ_ARM -D__VCCOREVER__=0x04000000 -I$S/contrib/vchiq" contrib/vchiq/interface/vchiq_arm/vchiq_core.c optional vchiq soc_brcm_bcm2837 \ compile-with "${NORMAL_C} -DUSE_VCHIQ_ARM -D__VCCOREVER__=0x04000000 -I$S/contrib/vchiq" contrib/vchiq/interface/vchiq_arm/vchiq_kern_lib.c optional vchiq soc_brcm_bcm2837 \ compile-with "${NORMAL_C} -DUSE_VCHIQ_ARM -D__VCCOREVER__=0x04000000 -I$S/contrib/vchiq" contrib/vchiq/interface/vchiq_arm/vchiq_kmod.c optional vchiq soc_brcm_bcm2837 \ compile-with "${NORMAL_C} -DUSE_VCHIQ_ARM -D__VCCOREVER__=0x04000000 -I$S/contrib/vchiq" contrib/vchiq/interface/vchiq_arm/vchiq_shim.c optional vchiq soc_brcm_bcm2837 \ compile-with "${NORMAL_C} -DUSE_VCHIQ_ARM -D__VCCOREVER__=0x04000000 -I$S/contrib/vchiq" contrib/vchiq/interface/vchiq_arm/vchiq_util.c optional vchiq soc_brcm_bcm2837 \ compile-with "${NORMAL_C} -DUSE_VCHIQ_ARM -D__VCCOREVER__=0x04000000 -I$S/contrib/vchiq" crypto/armv8/armv8_crypto.c optional armv8crypto armv8_crypto_wrap.o optional armv8crypto \ dependency "$S/crypto/armv8/armv8_crypto_wrap.c" \ compile-with "${CC} -c ${CFLAGS:C/^-O2$/-O3/:N-nostdinc:N-mgeneral-regs-only} -I$S/crypto/armv8/ ${WERROR} ${NO_WCAST_QUAL} ${PROF} -march=armv8-a+crypto ${.IMPSRC}" \ no-implicit-rule \ clean "armv8_crypto_wrap.o" crypto/des/des_enc.c optional netsmb dev/acpica/acpi_bus_if.m optional acpi dev/acpica/acpi_if.m optional acpi dev/acpica/acpi_pci_link.c optional acpi pci dev/acpica/acpi_pcib.c optional acpi pci dev/acpica/acpi_pxm.c optional acpi dev/ahci/ahci_fsl_fdt.c optional SOC_NXP_LS ahci fdt dev/ahci/ahci_generic.c optional ahci dev/altera/dwc/if_dwc_socfpga.c optional fdt dwc_socfpga dev/axgbe/if_axgbe.c optional axgbe dev/axgbe/xgbe-desc.c optional axgbe dev/axgbe/xgbe-dev.c optional axgbe dev/axgbe/xgbe-drv.c optional axgbe dev/axgbe/xgbe-mdio.c optional axgbe dev/cpufreq/cpufreq_dt.c optional cpufreq fdt dev/ice/if_ice_iflib.c optional ice pci \ compile-with "${NORMAL_C} -I$S/dev/ice" dev/ice/ice_lib.c optional ice pci \ compile-with "${NORMAL_C} -I$S/dev/ice" dev/ice/ice_osdep.c optional ice pci \ compile-with "${NORMAL_C} -I$S/dev/ice" dev/ice/ice_resmgr.c optional ice pci \ compile-with "${NORMAL_C} -I$S/dev/ice" dev/ice/ice_strings.c optional ice pci \ compile-with "${NORMAL_C} -I$S/dev/ice" dev/ice/ice_iflib_recovery_txrx.c optional ice pci \ compile-with "${NORMAL_C} -I$S/dev/ice" dev/ice/ice_iflib_txrx.c optional ice pci \ compile-with "${NORMAL_C} -I$S/dev/ice" dev/ice/ice_common.c optional ice pci \ compile-with "${NORMAL_C} -I$S/dev/ice" dev/ice/ice_controlq.c optional ice pci \ compile-with "${NORMAL_C} -I$S/dev/ice" dev/ice/ice_dcb.c optional ice pci \ compile-with "${NORMAL_C} -I$S/dev/ice" dev/ice/ice_flex_pipe.c optional ice pci \ compile-with "${NORMAL_C} -I$S/dev/ice" dev/ice/ice_flow.c optional ice pci \ compile-with "${NORMAL_C} -I$S/dev/ice" dev/ice/ice_nvm.c optional ice pci \ compile-with "${NORMAL_C} -I$S/dev/ice" dev/ice/ice_sched.c optional ice pci \ compile-with "${NORMAL_C} -I$S/dev/ice" dev/ice/ice_sriov.c optional ice pci \ compile-with "${NORMAL_C} -I$S/dev/ice" dev/ice/ice_switch.c optional ice pci \ compile-with "${NORMAL_C} -I$S/dev/ice" ice_ddp.c optional ice_ddp \ compile-with "${AWK} -f $S/tools/fw_stub.awk ice_ddp.fw:ice_ddp:0x01030900 -mice_ddp -c${.TARGET}" \ no-implicit-rule before-depend local \ clean "ice_ddp.c" ice_ddp.fwo optional ice_ddp \ dependency "ice_ddp.fw" \ compile-with "${NORMAL_FWO}" \ no-implicit-rule \ clean "ice_ddp.fwo" ice_ddp.fw optional ice_ddp \ dependency "$S/contrib/dev/ice/ice-1.3.9.0.pkg" \ compile-with "${CP} $S/contrib/dev/ice/ice-1.3.9.0.pkg ice_ddp.fw" \ no-obj no-implicit-rule \ clean "ice_ddp.fw" dev/iicbus/sy8106a.c optional sy8106a fdt dev/iicbus/twsi/mv_twsi.c optional twsi fdt dev/iicbus/twsi/a10_twsi.c optional twsi fdt dev/iicbus/twsi/twsi.c optional twsi fdt dev/hwpmc/hwpmc_arm64.c optional hwpmc dev/hwpmc/hwpmc_arm64_md.c optional hwpmc dev/mbox/mbox_if.m optional soc_brcm_bcm2837 dev/mmc/host/dwmmc.c optional dwmmc fdt dev/mmc/host/dwmmc_altera.c optional dwmmc dwmmc_altera fdt dev/mmc/host/dwmmc_hisi.c optional dwmmc dwmmc_hisi fdt dev/mmc/host/dwmmc_rockchip.c optional dwmmc rk_dwmmc fdt dev/neta/if_mvneta_fdt.c optional neta fdt dev/neta/if_mvneta.c optional neta mdio mii dev/ofw/ofw_cpu.c optional fdt dev/ofw/ofwpci.c optional fdt pci dev/pci/controller/pci_n1sdp.c optional pci_n1sdp acpi dev/pci/pci_host_generic.c optional pci dev/pci/pci_host_generic_acpi.c optional pci acpi dev/pci/pci_host_generic_fdt.c optional pci fdt dev/pci/pci_dw_mv.c optional pci fdt dev/pci/pci_dw.c optional pci fdt dev/pci/pci_dw_if.m optional pci fdt dev/psci/psci.c standard dev/psci/smccc_arm64.S standard dev/psci/smccc.c standard dev/sdhci/sdhci_xenon.c optional sdhci_xenon sdhci fdt dev/uart/uart_cpu_arm64.c optional uart dev/uart/uart_dev_mu.c optional uart uart_mu dev/uart/uart_dev_pl011.c optional uart pl011 dev/usb/controller/dwc_otg_hisi.c optional dwcotg fdt soc_hisi_hi6220 dev/usb/controller/dwc3.c optional fdt dwc3 dev/usb/controller/ehci_mv.c optional ehci_mv fdt dev/usb/controller/generic_ehci.c optional ehci dev/usb/controller/generic_ehci_acpi.c optional ehci acpi dev/usb/controller/generic_ehci_fdt.c optional ehci fdt dev/usb/controller/generic_ohci.c optional ohci fdt dev/usb/controller/generic_usb_if.m optional ohci fdt dev/usb/controller/usb_nop_xceiv.c optional fdt ext_resources dev/usb/controller/generic_xhci.c optional xhci dev/usb/controller/generic_xhci_acpi.c optional xhci acpi dev/usb/controller/generic_xhci_fdt.c optional xhci fdt dev/vnic/mrml_bridge.c optional vnic fdt dev/vnic/nic_main.c optional vnic pci dev/vnic/nicvf_main.c optional vnic pci pci_iov dev/vnic/nicvf_queues.c optional vnic pci pci_iov dev/vnic/thunder_bgx_fdt.c optional vnic fdt dev/vnic/thunder_bgx.c optional vnic pci dev/vnic/thunder_mdio_fdt.c optional vnic fdt dev/vnic/thunder_mdio.c optional vnic dev/vnic/lmac_if.m optional inet | inet6 | vnic kern/kern_clocksource.c standard kern/msi_if.m optional intrng kern/pic_if.m optional intrng kern/subr_devmap.c standard kern/subr_intr.c optional intrng kern/subr_physmem.c standard libkern/bcmp.c standard libkern/memcmp.c standard \ compile-with "${NORMAL_C:N-fsanitize*}" libkern/memset.c standard \ compile-with "${NORMAL_C:N-fsanitize*}" libkern/arm64/crc32c_armv8.S standard cddl/dev/dtrace/aarch64/dtrace_asm.S optional dtrace compile-with "${DTRACE_S}" cddl/dev/dtrace/aarch64/dtrace_subr.c optional dtrace compile-with "${DTRACE_C}" cddl/dev/fbt/aarch64/fbt_isa.c optional dtrace_fbt | dtraceall compile-with "${FBT_C}" # RockChip Drivers arm64/rockchip/rk3399_emmcphy.c optional fdt rk_emmcphy soc_rockchip_rk3399 arm64/rockchip/rk_dwc3.c optional fdt rk_dwc3 soc_rockchip_rk3399 arm64/rockchip/rk_i2c.c optional fdt rk_i2c soc_rockchip_rk3328 | fdt rk_i2c soc_rockchip_rk3399 arm64/rockchip/rk805.c optional fdt rk805 soc_rockchip_rk3328 | fdt rk805 soc_rockchip_rk3399 arm64/rockchip/rk_grf.c optional fdt soc_rockchip_rk3328 | fdt soc_rockchip_rk3399 arm64/rockchip/rk_pinctrl.c optional fdt rk_pinctrl soc_rockchip_rk3328 | fdt rk_pinctrl soc_rockchip_rk3399 arm64/rockchip/rk_gpio.c optional fdt rk_gpio soc_rockchip_rk3328 | fdt rk_gpio soc_rockchip_rk3399 arm64/rockchip/rk_iodomain.c optional fdt rk_iodomain arm64/rockchip/rk_spi.c optional fdt rk_spi arm64/rockchip/rk_usb2phy.c optional fdt rk_usb2phy soc_rockchip_rk3328 | soc_rockchip_rk3399 arm64/rockchip/rk_typec_phy.c optional fdt rk_typec_phy soc_rockchip_rk3399 arm64/rockchip/if_dwc_rk.c optional fdt dwc_rk soc_rockchip_rk3328 | fdt dwc_rk soc_rockchip_rk3399 arm64/rockchip/rk_tsadc_if.m optional fdt soc_rockchip_rk3399 arm64/rockchip/rk_tsadc.c optional fdt soc_rockchip_rk3399 arm64/rockchip/rk_pwm.c optional fdt rk_pwm arm64/rockchip/rk_pcie.c optional fdt pci soc_rockchip_rk3399 arm64/rockchip/rk_pcie_phy.c optional fdt pci soc_rockchip_rk3399 dev/dwc/if_dwc.c optional fdt dwc_rk soc_rockchip_rk3328 | fdt dwc_rk soc_rockchip_rk3399 dev/dwc/if_dwc_if.m optional fdt dwc_rk soc_rockchip_rk3328 | fdt dwc_rk soc_rockchip_rk3399 # RockChip Clock support arm64/rockchip/clk/rk_cru.c optional fdt soc_rockchip_rk3328 | fdt soc_rockchip_rk3399 arm64/rockchip/clk/rk_clk_armclk.c optional fdt soc_rockchip_rk3328 | fdt soc_rockchip_rk3399 arm64/rockchip/clk/rk_clk_composite.c optional fdt soc_rockchip_rk3328 | fdt soc_rockchip_rk3399 arm64/rockchip/clk/rk_clk_fract.c optional fdt soc_rockchip_rk3328 | fdt soc_rockchip_rk3399 arm64/rockchip/clk/rk_clk_gate.c optional fdt soc_rockchip_rk3328 | fdt soc_rockchip_rk3399 arm64/rockchip/clk/rk_clk_mux.c optional fdt soc_rockchip_rk3328 | fdt soc_rockchip_rk3399 arm64/rockchip/clk/rk_clk_pll.c optional fdt soc_rockchip_rk3328 | fdt soc_rockchip_rk3399 arm64/rockchip/clk/rk3328_cru.c optional fdt soc_rockchip_rk3328 arm64/rockchip/clk/rk3399_cru.c optional fdt soc_rockchip_rk3399 arm64/rockchip/clk/rk3399_pmucru.c optional fdt soc_rockchip_rk3399