Index: head/sys/arm64/broadcom/brcmmdio/mdio_mux_iproc.c =================================================================== --- head/sys/arm64/broadcom/brcmmdio/mdio_mux_iproc.c (nonexistent) +++ head/sys/arm64/broadcom/brcmmdio/mdio_mux_iproc.c (revision 359647) @@ -0,0 +1,399 @@ +/*- + * Copyright (c) 2019 Juniper Networks, Inc. + * Copyright (c) 2019 Semihalf. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, + * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include +__FBSDID("$FreeBSD$"); + +#include +#include +#include +#include +#include +#include + +#include +#include +#include + +#include +#include + +#include "mdio_if.h" + +#define REG_BASE_RID 0 + +#define MDIO_RATE_ADJ_EXT_OFFSET 0x000 +#define MDIO_RATE_ADJ_INT_OFFSET 0x004 +#define MDIO_RATE_ADJ_DIVIDENT_SHIFT 16 + +#define MDIO_SCAN_CTRL_OFFSET 0x008 +#define MDIO_SCAN_CTRL_OVRIDE_EXT_MSTR 28 + +#define MDIO_PARAM_OFFSET 0x23c +#define MDIO_PARAM_MIIM_CYCLE 29 +#define MDIO_PARAM_INTERNAL_SEL 25 +#define MDIO_PARAM_BUS_ID 22 +#define MDIO_PARAM_C45_SEL 21 +#define MDIO_PARAM_PHY_ID 16 +#define MDIO_PARAM_PHY_DATA 0 + +#define MDIO_READ_OFFSET 0x240 +#define MDIO_READ_DATA_MASK 0xffff +#define MDIO_ADDR_OFFSET 0x244 + +#define MDIO_CTRL_OFFSET 0x248 +#define MDIO_CTRL_WRITE_OP 0x1 +#define MDIO_CTRL_READ_OP 0x2 + +#define MDIO_STAT_OFFSET 0x24c +#define MDIO_STAT_DONE 1 + +#define BUS_MAX_ADDR 32 +#define EXT_BUS_START_ADDR 16 + +#define MDIO_REG_ADDR_SPACE_SIZE 0x250 + +#define MDIO_OPERATING_FREQUENCY 11000000 +#define MDIO_RATE_ADJ_DIVIDENT 1 + +#define MII_ADDR_C45 (1<<30) + +static int brcm_iproc_mdio_probe(device_t); +static int brcm_iproc_mdio_attach(device_t); +static int brcm_iproc_mdio_detach(device_t); + +/* OFW bus interface */ +struct brcm_mdio_ofw_devinfo { + struct ofw_bus_devinfo di_dinfo; + struct resource_list di_rl; +}; + +struct brcm_iproc_mdio_softc { + struct simplebus_softc sbus; + device_t dev; + struct resource * reg_base; + uint32_t clock_rate; +}; + +MALLOC_DEFINE(M_BRCM_IPROC_MDIO, "Broadcom IPROC MDIO", + "Broadcom IPROC MDIO dynamic memory"); + +static int brcm_iproc_config(struct brcm_iproc_mdio_softc*); +static const struct ofw_bus_devinfo * +brcm_iproc_mdio_get_devinfo(device_t, device_t); +static int brcm_iproc_mdio_write_mux(device_t, int, int, int, int); +static int brcm_iproc_mdio_read_mux(device_t, int, int, int); + +static device_method_t brcm_iproc_mdio_fdt_methods[] = { + /* Device interface */ + DEVMETHOD(device_probe, brcm_iproc_mdio_probe), + DEVMETHOD(device_attach, brcm_iproc_mdio_attach), + DEVMETHOD(device_detach, brcm_iproc_mdio_detach), + + /* Bus interface */ + DEVMETHOD(bus_alloc_resource, bus_generic_alloc_resource), + DEVMETHOD(bus_release_resource, bus_generic_release_resource), + DEVMETHOD(bus_activate_resource, bus_generic_activate_resource), + + /* ofw_bus interface */ + DEVMETHOD(ofw_bus_get_devinfo, brcm_iproc_mdio_get_devinfo), + DEVMETHOD(ofw_bus_get_compat, ofw_bus_gen_get_compat), + DEVMETHOD(ofw_bus_get_model, ofw_bus_gen_get_model), + DEVMETHOD(ofw_bus_get_name, ofw_bus_gen_get_name), + DEVMETHOD(ofw_bus_get_node, ofw_bus_gen_get_node), + DEVMETHOD(ofw_bus_get_type, ofw_bus_gen_get_type), + + /* MDIO interface */ + DEVMETHOD(mdio_writereg_mux, brcm_iproc_mdio_write_mux), + DEVMETHOD(mdio_readreg_mux, brcm_iproc_mdio_read_mux), + + /* End */ + DEVMETHOD_END +}; + +DEFINE_CLASS_0(brcm_iproc_mdio, brcm_iproc_mdio_driver, + brcm_iproc_mdio_fdt_methods, sizeof(struct brcm_iproc_mdio_softc)); + +static devclass_t brcm_iproc_mdio_fdt_devclass; + +EARLY_DRIVER_MODULE(brcm_iproc_mdio, ofwbus, brcm_iproc_mdio_driver, + brcm_iproc_mdio_fdt_devclass, 0, 0, BUS_PASS_BUS + BUS_PASS_ORDER_MIDDLE); +EARLY_DRIVER_MODULE(brcm_iproc_mdio, simplebus, brcm_iproc_mdio_driver, + brcm_iproc_mdio_fdt_devclass, 0, 0, BUS_PASS_BUS + BUS_PASS_ORDER_MIDDLE); + +static struct ofw_compat_data mdio_compat_data[] = { + {"brcm,mdio-mux-iproc", true}, + {NULL, false} +}; + +static int +brcm_iproc_switch(struct brcm_iproc_mdio_softc *sc, int child) +{ + uint32_t param, bus_id; + uint32_t bus_dir; + + /* select bus and its properties */ + bus_dir = (child < EXT_BUS_START_ADDR); + bus_id = bus_dir ? child : (child - EXT_BUS_START_ADDR); + + param = (bus_dir ? 1 : 0) << MDIO_PARAM_INTERNAL_SEL; + param |= (bus_id << MDIO_PARAM_BUS_ID); + + bus_write_4(sc->reg_base, MDIO_PARAM_OFFSET, param); + + return (0); +} + +static int +iproc_mdio_wait_for_idle(struct brcm_iproc_mdio_softc *sc, uint32_t result) +{ + unsigned int timeout = 1000; /* loop for 1s */ + uint32_t val; + + do { + val = bus_read_4(sc->reg_base, MDIO_STAT_OFFSET); + if ((val & MDIO_STAT_DONE) == result) + return (0); + + pause("BRCM MDIO SLEEP", 1000 / hz); + } while (timeout--); + + return (ETIMEDOUT); +} + +/* start_miim_ops- Program and start MDIO transaction over mdio bus. + * @base: Base address + * @phyid: phyid of the selected bus. + * @reg: register offset to be read/written. + * @val :0 if read op else value to be written in @reg; + * @op: Operation that need to be carried out. + * MDIO_CTRL_READ_OP: Read transaction. + * MDIO_CTRL_WRITE_OP: Write transaction. + * + * Return value: Successful Read operation returns read reg values and write + * operation returns 0. Failure operation returns negative error code. + */ +static int +brcm_iproc_mdio_op(struct brcm_iproc_mdio_softc *sc, + uint16_t phyid, uint32_t reg, uint32_t val, uint32_t op) +{ + uint32_t param; + int ret; + + bus_write_4(sc->reg_base, MDIO_CTRL_OFFSET, 0); + bus_read_4(sc->reg_base, MDIO_STAT_OFFSET); + ret = iproc_mdio_wait_for_idle(sc, 0); + if (ret) + goto err; + + param = bus_read_4(sc->reg_base, MDIO_PARAM_OFFSET); + param |= phyid << MDIO_PARAM_PHY_ID; + param |= val << MDIO_PARAM_PHY_DATA; + if (reg & MII_ADDR_C45) + param |= (1 << MDIO_PARAM_C45_SEL); + + bus_write_4(sc->reg_base, MDIO_PARAM_OFFSET, param); + + bus_write_4(sc->reg_base, MDIO_ADDR_OFFSET, reg); + + bus_write_4(sc->reg_base, MDIO_CTRL_OFFSET, op); + + ret = iproc_mdio_wait_for_idle(sc, 1); + if (ret) + goto err; + + if (op == MDIO_CTRL_READ_OP) + ret = bus_read_4(sc->reg_base, MDIO_READ_OFFSET) & MDIO_READ_DATA_MASK; +err: + return ret; +} + +static int +brcm_iproc_config(struct brcm_iproc_mdio_softc *sc) +{ + uint32_t divisor; + uint32_t val; + + /* Disable external mdio master access */ + val = bus_read_4(sc->reg_base, MDIO_SCAN_CTRL_OFFSET); + val |= 1 << MDIO_SCAN_CTRL_OVRIDE_EXT_MSTR; + bus_write_4(sc->reg_base, MDIO_SCAN_CTRL_OFFSET, val); + + if (sc->clock_rate) { + /* use rate adjust regs to derrive the mdio's operating + * frequency from the specified core clock + */ + divisor = sc->clock_rate / MDIO_OPERATING_FREQUENCY; + divisor = divisor / (MDIO_RATE_ADJ_DIVIDENT + 1); + val = divisor; + val |= MDIO_RATE_ADJ_DIVIDENT << MDIO_RATE_ADJ_DIVIDENT_SHIFT; + bus_write_4(sc->reg_base, MDIO_RATE_ADJ_EXT_OFFSET, val); + bus_write_4(sc->reg_base, MDIO_RATE_ADJ_INT_OFFSET, val); + } + + return (0); +} + +static int +brcm_iproc_mdio_write_mux(device_t dev, int bus, int phy, int reg, int val) +{ + struct brcm_iproc_mdio_softc *sc; + + sc = device_get_softc(dev); + + if (brcm_iproc_switch(sc, bus) != 0) { + device_printf(dev, "Failed to set BUS MUX\n"); + return (EINVAL); + } + + return (brcm_iproc_mdio_op(sc, phy, reg, val, MDIO_CTRL_WRITE_OP)); +} + +static int +brcm_iproc_mdio_read_mux(device_t dev, int bus, int phy, int reg) +{ + struct brcm_iproc_mdio_softc *sc; + + sc = device_get_softc(dev); + + if (brcm_iproc_switch(sc, bus) != 0) { + device_printf(dev, "Failed to set BUS MUX\n"); + return (EINVAL); + } + + return (brcm_iproc_mdio_op(sc, phy, reg, 0, MDIO_CTRL_READ_OP)); +} + +static int +brcm_iproc_mdio_probe(device_t dev) +{ + + if (!ofw_bus_status_okay(dev)) + return (ENXIO); + if (!ofw_bus_search_compatible(dev, mdio_compat_data)->ocd_data) + return (ENXIO); + + device_set_desc(dev, "Broadcom MDIO MUX driver"); + return (BUS_PROBE_DEFAULT); +} + +static int +brcm_iproc_mdio_attach(device_t dev) +{ + struct brcm_iproc_mdio_softc *sc; + phandle_t node, parent; + struct brcm_mdio_ofw_devinfo *di; + int rid; + device_t child; + + sc = device_get_softc(dev); + sc->dev = dev; + + /* Allocate memory resources */ + rid = REG_BASE_RID; + sc->reg_base = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, + RF_ACTIVE); + if (sc->reg_base == NULL) { + device_printf(dev, "Could not allocate memory\n"); + return (ENXIO); + } + + /* Configure MDIO controlled */ + if (brcm_iproc_config(sc) < 0) { + device_printf(dev, "Unable to initialize IPROC MDIO\n"); + goto error; + } + + parent = ofw_bus_get_node(dev); + simplebus_init(dev, parent); + + /* Iterate through all bus subordinates */ + for (node = OF_child(parent); node > 0; node = OF_peer(node)) { + /* Allocate and populate devinfo. */ + di = malloc(sizeof(*di), M_BRCM_IPROC_MDIO, M_WAITOK | M_ZERO); + if (ofw_bus_gen_setup_devinfo(&di->di_dinfo, node) != 0) { + free(di, M_BRCM_IPROC_MDIO); + continue; + } + + /* Initialize and populate resource list. */ + resource_list_init(&di->di_rl); + ofw_bus_reg_to_rl(dev, node, sc->sbus.acells, sc->sbus.scells, + &di->di_rl); + ofw_bus_intr_to_rl(dev, node, &di->di_rl, NULL); + + /* Add newbus device for this FDT node */ + child = device_add_child(dev, NULL, -1); + if (child == NULL) { + printf("Failed to add child\n"); + resource_list_free(&di->di_rl); + ofw_bus_gen_destroy_devinfo(&di->di_dinfo); + free(di, M_BRCM_IPROC_MDIO); + continue; + } + + device_set_ivars(child, di); + } + + /* + * Register device to this node/xref. + * Thanks to that we will be able to retrieve device_t structure + * while holding only node reference acquired from FDT. + */ + node = ofw_bus_get_node(dev); + OF_device_register_xref(OF_xref_from_node(node), dev); + + return (bus_generic_attach(dev)); + +error: + brcm_iproc_mdio_detach(dev); + return (ENXIO); +} + +static const struct ofw_bus_devinfo * +brcm_iproc_mdio_get_devinfo(device_t bus __unused, device_t child) +{ + struct brcm_mdio_ofw_devinfo *di; + + di = device_get_ivars(child); + return (&di->di_dinfo); +} + +static int +brcm_iproc_mdio_detach(device_t dev) +{ + struct brcm_iproc_mdio_softc *sc; + + sc = device_get_softc(dev); + + if (sc->reg_base != NULL) { + bus_release_resource(dev, SYS_RES_MEMORY, REG_BASE_RID, + sc->reg_base); + } + + return (0); +} Property changes on: head/sys/arm64/broadcom/brcmmdio/mdio_mux_iproc.c ___________________________________________________________________ Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:keywords ## -0,0 +1 ## +FreeBSD=%H \ No newline at end of property Added: svn:mime-type ## -0,0 +1 ## +text/plain \ No newline at end of property Index: head/sys/arm64/broadcom/brcmmdio/mdio_nexus_iproc.c =================================================================== --- head/sys/arm64/broadcom/brcmmdio/mdio_nexus_iproc.c (nonexistent) +++ head/sys/arm64/broadcom/brcmmdio/mdio_nexus_iproc.c (revision 359647) @@ -0,0 +1,234 @@ +/*- + * Copyright (c) 2019 Juniper Networks, Inc. + * Copyright (c) 2019 Semihalf. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, + * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include +__FBSDID("$FreeBSD$"); + +#include +#include +#include +#include +#include +#include + +#include +#include +#include + +#include +#include + +#include "mdio_if.h" + +MALLOC_DEFINE(M_BRCM_IPROC_NEXUS, "Broadcom IPROC MDIO NEXUS", + "Broadcom IPROC MDIO NEXUS dynamic memory"); + +struct brcm_mdionexus_softc { + struct simplebus_softc simplebus_sc; + uint32_t mux_id; +}; + +/* OFW bus interface */ +struct brcm_mdionexus_ofw_devinfo { + struct ofw_bus_devinfo di_dinfo; + struct resource_list di_rl; +}; + +static device_probe_t brcm_mdionexus_fdt_probe; +static device_attach_t brcm_mdionexus_fdt_attach; + +static const struct ofw_bus_devinfo * brcm_mdionexus_ofw_get_devinfo(device_t, + device_t); +static int brcm_mdionexus_mdio_readreg(device_t, int, int); +static int brcm_mdionexus_mdio_writereg(device_t, int, int, int); + +static device_method_t brcm_mdionexus_fdt_methods[] = { + /* Device interface */ + DEVMETHOD(device_probe, brcm_mdionexus_fdt_probe), + DEVMETHOD(device_attach, brcm_mdionexus_fdt_attach), + + /* Bus interface */ + DEVMETHOD(bus_alloc_resource, bus_generic_alloc_resource), + DEVMETHOD(bus_release_resource, bus_generic_release_resource), + DEVMETHOD(bus_activate_resource, bus_generic_activate_resource), + + /* ofw_bus interface */ + DEVMETHOD(ofw_bus_get_devinfo, brcm_mdionexus_ofw_get_devinfo), + DEVMETHOD(ofw_bus_get_compat, ofw_bus_gen_get_compat), + DEVMETHOD(ofw_bus_get_model, ofw_bus_gen_get_model), + DEVMETHOD(ofw_bus_get_name, ofw_bus_gen_get_name), + DEVMETHOD(ofw_bus_get_node, ofw_bus_gen_get_node), + DEVMETHOD(ofw_bus_get_type, ofw_bus_gen_get_type), + + /* MDIO interface */ + /* MDIO interface */ + DEVMETHOD(mdio_readreg, brcm_mdionexus_mdio_readreg), + DEVMETHOD(mdio_writereg, brcm_mdionexus_mdio_writereg), + + DEVMETHOD_END +}; + +DEFINE_CLASS_0(brcm_mdionexus, brcm_mdionexus_fdt_driver, brcm_mdionexus_fdt_methods, + sizeof(struct brcm_mdionexus_softc)); + +static devclass_t brcm_mdionexus_fdt_devclass; + +static driver_t brcm_mdionexus_driver = { + "brcm_mdionexus", + brcm_mdionexus_fdt_methods, + sizeof(struct brcm_mdionexus_softc) +}; +EARLY_DRIVER_MODULE(brcm_mdionexus, brcm_iproc_mdio, brcm_mdionexus_driver, + brcm_mdionexus_fdt_devclass, NULL, NULL, BUS_PASS_BUS + BUS_PASS_ORDER_MIDDLE); + +static int brcm_mdionexus_ofw_bus_attach(device_t); + +static int +brcm_mdionexus_mdio_readreg(device_t dev, int phy, int reg) +{ + struct brcm_mdionexus_softc *sc; + + sc = device_get_softc(dev); + + return (MDIO_READREG_MUX(device_get_parent(dev), + sc->mux_id, phy, reg)); +} + +static int +brcm_mdionexus_mdio_writereg(device_t dev, int phy, int reg, int val) +{ + struct brcm_mdionexus_softc *sc; + + sc = device_get_softc(dev); + + return (MDIO_WRITEREG_MUX(device_get_parent(dev), + sc->mux_id, phy, reg, val)); +} + +static __inline void +get_addr_size_cells(phandle_t node, pcell_t *addr_cells, pcell_t *size_cells) +{ + + *addr_cells = 2; + /* Find address cells if present */ + OF_getencprop(node, "#address-cells", addr_cells, sizeof(*addr_cells)); + + *size_cells = 2; + /* Find size cells if present */ + OF_getencprop(node, "#size-cells", size_cells, sizeof(*size_cells)); +} + +static int +brcm_mdionexus_fdt_probe(device_t dev) +{ + + if (!ofw_bus_status_okay(dev)) + return (ENXIO); + device_set_desc(dev, "Broadcom MDIO nexus"); + return (BUS_PROBE_SPECIFIC); +} + +static int +brcm_mdionexus_fdt_attach(device_t dev) +{ + struct brcm_mdionexus_softc *sc; + int err; + pcell_t addr_cells, size_cells, buf[2]; + phandle_t node; + + sc = device_get_softc(dev); + + node = ofw_bus_get_node(dev); + get_addr_size_cells(node, &addr_cells, &size_cells); + if ((addr_cells != 1) || (size_cells != 0)) { + device_printf(dev, "Only addr_cells=1 and size_cells=0 are supported\n"); + return (EINVAL); + } + + if (OF_getencprop(node, "reg", buf, sizeof(pcell_t)) < 0) + return (ENXIO); + + sc->mux_id = buf[0]; + + err = brcm_mdionexus_ofw_bus_attach(dev); + if (err != 0) + return (err); + + return (bus_generic_attach(dev)); +} + +static const struct ofw_bus_devinfo * +brcm_mdionexus_ofw_get_devinfo(device_t bus __unused, device_t child) +{ + struct brcm_mdionexus_ofw_devinfo *di; + + di = device_get_ivars(child); + return (&di->di_dinfo); +} + +static int +brcm_mdionexus_ofw_bus_attach(device_t dev) +{ + struct simplebus_softc *sc; + struct brcm_mdionexus_ofw_devinfo *di; + device_t child; + phandle_t parent, node; + + parent = ofw_bus_get_node(dev); + simplebus_init(dev, parent); + + sc = (struct simplebus_softc *)device_get_softc(dev); + + /* Iterate through all bus subordinates */ + for (node = OF_child(parent); node > 0; node = OF_peer(node)) { + /* Allocate and populate devinfo. */ + di = malloc(sizeof(*di), M_BRCM_IPROC_NEXUS, M_WAITOK | M_ZERO); + if (ofw_bus_gen_setup_devinfo(&di->di_dinfo, node) != 0) { + free(di, M_BRCM_IPROC_NEXUS); + continue; + } + + /* Initialize and populate resource list. */ + resource_list_init(&di->di_rl); + ofw_bus_reg_to_rl(dev, node, sc->acells, sc->scells, + &di->di_rl); + ofw_bus_intr_to_rl(dev, node, &di->di_rl, NULL); + + /* Add newbus device for this FDT node */ + child = device_add_child(dev, NULL, -1); + if (child == NULL) { + resource_list_free(&di->di_rl); + ofw_bus_gen_destroy_devinfo(&di->di_dinfo); + free(di, M_BRCM_IPROC_NEXUS); + continue; + } + + device_set_ivars(child, di); + } + + return (0); +} Property changes on: head/sys/arm64/broadcom/brcmmdio/mdio_nexus_iproc.c ___________________________________________________________________ Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:keywords ## -0,0 +1 ## +FreeBSD=%H \ No newline at end of property Added: svn:mime-type ## -0,0 +1 ## +text/plain \ No newline at end of property Index: head/sys/arm64/broadcom/brcmmdio/mdio_ns2_pcie_phy.c =================================================================== --- head/sys/arm64/broadcom/brcmmdio/mdio_ns2_pcie_phy.c (nonexistent) +++ head/sys/arm64/broadcom/brcmmdio/mdio_ns2_pcie_phy.c (revision 359647) @@ -0,0 +1,162 @@ +/*- + * Copyright (c) 2019 Juniper Networks, Inc. + * Copyright (c) 2019 Semihalf. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, + * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, + * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include +__FBSDID("$FreeBSD$"); + +#include +#include +#include +#include +#include +#include + +#include +#include +#include + +#include +#include + +#include "mdio_if.h" + +#define BLK_ADDR_REG_OFFSET 0x1f +#define PLL_AFE1_100MHZ_BLK 0x2100 +#define PLL_CLK_AMP_OFFSET 0x03 +#define PLL_CLK_AMP_2P05V 0x2b18 + +struct ns2_pcie_phy_softc { + uint32_t phy_id; +}; + +static device_probe_t ns2_pcie_phy_fdt_probe; +static device_attach_t ns2_pcie_phy_fdt_attach; + +static int ns2_pci_phy_init(device_t dev); + +static device_method_t ns2_pcie_phy_fdt_methods[] = { + /* Device interface */ + DEVMETHOD(device_probe, ns2_pcie_phy_fdt_probe), + DEVMETHOD(device_attach, ns2_pcie_phy_fdt_attach), + + DEVMETHOD_END +}; + +DEFINE_CLASS_0(ns2_pcie_phy, ns2_pcie_phy_fdt_driver, ns2_pcie_phy_fdt_methods, + sizeof(struct ns2_pcie_phy_softc)); + +static devclass_t ns2_pcie_phy_fdt_devclass; + +static driver_t ns2_pcie_phy_driver = { + "ns2_pcie_phy", + ns2_pcie_phy_fdt_methods, + sizeof(struct ns2_pcie_phy_softc) +}; +EARLY_DRIVER_MODULE(ns2_pcie_phy, brcm_mdionexus, ns2_pcie_phy_driver, + ns2_pcie_phy_fdt_devclass, NULL, NULL, BUS_PASS_BUS + BUS_PASS_ORDER_MIDDLE); + +static int +ns2_pci_phy_init(device_t dev) +{ + struct ns2_pcie_phy_softc *sc; + int err; + + sc = device_get_softc(dev); + + /* select the AFE 100MHz block page */ + err = MDIO_WRITEREG(device_get_parent(dev), sc->phy_id, + BLK_ADDR_REG_OFFSET, PLL_AFE1_100MHZ_BLK); + if (err) + goto err; + + /* set the 100 MHz reference clock amplitude to 2.05 v */ + err = MDIO_WRITEREG(device_get_parent(dev), sc->phy_id, + PLL_CLK_AMP_OFFSET, PLL_CLK_AMP_2P05V); + if (err) + goto err; + + return 0; + +err: + device_printf(dev, "Error %d writing to phy\n", err); + return (err); +} + +static __inline void +get_addr_size_cells(phandle_t node, pcell_t *addr_cells, pcell_t *size_cells) +{ + + *addr_cells = 2; + /* Find address cells if present */ + OF_getencprop(node, "#address-cells", addr_cells, sizeof(*addr_cells)); + + *size_cells = 2; + /* Find size cells if present */ + OF_getencprop(node, "#size-cells", size_cells, sizeof(*size_cells)); +} + +static int +ns2_pcie_phy_fdt_probe(device_t dev) +{ + + if (!ofw_bus_status_okay(dev)) + return (ENXIO); + + if (!ofw_bus_is_compatible(dev, "brcm,ns2-pcie-phy")) + return (ENXIO); + + device_set_desc(dev, "Broadcom NS2 PCIe PHY"); + return (BUS_PROBE_SPECIFIC); +} + +static int +ns2_pcie_phy_fdt_attach(device_t dev) +{ + struct ns2_pcie_phy_softc *sc; + pcell_t addr_cells, size_cells, buf[2]; + phandle_t node; + + sc = device_get_softc(dev); + + node = ofw_bus_get_node(dev); + get_addr_size_cells(OF_parent(node), &addr_cells, &size_cells); + if ((addr_cells != 1) || (size_cells != 0)) { + device_printf(dev, + "Only addr_cells=1 and size_cells=0 are supported\n"); + return (EINVAL); + } + + if (OF_getencprop(node, "reg", buf, sizeof(pcell_t)) < 0) + return (ENXIO); + + sc->phy_id = buf[0]; + + if (ns2_pci_phy_init(dev) < 0) + return (EINVAL); + + return (bus_generic_attach(dev)); +} Property changes on: head/sys/arm64/broadcom/brcmmdio/mdio_ns2_pcie_phy.c ___________________________________________________________________ Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:keywords ## -0,0 +1 ## +FreeBSD=%H \ No newline at end of property Added: svn:mime-type ## -0,0 +1 ## +text/plain \ No newline at end of property Index: head/sys/conf/files.arm64 =================================================================== --- head/sys/conf/files.arm64 (revision 359646) +++ head/sys/conf/files.arm64 (revision 359647) @@ -1,332 +1,335 @@ # $FreeBSD$ cloudabi32_vdso.o optional compat_cloudabi32 \ dependency "$S/contrib/cloudabi/cloudabi_vdso_armv6_on_64bit.S" \ compile-with "${CC} -x assembler-with-cpp -m32 -shared -nostdinc -nostdlib -Wl,-T$S/compat/cloudabi/cloudabi_vdso.lds $S/contrib/cloudabi/cloudabi_vdso_armv6_on_64bit.S -o ${.TARGET}" \ no-obj no-implicit-rule \ clean "cloudabi32_vdso.o" # cloudabi32_vdso_blob.o optional compat_cloudabi32 \ dependency "cloudabi32_vdso.o" \ compile-with "${OBJCOPY} --input-target binary --output-target elf64-littleaarch64 --binary-architecture aarch64 cloudabi32_vdso.o ${.TARGET}" \ no-implicit-rule \ clean "cloudabi32_vdso_blob.o" # cloudabi64_vdso.o optional compat_cloudabi64 \ dependency "$S/contrib/cloudabi/cloudabi_vdso_aarch64.S" \ compile-with "${CC} -x assembler-with-cpp -shared -nostdinc -nostdlib -Wl,-T$S/compat/cloudabi/cloudabi_vdso.lds $S/contrib/cloudabi/cloudabi_vdso_aarch64.S -o ${.TARGET}" \ no-obj no-implicit-rule \ clean "cloudabi64_vdso.o" # cloudabi64_vdso_blob.o optional compat_cloudabi64 \ dependency "cloudabi64_vdso.o" \ compile-with "${OBJCOPY} --input-target binary --output-target elf64-littleaarch64 --binary-architecture aarch64 cloudabi64_vdso.o ${.TARGET}" \ no-implicit-rule \ clean "cloudabi64_vdso_blob.o" # # Allwinner common files arm/allwinner/a10_timer.c optional a10_timer fdt arm/allwinner/a10_codec.c optional sound a10_codec arm/allwinner/a31_dmac.c optional a31_dmac arm/allwinner/sunxi_dma_if.m optional a31_dmac arm/allwinner/aw_cir.c optional evdev aw_cir fdt arm/allwinner/aw_dwc3.c optional aw_dwc3 fdt arm/allwinner/aw_gpio.c optional gpio aw_gpio fdt arm/allwinner/aw_mmc.c optional mmc aw_mmc fdt | mmccam aw_mmc fdt arm/allwinner/aw_nmi.c optional aw_nmi fdt \ compile-with "${NORMAL_C} -I$S/gnu/dts/include" arm/allwinner/aw_pwm.c optional aw_pwm fdt arm/allwinner/aw_rsb.c optional aw_rsb fdt arm/allwinner/aw_rtc.c optional aw_rtc fdt arm/allwinner/aw_sid.c optional aw_sid nvmem fdt arm/allwinner/aw_spi.c optional aw_spi fdt arm/allwinner/aw_syscon.c optional aw_syscon ext_resources syscon fdt arm/allwinner/aw_thermal.c optional aw_thermal nvmem fdt arm/allwinner/aw_usbphy.c optional ehci aw_usbphy fdt arm/allwinner/aw_usb3phy.c optional xhci aw_usbphy fdt arm/allwinner/aw_wdog.c optional aw_wdog fdt arm/allwinner/axp81x.c optional axp81x fdt arm/allwinner/if_awg.c optional awg ext_resources syscon aw_sid nvmem fdt # Allwinner clock driver arm/allwinner/clkng/aw_ccung.c optional aw_ccu fdt arm/allwinner/clkng/aw_clk_frac.c optional aw_ccu fdt arm/allwinner/clkng/aw_clk_m.c optional aw_ccu fdt arm/allwinner/clkng/aw_clk_mipi.c optional aw_ccu fdt arm/allwinner/clkng/aw_clk_nkmp.c optional aw_ccu fdt arm/allwinner/clkng/aw_clk_nm.c optional aw_ccu fdt arm/allwinner/clkng/aw_clk_nmm.c optional aw_ccu fdt arm/allwinner/clkng/aw_clk_np.c optional aw_ccu fdt arm/allwinner/clkng/aw_clk_prediv_mux.c optional aw_ccu fdt arm/allwinner/clkng/ccu_a64.c optional soc_allwinner_a64 aw_ccu fdt arm/allwinner/clkng/ccu_h3.c optional soc_allwinner_h5 aw_ccu fdt arm/allwinner/clkng/ccu_h6.c optional soc_allwinner_h6 aw_ccu fdt arm/allwinner/clkng/ccu_h6_r.c optional soc_allwinner_h6 aw_ccu fdt arm/allwinner/clkng/ccu_sun8i_r.c optional aw_ccu fdt arm/allwinner/clkng/ccu_de2.c optional aw_ccu fdt # Allwinner padconf files arm/allwinner/a64/a64_padconf.c optional soc_allwinner_a64 fdt arm/allwinner/a64/a64_r_padconf.c optional soc_allwinner_a64 fdt arm/allwinner/h3/h3_padconf.c optional soc_allwinner_h5 fdt arm/allwinner/h3/h3_r_padconf.c optional soc_allwinner_h5 fdt arm/allwinner/h6/h6_padconf.c optional soc_allwinner_h6 fdt arm/allwinner/h6/h6_r_padconf.c optional soc_allwinner_h6 fdt arm/annapurna/alpine/alpine_ccu.c optional al_ccu fdt arm/annapurna/alpine/alpine_nb_service.c optional al_nb_service fdt arm/annapurna/alpine/alpine_pci.c optional al_pci fdt arm/annapurna/alpine/alpine_pci_msix.c optional al_pci fdt arm/annapurna/alpine/alpine_serdes.c optional al_serdes fdt \ no-depend \ compile-with "${CC} -c -o ${.TARGET} ${CFLAGS} -I$S/contrib/alpine-hal -I$S/contrib/alpine-hal/eth ${PROF} ${.IMPSRC}" arm/arm/generic_timer.c standard arm/arm/gic.c standard arm/arm/gic_acpi.c optional acpi arm/arm/gic_fdt.c optional fdt arm/arm/pmu.c standard arm/arm/physmem.c standard arm/broadcom/bcm2835/bcm2835_audio.c optional sound vchiq fdt \ compile-with "${NORMAL_C} -DUSE_VCHIQ_ARM -D__VCCOREVER__=0x04000000 -I$S/contrib/vchiq" arm/broadcom/bcm2835/bcm2835_bsc.c optional bcm2835_bsc fdt arm/broadcom/bcm2835/bcm2835_clkman.c optional soc_brcm_bcm2837 fdt | soc_brcm_bcm2838 fdt arm/broadcom/bcm2835/bcm2835_cpufreq.c optional soc_brcm_bcm2837 fdt | soc_brcm_bcm2838 fdt arm/broadcom/bcm2835/bcm2835_dma.c optional soc_brcm_bcm2837 fdt | soc_brcm_bcm2838 fdt arm/broadcom/bcm2835/bcm2835_fbd.c optional vt soc_brcm_bcm2837 fdt | vt soc_brcm_bcm2838 fdt arm/broadcom/bcm2835/bcm2835_ft5406.c optional evdev bcm2835_ft5406 fdt arm/broadcom/bcm2835/bcm2835_gpio.c optional gpio soc_brcm_bcm2837 fdt | gpio soc_brcm_bcm2838 fdt arm/broadcom/bcm2835/bcm2835_intr.c optional soc_brcm_bcm2837 fdt | soc_brcm_bcm2838 fdt arm/broadcom/bcm2835/bcm2835_mbox.c optional soc_brcm_bcm2837 fdt | soc_brcm_bcm2838 fdt arm/broadcom/bcm2835/bcm2835_rng.c optional !random_loadable soc_brcm_bcm2837 fdt | !random_loadable soc_brcm_bcm2838 fdt arm/broadcom/bcm2835/bcm2835_sdhci.c optional sdhci soc_brcm_bcm2837 fdt | sdhci soc_brcm_bcm2838 fdt arm/broadcom/bcm2835/bcm2835_sdhost.c optional sdhci soc_brcm_bcm2837 fdt | sdhci soc_brcm_bcm2838 fdt arm/broadcom/bcm2835/bcm2835_spi.c optional bcm2835_spi fdt arm/broadcom/bcm2835/bcm2835_vcbus.c optional soc_brcm_bcm2837 fdt | soc_brcm_bcm2838 fdt arm/broadcom/bcm2835/bcm2835_vcio.c optional soc_brcm_bcm2837 fdt | soc_brcm_bcm2838 fdt arm/broadcom/bcm2835/bcm2835_wdog.c optional soc_brcm_bcm2837 fdt | soc_brcm_bcm2838 fdt arm/broadcom/bcm2835/bcm2836.c optional soc_brcm_bcm2837 fdt | soc_brcm_bcm2838 fdt arm/broadcom/bcm2835/bcm283x_dwc_fdt.c optional dwcotg fdt soc_brcm_bcm2837 | dwcotg fdt soc_brcm_bcm2838 arm/mv/a37x0_gpio.c optional a37x0_gpio gpio fdt arm/mv/a37x0_iic.c optional a37x0_iic iicbus fdt arm/mv/a37x0_spi.c optional a37x0_spi spibus fdt arm/mv/armada38x/armada38x_rtc.c optional mv_rtc fdt arm/mv/gpio.c optional mv_gpio fdt arm/mv/mvebu_pinctrl.c optional mvebu_pinctrl fdt arm/mv/mv_ap806_clock.c optional SOC_MARVELL_8K fdt arm/mv/mv_ap806_gicp.c optional mv_ap806_gicp fdt arm/mv/mv_ap806_sei.c optional mv_ap806_sei fdt arm/mv/mv_cp110_clock.c optional SOC_MARVELL_8K fdt arm/mv/mv_cp110_icu.c optional mv_cp110_icu fdt arm/mv/mv_cp110_icu_bus.c optional mv_cp110_icu fdt arm/mv/mv_thermal.c optional SOC_MARVELL_8K mv_thermal fdt arm/mv/armada38x/armada38x_rtc.c optional mv_rtc fdt arm/xilinx/uart_dev_cdnc.c optional uart soc_xilinx_zynq arm64/acpica/acpi_iort.c optional acpi arm64/acpica/acpi_machdep.c optional acpi arm64/acpica/OsdEnvironment.c optional acpi arm64/acpica/acpi_wakeup.c optional acpi arm64/acpica/pci_cfgreg.c optional acpi pci arm64/arm64/autoconf.c standard arm64/arm64/bus_machdep.c standard arm64/arm64/bus_space_asm.S standard arm64/arm64/busdma_bounce.c standard arm64/arm64/busdma_machdep.c standard arm64/arm64/bzero.S standard arm64/arm64/clock.c standard arm64/arm64/copyinout.S standard arm64/arm64/copystr.c standard arm64/arm64/cpu_errata.c standard arm64/arm64/cpufunc_asm.S standard arm64/arm64/db_disasm.c optional ddb arm64/arm64/db_interface.c optional ddb arm64/arm64/db_trace.c optional ddb arm64/arm64/debug_monitor.c standard arm64/arm64/disassem.c optional ddb arm64/arm64/dump_machdep.c standard arm64/arm64/efirt_machdep.c optional efirt arm64/arm64/elf32_machdep.c optional compat_freebsd32 arm64/arm64/elf_machdep.c standard arm64/arm64/exception.S standard arm64/arm64/freebsd32_machdep.c optional compat_freebsd32 arm64/arm64/gicv3_its.c optional intrng fdt arm64/arm64/gic_v3.c standard arm64/arm64/gic_v3_acpi.c optional acpi arm64/arm64/gic_v3_fdt.c optional fdt arm64/arm64/identcpu.c standard arm64/arm64/in_cksum.c optional inet | inet6 arm64/arm64/locore.S standard no-obj arm64/arm64/machdep.c standard arm64/arm64/machdep_boot.c standard arm64/arm64/mem.c standard arm64/arm64/memcpy.S standard arm64/arm64/memmove.S standard arm64/arm64/minidump_machdep.c standard arm64/arm64/mp_machdep.c optional smp arm64/arm64/nexus.c standard arm64/arm64/ofw_machdep.c optional fdt arm64/arm64/pmap.c standard arm64/arm64/stack_machdep.c optional ddb | stack arm64/arm64/support.S standard arm64/arm64/swtch.S standard arm64/arm64/sys_machdep.c standard arm64/arm64/trap.c standard arm64/arm64/uio_machdep.c standard arm64/arm64/uma_machdep.c standard arm64/arm64/undefined.c standard arm64/arm64/unwind.c optional ddb | kdtrace_hooks | stack arm64/arm64/vfp.c standard arm64/arm64/vm_machdep.c standard +arm64/broadcom/brcmmdio/mdio_mux_iproc.c optional fdt +arm64/broadcom/brcmmdio/mdio_nexus_iproc.c optional fdt +arm64/broadcom/brcmmdio/mdio_ns2_pcie_phy.c optional fdt pci arm64/cavium/thunder_pcie_fdt.c optional soc_cavm_thunderx pci fdt arm64/cavium/thunder_pcie_pem.c optional soc_cavm_thunderx pci arm64/cavium/thunder_pcie_pem_fdt.c optional soc_cavm_thunderx pci fdt arm64/cavium/thunder_pcie_common.c optional soc_cavm_thunderx pci arm64/cloudabi32/cloudabi32_sysvec.c optional compat_cloudabi32 arm64/cloudabi64/cloudabi64_sysvec.c optional compat_cloudabi64 arm64/coresight/coresight.c standard arm64/coresight/coresight_if.m standard arm64/coresight/coresight-cmd.c standard arm64/coresight/coresight-cpu-debug.c standard arm64/coresight/coresight-dynamic-replicator.c standard arm64/coresight/coresight-etm4x.c standard arm64/coresight/coresight-funnel.c standard arm64/coresight/coresight-tmc.c standard arm64/intel/firmware.c optional soc_intel_stratix10 arm64/intel/stratix10-soc-fpga-mgr.c optional soc_intel_stratix10 arm64/intel/stratix10-svc.c optional soc_intel_stratix10 arm64/qualcomm/qcom_gcc.c optional qcom_gcc fdt contrib/vchiq/interface/compat/vchi_bsd.c optional vchiq soc_brcm_bcm2837 \ compile-with "${NORMAL_C} -DUSE_VCHIQ_ARM -D__VCCOREVER__=0x04000000 -I$S/contrib/vchiq" contrib/vchiq/interface/vchiq_arm/vchiq_2835_arm.c optional vchiq soc_brcm_bcm2837 \ compile-with "${NORMAL_C} -Wno-unused -DUSE_VCHIQ_ARM -D__VCCOREVER__=0x04000000 -I$S/contrib/vchiq" contrib/vchiq/interface/vchiq_arm/vchiq_arm.c optional vchiq soc_brcm_bcm2837 \ compile-with "${NORMAL_C} -Wno-unused -DUSE_VCHIQ_ARM -D__VCCOREVER__=0x04000000 -I$S/contrib/vchiq" contrib/vchiq/interface/vchiq_arm/vchiq_connected.c optional vchiq soc_brcm_bcm2837 \ compile-with "${NORMAL_C} -DUSE_VCHIQ_ARM -D__VCCOREVER__=0x04000000 -I$S/contrib/vchiq" contrib/vchiq/interface/vchiq_arm/vchiq_core.c optional vchiq soc_brcm_bcm2837 \ compile-with "${NORMAL_C} -DUSE_VCHIQ_ARM -D__VCCOREVER__=0x04000000 -I$S/contrib/vchiq" contrib/vchiq/interface/vchiq_arm/vchiq_kern_lib.c optional vchiq soc_brcm_bcm2837 \ compile-with "${NORMAL_C} -DUSE_VCHIQ_ARM -D__VCCOREVER__=0x04000000 -I$S/contrib/vchiq" contrib/vchiq/interface/vchiq_arm/vchiq_kmod.c optional vchiq soc_brcm_bcm2837 \ compile-with "${NORMAL_C} -DUSE_VCHIQ_ARM -D__VCCOREVER__=0x04000000 -I$S/contrib/vchiq" contrib/vchiq/interface/vchiq_arm/vchiq_shim.c optional vchiq soc_brcm_bcm2837 \ compile-with "${NORMAL_C} -DUSE_VCHIQ_ARM -D__VCCOREVER__=0x04000000 -I$S/contrib/vchiq" contrib/vchiq/interface/vchiq_arm/vchiq_util.c optional vchiq soc_brcm_bcm2837 \ compile-with "${NORMAL_C} -DUSE_VCHIQ_ARM -D__VCCOREVER__=0x04000000 -I$S/contrib/vchiq" crypto/armv8/armv8_crypto.c optional armv8crypto armv8_crypto_wrap.o optional armv8crypto \ dependency "$S/crypto/armv8/armv8_crypto_wrap.c" \ compile-with "${CC} -c ${CFLAGS:C/^-O2$/-O3/:N-nostdinc:N-mgeneral-regs-only} -I$S/crypto/armv8/ ${WERROR} ${NO_WCAST_QUAL} ${PROF} -march=armv8-a+crypto ${.IMPSRC}" \ no-implicit-rule \ clean "armv8_crypto_wrap.o" crypto/blowfish/bf_enc.c optional crypto | ipsec | ipsec_support crypto/des/des_enc.c optional crypto | ipsec | ipsec_support | netsmb dev/acpica/acpi_bus_if.m optional acpi dev/acpica/acpi_if.m optional acpi dev/acpica/acpi_pci_link.c optional acpi pci dev/acpica/acpi_pcib.c optional acpi pci dev/acpica/acpi_pxm.c optional acpi dev/ahci/ahci_generic.c optional ahci dev/altera/dwc/if_dwc_socfpga.c optional fdt dwc_socfpga dev/axgbe/if_axgbe.c optional axgbe dev/axgbe/xgbe-desc.c optional axgbe dev/axgbe/xgbe-dev.c optional axgbe dev/axgbe/xgbe-drv.c optional axgbe dev/axgbe/xgbe-mdio.c optional axgbe dev/cpufreq/cpufreq_dt.c optional cpufreq fdt dev/iicbus/sy8106a.c optional sy8106a fdt dev/iicbus/twsi/mv_twsi.c optional twsi fdt dev/iicbus/twsi/a10_twsi.c optional twsi fdt dev/iicbus/twsi/twsi.c optional twsi fdt dev/hwpmc/hwpmc_arm64.c optional hwpmc dev/hwpmc/hwpmc_arm64_md.c optional hwpmc dev/mbox/mbox_if.m optional soc_brcm_bcm2837 dev/mmc/host/dwmmc.c optional dwmmc fdt dev/mmc/host/dwmmc_altera.c optional dwmmc dwmmc_altera fdt dev/mmc/host/dwmmc_hisi.c optional dwmmc dwmmc_hisi fdt dev/mmc/host/dwmmc_rockchip.c optional dwmmc rk_dwmmc fdt dev/neta/if_mvneta_fdt.c optional neta fdt dev/neta/if_mvneta.c optional neta mdio mii dev/ofw/ofw_cpu.c optional fdt dev/ofw/ofwpci.c optional fdt pci dev/pci/controller/pci_n1sdp.c optional pci_n1sdp acpi dev/pci/pci_host_generic.c optional pci dev/pci/pci_host_generic_acpi.c optional pci acpi dev/pci/pci_host_generic_fdt.c optional pci fdt dev/pci/pci_dw_mv.c optional pci fdt dev/pci/pci_dw.c optional pci fdt dev/pci/pci_dw_if.m optional pci fdt dev/psci/psci.c standard dev/psci/smccc_arm64.S standard dev/psci/smccc.c standard dev/sdhci/sdhci_xenon.c optional sdhci_xenon sdhci fdt dev/uart/uart_cpu_arm64.c optional uart dev/uart/uart_dev_mu.c optional uart uart_mu dev/uart/uart_dev_pl011.c optional uart pl011 dev/usb/controller/dwc_otg_hisi.c optional dwcotg fdt soc_hisi_hi6220 dev/usb/controller/dwc3.c optional fdt dwc3 dev/usb/controller/ehci_mv.c optional ehci_mv fdt dev/usb/controller/generic_ehci.c optional ehci dev/usb/controller/generic_ehci_acpi.c optional ehci acpi dev/usb/controller/generic_ehci_fdt.c optional ehci fdt dev/usb/controller/generic_ohci.c optional ohci fdt dev/usb/controller/generic_usb_if.m optional ohci fdt dev/usb/controller/usb_nop_xceiv.c optional fdt ext_resources dev/usb/controller/generic_xhci.c optional xhci dev/usb/controller/generic_xhci_acpi.c optional xhci acpi dev/usb/controller/generic_xhci_fdt.c optional xhci fdt dev/vnic/mrml_bridge.c optional vnic fdt dev/vnic/nic_main.c optional vnic pci dev/vnic/nicvf_main.c optional vnic pci pci_iov dev/vnic/nicvf_queues.c optional vnic pci pci_iov dev/vnic/thunder_bgx_fdt.c optional vnic fdt dev/vnic/thunder_bgx.c optional vnic pci dev/vnic/thunder_mdio_fdt.c optional vnic fdt dev/vnic/thunder_mdio.c optional vnic dev/vnic/lmac_if.m optional inet | inet6 | vnic kern/kern_clocksource.c standard kern/msi_if.m optional intrng kern/pic_if.m optional intrng kern/subr_devmap.c standard kern/subr_intr.c optional intrng libkern/bcmp.c standard libkern/memcmp.c standard \ compile-with "${NORMAL_C:N-fsanitize*}" libkern/memset.c standard \ compile-with "${NORMAL_C:N-fsanitize*}" libkern/arm64/crc32c_armv8.S standard cddl/dev/dtrace/aarch64/dtrace_asm.S optional dtrace compile-with "${DTRACE_S}" cddl/dev/dtrace/aarch64/dtrace_subr.c optional dtrace compile-with "${DTRACE_C}" cddl/dev/fbt/aarch64/fbt_isa.c optional dtrace_fbt | dtraceall compile-with "${FBT_C}" # RockChip Drivers arm64/rockchip/rk3399_emmcphy.c optional fdt rk_emmcphy soc_rockchip_rk3399 arm64/rockchip/rk_dwc3.c optional fdt rk_dwc3 soc_rockchip_rk3399 arm64/rockchip/rk_i2c.c optional fdt rk_i2c soc_rockchip_rk3328 | fdt rk_i2c soc_rockchip_rk3399 arm64/rockchip/rk805.c optional fdt rk805 soc_rockchip_rk3328 | fdt rk805 soc_rockchip_rk3399 arm64/rockchip/rk_grf.c optional fdt soc_rockchip_rk3328 | fdt soc_rockchip_rk3399 arm64/rockchip/rk_pinctrl.c optional fdt rk_pinctrl soc_rockchip_rk3328 | fdt rk_pinctrl soc_rockchip_rk3399 arm64/rockchip/rk_gpio.c optional fdt rk_gpio soc_rockchip_rk3328 | fdt rk_gpio soc_rockchip_rk3399 arm64/rockchip/rk_iodomain.c optional fdt rk_iodomain arm64/rockchip/rk_spi.c optional fdt rk_spi arm64/rockchip/rk_usb2phy.c optional fdt rk_usb2phy soc_rockchip_rk3328 | soc_rockchip_rk3399 arm64/rockchip/rk_typec_phy.c optional fdt rk_typec_phy soc_rockchip_rk3399 arm64/rockchip/if_dwc_rk.c optional fdt dwc_rk soc_rockchip_rk3328 | fdt dwc_rk soc_rockchip_rk3399 arm64/rockchip/rk_tsadc_if.m optional fdt soc_rockchip_rk3399 arm64/rockchip/rk_tsadc.c optional fdt soc_rockchip_rk3399 arm64/rockchip/rk_pwm.c optional fdt rk_pwm arm64/rockchip/rk_pcie.c optional fdt pci soc_rockchip_rk3399 arm64/rockchip/rk_pcie_phy.c optional fdt pci soc_rockchip_rk3399 dev/dwc/if_dwc.c optional fdt dwc_rk soc_rockchip_rk3328 | fdt dwc_rk soc_rockchip_rk3399 dev/dwc/if_dwc_if.m optional fdt dwc_rk soc_rockchip_rk3328 | fdt dwc_rk soc_rockchip_rk3399 # RockChip Clock support arm64/rockchip/clk/rk_cru.c optional fdt soc_rockchip_rk3328 | fdt soc_rockchip_rk3399 arm64/rockchip/clk/rk_clk_armclk.c optional fdt soc_rockchip_rk3328 | fdt soc_rockchip_rk3399 arm64/rockchip/clk/rk_clk_composite.c optional fdt soc_rockchip_rk3328 | fdt soc_rockchip_rk3399 arm64/rockchip/clk/rk_clk_fract.c optional fdt soc_rockchip_rk3328 | fdt soc_rockchip_rk3399 arm64/rockchip/clk/rk_clk_gate.c optional fdt soc_rockchip_rk3328 | fdt soc_rockchip_rk3399 arm64/rockchip/clk/rk_clk_mux.c optional fdt soc_rockchip_rk3328 | fdt soc_rockchip_rk3399 arm64/rockchip/clk/rk_clk_pll.c optional fdt soc_rockchip_rk3328 | fdt soc_rockchip_rk3399 arm64/rockchip/clk/rk3328_cru.c optional fdt soc_rockchip_rk3328 arm64/rockchip/clk/rk3399_cru.c optional fdt soc_rockchip_rk3399 arm64/rockchip/clk/rk3399_pmucru.c optional fdt soc_rockchip_rk3399 Index: head/sys/dev/mdio/mdio_if.m =================================================================== --- head/sys/dev/mdio/mdio_if.m (revision 359646) +++ head/sys/dev/mdio/mdio_if.m (revision 359647) @@ -1,91 +1,123 @@ # $FreeBSD$ #include INTERFACE mdio; CODE { #include static int mdio_null_readextreg(device_t dev, int phy, int devad, int reg) { if (devad == MDIO_DEVADDR_NONE) return (MDIO_READREG(dev, phy, reg)); return (~0U); } static int mdio_null_writeextreg(device_t dev, int phy, int devad, int reg, int val) { if (devad == MDIO_DEVADDR_NONE) return (MDIO_WRITEREG(dev, phy, reg, val)); return (EINVAL); } } /** * @brief Read register from device on MDIO bus. * * @param dev MDIO bus device. * @param phy PHY address. * @param reg The PHY register offset. */ METHOD int readreg { device_t dev; int phy; int reg; }; /** + * @brief Read register from device on MDIO muxed bus. + * + * @param dev MDIO bus device. + * @param bus MDIO bus mux position + * @param phy PHY address. + * @param reg The PHY register offset. + */ +METHOD int readreg_mux { + device_t dev; + int bus; + int phy; + int reg; +}; + +/** * @brief Write register to device on MDIO bus. * * @param dev MDIO bus device. * @param phy PHY address. * @param reg The PHY register offset. * @param val The value to write at offset @p reg. */ METHOD int writereg { device_t dev; + int phy; + int reg; + int val; +}; + +/** + * @brief Write register to device on MDIO muxed bus. + * + * @param dev MDIO bus device. + * @param bus MDIO bus mux position + * @param phy PHY address. + * @param reg The PHY register offset. + * @param val The value to write at offset @p reg. + */ +METHOD int writereg_mux { + device_t dev; + int bus; int phy; int reg; int val; }; /** * @brief Read extended register from device on MDIO bus. * * @param dev MDIO bus device. * @param phy PHY address. * @param devad The MDIO IEEE 802.3 Clause 45 device address, or * MDIO_DEVADDR_NONE to request Clause 22 register addressing. * @param reg The PHY register offset. */ METHOD int readextreg { device_t dev; int phy; int devad; int reg; } DEFAULT mdio_null_readextreg; /** * @brief Write extended register to device on MDIO bus. * * @param dev MDIO bus device. * @param phy PHY address. * @param devad The MDIO IEEE 802.3 Clause 45 device address, or * MDIO_DEVADDR_NONE to request Clause 22 register addressing. * @param reg The PHY register offset. * @param val The value to write at offset @p reg. */ METHOD int writeextreg { device_t dev; int phy; int devad; int reg; int val; } DEFAULT mdio_null_writeextreg;