Index: stable/11/sys/dev/ismt/ismt.c =================================================================== --- stable/11/sys/dev/ismt/ismt.c (revision 359359) +++ stable/11/sys/dev/ismt/ismt.c (revision 359360) @@ -1,782 +1,782 @@ /*- * Copyright (C) 2014 Intel Corporation * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * 3. Neither the name of Intel Corporation nor the names of its * contributors may be used to endorse or promote products derived from * this software without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. */ #include __FBSDID("$FreeBSD$"); #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include "smbus_if.h" #define ISMT_DESC_ENTRIES 32 /* Hardware Descriptor Constants - Control Field */ #define ISMT_DESC_CWRL 0x01 /* Command/Write Length */ #define ISMT_DESC_BLK 0X04 /* Perform Block Transaction */ #define ISMT_DESC_FAIR 0x08 /* Set fairness flag upon successful arbit. */ #define ISMT_DESC_PEC 0x10 /* Packet Error Code */ #define ISMT_DESC_I2C 0x20 /* I2C Enable */ #define ISMT_DESC_INT 0x40 /* Interrupt */ #define ISMT_DESC_SOE 0x80 /* Stop On Error */ /* Hardware Descriptor Constants - Status Field */ #define ISMT_DESC_SCS 0x01 /* Success */ #define ISMT_DESC_DLTO 0x04 /* Data Low Time Out */ #define ISMT_DESC_NAK 0x08 /* NAK Received */ #define ISMT_DESC_CRC 0x10 /* CRC Error */ #define ISMT_DESC_CLTO 0x20 /* Clock Low Time Out */ #define ISMT_DESC_COL 0x40 /* Collisions */ #define ISMT_DESC_LPR 0x80 /* Large Packet Received */ /* Macros */ -#define ISMT_DESC_ADDR_RW(addr, is_read) ((addr << 1) | (is_read)) +#define ISMT_DESC_ADDR_RW(addr, is_read) ((addr) | (is_read)) /* iSMT General Register address offsets (SMBBAR + ) */ #define ISMT_GR_GCTRL 0x000 /* General Control */ #define ISMT_GR_SMTICL 0x008 /* SMT Interrupt Cause Location */ #define ISMT_GR_ERRINTMSK 0x010 /* Error Interrupt Mask */ #define ISMT_GR_ERRAERMSK 0x014 /* Error AER Mask */ #define ISMT_GR_ERRSTS 0x018 /* Error Status */ #define ISMT_GR_ERRINFO 0x01c /* Error Information */ /* iSMT Master Registers */ #define ISMT_MSTR_MDBA 0x100 /* Master Descriptor Base Address */ #define ISMT_MSTR_MCTRL 0x108 /* Master Control */ #define ISMT_MSTR_MSTS 0x10c /* Master Status */ #define ISMT_MSTR_MDS 0x110 /* Master Descriptor Size */ #define ISMT_MSTR_RPOLICY 0x114 /* Retry Policy */ /* iSMT Miscellaneous Registers */ #define ISMT_SPGT 0x300 /* SMBus PHY Global Timing */ /* General Control Register (GCTRL) bit definitions */ #define ISMT_GCTRL_TRST 0x04 /* Target Reset */ #define ISMT_GCTRL_KILL 0x08 /* Kill */ #define ISMT_GCTRL_SRST 0x40 /* Soft Reset */ /* Master Control Register (MCTRL) bit definitions */ #define ISMT_MCTRL_SS 0x01 /* Start/Stop */ #define ISMT_MCTRL_MEIE 0x10 /* Master Error Interrupt Enable */ #define ISMT_MCTRL_FMHP 0x00ff0000 /* Firmware Master Head Ptr (FMHP) */ /* Master Status Register (MSTS) bit definitions */ #define ISMT_MSTS_HMTP 0xff0000 /* HW Master Tail Pointer (HMTP) */ #define ISMT_MSTS_MIS 0x20 /* Master Interrupt Status (MIS) */ #define ISMT_MSTS_MEIS 0x10 /* Master Error Int Status (MEIS) */ #define ISMT_MSTS_IP 0x01 /* In Progress */ /* Master Descriptor Size (MDS) bit definitions */ #define ISMT_MDS_MASK 0xff /* Master Descriptor Size mask (MDS) */ /* SMBus PHY Global Timing Register (SPGT) bit definitions */ #define ISMT_SPGT_SPD_MASK 0xc0000000 /* SMBus Speed mask */ #define ISMT_SPGT_SPD_80K 0x00 /* 80 kHz */ #define ISMT_SPGT_SPD_100K (0x1 << 30) /* 100 kHz */ #define ISMT_SPGT_SPD_400K (0x2 << 30) /* 400 kHz */ #define ISMT_SPGT_SPD_1M (0x3 << 30) /* 1 MHz */ /* MSI Control Register (MSICTL) bit definitions */ #define ISMT_MSICTL_MSIE 0x01 /* MSI Enable */ #define ISMT_MAX_BLOCK_SIZE 32 /* per SMBus spec */ //#define ISMT_DEBUG device_printf #ifndef ISMT_DEBUG #define ISMT_DEBUG(...) #endif /* iSMT Hardware Descriptor */ struct ismt_desc { uint8_t tgtaddr_rw; /* target address & r/w bit */ uint8_t wr_len_cmd; /* write length in bytes or a command */ uint8_t rd_len; /* read length */ uint8_t control; /* control bits */ uint8_t status; /* status bits */ uint8_t retry; /* collision retry and retry count */ uint8_t rxbytes; /* received bytes */ uint8_t txbytes; /* transmitted bytes */ uint32_t dptr_low; /* lower 32 bit of the data pointer */ uint32_t dptr_high; /* upper 32 bit of the data pointer */ } __packed; #define DESC_SIZE (ISMT_DESC_ENTRIES * sizeof(struct ismt_desc)) #define DMA_BUFFER_SIZE 64 struct ismt_softc { device_t pcidev; device_t smbdev; struct thread *bus_reserved; int intr_rid; struct resource *intr_res; void *intr_handle; bus_space_tag_t mmio_tag; bus_space_handle_t mmio_handle; int mmio_rid; struct resource *mmio_res; uint8_t head; struct ismt_desc *desc; bus_dma_tag_t desc_dma_tag; bus_dmamap_t desc_dma_map; uint64_t desc_bus_addr; uint8_t *dma_buffer; bus_dma_tag_t dma_buffer_dma_tag; bus_dmamap_t dma_buffer_dma_map; uint64_t dma_buffer_bus_addr; uint8_t using_msi; }; static void ismt_intr(void *arg) { struct ismt_softc *sc = arg; uint32_t val; val = bus_read_4(sc->mmio_res, ISMT_MSTR_MSTS); ISMT_DEBUG(sc->pcidev, "%s MSTS=0x%x\n", __func__, val); val |= (ISMT_MSTS_MIS | ISMT_MSTS_MEIS); bus_write_4(sc->mmio_res, ISMT_MSTR_MSTS, val); wakeup(sc); } static int ismt_callback(device_t dev, int index, void *data) { struct ismt_softc *sc; int acquired, err; sc = device_get_softc(dev); switch (index) { case SMB_REQUEST_BUS: acquired = atomic_cmpset_ptr( (uintptr_t *)&sc->bus_reserved, (uintptr_t)NULL, (uintptr_t)curthread); ISMT_DEBUG(dev, "SMB_REQUEST_BUS acquired=%d\n", acquired); if (acquired) err = 0; else err = EWOULDBLOCK; break; case SMB_RELEASE_BUS: KASSERT(sc->bus_reserved == curthread, ("SMB_RELEASE_BUS called by wrong thread\n")); ISMT_DEBUG(dev, "SMB_RELEASE_BUS\n"); atomic_store_rel_ptr((uintptr_t *)&sc->bus_reserved, (uintptr_t)NULL); err = 0; break; default: err = SMB_EABORT; break; } return (err); } static struct ismt_desc * ismt_alloc_desc(struct ismt_softc *sc) { struct ismt_desc *desc; KASSERT(sc->bus_reserved == curthread, ("curthread %p did not request bus (%p has reserved)\n", curthread, sc->bus_reserved)); desc = &sc->desc[sc->head++]; if (sc->head == ISMT_DESC_ENTRIES) sc->head = 0; memset(desc, 0, sizeof(*desc)); return (desc); } static int ismt_submit(struct ismt_softc *sc, struct ismt_desc *desc, uint8_t slave, uint8_t is_read) { uint32_t err, fmhp, val; desc->control |= ISMT_DESC_FAIR; if (sc->using_msi) desc->control |= ISMT_DESC_INT; desc->tgtaddr_rw = ISMT_DESC_ADDR_RW(slave, is_read); desc->dptr_low = (sc->dma_buffer_bus_addr & 0xFFFFFFFFLL); desc->dptr_high = (sc->dma_buffer_bus_addr >> 32); wmb(); fmhp = sc->head << 16; val = bus_read_4(sc->mmio_res, ISMT_MSTR_MCTRL); val &= ~ISMT_MCTRL_FMHP; val |= fmhp; bus_write_4(sc->mmio_res, ISMT_MSTR_MCTRL, val); /* set the start bit */ val = bus_read_4(sc->mmio_res, ISMT_MSTR_MCTRL); val |= ISMT_MCTRL_SS; bus_write_4(sc->mmio_res, ISMT_MSTR_MCTRL, val); err = tsleep(sc, PWAIT, "ismt_wait", 5 * hz); if (err != 0) { ISMT_DEBUG(sc->pcidev, "%s timeout\n", __func__); return (SMB_ETIMEOUT); } ISMT_DEBUG(sc->pcidev, "%s status=0x%x\n", __func__, desc->status); if (desc->status & ISMT_DESC_SCS) return (SMB_ENOERR); if (desc->status & ISMT_DESC_NAK) return (SMB_ENOACK); if (desc->status & ISMT_DESC_CRC) return (SMB_EBUSERR); if (desc->status & ISMT_DESC_COL) return (SMB_ECOLLI); if (desc->status & ISMT_DESC_LPR) return (SMB_EINVAL); if (desc->status & (ISMT_DESC_DLTO | ISMT_DESC_CLTO)) return (SMB_ETIMEOUT); return (SMB_EBUSERR); } static int ismt_quick(device_t dev, u_char slave, int how) { struct ismt_desc *desc; struct ismt_softc *sc; int is_read; ISMT_DEBUG(dev, "%s\n", __func__); if (how != SMB_QREAD && how != SMB_QWRITE) { return (SMB_ENOTSUPP); } sc = device_get_softc(dev); desc = ismt_alloc_desc(sc); is_read = (how == SMB_QREAD ? 1 : 0); return (ismt_submit(sc, desc, slave, is_read)); } static int ismt_sendb(device_t dev, u_char slave, char byte) { struct ismt_desc *desc; struct ismt_softc *sc; ISMT_DEBUG(dev, "%s\n", __func__); sc = device_get_softc(dev); desc = ismt_alloc_desc(sc); desc->control = ISMT_DESC_CWRL; desc->wr_len_cmd = byte; return (ismt_submit(sc, desc, slave, 0)); } static int ismt_recvb(device_t dev, u_char slave, char *byte) { struct ismt_desc *desc; struct ismt_softc *sc; int err; ISMT_DEBUG(dev, "%s\n", __func__); sc = device_get_softc(dev); desc = ismt_alloc_desc(sc); desc->rd_len = 1; err = ismt_submit(sc, desc, slave, 1); if (err != SMB_ENOERR) return (err); *byte = sc->dma_buffer[0]; return (err); } static int ismt_writeb(device_t dev, u_char slave, char cmd, char byte) { struct ismt_desc *desc; struct ismt_softc *sc; ISMT_DEBUG(dev, "%s\n", __func__); sc = device_get_softc(dev); desc = ismt_alloc_desc(sc); desc->wr_len_cmd = 2; sc->dma_buffer[0] = cmd; sc->dma_buffer[1] = byte; return (ismt_submit(sc, desc, slave, 0)); } static int ismt_writew(device_t dev, u_char slave, char cmd, short word) { struct ismt_desc *desc; struct ismt_softc *sc; ISMT_DEBUG(dev, "%s\n", __func__); sc = device_get_softc(dev); desc = ismt_alloc_desc(sc); desc->wr_len_cmd = 3; sc->dma_buffer[0] = cmd; sc->dma_buffer[1] = word & 0xFF; sc->dma_buffer[2] = word >> 8; return (ismt_submit(sc, desc, slave, 0)); } static int ismt_readb(device_t dev, u_char slave, char cmd, char *byte) { struct ismt_desc *desc; struct ismt_softc *sc; int err; ISMT_DEBUG(dev, "%s\n", __func__); sc = device_get_softc(dev); desc = ismt_alloc_desc(sc); desc->control = ISMT_DESC_CWRL; desc->wr_len_cmd = cmd; desc->rd_len = 1; err = ismt_submit(sc, desc, slave, 1); if (err != SMB_ENOERR) return (err); *byte = sc->dma_buffer[0]; return (err); } static int ismt_readw(device_t dev, u_char slave, char cmd, short *word) { struct ismt_desc *desc; struct ismt_softc *sc; int err; ISMT_DEBUG(dev, "%s\n", __func__); sc = device_get_softc(dev); desc = ismt_alloc_desc(sc); desc->control = ISMT_DESC_CWRL; desc->wr_len_cmd = cmd; desc->rd_len = 2; err = ismt_submit(sc, desc, slave, 1); if (err != SMB_ENOERR) return (err); *word = sc->dma_buffer[0] | (sc->dma_buffer[1] << 8); return (err); } static int ismt_pcall(device_t dev, u_char slave, char cmd, short sdata, short *rdata) { struct ismt_desc *desc; struct ismt_softc *sc; int err; ISMT_DEBUG(dev, "%s\n", __func__); sc = device_get_softc(dev); desc = ismt_alloc_desc(sc); desc->wr_len_cmd = 3; desc->rd_len = 2; sc->dma_buffer[0] = cmd; sc->dma_buffer[1] = sdata & 0xff; sc->dma_buffer[2] = sdata >> 8; err = ismt_submit(sc, desc, slave, 0); if (err != SMB_ENOERR) return (err); *rdata = sc->dma_buffer[0] | (sc->dma_buffer[1] << 8); return (err); } static int ismt_bwrite(device_t dev, u_char slave, char cmd, u_char count, char *buf) { struct ismt_desc *desc; struct ismt_softc *sc; ISMT_DEBUG(dev, "%s\n", __func__); if (count == 0 || count > ISMT_MAX_BLOCK_SIZE) return (SMB_EINVAL); sc = device_get_softc(dev); desc = ismt_alloc_desc(sc); desc->control = ISMT_DESC_I2C; desc->wr_len_cmd = count + 1; sc->dma_buffer[0] = cmd; memcpy(&sc->dma_buffer[1], buf, count); return (ismt_submit(sc, desc, slave, 0)); } static int ismt_bread(device_t dev, u_char slave, char cmd, u_char *count, char *buf) { struct ismt_desc *desc; struct ismt_softc *sc; int err; ISMT_DEBUG(dev, "%s\n", __func__); if (*count == 0 || *count > ISMT_MAX_BLOCK_SIZE) return (SMB_EINVAL); sc = device_get_softc(dev); desc = ismt_alloc_desc(sc); desc->control = ISMT_DESC_I2C | ISMT_DESC_CWRL; desc->wr_len_cmd = cmd; desc->rd_len = *count; err = ismt_submit(sc, desc, slave, 0); if (err != SMB_ENOERR) return (err); memcpy(buf, sc->dma_buffer, desc->rxbytes); *count = desc->rxbytes; return (err); } static int ismt_detach(device_t dev) { struct ismt_softc *sc; int error; ISMT_DEBUG(dev, "%s\n", __func__); sc = device_get_softc(dev); error = bus_generic_detach(dev); if (error) return (error); device_delete_child(dev, sc->smbdev); if (sc->intr_handle != NULL) { bus_teardown_intr(dev, sc->intr_res, sc->intr_handle); sc->intr_handle = NULL; } if (sc->intr_res != NULL) { bus_release_resource(dev, SYS_RES_IRQ, sc->intr_rid, sc->intr_res); sc->intr_res = NULL; } if (sc->using_msi == 1) pci_release_msi(dev); if (sc->mmio_res != NULL) { bus_release_resource(dev, SYS_RES_MEMORY, sc->mmio_rid, sc->mmio_res); sc->mmio_res = NULL; } bus_dmamap_unload(sc->desc_dma_tag, sc->desc_dma_map); bus_dmamap_unload(sc->dma_buffer_dma_tag, sc->dma_buffer_dma_map); bus_dmamem_free(sc->desc_dma_tag, sc->desc, sc->desc_dma_map); bus_dmamem_free(sc->dma_buffer_dma_tag, sc->dma_buffer, sc->dma_buffer_dma_map); bus_dma_tag_destroy(sc->desc_dma_tag); bus_dma_tag_destroy(sc->dma_buffer_dma_tag); pci_disable_busmaster(dev); return 0; } static void ismt_single_map(void *arg, bus_dma_segment_t *seg, int nseg, int error) { uint64_t *bus_addr = (uint64_t *)arg; KASSERT(error == 0, ("%s: error=%d\n", __func__, error)); KASSERT(nseg == 1, ("%s: nseg=%d\n", __func__, nseg)); *bus_addr = seg[0].ds_addr; } static int ismt_attach(device_t dev) { struct ismt_softc *sc = device_get_softc(dev); int err, num_vectors, val; sc->pcidev = dev; pci_enable_busmaster(dev); if ((sc->smbdev = device_add_child(dev, "smbus", -1)) == NULL) { device_printf(dev, "no smbus child found\n"); err = ENXIO; goto fail; } sc->mmio_rid = PCIR_BAR(0); sc->mmio_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &sc->mmio_rid, RF_ACTIVE); if (sc->mmio_res == NULL) { device_printf(dev, "cannot allocate mmio region\n"); err = ENOMEM; goto fail; } sc->mmio_tag = rman_get_bustag(sc->mmio_res); sc->mmio_handle = rman_get_bushandle(sc->mmio_res); /* Attach "smbus" child */ if ((err = bus_generic_attach(dev)) != 0) { device_printf(dev, "failed to attach child: %d\n", err); err = ENXIO; goto fail; } bus_dma_tag_create(bus_get_dma_tag(dev), 4, PAGE_SIZE, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, DESC_SIZE, 1, DESC_SIZE, 0, NULL, NULL, &sc->desc_dma_tag); bus_dma_tag_create(bus_get_dma_tag(dev), 4, PAGE_SIZE, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, DMA_BUFFER_SIZE, 1, DMA_BUFFER_SIZE, 0, NULL, NULL, &sc->dma_buffer_dma_tag); bus_dmamap_create(sc->desc_dma_tag, 0, &sc->desc_dma_map); bus_dmamap_create(sc->dma_buffer_dma_tag, 0, &sc->dma_buffer_dma_map); bus_dmamem_alloc(sc->desc_dma_tag, (void **)&sc->desc, BUS_DMA_WAITOK, &sc->desc_dma_map); bus_dmamem_alloc(sc->dma_buffer_dma_tag, (void **)&sc->dma_buffer, BUS_DMA_WAITOK, &sc->dma_buffer_dma_map); bus_dmamap_load(sc->desc_dma_tag, sc->desc_dma_map, sc->desc, DESC_SIZE, ismt_single_map, &sc->desc_bus_addr, 0); bus_dmamap_load(sc->dma_buffer_dma_tag, sc->dma_buffer_dma_map, sc->dma_buffer, DMA_BUFFER_SIZE, ismt_single_map, &sc->dma_buffer_bus_addr, 0); bus_write_4(sc->mmio_res, ISMT_MSTR_MDBA, (sc->desc_bus_addr & 0xFFFFFFFFLL)); bus_write_4(sc->mmio_res, ISMT_MSTR_MDBA + 4, (sc->desc_bus_addr >> 32)); /* initialize the Master Control Register (MCTRL) */ bus_write_4(sc->mmio_res, ISMT_MSTR_MCTRL, ISMT_MCTRL_MEIE); /* initialize the Master Status Register (MSTS) */ bus_write_4(sc->mmio_res, ISMT_MSTR_MSTS, 0); /* initialize the Master Descriptor Size (MDS) */ val = bus_read_4(sc->mmio_res, ISMT_MSTR_MDS); val &= ~ISMT_MDS_MASK; val |= (ISMT_DESC_ENTRIES - 1); bus_write_4(sc->mmio_res, ISMT_MSTR_MDS, val); sc->using_msi = 1; if (pci_msi_count(dev) == 0) { sc->using_msi = 0; goto intx; } num_vectors = 1; if (pci_alloc_msi(dev, &num_vectors) != 0) { sc->using_msi = 0; goto intx; } sc->intr_rid = 1; sc->intr_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &sc->intr_rid, RF_ACTIVE); if (sc->intr_res == NULL) { sc->using_msi = 0; pci_release_msi(dev); } intx: if (sc->using_msi == 0) { sc->intr_rid = 0; sc->intr_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &sc->intr_rid, RF_SHAREABLE | RF_ACTIVE); if (sc->intr_res == NULL) { device_printf(dev, "cannot allocate irq\n"); err = ENXIO; goto fail; } } ISMT_DEBUG(dev, "using_msi = %d\n", sc->using_msi); err = bus_setup_intr(dev, sc->intr_res, INTR_TYPE_MISC | INTR_MPSAFE, NULL, ismt_intr, sc, &sc->intr_handle); if (err != 0) { device_printf(dev, "cannot setup interrupt\n"); err = ENXIO; goto fail; } return (0); fail: ismt_detach(dev); return (err); } #define ID_INTEL_S1200_SMT0 0x0c598086 #define ID_INTEL_S1200_SMT1 0x0c5a8086 #define ID_INTEL_C2000_SMT 0x1f158086 #define ID_INTEL_C3000_SMT 0x19ac8086 static int ismt_probe(device_t dev) { const char *desc; switch (pci_get_devid(dev)) { case ID_INTEL_S1200_SMT0: desc = "Atom Processor S1200 SMBus 2.0 Controller 0"; break; case ID_INTEL_S1200_SMT1: desc = "Atom Processor S1200 SMBus 2.0 Controller 1"; break; case ID_INTEL_C2000_SMT: desc = "Atom Processor C2000 SMBus 2.0"; break; case ID_INTEL_C3000_SMT: desc = "Atom Processor C3000 SMBus 2.0"; break; default: return (ENXIO); } device_set_desc(dev, desc); return (BUS_PROBE_DEFAULT); } /* Device methods */ static device_method_t ismt_pci_methods[] = { DEVMETHOD(device_probe, ismt_probe), DEVMETHOD(device_attach, ismt_attach), DEVMETHOD(device_detach, ismt_detach), DEVMETHOD(smbus_callback, ismt_callback), DEVMETHOD(smbus_quick, ismt_quick), DEVMETHOD(smbus_sendb, ismt_sendb), DEVMETHOD(smbus_recvb, ismt_recvb), DEVMETHOD(smbus_writeb, ismt_writeb), DEVMETHOD(smbus_writew, ismt_writew), DEVMETHOD(smbus_readb, ismt_readb), DEVMETHOD(smbus_readw, ismt_readw), DEVMETHOD(smbus_pcall, ismt_pcall), DEVMETHOD(smbus_bwrite, ismt_bwrite), DEVMETHOD(smbus_bread, ismt_bread), DEVMETHOD_END }; static driver_t ismt_pci_driver = { "ismt", ismt_pci_methods, sizeof(struct ismt_softc) }; static devclass_t ismt_pci_devclass; DRIVER_MODULE(ismt, pci, ismt_pci_driver, ismt_pci_devclass, 0, 0); DRIVER_MODULE(smbus, ismt, smbus_driver, smbus_devclass, 0, 0); MODULE_DEPEND(ismt, pci, 1, 1, 1); MODULE_DEPEND(ismt, smbus, SMBUS_MINVER, SMBUS_PREFVER, SMBUS_MAXVER); MODULE_VERSION(ismt, 1); Index: stable/11 =================================================================== --- stable/11 (revision 359359) +++ stable/11 (revision 359360) Property changes on: stable/11 ___________________________________________________________________ Modified: svn:mergeinfo ## -0,0 +0,1 ## Merged /head:r359279 Index: stable/12/sys/dev/ichwd/ichwd.c =================================================================== --- stable/12/sys/dev/ichwd/ichwd.c (revision 359359) +++ stable/12/sys/dev/ichwd/ichwd.c (revision 359360) @@ -1,976 +1,977 @@ /*- * SPDX-License-Identifier: BSD-2-Clause-FreeBSD * * Copyright (c) 2004 Texas A&M University * All rights reserved. * * Developer: Wm. Daryl Hawkins * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. */ /* * Intel ICH Watchdog Timer (WDT) driver * * Originally developed by Wm. Daryl Hawkins of Texas A&M * Heavily modified by * * This is a tricky one. The ICH WDT can't be treated as a regular PCI * device as it's actually an integrated function of the ICH LPC interface * bridge. Detection is also awkward, because we can only infer the * presence of the watchdog timer from the fact that the machine has an * ICH chipset, or, on ACPI 2.x systems, by the presence of the 'WDDT' * ACPI table (although this driver does not support the ACPI detection * method). * * There is one slight problem on non-ACPI or ACPI 1.x systems: we have no * way of knowing if the WDT is permanently disabled (either by the BIOS * or in hardware). * * The WDT is programmed through I/O registers in the ACPI I/O space. * Intel swears it's always at offset 0x60, so we use that. * * For details about the ICH WDT, see Intel Application Note AP-725 * (document no. 292273-001). The WDT is also described in the individual * chipset datasheets, e.g. Intel82801EB ICH5 / 82801ER ICH5R Datasheet * (document no. 252516-001) sections 9.10 and 9.11. * * ICH6/7/8 support by Takeharu KATO * SoC PMC support by Denir Li */ #include __FBSDID("$FreeBSD$"); #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include static struct ichwd_device ichwd_devices[] = { { DEVICEID_82801AA, "Intel 82801AA watchdog timer", 1, 1 }, { DEVICEID_82801AB, "Intel 82801AB watchdog timer", 1, 1 }, { DEVICEID_82801BA, "Intel 82801BA watchdog timer", 2, 1 }, { DEVICEID_82801BAM, "Intel 82801BAM watchdog timer", 2, 1 }, { DEVICEID_82801CA, "Intel 82801CA watchdog timer", 3, 1 }, { DEVICEID_82801CAM, "Intel 82801CAM watchdog timer", 3, 1 }, { DEVICEID_82801DB, "Intel 82801DB watchdog timer", 4, 1 }, { DEVICEID_82801DBM, "Intel 82801DBM watchdog timer", 4, 1 }, { DEVICEID_82801E, "Intel 82801E watchdog timer", 5, 1 }, { DEVICEID_82801EB, "Intel 82801EB watchdog timer", 5, 1 }, { DEVICEID_82801EBR, "Intel 82801EB/ER watchdog timer", 5, 1 }, { DEVICEID_6300ESB, "Intel 6300ESB watchdog timer", 5, 1 }, { DEVICEID_82801FBR, "Intel 82801FB/FR watchdog timer", 6, 2 }, { DEVICEID_ICH6M, "Intel ICH6M watchdog timer", 6, 2 }, { DEVICEID_ICH6W, "Intel ICH6W watchdog timer", 6, 2 }, { DEVICEID_ICH7, "Intel ICH7 watchdog timer", 7, 2 }, { DEVICEID_ICH7DH, "Intel ICH7DH watchdog timer", 7, 2 }, { DEVICEID_ICH7M, "Intel ICH7M watchdog timer", 7, 2 }, { DEVICEID_ICH7MDH, "Intel ICH7MDH watchdog timer", 7, 2 }, { DEVICEID_NM10, "Intel NM10 watchdog timer", 7, 2 }, { DEVICEID_ICH8, "Intel ICH8 watchdog timer", 8, 2 }, { DEVICEID_ICH8DH, "Intel ICH8DH watchdog timer", 8, 2 }, { DEVICEID_ICH8DO, "Intel ICH8DO watchdog timer", 8, 2 }, { DEVICEID_ICH8M, "Intel ICH8M watchdog timer", 8, 2 }, { DEVICEID_ICH8ME, "Intel ICH8M-E watchdog timer", 8, 2 }, { DEVICEID_63XXESB, "Intel 63XXESB watchdog timer", 8, 2 }, { DEVICEID_ICH9, "Intel ICH9 watchdog timer", 9, 2 }, { DEVICEID_ICH9DH, "Intel ICH9DH watchdog timer", 9, 2 }, { DEVICEID_ICH9DO, "Intel ICH9DO watchdog timer", 9, 2 }, { DEVICEID_ICH9M, "Intel ICH9M watchdog timer", 9, 2 }, { DEVICEID_ICH9ME, "Intel ICH9M-E watchdog timer", 9, 2 }, { DEVICEID_ICH9R, "Intel ICH9R watchdog timer", 9, 2 }, { DEVICEID_ICH10, "Intel ICH10 watchdog timer", 10, 2 }, { DEVICEID_ICH10D, "Intel ICH10D watchdog timer", 10, 2 }, { DEVICEID_ICH10DO, "Intel ICH10DO watchdog timer", 10, 2 }, { DEVICEID_ICH10R, "Intel ICH10R watchdog timer", 10, 2 }, { DEVICEID_PCH, "Intel PCH watchdog timer", 10, 2 }, { DEVICEID_PCHM, "Intel PCH watchdog timer", 10, 2 }, { DEVICEID_P55, "Intel P55 watchdog timer", 10, 2 }, { DEVICEID_PM55, "Intel PM55 watchdog timer", 10, 2 }, { DEVICEID_H55, "Intel H55 watchdog timer", 10, 2 }, { DEVICEID_QM57, "Intel QM57 watchdog timer", 10, 2 }, { DEVICEID_H57, "Intel H57 watchdog timer", 10, 2 }, { DEVICEID_HM55, "Intel HM55 watchdog timer", 10, 2 }, { DEVICEID_Q57, "Intel Q57 watchdog timer", 10, 2 }, { DEVICEID_HM57, "Intel HM57 watchdog timer", 10, 2 }, { DEVICEID_PCHMSFF, "Intel PCHMSFF watchdog timer", 10, 2 }, { DEVICEID_QS57, "Intel QS57 watchdog timer", 10, 2 }, { DEVICEID_3400, "Intel 3400 watchdog timer", 10, 2 }, { DEVICEID_3420, "Intel 3420 watchdog timer", 10, 2 }, { DEVICEID_3450, "Intel 3450 watchdog timer", 10, 2 }, { DEVICEID_CPT0, "Intel Cougar Point watchdog timer", 10, 2 }, { DEVICEID_CPT1, "Intel Cougar Point watchdog timer", 10, 2 }, { DEVICEID_CPT2, "Intel Cougar Point watchdog timer", 10, 2 }, { DEVICEID_CPT3, "Intel Cougar Point watchdog timer", 10, 2 }, { DEVICEID_CPT4, "Intel Cougar Point watchdog timer", 10, 2 }, { DEVICEID_CPT5, "Intel Cougar Point watchdog timer", 10, 2 }, { DEVICEID_CPT6, "Intel Cougar Point watchdog timer", 10, 2 }, { DEVICEID_CPT7, "Intel Cougar Point watchdog timer", 10, 2 }, { DEVICEID_CPT8, "Intel Cougar Point watchdog timer", 10, 2 }, { DEVICEID_CPT9, "Intel Cougar Point watchdog timer", 10, 2 }, { DEVICEID_CPT10, "Intel Cougar Point watchdog timer", 10, 2 }, { DEVICEID_CPT11, "Intel Cougar Point watchdog timer", 10, 2 }, { DEVICEID_CPT12, "Intel Cougar Point watchdog timer", 10, 2 }, { DEVICEID_CPT13, "Intel Cougar Point watchdog timer", 10, 2 }, { DEVICEID_CPT14, "Intel Cougar Point watchdog timer", 10, 2 }, { DEVICEID_CPT15, "Intel Cougar Point watchdog timer", 10, 2 }, { DEVICEID_CPT16, "Intel Cougar Point watchdog timer", 10, 2 }, { DEVICEID_CPT17, "Intel Cougar Point watchdog timer", 10, 2 }, { DEVICEID_CPT18, "Intel Cougar Point watchdog timer", 10, 2 }, { DEVICEID_CPT19, "Intel Cougar Point watchdog timer", 10, 2 }, { DEVICEID_CPT20, "Intel Cougar Point watchdog timer", 10, 2 }, { DEVICEID_CPT21, "Intel Cougar Point watchdog timer", 10, 2 }, { DEVICEID_CPT22, "Intel Cougar Point watchdog timer", 10, 2 }, { DEVICEID_CPT23, "Intel Cougar Point watchdog timer", 10, 2 }, { DEVICEID_CPT24, "Intel Cougar Point watchdog timer", 10, 2 }, { DEVICEID_CPT25, "Intel Cougar Point watchdog timer", 10, 2 }, { DEVICEID_CPT26, "Intel Cougar Point watchdog timer", 10, 2 }, { DEVICEID_CPT27, "Intel Cougar Point watchdog timer", 10, 2 }, { DEVICEID_CPT28, "Intel Cougar Point watchdog timer", 10, 2 }, { DEVICEID_CPT29, "Intel Cougar Point watchdog timer", 10, 2 }, { DEVICEID_CPT30, "Intel Cougar Point watchdog timer", 10, 2 }, { DEVICEID_CPT31, "Intel Cougar Point watchdog timer", 10, 2 }, { DEVICEID_PATSBURG_LPC1, "Intel Patsburg watchdog timer", 10, 2 }, { DEVICEID_PATSBURG_LPC2, "Intel Patsburg watchdog timer", 10, 2 }, { DEVICEID_PPT0, "Intel Panther Point watchdog timer", 10, 2 }, { DEVICEID_PPT1, "Intel Panther Point watchdog timer", 10, 2 }, { DEVICEID_PPT2, "Intel Panther Point watchdog timer", 10, 2 }, { DEVICEID_PPT3, "Intel Panther Point watchdog timer", 10, 2 }, { DEVICEID_PPT4, "Intel Panther Point watchdog timer", 10, 2 }, { DEVICEID_PPT5, "Intel Panther Point watchdog timer", 10, 2 }, { DEVICEID_PPT6, "Intel Panther Point watchdog timer", 10, 2 }, { DEVICEID_PPT7, "Intel Panther Point watchdog timer", 10, 2 }, { DEVICEID_PPT8, "Intel Panther Point watchdog timer", 10, 2 }, { DEVICEID_PPT9, "Intel Panther Point watchdog timer", 10, 2 }, { DEVICEID_PPT10, "Intel Panther Point watchdog timer", 10, 2 }, { DEVICEID_PPT11, "Intel Panther Point watchdog timer", 10, 2 }, { DEVICEID_PPT12, "Intel Panther Point watchdog timer", 10, 2 }, { DEVICEID_PPT13, "Intel Panther Point watchdog timer", 10, 2 }, { DEVICEID_PPT14, "Intel Panther Point watchdog timer", 10, 2 }, { DEVICEID_PPT15, "Intel Panther Point watchdog timer", 10, 2 }, { DEVICEID_PPT16, "Intel Panther Point watchdog timer", 10, 2 }, { DEVICEID_PPT17, "Intel Panther Point watchdog timer", 10, 2 }, { DEVICEID_PPT18, "Intel Panther Point watchdog timer", 10, 2 }, { DEVICEID_PPT19, "Intel Panther Point watchdog timer", 10, 2 }, { DEVICEID_PPT20, "Intel Panther Point watchdog timer", 10, 2 }, { DEVICEID_PPT21, "Intel Panther Point watchdog timer", 10, 2 }, { DEVICEID_PPT22, "Intel Panther Point watchdog timer", 10, 2 }, { DEVICEID_PPT23, "Intel Panther Point watchdog timer", 10, 2 }, { DEVICEID_PPT24, "Intel Panther Point watchdog timer", 10, 2 }, { DEVICEID_PPT25, "Intel Panther Point watchdog timer", 10, 2 }, { DEVICEID_PPT26, "Intel Panther Point watchdog timer", 10, 2 }, { DEVICEID_PPT27, "Intel Panther Point watchdog timer", 10, 2 }, { DEVICEID_PPT28, "Intel Panther Point watchdog timer", 10, 2 }, { DEVICEID_PPT29, "Intel Panther Point watchdog timer", 10, 2 }, { DEVICEID_PPT30, "Intel Panther Point watchdog timer", 10, 2 }, { DEVICEID_PPT31, "Intel Panther Point watchdog timer", 10, 2 }, { DEVICEID_LPT0, "Intel Lynx Point watchdog timer", 10, 2 }, { DEVICEID_LPT1, "Intel Lynx Point watchdog timer", 10, 2 }, { DEVICEID_LPT2, "Intel Lynx Point watchdog timer", 10, 2 }, { DEVICEID_LPT3, "Intel Lynx Point watchdog timer", 10, 2 }, { DEVICEID_LPT4, "Intel Lynx Point watchdog timer", 10, 2 }, { DEVICEID_LPT5, "Intel Lynx Point watchdog timer", 10, 2 }, { DEVICEID_LPT6, "Intel Lynx Point watchdog timer", 10, 2 }, { DEVICEID_LPT7, "Intel Lynx Point watchdog timer", 10, 2 }, { DEVICEID_LPT8, "Intel Lynx Point watchdog timer", 10, 2 }, { DEVICEID_LPT9, "Intel Lynx Point watchdog timer", 10, 2 }, { DEVICEID_LPT10, "Intel Lynx Point watchdog timer", 10, 2 }, { DEVICEID_LPT11, "Intel Lynx Point watchdog timer", 10, 2 }, { DEVICEID_LPT12, "Intel Lynx Point watchdog timer", 10, 2 }, { DEVICEID_LPT13, "Intel Lynx Point watchdog timer", 10, 2 }, { DEVICEID_LPT14, "Intel Lynx Point watchdog timer", 10, 2 }, { DEVICEID_LPT15, "Intel Lynx Point watchdog timer", 10, 2 }, { DEVICEID_LPT16, "Intel Lynx Point watchdog timer", 10, 2 }, { DEVICEID_LPT17, "Intel Lynx Point watchdog timer", 10, 2 }, { DEVICEID_LPT18, "Intel Lynx Point watchdog timer", 10, 2 }, { DEVICEID_LPT19, "Intel Lynx Point watchdog timer", 10, 2 }, { DEVICEID_LPT20, "Intel Lynx Point watchdog timer", 10, 2 }, { DEVICEID_LPT21, "Intel Lynx Point watchdog timer", 10, 2 }, { DEVICEID_LPT22, "Intel Lynx Point watchdog timer", 10, 2 }, { DEVICEID_LPT23, "Intel Lynx Point watchdog timer", 10, 2 }, { DEVICEID_LPT24, "Intel Lynx Point watchdog timer", 10, 2 }, { DEVICEID_LPT25, "Intel Lynx Point watchdog timer", 10, 2 }, { DEVICEID_LPT26, "Intel Lynx Point watchdog timer", 10, 2 }, { DEVICEID_LPT27, "Intel Lynx Point watchdog timer", 10, 2 }, { DEVICEID_LPT28, "Intel Lynx Point watchdog timer", 10, 2 }, { DEVICEID_LPT29, "Intel Lynx Point watchdog timer", 10, 2 }, { DEVICEID_LPT30, "Intel Lynx Point watchdog timer", 10, 2 }, { DEVICEID_LPT31, "Intel Lynx Point watchdog timer", 10, 2 }, { DEVICEID_WCPT1, "Intel Wildcat Point watchdog timer", 10, 2 }, { DEVICEID_WCPT2, "Intel Wildcat Point watchdog timer", 10, 2 }, { DEVICEID_WCPT3, "Intel Wildcat Point watchdog timer", 10, 2 }, { DEVICEID_WCPT4, "Intel Wildcat Point watchdog timer", 10, 2 }, { DEVICEID_WCPT6, "Intel Wildcat Point watchdog timer", 10, 2 }, { DEVICEID_WBG0, "Intel Wellsburg watchdog timer", 10, 2 }, { DEVICEID_WBG1, "Intel Wellsburg watchdog timer", 10, 2 }, { DEVICEID_WBG2, "Intel Wellsburg watchdog timer", 10, 2 }, { DEVICEID_WBG3, "Intel Wellsburg watchdog timer", 10, 2 }, { DEVICEID_WBG4, "Intel Wellsburg watchdog timer", 10, 2 }, { DEVICEID_WBG5, "Intel Wellsburg watchdog timer", 10, 2 }, { DEVICEID_WBG6, "Intel Wellsburg watchdog timer", 10, 2 }, { DEVICEID_WBG7, "Intel Wellsburg watchdog timer", 10, 2 }, { DEVICEID_WBG8, "Intel Wellsburg watchdog timer", 10, 2 }, { DEVICEID_WBG9, "Intel Wellsburg watchdog timer", 10, 2 }, { DEVICEID_WBG10, "Intel Wellsburg watchdog timer", 10, 2 }, { DEVICEID_WBG11, "Intel Wellsburg watchdog timer", 10, 2 }, { DEVICEID_WBG12, "Intel Wellsburg watchdog timer", 10, 2 }, { DEVICEID_WBG13, "Intel Wellsburg watchdog timer", 10, 2 }, { DEVICEID_WBG14, "Intel Wellsburg watchdog timer", 10, 2 }, { DEVICEID_WBG15, "Intel Wellsburg watchdog timer", 10, 2 }, { DEVICEID_WBG16, "Intel Wellsburg watchdog timer", 10, 2 }, { DEVICEID_WBG17, "Intel Wellsburg watchdog timer", 10, 2 }, { DEVICEID_WBG18, "Intel Wellsburg watchdog timer", 10, 2 }, { DEVICEID_WBG19, "Intel Wellsburg watchdog timer", 10, 2 }, { DEVICEID_WBG20, "Intel Wellsburg watchdog timer", 10, 2 }, { DEVICEID_WBG21, "Intel Wellsburg watchdog timer", 10, 2 }, { DEVICEID_WBG22, "Intel Wellsburg watchdog timer", 10, 2 }, { DEVICEID_WBG23, "Intel Wellsburg watchdog timer", 10, 2 }, { DEVICEID_WBG24, "Intel Wellsburg watchdog timer", 10, 2 }, { DEVICEID_WBG25, "Intel Wellsburg watchdog timer", 10, 2 }, { DEVICEID_WBG26, "Intel Wellsburg watchdog timer", 10, 2 }, { DEVICEID_WBG27, "Intel Wellsburg watchdog timer", 10, 2 }, { DEVICEID_WBG28, "Intel Wellsburg watchdog timer", 10, 2 }, { DEVICEID_WBG29, "Intel Wellsburg watchdog timer", 10, 2 }, { DEVICEID_WBG30, "Intel Wellsburg watchdog timer", 10, 2 }, { DEVICEID_WBG31, "Intel Wellsburg watchdog timer", 10, 2 }, { DEVICEID_LPT_LP0, "Intel Lynx Point-LP watchdog timer", 10, 2 }, { DEVICEID_LPT_LP1, "Intel Lynx Point-LP watchdog timer", 10, 2 }, { DEVICEID_LPT_LP2, "Intel Lynx Point-LP watchdog timer", 10, 2 }, { DEVICEID_LPT_LP3, "Intel Lynx Point-LP watchdog timer", 10, 2 }, { DEVICEID_LPT_LP4, "Intel Lynx Point-LP watchdog timer", 10, 2 }, { DEVICEID_LPT_LP5, "Intel Lynx Point-LP watchdog timer", 10, 2 }, { DEVICEID_LPT_LP6, "Intel Lynx Point-LP watchdog timer", 10, 2 }, { DEVICEID_LPT_LP7, "Intel Lynx Point-LP watchdog timer", 10, 2 }, { DEVICEID_WCPT_LP1, "Intel Wildcat Point-LP watchdog timer", 10, 2 }, { DEVICEID_WCPT_LP2, "Intel Wildcat Point-LP watchdog timer", 10, 2 }, { DEVICEID_WCPT_LP3, "Intel Wildcat Point-LP watchdog timer", 10, 2 }, { DEVICEID_WCPT_LP5, "Intel Wildcat Point-LP watchdog timer", 10, 2 }, { DEVICEID_WCPT_LP6, "Intel Wildcat Point-LP watchdog timer", 10, 2 }, { DEVICEID_WCPT_LP7, "Intel Wildcat Point-LP watchdog timer", 10, 2 }, { DEVICEID_WCPT_LP9, "Intel Wildcat Point-LP watchdog timer", 10, 2 }, { DEVICEID_DH89XXCC_LPC, "Intel DH89xxCC watchdog timer", 10, 2 }, { DEVICEID_COLETOCRK_LPC, "Intel Coleto Creek watchdog timer", 10, 2 }, { DEVICEID_AVN0, "Intel Avoton/Rangeley SoC watchdog timer",10, 3 }, { DEVICEID_AVN1, "Intel Avoton/Rangeley SoC watchdog timer",10, 3 }, { DEVICEID_AVN2, "Intel Avoton/Rangeley SoC watchdog timer",10, 3 }, { DEVICEID_AVN3, "Intel Avoton/Rangeley SoC watchdog timer",10, 3 }, { DEVICEID_BAYTRAIL, "Intel Bay Trail SoC watchdog timer", 10, 3 }, { DEVICEID_BRASWELL, "Intel Braswell SoC watchdog timer", 10, 3 }, { 0, NULL, 0, 0 }, }; static struct ichwd_device ichwd_smb_devices[] = { { DEVICEID_LEWISBURG_SMB, "Lewisburg watchdog timer", 10, 4 }, { DEVICEID_SRPTLP_SMB, "Sunrise Point-LP watchdog timer", 10, 4 }, + { DEVICEID_C3000, "Intel Atom C3000 watchdog timer", 10, 4 }, { 0, NULL, 0, 0 }, }; static devclass_t ichwd_devclass; #define ichwd_read_tco_1(sc, off) \ bus_read_1((sc)->tco_res, (off)) #define ichwd_read_tco_2(sc, off) \ bus_read_2((sc)->tco_res, (off)) #define ichwd_read_tco_4(sc, off) \ bus_read_4((sc)->tco_res, (off)) #define ichwd_read_smi_4(sc, off) \ bus_read_4((sc)->smi_res, (off)) #define ichwd_read_gcs_4(sc, off) \ bus_read_4((sc)->gcs_res, (off)) /* NB: TCO version 3 devices use the gcs_res resource for the PMC register. */ #define ichwd_read_pmc_4(sc, off) \ bus_read_4((sc)->gcs_res, (off)) #define ichwd_read_gc_4(sc, off) \ bus_read_4((sc)->gc_res, (off)) #define ichwd_write_tco_1(sc, off, val) \ bus_write_1((sc)->tco_res, (off), (val)) #define ichwd_write_tco_2(sc, off, val) \ bus_write_2((sc)->tco_res, (off), (val)) #define ichwd_write_tco_4(sc, off, val) \ bus_write_4((sc)->tco_res, (off), (val)) #define ichwd_write_smi_4(sc, off, val) \ bus_write_4((sc)->smi_res, (off), (val)) #define ichwd_write_gcs_4(sc, off, val) \ bus_write_4((sc)->gcs_res, (off), (val)) /* NB: TCO version 3 devices use the gcs_res resource for the PMC register. */ #define ichwd_write_pmc_4(sc, off, val) \ bus_write_4((sc)->gcs_res, (off), (val)) #define ichwd_write_gc_4(sc, off, val) \ bus_write_4((sc)->gc_res, (off), (val)) #define ichwd_verbose_printf(dev, ...) \ do { \ if (bootverbose) \ device_printf(dev, __VA_ARGS__);\ } while (0) /* * Disable the watchdog timeout SMI handler. * * Apparently, some BIOSes install handlers that reset or disable the * watchdog timer instead of resetting the system, so we disable the SMI * (by clearing the SMI_TCO_EN bit of the SMI_EN register) to prevent this * from happening. */ static __inline void ichwd_smi_disable(struct ichwd_softc *sc) { ichwd_write_smi_4(sc, SMI_EN, ichwd_read_smi_4(sc, SMI_EN) & ~SMI_TCO_EN); } /* * Enable the watchdog timeout SMI handler. See above for details. */ static __inline void ichwd_smi_enable(struct ichwd_softc *sc) { ichwd_write_smi_4(sc, SMI_EN, ichwd_read_smi_4(sc, SMI_EN) | SMI_TCO_EN); } /* * Check if the watchdog SMI triggering is enabled. */ static __inline int ichwd_smi_is_enabled(struct ichwd_softc *sc) { return ((ichwd_read_smi_4(sc, SMI_EN) & SMI_TCO_EN) != 0); } /* * Reset the watchdog status bits. */ static __inline void ichwd_sts_reset(struct ichwd_softc *sc) { /* * The watchdog status bits are set to 1 by the hardware to * indicate various conditions. They can be cleared by software * by writing a 1, not a 0. */ ichwd_write_tco_2(sc, TCO1_STS, TCO_TIMEOUT); /* * According to Intel's docs, clearing SECOND_TO_STS and BOOT_STS must * be done in two separate operations. */ ichwd_write_tco_2(sc, TCO2_STS, TCO_SECOND_TO_STS); if (sc->tco_version < 4) ichwd_write_tco_2(sc, TCO2_STS, TCO_BOOT_STS); } /* * Enable the watchdog timer by clearing the TCO_TMR_HALT bit in the * TCO1_CNT register. This is complicated by the need to preserve bit 9 * of that same register, and the requirement that all other bits must be * written back as zero. */ static __inline void ichwd_tmr_enable(struct ichwd_softc *sc) { uint16_t cnt; cnt = ichwd_read_tco_2(sc, TCO1_CNT) & TCO_CNT_PRESERVE; ichwd_write_tco_2(sc, TCO1_CNT, cnt & ~TCO_TMR_HALT); sc->active = 1; ichwd_verbose_printf(sc->device, "timer enabled\n"); } /* * Disable the watchdog timer. See above for details. */ static __inline void ichwd_tmr_disable(struct ichwd_softc *sc) { uint16_t cnt; cnt = ichwd_read_tco_2(sc, TCO1_CNT) & TCO_CNT_PRESERVE; ichwd_write_tco_2(sc, TCO1_CNT, cnt | TCO_TMR_HALT); sc->active = 0; ichwd_verbose_printf(sc->device, "timer disabled\n"); } /* * Reload the watchdog timer: writing anything to any of the lower five * bits of the TCO_RLD register reloads the timer from the last value * written to TCO_TMR. */ static __inline void ichwd_tmr_reload(struct ichwd_softc *sc) { if (sc->tco_version == 1) ichwd_write_tco_1(sc, TCO_RLD, 1); else ichwd_write_tco_2(sc, TCO_RLD, 1); } /* * Set the initial timeout value. Note that this must always be followed * by a reload. */ static __inline void ichwd_tmr_set(struct ichwd_softc *sc, unsigned int timeout) { if (timeout < TCO_RLD_TMR_MIN) timeout = TCO_RLD_TMR_MIN; if (sc->tco_version == 1) { uint8_t tmr_val8 = ichwd_read_tco_1(sc, TCO_TMR1); tmr_val8 &= (~TCO_RLD1_TMR_MAX & 0xff); if (timeout > TCO_RLD1_TMR_MAX) timeout = TCO_RLD1_TMR_MAX; tmr_val8 |= timeout; ichwd_write_tco_1(sc, TCO_TMR1, tmr_val8); } else { uint16_t tmr_val16 = ichwd_read_tco_2(sc, TCO_TMR2); tmr_val16 &= (~TCO_RLD2_TMR_MAX & 0xffff); if (timeout > TCO_RLD2_TMR_MAX) timeout = TCO_RLD2_TMR_MAX; tmr_val16 |= timeout; ichwd_write_tco_2(sc, TCO_TMR2, tmr_val16); } sc->timeout = timeout; ichwd_verbose_printf(sc->device, "timeout set to %u ticks\n", timeout); } static __inline int ichwd_clear_noreboot(struct ichwd_softc *sc) { uint32_t status; int rc = 0; /* try to clear the NO_REBOOT bit */ switch (sc->tco_version) { case 1: status = pci_read_config(sc->ich, ICH_GEN_STA, 1); status &= ~ICH_GEN_STA_NO_REBOOT; pci_write_config(sc->ich, ICH_GEN_STA, status, 1); status = pci_read_config(sc->ich, ICH_GEN_STA, 1); if (status & ICH_GEN_STA_NO_REBOOT) rc = EIO; break; case 2: status = ichwd_read_gcs_4(sc, 0); status &= ~ICH_GCS_NO_REBOOT; ichwd_write_gcs_4(sc, 0, status); status = ichwd_read_gcs_4(sc, 0); if (status & ICH_GCS_NO_REBOOT) rc = EIO; break; case 3: status = ichwd_read_pmc_4(sc, 0); status &= ~ICH_PMC_NO_REBOOT; ichwd_write_pmc_4(sc, 0, status); status = ichwd_read_pmc_4(sc, 0); if (status & ICH_PMC_NO_REBOOT) rc = EIO; break; case 4: status = ichwd_read_gc_4(sc, 0); status &= ~SMB_GC_NO_REBOOT; ichwd_write_gc_4(sc, 0, status); status = ichwd_read_gc_4(sc, 0); if (status & SMB_GC_NO_REBOOT) rc = EIO; break; default: ichwd_verbose_printf(sc->device, "Unknown TCO Version: %d, can't set NO_REBOOT.\n", sc->tco_version); break; } if (rc) device_printf(sc->device, "ICH WDT present but disabled in BIOS or hardware\n"); return (rc); } /* * Watchdog event handler - called by the framework to enable or disable * the watchdog or change the initial timeout value. */ static void ichwd_event(void *arg, unsigned int cmd, int *error) { struct ichwd_softc *sc = arg; unsigned int timeout; /* convert from power-of-two-ns to WDT ticks */ cmd &= WD_INTERVAL; if (sc->tco_version == 3) { timeout = ((uint64_t)1 << cmd) / ICHWD_TCO_V3_TICK; } else { timeout = ((uint64_t)1 << cmd) / ICHWD_TICK; } if (cmd) { if (!sc->active) ichwd_tmr_enable(sc); if (timeout != sc->timeout) ichwd_tmr_set(sc, timeout); ichwd_tmr_reload(sc); *error = 0; } else { if (sc->active) ichwd_tmr_disable(sc); } } static device_t ichwd_find_ich_lpc_bridge(device_t isa, struct ichwd_device **id_p) { struct ichwd_device *id; device_t isab, pci; uint16_t devid; /* Check whether parent ISA bridge looks familiar. */ isab = device_get_parent(isa); pci = device_get_parent(isab); if (pci == NULL || device_get_devclass(pci) != devclass_find("pci")) return (NULL); if (pci_get_vendor(isab) != VENDORID_INTEL) return (NULL); devid = pci_get_device(isab); for (id = ichwd_devices; id->desc != NULL; ++id) { if (devid == id->device) { if (id_p != NULL) *id_p = id; return (isab); } } return (NULL); } static device_t ichwd_find_smb_dev(device_t isa, struct ichwd_device **id_p) { struct ichwd_device *id; device_t isab, smb; uint16_t devid; /* * Check if SMBus controller provides TCO configuration. * The controller's device and function are fixed and we expect * it to be on the same bus as ISA bridge. */ isab = device_get_parent(isa); smb = pci_find_dbsf(pci_get_domain(isab), pci_get_bus(isab), 31, 4); if (smb == NULL) return (NULL); if (pci_get_vendor(smb) != VENDORID_INTEL) return (NULL); devid = pci_get_device(smb); for (id = ichwd_smb_devices; id->desc != NULL; ++id) { if (devid == id->device) { if (id_p != NULL) *id_p = id; return (smb); } } return (NULL); } /* * Look for an ICH LPC interface bridge. If one is found, register an * ichwd device. There can be only one. */ static void ichwd_identify(driver_t *driver, device_t parent) { struct ichwd_device *id_p; device_t ich, smb; device_t dev; uint64_t base_address64; uint32_t base_address; uint32_t ctl; int rc; ich = ichwd_find_ich_lpc_bridge(parent, &id_p); if (ich == NULL) { smb = ichwd_find_smb_dev(parent, &id_p); if (smb == NULL) return; } KASSERT(id_p->tco_version >= 1, ("unexpected TCO version %d", id_p->tco_version)); KASSERT(id_p->tco_version != 4 || smb != NULL, ("could not find PCI SMBus device for TCOv4")); KASSERT(id_p->tco_version >= 4 || ich != NULL, ("could not find PCI LPC bridge device for TCOv1-3")); /* good, add child to bus */ if ((dev = device_find_child(parent, driver->name, 0)) == NULL) dev = BUS_ADD_CHILD(parent, 0, driver->name, 0); if (dev == NULL) return; switch (id_p->tco_version) { case 1: break; case 2: /* get RCBA (root complex base address) */ base_address = pci_read_config(ich, ICH_RCBA, 4); rc = bus_set_resource(ich, SYS_RES_MEMORY, 0, (base_address & 0xffffc000) + ICH_GCS_OFFSET, ICH_GCS_SIZE); if (rc) ichwd_verbose_printf(dev, "Can not set TCO v%d memory resource for RCBA\n", id_p->tco_version); break; case 3: /* get PBASE (Power Management Controller base address) */ base_address = pci_read_config(ich, ICH_PBASE, 4); rc = bus_set_resource(ich, SYS_RES_MEMORY, 0, (base_address & 0xfffffe00) + ICH_PMC_OFFSET, ICH_PMC_SIZE); if (rc) ichwd_verbose_printf(dev, "Can not set TCO v%d memory resource for PBASE\n", id_p->tco_version); break; case 4: /* Get TCO base address. */ ctl = pci_read_config(smb, ICH_TCOCTL, 4); if ((ctl & ICH_TCOCTL_TCO_BASE_EN) == 0) { ichwd_verbose_printf(dev, "TCO v%d decoding is not enabled\n", id_p->tco_version); break; } base_address = pci_read_config(smb, ICH_TCOBASE, 4); rc = bus_set_resource(dev, SYS_RES_IOPORT, 0, base_address & ICH_TCOBASE_ADDRMASK, ICH_TCOBASE_SIZE); if (rc != 0) { ichwd_verbose_printf(dev, "Can not set TCO v%d I/O resource (err = %d)\n", id_p->tco_version, rc); } /* * Unhide Primary to Sideband Bridge (P2SB) PCI device, so that * we can discover the base address of Private Configuration * Space via the bridge's BAR. * Then hide back the bridge. */ pci_cfgregwrite(0, 31, 1, 0xe1, 0, 1); base_address64 = pci_cfgregread(0, 31, 1, SBREG_BAR + 4, 4); base_address64 <<= 32; base_address64 |= pci_cfgregread(0, 31, 1, SBREG_BAR, 4); base_address64 &= ~0xfull; pci_cfgregwrite(0, 31, 1, 0xe1, 1, 1); /* * No Reboot bit is in General Control register, offset 0xc, * within the SMBus target port, ID 0xc6. */ base_address64 += PCR_REG_OFF(SMB_PORT_ID, SMB_GC_REG); rc = bus_set_resource(dev, SYS_RES_MEMORY, 1, base_address64, SMB_GC_SIZE); if (rc != 0) { ichwd_verbose_printf(dev, "Can not set TCO v%d PCR I/O resource (err = %d)\n", id_p->tco_version, rc); } break; default: ichwd_verbose_printf(dev, "Can not set unknown TCO v%d memory resource for unknown base address\n", id_p->tco_version); break; } } static int ichwd_probe(device_t dev) { struct ichwd_device *id_p; /* Do not claim some ISA PnP device by accident. */ if (isa_get_logicalid(dev) != 0) return (ENXIO); if (ichwd_find_ich_lpc_bridge(device_get_parent(dev), &id_p) == NULL && ichwd_find_smb_dev(device_get_parent(dev), &id_p) == NULL) return (ENXIO); device_set_desc_copy(dev, id_p->desc); return (0); } static int ichwd_smb_attach(device_t dev) { struct ichwd_softc *sc; struct ichwd_device *id_p; device_t isab, pmdev; device_t smb; uint32_t acpi_base; sc = device_get_softc(dev); smb = ichwd_find_smb_dev(device_get_parent(dev), &id_p); if (smb == NULL) return (ENXIO); sc->ich_version = id_p->ich_version; sc->tco_version = id_p->tco_version; /* Allocate TCO control I/O register space. */ sc->tco_rid = 0; sc->tco_res = bus_alloc_resource_any(dev, SYS_RES_IOPORT, &sc->tco_rid, RF_ACTIVE | RF_SHAREABLE); if (sc->tco_res == NULL) { device_printf(dev, "unable to reserve TCO registers\n"); return (ENXIO); } /* * Allocate General Control I/O register in PCH * Private Configuration Space (PCR). */ sc->gc_rid = 1; sc->gc_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &sc->gc_rid, RF_ACTIVE | RF_SHAREABLE); if (sc->gc_res == NULL) { device_printf(dev, "unable to reserve hidden P2SB registers\n"); return (ENXIO); } /* Get ACPI base address. */ isab = device_get_parent(device_get_parent(dev)); pmdev = pci_find_dbsf(pci_get_domain(isab), pci_get_bus(isab), 31, 2); if (pmdev == NULL) { device_printf(dev, "unable to find Power Management device\n"); return (ENXIO); } acpi_base = pci_read_config(pmdev, ICH_PMBASE, 4) & 0xffffff00; if (acpi_base == 0) { device_printf(dev, "ACPI base address is not set\n"); return (ENXIO); } /* Allocate SMI control I/O register space. */ sc->smi_rid = 2; sc->smi_res = bus_alloc_resource(dev, SYS_RES_IOPORT, &sc->smi_rid, acpi_base + SMI_BASE, acpi_base + SMI_BASE + SMI_LEN - 1, SMI_LEN, RF_ACTIVE | RF_SHAREABLE); if (sc->smi_res == NULL) { device_printf(dev, "unable to reserve SMI registers\n"); return (ENXIO); } return (0); } static int ichwd_lpc_attach(device_t dev) { struct ichwd_softc *sc; struct ichwd_device *id_p; device_t ich; unsigned int pmbase = 0; sc = device_get_softc(dev); ich = ichwd_find_ich_lpc_bridge(device_get_parent(dev), &id_p); if (ich == NULL) return (ENXIO); sc->ich = ich; sc->ich_version = id_p->ich_version; sc->tco_version = id_p->tco_version; /* get ACPI base address */ pmbase = pci_read_config(ich, ICH_PMBASE, 2) & ICH_PMBASE_MASK; if (pmbase == 0) { device_printf(dev, "ICH PMBASE register is empty\n"); return (ENXIO); } /* allocate I/O register space */ sc->smi_rid = 0; sc->smi_res = bus_alloc_resource(dev, SYS_RES_IOPORT, &sc->smi_rid, pmbase + SMI_BASE, pmbase + SMI_BASE + SMI_LEN - 1, SMI_LEN, RF_ACTIVE | RF_SHAREABLE); if (sc->smi_res == NULL) { device_printf(dev, "unable to reserve SMI registers\n"); return (ENXIO); } sc->tco_rid = 1; sc->tco_res = bus_alloc_resource(dev, SYS_RES_IOPORT, &sc->tco_rid, pmbase + TCO_BASE, pmbase + TCO_BASE + TCO_LEN - 1, TCO_LEN, RF_ACTIVE | RF_SHAREABLE); if (sc->tco_res == NULL) { device_printf(dev, "unable to reserve TCO registers\n"); return (ENXIO); } sc->gcs_rid = 0; if (sc->tco_version >= 2) { sc->gcs_res = bus_alloc_resource_any(ich, SYS_RES_MEMORY, &sc->gcs_rid, RF_ACTIVE|RF_SHAREABLE); if (sc->gcs_res == NULL) { device_printf(dev, "unable to reserve GCS registers\n"); return (ENXIO); } } return (0); } static int ichwd_attach(device_t dev) { struct ichwd_softc *sc; sc = device_get_softc(dev); sc->device = dev; if (ichwd_lpc_attach(dev) != 0 && ichwd_smb_attach(dev) != 0) goto fail; if (ichwd_clear_noreboot(sc) != 0) goto fail; /* * Determine if we are coming up after a watchdog-induced reset. Some * BIOSes may clear this bit at bootup, preventing us from reporting * this case on such systems. We clear this bit in ichwd_sts_reset(). */ if ((ichwd_read_tco_2(sc, TCO2_STS) & TCO_SECOND_TO_STS) != 0) device_printf(dev, "resuming after hardware watchdog timeout\n"); /* reset the watchdog status registers */ ichwd_sts_reset(sc); /* make sure the WDT starts out inactive */ ichwd_tmr_disable(sc); /* register the watchdog event handler */ sc->ev_tag = EVENTHANDLER_REGISTER(watchdog_list, ichwd_event, sc, 0); /* disable the SMI handler */ sc->smi_enabled = ichwd_smi_is_enabled(sc); ichwd_smi_disable(sc); return (0); fail: sc = device_get_softc(dev); if (sc->tco_res != NULL) bus_release_resource(dev, SYS_RES_IOPORT, sc->tco_rid, sc->tco_res); if (sc->smi_res != NULL) bus_release_resource(dev, SYS_RES_IOPORT, sc->smi_rid, sc->smi_res); if (sc->gcs_res != NULL) bus_release_resource(sc->ich, SYS_RES_MEMORY, sc->gcs_rid, sc->gcs_res); if (sc->gc_res != NULL) bus_release_resource(dev, SYS_RES_MEMORY, sc->gc_rid, sc->gc_res); return (ENXIO); } static int ichwd_detach(device_t dev) { struct ichwd_softc *sc; sc = device_get_softc(dev); /* halt the watchdog timer */ if (sc->active) ichwd_tmr_disable(sc); /* enable the SMI handler */ if (sc->smi_enabled != 0) ichwd_smi_enable(sc); /* deregister event handler */ if (sc->ev_tag != NULL) EVENTHANDLER_DEREGISTER(watchdog_list, sc->ev_tag); sc->ev_tag = NULL; /* reset the watchdog status registers */ ichwd_sts_reset(sc); /* deallocate I/O register space */ bus_release_resource(dev, SYS_RES_IOPORT, sc->tco_rid, sc->tco_res); bus_release_resource(dev, SYS_RES_IOPORT, sc->smi_rid, sc->smi_res); /* deallocate memory resource */ if (sc->gcs_res) bus_release_resource(sc->ich, SYS_RES_MEMORY, sc->gcs_rid, sc->gcs_res); if (sc->gc_res) bus_release_resource(dev, SYS_RES_MEMORY, sc->gc_rid, sc->gc_res); return (0); } static device_method_t ichwd_methods[] = { DEVMETHOD(device_identify, ichwd_identify), DEVMETHOD(device_probe, ichwd_probe), DEVMETHOD(device_attach, ichwd_attach), DEVMETHOD(device_detach, ichwd_detach), DEVMETHOD(device_shutdown, ichwd_detach), {0,0} }; static driver_t ichwd_driver = { "ichwd", ichwd_methods, sizeof(struct ichwd_softc), }; DRIVER_MODULE(ichwd, isa, ichwd_driver, ichwd_devclass, NULL, NULL); Index: stable/12/sys/dev/ichwd/ichwd.h =================================================================== --- stable/12/sys/dev/ichwd/ichwd.h (revision 359359) +++ stable/12/sys/dev/ichwd/ichwd.h (revision 359360) @@ -1,410 +1,411 @@ /*- * SPDX-License-Identifier: BSD-2-Clause-FreeBSD * * Copyright (c) 2004 Texas A&M University * All rights reserved. * * Developer: Wm. Daryl Hawkins * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. * * $FreeBSD$ */ #ifndef _ICHWD_H_ #define _ICHWD_H_ struct ichwd_device { uint16_t device; char *desc; unsigned int ich_version; unsigned int tco_version; }; struct ichwd_softc { device_t device; device_t ich; int ich_version; int tco_version; int active; unsigned int timeout; int smi_enabled; int smi_rid; struct resource *smi_res; int tco_rid; struct resource *tco_res; int gcs_rid; struct resource *gcs_res; int gc_rid; struct resource *gc_res; eventhandler_tag ev_tag; }; #define VENDORID_INTEL 0x8086 #define DEVICEID_BAYTRAIL 0x0f1c +#define DEVICEID_C3000 0x19df #define DEVICEID_CPT0 0x1c40 #define DEVICEID_CPT1 0x1c41 #define DEVICEID_CPT2 0x1c42 #define DEVICEID_CPT3 0x1c43 #define DEVICEID_CPT4 0x1c44 #define DEVICEID_CPT5 0x1c45 #define DEVICEID_CPT6 0x1c46 #define DEVICEID_CPT7 0x1c47 #define DEVICEID_CPT8 0x1c48 #define DEVICEID_CPT9 0x1c49 #define DEVICEID_CPT10 0x1c4a #define DEVICEID_CPT11 0x1c4b #define DEVICEID_CPT12 0x1c4c #define DEVICEID_CPT13 0x1c4d #define DEVICEID_CPT14 0x1c4e #define DEVICEID_CPT15 0x1c4f #define DEVICEID_CPT16 0x1c50 #define DEVICEID_CPT17 0x1c51 #define DEVICEID_CPT18 0x1c52 #define DEVICEID_CPT19 0x1c53 #define DEVICEID_CPT20 0x1c54 #define DEVICEID_CPT21 0x1c55 #define DEVICEID_CPT22 0x1c56 #define DEVICEID_CPT23 0x1c57 #define DEVICEID_CPT24 0x1c58 #define DEVICEID_CPT25 0x1c59 #define DEVICEID_CPT26 0x1c5a #define DEVICEID_CPT27 0x1c5b #define DEVICEID_CPT28 0x1c5c #define DEVICEID_CPT29 0x1c5d #define DEVICEID_CPT30 0x1c5e #define DEVICEID_CPT31 0x1c5f #define DEVICEID_PATSBURG_LPC1 0x1d40 #define DEVICEID_PATSBURG_LPC2 0x1d41 #define DEVICEID_PPT0 0x1e40 #define DEVICEID_PPT1 0x1e41 #define DEVICEID_PPT2 0x1e42 #define DEVICEID_PPT3 0x1e43 #define DEVICEID_PPT4 0x1e44 #define DEVICEID_PPT5 0x1e45 #define DEVICEID_PPT6 0x1e46 #define DEVICEID_PPT7 0x1e47 #define DEVICEID_PPT8 0x1e48 #define DEVICEID_PPT9 0x1e49 #define DEVICEID_PPT10 0x1e4a #define DEVICEID_PPT11 0x1e4b #define DEVICEID_PPT12 0x1e4c #define DEVICEID_PPT13 0x1e4d #define DEVICEID_PPT14 0x1e4e #define DEVICEID_PPT15 0x1e4f #define DEVICEID_PPT16 0x1e50 #define DEVICEID_PPT17 0x1e51 #define DEVICEID_PPT18 0x1e52 #define DEVICEID_PPT19 0x1e53 #define DEVICEID_PPT20 0x1e54 #define DEVICEID_PPT21 0x1e55 #define DEVICEID_PPT22 0x1e56 #define DEVICEID_PPT23 0x1e57 #define DEVICEID_PPT24 0x1e58 #define DEVICEID_PPT25 0x1e59 #define DEVICEID_PPT26 0x1e5a #define DEVICEID_PPT27 0x1e5b #define DEVICEID_PPT28 0x1e5c #define DEVICEID_PPT29 0x1e5d #define DEVICEID_PPT30 0x1e5e #define DEVICEID_PPT31 0x1e5f #define DEVICEID_AVN0 0x1f38 #define DEVICEID_AVN1 0x1f39 #define DEVICEID_AVN2 0x1f3a #define DEVICEID_AVN3 0x1f3b #define DEVICEID_BRASWELL 0x229c #define DEVICEID_DH89XXCC_LPC 0x2310 #define DEVICEID_COLETOCRK_LPC 0x2390 #define DEVICEID_82801AA 0x2410 #define DEVICEID_82801AB 0x2420 #define DEVICEID_82801BA 0x2440 #define DEVICEID_82801BAM 0x244c #define DEVICEID_82801CA 0x2480 #define DEVICEID_82801CAM 0x248c #define DEVICEID_82801DB 0x24c0 #define DEVICEID_82801DBM 0x24cc #define DEVICEID_82801E 0x2450 #define DEVICEID_82801EB 0x24dc #define DEVICEID_82801EBR 0x24d0 #define DEVICEID_6300ESB 0x25a1 #define DEVICEID_82801FBR 0x2640 #define DEVICEID_ICH6M 0x2641 #define DEVICEID_ICH6W 0x2642 #define DEVICEID_63XXESB 0x2670 #define DEVICEID_ICH7 0x27b8 #define DEVICEID_ICH7DH 0x27b0 #define DEVICEID_ICH7M 0x27b9 #define DEVICEID_NM10 0x27bc #define DEVICEID_ICH7MDH 0x27bd #define DEVICEID_ICH8 0x2810 #define DEVICEID_ICH8DH 0x2812 #define DEVICEID_ICH8DO 0x2814 #define DEVICEID_ICH8M 0x2815 #define DEVICEID_ICH8ME 0x2811 #define DEVICEID_ICH9 0x2918 #define DEVICEID_ICH9DH 0x2912 #define DEVICEID_ICH9DO 0x2914 #define DEVICEID_ICH9M 0x2919 #define DEVICEID_ICH9ME 0x2917 #define DEVICEID_ICH9R 0x2916 #define DEVICEID_ICH10 0x3a18 #define DEVICEID_ICH10D 0x3a1a #define DEVICEID_ICH10DO 0x3a14 #define DEVICEID_ICH10R 0x3a16 #define DEVICEID_PCH 0x3b00 #define DEVICEID_PCHM 0x3b01 #define DEVICEID_P55 0x3b02 #define DEVICEID_PM55 0x3b03 #define DEVICEID_H55 0x3b06 #define DEVICEID_QM57 0x3b07 #define DEVICEID_H57 0x3b08 #define DEVICEID_HM55 0x3b09 #define DEVICEID_Q57 0x3b0a #define DEVICEID_HM57 0x3b0b #define DEVICEID_PCHMSFF 0x3b0d #define DEVICEID_QS57 0x3b0f #define DEVICEID_3400 0x3b12 #define DEVICEID_3420 0x3b14 #define DEVICEID_3450 0x3b16 #define DEVICEID_LPT0 0x8c40 #define DEVICEID_LPT1 0x8c41 #define DEVICEID_LPT2 0x8c42 #define DEVICEID_LPT3 0x8c43 #define DEVICEID_LPT4 0x8c44 #define DEVICEID_LPT5 0x8c45 #define DEVICEID_LPT6 0x8c46 #define DEVICEID_LPT7 0x8c47 #define DEVICEID_LPT8 0x8c48 #define DEVICEID_LPT9 0x8c49 #define DEVICEID_LPT10 0x8c4a #define DEVICEID_LPT11 0x8c4b #define DEVICEID_LPT12 0x8c4c #define DEVICEID_LPT13 0x8c4d #define DEVICEID_LPT14 0x8c4e #define DEVICEID_LPT15 0x8c4f #define DEVICEID_LPT16 0x8c50 #define DEVICEID_LPT17 0x8c51 #define DEVICEID_LPT18 0x8c52 #define DEVICEID_LPT19 0x8c53 #define DEVICEID_LPT20 0x8c54 #define DEVICEID_LPT21 0x8c55 #define DEVICEID_LPT22 0x8c56 #define DEVICEID_LPT23 0x8c57 #define DEVICEID_LPT24 0x8c58 #define DEVICEID_LPT25 0x8c59 #define DEVICEID_LPT26 0x8c5a #define DEVICEID_LPT27 0x8c5b #define DEVICEID_LPT28 0x8c5c #define DEVICEID_LPT29 0x8c5d #define DEVICEID_LPT30 0x8c5e #define DEVICEID_LPT31 0x8c5f #define DEVICEID_WCPT1 0x8cc1 #define DEVICEID_WCPT2 0x8cc2 #define DEVICEID_WCPT3 0x8cc3 #define DEVICEID_WCPT4 0x8cc4 #define DEVICEID_WCPT6 0x8cc6 #define DEVICEID_WBG0 0x8d40 #define DEVICEID_WBG1 0x8d41 #define DEVICEID_WBG2 0x8d42 #define DEVICEID_WBG3 0x8d43 #define DEVICEID_WBG4 0x8d44 #define DEVICEID_WBG5 0x8d45 #define DEVICEID_WBG6 0x8d46 #define DEVICEID_WBG7 0x8d47 #define DEVICEID_WBG8 0x8d48 #define DEVICEID_WBG9 0x8d49 #define DEVICEID_WBG10 0x8d4a #define DEVICEID_WBG11 0x8d4b #define DEVICEID_WBG12 0x8d4c #define DEVICEID_WBG13 0x8d4d #define DEVICEID_WBG14 0x8d4e #define DEVICEID_WBG15 0x8d4f #define DEVICEID_WBG16 0x8d50 #define DEVICEID_WBG17 0x8d51 #define DEVICEID_WBG18 0x8d52 #define DEVICEID_WBG19 0x8d53 #define DEVICEID_WBG20 0x8d54 #define DEVICEID_WBG21 0x8d55 #define DEVICEID_WBG22 0x8d56 #define DEVICEID_WBG23 0x8d57 #define DEVICEID_WBG24 0x8d58 #define DEVICEID_WBG25 0x8d59 #define DEVICEID_WBG26 0x8d5a #define DEVICEID_WBG27 0x8d5b #define DEVICEID_WBG28 0x8d5c #define DEVICEID_WBG29 0x8d5d #define DEVICEID_WBG30 0x8d5e #define DEVICEID_WBG31 0x8d5f #define DEVICEID_LPT_LP0 0x9c40 #define DEVICEID_LPT_LP1 0x9c41 #define DEVICEID_LPT_LP2 0x9c42 #define DEVICEID_LPT_LP3 0x9c43 #define DEVICEID_LPT_LP4 0x9c44 #define DEVICEID_LPT_LP5 0x9c45 #define DEVICEID_LPT_LP6 0x9c46 #define DEVICEID_LPT_LP7 0x9c47 #define DEVICEID_WCPT_LP1 0x9cc1 #define DEVICEID_WCPT_LP2 0x9cc2 #define DEVICEID_WCPT_LP3 0x9cc3 #define DEVICEID_WCPT_LP5 0x9cc5 #define DEVICEID_WCPT_LP6 0x9cc6 #define DEVICEID_WCPT_LP7 0x9cc7 #define DEVICEID_WCPT_LP9 0x9cc9 #define DEVICEID_LEWISBURG_SMB 0xa1a3 #define DEVICEID_SRPTLP_SMB 0x9d23 /* ICH LPC Interface Bridge Registers (ICH5 and older) */ #define ICH_GEN_STA 0xd4 #define ICH_GEN_STA_NO_REBOOT 0x02 #define ICH_PMBASE 0x40 /* ACPI base address register */ #define ICH_PMBASE_MASK 0x7f80 /* bits 7-15 */ /* ICH Chipset Configuration Registers (ICH6 and newer) */ #define ICH_RCBA 0xf0 #define ICH_GCS_OFFSET 0x3410 #define ICH_GCS_SIZE 0x4 #define ICH_GCS_NO_REBOOT 0x20 /* SoC Power Management Configuration Registers */ #define ICH_PBASE 0x44 #define ICH_PMC_OFFSET 0x08 #define ICH_PMC_SIZE 0x4 #define ICH_PMC_NO_REBOOT 0x10 /* Lewisburg configration registers in SMBus controller. */ #define ICH_TCOBASE 0x50 /* TCO Base Addr */ #define ICH_TCOBASE_ADDRMASK 0xffe0 #define ICH_TCOBASE_SIZE 32 #define ICH_TCOCTL 0x54 /* TCO Control */ #define ICH_TCOCTL_TCO_BASE_EN 0x0100 /* TCO Base decoding enabled */ #define ICH_TCOCTL_TCO_BASE_LOCK 0x0001 /* TCOBASE is locked */ /* * Configuration registers in Sunrise Point and Lewisburg PCH Sideband Interface * and Private Configuration Space. */ #define SBREG_BAR 0x10 #define SMB_GC_REG 0xc #define SMB_GC_SIZE 4 #define SMB_GC_NO_REBOOT 0x2 #define SMB_PORT_ID 0xc6 #define PCR_PORTID_SHIFT 16 #define PCR_REG_OFF(pid, reg) (((pid) << PCR_PORTID_SHIFT) | (reg)) /* register names and locations (relative to PMBASE) */ #define SMI_BASE 0x30 /* base address for SMI registers */ #define SMI_LEN 0x08 #define SMI_EN 0x00 /* SMI Control and Enable Register */ #define SMI_STS 0x04 /* SMI Status Register */ #define TCO_BASE 0x60 /* base address for TCO registers */ #define TCO_LEN 0x20 #define TCO_RLD 0x00 /* TCO Reload and Current Value */ #define TCO_TMR1 0x01 /* TCO Timer Initial Value (ICH5 and older, 8 bits) */ #define TCO_TMR2 0x12 /* TCO Timer Initial Value (ICH6 and newer, 16 bits) */ #define TCO_DAT_IN 0x02 /* TCO Data In (DO NOT USE) */ #define TCO_DAT_OUT 0x03 /* TCO Data Out (DO NOT USE) */ #define TCO1_STS 0x04 /* TCO Status 1 */ #define TCO2_STS 0x06 /* TCO Status 2 */ #define TCO1_CNT 0x08 /* TCO Control 1 */ #define TCO2_CNT 0x08 /* TCO Control 2 */ #define TCO_MESSAGE1 0x0c /* TCO Message 1 */ #define TCO_MESSAGE2 0x0d /* TCO Message 2 */ #define TCO_WDSTATUS 0x0e /* TCO Watchdog status */ #define TCO_TMR 0x12 /* TCP Reload value */ /* bit definitions for SMI_EN and SMI_STS */ #define SMI_TCO_EN 0x2000 #define SMI_TCO_STS 0x2000 #define SMI_GBL_EN 0x0001 /* timer value mask for TCO_RLD and TCO_TMR */ #define TCO_TIMER_MASK 0x1f #define TCO_TIMER_MASK2 0x2f /* status bits for TCO1_STS */ #define TCO_SLVSEL 0x2000 /* TCO Slave Select Soft Strap */ #define TCO_CPUSERR_STS 0x1000 #define TCO_CPUSMI_STS 0x0400 #define TCO_CPUSCI_STS 0x0200 #define TCO_BIOSWR_STS 0x0100 #define TCO_NEWCENTURY 0x0080 /* set for RTC year roll over (99 to 00) */ #define TCO_TIMEOUT 0x0008 /* timed out */ #define TCO_INT_STS 0x0004 /* data out (DO NOT USE) */ #define TCO_SMI_STS 0x0002 /* data in (DO NOT USE) */ #define TCO_NMI2SMI_STS 0x0001 /* status bits for TCO2_STS */ #define TCO_SMLINK_SLAVE_SMI 0x0010 #define TCO_BOOT_STS 0x0004 /* failed to come out of reset */ #define TCO_SECOND_TO_STS 0x0002 /* ran down twice */ #define TCO_INTRD_DET 0x0001 /* control bits for TCO1_CNT */ #define TCO_LOCK 0x1000 /* SMI_BASE.TCO_EN locked */ #define TCO_TMR_HALT 0x0800 /* clear to enable WDT */ #define TCO_NMI2SMI_EN 0x0200 /* convert NMIs to SMIs */ #define TCO_CNT_PRESERVE TCO_NMI2SMI_EN /* preserve these bits */ #define TCO_NMI_NOW 0x0100 /* trigger an NMI */ /* control bits for TCO2_CNT */ #define TCO_OS_POLICY 0x0030 /* mask */ #define TCO_OS_POLICY_BOOT 0x0000 #define TCO_OS_POLICY_SHUTD 0x0010 #define TCO_OS_POLICY_NOLOAD 0x0020 #define TCO_SMB_ALERT_DISABLE 0x0008 #define TCO_INTRD_SEL 0x0003 /* mask */ #define TCO_INTRD_SEL_SILENT 0x0000 #define TCO_INTRD_SEL_INTR 0x0001 #define TCO_INTRD_SEL_SMI 0x0002 /* * Masks for the TCO timer value field in TCO_RLD. * If the datasheets are to be believed, the minimum value actually varies * from chipset to chipset - 4 for ICH5 and 2 for all other chipsets. * I suspect this is a bug in the ICH5 datasheet and that the minimum is * uniformly 2, but I'd rather err on the side of caution. */ #define TCO_RLD_TMR_MIN 0x0004 #define TCO_RLD1_TMR_MAX 0x003f #define TCO_RLD2_TMR_MAX 0x03ff /* * Approximate length in nanoseconds of one WDT tick (about 0.6 sec) * for TCO v1/v2/v4 */ #define ICHWD_TICK 600000000 /* * Approximate length in nanoseconds of one WDT tick (about 1.0 sec) * for TCO v3 */ #define ICHWD_TCO_V3_TICK 1000000000 #endif Index: stable/12/sys/dev/ismt/ismt.c =================================================================== --- stable/12/sys/dev/ismt/ismt.c (revision 359359) +++ stable/12/sys/dev/ismt/ismt.c (revision 359360) @@ -1,782 +1,782 @@ /*- * Copyright (C) 2014 Intel Corporation * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * 3. Neither the name of Intel Corporation nor the names of its * contributors may be used to endorse or promote products derived from * this software without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. */ #include __FBSDID("$FreeBSD$"); #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include "smbus_if.h" #define ISMT_DESC_ENTRIES 32 /* Hardware Descriptor Constants - Control Field */ #define ISMT_DESC_CWRL 0x01 /* Command/Write Length */ #define ISMT_DESC_BLK 0X04 /* Perform Block Transaction */ #define ISMT_DESC_FAIR 0x08 /* Set fairness flag upon successful arbit. */ #define ISMT_DESC_PEC 0x10 /* Packet Error Code */ #define ISMT_DESC_I2C 0x20 /* I2C Enable */ #define ISMT_DESC_INT 0x40 /* Interrupt */ #define ISMT_DESC_SOE 0x80 /* Stop On Error */ /* Hardware Descriptor Constants - Status Field */ #define ISMT_DESC_SCS 0x01 /* Success */ #define ISMT_DESC_DLTO 0x04 /* Data Low Time Out */ #define ISMT_DESC_NAK 0x08 /* NAK Received */ #define ISMT_DESC_CRC 0x10 /* CRC Error */ #define ISMT_DESC_CLTO 0x20 /* Clock Low Time Out */ #define ISMT_DESC_COL 0x40 /* Collisions */ #define ISMT_DESC_LPR 0x80 /* Large Packet Received */ /* Macros */ -#define ISMT_DESC_ADDR_RW(addr, is_read) ((addr << 1) | (is_read)) +#define ISMT_DESC_ADDR_RW(addr, is_read) ((addr) | (is_read)) /* iSMT General Register address offsets (SMBBAR + ) */ #define ISMT_GR_GCTRL 0x000 /* General Control */ #define ISMT_GR_SMTICL 0x008 /* SMT Interrupt Cause Location */ #define ISMT_GR_ERRINTMSK 0x010 /* Error Interrupt Mask */ #define ISMT_GR_ERRAERMSK 0x014 /* Error AER Mask */ #define ISMT_GR_ERRSTS 0x018 /* Error Status */ #define ISMT_GR_ERRINFO 0x01c /* Error Information */ /* iSMT Master Registers */ #define ISMT_MSTR_MDBA 0x100 /* Master Descriptor Base Address */ #define ISMT_MSTR_MCTRL 0x108 /* Master Control */ #define ISMT_MSTR_MSTS 0x10c /* Master Status */ #define ISMT_MSTR_MDS 0x110 /* Master Descriptor Size */ #define ISMT_MSTR_RPOLICY 0x114 /* Retry Policy */ /* iSMT Miscellaneous Registers */ #define ISMT_SPGT 0x300 /* SMBus PHY Global Timing */ /* General Control Register (GCTRL) bit definitions */ #define ISMT_GCTRL_TRST 0x04 /* Target Reset */ #define ISMT_GCTRL_KILL 0x08 /* Kill */ #define ISMT_GCTRL_SRST 0x40 /* Soft Reset */ /* Master Control Register (MCTRL) bit definitions */ #define ISMT_MCTRL_SS 0x01 /* Start/Stop */ #define ISMT_MCTRL_MEIE 0x10 /* Master Error Interrupt Enable */ #define ISMT_MCTRL_FMHP 0x00ff0000 /* Firmware Master Head Ptr (FMHP) */ /* Master Status Register (MSTS) bit definitions */ #define ISMT_MSTS_HMTP 0xff0000 /* HW Master Tail Pointer (HMTP) */ #define ISMT_MSTS_MIS 0x20 /* Master Interrupt Status (MIS) */ #define ISMT_MSTS_MEIS 0x10 /* Master Error Int Status (MEIS) */ #define ISMT_MSTS_IP 0x01 /* In Progress */ /* Master Descriptor Size (MDS) bit definitions */ #define ISMT_MDS_MASK 0xff /* Master Descriptor Size mask (MDS) */ /* SMBus PHY Global Timing Register (SPGT) bit definitions */ #define ISMT_SPGT_SPD_MASK 0xc0000000 /* SMBus Speed mask */ #define ISMT_SPGT_SPD_80K 0x00 /* 80 kHz */ #define ISMT_SPGT_SPD_100K (0x1 << 30) /* 100 kHz */ #define ISMT_SPGT_SPD_400K (0x2 << 30) /* 400 kHz */ #define ISMT_SPGT_SPD_1M (0x3 << 30) /* 1 MHz */ /* MSI Control Register (MSICTL) bit definitions */ #define ISMT_MSICTL_MSIE 0x01 /* MSI Enable */ #define ISMT_MAX_BLOCK_SIZE 32 /* per SMBus spec */ //#define ISMT_DEBUG device_printf #ifndef ISMT_DEBUG #define ISMT_DEBUG(...) #endif /* iSMT Hardware Descriptor */ struct ismt_desc { uint8_t tgtaddr_rw; /* target address & r/w bit */ uint8_t wr_len_cmd; /* write length in bytes or a command */ uint8_t rd_len; /* read length */ uint8_t control; /* control bits */ uint8_t status; /* status bits */ uint8_t retry; /* collision retry and retry count */ uint8_t rxbytes; /* received bytes */ uint8_t txbytes; /* transmitted bytes */ uint32_t dptr_low; /* lower 32 bit of the data pointer */ uint32_t dptr_high; /* upper 32 bit of the data pointer */ } __packed; #define DESC_SIZE (ISMT_DESC_ENTRIES * sizeof(struct ismt_desc)) #define DMA_BUFFER_SIZE 64 struct ismt_softc { device_t pcidev; device_t smbdev; struct thread *bus_reserved; int intr_rid; struct resource *intr_res; void *intr_handle; bus_space_tag_t mmio_tag; bus_space_handle_t mmio_handle; int mmio_rid; struct resource *mmio_res; uint8_t head; struct ismt_desc *desc; bus_dma_tag_t desc_dma_tag; bus_dmamap_t desc_dma_map; uint64_t desc_bus_addr; uint8_t *dma_buffer; bus_dma_tag_t dma_buffer_dma_tag; bus_dmamap_t dma_buffer_dma_map; uint64_t dma_buffer_bus_addr; uint8_t using_msi; }; static void ismt_intr(void *arg) { struct ismt_softc *sc = arg; uint32_t val; val = bus_read_4(sc->mmio_res, ISMT_MSTR_MSTS); ISMT_DEBUG(sc->pcidev, "%s MSTS=0x%x\n", __func__, val); val |= (ISMT_MSTS_MIS | ISMT_MSTS_MEIS); bus_write_4(sc->mmio_res, ISMT_MSTR_MSTS, val); wakeup(sc); } static int ismt_callback(device_t dev, int index, void *data) { struct ismt_softc *sc; int acquired, err; sc = device_get_softc(dev); switch (index) { case SMB_REQUEST_BUS: acquired = atomic_cmpset_ptr( (uintptr_t *)&sc->bus_reserved, (uintptr_t)NULL, (uintptr_t)curthread); ISMT_DEBUG(dev, "SMB_REQUEST_BUS acquired=%d\n", acquired); if (acquired) err = 0; else err = EWOULDBLOCK; break; case SMB_RELEASE_BUS: KASSERT(sc->bus_reserved == curthread, ("SMB_RELEASE_BUS called by wrong thread\n")); ISMT_DEBUG(dev, "SMB_RELEASE_BUS\n"); atomic_store_rel_ptr((uintptr_t *)&sc->bus_reserved, (uintptr_t)NULL); err = 0; break; default: err = SMB_EABORT; break; } return (err); } static struct ismt_desc * ismt_alloc_desc(struct ismt_softc *sc) { struct ismt_desc *desc; KASSERT(sc->bus_reserved == curthread, ("curthread %p did not request bus (%p has reserved)\n", curthread, sc->bus_reserved)); desc = &sc->desc[sc->head++]; if (sc->head == ISMT_DESC_ENTRIES) sc->head = 0; memset(desc, 0, sizeof(*desc)); return (desc); } static int ismt_submit(struct ismt_softc *sc, struct ismt_desc *desc, uint8_t slave, uint8_t is_read) { uint32_t err, fmhp, val; desc->control |= ISMT_DESC_FAIR; if (sc->using_msi) desc->control |= ISMT_DESC_INT; desc->tgtaddr_rw = ISMT_DESC_ADDR_RW(slave, is_read); desc->dptr_low = (sc->dma_buffer_bus_addr & 0xFFFFFFFFLL); desc->dptr_high = (sc->dma_buffer_bus_addr >> 32); wmb(); fmhp = sc->head << 16; val = bus_read_4(sc->mmio_res, ISMT_MSTR_MCTRL); val &= ~ISMT_MCTRL_FMHP; val |= fmhp; bus_write_4(sc->mmio_res, ISMT_MSTR_MCTRL, val); /* set the start bit */ val = bus_read_4(sc->mmio_res, ISMT_MSTR_MCTRL); val |= ISMT_MCTRL_SS; bus_write_4(sc->mmio_res, ISMT_MSTR_MCTRL, val); err = tsleep(sc, PWAIT, "ismt_wait", 5 * hz); if (err != 0) { ISMT_DEBUG(sc->pcidev, "%s timeout\n", __func__); return (SMB_ETIMEOUT); } ISMT_DEBUG(sc->pcidev, "%s status=0x%x\n", __func__, desc->status); if (desc->status & ISMT_DESC_SCS) return (SMB_ENOERR); if (desc->status & ISMT_DESC_NAK) return (SMB_ENOACK); if (desc->status & ISMT_DESC_CRC) return (SMB_EBUSERR); if (desc->status & ISMT_DESC_COL) return (SMB_ECOLLI); if (desc->status & ISMT_DESC_LPR) return (SMB_EINVAL); if (desc->status & (ISMT_DESC_DLTO | ISMT_DESC_CLTO)) return (SMB_ETIMEOUT); return (SMB_EBUSERR); } static int ismt_quick(device_t dev, u_char slave, int how) { struct ismt_desc *desc; struct ismt_softc *sc; int is_read; ISMT_DEBUG(dev, "%s\n", __func__); if (how != SMB_QREAD && how != SMB_QWRITE) { return (SMB_ENOTSUPP); } sc = device_get_softc(dev); desc = ismt_alloc_desc(sc); is_read = (how == SMB_QREAD ? 1 : 0); return (ismt_submit(sc, desc, slave, is_read)); } static int ismt_sendb(device_t dev, u_char slave, char byte) { struct ismt_desc *desc; struct ismt_softc *sc; ISMT_DEBUG(dev, "%s\n", __func__); sc = device_get_softc(dev); desc = ismt_alloc_desc(sc); desc->control = ISMT_DESC_CWRL; desc->wr_len_cmd = byte; return (ismt_submit(sc, desc, slave, 0)); } static int ismt_recvb(device_t dev, u_char slave, char *byte) { struct ismt_desc *desc; struct ismt_softc *sc; int err; ISMT_DEBUG(dev, "%s\n", __func__); sc = device_get_softc(dev); desc = ismt_alloc_desc(sc); desc->rd_len = 1; err = ismt_submit(sc, desc, slave, 1); if (err != SMB_ENOERR) return (err); *byte = sc->dma_buffer[0]; return (err); } static int ismt_writeb(device_t dev, u_char slave, char cmd, char byte) { struct ismt_desc *desc; struct ismt_softc *sc; ISMT_DEBUG(dev, "%s\n", __func__); sc = device_get_softc(dev); desc = ismt_alloc_desc(sc); desc->wr_len_cmd = 2; sc->dma_buffer[0] = cmd; sc->dma_buffer[1] = byte; return (ismt_submit(sc, desc, slave, 0)); } static int ismt_writew(device_t dev, u_char slave, char cmd, short word) { struct ismt_desc *desc; struct ismt_softc *sc; ISMT_DEBUG(dev, "%s\n", __func__); sc = device_get_softc(dev); desc = ismt_alloc_desc(sc); desc->wr_len_cmd = 3; sc->dma_buffer[0] = cmd; sc->dma_buffer[1] = word & 0xFF; sc->dma_buffer[2] = word >> 8; return (ismt_submit(sc, desc, slave, 0)); } static int ismt_readb(device_t dev, u_char slave, char cmd, char *byte) { struct ismt_desc *desc; struct ismt_softc *sc; int err; ISMT_DEBUG(dev, "%s\n", __func__); sc = device_get_softc(dev); desc = ismt_alloc_desc(sc); desc->control = ISMT_DESC_CWRL; desc->wr_len_cmd = cmd; desc->rd_len = 1; err = ismt_submit(sc, desc, slave, 1); if (err != SMB_ENOERR) return (err); *byte = sc->dma_buffer[0]; return (err); } static int ismt_readw(device_t dev, u_char slave, char cmd, short *word) { struct ismt_desc *desc; struct ismt_softc *sc; int err; ISMT_DEBUG(dev, "%s\n", __func__); sc = device_get_softc(dev); desc = ismt_alloc_desc(sc); desc->control = ISMT_DESC_CWRL; desc->wr_len_cmd = cmd; desc->rd_len = 2; err = ismt_submit(sc, desc, slave, 1); if (err != SMB_ENOERR) return (err); *word = sc->dma_buffer[0] | (sc->dma_buffer[1] << 8); return (err); } static int ismt_pcall(device_t dev, u_char slave, char cmd, short sdata, short *rdata) { struct ismt_desc *desc; struct ismt_softc *sc; int err; ISMT_DEBUG(dev, "%s\n", __func__); sc = device_get_softc(dev); desc = ismt_alloc_desc(sc); desc->wr_len_cmd = 3; desc->rd_len = 2; sc->dma_buffer[0] = cmd; sc->dma_buffer[1] = sdata & 0xff; sc->dma_buffer[2] = sdata >> 8; err = ismt_submit(sc, desc, slave, 0); if (err != SMB_ENOERR) return (err); *rdata = sc->dma_buffer[0] | (sc->dma_buffer[1] << 8); return (err); } static int ismt_bwrite(device_t dev, u_char slave, char cmd, u_char count, char *buf) { struct ismt_desc *desc; struct ismt_softc *sc; ISMT_DEBUG(dev, "%s\n", __func__); if (count == 0 || count > ISMT_MAX_BLOCK_SIZE) return (SMB_EINVAL); sc = device_get_softc(dev); desc = ismt_alloc_desc(sc); desc->control = ISMT_DESC_I2C; desc->wr_len_cmd = count + 1; sc->dma_buffer[0] = cmd; memcpy(&sc->dma_buffer[1], buf, count); return (ismt_submit(sc, desc, slave, 0)); } static int ismt_bread(device_t dev, u_char slave, char cmd, u_char *count, char *buf) { struct ismt_desc *desc; struct ismt_softc *sc; int err; ISMT_DEBUG(dev, "%s\n", __func__); if (*count == 0 || *count > ISMT_MAX_BLOCK_SIZE) return (SMB_EINVAL); sc = device_get_softc(dev); desc = ismt_alloc_desc(sc); desc->control = ISMT_DESC_I2C | ISMT_DESC_CWRL; desc->wr_len_cmd = cmd; desc->rd_len = *count; err = ismt_submit(sc, desc, slave, 0); if (err != SMB_ENOERR) return (err); memcpy(buf, sc->dma_buffer, desc->rxbytes); *count = desc->rxbytes; return (err); } static int ismt_detach(device_t dev) { struct ismt_softc *sc; int error; ISMT_DEBUG(dev, "%s\n", __func__); sc = device_get_softc(dev); error = bus_generic_detach(dev); if (error) return (error); device_delete_child(dev, sc->smbdev); if (sc->intr_handle != NULL) { bus_teardown_intr(dev, sc->intr_res, sc->intr_handle); sc->intr_handle = NULL; } if (sc->intr_res != NULL) { bus_release_resource(dev, SYS_RES_IRQ, sc->intr_rid, sc->intr_res); sc->intr_res = NULL; } if (sc->using_msi == 1) pci_release_msi(dev); if (sc->mmio_res != NULL) { bus_release_resource(dev, SYS_RES_MEMORY, sc->mmio_rid, sc->mmio_res); sc->mmio_res = NULL; } bus_dmamap_unload(sc->desc_dma_tag, sc->desc_dma_map); bus_dmamap_unload(sc->dma_buffer_dma_tag, sc->dma_buffer_dma_map); bus_dmamem_free(sc->desc_dma_tag, sc->desc, sc->desc_dma_map); bus_dmamem_free(sc->dma_buffer_dma_tag, sc->dma_buffer, sc->dma_buffer_dma_map); bus_dma_tag_destroy(sc->desc_dma_tag); bus_dma_tag_destroy(sc->dma_buffer_dma_tag); pci_disable_busmaster(dev); return 0; } static void ismt_single_map(void *arg, bus_dma_segment_t *seg, int nseg, int error) { uint64_t *bus_addr = (uint64_t *)arg; KASSERT(error == 0, ("%s: error=%d\n", __func__, error)); KASSERT(nseg == 1, ("%s: nseg=%d\n", __func__, nseg)); *bus_addr = seg[0].ds_addr; } static int ismt_attach(device_t dev) { struct ismt_softc *sc = device_get_softc(dev); int err, num_vectors, val; sc->pcidev = dev; pci_enable_busmaster(dev); if ((sc->smbdev = device_add_child(dev, "smbus", -1)) == NULL) { device_printf(dev, "no smbus child found\n"); err = ENXIO; goto fail; } sc->mmio_rid = PCIR_BAR(0); sc->mmio_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &sc->mmio_rid, RF_ACTIVE); if (sc->mmio_res == NULL) { device_printf(dev, "cannot allocate mmio region\n"); err = ENOMEM; goto fail; } sc->mmio_tag = rman_get_bustag(sc->mmio_res); sc->mmio_handle = rman_get_bushandle(sc->mmio_res); /* Attach "smbus" child */ if ((err = bus_generic_attach(dev)) != 0) { device_printf(dev, "failed to attach child: %d\n", err); err = ENXIO; goto fail; } bus_dma_tag_create(bus_get_dma_tag(dev), 4, PAGE_SIZE, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, DESC_SIZE, 1, DESC_SIZE, 0, NULL, NULL, &sc->desc_dma_tag); bus_dma_tag_create(bus_get_dma_tag(dev), 4, PAGE_SIZE, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, DMA_BUFFER_SIZE, 1, DMA_BUFFER_SIZE, 0, NULL, NULL, &sc->dma_buffer_dma_tag); bus_dmamap_create(sc->desc_dma_tag, 0, &sc->desc_dma_map); bus_dmamap_create(sc->dma_buffer_dma_tag, 0, &sc->dma_buffer_dma_map); bus_dmamem_alloc(sc->desc_dma_tag, (void **)&sc->desc, BUS_DMA_WAITOK, &sc->desc_dma_map); bus_dmamem_alloc(sc->dma_buffer_dma_tag, (void **)&sc->dma_buffer, BUS_DMA_WAITOK, &sc->dma_buffer_dma_map); bus_dmamap_load(sc->desc_dma_tag, sc->desc_dma_map, sc->desc, DESC_SIZE, ismt_single_map, &sc->desc_bus_addr, 0); bus_dmamap_load(sc->dma_buffer_dma_tag, sc->dma_buffer_dma_map, sc->dma_buffer, DMA_BUFFER_SIZE, ismt_single_map, &sc->dma_buffer_bus_addr, 0); bus_write_4(sc->mmio_res, ISMT_MSTR_MDBA, (sc->desc_bus_addr & 0xFFFFFFFFLL)); bus_write_4(sc->mmio_res, ISMT_MSTR_MDBA + 4, (sc->desc_bus_addr >> 32)); /* initialize the Master Control Register (MCTRL) */ bus_write_4(sc->mmio_res, ISMT_MSTR_MCTRL, ISMT_MCTRL_MEIE); /* initialize the Master Status Register (MSTS) */ bus_write_4(sc->mmio_res, ISMT_MSTR_MSTS, 0); /* initialize the Master Descriptor Size (MDS) */ val = bus_read_4(sc->mmio_res, ISMT_MSTR_MDS); val &= ~ISMT_MDS_MASK; val |= (ISMT_DESC_ENTRIES - 1); bus_write_4(sc->mmio_res, ISMT_MSTR_MDS, val); sc->using_msi = 1; if (pci_msi_count(dev) == 0) { sc->using_msi = 0; goto intx; } num_vectors = 1; if (pci_alloc_msi(dev, &num_vectors) != 0) { sc->using_msi = 0; goto intx; } sc->intr_rid = 1; sc->intr_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &sc->intr_rid, RF_ACTIVE); if (sc->intr_res == NULL) { sc->using_msi = 0; pci_release_msi(dev); } intx: if (sc->using_msi == 0) { sc->intr_rid = 0; sc->intr_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &sc->intr_rid, RF_SHAREABLE | RF_ACTIVE); if (sc->intr_res == NULL) { device_printf(dev, "cannot allocate irq\n"); err = ENXIO; goto fail; } } ISMT_DEBUG(dev, "using_msi = %d\n", sc->using_msi); err = bus_setup_intr(dev, sc->intr_res, INTR_TYPE_MISC | INTR_MPSAFE, NULL, ismt_intr, sc, &sc->intr_handle); if (err != 0) { device_printf(dev, "cannot setup interrupt\n"); err = ENXIO; goto fail; } return (0); fail: ismt_detach(dev); return (err); } #define ID_INTEL_S1200_SMT0 0x0c598086 #define ID_INTEL_S1200_SMT1 0x0c5a8086 #define ID_INTEL_C2000_SMT 0x1f158086 #define ID_INTEL_C3000_SMT 0x19ac8086 static int ismt_probe(device_t dev) { const char *desc; switch (pci_get_devid(dev)) { case ID_INTEL_S1200_SMT0: desc = "Atom Processor S1200 SMBus 2.0 Controller 0"; break; case ID_INTEL_S1200_SMT1: desc = "Atom Processor S1200 SMBus 2.0 Controller 1"; break; case ID_INTEL_C2000_SMT: desc = "Atom Processor C2000 SMBus 2.0"; break; case ID_INTEL_C3000_SMT: desc = "Atom Processor C3000 SMBus 2.0"; break; default: return (ENXIO); } device_set_desc(dev, desc); return (BUS_PROBE_DEFAULT); } /* Device methods */ static device_method_t ismt_pci_methods[] = { DEVMETHOD(device_probe, ismt_probe), DEVMETHOD(device_attach, ismt_attach), DEVMETHOD(device_detach, ismt_detach), DEVMETHOD(smbus_callback, ismt_callback), DEVMETHOD(smbus_quick, ismt_quick), DEVMETHOD(smbus_sendb, ismt_sendb), DEVMETHOD(smbus_recvb, ismt_recvb), DEVMETHOD(smbus_writeb, ismt_writeb), DEVMETHOD(smbus_writew, ismt_writew), DEVMETHOD(smbus_readb, ismt_readb), DEVMETHOD(smbus_readw, ismt_readw), DEVMETHOD(smbus_pcall, ismt_pcall), DEVMETHOD(smbus_bwrite, ismt_bwrite), DEVMETHOD(smbus_bread, ismt_bread), DEVMETHOD_END }; static driver_t ismt_pci_driver = { "ismt", ismt_pci_methods, sizeof(struct ismt_softc) }; static devclass_t ismt_pci_devclass; DRIVER_MODULE(ismt, pci, ismt_pci_driver, ismt_pci_devclass, 0, 0); DRIVER_MODULE(smbus, ismt, smbus_driver, smbus_devclass, 0, 0); MODULE_DEPEND(ismt, pci, 1, 1, 1); MODULE_DEPEND(ismt, smbus, SMBUS_MINVER, SMBUS_PREFVER, SMBUS_MAXVER); MODULE_VERSION(ismt, 1); Index: stable/12 =================================================================== --- stable/12 (revision 359359) +++ stable/12 (revision 359360) Property changes on: stable/12 ___________________________________________________________________ Modified: svn:mergeinfo ## -0,0 +0,1 ## Merged /head:r359279