Index: head/sys/conf/options.powerpc =================================================================== --- head/sys/conf/options.powerpc (revision 359057) +++ head/sys/conf/options.powerpc (revision 359058) @@ -1,41 +1,40 @@ # $FreeBSD$ # Options specific to the powerpc platform kernels AIM opt_global.h BOOKE opt_global.h BOOKE_E500 opt_global.h -BOOKE_PPC4XX opt_global.h CELL POWERPC POWERPC64 POWERPCSPE FPU_EMU COMPAT_FREEBSD32 opt_global.h GFB_DEBUG opt_gfb.h GFB_NO_FONT_LOADING opt_gfb.h GFB_NO_MODE_CHANGE opt_gfb.h MOEA64_STATS opt_pmap.h AMIGAONE opt_platform.h MIKROTIK opt_platform.h MPC85XX opt_platform.h POWERMAC opt_platform.h PS3 opt_platform.h MAMBO POWERNV opt_platform.h PSERIES PSIM SC_OFWFB opt_ofwfb.h OFWCONS_POLL_HZ opt_ofw.h # AGP debugging support AGP_DEBUG opt_agp.h # iWARP client interface support in ixl IXL_IW opt_ixl.h Index: head/sys/powerpc/booke/machdep_ppc4xx.c =================================================================== --- head/sys/powerpc/booke/machdep_ppc4xx.c (revision 359057) +++ head/sys/powerpc/booke/machdep_ppc4xx.c (nonexistent) @@ -1,216 +0,0 @@ -/*- - * SPDX-License-Identifier: BSD-2-Clause-FreeBSD - * - * Copyright (c) 2011-2012 Semihalf. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - */ - -#include -__FBSDID("$FreeBSD$"); - -#include -#include - -#include - -#include -#include - -#include - -#define OCP_ADDR_WORDLO(addr) ((uint32_t)((uint64_t)(addr) & 0xFFFFFFFF)) -#define OCP_ADDR_WORDHI(addr) ((uint32_t)((uint64_t)(addr) >> 32)) - -extern void tlb_write(u_int, uint32_t, uint32_t, uint32_t, tlbtid_t, uint32_t, - uint32_t); -extern void tlb_read(u_int, uint32_t *, uint32_t *, uint32_t *, uint32_t *, - uint32_t *, uint32_t *); - -unsigned int tlb_static_entries; -unsigned int tlb_current_entry = TLB_SIZE; -unsigned int tlb_misses = 0; -unsigned int tlb_invals = 0; - -void tlb_map(uint32_t, uint32_t, uint32_t, uint32_t, uint32_t); -void tlb_map_mem(uint32_t, uint32_t, uint32_t); -void tlb_dump(void); - -void -booke_init_tlb(vm_paddr_t fdt_immr_pa) -{ - - /* Map register space */ - tlb_map(APM86XXX_DEEP_SLEEP_VA, - OCP_ADDR_WORDLO(APM86XXX_DEEP_SLEEP_PA), - OCP_ADDR_WORDHI(APM86XXX_DEEP_SLEEP_PA), TLB_VALID | TLB_SIZE_16M, - TLB_SW | TLB_SR | TLB_I | TLB_G); - - tlb_map(APM86XXX_CSR_VA, OCP_ADDR_WORDLO(APM86XXX_CSR_PA), - OCP_ADDR_WORDHI(APM86XXX_CSR_PA), TLB_VALID | TLB_SIZE_16M, - TLB_SW | TLB_SR | TLB_I | TLB_G); - - tlb_map(APM86XXX_PRIMARY_FABRIC_VA, - OCP_ADDR_WORDLO(APM86XXX_PRIMARY_FABRIC_PA), - OCP_ADDR_WORDHI(APM86XXX_PRIMARY_FABRIC_PA), - TLB_VALID | TLB_SIZE_16M, - TLB_SW | TLB_SR | TLB_I | TLB_G); - - tlb_map(APM86XXX_AHB_VA, OCP_ADDR_WORDLO(APM86XXX_AHB_PA), - OCP_ADDR_WORDHI(APM86XXX_AHB_PA), - TLB_VALID | TLB_SIZE_16M, - TLB_SW | TLB_SR | TLB_I | TLB_G); - - /* Map MailBox space */ - tlb_map(APM86XXX_MBOX_VA, OCP_ADDR_WORDLO(APM86XXX_MBOX_PA), - OCP_ADDR_WORDHI(APM86XXX_MBOX_PA), - TLB_VALID | TLB_SIZE_4K, - TLB_UX | TLB_UW | TLB_UR | - TLB_SX | TLB_SW | TLB_SR | - TLB_I | TLB_G); - - tlb_map(APM86XXX_MBOX_VA + 0x1000, - OCP_ADDR_WORDLO(APM86XXX_MBOX_PA) + 0x1000, - OCP_ADDR_WORDHI(APM86XXX_MBOX_PA), - TLB_VALID | TLB_SIZE_4K, - TLB_UX | TLB_UW | TLB_UR | - TLB_SX | TLB_SW | TLB_SR | - TLB_I | TLB_G); - - tlb_map(APM86XXX_MBOX_VA + 0x2000, - OCP_ADDR_WORDLO(APM86XXX_MBOX_PA)+ 0x2000, - OCP_ADDR_WORDHI(APM86XXX_MBOX_PA), - TLB_VALID | TLB_SIZE_4K, - TLB_UX | TLB_UW | TLB_UR | - TLB_SX | TLB_SW | TLB_SR | - TLB_I | TLB_G); -} - -void -booke_enable_l1_cache(void) -{ -} - -void -booke_enable_l2_cache(void) -{ -} - -void -booke_disable_l2_cache(void) -{ - uint32_t ccr1,l2cr0; - - /* Disable L2 cache op broadcast */ - ccr1 = mfspr(SPR_CCR1); - ccr1 &= ~CCR1_L2COBE; - mtspr(SPR_CCR1, ccr1); - - /* Set L2 array size to 0 i.e. disable L2 cache */ - mtdcr(DCR_L2DCDCRAI, DCR_L2CR0); - l2cr0 = mfdcr(DCR_L2DCDCRDI); - l2cr0 &= ~L2CR0_AS; - mtdcr(DCR_L2DCDCRDI, l2cr0); -} - -void tlb_map(uint32_t epn, uint32_t rpn, uint32_t erpn, uint32_t flags, - uint32_t perms) -{ - - tlb_write(++tlb_static_entries, epn, rpn, erpn, 0, flags, perms); -} - -static void tlb_dump_entry(u_int entry) -{ - uint32_t epn, rpn, erpn, tid, flags, perms; - const char *size; - - tlb_read(entry, &epn, &rpn, &erpn, &tid, &flags, &perms); - - switch (flags & TLB_SIZE_MASK) { - case TLB_SIZE_1K: - size = " 1k"; - break; - case TLB_SIZE_4K: - size = " 4k"; - break; - case TLB_SIZE_16K: - size = " 16k"; - break; - case TLB_SIZE_256K: - size = "256k"; - break; - case TLB_SIZE_1M: - size = " 1M"; - break; - case TLB_SIZE_16M: - size = " 16M"; - break; - case TLB_SIZE_256M: - size = "256M"; - break; - case TLB_SIZE_1G: - size = " 1G"; - break; - default: - size = "????"; - break; - } - - - printf("TLB[%02u]: 0x%08X => " - "0x%01X_%08X %s %c %c %s %s %s %s %s " - "%c%c%c%c%c%c%c%c%c%c%c%c%c%c%c (%u)\n", - entry, epn, erpn, rpn, size, - (flags & TLB_TS) ? '1' : '0', - (flags & TLB_VALID) ? 'V' : '.', - (perms & TLB_WL1) ? "WL1" : "___", - (perms & TLB_IL1I) ? "IL1I" : "____", - (perms & TLB_IL1D) ? "IL1D" : "____", - (perms & TLB_IL2I) ? "IL2I" : "____", - (perms & TLB_IL2D) ? "IL2D" : "____", - (perms & TLB_U0) ? '1' : '.', - (perms & TLB_U1) ? '2' : '.', - (perms & TLB_U2) ? '3' : '.', - (perms & TLB_U3) ? '4' : '.', - (perms & TLB_W) ? 'W' : '.', - (perms & TLB_I) ? 'I' : '.', - (perms & TLB_M) ? 'M' : '.', - (perms & TLB_G) ? 'G' : '.', - (perms & TLB_E) ? 'E' : '.', - (perms & TLB_UX) ? 'x' : '.', - (perms & TLB_UW) ? 'w' : '.', - (perms & TLB_UR) ? 'r' : '.', - (perms & TLB_SX) ? 'X' : '.', - (perms & TLB_SW) ? 'W' : '.', - (perms & TLB_SR) ? 'R' : '.', - tid); -} - -void tlb_dump(void) -{ - int i; - - for (i = 0; i < TLB_SIZE; i++) - tlb_dump_entry(i); -} Property changes on: head/sys/powerpc/booke/machdep_ppc4xx.c ___________________________________________________________________ Deleted: svn:eol-style ## -1 +0,0 ## -native \ No newline at end of property Deleted: svn:keywords ## -1 +0,0 ## -FreeBSD=%H \ No newline at end of property Deleted: svn:mime-type ## -1 +0,0 ## -text/plain \ No newline at end of property Index: head/sys/powerpc/booke/machdep_e500.c =================================================================== --- head/sys/powerpc/booke/machdep_e500.c (revision 359057) +++ head/sys/powerpc/booke/machdep_e500.c (revision 359058) @@ -1,127 +1,121 @@ /*- * SPDX-License-Identifier: BSD-2-Clause-FreeBSD * * Copyright (c) 2011-2012 Semihalf. * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. */ #include __FBSDID("$FreeBSD$"); #include #include #include #include #include #include #include #include #include #include extern void dcache_enable(void); extern void dcache_inval(void); extern void icache_enable(void); extern void icache_inval(void); extern void l2cache_enable(void); extern void l2cache_inval(void); extern void bpred_enable(void); void -booke_init_tlb(vm_paddr_t fdt_immr_pa) -{ - -} - -void booke_enable_l1_cache(void) { uint32_t csr; /* Enable D-cache if applicable */ csr = mfspr(SPR_L1CSR0); if ((csr & L1CSR0_DCE) == 0) { dcache_inval(); dcache_enable(); } csr = mfspr(SPR_L1CSR0); if ((boothowto & RB_VERBOSE) != 0 || (csr & L1CSR0_DCE) == 0) printf("L1 D-cache %sabled\n", (csr & L1CSR0_DCE) ? "en" : "dis"); /* Enable L1 I-cache if applicable. */ csr = mfspr(SPR_L1CSR1); if ((csr & L1CSR1_ICE) == 0) { icache_inval(); icache_enable(); } csr = mfspr(SPR_L1CSR1); if ((boothowto & RB_VERBOSE) != 0 || (csr & L1CSR1_ICE) == 0) printf("L1 I-cache %sabled\n", (csr & L1CSR1_ICE) ? "en" : "dis"); } void booke_enable_l2_cache(void) { uint32_t csr; /* Enable L2 cache on E500mc */ if ((((mfpvr() >> 16) & 0xFFFF) == FSL_E500mc) || (((mfpvr() >> 16) & 0xFFFF) == FSL_E5500)) { csr = mfspr(SPR_L2CSR0); if ((csr & L2CSR0_L2E) == 0) { l2cache_inval(); l2cache_enable(); } csr = mfspr(SPR_L2CSR0); if ((boothowto & RB_VERBOSE) != 0 || (csr & L2CSR0_L2E) == 0) printf("L2 cache %sabled\n", (csr & L2CSR0_L2E) ? "en" : "dis"); } } void booke_enable_bpred(void) { uint32_t csr; bpred_enable(); csr = mfspr(SPR_BUCSR); if ((boothowto & RB_VERBOSE) != 0 || (csr & BUCSR_BPEN) == 0) printf("Branch Predictor %sabled\n", (csr & BUCSR_BPEN) ? "en" : "dis"); } void booke_disable_l2_cache(void) { } Index: head/sys/powerpc/conf/NOTES =================================================================== --- head/sys/powerpc/conf/NOTES (revision 359057) +++ head/sys/powerpc/conf/NOTES (revision 359058) @@ -1,92 +1,91 @@ # $FreeBSD$ # # This file contains machine dependent kernel configuration notes. For # machine independent notes, look in /sys/conf/NOTES. # # Enable the kernel DTrace hooks which are required to load the DTrace # kernel modules. # options KDTRACE_HOOKS # DTrace core # NOTE: introduces CDDL-licensed components into the kernel #device dtrace # DTrace modules #device dtrace_profile #device dtrace_sdt #device dtrace_fbt #device dtrace_systrace #device dtrace_prototype #device dtnfscl #device dtmalloc # Alternatively include all the DTrace modules #device dtraceall ##################################################################### # CPU OPTIONS # You must specify a machine directive to choose powerpc or powerpc64 #machine powerpc powerpc[64] # # You must specify at least one CPU (the one you intend to run on). cpu AIM #cpu BOOKE_E500 -#cpu BOOKE_PPC440 options FPU_EMU #options MPC85XX options POWERMAC #NewWorld Apple PowerMacs #options PS3 #Sony Playstation 3 options PSIM #GDB PSIM ppc simulator options MAMBO #IBM Mambo Full System Simulator # The cpufreq(4) driver provides support for CPU frequency control device cpufreq # Standard busses device agp device glc # Sony Playstation 3 Ethernet device kiic # Apple Keywest I2C Controller device ofwd # Open Firmware disks device adb # Apple Desktop Bus device cuda # VIA-CUDA ADB interface device ad7417 # PowerMac7,2 temperature sensor device ds1631 # PowerMac11,2 temperature sensor device ds1775 # PowerMac7,2 temperature sensor device fcu # Apple Fan Control Unit device max6690 # PowerMac7,2 temperature sensor device pmu # Apple Power Management Unit device smu # Apple System Management Unit device snd_ai2s # Apple I2S Audio device snd_davbus # Apple Davbus Audio device adm1030 # Apple G4 MDD fan controller ##################################################################### # Devices we don't want to deal with nodevice ccr nodevice cxgbe # XXX: builds on powerpc64 only. nodevice cxgbev nodevice mpr # no 64-bit atomics nodevice mps # no 64-bit atomics nodevice ppc # sound nodevice snd_cmi # wants gdb_cur nodevice dcons nodevice dcons_crom ##################################################################### # Options we don't want to deal with nooption PPC_DEBUG nooption PPC_PROBE_CHIPSET # uses inb/outb Index: head/sys/powerpc/include/machdep.h =================================================================== --- head/sys/powerpc/include/machdep.h (revision 359057) +++ head/sys/powerpc/include/machdep.h (revision 359058) @@ -1,40 +1,39 @@ /*- * SPDX-License-Identifier: BSD-2-Clause-FreeBSD * * Copyright (c) 2011-2012 Semihalf * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. * * $FreeBSD$ */ #ifndef _POWERPC_MACHDEP_H_ #define _POWERPC_MACHDEP_H_ void booke_disable_l2_cache(void); void booke_enable_l1_cache(void); void booke_enable_l2_cache(void); void booke_enable_bpred(void); -void booke_init_tlb(vm_paddr_t); #endif /* _POWERPC_MACHDEP_H_ */ Index: head/sys/powerpc/include/profile.h =================================================================== --- head/sys/powerpc/include/profile.h (revision 359057) +++ head/sys/powerpc/include/profile.h (revision 359058) @@ -1,235 +1,235 @@ /*- * SPDX-License-Identifier: MIT-CMU * * Copyright (c) 1994, 1995, 1996 Carnegie-Mellon University. * All rights reserved. * * Author: Chris G. Demetriou * * Permission to use, copy, modify and distribute this software and * its documentation is hereby granted, provided that both the copyright * notice and this permission notice appear in all copies of the * software, derivative works or modified versions, and any portions * thereof, and that both notices appear in supporting documentation. * * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS" * CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND * FOR ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE. * * Carnegie Mellon requests users of this software to return to * * Software Distribution Coordinator or Software.Distribution@CS.CMU.EDU * School of Computer Science * Carnegie Mellon University * Pittsburgh PA 15213-3890 * * any improvements or extensions that they make and grant Carnegie the * rights to redistribute these changes. * * from: NetBSD: profile.h,v 1.9 1997/04/06 08:47:37 cgd Exp * from: FreeBSD: src/sys/alpha/include/profile.h,v 1.4 1999/12/29 * $FreeBSD$ */ #ifndef _MACHINE_PROFILE_H_ #define _MACHINE_PROFILE_H_ #define _MCOUNT_DECL void __mcount #define FUNCTION_ALIGNMENT 4 typedef __ptrdiff_t fptrdiff_t; /* * The mcount trampoline macro, expanded in libc/gmon/mcount.c * * For PowerPC SVR4 ABI profiling, the compiler will insert * a data declaration and code sequence at the start of a routine of the form * * .function_mc: .data * .align 2 * .long 0 * .text * * function: mflr %r0 * addis %r11,%r0, .function_mc@ha * stw %r0,4(%r1) * addi %r0,%r11, .function_mc@l * bl _mcount * * The link register is saved in the LR save word in the caller's * stack frame, r0 is set up to point to the allocated longword, * and control is transferred to _mcount. * * On return from _mcount, the routine should function as it would * with no profiling so _mcount must restore register state to that upon * entry. Any routine called by the _mcount trampoline will save * callee-save registers, so _mcount must make sure it saves volatile * registers that may have state after it returns i.e. parameter registers. * * The FreeBSD libc mcount routine ignores the r0 longword pointer, but * instead requires as parameters the current PC and called PC. The current * PC is obtained from the link register, as a result of "bl _mcount" in * the stub, while the caller's PC is obtained from the LR save word. * * On return from libc mcount, the return is done indirectly with the * ctr register rather than the link register, to allow the link register * to be restored to what it was on entry to the profiled routine. */ #if defined(__powerpc64__) #if !defined(_CALL_ELF) || _CALL_ELF == 1 #define MCOUNT_PREAMBLE \ " .align 2 \n" \ " .globl _mcount \n" \ " .section \".opd\",\"aw\" \n" \ " .align 3 \n" \ "_mcount: \n" \ " .quad .L._mcount,.TOC.@tocbase,0\n" \ " .previous \n" \ " .size _mcount,24 \n" \ " .type _mcount,@function \n" \ " .align 4 \n" \ ".L._mcount: \n" #else #define MCOUNT_PREAMBLE \ " .globl _mcount \n" \ " .type _mcount,@function \n" \ " .align 4 \n" \ "_mcount: \n" #endif #define MCOUNT \ __asm( MCOUNT_PREAMBLE \ " stdu %r1,-(288+128)(%r1) \n" \ " std %r3,48(%r1) \n" \ " std %r4,56(%r1) \n" \ " std %r5,64(%r1) \n" \ " std %r6,72(%r1) \n" \ " std %r7,80(%r1) \n" \ " std %r8,88(%r1) \n" \ " std %r9,96(%r1) \n" \ " std %r10,104(%r1) \n" \ " mflr %r4 \n" \ " std %r4,112(%r1) \n" \ " ld %r3,0(%r1) \n" \ " ld %r3,0(%r3) \n" \ " ld %r3,16(%r3) \n" \ " bl __mcount \n" \ " nop \n" \ " ld %r4,112(%r1) \n" \ " mtlr %r4 \n" \ " ld %r3,48(%r1) \n" \ " ld %r4,56(%r1) \n" \ " ld %r5,64(%r1) \n" \ " ld %r6,72(%r1) \n" \ " ld %r7,80(%r1) \n" \ " ld %r8,88(%r1) \n" \ " ld %r9,96(%r1) \n" \ " ld %r10,104(%r1) \n" \ " addi %r1,%r1,(288+128) \n" \ " blr \n"); #else #ifdef PIC #define _PLT "@plt" #else #define _PLT #endif #define MCOUNT \ __asm( " .globl _mcount \n" \ " .type _mcount,@function \n" \ " .align 4 \n" \ "_mcount: \n" \ " stwu %r1,-64(%r1) \n" \ " stw %r3,16(%r1) \n" \ " stw %r4,20(%r1) \n" \ " stw %r5,24(%r1) \n" \ " stw %r6,28(%r1) \n" \ " stw %r7,32(%r1) \n" \ " stw %r8,36(%r1) \n" \ " stw %r9,40(%r1) \n" \ " stw %r10,44(%r1) \n" \ " mflr %r4 \n" \ " stw %r4,48(%r1) \n" \ " lwz %r3,68(%r1) \n" \ " bl __mcount" _PLT " \n" \ " lwz %r3,68(%r1) \n" \ " mtlr %r3 \n" \ " lwz %r4,48(%r1) \n" \ " mtctr %r4 \n" \ " lwz %r3,16(%r1) \n" \ " lwz %r4,20(%r1) \n" \ " lwz %r5,24(%r1) \n" \ " lwz %r6,28(%r1) \n" \ " lwz %r7,32(%r1) \n" \ " lwz %r8,36(%r1) \n" \ " lwz %r9,40(%r1) \n" \ " lwz %r10,44(%r1) \n" \ " addi %r1,%r1,64 \n" \ " bctr \n" \ "_mcount_end: \n" \ " .size _mcount,_mcount_end-_mcount"); #endif #ifdef _KERNEL #define MCOUNT_ENTER(s) s = intr_disable() #define MCOUNT_EXIT(s) intr_restore(s) #define MCOUNT_DECL(s) register_t s; #ifndef COMPILING_LINT #ifdef AIM #include #define __PROFILE_VECTOR_BASE EXC_RST #define __PROFILE_VECTOR_TOP (EXC_LAST + 0x100) #endif /* AIM */ #if defined(BOOKE) extern char interrupt_vector_base[]; extern char interrupt_vector_top[]; #define __PROFILE_VECTOR_BASE (uintfptr_t)interrupt_vector_base #define __PROFILE_VECTOR_TOP (uintfptr_t)interrupt_vector_top -#endif /* BOOKE_E500 || BOOKE_PPC4XX */ +#endif /* BOOKE_E500 */ #endif /* !COMPILING_LINT */ #ifndef __PROFILE_VECTOR_BASE #define __PROFILE_VECTOR_BASE 0 #endif #ifndef __PROFILE_VECTOR_TOP #define __PROFILE_VECTOR_TOP 1 #endif static __inline void powerpc_profile_interrupt(void) { } static __inline void powerpc_profile_userspace(void) { } #define MCOUNT_FROMPC_USER(pc) \ ((pc < (uintfptr_t)VM_MAXUSER_ADDRESS) ? \ (uintfptr_t)powerpc_profile_userspace : pc) #define MCOUNT_FROMPC_INTR(pc) \ ((pc >= __PROFILE_VECTOR_BASE && \ pc < __PROFILE_VECTOR_TOP) ? \ (uintfptr_t)powerpc_profile_interrupt : ~0U) void __mcount(uintfptr_t frompc, uintfptr_t selfpc); #else /* !_KERNEL */ #ifdef __powerpc64__ typedef u_long uintfptr_t; #else typedef u_int uintfptr_t; #endif #endif /* _KERNEL */ #endif /* !_MACHINE_PROFILE_H_ */ Index: head/sys/powerpc/include/pte.h =================================================================== --- head/sys/powerpc/include/pte.h (revision 359057) +++ head/sys/powerpc/include/pte.h (revision 359058) @@ -1,416 +1,398 @@ /*- * SPDX-License-Identifier: BSD-4-Clause * * Copyright (C) 1995, 1996 Wolfgang Solfrank. * Copyright (C) 1995, 1996 TooLs GmbH. * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * 3. All advertising materials mentioning features or use of this software * must display the following acknowledgement: * This product includes software developed by TooLs GmbH. * 4. The name of TooLs GmbH may not be used to endorse or promote products * derived from this software without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY TOOLS GMBH ``AS IS'' AND ANY EXPRESS OR * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. * IN NO EVENT SHALL TOOLS GMBH BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * * $NetBSD: pte.h,v 1.2 1998/08/31 14:43:40 tsubai Exp $ * $FreeBSD$ */ #ifndef _MACHINE_PTE_H_ #define _MACHINE_PTE_H_ #if defined(AIM) /* * Page Table Entries */ #ifndef LOCORE /* 32-bit PTE */ struct pte { u_int32_t pte_hi; u_int32_t pte_lo; }; struct pteg { struct pte pt[8]; }; /* 64-bit (long) PTE */ struct lpte { u_int64_t pte_hi; u_int64_t pte_lo; }; struct lpteg { struct lpte pt[8]; }; /* Partition table entry */ struct pate { u_int64_t pagetab; u_int64_t proctab; }; typedef struct pte pte_t; typedef struct lpte lpte_t; #endif /* LOCORE */ /* 32-bit PTE definitions */ /* High word: */ #define PTE_VALID 0x80000000 #define PTE_VSID_SHFT 7 #define PTE_HID 0x00000040 #define PTE_API 0x0000003f /* Low word: */ #define PTE_RPGN 0xfffff000 #define PTE_REF 0x00000100 #define PTE_CHG 0x00000080 #define PTE_WIMG 0x00000078 #define PTE_W 0x00000040 #define PTE_I 0x00000020 #define PTE_M 0x00000010 #define PTE_G 0x00000008 #define PTE_PP 0x00000003 #define PTE_SO 0x00000000 /* Super. Only (U: XX, S: RW) */ #define PTE_SW 0x00000001 /* Super. Write-Only (U: RO, S: RW) */ #define PTE_BW 0x00000002 /* Supervisor (U: RW, S: RW) */ #define PTE_BR 0x00000003 /* Both Read Only (U: RO, S: RO) */ #define PTE_RW PTE_BW #define PTE_RO PTE_BR #define PTE_EXEC 0x00000200 /* pseudo bit in attrs; page is exec */ /* 64-bit PTE definitions */ /* High quadword: */ #define LPTE_VSID_SHIFT 12 #define LPTE_AVPN_MASK 0xFFFFFFFFFFFFFF80ULL #define LPTE_API 0x0000000000000F80ULL #define LPTE_SWBITS 0x0000000000000078ULL #define LPTE_WIRED 0x0000000000000010ULL #define LPTE_LOCKED 0x0000000000000008ULL #define LPTE_BIG 0x0000000000000004ULL /* 4kb/16Mb page */ #define LPTE_HID 0x0000000000000002ULL #define LPTE_VALID 0x0000000000000001ULL /* Low quadword: */ #define EXTEND_PTE(x) UINT64_C(x) /* make constants 64-bit */ #define LPTE_RPGN 0xfffffffffffff000ULL #define LPTE_REF EXTEND_PTE( PTE_REF ) #define LPTE_CHG EXTEND_PTE( PTE_CHG ) #define LPTE_WIMG EXTEND_PTE( PTE_WIMG ) #define LPTE_W EXTEND_PTE( PTE_W ) #define LPTE_I EXTEND_PTE( PTE_I ) #define LPTE_M EXTEND_PTE( PTE_M ) #define LPTE_G EXTEND_PTE( PTE_G ) #define LPTE_NOEXEC 0x0000000000000004ULL #define LPTE_PP EXTEND_PTE( PTE_PP ) #define LPTE_SO EXTEND_PTE( PTE_SO ) /* Super. Only */ #define LPTE_SW EXTEND_PTE( PTE_SW ) /* Super. Write-Only */ #define LPTE_BW EXTEND_PTE( PTE_BW ) /* Supervisor */ #define LPTE_BR EXTEND_PTE( PTE_BR ) /* Both Read Only */ #define LPTE_RW LPTE_BW #define LPTE_RO LPTE_BR /* POWER ISA 3.0 Radix Table Definitions */ #define RPTE_VALID 0x8000000000000000ULL #define RPTE_LEAF 0x4000000000000000ULL /* is a PTE: always 1 */ #define RPTE_SW0 0x2000000000000000ULL #define RPTE_RPN_MASK 0x00FFFFFFFFFFF000ULL #define RPTE_RPN_SHIFT 12 #define RPTE_SW1 0x0000000000000800ULL #define RPTE_SW2 0x0000000000000400ULL #define RPTE_SW3 0x0000000000000200ULL #define RPTE_R 0x0000000000000100ULL #define RPTE_C 0x0000000000000080ULL #define RPTE_ATTR_MASK 0x0000000000000030ULL #define RPTE_ATTR_MEM 0x0000000000000000ULL /* PTE M */ #define RPTE_ATTR_SAO 0x0000000000000010ULL /* PTE WIM */ #define RPTE_ATTR_GUARDEDIO 0x0000000000000020ULL /* PTE IMG */ #define RPTE_ATTR_UNGUARDEDIO 0x0000000000000030ULL /* PTE IM */ #define RPTE_EAA_MASK 0x000000000000000FULL #define RPTE_EAA_P 0x0000000000000008ULL /* Supervisor only */ #define RPTE_EAA_R 0x0000000000000004ULL /* Read allowed */ #define RPTE_EAA_W 0x0000000000000002ULL /* Write (+read) */ #define RPTE_EAA_X 0x0000000000000001ULL /* Execute allowed */ #define RPDE_VALID RPTE_VALID #define RPDE_LEAF RPTE_LEAF /* is a PTE: always 0 */ #define RPDE_NLB_MASK 0x0FFFFFFFFFFFFF00ULL #define RPDE_NLB_SHIFT 8 #define RPDE_NLS_MASK 0x000000000000001FULL /* * Extract bits from address */ #define ADDR_SR_SHFT 28 #define ADDR_PIDX 0x0ffff000UL #define ADDR_PIDX_SHFT 12 #define ADDR_API_SHFT 22 #define ADDR_API_SHFT64 16 #define ADDR_POFF 0x00000fffUL /* * Bits in DSISR: */ #define DSISR_DIRECT 0x80000000 #define DSISR_NOTFOUND 0x40000000 #define DSISR_PROTECT 0x08000000 #define DSISR_INVRX 0x04000000 #define DSISR_STORE 0x02000000 #define DSISR_DABR 0x00400000 #define DSISR_SEGMENT 0x00200000 #define DSISR_EAR 0x00100000 /* * Bits in SRR1 on ISI: */ #define ISSRR1_NOTFOUND 0x40000000 #define ISSRR1_DIRECT 0x10000000 #define ISSRR1_PROTECT 0x08000000 #define ISSRR1_SEGMENT 0x00200000 #else /* BOOKE */ #include /* * Flags for pte_remove() routine. */ #define PTBL_HOLD 0x00000001 /* do not unhold ptbl pages */ #define PTBL_UNHOLD 0x00000002 /* unhold and attempt to free ptbl pages */ #define PTBL_HOLD_FLAG(pmap) (((pmap) == kernel_pmap) ? PTBL_HOLD : PTBL_UNHOLD) /* * Page Table Entry definitions and macros. * * RPN need only be 32-bit because Book-E has 36-bit addresses, and the smallest * page size is 4k (12-bit mask), so RPN can really fit into 24 bits. */ #ifndef LOCORE typedef uint64_t pte_t; #endif /* RPN mask, TLB0 4K pages */ #define PTE_PA_MASK PAGE_MASK #if defined(BOOKE_E500) /* PTE bits assigned to MAS2, MAS3 flags */ #define PTE_MAS2_SHIFT 19 #define PTE_W (MAS2_W << PTE_MAS2_SHIFT) #define PTE_I (MAS2_I << PTE_MAS2_SHIFT) #define PTE_M (MAS2_M << PTE_MAS2_SHIFT) #define PTE_G (MAS2_G << PTE_MAS2_SHIFT) #define PTE_MAS2_MASK (MAS2_G | MAS2_M | MAS2_I | MAS2_W) #define PTE_MAS3_SHIFT 2 #define PTE_UX (MAS3_UX << PTE_MAS3_SHIFT) #define PTE_SX (MAS3_SX << PTE_MAS3_SHIFT) #define PTE_UW (MAS3_UW << PTE_MAS3_SHIFT) #define PTE_SW (MAS3_SW << PTE_MAS3_SHIFT) #define PTE_UR (MAS3_UR << PTE_MAS3_SHIFT) #define PTE_SR (MAS3_SR << PTE_MAS3_SHIFT) #define PTE_MAS3_MASK ((MAS3_UX | MAS3_SX | MAS3_UW \ | MAS3_SW | MAS3_UR | MAS3_SR) << PTE_MAS3_SHIFT) #define PTE_PS_SHIFT 8 #define PTE_PS_4KB (2 << PTE_PS_SHIFT) -#elif defined(BOOKE_PPC4XX) - -#define PTE_WL1 TLB_WL1 -#define PTE_IL2I TLB_IL2I -#define PTE_IL2D TLB_IL2D - -#define PTE_W TLB_W -#define PTE_I TLB_I -#define PTE_M TLB_M -#define PTE_G TLB_G - -#define PTE_UX TLB_UX -#define PTE_SX TLB_SX -#define PTE_UW TLB_UW -#define PTE_SW TLB_SW -#define PTE_UR TLB_UR -#define PTE_SR TLB_SR - #endif /* Other PTE flags */ #define PTE_VALID 0x00000001 /* Valid */ #define PTE_MODIFIED 0x00001000 /* Modified */ #define PTE_WIRED 0x00002000 /* Wired */ #define PTE_MANAGED 0x00000002 /* Managed */ #define PTE_REFERENCED 0x00040000 /* Referenced */ /* * Page Table Entry definitions and macros. * * We use the hardware page table entry format: * * 63 24 23 19 18 17 14 13 12 11 8 7 6 5 4 3 2 1 0 * --------------------------------------------------------------- * ARPN(12:51) WIMGE R U0:U3 SW0 C PSIZE UX SX UW SW UR SR SW1 V * --------------------------------------------------------------- */ /* PTE fields. */ #define PTE_TSIZE_SHIFT (63-54) #define PTE_TSIZE_MASK 0x7 #define PTE_TSIZE_SHIFT_DIRECT (63-55) #define PTE_TSIZE_MASK_DIRECT 0xf #define PTE_PS_DIRECT(ps) (ps<> PTE_TSIZE_SHIFT) & PTE_TSIZE_MASK) #define PTE_TSIZE_DIRECT(pte) (int)((*pte >> PTE_TSIZE_SHIFT_DIRECT) & PTE_TSIZE_MASK_DIRECT) /* Macro argument must of pte_t type. */ #define PTE_ARPN_SHIFT 12 #define PTE_FLAGS_MASK 0x00ffffff #define PTE_RPN_FROM_PA(pa) (((pa) & ~PAGE_MASK) << PTE_ARPN_SHIFT) #define PTE_PA(pte) ((vm_paddr_t)(*pte >> PTE_ARPN_SHIFT) & ~PAGE_MASK) #define PTE_ISVALID(pte) ((*pte) & PTE_VALID) #define PTE_ISWIRED(pte) ((*pte) & PTE_WIRED) #define PTE_ISMANAGED(pte) ((*pte) & PTE_MANAGED) #define PTE_ISMODIFIED(pte) ((*pte) & PTE_MODIFIED) #define PTE_ISREFERENCED(pte) ((*pte) & PTE_REFERENCED) #endif /* BOOKE */ /* Book-E page table format, broken out for the generic pmap.h. */ #ifdef __powerpc64__ #include /* * The virtual address is: * * 4K page size * +-----+-----+-----+-------+-------------+-------------+----------------+ * | - |p2d#h| - | p2d#l | dir# | pte# | off in 4K page | * +-----+-----+-----+-------+-------------+-------------+----------------+ * 63 62 61 60 59 40 39 30 29 ^ 21 20 ^ 12 11 0 * | | * index in 1 page of pointers * * 1st level - pointers to page table directory (pp2d) * * pp2d consists of PP2D_NENTRIES entries, each being a pointer to * second level entity, i.e. the page table directory (pdir). */ #define PP2D_H_H 61 #define PP2D_H_L 60 #define PP2D_L_H 39 #define PP2D_L_L 30 /* >30 would work with no page table pool */ #define PP2D_SIZE (1 << PP2D_L_L) /* va range mapped by pp2d */ #define PP2D_L_SHIFT PP2D_L_L #define PP2D_L_NUM (PP2D_L_H-PP2D_L_L+1) #define PP2D_L_MASK ((1<> PP2D_H_SHIFT) & PP2D_H_MASK) | ((va >> PP2D_L_SHIFT) & PP2D_L_MASK)) #define PP2D_NENTRIES (1<<(PP2D_L_NUM+PP2D_H_NUM)) #define PP2D_ENTRY_SHIFT 3 /* log2 (sizeof(struct pte_entry **)) */ /* * 2nd level - page table directory (pdir) * * pdir consists of PDIR_NENTRIES entries, each being a pointer to * second level entity, i.e. the actual page table (ptbl). */ #define PDIR_H (PP2D_L_L-1) #define PDIR_L 21 #define PDIR_NUM (PDIR_H-PDIR_L+1) #define PDIR_SIZE (1 << PDIR_L) /* va range mapped by pdir */ #define PDIR_MASK ((1<> PDIR_SHIFT) & PDIR_MASK) #define PDIR_ENTRY_SHIFT 3 /* log2 (sizeof(struct pte_entry *)) */ #define PDIR_PAGES ((PDIR_NENTRIES * (1<> PTBL_SHIFT) & PTBL_MASK) #define PTBL_ENTRY_SHIFT 3 /* log2 (sizeof (struct pte_entry)) */ #define PTBL_PAGES ((PTBL_NENTRIES * (1<> PDIR_SHIFT) #define PDIR_ENTRY_SHIFT 2 /* entry size is 2^2 = 4 bytes */ /* * 2nd level - page table (ptbl) * * Page table covers 1024 page table entries. Page * table entry (pte) is 32 bit wide and defines mapping * for a single page. */ #define PTBL_SHIFT PAGE_SHIFT #define PTBL_SIZE PAGE_SIZE /* va range mapped by ptbl entry */ #define PTBL_MASK ((PDIR_SIZE - 1) & ~((1 << PAGE_SHIFT) - 1)) #define PTBL_NENTRIES 1024 /* number of pages mapped by ptbl */ /* Returns ptbl entry number for given va */ #define PTBL_IDX(va) (((va) & PTBL_MASK) >> PTBL_SHIFT) /* Size of ptbl in pages, 1024 entries, each sizeof(struct pte_entry). */ #define PTBL_PAGES 2 #define PTBL_ENTRY_SHIFT 3 /* entry size is 2^3 = 8 bytes */ #endif #endif /* _MACHINE_PTE_H_ */ Index: head/sys/powerpc/include/spr.h =================================================================== --- head/sys/powerpc/include/spr.h (revision 359057) +++ head/sys/powerpc/include/spr.h (revision 359058) @@ -1,916 +1,868 @@ /*- * SPDX-License-Identifier: BSD-2-Clause-FreeBSD * * Copyright (c) 2001 The NetBSD Foundation, Inc. * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE * POSSIBILITY OF SUCH DAMAGE. * * $NetBSD: spr.h,v 1.25 2002/08/14 15:38:40 matt Exp $ * $FreeBSD$ */ #ifndef _POWERPC_SPR_H_ #define _POWERPC_SPR_H_ #ifndef _LOCORE #define mtspr(reg, val) \ __asm __volatile("mtspr %0,%1" : : "K"(reg), "r"(val)) #define mfspr(reg) \ ( { register_t val; \ __asm __volatile("mfspr %0,%1" : "=r"(val) : "K"(reg)); \ val; } ) #ifndef __powerpc64__ /* The following routines allow manipulation of the full 64-bit width * of SPRs on 64 bit CPUs in bridge mode */ #define mtspr64(reg,valhi,vallo,scratch) \ __asm __volatile(" \ mfmsr %0; \ insrdi %0,%5,1,0; \ mtmsrd %0; \ isync; \ \ sld %1,%1,%4; \ or %1,%1,%2; \ mtspr %3,%1; \ srd %1,%1,%4; \ \ clrldi %0,%0,1; \ mtmsrd %0; \ isync;" \ : "=r"(scratch), "=r"(valhi) : "r"(vallo), "K"(reg), "r"(32), "r"(1)) #define mfspr64upper(reg,scratch) \ ( { register_t val; \ __asm __volatile(" \ mfmsr %0; \ insrdi %0,%4,1,0; \ mtmsrd %0; \ isync; \ \ mfspr %1,%2; \ srd %1,%1,%3; \ \ clrldi %0,%0,1; \ mtmsrd %0; \ isync;" \ : "=r"(scratch), "=r"(val) : "K"(reg), "r"(32), "r"(1)); \ val; } ) #endif #endif /* _LOCORE */ /* * Special Purpose Register declarations. * * The first column in the comments indicates which PowerPC * architectures the SPR is valid on - 4 for 4xx series, * 6 for 6xx/7xx series and 8 for 8xx and 8xxx series. */ #define SPR_MQ 0x000 /* .6. 601 MQ register */ #define SPR_XER 0x001 /* 468 Fixed Point Exception Register */ #define SPR_DSCR 0x003 /* .6. Data Stream Control Register (Unprivileged) */ #define SPR_RTCU_R 0x004 /* .6. 601 RTC Upper - Read */ #define SPR_RTCL_R 0x005 /* .6. 601 RTC Lower - Read */ #define SPR_LR 0x008 /* 468 Link Register */ #define SPR_CTR 0x009 /* 468 Count Register */ #define SPR_DSCRP 0x011 /* Data Stream Control Register (Privileged) */ #define SPR_DSISR 0x012 /* .68 DSI exception source */ #define DSISR_DIRECT 0x80000000 /* Direct-store error exception */ #define DSISR_NOTFOUND 0x40000000 /* Translation not found */ #define DSISR_PROTECT 0x08000000 /* Memory access not permitted */ #define DSISR_INVRX 0x04000000 /* Reserve-indexed insn direct-store access */ #define DSISR_STORE 0x02000000 /* Store operation */ #define DSISR_DABR 0x00400000 /* DABR match */ #define DSISR_SEGMENT 0x00200000 /* XXX; not in 6xx PEM */ #define DSISR_EAR 0x00100000 /* eciwx/ecowx && EAR[E] == 0 */ #define SPR_DAR 0x013 /* .68 Data Address Register */ #define SPR_RTCU_W 0x014 /* .6. 601 RTC Upper - Write */ #define SPR_RTCL_W 0x015 /* .6. 601 RTC Lower - Write */ #define SPR_DEC 0x016 /* .68 DECrementer register */ #define SPR_SDR1 0x019 /* .68 Page table base address register */ #define SPR_SRR0 0x01a /* 468 Save/Restore Register 0 */ #define SPR_SRR1 0x01b /* 468 Save/Restore Register 1 */ #define SRR1_ISI_PFAULT 0x40000000 /* ISI page not found */ #define SRR1_ISI_NOEXECUTE 0x10000000 /* Memory marked no-execute */ #define SRR1_ISI_PP 0x08000000 /* PP bits forbid access */ #define SPR_DECAR 0x036 /* ..8 Decrementer auto reload */ #define SPR_EIE 0x050 /* ..8 Exception Interrupt ??? */ #define SPR_EID 0x051 /* ..8 Exception Interrupt ??? */ #define SPR_NRI 0x052 /* ..8 Exception Interrupt ??? */ #define SPR_FSCR 0x099 /* Facility Status and Control Register */ #define FSCR_IC_MASK 0xFF00000000000000ULL /* FSCR[0:7] is Interrupt Cause */ #define FSCR_IC_FP 0x0000000000000000ULL /* FP unavailable */ #define FSCR_IC_VSX 0x0100000000000000ULL /* VSX unavailable */ #define FSCR_IC_DSCR 0x0200000000000000ULL /* Access to the DSCR at SPRs 3 or 17 */ #define FSCR_IC_PM 0x0300000000000000ULL /* Read or write access of a Performance Monitor SPR in group A */ #define FSCR_IC_BHRB 0x0400000000000000ULL /* Execution of a BHRB Instruction */ #define FSCR_IC_HTM 0x0500000000000000ULL /* Access to a Transactional Memory */ /* Reserved 0x0600000000000000ULL */ #define FSCR_IC_EBB 0x0700000000000000ULL /* Access to Event-Based Branch */ #define FSCR_IC_TAR 0x0800000000000000ULL /* Access to Target Address Register */ #define FSCR_IC_STOP 0x0900000000000000ULL /* Access to the 'stop' instruction in privileged non-hypervisor state */ #define FSCR_IC_MSG 0x0A00000000000000ULL /* Access to 'msgsndp' or 'msgclrp' instructions */ #define FSCR_IC_LM 0x0A00000000000000ULL /* Access to load monitored facility */ #define FSCR_IC_SCV 0x0C00000000000000ULL /* Execution of a 'scv' instruction */ #define FSCR_SCV 0x0000000000001000 /* scv instruction available */ #define FSCR_LM 0x0000000000000800 /* Load monitored facilities available */ #define FSCR_MSGP 0x0000000000000400 /* msgsndp and SPRs available */ #define FSCR_TAR 0x0000000000000100 /* TAR register available */ #define FSCR_EBB 0x0000000000000080 /* Event-based branch available */ #define FSCR_DSCR 0x0000000000000004 /* DSCR available in PR state */ #define SPR_DPDES 0x0b0 /* .6. Directed Privileged Doorbell Exception State Register */ -#define SPR_USPRG0 0x100 /* 4.. User SPR General 0 */ +#define SPR_USPRG0 0x100 /* 4.8 User SPR General 0 */ #define SPR_VRSAVE 0x100 /* .6. AltiVec VRSAVE */ #define SPR_SPRG0 0x110 /* 468 SPR General 0 */ #define SPR_SPRG1 0x111 /* 468 SPR General 1 */ #define SPR_SPRG2 0x112 /* 468 SPR General 2 */ #define SPR_SPRG3 0x113 /* 468 SPR General 3 */ -#define SPR_SPRG4 0x114 /* 4.. SPR General 4 */ -#define SPR_SPRG5 0x115 /* 4.. SPR General 5 */ -#define SPR_SPRG6 0x116 /* 4.. SPR General 6 */ -#define SPR_SPRG7 0x117 /* 4.. SPR General 7 */ +#define SPR_SPRG4 0x114 /* 4.8 SPR General 4 */ +#define SPR_SPRG5 0x115 /* 4.8 SPR General 5 */ +#define SPR_SPRG6 0x116 /* 4.8 SPR General 6 */ +#define SPR_SPRG7 0x117 /* 4.8 SPR General 7 */ #define SPR_SCOMC 0x114 /* ... SCOM Address Register (970) */ #define SPR_SCOMD 0x115 /* ... SCOM Data Register (970) */ #define SPR_ASR 0x118 /* ... Address Space Register (PPC64) */ #define SPR_EAR 0x11a /* .68 External Access Register */ #define SPR_PVR 0x11f /* 468 Processor Version Register */ #define MPC601 0x0001 #define MPC603 0x0003 #define MPC604 0x0004 #define MPC602 0x0005 #define MPC603e 0x0006 #define MPC603ev 0x0007 #define MPC750 0x0008 #define MPC750CL 0x7000 /* Nintendo Wii's Broadway */ #define MPC604ev 0x0009 #define MPC7400 0x000c #define MPC620 0x0014 #define IBM403 0x0020 #define IBM401A1 0x0021 #define IBM401B2 0x0022 #define IBM401C2 0x0023 #define IBM401D2 0x0024 #define IBM401E2 0x0025 #define IBM401F2 0x0026 #define IBM401G2 0x0027 #define IBMRS64II 0x0033 #define IBMRS64III 0x0034 #define IBMPOWER4 0x0035 #define IBMRS64III_2 0x0036 #define IBMRS64IV 0x0037 #define IBMPOWER4PLUS 0x0038 #define IBM970 0x0039 #define IBMPOWER5 0x003a #define IBMPOWER5PLUS 0x003b #define IBM970FX 0x003c #define IBMPOWER6 0x003e #define IBMPOWER7 0x003f #define IBMPOWER3 0x0040 #define IBMPOWER3PLUS 0x0041 #define IBM970MP 0x0044 #define IBM970GX 0x0045 #define IBMPOWERPCA2 0x0049 #define IBMPOWER7PLUS 0x004a #define IBMPOWER8E 0x004b #define IBMPOWER8NVL 0x004c #define IBMPOWER8 0x004d #define IBMPOWER9 0x004e #define MPC860 0x0050 #define IBMCELLBE 0x0070 #define MPC8240 0x0081 #define PA6T 0x0090 #define IBM405GP 0x4011 #define IBM405L 0x4161 #define IBM750FX 0x7000 #define MPC745X_P(v) ((v & 0xFFF8) == 0x8000) #define MPC7450 0x8000 #define MPC7455 0x8001 #define MPC7457 0x8002 #define MPC7447A 0x8003 #define MPC7448 0x8004 #define MPC7410 0x800c #define MPC8245 0x8081 #define FSL_E500v1 0x8020 #define FSL_E500v2 0x8021 #define FSL_E500mc 0x8023 #define FSL_E5500 0x8024 #define FSL_E6500 0x8040 #define FSL_E300C1 0x8083 #define FSL_E300C2 0x8084 #define FSL_E300C3 0x8085 #define FSL_E300C4 0x8086 #define LPCR_PECE_WAKESET (LPCR_PECE_EXT | LPCR_PECE_DECR | LPCR_PECE_ME) +#define SPR_DBSR 0x130 /* ..8 Debug Status Register */ +#define DBSR_IDE 0x80000000 /* Imprecise debug event. */ +#define DBSR_UDE 0x40000000 /* Unconditional debug event. */ +#define DBSR_MRR 0x30000000 /* Most recent Reset (mask). */ +#define DBSR_ICMP 0x08000000 /* Instr. complete debug event. */ +#define DBSR_BRT 0x04000000 /* Branch taken debug event. */ +#define DBSR_IRPT 0x02000000 /* Interrupt taken debug event. */ +#define DBSR_TRAP 0x01000000 /* Trap instr. debug event. */ +#define DBSR_IAC1 0x00800000 /* Instr. address compare #1. */ +#define DBSR_IAC2 0x00400000 /* Instr. address compare #2. */ +#define DBSR_IAC3 0x00200000 /* Instr. address compare #3. */ +#define DBSR_IAC4 0x00100000 /* Instr. address compare #4. */ +#define DBSR_DAC1R 0x00080000 /* Data addr. read compare #1. */ +#define DBSR_DAC1W 0x00040000 /* Data addr. write compare #1. */ +#define DBSR_DAC2R 0x00020000 /* Data addr. read compare #2. */ +#define DBSR_DAC2W 0x00010000 /* Data addr. write compare #2. */ +#define DBSR_RET 0x00008000 /* Return debug event. */ #define SPR_EPCR 0x133 #define EPCR_EXTGS 0x80000000 #define EPCR_DTLBGS 0x40000000 #define EPCR_ITLBGS 0x20000000 #define EPCR_DSIGS 0x10000000 #define EPCR_ISIGS 0x08000000 #define EPCR_DUVGS 0x04000000 #define EPCR_ICM 0x02000000 #define EPCR_GICMGS 0x01000000 #define EPCR_DGTMI 0x00800000 #define EPCR_DMIUH 0x00400000 #define EPCR_PMGS 0x00200000 +#define SPR_DBCR0 0x134 /* ..8 Debug Control Register 0 */ +#define SPR_DBCR1 0x135 /* ..8 Debug Control Register 1 */ +#define SPR_IAC1 0x138 /* ..8 Instruction Address Compare 1 */ +#define SPR_IAC2 0x139 /* ..8 Instruction Address Compare 2 */ +#define SPR_IAC3 0x13a /* ..8 Instruction Address Compare 3 */ +#define SPR_IAC4 0x13b /* ..8 Instruction Address Compare 4 */ #define SPR_HSRR0 0x13a #define SPR_HSRR1 0x13b -#define SPR_LPCR 0x13e /* Logical Partitioning Control */ +#define SPR_DAC1 0x13c /* ..8 Data Address Compare 1 */ +#define SPR_DAC2 0x13d /* ..8 Data Address Compare 2 */ +#define SPR_DVC1 0x13e /* ..8 Data Value Compare 1 */ +#define SPR_DVC2 0x13f /* ..8 Data Value Compare 2 */ + +#define SPR_LPCR 0x13e /* .6. Logical Partitioning Control */ #define LPCR_LPES 0x008 /* Bit 60 */ #define LPCR_HVICE 0x002 /* Hypervisor Virtualization Interrupt (Arch 3.0) */ #define LPCR_PECE_DRBL (1ULL << 16) /* Directed Privileged Doorbell */ #define LPCR_PECE_HDRBL (1ULL << 15) /* Directed Hypervisor Doorbell */ #define LPCR_PECE_EXT (1ULL << 14) /* External exceptions */ #define LPCR_PECE_DECR (1ULL << 13) /* Decrementer exceptions */ #define LPCR_PECE_ME (1ULL << 12) /* Machine Check and Hypervisor */ /* Maintenance exceptions */ -#define SPR_LPID 0x13f /* Logical Partitioning Control */ +#define SPR_LPID 0x13f /* .6. Logical Partitioning Control */ #define SPR_HMER 0x150 /* Hypervisor Maintenance Exception Register */ #define SPR_HMEER 0x151 /* Hypervisor Maintenance Exception Enable Register */ #define SPR_TIR 0x1be /* .6. Thread Identification Register */ #define SPR_PTCR 0x1d0 /* Partition Table Control Register */ #define SPR_SPEFSCR 0x200 /* ..8 Signal Processing Engine FSCR. */ #define SPEFSCR_SOVH 0x80000000 #define SPEFSCR_OVH 0x40000000 #define SPEFSCR_FGH 0x20000000 #define SPEFSCR_FXH 0x10000000 #define SPEFSCR_FINVH 0x08000000 #define SPEFSCR_FDBZH 0x04000000 #define SPEFSCR_FUNFH 0x02000000 #define SPEFSCR_FOVFH 0x01000000 #define SPEFSCR_FINXS 0x00200000 #define SPEFSCR_FINVS 0x00100000 #define SPEFSCR_FDBZS 0x00080000 #define SPEFSCR_FUNFS 0x00040000 #define SPEFSCR_FOVFS 0x00020000 #define SPEFSCR_SOV 0x00008000 #define SPEFSCR_OV 0x00004000 #define SPEFSCR_FG 0x00002000 #define SPEFSCR_FX 0x00001000 #define SPEFSCR_FINV 0x00000800 #define SPEFSCR_FDBZ 0x00000400 #define SPEFSCR_FUNF 0x00000200 #define SPEFSCR_FOVF 0x00000100 #define SPEFSCR_FINXE 0x00000040 #define SPEFSCR_FINVE 0x00000020 #define SPEFSCR_FDBZE 0x00000010 #define SPEFSCR_FUNFE 0x00000008 #define SPEFSCR_FOVFE 0x00000004 #define SPEFSCR_FRMC_M 0x00000003 #define SPR_IBAT0U 0x210 /* .6. Instruction BAT Reg 0 Upper */ #define SPR_IBAT0L 0x211 /* .6. Instruction BAT Reg 0 Lower */ #define SPR_IBAT1U 0x212 /* .6. Instruction BAT Reg 1 Upper */ #define SPR_IBAT1L 0x213 /* .6. Instruction BAT Reg 1 Lower */ #define SPR_IBAT2U 0x214 /* .6. Instruction BAT Reg 2 Upper */ #define SPR_IBAT2L 0x215 /* .6. Instruction BAT Reg 2 Lower */ #define SPR_IBAT3U 0x216 /* .6. Instruction BAT Reg 3 Upper */ #define SPR_IBAT3L 0x217 /* .6. Instruction BAT Reg 3 Lower */ #define SPR_DBAT0U 0x218 /* .6. Data BAT Reg 0 Upper */ #define SPR_DBAT0L 0x219 /* .6. Data BAT Reg 0 Lower */ #define SPR_DBAT1U 0x21a /* .6. Data BAT Reg 1 Upper */ #define SPR_DBAT1L 0x21b /* .6. Data BAT Reg 1 Lower */ #define SPR_DBAT2U 0x21c /* .6. Data BAT Reg 2 Upper */ #define SPR_DBAT2L 0x21d /* .6. Data BAT Reg 2 Lower */ #define SPR_DBAT3U 0x21e /* .6. Data BAT Reg 3 Upper */ #define SPR_DBAT3L 0x21f /* .6. Data BAT Reg 3 Lower */ #define SPR_IC_CST 0x230 /* ..8 Instruction Cache CSR */ #define IC_CST_IEN 0x80000000 /* I cache is ENabled (RO) */ #define IC_CST_CMD_INVALL 0x0c000000 /* I cache invalidate all */ #define IC_CST_CMD_UNLOCKALL 0x0a000000 /* I cache unlock all */ #define IC_CST_CMD_UNLOCK 0x08000000 /* I cache unlock block */ #define IC_CST_CMD_LOADLOCK 0x06000000 /* I cache load & lock block */ #define IC_CST_CMD_DISABLE 0x04000000 /* I cache disable */ #define IC_CST_CMD_ENABLE 0x02000000 /* I cache enable */ #define IC_CST_CCER1 0x00200000 /* I cache error type 1 (RO) */ #define IC_CST_CCER2 0x00100000 /* I cache error type 2 (RO) */ #define IC_CST_CCER3 0x00080000 /* I cache error type 3 (RO) */ #define SPR_IBAT4U 0x230 /* .6. Instruction BAT Reg 4 Upper */ #define SPR_IC_ADR 0x231 /* ..8 Instruction Cache Address */ #define SPR_IBAT4L 0x231 /* .6. Instruction BAT Reg 4 Lower */ #define SPR_IC_DAT 0x232 /* ..8 Instruction Cache Data */ #define SPR_IBAT5U 0x232 /* .6. Instruction BAT Reg 5 Upper */ #define SPR_IBAT5L 0x233 /* .6. Instruction BAT Reg 5 Lower */ #define SPR_IBAT6U 0x234 /* .6. Instruction BAT Reg 6 Upper */ #define SPR_IBAT6L 0x235 /* .6. Instruction BAT Reg 6 Lower */ #define SPR_IBAT7U 0x236 /* .6. Instruction BAT Reg 7 Upper */ #define SPR_IBAT7L 0x237 /* .6. Instruction BAT Reg 7 Lower */ #define SPR_DC_CST 0x230 /* ..8 Data Cache CSR */ #define DC_CST_DEN 0x80000000 /* D cache ENabled (RO) */ #define DC_CST_DFWT 0x40000000 /* D cache Force Write-Thru (RO) */ #define DC_CST_LES 0x20000000 /* D cache Little Endian Swap (RO) */ #define DC_CST_CMD_FLUSH 0x0e000000 /* D cache invalidate all */ #define DC_CST_CMD_INVALL 0x0c000000 /* D cache invalidate all */ #define DC_CST_CMD_UNLOCKALL 0x0a000000 /* D cache unlock all */ #define DC_CST_CMD_UNLOCK 0x08000000 /* D cache unlock block */ #define DC_CST_CMD_CLRLESWAP 0x07000000 /* D cache clr little-endian swap */ #define DC_CST_CMD_LOADLOCK 0x06000000 /* D cache load & lock block */ #define DC_CST_CMD_SETLESWAP 0x05000000 /* D cache set little-endian swap */ #define DC_CST_CMD_DISABLE 0x04000000 /* D cache disable */ #define DC_CST_CMD_CLRFWT 0x03000000 /* D cache clear forced write-thru */ #define DC_CST_CMD_ENABLE 0x02000000 /* D cache enable */ #define DC_CST_CMD_SETFWT 0x01000000 /* D cache set forced write-thru */ #define DC_CST_CCER1 0x00200000 /* D cache error type 1 (RO) */ #define DC_CST_CCER2 0x00100000 /* D cache error type 2 (RO) */ #define DC_CST_CCER3 0x00080000 /* D cache error type 3 (RO) */ #define SPR_DBAT4U 0x238 /* .6. Data BAT Reg 4 Upper */ #define SPR_DC_ADR 0x231 /* ..8 Data Cache Address */ #define SPR_DBAT4L 0x239 /* .6. Data BAT Reg 4 Lower */ #define SPR_DC_DAT 0x232 /* ..8 Data Cache Data */ #define SPR_DBAT5U 0x23a /* .6. Data BAT Reg 5 Upper */ #define SPR_DBAT5L 0x23b /* .6. Data BAT Reg 5 Lower */ #define SPR_DBAT6U 0x23c /* .6. Data BAT Reg 6 Upper */ #define SPR_DBAT6L 0x23d /* .6. Data BAT Reg 6 Lower */ #define SPR_DBAT7U 0x23e /* .6. Data BAT Reg 7 Upper */ #define SPR_DBAT7L 0x23f /* .6. Data BAT Reg 7 Lower */ #define SPR_SPRG8 0x25c /* ..8 SPR General 8 */ #define SPR_MI_CTR 0x310 /* ..8 IMMU control */ #define Mx_CTR_GPM 0x80000000 /* Group Protection Mode */ #define Mx_CTR_PPM 0x40000000 /* Page Protection Mode */ #define Mx_CTR_CIDEF 0x20000000 /* Cache-Inhibit DEFault */ #define MD_CTR_WTDEF 0x20000000 /* Write-Through DEFault */ #define Mx_CTR_RSV4 0x08000000 /* Reserve 4 TLB entries */ #define MD_CTR_TWAM 0x04000000 /* TableWalk Assist Mode */ #define Mx_CTR_PPCS 0x02000000 /* Priv/user state compare mode */ #define Mx_CTR_TLB_INDX 0x000001f0 /* TLB index mask */ #define Mx_CTR_TLB_INDX_BITPOS 8 /* TLB index shift */ #define SPR_MI_AP 0x312 /* ..8 IMMU access protection */ #define Mx_GP_SUPER(n) (0 << (2*(15-(n)))) /* access is supervisor */ #define Mx_GP_PAGE (1 << (2*(15-(n)))) /* access is page protect */ #define Mx_GP_SWAPPED (2 << (2*(15-(n)))) /* access is swapped */ #define Mx_GP_USER (3 << (2*(15-(n)))) /* access is user */ #define SPR_MI_EPN 0x313 /* ..8 IMMU effective number */ #define Mx_EPN_EPN 0xfffff000 /* Effective Page Number mask */ #define Mx_EPN_EV 0x00000020 /* Entry Valid */ #define Mx_EPN_ASID 0x0000000f /* Address Space ID */ #define SPR_MI_TWC 0x315 /* ..8 IMMU tablewalk control */ #define MD_TWC_L2TB 0xfffff000 /* Level-2 Tablewalk Base */ #define Mx_TWC_APG 0x000001e0 /* Access Protection Group */ #define Mx_TWC_G 0x00000010 /* Guarded memory */ #define Mx_TWC_PS 0x0000000c /* Page Size (L1) */ #define MD_TWC_WT 0x00000002 /* Write-Through */ #define Mx_TWC_V 0x00000001 /* Entry Valid */ #define SPR_MI_RPN 0x316 /* ..8 IMMU real (phys) page number */ #define Mx_RPN_RPN 0xfffff000 /* Real Page Number */ #define Mx_RPN_PP 0x00000ff0 /* Page Protection */ #define Mx_RPN_SPS 0x00000008 /* Small Page Size */ #define Mx_RPN_SH 0x00000004 /* SHared page */ #define Mx_RPN_CI 0x00000002 /* Cache Inhibit */ #define Mx_RPN_V 0x00000001 /* Valid */ #define SPR_MD_CTR 0x318 /* ..8 DMMU control */ #define SPR_M_CASID 0x319 /* ..8 CASID */ #define M_CASID 0x0000000f /* Current AS Id */ #define SPR_MD_AP 0x31a /* ..8 DMMU access protection */ #define SPR_MD_EPN 0x31b /* ..8 DMMU effective number */ #define SPR_970MMCR0 0x31b /* ... Monitor Mode Control Register 0 (PPC 970) */ #define SPR_970MMCR0_PMC1SEL(x) ((x) << 8) /* PMC1 selector (970) */ #define SPR_970MMCR0_PMC2SEL(x) ((x) << 1) /* PMC2 selector (970) */ #define SPR_970MMCR1 0x31e /* ... Monitor Mode Control Register 1 (PPC 970) */ #define SPR_970MMCR1_PMC3SEL(x) (((x) & 0x1f) << 27) /* PMC 3 selector */ #define SPR_970MMCR1_PMC4SEL(x) (((x) & 0x1f) << 22) /* PMC 4 selector */ #define SPR_970MMCR1_PMC5SEL(x) (((x) & 0x1f) << 17) /* PMC 5 selector */ #define SPR_970MMCR1_PMC6SEL(x) (((x) & 0x1f) << 12) /* PMC 6 selector */ #define SPR_970MMCR1_PMC7SEL(x) (((x) & 0x1f) << 7) /* PMC 7 selector */ #define SPR_970MMCR1_PMC8SEL(x) (((x) & 0x1f) << 2) /* PMC 8 selector */ #define SPR_970MMCRA 0x312 /* ... Monitor Mode Control Register 2 (PPC 970) */ #define SPR_970PMC1 0x313 /* ... PMC 1 */ #define SPR_970PMC2 0x314 /* ... PMC 2 */ #define SPR_970PMC3 0x315 /* ... PMC 3 */ #define SPR_970PMC4 0x316 /* ... PMC 4 */ #define SPR_970PMC5 0x317 /* ... PMC 5 */ #define SPR_970PMC6 0x318 /* ... PMC 6 */ #define SPR_970PMC7 0x319 /* ... PMC 7 */ #define SPR_970PMC8 0x31a /* ... PMC 8 */ #define SPR_M_TWB 0x31c /* ..8 MMU tablewalk base */ #define M_TWB_L1TB 0xfffff000 /* level-1 translation base */ #define M_TWB_L1INDX 0x00000ffc /* level-1 index */ #define SPR_MD_TWC 0x31d /* ..8 DMMU tablewalk control */ #define SPR_MD_RPN 0x31e /* ..8 DMMU real (phys) page number */ #define SPR_MD_TW 0x31f /* ..8 MMU tablewalk scratch */ #define SPR_BESCRS 0x320 /* .6. Branch Event Status and Control Set Register */ #define SPR_BESCRSU 0x321 /* .6. Branch Event Status and Control Set Register (upper 32-bit) */ #define SPR_BESCRR 0x322 /* .6. Branch Event Status and Control Reset Register */ #define SPR_BESCRRU 0x323 /* .6. Branch Event Status and Control Register (upper 32-bit) */ #define SPR_EBBHR 0x324 /* .6. Event-based Branch Handler Register */ #define SPR_EBBRR 0x325 /* .6. Event-based Branch Return Register */ #define SPR_BESCR 0x326 /* .6. Branch Event Status and Control Register */ #define SPR_LMRR 0x32d /* .6. Load Monitored Region Register */ #define SPR_LMSER 0x32e /* .6. Load Monitored Section Enable Register */ #define SPR_TAR 0x32f /* .6. Branch Target Address Register */ #define SPR_MI_CAM 0x330 /* ..8 IMMU CAM entry read */ #define SPR_MI_RAM0 0x331 /* ..8 IMMU RAM entry read reg 0 */ #define SPR_MI_RAM1 0x332 /* ..8 IMMU RAM entry read reg 1 */ #define SPR_MD_CAM 0x338 /* ..8 IMMU CAM entry read */ #define SPR_MD_RAM0 0x339 /* ..8 IMMU RAM entry read reg 0 */ #define SPR_MD_RAM1 0x33a /* ..8 IMMU RAM entry read reg 1 */ #define SPR_PSSCR 0x357 /* Processor Stop Status and Control Register (ISA 3.0) */ #define PSSCR_PLS_S 60 #define PSSCR_PLS_M (0xf << PSSCR_PLS_S) #define PSSCR_SD (1 << 22) #define PSSCR_ESL (1 << 21) #define PSSCR_EC (1 << 20) #define PSSCR_PSLL_S 16 #define PSSCR_PSLL_M (0xf << PSSCR_PSLL_S) #define PSSCR_TR_S 8 #define PSSCR_TR_M (0x3 << PSSCR_TR_S) #define PSSCR_MTL_S 4 #define PSSCR_MTL_M (0xf << PSSCR_MTL_S) #define PSSCR_RL_S 0 #define PSSCR_RL_M (0xf << PSSCR_RL_S) #define SPR_PMCR 0x374 /* Processor Management Control Register */ #define SPR_UMMCR2 0x3a0 /* .6. User Monitor Mode Control Register 2 */ #define SPR_UMMCR0 0x3a8 /* .6. User Monitor Mode Control Register 0 */ #define SPR_USIA 0x3ab /* .6. User Sampled Instruction Address */ #define SPR_UMMCR1 0x3ac /* .6. User Monitor Mode Control Register 1 */ -#define SPR_ZPR 0x3b0 /* 4.. Zone Protection Register */ #define SPR_MMCR2 0x3b0 /* .6. Monitor Mode Control Register 2 */ #define SPR_MMCR2_THRESHMULT_32 0x80000000 /* Multiply MMCR0 threshold by 32 */ #define SPR_MMCR2_THRESHMULT_2 0x00000000 /* Multiply MMCR0 threshold by 2 */ -#define SPR_PID 0x3b1 /* 4.. Process ID */ #define SPR_PMC5 0x3b1 /* .6. Performance Counter Register 5 */ #define SPR_PMC6 0x3b2 /* .6. Performance Counter Register 6 */ -#define SPR_CCR0 0x3b3 /* 4.. Core Configuration Register 0 */ -#define SPR_IAC3 0x3b4 /* 4.. Instruction Address Compare 3 */ -#define SPR_IAC4 0x3b5 /* 4.. Instruction Address Compare 4 */ -#define SPR_DVC1 0x3b6 /* 4.. Data Value Compare 1 */ -#define SPR_DVC2 0x3b7 /* 4.. Data Value Compare 2 */ #define SPR_MMCR0 0x3b8 /* .6. Monitor Mode Control Register 0 */ #define SPR_MMCR0_FC 0x80000000 /* Freeze counters */ #define SPR_MMCR0_FCS 0x40000000 /* Freeze counters in supervisor mode */ #define SPR_MMCR0_FCP 0x20000000 /* Freeze counters in user mode */ #define SPR_MMCR0_FCM1 0x10000000 /* Freeze counters when mark=1 */ #define SPR_MMCR0_FCM0 0x08000000 /* Freeze counters when mark=0 */ #define SPR_MMCR0_PMXE 0x04000000 /* Enable PM interrupt */ #define SPR_MMCR0_FCECE 0x02000000 /* Freeze counters after event */ #define SPR_MMCR0_TBSEL_15 0x01800000 /* Count bit 15 of TBL */ #define SPR_MMCR0_TBSEL_19 0x01000000 /* Count bit 19 of TBL */ #define SPR_MMCR0_TBSEL_23 0x00800000 /* Count bit 23 of TBL */ #define SPR_MMCR0_TBSEL_31 0x00000000 /* Count bit 31 of TBL */ #define SPR_MMCR0_TBEE 0x00400000 /* Time-base event enable */ #define SPR_MMCRO_THRESHOLD(x) ((x) << 16) /* Threshold value */ #define SPR_MMCR0_PMC1CE 0x00008000 /* PMC1 condition enable */ #define SPR_MMCR0_PMCNCE 0x00004000 /* PMCn condition enable */ #define SPR_MMCR0_TRIGGER 0x00002000 /* Trigger */ #define SPR_MMCR0_PMC1SEL(x) (((x) & 0x3f) << 6) /* PMC1 selector */ #define SPR_MMCR0_PMC2SEL(x) (((x) & 0x3f) << 0) /* PMC2 selector */ -#define SPR_SGR 0x3b9 /* 4.. Storage Guarded Register */ #define SPR_PMC1 0x3b9 /* .6. Performance Counter Register 1 */ -#define SPR_DCWR 0x3ba /* 4.. Data Cache Write-through Register */ #define SPR_PMC2 0x3ba /* .6. Performance Counter Register 2 */ -#define SPR_SLER 0x3bb /* 4.. Storage Little Endian Register */ #define SPR_SIA 0x3bb /* .6. Sampled Instruction Address */ #define SPR_MMCR1 0x3bc /* .6. Monitor Mode Control Register 2 */ #define SPR_MMCR1_PMC3SEL(x) (((x) & 0x1f) << 27) /* PMC 3 selector */ #define SPR_MMCR1_PMC4SEL(x) (((x) & 0x1f) << 22) /* PMC 4 selector */ #define SPR_MMCR1_PMC5SEL(x) (((x) & 0x1f) << 17) /* PMC 5 selector */ #define SPR_MMCR1_PMC6SEL(x) (((x) & 0x3f) << 11) /* PMC 6 selector */ -#define SPR_SU0R 0x3bc /* 4.. Storage User-defined 0 Register */ #define SPR_PMC3 0x3bd /* .6. Performance Counter Register 3 */ #define SPR_PMC4 0x3be /* .6. Performance Counter Register 4 */ #define SPR_DMISS 0x3d0 /* .68 Data TLB Miss Address Register */ #define SPR_DCMP 0x3d1 /* .68 Data TLB Compare Register */ #define SPR_HASH1 0x3d2 /* .68 Primary Hash Address Register */ -#define SPR_ICDBDR 0x3d3 /* 4.. Instruction Cache Debug Data Register */ #define SPR_HASH2 0x3d3 /* .68 Secondary Hash Address Register */ #define SPR_IMISS 0x3d4 /* .68 Instruction TLB Miss Address Register */ #define SPR_TLBMISS 0x3d4 /* .6. TLB Miss Address Register */ -#if defined(BOOKE_PPC4XX) -#define SPR_DEAR 0x3d5 /* 4.. Data Error Address Register */ -#else #define SPR_DEAR 0x03d /* ..8 Data Exception Address Register */ -#endif #define SPR_ICMP 0x3d5 /* .68 Instruction TLB Compare Register */ #define SPR_PTEHI 0x3d5 /* .6. Instruction TLB Compare Register */ -#define SPR_EVPR 0x3d6 /* 4.. Exception Vector Prefix Register */ #define SPR_RPA 0x3d6 /* .68 Required Physical Address Register */ #define SPR_PTELO 0x3d6 /* .6. Required Physical Address Register */ #define SPR_TSR 0x150 /* ..8 Timer Status Register */ #define SPR_TCR 0x154 /* ..8 Timer Control Register */ #define TSR_ENW 0x80000000 /* Enable Next Watchdog */ #define TSR_WIS 0x40000000 /* Watchdog Interrupt Status */ #define TSR_WRS_MASK 0x30000000 /* Watchdog Reset Status */ #define TSR_WRS_NONE 0x00000000 /* No watchdog reset has occurred */ #define TSR_WRS_CORE 0x10000000 /* Core reset was forced by the watchdog */ #define TSR_WRS_CHIP 0x20000000 /* Chip reset was forced by the watchdog */ #define TSR_WRS_SYSTEM 0x30000000 /* System reset was forced by the watchdog */ #define TSR_PIS 0x08000000 /* PIT Interrupt Status */ #define TSR_DIS 0x08000000 /* Decrementer Interrupt Status */ #define TSR_FIS 0x04000000 /* FIT Interrupt Status */ #define TCR_WP_MASK 0xc0000000 /* Watchdog Period mask */ #define TCR_WP_2_17 0x00000000 /* 2**17 clocks */ #define TCR_WP_2_21 0x40000000 /* 2**21 clocks */ #define TCR_WP_2_25 0x80000000 /* 2**25 clocks */ #define TCR_WP_2_29 0xc0000000 /* 2**29 clocks */ #define TCR_WRC_MASK 0x30000000 /* Watchdog Reset Control mask */ #define TCR_WRC_NONE 0x00000000 /* No watchdog reset */ #define TCR_WRC_CORE 0x10000000 /* Core reset */ #define TCR_WRC_CHIP 0x20000000 /* Chip reset */ #define TCR_WRC_SYSTEM 0x30000000 /* System reset */ #define TCR_WIE 0x08000000 /* Watchdog Interrupt Enable */ #define TCR_PIE 0x04000000 /* PIT Interrupt Enable */ #define TCR_DIE 0x04000000 /* Pecrementer Interrupt Enable */ #define TCR_FP_MASK 0x03000000 /* FIT Period */ #define TCR_FP_2_9 0x00000000 /* 2**9 clocks */ #define TCR_FP_2_13 0x01000000 /* 2**13 clocks */ #define TCR_FP_2_17 0x02000000 /* 2**17 clocks */ #define TCR_FP_2_21 0x03000000 /* 2**21 clocks */ #define TCR_FIE 0x00800000 /* FIT Interrupt Enable */ #define TCR_ARE 0x00400000 /* Auto Reload Enable */ -#define SPR_PIT 0x3db /* 4.. Programmable Interval Timer */ -#define SPR_SRR2 0x3de /* 4.. Save/Restore Register 2 */ -#define SPR_SRR3 0x3df /* 4.. Save/Restore Register 3 */ #define SPR_HID0 0x3f0 /* ..8 Hardware Implementation Register 0 */ #define SPR_HID1 0x3f1 /* ..8 Hardware Implementation Register 1 */ #define SPR_HID2 0x3f3 /* ..8 Hardware Implementation Register 2 */ #define SPR_HID4 0x3f4 /* ..8 Hardware Implementation Register 4 */ #define SPR_HID5 0x3f6 /* ..8 Hardware Implementation Register 5 */ #define SPR_HID6 0x3f9 /* ..8 Hardware Implementation Register 6 */ #define SPR_CELL_TSRL 0x380 /* ... Cell BE Thread Status Register */ #define SPR_CELL_TSCR 0x399 /* ... Cell BE Thread Switch Register */ #if defined(AIM) -#define SPR_DBSR 0x3f0 /* 4.. Debug Status Register */ -#define DBSR_IC 0x80000000 /* Instruction completion debug event */ -#define DBSR_BT 0x40000000 /* Branch Taken debug event */ -#define DBSR_EDE 0x20000000 /* Exception debug event */ -#define DBSR_TIE 0x10000000 /* Trap Instruction debug event */ -#define DBSR_UDE 0x08000000 /* Unconditional debug event */ -#define DBSR_IA1 0x04000000 /* IAC1 debug event */ -#define DBSR_IA2 0x02000000 /* IAC2 debug event */ -#define DBSR_DR1 0x01000000 /* DAC1 Read debug event */ -#define DBSR_DW1 0x00800000 /* DAC1 Write debug event */ -#define DBSR_DR2 0x00400000 /* DAC2 Read debug event */ -#define DBSR_DW2 0x00200000 /* DAC2 Write debug event */ -#define DBSR_IDE 0x00100000 /* Imprecise debug event */ -#define DBSR_IA3 0x00080000 /* IAC3 debug event */ -#define DBSR_IA4 0x00040000 /* IAC4 debug event */ -#define DBSR_MRR 0x00000300 /* Most recent reset */ -#define SPR_DBCR0 0x3f2 /* 4.. Debug Control Register 0 */ -#define SPR_DBCR1 0x3bd /* 4.. Debug Control Register 1 */ -#define SPR_IAC1 0x3f4 /* 4.. Instruction Address Compare 1 */ -#define SPR_IAC2 0x3f5 /* 4.. Instruction Address Compare 2 */ -#define SPR_DAC1 0x3f6 /* 4.. Data Address Compare 1 */ -#define SPR_DAC2 0x3f7 /* 4.. Data Address Compare 2 */ #define SPR_PIR 0x3ff /* .6. Processor Identification Register */ #elif defined(BOOKE) #define SPR_PIR 0x11e /* ..8 Processor Identification Register */ -#define SPR_DBSR 0x130 /* ..8 Debug Status Register */ -#define DBSR_IDE 0x80000000 /* Imprecise debug event. */ -#define DBSR_UDE 0x40000000 /* Unconditional debug event. */ -#define DBSR_MRR 0x30000000 /* Most recent Reset (mask). */ -#define DBSR_ICMP 0x08000000 /* Instr. complete debug event. */ -#define DBSR_BRT 0x04000000 /* Branch taken debug event. */ -#define DBSR_IRPT 0x02000000 /* Interrupt taken debug event. */ -#define DBSR_TRAP 0x01000000 /* Trap instr. debug event. */ -#define DBSR_IAC1 0x00800000 /* Instr. address compare #1. */ -#define DBSR_IAC2 0x00400000 /* Instr. address compare #2. */ -#define DBSR_IAC3 0x00200000 /* Instr. address compare #3. */ -#define DBSR_IAC4 0x00100000 /* Instr. address compare #4. */ -#define DBSR_DAC1R 0x00080000 /* Data addr. read compare #1. */ -#define DBSR_DAC1W 0x00040000 /* Data addr. write compare #1. */ -#define DBSR_DAC2R 0x00020000 /* Data addr. read compare #2. */ -#define DBSR_DAC2W 0x00010000 /* Data addr. write compare #2. */ -#define DBSR_RET 0x00008000 /* Return debug event. */ -#define SPR_DBCR0 0x134 /* ..8 Debug Control Register 0 */ -#define SPR_DBCR1 0x135 /* ..8 Debug Control Register 1 */ -#define SPR_IAC1 0x138 /* ..8 Instruction Address Compare 1 */ -#define SPR_IAC2 0x139 /* ..8 Instruction Address Compare 2 */ -#define SPR_DAC1 0x13c /* ..8 Data Address Compare 1 */ -#define SPR_DAC2 0x13d /* ..8 Data Address Compare 2 */ #endif #define DBCR0_EDM 0x80000000 /* External Debug Mode */ #define DBCR0_IDM 0x40000000 /* Internal Debug Mode */ #define DBCR0_RST_MASK 0x30000000 /* ReSeT */ #define DBCR0_RST_NONE 0x00000000 /* No action */ #define DBCR0_RST_CORE 0x10000000 /* Core reset */ #define DBCR0_RST_CHIP 0x20000000 /* Chip reset */ #define DBCR0_RST_SYSTEM 0x30000000 /* System reset */ #define DBCR0_IC 0x08000000 /* Instruction Completion debug event */ #define DBCR0_BT 0x04000000 /* Branch Taken debug event */ #define DBCR0_EDE 0x02000000 /* Exception Debug Event */ #define DBCR0_TDE 0x01000000 /* Trap Debug Event */ #define DBCR0_IA1 0x00800000 /* IAC (Instruction Address Compare) 1 debug event */ #define DBCR0_IA2 0x00400000 /* IAC 2 debug event */ #define DBCR0_IA12 0x00200000 /* Instruction Address Range Compare 1-2 */ #define DBCR0_IA12X 0x00100000 /* IA12 eXclusive */ #define DBCR0_IA3 0x00080000 /* IAC 3 debug event */ #define DBCR0_IA4 0x00040000 /* IAC 4 debug event */ #define DBCR0_IA34 0x00020000 /* Instruction Address Range Compare 3-4 */ #define DBCR0_IA34X 0x00010000 /* IA34 eXclusive */ #define DBCR0_IA12T 0x00008000 /* Instruction Address Range Compare 1-2 range Toggle */ #define DBCR0_IA34T 0x00004000 /* Instruction Address Range Compare 3-4 range Toggle */ #define DBCR0_FT 0x00000001 /* Freeze Timers on debug event */ #define SPR_IABR 0x3f2 /* ..8 Instruction Address Breakpoint Register 0 */ #define SPR_DABR 0x3f5 /* .6. Data Address Breakpoint Register */ #define SPR_MSSCR0 0x3f6 /* .6. Memory SubSystem Control Register */ #define MSSCR0_SHDEN 0x80000000 /* 0: Shared-state enable */ #define MSSCR0_SHDPEN3 0x40000000 /* 1: ~SHD[01] signal enable in MEI mode */ #define MSSCR0_L1INTVEN 0x38000000 /* 2-4: L1 data cache ~HIT intervention enable */ #define MSSCR0_L2INTVEN 0x07000000 /* 5-7: L2 data cache ~HIT intervention enable*/ #define MSSCR0_DL1HWF 0x00800000 /* 8: L1 data cache hardware flush */ #define MSSCR0_MBO 0x00400000 /* 9: must be one */ #define MSSCR0_EMODE 0x00200000 /* 10: MPX bus mode (read-only) */ #define MSSCR0_ABD 0x00100000 /* 11: address bus driven (read-only) */ #define MSSCR0_MBZ 0x000fffff /* 12-31: must be zero */ #define MSSCR0_L2PFE 0x00000003 /* 30-31: L2 prefetch enable */ #define SPR_MSSSR0 0x3f7 /* .6. Memory Subsystem Status Register (MPC745x) */ #define MSSSR0_L2TAG 0x00040000 /* 13: L2 tag parity error */ #define MSSSR0_L2DAT 0x00020000 /* 14: L2 data parity error */ #define MSSSR0_L3TAG 0x00010000 /* 15: L3 tag parity error */ #define MSSSR0_L3DAT 0x00008000 /* 16: L3 data parity error */ #define MSSSR0_APE 0x00004000 /* 17: Address parity error */ #define MSSSR0_DPE 0x00002000 /* 18: Data parity error */ #define MSSSR0_TEA 0x00001000 /* 19: Bus transfer error acknowledge */ #define SPR_LDSTCR 0x3f8 /* .6. Load/Store Control Register */ #define SPR_L2PM 0x3f8 /* .6. L2 Private Memory Control Register */ #define SPR_L2CR 0x3f9 /* .6. L2 Control Register */ #define L2CR_L2E 0x80000000 /* 0: L2 enable */ #define L2CR_L2PE 0x40000000 /* 1: L2 data parity enable */ #define L2CR_L2SIZ 0x30000000 /* 2-3: L2 size */ #define L2SIZ_2M 0x00000000 #define L2SIZ_256K 0x10000000 #define L2SIZ_512K 0x20000000 #define L2SIZ_1M 0x30000000 #define L2CR_L2CLK 0x0e000000 /* 4-6: L2 clock ratio */ #define L2CLK_DIS 0x00000000 /* disable L2 clock */ #define L2CLK_10 0x02000000 /* core clock / 1 */ #define L2CLK_15 0x04000000 /* / 1.5 */ #define L2CLK_20 0x08000000 /* / 2 */ #define L2CLK_25 0x0a000000 /* / 2.5 */ #define L2CLK_30 0x0c000000 /* / 3 */ #define L2CR_L2RAM 0x01800000 /* 7-8: L2 RAM type */ #define L2RAM_FLOWTHRU_BURST 0x00000000 #define L2RAM_PIPELINE_BURST 0x01000000 #define L2RAM_PIPELINE_LATE 0x01800000 #define L2CR_L2DO 0x00400000 /* 9: L2 data-only. Setting this bit disables instruction caching. */ #define L2CR_L2I 0x00200000 /* 10: L2 global invalidate. */ #define L2CR_L2IO_7450 0x00010000 /* 11: L2 instruction-only (MPC745x). */ #define L2CR_L2CTL 0x00100000 /* 11: L2 RAM control (ZZ enable). Enables automatic operation of the L2ZZ (low-power mode) signal. */ #define L2CR_L2WT 0x00080000 /* 12: L2 write-through. */ #define L2CR_L2TS 0x00040000 /* 13: L2 test support. */ #define L2CR_L2OH 0x00030000 /* 14-15: L2 output hold. */ #define L2CR_L2DO_7450 0x00010000 /* 15: L2 data-only (MPC745x). */ #define L2CR_L2SL 0x00008000 /* 16: L2 DLL slow. */ #define L2CR_L2DF 0x00004000 /* 17: L2 differential clock. */ #define L2CR_L2BYP 0x00002000 /* 18: L2 DLL bypass. */ #define L2CR_L2FA 0x00001000 /* 19: L2 flush assist (for software flush). */ #define L2CR_L2HWF 0x00000800 /* 20: L2 hardware flush. */ #define L2CR_L2IO 0x00000400 /* 21: L2 instruction-only. */ #define L2CR_L2CLKSTP 0x00000200 /* 22: L2 clock stop. */ #define L2CR_L2DRO 0x00000100 /* 23: L2DLL rollover checkstop enable. */ #define L2CR_L2IP 0x00000001 /* 31: L2 global invalidate in */ /* progress (read only). */ #define SPR_L3CR 0x3fa /* .6. L3 Control Register */ #define L3CR_L3E 0x80000000 /* 0: L3 enable */ #define L3CR_L3PE 0x40000000 /* 1: L3 data parity enable */ #define L3CR_L3APE 0x20000000 #define L3CR_L3SIZ 0x10000000 /* 3: L3 size (0=1MB, 1=2MB) */ #define L3CR_L3CLKEN 0x08000000 /* 4: Enables L3_CLK[0:1] */ #define L3CR_L3CLK 0x03800000 #define L3CR_L3IO 0x00400000 #define L3CR_L3CLKEXT 0x00200000 #define L3CR_L3CKSPEXT 0x00100000 #define L3CR_L3OH1 0x00080000 #define L3CR_L3SPO 0x00040000 #define L3CR_L3CKSP 0x00030000 #define L3CR_L3PSP 0x0000e000 #define L3CR_L3REP 0x00001000 #define L3CR_L3HWF 0x00000800 #define L3CR_L3I 0x00000400 /* 21: L3 global invalidate */ #define L3CR_L3RT 0x00000300 #define L3CR_L3NIRCA 0x00000080 #define L3CR_L3DO 0x00000040 #define L3CR_PMEN 0x00000004 #define L3CR_PMSIZ 0x00000003 -#define SPR_DCCR 0x3fa /* 4.. Data Cache Cachability Register */ -#define SPR_ICCR 0x3fb /* 4.. Instruction Cache Cachability Register */ #define SPR_THRM1 0x3fc /* .6. Thermal Management Register */ #define SPR_THRM2 0x3fd /* .6. Thermal Management Register */ #define SPR_THRM_TIN 0x80000000 /* Thermal interrupt bit (RO) */ #define SPR_THRM_TIV 0x40000000 /* Thermal interrupt valid (RO) */ #define SPR_THRM_THRESHOLD(x) ((x) << 23) /* Thermal sensor threshold */ #define SPR_THRM_TID 0x00000004 /* Thermal interrupt direction */ #define SPR_THRM_TIE 0x00000002 /* Thermal interrupt enable */ #define SPR_THRM_VALID 0x00000001 /* Valid bit */ #define SPR_THRM3 0x3fe /* .6. Thermal Management Register */ #define SPR_THRM_TIMER(x) ((x) << 1) /* Sampling interval timer */ #define SPR_THRM_ENABLE 0x00000001 /* TAU Enable */ #define SPR_FPECR 0x3fe /* .6. Floating-Point Exception Cause Register */ /* Time Base Register declarations */ #define TBR_TBL 0x10c /* 468 Time Base Lower - read */ #define TBR_TBU 0x10d /* 468 Time Base Upper - read */ #define TBR_TBWL 0x11c /* 468 Time Base Lower - supervisor, write */ #define TBR_TBWU 0x11d /* 468 Time Base Upper - supervisor, write */ /* Performance counter declarations */ #define PMC_OVERFLOW 0x80000000 /* Counter has overflowed */ /* The first five countable [non-]events are common to many PMC's */ #define PMCN_NONE 0 /* Count nothing */ #define PMCN_CYCLES 1 /* Processor cycles */ #define PMCN_ICOMP 2 /* Instructions completed */ #define PMCN_TBLTRANS 3 /* TBL bit transitions */ #define PCMN_IDISPATCH 4 /* Instructions dispatched */ /* Similar things for the 970 PMC direct counters */ #define PMC970N_NONE 0x8 /* Count nothing */ #define PMC970N_CYCLES 0xf /* Processor cycles */ #define PMC970N_ICOMP 0x9 /* Instructions completed */ #if defined(BOOKE) #define SPR_MCARU 0x239 /* ..8 Machine Check Address register upper bits */ #define SPR_MCSR 0x23c /* ..8 Machine Check Syndrome register */ #define SPR_MCAR 0x23d /* ..8 Machine Check Address register */ #define SPR_ESR 0x003e /* ..8 Exception Syndrome Register */ #define ESR_PIL 0x08000000 /* Program interrupt - illegal */ #define ESR_PPR 0x04000000 /* Program interrupt - privileged */ #define ESR_PTR 0x02000000 /* Program interrupt - trap */ #define ESR_ST 0x00800000 /* Store operation */ #define ESR_DLK 0x00200000 /* Data storage, D cache locking */ #define ESR_ILK 0x00100000 /* Data storage, I cache locking */ #define ESR_BO 0x00020000 /* Data/instruction storage, byte ordering */ #define ESR_SPE 0x00000080 /* SPE exception bit */ #define SPR_CSRR0 0x03a /* ..8 58 Critical SRR0 */ #define SPR_CSRR1 0x03b /* ..8 59 Critical SRR1 */ #define SPR_MCSRR0 0x23a /* ..8 570 Machine check SRR0 */ #define SPR_MCSRR1 0x23b /* ..8 571 Machine check SRR1 */ #define SPR_DSRR0 0x23e /* ..8 574 Debug SRR0 */ #define SPR_DSRR1 0x23f /* ..8 575 Debug SRR1 */ - -#define SPR_MMUCR 0x3b2 /* 4.. MMU Control Register */ -#define MMUCR_SWOA (0x80000000 >> 7) -#define MMUCR_U1TE (0x80000000 >> 9) -#define MMUCR_U2SWOAE (0x80000000 >> 10) -#define MMUCR_DULXE (0x80000000 >> 12) -#define MMUCR_IULXE (0x80000000 >> 13) -#define MMUCR_STS (0x80000000 >> 15) -#define MMUCR_STID_MASK (0xFF000000 >> 24) #define SPR_MMUCSR0 0x3f4 /* ..8 1012 MMU Control and Status Register 0 */ #define MMUCSR0_L2TLB0_FI 0x04 /* TLB0 flash invalidate */ #define MMUCSR0_L2TLB1_FI 0x02 /* TLB1 flash invalidate */ #define SPR_SVR 0x3ff /* ..8 1023 System Version Register */ #define SVR_MPC8533 0x8034 #define SVR_MPC8533E 0x803c #define SVR_MPC8541 0x8072 #define SVR_MPC8541E 0x807a #define SVR_MPC8548 0x8031 #define SVR_MPC8548E 0x8039 #define SVR_MPC8555 0x8071 #define SVR_MPC8555E 0x8079 #define SVR_MPC8572 0x80e0 #define SVR_MPC8572E 0x80e8 #define SVR_P1011 0x80e5 #define SVR_P1011E 0x80ed #define SVR_P1013 0x80e7 #define SVR_P1013E 0x80ef #define SVR_P1020 0x80e4 #define SVR_P1020E 0x80ec #define SVR_P1022 0x80e6 #define SVR_P1022E 0x80ee #define SVR_P2010 0x80e3 #define SVR_P2010E 0x80eb #define SVR_P2020 0x80e2 #define SVR_P2020E 0x80ea #define SVR_P2041 0x8210 #define SVR_P2041E 0x8218 #define SVR_P3041 0x8211 #define SVR_P3041E 0x8219 #define SVR_P4040 0x8200 #define SVR_P4040E 0x8208 #define SVR_P4080 0x8201 #define SVR_P4080E 0x8209 #define SVR_P5010 0x8221 #define SVR_P5010E 0x8229 #define SVR_P5020 0x8220 #define SVR_P5020E 0x8228 #define SVR_P5021 0x8205 #define SVR_P5021E 0x820d #define SVR_P5040 0x8204 #define SVR_P5040E 0x820c #define SVR_VER(svr) (((svr) >> 16) & 0xffff) #define SPR_PID0 0x030 /* ..8 Process ID Register 0 */ #define SPR_PID1 0x279 /* ..8 Process ID Register 1 */ #define SPR_PID2 0x27a /* ..8 Process ID Register 2 */ #define SPR_TLB0CFG 0x2B0 /* ..8 TLB 0 Config Register */ #define SPR_TLB1CFG 0x2B1 /* ..8 TLB 1 Config Register */ #define TLBCFG_ASSOC_MASK 0xff000000 /* Associativity of TLB */ #define TLBCFG_ASSOC_SHIFT 24 #define TLBCFG_NENTRY_MASK 0x00000fff /* Number of entries in TLB */ #define SPR_IVPR 0x03f /* ..8 Interrupt Vector Prefix Register */ #define SPR_IVOR0 0x190 /* ..8 Critical input */ #define SPR_IVOR1 0x191 /* ..8 Machine check */ #define SPR_IVOR2 0x192 #define SPR_IVOR3 0x193 #define SPR_IVOR4 0x194 #define SPR_IVOR5 0x195 #define SPR_IVOR6 0x196 #define SPR_IVOR7 0x197 #define SPR_IVOR8 0x198 #define SPR_IVOR9 0x199 #define SPR_IVOR10 0x19a #define SPR_IVOR11 0x19b #define SPR_IVOR12 0x19c #define SPR_IVOR13 0x19d #define SPR_IVOR14 0x19e #define SPR_IVOR15 0x19f #define SPR_IVOR32 0x210 #define SPR_IVOR33 0x211 #define SPR_IVOR34 0x212 #define SPR_IVOR35 0x213 #define SPR_MAS0 0x270 /* ..8 MMU Assist Register 0 Book-E/e500 */ #define SPR_MAS1 0x271 /* ..8 MMU Assist Register 1 Book-E/e500 */ #define SPR_MAS2 0x272 /* ..8 MMU Assist Register 2 Book-E/e500 */ #define SPR_MAS3 0x273 /* ..8 MMU Assist Register 3 Book-E/e500 */ #define SPR_MAS4 0x274 /* ..8 MMU Assist Register 4 Book-E/e500 */ #define SPR_MAS5 0x275 /* ..8 MMU Assist Register 5 Book-E */ #define SPR_MAS6 0x276 /* ..8 MMU Assist Register 6 Book-E/e500 */ #define SPR_MAS7 0x3B0 /* ..8 MMU Assist Register 7 Book-E/e500 */ #define SPR_MAS8 0x155 /* ..8 MMU Assist Register 8 Book-E/e500 */ #define SPR_L1CFG0 0x203 /* ..8 L1 cache configuration register 0 */ #define SPR_L1CFG1 0x204 /* ..8 L1 cache configuration register 1 */ #define SPR_CCR1 0x378 #define CCR1_L2COBE 0x00000040 #define DCR_L2DCDCRAI 0x0000 /* L2 D-Cache DCR Address Pointer */ #define DCR_L2DCDCRDI 0x0001 /* L2 D-Cache DCR Data Indirect */ #define DCR_L2CR0 0x00 /* L2 Cache Configuration Register 0 */ #define L2CR0_AS 0x30000000 #define SPR_L1CSR0 0x3F2 /* ..8 L1 Cache Control and Status Register 0 */ #define L1CSR0_DCPE 0x00010000 /* Data Cache Parity Enable */ #define L1CSR0_DCLFR 0x00000100 /* Data Cache Lock Bits Flash Reset */ #define L1CSR0_DCFI 0x00000002 /* Data Cache Flash Invalidate */ #define L1CSR0_DCE 0x00000001 /* Data Cache Enable */ #define SPR_L1CSR1 0x3F3 /* ..8 L1 Cache Control and Status Register 1 */ #define L1CSR1_ICPE 0x00010000 /* Instruction Cache Parity Enable */ #define L1CSR1_ICUL 0x00000400 /* Instr Cache Unable to Lock */ #define L1CSR1_ICLFR 0x00000100 /* Instruction Cache Lock Bits Flash Reset */ #define L1CSR1_ICFI 0x00000002 /* Instruction Cache Flash Invalidate */ #define L1CSR1_ICE 0x00000001 /* Instruction Cache Enable */ #define SPR_L2CSR0 0x3F9 /* ..8 L2 Cache Control and Status Register 0 */ #define L2CSR0_L2E 0x80000000 /* L2 Cache Enable */ #define L2CSR0_L2PE 0x40000000 /* L2 Cache Parity Enable */ #define L2CSR0_L2FI 0x00200000 /* L2 Cache Flash Invalidate */ #define L2CSR0_L2LFC 0x00000400 /* L2 Cache Lock Flags Clear */ #define SPR_BUCSR 0x3F5 /* ..8 Branch Unit Control and Status Register */ #define BUCSR_BPEN 0x00000001 /* Branch Prediction Enable */ #define BUCSR_BBFI 0x00000200 /* Branch Buffer Flash Invalidate */ #endif /* BOOKE */ #endif /* !_POWERPC_SPR_H_ */ Index: head/sys/powerpc/include/tlb.h =================================================================== --- head/sys/powerpc/include/tlb.h (revision 359057) +++ head/sys/powerpc/include/tlb.h (revision 359058) @@ -1,233 +1,183 @@ /*- * SPDX-License-Identifier: BSD-3-Clause * * Copyright (C) 2006-2012 Semihalf. * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * 3. The name of the author may not be used to endorse or promote products * derived from this software without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED * TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * * $FreeBSD$ */ #ifndef _MACHINE_TLB_H_ #define _MACHINE_TLB_H_ #if defined(BOOKE_E500) /* PowerPC E500 MAS registers */ #define MAS0_TLBSEL(x) ((x << 28) & 0x10000000) #define MAS0_ESEL(x) ((x << 16) & 0x003F0000) #define MAS0_TLBSEL1 0x10000000 #define MAS0_TLBSEL0 0x00000000 #define MAS0_ESEL_TLB1MASK 0x000F0000 #define MAS0_ESEL_TLB0MASK 0x00030000 #define MAS0_ESEL_SHIFT 16 #define MAS0_NV_MASK 0x00000003 #define MAS0_NV_SHIFT 0 #define MAS1_VALID 0x80000000 #define MAS1_IPROT 0x40000000 #define MAS1_TID_MASK 0x00FF0000 #define MAS1_TID_SHIFT 16 #define MAS1_TS_MASK 0x00001000 #define MAS1_TS_SHIFT 12 #define MAS1_TSIZE_MASK 0x00000F00 #define MAS1_TSIZE_SHIFT 8 #define TLB_SIZE_4K 1 #define TLB_SIZE_16K 2 #define TLB_SIZE_64K 3 #define TLB_SIZE_256K 4 #define TLB_SIZE_1M 5 #define TLB_SIZE_4M 6 #define TLB_SIZE_16M 7 #define TLB_SIZE_64M 8 #define TLB_SIZE_256M 9 #define TLB_SIZE_1G 10 #define TLB_SIZE_4G 11 #ifdef __powerpc64__ #define MAS2_EPN_MASK 0xFFFFFFFFFFFFF000UL #else #define MAS2_EPN_MASK 0xFFFFF000 #endif #define MAS2_EPN_SHIFT 12 #define MAS2_X0 0x00000040 #define MAS2_X1 0x00000020 #define MAS2_W 0x00000010 #define MAS2_I 0x00000008 #define MAS2_M 0x00000004 #define MAS2_G 0x00000002 #define MAS2_E 0x00000001 #define MAS2_WIMGE_MASK 0x0000007F #define MAS3_RPN 0xFFFFF000 #define MAS3_RPN_SHIFT 12 #define MAS3_U0 0x00000200 #define MAS3_U1 0x00000100 #define MAS3_U2 0x00000080 #define MAS3_U3 0x00000040 #define MAS3_UX 0x00000020 #define MAS3_SX 0x00000010 #define MAS3_UW 0x00000008 #define MAS3_SW 0x00000004 #define MAS3_UR 0x00000002 #define MAS3_SR 0x00000001 #define MAS4_TLBSELD1 0x10000000 #define MAS4_TLBSELD0 0x00000000 #define MAS4_TIDSELD_MASK 0x00030000 #define MAS4_TIDSELD_SHIFT 16 #define MAS4_TSIZED_MASK 0x00000F00 #define MAS4_TSIZED_SHIFT 8 #define MAS4_X0D 0x00000040 #define MAS4_X1D 0x00000020 #define MAS4_WD 0x00000010 #define MAS4_ID 0x00000008 #define MAS4_MD 0x00000004 #define MAS4_GD 0x00000002 #define MAS4_ED 0x00000001 #define MAS6_SPID0_MASK 0x00FF0000 #define MAS6_SPID0_SHIFT 16 #define MAS6_SAS 0x00000001 #define MAS7_RPN 0x0000000F #define MAS1_GETTID(mas1) (((mas1) & MAS1_TID_MASK) >> MAS1_TID_SHIFT) #define MAS2_TLB0_ENTRY_IDX_MASK 0x0007f000 #define MAS2_TLB0_ENTRY_IDX_SHIFT 12 /* * Maximum number of TLB1 entries used for a permanent mapping of kernel * region (kernel image plus statically allocated data). */ #define KERNEL_REGION_MAX_TLB_ENTRIES 4 /* * Use MAS2_X0 to mark entries which will be copied * to AP CPUs during SMP bootstrap. As result entries * marked with _TLB_ENTRY_SHARED will be shared by all CPUs. */ #define _TLB_ENTRY_SHARED (MAS2_X0) /* XXX under SMP? */ #define _TLB_ENTRY_IO (MAS2_I | MAS2_G) #define _TLB_ENTRY_MEM (MAS2_M) #define TLB1_MAX_ENTRIES 64 #if !defined(LOCORE) typedef struct tlb_entry { vm_paddr_t phys; vm_offset_t virt; vm_size_t size; uint32_t mas1; #ifdef __powerpc64__ uint64_t mas2; #else uint32_t mas2; #endif uint32_t mas3; uint32_t mas7; } tlb_entry_t; void tlb1_inval_entry(unsigned int); void tlb1_init(void); #endif /* !LOCORE */ -#elif defined(BOOKE_PPC4XX) - -/* TLB Words */ -#define TLB_PAGEID 0 -#define TLB_XLAT 1 -#define TLB_ATTRIB 2 - -/* Page identification fields */ -#define TLB_EPN_MASK (0xFFFFFC00 >> 0) -#define TLB_VALID (0x80000000 >> 22) -#define TLB_TS (0x80000000 >> 23) -#define TLB_SIZE_1K (0x00000000 >> 24) -#define TLB_SIZE_MASK (0xF0000000 >> 24) - -/* Translation fields */ -#define TLB_RPN_MASK (0xFFFFFC00 >> 0) -#define TLB_ERPN_MASK (0xF0000000 >> 28) - -/* Storage attribute and access control fields */ -#define TLB_WL1 (0x80000000 >> 11) -#define TLB_IL1I (0x80000000 >> 12) -#define TLB_IL1D (0x80000000 >> 13) -#define TLB_IL2I (0x80000000 >> 14) -#define TLB_IL2D (0x80000000 >> 15) -#define TLB_U0 (0x80000000 >> 16) -#define TLB_U1 (0x80000000 >> 17) -#define TLB_U2 (0x80000000 >> 18) -#define TLB_U3 (0x80000000 >> 19) -#define TLB_W (0x80000000 >> 20) -#define TLB_I (0x80000000 >> 21) -#define TLB_M (0x80000000 >> 22) -#define TLB_G (0x80000000 >> 23) -#define TLB_E (0x80000000 >> 24) -#define TLB_UX (0x80000000 >> 26) -#define TLB_UW (0x80000000 >> 27) -#define TLB_UR (0x80000000 >> 28) -#define TLB_SX (0x80000000 >> 29) -#define TLB_SW (0x80000000 >> 30) -#define TLB_SR (0x80000000 >> 31) -#define TLB_SIZE 64 - -#define TLB_SIZE_4K (0x10000000 >> 24) -#define TLB_SIZE_16K (0x20000000 >> 24) -#define TLB_SIZE_64K (0x30000000 >> 24) -#define TLB_SIZE_256K (0x40000000 >> 24) -#define TLB_SIZE_1M (0x50000000 >> 24) -#define TLB_SIZE_16M (0x70000000 >> 24) -#define TLB_SIZE_256M (0x90000000 >> 24) -#define TLB_SIZE_1G (0xA0000000 >> 24) - #endif /* BOOKE_E500 */ #define TID_KERNEL 0 /* TLB TID to use for kernel (shared) translations */ #define TID_KRESERVED 1 /* Number of TIDs reserved for kernel */ #define TID_URESERVED 0 /* Number of TIDs reserved for user */ #define TID_MIN (TID_KRESERVED + TID_URESERVED) #define TID_MAX 255 #define TID_NONE -1 #define TLB_UNLOCKED 0 #if !defined(LOCORE) typedef int tlbtid_t; struct pmap; void tlb_lock(uintptr_t *); void tlb_unlock(uintptr_t *); void tlb1_ap_prep(void); int tlb1_set_entry(vm_offset_t, vm_paddr_t, vm_size_t, uint32_t); #endif /* !LOCORE */ #endif /* _MACHINE_TLB_H_ */ Index: head/sys/powerpc/powerpc/db_disasm.c =================================================================== --- head/sys/powerpc/powerpc/db_disasm.c (revision 359057) +++ head/sys/powerpc/powerpc/db_disasm.c (revision 359058) @@ -1,1096 +1,1083 @@ /* $NetBSD: db_disasm.c,v 1.28 2013/07/04 23:00:23 joerg Exp $ */ /* $OpenBSD: db_disasm.c,v 1.2 1996/12/28 06:21:48 rahnds Exp $ */ #include __FBSDID("$FreeBSD$"); #include #include #include #include #include #include #include #include #include enum function_mask { Op_A = 0x00000001, Op_B = 0x00000002, Op_BI = 0x00000004, Op_BO = 0x00000008, Op_BC = Op_BI | Op_BO, Op_CRM = 0x00000010, Op_D = 0x00000020, Op_ST = 0x00000020, /* Op_S for store-operations, same as D */ Op_S = 0x00000040, /* S-field is swapped with A-field */ Op_FM = Op_D | Op_S, /* kludge (reduce Op_s) */ Op_dA = 0x00000080, Op_LK = 0x00000100, Op_Rc = 0x00000200, Op_AA = Op_LK | Op_Rc, /* kludge (reduce Op_s) */ Op_LKM = Op_AA, Op_RcM = Op_AA, Op_OE = 0x00000400, Op_SR = 0x00000800, Op_TO = 0x00001000, Op_sign = 0x00002000, Op_const = 0x00004000, Op_SIMM = Op_const | Op_sign, Op_UIMM = Op_const, Op_crbA = 0x00008000, Op_crbB = 0x00010000, Op_WS = Op_crbB, /* kludge, same field as crbB */ Op_rSH = Op_crbB, /* kludge, same field as crbB */ Op_crbD = 0x00020000, Op_crfD = 0x00040000, Op_crfS = 0x00080000, Op_ds = 0x00100000, Op_me = 0x00200000, Op_spr = 0x00400000, Op_dcr = Op_spr, /* out of bits - cheat with Op_spr */ Op_tbr = 0x00800000, Op_BP = 0x01000000, Op_BD = 0x02000000, Op_LI = 0x04000000, Op_C = 0x08000000, Op_NB = 0x10000000, Op_sh_mb_sh = 0x20000000, Op_sh = 0x40000000, Op_SH = Op_sh | Op_sh_mb_sh, Op_mb = 0x80000000, Op_MB = Op_mb | Op_sh_mb_sh, Op_ME = Op_MB, }; struct opcode { const char *name; u_int32_t mask; u_int32_t code; enum function_mask func; }; typedef u_int32_t instr_t; typedef void (op_class_func) (instr_t, vm_offset_t); u_int32_t extract_field(u_int32_t value, u_int32_t base, u_int32_t width); void disasm_fields(const struct opcode *popcode, instr_t instr, vm_offset_t loc, char *disasm_str, size_t slen); void dis_ppc(const struct opcode *opcodeset, instr_t instr, vm_offset_t loc); op_class_func op_ill, op_base; op_class_func op_cl_x13, op_cl_x1e, op_cl_x1f; op_class_func op_cl_x3a, op_cl_x3b; op_class_func op_cl_x3e, op_cl_x3f; op_class_func *opcodes_base[] = { /*x00*/ op_ill, op_ill, op_base, op_ill, /*x04*/ op_ill, op_ill, op_ill, op_base, /*x08*/ op_base, op_base, op_base, op_base, /*x0C*/ op_base, op_base, op_base/*XXX*/, op_base/*XXX*/, /*x10*/ op_base, op_base, op_base, op_cl_x13, /*x14*/ op_base, op_base, op_ill, op_base, /*x18*/ op_base, op_base, op_base, op_base, /*x1C*/ op_base, op_base, op_cl_x1e, op_cl_x1f, /*x20*/ op_base, op_base, op_base, op_base, /*x24*/ op_base, op_base, op_base, op_base, /*x28*/ op_base, op_base, op_base, op_base, /*x2C*/ op_base, op_base, op_base, op_base, /*x30*/ op_base, op_base, op_base, op_base, /*x34*/ op_base, op_base, op_base, op_base, /*x38*/ op_ill, op_ill, op_cl_x3a, op_cl_x3b, /*x3C*/ op_ill, op_ill, op_cl_x3e, op_cl_x3f }; /* This table could be modified to make significant the "reserved" fields * of the opcodes, But I didn't feel like it when typing in the table, * I would recommend that this table be looked over for errors, * This was derived from the table in Appendix A.2 of (Mot part # MPCFPE/AD) * PowerPC Microprocessor Family: The Programming Environments */ const struct opcode opcodes[] = { { "tdi", 0xfc000000, 0x08000000, Op_TO | Op_A | Op_SIMM }, { "twi", 0xfc000000, 0x0c000000, Op_TO | Op_A | Op_SIMM }, { "mulli", 0xfc000000, 0x1c000000, Op_D | Op_A | Op_SIMM }, { "subfic", 0xfc000000, 0x20000000, Op_D | Op_A | Op_SIMM }, { "cmplwi", 0xfc200000, 0x28000000, Op_crfD | Op_A | Op_SIMM }, { "cmpldi", 0xfc200000, 0x28200000, Op_crfD | Op_A | Op_SIMM }, { "cmpwi", 0xfc200000, 0x2c000000, Op_crfD | Op_A | Op_SIMM }, { "cmpdi", 0xfc200000, 0x2c200000, Op_crfD | Op_A | Op_SIMM }, { "addic", 0xfc000000, 0x30000000, Op_D | Op_A | Op_SIMM }, { "addic.", 0xfc000000, 0x34000000, Op_D | Op_A | Op_SIMM }, { "addi", 0xfc000000, 0x38000000, Op_D | Op_A | Op_SIMM }, { "addis", 0xfc000000, 0x3c000000, Op_D | Op_A | Op_SIMM }, { "b", 0xfc000000, 0x40000000, Op_BC | Op_BD | Op_AA | Op_LK }, /* bc */ { "sc", 0xffffffff, 0x44000002, 0 }, { "b", 0xfc000000, 0x48000000, Op_LI | Op_AA | Op_LK }, { "rlwimi", 0xfc000000, 0x50000000, Op_S | Op_A | Op_SH | Op_MB | Op_ME | Op_Rc }, { "rlwinm", 0xfc000000, 0x54000000, Op_S | Op_A | Op_SH | Op_MB | Op_ME | Op_Rc }, { "rlwnm", 0xfc000000, 0x5c000000, Op_S | Op_A | Op_SH | Op_MB | Op_ME | Op_Rc }, { "ori", 0xfc000000, 0x60000000, Op_S | Op_A | Op_UIMM }, { "oris", 0xfc000000, 0x64000000, Op_S | Op_A | Op_UIMM }, { "xori", 0xfc000000, 0x68000000, Op_S | Op_A | Op_UIMM }, { "xoris", 0xfc000000, 0x6c000000, Op_S | Op_A | Op_UIMM }, { "andi.", 0xfc000000, 0x70000000, Op_S | Op_A | Op_UIMM }, { "andis.", 0xfc000000, 0x74000000, Op_S | Op_A | Op_UIMM }, { "lwz", 0xfc000000, 0x80000000, Op_D | Op_dA }, { "lwzu", 0xfc000000, 0x84000000, Op_D | Op_dA }, { "lbz", 0xfc000000, 0x88000000, Op_D | Op_dA }, { "lbzu", 0xfc000000, 0x8c000000, Op_D | Op_dA }, { "stw", 0xfc000000, 0x90000000, Op_ST | Op_dA }, { "stwu", 0xfc000000, 0x94000000, Op_ST | Op_dA }, { "stb", 0xfc000000, 0x98000000, Op_ST | Op_dA }, { "stbu", 0xfc000000, 0x9c000000, Op_ST | Op_dA }, { "lhz", 0xfc000000, 0xa0000000, Op_D | Op_dA }, { "lhzu", 0xfc000000, 0xa4000000, Op_D | Op_dA }, { "lha", 0xfc000000, 0xa8000000, Op_D | Op_dA }, { "lhau", 0xfc000000, 0xac000000, Op_D | Op_dA }, { "sth", 0xfc000000, 0xb0000000, Op_ST | Op_dA }, { "sthu", 0xfc000000, 0xb4000000, Op_ST | Op_dA }, { "lmw", 0xfc000000, 0xb8000000, Op_D | Op_dA }, { "stmw", 0xfc000000, 0xbc000000, Op_ST | Op_dA }, { "lfs", 0xfc000000, 0xc0000000, Op_D | Op_dA }, { "lfsu", 0xfc000000, 0xc4000000, Op_D | Op_dA }, { "lfd", 0xfc000000, 0xc8000000, Op_D | Op_dA }, { "lfdu", 0xfc000000, 0xcc000000, Op_D | Op_dA }, { "stfs", 0xfc000000, 0xd0000000, Op_ST | Op_dA }, { "stfsu", 0xfc000000, 0xd4000000, Op_ST | Op_dA }, { "stfd", 0xfc000000, 0xd8000000, Op_ST | Op_dA }, { "stfdu", 0xfc000000, 0xdc000000, Op_ST | Op_dA }, { "", 0x0, 0x0, 0 } }; /* 13 * 4 = 4c */ const struct opcode opcodes_13[] = { /* 0x13 << 2 */ { "mcrf", 0xfc0007fe, 0x4c000000, Op_crfD | Op_crfS }, { "b", 0xfc0007fe, 0x4c000020, Op_BC | Op_LK }, /* bclr */ { "crnor", 0xfc0007fe, 0x4c000042, Op_crbD | Op_crbA | Op_crbB }, { "rfi", 0xfc0007fe, 0x4c000064, 0 }, { "crandc", 0xfc0007fe, 0x4c000102, Op_crbD | Op_crbA | Op_crbB }, { "isync", 0xfc0007fe, 0x4c00012c, 0 }, { "crxor", 0xfc0007fe, 0x4c000182, Op_crbD | Op_crbA | Op_crbB }, { "crnand", 0xfc0007fe, 0x4c0001c2, Op_crbD | Op_crbA | Op_crbB }, { "crand", 0xfc0007fe, 0x4c000202, Op_crbD | Op_crbA | Op_crbB }, { "creqv", 0xfc0007fe, 0x4c000242, Op_crbD | Op_crbA | Op_crbB }, { "crorc", 0xfc0007fe, 0x4c000342, Op_crbD | Op_crbA | Op_crbB }, { "cror", 0xfc0007fe, 0x4c000382, Op_crbD | Op_crbA | Op_crbB }, { "b", 0xfc0007fe, 0x4c000420, Op_BC | Op_LK }, /* bcctr */ { "", 0x0, 0x0, 0 } }; /* 1e * 4 = 78 */ const struct opcode opcodes_1e[] = { { "rldicl", 0xfc00001c, 0x78000000, Op_S | Op_A | Op_sh | Op_mb | Op_Rc }, { "rldicr", 0xfc00001c, 0x78000004, Op_S | Op_A | Op_sh | Op_me | Op_Rc }, { "rldic", 0xfc00001c, 0x78000008, Op_S | Op_A | Op_sh | Op_mb | Op_Rc }, { "rldimi", 0xfc00001c, 0x7800000c, Op_S | Op_A | Op_sh | Op_mb | Op_Rc }, { "rldcl", 0xfc00003e, 0x78000010, Op_S | Op_A | Op_B | Op_mb | Op_Rc }, { "rldcr", 0xfc00003e, 0x78000012, Op_S | Op_A | Op_B | Op_me | Op_Rc }, { "", 0x0, 0x0, 0 } }; /* 1f * 4 = 7c */ const struct opcode opcodes_1f[] = { /* 1f << 2 */ { "cmpw", 0xfc2007fe, 0x7c000000, Op_crfD | Op_A | Op_B }, { "cmpd", 0xfc2007fe, 0x7c200000, Op_crfD | Op_A | Op_B }, { "tw", 0xfc0007fe, 0x7c000008, Op_TO | Op_A | Op_B }, { "subfc", 0xfc0003fe, 0x7c000010, Op_D | Op_A | Op_B | Op_OE | Op_Rc }, { "mulhdu", 0xfc0007fe, 0x7c000012, Op_D | Op_A | Op_B | Op_Rc }, { "addc", 0xfc0003fe, 0x7c000014, Op_D | Op_A | Op_B | Op_OE | Op_Rc }, { "mulhwu", 0xfc0007fe, 0x7c000016, Op_D | Op_A | Op_B | Op_Rc }, { "isellt", 0xfc0007ff, 0x7c00001e, Op_D | Op_A | Op_B }, { "iselgt", 0xfc0007ff, 0x7c00005e, Op_D | Op_A | Op_B }, { "iseleq", 0xfc0007ff, 0x7c00009e, Op_D | Op_A | Op_B }, { "mfcr", 0xfc0007fe, 0x7c000026, Op_D }, { "lwarx", 0xfc0007fe, 0x7c000028, Op_D | Op_A | Op_B }, { "ldx", 0xfc0007fe, 0x7c00002a, Op_D | Op_A | Op_B }, { "lwzx", 0xfc0007fe, 0x7c00002e, Op_D | Op_A | Op_B }, { "slw", 0xfc0007fe, 0x7c000030, Op_D | Op_A | Op_B | Op_Rc }, { "cntlzw", 0xfc0007fe, 0x7c000034, Op_S | Op_A | Op_Rc }, { "sld", 0xfc0007fe, 0x7c000036, Op_D | Op_A | Op_B | Op_Rc }, { "and", 0xfc0007fe, 0x7c000038, Op_D | Op_A | Op_B | Op_Rc }, { "cmplw", 0xfc2007fe, 0x7c000040, Op_crfD | Op_A | Op_B }, { "cmpld", 0xfc2007fe, 0x7c200040, Op_crfD | Op_A | Op_B }, { "subf", 0xfc0003fe, 0x7c000050, Op_D | Op_A | Op_B | Op_OE | Op_Rc }, { "ldux", 0xfc0007fe, 0x7c00006a, Op_D | Op_A | Op_B }, { "dcbst", 0xfc0007fe, 0x7c00006c, Op_A | Op_B }, { "lwzux", 0xfc0007fe, 0x7c00006e, Op_D | Op_A | Op_B }, { "cntlzd", 0xfc0007fe, 0x7c000074, Op_S | Op_A | Op_Rc }, { "andc", 0xfc0007fe, 0x7c000078, Op_S | Op_A | Op_B | Op_Rc }, { "td", 0xfc0007fe, 0x7c000088, Op_TO | Op_A | Op_B }, { "mulhd", 0xfc0007fe, 0x7c000092, Op_D | Op_A | Op_B | Op_Rc }, { "mulhw", 0xfc0007fe, 0x7c000096, Op_D | Op_A | Op_B | Op_Rc }, { "mfmsr", 0xfc0007fe, 0x7c0000a6, Op_D }, { "ldarx", 0xfc0007fe, 0x7c0000a8, Op_D | Op_A | Op_B }, { "dcbf", 0xfc0007fe, 0x7c0000ac, Op_A | Op_B }, { "lbzx", 0xfc0007fe, 0x7c0000ae, Op_D | Op_A | Op_B }, { "neg", 0xfc0003fe, 0x7c0000d0, Op_D | Op_A | Op_OE | Op_Rc }, { "lbzux", 0xfc0007fe, 0x7c0000ee, Op_D | Op_A | Op_B }, { "nor", 0xfc0007fe, 0x7c0000f8, Op_S | Op_A | Op_B | Op_Rc }, { "wrtee", 0xfc0003ff, 0x7c000106, Op_S }, { "subfe", 0xfc0003fe, 0x7c000110, Op_D | Op_A | Op_B | Op_OE | Op_Rc }, { "adde", 0xfc0003fe, 0x7c000114, Op_D | Op_A | Op_B | Op_OE | Op_Rc }, { "mtcrf", 0xfc0007fe, 0x7c000120, Op_S | Op_CRM }, { "mtmsr", 0xfc0007fe, 0x7c000124, Op_S }, { "stdx", 0xfc0007fe, 0x7c00012a, Op_ST | Op_A | Op_B }, { "stwcx.", 0xfc0007ff, 0x7c00012d, Op_ST | Op_A | Op_B }, { "stwx", 0xfc0007fe, 0x7c00012e, Op_ST | Op_A | Op_B }, { "wrteei", 0xfc0003fe, 0x7c000146, 0 }, /* XXX: out of flags! */ { "stdux", 0xfc0007fe, 0x7c00016a, Op_ST | Op_A | Op_B }, { "stwux", 0xfc0007fe, 0x7c00016e, Op_ST | Op_A | Op_B }, { "subfze", 0xfc0003fe, 0x7c000190, Op_D | Op_A | Op_OE | Op_Rc }, { "addze", 0xfc0003fe, 0x7c000194, Op_D | Op_A | Op_OE | Op_Rc }, { "mtsr", 0xfc0007fe, 0x7c0001a4, Op_S | Op_SR }, { "stdcx.", 0xfc0007ff, 0x7c0001ad, Op_ST | Op_A | Op_B }, { "stbx", 0xfc0007fe, 0x7c0001ae, Op_ST | Op_A | Op_B }, { "subfme", 0xfc0003fe, 0x7c0001d0, Op_D | Op_A | Op_OE | Op_Rc }, { "mulld", 0xfc0003fe, 0x7c0001d2, Op_D | Op_A | Op_B | Op_OE | Op_Rc }, { "addme", 0xfc0003fe, 0x7c0001d4, Op_D | Op_A | Op_OE | Op_Rc }, { "mullw", 0xfc0003fe, 0x7c0001d6, Op_D | Op_A | Op_B | Op_OE | Op_Rc }, { "mtsrin", 0xfc0007fe, 0x7c0001e4, Op_S | Op_B }, { "dcbtst", 0xfc0007fe, 0x7c0001ec, Op_A | Op_B }, { "stbux", 0xfc0007fe, 0x7c0001ee, Op_ST | Op_A | Op_B }, { "add", 0xfc0003fe, 0x7c000214, Op_D | Op_A | Op_B | Op_OE | Op_Rc }, { "dcbt", 0xfc0007fe, 0x7c00022c, Op_A | Op_B }, { "lhzx", 0xfc0007ff, 0x7c00022e, Op_D | Op_A | Op_B }, { "eqv", 0xfc0007fe, 0x7c000238, Op_S | Op_A | Op_B | Op_Rc }, { "tlbie", 0xfc0007fe, 0x7c000264, Op_B }, { "eciwx", 0xfc0007fe, 0x7c00026c, Op_D | Op_A | Op_B }, { "lhzux", 0xfc0007fe, 0x7c00026e, Op_D | Op_A | Op_B }, { "xor", 0xfc0007fe, 0x7c000278, Op_S | Op_A | Op_B | Op_Rc }, { "mfdcr", 0xfc0007fe, 0x7c000286, Op_D | Op_dcr }, { "mfspr", 0xfc0007fe, 0x7c0002a6, Op_D | Op_spr }, { "lwax", 0xfc0007fe, 0x7c0002aa, Op_D | Op_A | Op_B }, { "lhax", 0xfc0007fe, 0x7c0002ae, Op_D | Op_A | Op_B }, { "tlbia", 0xfc0007fe, 0x7c0002e4, 0 }, { "mftb", 0xfc0007fe, 0x7c0002e6, Op_D | Op_tbr }, { "lwaux", 0xfc0007fe, 0x7c0002ea, Op_D | Op_A | Op_B }, { "lhaux", 0xfc0007fe, 0x7c0002ee, Op_D | Op_A | Op_B }, { "sthx", 0xfc0007fe, 0x7c00032e, Op_ST | Op_A | Op_B }, { "orc", 0xfc0007fe, 0x7c000338, Op_S | Op_A | Op_B | Op_Rc }, { "ecowx", 0xfc0007fe, 0x7c00036c, Op_ST | Op_A | Op_B | Op_Rc }, { "slbie", 0xfc0007fc, 0x7c000364, Op_B }, { "sthux", 0xfc0007fe, 0x7c00036e, Op_ST | Op_A | Op_B }, { "or", 0xfc0007fe, 0x7c000378, Op_S | Op_A | Op_B | Op_Rc }, { "mtdcr", 0xfc0007fe, 0x7c000386, Op_S | Op_dcr }, { "divdu", 0xfc0003fe, 0x7c000392, Op_D | Op_A | Op_B | Op_OE | Op_Rc }, { "divwu", 0xfc0003fe, 0x7c000396, Op_D | Op_A | Op_B | Op_OE | Op_Rc }, { "mtspr", 0xfc0007fe, 0x7c0003a6, Op_S | Op_spr }, { "dcbi", 0xfc0007fe, 0x7c0003ac, Op_A | Op_B }, { "nand", 0xfc0007fe, 0x7c0003b8, Op_S | Op_A | Op_B | Op_Rc }, { "dcread", 0xfc0007fe, 0x7c0003cc, Op_D | Op_A | Op_B }, { "divd", 0xfc0003fe, 0x7c0003d2, Op_S | Op_A | Op_B | Op_OE | Op_Rc }, { "divw", 0xfc0003fe, 0x7c0003d6, Op_S | Op_A | Op_B | Op_OE | Op_Rc }, { "slbia", 0xfc0003fe, 0x7c0003e4, Op_S | Op_A | Op_B | Op_OE | Op_Rc }, { "mcrxr", 0xfc0007fe, 0x7c000400, Op_crfD }, { "lswx", 0xfc0007fe, 0x7c00042a, Op_D | Op_A | Op_B }, { "lwbrx", 0xfc0007fe, 0x7c00042c, Op_D | Op_A | Op_B }, { "lfsx", 0xfc0007fe, 0x7c00042e, Op_D | Op_A | Op_B }, { "srw", 0xfc0007fe, 0x7c000430, Op_S | Op_A | Op_B | Op_Rc }, { "srd", 0xfc0007fe, 0x7c000436, Op_S | Op_A | Op_B | Op_Rc }, { "tlbsync", 0xfc0007fe, 0x7c00046c, 0 }, { "lfsux", 0xfc0007fe, 0x7c00046e, Op_D | Op_A | Op_B }, { "mfsr", 0xfc0007fe, 0x7c0004a6, Op_D | Op_SR }, { "lswi", 0xfc0007fe, 0x7c0004aa, Op_D | Op_A | Op_NB }, { "sync", 0xfc6007fe, 0x7c0004ac, 0 }, { "lwsync", 0xfc6007fe, 0x7c2004ac, 0 }, { "ptesync", 0xfc6007fe, 0x7c4004ac, 0 }, { "lfdx", 0xfc0007fe, 0x7c0004ae, Op_D | Op_A | Op_B }, { "lfdux", 0xfc0007fe, 0x7c0004ee, Op_D | Op_A | Op_B }, { "mfsrin", 0xfc0007fe, 0x7c000526, Op_D | Op_B }, { "stswx", 0xfc0007fe, 0x7c00052a, Op_ST | Op_A | Op_B }, { "stwbrx", 0xfc0007fe, 0x7c00052c, Op_ST | Op_A | Op_B }, { "stfsx", 0xfc0007fe, 0x7c00052e, Op_ST | Op_A | Op_B }, { "stfsux", 0xfc0007fe, 0x7c00056e, Op_ST | Op_A | Op_B }, { "stswi", 0xfc0007fe, 0x7c0005aa, Op_ST | Op_A | Op_NB }, { "stfdx", 0xfc0007fe, 0x7c0005ae, Op_ST | Op_A | Op_B }, { "stfdux", 0xfc0007fe, 0x7c0005ee, Op_ST | Op_A | Op_B }, { "lhbrx", 0xfc0007fe, 0x7c00062c, Op_D | Op_A | Op_B }, { "sraw", 0xfc0007fe, 0x7c000630, Op_S | Op_A | Op_B }, { "srad", 0xfc0007fe, 0x7c000634, Op_S | Op_A | Op_B | Op_Rc }, { "srawi", 0xfc0007fe, 0x7c000670, Op_S | Op_A | Op_rSH | Op_Rc }, { "sradi", 0xfc0007fc, 0x7c000674, Op_S | Op_A | Op_sh }, { "eieio", 0xfc0007fe, 0x7c0006ac, 0 }, { "tlbsx", 0xfc0007fe, 0x7c000724, Op_S | Op_A | Op_B | Op_Rc }, { "sthbrx", 0xfc0007fe, 0x7c00072c, Op_ST | Op_A | Op_B }, { "extsh", 0xfc0007fe, 0x7c000734, Op_S | Op_A | Op_Rc }, { "tlbre", 0xfc0007fe, 0x7c000764, Op_D | Op_A | Op_WS }, { "extsb", 0xfc0007fe, 0x7c000774, Op_S | Op_A | Op_Rc }, { "icbi", 0xfc0007fe, 0x7c0007ac, Op_A | Op_B }, { "tlbwe", 0xfc0007fe, 0x7c0007a4, Op_S | Op_A | Op_WS }, { "stfiwx", 0xfc0007fe, 0x7c0007ae, Op_ST | Op_A | Op_B }, { "extsw", 0xfc0007fe, 0x7c0007b4, Op_S | Op_A | Op_Rc }, { "dcbz", 0xfc0007fe, 0x7c0007ec, Op_A | Op_B }, { "", 0x0, 0x0, 0 } }; /* 3a * 4 = e8 */ const struct opcode opcodes_3a[] = { { "ld", 0xfc000003, 0xe8000000, Op_D | Op_A | Op_ds }, { "ldu", 0xfc000003, 0xe8000001, Op_D | Op_A | Op_ds }, { "lwa", 0xfc000003, 0xe8000002, Op_D | Op_A | Op_ds }, { "", 0x0, 0x0, 0 } }; /* 3b * 4 = ec */ const struct opcode opcodes_3b[] = { { "fdivs", 0xfc00003e, 0xec000024, Op_D | Op_A | Op_B | Op_Rc }, { "fsubs", 0xfc00003e, 0xec000028, Op_D | Op_A | Op_B | Op_Rc }, { "fadds", 0xfc00003e, 0xec00002a, Op_D | Op_A | Op_B | Op_Rc }, { "fsqrts", 0xfc00003e, 0xec00002c, Op_D | Op_B | Op_Rc }, { "fres", 0xfc00003e, 0xec000030, Op_D | Op_B | Op_Rc }, { "fmuls", 0xfc00003e, 0xec000032, Op_D | Op_A | Op_C | Op_Rc }, { "fmsubs", 0xfc00003e, 0xec000038, Op_D | Op_A | Op_B | Op_C | Op_Rc }, { "fmadds", 0xfc00003e, 0xec00003a, Op_D | Op_A | Op_B | Op_C | Op_Rc }, { "fnmsubs", 0xfc00003e, 0xec00003c, Op_D | Op_A | Op_B | Op_C | Op_Rc }, { "fnmadds", 0xfc00003e, 0xec00003e, Op_D | Op_A | Op_B | Op_C | Op_Rc }, { "", 0x0, 0x0, 0 } }; /* 3e * 4 = f8 */ const struct opcode opcodes_3e[] = { { "std", 0xfc000003, 0xf8000000, Op_ST | Op_A | Op_ds }, { "stdu", 0xfc000003, 0xf8000001, Op_ST | Op_A | Op_ds }, { "", 0x0, 0x0, 0 } }; /* 3f * 4 = fc */ const struct opcode opcodes_3f[] = { { "fcmpu", 0xfc0007fe, 0xfc000000, Op_crfD | Op_A | Op_B }, { "frsp", 0xfc0007fe, 0xfc000018, Op_D | Op_B | Op_Rc }, { "fctiw", 0xfc0007fe, 0xfc00001c, Op_D | Op_B | Op_Rc }, { "fctiwz", 0xfc0007fe, 0xfc00001e, Op_D | Op_B | Op_Rc }, { "fdiv", 0xfc00003e, 0xfc000024, Op_D | Op_A | Op_B | Op_Rc }, { "fsub", 0xfc00003e, 0xfc000028, Op_D | Op_A | Op_B | Op_Rc }, { "fadd", 0xfc00003e, 0xfc00002a, Op_D | Op_A | Op_B | Op_Rc }, { "fsqrt", 0xfc00003e, 0xfc00002c, Op_D | Op_B | Op_Rc }, { "fsel", 0xfc00003e, 0xfc00002e, Op_D | Op_A | Op_B | Op_C | Op_Rc }, { "fmul", 0xfc00003e, 0xfc000032, Op_D | Op_A | Op_C | Op_Rc }, { "frsqrte", 0xfc00003e, 0xfc000034, Op_D | Op_B | Op_Rc }, { "fmsub", 0xfc00003e, 0xfc000038, Op_D | Op_A | Op_B | Op_C | Op_Rc }, { "fmadd", 0xfc00003e, 0xfc00003a, Op_D | Op_A | Op_B | Op_C | Op_Rc }, { "fnmsub", 0xfc00003e, 0xfc00003c, Op_D | Op_A | Op_B | Op_C | Op_Rc }, { "fnmadd", 0xfc00003e, 0xfc00003e, Op_D | Op_A | Op_B | Op_C | Op_Rc }, { "fcmpo", 0xfc0007fe, 0xfc000040, Op_crfD | Op_A | Op_B }, { "mtfsb1", 0xfc0007fe, 0xfc00004c, Op_crfD | Op_Rc }, { "fneg", 0xfc0007fe, 0xfc000050, Op_D | Op_B | Op_Rc }, { "mcrfs", 0xfc0007fe, 0xfc000080, Op_D | Op_B | Op_Rc }, { "mtfsb0", 0xfc0007fe, 0xfc00008c, Op_crfD | Op_Rc }, { "fmr", 0xfc0007fe, 0xfc000090, Op_D | Op_B | Op_Rc }, { "mtfsfi", 0xfc0007fe, 0xfc00010c, 0 }, /* XXX: out of flags! */ { "fnabs", 0xfc0007fe, 0xfc000110, Op_D | Op_B | Op_Rc }, { "fabs", 0xfc0007fe, 0xfc000210, Op_D | Op_B | Op_Rc }, { "mffs", 0xfc0007fe, 0xfc00048e, Op_D | Op_B | Op_Rc }, { "mtfsf", 0xfc0007fe, 0xfc00058e, Op_FM | Op_B | Op_Rc }, { "fctid", 0xfc0007fe, 0xfc00065c, Op_D | Op_B | Op_Rc }, { "fctidz", 0xfc0007fe, 0xfc00065e, Op_D | Op_B | Op_Rc }, { "fcfid", 0xfc0007fe, 0xfc00069c, Op_D | Op_B | Op_Rc }, { "", 0x0, 0x0, 0 } }; struct specialreg { int reg; const char *name; }; const struct specialreg sprregs[] = { { 0x000, "mq" }, { 0x001, "xer" }, { 0x008, "lr" }, { 0x009, "ctr" }, { 0x012, "dsisr" }, { 0x013, "dar" }, { 0x016, "dec" }, { 0x019, "sdr1" }, { 0x01a, "srr0" }, { 0x01b, "srr1" }, -#ifdef BOOKE_PPC4XX - { 0x100, "usprg0" }, -#else { 0x100, "vrsave" }, -#endif { 0x110, "sprg0" }, { 0x111, "sprg1" }, { 0x112, "sprg2" }, { 0x113, "sprg3" }, { 0x114, "sprg4" }, { 0x115, "sprg5" }, { 0x116, "sprg6" }, { 0x117, "sprg7" }, { 0x118, "asr" }, { 0x11a, "aer" }, { 0x11c, "tbl" }, { 0x11d, "tbu" }, { 0x11f, "pvr" }, { 0x210, "ibat0u" }, { 0x211, "ibat0l" }, { 0x212, "ibat1u" }, { 0x213, "ibat1l" }, { 0x214, "ibat2u" }, { 0x215, "ibat2l" }, { 0x216, "ibat3u" }, { 0x217, "ibat3l" }, { 0x218, "dbat0u" }, { 0x219, "dbat0l" }, { 0x21a, "dbat1u" }, { 0x21b, "dbat1l" }, { 0x21c, "dbat2u" }, { 0x21d, "dbat2l" }, { 0x21e, "dbat3u" }, { 0x21f, "dbat3l" }, { 0x230, "ibat4u" }, { 0x231, "ibat4l" }, { 0x232, "ibat5u" }, { 0x233, "ibat5l" }, { 0x234, "ibat6u" }, { 0x235, "ibat6l" }, { 0x236, "ibat7u" }, { 0x237, "ibat7l" }, { 0x238, "dbat4u" }, { 0x239, "dbat4l" }, { 0x23a, "dbat5u" }, { 0x23b, "dbat5l" }, { 0x23c, "dbat6u" }, { 0x23d, "dbat6l" }, { 0x23e, "dbat7u" }, { 0x23f, "dbat7l" }, { 0x3b0, "zpr" }, { 0x3b1, "pid" }, { 0x3b3, "ccr0" }, { 0x3b4, "iac3" }, { 0x3b5, "iac4" }, { 0x3b6, "dvc1" }, { 0x3b7, "dvc2" }, { 0x3b9, "sgr" }, { 0x3ba, "dcwr" }, { 0x3bb, "sler" }, { 0x3bc, "su0r" }, { 0x3bd, "dbcr1" }, { 0x3d3, "icdbdr" }, { 0x3d4, "esr" }, { 0x3d5, "dear" }, { 0x3d6, "evpr" }, { 0x3d8, "tsr" }, { 0x3da, "tcr" }, { 0x3db, "pit" }, { 0x3de, "srr2" }, { 0x3df, "srr3" }, -#ifdef BOOKE_PPC4XX - { 0x3f0, "dbsr" }, - { 0x3f2, "dbcr0" }, - { 0x3f4, "iac1" }, - { 0x3f5, "iac2" }, - { 0x3f6, "dac1" }, - { 0x3f7, "dac2" }, -#else { 0x3f0, "hid0" }, { 0x3f1, "hid1" }, { 0x3f2, "iabr" }, { 0x3f3, "hid2" }, { 0x3f5, "dabr" }, { 0x3f6, "msscr0" }, { 0x3f7, "msscr1" }, -#endif { 0x3f9, "l2cr" }, { 0x3fa, "dccr" }, { 0x3fb, "iccr" }, { 0x3ff, "pir" }, { 0, NULL } }; const struct specialreg dcrregs[] = { { 0x010, "sdram0_cfgaddr" }, { 0x011, "sdram0_cfgdata" }, { 0x012, "ebc0_cfgaddr" }, { 0x013, "ebc0_cfgdata" }, { 0x014, "dcp0_cfgaddr" }, { 0x015, "dcp0_cfgdata" }, { 0x018, "ocm0_isarc" }, { 0x019, "ocm0_iscntl" }, { 0x01a, "ocm0_dsarc" }, { 0x01b, "ocm0_dscntl" }, { 0x084, "plb0_besr" }, { 0x086, "plb0_bear" }, { 0x087, "plb0_acr" }, { 0x0a0, "pob0_besr0" }, { 0x0a2, "pob0_bear" }, { 0x0a4, "pob0_besr1" }, { 0x0b0, "cpc0_pllmr" }, { 0x0b1, "cpc0_cr0" }, { 0x0b2, "cpc0_cr1" }, { 0x0b4, "cpc0_psr" }, { 0x0b5, "cpc0_jtagid" }, { 0x0b8, "cpc0_sr" }, { 0x0b9, "cpc0_er" }, { 0x0ba, "cpc0_fr" }, { 0x0c0, "uic0_sr" }, { 0x0c2, "uic0_er" }, { 0x0c3, "uic0_cr" }, { 0x0c4, "uic0_pr" }, { 0x0c5, "uic0_tr" }, { 0x0c6, "uic0_msr" }, { 0x0c7, "uic0_vr" }, { 0x0c8, "uic0_vcr" }, { 0x100, "dma0_cr0" }, { 0x101, "dma0_ct0" }, { 0x102, "dma0_da0" }, { 0x103, "dma0_sa0" }, { 0x104, "dma0_sg0" }, { 0x108, "dma0_cr1" }, { 0x109, "dma0_ct1" }, { 0x10a, "dma0_da1" }, { 0x10b, "dma0_sa1" }, { 0x10c, "dma0_sg1" }, { 0x110, "dma0_cr2" }, { 0x111, "dma0_ct2" }, { 0x112, "dma0_da2" }, { 0x113, "dma0_sa2" }, { 0x114, "dma0_sg2" }, { 0x118, "dma0_cr3" }, { 0x119, "dma0_ct3" }, { 0x11a, "dma0_da3" }, { 0x11b, "dma0_sa3" }, { 0x11c, "dma0_sg3" }, { 0x120, "dma0_sr" }, { 0x123, "dma0_sgc" }, { 0x125, "dma0_slp" }, { 0x126, "dma0_pol" }, { 0x180, "mal0_cfg" }, { 0x181, "mal0_esr" }, { 0x182, "mal0_ier" }, { 0x184, "mal0_txcasr" }, { 0x185, "mal0_txcarr" }, { 0x186, "mal0_txeobisr" }, { 0x187, "mal0_txdeir" }, { 0x190, "mal0_rxcasr" }, { 0x191, "mal0_rxcarr" }, { 0x192, "mal0_rxeobisr" }, { 0x193, "mal0_rxdeir" }, { 0x1a0, "mal0_txctp0r" }, { 0x1a1, "mal0_txctp1r" }, { 0x1a2, "mal0_txctp2r" }, { 0x1a3, "mal0_txctp3r" }, { 0x1c0, "mal0_rxctp0r" }, { 0x1e0, "mal0_rcbs0" }, { 0, NULL } }; static const char *condstr[8] = { "ge", "le", "ne", "ns", "lt", "gt", "eq", "so" }; void op_ill(instr_t instr, vm_offset_t loc) { db_printf("illegal instruction %x\n", instr); } u_int32_t extract_field(u_int32_t value, u_int32_t base, u_int32_t width) { u_int32_t mask = (1 << width) - 1; return ((value >> base) & mask); } const struct opcode * search_op(const struct opcode *); void disasm_fields(const struct opcode *popcode, instr_t instr, vm_offset_t loc, char *disasm_str, size_t slen) { char * pstr; enum function_mask func; int len; #define ADD_LEN(s) do { \ len = (s); \ slen -= len; \ pstr += len; \ } while(0) #define APP_PSTR(fmt, arg) ADD_LEN(snprintf(pstr, slen, (fmt), (arg))) #define APP_PSTRS(fmt) ADD_LEN(snprintf(pstr, slen, "%s", (fmt))) pstr = disasm_str; func = popcode->func; if (func & Op_BC) { u_int BO, BI; BO = extract_field(instr, 31 - 10, 5); BI = extract_field(instr, 31 - 15, 5); func &= ~Op_BC; if (BO & 4) { /* standard, no decrement */ if (BO & 16) { if (popcode->code == 0x40000000) { APP_PSTRS("c"); func |= Op_BO | Op_BI; } } else { APP_PSTRS(condstr[((BO & 8) >> 1) + (BI & 3)]); if (BI >= 4) func |= Op_crfS; } } else { /* decrement and branch */ if (BO & 2) APP_PSTRS("dz"); else APP_PSTRS("dnz"); if ((BO & 24) == 0) APP_PSTRS("f"); else if ((BO & 24) == 8) APP_PSTRS("t"); else func |= Op_BI; } if (popcode->code == 0x4c000020) APP_PSTRS("lr"); else if (popcode->code == 0x4c000420) APP_PSTRS("ctr"); if ((BO & 20) != 20 && (func & Op_BO) == 0) func |= Op_BP; /* branch prediction hint */ } if (func & Op_OE) { u_int OE; OE = extract_field(instr, 31 - 21, 1); if (OE) { APP_PSTRS("o"); } func &= ~Op_OE; } switch (func & Op_LKM) { case Op_Rc: if (instr & 0x1) APP_PSTRS("."); break; case Op_AA: if (instr & 0x1) APP_PSTRS("l"); if (instr & 0x2) { APP_PSTRS("a"); loc = 0; /* Absolute address */ } break; case Op_LK: if (instr & 0x1) APP_PSTRS("l"); break; default: func &= ~Op_LKM; } if (func & Op_BP) { int y; y = (instr & 0x200000) != 0; if (popcode->code == 0x40000000) { int BD; BD = extract_field(instr, 31 - 29, 14); BD = BD << 18; BD = BD >> 16; BD += loc; if ((vm_offset_t)BD < loc) y ^= 1; } APP_PSTR("%c", y ? '+' : '-'); func &= ~Op_BP; } APP_PSTRS("\t"); /* XXX: special cases here, out of flags in a 32bit word. */ if (strcmp(popcode->name, "wrteei") == 0) { int E; E = extract_field(instr, 31 - 16, 5); APP_PSTR("%d", E); return; } else if (strcmp(popcode->name, "mtfsfi") == 0) { u_int UI; UI = extract_field(instr, 31 - 8, 3); APP_PSTR("crf%u, ", UI); UI = extract_field(instr, 31 - 19, 4); APP_PSTR("0x%x", UI); } /* XXX: end of special cases here. */ if ((func & Op_FM) == Op_FM) { u_int FM; FM = extract_field(instr, 31 - 14, 8); APP_PSTR("0x%x, ", FM); func &= ~Op_FM; } if (func & Op_D) { /* Op_ST is the same */ u_int D; D = extract_field(instr, 31 - 10, 5); APP_PSTR("r%d, ", D); func &= ~Op_D; } if (func & Op_crbD) { u_int crbD; crbD = extract_field(instr, 31 - 10, 5); APP_PSTR("crb%d, ", crbD); func &= ~Op_crbD; } if (func & Op_crfD) { u_int crfD; crfD = extract_field(instr, 31 - 8, 3); APP_PSTR("crf%d, ", crfD); func &= ~Op_crfD; } if (func & Op_TO) { u_int TO; TO = extract_field(instr, 31 - 10, 1); APP_PSTR("%d, ", TO); func &= ~Op_TO; } if (func & Op_crfS) { u_int crfS; crfS = extract_field(instr, 31 - 13, 3); APP_PSTR("crf%d, ", crfS); func &= ~Op_crfS; } if (func & Op_CRM) { u_int CRM; CRM = extract_field(instr, 31 - 19, 8); APP_PSTR("0x%x, ", CRM); func &= ~Op_CRM; } if (func & Op_BO) { u_int BO; BO = extract_field(instr, 31 - 10, 5); APP_PSTR("%d, ", BO); func &= ~Op_BO; } if (func & Op_BI) { u_int BI; BI = extract_field(instr, 31 - 15, 5); APP_PSTR("%d, ", BI); func &= ~Op_BI; } if (func & Op_dA) { /* register A indirect with displacement */ u_int A; A = extract_field(instr, 31 - 31, 16); if (A & 0x8000) { APP_PSTRS("-"); A = 0x10000-A; } APP_PSTR("0x%x", A); A = extract_field(instr, 31 - 15, 5); APP_PSTR("(r%d)", A); func &= ~Op_dA; } if (func & Op_spr) { u_int spr; u_int sprl; u_int sprh; const struct specialreg *regs; int i; sprl = extract_field(instr, 31 - 15, 5); sprh = extract_field(instr, 31 - 20, 5); spr = sprh << 5 | sprl; /* ugly hack - out of bitfields in the function mask */ if (popcode->name[2] == 'd') /* m.Dcr */ regs = dcrregs; else regs = sprregs; for (i = 0; regs[i].name != NULL; i++) if (spr == regs[i].reg) break; if (regs[i].name == NULL) APP_PSTR("[unknown special reg (%d)]", spr); else APP_PSTR("%s", regs[i].name); if (popcode->name[1] == 't') /* spr is destination */ APP_PSTRS(", "); func &= ~Op_spr; } if (func & Op_SR) { u_int SR; SR = extract_field(instr, 31 - 15, 3); APP_PSTR("sr%d", SR); if (popcode->name[1] == 't') /* SR is destination */ APP_PSTRS(", "); func &= ~Op_SR; } if (func & Op_A) { u_int A; A = extract_field(instr, 31 - 15, 5); APP_PSTR("r%d, ", A); func &= ~Op_A; } if (func & Op_S) { u_int D; D = extract_field(instr, 31 - 10, 5); APP_PSTR("r%d, ", D); func &= ~Op_S; } if (func & Op_C) { u_int C; C = extract_field(instr, 31 - 25, 5); APP_PSTR("r%d, ", C); func &= ~Op_C; } if (func & Op_B) { u_int B; B = extract_field(instr, 31 - 20, 5); APP_PSTR("r%d", B); func &= ~Op_B; } if (func & Op_crbA) { u_int crbA; crbA = extract_field(instr, 31 - 15, 5); APP_PSTR("%d, ", crbA); func &= ~Op_crbA; } if (func & Op_crbB) { u_int crbB; crbB = extract_field(instr, 31 - 20, 5); APP_PSTR("%d, ", crbB); func &= ~Op_crbB; } if (func & Op_LI) { int LI; LI = extract_field(instr, 31 - 29, 24); LI = LI << 8; LI = LI >> 6; LI += loc; APP_PSTR("0x%x", LI); func &= ~Op_LI; } switch (func & Op_SIMM) { u_int IMM; case Op_SIMM: /* same as Op_d */ IMM = extract_field(instr, 31 - 31, 16); if (IMM & 0x8000) { APP_PSTRS("-"); IMM = 0x10000-IMM; } func &= ~Op_SIMM; goto common; case Op_UIMM: IMM = extract_field(instr, 31 - 31, 16); func &= ~Op_UIMM; goto common; common: APP_PSTR("0x%x", IMM); break; default: ; } if (func & Op_BD) { int BD; BD = extract_field(instr, 31 - 29, 14); BD = BD << 18; BD = BD >> 16; BD += loc; /* Need to sign extend and shift up 2, then add addr */ APP_PSTR("0x%x", BD); func &= ~Op_BD; } if (func & Op_ds) { u_int ds; ds = extract_field(instr, 31 - 29, 14) << 2; APP_PSTR("0x%x", ds); func &= ~Op_ds; } if (func & Op_me) { u_int me, mel, meh; mel = extract_field(instr, 31 - 25, 4); meh = extract_field(instr, 31 - 26, 1); me = meh << 4 | mel; APP_PSTR(", 0x%x", me); func &= ~Op_me; } if ((func & Op_SH) && (func & Op_sh_mb_sh)) { u_int SH; SH = extract_field(instr, 31 - 20, 5); APP_PSTR("%d", SH); } if ((func & Op_MB) && (func & Op_sh_mb_sh)) { u_int MB; u_int ME; MB = extract_field(instr, 31 - 25, 5); APP_PSTR(", %d", MB); ME = extract_field(instr, 31 - 30, 5); APP_PSTR(", %d", ME); } if ((func & Op_sh) && ! (func & Op_sh_mb_sh)) { u_int sh, shl, shh; shl = extract_field(instr, 31 - 19, 4); shh = extract_field(instr, 31 - 20, 1); sh = shh << 4 | shl; APP_PSTR(", %d", sh); } if ((func & Op_mb) && ! (func & Op_sh_mb_sh)) { u_int mb, mbl, mbh; mbl = extract_field(instr, 31 - 25, 4); mbh = extract_field(instr, 31 - 26, 1); mb = mbh << 4 | mbl; APP_PSTR(", %d", mb); } if ((func & Op_me) && ! (func & Op_sh_mb_sh)) { u_int me, mel, meh; mel = extract_field(instr, 31 - 25, 4); meh = extract_field(instr, 31 - 26, 1); me = meh << 4 | mel; APP_PSTR(", %d", me); } if (func & Op_tbr) { u_int tbr; u_int tbrl; u_int tbrh; const char *reg; tbrl = extract_field(instr, 31 - 15, 5); tbrh = extract_field(instr, 31 - 20, 5); tbr = tbrh << 5 | tbrl; switch (tbr) { case 268: reg = "tbl"; break; case 269: reg = "tbu"; break; default: reg = NULL; } if (reg == NULL) APP_PSTR(", [unknown tbr %d ]", tbr); else APP_PSTR(", %s", reg); func &= ~Op_tbr; } if (func & Op_NB) { u_int NB; NB = extract_field(instr, 31 - 20, 5); if (NB == 0) NB = 32; APP_PSTR(", %d", NB); func &= ~Op_SR; } #undef ADD_LEN #undef APP_PSTR #undef APP_PSTRS } void op_base(instr_t instr, vm_offset_t loc) { dis_ppc(opcodes, instr, loc); } void op_cl_x13(instr_t instr, vm_offset_t loc) { dis_ppc(opcodes_13, instr, loc); } void op_cl_x1e(instr_t instr, vm_offset_t loc) { dis_ppc(opcodes_1e, instr, loc); } void op_cl_x1f(instr_t instr, vm_offset_t loc) { dis_ppc(opcodes_1f, instr, loc); } void op_cl_x3a(instr_t instr, vm_offset_t loc) { dis_ppc(opcodes_3a, instr, loc); } void op_cl_x3b(instr_t instr, vm_offset_t loc) { dis_ppc(opcodes_3b, instr, loc); } void op_cl_x3e(instr_t instr, vm_offset_t loc) { dis_ppc(opcodes_3e, instr, loc); } void op_cl_x3f(instr_t instr, vm_offset_t loc) { dis_ppc(opcodes_3f, instr, loc); } void dis_ppc(const struct opcode *opcodeset, instr_t instr, vm_offset_t loc) { const struct opcode *op; int found = 0; int i; char disasm_str[80]; for (i = 0, op = &opcodeset[0]; found == 0 && op->mask != 0; i++, op = &opcodeset[i]) { if ((instr & op->mask) == op->code) { found = 1; disasm_fields(op, instr, loc, disasm_str, sizeof disasm_str); db_printf("%s%s\n", op->name, disasm_str); return; } } op_ill(instr, loc); } db_addr_t db_disasm(db_addr_t loc, bool extended) { int class; instr_t opcode; opcode = *(instr_t *)(loc); if (extended) db_printf("|%08x| ", opcode); class = opcode >> 26; (opcodes_base[class])(opcode, loc); return (loc + 4); } vm_offset_t opc_disasm(vm_offset_t loc, int); vm_offset_t opc_disasm(vm_offset_t loc, int xin) { int class; instr_t opcode; opcode = xin; class = opcode >> 26; (opcodes_base[class])(opcode, loc); return (loc + 4); }