Index: stable/12/sys/arm64/conf/GENERIC =================================================================== --- stable/12/sys/arm64/conf/GENERIC (revision 358640) +++ stable/12/sys/arm64/conf/GENERIC (revision 358641) @@ -1,304 +1,306 @@ # # GENERIC -- Generic kernel configuration file for FreeBSD/arm64 # # For more information on this file, please read the config(5) manual page, # and/or the handbook section on Kernel Configuration Files: # # https://www.FreeBSD.org/doc/en_US.ISO8859-1/books/handbook/kernelconfig-config.html # # The handbook is also available locally in /usr/share/doc/handbook # if you've installed the doc distribution, otherwise always see the # FreeBSD World Wide Web server (https://www.FreeBSD.org/) for the # latest information. # # An exhaustive list of options and more detailed explanations of the # device lines is also present in the ../../conf/NOTES and NOTES files. # If you are in doubt as to the purpose or necessity of a line, check first # in NOTES. # # $FreeBSD$ cpu ARM64 ident GENERIC makeoptions DEBUG=-g # Build kernel with gdb(1) debug symbols makeoptions WITH_CTF=1 # Run ctfconvert(1) for DTrace support options SCHED_ULE # ULE scheduler options PREEMPTION # Enable kernel thread preemption options VIMAGE # Subsystem virtualization, e.g. VNET options INET # InterNETworking options INET6 # IPv6 communications protocols options IPSEC # IP (v4/v6) security options IPSEC_SUPPORT # Allow kldload of ipsec and tcpmd5 options TCP_HHOOK # hhook(9) framework for TCP options TCP_OFFLOAD # TCP offload options TCP_RFC7413 # TCP Fast Open options SCTP # Stream Control Transmission Protocol options FFS # Berkeley Fast Filesystem options SOFTUPDATES # Enable FFS soft updates support options UFS_ACL # Support for access control lists options UFS_DIRHASH # Improve performance on big directories options UFS_GJOURNAL # Enable gjournal-based UFS journaling options QUOTA # Enable disk quotas for UFS options MD_ROOT # MD is a potential root device options NFSCL # Network Filesystem Client options NFSD # Network Filesystem Server options NFSLOCKD # Network Lock Manager options NFS_ROOT # NFS usable as /, requires NFSCL options MSDOSFS # MSDOS Filesystem options CD9660 # ISO 9660 Filesystem options PROCFS # Process filesystem (requires PSEUDOFS) options PSEUDOFS # Pseudo-filesystem framework options GEOM_RAID # Soft RAID functionality. options GEOM_LABEL # Provides labelization options COMPAT_FREEBSD32 # Incomplete, but used by cloudabi32.ko. options COMPAT_FREEBSD11 # Compatible with FreeBSD11 options SCSI_DELAY=5000 # Delay (in ms) before probing SCSI options KTRACE # ktrace(1) support options STACK # stack(9) support options SYSVSHM # SYSV-style shared memory options SYSVMSG # SYSV-style message queues options SYSVSEM # SYSV-style semaphores options _KPOSIX_PRIORITY_SCHEDULING # POSIX P1003_1B real-time extensions options PRINTF_BUFR_SIZE=128 # Prevent printf output being interspersed. options KBD_INSTALL_CDEV # install a CDEV entry in /dev options HWPMC_HOOKS # Necessary kernel hooks for hwpmc(4) options AUDIT # Security event auditing options CAPABILITY_MODE # Capsicum capability mode options CAPABILITIES # Capsicum capabilities options MAC # TrustedBSD MAC Framework options KDTRACE_FRAME # Ensure frames are compiled in options KDTRACE_HOOKS # Kernel DTrace hooks options VFP # Floating-point support options RACCT # Resource accounting framework options RACCT_DEFAULT_TO_DISABLED # Set kern.racct.enable=0 by default options RCTL # Resource limits options SMP options INTRNG # Debugging support. Always need this: options KDB # Enable kernel debugger support. options KDB_TRACE # Print a stack trace for a panic. # Kernel dump features. options EKCD # Support for encrypted kernel dumps options GZIO # gzip-compressed kernel and user dumps options ZSTDIO # zstd-compressed kernel and user dumps options NETDUMP # netdump(4) client support # SoC support options SOC_ALLWINNER_A64 options SOC_ALLWINNER_H5 options SOC_CAVM_THUNDERX options SOC_HISI_HI6220 options SOC_BRCM_BCM2837 options SOC_BRCM_BCM2838 options SOC_MARVELL_8K options SOC_ROCKCHIP_RK3328 options SOC_ROCKCHIP_RK3399 options SOC_XILINX_ZYNQ # Timer drivers device a10_timer # Annapurna Alpine drivers device al_ccu # Alpine Cache Coherency Unit device al_nb_service # Alpine North Bridge Service device al_iofic # I/O Fabric Interrupt Controller device al_serdes # Serializer/Deserializer device al_udma # Universal DMA # Qualcomm Snapdragon drivers device qcom_gcc # Global Clock Controller # VirtIO support device virtio device virtio_pci device virtio_mmio device virtio_blk device vtnet # CPU frequency control device cpufreq # Bus drivers device pci device al_pci # Annapurna Alpine PCI-E options PCI_HP # PCI-Express native HotPlug options PCI_IOV # PCI SR-IOV support # PCI/PCI-X/PCIe Ethernet NICs that use iflib infrastructure device iflib device em # Intel PRO/1000 Gigabit Ethernet Family device ix # Intel 10Gb Ethernet Family # Ethernet NICs device mdio device mii device miibus # MII bus support device awg # Allwinner EMAC Gigabit Ethernet device axgbe # AMD Opteron A1100 integrated NIC device msk # Marvell/SysKonnect Yukon II Gigabit Ethernet device neta # Marvell Armada 370/38x/XP/3700 NIC device smc # SMSC LAN91C111 device vnic # Cavium ThunderX NIC device al_eth # Annapurna Alpine Ethernet NIC device dwc_rk # Rockchip Designware # Block devices device ahci device scbus device da # ATA/SCSI peripherals device pass # Passthrough device (direct ATA/SCSI access) # NVM Express (NVMe) support device nvme # base NVMe driver options NVME_USE_NVD=0 # prefer the cam(4) based nda(4) driver device nvd # expose NVMe namespaces as disks, depends on nvme # MMC/SD/SDIO Card slot support device sdhci device sdhci_xenon # Marvell Xenon SD/MMC controller device aw_mmc # Allwinner SD/MMC controller device mmc # mmc/sd bus device mmcsd # mmc/sd flash cards device dwmmc device rk_emmcphy # Serial (COM) ports device uart # Generic UART driver device uart_msm # Qualcomm MSM UART driver device uart_mu # RPI3 aux port device uart_mvebu # Armada 3700 UART driver device uart_ns8250 # ns8250-type UART driver device uart_snps device pl011 # USB support device aw_usbphy # Allwinner USB PHY device rk_usb2phy # Rockchip USB2PHY +device rk_typec_phy # Rockchip TypeC PHY device dwcotg # DWC OTG controller device ohci # OHCI USB interface device ehci # EHCI USB interface (USB 2.0) device ehci_mv # Marvell EHCI USB interface device xhci # XHCI PCI->USB interface (USB 3.0) device usb # USB Bus (required) device ukbd # Keyboard device umass # Disks/Mass storage - Requires scbus and da # USB ethernet support device muge device smcphy device smsc # Sound support device sound device a10_codec # DMA controller device a31_dmac # GPIO / PINCTRL device a37x0_gpio # Marvell Armada 37x0 GPIO controller device aw_gpio # Allwinner GPIO controller device gpio device gpioled device fdt_pinctrl device gpioregulator device mv_gpio # Marvell GPIO controller device mvebu_pinctrl # Marvell Pinmux Controller device rk_gpio # RockChip GPIO Controller device rk_pinctrl # RockChip Pinmux Controller # I2C device aw_rsb # Allwinner Reduced Serial Bus device bcm2835_bsc # Broadcom BCM283x I2C bus device iicbus device iic device twsi # Allwinner I2C controller device syr827 # Silergy SYR827 PMIC device rk_i2c # RockChip I2C controller # Clock and reset controllers device aw_ccu # Allwinner clock controller # Interrupt controllers device aw_nmi # Allwinner NMI support device mv_cp110_icu # Marvell CP110 ICU device mv_ap806_gicp # Marvell AP806 GICP # Real-time clock support device aw_rtc # Allwinner Real-time Clock device mv_rtc # Marvell Real-time Clock # Watchdog controllers device aw_wdog # Allwinner Watchdog # Power management controllers device axp81x # X-Powers AXP81x PMIC device rk805 # RockChip RK805 PMIC # EFUSE device aw_sid # Allwinner Secure ID EFUSE # Thermal sensors device aw_thermal # Allwinner Thermal Sensor Controller device mv_thermal # Marvell Thermal Sensor Controller # SPI device spibus device bcm2835_spi # Broadcom BCM283x SPI bus +device rk_spi # RockChip SPI controller # PWM device pwm device aw_pwm # Console device vt device kbdmux device vt_efifb # EVDEV support device evdev # input event device support options EVDEV_SUPPORT # evdev support in legacy drivers device uinput # install /dev/uinput cdev # Pseudo devices. device crypto # core crypto support device loop # Network loopback device random # Entropy device device ether # Ethernet support device vlan # 802.1Q VLAN support device tuntap # Packet tunnel. device md # Memory "disks" device gif # IPv6 and IPv4 tunneling device firmware # firmware assist module options EFIRT # EFI Runtime Services # EXT_RESOURCES pseudo devices options EXT_RESOURCES device clk device phy device hwreset device nvmem device regulator device syscon device aw_syscon # The `bpf' device enables the Berkeley Packet Filter. # Be aware of the administrative consequences of enabling this! # Note that 'bpf' is required for DHCP. device bpf # Berkeley packet filter # Chip-specific errata options THUNDERX_PASS_1_1_ERRATA options FDT device acpi # DTBs makeoptions MODULES_EXTRA="dtb/allwinner dtb/rockchip dtb/rpi" Index: stable/12/sys/arm64/rockchip/clk/rk3399_cru.c =================================================================== --- stable/12/sys/arm64/rockchip/clk/rk3399_cru.c (revision 358640) +++ stable/12/sys/arm64/rockchip/clk/rk3399_cru.c (revision 358641) @@ -1,1696 +1,2028 @@ /*- * SPDX-License-Identifier: BSD-2-Clause-FreeBSD * * Copyright (c) 2018 Emmanuel Vadot * Copyright (c) 2018 Greg V * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. * * $FreeBSD$ */ #include __FBSDID("$FreeBSD$"); #include #include #include #include #include #include #include #include #include #include #include #include #include #include /* GATES */ #define SCLK_USB2PHY0_REF 123 #define SCLK_USB2PHY1_REF 124 +#define SCLK_USB3OTG0_REF 129 +#define SCLK_USB3OTG1_REF 130 +#define SCLK_USB3OTG0_SUSPEND 131 +#define SCLK_USB3OTG1_SUSPEND 132 #define ACLK_EMMC_CORE 241 #define ACLK_EMMC_NOC 242 #define ACLK_EMMC_GRF 243 +#define ACLK_USB3_NOC 245 +#define ACLK_USB3OTG0 246 +#define ACLK_USB3OTG1 247 +#define ACLK_USB3_RKSOC_AXI_PERF 248 +#define ACLK_USB3_GRF 249 #define PCLK_GPIO2 336 #define PCLK_GPIO3 337 #define PCLK_GPIO4 338 #define PCLK_I2C1 341 #define PCLK_I2C2 342 #define PCLK_I2C3 343 #define PCLK_I2C5 344 #define PCLK_I2C6 345 #define PCLK_I2C7 346 +#define PCLK_SPI0 347 +#define PCLK_SPI1 348 +#define PCLK_SPI2 349 +#define PCLK_SPI4 350 +#define PCLK_SPI5 351 #define HCLK_HOST0 456 #define HCLK_HOST0_ARB 457 #define HCLK_HOST1 458 #define HCLK_HOST1_ARB 459 #define HCLK_SDMMC 462 static struct rk_cru_gate rk3399_gates[] = { /* CRU_CLKGATE_CON0 */ CRU_GATE(0, "clk_core_l_lpll_src", "lpll", 0x300, 0) CRU_GATE(0, "clk_core_l_bpll_src", "bpll", 0x300, 1) CRU_GATE(0, "clk_core_l_dpll_src", "dpll", 0x300, 2) CRU_GATE(0, "clk_core_l_gpll_src", "gpll", 0x300, 3) /* CRU_CLKGATE_CON1 */ CRU_GATE(0, "clk_core_b_lpll_src", "lpll", 0x304, 0) CRU_GATE(0, "clk_core_b_bpll_src", "bpll", 0x304, 1) CRU_GATE(0, "clk_core_b_dpll_src", "dpll", 0x304, 2) CRU_GATE(0, "clk_core_b_gpll_src", "gpll", 0x304, 3) /* CRU_CLKGATE_CON5 */ CRU_GATE(0, "cpll_aclk_perihp_src", "cpll", 0x314, 0) CRU_GATE(0, "gpll_aclk_perihp_src", "gpll", 0x314, 1) /* CRU_CLKGATE_CON6 */ CRU_GATE(0, "gpll_aclk_emmc_src", "gpll", 0x318, 12) CRU_GATE(0, "cpll_aclk_emmc_src", "cpll", 0x318, 13) CRU_GATE(SCLK_USB2PHY0_REF, "clk_usb2phy0_ref", "xin24m", 0x318, 5) CRU_GATE(SCLK_USB2PHY1_REF, "clk_usb2phy1_ref", "xin24m", 0x318, 6) /* CRU_CLKGATE_CON7 */ CRU_GATE(0, "gpll_aclk_perilp0_src", "gpll", 0x31C, 0) CRU_GATE(0, "cpll_aclk_perilp0_src", "cpll", 0x31C, 1) /* CRU_CLKGATE_CON8 */ CRU_GATE(0, "hclk_perilp1_cpll_src", "cpll", 0x320, 1) CRU_GATE(0, "hclk_perilp1_gpll_src", "gpll", 0x320, 0) + /* CRU_CLKGATE_CON12 */ + CRU_GATE(SCLK_USB3OTG0_REF, "sclk_usb3otg0_ref", "xin24m", 0x330, 1) + CRU_GATE(SCLK_USB3OTG1_REF, "sclk_usb3otg1_ref", "xin24m", 0x330, 2) + CRU_GATE(SCLK_USB3OTG0_SUSPEND, "sclk_usb3otg0_suspend", "xin24m", 0x330, 3) + CRU_GATE(SCLK_USB3OTG1_SUSPEND, "sclk_usb3otg1_suspend", "xin24m", 0x330, 4) + /* CRU_CLKGATE_CON20 */ CRU_GATE(HCLK_HOST0, "hclk_host0", "hclk_perihp", 0x350, 5) CRU_GATE(HCLK_HOST0_ARB, "hclk_host0_arb", "hclk_perihp", 0x350, 6) CRU_GATE(HCLK_HOST1, "hclk_host1", "hclk_perihp", 0x350, 7) CRU_GATE(HCLK_HOST1_ARB, "hclk_host1_arb", "hclk_perihp", 0x350, 8) /* CRU_CLKGATE_CON22 */ CRU_GATE(PCLK_I2C7, "pclk_rki2c7", "pclk_perilp1", 0x358, 5) CRU_GATE(PCLK_I2C1, "pclk_rki2c1", "pclk_perilp1", 0x358, 6) CRU_GATE(PCLK_I2C5, "pclk_rki2c5", "pclk_perilp1", 0x358, 7) CRU_GATE(PCLK_I2C6, "pclk_rki2c6", "pclk_perilp1", 0x358, 8) CRU_GATE(PCLK_I2C2, "pclk_rki2c2", "pclk_perilp1", 0x358, 9) CRU_GATE(PCLK_I2C3, "pclk_rki2c3", "pclk_perilp1", 0x358, 10) + /* CRU_CLKGATE_CON23 */ + CRU_GATE(PCLK_SPI0, "pclk_spi0", "pclk_perilp1", 0x35C, 10) + CRU_GATE(PCLK_SPI1, "pclk_spi1", "pclk_perilp1", 0x35C, 11) + CRU_GATE(PCLK_SPI2, "pclk_spi2", "pclk_perilp1", 0x35C, 12) + CRU_GATE(PCLK_SPI4, "pclk_spi4", "pclk_perilp1", 0x35C, 13) + + /* CRU_CLKGATE_CON30 */ + CRU_GATE(ACLK_USB3_NOC, "aclk_usb3_noc", "aclk_usb3", 0x378, 0) + CRU_GATE(ACLK_USB3OTG0, "aclk_usb3otg0", "aclk_usb3", 0x378, 1) + CRU_GATE(ACLK_USB3OTG1, "aclk_usb3otg1", "aclk_usb3", 0x378, 2) + CRU_GATE(ACLK_USB3_RKSOC_AXI_PERF, "aclk_usb3_rksoc_axi_perf", "aclk_usb3", 0x378, 3) + CRU_GATE(ACLK_USB3_GRF, "aclk_usb3_grf", "aclk_usb3", 0x378, 4) + /* CRU_CLKGATE_CON31 */ CRU_GATE(PCLK_GPIO2, "pclk_gpio2", "pclk_alive", 0x37c, 3) CRU_GATE(PCLK_GPIO3, "pclk_gpio3", "pclk_alive", 0x37c, 4) CRU_GATE(PCLK_GPIO4, "pclk_gpio4", "pclk_alive", 0x37c, 5) /* CRU_CLKGATE_CON32 */ CRU_GATE(ACLK_EMMC_CORE, "aclk_emmccore", "aclk_emmc", 0x380, 8) CRU_GATE(ACLK_EMMC_NOC, "aclk_emmc_noc", "aclk_emmc", 0x380, 9) CRU_GATE(ACLK_EMMC_GRF, "aclk_emmcgrf", "aclk_emmc", 0x380, 10) /* CRU_CLKGATE_CON33 */ CRU_GATE(HCLK_SDMMC, "hclk_sdmmc", "hclk_sd", 0x384, 8) + + /* CRU_CLKGATE_CON34 */ + CRU_GATE(PCLK_SPI4, "pclk_spi5", "pclk_perilp1", 0x388, 5) }; /* * PLLs */ #define PLL_APLLL 1 #define PLL_APLLB 2 #define PLL_DPLL 3 #define PLL_CPLL 4 #define PLL_GPLL 5 #define PLL_NPLL 6 #define PLL_VPLL 7 static struct rk_clk_pll_rate rk3399_pll_rates[] = { { .freq = 2208000000, .refdiv = 1, .fbdiv = 92, .postdiv1 = 1, .postdiv2 = 1, .dsmpd = 1, }, { .freq = 2184000000, .refdiv = 1, .fbdiv = 91, .postdiv1 = 1, .postdiv2 = 1, .dsmpd = 1, }, { .freq = 2160000000, .refdiv = 1, .fbdiv = 90, .postdiv1 = 1, .postdiv2 = 1, .dsmpd = 1, }, { .freq = 2136000000, .refdiv = 1, .fbdiv = 89, .postdiv1 = 1, .postdiv2 = 1, .dsmpd = 1, }, { .freq = 2112000000, .refdiv = 1, .fbdiv = 88, .postdiv1 = 1, .postdiv2 = 1, .dsmpd = 1, }, { .freq = 2088000000, .refdiv = 1, .fbdiv = 87, .postdiv1 = 1, .postdiv2 = 1, .dsmpd = 1, }, { .freq = 2064000000, .refdiv = 1, .fbdiv = 86, .postdiv1 = 1, .postdiv2 = 1, .dsmpd = 1, }, { .freq = 2040000000, .refdiv = 1, .fbdiv = 85, .postdiv1 = 1, .postdiv2 = 1, .dsmpd = 1, }, { .freq = 2016000000, .refdiv = 1, .fbdiv = 84, .postdiv1 = 1, .postdiv2 = 1, .dsmpd = 1, }, { .freq = 1992000000, .refdiv = 1, .fbdiv = 83, .postdiv1 = 1, .postdiv2 = 1, .dsmpd = 1, }, { .freq = 1968000000, .refdiv = 1, .fbdiv = 82, .postdiv1 = 1, .postdiv2 = 1, .dsmpd = 1, }, { .freq = 1944000000, .refdiv = 1, .fbdiv = 81, .postdiv1 = 1, .postdiv2 = 1, .dsmpd = 1, }, { .freq = 1920000000, .refdiv = 1, .fbdiv = 80, .postdiv1 = 1, .postdiv2 = 1, .dsmpd = 1, }, { .freq = 1896000000, .refdiv = 1, .fbdiv = 79, .postdiv1 = 1, .postdiv2 = 1, .dsmpd = 1, }, { .freq = 1872000000, .refdiv = 1, .fbdiv = 78, .postdiv1 = 1, .postdiv2 = 1, .dsmpd = 1, }, { .freq = 1848000000, .refdiv = 1, .fbdiv = 77, .postdiv1 = 1, .postdiv2 = 1, .dsmpd = 1, }, { .freq = 1824000000, .refdiv = 1, .fbdiv = 76, .postdiv1 = 1, .postdiv2 = 1, .dsmpd = 1, }, { .freq = 1800000000, .refdiv = 1, .fbdiv = 75, .postdiv1 = 1, .postdiv2 = 1, .dsmpd = 1, }, { .freq = 1776000000, .refdiv = 1, .fbdiv = 74, .postdiv1 = 1, .postdiv2 = 1, .dsmpd = 1, }, { .freq = 1752000000, .refdiv = 1, .fbdiv = 73, .postdiv1 = 1, .postdiv2 = 1, .dsmpd = 1, }, { .freq = 1728000000, .refdiv = 1, .fbdiv = 72, .postdiv1 = 1, .postdiv2 = 1, .dsmpd = 1, }, { .freq = 1704000000, .refdiv = 1, .fbdiv = 71, .postdiv1 = 1, .postdiv2 = 1, .dsmpd = 1, }, { .freq = 1680000000, .refdiv = 1, .fbdiv = 70, .postdiv1 = 1, .postdiv2 = 1, .dsmpd = 1, }, { .freq = 1656000000, .refdiv = 1, .fbdiv = 69, .postdiv1 = 1, .postdiv2 = 1, .dsmpd = 1, }, { .freq = 1632000000, .refdiv = 1, .fbdiv = 68, .postdiv1 = 1, .postdiv2 = 1, .dsmpd = 1, }, { .freq = 1608000000, .refdiv = 1, .fbdiv = 67, .postdiv1 = 1, .postdiv2 = 1, .dsmpd = 1, }, { .freq = 1600000000, .refdiv = 3, .fbdiv = 200, .postdiv1 = 1, .postdiv2 = 1, .dsmpd = 1, }, { .freq = 1584000000, .refdiv = 1, .fbdiv = 66, .postdiv1 = 1, .postdiv2 = 1, .dsmpd = 1, }, { .freq = 1560000000, .refdiv = 1, .fbdiv = 65, .postdiv1 = 1, .postdiv2 = 1, .dsmpd = 1, }, { .freq = 1536000000, .refdiv = 1, .fbdiv = 64, .postdiv1 = 1, .postdiv2 = 1, .dsmpd = 1, }, { .freq = 1512000000, .refdiv = 1, .fbdiv = 63, .postdiv1 = 1, .postdiv2 = 1, .dsmpd = 1, }, { .freq = 1488000000, .refdiv = 1, .fbdiv = 62, .postdiv1 = 1, .postdiv2 = 1, .dsmpd = 1, }, { .freq = 1464000000, .refdiv = 1, .fbdiv = 61, .postdiv1 = 1, .postdiv2 = 1, .dsmpd = 1, }, { .freq = 1440000000, .refdiv = 1, .fbdiv = 60, .postdiv1 = 1, .postdiv2 = 1, .dsmpd = 1, }, { .freq = 1416000000, .refdiv = 1, .fbdiv = 59, .postdiv1 = 1, .postdiv2 = 1, .dsmpd = 1, }, { .freq = 1392000000, .refdiv = 1, .fbdiv = 58, .postdiv1 = 1, .postdiv2 = 1, .dsmpd = 1, }, { .freq = 1368000000, .refdiv = 1, .fbdiv = 57, .postdiv1 = 1, .postdiv2 = 1, .dsmpd = 1, }, { .freq = 1344000000, .refdiv = 1, .fbdiv = 56, .postdiv1 = 1, .postdiv2 = 1, .dsmpd = 1, }, { .freq = 1320000000, .refdiv = 1, .fbdiv = 55, .postdiv1 = 1, .postdiv2 = 1, .dsmpd = 1, }, { .freq = 1296000000, .refdiv = 1, .fbdiv = 54, .postdiv1 = 1, .postdiv2 = 1, .dsmpd = 1, }, { .freq = 1272000000, .refdiv = 1, .fbdiv = 53, .postdiv1 = 1, .postdiv2 = 1, .dsmpd = 1, }, { .freq = 1248000000, .refdiv = 1, .fbdiv = 52, .postdiv1 = 1, .postdiv2 = 1, .dsmpd = 1, }, { .freq = 1200000000, .refdiv = 1, .fbdiv = 50, .postdiv1 = 1, .postdiv2 = 1, .dsmpd = 1, }, { .freq = 1188000000, .refdiv = 2, .fbdiv = 99, .postdiv1 = 1, .postdiv2 = 1, .dsmpd = 1, }, { .freq = 1104000000, .refdiv = 1, .fbdiv = 46, .postdiv1 = 1, .postdiv2 = 1, .dsmpd = 1, }, { .freq = 1100000000, .refdiv = 12, .fbdiv = 550, .postdiv1 = 1, .postdiv2 = 1, .dsmpd = 1, }, { .freq = 1008000000, .refdiv = 1, .fbdiv = 84, .postdiv1 = 2, .postdiv2 = 1, .dsmpd = 1, }, { .freq = 1000000000, .refdiv = 1, .fbdiv = 125, .postdiv1 = 3, .postdiv2 = 1, .dsmpd = 1, }, { .freq = 984000000, .refdiv = 1, .fbdiv = 82, .postdiv1 = 2, .postdiv2 = 1, .dsmpd = 1, }, { .freq = 960000000, .refdiv = 1, .fbdiv = 80, .postdiv1 = 2, .postdiv2 = 1, .dsmpd = 1, }, { .freq = 936000000, .refdiv = 1, .fbdiv = 78, .postdiv1 = 2, .postdiv2 = 1, .dsmpd = 1, }, { .freq = 912000000, .refdiv = 1, .fbdiv = 76, .postdiv1 = 2, .postdiv2 = 1, .dsmpd = 1, }, { .freq = 900000000, .refdiv = 4, .fbdiv = 300, .postdiv1 = 2, .postdiv2 = 1, .dsmpd = 1, }, { .freq = 888000000, .refdiv = 1, .fbdiv = 74, .postdiv1 = 2, .postdiv2 = 1, .dsmpd = 1, }, { .freq = 864000000, .refdiv = 1, .fbdiv = 72, .postdiv1 = 2, .postdiv2 = 1, .dsmpd = 1, }, { .freq = 840000000, .refdiv = 1, .fbdiv = 70, .postdiv1 = 2, .postdiv2 = 1, .dsmpd = 1, }, { .freq = 816000000, .refdiv = 1, .fbdiv = 68, .postdiv1 = 2, .postdiv2 = 1, .dsmpd = 1, }, { .freq = 800000000, .refdiv = 1, .fbdiv = 100, .postdiv1 = 3, .postdiv2 = 1, .dsmpd = 1, }, { .freq = 700000000, .refdiv = 6, .fbdiv = 350, .postdiv1 = 2, .postdiv2 = 1, .dsmpd = 1, }, { .freq = 696000000, .refdiv = 1, .fbdiv = 58, .postdiv1 = 2, .postdiv2 = 1, .dsmpd = 1, }, { .freq = 676000000, .refdiv = 3, .fbdiv = 169, .postdiv1 = 2, .postdiv2 = 1, .dsmpd = 1, }, { .freq = 600000000, .refdiv = 1, .fbdiv = 75, .postdiv1 = 3, .postdiv2 = 1, .dsmpd = 1, }, { .freq = 594000000, .refdiv = 1, .fbdiv = 99, .postdiv1 = 4, .postdiv2 = 1, .dsmpd = 1, }, { .freq = 533250000, .refdiv = 8, .fbdiv = 711, .postdiv1 = 4, .postdiv2 = 1, .dsmpd = 1, }, { .freq = 504000000, .refdiv = 1, .fbdiv = 63, .postdiv1 = 3, .postdiv2 = 1, .dsmpd = 1, }, { .freq = 500000000, .refdiv = 6, .fbdiv = 250, .postdiv1 = 2, .postdiv2 = 1, .dsmpd = 1, }, { .freq = 408000000, .refdiv = 1, .fbdiv = 68, .postdiv1 = 2, .postdiv2 = 2, .dsmpd = 1, }, { .freq = 312000000, .refdiv = 1, .fbdiv = 52, .postdiv1 = 2, .postdiv2 = 2, .dsmpd = 1, }, { .freq = 297000000, .refdiv = 1, .fbdiv = 99, .postdiv1 = 4, .postdiv2 = 2, .dsmpd = 1, }, { .freq = 216000000, .refdiv = 1, .fbdiv = 72, .postdiv1 = 4, .postdiv2 = 2, .dsmpd = 1, }, { .freq = 148500000, .refdiv = 1, .fbdiv = 99, .postdiv1 = 4, .postdiv2 = 4, .dsmpd = 1, }, { .freq = 106500000, .refdiv = 1, .fbdiv = 71, .postdiv1 = 4, .postdiv2 = 4, .dsmpd = 1, }, { .freq = 96000000, .refdiv = 1, .fbdiv = 64, .postdiv1 = 4, .postdiv2 = 4, .dsmpd = 1, }, { .freq = 74250000, .refdiv = 2, .fbdiv = 99, .postdiv1 = 4, .postdiv2 = 4, .dsmpd = 1, }, { .freq = 65000000, .refdiv = 1, .fbdiv = 65, .postdiv1 = 6, .postdiv2 = 4, .dsmpd = 1, }, { .freq = 54000000, .refdiv = 1, .fbdiv = 54, .postdiv1 = 6, .postdiv2 = 4, .dsmpd = 1, }, { .freq = 27000000, .refdiv = 1, .fbdiv = 27, .postdiv1 = 6, .postdiv2 = 4, .dsmpd = 1, }, {}, }; static const char *pll_parents[] = {"xin24m"}; static struct rk_clk_pll_def lpll = { .clkdef = { .id = PLL_APLLL, .name = "lpll", .parent_names = pll_parents, .parent_cnt = nitems(pll_parents), }, .base_offset = 0x00, .gate_offset = 0x300, .gate_shift = 0, .flags = RK_CLK_PLL_HAVE_GATE, .rates = rk3399_pll_rates, .normal_mode = true, }; static struct rk_clk_pll_def bpll = { .clkdef = { .id = PLL_APLLB, .name = "bpll", .parent_names = pll_parents, .parent_cnt = nitems(pll_parents), }, .base_offset = 0x20, .gate_offset = 0x300, .gate_shift = 1, .flags = RK_CLK_PLL_HAVE_GATE, .rates = rk3399_pll_rates, .normal_mode = true, }; static struct rk_clk_pll_def dpll = { .clkdef = { .id = PLL_DPLL, .name = "dpll", .parent_names = pll_parents, .parent_cnt = nitems(pll_parents), }, .base_offset = 0x40, .gate_offset = 0x300, .gate_shift = 2, .flags = RK_CLK_PLL_HAVE_GATE, .rates = rk3399_pll_rates, }; static struct rk_clk_pll_def cpll = { .clkdef = { .id = PLL_CPLL, .name = "cpll", .parent_names = pll_parents, .parent_cnt = nitems(pll_parents), }, .base_offset = 0x60, .rates = rk3399_pll_rates, }; static struct rk_clk_pll_def gpll = { .clkdef = { .id = PLL_GPLL, .name = "gpll", .parent_names = pll_parents, .parent_cnt = nitems(pll_parents), }, .base_offset = 0x80, .gate_offset = 0x300, .gate_shift = 3, .flags = RK_CLK_PLL_HAVE_GATE, .rates = rk3399_pll_rates, }; static struct rk_clk_pll_def npll = { .clkdef = { .id = PLL_NPLL, .name = "npll", .parent_names = pll_parents, .parent_cnt = nitems(pll_parents), }, .base_offset = 0xa0, .rates = rk3399_pll_rates, }; static struct rk_clk_pll_def vpll = { .clkdef = { .id = PLL_VPLL, .name = "vpll", .parent_names = pll_parents, .parent_cnt = nitems(pll_parents), }, .base_offset = 0xc0, .rates = rk3399_pll_rates, }; #define ACLK_PERIHP 192 #define HCLK_PERIHP 448 #define PCLK_PERIHP 320 static const char *aclk_perihp_parents[] = {"cpll_aclk_perihp_src", "gpll_aclk_perihp_src"}; static struct rk_clk_composite_def aclk_perihp = { .clkdef = { .id = ACLK_PERIHP, .name = "aclk_perihp", .parent_names = aclk_perihp_parents, .parent_cnt = nitems(aclk_perihp_parents), }, /* CRU_CLKSEL_CON14 */ .muxdiv_offset = 0x138, .mux_shift = 7, .mux_width = 1, .div_shift = 0, .div_width = 5, /* CRU_CLKGATE_CON5 */ .gate_offset = 0x314, .gate_shift = 2, .flags = RK_CLK_COMPOSITE_HAVE_MUX | RK_CLK_COMPOSITE_HAVE_GATE, }; static const char *hclk_pclk_perihp_parents[] = {"aclk_perihp"}; static struct rk_clk_composite_def hclk_perihp = { .clkdef = { .id = HCLK_PERIHP, .name = "hclk_perihp", .parent_names = hclk_pclk_perihp_parents, .parent_cnt = nitems(hclk_pclk_perihp_parents), }, /* CRU_CLKSEL_CON14 */ .muxdiv_offset = 0x138, .div_shift = 8, .div_width = 2, /* CRU_CLKGATE_CON5 */ .gate_offset = 0x314, .gate_shift = 3, .flags = RK_CLK_COMPOSITE_HAVE_MUX | RK_CLK_COMPOSITE_HAVE_GATE, }; static struct rk_clk_composite_def pclk_perihp = { .clkdef = { .id = PCLK_PERIHP, .name = "pclk_perihp", .parent_names = hclk_pclk_perihp_parents, .parent_cnt = nitems(hclk_pclk_perihp_parents), }, /* CRU_CLKSEL_CON14 */ .muxdiv_offset = 0x138, .div_shift = 12, .div_width = 3, /* CRU_CLKGATE_CON5 */ .gate_offset = 0x314, .gate_shift = 4, .flags = RK_CLK_COMPOSITE_HAVE_MUX | RK_CLK_COMPOSITE_HAVE_GATE, }; #define ACLK_PERILP0 194 #define HCLK_PERILP0 449 #define PCLK_PERILP0 322 static const char *aclk_perilp0_parents[] = {"cpll_aclk_perilp0_src", "gpll_aclk_perilp0_src"}; static struct rk_clk_composite_def aclk_perilp0 = { .clkdef = { .id = ACLK_PERILP0, .name = "aclk_perilp0", .parent_names = aclk_perilp0_parents, .parent_cnt = nitems(aclk_perilp0_parents), }, /* CRU_CLKSEL_CON14 */ .muxdiv_offset = 0x15C, .mux_shift = 7, .mux_width = 1, .div_shift = 0, .div_width = 5, /* CRU_CLKGATE_CON7 */ .gate_offset = 0x31C, .gate_shift = 2, .flags = RK_CLK_COMPOSITE_HAVE_MUX | RK_CLK_COMPOSITE_HAVE_GATE, }; static const char *hclk_pclk_perilp0_parents[] = {"aclk_perilp0"}; static struct rk_clk_composite_def hclk_perilp0 = { .clkdef = { .id = HCLK_PERILP0, .name = "hclk_perilp0", .parent_names = hclk_pclk_perilp0_parents, .parent_cnt = nitems(hclk_pclk_perilp0_parents), }, /* CRU_CLKSEL_CON23 */ .muxdiv_offset = 0x15C, .div_shift = 8, .div_width = 2, /* CRU_CLKGATE_CON7 */ .gate_offset = 0x31C, .gate_shift = 3, .flags = RK_CLK_COMPOSITE_HAVE_MUX | RK_CLK_COMPOSITE_HAVE_GATE, }; static struct rk_clk_composite_def pclk_perilp0 = { .clkdef = { .id = PCLK_PERILP0, .name = "pclk_perilp0", .parent_names = hclk_pclk_perilp0_parents, .parent_cnt = nitems(hclk_pclk_perilp0_parents), }, /* CRU_CLKSEL_CON23 */ .muxdiv_offset = 0x15C, .div_shift = 12, .div_width = 3, /* CRU_CLKGATE_CON7 */ .gate_offset = 0x31C, .gate_shift = 4, .flags = RK_CLK_COMPOSITE_HAVE_MUX | RK_CLK_COMPOSITE_HAVE_GATE, }; /* * misc */ #define PCLK_ALIVE 390 static const char *alive_parents[] = {"gpll"}; static struct rk_clk_composite_def pclk_alive = { .clkdef = { .id = PCLK_ALIVE, .name = "pclk_alive", .parent_names = alive_parents, .parent_cnt = nitems(alive_parents), }, /* CRU_CLKSEL_CON57 */ .muxdiv_offset = 0x01e4, .div_shift = 0, .div_width = 5, }; #define HCLK_PERILP1 450 #define PCLK_PERILP1 323 static const char *hclk_perilp1_parents[] = {"cpll", "gpll"}; static struct rk_clk_composite_def hclk_perilp1 = { .clkdef = { .id = HCLK_PERILP1, .name = "hclk_perilp1", .parent_names = hclk_perilp1_parents, .parent_cnt = nitems(hclk_perilp1_parents), }, /* CRU_CLKSEL_CON25 */ .muxdiv_offset = 0x164, .mux_shift = 7, .mux_width = 1, .div_shift = 0, .div_width = 5, .flags = RK_CLK_COMPOSITE_HAVE_MUX, }; static const char *pclk_perilp1_parents[] = {"hclk_perilp1"}; static struct rk_clk_composite_def pclk_perilp1 = { .clkdef = { .id = PCLK_PERILP1, .name = "pclk_perilp1", .parent_names = pclk_perilp1_parents, .parent_cnt = nitems(pclk_perilp1_parents), }, /* CRU_CLKSEL_CON25 */ .muxdiv_offset = 0x164, .div_shift = 8, .div_width = 3, /* CRU_CLKGATE_CON8 */ .gate_offset = 0x320, .gate_shift = 2, .flags = RK_CLK_COMPOSITE_HAVE_GATE, }; +/* USB3 clock */ + +#define ACLK_USB3 244 +static const char *aclk_usb3_parents[] = {"cpll", "gpll", "npll", "npll"}; +static struct rk_clk_composite_def aclk_usb3 = { + .clkdef = { + .id = ACLK_USB3, + .name = "aclk_usb3", + .parent_names = aclk_usb3_parents, + .parent_cnt = nitems(aclk_usb3_parents), + }, + /* CRU_CLKSET_CON39 */ + .muxdiv_offset = 0x19C, + .mux_shift = 6, + .mux_width = 2, + + .div_shift = 0, + .div_width = 5, + + /* CRU_CLKGATE_CON12 */ + .gate_offset = 0x330, + .gate_shift = 0, + + .flags = RK_CLK_COMPOSITE_HAVE_GATE, +}; + /* * i2c */ static const char *i2c_parents[] = {"cpll", "gpll"}; #define SCLK_I2C1 65 #define SCLK_I2C2 66 #define SCLK_I2C3 67 #define SCLK_I2C5 68 #define SCLK_I2C6 69 #define SCLK_I2C7 70 static struct rk_clk_composite_def i2c1 = { .clkdef = { .id = SCLK_I2C1, .name = "clk_i2c1", .parent_names = i2c_parents, .parent_cnt = nitems(i2c_parents), }, /* CRU_CLKSEL_CON61 */ .muxdiv_offset = 0x01f4, .mux_shift = 7, .mux_width = 1, .div_shift = 0, .div_width = 7, /* CRU_CLKGATE_CON10 */ .gate_offset = 0x0328, .gate_shift = 0, .flags = RK_CLK_COMPOSITE_HAVE_MUX | RK_CLK_COMPOSITE_HAVE_GATE, }; static struct rk_clk_composite_def i2c2 = { .clkdef = { .id = SCLK_I2C2, .name = "clk_i2c2", .parent_names = i2c_parents, .parent_cnt = nitems(i2c_parents), }, /* CRU_CLKSEL_CON62 */ .muxdiv_offset = 0x01f8, .mux_shift = 7, .mux_width = 1, .div_shift = 0, .div_width = 7, /* CRU_CLKGATE_CON10 */ .gate_offset = 0x0328, .gate_shift = 2, .flags = RK_CLK_COMPOSITE_HAVE_MUX | RK_CLK_COMPOSITE_HAVE_GATE, }; static struct rk_clk_composite_def i2c3 = { .clkdef = { .id = SCLK_I2C3, .name = "clk_i2c3", .parent_names = i2c_parents, .parent_cnt = nitems(i2c_parents), }, /* CRU_CLKSEL_CON63 */ .muxdiv_offset = 0x01fc, .mux_shift = 7, .mux_width = 1, .div_shift = 0, .div_width = 7, /* CRU_CLKGATE_CON10 */ .gate_offset = 0x0328, .gate_shift = 4, .flags = RK_CLK_COMPOSITE_HAVE_MUX | RK_CLK_COMPOSITE_HAVE_GATE, }; static struct rk_clk_composite_def i2c5 = { .clkdef = { .id = SCLK_I2C5, .name = "clk_i2c5", .parent_names = i2c_parents, .parent_cnt = nitems(i2c_parents), }, /* CRU_CLKSEL_CON61 */ .muxdiv_offset = 0x01f4, .mux_shift = 15, .mux_width = 1, .div_shift = 8, .div_width = 7, /* CRU_CLKGATE_CON10 */ .gate_offset = 0x0328, .gate_shift = 1, .flags = RK_CLK_COMPOSITE_HAVE_MUX | RK_CLK_COMPOSITE_HAVE_GATE, }; static struct rk_clk_composite_def i2c6 = { .clkdef = { .id = SCLK_I2C6, .name = "clk_i2c6", .parent_names = i2c_parents, .parent_cnt = nitems(i2c_parents), }, /* CRU_CLKSEL_CON62 */ .muxdiv_offset = 0x01f8, .mux_shift = 15, .mux_width = 1, .div_shift = 8, .div_width = 7, /* CRU_CLKGATE_CON10 */ .gate_offset = 0x0328, .gate_shift = 3, .flags = RK_CLK_COMPOSITE_HAVE_MUX | RK_CLK_COMPOSITE_HAVE_GATE, }; static struct rk_clk_composite_def i2c7 = { .clkdef = { .id = SCLK_I2C7, .name = "clk_i2c7", .parent_names = i2c_parents, .parent_cnt = nitems(i2c_parents), }, /* CRU_CLKSEL_CON63 */ .muxdiv_offset = 0x01fc, .mux_shift = 15, .mux_width = 1, .div_shift = 8, .div_width = 7, /* CRU_CLKGATE_CON10 */ .gate_offset = 0x0328, .gate_shift = 5, .flags = RK_CLK_COMPOSITE_HAVE_MUX | RK_CLK_COMPOSITE_HAVE_GATE, }; +/* USB3 */ + +#define SCLK_UPHY0_TCPDPHY_REF 125 +#define SCLK_UPHY0_TCPDCORE 126 + +/* Missing xin32k exported by rk808 */ +static const char *uphy0_tcpdphy_ref_parents[] = {"xin24m"}; + +static struct rk_clk_composite_def uphy0_tcpdphy_ref = { + .clkdef = { + .id = SCLK_UPHY0_TCPDPHY_REF, + .name = "uphy0_tcpdphy_ref", + .parent_names = uphy0_tcpdphy_ref_parents, + .parent_cnt = nitems(uphy0_tcpdphy_ref_parents), + }, + /* CRU_CLKSET_CON64 */ + .muxdiv_offset = 0x0200, + .mux_shift = 15, + .mux_width = 1, + + .div_shift = 8, + .div_width = 5, + + /* CRU_CLKGATE_CON13 */ + .gate_offset = 0x0334, + .gate_shift = 4, + + .flags = RK_CLK_COMPOSITE_HAVE_MUX | RK_CLK_COMPOSITE_HAVE_GATE, +}; + +/* Missing xin32k exported by rk808 */ +static const char *uphy0_tcpdcore_parents[] = {"xin24m", "xin24m", "cpll", "gpll"}; + +static struct rk_clk_composite_def uphy0_tcpdcore = { + .clkdef = { + .id = SCLK_UPHY0_TCPDCORE, + .name = "uphy0_tcpdcore", + .parent_names = uphy0_tcpdcore_parents, + .parent_cnt = nitems(uphy0_tcpdcore_parents), + }, + /* CRU_CLKSET_CON64 */ + .muxdiv_offset = 0x0200, + .mux_shift = 6, + .mux_width = 2, + + .div_shift = 0, + .div_width = 5, + + /* CRU_CLKGATE_CON13 */ + .gate_offset = 0x0334, + .gate_shift = 5, + + .flags = RK_CLK_COMPOSITE_HAVE_MUX | RK_CLK_COMPOSITE_HAVE_GATE, +}; + +#define SCLK_UPHY1_TCPDPHY_REF 127 +#define SCLK_UPHY1_TCPDCORE 128 + +/* Missing xin32k exported by rk808 */ +static const char *uphy1_tcpdphy_ref_parents[] = {"xin24m"}; + +static struct rk_clk_composite_def uphy1_tcpdphy_ref = { + .clkdef = { + .id = SCLK_UPHY1_TCPDPHY_REF, + .name = "uphy1_tcpdphy_ref", + .parent_names = uphy1_tcpdphy_ref_parents, + .parent_cnt = nitems(uphy1_tcpdphy_ref_parents), + }, + /* CRU_CLKSET_CON65 */ + .muxdiv_offset = 0x0204, + .mux_shift = 15, + .mux_width = 1, + + .div_shift = 8, + .div_width = 5, + + /* CRU_CLKGATE_CON13 */ + .gate_offset = 0x0334, + .gate_shift = 6, + + .flags = RK_CLK_COMPOSITE_HAVE_MUX | RK_CLK_COMPOSITE_HAVE_GATE, +}; + +/* Missing xin32k exported by rk808 */ +static const char *uphy1_tcpdcore_parents[] = {"xin24m", "xin24m", "cpll", "gpll"}; + +static struct rk_clk_composite_def uphy1_tcpdcore = { + .clkdef = { + .id = SCLK_UPHY1_TCPDCORE, + .name = "uphy1_tcpdcore", + .parent_names = uphy1_tcpdcore_parents, + .parent_cnt = nitems(uphy1_tcpdcore_parents), + }, + /* CRU_CLKSET_CON65 */ + .muxdiv_offset = 0x0204, + .mux_shift = 6, + .mux_width = 2, + + .div_shift = 0, + .div_width = 5, + + /* CRU_CLKGATE_CON13 */ + .gate_offset = 0x0334, + .gate_shift = 7, + + .flags = RK_CLK_COMPOSITE_HAVE_MUX | RK_CLK_COMPOSITE_HAVE_GATE, +}; + /* + * spi + */ +static const char *spi_parents[] = {"cpll", "gpll"}; + +#define SCLK_SPI0 71 +#define SCLK_SPI1 72 +#define SCLK_SPI2 73 +#define SCLK_SPI4 74 +#define SCLK_SPI5 75 + +static struct rk_clk_composite_def spi0 = { + .clkdef = { + .id = SCLK_SPI0, + .name = "clk_spi0", + .parent_names = spi_parents, + .parent_cnt = nitems(spi_parents), + }, + /* CRU_CLKSEL_CON59 */ + .muxdiv_offset = 0x01ec, + .mux_shift = 7, + .mux_width = 1, + + .div_shift = 0, + .div_width = 7, + + /* CRU_CLKGATE_CON9 */ + .gate_offset = 0x0324, + .gate_shift = 12, + + .flags = RK_CLK_COMPOSITE_HAVE_MUX | RK_CLK_COMPOSITE_HAVE_GATE, +}; + +static struct rk_clk_composite_def spi1 = { + .clkdef = { + .id = SCLK_SPI1, + .name = "clk_spi1", + .parent_names = spi_parents, + .parent_cnt = nitems(spi_parents), + }, + /* CRU_CLKSEL_CON59 */ + .muxdiv_offset = 0x01ec, + .mux_shift = 15, + .mux_width = 1, + + .div_shift = 8, + .div_width = 7, + + /* CRU_CLKGATE_CON9 */ + .gate_offset = 0x0324, + .gate_shift = 13, + + .flags = RK_CLK_COMPOSITE_HAVE_MUX | RK_CLK_COMPOSITE_HAVE_GATE, +}; + +static struct rk_clk_composite_def spi2 = { + .clkdef = { + .id = SCLK_SPI2, + .name = "clk_spi2", + .parent_names = spi_parents, + .parent_cnt = nitems(spi_parents), + }, + /* CRU_CLKSEL_CON60 */ + .muxdiv_offset = 0x01f0, + .mux_shift = 7, + .mux_width = 1, + + .div_shift = 0, + .div_width = 7, + + /* CRU_CLKGATE_CON9 */ + .gate_offset = 0x0324, + .gate_shift = 14, + + .flags = RK_CLK_COMPOSITE_HAVE_MUX | RK_CLK_COMPOSITE_HAVE_GATE, +}; + +static struct rk_clk_composite_def spi4 = { + .clkdef = { + .id = SCLK_SPI4, + .name = "clk_spi4", + .parent_names = spi_parents, + .parent_cnt = nitems(spi_parents), + }, + /* CRU_CLKSEL_CON60 */ + .muxdiv_offset = 0x01f0, + .mux_shift = 15, + .mux_width = 1, + + .div_shift = 8, + .div_width = 7, + + /* CRU_CLKGATE_CON9 */ + .gate_offset = 0x0324, + .gate_shift = 15, + + .flags = RK_CLK_COMPOSITE_HAVE_MUX | RK_CLK_COMPOSITE_HAVE_GATE, +}; + +static struct rk_clk_composite_def spi5 = { + .clkdef = { + .id = SCLK_SPI5, + .name = "clk_spi5", + .parent_names = spi_parents, + .parent_cnt = nitems(spi_parents), + }, + /* CRU_CLKSEL_CON58 */ + .muxdiv_offset = 0x01e8, + .mux_shift = 15, + .mux_width = 1, + + .div_shift = 8, + .div_width = 7, + + /* CRU_CLKGATE_CON13 */ + .gate_offset = 0x0334, + .gate_shift = 13, + + .flags = RK_CLK_COMPOSITE_HAVE_MUX | RK_CLK_COMPOSITE_HAVE_GATE, +}; + +/* * ARM CPU clocks (LITTLE and big) */ #define ARMCLKL 8 #define ARMCLKB 9 static const char *armclk_parents[] = {"lpll", "bpll", "dpll", "gpll"}; static struct rk_clk_armclk_rates rk3399_armclkl_rates[] = { { .freq = 1800000000, .div = 1, }, { .freq = 1704000000, .div = 1, }, { .freq = 1608000000, .div = 1, }, { .freq = 1512000000, .div = 1, }, { .freq = 1488000000, .div = 1, }, { .freq = 1416000000, .div = 1, }, { .freq = 1200000000, .div = 1, }, { .freq = 1008000000, .div = 1, }, { .freq = 816000000, .div = 1, }, { .freq = 696000000, .div = 1, }, { .freq = 600000000, .div = 1, }, { .freq = 408000000, .div = 1, }, { .freq = 312000000, .div = 1, }, { .freq = 216000000, .div = 1, }, { .freq = 96000000, .div = 1, }, }; static struct rk_clk_armclk_def armclk_l = { .clkdef = { .id = ARMCLKL, .name = "armclkl", .parent_names = armclk_parents, .parent_cnt = nitems(armclk_parents), }, /* CRU_CLKSEL_CON0 */ .muxdiv_offset = 0x100, .mux_shift = 6, .mux_width = 2, .div_shift = 0, .div_width = 5, .flags = RK_CLK_COMPOSITE_HAVE_MUX, .main_parent = 0, .alt_parent = 3, .rates = rk3399_armclkl_rates, .nrates = nitems(rk3399_armclkl_rates), }; static struct rk_clk_armclk_rates rk3399_armclkb_rates[] = { { .freq = 2208000000, .div = 1, }, { .freq = 2184000000, .div = 1, }, { .freq = 2088000000, .div = 1, }, { .freq = 2040000000, .div = 1, }, { .freq = 2016000000, .div = 1, }, { .freq = 1992000000, .div = 1, }, { .freq = 1896000000, .div = 1, }, { .freq = 1800000000, .div = 1, }, { .freq = 1704000000, .div = 1, }, { .freq = 1608000000, .div = 1, }, { .freq = 1512000000, .div = 1, }, { .freq = 1488000000, .div = 1, }, { .freq = 1416000000, .div = 1, }, { .freq = 1200000000, .div = 1, }, { .freq = 1008000000, .div = 1, }, { .freq = 816000000, .div = 1, }, { .freq = 696000000, .div = 1, }, { .freq = 600000000, .div = 1, }, { .freq = 408000000, .div = 1, }, { .freq = 312000000, .div = 1, }, { .freq = 216000000, .div = 1, }, { .freq = 96000000, .div = 1, }, }; static struct rk_clk_armclk_def armclk_b = { .clkdef = { .id = ARMCLKB, .name = "armclkb", .parent_names = armclk_parents, .parent_cnt = nitems(armclk_parents), }, .muxdiv_offset = 0x108, .mux_shift = 6, .mux_width = 2, .div_shift = 0, .div_width = 5, .flags = RK_CLK_COMPOSITE_HAVE_MUX, .main_parent = 1, .alt_parent = 3, .rates = rk3399_armclkb_rates, .nrates = nitems(rk3399_armclkb_rates), }; /* * sdmmc */ #define HCLK_SD 461 static const char *hclk_sd_parents[] = {"cpll", "gpll"}; static struct rk_clk_composite_def hclk_sd = { .clkdef = { .id = HCLK_SD, .name = "hclk_sd", .parent_names = hclk_sd_parents, .parent_cnt = nitems(hclk_sd_parents), }, .muxdiv_offset = 0x134, .mux_shift = 15, .mux_width = 1, .div_shift = 8, .div_width = 5, .gate_offset = 0x330, .gate_shift = 13, .flags = RK_CLK_COMPOSITE_HAVE_MUX | RK_CLK_COMPOSITE_HAVE_GATE, }; #define SCLK_SDMMC 76 static const char *sclk_sdmmc_parents[] = {"cpll", "gpll", "npll", "ppll"}; static struct rk_clk_composite_def sclk_sdmmc = { .clkdef = { .id = SCLK_SDMMC, .name = "sclk_sdmmc", .parent_names = sclk_sdmmc_parents, .parent_cnt = nitems(sclk_sdmmc_parents), }, .muxdiv_offset = 0x140, .mux_shift = 8, .mux_width = 3, .div_shift = 0, .div_width = 7, .gate_offset = 0x318, .gate_shift = 1, .flags = RK_CLK_COMPOSITE_HAVE_MUX | RK_CLK_COMPOSITE_HAVE_GATE, }; /* * emmc */ #define SCLK_EMMC 78 static const char *sclk_emmc_parents[] = {"cpll", "gpll", "npll"}; static struct rk_clk_composite_def sclk_emmc = { .clkdef = { .id = SCLK_EMMC, .name = "sclk_emmc", .parent_names = sclk_emmc_parents, .parent_cnt = nitems(sclk_emmc_parents), }, .muxdiv_offset = 0x158, .mux_shift = 8, .mux_width = 3, .div_shift = 0, .div_width = 7, .gate_offset = 0x318, .gate_shift = 14, .flags = RK_CLK_COMPOSITE_HAVE_MUX | RK_CLK_COMPOSITE_HAVE_GATE, }; #define ACLK_EMMC 240 static const char *aclk_emmc_parents[] = { "cpll_aclk_emmc_src", "gpll_aclk_emmc_src" }; static struct rk_clk_composite_def aclk_emmc = { .clkdef = { .id = ACLK_EMMC, .name = "aclk_emmc", .parent_names = aclk_emmc_parents, .parent_cnt = nitems(aclk_emmc_parents), }, .muxdiv_offset = 0x154, .mux_shift = 7, .mux_width = 1, .div_shift = 0, .div_width = 5, .flags = RK_CLK_COMPOSITE_HAVE_MUX, }; static struct rk_clk rk3399_clks[] = { { .type = RK3399_CLK_PLL, .clk.pll = &lpll }, { .type = RK3399_CLK_PLL, .clk.pll = &bpll }, { .type = RK3399_CLK_PLL, .clk.pll = &dpll }, { .type = RK3399_CLK_PLL, .clk.pll = &cpll }, { .type = RK3399_CLK_PLL, .clk.pll = &gpll }, { .type = RK3399_CLK_PLL, .clk.pll = &npll }, { .type = RK3399_CLK_PLL, .clk.pll = &vpll }, { .type = RK_CLK_COMPOSITE, .clk.composite = &aclk_perihp, }, { .type = RK_CLK_COMPOSITE, .clk.composite = &hclk_perihp, }, { .type = RK_CLK_COMPOSITE, .clk.composite = &pclk_perihp, }, { .type = RK_CLK_COMPOSITE, .clk.composite = &aclk_perilp0, }, { .type = RK_CLK_COMPOSITE, .clk.composite = &hclk_perilp0, }, { .type = RK_CLK_COMPOSITE, .clk.composite = &pclk_perilp0, }, { .type = RK_CLK_COMPOSITE, .clk.composite = &pclk_alive, }, { .type = RK_CLK_COMPOSITE, .clk.composite = &hclk_perilp1, }, { .type = RK_CLK_COMPOSITE, .clk.composite = &pclk_perilp1, }, { .type = RK_CLK_COMPOSITE, + .clk.composite = &aclk_usb3, + }, + { + .type = RK_CLK_COMPOSITE, .clk.composite = &i2c1, }, { .type = RK_CLK_COMPOSITE, .clk.composite = &i2c2, }, { .type = RK_CLK_COMPOSITE, .clk.composite = &i2c3, }, { .type = RK_CLK_COMPOSITE, .clk.composite = &i2c5, }, { .type = RK_CLK_COMPOSITE, .clk.composite = &i2c6, }, { .type = RK_CLK_COMPOSITE, .clk.composite = &i2c7, + }, + { + .type = RK_CLK_COMPOSITE, + .clk.composite = &uphy0_tcpdphy_ref, + }, + { + .type = RK_CLK_COMPOSITE, + .clk.composite = &uphy0_tcpdcore, + }, + { + .type = RK_CLK_COMPOSITE, + .clk.composite = &uphy1_tcpdphy_ref, + }, + { + .type = RK_CLK_COMPOSITE, + .clk.composite = &uphy1_tcpdcore, + }, + + { + .type = RK_CLK_COMPOSITE, + .clk.composite = &spi0, + }, + { + .type = RK_CLK_COMPOSITE, + .clk.composite = &spi1, + }, + { + .type = RK_CLK_COMPOSITE, + .clk.composite = &spi2, + }, + { + .type = RK_CLK_COMPOSITE, + .clk.composite = &spi4, + }, + { + .type = RK_CLK_COMPOSITE, + .clk.composite = &spi5, }, { .type = RK_CLK_ARMCLK, .clk.armclk = &armclk_l, }, { .type = RK_CLK_ARMCLK, .clk.armclk = &armclk_b, }, { .type = RK_CLK_COMPOSITE, .clk.composite = &hclk_sd, }, { .type = RK_CLK_COMPOSITE, .clk.composite = &sclk_sdmmc, }, { .type = RK_CLK_COMPOSITE, .clk.composite = &sclk_emmc, }, { .type = RK_CLK_COMPOSITE, .clk.composite = &aclk_emmc, }, }; static int rk3399_cru_probe(device_t dev) { if (!ofw_bus_status_okay(dev)) return (ENXIO); if (ofw_bus_is_compatible(dev, "rockchip,rk3399-cru")) { device_set_desc(dev, "Rockchip RK3399 Clock and Reset Unit"); return (BUS_PROBE_DEFAULT); } return (ENXIO); } static int rk3399_cru_attach(device_t dev) { struct rk_cru_softc *sc; sc = device_get_softc(dev); sc->dev = dev; sc->gates = rk3399_gates; sc->ngates = nitems(rk3399_gates); sc->clks = rk3399_clks; sc->nclks = nitems(rk3399_clks); sc->reset_offset = 0x400; sc->reset_num = 335; return (rk_cru_attach(dev)); } static device_method_t rk3399_cru_methods[] = { /* Device interface */ DEVMETHOD(device_probe, rk3399_cru_probe), DEVMETHOD(device_attach, rk3399_cru_attach), DEVMETHOD_END }; static devclass_t rk3399_cru_devclass; DEFINE_CLASS_1(rk3399_cru, rk3399_cru_driver, rk3399_cru_methods, sizeof(struct rk_cru_softc), rk_cru_driver); EARLY_DRIVER_MODULE(rk3399_cru, simplebus, rk3399_cru_driver, rk3399_cru_devclass, 0, 0, BUS_PASS_BUS + BUS_PASS_ORDER_MIDDLE); Index: stable/12/sys/arm64/rockchip/rk805.c =================================================================== --- stable/12/sys/arm64/rockchip/rk805.c (revision 358640) +++ stable/12/sys/arm64/rockchip/rk805.c (revision 358641) @@ -1,558 +1,561 @@ /*- * SPDX-License-Identifier: BSD-2-Clause-FreeBSD * * Copyright (c) 2018 Emmanuel Vadot * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. */ #include __FBSDID("$FreeBSD$"); #include #include #include #include #include #include #include #include #include #include #include #include #include #include "regdev_if.h" MALLOC_DEFINE(M_RK805_REG, "RK805 regulator", "RK805 power regulator"); /* #define dprintf(sc, format, arg...) device_printf(sc->base_dev, "%s: " format, __func__, arg) */ #define dprintf(sc, format, arg...) enum rk_pmic_type { RK805 = 1, RK808, }; static struct ofw_compat_data compat_data[] = { {"rockchip,rk805", RK805}, {"rockchip,rk808", RK808}, {NULL, 0} }; struct rk805_regdef { intptr_t id; char *name; uint8_t enable_reg; uint8_t enable_mask; uint8_t voltage_reg; uint8_t voltage_mask; int voltage_min; int voltage_max; int voltage_step; int voltage_nstep; }; struct rk805_reg_sc { struct regnode *regnode; device_t base_dev; struct rk805_regdef *def; phandle_t xref; struct regnode_std_param *param; }; struct rk805_softc { device_t dev; struct mtx mtx; struct resource * res[1]; void * intrcookie; struct intr_config_hook intr_hook; enum rk_pmic_type type; struct rk805_reg_sc **regs; int nregs; }; static struct rk805_regdef rk805_regdefs[] = { { .id = RK805_DCDC1, .name = "DCDC_REG1", .enable_reg = RK805_DCDC_EN, .enable_mask = 0x11, .voltage_reg = RK805_DCDC1_ON_VSEL, .voltage_mask = 0x3F, .voltage_min = 712500, .voltage_max = 1450000, .voltage_step = 12500, .voltage_nstep = 64, }, { .id = RK805_DCDC2, .name = "DCDC_REG2", .enable_reg = RK805_DCDC_EN, .enable_mask = 0x22, .voltage_reg = RK805_DCDC2_ON_VSEL, .voltage_mask = 0x3F, .voltage_min = 712500, .voltage_max = 1450000, .voltage_step = 12500, .voltage_nstep = 64, }, { .id = RK805_DCDC3, .name = "DCDC_REG3", .enable_reg = RK805_DCDC_EN, .enable_mask = 0x44, }, { .id = RK805_DCDC4, .name = "DCDC_REG4", .enable_reg = RK805_DCDC_EN, .enable_mask = 0x88, .voltage_reg = RK805_DCDC4_ON_VSEL, .voltage_mask = 0x3F, .voltage_min = 800000, .voltage_max = 3500000, .voltage_step = 100000, .voltage_nstep = 28, }, { .id = RK805_LDO1, .name = "LDO_REG1", .enable_reg = RK805_LDO_EN, .enable_mask = 0x11, .voltage_reg = RK805_LDO1_ON_VSEL, .voltage_mask = 0x1F, .voltage_min = 800000, .voltage_max = 3400000, .voltage_step = 100000, .voltage_nstep = 27, }, { .id = RK805_LDO2, .name = "LDO_REG2", .enable_reg = RK805_LDO_EN, .enable_mask = 0x22, .voltage_reg = RK805_LDO2_ON_VSEL, .voltage_mask = 0x1F, .voltage_min = 800000, .voltage_max = 3400000, .voltage_step = 100000, .voltage_nstep = 27, }, { .id = RK805_LDO3, .name = "LDO_REG3", .enable_reg = RK805_LDO_EN, .enable_mask = 0x44, .voltage_reg = RK805_LDO3_ON_VSEL, .voltage_mask = 0x1F, .voltage_min = 800000, .voltage_max = 3400000, .voltage_step = 100000, .voltage_nstep = 27, }, }; static struct rk805_regdef rk808_regdefs[] = { { .id = RK805_DCDC1, .name = "DCDC_REG1", .enable_reg = RK805_DCDC_EN, .enable_mask = 0x1, .voltage_reg = RK805_DCDC1_ON_VSEL, .voltage_mask = 0x3F, .voltage_min = 712500, .voltage_max = 1500000, .voltage_step = 12500, .voltage_nstep = 64, }, { .id = RK805_DCDC2, .name = "DCDC_REG2", .enable_reg = RK805_DCDC_EN, .enable_mask = 0x2, .voltage_reg = RK805_DCDC2_ON_VSEL, .voltage_mask = 0x3F, .voltage_min = 712500, .voltage_max = 1500000, .voltage_step = 12500, .voltage_nstep = 64, }, { .id = RK805_DCDC3, .name = "DCDC_REG3", .enable_reg = RK805_DCDC_EN, .enable_mask = 0x4, }, { .id = RK805_DCDC4, .name = "DCDC_REG4", .enable_reg = RK805_DCDC_EN, .enable_mask = 0x8, .voltage_reg = RK805_DCDC4_ON_VSEL, .voltage_mask = 0xF, .voltage_min = 1800000, .voltage_max = 3300000, .voltage_step = 100000, .voltage_nstep = 16, }, }; static int rk805_read(device_t dev, uint8_t reg, uint8_t *data, uint8_t size) { int err; err = iicdev_readfrom(dev, reg, data, size, IIC_INTRWAIT); return (err); } static int rk805_write(device_t dev, uint8_t reg, uint8_t data) { return (iicdev_writeto(dev, reg, &data, 1, IIC_INTRWAIT)); } static int rk805_regnode_init(struct regnode *regnode) { return (0); } static int rk805_regnode_enable(struct regnode *regnode, bool enable, int *udelay) { struct rk805_reg_sc *sc; uint8_t val; sc = regnode_get_softc(regnode); dprintf(sc, "%sabling regulator %s\n", enable ? "En" : "Dis", sc->def->name); rk805_read(sc->base_dev, sc->def->enable_reg, &val, 1); if (enable) val |= sc->def->enable_mask; else val &= ~sc->def->enable_mask; rk805_write(sc->base_dev, sc->def->enable_reg, val); *udelay = 0; return (0); } static void rk805_regnode_reg_to_voltage(struct rk805_reg_sc *sc, uint8_t val, int *uv) { if (val < sc->def->voltage_nstep) *uv = sc->def->voltage_min + val * sc->def->voltage_step; else *uv = sc->def->voltage_min + (sc->def->voltage_nstep * sc->def->voltage_step); } static int rk805_regnode_voltage_to_reg(struct rk805_reg_sc *sc, int min_uvolt, int max_uvolt, uint8_t *val) { uint8_t nval; int nstep, uvolt; nval = 0; uvolt = sc->def->voltage_min; for (nstep = 0; nstep < sc->def->voltage_nstep && uvolt < min_uvolt; nstep++) { ++nval; uvolt += sc->def->voltage_step; } if (uvolt > max_uvolt) return (EINVAL); *val = nval; return (0); } static int rk805_regnode_set_voltage(struct regnode *regnode, int min_uvolt, int max_uvolt, int *udelay) { struct rk805_reg_sc *sc; uint8_t val; int uvolt; sc = regnode_get_softc(regnode); if (!sc->def->voltage_step) return (ENXIO); dprintf(sc, "Setting %s to %d<->%d uvolts\n", sc->def->name, min_uvolt, max_uvolt); rk805_read(sc->base_dev, sc->def->voltage_reg, &val, 1); if (rk805_regnode_voltage_to_reg(sc, min_uvolt, max_uvolt, &val) != 0) return (ERANGE); rk805_write(sc->base_dev, sc->def->voltage_reg, val); rk805_read(sc->base_dev, sc->def->voltage_reg, &val, 1); *udelay = 0; rk805_regnode_reg_to_voltage(sc, val, &uvolt); dprintf(sc, "Regulator %s set to %d uvolt\n", sc->def->name, uvolt); return (0); } static int rk805_regnode_get_voltage(struct regnode *regnode, int *uvolt) { struct rk805_reg_sc *sc; uint8_t val; sc = regnode_get_softc(regnode); if (!sc->def->voltage_step) return (ENXIO); rk805_read(sc->base_dev, sc->def->voltage_reg, &val, 1); rk805_regnode_reg_to_voltage(sc, val & sc->def->voltage_mask, uvolt); dprintf(sc, "Regulator %s is at %d uvolt\n", sc->def->name, *uvolt); return (0); } static regnode_method_t rk805_regnode_methods[] = { /* Regulator interface */ REGNODEMETHOD(regnode_init, rk805_regnode_init), REGNODEMETHOD(regnode_enable, rk805_regnode_enable), REGNODEMETHOD(regnode_set_voltage, rk805_regnode_set_voltage), REGNODEMETHOD(regnode_get_voltage, rk805_regnode_get_voltage), REGNODEMETHOD(regnode_check_voltage, regnode_method_check_voltage), REGNODEMETHOD_END }; DEFINE_CLASS_1(rk805_regnode, rk805_regnode_class, rk805_regnode_methods, sizeof(struct rk805_reg_sc), regnode_class); static struct rk805_reg_sc * rk805_reg_attach(device_t dev, phandle_t node, struct rk805_regdef *def) { struct rk805_reg_sc *reg_sc; struct regnode_init_def initdef; struct regnode *regnode; memset(&initdef, 0, sizeof(initdef)); if (regulator_parse_ofw_stdparam(dev, node, &initdef) != 0) { device_printf(dev, "cannot create regulator\n"); return (NULL); } if (initdef.std_param.min_uvolt == 0) initdef.std_param.min_uvolt = def->voltage_min; if (initdef.std_param.max_uvolt == 0) initdef.std_param.max_uvolt = def->voltage_max; initdef.id = def->id; initdef.ofw_node = node; regnode = regnode_create(dev, &rk805_regnode_class, &initdef); if (regnode == NULL) { device_printf(dev, "cannot create regulator\n"); return (NULL); } reg_sc = regnode_get_softc(regnode); reg_sc->regnode = regnode; reg_sc->base_dev = dev; reg_sc->def = def; reg_sc->xref = OF_xref_from_node(node); reg_sc->param = regnode_get_stdparam(regnode); regnode_register(regnode); return (reg_sc); } static int rk805_probe(device_t dev) { if (!ofw_bus_status_okay(dev)) return (ENXIO); if (ofw_bus_search_compatible(dev, compat_data)->ocd_data == 0) return (ENXIO); device_set_desc(dev, "RockChip RK805 PMIC"); return (BUS_PROBE_DEFAULT); } static void rk805_start(void *pdev) { struct rk805_softc *sc; device_t dev; uint8_t data[2]; int err; dev = pdev; sc = device_get_softc(dev); sc->dev = dev; /* No version register in RK808 */ if (bootverbose && sc->type == RK805) { err = rk805_read(dev, RK805_CHIP_NAME, data, 1); if (err != 0) { device_printf(dev, "Cannot read chip name reg\n"); return; } err = rk805_read(dev, RK805_CHIP_VER, data + 1, 1); if (err != 0) { device_printf(dev, "Cannot read chip version reg\n"); return; } device_printf(dev, "Chip Name: %x\n", data[0] << 4 | ((data[1] >> 4) & 0xf)); device_printf(dev, "Chip Version: %x\n", data[1] & 0xf); } config_intrhook_disestablish(&sc->intr_hook); } static int rk805_attach(device_t dev) { struct rk805_softc *sc; struct rk805_reg_sc *reg; struct rk805_regdef *regdefs; phandle_t rnode, child; int i; sc = device_get_softc(dev); sc->intr_hook.ich_func = rk805_start; sc->intr_hook.ich_arg = dev; if (config_intrhook_establish(&sc->intr_hook) != 0) return (ENOMEM); - sc->regs = malloc(sizeof(struct rk805_reg_sc *) * sc->nregs, - M_RK805_REG, M_WAITOK | M_ZERO); - sc->type = ofw_bus_search_compatible(dev, compat_data)->ocd_data; switch (sc->type) { case RK805: regdefs = rk805_regdefs; sc->nregs = nitems(rk805_regdefs); break; case RK808: regdefs = rk808_regdefs; sc->nregs = nitems(rk808_regdefs); break; + default: + device_printf(dev, "Unknown type %d\n", sc->type); + return (ENXIO); } + + sc->regs = malloc(sizeof(struct rk805_reg_sc *) * sc->nregs, + M_RK805_REG, M_WAITOK | M_ZERO); rnode = ofw_bus_find_child(ofw_bus_get_node(dev), "regulators"); if (rnode > 0) { for (i = 0; i < sc->nregs; i++) { child = ofw_bus_find_child(rnode, regdefs[i].name); if (child == 0) continue; reg = rk805_reg_attach(dev, child, ®defs[i]); if (reg == NULL) { device_printf(dev, "cannot attach regulator %s\n", regdefs[i].name); continue; } sc->regs[i] = reg; if (bootverbose) device_printf(dev, "Regulator %s attached\n", regdefs[i].name); } } return (0); } static int rk805_detach(device_t dev) { /* We cannot detach regulators */ return (EBUSY); } static int rk805_map(device_t dev, phandle_t xref, int ncells, pcell_t *cells, intptr_t *id) { struct rk805_softc *sc; int i; sc = device_get_softc(dev); for (i = 0; i < sc->nregs; i++) { if (sc->regs[i]->xref == xref) { *id = sc->regs[i]->def->id; return (0); } } return (ERANGE); } static device_method_t rk805_methods[] = { DEVMETHOD(device_probe, rk805_probe), DEVMETHOD(device_attach, rk805_attach), DEVMETHOD(device_detach, rk805_detach), /* regdev interface */ DEVMETHOD(regdev_map, rk805_map), DEVMETHOD_END }; static driver_t rk805_driver = { "rk805_pmu", rk805_methods, sizeof(struct rk805_softc), }; static devclass_t rk805_devclass; EARLY_DRIVER_MODULE(rk805, iicbus, rk805_driver, rk805_devclass, 0, 0, BUS_PASS_INTERRUPT + BUS_PASS_ORDER_LAST); MODULE_DEPEND(rk805, iicbus, IICBUS_MINVER, IICBUS_PREFVER, IICBUS_MAXVER); MODULE_VERSION(rk805, 1); Index: stable/12/sys/arm64/rockchip/rk_spi.c =================================================================== --- stable/12/sys/arm64/rockchip/rk_spi.c (nonexistent) +++ stable/12/sys/arm64/rockchip/rk_spi.c (revision 358641) @@ -0,0 +1,483 @@ +/*- + * SPDX-License-Identifier: BSD-2-Clause-FreeBSD + * + * Copyright (c) 2019 Oleksandr Tymoshenko + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * $FreeBSD$ + */ + +#include +__FBSDID("$FreeBSD$"); + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include + +#include +#include + +#include +#include + +#include "spibus_if.h" + +#define RK_SPI_CTRLR0 0x0000 +#define CTRLR0_OPM_MASTER (0 << 20) +#define CTRLR0_XFM_TR (0 << 18) +#define CTRLR0_FRF_MOTO (0 << 16) +#define CTRLR0_BHT_8BIT (1 << 13) +#define CTRLR0_EM_BIG (1 << 11) +#define CTRLR0_SSD_ONE (1 << 10) +#define CTRLR0_SCPOL (1 << 7) +#define CTRLR0_SCPH (1 << 6) +#define CTRLR0_DFS_8BIT (1 << 0) +#define RK_SPI_CTRLR1 0x0004 +#define RK_SPI_ENR 0x0008 +#define RK_SPI_SER 0x000c +#define RK_SPI_BAUDR 0x0010 +#define RK_SPI_TXFTLR 0x0014 +#define RK_SPI_RXFTLR 0x0018 +#define RK_SPI_TXFLR 0x001c +#define RK_SPI_RXFLR 0x0020 +#define RK_SPI_SR 0x0024 +#define SR_BUSY (1 << 0) +#define RK_SPI_IPR 0x0028 +#define RK_SPI_IMR 0x002c +#define IMR_RFFIM (1 << 4) +#define IMR_TFEIM (1 << 0) +#define RK_SPI_ISR 0x0030 +#define ISR_RFFIS (1 << 4) +#define ISR_TFEIS (1 << 0) +#define RK_SPI_RISR 0x0034 +#define RK_SPI_ICR 0x0038 +#define RK_SPI_DMACR 0x003c +#define RK_SPI_DMATDLR 0x0040 +#define RK_SPI_DMARDLR 0x0044 +#define RK_SPI_TXDR 0x0400 +#define RK_SPI_RXDR 0x0800 + +#define CS_MAX 1 + +static struct ofw_compat_data compat_data[] = { + { "rockchip,rk3399-spi", 1 }, + { NULL, 0 } +}; + +static struct resource_spec rk_spi_spec[] = { + { SYS_RES_MEMORY, 0, RF_ACTIVE }, + { SYS_RES_IRQ, 0, RF_ACTIVE | RF_SHAREABLE }, + { -1, 0 } +}; + +struct rk_spi_softc { + device_t dev; + device_t spibus; + struct resource *res[2]; + struct mtx mtx; + clk_t clk_apb; + clk_t clk_spi; + void * intrhand; + int transfer; + uint32_t fifo_size; + uint64_t max_freq; + + uint32_t intreg; + uint8_t *rxbuf; + uint32_t rxidx; + uint8_t *txbuf; + uint32_t txidx; + uint32_t txlen; + uint32_t rxlen; +}; + +#define RK_SPI_LOCK(sc) mtx_lock(&(sc)->mtx) +#define RK_SPI_UNLOCK(sc) mtx_unlock(&(sc)->mtx) +#define RK_SPI_READ_4(sc, reg) bus_read_4((sc)->res[0], (reg)) +#define RK_SPI_WRITE_4(sc, reg, val) bus_write_4((sc)->res[0], (reg), (val)) + +static int rk_spi_probe(device_t dev); +static int rk_spi_attach(device_t dev); +static int rk_spi_detach(device_t dev); +static void rk_spi_intr(void *arg); + +static void +rk_spi_enable_chip(struct rk_spi_softc *sc, int enable) +{ + + RK_SPI_WRITE_4(sc, RK_SPI_ENR, enable ? 1 : 0); +} + +static int +rk_spi_set_cs(struct rk_spi_softc *sc, uint32_t cs, bool active) +{ + uint32_t reg; + + if (cs & SPIBUS_CS_HIGH) { + device_printf(sc->dev, "SPIBUS_CS_HIGH is not supported\n"); + return (EINVAL); + } + + if (cs > CS_MAX) + return (EINVAL); + + reg = RK_SPI_READ_4(sc, RK_SPI_SER); + if (active) + reg |= (1 << cs); + else + reg &= ~(1 << cs); + RK_SPI_WRITE_4(sc, RK_SPI_SER, reg); + + return (0); +} + +static void +rk_spi_hw_setup(struct rk_spi_softc *sc, uint32_t mode, uint32_t freq) +{ + uint32_t cr0; + uint32_t div; + + cr0 = CTRLR0_OPM_MASTER | CTRLR0_XFM_TR | CTRLR0_FRF_MOTO | + CTRLR0_BHT_8BIT | CTRLR0_EM_BIG | CTRLR0_SSD_ONE | + CTRLR0_DFS_8BIT; + + if (mode & SPIBUS_MODE_CPHA) + cr0 |= CTRLR0_SCPH; + if (mode & SPIBUS_MODE_CPOL) + cr0 |= CTRLR0_SCPOL; + + /* minimum divider is 2 */ + if (sc->max_freq < freq*2) { + clk_set_freq(sc->clk_spi, 2 * freq, CLK_SET_ROUND_DOWN); + clk_get_freq(sc->clk_spi, &sc->max_freq); + } + + div = ((sc->max_freq + freq - 1) / freq); + div = (div + 1) & 0xfffe; + RK_SPI_WRITE_4(sc, RK_SPI_BAUDR, div); + + RK_SPI_WRITE_4(sc, RK_SPI_CTRLR0, cr0); +} + +static uint32_t +rk_spi_fifo_size(struct rk_spi_softc *sc) +{ + uint32_t txftlr, reg; + + for (txftlr = 2; txftlr < 32; txftlr++) { + RK_SPI_WRITE_4(sc, RK_SPI_TXFTLR, txftlr); + reg = RK_SPI_READ_4(sc, RK_SPI_TXFTLR); + if (reg != txftlr) + break; + } + RK_SPI_WRITE_4(sc, RK_SPI_TXFTLR, 0); + + if (txftlr == 31) + return 0; + + return txftlr; +} + +static void +rk_spi_empty_rxfifo(struct rk_spi_softc *sc) +{ + uint32_t rxlevel; + rxlevel = RK_SPI_READ_4(sc, RK_SPI_RXFLR); + while (sc->rxidx < sc->rxlen && + (rxlevel-- > 0)) { + sc->rxbuf[sc->rxidx++] = (uint8_t)RK_SPI_READ_4(sc, RK_SPI_RXDR); + } +} + +static void +rk_spi_fill_txfifo(struct rk_spi_softc *sc) +{ + uint32_t txlevel; + txlevel = RK_SPI_READ_4(sc, RK_SPI_TXFLR); + int cnt = 0; + + while (sc->txidx < sc->txlen && txlevel < sc->fifo_size) { + RK_SPI_WRITE_4(sc, RK_SPI_TXDR, sc->txbuf[sc->txidx++]); + txlevel++; + cnt++; + } + + if (sc->txidx != sc->txlen) + sc->intreg |= (IMR_TFEIM | IMR_RFFIM); +} + +static int +rk_spi_xfer_buf(struct rk_spi_softc *sc, void *rxbuf, void *txbuf, uint32_t len) +{ + int err; + + if (len == 0) + return (0); + + sc->rxbuf = rxbuf; + sc->rxlen = len; + sc->rxidx = 0; + sc->txbuf = txbuf; + sc->txlen = len; + sc->txidx = 0; + sc->intreg = 0; + rk_spi_fill_txfifo(sc); + + RK_SPI_WRITE_4(sc, RK_SPI_IMR, sc->intreg); + + err = 0; + while (err == 0 && sc->intreg != 0) + err = msleep(sc, &sc->mtx, 0, "rk_spi", 10 * hz); + + while (err == 0 && sc->rxidx != sc->txidx) { + /* read residual data from RX fifo */ + rk_spi_empty_rxfifo(sc); + } + + if (sc->rxidx != sc->rxlen || sc->txidx != sc->txlen) + err = EIO; + + return (err); +} + +static int +rk_spi_probe(device_t dev) +{ + if (!ofw_bus_status_okay(dev)) + return (ENXIO); + + if (!ofw_bus_search_compatible(dev, compat_data)->ocd_data) + return (ENXIO); + + device_set_desc(dev, "Rockchip SPI"); + return (BUS_PROBE_DEFAULT); +} + +static int +rk_spi_attach(device_t dev) +{ + struct rk_spi_softc *sc; + int error; + + sc = device_get_softc(dev); + sc->dev = dev; + + mtx_init(&sc->mtx, device_get_nameunit(dev), NULL, MTX_DEF); + + if (bus_alloc_resources(dev, rk_spi_spec, sc->res) != 0) { + device_printf(dev, "cannot allocate resources for device\n"); + error = ENXIO; + goto fail; + } + + if (bus_setup_intr(dev, sc->res[1], + INTR_TYPE_MISC | INTR_MPSAFE, NULL, rk_spi_intr, sc, + &sc->intrhand)) { + bus_release_resources(dev, rk_spi_spec, sc->res); + device_printf(dev, "cannot setup interrupt handler\n"); + return (ENXIO); + } + + /* Activate the module clock. */ + error = clk_get_by_ofw_name(dev, 0, "apb_pclk", &sc->clk_apb); + if (error != 0) { + device_printf(dev, "cannot get apb_pclk clock\n"); + goto fail; + } + error = clk_get_by_ofw_name(dev, 0, "spiclk", &sc->clk_spi); + if (error != 0) { + device_printf(dev, "cannot get spiclk clock\n"); + goto fail; + } + error = clk_enable(sc->clk_apb); + if (error != 0) { + device_printf(dev, "cannot enable ahb clock\n"); + goto fail; + } + error = clk_enable(sc->clk_spi); + if (error != 0) { + device_printf(dev, "cannot enable spiclk clock\n"); + goto fail; + } + clk_get_freq(sc->clk_spi, &sc->max_freq); + + sc->fifo_size = rk_spi_fifo_size(sc); + if (sc->fifo_size == 0) { + device_printf(dev, "failed to get fifo size\n"); + goto fail; + } + + sc->spibus = device_add_child(dev, "spibus", -1); + + RK_SPI_WRITE_4(sc, RK_SPI_IMR, 0); + RK_SPI_WRITE_4(sc, RK_SPI_TXFTLR, sc->fifo_size/2 - 1); + RK_SPI_WRITE_4(sc, RK_SPI_RXFTLR, sc->fifo_size/2 - 1); + + return (bus_generic_attach(dev)); + +fail: + rk_spi_detach(dev); + return (error); +} + +static int +rk_spi_detach(device_t dev) +{ + struct rk_spi_softc *sc; + + sc = device_get_softc(dev); + + bus_generic_detach(sc->dev); + if (sc->spibus != NULL) + device_delete_child(dev, sc->spibus); + + if (sc->clk_spi != NULL) + clk_release(sc->clk_spi); + if (sc->clk_apb) + clk_release(sc->clk_apb); + + if (sc->intrhand != NULL) + bus_teardown_intr(sc->dev, sc->res[1], sc->intrhand); + + bus_release_resources(dev, rk_spi_spec, sc->res); + mtx_destroy(&sc->mtx); + + return (0); +} + +static void +rk_spi_intr(void *arg) +{ + struct rk_spi_softc *sc; + uint32_t intreg, isr; + + sc = arg; + + RK_SPI_LOCK(sc); + intreg = RK_SPI_READ_4(sc, RK_SPI_IMR); + isr = RK_SPI_READ_4(sc, RK_SPI_ISR); + RK_SPI_WRITE_4(sc, RK_SPI_ICR, isr); + + if (isr & ISR_RFFIS) + rk_spi_empty_rxfifo(sc); + + if (isr & ISR_TFEIS) + rk_spi_fill_txfifo(sc); + + /* no bytes left, disable interrupt */ + if (sc->txidx == sc->txlen) { + sc->intreg = 0; + wakeup(sc); + } + + if (sc->intreg != intreg) { + (void)RK_SPI_WRITE_4(sc, RK_SPI_IMR, sc->intreg); + (void)RK_SPI_READ_4(sc, RK_SPI_IMR); + } + + RK_SPI_UNLOCK(sc); +} + +static phandle_t +rk_spi_get_node(device_t bus, device_t dev) +{ + + return ofw_bus_get_node(bus); +} + +static int +rk_spi_transfer(device_t dev, device_t child, struct spi_command *cmd) +{ + struct rk_spi_softc *sc; + uint32_t cs, mode, clock; + int err = 0; + + sc = device_get_softc(dev); + + spibus_get_cs(child, &cs); + spibus_get_clock(child, &clock); + spibus_get_mode(child, &mode); + + RK_SPI_LOCK(sc); + rk_spi_hw_setup(sc, mode, clock); + rk_spi_enable_chip(sc, 1); + err = rk_spi_set_cs(sc, cs, true); + if (err != 0) { + rk_spi_enable_chip(sc, 0); + RK_SPI_UNLOCK(sc); + return (err); + } + + /* Transfer command then data bytes. */ + err = 0; + if (cmd->tx_cmd_sz > 0) + err = rk_spi_xfer_buf(sc, cmd->rx_cmd, cmd->tx_cmd, + cmd->tx_cmd_sz); + if (cmd->tx_data_sz > 0 && err == 0) + err = rk_spi_xfer_buf(sc, cmd->rx_data, cmd->tx_data, + cmd->tx_data_sz); + + rk_spi_set_cs(sc, cs, false); + rk_spi_enable_chip(sc, 0); + RK_SPI_UNLOCK(sc); + + return (err); +} + +static device_method_t rk_spi_methods[] = { + /* Device interface */ + DEVMETHOD(device_probe, rk_spi_probe), + DEVMETHOD(device_attach, rk_spi_attach), + DEVMETHOD(device_detach, rk_spi_detach), + + /* spibus_if */ + DEVMETHOD(spibus_transfer, rk_spi_transfer), + + /* ofw_bus_if */ + DEVMETHOD(ofw_bus_get_node, rk_spi_get_node), + + DEVMETHOD_END +}; + +static driver_t rk_spi_driver = { + "spi", + rk_spi_methods, + sizeof(struct rk_spi_softc), +}; + +static devclass_t rk_spi_devclass; + +DRIVER_MODULE(rk_spi, simplebus, rk_spi_driver, rk_spi_devclass, 0, 0); +DRIVER_MODULE(ofw_spibus, rk_spi, ofw_spibus_driver, ofw_spibus_devclass, 0, 0); +MODULE_DEPEND(rk_spi, ofw_spibus, 1, 1, 1); +SIMPLEBUS_PNP_INFO(compat_data); Property changes on: stable/12/sys/arm64/rockchip/rk_spi.c ___________________________________________________________________ Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:keywords ## -0,0 +1 ## +FreeBSD=%H \ No newline at end of property Added: svn:mime-type ## -0,0 +1 ## +text/plain \ No newline at end of property Index: stable/12/sys/arm64/rockchip/rk_typec_phy.c =================================================================== --- stable/12/sys/arm64/rockchip/rk_typec_phy.c (nonexistent) +++ stable/12/sys/arm64/rockchip/rk_typec_phy.c (revision 358641) @@ -0,0 +1,474 @@ +/*- + * SPDX-License-Identifier: BSD-2-Clause-FreeBSD + * + * Copyright (c) 2019 Emmanuel Vadot + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + +/* + * Rockchip PHY TYPEC + */ + +#include +__FBSDID("$FreeBSD$"); + +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include + +#include +#include +#include +#include + +#include "syscon_if.h" + +#define GRF_USB3OTG_BASE(x) (0x2430 + (0x10 * x)) +#define GRF_USB3OTG_CON0(x) (GRF_USB3OTG_BASE(x) + 0x0) +#define GRF_USB3OTG_CON1(x) (GRF_USB3OTG_BASE(x) + 0x4) +#define USB3OTG_CON1_U3_DIS (1 << 0) + +#define GRF_USB3PHY_BASE(x) (0x0e580 + (0xc * (x))) +#define GRF_USB3PHY_CON0(x) (GRF_USB3PHY_BASE(x) + 0x0) +#define USB3PHY_CON0_USB2_ONLY (1 << 3) +#define GRF_USB3PHY_CON1(x) (GRF_USB3PHY_BASE(x) + 0x4) +#define GRF_USB3PHY_CON2(x) (GRF_USB3PHY_BASE(x) + 0x8) +#define GRF_USB3PHY_STATUS0 0x0e5c0 +#define GRF_USB3PHY_STATUS1 0x0e5c4 + +#define CMN_PLL0_VCOCAL_INIT (0x84 << 2) +#define CMN_PLL0_VCOCAL_ITER (0x85 << 2) +#define CMN_PLL0_INTDIV (0x94 << 2) +#define CMN_PLL0_FRACDIV (0x95 << 2) +#define CMN_PLL0_HIGH_THR (0x96 << 2) +#define CMN_PLL0_DSM_DIAG (0x97 << 2) +#define CMN_PLL0_SS_CTRL1 (0x98 << 2) +#define CMN_PLL0_SS_CTRL2 (0x99 << 2) +#define CMN_DIAG_PLL0_FBH_OVRD (0x1c0 << 2) +#define CMN_DIAG_PLL0_FBL_OVRD (0x1c1 << 2) +#define CMN_DIAG_PLL0_OVRD (0x1c2 << 2) +#define CMN_DIAG_PLL0_V2I_TUNE (0x1c5 << 2) +#define CMN_DIAG_PLL0_CP_TUNE (0x1c6 << 2) +#define CMN_DIAG_PLL0_LF_PROG (0x1c7 << 2) +#define CMN_DIAG_HSCLK_SEL (0x1e0 << 2) +#define CMN_DIAG_HSCLK_SEL_PLL_CONFIG 0x30 +#define CMN_DIAG_HSCLK_SEL_PLL_MASK 0x33 + +#define TX_TXCC_MGNFS_MULT_000(lane) ((0x4050 | ((lane) << 9)) << 2) +#define XCVR_DIAG_BIDI_CTRL(lane) ((0x40e8 | ((lane) << 9)) << 2) +#define XCVR_DIAG_LANE_FCM_EN_MGN(lane) ((0x40f2 | ((lane) << 9)) << 2) +#define TX_PSC_A0(lane) ((0x4100 | ((lane) << 9)) << 2) +#define TX_PSC_A1(lane) ((0x4101 | ((lane) << 9)) << 2) +#define TX_PSC_A2(lane) ((0x4102 | ((lane) << 9)) << 2) +#define TX_PSC_A3(lane) ((0x4103 | ((lane) << 9)) << 2) +#define TX_RCVDET_EN_TMR(lane) ((0x4122 | ((lane) << 9)) << 2) +#define TX_RCVDET_ST_TMR(lane) ((0x4123 | ((lane) << 9)) << 2) + +#define RX_PSC_A0(lane) ((0x8000 | ((lane) << 9)) << 2) +#define RX_PSC_A1(lane) ((0x8001 | ((lane) << 9)) << 2) +#define RX_PSC_A2(lane) ((0x8002 | ((lane) << 9)) << 2) +#define RX_PSC_A3(lane) ((0x8003 | ((lane) << 9)) << 2) +#define RX_PSC_CAL(lane) ((0x8006 | ((lane) << 9)) << 2) +#define RX_PSC_RDY(lane) ((0x8007 | ((lane) << 9)) << 2) +#define RX_SIGDET_HL_FILT_TMR(lane) ((0x8090 | ((lane) << 9)) << 2) +#define RX_REE_CTRL_DATA_MASK(lane) ((0x81bb | ((lane) << 9)) << 2) +#define RX_DIAG_SIGDET_TUNE(lane) ((0x81dc | ((lane) << 9)) << 2) + +#define PMA_LANE_CFG (0xc000 << 2) +#define PIN_ASSIGN_D_F 0x5100 +#define DP_MODE_CTL (0xc008 << 2) +#define DP_MODE_ENTER_A2 0xc104 +#define PMA_CMN_CTRL1 (0xc800 << 2) +#define PMA_CMN_CTRL1_READY (1 << 0) + +static struct ofw_compat_data compat_data[] = { + { "rockchip,rk3399-typec-phy", 1 }, + { NULL, 0 } +}; + +static struct resource_spec rk_typec_phy_spec[] = { + { SYS_RES_MEMORY, 0, RF_ACTIVE }, + { -1, 0 } +}; + +struct rk_typec_phy_softc { + device_t dev; + struct resource *res; + struct syscon *grf; + clk_t tcpdcore; + clk_t tcpdphy_ref; + hwreset_t rst_uphy; + hwreset_t rst_pipe; + hwreset_t rst_tcphy; + int mode; + int phy_ctrl_id; +}; + +#define RK_TYPEC_PHY_READ(sc, reg) bus_read_4(sc->res, (reg)) +#define RK_TYPEC_PHY_WRITE(sc, reg, val) bus_write_4(sc->res, (reg), (val)) + +/* Phy class and methods. */ +static int rk_typec_phy_enable(struct phynode *phynode, bool enable); +static int rk_typec_phy_get_mode(struct phynode *phy, int *mode); +static int rk_typec_phy_set_mode(struct phynode *phy, int mode); +static phynode_method_t rk_typec_phy_phynode_methods[] = { + PHYNODEMETHOD(phynode_enable, rk_typec_phy_enable), + PHYNODEMETHOD(phynode_usb_get_mode, rk_typec_phy_get_mode), + PHYNODEMETHOD(phynode_usb_set_mode, rk_typec_phy_set_mode), + + PHYNODEMETHOD_END +}; + +DEFINE_CLASS_1(rk_typec_phy_phynode, rk_typec_phy_phynode_class, + rk_typec_phy_phynode_methods, + sizeof(struct phynode_usb_sc), phynode_usb_class); + +enum RK3399_USBPHY { + RK3399_TYPEC_PHY_DP = 0, + RK3399_TYPEC_PHY_USB3, +}; + +static void +rk_typec_phy_set_usb2_only(struct rk_typec_phy_softc *sc, bool usb2only) +{ + uint32_t reg; + + /* Disable usb3tousb2 only */ + reg = SYSCON_READ_4(sc->grf, GRF_USB3PHY_CON0(sc->phy_ctrl_id)); + if (usb2only) + reg |= USB3PHY_CON0_USB2_ONLY; + else + reg &= ~USB3PHY_CON0_USB2_ONLY; + /* Write Mask */ + reg |= (USB3PHY_CON0_USB2_ONLY) << 16; + SYSCON_WRITE_4(sc->grf, GRF_USB3PHY_CON0(sc->phy_ctrl_id), reg); + + /* Enable the USB3 Super Speed port */ + reg = SYSCON_READ_4(sc->grf, GRF_USB3OTG_CON1(sc->phy_ctrl_id)); + if (usb2only) + reg |= USB3OTG_CON1_U3_DIS; + else + reg &= ~USB3OTG_CON1_U3_DIS; + /* Write Mask */ + reg |= (USB3OTG_CON1_U3_DIS) << 16; + SYSCON_WRITE_4(sc->grf, GRF_USB3OTG_CON1(sc->phy_ctrl_id), reg); +} + +static int +rk_typec_phy_enable(struct phynode *phynode, bool enable) +{ + struct rk_typec_phy_softc *sc; + device_t dev; + intptr_t phy; + uint32_t reg; + int err, retry; + + dev = phynode_get_device(phynode); + phy = phynode_get_id(phynode); + sc = device_get_softc(dev); + + if (phy != RK3399_TYPEC_PHY_USB3) + return (ERANGE); + + rk_typec_phy_set_usb2_only(sc, false); + + err = clk_enable(sc->tcpdcore); + if (err != 0) { + device_printf(dev, "Could not enable clock %s\n", + clk_get_name(sc->tcpdcore)); + return (ENXIO); + } + err = clk_enable(sc->tcpdphy_ref); + if (err != 0) { + device_printf(dev, "Could not enable clock %s\n", + clk_get_name(sc->tcpdphy_ref)); + clk_disable(sc->tcpdcore); + return (ENXIO); + } + + hwreset_deassert(sc->rst_tcphy); + + /* 24M configuration, magic values from rockchip */ + RK_TYPEC_PHY_WRITE(sc, PMA_CMN_CTRL1, 0x830); + for (int i = 0; i < 4; i++) { + RK_TYPEC_PHY_WRITE(sc, XCVR_DIAG_LANE_FCM_EN_MGN(i), 0x90); + RK_TYPEC_PHY_WRITE(sc, TX_RCVDET_EN_TMR(i), 0x960); + RK_TYPEC_PHY_WRITE(sc, TX_RCVDET_ST_TMR(i), 0x30); + } + reg = RK_TYPEC_PHY_READ(sc, CMN_DIAG_HSCLK_SEL); + reg &= ~CMN_DIAG_HSCLK_SEL_PLL_MASK; + reg |= CMN_DIAG_HSCLK_SEL_PLL_CONFIG; + RK_TYPEC_PHY_WRITE(sc, CMN_DIAG_HSCLK_SEL, reg); + + /* PLL configuration, magic values from rockchip */ + RK_TYPEC_PHY_WRITE(sc, CMN_PLL0_VCOCAL_INIT, 0xf0); + RK_TYPEC_PHY_WRITE(sc, CMN_PLL0_VCOCAL_ITER, 0x18); + RK_TYPEC_PHY_WRITE(sc, CMN_PLL0_INTDIV, 0xd0); + RK_TYPEC_PHY_WRITE(sc, CMN_PLL0_FRACDIV, 0x4a4a); + RK_TYPEC_PHY_WRITE(sc, CMN_PLL0_HIGH_THR, 0x34); + RK_TYPEC_PHY_WRITE(sc, CMN_PLL0_SS_CTRL1, 0x1ee); + RK_TYPEC_PHY_WRITE(sc, CMN_PLL0_SS_CTRL2, 0x7f03); + RK_TYPEC_PHY_WRITE(sc, CMN_PLL0_DSM_DIAG, 0x20); + RK_TYPEC_PHY_WRITE(sc, CMN_DIAG_PLL0_OVRD, 0); + RK_TYPEC_PHY_WRITE(sc, CMN_DIAG_PLL0_FBH_OVRD, 0); + RK_TYPEC_PHY_WRITE(sc, CMN_DIAG_PLL0_FBL_OVRD, 0); + RK_TYPEC_PHY_WRITE(sc, CMN_DIAG_PLL0_V2I_TUNE, 0x7); + RK_TYPEC_PHY_WRITE(sc, CMN_DIAG_PLL0_CP_TUNE, 0x45); + RK_TYPEC_PHY_WRITE(sc, CMN_DIAG_PLL0_LF_PROG, 0x8); + + /* Configure the TX and RX line, magic values from rockchip */ + RK_TYPEC_PHY_WRITE(sc, TX_PSC_A0(0), 0x7799); + RK_TYPEC_PHY_WRITE(sc, TX_PSC_A1(0), 0x7798); + RK_TYPEC_PHY_WRITE(sc, TX_PSC_A2(0), 0x5098); + RK_TYPEC_PHY_WRITE(sc, TX_PSC_A3(0), 0x5098); + RK_TYPEC_PHY_WRITE(sc, TX_TXCC_MGNFS_MULT_000(0), 0x0); + RK_TYPEC_PHY_WRITE(sc, XCVR_DIAG_BIDI_CTRL(0), 0xbf); + + RK_TYPEC_PHY_WRITE(sc, RX_PSC_A0(1), 0xa6fd); + RK_TYPEC_PHY_WRITE(sc, RX_PSC_A1(1), 0xa6fd); + RK_TYPEC_PHY_WRITE(sc, RX_PSC_A2(1), 0xa410); + RK_TYPEC_PHY_WRITE(sc, RX_PSC_A3(1), 0x2410); + RK_TYPEC_PHY_WRITE(sc, RX_PSC_CAL(1), 0x23ff); + RK_TYPEC_PHY_WRITE(sc, RX_SIGDET_HL_FILT_TMR(1), 0x13); + RK_TYPEC_PHY_WRITE(sc, RX_REE_CTRL_DATA_MASK(1), 0x03e7); + RK_TYPEC_PHY_WRITE(sc, RX_DIAG_SIGDET_TUNE(1), 0x1004); + RK_TYPEC_PHY_WRITE(sc, RX_PSC_RDY(1), 0x2010); + RK_TYPEC_PHY_WRITE(sc, XCVR_DIAG_BIDI_CTRL(1), 0xfb); + + RK_TYPEC_PHY_WRITE(sc, PMA_LANE_CFG, PIN_ASSIGN_D_F); + + RK_TYPEC_PHY_WRITE(sc, DP_MODE_CTL, DP_MODE_ENTER_A2); + + hwreset_deassert(sc->rst_uphy); + + for (retry = 10000; retry > 0; retry--) { + reg = RK_TYPEC_PHY_READ(sc, PMA_CMN_CTRL1); + if (reg & PMA_CMN_CTRL1_READY) + break; + DELAY(10); + } + if (retry == 0) { + device_printf(sc->dev, "Timeout waiting for PMA\n"); + return (ENXIO); + } + + hwreset_deassert(sc->rst_pipe); + + return (0); +} + +static int +rk_typec_phy_get_mode(struct phynode *phynode, int *mode) +{ + struct rk_typec_phy_softc *sc; + intptr_t phy; + device_t dev; + + dev = phynode_get_device(phynode); + phy = phynode_get_id(phynode); + sc = device_get_softc(dev); + + if (phy != RK3399_TYPEC_PHY_USB3) + return (ERANGE); + + *mode = sc->mode; + + return (0); +} + +static int +rk_typec_phy_set_mode(struct phynode *phynode, int mode) +{ + struct rk_typec_phy_softc *sc; + intptr_t phy; + device_t dev; + + dev = phynode_get_device(phynode); + phy = phynode_get_id(phynode); + sc = device_get_softc(dev); + + if (phy != RK3399_TYPEC_PHY_USB3) + return (ERANGE); + + sc->mode = mode; + + return (0); +} + +static int +rk_typec_phy_probe(device_t dev) +{ + + if (!ofw_bus_status_okay(dev)) + return (ENXIO); + + if (ofw_bus_search_compatible(dev, compat_data)->ocd_data == 0) + return (ENXIO); + + device_set_desc(dev, "Rockchip RK3399 PHY TYPEC"); + return (BUS_PROBE_DEFAULT); +} + +static int +rk_typec_phy_attach(device_t dev) +{ + struct rk_typec_phy_softc *sc; + struct phynode_init_def phy_init; + struct phynode *phynode; + phandle_t node, usb3; + phandle_t reg_prop[4]; + + sc = device_get_softc(dev); + sc->dev = dev; + node = ofw_bus_get_node(dev); + + /* + * Find out which phy we are. + * There is not property for this so we need to know the + * address to use the correct GRF registers. + */ + if (OF_getencprop(node, "reg", reg_prop, sizeof(reg_prop)) <= 0) { + device_printf(dev, "Cannot guess phy controller id\n"); + return (ENXIO); + } + switch (reg_prop[1]) { + case 0xff7c0000: + sc->phy_ctrl_id = 0; + break; + case 0xff800000: + sc->phy_ctrl_id = 1; + break; + default: + device_printf(dev, "Unknown address %x for typec-phy\n", reg_prop[1]); + return (ENXIO); + } + + if (bus_alloc_resources(dev, rk_typec_phy_spec, &sc->res) != 0) { + device_printf(dev, "cannot allocate resources for device\n"); + goto fail; + } + + if (syscon_get_by_ofw_property(dev, node, + "rockchip,grf", &sc->grf) != 0) { + device_printf(dev, "Cannot get syscon handle\n"); + goto fail; + } + + if (clk_get_by_ofw_name(dev, 0, "tcpdcore", &sc->tcpdcore) != 0) { + device_printf(dev, "Cannot get tcpdcore clock\n"); + goto fail; + } + if (clk_get_by_ofw_name(dev, 0, "tcpdphy-ref", &sc->tcpdphy_ref) != 0) { + device_printf(dev, "Cannot get tcpdphy-ref clock\n"); + goto fail; + } + + if (hwreset_get_by_ofw_name(dev, 0, "uphy", &sc->rst_uphy) != 0) { + device_printf(dev, "Cannot get uphy reset\n"); + goto fail; + } + if (hwreset_get_by_ofw_name(dev, 0, "uphy-pipe", &sc->rst_pipe) != 0) { + device_printf(dev, "Cannot get uphy-pipe reset\n"); + goto fail; + } + if (hwreset_get_by_ofw_name(dev, 0, "uphy-tcphy", &sc->rst_tcphy) != 0) { + device_printf(dev, "Cannot get uphy-tcphy reset\n"); + goto fail; + } + + /* + * Make sure that the module is asserted + * We need to deassert in a certain order when we enable the phy + */ + hwreset_assert(sc->rst_uphy); + hwreset_assert(sc->rst_pipe); + hwreset_assert(sc->rst_tcphy); + + /* Set the assigned clocks parent and freq */ + if (clk_set_assigned(dev, node) != 0) { + device_printf(dev, "clk_set_assigned failed\n"); + goto fail; + } + + /* Only usb3 port is supported right now */ + usb3 = ofw_bus_find_child(node, "usb3-port"); + if (usb3 == 0) { + device_printf(dev, "Cannot find usb3-port child node\n"); + goto fail; + } + /* If the child isn't enable attach the driver + * but do not register the PHY. + */ + if (!ofw_bus_node_status_okay(usb3)) + return (0); + + phy_init.id = RK3399_TYPEC_PHY_USB3; + phy_init.ofw_node = usb3; + phynode = phynode_create(dev, &rk_typec_phy_phynode_class, &phy_init); + if (phynode == NULL) { + device_printf(dev, "failed to create phy usb3-port\n"); + goto fail; + } + if (phynode_register(phynode) == NULL) { + device_printf(dev, "failed to register phy usb3-port\n"); + goto fail; + } + + OF_device_register_xref(OF_xref_from_node(usb3), dev); + + return (0); + +fail: + bus_release_resources(dev, rk_typec_phy_spec, &sc->res); + + return (ENXIO); +} + +static device_method_t rk_typec_phy_methods[] = { + /* Device interface */ + DEVMETHOD(device_probe, rk_typec_phy_probe), + DEVMETHOD(device_attach, rk_typec_phy_attach), + + DEVMETHOD_END +}; + +static driver_t rk_typec_phy_driver = { + "rk_typec_phy", + rk_typec_phy_methods, + sizeof(struct rk_typec_phy_softc) +}; + +static devclass_t rk_typec_phy_devclass; +EARLY_DRIVER_MODULE(rk_typec_phy, simplebus, rk_typec_phy_driver, + rk_typec_phy_devclass, 0, 0, BUS_PASS_SUPPORTDEV + BUS_PASS_ORDER_MIDDLE); +MODULE_VERSION(rk_typec_phy, 1); Property changes on: stable/12/sys/arm64/rockchip/rk_typec_phy.c ___________________________________________________________________ Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:keywords ## -0,0 +1 ## +FreeBSD=%H \ No newline at end of property Added: svn:mime-type ## -0,0 +1 ## +text/plain \ No newline at end of property Index: stable/12/sys/conf/files.arm64 =================================================================== --- stable/12/sys/conf/files.arm64 (revision 358640) +++ stable/12/sys/conf/files.arm64 (revision 358641) @@ -1,301 +1,303 @@ # $FreeBSD$ cloudabi32_vdso.o optional compat_cloudabi32 \ dependency "$S/contrib/cloudabi/cloudabi_vdso_armv6_on_64bit.S" \ compile-with "${CC} -x assembler-with-cpp -m32 -shared -nostdinc -nostdlib -Wl,-T$S/compat/cloudabi/cloudabi_vdso.lds $S/contrib/cloudabi/cloudabi_vdso_armv6_on_64bit.S -o ${.TARGET}" \ no-obj no-implicit-rule \ clean "cloudabi32_vdso.o" # cloudabi32_vdso_blob.o optional compat_cloudabi32 \ dependency "cloudabi32_vdso.o" \ compile-with "${OBJCOPY} --input-target binary --output-target elf64-littleaarch64 --binary-architecture aarch64 cloudabi32_vdso.o ${.TARGET}" \ no-implicit-rule \ clean "cloudabi32_vdso_blob.o" # cloudabi64_vdso.o optional compat_cloudabi64 \ dependency "$S/contrib/cloudabi/cloudabi_vdso_aarch64.S" \ compile-with "${CC} -x assembler-with-cpp -shared -nostdinc -nostdlib -Wl,-T$S/compat/cloudabi/cloudabi_vdso.lds $S/contrib/cloudabi/cloudabi_vdso_aarch64.S -o ${.TARGET}" \ no-obj no-implicit-rule \ clean "cloudabi64_vdso.o" # cloudabi64_vdso_blob.o optional compat_cloudabi64 \ dependency "cloudabi64_vdso.o" \ compile-with "${OBJCOPY} --input-target binary --output-target elf64-littleaarch64 --binary-architecture aarch64 cloudabi64_vdso.o ${.TARGET}" \ no-implicit-rule \ clean "cloudabi64_vdso_blob.o" # # Allwinner common files arm/allwinner/a10_timer.c optional a10_timer fdt arm/allwinner/a10_codec.c optional sound a10_codec arm/allwinner/a31_dmac.c optional a31_dmac arm/allwinner/sunxi_dma_if.m optional a31_dmac arm/allwinner/aw_cir.c optional evdev aw_cir fdt arm/allwinner/aw_gpio.c optional gpio aw_gpio fdt arm/allwinner/aw_mmc.c optional mmc aw_mmc fdt | mmccam aw_mmc fdt arm/allwinner/aw_nmi.c optional aw_nmi fdt \ compile-with "${NORMAL_C} -I$S/gnu/dts/include" arm/allwinner/aw_pwm.c optional aw_pwm fdt arm/allwinner/aw_rsb.c optional aw_rsb fdt arm/allwinner/aw_rtc.c optional aw_rtc fdt arm/allwinner/aw_sid.c optional aw_sid nvmem fdt arm/allwinner/aw_spi.c optional aw_spi fdt arm/allwinner/aw_syscon.c optional aw_syscon ext_resources syscon fdt arm/allwinner/aw_thermal.c optional aw_thermal nvmem fdt arm/allwinner/aw_usbphy.c optional ehci aw_usbphy fdt arm/allwinner/aw_wdog.c optional aw_wdog fdt arm/allwinner/axp81x.c optional axp81x fdt arm/allwinner/if_awg.c optional awg ext_resources syscon aw_sid nvmem fdt # Allwinner clock driver arm/allwinner/clkng/aw_ccung.c optional aw_ccu fdt arm/allwinner/clkng/aw_clk_frac.c optional aw_ccu fdt arm/allwinner/clkng/aw_clk_m.c optional aw_ccu fdt arm/allwinner/clkng/aw_clk_mipi.c optional aw_ccu fdt arm/allwinner/clkng/aw_clk_nkmp.c optional aw_ccu fdt arm/allwinner/clkng/aw_clk_nm.c optional aw_ccu fdt arm/allwinner/clkng/aw_clk_nmm.c optional aw_ccu fdt arm/allwinner/clkng/aw_clk_np.c optional aw_ccu fdt arm/allwinner/clkng/aw_clk_prediv_mux.c optional aw_ccu fdt arm/allwinner/clkng/ccu_a64.c optional soc_allwinner_a64 aw_ccu fdt arm/allwinner/clkng/ccu_h3.c optional soc_allwinner_h5 aw_ccu fdt arm/allwinner/clkng/ccu_sun8i_r.c optional aw_ccu fdt arm/allwinner/clkng/ccu_de2.c optional aw_ccu fdt # Allwinner padconf files arm/allwinner/a64/a64_padconf.c optional soc_allwinner_a64 fdt arm/allwinner/a64/a64_r_padconf.c optional soc_allwinner_a64 fdt arm/allwinner/h3/h3_padconf.c optional soc_allwinner_h5 fdt arm/allwinner/h3/h3_r_padconf.c optional soc_allwinner_h5 fdt arm/annapurna/alpine/alpine_ccu.c optional al_ccu fdt arm/annapurna/alpine/alpine_nb_service.c optional al_nb_service fdt arm/annapurna/alpine/alpine_pci.c optional al_pci fdt arm/annapurna/alpine/alpine_pci_msix.c optional al_pci fdt arm/annapurna/alpine/alpine_serdes.c optional al_serdes fdt \ no-depend \ compile-with "${CC} -c -o ${.TARGET} ${CFLAGS} -I$S/contrib/alpine-hal -I$S/contrib/alpine-hal/eth ${PROF} ${.IMPSRC}" arm/arm/generic_timer.c standard arm/arm/gic.c standard arm/arm/gic_acpi.c optional acpi arm/arm/gic_fdt.c optional fdt arm/arm/pmu.c standard arm/arm/physmem.c standard arm/broadcom/bcm2835/bcm2835_audio.c optional sound vchiq fdt \ compile-with "${NORMAL_C} -DUSE_VCHIQ_ARM -D__VCCOREVER__=0x04000000 -I$S/contrib/vchiq" arm/broadcom/bcm2835/bcm2835_bsc.c optional bcm2835_bsc fdt arm/broadcom/bcm2835/bcm2835_clkman.c optional soc_brcm_bcm2837 fdt | soc_brcm_bcm2838 fdt arm/broadcom/bcm2835/bcm2835_cpufreq.c optional soc_brcm_bcm2837 fdt | soc_brcm_bcm2838 fdt arm/broadcom/bcm2835/bcm2835_dma.c optional soc_brcm_bcm2837 fdt | soc_brcm_bcm2838 fdt arm/broadcom/bcm2835/bcm2835_fbd.c optional vt soc_brcm_bcm2837 fdt | vt soc_brcm_bcm2838 fdt arm/broadcom/bcm2835/bcm2835_ft5406.c optional evdev bcm2835_ft5406 fdt arm/broadcom/bcm2835/bcm2835_gpio.c optional gpio soc_brcm_bcm2837 fdt | gpio soc_brcm_bcm2838 fdt arm/broadcom/bcm2835/bcm2835_intr.c optional soc_brcm_bcm2837 fdt | soc_brcm_bcm2838 fdt arm/broadcom/bcm2835/bcm2835_mbox.c optional soc_brcm_bcm2837 fdt | soc_brcm_bcm2838 fdt arm/broadcom/bcm2835/bcm2835_rng.c optional random soc_brcm_bcm2837 fdt | random soc_brcm_bcm2838 fdt arm/broadcom/bcm2835/bcm2835_sdhci.c optional sdhci soc_brcm_bcm2837 fdt | sdhci soc_brcm_bcm2838 fdt arm/broadcom/bcm2835/bcm2835_sdhost.c optional sdhci soc_brcm_bcm2837 fdt | sdhci soc_brcm_bcm2838 fdt arm/broadcom/bcm2835/bcm2835_spi.c optional bcm2835_spi fdt arm/broadcom/bcm2835/bcm2835_vcbus.c optional soc_brcm_bcm2837 fdt | soc_brcm_bcm2838 fdt arm/broadcom/bcm2835/bcm2835_vcio.c optional soc_brcm_bcm2837 fdt | soc_brcm_bcm2838 fdt arm/broadcom/bcm2835/bcm2835_wdog.c optional soc_brcm_bcm2837 fdt | soc_brcm_bcm2838 fdt arm/broadcom/bcm2835/bcm2836.c optional soc_brcm_bcm2837 fdt | soc_brcm_bcm2838 fdt arm/broadcom/bcm2835/bcm283x_dwc_fdt.c optional dwcotg fdt soc_brcm_bcm2837 | dwcotg fdt soc_brcm_bcm2838 arm/mv/a37x0_gpio.c optional a37x0_gpio gpio fdt arm/mv/gpio.c optional mv_gpio fdt arm/mv/mvebu_pinctrl.c optional mvebu_pinctrl fdt arm/mv/mv_cp110_icu.c optional mv_cp110_icu fdt arm/mv/mv_ap806_gicp.c optional mv_ap806_gicp fdt arm/mv/mv_ap806_clock.c optional SOC_MARVELL_8K fdt arm/mv/mv_cp110_clock.c optional SOC_MARVELL_8K fdt arm/mv/mv_thermal.c optional SOC_MARVELL_8K mv_thermal fdt arm/mv/armada38x/armada38x_rtc.c optional mv_rtc fdt arm/xilinx/uart_dev_cdnc.c optional uart soc_xilinx_zynq arm64/acpica/acpi_iort.c optional acpi arm64/acpica/acpi_machdep.c optional acpi arm64/acpica/OsdEnvironment.c optional acpi arm64/acpica/acpi_wakeup.c optional acpi arm64/acpica/pci_cfgreg.c optional acpi pci arm64/arm64/autoconf.c standard arm64/arm64/bus_machdep.c standard arm64/arm64/bus_space_asm.S standard arm64/arm64/busdma_bounce.c standard arm64/arm64/busdma_machdep.c standard arm64/arm64/bzero.S standard arm64/arm64/clock.c standard arm64/arm64/copyinout.S standard arm64/arm64/copystr.c standard arm64/arm64/cpu_errata.c standard arm64/arm64/cpufunc_asm.S standard arm64/arm64/db_disasm.c optional ddb arm64/arm64/db_interface.c optional ddb arm64/arm64/db_trace.c optional ddb arm64/arm64/debug_monitor.c optional ddb arm64/arm64/disassem.c optional ddb arm64/arm64/dump_machdep.c standard arm64/arm64/efirt_machdep.c optional efirt arm64/arm64/elf32_machdep.c optional compat_freebsd32 arm64/arm64/elf_machdep.c standard arm64/arm64/exception.S standard arm64/arm64/freebsd32_machdep.c optional compat_freebsd32 arm64/arm64/gicv3_its.c optional intrng fdt arm64/arm64/gic_v3.c standard arm64/arm64/gic_v3_acpi.c optional acpi arm64/arm64/gic_v3_fdt.c optional fdt arm64/arm64/identcpu.c standard arm64/arm64/in_cksum.c optional inet | inet6 arm64/arm64/locore.S standard no-obj arm64/arm64/machdep.c standard arm64/arm64/mem.c standard arm64/arm64/memcpy.S standard arm64/arm64/memmove.S standard arm64/arm64/minidump_machdep.c standard arm64/arm64/mp_machdep.c optional smp arm64/arm64/nexus.c standard arm64/arm64/ofw_machdep.c optional fdt arm64/arm64/pmap.c standard arm64/arm64/stack_machdep.c optional ddb | stack arm64/arm64/support.S standard arm64/arm64/swtch.S standard arm64/arm64/sys_machdep.c standard arm64/arm64/trap.c standard arm64/arm64/uio_machdep.c standard arm64/arm64/uma_machdep.c standard arm64/arm64/undefined.c standard arm64/arm64/unwind.c optional ddb | kdtrace_hooks | stack arm64/arm64/vfp.c standard arm64/arm64/vm_machdep.c standard arm64/cavium/thunder_pcie_fdt.c optional soc_cavm_thunderx pci fdt arm64/cavium/thunder_pcie_pem.c optional soc_cavm_thunderx pci arm64/cavium/thunder_pcie_pem_fdt.c optional soc_cavm_thunderx pci fdt arm64/cavium/thunder_pcie_common.c optional soc_cavm_thunderx pci arm64/cloudabi32/cloudabi32_sysvec.c optional compat_cloudabi32 arm64/cloudabi64/cloudabi64_sysvec.c optional compat_cloudabi64 arm64/coresight/coresight.c standard arm64/coresight/coresight_if.m standard arm64/coresight/coresight-cmd.c standard arm64/coresight/coresight-cpu-debug.c standard arm64/coresight/coresight-dynamic-replicator.c standard arm64/coresight/coresight-etm4x.c standard arm64/coresight/coresight-funnel.c standard arm64/coresight/coresight-tmc.c standard arm64/qualcomm/qcom_gcc.c optional qcom_gcc fdt contrib/vchiq/interface/compat/vchi_bsd.c optional vchiq soc_brcm_bcm2837 \ compile-with "${NORMAL_C} -DUSE_VCHIQ_ARM -D__VCCOREVER__=0x04000000 -I$S/contrib/vchiq" contrib/vchiq/interface/vchiq_arm/vchiq_2835_arm.c optional vchiq soc_brcm_bcm2837 \ compile-with "${NORMAL_C} -Wno-unused -DUSE_VCHIQ_ARM -D__VCCOREVER__=0x04000000 -I$S/contrib/vchiq" contrib/vchiq/interface/vchiq_arm/vchiq_arm.c optional vchiq soc_brcm_bcm2837 \ compile-with "${NORMAL_C} -Wno-unused -DUSE_VCHIQ_ARM -D__VCCOREVER__=0x04000000 -I$S/contrib/vchiq" contrib/vchiq/interface/vchiq_arm/vchiq_connected.c optional vchiq soc_brcm_bcm2837 \ compile-with "${NORMAL_C} -DUSE_VCHIQ_ARM -D__VCCOREVER__=0x04000000 -I$S/contrib/vchiq" contrib/vchiq/interface/vchiq_arm/vchiq_core.c optional vchiq soc_brcm_bcm2837 \ compile-with "${NORMAL_C} -DUSE_VCHIQ_ARM -D__VCCOREVER__=0x04000000 -I$S/contrib/vchiq" contrib/vchiq/interface/vchiq_arm/vchiq_kern_lib.c optional vchiq soc_brcm_bcm2837 \ compile-with "${NORMAL_C} -DUSE_VCHIQ_ARM -D__VCCOREVER__=0x04000000 -I$S/contrib/vchiq" contrib/vchiq/interface/vchiq_arm/vchiq_kmod.c optional vchiq soc_brcm_bcm2837 \ compile-with "${NORMAL_C} -DUSE_VCHIQ_ARM -D__VCCOREVER__=0x04000000 -I$S/contrib/vchiq" contrib/vchiq/interface/vchiq_arm/vchiq_shim.c optional vchiq soc_brcm_bcm2837 \ compile-with "${NORMAL_C} -DUSE_VCHIQ_ARM -D__VCCOREVER__=0x04000000 -I$S/contrib/vchiq" contrib/vchiq/interface/vchiq_arm/vchiq_util.c optional vchiq soc_brcm_bcm2837 \ compile-with "${NORMAL_C} -DUSE_VCHIQ_ARM -D__VCCOREVER__=0x04000000 -I$S/contrib/vchiq" crypto/armv8/armv8_crypto.c optional armv8crypto armv8_crypto_wrap.o optional armv8crypto \ dependency "$S/crypto/armv8/armv8_crypto_wrap.c" \ compile-with "${CC} -c ${CFLAGS:C/^-O2$/-O3/:N-nostdinc:N-mgeneral-regs-only} -I$S/crypto/armv8/ ${WERROR} ${NO_WCAST_QUAL} ${PROF} -march=armv8-a+crypto ${.IMPSRC}" \ no-implicit-rule \ clean "armv8_crypto_wrap.o" crypto/blowfish/bf_enc.c optional crypto | ipsec | ipsec_support crypto/des/des_enc.c optional crypto | ipsec | ipsec_support | netsmb dev/acpica/acpi_bus_if.m optional acpi dev/acpica/acpi_if.m optional acpi dev/acpica/acpi_pci_link.c optional acpi pci dev/acpica/acpi_pcib.c optional acpi pci dev/acpica/acpi_pxm.c optional acpi dev/ahci/ahci_generic.c optional ahci dev/axgbe/if_axgbe.c optional axgbe dev/axgbe/xgbe-desc.c optional axgbe dev/axgbe/xgbe-dev.c optional axgbe dev/axgbe/xgbe-drv.c optional axgbe dev/axgbe/xgbe-mdio.c optional axgbe dev/cpufreq/cpufreq_dt.c optional cpufreq fdt dev/iicbus/twsi/mv_twsi.c optional twsi fdt dev/iicbus/twsi/a10_twsi.c optional twsi fdt dev/iicbus/twsi/twsi.c optional twsi fdt dev/hwpmc/hwpmc_arm64.c optional hwpmc dev/hwpmc/hwpmc_arm64_md.c optional hwpmc dev/mbox/mbox_if.m optional soc_brcm_bcm2837 dev/mmc/host/dwmmc.c optional dwmmc fdt dev/mmc/host/dwmmc_hisi.c optional dwmmc fdt soc_hisi_hi6220 dev/mmc/host/dwmmc_rockchip.c optional dwmmc fdt soc_rockchip_rk3328 dev/neta/if_mvneta_fdt.c optional neta fdt dev/neta/if_mvneta.c optional neta mdio mii dev/ofw/ofw_cpu.c optional fdt dev/ofw/ofwpci.c optional fdt pci dev/pci/pci_host_generic.c optional pci dev/pci/pci_host_generic_acpi.c optional pci acpi dev/pci/pci_host_generic_fdt.c optional pci fdt dev/psci/psci.c standard dev/psci/psci_arm64.S standard dev/psci/smccc.c standard dev/sdhci/sdhci_xenon.c optional sdhci_xenon sdhci fdt dev/uart/uart_cpu_arm64.c optional uart dev/uart/uart_dev_mu.c optional uart uart_mu dev/uart/uart_dev_pl011.c optional uart pl011 dev/usb/controller/dwc_otg_hisi.c optional dwcotg fdt soc_hisi_hi6220 dev/usb/controller/ehci_mv.c optional ehci_mv fdt dev/usb/controller/generic_ehci.c optional ehci dev/usb/controller/generic_ehci_acpi.c optional ehci acpi dev/usb/controller/generic_ehci_fdt.c optional ehci fdt dev/usb/controller/generic_ohci.c optional ohci fdt dev/usb/controller/generic_usb_if.m optional ohci fdt dev/usb/controller/usb_nop_xceiv.c optional fdt ext_resources dev/usb/controller/generic_xhci.c optional xhci fdt dev/vnic/mrml_bridge.c optional vnic fdt dev/vnic/nic_main.c optional vnic pci dev/vnic/nicvf_main.c optional vnic pci pci_iov dev/vnic/nicvf_queues.c optional vnic pci pci_iov dev/vnic/thunder_bgx_fdt.c optional vnic fdt dev/vnic/thunder_bgx.c optional vnic pci dev/vnic/thunder_mdio_fdt.c optional vnic fdt dev/vnic/thunder_mdio.c optional vnic dev/vnic/lmac_if.m optional inet | inet6 | vnic kern/kern_clocksource.c standard kern/msi_if.m optional intrng kern/pic_if.m optional intrng kern/subr_devmap.c standard kern/subr_intr.c optional intrng libkern/bcmp.c standard libkern/ffs.c standard libkern/ffsl.c standard libkern/ffsll.c standard libkern/fls.c standard libkern/flsl.c standard libkern/flsll.c standard libkern/memcmp.c standard libkern/memset.c standard libkern/arm64/crc32c_armv8.S standard cddl/dev/dtrace/aarch64/dtrace_asm.S optional dtrace compile-with "${DTRACE_S}" cddl/dev/dtrace/aarch64/dtrace_subr.c optional dtrace compile-with "${DTRACE_C}" cddl/dev/fbt/aarch64/fbt_isa.c optional dtrace_fbt | dtraceall compile-with "${FBT_C}" # RockChip Drivers arm64/rockchip/rk3399_emmcphy.c optional fdt rk_emmcphy soc_rockchip_rk3399 arm64/rockchip/rk_i2c.c optional fdt rk_i2c soc_rockchip_rk3328 | fdt rk_i2c soc_rockchip_rk3399 arm64/rockchip/rk805.c optional fdt rk805 soc_rockchip_rk3328 | fdt rk805 soc_rockchip_rk3399 arm64/rockchip/rk_grf.c optional fdt soc_rockchip_rk3328 | fdt soc_rockchip_rk3399 arm64/rockchip/rk_pinctrl.c optional fdt rk_pinctrl soc_rockchip_rk3328 | fdt rk_pinctrl soc_rockchip_rk3399 arm64/rockchip/rk_gpio.c optional fdt rk_gpio soc_rockchip_rk3328 | fdt rk_gpio soc_rockchip_rk3399 +arm64/rockchip/rk_spi.c optional fdt rk_spi arm64/rockchip/rk_usb2phy.c optional fdt rk_usb2phy soc_rockchip_rk3328 | soc_rockchip_rk3399 +arm64/rockchip/rk_typec_phy.c optional fdt rk_typec_phy soc_rockchip_rk3399 arm64/rockchip/if_dwc_rk.c optional fdt dwc_rk soc_rockchip_rk3328 | fdt dwc_rk soc_rockchip_rk3399 dev/dwc/if_dwc.c optional fdt dwc_rk soc_rockchip_rk3328 | fdt dwc_rk soc_rockchip_rk3399 dev/dwc/if_dwc_if.m optional fdt dwc_rk soc_rockchip_rk3328 | fdt dwc_rk soc_rockchip_rk3399 # RockChip Clock support arm64/rockchip/clk/rk_cru.c optional fdt soc_rockchip_rk3328 | fdt soc_rockchip_rk3399 arm64/rockchip/clk/rk_clk_armclk.c optional fdt soc_rockchip_rk3328 | fdt soc_rockchip_rk3399 arm64/rockchip/clk/rk_clk_composite.c optional fdt soc_rockchip_rk3328 | fdt soc_rockchip_rk3399 arm64/rockchip/clk/rk_clk_gate.c optional fdt soc_rockchip_rk3328 | fdt soc_rockchip_rk3399 arm64/rockchip/clk/rk_clk_mux.c optional fdt soc_rockchip_rk3328 | fdt soc_rockchip_rk3399 arm64/rockchip/clk/rk_clk_pll.c optional fdt soc_rockchip_rk3328 | fdt soc_rockchip_rk3399 arm64/rockchip/clk/rk3328_cru.c optional fdt soc_rockchip_rk3328 arm64/rockchip/clk/rk3399_cru.c optional fdt soc_rockchip_rk3399 arm64/rockchip/clk/rk3399_pmucru.c optional fdt soc_rockchip_rk3399 Index: stable/12 =================================================================== --- stable/12 (revision 358640) +++ stable/12 (revision 358641) Property changes on: stable/12 ___________________________________________________________________ Modified: svn:mergeinfo ## -0,0 +0,1 ## Merged /head:r354087,354089,354094,354100,354103,354152