Index: stable/12/sys/arm64/conf/GENERIC
===================================================================
--- stable/12/sys/arm64/conf/GENERIC	(revision 358639)
+++ stable/12/sys/arm64/conf/GENERIC	(revision 358640)
@@ -1,303 +1,304 @@
 #
 # GENERIC -- Generic kernel configuration file for FreeBSD/arm64
 #
 # For more information on this file, please read the config(5) manual page,
 # and/or the handbook section on Kernel Configuration Files:
 #
 #    https://www.FreeBSD.org/doc/en_US.ISO8859-1/books/handbook/kernelconfig-config.html
 #
 # The handbook is also available locally in /usr/share/doc/handbook
 # if you've installed the doc distribution, otherwise always see the
 # FreeBSD World Wide Web server (https://www.FreeBSD.org/) for the
 # latest information.
 #
 # An exhaustive list of options and more detailed explanations of the
 # device lines is also present in the ../../conf/NOTES and NOTES files.
 # If you are in doubt as to the purpose or necessity of a line, check first
 # in NOTES.
 #
 # $FreeBSD$
 
 cpu		ARM64
 ident		GENERIC
 
 makeoptions	DEBUG=-g		# Build kernel with gdb(1) debug symbols
 makeoptions	WITH_CTF=1		# Run ctfconvert(1) for DTrace support
 
 options 	SCHED_ULE		# ULE scheduler
 options 	PREEMPTION		# Enable kernel thread preemption
 options 	VIMAGE			# Subsystem virtualization, e.g. VNET
 options 	INET			# InterNETworking
 options 	INET6			# IPv6 communications protocols
 options 	IPSEC			# IP (v4/v6) security
 options 	IPSEC_SUPPORT		# Allow kldload of ipsec and tcpmd5
 options 	TCP_HHOOK		# hhook(9) framework for TCP
 options 	TCP_OFFLOAD		# TCP offload
 options		TCP_RFC7413		# TCP Fast Open
 options 	SCTP			# Stream Control Transmission Protocol
 options 	FFS			# Berkeley Fast Filesystem
 options 	SOFTUPDATES		# Enable FFS soft updates support
 options 	UFS_ACL			# Support for access control lists
 options 	UFS_DIRHASH		# Improve performance on big directories
 options 	UFS_GJOURNAL		# Enable gjournal-based UFS journaling
 options 	QUOTA			# Enable disk quotas for UFS
 options 	MD_ROOT			# MD is a potential root device
 options 	NFSCL			# Network Filesystem Client
 options 	NFSD			# Network Filesystem Server
 options 	NFSLOCKD		# Network Lock Manager
 options 	NFS_ROOT		# NFS usable as /, requires NFSCL
 options 	MSDOSFS			# MSDOS Filesystem
 options 	CD9660			# ISO 9660 Filesystem
 options 	PROCFS			# Process filesystem (requires PSEUDOFS)
 options 	PSEUDOFS		# Pseudo-filesystem framework
 options 	GEOM_RAID		# Soft RAID functionality.
 options 	GEOM_LABEL		# Provides labelization
 options 	COMPAT_FREEBSD32	# Incomplete, but used by cloudabi32.ko.
 options 	COMPAT_FREEBSD11	# Compatible with FreeBSD11
 options 	SCSI_DELAY=5000		# Delay (in ms) before probing SCSI
 options 	KTRACE			# ktrace(1) support
 options 	STACK			# stack(9) support
 options 	SYSVSHM			# SYSV-style shared memory
 options 	SYSVMSG			# SYSV-style message queues
 options 	SYSVSEM			# SYSV-style semaphores
 options 	_KPOSIX_PRIORITY_SCHEDULING # POSIX P1003_1B real-time extensions
 options 	PRINTF_BUFR_SIZE=128	# Prevent printf output being interspersed.
 options 	KBD_INSTALL_CDEV	# install a CDEV entry in /dev
 options 	HWPMC_HOOKS		# Necessary kernel hooks for hwpmc(4)
 options 	AUDIT			# Security event auditing
 options 	CAPABILITY_MODE		# Capsicum capability mode
 options 	CAPABILITIES		# Capsicum capabilities
 options 	MAC			# TrustedBSD MAC Framework
 options 	KDTRACE_FRAME		# Ensure frames are compiled in
 options 	KDTRACE_HOOKS		# Kernel DTrace hooks
 options 	VFP			# Floating-point support
 options 	RACCT			# Resource accounting framework
 options 	RACCT_DEFAULT_TO_DISABLED # Set kern.racct.enable=0 by default
 options 	RCTL			# Resource limits
 options 	SMP
 options 	INTRNG
 
 # Debugging support.  Always need this:
 options 	KDB			# Enable kernel debugger support.
 options 	KDB_TRACE		# Print a stack trace for a panic.
 
 # Kernel dump features.
 options 	EKCD			# Support for encrypted kernel dumps
 options 	GZIO			# gzip-compressed kernel and user dumps
 options 	ZSTDIO			# zstd-compressed kernel and user dumps
 options 	NETDUMP			# netdump(4) client support
 
 # SoC support
 options 	SOC_ALLWINNER_A64
 options 	SOC_ALLWINNER_H5
 options 	SOC_CAVM_THUNDERX
 options 	SOC_HISI_HI6220
 options 	SOC_BRCM_BCM2837
 options 	SOC_BRCM_BCM2838
 options 	SOC_MARVELL_8K
 options 	SOC_ROCKCHIP_RK3328
 options 	SOC_ROCKCHIP_RK3399
 options 	SOC_XILINX_ZYNQ
 
 # Timer drivers
 device		a10_timer
 
 # Annapurna Alpine drivers
 device		al_ccu			# Alpine Cache Coherency Unit
 device		al_nb_service		# Alpine North Bridge Service
 device		al_iofic		# I/O Fabric Interrupt Controller
 device		al_serdes		# Serializer/Deserializer
 device		al_udma			# Universal DMA
 
 # Qualcomm Snapdragon drivers
 device		qcom_gcc		# Global Clock Controller
 
 # VirtIO support
 device		virtio
 device		virtio_pci
 device		virtio_mmio
 device		virtio_blk
 device		vtnet
 
 # CPU frequency control
 device		cpufreq
 
 # Bus drivers
 device		pci
 device		al_pci		# Annapurna Alpine PCI-E
 options 	PCI_HP			# PCI-Express native HotPlug
 options 	PCI_IOV		# PCI SR-IOV support
 
 # PCI/PCI-X/PCIe Ethernet NICs that use iflib infrastructure
 device		iflib
 device		em		# Intel PRO/1000 Gigabit Ethernet Family
 device		ix		# Intel 10Gb Ethernet Family
 
 # Ethernet NICs
 device		mdio
 device		mii
 device		miibus		# MII bus support
 device		awg		# Allwinner EMAC Gigabit Ethernet
 device		axgbe		# AMD Opteron A1100 integrated NIC
 device		msk		# Marvell/SysKonnect Yukon II Gigabit Ethernet
 device		neta		# Marvell Armada 370/38x/XP/3700 NIC
 device  	smc		# SMSC LAN91C111
 device		vnic		# Cavium ThunderX NIC
 device		al_eth		# Annapurna Alpine Ethernet NIC
 device		dwc_rk		# Rockchip Designware
 
 # Block devices
 device		ahci
 device		scbus
 device		da
 
 # ATA/SCSI peripherals
 device		pass		# Passthrough device (direct ATA/SCSI access)
 
 # NVM Express (NVMe) support
 device		nvme		# base NVMe driver
 options 	NVME_USE_NVD=0	# prefer the cam(4) based nda(4) driver
 device		nvd		# expose NVMe namespaces as disks, depends on nvme
 
 # MMC/SD/SDIO Card slot support
 device		sdhci
 device		sdhci_xenon		# Marvell Xenon SD/MMC controller
 device		aw_mmc			# Allwinner SD/MMC controller
 device		mmc			# mmc/sd bus
 device		mmcsd			# mmc/sd flash cards
 device		dwmmc
+device		rk_emmcphy
 
 # Serial (COM) ports
 device		uart		# Generic UART driver
 device		uart_msm	# Qualcomm MSM UART driver
 device		uart_mu		# RPI3 aux port
 device		uart_mvebu	# Armada 3700 UART driver
 device		uart_ns8250	# ns8250-type UART driver
 device		uart_snps
 device		pl011
 
 # USB support
 device		aw_usbphy		# Allwinner USB PHY
 device		rk_usb2phy		# Rockchip USB2PHY
 device		dwcotg			# DWC OTG controller
 device		ohci			# OHCI USB interface
 device		ehci			# EHCI USB interface (USB 2.0)
 device		ehci_mv			# Marvell EHCI USB interface
 device		xhci			# XHCI PCI->USB interface (USB 3.0)
 device		usb			# USB Bus (required)
 device		ukbd			# Keyboard
 device		umass			# Disks/Mass storage - Requires scbus and da
 
 # USB ethernet support
 device		muge
 device		smcphy
 device		smsc
 
 # Sound support
 device sound
 device a10_codec
 
 # DMA controller
 device		a31_dmac
 
 # GPIO / PINCTRL
 device		a37x0_gpio	# Marvell Armada 37x0 GPIO controller
 device		aw_gpio		# Allwinner GPIO controller
 device		gpio
 device		gpioled
 device		fdt_pinctrl
 device		gpioregulator
 device		mv_gpio		# Marvell GPIO controller
 device		mvebu_pinctrl	# Marvell Pinmux Controller
 device		rk_gpio		# RockChip GPIO Controller
 device		rk_pinctrl	# RockChip Pinmux Controller
 
 # I2C
 device		aw_rsb		# Allwinner Reduced Serial Bus
 device		bcm2835_bsc	# Broadcom BCM283x I2C bus
 device		iicbus
 device		iic
 device		twsi		# Allwinner I2C controller
 device		syr827		# Silergy SYR827 PMIC
 device		rk_i2c		# RockChip I2C controller
 
 # Clock and reset controllers
 device		aw_ccu		# Allwinner clock controller
 
 # Interrupt controllers
 device		aw_nmi		# Allwinner NMI support
 device		mv_cp110_icu	# Marvell CP110 ICU
 device		mv_ap806_gicp	# Marvell AP806 GICP
 
 # Real-time clock support
 device		aw_rtc		# Allwinner Real-time Clock
 device		mv_rtc		# Marvell Real-time Clock
 
 # Watchdog controllers
 device		aw_wdog		# Allwinner Watchdog
 
 # Power management controllers
 device		axp81x		# X-Powers AXP81x PMIC
 device		rk805		# RockChip RK805 PMIC
 
 # EFUSE
 device		aw_sid		# Allwinner Secure ID EFUSE
 
 # Thermal sensors
 device		aw_thermal	# Allwinner Thermal Sensor Controller
 device		mv_thermal	# Marvell Thermal Sensor Controller
 
 # SPI
 device		spibus
 device		bcm2835_spi	# Broadcom BCM283x SPI bus
 
 # PWM
 device		pwm
 device		aw_pwm
 
 # Console
 device		vt
 device		kbdmux
 
 device		vt_efifb
 
 # EVDEV support
 device		evdev			# input event device support
 options		EVDEV_SUPPORT		# evdev support in legacy drivers
 device		uinput			# install /dev/uinput cdev
 
 # Pseudo devices.
 device		crypto		# core crypto support
 device		loop		# Network loopback
 device		random		# Entropy device
 device		ether		# Ethernet support
 device		vlan		# 802.1Q VLAN support
 device		tuntap		# Packet tunnel.
 device		md		# Memory "disks"
 device		gif		# IPv6 and IPv4 tunneling
 device		firmware	# firmware assist module
 options 	EFIRT		# EFI Runtime Services
 
 # EXT_RESOURCES pseudo devices
 options 	EXT_RESOURCES
 device		clk
 device		phy
 device		hwreset
 device		nvmem
 device		regulator
 device		syscon
 device		aw_syscon
 
 # The `bpf' device enables the Berkeley Packet Filter.
 # Be aware of the administrative consequences of enabling this!
 # Note that 'bpf' is required for DHCP.
 device		bpf		# Berkeley packet filter
 
 # Chip-specific errata
 options 	THUNDERX_PASS_1_1_ERRATA
 
 options 	FDT
 device		acpi
 
 # DTBs
 makeoptions	MODULES_EXTRA="dtb/allwinner dtb/rockchip dtb/rpi"
Index: stable/12/sys/arm64/rockchip/rk3399_emmcphy.c
===================================================================
--- stable/12/sys/arm64/rockchip/rk3399_emmcphy.c	(nonexistent)
+++ stable/12/sys/arm64/rockchip/rk3399_emmcphy.c	(revision 358640)
@@ -0,0 +1,341 @@
+/*-
+ * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
+ *
+ * Copyright (c) 2019 Ganbold Tsagaankhuu <ganbold@FreeBSD.org>
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+/*
+ * Rockchip RK3399 eMMC PHY
+ */
+
+#include <sys/cdefs.h>
+__FBSDID("$FreeBSD$");
+
+#include <sys/param.h>
+#include <sys/systm.h>
+#include <sys/bus.h>
+#include <sys/rman.h>
+#include <sys/kernel.h>
+#include <sys/module.h>
+#include <sys/gpio.h>
+#include <machine/bus.h>
+
+#include <dev/fdt/fdt_common.h>
+#include <dev/ofw/ofw_bus.h>
+#include <dev/ofw/ofw_bus_subr.h>
+
+#include <dev/extres/clk/clk.h>
+#include <dev/extres/syscon/syscon.h>
+#include <dev/extres/phy/phy.h>
+
+#include "syscon_if.h"
+
+#define	GRF_EMMCPHY_BASE	0xf780
+#define	GRF_EMMCPHY_CON0	(GRF_EMMCPHY_BASE + 0x00)
+#define	 PHYCTRL_FRQSEL		(1 << 13) | (1 << 12)
+#define	  PHYCTRL_FRQSEL_200M	0
+#define	  PHYCTRL_FRQSEL_50M	1
+#define	  PHYCTRL_FRQSEL_100M	2
+#define	  PHYCTRL_FRQSEL_150M	3
+#define	 PHYCTRL_OTAPDLYENA	(1 << 11)
+#define	 PHYCTRL_OTAPDLYSEL	(1 << 10) | (1 << 9) | (1 << 8) | (1 << 7)
+#define	 PHYCTRL_ITAPCHGWIN	(1 << 6)
+#define	 PHYCTRL_ITAPDLYSEL	(1 << 5) | (1 << 4)  | (1 << 3) | (1 << 2) | \
+    (1 << 1)
+#define	 PHYCTRL_ITAPDLYENA	(1 << 0)
+#define	GRF_EMMCPHY_CON1	(GRF_EMMCPHY_BASE + 0x04)
+#define	 PHYCTRL_CLKBUFSEL	(1 << 8) | (1 << 7) | (1 << 6)
+#define	 PHYCTRL_SELDLYTXCLK	(1 << 5)
+#define	 PHYCTRL_SELDLYRXCLK	(1 << 4)
+#define	 PHYCTRL_STRBSEL	0xf
+#define	GRF_EMMCPHY_CON2	(GRF_EMMCPHY_BASE + 0x08)
+#define	 PHYCTRL_REN_STRB	(1 << 9)
+#define	 PHYCTRL_REN_CMD	(1 << 8)
+#define	 PHYCTRL_REN_DAT	0xff
+#define	GRF_EMMCPHY_CON3	(GRF_EMMCPHY_BASE + 0x0c)
+#define	 PHYCTRL_PU_STRB	(1 << 9)
+#define	 PHYCTRL_PU_CMD		(1 << 8)
+#define	 PHYCTRL_PU_DAT		0xff
+#define	GRF_EMMCPHY_CON4	(GRF_EMMCPHY_BASE + 0x10)
+#define	 PHYCTRL_OD_RELEASE_CMD		(1 << 9)
+#define	 PHYCTRL_OD_RELEASE_STRB	(1 << 8)
+#define	 PHYCTRL_OD_RELEASE_DAT		0xff
+#define	GRF_EMMCPHY_CON5	(GRF_EMMCPHY_BASE + 0x14)
+#define	 PHYCTRL_ODEN_STRB	(1 << 9)
+#define	 PHYCTRL_ODEN_CMD	(1 << 8)
+#define	 PHYCTRL_ODEN_DAT	0xff
+#define	GRF_EMMCPHY_CON6	(GRF_EMMCPHY_BASE + 0x18)
+#define	 PHYCTRL_DLL_TRM_ICP	(1 << 12) | (1 << 11) | (1 << 10) | (1 << 9)
+#define	 PHYCTRL_EN_RTRIM	(1 << 8)
+#define	 PHYCTRL_RETRIM		(1 << 7)
+#define	 PHYCTRL_DR_TY		(1 << 6) | (1 << 5) | (1 << 4)
+#define	 PHYCTRL_RETENB		(1 << 3)
+#define	 PHYCTRL_RETEN		(1 << 2)
+#define	 PHYCTRL_ENDLL		(1 << 1)
+#define	 PHYCTRL_PDB		(1 << 0)
+#define	GRF_EMMCPHY_STATUS	(GRF_EMMCPHY_BASE + 0x20)
+#define	 PHYCTRL_CALDONE	(1 << 6)
+#define	 PHYCTRL_DLLRDY		(1 << 5)
+#define	 PHYCTRL_RTRIM		(1 << 4) | (1 << 3) | (1 << 2) | (1 << 1)
+#define	 PHYCTRL_EXR_NINST	(1 << 0)
+
+static struct ofw_compat_data compat_data[] = {
+	{ "rockchip,rk3399-emmc-phy",	1 },
+	{ NULL,				0 }
+};
+
+struct rk_emmcphy_softc {
+	struct syscon		*syscon;
+	struct rk_emmcphy_conf	*phy_conf;
+	clk_t			clk;
+};
+
+#define	LOWEST_SET_BIT(mask)	((((mask) - 1) & (mask)) ^ (mask))
+#define	SHIFTIN(x, mask)	((x) * LOWEST_SET_BIT(mask))
+
+/* Phy class and methods. */
+static int rk_emmcphy_enable(struct phynode *phynode, bool enable);
+static phynode_method_t rk_emmcphy_phynode_methods[] = {
+	PHYNODEMETHOD(phynode_enable,	rk_emmcphy_enable),
+	PHYNODEMETHOD_END
+};
+
+DEFINE_CLASS_1(rk_emmcphy_phynode, rk_emmcphy_phynode_class,
+    rk_emmcphy_phynode_methods, 0, phynode_class);
+
+static int
+rk_emmcphy_enable(struct phynode *phynode, bool enable)
+{
+	struct rk_emmcphy_softc *sc;
+	device_t dev;
+	intptr_t phy;
+	uint64_t rate, frqsel;
+	uint32_t mask, val;
+	int error;
+
+	dev = phynode_get_device(phynode);
+	phy = phynode_get_id(phynode);
+	sc = device_get_softc(dev);
+
+	if (bootverbose)
+		device_printf(dev, "Phy id: %ld\n", phy);
+
+	if (phy != 0) {
+		device_printf(dev, "Unknown phy: %ld\n", phy);
+		return (ERANGE);
+	}
+	if (enable) {
+		/* Drive strength */
+		mask = PHYCTRL_DR_TY;
+		val = SHIFTIN(0, PHYCTRL_DR_TY);
+		SYSCON_WRITE_4(sc->syscon, GRF_EMMCPHY_CON6,
+		    (mask << 16) | val);
+
+		/* Enable output tap delay */
+		mask = PHYCTRL_OTAPDLYENA | PHYCTRL_OTAPDLYSEL;
+		val = PHYCTRL_OTAPDLYENA | SHIFTIN(4, PHYCTRL_OTAPDLYSEL);
+		SYSCON_WRITE_4(sc->syscon, GRF_EMMCPHY_CON0,
+		    (mask << 16) | val);
+	}
+
+	/* Power down PHY and disable DLL before making changes */
+	mask = PHYCTRL_ENDLL | PHYCTRL_PDB;
+	val = 0;
+	SYSCON_WRITE_4(sc->syscon, GRF_EMMCPHY_CON6, (mask << 16) | val);
+
+	if (enable == false)
+		return (0);
+
+	sc->phy_conf = (struct rk_emmcphy_conf *)ofw_bus_search_compatible(dev,
+	    compat_data)->ocd_data;
+
+	/* Get clock */
+	error = clk_get_by_ofw_name(dev, 0, "emmcclk", &sc->clk);
+	if (error != 0) {
+		device_printf(dev, "cannot get emmcclk clock, continue\n");
+		sc->clk = NULL;
+	} else
+		device_printf(dev, "got emmcclk clock\n");
+
+	if (sc->clk) {
+		error = clk_get_freq(sc->clk, &rate);
+		if (error != 0) {
+			device_printf(dev, "cannot get clock frequency\n");
+			return (ENXIO);
+		}
+	} else
+		rate = 0;
+
+	if (rate != 0) {
+		if (rate < 75000000)
+			frqsel = PHYCTRL_FRQSEL_50M;
+		else if (rate < 125000000)
+			frqsel = PHYCTRL_FRQSEL_100M;
+		else if (rate < 175000000)
+			frqsel = PHYCTRL_FRQSEL_150M;
+		else
+			frqsel = PHYCTRL_FRQSEL_200M;
+	} else
+		frqsel = PHYCTRL_FRQSEL_200M;
+
+	DELAY(3);
+
+	/* Power up PHY */
+	mask = PHYCTRL_PDB;
+	val = PHYCTRL_PDB;
+	SYSCON_WRITE_4(sc->syscon, GRF_EMMCPHY_CON6, (mask << 16) | val);
+
+	/* Wait for calibration */
+	DELAY(10);
+	val = SYSCON_READ_4(sc->syscon, GRF_EMMCPHY_STATUS);
+	if ((val & PHYCTRL_CALDONE) == 0) {
+		device_printf(dev, "PHY calibration did not complete\n");
+		return (ENXIO);
+	}
+
+	/* Set DLL frequency */
+	mask = PHYCTRL_FRQSEL;
+	val = SHIFTIN(frqsel, PHYCTRL_FRQSEL);
+	SYSCON_WRITE_4(sc->syscon, GRF_EMMCPHY_CON0, (mask << 16) | val);
+
+	/* Enable DLL */
+	mask = PHYCTRL_ENDLL;
+	val = PHYCTRL_ENDLL;
+	SYSCON_WRITE_4(sc->syscon, GRF_EMMCPHY_CON6, (mask << 16) | val);
+
+	if (rate != 0) {
+		/*
+		 * Rockchip RK3399 TRM V1.3 Part2.pdf says in page 698:
+		 * After the DLL control loop reaches steady state a DLL
+		 * ready signal is generated by the DLL circuits
+		 * 'phyctrl_dllrdy'.
+		 * The time from 'phyctrl_endll' to DLL ready signal
+		 * 'phyctrl_dllrdy' varies with the clock frequency.
+		 * At 200MHz clock frequency the DLL ready delay is 2.56us,
+		 * at 100MHz clock frequency the DLL ready delay is 5.112us and
+		 * at 50 MHz clock frequency the DLL ready delay is 10.231us.
+		 * We could use safe values for wait, 12us, 8us, 6us and 4us
+		 * respectively.
+		 * However due to some unknown reason it is not working and
+		 * DLL seems to take extra long time to lock.
+		 * So we will use more safe value 50ms here.
+		 */
+
+		/* Wait for DLL ready */
+		DELAY(50000);
+		val = SYSCON_READ_4(sc->syscon, GRF_EMMCPHY_STATUS);
+		if ((val & PHYCTRL_DLLRDY) == 0) {
+			device_printf(dev, "DLL loop failed to lock\n");
+			return (ENXIO);
+		}
+	}
+
+	return (0);
+}
+
+static int
+rk_emmcphy_probe(device_t dev)
+{
+
+	if (!ofw_bus_status_okay(dev))
+		return (ENXIO);
+
+	if (ofw_bus_search_compatible(dev, compat_data)->ocd_data == 0)
+		return (ENXIO);
+
+	device_set_desc(dev, "Rockchip RK3399 eMMC PHY");
+	return (BUS_PROBE_DEFAULT);
+}
+
+static int
+rk_emmcphy_attach(device_t dev)
+{
+	struct phynode_init_def phy_init;
+	struct phynode *phynode;
+	struct rk_emmcphy_softc *sc;
+	phandle_t node;
+	phandle_t xnode;
+	pcell_t handle;
+	intptr_t phy;
+
+	sc = device_get_softc(dev);
+	node = ofw_bus_get_node(dev);
+
+	if (OF_getencprop(node, "clocks", (void *)&handle,
+	    sizeof(handle)) <= 0) {
+		device_printf(dev, "cannot get clocks handle\n");
+		return (ENXIO);
+	}
+	xnode = OF_node_from_xref(handle);
+	if (OF_hasprop(xnode, "arasan,soc-ctl-syscon") &&
+	    syscon_get_by_ofw_property(dev, xnode,
+	    "arasan,soc-ctl-syscon", &sc->syscon) != 0) {
+		device_printf(dev, "cannot get grf driver handle\n");
+		return (ENXIO);
+	}
+
+	if (sc->syscon == NULL) {
+		device_printf(dev, "failed to get syscon\n");
+		return (ENXIO);
+	}
+
+	/* Create and register phy */
+	bzero(&phy_init, sizeof(phy_init));
+	phy_init.id = 0;
+	phy_init.ofw_node = ofw_bus_get_node(dev);
+	phynode = phynode_create(dev, &rk_emmcphy_phynode_class, &phy_init);
+	if (phynode == NULL) {
+		device_printf(dev, "failed to create eMMC PHY\n");
+		return (ENXIO);
+	}
+	if (phynode_register(phynode) == NULL) {
+		device_printf(dev, "failed to register eMMC PHY\n");
+		return (ENXIO);
+	}
+	if (bootverbose) {
+		phy = phynode_get_id(phynode);
+		device_printf(dev, "Attached phy id: %ld\n", phy);
+	}
+	return (0);
+}
+
+static device_method_t rk_emmcphy_methods[] = {
+	/* Device interface */
+	DEVMETHOD(device_probe,		rk_emmcphy_probe),
+	DEVMETHOD(device_attach,	rk_emmcphy_attach),
+
+	DEVMETHOD_END
+};
+
+static driver_t rk_emmcphy_driver = {
+	"rk_emmcphy",
+	rk_emmcphy_methods,
+	sizeof(struct rk_emmcphy_softc)
+};
+
+static devclass_t rk_emmcphy_devclass;
+EARLY_DRIVER_MODULE(rk_emmcphy, simplebus, rk_emmcphy_driver,
+    rk_emmcphy_devclass, 0, 0, BUS_PASS_SUPPORTDEV + BUS_PASS_ORDER_MIDDLE);
+MODULE_VERSION(rk_emmcphy, 1);

Property changes on: stable/12/sys/arm64/rockchip/rk3399_emmcphy.c
___________________________________________________________________
Added: svn:eol-style
## -0,0 +1 ##
+native
\ No newline at end of property
Added: svn:keywords
## -0,0 +1 ##
+FreeBSD=%H
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+text/plain
\ No newline at end of property
Index: stable/12/sys/arm64/rockchip/rk_grf.c
===================================================================
--- stable/12/sys/arm64/rockchip/rk_grf.c	(revision 358639)
+++ stable/12/sys/arm64/rockchip/rk_grf.c	(revision 358640)
@@ -1,85 +1,85 @@
 /*-
  * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
  *
  * Copyright (c) 2018 Emmanuel Vadot <manu@FreeBSD.org>
  * All rights reserved.
  *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions
  * are met:
  * 1. Redistributions of source code must retain the above copyright
  *    notice, this list of conditions and the following disclaimer.
  * 2. Redistributions in binary form must reproduce the above copyright
  *    notice, this list of conditions and the following disclaimer in the
  *    documentation and/or other materials provided with the distribution.
  *
  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  * SUCH DAMAGE.
  */
 
 #include <sys/cdefs.h>
 __FBSDID("$FreeBSD$");
 
 #include <sys/param.h>
 #include <sys/bus.h>
 #include <sys/kernel.h>
 #include <sys/module.h>
 #include <sys/mutex.h>
 #include <sys/rman.h>
 #include <machine/bus.h>
 
 #include <dev/ofw/openfirm.h>
 #include <dev/ofw/ofw_bus.h>
 #include <dev/ofw/ofw_bus_subr.h>
 
 #include <dev/extres/syscon/syscon.h>
-#include <dev/extres/syscon/syscon_generic.h>
+#include <dev/fdt/simple_mfd.h>
 
 #include "opt_soc.h"
 
 static struct ofw_compat_data compat_data[] = {
 #ifdef SOC_ROCKCHIP_RK3328
 	{"rockchip,rk3328-grf", 1},
 #endif
 #ifdef SOC_ROCKCHIP_RK3399
 	{"rockchip,rk3399-grf", 1},
 	{"rockchip,rk3399-pmugrf", 1},
 #endif
 	{NULL,             0}
 };
 
 static int
 rk_grf_probe(device_t dev)
 {
 
 	if (!ofw_bus_status_okay(dev))
 		return (ENXIO);
 	if (ofw_bus_search_compatible(dev, compat_data)->ocd_data == 0)
 		return (ENXIO);
 
 	device_set_desc(dev, "RockChip General Register Files");
 	return (BUS_PROBE_DEFAULT);
 }
 
 static device_method_t rk_grf_methods[] = {
 	DEVMETHOD(device_probe, rk_grf_probe),
 
 	DEVMETHOD_END
 };
 
 DEFINE_CLASS_1(rk_grf, rk_grf_driver, rk_grf_methods,
-    sizeof(struct syscon_generic_softc), syscon_generic_driver);
+    sizeof(struct simple_mfd_softc), simple_mfd_driver);
 
 static devclass_t rk_grf_devclass;
 EARLY_DRIVER_MODULE(rk_grf, simplebus, rk_grf_driver, rk_grf_devclass,
     0, 0, BUS_PASS_BUS + BUS_PASS_ORDER_MIDDLE);
 MODULE_VERSION(rk_grf, 1);
Index: stable/12/sys/arm64/rockchip/rk_i2c.c
===================================================================
--- stable/12/sys/arm64/rockchip/rk_i2c.c	(revision 358639)
+++ stable/12/sys/arm64/rockchip/rk_i2c.c	(revision 358640)
@@ -1,610 +1,702 @@
 /*-
  * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
  *
  * Copyright (c) 2018 Emmanuel Vadot <manu@FreeBSD.org>
  *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions
  * are met:
  * 1. Redistributions of source code must retain the above copyright
  *    notice, this list of conditions and the following disclaimer.
  * 2. Redistributions in binary form must reproduce the above copyright
  *    notice, this list of conditions and the following disclaimer in the
  *    documentation and/or other materials provided with the distribution.
  *
  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  * SUCH DAMAGE.
  */
 
 #include <sys/cdefs.h>
 __FBSDID("$FreeBSD$");
 
 #include <sys/param.h>
 #include <sys/bus.h>
 #include <sys/kernel.h>
 #include <sys/module.h>
 #include <sys/mutex.h>
 #include <sys/rman.h>
 #include <machine/bus.h>
 
 #include <dev/ofw/ofw_bus.h>
 #include <dev/ofw/ofw_bus_subr.h>
 
 #include <dev/iicbus/iiconf.h>
 #include <dev/iicbus/iicbus.h>
 
 #include <dev/extres/clk/clk.h>
 
 #include "iicbus_if.h"
 
-#include "opt_soc.h"
 
-
 #define	RK_I2C_CON			0x00
 #define	 RK_I2C_CON_EN			(1 << 0)
 #define	 RK_I2C_CON_MODE_SHIFT		1
 #define	 RK_I2C_CON_MODE_TX		0
 #define	 RK_I2C_CON_MODE_RRX		1
 #define	 RK_I2C_CON_MODE_RX		2
 #define	 RK_I2C_CON_MODE_RTX		3
 #define	 RK_I2C_CON_MODE_MASK		0x6
 #define	 RK_I2C_CON_START		(1 << 3)
 #define	 RK_I2C_CON_STOP		(1 << 4)
 #define	 RK_I2C_CON_LASTACK		(1 << 5)
 #define	 RK_I2C_CON_NAKSTOP		(1 << 6)
+#define	 RK_I2C_CON_CTRL_MASK		0xFF
 
 #define	RK_I2C_CLKDIV		0x04
 #define	 RK_I2C_CLKDIVL_MASK	0xFFFF
 #define	 RK_I2C_CLKDIVL_SHIFT	0
 #define	 RK_I2C_CLKDIVH_MASK	0xFFFF0000
 #define	 RK_I2C_CLKDIVH_SHIFT	16
 #define	 RK_I2C_CLKDIV_MUL	8
 
 #define	RK_I2C_MRXADDR			0x08
 #define	 RK_I2C_MRXADDR_SADDR_MASK	0xFFFFFF
 #define	 RK_I2C_MRXADDR_VALID(x)	(1 << (24 + x))
 
 #define	RK_I2C_MRXRADDR			0x0C
 #define	 RK_I2C_MRXRADDR_SRADDR_MASK	0xFFFFFF
 #define	 RK_I2C_MRXRADDR_VALID(x)	(1 << (24 + x))
 
 #define	RK_I2C_MTXCNT		0x10
 #define	 RK_I2C_MTXCNT_MASK	0x3F
 
 #define	RK_I2C_MRXCNT		0x14
 #define	 RK_I2C_MRXCNT_MASK	0x3F
 
 #define	RK_I2C_IEN		0x18
 #define	 RK_I2C_IEN_BTFIEN	(1 << 0)
 #define	 RK_I2C_IEN_BRFIEN	(1 << 1)
 #define	 RK_I2C_IEN_MBTFIEN	(1 << 2)
 #define	 RK_I2C_IEN_MBRFIEN	(1 << 3)
 #define	 RK_I2C_IEN_STARTIEN	(1 << 4)
 #define	 RK_I2C_IEN_STOPIEN	(1 << 5)
 #define	 RK_I2C_IEN_NAKRCVIEN	(1 << 6)
-#define	 RK_I2C_IEN_ALL		(RK_I2C_IEN_BTFIEN | \
-	RK_I2C_IEN_BRFIEN | RK_I2C_IEN_MBTFIEN | RK_I2C_IEN_MBRFIEN | \
+#define	 RK_I2C_IEN_ALL		(RK_I2C_IEN_MBTFIEN | RK_I2C_IEN_MBRFIEN | \
 	RK_I2C_IEN_STARTIEN | RK_I2C_IEN_STOPIEN | RK_I2C_IEN_NAKRCVIEN)
 
 #define	RK_I2C_IPD		0x1C
 #define	 RK_I2C_IPD_BTFIPD	(1 << 0)
 #define	 RK_I2C_IPD_BRFIPD	(1 << 1)
 #define	 RK_I2C_IPD_MBTFIPD	(1 << 2)
 #define	 RK_I2C_IPD_MBRFIPD	(1 << 3)
 #define	 RK_I2C_IPD_STARTIPD	(1 << 4)
 #define	 RK_I2C_IPD_STOPIPD	(1 << 5)
 #define	 RK_I2C_IPD_NAKRCVIPD	(1 << 6)
-#define	 RK_I2C_IPD_ALL		(RK_I2C_IPD_BTFIPD | \
-	RK_I2C_IPD_BRFIPD | RK_I2C_IPD_MBTFIPD | RK_I2C_IPD_MBRFIPD | \
+#define	 RK_I2C_IPD_ALL		(RK_I2C_IPD_MBTFIPD | RK_I2C_IPD_MBRFIPD | \
 	RK_I2C_IPD_STARTIPD | RK_I2C_IPD_STOPIPD | RK_I2C_IPD_NAKRCVIPD)
 
 #define	RK_I2C_FNCT		0x20
 #define	 RK_I2C_FNCT_MASK	0x3F
 
 #define	RK_I2C_TXDATA_BASE	0x100
 
 #define	RK_I2C_RXDATA_BASE	0x200
 
 enum rk_i2c_state {
 	STATE_IDLE = 0,
 	STATE_START,
 	STATE_READ,
 	STATE_WRITE,
 	STATE_STOP
 };
 
 struct rk_i2c_softc {
 	device_t	dev;
 	struct resource	*res[2];
 	struct mtx	mtx;
 	clk_t		sclk;
 	clk_t		pclk;
 	int		busy;
 	void *		intrhand;
 	uint32_t	intr;
 	uint32_t	ipd;
 	struct iic_msg	*msg;
 	size_t		cnt;
-	int		transfer_done;
-	int		nak_recv;
+	int		msg_len;
+	bool		transfer_done;
+	bool		nak_recv;
+	bool		tx_slave_addr;
 	uint8_t		mode;
 	uint8_t		state;
 
 	device_t	iicbus;
 };
 
 static struct ofw_compat_data compat_data[] = {
-#ifdef SOC_ROCKCHIP_RK3328
+	{"rockchip,rk3288-i2c", 1},
 	{"rockchip,rk3328-i2c", 1},
-#endif
-#ifdef SOC_ROCKCHIP_RK3399
 	{"rockchip,rk3399-i2c", 1},
-#endif
 	{NULL,             0}
 };
 
 static struct resource_spec rk_i2c_spec[] = {
 	{ SYS_RES_MEMORY,	0,	RF_ACTIVE },
 	{ SYS_RES_IRQ,		0,	RF_ACTIVE | RF_SHAREABLE },
 	{ -1, 0 }
 };
 
 static int rk_i2c_probe(device_t dev);
 static int rk_i2c_attach(device_t dev);
 static int rk_i2c_detach(device_t dev);
 
 #define	RK_I2C_LOCK(sc)			mtx_lock(&(sc)->mtx)
 #define	RK_I2C_UNLOCK(sc)		mtx_unlock(&(sc)->mtx)
 #define	RK_I2C_ASSERT_LOCKED(sc)	mtx_assert(&(sc)->mtx, MA_OWNED)
 #define	RK_I2C_READ(sc, reg)		bus_read_4((sc)->res[0], (reg))
 #define	RK_I2C_WRITE(sc, reg, val)	bus_write_4((sc)->res[0], (reg), (val))
 
 static uint32_t
-rk_i2c_get_clkdiv(struct rk_i2c_softc *sc, uint64_t speed)
+rk_i2c_get_clkdiv(struct rk_i2c_softc *sc, uint32_t speed)
 {
 	uint64_t sclk_freq;
 	uint32_t clkdiv;
 	int err;
 
 	err = clk_get_freq(sc->sclk, &sclk_freq);
 	if (err != 0)
 		return (err);
 
 	clkdiv = (sclk_freq / speed / RK_I2C_CLKDIV_MUL / 2) - 1;
 	clkdiv &= RK_I2C_CLKDIVL_MASK;
 
 	clkdiv = clkdiv << RK_I2C_CLKDIVH_SHIFT | clkdiv;
 
 	return (clkdiv);
 }
 
 static int
 rk_i2c_reset(device_t dev, u_char speed, u_char addr, u_char *oldaddr)
 {
 	struct rk_i2c_softc *sc;
 	uint32_t clkdiv;
 	u_int busfreq;
 
 	sc = device_get_softc(dev);
 
 	busfreq = IICBUS_GET_FREQUENCY(sc->iicbus, speed);
 
 	clkdiv = rk_i2c_get_clkdiv(sc, busfreq);
 
 	RK_I2C_LOCK(sc);
 
 	/* Set the clock divider */
 	RK_I2C_WRITE(sc, RK_I2C_CLKDIV, clkdiv);
 
 	/* Disable the module */
 	RK_I2C_WRITE(sc, RK_I2C_CON, 0);
 
 	RK_I2C_UNLOCK(sc);
 
 	return (0);
 }
 
-static void
+static uint8_t
 rk_i2c_fill_tx(struct rk_i2c_softc *sc)
 {
 	uint32_t buf32;
 	uint8_t buf;
 	int i, j, len;
 
 	if (sc->msg == NULL || sc->msg->len == sc->cnt)
-		return;
+		return (0);
 
 	len = sc->msg->len - sc->cnt;
 	if (len > 8)
 		len = 8;
 
 	for (i = 0; i < len; i++) {
 		buf32 = 0;
 		for (j = 0; j < 4 ; j++) {
 			if (sc->cnt == sc->msg->len)
 				break;
 
 			/* Fill the addr if needed */
-			if (sc->cnt == 0) {
+			if (sc->cnt == 0 && sc->tx_slave_addr) {
 				buf = sc->msg->slave;
+				sc->tx_slave_addr = false;
+			} else {
+				buf = sc->msg->buf[sc->cnt];
+				sc->cnt++;
 			}
-			else
-				buf = sc->msg->buf[sc->cnt - 1];
-
 			buf32 |= buf << (j * 8);
 
-			sc->cnt++;
 		}
-
 		RK_I2C_WRITE(sc, RK_I2C_TXDATA_BASE + 4 * i, buf32);
 
 		if (sc->cnt == sc->msg->len)
 			break;
 	}
+
+	return (uint8_t)len;
 }
 
 static void
 rk_i2c_drain_rx(struct rk_i2c_softc *sc)
 {
 	uint32_t buf32 = 0;
 	uint8_t buf8;
 	int len;
 	int i;
 
 	if (sc->msg == NULL) {
 		device_printf(sc->dev, "No current iic msg\n");
 		return;
 	}
 
 	len = sc->msg->len - sc->cnt;
 	if (len > 32)
 		len = 32;
 
 	for (i = 0; i < len; i++) {
 		if (i % 4 == 0)
 			buf32 = RK_I2C_READ(sc, RK_I2C_RXDATA_BASE + (i / 4) * 4);
 
 		buf8 = (buf32 >> ((i % 4) * 8)) & 0xFF;
-
 		sc->msg->buf[sc->cnt++] = buf8;
 	}
 }
 
 static void
-rk_i2c_send_start(struct rk_i2c_softc *sc)
-{
-	uint32_t reg;
-
-	RK_I2C_WRITE(sc, RK_I2C_IEN, RK_I2C_IEN_STARTIEN);
-
-	sc->state = STATE_START;
-
-	reg = RK_I2C_READ(sc, RK_I2C_CON);
-	reg |= RK_I2C_CON_START;
-	reg |= RK_I2C_CON_EN;
-	reg &= ~RK_I2C_CON_MODE_MASK;
-	reg |= sc->mode << RK_I2C_CON_MODE_SHIFT;
-	RK_I2C_WRITE(sc, RK_I2C_CON, reg);
-}
-
-static void
 rk_i2c_send_stop(struct rk_i2c_softc *sc)
 {
 	uint32_t reg;
 
 	RK_I2C_WRITE(sc, RK_I2C_IEN, RK_I2C_IEN_STOPIEN);
 
 	sc->state = STATE_STOP;
 
 	reg = RK_I2C_READ(sc, RK_I2C_CON);
 	reg |= RK_I2C_CON_STOP;
 	RK_I2C_WRITE(sc, RK_I2C_CON, reg);
 }
 
 static void
-rk_i2c_intr(void *arg)
+rk_i2c_intr_locked(struct rk_i2c_softc *sc)
 {
-	struct rk_i2c_softc *sc;
 	uint32_t reg;
 
-	sc = (struct rk_i2c_softc *)arg;
+	sc->ipd = RK_I2C_READ(sc, RK_I2C_IPD);
 
-	RK_I2C_LOCK(sc);
+	/* Something to handle? */
+	if ((sc->ipd & RK_I2C_IPD_ALL) == 0)
+		return;
 
-	sc->ipd = RK_I2C_READ(sc, RK_I2C_IPD);
 	RK_I2C_WRITE(sc, RK_I2C_IPD, sc->ipd);
+	sc->ipd &= RK_I2C_IPD_ALL;
 
+	if (sc->ipd & RK_I2C_IPD_NAKRCVIPD) {
+		/* NACK received */
+		sc->ipd &= ~RK_I2C_IPD_NAKRCVIPD;
+		sc->nak_recv = 1;
+		/* XXXX last byte !!!, signal error !!! */
+		sc->transfer_done = 1;
+		sc->state = STATE_IDLE;
+		goto err;
+	}
+
 	switch (sc->state) {
 	case STATE_START:
 		/* Disable start bit */
 		reg = RK_I2C_READ(sc, RK_I2C_CON);
 		reg &= ~RK_I2C_CON_START;
 		RK_I2C_WRITE(sc, RK_I2C_CON, reg);
 
 		if (sc->mode == RK_I2C_CON_MODE_RRX ||
 		    sc->mode == RK_I2C_CON_MODE_RX) {
 			sc->state = STATE_READ;
 			RK_I2C_WRITE(sc, RK_I2C_IEN, RK_I2C_IEN_MBRFIEN |
 			    RK_I2C_IEN_NAKRCVIEN);
 
 			reg = RK_I2C_READ(sc, RK_I2C_CON);
 			reg |= RK_I2C_CON_LASTACK;
 			RK_I2C_WRITE(sc, RK_I2C_CON, reg);
 
 			RK_I2C_WRITE(sc, RK_I2C_MRXCNT, sc->msg->len);
 		} else {
 			sc->state = STATE_WRITE;
 			RK_I2C_WRITE(sc, RK_I2C_IEN, RK_I2C_IEN_MBTFIEN |
 			    RK_I2C_IEN_NAKRCVIEN);
 
 			sc->msg->len += 1;
 			rk_i2c_fill_tx(sc);
 			RK_I2C_WRITE(sc, RK_I2C_MTXCNT, sc->msg->len);
 		}
 		break;
 	case STATE_READ:
 		rk_i2c_drain_rx(sc);
 
 		if (sc->cnt == sc->msg->len)
 			rk_i2c_send_stop(sc);
 
 		break;
 	case STATE_WRITE:
-		if (sc->cnt == sc->msg->len)
+		if (sc->cnt == sc->msg->len &&
+		     !(sc->msg->flags & IIC_M_NOSTOP)) {
 			rk_i2c_send_stop(sc);
-
-		break;
+			break;
+		}
+		/* passthru */
 	case STATE_STOP:
 		/* Disable stop bit */
 		reg = RK_I2C_READ(sc, RK_I2C_CON);
 		reg &= ~RK_I2C_CON_STOP;
 		RK_I2C_WRITE(sc, RK_I2C_CON, reg);
 
 		sc->transfer_done = 1;
 		sc->state = STATE_IDLE;
 		break;
 	case STATE_IDLE:
 		break;
 	}
 
+err:
 	wakeup(sc);
+}
+
+static void
+rk_i2c_intr(void *arg)
+{
+	struct rk_i2c_softc *sc;
+
+	sc = (struct rk_i2c_softc *)arg;
+
+	RK_I2C_LOCK(sc);
+	rk_i2c_intr_locked(sc);
 	RK_I2C_UNLOCK(sc);
 }
 
+static void
+rk_i2c_start_xfer(struct rk_i2c_softc *sc, struct iic_msg *msg, boolean_t last)
+{
+	uint32_t reg;
+	uint8_t len;
+
+	sc->transfer_done = false;
+	sc->nak_recv = false;
+	sc->tx_slave_addr = false;
+	sc->cnt = 0;
+	sc->state = STATE_IDLE;
+	sc->msg = msg;
+	sc->msg_len = sc->msg->len;
+
+	reg = RK_I2C_READ(sc, RK_I2C_CON) & ~RK_I2C_CON_CTRL_MASK;
+	if (!(sc->msg->flags & IIC_M_NOSTART)) {
+		/* Stadard message */
+		if (sc->mode == RK_I2C_CON_MODE_TX) {
+			sc->msg_len++;	/* Take slave address in account. */
+			sc->tx_slave_addr = true;
+		}
+		sc->state = STATE_START;
+		reg |= RK_I2C_CON_START;
+
+		RK_I2C_WRITE(sc, RK_I2C_IEN, RK_I2C_IEN_STARTIEN);
+	} else {
+		/* Continuation message */
+		if (sc->mode == RK_I2C_CON_MODE_RX) {
+			sc->state = STATE_READ;
+			if (last)
+				reg |= RK_I2C_CON_LASTACK;
+
+			RK_I2C_WRITE(sc, RK_I2C_MRXCNT, sc->msg->len);
+			RK_I2C_WRITE(sc, RK_I2C_IEN, RK_I2C_IEN_MBRFIEN |
+			    RK_I2C_IEN_NAKRCVIEN);
+		} else {
+			sc->state = STATE_WRITE;
+			len = rk_i2c_fill_tx(sc);
+
+			RK_I2C_WRITE(sc, RK_I2C_MTXCNT, len);
+
+			RK_I2C_WRITE(sc, RK_I2C_IEN, RK_I2C_IEN_MBTFIEN |
+			    RK_I2C_IEN_NAKRCVIEN);
+		}
+	}
+	reg |= sc->mode << RK_I2C_CON_MODE_SHIFT;
+	reg |= RK_I2C_CON_EN;
+	RK_I2C_WRITE(sc, RK_I2C_CON, reg);
+}
+
 static int
 rk_i2c_transfer(device_t dev, struct iic_msg *msgs, uint32_t nmsgs)
 {
 	struct rk_i2c_softc *sc;
 	uint32_t reg;
-	int i, j, msgskip, err = 0;
+	bool last_msg;
+	int i, j, timeout, err;
 
 	sc = device_get_softc(dev);
 
+	RK_I2C_LOCK(sc);
+
 	while (sc->busy)
 		mtx_sleep(sc, &sc->mtx, 0, "i2cbuswait", 0);
-
 	sc->busy = 1;
 
-	err = clk_enable(sc->pclk);
-	if (err != 0) {
-		device_printf(dev, "cannot enable pclk clock\n");
-		goto out;
-	}
-	err = clk_enable(sc->sclk);
-	if (err != 0) {
-		device_printf(dev, "cannot enable i2c clock\n");
-		goto out;
-	}
+	/* Disable the module and interrupts */
+	RK_I2C_WRITE(sc, RK_I2C_CON, 0);
+	RK_I2C_WRITE(sc, RK_I2C_IEN, 0);
 
-	RK_I2C_LOCK(sc);
-
 	/* Clean stale interrupts */
 	RK_I2C_WRITE(sc, RK_I2C_IPD, RK_I2C_IPD_ALL);
 
-	for (i = 0; i < nmsgs; i += msgskip) {
-		if (nmsgs - i >= 2 && !(msgs[i].flags & IIC_M_RD) &&
-		  msgs[i + 1].flags & IIC_M_RD && msgs[i].len <= 4) {
+	err = 0;
+	for (i = 0; i < nmsgs; i++) {
+		/* Validate parameters. */
+		if (msgs == NULL || msgs[i].buf == NULL ||
+		    msgs[i].len == 0) {
+			err = EINVAL;
+			break;
+		}
+		/*
+		 * If next message have NOSTART flag, then they both
+		 * should be same type (read/write) and same address.
+		 */
+		if (i < nmsgs - 1) {
+			if ((msgs[i + 1].flags & IIC_M_NOSTART) &&
+			    ((msgs[i].flags & IIC_M_RD) !=
+			    (msgs[i + 1].flags & IIC_M_RD) ||
+			    (msgs[i].slave !=  msgs[i + 1].slave))) {
+				err = EINVAL;
+				break;
+			}
+		}
+		/*
+		 * Detect simple register read case.
+		 * The first message should be IIC_M_WR | IIC_M_NOSTOP,
+		 * next pure IIC_M_RD (no other flags allowed). Both
+		 * messages should have same slave address.
+		 */
+
+		if (nmsgs - i >= 2 && msgs[i].len < 4 &&
+		    msgs[i].flags == (IIC_M_WR  | IIC_M_NOSTOP) &&
+		    msgs[i + 1].flags == IIC_M_RD &&
+		    (msgs[i].slave & ~LSB) == (msgs[i + 1].slave & ~LSB)) {
 			sc->mode = RK_I2C_CON_MODE_RRX;
-			msgskip = 2;
-			sc->msg = &msgs[i + 1];
 
 			/* Write slave address */
-			reg = msgs[i].slave | RK_I2C_MRXADDR_VALID(0);
+			reg = msgs[i].slave & ~LSB;
+			reg |= RK_I2C_MRXADDR_VALID(0);
 			RK_I2C_WRITE(sc, RK_I2C_MRXADDR, reg);
+
 			/* Write slave register address */
-			for (j = 0, reg = 0; j < msgs[i].len; j++) {
+			reg = 0;
+			for (j = 0; j < msgs[i].len ; j++) {
 				reg |= (msgs[i].buf[j] & 0xff) << (j * 8);
 				reg |= RK_I2C_MRXADDR_VALID(j);
 			}
-
 			RK_I2C_WRITE(sc, RK_I2C_MRXRADDR, reg);
+
+			i++;
 		} else {
 			if (msgs[i].flags & IIC_M_RD) {
-				sc->mode = RK_I2C_CON_MODE_RX;
-				msgs[i].slave |= LSB;
-			}
-			else {
+				if (msgs[i].flags & IIC_M_NOSTART) {
+					sc->mode = RK_I2C_CON_MODE_RX;
+				} else {
+					sc->mode = RK_I2C_CON_MODE_RRX;
+					reg = msgs[i].slave & LSB;
+					reg |= RK_I2C_MRXADDR_VALID(0);
+					RK_I2C_WRITE(sc, RK_I2C_MRXADDR, reg);
+					RK_I2C_WRITE(sc, RK_I2C_MRXRADDR, 0);
+				}
+			} else {
 				sc->mode = RK_I2C_CON_MODE_TX;
-				msgs[i].slave &= ~LSB;
 			}
-			msgskip = 1;
-			sc->msg = &msgs[i];
 		}
+		/* last message ? */
+		last_msg = (i > nmsgs - 1) ||
+		    !(msgs[i + 1].flags & IIC_M_NOSTART);
+		rk_i2c_start_xfer(sc, msgs + i, last_msg);
 
-		sc->transfer_done = 0;
-		sc->cnt = 0;
-		sc->state = STATE_IDLE;
-		rk_i2c_send_start(sc);
-
-		while (err == 0 && sc->transfer_done != 1) {
-			err = msleep(sc, &sc->mtx, 0, "rk_i2c", 10 * hz);
+		if (cold) {
+			for(timeout = 10000; timeout > 0; timeout--)  {
+				rk_i2c_intr_locked(sc);
+				if (sc->transfer_done != 0)
+					break;
+				DELAY(100);
+			}
+			if (timeout <= 0)
+				err = ETIMEDOUT;
+		} else {
+			while (err == 0 && sc->transfer_done != 1) {
+				err = msleep(sc, &sc->mtx, PZERO, "rk_i2c",
+				    10 * hz);
+			}
 		}
 	}
 
 	/* Disable the module and interrupts */
 	RK_I2C_WRITE(sc, RK_I2C_CON, 0);
 	RK_I2C_WRITE(sc, RK_I2C_IEN, 0);
 
 	sc->busy = 0;
 
 	RK_I2C_UNLOCK(sc);
-
-	err = clk_disable(sc->pclk);
-	if (err != 0) {
-		device_printf(dev, "cannot enable pclk clock\n");
-		goto out;
-	}
-	err = clk_disable(sc->sclk);
-	if (err != 0) {
-		device_printf(dev, "cannot enable i2c clock\n");
-		goto out;
-	}
-
-out:
 	return (err);
 }
 
 static int
 rk_i2c_probe(device_t dev)
 {
 
 	if (!ofw_bus_status_okay(dev))
 		return (ENXIO);
 	if (ofw_bus_search_compatible(dev, compat_data)->ocd_data == 0)
 		return (ENXIO);
 
 	device_set_desc(dev, "RockChip I2C");
 	return (BUS_PROBE_DEFAULT);
 }
 
 static int
 rk_i2c_attach(device_t dev)
 {
 	struct rk_i2c_softc *sc;
 	int error;
 
 	sc = device_get_softc(dev);
 	sc->dev = dev;
 
 	mtx_init(&sc->mtx, device_get_nameunit(dev), "rk_i2c", MTX_DEF);
 
 	if (bus_alloc_resources(dev, rk_i2c_spec, sc->res) != 0) {
 		device_printf(dev, "cannot allocate resources for device\n");
 		error = ENXIO;
 		goto fail;
 	}
 
 	if (bus_setup_intr(dev, sc->res[1],
 	    INTR_TYPE_MISC | INTR_MPSAFE, NULL, rk_i2c_intr, sc,
 	    &sc->intrhand)) {
 		bus_release_resources(dev, rk_i2c_spec, sc->res);
 		device_printf(dev, "cannot setup interrupt handler\n");
 		return (ENXIO);
 	}
 
 	clk_set_assigned(dev, ofw_bus_get_node(dev));
 
 	/* Activate the module clocks. */
 	error = clk_get_by_ofw_name(dev, 0, "i2c", &sc->sclk);
 	if (error != 0) {
 		device_printf(dev, "cannot get i2c clock\n");
 		goto fail;
 	}
-	error = clk_get_by_ofw_name(dev, 0, "pclk", &sc->pclk);
+	error = clk_enable(sc->sclk);
 	if (error != 0) {
+		device_printf(dev, "cannot enable i2c clock\n");
+		goto fail;
+	}
+	/* pclk clock is optional. */
+	error = clk_get_by_ofw_name(dev, 0, "pclk", &sc->pclk);
+	if (error != 0 && error != ENOENT) {
 		device_printf(dev, "cannot get pclk clock\n");
 		goto fail;
+	}
+	if (sc->sclk != NULL) {
+		error = clk_enable(sc->sclk);
+		if (error != 0) {
+			device_printf(dev, "cannot enable pclk clock\n");
+			goto fail;
+		}
 	}
 
 	sc->iicbus = device_add_child(dev, "iicbus", -1);
 	if (sc->iicbus == NULL) {
 		device_printf(dev, "cannot add iicbus child device\n");
 		error = ENXIO;
 		goto fail;
 	}
 
 	bus_generic_attach(dev);
 
 	return (0);
 
 fail:
 	if (rk_i2c_detach(dev) != 0)
 		device_printf(dev, "Failed to detach\n");
 	return (error);
 }
 
 static int
 rk_i2c_detach(device_t dev)
 {
 	struct rk_i2c_softc *sc;
 	int error;
 
 	sc = device_get_softc(dev);
 
 	if ((error = bus_generic_detach(dev)) != 0)
 		return (error);
 
 	if (sc->iicbus != NULL)
 		if ((error = device_delete_child(dev, sc->iicbus)) != 0)
 			return (error);
 
 	if (sc->sclk != NULL)
 		clk_release(sc->sclk);
 	if (sc->pclk != NULL)
 		clk_release(sc->pclk);
 
 	if (sc->intrhand != NULL)
 		bus_teardown_intr(sc->dev, sc->res[1], sc->intrhand);
 
 	bus_release_resources(dev, rk_i2c_spec, sc->res);
 
 	mtx_destroy(&sc->mtx);
 
 	return (0);
 }
 
 static phandle_t
 rk_i2c_get_node(device_t bus, device_t dev)
 {
 
 	return ofw_bus_get_node(bus);
 }
 
 static device_method_t rk_i2c_methods[] = {
 	DEVMETHOD(device_probe,		rk_i2c_probe),
 	DEVMETHOD(device_attach,	rk_i2c_attach),
 	DEVMETHOD(device_detach,	rk_i2c_detach),
 
 	/* OFW methods */
 	DEVMETHOD(ofw_bus_get_node,		rk_i2c_get_node),
 
 	DEVMETHOD(iicbus_callback,	iicbus_null_callback),
 	DEVMETHOD(iicbus_reset,		rk_i2c_reset),
 	DEVMETHOD(iicbus_transfer,	rk_i2c_transfer),
 
 	DEVMETHOD_END
 };
 
 static driver_t rk_i2c_driver = {
 	"rk_i2c",
 	rk_i2c_methods,
 	sizeof(struct rk_i2c_softc),
 };
 
 static devclass_t rk_i2c_devclass;
 
 EARLY_DRIVER_MODULE(rk_i2c, simplebus, rk_i2c_driver, rk_i2c_devclass, 0, 0,
     BUS_PASS_INTERRUPT + BUS_PASS_ORDER_LATE);
 EARLY_DRIVER_MODULE(ofw_iicbus, rk_i2c, ofw_iicbus_driver, ofw_iicbus_devclass,
     0, 0, BUS_PASS_INTERRUPT + BUS_PASS_ORDER_LATE);
 MODULE_DEPEND(rk_i2c, iicbus, 1, 1, 1);
 MODULE_VERSION(rk_i2c, 1);
Index: stable/12/sys/conf/files.arm64
===================================================================
--- stable/12/sys/conf/files.arm64	(revision 358639)
+++ stable/12/sys/conf/files.arm64	(revision 358640)
@@ -1,300 +1,301 @@
 # $FreeBSD$
 cloudabi32_vdso.o		optional	compat_cloudabi32	\
 	dependency	"$S/contrib/cloudabi/cloudabi_vdso_armv6_on_64bit.S"	\
 	compile-with	"${CC} -x assembler-with-cpp -m32 -shared -nostdinc -nostdlib -Wl,-T$S/compat/cloudabi/cloudabi_vdso.lds $S/contrib/cloudabi/cloudabi_vdso_armv6_on_64bit.S -o ${.TARGET}" \
 	no-obj no-implicit-rule						\
 	clean		"cloudabi32_vdso.o"
 #
 cloudabi32_vdso_blob.o		optional	compat_cloudabi32	\
 	dependency 	"cloudabi32_vdso.o"			\
 	compile-with	"${OBJCOPY} --input-target binary --output-target elf64-littleaarch64 --binary-architecture aarch64 cloudabi32_vdso.o ${.TARGET}" \
 	no-implicit-rule						\
 	clean		"cloudabi32_vdso_blob.o"
 #
 cloudabi64_vdso.o		optional	compat_cloudabi64	\
 	dependency	"$S/contrib/cloudabi/cloudabi_vdso_aarch64.S"	\
 	compile-with	"${CC} -x assembler-with-cpp -shared -nostdinc -nostdlib -Wl,-T$S/compat/cloudabi/cloudabi_vdso.lds $S/contrib/cloudabi/cloudabi_vdso_aarch64.S -o ${.TARGET}" \
 	no-obj no-implicit-rule						\
 	clean		"cloudabi64_vdso.o"
 #
 cloudabi64_vdso_blob.o		optional	compat_cloudabi64	\
 	dependency 	"cloudabi64_vdso.o"			\
 	compile-with	"${OBJCOPY} --input-target binary --output-target elf64-littleaarch64 --binary-architecture aarch64 cloudabi64_vdso.o ${.TARGET}" \
 	no-implicit-rule						\
 	clean		"cloudabi64_vdso_blob.o"
 #
 
 # Allwinner common files
 arm/allwinner/a10_timer.c	optional	a10_timer fdt
 arm/allwinner/a10_codec.c	optional	sound a10_codec
 arm/allwinner/a31_dmac.c	optional	a31_dmac
 arm/allwinner/sunxi_dma_if.m	optional	a31_dmac
 arm/allwinner/aw_cir.c		optional	evdev aw_cir fdt
 arm/allwinner/aw_gpio.c		optional	gpio aw_gpio fdt
 arm/allwinner/aw_mmc.c		optional	mmc aw_mmc fdt | mmccam aw_mmc fdt
 arm/allwinner/aw_nmi.c		optional	aw_nmi fdt \
 	compile-with "${NORMAL_C} -I$S/gnu/dts/include"
 arm/allwinner/aw_pwm.c		optional	aw_pwm fdt
 arm/allwinner/aw_rsb.c		optional	aw_rsb fdt
 arm/allwinner/aw_rtc.c		optional	aw_rtc fdt
 arm/allwinner/aw_sid.c		optional	aw_sid nvmem fdt
 arm/allwinner/aw_spi.c		optional	aw_spi fdt
 arm/allwinner/aw_syscon.c	optional	aw_syscon ext_resources syscon fdt
 arm/allwinner/aw_thermal.c	optional	aw_thermal nvmem fdt
 arm/allwinner/aw_usbphy.c	optional	ehci aw_usbphy fdt
 arm/allwinner/aw_wdog.c		optional	aw_wdog fdt
 arm/allwinner/axp81x.c		optional	axp81x fdt
 arm/allwinner/if_awg.c		optional	awg ext_resources syscon aw_sid nvmem fdt
 
 # Allwinner clock driver
 arm/allwinner/clkng/aw_ccung.c		optional	aw_ccu fdt
 arm/allwinner/clkng/aw_clk_frac.c	optional	aw_ccu fdt
 arm/allwinner/clkng/aw_clk_m.c		optional	aw_ccu fdt
 arm/allwinner/clkng/aw_clk_mipi.c	optional	aw_ccu fdt
 arm/allwinner/clkng/aw_clk_nkmp.c	optional	aw_ccu fdt
 arm/allwinner/clkng/aw_clk_nm.c		optional	aw_ccu fdt
 arm/allwinner/clkng/aw_clk_nmm.c	optional	aw_ccu fdt
 arm/allwinner/clkng/aw_clk_np.c		optional	aw_ccu fdt
 arm/allwinner/clkng/aw_clk_prediv_mux.c	optional	aw_ccu fdt
 arm/allwinner/clkng/ccu_a64.c		optional	soc_allwinner_a64 aw_ccu fdt
 arm/allwinner/clkng/ccu_h3.c		optional	soc_allwinner_h5 aw_ccu fdt
 arm/allwinner/clkng/ccu_sun8i_r.c	optional	aw_ccu fdt
 arm/allwinner/clkng/ccu_de2.c		optional	aw_ccu fdt
 
 # Allwinner padconf files
 arm/allwinner/a64/a64_padconf.c	optional	soc_allwinner_a64 fdt
 arm/allwinner/a64/a64_r_padconf.c optional	soc_allwinner_a64 fdt
 arm/allwinner/h3/h3_padconf.c	optional	soc_allwinner_h5 fdt
 arm/allwinner/h3/h3_r_padconf.c optional	soc_allwinner_h5 fdt
 
 arm/annapurna/alpine/alpine_ccu.c		optional	al_ccu fdt
 arm/annapurna/alpine/alpine_nb_service.c	optional	al_nb_service fdt
 arm/annapurna/alpine/alpine_pci.c		optional	al_pci fdt
 arm/annapurna/alpine/alpine_pci_msix.c		optional	al_pci fdt
 arm/annapurna/alpine/alpine_serdes.c		optional al_serdes fdt		\
 	no-depend	\
 	compile-with "${CC} -c -o ${.TARGET} ${CFLAGS} -I$S/contrib/alpine-hal -I$S/contrib/alpine-hal/eth ${PROF} ${.IMPSRC}"
 arm/arm/generic_timer.c		standard
 arm/arm/gic.c			standard
 arm/arm/gic_acpi.c		optional	acpi
 arm/arm/gic_fdt.c		optional	fdt
 arm/arm/pmu.c			standard
 arm/arm/physmem.c		standard
 arm/broadcom/bcm2835/bcm2835_audio.c		optional sound vchiq fdt \
 	compile-with "${NORMAL_C} -DUSE_VCHIQ_ARM -D__VCCOREVER__=0x04000000 -I$S/contrib/vchiq"
 arm/broadcom/bcm2835/bcm2835_bsc.c		optional bcm2835_bsc fdt
 arm/broadcom/bcm2835/bcm2835_clkman.c		optional soc_brcm_bcm2837 fdt | soc_brcm_bcm2838 fdt
 arm/broadcom/bcm2835/bcm2835_cpufreq.c		optional soc_brcm_bcm2837 fdt | soc_brcm_bcm2838 fdt
 arm/broadcom/bcm2835/bcm2835_dma.c		optional soc_brcm_bcm2837 fdt | soc_brcm_bcm2838 fdt
 arm/broadcom/bcm2835/bcm2835_fbd.c		optional vt soc_brcm_bcm2837 fdt | vt soc_brcm_bcm2838 fdt
 arm/broadcom/bcm2835/bcm2835_ft5406.c		optional evdev bcm2835_ft5406 fdt
 arm/broadcom/bcm2835/bcm2835_gpio.c		optional gpio soc_brcm_bcm2837 fdt | gpio soc_brcm_bcm2838 fdt
 arm/broadcom/bcm2835/bcm2835_intr.c		optional soc_brcm_bcm2837 fdt | soc_brcm_bcm2838 fdt
 arm/broadcom/bcm2835/bcm2835_mbox.c		optional soc_brcm_bcm2837 fdt | soc_brcm_bcm2838 fdt
 arm/broadcom/bcm2835/bcm2835_rng.c		optional random soc_brcm_bcm2837 fdt | random soc_brcm_bcm2838 fdt
 arm/broadcom/bcm2835/bcm2835_sdhci.c		optional sdhci soc_brcm_bcm2837 fdt | sdhci soc_brcm_bcm2838 fdt
 arm/broadcom/bcm2835/bcm2835_sdhost.c		optional sdhci soc_brcm_bcm2837 fdt | sdhci soc_brcm_bcm2838 fdt
 arm/broadcom/bcm2835/bcm2835_spi.c		optional bcm2835_spi fdt
 arm/broadcom/bcm2835/bcm2835_vcbus.c		optional soc_brcm_bcm2837 fdt | soc_brcm_bcm2838 fdt
 arm/broadcom/bcm2835/bcm2835_vcio.c		optional soc_brcm_bcm2837 fdt | soc_brcm_bcm2838 fdt
 arm/broadcom/bcm2835/bcm2835_wdog.c		optional soc_brcm_bcm2837 fdt | soc_brcm_bcm2838 fdt
 arm/broadcom/bcm2835/bcm2836.c			optional soc_brcm_bcm2837 fdt | soc_brcm_bcm2838 fdt
 arm/broadcom/bcm2835/bcm283x_dwc_fdt.c		optional dwcotg fdt soc_brcm_bcm2837 | dwcotg fdt soc_brcm_bcm2838
 arm/mv/a37x0_gpio.c				optional a37x0_gpio gpio fdt
 arm/mv/gpio.c					optional mv_gpio fdt
 arm/mv/mvebu_pinctrl.c				optional mvebu_pinctrl fdt
 arm/mv/mv_cp110_icu.c				optional mv_cp110_icu fdt
 arm/mv/mv_ap806_gicp.c				optional mv_ap806_gicp fdt
 arm/mv/mv_ap806_clock.c				optional SOC_MARVELL_8K fdt
 arm/mv/mv_cp110_clock.c				optional SOC_MARVELL_8K fdt
 arm/mv/mv_thermal.c				optional SOC_MARVELL_8K mv_thermal fdt
 arm/mv/armada38x/armada38x_rtc.c		optional mv_rtc fdt
 arm/xilinx/uart_dev_cdnc.c			optional uart soc_xilinx_zynq
 arm64/acpica/acpi_iort.c	optional	acpi
 arm64/acpica/acpi_machdep.c	optional	acpi
 arm64/acpica/OsdEnvironment.c	optional	acpi
 arm64/acpica/acpi_wakeup.c	optional	acpi
 arm64/acpica/pci_cfgreg.c	optional	acpi	pci
 arm64/arm64/autoconf.c		standard
 arm64/arm64/bus_machdep.c	standard
 arm64/arm64/bus_space_asm.S	standard
 arm64/arm64/busdma_bounce.c	standard
 arm64/arm64/busdma_machdep.c	standard
 arm64/arm64/bzero.S		standard
 arm64/arm64/clock.c		standard
 arm64/arm64/copyinout.S		standard
 arm64/arm64/copystr.c		standard
 arm64/arm64/cpu_errata.c	standard
 arm64/arm64/cpufunc_asm.S	standard
 arm64/arm64/db_disasm.c		optional	ddb
 arm64/arm64/db_interface.c	optional	ddb
 arm64/arm64/db_trace.c		optional	ddb
 arm64/arm64/debug_monitor.c	optional	ddb
 arm64/arm64/disassem.c		optional	ddb
 arm64/arm64/dump_machdep.c	standard
 arm64/arm64/efirt_machdep.c	optional	efirt
 arm64/arm64/elf32_machdep.c	optional	compat_freebsd32
 arm64/arm64/elf_machdep.c	standard
 arm64/arm64/exception.S		standard
 arm64/arm64/freebsd32_machdep.c	optional	compat_freebsd32
 arm64/arm64/gicv3_its.c		optional	intrng fdt
 arm64/arm64/gic_v3.c		standard
 arm64/arm64/gic_v3_acpi.c	optional	acpi
 arm64/arm64/gic_v3_fdt.c	optional	fdt
 arm64/arm64/identcpu.c		standard
 arm64/arm64/in_cksum.c		optional	inet | inet6
 arm64/arm64/locore.S		standard	no-obj
 arm64/arm64/machdep.c		standard
 arm64/arm64/mem.c		standard
 arm64/arm64/memcpy.S		standard
 arm64/arm64/memmove.S		standard
 arm64/arm64/minidump_machdep.c	standard
 arm64/arm64/mp_machdep.c	optional	smp
 arm64/arm64/nexus.c		standard
 arm64/arm64/ofw_machdep.c	optional	fdt
 arm64/arm64/pmap.c		standard
 arm64/arm64/stack_machdep.c	optional	ddb | stack
 arm64/arm64/support.S		standard
 arm64/arm64/swtch.S		standard
 arm64/arm64/sys_machdep.c	standard
 arm64/arm64/trap.c		standard
 arm64/arm64/uio_machdep.c	standard
 arm64/arm64/uma_machdep.c	standard
 arm64/arm64/undefined.c		standard
 arm64/arm64/unwind.c		optional	ddb | kdtrace_hooks | stack
 arm64/arm64/vfp.c		standard
 arm64/arm64/vm_machdep.c	standard
 arm64/cavium/thunder_pcie_fdt.c		optional	soc_cavm_thunderx pci fdt
 arm64/cavium/thunder_pcie_pem.c		optional	soc_cavm_thunderx pci
 arm64/cavium/thunder_pcie_pem_fdt.c	optional	soc_cavm_thunderx pci fdt
 arm64/cavium/thunder_pcie_common.c	optional	soc_cavm_thunderx pci
 arm64/cloudabi32/cloudabi32_sysvec.c	optional compat_cloudabi32
 arm64/cloudabi64/cloudabi64_sysvec.c	optional compat_cloudabi64
 arm64/coresight/coresight.c			standard
 arm64/coresight/coresight_if.m			standard
 arm64/coresight/coresight-cmd.c			standard
 arm64/coresight/coresight-cpu-debug.c		standard
 arm64/coresight/coresight-dynamic-replicator.c	standard
 arm64/coresight/coresight-etm4x.c		standard
 arm64/coresight/coresight-funnel.c		standard
 arm64/coresight/coresight-tmc.c			standard
 arm64/qualcomm/qcom_gcc.c			optional qcom_gcc fdt
 contrib/vchiq/interface/compat/vchi_bsd.c	optional vchiq soc_brcm_bcm2837 \
 	compile-with "${NORMAL_C} -DUSE_VCHIQ_ARM -D__VCCOREVER__=0x04000000 -I$S/contrib/vchiq"
 contrib/vchiq/interface/vchiq_arm/vchiq_2835_arm.c	optional vchiq soc_brcm_bcm2837 \
 	compile-with "${NORMAL_C} -Wno-unused -DUSE_VCHIQ_ARM -D__VCCOREVER__=0x04000000 -I$S/contrib/vchiq"
 contrib/vchiq/interface/vchiq_arm/vchiq_arm.c	optional vchiq soc_brcm_bcm2837 \
 	compile-with "${NORMAL_C} -Wno-unused -DUSE_VCHIQ_ARM -D__VCCOREVER__=0x04000000 -I$S/contrib/vchiq"
 contrib/vchiq/interface/vchiq_arm/vchiq_connected.c	optional vchiq soc_brcm_bcm2837 \
 	compile-with "${NORMAL_C} -DUSE_VCHIQ_ARM -D__VCCOREVER__=0x04000000 -I$S/contrib/vchiq"
 contrib/vchiq/interface/vchiq_arm/vchiq_core.c	optional vchiq soc_brcm_bcm2837 \
 	compile-with "${NORMAL_C} -DUSE_VCHIQ_ARM -D__VCCOREVER__=0x04000000 -I$S/contrib/vchiq"
 contrib/vchiq/interface/vchiq_arm/vchiq_kern_lib.c	optional vchiq soc_brcm_bcm2837 \
 	compile-with "${NORMAL_C} -DUSE_VCHIQ_ARM -D__VCCOREVER__=0x04000000 -I$S/contrib/vchiq"
 contrib/vchiq/interface/vchiq_arm/vchiq_kmod.c	optional vchiq soc_brcm_bcm2837 \
 	compile-with "${NORMAL_C} -DUSE_VCHIQ_ARM -D__VCCOREVER__=0x04000000 -I$S/contrib/vchiq"
 contrib/vchiq/interface/vchiq_arm/vchiq_shim.c	optional vchiq soc_brcm_bcm2837 \
 	compile-with "${NORMAL_C} -DUSE_VCHIQ_ARM -D__VCCOREVER__=0x04000000 -I$S/contrib/vchiq"
 contrib/vchiq/interface/vchiq_arm/vchiq_util.c	optional vchiq soc_brcm_bcm2837 \
 	compile-with "${NORMAL_C} -DUSE_VCHIQ_ARM -D__VCCOREVER__=0x04000000 -I$S/contrib/vchiq"
 crypto/armv8/armv8_crypto.c	optional	armv8crypto
 armv8_crypto_wrap.o		optional	armv8crypto		\
 	dependency	"$S/crypto/armv8/armv8_crypto_wrap.c"		\
 	compile-with	"${CC} -c ${CFLAGS:C/^-O2$/-O3/:N-nostdinc:N-mgeneral-regs-only} -I$S/crypto/armv8/ ${WERROR} ${NO_WCAST_QUAL} ${PROF} -march=armv8-a+crypto ${.IMPSRC}" \
 	no-implicit-rule						\
 	clean		"armv8_crypto_wrap.o"
 crypto/blowfish/bf_enc.c	optional	crypto | ipsec | ipsec_support
 crypto/des/des_enc.c		optional	crypto | ipsec | ipsec_support | netsmb
 dev/acpica/acpi_bus_if.m	optional	acpi
 dev/acpica/acpi_if.m		optional	acpi
 dev/acpica/acpi_pci_link.c	optional	acpi pci
 dev/acpica/acpi_pcib.c		optional	acpi pci
 dev/acpica/acpi_pxm.c		optional	acpi
 dev/ahci/ahci_generic.c		optional	ahci
 dev/axgbe/if_axgbe.c		optional	axgbe
 dev/axgbe/xgbe-desc.c		optional	axgbe
 dev/axgbe/xgbe-dev.c		optional	axgbe
 dev/axgbe/xgbe-drv.c		optional	axgbe
 dev/axgbe/xgbe-mdio.c		optional	axgbe
 dev/cpufreq/cpufreq_dt.c	optional	cpufreq fdt
 dev/iicbus/twsi/mv_twsi.c	optional	twsi fdt
 dev/iicbus/twsi/a10_twsi.c	optional	twsi fdt
 dev/iicbus/twsi/twsi.c		optional	twsi fdt
 dev/hwpmc/hwpmc_arm64.c		optional	hwpmc
 dev/hwpmc/hwpmc_arm64_md.c	optional	hwpmc
 dev/mbox/mbox_if.m		optional	soc_brcm_bcm2837
 dev/mmc/host/dwmmc.c		optional	dwmmc fdt
 dev/mmc/host/dwmmc_hisi.c	optional	dwmmc fdt soc_hisi_hi6220
 dev/mmc/host/dwmmc_rockchip.c	optional	dwmmc fdt soc_rockchip_rk3328
 dev/neta/if_mvneta_fdt.c	optional	neta fdt
 dev/neta/if_mvneta.c		optional	neta mdio mii
 dev/ofw/ofw_cpu.c		optional	fdt
 dev/ofw/ofwpci.c		optional 	fdt pci
 dev/pci/pci_host_generic.c	optional	pci
 dev/pci/pci_host_generic_acpi.c	optional	pci acpi
 dev/pci/pci_host_generic_fdt.c	optional	pci fdt
 dev/psci/psci.c			standard
 dev/psci/psci_arm64.S		standard
 dev/psci/smccc.c		standard
 dev/sdhci/sdhci_xenon.c		optional	sdhci_xenon sdhci fdt
 dev/uart/uart_cpu_arm64.c	optional	uart
 dev/uart/uart_dev_mu.c		optional	uart uart_mu
 dev/uart/uart_dev_pl011.c	optional	uart pl011
 dev/usb/controller/dwc_otg_hisi.c optional	dwcotg fdt soc_hisi_hi6220
 dev/usb/controller/ehci_mv.c	optional	ehci_mv fdt
 dev/usb/controller/generic_ehci.c optional	ehci
 dev/usb/controller/generic_ehci_acpi.c optional	ehci acpi
 dev/usb/controller/generic_ehci_fdt.c optional	ehci fdt
 dev/usb/controller/generic_ohci.c optional	ohci fdt
 dev/usb/controller/generic_usb_if.m optional	ohci fdt
 dev/usb/controller/usb_nop_xceiv.c	optional fdt ext_resources
 dev/usb/controller/generic_xhci.c	optional	xhci fdt
 dev/vnic/mrml_bridge.c		optional	vnic fdt
 dev/vnic/nic_main.c		optional	vnic pci
 dev/vnic/nicvf_main.c		optional	vnic pci pci_iov
 dev/vnic/nicvf_queues.c		optional	vnic pci pci_iov
 dev/vnic/thunder_bgx_fdt.c	optional	vnic fdt
 dev/vnic/thunder_bgx.c		optional	vnic pci
 dev/vnic/thunder_mdio_fdt.c	optional	vnic fdt
 dev/vnic/thunder_mdio.c		optional	vnic
 dev/vnic/lmac_if.m		optional	inet | inet6 | vnic
 kern/kern_clocksource.c		standard
 kern/msi_if.m			optional	intrng
 kern/pic_if.m			optional	intrng
 kern/subr_devmap.c		standard
 kern/subr_intr.c		optional	intrng
 libkern/bcmp.c			standard
 libkern/ffs.c			standard
 libkern/ffsl.c			standard
 libkern/ffsll.c			standard
 libkern/fls.c			standard
 libkern/flsl.c			standard
 libkern/flsll.c			standard
 libkern/memcmp.c		standard
 libkern/memset.c		standard
 libkern/arm64/crc32c_armv8.S	standard
 cddl/dev/dtrace/aarch64/dtrace_asm.S			optional dtrace compile-with "${DTRACE_S}"
 cddl/dev/dtrace/aarch64/dtrace_subr.c			optional dtrace compile-with "${DTRACE_C}"
 cddl/dev/fbt/aarch64/fbt_isa.c				optional dtrace_fbt | dtraceall compile-with "${FBT_C}"
 
 # RockChip Drivers
+arm64/rockchip/rk3399_emmcphy.c		optional fdt rk_emmcphy soc_rockchip_rk3399
 arm64/rockchip/rk_i2c.c			optional fdt rk_i2c soc_rockchip_rk3328 | fdt rk_i2c soc_rockchip_rk3399
 arm64/rockchip/rk805.c			optional fdt rk805 soc_rockchip_rk3328 | fdt rk805 soc_rockchip_rk3399
 arm64/rockchip/rk_grf.c			optional fdt soc_rockchip_rk3328 | fdt soc_rockchip_rk3399
 arm64/rockchip/rk_pinctrl.c		optional fdt rk_pinctrl soc_rockchip_rk3328 | fdt rk_pinctrl soc_rockchip_rk3399
 arm64/rockchip/rk_gpio.c		optional fdt rk_gpio soc_rockchip_rk3328 | fdt rk_gpio soc_rockchip_rk3399
 arm64/rockchip/rk_usb2phy.c		optional fdt rk_usb2phy soc_rockchip_rk3328 | soc_rockchip_rk3399
 arm64/rockchip/if_dwc_rk.c		optional fdt dwc_rk soc_rockchip_rk3328 | fdt dwc_rk soc_rockchip_rk3399
 dev/dwc/if_dwc.c			optional fdt dwc_rk soc_rockchip_rk3328 | fdt dwc_rk soc_rockchip_rk3399
 dev/dwc/if_dwc_if.m			optional fdt dwc_rk soc_rockchip_rk3328 | fdt dwc_rk soc_rockchip_rk3399
 
 # RockChip Clock support
 arm64/rockchip/clk/rk_cru.c		optional fdt soc_rockchip_rk3328 | fdt soc_rockchip_rk3399
 arm64/rockchip/clk/rk_clk_armclk.c	optional fdt soc_rockchip_rk3328 | fdt soc_rockchip_rk3399
 arm64/rockchip/clk/rk_clk_composite.c	optional fdt soc_rockchip_rk3328 | fdt soc_rockchip_rk3399
 arm64/rockchip/clk/rk_clk_gate.c	optional fdt soc_rockchip_rk3328 | fdt soc_rockchip_rk3399
 arm64/rockchip/clk/rk_clk_mux.c		optional fdt soc_rockchip_rk3328 | fdt soc_rockchip_rk3399
 arm64/rockchip/clk/rk_clk_pll.c		optional fdt soc_rockchip_rk3328 | fdt soc_rockchip_rk3399
 arm64/rockchip/clk/rk3328_cru.c		optional fdt soc_rockchip_rk3328
 arm64/rockchip/clk/rk3399_cru.c		optional fdt soc_rockchip_rk3399
 arm64/rockchip/clk/rk3399_pmucru.c	optional fdt soc_rockchip_rk3399
Index: stable/12
===================================================================
--- stable/12	(revision 358639)
+++ stable/12	(revision 358640)

Property changes on: stable/12
___________________________________________________________________
Modified: svn:mergeinfo
## -0,0 +0,1 ##
   Merged /head:r349638,350161,351186