Index: head/sys/arm/conf/GENERIC =================================================================== --- head/sys/arm/conf/GENERIC (revision 356894) +++ head/sys/arm/conf/GENERIC (revision 356895) @@ -1,294 +1,295 @@ # # GENERICV6 -- Generic(ish) kernel config. # # For more information on this file, please read the config(5) manual page, # and/or the handbook section on Kernel Configuration Files: # # https://www.FreeBSD.org/doc/en_US.ISO8859-1/books/handbook/kernelconfig-config.html # # The handbook is also available locally in /usr/share/doc/handbook # if you've installed the doc distribution, otherwise always see the # FreeBSD World Wide Web server (https://www.FreeBSD.org/) for the # latest information. # # An exhaustive list of options and more detailed explanations of the # device lines is also present in the ../../conf/NOTES and NOTES files. # If you are in doubt as to the purpose or necessity of a line, check first # in NOTES. # # $FreeBSD$ ident GENERIC cpu CPU_CORTEXA cpu CPU_MV_PJ4B options SMP_ON_UP machine arm armv7 makeoptions CONF_CFLAGS="-march=armv7a" include "std.armv7" files "../allwinner/files.allwinner" files "../allwinner/files.allwinner_up" files "../allwinner/a10/files.a10" files "../allwinner/a13/files.a13" files "../allwinner/a20/files.a20" files "../allwinner/a31/files.a31" files "../allwinner/a33/files.a33" files "../allwinner/a83t/files.a83t" files "../allwinner/h3/files.h3" files "../broadcom/bcm2835/files.bcm2836" files "../broadcom/bcm2835/files.bcm283x" files "../freescale/imx/files.imx6" files "../mv/files.arm7" files "../nvidia/tegra124/files.tegra124" files "../qemu/files.qemu" files "../ti/files.ti" files "../ti/am335x/files.am335x" files "../ti/omap4/files.omap4" files "../xilinx/files.zynq7" options SOC_ALLWINNER_A10 options SOC_ALLWINNER_A13 options SOC_ALLWINNER_A20 options SOC_ALLWINNER_A31 options SOC_ALLWINNER_A31S options SOC_ALLWINNER_A33 options SOC_ALLWINNER_A83T options SOC_ALLWINNER_H2PLUS options SOC_ALLWINNER_H3 options SOC_BCM2836 options SOC_BRCM_BCM2837 options SOC_MV_ARMADA38X options SOC_MV_ARMADAXP options SOC_TI_AM335X options SOC_OMAP4 options SCHED_ULE # ULE scheduler options SMP # Enable multiple cores options PLATFORM options LINUX_BOOT_ABI # EXT_RESOURCES pseudo devices options EXT_RESOURCES device clk device phy device hwreset device nvmem device regulator device syscon # CPU frequency control device cpufreq # Interrupt controller device gic # PMU support (for CCNT). device pmu # ARM Generic Timer device generic_timer device mpcore_timer # MMC/SD/SDIO Card slot support device sdhci # SD controller device mmc # mmc/sd bus device mmcsd # mmc/sd flash cards # ATA controllers device ahci # AHCI-compatible SATA controllers #device ata # Legacy ATA/SATA controllers # PCI options NEW_PCIB device pci device pci_host_generic # PCI NICs device re # RealTek 8139C+/8169/8169S/8110S # VirtIO device virtio device virtio_mmio device virtio_pci device virtio_blk device vtnet # Console and misc device uart device uart_ns8250 device uart_snps device pl011 device pty device snp device md # Memory "disks" device firmware # firmware assist module device pl310 # PL310 L2 cache controller device psci # I2C support device iicbus device iic device twsi device rsb # Allwinner Reduced Serial Bus device p2wi # Allwinner Push-Pull Two Wire device axp209 # AXP209 Power Management Unit device axp81x # AXP813/818 Power Management Unit device bcm2835_bsc device fsliic # Freescale i2c/iic device icee # AT24Cxxx and compatible EEPROMs device sy8106a # SY8106A Buck Regulator device ti_i2c device am335x_pmic # AM335x Power Management IC (TPC65217) device am335x_rtc # RTC support (power management only) device twl # TI TWLX0X0/TPS659x0 Power Management device twl_vreg # twl voltage regulation device twl_clks # twl external clocks # i2c RTCs device ds1307 # Dallas DS1307 RTC and compatible device ds13rtc # All Dallas/Maxim DS13xx RTCs device ds1672 # Dallas DS1672 RTC device ds3231 # Dallas DS3231 RTC + temperature device nxprtc # NXP RTCs: PCA/PFC212x PCA/PCF85xx device s35390a # Seiko s3539x RTCs # GPIO device dwgpio # Synopsys DesignWare APB GPIO Controller device gpio device gpiobacklight device gpioled device gpioregulator # EVDEV support device evdev # input event device support options EVDEV_SUPPORT # evdev support in legacy drivers device uinput # install /dev/uinput cdev device aw_cir # SPI device spibus device spigen device bcm2835_spi device mv_spi device ti_spi +device zy7_qspi # Xilinx Zynq QSPI controller # ADC support device ti_adc # PWM device pwm # Watchdog support # If we don't enable the watchdog driver, the BealeBone could potentially # reboot automatically because the boot loader might have enabled the # watchdog. device ti_wdt device imxwdt # Watchdog. WARNING: can't be disabled!!! device aw_wdog # Allwinner Watchdog device scbus # SCSI bus (required for ATA/SCSI) device da # Direct Access (disks) device cd # CD device pass # Passthrough device (direct ATA/SCSI access) # USB support options USB_HOST_ALIGN=64 # Align usb buffers to cache line size. device usb device uhci device ohci device ehci device xhci device dwcotg # DWC OTG controller device musb device axe # USB-Ethernet device umass # Disks/Mass storage - Requires scbus and da device uhid # "Human Interface Devices" device ukbd # Allow keyboard like HIDs to control console # Device mode support device usb_template # Control of the gadget # Ethernet device loop device ether device vlan # 802.1Q VLAN support device bpf device mii device mdio device etherswitch device e6000sw # Ethernet NICs that use the common MII bus controller code. # NOTE: Be sure to keep the 'device miibus' line in order to use these NICs! device miibus device awg # 10/100/1000 integrated EMAC controller device cpsw # TI Common Platform Ethernet Switch (CPSW) device cgem # Zynq-7000 gig ethernet device device dwc # 10/100/1000 integrated GMAC controller device emac # 10/100 integrated EMAC controller device ffec # Freescale Fast Ethernet Controller device neta # Marvell 10/100/1000 Network controller device smsc # SMSC LAN91C111 # Sound support device sound # Framebuffer support device vt device kbdmux device ums device videomode device hdmi device vchiq # Pinmux device fdt_pinctrl # TI Programmable Realtime Unit support device ti_pruss # Mailbox support device ti_mbox # DMA controller device fslsdma device ti_sdma device a10_dmac device a31_dmac # Extensible Firmware Interface options EFI # Marvell Cryptographic Engine and Security Accelerator device cesa device crypto device cryptodev # RTC device imx6_snvs # IMX6 On-chip RTC device aw_rtc # Allwinner On-chip RTC # EFUSE device aw_sid # Allwinner Secure ID EFUSE # Thermal sensors device aw_thermal # Allwinner Thermal Sensor Controller # Flattened Device Tree options FDT # Configure using FDT/DTB data makeoptions MODULES_EXTRA+="dtb/allwinner" makeoptions MODULES_EXTRA+="dtb/am335x" makeoptions MODULES_EXTRA+="dtb/imx6" makeoptions MODULES_EXTRA+="dtb/nvidia" makeoptions MODULES_EXTRA+="dtb/omap4" makeoptions MODULES_EXTRA+="dtb/rpi" makeoptions MODULES_EXTRA+="dtb/zynq" # SOC-specific modules makeoptions MODULES_EXTRA+="allwinner" makeoptions MODULES_EXTRA+="arm_ti" makeoptions MODULES_EXTRA+="imx" Index: head/sys/arm/conf/ZEDBOARD =================================================================== --- head/sys/arm/conf/ZEDBOARD (revision 356894) +++ head/sys/arm/conf/ZEDBOARD (revision 356895) @@ -1,79 +1,83 @@ # # ZEDBOARD -- Custom configuration for the Xilinx Zynq-7000 based # ZedBoard (www.zedboard.org) and similar Zynq boards. # # For more information on this file, please read the config(5) manual page, # and/or the handbook section on Kernel Configuration Files: # # https://www.FreeBSD.org/doc/en_US.ISO8859-1/books/handbook/kernelconfig-config.html # # The handbook is also available locally in /usr/share/doc/handbook # if you've installed the doc distribution, otherwise always see the # FreeBSD World Wide Web server (https://www.FreeBSD.org/) for the # latest information. # # An exhaustive list of options and more detailed explanations of the # device lines is also present in the ../../conf/NOTES and NOTES files. # If you are in doubt as to the purpose or necessity of a line, check first # in NOTES. # # $FreeBSD$ ident ZEDBOARD include "std.armv7" include "../xilinx/std.zynq7" makeoptions MODULES_EXTRA="dtb/zynq" options SCHED_ULE # ULE scheduler options PLATFORM # Platform based SoC #options NFSSD # Network Filesystem Server options SMP # Enable multiple cores # NFS root from boopt/dhcp #options BOOTP #options BOOTP_NFSROOT #options BOOTP_COMPAT #options BOOTP_NFSV3 options ROOTDEVNAME=\"ufs:mmcsd0s2a\" # Interrupt controller device gic # Cache controller device pl310 # PL310 L2 cache controller # ARM MPCore timer device mpcore_timer device loop device ether device cgem # Zynq-7000 gig ethernet device device mii device e1000phy device rgephy # Zybo uses Realtek RTL8211E device pty device uart device gpio +device spibus +device mx25l +device zy7_qspi # Xilinx Zynq QSPI controller + device md device mmc # mmc/sd bus device mmcsd # mmc/sd flash cards device sdhci # generic sdhci device bpf # Berkeley packet filter # USB support device usb device ehci device umass device scbus # SCSI bus (required for ATA/SCSI) device da # Direct Access (disks) device axe # USB-Ethernet # Flattened Device Tree options FDT # Configure using FDT/DTB data #options FDT_DTB_STATIC #makeoptions FDT_DTS_FILE=zedboard.dts Index: head/sys/arm/xilinx/files.zynq7 =================================================================== --- head/sys/arm/xilinx/files.zynq7 (revision 356894) +++ head/sys/arm/xilinx/files.zynq7 (revision 356895) @@ -1,16 +1,17 @@ # # files.zynq7 # # $FreeBSD$ arm/xilinx/zy7_machdep.c standard arm/xilinx/zy7_l2cache.c standard arm/xilinx/zy7_slcr.c standard arm/xilinx/zy7_devcfg.c standard arm/xilinx/zy7_mp.c optional smp dev/cadence/if_cgem.c optional cgem arm/xilinx/zy7_ehci.c optional ehci arm/xilinx/uart_dev_cdnc.c optional uart arm/xilinx/zy7_gpio.c optional gpio +arm/xilinx/zy7_qspi.c optional zy7_qspi Index: head/sys/arm/xilinx/zy7_qspi.c =================================================================== --- head/sys/arm/xilinx/zy7_qspi.c (nonexistent) +++ head/sys/arm/xilinx/zy7_qspi.c (revision 356895) @@ -0,0 +1,763 @@ +/*- + * SPDX-License-Identifier: BSD-2-Clause-FreeBSD + * + * Copyright (c) 2018 Thomas Skibo + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + +#include +__FBSDID("$FreeBSD$"); + +/* + * This is a driver for the Quad-SPI Flash Controller in the Xilinx + * Zynq-7000 SoC. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include + +#include +#include +#include + +#include +#include + +#include + +#include "spibus_if.h" + +static struct ofw_compat_data compat_data[] = { + {"xlnx,zy7_qspi", 1}, + {"xlnx,zynq-qspi-1.0", 1}, + {NULL, 0} +}; + +struct zy7_qspi_softc { + device_t dev; + device_t child; + struct mtx sc_mtx; + struct resource *mem_res; + struct resource *irq_res; + void *intrhandle; + + uint32_t cfg_reg_shadow; + uint32_t lqspi_cfg_shadow; + uint32_t spi_clock; + uint32_t ref_clock; + unsigned int spi_clk_real_freq; + unsigned int rx_overflows; + unsigned int tx_underflows; + unsigned int interrupts; + unsigned int stray_ints; + struct spi_command *cmd; + int tx_bytes; /* tx_cmd_sz + tx_data_sz */ + int tx_bytes_sent; + int rx_bytes; /* rx_cmd_sz + rx_data_sz */ + int rx_bytes_rcvd; + int busy; + int is_dual; + int is_stacked; + int is_dio; +}; + +#define ZY7_QSPI_DEFAULT_SPI_CLOCK 50000000 + +#define QSPI_SC_LOCK(sc) mtx_lock(&(sc)->sc_mtx) +#define QSPI_SC_UNLOCK(sc) mtx_unlock(&(sc)->sc_mtx) +#define QSPI_SC_LOCK_INIT(sc) \ + mtx_init(&(sc)->sc_mtx, device_get_nameunit((sc)->dev), NULL, MTX_DEF) +#define QSPI_SC_LOCK_DESTROY(sc) mtx_destroy(&(sc)->sc_mtx) +#define QSPI_SC_ASSERT_LOCKED(sc) mtx_assert(&(sc)->sc_mtx, MA_OWNED) + +#define RD4(sc, off) (bus_read_4((sc)->mem_res, (off))) +#define WR4(sc, off, val) (bus_write_4((sc)->mem_res, (off), (val))) + +/* + * QSPI device registers. + * Reference: Zynq-7000 All Programmable SoC Technical Reference Manual. + * (v1.12.2) July 1, 2018. Xilinx doc UG585. + */ +#define ZY7_QSPI_CONFIG_REG 0x0000 +#define ZY7_QSPI_CONFIG_IFMODE (1U << 31) +#define ZY7_QSPI_CONFIG_ENDIAN (1 << 26) +#define ZY7_QSPI_CONFIG_HOLDB_DR (1 << 19) +#define ZY7_QSPI_CONFIG_RSVD1 (1 << 17) /* must be 1 */ +#define ZY7_QSPI_CONFIG_MANSTRT (1 << 16) +#define ZY7_QSPI_CONFIG_MANSTRTEN (1 << 15) +#define ZY7_QSPI_CONFIG_SSFORCE (1 << 14) +#define ZY7_QSPI_CONFIG_PCS (1 << 10) +#define ZY7_QSPI_CONFIG_REF_CLK (1 << 8) +#define ZY7_QSPI_CONFIG_FIFO_WIDTH_MASK (3 << 6) +#define ZY7_QSPI_CONFIG_FIFO_WIDTH32 (3 << 6) +#define ZY7_QSPI_CONFIG_BAUD_RATE_DIV_MASK (7 << 3) +#define ZY7_QSPI_CONFIG_BAUD_RATE_DIV_SHIFT 3 +#define ZY7_QSPI_CONFIG_BAUD_RATE_DIV(x) ((x) << 3) /* divide by 2< 0) { + nvalid = MIN(4, nbytes); + data = 0xffffffff; + + /* + * A hardware bug forces us to wait until the tx fifo is + * empty before writing partial words. We'll come back + * next tx interrupt. + */ + if (nvalid < 4 && (RD4(sc, ZY7_QSPI_INTR_STAT_REG) & + ZY7_QSPI_INTR_TX_FIFO_NOT_FULL) == 0) + return; + + if (sc->tx_bytes_sent < sc->cmd->tx_cmd_sz) { + /* Writing command. */ + n = MIN(nvalid, sc->cmd->tx_cmd_sz - + sc->tx_bytes_sent); + memcpy(&data, (uint8_t *)sc->cmd->tx_cmd + + sc->tx_bytes_sent, n); + + if (nvalid > n) { + /* Writing start of data. */ + memcpy((uint8_t *)&data + n, + sc->cmd->tx_data, nvalid - n); + } + } else + /* Writing data. */ + memcpy(&data, (uint8_t *)sc->cmd->tx_data + + (sc->tx_bytes_sent - sc->cmd->tx_cmd_sz), nvalid); + + switch (nvalid) { + case 1: + WR4(sc, ZY7_QSPI_TXD1_REG, data); + break; + case 2: + WR4(sc, ZY7_QSPI_TXD2_REG, data); + break; + case 3: + WR4(sc, ZY7_QSPI_TXD3_REG, data); + break; + case 4: + WR4(sc, ZY7_QSPI_TXD0_REG, data); + break; + } + + sc->tx_bytes_sent += nvalid; + nbytes -= nvalid; + } +} + + +/* Read hardware fifo data into command response and data buffers. */ +static void +zy7_qspi_read_fifo(struct zy7_qspi_softc *sc) +{ + int n, nbytes; + uint32_t data; + + do { + data = RD4(sc, ZY7_QSPI_RX_DATA_REG); + nbytes = MIN(4, sc->rx_bytes - sc->rx_bytes_rcvd); + + /* + * Last word in non-word-multiple transfer is packed + * non-intuitively. + */ + if (nbytes < 4) + data >>= 8 * (4 - nbytes); + + if (sc->rx_bytes_rcvd < sc->cmd->rx_cmd_sz) { + /* Reading command. */ + n = MIN(nbytes, sc->cmd->rx_cmd_sz - + sc->rx_bytes_rcvd); + memcpy((uint8_t *)sc->cmd->rx_cmd + sc->rx_bytes_rcvd, + &data, n); + sc->rx_bytes_rcvd += n; + nbytes -= n; + data >>= 8 * n; + } + + if (nbytes > 0) { + /* Reading data. */ + memcpy((uint8_t *)sc->cmd->rx_data + + (sc->rx_bytes_rcvd - sc->cmd->rx_cmd_sz), + &data, nbytes); + sc->rx_bytes_rcvd += nbytes; + } + + } while (sc->rx_bytes_rcvd < sc->rx_bytes && + (RD4(sc, ZY7_QSPI_INTR_STAT_REG) & + ZY7_QSPI_INTR_RX_FIFO_NOT_EMPTY) != 0); +} + +/* End a transfer early by draining rx fifo and disabling interrupts. */ +static void +zy7_qspi_abort_transfer(struct zy7_qspi_softc *sc) +{ + /* Drain receive fifo. */ + while ((RD4(sc, ZY7_QSPI_INTR_STAT_REG) & + ZY7_QSPI_INTR_RX_FIFO_NOT_EMPTY) != 0) + (void)RD4(sc, ZY7_QSPI_RX_DATA_REG); + + /* Shut down interrupts. */ + WR4(sc, ZY7_QSPI_INTR_DIS_REG, + ZY7_QSPI_INTR_RX_OVERFLOW | + ZY7_QSPI_INTR_RX_FIFO_NOT_EMPTY | + ZY7_QSPI_INTR_TX_FIFO_NOT_FULL); +} + + +static void +zy7_qspi_intr(void *arg) +{ + struct zy7_qspi_softc *sc = (struct zy7_qspi_softc *)arg; + uint32_t istatus; + + QSPI_SC_LOCK(sc); + + sc->interrupts++; + + istatus = RD4(sc, ZY7_QSPI_INTR_STAT_REG); + + /* Stray interrupts can happen if a transfer gets interrupted. */ + if (!sc->busy) { + sc->stray_ints++; + QSPI_SC_UNLOCK(sc); + return; + } + + if ((istatus & ZY7_QSPI_INTR_RX_OVERFLOW) != 0) { + device_printf(sc->dev, "rx fifo overflow!\n"); + sc->rx_overflows++; + + /* Clear status bit. */ + WR4(sc, ZY7_QSPI_INTR_STAT_REG, + ZY7_QSPI_INTR_RX_OVERFLOW); + } + + /* Empty receive fifo before any more transmit data is sent. */ + if (sc->rx_bytes_rcvd < sc->rx_bytes && + (istatus & ZY7_QSPI_INTR_RX_FIFO_NOT_EMPTY) != 0) { + zy7_qspi_read_fifo(sc); + if (sc->rx_bytes_rcvd == sc->rx_bytes) + /* Disable receive interrupts. */ + WR4(sc, ZY7_QSPI_INTR_DIS_REG, + ZY7_QSPI_INTR_RX_FIFO_NOT_EMPTY | + ZY7_QSPI_INTR_RX_OVERFLOW); + } + + /* + * Transmit underflows aren't really a bug because a hardware + * bug forces us to allow the tx fifo to go empty between full + * and partial fifo writes. Why bother counting? + */ + if ((istatus & ZY7_QSPI_INTR_TX_FIFO_UNDERFLOW) != 0) { + sc->tx_underflows++; + + /* Clear status bit. */ + WR4(sc, ZY7_QSPI_INTR_STAT_REG, + ZY7_QSPI_INTR_TX_FIFO_UNDERFLOW); + } + + /* Fill transmit fifo. */ + if (sc->tx_bytes_sent < sc->tx_bytes && + (istatus & ZY7_QSPI_INTR_TX_FIFO_NOT_FULL) != 0) { + zy7_qspi_write_fifo(sc, MIN(240, sc->tx_bytes - + sc->tx_bytes_sent)); + + if (sc->tx_bytes_sent == sc->tx_bytes) { + /* + * Disable transmit FIFO interrupt, enable receive + * FIFO interrupt. + */ + WR4(sc, ZY7_QSPI_INTR_DIS_REG, + ZY7_QSPI_INTR_TX_FIFO_NOT_FULL); + WR4(sc, ZY7_QSPI_INTR_EN_REG, + ZY7_QSPI_INTR_RX_FIFO_NOT_EMPTY); + } + } + + /* Finished with transfer? */ + if (sc->tx_bytes_sent == sc->tx_bytes && + sc->rx_bytes_rcvd == sc->rx_bytes) { + + /* De-assert CS. */ + sc->cfg_reg_shadow |= ZY7_QSPI_CONFIG_PCS; + WR4(sc, ZY7_QSPI_CONFIG_REG, sc->cfg_reg_shadow); + + wakeup(sc->dev); + } + + QSPI_SC_UNLOCK(sc); +} + +/* Initialize hardware. */ +static int +zy7_qspi_init_hw(struct zy7_qspi_softc *sc) +{ + uint32_t baud_div; + + /* Configure LQSPI Config register. Disable linear mode. */ + sc->lqspi_cfg_shadow = RD4(sc, ZY7_QSPI_LQSPI_CFG_REG); + sc->lqspi_cfg_shadow &= ~(ZY7_QSPI_LQSPI_CFG_LINEAR | + ZY7_QSPI_LQSPI_CFG_TWO_MEM | + ZY7_QSPI_LQSPI_CFG_SEP_BUS); + if (sc->is_dual) { + sc->lqspi_cfg_shadow |= ZY7_QSPI_LQSPI_CFG_TWO_MEM; + if (sc->is_stacked) { + sc->lqspi_cfg_shadow &= + ~ZY7_QSPI_LQSPI_CFG_INST_CODE_MASK; + sc->lqspi_cfg_shadow |= + ZY7_QSPI_LQSPI_CFG_INST_CODE(sc->is_dio ? + CMD_READ_DUAL_IO : CMD_READ_QUAD_OUTPUT); + } else + sc->lqspi_cfg_shadow |= ZY7_QSPI_LQSPI_CFG_SEP_BUS; + } + WR4(sc, ZY7_QSPI_LQSPI_CFG_REG, sc->lqspi_cfg_shadow); + + /* Find best clock divider. */ + baud_div = 0; + while ((sc->ref_clock >> (baud_div + 1)) > sc->spi_clock && + baud_div < 8) + baud_div++; + if (baud_div >= 8) { + device_printf(sc->dev, "cannot configure clock divider: ref=%d" + " spi=%d.\n", sc->ref_clock, sc->spi_clock); + return (EINVAL); + } + sc->spi_clk_real_freq = sc->ref_clock >> (baud_div + 1); + + /* + * If divider is 2 (the max speed), use internal loopback master + * clock for read data. (See section 12.3.1 in ref man.) + */ + if (baud_div == 0) + WR4(sc, ZY7_QSPI_LPBK_DLY_ADJ_REG, + ZY7_QSPI_LPBK_DLY_ADJ_USE_LPBK | + ZY7_QSPI_LPBK_DLY_ADJ_DLY1(0) | + ZY7_QSPI_LPBK_DLY_ADJ_DLY0(0)); + else + WR4(sc, ZY7_QSPI_LPBK_DLY_ADJ_REG, 0); + + /* Set up configuration register. */ + sc->cfg_reg_shadow = + ZY7_QSPI_CONFIG_IFMODE | + ZY7_QSPI_CONFIG_HOLDB_DR | + ZY7_QSPI_CONFIG_RSVD1 | + ZY7_QSPI_CONFIG_SSFORCE | + ZY7_QSPI_CONFIG_PCS | + ZY7_QSPI_CONFIG_FIFO_WIDTH32 | + ZY7_QSPI_CONFIG_BAUD_RATE_DIV(baud_div) | + ZY7_QSPI_CONFIG_MODE_SEL; + WR4(sc, ZY7_QSPI_CONFIG_REG, sc->cfg_reg_shadow); + + /* + * Set thresholds. We must use 1 for tx threshold because there + * is no fifo empty flag and we need one to implement a bug + * workaround. + */ + WR4(sc, ZY7_QSPI_TX_THRESH_REG, 1); + WR4(sc, ZY7_QSPI_RX_THRESH_REG, 1); + + /* Clear and disable all interrupts. */ + WR4(sc, ZY7_QSPI_INTR_STAT_REG, ~0); + WR4(sc, ZY7_QSPI_INTR_DIS_REG, ~0); + + /* Enable SPI. */ + WR4(sc, ZY7_QSPI_EN_REG, ZY7_SPI_ENABLE); + + return (0); +} + + +static void +zy7_qspi_add_sysctls(device_t dev) +{ + struct zy7_qspi_softc *sc = device_get_softc(dev); + struct sysctl_ctx_list *ctx; + struct sysctl_oid_list *child; + + ctx = device_get_sysctl_ctx(dev); + child = SYSCTL_CHILDREN(device_get_sysctl_tree(dev)); + + SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "spi_clk_real_freq", CTLFLAG_RD, + &sc->spi_clk_real_freq, 0, "SPI clock real frequency"); + + SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "rx_overflows", CTLFLAG_RD, + &sc->rx_overflows, 0, "RX FIFO overflow events"); + + SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "tx_underflows", CTLFLAG_RD, + &sc->tx_underflows, 0, "TX FIFO underflow events"); + + SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "interrupts", CTLFLAG_RD, + &sc->interrupts, 0, "interrupt calls"); + + SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "stray_ints", CTLFLAG_RD, + &sc->stray_ints, 0, "stray interrupts"); +} + + +static int +zy7_qspi_probe(device_t dev) +{ + + if (!ofw_bus_status_okay(dev)) + return (ENXIO); + + if (ofw_bus_search_compatible(dev, compat_data)->ocd_data == 0) + return (ENXIO); + + device_set_desc(dev, "Zynq Quad-SPI Flash Controller"); + + return (BUS_PROBE_DEFAULT); +} + + +static int +zy7_qspi_attach(device_t dev) +{ + struct zy7_qspi_softc *sc; + int rid, err; + phandle_t node; + pcell_t cell; + + sc = device_get_softc(dev); + sc->dev = dev; + + QSPI_SC_LOCK_INIT(sc); + + /* Get ref-clock, spi-clock, and other properties. */ + node = ofw_bus_get_node(dev); + if (OF_getprop(node, "ref-clock", &cell, sizeof(cell)) > 0) + sc->ref_clock = fdt32_to_cpu(cell); + else { + device_printf(dev, "must have ref-clock property\n"); + return (ENXIO); + } + if (OF_getprop(node, "spi-clock", &cell, sizeof(cell)) > 0) + sc->spi_clock = fdt32_to_cpu(cell); + else + sc->spi_clock = ZY7_QSPI_DEFAULT_SPI_CLOCK; + if (OF_getprop(node, "is-stacked", &cell, sizeof(cell)) > 0 && + fdt32_to_cpu(cell) != 0) { + sc->is_dual = 1; + sc->is_stacked = 1; + } else if (OF_getprop(node, "is-dual", &cell, sizeof(cell)) > 0 && + fdt32_to_cpu(cell) != 0) + sc->is_dual = 1; + if (OF_getprop(node, "is-dio", &cell, sizeof(cell)) > 0 && + fdt32_to_cpu(cell) != 0) + sc->is_dio = 1; + + /* Get memory resource. */ + rid = 0; + sc->mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, + RF_ACTIVE); + if (sc->mem_res == NULL) { + device_printf(dev, "could not allocate memory resources.\n"); + zy7_qspi_detach(dev); + return (ENOMEM); + } + + /* Allocate IRQ. */ + rid = 0; + sc->irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, + RF_ACTIVE); + if (sc->irq_res == NULL) { + device_printf(dev, "could not allocate IRQ resource.\n"); + zy7_qspi_detach(dev); + return (ENOMEM); + } + + /* Activate the interrupt. */ + err = bus_setup_intr(dev, sc->irq_res, INTR_TYPE_MISC | INTR_MPSAFE, + NULL, zy7_qspi_intr, sc, &sc->intrhandle); + if (err) { + device_printf(dev, "could not setup IRQ.\n"); + zy7_qspi_detach(dev); + return (err); + } + + /* Configure the device. */ + err = zy7_qspi_init_hw(sc); + if (err) { + zy7_qspi_detach(dev); + return (err); + } + + sc->child = device_add_child(dev, "spibus", -1); + + zy7_qspi_add_sysctls(dev); + + /* Attach spibus driver as a child later when interrupts work. */ + config_intrhook_oneshot((ich_func_t)bus_generic_attach, dev); + + return (0); +} + +static int +zy7_qspi_detach(device_t dev) +{ + struct zy7_qspi_softc *sc = device_get_softc(dev); + + if (device_is_attached(dev)) + bus_generic_detach(dev); + + /* Delete child bus. */ + if (sc->child) + device_delete_child(dev, sc->child); + + /* Disable hardware. */ + if (sc->mem_res != NULL) { + /* Disable SPI. */ + WR4(sc, ZY7_QSPI_EN_REG, 0); + + /* Clear and disable all interrupts. */ + WR4(sc, ZY7_QSPI_INTR_STAT_REG, ~0); + WR4(sc, ZY7_QSPI_INTR_DIS_REG, ~0); + } + + /* Teardown and release interrupt. */ + if (sc->irq_res != NULL) { + if (sc->intrhandle) + bus_teardown_intr(dev, sc->irq_res, sc->intrhandle); + bus_release_resource(dev, SYS_RES_IRQ, + rman_get_rid(sc->irq_res), sc->irq_res); + } + + /* Release memory resource. */ + if (sc->mem_res != NULL) + bus_release_resource(dev, SYS_RES_MEMORY, + rman_get_rid(sc->mem_res), sc->mem_res); + + QSPI_SC_LOCK_DESTROY(sc); + + return (0); +} + + +static phandle_t +zy7_qspi_get_node(device_t bus, device_t dev) +{ + + return (ofw_bus_get_node(bus)); +} + + +static int +zy7_qspi_transfer(device_t dev, device_t child, struct spi_command *cmd) +{ + struct zy7_qspi_softc *sc = device_get_softc(dev); + int err = 0; + + KASSERT(cmd->tx_cmd_sz == cmd->rx_cmd_sz, + ("TX/RX command sizes should be equal")); + KASSERT(cmd->tx_data_sz == cmd->rx_data_sz, + ("TX/RX data sizes should be equal")); + + if (sc->is_dual && cmd->tx_data_sz % 2 != 0) { + device_printf(dev, "driver does not support odd byte data " + "transfers in dual mode. (sz=%d)\n", cmd->tx_data_sz); + return (EINVAL); + } + + QSPI_SC_LOCK(sc); + + /* Wait for controller available. */ + while (sc->busy != 0) { + err = mtx_sleep(dev, &sc->sc_mtx, 0, "zqspi0", 0); + if (err) { + QSPI_SC_UNLOCK(sc); + return (err); + } + } + + /* Start transfer. */ + sc->busy = 1; + sc->cmd = cmd; + sc->tx_bytes = sc->cmd->tx_cmd_sz + sc->cmd->tx_data_sz; + sc->tx_bytes_sent = 0; + sc->rx_bytes = sc->cmd->rx_cmd_sz + sc->cmd->rx_data_sz; + sc->rx_bytes_rcvd = 0; + + /* Enable interrupts. zy7_qspi_intr() will handle transfer. */ + WR4(sc, ZY7_QSPI_INTR_EN_REG, + ZY7_QSPI_INTR_TX_FIFO_NOT_FULL | + ZY7_QSPI_INTR_RX_OVERFLOW); + +#ifdef SPI_XFER_U_PAGE /* XXX: future support for stacked memories. */ + if (sc->is_stacked) { + if ((cmd->flags & SPI_XFER_U_PAGE) != 0) + sc->lqspi_cfg_shadow |= ZY7_QSPI_LQSPI_CFG_U_PAGE; + else + sc->lqspi_cfg_shadow &= ~ZY7_QSPI_LQSPI_CFG_U_PAGE; + WR4(sc, ZY7_QSPI_LQSPI_CFG_REG, sc->lqspi_cfg_shadow); + } +#endif + + /* Assert CS. */ + sc->cfg_reg_shadow &= ~ZY7_QSPI_CONFIG_PCS; + WR4(sc, ZY7_QSPI_CONFIG_REG, sc->cfg_reg_shadow); + + /* Wait for completion. */ + err = mtx_sleep(dev, &sc->sc_mtx, 0, "zqspi1", hz * 2); + if (err) + zy7_qspi_abort_transfer(sc); + + /* Release controller. */ + sc->busy = 0; + wakeup_one(dev); + + QSPI_SC_UNLOCK(sc); + + return (err); +} + +static device_method_t zy7_qspi_methods[] = { + /* Device interface */ + DEVMETHOD(device_probe, zy7_qspi_probe), + DEVMETHOD(device_attach, zy7_qspi_attach), + DEVMETHOD(device_detach, zy7_qspi_detach), + + /* SPI interface */ + DEVMETHOD(spibus_transfer, zy7_qspi_transfer), + + /* ofw_bus interface */ + DEVMETHOD(ofw_bus_get_node, zy7_qspi_get_node), + + DEVMETHOD_END +}; + + +static driver_t zy7_qspi_driver = { + "zy7_qspi", + zy7_qspi_methods, + sizeof(struct zy7_qspi_softc), +}; +static devclass_t zy7_qspi_devclass; + +DRIVER_MODULE(zy7_qspi, simplebus, zy7_qspi_driver, zy7_qspi_devclass, 0, 0); +DRIVER_MODULE(ofw_spibus, zy7_qspi, ofw_spibus_driver, ofw_spibus_devclass, 0, 0); +SIMPLEBUS_PNP_INFO(compat_data); +MODULE_DEPEND(zy7_qspi, ofw_spibus, 1, 1, 1); Property changes on: head/sys/arm/xilinx/zy7_qspi.c ___________________________________________________________________ Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:keywords ## -0,0 +1 ## +FreeBSD=%H \ No newline at end of property Added: svn:mime-type ## -0,0 +1 ## +text/plain \ No newline at end of property Index: head/sys/dev/flash/mx25lreg.h =================================================================== --- head/sys/dev/flash/mx25lreg.h (revision 356894) +++ head/sys/dev/flash/mx25lreg.h (revision 356895) @@ -1,71 +1,73 @@ /*- * SPDX-License-Identifier: BSD-2-Clause-FreeBSD * * Copyright (c) 2009, Oleksandr Tymoshenko * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice unmodified, this list of conditions, and the following * disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. * * $FreeBSD$ */ #ifndef __MX25LREG_H__ #define __MX25LREG_H__ /* * Commands */ #define CMD_WRITE_ENABLE 0x06 #define CMD_WRITE_DISABLE 0x04 #define CMD_READ_IDENT 0x9F #define CMD_READ_STATUS 0x05 #define CMD_WRITE_STATUS 0x01 #define CMD_READ 0x03 #define CMD_FAST_READ 0x0B +#define CMD_READ_DUAL_IO 0xBB +#define CMD_READ_QUAD_OUTPUT 0x6B #define CMD_PAGE_PROGRAM 0x02 #define CMD_SECTOR_ERASE 0xD8 #define CMD_BULK_ERASE 0xC7 #define CMD_BLOCK_4K_ERASE 0x20 #define CMD_BLOCK_32K_ERASE 0x52 #define CMD_ENTER_4B_MODE 0xB7 #define CMD_EXIT_4B_MODE 0xE9 /* Quad 4B-addressing operations. */ #define CMD_QUAD_SECTOR_ERASE 0xDC #define CMD_QUAD_PAGE_PROGRAM 0x34 #define CMD_READ_4B_QUAD_OUTPUT 0x6C /* * Status register flags */ #define STATUS_SRWD (1 << 7) #define STATUS_BP2 (1 << 4) #define STATUS_BP1 (1 << 3) #define STATUS_BP0 (1 << 2) #define STATUS_WEL (1 << 1) #define STATUS_WIP (1 << 0) #define FLASH_PAGE_SIZE 256 #endif /* __MX25LREG_H__ */ Index: head/sys/dts/arm/zedboard.dts =================================================================== --- head/sys/dts/arm/zedboard.dts (revision 356894) +++ head/sys/dts/arm/zedboard.dts (revision 356895) @@ -1,71 +1,80 @@ /*- * Copyright (c) 2016 The FreeBSD Foundation * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. * * $FreeBSD$ */ /dts-v1/; /include/ "zynq-7000.dtsi" / { model = "zedboard"; compatible = "digilent,zedboard", "xlnx,zynq-7000"; memory { // First megabyte isn't accessible by all interconnect masters. device_type = "memory"; reg = <0x100000 0x1ff00000>; /* 511MB RAM at 0x100000 */ }; chosen { stdin = &uart1; stdout = &uart1; }; }; &slcr { clock-frequency = <33333333>; // 33Mhz PS_CLK }; &global_timer { clock-frequency = <333333333>; // 333Mhz }; &uart1 { status = "okay"; }; ð0 { status = "okay"; }; +&qspi0 { + status = "okay"; + + flash0 { + compatible = "st,m25p", "s25fl128"; + spi-chipselect = <0>; + }; +}; + &sdhci0 { status = "okay"; }; &ehci0 { status = "okay"; phy_vbus_ext; }; Index: head/sys/dts/arm/zybo.dts =================================================================== --- head/sys/dts/arm/zybo.dts (revision 356894) +++ head/sys/dts/arm/zybo.dts (revision 356895) @@ -1,69 +1,78 @@ /*- * Copyright (c) 2016 The FreeBSD Foundation * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. * * $FreeBSD$ */ /dts-v1/; /include/ "zynq-7000.dtsi" / { model = "zybo"; compatible = "digilent,zybo", "xlnx,zynq-7000"; memory { // First megabyte isn't accessible by all interconnect masters. device_type = "memory"; reg = <0x100000 0x1ff00000>; /* 511MB RAM at 0x100000 */ }; chosen { stdin = &uart1; stdout = &uart1; }; }; &slcr { clock-frequency = <50000000>; // 50Mhz PS_CLK }; &global_timer { clock-frequency = <325000000>; // 325Mhz }; &uart1 { status = "okay"; }; ð0 { status = "okay"; }; +&qspi0 { + status = "okay"; + + flash0 { + compatible = "st,m25p", "s25fl128"; + spi-chipselect = <0>; + }; +}; + &sdhci0 { status = "okay"; }; &ehci0 { status = "okay"; }; Index: head/sys/dts/arm/zynq-7000.dtsi =================================================================== --- head/sys/dts/arm/zynq-7000.dtsi (revision 356894) +++ head/sys/dts/arm/zynq-7000.dtsi (revision 356895) @@ -1,229 +1,230 @@ /*- * Copyright (c) 2016 The FreeBSD Foundation * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. * * $FreeBSD$ */ / { compatible = "xlnx,zynq-7000"; #address-cells = <1>; #size-cells = <1>; interrupt-parent = <&GIC>; // Reserve first half megabyte because it is not accessible to all // bus masters. memreserve = <0x00000000 0x00080000>; // Zynq PS System registers. // ps7sys@f8000000 { device_type = "soc"; compatible = "simple-bus"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0xf8000000 0xf10000>; // SLCR block slcr: slcr@7000 { compatible = "xlnx,zy7_slcr"; reg = <0x0 0x1000>; }; // Interrupt controller GIC: gic { compatible = "arm,gic"; interrupt-controller; #address-cells = <0>; #interrupt-cells = <3>; reg = <0xf01000 0x1000>, // distributer registers <0xf00100 0x0100>; // CPU if registers }; // L2 cache controller pl310@f02000 { compatible = "arm,pl310"; reg = <0xf02000 0x1000>; interrupts = <0 2 4>; interrupt-parent = <&GIC>; }; // Device Config devcfg: devcfg@7000 { compatible = "xlnx,zy7_devcfg"; reg = <0x7000 0x1000>; interrupts = <0 8 4>; interrupt-parent = <&GIC>; }; // triple timer counters0,1 ttc0: ttc@1000 { compatible = "xlnx,ttc"; reg = <0x1000 0x1000>; }; ttc1: ttc@2000 { compatible = "xlnx,ttc"; reg = <0x2000 0x1000>; }; // ARM Cortex A9 TWD Timer global_timer: timer@f00600 { compatible = "arm,mpcore-timers"; #address-cells = <1>; #size-cells = <0>; reg = <0xf00200 0x100>, // Global Timer Regs <0xf00600 0x20>; // Private Timer Regs interrupts = <1 11 1>, <1 13 1>; interrupt-parent = <&GIC>; }; // system watch-dog timer swdt@5000 { device_type = "watchdog"; compatible = "xlnx,zy7_wdt"; reg = <0x5000 0x1000>; interrupts = <0 9 1>; interrupt-parent = <&GIC>; }; scuwdt@f00620 { device_type = "watchdog"; compatible = "arm,mpcore_wdt"; reg = <0xf00620 0x20>; interrupts = <1 14 1>; interrupt-parent = <&GIC>; reset = <1>; }; }; // pssys@f8000000 // Zynq PS I/O Peripheral registers. // ps7io@e0000000 { device_type = "soc"; compatible = "simple-bus"; #address-cells = <1>; #size-cells = <1>; ranges = <0x0 0xe0000000 0x300000>; // UART controllers uart0: uart@0000 { device_type = "serial"; compatible = "cadence,uart"; status = "disabled"; reg = <0x0000 0x1000>; interrupts = <0 27 4>; interrupt-parent = <&GIC>; clock-frequency = <50000000>; }; uart1: uart@1000 { device_type = "serial"; compatible = "cadence,uart"; status = "disabled"; reg = <0x1000 0x1000>; interrupts = <0 50 4>; interrupt-parent = <&GIC>; clock-frequency = <50000000>; }; // USB controllers ehci0: ehci@2000 { compatible = "xlnx,zy7_ehci"; status = "disabled"; reg = <0x2000 0x1000>; interrupts = <0 21 4>; interrupt-parent = <&GIC>; }; ehci1: ehci@3000 { compatible = "xlnx,zy7_ehci"; status = "disabled"; reg = <0x3000 0x1000>; interrupts = <0 44 4>; interrupt-parent = <&GIC>; }; // GPIO controller gpio: gpio@a000 { compatible = "xlnx,zy7_gpio"; reg = <0xa000 0x1000>; interrupts = <0 20 4>; interrupt-parent = <&GIC>; }; // Gigabit Ethernet controllers eth0: eth@b000 { device_type = "network"; compatible = "cadence,gem"; status = "disabled"; reg = <0xb000 0x1000>; interrupts = <0 22 4>; interrupt-parent = <&GIC>; ref-clock-num = <0>; }; eth1: eth@c000 { device_type = "network"; compatible = "cadence,gem"; status = "disabled"; reg = <0xc000 0x1000>; interrupts = <0 45 4>; interrupt-parent = <&GIC>; ref-clock-num = <1>; }; // Quad-SPI controller qspi0: qspi@d000 { compatible = "xlnx,zy7_qspi"; status = "disabled"; reg = <0xd000 0x1000>; interrupts = <0 19 4>; interrupt-parent = <&GIC>; - spi-clock = <50000000>; + ref-clock = <200000000>; // 200 Mhz + spi-clock = <50000000>; // 50 Mhz }; // SDIO controllers sdhci0: sdhci@100000 { compatible = "xlnx,zy7_sdhci"; status = "disabled"; reg = <0x100000 0x1000>; interrupts = <0 24 4>; interrupt-parent = <&GIC>; max-frequency = <50000000>; }; sdhci1: sdhci@101000 { compatible = "xlnx,zy7_sdhci"; status = "disabled"; reg = <0x101000 0x1000>; interrupts = <0 47 4>; interrupt-parent = <&GIC>; max-frequency = <50000000>; }; }; // ps7io@e0000000 };