Index: head/sys/dev/exca/exca.c =================================================================== --- head/sys/dev/exca/exca.c (revision 355823) +++ head/sys/dev/exca/exca.c (revision 355824) @@ -1,929 +1,936 @@ /*- * SPDX-License-Identifier: BSD-4-Clause AND BSD-2-Clause-FreeBSD * * Copyright (c) 2002-2005 M. Warner Losh * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * * This software may be derived from NetBSD i82365.c and other files with * the following copyright: * * Copyright (c) 1997 Marc Horowitz. All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * 3. All advertising materials mentioning features or use of this software * must display the following acknowledgement: * This product includes software developed by Marc Horowitz. * 4. The name of the author may not be used to endorse or promote products * derived from this software without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ #include __FBSDID("$FreeBSD$"); #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #ifdef EXCA_DEBUG #define DEVPRINTF(dev, fmt, args...) device_printf((dev), (fmt), ## args) #define DPRINTF(fmt, args...) printf(fmt, ## args) #else #define DEVPRINTF(dev, fmt, args...) #define DPRINTF(fmt, args...) #endif static const char *chip_names[] = { "CardBus socket", "Intel i82365SL-A/B or clone", "Intel i82365sl-DF step", "VLSI chip", "Cirrus Logic PD6710", "Cirrus logic PD6722", "Cirrus Logic PD6729", "Vadem 365", "Vadem 465", "Vadem 468", "Vadem 469", "Ricoh RF5C296", "Ricoh RF5C396", "IBM clone", "IBM KING PCMCIA Controller" }; static exca_getb_fn exca_mem_getb; static exca_putb_fn exca_mem_putb; static exca_getb_fn exca_io_getb; static exca_putb_fn exca_io_putb; /* memory */ #define EXCA_MEMINFO(NUM) { \ EXCA_SYSMEM_ADDR ## NUM ## _START_LSB, \ EXCA_SYSMEM_ADDR ## NUM ## _START_MSB, \ EXCA_SYSMEM_ADDR ## NUM ## _STOP_LSB, \ EXCA_SYSMEM_ADDR ## NUM ## _STOP_MSB, \ EXCA_SYSMEM_ADDR ## NUM ## _WIN, \ EXCA_CARDMEM_ADDR ## NUM ## _LSB, \ EXCA_CARDMEM_ADDR ## NUM ## _MSB, \ EXCA_ADDRWIN_ENABLE_MEM ## NUM, \ } static struct mem_map_index_st { int sysmem_start_lsb; int sysmem_start_msb; int sysmem_stop_lsb; int sysmem_stop_msb; int sysmem_win; int cardmem_lsb; int cardmem_msb; int memenable; } mem_map_index[] = { EXCA_MEMINFO(0), EXCA_MEMINFO(1), EXCA_MEMINFO(2), EXCA_MEMINFO(3), EXCA_MEMINFO(4) }; #undef EXCA_MEMINFO static uint8_t exca_mem_getb(struct exca_softc *sc, int reg) { return (bus_space_read_1(sc->bst, sc->bsh, sc->offset + reg)); } static void exca_mem_putb(struct exca_softc *sc, int reg, uint8_t val) { bus_space_write_1(sc->bst, sc->bsh, sc->offset + reg, val); } static uint8_t exca_io_getb(struct exca_softc *sc, int reg) { bus_space_write_1(sc->bst, sc->bsh, EXCA_REG_INDEX, reg + sc->offset); return (bus_space_read_1(sc->bst, sc->bsh, EXCA_REG_DATA)); } static void exca_io_putb(struct exca_softc *sc, int reg, uint8_t val) { bus_space_write_1(sc->bst, sc->bsh, EXCA_REG_INDEX, reg + sc->offset); bus_space_write_1(sc->bst, sc->bsh, EXCA_REG_DATA, val); } /* * Helper function. This will map the requested memory slot. We setup the * map before we call this function. This is used to initially force the * mapping, as well as later restore the mapping after it has been destroyed * in some fashion (due to a power event typically). */ static void exca_do_mem_map(struct exca_softc *sc, int win) { struct mem_map_index_st *map; struct pccard_mem_handle *mem; uint32_t offset; uint32_t mem16; uint32_t attrmem; map = &mem_map_index[win]; mem = &sc->mem[win]; mem16 = (mem->kind & PCCARD_MEM_16BIT) ? EXCA_SYSMEM_ADDRX_START_MSB_DATASIZE_16BIT : 0; attrmem = (mem->kind & PCCARD_MEM_ATTR) ? EXCA_CARDMEM_ADDRX_MSB_REGACTIVE_ATTR : 0; offset = ((mem->cardaddr >> EXCA_CARDMEM_ADDRX_SHIFT) - (mem->addr >> EXCA_SYSMEM_ADDRX_SHIFT)) & 0x3fff; exca_putb(sc, map->sysmem_start_lsb, mem->addr >> EXCA_SYSMEM_ADDRX_SHIFT); exca_putb(sc, map->sysmem_start_msb, ((mem->addr >> (EXCA_SYSMEM_ADDRX_SHIFT + 8)) & EXCA_SYSMEM_ADDRX_START_MSB_ADDR_MASK) | mem16); exca_putb(sc, map->sysmem_stop_lsb, (mem->addr + mem->realsize - 1) >> EXCA_SYSMEM_ADDRX_SHIFT); exca_putb(sc, map->sysmem_stop_msb, (((mem->addr + mem->realsize - 1) >> (EXCA_SYSMEM_ADDRX_SHIFT + 8)) & EXCA_SYSMEM_ADDRX_STOP_MSB_ADDR_MASK) | EXCA_SYSMEM_ADDRX_STOP_MSB_WAIT2); exca_putb(sc, map->sysmem_win, mem->addr >> EXCA_MEMREG_WIN_SHIFT); exca_putb(sc, map->cardmem_lsb, offset & 0xff); exca_putb(sc, map->cardmem_msb, ((offset >> 8) & EXCA_CARDMEM_ADDRX_MSB_ADDR_MASK) | attrmem); DPRINTF("%s %d-bit memory", mem->kind & PCCARD_MEM_ATTR ? "attribute" : "common", mem->kind & PCCARD_MEM_16BIT ? 16 : 8); exca_setb(sc, EXCA_ADDRWIN_ENABLE, map->memenable | EXCA_ADDRWIN_ENABLE_MEMCS16); DELAY(100); #ifdef EXCA_DEBUG { int r1, r2, r3, r4, r5, r6, r7; r1 = exca_getb(sc, map->sysmem_start_msb); r2 = exca_getb(sc, map->sysmem_start_lsb); r3 = exca_getb(sc, map->sysmem_stop_msb); r4 = exca_getb(sc, map->sysmem_stop_lsb); r5 = exca_getb(sc, map->cardmem_msb); r6 = exca_getb(sc, map->cardmem_lsb); r7 = exca_getb(sc, map->sysmem_win); printf("exca_do_mem_map win %d: %#02x%#02x %#02x%#02x " "%#02x%#02x %#02x (%#08x+%#06x.%#06x*%#06x) flags %#x\n", win, r1, r2, r3, r4, r5, r6, r7, mem->addr, mem->size, mem->realsize, mem->cardaddr, mem->kind); } #endif } /* * public interface to map a resource. kind is the type of memory to * map (either common or attribute). Memory created via this interface * starts out at card address 0. Since the only way to set this is * to set it on a struct resource after it has been mapped, we're safe * in maping this assumption. Note that resources can be remapped using * exca_do_mem_map so that's how the card address can be set later. */ int exca_mem_map(struct exca_softc *sc, int kind, struct resource *res) { int win; for (win = 0; win < EXCA_MEM_WINS; win++) { if ((sc->memalloc & (1 << win)) == 0) { sc->memalloc |= (1 << win); break; } } if (win >= EXCA_MEM_WINS) return (ENOSPC); if (sc->flags & EXCA_HAS_MEMREG_WIN) { #ifdef __LP64__ if (rman_get_start(res) >> (EXCA_MEMREG_WIN_SHIFT + 8) != 0) { device_printf(sc->dev, "Does not support mapping above 4GB."); return (EINVAL); } #endif } else { if (rman_get_start(res) >> EXCA_MEMREG_WIN_SHIFT != 0) { device_printf(sc->dev, "Does not support mapping above 16M."); return (EINVAL); } } sc->mem[win].cardaddr = 0; sc->mem[win].memt = rman_get_bustag(res); sc->mem[win].memh = rman_get_bushandle(res); sc->mem[win].addr = rman_get_start(res); sc->mem[win].size = rman_get_end(res) - sc->mem[win].addr + 1; sc->mem[win].realsize = sc->mem[win].size + EXCA_MEM_PAGESIZE - 1; sc->mem[win].realsize = sc->mem[win].realsize - (sc->mem[win].realsize % EXCA_MEM_PAGESIZE); sc->mem[win].kind = kind; DPRINTF("exca_mem_map window %d bus %x+%x card addr %x\n", win, sc->mem[win].addr, sc->mem[win].size, sc->mem[win].cardaddr); exca_do_mem_map(sc, win); return (0); } /* * Private helper function. This turns off a given memory map that is in * use. We do this by just clearing the enable bit in the pcic. If we needed * to make memory unmapping/mapping pairs faster, we would have to store * more state information about the pcic and then use that to intelligently * to the map/unmap. However, since we don't do that sort of thing often * (generally just at configure time), it isn't a case worth optimizing. */ static void exca_mem_unmap(struct exca_softc *sc, int window) { if (window < 0 || window >= EXCA_MEM_WINS) panic("exca_mem_unmap: window out of range"); exca_clrb(sc, EXCA_ADDRWIN_ENABLE, mem_map_index[window].memenable); sc->memalloc &= ~(1 << window); } /* * Find the map that we're using to hold the resource. This works well * so long as the client drivers don't do silly things like map the same * area mutliple times, or map both common and attribute memory at the * same time. This latter restriction is a bug. We likely should just * store a pointer to the res in the mem[x] data structure. */ static int exca_mem_findmap(struct exca_softc *sc, struct resource *res) { int win; for (win = 0; win < EXCA_MEM_WINS; win++) { if (sc->mem[win].memt == rman_get_bustag(res) && sc->mem[win].addr == rman_get_start(res) && sc->mem[win].size == rman_get_size(res)) return (win); } return (-1); } /* * Set the memory flag. This means that we are setting if the memory * is coming from attribute memory or from common memory on the card. * CIS entries are generally in attribute memory (although they can * reside in common memory). Generally, this is the only use for attribute * memory. However, some cards require their drivers to dance in both * common and/or attribute memory and this interface (and setting the * offset interface) exist for such cards. */ int exca_mem_set_flags(struct exca_softc *sc, struct resource *res, uint32_t flags) { int win; win = exca_mem_findmap(sc, res); if (win < 0) { device_printf(sc->dev, "set_res_flags: specified resource not active\n"); return (ENOENT); } switch (flags) { case PCCARD_A_MEM_ATTR: sc->mem[win].kind |= PCCARD_MEM_ATTR; break; case PCCARD_A_MEM_COM: sc->mem[win].kind &= ~PCCARD_MEM_ATTR; break; case PCCARD_A_MEM_16BIT: sc->mem[win].kind |= PCCARD_MEM_16BIT; break; case PCCARD_A_MEM_8BIT: sc->mem[win].kind &= ~PCCARD_MEM_16BIT; break; } exca_do_mem_map(sc, win); return (0); } /* * Given a resource, go ahead and unmap it if we can find it in the * resrouce list that's used. */ int exca_mem_unmap_res(struct exca_softc *sc, struct resource *res) { int win; win = exca_mem_findmap(sc, res); if (win < 0) return (ENOENT); exca_mem_unmap(sc, win); return (0); } /* * Set the offset of the memory. We use this for reading the CIS and * frobbing the pccard's pccard registers (CCR, etc). Some drivers * need to access arbitrary attribute and common memory during their * initialization and operation. */ int exca_mem_set_offset(struct exca_softc *sc, struct resource *res, uint32_t cardaddr, uint32_t *deltap) { int win; uint32_t delta; win = exca_mem_findmap(sc, res); if (win < 0) { device_printf(sc->dev, "set_memory_offset: specified resource not active\n"); return (ENOENT); } sc->mem[win].cardaddr = rounddown2(cardaddr, EXCA_MEM_PAGESIZE); delta = cardaddr % EXCA_MEM_PAGESIZE; if (deltap) *deltap = delta; sc->mem[win].realsize = sc->mem[win].size + delta + EXCA_MEM_PAGESIZE - 1; sc->mem[win].realsize = sc->mem[win].realsize - (sc->mem[win].realsize % EXCA_MEM_PAGESIZE); exca_do_mem_map(sc, win); return (0); } /* I/O */ #define EXCA_IOINFO(NUM) { \ EXCA_IOADDR ## NUM ## _START_LSB, \ EXCA_IOADDR ## NUM ## _START_MSB, \ EXCA_IOADDR ## NUM ## _STOP_LSB, \ EXCA_IOADDR ## NUM ## _STOP_MSB, \ EXCA_ADDRWIN_ENABLE_IO ## NUM, \ EXCA_IOCTL_IO ## NUM ## _WAITSTATE \ | EXCA_IOCTL_IO ## NUM ## _ZEROWAIT \ | EXCA_IOCTL_IO ## NUM ## _IOCS16SRC_MASK \ | EXCA_IOCTL_IO ## NUM ## _DATASIZE_MASK, \ { \ EXCA_IOCTL_IO ## NUM ## _IOCS16SRC_CARD, \ EXCA_IOCTL_IO ## NUM ## _IOCS16SRC_DATASIZE \ | EXCA_IOCTL_IO ## NUM ## _DATASIZE_8BIT, \ EXCA_IOCTL_IO ## NUM ## _IOCS16SRC_DATASIZE \ | EXCA_IOCTL_IO ## NUM ## _DATASIZE_16BIT, \ } \ } static struct io_map_index_st { int start_lsb; int start_msb; int stop_lsb; int stop_msb; int ioenable; int ioctlmask; int ioctlbits[3]; /* indexed by PCCARD_WIDTH_* */ } io_map_index[] = { EXCA_IOINFO(0), EXCA_IOINFO(1), }; #undef EXCA_IOINFO static void exca_do_io_map(struct exca_softc *sc, int win) { struct io_map_index_st *map; struct pccard_io_handle *io; map = &io_map_index[win]; io = &sc->io[win]; exca_putb(sc, map->start_lsb, io->addr & 0xff); exca_putb(sc, map->start_msb, (io->addr >> 8) & 0xff); exca_putb(sc, map->stop_lsb, (io->addr + io->size - 1) & 0xff); exca_putb(sc, map->stop_msb, ((io->addr + io->size - 1) >> 8) & 0xff); exca_clrb(sc, EXCA_IOCTL, map->ioctlmask); exca_setb(sc, EXCA_IOCTL, map->ioctlbits[io->width]); exca_setb(sc, EXCA_ADDRWIN_ENABLE, map->ioenable); #ifdef EXCA_DEBUG { int r1, r2, r3, r4; r1 = exca_getb(sc, map->start_msb); r2 = exca_getb(sc, map->start_lsb); r3 = exca_getb(sc, map->stop_msb); r4 = exca_getb(sc, map->stop_lsb); DPRINTF("exca_do_io_map window %d: %02x%02x %02x%02x " "(%08x+%08x)\n", win, r1, r2, r3, r4, io->addr, io->size); } #endif } int exca_io_map(struct exca_softc *sc, int width, struct resource *r) { int win; #ifdef EXCA_DEBUG static char *width_names[] = { "auto", "io8", "io16"}; #endif for (win=0; win < EXCA_IO_WINS; win++) { if ((sc->ioalloc & (1 << win)) == 0) { sc->ioalloc |= (1 << win); break; } } if (win >= EXCA_IO_WINS) return (ENOSPC); sc->io[win].iot = rman_get_bustag(r); sc->io[win].ioh = rman_get_bushandle(r); sc->io[win].addr = rman_get_start(r); sc->io[win].size = rman_get_end(r) - sc->io[win].addr + 1; sc->io[win].flags = 0; sc->io[win].width = width; DPRINTF("exca_io_map window %d %s port %x+%x\n", win, width_names[width], sc->io[win].addr, sc->io[win].size); exca_do_io_map(sc, win); return (0); } static void exca_io_unmap(struct exca_softc *sc, int window) { if (window >= EXCA_IO_WINS) panic("exca_io_unmap: window out of range"); exca_clrb(sc, EXCA_ADDRWIN_ENABLE, io_map_index[window].ioenable); sc->ioalloc &= ~(1 << window); sc->io[window].iot = 0; sc->io[window].ioh = 0; sc->io[window].addr = 0; sc->io[window].size = 0; sc->io[window].flags = 0; sc->io[window].width = 0; } static int exca_io_findmap(struct exca_softc *sc, struct resource *res) { int win; for (win = 0; win < EXCA_IO_WINS; win++) { if (sc->io[win].iot == rman_get_bustag(res) && sc->io[win].addr == rman_get_start(res) && sc->io[win].size == rman_get_size(res)) return (win); } return (-1); } int exca_io_unmap_res(struct exca_softc *sc, struct resource *res) { int win; win = exca_io_findmap(sc, res); if (win < 0) return (ENOENT); exca_io_unmap(sc, win); return (0); } /* Misc */ /* * If interrupts are enabled, then we should be able to just wait for * an interrupt routine to wake us up. Busy waiting shouldn't be * necessary. Sadly, not all legacy ISA cards support an interrupt * for the busy state transitions, at least according to their datasheets, * so we busy wait a while here.. */ static void exca_wait_ready(struct exca_softc *sc) { int i; DEVPRINTF(sc->dev, "exca_wait_ready: status 0x%02x\n", exca_getb(sc, EXCA_IF_STATUS)); for (i = 0; i < 10000; i++) { if (exca_getb(sc, EXCA_IF_STATUS) & EXCA_IF_STATUS_READY) return; DELAY(500); } device_printf(sc->dev, "ready never happened, status = %02x\n", exca_getb(sc, EXCA_IF_STATUS)); } /* * Reset the card. Ideally, we'd do a lot of this via interrupts. * However, many PC Cards will deassert the ready signal. This means * that they are asserting an interrupt. This makes it hard to * do anything but a busy wait here. One could argue that these * such cards are broken, or that the bridge that allows this sort * of interrupt through isn't quite what you'd want (and may be a standards * violation). However, such arguing would leave a huge class of PC Cards * and bridges out of reach for use in the system. * * Maybe I should reevaluate the above based on the power bug I fixed * in OLDCARD. */ void exca_reset(struct exca_softc *sc, device_t child) { int win; /* enable socket i/o */ exca_setb(sc, EXCA_PWRCTL, EXCA_PWRCTL_OE); exca_putb(sc, EXCA_INTR, EXCA_INTR_ENABLE); /* hold reset for 30ms */ DELAY(30*1000); /* clear the reset flag */ exca_setb(sc, EXCA_INTR, EXCA_INTR_RESET); /* wait 20ms as per PC Card standard (r2.01) section 4.3.6 */ DELAY(20*1000); exca_wait_ready(sc); /* disable all address windows */ exca_putb(sc, EXCA_ADDRWIN_ENABLE, 0); exca_setb(sc, EXCA_INTR, EXCA_INTR_CARDTYPE_IO); DEVPRINTF(sc->dev, "card type is io\n"); /* reinstall all the memory and io mappings */ for (win = 0; win < EXCA_MEM_WINS; ++win) if (sc->memalloc & (1 << win)) exca_do_mem_map(sc, win); for (win = 0; win < EXCA_IO_WINS; ++win) if (sc->ioalloc & (1 << win)) exca_do_io_map(sc, win); } /* * Initialize the exca_softc data structure for the first time. */ void exca_init(struct exca_softc *sc, device_t dev, bus_space_tag_t bst, bus_space_handle_t bsh, uint32_t offset) { sc->dev = dev; sc->memalloc = 0; sc->ioalloc = 0; sc->bst = bst; sc->bsh = bsh; sc->offset = offset; sc->flags = 0; sc->getb = exca_mem_getb; sc->putb = exca_mem_putb; + sc->pccarddev = device_add_child(dev, "pccard", -1); + if (sc->pccarddev == NULL) + DEVPRINTF(brdev, "WARNING: cannot add pccard bus.\n"); + else if (device_probe_and_attach(sc->pccarddev) != 0) + DEVPRINTF(brdev, "WARNING: cannot attach pccard bus.\n"); } /* * Is this socket valid? */ static int exca_valid_slot(struct exca_softc *exca) { uint8_t c; /* Assume the worst */ exca->chipset = EXCA_BOGUS; /* * see if there's a PCMCIA controller here * Intel PCMCIA controllers use 0x82 and 0x83 * IBM clone chips use 0x88 and 0x89, apparently */ c = exca_getb(exca, EXCA_IDENT); DEVPRINTF(exca->dev, "Ident is %x\n", c); if ((c & EXCA_IDENT_IFTYPE_MASK) != EXCA_IDENT_IFTYPE_MEM_AND_IO) return (0); if ((c & EXCA_IDENT_ZERO) != 0) return (0); switch (c & EXCA_IDENT_REV_MASK) { /* * 82365 or clones. */ case EXCA_IDENT_REV_I82365SLR0: case EXCA_IDENT_REV_I82365SLR1: exca->chipset = EXCA_I82365; /* * Check for Vadem chips by unlocking their extra * registers and looking for valid ID. Bit 3 in * the ID register is normally 0, except when * EXCA_VADEMREV is set. Other bridges appear * to ignore this frobbing. */ bus_space_write_1(exca->bst, exca->bsh, EXCA_REG_INDEX, EXCA_VADEM_COOKIE1); bus_space_write_1(exca->bst, exca->bsh, EXCA_REG_INDEX, EXCA_VADEM_COOKIE2); exca_setb(exca, EXCA_VADEM_VMISC, EXCA_VADEM_REV); c = exca_getb(exca, EXCA_IDENT); if (c & 0x08) { switch (c & 7) { case 1: exca->chipset = EXCA_VG365; break; case 2: exca->chipset = EXCA_VG465; break; case 3: exca->chipset = EXCA_VG468; break; default: exca->chipset = EXCA_VG469; break; } exca_clrb(exca, EXCA_VADEM_VMISC, EXCA_VADEM_REV); break; } /* * Check for RICOH RF5C[23]96 PCMCIA Controller */ c = exca_getb(exca, EXCA_RICOH_ID); if (c == EXCA_RID_396) { exca->chipset = EXCA_RF5C396; break; } else if (c == EXCA_RID_296) { exca->chipset = EXCA_RF5C296; break; } /* * Check for Cirrus logic chips. */ exca_putb(exca, EXCA_CIRRUS_CHIP_INFO, 0); c = exca_getb(exca, EXCA_CIRRUS_CHIP_INFO); if ((c & EXCA_CIRRUS_CHIP_INFO_CHIP_ID) == EXCA_CIRRUS_CHIP_INFO_CHIP_ID) { c = exca_getb(exca, EXCA_CIRRUS_CHIP_INFO); if ((c & EXCA_CIRRUS_CHIP_INFO_CHIP_ID) == 0) { if (c & EXCA_CIRRUS_CHIP_INFO_SLOTS) exca->chipset = EXCA_PD6722; else exca->chipset = EXCA_PD6710; break; } } break; case EXCA_IDENT_REV_I82365SLDF: /* * Intel i82365sl-DF step or maybe a vlsi 82c146 * we detected the vlsi case earlier, so if the controller * isn't set, we know it is a i82365sl step D. + * XXXX Except we didn't -- this is a regression but VLSI + * controllers are super hard to find these days for testing. */ exca->chipset = EXCA_I82365SL_DF; break; case EXCA_IDENT_REV_IBM1: case EXCA_IDENT_REV_IBM2: exca->chipset = EXCA_IBM; break; case EXCA_IDENT_REV_IBM_KING: exca->chipset = EXCA_IBM_KING; break; default: return (0); } return (1); } /* * Probe the expected slots. We maybe should set the ID for each of these * slots too while we're at it. But maybe that belongs to a separate * function. * * The caller must guarantee that at least EXCA_NSLOTS are present in exca. */ int exca_probe_slots(device_t dev, struct exca_softc *exca, bus_space_tag_t iot, bus_space_handle_t ioh) { int err; int i; err = ENXIO; for (i = 0; i < EXCA_NSLOTS; i++) { exca_init(&exca[i], dev, iot, ioh, i * EXCA_SOCKET_SIZE); exca->getb = exca_io_getb; exca->putb = exca_io_putb; if (exca_valid_slot(&exca[i])) { device_set_desc(dev, chip_names[exca[i].chipset]); err = 0; } } return (err); } void exca_insert(struct exca_softc *exca) { if (device_is_attached(exca->pccarddev)) { if (CARD_ATTACH_CARD(exca->pccarddev) != 0) device_printf(exca->dev, "PC Card card activation failed\n"); } else { device_printf(exca->dev, "PC Card inserted, but no pccard bus.\n"); } } void exca_removal(struct exca_softc *exca) { if (device_is_attached(exca->pccarddev)) CARD_DETACH_CARD(exca->pccarddev); } int exca_activate_resource(struct exca_softc *exca, device_t child, int type, int rid, struct resource *res) { int err; if (rman_get_flags(res) & RF_ACTIVE) return (0); err = BUS_ACTIVATE_RESOURCE(device_get_parent(exca->dev), child, type, rid, res); if (err) return (err); switch (type) { case SYS_RES_IOPORT: err = exca_io_map(exca, PCCARD_WIDTH_AUTO, res); break; case SYS_RES_MEMORY: err = exca_mem_map(exca, 0, res); break; } if (err) BUS_DEACTIVATE_RESOURCE(device_get_parent(exca->dev), child, type, rid, res); return (err); } int exca_deactivate_resource(struct exca_softc *exca, device_t child, int type, int rid, struct resource *res) { if (rman_get_flags(res) & RF_ACTIVE) { /* if activated */ switch (type) { case SYS_RES_IOPORT: if (exca_io_unmap_res(exca, res)) return (ENOENT); break; case SYS_RES_MEMORY: if (exca_mem_unmap_res(exca, res)) return (ENOENT); break; } } return (BUS_DEACTIVATE_RESOURCE(device_get_parent(exca->dev), child, type, rid, res)); } #if 0 static struct resource * exca_alloc_resource(struct exca_softc *sc, device_t child, int type, int *rid, u_long start, u_long end, u_long count, uint flags) { struct resource *res = NULL; int tmp; switch (type) { case SYS_RES_MEMORY: if (start < cbb_start_mem) start = cbb_start_mem; if (end < start) end = start; flags = (flags & ~RF_ALIGNMENT_MASK) | rman_make_alignment_flags(CBB_MEMALIGN); break; case SYS_RES_IOPORT: if (start < cbb_start_16_io) start = cbb_start_16_io; if (end < start) end = start; break; case SYS_RES_IRQ: tmp = rman_get_start(sc->irq_res); if (start > tmp || end < tmp || count != 1) { device_printf(child, "requested interrupt %ld-%ld," "count = %ld not supported by cbb\n", start, end, count); return (NULL); } flags |= RF_SHAREABLE; start = end = rman_get_start(sc->irq_res); break; } res = BUS_ALLOC_RESOURCE(up, child, type, rid, start, end, count, flags & ~RF_ACTIVE); if (res == NULL) return (NULL); cbb_insert_res(sc, res, type, *rid); if (flags & RF_ACTIVE) { if (bus_activate_resource(child, type, *rid, res) != 0) { bus_release_resource(child, type, *rid, res); return (NULL); } } return (res); } static int exca_release_resource(struct exca_softc *sc, device_t child, int type, int rid, struct resource *res) { int error; if (rman_get_flags(res) & RF_ACTIVE) { error = bus_deactivate_resource(child, type, rid, res); if (error != 0) return (error); } cbb_remove_res(sc, res); return (BUS_RELEASE_RESOURCE(device_get_parent(brdev), child, type, rid, res)); } #endif static int exca_modevent(module_t mod, int cmd, void *arg) { return 0; } DEV_MODULE(exca, exca_modevent, NULL); MODULE_VERSION(exca, 1); Index: head/sys/dev/pccbb/pccbb_pci.c =================================================================== --- head/sys/dev/pccbb/pccbb_pci.c (revision 355823) +++ head/sys/dev/pccbb/pccbb_pci.c (revision 355824) @@ -1,986 +1,980 @@ /*- * SPDX-License-Identifier: BSD-2-Clause-FreeBSD * * Copyright (c) 2000-2001 Jonathan Chen All rights reserved. * Copyright (c) 2002-2004 M. Warner Losh * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. * */ /*- * Copyright (c) 1998, 1999 and 2000 * HAYAKAWA Koichi. All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * 3. All advertising materials mentioning features or use of this software * must display the following acknowledgement: * This product includes software developed by HAYAKAWA Koichi. * 4. The name of the author may not be used to endorse or promote products * derived from this software without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* * Driver for PCI to CardBus Bridge chips * * References: * TI Datasheets: * http://www-s.ti.com/cgi-bin/sc/generic2.cgi?family=PCI+CARDBUS+CONTROLLERS * * Written by Jonathan Chen * The author would like to acknowledge: * * HAYAKAWA Koichi: Author of the NetBSD code for the same thing * * Warner Losh: Newbus/newcard guru and author of the pccard side of things * * YAMAMOTO Shigeru: Author of another FreeBSD cardbus driver * * David Cross: Author of the initial ugly hack for a specific cardbus card */ #include __FBSDID("$FreeBSD$"); #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include "power_if.h" #include "card_if.h" #include "pcib_if.h" #define DPRINTF(x) do { if (cbb_debug) printf x; } while (0) #define DEVPRINTF(x) do { if (cbb_debug) device_printf x; } while (0) #define PCI_MASK_CONFIG(DEV,REG,MASK,SIZE) \ pci_write_config(DEV, REG, pci_read_config(DEV, REG, SIZE) MASK, SIZE) #define PCI_MASK2_CONFIG(DEV,REG,MASK1,MASK2,SIZE) \ pci_write_config(DEV, REG, ( \ pci_read_config(DEV, REG, SIZE) MASK1) MASK2, SIZE) static void cbb_chipinit(struct cbb_softc *sc); static int cbb_pci_filt(void *arg); static struct yenta_chipinfo { uint32_t yc_id; const char *yc_name; int yc_chiptype; } yc_chipsets[] = { /* Texas Instruments chips */ {PCIC_ID_TI1031, "TI1031 PCI-PC Card Bridge", CB_TI113X}, {PCIC_ID_TI1130, "TI1130 PCI-CardBus Bridge", CB_TI113X}, {PCIC_ID_TI1131, "TI1131 PCI-CardBus Bridge", CB_TI113X}, {PCIC_ID_TI1210, "TI1210 PCI-CardBus Bridge", CB_TI12XX}, {PCIC_ID_TI1211, "TI1211 PCI-CardBus Bridge", CB_TI12XX}, {PCIC_ID_TI1220, "TI1220 PCI-CardBus Bridge", CB_TI12XX}, {PCIC_ID_TI1221, "TI1221 PCI-CardBus Bridge", CB_TI12XX}, {PCIC_ID_TI1225, "TI1225 PCI-CardBus Bridge", CB_TI12XX}, {PCIC_ID_TI1250, "TI1250 PCI-CardBus Bridge", CB_TI125X}, {PCIC_ID_TI1251, "TI1251 PCI-CardBus Bridge", CB_TI125X}, {PCIC_ID_TI1251B,"TI1251B PCI-CardBus Bridge",CB_TI125X}, {PCIC_ID_TI1260, "TI1260 PCI-CardBus Bridge", CB_TI12XX}, {PCIC_ID_TI1260B,"TI1260B PCI-CardBus Bridge",CB_TI12XX}, {PCIC_ID_TI1410, "TI1410 PCI-CardBus Bridge", CB_TI12XX}, {PCIC_ID_TI1420, "TI1420 PCI-CardBus Bridge", CB_TI12XX}, {PCIC_ID_TI1421, "TI1421 PCI-CardBus Bridge", CB_TI12XX}, {PCIC_ID_TI1450, "TI1450 PCI-CardBus Bridge", CB_TI125X}, /*SIC!*/ {PCIC_ID_TI1451, "TI1451 PCI-CardBus Bridge", CB_TI12XX}, {PCIC_ID_TI1510, "TI1510 PCI-CardBus Bridge", CB_TI12XX}, {PCIC_ID_TI1520, "TI1520 PCI-CardBus Bridge", CB_TI12XX}, {PCIC_ID_TI4410, "TI4410 PCI-CardBus Bridge", CB_TI12XX}, {PCIC_ID_TI4450, "TI4450 PCI-CardBus Bridge", CB_TI12XX}, {PCIC_ID_TI4451, "TI4451 PCI-CardBus Bridge", CB_TI12XX}, {PCIC_ID_TI4510, "TI4510 PCI-CardBus Bridge", CB_TI12XX}, {PCIC_ID_TI6411, "TI6411 PCI-CardBus Bridge", CB_TI12XX}, {PCIC_ID_TI6420, "TI6420 PCI-CardBus Bridge", CB_TI12XX}, {PCIC_ID_TI6420SC, "TI6420 PCI-CardBus Bridge", CB_TI12XX}, {PCIC_ID_TI7410, "TI7410 PCI-CardBus Bridge", CB_TI12XX}, {PCIC_ID_TI7510, "TI7510 PCI-CardBus Bridge", CB_TI12XX}, {PCIC_ID_TI7610, "TI7610 PCI-CardBus Bridge", CB_TI12XX}, {PCIC_ID_TI7610M, "TI7610 PCI-CardBus Bridge", CB_TI12XX}, {PCIC_ID_TI7610SD, "TI7610 PCI-CardBus Bridge", CB_TI12XX}, {PCIC_ID_TI7610MS, "TI7610 PCI-CardBus Bridge", CB_TI12XX}, /* ENE */ {PCIC_ID_ENE_CB710, "ENE CB710 PCI-CardBus Bridge", CB_TI12XX}, {PCIC_ID_ENE_CB720, "ENE CB720 PCI-CardBus Bridge", CB_TI12XX}, {PCIC_ID_ENE_CB1211, "ENE CB1211 PCI-CardBus Bridge", CB_TI12XX}, {PCIC_ID_ENE_CB1225, "ENE CB1225 PCI-CardBus Bridge", CB_TI12XX}, {PCIC_ID_ENE_CB1410, "ENE CB1410 PCI-CardBus Bridge", CB_TI12XX}, {PCIC_ID_ENE_CB1420, "ENE CB1420 PCI-CardBus Bridge", CB_TI12XX}, /* Ricoh chips */ {PCIC_ID_RICOH_RL5C465, "RF5C465 PCI-CardBus Bridge", CB_RF5C46X}, {PCIC_ID_RICOH_RL5C466, "RF5C466 PCI-CardBus Bridge", CB_RF5C46X}, {PCIC_ID_RICOH_RL5C475, "RF5C475 PCI-CardBus Bridge", CB_RF5C47X}, {PCIC_ID_RICOH_RL5C476, "RF5C476 PCI-CardBus Bridge", CB_RF5C47X}, {PCIC_ID_RICOH_RL5C477, "RF5C477 PCI-CardBus Bridge", CB_RF5C47X}, {PCIC_ID_RICOH_RL5C478, "RF5C478 PCI-CardBus Bridge", CB_RF5C47X}, /* Toshiba products */ {PCIC_ID_TOPIC95, "ToPIC95 PCI-CardBus Bridge", CB_TOPIC95}, {PCIC_ID_TOPIC95B, "ToPIC95B PCI-CardBus Bridge", CB_TOPIC95}, {PCIC_ID_TOPIC97, "ToPIC97 PCI-CardBus Bridge", CB_TOPIC97}, {PCIC_ID_TOPIC100, "ToPIC100 PCI-CardBus Bridge", CB_TOPIC97}, /* Cirrus Logic */ {PCIC_ID_CLPD6832, "CLPD6832 PCI-CardBus Bridge", CB_CIRRUS}, {PCIC_ID_CLPD6833, "CLPD6833 PCI-CardBus Bridge", CB_CIRRUS}, {PCIC_ID_CLPD6834, "CLPD6834 PCI-CardBus Bridge", CB_CIRRUS}, /* 02Micro */ {PCIC_ID_OZ6832, "O2Micro OZ6832/6833 PCI-CardBus Bridge", CB_O2MICRO}, {PCIC_ID_OZ6860, "O2Micro OZ6836/6860 PCI-CardBus Bridge", CB_O2MICRO}, {PCIC_ID_OZ6872, "O2Micro OZ6812/6872 PCI-CardBus Bridge", CB_O2MICRO}, {PCIC_ID_OZ6912, "O2Micro OZ6912/6972 PCI-CardBus Bridge", CB_O2MICRO}, {PCIC_ID_OZ6922, "O2Micro OZ6922 PCI-CardBus Bridge", CB_O2MICRO}, {PCIC_ID_OZ6933, "O2Micro OZ6933 PCI-CardBus Bridge", CB_O2MICRO}, {PCIC_ID_OZ711E1, "O2Micro OZ711E1 PCI-CardBus Bridge", CB_O2MICRO}, {PCIC_ID_OZ711EC1, "O2Micro OZ711EC1/M1 PCI-CardBus Bridge", CB_O2MICRO}, {PCIC_ID_OZ711E2, "O2Micro OZ711E2 PCI-CardBus Bridge", CB_O2MICRO}, {PCIC_ID_OZ711M1, "O2Micro OZ711M1 PCI-CardBus Bridge", CB_O2MICRO}, {PCIC_ID_OZ711M2, "O2Micro OZ711M2 PCI-CardBus Bridge", CB_O2MICRO}, {PCIC_ID_OZ711M3, "O2Micro OZ711M3 PCI-CardBus Bridge", CB_O2MICRO}, /* SMC */ {PCIC_ID_SMC_34C90, "SMC 34C90 PCI-CardBus Bridge", CB_CIRRUS}, /* sentinel */ {0 /* null id */, "unknown", CB_UNKNOWN}, }; /************************************************************************/ /* Probe/Attach */ /************************************************************************/ static int cbb_chipset(uint32_t pci_id, const char **namep) { struct yenta_chipinfo *ycp; for (ycp = yc_chipsets; ycp->yc_id != 0 && pci_id != ycp->yc_id; ++ycp) continue; if (namep != NULL) *namep = ycp->yc_name; return (ycp->yc_chiptype); } static int cbb_pci_probe(device_t brdev) { const char *name; uint32_t progif; uint32_t baseclass; uint32_t subclass; /* * Do we know that we support the chipset? If so, then we * accept the device. */ if (cbb_chipset(pci_get_devid(brdev), &name) != CB_UNKNOWN) { device_set_desc(brdev, name); return (BUS_PROBE_DEFAULT); } /* * We do support generic CardBus bridges. All that we've seen * to date have progif 0 (the Yenta spec, and successors mandate * this). */ baseclass = pci_get_class(brdev); subclass = pci_get_subclass(brdev); progif = pci_get_progif(brdev); if (baseclass == PCIC_BRIDGE && subclass == PCIS_BRIDGE_CARDBUS && progif == 0) { device_set_desc(brdev, "PCI-CardBus Bridge"); return (BUS_PROBE_GENERIC); } return (ENXIO); } /* * Print out the config space */ static void cbb_print_config(device_t dev) { int i; device_printf(dev, "PCI Configuration space:"); for (i = 0; i < 256; i += 4) { if (i % 16 == 0) printf("\n 0x%02x: ", i); printf("0x%08x ", pci_read_config(dev, i, 4)); } printf("\n"); } static int cbb_pci_attach(device_t brdev) { #if !(defined(NEW_PCIB) && defined(PCI_RES_BUS)) static int curr_bus_number = 2; /* XXX EVILE BAD (see below) */ uint32_t pribus; #endif struct cbb_softc *sc = (struct cbb_softc *)device_get_softc(brdev); struct sysctl_ctx_list *sctx; struct sysctl_oid *soid; int rid; device_t parent; parent = device_get_parent(brdev); mtx_init(&sc->mtx, device_get_nameunit(brdev), "cbb", MTX_DEF); sc->chipset = cbb_chipset(pci_get_devid(brdev), NULL); sc->dev = brdev; sc->cbdev = NULL; sc->domain = pci_get_domain(brdev); sc->pribus = pcib_get_bus(parent); #if defined(NEW_PCIB) && defined(PCI_RES_BUS) pci_write_config(brdev, PCIR_PRIBUS_2, sc->pribus, 1); pcib_setup_secbus(brdev, &sc->bus, 1); #else sc->bus.sec = pci_read_config(brdev, PCIR_SECBUS_2, 1); sc->bus.sub = pci_read_config(brdev, PCIR_SUBBUS_2, 1); #endif SLIST_INIT(&sc->rl); rid = CBBR_SOCKBASE; sc->base_res = bus_alloc_resource_any(brdev, SYS_RES_MEMORY, &rid, RF_ACTIVE); if (!sc->base_res) { device_printf(brdev, "Could not map register memory\n"); mtx_destroy(&sc->mtx); return (ENOMEM); } else { DEVPRINTF((brdev, "Found memory at %jx\n", rman_get_start(sc->base_res))); } + /* attach children */ + sc->cbdev = device_add_child(brdev, "cardbus", -1); + if (sc->cbdev == NULL) + DEVPRINTF((brdev, "WARNING: cannot add cardbus bus.\n")); + else if (device_probe_and_attach(sc->cbdev) != 0) + DEVPRINTF((brdev, "WARNING: cannot attach cardbus bus!\n")); + sc->bst = rman_get_bustag(sc->base_res); sc->bsh = rman_get_bushandle(sc->base_res); exca_init(&sc->exca, brdev, sc->bst, sc->bsh, CBB_EXCA_OFFSET); sc->exca.flags |= EXCA_HAS_MEMREG_WIN; sc->exca.chipset = EXCA_CARDBUS; sc->chipinit = cbb_chipinit; sc->chipinit(sc); /*Sysctls*/ sctx = device_get_sysctl_ctx(brdev); soid = device_get_sysctl_tree(brdev); SYSCTL_ADD_UINT(sctx, SYSCTL_CHILDREN(soid), OID_AUTO, "domain", CTLFLAG_RD, &sc->domain, 0, "Domain number"); SYSCTL_ADD_UINT(sctx, SYSCTL_CHILDREN(soid), OID_AUTO, "pribus", CTLFLAG_RD, &sc->pribus, 0, "Primary bus number"); SYSCTL_ADD_UINT(sctx, SYSCTL_CHILDREN(soid), OID_AUTO, "secbus", CTLFLAG_RD, &sc->bus.sec, 0, "Secondary bus number"); SYSCTL_ADD_UINT(sctx, SYSCTL_CHILDREN(soid), OID_AUTO, "subbus", CTLFLAG_RD, &sc->bus.sub, 0, "Subordinate bus number"); #if 0 SYSCTL_ADD_UINT(sctx, SYSCTL_CHILDREN(soid), OID_AUTO, "memory", CTLFLAG_RD, &sc->subbus, 0, "Memory window open"); SYSCTL_ADD_UINT(sctx, SYSCTL_CHILDREN(soid), OID_AUTO, "premem", CTLFLAG_RD, &sc->subbus, 0, "Prefetch memory window open"); SYSCTL_ADD_UINT(sctx, SYSCTL_CHILDREN(soid), OID_AUTO, "io1", CTLFLAG_RD, &sc->subbus, 0, "io range 1 open"); SYSCTL_ADD_UINT(sctx, SYSCTL_CHILDREN(soid), OID_AUTO, "io2", CTLFLAG_RD, &sc->subbus, 0, "io range 2 open"); #endif #if !(defined(NEW_PCIB) && defined(PCI_RES_BUS)) /* * This is a gross hack. We should be scanning the entire pci * tree, assigning bus numbers in a way such that we (1) can * reserve 1 extra bus just in case and (2) all sub buses * are in an appropriate range. */ DEVPRINTF((brdev, "Secondary bus is %d\n", sc->bus.sec)); pribus = pci_read_config(brdev, PCIR_PRIBUS_2, 1); if (sc->bus.sec == 0 || sc->pribus != pribus) { if (curr_bus_number <= sc->pribus) curr_bus_number = sc->pribus + 1; if (pribus != sc->pribus) { DEVPRINTF((brdev, "Setting primary bus to %d\n", sc->pribus)); pci_write_config(brdev, PCIR_PRIBUS_2, sc->pribus, 1); } sc->bus.sec = curr_bus_number++; sc->bus.sub = curr_bus_number++; DEVPRINTF((brdev, "Secondary bus set to %d subbus %d\n", sc->bus.sec, sc->bus.sub)); pci_write_config(brdev, PCIR_SECBUS_2, sc->bus.sec, 1); pci_write_config(brdev, PCIR_SUBBUS_2, sc->bus.sub, 1); } #endif - - /* attach children */ - sc->cbdev = device_add_child(brdev, "cardbus", -1); - if (sc->cbdev == NULL) - DEVPRINTF((brdev, "WARNING: cannot add cardbus bus.\n")); - else if (device_probe_and_attach(sc->cbdev) != 0) - DEVPRINTF((brdev, "WARNING: cannot attach cardbus bus!\n")); - - sc->exca.pccarddev = device_add_child(brdev, "pccard", -1); - if (sc->exca.pccarddev == NULL) - DEVPRINTF((brdev, "WARNING: cannot add pccard bus.\n")); - else if (device_probe_and_attach(sc->exca.pccarddev) != 0) - DEVPRINTF((brdev, "WARNING: cannot attach pccard bus.\n")); /* Map and establish the interrupt. */ rid = 0; sc->irq_res = bus_alloc_resource_any(brdev, SYS_RES_IRQ, &rid, RF_SHAREABLE | RF_ACTIVE); if (sc->irq_res == NULL) { device_printf(brdev, "Unable to map IRQ...\n"); goto err; } if (bus_setup_intr(brdev, sc->irq_res, INTR_TYPE_AV | INTR_MPSAFE, cbb_pci_filt, NULL, sc, &sc->intrhand)) { device_printf(brdev, "couldn't establish interrupt\n"); goto err; } /* reset 16-bit pcmcia bus */ exca_clrb(&sc->exca, EXCA_INTR, EXCA_INTR_RESET); /* turn off power */ cbb_power(brdev, CARD_OFF); /* CSC Interrupt: Card detect interrupt on */ cbb_setb(sc, CBB_SOCKET_MASK, CBB_SOCKET_MASK_CD); /* reset interrupt */ cbb_set(sc, CBB_SOCKET_EVENT, cbb_get(sc, CBB_SOCKET_EVENT)); if (bootverbose) cbb_print_config(brdev); /* Start the thread */ if (kproc_create(cbb_event_thread, sc, &sc->event_thread, 0, 0, "%s event thread", device_get_nameunit(brdev))) { device_printf(brdev, "unable to create event thread.\n"); panic("cbb_create_event_thread"); } sc->sc_root_token = root_mount_hold(device_get_nameunit(sc->dev)); return (0); err: if (sc->irq_res) bus_release_resource(brdev, SYS_RES_IRQ, 0, sc->irq_res); if (sc->base_res) { bus_release_resource(brdev, SYS_RES_MEMORY, CBBR_SOCKBASE, sc->base_res); } mtx_destroy(&sc->mtx); return (ENOMEM); } static int cbb_pci_detach(device_t brdev) { #if defined(NEW_PCIB) && defined(PCI_RES_BUS) struct cbb_softc *sc = device_get_softc(brdev); #endif int error; error = cbb_detach(brdev); #if defined(NEW_PCIB) && defined(PCI_RES_BUS) if (error == 0) pcib_free_secbus(brdev, &sc->bus); #endif return (error); } static void cbb_chipinit(struct cbb_softc *sc) { uint32_t mux, sysctrl, reg; /* Set CardBus latency timer */ if (pci_read_config(sc->dev, PCIR_SECLAT_2, 1) < 0x20) pci_write_config(sc->dev, PCIR_SECLAT_2, 0x20, 1); /* Set PCI latency timer */ if (pci_read_config(sc->dev, PCIR_LATTIMER, 1) < 0x20) pci_write_config(sc->dev, PCIR_LATTIMER, 0x20, 1); /* Enable DMA, memory access for this card and I/O access for children */ pci_enable_busmaster(sc->dev); pci_enable_io(sc->dev, SYS_RES_IOPORT); pci_enable_io(sc->dev, SYS_RES_MEMORY); /* disable Legacy IO */ switch (sc->chipset) { case CB_RF5C46X: PCI_MASK_CONFIG(sc->dev, CBBR_BRIDGECTRL, & ~(CBBM_BRIDGECTRL_RL_3E0_EN | CBBM_BRIDGECTRL_RL_3E2_EN), 2); break; default: pci_write_config(sc->dev, CBBR_LEGACY, 0x0, 4); break; } /* Use PCI interrupt for interrupt routing */ PCI_MASK2_CONFIG(sc->dev, CBBR_BRIDGECTRL, & ~(CBBM_BRIDGECTRL_MASTER_ABORT | CBBM_BRIDGECTRL_INTR_IREQ_ISA_EN), | CBBM_BRIDGECTRL_WRITE_POST_EN, 2); /* * XXX this should be a function table, ala OLDCARD. This means * that we could more easily support ISA interrupts for pccard * cards if we had to. */ switch (sc->chipset) { case CB_TI113X: /* * The TI 1031, TI 1130 and TI 1131 all require another bit * be set to enable PCI routing of interrupts, and then * a bit for each of the CSC and Function interrupts we * want routed. */ PCI_MASK_CONFIG(sc->dev, CBBR_CBCTRL, | CBBM_CBCTRL_113X_PCI_INTR | CBBM_CBCTRL_113X_PCI_CSC | CBBM_CBCTRL_113X_PCI_IRQ_EN, 1); PCI_MASK_CONFIG(sc->dev, CBBR_DEVCTRL, & ~(CBBM_DEVCTRL_INT_SERIAL | CBBM_DEVCTRL_INT_PCI), 1); break; case CB_TI12XX: /* * Some TI 12xx (and [14][45]xx) based pci cards * sometimes have issues with the MFUNC register not * being initialized due to a bad EEPROM on board. * Laptops that this matters on have this register * properly initialized. * * The TI125X parts have a different register. * * Note: Only the lower two nibbles matter. When set * to 0, the MFUNC{0,1} pins are GPIO, which isn't * going to work out too well because we specifically * program these parts to parallel interrupt signalling * elsewhere. We preserve the upper bits of this * register since changing them have subtle side effects * for different variants of the card and are * extremely difficult to exaustively test. * * Also, the TI 1510/1520 changed the default for the MFUNC * register from 0x0 to 0x1000 to enable IRQSER by default. * We want to be careful to avoid overriding that, and the * below test will do that. Should this check prove to be * too permissive, we should just check against 0 and 0x1000 * and not touch it otherwise. */ mux = pci_read_config(sc->dev, CBBR_MFUNC, 4); sysctrl = pci_read_config(sc->dev, CBBR_SYSCTRL, 4); if ((mux & (CBBM_MFUNC_PIN0 | CBBM_MFUNC_PIN1)) == 0) { mux = (mux & ~CBBM_MFUNC_PIN0) | CBBM_MFUNC_PIN0_INTA; if ((sysctrl & CBBM_SYSCTRL_INTRTIE) == 0) mux = (mux & ~CBBM_MFUNC_PIN1) | CBBM_MFUNC_PIN1_INTB; pci_write_config(sc->dev, CBBR_MFUNC, mux, 4); } /*FALLTHROUGH*/ case CB_TI125X: /* * Disable zoom video. Some machines initialize this * improperly and exerpience has shown that this helps * prevent strange behavior. We don't support zoom * video anyway, so no harm can come from this. */ pci_write_config(sc->dev, CBBR_MMCTRL, 0, 4); break; case CB_O2MICRO: /* * Issue #1: INT# generated at the same time as * selected ISA IRQ. When IREQ# or STSCHG# is active, * in addition to the ISA IRQ being generated, INT# * will also be generated at the same time. * * Some of the older controllers have an issue in * which the slot's PCI INT# will be asserted whenever * IREQ# or STSCGH# is asserted even if ExCA registers * 03h or 05h have an ISA IRQ selected. * * The fix for this issue, which will work for any * controller (old or new), is to set ExCA registers * 3Ah (slot 0) & 7Ah (slot 1) bits 7:4 = 1010b. * These bits are undocumented. By setting this * register (of each slot) to '1010xxxxb' a routing of * IREQ# to INTC# and STSCHG# to INTC# is selected. * Since INTC# isn't connected there will be no * unexpected PCI INT when IREQ# or STSCHG# is active. * However, INTA# (slot 0) or INTB# (slot 1) will * still be correctly generated if NO ISA IRQ is * selected (ExCA regs 03h or 05h are cleared). */ reg = exca_getb(&sc->exca, EXCA_O2MICRO_CTRL_C); reg = (reg & 0x0f) | EXCA_O2CC_IREQ_INTC | EXCA_O2CC_STSCHG_INTC; exca_putb(&sc->exca, EXCA_O2MICRO_CTRL_C, reg); break; case CB_TOPIC97: /* * Disable Zoom Video, ToPIC 97, 100. */ pci_write_config(sc->dev, TOPIC97_ZV_CONTROL, 0, 1); /* * ToPIC 97, 100 * At offset 0xa1: INTERRUPT CONTROL register * 0x1: Turn on INT interrupts. */ PCI_MASK_CONFIG(sc->dev, TOPIC_INTCTRL, | TOPIC97_INTCTRL_INTIRQSEL, 1); /* * ToPIC97, 100 * Need to assert support for low voltage cards */ exca_setb(&sc->exca, EXCA_TOPIC97_CTRL, EXCA_TOPIC97_CTRL_LV_MASK); goto topic_common; case CB_TOPIC95: /* * SOCKETCTRL appears to be TOPIC 95/B specific */ PCI_MASK_CONFIG(sc->dev, TOPIC95_SOCKETCTRL, | TOPIC95_SOCKETCTRL_SCR_IRQSEL, 4); topic_common:; /* * At offset 0xa0: SLOT CONTROL * 0x80 Enable CardBus Functionality * 0x40 Enable CardBus and PC Card registers * 0x20 Lock ID in exca regs * 0x10 Write protect ID in config regs * Clear the rest of the bits, which defaults the slot * in legacy mode to 0x3e0 and offset 0. (legacy * mode is determined elsewhere) */ pci_write_config(sc->dev, TOPIC_SLOTCTRL, TOPIC_SLOTCTRL_SLOTON | TOPIC_SLOTCTRL_SLOTEN | TOPIC_SLOTCTRL_ID_LOCK | TOPIC_SLOTCTRL_ID_WP, 1); /* * At offset 0xa3 Card Detect Control Register * 0x80 CARDBUS enbale * 0x01 Cleared for hardware change detect */ PCI_MASK2_CONFIG(sc->dev, TOPIC_CDC, | TOPIC_CDC_CARDBUS, & ~TOPIC_CDC_SWDETECT, 4); break; } /* * Need to tell ExCA registers to CSC interrupts route via PCI * interrupts. There are two ways to do this. One is to set * INTR_ENABLE and the other is to set CSC to 0. Since both * methods are mutually compatible, we do both. */ exca_putb(&sc->exca, EXCA_INTR, EXCA_INTR_ENABLE); exca_putb(&sc->exca, EXCA_CSC_INTR, 0); cbb_disable_func_intr(sc); /* close all memory and io windows */ pci_write_config(sc->dev, CBBR_MEMBASE0, 0xffffffff, 4); pci_write_config(sc->dev, CBBR_MEMLIMIT0, 0, 4); pci_write_config(sc->dev, CBBR_MEMBASE1, 0xffffffff, 4); pci_write_config(sc->dev, CBBR_MEMLIMIT1, 0, 4); pci_write_config(sc->dev, CBBR_IOBASE0, 0xffffffff, 4); pci_write_config(sc->dev, CBBR_IOLIMIT0, 0, 4); pci_write_config(sc->dev, CBBR_IOBASE1, 0xffffffff, 4); pci_write_config(sc->dev, CBBR_IOLIMIT1, 0, 4); } static int cbb_route_interrupt(device_t pcib, device_t dev, int pin) { struct cbb_softc *sc = (struct cbb_softc *)device_get_softc(pcib); return (rman_get_start(sc->irq_res)); } static int cbb_pci_shutdown(device_t brdev) { struct cbb_softc *sc = (struct cbb_softc *)device_get_softc(brdev); /* * We're about to pull the rug out from the card, so mark it as * gone to prevent harm. */ sc->cardok = 0; /* * Place the cards in reset, turn off the interrupts and power * down the socket. */ PCI_MASK_CONFIG(brdev, CBBR_BRIDGECTRL, |CBBM_BRIDGECTRL_RESET, 2); exca_clrb(&sc->exca, EXCA_INTR, EXCA_INTR_RESET); cbb_set(sc, CBB_SOCKET_MASK, 0); cbb_set(sc, CBB_SOCKET_EVENT, 0xffffffff); cbb_power(brdev, CARD_OFF); /* * For paranoia, turn off all address decoding. Really not needed, * it seems, but it can't hurt */ exca_putb(&sc->exca, EXCA_ADDRWIN_ENABLE, 0); pci_write_config(brdev, CBBR_MEMBASE0, 0, 4); pci_write_config(brdev, CBBR_MEMLIMIT0, 0, 4); pci_write_config(brdev, CBBR_MEMBASE1, 0, 4); pci_write_config(brdev, CBBR_MEMLIMIT1, 0, 4); pci_write_config(brdev, CBBR_IOBASE0, 0, 4); pci_write_config(brdev, CBBR_IOLIMIT0, 0, 4); pci_write_config(brdev, CBBR_IOBASE1, 0, 4); pci_write_config(brdev, CBBR_IOLIMIT1, 0, 4); return (0); } static int cbb_pci_filt(void *arg) { struct cbb_softc *sc = arg; uint32_t sockevent; uint8_t csc; int retval = FILTER_STRAY; /* * Some chips also require us to read the old ExCA registe for card * status change when we route CSC vis PCI. This isn't supposed to be * required, but it clears the interrupt state on some chipsets. * Maybe there's a setting that would obviate its need. Maybe we * should test the status bits and deal with them, but so far we've * not found any machines that don't also give us the socket status * indication above. * * This call used to be unconditional. However, further research * suggests that we hit this condition when the card READY interrupt * fired. So now we only read it for 16-bit cards, and we only claim * the interrupt if READY is set. If this still causes problems, then * the next step would be to read this if we have a 16-bit card *OR* * we have no card. We treat the READY signal as if it were the power * completion signal. Some bridges may double signal things here, bit * signalling twice should be OK since we only sleep on the powerintr * in one place and a double wakeup would be benign there. */ if (sc->flags & CBB_16BIT_CARD) { csc = exca_getb(&sc->exca, EXCA_CSC); if (csc & EXCA_CSC_READY) { atomic_add_int(&sc->powerintr, 1); wakeup((void *)&sc->powerintr); retval = FILTER_HANDLED; } } /* * Read the socket event. Sometimes, the theory goes, the PCI bus is * so loaded that it cannot satisfy the read request, so we get * garbage back from the following read. We have to filter out the * garbage so that we don't spontaneously reset the card under high * load. PCI isn't supposed to act like this. No doubt this is a bug * in the PCI bridge chipset (or cbb brige) that's being used in * certain amd64 laptops today. Work around the issue by assuming * that any bits we don't know about being set means that we got * garbage. */ sockevent = cbb_get(sc, CBB_SOCKET_EVENT); if (sockevent != 0 && (sockevent & ~CBB_SOCKET_EVENT_VALID_MASK) == 0) { /* * If anything has happened to the socket, we assume that the * card is no longer OK, and we shouldn't call its ISR. We * set cardok as soon as we've attached the card. This helps * in a noisy eject, which happens all too often when users * are ejecting their PC Cards. * * We use this method in preference to checking to see if the * card is still there because the check suffers from a race * condition in the bouncing case. */ #define DELTA (CBB_SOCKET_MASK_CD) if (sockevent & DELTA) { cbb_clrb(sc, CBB_SOCKET_MASK, DELTA); cbb_set(sc, CBB_SOCKET_EVENT, DELTA); sc->cardok = 0; cbb_disable_func_intr(sc); wakeup(&sc->intrhand); } #undef DELTA /* * Wakeup anybody waiting for a power interrupt. We have to * use atomic_add_int for wakups on other cores. */ if (sockevent & CBB_SOCKET_EVENT_POWER) { cbb_clrb(sc, CBB_SOCKET_MASK, CBB_SOCKET_EVENT_POWER); cbb_set(sc, CBB_SOCKET_EVENT, CBB_SOCKET_EVENT_POWER); atomic_add_int(&sc->powerintr, 1); wakeup((void *)&sc->powerintr); } /* * Status change interrupts aren't presently used in the * rest of the driver. For now, just ACK them. */ if (sockevent & CBB_SOCKET_EVENT_CSTS) cbb_set(sc, CBB_SOCKET_EVENT, CBB_SOCKET_EVENT_CSTS); retval = FILTER_HANDLED; } return retval; } #if defined(NEW_PCIB) && defined(PCI_RES_BUS) static struct resource * cbb_pci_alloc_resource(device_t bus, device_t child, int type, int *rid, rman_res_t start, rman_res_t end, rman_res_t count, u_int flags) { struct cbb_softc *sc; sc = device_get_softc(bus); if (type == PCI_RES_BUS) return (pcib_alloc_subbus(&sc->bus, child, rid, start, end, count, flags)); return (cbb_alloc_resource(bus, child, type, rid, start, end, count, flags)); } static int cbb_pci_adjust_resource(device_t bus, device_t child, int type, struct resource *r, rman_res_t start, rman_res_t end) { struct cbb_softc *sc; sc = device_get_softc(bus); if (type == PCI_RES_BUS) { if (!rman_is_region_manager(r, &sc->bus.rman)) return (EINVAL); return (rman_adjust_resource(r, start, end)); } return (bus_generic_adjust_resource(bus, child, type, r, start, end)); } static int cbb_pci_release_resource(device_t bus, device_t child, int type, int rid, struct resource *r) { struct cbb_softc *sc; int error; sc = device_get_softc(bus); if (type == PCI_RES_BUS) { if (!rman_is_region_manager(r, &sc->bus.rman)) return (EINVAL); if (rman_get_flags(r) & RF_ACTIVE) { error = bus_deactivate_resource(child, type, rid, r); if (error) return (error); } return (rman_release_resource(r)); } return (cbb_release_resource(bus, child, type, rid, r)); } #endif /************************************************************************/ /* PCI compat methods */ /************************************************************************/ static int cbb_maxslots(device_t brdev) { return (0); } static uint32_t cbb_read_config(device_t brdev, u_int b, u_int s, u_int f, u_int reg, int width) { /* * Pass through to the next ppb up the chain (i.e. our grandparent). */ return (PCIB_READ_CONFIG(device_get_parent(device_get_parent(brdev)), b, s, f, reg, width)); } static void cbb_write_config(device_t brdev, u_int b, u_int s, u_int f, u_int reg, uint32_t val, int width) { /* * Pass through to the next ppb up the chain (i.e. our grandparent). */ PCIB_WRITE_CONFIG(device_get_parent(device_get_parent(brdev)), b, s, f, reg, val, width); } static int cbb_pci_suspend(device_t brdev) { int error = 0; struct cbb_softc *sc = device_get_softc(brdev); error = bus_generic_suspend(brdev); if (error != 0) return (error); cbb_set(sc, CBB_SOCKET_MASK, 0); /* Quiet hardware */ sc->cardok = 0; /* Card is bogus now */ return (0); } static int cbb_pci_resume(device_t brdev) { int error = 0; struct cbb_softc *sc = (struct cbb_softc *)device_get_softc(brdev); uint32_t tmp; /* * In the APM and early ACPI era, BIOSes saved the PCI config * registers. As chips became more complicated, that functionality moved * into the ACPI code / tables. We must therefore, restore the settings * we made here to make sure the device come back. Transitions to Dx * from D0 and back to D0 cause the bridge to lose its config space, so * all the bus mappings and such are preserved. * * The PCI layer handles standard PCI registers like the * command register and BARs, but cbb-specific registers are * handled here. */ sc->chipinit(sc); /* reset interrupt -- Do we really need to do this? */ tmp = cbb_get(sc, CBB_SOCKET_EVENT); cbb_set(sc, CBB_SOCKET_EVENT, tmp); /* CSC Interrupt: Card detect interrupt on */ cbb_setb(sc, CBB_SOCKET_MASK, CBB_SOCKET_MASK_CD); /* Signal the thread to wakeup. */ wakeup(&sc->intrhand); error = bus_generic_resume(brdev); return (error); } static device_method_t cbb_methods[] = { /* Device interface */ DEVMETHOD(device_probe, cbb_pci_probe), DEVMETHOD(device_attach, cbb_pci_attach), DEVMETHOD(device_detach, cbb_pci_detach), DEVMETHOD(device_shutdown, cbb_pci_shutdown), DEVMETHOD(device_suspend, cbb_pci_suspend), DEVMETHOD(device_resume, cbb_pci_resume), /* bus methods */ DEVMETHOD(bus_read_ivar, cbb_read_ivar), DEVMETHOD(bus_write_ivar, cbb_write_ivar), #if defined(NEW_PCIB) && defined(PCI_RES_BUS) DEVMETHOD(bus_alloc_resource, cbb_pci_alloc_resource), DEVMETHOD(bus_adjust_resource, cbb_pci_adjust_resource), DEVMETHOD(bus_release_resource, cbb_pci_release_resource), #else DEVMETHOD(bus_alloc_resource, cbb_alloc_resource), DEVMETHOD(bus_release_resource, cbb_release_resource), #endif DEVMETHOD(bus_activate_resource, cbb_activate_resource), DEVMETHOD(bus_deactivate_resource, cbb_deactivate_resource), DEVMETHOD(bus_driver_added, cbb_driver_added), DEVMETHOD(bus_child_detached, cbb_child_detached), DEVMETHOD(bus_setup_intr, cbb_setup_intr), DEVMETHOD(bus_teardown_intr, cbb_teardown_intr), DEVMETHOD(bus_child_present, cbb_child_present), /* 16-bit card interface */ DEVMETHOD(card_set_res_flags, cbb_pcic_set_res_flags), DEVMETHOD(card_set_memory_offset, cbb_pcic_set_memory_offset), /* power interface */ DEVMETHOD(power_enable_socket, cbb_power_enable_socket), DEVMETHOD(power_disable_socket, cbb_power_disable_socket), /* pcib compatibility interface */ DEVMETHOD(pcib_maxslots, cbb_maxslots), DEVMETHOD(pcib_read_config, cbb_read_config), DEVMETHOD(pcib_write_config, cbb_write_config), DEVMETHOD(pcib_route_interrupt, cbb_route_interrupt), DEVMETHOD_END }; static driver_t cbb_driver = { "cbb", cbb_methods, sizeof(struct cbb_softc) }; DRIVER_MODULE(cbb, pci, cbb_driver, cbb_devclass, 0, 0); MODULE_PNP_INFO("W32:vendor/device;D:#", pci, cbb, yc_chipsets, nitems(yc_chipsets) - 1); MODULE_DEPEND(cbb, exca, 1, 1, 1);