Index: head/sys/arm/broadcom/bcm2835/bcm2835_bsc.c =================================================================== --- head/sys/arm/broadcom/bcm2835/bcm2835_bsc.c (revision 355734) +++ head/sys/arm/broadcom/bcm2835/bcm2835_bsc.c (revision 355735) @@ -1,725 +1,723 @@ /*- * SPDX-License-Identifier: BSD-2-Clause-FreeBSD * * Copyright (c) 2001 Tsubai Masanari. * Copyright (c) 2012 Oleksandr Tymoshenko * Copyright (c) 2013 Luiz Otavio O Souza * Copyright (c) 2017 Ian Lepore * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. * */ #include __FBSDID("$FreeBSD$"); /* * Driver for bcm2835 i2c-compatible two-wire bus, named 'BSC' on this SoC. * * This controller can only perform complete transfers, it does not provide * low-level control over sending start/repeat-start/stop sequences on the bus. * In addition, bugs in the silicon make it somewhat difficult to perform a * repeat-start, and limit the repeat-start to a read following a write on * the same slave device. (The i2c protocol allows a repeat start to change * direction or not, and change slave address or not at any time.) * * The repeat-start bug and workaround are described in a problem report at * https://github.com/raspberrypi/linux/issues/254 with the crucial part being * in a comment block from a fragment of a GPU i2c driver, containing this: * * ----------------------------------------------------------------------------- * - See i2c.v: The I2C peripheral samples the values for rw_bit and xfer_count * - in the IDLE state if start is set. * - * - We want to generate a ReSTART not a STOP at the end of the TX phase. In * - order to do that we must ensure the state machine goes RACK1 -> RACK2 -> * - SRSTRT1 (not RACK1 -> RACK2 -> SSTOP1). * - * - So, in the RACK2 state when (TX) xfer_count==0 we must therefore have * - already set, ready to be sampled: * - READ ; rw_bit <= I2CC bit 0 -- must be "read" * - ST; start <= I2CC bit 7 -- must be "Go" in order to not issue STOP * - DLEN; xfer_count <= I2CDLEN -- must be equal to our read amount * - * - The plan to do this is: * - 1. Start the sub-address write, but don't let it finish * - (keep xfer_count > 0) * - 2. Populate READ, DLEN and ST in preparation for ReSTART read sequence * - 3. Let TX finish (write the rest of the data) * - 4. Read back data as it arrives * ----------------------------------------------------------------------------- * * The transfer function below scans the list of messages passed to it, looking * for a read following a write to the same slave. When it finds that, it * starts the write without prefilling the tx fifo, which holds xfer_count>0, * then presets the direction, length, and start command for the following read, * as described above. Then the tx fifo is filled and the rest of the transfer * proceeds as normal, with the controller automatically supplying a * repeat-start on the bus when the write operation finishes. * * XXX I suspect the controller may be able to do a repeat-start on any * write->read or write->write transition, even when the slave addresses differ. * It's unclear whether the slave address can be prestaged along with the * direction and length while the write xfer_count is being held at zero. In * fact, if it can't do this, then it couldn't be used to read EDID data. */ #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include "iicbus_if.h" static struct ofw_compat_data compat_data[] = { {"broadcom,bcm2835-bsc", 1}, {"brcm,bcm2708-i2c", 1}, {"brcm,bcm2835-i2c", 1}, {NULL, 0} }; #define DEVICE_DEBUGF(sc, lvl, fmt, args...) \ if ((lvl) <= (sc)->sc_debug) \ device_printf((sc)->sc_dev, fmt, ##args) #define DEBUGF(sc, lvl, fmt, args...) \ if ((lvl) <= (sc)->sc_debug) \ printf(fmt, ##args) static void bcm_bsc_intr(void *); static int bcm_bsc_detach(device_t); static void bcm_bsc_modifyreg(struct bcm_bsc_softc *sc, uint32_t off, uint32_t mask, uint32_t value) { uint32_t reg; mtx_assert(&sc->sc_mtx, MA_OWNED); reg = BCM_BSC_READ(sc, off); reg &= ~mask; reg |= value; BCM_BSC_WRITE(sc, off, reg); } static int bcm_bsc_clock_proc(SYSCTL_HANDLER_ARGS) { struct bcm_bsc_softc *sc; uint32_t clk; sc = (struct bcm_bsc_softc *)arg1; BCM_BSC_LOCK(sc); clk = BCM_BSC_READ(sc, BCM_BSC_CLOCK); BCM_BSC_UNLOCK(sc); clk &= 0xffff; if (clk == 0) clk = 32768; clk = BCM_BSC_CORE_CLK / clk; return (sysctl_handle_int(oidp, &clk, 0, req)); } static int bcm_bsc_clkt_proc(SYSCTL_HANDLER_ARGS) { struct bcm_bsc_softc *sc; uint32_t clkt; int error; sc = (struct bcm_bsc_softc *)arg1; BCM_BSC_LOCK(sc); clkt = BCM_BSC_READ(sc, BCM_BSC_CLKT); BCM_BSC_UNLOCK(sc); clkt &= 0xffff; error = sysctl_handle_int(oidp, &clkt, sizeof(clkt), req); if (error != 0 || req->newptr == NULL) return (error); BCM_BSC_LOCK(sc); BCM_BSC_WRITE(sc, BCM_BSC_CLKT, clkt & 0xffff); BCM_BSC_UNLOCK(sc); return (0); } static int bcm_bsc_fall_proc(SYSCTL_HANDLER_ARGS) { struct bcm_bsc_softc *sc; uint32_t clk, reg; int error; sc = (struct bcm_bsc_softc *)arg1; BCM_BSC_LOCK(sc); reg = BCM_BSC_READ(sc, BCM_BSC_DELAY); BCM_BSC_UNLOCK(sc); reg >>= 16; error = sysctl_handle_int(oidp, ®, sizeof(reg), req); if (error != 0 || req->newptr == NULL) return (error); BCM_BSC_LOCK(sc); clk = BCM_BSC_READ(sc, BCM_BSC_CLOCK); clk = BCM_BSC_CORE_CLK / clk; if (reg > clk / 2) reg = clk / 2 - 1; bcm_bsc_modifyreg(sc, BCM_BSC_DELAY, 0xffff0000, reg << 16); BCM_BSC_UNLOCK(sc); return (0); } static int bcm_bsc_rise_proc(SYSCTL_HANDLER_ARGS) { struct bcm_bsc_softc *sc; uint32_t clk, reg; int error; sc = (struct bcm_bsc_softc *)arg1; BCM_BSC_LOCK(sc); reg = BCM_BSC_READ(sc, BCM_BSC_DELAY); BCM_BSC_UNLOCK(sc); reg &= 0xffff; error = sysctl_handle_int(oidp, ®, sizeof(reg), req); if (error != 0 || req->newptr == NULL) return (error); BCM_BSC_LOCK(sc); clk = BCM_BSC_READ(sc, BCM_BSC_CLOCK); clk = BCM_BSC_CORE_CLK / clk; if (reg > clk / 2) reg = clk / 2 - 1; bcm_bsc_modifyreg(sc, BCM_BSC_DELAY, 0xffff, reg); BCM_BSC_UNLOCK(sc); return (0); } static void bcm_bsc_sysctl_init(struct bcm_bsc_softc *sc) { struct sysctl_ctx_list *ctx; struct sysctl_oid *tree_node; struct sysctl_oid_list *tree; /* * Add system sysctl tree/handlers. */ ctx = device_get_sysctl_ctx(sc->sc_dev); tree_node = device_get_sysctl_tree(sc->sc_dev); tree = SYSCTL_CHILDREN(tree_node); SYSCTL_ADD_PROC(ctx, tree, OID_AUTO, "frequency", CTLFLAG_RW | CTLTYPE_UINT, sc, sizeof(*sc), bcm_bsc_clock_proc, "IU", "I2C BUS clock frequency"); SYSCTL_ADD_PROC(ctx, tree, OID_AUTO, "clock_stretch", CTLFLAG_RW | CTLTYPE_UINT, sc, sizeof(*sc), bcm_bsc_clkt_proc, "IU", "I2C BUS clock stretch timeout"); SYSCTL_ADD_PROC(ctx, tree, OID_AUTO, "fall_edge_delay", CTLFLAG_RW | CTLTYPE_UINT, sc, sizeof(*sc), bcm_bsc_fall_proc, "IU", "I2C BUS falling edge delay"); SYSCTL_ADD_PROC(ctx, tree, OID_AUTO, "rise_edge_delay", CTLFLAG_RW | CTLTYPE_UINT, sc, sizeof(*sc), bcm_bsc_rise_proc, "IU", "I2C BUS rising edge delay"); SYSCTL_ADD_INT(ctx, tree, OID_AUTO, "debug", CTLFLAG_RWTUN, &sc->sc_debug, 0, "Enable debug; 1=reads/writes, 2=add starts/stops"); } static void bcm_bsc_reset(struct bcm_bsc_softc *sc) { /* Enable the BSC Controller, disable interrupts. */ BCM_BSC_WRITE(sc, BCM_BSC_CTRL, BCM_BSC_CTRL_I2CEN); /* Clear pending interrupts. */ BCM_BSC_WRITE(sc, BCM_BSC_STATUS, BCM_BSC_STATUS_CLKT | BCM_BSC_STATUS_ERR | BCM_BSC_STATUS_DONE); /* Clear the FIFO. */ bcm_bsc_modifyreg(sc, BCM_BSC_CTRL, BCM_BSC_CTRL_CLEAR0, BCM_BSC_CTRL_CLEAR0); } static int bcm_bsc_probe(device_t dev) { if (!ofw_bus_status_okay(dev)) return (ENXIO); if (ofw_bus_search_compatible(dev, compat_data)->ocd_data == 0) return (ENXIO); device_set_desc(dev, "BCM2708/2835 BSC controller"); return (BUS_PROBE_DEFAULT); } static int bcm_bsc_attach(device_t dev) { struct bcm_bsc_softc *sc; int rid; sc = device_get_softc(dev); sc->sc_dev = dev; rid = 0; sc->sc_mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, RF_ACTIVE); if (!sc->sc_mem_res) { device_printf(dev, "cannot allocate memory window\n"); return (ENXIO); } sc->sc_bst = rman_get_bustag(sc->sc_mem_res); sc->sc_bsh = rman_get_bushandle(sc->sc_mem_res); rid = 0; sc->sc_irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, RF_ACTIVE | RF_SHAREABLE); if (!sc->sc_irq_res) { bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->sc_mem_res); device_printf(dev, "cannot allocate interrupt\n"); return (ENXIO); } /* Hook up our interrupt handler. */ if (bus_setup_intr(dev, sc->sc_irq_res, INTR_TYPE_MISC | INTR_MPSAFE, NULL, bcm_bsc_intr, sc, &sc->sc_intrhand)) { bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sc_irq_res); bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->sc_mem_res); device_printf(dev, "cannot setup the interrupt handler\n"); return (ENXIO); } mtx_init(&sc->sc_mtx, "bcm_bsc", NULL, MTX_DEF); bcm_bsc_sysctl_init(sc); /* Enable the BSC controller. Flush the FIFO. */ BCM_BSC_LOCK(sc); bcm_bsc_reset(sc); BCM_BSC_UNLOCK(sc); sc->sc_iicbus = device_add_child(dev, "iicbus", -1); if (sc->sc_iicbus == NULL) { bcm_bsc_detach(dev); return (ENXIO); } /* Probe and attach the iicbus when interrupts are available. */ - bus_delayed_attach_children(dev); - - return (0); + return (bus_delayed_attach_children(dev)); } static int bcm_bsc_detach(device_t dev) { struct bcm_bsc_softc *sc; bus_generic_detach(dev); sc = device_get_softc(dev); if (sc->sc_iicbus != NULL) device_delete_child(dev, sc->sc_iicbus); mtx_destroy(&sc->sc_mtx); if (sc->sc_intrhand) bus_teardown_intr(dev, sc->sc_irq_res, sc->sc_intrhand); if (sc->sc_irq_res) bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sc_irq_res); if (sc->sc_mem_res) bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->sc_mem_res); return (0); } static void bcm_bsc_empty_rx_fifo(struct bcm_bsc_softc *sc) { uint32_t status; /* Assumes sc_totlen > 0 and BCM_BSC_STATUS_RXD is asserted on entry. */ do { if (sc->sc_resid == 0) { sc->sc_data = sc->sc_curmsg->buf; sc->sc_dlen = sc->sc_curmsg->len; sc->sc_resid = sc->sc_dlen; ++sc->sc_curmsg; } do { *sc->sc_data = BCM_BSC_READ(sc, BCM_BSC_DATA); DEBUGF(sc, 1, "0x%02x ", *sc->sc_data); ++sc->sc_data; --sc->sc_resid; --sc->sc_totlen; status = BCM_BSC_READ(sc, BCM_BSC_STATUS); } while (sc->sc_resid > 0 && (status & BCM_BSC_STATUS_RXD)); } while (sc->sc_totlen > 0 && (status & BCM_BSC_STATUS_RXD)); } static void bcm_bsc_fill_tx_fifo(struct bcm_bsc_softc *sc) { uint32_t status; /* Assumes sc_totlen > 0 and BCM_BSC_STATUS_TXD is asserted on entry. */ do { if (sc->sc_resid == 0) { sc->sc_data = sc->sc_curmsg->buf; sc->sc_dlen = sc->sc_curmsg->len; sc->sc_resid = sc->sc_dlen; ++sc->sc_curmsg; } do { BCM_BSC_WRITE(sc, BCM_BSC_DATA, *sc->sc_data); DEBUGF(sc, 1, "0x%02x ", *sc->sc_data); ++sc->sc_data; --sc->sc_resid; --sc->sc_totlen; status = BCM_BSC_READ(sc, BCM_BSC_STATUS); } while (sc->sc_resid > 0 && (status & BCM_BSC_STATUS_TXD)); /* * If a repeat-start was pending and we just hit the end of a tx * buffer, see if it's also the end of the writes that preceeded * the repeat-start. If so, log the repeat-start and the start * of the following read, and return because we're not writing * anymore (and TXD will be true because there's room to write * in the fifo). */ if (sc->sc_replen > 0 && sc->sc_resid == 0) { sc->sc_replen -= sc->sc_dlen; if (sc->sc_replen == 0) { DEBUGF(sc, 1, " err=0\n"); DEVICE_DEBUGF(sc, 2, "rstart 0x%02x\n", sc->sc_curmsg->slave | 0x01); DEVICE_DEBUGF(sc, 1, "read 0x%02x len %d: ", sc->sc_curmsg->slave | 0x01, sc->sc_totlen); sc->sc_flags |= BCM_I2C_READ; return; } } } while (sc->sc_totlen > 0 && (status & BCM_BSC_STATUS_TXD)); } static void bcm_bsc_intr(void *arg) { struct bcm_bsc_softc *sc; uint32_t status; sc = (struct bcm_bsc_softc *)arg; BCM_BSC_LOCK(sc); /* The I2C interrupt is shared among all the BSC controllers. */ if ((sc->sc_flags & BCM_I2C_BUSY) == 0) { BCM_BSC_UNLOCK(sc); return; } status = BCM_BSC_READ(sc, BCM_BSC_STATUS); DEBUGF(sc, 4, " ", status); /* RXD and DONE can assert together, empty fifo before checking done. */ if ((sc->sc_flags & BCM_I2C_READ) && (status & BCM_BSC_STATUS_RXD)) bcm_bsc_empty_rx_fifo(sc); /* Check for completion. */ if (status & (BCM_BSC_STATUS_ERRBITS | BCM_BSC_STATUS_DONE)) { sc->sc_flags |= BCM_I2C_DONE; if (status & BCM_BSC_STATUS_ERRBITS) sc->sc_flags |= BCM_I2C_ERROR; /* Disable interrupts. */ bcm_bsc_reset(sc); wakeup(sc); } else if (!(sc->sc_flags & BCM_I2C_READ)) { /* * Don't check for TXD until after determining whether the * transfer is complete; TXD will be asserted along with ERR or * DONE if there is room in the fifo. */ if ((status & BCM_BSC_STATUS_TXD) && sc->sc_totlen > 0) bcm_bsc_fill_tx_fifo(sc); } BCM_BSC_UNLOCK(sc); } static int bcm_bsc_transfer(device_t dev, struct iic_msg *msgs, uint32_t nmsgs) { struct bcm_bsc_softc *sc; struct iic_msg *endmsgs, *nxtmsg; uint32_t readctl, status; int err; uint16_t curlen; uint8_t curisread, curslave, nxtisread, nxtslave; sc = device_get_softc(dev); BCM_BSC_LOCK(sc); /* If the controller is busy wait until it is available. */ while (sc->sc_flags & BCM_I2C_BUSY) mtx_sleep(dev, &sc->sc_mtx, 0, "bscbusw", 0); /* Now we have control over the BSC controller. */ sc->sc_flags = BCM_I2C_BUSY; DEVICE_DEBUGF(sc, 3, "Transfer %d msgs\n", nmsgs); /* Clear the FIFO and the pending interrupts. */ bcm_bsc_reset(sc); /* * Perform all the transfers requested in the array of msgs. Note that * it is bcm_bsc_empty_rx_fifo() and bcm_bsc_fill_tx_fifo() that advance * sc->sc_curmsg through the array of messages, as the data from each * message is fully consumed, but it is this loop that notices when we * have no more messages to process. */ err = 0; sc->sc_resid = 0; sc->sc_curmsg = msgs; endmsgs = &msgs[nmsgs]; while (sc->sc_curmsg < endmsgs) { readctl = 0; curslave = sc->sc_curmsg->slave >> 1; curisread = sc->sc_curmsg->flags & IIC_M_RD; sc->sc_replen = 0; sc->sc_totlen = sc->sc_curmsg->len; /* * Scan for scatter/gather IO (same slave and direction) or * repeat-start (read following write for the same slave). */ for (nxtmsg = sc->sc_curmsg + 1; nxtmsg < endmsgs; ++nxtmsg) { nxtslave = nxtmsg->slave >> 1; if (curslave == nxtslave) { nxtisread = nxtmsg->flags & IIC_M_RD; if (curisread == nxtisread) { /* * Same slave and direction, this * message will be part of the same * transfer as the previous one. */ sc->sc_totlen += nxtmsg->len; continue; } else if (curisread == IIC_M_WR) { /* * Read after write to same slave means * repeat-start, remember how many bytes * come before the repeat-start, switch * the direction to IIC_M_RD, and gather * up following reads to the same slave. */ curisread = IIC_M_RD; sc->sc_replen = sc->sc_totlen; sc->sc_totlen += nxtmsg->len; continue; } } break; } /* * curslave and curisread temporaries from above may refer to * the after-repstart msg, reset them to reflect sc_curmsg. */ curisread = (sc->sc_curmsg->flags & IIC_M_RD) ? 1 : 0; curslave = sc->sc_curmsg->slave | curisread; /* Write the slave address. */ BCM_BSC_WRITE(sc, BCM_BSC_SLAVE, curslave >> 1); DEVICE_DEBUGF(sc, 2, "start 0x%02x\n", curslave); /* * Either set up read length and direction variables for a * simple transfer or get the hardware started on the first * piece of a transfer that involves a repeat-start and set up * the read length and direction vars for the second piece. */ if (sc->sc_replen == 0) { DEVICE_DEBUGF(sc, 1, "%-6s 0x%02x len %d: ", (curisread) ? "read" : "write", curslave, sc->sc_totlen); curlen = sc->sc_totlen; if (curisread) { readctl = BCM_BSC_CTRL_READ; sc->sc_flags |= BCM_I2C_READ; } else { readctl = 0; sc->sc_flags &= ~BCM_I2C_READ; } } else { DEVICE_DEBUGF(sc, 1, "%-6s 0x%02x len %d: ", (curisread) ? "read" : "write", curslave, sc->sc_replen); /* * Start the write transfer with an empty fifo and wait * for the 'transfer active' status bit to light up; * that indicates that the hardware has latched the * direction and length for the write, and we can safely * reload those registers and issue the start for the * following read; interrupts are not enabled here. */ BCM_BSC_WRITE(sc, BCM_BSC_DLEN, sc->sc_replen); BCM_BSC_WRITE(sc, BCM_BSC_CTRL, BCM_BSC_CTRL_I2CEN | BCM_BSC_CTRL_ST); do { status = BCM_BSC_READ(sc, BCM_BSC_STATUS); if (status & BCM_BSC_STATUS_ERR) { /* no ACK on slave addr */ err = EIO; goto xfer_done; } } while ((status & BCM_BSC_STATUS_TA) == 0); /* * Set curlen and readctl for the repeat-start read that * we need to set up below, but set sc_flags to write, * because that is the operation in progress right now. */ curlen = sc->sc_totlen - sc->sc_replen; readctl = BCM_BSC_CTRL_READ; sc->sc_flags &= ~BCM_I2C_READ; } /* * Start the transfer with interrupts enabled, then if doing a * write, fill the tx fifo. Not prefilling the fifo until after * this start command is the key workaround for making * repeat-start work, and it's harmless to do it in this order * for a regular write too. */ BCM_BSC_WRITE(sc, BCM_BSC_DLEN, curlen); BCM_BSC_WRITE(sc, BCM_BSC_CTRL, readctl | BCM_BSC_CTRL_I2CEN | BCM_BSC_CTRL_ST | BCM_BSC_CTRL_INT_ALL); if (!(sc->sc_curmsg->flags & IIC_M_RD)) { bcm_bsc_fill_tx_fifo(sc); } /* Wait for the transaction to complete. */ while (err == 0 && !(sc->sc_flags & BCM_I2C_DONE)) { err = mtx_sleep(sc, &sc->sc_mtx, 0, "bsciow", hz); } /* Check for errors. */ if (err == 0 && (sc->sc_flags & BCM_I2C_ERROR)) err = EIO; xfer_done: DEBUGF(sc, 1, " err=%d\n", err); DEVICE_DEBUGF(sc, 2, "stop\n"); if (err != 0) break; } /* Disable interrupts, clean fifo, etc. */ bcm_bsc_reset(sc); /* Clean the controller flags. */ sc->sc_flags = 0; /* Wake up the threads waiting for bus. */ wakeup(dev); BCM_BSC_UNLOCK(sc); return (err); } static int bcm_bsc_iicbus_reset(device_t dev, u_char speed, u_char addr, u_char *oldaddr) { struct bcm_bsc_softc *sc; uint32_t busfreq; sc = device_get_softc(dev); BCM_BSC_LOCK(sc); bcm_bsc_reset(sc); if (sc->sc_iicbus == NULL) busfreq = 100000; else busfreq = IICBUS_GET_FREQUENCY(sc->sc_iicbus, speed); BCM_BSC_WRITE(sc, BCM_BSC_CLOCK, BCM_BSC_CORE_CLK / busfreq); BCM_BSC_UNLOCK(sc); return (IIC_ENOADDR); } static phandle_t bcm_bsc_get_node(device_t bus, device_t dev) { /* We only have one child, the I2C bus, which needs our own node. */ return (ofw_bus_get_node(bus)); } static device_method_t bcm_bsc_methods[] = { /* Device interface */ DEVMETHOD(device_probe, bcm_bsc_probe), DEVMETHOD(device_attach, bcm_bsc_attach), DEVMETHOD(device_detach, bcm_bsc_detach), /* iicbus interface */ DEVMETHOD(iicbus_reset, bcm_bsc_iicbus_reset), DEVMETHOD(iicbus_callback, iicbus_null_callback), DEVMETHOD(iicbus_transfer, bcm_bsc_transfer), /* ofw_bus interface */ DEVMETHOD(ofw_bus_get_node, bcm_bsc_get_node), DEVMETHOD_END }; static devclass_t bcm_bsc_devclass; static driver_t bcm_bsc_driver = { "iichb", bcm_bsc_methods, sizeof(struct bcm_bsc_softc), }; DRIVER_MODULE(iicbus, bcm2835_bsc, iicbus_driver, iicbus_devclass, 0, 0); DRIVER_MODULE(bcm2835_bsc, simplebus, bcm_bsc_driver, bcm_bsc_devclass, 0, 0); Index: head/sys/arm/mv/a37x0_spi.c =================================================================== --- head/sys/arm/mv/a37x0_spi.c (revision 355734) +++ head/sys/arm/mv/a37x0_spi.c (revision 355735) @@ -1,496 +1,494 @@ /*- * Copyright (c) 2018, 2019 Rubicon Communications, LLC (Netgate) * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * */ #include __FBSDID("$FreeBSD$"); #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include "spibus_if.h" struct a37x0_spi_softc { device_t sc_dev; struct mtx sc_mtx; struct resource *sc_mem_res; struct resource *sc_irq_res; struct spi_command *sc_cmd; bus_space_tag_t sc_bst; bus_space_handle_t sc_bsh; uint32_t sc_len; uint32_t sc_maxfreq; uint32_t sc_read; uint32_t sc_flags; uint32_t sc_written; void *sc_intrhand; }; #define A37X0_SPI_WRITE(_sc, _off, _val) \ bus_space_write_4((_sc)->sc_bst, (_sc)->sc_bsh, (_off), (_val)) #define A37X0_SPI_READ(_sc, _off) \ bus_space_read_4((_sc)->sc_bst, (_sc)->sc_bsh, (_off)) #define A37X0_SPI_LOCK(_sc) mtx_lock(&(_sc)->sc_mtx) #define A37X0_SPI_UNLOCK(_sc) mtx_unlock(&(_sc)->sc_mtx) #define A37X0_SPI_BUSY (1 << 0) /* * While the A3700 utils from Marvell usually sets the QSF clock to 200MHz, * there is no guarantee that it is correct without the proper clock framework * to retrieve the actual TBG and PLL settings. */ #define A37X0_SPI_CLOCK 200000000 /* QSF Clock 200MHz */ #define A37X0_SPI_CONTROL 0x0 #define A37X0_SPI_CS_SHIFT 16 #define A37X0_SPI_CS_MASK (0xf << A37X0_SPI_CS_SHIFT) #define A37X0_SPI_CONF 0x4 #define A37X0_SPI_WFIFO_THRS_SHIFT 28 #define A37X0_SPI_RFIFO_THRS_SHIFT 24 #define A37X0_SPI_AUTO_CS_EN (1 << 20) #define A37X0_SPI_DMA_WR_EN (1 << 19) #define A37X0_SPI_DMA_RD_EN (1 << 18) #define A37X0_SPI_FIFO_MODE (1 << 17) #define A37X0_SPI_SRST (1 << 16) #define A37X0_SPI_XFER_START (1 << 15) #define A37X0_SPI_XFER_STOP (1 << 14) #define A37X0_SPI_INSTR_PIN (1 << 13) #define A37X0_SPI_ADDR_PIN (1 << 12) #define A37X0_SPI_DATA_PIN_MASK 0x3 #define A37X0_SPI_DATA_PIN_SHIFT 10 #define A37X0_SPI_FIFO_FLUSH (1 << 9) #define A37X0_SPI_RW_EN (1 << 8) #define A37X0_SPI_CLK_POL (1 << 7) #define A37X0_SPI_CLK_PHASE (1 << 6) #define A37X0_SPI_BYTE_LEN (1 << 5) #define A37X0_SPI_PSC_MASK 0x1f #define A37X0_SPI_DATA_OUT 0x8 #define A37X0_SPI_DATA_IN 0xc #define A37X0_SPI_INTR_STAT 0x28 #define A37X0_SPI_INTR_MASK 0x2c #define A37X0_SPI_RDY (1 << 1) #define A37X0_SPI_XFER_DONE (1 << 0) static struct ofw_compat_data compat_data[] = { { "marvell,armada-3700-spi", 1 }, { NULL, 0 } }; static void a37x0_spi_intr(void *); static int a37x0_spi_wait(struct a37x0_spi_softc *sc, int timeout, uint32_t reg, uint32_t mask) { int i; for (i = 0; i < timeout; i++) { if ((A37X0_SPI_READ(sc, reg) & mask) == 0) return (0); DELAY(100); } return (ETIMEDOUT); } static int a37x0_spi_probe(device_t dev) { if (!ofw_bus_status_okay(dev)) return (ENXIO); if (ofw_bus_search_compatible(dev, compat_data)->ocd_data == 0) return (ENXIO); device_set_desc(dev, "Armada 37x0 SPI controller"); return (BUS_PROBE_DEFAULT); } static int a37x0_spi_attach(device_t dev) { int err, rid; pcell_t maxfreq; struct a37x0_spi_softc *sc; uint32_t reg; sc = device_get_softc(dev); sc->sc_dev = dev; rid = 0; sc->sc_mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, RF_ACTIVE); if (!sc->sc_mem_res) { device_printf(dev, "cannot allocate memory window\n"); return (ENXIO); } sc->sc_bst = rman_get_bustag(sc->sc_mem_res); sc->sc_bsh = rman_get_bushandle(sc->sc_mem_res); rid = 0; sc->sc_irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, RF_ACTIVE); if (!sc->sc_irq_res) { bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->sc_mem_res); device_printf(dev, "cannot allocate interrupt\n"); return (ENXIO); } /* Make sure that no CS is asserted. */ reg = A37X0_SPI_READ(sc, A37X0_SPI_CONTROL); A37X0_SPI_WRITE(sc, A37X0_SPI_CONTROL, reg & ~A37X0_SPI_CS_MASK); /* Reset FIFO. */ reg = A37X0_SPI_READ(sc, A37X0_SPI_CONF); A37X0_SPI_WRITE(sc, A37X0_SPI_CONF, reg | A37X0_SPI_FIFO_FLUSH); err = a37x0_spi_wait(sc, 20, A37X0_SPI_CONF, A37X0_SPI_FIFO_FLUSH); if (err != 0) { bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sc_irq_res); bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->sc_mem_res); device_printf(dev, "cannot flush the controller fifo.\n"); return (ENXIO); } /* Reset the Controller. */ reg = A37X0_SPI_READ(sc, A37X0_SPI_CONF); A37X0_SPI_WRITE(sc, A37X0_SPI_CONF, reg | A37X0_SPI_SRST); DELAY(1000); /* Enable the single byte IO, disable FIFO. */ reg &= ~(A37X0_SPI_FIFO_MODE | A37X0_SPI_BYTE_LEN); A37X0_SPI_WRITE(sc, A37X0_SPI_CONF, reg); /* Disable and clear interrupts. */ A37X0_SPI_WRITE(sc, A37X0_SPI_INTR_MASK, 0); reg = A37X0_SPI_READ(sc, A37X0_SPI_INTR_STAT); A37X0_SPI_WRITE(sc, A37X0_SPI_INTR_STAT, reg); /* Hook up our interrupt handler. */ if (bus_setup_intr(dev, sc->sc_irq_res, INTR_TYPE_MISC | INTR_MPSAFE, NULL, a37x0_spi_intr, sc, &sc->sc_intrhand)) { bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sc_irq_res); bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->sc_mem_res); device_printf(dev, "cannot setup the interrupt handler\n"); return (ENXIO); } mtx_init(&sc->sc_mtx, "a37x0_spi", NULL, MTX_DEF); /* Read the controller max-frequency. */ if (OF_getencprop(ofw_bus_get_node(dev), "spi-max-frequency", &maxfreq, sizeof(maxfreq)) == -1) maxfreq = 0; sc->sc_maxfreq = maxfreq; device_add_child(dev, "spibus", -1); /* Probe and attach the spibus when interrupts are available. */ - bus_delayed_attach_children(dev); - - return (0); + return (bus_delayed_attach_children(dev)); } static int a37x0_spi_detach(device_t dev) { int err; struct a37x0_spi_softc *sc; if ((err = device_delete_children(dev)) != 0) return (err); sc = device_get_softc(dev); mtx_destroy(&sc->sc_mtx); if (sc->sc_intrhand) bus_teardown_intr(dev, sc->sc_irq_res, sc->sc_intrhand); if (sc->sc_irq_res) bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sc_irq_res); if (sc->sc_mem_res) bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->sc_mem_res); return (0); } static __inline void a37x0_spi_rx_byte(struct a37x0_spi_softc *sc) { struct spi_command *cmd; uint32_t read; uint8_t *p; if (sc->sc_read == sc->sc_len) return; cmd = sc->sc_cmd; p = (uint8_t *)cmd->rx_cmd; read = sc->sc_read++; if (read >= cmd->rx_cmd_sz) { p = (uint8_t *)cmd->rx_data; read -= cmd->rx_cmd_sz; } p[read] = A37X0_SPI_READ(sc, A37X0_SPI_DATA_IN) & 0xff; } static __inline void a37x0_spi_tx_byte(struct a37x0_spi_softc *sc) { struct spi_command *cmd; uint32_t written; uint8_t *p; if (sc->sc_written == sc->sc_len) return; cmd = sc->sc_cmd; p = (uint8_t *)cmd->tx_cmd; written = sc->sc_written++; if (written >= cmd->tx_cmd_sz) { p = (uint8_t *)cmd->tx_data; written -= cmd->tx_cmd_sz; } A37X0_SPI_WRITE(sc, A37X0_SPI_DATA_OUT, p[written]); } static __inline void a37x0_spi_set_clock(struct a37x0_spi_softc *sc, uint32_t clock) { uint32_t psc, reg; if (sc->sc_maxfreq > 0 && clock > sc->sc_maxfreq) clock = sc->sc_maxfreq; psc = A37X0_SPI_CLOCK / clock; if ((A37X0_SPI_CLOCK % clock) > 0) psc++; reg = A37X0_SPI_READ(sc, A37X0_SPI_CONF); reg &= ~A37X0_SPI_PSC_MASK; reg |= psc & A37X0_SPI_PSC_MASK; A37X0_SPI_WRITE(sc, A37X0_SPI_CONF, reg); } static __inline void a37x0_spi_set_pins(struct a37x0_spi_softc *sc, uint32_t npins) { uint32_t reg; /* Sets single, dual or quad SPI mode. */ reg = A37X0_SPI_READ(sc, A37X0_SPI_CONF); reg &= ~(A37X0_SPI_DATA_PIN_MASK << A37X0_SPI_DATA_PIN_SHIFT); reg |= (npins / 2) << A37X0_SPI_DATA_PIN_SHIFT; reg |= A37X0_SPI_INSTR_PIN | A37X0_SPI_ADDR_PIN; A37X0_SPI_WRITE(sc, A37X0_SPI_CONF, reg); } static __inline void a37x0_spi_set_mode(struct a37x0_spi_softc *sc, uint32_t mode) { uint32_t reg; reg = A37X0_SPI_READ(sc, A37X0_SPI_CONF); switch (mode) { case 0: reg &= ~(A37X0_SPI_CLK_PHASE | A37X0_SPI_CLK_POL); break; case 1: reg &= ~A37X0_SPI_CLK_POL; reg |= A37X0_SPI_CLK_PHASE; break; case 2: reg &= ~A37X0_SPI_CLK_PHASE; reg |= A37X0_SPI_CLK_POL; break; case 3: reg |= (A37X0_SPI_CLK_PHASE | A37X0_SPI_CLK_POL); break; } A37X0_SPI_WRITE(sc, A37X0_SPI_CONF, reg); } static void a37x0_spi_intr(void *arg) { struct a37x0_spi_softc *sc; uint32_t status; sc = (struct a37x0_spi_softc *)arg; A37X0_SPI_LOCK(sc); /* Filter stray interrupts. */ if ((sc->sc_flags & A37X0_SPI_BUSY) == 0) { A37X0_SPI_UNLOCK(sc); return; } status = A37X0_SPI_READ(sc, A37X0_SPI_INTR_STAT); if (status & A37X0_SPI_XFER_DONE) a37x0_spi_rx_byte(sc); /* Clear the interrupt status. */ A37X0_SPI_WRITE(sc, A37X0_SPI_INTR_STAT, status); /* Check for end of transfer. */ if (sc->sc_written == sc->sc_len && sc->sc_read == sc->sc_len) wakeup(sc->sc_dev); else a37x0_spi_tx_byte(sc); A37X0_SPI_UNLOCK(sc); } static int a37x0_spi_transfer(device_t dev, device_t child, struct spi_command *cmd) { int timeout; struct a37x0_spi_softc *sc; uint32_t clock, cs, mode, reg; KASSERT(cmd->tx_cmd_sz == cmd->rx_cmd_sz, ("TX/RX command sizes should be equal")); KASSERT(cmd->tx_data_sz == cmd->rx_data_sz, ("TX/RX data sizes should be equal")); /* Get the proper data for this child. */ spibus_get_cs(child, &cs); cs &= ~SPIBUS_CS_HIGH; if (cs > 3) { device_printf(dev, "Invalid CS %d requested by %s\n", cs, device_get_nameunit(child)); return (EINVAL); } spibus_get_clock(child, &clock); if (clock == 0) { device_printf(dev, "Invalid clock %uHz requested by %s\n", clock, device_get_nameunit(child)); return (EINVAL); } spibus_get_mode(child, &mode); if (mode > 3) { device_printf(dev, "Invalid mode %u requested by %s\n", mode, device_get_nameunit(child)); return (EINVAL); } sc = device_get_softc(dev); A37X0_SPI_LOCK(sc); /* Wait until the controller is free. */ while (sc->sc_flags & A37X0_SPI_BUSY) mtx_sleep(dev, &sc->sc_mtx, 0, "a37x0_spi", 0); /* Now we have control over SPI controller. */ sc->sc_flags = A37X0_SPI_BUSY; /* Set transfer mode and clock. */ a37x0_spi_set_mode(sc, mode); a37x0_spi_set_pins(sc, 1); a37x0_spi_set_clock(sc, clock); /* Set CS. */ A37X0_SPI_WRITE(sc, A37X0_SPI_CONTROL, 1 << (A37X0_SPI_CS_SHIFT + cs)); /* Save a pointer to the SPI command. */ sc->sc_cmd = cmd; sc->sc_read = 0; sc->sc_written = 0; sc->sc_len = cmd->tx_cmd_sz + cmd->tx_data_sz; /* Clear interrupts. */ reg = A37X0_SPI_READ(sc, A37X0_SPI_INTR_STAT); A37X0_SPI_WRITE(sc, A37X0_SPI_INTR_STAT, reg); while ((sc->sc_len - sc->sc_written) > 0) { /* * Write to start the transmission and read the byte * back when ready. */ a37x0_spi_tx_byte(sc); timeout = 1000; while (--timeout > 0) { reg = A37X0_SPI_READ(sc, A37X0_SPI_CONTROL); if (reg & A37X0_SPI_XFER_DONE) break; DELAY(1); } if (timeout == 0) break; a37x0_spi_rx_byte(sc); } /* Stop the controller. */ reg = A37X0_SPI_READ(sc, A37X0_SPI_CONTROL); A37X0_SPI_WRITE(sc, A37X0_SPI_CONTROL, reg & ~A37X0_SPI_CS_MASK); A37X0_SPI_WRITE(sc, A37X0_SPI_INTR_MASK, 0); /* Release the controller and wakeup the next thread waiting for it. */ sc->sc_flags = 0; wakeup_one(dev); A37X0_SPI_UNLOCK(sc); return ((timeout == 0) ? EIO : 0); } static phandle_t a37x0_spi_get_node(device_t bus, device_t dev) { return (ofw_bus_get_node(bus)); } static device_method_t a37x0_spi_methods[] = { /* Device interface */ DEVMETHOD(device_probe, a37x0_spi_probe), DEVMETHOD(device_attach, a37x0_spi_attach), DEVMETHOD(device_detach, a37x0_spi_detach), /* SPI interface */ DEVMETHOD(spibus_transfer, a37x0_spi_transfer), /* ofw_bus interface */ DEVMETHOD(ofw_bus_get_node, a37x0_spi_get_node), DEVMETHOD_END }; static devclass_t a37x0_spi_devclass; static driver_t a37x0_spi_driver = { "spi", a37x0_spi_methods, sizeof(struct a37x0_spi_softc), }; DRIVER_MODULE(a37x0_spi, simplebus, a37x0_spi_driver, a37x0_spi_devclass, 0, 0); Index: head/sys/dev/ow/owc_gpiobus.c =================================================================== --- head/sys/dev/ow/owc_gpiobus.c (revision 355734) +++ head/sys/dev/ow/owc_gpiobus.c (revision 355735) @@ -1,421 +1,419 @@ /*- * Copyright (c) 2015 M. Warner Losh * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. */ #include __FBSDID("$FreeBSD$"); #include "opt_platform.h" #include #include #include #include #include #include #include #include #include #ifdef FDT #include #include #include #endif #include #include "gpiobus_if.h" #include #define OW_PIN 0 #define OWC_GPIOBUS_LOCK(_sc) mtx_lock(&(_sc)->sc_mtx) #define OWC_GPIOBUS_UNLOCK(_sc) mtx_unlock(&(_sc)->sc_mtx) #define OWC_GPIOBUS_LOCK_INIT(_sc) \ mtx_init(&_sc->sc_mtx, device_get_nameunit(_sc->sc_dev), \ "owc_gpiobus", MTX_DEF) #define OWC_GPIOBUS_LOCK_DESTROY(_sc) mtx_destroy(&_sc->sc_mtx); struct owc_gpiobus_softc { device_t sc_dev; device_t sc_busdev; struct mtx sc_mtx; }; static int owc_gpiobus_probe(device_t); static int owc_gpiobus_attach(device_t); static int owc_gpiobus_detach(device_t); #ifdef FDT static void owc_gpiobus_identify(driver_t *driver, device_t bus) { phandle_t w1, root; /* * Find all the 1-wire bus pseudo-nodes that are * at the top level of the FDT. Would be nice to * somehow preserve the node name of these busses, * but there's no good place to put it. The driver's * name is used for the device name, and the 1-wire * bus overwrites the description. */ root = OF_finddevice("/"); if (root == -1) return; for (w1 = OF_child(root); w1 != 0; w1 = OF_peer(w1)) { if (!fdt_is_compatible_strict(w1, "w1-gpio")) continue; if (!OF_hasprop(w1, "gpios")) continue; ofw_gpiobus_add_fdt_child(bus, driver->name, w1); } } #endif static int owc_gpiobus_probe(device_t dev) { #ifdef FDT if (!ofw_bus_status_okay(dev)) return (ENXIO); if (ofw_bus_is_compatible(dev, "w1-gpio")) { device_set_desc(dev, "FDT GPIO attached one-wire bus"); return (BUS_PROBE_DEFAULT); } return (ENXIO); #else device_set_desc(dev, "GPIO attached one-wire bus"); return 0; #endif } static int owc_gpiobus_attach(device_t dev) { struct owc_gpiobus_softc *sc; device_t *kids; int nkid; sc = device_get_softc(dev); sc->sc_dev = dev; sc->sc_busdev = device_get_parent(dev); OWC_GPIOBUS_LOCK_INIT(sc); nkid = 0; if (device_get_children(dev, &kids, &nkid) == 0) free(kids, M_TEMP); if (nkid == 0) device_add_child(dev, "ow", -1); - bus_delayed_attach_children(dev); - - return (0); + return (bus_delayed_attach_children(dev)); } static int owc_gpiobus_detach(device_t dev) { struct owc_gpiobus_softc *sc; sc = device_get_softc(dev); OWC_GPIOBUS_LOCK_DESTROY(sc); bus_generic_detach(dev); return (0); } /* * In the diagrams below, R is driven by the resistor pullup, M is driven by the * master, and S is driven by the slave / target. */ /* * These macros let what why we're doing stuff shine in the code * below, and let the how be confined to here. */ #define GETBUS(sc) GPIOBUS_ACQUIRE_BUS((sc)->sc_busdev, \ (sc)->sc_dev, GPIOBUS_WAIT) #define RELBUS(sc) GPIOBUS_RELEASE_BUS((sc)->sc_busdev, \ (sc)->sc_dev) #define OUTPIN(sc) GPIOBUS_PIN_SETFLAGS((sc)->sc_busdev, \ (sc)->sc_dev, OW_PIN, GPIO_PIN_OUTPUT) #define INPIN(sc) GPIOBUS_PIN_SETFLAGS((sc)->sc_busdev, \ (sc)->sc_dev, OW_PIN, GPIO_PIN_INPUT) #define GETPIN(sc, bit) GPIOBUS_PIN_GET((sc)->sc_busdev, \ (sc)->sc_dev, OW_PIN, bit) #define LOW(sc) GPIOBUS_PIN_SET((sc)->sc_busdev, \ (sc)->sc_dev, OW_PIN, GPIO_PIN_LOW) /* * WRITE-ONE (see owll_if.m for timings) From Figure 4-1 AN-937 * * |<---------tSLOT---->|<-tREC->| * High RRRRM | RRRRRRRRRRRR|RRRRRRRRM * M | R | | | M * M| R | | | M * Low MMMMMMM | | | MMMMMM... * |<-tLOW1->| | | * |<------15us--->| | * |<--------60us---->| */ static int owc_gpiobus_write_one(device_t dev, struct ow_timing *t) { struct owc_gpiobus_softc *sc; int error; sc = device_get_softc(dev); error = GETBUS(sc); if (error != 0) return (error); critical_enter(); /* Force low */ OUTPIN(sc); LOW(sc); DELAY(t->t_low1); /* Allow resistor to float line high */ INPIN(sc); DELAY(t->t_slot - t->t_low1 + t->t_rec); critical_exit(); RELBUS(sc); return (0); } /* * WRITE-ZERO (see owll_if.m for timings) From Figure 4-2 AN-937 * * |<---------tSLOT------>|<-tREC->| * High RRRRM | | |RRRRRRRM * M | | R M * M| | | |R M * Low MMMMMMMMMMMMMMMMMMMMMR MMMMMM... * |<--15us->| | | * |<------60us--->| | * |<-------tLOW0------>| */ static int owc_gpiobus_write_zero(device_t dev, struct ow_timing *t) { struct owc_gpiobus_softc *sc; int error; sc = device_get_softc(dev); error = GETBUS(sc); if (error != 0) return (error); critical_enter(); /* Force low */ OUTPIN(sc); LOW(sc); DELAY(t->t_low0); /* Allow resistor to float line high */ INPIN(sc); DELAY(t->t_slot - t->t_low0 + t->t_rec); critical_exit(); RELBUS(sc); return (0); } /* * READ-DATA (see owll_if.m for timings) From Figure 4-3 AN-937 * * |<---------tSLOT------>|<-tREC->| * High RRRRM | rrrrrrrrrrrrrrrRRRRRRRM * M | r | R M * M| r | |R M * Low MMMMMMMSSSSSSSSSSSSSSR MMMMMM... * |< sample > | * |<------tRDV---->| | * ->| |<-tRELEASE * * r -- allowed to pull high via the resitor when slave writes a 1-bit * */ static int owc_gpiobus_read_data(device_t dev, struct ow_timing *t, int *bit) { struct owc_gpiobus_softc *sc; int error, sample; sbintime_t then, now; sc = device_get_softc(dev); error = GETBUS(sc); if (error != 0) return (error); critical_enter(); /* Force low for t_lowr microseconds */ then = sbinuptime(); OUTPIN(sc); LOW(sc); DELAY(t->t_lowr); /* * Slave is supposed to hold the line low for t_rdv microseconds for 0 * and immediately float it high for a 1. This is measured from the * master's pushing the line low. */ INPIN(sc); do { now = sbinuptime(); GETPIN(sc, &sample); } while (now - then < (t->t_rdv + 2) * SBT_1US && sample == 0); critical_exit(); if (now - then < t->t_rdv * SBT_1US) *bit = 1; else *bit = 0; /* Wait out the rest of t_slot */ do { now = sbinuptime(); } while (now - then < (t->t_slot + t->t_rec) * SBT_1US); RELBUS(sc); return (error); } /* * RESET AND PRESENCE PULSE (see owll_if.m for timings) From Figure 4-4 AN-937 * * |<---------tRSTH------------>| * High RRRM | | RRRRRRRS | RRRR RRM * M | |R| |S | R M * M| R | | S |R M * Low MMMMMMMM MMMMMM| | | SSSSSSSSSS MMMMMM * |<----tRSTL--->| | |<-tPDL---->| * | ->| |<-tR | | * || * * Note: for Regular Speed operations, tRSTL + tR should be less than 960us to * avoid interferring with other devices on the bus */ static int owc_gpiobus_reset_and_presence(device_t dev, struct ow_timing *t, int *bit) { struct owc_gpiobus_softc *sc; int error; int buf = -1; sc = device_get_softc(dev); error = GETBUS(sc); if (error != 0) return (error); /* * Read the current state of the bus. The steady state of an idle bus is * high. Badly wired buses that are missing the required pull up, or * that have a short circuit to ground cause all kinds of mischief when * we try to read them later. Return EIO and release the bus if the bus * is currently low. */ INPIN(sc); GETPIN(sc, &buf); if (buf == 0) { *bit = -1; RELBUS(sc); return (EIO); } critical_enter(); /* Force low */ OUTPIN(sc); LOW(sc); DELAY(t->t_rstl); /* Allow resistor to float line high and then wait for reset pulse */ INPIN(sc); DELAY(t->t_pdh + t->t_pdl / 2); /* Read presence pulse */ GETPIN(sc, &buf); *bit = !!buf; critical_exit(); DELAY(t->t_rsth - (t->t_pdh + t->t_pdl / 2)); /* Timing not critical for this one */ /* * Read the state of the bus after we've waited past the end of the rest * window. It should return to high. If it is low, then we have some * problem and should abort the reset. */ GETPIN(sc, &buf); if (buf == 0) { *bit = -1; RELBUS(sc); return (EIO); } RELBUS(sc); return (0); } static devclass_t owc_gpiobus_devclass; static device_method_t owc_gpiobus_methods[] = { /* Device interface */ #ifdef FDT DEVMETHOD(device_identify, owc_gpiobus_identify), #endif DEVMETHOD(device_probe, owc_gpiobus_probe), DEVMETHOD(device_attach, owc_gpiobus_attach), DEVMETHOD(device_detach, owc_gpiobus_detach), DEVMETHOD(owll_write_one, owc_gpiobus_write_one), DEVMETHOD(owll_write_zero, owc_gpiobus_write_zero), DEVMETHOD(owll_read_data, owc_gpiobus_read_data), DEVMETHOD(owll_reset_and_presence, owc_gpiobus_reset_and_presence), { 0, 0 } }; static driver_t owc_gpiobus_driver = { "owc", owc_gpiobus_methods, sizeof(struct owc_gpiobus_softc), }; DRIVER_MODULE(owc_gpiobus, gpiobus, owc_gpiobus_driver, owc_gpiobus_devclass, 0, 0); MODULE_DEPEND(owc_gpiobus, ow, 1, 1, 1); MODULE_DEPEND(owc_gpiobus, gpiobus, 1, 1, 1); MODULE_VERSION(owc_gpiobus, 1);