Index: stable/12/sys/arm64/rockchip/clk/rk3328_cru.c =================================================================== --- stable/12/sys/arm64/rockchip/clk/rk3328_cru.c (revision 355175) +++ stable/12/sys/arm64/rockchip/clk/rk3328_cru.c (revision 355176) @@ -1,1103 +1,1106 @@ /*- * SPDX-License-Identifier: BSD-2-Clause-FreeBSD * * Copyright (c) 2018 Emmanuel Vadot * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. * * $FreeBSD$ */ #include __FBSDID("$FreeBSD$"); #include #include #include #include #include #include #include #include #include #include #include #include #include #include /* GATES */ #define ACLK_PERI 153 #define PCLK_GPIO0 200 #define PCLK_GPIO1 201 #define PCLK_GPIO2 202 #define PCLK_GPIO3 203 #define PCLK_I2C0 205 #define PCLK_I2C1 206 #define PCLK_I2C2 207 #define PCLK_I2C3 208 #define HCLK_SDMMC 317 #define HCLK_SDIO 318 #define HCLK_EMMC 319 #define HCLK_SDMMC_EXT 320 static struct rk_cru_gate rk3328_gates[] = { /* CRU_CLKGATE_CON0 */ CRU_GATE(0, "apll_core", "apll", 0x200, 0) CRU_GATE(0, "dpll_core", "dpll", 0x200, 1) CRU_GATE(0, "gpll_core", "gpll", 0x200, 2) CRU_GATE(0, "npll_core", "npll", 0x200, 12) /* CRU_CLKGATE_CON4 */ CRU_GATE(0, "gpll_peri", "gpll", 0x210, 0) CRU_GATE(0, "cpll_peri", "cpll", 0x210, 1) /* CRU_CLKGATE_CON8 */ CRU_GATE(0, "pclk_bus", "pclk_bus_pre", 0x220, 3) CRU_GATE(0, "pclk_phy_pre", "pclk_bus_pre", 0x220, 4) /* CRU_CLKGATE_CON10 */ CRU_GATE(ACLK_PERI, "aclk_peri", "aclk_peri_pre", 0x228, 0) /* CRU_CLKGATE_CON15*/ CRU_GATE(PCLK_I2C0, "pclk_i2c0", "pclk_bus", 0x23C, 10) /* CRU_CLKGATE_CON16 */ CRU_GATE(PCLK_I2C1, "pclk_i2c1", "pclk_bus", 0x23C, 0) CRU_GATE(PCLK_I2C2, "pclk_i2c2", "pclk_bus", 0x23C, 1) CRU_GATE(PCLK_I2C3, "pclk_i2c3", "pclk_bus", 0x23C, 2) CRU_GATE(PCLK_GPIO0, "pclk_gpio0", "pclk_bus", 0x240, 7) CRU_GATE(PCLK_GPIO1, "pclk_gpio1", "pclk_bus", 0x240, 8) CRU_GATE(PCLK_GPIO2, "pclk_gpio2", "pclk_bus", 0x240, 9) CRU_GATE(PCLK_GPIO3, "pclk_gpio3", "pclk_bus", 0x240, 10) /* CRU_CLKGATE_CON19 */ CRU_GATE(HCLK_SDMMC, "hclk_sdmmc", "hclk_peri", 0x24C, 0) CRU_GATE(HCLK_SDIO, "hclk_sdio", "hclk_peri", 0x24C, 1) CRU_GATE(HCLK_EMMC, "hclk_emmc", "hclk_peri", 0x24C, 2) CRU_GATE(HCLK_SDMMC_EXT, "hclk_sdmmc_ext", "hclk_peri", 0x24C, 15) }; /* * PLLs */ #define PLL_APLL 1 #define PLL_DPLL 2 #define PLL_CPLL 3 #define PLL_GPLL 4 #define PLL_NPLL 5 static struct rk_clk_pll_rate rk3328_pll_rates[] = { { .freq = 1608000000, .refdiv = 1, .fbdiv = 67, .postdiv1 = 1, .postdiv2 = 1, .dsmpd = 1, }, { .freq = 1584000000, .refdiv = 1, .fbdiv = 66, .postdiv1 = 1, .postdiv2 = 1, .dsmpd = 1, }, { .freq = 1560000000, .refdiv = 1, .fbdiv = 65, .postdiv1 = 1, .postdiv2 = 1, .dsmpd = 1, }, { .freq = 1536000000, .refdiv = 1, .fbdiv = 64, .postdiv1 = 1, .postdiv2 = 1, .dsmpd = 1, }, { .freq = 1512000000, .refdiv = 1, .fbdiv = 63, .postdiv1 = 1, .postdiv2 = 1, .dsmpd = 1, }, { .freq = 1488000000, .refdiv = 1, .fbdiv = 62, .postdiv1 = 1, .postdiv2 = 1, .dsmpd = 1, }, { .freq = 1464000000, .refdiv = 1, .fbdiv = 61, .postdiv1 = 1, .postdiv2 = 1, .dsmpd = 1, }, { .freq = 1440000000, .refdiv = 1, .fbdiv = 60, .postdiv1 = 1, .postdiv2 = 1, .dsmpd = 1, }, { .freq = 1416000000, .refdiv = 1, .fbdiv = 59, .postdiv1 = 1, .postdiv2 = 1, .dsmpd = 1, }, { .freq = 1392000000, .refdiv = 1, .fbdiv = 58, .postdiv1 = 1, .postdiv2 = 1, .dsmpd = 1, }, { .freq = 1368000000, .refdiv = 1, .fbdiv = 57, .postdiv1 = 1, .postdiv2 = 1, .dsmpd = 1, }, { .freq = 1344000000, .refdiv = 1, .fbdiv = 56, .postdiv1 = 1, .postdiv2 = 1, .dsmpd = 1, }, { .freq = 1320000000, .refdiv = 1, .fbdiv = 55, .postdiv1 = 1, .postdiv2 = 1, .dsmpd = 1, }, { .freq = 1296000000, .refdiv = 1, .fbdiv = 54, .postdiv1 = 1, .postdiv2 = 1, .dsmpd = 1, }, { .freq = 1272000000, .refdiv = 1, .fbdiv = 53, .postdiv1 = 1, .postdiv2 = 1, .dsmpd = 1, }, { .freq = 1248000000, .refdiv = 1, .fbdiv = 52, .postdiv1 = 1, .postdiv2 = 1, .dsmpd = 1, }, { .freq = 1200000000, .refdiv = 1, .fbdiv = 50, .postdiv1 = 1, .postdiv2 = 1, .dsmpd = 1, }, { .freq = 1188000000, .refdiv = 2, .fbdiv = 99, .postdiv1 = 1, .postdiv2 = 1, .dsmpd = 1, }, { .freq = 1104000000, .refdiv = 1, .fbdiv = 46, .postdiv1 = 1, .postdiv2 = 1, .dsmpd = 1, }, { .freq = 1100000000, .refdiv = 12, .fbdiv = 550, .postdiv1 = 1, .postdiv2 = 1, .dsmpd = 1, }, { .freq = 1008000000, .refdiv = 1, .fbdiv = 84, .postdiv1 = 2, .postdiv2 = 1, .dsmpd = 1, }, { .freq = 1000000000, .refdiv = 6, .fbdiv = 500, .postdiv1 = 2, .postdiv2 = 1, .dsmpd = 1, }, { .freq = 984000000, .refdiv = 1, .fbdiv = 82, .postdiv1 = 2, .postdiv2 = 1, .dsmpd = 1, }, { .freq = 960000000, .refdiv = 1, .fbdiv = 80, .postdiv1 = 2, .postdiv2 = 1, .dsmpd = 1, }, { .freq = 936000000, .refdiv = 1, .fbdiv = 78, .postdiv1 = 2, .postdiv2 = 1, .dsmpd = 1, }, { .freq = 912000000, .refdiv = 1, .fbdiv = 76, .postdiv1 = 2, .postdiv2 = 1, .dsmpd = 1, }, { .freq = 900000000, .refdiv = 4, .fbdiv = 300, .postdiv1 = 2, .postdiv2 = 1, .dsmpd = 1, }, { .freq = 888000000, .refdiv = 1, .fbdiv = 74, .postdiv1 = 2, .postdiv2 = 1, .dsmpd = 1, }, { .freq = 864000000, .refdiv = 1, .fbdiv = 72, .postdiv1 = 2, .postdiv2 = 1, .dsmpd = 1, }, { .freq = 840000000, .refdiv = 1, .fbdiv = 70, .postdiv1 = 2, .postdiv2 = 1, .dsmpd = 1, }, { .freq = 816000000, .refdiv = 1, .fbdiv = 68, .postdiv1 = 2, .postdiv2 = 1, .dsmpd = 1, }, { .freq = 800000000, .refdiv = 6, .fbdiv = 400, .postdiv1 = 2, .postdiv2 = 1, .dsmpd = 1, }, { .freq = 700000000, .refdiv = 6, .fbdiv = 350, .postdiv1 = 2, .postdiv2 = 1, .dsmpd = 1, }, { .freq = 696000000, .refdiv = 1, .fbdiv = 58, .postdiv1 = 2, .postdiv2 = 1, .dsmpd = 1, }, { .freq = 600000000, .refdiv = 1, .fbdiv = 75, .postdiv1 = 3, .postdiv2 = 1, .dsmpd = 1, }, { .freq = 594000000, .refdiv = 2, .fbdiv = 99, .postdiv1 = 2, .postdiv2 = 1, .dsmpd = 1, }, { .freq = 504000000, .refdiv = 1, .fbdiv = 63, .postdiv1 = 3, .postdiv2 = 1, .dsmpd = 1, }, { .freq = 500000000, .refdiv = 6, .fbdiv = 250, .postdiv1 = 2, .postdiv2 = 1, .dsmpd = 1, }, { .freq = 408000000, .refdiv = 1, .fbdiv = 68, .postdiv1 = 2, .postdiv2 = 2, .dsmpd = 1, }, { .freq = 312000000, .refdiv = 1, .fbdiv = 52, .postdiv1 = 2, .postdiv2 = 2, .dsmpd = 1, }, { .freq = 216000000, .refdiv = 1, .fbdiv = 72, .postdiv1 = 4, .postdiv2 = 2, .dsmpd = 1, }, { .freq = 96000000, .refdiv = 1, .fbdiv = 64, .postdiv1 = 4, .postdiv2 = 4, .dsmpd = 1, }, {}, }; static struct rk_clk_pll_rate rk3328_pll_frac_rates[] = { { .freq = 1016064000, .refdiv = 3, .fbdiv = 127, .postdiv1 = 1, .postdiv2 = 1, .dsmpd = 0, .frac = 134217, }, { .freq = 983040000, .refdiv = 24, .fbdiv = 983, .postdiv1 = 1, .postdiv2 = 1, .dsmpd = 0, .frac = 671088, }, { .freq = 491520000, .refdiv = 24, .fbdiv = 983, .postdiv1 = 2, .postdiv2 = 1, .dsmpd = 0, .frac = 671088, }, { .freq = 61440000, .refdiv = 6, .fbdiv = 215, .postdiv1 = 7, .postdiv2 = 2, .dsmpd = 0, .frac = 671088, }, { .freq = 56448000, .refdiv = 12, .fbdiv = 451, .postdiv1 = 4, .postdiv2 = 4, .dsmpd = 0, .frac = 9797894, }, { .freq = 40960000, .refdiv = 12, .fbdiv = 409, .postdiv1 = 4, .postdiv2 = 5, .dsmpd = 0, .frac = 10066329, }, {}, }; static const char *pll_parents[] = {"xin24m"}; static struct rk_clk_pll_def apll = { .clkdef = { .id = PLL_APLL, .name = "apll", .parent_names = pll_parents, .parent_cnt = nitems(pll_parents), }, .base_offset = 0x00, .gate_offset = 0x200, .gate_shift = 0, .mode_reg = 0x80, .mode_shift = 1, .flags = RK_CLK_PLL_HAVE_GATE, .frac_rates = rk3328_pll_frac_rates, }; static struct rk_clk_pll_def dpll = { .clkdef = { .id = PLL_DPLL, .name = "dpll", .parent_names = pll_parents, .parent_cnt = nitems(pll_parents), }, .base_offset = 0x20, .gate_offset = 0x200, .gate_shift = 1, .mode_reg = 0x80, .mode_shift = 4, .flags = RK_CLK_PLL_HAVE_GATE, }; static struct rk_clk_pll_def cpll = { .clkdef = { .id = PLL_CPLL, .name = "cpll", .parent_names = pll_parents, .parent_cnt = nitems(pll_parents), }, .base_offset = 0x40, .mode_reg = 0x80, .mode_shift = 8, .rates = rk3328_pll_rates, }; static struct rk_clk_pll_def gpll = { .clkdef = { .id = PLL_GPLL, .name = "gpll", .parent_names = pll_parents, .parent_cnt = nitems(pll_parents), }, .base_offset = 0x60, .gate_offset = 0x200, .gate_shift = 2, .mode_reg = 0x80, .mode_shift = 12, .flags = RK_CLK_PLL_HAVE_GATE, .frac_rates = rk3328_pll_frac_rates, }; static struct rk_clk_pll_def npll = { .clkdef = { .id = PLL_NPLL, .name = "npll", .parent_names = pll_parents, .parent_cnt = nitems(pll_parents), }, .base_offset = 0xa0, .gate_offset = 0x200, .gate_shift = 12, .mode_reg = 0x80, .mode_shift = 1, .flags = RK_CLK_PLL_HAVE_GATE, .rates = rk3328_pll_rates, }; /* CRU_CLKSEL_CON0 */ #define ACLK_BUS_PRE 136 /* Needs hdmiphy as parent too*/ static const char *aclk_bus_pre_parents[] = {"cpll", "gpll"}; static struct rk_clk_composite_def aclk_bus_pre = { .clkdef = { .id = ACLK_BUS_PRE, .name = "aclk_bus_pre", .parent_names = aclk_bus_pre_parents, .parent_cnt = nitems(aclk_bus_pre_parents), }, .muxdiv_offset = 0x100, .mux_shift = 13, .mux_width = 2, .div_shift = 8, .div_width = 5, .gate_offset = 0x220, .gate_shift = 0, .flags = RK_CLK_COMPOSITE_HAVE_MUX | RK_CLK_COMPOSITE_HAVE_GATE, }; static struct rk_clk_armclk_rates rk3328_armclk_rates[] = { { .freq = 1296000000, .div = 1, }, { .freq = 1200000000, .div = 1, }, { .freq = 1104000000, .div = 1, }, { .freq = 1008000000, .div = 1, }, { .freq = 912000000, .div = 1, }, { .freq = 816000000, .div = 1, }, { .freq = 696000000, .div = 1, }, { .freq = 600000000, .div = 1, }, { .freq = 408000000, .div = 1, }, { .freq = 312000000, .div = 1, }, { .freq = 216000000, .div = 1, }, { .freq = 96000000, .div = 1, }, }; #define ARMCLK 6 static const char *armclk_parents[] = {"apll", "gpll", "dpll", "npll" }; static struct rk_clk_armclk_def armclk = { .clkdef = { .id = ARMCLK, .name = "armclk", .parent_names = armclk_parents, .parent_cnt = nitems(armclk_parents), }, .muxdiv_offset = 0x100, .mux_shift = 6, .mux_width = 2, .div_shift = 0, .div_width = 5, .flags = RK_CLK_COMPOSITE_HAVE_MUX, .main_parent = 3, /* npll */ .alt_parent = 0, /* apll */ .rates = rk3328_armclk_rates, .nrates = nitems(rk3328_armclk_rates), }; /* CRU_CLKSEL_CON1 */ #define PCLK_BUS_PRE 216 #define HCLK_BUS_PRE 328 static const char *hclk_bus_pre_parents[] = {"aclk_bus_pre"}; static struct rk_clk_composite_def hclk_bus_pre = { .clkdef = { .id = HCLK_BUS_PRE, .name = "hclk_bus_pre", .parent_names = hclk_bus_pre_parents, .parent_cnt = nitems(hclk_bus_pre_parents), }, .muxdiv_offset = 0x104, .div_shift = 8, .div_width = 2, .gate_offset = 0x220, .gate_shift = 1, .flags = RK_CLK_COMPOSITE_HAVE_GATE, }; static const char *pclk_bus_pre_parents[] = {"aclk_bus_pre"}; static struct rk_clk_composite_def pclk_bus_pre = { .clkdef = { .id = PCLK_BUS_PRE, .name = "pclk_bus_pre", .parent_names = pclk_bus_pre_parents, .parent_cnt = nitems(pclk_bus_pre_parents), }, .muxdiv_offset = 0x104, .div_shift = 12, .div_width = 3, .gate_offset = 0x220, .gate_shift = 2, .flags = RK_CLK_COMPOSITE_HAVE_GATE, }; /* CRU_CLKSEL_CON28 */ #define ACLK_PERI_PRE 137 static const char *aclk_peri_pre_parents[] = {"cpll", "gpll"/* , "hdmiphy" */}; static struct rk_clk_composite_def aclk_peri_pre = { .clkdef = { .id = ACLK_PERI_PRE, .name = "aclk_peri_pre", .parent_names = aclk_peri_pre_parents, .parent_cnt = nitems(aclk_peri_pre_parents), }, .muxdiv_offset = 0x170, .mux_shift = 6, .mux_width = 2, .div_shift = 0, .div_width = 5, .flags = RK_CLK_COMPOSITE_HAVE_MUX, }; /* CRU_CLKSEL_CON29 */ #define PCLK_PERI 230 #define HCLK_PERI 308 static const char *phclk_peri_parents[] = {"aclk_peri_pre"}; static struct rk_clk_composite_def pclk_peri = { .clkdef = { .id = PCLK_PERI, .name = "pclk_peri", .parent_names = phclk_peri_parents, .parent_cnt = nitems(phclk_peri_parents), }, .div_shift = 0, .div_width = 2, /* CRU_CLKGATE_CON10 */ .gate_offset = 0x228, .gate_shift = 2, .flags = RK_CLK_COMPOSITE_HAVE_GATE, }; static struct rk_clk_composite_def hclk_peri = { .clkdef = { .id = HCLK_PERI, .name = "hclk_peri", .parent_names = phclk_peri_parents, .parent_cnt = nitems(phclk_peri_parents), }, .div_shift = 4, .div_width = 3, /* CRU_CLKGATE_CON10 */ .gate_offset = 0x228, .gate_shift = 1, .flags = RK_CLK_COMPOSITE_HAVE_GATE, }; /* CRU_CLKSEL_CON30 */ #define SCLK_SDMMC 33 static const char *mmc_parents[] = {"cpll", "gpll", "xin24m"/* , "usb480m" */}; static struct rk_clk_composite_def sdmmc = { .clkdef = { .id = SCLK_SDMMC, .name = "clk_sdmmc", .parent_names = mmc_parents, .parent_cnt = nitems(mmc_parents), }, .muxdiv_offset = 0x178, .mux_shift = 8, .mux_width = 2, .div_shift = 0, .div_width = 8, /* CRU_CLKGATE_CON4 */ .gate_offset = 0x210, .gate_shift = 3, .flags = RK_CLK_COMPOSITE_HAVE_MUX | RK_CLK_COMPOSITE_HAVE_GATE, }; /* CRU_CLKSEL_CON31 */ #define SCLK_SDIO 34 static struct rk_clk_composite_def sdio = { .clkdef = { .id = SCLK_SDIO, .name = "clk_sdio", .parent_names = mmc_parents, .parent_cnt = nitems(mmc_parents), }, .muxdiv_offset = 0x17C, .mux_shift = 8, .mux_width = 2, .div_shift = 0, .div_width = 8, /* CRU_CLKGATE_CON4 */ .gate_offset = 0x210, .gate_shift = 4, .flags = RK_CLK_COMPOSITE_HAVE_MUX | RK_CLK_COMPOSITE_HAVE_GATE, }; /* CRU_CLKSEL_CON32 */ #define SCLK_EMMC 35 static struct rk_clk_composite_def emmc = { .clkdef = { .id = SCLK_EMMC, .name = "clk_emmc", .parent_names = mmc_parents, .parent_cnt = nitems(mmc_parents), }, .muxdiv_offset = 0x180, .mux_shift = 8, .mux_width = 2, .div_shift = 0, .div_width = 8, /* CRU_CLKGATE_CON4 */ .gate_offset = 0x210, .gate_shift = 5, .flags = RK_CLK_COMPOSITE_HAVE_MUX | RK_CLK_COMPOSITE_HAVE_GATE, }; /* CRU_CLKSEL_CON34 */ #define SCLK_I2C0 55 #define SCLK_I2C1 56 static const char *i2c_parents[] = {"cpll", "gpll"}; static struct rk_clk_composite_def i2c0 = { .clkdef = { .id = SCLK_I2C0, .name = "clk_i2c0", .parent_names = i2c_parents, .parent_cnt = nitems(i2c_parents), }, .muxdiv_offset = 0x188, .mux_shift = 7, .mux_width = 1, .div_shift = 0, .div_width = 6, /* CRU_CLKGATE_CON2 */ .gate_offset = 0x208, .gate_shift = 9, .flags = RK_CLK_COMPOSITE_HAVE_MUX | RK_CLK_COMPOSITE_HAVE_GATE, }; static struct rk_clk_composite_def i2c1 = { .clkdef = { .id = SCLK_I2C1, .name = "clk_i2c1", .parent_names = i2c_parents, .parent_cnt = nitems(i2c_parents), }, .muxdiv_offset = 0x188, .mux_shift = 15, .mux_width = 1, .div_shift = 8, .div_width = 6, /* CRU_CLKGATE_CON2 */ .gate_offset = 0x208, .gate_shift = 10, .flags = RK_CLK_COMPOSITE_HAVE_MUX | RK_CLK_COMPOSITE_HAVE_GATE, }; /* CRU_CLKSEL_CON35 */ #define SCLK_I2C2 57 #define SCLK_I2C3 58 static struct rk_clk_composite_def i2c2 = { .clkdef = { .id = SCLK_I2C2, .name = "clk_i2c2", .parent_names = i2c_parents, .parent_cnt = nitems(i2c_parents), }, .muxdiv_offset = 0x18C, .mux_shift = 7, .mux_width = 1, .div_shift = 0, .div_width = 6, /* CRU_CLKGATE_CON2 */ .gate_offset = 0x208, .gate_shift = 11, .flags = RK_CLK_COMPOSITE_HAVE_MUX | RK_CLK_COMPOSITE_HAVE_GATE, }; static struct rk_clk_composite_def i2c3 = { .clkdef = { .id = SCLK_I2C3, .name = "clk_i2c3", .parent_names = i2c_parents, .parent_cnt = nitems(i2c_parents), }, .muxdiv_offset = 0x18C, .mux_shift = 15, .mux_width = 1, .div_shift = 8, .div_width = 6, /* CRU_CLKGATE_CON2 */ .gate_offset = 0x208, .gate_shift = 12, .flags = RK_CLK_COMPOSITE_HAVE_MUX | RK_CLK_COMPOSITE_HAVE_GATE, }; static struct rk_clk rk3328_clks[] = { { .type = RK3328_CLK_PLL, .clk.pll = &apll }, { .type = RK3328_CLK_PLL, .clk.pll = &dpll }, { .type = RK3328_CLK_PLL, .clk.pll = &cpll }, { .type = RK3328_CLK_PLL, .clk.pll = &gpll }, { .type = RK3328_CLK_PLL, .clk.pll = &npll }, { .type = RK_CLK_COMPOSITE, .clk.composite = &aclk_bus_pre }, { .type = RK_CLK_COMPOSITE, .clk.composite = &hclk_bus_pre }, { .type = RK_CLK_COMPOSITE, .clk.composite = &pclk_bus_pre }, { .type = RK_CLK_ARMCLK, .clk.armclk = &armclk, }, { .type = RK_CLK_COMPOSITE, .clk.composite = &aclk_peri_pre, }, { .type = RK_CLK_COMPOSITE, .clk.composite = &pclk_peri, }, { .type = RK_CLK_COMPOSITE, .clk.composite = &hclk_peri, }, { .type = RK_CLK_COMPOSITE, .clk.composite = &sdmmc }, { .type = RK_CLK_COMPOSITE, .clk.composite = &sdio }, { .type = RK_CLK_COMPOSITE, .clk.composite = &emmc }, { .type = RK_CLK_COMPOSITE, .clk.composite = &i2c0 }, { .type = RK_CLK_COMPOSITE, .clk.composite = &i2c1 }, { .type = RK_CLK_COMPOSITE, .clk.composite = &i2c2 }, { .type = RK_CLK_COMPOSITE, .clk.composite = &i2c3 }, }; static int rk3328_cru_probe(device_t dev) { if (!ofw_bus_status_okay(dev)) return (ENXIO); if (ofw_bus_is_compatible(dev, "rockchip,rk3328-cru")) { device_set_desc(dev, "Rockchip RK3328 Clock and Reset Unit"); return (BUS_PROBE_DEFAULT); } return (ENXIO); } static int rk3328_cru_attach(device_t dev) { struct rk_cru_softc *sc; sc = device_get_softc(dev); sc->dev = dev; sc->gates = rk3328_gates; sc->ngates = nitems(rk3328_gates); sc->clks = rk3328_clks; sc->nclks = nitems(rk3328_clks); + sc->reset_offset = 0x300; + sc->reset_num = 184; + return (rk_cru_attach(dev)); } static device_method_t rk3328_cru_methods[] = { /* Device interface */ DEVMETHOD(device_probe, rk3328_cru_probe), DEVMETHOD(device_attach, rk3328_cru_attach), DEVMETHOD_END }; static devclass_t rk3328_cru_devclass; DEFINE_CLASS_1(rk3328_cru, rk3328_cru_driver, rk3328_cru_methods, sizeof(struct rk_cru_softc), rk_cru_driver); EARLY_DRIVER_MODULE(rk3328_cru, simplebus, rk3328_cru_driver, rk3328_cru_devclass, 0, 0, BUS_PASS_BUS + BUS_PASS_ORDER_MIDDLE); Index: stable/12/sys/arm64/rockchip/clk/rk3399_cru.c =================================================================== --- stable/12/sys/arm64/rockchip/clk/rk3399_cru.c (revision 355175) +++ stable/12/sys/arm64/rockchip/clk/rk3399_cru.c (revision 355176) @@ -1,1604 +1,1696 @@ /*- * SPDX-License-Identifier: BSD-2-Clause-FreeBSD * * Copyright (c) 2018 Emmanuel Vadot * Copyright (c) 2018 Greg V * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. * * $FreeBSD$ */ #include __FBSDID("$FreeBSD$"); #include #include #include #include #include #include #include #include #include #include #include #include #include #include /* GATES */ +#define SCLK_USB2PHY0_REF 123 +#define SCLK_USB2PHY1_REF 124 +#define ACLK_EMMC_CORE 241 +#define ACLK_EMMC_NOC 242 +#define ACLK_EMMC_GRF 243 #define PCLK_GPIO2 336 #define PCLK_GPIO3 337 #define PCLK_GPIO4 338 #define PCLK_I2C1 341 #define PCLK_I2C2 342 #define PCLK_I2C3 343 #define PCLK_I2C5 344 #define PCLK_I2C6 345 #define PCLK_I2C7 346 +#define HCLK_HOST0 456 +#define HCLK_HOST0_ARB 457 +#define HCLK_HOST1 458 +#define HCLK_HOST1_ARB 459 #define HCLK_SDMMC 462 static struct rk_cru_gate rk3399_gates[] = { /* CRU_CLKGATE_CON0 */ CRU_GATE(0, "clk_core_l_lpll_src", "lpll", 0x300, 0) CRU_GATE(0, "clk_core_l_bpll_src", "bpll", 0x300, 1) CRU_GATE(0, "clk_core_l_dpll_src", "dpll", 0x300, 2) CRU_GATE(0, "clk_core_l_gpll_src", "gpll", 0x300, 3) /* CRU_CLKGATE_CON1 */ CRU_GATE(0, "clk_core_b_lpll_src", "lpll", 0x304, 0) CRU_GATE(0, "clk_core_b_bpll_src", "bpll", 0x304, 1) CRU_GATE(0, "clk_core_b_dpll_src", "dpll", 0x304, 2) CRU_GATE(0, "clk_core_b_gpll_src", "gpll", 0x304, 3) /* CRU_CLKGATE_CON5 */ CRU_GATE(0, "cpll_aclk_perihp_src", "cpll", 0x314, 0) CRU_GATE(0, "gpll_aclk_perihp_src", "gpll", 0x314, 1) + /* CRU_CLKGATE_CON6 */ + CRU_GATE(0, "gpll_aclk_emmc_src", "gpll", 0x318, 12) + CRU_GATE(0, "cpll_aclk_emmc_src", "cpll", 0x318, 13) + CRU_GATE(SCLK_USB2PHY0_REF, "clk_usb2phy0_ref", "xin24m", 0x318, 5) + CRU_GATE(SCLK_USB2PHY1_REF, "clk_usb2phy1_ref", "xin24m", 0x318, 6) + /* CRU_CLKGATE_CON7 */ CRU_GATE(0, "gpll_aclk_perilp0_src", "gpll", 0x31C, 0) CRU_GATE(0, "cpll_aclk_perilp0_src", "cpll", 0x31C, 1) /* CRU_CLKGATE_CON8 */ CRU_GATE(0, "hclk_perilp1_cpll_src", "cpll", 0x320, 1) CRU_GATE(0, "hclk_perilp1_gpll_src", "gpll", 0x320, 0) + /* CRU_CLKGATE_CON20 */ + CRU_GATE(HCLK_HOST0, "hclk_host0", "hclk_perihp", 0x350, 5) + CRU_GATE(HCLK_HOST0_ARB, "hclk_host0_arb", "hclk_perihp", 0x350, 6) + CRU_GATE(HCLK_HOST1, "hclk_host1", "hclk_perihp", 0x350, 7) + CRU_GATE(HCLK_HOST1_ARB, "hclk_host1_arb", "hclk_perihp", 0x350, 8) + /* CRU_CLKGATE_CON22 */ CRU_GATE(PCLK_I2C7, "pclk_rki2c7", "pclk_perilp1", 0x358, 5) CRU_GATE(PCLK_I2C1, "pclk_rki2c1", "pclk_perilp1", 0x358, 6) CRU_GATE(PCLK_I2C5, "pclk_rki2c5", "pclk_perilp1", 0x358, 7) CRU_GATE(PCLK_I2C6, "pclk_rki2c6", "pclk_perilp1", 0x358, 8) CRU_GATE(PCLK_I2C2, "pclk_rki2c2", "pclk_perilp1", 0x358, 9) CRU_GATE(PCLK_I2C3, "pclk_rki2c3", "pclk_perilp1", 0x358, 10) /* CRU_CLKGATE_CON31 */ CRU_GATE(PCLK_GPIO2, "pclk_gpio2", "pclk_alive", 0x37c, 3) CRU_GATE(PCLK_GPIO3, "pclk_gpio3", "pclk_alive", 0x37c, 4) CRU_GATE(PCLK_GPIO4, "pclk_gpio4", "pclk_alive", 0x37c, 5) + /* CRU_CLKGATE_CON32 */ + CRU_GATE(ACLK_EMMC_CORE, "aclk_emmccore", "aclk_emmc", 0x380, 8) + CRU_GATE(ACLK_EMMC_NOC, "aclk_emmc_noc", "aclk_emmc", 0x380, 9) + CRU_GATE(ACLK_EMMC_GRF, "aclk_emmcgrf", "aclk_emmc", 0x380, 10) + /* CRU_CLKGATE_CON33 */ CRU_GATE(HCLK_SDMMC, "hclk_sdmmc", "hclk_sd", 0x384, 8) }; /* * PLLs */ #define PLL_APLLL 1 #define PLL_APLLB 2 #define PLL_DPLL 3 #define PLL_CPLL 4 #define PLL_GPLL 5 #define PLL_NPLL 6 #define PLL_VPLL 7 static struct rk_clk_pll_rate rk3399_pll_rates[] = { { .freq = 2208000000, .refdiv = 1, .fbdiv = 92, .postdiv1 = 1, .postdiv2 = 1, .dsmpd = 1, }, { .freq = 2184000000, .refdiv = 1, .fbdiv = 91, .postdiv1 = 1, .postdiv2 = 1, .dsmpd = 1, }, { .freq = 2160000000, .refdiv = 1, .fbdiv = 90, .postdiv1 = 1, .postdiv2 = 1, .dsmpd = 1, }, { .freq = 2136000000, .refdiv = 1, .fbdiv = 89, .postdiv1 = 1, .postdiv2 = 1, .dsmpd = 1, }, { .freq = 2112000000, .refdiv = 1, .fbdiv = 88, .postdiv1 = 1, .postdiv2 = 1, .dsmpd = 1, }, { .freq = 2088000000, .refdiv = 1, .fbdiv = 87, .postdiv1 = 1, .postdiv2 = 1, .dsmpd = 1, }, { .freq = 2064000000, .refdiv = 1, .fbdiv = 86, .postdiv1 = 1, .postdiv2 = 1, .dsmpd = 1, }, { .freq = 2040000000, .refdiv = 1, .fbdiv = 85, .postdiv1 = 1, .postdiv2 = 1, .dsmpd = 1, }, { .freq = 2016000000, .refdiv = 1, .fbdiv = 84, .postdiv1 = 1, .postdiv2 = 1, .dsmpd = 1, }, { .freq = 1992000000, .refdiv = 1, .fbdiv = 83, .postdiv1 = 1, .postdiv2 = 1, .dsmpd = 1, }, { .freq = 1968000000, .refdiv = 1, .fbdiv = 82, .postdiv1 = 1, .postdiv2 = 1, .dsmpd = 1, }, { .freq = 1944000000, .refdiv = 1, .fbdiv = 81, .postdiv1 = 1, .postdiv2 = 1, .dsmpd = 1, }, { .freq = 1920000000, .refdiv = 1, .fbdiv = 80, .postdiv1 = 1, .postdiv2 = 1, .dsmpd = 1, }, { .freq = 1896000000, .refdiv = 1, .fbdiv = 79, .postdiv1 = 1, .postdiv2 = 1, .dsmpd = 1, }, { .freq = 1872000000, .refdiv = 1, .fbdiv = 78, .postdiv1 = 1, .postdiv2 = 1, .dsmpd = 1, }, { .freq = 1848000000, .refdiv = 1, .fbdiv = 77, .postdiv1 = 1, .postdiv2 = 1, .dsmpd = 1, }, { .freq = 1824000000, .refdiv = 1, .fbdiv = 76, .postdiv1 = 1, .postdiv2 = 1, .dsmpd = 1, }, { .freq = 1800000000, .refdiv = 1, .fbdiv = 75, .postdiv1 = 1, .postdiv2 = 1, .dsmpd = 1, }, { .freq = 1776000000, .refdiv = 1, .fbdiv = 74, .postdiv1 = 1, .postdiv2 = 1, .dsmpd = 1, }, { .freq = 1752000000, .refdiv = 1, .fbdiv = 73, .postdiv1 = 1, .postdiv2 = 1, .dsmpd = 1, }, { .freq = 1728000000, .refdiv = 1, .fbdiv = 72, .postdiv1 = 1, .postdiv2 = 1, .dsmpd = 1, }, { .freq = 1704000000, .refdiv = 1, .fbdiv = 71, .postdiv1 = 1, .postdiv2 = 1, .dsmpd = 1, }, { .freq = 1680000000, .refdiv = 1, .fbdiv = 70, .postdiv1 = 1, .postdiv2 = 1, .dsmpd = 1, }, { .freq = 1656000000, .refdiv = 1, .fbdiv = 69, .postdiv1 = 1, .postdiv2 = 1, .dsmpd = 1, }, { .freq = 1632000000, .refdiv = 1, .fbdiv = 68, .postdiv1 = 1, .postdiv2 = 1, .dsmpd = 1, }, { .freq = 1608000000, .refdiv = 1, .fbdiv = 67, .postdiv1 = 1, .postdiv2 = 1, .dsmpd = 1, }, { .freq = 1600000000, .refdiv = 3, .fbdiv = 200, .postdiv1 = 1, .postdiv2 = 1, .dsmpd = 1, }, { .freq = 1584000000, .refdiv = 1, .fbdiv = 66, .postdiv1 = 1, .postdiv2 = 1, .dsmpd = 1, }, { .freq = 1560000000, .refdiv = 1, .fbdiv = 65, .postdiv1 = 1, .postdiv2 = 1, .dsmpd = 1, }, { .freq = 1536000000, .refdiv = 1, .fbdiv = 64, .postdiv1 = 1, .postdiv2 = 1, .dsmpd = 1, }, { .freq = 1512000000, .refdiv = 1, .fbdiv = 63, .postdiv1 = 1, .postdiv2 = 1, .dsmpd = 1, }, { .freq = 1488000000, .refdiv = 1, .fbdiv = 62, .postdiv1 = 1, .postdiv2 = 1, .dsmpd = 1, }, { .freq = 1464000000, .refdiv = 1, .fbdiv = 61, .postdiv1 = 1, .postdiv2 = 1, .dsmpd = 1, }, { .freq = 1440000000, .refdiv = 1, .fbdiv = 60, .postdiv1 = 1, .postdiv2 = 1, .dsmpd = 1, }, { .freq = 1416000000, .refdiv = 1, .fbdiv = 59, .postdiv1 = 1, .postdiv2 = 1, .dsmpd = 1, }, { .freq = 1392000000, .refdiv = 1, .fbdiv = 58, .postdiv1 = 1, .postdiv2 = 1, .dsmpd = 1, }, { .freq = 1368000000, .refdiv = 1, .fbdiv = 57, .postdiv1 = 1, .postdiv2 = 1, .dsmpd = 1, }, { .freq = 1344000000, .refdiv = 1, .fbdiv = 56, .postdiv1 = 1, .postdiv2 = 1, .dsmpd = 1, }, { .freq = 1320000000, .refdiv = 1, .fbdiv = 55, .postdiv1 = 1, .postdiv2 = 1, .dsmpd = 1, }, { .freq = 1296000000, .refdiv = 1, .fbdiv = 54, .postdiv1 = 1, .postdiv2 = 1, .dsmpd = 1, }, { .freq = 1272000000, .refdiv = 1, .fbdiv = 53, .postdiv1 = 1, .postdiv2 = 1, .dsmpd = 1, }, { .freq = 1248000000, .refdiv = 1, .fbdiv = 52, .postdiv1 = 1, .postdiv2 = 1, .dsmpd = 1, }, { .freq = 1200000000, .refdiv = 1, .fbdiv = 50, .postdiv1 = 1, .postdiv2 = 1, .dsmpd = 1, }, { .freq = 1188000000, .refdiv = 2, .fbdiv = 99, .postdiv1 = 1, .postdiv2 = 1, .dsmpd = 1, }, { .freq = 1104000000, .refdiv = 1, .fbdiv = 46, .postdiv1 = 1, .postdiv2 = 1, .dsmpd = 1, }, { .freq = 1100000000, .refdiv = 12, .fbdiv = 550, .postdiv1 = 1, .postdiv2 = 1, .dsmpd = 1, }, { .freq = 1008000000, .refdiv = 1, .fbdiv = 84, .postdiv1 = 2, .postdiv2 = 1, .dsmpd = 1, }, { .freq = 1000000000, .refdiv = 1, .fbdiv = 125, .postdiv1 = 3, .postdiv2 = 1, .dsmpd = 1, }, { .freq = 984000000, .refdiv = 1, .fbdiv = 82, .postdiv1 = 2, .postdiv2 = 1, .dsmpd = 1, }, { .freq = 960000000, .refdiv = 1, .fbdiv = 80, .postdiv1 = 2, .postdiv2 = 1, .dsmpd = 1, }, { .freq = 936000000, .refdiv = 1, .fbdiv = 78, .postdiv1 = 2, .postdiv2 = 1, .dsmpd = 1, }, { .freq = 912000000, .refdiv = 1, .fbdiv = 76, .postdiv1 = 2, .postdiv2 = 1, .dsmpd = 1, }, { .freq = 900000000, .refdiv = 4, .fbdiv = 300, .postdiv1 = 2, .postdiv2 = 1, .dsmpd = 1, }, { .freq = 888000000, .refdiv = 1, .fbdiv = 74, .postdiv1 = 2, .postdiv2 = 1, .dsmpd = 1, }, { .freq = 864000000, .refdiv = 1, .fbdiv = 72, .postdiv1 = 2, .postdiv2 = 1, .dsmpd = 1, }, { .freq = 840000000, .refdiv = 1, .fbdiv = 70, .postdiv1 = 2, .postdiv2 = 1, .dsmpd = 1, }, { .freq = 816000000, .refdiv = 1, .fbdiv = 68, .postdiv1 = 2, .postdiv2 = 1, .dsmpd = 1, }, { .freq = 800000000, .refdiv = 1, .fbdiv = 100, .postdiv1 = 3, .postdiv2 = 1, .dsmpd = 1, }, { .freq = 700000000, .refdiv = 6, .fbdiv = 350, .postdiv1 = 2, .postdiv2 = 1, .dsmpd = 1, }, { .freq = 696000000, .refdiv = 1, .fbdiv = 58, .postdiv1 = 2, .postdiv2 = 1, .dsmpd = 1, }, { .freq = 676000000, .refdiv = 3, .fbdiv = 169, .postdiv1 = 2, .postdiv2 = 1, .dsmpd = 1, }, { .freq = 600000000, .refdiv = 1, .fbdiv = 75, .postdiv1 = 3, .postdiv2 = 1, .dsmpd = 1, }, { .freq = 594000000, .refdiv = 1, .fbdiv = 99, .postdiv1 = 4, .postdiv2 = 1, .dsmpd = 1, }, { .freq = 533250000, .refdiv = 8, .fbdiv = 711, .postdiv1 = 4, .postdiv2 = 1, .dsmpd = 1, }, { .freq = 504000000, .refdiv = 1, .fbdiv = 63, .postdiv1 = 3, .postdiv2 = 1, .dsmpd = 1, }, { .freq = 500000000, .refdiv = 6, .fbdiv = 250, .postdiv1 = 2, .postdiv2 = 1, .dsmpd = 1, }, { .freq = 408000000, .refdiv = 1, .fbdiv = 68, .postdiv1 = 2, .postdiv2 = 2, .dsmpd = 1, }, { .freq = 312000000, .refdiv = 1, .fbdiv = 52, .postdiv1 = 2, .postdiv2 = 2, .dsmpd = 1, }, { .freq = 297000000, .refdiv = 1, .fbdiv = 99, .postdiv1 = 4, .postdiv2 = 2, .dsmpd = 1, }, { .freq = 216000000, .refdiv = 1, .fbdiv = 72, .postdiv1 = 4, .postdiv2 = 2, .dsmpd = 1, }, { .freq = 148500000, .refdiv = 1, .fbdiv = 99, .postdiv1 = 4, .postdiv2 = 4, .dsmpd = 1, }, { .freq = 106500000, .refdiv = 1, .fbdiv = 71, .postdiv1 = 4, .postdiv2 = 4, .dsmpd = 1, }, { .freq = 96000000, .refdiv = 1, .fbdiv = 64, .postdiv1 = 4, .postdiv2 = 4, .dsmpd = 1, }, { .freq = 74250000, .refdiv = 2, .fbdiv = 99, .postdiv1 = 4, .postdiv2 = 4, .dsmpd = 1, }, { .freq = 65000000, .refdiv = 1, .fbdiv = 65, .postdiv1 = 6, .postdiv2 = 4, .dsmpd = 1, }, { .freq = 54000000, .refdiv = 1, .fbdiv = 54, .postdiv1 = 6, .postdiv2 = 4, .dsmpd = 1, }, { .freq = 27000000, .refdiv = 1, .fbdiv = 27, .postdiv1 = 6, .postdiv2 = 4, .dsmpd = 1, }, {}, }; static const char *pll_parents[] = {"xin24m"}; static struct rk_clk_pll_def lpll = { .clkdef = { .id = PLL_APLLL, .name = "lpll", .parent_names = pll_parents, .parent_cnt = nitems(pll_parents), }, .base_offset = 0x00, .gate_offset = 0x300, .gate_shift = 0, .flags = RK_CLK_PLL_HAVE_GATE, .rates = rk3399_pll_rates, .normal_mode = true, }; static struct rk_clk_pll_def bpll = { .clkdef = { .id = PLL_APLLB, .name = "bpll", .parent_names = pll_parents, .parent_cnt = nitems(pll_parents), }, .base_offset = 0x20, .gate_offset = 0x300, .gate_shift = 1, .flags = RK_CLK_PLL_HAVE_GATE, .rates = rk3399_pll_rates, .normal_mode = true, }; static struct rk_clk_pll_def dpll = { .clkdef = { .id = PLL_DPLL, .name = "dpll", .parent_names = pll_parents, .parent_cnt = nitems(pll_parents), }, .base_offset = 0x40, .gate_offset = 0x300, .gate_shift = 2, .flags = RK_CLK_PLL_HAVE_GATE, .rates = rk3399_pll_rates, }; static struct rk_clk_pll_def cpll = { .clkdef = { .id = PLL_CPLL, .name = "cpll", .parent_names = pll_parents, .parent_cnt = nitems(pll_parents), }, .base_offset = 0x60, .rates = rk3399_pll_rates, }; static struct rk_clk_pll_def gpll = { .clkdef = { .id = PLL_GPLL, .name = "gpll", .parent_names = pll_parents, .parent_cnt = nitems(pll_parents), }, .base_offset = 0x80, .gate_offset = 0x300, .gate_shift = 3, .flags = RK_CLK_PLL_HAVE_GATE, .rates = rk3399_pll_rates, }; static struct rk_clk_pll_def npll = { .clkdef = { .id = PLL_NPLL, .name = "npll", .parent_names = pll_parents, .parent_cnt = nitems(pll_parents), }, .base_offset = 0xa0, .rates = rk3399_pll_rates, }; static struct rk_clk_pll_def vpll = { .clkdef = { .id = PLL_VPLL, .name = "vpll", .parent_names = pll_parents, .parent_cnt = nitems(pll_parents), }, .base_offset = 0xc0, .rates = rk3399_pll_rates, }; #define ACLK_PERIHP 192 #define HCLK_PERIHP 448 #define PCLK_PERIHP 320 static const char *aclk_perihp_parents[] = {"cpll_aclk_perihp_src", "gpll_aclk_perihp_src"}; static struct rk_clk_composite_def aclk_perihp = { .clkdef = { .id = ACLK_PERIHP, .name = "aclk_perihp", .parent_names = aclk_perihp_parents, .parent_cnt = nitems(aclk_perihp_parents), }, /* CRU_CLKSEL_CON14 */ .muxdiv_offset = 0x138, .mux_shift = 7, .mux_width = 1, .div_shift = 0, .div_width = 5, /* CRU_CLKGATE_CON5 */ .gate_offset = 0x314, .gate_shift = 2, .flags = RK_CLK_COMPOSITE_HAVE_MUX | RK_CLK_COMPOSITE_HAVE_GATE, }; static const char *hclk_pclk_perihp_parents[] = {"aclk_perihp"}; static struct rk_clk_composite_def hclk_perihp = { .clkdef = { .id = HCLK_PERIHP, .name = "hclk_perihp", .parent_names = hclk_pclk_perihp_parents, .parent_cnt = nitems(hclk_pclk_perihp_parents), }, /* CRU_CLKSEL_CON14 */ .muxdiv_offset = 0x138, .div_shift = 8, .div_width = 2, /* CRU_CLKGATE_CON5 */ .gate_offset = 0x314, .gate_shift = 3, .flags = RK_CLK_COMPOSITE_HAVE_MUX | RK_CLK_COMPOSITE_HAVE_GATE, }; static struct rk_clk_composite_def pclk_perihp = { .clkdef = { .id = PCLK_PERIHP, .name = "pclk_perihp", .parent_names = hclk_pclk_perihp_parents, .parent_cnt = nitems(hclk_pclk_perihp_parents), }, /* CRU_CLKSEL_CON14 */ .muxdiv_offset = 0x138, .div_shift = 12, .div_width = 3, /* CRU_CLKGATE_CON5 */ .gate_offset = 0x314, .gate_shift = 4, .flags = RK_CLK_COMPOSITE_HAVE_MUX | RK_CLK_COMPOSITE_HAVE_GATE, }; #define ACLK_PERILP0 194 #define HCLK_PERILP0 449 #define PCLK_PERILP0 322 static const char *aclk_perilp0_parents[] = {"cpll_aclk_perilp0_src", "gpll_aclk_perilp0_src"}; static struct rk_clk_composite_def aclk_perilp0 = { .clkdef = { .id = ACLK_PERILP0, .name = "aclk_perilp0", .parent_names = aclk_perilp0_parents, .parent_cnt = nitems(aclk_perilp0_parents), }, /* CRU_CLKSEL_CON14 */ .muxdiv_offset = 0x15C, .mux_shift = 7, .mux_width = 1, .div_shift = 0, .div_width = 5, /* CRU_CLKGATE_CON7 */ .gate_offset = 0x31C, .gate_shift = 2, .flags = RK_CLK_COMPOSITE_HAVE_MUX | RK_CLK_COMPOSITE_HAVE_GATE, }; static const char *hclk_pclk_perilp0_parents[] = {"aclk_perilp0"}; static struct rk_clk_composite_def hclk_perilp0 = { .clkdef = { .id = HCLK_PERILP0, .name = "hclk_perilp0", .parent_names = hclk_pclk_perilp0_parents, .parent_cnt = nitems(hclk_pclk_perilp0_parents), }, /* CRU_CLKSEL_CON23 */ .muxdiv_offset = 0x15C, .div_shift = 8, .div_width = 2, /* CRU_CLKGATE_CON7 */ .gate_offset = 0x31C, .gate_shift = 3, .flags = RK_CLK_COMPOSITE_HAVE_MUX | RK_CLK_COMPOSITE_HAVE_GATE, }; static struct rk_clk_composite_def pclk_perilp0 = { .clkdef = { .id = PCLK_PERILP0, .name = "pclk_perilp0", .parent_names = hclk_pclk_perilp0_parents, .parent_cnt = nitems(hclk_pclk_perilp0_parents), }, /* CRU_CLKSEL_CON23 */ .muxdiv_offset = 0x15C, .div_shift = 12, .div_width = 3, /* CRU_CLKGATE_CON7 */ .gate_offset = 0x31C, .gate_shift = 4, .flags = RK_CLK_COMPOSITE_HAVE_MUX | RK_CLK_COMPOSITE_HAVE_GATE, }; /* * misc */ #define PCLK_ALIVE 390 static const char *alive_parents[] = {"gpll"}; static struct rk_clk_composite_def pclk_alive = { .clkdef = { .id = PCLK_ALIVE, .name = "pclk_alive", .parent_names = alive_parents, .parent_cnt = nitems(alive_parents), }, /* CRU_CLKSEL_CON57 */ .muxdiv_offset = 0x01e4, .div_shift = 0, .div_width = 5, }; #define HCLK_PERILP1 450 #define PCLK_PERILP1 323 static const char *hclk_perilp1_parents[] = {"cpll", "gpll"}; static struct rk_clk_composite_def hclk_perilp1 = { .clkdef = { .id = HCLK_PERILP1, .name = "hclk_perilp1", .parent_names = hclk_perilp1_parents, .parent_cnt = nitems(hclk_perilp1_parents), }, /* CRU_CLKSEL_CON25 */ .muxdiv_offset = 0x164, .mux_shift = 7, .mux_width = 1, .div_shift = 0, .div_width = 5, .flags = RK_CLK_COMPOSITE_HAVE_MUX, }; static const char *pclk_perilp1_parents[] = {"hclk_perilp1"}; static struct rk_clk_composite_def pclk_perilp1 = { .clkdef = { .id = PCLK_PERILP1, .name = "pclk_perilp1", .parent_names = pclk_perilp1_parents, .parent_cnt = nitems(pclk_perilp1_parents), }, /* CRU_CLKSEL_CON25 */ .muxdiv_offset = 0x164, .div_shift = 8, .div_width = 3, /* CRU_CLKGATE_CON8 */ .gate_offset = 0x320, .gate_shift = 2, .flags = RK_CLK_COMPOSITE_HAVE_GATE, }; /* * i2c */ static const char *i2c_parents[] = {"cpll", "gpll"}; #define SCLK_I2C1 65 #define SCLK_I2C2 66 #define SCLK_I2C3 67 #define SCLK_I2C5 68 #define SCLK_I2C6 69 #define SCLK_I2C7 70 static struct rk_clk_composite_def i2c1 = { .clkdef = { .id = SCLK_I2C1, .name = "clk_i2c1", .parent_names = i2c_parents, .parent_cnt = nitems(i2c_parents), }, /* CRU_CLKSEL_CON61 */ .muxdiv_offset = 0x01f4, .mux_shift = 7, .mux_width = 1, .div_shift = 0, .div_width = 7, /* CRU_CLKGATE_CON10 */ .gate_offset = 0x0328, .gate_shift = 0, .flags = RK_CLK_COMPOSITE_HAVE_MUX | RK_CLK_COMPOSITE_HAVE_GATE, }; static struct rk_clk_composite_def i2c2 = { .clkdef = { .id = SCLK_I2C2, .name = "clk_i2c2", .parent_names = i2c_parents, .parent_cnt = nitems(i2c_parents), }, /* CRU_CLKSEL_CON62 */ .muxdiv_offset = 0x01f8, .mux_shift = 7, .mux_width = 1, .div_shift = 0, .div_width = 7, /* CRU_CLKGATE_CON10 */ .gate_offset = 0x0328, .gate_shift = 2, .flags = RK_CLK_COMPOSITE_HAVE_MUX | RK_CLK_COMPOSITE_HAVE_GATE, }; static struct rk_clk_composite_def i2c3 = { .clkdef = { .id = SCLK_I2C3, .name = "clk_i2c3", .parent_names = i2c_parents, .parent_cnt = nitems(i2c_parents), }, /* CRU_CLKSEL_CON63 */ .muxdiv_offset = 0x01fc, .mux_shift = 7, .mux_width = 1, .div_shift = 0, .div_width = 7, /* CRU_CLKGATE_CON10 */ .gate_offset = 0x0328, .gate_shift = 4, .flags = RK_CLK_COMPOSITE_HAVE_MUX | RK_CLK_COMPOSITE_HAVE_GATE, }; static struct rk_clk_composite_def i2c5 = { .clkdef = { .id = SCLK_I2C5, .name = "clk_i2c5", .parent_names = i2c_parents, .parent_cnt = nitems(i2c_parents), }, /* CRU_CLKSEL_CON61 */ .muxdiv_offset = 0x01f4, .mux_shift = 15, .mux_width = 1, .div_shift = 8, .div_width = 7, /* CRU_CLKGATE_CON10 */ .gate_offset = 0x0328, .gate_shift = 1, .flags = RK_CLK_COMPOSITE_HAVE_MUX | RK_CLK_COMPOSITE_HAVE_GATE, }; static struct rk_clk_composite_def i2c6 = { .clkdef = { .id = SCLK_I2C6, .name = "clk_i2c6", .parent_names = i2c_parents, .parent_cnt = nitems(i2c_parents), }, /* CRU_CLKSEL_CON62 */ .muxdiv_offset = 0x01f8, .mux_shift = 15, .mux_width = 1, .div_shift = 8, .div_width = 7, /* CRU_CLKGATE_CON10 */ .gate_offset = 0x0328, .gate_shift = 3, .flags = RK_CLK_COMPOSITE_HAVE_MUX | RK_CLK_COMPOSITE_HAVE_GATE, }; static struct rk_clk_composite_def i2c7 = { .clkdef = { .id = SCLK_I2C7, .name = "clk_i2c7", .parent_names = i2c_parents, .parent_cnt = nitems(i2c_parents), }, /* CRU_CLKSEL_CON63 */ .muxdiv_offset = 0x01fc, .mux_shift = 15, .mux_width = 1, .div_shift = 8, .div_width = 7, /* CRU_CLKGATE_CON10 */ .gate_offset = 0x0328, .gate_shift = 5, .flags = RK_CLK_COMPOSITE_HAVE_MUX | RK_CLK_COMPOSITE_HAVE_GATE, }; /* * ARM CPU clocks (LITTLE and big) */ #define ARMCLKL 8 #define ARMCLKB 9 static const char *armclk_parents[] = {"lpll", "bpll", "dpll", "gpll"}; static struct rk_clk_armclk_rates rk3399_armclkl_rates[] = { { .freq = 1800000000, .div = 1, }, { .freq = 1704000000, .div = 1, }, { .freq = 1608000000, .div = 1, }, { .freq = 1512000000, .div = 1, }, { .freq = 1488000000, .div = 1, }, { .freq = 1416000000, .div = 1, }, { .freq = 1200000000, .div = 1, }, { .freq = 1008000000, .div = 1, }, { .freq = 816000000, .div = 1, }, { .freq = 696000000, .div = 1, }, { .freq = 600000000, .div = 1, }, { .freq = 408000000, .div = 1, }, { .freq = 312000000, .div = 1, }, { .freq = 216000000, .div = 1, }, { .freq = 96000000, .div = 1, }, }; static struct rk_clk_armclk_def armclk_l = { .clkdef = { .id = ARMCLKL, .name = "armclkl", .parent_names = armclk_parents, .parent_cnt = nitems(armclk_parents), }, /* CRU_CLKSEL_CON0 */ .muxdiv_offset = 0x100, .mux_shift = 6, .mux_width = 2, .div_shift = 0, .div_width = 5, .flags = RK_CLK_COMPOSITE_HAVE_MUX, .main_parent = 0, .alt_parent = 3, .rates = rk3399_armclkl_rates, .nrates = nitems(rk3399_armclkl_rates), }; static struct rk_clk_armclk_rates rk3399_armclkb_rates[] = { { .freq = 2208000000, .div = 1, }, { .freq = 2184000000, .div = 1, }, { .freq = 2088000000, .div = 1, }, { .freq = 2040000000, .div = 1, }, { .freq = 2016000000, .div = 1, }, { .freq = 1992000000, .div = 1, }, { .freq = 1896000000, .div = 1, }, { .freq = 1800000000, .div = 1, }, { .freq = 1704000000, .div = 1, }, { .freq = 1608000000, .div = 1, }, { .freq = 1512000000, .div = 1, }, { .freq = 1488000000, .div = 1, }, { .freq = 1416000000, .div = 1, }, { .freq = 1200000000, .div = 1, }, { .freq = 1008000000, .div = 1, }, { .freq = 816000000, .div = 1, }, { .freq = 696000000, .div = 1, }, { .freq = 600000000, .div = 1, }, { .freq = 408000000, .div = 1, }, { .freq = 312000000, .div = 1, }, { .freq = 216000000, .div = 1, }, { .freq = 96000000, .div = 1, }, }; static struct rk_clk_armclk_def armclk_b = { .clkdef = { .id = ARMCLKB, .name = "armclkb", .parent_names = armclk_parents, .parent_cnt = nitems(armclk_parents), }, .muxdiv_offset = 0x108, .mux_shift = 6, .mux_width = 2, .div_shift = 0, .div_width = 5, .flags = RK_CLK_COMPOSITE_HAVE_MUX, .main_parent = 1, .alt_parent = 3, .rates = rk3399_armclkb_rates, .nrates = nitems(rk3399_armclkb_rates), }; /* * sdmmc */ #define HCLK_SD 461 static const char *hclk_sd_parents[] = {"cpll", "gpll"}; static struct rk_clk_composite_def hclk_sd = { .clkdef = { .id = HCLK_SD, .name = "hclk_sd", .parent_names = hclk_sd_parents, .parent_cnt = nitems(hclk_sd_parents), }, .muxdiv_offset = 0x134, .mux_shift = 15, .mux_width = 1, .div_shift = 8, .div_width = 5, .gate_offset = 0x330, .gate_shift = 13, .flags = RK_CLK_COMPOSITE_HAVE_MUX | RK_CLK_COMPOSITE_HAVE_GATE, }; #define SCLK_SDMMC 76 static const char *sclk_sdmmc_parents[] = {"cpll", "gpll", "npll", "ppll"}; static struct rk_clk_composite_def sclk_sdmmc = { .clkdef = { .id = SCLK_SDMMC, .name = "sclk_sdmmc", .parent_names = sclk_sdmmc_parents, .parent_cnt = nitems(sclk_sdmmc_parents), }, .muxdiv_offset = 0x140, .mux_shift = 8, .mux_width = 3, .div_shift = 0, .div_width = 7, .gate_offset = 0x318, .gate_shift = 1, .flags = RK_CLK_COMPOSITE_HAVE_MUX | RK_CLK_COMPOSITE_HAVE_GATE, }; +/* + * emmc + */ + +#define SCLK_EMMC 78 + +static const char *sclk_emmc_parents[] = {"cpll", "gpll", "npll"}; + +static struct rk_clk_composite_def sclk_emmc = { + .clkdef = { + .id = SCLK_EMMC, + .name = "sclk_emmc", + .parent_names = sclk_emmc_parents, + .parent_cnt = nitems(sclk_emmc_parents), + }, + + .muxdiv_offset = 0x158, + .mux_shift = 8, + .mux_width = 3, + + .div_shift = 0, + .div_width = 7, + + .gate_offset = 0x318, + .gate_shift = 14, + + .flags = RK_CLK_COMPOSITE_HAVE_MUX | RK_CLK_COMPOSITE_HAVE_GATE, +}; + +#define ACLK_EMMC 240 + +static const char *aclk_emmc_parents[] = { + "cpll_aclk_emmc_src", + "gpll_aclk_emmc_src" +}; + +static struct rk_clk_composite_def aclk_emmc = { + .clkdef = { + .id = ACLK_EMMC, + .name = "aclk_emmc", + .parent_names = aclk_emmc_parents, + .parent_cnt = nitems(aclk_emmc_parents), + }, + + .muxdiv_offset = 0x154, + .mux_shift = 7, + .mux_width = 1, + + .div_shift = 0, + .div_width = 5, + + .flags = RK_CLK_COMPOSITE_HAVE_MUX, +}; + static struct rk_clk rk3399_clks[] = { { .type = RK3399_CLK_PLL, .clk.pll = &lpll }, { .type = RK3399_CLK_PLL, .clk.pll = &bpll }, { .type = RK3399_CLK_PLL, .clk.pll = &dpll }, { .type = RK3399_CLK_PLL, .clk.pll = &cpll }, { .type = RK3399_CLK_PLL, .clk.pll = &gpll }, { .type = RK3399_CLK_PLL, .clk.pll = &npll }, { .type = RK3399_CLK_PLL, .clk.pll = &vpll }, { .type = RK_CLK_COMPOSITE, .clk.composite = &aclk_perihp, }, { .type = RK_CLK_COMPOSITE, .clk.composite = &hclk_perihp, }, { .type = RK_CLK_COMPOSITE, .clk.composite = &pclk_perihp, }, { .type = RK_CLK_COMPOSITE, .clk.composite = &aclk_perilp0, }, { .type = RK_CLK_COMPOSITE, .clk.composite = &hclk_perilp0, }, { .type = RK_CLK_COMPOSITE, .clk.composite = &pclk_perilp0, }, { .type = RK_CLK_COMPOSITE, .clk.composite = &pclk_alive, }, { .type = RK_CLK_COMPOSITE, .clk.composite = &hclk_perilp1, }, { .type = RK_CLK_COMPOSITE, .clk.composite = &pclk_perilp1, }, { .type = RK_CLK_COMPOSITE, .clk.composite = &i2c1, }, { .type = RK_CLK_COMPOSITE, .clk.composite = &i2c2, }, { .type = RK_CLK_COMPOSITE, .clk.composite = &i2c3, }, { .type = RK_CLK_COMPOSITE, .clk.composite = &i2c5, }, { .type = RK_CLK_COMPOSITE, .clk.composite = &i2c6, }, { .type = RK_CLK_COMPOSITE, .clk.composite = &i2c7, }, { .type = RK_CLK_ARMCLK, .clk.armclk = &armclk_l, }, { .type = RK_CLK_ARMCLK, .clk.armclk = &armclk_b, }, { .type = RK_CLK_COMPOSITE, .clk.composite = &hclk_sd, }, { .type = RK_CLK_COMPOSITE, .clk.composite = &sclk_sdmmc, }, + + { + .type = RK_CLK_COMPOSITE, + .clk.composite = &sclk_emmc, + }, + { + .type = RK_CLK_COMPOSITE, + .clk.composite = &aclk_emmc, + }, }; static int rk3399_cru_probe(device_t dev) { if (!ofw_bus_status_okay(dev)) return (ENXIO); if (ofw_bus_is_compatible(dev, "rockchip,rk3399-cru")) { device_set_desc(dev, "Rockchip RK3399 Clock and Reset Unit"); return (BUS_PROBE_DEFAULT); } return (ENXIO); } static int rk3399_cru_attach(device_t dev) { struct rk_cru_softc *sc; sc = device_get_softc(dev); sc->dev = dev; sc->gates = rk3399_gates; sc->ngates = nitems(rk3399_gates); sc->clks = rk3399_clks; sc->nclks = nitems(rk3399_clks); + + sc->reset_offset = 0x400; + sc->reset_num = 335; return (rk_cru_attach(dev)); } static device_method_t rk3399_cru_methods[] = { /* Device interface */ DEVMETHOD(device_probe, rk3399_cru_probe), DEVMETHOD(device_attach, rk3399_cru_attach), DEVMETHOD_END }; static devclass_t rk3399_cru_devclass; DEFINE_CLASS_1(rk3399_cru, rk3399_cru_driver, rk3399_cru_methods, sizeof(struct rk_cru_softc), rk_cru_driver); EARLY_DRIVER_MODULE(rk3399_cru, simplebus, rk3399_cru_driver, rk3399_cru_devclass, 0, 0, BUS_PASS_BUS + BUS_PASS_ORDER_MIDDLE); Index: stable/12/sys/arm64/rockchip/clk/rk3399_pmucru.c =================================================================== --- stable/12/sys/arm64/rockchip/clk/rk3399_pmucru.c (revision 355175) +++ stable/12/sys/arm64/rockchip/clk/rk3399_pmucru.c (revision 355176) @@ -1,866 +1,869 @@ /*- * SPDX-License-Identifier: BSD-2-Clause-FreeBSD * * Copyright (c) 2018 Emmanuel Vadot * Copyright (c) 2018 Greg V * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. * * $FreeBSD$ */ #include __FBSDID("$FreeBSD$"); #include #include #include #include #include #include #include #include #include #include #include #include #include #include /* GATES */ #define PCLK_PMU 20 #define PCLK_GPIO0_PMU 23 #define PCLK_GPIO1_PMU 24 #define PCLK_I2C0_PMU 27 #define PCLK_I2C4_PMU 28 #define PCLK_I2C8_PMU 29 static struct rk_cru_gate rk3399_pmu_gates[] = { /* PMUCRU_CLKGATE_CON1 */ CRU_GATE(PCLK_PMU, "pclk_pmu", "pclk_pmu_src", 0x104, 0) CRU_GATE(PCLK_GPIO0_PMU, "pclk_gpio0_pmu", "pclk_pmu_src", 0x104, 3) CRU_GATE(PCLK_GPIO1_PMU, "pclk_gpio1_pmu", "pclk_pmu_src", 0x104, 4) CRU_GATE(PCLK_I2C0_PMU, "pclk_i2c0_pmu", "pclk_pmu_src", 0x104, 7) CRU_GATE(PCLK_I2C4_PMU, "pclk_i2c4_pmu", "pclk_pmu_src", 0x104, 8) CRU_GATE(PCLK_I2C8_PMU, "pclk_i2c8_pmu", "pclk_pmu_src", 0x104, 9) }; /* * PLLs */ #define PLL_PPLL 1 static struct rk_clk_pll_rate rk3399_pll_rates[] = { { .freq = 2208000000, .refdiv = 1, .fbdiv = 92, .postdiv1 = 1, .postdiv2 = 1, .dsmpd = 1, }, { .freq = 2184000000, .refdiv = 1, .fbdiv = 91, .postdiv1 = 1, .postdiv2 = 1, .dsmpd = 1, }, { .freq = 2160000000, .refdiv = 1, .fbdiv = 90, .postdiv1 = 1, .postdiv2 = 1, .dsmpd = 1, }, { .freq = 2136000000, .refdiv = 1, .fbdiv = 89, .postdiv1 = 1, .postdiv2 = 1, .dsmpd = 1, }, { .freq = 2112000000, .refdiv = 1, .fbdiv = 88, .postdiv1 = 1, .postdiv2 = 1, .dsmpd = 1, }, { .freq = 2088000000, .refdiv = 1, .fbdiv = 87, .postdiv1 = 1, .postdiv2 = 1, .dsmpd = 1, }, { .freq = 2064000000, .refdiv = 1, .fbdiv = 86, .postdiv1 = 1, .postdiv2 = 1, .dsmpd = 1, }, { .freq = 2040000000, .refdiv = 1, .fbdiv = 85, .postdiv1 = 1, .postdiv2 = 1, .dsmpd = 1, }, { .freq = 2016000000, .refdiv = 1, .fbdiv = 84, .postdiv1 = 1, .postdiv2 = 1, .dsmpd = 1, }, { .freq = 1992000000, .refdiv = 1, .fbdiv = 83, .postdiv1 = 1, .postdiv2 = 1, .dsmpd = 1, }, { .freq = 1968000000, .refdiv = 1, .fbdiv = 82, .postdiv1 = 1, .postdiv2 = 1, .dsmpd = 1, }, { .freq = 1944000000, .refdiv = 1, .fbdiv = 81, .postdiv1 = 1, .postdiv2 = 1, .dsmpd = 1, }, { .freq = 1920000000, .refdiv = 1, .fbdiv = 80, .postdiv1 = 1, .postdiv2 = 1, .dsmpd = 1, }, { .freq = 1896000000, .refdiv = 1, .fbdiv = 79, .postdiv1 = 1, .postdiv2 = 1, .dsmpd = 1, }, { .freq = 1872000000, .refdiv = 1, .fbdiv = 78, .postdiv1 = 1, .postdiv2 = 1, .dsmpd = 1, }, { .freq = 1848000000, .refdiv = 1, .fbdiv = 77, .postdiv1 = 1, .postdiv2 = 1, .dsmpd = 1, }, { .freq = 1824000000, .refdiv = 1, .fbdiv = 76, .postdiv1 = 1, .postdiv2 = 1, .dsmpd = 1, }, { .freq = 1800000000, .refdiv = 1, .fbdiv = 75, .postdiv1 = 1, .postdiv2 = 1, .dsmpd = 1, }, { .freq = 1776000000, .refdiv = 1, .fbdiv = 74, .postdiv1 = 1, .postdiv2 = 1, .dsmpd = 1, }, { .freq = 1752000000, .refdiv = 1, .fbdiv = 73, .postdiv1 = 1, .postdiv2 = 1, .dsmpd = 1, }, { .freq = 1728000000, .refdiv = 1, .fbdiv = 72, .postdiv1 = 1, .postdiv2 = 1, .dsmpd = 1, }, { .freq = 1704000000, .refdiv = 1, .fbdiv = 71, .postdiv1 = 1, .postdiv2 = 1, .dsmpd = 1, }, { .freq = 1680000000, .refdiv = 1, .fbdiv = 70, .postdiv1 = 1, .postdiv2 = 1, .dsmpd = 1, }, { .freq = 1656000000, .refdiv = 1, .fbdiv = 69, .postdiv1 = 1, .postdiv2 = 1, .dsmpd = 1, }, { .freq = 1632000000, .refdiv = 1, .fbdiv = 68, .postdiv1 = 1, .postdiv2 = 1, .dsmpd = 1, }, { .freq = 1608000000, .refdiv = 1, .fbdiv = 67, .postdiv1 = 1, .postdiv2 = 1, .dsmpd = 1, }, { .freq = 1600000000, .refdiv = 3, .fbdiv = 200, .postdiv1 = 1, .postdiv2 = 1, .dsmpd = 1, }, { .freq = 1584000000, .refdiv = 1, .fbdiv = 66, .postdiv1 = 1, .postdiv2 = 1, .dsmpd = 1, }, { .freq = 1560000000, .refdiv = 1, .fbdiv = 65, .postdiv1 = 1, .postdiv2 = 1, .dsmpd = 1, }, { .freq = 1536000000, .refdiv = 1, .fbdiv = 64, .postdiv1 = 1, .postdiv2 = 1, .dsmpd = 1, }, { .freq = 1512000000, .refdiv = 1, .fbdiv = 63, .postdiv1 = 1, .postdiv2 = 1, .dsmpd = 1, }, { .freq = 1488000000, .refdiv = 1, .fbdiv = 62, .postdiv1 = 1, .postdiv2 = 1, .dsmpd = 1, }, { .freq = 1464000000, .refdiv = 1, .fbdiv = 61, .postdiv1 = 1, .postdiv2 = 1, .dsmpd = 1, }, { .freq = 1440000000, .refdiv = 1, .fbdiv = 60, .postdiv1 = 1, .postdiv2 = 1, .dsmpd = 1, }, { .freq = 1416000000, .refdiv = 1, .fbdiv = 59, .postdiv1 = 1, .postdiv2 = 1, .dsmpd = 1, }, { .freq = 1392000000, .refdiv = 1, .fbdiv = 58, .postdiv1 = 1, .postdiv2 = 1, .dsmpd = 1, }, { .freq = 1368000000, .refdiv = 1, .fbdiv = 57, .postdiv1 = 1, .postdiv2 = 1, .dsmpd = 1, }, { .freq = 1344000000, .refdiv = 1, .fbdiv = 56, .postdiv1 = 1, .postdiv2 = 1, .dsmpd = 1, }, { .freq = 1320000000, .refdiv = 1, .fbdiv = 55, .postdiv1 = 1, .postdiv2 = 1, .dsmpd = 1, }, { .freq = 1296000000, .refdiv = 1, .fbdiv = 54, .postdiv1 = 1, .postdiv2 = 1, .dsmpd = 1, }, { .freq = 1272000000, .refdiv = 1, .fbdiv = 53, .postdiv1 = 1, .postdiv2 = 1, .dsmpd = 1, }, { .freq = 1248000000, .refdiv = 1, .fbdiv = 52, .postdiv1 = 1, .postdiv2 = 1, .dsmpd = 1, }, { .freq = 1200000000, .refdiv = 1, .fbdiv = 50, .postdiv1 = 1, .postdiv2 = 1, .dsmpd = 1, }, { .freq = 1188000000, .refdiv = 2, .fbdiv = 99, .postdiv1 = 1, .postdiv2 = 1, .dsmpd = 1, }, { .freq = 1104000000, .refdiv = 1, .fbdiv = 46, .postdiv1 = 1, .postdiv2 = 1, .dsmpd = 1, }, { .freq = 1100000000, .refdiv = 12, .fbdiv = 550, .postdiv1 = 1, .postdiv2 = 1, .dsmpd = 1, }, { .freq = 1008000000, .refdiv = 1, .fbdiv = 84, .postdiv1 = 2, .postdiv2 = 1, .dsmpd = 1, }, { .freq = 1000000000, .refdiv = 1, .fbdiv = 125, .postdiv1 = 3, .postdiv2 = 1, .dsmpd = 1, }, { .freq = 984000000, .refdiv = 1, .fbdiv = 82, .postdiv1 = 2, .postdiv2 = 1, .dsmpd = 1, }, { .freq = 960000000, .refdiv = 1, .fbdiv = 80, .postdiv1 = 2, .postdiv2 = 1, .dsmpd = 1, }, { .freq = 936000000, .refdiv = 1, .fbdiv = 78, .postdiv1 = 2, .postdiv2 = 1, .dsmpd = 1, }, { .freq = 912000000, .refdiv = 1, .fbdiv = 76, .postdiv1 = 2, .postdiv2 = 1, .dsmpd = 1, }, { .freq = 900000000, .refdiv = 4, .fbdiv = 300, .postdiv1 = 2, .postdiv2 = 1, .dsmpd = 1, }, { .freq = 888000000, .refdiv = 1, .fbdiv = 74, .postdiv1 = 2, .postdiv2 = 1, .dsmpd = 1, }, { .freq = 864000000, .refdiv = 1, .fbdiv = 72, .postdiv1 = 2, .postdiv2 = 1, .dsmpd = 1, }, { .freq = 840000000, .refdiv = 1, .fbdiv = 70, .postdiv1 = 2, .postdiv2 = 1, .dsmpd = 1, }, { .freq = 816000000, .refdiv = 1, .fbdiv = 68, .postdiv1 = 2, .postdiv2 = 1, .dsmpd = 1, }, { .freq = 800000000, .refdiv = 1, .fbdiv = 100, .postdiv1 = 3, .postdiv2 = 1, .dsmpd = 1, }, { .freq = 700000000, .refdiv = 6, .fbdiv = 350, .postdiv1 = 2, .postdiv2 = 1, .dsmpd = 1, }, { .freq = 696000000, .refdiv = 1, .fbdiv = 58, .postdiv1 = 2, .postdiv2 = 1, .dsmpd = 1, }, { .freq = 676000000, .refdiv = 3, .fbdiv = 169, .postdiv1 = 2, .postdiv2 = 1, .dsmpd = 1, }, { .freq = 600000000, .refdiv = 1, .fbdiv = 75, .postdiv1 = 3, .postdiv2 = 1, .dsmpd = 1, }, { .freq = 594000000, .refdiv = 1, .fbdiv = 99, .postdiv1 = 4, .postdiv2 = 1, .dsmpd = 1, }, { .freq = 533250000, .refdiv = 8, .fbdiv = 711, .postdiv1 = 4, .postdiv2 = 1, .dsmpd = 1, }, { .freq = 504000000, .refdiv = 1, .fbdiv = 63, .postdiv1 = 3, .postdiv2 = 1, .dsmpd = 1, }, { .freq = 500000000, .refdiv = 6, .fbdiv = 250, .postdiv1 = 2, .postdiv2 = 1, .dsmpd = 1, }, { .freq = 408000000, .refdiv = 1, .fbdiv = 68, .postdiv1 = 2, .postdiv2 = 2, .dsmpd = 1, }, { .freq = 312000000, .refdiv = 1, .fbdiv = 52, .postdiv1 = 2, .postdiv2 = 2, .dsmpd = 1, }, { .freq = 297000000, .refdiv = 1, .fbdiv = 99, .postdiv1 = 4, .postdiv2 = 2, .dsmpd = 1, }, { .freq = 216000000, .refdiv = 1, .fbdiv = 72, .postdiv1 = 4, .postdiv2 = 2, .dsmpd = 1, }, { .freq = 148500000, .refdiv = 1, .fbdiv = 99, .postdiv1 = 4, .postdiv2 = 4, .dsmpd = 1, }, { .freq = 106500000, .refdiv = 1, .fbdiv = 71, .postdiv1 = 4, .postdiv2 = 4, .dsmpd = 1, }, { .freq = 96000000, .refdiv = 1, .fbdiv = 64, .postdiv1 = 4, .postdiv2 = 4, .dsmpd = 1, }, { .freq = 74250000, .refdiv = 2, .fbdiv = 99, .postdiv1 = 4, .postdiv2 = 4, .dsmpd = 1, }, { .freq = 65000000, .refdiv = 1, .fbdiv = 65, .postdiv1 = 6, .postdiv2 = 4, .dsmpd = 1, }, { .freq = 54000000, .refdiv = 1, .fbdiv = 54, .postdiv1 = 6, .postdiv2 = 4, .dsmpd = 1, }, { .freq = 27000000, .refdiv = 1, .fbdiv = 27, .postdiv1 = 6, .postdiv2 = 4, .dsmpd = 1, }, {}, }; static const char *pll_parents[] = {"xin24m"}; static struct rk_clk_pll_def ppll = { .clkdef = { .id = PLL_PPLL, .name = "ppll", .parent_names = pll_parents, .parent_cnt = nitems(pll_parents), }, .base_offset = 0x00, .rates = rk3399_pll_rates, }; static const char *pmu_parents[] = {"ppll"}; #define PCLK_PMU_SRC 19 static struct rk_clk_composite_def pclk_pmu_src = { .clkdef = { .id = PCLK_PMU_SRC, .name = "pclk_pmu_src", .parent_names = pmu_parents, .parent_cnt = nitems(pmu_parents), }, /* PMUCRU_CLKSEL_CON0 */ .muxdiv_offset = 0x80, .div_shift = 0, .div_width = 5, }; #define SCLK_I2C0_PMU 9 #define SCLK_I2C4_PMU 10 #define SCLK_I2C8_PMU 11 static struct rk_clk_composite_def i2c0 = { .clkdef = { .id = SCLK_I2C0_PMU, .name = "clk_i2c0_pmu", .parent_names = pmu_parents, .parent_cnt = nitems(pmu_parents), }, /* PMUCRU_CLKSEL_CON2 */ .muxdiv_offset = 0x88, .div_shift = 0, .div_width = 7, /* PMUCRU_CLKGATE_CON0 */ .gate_offset = 0x100, .gate_shift = 9, .flags = RK_CLK_COMPOSITE_HAVE_GATE, }; static struct rk_clk_composite_def i2c8 = { .clkdef = { .id = SCLK_I2C8_PMU, .name = "clk_i2c8_pmu", .parent_names = pmu_parents, .parent_cnt = nitems(pmu_parents), }, /* PMUCRU_CLKSEL_CON2 */ .muxdiv_offset = 0x88, .div_shift = 8, .div_width = 7, /* PMUCRU_CLKGATE_CON0 */ .gate_offset = 0x100, .gate_shift = 11, .flags = RK_CLK_COMPOSITE_HAVE_GATE, }; static struct rk_clk_composite_def i2c4 = { .clkdef = { .id = SCLK_I2C4_PMU, .name = "clk_i2c4_pmu", .parent_names = pmu_parents, .parent_cnt = nitems(pmu_parents), }, /* PMUCRU_CLKSEL_CON3 */ .muxdiv_offset = 0x8c, .div_shift = 0, .div_width = 7, /* PMUCRU_CLKGATE_CON0 */ .gate_offset = 0x100, .gate_shift = 10, .flags = RK_CLK_COMPOSITE_HAVE_GATE, }; static struct rk_clk rk3399_pmu_clks[] = { { .type = RK3399_CLK_PLL, .clk.pll = &ppll }, { .type = RK_CLK_COMPOSITE, .clk.composite = &pclk_pmu_src }, { .type = RK_CLK_COMPOSITE, .clk.composite = &i2c0 }, { .type = RK_CLK_COMPOSITE, .clk.composite = &i2c4 }, { .type = RK_CLK_COMPOSITE, .clk.composite = &i2c8 }, }; static int rk3399_pmucru_probe(device_t dev) { if (!ofw_bus_status_okay(dev)) return (ENXIO); if (ofw_bus_is_compatible(dev, "rockchip,rk3399-pmucru")) { device_set_desc(dev, "Rockchip RK3399 PMU Clock and Reset Unit"); return (BUS_PROBE_DEFAULT); } return (ENXIO); } static int rk3399_pmucru_attach(device_t dev) { struct rk_cru_softc *sc; sc = device_get_softc(dev); sc->dev = dev; sc->gates = rk3399_pmu_gates; sc->ngates = nitems(rk3399_pmu_gates); sc->clks = rk3399_pmu_clks; sc->nclks = nitems(rk3399_pmu_clks); + sc->reset_offset = 0x110; + sc->reset_num = 30; + return (rk_cru_attach(dev)); } static device_method_t rk3399_pmucru_methods[] = { /* Device interface */ DEVMETHOD(device_probe, rk3399_pmucru_probe), DEVMETHOD(device_attach, rk3399_pmucru_attach), DEVMETHOD_END }; static devclass_t rk3399_pmucru_devclass; DEFINE_CLASS_1(rk3399_pmucru, rk3399_pmucru_driver, rk3399_pmucru_methods, sizeof(struct rk_cru_softc), rk_cru_driver); EARLY_DRIVER_MODULE(rk3399_pmucru, simplebus, rk3399_pmucru_driver, rk3399_pmucru_devclass, 0, 0, BUS_PASS_BUS + BUS_PASS_ORDER_MIDDLE); Index: stable/12/sys/arm64/rockchip/clk/rk_cru.c =================================================================== --- stable/12/sys/arm64/rockchip/clk/rk_cru.c (revision 355175) +++ stable/12/sys/arm64/rockchip/clk/rk_cru.c (revision 355176) @@ -1,279 +1,289 @@ /*- * SPDX-License-Identifier: BSD-2-Clause-FreeBSD * * Copyright (c) 2018 Emmanuel Vadot * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. * * $FreeBSD$ */ /* * RockChip Clock and Reset Unit */ #include __FBSDID("$FreeBSD$"); #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include "clkdev_if.h" #include "hwreset_if.h" static struct resource_spec rk_cru_spec[] = { { SYS_RES_MEMORY, 0, RF_ACTIVE }, { -1, 0 } }; #define CCU_READ4(sc, reg) bus_read_4((sc)->res, (reg)) #define CCU_WRITE4(sc, reg, val) bus_write_4((sc)->res, (reg), (val)) void rk3328_cru_register_clocks(struct rk_cru_softc *sc); static int rk_cru_write_4(device_t dev, bus_addr_t addr, uint32_t val) { struct rk_cru_softc *sc; sc = device_get_softc(dev); CCU_WRITE4(sc, addr, val); return (0); } static int rk_cru_read_4(device_t dev, bus_addr_t addr, uint32_t *val) { struct rk_cru_softc *sc; sc = device_get_softc(dev); *val = CCU_READ4(sc, addr); return (0); } static int rk_cru_modify_4(device_t dev, bus_addr_t addr, uint32_t clr, uint32_t set) { struct rk_cru_softc *sc; uint32_t reg; sc = device_get_softc(dev); reg = CCU_READ4(sc, addr); reg &= ~clr; reg |= set; CCU_WRITE4(sc, addr, reg); return (0); } static int rk_cru_reset_assert(device_t dev, intptr_t id, bool reset) { struct rk_cru_softc *sc; + uint32_t reg; + int bit; uint32_t val; sc = device_get_softc(dev); - if (id >= sc->nresets || sc->resets[id].offset == 0) - return (0); + if (id > sc->reset_num) + return (ENXIO); + reg = sc->reset_offset + id / 16 * 4; + bit = id % 16; + mtx_lock(&sc->mtx); - val = CCU_READ4(sc, sc->resets[id].offset); + val = 0; if (reset) - val &= ~(1 << sc->resets[id].shift); - else - val |= 1 << sc->resets[id].shift; - CCU_WRITE4(sc, sc->resets[id].offset, val); + val = (1 << bit); + CCU_WRITE4(sc, reg, val | ((1 << bit) << 16)); mtx_unlock(&sc->mtx); return (0); } static int rk_cru_reset_is_asserted(device_t dev, intptr_t id, bool *reset) { struct rk_cru_softc *sc; + uint32_t reg; + int bit; uint32_t val; sc = device_get_softc(dev); - if (id >= sc->nresets || sc->resets[id].offset == 0) - return (0); + if (id > sc->reset_num) + return (ENXIO); + reg = sc->reset_offset + id / 16 * 4; + bit = id % 16; mtx_lock(&sc->mtx); - val = CCU_READ4(sc, sc->resets[id].offset); - *reset = (val & (1 << sc->resets[id].shift)) != 0 ? false : true; + val = CCU_READ4(sc, reg); mtx_unlock(&sc->mtx); + *reset = true; + if (val & (1 << bit)) + *reset = true; + return (0); } static void rk_cru_device_lock(device_t dev) { struct rk_cru_softc *sc; sc = device_get_softc(dev); mtx_lock(&sc->mtx); } static void rk_cru_device_unlock(device_t dev) { struct rk_cru_softc *sc; sc = device_get_softc(dev); mtx_unlock(&sc->mtx); } static int rk_cru_register_gates(struct rk_cru_softc *sc) { struct rk_clk_gate_def def; int i; for (i = 0; i < sc->ngates; i++) { if (sc->gates[i].name == NULL) continue; memset(&def, 0, sizeof(def)); def.clkdef.id = sc->gates[i].id; def.clkdef.name = sc->gates[i].name; def.clkdef.parent_names = &sc->gates[i].parent_name; def.clkdef.parent_cnt = 1; def.offset = sc->gates[i].offset; def.shift = sc->gates[i].shift; def.mask = 1; def.on_value = 0; def.off_value = 1; rk_clk_gate_register(sc->clkdom, &def); } return (0); } int rk_cru_attach(device_t dev) { struct rk_cru_softc *sc; phandle_t node; int i; sc = device_get_softc(dev); sc->dev = dev; node = ofw_bus_get_node(dev); if (bus_alloc_resources(dev, rk_cru_spec, &sc->res) != 0) { device_printf(dev, "cannot allocate resources for device\n"); return (ENXIO); } mtx_init(&sc->mtx, device_get_nameunit(dev), NULL, MTX_DEF); sc->clkdom = clkdom_create(dev); if (sc->clkdom == NULL) panic("Cannot create clkdom\n"); for (i = 0; i < sc->nclks; i++) { switch (sc->clks[i].type) { case RK_CLK_UNDEFINED: break; case RK3328_CLK_PLL: rk3328_clk_pll_register(sc->clkdom, sc->clks[i].clk.pll); break; case RK3399_CLK_PLL: rk3399_clk_pll_register(sc->clkdom, sc->clks[i].clk.pll); break; case RK_CLK_COMPOSITE: rk_clk_composite_register(sc->clkdom, sc->clks[i].clk.composite); break; case RK_CLK_MUX: rk_clk_mux_register(sc->clkdom, sc->clks[i].clk.mux); break; case RK_CLK_ARMCLK: rk_clk_armclk_register(sc->clkdom, sc->clks[i].clk.armclk); break; default: device_printf(dev, "Unknown clock type\n"); return (ENXIO); break; } } if (sc->gates) rk_cru_register_gates(sc); if (clkdom_finit(sc->clkdom) != 0) panic("cannot finalize clkdom initialization\n"); if (bootverbose) clkdom_dump(sc->clkdom); clk_set_assigned(dev, node); /* If we have resets, register our self as a reset provider */ - if (sc->resets) - hwreset_register_ofw_provider(dev); + /* if (sc->resets) */ + /* hwreset_register_ofw_provider(dev); */ return (0); } static device_method_t rk_cru_methods[] = { /* clkdev interface */ DEVMETHOD(clkdev_write_4, rk_cru_write_4), DEVMETHOD(clkdev_read_4, rk_cru_read_4), DEVMETHOD(clkdev_modify_4, rk_cru_modify_4), DEVMETHOD(clkdev_device_lock, rk_cru_device_lock), DEVMETHOD(clkdev_device_unlock, rk_cru_device_unlock), /* Reset interface */ DEVMETHOD(hwreset_assert, rk_cru_reset_assert), DEVMETHOD(hwreset_is_asserted, rk_cru_reset_is_asserted), DEVMETHOD_END }; DEFINE_CLASS_0(rk_cru, rk_cru_driver, rk_cru_methods, sizeof(struct rk_cru_softc)); Index: stable/12/sys/arm64/rockchip/clk/rk_cru.h =================================================================== --- stable/12/sys/arm64/rockchip/clk/rk_cru.h (revision 355175) +++ stable/12/sys/arm64/rockchip/clk/rk_cru.h (revision 355176) @@ -1,102 +1,97 @@ /*- * SPDX-License-Identifier: BSD-2-Clause-FreeBSD * * Copyright (c) 2018 Emmanuel Vadot * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. * * $FreeBSD$ */ #ifndef __RK_CRU_H__ #define __RK_CRU_H__ #include #include #include #include #include -struct rk_cru_reset { - uint32_t offset; - uint32_t shift; -}; - struct rk_cru_gate { const char *name; const char *parent_name; uint32_t id; uint32_t offset; uint32_t shift; }; #define CRU_GATE(idx, clkname, pname, o, s) \ { \ .id = idx, \ .name = clkname, \ .parent_name = pname, \ .offset = o, \ .shift = s, \ }, enum rk_clk_type { RK_CLK_UNDEFINED = 0, RK3328_CLK_PLL, RK3399_CLK_PLL, RK_CLK_COMPOSITE, RK_CLK_MUX, RK_CLK_ARMCLK, }; struct rk_clk { enum rk_clk_type type; union { struct rk_clk_pll_def *pll; struct rk_clk_composite_def *composite; struct rk_clk_mux_def *mux; struct rk_clk_armclk_def *armclk; } clk; }; struct rk_cru_softc { device_t dev; struct resource *res; struct clkdom *clkdom; struct mtx mtx; int type; - struct rk_cru_reset *resets; - int nresets; + uint32_t reset_offset; + uint32_t reset_num; struct rk_cru_gate *gates; int ngates; struct rk_clk *clks; int nclks; struct rk_clk_armclk_def *armclk; struct rk_clk_armclk_rates *armclk_rates; int narmclk_rates; }; DECLARE_CLASS(rk_cru_driver); int rk_cru_attach(device_t dev); #endif /* __RK_CRU_H__ */ Index: stable/12/sys/arm64/rockchip/rk_gpio.c =================================================================== --- stable/12/sys/arm64/rockchip/rk_gpio.c (revision 355175) +++ stable/12/sys/arm64/rockchip/rk_gpio.c (revision 355176) @@ -1,429 +1,429 @@ /*- * SPDX-License-Identifier: BSD-2-Clause-FreeBSD * * Copyright (c) 2018 Emmanuel Vadot * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. * */ #include __FBSDID("$FreeBSD$"); #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include "opt_soc.h" #include "gpio_if.h" #define RK_GPIO_SWPORTA_DR 0x00 /* Data register */ #define RK_GPIO_SWPORTA_DDR 0x04 /* Data direction register */ #define RK_GPIO_INTEN 0x30 /* Interrupt enable register */ #define RK_GPIO_INTMASK 0x34 /* Interrupt mask register */ #define RK_GPIO_INTTYPE_LEVEL 0x38 /* Interrupt level register */ #define RK_GPIO_INT_POLARITY 0x3C /* Interrupt polarity register */ #define RK_GPIO_INT_STATUS 0x40 /* Interrupt status register */ #define RK_GPIO_INT_RAWSTATUS 0x44 /* Raw Interrupt status register */ #define RK_GPIO_DEBOUNCE 0x48 /* Debounce enable register */ #define RK_GPIO_PORTA_EOI 0x4C /* Clear interrupt register */ #define RK_GPIO_EXT_PORTA 0x50 /* External port register */ #define RK_GPIO_LS_SYNC 0x60 /* Level sensitive syncronization enable register */ struct rk_gpio_softc { device_t sc_dev; device_t sc_busdev; struct mtx sc_mtx; struct resource *sc_res[2]; bus_space_tag_t sc_bst; bus_space_handle_t sc_bsh; clk_t clk; }; static struct ofw_compat_data compat_data[] = { {"rockchip,gpio-bank", 1}, {NULL, 0} }; static struct resource_spec rk_gpio_spec[] = { { SYS_RES_MEMORY, 0, RF_ACTIVE }, { SYS_RES_IRQ, 0, RF_ACTIVE }, { -1, 0 } }; static int rk_gpio_detach(device_t dev); #define RK_GPIO_LOCK(_sc) mtx_lock_spin(&(_sc)->sc_mtx) #define RK_GPIO_UNLOCK(_sc) mtx_unlock_spin(&(_sc)->sc_mtx) #define RK_GPIO_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->sc_mtx, MA_OWNED) #define RK_GPIO_WRITE(_sc, _off, _val) \ bus_space_write_4(_sc->sc_bst, _sc->sc_bsh, _off, _val) #define RK_GPIO_READ(_sc, _off) \ bus_space_read_4(_sc->sc_bst, _sc->sc_bsh, _off) static int rk_gpio_probe(device_t dev) { if (!ofw_bus_status_okay(dev)) return (ENXIO); if (ofw_bus_search_compatible(dev, compat_data)->ocd_data == 0) return (ENXIO); device_set_desc(dev, "RockChip GPIO Bank controller"); return (BUS_PROBE_DEFAULT); } static int rk_gpio_attach(device_t dev) { struct rk_gpio_softc *sc; phandle_t node; int err; sc = device_get_softc(dev); sc->sc_dev = dev; node = ofw_bus_get_node(sc->sc_dev); if (!OF_hasprop(node, "gpio-controller")) return (ENXIO); mtx_init(&sc->sc_mtx, "rk gpio", "gpio", MTX_SPIN); if (bus_alloc_resources(dev, rk_gpio_spec, sc->sc_res)) { device_printf(dev, "could not allocate resources\n"); bus_release_resources(dev, rk_gpio_spec, sc->sc_res); mtx_destroy(&sc->sc_mtx); return (ENXIO); } sc->sc_bst = rman_get_bustag(sc->sc_res[0]); sc->sc_bsh = rman_get_bushandle(sc->sc_res[0]); if (clk_get_by_ofw_index(dev, 0, 0, &sc->clk) != 0) { device_printf(dev, "Cannot get clock\n"); rk_gpio_detach(dev); return (ENXIO); } err = clk_enable(sc->clk); if (err != 0) { device_printf(dev, "Could not enable clock %s\n", clk_get_name(sc->clk)); rk_gpio_detach(dev); return (ENXIO); } sc->sc_busdev = gpiobus_attach_bus(dev); if (sc->sc_busdev == NULL) { rk_gpio_detach(dev); return (ENXIO); } return (0); } static int rk_gpio_detach(device_t dev) { struct rk_gpio_softc *sc; sc = device_get_softc(dev); if (sc->sc_busdev) gpiobus_detach_bus(dev); bus_release_resources(dev, rk_gpio_spec, sc->sc_res); mtx_destroy(&sc->sc_mtx); clk_disable(sc->clk); return(0); } static device_t rk_gpio_get_bus(device_t dev) { struct rk_gpio_softc *sc; sc = device_get_softc(dev); return (sc->sc_busdev); } static int rk_gpio_pin_max(device_t dev, int *maxpin) { /* Each bank have always 32 pins */ *maxpin = 32; return (0); } static int rk_gpio_pin_getname(device_t dev, uint32_t pin, char *name) { struct rk_gpio_softc *sc; sc = device_get_softc(dev); if (pin >= 32) return (EINVAL); RK_GPIO_LOCK(sc); snprintf(name, GPIOMAXNAME, "gpio%d", pin); RK_GPIO_UNLOCK(sc); return (0); } static int rk_gpio_pin_getflags(device_t dev, uint32_t pin, uint32_t *flags) { struct rk_gpio_softc *sc; uint32_t reg; sc = device_get_softc(dev); RK_GPIO_LOCK(sc); reg = RK_GPIO_READ(sc, RK_GPIO_SWPORTA_DDR); RK_GPIO_UNLOCK(sc); if (reg & (1 << pin)) *flags = GPIO_PIN_OUTPUT; else *flags = GPIO_PIN_INPUT; return (0); } static int rk_gpio_pin_getcaps(device_t dev, uint32_t pin, uint32_t *caps) { /* Caps are managed by the pinctrl device */ *caps = 0; return (0); } static int rk_gpio_pin_setflags(device_t dev, uint32_t pin, uint32_t flags) { struct rk_gpio_softc *sc; uint32_t reg; sc = device_get_softc(dev); RK_GPIO_LOCK(sc); reg = RK_GPIO_READ(sc, RK_GPIO_SWPORTA_DDR); if (flags & GPIO_PIN_INPUT) reg &= ~(1 << pin); else if (flags & GPIO_PIN_OUTPUT) reg |= (1 << pin); RK_GPIO_WRITE(sc, RK_GPIO_SWPORTA_DDR, reg); RK_GPIO_UNLOCK(sc); return (0); } static int rk_gpio_pin_get(device_t dev, uint32_t pin, unsigned int *val) { struct rk_gpio_softc *sc; uint32_t reg; sc = device_get_softc(dev); RK_GPIO_LOCK(sc); reg = RK_GPIO_READ(sc, RK_GPIO_EXT_PORTA); RK_GPIO_UNLOCK(sc); *val = reg & (1 << pin) ? 1 : 0; return (0); } static int rk_gpio_pin_set(device_t dev, uint32_t pin, unsigned int value) { struct rk_gpio_softc *sc; uint32_t reg; sc = device_get_softc(dev); RK_GPIO_LOCK(sc); reg = RK_GPIO_READ(sc, RK_GPIO_SWPORTA_DR); if (value) reg |= (1 << pin); else reg &= ~(1 << pin); RK_GPIO_WRITE(sc, RK_GPIO_SWPORTA_DR, reg); RK_GPIO_UNLOCK(sc); return (0); } static int rk_gpio_pin_toggle(device_t dev, uint32_t pin) { struct rk_gpio_softc *sc; uint32_t reg; sc = device_get_softc(dev); RK_GPIO_LOCK(sc); reg = RK_GPIO_READ(sc, RK_GPIO_SWPORTA_DR); if (reg & (1 << pin)) reg &= ~(1 << pin); else reg |= (1 << pin); RK_GPIO_WRITE(sc, RK_GPIO_SWPORTA_DR, reg); RK_GPIO_UNLOCK(sc); return (0); } static int rk_gpio_pin_access_32(device_t dev, uint32_t first_pin, uint32_t clear_pins, uint32_t change_pins, uint32_t *orig_pins) { struct rk_gpio_softc *sc; uint32_t reg; sc = device_get_softc(dev); RK_GPIO_LOCK(sc); reg = RK_GPIO_READ(sc, RK_GPIO_SWPORTA_DR); if (orig_pins) *orig_pins = reg; if ((clear_pins | change_pins) != 0) { reg = (reg & ~clear_pins) ^ change_pins; RK_GPIO_WRITE(sc, RK_GPIO_SWPORTA_DR, reg); } RK_GPIO_UNLOCK(sc); return (0); } static int rk_gpio_pin_config_32(device_t dev, uint32_t first_pin, uint32_t num_pins, uint32_t *pin_flags) { struct rk_gpio_softc *sc; uint32_t reg, set, mask, flags; int i; sc = device_get_softc(dev); if (first_pin != 0 || num_pins > 32) return (EINVAL); set = 0; mask = 0; for (i = 0; i < num_pins; i++) { mask = (mask << 1) | 1; flags = pin_flags[i]; if (flags & GPIO_PIN_INPUT) { set &= ~(1 << i); } else if (flags & GPIO_PIN_OUTPUT) { set |= (1 << i); } } RK_GPIO_LOCK(sc); reg = RK_GPIO_READ(sc, RK_GPIO_SWPORTA_DDR); reg &= ~mask; reg |= set; RK_GPIO_WRITE(sc, RK_GPIO_SWPORTA_DDR, reg); RK_GPIO_UNLOCK(sc); return (0); } static int rk_gpio_map_gpios(device_t bus, phandle_t dev, phandle_t gparent, int gcells, pcell_t *gpios, uint32_t *pin, uint32_t *flags) { - /* The gpios are mapped as */ - *pin = gpios[1]; - *flags = gpios[2]; + /* The gpios are mapped as */ + *pin = gpios[0]; + *flags = gpios[1]; return (0); } static device_method_t rk_gpio_methods[] = { /* Device interface */ DEVMETHOD(device_probe, rk_gpio_probe), DEVMETHOD(device_attach, rk_gpio_attach), DEVMETHOD(device_detach, rk_gpio_detach), /* GPIO protocol */ DEVMETHOD(gpio_get_bus, rk_gpio_get_bus), DEVMETHOD(gpio_pin_max, rk_gpio_pin_max), DEVMETHOD(gpio_pin_getname, rk_gpio_pin_getname), DEVMETHOD(gpio_pin_getflags, rk_gpio_pin_getflags), DEVMETHOD(gpio_pin_getcaps, rk_gpio_pin_getcaps), DEVMETHOD(gpio_pin_setflags, rk_gpio_pin_setflags), DEVMETHOD(gpio_pin_get, rk_gpio_pin_get), DEVMETHOD(gpio_pin_set, rk_gpio_pin_set), DEVMETHOD(gpio_pin_toggle, rk_gpio_pin_toggle), DEVMETHOD(gpio_pin_access_32, rk_gpio_pin_access_32), DEVMETHOD(gpio_pin_config_32, rk_gpio_pin_config_32), DEVMETHOD(gpio_map_gpios, rk_gpio_map_gpios), DEVMETHOD_END }; static driver_t rk_gpio_driver = { "gpio", rk_gpio_methods, sizeof(struct rk_gpio_softc), }; static devclass_t rk_gpio_devclass; EARLY_DRIVER_MODULE(rk_gpio, simplebus, rk_gpio_driver, rk_gpio_devclass, 0, 0, BUS_PASS_INTERRUPT + BUS_PASS_ORDER_LATE); Index: stable/12/sys/arm64/rockchip/rk_pinctrl.c =================================================================== --- stable/12/sys/arm64/rockchip/rk_pinctrl.c (revision 355175) +++ stable/12/sys/arm64/rockchip/rk_pinctrl.c (revision 355176) @@ -1,777 +1,1040 @@ /*- * SPDX-License-Identifier: BSD-2-Clause-FreeBSD * * Copyright (c) 2018 Emmanuel Vadot * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. * */ #include __FBSDID("$FreeBSD$"); #include #include #include +#include #include -#include -#include #include +#include #include +#include #include #include #include #include #include #include #include #include +#include "gpio_if.h" #include "syscon_if.h" -#include "opt_soc.h" - struct rk_pinctrl_pin_drive { uint32_t bank; uint32_t subbank; uint32_t offset; uint32_t value; uint32_t ma; }; struct rk_pinctrl_bank { - uint32_t bank_num; - uint32_t subbank_num; + uint32_t bank; + uint32_t subbank; uint32_t offset; uint32_t nbits; }; struct rk_pinctrl_pin_fixup { uint32_t bank; uint32_t subbank; uint32_t pin; uint32_t reg; uint32_t bit; uint32_t mask; }; +struct rk_pinctrl_gpio { + uint32_t bank; + char *gpio_name; + device_t gpio_dev; +}; + + struct rk_pinctrl_softc; struct rk_pinctrl_conf { struct rk_pinctrl_bank *iomux_conf; uint32_t iomux_nbanks; struct rk_pinctrl_pin_fixup *pin_fixup; uint32_t npin_fixup; struct rk_pinctrl_pin_drive *pin_drive; uint32_t npin_drive; - uint32_t (*get_pd_offset)(struct rk_pinctrl_softc *, uint32_t); - struct syscon *(*get_syscon)(struct rk_pinctrl_softc *, uint32_t); + struct rk_pinctrl_gpio *gpio_bank; + uint32_t ngpio_bank; + uint32_t (*get_pd_offset)(struct rk_pinctrl_softc *, uint32_t); + struct syscon *(*get_syscon)(struct rk_pinctrl_softc *, uint32_t); }; struct rk_pinctrl_softc { struct simplebus_softc simplebus_sc; device_t dev; struct syscon *grf; struct syscon *pmu; struct rk_pinctrl_conf *conf; }; +#define RK_IOMUX(_bank, _subbank, _offset, _nbits) \ +{ \ + .bank = _bank, \ + .subbank = _subbank, \ + .offset = _offset, \ + .nbits = _nbits, \ +} + +#define RK_PINFIX(_bank, _pin, _reg, _bit, _mask) \ +{ \ + .bank = _bank, \ + .pin = _pin, \ + .reg = _reg, \ + .bit = _bit, \ + .mask = _mask, \ +} + +#define RK_PINDRIVE(_bank, _subbank, _offset, _value, _ma) \ +{ \ + .bank = _bank, \ + .subbank = _subbank, \ + .offset = _offset, \ + .value = _value, \ + .ma = _ma, \ +} +#define RK_GPIO(_bank, _name) \ +{ \ + .bank = _bank, \ + .gpio_name = _name, \ +} + +static struct rk_pinctrl_gpio rk3288_gpio_bank[] = { + RK_GPIO(0, "gpio0"), + RK_GPIO(1, "gpio1"), + RK_GPIO(2, "gpio2"), + RK_GPIO(3, "gpio3"), + RK_GPIO(4, "gpio4"), + RK_GPIO(5, "gpio5"), + RK_GPIO(6, "gpio6"), + RK_GPIO(7, "gpio7"), + RK_GPIO(8, "gpio8"), +}; + +static struct rk_pinctrl_bank rk3288_iomux_bank[] = { + /* bank sub offs nbits */ + /* PMU */ + RK_IOMUX(0, 0, 0x0084, 2), + RK_IOMUX(0, 1, 0x0088, 2), + RK_IOMUX(0, 2, 0x008C, 2), + /* GFR */ + RK_IOMUX(1, 3, 0x000C, 2), + RK_IOMUX(2, 0, 0x0010, 2), + RK_IOMUX(2, 1, 0x0014, 2), + RK_IOMUX(2, 2, 0x0018, 2), + RK_IOMUX(2, 3, 0x001C, 2), + RK_IOMUX(3, 0, 0x0020, 2), + RK_IOMUX(3, 1, 0x0024, 2), + RK_IOMUX(3, 2, 0x0028, 2), + RK_IOMUX(3, 3, 0x002C, 4), + RK_IOMUX(4, 0, 0x0034, 4), + RK_IOMUX(4, 1, 0x003C, 4), + RK_IOMUX(4, 2, 0x0044, 2), + RK_IOMUX(4, 3, 0x0048, 2), + /* 5,0 - Empty */ + RK_IOMUX(5, 1, 0x0050, 2), + RK_IOMUX(5, 2, 0x0054, 2), + /* 5,3 - Empty */ + RK_IOMUX(6, 0, 0x005C, 2), + RK_IOMUX(6, 1, 0x0060, 2), + RK_IOMUX(6, 2, 0x0064, 2), + /* 6,3 - Empty */ + RK_IOMUX(7, 0, 0x006C, 2), + RK_IOMUX(7, 1, 0x0070, 2), + RK_IOMUX(7, 2, 0x0074, 4), + /* 7,3 - Empty */ + RK_IOMUX(8, 0, 0x0080, 2), + RK_IOMUX(8, 1, 0x0084, 2), + /* 8,2 - Empty */ + /* 8,3 - Empty */ + +}; + +static struct rk_pinctrl_pin_fixup rk3288_pin_fixup[] = { +}; + +static struct rk_pinctrl_pin_drive rk3288_pin_drive[] = { + /* bank sub offs val ma */ + /* GPIO0A (PMU)*/ + RK_PINDRIVE(0, 0, 0x070, 0, 2), + RK_PINDRIVE(0, 0, 0x070, 1, 4), + RK_PINDRIVE(0, 0, 0x070, 2, 8), + RK_PINDRIVE(0, 0, 0x070, 3, 12), + + /* GPIO0B (PMU)*/ + RK_PINDRIVE(0, 1, 0x074, 0, 2), + RK_PINDRIVE(0, 1, 0x074, 1, 4), + RK_PINDRIVE(0, 1, 0x074, 2, 8), + RK_PINDRIVE(0, 1, 0x074, 3, 12), + + /* GPIO0C (PMU)*/ + RK_PINDRIVE(0, 2, 0x078, 0, 2), + RK_PINDRIVE(0, 2, 0x078, 1, 4), + RK_PINDRIVE(0, 2, 0x078, 2, 8), + RK_PINDRIVE(0, 2, 0x078, 3, 12), + + /* GPIO1D */ + RK_PINDRIVE(1, 3, 0x1CC, 0, 2), + RK_PINDRIVE(1, 3, 0x1CC, 1, 4), + RK_PINDRIVE(1, 3, 0x1CC, 2, 8), + RK_PINDRIVE(1, 3, 0x1CC, 3, 12), + + /* GPIO2A */ + RK_PINDRIVE(2, 0, 0x1D0, 0, 2), + RK_PINDRIVE(2, 0, 0x1D0, 1, 4), + RK_PINDRIVE(2, 0, 0x1D0, 2, 8), + RK_PINDRIVE(2, 0, 0x1D0, 3, 12), + + /* GPIO2B */ + RK_PINDRIVE(2, 1, 0x1D4, 0, 2), + RK_PINDRIVE(2, 1, 0x1D4, 1, 4), + RK_PINDRIVE(2, 1, 0x1D4, 2, 8), + RK_PINDRIVE(2, 1, 0x1D4, 3, 12), + + /* GPIO2C */ + RK_PINDRIVE(2, 2, 0x1D8, 0, 2), + RK_PINDRIVE(2, 2, 0x1D8, 1, 4), + RK_PINDRIVE(2, 2, 0x1D8, 2, 8), + RK_PINDRIVE(2, 2, 0x1D8, 3, 12), + + /* GPIO2D */ + RK_PINDRIVE(2, 3, 0x1DC, 0, 2), + RK_PINDRIVE(2, 3, 0x1DC, 1, 4), + RK_PINDRIVE(2, 3, 0x1DC, 2, 8), + RK_PINDRIVE(2, 3, 0x1DC, 3, 12), + + /* GPIO3A */ + RK_PINDRIVE(3, 0, 0x1E0, 0, 2), + RK_PINDRIVE(3, 0, 0x1E0, 1, 4), + RK_PINDRIVE(3, 0, 0x1E0, 2, 8), + RK_PINDRIVE(3, 0, 0x1E0, 3, 12), + + /* GPIO3B */ + RK_PINDRIVE(3, 1, 0x1E4, 0, 2), + RK_PINDRIVE(3, 1, 0x1E4, 1, 4), + RK_PINDRIVE(3, 1, 0x1E4, 2, 8), + RK_PINDRIVE(3, 1, 0x1E4, 3, 12), + + /* GPIO3C */ + RK_PINDRIVE(3, 2, 0x1E8, 0, 2), + RK_PINDRIVE(3, 2, 0x1E8, 1, 4), + RK_PINDRIVE(3, 2, 0x1E8, 2, 8), + RK_PINDRIVE(3, 2, 0x1E8, 3, 12), + + /* GPIO3D */ + RK_PINDRIVE(3, 3, 0x1EC, 0, 2), + RK_PINDRIVE(3, 3, 0x1EC, 1, 4), + RK_PINDRIVE(3, 3, 0x1EC, 2, 8), + RK_PINDRIVE(3, 3, 0x1EC, 3, 12), + + /* GPIO4A */ + RK_PINDRIVE(4, 0, 0x1F0, 0, 2), + RK_PINDRIVE(4, 0, 0x1F0, 1, 4), + RK_PINDRIVE(4, 0, 0x1F0, 2, 8), + RK_PINDRIVE(4, 0, 0x1F0, 3, 12), + + /* GPIO4B */ + RK_PINDRIVE(4, 1, 0x1F4, 0, 2), + RK_PINDRIVE(4, 1, 0x1F4, 1, 4), + RK_PINDRIVE(4, 1, 0x1F4, 2, 8), + RK_PINDRIVE(4, 1, 0x1F4, 3, 12), + + /* GPIO4C */ + RK_PINDRIVE(4, 2, 0x1F8, 0, 2), + RK_PINDRIVE(4, 2, 0x1F8, 1, 4), + RK_PINDRIVE(4, 2, 0x1F8, 2, 8), + RK_PINDRIVE(4, 2, 0x1F8, 3, 12), + + /* GPIO4D */ + RK_PINDRIVE(4, 3, 0x1FC, 0, 2), + RK_PINDRIVE(4, 3, 0x1FC, 1, 4), + RK_PINDRIVE(4, 3, 0x1FC, 2, 8), + RK_PINDRIVE(4, 3, 0x1FC, 3, 12), + + /* GPIO5B */ + RK_PINDRIVE(5, 1, 0x204, 0, 2), + RK_PINDRIVE(5, 1, 0x204, 1, 4), + RK_PINDRIVE(5, 1, 0x204, 2, 8), + RK_PINDRIVE(5, 1, 0x204, 3, 12), + + /* GPIO5C */ + RK_PINDRIVE(5, 2, 0x208, 0, 2), + RK_PINDRIVE(5, 2, 0x208, 1, 4), + RK_PINDRIVE(5, 2, 0x208, 2, 8), + RK_PINDRIVE(5, 2, 0x208, 3, 12), + + /* GPIO6A */ + RK_PINDRIVE(6, 0, 0x210, 0, 2), + RK_PINDRIVE(6, 0, 0x210, 1, 4), + RK_PINDRIVE(6, 0, 0x210, 2, 8), + RK_PINDRIVE(6, 0, 0x210, 3, 12), + + /* GPIO6B */ + RK_PINDRIVE(6, 1, 0x214, 0, 2), + RK_PINDRIVE(6, 1, 0x214, 1, 4), + RK_PINDRIVE(6, 1, 0x214, 2, 8), + RK_PINDRIVE(6, 1, 0x214, 3, 12), + + /* GPIO6C */ + RK_PINDRIVE(6, 2, 0x218, 0, 2), + RK_PINDRIVE(6, 2, 0x218, 1, 4), + RK_PINDRIVE(6, 2, 0x218, 2, 8), + RK_PINDRIVE(6, 2, 0x218, 3, 12), + + /* GPIO7A */ + RK_PINDRIVE(7, 0, 0x220, 0, 2), + RK_PINDRIVE(7, 0, 0x220, 1, 4), + RK_PINDRIVE(7, 0, 0x220, 2, 8), + RK_PINDRIVE(7, 0, 0x220, 3, 12), + + /* GPIO7B */ + RK_PINDRIVE(7, 1, 0x224, 0, 2), + RK_PINDRIVE(7, 1, 0x224, 1, 4), + RK_PINDRIVE(7, 1, 0x224, 2, 8), + RK_PINDRIVE(7, 1, 0x224, 3, 12), + + /* GPIO7C */ + RK_PINDRIVE(7, 2, 0x228, 0, 2), + RK_PINDRIVE(7, 2, 0x228, 1, 4), + RK_PINDRIVE(7, 2, 0x228, 2, 8), + RK_PINDRIVE(7, 2, 0x228, 3, 12), + + /* GPIO8A */ + RK_PINDRIVE(8, 0, 0x230, 0, 2), + RK_PINDRIVE(8, 0, 0x230, 1, 4), + RK_PINDRIVE(8, 0, 0x230, 2, 8), + RK_PINDRIVE(8, 0, 0x230, 3, 12), + + /* GPIO8B */ + RK_PINDRIVE(8, 1, 0x234, 0, 2), + RK_PINDRIVE(8, 1, 0x234, 1, 4), + RK_PINDRIVE(8, 1, 0x234, 2, 8), + RK_PINDRIVE(8, 1, 0x234, 3, 12), +}; + +static uint32_t +rk3288_get_pd_offset(struct rk_pinctrl_softc *sc, uint32_t bank) +{ + if (bank == 0) + return (0x064); /* PMU */ + return (0x130); +} + +static struct syscon * +rk3288_get_syscon(struct rk_pinctrl_softc *sc, uint32_t bank) +{ + if (bank == 0) + return (sc->pmu); + return (sc->grf); +} + +struct rk_pinctrl_conf rk3288_conf = { + .iomux_conf = rk3288_iomux_bank, + .iomux_nbanks = nitems(rk3288_iomux_bank), + .pin_fixup = rk3288_pin_fixup, + .npin_fixup = nitems(rk3288_pin_fixup), + .pin_drive = rk3288_pin_drive, + .npin_drive = nitems(rk3288_pin_drive), + .gpio_bank = rk3288_gpio_bank, + .ngpio_bank = nitems(rk3288_gpio_bank), + .get_pd_offset = rk3288_get_pd_offset, + .get_syscon = rk3288_get_syscon, +}; + +static struct rk_pinctrl_gpio rk3328_gpio_bank[] = { + RK_GPIO(0, "gpio0"), + RK_GPIO(1, "gpio1"), + RK_GPIO(2, "gpio2"), + RK_GPIO(3, "gpio3"), +}; + static struct rk_pinctrl_bank rk3328_iomux_bank[] = { - { - .bank_num = 0, - .subbank_num = 0, - .offset = 0x00, - .nbits = 2, - }, - { - .bank_num = 0, - .subbank_num = 1, - .offset = 0x04, - .nbits = 2, - }, - { - .bank_num = 0, - .subbank_num = 2, - .offset = 0x08, - .nbits = 2, - }, - { - .bank_num = 0, - .subbank_num = 3, - .offset = 0xc, - .nbits = 2, - }, - { - .bank_num = 1, - .subbank_num = 0, - .offset = 0x10, - .nbits = 2, - }, - { - .bank_num = 1, - .subbank_num = 1, - .offset = 0x14, - .nbits = 2, - }, - { - .bank_num = 1, - .subbank_num = 2, - .offset = 0x18, - .nbits = 2, - }, - { - .bank_num = 1, - .subbank_num = 3, - .offset = 0x1C, - .nbits = 2, - }, - { - .bank_num = 2, - .subbank_num = 0, - .offset = 0x20, - .nbits = 2, - }, - { - .bank_num = 2, - .subbank_num = 1, - .offset = 0x24, - .nbits = 3, - }, - { - .bank_num = 2, - .subbank_num = 2, - .offset = 0x2c, - .nbits = 3, - }, - { - .bank_num = 2, - .subbank_num = 3, - .offset = 0x34, - .nbits = 2, - }, - { - .bank_num = 3, - .subbank_num = 0, - .offset = 0x38, - .nbits = 3, - }, - { - .bank_num = 3, - .subbank_num = 1, - .offset = 0x40, - .nbits = 3, - }, - { - .bank_num = 3, - .subbank_num = 2, - .offset = 0x48, - .nbits = 2, - }, - { - .bank_num = 3, - .subbank_num = 3, - .offset = 0x4c, - .nbits = 2, - }, + /* bank sub offs nbits */ + RK_IOMUX(0, 0, 0x0000, 2), + RK_IOMUX(0, 1, 0x0004, 2), + RK_IOMUX(0, 2, 0x0008, 2), + RK_IOMUX(0, 3, 0x000C, 2), + RK_IOMUX(1, 0, 0x0010, 2), + RK_IOMUX(1, 1, 0x0014, 2), + RK_IOMUX(1, 2, 0x0018, 2), + RK_IOMUX(1, 3, 0x001C, 2), + RK_IOMUX(2, 0, 0x0020, 2), + RK_IOMUX(2, 1, 0x0024, 3), + RK_IOMUX(2, 2, 0x002c, 3), + RK_IOMUX(2, 3, 0x0034, 2), + RK_IOMUX(3, 0, 0x0038, 3), + RK_IOMUX(3, 1, 0x0040, 3), + RK_IOMUX(3, 2, 0x0048, 2), + RK_IOMUX(3, 3, 0x004c, 2), }; static struct rk_pinctrl_pin_fixup rk3328_pin_fixup[] = { - { - .bank = 2, - .pin = 12, - .reg = 0x24, - .bit = 8, - .mask = 0x300, - }, - { - .bank = 2, - .pin = 15, - .reg = 0x28, - .bit = 0, - .mask = 0x7, - }, - { - .bank = 2, - .pin = 23, - .reg = 0x30, - .bit = 14, - .mask = 0x6000, - }, + /* bank pin reg bit mask */ + RK_PINFIX(2, 12, 0x24, 8, 0x300), + RK_PINFIX(2, 15, 0x28, 0, 0x7), + RK_PINFIX(2, 23, 0x30, 14, 0x6000), }; -#define RK_PINDRIVE(_bank, _subbank, _offset, _value, _ma) \ - { \ - .bank = _bank, \ - .subbank = _subbank, \ - .offset = _offset, \ - .value = _value, \ - .ma = _ma, \ - }, static struct rk_pinctrl_pin_drive rk3328_pin_drive[] = { - RK_PINDRIVE(0, 0, 0x200, 0, 2) - RK_PINDRIVE(0, 0, 0x200, 1, 4) - RK_PINDRIVE(0, 0, 0x200, 2, 8) - RK_PINDRIVE(0, 0, 0x200, 3, 12) + /* bank sub offs val ma */ + RK_PINDRIVE(0, 0, 0x200, 0, 2), + RK_PINDRIVE(0, 0, 0x200, 1, 4), + RK_PINDRIVE(0, 0, 0x200, 2, 8), + RK_PINDRIVE(0, 0, 0x200, 3, 12), - RK_PINDRIVE(0, 1, 0x204, 0, 2) - RK_PINDRIVE(0, 1, 0x204, 1, 4) - RK_PINDRIVE(0, 1, 0x204, 2, 8) - RK_PINDRIVE(0, 1, 0x204, 3, 12) + RK_PINDRIVE(0, 1, 0x204, 0, 2), + RK_PINDRIVE(0, 1, 0x204, 1, 4), + RK_PINDRIVE(0, 1, 0x204, 2, 8), + RK_PINDRIVE(0, 1, 0x204, 3, 12), - RK_PINDRIVE(0, 2, 0x208, 0, 2) - RK_PINDRIVE(0, 2, 0x208, 1, 4) - RK_PINDRIVE(0, 2, 0x208, 2, 8) - RK_PINDRIVE(0, 2, 0x208, 3, 12) + RK_PINDRIVE(0, 2, 0x208, 0, 2), + RK_PINDRIVE(0, 2, 0x208, 1, 4), + RK_PINDRIVE(0, 2, 0x208, 2, 8), + RK_PINDRIVE(0, 2, 0x208, 3, 12), - RK_PINDRIVE(0, 3, 0x20C, 0, 2) - RK_PINDRIVE(0, 3, 0x20C, 1, 4) - RK_PINDRIVE(0, 3, 0x20C, 2, 8) - RK_PINDRIVE(0, 3, 0x20C, 3, 12) + RK_PINDRIVE(0, 3, 0x20C, 0, 2), + RK_PINDRIVE(0, 3, 0x20C, 1, 4), + RK_PINDRIVE(0, 3, 0x20C, 2, 8), + RK_PINDRIVE(0, 3, 0x20C, 3, 12), - RK_PINDRIVE(1, 0, 0x210, 0, 2) - RK_PINDRIVE(1, 0, 0x210, 1, 4) - RK_PINDRIVE(1, 0, 0x210, 2, 8) - RK_PINDRIVE(1, 0, 0x210, 3, 12) + RK_PINDRIVE(1, 0, 0x210, 0, 2), + RK_PINDRIVE(1, 0, 0x210, 1, 4), + RK_PINDRIVE(1, 0, 0x210, 2, 8), + RK_PINDRIVE(1, 0, 0x210, 3, 12), - RK_PINDRIVE(1, 1, 0x214, 0, 2) - RK_PINDRIVE(1, 1, 0x214, 1, 4) - RK_PINDRIVE(1, 1, 0x214, 2, 8) - RK_PINDRIVE(1, 1, 0x214, 3, 12) + RK_PINDRIVE(1, 1, 0x214, 0, 2), + RK_PINDRIVE(1, 1, 0x214, 1, 4), + RK_PINDRIVE(1, 1, 0x214, 2, 8), + RK_PINDRIVE(1, 1, 0x214, 3, 12), - RK_PINDRIVE(1, 2, 0x218, 0, 2) - RK_PINDRIVE(1, 2, 0x218, 1, 4) - RK_PINDRIVE(1, 2, 0x218, 2, 8) - RK_PINDRIVE(1, 2, 0x218, 3, 12) + RK_PINDRIVE(1, 2, 0x218, 0, 2), + RK_PINDRIVE(1, 2, 0x218, 1, 4), + RK_PINDRIVE(1, 2, 0x218, 2, 8), + RK_PINDRIVE(1, 2, 0x218, 3, 12), - RK_PINDRIVE(1, 3, 0x21C, 0, 2) - RK_PINDRIVE(1, 3, 0x21C, 1, 4) - RK_PINDRIVE(1, 3, 0x21C, 2, 8) - RK_PINDRIVE(1, 3, 0x21C, 3, 12) + RK_PINDRIVE(1, 3, 0x21C, 0, 2), + RK_PINDRIVE(1, 3, 0x21C, 1, 4), + RK_PINDRIVE(1, 3, 0x21C, 2, 8), + RK_PINDRIVE(1, 3, 0x21C, 3, 12), - RK_PINDRIVE(2, 0, 0x220, 0, 2) - RK_PINDRIVE(2, 0, 0x220, 1, 4) - RK_PINDRIVE(2, 0, 0x220, 2, 8) - RK_PINDRIVE(2, 0, 0x220, 3, 12) + RK_PINDRIVE(2, 0, 0x220, 0, 2), + RK_PINDRIVE(2, 0, 0x220, 1, 4), + RK_PINDRIVE(2, 0, 0x220, 2, 8), + RK_PINDRIVE(2, 0, 0x220, 3, 12), - RK_PINDRIVE(2, 1, 0x224, 0, 2) - RK_PINDRIVE(2, 1, 0x224, 1, 4) - RK_PINDRIVE(2, 1, 0x224, 2, 8) - RK_PINDRIVE(2, 1, 0x224, 3, 12) + RK_PINDRIVE(2, 1, 0x224, 0, 2), + RK_PINDRIVE(2, 1, 0x224, 1, 4), + RK_PINDRIVE(2, 1, 0x224, 2, 8), + RK_PINDRIVE(2, 1, 0x224, 3, 12), - RK_PINDRIVE(2, 2, 0x228, 0, 2) - RK_PINDRIVE(2, 2, 0x228, 1, 4) - RK_PINDRIVE(2, 2, 0x228, 2, 8) - RK_PINDRIVE(2, 2, 0x228, 3, 12) + RK_PINDRIVE(2, 2, 0x228, 0, 2), + RK_PINDRIVE(2, 2, 0x228, 1, 4), + RK_PINDRIVE(2, 2, 0x228, 2, 8), + RK_PINDRIVE(2, 2, 0x228, 3, 12), - RK_PINDRIVE(2, 3, 0x22C, 0, 2) - RK_PINDRIVE(2, 3, 0x22C, 1, 4) - RK_PINDRIVE(2, 3, 0x22C, 2, 8) - RK_PINDRIVE(2, 3, 0x22C, 3, 12) + RK_PINDRIVE(2, 3, 0x22C, 0, 2), + RK_PINDRIVE(2, 3, 0x22C, 1, 4), + RK_PINDRIVE(2, 3, 0x22C, 2, 8), + RK_PINDRIVE(2, 3, 0x22C, 3, 12), - RK_PINDRIVE(3, 0, 0x230, 0, 2) - RK_PINDRIVE(3, 0, 0x230, 1, 4) - RK_PINDRIVE(3, 0, 0x230, 2, 8) - RK_PINDRIVE(3, 0, 0x230, 3, 12) + RK_PINDRIVE(3, 0, 0x230, 0, 2), + RK_PINDRIVE(3, 0, 0x230, 1, 4), + RK_PINDRIVE(3, 0, 0x230, 2, 8), + RK_PINDRIVE(3, 0, 0x230, 3, 12), - RK_PINDRIVE(3, 1, 0x234, 0, 2) - RK_PINDRIVE(3, 1, 0x234, 1, 4) - RK_PINDRIVE(3, 1, 0x234, 2, 8) - RK_PINDRIVE(3, 1, 0x234, 3, 12) + RK_PINDRIVE(3, 1, 0x234, 0, 2), + RK_PINDRIVE(3, 1, 0x234, 1, 4), + RK_PINDRIVE(3, 1, 0x234, 2, 8), + RK_PINDRIVE(3, 1, 0x234, 3, 12), - RK_PINDRIVE(3, 2, 0x238, 0, 2) - RK_PINDRIVE(3, 2, 0x238, 1, 4) - RK_PINDRIVE(3, 2, 0x238, 2, 8) - RK_PINDRIVE(3, 2, 0x238, 3, 12) + RK_PINDRIVE(3, 2, 0x238, 0, 2), + RK_PINDRIVE(3, 2, 0x238, 1, 4), + RK_PINDRIVE(3, 2, 0x238, 2, 8), + RK_PINDRIVE(3, 2, 0x238, 3, 12), - RK_PINDRIVE(3, 3, 0x23C, 0, 2) - RK_PINDRIVE(3, 3, 0x23C, 1, 4) - RK_PINDRIVE(3, 3, 0x23C, 2, 8) - RK_PINDRIVE(3, 3, 0x23C, 3, 12) + RK_PINDRIVE(3, 3, 0x23C, 0, 2), + RK_PINDRIVE(3, 3, 0x23C, 1, 4), + RK_PINDRIVE(3, 3, 0x23C, 2, 8), + RK_PINDRIVE(3, 3, 0x23C, 3, 12), }; static uint32_t rk3328_get_pd_offset(struct rk_pinctrl_softc *sc, uint32_t bank) { return (0x100); } static struct syscon * rk3328_get_syscon(struct rk_pinctrl_softc *sc, uint32_t bank) { return (sc->grf); } struct rk_pinctrl_conf rk3328_conf = { .iomux_conf = rk3328_iomux_bank, .iomux_nbanks = nitems(rk3328_iomux_bank), .pin_fixup = rk3328_pin_fixup, .npin_fixup = nitems(rk3328_pin_fixup), .pin_drive = rk3328_pin_drive, .npin_drive = nitems(rk3328_pin_drive), + .gpio_bank = rk3328_gpio_bank, + .ngpio_bank = nitems(rk3328_gpio_bank), .get_pd_offset = rk3328_get_pd_offset, .get_syscon = rk3328_get_syscon, }; +static struct rk_pinctrl_gpio rk3399_gpio_bank[] = { + RK_GPIO(0, "gpio0"), + RK_GPIO(1, "gpio1"), + RK_GPIO(2, "gpio2"), + RK_GPIO(3, "gpio3"), + RK_GPIO(4, "gpio4"), +}; + static struct rk_pinctrl_bank rk3399_iomux_bank[] = { - { - .bank_num = 0, - .subbank_num = 0, - .offset = 0x00, - .nbits = 2, - }, - { - .bank_num = 0, - .subbank_num = 1, - .offset = 0x04, - .nbits = 2, - }, - { - .bank_num = 0, - .subbank_num = 2, - .offset = 0x08, - .nbits = 2, - }, - { - .bank_num = 0, - .subbank_num = 3, - .offset = 0x0c, - .nbits = 2, - }, - { - .bank_num = 1, - .subbank_num = 0, - .offset = 0x10, - .nbits = 2, - }, - { - .bank_num = 1, - .subbank_num = 1, - .offset = 0x14, - .nbits = 2, - }, - { - .bank_num = 1, - .subbank_num = 2, - .offset = 0x18, - .nbits = 2, - }, - { - .bank_num = 1, - .subbank_num = 3, - .offset = 0x1c, - .nbits = 2, - }, - { - .bank_num = 2, - .subbank_num = 0, - .offset = 0xe000, - .nbits = 2, - }, - { - .bank_num = 2, - .subbank_num = 1, - .offset = 0xe004, - .nbits = 2, - }, - { - .bank_num = 2, - .subbank_num = 2, - .offset = 0xe008, - .nbits = 2, - }, - { - .bank_num = 2, - .subbank_num = 3, - .offset = 0xe00c, - .nbits = 2, - }, - { - .bank_num = 3, - .subbank_num = 0, - .offset = 0xe010, - .nbits = 2, - }, - { - .bank_num = 3, - .subbank_num = 1, - .offset = 0xe014, - .nbits = 2, - }, - { - .bank_num = 3, - .subbank_num = 2, - .offset = 0xe018, - .nbits = 2, - }, - { - .bank_num = 3, - .subbank_num = 3, - .offset = 0xe01c, - .nbits = 2, - }, - { - .bank_num = 4, - .subbank_num = 0, - .offset = 0xe020, - .nbits = 2, - }, - { - .bank_num = 4, - .subbank_num = 1, - .offset = 0xe024, - .nbits = 2, - }, - { - .bank_num = 4, - .subbank_num = 2, - .offset = 0xe028, - .nbits = 2, - }, - { - .bank_num = 4, - .subbank_num = 3, - .offset = 0xe02c, - .nbits = 2, - }, + /* bank sub offs nbits */ + RK_IOMUX(0, 0, 0x0000, 2), + RK_IOMUX(0, 1, 0x0004, 2), + RK_IOMUX(0, 2, 0x0008, 2), + RK_IOMUX(0, 3, 0x000C, 2), + RK_IOMUX(1, 0, 0x0010, 2), + RK_IOMUX(1, 1, 0x0014, 2), + RK_IOMUX(1, 2, 0x0018, 2), + RK_IOMUX(1, 3, 0x001C, 2), + RK_IOMUX(2, 0, 0xE000, 2), + RK_IOMUX(2, 1, 0xE004, 2), + RK_IOMUX(2, 2, 0xE008, 2), + RK_IOMUX(2, 3, 0xE00C, 2), + RK_IOMUX(3, 0, 0xE010, 2), + RK_IOMUX(3, 1, 0xE014, 2), + RK_IOMUX(3, 2, 0xE018, 2), + RK_IOMUX(3, 3, 0xE01C, 2), + RK_IOMUX(4, 0, 0xE020, 2), + RK_IOMUX(4, 1, 0xE024, 2), + RK_IOMUX(4, 2, 0xE028, 2), + RK_IOMUX(4, 3, 0xE02C, 2), }; static struct rk_pinctrl_pin_fixup rk3399_pin_fixup[] = {}; static struct rk_pinctrl_pin_drive rk3399_pin_drive[] = { + /* bank sub offs val ma */ /* GPIO0A */ - RK_PINDRIVE(0, 0, 0x80, 0, 5) - RK_PINDRIVE(0, 0, 0x80, 1, 10) - RK_PINDRIVE(0, 0, 0x80, 2, 15) - RK_PINDRIVE(0, 0, 0x80, 3, 20) + RK_PINDRIVE(0, 0, 0x80, 0, 5), + RK_PINDRIVE(0, 0, 0x80, 1, 10), + RK_PINDRIVE(0, 0, 0x80, 2, 15), + RK_PINDRIVE(0, 0, 0x80, 3, 20), /* GPIOB */ - RK_PINDRIVE(0, 1, 0x88, 0, 5) - RK_PINDRIVE(0, 1, 0x88, 1, 10) - RK_PINDRIVE(0, 1, 0x88, 2, 15) - RK_PINDRIVE(0, 1, 0x88, 3, 20) + RK_PINDRIVE(0, 1, 0x88, 0, 5), + RK_PINDRIVE(0, 1, 0x88, 1, 10), + RK_PINDRIVE(0, 1, 0x88, 2, 15), + RK_PINDRIVE(0, 1, 0x88, 3, 20), /* GPIO1A */ - RK_PINDRIVE(1, 0, 0xA0, 0, 3) - RK_PINDRIVE(1, 0, 0xA0, 1, 6) - RK_PINDRIVE(1, 0, 0xA0, 2, 9) - RK_PINDRIVE(1, 0, 0xA0, 3, 12) + RK_PINDRIVE(1, 0, 0xA0, 0, 3), + RK_PINDRIVE(1, 0, 0xA0, 1, 6), + RK_PINDRIVE(1, 0, 0xA0, 2, 9), + RK_PINDRIVE(1, 0, 0xA0, 3, 12), /* GPIO1B */ - RK_PINDRIVE(1, 1, 0xA8, 0, 3) - RK_PINDRIVE(1, 1, 0xA8, 1, 6) - RK_PINDRIVE(1, 1, 0xA8, 2, 9) - RK_PINDRIVE(1, 1, 0xA8, 3, 12) + RK_PINDRIVE(1, 1, 0xA8, 0, 3), + RK_PINDRIVE(1, 1, 0xA8, 1, 6), + RK_PINDRIVE(1, 1, 0xA8, 2, 9), + RK_PINDRIVE(1, 1, 0xA8, 3, 12), /* GPIO1C */ - RK_PINDRIVE(1, 2, 0xB0, 0, 3) - RK_PINDRIVE(1, 2, 0xB0, 1, 6) - RK_PINDRIVE(1, 2, 0xB0, 2, 9) - RK_PINDRIVE(1, 2, 0xB0, 3, 12) + RK_PINDRIVE(1, 2, 0xB0, 0, 3), + RK_PINDRIVE(1, 2, 0xB0, 1, 6), + RK_PINDRIVE(1, 2, 0xB0, 2, 9), + RK_PINDRIVE(1, 2, 0xB0, 3, 12), /* GPIO1D */ - RK_PINDRIVE(1, 3, 0xB8, 0, 3) - RK_PINDRIVE(1, 3, 0xB8, 1, 6) - RK_PINDRIVE(1, 3, 0xB8, 2, 9) - RK_PINDRIVE(1, 3, 0xB8, 3, 12) + RK_PINDRIVE(1, 3, 0xB8, 0, 3), + RK_PINDRIVE(1, 3, 0xB8, 1, 6), + RK_PINDRIVE(1, 3, 0xB8, 2, 9), + RK_PINDRIVE(1, 3, 0xB8, 3, 12), }; static uint32_t rk3399_get_pd_offset(struct rk_pinctrl_softc *sc, uint32_t bank) { if (bank < 2) return (0x40); - return (0xe040); + return (0xE040); } static struct syscon * rk3399_get_syscon(struct rk_pinctrl_softc *sc, uint32_t bank) { if (bank < 2) return (sc->pmu); return (sc->grf); } struct rk_pinctrl_conf rk3399_conf = { .iomux_conf = rk3399_iomux_bank, .iomux_nbanks = nitems(rk3399_iomux_bank), .pin_fixup = rk3399_pin_fixup, .npin_fixup = nitems(rk3399_pin_fixup), .pin_drive = rk3399_pin_drive, .npin_drive = nitems(rk3399_pin_drive), + .gpio_bank = rk3399_gpio_bank, + .ngpio_bank = nitems(rk3399_gpio_bank), .get_pd_offset = rk3399_get_pd_offset, .get_syscon = rk3399_get_syscon, }; static struct ofw_compat_data compat_data[] = { -#ifdef SOC_ROCKCHIP_RK3328 + {"rockchip,rk3288-pinctrl", (uintptr_t)&rk3288_conf}, {"rockchip,rk3328-pinctrl", (uintptr_t)&rk3328_conf}, -#endif -#ifdef SOC_ROCKCHIP_RK3399 {"rockchip,rk3399-pinctrl", (uintptr_t)&rk3399_conf}, -#endif {NULL, 0} }; static int rk_pinctrl_parse_bias(phandle_t node) { if (OF_hasprop(node, "bias-disable")) return (0); if (OF_hasprop(node, "bias-pull-up")) return (1); if (OF_hasprop(node, "bias-pull-down")) return (2); return (-1); } -static int rk_pinctrl_parse_drive(struct rk_pinctrl_softc *sc, phandle_t node, +static int +rk_pinctrl_parse_drive(struct rk_pinctrl_softc *sc, phandle_t node, uint32_t bank, uint32_t subbank, uint32_t *drive, uint32_t *offset) { uint32_t value; int i; if (OF_getencprop(node, "drive-strength", &value, sizeof(value)) != 0) return (-1); /* Map to the correct drive value */ for (i = 0; i < sc->conf->npin_drive; i++) { if (sc->conf->pin_drive[i].bank != bank && sc->conf->pin_drive[i].subbank != subbank) continue; if (sc->conf->pin_drive[i].ma == value) { *drive = sc->conf->pin_drive[i].value; return (0); } } return (-1); } static void rk_pinctrl_get_fixup(struct rk_pinctrl_softc *sc, uint32_t bank, uint32_t pin, uint32_t *reg, uint32_t *mask, uint32_t *bit) { int i; for (i = 0; i < sc->conf->npin_fixup; i++) if (sc->conf->pin_fixup[i].bank == bank && sc->conf->pin_fixup[i].pin == pin) { *reg = sc->conf->pin_fixup[i].reg; *mask = sc->conf->pin_fixup[i].mask; *bit = sc->conf->pin_fixup[i].bit; return; } } +static int +rk_pinctrl_handle_io(struct rk_pinctrl_softc *sc, phandle_t node, uint32_t bank, +uint32_t pin) +{ + bool have_cfg, have_direction, have_value; + uint32_t direction_value, pin_value; + struct rk_pinctrl_gpio *gpio; + int i, rv; + + have_cfg = false; + have_direction = false; + have_value = false; + + /* Get (subset of) GPIO pin properties. */ + if (OF_hasprop(node, "output-disable")) { + have_cfg = true; + have_direction = true; + direction_value = GPIO_PIN_INPUT; + } + + if (OF_hasprop(node, "output-enable")) { + have_cfg = true; + have_direction = true; + direction_value = GPIO_PIN_OUTPUT; + } + + if (OF_hasprop(node, "output-low")) { + have_cfg = true; + have_direction = true; + direction_value = GPIO_PIN_OUTPUT; + have_value = true; + pin_value = 0; + } + + if (OF_hasprop(node, "output-high")) { + have_cfg = true; + have_direction = true; + direction_value = GPIO_PIN_OUTPUT; + have_value = true; + pin_value = 1; + } + + if (!have_cfg) + return (0); + + /* Find gpio */ + gpio = NULL; + for(i = 0; i < sc->conf->ngpio_bank; i++) { + if (bank == sc->conf->gpio_bank[i].bank) { + gpio = sc->conf->gpio_bank + i; + break; + } + } + if (gpio == NULL) { + device_printf(sc->dev, "Cannot find GPIO bank %d\n", bank); + return (ENXIO); + } + if (gpio->gpio_dev == NULL) { + device_printf(sc->dev, + "No GPIO subdevice found for bank %d\n", bank); + return (ENXIO); + } + + rv = 0; + if (have_value) { + rv = GPIO_PIN_SET(gpio->gpio_dev, pin, pin_value); + if (rv != 0) { + device_printf(sc->dev, "Cannot set GPIO value: %d\n", + rv); + return (rv); + } + } + + if (have_direction) { + rv = GPIO_PIN_SETFLAGS(gpio->gpio_dev, pin, direction_value); + if (rv != 0) { + device_printf(sc->dev, + "Cannot set GPIO direction: %d\n", rv); + return (rv); + } + } + + return (0); +} + static void rk_pinctrl_configure_pin(struct rk_pinctrl_softc *sc, uint32_t *pindata) { phandle_t pin_conf; struct syscon *syscon; uint32_t bank, subbank, pin, function, bias; uint32_t bit, mask, reg, drive; - int i; + int i, rv; bank = pindata[0]; pin = pindata[1]; function = pindata[2]; pin_conf = OF_node_from_xref(pindata[3]); subbank = pin / 8; for (i = 0; i < sc->conf->iomux_nbanks; i++) - if (sc->conf->iomux_conf[i].bank_num == bank && - sc->conf->iomux_conf[i].subbank_num == subbank) + if (sc->conf->iomux_conf[i].bank == bank && + sc->conf->iomux_conf[i].subbank == subbank) break; if (i == sc->conf->iomux_nbanks) { device_printf(sc->dev, "Unknown pin %d in bank %d\n", pin, bank); return; } /* Find syscon */ syscon = sc->conf->get_syscon(sc, bank); /* Parse pin function */ reg = sc->conf->iomux_conf[i].offset; switch (sc->conf->iomux_conf[i].nbits) { + case 4: + if ((pin % 8) >= 4) + reg += 0x4; + bit = (pin % 4) * 4; + mask = (0xF << bit); + break; case 3: if ((pin % 8) >= 5) reg += 4; bit = (pin % 8 % 5) * 3; - mask = (0x7 << bit) << 16; + mask = (0x7 << bit); break; case 2: - default: bit = (pin % 8) * 2; - mask = (0x3 << bit) << 16; + mask = (0x3 << bit); break; + default: + device_printf(sc->dev, + "Unknown pin stride width %d in bank %d\n", + sc->conf->iomux_conf[i].nbits, bank); + return; } rk_pinctrl_get_fixup(sc, bank, pin, ®, &mask, &bit); - SYSCON_WRITE_4(syscon, reg, function << bit | mask); + /* + * NOTE: not all syscon registers uses hi-word write mask, thus + * register modify method should be used. + * XXXX We should not pass write mask to syscon register + * without hi-word write mask. + */ + SYSCON_MODIFY_4(syscon, reg, mask, function << bit | (mask << 16)); + /* Pull-Up/Down */ bias = rk_pinctrl_parse_bias(pin_conf); if (bias >= 0) { reg = sc->conf->get_pd_offset(sc, bank); reg += bank * 0x10 + ((pin / 8) * 0x4); bit = (pin % 8) * 2; mask = (0x3 << bit) << 16; - SYSCON_WRITE_4(syscon, reg, bias << bit | mask); + SYSCON_MODIFY_4(syscon, reg, mask, bias << bit | (mask << 16)); } /* Drive Strength */ - if (rk_pinctrl_parse_drive(sc, pin_conf, bank, subbank, &drive, ®) == 0) { + rv = rk_pinctrl_parse_drive(sc, pin_conf, bank, subbank, &drive, ®); + if (rv == 0) { bit = (pin % 8) * 2; mask = (0x3 << bit) << 16; - SYSCON_WRITE_4(syscon, reg, bias << bit | mask); + SYSCON_MODIFY_4(syscon, reg, mask, drive << bit | (mask << 16)); } + + /* Input/Outpot + default level */ + rv = rk_pinctrl_handle_io(sc, pin_conf, bank, pin); } static int rk_pinctrl_configure_pins(device_t dev, phandle_t cfgxref) { struct rk_pinctrl_softc *sc; phandle_t node; uint32_t *pins; int i, npins; sc = device_get_softc(dev); node = OF_node_from_xref(cfgxref); npins = OF_getencprop_alloc_multi(node, "rockchip,pins", sizeof(*pins), (void **)&pins); if (npins <= 0) return (ENOENT); for (i = 0; i != npins; i += 4) rk_pinctrl_configure_pin(sc, pins + i); return (0); } + static int +rk_pinctrl_register_gpio(struct rk_pinctrl_softc *sc, char *gpio_name, + device_t gpio_dev) +{ + int i; + + for(i = 0; i < sc->conf->ngpio_bank; i++) { + if (strcmp(gpio_name, sc->conf->gpio_bank[i].gpio_name) != 0) + continue; + sc->conf->gpio_bank[i].gpio_dev = gpio_dev; + return(0); + } + return (ENXIO); +} + +static int rk_pinctrl_probe(device_t dev) { if (!ofw_bus_status_okay(dev)) return (ENXIO); if (ofw_bus_search_compatible(dev, compat_data)->ocd_data == 0) return (ENXIO); device_set_desc(dev, "RockChip Pinctrl controller"); return (BUS_PROBE_DEFAULT); } static int rk_pinctrl_attach(device_t dev) { struct rk_pinctrl_softc *sc; phandle_t node; device_t cdev; + char *gpio_name, *eptr; + int rv; sc = device_get_softc(dev); sc->dev = dev; node = ofw_bus_get_node(dev); if (OF_hasprop(node, "rockchip,grf") && syscon_get_by_ofw_property(dev, node, "rockchip,grf", &sc->grf) != 0) { device_printf(dev, "cannot get grf driver handle\n"); return (ENXIO); } - // RK3399 has banks in PMU. RK3328 does not have a PMU. - if (ofw_bus_node_is_compatible(node, "rockchip,rk3399-pinctrl")) { + /* RK3399,RK3288 has banks in PMU. RK3328 does not have a PMU. */ + if (ofw_bus_node_is_compatible(node, "rockchip,rk3399-pinctrl") || + ofw_bus_node_is_compatible(node, "rockchip,rk3288-pinctrl")) { if (OF_hasprop(node, "rockchip,pmu") && syscon_get_by_ofw_property(dev, node, "rockchip,pmu", &sc->pmu) != 0) { device_printf(dev, "cannot get pmu driver handle\n"); return (ENXIO); } } sc->conf = (struct rk_pinctrl_conf *)ofw_bus_search_compatible(dev, compat_data)->ocd_data; fdt_pinctrl_register(dev, "rockchip,pins"); - fdt_pinctrl_configure_tree(dev); simplebus_init(dev, node); bus_generic_probe(dev); /* Attach child devices */ for (node = OF_child(node); node > 0; node = OF_peer(node)) { if (!ofw_bus_node_is_compatible(node, "rockchip,gpio-bank")) continue; + + rv = OF_getprop_alloc(node, "name", (void **)&gpio_name); + if (rv <= 0) { + device_printf(sc->dev, "Cannot GPIO subdevice name.\n"); + continue; + } + cdev = simplebus_add_device(dev, node, 0, NULL, -1, NULL); - if (cdev != NULL) - device_probe_and_attach(cdev); + if (cdev == NULL) { + device_printf(dev, " Cannot add GPIO subdevice: %s\n", + gpio_name); + OF_prop_free(gpio_name); + continue; + } + + rv = device_probe_and_attach(cdev); + if (rv != 0) { + device_printf(sc->dev, + "Cannot attach GPIO subdevice: %s\n", gpio_name); + OF_prop_free(gpio_name); + continue; + } + + /* Grep device name from name property */ + eptr = gpio_name; + strsep(&eptr, "@"); + if (gpio_name == eptr) { + device_printf(sc->dev, + "Unrecognized format of GPIO subdevice name: %s\n", + gpio_name); + OF_prop_free(gpio_name); + continue; + } + rv = rk_pinctrl_register_gpio(sc, gpio_name, cdev); + if (rv != 0) { + device_printf(sc->dev, + "Cannot register GPIO subdevice %s: %d\n", + gpio_name, rv); + OF_prop_free(gpio_name); + continue; + } + OF_prop_free(gpio_name); } + fdt_pinctrl_configure_tree(dev); + return (bus_generic_attach(dev)); } static int rk_pinctrl_detach(device_t dev) { return (EBUSY); } static device_method_t rk_pinctrl_methods[] = { /* Device interface */ - DEVMETHOD(device_probe, rk_pinctrl_probe), - DEVMETHOD(device_attach, rk_pinctrl_attach), - DEVMETHOD(device_detach, rk_pinctrl_detach), + DEVMETHOD(device_probe, rk_pinctrl_probe), + DEVMETHOD(device_attach, rk_pinctrl_attach), + DEVMETHOD(device_detach, rk_pinctrl_detach), /* fdt_pinctrl interface */ - DEVMETHOD(fdt_pinctrl_configure,rk_pinctrl_configure_pins), + DEVMETHOD(fdt_pinctrl_configure, rk_pinctrl_configure_pins), DEVMETHOD_END }; static devclass_t rk_pinctrl_devclass; DEFINE_CLASS_1(rk_pinctrl, rk_pinctrl_driver, rk_pinctrl_methods, sizeof(struct rk_pinctrl_softc), simplebus_driver); EARLY_DRIVER_MODULE(rk_pinctrl, simplebus, rk_pinctrl_driver, rk_pinctrl_devclass, 0, 0, BUS_PASS_INTERRUPT + BUS_PASS_ORDER_MIDDLE); MODULE_VERSION(rk_pinctrl, 1); Index: stable/12/sys/dev/dwc/if_dwc.c =================================================================== --- stable/12/sys/dev/dwc/if_dwc.c (revision 355175) +++ stable/12/sys/dev/dwc/if_dwc.c (revision 355176) @@ -1,1394 +1,1391 @@ /*- * Copyright (c) 2014 Ruslan Bukin * All rights reserved. * * This software was developed by SRI International and the University of * Cambridge Computer Laboratory under DARPA/AFRL contract (FA8750-10-C-0237) * ("CTSRD"), as part of the DARPA CRASH research programme. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. */ /* * Ethernet media access controller (EMAC) * Chapter 17, Altera Cyclone V Device Handbook (CV-5V2 2014.07.22) * * EMAC is an instance of the Synopsys DesignWare 3504-0 * Universal 10/100/1000 Ethernet MAC (DWC_gmac). */ #include __FBSDID("$FreeBSD$"); #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #ifdef EXT_RESOURCES #include #include #endif #include "if_dwc_if.h" #include "gpio_if.h" #include "miibus_if.h" #define READ4(_sc, _reg) \ bus_read_4((_sc)->res[0], _reg) #define WRITE4(_sc, _reg, _val) \ bus_write_4((_sc)->res[0], _reg, _val) #define MAC_RESET_TIMEOUT 100 #define WATCHDOG_TIMEOUT_SECS 5 #define STATS_HARVEST_INTERVAL 2 #define DWC_LOCK(sc) mtx_lock(&(sc)->mtx) #define DWC_UNLOCK(sc) mtx_unlock(&(sc)->mtx) #define DWC_ASSERT_LOCKED(sc) mtx_assert(&(sc)->mtx, MA_OWNED) #define DWC_ASSERT_UNLOCKED(sc) mtx_assert(&(sc)->mtx, MA_NOTOWNED) #define DDESC_TDES0_OWN (1U << 31) #define DDESC_TDES0_TXINT (1U << 30) #define DDESC_TDES0_TXLAST (1U << 29) #define DDESC_TDES0_TXFIRST (1U << 28) #define DDESC_TDES0_TXCRCDIS (1U << 27) #define DDESC_TDES0_TXRINGEND (1U << 21) #define DDESC_TDES0_TXCHAIN (1U << 20) #define DDESC_RDES0_OWN (1U << 31) #define DDESC_RDES0_FL_MASK 0x3fff #define DDESC_RDES0_FL_SHIFT 16 /* Frame Length */ #define DDESC_RDES1_CHAINED (1U << 14) /* Alt descriptor bits. */ #define DDESC_CNTL_TXINT (1U << 31) #define DDESC_CNTL_TXLAST (1U << 30) #define DDESC_CNTL_TXFIRST (1U << 29) #define DDESC_CNTL_TXCRCDIS (1U << 26) #define DDESC_CNTL_TXRINGEND (1U << 25) #define DDESC_CNTL_TXCHAIN (1U << 24) #define DDESC_CNTL_CHAINED (1U << 24) /* * A hardware buffer descriptor. Rx and Tx buffers have the same descriptor * layout, but the bits in the fields have different meanings. */ struct dwc_hwdesc { uint32_t tdes0; /* status for alt layout */ uint32_t tdes1; /* cntl for alt layout */ uint32_t addr; /* pointer to buffer data */ uint32_t addr_next; /* link to next descriptor */ }; /* * The hardware imposes alignment restrictions on various objects involved in * DMA transfers. These values are expressed in bytes (not bits). */ #define DWC_DESC_RING_ALIGN 2048 static struct resource_spec dwc_spec[] = { { SYS_RES_MEMORY, 0, RF_ACTIVE }, { SYS_RES_IRQ, 0, RF_ACTIVE }, { -1, 0 } }; static void dwc_txfinish_locked(struct dwc_softc *sc); static void dwc_rxfinish_locked(struct dwc_softc *sc); static void dwc_stop_locked(struct dwc_softc *sc); static void dwc_setup_rxfilter(struct dwc_softc *sc); static inline uint32_t next_rxidx(struct dwc_softc *sc, uint32_t curidx) { return ((curidx + 1) % RX_DESC_COUNT); } static inline uint32_t next_txidx(struct dwc_softc *sc, uint32_t curidx) { return ((curidx + 1) % TX_DESC_COUNT); } static void dwc_get1paddr(void *arg, bus_dma_segment_t *segs, int nsegs, int error) { if (error != 0) return; *(bus_addr_t *)arg = segs[0].ds_addr; } inline static uint32_t dwc_setup_txdesc(struct dwc_softc *sc, int idx, bus_addr_t paddr, uint32_t len) { uint32_t flags; uint32_t nidx; nidx = next_txidx(sc, idx); /* Addr/len 0 means we're clearing the descriptor after xmit done. */ if (paddr == 0 || len == 0) { flags = 0; --sc->txcount; } else { if (sc->mactype == DWC_GMAC_ALT_DESC) flags = DDESC_CNTL_TXCHAIN | DDESC_CNTL_TXFIRST | DDESC_CNTL_TXLAST | DDESC_CNTL_TXINT; else flags = DDESC_TDES0_TXCHAIN | DDESC_TDES0_TXFIRST | DDESC_TDES0_TXLAST | DDESC_TDES0_TXINT; ++sc->txcount; } sc->txdesc_ring[idx].addr = (uint32_t)(paddr); if (sc->mactype == DWC_GMAC_ALT_DESC) { sc->txdesc_ring[idx].tdes0 = 0; sc->txdesc_ring[idx].tdes1 = flags | len; } else { sc->txdesc_ring[idx].tdes0 = flags; sc->txdesc_ring[idx].tdes1 = len; } if (paddr && len) { wmb(); sc->txdesc_ring[idx].tdes0 |= DDESC_TDES0_OWN; wmb(); } return (nidx); } static int dwc_setup_txbuf(struct dwc_softc *sc, int idx, struct mbuf **mp) { struct bus_dma_segment seg; int error, nsegs; struct mbuf * m; if ((m = m_defrag(*mp, M_NOWAIT)) == NULL) return (ENOMEM); *mp = m; error = bus_dmamap_load_mbuf_sg(sc->txbuf_tag, sc->txbuf_map[idx].map, m, &seg, &nsegs, 0); if (error != 0) { return (ENOMEM); } KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs)); bus_dmamap_sync(sc->txbuf_tag, sc->txbuf_map[idx].map, BUS_DMASYNC_PREWRITE); sc->txbuf_map[idx].mbuf = m; dwc_setup_txdesc(sc, idx, seg.ds_addr, seg.ds_len); return (0); } static void dwc_txstart_locked(struct dwc_softc *sc) { struct ifnet *ifp; struct mbuf *m; int enqueued; DWC_ASSERT_LOCKED(sc); if (!sc->link_is_up) return; ifp = sc->ifp; if (ifp->if_drv_flags & IFF_DRV_OACTIVE) { return; } enqueued = 0; for (;;) { if (sc->txcount == (TX_DESC_COUNT-1)) { ifp->if_drv_flags |= IFF_DRV_OACTIVE; break; } IFQ_DRV_DEQUEUE(&ifp->if_snd, m); if (m == NULL) break; if (dwc_setup_txbuf(sc, sc->tx_idx_head, &m) != 0) { IFQ_DRV_PREPEND(&ifp->if_snd, m); break; } BPF_MTAP(ifp, m); sc->tx_idx_head = next_txidx(sc, sc->tx_idx_head); ++enqueued; } if (enqueued != 0) { WRITE4(sc, TRANSMIT_POLL_DEMAND, 0x1); sc->tx_watchdog_count = WATCHDOG_TIMEOUT_SECS; } } static void dwc_txstart(struct ifnet *ifp) { struct dwc_softc *sc = ifp->if_softc; DWC_LOCK(sc); dwc_txstart_locked(sc); DWC_UNLOCK(sc); } static void dwc_stop_locked(struct dwc_softc *sc) { struct ifnet *ifp; uint32_t reg; DWC_ASSERT_LOCKED(sc); ifp = sc->ifp; ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); sc->tx_watchdog_count = 0; sc->stats_harvest_count = 0; callout_stop(&sc->dwc_callout); /* Stop DMA TX */ reg = READ4(sc, OPERATION_MODE); reg &= ~(MODE_ST); WRITE4(sc, OPERATION_MODE, reg); /* Flush TX */ reg = READ4(sc, OPERATION_MODE); reg |= (MODE_FTF); WRITE4(sc, OPERATION_MODE, reg); /* Stop transmitters */ reg = READ4(sc, MAC_CONFIGURATION); reg &= ~(CONF_TE | CONF_RE); WRITE4(sc, MAC_CONFIGURATION, reg); /* Stop DMA RX */ reg = READ4(sc, OPERATION_MODE); reg &= ~(MODE_SR); WRITE4(sc, OPERATION_MODE, reg); } static void dwc_clear_stats(struct dwc_softc *sc) { uint32_t reg; reg = READ4(sc, MMC_CONTROL); reg |= (MMC_CONTROL_CNTRST); WRITE4(sc, MMC_CONTROL, reg); } static void dwc_harvest_stats(struct dwc_softc *sc) { struct ifnet *ifp; /* We don't need to harvest too often. */ if (++sc->stats_harvest_count < STATS_HARVEST_INTERVAL) return; sc->stats_harvest_count = 0; ifp = sc->ifp; if_inc_counter(ifp, IFCOUNTER_IPACKETS, READ4(sc, RXFRAMECOUNT_GB)); if_inc_counter(ifp, IFCOUNTER_IMCASTS, READ4(sc, RXMULTICASTFRAMES_G)); if_inc_counter(ifp, IFCOUNTER_IERRORS, READ4(sc, RXOVERSIZE_G) + READ4(sc, RXUNDERSIZE_G) + READ4(sc, RXCRCERROR) + READ4(sc, RXALIGNMENTERROR) + READ4(sc, RXRUNTERROR) + READ4(sc, RXJABBERERROR) + READ4(sc, RXLENGTHERROR)); if_inc_counter(ifp, IFCOUNTER_OPACKETS, READ4(sc, TXFRAMECOUNT_G)); if_inc_counter(ifp, IFCOUNTER_OMCASTS, READ4(sc, TXMULTICASTFRAMES_G)); if_inc_counter(ifp, IFCOUNTER_OERRORS, READ4(sc, TXOVERSIZE_G) + READ4(sc, TXEXCESSDEF) + READ4(sc, TXCARRIERERR) + READ4(sc, TXUNDERFLOWERROR)); if_inc_counter(ifp, IFCOUNTER_COLLISIONS, READ4(sc, TXEXESSCOL) + READ4(sc, TXLATECOL)); dwc_clear_stats(sc); } static void dwc_tick(void *arg) { struct dwc_softc *sc; struct ifnet *ifp; int link_was_up; sc = arg; DWC_ASSERT_LOCKED(sc); ifp = sc->ifp; if (!(ifp->if_drv_flags & IFF_DRV_RUNNING)) return; /* * Typical tx watchdog. If this fires it indicates that we enqueued * packets for output and never got a txdone interrupt for them. Maybe * it's a missed interrupt somehow, just pretend we got one. */ if (sc->tx_watchdog_count > 0) { if (--sc->tx_watchdog_count == 0) { dwc_txfinish_locked(sc); } } /* Gather stats from hardware counters. */ dwc_harvest_stats(sc); /* Check the media status. */ link_was_up = sc->link_is_up; mii_tick(sc->mii_softc); if (sc->link_is_up && !link_was_up) dwc_txstart_locked(sc); /* Schedule another check one second from now. */ callout_reset(&sc->dwc_callout, hz, dwc_tick, sc); } static void dwc_init_locked(struct dwc_softc *sc) { struct ifnet *ifp = sc->ifp; uint32_t reg; DWC_ASSERT_LOCKED(sc); if (ifp->if_drv_flags & IFF_DRV_RUNNING) return; ifp->if_drv_flags |= IFF_DRV_RUNNING; dwc_setup_rxfilter(sc); /* Initializa DMA and enable transmitters */ reg = READ4(sc, OPERATION_MODE); reg |= (MODE_TSF | MODE_OSF | MODE_FUF); reg &= ~(MODE_RSF); reg |= (MODE_RTC_LEV32 << MODE_RTC_SHIFT); WRITE4(sc, OPERATION_MODE, reg); WRITE4(sc, INTERRUPT_ENABLE, INT_EN_DEFAULT); /* Start DMA */ reg = READ4(sc, OPERATION_MODE); reg |= (MODE_ST | MODE_SR); WRITE4(sc, OPERATION_MODE, reg); /* Enable transmitters */ reg = READ4(sc, MAC_CONFIGURATION); reg |= (CONF_JD | CONF_ACS | CONF_BE); reg |= (CONF_TE | CONF_RE); WRITE4(sc, MAC_CONFIGURATION, reg); /* * Call mii_mediachg() which will call back into dwc_miibus_statchg() * to set up the remaining config registers based on current media. */ mii_mediachg(sc->mii_softc); callout_reset(&sc->dwc_callout, hz, dwc_tick, sc); } static void dwc_init(void *if_softc) { struct dwc_softc *sc = if_softc; DWC_LOCK(sc); dwc_init_locked(sc); DWC_UNLOCK(sc); } inline static uint32_t dwc_setup_rxdesc(struct dwc_softc *sc, int idx, bus_addr_t paddr) { uint32_t nidx; sc->rxdesc_ring[idx].addr = (uint32_t)paddr; nidx = next_rxidx(sc, idx); sc->rxdesc_ring[idx].addr_next = sc->rxdesc_ring_paddr + \ (nidx * sizeof(struct dwc_hwdesc)); if (sc->mactype == DWC_GMAC_ALT_DESC) sc->rxdesc_ring[idx].tdes1 = DDESC_CNTL_CHAINED | RX_MAX_PACKET; else sc->rxdesc_ring[idx].tdes1 = DDESC_RDES1_CHAINED | MCLBYTES; wmb(); sc->rxdesc_ring[idx].tdes0 = DDESC_RDES0_OWN; wmb(); return (nidx); } static int dwc_setup_rxbuf(struct dwc_softc *sc, int idx, struct mbuf *m) { struct bus_dma_segment seg; int error, nsegs; m_adj(m, ETHER_ALIGN); error = bus_dmamap_load_mbuf_sg(sc->rxbuf_tag, sc->rxbuf_map[idx].map, m, &seg, &nsegs, 0); if (error != 0) { return (error); } KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs)); bus_dmamap_sync(sc->rxbuf_tag, sc->rxbuf_map[idx].map, BUS_DMASYNC_PREREAD); sc->rxbuf_map[idx].mbuf = m; dwc_setup_rxdesc(sc, idx, seg.ds_addr); return (0); } static struct mbuf * dwc_alloc_mbufcl(struct dwc_softc *sc) { struct mbuf *m; m = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR); if (m != NULL) m->m_pkthdr.len = m->m_len = m->m_ext.ext_size; return (m); } static void dwc_media_status(struct ifnet * ifp, struct ifmediareq *ifmr) { struct dwc_softc *sc; struct mii_data *mii; sc = ifp->if_softc; mii = sc->mii_softc; DWC_LOCK(sc); mii_pollstat(mii); ifmr->ifm_active = mii->mii_media_active; ifmr->ifm_status = mii->mii_media_status; DWC_UNLOCK(sc); } static int dwc_media_change_locked(struct dwc_softc *sc) { return (mii_mediachg(sc->mii_softc)); } static int dwc_media_change(struct ifnet * ifp) { struct dwc_softc *sc; int error; sc = ifp->if_softc; DWC_LOCK(sc); error = dwc_media_change_locked(sc); DWC_UNLOCK(sc); return (error); } static const uint8_t nibbletab[] = { /* 0x0 0000 -> 0000 */ 0x0, /* 0x1 0001 -> 1000 */ 0x8, /* 0x2 0010 -> 0100 */ 0x4, /* 0x3 0011 -> 1100 */ 0xc, /* 0x4 0100 -> 0010 */ 0x2, /* 0x5 0101 -> 1010 */ 0xa, /* 0x6 0110 -> 0110 */ 0x6, /* 0x7 0111 -> 1110 */ 0xe, /* 0x8 1000 -> 0001 */ 0x1, /* 0x9 1001 -> 1001 */ 0x9, /* 0xa 1010 -> 0101 */ 0x5, /* 0xb 1011 -> 1101 */ 0xd, /* 0xc 1100 -> 0011 */ 0x3, /* 0xd 1101 -> 1011 */ 0xb, /* 0xe 1110 -> 0111 */ 0x7, /* 0xf 1111 -> 1111 */ 0xf, }; static uint8_t bitreverse(uint8_t x) { return (nibbletab[x & 0xf] << 4) | nibbletab[x >> 4]; } static void dwc_setup_rxfilter(struct dwc_softc *sc) { struct ifmultiaddr *ifma; struct ifnet *ifp; uint8_t *eaddr, val; uint32_t crc, ffval, hashbit, hashreg, hi, lo, hash[8]; int nhash, i; DWC_ASSERT_LOCKED(sc); ifp = sc->ifp; nhash = sc->mactype == DWC_GMAC_ALT_DESC ? 2 : 8; /* * Set the multicast (group) filter hash. */ if ((ifp->if_flags & IFF_ALLMULTI) != 0) { ffval = (FRAME_FILTER_PM); for (i = 0; i < nhash; i++) hash[i] = ~0; } else { ffval = (FRAME_FILTER_HMC); for (i = 0; i < nhash; i++) hash[i] = 0; if_maddr_rlock(ifp); CK_STAILQ_FOREACH(ifma, &sc->ifp->if_multiaddrs, ifma_link) { if (ifma->ifma_addr->sa_family != AF_LINK) continue; crc = ether_crc32_le(LLADDR((struct sockaddr_dl *) ifma->ifma_addr), ETHER_ADDR_LEN); /* Take lower 8 bits and reverse it */ val = bitreverse(~crc & 0xff); if (sc->mactype == DWC_GMAC_ALT_DESC) val >>= nhash; /* Only need lower 6 bits */ hashreg = (val >> 5); hashbit = (val & 31); hash[hashreg] |= (1 << hashbit); } if_maddr_runlock(ifp); } /* * Set the individual address filter hash. */ if (ifp->if_flags & IFF_PROMISC) ffval |= (FRAME_FILTER_PR); /* * Set the primary address. */ eaddr = IF_LLADDR(ifp); lo = eaddr[0] | (eaddr[1] << 8) | (eaddr[2] << 16) | (eaddr[3] << 24); hi = eaddr[4] | (eaddr[5] << 8); WRITE4(sc, MAC_ADDRESS_LOW(0), lo); WRITE4(sc, MAC_ADDRESS_HIGH(0), hi); WRITE4(sc, MAC_FRAME_FILTER, ffval); if (sc->mactype == DWC_GMAC_ALT_DESC) { WRITE4(sc, GMAC_MAC_HTLOW, hash[0]); WRITE4(sc, GMAC_MAC_HTHIGH, hash[1]); } else { for (i = 0; i < nhash; i++) WRITE4(sc, HASH_TABLE_REG(i), hash[i]); } } static int dwc_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data) { struct dwc_softc *sc; struct mii_data *mii; struct ifreq *ifr; int mask, error; sc = ifp->if_softc; ifr = (struct ifreq *)data; error = 0; switch (cmd) { case SIOCSIFFLAGS: DWC_LOCK(sc); if (ifp->if_flags & IFF_UP) { if (ifp->if_drv_flags & IFF_DRV_RUNNING) { if ((ifp->if_flags ^ sc->if_flags) & (IFF_PROMISC | IFF_ALLMULTI)) dwc_setup_rxfilter(sc); } else { if (!sc->is_detaching) dwc_init_locked(sc); } } else { if (ifp->if_drv_flags & IFF_DRV_RUNNING) dwc_stop_locked(sc); } sc->if_flags = ifp->if_flags; DWC_UNLOCK(sc); break; case SIOCADDMULTI: case SIOCDELMULTI: if (ifp->if_drv_flags & IFF_DRV_RUNNING) { DWC_LOCK(sc); dwc_setup_rxfilter(sc); DWC_UNLOCK(sc); } break; case SIOCSIFMEDIA: case SIOCGIFMEDIA: mii = sc->mii_softc; error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, cmd); break; case SIOCSIFCAP: mask = ifp->if_capenable ^ ifr->ifr_reqcap; if (mask & IFCAP_VLAN_MTU) { /* No work to do except acknowledge the change took */ ifp->if_capenable ^= IFCAP_VLAN_MTU; } break; default: error = ether_ioctl(ifp, cmd, data); break; } return (error); } static void dwc_txfinish_locked(struct dwc_softc *sc) { struct dwc_bufmap *bmap; struct dwc_hwdesc *desc; struct ifnet *ifp; DWC_ASSERT_LOCKED(sc); ifp = sc->ifp; while (sc->tx_idx_tail != sc->tx_idx_head) { desc = &sc->txdesc_ring[sc->tx_idx_tail]; if ((desc->tdes0 & DDESC_TDES0_OWN) != 0) break; bmap = &sc->txbuf_map[sc->tx_idx_tail]; bus_dmamap_sync(sc->txbuf_tag, bmap->map, BUS_DMASYNC_POSTWRITE); bus_dmamap_unload(sc->txbuf_tag, bmap->map); m_freem(bmap->mbuf); bmap->mbuf = NULL; dwc_setup_txdesc(sc, sc->tx_idx_tail, 0, 0); sc->tx_idx_tail = next_txidx(sc, sc->tx_idx_tail); ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; if_inc_counter(ifp, IFCOUNTER_OPACKETS, 1); } /* If there are no buffers outstanding, muzzle the watchdog. */ if (sc->tx_idx_tail == sc->tx_idx_head) { sc->tx_watchdog_count = 0; } } static void dwc_rxfinish_locked(struct dwc_softc *sc) { struct ifnet *ifp; struct mbuf *m0; struct mbuf *m; int error, idx, len; uint32_t rdes0; ifp = sc->ifp; for (;;) { idx = sc->rx_idx; rdes0 = sc->rxdesc_ring[idx].tdes0; if ((rdes0 & DDESC_RDES0_OWN) != 0) break; bus_dmamap_sync(sc->rxbuf_tag, sc->rxbuf_map[idx].map, BUS_DMASYNC_POSTREAD); bus_dmamap_unload(sc->rxbuf_tag, sc->rxbuf_map[idx].map); len = (rdes0 >> DDESC_RDES0_FL_SHIFT) & DDESC_RDES0_FL_MASK; if (len != 0) { m = sc->rxbuf_map[idx].mbuf; m->m_pkthdr.rcvif = ifp; m->m_pkthdr.len = len; m->m_len = len; if_inc_counter(ifp, IFCOUNTER_IPACKETS, 1); /* Remove trailing FCS */ m_adj(m, -ETHER_CRC_LEN); DWC_UNLOCK(sc); (*ifp->if_input)(ifp, m); DWC_LOCK(sc); } else { /* XXX Zero-length packet ? */ } if ((m0 = dwc_alloc_mbufcl(sc)) != NULL) { if ((error = dwc_setup_rxbuf(sc, idx, m0)) != 0) { /* * XXX Now what? * We've got a hole in the rx ring. */ } } else if_inc_counter(sc->ifp, IFCOUNTER_IQDROPS, 1); sc->rx_idx = next_rxidx(sc, sc->rx_idx); } } static void dwc_intr(void *arg) { struct dwc_softc *sc; uint32_t reg; sc = arg; DWC_LOCK(sc); reg = READ4(sc, INTERRUPT_STATUS); if (reg) READ4(sc, SGMII_RGMII_SMII_CTRL_STATUS); reg = READ4(sc, DMA_STATUS); if (reg & DMA_STATUS_NIS) { if (reg & DMA_STATUS_RI) dwc_rxfinish_locked(sc); if (reg & DMA_STATUS_TI) { dwc_txfinish_locked(sc); dwc_txstart_locked(sc); } } if (reg & DMA_STATUS_AIS) { if (reg & DMA_STATUS_FBI) { /* Fatal bus error */ device_printf(sc->dev, "Ethernet DMA error, restarting controller.\n"); dwc_stop_locked(sc); dwc_init_locked(sc); } } WRITE4(sc, DMA_STATUS, reg & DMA_STATUS_INTR_MASK); DWC_UNLOCK(sc); } static int setup_dma(struct dwc_softc *sc) { struct mbuf *m; int error; int nidx; int idx; /* * Set up TX descriptor ring, descriptors, and dma maps. */ error = bus_dma_tag_create( bus_get_dma_tag(sc->dev), /* Parent tag. */ DWC_DESC_RING_ALIGN, 0, /* alignment, boundary */ BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ BUS_SPACE_MAXADDR, /* highaddr */ NULL, NULL, /* filter, filterarg */ TX_DESC_SIZE, 1, /* maxsize, nsegments */ TX_DESC_SIZE, /* maxsegsize */ 0, /* flags */ NULL, NULL, /* lockfunc, lockarg */ &sc->txdesc_tag); if (error != 0) { device_printf(sc->dev, "could not create TX ring DMA tag.\n"); goto out; } error = bus_dmamem_alloc(sc->txdesc_tag, (void**)&sc->txdesc_ring, BUS_DMA_COHERENT | BUS_DMA_WAITOK | BUS_DMA_ZERO, &sc->txdesc_map); if (error != 0) { device_printf(sc->dev, "could not allocate TX descriptor ring.\n"); goto out; } error = bus_dmamap_load(sc->txdesc_tag, sc->txdesc_map, sc->txdesc_ring, TX_DESC_SIZE, dwc_get1paddr, &sc->txdesc_ring_paddr, 0); if (error != 0) { device_printf(sc->dev, "could not load TX descriptor ring map.\n"); goto out; } for (idx = 0; idx < TX_DESC_COUNT; idx++) { nidx = next_txidx(sc, idx); sc->txdesc_ring[idx].addr_next = sc->txdesc_ring_paddr + (nidx * sizeof(struct dwc_hwdesc)); } error = bus_dma_tag_create( bus_get_dma_tag(sc->dev), /* Parent tag. */ 1, 0, /* alignment, boundary */ BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ BUS_SPACE_MAXADDR, /* highaddr */ NULL, NULL, /* filter, filterarg */ MCLBYTES, 1, /* maxsize, nsegments */ MCLBYTES, /* maxsegsize */ 0, /* flags */ NULL, NULL, /* lockfunc, lockarg */ &sc->txbuf_tag); if (error != 0) { device_printf(sc->dev, "could not create TX ring DMA tag.\n"); goto out; } for (idx = 0; idx < TX_DESC_COUNT; idx++) { error = bus_dmamap_create(sc->txbuf_tag, BUS_DMA_COHERENT, &sc->txbuf_map[idx].map); if (error != 0) { device_printf(sc->dev, "could not create TX buffer DMA map.\n"); goto out; } dwc_setup_txdesc(sc, idx, 0, 0); } /* * Set up RX descriptor ring, descriptors, dma maps, and mbufs. */ error = bus_dma_tag_create( bus_get_dma_tag(sc->dev), /* Parent tag. */ DWC_DESC_RING_ALIGN, 0, /* alignment, boundary */ BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ BUS_SPACE_MAXADDR, /* highaddr */ NULL, NULL, /* filter, filterarg */ RX_DESC_SIZE, 1, /* maxsize, nsegments */ RX_DESC_SIZE, /* maxsegsize */ 0, /* flags */ NULL, NULL, /* lockfunc, lockarg */ &sc->rxdesc_tag); if (error != 0) { device_printf(sc->dev, "could not create RX ring DMA tag.\n"); goto out; } error = bus_dmamem_alloc(sc->rxdesc_tag, (void **)&sc->rxdesc_ring, BUS_DMA_COHERENT | BUS_DMA_WAITOK | BUS_DMA_ZERO, &sc->rxdesc_map); if (error != 0) { device_printf(sc->dev, "could not allocate RX descriptor ring.\n"); goto out; } error = bus_dmamap_load(sc->rxdesc_tag, sc->rxdesc_map, sc->rxdesc_ring, RX_DESC_SIZE, dwc_get1paddr, &sc->rxdesc_ring_paddr, 0); if (error != 0) { device_printf(sc->dev, "could not load RX descriptor ring map.\n"); goto out; } error = bus_dma_tag_create( bus_get_dma_tag(sc->dev), /* Parent tag. */ 1, 0, /* alignment, boundary */ BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ BUS_SPACE_MAXADDR, /* highaddr */ NULL, NULL, /* filter, filterarg */ MCLBYTES, 1, /* maxsize, nsegments */ MCLBYTES, /* maxsegsize */ 0, /* flags */ NULL, NULL, /* lockfunc, lockarg */ &sc->rxbuf_tag); if (error != 0) { device_printf(sc->dev, "could not create RX buf DMA tag.\n"); goto out; } for (idx = 0; idx < RX_DESC_COUNT; idx++) { error = bus_dmamap_create(sc->rxbuf_tag, BUS_DMA_COHERENT, &sc->rxbuf_map[idx].map); if (error != 0) { device_printf(sc->dev, "could not create RX buffer DMA map.\n"); goto out; } if ((m = dwc_alloc_mbufcl(sc)) == NULL) { device_printf(sc->dev, "Could not alloc mbuf\n"); error = ENOMEM; goto out; } if ((error = dwc_setup_rxbuf(sc, idx, m)) != 0) { device_printf(sc->dev, "could not create new RX buffer.\n"); goto out; } } out: if (error != 0) return (ENXIO); return (0); } static int dwc_get_hwaddr(struct dwc_softc *sc, uint8_t *hwaddr) { uint32_t hi, lo, rnd; /* * Try to recover a MAC address from the running hardware. If there's * something non-zero there, assume the bootloader did the right thing * and just use it. * * Otherwise, set the address to a convenient locally assigned address, * 'bsd' + random 24 low-order bits. 'b' is 0x62, which has the locally * assigned bit set, and the broadcast/multicast bit clear. */ lo = READ4(sc, MAC_ADDRESS_LOW(0)); hi = READ4(sc, MAC_ADDRESS_HIGH(0)) & 0xffff; if ((lo != 0xffffffff) || (hi != 0xffff)) { hwaddr[0] = (lo >> 0) & 0xff; hwaddr[1] = (lo >> 8) & 0xff; hwaddr[2] = (lo >> 16) & 0xff; hwaddr[3] = (lo >> 24) & 0xff; hwaddr[4] = (hi >> 0) & 0xff; hwaddr[5] = (hi >> 8) & 0xff; } else { rnd = arc4random() & 0x00ffffff; hwaddr[0] = 'b'; hwaddr[1] = 's'; hwaddr[2] = 'd'; hwaddr[3] = rnd >> 16; hwaddr[4] = rnd >> 8; hwaddr[5] = rnd >> 0; } return (0); } #define GPIO_ACTIVE_LOW 1 static int dwc_reset(device_t dev) { pcell_t gpio_prop[4]; pcell_t delay_prop[3]; phandle_t node, gpio_node; device_t gpio; uint32_t pin, flags; uint32_t pin_value; node = ofw_bus_get_node(dev); if (OF_getencprop(node, "snps,reset-gpio", gpio_prop, sizeof(gpio_prop)) <= 0) return (0); if (OF_getencprop(node, "snps,reset-delays-us", delay_prop, sizeof(delay_prop)) <= 0) { device_printf(dev, "Wrong property for snps,reset-delays-us"); return (ENXIO); } gpio_node = OF_node_from_xref(gpio_prop[0]); if ((gpio = OF_device_from_xref(gpio_prop[0])) == NULL) { device_printf(dev, "Can't find gpio controller for phy reset\n"); return (ENXIO); } if (GPIO_MAP_GPIOS(gpio, node, gpio_node, nitems(gpio_prop) - 1, gpio_prop + 1, &pin, &flags) != 0) { device_printf(dev, "Can't map gpio for phy reset\n"); return (ENXIO); } pin_value = GPIO_PIN_LOW; if (OF_hasprop(node, "snps,reset-active-low")) pin_value = GPIO_PIN_HIGH; - if (flags & GPIO_ACTIVE_LOW) - pin_value = !pin_value; - GPIO_PIN_SETFLAGS(gpio, pin, GPIO_PIN_OUTPUT); GPIO_PIN_SET(gpio, pin, pin_value); - DELAY(delay_prop[0]); + DELAY(delay_prop[0] * 5); GPIO_PIN_SET(gpio, pin, !pin_value); - DELAY(delay_prop[1]); + DELAY(delay_prop[1] * 5); GPIO_PIN_SET(gpio, pin, pin_value); - DELAY(delay_prop[2]); + DELAY(delay_prop[2] * 5); return (0); } #ifdef EXT_RESOURCES static int dwc_clock_init(device_t dev) { hwreset_t rst; clk_t clk; int error; /* Enable clock */ if (clk_get_by_ofw_name(dev, 0, "stmmaceth", &clk) == 0) { error = clk_enable(clk); if (error != 0) { device_printf(dev, "could not enable main clock\n"); return (error); } } /* De-assert reset */ if (hwreset_get_by_ofw_name(dev, 0, "stmmaceth", &rst) == 0) { error = hwreset_deassert(rst); if (error != 0) { device_printf(dev, "could not de-assert reset\n"); return (error); } } return (0); } #endif static int dwc_probe(device_t dev) { if (!ofw_bus_status_okay(dev)) return (ENXIO); if (!ofw_bus_is_compatible(dev, "snps,dwmac")) return (ENXIO); device_set_desc(dev, "Gigabit Ethernet Controller"); return (BUS_PROBE_DEFAULT); } static int dwc_attach(device_t dev) { uint8_t macaddr[ETHER_ADDR_LEN]; struct dwc_softc *sc; struct ifnet *ifp; int error, i; uint32_t reg; sc = device_get_softc(dev); sc->dev = dev; sc->rx_idx = 0; sc->txcount = TX_DESC_COUNT; sc->mii_clk = IF_DWC_MII_CLK(dev); sc->mactype = IF_DWC_MAC_TYPE(dev); if (IF_DWC_INIT(dev) != 0) return (ENXIO); #ifdef EXT_RESOURCES if (dwc_clock_init(dev) != 0) return (ENXIO); #endif if (bus_alloc_resources(dev, dwc_spec, sc->res)) { device_printf(dev, "could not allocate resources\n"); return (ENXIO); } /* Memory interface */ sc->bst = rman_get_bustag(sc->res[0]); sc->bsh = rman_get_bushandle(sc->res[0]); /* Read MAC before reset */ if (dwc_get_hwaddr(sc, macaddr)) { device_printf(sc->dev, "can't get mac\n"); return (ENXIO); } /* Reset the PHY if needed */ if (dwc_reset(dev) != 0) { device_printf(dev, "Can't reset the PHY\n"); return (ENXIO); } /* Reset */ reg = READ4(sc, BUS_MODE); reg |= (BUS_MODE_SWR); WRITE4(sc, BUS_MODE, reg); for (i = 0; i < MAC_RESET_TIMEOUT; i++) { if ((READ4(sc, BUS_MODE) & BUS_MODE_SWR) == 0) break; DELAY(10); } if (i >= MAC_RESET_TIMEOUT) { device_printf(sc->dev, "Can't reset DWC.\n"); return (ENXIO); } if (sc->mactype == DWC_GMAC_ALT_DESC) { reg = BUS_MODE_FIXEDBURST; reg |= (BUS_MODE_PRIORXTX_41 << BUS_MODE_PRIORXTX_SHIFT); } else reg = (BUS_MODE_EIGHTXPBL); reg |= (BUS_MODE_PBL_BEATS_8 << BUS_MODE_PBL_SHIFT); WRITE4(sc, BUS_MODE, reg); /* * DMA must be stop while changing descriptor list addresses. */ reg = READ4(sc, OPERATION_MODE); reg &= ~(MODE_ST | MODE_SR); WRITE4(sc, OPERATION_MODE, reg); if (setup_dma(sc)) return (ENXIO); /* Setup addresses */ WRITE4(sc, RX_DESCR_LIST_ADDR, sc->rxdesc_ring_paddr); WRITE4(sc, TX_DESCR_LIST_ADDR, sc->txdesc_ring_paddr); mtx_init(&sc->mtx, device_get_nameunit(sc->dev), MTX_NETWORK_LOCK, MTX_DEF); callout_init_mtx(&sc->dwc_callout, &sc->mtx, 0); /* Setup interrupt handler. */ error = bus_setup_intr(dev, sc->res[1], INTR_TYPE_NET | INTR_MPSAFE, NULL, dwc_intr, sc, &sc->intr_cookie); if (error != 0) { device_printf(dev, "could not setup interrupt handler.\n"); return (ENXIO); } /* Set up the ethernet interface. */ sc->ifp = ifp = if_alloc(IFT_ETHER); ifp->if_softc = sc; if_initname(ifp, device_get_name(dev), device_get_unit(dev)); ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; ifp->if_capabilities = IFCAP_VLAN_MTU; ifp->if_capenable = ifp->if_capabilities; ifp->if_start = dwc_txstart; ifp->if_ioctl = dwc_ioctl; ifp->if_init = dwc_init; IFQ_SET_MAXLEN(&ifp->if_snd, TX_DESC_COUNT - 1); ifp->if_snd.ifq_drv_maxlen = TX_DESC_COUNT - 1; IFQ_SET_READY(&ifp->if_snd); /* Attach the mii driver. */ error = mii_attach(dev, &sc->miibus, ifp, dwc_media_change, dwc_media_status, BMSR_DEFCAPMASK, MII_PHY_ANY, MII_OFFSET_ANY, 0); if (error != 0) { device_printf(dev, "PHY attach failed\n"); return (ENXIO); } sc->mii_softc = device_get_softc(sc->miibus); /* All ready to run, attach the ethernet interface. */ ether_ifattach(ifp, macaddr); sc->is_attached = true; return (0); } static int dwc_miibus_read_reg(device_t dev, int phy, int reg) { struct dwc_softc *sc; uint16_t mii; size_t cnt; int rv = 0; sc = device_get_softc(dev); mii = ((phy & GMII_ADDRESS_PA_MASK) << GMII_ADDRESS_PA_SHIFT) | ((reg & GMII_ADDRESS_GR_MASK) << GMII_ADDRESS_GR_SHIFT) | (sc->mii_clk << GMII_ADDRESS_CR_SHIFT) | GMII_ADDRESS_GB; /* Busy flag */ WRITE4(sc, GMII_ADDRESS, mii); for (cnt = 0; cnt < 1000; cnt++) { if (!(READ4(sc, GMII_ADDRESS) & GMII_ADDRESS_GB)) { rv = READ4(sc, GMII_DATA); break; } DELAY(10); } return rv; } static int dwc_miibus_write_reg(device_t dev, int phy, int reg, int val) { struct dwc_softc *sc; uint16_t mii; size_t cnt; sc = device_get_softc(dev); mii = ((phy & GMII_ADDRESS_PA_MASK) << GMII_ADDRESS_PA_SHIFT) | ((reg & GMII_ADDRESS_GR_MASK) << GMII_ADDRESS_GR_SHIFT) | (sc->mii_clk << GMII_ADDRESS_CR_SHIFT) | GMII_ADDRESS_GB | GMII_ADDRESS_GW; WRITE4(sc, GMII_DATA, val); WRITE4(sc, GMII_ADDRESS, mii); for (cnt = 0; cnt < 1000; cnt++) { if (!(READ4(sc, GMII_ADDRESS) & GMII_ADDRESS_GB)) { break; } DELAY(10); } return (0); } static void dwc_miibus_statchg(device_t dev) { struct dwc_softc *sc; struct mii_data *mii; uint32_t reg; /* * Called by the MII bus driver when the PHY establishes * link to set the MAC interface registers. */ sc = device_get_softc(dev); DWC_ASSERT_LOCKED(sc); mii = sc->mii_softc; if (mii->mii_media_status & IFM_ACTIVE) sc->link_is_up = true; else sc->link_is_up = false; reg = READ4(sc, MAC_CONFIGURATION); switch (IFM_SUBTYPE(mii->mii_media_active)) { case IFM_1000_T: case IFM_1000_SX: reg &= ~(CONF_FES | CONF_PS); break; case IFM_100_TX: reg |= (CONF_FES | CONF_PS); break; case IFM_10_T: reg &= ~(CONF_FES); reg |= (CONF_PS); break; case IFM_NONE: sc->link_is_up = false; return; default: sc->link_is_up = false; device_printf(dev, "Unsupported media %u\n", IFM_SUBTYPE(mii->mii_media_active)); return; } if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0) reg |= (CONF_DM); else reg &= ~(CONF_DM); WRITE4(sc, MAC_CONFIGURATION, reg); } static device_method_t dwc_methods[] = { DEVMETHOD(device_probe, dwc_probe), DEVMETHOD(device_attach, dwc_attach), /* MII Interface */ DEVMETHOD(miibus_readreg, dwc_miibus_read_reg), DEVMETHOD(miibus_writereg, dwc_miibus_write_reg), DEVMETHOD(miibus_statchg, dwc_miibus_statchg), { 0, 0 } }; driver_t dwc_driver = { "dwc", dwc_methods, sizeof(struct dwc_softc), }; static devclass_t dwc_devclass; DRIVER_MODULE(dwc, simplebus, dwc_driver, dwc_devclass, 0, 0); DRIVER_MODULE(miibus, dwc, miibus_driver, miibus_devclass, 0, 0); MODULE_DEPEND(dwc, ether, 1, 1, 1); MODULE_DEPEND(dwc, miibus, 1, 1, 1); Index: stable/12 =================================================================== --- stable/12 (revision 355175) +++ stable/12 (revision 355176) Property changes on: stable/12 ___________________________________________________________________ Modified: svn:mergeinfo ## -0,0 +0,1 ## Merged /head:r347097,351187,351551-351552,352849-352852