Index: head/sys/dev/ichiic/ig4_iic.c =================================================================== --- head/sys/dev/ichiic/ig4_iic.c (revision 354313) +++ head/sys/dev/ichiic/ig4_iic.c (revision 354314) @@ -1,1085 +1,1139 @@ /* * Copyright (c) 2014 The DragonFly Project. All rights reserved. * * This code is derived from software contributed to The DragonFly Project * by Matthew Dillon and was subsequently ported * to FreeBSD by Michael Gmelin * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in * the documentation and/or other materials provided with the * distribution. * 3. Neither the name of The DragonFly Project nor the names of its * contributors may be used to endorse or promote products derived * from this software without specific, prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE * COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, * INCIDENTAL, SPECIAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES (INCLUDING, * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. */ #include __FBSDID("$FreeBSD$"); /* * Intel fourth generation mobile cpus integrated I2C device. * * See ig4_reg.h for datasheet reference and notes. * See ig4_var.h for locking semantics. */ #include "opt_acpi.h" #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #ifdef DEV_ACPI #include #include #include #endif #include #include #include #include #define DO_POLL(sc) (cold || kdb_active || SCHEDULER_STOPPED() || sc->poll) /* * tLOW, tHIGH periods of the SCL clock and maximal falling time of both * lines are taken from I2C specifications. */ #define IG4_SPEED_STD_THIGH 4000 /* nsec */ #define IG4_SPEED_STD_TLOW 4700 /* nsec */ #define IG4_SPEED_STD_TF_MAX 300 /* nsec */ #define IG4_SPEED_FAST_THIGH 600 /* nsec */ #define IG4_SPEED_FAST_TLOW 1300 /* nsec */ #define IG4_SPEED_FAST_TF_MAX 300 /* nsec */ /* * Ig4 hardware parameters except Haswell are taken from intel_lpss driver */ static const struct ig4_hw ig4iic_hw[] = { [IG4_HASWELL] = { .ic_clock_rate = 100, /* MHz */ .sda_hold_time = 90, /* nsec */ .txfifo_depth = 32, .rxfifo_depth = 32, }, [IG4_ATOM] = { .ic_clock_rate = 100, .sda_fall_time = 280, .scl_fall_time = 240, .sda_hold_time = 60, .txfifo_depth = 32, .rxfifo_depth = 32, }, [IG4_SKYLAKE] = { .ic_clock_rate = 120, .sda_hold_time = 230, }, [IG4_APL] = { .ic_clock_rate = 133, .sda_fall_time = 171, .scl_fall_time = 208, .sda_hold_time = 207, }, }; static void ig4iic_intr(void *cookie); static void ig4iic_dump(ig4iic_softc_t *sc); static int ig4_dump; SYSCTL_INT(_debug, OID_AUTO, ig4_dump, CTLFLAG_RW, &ig4_dump, 0, "Dump controller registers"); /* * Clock registers initialization control * 0 - Try read clock registers from ACPI and fallback to p.1. * 1 - Calculate values based on controller type (IC clock rate). * 2 - Use values inherited from DragonflyBSD driver (old behavior). * 3 - Keep clock registers intact. */ static int ig4_timings; SYSCTL_INT(_debug, OID_AUTO, ig4_timings, CTLFLAG_RDTUN, &ig4_timings, 0, "Controller timings 0=ACPI, 1=predefined, 2=legacy, 3=do not change"); /* * Low-level inline support functions */ static __inline void reg_write(ig4iic_softc_t *sc, uint32_t reg, uint32_t value) { bus_write_4(sc->regs_res, reg, value); bus_barrier(sc->regs_res, reg, 4, BUS_SPACE_BARRIER_WRITE); } static __inline uint32_t reg_read(ig4iic_softc_t *sc, uint32_t reg) { uint32_t value; bus_barrier(sc->regs_res, reg, 4, BUS_SPACE_BARRIER_READ); value = bus_read_4(sc->regs_res, reg); return (value); } static void set_intr_mask(ig4iic_softc_t *sc, uint32_t val) { if (sc->intr_mask != val) { reg_write(sc, IG4_REG_INTR_MASK, val); sc->intr_mask = val; } } +static int +intrstat2iic(ig4iic_softc_t *sc, uint32_t val) +{ + uint32_t src; + + if (val & IG4_INTR_RX_UNDER) + reg_read(sc, IG4_REG_CLR_RX_UNDER); + if (val & IG4_INTR_RX_OVER) + reg_read(sc, IG4_REG_CLR_RX_OVER); + if (val & IG4_INTR_TX_OVER) + reg_read(sc, IG4_REG_CLR_TX_OVER); + + if (val & IG4_INTR_TX_ABRT) { + src = reg_read(sc, IG4_REG_TX_ABRT_SOURCE); + reg_read(sc, IG4_REG_CLR_TX_ABORT); + /* User-requested abort. Not really a error */ + if (src & IG4_ABRTSRC_TRANSFER) + return (IIC_ESTATUS); + /* Master has lost arbitration */ + if (src & IG4_ABRTSRC_ARBLOST) + return (IIC_EBUSBSY); + /* Did not receive an acknowledge from the remote slave */ + if (src & (IG4_ABRTSRC_TXNOACK_ADDR7 | + IG4_ABRTSRC_TXNOACK_ADDR10_1 | + IG4_ABRTSRC_TXNOACK_ADDR10_2 | + IG4_ABRTSRC_TXNOACK_DATA | + IG4_ABRTSRC_GENCALL_NOACK)) + return (IIC_ENOACK); + /* Programming errors */ + if (src & (IG4_ABRTSRC_GENCALL_READ | + IG4_ABRTSRC_NORESTART_START | + IG4_ABRTSRC_NORESTART_10)) + return (IIC_ENOTSUPP); + /* Other errors */ + if (src & IG4_ABRTSRC_ACKED_START) + return (IIC_EBUSERR); + } + /* + * TX_OVER, RX_OVER and RX_UNDER are caused by wrong RX/TX FIFO depth + * detection or driver's read/write pipelining errors. + */ + if (val & (IG4_INTR_TX_OVER | IG4_INTR_RX_OVER)) + return (IIC_EOVERFLOW); + if (val & IG4_INTR_RX_UNDER) + return (IIC_EUNDERFLOW); + + return (IIC_NOERR); +} + /* * Enable or disable the controller and wait for the controller to acknowledge * the state change. */ static int set_controller(ig4iic_softc_t *sc, uint32_t ctl) { int retry; int error; uint32_t v; /* * When the controller is enabled, interrupt on STOP detect * or receive character ready and clear pending interrupts. */ set_intr_mask(sc, 0); if (ctl & IG4_I2C_ENABLE) reg_read(sc, IG4_REG_CLR_INTR); reg_write(sc, IG4_REG_I2C_EN, ctl); error = IIC_ETIMEOUT; for (retry = 100; retry > 0; --retry) { v = reg_read(sc, IG4_REG_ENABLE_STATUS); if (((v ^ ctl) & IG4_I2C_ENABLE) == 0) { error = 0; break; } pause("i2cslv", 1); } return (error); } /* * Wait up to 25ms for the requested interrupt using a 25uS polling loop. */ static int wait_intr(ig4iic_softc_t *sc, uint32_t intr) { uint32_t v; int error; int txlvl = -1; u_int count_us = 0; u_int limit_us = 25000; /* 25ms */ - error = IIC_ETIMEOUT; - for (;;) { /* * Check requested status */ v = reg_read(sc, IG4_REG_RAW_INTR_STAT); - if (v & intr) { - error = 0; + error = intrstat2iic(sc, v & IG4_INTR_ERR_MASK); + if (error || (v & intr)) break; - } /* * When waiting for the transmit FIFO to become empty, * reset the timeout if we see a change in the transmit * FIFO level as progress is being made. */ if (intr & IG4_INTR_TX_EMPTY) { v = reg_read(sc, IG4_REG_TXFLR) & IG4_FIFOLVL_MASK; if (txlvl != v) { txlvl = v; count_us = 0; } } /* * Stop if we've run out of time. */ - if (count_us >= limit_us) + if (count_us >= limit_us) { + error = IIC_ETIMEOUT; break; + } /* * When polling is not requested let the interrupt do its work. */ if (!DO_POLL(sc)) { mtx_lock(&sc->io_lock); - set_intr_mask(sc, intr); + set_intr_mask(sc, intr | IG4_INTR_ERR_MASK); mtx_sleep(sc, &sc->io_lock, 0, "i2cwait", (hz + 99) / 100); /* sleep up to 10ms */ set_intr_mask(sc, 0); mtx_unlock(&sc->io_lock); count_us += 10000; } else { DELAY(25); count_us += 25; } } return (error); } /* * Set the slave address. The controller must be disabled when * changing the address. * * This operation does not issue anything to the I2C bus but sets * the target address for when the controller later issues a START. */ static void set_slave_addr(ig4iic_softc_t *sc, uint8_t slave) { uint32_t tar; uint32_t ctl; int use_10bit; use_10bit = 0; if (sc->slave_valid && sc->last_slave == slave && sc->use_10bit == use_10bit) { return; } sc->use_10bit = use_10bit; /* * Wait for TXFIFO to drain before disabling the controller. */ wait_intr(sc, IG4_INTR_TX_EMPTY); set_controller(sc, 0); ctl = reg_read(sc, IG4_REG_CTL); ctl &= ~IG4_CTL_10BIT; ctl |= IG4_CTL_RESTARTEN; tar = slave; if (sc->use_10bit) { tar |= IG4_TAR_10BIT; ctl |= IG4_CTL_10BIT; } reg_write(sc, IG4_REG_CTL, ctl); reg_write(sc, IG4_REG_TAR_ADD, tar); set_controller(sc, IG4_I2C_ENABLE); sc->slave_valid = 1; sc->last_slave = slave; } /* * IICBUS API FUNCTIONS */ static int -ig4iic_xfer_start(ig4iic_softc_t *sc, uint16_t slave) +ig4iic_xfer_start(ig4iic_softc_t *sc, uint16_t slave, bool repeated_start) { set_slave_addr(sc, slave >> 1); + + if (!repeated_start) { + /* + * Clear any previous TX/RX FIFOs overflow/underflow bits. + */ + reg_read(sc, IG4_REG_CLR_INTR); + } + return (0); } /* * Amount of unread data before next burst to get better I2C bus utilization. * 2 bytes is enough in FAST mode. 8 bytes is better in FAST+ and HIGH modes. * Intel-recommended value is 16 for DMA transfers with 64-byte depth FIFOs. */ #define IG4_FIFO_LOWAT 2 static int ig4iic_read(ig4iic_softc_t *sc, uint8_t *buf, uint16_t len, bool repeated_start, bool stop) { uint32_t cmd; int requested = 0; int received = 0; int burst, target, lowat = 0; int error; if (len == 0) return (0); while (received < len) { burst = sc->cfg.txfifo_depth - (reg_read(sc, IG4_REG_TXFLR) & IG4_FIFOLVL_MASK); if (burst <= 0) { error = wait_intr(sc, IG4_INTR_TX_EMPTY); if (error) break; burst = sc->cfg.txfifo_depth; } /* Ensure we have enough free space in RXFIFO */ burst = MIN(burst, sc->cfg.rxfifo_depth - lowat); target = MIN(requested + burst, (int)len); while (requested < target) { cmd = IG4_DATA_COMMAND_RD; if (repeated_start && requested == 0) cmd |= IG4_DATA_RESTART; if (stop && requested == len - 1) cmd |= IG4_DATA_STOP; reg_write(sc, IG4_REG_DATA_CMD, cmd); requested++; } /* Leave some data queued to maintain the hardware pipeline */ lowat = 0; if (requested != len && requested - received > IG4_FIFO_LOWAT) lowat = IG4_FIFO_LOWAT; /* After TXFLR fills up, clear it by reading available data */ while (received < requested - lowat) { burst = MIN((int)len - received, reg_read(sc, IG4_REG_RXFLR) & IG4_FIFOLVL_MASK); if (burst > 0) { while (burst--) buf[received++] = 0xFF & reg_read(sc, IG4_REG_DATA_CMD); } else { error = wait_intr(sc, IG4_INTR_RX_FULL); if (error) goto out; } } } out: - (void)reg_read(sc, IG4_REG_TX_ABRT_SOURCE); return (error); } static int ig4iic_write(ig4iic_softc_t *sc, uint8_t *buf, uint16_t len, bool repeated_start, bool stop) { uint32_t cmd; int sent = 0; int burst, target; int error; if (len == 0) return (0); while (sent < len) { burst = sc->cfg.txfifo_depth - (reg_read(sc, IG4_REG_TXFLR) & IG4_FIFOLVL_MASK); target = MIN(sent + burst, (int)len); while(sent < target) { cmd = buf[sent]; if (repeated_start && sent == 0) cmd |= IG4_DATA_RESTART; if (stop && sent == len - 1) cmd |= IG4_DATA_STOP; reg_write(sc, IG4_REG_DATA_CMD, cmd); sent++; } if (sent < len) { error = wait_intr(sc, IG4_INTR_TX_EMPTY); if (error) break; } } - (void)reg_read(sc, IG4_REG_TX_ABRT_SOURCE); return (error); } int ig4iic_transfer(device_t dev, struct iic_msg *msgs, uint32_t nmsgs) { ig4iic_softc_t *sc = device_get_softc(dev); const char *reason = NULL; uint32_t i; int error; int unit; bool rpstart; bool stop; bool allocated; /* * The hardware interface imposes limits on allowed I2C messages. * It is not possible to explicitly send a start or stop. * They are automatically sent (or not sent, depending on the * configuration) when a data byte is transferred. * For this reason it's impossible to send a message with no data * at all (like an SMBus quick message). * The start condition is automatically generated after the stop * condition, so it's impossible to not have a start after a stop. * The repeated start condition is automatically sent if a change * of the transfer direction happens, so it's impossible to have * a change of direction without a (repeated) start. * The repeated start can be forced even without the change of * direction. * Changing the target slave address requires resetting the hardware * state, so it's impossible to do that without the stop followed * by the start. */ for (i = 0; i < nmsgs; i++) { #if 0 if (i == 0 && (msgs[i].flags & IIC_M_NOSTART) != 0) { reason = "first message without start"; break; } if (i == nmsgs - 1 && (msgs[i].flags & IIC_M_NOSTOP) != 0) { reason = "last message without stop"; break; } #endif if (msgs[i].len == 0) { reason = "message with no data"; break; } if (i > 0) { if ((msgs[i].flags & IIC_M_NOSTART) != 0 && (msgs[i - 1].flags & IIC_M_NOSTOP) == 0) { reason = "stop not followed by start"; break; } if ((msgs[i - 1].flags & IIC_M_NOSTOP) != 0 && msgs[i].slave != msgs[i - 1].slave) { reason = "change of slave without stop"; break; } if ((msgs[i].flags & IIC_M_NOSTART) != 0 && (msgs[i].flags & IIC_M_RD) != (msgs[i - 1].flags & IIC_M_RD)) { reason = "change of direction without repeated" " start"; break; } } } if (reason != NULL) { if (bootverbose) device_printf(dev, "%s\n", reason); return (IIC_ENOTSUPP); } /* Check if device is already allocated with iicbus_request_bus() */ allocated = sx_xlocked(&sc->call_lock) != 0; if (!allocated) sx_xlock(&sc->call_lock); /* Debugging - dump registers. */ if (ig4_dump) { unit = device_get_unit(dev); if (ig4_dump & (1 << unit)) { ig4_dump &= ~(1 << unit); ig4iic_dump(sc); } } /* * Clear any previous abort condition that may have been holding * the txfifo in reset. */ reg_read(sc, IG4_REG_CLR_TX_ABORT); rpstart = false; error = 0; for (i = 0; i < nmsgs; i++) { if ((msgs[i].flags & IIC_M_NOSTART) == 0) { - error = ig4iic_xfer_start(sc, msgs[i].slave); + error = ig4iic_xfer_start(sc, msgs[i].slave, rpstart); } else { if (!sc->slave_valid || (msgs[i].slave >> 1) != sc->last_slave) { device_printf(dev, "start condition suppressed" "but slave address is not set up"); error = EINVAL; break; } rpstart = false; } if (error != 0) break; stop = (msgs[i].flags & IIC_M_NOSTOP) == 0; if (msgs[i].flags & IIC_M_RD) error = ig4iic_read(sc, msgs[i].buf, msgs[i].len, rpstart, stop); else error = ig4iic_write(sc, msgs[i].buf, msgs[i].len, rpstart, stop); if (error != 0) break; rpstart = !stop; } if (!allocated) sx_unlock(&sc->call_lock); return (error); } int ig4iic_reset(device_t dev, u_char speed, u_char addr, u_char *oldaddr) { ig4iic_softc_t *sc = device_get_softc(dev); bool allocated; allocated = sx_xlocked(&sc->call_lock) != 0; if (!allocated) sx_xlock(&sc->call_lock); /* TODO handle speed configuration? */ if (oldaddr != NULL) *oldaddr = sc->last_slave << 1; set_slave_addr(sc, addr >> 1); if (addr == IIC_UNKNOWN) sc->slave_valid = false; if (!allocated) sx_unlock(&sc->call_lock); return (0); } int ig4iic_callback(device_t dev, int index, caddr_t data) { ig4iic_softc_t *sc = device_get_softc(dev); int error = 0; int how; switch (index) { case IIC_REQUEST_BUS: /* force polling if ig4iic is requested with IIC_DONTWAIT */ how = *(int *)data; if ((how & IIC_WAIT) == 0) { if (sx_try_xlock(&sc->call_lock) == 0) error = IIC_EBUSBSY; else sc->poll = true; } else sx_xlock(&sc->call_lock); break; case IIC_RELEASE_BUS: sc->poll = false; sx_unlock(&sc->call_lock); break; default: error = errno2iic(EINVAL); } return (error); } /* * Clock register values can be calculated with following rough equations: * SCL_HCNT = ceil(IC clock rate * tHIGH) * SCL_LCNT = ceil(IC clock rate * tLOW) * SDA_HOLD = ceil(IC clock rate * SDA hold time) * Precise equations take signal's falling, rising and spike suppression * times in to account. They can be found in Synopsys or Intel documentation. * * Here we snarf formulas and defaults from Linux driver to be able to use * timing values provided by Intel LPSS driver "as is". */ static int ig4iic_clk_params(const struct ig4_hw *hw, int speed, uint16_t *scl_hcnt, uint16_t *scl_lcnt, uint16_t *sda_hold) { uint32_t thigh, tlow, tf_max; /* nsec */ uint32_t sda_fall_time; /* nsec */ uint32_t scl_fall_time; /* nsec */ switch (speed) { case IG4_CTL_SPEED_STD: thigh = IG4_SPEED_STD_THIGH; tlow = IG4_SPEED_STD_TLOW; tf_max = IG4_SPEED_STD_TF_MAX; break; case IG4_CTL_SPEED_FAST: thigh = IG4_SPEED_FAST_THIGH; tlow = IG4_SPEED_FAST_TLOW; tf_max = IG4_SPEED_FAST_TF_MAX; break; default: return (EINVAL); } /* Use slowest falling time defaults to be on the safe side */ sda_fall_time = hw->sda_fall_time == 0 ? tf_max : hw->sda_fall_time; *scl_hcnt = (uint16_t) ((hw->ic_clock_rate * (thigh + sda_fall_time) + 500) / 1000 - 3); scl_fall_time = hw->scl_fall_time == 0 ? tf_max : hw->scl_fall_time; *scl_lcnt = (uint16_t) ((hw->ic_clock_rate * (tlow + scl_fall_time) + 500) / 1000 - 1); /* * There is no "known good" default value for tHD;DAT so keep SDA_HOLD * intact if sda_hold_time value is not provided. */ if (hw->sda_hold_time != 0) *sda_hold = (uint16_t) ((hw->ic_clock_rate * hw->sda_hold_time + 500) / 1000); return (0); } #ifdef DEV_ACPI static ACPI_STATUS ig4iic_acpi_params(ACPI_HANDLE handle, char *method, uint16_t *scl_hcnt, uint16_t *scl_lcnt, uint16_t *sda_hold) { ACPI_BUFFER buf; ACPI_OBJECT *obj, *elems; ACPI_STATUS status; buf.Pointer = NULL; buf.Length = ACPI_ALLOCATE_BUFFER; status = AcpiEvaluateObject(handle, method, NULL, &buf); if (ACPI_FAILURE(status)) return (status); status = AE_TYPE; obj = (ACPI_OBJECT *)buf.Pointer; if (obj->Type == ACPI_TYPE_PACKAGE && obj->Package.Count == 3) { elems = obj->Package.Elements; *scl_hcnt = elems[0].Integer.Value & IG4_SCL_CLOCK_MASK; *scl_lcnt = elems[1].Integer.Value & IG4_SCL_CLOCK_MASK; *sda_hold = elems[2].Integer.Value & IG4_SDA_TX_HOLD_MASK; status = AE_OK; } AcpiOsFree(obj); return (status); } #endif /* DEV_ACPI */ static void ig4iic_get_config(ig4iic_softc_t *sc) { const struct ig4_hw *hw; uint32_t v; #ifdef DEV_ACPI ACPI_HANDLE handle; #endif /* Fetch default hardware config from controller */ sc->cfg.version = reg_read(sc, IG4_REG_COMP_VER); sc->cfg.bus_speed = reg_read(sc, IG4_REG_CTL) & IG4_CTL_SPEED_MASK; sc->cfg.ss_scl_hcnt = reg_read(sc, IG4_REG_SS_SCL_HCNT) & IG4_SCL_CLOCK_MASK; sc->cfg.ss_scl_lcnt = reg_read(sc, IG4_REG_SS_SCL_LCNT) & IG4_SCL_CLOCK_MASK; sc->cfg.fs_scl_hcnt = reg_read(sc, IG4_REG_FS_SCL_HCNT) & IG4_SCL_CLOCK_MASK; sc->cfg.fs_scl_lcnt = reg_read(sc, IG4_REG_FS_SCL_LCNT) & IG4_SCL_CLOCK_MASK; sc->cfg.ss_sda_hold = sc->cfg.fs_sda_hold = reg_read(sc, IG4_REG_SDA_HOLD) & IG4_SDA_TX_HOLD_MASK; if (sc->cfg.bus_speed != IG4_CTL_SPEED_STD) sc->cfg.bus_speed = IG4_CTL_SPEED_FAST; /* REG_COMP_PARAM1 is not documented in latest Intel specs */ if (sc->version == IG4_HASWELL || sc->version == IG4_ATOM) { v = reg_read(sc, IG4_REG_COMP_PARAM1); if (IG4_PARAM1_TXFIFO_DEPTH(v) != 0) sc->cfg.txfifo_depth = IG4_PARAM1_TXFIFO_DEPTH(v); if (IG4_PARAM1_RXFIFO_DEPTH(v) != 0) sc->cfg.rxfifo_depth = IG4_PARAM1_RXFIFO_DEPTH(v); } else { /* * Hardware does not allow FIFO Threshold Levels value to be * set larger than the depth of the buffer. If an attempt is * made to do that, the actual value set will be the maximum * depth of the buffer. */ v = reg_read(sc, IG4_REG_TX_TL); reg_write(sc, IG4_REG_TX_TL, v | IG4_FIFO_MASK); sc->cfg.txfifo_depth = (reg_read(sc, IG4_REG_TX_TL) & IG4_FIFO_MASK) + 1; reg_write(sc, IG4_REG_TX_TL, v); v = reg_read(sc, IG4_REG_RX_TL); reg_write(sc, IG4_REG_RX_TL, v | IG4_FIFO_MASK); sc->cfg.rxfifo_depth = (reg_read(sc, IG4_REG_RX_TL) & IG4_FIFO_MASK) + 1; reg_write(sc, IG4_REG_RX_TL, v); } /* Override hardware config with IC_clock-based counter values */ if (ig4_timings < 2 && sc->version < nitems(ig4iic_hw)) { hw = &ig4iic_hw[sc->version]; sc->cfg.bus_speed = IG4_CTL_SPEED_FAST; ig4iic_clk_params(hw, IG4_CTL_SPEED_STD, &sc->cfg.ss_scl_hcnt, &sc->cfg.ss_scl_lcnt, &sc->cfg.ss_sda_hold); ig4iic_clk_params(hw, IG4_CTL_SPEED_FAST, &sc->cfg.fs_scl_hcnt, &sc->cfg.fs_scl_lcnt, &sc->cfg.fs_sda_hold); if (hw->txfifo_depth != 0) sc->cfg.txfifo_depth = hw->txfifo_depth; if (hw->rxfifo_depth != 0) sc->cfg.rxfifo_depth = hw->rxfifo_depth; } else if (ig4_timings == 2) { /* * Timings of original ig4 driver: * Program based on a 25000 Hz clock. This is a bit of a * hack (obviously). The defaults are 400 and 470 for standard * and 60 and 130 for fast. The defaults for standard fail * utterly (presumably cause an abort) because the clock time * is ~18.8ms by default. This brings it down to ~4ms. */ sc->cfg.bus_speed = IG4_CTL_SPEED_STD; sc->cfg.ss_scl_hcnt = sc->cfg.fs_scl_hcnt = 100; sc->cfg.ss_scl_lcnt = sc->cfg.fs_scl_lcnt = 125; if (sc->version == IG4_SKYLAKE) sc->cfg.ss_sda_hold = sc->cfg.fs_sda_hold = 28; } #ifdef DEV_ACPI /* Evaluate SSCN and FMCN ACPI methods to fetch timings */ if (ig4_timings == 0 && (handle = acpi_get_handle(sc->dev)) != NULL) { ig4iic_acpi_params(handle, "SSCN", &sc->cfg.ss_scl_hcnt, &sc->cfg.ss_scl_lcnt, &sc->cfg.ss_sda_hold); ig4iic_acpi_params(handle, "FMCN", &sc->cfg.fs_scl_hcnt, &sc->cfg.fs_scl_lcnt, &sc->cfg.fs_sda_hold); } #endif if (bootverbose) { device_printf(sc->dev, "Controller parameters:\n"); printf(" Speed: %s\n", sc->cfg.bus_speed == IG4_CTL_SPEED_STD ? "Std" : "Fast"); printf(" Regs: HCNT :LCNT :SDAHLD\n"); printf(" Std: 0x%04hx:0x%04hx:0x%04hx\n", sc->cfg.ss_scl_hcnt, sc->cfg.ss_scl_lcnt, sc->cfg.ss_sda_hold); printf(" Fast: 0x%04hx:0x%04hx:0x%04hx\n", sc->cfg.fs_scl_hcnt, sc->cfg.fs_scl_lcnt, sc->cfg.fs_sda_hold); printf(" FIFO: RX:0x%04x: TX:0x%04x\n", sc->cfg.rxfifo_depth, sc->cfg.txfifo_depth); } } static int ig4iic_set_config(ig4iic_softc_t *sc) { uint32_t v; v = reg_read(sc, IG4_REG_DEVIDLE_CTRL); if (sc->version == IG4_SKYLAKE && (v & IG4_RESTORE_REQUIRED) ) { reg_write(sc, IG4_REG_DEVIDLE_CTRL, IG4_DEVICE_IDLE | IG4_RESTORE_REQUIRED); reg_write(sc, IG4_REG_DEVIDLE_CTRL, 0); reg_write(sc, IG4_REG_RESETS_SKL, IG4_RESETS_ASSERT_SKL); reg_write(sc, IG4_REG_RESETS_SKL, IG4_RESETS_DEASSERT_SKL); DELAY(1000); } if (sc->version == IG4_ATOM) v = reg_read(sc, IG4_REG_COMP_TYPE); if (sc->version == IG4_HASWELL || sc->version == IG4_ATOM) { v = reg_read(sc, IG4_REG_COMP_PARAM1); v = reg_read(sc, IG4_REG_GENERAL); /* * The content of IG4_REG_GENERAL is different for each * controller version. */ if (sc->version == IG4_HASWELL && (v & IG4_GENERAL_SWMODE) == 0) { v |= IG4_GENERAL_SWMODE; reg_write(sc, IG4_REG_GENERAL, v); v = reg_read(sc, IG4_REG_GENERAL); } } if (sc->version == IG4_HASWELL) { v = reg_read(sc, IG4_REG_SW_LTR_VALUE); v = reg_read(sc, IG4_REG_AUTO_LTR_VALUE); } else if (sc->version == IG4_SKYLAKE) { v = reg_read(sc, IG4_REG_ACTIVE_LTR_VALUE); v = reg_read(sc, IG4_REG_IDLE_LTR_VALUE); } if (sc->version == IG4_HASWELL || sc->version == IG4_ATOM) { v = reg_read(sc, IG4_REG_COMP_VER); if (v < IG4_COMP_MIN_VER) return(ENXIO); } if (set_controller(sc, 0)) { device_printf(sc->dev, "controller error during attach-1\n"); return (ENXIO); } reg_read(sc, IG4_REG_CLR_INTR); reg_write(sc, IG4_REG_INTR_MASK, 0); sc->intr_mask = 0; reg_write(sc, IG4_REG_SS_SCL_HCNT, sc->cfg.ss_scl_hcnt); reg_write(sc, IG4_REG_SS_SCL_LCNT, sc->cfg.ss_scl_lcnt); reg_write(sc, IG4_REG_FS_SCL_HCNT, sc->cfg.fs_scl_hcnt); reg_write(sc, IG4_REG_FS_SCL_LCNT, sc->cfg.fs_scl_lcnt); reg_write(sc, IG4_REG_SDA_HOLD, (sc->cfg.bus_speed & IG4_CTL_SPEED_MASK) == IG4_CTL_SPEED_STD ? sc->cfg.ss_sda_hold : sc->cfg.fs_sda_hold); /* * Use a threshold of 1 so we get interrupted on each character, * allowing us to use mtx_sleep() in our poll code. Not perfect * but this is better than using DELAY() for receiving data. * * See ig4_var.h for details on interrupt handler synchronization. */ reg_write(sc, IG4_REG_RX_TL, 0); reg_write(sc, IG4_REG_TX_TL, 0); reg_write(sc, IG4_REG_CTL, IG4_CTL_MASTER | IG4_CTL_SLAVE_DISABLE | IG4_CTL_RESTARTEN | (sc->cfg.bus_speed & IG4_CTL_SPEED_MASK)); return (0); } /* * Called from ig4iic_pci_attach/detach() */ int ig4iic_attach(ig4iic_softc_t *sc) { int error; mtx_init(&sc->io_lock, "IG4 I/O lock", NULL, MTX_DEF); sx_init(&sc->call_lock, "IG4 call lock"); ig4iic_get_config(sc); error = ig4iic_set_config(sc); if (error) goto done; sc->iicbus = device_add_child(sc->dev, "iicbus", -1); if (sc->iicbus == NULL) { device_printf(sc->dev, "iicbus driver not found\n"); error = ENXIO; goto done; } #if 0 /* * Don't do this, it blows up the PCI config */ if (sc->version == IG4_HASWELL || sc->version == IG4_ATOM) { reg_write(sc, IG4_REG_RESETS_HSW, IG4_RESETS_ASSERT_HSW); reg_write(sc, IG4_REG_RESETS_HSW, IG4_RESETS_DEASSERT_HSW); } else if (sc->version = IG4_SKYLAKE) { reg_write(sc, IG4_REG_RESETS_SKL, IG4_RESETS_ASSERT_SKL); reg_write(sc, IG4_REG_RESETS_SKL, IG4_RESETS_DEASSERT_SKL); } #endif if (set_controller(sc, IG4_I2C_ENABLE)) { device_printf(sc->dev, "controller error during attach-2\n"); error = ENXIO; goto done; } if (set_controller(sc, 0)) { device_printf(sc->dev, "controller error during attach-3\n"); error = ENXIO; goto done; } error = bus_setup_intr(sc->dev, sc->intr_res, INTR_TYPE_MISC | INTR_MPSAFE, NULL, ig4iic_intr, sc, &sc->intr_handle); if (error) { device_printf(sc->dev, "Unable to setup irq: error %d\n", error); } error = bus_generic_attach(sc->dev); if (error) { device_printf(sc->dev, "failed to attach child: error %d\n", error); } done: return (error); } int ig4iic_detach(ig4iic_softc_t *sc) { int error; if (device_is_attached(sc->dev)) { error = bus_generic_detach(sc->dev); if (error) return (error); } if (sc->iicbus) device_delete_child(sc->dev, sc->iicbus); if (sc->intr_handle) bus_teardown_intr(sc->dev, sc->intr_res, sc->intr_handle); sx_xlock(&sc->call_lock); sc->iicbus = NULL; sc->intr_handle = NULL; reg_write(sc, IG4_REG_INTR_MASK, 0); set_controller(sc, 0); sx_xunlock(&sc->call_lock); mtx_destroy(&sc->io_lock); sx_destroy(&sc->call_lock); return (0); } int ig4iic_suspend(ig4iic_softc_t *sc) { int error; /* suspend all children */ error = bus_generic_suspend(sc->dev); sx_xlock(&sc->call_lock); set_controller(sc, 0); if (sc->version == IG4_SKYLAKE) { /* * Place the device in the idle state, just to be safe */ reg_write(sc, IG4_REG_DEVIDLE_CTRL, IG4_DEVICE_IDLE); /* * Controller can become dysfunctional if I2C lines are pulled * down when suspend procedure turns off power to I2C device. * Place device in the reset state to avoid this. */ reg_write(sc, IG4_REG_RESETS_SKL, IG4_RESETS_ASSERT_SKL); } sx_xunlock(&sc->call_lock); return (error); } int ig4iic_resume(ig4iic_softc_t *sc) { int error; sx_xlock(&sc->call_lock); if (ig4iic_set_config(sc)) device_printf(sc->dev, "controller error during resume\n"); /* Force setting of the target address on the next transfer */ sc->slave_valid = 0; sx_xunlock(&sc->call_lock); error = bus_generic_resume(sc->dev); return (error); } /* * Interrupt Operation, see ig4_var.h for locking semantics. */ static void ig4iic_intr(void *cookie) { ig4iic_softc_t *sc = cookie; mtx_lock(&sc->io_lock); /* Ignore stray interrupts */ if (sc->intr_mask != 0 && reg_read(sc, IG4_REG_INTR_STAT) != 0) { + /* Interrupt bits are cleared in wait_intr() loop */ set_intr_mask(sc, 0); - reg_read(sc, IG4_REG_CLR_INTR); wakeup(sc); } mtx_unlock(&sc->io_lock); } #define REGDUMP(sc, reg) \ device_printf(sc->dev, " %-23s %08x\n", #reg, reg_read(sc, reg)) static void ig4iic_dump(ig4iic_softc_t *sc) { device_printf(sc->dev, "ig4iic register dump:\n"); REGDUMP(sc, IG4_REG_CTL); REGDUMP(sc, IG4_REG_TAR_ADD); REGDUMP(sc, IG4_REG_SS_SCL_HCNT); REGDUMP(sc, IG4_REG_SS_SCL_LCNT); REGDUMP(sc, IG4_REG_FS_SCL_HCNT); REGDUMP(sc, IG4_REG_FS_SCL_LCNT); REGDUMP(sc, IG4_REG_INTR_STAT); REGDUMP(sc, IG4_REG_INTR_MASK); REGDUMP(sc, IG4_REG_RAW_INTR_STAT); REGDUMP(sc, IG4_REG_RX_TL); REGDUMP(sc, IG4_REG_TX_TL); REGDUMP(sc, IG4_REG_I2C_EN); REGDUMP(sc, IG4_REG_I2C_STA); REGDUMP(sc, IG4_REG_TXFLR); REGDUMP(sc, IG4_REG_RXFLR); REGDUMP(sc, IG4_REG_SDA_HOLD); REGDUMP(sc, IG4_REG_TX_ABRT_SOURCE); REGDUMP(sc, IG4_REG_SLV_DATA_NACK); REGDUMP(sc, IG4_REG_DMA_CTRL); REGDUMP(sc, IG4_REG_DMA_TDLR); REGDUMP(sc, IG4_REG_DMA_RDLR); REGDUMP(sc, IG4_REG_SDA_SETUP); REGDUMP(sc, IG4_REG_ENABLE_STATUS); REGDUMP(sc, IG4_REG_COMP_PARAM1); REGDUMP(sc, IG4_REG_COMP_VER); if (sc->version == IG4_ATOM) { REGDUMP(sc, IG4_REG_COMP_TYPE); REGDUMP(sc, IG4_REG_CLK_PARMS); } if (sc->version == IG4_HASWELL || sc->version == IG4_ATOM) { REGDUMP(sc, IG4_REG_RESETS_HSW); REGDUMP(sc, IG4_REG_GENERAL); } else if (sc->version == IG4_SKYLAKE) { REGDUMP(sc, IG4_REG_RESETS_SKL); } if (sc->version == IG4_HASWELL) { REGDUMP(sc, IG4_REG_SW_LTR_VALUE); REGDUMP(sc, IG4_REG_AUTO_LTR_VALUE); } else if (sc->version == IG4_SKYLAKE) { REGDUMP(sc, IG4_REG_ACTIVE_LTR_VALUE); REGDUMP(sc, IG4_REG_IDLE_LTR_VALUE); } } #undef REGDUMP devclass_t ig4iic_devclass; DRIVER_MODULE(iicbus, ig4iic, iicbus_driver, iicbus_devclass, NULL, NULL); MODULE_DEPEND(ig4iic, iicbus, IICBUS_MINVER, IICBUS_PREFVER, IICBUS_MAXVER); MODULE_VERSION(ig4iic, 1); Index: head/sys/dev/ichiic/ig4_reg.h =================================================================== --- head/sys/dev/ichiic/ig4_reg.h (revision 354313) +++ head/sys/dev/ichiic/ig4_reg.h (revision 354314) @@ -1,654 +1,657 @@ /* * Copyright (c) 2014 The DragonFly Project. All rights reserved. * * This code is derived from software contributed to The DragonFly Project * by Matthew Dillon and was subsequently ported * to FreeBSD by Michael Gmelin * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in * the documentation and/or other materials provided with the * distribution. * 3. Neither the name of The DragonFly Project nor the names of its * contributors may be used to endorse or promote products derived * from this software without specific, prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE * COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, * INCIDENTAL, SPECIAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES (INCLUDING, * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. * * $FreeBSD$ */ /* * Intel fourth generation mobile cpus integrated I2C device. * * Datasheet reference: Section 22. * * http://www.intel.com/content/www/us/en/processors/core/4th-gen-core-family-mobile-i-o-datasheet.html?wapkw=datasheets+4th+generation * * This is a from-scratch driver under the BSD license using the Intel data * sheet and the linux driver for reference. All code is freshly written * without referencing the linux driver code. However, during testing * I am also using the linux driver code as a reference to help resolve any * issues that come. These will be specifically documented in the code. * * This controller is an I2C master only and cannot act as a slave. The IO * voltage should be set by the BIOS. Standard (100Kb/s) and Fast (400Kb/s) * and fast mode plus (1MB/s) is supported. High speed mode (3.4 MB/s) is NOT * supported. */ #ifndef _ICHIIC_IG4_REG_H_ #define _ICHIIC_IG4_REG_H_ /* * 22.2 MMIO registers can be accessed through BAR0 in PCI mode or through * BAR1 when in ACPI mode. * * Register width is 32-bits * * 22.2 Default Values on device reset are 0 except as specified here: * TAR_ADD 0x00000055 * SS_SCL_HCNT 0x00000264 * SS_SCL_LCNT 0x000002C2 * FS_SCL_HCNT 0x0000006E * FS_SCL_LCNT 0x000000CF * INTR_MASK 0x000008FF * I2C_STA 0x00000006 * SDA_HOLD 0x00000001 * SDA_SETUP 0x00000064 * COMP_PARAM1 0x00FFFF6E */ #define IG4_REG_CTL 0x0000 /* RW Control Register */ #define IG4_REG_TAR_ADD 0x0004 /* RW Target Address */ #define IG4_REG_HS_MADDR 0x000C /* RW High Speed Master Mode Code Address*/ #define IG4_REG_DATA_CMD 0x0010 /* RW Data Buffer and Command */ #define IG4_REG_SS_SCL_HCNT 0x0014 /* RW Std Speed clock High Count */ #define IG4_REG_SS_SCL_LCNT 0x0018 /* RW Std Speed clock Low Count */ #define IG4_REG_FS_SCL_HCNT 0x001C /* RW Fast Speed clock High Count */ #define IG4_REG_FS_SCL_LCNT 0x0020 /* RW Fast Speed clock Low Count */ #define IG4_REG_INTR_STAT 0x002C /* RO Interrupt Status */ #define IG4_REG_INTR_MASK 0x0030 /* RW Interrupt Mask */ #define IG4_REG_RAW_INTR_STAT 0x0034 /* RO Raw Interrupt Status */ #define IG4_REG_RX_TL 0x0038 /* RW Receive FIFO Threshold */ #define IG4_REG_TX_TL 0x003C /* RW Transmit FIFO Threshold */ #define IG4_REG_CLR_INTR 0x0040 /* RO Clear Interrupt */ #define IG4_REG_CLR_RX_UNDER 0x0044 /* RO Clear RX_Under Interrupt */ #define IG4_REG_CLR_RX_OVER 0x0048 /* RO Clear RX_Over Interrupt */ #define IG4_REG_CLR_TX_OVER 0x004C /* RO Clear TX_Over Interrupt */ #define IG4_REG_CLR_RD_REQ 0x0050 /* RO Clear RD_Req Interrupt */ #define IG4_REG_CLR_TX_ABORT 0x0054 /* RO Clear TX_Abort Interrupt */ #define IG4_REG_CLR_RX_DONE 0x0058 /* RO Clear RX_Done Interrupt */ #define IG4_REG_CLR_ACTIVITY 0x005C /* RO Clear Activity Interrupt */ #define IG4_REG_CLR_STOP_DET 0x0060 /* RO Clear STOP Detection Int */ #define IG4_REG_CLR_START_DET 0x0064 /* RO Clear START Detection Int */ #define IG4_REG_CLR_GEN_CALL 0x0068 /* RO Clear General Call Interrupt */ #define IG4_REG_I2C_EN 0x006C /* RW I2C Enable */ #define IG4_REG_I2C_STA 0x0070 /* RO I2C Status */ #define IG4_REG_TXFLR 0x0074 /* RO Transmit FIFO Level */ #define IG4_REG_RXFLR 0x0078 /* RO Receive FIFO Level */ #define IG4_REG_SDA_HOLD 0x007C /* RW SDA Hold Time Length */ #define IG4_REG_TX_ABRT_SOURCE 0x0080 /* RO Transmit Abort Source */ #define IG4_REG_SLV_DATA_NACK 0x0084 /* RW General Slave Data NACK */ #define IG4_REG_DMA_CTRL 0x0088 /* RW DMA Control */ #define IG4_REG_DMA_TDLR 0x008C /* RW DMA Transmit Data Level */ #define IG4_REG_DMA_RDLR 0x0090 /* RW DMA Receive Data Level */ #define IG4_REG_SDA_SETUP 0x0094 /* RW SDA Setup */ #define IG4_REG_ACK_GENERAL_CALL 0x0098 /* RW I2C ACK General Call */ #define IG4_REG_ENABLE_STATUS 0x009C /* RO Enable Status */ /* Available at least on Atom SoCs, Haswell mobile and some Skylakes. */ #define IG4_REG_COMP_PARAM1 0x00F4 /* RO Component Parameter */ #define IG4_REG_COMP_VER 0x00F8 /* RO Component Version */ /* Available at least on Atom SoCs */ #define IG4_REG_COMP_TYPE 0x00FC /* RO Probe width/endian? (linux) */ /* Available on Skylake-U/Y and Kaby Lake-U/Y */ #define IG4_REG_RESETS_SKL 0x0204 /* RW Reset Register */ #define IG4_REG_ACTIVE_LTR_VALUE 0x0210 /* RW Active LTR Value */ #define IG4_REG_IDLE_LTR_VALUE 0x0214 /* RW Idle LTR Value */ #define IG4_REG_TX_ACK_COUNT 0x0218 /* RO TX ACK Count */ #define IG4_REG_RX_BYTE_COUNT 0x021C /* RO RX ACK Count */ #define IG4_REG_DEVIDLE_CTRL 0x024C /* RW Device Control */ /* Available at least on Atom SoCs */ #define IG4_REG_CLK_PARMS 0x0800 /* RW Clock Parameters */ /* Available at least on Atom SoCs and Haswell mobile */ #define IG4_REG_RESETS_HSW 0x0804 /* RW Reset Register */ #define IG4_REG_GENERAL 0x0808 /* RW General Register */ /* These LTR config registers are at least available on Haswell mobile. */ #define IG4_REG_SW_LTR_VALUE 0x0810 /* RW SW LTR Value */ #define IG4_REG_AUTO_LTR_VALUE 0x0814 /* RW Auto LTR Value */ /* * CTL - Control Register 22.2.1 * Default Value: 0x0000007F. * * RESTARTEN - RW Restart Enable * 10BIT - RW Controller operates in 10-bit mode, else 7-bit * * NOTE: When restart is disabled the controller is incapable of * performing the following functions: * * Sending a START Byte * Performing any high-speed mode op * Performing direction changes in combined format mode * Performing a read operation with a 10-bit address * * Attempting to perform the above operations will result in the * TX_ABORT bit being set in RAW_INTR_STAT. */ #define IG4_CTL_SLAVE_DISABLE 0x0040 /* snarfed from linux */ #define IG4_CTL_RESTARTEN 0x0020 /* Allow Restart when master */ #define IG4_CTL_10BIT 0x0010 /* ctlr accepts 10-bit addresses */ #define IG4_CTL_SPEED_MASK 0x0006 /* speed at which the I2C operates */ #define IG4_CTL_MASTER 0x0001 /* snarfed from linux */ #define IG4_CTL_SPEED_HIGH 0x0006 /* snarfed from linux */ #define IG4_CTL_SPEED_FAST 0x0004 /* snarfed from linux */ #define IG4_CTL_SPEED_STD 0x0002 /* snarfed from linux */ /* * TAR_ADD - Target Address Register 22.2.2 * Default Value: 0x00000055F * * 10BIT - RW controller starts its transfers in 10-bit * address mode, else 7-bit. * * SPECIAL - RW Indicates whether software performs a General Call * or START BYTE command. * * 0 Ignore GC_OR_START and use TAR address. * * 1 Perform special I2C Command based on GC_OR_START. * * GC_OR_START - RW (only if SPECIAL is set) * * 0 General Call Address. After issuing a General Call, * only writes may be performed. Attempting to issue * a read command results in IX_ABRT in RAW_INTR_STAT. * The controller remains in General Call mode until * bit 11 (SPECIAL) is cleared. * * 1 START BYTE. * * * IC_TAR - RW when transmitting a general call, these bits are * ignored. To generate a START BYTE, the address * needs to be written into these bits once. * * This register should only be updated when the IIC is disabled (I2C_ENABLE=0) */ #define IG4_TAR_10BIT 0x1000 /* start xfer in 10-bit mode */ #define IG4_TAR_SPECIAL 0x0800 /* Perform special command */ #define IG4_TAR_GC_OR_START 0x0400 /* General Call or Start */ #define IG4_TAR_ADDR_MASK 0x03FF /* Target address */ /* * TAR_DATA_CMD - Data Buffer and Command Register 22.2.3 * * RESTART - RW This bit controls whether a forced RESTART is * issued before the byte is sent or received. * * 0 If not set a RESTART is only issued if the transfer * direction is changing from the previous command. * * 1 A RESTART is issued before the byte is sent or * received, regardless of whether or not the transfer * direction is changing from the previous command. * * STOP - RW This bit controls whether a STOP is issued after * the byte is sent or received. * * 0 STOP is not issued after this byte, regardless * of whether or not the Tx FIFO is empty. * * 1 STOP is issued after this byte, regardless of * whether or not the Tx FIFO is empty. If the * Tx FIFO is not empty the master immediately tries * to start a new transfer by issuing a START and * arbitrating for the bus. * * i.e. the STOP is issued along with this byte, * within the write stream. * * COMMAND - RW Control whether a read or write is performed. * * 0 WRITE * * 1 READ * * DATA (7:0) - RW Contains the data to be transmitted or received * on the I2C bus. * * NOTE: Writing to this register causes a START + slave + RW to be * issued if the direction has changed or the last data byte was * sent with a STOP. * * NOTE: We control termination? so this register must be written * for each byte we wish to receive. We can then drain the * receive FIFO. */ #define IG4_DATA_RESTART 0x0400 /* Force RESTART */ #define IG4_DATA_STOP 0x0200 /* Force STOP[+START] */ #define IG4_DATA_COMMAND_RD 0x0100 /* bus direction 0=write 1=read */ #define IG4_DATA_MASK 0x00FF /* * SS_SCL_HCNT - Standard Speed Clock High Count Register 22.2.4 * SS_SCL_LCNT - Standard Speed Clock Low Count Register 22.2.5 * FS_SCL_HCNT - Fast Speed Clock High Count Register 22.2.6 * FS_SCL_LCNT - Fast Speed Clock Low Count Register 22.2.7 * * COUNT (15:0) - Set the period count to a value between 6 and * 65525. */ #define IG4_SCL_CLOCK_MASK 0xFFFFU /* count bits in register */ /* * INTR_STAT - (RO) Interrupt Status Register 22.2.8 * INTR_MASK - (RW) Interrupt Mask Register 22.2.9 * RAW_INTR_STAT- (RO) Raw Interrupt Status Register 22.2.10 * * GEN_CALL Set only when a general call (broadcast) address * is received and acknowleged, stays set until * cleared by reading CLR_GEN_CALL. * * START_DET Set when a START or RESTART condition has occurred * on the interface. * * STOP_DET Set when a STOP condition has occurred on the * interface. * * ACTIVITY Set by any activity on the interface. Cleared * by reading CLR_ACTIVITY or CLR_INTR. * * TX_ABRT Indicates the controller as a transmitter is * unable to complete the intended action. When set, * the controller will hold the TX FIFO in a reset * state (flushed) until CLR_TX_ABORT is read to * clear the condition. Once cleared, the TX FIFO * will be available again. * * TX_EMPTY Indicates that the transmitter is at or below * the specified TX_TL threshold. Automatically * cleared by HW when the buffer level goes above * the threshold. * * TX_OVER Indicates that the processor attempted to write * to the TX FIFO while the TX FIFO was full. Cleared * by reading CLR_TX_OVER. * * RX_FULL Indicates that the receive FIFO has reached or * exceeded the specified RX_TL threshold. Cleared * by HW when the cpu drains the FIFO to below the * threshold. * * RX_OVER Indicates that the receive FIFO was unable to * accept new data and data was lost. Cleared by * reading CLR_RX_OVER. * * RX_UNDER Indicates that the cpu attempted to read data * from the receive buffer while the RX FIFO was * empty. Cleared by reading CLR_RX_UNDER. * * NOTES ON RAW_INTR_STAT: * * This register can be used to monitor the GEN_CALL, START_DET, * STOP_DET, ACTIVITY, TX_ABRT, TX_EMPTY, TX_OVER, RX_FULL, RX_OVER, * and RX_UNDER bits. The documentation is a bit unclear but presumably * this is the unlatched version. * * Code should test FIFO conditions using the I2C_STA (status) register, * not the interrupt status registers. */ #define IG4_INTR_GEN_CALL 0x0800 #define IG4_INTR_START_DET 0x0400 #define IG4_INTR_STOP_DET 0x0200 #define IG4_INTR_ACTIVITY 0x0100 #define IG4_INTR_TX_ABRT 0x0040 #define IG4_INTR_TX_EMPTY 0x0010 #define IG4_INTR_TX_OVER 0x0008 #define IG4_INTR_RX_FULL 0x0004 #define IG4_INTR_RX_OVER 0x0002 #define IG4_INTR_RX_UNDER 0x0001 +#define IG4_INTR_ERR_MASK (IG4_INTR_TX_ABRT | IG4_INTR_TX_OVER | \ + IG4_INTR_RX_OVER | IG4_INTR_RX_UNDER) + /* * RX_TL - (RW) Receive FIFO Threshold Register 22.2.11 * TX_TL - (RW) Transmit FIFO Threshold Register 22.2.12 * * Specify the receive and transmit FIFO threshold register. The * FIFOs have 16 elements. The valid range is 0-15. Setting a * value greater than 15 causes the actual value to be the maximum * depth of the FIFO. * * Generally speaking since everything is messaged, we can use a * mid-level setting for both parameters and (e.g.) fully drain the * receive FIFO on the STOP_DET condition to handle loose ends. */ #define IG4_FIFO_MASK 0x00FF #define IG4_FIFO_LIMIT 16 /* * CLR_INTR - (RO) Clear Interrupt Register 22.2.13 * CLR_RX_UNDER - (RO) Clear Interrupt Register (specific) 22.2.14 * CLR_RX_OVER - (RO) Clear Interrupt Register (specific) 22.2.15 * CLR_TX_OVER - (RO) Clear Interrupt Register (specific) 22.2.16 * CLR_TX_ABORT - (RO) Clear Interrupt Register (specific) 22.2.17 * CLR_ACTIVITY - (RO) Clear Interrupt Register (specific) 22.2.18 * CLR_STOP_DET - (RO) Clear Interrupt Register (specific) 22.2.19 * CLR_START_DET- (RO) Clear Interrupt Register (specific) 22.2.20 * CLR_GEN_CALL - (RO) Clear Interrupt Register (specific) 22.2.21 * * CLR_* specific operations clear the appropriate bit in the * RAW_INTR_STAT register. Intel does not really document whether * these operations clear the normal interrupt status register. * * CLR_INTR clears bits in the normal interrupt status register and * presumably also the raw(?) register? Intel is again unclear. * * NOTE: CLR_INTR only clears software-clearable interrupts. Hardware * clearable interrupts are controlled entirely by the hardware. * CLR_INTR also clears the TX_ABRT_SOURCE register. * * NOTE: CLR_TX_ABORT also clears the TX_ABRT_SOURCE register and releases * the TX FIFO from its flushed/reset state, allowing more writes * to the TX FIFO. * * NOTE: CLR_ACTIVITY has no effect if the I2C bus is still active. * Intel documents that the bit is automatically cleared when * there is no further activity on the bus. */ #define IG4_CLR_BIT 0x0001 /* Reflects source */ /* * I2C_EN - (RW) I2C Enable Register 22.2.22 * * ABORT Software can abort an I2C transfer by setting this * bit. Hardware will clear the bit once the STOP has * been detected. This bit can only be set while the * I2C interface is enabled. * * I2C_ENABLE Enable the controller, else disable it. * (Use I2C_ENABLE_STATUS to poll enable status * & wait for changes) */ #define IG4_I2C_ABORT 0x0002 #define IG4_I2C_ENABLE 0x0001 /* * I2C_STA - (RO) I2C Status Register 22.2.23 */ #define IG4_STATUS_ACTIVITY 0x0020 /* Controller is active */ #define IG4_STATUS_RX_FULL 0x0010 /* RX FIFO completely full */ #define IG4_STATUS_RX_NOTEMPTY 0x0008 /* RX FIFO not empty */ #define IG4_STATUS_TX_EMPTY 0x0004 /* TX FIFO completely empty */ #define IG4_STATUS_TX_NOTFULL 0x0002 /* TX FIFO not full */ #define IG4_STATUS_I2C_ACTIVE 0x0001 /* I2C bus is active */ /* * TXFLR - (RO) Transmit FIFO Level Register 22.2.24 * RXFLR - (RO) Receive FIFO Level Register 22.2.25 * * Read the number of entries currently in the Transmit or Receive * FIFOs. Note that for some reason the mask is 9 bits instead of * the 8 bits the fill level controls. */ #define IG4_FIFOLVL_MASK 0x01FF /* * SDA_HOLD - (RW) SDA Hold Time Length Register 22.2.26 * * Set the SDA hold time length register in I2C clocks. */ #define IG4_SDA_TX_HOLD_MASK 0x0000FFFF /* * TX_ABRT_SOURCE- (RO) Transmit Abort Source Register 22.2.27 * * Indicates the cause of a transmit abort. This can indicate a * software programming error or a device expected address width * mismatch or other issues. The NORESTART conditions and GENCALL_NOACK * can only occur if a programming error was made in the driver software. * * In particular, it should be possible to detect whether any devices * are on the bus by observing the GENCALL_READ status, and it might * be possible to detect ADDR7 vs ADDR10 mismatches. */ #define IG4_ABRTSRC_TRANSFER 0x00010000 /* Abort initiated by user */ #define IG4_ABRTSRC_ARBLOST 0x00001000 /* Arbitration lost */ #define IG4_ABRTSRC_NORESTART_10 0x00000400 /* RESTART disabled */ #define IG4_ABRTSRC_NORESTART_START 0x00000200 /* RESTART disabled */ #define IG4_ABRTSRC_ACKED_START 0x00000080 /* Improper acked START */ -#define IG4_ABRTSRC_GENCALL_NOACK 0x00000020 /* Improper GENCALL */ -#define IG4_ABRTSRC_GENCALL_READ 0x00000010 /* Nobody acked GENCALL */ +#define IG4_ABRTSRC_GENCALL_READ 0x00000020 /* Improper GENCALL */ +#define IG4_ABRTSRC_GENCALL_NOACK 0x00000010 /* Nobody acked GENCALL */ #define IG4_ABRTSRC_TXNOACK_DATA 0x00000008 /* data phase no ACK */ #define IG4_ABRTSRC_TXNOACK_ADDR10_2 0x00000004 /* addr10/1 phase no ACK */ #define IG4_ABRTSRC_TXNOACK_ADDR10_1 0x00000002 /* addr10/2 phase no ACK */ #define IG4_ABRTSRC_TXNOACK_ADDR7 0x00000001 /* addr7 phase no ACK */ /* * SLV_DATA_NACK - (RW) Generate Slave DATA NACK Register 22.2.28 * * When the controller is a receiver a NACK can be generated on * receipt of data. * * NACK_GENERATE Set to 0 for normal NACK/ACK generation. * Set to 1 to generate a NACK after next data * byte received. * */ #define IG4_NACK_GENERATE 0x0001 /* * DMA_CTRL - (RW) DMA Control Register 22.2.29 * * Enables DMA on the transmit and/or receive DMA channel. */ #define IG4_TX_DMA_ENABLE 0x0002 #define IG4_RX_DMA_ENABLE 0x0001 /* * DMA_TDLR - (RW) DMA Transmit Data Level Register 22.2.30 * DMA_RDLR - (RW) DMA Receive Data Level Register 22.2.31 * * Similar to RX_TL and TX_TL but controls when a DMA burst occurs * to empty or fill the FIFOs. Use the same IG4_FIFO_MASK and * IG4_FIFO_LIMIT defines for RX_RL and TX_TL. */ /* empty */ /* * SDA_SETUP - (RW) SDA Setup Time Length Register 22.2.32 * * Set the SDA setup time length register in I2C clocks. * The register must be programmed with a value >=2. * (Defaults to 0x64). */ #define IG4_SDA_SETUP_MASK 0x00FF /* * ACK_GEN_CALL - (RW) ACK General Call Register 22.2.33 * * Control whether the controller responds with a ACK or NACK when * it receives an I2C General Call address. * * If set to 0 a NACK is generated and a General Call interrupt is * NOT generated. Otherwise an ACK + interrupt is generated. */ #define IG4_ACKGC_ACK 0x0001 /* * ENABLE_STATUS - (RO) Enable Status Registger 22.2.34 * * DATA_LOST - Indicates that a slave receiver operation has * been aborted with at least one data byte received * from a transfer due to the I2C controller being * disabled (IG4_I2C_ENABLE -> 0) * * ENABLED - Intel documentation is lacking but I assume this * is a reflection of the IG4_I2C_ENABLE bit in the * I2C_EN register. * */ #define IG4_ENASTAT_DATA_LOST 0x0004 #define IG4_ENASTAT_ENABLED 0x0001 /* * COMP_PARAM1 - (RO) Component Parameter Register 22.2.35 * Default Value 0x00FFFF6E * * VALID - Intel documentation is unclear but I believe this * must be read as a 1 to indicate that the rest of * the bits in the register are valid. * * HASDMA - Indicates that the chip is DMA-capable. Presumably * in certain virtualization cases the chip might be * set to not be DMA-capable. * * INTR_IO - Indicates that all interrupts are combined to * generate one interrupt. If not set, interrupts * are individual (more virtualization stuff?) * * HCCNT_RO - Indicates that the clock timing registers are * RW. If not set, the registers are RO. * (more virtualization stuff). * * MAXSPEED - Indicates the maximum speed supported. * * DATAW - Indicates the internal bus width in bits. */ #define IG4_PARAM1_TXFIFO_DEPTH(v) ((((v) >> 16) & 0xFF) + 1) #define IG4_PARAM1_RXFIFO_DEPTH(v) ((((v) >> 8) & 0xFF) + 1) #define IG4_PARAM1_CONFIG_VALID 0x00000080 #define IG4_PARAM1_CONFIG_HASDMA 0x00000040 #define IG4_PARAM1_CONFIG_INTR_IO 0x00000020 #define IG4_PARAM1_CONFIG_HCCNT_RO 0x00000010 #define IG4_PARAM1_CONFIG_MAXSPEED_MASK 0x0000000C #define IG4_PARAM1_CONFIG_DATAW_MASK 0x00000003 #define IG4_CONFIG_MAXSPEED_RESERVED00 0x00000000 #define IG4_CONFIG_MAXSPEED_STANDARD 0x00000004 #define IG4_CONFIG_MAXSPEED_FAST 0x00000008 #define IG4_CONFIG_MAXSPEED_HIGH 0x0000000C #define IG4_CONFIG_DATAW_8 0x00000000 #define IG4_CONFIG_DATAW_16 0x00000001 #define IG4_CONFIG_DATAW_32 0x00000002 #define IG4_CONFIG_DATAW_RESERVED11 0x00000003 /* * COMP_VER - (RO) Component Version Register 22.2.36 * * Contains the chip version number. All 32 bits. */ #define IG4_COMP_MIN_VER 0x3131352A /* * COMP_TYPE - (RO) (linux) Endian and bus width probe * * Read32 from this register and test against IG4_COMP_TYPE * to determine the bus width. e.g. 01404457 = endian-reversed, * and 00000140 or 00004457 means internal 16-bit bus (?). * * This register is not in the intel documentation, I pulled it * from the linux driver i2c-designware-core.c. */ #define IG4_COMP_TYPE 0x44570140 /* * RESETS - (RW) Resets Register 22.2.37 * * Used to reset the I2C host controller by SW. There is no timing * requirement, software can assert and de-assert in back-to-back * transactions. * * 00 I2C host controller is NOT in reset. * 01 (reserved) * 10 (reserved) * 11 I2C host controller is in reset. */ #define IG4_RESETS_ASSERT_HSW 0x0003 #define IG4_RESETS_DEASSERT_HSW 0x0000 /* Skylake-U/Y and Kaby Lake-U/Y have the reset bits inverted */ #define IG4_RESETS_DEASSERT_SKL 0x0003 #define IG4_RESETS_ASSERT_SKL 0x0000 /* Newer versions of the I2C controller allow to check whether * the above ASSERT/DEASSERT is necessary by querying the DEVIDLE_CONTROL * register. * * the RESTORE_REQUIRED bit can be cleared by writing 1 * the DEVICE_IDLE status can be set to put the controller in an idle state * */ #define IG4_RESTORE_REQUIRED 0x0008 #define IG4_DEVICE_IDLE 0x0004 /* * GENERAL - (RW) General Reigster 22.2.38 * * IOVOLT 0=1.8V 1=3.3V * * LTR 0=Auto 1=SW * * In Auto mode the BIOS will write to the host controller's * AUTO LTR Value register (offset 0x0814) with the active * state LTR value, and will write to the SW LTR Value register * (offset 0x0810) with the idle state LTR value. * * In SW mode the SW will write to the host controller SW LTR * value (offset 0x0810). It is the SW responsibility to update * the LTR with the appropriate value. */ #define IG4_GENERAL_IOVOLT3_3 0x0008 #define IG4_GENERAL_SWMODE 0x0004 /* * SW_LTR_VALUE - (RW) SW LTR Value Register 22.2.39 * AUTO_LTR_VALUE - (RW) SW LTR Value Register 22.2.40 * * Default value is 0x00000800 which means the best possible * service/response time. * * It isn't quite clear how the snooping works. There are two scale * bits for both sets but two of the four codes are reserved. The * *SNOOP_VALUE() is specified as a 10-bit latency value. If 0, it * indicates that the device cannot tolerate any delay and needs the * best possible service/response time. * * I think this is for snooping (testing) the I2C bus. The lowest * delay (0) probably runs the controller polling at a high, power hungry * rate. But I dunno. */ #define IG4_SWLTR_NSNOOP_REQ 0x80000000 /* (ro) */ #define IG4_SWLTR_NSNOOP_SCALE_MASK 0x1C000000 /* (ro) */ #define IG4_SWLTR_NSNOOP_SCALE_1US 0x08000000 /* (ro) */ #define IG4_SWLTR_NSNOOP_SCALE_32US 0x0C000000 /* (ro) */ #define IG4_SWLTR_NSNOOP_VALUE_DECODE(v) (((v) >> 16) & 0x3F) #define IG4_SWLTR_NSNOOP_VALUE_ENCODE(v) (((v) & 0x3F) << 16) #define IG4_SWLTR_SNOOP_REQ 0x00008000 /* (rw) */ #define IG4_SWLTR_SNOOP_SCALE_MASK 0x00001C00 /* (rw) */ #define IG4_SWLTR_SNOOP_SCALE_1US 0x00000800 /* (rw) */ #define IG4_SWLTR_SNOOP_SCALE_32US 0x00000C00 /* (rw) */ #define IG4_SWLTR_SNOOP_VALUE_DECODE(v) ((v) & 0x3F) #define IG4_SWLTR_SNOOP_VALUE_ENCODE(v) ((v) & 0x3F) #endif /* _ICHIIC_IG4_REG_H_ */