Index: head/sys/dev/ichiic/ig4_acpi.c =================================================================== --- head/sys/dev/ichiic/ig4_acpi.c (revision 354307) +++ head/sys/dev/ichiic/ig4_acpi.c (revision 354308) @@ -1,169 +1,187 @@ /*- * Copyright (c) 2016 Oleksandr Tymoshenko * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. */ #include __FBSDID("$FreeBSD$"); #include "opt_acpi.h" #include #include #include #include #include #include #include #include #include #include #include #include #include #include static int ig4iic_acpi_probe(device_t dev); static int ig4iic_acpi_attach(device_t dev); static int ig4iic_acpi_detach(device_t dev); static char *ig4iic_ids[] = { "INT33C2", "INT33C3", "INT3432", "INT3433", "80860F41", "808622C1", "AMDI0510", "AMDI0010", "APMC0D0F", NULL }; static int ig4iic_acpi_probe(device_t dev) { ig4iic_softc_t *sc; int rv; sc = device_get_softc(dev); if (acpi_disabled("ig4iic")) return (ENXIO); rv = ACPI_ID_PROBE(device_get_parent(dev), dev, ig4iic_ids, NULL); if (rv > 0) return (rv); device_set_desc(dev, "Designware I2C Controller"); return (rv); } static int ig4iic_acpi_attach(device_t dev) { ig4iic_softc_t *sc; int error; sc = device_get_softc(dev); sc->dev = dev; /* All the HIDs matched are Atom SOCs. */ sc->version = IG4_ATOM; sc->regs_rid = 0; sc->regs_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &sc->regs_rid, RF_ACTIVE); if (sc->regs_res == NULL) { device_printf(dev, "unable to map registers\n"); ig4iic_acpi_detach(dev); return (ENXIO); } sc->intr_rid = 0; sc->intr_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &sc->intr_rid, RF_SHAREABLE | RF_ACTIVE); if (sc->intr_res == NULL) { device_printf(dev, "unable to map interrupt\n"); ig4iic_acpi_detach(dev); return (ENXIO); } sc->platform_attached = 1; error = ig4iic_attach(sc); if (error) ig4iic_acpi_detach(dev); return (error); } static int ig4iic_acpi_detach(device_t dev) { ig4iic_softc_t *sc = device_get_softc(dev); int error; if (sc->platform_attached) { error = ig4iic_detach(sc); if (error) return (error); sc->platform_attached = 0; } if (sc->intr_res) { bus_release_resource(dev, SYS_RES_IRQ, sc->intr_rid, sc->intr_res); sc->intr_res = NULL; } if (sc->regs_res) { bus_release_resource(dev, SYS_RES_MEMORY, sc->regs_rid, sc->regs_res); sc->regs_res = NULL; } return (0); } +static int +ig4iic_acpi_suspend(device_t dev) +{ + ig4iic_softc_t *sc = device_get_softc(dev); + + return (ig4iic_suspend(sc)); +} + +static int +ig4iic_acpi_resume(device_t dev) +{ + ig4iic_softc_t *sc = device_get_softc(dev); + + return (ig4iic_resume(sc)); +} + static device_method_t ig4iic_acpi_methods[] = { /* Device interface */ DEVMETHOD(device_probe, ig4iic_acpi_probe), DEVMETHOD(device_attach, ig4iic_acpi_attach), DEVMETHOD(device_detach, ig4iic_acpi_detach), + DEVMETHOD(device_suspend, ig4iic_acpi_suspend), + DEVMETHOD(device_resume, ig4iic_acpi_resume), /* iicbus interface */ DEVMETHOD(iicbus_transfer, ig4iic_transfer), DEVMETHOD(iicbus_reset, ig4iic_reset), DEVMETHOD(iicbus_callback, ig4iic_callback), DEVMETHOD_END }; static driver_t ig4iic_acpi_driver = { "ig4iic", ig4iic_acpi_methods, sizeof(struct ig4iic_softc), }; DRIVER_MODULE(ig4iic, acpi, ig4iic_acpi_driver, ig4iic_devclass, 0, 0); MODULE_DEPEND(ig4iic, acpi, 1, 1, 1); Index: head/sys/dev/ichiic/ig4_iic.c =================================================================== --- head/sys/dev/ichiic/ig4_iic.c (revision 354307) +++ head/sys/dev/ichiic/ig4_iic.c (revision 354308) @@ -1,1044 +1,1095 @@ /* * Copyright (c) 2014 The DragonFly Project. All rights reserved. * * This code is derived from software contributed to The DragonFly Project * by Matthew Dillon and was subsequently ported * to FreeBSD by Michael Gmelin * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in * the documentation and/or other materials provided with the * distribution. * 3. Neither the name of The DragonFly Project nor the names of its * contributors may be used to endorse or promote products derived * from this software without specific, prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE * COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, * INCIDENTAL, SPECIAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES (INCLUDING, * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. */ #include __FBSDID("$FreeBSD$"); /* * Intel fourth generation mobile cpus integrated I2C device. * * See ig4_reg.h for datasheet reference and notes. * See ig4_var.h for locking semantics. */ #include "opt_acpi.h" #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #ifdef DEV_ACPI #include #include #include #endif #include #include #include #include #include #include #define TRANS_NORMAL 1 #define TRANS_PCALL 2 #define TRANS_BLOCK 3 #define DO_POLL(sc) (cold || kdb_active || SCHEDULER_STOPPED() || sc->poll) /* * tLOW, tHIGH periods of the SCL clock and maximal falling time of both * lines are taken from I2C specifications. */ #define IG4_SPEED_STD_THIGH 4000 /* nsec */ #define IG4_SPEED_STD_TLOW 4700 /* nsec */ #define IG4_SPEED_STD_TF_MAX 300 /* nsec */ #define IG4_SPEED_FAST_THIGH 600 /* nsec */ #define IG4_SPEED_FAST_TLOW 1300 /* nsec */ #define IG4_SPEED_FAST_TF_MAX 300 /* nsec */ /* * Ig4 hardware parameters except Haswell are taken from intel_lpss driver */ static const struct ig4_hw ig4iic_hw[] = { [IG4_HASWELL] = { .ic_clock_rate = 100, /* MHz */ .sda_hold_time = 90, /* nsec */ .txfifo_depth = 32, .rxfifo_depth = 32, }, [IG4_ATOM] = { .ic_clock_rate = 100, .sda_fall_time = 280, .scl_fall_time = 240, .sda_hold_time = 60, .txfifo_depth = 32, .rxfifo_depth = 32, }, [IG4_SKYLAKE] = { .ic_clock_rate = 120, .sda_hold_time = 230, }, [IG4_APL] = { .ic_clock_rate = 133, .sda_fall_time = 171, .scl_fall_time = 208, .sda_hold_time = 207, }, }; static void ig4iic_intr(void *cookie); static void ig4iic_dump(ig4iic_softc_t *sc); static int ig4_dump; SYSCTL_INT(_debug, OID_AUTO, ig4_dump, CTLFLAG_RW, &ig4_dump, 0, "Dump controller registers"); /* * Clock registers initialization control * 0 - Try read clock registers from ACPI and fallback to p.1. * 1 - Calculate values based on controller type (IC clock rate). * 2 - Use values inherited from DragonflyBSD driver (old behavior). * 3 - Keep clock registers intact. */ static int ig4_timings; SYSCTL_INT(_debug, OID_AUTO, ig4_timings, CTLFLAG_RDTUN, &ig4_timings, 0, "Controller timings 0=ACPI, 1=predefined, 2=legacy, 3=do not change"); /* * Low-level inline support functions */ static __inline void reg_write(ig4iic_softc_t *sc, uint32_t reg, uint32_t value) { bus_write_4(sc->regs_res, reg, value); bus_barrier(sc->regs_res, reg, 4, BUS_SPACE_BARRIER_WRITE); } static __inline uint32_t reg_read(ig4iic_softc_t *sc, uint32_t reg) { uint32_t value; bus_barrier(sc->regs_res, reg, 4, BUS_SPACE_BARRIER_READ); value = bus_read_4(sc->regs_res, reg); return (value); } static void set_intr_mask(ig4iic_softc_t *sc, uint32_t val) { if (sc->intr_mask != val) { reg_write(sc, IG4_REG_INTR_MASK, val); sc->intr_mask = val; } } /* * Enable or disable the controller and wait for the controller to acknowledge * the state change. */ static int set_controller(ig4iic_softc_t *sc, uint32_t ctl) { int retry; int error; uint32_t v; /* * When the controller is enabled, interrupt on STOP detect * or receive character ready and clear pending interrupts. */ set_intr_mask(sc, 0); if (ctl & IG4_I2C_ENABLE) reg_read(sc, IG4_REG_CLR_INTR); reg_write(sc, IG4_REG_I2C_EN, ctl); error = IIC_ETIMEOUT; for (retry = 100; retry > 0; --retry) { v = reg_read(sc, IG4_REG_ENABLE_STATUS); if (((v ^ ctl) & IG4_I2C_ENABLE) == 0) { error = 0; break; } pause("i2cslv", 1); } return (error); } /* * Wait up to 25ms for the requested status using a 25uS polling loop. */ static int wait_status(ig4iic_softc_t *sc, uint32_t status) { uint32_t v; int error; int txlvl = -1; u_int count_us = 0; u_int limit_us = 25000; /* 25ms */ error = IIC_ETIMEOUT; for (;;) { /* * Check requested status */ v = reg_read(sc, IG4_REG_I2C_STA); if (v & status) { error = 0; break; } /* * When waiting for the transmit FIFO to become empty, * reset the timeout if we see a change in the transmit * FIFO level as progress is being made. */ if (status & IG4_STATUS_TX_EMPTY) { v = reg_read(sc, IG4_REG_TXFLR) & IG4_FIFOLVL_MASK; if (txlvl != v) { txlvl = v; count_us = 0; } } /* * Stop if we've run out of time. */ if (count_us >= limit_us) break; /* * When waiting for receive data let the interrupt do its * work, otherwise poll with the lock held. */ if ((status & IG4_STATUS_RX_NOTEMPTY) && !DO_POLL(sc)) { mtx_lock(&sc->io_lock); set_intr_mask(sc, IG4_INTR_STOP_DET | IG4_INTR_RX_FULL); mtx_sleep(sc, &sc->io_lock, 0, "i2cwait", (hz + 99) / 100); /* sleep up to 10ms */ set_intr_mask(sc, 0); mtx_unlock(&sc->io_lock); count_us += 10000; } else { DELAY(25); count_us += 25; } } return (error); } /* * Set the slave address. The controller must be disabled when * changing the address. * * This operation does not issue anything to the I2C bus but sets * the target address for when the controller later issues a START. */ static void set_slave_addr(ig4iic_softc_t *sc, uint8_t slave) { uint32_t tar; uint32_t ctl; int use_10bit; use_10bit = 0; if (sc->slave_valid && sc->last_slave == slave && sc->use_10bit == use_10bit) { return; } sc->use_10bit = use_10bit; /* * Wait for TXFIFO to drain before disabling the controller. * * If a write message has not been completed it's really a * programming error, but for now in that case issue an extra * byte + STOP. * * If a read message has not been completed it's also a programming * error, for now just ignore it. */ wait_status(sc, IG4_STATUS_TX_NOTFULL); if (sc->write_started) { reg_write(sc, IG4_REG_DATA_CMD, IG4_DATA_STOP); sc->write_started = 0; } if (sc->read_started) sc->read_started = 0; wait_status(sc, IG4_STATUS_TX_EMPTY); set_controller(sc, 0); ctl = reg_read(sc, IG4_REG_CTL); ctl &= ~IG4_CTL_10BIT; ctl |= IG4_CTL_RESTARTEN; tar = slave; if (sc->use_10bit) { tar |= IG4_TAR_10BIT; ctl |= IG4_CTL_10BIT; } reg_write(sc, IG4_REG_CTL, ctl); reg_write(sc, IG4_REG_TAR_ADD, tar); set_controller(sc, IG4_I2C_ENABLE); sc->slave_valid = 1; sc->last_slave = slave; } /* * IICBUS API FUNCTIONS */ static int ig4iic_xfer_start(ig4iic_softc_t *sc, uint16_t slave) { set_slave_addr(sc, slave >> 1); return (0); } /* * Amount of unread data before next burst to get better I2C bus utilization. * 2 bytes is enough in FAST mode. 8 bytes is better in FAST+ and HIGH modes. * Intel-recommended value is 16 for DMA transfers with 64-byte depth FIFOs. */ #define IG4_FIFO_LOWAT 2 static int ig4iic_read(ig4iic_softc_t *sc, uint8_t *buf, uint16_t len, bool repeated_start, bool stop) { uint32_t cmd; int requested = 0; int received = 0; int burst, target, lowat = 0; int error; if (len == 0) return (0); while (received < len) { burst = sc->cfg.txfifo_depth - (reg_read(sc, IG4_REG_TXFLR) & IG4_FIFOLVL_MASK); /* Ensure we have enough free space in RXFIFO */ burst = MIN(burst, sc->cfg.rxfifo_depth - lowat); if (burst <= 0) { error = wait_status(sc, IG4_STATUS_TX_NOTFULL); if (error) break; burst = 1; } target = MIN(requested + burst, (int)len); while (requested < target) { cmd = IG4_DATA_COMMAND_RD; if (repeated_start && requested == 0) cmd |= IG4_DATA_RESTART; if (stop && requested == len - 1) cmd |= IG4_DATA_STOP; reg_write(sc, IG4_REG_DATA_CMD, cmd); requested++; } /* Leave some data queued to maintain the hardware pipeline */ lowat = 0; if (requested != len && requested - received > IG4_FIFO_LOWAT) lowat = IG4_FIFO_LOWAT; /* After TXFLR fills up, clear it by reading available data */ while (received < requested - lowat) { burst = MIN((int)len - received, reg_read(sc, IG4_REG_RXFLR) & IG4_FIFOLVL_MASK); if (burst > 0) { while (burst--) buf[received++] = 0xFF & reg_read(sc, IG4_REG_DATA_CMD); } else { error = wait_status(sc, IG4_STATUS_RX_NOTEMPTY); if (error) goto out; } } } out: (void)reg_read(sc, IG4_REG_TX_ABRT_SOURCE); return (error); } static int ig4iic_write(ig4iic_softc_t *sc, uint8_t *buf, uint16_t len, bool repeated_start, bool stop) { uint32_t cmd; uint16_t i; int error; if (len == 0) return (0); cmd = repeated_start ? IG4_DATA_RESTART : 0; for (i = 0; i < len; i++) { error = wait_status(sc, IG4_STATUS_TX_NOTFULL); if (error) break; cmd |= buf[i]; cmd |= stop && i == len - 1 ? IG4_DATA_STOP : 0; reg_write(sc, IG4_REG_DATA_CMD, cmd); cmd = 0; } (void)reg_read(sc, IG4_REG_TX_ABRT_SOURCE); return (error); } int ig4iic_transfer(device_t dev, struct iic_msg *msgs, uint32_t nmsgs) { ig4iic_softc_t *sc = device_get_softc(dev); const char *reason = NULL; uint32_t i; int error; int unit; bool rpstart; bool stop; bool allocated; /* * The hardware interface imposes limits on allowed I2C messages. * It is not possible to explicitly send a start or stop. * They are automatically sent (or not sent, depending on the * configuration) when a data byte is transferred. * For this reason it's impossible to send a message with no data * at all (like an SMBus quick message). * The start condition is automatically generated after the stop * condition, so it's impossible to not have a start after a stop. * The repeated start condition is automatically sent if a change * of the transfer direction happens, so it's impossible to have * a change of direction without a (repeated) start. * The repeated start can be forced even without the change of * direction. * Changing the target slave address requires resetting the hardware * state, so it's impossible to do that without the stop followed * by the start. */ for (i = 0; i < nmsgs; i++) { #if 0 if (i == 0 && (msgs[i].flags & IIC_M_NOSTART) != 0) { reason = "first message without start"; break; } if (i == nmsgs - 1 && (msgs[i].flags & IIC_M_NOSTOP) != 0) { reason = "last message without stop"; break; } #endif if (msgs[i].len == 0) { reason = "message with no data"; break; } if (i > 0) { if ((msgs[i].flags & IIC_M_NOSTART) != 0 && (msgs[i - 1].flags & IIC_M_NOSTOP) == 0) { reason = "stop not followed by start"; break; } if ((msgs[i - 1].flags & IIC_M_NOSTOP) != 0 && msgs[i].slave != msgs[i - 1].slave) { reason = "change of slave without stop"; break; } if ((msgs[i].flags & IIC_M_NOSTART) != 0 && (msgs[i].flags & IIC_M_RD) != (msgs[i - 1].flags & IIC_M_RD)) { reason = "change of direction without repeated" " start"; break; } } } if (reason != NULL) { if (bootverbose) device_printf(dev, "%s\n", reason); return (IIC_ENOTSUPP); } /* Check if device is already allocated with iicbus_request_bus() */ allocated = sx_xlocked(&sc->call_lock) != 0; if (!allocated) sx_xlock(&sc->call_lock); /* Debugging - dump registers. */ if (ig4_dump) { unit = device_get_unit(dev); if (ig4_dump & (1 << unit)) { ig4_dump &= ~(1 << unit); ig4iic_dump(sc); } } /* * Clear any previous abort condition that may have been holding * the txfifo in reset. */ reg_read(sc, IG4_REG_CLR_TX_ABORT); rpstart = false; error = 0; for (i = 0; i < nmsgs; i++) { if ((msgs[i].flags & IIC_M_NOSTART) == 0) { error = ig4iic_xfer_start(sc, msgs[i].slave); } else { if (!sc->slave_valid || (msgs[i].slave >> 1) != sc->last_slave) { device_printf(dev, "start condition suppressed" "but slave address is not set up"); error = EINVAL; break; } rpstart = false; } if (error != 0) break; stop = (msgs[i].flags & IIC_M_NOSTOP) == 0; if (msgs[i].flags & IIC_M_RD) error = ig4iic_read(sc, msgs[i].buf, msgs[i].len, rpstart, stop); else error = ig4iic_write(sc, msgs[i].buf, msgs[i].len, rpstart, stop); if (error != 0) break; rpstart = !stop; } if (!allocated) sx_unlock(&sc->call_lock); return (error); } int ig4iic_reset(device_t dev, u_char speed, u_char addr, u_char *oldaddr) { ig4iic_softc_t *sc = device_get_softc(dev); bool allocated; allocated = sx_xlocked(&sc->call_lock) != 0; if (!allocated) sx_xlock(&sc->call_lock); /* TODO handle speed configuration? */ if (oldaddr != NULL) *oldaddr = sc->last_slave << 1; set_slave_addr(sc, addr >> 1); if (addr == IIC_UNKNOWN) sc->slave_valid = false; if (!allocated) sx_unlock(&sc->call_lock); return (0); } int ig4iic_callback(device_t dev, int index, caddr_t data) { ig4iic_softc_t *sc = device_get_softc(dev); int error = 0; int how; switch (index) { case IIC_REQUEST_BUS: /* force polling if ig4iic is requested with IIC_DONTWAIT */ how = *(int *)data; if ((how & IIC_WAIT) == 0) { if (sx_try_xlock(&sc->call_lock) == 0) error = IIC_EBUSBSY; else sc->poll = true; } else sx_xlock(&sc->call_lock); break; case IIC_RELEASE_BUS: sc->poll = false; sx_unlock(&sc->call_lock); break; default: error = errno2iic(EINVAL); } return (error); } /* * Clock register values can be calculated with following rough equations: * SCL_HCNT = ceil(IC clock rate * tHIGH) * SCL_LCNT = ceil(IC clock rate * tLOW) * SDA_HOLD = ceil(IC clock rate * SDA hold time) * Precise equations take signal's falling, rising and spike suppression * times in to account. They can be found in Synopsys or Intel documentation. * * Here we snarf formulas and defaults from Linux driver to be able to use * timing values provided by Intel LPSS driver "as is". */ static int ig4iic_clk_params(const struct ig4_hw *hw, int speed, uint16_t *scl_hcnt, uint16_t *scl_lcnt, uint16_t *sda_hold) { uint32_t thigh, tlow, tf_max; /* nsec */ uint32_t sda_fall_time; /* nsec */ uint32_t scl_fall_time; /* nsec */ switch (speed) { case IG4_CTL_SPEED_STD: thigh = IG4_SPEED_STD_THIGH; tlow = IG4_SPEED_STD_TLOW; tf_max = IG4_SPEED_STD_TF_MAX; break; case IG4_CTL_SPEED_FAST: thigh = IG4_SPEED_FAST_THIGH; tlow = IG4_SPEED_FAST_TLOW; tf_max = IG4_SPEED_FAST_TF_MAX; break; default: return (EINVAL); } /* Use slowest falling time defaults to be on the safe side */ sda_fall_time = hw->sda_fall_time == 0 ? tf_max : hw->sda_fall_time; *scl_hcnt = (uint16_t) ((hw->ic_clock_rate * (thigh + sda_fall_time) + 500) / 1000 - 3); scl_fall_time = hw->scl_fall_time == 0 ? tf_max : hw->scl_fall_time; *scl_lcnt = (uint16_t) ((hw->ic_clock_rate * (tlow + scl_fall_time) + 500) / 1000 - 1); /* * There is no "known good" default value for tHD;DAT so keep SDA_HOLD * intact if sda_hold_time value is not provided. */ if (hw->sda_hold_time != 0) *sda_hold = (uint16_t) ((hw->ic_clock_rate * hw->sda_hold_time + 500) / 1000); return (0); } #ifdef DEV_ACPI static ACPI_STATUS ig4iic_acpi_params(ACPI_HANDLE handle, char *method, uint16_t *scl_hcnt, uint16_t *scl_lcnt, uint16_t *sda_hold) { ACPI_BUFFER buf; ACPI_OBJECT *obj, *elems; ACPI_STATUS status; buf.Pointer = NULL; buf.Length = ACPI_ALLOCATE_BUFFER; status = AcpiEvaluateObject(handle, method, NULL, &buf); if (ACPI_FAILURE(status)) return (status); status = AE_TYPE; obj = (ACPI_OBJECT *)buf.Pointer; if (obj->Type == ACPI_TYPE_PACKAGE && obj->Package.Count == 3) { elems = obj->Package.Elements; *scl_hcnt = elems[0].Integer.Value & IG4_SCL_CLOCK_MASK; *scl_lcnt = elems[1].Integer.Value & IG4_SCL_CLOCK_MASK; *sda_hold = elems[2].Integer.Value & IG4_SDA_TX_HOLD_MASK; status = AE_OK; } AcpiOsFree(obj); return (status); } #endif /* DEV_ACPI */ static void ig4iic_get_config(ig4iic_softc_t *sc) { const struct ig4_hw *hw; uint32_t v; #ifdef DEV_ACPI ACPI_HANDLE handle; #endif /* Fetch default hardware config from controller */ sc->cfg.version = reg_read(sc, IG4_REG_COMP_VER); sc->cfg.bus_speed = reg_read(sc, IG4_REG_CTL) & IG4_CTL_SPEED_MASK; sc->cfg.ss_scl_hcnt = reg_read(sc, IG4_REG_SS_SCL_HCNT) & IG4_SCL_CLOCK_MASK; sc->cfg.ss_scl_lcnt = reg_read(sc, IG4_REG_SS_SCL_LCNT) & IG4_SCL_CLOCK_MASK; sc->cfg.fs_scl_hcnt = reg_read(sc, IG4_REG_FS_SCL_HCNT) & IG4_SCL_CLOCK_MASK; sc->cfg.fs_scl_lcnt = reg_read(sc, IG4_REG_FS_SCL_LCNT) & IG4_SCL_CLOCK_MASK; sc->cfg.ss_sda_hold = sc->cfg.fs_sda_hold = reg_read(sc, IG4_REG_SDA_HOLD) & IG4_SDA_TX_HOLD_MASK; if (sc->cfg.bus_speed != IG4_CTL_SPEED_STD) sc->cfg.bus_speed = IG4_CTL_SPEED_FAST; /* REG_COMP_PARAM1 is not documented in latest Intel specs */ if (sc->version == IG4_HASWELL || sc->version == IG4_ATOM) { v = reg_read(sc, IG4_REG_COMP_PARAM1); if (IG4_PARAM1_TXFIFO_DEPTH(v) != 0) sc->cfg.txfifo_depth = IG4_PARAM1_TXFIFO_DEPTH(v); if (IG4_PARAM1_RXFIFO_DEPTH(v) != 0) sc->cfg.rxfifo_depth = IG4_PARAM1_RXFIFO_DEPTH(v); } else { /* * Hardware does not allow FIFO Threshold Levels value to be * set larger than the depth of the buffer. If an attempt is * made to do that, the actual value set will be the maximum * depth of the buffer. */ v = reg_read(sc, IG4_REG_TX_TL); reg_write(sc, IG4_REG_TX_TL, v | IG4_FIFO_MASK); sc->cfg.txfifo_depth = (reg_read(sc, IG4_REG_TX_TL) & IG4_FIFO_MASK) + 1; reg_write(sc, IG4_REG_TX_TL, v); v = reg_read(sc, IG4_REG_RX_TL); reg_write(sc, IG4_REG_RX_TL, v | IG4_FIFO_MASK); sc->cfg.rxfifo_depth = (reg_read(sc, IG4_REG_RX_TL) & IG4_FIFO_MASK) + 1; reg_write(sc, IG4_REG_RX_TL, v); } /* Override hardware config with IC_clock-based counter values */ if (ig4_timings < 2 && sc->version < nitems(ig4iic_hw)) { hw = &ig4iic_hw[sc->version]; sc->cfg.bus_speed = IG4_CTL_SPEED_FAST; ig4iic_clk_params(hw, IG4_CTL_SPEED_STD, &sc->cfg.ss_scl_hcnt, &sc->cfg.ss_scl_lcnt, &sc->cfg.ss_sda_hold); ig4iic_clk_params(hw, IG4_CTL_SPEED_FAST, &sc->cfg.fs_scl_hcnt, &sc->cfg.fs_scl_lcnt, &sc->cfg.fs_sda_hold); if (hw->txfifo_depth != 0) sc->cfg.txfifo_depth = hw->txfifo_depth; if (hw->rxfifo_depth != 0) sc->cfg.rxfifo_depth = hw->rxfifo_depth; } else if (ig4_timings == 2) { /* * Timings of original ig4 driver: * Program based on a 25000 Hz clock. This is a bit of a * hack (obviously). The defaults are 400 and 470 for standard * and 60 and 130 for fast. The defaults for standard fail * utterly (presumably cause an abort) because the clock time * is ~18.8ms by default. This brings it down to ~4ms. */ sc->cfg.bus_speed = IG4_CTL_SPEED_STD; sc->cfg.ss_scl_hcnt = sc->cfg.fs_scl_hcnt = 100; sc->cfg.ss_scl_lcnt = sc->cfg.fs_scl_lcnt = 125; if (sc->version == IG4_SKYLAKE) sc->cfg.ss_sda_hold = sc->cfg.fs_sda_hold = 28; } #ifdef DEV_ACPI /* Evaluate SSCN and FMCN ACPI methods to fetch timings */ if (ig4_timings == 0 && (handle = acpi_get_handle(sc->dev)) != NULL) { ig4iic_acpi_params(handle, "SSCN", &sc->cfg.ss_scl_hcnt, &sc->cfg.ss_scl_lcnt, &sc->cfg.ss_sda_hold); ig4iic_acpi_params(handle, "FMCN", &sc->cfg.fs_scl_hcnt, &sc->cfg.fs_scl_lcnt, &sc->cfg.fs_sda_hold); } #endif if (bootverbose) { device_printf(sc->dev, "Controller parameters:\n"); printf(" Speed: %s\n", sc->cfg.bus_speed == IG4_CTL_SPEED_STD ? "Std" : "Fast"); printf(" Regs: HCNT :LCNT :SDAHLD\n"); printf(" Std: 0x%04hx:0x%04hx:0x%04hx\n", sc->cfg.ss_scl_hcnt, sc->cfg.ss_scl_lcnt, sc->cfg.ss_sda_hold); printf(" Fast: 0x%04hx:0x%04hx:0x%04hx\n", sc->cfg.fs_scl_hcnt, sc->cfg.fs_scl_lcnt, sc->cfg.fs_sda_hold); printf(" FIFO: RX:0x%04x: TX:0x%04x\n", sc->cfg.rxfifo_depth, sc->cfg.txfifo_depth); } } -/* - * Called from ig4iic_pci_attach/detach() - */ -int -ig4iic_attach(ig4iic_softc_t *sc) +static int +ig4iic_set_config(ig4iic_softc_t *sc) { - int error; uint32_t v; - mtx_init(&sc->io_lock, "IG4 I/O lock", NULL, MTX_DEF); - sx_init(&sc->call_lock, "IG4 call lock"); - - ig4iic_get_config(sc); - v = reg_read(sc, IG4_REG_DEVIDLE_CTRL); if (sc->version == IG4_SKYLAKE && (v & IG4_RESTORE_REQUIRED) ) { reg_write(sc, IG4_REG_DEVIDLE_CTRL, IG4_DEVICE_IDLE | IG4_RESTORE_REQUIRED); reg_write(sc, IG4_REG_DEVIDLE_CTRL, 0); reg_write(sc, IG4_REG_RESETS_SKL, IG4_RESETS_ASSERT_SKL); reg_write(sc, IG4_REG_RESETS_SKL, IG4_RESETS_DEASSERT_SKL); DELAY(1000); } if (sc->version == IG4_ATOM) v = reg_read(sc, IG4_REG_COMP_TYPE); if (sc->version == IG4_HASWELL || sc->version == IG4_ATOM) { v = reg_read(sc, IG4_REG_COMP_PARAM1); v = reg_read(sc, IG4_REG_GENERAL); /* * The content of IG4_REG_GENERAL is different for each * controller version. */ if (sc->version == IG4_HASWELL && (v & IG4_GENERAL_SWMODE) == 0) { v |= IG4_GENERAL_SWMODE; reg_write(sc, IG4_REG_GENERAL, v); v = reg_read(sc, IG4_REG_GENERAL); } } if (sc->version == IG4_HASWELL) { v = reg_read(sc, IG4_REG_SW_LTR_VALUE); v = reg_read(sc, IG4_REG_AUTO_LTR_VALUE); } else if (sc->version == IG4_SKYLAKE) { v = reg_read(sc, IG4_REG_ACTIVE_LTR_VALUE); v = reg_read(sc, IG4_REG_IDLE_LTR_VALUE); } if (sc->version == IG4_HASWELL || sc->version == IG4_ATOM) { v = reg_read(sc, IG4_REG_COMP_VER); - if (v < IG4_COMP_MIN_VER) { - error = ENXIO; - goto done; - } + if (v < IG4_COMP_MIN_VER) + return(ENXIO); } if (set_controller(sc, 0)) { device_printf(sc->dev, "controller error during attach-1\n"); - error = ENXIO; - goto done; + return (ENXIO); } reg_read(sc, IG4_REG_CLR_INTR); reg_write(sc, IG4_REG_INTR_MASK, 0); sc->intr_mask = 0; reg_write(sc, IG4_REG_SS_SCL_HCNT, sc->cfg.ss_scl_hcnt); reg_write(sc, IG4_REG_SS_SCL_LCNT, sc->cfg.ss_scl_lcnt); reg_write(sc, IG4_REG_FS_SCL_HCNT, sc->cfg.fs_scl_hcnt); reg_write(sc, IG4_REG_FS_SCL_LCNT, sc->cfg.fs_scl_lcnt); reg_write(sc, IG4_REG_SDA_HOLD, (sc->cfg.bus_speed & IG4_CTL_SPEED_MASK) == IG4_CTL_SPEED_STD ? sc->cfg.ss_sda_hold : sc->cfg.fs_sda_hold); /* * Use a threshold of 1 so we get interrupted on each character, * allowing us to use mtx_sleep() in our poll code. Not perfect * but this is better than using DELAY() for receiving data. * * See ig4_var.h for details on interrupt handler synchronization. */ reg_write(sc, IG4_REG_RX_TL, 0); reg_write(sc, IG4_REG_CTL, IG4_CTL_MASTER | IG4_CTL_SLAVE_DISABLE | IG4_CTL_RESTARTEN | (sc->cfg.bus_speed & IG4_CTL_SPEED_MASK)); + return (0); +} + +/* + * Called from ig4iic_pci_attach/detach() + */ +int +ig4iic_attach(ig4iic_softc_t *sc) +{ + int error; + + mtx_init(&sc->io_lock, "IG4 I/O lock", NULL, MTX_DEF); + sx_init(&sc->call_lock, "IG4 call lock"); + + ig4iic_get_config(sc); + + error = ig4iic_set_config(sc); + if (error) + goto done; + sc->iicbus = device_add_child(sc->dev, "iicbus", -1); if (sc->iicbus == NULL) { device_printf(sc->dev, "iicbus driver not found\n"); error = ENXIO; goto done; } #if 0 /* * Don't do this, it blows up the PCI config */ if (sc->version == IG4_HASWELL || sc->version == IG4_ATOM) { reg_write(sc, IG4_REG_RESETS_HSW, IG4_RESETS_ASSERT_HSW); reg_write(sc, IG4_REG_RESETS_HSW, IG4_RESETS_DEASSERT_HSW); } else if (sc->version = IG4_SKYLAKE) { reg_write(sc, IG4_REG_RESETS_SKL, IG4_RESETS_ASSERT_SKL); reg_write(sc, IG4_REG_RESETS_SKL, IG4_RESETS_DEASSERT_SKL); } #endif if (set_controller(sc, IG4_I2C_ENABLE)) { device_printf(sc->dev, "controller error during attach-2\n"); error = ENXIO; goto done; } if (set_controller(sc, 0)) { device_printf(sc->dev, "controller error during attach-3\n"); error = ENXIO; goto done; } error = bus_setup_intr(sc->dev, sc->intr_res, INTR_TYPE_MISC | INTR_MPSAFE, NULL, ig4iic_intr, sc, &sc->intr_handle); if (error) { device_printf(sc->dev, "Unable to setup irq: error %d\n", error); } error = bus_generic_attach(sc->dev); if (error) { device_printf(sc->dev, "failed to attach child: error %d\n", error); } done: return (error); } int ig4iic_detach(ig4iic_softc_t *sc) { int error; if (device_is_attached(sc->dev)) { error = bus_generic_detach(sc->dev); if (error) return (error); } if (sc->iicbus) device_delete_child(sc->dev, sc->iicbus); if (sc->intr_handle) bus_teardown_intr(sc->dev, sc->intr_res, sc->intr_handle); sx_xlock(&sc->call_lock); sc->iicbus = NULL; sc->intr_handle = NULL; reg_write(sc, IG4_REG_INTR_MASK, 0); set_controller(sc, 0); sx_xunlock(&sc->call_lock); mtx_destroy(&sc->io_lock); sx_destroy(&sc->call_lock); return (0); +} + +int +ig4iic_suspend(ig4iic_softc_t *sc) +{ + int error; + + /* suspend all children */ + error = bus_generic_suspend(sc->dev); + + sx_xlock(&sc->call_lock); + set_controller(sc, 0); + if (sc->version == IG4_SKYLAKE) { + /* + * Place the device in the idle state, just to be safe + */ + reg_write(sc, IG4_REG_DEVIDLE_CTRL, IG4_DEVICE_IDLE); + /* + * Controller can become dysfunctional if I2C lines are pulled + * down when suspend procedure turns off power to I2C device. + * Place device in the reset state to avoid this. + */ + reg_write(sc, IG4_REG_RESETS_SKL, IG4_RESETS_ASSERT_SKL); + } + sx_xunlock(&sc->call_lock); + + return (error); +} + +int ig4iic_resume(ig4iic_softc_t *sc) +{ + int error; + + sx_xlock(&sc->call_lock); + if (ig4iic_set_config(sc)) + device_printf(sc->dev, "controller error during resume\n"); + /* Force setting of the target address on the next transfer */ + sc->slave_valid = 0; + sx_xunlock(&sc->call_lock); + + error = bus_generic_resume(sc->dev); + + return (error); } /* * Interrupt Operation, see ig4_var.h for locking semantics. */ static void ig4iic_intr(void *cookie) { ig4iic_softc_t *sc = cookie; mtx_lock(&sc->io_lock); /* Ignore stray interrupts */ if (sc->intr_mask != 0 && reg_read(sc, IG4_REG_INTR_STAT) != 0) { set_intr_mask(sc, 0); reg_read(sc, IG4_REG_CLR_INTR); wakeup(sc); } mtx_unlock(&sc->io_lock); } #define REGDUMP(sc, reg) \ device_printf(sc->dev, " %-23s %08x\n", #reg, reg_read(sc, reg)) static void ig4iic_dump(ig4iic_softc_t *sc) { device_printf(sc->dev, "ig4iic register dump:\n"); REGDUMP(sc, IG4_REG_CTL); REGDUMP(sc, IG4_REG_TAR_ADD); REGDUMP(sc, IG4_REG_SS_SCL_HCNT); REGDUMP(sc, IG4_REG_SS_SCL_LCNT); REGDUMP(sc, IG4_REG_FS_SCL_HCNT); REGDUMP(sc, IG4_REG_FS_SCL_LCNT); REGDUMP(sc, IG4_REG_INTR_STAT); REGDUMP(sc, IG4_REG_INTR_MASK); REGDUMP(sc, IG4_REG_RAW_INTR_STAT); REGDUMP(sc, IG4_REG_RX_TL); REGDUMP(sc, IG4_REG_TX_TL); REGDUMP(sc, IG4_REG_I2C_EN); REGDUMP(sc, IG4_REG_I2C_STA); REGDUMP(sc, IG4_REG_TXFLR); REGDUMP(sc, IG4_REG_RXFLR); REGDUMP(sc, IG4_REG_SDA_HOLD); REGDUMP(sc, IG4_REG_TX_ABRT_SOURCE); REGDUMP(sc, IG4_REG_SLV_DATA_NACK); REGDUMP(sc, IG4_REG_DMA_CTRL); REGDUMP(sc, IG4_REG_DMA_TDLR); REGDUMP(sc, IG4_REG_DMA_RDLR); REGDUMP(sc, IG4_REG_SDA_SETUP); REGDUMP(sc, IG4_REG_ENABLE_STATUS); REGDUMP(sc, IG4_REG_COMP_PARAM1); REGDUMP(sc, IG4_REG_COMP_VER); if (sc->version == IG4_ATOM) { REGDUMP(sc, IG4_REG_COMP_TYPE); REGDUMP(sc, IG4_REG_CLK_PARMS); } if (sc->version == IG4_HASWELL || sc->version == IG4_ATOM) { REGDUMP(sc, IG4_REG_RESETS_HSW); REGDUMP(sc, IG4_REG_GENERAL); } else if (sc->version == IG4_SKYLAKE) { REGDUMP(sc, IG4_REG_RESETS_SKL); } if (sc->version == IG4_HASWELL) { REGDUMP(sc, IG4_REG_SW_LTR_VALUE); REGDUMP(sc, IG4_REG_AUTO_LTR_VALUE); } else if (sc->version == IG4_SKYLAKE) { REGDUMP(sc, IG4_REG_ACTIVE_LTR_VALUE); REGDUMP(sc, IG4_REG_IDLE_LTR_VALUE); } } #undef REGDUMP devclass_t ig4iic_devclass; DRIVER_MODULE(iicbus, ig4iic, iicbus_driver, iicbus_devclass, NULL, NULL); MODULE_DEPEND(ig4iic, iicbus, IICBUS_MINVER, IICBUS_PREFVER, IICBUS_MAXVER); MODULE_VERSION(ig4iic, 1); Index: head/sys/dev/ichiic/ig4_pci.c =================================================================== --- head/sys/dev/ichiic/ig4_pci.c (revision 354307) +++ head/sys/dev/ichiic/ig4_pci.c (revision 354308) @@ -1,232 +1,250 @@ /* * Copyright (c) 2014 The DragonFly Project. All rights reserved. * * This code is derived from software contributed to The DragonFly Project * by Matthew Dillon and was subsequently ported * to FreeBSD by Michael Gmelin * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in * the documentation and/or other materials provided with the * distribution. * 3. Neither the name of The DragonFly Project nor the names of its * contributors may be used to endorse or promote products derived * from this software without specific, prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE * COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, * INCIDENTAL, SPECIAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES (INCLUDING, * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. */ #include __FBSDID("$FreeBSD$"); /* * Intel fourth generation mobile cpus integrated I2C device. * * See ig4_reg.h for datasheet reference and notes. */ #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include static int ig4iic_pci_detach(device_t dev); #define PCI_CHIP_LYNXPT_LP_I2C_1 0x9c618086 #define PCI_CHIP_LYNXPT_LP_I2C_2 0x9c628086 #define PCI_CHIP_BRASWELL_I2C_1 0x22c18086 #define PCI_CHIP_BRASWELL_I2C_2 0x22c28086 #define PCI_CHIP_BRASWELL_I2C_3 0x22c38086 #define PCI_CHIP_BRASWELL_I2C_5 0x22c58086 #define PCI_CHIP_BRASWELL_I2C_6 0x22c68086 #define PCI_CHIP_BRASWELL_I2C_7 0x22c78086 #define PCI_CHIP_SKYLAKE_I2C_0 0x9d608086 #define PCI_CHIP_SKYLAKE_I2C_1 0x9d618086 #define PCI_CHIP_SKYLAKE_I2C_2 0x9d628086 #define PCI_CHIP_SKYLAKE_I2C_3 0x9d638086 #define PCI_CHIP_SKYLAKE_I2C_4 0x9d648086 #define PCI_CHIP_SKYLAKE_I2C_5 0x9d658086 #define PCI_CHIP_KABYLAKE_I2C_0 0xa1608086 #define PCI_CHIP_KABYLAKE_I2C_1 0xa1618086 #define PCI_CHIP_APL_I2C_0 0x5aac8086 #define PCI_CHIP_APL_I2C_1 0x5aae8086 #define PCI_CHIP_APL_I2C_2 0x5ab08086 #define PCI_CHIP_APL_I2C_3 0x5ab28086 #define PCI_CHIP_APL_I2C_4 0x5ab48086 #define PCI_CHIP_APL_I2C_5 0x5ab68086 #define PCI_CHIP_APL_I2C_6 0x5ab88086 #define PCI_CHIP_APL_I2C_7 0x5aba8086 struct ig4iic_pci_device { uint32_t devid; const char *desc; enum ig4_vers version; }; static struct ig4iic_pci_device ig4iic_pci_devices[] = { { PCI_CHIP_LYNXPT_LP_I2C_1, "Intel Lynx Point-LP I2C Controller-1", IG4_HASWELL}, { PCI_CHIP_LYNXPT_LP_I2C_2, "Intel Lynx Point-LP I2C Controller-2", IG4_HASWELL}, { PCI_CHIP_BRASWELL_I2C_1, "Intel Braswell Serial I/O I2C Port 1", IG4_ATOM}, { PCI_CHIP_BRASWELL_I2C_2, "Intel Braswell Serial I/O I2C Port 2", IG4_ATOM}, { PCI_CHIP_BRASWELL_I2C_3, "Intel Braswell Serial I/O I2C Port 3", IG4_ATOM}, { PCI_CHIP_BRASWELL_I2C_5, "Intel Braswell Serial I/O I2C Port 5", IG4_ATOM}, { PCI_CHIP_BRASWELL_I2C_6, "Intel Braswell Serial I/O I2C Port 6", IG4_ATOM}, { PCI_CHIP_BRASWELL_I2C_7, "Intel Braswell Serial I/O I2C Port 7", IG4_ATOM}, { PCI_CHIP_SKYLAKE_I2C_0, "Intel Sunrise Point-LP I2C Controller-0", IG4_SKYLAKE}, { PCI_CHIP_SKYLAKE_I2C_1, "Intel Sunrise Point-LP I2C Controller-1", IG4_SKYLAKE}, { PCI_CHIP_SKYLAKE_I2C_2, "Intel Sunrise Point-LP I2C Controller-2", IG4_SKYLAKE}, { PCI_CHIP_SKYLAKE_I2C_3, "Intel Sunrise Point-LP I2C Controller-3", IG4_SKYLAKE}, { PCI_CHIP_SKYLAKE_I2C_4, "Intel Sunrise Point-LP I2C Controller-4", IG4_SKYLAKE}, { PCI_CHIP_SKYLAKE_I2C_5, "Intel Sunrise Point-LP I2C Controller-5", IG4_SKYLAKE}, { PCI_CHIP_KABYLAKE_I2C_0, "Intel Sunrise Point-H I2C Controller-0", IG4_SKYLAKE}, { PCI_CHIP_KABYLAKE_I2C_1, "Intel Sunrise Point-H I2C Controller-1", IG4_SKYLAKE}, { PCI_CHIP_APL_I2C_0, "Intel Apollo Lake I2C Controller-0", IG4_APL}, { PCI_CHIP_APL_I2C_1, "Intel Apollo Lake I2C Controller-1", IG4_APL}, { PCI_CHIP_APL_I2C_2, "Intel Apollo Lake I2C Controller-2", IG4_APL}, { PCI_CHIP_APL_I2C_3, "Intel Apollo Lake I2C Controller-3", IG4_APL}, { PCI_CHIP_APL_I2C_4, "Intel Apollo Lake I2C Controller-4", IG4_APL}, { PCI_CHIP_APL_I2C_5, "Intel Apollo Lake I2C Controller-5", IG4_APL}, { PCI_CHIP_APL_I2C_6, "Intel Apollo Lake I2C Controller-6", IG4_APL}, { PCI_CHIP_APL_I2C_7, "Intel Apollo Lake I2C Controller-7", IG4_APL} }; static int ig4iic_pci_probe(device_t dev) { ig4iic_softc_t *sc = device_get_softc(dev); uint32_t devid; int i; devid = pci_get_devid(dev); for (i = 0; i < nitems(ig4iic_pci_devices); i++) { if (ig4iic_pci_devices[i].devid == devid) { device_set_desc(dev, ig4iic_pci_devices[i].desc); sc->version = ig4iic_pci_devices[i].version; return (BUS_PROBE_DEFAULT); } } return (ENXIO); } static int ig4iic_pci_attach(device_t dev) { ig4iic_softc_t *sc = device_get_softc(dev); int error; sc->dev = dev; sc->regs_rid = PCIR_BAR(0); sc->regs_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &sc->regs_rid, RF_ACTIVE); if (sc->regs_res == NULL) { device_printf(dev, "unable to map registers\n"); ig4iic_pci_detach(dev); return (ENXIO); } sc->intr_rid = 0; if (pci_alloc_msi(dev, &sc->intr_rid)) { device_printf(dev, "Using MSI\n"); } sc->intr_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &sc->intr_rid, RF_SHAREABLE | RF_ACTIVE); if (sc->intr_res == NULL) { device_printf(dev, "unable to map interrupt\n"); ig4iic_pci_detach(dev); return (ENXIO); } sc->platform_attached = 1; error = ig4iic_attach(sc); if (error) ig4iic_pci_detach(dev); return (error); } static int ig4iic_pci_detach(device_t dev) { ig4iic_softc_t *sc = device_get_softc(dev); int error; if (sc->platform_attached) { error = ig4iic_detach(sc); if (error) return (error); sc->platform_attached = 0; } if (sc->intr_res) { bus_release_resource(dev, SYS_RES_IRQ, sc->intr_rid, sc->intr_res); sc->intr_res = NULL; } if (sc->intr_rid != 0) pci_release_msi(dev); if (sc->regs_res) { bus_release_resource(dev, SYS_RES_MEMORY, sc->regs_rid, sc->regs_res); sc->regs_res = NULL; } return (0); } +static int +ig4iic_pci_suspend(device_t dev) +{ + ig4iic_softc_t *sc = device_get_softc(dev); + + return (ig4iic_suspend(sc)); +} + +static int +ig4iic_pci_resume(device_t dev) +{ + ig4iic_softc_t *sc = device_get_softc(dev); + + return (ig4iic_resume(sc)); +} + static device_method_t ig4iic_pci_methods[] = { /* Device interface */ DEVMETHOD(device_probe, ig4iic_pci_probe), DEVMETHOD(device_attach, ig4iic_pci_attach), DEVMETHOD(device_detach, ig4iic_pci_detach), + DEVMETHOD(device_suspend, ig4iic_pci_suspend), + DEVMETHOD(device_resume, ig4iic_pci_resume), DEVMETHOD(iicbus_transfer, ig4iic_transfer), DEVMETHOD(iicbus_reset, ig4iic_reset), DEVMETHOD(iicbus_callback, ig4iic_callback), DEVMETHOD_END }; static driver_t ig4iic_pci_driver = { "ig4iic", ig4iic_pci_methods, sizeof(struct ig4iic_softc) }; DRIVER_MODULE_ORDERED(ig4iic, pci, ig4iic_pci_driver, ig4iic_devclass, 0, 0, SI_ORDER_ANY); MODULE_DEPEND(ig4iic, pci, 1, 1, 1); MODULE_PNP_INFO("W32:vendor/device", pci, ig4iic, ig4iic_pci_devices, nitems(ig4iic_pci_devices)); Index: head/sys/dev/ichiic/ig4_var.h =================================================================== --- head/sys/dev/ichiic/ig4_var.h (revision 354307) +++ head/sys/dev/ichiic/ig4_var.h (revision 354308) @@ -1,123 +1,125 @@ /* * Copyright (c) 2014 The DragonFly Project. All rights reserved. * * This code is derived from software contributed to The DragonFly Project * by Matthew Dillon and was subsequently ported * to FreeBSD by Michael Gmelin * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in * the documentation and/or other materials provided with the * distribution. * 3. Neither the name of The DragonFly Project nor the names of its * contributors may be used to endorse or promote products derived * from this software without specific, prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE * COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, * INCIDENTAL, SPECIAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES (INCLUDING, * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. * * $FreeBSD$ */ #ifndef _ICHIIC_IG4_VAR_H_ #define _ICHIIC_IG4_VAR_H_ #include "bus_if.h" #include "device_if.h" #include "pci_if.h" #include "iicbus_if.h" enum ig4_op { IG4_IDLE, IG4_READ, IG4_WRITE }; enum ig4_vers { IG4_HASWELL, IG4_ATOM, IG4_SKYLAKE, IG4_APL }; struct ig4_hw { uint32_t ic_clock_rate; /* MHz */ uint32_t sda_fall_time; /* nsec */ uint32_t scl_fall_time; /* nsec */ uint32_t sda_hold_time; /* nsec */ int txfifo_depth; int rxfifo_depth; }; struct ig4_cfg { uint32_t version; uint32_t bus_speed; uint16_t ss_scl_hcnt; uint16_t ss_scl_lcnt; uint16_t ss_sda_hold; uint16_t fs_scl_hcnt; uint16_t fs_scl_lcnt; uint16_t fs_sda_hold; int txfifo_depth; int rxfifo_depth; }; struct ig4iic_softc { device_t dev; device_t iicbus; struct resource *regs_res; int regs_rid; struct resource *intr_res; int intr_rid; void *intr_handle; int intr_type; enum ig4_vers version; enum ig4_op op; struct ig4_cfg cfg; int cmd; uint32_t intr_mask; int error; uint8_t last_slave; int platform_attached : 1; int use_10bit : 1; int slave_valid : 1; int read_started : 1; int write_started : 1; int poll: 1; /* * Locking semantics: * * Functions implementing the icbus interface that interact * with the controller acquire an exclusive lock on call_lock * to prevent interleaving of calls to the interface. * * io_lock is used as condition variable to synchronize active process * with the interrupt handler. It should not be used for tasks other * than waiting for interrupt and passing parameters to and from * it's handler. */ struct sx call_lock; struct mtx io_lock; }; typedef struct ig4iic_softc ig4iic_softc_t; extern devclass_t ig4iic_devclass; /* Attach/Detach called from ig4iic_pci_*() */ int ig4iic_attach(ig4iic_softc_t *sc); int ig4iic_detach(ig4iic_softc_t *sc); +int ig4iic_suspend(ig4iic_softc_t *sc); +int ig4iic_resume(ig4iic_softc_t *sc); /* iicbus methods */ extern iicbus_transfer_t ig4iic_transfer; extern iicbus_reset_t ig4iic_reset; extern iicbus_callback_t ig4iic_callback; #endif /* _ICHIIC_IG4_VAR_H_ */ Index: head/sys/dev/iicbus/iicbus.c =================================================================== --- head/sys/dev/iicbus/iicbus.c (revision 354307) +++ head/sys/dev/iicbus/iicbus.c (revision 354308) @@ -1,370 +1,372 @@ /*- * SPDX-License-Identifier: BSD-2-Clause-FreeBSD * * Copyright (c) 1998, 2001 Nicolas Souchu * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. */ #include __FBSDID("$FreeBSD$"); /* * Autoconfiguration and support routines for the Philips serial I2C bus */ #include #include #include #include #include #include #include #include #include #include #include #include #include "iicbus_if.h" /* See comments below for why auto-scanning is a bad idea. */ #define SCAN_IICBUS 0 static int iicbus_probe(device_t dev) { device_set_desc(dev, "Philips I2C bus"); /* Allow other subclasses to override this driver. */ return (BUS_PROBE_GENERIC); } #if SCAN_IICBUS static int iic_probe_device(device_t dev, u_char addr) { int count; char byte; if ((addr & 1) == 0) { /* is device writable? */ if (!iicbus_start(dev, (u_char)addr, 0)) { iicbus_stop(dev); return (1); } } else { /* is device readable? */ if (!iicbus_block_read(dev, (u_char)addr, &byte, 1, &count)) return (1); } return (0); } #endif /* * We add all the devices which we know about. * The generic attach routine will attach them if they are alive. */ static int iicbus_attach(device_t dev) { #if SCAN_IICBUS unsigned char addr; #endif struct iicbus_softc *sc = IICBUS_SOFTC(dev); int strict; sc->dev = dev; mtx_init(&sc->lock, "iicbus", NULL, MTX_DEF); iicbus_init_frequency(dev, 0); iicbus_reset(dev, IIC_FASTEST, 0, NULL); if (resource_int_value(device_get_name(dev), device_get_unit(dev), "strict", &strict) == 0) sc->strict = strict; else sc->strict = 1; /* device probing is meaningless since the bus is supposed to be * hot-plug. Moreover, some I2C chips do not appreciate random * accesses like stop after start to fast, reads for less than * x bytes... */ #if SCAN_IICBUS printf("Probing for devices on iicbus%d:", device_get_unit(dev)); /* probe any devices */ for (addr = 16; addr < 240; addr++) { if (iic_probe_device(dev, (u_char)addr)) { printf(" <%x>", addr); } } printf("\n"); #endif bus_generic_probe(dev); bus_enumerate_hinted_children(dev); bus_generic_attach(dev); return (0); } static int iicbus_detach(device_t dev) { struct iicbus_softc *sc = IICBUS_SOFTC(dev); iicbus_reset(dev, IIC_FASTEST, 0, NULL); bus_generic_detach(dev); device_delete_children(dev); mtx_destroy(&sc->lock); return (0); } static int iicbus_print_child(device_t dev, device_t child) { struct iicbus_ivar *devi = IICBUS_IVAR(child); int retval = 0; retval += bus_print_child_header(dev, child); if (devi->addr != 0) retval += printf(" at addr %#x", devi->addr); resource_list_print_type(&devi->rl, "irq", SYS_RES_IRQ, "%jd"); retval += bus_print_child_footer(dev, child); return (retval); } static void iicbus_probe_nomatch(device_t bus, device_t child) { struct iicbus_ivar *devi = IICBUS_IVAR(child); device_printf(bus, " at addr %#x\n", devi->addr); } static int iicbus_child_location_str(device_t bus, device_t child, char *buf, size_t buflen) { struct iicbus_ivar *devi = IICBUS_IVAR(child); snprintf(buf, buflen, "addr=%#x", devi->addr); return (0); } static int iicbus_child_pnpinfo_str(device_t bus, device_t child, char *buf, size_t buflen) { *buf = '\0'; return (0); } static int iicbus_read_ivar(device_t bus, device_t child, int which, uintptr_t *result) { struct iicbus_ivar *devi = IICBUS_IVAR(child); switch (which) { default: return (EINVAL); case IICBUS_IVAR_ADDR: *result = devi->addr; break; } return (0); } static int iicbus_write_ivar(device_t bus, device_t child, int which, uintptr_t value) { struct iicbus_ivar *devi = IICBUS_IVAR(child); switch (which) { default: return (EINVAL); case IICBUS_IVAR_ADDR: if (devi->addr != 0) return (EINVAL); devi->addr = value; } return (0); } static device_t iicbus_add_child(device_t dev, u_int order, const char *name, int unit) { device_t child; struct iicbus_ivar *devi; child = device_add_child_ordered(dev, order, name, unit); if (child == NULL) return (child); devi = malloc(sizeof(struct iicbus_ivar), M_DEVBUF, M_NOWAIT | M_ZERO); if (devi == NULL) { device_delete_child(dev, child); return (0); } resource_list_init(&devi->rl); device_set_ivars(child, devi); return (child); } static void iicbus_hinted_child(device_t bus, const char *dname, int dunit) { device_t child; int irq; struct iicbus_ivar *devi; child = BUS_ADD_CHILD(bus, 0, dname, dunit); devi = IICBUS_IVAR(child); resource_int_value(dname, dunit, "addr", &devi->addr); if (resource_int_value(dname, dunit, "irq", &irq) == 0) { if (bus_set_resource(child, SYS_RES_IRQ, 0, irq, 1) != 0) device_printf(bus, "warning: bus_set_resource() failed\n"); } } static struct resource_list * iicbus_get_resource_list(device_t bus __unused, device_t child) { struct iicbus_ivar *devi; devi = IICBUS_IVAR(child); return (&devi->rl); } int iicbus_generic_intr(device_t dev, int event, char *buf) { return (0); } int iicbus_null_callback(device_t dev, int index, caddr_t data) { return (0); } int iicbus_null_repeated_start(device_t dev, u_char addr) { return (IIC_ENOTSUPP); } void iicbus_init_frequency(device_t dev, u_int bus_freq) { struct iicbus_softc *sc = IICBUS_SOFTC(dev); /* * If a bus frequency value was passed in, use it. Otherwise initialize * it first to the standard i2c 100KHz frequency, then override that * from a hint if one exists. */ if (bus_freq > 0) sc->bus_freq = bus_freq; else { sc->bus_freq = 100000; resource_int_value(device_get_name(dev), device_get_unit(dev), "frequency", (int *)&sc->bus_freq); } /* * Set up the sysctl that allows the bus frequency to be changed. * It is flagged as a tunable so that the user can set the value in * loader(8), and that will override any other setting from any source. * The sysctl tunable/value is the one most directly controlled by the * user and thus the one that always takes precedence. */ SYSCTL_ADD_UINT(device_get_sysctl_ctx(dev), SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), OID_AUTO, "frequency", CTLFLAG_RW | CTLFLAG_TUN, &sc->bus_freq, sc->bus_freq, "Bus frequency in Hz"); } static u_int iicbus_get_frequency(device_t dev, u_char speed) { struct iicbus_softc *sc = IICBUS_SOFTC(dev); /* * If the frequency has not been configured for the bus, or the request * is specifically for SLOW speed, use the standard 100KHz rate, else * use the configured bus speed. */ if (sc->bus_freq == 0 || speed == IIC_SLOW) return (100000); return (sc->bus_freq); } static device_method_t iicbus_methods[] = { /* device interface */ DEVMETHOD(device_probe, iicbus_probe), DEVMETHOD(device_attach, iicbus_attach), DEVMETHOD(device_detach, iicbus_detach), + DEVMETHOD(device_suspend, bus_generic_suspend), + DEVMETHOD(device_resume, bus_generic_resume), /* bus interface */ DEVMETHOD(bus_setup_intr, bus_generic_setup_intr), DEVMETHOD(bus_teardown_intr, bus_generic_teardown_intr), DEVMETHOD(bus_activate_resource, bus_generic_activate_resource), DEVMETHOD(bus_deactivate_resource, bus_generic_deactivate_resource), DEVMETHOD(bus_adjust_resource, bus_generic_adjust_resource), DEVMETHOD(bus_alloc_resource, bus_generic_rl_alloc_resource), DEVMETHOD(bus_get_resource, bus_generic_rl_get_resource), DEVMETHOD(bus_release_resource, bus_generic_rl_release_resource), DEVMETHOD(bus_set_resource, bus_generic_rl_set_resource), DEVMETHOD(bus_get_resource_list, iicbus_get_resource_list), DEVMETHOD(bus_add_child, iicbus_add_child), DEVMETHOD(bus_print_child, iicbus_print_child), DEVMETHOD(bus_probe_nomatch, iicbus_probe_nomatch), DEVMETHOD(bus_read_ivar, iicbus_read_ivar), DEVMETHOD(bus_write_ivar, iicbus_write_ivar), DEVMETHOD(bus_child_pnpinfo_str, iicbus_child_pnpinfo_str), DEVMETHOD(bus_child_location_str, iicbus_child_location_str), DEVMETHOD(bus_hinted_child, iicbus_hinted_child), /* iicbus interface */ DEVMETHOD(iicbus_transfer, iicbus_transfer), DEVMETHOD(iicbus_get_frequency, iicbus_get_frequency), DEVMETHOD_END }; driver_t iicbus_driver = { "iicbus", iicbus_methods, sizeof(struct iicbus_softc), }; devclass_t iicbus_devclass; MODULE_VERSION(iicbus, IICBUS_MODVER); DRIVER_MODULE(iicbus, iichb, iicbus_driver, iicbus_devclass, 0, 0);