Index: head/sys/arm64/arm64/db_trace.c
===================================================================
--- head/sys/arm64/arm64/db_trace.c (revision 354174)
+++ head/sys/arm64/arm64/db_trace.c (revision 354175)
@@ -1,133 +1,133 @@
/*-
* Copyright (c) 2015 The FreeBSD Foundation
* All rights reserved.
*
* This software was developed by Semihalf under
* the sponsorship of the FreeBSD Foundation.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*/
#include "opt_ddb.h"
#include <sys/cdefs.h>
__FBSDID("$FreeBSD$");
#include <sys/param.h>
#include <sys/proc.h>
#include <sys/kdb.h>
+
#include <machine/pcb.h>
#include <ddb/ddb.h>
#include <ddb/db_sym.h>
#include <machine/armreg.h>
#include <machine/debug_monitor.h>
#include <machine/stack.h>
void
db_md_list_watchpoints()
{
dbg_show_watchpoint();
}
int
db_md_clr_watchpoint(db_expr_t addr, db_expr_t size)
{
- return (dbg_remove_watchpoint(addr, size, DBG_FROM_EL1));
+ return (dbg_remove_watchpoint(NULL, addr, size));
}
int
db_md_set_watchpoint(db_expr_t addr, db_expr_t size)
{
- return (dbg_setup_watchpoint(addr, size, DBG_FROM_EL1,
- HW_BREAKPOINT_RW));
+ return (dbg_setup_watchpoint(NULL, addr, size, HW_BREAKPOINT_RW));
}
static void
db_stack_trace_cmd(struct unwind_state *frame)
{
c_db_sym_t sym;
const char *name;
db_expr_t value;
db_expr_t offset;
while (1) {
uint64_t pc = frame->pc;
int ret;
ret = unwind_frame(frame);
if (ret < 0)
break;
sym = db_search_symbol(pc, DB_STGY_ANY, &offset);
if (sym == C_DB_SYM_NULL) {
value = 0;
name = "(null)";
} else
db_symbol_values(sym, &name, &value);
db_printf("%s() at ", name);
db_printsym(frame->pc, DB_STGY_PROC);
db_printf("\n");
db_printf("\t pc = 0x%016lx lr = 0x%016lx\n", pc,
frame->pc);
db_printf("\t sp = 0x%016lx fp = 0x%016lx\n", frame->sp,
frame->fp);
/* TODO: Show some more registers */
db_printf("\n");
}
}
int
db_trace_thread(struct thread *thr, int count)
{
struct unwind_state frame;
struct pcb *ctx;
if (thr != curthread) {
ctx = kdb_thr_ctx(thr);
frame.sp = (uint64_t)ctx->pcb_sp;
frame.fp = (uint64_t)ctx->pcb_x[29];
frame.pc = (uint64_t)ctx->pcb_x[30];
db_stack_trace_cmd(&frame);
} else
db_trace_self();
return (0);
}
void
db_trace_self(void)
{
struct unwind_state frame;
uint64_t sp;
__asm __volatile("mov %0, sp" : "=&r" (sp));
frame.sp = sp;
frame.fp = (uint64_t)__builtin_frame_address(0);
frame.pc = (uint64_t)db_trace_self;
db_stack_trace_cmd(&frame);
}
Index: head/sys/arm64/arm64/debug_monitor.c
===================================================================
--- head/sys/arm64/arm64/debug_monitor.c (revision 354174)
+++ head/sys/arm64/arm64/debug_monitor.c (revision 354175)
@@ -1,485 +1,499 @@
/*-
* Copyright (c) 2014 The FreeBSD Foundation
* All rights reserved.
*
* This software was developed by Semihalf under
* the sponsorship of the FreeBSD Foundation.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*/
#include "opt_ddb.h"
#include <sys/cdefs.h>
__FBSDID("$FreeBSD$");
#include <sys/param.h>
#include <sys/types.h>
#include <sys/kdb.h>
#include <sys/pcpu.h>
#include <sys/systm.h>
#include <machine/armreg.h>
#include <machine/cpu.h>
#include <machine/debug_monitor.h>
#include <machine/kdb.h>
+#ifdef DDB
#include <ddb/ddb.h>
#include <ddb/db_sym.h>
+#endif
enum dbg_t {
DBG_TYPE_BREAKPOINT = 0,
DBG_TYPE_WATCHPOINT = 1,
};
static int dbg_watchpoint_num;
static int dbg_breakpoint_num;
-static int dbg_ref_count_mde[MAXCPU];
-static int dbg_ref_count_kde[MAXCPU];
+static struct debug_monitor_state kernel_monitor = {
+ .dbg_flags = DBGMON_KERNEL
+};
/* Watchpoints/breakpoints control register bitfields */
#define DBG_WATCH_CTRL_LEN_1 (0x1 << 5)
#define DBG_WATCH_CTRL_LEN_2 (0x3 << 5)
#define DBG_WATCH_CTRL_LEN_4 (0xf << 5)
#define DBG_WATCH_CTRL_LEN_8 (0xff << 5)
#define DBG_WATCH_CTRL_LEN_MASK(x) ((x) & (0xff << 5))
#define DBG_WATCH_CTRL_EXEC (0x0 << 3)
#define DBG_WATCH_CTRL_LOAD (0x1 << 3)
#define DBG_WATCH_CTRL_STORE (0x2 << 3)
#define DBG_WATCH_CTRL_ACCESS_MASK(x) ((x) & (0x3 << 3))
/* Common for breakpoint and watchpoint */
#define DBG_WB_CTRL_EL1 (0x1 << 1)
#define DBG_WB_CTRL_EL0 (0x2 << 1)
#define DBG_WB_CTRL_ELX_MASK(x) ((x) & (0x3 << 1))
#define DBG_WB_CTRL_E (0x1 << 0)
#define DBG_REG_BASE_BVR 0
#define DBG_REG_BASE_BCR (DBG_REG_BASE_BVR + 16)
#define DBG_REG_BASE_WVR (DBG_REG_BASE_BCR + 16)
#define DBG_REG_BASE_WCR (DBG_REG_BASE_WVR + 16)
/* Watchpoint/breakpoint helpers */
#define DBG_WB_WVR "wvr"
#define DBG_WB_WCR "wcr"
#define DBG_WB_BVR "bvr"
#define DBG_WB_BCR "bcr"
#define DBG_WB_READ(reg, num, val) do { \
__asm __volatile("mrs %0, dbg" reg #num "_el1" : "=r" (val)); \
} while (0)
#define DBG_WB_WRITE(reg, num, val) do { \
__asm __volatile("msr dbg" reg #num "_el1, %0" :: "r" (val)); \
} while (0)
#define READ_WB_REG_CASE(reg, num, offset, val) \
case (num + offset): \
DBG_WB_READ(reg, num, val); \
break
#define WRITE_WB_REG_CASE(reg, num, offset, val) \
case (num + offset): \
DBG_WB_WRITE(reg, num, val); \
break
#define SWITCH_CASES_READ_WB_REG(reg, offset, val) \
READ_WB_REG_CASE(reg, 0, offset, val); \
READ_WB_REG_CASE(reg, 1, offset, val); \
READ_WB_REG_CASE(reg, 2, offset, val); \
READ_WB_REG_CASE(reg, 3, offset, val); \
READ_WB_REG_CASE(reg, 4, offset, val); \
READ_WB_REG_CASE(reg, 5, offset, val); \
READ_WB_REG_CASE(reg, 6, offset, val); \
READ_WB_REG_CASE(reg, 7, offset, val); \
READ_WB_REG_CASE(reg, 8, offset, val); \
READ_WB_REG_CASE(reg, 9, offset, val); \
READ_WB_REG_CASE(reg, 10, offset, val); \
READ_WB_REG_CASE(reg, 11, offset, val); \
READ_WB_REG_CASE(reg, 12, offset, val); \
READ_WB_REG_CASE(reg, 13, offset, val); \
READ_WB_REG_CASE(reg, 14, offset, val); \
READ_WB_REG_CASE(reg, 15, offset, val)
#define SWITCH_CASES_WRITE_WB_REG(reg, offset, val) \
WRITE_WB_REG_CASE(reg, 0, offset, val); \
WRITE_WB_REG_CASE(reg, 1, offset, val); \
WRITE_WB_REG_CASE(reg, 2, offset, val); \
WRITE_WB_REG_CASE(reg, 3, offset, val); \
WRITE_WB_REG_CASE(reg, 4, offset, val); \
WRITE_WB_REG_CASE(reg, 5, offset, val); \
WRITE_WB_REG_CASE(reg, 6, offset, val); \
WRITE_WB_REG_CASE(reg, 7, offset, val); \
WRITE_WB_REG_CASE(reg, 8, offset, val); \
WRITE_WB_REG_CASE(reg, 9, offset, val); \
WRITE_WB_REG_CASE(reg, 10, offset, val); \
WRITE_WB_REG_CASE(reg, 11, offset, val); \
WRITE_WB_REG_CASE(reg, 12, offset, val); \
WRITE_WB_REG_CASE(reg, 13, offset, val); \
WRITE_WB_REG_CASE(reg, 14, offset, val); \
WRITE_WB_REG_CASE(reg, 15, offset, val)
+#ifdef DDB
static uint64_t
dbg_wb_read_reg(int reg, int n)
{
uint64_t val = 0;
switch (reg + n) {
SWITCH_CASES_READ_WB_REG(DBG_WB_WVR, DBG_REG_BASE_WVR, val);
SWITCH_CASES_READ_WB_REG(DBG_WB_WCR, DBG_REG_BASE_WCR, val);
SWITCH_CASES_READ_WB_REG(DBG_WB_BVR, DBG_REG_BASE_BVR, val);
SWITCH_CASES_READ_WB_REG(DBG_WB_BCR, DBG_REG_BASE_BCR, val);
default:
- db_printf("trying to read from wrong debug register %d\n", n);
+ printf("trying to read from wrong debug register %d\n", n);
}
return val;
}
+#endif /* DDB */
static void
dbg_wb_write_reg(int reg, int n, uint64_t val)
{
switch (reg + n) {
SWITCH_CASES_WRITE_WB_REG(DBG_WB_WVR, DBG_REG_BASE_WVR, val);
SWITCH_CASES_WRITE_WB_REG(DBG_WB_WCR, DBG_REG_BASE_WCR, val);
SWITCH_CASES_WRITE_WB_REG(DBG_WB_BVR, DBG_REG_BASE_BVR, val);
SWITCH_CASES_WRITE_WB_REG(DBG_WB_BCR, DBG_REG_BASE_BCR, val);
default:
- db_printf("trying to write to wrong debug register %d\n", n);
+ printf("trying to write to wrong debug register %d\n", n);
+ return;
}
isb();
}
+#ifdef DDB
void
kdb_cpu_set_singlestep(void)
{
kdb_frame->tf_spsr |= DBG_SPSR_SS;
- WRITE_SPECIALREG(MDSCR_EL1, READ_SPECIALREG(MDSCR_EL1) |
+ WRITE_SPECIALREG(mdscr_el1, READ_SPECIALREG(mdscr_el1) |
DBG_MDSCR_SS | DBG_MDSCR_KDE);
/*
* Disable breakpoints and watchpoints, e.g. stepping
* over watched instruction will trigger break exception instead of
* single-step exception and locks CPU on that instruction for ever.
*/
- if (dbg_ref_count_mde[PCPU_GET(cpuid)] > 0) {
- WRITE_SPECIALREG(MDSCR_EL1,
- READ_SPECIALREG(MDSCR_EL1) & ~DBG_MDSCR_MDE);
+ if ((kernel_monitor.dbg_flags & DBGMON_ENABLED) != 0) {
+ WRITE_SPECIALREG(mdscr_el1,
+ READ_SPECIALREG(mdscr_el1) & ~DBG_MDSCR_MDE);
}
}
void
kdb_cpu_clear_singlestep(void)
{
- WRITE_SPECIALREG(MDSCR_EL1, READ_SPECIALREG(MDSCR_EL1) &
+ WRITE_SPECIALREG(mdscr_el1, READ_SPECIALREG(mdscr_el1) &
~(DBG_MDSCR_SS | DBG_MDSCR_KDE));
/* Restore breakpoints and watchpoints */
- if (dbg_ref_count_mde[PCPU_GET(cpuid)] > 0) {
- WRITE_SPECIALREG(MDSCR_EL1,
- READ_SPECIALREG(MDSCR_EL1) | DBG_MDSCR_MDE);
- }
+ if ((kernel_monitor.dbg_flags & DBGMON_ENABLED) != 0) {
+ WRITE_SPECIALREG(mdscr_el1,
+ READ_SPECIALREG(mdscr_el1) | DBG_MDSCR_MDE);
- if (dbg_ref_count_kde[PCPU_GET(cpuid)] > 0) {
- WRITE_SPECIALREG(MDSCR_EL1,
- READ_SPECIALREG(MDSCR_EL1) | DBG_MDSCR_KDE);
+ if ((kernel_monitor.dbg_flags & DBGMON_KERNEL) != 0) {
+ WRITE_SPECIALREG(mdscr_el1,
+ READ_SPECIALREG(mdscr_el1) | DBG_MDSCR_KDE);
+ }
}
}
static const char *
dbg_watchtype_str(uint32_t type)
{
switch (type) {
case DBG_WATCH_CTRL_EXEC:
return ("execute");
case DBG_WATCH_CTRL_STORE:
return ("write");
case DBG_WATCH_CTRL_LOAD:
return ("read");
case DBG_WATCH_CTRL_LOAD | DBG_WATCH_CTRL_STORE:
return ("read/write");
default:
return ("invalid");
}
}
static int
dbg_watchtype_len(uint32_t len)
{
switch (len) {
case DBG_WATCH_CTRL_LEN_1:
return (1);
case DBG_WATCH_CTRL_LEN_2:
return (2);
case DBG_WATCH_CTRL_LEN_4:
return (4);
case DBG_WATCH_CTRL_LEN_8:
return (8);
default:
return (0);
}
}
void
dbg_show_watchpoint(void)
{
uint32_t wcr, len, type;
uint64_t addr;
int i;
db_printf("\nhardware watchpoints:\n");
db_printf(" watch status type len address symbol\n");
db_printf(" ----- -------- ---------- --- ------------------ ------------------\n");
for (i = 0; i < dbg_watchpoint_num; i++) {
wcr = dbg_wb_read_reg(DBG_REG_BASE_WCR, i);
if ((wcr & DBG_WB_CTRL_E) != 0) {
type = DBG_WATCH_CTRL_ACCESS_MASK(wcr);
len = DBG_WATCH_CTRL_LEN_MASK(wcr);
addr = dbg_wb_read_reg(DBG_REG_BASE_WVR, i);
db_printf(" %-5d %-8s %10s %3d 0x%16lx ",
i, "enabled", dbg_watchtype_str(type),
dbg_watchtype_len(len), addr);
db_printsym((db_addr_t)addr, DB_STGY_ANY);
db_printf("\n");
} else {
db_printf(" %-5d disabled\n", i);
}
}
}
+#endif /* DDB */
-
static int
-dbg_find_free_slot(enum dbg_t type)
+dbg_find_free_slot(struct debug_monitor_state *monitor, enum dbg_t type)
{
- u_int max, reg, i;
+ uint64_t *reg;
+ u_int max, i;
switch(type) {
case DBG_TYPE_BREAKPOINT:
max = dbg_breakpoint_num;
- reg = DBG_REG_BASE_BCR;
-
+ reg = monitor->dbg_bcr;
break;
case DBG_TYPE_WATCHPOINT:
max = dbg_watchpoint_num;
- reg = DBG_REG_BASE_WCR;
+ reg = monitor->dbg_wcr;
break;
default:
- db_printf("Unsupported debug type\n");
+ printf("Unsupported debug type\n");
return (i);
}
for (i = 0; i < max; i++) {
- if ((dbg_wb_read_reg(reg, i) & DBG_WB_CTRL_E) == 0)
+ if ((reg[i] & DBG_WB_CTRL_E) == 0)
return (i);
}
return (-1);
}
static int
-dbg_find_slot(enum dbg_t type, db_expr_t addr)
+dbg_find_slot(struct debug_monitor_state *monitor, enum dbg_t type,
+ vm_offset_t addr)
{
- u_int max, reg_addr, reg_ctrl, i;
+ uint64_t *reg_addr, *reg_ctrl;
+ u_int max, i;
switch(type) {
case DBG_TYPE_BREAKPOINT:
max = dbg_breakpoint_num;
- reg_addr = DBG_REG_BASE_BVR;
- reg_ctrl = DBG_REG_BASE_BCR;
+ reg_addr = monitor->dbg_bvr;
+ reg_ctrl = monitor->dbg_bcr;
break;
case DBG_TYPE_WATCHPOINT:
max = dbg_watchpoint_num;
- reg_addr = DBG_REG_BASE_WVR;
- reg_ctrl = DBG_REG_BASE_WCR;
+ reg_addr = monitor->dbg_wvr;
+ reg_ctrl = monitor->dbg_wcr;
break;
default:
- db_printf("Unsupported debug type\n");
+ printf("Unsupported debug type\n");
return (i);
}
for (i = 0; i < max; i++) {
- if ((dbg_wb_read_reg(reg_addr, i) == addr) &&
- ((dbg_wb_read_reg(reg_ctrl, i) & DBG_WB_CTRL_E) != 0))
+ if (reg_addr[i] == addr &&
+ (reg_ctrl[i] & DBG_WB_CTRL_E) != 0)
return (i);
}
return (-1);
}
-static void
-dbg_enable_monitor(enum dbg_el_t el)
-{
- uint64_t reg_mdcr = 0;
-
- /*
- * There is no need to have debug monitor on permanently, thus we are
- * refcounting and turn it on only if any of CPU is going to use that.
- */
- if (atomic_fetchadd_int(&dbg_ref_count_mde[PCPU_GET(cpuid)], 1) == 0)
- reg_mdcr = DBG_MDSCR_MDE;
-
- if ((el == DBG_FROM_EL1) &&
- atomic_fetchadd_int(&dbg_ref_count_kde[PCPU_GET(cpuid)], 1) == 0)
- reg_mdcr |= DBG_MDSCR_KDE;
-
- if (reg_mdcr)
- WRITE_SPECIALREG(MDSCR_EL1, READ_SPECIALREG(MDSCR_EL1) | reg_mdcr);
-}
-
-static void
-dbg_disable_monitor(enum dbg_el_t el)
-{
- uint64_t reg_mdcr = 0;
-
- if (atomic_fetchadd_int(&dbg_ref_count_mde[PCPU_GET(cpuid)], -1) == 1)
- reg_mdcr = DBG_MDSCR_MDE;
-
- if ((el == DBG_FROM_EL1) &&
- atomic_fetchadd_int(&dbg_ref_count_kde[PCPU_GET(cpuid)], -1) == 1)
- reg_mdcr |= DBG_MDSCR_KDE;
-
- if (reg_mdcr)
- WRITE_SPECIALREG(MDSCR_EL1, READ_SPECIALREG(MDSCR_EL1) & ~reg_mdcr);
-}
-
int
-dbg_setup_watchpoint(db_expr_t addr, db_expr_t size, enum dbg_el_t el,
- enum dbg_access_t access)
+dbg_setup_watchpoint(struct debug_monitor_state *monitor, vm_offset_t addr,
+ vm_size_t size, enum dbg_access_t access)
{
uint64_t wcr_size, wcr_priv, wcr_access;
u_int i;
- i = dbg_find_free_slot(DBG_TYPE_WATCHPOINT);
+ if (monitor == NULL)
+ monitor = &kernel_monitor;
+
+ i = dbg_find_free_slot(monitor, DBG_TYPE_WATCHPOINT);
if (i == -1) {
- db_printf("Can not find slot for watchpoint, max %d"
+ printf("Can not find slot for watchpoint, max %d"
" watchpoints supported\n", dbg_watchpoint_num);
return (i);
}
switch(size) {
case 1:
wcr_size = DBG_WATCH_CTRL_LEN_1;
break;
case 2:
wcr_size = DBG_WATCH_CTRL_LEN_2;
break;
case 4:
wcr_size = DBG_WATCH_CTRL_LEN_4;
break;
case 8:
wcr_size = DBG_WATCH_CTRL_LEN_8;
break;
default:
- db_printf("Unsupported address size for watchpoint\n");
+ printf("Unsupported address size for watchpoint\n");
return (-1);
}
- switch(el) {
- case DBG_FROM_EL0:
+ if ((monitor->dbg_flags & DBGMON_KERNEL) == 0)
wcr_priv = DBG_WB_CTRL_EL0;
- break;
- case DBG_FROM_EL1:
+ else
wcr_priv = DBG_WB_CTRL_EL1;
- break;
- default:
- db_printf("Unsupported exception level for watchpoint\n");
- return (-1);
- }
switch(access) {
case HW_BREAKPOINT_X:
wcr_access = DBG_WATCH_CTRL_EXEC;
break;
case HW_BREAKPOINT_R:
wcr_access = DBG_WATCH_CTRL_LOAD;
break;
case HW_BREAKPOINT_W:
wcr_access = DBG_WATCH_CTRL_STORE;
break;
case HW_BREAKPOINT_RW:
wcr_access = DBG_WATCH_CTRL_LOAD | DBG_WATCH_CTRL_STORE;
break;
default:
- db_printf("Unsupported exception level for watchpoint\n");
+ printf("Unsupported exception level for watchpoint\n");
return (-1);
}
- dbg_wb_write_reg(DBG_REG_BASE_WVR, i, addr);
- dbg_wb_write_reg(DBG_REG_BASE_WCR, i, wcr_size | wcr_access | wcr_priv |
- DBG_WB_CTRL_E);
- dbg_enable_monitor(el);
+ monitor->dbg_wvr[i] = addr;
+ monitor->dbg_wcr[i] = wcr_size | wcr_access | wcr_priv | DBG_WB_CTRL_E;
+ monitor->dbg_enable_count++;
+ monitor->dbg_flags |= DBGMON_ENABLED;
+
+ dbg_register_sync(monitor);
return (0);
}
int
-dbg_remove_watchpoint(db_expr_t addr, db_expr_t size, enum dbg_el_t el)
+dbg_remove_watchpoint(struct debug_monitor_state *monitor, vm_offset_t addr,
+ vm_size_t size)
{
u_int i;
- i = dbg_find_slot(DBG_TYPE_WATCHPOINT, addr);
+ if (monitor == NULL)
+ monitor = &kernel_monitor;
+
+ i = dbg_find_slot(monitor, DBG_TYPE_WATCHPOINT, addr);
if (i == -1) {
- db_printf("Can not find watchpoint for address 0%lx\n", addr);
+ printf("Can not find watchpoint for address 0%lx\n", addr);
return (i);
}
- dbg_wb_write_reg(DBG_REG_BASE_WCR, i, 0);
- dbg_disable_monitor(el);
+ monitor->dbg_wvr[i] = 0;
+ monitor->dbg_wcr[i] = 0;
+ monitor->dbg_enable_count--;
+ if (monitor->dbg_enable_count == 0)
+ monitor->dbg_flags &= ~DBGMON_ENABLED;
+
+ dbg_register_sync(monitor);
return (0);
}
void
+dbg_register_sync(struct debug_monitor_state *monitor)
+{
+ uint64_t mdscr;
+ int i;
+
+ if (monitor == NULL)
+ monitor = &kernel_monitor;
+
+ mdscr = READ_SPECIALREG(mdscr_el1);
+ if ((monitor->dbg_flags & DBGMON_ENABLED) == 0) {
+ mdscr &= ~(DBG_MDSCR_MDE | DBG_MDSCR_KDE);
+ } else {
+ for (i = 0; i < dbg_breakpoint_num; i++) {
+ dbg_wb_write_reg(DBG_REG_BASE_BCR, i,
+ monitor->dbg_bcr[i]);
+ dbg_wb_write_reg(DBG_REG_BASE_BVR, i,
+ monitor->dbg_bvr[i]);
+ }
+
+ for (i = 0; i < dbg_watchpoint_num; i++) {
+ dbg_wb_write_reg(DBG_REG_BASE_WCR, i,
+ monitor->dbg_wcr[i]);
+ dbg_wb_write_reg(DBG_REG_BASE_WVR, i,
+ monitor->dbg_wvr[i]);
+ }
+ mdscr |= DBG_MDSCR_MDE;
+ if ((monitor->dbg_flags & DBGMON_KERNEL) == DBGMON_KERNEL)
+ mdscr |= DBG_MDSCR_KDE;
+ }
+ WRITE_SPECIALREG(mdscr_el1, mdscr);
+ isb();
+}
+
+void
dbg_monitor_init(void)
{
u_int i;
/* Find out many breakpoints and watchpoints we can use */
dbg_watchpoint_num = ((READ_SPECIALREG(ID_AA64DFR0_EL1) >> 20) & 0xf) + 1;
dbg_breakpoint_num = ((READ_SPECIALREG(ID_AA64DFR0_EL1) >> 12) & 0xf) + 1;
if (bootverbose && PCPU_GET(cpuid) == 0) {
printf("%d watchpoints and %d breakpoints supported\n",
dbg_watchpoint_num, dbg_breakpoint_num);
}
/*
* We have limited number of {watch,break}points, each consists of
* two registers:
* - wcr/bcr regsiter configurates corresponding {watch,break}point
* behaviour
* - wvr/bvr register keeps address we are hunting for
*
* Reset all breakpoints and watchpoints.
*/
- for (i = 0; i < dbg_watchpoint_num; ++i) {
+ for (i = 0; i < dbg_watchpoint_num; i++) {
dbg_wb_write_reg(DBG_REG_BASE_WCR, i, 0);
dbg_wb_write_reg(DBG_REG_BASE_WVR, i, 0);
}
- for (i = 0; i < dbg_breakpoint_num; ++i) {
+ for (i = 0; i < dbg_breakpoint_num; i++) {
dbg_wb_write_reg(DBG_REG_BASE_BCR, i, 0);
dbg_wb_write_reg(DBG_REG_BASE_BVR, i, 0);
}
dbg_enable();
}
Index: head/sys/arm64/arm64/exception.S
===================================================================
--- head/sys/arm64/arm64/exception.S (revision 354174)
+++ head/sys/arm64/arm64/exception.S (revision 354175)
@@ -1,246 +1,248 @@
/*-
* Copyright (c) 2014 Andrew Turner
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*
*/
#include <machine/asm.h>
#include <machine/armreg.h>
__FBSDID("$FreeBSD$");
#include "assym.inc"
.text
.macro save_registers el
.if \el == 1
mov x18, sp
sub sp, sp, #128
.endif
sub sp, sp, #(TF_SIZE + 16)
stp x29, x30, [sp, #(TF_SIZE)]
stp x28, x29, [sp, #(TF_X + 28 * 8)]
stp x26, x27, [sp, #(TF_X + 26 * 8)]
stp x24, x25, [sp, #(TF_X + 24 * 8)]
stp x22, x23, [sp, #(TF_X + 22 * 8)]
stp x20, x21, [sp, #(TF_X + 20 * 8)]
stp x18, x19, [sp, #(TF_X + 18 * 8)]
stp x16, x17, [sp, #(TF_X + 16 * 8)]
stp x14, x15, [sp, #(TF_X + 14 * 8)]
stp x12, x13, [sp, #(TF_X + 12 * 8)]
stp x10, x11, [sp, #(TF_X + 10 * 8)]
stp x8, x9, [sp, #(TF_X + 8 * 8)]
stp x6, x7, [sp, #(TF_X + 6 * 8)]
stp x4, x5, [sp, #(TF_X + 4 * 8)]
stp x2, x3, [sp, #(TF_X + 2 * 8)]
stp x0, x1, [sp, #(TF_X + 0 * 8)]
mrs x10, elr_el1
mrs x11, spsr_el1
mrs x12, esr_el1
.if \el == 0
mrs x18, sp_el0
.endif
str x10, [sp, #(TF_ELR)]
stp w11, w12, [sp, #(TF_SPSR)]
stp x18, lr, [sp, #(TF_SP)]
mrs x18, tpidr_el1
add x29, sp, #(TF_SIZE)
.if \el == 0
/* Apply the SSBD (CVE-2018-3639) workaround if needed */
ldr x1, [x18, #PC_SSBD]
cbz x1, 1f
mov w0, #1
blr x1
1:
.endif
+ msr daifclr, #8 /* Enable the debug exception */
.endm
.macro restore_registers el
.if \el == 1
- msr daifset, #2
/*
- * Disable interrupts, x18 may change in the interrupt exception
- * handler. For EL0 exceptions, do_ast already did this.
+ * Disable interrupts and debug exceptions, x18 may change in the
+ * interrupt exception handler. For EL0 exceptions, do_ast already
+ * did this.
*/
+ msr daifset, #10
.endif
.if \el == 0
/* Remove the SSBD (CVE-2018-3639) workaround if needed */
ldr x1, [x18, #PC_SSBD]
cbz x1, 1f
mov w0, #0
blr x1
1:
.endif
ldp x18, lr, [sp, #(TF_SP)]
ldp x10, x11, [sp, #(TF_ELR)]
.if \el == 0
msr sp_el0, x18
.endif
msr spsr_el1, x11
msr elr_el1, x10
ldp x0, x1, [sp, #(TF_X + 0 * 8)]
ldp x2, x3, [sp, #(TF_X + 2 * 8)]
ldp x4, x5, [sp, #(TF_X + 4 * 8)]
ldp x6, x7, [sp, #(TF_X + 6 * 8)]
ldp x8, x9, [sp, #(TF_X + 8 * 8)]
ldp x10, x11, [sp, #(TF_X + 10 * 8)]
ldp x12, x13, [sp, #(TF_X + 12 * 8)]
ldp x14, x15, [sp, #(TF_X + 14 * 8)]
ldp x16, x17, [sp, #(TF_X + 16 * 8)]
.if \el == 0
/*
* We only restore the callee saved registers when returning to
* userland as they may have been updated by a system call or signal.
*/
ldp x18, x19, [sp, #(TF_X + 18 * 8)]
ldp x20, x21, [sp, #(TF_X + 20 * 8)]
ldp x22, x23, [sp, #(TF_X + 22 * 8)]
ldp x24, x25, [sp, #(TF_X + 24 * 8)]
ldp x26, x27, [sp, #(TF_X + 26 * 8)]
ldp x28, x29, [sp, #(TF_X + 28 * 8)]
.else
ldr x29, [sp, #(TF_X + 29 * 8)]
.endif
.if \el == 0
add sp, sp, #(TF_SIZE + 16)
.else
mov sp, x18
mrs x18, tpidr_el1
.endif
.endm
.macro do_ast
mrs x19, daif
/* Make sure the IRQs are enabled before calling ast() */
bic x19, x19, #PSR_I
1:
/* Disable interrupts */
- msr daifset, #2
+ msr daifset, #10
/* Read the current thread flags */
ldr x1, [x18, #PC_CURTHREAD] /* Load curthread */
ldr x2, [x1, #TD_FLAGS]
/* Check if we have either bits set */
mov x3, #((TDF_ASTPENDING|TDF_NEEDRESCHED) >> 8)
lsl x3, x3, #8
and x2, x2, x3
cbz x2, 2f
/* Restore interrupts */
msr daif, x19
/* handle the ast */
mov x0, sp
bl _C_LABEL(ast)
/* Re-check for new ast scheduled */
b 1b
2:
.endm
ENTRY(handle_el1h_sync)
save_registers 1
ldr x0, [x18, #PC_CURTHREAD]
mov x1, sp
bl do_el1h_sync
restore_registers 1
eret
END(handle_el1h_sync)
ENTRY(handle_el1h_irq)
save_registers 1
mov x0, sp
bl intr_irq_handler
restore_registers 1
eret
END(handle_el1h_irq)
ENTRY(handle_el0_sync)
save_registers 0
ldr x0, [x18, #PC_CURTHREAD]
mov x1, sp
str x1, [x0, #TD_FRAME]
bl do_el0_sync
do_ast
restore_registers 0
eret
END(handle_el0_sync)
ENTRY(handle_el0_irq)
save_registers 0
mov x0, sp
bl intr_irq_handler
do_ast
restore_registers 0
eret
END(handle_el0_irq)
ENTRY(handle_serror)
save_registers 0
mov x0, sp
1: bl do_serror
b 1b
END(handle_serror)
ENTRY(handle_empty_exception)
save_registers 0
mov x0, sp
1: bl unhandled_exception
b 1b
END(handle_unhandled_exception)
.macro vempty
.align 7
b handle_empty_exception
.endm
.macro vector name
.align 7
b handle_\name
.endm
.align 11
.globl exception_vectors
exception_vectors:
vempty /* Synchronous EL1t */
vempty /* IRQ EL1t */
vempty /* FIQ EL1t */
vempty /* Error EL1t */
vector el1h_sync /* Synchronous EL1h */
vector el1h_irq /* IRQ EL1h */
vempty /* FIQ EL1h */
vector serror /* Error EL1h */
vector el0_sync /* Synchronous 64-bit EL0 */
vector el0_irq /* IRQ 64-bit EL0 */
vempty /* FIQ 64-bit EL0 */
vector serror /* Error 64-bit EL0 */
vector el0_sync /* Synchronous 32-bit EL0 */
vector el0_irq /* IRQ 32-bit EL0 */
vempty /* FIQ 32-bit EL0 */
vector serror /* Error 32-bit EL0 */
Index: head/sys/arm64/arm64/mp_machdep.c
===================================================================
--- head/sys/arm64/arm64/mp_machdep.c (revision 354174)
+++ head/sys/arm64/arm64/mp_machdep.c (revision 354175)
@@ -1,829 +1,835 @@
/*-
* Copyright (c) 2015-2016 The FreeBSD Foundation
* All rights reserved.
*
* This software was developed by Andrew Turner under
* sponsorship from the FreeBSD Foundation.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*
*/
#include "opt_acpi.h"
+#include "opt_ddb.h"
#include "opt_kstack_pages.h"
#include "opt_platform.h"
#include <sys/cdefs.h>
__FBSDID("$FreeBSD$");
#include <sys/param.h>
#include <sys/systm.h>
#include <sys/bus.h>
#include <sys/cpu.h>
#include <sys/kernel.h>
#include <sys/ktr.h>
#include <sys/malloc.h>
#include <sys/module.h>
#include <sys/mutex.h>
#include <sys/pcpu.h>
#include <sys/proc.h>
#include <sys/sched.h>
#include <sys/smp.h>
#include <vm/vm.h>
#include <vm/pmap.h>
#include <vm/vm_extern.h>
#include <vm/vm_kern.h>
#include <machine/machdep.h>
+#include <machine/debug_monitor.h>
#include <machine/intr.h>
#include <machine/smp.h>
#ifdef VFP
#include <machine/vfp.h>
#endif
#ifdef DEV_ACPI
#include <contrib/dev/acpica/include/acpi.h>
#include <dev/acpica/acpivar.h>
#endif
#ifdef FDT
#include <dev/ofw/openfirm.h>
#include <dev/ofw/ofw_bus.h>
#include <dev/ofw/ofw_bus_subr.h>
#include <dev/ofw/ofw_cpu.h>
#endif
#include <dev/psci/psci.h>
#include "pic_if.h"
#define MP_QUIRK_CPULIST 0x01 /* The list of cpus may be wrong, */
/* don't panic if one fails to start */
static uint32_t mp_quirks;
#ifdef FDT
static struct {
const char *compat;
uint32_t quirks;
} fdt_quirks[] = {
{ "arm,foundation-aarch64", MP_QUIRK_CPULIST },
{ "arm,fvp-base", MP_QUIRK_CPULIST },
/* This is incorrect in some DTS files */
{ "arm,vfp-base", MP_QUIRK_CPULIST },
{ NULL, 0 },
};
#endif
typedef void intr_ipi_send_t(void *, cpuset_t, u_int);
typedef void intr_ipi_handler_t(void *);
#define INTR_IPI_NAMELEN (MAXCOMLEN + 1)
struct intr_ipi {
intr_ipi_handler_t * ii_handler;
void * ii_handler_arg;
intr_ipi_send_t * ii_send;
void * ii_send_arg;
char ii_name[INTR_IPI_NAMELEN];
u_long * ii_count;
};
static struct intr_ipi ipi_sources[INTR_IPI_COUNT];
static struct intr_ipi *intr_ipi_lookup(u_int);
static void intr_pic_ipi_setup(u_int, const char *, intr_ipi_handler_t *,
void *);
static void ipi_ast(void *);
static void ipi_hardclock(void *);
static void ipi_preempt(void *);
static void ipi_rendezvous(void *);
static void ipi_stop(void *);
struct mtx ap_boot_mtx;
struct pcb stoppcbs[MAXCPU];
/*
* Not all systems boot from the first CPU in the device tree. To work around
* this we need to find which CPU we have booted from so when we later
* enable the secondary CPUs we skip this one.
*/
static int cpu0 = -1;
void mpentry(unsigned long cpuid);
void init_secondary(uint64_t);
uint8_t secondary_stacks[MAXCPU - 1][PAGE_SIZE * KSTACK_PAGES] __aligned(16);
/* Set to 1 once we're ready to let the APs out of the pen. */
volatile int aps_ready = 0;
/* Temporary variables for init_secondary() */
void *dpcpu[MAXCPU - 1];
static void
release_aps(void *dummy __unused)
{
int i, started;
/* Only release CPUs if they exist */
if (mp_ncpus == 1)
return;
intr_pic_ipi_setup(IPI_AST, "ast", ipi_ast, NULL);
intr_pic_ipi_setup(IPI_PREEMPT, "preempt", ipi_preempt, NULL);
intr_pic_ipi_setup(IPI_RENDEZVOUS, "rendezvous", ipi_rendezvous, NULL);
intr_pic_ipi_setup(IPI_STOP, "stop", ipi_stop, NULL);
intr_pic_ipi_setup(IPI_STOP_HARD, "stop hard", ipi_stop, NULL);
intr_pic_ipi_setup(IPI_HARDCLOCK, "hardclock", ipi_hardclock, NULL);
atomic_store_rel_int(&aps_ready, 1);
/* Wake up the other CPUs */
__asm __volatile(
"dsb ishst \n"
"sev \n"
::: "memory");
printf("Release APs...");
started = 0;
for (i = 0; i < 2000; i++) {
if (smp_started) {
printf("done\n");
return;
}
/*
* Don't time out while we are making progress. Some large
* systems can take a while to start all CPUs.
*/
if (smp_cpus > started) {
i = 0;
started = smp_cpus;
}
DELAY(1000);
}
printf("APs not started\n");
}
SYSINIT(start_aps, SI_SUB_SMP, SI_ORDER_FIRST, release_aps, NULL);
void
init_secondary(uint64_t cpu)
{
struct pcpu *pcpup;
pcpup = &__pcpu[cpu];
/*
* Set the pcpu pointer with a backup in tpidr_el1 to be
* loaded when entering the kernel from userland.
*/
__asm __volatile(
"mov x18, %0 \n"
"msr tpidr_el1, %0" :: "r"(pcpup));
/* Spin until the BSP releases the APs */
while (!aps_ready)
__asm __volatile("wfe");
/* Initialize curthread */
KASSERT(PCPU_GET(idlethread) != NULL, ("no idle thread"));
pcpup->pc_curthread = pcpup->pc_idlethread;
pcpup->pc_curpcb = pcpup->pc_idlethread->td_pcb;
/*
* Identify current CPU. This is necessary to setup
* affinity registers and to provide support for
* runtime chip identification.
*/
identify_cpu();
install_cpu_errata();
intr_pic_init_secondary();
/* Start per-CPU event timers. */
cpu_initclocks_ap();
#ifdef VFP
vfp_init();
#endif
dbg_init();
pan_enable();
/* Enable interrupts */
intr_enable();
mtx_lock_spin(&ap_boot_mtx);
atomic_add_rel_32(&smp_cpus, 1);
if (smp_cpus == mp_ncpus) {
/* enable IPI's, tlb shootdown, freezes etc */
atomic_store_rel_int(&smp_started, 1);
}
mtx_unlock_spin(&ap_boot_mtx);
/* Enter the scheduler */
sched_throw(NULL);
panic("scheduler returned us to init_secondary");
/* NOTREACHED */
}
/*
* Send IPI thru interrupt controller.
*/
static void
pic_ipi_send(void *arg, cpuset_t cpus, u_int ipi)
{
KASSERT(intr_irq_root_dev != NULL, ("%s: no root attached", __func__));
PIC_IPI_SEND(intr_irq_root_dev, arg, cpus, ipi);
}
/*
* Setup IPI handler on interrupt controller.
*
* Not SMP coherent.
*/
static void
intr_pic_ipi_setup(u_int ipi, const char *name, intr_ipi_handler_t *hand,
void *arg)
{
struct intr_irqsrc *isrc;
struct intr_ipi *ii;
int error;
KASSERT(intr_irq_root_dev != NULL, ("%s: no root attached", __func__));
KASSERT(hand != NULL, ("%s: ipi %u no handler", __func__, ipi));
error = PIC_IPI_SETUP(intr_irq_root_dev, ipi, &isrc);
if (error != 0)
return;
isrc->isrc_handlers++;
ii = intr_ipi_lookup(ipi);
KASSERT(ii->ii_count == NULL, ("%s: ipi %u reused", __func__, ipi));
ii->ii_handler = hand;
ii->ii_handler_arg = arg;
ii->ii_send = pic_ipi_send;
ii->ii_send_arg = isrc;
strlcpy(ii->ii_name, name, INTR_IPI_NAMELEN);
ii->ii_count = intr_ipi_setup_counters(name);
}
static void
intr_ipi_send(cpuset_t cpus, u_int ipi)
{
struct intr_ipi *ii;
ii = intr_ipi_lookup(ipi);
if (ii->ii_count == NULL)
panic("%s: not setup IPI %u", __func__, ipi);
ii->ii_send(ii->ii_send_arg, cpus, ipi);
}
static void
ipi_ast(void *dummy __unused)
{
CTR0(KTR_SMP, "IPI_AST");
}
static void
ipi_hardclock(void *dummy __unused)
{
CTR1(KTR_SMP, "%s: IPI_HARDCLOCK", __func__);
hardclockintr();
}
static void
ipi_preempt(void *dummy __unused)
{
CTR1(KTR_SMP, "%s: IPI_PREEMPT", __func__);
sched_preempt(curthread);
}
static void
ipi_rendezvous(void *dummy __unused)
{
CTR0(KTR_SMP, "IPI_RENDEZVOUS");
smp_rendezvous_action();
}
static void
ipi_stop(void *dummy __unused)
{
u_int cpu;
CTR0(KTR_SMP, "IPI_STOP");
cpu = PCPU_GET(cpuid);
savectx(&stoppcbs[cpu]);
/* Indicate we are stopped */
CPU_SET_ATOMIC(cpu, &stopped_cpus);
/* Wait for restart */
while (!CPU_ISSET(cpu, &started_cpus))
cpu_spinwait();
+
+#ifdef DDB
+ dbg_register_sync(NULL);
+#endif
CPU_CLR_ATOMIC(cpu, &started_cpus);
CPU_CLR_ATOMIC(cpu, &stopped_cpus);
CTR0(KTR_SMP, "IPI_STOP (restart)");
}
struct cpu_group *
cpu_topo(void)
{
return (smp_topo_none());
}
/* Determine if we running MP machine */
int
cpu_mp_probe(void)
{
/* ARM64TODO: Read the u bit of mpidr_el1 to determine this */
return (1);
}
static bool
start_cpu(u_int id, uint64_t target_cpu)
{
struct pcpu *pcpup;
vm_paddr_t pa;
u_int cpuid;
int err;
/* Check we are able to start this cpu */
if (id > mp_maxid)
return (false);
KASSERT(id < MAXCPU, ("Too many CPUs"));
/* We are already running on cpu 0 */
if (id == cpu0)
return (true);
/*
* Rotate the CPU IDs to put the boot CPU as CPU 0. We keep the other
* CPUs ordered as the are likely grouped into clusters so it can be
* useful to keep that property, e.g. for the GICv3 driver to send
* an IPI to all CPUs in the cluster.
*/
cpuid = id;
if (cpuid < cpu0)
cpuid += mp_maxid + 1;
cpuid -= cpu0;
pcpup = &__pcpu[cpuid];
pcpu_init(pcpup, cpuid, sizeof(struct pcpu));
dpcpu[cpuid - 1] = (void *)kmem_malloc(DPCPU_SIZE, M_WAITOK | M_ZERO);
dpcpu_init(dpcpu[cpuid - 1], cpuid);
printf("Starting CPU %u (%lx)\n", cpuid, target_cpu);
pa = pmap_extract(kernel_pmap, (vm_offset_t)mpentry);
err = psci_cpu_on(target_cpu, pa, cpuid);
if (err != PSCI_RETVAL_SUCCESS) {
/*
* Panic here if INVARIANTS are enabled and PSCI failed to
* start the requested CPU. If psci_cpu_on returns PSCI_MISSING
* to indicate we are unable to use it to start the given CPU.
*/
KASSERT(err == PSCI_MISSING ||
(mp_quirks & MP_QUIRK_CPULIST) == MP_QUIRK_CPULIST,
("Failed to start CPU %u (%lx)\n", id, target_cpu));
pcpu_destroy(pcpup);
kmem_free((vm_offset_t)dpcpu[cpuid - 1], DPCPU_SIZE);
dpcpu[cpuid - 1] = NULL;
mp_ncpus--;
/* Notify the user that the CPU failed to start */
printf("Failed to start CPU %u (%lx)\n", id, target_cpu);
} else
CPU_SET(cpuid, &all_cpus);
return (true);
}
#ifdef DEV_ACPI
static void
madt_handler(ACPI_SUBTABLE_HEADER *entry, void *arg)
{
ACPI_MADT_GENERIC_INTERRUPT *intr;
u_int *cpuid;
u_int id;
switch(entry->Type) {
case ACPI_MADT_TYPE_GENERIC_INTERRUPT:
intr = (ACPI_MADT_GENERIC_INTERRUPT *)entry;
cpuid = arg;
id = *cpuid;
start_cpu(id, intr->ArmMpidr);
__pcpu[id].pc_acpi_id = intr->Uid;
(*cpuid)++;
break;
default:
break;
}
}
static void
cpu_init_acpi(void)
{
ACPI_TABLE_MADT *madt;
vm_paddr_t physaddr;
u_int cpuid;
physaddr = acpi_find_table(ACPI_SIG_MADT);
if (physaddr == 0)
return;
madt = acpi_map_table(physaddr, ACPI_SIG_MADT);
if (madt == NULL) {
printf("Unable to map the MADT, not starting APs\n");
return;
}
cpuid = 0;
acpi_walk_subtables(madt + 1, (char *)madt + madt->Header.Length,
madt_handler, &cpuid);
acpi_unmap_table(madt);
#if MAXMEMDOM > 1
/* set proximity info */
acpi_pxm_set_cpu_locality();
acpi_pxm_free();
#endif
}
#endif
#ifdef FDT
static boolean_t
cpu_init_fdt(u_int id, phandle_t node, u_int addr_size, pcell_t *reg)
{
uint64_t target_cpu;
int domain;
target_cpu = reg[0];
if (addr_size == 2) {
target_cpu <<= 32;
target_cpu |= reg[1];
}
if (!start_cpu(id, target_cpu))
return (FALSE);
/* Try to read the numa node of this cpu */
if (vm_ndomains == 1 ||
OF_getencprop(node, "numa-node-id", &domain, sizeof(domain)) <= 0)
domain = 0;
__pcpu[id].pc_domain = domain;
if (domain < MAXMEMDOM)
CPU_SET(id, &cpuset_domain[domain]);
return (TRUE);
}
#endif
/* Initialize and fire up non-boot processors */
void
cpu_mp_start(void)
{
#ifdef FDT
phandle_t node;
int i;
#endif
mtx_init(&ap_boot_mtx, "ap boot", NULL, MTX_SPIN);
CPU_SET(0, &all_cpus);
switch(arm64_bus_method) {
#ifdef DEV_ACPI
case ARM64_BUS_ACPI:
mp_quirks = MP_QUIRK_CPULIST;
KASSERT(cpu0 >= 0, ("Current CPU was not found"));
cpu_init_acpi();
break;
#endif
#ifdef FDT
case ARM64_BUS_FDT:
node = OF_peer(0);
for (i = 0; fdt_quirks[i].compat != NULL; i++) {
if (ofw_bus_node_is_compatible(node,
fdt_quirks[i].compat) != 0) {
mp_quirks = fdt_quirks[i].quirks;
}
}
KASSERT(cpu0 >= 0, ("Current CPU was not found"));
ofw_cpu_early_foreach(cpu_init_fdt, true);
break;
#endif
default:
break;
}
}
/* Introduce rest of cores to the world */
void
cpu_mp_announce(void)
{
}
#ifdef DEV_ACPI
static void
cpu_count_acpi_handler(ACPI_SUBTABLE_HEADER *entry, void *arg)
{
ACPI_MADT_GENERIC_INTERRUPT *intr;
u_int *cores = arg;
uint64_t mpidr_reg;
switch(entry->Type) {
case ACPI_MADT_TYPE_GENERIC_INTERRUPT:
intr = (ACPI_MADT_GENERIC_INTERRUPT *)entry;
if (cpu0 < 0) {
mpidr_reg = READ_SPECIALREG(mpidr_el1);
if ((mpidr_reg & 0xff00fffffful) == intr->ArmMpidr)
cpu0 = *cores;
}
(*cores)++;
break;
default:
break;
}
}
static u_int
cpu_count_acpi(void)
{
ACPI_TABLE_MADT *madt;
vm_paddr_t physaddr;
u_int cores;
physaddr = acpi_find_table(ACPI_SIG_MADT);
if (physaddr == 0)
return (0);
madt = acpi_map_table(physaddr, ACPI_SIG_MADT);
if (madt == NULL) {
printf("Unable to map the MADT, not starting APs\n");
return (0);
}
cores = 0;
acpi_walk_subtables(madt + 1, (char *)madt + madt->Header.Length,
cpu_count_acpi_handler, &cores);
acpi_unmap_table(madt);
return (cores);
}
#endif
#ifdef FDT
static boolean_t
cpu_find_cpu0_fdt(u_int id, phandle_t node, u_int addr_size, pcell_t *reg)
{
uint64_t mpidr_fdt, mpidr_reg;
if (cpu0 < 0) {
mpidr_fdt = reg[0];
if (addr_size == 2) {
mpidr_fdt <<= 32;
mpidr_fdt |= reg[1];
}
mpidr_reg = READ_SPECIALREG(mpidr_el1);
if ((mpidr_reg & 0xff00fffffful) == mpidr_fdt)
cpu0 = id;
}
return (TRUE);
}
#endif
void
cpu_mp_setmaxid(void)
{
int cores;
mp_ncpus = 1;
mp_maxid = 0;
switch(arm64_bus_method) {
#ifdef DEV_ACPI
case ARM64_BUS_ACPI:
cores = cpu_count_acpi();
if (cores > 0) {
cores = MIN(cores, MAXCPU);
if (bootverbose)
printf("Found %d CPUs in the ACPI tables\n",
cores);
mp_ncpus = cores;
mp_maxid = cores - 1;
}
break;
#endif
#ifdef FDT
case ARM64_BUS_FDT:
cores = ofw_cpu_early_foreach(cpu_find_cpu0_fdt, false);
if (cores > 0) {
cores = MIN(cores, MAXCPU);
if (bootverbose)
printf("Found %d CPUs in the device tree\n",
cores);
mp_ncpus = cores;
mp_maxid = cores - 1;
}
break;
#endif
default:
if (bootverbose)
printf("No CPU data, limiting to 1 core\n");
break;
}
if (TUNABLE_INT_FETCH("hw.ncpu", &cores)) {
if (cores > 0 && cores < mp_ncpus) {
mp_ncpus = cores;
mp_maxid = cores - 1;
}
}
}
/*
* Lookup IPI source.
*/
static struct intr_ipi *
intr_ipi_lookup(u_int ipi)
{
if (ipi >= INTR_IPI_COUNT)
panic("%s: no such IPI %u", __func__, ipi);
return (&ipi_sources[ipi]);
}
/*
* interrupt controller dispatch function for IPIs. It should
* be called straight from the interrupt controller, when associated
* interrupt source is learned. Or from anybody who has an interrupt
* source mapped.
*/
void
intr_ipi_dispatch(u_int ipi, struct trapframe *tf)
{
void *arg;
struct intr_ipi *ii;
ii = intr_ipi_lookup(ipi);
if (ii->ii_count == NULL)
panic("%s: not setup IPI %u", __func__, ipi);
intr_ipi_increment_count(ii->ii_count, PCPU_GET(cpuid));
/*
* Supply ipi filter with trapframe argument
* if none is registered.
*/
arg = ii->ii_handler_arg != NULL ? ii->ii_handler_arg : tf;
ii->ii_handler(arg);
}
#ifdef notyet
/*
* Map IPI into interrupt controller.
*
* Not SMP coherent.
*/
static int
ipi_map(struct intr_irqsrc *isrc, u_int ipi)
{
boolean_t is_percpu;
int error;
if (ipi >= INTR_IPI_COUNT)
panic("%s: no such IPI %u", __func__, ipi);
KASSERT(intr_irq_root_dev != NULL, ("%s: no root attached", __func__));
isrc->isrc_type = INTR_ISRCT_NAMESPACE;
isrc->isrc_nspc_type = INTR_IRQ_NSPC_IPI;
isrc->isrc_nspc_num = ipi_next_num;
error = PIC_REGISTER(intr_irq_root_dev, isrc, &is_percpu);
if (error == 0) {
isrc->isrc_dev = intr_irq_root_dev;
ipi_next_num++;
}
return (error);
}
/*
* Setup IPI handler to interrupt source.
*
* Note that there could be more ways how to send and receive IPIs
* on a platform like fast interrupts for example. In that case,
* one can call this function with ASIF_NOALLOC flag set and then
* call intr_ipi_dispatch() when appropriate.
*
* Not SMP coherent.
*/
int
intr_ipi_set_handler(u_int ipi, const char *name, intr_ipi_filter_t *filter,
void *arg, u_int flags)
{
struct intr_irqsrc *isrc;
int error;
if (filter == NULL)
return(EINVAL);
isrc = intr_ipi_lookup(ipi);
if (isrc->isrc_ipifilter != NULL)
return (EEXIST);
if ((flags & AISHF_NOALLOC) == 0) {
error = ipi_map(isrc, ipi);
if (error != 0)
return (error);
}
isrc->isrc_ipifilter = filter;
isrc->isrc_arg = arg;
isrc->isrc_handlers = 1;
isrc->isrc_count = intr_ipi_setup_counters(name);
isrc->isrc_index = 0; /* it should not be used in IPI case */
if (isrc->isrc_dev != NULL) {
PIC_ENABLE_INTR(isrc->isrc_dev, isrc);
PIC_ENABLE_SOURCE(isrc->isrc_dev, isrc);
}
return (0);
}
#endif
/* Sending IPI */
void
ipi_all_but_self(u_int ipi)
{
cpuset_t cpus;
cpus = all_cpus;
CPU_CLR(PCPU_GET(cpuid), &cpus);
CTR2(KTR_SMP, "%s: ipi: %x", __func__, ipi);
intr_ipi_send(cpus, ipi);
}
void
ipi_cpu(int cpu, u_int ipi)
{
cpuset_t cpus;
CPU_ZERO(&cpus);
CPU_SET(cpu, &cpus);
CTR3(KTR_SMP, "%s: cpu: %d, ipi: %x", __func__, cpu, ipi);
intr_ipi_send(cpus, ipi);
}
void
ipi_selected(cpuset_t cpus, u_int ipi)
{
CTR2(KTR_SMP, "%s: ipi: %x", __func__, ipi);
intr_ipi_send(cpus, ipi);
}
Index: head/sys/arm64/include/debug_monitor.h
===================================================================
--- head/sys/arm64/include/debug_monitor.h (revision 354174)
+++ head/sys/arm64/include/debug_monitor.h (revision 354175)
@@ -1,63 +1,70 @@
/*-
* Copyright (c) 2014 The FreeBSD Foundation
* All rights reserved.
*
* This software was developed by Semihalf under
* the sponsorship of the FreeBSD Foundation.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*
* $FreeBSD$
*/
#ifndef _MACHINE_DEBUG_MONITOR_H_
#define _MACHINE_DEBUG_MONITOR_H_
-#ifdef DDB
+#ifdef _KERNEL
-#include <machine/db_machdep.h>
+#define DBG_BRP_MAX 16
+#define DBG_WRP_MAX 16
-enum dbg_el_t {
- DBG_FROM_EL0 = 0,
- DBG_FROM_EL1 = 1,
+struct debug_monitor_state {
+ uint32_t dbg_enable_count;
+ uint32_t dbg_flags;
+#define DBGMON_ENABLED (1 << 0)
+#define DBGMON_KERNEL (1 << 1)
+ uint64_t dbg_bcr[DBG_BRP_MAX];
+ uint64_t dbg_bvr[DBG_BRP_MAX];
+ uint64_t dbg_wcr[DBG_WRP_MAX];
+ uint64_t dbg_wvr[DBG_WRP_MAX];
};
enum dbg_access_t {
HW_BREAKPOINT_X = 0,
HW_BREAKPOINT_R = 1,
HW_BREAKPOINT_W = 2,
HW_BREAKPOINT_RW = HW_BREAKPOINT_R | HW_BREAKPOINT_W,
};
void dbg_monitor_init(void);
+void dbg_register_sync(struct debug_monitor_state *);
+int dbg_setup_watchpoint(struct debug_monitor_state *, vm_offset_t, vm_size_t,
+ enum dbg_access_t);
+int dbg_remove_watchpoint(struct debug_monitor_state *, vm_offset_t, vm_size_t);
+
+#ifdef DDB
void dbg_show_watchpoint(void);
-int dbg_setup_watchpoint(db_expr_t addr, db_expr_t size, enum dbg_el_t el,
- enum dbg_access_t access);
-int dbg_remove_watchpoint(db_expr_t addr, db_expr_t size, enum dbg_el_t el);
-#else
-static __inline void
-dbg_monitor_init(void)
-{
-}
#endif
+
+#endif /* _KERNEL */
#endif /* _MACHINE_DEBUG_MONITOR_H_ */
Index: head/sys/arm64/include/pcpu.h
===================================================================
--- head/sys/arm64/include/pcpu.h (revision 354174)
+++ head/sys/arm64/include/pcpu.h (revision 354175)
@@ -1,82 +1,83 @@
/*-
* Copyright (c) 1999 Luoqi Chen <luoqi@freebsd.org>
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*
* from: FreeBSD: src/sys/i386/include/globaldata.h,v 1.27 2001/04/27
* $FreeBSD$
*/
#ifndef _MACHINE_PCPU_H_
#define _MACHINE_PCPU_H_
#include <machine/cpu.h>
#include <machine/cpufunc.h>
#define ALT_STACK_SIZE 128
typedef int (*pcpu_bp_harden)(void);
typedef int (*pcpu_ssbd)(int);
+struct debug_monitor_state;
#define PCPU_MD_FIELDS \
u_int pc_acpi_id; /* ACPI CPU id */ \
u_int pc_midr; /* stored MIDR value */ \
uint64_t pc_clock; \
pcpu_bp_harden pc_bp_harden; \
pcpu_ssbd pc_ssbd; \
char __pad[225]
#ifdef _KERNEL
struct pcb;
struct pcpu;
static inline struct pcpu *
get_pcpu(void)
{
struct pcpu *pcpu;
__asm __volatile("mov %0, x18" : "=&r"(pcpu));
return (pcpu);
}
static inline struct thread *
get_curthread(void)
{
struct thread *td;
__asm __volatile("ldr %0, [x18]" : "=&r"(td));
return (td);
}
#define curthread get_curthread()
#define PCPU_GET(member) (get_pcpu()->pc_ ## member)
#define PCPU_ADD(member, value) (get_pcpu()->pc_ ## member += (value))
#define PCPU_INC(member) PCPU_ADD(member, 1)
#define PCPU_PTR(member) (&get_pcpu()->pc_ ## member)
#define PCPU_SET(member,value) (get_pcpu()->pc_ ## member = (value))
#endif /* _KERNEL */
#endif /* !_MACHINE_PCPU_H_ */
Index: head/sys/conf/files.arm64
===================================================================
--- head/sys/conf/files.arm64 (revision 354174)
+++ head/sys/conf/files.arm64 (revision 354175)
@@ -1,317 +1,317 @@
# $FreeBSD$
cloudabi32_vdso.o optional compat_cloudabi32 \
dependency "$S/contrib/cloudabi/cloudabi_vdso_armv6_on_64bit.S" \
compile-with "${CC} -x assembler-with-cpp -m32 -shared -nostdinc -nostdlib -Wl,-T$S/compat/cloudabi/cloudabi_vdso.lds $S/contrib/cloudabi/cloudabi_vdso_armv6_on_64bit.S -o ${.TARGET}" \
no-obj no-implicit-rule \
clean "cloudabi32_vdso.o"
#
cloudabi32_vdso_blob.o optional compat_cloudabi32 \
dependency "cloudabi32_vdso.o" \
compile-with "${OBJCOPY} --input-target binary --output-target elf64-littleaarch64 --binary-architecture aarch64 cloudabi32_vdso.o ${.TARGET}" \
no-implicit-rule \
clean "cloudabi32_vdso_blob.o"
#
cloudabi64_vdso.o optional compat_cloudabi64 \
dependency "$S/contrib/cloudabi/cloudabi_vdso_aarch64.S" \
compile-with "${CC} -x assembler-with-cpp -shared -nostdinc -nostdlib -Wl,-T$S/compat/cloudabi/cloudabi_vdso.lds $S/contrib/cloudabi/cloudabi_vdso_aarch64.S -o ${.TARGET}" \
no-obj no-implicit-rule \
clean "cloudabi64_vdso.o"
#
cloudabi64_vdso_blob.o optional compat_cloudabi64 \
dependency "cloudabi64_vdso.o" \
compile-with "${OBJCOPY} --input-target binary --output-target elf64-littleaarch64 --binary-architecture aarch64 cloudabi64_vdso.o ${.TARGET}" \
no-implicit-rule \
clean "cloudabi64_vdso_blob.o"
#
# Allwinner common files
arm/allwinner/a10_timer.c optional a10_timer fdt
arm/allwinner/a10_codec.c optional sound a10_codec
arm/allwinner/a31_dmac.c optional a31_dmac
arm/allwinner/sunxi_dma_if.m optional a31_dmac
arm/allwinner/aw_cir.c optional evdev aw_cir fdt
arm/allwinner/aw_dwc3.c optional aw_dwc3 fdt
arm/allwinner/aw_gpio.c optional gpio aw_gpio fdt
arm/allwinner/aw_mmc.c optional mmc aw_mmc fdt | mmccam aw_mmc fdt
arm/allwinner/aw_nmi.c optional aw_nmi fdt \
compile-with "${NORMAL_C} -I$S/gnu/dts/include"
arm/allwinner/aw_pwm.c optional aw_pwm fdt
arm/allwinner/aw_rsb.c optional aw_rsb fdt
arm/allwinner/aw_rtc.c optional aw_rtc fdt
arm/allwinner/aw_sid.c optional aw_sid nvmem fdt
arm/allwinner/aw_spi.c optional aw_spi fdt
arm/allwinner/aw_syscon.c optional aw_syscon ext_resources syscon fdt
arm/allwinner/aw_thermal.c optional aw_thermal nvmem fdt
arm/allwinner/aw_usbphy.c optional ehci aw_usbphy fdt
arm/allwinner/aw_usb3phy.c optional xhci aw_usbphy fdt
arm/allwinner/aw_wdog.c optional aw_wdog fdt
arm/allwinner/axp81x.c optional axp81x fdt
arm/allwinner/if_awg.c optional awg ext_resources syscon aw_sid nvmem fdt
# Allwinner clock driver
arm/allwinner/clkng/aw_ccung.c optional aw_ccu fdt
arm/allwinner/clkng/aw_clk_frac.c optional aw_ccu fdt
arm/allwinner/clkng/aw_clk_m.c optional aw_ccu fdt
arm/allwinner/clkng/aw_clk_mipi.c optional aw_ccu fdt
arm/allwinner/clkng/aw_clk_nkmp.c optional aw_ccu fdt
arm/allwinner/clkng/aw_clk_nm.c optional aw_ccu fdt
arm/allwinner/clkng/aw_clk_nmm.c optional aw_ccu fdt
arm/allwinner/clkng/aw_clk_np.c optional aw_ccu fdt
arm/allwinner/clkng/aw_clk_prediv_mux.c optional aw_ccu fdt
arm/allwinner/clkng/ccu_a64.c optional soc_allwinner_a64 aw_ccu fdt
arm/allwinner/clkng/ccu_h3.c optional soc_allwinner_h5 aw_ccu fdt
arm/allwinner/clkng/ccu_h6.c optional soc_allwinner_h6 aw_ccu fdt
arm/allwinner/clkng/ccu_h6_r.c optional soc_allwinner_h6 aw_ccu fdt
arm/allwinner/clkng/ccu_sun8i_r.c optional aw_ccu fdt
arm/allwinner/clkng/ccu_de2.c optional aw_ccu fdt
# Allwinner padconf files
arm/allwinner/a64/a64_padconf.c optional soc_allwinner_a64 fdt
arm/allwinner/a64/a64_r_padconf.c optional soc_allwinner_a64 fdt
arm/allwinner/h3/h3_padconf.c optional soc_allwinner_h5 fdt
arm/allwinner/h3/h3_r_padconf.c optional soc_allwinner_h5 fdt
arm/allwinner/h6/h6_padconf.c optional soc_allwinner_h6 fdt
arm/allwinner/h6/h6_r_padconf.c optional soc_allwinner_h6 fdt
arm/annapurna/alpine/alpine_ccu.c optional al_ccu fdt
arm/annapurna/alpine/alpine_nb_service.c optional al_nb_service fdt
arm/annapurna/alpine/alpine_pci.c optional al_pci fdt
arm/annapurna/alpine/alpine_pci_msix.c optional al_pci fdt
arm/annapurna/alpine/alpine_serdes.c optional al_serdes fdt \
no-depend \
compile-with "${CC} -c -o ${.TARGET} ${CFLAGS} -I$S/contrib/alpine-hal -I$S/contrib/alpine-hal/eth ${PROF} ${.IMPSRC}"
arm/arm/generic_timer.c standard
arm/arm/gic.c standard
arm/arm/gic_acpi.c optional acpi
arm/arm/gic_fdt.c optional fdt
arm/arm/pmu.c standard
arm/arm/physmem.c standard
arm/broadcom/bcm2835/bcm2835_audio.c optional sound vchiq fdt \
compile-with "${NORMAL_C} -DUSE_VCHIQ_ARM -D__VCCOREVER__=0x04000000 -I$S/contrib/vchiq"
arm/broadcom/bcm2835/bcm2835_bsc.c optional bcm2835_bsc soc_brcm_bcm2837 fdt
arm/broadcom/bcm2835/bcm2835_cpufreq.c optional soc_brcm_bcm2837 fdt
arm/broadcom/bcm2835/bcm2835_dma.c optional soc_brcm_bcm2837 fdt
arm/broadcom/bcm2835/bcm2835_fbd.c optional vt soc_brcm_bcm2837 fdt
arm/broadcom/bcm2835/bcm2835_ft5406.c optional evdev bcm2835_ft5406 soc_brcm_bcm2837 fdt
arm/broadcom/bcm2835/bcm2835_gpio.c optional gpio soc_brcm_bcm2837 fdt
arm/broadcom/bcm2835/bcm2835_intr.c optional soc_brcm_bcm2837 fdt
arm/broadcom/bcm2835/bcm2835_mbox.c optional soc_brcm_bcm2837 fdt
arm/broadcom/bcm2835/bcm2835_rng.c optional !random_loadable soc_brcm_bcm2837 fdt
arm/broadcom/bcm2835/bcm2835_sdhci.c optional sdhci soc_brcm_bcm2837 fdt
arm/broadcom/bcm2835/bcm2835_sdhost.c optional sdhci soc_brcm_bcm2837 fdt
arm/broadcom/bcm2835/bcm2835_spi.c optional bcm2835_spi soc_brcm_bcm2837 fdt
arm/broadcom/bcm2835/bcm2835_vcio.c optional soc_brcm_bcm2837 fdt
arm/broadcom/bcm2835/bcm2835_wdog.c optional soc_brcm_bcm2837 fdt
arm/broadcom/bcm2835/bcm2836.c optional soc_brcm_bcm2837 fdt
arm/broadcom/bcm2835/bcm283x_dwc_fdt.c optional dwcotg fdt soc_brcm_bcm2837
arm/mv/a37x0_gpio.c optional a37x0_gpio gpio fdt
arm/mv/armada38x/armada38x_rtc.c optional mv_rtc fdt
arm/mv/gpio.c optional mv_gpio fdt
arm/mv/mvebu_pinctrl.c optional mvebu_pinctrl fdt
arm/mv/mv_ap806_clock.c optional SOC_MARVELL_8K fdt
arm/mv/mv_ap806_gicp.c optional mv_ap806_gicp fdt
arm/mv/mv_ap806_sei.c optional mv_ap806_sei fdt
arm/mv/mv_cp110_clock.c optional SOC_MARVELL_8K fdt
arm/mv/mv_cp110_icu.c optional mv_cp110_icu fdt
arm/mv/mv_cp110_icu_bus.c optional mv_cp110_icu fdt
arm/mv/mv_thermal.c optional SOC_MARVELL_8K mv_thermal fdt
arm/mv/armada38x/armada38x_rtc.c optional mv_rtc fdt
arm/xilinx/uart_dev_cdnc.c optional uart soc_xilinx_zynq
arm64/acpica/acpi_iort.c optional acpi
arm64/acpica/acpi_machdep.c optional acpi
arm64/acpica/OsdEnvironment.c optional acpi
arm64/acpica/acpi_wakeup.c optional acpi
arm64/acpica/pci_cfgreg.c optional acpi pci
arm64/arm64/autoconf.c standard
arm64/arm64/bus_machdep.c standard
arm64/arm64/bus_space_asm.S standard
arm64/arm64/busdma_bounce.c standard
arm64/arm64/busdma_machdep.c standard
arm64/arm64/bzero.S standard
arm64/arm64/clock.c standard
arm64/arm64/copyinout.S standard
arm64/arm64/copystr.c standard
arm64/arm64/cpu_errata.c standard
arm64/arm64/cpufunc_asm.S standard
arm64/arm64/db_disasm.c optional ddb
arm64/arm64/db_interface.c optional ddb
arm64/arm64/db_trace.c optional ddb
-arm64/arm64/debug_monitor.c optional ddb
+arm64/arm64/debug_monitor.c standard
arm64/arm64/disassem.c optional ddb
arm64/arm64/dump_machdep.c standard
arm64/arm64/efirt_machdep.c optional efirt
arm64/arm64/elf32_machdep.c optional compat_freebsd32
arm64/arm64/elf_machdep.c standard
arm64/arm64/exception.S standard
arm64/arm64/freebsd32_machdep.c optional compat_freebsd32
arm64/arm64/gicv3_its.c optional intrng fdt
arm64/arm64/gic_v3.c standard
arm64/arm64/gic_v3_acpi.c optional acpi
arm64/arm64/gic_v3_fdt.c optional fdt
arm64/arm64/identcpu.c standard
arm64/arm64/in_cksum.c optional inet | inet6
arm64/arm64/locore.S standard no-obj
arm64/arm64/machdep.c standard
arm64/arm64/mem.c standard
arm64/arm64/memcpy.S standard
arm64/arm64/memmove.S standard
arm64/arm64/minidump_machdep.c standard
arm64/arm64/mp_machdep.c optional smp
arm64/arm64/nexus.c standard
arm64/arm64/ofw_machdep.c optional fdt
arm64/arm64/pmap.c standard
arm64/arm64/stack_machdep.c optional ddb | stack
arm64/arm64/support.S standard
arm64/arm64/swtch.S standard
arm64/arm64/sys_machdep.c standard
arm64/arm64/trap.c standard
arm64/arm64/uio_machdep.c standard
arm64/arm64/uma_machdep.c standard
arm64/arm64/undefined.c standard
arm64/arm64/unwind.c optional ddb | kdtrace_hooks | stack
arm64/arm64/vfp.c standard
arm64/arm64/vm_machdep.c standard
arm64/cavium/thunder_pcie_fdt.c optional soc_cavm_thunderx pci fdt
arm64/cavium/thunder_pcie_pem.c optional soc_cavm_thunderx pci
arm64/cavium/thunder_pcie_pem_fdt.c optional soc_cavm_thunderx pci fdt
arm64/cavium/thunder_pcie_common.c optional soc_cavm_thunderx pci
arm64/cloudabi32/cloudabi32_sysvec.c optional compat_cloudabi32
arm64/cloudabi64/cloudabi64_sysvec.c optional compat_cloudabi64
arm64/coresight/coresight.c standard
arm64/coresight/coresight_if.m standard
arm64/coresight/coresight-cmd.c standard
arm64/coresight/coresight-cpu-debug.c standard
arm64/coresight/coresight-dynamic-replicator.c standard
arm64/coresight/coresight-etm4x.c standard
arm64/coresight/coresight-funnel.c standard
arm64/coresight/coresight-tmc.c standard
arm64/intel/firmware.c optional soc_intel_stratix10
arm64/intel/stratix10-soc-fpga-mgr.c optional soc_intel_stratix10
arm64/intel/stratix10-svc.c optional soc_intel_stratix10
arm64/qualcomm/qcom_gcc.c optional qcom_gcc fdt
contrib/vchiq/interface/compat/vchi_bsd.c optional vchiq soc_brcm_bcm2837 \
compile-with "${NORMAL_C} -DUSE_VCHIQ_ARM -D__VCCOREVER__=0x04000000 -I$S/contrib/vchiq"
contrib/vchiq/interface/vchiq_arm/vchiq_2835_arm.c optional vchiq soc_brcm_bcm2837 \
compile-with "${NORMAL_C} -Wno-unused -DUSE_VCHIQ_ARM -D__VCCOREVER__=0x04000000 -I$S/contrib/vchiq"
contrib/vchiq/interface/vchiq_arm/vchiq_arm.c optional vchiq soc_brcm_bcm2837 \
compile-with "${NORMAL_C} -Wno-unused -DUSE_VCHIQ_ARM -D__VCCOREVER__=0x04000000 -I$S/contrib/vchiq"
contrib/vchiq/interface/vchiq_arm/vchiq_connected.c optional vchiq soc_brcm_bcm2837 \
compile-with "${NORMAL_C} -DUSE_VCHIQ_ARM -D__VCCOREVER__=0x04000000 -I$S/contrib/vchiq"
contrib/vchiq/interface/vchiq_arm/vchiq_core.c optional vchiq soc_brcm_bcm2837 \
compile-with "${NORMAL_C} -DUSE_VCHIQ_ARM -D__VCCOREVER__=0x04000000 -I$S/contrib/vchiq"
contrib/vchiq/interface/vchiq_arm/vchiq_kern_lib.c optional vchiq soc_brcm_bcm2837 \
compile-with "${NORMAL_C} -DUSE_VCHIQ_ARM -D__VCCOREVER__=0x04000000 -I$S/contrib/vchiq"
contrib/vchiq/interface/vchiq_arm/vchiq_kmod.c optional vchiq soc_brcm_bcm2837 \
compile-with "${NORMAL_C} -DUSE_VCHIQ_ARM -D__VCCOREVER__=0x04000000 -I$S/contrib/vchiq"
contrib/vchiq/interface/vchiq_arm/vchiq_shim.c optional vchiq soc_brcm_bcm2837 \
compile-with "${NORMAL_C} -DUSE_VCHIQ_ARM -D__VCCOREVER__=0x04000000 -I$S/contrib/vchiq"
contrib/vchiq/interface/vchiq_arm/vchiq_util.c optional vchiq soc_brcm_bcm2837 \
compile-with "${NORMAL_C} -DUSE_VCHIQ_ARM -D__VCCOREVER__=0x04000000 -I$S/contrib/vchiq"
crypto/armv8/armv8_crypto.c optional armv8crypto
armv8_crypto_wrap.o optional armv8crypto \
dependency "$S/crypto/armv8/armv8_crypto_wrap.c" \
compile-with "${CC} -c ${CFLAGS:C/^-O2$/-O3/:N-nostdinc:N-mgeneral-regs-only} -I$S/crypto/armv8/ ${WERROR} ${NO_WCAST_QUAL} ${PROF} -march=armv8-a+crypto ${.IMPSRC}" \
no-implicit-rule \
clean "armv8_crypto_wrap.o"
crypto/blowfish/bf_enc.c optional crypto | ipsec | ipsec_support
crypto/des/des_enc.c optional crypto | ipsec | ipsec_support | netsmb
dev/acpica/acpi_bus_if.m optional acpi
dev/acpica/acpi_if.m optional acpi
dev/acpica/acpi_pci_link.c optional acpi pci
dev/acpica/acpi_pcib.c optional acpi pci
dev/acpica/acpi_pxm.c optional acpi
dev/ahci/ahci_generic.c optional ahci
dev/altera/dwc/if_dwc_socfpga.c optional fdt dwc_socfpga
dev/axgbe/if_axgbe.c optional axgbe
dev/axgbe/xgbe-desc.c optional axgbe
dev/axgbe/xgbe-dev.c optional axgbe
dev/axgbe/xgbe-drv.c optional axgbe
dev/axgbe/xgbe-mdio.c optional axgbe
dev/cpufreq/cpufreq_dt.c optional cpufreq fdt
dev/iicbus/sy8106a.c optional sy8106a fdt
dev/iicbus/twsi/mv_twsi.c optional twsi fdt
dev/iicbus/twsi/a10_twsi.c optional twsi fdt
dev/iicbus/twsi/twsi.c optional twsi fdt
dev/hwpmc/hwpmc_arm64.c optional hwpmc
dev/hwpmc/hwpmc_arm64_md.c optional hwpmc
dev/mbox/mbox_if.m optional soc_brcm_bcm2837
dev/mmc/host/dwmmc.c optional dwmmc fdt
dev/mmc/host/dwmmc_altera.c optional dwmmc fdt dwmmc_altera
dev/mmc/host/dwmmc_hisi.c optional dwmmc fdt soc_hisi_hi6220
dev/mmc/host/dwmmc_rockchip.c optional dwmmc fdt soc_rockchip_rk3328
dev/neta/if_mvneta_fdt.c optional neta fdt
dev/neta/if_mvneta.c optional neta mdio mii
dev/ofw/ofw_cpu.c optional fdt
dev/ofw/ofwpci.c optional fdt pci
dev/pci/pci_host_generic.c optional pci
dev/pci/pci_host_generic_acpi.c optional pci acpi
dev/pci/pci_host_generic_fdt.c optional pci fdt
dev/pci/pci_dw_mv.c optional pci fdt
dev/pci/pci_dw.c optional pci fdt
dev/pci/pci_dw_if.m optional pci fdt
dev/psci/psci.c standard
dev/psci/smccc_arm64.S standard
dev/psci/smccc.c standard
dev/sdhci/sdhci_xenon.c optional sdhci_xenon sdhci fdt
dev/uart/uart_cpu_arm64.c optional uart
dev/uart/uart_dev_mu.c optional uart uart_mu
dev/uart/uart_dev_pl011.c optional uart pl011
dev/usb/controller/dwc_otg_hisi.c optional dwcotg fdt soc_hisi_hi6220
dev/usb/controller/dwc3.c optional fdt dwc3
dev/usb/controller/ehci_mv.c optional ehci_mv fdt
dev/usb/controller/generic_ehci.c optional ehci
dev/usb/controller/generic_ehci_acpi.c optional ehci acpi
dev/usb/controller/generic_ehci_fdt.c optional ehci fdt
dev/usb/controller/generic_ohci.c optional ohci fdt
dev/usb/controller/generic_usb_if.m optional ohci fdt
dev/usb/controller/usb_nop_xceiv.c optional fdt ext_resources
dev/usb/controller/generic_xhci.c optional xhci
dev/usb/controller/generic_xhci_acpi.c optional xhci acpi
dev/usb/controller/generic_xhci_fdt.c optional xhci fdt
dev/vnic/mrml_bridge.c optional vnic fdt
dev/vnic/nic_main.c optional vnic pci
dev/vnic/nicvf_main.c optional vnic pci pci_iov
dev/vnic/nicvf_queues.c optional vnic pci pci_iov
dev/vnic/thunder_bgx_fdt.c optional vnic fdt
dev/vnic/thunder_bgx.c optional vnic pci
dev/vnic/thunder_mdio_fdt.c optional vnic fdt
dev/vnic/thunder_mdio.c optional vnic
dev/vnic/lmac_if.m optional inet | inet6 | vnic
kern/kern_clocksource.c standard
kern/msi_if.m optional intrng
kern/pic_if.m optional intrng
kern/subr_devmap.c standard
kern/subr_intr.c optional intrng
libkern/bcmp.c standard
libkern/memcmp.c standard
libkern/memset.c standard
libkern/arm64/crc32c_armv8.S standard
cddl/dev/dtrace/aarch64/dtrace_asm.S optional dtrace compile-with "${DTRACE_S}"
cddl/dev/dtrace/aarch64/dtrace_subr.c optional dtrace compile-with "${DTRACE_C}"
cddl/dev/fbt/aarch64/fbt_isa.c optional dtrace_fbt | dtraceall compile-with "${FBT_C}"
# RockChip Drivers
arm64/rockchip/rk3399_emmcphy.c optional fdt rk_emmcphy soc_rockchip_rk3399
arm64/rockchip/rk_dwc3.c optional fdt rk_dwc3 soc_rockchip_rk3399
arm64/rockchip/rk_i2c.c optional fdt rk_i2c soc_rockchip_rk3328 | fdt rk_i2c soc_rockchip_rk3399
arm64/rockchip/rk805.c optional fdt rk805 soc_rockchip_rk3328 | fdt rk805 soc_rockchip_rk3399
arm64/rockchip/rk_grf.c optional fdt soc_rockchip_rk3328 | fdt soc_rockchip_rk3399
arm64/rockchip/rk_pinctrl.c optional fdt rk_pinctrl soc_rockchip_rk3328 | fdt rk_pinctrl soc_rockchip_rk3399
arm64/rockchip/rk_gpio.c optional fdt rk_gpio soc_rockchip_rk3328 | fdt rk_gpio soc_rockchip_rk3399
arm64/rockchip/rk_spi.c optional fdt rk_spi
arm64/rockchip/rk_usb2phy.c optional fdt rk_usb2phy soc_rockchip_rk3328 | soc_rockchip_rk3399
arm64/rockchip/rk_typec_phy.c optional fdt rk_typec_phy soc_rockchip_rk3399
arm64/rockchip/if_dwc_rk.c optional fdt dwc_rk soc_rockchip_rk3328 | fdt dwc_rk soc_rockchip_rk3399
dev/dwc/if_dwc.c optional fdt dwc_rk soc_rockchip_rk3328 | fdt dwc_rk soc_rockchip_rk3399
dev/dwc/if_dwc_if.m optional fdt dwc_rk soc_rockchip_rk3328 | fdt dwc_rk soc_rockchip_rk3399
# RockChip Clock support
arm64/rockchip/clk/rk_cru.c optional fdt soc_rockchip_rk3328 | fdt soc_rockchip_rk3399
arm64/rockchip/clk/rk_clk_armclk.c optional fdt soc_rockchip_rk3328 | fdt soc_rockchip_rk3399
arm64/rockchip/clk/rk_clk_composite.c optional fdt soc_rockchip_rk3328 | fdt soc_rockchip_rk3399
arm64/rockchip/clk/rk_clk_gate.c optional fdt soc_rockchip_rk3328 | fdt soc_rockchip_rk3399
arm64/rockchip/clk/rk_clk_mux.c optional fdt soc_rockchip_rk3328 | fdt soc_rockchip_rk3399
arm64/rockchip/clk/rk_clk_pll.c optional fdt soc_rockchip_rk3328 | fdt soc_rockchip_rk3399
arm64/rockchip/clk/rk3328_cru.c optional fdt soc_rockchip_rk3328
arm64/rockchip/clk/rk3399_cru.c optional fdt soc_rockchip_rk3399
arm64/rockchip/clk/rk3399_pmucru.c optional fdt soc_rockchip_rk3399