Index: head/contrib/llvm/lib/Object/ELFObjectFile.cpp =================================================================== --- head/contrib/llvm/lib/Object/ELFObjectFile.cpp (revision 354096) +++ head/contrib/llvm/lib/Object/ELFObjectFile.cpp (revision 354097) @@ -1,422 +1,422 @@ //===- ELFObjectFile.cpp - ELF object file implementation -----------------===// // // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. // See https://llvm.org/LICENSE.txt for license information. // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception // //===----------------------------------------------------------------------===// // // Part of the ELFObjectFile class implementation. // //===----------------------------------------------------------------------===// #include "llvm/Object/ELFObjectFile.h" #include "llvm/ADT/Triple.h" #include "llvm/BinaryFormat/ELF.h" #include "llvm/MC/MCInstrAnalysis.h" #include "llvm/MC/SubtargetFeature.h" #include "llvm/Object/ELF.h" #include "llvm/Object/ELFTypes.h" #include "llvm/Object/Error.h" #include "llvm/Support/ARMAttributeParser.h" #include "llvm/Support/ARMBuildAttributes.h" #include "llvm/Support/Endian.h" #include "llvm/Support/ErrorHandling.h" #include "llvm/Support/MathExtras.h" #include "llvm/Support/TargetRegistry.h" #include #include #include #include #include #include #include using namespace llvm; using namespace object; const EnumEntry llvm::object::ElfSymbolTypes[NumElfSymbolTypes] = { {"None", "NOTYPE", ELF::STT_NOTYPE}, {"Object", "OBJECT", ELF::STT_OBJECT}, {"Function", "FUNC", ELF::STT_FUNC}, {"Section", "SECTION", ELF::STT_SECTION}, {"File", "FILE", ELF::STT_FILE}, {"Common", "COMMON", ELF::STT_COMMON}, {"TLS", "TLS", ELF::STT_TLS}, {"GNU_IFunc", "IFUNC", ELF::STT_GNU_IFUNC}}; ELFObjectFileBase::ELFObjectFileBase(unsigned int Type, MemoryBufferRef Source) : ObjectFile(Type, Source) {} template static Expected>> createPtr(MemoryBufferRef Object) { auto Ret = ELFObjectFile::create(Object); if (Error E = Ret.takeError()) return std::move(E); return make_unique>(std::move(*Ret)); } Expected> ObjectFile::createELFObjectFile(MemoryBufferRef Obj) { std::pair Ident = getElfArchType(Obj.getBuffer()); std::size_t MaxAlignment = 1ULL << countTrailingZeros(uintptr_t(Obj.getBufferStart())); if (MaxAlignment < 2) return createError("Insufficient alignment"); if (Ident.first == ELF::ELFCLASS32) { if (Ident.second == ELF::ELFDATA2LSB) return createPtr(Obj); else if (Ident.second == ELF::ELFDATA2MSB) return createPtr(Obj); else return createError("Invalid ELF data"); } else if (Ident.first == ELF::ELFCLASS64) { if (Ident.second == ELF::ELFDATA2LSB) return createPtr(Obj); else if (Ident.second == ELF::ELFDATA2MSB) return createPtr(Obj); else return createError("Invalid ELF data"); } return createError("Invalid ELF class"); } SubtargetFeatures ELFObjectFileBase::getMIPSFeatures() const { SubtargetFeatures Features; unsigned PlatformFlags = getPlatformFlags(); switch (PlatformFlags & ELF::EF_MIPS_ARCH) { case ELF::EF_MIPS_ARCH_1: break; case ELF::EF_MIPS_ARCH_2: Features.AddFeature("mips2"); break; case ELF::EF_MIPS_ARCH_3: Features.AddFeature("mips3"); break; case ELF::EF_MIPS_ARCH_4: Features.AddFeature("mips4"); break; case ELF::EF_MIPS_ARCH_5: Features.AddFeature("mips5"); break; case ELF::EF_MIPS_ARCH_32: Features.AddFeature("mips32"); break; case ELF::EF_MIPS_ARCH_64: Features.AddFeature("mips64"); break; case ELF::EF_MIPS_ARCH_32R2: Features.AddFeature("mips32r2"); break; case ELF::EF_MIPS_ARCH_64R2: Features.AddFeature("mips64r2"); break; case ELF::EF_MIPS_ARCH_32R6: Features.AddFeature("mips32r6"); break; case ELF::EF_MIPS_ARCH_64R6: Features.AddFeature("mips64r6"); break; default: llvm_unreachable("Unknown EF_MIPS_ARCH value"); } switch (PlatformFlags & ELF::EF_MIPS_MACH) { case ELF::EF_MIPS_MACH_NONE: // No feature associated with this value. break; case ELF::EF_MIPS_MACH_OCTEON: Features.AddFeature("cnmips"); break; default: llvm_unreachable("Unknown EF_MIPS_ARCH value"); } if (PlatformFlags & ELF::EF_MIPS_ARCH_ASE_M16) Features.AddFeature("mips16"); if (PlatformFlags & ELF::EF_MIPS_MICROMIPS) Features.AddFeature("micromips"); return Features; } SubtargetFeatures ELFObjectFileBase::getARMFeatures() const { SubtargetFeatures Features; ARMAttributeParser Attributes; if (Error E = getBuildAttributes(Attributes)) return SubtargetFeatures(); // both ARMv7-M and R have to support thumb hardware div bool isV7 = false; if (Attributes.hasAttribute(ARMBuildAttrs::CPU_arch)) isV7 = Attributes.getAttributeValue(ARMBuildAttrs::CPU_arch) == ARMBuildAttrs::v7; if (Attributes.hasAttribute(ARMBuildAttrs::CPU_arch_profile)) { switch(Attributes.getAttributeValue(ARMBuildAttrs::CPU_arch_profile)) { case ARMBuildAttrs::ApplicationProfile: Features.AddFeature("aclass"); break; case ARMBuildAttrs::RealTimeProfile: Features.AddFeature("rclass"); if (isV7) Features.AddFeature("hwdiv"); break; case ARMBuildAttrs::MicroControllerProfile: Features.AddFeature("mclass"); if (isV7) Features.AddFeature("hwdiv"); break; } } if (Attributes.hasAttribute(ARMBuildAttrs::THUMB_ISA_use)) { switch(Attributes.getAttributeValue(ARMBuildAttrs::THUMB_ISA_use)) { default: break; case ARMBuildAttrs::Not_Allowed: Features.AddFeature("thumb", false); Features.AddFeature("thumb2", false); break; case ARMBuildAttrs::AllowThumb32: Features.AddFeature("thumb2"); break; } } if (Attributes.hasAttribute(ARMBuildAttrs::FP_arch)) { switch(Attributes.getAttributeValue(ARMBuildAttrs::FP_arch)) { default: break; case ARMBuildAttrs::Not_Allowed: - Features.AddFeature("vfp2d16sp", false); + Features.AddFeature("vfp2sp", false); Features.AddFeature("vfp3d16sp", false); Features.AddFeature("vfp4d16sp", false); break; case ARMBuildAttrs::AllowFPv2: Features.AddFeature("vfp2"); break; case ARMBuildAttrs::AllowFPv3A: case ARMBuildAttrs::AllowFPv3B: Features.AddFeature("vfp3"); break; case ARMBuildAttrs::AllowFPv4A: case ARMBuildAttrs::AllowFPv4B: Features.AddFeature("vfp4"); break; } } if (Attributes.hasAttribute(ARMBuildAttrs::Advanced_SIMD_arch)) { switch(Attributes.getAttributeValue(ARMBuildAttrs::Advanced_SIMD_arch)) { default: break; case ARMBuildAttrs::Not_Allowed: Features.AddFeature("neon", false); Features.AddFeature("fp16", false); break; case ARMBuildAttrs::AllowNeon: Features.AddFeature("neon"); break; case ARMBuildAttrs::AllowNeon2: Features.AddFeature("neon"); Features.AddFeature("fp16"); break; } } if (Attributes.hasAttribute(ARMBuildAttrs::MVE_arch)) { switch(Attributes.getAttributeValue(ARMBuildAttrs::MVE_arch)) { default: break; case ARMBuildAttrs::Not_Allowed: Features.AddFeature("mve", false); Features.AddFeature("mve.fp", false); break; case ARMBuildAttrs::AllowMVEInteger: Features.AddFeature("mve.fp", false); Features.AddFeature("mve"); break; case ARMBuildAttrs::AllowMVEIntegerAndFloat: Features.AddFeature("mve.fp"); break; } } if (Attributes.hasAttribute(ARMBuildAttrs::DIV_use)) { switch(Attributes.getAttributeValue(ARMBuildAttrs::DIV_use)) { default: break; case ARMBuildAttrs::DisallowDIV: Features.AddFeature("hwdiv", false); Features.AddFeature("hwdiv-arm", false); break; case ARMBuildAttrs::AllowDIVExt: Features.AddFeature("hwdiv"); Features.AddFeature("hwdiv-arm"); break; } } return Features; } SubtargetFeatures ELFObjectFileBase::getRISCVFeatures() const { SubtargetFeatures Features; unsigned PlatformFlags = getPlatformFlags(); if (PlatformFlags & ELF::EF_RISCV_RVC) { Features.AddFeature("c"); } return Features; } SubtargetFeatures ELFObjectFileBase::getFeatures() const { switch (getEMachine()) { case ELF::EM_MIPS: return getMIPSFeatures(); case ELF::EM_ARM: return getARMFeatures(); case ELF::EM_RISCV: return getRISCVFeatures(); default: return SubtargetFeatures(); } } // FIXME Encode from a tablegen description or target parser. void ELFObjectFileBase::setARMSubArch(Triple &TheTriple) const { if (TheTriple.getSubArch() != Triple::NoSubArch) return; ARMAttributeParser Attributes; if (Error E = getBuildAttributes(Attributes)) return; std::string Triple; // Default to ARM, but use the triple if it's been set. if (TheTriple.isThumb()) Triple = "thumb"; else Triple = "arm"; if (Attributes.hasAttribute(ARMBuildAttrs::CPU_arch)) { switch(Attributes.getAttributeValue(ARMBuildAttrs::CPU_arch)) { case ARMBuildAttrs::v4: Triple += "v4"; break; case ARMBuildAttrs::v4T: Triple += "v4t"; break; case ARMBuildAttrs::v5T: Triple += "v5t"; break; case ARMBuildAttrs::v5TE: Triple += "v5te"; break; case ARMBuildAttrs::v5TEJ: Triple += "v5tej"; break; case ARMBuildAttrs::v6: Triple += "v6"; break; case ARMBuildAttrs::v6KZ: Triple += "v6kz"; break; case ARMBuildAttrs::v6T2: Triple += "v6t2"; break; case ARMBuildAttrs::v6K: Triple += "v6k"; break; case ARMBuildAttrs::v7: Triple += "v7"; break; case ARMBuildAttrs::v6_M: Triple += "v6m"; break; case ARMBuildAttrs::v6S_M: Triple += "v6sm"; break; case ARMBuildAttrs::v7E_M: Triple += "v7em"; break; } } if (!isLittleEndian()) Triple += "eb"; TheTriple.setArchName(Triple); } std::vector> ELFObjectFileBase::getPltAddresses() const { std::string Err; const auto Triple = makeTriple(); const auto *T = TargetRegistry::lookupTarget(Triple.str(), Err); if (!T) return {}; uint64_t JumpSlotReloc = 0; switch (Triple.getArch()) { case Triple::x86: JumpSlotReloc = ELF::R_386_JUMP_SLOT; break; case Triple::x86_64: JumpSlotReloc = ELF::R_X86_64_JUMP_SLOT; break; case Triple::aarch64: JumpSlotReloc = ELF::R_AARCH64_JUMP_SLOT; break; default: return {}; } std::unique_ptr MII(T->createMCInstrInfo()); std::unique_ptr MIA( T->createMCInstrAnalysis(MII.get())); if (!MIA) return {}; Optional Plt = None, RelaPlt = None, GotPlt = None; for (const SectionRef &Section : sections()) { StringRef Name; if (Section.getName(Name)) continue; if (Name == ".plt") Plt = Section; else if (Name == ".rela.plt" || Name == ".rel.plt") RelaPlt = Section; else if (Name == ".got.plt") GotPlt = Section; } if (!Plt || !RelaPlt || !GotPlt) return {}; Expected PltContents = Plt->getContents(); if (!PltContents) { consumeError(PltContents.takeError()); return {}; } auto PltEntries = MIA->findPltEntries(Plt->getAddress(), arrayRefFromStringRef(*PltContents), GotPlt->getAddress(), Triple); // Build a map from GOT entry virtual address to PLT entry virtual address. DenseMap GotToPlt; for (const auto &Entry : PltEntries) GotToPlt.insert(std::make_pair(Entry.second, Entry.first)); // Find the relocations in the dynamic relocation table that point to // locations in the GOT for which we know the corresponding PLT entry. std::vector> Result; for (const auto &Relocation : RelaPlt->relocations()) { if (Relocation.getType() != JumpSlotReloc) continue; auto PltEntryIter = GotToPlt.find(Relocation.getOffset()); if (PltEntryIter != GotToPlt.end()) Result.push_back(std::make_pair( Relocation.getSymbol()->getRawDataRefImpl(), PltEntryIter->second)); } return Result; } Index: head/contrib/llvm/lib/Support/ARMTargetParser.cpp =================================================================== --- head/contrib/llvm/lib/Support/ARMTargetParser.cpp (revision 354096) +++ head/contrib/llvm/lib/Support/ARMTargetParser.cpp (revision 354097) @@ -1,628 +1,626 @@ //===-- ARMTargetParser - Parser for ARM target features --------*- C++ -*-===// // // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. // See https://llvm.org/LICENSE.txt for license information. // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception // //===----------------------------------------------------------------------===// // // This file implements a target parser to recognise ARM hardware features // such as FPU/CPU/ARCH/extensions and specific support such as HWDIV. // //===----------------------------------------------------------------------===// #include "llvm/Support/ARMTargetParser.h" #include "llvm/ADT/StringSwitch.h" #include using namespace llvm; static StringRef getHWDivSynonym(StringRef HWDiv) { return StringSwitch(HWDiv) .Case("thumb,arm", "arm,thumb") .Default(HWDiv); } // Allows partial match, ex. "v7a" matches "armv7a". ARM::ArchKind ARM::parseArch(StringRef Arch) { Arch = getCanonicalArchName(Arch); StringRef Syn = getArchSynonym(Arch); for (const auto A : ARCHNames) { if (A.getName().endswith(Syn)) return A.ID; } return ArchKind::INVALID; } // Version number (ex. v7 = 7). unsigned ARM::parseArchVersion(StringRef Arch) { Arch = getCanonicalArchName(Arch); switch (parseArch(Arch)) { case ArchKind::ARMV2: case ArchKind::ARMV2A: return 2; case ArchKind::ARMV3: case ArchKind::ARMV3M: return 3; case ArchKind::ARMV4: case ArchKind::ARMV4T: return 4; case ArchKind::ARMV5T: case ArchKind::ARMV5TE: case ArchKind::IWMMXT: case ArchKind::IWMMXT2: case ArchKind::XSCALE: case ArchKind::ARMV5TEJ: return 5; case ArchKind::ARMV6: case ArchKind::ARMV6K: case ArchKind::ARMV6T2: case ArchKind::ARMV6KZ: case ArchKind::ARMV6M: return 6; case ArchKind::ARMV7A: case ArchKind::ARMV7VE: case ArchKind::ARMV7R: case ArchKind::ARMV7M: case ArchKind::ARMV7S: case ArchKind::ARMV7EM: case ArchKind::ARMV7K: return 7; case ArchKind::ARMV8A: case ArchKind::ARMV8_1A: case ArchKind::ARMV8_2A: case ArchKind::ARMV8_3A: case ArchKind::ARMV8_4A: case ArchKind::ARMV8_5A: case ArchKind::ARMV8R: case ArchKind::ARMV8MBaseline: case ArchKind::ARMV8MMainline: case ArchKind::ARMV8_1MMainline: return 8; case ArchKind::INVALID: return 0; } llvm_unreachable("Unhandled architecture"); } // Profile A/R/M ARM::ProfileKind ARM::parseArchProfile(StringRef Arch) { Arch = getCanonicalArchName(Arch); switch (parseArch(Arch)) { case ArchKind::ARMV6M: case ArchKind::ARMV7M: case ArchKind::ARMV7EM: case ArchKind::ARMV8MMainline: case ArchKind::ARMV8MBaseline: case ArchKind::ARMV8_1MMainline: return ProfileKind::M; case ArchKind::ARMV7R: case ArchKind::ARMV8R: return ProfileKind::R; case ArchKind::ARMV7A: case ArchKind::ARMV7VE: case ArchKind::ARMV7K: case ArchKind::ARMV8A: case ArchKind::ARMV8_1A: case ArchKind::ARMV8_2A: case ArchKind::ARMV8_3A: case ArchKind::ARMV8_4A: case ArchKind::ARMV8_5A: return ProfileKind::A; case ArchKind::ARMV2: case ArchKind::ARMV2A: case ArchKind::ARMV3: case ArchKind::ARMV3M: case ArchKind::ARMV4: case ArchKind::ARMV4T: case ArchKind::ARMV5T: case ArchKind::ARMV5TE: case ArchKind::ARMV5TEJ: case ArchKind::ARMV6: case ArchKind::ARMV6K: case ArchKind::ARMV6T2: case ArchKind::ARMV6KZ: case ArchKind::ARMV7S: case ArchKind::IWMMXT: case ArchKind::IWMMXT2: case ArchKind::XSCALE: case ArchKind::INVALID: return ProfileKind::INVALID; } llvm_unreachable("Unhandled architecture"); } StringRef ARM::getArchSynonym(StringRef Arch) { return StringSwitch(Arch) .Case("v5", "v5t") .Case("v5e", "v5te") .Case("v6j", "v6") .Case("v6hl", "v6k") .Cases("v6m", "v6sm", "v6s-m", "v6-m") .Cases("v6z", "v6zk", "v6kz") .Cases("v7", "v7a", "v7hl", "v7l", "v7-a") .Case("v7r", "v7-r") .Case("v7m", "v7-m") .Case("v7em", "v7e-m") .Cases("v8", "v8a", "v8l", "aarch64", "arm64", "v8-a") .Case("v8.1a", "v8.1-a") .Case("v8.2a", "v8.2-a") .Case("v8.3a", "v8.3-a") .Case("v8.4a", "v8.4-a") .Case("v8.5a", "v8.5-a") .Case("v8r", "v8-r") .Case("v8m.base", "v8-m.base") .Case("v8m.main", "v8-m.main") .Case("v8.1m.main", "v8.1-m.main") .Default(Arch); } bool ARM::getFPUFeatures(unsigned FPUKind, std::vector &Features) { if (FPUKind >= FK_LAST || FPUKind == FK_INVALID) return false; static const struct FPUFeatureNameInfo { const char *PlusName, *MinusName; FPUVersion MinVersion; FPURestriction MaxRestriction; } FPUFeatureInfoList[] = { // We have to specify the + and - versions of the name in full so // that we can return them as static StringRefs. // // Also, the SubtargetFeatures ending in just "sp" are listed here // under FPURestriction::None, which is the only FPURestriction in // which they would be valid (since FPURestriction::SP doesn't // exist). {"+fpregs", "-fpregs", FPUVersion::VFPV2, FPURestriction::SP_D16}, - {"+vfp2", "-vfp2", FPUVersion::VFPV2, FPURestriction::None}, - {"+vfp2d16", "-vfp2d16", FPUVersion::VFPV2, FPURestriction::D16}, - {"+vfp2d16sp", "-vfp2d16sp", FPUVersion::VFPV2, FPURestriction::SP_D16}, - {"+vfp2sp", "-vfp2sp", FPUVersion::VFPV2, FPURestriction::None}, + {"+vfp2", "-vfp2", FPUVersion::VFPV2, FPURestriction::D16}, + {"+vfp2sp", "-vfp2sp", FPUVersion::VFPV2, FPURestriction::SP_D16}, {"+vfp3", "-vfp3", FPUVersion::VFPV3, FPURestriction::None}, {"+vfp3d16", "-vfp3d16", FPUVersion::VFPV3, FPURestriction::D16}, {"+vfp3d16sp", "-vfp3d16sp", FPUVersion::VFPV3, FPURestriction::SP_D16}, {"+vfp3sp", "-vfp3sp", FPUVersion::VFPV3, FPURestriction::None}, {"+fp16", "-fp16", FPUVersion::VFPV3_FP16, FPURestriction::SP_D16}, {"+vfp4", "-vfp4", FPUVersion::VFPV4, FPURestriction::None}, {"+vfp4d16", "-vfp4d16", FPUVersion::VFPV4, FPURestriction::D16}, {"+vfp4d16sp", "-vfp4d16sp", FPUVersion::VFPV4, FPURestriction::SP_D16}, {"+vfp4sp", "-vfp4sp", FPUVersion::VFPV4, FPURestriction::None}, {"+fp-armv8", "-fp-armv8", FPUVersion::VFPV5, FPURestriction::None}, {"+fp-armv8d16", "-fp-armv8d16", FPUVersion::VFPV5, FPURestriction::D16}, {"+fp-armv8d16sp", "-fp-armv8d16sp", FPUVersion::VFPV5, FPURestriction::SP_D16}, {"+fp-armv8sp", "-fp-armv8sp", FPUVersion::VFPV5, FPURestriction::None}, {"+fullfp16", "-fullfp16", FPUVersion::VFPV5_FULLFP16, FPURestriction::SP_D16}, {"+fp64", "-fp64", FPUVersion::VFPV2, FPURestriction::D16}, - {"+d32", "-d32", FPUVersion::VFPV2, FPURestriction::None}, + {"+d32", "-d32", FPUVersion::VFPV3, FPURestriction::None}, }; for (const auto &Info: FPUFeatureInfoList) { if (FPUNames[FPUKind].FPUVer >= Info.MinVersion && FPUNames[FPUKind].Restriction <= Info.MaxRestriction) Features.push_back(Info.PlusName); else Features.push_back(Info.MinusName); } static const struct NeonFeatureNameInfo { const char *PlusName, *MinusName; NeonSupportLevel MinSupportLevel; } NeonFeatureInfoList[] = { {"+neon", "-neon", NeonSupportLevel::Neon}, {"+crypto", "-crypto", NeonSupportLevel::Crypto}, }; for (const auto &Info: NeonFeatureInfoList) { if (FPUNames[FPUKind].NeonSupport >= Info.MinSupportLevel) Features.push_back(Info.PlusName); else Features.push_back(Info.MinusName); } return true; } // Little/Big endian ARM::EndianKind ARM::parseArchEndian(StringRef Arch) { if (Arch.startswith("armeb") || Arch.startswith("thumbeb") || Arch.startswith("aarch64_be")) return EndianKind::BIG; if (Arch.startswith("arm") || Arch.startswith("thumb")) { if (Arch.endswith("eb")) return EndianKind::BIG; else return EndianKind::LITTLE; } if (Arch.startswith("aarch64") || Arch.startswith("aarch64_32")) return EndianKind::LITTLE; return EndianKind::INVALID; } // ARM, Thumb, AArch64 ARM::ISAKind ARM::parseArchISA(StringRef Arch) { return StringSwitch(Arch) .StartsWith("aarch64", ISAKind::AARCH64) .StartsWith("arm64", ISAKind::AARCH64) .StartsWith("thumb", ISAKind::THUMB) .StartsWith("arm", ISAKind::ARM) .Default(ISAKind::INVALID); } unsigned ARM::parseFPU(StringRef FPU) { StringRef Syn = getFPUSynonym(FPU); for (const auto F : FPUNames) { if (Syn == F.getName()) return F.ID; } return FK_INVALID; } ARM::NeonSupportLevel ARM::getFPUNeonSupportLevel(unsigned FPUKind) { if (FPUKind >= FK_LAST) return NeonSupportLevel::None; return FPUNames[FPUKind].NeonSupport; } // MArch is expected to be of the form (arm|thumb)?(eb)?(v.+)?(eb)?, but // (iwmmxt|xscale)(eb)? is also permitted. If the former, return // "v.+", if the latter, return unmodified string, minus 'eb'. // If invalid, return empty string. StringRef ARM::getCanonicalArchName(StringRef Arch) { size_t offset = StringRef::npos; StringRef A = Arch; StringRef Error = ""; // Begins with "arm" / "thumb", move past it. if (A.startswith("arm64_32")) offset = 8; else if (A.startswith("arm64")) offset = 5; else if (A.startswith("aarch64_32")) offset = 10; else if (A.startswith("arm")) offset = 3; else if (A.startswith("thumb")) offset = 5; else if (A.startswith("aarch64")) { offset = 7; // AArch64 uses "_be", not "eb" suffix. if (A.find("eb") != StringRef::npos) return Error; if (A.substr(offset, 3) == "_be") offset += 3; } // Ex. "armebv7", move past the "eb". if (offset != StringRef::npos && A.substr(offset, 2) == "eb") offset += 2; // Or, if it ends with eb ("armv7eb"), chop it off. else if (A.endswith("eb")) A = A.substr(0, A.size() - 2); // Trim the head if (offset != StringRef::npos) A = A.substr(offset); // Empty string means offset reached the end, which means it's valid. if (A.empty()) return Arch; // Only match non-marketing names if (offset != StringRef::npos) { // Must start with 'vN'. if (A.size() >= 2 && (A[0] != 'v' || !std::isdigit(A[1]))) return Error; // Can't have an extra 'eb'. if (A.find("eb") != StringRef::npos) return Error; } // Arch will either be a 'v' name (v7a) or a marketing name (xscale). return A; } StringRef ARM::getFPUSynonym(StringRef FPU) { return StringSwitch(FPU) .Cases("fpa", "fpe2", "fpe3", "maverick", "invalid") // Unsupported .Case("vfp2", "vfpv2") .Case("vfp3", "vfpv3") .Case("vfp4", "vfpv4") .Case("vfp3-d16", "vfpv3-d16") .Case("vfp4-d16", "vfpv4-d16") .Cases("fp4-sp-d16", "vfpv4-sp-d16", "fpv4-sp-d16") .Cases("fp4-dp-d16", "fpv4-dp-d16", "vfpv4-d16") .Case("fp5-sp-d16", "fpv5-sp-d16") .Cases("fp5-dp-d16", "fpv5-dp-d16", "fpv5-d16") // FIXME: Clang uses it, but it's bogus, since neon defaults to vfpv3. .Case("neon-vfpv3", "neon") .Default(FPU); } StringRef ARM::getFPUName(unsigned FPUKind) { if (FPUKind >= FK_LAST) return StringRef(); return FPUNames[FPUKind].getName(); } ARM::FPUVersion ARM::getFPUVersion(unsigned FPUKind) { if (FPUKind >= FK_LAST) return FPUVersion::NONE; return FPUNames[FPUKind].FPUVer; } ARM::FPURestriction ARM::getFPURestriction(unsigned FPUKind) { if (FPUKind >= FK_LAST) return FPURestriction::None; return FPUNames[FPUKind].Restriction; } unsigned ARM::getDefaultFPU(StringRef CPU, ARM::ArchKind AK) { if (CPU == "generic") return ARM::ARCHNames[static_cast(AK)].DefaultFPU; return StringSwitch(CPU) #define ARM_CPU_NAME(NAME, ID, DEFAULT_FPU, IS_DEFAULT, DEFAULT_EXT) \ .Case(NAME, DEFAULT_FPU) #include "llvm/Support/ARMTargetParser.def" .Default(ARM::FK_INVALID); } unsigned ARM::getDefaultExtensions(StringRef CPU, ARM::ArchKind AK) { if (CPU == "generic") return ARM::ARCHNames[static_cast(AK)].ArchBaseExtensions; return StringSwitch(CPU) #define ARM_CPU_NAME(NAME, ID, DEFAULT_FPU, IS_DEFAULT, DEFAULT_EXT) \ .Case(NAME, \ ARCHNames[static_cast(ArchKind::ID)].ArchBaseExtensions | \ DEFAULT_EXT) #include "llvm/Support/ARMTargetParser.def" .Default(ARM::AEK_INVALID); } bool ARM::getHWDivFeatures(unsigned HWDivKind, std::vector &Features) { if (HWDivKind == AEK_INVALID) return false; if (HWDivKind & AEK_HWDIVARM) Features.push_back("+hwdiv-arm"); else Features.push_back("-hwdiv-arm"); if (HWDivKind & AEK_HWDIVTHUMB) Features.push_back("+hwdiv"); else Features.push_back("-hwdiv"); return true; } bool ARM::getExtensionFeatures(unsigned Extensions, std::vector &Features) { if (Extensions == AEK_INVALID) return false; for (const auto AE : ARCHExtNames) { if ((Extensions & AE.ID) == AE.ID && AE.Feature) Features.push_back(AE.Feature); else if (AE.NegFeature) Features.push_back(AE.NegFeature); } return getHWDivFeatures(Extensions, Features); } StringRef ARM::getArchName(ARM::ArchKind AK) { return ARCHNames[static_cast(AK)].getName(); } StringRef ARM::getCPUAttr(ARM::ArchKind AK) { return ARCHNames[static_cast(AK)].getCPUAttr(); } StringRef ARM::getSubArch(ARM::ArchKind AK) { return ARCHNames[static_cast(AK)].getSubArch(); } unsigned ARM::getArchAttr(ARM::ArchKind AK) { return ARCHNames[static_cast(AK)].ArchAttr; } StringRef ARM::getArchExtName(unsigned ArchExtKind) { for (const auto AE : ARCHExtNames) { if (ArchExtKind == AE.ID) return AE.getName(); } return StringRef(); } static bool stripNegationPrefix(StringRef &Name) { if (Name.startswith("no")) { Name = Name.substr(2); return true; } return false; } StringRef ARM::getArchExtFeature(StringRef ArchExt) { bool Negated = stripNegationPrefix(ArchExt); for (const auto AE : ARCHExtNames) { if (AE.Feature && ArchExt == AE.getName()) return StringRef(Negated ? AE.NegFeature : AE.Feature); } return StringRef(); } static unsigned findDoublePrecisionFPU(unsigned InputFPUKind) { const ARM::FPUName &InputFPU = ARM::FPUNames[InputFPUKind]; // If the input FPU already supports double-precision, then there // isn't any different FPU we can return here. // // The current available FPURestriction values are None (no // restriction), D16 (only 16 d-regs) and SP_D16 (16 d-regs // and single precision only); there's no value representing // SP restriction without D16. So this test just means 'is it // SP only?'. if (InputFPU.Restriction != ARM::FPURestriction::SP_D16) return ARM::FK_INVALID; // Otherwise, look for an FPU entry with all the same fields, except // that SP_D16 has been replaced with just D16, representing adding // double precision and not changing anything else. for (const ARM::FPUName &CandidateFPU : ARM::FPUNames) { if (CandidateFPU.FPUVer == InputFPU.FPUVer && CandidateFPU.NeonSupport == InputFPU.NeonSupport && CandidateFPU.Restriction == ARM::FPURestriction::D16) { return CandidateFPU.ID; } } // nothing found return ARM::FK_INVALID; } static unsigned getAEKID(StringRef ArchExtName) { for (const auto AE : ARM::ARCHExtNames) if (AE.getName() == ArchExtName) return AE.ID; return ARM::AEK_INVALID; } bool ARM::appendArchExtFeatures( StringRef CPU, ARM::ArchKind AK, StringRef ArchExt, std::vector &Features) { size_t StartingNumFeatures = Features.size(); const bool Negated = stripNegationPrefix(ArchExt); unsigned ID = getAEKID(ArchExt); if (ID == AEK_INVALID) return false; for (const auto AE : ARCHExtNames) { if (Negated && (AE.ID & ID) == ID && AE.NegFeature) Features.push_back(AE.NegFeature); else if (AE.ID == ID && AE.Feature) Features.push_back(AE.Feature); } if (CPU == "") CPU = "generic"; if (ArchExt == "fp" || ArchExt == "fp.dp") { unsigned FPUKind; if (ArchExt == "fp.dp") { if (Negated) { Features.push_back("-fp64"); return true; } FPUKind = findDoublePrecisionFPU(getDefaultFPU(CPU, AK)); } else if (Negated) { FPUKind = ARM::FK_NONE; } else { FPUKind = getDefaultFPU(CPU, AK); } return ARM::getFPUFeatures(FPUKind, Features); } return StartingNumFeatures != Features.size(); } StringRef ARM::getHWDivName(unsigned HWDivKind) { for (const auto D : HWDivNames) { if (HWDivKind == D.ID) return D.getName(); } return StringRef(); } StringRef ARM::getDefaultCPU(StringRef Arch) { ArchKind AK = parseArch(Arch); if (AK == ArchKind::INVALID) return StringRef(); // Look for multiple AKs to find the default for pair AK+Name. for (const auto CPU : CPUNames) { if (CPU.ArchID == AK && CPU.Default) return CPU.getName(); } // If we can't find a default then target the architecture instead return "generic"; } unsigned ARM::parseHWDiv(StringRef HWDiv) { StringRef Syn = getHWDivSynonym(HWDiv); for (const auto D : HWDivNames) { if (Syn == D.getName()) return D.ID; } return AEK_INVALID; } unsigned ARM::parseArchExt(StringRef ArchExt) { for (const auto A : ARCHExtNames) { if (ArchExt == A.getName()) return A.ID; } return AEK_INVALID; } ARM::ArchKind ARM::parseCPUArch(StringRef CPU) { for (const auto C : CPUNames) { if (CPU == C.getName()) return C.ArchID; } return ArchKind::INVALID; } void ARM::fillValidCPUArchList(SmallVectorImpl &Values) { for (const CpuNames &Arch : CPUNames) { if (Arch.ArchID != ArchKind::INVALID) Values.push_back(Arch.getName()); } } StringRef ARM::computeDefaultTargetABI(const Triple &TT, StringRef CPU) { StringRef ArchName = CPU.empty() ? TT.getArchName() : getArchName(parseCPUArch(CPU)); if (TT.isOSBinFormatMachO()) { if (TT.getEnvironment() == Triple::EABI || TT.getOS() == Triple::UnknownOS || parseArchProfile(ArchName) == ProfileKind::M) return "aapcs"; if (TT.isWatchABI()) return "aapcs16"; return "apcs-gnu"; } else if (TT.isOSWindows()) // FIXME: this is invalid for WindowsCE. return "aapcs"; // Select the default based on the platform. switch (TT.getEnvironment()) { case Triple::Android: case Triple::GNUEABI: case Triple::GNUEABIHF: case Triple::MuslEABI: case Triple::MuslEABIHF: return "aapcs-linux"; case Triple::EABIHF: case Triple::EABI: return "aapcs"; default: if (TT.isOSNetBSD()) return "apcs-gnu"; if (TT.isOSOpenBSD()) return "aapcs-linux"; return "aapcs"; } } Index: head/contrib/llvm/lib/Target/ARM/ARM.td =================================================================== --- head/contrib/llvm/lib/Target/ARM/ARM.td (revision 354096) +++ head/contrib/llvm/lib/Target/ARM/ARM.td (revision 354097) @@ -1,1238 +1,1248 @@ //===-- ARM.td - Describe the ARM Target Machine -----------*- tablegen -*-===// // // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. // See https://llvm.org/LICENSE.txt for license information. // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception // //===----------------------------------------------------------------------===// // // //===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===// // Target-independent interfaces which we are implementing //===----------------------------------------------------------------------===// include "llvm/Target/Target.td" //===----------------------------------------------------------------------===// // ARM Subtarget state. // def ModeThumb : SubtargetFeature<"thumb-mode", "InThumbMode", "true", "Thumb mode">; def ModeSoftFloat : SubtargetFeature<"soft-float","UseSoftFloat", "true", "Use software floating " "point features.">; //===----------------------------------------------------------------------===// // ARM Subtarget features. // // Floating Point, HW Division and Neon Support // FP loads/stores/moves, shared between VFP and MVE (even in the integer-only // version). def FeatureFPRegs : SubtargetFeature<"fpregs", "HasFPRegs", "true", "Enable FP registers">; // 16-bit FP loads/stores/moves, shared between VFP (with the v8.2A FP16 // extension) and MVE (even in the integer-only version). def FeatureFPRegs16 : SubtargetFeature<"fpregs16", "HasFPRegs16", "true", "Enable 16-bit FP registers", [FeatureFPRegs]>; def FeatureFPRegs64 : SubtargetFeature<"fpregs64", "HasFPRegs64", "true", "Enable 64-bit FP registers", [FeatureFPRegs]>; def FeatureFP64 : SubtargetFeature<"fp64", "HasFP64", "true", "Floating point unit supports " "double precision", [FeatureFPRegs64]>; def FeatureD32 : SubtargetFeature<"d32", "HasD32", "true", "Extend FP to 32 double registers">; multiclass VFPver prev = [], - list otherimplies = []> { + list prev, + list otherimplies, + list vfp2prev = []> { def _D16_SP: SubtargetFeature< name#"d16sp", query#"D16SP", "true", description#" with only 16 d-registers and no double precision", - !foreach(v, prev, !cast(v # "_D16_SP")) # otherimplies>; + !foreach(v, prev, !cast(v # "_D16_SP")) # + !foreach(v, vfp2prev, !cast(v # "_SP")) # + otherimplies>; def _SP: SubtargetFeature< name#"sp", query#"SP", "true", description#" with no double precision", !foreach(v, prev, !cast(v # "_SP")) # otherimplies # [FeatureD32, !cast(NAME # "_D16_SP")]>; def _D16: SubtargetFeature< name#"d16", query#"D16", "true", description#" with only 16 d-registers", !foreach(v, prev, !cast(v # "_D16")) # + vfp2prev # otherimplies # [FeatureFP64, !cast(NAME # "_D16_SP")]>; def "": SubtargetFeature< name, query, "true", description, prev # otherimplies # [ !cast(NAME # "_D16"), !cast(NAME # "_SP")]>; } -defm FeatureVFP2: VFPver<"vfp2", "HasVFPv2", "Enable VFP2 instructions", - [], [FeatureFPRegs]>; +def FeatureVFP2_SP : SubtargetFeature<"vfp2sp", "HasVFPv2SP", "true", + "Enable VFP2 instructions with " + "no double precision", + [FeatureFPRegs]>; +def FeatureVFP2 : SubtargetFeature<"vfp2", "HasVFPv2", "true", + "Enable VFP2 instructions", + [FeatureFP64, FeatureVFP2_SP]>; + defm FeatureVFP3: VFPver<"vfp3", "HasVFPv3", "Enable VFP3 instructions", - [FeatureVFP2]>; + [], [], [FeatureVFP2]>; def FeatureNEON : SubtargetFeature<"neon", "HasNEON", "true", "Enable NEON instructions", [FeatureVFP3]>; def FeatureFP16 : SubtargetFeature<"fp16", "HasFP16", "true", "Enable half-precision " "floating point">; defm FeatureVFP4: VFPver<"vfp4", "HasVFPv4", "Enable VFP4 instructions", [FeatureVFP3], [FeatureFP16]>; defm FeatureFPARMv8: VFPver<"fp-armv8", "HasFPARMv8", "Enable ARMv8 FP", - [FeatureVFP4]>; + [FeatureVFP4], []>; def FeatureFullFP16 : SubtargetFeature<"fullfp16", "HasFullFP16", "true", "Enable full half-precision " "floating point", [FeatureFPARMv8_D16_SP, FeatureFPRegs16]>; def FeatureFP16FML : SubtargetFeature<"fp16fml", "HasFP16FML", "true", "Enable full half-precision " "floating point fml instructions", [FeatureFullFP16]>; def FeatureHWDivThumb : SubtargetFeature<"hwdiv", "HasHardwareDivideInThumb", "true", "Enable divide instructions in Thumb">; def FeatureHWDivARM : SubtargetFeature<"hwdiv-arm", "HasHardwareDivideInARM", "true", "Enable divide instructions in ARM mode">; // Atomic Support def FeatureDB : SubtargetFeature<"db", "HasDataBarrier", "true", "Has data barrier (dmb/dsb) instructions">; def FeatureV7Clrex : SubtargetFeature<"v7clrex", "HasV7Clrex", "true", "Has v7 clrex instruction">; def FeatureDFB : SubtargetFeature<"dfb", "HasFullDataBarrier", "true", "Has full data barrier (dfb) instruction">; def FeatureAcquireRelease : SubtargetFeature<"acquire-release", "HasAcquireRelease", "true", "Has v8 acquire/release (lda/ldaex " " etc) instructions">; def FeatureSlowFPBrcc : SubtargetFeature<"slow-fp-brcc", "SlowFPBrcc", "true", "FP compare + branch is slow">; def FeaturePerfMon : SubtargetFeature<"perfmon", "HasPerfMon", "true", "Enable support for Performance " "Monitor extensions">; // TrustZone Security Extensions def FeatureTrustZone : SubtargetFeature<"trustzone", "HasTrustZone", "true", "Enable support for TrustZone " "security extensions">; def Feature8MSecExt : SubtargetFeature<"8msecext", "Has8MSecExt", "true", "Enable support for ARMv8-M " "Security Extensions">; def FeatureSHA2 : SubtargetFeature<"sha2", "HasSHA2", "true", "Enable SHA1 and SHA256 support", [FeatureNEON]>; def FeatureAES : SubtargetFeature<"aes", "HasAES", "true", "Enable AES support", [FeatureNEON]>; def FeatureCrypto : SubtargetFeature<"crypto", "HasCrypto", "true", "Enable support for " "Cryptography extensions", [FeatureNEON, FeatureSHA2, FeatureAES]>; def FeatureCRC : SubtargetFeature<"crc", "HasCRC", "true", "Enable support for CRC instructions">; def FeatureDotProd : SubtargetFeature<"dotprod", "HasDotProd", "true", "Enable support for dot product instructions", [FeatureNEON]>; // Not to be confused with FeatureHasRetAddrStack (return address stack) def FeatureRAS : SubtargetFeature<"ras", "HasRAS", "true", "Enable Reliability, Availability " "and Serviceability extensions">; // Fast computation of non-negative address offsets def FeatureFPAO : SubtargetFeature<"fpao", "HasFPAO", "true", "Enable fast computation of " "positive address offsets">; // Fast execution of AES crypto operations def FeatureFuseAES : SubtargetFeature<"fuse-aes", "HasFuseAES", "true", "CPU fuses AES crypto operations">; // Fast execution of bottom and top halves of literal generation def FeatureFuseLiterals : SubtargetFeature<"fuse-literals", "HasFuseLiterals", "true", "CPU fuses literal generation operations">; // The way of reading thread pointer def FeatureReadTp : SubtargetFeature<"read-tp-hard", "ReadTPHard", "true", "Reading thread pointer from register">; // Cyclone can zero VFP registers in 0 cycles. def FeatureZCZeroing : SubtargetFeature<"zcz", "HasZeroCycleZeroing", "true", "Has zero-cycle zeroing instructions">; // Whether it is profitable to unpredicate certain instructions during if-conversion def FeatureProfUnpredicate : SubtargetFeature<"prof-unpr", "IsProfitableToUnpredicate", "true", "Is profitable to unpredicate">; // Some targets (e.g. Swift) have microcoded VGETLNi32. def FeatureSlowVGETLNi32 : SubtargetFeature<"slow-vgetlni32", "HasSlowVGETLNi32", "true", "Has slow VGETLNi32 - prefer VMOV">; // Some targets (e.g. Swift) have microcoded VDUP32. def FeatureSlowVDUP32 : SubtargetFeature<"slow-vdup32", "HasSlowVDUP32", "true", "Has slow VDUP32 - prefer VMOV">; // Some targets (e.g. Cortex-A9) prefer VMOVSR to VMOVDRR even when using NEON // for scalar FP, as this allows more effective execution domain optimization. def FeaturePreferVMOVSR : SubtargetFeature<"prefer-vmovsr", "PreferVMOVSR", "true", "Prefer VMOVSR">; // Swift has ISHST barriers compatible with Atomic Release semantics but weaker // than ISH def FeaturePrefISHSTBarrier : SubtargetFeature<"prefer-ishst", "PreferISHST", "true", "Prefer ISHST barriers">; // Some targets (e.g. Cortex-A9) have muxed AGU and NEON/FPU. def FeatureMuxedUnits : SubtargetFeature<"muxed-units", "HasMuxedUnits", "true", "Has muxed AGU and NEON/FPU">; // Whether VLDM/VSTM starting with odd register number need more microops // than single VLDRS def FeatureSlowOddRegister : SubtargetFeature<"slow-odd-reg", "SlowOddRegister", "true", "VLDM/VSTM starting " "with an odd register is slow">; // Some targets have a renaming dependency when loading into D subregisters. def FeatureSlowLoadDSubreg : SubtargetFeature<"slow-load-D-subreg", "SlowLoadDSubregister", "true", "Loading into D subregs is slow">; def FeatureUseWideStrideVFP : SubtargetFeature<"wide-stride-vfp", "UseWideStrideVFP", "true", "Use a wide stride when allocating VFP registers">; // Some targets (e.g. Cortex-A15) never want VMOVS to be widened to VMOVD. def FeatureDontWidenVMOVS : SubtargetFeature<"dont-widen-vmovs", "DontWidenVMOVS", "true", "Don't widen VMOVS to VMOVD">; // Some targets (e.g. Cortex-A15) prefer to avoid mixing operations on different // VFP register widths. def FeatureSplatVFPToNeon : SubtargetFeature<"splat-vfp-neon", "SplatVFPToNeon", "true", "Splat register from VFP to NEON", [FeatureDontWidenVMOVS]>; // Whether or not it is profitable to expand VFP/NEON MLA/MLS instructions. def FeatureExpandMLx : SubtargetFeature<"expand-fp-mlx", "ExpandMLx", "true", "Expand VFP/NEON MLA/MLS instructions">; // Some targets have special RAW hazards for VFP/NEON VMLA/VMLS. def FeatureHasVMLxHazards : SubtargetFeature<"vmlx-hazards", "HasVMLxHazards", "true", "Has VMLx hazards">; // Some targets (e.g. Cortex-A9) want to convert VMOVRS, VMOVSR and VMOVS from // VFP to NEON, as an execution domain optimization. def FeatureNEONForFPMovs : SubtargetFeature<"neon-fpmovs", "UseNEONForFPMovs", "true", "Convert VMOVSR, VMOVRS, " "VMOVS to NEON">; // Some processors benefit from using NEON instructions for scalar // single-precision FP operations. This affects instruction selection and should // only be enabled if the handling of denormals is not important. def FeatureNEONForFP : SubtargetFeature<"neonfp", "UseNEONForSinglePrecisionFP", "true", "Use NEON for single precision FP">; // On some processors, VLDn instructions that access unaligned data take one // extra cycle. Take that into account when computing operand latencies. def FeatureCheckVLDnAlign : SubtargetFeature<"vldn-align", "CheckVLDnAlign", "true", "Check for VLDn unaligned access">; // Some processors have a nonpipelined VFP coprocessor. def FeatureNonpipelinedVFP : SubtargetFeature<"nonpipelined-vfp", "NonpipelinedVFP", "true", "VFP instructions are not pipelined">; // Some processors have FP multiply-accumulate instructions that don't // play nicely with other VFP / NEON instructions, and it's generally better // to just not use them. def FeatureHasSlowFPVMLx : SubtargetFeature<"slowfpvmlx", "SlowFPVMLx", "true", "Disable VFP / NEON MAC instructions">; // Cortex-A8 / A9 Advanced SIMD has multiplier accumulator forwarding. def FeatureVMLxForwarding : SubtargetFeature<"vmlx-forwarding", "HasVMLxForwarding", "true", "Has multiplier accumulator forwarding">; // Disable 32-bit to 16-bit narrowing for experimentation. def FeaturePref32BitThumb : SubtargetFeature<"32bit", "Pref32BitThumb", "true", "Prefer 32-bit Thumb instrs">; def FeaturePrefLoopAlign32 : SubtargetFeature<"loop-align", "PrefLoopAlignment","2", "Prefer 32-bit alignment for loops">; /// Some instructions update CPSR partially, which can add false dependency for /// out-of-order implementation, e.g. Cortex-A9, unless each individual bit is /// mapped to a separate physical register. Avoid partial CPSR update for these /// processors. def FeatureAvoidPartialCPSR : SubtargetFeature<"avoid-partial-cpsr", "AvoidCPSRPartialUpdate", "true", "Avoid CPSR partial update for OOO execution">; /// Disable +1 predication cost for instructions updating CPSR. /// Enabled for Cortex-A57. def FeatureCheapPredicableCPSR : SubtargetFeature<"cheap-predicable-cpsr", "CheapPredicableCPSRDef", "true", "Disable +1 predication cost for instructions updating CPSR">; def FeatureAvoidMOVsShOp : SubtargetFeature<"avoid-movs-shop", "AvoidMOVsShifterOperand", "true", "Avoid movs instructions with " "shifter operand">; // Some processors perform return stack prediction. CodeGen should avoid issue // "normal" call instructions to callees which do not return. def FeatureHasRetAddrStack : SubtargetFeature<"ret-addr-stack", "HasRetAddrStack", "true", "Has return address stack">; // Some processors have no branch predictor, which changes the expected cost of // taking a branch which affects the choice of whether to use predicated // instructions. def FeatureHasNoBranchPredictor : SubtargetFeature<"no-branch-predictor", "HasBranchPredictor", "false", "Has no branch predictor">; /// DSP extension. def FeatureDSP : SubtargetFeature<"dsp", "HasDSP", "true", "Supports DSP instructions in " "ARM and/or Thumb2">; // Multiprocessing extension. def FeatureMP : SubtargetFeature<"mp", "HasMPExtension", "true", "Supports Multiprocessing extension">; // Virtualization extension - requires HW divide (ARMv7-AR ARMARM - 4.4.8). def FeatureVirtualization : SubtargetFeature<"virtualization", "HasVirtualization", "true", "Supports Virtualization extension", [FeatureHWDivThumb, FeatureHWDivARM]>; // Special TRAP encoding for NaCl, which looks like a TRAP in Thumb too. // See ARMInstrInfo.td for details. def FeatureNaClTrap : SubtargetFeature<"nacl-trap", "UseNaClTrap", "true", "NaCl trap">; def FeatureStrictAlign : SubtargetFeature<"strict-align", "StrictAlign", "true", "Disallow all unaligned memory " "access">; def FeatureLongCalls : SubtargetFeature<"long-calls", "GenLongCalls", "true", "Generate calls via indirect call " "instructions">; def FeatureExecuteOnly : SubtargetFeature<"execute-only", "GenExecuteOnly", "true", "Enable the generation of " "execute only code.">; def FeatureReserveR9 : SubtargetFeature<"reserve-r9", "ReserveR9", "true", "Reserve R9, making it unavailable" " as GPR">; def FeatureNoMovt : SubtargetFeature<"no-movt", "NoMovt", "true", "Don't use movt/movw pairs for " "32-bit imms">; def FeatureNoNegativeImmediates : SubtargetFeature<"no-neg-immediates", "NegativeImmediates", "false", "Convert immediates and instructions " "to their negated or complemented " "equivalent when the immediate does " "not fit in the encoding.">; // Use the MachineScheduler for instruction scheduling for the subtarget. def FeatureUseMISched: SubtargetFeature<"use-misched", "UseMISched", "true", "Use the MachineScheduler">; def FeatureNoPostRASched : SubtargetFeature<"disable-postra-scheduler", "DisablePostRAScheduler", "true", "Don't schedule again after register allocation">; // Enable use of alias analysis during code generation def FeatureUseAA : SubtargetFeature<"use-aa", "UseAA", "true", "Use alias analysis during codegen">; // Armv8.5-A extensions def FeatureSB : SubtargetFeature<"sb", "HasSB", "true", "Enable v8.5a Speculation Barrier" >; // Armv8.1-M extensions def FeatureLOB : SubtargetFeature<"lob", "HasLOB", "true", "Enable Low Overhead Branch " "extensions">; //===----------------------------------------------------------------------===// // ARM architecture class // // A-series ISA def FeatureAClass : SubtargetFeature<"aclass", "ARMProcClass", "AClass", "Is application profile ('A' series)">; // R-series ISA def FeatureRClass : SubtargetFeature<"rclass", "ARMProcClass", "RClass", "Is realtime profile ('R' series)">; // M-series ISA def FeatureMClass : SubtargetFeature<"mclass", "ARMProcClass", "MClass", "Is microcontroller profile ('M' series)">; def FeatureThumb2 : SubtargetFeature<"thumb2", "HasThumb2", "true", "Enable Thumb2 instructions">; def FeatureNoARM : SubtargetFeature<"noarm", "NoARM", "true", "Does not support ARM mode execution">; //===----------------------------------------------------------------------===// // ARM ISAa. // def HasV4TOps : SubtargetFeature<"v4t", "HasV4TOps", "true", "Support ARM v4T instructions">; def HasV5TOps : SubtargetFeature<"v5t", "HasV5TOps", "true", "Support ARM v5T instructions", [HasV4TOps]>; def HasV5TEOps : SubtargetFeature<"v5te", "HasV5TEOps", "true", "Support ARM v5TE, v5TEj, and " "v5TExp instructions", [HasV5TOps]>; def HasV6Ops : SubtargetFeature<"v6", "HasV6Ops", "true", "Support ARM v6 instructions", [HasV5TEOps]>; def HasV6MOps : SubtargetFeature<"v6m", "HasV6MOps", "true", "Support ARM v6M instructions", [HasV6Ops]>; def HasV8MBaselineOps : SubtargetFeature<"v8m", "HasV8MBaselineOps", "true", "Support ARM v8M Baseline instructions", [HasV6MOps]>; def HasV6KOps : SubtargetFeature<"v6k", "HasV6KOps", "true", "Support ARM v6k instructions", [HasV6Ops]>; def HasV6T2Ops : SubtargetFeature<"v6t2", "HasV6T2Ops", "true", "Support ARM v6t2 instructions", [HasV8MBaselineOps, HasV6KOps, FeatureThumb2]>; def HasV7Ops : SubtargetFeature<"v7", "HasV7Ops", "true", "Support ARM v7 instructions", [HasV6T2Ops, FeaturePerfMon, FeatureV7Clrex]>; def HasV8MMainlineOps : SubtargetFeature<"v8m.main", "HasV8MMainlineOps", "true", "Support ARM v8M Mainline instructions", [HasV7Ops]>; def HasV8Ops : SubtargetFeature<"v8", "HasV8Ops", "true", "Support ARM v8 instructions", [HasV7Ops, FeatureAcquireRelease]>; def HasV8_1aOps : SubtargetFeature<"v8.1a", "HasV8_1aOps", "true", "Support ARM v8.1a instructions", [HasV8Ops]>; def HasV8_2aOps : SubtargetFeature<"v8.2a", "HasV8_2aOps", "true", "Support ARM v8.2a instructions", [HasV8_1aOps]>; def HasV8_3aOps : SubtargetFeature<"v8.3a", "HasV8_3aOps", "true", "Support ARM v8.3a instructions", [HasV8_2aOps]>; def HasV8_4aOps : SubtargetFeature<"v8.4a", "HasV8_4aOps", "true", "Support ARM v8.4a instructions", [HasV8_3aOps, FeatureDotProd]>; def HasV8_5aOps : SubtargetFeature<"v8.5a", "HasV8_5aOps", "true", "Support ARM v8.5a instructions", [HasV8_4aOps, FeatureSB]>; def HasV8_1MMainlineOps : SubtargetFeature< "v8.1m.main", "HasV8_1MMainlineOps", "true", "Support ARM v8-1M Mainline instructions", [HasV8MMainlineOps]>; def HasMVEIntegerOps : SubtargetFeature< "mve", "HasMVEIntegerOps", "true", "Support M-Class Vector Extension with integer ops", [HasV8_1MMainlineOps, FeatureDSP, FeatureFPRegs16, FeatureFPRegs64]>; def HasMVEFloatOps : SubtargetFeature< "mve.fp", "HasMVEFloatOps", "true", "Support M-Class Vector Extension with integer and floating ops", [HasMVEIntegerOps, FeatureFPARMv8_D16_SP, FeatureFullFP16]>; //===----------------------------------------------------------------------===// // ARM Processor subtarget features. // def ProcA5 : SubtargetFeature<"a5", "ARMProcFamily", "CortexA5", "Cortex-A5 ARM processors", []>; def ProcA7 : SubtargetFeature<"a7", "ARMProcFamily", "CortexA7", "Cortex-A7 ARM processors", []>; def ProcA8 : SubtargetFeature<"a8", "ARMProcFamily", "CortexA8", "Cortex-A8 ARM processors", []>; def ProcA9 : SubtargetFeature<"a9", "ARMProcFamily", "CortexA9", "Cortex-A9 ARM processors", []>; def ProcA12 : SubtargetFeature<"a12", "ARMProcFamily", "CortexA12", "Cortex-A12 ARM processors", []>; def ProcA15 : SubtargetFeature<"a15", "ARMProcFamily", "CortexA15", "Cortex-A15 ARM processors", []>; def ProcA17 : SubtargetFeature<"a17", "ARMProcFamily", "CortexA17", "Cortex-A17 ARM processors", []>; def ProcA32 : SubtargetFeature<"a32", "ARMProcFamily", "CortexA32", "Cortex-A32 ARM processors", []>; def ProcA35 : SubtargetFeature<"a35", "ARMProcFamily", "CortexA35", "Cortex-A35 ARM processors", []>; def ProcA53 : SubtargetFeature<"a53", "ARMProcFamily", "CortexA53", "Cortex-A53 ARM processors", []>; def ProcA55 : SubtargetFeature<"a55", "ARMProcFamily", "CortexA55", "Cortex-A55 ARM processors", []>; def ProcA57 : SubtargetFeature<"a57", "ARMProcFamily", "CortexA57", "Cortex-A57 ARM processors", []>; def ProcA72 : SubtargetFeature<"a72", "ARMProcFamily", "CortexA72", "Cortex-A72 ARM processors", []>; def ProcA73 : SubtargetFeature<"a73", "ARMProcFamily", "CortexA73", "Cortex-A73 ARM processors", []>; def ProcA75 : SubtargetFeature<"a75", "ARMProcFamily", "CortexA75", "Cortex-A75 ARM processors", []>; def ProcA76 : SubtargetFeature<"a76", "ARMProcFamily", "CortexA76", "Cortex-A76 ARM processors", []>; def ProcKrait : SubtargetFeature<"krait", "ARMProcFamily", "Krait", "Qualcomm Krait processors", []>; def ProcKryo : SubtargetFeature<"kryo", "ARMProcFamily", "Kryo", "Qualcomm Kryo processors", []>; def ProcSwift : SubtargetFeature<"swift", "ARMProcFamily", "Swift", "Swift ARM processors", []>; def ProcExynos : SubtargetFeature<"exynos", "ARMProcFamily", "Exynos", "Samsung Exynos processors", [FeatureZCZeroing, FeatureUseWideStrideVFP, FeatureUseAA, FeatureSplatVFPToNeon, FeatureSlowVGETLNi32, FeatureSlowVDUP32, FeatureSlowFPBrcc, FeatureProfUnpredicate, FeatureHWDivThumb, FeatureHWDivARM, FeatureHasSlowFPVMLx, FeatureHasRetAddrStack, FeatureFuseLiterals, FeatureFuseAES, FeatureExpandMLx, FeatureCrypto, FeatureCRC]>; def ProcR4 : SubtargetFeature<"r4", "ARMProcFamily", "CortexR4", "Cortex-R4 ARM processors", []>; def ProcR5 : SubtargetFeature<"r5", "ARMProcFamily", "CortexR5", "Cortex-R5 ARM processors", []>; def ProcR7 : SubtargetFeature<"r7", "ARMProcFamily", "CortexR7", "Cortex-R7 ARM processors", []>; def ProcR52 : SubtargetFeature<"r52", "ARMProcFamily", "CortexR52", "Cortex-R52 ARM processors", []>; def ProcM3 : SubtargetFeature<"m3", "ARMProcFamily", "CortexM3", "Cortex-M3 ARM processors", []>; //===----------------------------------------------------------------------===// // ARM Helper classes. // class Architecture features> : SubtargetFeature; class ProcNoItin Features> : Processor; //===----------------------------------------------------------------------===// // ARM architectures // def ARMv2 : Architecture<"armv2", "ARMv2", []>; def ARMv2a : Architecture<"armv2a", "ARMv2a", []>; def ARMv3 : Architecture<"armv3", "ARMv3", []>; def ARMv3m : Architecture<"armv3m", "ARMv3m", []>; def ARMv4 : Architecture<"armv4", "ARMv4", []>; def ARMv4t : Architecture<"armv4t", "ARMv4t", [HasV4TOps]>; def ARMv5t : Architecture<"armv5t", "ARMv5t", [HasV5TOps]>; def ARMv5te : Architecture<"armv5te", "ARMv5te", [HasV5TEOps]>; def ARMv5tej : Architecture<"armv5tej", "ARMv5tej", [HasV5TEOps]>; def ARMv6 : Architecture<"armv6", "ARMv6", [HasV6Ops, FeatureDSP]>; def ARMv6t2 : Architecture<"armv6t2", "ARMv6t2", [HasV6T2Ops, FeatureDSP]>; def ARMv6k : Architecture<"armv6k", "ARMv6k", [HasV6KOps]>; def ARMv6kz : Architecture<"armv6kz", "ARMv6kz", [HasV6KOps, FeatureTrustZone]>; def ARMv6m : Architecture<"armv6-m", "ARMv6m", [HasV6MOps, FeatureNoARM, ModeThumb, FeatureDB, FeatureMClass, FeatureStrictAlign]>; def ARMv6sm : Architecture<"armv6s-m", "ARMv6sm", [HasV6MOps, FeatureNoARM, ModeThumb, FeatureDB, FeatureMClass, FeatureStrictAlign]>; def ARMv7a : Architecture<"armv7-a", "ARMv7a", [HasV7Ops, FeatureNEON, FeatureDB, FeatureDSP, FeatureAClass]>; def ARMv7ve : Architecture<"armv7ve", "ARMv7ve", [HasV7Ops, FeatureNEON, FeatureDB, FeatureDSP, FeatureTrustZone, FeatureMP, FeatureVirtualization, FeatureAClass]>; def ARMv7r : Architecture<"armv7-r", "ARMv7r", [HasV7Ops, FeatureDB, FeatureDSP, FeatureHWDivThumb, FeatureRClass]>; def ARMv7m : Architecture<"armv7-m", "ARMv7m", [HasV7Ops, FeatureThumb2, FeatureNoARM, ModeThumb, FeatureDB, FeatureHWDivThumb, FeatureMClass]>; def ARMv7em : Architecture<"armv7e-m", "ARMv7em", [HasV7Ops, FeatureThumb2, FeatureNoARM, ModeThumb, FeatureDB, FeatureHWDivThumb, FeatureMClass, FeatureDSP]>; def ARMv8a : Architecture<"armv8-a", "ARMv8a", [HasV8Ops, FeatureAClass, FeatureDB, FeatureFPARMv8, FeatureNEON, FeatureDSP, FeatureTrustZone, FeatureMP, FeatureVirtualization, FeatureCrypto, FeatureCRC]>; def ARMv81a : Architecture<"armv8.1-a", "ARMv81a", [HasV8_1aOps, FeatureAClass, FeatureDB, FeatureFPARMv8, FeatureNEON, FeatureDSP, FeatureTrustZone, FeatureMP, FeatureVirtualization, FeatureCrypto, FeatureCRC]>; def ARMv82a : Architecture<"armv8.2-a", "ARMv82a", [HasV8_2aOps, FeatureAClass, FeatureDB, FeatureFPARMv8, FeatureNEON, FeatureDSP, FeatureTrustZone, FeatureMP, FeatureVirtualization, FeatureCrypto, FeatureCRC, FeatureRAS]>; def ARMv83a : Architecture<"armv8.3-a", "ARMv83a", [HasV8_3aOps, FeatureAClass, FeatureDB, FeatureFPARMv8, FeatureNEON, FeatureDSP, FeatureTrustZone, FeatureMP, FeatureVirtualization, FeatureCrypto, FeatureCRC, FeatureRAS]>; def ARMv84a : Architecture<"armv8.4-a", "ARMv84a", [HasV8_4aOps, FeatureAClass, FeatureDB, FeatureFPARMv8, FeatureNEON, FeatureDSP, FeatureTrustZone, FeatureMP, FeatureVirtualization, FeatureCrypto, FeatureCRC, FeatureRAS, FeatureDotProd]>; def ARMv85a : Architecture<"armv8.5-a", "ARMv85a", [HasV8_5aOps, FeatureAClass, FeatureDB, FeatureFPARMv8, FeatureNEON, FeatureDSP, FeatureTrustZone, FeatureMP, FeatureVirtualization, FeatureCrypto, FeatureCRC, FeatureRAS, FeatureDotProd]>; def ARMv8r : Architecture<"armv8-r", "ARMv8r", [HasV8Ops, FeatureRClass, FeatureDB, FeatureDFB, FeatureDSP, FeatureCRC, FeatureMP, FeatureVirtualization, FeatureFPARMv8, FeatureNEON]>; def ARMv8mBaseline : Architecture<"armv8-m.base", "ARMv8mBaseline", [HasV8MBaselineOps, FeatureNoARM, ModeThumb, FeatureDB, FeatureHWDivThumb, FeatureV7Clrex, Feature8MSecExt, FeatureAcquireRelease, FeatureMClass, FeatureStrictAlign]>; def ARMv8mMainline : Architecture<"armv8-m.main", "ARMv8mMainline", [HasV8MMainlineOps, FeatureNoARM, ModeThumb, FeatureDB, FeatureHWDivThumb, Feature8MSecExt, FeatureAcquireRelease, FeatureMClass]>; def ARMv81mMainline : Architecture<"armv8.1-m.main", "ARMv81mMainline", [HasV8_1MMainlineOps, FeatureNoARM, ModeThumb, FeatureDB, FeatureHWDivThumb, Feature8MSecExt, FeatureAcquireRelease, FeatureMClass, FeatureRAS, FeatureLOB]>; // Aliases def IWMMXT : Architecture<"iwmmxt", "ARMv5te", [ARMv5te]>; def IWMMXT2 : Architecture<"iwmmxt2", "ARMv5te", [ARMv5te]>; def XScale : Architecture<"xscale", "ARMv5te", [ARMv5te]>; def ARMv6j : Architecture<"armv6j", "ARMv7a", [ARMv6]>; def ARMv7k : Architecture<"armv7k", "ARMv7a", [ARMv7a]>; def ARMv7s : Architecture<"armv7s", "ARMv7a", [ARMv7a]>; //===----------------------------------------------------------------------===// // ARM schedules. //===----------------------------------------------------------------------===// // include "ARMPredicates.td" include "ARMSchedule.td" //===----------------------------------------------------------------------===// // ARM processors // // Dummy CPU, used to target architectures def : ProcessorModel<"generic", CortexA8Model, []>; // FIXME: Several processors below are not using their own scheduler // model, but one of similar/previous processor. These should be fixed. def : ProcNoItin<"arm8", [ARMv4]>; def : ProcNoItin<"arm810", [ARMv4]>; def : ProcNoItin<"strongarm", [ARMv4]>; def : ProcNoItin<"strongarm110", [ARMv4]>; def : ProcNoItin<"strongarm1100", [ARMv4]>; def : ProcNoItin<"strongarm1110", [ARMv4]>; def : ProcNoItin<"arm7tdmi", [ARMv4t]>; def : ProcNoItin<"arm7tdmi-s", [ARMv4t]>; def : ProcNoItin<"arm710t", [ARMv4t]>; def : ProcNoItin<"arm720t", [ARMv4t]>; def : ProcNoItin<"arm9", [ARMv4t]>; def : ProcNoItin<"arm9tdmi", [ARMv4t]>; def : ProcNoItin<"arm920", [ARMv4t]>; def : ProcNoItin<"arm920t", [ARMv4t]>; def : ProcNoItin<"arm922t", [ARMv4t]>; def : ProcNoItin<"arm940t", [ARMv4t]>; def : ProcNoItin<"ep9312", [ARMv4t]>; def : ProcNoItin<"arm10tdmi", [ARMv5t]>; def : ProcNoItin<"arm1020t", [ARMv5t]>; def : ProcNoItin<"arm9e", [ARMv5te]>; def : ProcNoItin<"arm926ej-s", [ARMv5te]>; def : ProcNoItin<"arm946e-s", [ARMv5te]>; def : ProcNoItin<"arm966e-s", [ARMv5te]>; def : ProcNoItin<"arm968e-s", [ARMv5te]>; def : ProcNoItin<"arm10e", [ARMv5te]>; def : ProcNoItin<"arm1020e", [ARMv5te]>; def : ProcNoItin<"arm1022e", [ARMv5te]>; def : ProcNoItin<"xscale", [ARMv5te]>; def : ProcNoItin<"iwmmxt", [ARMv5te]>; def : Processor<"arm1136j-s", ARMV6Itineraries, [ARMv6]>; def : Processor<"arm1136jf-s", ARMV6Itineraries, [ARMv6, FeatureVFP2, FeatureHasSlowFPVMLx]>; def : Processor<"cortex-m0", ARMV6Itineraries, [ARMv6m]>; def : Processor<"cortex-m0plus", ARMV6Itineraries, [ARMv6m]>; def : Processor<"cortex-m1", ARMV6Itineraries, [ARMv6m]>; def : Processor<"sc000", ARMV6Itineraries, [ARMv6m]>; def : Processor<"arm1176j-s", ARMV6Itineraries, [ARMv6kz]>; def : Processor<"arm1176jz-s", ARMV6Itineraries, [ARMv6kz]>; def : Processor<"arm1176jzf-s", ARMV6Itineraries, [ARMv6kz, FeatureVFP2, FeatureHasSlowFPVMLx]>; def : Processor<"mpcorenovfp", ARMV6Itineraries, [ARMv6k]>; def : Processor<"mpcore", ARMV6Itineraries, [ARMv6k, FeatureVFP2, FeatureHasSlowFPVMLx]>; def : Processor<"arm1156t2-s", ARMV6Itineraries, [ARMv6t2]>; def : Processor<"arm1156t2f-s", ARMV6Itineraries, [ARMv6t2, FeatureVFP2, FeatureHasSlowFPVMLx]>; def : ProcessorModel<"cortex-a5", CortexA8Model, [ARMv7a, ProcA5, FeatureHasRetAddrStack, FeatureTrustZone, FeatureSlowFPBrcc, FeatureHasSlowFPVMLx, FeatureVMLxForwarding, FeatureMP, FeatureVFP4]>; def : ProcessorModel<"cortex-a7", CortexA8Model, [ARMv7a, ProcA7, FeatureHasRetAddrStack, FeatureTrustZone, FeatureSlowFPBrcc, FeatureHasVMLxHazards, FeatureHasSlowFPVMLx, FeatureVMLxForwarding, FeatureMP, FeatureVFP4, FeatureVirtualization]>; def : ProcessorModel<"cortex-a8", CortexA8Model, [ARMv7a, ProcA8, FeatureHasRetAddrStack, FeatureNonpipelinedVFP, FeatureTrustZone, FeatureSlowFPBrcc, FeatureHasVMLxHazards, FeatureHasSlowFPVMLx, FeatureVMLxForwarding]>; def : ProcessorModel<"cortex-a9", CortexA9Model, [ARMv7a, ProcA9, FeatureHasRetAddrStack, FeatureTrustZone, FeatureHasVMLxHazards, FeatureVMLxForwarding, FeatureFP16, FeatureAvoidPartialCPSR, FeatureExpandMLx, FeaturePreferVMOVSR, FeatureMuxedUnits, FeatureNEONForFPMovs, FeatureCheckVLDnAlign, FeatureMP]>; def : ProcessorModel<"cortex-a12", CortexA9Model, [ARMv7a, ProcA12, FeatureHasRetAddrStack, FeatureTrustZone, FeatureVMLxForwarding, FeatureVFP4, FeatureAvoidPartialCPSR, FeatureVirtualization, FeatureMP]>; def : ProcessorModel<"cortex-a15", CortexA9Model, [ARMv7a, ProcA15, FeatureDontWidenVMOVS, FeatureSplatVFPToNeon, FeatureHasRetAddrStack, FeatureMuxedUnits, FeatureTrustZone, FeatureVFP4, FeatureMP, FeatureCheckVLDnAlign, FeatureAvoidPartialCPSR, FeatureVirtualization]>; def : ProcessorModel<"cortex-a17", CortexA9Model, [ARMv7a, ProcA17, FeatureHasRetAddrStack, FeatureTrustZone, FeatureMP, FeatureVMLxForwarding, FeatureVFP4, FeatureAvoidPartialCPSR, FeatureVirtualization]>; // FIXME: krait has currently the same features as A9 plus VFP4 and HWDiv def : ProcessorModel<"krait", CortexA9Model, [ARMv7a, ProcKrait, FeatureHasRetAddrStack, FeatureMuxedUnits, FeatureCheckVLDnAlign, FeatureVMLxForwarding, FeatureFP16, FeatureAvoidPartialCPSR, FeatureVFP4, FeatureHWDivThumb, FeatureHWDivARM]>; def : ProcessorModel<"swift", SwiftModel, [ARMv7a, ProcSwift, FeatureHasRetAddrStack, FeatureNEONForFP, FeatureVFP4, FeatureUseWideStrideVFP, FeatureMP, FeatureHWDivThumb, FeatureHWDivARM, FeatureAvoidPartialCPSR, FeatureAvoidMOVsShOp, FeatureHasSlowFPVMLx, FeatureHasVMLxHazards, FeatureProfUnpredicate, FeaturePrefISHSTBarrier, FeatureSlowOddRegister, FeatureSlowLoadDSubreg, FeatureSlowVGETLNi32, FeatureSlowVDUP32, FeatureUseMISched, FeatureNoPostRASched]>; def : ProcessorModel<"cortex-r4", CortexA8Model, [ARMv7r, ProcR4, FeatureHasRetAddrStack, FeatureAvoidPartialCPSR]>; def : ProcessorModel<"cortex-r4f", CortexA8Model, [ARMv7r, ProcR4, FeatureHasRetAddrStack, FeatureSlowFPBrcc, FeatureHasSlowFPVMLx, FeatureVFP3_D16, FeatureAvoidPartialCPSR]>; def : ProcessorModel<"cortex-r5", CortexA8Model, [ARMv7r, ProcR5, FeatureHasRetAddrStack, FeatureVFP3_D16, FeatureSlowFPBrcc, FeatureHWDivARM, FeatureHasSlowFPVMLx, FeatureAvoidPartialCPSR]>; def : ProcessorModel<"cortex-r7", CortexA8Model, [ARMv7r, ProcR7, FeatureHasRetAddrStack, FeatureVFP3_D16, FeatureFP16, FeatureMP, FeatureSlowFPBrcc, FeatureHWDivARM, FeatureHasSlowFPVMLx, FeatureAvoidPartialCPSR]>; def : ProcessorModel<"cortex-r8", CortexA8Model, [ARMv7r, FeatureHasRetAddrStack, FeatureVFP3_D16, FeatureFP16, FeatureMP, FeatureSlowFPBrcc, FeatureHWDivARM, FeatureHasSlowFPVMLx, FeatureAvoidPartialCPSR]>; def : ProcessorModel<"cortex-m3", CortexM4Model, [ARMv7m, ProcM3, FeaturePrefLoopAlign32, FeatureUseMISched, FeatureUseAA, FeatureHasNoBranchPredictor]>; def : ProcessorModel<"sc300", CortexM4Model, [ARMv7m, ProcM3, FeatureUseMISched, FeatureUseAA, FeatureHasNoBranchPredictor]>; def : ProcessorModel<"cortex-m4", CortexM4Model, [ARMv7em, FeatureVFP4_D16_SP, FeaturePrefLoopAlign32, FeatureHasSlowFPVMLx, FeatureUseMISched, FeatureUseAA, FeatureHasNoBranchPredictor]>; def : ProcNoItin<"cortex-m7", [ARMv7em, FeatureFPARMv8_D16]>; def : ProcNoItin<"cortex-m23", [ARMv8mBaseline, FeatureNoMovt]>; def : ProcessorModel<"cortex-m33", CortexM4Model, [ARMv8mMainline, FeatureDSP, FeatureFPARMv8_D16_SP, FeaturePrefLoopAlign32, FeatureHasSlowFPVMLx, FeatureUseMISched, FeatureUseAA, FeatureHasNoBranchPredictor]>; def : ProcessorModel<"cortex-m35p", CortexM4Model, [ARMv8mMainline, FeatureDSP, FeatureFPARMv8_D16_SP, FeaturePrefLoopAlign32, FeatureHasSlowFPVMLx, FeatureUseMISched, FeatureUseAA, FeatureHasNoBranchPredictor]>; def : ProcNoItin<"cortex-a32", [ARMv8a, FeatureHWDivThumb, FeatureHWDivARM, FeatureCrypto, FeatureCRC]>; def : ProcNoItin<"cortex-a35", [ARMv8a, ProcA35, FeatureHWDivThumb, FeatureHWDivARM, FeatureCrypto, FeatureCRC]>; def : ProcNoItin<"cortex-a53", [ARMv8a, ProcA53, FeatureHWDivThumb, FeatureHWDivARM, FeatureCrypto, FeatureCRC, FeatureFPAO]>; def : ProcNoItin<"cortex-a55", [ARMv82a, ProcA55, FeatureHWDivThumb, FeatureHWDivARM, FeatureDotProd]>; def : ProcessorModel<"cortex-a57", CortexA57Model, [ARMv8a, ProcA57, FeatureHWDivThumb, FeatureHWDivARM, FeatureCrypto, FeatureCRC, FeatureFPAO, FeatureAvoidPartialCPSR, FeatureCheapPredicableCPSR]>; def : ProcessorModel<"cortex-a72", CortexA57Model, [ARMv8a, ProcA72, FeatureHWDivThumb, FeatureHWDivARM, FeatureCrypto, FeatureCRC]>; def : ProcNoItin<"cortex-a73", [ARMv8a, ProcA73, FeatureHWDivThumb, FeatureHWDivARM, FeatureCrypto, FeatureCRC]>; def : ProcNoItin<"cortex-a75", [ARMv82a, ProcA75, FeatureHWDivThumb, FeatureHWDivARM, FeatureDotProd]>; def : ProcNoItin<"cortex-a76", [ARMv82a, ProcA76, FeatureHWDivThumb, FeatureHWDivARM, FeatureCrypto, FeatureCRC, FeatureFullFP16, FeatureDotProd]>; def : ProcNoItin<"cortex-a76ae", [ARMv82a, ProcA76, FeatureHWDivThumb, FeatureHWDivARM, FeatureCrypto, FeatureCRC, FeatureFullFP16, FeatureDotProd]>; def : ProcessorModel<"cyclone", SwiftModel, [ARMv8a, ProcSwift, FeatureHasRetAddrStack, FeatureNEONForFP, FeatureVFP4, FeatureMP, FeatureHWDivThumb, FeatureHWDivARM, FeatureAvoidPartialCPSR, FeatureAvoidMOVsShOp, FeatureHasSlowFPVMLx, FeatureCrypto, FeatureUseMISched, FeatureZCZeroing, FeatureNoPostRASched]>; def : ProcNoItin<"exynos-m1", [ARMv8a, ProcExynos]>; def : ProcNoItin<"exynos-m2", [ARMv8a, ProcExynos]>; def : ProcNoItin<"exynos-m3", [ARMv8a, ProcExynos]>; def : ProcNoItin<"exynos-m4", [ARMv82a, ProcExynos, FeatureFullFP16, FeatureDotProd]>; def : ProcNoItin<"exynos-m5", [ARMv82a, ProcExynos, FeatureFullFP16, FeatureDotProd]>; def : ProcNoItin<"kryo", [ARMv8a, ProcKryo, FeatureHWDivThumb, FeatureHWDivARM, FeatureCrypto, FeatureCRC]>; def : ProcessorModel<"cortex-r52", CortexR52Model, [ARMv8r, ProcR52, FeatureUseMISched, FeatureFPAO, FeatureUseAA]>; //===----------------------------------------------------------------------===// // Register File Description //===----------------------------------------------------------------------===// include "ARMRegisterInfo.td" include "ARMRegisterBanks.td" include "ARMCallingConv.td" //===----------------------------------------------------------------------===// // Instruction Descriptions //===----------------------------------------------------------------------===// include "ARMInstrInfo.td" def ARMInstrInfo : InstrInfo; //===----------------------------------------------------------------------===// // Declare the target which we are implementing //===----------------------------------------------------------------------===// def ARMAsmWriter : AsmWriter { string AsmWriterClassName = "InstPrinter"; int PassSubtarget = 1; int Variant = 0; bit isMCAsmWriter = 1; } def ARMAsmParser : AsmParser { bit ReportMultipleNearMisses = 1; } def ARMAsmParserVariant : AsmParserVariant { int Variant = 0; string Name = "ARM"; string BreakCharacters = "."; } def ARM : Target { // Pull in Instruction Info. let InstructionSet = ARMInstrInfo; let AssemblyWriters = [ARMAsmWriter]; let AssemblyParsers = [ARMAsmParser]; let AssemblyParserVariants = [ARMAsmParserVariant]; let AllowRegisterRenaming = 1; } Index: head/contrib/llvm/lib/Target/ARM/ARMPredicates.td =================================================================== --- head/contrib/llvm/lib/Target/ARM/ARMPredicates.td (revision 354096) +++ head/contrib/llvm/lib/Target/ARM/ARMPredicates.td (revision 354097) @@ -1,211 +1,211 @@ //===-- ARMPredicates.td - ARM Instruction Predicates ------*- tablegen -*-===// // // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. // See https://llvm.org/LICENSE.txt for license information. // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception // //===----------------------------------------------------------------------===// def HasV4T : Predicate<"Subtarget->hasV4TOps()">, AssemblerPredicate<"HasV4TOps", "armv4t">; def NoV4T : Predicate<"!Subtarget->hasV4TOps()">; def HasV5T : Predicate<"Subtarget->hasV5TOps()">, AssemblerPredicate<"HasV5TOps", "armv5t">; def NoV5T : Predicate<"!Subtarget->hasV5TOps()">; def HasV5TE : Predicate<"Subtarget->hasV5TEOps()">, AssemblerPredicate<"HasV5TEOps", "armv5te">; def HasV6 : Predicate<"Subtarget->hasV6Ops()">, AssemblerPredicate<"HasV6Ops", "armv6">; def NoV6 : Predicate<"!Subtarget->hasV6Ops()">; def HasV6M : Predicate<"Subtarget->hasV6MOps()">, AssemblerPredicate<"HasV6MOps", "armv6m or armv6t2">; def HasV8MBaseline : Predicate<"Subtarget->hasV8MBaselineOps()">, AssemblerPredicate<"HasV8MBaselineOps", "armv8m.base">; def HasV8MMainline : Predicate<"Subtarget->hasV8MMainlineOps()">, AssemblerPredicate<"HasV8MMainlineOps", "armv8m.main">; def HasV8_1MMainline : Predicate<"Subtarget->hasV8_1MMainlineOps()">, AssemblerPredicate<"HasV8_1MMainlineOps", "armv8.1m.main">; def HasMVEInt : Predicate<"Subtarget->hasMVEIntegerOps()">, AssemblerPredicate<"HasMVEIntegerOps", "mve">; def HasMVEFloat : Predicate<"Subtarget->hasMVEFloatOps()">, AssemblerPredicate<"HasMVEFloatOps", "mve.fp">; def HasFPRegs : Predicate<"Subtarget->hasFPRegs()">, AssemblerPredicate<"FeatureFPRegs", "fp registers">; def HasFPRegs16 : Predicate<"Subtarget->hasFPRegs16()">, AssemblerPredicate<"FeatureFPRegs16", "16-bit fp registers">; def HasFPRegs64 : Predicate<"Subtarget->hasFPRegs64()">, AssemblerPredicate<"FeatureFPRegs64", "64-bit fp registers">; def HasFPRegsV8_1M : Predicate<"Subtarget->hasFPRegs() && Subtarget->hasV8_1MMainlineOps()">, AssemblerPredicate<"FeatureFPRegs,HasV8_1MMainlineOps", "armv8.1m.main with FP or MVE">; def HasV6T2 : Predicate<"Subtarget->hasV6T2Ops()">, AssemblerPredicate<"HasV6T2Ops", "armv6t2">; def NoV6T2 : Predicate<"!Subtarget->hasV6T2Ops()">; def HasV6K : Predicate<"Subtarget->hasV6KOps()">, AssemblerPredicate<"HasV6KOps", "armv6k">; def NoV6K : Predicate<"!Subtarget->hasV6KOps()">; def HasV7 : Predicate<"Subtarget->hasV7Ops()">, AssemblerPredicate<"HasV7Ops", "armv7">; def HasV8 : Predicate<"Subtarget->hasV8Ops()">, AssemblerPredicate<"HasV8Ops", "armv8">; def PreV8 : Predicate<"!Subtarget->hasV8Ops()">, AssemblerPredicate<"!HasV8Ops", "armv7 or earlier">; def HasV8_1a : Predicate<"Subtarget->hasV8_1aOps()">, AssemblerPredicate<"HasV8_1aOps", "armv8.1a">; def HasV8_2a : Predicate<"Subtarget->hasV8_2aOps()">, AssemblerPredicate<"HasV8_2aOps", "armv8.2a">; def HasV8_3a : Predicate<"Subtarget->hasV8_3aOps()">, AssemblerPredicate<"HasV8_3aOps", "armv8.3a">; def HasV8_4a : Predicate<"Subtarget->hasV8_4aOps()">, AssemblerPredicate<"HasV8_4aOps", "armv8.4a">; def HasV8_5a : Predicate<"Subtarget->hasV8_5aOps()">, AssemblerPredicate<"HasV8_5aOps", "armv8.5a">; def NoVFP : Predicate<"!Subtarget->hasVFP2Base()">; def HasVFP2 : Predicate<"Subtarget->hasVFP2Base()">, - AssemblerPredicate<"FeatureVFP2_D16_SP", "VFP2">; + AssemblerPredicate<"FeatureVFP2_SP", "VFP2">; def HasVFP3 : Predicate<"Subtarget->hasVFP3Base()">, AssemblerPredicate<"FeatureVFP3_D16_SP", "VFP3">; def HasVFP4 : Predicate<"Subtarget->hasVFP4Base()">, AssemblerPredicate<"FeatureVFP4_D16_SP", "VFP4">; def HasDPVFP : Predicate<"Subtarget->hasFP64()">, AssemblerPredicate<"FeatureFP64", "double precision VFP">; def HasFPARMv8 : Predicate<"Subtarget->hasFPARMv8Base()">, AssemblerPredicate<"FeatureFPARMv8_D16_SP", "FPARMv8">; def HasNEON : Predicate<"Subtarget->hasNEON()">, AssemblerPredicate<"FeatureNEON", "NEON">; def HasSHA2 : Predicate<"Subtarget->hasSHA2()">, AssemblerPredicate<"FeatureSHA2", "sha2">; def HasAES : Predicate<"Subtarget->hasAES()">, AssemblerPredicate<"FeatureAES", "aes">; def HasCrypto : Predicate<"Subtarget->hasCrypto()">, AssemblerPredicate<"FeatureCrypto", "crypto">; def HasDotProd : Predicate<"Subtarget->hasDotProd()">, AssemblerPredicate<"FeatureDotProd", "dotprod">; def HasCRC : Predicate<"Subtarget->hasCRC()">, AssemblerPredicate<"FeatureCRC", "crc">; def HasRAS : Predicate<"Subtarget->hasRAS()">, AssemblerPredicate<"FeatureRAS", "ras">; def HasLOB : Predicate<"Subtarget->hasLOB()">, AssemblerPredicate<"FeatureLOB", "lob">; def HasFP16 : Predicate<"Subtarget->hasFP16()">, AssemblerPredicate<"FeatureFP16","half-float conversions">; def HasFullFP16 : Predicate<"Subtarget->hasFullFP16()">, AssemblerPredicate<"FeatureFullFP16","full half-float">; def HasFP16FML : Predicate<"Subtarget->hasFP16FML()">, AssemblerPredicate<"FeatureFP16FML","full half-float fml">; def HasDivideInThumb : Predicate<"Subtarget->hasDivideInThumbMode()">, AssemblerPredicate<"FeatureHWDivThumb", "divide in THUMB">; def HasDivideInARM : Predicate<"Subtarget->hasDivideInARMMode()">, AssemblerPredicate<"FeatureHWDivARM", "divide in ARM">; def HasDSP : Predicate<"Subtarget->hasDSP()">, AssemblerPredicate<"FeatureDSP", "dsp">; def HasDB : Predicate<"Subtarget->hasDataBarrier()">, AssemblerPredicate<"FeatureDB", "data-barriers">; def HasDFB : Predicate<"Subtarget->hasFullDataBarrier()">, AssemblerPredicate<"FeatureDFB", "full-data-barrier">; def HasV7Clrex : Predicate<"Subtarget->hasV7Clrex()">, AssemblerPredicate<"FeatureV7Clrex", "v7 clrex">; def HasAcquireRelease : Predicate<"Subtarget->hasAcquireRelease()">, AssemblerPredicate<"FeatureAcquireRelease", "acquire/release">; def HasMP : Predicate<"Subtarget->hasMPExtension()">, AssemblerPredicate<"FeatureMP", "mp-extensions">; def HasVirtualization: Predicate<"false">, AssemblerPredicate<"FeatureVirtualization", "virtualization-extensions">; def HasTrustZone : Predicate<"Subtarget->hasTrustZone()">, AssemblerPredicate<"FeatureTrustZone", "TrustZone">; def Has8MSecExt : Predicate<"Subtarget->has8MSecExt()">, AssemblerPredicate<"Feature8MSecExt", "ARMv8-M Security Extensions">; def HasZCZ : Predicate<"Subtarget->hasZeroCycleZeroing()">; def UseNEONForFP : Predicate<"Subtarget->useNEONForSinglePrecisionFP()">; def DontUseNEONForFP : Predicate<"!Subtarget->useNEONForSinglePrecisionFP()">; def IsThumb : Predicate<"Subtarget->isThumb()">, AssemblerPredicate<"ModeThumb", "thumb">; def IsThumb1Only : Predicate<"Subtarget->isThumb1Only()">; def IsThumb2 : Predicate<"Subtarget->isThumb2()">, AssemblerPredicate<"ModeThumb,FeatureThumb2", "thumb2">; def IsMClass : Predicate<"Subtarget->isMClass()">, AssemblerPredicate<"FeatureMClass", "armv*m">; def IsNotMClass : Predicate<"!Subtarget->isMClass()">, AssemblerPredicate<"!FeatureMClass", "!armv*m">; def IsARM : Predicate<"!Subtarget->isThumb()">, AssemblerPredicate<"!ModeThumb", "arm-mode">; def IsMachO : Predicate<"Subtarget->isTargetMachO()">; def IsNotMachO : Predicate<"!Subtarget->isTargetMachO()">; def IsNaCl : Predicate<"Subtarget->isTargetNaCl()">; def IsWindows : Predicate<"Subtarget->isTargetWindows()">; def IsNotWindows : Predicate<"!Subtarget->isTargetWindows()">; def IsReadTPHard : Predicate<"Subtarget->isReadTPHard()">; def IsReadTPSoft : Predicate<"!Subtarget->isReadTPHard()">; def UseNaClTrap : Predicate<"Subtarget->useNaClTrap()">, AssemblerPredicate<"FeatureNaClTrap", "NaCl">; def DontUseNaClTrap : Predicate<"!Subtarget->useNaClTrap()">; def UseNegativeImmediates : Predicate<"false">, AssemblerPredicate<"!FeatureNoNegativeImmediates", "NegativeImmediates">; // FIXME: Eventually this will be just "hasV6T2Ops". let RecomputePerFunction = 1 in { def UseMovt : Predicate<"Subtarget->useMovt()">; def DontUseMovt : Predicate<"!Subtarget->useMovt()">; def UseMovtInPic : Predicate<"Subtarget->useMovt() && Subtarget->allowPositionIndependentMovt()">; def DontUseMovtInPic : Predicate<"!Subtarget->useMovt() || !Subtarget->allowPositionIndependentMovt()">; def UseFPVMLx: Predicate<"((Subtarget->useFPVMLx() &&" " TM.Options.AllowFPOpFusion != FPOpFusion::Fast) ||" "Subtarget->hasMinSize())">; } def UseMulOps : Predicate<"Subtarget->useMulOps()">; // Prefer fused MAC for fp mul + add over fp VMLA / VMLS if they are available. // But only select them if more precision in FP computation is allowed, and when // they are not slower than a mul + add sequence. // Do not use them for Darwin platforms. def UseFusedMAC : Predicate<"(TM.Options.AllowFPOpFusion ==" " FPOpFusion::Fast && " " Subtarget->hasVFP4Base()) && " "!Subtarget->isTargetDarwin() &&" "Subtarget->useFPVMLx()">; def HasFastVGETLNi32 : Predicate<"!Subtarget->hasSlowVGETLNi32()">; def HasSlowVGETLNi32 : Predicate<"Subtarget->hasSlowVGETLNi32()">; def HasFastVDUP32 : Predicate<"!Subtarget->hasSlowVDUP32()">; def HasSlowVDUP32 : Predicate<"Subtarget->hasSlowVDUP32()">; def UseVMOVSR : Predicate<"Subtarget->preferVMOVSR() ||" "!Subtarget->useNEONForSinglePrecisionFP()">; def DontUseVMOVSR : Predicate<"!Subtarget->preferVMOVSR() &&" "Subtarget->useNEONForSinglePrecisionFP()">; let RecomputePerFunction = 1 in { def IsLE : Predicate<"MF->getDataLayout().isLittleEndian()">; def IsBE : Predicate<"MF->getDataLayout().isBigEndian()">; } def GenExecuteOnly : Predicate<"Subtarget->genExecuteOnly()">; // Armv8.5-A extensions def HasSB : Predicate<"Subtarget->hasSB()">, AssemblerPredicate<"FeatureSB", "sb">; Index: head/contrib/llvm/lib/Target/ARM/ARMSubtarget.h =================================================================== --- head/contrib/llvm/lib/Target/ARM/ARMSubtarget.h (revision 354096) +++ head/contrib/llvm/lib/Target/ARM/ARMSubtarget.h (revision 354097) @@ -1,867 +1,865 @@ //===-- ARMSubtarget.h - Define Subtarget for the ARM ----------*- C++ -*--===// // // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. // See https://llvm.org/LICENSE.txt for license information. // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception // //===----------------------------------------------------------------------===// // // This file declares the ARM specific subclass of TargetSubtargetInfo. // //===----------------------------------------------------------------------===// #ifndef LLVM_LIB_TARGET_ARM_ARMSUBTARGET_H #define LLVM_LIB_TARGET_ARM_ARMSUBTARGET_H #include "ARMBaseInstrInfo.h" #include "ARMBaseRegisterInfo.h" #include "ARMConstantPoolValue.h" #include "ARMFrameLowering.h" #include "ARMISelLowering.h" #include "ARMSelectionDAGInfo.h" #include "llvm/ADT/Triple.h" #include "llvm/CodeGen/GlobalISel/CallLowering.h" #include "llvm/CodeGen/GlobalISel/InstructionSelector.h" #include "llvm/CodeGen/GlobalISel/LegalizerInfo.h" #include "llvm/CodeGen/GlobalISel/RegisterBankInfo.h" #include "llvm/CodeGen/MachineFunction.h" #include "llvm/CodeGen/TargetSubtargetInfo.h" #include "llvm/MC/MCInstrItineraries.h" #include "llvm/MC/MCSchedule.h" #include "llvm/Target/TargetOptions.h" #include #include #define GET_SUBTARGETINFO_HEADER #include "ARMGenSubtargetInfo.inc" namespace llvm { class ARMBaseTargetMachine; class GlobalValue; class StringRef; class ARMSubtarget : public ARMGenSubtargetInfo { protected: enum ARMProcFamilyEnum { Others, CortexA12, CortexA15, CortexA17, CortexA32, CortexA35, CortexA5, CortexA53, CortexA55, CortexA57, CortexA7, CortexA72, CortexA73, CortexA75, CortexA76, CortexA8, CortexA9, CortexM3, CortexR4, CortexR4F, CortexR5, CortexR52, CortexR7, Exynos, Krait, Kryo, Swift }; enum ARMProcClassEnum { None, AClass, MClass, RClass }; enum ARMArchEnum { ARMv2, ARMv2a, ARMv3, ARMv3m, ARMv4, ARMv4t, ARMv5, ARMv5t, ARMv5te, ARMv5tej, ARMv6, ARMv6k, ARMv6kz, ARMv6m, ARMv6sm, ARMv6t2, ARMv7a, ARMv7em, ARMv7m, ARMv7r, ARMv7ve, ARMv81a, ARMv82a, ARMv83a, ARMv84a, ARMv85a, ARMv8a, ARMv8mBaseline, ARMv8mMainline, ARMv8r, ARMv81mMainline, }; public: /// What kind of timing do load multiple/store multiple instructions have. enum ARMLdStMultipleTiming { /// Can load/store 2 registers/cycle. DoubleIssue, /// Can load/store 2 registers/cycle, but needs an extra cycle if the access /// is not 64-bit aligned. DoubleIssueCheckUnalignedAccess, /// Can load/store 1 register/cycle. SingleIssue, /// Can load/store 1 register/cycle, but needs an extra cycle for address /// computation and potentially also for register writeback. SingleIssuePlusExtras, }; protected: /// ARMProcFamily - ARM processor family: Cortex-A8, Cortex-A9, and others. ARMProcFamilyEnum ARMProcFamily = Others; /// ARMProcClass - ARM processor class: None, AClass, RClass or MClass. ARMProcClassEnum ARMProcClass = None; /// ARMArch - ARM architecture ARMArchEnum ARMArch = ARMv4t; /// HasV4TOps, HasV5TOps, HasV5TEOps, /// HasV6Ops, HasV6MOps, HasV6KOps, HasV6T2Ops, HasV7Ops, HasV8Ops - /// Specify whether target support specific ARM ISA variants. bool HasV4TOps = false; bool HasV5TOps = false; bool HasV5TEOps = false; bool HasV6Ops = false; bool HasV6MOps = false; bool HasV6KOps = false; bool HasV6T2Ops = false; bool HasV7Ops = false; bool HasV8Ops = false; bool HasV8_1aOps = false; bool HasV8_2aOps = false; bool HasV8_3aOps = false; bool HasV8_4aOps = false; bool HasV8_5aOps = false; bool HasV8MBaselineOps = false; bool HasV8MMainlineOps = false; bool HasV8_1MMainlineOps = false; bool HasMVEIntegerOps = false; bool HasMVEFloatOps = false; /// HasVFPv2, HasVFPv3, HasVFPv4, HasFPARMv8, HasNEON - Specify what /// floating point ISAs are supported. bool HasVFPv2 = false; bool HasVFPv3 = false; bool HasVFPv4 = false; bool HasFPARMv8 = false; bool HasNEON = false; bool HasFPRegs = false; bool HasFPRegs16 = false; bool HasFPRegs64 = false; /// Versions of the VFP flags restricted to single precision, or to /// 16 d-registers, or both. bool HasVFPv2SP = false; bool HasVFPv3SP = false; bool HasVFPv4SP = false; bool HasFPARMv8SP = false; - bool HasVFPv2D16 = false; bool HasVFPv3D16 = false; bool HasVFPv4D16 = false; bool HasFPARMv8D16 = false; - bool HasVFPv2D16SP = false; bool HasVFPv3D16SP = false; bool HasVFPv4D16SP = false; bool HasFPARMv8D16SP = false; /// HasDotProd - True if the ARMv8.2A dot product instructions are supported. bool HasDotProd = false; /// UseNEONForSinglePrecisionFP - if the NEONFP attribute has been /// specified. Use the method useNEONForSinglePrecisionFP() to /// determine if NEON should actually be used. bool UseNEONForSinglePrecisionFP = false; /// UseMulOps - True if non-microcoded fused integer multiply-add and /// multiply-subtract instructions should be used. bool UseMulOps = false; /// SlowFPVMLx - If the VFP2 / NEON instructions are available, indicates /// whether the FP VML[AS] instructions are slow (if so, don't use them). bool SlowFPVMLx = false; /// HasVMLxForwarding - If true, NEON has special multiplier accumulator /// forwarding to allow mul + mla being issued back to back. bool HasVMLxForwarding = false; /// SlowFPBrcc - True if floating point compare + branch is slow. bool SlowFPBrcc = false; /// InThumbMode - True if compiling for Thumb, false for ARM. bool InThumbMode = false; /// UseSoftFloat - True if we're using software floating point features. bool UseSoftFloat = false; /// UseMISched - True if MachineScheduler should be used for this subtarget. bool UseMISched = false; /// DisablePostRAScheduler - False if scheduling should happen again after /// register allocation. bool DisablePostRAScheduler = false; /// UseAA - True if using AA during codegen (DAGCombine, MISched, etc) bool UseAA = false; /// HasThumb2 - True if Thumb2 instructions are supported. bool HasThumb2 = false; /// NoARM - True if subtarget does not support ARM mode execution. bool NoARM = false; /// ReserveR9 - True if R9 is not available as a general purpose register. bool ReserveR9 = false; /// NoMovt - True if MOVT / MOVW pairs are not used for materialization of /// 32-bit imms (including global addresses). bool NoMovt = false; /// SupportsTailCall - True if the OS supports tail call. The dynamic linker /// must be able to synthesize call stubs for interworking between ARM and /// Thumb. bool SupportsTailCall = false; /// HasFP16 - True if subtarget supports half-precision FP conversions bool HasFP16 = false; /// HasFullFP16 - True if subtarget supports half-precision FP operations bool HasFullFP16 = false; /// HasFP16FML - True if subtarget supports half-precision FP fml operations bool HasFP16FML = false; /// HasD32 - True if subtarget has the full 32 double precision /// FP registers for VFPv3. bool HasD32 = false; /// HasHardwareDivide - True if subtarget supports [su]div in Thumb mode bool HasHardwareDivideInThumb = false; /// HasHardwareDivideInARM - True if subtarget supports [su]div in ARM mode bool HasHardwareDivideInARM = false; /// HasDataBarrier - True if the subtarget supports DMB / DSB data barrier /// instructions. bool HasDataBarrier = false; /// HasFullDataBarrier - True if the subtarget supports DFB data barrier /// instruction. bool HasFullDataBarrier = false; /// HasV7Clrex - True if the subtarget supports CLREX instructions bool HasV7Clrex = false; /// HasAcquireRelease - True if the subtarget supports v8 atomics (LDA/LDAEX etc) /// instructions bool HasAcquireRelease = false; /// Pref32BitThumb - If true, codegen would prefer 32-bit Thumb instructions /// over 16-bit ones. bool Pref32BitThumb = false; /// AvoidCPSRPartialUpdate - If true, codegen would avoid using instructions /// that partially update CPSR and add false dependency on the previous /// CPSR setting instruction. bool AvoidCPSRPartialUpdate = false; /// CheapPredicableCPSRDef - If true, disable +1 predication cost /// for instructions updating CPSR. Enabled for Cortex-A57. bool CheapPredicableCPSRDef = false; /// AvoidMOVsShifterOperand - If true, codegen should avoid using flag setting /// movs with shifter operand (i.e. asr, lsl, lsr). bool AvoidMOVsShifterOperand = false; /// HasRetAddrStack - Some processors perform return stack prediction. CodeGen should /// avoid issue "normal" call instructions to callees which do not return. bool HasRetAddrStack = false; /// HasBranchPredictor - True if the subtarget has a branch predictor. Having /// a branch predictor or not changes the expected cost of taking a branch /// which affects the choice of whether to use predicated instructions. bool HasBranchPredictor = true; /// HasMPExtension - True if the subtarget supports Multiprocessing /// extension (ARMv7 only). bool HasMPExtension = false; /// HasVirtualization - True if the subtarget supports the Virtualization /// extension. bool HasVirtualization = false; /// HasFP64 - If true, the floating point unit supports double /// precision. bool HasFP64 = false; /// If true, the processor supports the Performance Monitor Extensions. These /// include a generic cycle-counter as well as more fine-grained (often /// implementation-specific) events. bool HasPerfMon = false; /// HasTrustZone - if true, processor supports TrustZone security extensions bool HasTrustZone = false; /// Has8MSecExt - if true, processor supports ARMv8-M Security Extensions bool Has8MSecExt = false; /// HasSHA2 - if true, processor supports SHA1 and SHA256 bool HasSHA2 = false; /// HasAES - if true, processor supports AES bool HasAES = false; /// HasCrypto - if true, processor supports Cryptography extensions bool HasCrypto = false; /// HasCRC - if true, processor supports CRC instructions bool HasCRC = false; /// HasRAS - if true, the processor supports RAS extensions bool HasRAS = false; /// HasLOB - if true, the processor supports the Low Overhead Branch extension bool HasLOB = false; /// If true, the instructions "vmov.i32 d0, #0" and "vmov.i32 q0, #0" are /// particularly effective at zeroing a VFP register. bool HasZeroCycleZeroing = false; /// HasFPAO - if true, processor does positive address offset computation faster bool HasFPAO = false; /// HasFuseAES - if true, processor executes back to back AES instruction /// pairs faster. bool HasFuseAES = false; /// HasFuseLiterals - if true, processor executes back to back /// bottom and top halves of literal generation faster. bool HasFuseLiterals = false; /// If true, if conversion may decide to leave some instructions unpredicated. bool IsProfitableToUnpredicate = false; /// If true, VMOV will be favored over VGETLNi32. bool HasSlowVGETLNi32 = false; /// If true, VMOV will be favored over VDUP. bool HasSlowVDUP32 = false; /// If true, VMOVSR will be favored over VMOVDRR. bool PreferVMOVSR = false; /// If true, ISHST barriers will be used for Release semantics. bool PreferISHST = false; /// If true, a VLDM/VSTM starting with an odd register number is considered to /// take more microops than single VLDRS/VSTRS. bool SlowOddRegister = false; /// If true, loading into a D subregister will be penalized. bool SlowLoadDSubregister = false; /// If true, use a wider stride when allocating VFP registers. bool UseWideStrideVFP = false; /// If true, the AGU and NEON/FPU units are multiplexed. bool HasMuxedUnits = false; /// If true, VMOVS will never be widened to VMOVD. bool DontWidenVMOVS = false; /// If true, splat a register between VFP and NEON instructions. bool SplatVFPToNeon = false; /// If true, run the MLx expansion pass. bool ExpandMLx = false; /// If true, VFP/NEON VMLA/VMLS have special RAW hazards. bool HasVMLxHazards = false; // If true, read thread pointer from coprocessor register. bool ReadTPHard = false; /// If true, VMOVRS, VMOVSR and VMOVS will be converted from VFP to NEON. bool UseNEONForFPMovs = false; /// If true, VLDn instructions take an extra cycle for unaligned accesses. bool CheckVLDnAlign = false; /// If true, VFP instructions are not pipelined. bool NonpipelinedVFP = false; /// StrictAlign - If true, the subtarget disallows unaligned memory /// accesses for some types. For details, see /// ARMTargetLowering::allowsMisalignedMemoryAccesses(). bool StrictAlign = false; /// RestrictIT - If true, the subtarget disallows generation of deprecated IT /// blocks to conform to ARMv8 rule. bool RestrictIT = false; /// HasDSP - If true, the subtarget supports the DSP (saturating arith /// and such) instructions. bool HasDSP = false; /// NaCl TRAP instruction is generated instead of the regular TRAP. bool UseNaClTrap = false; /// Generate calls via indirect call instructions. bool GenLongCalls = false; /// Generate code that does not contain data access to code sections. bool GenExecuteOnly = false; /// Target machine allowed unsafe FP math (such as use of NEON fp) bool UnsafeFPMath = false; /// UseSjLjEH - If true, the target uses SjLj exception handling (e.g. iOS). bool UseSjLjEH = false; /// Has speculation barrier bool HasSB = false; /// Implicitly convert an instruction to a different one if its immediates /// cannot be encoded. For example, ADD r0, r1, #FFFFFFFF -> SUB r0, r1, #1. bool NegativeImmediates = true; /// stackAlignment - The minimum alignment known to hold of the stack frame on /// entry to the function and which must be maintained by every function. unsigned stackAlignment = 4; /// CPUString - String name of used CPU. std::string CPUString; unsigned MaxInterleaveFactor = 1; /// Clearance before partial register updates (in number of instructions) unsigned PartialUpdateClearance = 0; /// What kind of timing do load multiple/store multiple have (double issue, /// single issue etc). ARMLdStMultipleTiming LdStMultipleTiming = SingleIssue; /// The adjustment that we need to apply to get the operand latency from the /// operand cycle returned by the itinerary data for pre-ISel operands. int PreISelOperandLatencyAdjustment = 2; /// What alignment is preferred for loop bodies, in log2(bytes). unsigned PrefLoopAlignment = 0; /// OptMinSize - True if we're optimising for minimum code size, equal to /// the function attribute. bool OptMinSize = false; /// IsLittle - The target is Little Endian bool IsLittle; /// TargetTriple - What processor and OS we're targeting. Triple TargetTriple; /// SchedModel - Processor specific instruction costs. MCSchedModel SchedModel; /// Selected instruction itineraries (one entry per itinerary class.) InstrItineraryData InstrItins; /// Options passed via command line that could influence the target const TargetOptions &Options; const ARMBaseTargetMachine &TM; public: /// This constructor initializes the data members to match that /// of the specified triple. /// ARMSubtarget(const Triple &TT, const std::string &CPU, const std::string &FS, const ARMBaseTargetMachine &TM, bool IsLittle, bool MinSize = false); /// getMaxInlineSizeThreshold - Returns the maximum memset / memcpy size /// that still makes it profitable to inline the call. unsigned getMaxInlineSizeThreshold() const { return 64; } /// ParseSubtargetFeatures - Parses features string setting specified /// subtarget options. Definition of function is auto generated by tblgen. void ParseSubtargetFeatures(StringRef CPU, StringRef FS); /// initializeSubtargetDependencies - Initializes using a CPU and feature string /// so that we can use initializer lists for subtarget initialization. ARMSubtarget &initializeSubtargetDependencies(StringRef CPU, StringRef FS); const ARMSelectionDAGInfo *getSelectionDAGInfo() const override { return &TSInfo; } const ARMBaseInstrInfo *getInstrInfo() const override { return InstrInfo.get(); } const ARMTargetLowering *getTargetLowering() const override { return &TLInfo; } const ARMFrameLowering *getFrameLowering() const override { return FrameLowering.get(); } const ARMBaseRegisterInfo *getRegisterInfo() const override { return &InstrInfo->getRegisterInfo(); } const CallLowering *getCallLowering() const override; const InstructionSelector *getInstructionSelector() const override; const LegalizerInfo *getLegalizerInfo() const override; const RegisterBankInfo *getRegBankInfo() const override; private: ARMSelectionDAGInfo TSInfo; // Either Thumb1FrameLowering or ARMFrameLowering. std::unique_ptr FrameLowering; // Either Thumb1InstrInfo or Thumb2InstrInfo. std::unique_ptr InstrInfo; ARMTargetLowering TLInfo; /// GlobalISel related APIs. std::unique_ptr CallLoweringInfo; std::unique_ptr InstSelector; std::unique_ptr Legalizer; std::unique_ptr RegBankInfo; void initializeEnvironment(); void initSubtargetFeatures(StringRef CPU, StringRef FS); ARMFrameLowering *initializeFrameLowering(StringRef CPU, StringRef FS); public: void computeIssueWidth(); bool hasV4TOps() const { return HasV4TOps; } bool hasV5TOps() const { return HasV5TOps; } bool hasV5TEOps() const { return HasV5TEOps; } bool hasV6Ops() const { return HasV6Ops; } bool hasV6MOps() const { return HasV6MOps; } bool hasV6KOps() const { return HasV6KOps; } bool hasV6T2Ops() const { return HasV6T2Ops; } bool hasV7Ops() const { return HasV7Ops; } bool hasV8Ops() const { return HasV8Ops; } bool hasV8_1aOps() const { return HasV8_1aOps; } bool hasV8_2aOps() const { return HasV8_2aOps; } bool hasV8_3aOps() const { return HasV8_3aOps; } bool hasV8_4aOps() const { return HasV8_4aOps; } bool hasV8_5aOps() const { return HasV8_5aOps; } bool hasV8MBaselineOps() const { return HasV8MBaselineOps; } bool hasV8MMainlineOps() const { return HasV8MMainlineOps; } bool hasV8_1MMainlineOps() const { return HasV8_1MMainlineOps; } bool hasMVEIntegerOps() const { return HasMVEIntegerOps; } bool hasMVEFloatOps() const { return HasMVEFloatOps; } bool hasFPRegs() const { return HasFPRegs; } bool hasFPRegs16() const { return HasFPRegs16; } bool hasFPRegs64() const { return HasFPRegs64; } /// @{ /// These functions are obsolete, please consider adding subtarget features /// or properties instead of calling them. bool isCortexA5() const { return ARMProcFamily == CortexA5; } bool isCortexA7() const { return ARMProcFamily == CortexA7; } bool isCortexA8() const { return ARMProcFamily == CortexA8; } bool isCortexA9() const { return ARMProcFamily == CortexA9; } bool isCortexA15() const { return ARMProcFamily == CortexA15; } bool isSwift() const { return ARMProcFamily == Swift; } bool isCortexM3() const { return ARMProcFamily == CortexM3; } bool isLikeA9() const { return isCortexA9() || isCortexA15() || isKrait(); } bool isCortexR5() const { return ARMProcFamily == CortexR5; } bool isKrait() const { return ARMProcFamily == Krait; } /// @} bool hasARMOps() const { return !NoARM; } - bool hasVFP2Base() const { return HasVFPv2D16SP; } + bool hasVFP2Base() const { return HasVFPv2SP; } bool hasVFP3Base() const { return HasVFPv3D16SP; } bool hasVFP4Base() const { return HasVFPv4D16SP; } bool hasFPARMv8Base() const { return HasFPARMv8D16SP; } bool hasNEON() const { return HasNEON; } bool hasSHA2() const { return HasSHA2; } bool hasAES() const { return HasAES; } bool hasCrypto() const { return HasCrypto; } bool hasDotProd() const { return HasDotProd; } bool hasCRC() const { return HasCRC; } bool hasRAS() const { return HasRAS; } bool hasLOB() const { return HasLOB; } bool hasVirtualization() const { return HasVirtualization; } bool useNEONForSinglePrecisionFP() const { return hasNEON() && UseNEONForSinglePrecisionFP; } bool hasDivideInThumbMode() const { return HasHardwareDivideInThumb; } bool hasDivideInARMMode() const { return HasHardwareDivideInARM; } bool hasDataBarrier() const { return HasDataBarrier; } bool hasFullDataBarrier() const { return HasFullDataBarrier; } bool hasV7Clrex() const { return HasV7Clrex; } bool hasAcquireRelease() const { return HasAcquireRelease; } bool hasAnyDataBarrier() const { return HasDataBarrier || (hasV6Ops() && !isThumb()); } bool useMulOps() const { return UseMulOps; } bool useFPVMLx() const { return !SlowFPVMLx; } bool hasVMLxForwarding() const { return HasVMLxForwarding; } bool isFPBrccSlow() const { return SlowFPBrcc; } bool hasFP64() const { return HasFP64; } bool hasPerfMon() const { return HasPerfMon; } bool hasTrustZone() const { return HasTrustZone; } bool has8MSecExt() const { return Has8MSecExt; } bool hasZeroCycleZeroing() const { return HasZeroCycleZeroing; } bool hasFPAO() const { return HasFPAO; } bool isProfitableToUnpredicate() const { return IsProfitableToUnpredicate; } bool hasSlowVGETLNi32() const { return HasSlowVGETLNi32; } bool hasSlowVDUP32() const { return HasSlowVDUP32; } bool preferVMOVSR() const { return PreferVMOVSR; } bool preferISHSTBarriers() const { return PreferISHST; } bool expandMLx() const { return ExpandMLx; } bool hasVMLxHazards() const { return HasVMLxHazards; } bool hasSlowOddRegister() const { return SlowOddRegister; } bool hasSlowLoadDSubregister() const { return SlowLoadDSubregister; } bool useWideStrideVFP() const { return UseWideStrideVFP; } bool hasMuxedUnits() const { return HasMuxedUnits; } bool dontWidenVMOVS() const { return DontWidenVMOVS; } bool useSplatVFPToNeon() const { return SplatVFPToNeon; } bool useNEONForFPMovs() const { return UseNEONForFPMovs; } bool checkVLDnAccessAlignment() const { return CheckVLDnAlign; } bool nonpipelinedVFP() const { return NonpipelinedVFP; } bool prefers32BitThumb() const { return Pref32BitThumb; } bool avoidCPSRPartialUpdate() const { return AvoidCPSRPartialUpdate; } bool cheapPredicableCPSRDef() const { return CheapPredicableCPSRDef; } bool avoidMOVsShifterOperand() const { return AvoidMOVsShifterOperand; } bool hasRetAddrStack() const { return HasRetAddrStack; } bool hasBranchPredictor() const { return HasBranchPredictor; } bool hasMPExtension() const { return HasMPExtension; } bool hasDSP() const { return HasDSP; } bool useNaClTrap() const { return UseNaClTrap; } bool useSjLjEH() const { return UseSjLjEH; } bool hasSB() const { return HasSB; } bool genLongCalls() const { return GenLongCalls; } bool genExecuteOnly() const { return GenExecuteOnly; } bool hasFP16() const { return HasFP16; } bool hasD32() const { return HasD32; } bool hasFullFP16() const { return HasFullFP16; } bool hasFP16FML() const { return HasFP16FML; } bool hasFuseAES() const { return HasFuseAES; } bool hasFuseLiterals() const { return HasFuseLiterals; } /// Return true if the CPU supports any kind of instruction fusion. bool hasFusion() const { return hasFuseAES() || hasFuseLiterals(); } const Triple &getTargetTriple() const { return TargetTriple; } bool isTargetDarwin() const { return TargetTriple.isOSDarwin(); } bool isTargetIOS() const { return TargetTriple.isiOS(); } bool isTargetWatchOS() const { return TargetTriple.isWatchOS(); } bool isTargetWatchABI() const { return TargetTriple.isWatchABI(); } bool isTargetLinux() const { return TargetTriple.isOSLinux(); } bool isTargetNaCl() const { return TargetTriple.isOSNaCl(); } bool isTargetNetBSD() const { return TargetTriple.isOSNetBSD(); } bool isTargetWindows() const { return TargetTriple.isOSWindows(); } bool isTargetCOFF() const { return TargetTriple.isOSBinFormatCOFF(); } bool isTargetELF() const { return TargetTriple.isOSBinFormatELF(); } bool isTargetMachO() const { return TargetTriple.isOSBinFormatMachO(); } // ARM EABI is the bare-metal EABI described in ARM ABI documents and // can be accessed via -target arm-none-eabi. This is NOT GNUEABI. // FIXME: Add a flag for bare-metal for that target and set Triple::EABI // even for GNUEABI, so we can make a distinction here and still conform to // the EABI on GNU (and Android) mode. This requires change in Clang, too. // FIXME: The Darwin exception is temporary, while we move users to // "*-*-*-macho" triples as quickly as possible. bool isTargetAEABI() const { return (TargetTriple.getEnvironment() == Triple::EABI || TargetTriple.getEnvironment() == Triple::EABIHF) && !isTargetDarwin() && !isTargetWindows(); } bool isTargetGNUAEABI() const { return (TargetTriple.getEnvironment() == Triple::GNUEABI || TargetTriple.getEnvironment() == Triple::GNUEABIHF) && !isTargetDarwin() && !isTargetWindows(); } bool isTargetMuslAEABI() const { return (TargetTriple.getEnvironment() == Triple::MuslEABI || TargetTriple.getEnvironment() == Triple::MuslEABIHF) && !isTargetDarwin() && !isTargetWindows(); } // ARM Targets that support EHABI exception handling standard // Darwin uses SjLj. Other targets might need more checks. bool isTargetEHABICompatible() const { return (TargetTriple.getEnvironment() == Triple::EABI || TargetTriple.getEnvironment() == Triple::GNUEABI || TargetTriple.getEnvironment() == Triple::MuslEABI || TargetTriple.getEnvironment() == Triple::EABIHF || TargetTriple.getEnvironment() == Triple::GNUEABIHF || TargetTriple.getEnvironment() == Triple::MuslEABIHF || isTargetAndroid()) && !isTargetDarwin() && !isTargetWindows(); } bool isTargetHardFloat() const; bool isTargetAndroid() const { return TargetTriple.isAndroid(); } bool isXRaySupported() const override; bool isAPCS_ABI() const; bool isAAPCS_ABI() const; bool isAAPCS16_ABI() const; bool isROPI() const; bool isRWPI() const; bool useMachineScheduler() const { return UseMISched; } bool disablePostRAScheduler() const { return DisablePostRAScheduler; } bool useSoftFloat() const { return UseSoftFloat; } bool isThumb() const { return InThumbMode; } bool hasMinSize() const { return OptMinSize; } bool isThumb1Only() const { return InThumbMode && !HasThumb2; } bool isThumb2() const { return InThumbMode && HasThumb2; } bool hasThumb2() const { return HasThumb2; } bool isMClass() const { return ARMProcClass == MClass; } bool isRClass() const { return ARMProcClass == RClass; } bool isAClass() const { return ARMProcClass == AClass; } bool isReadTPHard() const { return ReadTPHard; } bool isR9Reserved() const { return isTargetMachO() ? (ReserveR9 || !HasV6Ops) : ReserveR9; } bool useR7AsFramePointer() const { return isTargetDarwin() || (!isTargetWindows() && isThumb()); } /// Returns true if the frame setup is split into two separate pushes (first /// r0-r7,lr then r8-r11), principally so that the frame pointer is adjacent /// to lr. This is always required on Thumb1-only targets, as the push and /// pop instructions can't access the high registers. bool splitFramePushPop(const MachineFunction &MF) const { return (useR7AsFramePointer() && MF.getTarget().Options.DisableFramePointerElim(MF)) || isThumb1Only(); } bool useStride4VFPs() const; bool useMovt() const; bool supportsTailCall() const { return SupportsTailCall; } bool allowsUnalignedMem() const { return !StrictAlign; } bool restrictIT() const { return RestrictIT; } const std::string & getCPUString() const { return CPUString; } bool isLittle() const { return IsLittle; } unsigned getMispredictionPenalty() const; /// Returns true if machine scheduler should be enabled. bool enableMachineScheduler() const override; /// True for some subtargets at > -O0. bool enablePostRAScheduler() const override; /// Enable use of alias analysis during code generation (during MI /// scheduling, DAGCombine, etc.). bool useAA() const override { return UseAA; } // enableAtomicExpand- True if we need to expand our atomics. bool enableAtomicExpand() const override; /// getInstrItins - Return the instruction itineraries based on subtarget /// selection. const InstrItineraryData *getInstrItineraryData() const override { return &InstrItins; } /// getStackAlignment - Returns the minimum alignment known to hold of the /// stack frame on entry to the function and which must be maintained by every /// function for this subtarget. unsigned getStackAlignment() const { return stackAlignment; } unsigned getMaxInterleaveFactor() const { return MaxInterleaveFactor; } unsigned getPartialUpdateClearance() const { return PartialUpdateClearance; } ARMLdStMultipleTiming getLdStMultipleTiming() const { return LdStMultipleTiming; } int getPreISelOperandLatencyAdjustment() const { return PreISelOperandLatencyAdjustment; } /// True if the GV will be accessed via an indirect symbol. bool isGVIndirectSymbol(const GlobalValue *GV) const; /// Returns the constant pool modifier needed to access the GV. bool isGVInGOT(const GlobalValue *GV) const; /// True if fast-isel is used. bool useFastISel() const; /// Returns the correct return opcode for the current feature set. /// Use BX if available to allow mixing thumb/arm code, but fall back /// to plain mov pc,lr on ARMv4. unsigned getReturnOpcode() const { if (isThumb()) return ARM::tBX_RET; if (hasV4TOps()) return ARM::BX_RET; return ARM::MOVPCLR; } /// Allow movt+movw for PIC global address calculation. /// ELF does not have GOT relocations for movt+movw. /// ROPI does not use GOT. bool allowPositionIndependentMovt() const { return isROPI() || !isTargetELF(); } unsigned getPrefLoopAlignment() const { return PrefLoopAlignment; } bool ignoreCSRForAllocationOrder(const MachineFunction &MF, unsigned PhysReg) const override; unsigned getGPRAllocationOrder(const MachineFunction &MF) const; }; } // end namespace llvm #endif // LLVM_LIB_TARGET_ARM_ARMSUBTARGET_H Index: head/contrib/llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp =================================================================== --- head/contrib/llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp (revision 354096) +++ head/contrib/llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp (revision 354097) @@ -1,11891 +1,11891 @@ //===- ARMAsmParser.cpp - Parse ARM assembly to MCInst instructions -------===// // // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. // See https://llvm.org/LICENSE.txt for license information. // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception // //===----------------------------------------------------------------------===// #include "ARMFeatures.h" #include "ARMBaseInstrInfo.h" #include "Utils/ARMBaseInfo.h" #include "MCTargetDesc/ARMAddressingModes.h" #include "MCTargetDesc/ARMBaseInfo.h" #include "MCTargetDesc/ARMInstPrinter.h" #include "MCTargetDesc/ARMMCExpr.h" #include "MCTargetDesc/ARMMCTargetDesc.h" #include "TargetInfo/ARMTargetInfo.h" #include "llvm/ADT/APFloat.h" #include "llvm/ADT/APInt.h" #include "llvm/ADT/None.h" #include "llvm/ADT/STLExtras.h" #include "llvm/ADT/SmallSet.h" #include "llvm/ADT/SmallVector.h" #include "llvm/ADT/StringMap.h" #include "llvm/ADT/StringRef.h" #include "llvm/ADT/StringSwitch.h" #include "llvm/ADT/Triple.h" #include "llvm/ADT/Twine.h" #include "llvm/MC/MCContext.h" #include "llvm/MC/MCExpr.h" #include "llvm/MC/MCInst.h" #include "llvm/MC/MCInstrDesc.h" #include "llvm/MC/MCInstrInfo.h" #include "llvm/MC/MCObjectFileInfo.h" #include "llvm/MC/MCParser/MCAsmLexer.h" #include "llvm/MC/MCParser/MCAsmParser.h" #include "llvm/MC/MCParser/MCAsmParserExtension.h" #include "llvm/MC/MCParser/MCAsmParserUtils.h" #include "llvm/MC/MCParser/MCParsedAsmOperand.h" #include "llvm/MC/MCParser/MCTargetAsmParser.h" #include "llvm/MC/MCRegisterInfo.h" #include "llvm/MC/MCSection.h" #include "llvm/MC/MCStreamer.h" #include "llvm/MC/MCSubtargetInfo.h" #include "llvm/MC/MCSymbol.h" #include "llvm/MC/SubtargetFeature.h" #include "llvm/Support/ARMBuildAttributes.h" #include "llvm/Support/ARMEHABI.h" #include "llvm/Support/Casting.h" #include "llvm/Support/CommandLine.h" #include "llvm/Support/Compiler.h" #include "llvm/Support/ErrorHandling.h" #include "llvm/Support/MathExtras.h" #include "llvm/Support/SMLoc.h" #include "llvm/Support/TargetParser.h" #include "llvm/Support/TargetRegistry.h" #include "llvm/Support/raw_ostream.h" #include #include #include #include #include #include #include #include #include #include #define DEBUG_TYPE "asm-parser" using namespace llvm; namespace llvm { extern const MCInstrDesc ARMInsts[]; } // end namespace llvm namespace { enum class ImplicitItModeTy { Always, Never, ARMOnly, ThumbOnly }; static cl::opt ImplicitItMode( "arm-implicit-it", cl::init(ImplicitItModeTy::ARMOnly), cl::desc("Allow conditional instructions outdside of an IT block"), cl::values(clEnumValN(ImplicitItModeTy::Always, "always", "Accept in both ISAs, emit implicit ITs in Thumb"), clEnumValN(ImplicitItModeTy::Never, "never", "Warn in ARM, reject in Thumb"), clEnumValN(ImplicitItModeTy::ARMOnly, "arm", "Accept in ARM, reject in Thumb"), clEnumValN(ImplicitItModeTy::ThumbOnly, "thumb", "Warn in ARM, emit implicit ITs in Thumb"))); static cl::opt AddBuildAttributes("arm-add-build-attributes", cl::init(false)); enum VectorLaneTy { NoLanes, AllLanes, IndexedLane }; static inline unsigned extractITMaskBit(unsigned Mask, unsigned Position) { // Position==0 means we're not in an IT block at all. Position==1 // means we want the first state bit, which is always 0 (Then). // Position==2 means we want the second state bit, stored at bit 3 // of Mask, and so on downwards. So (5 - Position) will shift the // right bit down to bit 0, including the always-0 bit at bit 4 for // the mandatory initial Then. return (Mask >> (5 - Position) & 1); } class UnwindContext { using Locs = SmallVector; MCAsmParser &Parser; Locs FnStartLocs; Locs CantUnwindLocs; Locs PersonalityLocs; Locs PersonalityIndexLocs; Locs HandlerDataLocs; int FPReg; public: UnwindContext(MCAsmParser &P) : Parser(P), FPReg(ARM::SP) {} bool hasFnStart() const { return !FnStartLocs.empty(); } bool cantUnwind() const { return !CantUnwindLocs.empty(); } bool hasHandlerData() const { return !HandlerDataLocs.empty(); } bool hasPersonality() const { return !(PersonalityLocs.empty() && PersonalityIndexLocs.empty()); } void recordFnStart(SMLoc L) { FnStartLocs.push_back(L); } void recordCantUnwind(SMLoc L) { CantUnwindLocs.push_back(L); } void recordPersonality(SMLoc L) { PersonalityLocs.push_back(L); } void recordHandlerData(SMLoc L) { HandlerDataLocs.push_back(L); } void recordPersonalityIndex(SMLoc L) { PersonalityIndexLocs.push_back(L); } void saveFPReg(int Reg) { FPReg = Reg; } int getFPReg() const { return FPReg; } void emitFnStartLocNotes() const { for (Locs::const_iterator FI = FnStartLocs.begin(), FE = FnStartLocs.end(); FI != FE; ++FI) Parser.Note(*FI, ".fnstart was specified here"); } void emitCantUnwindLocNotes() const { for (Locs::const_iterator UI = CantUnwindLocs.begin(), UE = CantUnwindLocs.end(); UI != UE; ++UI) Parser.Note(*UI, ".cantunwind was specified here"); } void emitHandlerDataLocNotes() const { for (Locs::const_iterator HI = HandlerDataLocs.begin(), HE = HandlerDataLocs.end(); HI != HE; ++HI) Parser.Note(*HI, ".handlerdata was specified here"); } void emitPersonalityLocNotes() const { for (Locs::const_iterator PI = PersonalityLocs.begin(), PE = PersonalityLocs.end(), PII = PersonalityIndexLocs.begin(), PIE = PersonalityIndexLocs.end(); PI != PE || PII != PIE;) { if (PI != PE && (PII == PIE || PI->getPointer() < PII->getPointer())) Parser.Note(*PI++, ".personality was specified here"); else if (PII != PIE && (PI == PE || PII->getPointer() < PI->getPointer())) Parser.Note(*PII++, ".personalityindex was specified here"); else llvm_unreachable(".personality and .personalityindex cannot be " "at the same location"); } } void reset() { FnStartLocs = Locs(); CantUnwindLocs = Locs(); PersonalityLocs = Locs(); HandlerDataLocs = Locs(); PersonalityIndexLocs = Locs(); FPReg = ARM::SP; } }; class ARMAsmParser : public MCTargetAsmParser { const MCRegisterInfo *MRI; UnwindContext UC; ARMTargetStreamer &getTargetStreamer() { assert(getParser().getStreamer().getTargetStreamer() && "do not have a target streamer"); MCTargetStreamer &TS = *getParser().getStreamer().getTargetStreamer(); return static_cast(TS); } // Map of register aliases registers via the .req directive. StringMap RegisterReqs; bool NextSymbolIsThumb; bool useImplicitITThumb() const { return ImplicitItMode == ImplicitItModeTy::Always || ImplicitItMode == ImplicitItModeTy::ThumbOnly; } bool useImplicitITARM() const { return ImplicitItMode == ImplicitItModeTy::Always || ImplicitItMode == ImplicitItModeTy::ARMOnly; } struct { ARMCC::CondCodes Cond; // Condition for IT block. unsigned Mask:4; // Condition mask for instructions. // Starting at first 1 (from lsb). // '1' condition as indicated in IT. // '0' inverse of condition (else). // Count of instructions in IT block is // 4 - trailingzeroes(mask) // Note that this does not have the same encoding // as in the IT instruction, which also depends // on the low bit of the condition code. unsigned CurPosition; // Current position in parsing of IT // block. In range [0,4], with 0 being the IT // instruction itself. Initialized according to // count of instructions in block. ~0U if no // active IT block. bool IsExplicit; // true - The IT instruction was present in the // input, we should not modify it. // false - The IT instruction was added // implicitly, we can extend it if that // would be legal. } ITState; SmallVector PendingConditionalInsts; void flushPendingInstructions(MCStreamer &Out) override { if (!inImplicitITBlock()) { assert(PendingConditionalInsts.size() == 0); return; } // Emit the IT instruction MCInst ITInst; ITInst.setOpcode(ARM::t2IT); ITInst.addOperand(MCOperand::createImm(ITState.Cond)); ITInst.addOperand(MCOperand::createImm(ITState.Mask)); Out.EmitInstruction(ITInst, getSTI()); // Emit the conditonal instructions assert(PendingConditionalInsts.size() <= 4); for (const MCInst &Inst : PendingConditionalInsts) { Out.EmitInstruction(Inst, getSTI()); } PendingConditionalInsts.clear(); // Clear the IT state ITState.Mask = 0; ITState.CurPosition = ~0U; } bool inITBlock() { return ITState.CurPosition != ~0U; } bool inExplicitITBlock() { return inITBlock() && ITState.IsExplicit; } bool inImplicitITBlock() { return inITBlock() && !ITState.IsExplicit; } bool lastInITBlock() { return ITState.CurPosition == 4 - countTrailingZeros(ITState.Mask); } void forwardITPosition() { if (!inITBlock()) return; // Move to the next instruction in the IT block, if there is one. If not, // mark the block as done, except for implicit IT blocks, which we leave // open until we find an instruction that can't be added to it. unsigned TZ = countTrailingZeros(ITState.Mask); if (++ITState.CurPosition == 5 - TZ && ITState.IsExplicit) ITState.CurPosition = ~0U; // Done with the IT block after this. } // Rewind the state of the current IT block, removing the last slot from it. void rewindImplicitITPosition() { assert(inImplicitITBlock()); assert(ITState.CurPosition > 1); ITState.CurPosition--; unsigned TZ = countTrailingZeros(ITState.Mask); unsigned NewMask = 0; NewMask |= ITState.Mask & (0xC << TZ); NewMask |= 0x2 << TZ; ITState.Mask = NewMask; } // Rewind the state of the current IT block, removing the last slot from it. // If we were at the first slot, this closes the IT block. void discardImplicitITBlock() { assert(inImplicitITBlock()); assert(ITState.CurPosition == 1); ITState.CurPosition = ~0U; } // Return the low-subreg of a given Q register. unsigned getDRegFromQReg(unsigned QReg) const { return MRI->getSubReg(QReg, ARM::dsub_0); } // Get the condition code corresponding to the current IT block slot. ARMCC::CondCodes currentITCond() { unsigned MaskBit = extractITMaskBit(ITState.Mask, ITState.CurPosition); return MaskBit ? ARMCC::getOppositeCondition(ITState.Cond) : ITState.Cond; } // Invert the condition of the current IT block slot without changing any // other slots in the same block. void invertCurrentITCondition() { if (ITState.CurPosition == 1) { ITState.Cond = ARMCC::getOppositeCondition(ITState.Cond); } else { ITState.Mask ^= 1 << (5 - ITState.CurPosition); } } // Returns true if the current IT block is full (all 4 slots used). bool isITBlockFull() { return inITBlock() && (ITState.Mask & 1); } // Extend the current implicit IT block to have one more slot with the given // condition code. void extendImplicitITBlock(ARMCC::CondCodes Cond) { assert(inImplicitITBlock()); assert(!isITBlockFull()); assert(Cond == ITState.Cond || Cond == ARMCC::getOppositeCondition(ITState.Cond)); unsigned TZ = countTrailingZeros(ITState.Mask); unsigned NewMask = 0; // Keep any existing condition bits. NewMask |= ITState.Mask & (0xE << TZ); // Insert the new condition bit. NewMask |= (Cond != ITState.Cond) << TZ; // Move the trailing 1 down one bit. NewMask |= 1 << (TZ - 1); ITState.Mask = NewMask; } // Create a new implicit IT block with a dummy condition code. void startImplicitITBlock() { assert(!inITBlock()); ITState.Cond = ARMCC::AL; ITState.Mask = 8; ITState.CurPosition = 1; ITState.IsExplicit = false; } // Create a new explicit IT block with the given condition and mask. // The mask should be in the format used in ARMOperand and // MCOperand, with a 1 implying 'e', regardless of the low bit of // the condition. void startExplicitITBlock(ARMCC::CondCodes Cond, unsigned Mask) { assert(!inITBlock()); ITState.Cond = Cond; ITState.Mask = Mask; ITState.CurPosition = 0; ITState.IsExplicit = true; } struct { unsigned Mask : 4; unsigned CurPosition; } VPTState; bool inVPTBlock() { return VPTState.CurPosition != ~0U; } void forwardVPTPosition() { if (!inVPTBlock()) return; unsigned TZ = countTrailingZeros(VPTState.Mask); if (++VPTState.CurPosition == 5 - TZ) VPTState.CurPosition = ~0U; } void Note(SMLoc L, const Twine &Msg, SMRange Range = None) { return getParser().Note(L, Msg, Range); } bool Warning(SMLoc L, const Twine &Msg, SMRange Range = None) { return getParser().Warning(L, Msg, Range); } bool Error(SMLoc L, const Twine &Msg, SMRange Range = None) { return getParser().Error(L, Msg, Range); } bool validatetLDMRegList(const MCInst &Inst, const OperandVector &Operands, unsigned ListNo, bool IsARPop = false); bool validatetSTMRegList(const MCInst &Inst, const OperandVector &Operands, unsigned ListNo); int tryParseRegister(); bool tryParseRegisterWithWriteBack(OperandVector &); int tryParseShiftRegister(OperandVector &); bool parseRegisterList(OperandVector &, bool EnforceOrder = true); bool parseMemory(OperandVector &); bool parseOperand(OperandVector &, StringRef Mnemonic); bool parsePrefix(ARMMCExpr::VariantKind &RefKind); bool parseMemRegOffsetShift(ARM_AM::ShiftOpc &ShiftType, unsigned &ShiftAmount); bool parseLiteralValues(unsigned Size, SMLoc L); bool parseDirectiveThumb(SMLoc L); bool parseDirectiveARM(SMLoc L); bool parseDirectiveThumbFunc(SMLoc L); bool parseDirectiveCode(SMLoc L); bool parseDirectiveSyntax(SMLoc L); bool parseDirectiveReq(StringRef Name, SMLoc L); bool parseDirectiveUnreq(SMLoc L); bool parseDirectiveArch(SMLoc L); bool parseDirectiveEabiAttr(SMLoc L); bool parseDirectiveCPU(SMLoc L); bool parseDirectiveFPU(SMLoc L); bool parseDirectiveFnStart(SMLoc L); bool parseDirectiveFnEnd(SMLoc L); bool parseDirectiveCantUnwind(SMLoc L); bool parseDirectivePersonality(SMLoc L); bool parseDirectiveHandlerData(SMLoc L); bool parseDirectiveSetFP(SMLoc L); bool parseDirectivePad(SMLoc L); bool parseDirectiveRegSave(SMLoc L, bool IsVector); bool parseDirectiveInst(SMLoc L, char Suffix = '\0'); bool parseDirectiveLtorg(SMLoc L); bool parseDirectiveEven(SMLoc L); bool parseDirectivePersonalityIndex(SMLoc L); bool parseDirectiveUnwindRaw(SMLoc L); bool parseDirectiveTLSDescSeq(SMLoc L); bool parseDirectiveMovSP(SMLoc L); bool parseDirectiveObjectArch(SMLoc L); bool parseDirectiveArchExtension(SMLoc L); bool parseDirectiveAlign(SMLoc L); bool parseDirectiveThumbSet(SMLoc L); bool isMnemonicVPTPredicable(StringRef Mnemonic, StringRef ExtraToken); StringRef splitMnemonic(StringRef Mnemonic, StringRef ExtraToken, unsigned &PredicationCode, unsigned &VPTPredicationCode, bool &CarrySetting, unsigned &ProcessorIMod, StringRef &ITMask); void getMnemonicAcceptInfo(StringRef Mnemonic, StringRef ExtraToken, StringRef FullInst, bool &CanAcceptCarrySet, bool &CanAcceptPredicationCode, bool &CanAcceptVPTPredicationCode); void tryConvertingToTwoOperandForm(StringRef Mnemonic, bool CarrySetting, OperandVector &Operands); bool isThumb() const { // FIXME: Can tablegen auto-generate this? return getSTI().getFeatureBits()[ARM::ModeThumb]; } bool isThumbOne() const { return isThumb() && !getSTI().getFeatureBits()[ARM::FeatureThumb2]; } bool isThumbTwo() const { return isThumb() && getSTI().getFeatureBits()[ARM::FeatureThumb2]; } bool hasThumb() const { return getSTI().getFeatureBits()[ARM::HasV4TOps]; } bool hasThumb2() const { return getSTI().getFeatureBits()[ARM::FeatureThumb2]; } bool hasV6Ops() const { return getSTI().getFeatureBits()[ARM::HasV6Ops]; } bool hasV6T2Ops() const { return getSTI().getFeatureBits()[ARM::HasV6T2Ops]; } bool hasV6MOps() const { return getSTI().getFeatureBits()[ARM::HasV6MOps]; } bool hasV7Ops() const { return getSTI().getFeatureBits()[ARM::HasV7Ops]; } bool hasV8Ops() const { return getSTI().getFeatureBits()[ARM::HasV8Ops]; } bool hasV8MBaseline() const { return getSTI().getFeatureBits()[ARM::HasV8MBaselineOps]; } bool hasV8MMainline() const { return getSTI().getFeatureBits()[ARM::HasV8MMainlineOps]; } bool hasV8_1MMainline() const { return getSTI().getFeatureBits()[ARM::HasV8_1MMainlineOps]; } bool hasMVE() const { return getSTI().getFeatureBits()[ARM::HasMVEIntegerOps]; } bool hasMVEFloat() const { return getSTI().getFeatureBits()[ARM::HasMVEFloatOps]; } bool has8MSecExt() const { return getSTI().getFeatureBits()[ARM::Feature8MSecExt]; } bool hasARM() const { return !getSTI().getFeatureBits()[ARM::FeatureNoARM]; } bool hasDSP() const { return getSTI().getFeatureBits()[ARM::FeatureDSP]; } bool hasD32() const { return getSTI().getFeatureBits()[ARM::FeatureD32]; } bool hasV8_1aOps() const { return getSTI().getFeatureBits()[ARM::HasV8_1aOps]; } bool hasRAS() const { return getSTI().getFeatureBits()[ARM::FeatureRAS]; } void SwitchMode() { MCSubtargetInfo &STI = copySTI(); auto FB = ComputeAvailableFeatures(STI.ToggleFeature(ARM::ModeThumb)); setAvailableFeatures(FB); } void FixModeAfterArchChange(bool WasThumb, SMLoc Loc); bool isMClass() const { return getSTI().getFeatureBits()[ARM::FeatureMClass]; } /// @name Auto-generated Match Functions /// { #define GET_ASSEMBLER_HEADER #include "ARMGenAsmMatcher.inc" /// } OperandMatchResultTy parseITCondCode(OperandVector &); OperandMatchResultTy parseCoprocNumOperand(OperandVector &); OperandMatchResultTy parseCoprocRegOperand(OperandVector &); OperandMatchResultTy parseCoprocOptionOperand(OperandVector &); OperandMatchResultTy parseMemBarrierOptOperand(OperandVector &); OperandMatchResultTy parseTraceSyncBarrierOptOperand(OperandVector &); OperandMatchResultTy parseInstSyncBarrierOptOperand(OperandVector &); OperandMatchResultTy parseProcIFlagsOperand(OperandVector &); OperandMatchResultTy parseMSRMaskOperand(OperandVector &); OperandMatchResultTy parseBankedRegOperand(OperandVector &); OperandMatchResultTy parsePKHImm(OperandVector &O, StringRef Op, int Low, int High); OperandMatchResultTy parsePKHLSLImm(OperandVector &O) { return parsePKHImm(O, "lsl", 0, 31); } OperandMatchResultTy parsePKHASRImm(OperandVector &O) { return parsePKHImm(O, "asr", 1, 32); } OperandMatchResultTy parseSetEndImm(OperandVector &); OperandMatchResultTy parseShifterImm(OperandVector &); OperandMatchResultTy parseRotImm(OperandVector &); OperandMatchResultTy parseModImm(OperandVector &); OperandMatchResultTy parseBitfield(OperandVector &); OperandMatchResultTy parsePostIdxReg(OperandVector &); OperandMatchResultTy parseAM3Offset(OperandVector &); OperandMatchResultTy parseFPImm(OperandVector &); OperandMatchResultTy parseVectorList(OperandVector &); OperandMatchResultTy parseVectorLane(VectorLaneTy &LaneKind, unsigned &Index, SMLoc &EndLoc); // Asm Match Converter Methods void cvtThumbMultiply(MCInst &Inst, const OperandVector &); void cvtThumbBranches(MCInst &Inst, const OperandVector &); void cvtMVEVMOVQtoDReg(MCInst &Inst, const OperandVector &); bool validateInstruction(MCInst &Inst, const OperandVector &Ops); bool processInstruction(MCInst &Inst, const OperandVector &Ops, MCStreamer &Out); bool shouldOmitCCOutOperand(StringRef Mnemonic, OperandVector &Operands); bool shouldOmitPredicateOperand(StringRef Mnemonic, OperandVector &Operands); bool shouldOmitVectorPredicateOperand(StringRef Mnemonic, OperandVector &Operands); bool isITBlockTerminator(MCInst &Inst) const; void fixupGNULDRDAlias(StringRef Mnemonic, OperandVector &Operands); bool validateLDRDSTRD(MCInst &Inst, const OperandVector &Operands, bool Load, bool ARMMode, bool Writeback); public: enum ARMMatchResultTy { Match_RequiresITBlock = FIRST_TARGET_MATCH_RESULT_TY, Match_RequiresNotITBlock, Match_RequiresV6, Match_RequiresThumb2, Match_RequiresV8, Match_RequiresFlagSetting, #define GET_OPERAND_DIAGNOSTIC_TYPES #include "ARMGenAsmMatcher.inc" }; ARMAsmParser(const MCSubtargetInfo &STI, MCAsmParser &Parser, const MCInstrInfo &MII, const MCTargetOptions &Options) : MCTargetAsmParser(Options, STI, MII), UC(Parser) { MCAsmParserExtension::Initialize(Parser); // Cache the MCRegisterInfo. MRI = getContext().getRegisterInfo(); // Initialize the set of available features. setAvailableFeatures(ComputeAvailableFeatures(STI.getFeatureBits())); // Add build attributes based on the selected target. if (AddBuildAttributes) getTargetStreamer().emitTargetAttributes(STI); // Not in an ITBlock to start with. ITState.CurPosition = ~0U; VPTState.CurPosition = ~0U; NextSymbolIsThumb = false; } // Implementation of the MCTargetAsmParser interface: bool ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc) override; bool ParseInstruction(ParseInstructionInfo &Info, StringRef Name, SMLoc NameLoc, OperandVector &Operands) override; bool ParseDirective(AsmToken DirectiveID) override; unsigned validateTargetOperandClass(MCParsedAsmOperand &Op, unsigned Kind) override; unsigned checkTargetMatchPredicate(MCInst &Inst) override; bool MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode, OperandVector &Operands, MCStreamer &Out, uint64_t &ErrorInfo, bool MatchingInlineAsm) override; unsigned MatchInstruction(OperandVector &Operands, MCInst &Inst, SmallVectorImpl &NearMisses, bool MatchingInlineAsm, bool &EmitInITBlock, MCStreamer &Out); struct NearMissMessage { SMLoc Loc; SmallString<128> Message; }; const char *getCustomOperandDiag(ARMMatchResultTy MatchError); void FilterNearMisses(SmallVectorImpl &NearMissesIn, SmallVectorImpl &NearMissesOut, SMLoc IDLoc, OperandVector &Operands); void ReportNearMisses(SmallVectorImpl &NearMisses, SMLoc IDLoc, OperandVector &Operands); void doBeforeLabelEmit(MCSymbol *Symbol) override; void onLabelParsed(MCSymbol *Symbol) override; }; /// ARMOperand - Instances of this class represent a parsed ARM machine /// operand. class ARMOperand : public MCParsedAsmOperand { enum KindTy { k_CondCode, k_VPTPred, k_CCOut, k_ITCondMask, k_CoprocNum, k_CoprocReg, k_CoprocOption, k_Immediate, k_MemBarrierOpt, k_InstSyncBarrierOpt, k_TraceSyncBarrierOpt, k_Memory, k_PostIndexRegister, k_MSRMask, k_BankedReg, k_ProcIFlags, k_VectorIndex, k_Register, k_RegisterList, k_RegisterListWithAPSR, k_DPRRegisterList, k_SPRRegisterList, k_FPSRegisterListWithVPR, k_FPDRegisterListWithVPR, k_VectorList, k_VectorListAllLanes, k_VectorListIndexed, k_ShiftedRegister, k_ShiftedImmediate, k_ShifterImmediate, k_RotateImmediate, k_ModifiedImmediate, k_ConstantPoolImmediate, k_BitfieldDescriptor, k_Token, } Kind; SMLoc StartLoc, EndLoc, AlignmentLoc; SmallVector Registers; struct CCOp { ARMCC::CondCodes Val; }; struct VCCOp { ARMVCC::VPTCodes Val; }; struct CopOp { unsigned Val; }; struct CoprocOptionOp { unsigned Val; }; struct ITMaskOp { unsigned Mask:4; }; struct MBOptOp { ARM_MB::MemBOpt Val; }; struct ISBOptOp { ARM_ISB::InstSyncBOpt Val; }; struct TSBOptOp { ARM_TSB::TraceSyncBOpt Val; }; struct IFlagsOp { ARM_PROC::IFlags Val; }; struct MMaskOp { unsigned Val; }; struct BankedRegOp { unsigned Val; }; struct TokOp { const char *Data; unsigned Length; }; struct RegOp { unsigned RegNum; }; // A vector register list is a sequential list of 1 to 4 registers. struct VectorListOp { unsigned RegNum; unsigned Count; unsigned LaneIndex; bool isDoubleSpaced; }; struct VectorIndexOp { unsigned Val; }; struct ImmOp { const MCExpr *Val; }; /// Combined record for all forms of ARM address expressions. struct MemoryOp { unsigned BaseRegNum; // Offset is in OffsetReg or OffsetImm. If both are zero, no offset // was specified. const MCConstantExpr *OffsetImm; // Offset immediate value unsigned OffsetRegNum; // Offset register num, when OffsetImm == NULL ARM_AM::ShiftOpc ShiftType; // Shift type for OffsetReg unsigned ShiftImm; // shift for OffsetReg. unsigned Alignment; // 0 = no alignment specified // n = alignment in bytes (2, 4, 8, 16, or 32) unsigned isNegative : 1; // Negated OffsetReg? (~'U' bit) }; struct PostIdxRegOp { unsigned RegNum; bool isAdd; ARM_AM::ShiftOpc ShiftTy; unsigned ShiftImm; }; struct ShifterImmOp { bool isASR; unsigned Imm; }; struct RegShiftedRegOp { ARM_AM::ShiftOpc ShiftTy; unsigned SrcReg; unsigned ShiftReg; unsigned ShiftImm; }; struct RegShiftedImmOp { ARM_AM::ShiftOpc ShiftTy; unsigned SrcReg; unsigned ShiftImm; }; struct RotImmOp { unsigned Imm; }; struct ModImmOp { unsigned Bits; unsigned Rot; }; struct BitfieldOp { unsigned LSB; unsigned Width; }; union { struct CCOp CC; struct VCCOp VCC; struct CopOp Cop; struct CoprocOptionOp CoprocOption; struct MBOptOp MBOpt; struct ISBOptOp ISBOpt; struct TSBOptOp TSBOpt; struct ITMaskOp ITMask; struct IFlagsOp IFlags; struct MMaskOp MMask; struct BankedRegOp BankedReg; struct TokOp Tok; struct RegOp Reg; struct VectorListOp VectorList; struct VectorIndexOp VectorIndex; struct ImmOp Imm; struct MemoryOp Memory; struct PostIdxRegOp PostIdxReg; struct ShifterImmOp ShifterImm; struct RegShiftedRegOp RegShiftedReg; struct RegShiftedImmOp RegShiftedImm; struct RotImmOp RotImm; struct ModImmOp ModImm; struct BitfieldOp Bitfield; }; public: ARMOperand(KindTy K) : MCParsedAsmOperand(), Kind(K) {} /// getStartLoc - Get the location of the first token of this operand. SMLoc getStartLoc() const override { return StartLoc; } /// getEndLoc - Get the location of the last token of this operand. SMLoc getEndLoc() const override { return EndLoc; } /// getLocRange - Get the range between the first and last token of this /// operand. SMRange getLocRange() const { return SMRange(StartLoc, EndLoc); } /// getAlignmentLoc - Get the location of the Alignment token of this operand. SMLoc getAlignmentLoc() const { assert(Kind == k_Memory && "Invalid access!"); return AlignmentLoc; } ARMCC::CondCodes getCondCode() const { assert(Kind == k_CondCode && "Invalid access!"); return CC.Val; } ARMVCC::VPTCodes getVPTPred() const { assert(isVPTPred() && "Invalid access!"); return VCC.Val; } unsigned getCoproc() const { assert((Kind == k_CoprocNum || Kind == k_CoprocReg) && "Invalid access!"); return Cop.Val; } StringRef getToken() const { assert(Kind == k_Token && "Invalid access!"); return StringRef(Tok.Data, Tok.Length); } unsigned getReg() const override { assert((Kind == k_Register || Kind == k_CCOut) && "Invalid access!"); return Reg.RegNum; } const SmallVectorImpl &getRegList() const { assert((Kind == k_RegisterList || Kind == k_RegisterListWithAPSR || Kind == k_DPRRegisterList || Kind == k_SPRRegisterList || Kind == k_FPSRegisterListWithVPR || Kind == k_FPDRegisterListWithVPR) && "Invalid access!"); return Registers; } const MCExpr *getImm() const { assert(isImm() && "Invalid access!"); return Imm.Val; } const MCExpr *getConstantPoolImm() const { assert(isConstantPoolImm() && "Invalid access!"); return Imm.Val; } unsigned getVectorIndex() const { assert(Kind == k_VectorIndex && "Invalid access!"); return VectorIndex.Val; } ARM_MB::MemBOpt getMemBarrierOpt() const { assert(Kind == k_MemBarrierOpt && "Invalid access!"); return MBOpt.Val; } ARM_ISB::InstSyncBOpt getInstSyncBarrierOpt() const { assert(Kind == k_InstSyncBarrierOpt && "Invalid access!"); return ISBOpt.Val; } ARM_TSB::TraceSyncBOpt getTraceSyncBarrierOpt() const { assert(Kind == k_TraceSyncBarrierOpt && "Invalid access!"); return TSBOpt.Val; } ARM_PROC::IFlags getProcIFlags() const { assert(Kind == k_ProcIFlags && "Invalid access!"); return IFlags.Val; } unsigned getMSRMask() const { assert(Kind == k_MSRMask && "Invalid access!"); return MMask.Val; } unsigned getBankedReg() const { assert(Kind == k_BankedReg && "Invalid access!"); return BankedReg.Val; } bool isCoprocNum() const { return Kind == k_CoprocNum; } bool isCoprocReg() const { return Kind == k_CoprocReg; } bool isCoprocOption() const { return Kind == k_CoprocOption; } bool isCondCode() const { return Kind == k_CondCode; } bool isVPTPred() const { return Kind == k_VPTPred; } bool isCCOut() const { return Kind == k_CCOut; } bool isITMask() const { return Kind == k_ITCondMask; } bool isITCondCode() const { return Kind == k_CondCode; } bool isImm() const override { return Kind == k_Immediate; } bool isARMBranchTarget() const { if (!isImm()) return false; if (const MCConstantExpr *CE = dyn_cast(getImm())) return CE->getValue() % 4 == 0; return true; } bool isThumbBranchTarget() const { if (!isImm()) return false; if (const MCConstantExpr *CE = dyn_cast(getImm())) return CE->getValue() % 2 == 0; return true; } // checks whether this operand is an unsigned offset which fits is a field // of specified width and scaled by a specific number of bits template bool isUnsignedOffset() const { if (!isImm()) return false; if (isa(Imm.Val)) return true; if (const MCConstantExpr *CE = dyn_cast(Imm.Val)) { int64_t Val = CE->getValue(); int64_t Align = 1LL << scale; int64_t Max = Align * ((1LL << width) - 1); return ((Val % Align) == 0) && (Val >= 0) && (Val <= Max); } return false; } // checks whether this operand is an signed offset which fits is a field // of specified width and scaled by a specific number of bits template bool isSignedOffset() const { if (!isImm()) return false; if (isa(Imm.Val)) return true; if (const MCConstantExpr *CE = dyn_cast(Imm.Val)) { int64_t Val = CE->getValue(); int64_t Align = 1LL << scale; int64_t Max = Align * ((1LL << (width-1)) - 1); int64_t Min = -Align * (1LL << (width-1)); return ((Val % Align) == 0) && (Val >= Min) && (Val <= Max); } return false; } // checks whether this operand is an offset suitable for the LE / // LETP instructions in Arm v8.1M bool isLEOffset() const { if (!isImm()) return false; if (isa(Imm.Val)) return true; if (const MCConstantExpr *CE = dyn_cast(Imm.Val)) { int64_t Val = CE->getValue(); return Val < 0 && Val >= -4094 && (Val & 1) == 0; } return false; } // checks whether this operand is a memory operand computed as an offset // applied to PC. the offset may have 8 bits of magnitude and is represented // with two bits of shift. textually it may be either [pc, #imm], #imm or // relocable expression... bool isThumbMemPC() const { int64_t Val = 0; if (isImm()) { if (isa(Imm.Val)) return true; const MCConstantExpr *CE = dyn_cast(Imm.Val); if (!CE) return false; Val = CE->getValue(); } else if (isGPRMem()) { if(!Memory.OffsetImm || Memory.OffsetRegNum) return false; if(Memory.BaseRegNum != ARM::PC) return false; Val = Memory.OffsetImm->getValue(); } else return false; return ((Val % 4) == 0) && (Val >= 0) && (Val <= 1020); } bool isFPImm() const { if (!isImm()) return false; const MCConstantExpr *CE = dyn_cast(getImm()); if (!CE) return false; int Val = ARM_AM::getFP32Imm(APInt(32, CE->getValue())); return Val != -1; } template bool isImmediate() const { if (!isImm()) return false; const MCConstantExpr *CE = dyn_cast(getImm()); if (!CE) return false; int64_t Value = CE->getValue(); return Value >= N && Value <= M; } template bool isImmediateS4() const { if (!isImm()) return false; const MCConstantExpr *CE = dyn_cast(getImm()); if (!CE) return false; int64_t Value = CE->getValue(); return ((Value & 3) == 0) && Value >= N && Value <= M; } template bool isImmediateS2() const { if (!isImm()) return false; const MCConstantExpr *CE = dyn_cast(getImm()); if (!CE) return false; int64_t Value = CE->getValue(); return ((Value & 1) == 0) && Value >= N && Value <= M; } bool isFBits16() const { return isImmediate<0, 17>(); } bool isFBits32() const { return isImmediate<1, 33>(); } bool isImm8s4() const { return isImmediateS4<-1020, 1020>(); } bool isImm7s4() const { return isImmediateS4<-508, 508>(); } bool isImm7Shift0() const { return isImmediate<-127, 127>(); } bool isImm7Shift1() const { return isImmediateS2<-255, 255>(); } bool isImm7Shift2() const { return isImmediateS4<-511, 511>(); } bool isImm7() const { return isImmediate<-127, 127>(); } bool isImm0_1020s4() const { return isImmediateS4<0, 1020>(); } bool isImm0_508s4() const { return isImmediateS4<0, 508>(); } bool isImm0_508s4Neg() const { if (!isImm()) return false; const MCConstantExpr *CE = dyn_cast(getImm()); if (!CE) return false; int64_t Value = -CE->getValue(); // explicitly exclude zero. we want that to use the normal 0_508 version. return ((Value & 3) == 0) && Value > 0 && Value <= 508; } bool isImm0_4095Neg() const { if (!isImm()) return false; const MCConstantExpr *CE = dyn_cast(getImm()); if (!CE) return false; // isImm0_4095Neg is used with 32-bit immediates only. // 32-bit immediates are zero extended to 64-bit when parsed, // thus simple -CE->getValue() results in a big negative number, // not a small positive number as intended if ((CE->getValue() >> 32) > 0) return false; uint32_t Value = -static_cast(CE->getValue()); return Value > 0 && Value < 4096; } bool isImm0_7() const { return isImmediate<0, 7>(); } bool isImm1_16() const { return isImmediate<1, 16>(); } bool isImm1_32() const { return isImmediate<1, 32>(); } bool isImm8_255() const { return isImmediate<8, 255>(); } bool isImm256_65535Expr() const { if (!isImm()) return false; const MCConstantExpr *CE = dyn_cast(getImm()); // If it's not a constant expression, it'll generate a fixup and be // handled later. if (!CE) return true; int64_t Value = CE->getValue(); return Value >= 256 && Value < 65536; } bool isImm0_65535Expr() const { if (!isImm()) return false; const MCConstantExpr *CE = dyn_cast(getImm()); // If it's not a constant expression, it'll generate a fixup and be // handled later. if (!CE) return true; int64_t Value = CE->getValue(); return Value >= 0 && Value < 65536; } bool isImm24bit() const { return isImmediate<0, 0xffffff + 1>(); } bool isImmThumbSR() const { return isImmediate<1, 33>(); } template bool isExpImmValue(uint64_t Value) const { uint64_t mask = (1 << shift) - 1; if ((Value & mask) != 0 || (Value >> shift) > 0xff) return false; return true; } template bool isExpImm() const { if (!isImm()) return false; const MCConstantExpr *CE = dyn_cast(getImm()); if (!CE) return false; return isExpImmValue(CE->getValue()); } template bool isInvertedExpImm() const { if (!isImm()) return false; const MCConstantExpr *CE = dyn_cast(getImm()); if (!CE) return false; uint64_t OriginalValue = CE->getValue(); uint64_t InvertedValue = OriginalValue ^ (((uint64_t)1 << size) - 1); return isExpImmValue(InvertedValue); } bool isPKHLSLImm() const { return isImmediate<0, 32>(); } bool isPKHASRImm() const { return isImmediate<0, 33>(); } bool isAdrLabel() const { // If we have an immediate that's not a constant, treat it as a label // reference needing a fixup. if (isImm() && !isa(getImm())) return true; // If it is a constant, it must fit into a modified immediate encoding. if (!isImm()) return false; const MCConstantExpr *CE = dyn_cast(getImm()); if (!CE) return false; int64_t Value = CE->getValue(); return (ARM_AM::getSOImmVal(Value) != -1 || ARM_AM::getSOImmVal(-Value) != -1); } bool isT2SOImm() const { // If we have an immediate that's not a constant, treat it as an expression // needing a fixup. if (isImm() && !isa(getImm())) { // We want to avoid matching :upper16: and :lower16: as we want these // expressions to match in isImm0_65535Expr() const ARMMCExpr *ARM16Expr = dyn_cast(getImm()); return (!ARM16Expr || (ARM16Expr->getKind() != ARMMCExpr::VK_ARM_HI16 && ARM16Expr->getKind() != ARMMCExpr::VK_ARM_LO16)); } if (!isImm()) return false; const MCConstantExpr *CE = dyn_cast(getImm()); if (!CE) return false; int64_t Value = CE->getValue(); return ARM_AM::getT2SOImmVal(Value) != -1; } bool isT2SOImmNot() const { if (!isImm()) return false; const MCConstantExpr *CE = dyn_cast(getImm()); if (!CE) return false; int64_t Value = CE->getValue(); return ARM_AM::getT2SOImmVal(Value) == -1 && ARM_AM::getT2SOImmVal(~Value) != -1; } bool isT2SOImmNeg() const { if (!isImm()) return false; const MCConstantExpr *CE = dyn_cast(getImm()); if (!CE) return false; int64_t Value = CE->getValue(); // Only use this when not representable as a plain so_imm. return ARM_AM::getT2SOImmVal(Value) == -1 && ARM_AM::getT2SOImmVal(-Value) != -1; } bool isSetEndImm() const { if (!isImm()) return false; const MCConstantExpr *CE = dyn_cast(getImm()); if (!CE) return false; int64_t Value = CE->getValue(); return Value == 1 || Value == 0; } bool isReg() const override { return Kind == k_Register; } bool isRegList() const { return Kind == k_RegisterList; } bool isRegListWithAPSR() const { return Kind == k_RegisterListWithAPSR || Kind == k_RegisterList; } bool isDPRRegList() const { return Kind == k_DPRRegisterList; } bool isSPRRegList() const { return Kind == k_SPRRegisterList; } bool isFPSRegListWithVPR() const { return Kind == k_FPSRegisterListWithVPR; } bool isFPDRegListWithVPR() const { return Kind == k_FPDRegisterListWithVPR; } bool isToken() const override { return Kind == k_Token; } bool isMemBarrierOpt() const { return Kind == k_MemBarrierOpt; } bool isInstSyncBarrierOpt() const { return Kind == k_InstSyncBarrierOpt; } bool isTraceSyncBarrierOpt() const { return Kind == k_TraceSyncBarrierOpt; } bool isMem() const override { return isGPRMem() || isMVEMem(); } bool isMVEMem() const { if (Kind != k_Memory) return false; if (Memory.BaseRegNum && !ARMMCRegisterClasses[ARM::GPRRegClassID].contains(Memory.BaseRegNum) && !ARMMCRegisterClasses[ARM::MQPRRegClassID].contains(Memory.BaseRegNum)) return false; if (Memory.OffsetRegNum && !ARMMCRegisterClasses[ARM::MQPRRegClassID].contains( Memory.OffsetRegNum)) return false; return true; } bool isGPRMem() const { if (Kind != k_Memory) return false; if (Memory.BaseRegNum && !ARMMCRegisterClasses[ARM::GPRRegClassID].contains(Memory.BaseRegNum)) return false; if (Memory.OffsetRegNum && !ARMMCRegisterClasses[ARM::GPRRegClassID].contains(Memory.OffsetRegNum)) return false; return true; } bool isShifterImm() const { return Kind == k_ShifterImmediate; } bool isRegShiftedReg() const { return Kind == k_ShiftedRegister && ARMMCRegisterClasses[ARM::GPRRegClassID].contains( RegShiftedReg.SrcReg) && ARMMCRegisterClasses[ARM::GPRRegClassID].contains( RegShiftedReg.ShiftReg); } bool isRegShiftedImm() const { return Kind == k_ShiftedImmediate && ARMMCRegisterClasses[ARM::GPRRegClassID].contains( RegShiftedImm.SrcReg); } bool isRotImm() const { return Kind == k_RotateImmediate; } template bool isPowerTwoInRange() const { if (!isImm()) return false; const MCConstantExpr *CE = dyn_cast(getImm()); if (!CE) return false; int64_t Value = CE->getValue(); return Value > 0 && countPopulation((uint64_t)Value) == 1 && Value >= Min && Value <= Max; } bool isModImm() const { return Kind == k_ModifiedImmediate; } bool isModImmNot() const { if (!isImm()) return false; const MCConstantExpr *CE = dyn_cast(getImm()); if (!CE) return false; int64_t Value = CE->getValue(); return ARM_AM::getSOImmVal(~Value) != -1; } bool isModImmNeg() const { if (!isImm()) return false; const MCConstantExpr *CE = dyn_cast(getImm()); if (!CE) return false; int64_t Value = CE->getValue(); return ARM_AM::getSOImmVal(Value) == -1 && ARM_AM::getSOImmVal(-Value) != -1; } bool isThumbModImmNeg1_7() const { if (!isImm()) return false; const MCConstantExpr *CE = dyn_cast(getImm()); if (!CE) return false; int32_t Value = -(int32_t)CE->getValue(); return 0 < Value && Value < 8; } bool isThumbModImmNeg8_255() const { if (!isImm()) return false; const MCConstantExpr *CE = dyn_cast(getImm()); if (!CE) return false; int32_t Value = -(int32_t)CE->getValue(); return 7 < Value && Value < 256; } bool isConstantPoolImm() const { return Kind == k_ConstantPoolImmediate; } bool isBitfield() const { return Kind == k_BitfieldDescriptor; } bool isPostIdxRegShifted() const { return Kind == k_PostIndexRegister && ARMMCRegisterClasses[ARM::GPRRegClassID].contains(PostIdxReg.RegNum); } bool isPostIdxReg() const { return isPostIdxRegShifted() && PostIdxReg.ShiftTy == ARM_AM::no_shift; } bool isMemNoOffset(bool alignOK = false, unsigned Alignment = 0) const { if (!isGPRMem()) return false; // No offset of any kind. return Memory.OffsetRegNum == 0 && Memory.OffsetImm == nullptr && (alignOK || Memory.Alignment == Alignment); } bool isMemNoOffsetT2(bool alignOK = false, unsigned Alignment = 0) const { if (!isGPRMem()) return false; if (!ARMMCRegisterClasses[ARM::GPRnopcRegClassID].contains( Memory.BaseRegNum)) return false; // No offset of any kind. return Memory.OffsetRegNum == 0 && Memory.OffsetImm == nullptr && (alignOK || Memory.Alignment == Alignment); } bool isMemNoOffsetT2NoSp(bool alignOK = false, unsigned Alignment = 0) const { if (!isGPRMem()) return false; if (!ARMMCRegisterClasses[ARM::rGPRRegClassID].contains( Memory.BaseRegNum)) return false; // No offset of any kind. return Memory.OffsetRegNum == 0 && Memory.OffsetImm == nullptr && (alignOK || Memory.Alignment == Alignment); } bool isMemNoOffsetT(bool alignOK = false, unsigned Alignment = 0) const { if (!isGPRMem()) return false; if (!ARMMCRegisterClasses[ARM::tGPRRegClassID].contains( Memory.BaseRegNum)) return false; // No offset of any kind. return Memory.OffsetRegNum == 0 && Memory.OffsetImm == nullptr && (alignOK || Memory.Alignment == Alignment); } bool isMemPCRelImm12() const { if (!isGPRMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0) return false; // Base register must be PC. if (Memory.BaseRegNum != ARM::PC) return false; // Immediate offset in range [-4095, 4095]. if (!Memory.OffsetImm) return true; int64_t Val = Memory.OffsetImm->getValue(); return (Val > -4096 && Val < 4096) || (Val == std::numeric_limits::min()); } bool isAlignedMemory() const { return isMemNoOffset(true); } bool isAlignedMemoryNone() const { return isMemNoOffset(false, 0); } bool isDupAlignedMemoryNone() const { return isMemNoOffset(false, 0); } bool isAlignedMemory16() const { if (isMemNoOffset(false, 2)) // alignment in bytes for 16-bits is 2. return true; return isMemNoOffset(false, 0); } bool isDupAlignedMemory16() const { if (isMemNoOffset(false, 2)) // alignment in bytes for 16-bits is 2. return true; return isMemNoOffset(false, 0); } bool isAlignedMemory32() const { if (isMemNoOffset(false, 4)) // alignment in bytes for 32-bits is 4. return true; return isMemNoOffset(false, 0); } bool isDupAlignedMemory32() const { if (isMemNoOffset(false, 4)) // alignment in bytes for 32-bits is 4. return true; return isMemNoOffset(false, 0); } bool isAlignedMemory64() const { if (isMemNoOffset(false, 8)) // alignment in bytes for 64-bits is 8. return true; return isMemNoOffset(false, 0); } bool isDupAlignedMemory64() const { if (isMemNoOffset(false, 8)) // alignment in bytes for 64-bits is 8. return true; return isMemNoOffset(false, 0); } bool isAlignedMemory64or128() const { if (isMemNoOffset(false, 8)) // alignment in bytes for 64-bits is 8. return true; if (isMemNoOffset(false, 16)) // alignment in bytes for 128-bits is 16. return true; return isMemNoOffset(false, 0); } bool isDupAlignedMemory64or128() const { if (isMemNoOffset(false, 8)) // alignment in bytes for 64-bits is 8. return true; if (isMemNoOffset(false, 16)) // alignment in bytes for 128-bits is 16. return true; return isMemNoOffset(false, 0); } bool isAlignedMemory64or128or256() const { if (isMemNoOffset(false, 8)) // alignment in bytes for 64-bits is 8. return true; if (isMemNoOffset(false, 16)) // alignment in bytes for 128-bits is 16. return true; if (isMemNoOffset(false, 32)) // alignment in bytes for 256-bits is 32. return true; return isMemNoOffset(false, 0); } bool isAddrMode2() const { if (!isGPRMem() || Memory.Alignment != 0) return false; // Check for register offset. if (Memory.OffsetRegNum) return true; // Immediate offset in range [-4095, 4095]. if (!Memory.OffsetImm) return true; int64_t Val = Memory.OffsetImm->getValue(); return Val > -4096 && Val < 4096; } bool isAM2OffsetImm() const { if (!isImm()) return false; // Immediate offset in range [-4095, 4095]. const MCConstantExpr *CE = dyn_cast(getImm()); if (!CE) return false; int64_t Val = CE->getValue(); return (Val == std::numeric_limits::min()) || (Val > -4096 && Val < 4096); } bool isAddrMode3() const { // If we have an immediate that's not a constant, treat it as a label // reference needing a fixup. If it is a constant, it's something else // and we reject it. if (isImm() && !isa(getImm())) return true; if (!isGPRMem() || Memory.Alignment != 0) return false; // No shifts are legal for AM3. if (Memory.ShiftType != ARM_AM::no_shift) return false; // Check for register offset. if (Memory.OffsetRegNum) return true; // Immediate offset in range [-255, 255]. if (!Memory.OffsetImm) return true; int64_t Val = Memory.OffsetImm->getValue(); // The #-0 offset is encoded as std::numeric_limits::min(), and we // have to check for this too. return (Val > -256 && Val < 256) || Val == std::numeric_limits::min(); } bool isAM3Offset() const { if (isPostIdxReg()) return true; if (!isImm()) return false; // Immediate offset in range [-255, 255]. const MCConstantExpr *CE = dyn_cast(getImm()); if (!CE) return false; int64_t Val = CE->getValue(); // Special case, #-0 is std::numeric_limits::min(). return (Val > -256 && Val < 256) || Val == std::numeric_limits::min(); } bool isAddrMode5() const { // If we have an immediate that's not a constant, treat it as a label // reference needing a fixup. If it is a constant, it's something else // and we reject it. if (isImm() && !isa(getImm())) return true; if (!isGPRMem() || Memory.Alignment != 0) return false; // Check for register offset. if (Memory.OffsetRegNum) return false; // Immediate offset in range [-1020, 1020] and a multiple of 4. if (!Memory.OffsetImm) return true; int64_t Val = Memory.OffsetImm->getValue(); return (Val >= -1020 && Val <= 1020 && ((Val & 3) == 0)) || Val == std::numeric_limits::min(); } bool isAddrMode5FP16() const { // If we have an immediate that's not a constant, treat it as a label // reference needing a fixup. If it is a constant, it's something else // and we reject it. if (isImm() && !isa(getImm())) return true; if (!isGPRMem() || Memory.Alignment != 0) return false; // Check for register offset. if (Memory.OffsetRegNum) return false; // Immediate offset in range [-510, 510] and a multiple of 2. if (!Memory.OffsetImm) return true; int64_t Val = Memory.OffsetImm->getValue(); return (Val >= -510 && Val <= 510 && ((Val & 1) == 0)) || Val == std::numeric_limits::min(); } bool isMemTBB() const { if (!isGPRMem() || !Memory.OffsetRegNum || Memory.isNegative || Memory.ShiftType != ARM_AM::no_shift || Memory.Alignment != 0) return false; return true; } bool isMemTBH() const { if (!isGPRMem() || !Memory.OffsetRegNum || Memory.isNegative || Memory.ShiftType != ARM_AM::lsl || Memory.ShiftImm != 1 || Memory.Alignment != 0 ) return false; return true; } bool isMemRegOffset() const { if (!isGPRMem() || !Memory.OffsetRegNum || Memory.Alignment != 0) return false; return true; } bool isT2MemRegOffset() const { if (!isGPRMem() || !Memory.OffsetRegNum || Memory.isNegative || Memory.Alignment != 0 || Memory.BaseRegNum == ARM::PC) return false; // Only lsl #{0, 1, 2, 3} allowed. if (Memory.ShiftType == ARM_AM::no_shift) return true; if (Memory.ShiftType != ARM_AM::lsl || Memory.ShiftImm > 3) return false; return true; } bool isMemThumbRR() const { // Thumb reg+reg addressing is simple. Just two registers, a base and // an offset. No shifts, negations or any other complicating factors. if (!isGPRMem() || !Memory.OffsetRegNum || Memory.isNegative || Memory.ShiftType != ARM_AM::no_shift || Memory.Alignment != 0) return false; return isARMLowRegister(Memory.BaseRegNum) && (!Memory.OffsetRegNum || isARMLowRegister(Memory.OffsetRegNum)); } bool isMemThumbRIs4() const { if (!isGPRMem() || Memory.OffsetRegNum != 0 || !isARMLowRegister(Memory.BaseRegNum) || Memory.Alignment != 0) return false; // Immediate offset, multiple of 4 in range [0, 124]. if (!Memory.OffsetImm) return true; int64_t Val = Memory.OffsetImm->getValue(); return Val >= 0 && Val <= 124 && (Val % 4) == 0; } bool isMemThumbRIs2() const { if (!isGPRMem() || Memory.OffsetRegNum != 0 || !isARMLowRegister(Memory.BaseRegNum) || Memory.Alignment != 0) return false; // Immediate offset, multiple of 4 in range [0, 62]. if (!Memory.OffsetImm) return true; int64_t Val = Memory.OffsetImm->getValue(); return Val >= 0 && Val <= 62 && (Val % 2) == 0; } bool isMemThumbRIs1() const { if (!isGPRMem() || Memory.OffsetRegNum != 0 || !isARMLowRegister(Memory.BaseRegNum) || Memory.Alignment != 0) return false; // Immediate offset in range [0, 31]. if (!Memory.OffsetImm) return true; int64_t Val = Memory.OffsetImm->getValue(); return Val >= 0 && Val <= 31; } bool isMemThumbSPI() const { if (!isGPRMem() || Memory.OffsetRegNum != 0 || Memory.BaseRegNum != ARM::SP || Memory.Alignment != 0) return false; // Immediate offset, multiple of 4 in range [0, 1020]. if (!Memory.OffsetImm) return true; int64_t Val = Memory.OffsetImm->getValue(); return Val >= 0 && Val <= 1020 && (Val % 4) == 0; } bool isMemImm8s4Offset() const { // If we have an immediate that's not a constant, treat it as a label // reference needing a fixup. If it is a constant, it's something else // and we reject it. if (isImm() && !isa(getImm())) return true; if (!isGPRMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0) return false; // Immediate offset a multiple of 4 in range [-1020, 1020]. if (!Memory.OffsetImm) return true; int64_t Val = Memory.OffsetImm->getValue(); // Special case, #-0 is std::numeric_limits::min(). return (Val >= -1020 && Val <= 1020 && (Val & 3) == 0) || Val == std::numeric_limits::min(); } bool isMemImm7s4Offset() const { // If we have an immediate that's not a constant, treat it as a label // reference needing a fixup. If it is a constant, it's something else // and we reject it. if (isImm() && !isa(getImm())) return true; if (!isGPRMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0 || !ARMMCRegisterClasses[ARM::GPRnopcRegClassID].contains( Memory.BaseRegNum)) return false; // Immediate offset a multiple of 4 in range [-508, 508]. if (!Memory.OffsetImm) return true; int64_t Val = Memory.OffsetImm->getValue(); // Special case, #-0 is INT32_MIN. return (Val >= -508 && Val <= 508 && (Val & 3) == 0) || Val == INT32_MIN; } bool isMemImm0_1020s4Offset() const { if (!isGPRMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0) return false; // Immediate offset a multiple of 4 in range [0, 1020]. if (!Memory.OffsetImm) return true; int64_t Val = Memory.OffsetImm->getValue(); return Val >= 0 && Val <= 1020 && (Val & 3) == 0; } bool isMemImm8Offset() const { if (!isGPRMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0) return false; // Base reg of PC isn't allowed for these encodings. if (Memory.BaseRegNum == ARM::PC) return false; // Immediate offset in range [-255, 255]. if (!Memory.OffsetImm) return true; int64_t Val = Memory.OffsetImm->getValue(); return (Val == std::numeric_limits::min()) || (Val > -256 && Val < 256); } template bool isMemImm7ShiftedOffset() const { if (!isGPRMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0 || !ARMMCRegisterClasses[RegClassID].contains(Memory.BaseRegNum)) return false; // Expect an immediate offset equal to an element of the range // [-127, 127], shifted left by Bits. if (!Memory.OffsetImm) return true; int64_t Val = Memory.OffsetImm->getValue(); // INT32_MIN is a special-case value (indicating the encoding with // zero offset and the subtract bit set) if (Val == INT32_MIN) return true; unsigned Divisor = 1U << Bits; // Check that the low bits are zero if (Val % Divisor != 0) return false; // Check that the remaining offset is within range. Val /= Divisor; return (Val >= -127 && Val <= 127); } template bool isMemRegRQOffset() const { if (!isMVEMem() || Memory.OffsetImm != 0 || Memory.Alignment != 0) return false; if (!ARMMCRegisterClasses[ARM::GPRnopcRegClassID].contains( Memory.BaseRegNum)) return false; if (!ARMMCRegisterClasses[ARM::MQPRRegClassID].contains( Memory.OffsetRegNum)) return false; if (shift == 0 && Memory.ShiftType != ARM_AM::no_shift) return false; if (shift > 0 && (Memory.ShiftType != ARM_AM::uxtw || Memory.ShiftImm != shift)) return false; return true; } template bool isMemRegQOffset() const { if (!isMVEMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0) return false; if (!ARMMCRegisterClasses[ARM::MQPRRegClassID].contains( Memory.BaseRegNum)) return false; if(!Memory.OffsetImm) return true; static_assert(shift < 56, "Such that we dont shift by a value higher than 62"); int64_t Val = Memory.OffsetImm->getValue(); // The value must be a multiple of (1 << shift) if ((Val & ((1U << shift) - 1)) != 0) return false; // And be in the right range, depending on the amount that it is shifted // by. Shift 0, is equal to 7 unsigned bits, the sign bit is set // separately. int64_t Range = (1U << (7+shift)) - 1; return (Val == INT32_MIN) || (Val > -Range && Val < Range); } bool isMemPosImm8Offset() const { if (!isGPRMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0) return false; // Immediate offset in range [0, 255]. if (!Memory.OffsetImm) return true; int64_t Val = Memory.OffsetImm->getValue(); return Val >= 0 && Val < 256; } bool isMemNegImm8Offset() const { if (!isGPRMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0) return false; // Base reg of PC isn't allowed for these encodings. if (Memory.BaseRegNum == ARM::PC) return false; // Immediate offset in range [-255, -1]. if (!Memory.OffsetImm) return false; int64_t Val = Memory.OffsetImm->getValue(); return (Val == std::numeric_limits::min()) || (Val > -256 && Val < 0); } bool isMemUImm12Offset() const { if (!isGPRMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0) return false; // Immediate offset in range [0, 4095]. if (!Memory.OffsetImm) return true; int64_t Val = Memory.OffsetImm->getValue(); return (Val >= 0 && Val < 4096); } bool isMemImm12Offset() const { // If we have an immediate that's not a constant, treat it as a label // reference needing a fixup. If it is a constant, it's something else // and we reject it. if (isImm() && !isa(getImm())) return true; if (!isGPRMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0) return false; // Immediate offset in range [-4095, 4095]. if (!Memory.OffsetImm) return true; int64_t Val = Memory.OffsetImm->getValue(); return (Val > -4096 && Val < 4096) || (Val == std::numeric_limits::min()); } bool isConstPoolAsmImm() const { // Delay processing of Constant Pool Immediate, this will turn into // a constant. Match no other operand return (isConstantPoolImm()); } bool isPostIdxImm8() const { if (!isImm()) return false; const MCConstantExpr *CE = dyn_cast(getImm()); if (!CE) return false; int64_t Val = CE->getValue(); return (Val > -256 && Val < 256) || (Val == std::numeric_limits::min()); } bool isPostIdxImm8s4() const { if (!isImm()) return false; const MCConstantExpr *CE = dyn_cast(getImm()); if (!CE) return false; int64_t Val = CE->getValue(); return ((Val & 3) == 0 && Val >= -1020 && Val <= 1020) || (Val == std::numeric_limits::min()); } bool isMSRMask() const { return Kind == k_MSRMask; } bool isBankedReg() const { return Kind == k_BankedReg; } bool isProcIFlags() const { return Kind == k_ProcIFlags; } // NEON operands. bool isSingleSpacedVectorList() const { return Kind == k_VectorList && !VectorList.isDoubleSpaced; } bool isDoubleSpacedVectorList() const { return Kind == k_VectorList && VectorList.isDoubleSpaced; } bool isVecListOneD() const { if (!isSingleSpacedVectorList()) return false; return VectorList.Count == 1; } bool isVecListTwoMQ() const { return isSingleSpacedVectorList() && VectorList.Count == 2 && ARMMCRegisterClasses[ARM::MQPRRegClassID].contains( VectorList.RegNum); } bool isVecListDPair() const { if (!isSingleSpacedVectorList()) return false; return (ARMMCRegisterClasses[ARM::DPairRegClassID] .contains(VectorList.RegNum)); } bool isVecListThreeD() const { if (!isSingleSpacedVectorList()) return false; return VectorList.Count == 3; } bool isVecListFourD() const { if (!isSingleSpacedVectorList()) return false; return VectorList.Count == 4; } bool isVecListDPairSpaced() const { if (Kind != k_VectorList) return false; if (isSingleSpacedVectorList()) return false; return (ARMMCRegisterClasses[ARM::DPairSpcRegClassID] .contains(VectorList.RegNum)); } bool isVecListThreeQ() const { if (!isDoubleSpacedVectorList()) return false; return VectorList.Count == 3; } bool isVecListFourQ() const { if (!isDoubleSpacedVectorList()) return false; return VectorList.Count == 4; } bool isVecListFourMQ() const { return isSingleSpacedVectorList() && VectorList.Count == 4 && ARMMCRegisterClasses[ARM::MQPRRegClassID].contains( VectorList.RegNum); } bool isSingleSpacedVectorAllLanes() const { return Kind == k_VectorListAllLanes && !VectorList.isDoubleSpaced; } bool isDoubleSpacedVectorAllLanes() const { return Kind == k_VectorListAllLanes && VectorList.isDoubleSpaced; } bool isVecListOneDAllLanes() const { if (!isSingleSpacedVectorAllLanes()) return false; return VectorList.Count == 1; } bool isVecListDPairAllLanes() const { if (!isSingleSpacedVectorAllLanes()) return false; return (ARMMCRegisterClasses[ARM::DPairRegClassID] .contains(VectorList.RegNum)); } bool isVecListDPairSpacedAllLanes() const { if (!isDoubleSpacedVectorAllLanes()) return false; return VectorList.Count == 2; } bool isVecListThreeDAllLanes() const { if (!isSingleSpacedVectorAllLanes()) return false; return VectorList.Count == 3; } bool isVecListThreeQAllLanes() const { if (!isDoubleSpacedVectorAllLanes()) return false; return VectorList.Count == 3; } bool isVecListFourDAllLanes() const { if (!isSingleSpacedVectorAllLanes()) return false; return VectorList.Count == 4; } bool isVecListFourQAllLanes() const { if (!isDoubleSpacedVectorAllLanes()) return false; return VectorList.Count == 4; } bool isSingleSpacedVectorIndexed() const { return Kind == k_VectorListIndexed && !VectorList.isDoubleSpaced; } bool isDoubleSpacedVectorIndexed() const { return Kind == k_VectorListIndexed && VectorList.isDoubleSpaced; } bool isVecListOneDByteIndexed() const { if (!isSingleSpacedVectorIndexed()) return false; return VectorList.Count == 1 && VectorList.LaneIndex <= 7; } bool isVecListOneDHWordIndexed() const { if (!isSingleSpacedVectorIndexed()) return false; return VectorList.Count == 1 && VectorList.LaneIndex <= 3; } bool isVecListOneDWordIndexed() const { if (!isSingleSpacedVectorIndexed()) return false; return VectorList.Count == 1 && VectorList.LaneIndex <= 1; } bool isVecListTwoDByteIndexed() const { if (!isSingleSpacedVectorIndexed()) return false; return VectorList.Count == 2 && VectorList.LaneIndex <= 7; } bool isVecListTwoDHWordIndexed() const { if (!isSingleSpacedVectorIndexed()) return false; return VectorList.Count == 2 && VectorList.LaneIndex <= 3; } bool isVecListTwoQWordIndexed() const { if (!isDoubleSpacedVectorIndexed()) return false; return VectorList.Count == 2 && VectorList.LaneIndex <= 1; } bool isVecListTwoQHWordIndexed() const { if (!isDoubleSpacedVectorIndexed()) return false; return VectorList.Count == 2 && VectorList.LaneIndex <= 3; } bool isVecListTwoDWordIndexed() const { if (!isSingleSpacedVectorIndexed()) return false; return VectorList.Count == 2 && VectorList.LaneIndex <= 1; } bool isVecListThreeDByteIndexed() const { if (!isSingleSpacedVectorIndexed()) return false; return VectorList.Count == 3 && VectorList.LaneIndex <= 7; } bool isVecListThreeDHWordIndexed() const { if (!isSingleSpacedVectorIndexed()) return false; return VectorList.Count == 3 && VectorList.LaneIndex <= 3; } bool isVecListThreeQWordIndexed() const { if (!isDoubleSpacedVectorIndexed()) return false; return VectorList.Count == 3 && VectorList.LaneIndex <= 1; } bool isVecListThreeQHWordIndexed() const { if (!isDoubleSpacedVectorIndexed()) return false; return VectorList.Count == 3 && VectorList.LaneIndex <= 3; } bool isVecListThreeDWordIndexed() const { if (!isSingleSpacedVectorIndexed()) return false; return VectorList.Count == 3 && VectorList.LaneIndex <= 1; } bool isVecListFourDByteIndexed() const { if (!isSingleSpacedVectorIndexed()) return false; return VectorList.Count == 4 && VectorList.LaneIndex <= 7; } bool isVecListFourDHWordIndexed() const { if (!isSingleSpacedVectorIndexed()) return false; return VectorList.Count == 4 && VectorList.LaneIndex <= 3; } bool isVecListFourQWordIndexed() const { if (!isDoubleSpacedVectorIndexed()) return false; return VectorList.Count == 4 && VectorList.LaneIndex <= 1; } bool isVecListFourQHWordIndexed() const { if (!isDoubleSpacedVectorIndexed()) return false; return VectorList.Count == 4 && VectorList.LaneIndex <= 3; } bool isVecListFourDWordIndexed() const { if (!isSingleSpacedVectorIndexed()) return false; return VectorList.Count == 4 && VectorList.LaneIndex <= 1; } bool isVectorIndex() const { return Kind == k_VectorIndex; } template bool isVectorIndexInRange() const { if (Kind != k_VectorIndex) return false; return VectorIndex.Val < NumLanes; } bool isVectorIndex8() const { return isVectorIndexInRange<8>(); } bool isVectorIndex16() const { return isVectorIndexInRange<4>(); } bool isVectorIndex32() const { return isVectorIndexInRange<2>(); } bool isVectorIndex64() const { return isVectorIndexInRange<1>(); } template bool isMVEPairVectorIndex() const { if (Kind != k_VectorIndex) return false; return VectorIndex.Val == PermittedValue || VectorIndex.Val == OtherPermittedValue; } bool isNEONi8splat() const { if (!isImm()) return false; const MCConstantExpr *CE = dyn_cast(getImm()); // Must be a constant. if (!CE) return false; int64_t Value = CE->getValue(); // i8 value splatted across 8 bytes. The immediate is just the 8 byte // value. return Value >= 0 && Value < 256; } bool isNEONi16splat() const { if (isNEONByteReplicate(2)) return false; // Leave that for bytes replication and forbid by default. if (!isImm()) return false; const MCConstantExpr *CE = dyn_cast(getImm()); // Must be a constant. if (!CE) return false; unsigned Value = CE->getValue(); return ARM_AM::isNEONi16splat(Value); } bool isNEONi16splatNot() const { if (!isImm()) return false; const MCConstantExpr *CE = dyn_cast(getImm()); // Must be a constant. if (!CE) return false; unsigned Value = CE->getValue(); return ARM_AM::isNEONi16splat(~Value & 0xffff); } bool isNEONi32splat() const { if (isNEONByteReplicate(4)) return false; // Leave that for bytes replication and forbid by default. if (!isImm()) return false; const MCConstantExpr *CE = dyn_cast(getImm()); // Must be a constant. if (!CE) return false; unsigned Value = CE->getValue(); return ARM_AM::isNEONi32splat(Value); } bool isNEONi32splatNot() const { if (!isImm()) return false; const MCConstantExpr *CE = dyn_cast(getImm()); // Must be a constant. if (!CE) return false; unsigned Value = CE->getValue(); return ARM_AM::isNEONi32splat(~Value); } static bool isValidNEONi32vmovImm(int64_t Value) { // i32 value with set bits only in one byte X000, 0X00, 00X0, or 000X, // for VMOV/VMVN only, 00Xf or 0Xff are also accepted. return ((Value & 0xffffffffffffff00) == 0) || ((Value & 0xffffffffffff00ff) == 0) || ((Value & 0xffffffffff00ffff) == 0) || ((Value & 0xffffffff00ffffff) == 0) || ((Value & 0xffffffffffff00ff) == 0xff) || ((Value & 0xffffffffff00ffff) == 0xffff); } bool isNEONReplicate(unsigned Width, unsigned NumElems, bool Inv) const { assert((Width == 8 || Width == 16 || Width == 32) && "Invalid element width"); assert(NumElems * Width <= 64 && "Invalid result width"); if (!isImm()) return false; const MCConstantExpr *CE = dyn_cast(getImm()); // Must be a constant. if (!CE) return false; int64_t Value = CE->getValue(); if (!Value) return false; // Don't bother with zero. if (Inv) Value = ~Value; uint64_t Mask = (1ull << Width) - 1; uint64_t Elem = Value & Mask; if (Width == 16 && (Elem & 0x00ff) != 0 && (Elem & 0xff00) != 0) return false; if (Width == 32 && !isValidNEONi32vmovImm(Elem)) return false; for (unsigned i = 1; i < NumElems; ++i) { Value >>= Width; if ((Value & Mask) != Elem) return false; } return true; } bool isNEONByteReplicate(unsigned NumBytes) const { return isNEONReplicate(8, NumBytes, false); } static void checkNeonReplicateArgs(unsigned FromW, unsigned ToW) { assert((FromW == 8 || FromW == 16 || FromW == 32) && "Invalid source width"); assert((ToW == 16 || ToW == 32 || ToW == 64) && "Invalid destination width"); assert(FromW < ToW && "ToW is not less than FromW"); } template bool isNEONmovReplicate() const { checkNeonReplicateArgs(FromW, ToW); if (ToW == 64 && isNEONi64splat()) return false; return isNEONReplicate(FromW, ToW / FromW, false); } template bool isNEONinvReplicate() const { checkNeonReplicateArgs(FromW, ToW); return isNEONReplicate(FromW, ToW / FromW, true); } bool isNEONi32vmov() const { if (isNEONByteReplicate(4)) return false; // Let it to be classified as byte-replicate case. if (!isImm()) return false; const MCConstantExpr *CE = dyn_cast(getImm()); // Must be a constant. if (!CE) return false; return isValidNEONi32vmovImm(CE->getValue()); } bool isNEONi32vmovNeg() const { if (!isImm()) return false; const MCConstantExpr *CE = dyn_cast(getImm()); // Must be a constant. if (!CE) return false; return isValidNEONi32vmovImm(~CE->getValue()); } bool isNEONi64splat() const { if (!isImm()) return false; const MCConstantExpr *CE = dyn_cast(getImm()); // Must be a constant. if (!CE) return false; uint64_t Value = CE->getValue(); // i64 value with each byte being either 0 or 0xff. for (unsigned i = 0; i < 8; ++i, Value >>= 8) if ((Value & 0xff) != 0 && (Value & 0xff) != 0xff) return false; return true; } template bool isComplexRotation() const { if (!isImm()) return false; const MCConstantExpr *CE = dyn_cast(getImm()); if (!CE) return false; uint64_t Value = CE->getValue(); return (Value % Angle == Remainder && Value <= 270); } bool isMVELongShift() const { if (!isImm()) return false; const MCConstantExpr *CE = dyn_cast(getImm()); // Must be a constant. if (!CE) return false; uint64_t Value = CE->getValue(); return Value >= 1 && Value <= 32; } bool isITCondCodeNoAL() const { if (!isITCondCode()) return false; ARMCC::CondCodes CC = getCondCode(); return CC != ARMCC::AL; } bool isITCondCodeRestrictedI() const { if (!isITCondCode()) return false; ARMCC::CondCodes CC = getCondCode(); return CC == ARMCC::EQ || CC == ARMCC::NE; } bool isITCondCodeRestrictedS() const { if (!isITCondCode()) return false; ARMCC::CondCodes CC = getCondCode(); return CC == ARMCC::LT || CC == ARMCC::GT || CC == ARMCC::LE || CC == ARMCC::GE; } bool isITCondCodeRestrictedU() const { if (!isITCondCode()) return false; ARMCC::CondCodes CC = getCondCode(); return CC == ARMCC::HS || CC == ARMCC::HI; } bool isITCondCodeRestrictedFP() const { if (!isITCondCode()) return false; ARMCC::CondCodes CC = getCondCode(); return CC == ARMCC::EQ || CC == ARMCC::NE || CC == ARMCC::LT || CC == ARMCC::GT || CC == ARMCC::LE || CC == ARMCC::GE; } void addExpr(MCInst &Inst, const MCExpr *Expr) const { // Add as immediates when possible. Null MCExpr = 0. if (!Expr) Inst.addOperand(MCOperand::createImm(0)); else if (const MCConstantExpr *CE = dyn_cast(Expr)) Inst.addOperand(MCOperand::createImm(CE->getValue())); else Inst.addOperand(MCOperand::createExpr(Expr)); } void addARMBranchTargetOperands(MCInst &Inst, unsigned N) const { assert(N == 1 && "Invalid number of operands!"); addExpr(Inst, getImm()); } void addThumbBranchTargetOperands(MCInst &Inst, unsigned N) const { assert(N == 1 && "Invalid number of operands!"); addExpr(Inst, getImm()); } void addCondCodeOperands(MCInst &Inst, unsigned N) const { assert(N == 2 && "Invalid number of operands!"); Inst.addOperand(MCOperand::createImm(unsigned(getCondCode()))); unsigned RegNum = getCondCode() == ARMCC::AL ? 0: ARM::CPSR; Inst.addOperand(MCOperand::createReg(RegNum)); } void addVPTPredNOperands(MCInst &Inst, unsigned N) const { assert(N == 2 && "Invalid number of operands!"); Inst.addOperand(MCOperand::createImm(unsigned(getVPTPred()))); unsigned RegNum = getVPTPred() == ARMVCC::None ? 0: ARM::P0; Inst.addOperand(MCOperand::createReg(RegNum)); } void addVPTPredROperands(MCInst &Inst, unsigned N) const { assert(N == 3 && "Invalid number of operands!"); addVPTPredNOperands(Inst, N-1); unsigned RegNum; if (getVPTPred() == ARMVCC::None) { RegNum = 0; } else { unsigned NextOpIndex = Inst.getNumOperands(); const MCInstrDesc &MCID = ARMInsts[Inst.getOpcode()]; int TiedOp = MCID.getOperandConstraint(NextOpIndex, MCOI::TIED_TO); assert(TiedOp >= 0 && "Inactive register in vpred_r is not tied to an output!"); RegNum = Inst.getOperand(TiedOp).getReg(); } Inst.addOperand(MCOperand::createReg(RegNum)); } void addCoprocNumOperands(MCInst &Inst, unsigned N) const { assert(N == 1 && "Invalid number of operands!"); Inst.addOperand(MCOperand::createImm(getCoproc())); } void addCoprocRegOperands(MCInst &Inst, unsigned N) const { assert(N == 1 && "Invalid number of operands!"); Inst.addOperand(MCOperand::createImm(getCoproc())); } void addCoprocOptionOperands(MCInst &Inst, unsigned N) const { assert(N == 1 && "Invalid number of operands!"); Inst.addOperand(MCOperand::createImm(CoprocOption.Val)); } void addITMaskOperands(MCInst &Inst, unsigned N) const { assert(N == 1 && "Invalid number of operands!"); Inst.addOperand(MCOperand::createImm(ITMask.Mask)); } void addITCondCodeOperands(MCInst &Inst, unsigned N) const { assert(N == 1 && "Invalid number of operands!"); Inst.addOperand(MCOperand::createImm(unsigned(getCondCode()))); } void addITCondCodeInvOperands(MCInst &Inst, unsigned N) const { assert(N == 1 && "Invalid number of operands!"); Inst.addOperand(MCOperand::createImm(unsigned(ARMCC::getOppositeCondition(getCondCode())))); } void addCCOutOperands(MCInst &Inst, unsigned N) const { assert(N == 1 && "Invalid number of operands!"); Inst.addOperand(MCOperand::createReg(getReg())); } void addRegOperands(MCInst &Inst, unsigned N) const { assert(N == 1 && "Invalid number of operands!"); Inst.addOperand(MCOperand::createReg(getReg())); } void addRegShiftedRegOperands(MCInst &Inst, unsigned N) const { assert(N == 3 && "Invalid number of operands!"); assert(isRegShiftedReg() && "addRegShiftedRegOperands() on non-RegShiftedReg!"); Inst.addOperand(MCOperand::createReg(RegShiftedReg.SrcReg)); Inst.addOperand(MCOperand::createReg(RegShiftedReg.ShiftReg)); Inst.addOperand(MCOperand::createImm( ARM_AM::getSORegOpc(RegShiftedReg.ShiftTy, RegShiftedReg.ShiftImm))); } void addRegShiftedImmOperands(MCInst &Inst, unsigned N) const { assert(N == 2 && "Invalid number of operands!"); assert(isRegShiftedImm() && "addRegShiftedImmOperands() on non-RegShiftedImm!"); Inst.addOperand(MCOperand::createReg(RegShiftedImm.SrcReg)); // Shift of #32 is encoded as 0 where permitted unsigned Imm = (RegShiftedImm.ShiftImm == 32 ? 0 : RegShiftedImm.ShiftImm); Inst.addOperand(MCOperand::createImm( ARM_AM::getSORegOpc(RegShiftedImm.ShiftTy, Imm))); } void addShifterImmOperands(MCInst &Inst, unsigned N) const { assert(N == 1 && "Invalid number of operands!"); Inst.addOperand(MCOperand::createImm((ShifterImm.isASR << 5) | ShifterImm.Imm)); } void addRegListOperands(MCInst &Inst, unsigned N) const { assert(N == 1 && "Invalid number of operands!"); const SmallVectorImpl &RegList = getRegList(); for (SmallVectorImpl::const_iterator I = RegList.begin(), E = RegList.end(); I != E; ++I) Inst.addOperand(MCOperand::createReg(*I)); } void addRegListWithAPSROperands(MCInst &Inst, unsigned N) const { assert(N == 1 && "Invalid number of operands!"); const SmallVectorImpl &RegList = getRegList(); for (SmallVectorImpl::const_iterator I = RegList.begin(), E = RegList.end(); I != E; ++I) Inst.addOperand(MCOperand::createReg(*I)); } void addDPRRegListOperands(MCInst &Inst, unsigned N) const { addRegListOperands(Inst, N); } void addSPRRegListOperands(MCInst &Inst, unsigned N) const { addRegListOperands(Inst, N); } void addFPSRegListWithVPROperands(MCInst &Inst, unsigned N) const { addRegListOperands(Inst, N); } void addFPDRegListWithVPROperands(MCInst &Inst, unsigned N) const { addRegListOperands(Inst, N); } void addRotImmOperands(MCInst &Inst, unsigned N) const { assert(N == 1 && "Invalid number of operands!"); // Encoded as val>>3. The printer handles display as 8, 16, 24. Inst.addOperand(MCOperand::createImm(RotImm.Imm >> 3)); } void addModImmOperands(MCInst &Inst, unsigned N) const { assert(N == 1 && "Invalid number of operands!"); // Support for fixups (MCFixup) if (isImm()) return addImmOperands(Inst, N); Inst.addOperand(MCOperand::createImm(ModImm.Bits | (ModImm.Rot << 7))); } void addModImmNotOperands(MCInst &Inst, unsigned N) const { assert(N == 1 && "Invalid number of operands!"); const MCConstantExpr *CE = dyn_cast(getImm()); uint32_t Enc = ARM_AM::getSOImmVal(~CE->getValue()); Inst.addOperand(MCOperand::createImm(Enc)); } void addModImmNegOperands(MCInst &Inst, unsigned N) const { assert(N == 1 && "Invalid number of operands!"); const MCConstantExpr *CE = dyn_cast(getImm()); uint32_t Enc = ARM_AM::getSOImmVal(-CE->getValue()); Inst.addOperand(MCOperand::createImm(Enc)); } void addThumbModImmNeg8_255Operands(MCInst &Inst, unsigned N) const { assert(N == 1 && "Invalid number of operands!"); const MCConstantExpr *CE = dyn_cast(getImm()); uint32_t Val = -CE->getValue(); Inst.addOperand(MCOperand::createImm(Val)); } void addThumbModImmNeg1_7Operands(MCInst &Inst, unsigned N) const { assert(N == 1 && "Invalid number of operands!"); const MCConstantExpr *CE = dyn_cast(getImm()); uint32_t Val = -CE->getValue(); Inst.addOperand(MCOperand::createImm(Val)); } void addBitfieldOperands(MCInst &Inst, unsigned N) const { assert(N == 1 && "Invalid number of operands!"); // Munge the lsb/width into a bitfield mask. unsigned lsb = Bitfield.LSB; unsigned width = Bitfield.Width; // Make a 32-bit mask w/ the referenced bits clear and all other bits set. uint32_t Mask = ~(((uint32_t)0xffffffff >> lsb) << (32 - width) >> (32 - (lsb + width))); Inst.addOperand(MCOperand::createImm(Mask)); } void addImmOperands(MCInst &Inst, unsigned N) const { assert(N == 1 && "Invalid number of operands!"); addExpr(Inst, getImm()); } void addFBits16Operands(MCInst &Inst, unsigned N) const { assert(N == 1 && "Invalid number of operands!"); const MCConstantExpr *CE = dyn_cast(getImm()); Inst.addOperand(MCOperand::createImm(16 - CE->getValue())); } void addFBits32Operands(MCInst &Inst, unsigned N) const { assert(N == 1 && "Invalid number of operands!"); const MCConstantExpr *CE = dyn_cast(getImm()); Inst.addOperand(MCOperand::createImm(32 - CE->getValue())); } void addFPImmOperands(MCInst &Inst, unsigned N) const { assert(N == 1 && "Invalid number of operands!"); const MCConstantExpr *CE = dyn_cast(getImm()); int Val = ARM_AM::getFP32Imm(APInt(32, CE->getValue())); Inst.addOperand(MCOperand::createImm(Val)); } void addImm8s4Operands(MCInst &Inst, unsigned N) const { assert(N == 1 && "Invalid number of operands!"); // FIXME: We really want to scale the value here, but the LDRD/STRD // instruction don't encode operands that way yet. const MCConstantExpr *CE = dyn_cast(getImm()); Inst.addOperand(MCOperand::createImm(CE->getValue())); } void addImm7s4Operands(MCInst &Inst, unsigned N) const { assert(N == 1 && "Invalid number of operands!"); // FIXME: We really want to scale the value here, but the VSTR/VLDR_VSYSR // instruction don't encode operands that way yet. const MCConstantExpr *CE = dyn_cast(getImm()); Inst.addOperand(MCOperand::createImm(CE->getValue())); } void addImm7Shift0Operands(MCInst &Inst, unsigned N) const { assert(N == 1 && "Invalid number of operands!"); const MCConstantExpr *CE = dyn_cast(getImm()); assert(CE != nullptr && "Invalid operand type!"); Inst.addOperand(MCOperand::createImm(CE->getValue())); } void addImm7Shift1Operands(MCInst &Inst, unsigned N) const { assert(N == 1 && "Invalid number of operands!"); const MCConstantExpr *CE = dyn_cast(getImm()); assert(CE != nullptr && "Invalid operand type!"); Inst.addOperand(MCOperand::createImm(CE->getValue())); } void addImm7Shift2Operands(MCInst &Inst, unsigned N) const { assert(N == 1 && "Invalid number of operands!"); const MCConstantExpr *CE = dyn_cast(getImm()); assert(CE != nullptr && "Invalid operand type!"); Inst.addOperand(MCOperand::createImm(CE->getValue())); } void addImm7Operands(MCInst &Inst, unsigned N) const { assert(N == 1 && "Invalid number of operands!"); const MCConstantExpr *CE = dyn_cast(getImm()); assert(CE != nullptr && "Invalid operand type!"); Inst.addOperand(MCOperand::createImm(CE->getValue())); } void addImm0_1020s4Operands(MCInst &Inst, unsigned N) const { assert(N == 1 && "Invalid number of operands!"); // The immediate is scaled by four in the encoding and is stored // in the MCInst as such. Lop off the low two bits here. const MCConstantExpr *CE = dyn_cast(getImm()); Inst.addOperand(MCOperand::createImm(CE->getValue() / 4)); } void addImm0_508s4NegOperands(MCInst &Inst, unsigned N) const { assert(N == 1 && "Invalid number of operands!"); // The immediate is scaled by four in the encoding and is stored // in the MCInst as such. Lop off the low two bits here. const MCConstantExpr *CE = dyn_cast(getImm()); Inst.addOperand(MCOperand::createImm(-(CE->getValue() / 4))); } void addImm0_508s4Operands(MCInst &Inst, unsigned N) const { assert(N == 1 && "Invalid number of operands!"); // The immediate is scaled by four in the encoding and is stored // in the MCInst as such. Lop off the low two bits here. const MCConstantExpr *CE = dyn_cast(getImm()); Inst.addOperand(MCOperand::createImm(CE->getValue() / 4)); } void addImm1_16Operands(MCInst &Inst, unsigned N) const { assert(N == 1 && "Invalid number of operands!"); // The constant encodes as the immediate-1, and we store in the instruction // the bits as encoded, so subtract off one here. const MCConstantExpr *CE = dyn_cast(getImm()); Inst.addOperand(MCOperand::createImm(CE->getValue() - 1)); } void addImm1_32Operands(MCInst &Inst, unsigned N) const { assert(N == 1 && "Invalid number of operands!"); // The constant encodes as the immediate-1, and we store in the instruction // the bits as encoded, so subtract off one here. const MCConstantExpr *CE = dyn_cast(getImm()); Inst.addOperand(MCOperand::createImm(CE->getValue() - 1)); } void addImmThumbSROperands(MCInst &Inst, unsigned N) const { assert(N == 1 && "Invalid number of operands!"); // The constant encodes as the immediate, except for 32, which encodes as // zero. const MCConstantExpr *CE = dyn_cast(getImm()); unsigned Imm = CE->getValue(); Inst.addOperand(MCOperand::createImm((Imm == 32 ? 0 : Imm))); } void addPKHASRImmOperands(MCInst &Inst, unsigned N) const { assert(N == 1 && "Invalid number of operands!"); // An ASR value of 32 encodes as 0, so that's how we want to add it to // the instruction as well. const MCConstantExpr *CE = dyn_cast(getImm()); int Val = CE->getValue(); Inst.addOperand(MCOperand::createImm(Val == 32 ? 0 : Val)); } void addT2SOImmNotOperands(MCInst &Inst, unsigned N) const { assert(N == 1 && "Invalid number of operands!"); // The operand is actually a t2_so_imm, but we have its bitwise // negation in the assembly source, so twiddle it here. const MCConstantExpr *CE = dyn_cast(getImm()); Inst.addOperand(MCOperand::createImm(~(uint32_t)CE->getValue())); } void addT2SOImmNegOperands(MCInst &Inst, unsigned N) const { assert(N == 1 && "Invalid number of operands!"); // The operand is actually a t2_so_imm, but we have its // negation in the assembly source, so twiddle it here. const MCConstantExpr *CE = dyn_cast(getImm()); Inst.addOperand(MCOperand::createImm(-(uint32_t)CE->getValue())); } void addImm0_4095NegOperands(MCInst &Inst, unsigned N) const { assert(N == 1 && "Invalid number of operands!"); // The operand is actually an imm0_4095, but we have its // negation in the assembly source, so twiddle it here. const MCConstantExpr *CE = dyn_cast(getImm()); Inst.addOperand(MCOperand::createImm(-(uint32_t)CE->getValue())); } void addUnsignedOffset_b8s2Operands(MCInst &Inst, unsigned N) const { if(const MCConstantExpr *CE = dyn_cast(getImm())) { Inst.addOperand(MCOperand::createImm(CE->getValue() >> 2)); return; } const MCSymbolRefExpr *SR = dyn_cast(Imm.Val); assert(SR && "Unknown value type!"); Inst.addOperand(MCOperand::createExpr(SR)); } void addThumbMemPCOperands(MCInst &Inst, unsigned N) const { assert(N == 1 && "Invalid number of operands!"); if (isImm()) { const MCConstantExpr *CE = dyn_cast(getImm()); if (CE) { Inst.addOperand(MCOperand::createImm(CE->getValue())); return; } const MCSymbolRefExpr *SR = dyn_cast(Imm.Val); assert(SR && "Unknown value type!"); Inst.addOperand(MCOperand::createExpr(SR)); return; } assert(isGPRMem() && "Unknown value type!"); assert(isa(Memory.OffsetImm) && "Unknown value type!"); Inst.addOperand(MCOperand::createImm(Memory.OffsetImm->getValue())); } void addMemBarrierOptOperands(MCInst &Inst, unsigned N) const { assert(N == 1 && "Invalid number of operands!"); Inst.addOperand(MCOperand::createImm(unsigned(getMemBarrierOpt()))); } void addInstSyncBarrierOptOperands(MCInst &Inst, unsigned N) const { assert(N == 1 && "Invalid number of operands!"); Inst.addOperand(MCOperand::createImm(unsigned(getInstSyncBarrierOpt()))); } void addTraceSyncBarrierOptOperands(MCInst &Inst, unsigned N) const { assert(N == 1 && "Invalid number of operands!"); Inst.addOperand(MCOperand::createImm(unsigned(getTraceSyncBarrierOpt()))); } void addMemNoOffsetOperands(MCInst &Inst, unsigned N) const { assert(N == 1 && "Invalid number of operands!"); Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum)); } void addMemNoOffsetT2Operands(MCInst &Inst, unsigned N) const { assert(N == 1 && "Invalid number of operands!"); Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum)); } void addMemNoOffsetT2NoSpOperands(MCInst &Inst, unsigned N) const { assert(N == 1 && "Invalid number of operands!"); Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum)); } void addMemNoOffsetTOperands(MCInst &Inst, unsigned N) const { assert(N == 1 && "Invalid number of operands!"); Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum)); } void addMemPCRelImm12Operands(MCInst &Inst, unsigned N) const { assert(N == 1 && "Invalid number of operands!"); int32_t Imm = Memory.OffsetImm->getValue(); Inst.addOperand(MCOperand::createImm(Imm)); } void addAdrLabelOperands(MCInst &Inst, unsigned N) const { assert(N == 1 && "Invalid number of operands!"); assert(isImm() && "Not an immediate!"); // If we have an immediate that's not a constant, treat it as a label // reference needing a fixup. if (!isa(getImm())) { Inst.addOperand(MCOperand::createExpr(getImm())); return; } const MCConstantExpr *CE = dyn_cast(getImm()); int Val = CE->getValue(); Inst.addOperand(MCOperand::createImm(Val)); } void addAlignedMemoryOperands(MCInst &Inst, unsigned N) const { assert(N == 2 && "Invalid number of operands!"); Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum)); Inst.addOperand(MCOperand::createImm(Memory.Alignment)); } void addDupAlignedMemoryNoneOperands(MCInst &Inst, unsigned N) const { addAlignedMemoryOperands(Inst, N); } void addAlignedMemoryNoneOperands(MCInst &Inst, unsigned N) const { addAlignedMemoryOperands(Inst, N); } void addAlignedMemory16Operands(MCInst &Inst, unsigned N) const { addAlignedMemoryOperands(Inst, N); } void addDupAlignedMemory16Operands(MCInst &Inst, unsigned N) const { addAlignedMemoryOperands(Inst, N); } void addAlignedMemory32Operands(MCInst &Inst, unsigned N) const { addAlignedMemoryOperands(Inst, N); } void addDupAlignedMemory32Operands(MCInst &Inst, unsigned N) const { addAlignedMemoryOperands(Inst, N); } void addAlignedMemory64Operands(MCInst &Inst, unsigned N) const { addAlignedMemoryOperands(Inst, N); } void addDupAlignedMemory64Operands(MCInst &Inst, unsigned N) const { addAlignedMemoryOperands(Inst, N); } void addAlignedMemory64or128Operands(MCInst &Inst, unsigned N) const { addAlignedMemoryOperands(Inst, N); } void addDupAlignedMemory64or128Operands(MCInst &Inst, unsigned N) const { addAlignedMemoryOperands(Inst, N); } void addAlignedMemory64or128or256Operands(MCInst &Inst, unsigned N) const { addAlignedMemoryOperands(Inst, N); } void addAddrMode2Operands(MCInst &Inst, unsigned N) const { assert(N == 3 && "Invalid number of operands!"); int32_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0; if (!Memory.OffsetRegNum) { ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add; // Special case for #-0 if (Val == std::numeric_limits::min()) Val = 0; if (Val < 0) Val = -Val; Val = ARM_AM::getAM2Opc(AddSub, Val, ARM_AM::no_shift); } else { // For register offset, we encode the shift type and negation flag // here. Val = ARM_AM::getAM2Opc(Memory.isNegative ? ARM_AM::sub : ARM_AM::add, Memory.ShiftImm, Memory.ShiftType); } Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum)); Inst.addOperand(MCOperand::createReg(Memory.OffsetRegNum)); Inst.addOperand(MCOperand::createImm(Val)); } void addAM2OffsetImmOperands(MCInst &Inst, unsigned N) const { assert(N == 2 && "Invalid number of operands!"); const MCConstantExpr *CE = dyn_cast(getImm()); assert(CE && "non-constant AM2OffsetImm operand!"); int32_t Val = CE->getValue(); ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add; // Special case for #-0 if (Val == std::numeric_limits::min()) Val = 0; if (Val < 0) Val = -Val; Val = ARM_AM::getAM2Opc(AddSub, Val, ARM_AM::no_shift); Inst.addOperand(MCOperand::createReg(0)); Inst.addOperand(MCOperand::createImm(Val)); } void addAddrMode3Operands(MCInst &Inst, unsigned N) const { assert(N == 3 && "Invalid number of operands!"); // If we have an immediate that's not a constant, treat it as a label // reference needing a fixup. If it is a constant, it's something else // and we reject it. if (isImm()) { Inst.addOperand(MCOperand::createExpr(getImm())); Inst.addOperand(MCOperand::createReg(0)); Inst.addOperand(MCOperand::createImm(0)); return; } int32_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0; if (!Memory.OffsetRegNum) { ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add; // Special case for #-0 if (Val == std::numeric_limits::min()) Val = 0; if (Val < 0) Val = -Val; Val = ARM_AM::getAM3Opc(AddSub, Val); } else { // For register offset, we encode the shift type and negation flag // here. Val = ARM_AM::getAM3Opc(Memory.isNegative ? ARM_AM::sub : ARM_AM::add, 0); } Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum)); Inst.addOperand(MCOperand::createReg(Memory.OffsetRegNum)); Inst.addOperand(MCOperand::createImm(Val)); } void addAM3OffsetOperands(MCInst &Inst, unsigned N) const { assert(N == 2 && "Invalid number of operands!"); if (Kind == k_PostIndexRegister) { int32_t Val = ARM_AM::getAM3Opc(PostIdxReg.isAdd ? ARM_AM::add : ARM_AM::sub, 0); Inst.addOperand(MCOperand::createReg(PostIdxReg.RegNum)); Inst.addOperand(MCOperand::createImm(Val)); return; } // Constant offset. const MCConstantExpr *CE = static_cast(getImm()); int32_t Val = CE->getValue(); ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add; // Special case for #-0 if (Val == std::numeric_limits::min()) Val = 0; if (Val < 0) Val = -Val; Val = ARM_AM::getAM3Opc(AddSub, Val); Inst.addOperand(MCOperand::createReg(0)); Inst.addOperand(MCOperand::createImm(Val)); } void addAddrMode5Operands(MCInst &Inst, unsigned N) const { assert(N == 2 && "Invalid number of operands!"); // If we have an immediate that's not a constant, treat it as a label // reference needing a fixup. If it is a constant, it's something else // and we reject it. if (isImm()) { Inst.addOperand(MCOperand::createExpr(getImm())); Inst.addOperand(MCOperand::createImm(0)); return; } // The lower two bits are always zero and as such are not encoded. int32_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() / 4 : 0; ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add; // Special case for #-0 if (Val == std::numeric_limits::min()) Val = 0; if (Val < 0) Val = -Val; Val = ARM_AM::getAM5Opc(AddSub, Val); Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum)); Inst.addOperand(MCOperand::createImm(Val)); } void addAddrMode5FP16Operands(MCInst &Inst, unsigned N) const { assert(N == 2 && "Invalid number of operands!"); // If we have an immediate that's not a constant, treat it as a label // reference needing a fixup. If it is a constant, it's something else // and we reject it. if (isImm()) { Inst.addOperand(MCOperand::createExpr(getImm())); Inst.addOperand(MCOperand::createImm(0)); return; } // The lower bit is always zero and as such is not encoded. int32_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() / 2 : 0; ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add; // Special case for #-0 if (Val == std::numeric_limits::min()) Val = 0; if (Val < 0) Val = -Val; Val = ARM_AM::getAM5FP16Opc(AddSub, Val); Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum)); Inst.addOperand(MCOperand::createImm(Val)); } void addMemImm8s4OffsetOperands(MCInst &Inst, unsigned N) const { assert(N == 2 && "Invalid number of operands!"); // If we have an immediate that's not a constant, treat it as a label // reference needing a fixup. If it is a constant, it's something else // and we reject it. if (isImm()) { Inst.addOperand(MCOperand::createExpr(getImm())); Inst.addOperand(MCOperand::createImm(0)); return; } int64_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0; Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum)); Inst.addOperand(MCOperand::createImm(Val)); } void addMemImm7s4OffsetOperands(MCInst &Inst, unsigned N) const { assert(N == 2 && "Invalid number of operands!"); // If we have an immediate that's not a constant, treat it as a label // reference needing a fixup. If it is a constant, it's something else // and we reject it. if (isImm()) { Inst.addOperand(MCOperand::createExpr(getImm())); Inst.addOperand(MCOperand::createImm(0)); return; } int64_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0; Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum)); Inst.addOperand(MCOperand::createImm(Val)); } void addMemImm0_1020s4OffsetOperands(MCInst &Inst, unsigned N) const { assert(N == 2 && "Invalid number of operands!"); // The lower two bits are always zero and as such are not encoded. int32_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() / 4 : 0; Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum)); Inst.addOperand(MCOperand::createImm(Val)); } void addMemImmOffsetOperands(MCInst &Inst, unsigned N) const { assert(N == 2 && "Invalid number of operands!"); int64_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0; Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum)); Inst.addOperand(MCOperand::createImm(Val)); } void addMemRegRQOffsetOperands(MCInst &Inst, unsigned N) const { assert(N == 2 && "Invalid number of operands!"); Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum)); Inst.addOperand(MCOperand::createReg(Memory.OffsetRegNum)); } void addMemUImm12OffsetOperands(MCInst &Inst, unsigned N) const { assert(N == 2 && "Invalid number of operands!"); // If this is an immediate, it's a label reference. if (isImm()) { addExpr(Inst, getImm()); Inst.addOperand(MCOperand::createImm(0)); return; } // Otherwise, it's a normal memory reg+offset. int64_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0; Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum)); Inst.addOperand(MCOperand::createImm(Val)); } void addMemImm12OffsetOperands(MCInst &Inst, unsigned N) const { assert(N == 2 && "Invalid number of operands!"); // If this is an immediate, it's a label reference. if (isImm()) { addExpr(Inst, getImm()); Inst.addOperand(MCOperand::createImm(0)); return; } // Otherwise, it's a normal memory reg+offset. int64_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0; Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum)); Inst.addOperand(MCOperand::createImm(Val)); } void addConstPoolAsmImmOperands(MCInst &Inst, unsigned N) const { assert(N == 1 && "Invalid number of operands!"); // This is container for the immediate that we will create the constant // pool from addExpr(Inst, getConstantPoolImm()); return; } void addMemTBBOperands(MCInst &Inst, unsigned N) const { assert(N == 2 && "Invalid number of operands!"); Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum)); Inst.addOperand(MCOperand::createReg(Memory.OffsetRegNum)); } void addMemTBHOperands(MCInst &Inst, unsigned N) const { assert(N == 2 && "Invalid number of operands!"); Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum)); Inst.addOperand(MCOperand::createReg(Memory.OffsetRegNum)); } void addMemRegOffsetOperands(MCInst &Inst, unsigned N) const { assert(N == 3 && "Invalid number of operands!"); unsigned Val = ARM_AM::getAM2Opc(Memory.isNegative ? ARM_AM::sub : ARM_AM::add, Memory.ShiftImm, Memory.ShiftType); Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum)); Inst.addOperand(MCOperand::createReg(Memory.OffsetRegNum)); Inst.addOperand(MCOperand::createImm(Val)); } void addT2MemRegOffsetOperands(MCInst &Inst, unsigned N) const { assert(N == 3 && "Invalid number of operands!"); Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum)); Inst.addOperand(MCOperand::createReg(Memory.OffsetRegNum)); Inst.addOperand(MCOperand::createImm(Memory.ShiftImm)); } void addMemThumbRROperands(MCInst &Inst, unsigned N) const { assert(N == 2 && "Invalid number of operands!"); Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum)); Inst.addOperand(MCOperand::createReg(Memory.OffsetRegNum)); } void addMemThumbRIs4Operands(MCInst &Inst, unsigned N) const { assert(N == 2 && "Invalid number of operands!"); int64_t Val = Memory.OffsetImm ? (Memory.OffsetImm->getValue() / 4) : 0; Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum)); Inst.addOperand(MCOperand::createImm(Val)); } void addMemThumbRIs2Operands(MCInst &Inst, unsigned N) const { assert(N == 2 && "Invalid number of operands!"); int64_t Val = Memory.OffsetImm ? (Memory.OffsetImm->getValue() / 2) : 0; Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum)); Inst.addOperand(MCOperand::createImm(Val)); } void addMemThumbRIs1Operands(MCInst &Inst, unsigned N) const { assert(N == 2 && "Invalid number of operands!"); int64_t Val = Memory.OffsetImm ? (Memory.OffsetImm->getValue()) : 0; Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum)); Inst.addOperand(MCOperand::createImm(Val)); } void addMemThumbSPIOperands(MCInst &Inst, unsigned N) const { assert(N == 2 && "Invalid number of operands!"); int64_t Val = Memory.OffsetImm ? (Memory.OffsetImm->getValue() / 4) : 0; Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum)); Inst.addOperand(MCOperand::createImm(Val)); } void addPostIdxImm8Operands(MCInst &Inst, unsigned N) const { assert(N == 1 && "Invalid number of operands!"); const MCConstantExpr *CE = dyn_cast(getImm()); assert(CE && "non-constant post-idx-imm8 operand!"); int Imm = CE->getValue(); bool isAdd = Imm >= 0; if (Imm == std::numeric_limits::min()) Imm = 0; Imm = (Imm < 0 ? -Imm : Imm) | (int)isAdd << 8; Inst.addOperand(MCOperand::createImm(Imm)); } void addPostIdxImm8s4Operands(MCInst &Inst, unsigned N) const { assert(N == 1 && "Invalid number of operands!"); const MCConstantExpr *CE = dyn_cast(getImm()); assert(CE && "non-constant post-idx-imm8s4 operand!"); int Imm = CE->getValue(); bool isAdd = Imm >= 0; if (Imm == std::numeric_limits::min()) Imm = 0; // Immediate is scaled by 4. Imm = ((Imm < 0 ? -Imm : Imm) / 4) | (int)isAdd << 8; Inst.addOperand(MCOperand::createImm(Imm)); } void addPostIdxRegOperands(MCInst &Inst, unsigned N) const { assert(N == 2 && "Invalid number of operands!"); Inst.addOperand(MCOperand::createReg(PostIdxReg.RegNum)); Inst.addOperand(MCOperand::createImm(PostIdxReg.isAdd)); } void addPostIdxRegShiftedOperands(MCInst &Inst, unsigned N) const { assert(N == 2 && "Invalid number of operands!"); Inst.addOperand(MCOperand::createReg(PostIdxReg.RegNum)); // The sign, shift type, and shift amount are encoded in a single operand // using the AM2 encoding helpers. ARM_AM::AddrOpc opc = PostIdxReg.isAdd ? ARM_AM::add : ARM_AM::sub; unsigned Imm = ARM_AM::getAM2Opc(opc, PostIdxReg.ShiftImm, PostIdxReg.ShiftTy); Inst.addOperand(MCOperand::createImm(Imm)); } void addPowerTwoOperands(MCInst &Inst, unsigned N) const { assert(N == 1 && "Invalid number of operands!"); const MCConstantExpr *CE = dyn_cast(getImm()); Inst.addOperand(MCOperand::createImm(CE->getValue())); } void addMSRMaskOperands(MCInst &Inst, unsigned N) const { assert(N == 1 && "Invalid number of operands!"); Inst.addOperand(MCOperand::createImm(unsigned(getMSRMask()))); } void addBankedRegOperands(MCInst &Inst, unsigned N) const { assert(N == 1 && "Invalid number of operands!"); Inst.addOperand(MCOperand::createImm(unsigned(getBankedReg()))); } void addProcIFlagsOperands(MCInst &Inst, unsigned N) const { assert(N == 1 && "Invalid number of operands!"); Inst.addOperand(MCOperand::createImm(unsigned(getProcIFlags()))); } void addVecListOperands(MCInst &Inst, unsigned N) const { assert(N == 1 && "Invalid number of operands!"); Inst.addOperand(MCOperand::createReg(VectorList.RegNum)); } void addMVEVecListOperands(MCInst &Inst, unsigned N) const { assert(N == 1 && "Invalid number of operands!"); // When we come here, the VectorList field will identify a range // of q-registers by its base register and length, and it will // have already been error-checked to be the expected length of // range and contain only q-regs in the range q0-q7. So we can // count on the base register being in the range q0-q6 (for 2 // regs) or q0-q4 (for 4) // // The MVE instructions taking a register range of this kind will // need an operand in the QQPR or QQQQPR class, representing the // entire range as a unit. So we must translate into that class, // by finding the index of the base register in the MQPR reg // class, and returning the super-register at the corresponding // index in the target class. const MCRegisterClass *RC_in = &ARMMCRegisterClasses[ARM::MQPRRegClassID]; const MCRegisterClass *RC_out = (VectorList.Count == 2) ? &ARMMCRegisterClasses[ARM::QQPRRegClassID] : &ARMMCRegisterClasses[ARM::QQQQPRRegClassID]; unsigned I, E = RC_out->getNumRegs(); for (I = 0; I < E; I++) if (RC_in->getRegister(I) == VectorList.RegNum) break; assert(I < E && "Invalid vector list start register!"); Inst.addOperand(MCOperand::createReg(RC_out->getRegister(I))); } void addVecListIndexedOperands(MCInst &Inst, unsigned N) const { assert(N == 2 && "Invalid number of operands!"); Inst.addOperand(MCOperand::createReg(VectorList.RegNum)); Inst.addOperand(MCOperand::createImm(VectorList.LaneIndex)); } void addVectorIndex8Operands(MCInst &Inst, unsigned N) const { assert(N == 1 && "Invalid number of operands!"); Inst.addOperand(MCOperand::createImm(getVectorIndex())); } void addVectorIndex16Operands(MCInst &Inst, unsigned N) const { assert(N == 1 && "Invalid number of operands!"); Inst.addOperand(MCOperand::createImm(getVectorIndex())); } void addVectorIndex32Operands(MCInst &Inst, unsigned N) const { assert(N == 1 && "Invalid number of operands!"); Inst.addOperand(MCOperand::createImm(getVectorIndex())); } void addVectorIndex64Operands(MCInst &Inst, unsigned N) const { assert(N == 1 && "Invalid number of operands!"); Inst.addOperand(MCOperand::createImm(getVectorIndex())); } void addMVEVectorIndexOperands(MCInst &Inst, unsigned N) const { assert(N == 1 && "Invalid number of operands!"); Inst.addOperand(MCOperand::createImm(getVectorIndex())); } void addMVEPairVectorIndexOperands(MCInst &Inst, unsigned N) const { assert(N == 1 && "Invalid number of operands!"); Inst.addOperand(MCOperand::createImm(getVectorIndex())); } void addNEONi8splatOperands(MCInst &Inst, unsigned N) const { assert(N == 1 && "Invalid number of operands!"); // The immediate encodes the type of constant as well as the value. // Mask in that this is an i8 splat. const MCConstantExpr *CE = dyn_cast(getImm()); Inst.addOperand(MCOperand::createImm(CE->getValue() | 0xe00)); } void addNEONi16splatOperands(MCInst &Inst, unsigned N) const { assert(N == 1 && "Invalid number of operands!"); // The immediate encodes the type of constant as well as the value. const MCConstantExpr *CE = dyn_cast(getImm()); unsigned Value = CE->getValue(); Value = ARM_AM::encodeNEONi16splat(Value); Inst.addOperand(MCOperand::createImm(Value)); } void addNEONi16splatNotOperands(MCInst &Inst, unsigned N) const { assert(N == 1 && "Invalid number of operands!"); // The immediate encodes the type of constant as well as the value. const MCConstantExpr *CE = dyn_cast(getImm()); unsigned Value = CE->getValue(); Value = ARM_AM::encodeNEONi16splat(~Value & 0xffff); Inst.addOperand(MCOperand::createImm(Value)); } void addNEONi32splatOperands(MCInst &Inst, unsigned N) const { assert(N == 1 && "Invalid number of operands!"); // The immediate encodes the type of constant as well as the value. const MCConstantExpr *CE = dyn_cast(getImm()); unsigned Value = CE->getValue(); Value = ARM_AM::encodeNEONi32splat(Value); Inst.addOperand(MCOperand::createImm(Value)); } void addNEONi32splatNotOperands(MCInst &Inst, unsigned N) const { assert(N == 1 && "Invalid number of operands!"); // The immediate encodes the type of constant as well as the value. const MCConstantExpr *CE = dyn_cast(getImm()); unsigned Value = CE->getValue(); Value = ARM_AM::encodeNEONi32splat(~Value); Inst.addOperand(MCOperand::createImm(Value)); } void addNEONi8ReplicateOperands(MCInst &Inst, bool Inv) const { // The immediate encodes the type of constant as well as the value. const MCConstantExpr *CE = dyn_cast(getImm()); assert((Inst.getOpcode() == ARM::VMOVv8i8 || Inst.getOpcode() == ARM::VMOVv16i8) && "All instructions that wants to replicate non-zero byte " "always must be replaced with VMOVv8i8 or VMOVv16i8."); unsigned Value = CE->getValue(); if (Inv) Value = ~Value; unsigned B = Value & 0xff; B |= 0xe00; // cmode = 0b1110 Inst.addOperand(MCOperand::createImm(B)); } void addNEONinvi8ReplicateOperands(MCInst &Inst, unsigned N) const { assert(N == 1 && "Invalid number of operands!"); addNEONi8ReplicateOperands(Inst, true); } static unsigned encodeNeonVMOVImmediate(unsigned Value) { if (Value >= 256 && Value <= 0xffff) Value = (Value >> 8) | ((Value & 0xff) ? 0xc00 : 0x200); else if (Value > 0xffff && Value <= 0xffffff) Value = (Value >> 16) | ((Value & 0xff) ? 0xd00 : 0x400); else if (Value > 0xffffff) Value = (Value >> 24) | 0x600; return Value; } void addNEONi32vmovOperands(MCInst &Inst, unsigned N) const { assert(N == 1 && "Invalid number of operands!"); // The immediate encodes the type of constant as well as the value. const MCConstantExpr *CE = dyn_cast(getImm()); unsigned Value = encodeNeonVMOVImmediate(CE->getValue()); Inst.addOperand(MCOperand::createImm(Value)); } void addNEONvmovi8ReplicateOperands(MCInst &Inst, unsigned N) const { assert(N == 1 && "Invalid number of operands!"); addNEONi8ReplicateOperands(Inst, false); } void addNEONvmovi16ReplicateOperands(MCInst &Inst, unsigned N) const { assert(N == 1 && "Invalid number of operands!"); const MCConstantExpr *CE = dyn_cast(getImm()); assert((Inst.getOpcode() == ARM::VMOVv4i16 || Inst.getOpcode() == ARM::VMOVv8i16 || Inst.getOpcode() == ARM::VMVNv4i16 || Inst.getOpcode() == ARM::VMVNv8i16) && "All instructions that want to replicate non-zero half-word " "always must be replaced with V{MOV,MVN}v{4,8}i16."); uint64_t Value = CE->getValue(); unsigned Elem = Value & 0xffff; if (Elem >= 256) Elem = (Elem >> 8) | 0x200; Inst.addOperand(MCOperand::createImm(Elem)); } void addNEONi32vmovNegOperands(MCInst &Inst, unsigned N) const { assert(N == 1 && "Invalid number of operands!"); // The immediate encodes the type of constant as well as the value. const MCConstantExpr *CE = dyn_cast(getImm()); unsigned Value = encodeNeonVMOVImmediate(~CE->getValue()); Inst.addOperand(MCOperand::createImm(Value)); } void addNEONvmovi32ReplicateOperands(MCInst &Inst, unsigned N) const { assert(N == 1 && "Invalid number of operands!"); const MCConstantExpr *CE = dyn_cast(getImm()); assert((Inst.getOpcode() == ARM::VMOVv2i32 || Inst.getOpcode() == ARM::VMOVv4i32 || Inst.getOpcode() == ARM::VMVNv2i32 || Inst.getOpcode() == ARM::VMVNv4i32) && "All instructions that want to replicate non-zero word " "always must be replaced with V{MOV,MVN}v{2,4}i32."); uint64_t Value = CE->getValue(); unsigned Elem = encodeNeonVMOVImmediate(Value & 0xffffffff); Inst.addOperand(MCOperand::createImm(Elem)); } void addNEONi64splatOperands(MCInst &Inst, unsigned N) const { assert(N == 1 && "Invalid number of operands!"); // The immediate encodes the type of constant as well as the value. const MCConstantExpr *CE = dyn_cast(getImm()); uint64_t Value = CE->getValue(); unsigned Imm = 0; for (unsigned i = 0; i < 8; ++i, Value >>= 8) { Imm |= (Value & 1) << i; } Inst.addOperand(MCOperand::createImm(Imm | 0x1e00)); } void addComplexRotationEvenOperands(MCInst &Inst, unsigned N) const { assert(N == 1 && "Invalid number of operands!"); const MCConstantExpr *CE = dyn_cast(getImm()); Inst.addOperand(MCOperand::createImm(CE->getValue() / 90)); } void addComplexRotationOddOperands(MCInst &Inst, unsigned N) const { assert(N == 1 && "Invalid number of operands!"); const MCConstantExpr *CE = dyn_cast(getImm()); Inst.addOperand(MCOperand::createImm((CE->getValue() - 90) / 180)); } void print(raw_ostream &OS) const override; static std::unique_ptr CreateITMask(unsigned Mask, SMLoc S) { auto Op = make_unique(k_ITCondMask); Op->ITMask.Mask = Mask; Op->StartLoc = S; Op->EndLoc = S; return Op; } static std::unique_ptr CreateCondCode(ARMCC::CondCodes CC, SMLoc S) { auto Op = make_unique(k_CondCode); Op->CC.Val = CC; Op->StartLoc = S; Op->EndLoc = S; return Op; } static std::unique_ptr CreateVPTPred(ARMVCC::VPTCodes CC, SMLoc S) { auto Op = make_unique(k_VPTPred); Op->VCC.Val = CC; Op->StartLoc = S; Op->EndLoc = S; return Op; } static std::unique_ptr CreateCoprocNum(unsigned CopVal, SMLoc S) { auto Op = make_unique(k_CoprocNum); Op->Cop.Val = CopVal; Op->StartLoc = S; Op->EndLoc = S; return Op; } static std::unique_ptr CreateCoprocReg(unsigned CopVal, SMLoc S) { auto Op = make_unique(k_CoprocReg); Op->Cop.Val = CopVal; Op->StartLoc = S; Op->EndLoc = S; return Op; } static std::unique_ptr CreateCoprocOption(unsigned Val, SMLoc S, SMLoc E) { auto Op = make_unique(k_CoprocOption); Op->Cop.Val = Val; Op->StartLoc = S; Op->EndLoc = E; return Op; } static std::unique_ptr CreateCCOut(unsigned RegNum, SMLoc S) { auto Op = make_unique(k_CCOut); Op->Reg.RegNum = RegNum; Op->StartLoc = S; Op->EndLoc = S; return Op; } static std::unique_ptr CreateToken(StringRef Str, SMLoc S) { auto Op = make_unique(k_Token); Op->Tok.Data = Str.data(); Op->Tok.Length = Str.size(); Op->StartLoc = S; Op->EndLoc = S; return Op; } static std::unique_ptr CreateReg(unsigned RegNum, SMLoc S, SMLoc E) { auto Op = make_unique(k_Register); Op->Reg.RegNum = RegNum; Op->StartLoc = S; Op->EndLoc = E; return Op; } static std::unique_ptr CreateShiftedRegister(ARM_AM::ShiftOpc ShTy, unsigned SrcReg, unsigned ShiftReg, unsigned ShiftImm, SMLoc S, SMLoc E) { auto Op = make_unique(k_ShiftedRegister); Op->RegShiftedReg.ShiftTy = ShTy; Op->RegShiftedReg.SrcReg = SrcReg; Op->RegShiftedReg.ShiftReg = ShiftReg; Op->RegShiftedReg.ShiftImm = ShiftImm; Op->StartLoc = S; Op->EndLoc = E; return Op; } static std::unique_ptr CreateShiftedImmediate(ARM_AM::ShiftOpc ShTy, unsigned SrcReg, unsigned ShiftImm, SMLoc S, SMLoc E) { auto Op = make_unique(k_ShiftedImmediate); Op->RegShiftedImm.ShiftTy = ShTy; Op->RegShiftedImm.SrcReg = SrcReg; Op->RegShiftedImm.ShiftImm = ShiftImm; Op->StartLoc = S; Op->EndLoc = E; return Op; } static std::unique_ptr CreateShifterImm(bool isASR, unsigned Imm, SMLoc S, SMLoc E) { auto Op = make_unique(k_ShifterImmediate); Op->ShifterImm.isASR = isASR; Op->ShifterImm.Imm = Imm; Op->StartLoc = S; Op->EndLoc = E; return Op; } static std::unique_ptr CreateRotImm(unsigned Imm, SMLoc S, SMLoc E) { auto Op = make_unique(k_RotateImmediate); Op->RotImm.Imm = Imm; Op->StartLoc = S; Op->EndLoc = E; return Op; } static std::unique_ptr CreateModImm(unsigned Bits, unsigned Rot, SMLoc S, SMLoc E) { auto Op = make_unique(k_ModifiedImmediate); Op->ModImm.Bits = Bits; Op->ModImm.Rot = Rot; Op->StartLoc = S; Op->EndLoc = E; return Op; } static std::unique_ptr CreateConstantPoolImm(const MCExpr *Val, SMLoc S, SMLoc E) { auto Op = make_unique(k_ConstantPoolImmediate); Op->Imm.Val = Val; Op->StartLoc = S; Op->EndLoc = E; return Op; } static std::unique_ptr CreateBitfield(unsigned LSB, unsigned Width, SMLoc S, SMLoc E) { auto Op = make_unique(k_BitfieldDescriptor); Op->Bitfield.LSB = LSB; Op->Bitfield.Width = Width; Op->StartLoc = S; Op->EndLoc = E; return Op; } static std::unique_ptr CreateRegList(SmallVectorImpl> &Regs, SMLoc StartLoc, SMLoc EndLoc) { assert(Regs.size() > 0 && "RegList contains no registers?"); KindTy Kind = k_RegisterList; if (ARMMCRegisterClasses[ARM::DPRRegClassID].contains( Regs.front().second)) { if (Regs.back().second == ARM::VPR) Kind = k_FPDRegisterListWithVPR; else Kind = k_DPRRegisterList; } else if (ARMMCRegisterClasses[ARM::SPRRegClassID].contains( Regs.front().second)) { if (Regs.back().second == ARM::VPR) Kind = k_FPSRegisterListWithVPR; else Kind = k_SPRRegisterList; } // Sort based on the register encoding values. array_pod_sort(Regs.begin(), Regs.end()); if (Kind == k_RegisterList && Regs.back().second == ARM::APSR) Kind = k_RegisterListWithAPSR; auto Op = make_unique(Kind); for (SmallVectorImpl>::const_iterator I = Regs.begin(), E = Regs.end(); I != E; ++I) Op->Registers.push_back(I->second); Op->StartLoc = StartLoc; Op->EndLoc = EndLoc; return Op; } static std::unique_ptr CreateVectorList(unsigned RegNum, unsigned Count, bool isDoubleSpaced, SMLoc S, SMLoc E) { auto Op = make_unique(k_VectorList); Op->VectorList.RegNum = RegNum; Op->VectorList.Count = Count; Op->VectorList.isDoubleSpaced = isDoubleSpaced; Op->StartLoc = S; Op->EndLoc = E; return Op; } static std::unique_ptr CreateVectorListAllLanes(unsigned RegNum, unsigned Count, bool isDoubleSpaced, SMLoc S, SMLoc E) { auto Op = make_unique(k_VectorListAllLanes); Op->VectorList.RegNum = RegNum; Op->VectorList.Count = Count; Op->VectorList.isDoubleSpaced = isDoubleSpaced; Op->StartLoc = S; Op->EndLoc = E; return Op; } static std::unique_ptr CreateVectorListIndexed(unsigned RegNum, unsigned Count, unsigned Index, bool isDoubleSpaced, SMLoc S, SMLoc E) { auto Op = make_unique(k_VectorListIndexed); Op->VectorList.RegNum = RegNum; Op->VectorList.Count = Count; Op->VectorList.LaneIndex = Index; Op->VectorList.isDoubleSpaced = isDoubleSpaced; Op->StartLoc = S; Op->EndLoc = E; return Op; } static std::unique_ptr CreateVectorIndex(unsigned Idx, SMLoc S, SMLoc E, MCContext &Ctx) { auto Op = make_unique(k_VectorIndex); Op->VectorIndex.Val = Idx; Op->StartLoc = S; Op->EndLoc = E; return Op; } static std::unique_ptr CreateImm(const MCExpr *Val, SMLoc S, SMLoc E) { auto Op = make_unique(k_Immediate); Op->Imm.Val = Val; Op->StartLoc = S; Op->EndLoc = E; return Op; } static std::unique_ptr CreateMem(unsigned BaseRegNum, const MCConstantExpr *OffsetImm, unsigned OffsetRegNum, ARM_AM::ShiftOpc ShiftType, unsigned ShiftImm, unsigned Alignment, bool isNegative, SMLoc S, SMLoc E, SMLoc AlignmentLoc = SMLoc()) { auto Op = make_unique(k_Memory); Op->Memory.BaseRegNum = BaseRegNum; Op->Memory.OffsetImm = OffsetImm; Op->Memory.OffsetRegNum = OffsetRegNum; Op->Memory.ShiftType = ShiftType; Op->Memory.ShiftImm = ShiftImm; Op->Memory.Alignment = Alignment; Op->Memory.isNegative = isNegative; Op->StartLoc = S; Op->EndLoc = E; Op->AlignmentLoc = AlignmentLoc; return Op; } static std::unique_ptr CreatePostIdxReg(unsigned RegNum, bool isAdd, ARM_AM::ShiftOpc ShiftTy, unsigned ShiftImm, SMLoc S, SMLoc E) { auto Op = make_unique(k_PostIndexRegister); Op->PostIdxReg.RegNum = RegNum; Op->PostIdxReg.isAdd = isAdd; Op->PostIdxReg.ShiftTy = ShiftTy; Op->PostIdxReg.ShiftImm = ShiftImm; Op->StartLoc = S; Op->EndLoc = E; return Op; } static std::unique_ptr CreateMemBarrierOpt(ARM_MB::MemBOpt Opt, SMLoc S) { auto Op = make_unique(k_MemBarrierOpt); Op->MBOpt.Val = Opt; Op->StartLoc = S; Op->EndLoc = S; return Op; } static std::unique_ptr CreateInstSyncBarrierOpt(ARM_ISB::InstSyncBOpt Opt, SMLoc S) { auto Op = make_unique(k_InstSyncBarrierOpt); Op->ISBOpt.Val = Opt; Op->StartLoc = S; Op->EndLoc = S; return Op; } static std::unique_ptr CreateTraceSyncBarrierOpt(ARM_TSB::TraceSyncBOpt Opt, SMLoc S) { auto Op = make_unique(k_TraceSyncBarrierOpt); Op->TSBOpt.Val = Opt; Op->StartLoc = S; Op->EndLoc = S; return Op; } static std::unique_ptr CreateProcIFlags(ARM_PROC::IFlags IFlags, SMLoc S) { auto Op = make_unique(k_ProcIFlags); Op->IFlags.Val = IFlags; Op->StartLoc = S; Op->EndLoc = S; return Op; } static std::unique_ptr CreateMSRMask(unsigned MMask, SMLoc S) { auto Op = make_unique(k_MSRMask); Op->MMask.Val = MMask; Op->StartLoc = S; Op->EndLoc = S; return Op; } static std::unique_ptr CreateBankedReg(unsigned Reg, SMLoc S) { auto Op = make_unique(k_BankedReg); Op->BankedReg.Val = Reg; Op->StartLoc = S; Op->EndLoc = S; return Op; } }; } // end anonymous namespace. void ARMOperand::print(raw_ostream &OS) const { auto RegName = [](unsigned Reg) { if (Reg) return ARMInstPrinter::getRegisterName(Reg); else return "noreg"; }; switch (Kind) { case k_CondCode: OS << ""; break; case k_VPTPred: OS << ""; break; case k_CCOut: OS << ""; break; case k_ITCondMask: { static const char *const MaskStr[] = { "(invalid)", "(tttt)", "(ttt)", "(ttte)", "(tt)", "(ttet)", "(tte)", "(ttee)", "(t)", "(tett)", "(tet)", "(tete)", "(te)", "(teet)", "(tee)", "(teee)", }; assert((ITMask.Mask & 0xf) == ITMask.Mask); OS << ""; break; } case k_CoprocNum: OS << ""; break; case k_CoprocReg: OS << ""; break; case k_CoprocOption: OS << ""; break; case k_MSRMask: OS << ""; break; case k_BankedReg: OS << ""; break; case k_Immediate: OS << *getImm(); break; case k_MemBarrierOpt: OS << ""; break; case k_InstSyncBarrierOpt: OS << ""; break; case k_TraceSyncBarrierOpt: OS << ""; break; case k_Memory: OS << ""; break; case k_PostIndexRegister: OS << "post-idx register " << (PostIdxReg.isAdd ? "" : "-") << RegName(PostIdxReg.RegNum); if (PostIdxReg.ShiftTy != ARM_AM::no_shift) OS << ARM_AM::getShiftOpcStr(PostIdxReg.ShiftTy) << " " << PostIdxReg.ShiftImm; OS << ">"; break; case k_ProcIFlags: { OS << "= 0; --i) if (IFlags & (1 << i)) OS << ARM_PROC::IFlagsToString(1 << i); OS << ">"; break; } case k_Register: OS << ""; break; case k_ShifterImmediate: OS << ""; break; case k_ShiftedRegister: OS << ""; break; case k_ShiftedImmediate: OS << ""; break; case k_RotateImmediate: OS << ""; break; case k_ModifiedImmediate: OS << ""; break; case k_ConstantPoolImmediate: OS << ""; break; case k_RegisterList: case k_RegisterListWithAPSR: case k_DPRRegisterList: case k_SPRRegisterList: case k_FPSRegisterListWithVPR: case k_FPDRegisterListWithVPR: { OS << " &RegList = getRegList(); for (SmallVectorImpl::const_iterator I = RegList.begin(), E = RegList.end(); I != E; ) { OS << RegName(*I); if (++I < E) OS << ", "; } OS << ">"; break; } case k_VectorList: OS << ""; break; case k_VectorListAllLanes: OS << ""; break; case k_VectorListIndexed: OS << ""; break; case k_Token: OS << "'" << getToken() << "'"; break; case k_VectorIndex: OS << ""; break; } } /// @name Auto-generated Match Functions /// { static unsigned MatchRegisterName(StringRef Name); /// } bool ARMAsmParser::ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc) { const AsmToken &Tok = getParser().getTok(); StartLoc = Tok.getLoc(); EndLoc = Tok.getEndLoc(); RegNo = tryParseRegister(); return (RegNo == (unsigned)-1); } /// Try to parse a register name. The token must be an Identifier when called, /// and if it is a register name the token is eaten and the register number is /// returned. Otherwise return -1. int ARMAsmParser::tryParseRegister() { MCAsmParser &Parser = getParser(); const AsmToken &Tok = Parser.getTok(); if (Tok.isNot(AsmToken::Identifier)) return -1; std::string lowerCase = Tok.getString().lower(); unsigned RegNum = MatchRegisterName(lowerCase); if (!RegNum) { RegNum = StringSwitch(lowerCase) .Case("r13", ARM::SP) .Case("r14", ARM::LR) .Case("r15", ARM::PC) .Case("ip", ARM::R12) // Additional register name aliases for 'gas' compatibility. .Case("a1", ARM::R0) .Case("a2", ARM::R1) .Case("a3", ARM::R2) .Case("a4", ARM::R3) .Case("v1", ARM::R4) .Case("v2", ARM::R5) .Case("v3", ARM::R6) .Case("v4", ARM::R7) .Case("v5", ARM::R8) .Case("v6", ARM::R9) .Case("v7", ARM::R10) .Case("v8", ARM::R11) .Case("sb", ARM::R9) .Case("sl", ARM::R10) .Case("fp", ARM::R11) .Default(0); } if (!RegNum) { // Check for aliases registered via .req. Canonicalize to lower case. // That's more consistent since register names are case insensitive, and // it's how the original entry was passed in from MC/MCParser/AsmParser. StringMap::const_iterator Entry = RegisterReqs.find(lowerCase); // If no match, return failure. if (Entry == RegisterReqs.end()) return -1; Parser.Lex(); // Eat identifier token. return Entry->getValue(); } // Some FPUs only have 16 D registers, so D16-D31 are invalid if (!hasD32() && RegNum >= ARM::D16 && RegNum <= ARM::D31) return -1; Parser.Lex(); // Eat identifier token. return RegNum; } // Try to parse a shifter (e.g., "lsl "). On success, return 0. // If a recoverable error occurs, return 1. If an irrecoverable error // occurs, return -1. An irrecoverable error is one where tokens have been // consumed in the process of trying to parse the shifter (i.e., when it is // indeed a shifter operand, but malformed). int ARMAsmParser::tryParseShiftRegister(OperandVector &Operands) { MCAsmParser &Parser = getParser(); SMLoc S = Parser.getTok().getLoc(); const AsmToken &Tok = Parser.getTok(); if (Tok.isNot(AsmToken::Identifier)) return -1; std::string lowerCase = Tok.getString().lower(); ARM_AM::ShiftOpc ShiftTy = StringSwitch(lowerCase) .Case("asl", ARM_AM::lsl) .Case("lsl", ARM_AM::lsl) .Case("lsr", ARM_AM::lsr) .Case("asr", ARM_AM::asr) .Case("ror", ARM_AM::ror) .Case("rrx", ARM_AM::rrx) .Default(ARM_AM::no_shift); if (ShiftTy == ARM_AM::no_shift) return 1; Parser.Lex(); // Eat the operator. // The source register for the shift has already been added to the // operand list, so we need to pop it off and combine it into the shifted // register operand instead. std::unique_ptr PrevOp( (ARMOperand *)Operands.pop_back_val().release()); if (!PrevOp->isReg()) return Error(PrevOp->getStartLoc(), "shift must be of a register"); int SrcReg = PrevOp->getReg(); SMLoc EndLoc; int64_t Imm = 0; int ShiftReg = 0; if (ShiftTy == ARM_AM::rrx) { // RRX Doesn't have an explicit shift amount. The encoder expects // the shift register to be the same as the source register. Seems odd, // but OK. ShiftReg = SrcReg; } else { // Figure out if this is shifted by a constant or a register (for non-RRX). if (Parser.getTok().is(AsmToken::Hash) || Parser.getTok().is(AsmToken::Dollar)) { Parser.Lex(); // Eat hash. SMLoc ImmLoc = Parser.getTok().getLoc(); const MCExpr *ShiftExpr = nullptr; if (getParser().parseExpression(ShiftExpr, EndLoc)) { Error(ImmLoc, "invalid immediate shift value"); return -1; } // The expression must be evaluatable as an immediate. const MCConstantExpr *CE = dyn_cast(ShiftExpr); if (!CE) { Error(ImmLoc, "invalid immediate shift value"); return -1; } // Range check the immediate. // lsl, ror: 0 <= imm <= 31 // lsr, asr: 0 <= imm <= 32 Imm = CE->getValue(); if (Imm < 0 || ((ShiftTy == ARM_AM::lsl || ShiftTy == ARM_AM::ror) && Imm > 31) || ((ShiftTy == ARM_AM::lsr || ShiftTy == ARM_AM::asr) && Imm > 32)) { Error(ImmLoc, "immediate shift value out of range"); return -1; } // shift by zero is a nop. Always send it through as lsl. // ('as' compatibility) if (Imm == 0) ShiftTy = ARM_AM::lsl; } else if (Parser.getTok().is(AsmToken::Identifier)) { SMLoc L = Parser.getTok().getLoc(); EndLoc = Parser.getTok().getEndLoc(); ShiftReg = tryParseRegister(); if (ShiftReg == -1) { Error(L, "expected immediate or register in shift operand"); return -1; } } else { Error(Parser.getTok().getLoc(), "expected immediate or register in shift operand"); return -1; } } if (ShiftReg && ShiftTy != ARM_AM::rrx) Operands.push_back(ARMOperand::CreateShiftedRegister(ShiftTy, SrcReg, ShiftReg, Imm, S, EndLoc)); else Operands.push_back(ARMOperand::CreateShiftedImmediate(ShiftTy, SrcReg, Imm, S, EndLoc)); return 0; } /// Try to parse a register name. The token must be an Identifier when called. /// If it's a register, an AsmOperand is created. Another AsmOperand is created /// if there is a "writeback". 'true' if it's not a register. /// /// TODO this is likely to change to allow different register types and or to /// parse for a specific register type. bool ARMAsmParser::tryParseRegisterWithWriteBack(OperandVector &Operands) { MCAsmParser &Parser = getParser(); SMLoc RegStartLoc = Parser.getTok().getLoc(); SMLoc RegEndLoc = Parser.getTok().getEndLoc(); int RegNo = tryParseRegister(); if (RegNo == -1) return true; Operands.push_back(ARMOperand::CreateReg(RegNo, RegStartLoc, RegEndLoc)); const AsmToken &ExclaimTok = Parser.getTok(); if (ExclaimTok.is(AsmToken::Exclaim)) { Operands.push_back(ARMOperand::CreateToken(ExclaimTok.getString(), ExclaimTok.getLoc())); Parser.Lex(); // Eat exclaim token return false; } // Also check for an index operand. This is only legal for vector registers, // but that'll get caught OK in operand matching, so we don't need to // explicitly filter everything else out here. if (Parser.getTok().is(AsmToken::LBrac)) { SMLoc SIdx = Parser.getTok().getLoc(); Parser.Lex(); // Eat left bracket token. const MCExpr *ImmVal; if (getParser().parseExpression(ImmVal)) return true; const MCConstantExpr *MCE = dyn_cast(ImmVal); if (!MCE) return TokError("immediate value expected for vector index"); if (Parser.getTok().isNot(AsmToken::RBrac)) return Error(Parser.getTok().getLoc(), "']' expected"); SMLoc E = Parser.getTok().getEndLoc(); Parser.Lex(); // Eat right bracket token. Operands.push_back(ARMOperand::CreateVectorIndex(MCE->getValue(), SIdx, E, getContext())); } return false; } /// MatchCoprocessorOperandName - Try to parse an coprocessor related /// instruction with a symbolic operand name. /// We accept "crN" syntax for GAS compatibility. /// ::= /// If CoprocOp is 'c', then: /// ::= c | cr /// If CoprocOp is 'p', then : /// ::= p /// ::= integer in range [0, 15] static int MatchCoprocessorOperandName(StringRef Name, char CoprocOp) { // Use the same layout as the tablegen'erated register name matcher. Ugly, // but efficient. if (Name.size() < 2 || Name[0] != CoprocOp) return -1; Name = (Name[1] == 'r') ? Name.drop_front(2) : Name.drop_front(); switch (Name.size()) { default: return -1; case 1: switch (Name[0]) { default: return -1; case '0': return 0; case '1': return 1; case '2': return 2; case '3': return 3; case '4': return 4; case '5': return 5; case '6': return 6; case '7': return 7; case '8': return 8; case '9': return 9; } case 2: if (Name[0] != '1') return -1; switch (Name[1]) { default: return -1; // CP10 and CP11 are VFP/NEON and so vector instructions should be used. // However, old cores (v5/v6) did use them in that way. case '0': return 10; case '1': return 11; case '2': return 12; case '3': return 13; case '4': return 14; case '5': return 15; } } } /// parseITCondCode - Try to parse a condition code for an IT instruction. OperandMatchResultTy ARMAsmParser::parseITCondCode(OperandVector &Operands) { MCAsmParser &Parser = getParser(); SMLoc S = Parser.getTok().getLoc(); const AsmToken &Tok = Parser.getTok(); if (!Tok.is(AsmToken::Identifier)) return MatchOperand_NoMatch; unsigned CC = ARMCondCodeFromString(Tok.getString()); if (CC == ~0U) return MatchOperand_NoMatch; Parser.Lex(); // Eat the token. Operands.push_back(ARMOperand::CreateCondCode(ARMCC::CondCodes(CC), S)); return MatchOperand_Success; } /// parseCoprocNumOperand - Try to parse an coprocessor number operand. The /// token must be an Identifier when called, and if it is a coprocessor /// number, the token is eaten and the operand is added to the operand list. OperandMatchResultTy ARMAsmParser::parseCoprocNumOperand(OperandVector &Operands) { MCAsmParser &Parser = getParser(); SMLoc S = Parser.getTok().getLoc(); const AsmToken &Tok = Parser.getTok(); if (Tok.isNot(AsmToken::Identifier)) return MatchOperand_NoMatch; int Num = MatchCoprocessorOperandName(Tok.getString().lower(), 'p'); if (Num == -1) return MatchOperand_NoMatch; if (!isValidCoprocessorNumber(Num, getSTI().getFeatureBits())) return MatchOperand_NoMatch; Parser.Lex(); // Eat identifier token. Operands.push_back(ARMOperand::CreateCoprocNum(Num, S)); return MatchOperand_Success; } /// parseCoprocRegOperand - Try to parse an coprocessor register operand. The /// token must be an Identifier when called, and if it is a coprocessor /// number, the token is eaten and the operand is added to the operand list. OperandMatchResultTy ARMAsmParser::parseCoprocRegOperand(OperandVector &Operands) { MCAsmParser &Parser = getParser(); SMLoc S = Parser.getTok().getLoc(); const AsmToken &Tok = Parser.getTok(); if (Tok.isNot(AsmToken::Identifier)) return MatchOperand_NoMatch; int Reg = MatchCoprocessorOperandName(Tok.getString().lower(), 'c'); if (Reg == -1) return MatchOperand_NoMatch; Parser.Lex(); // Eat identifier token. Operands.push_back(ARMOperand::CreateCoprocReg(Reg, S)); return MatchOperand_Success; } /// parseCoprocOptionOperand - Try to parse an coprocessor option operand. /// coproc_option : '{' imm0_255 '}' OperandMatchResultTy ARMAsmParser::parseCoprocOptionOperand(OperandVector &Operands) { MCAsmParser &Parser = getParser(); SMLoc S = Parser.getTok().getLoc(); // If this isn't a '{', this isn't a coprocessor immediate operand. if (Parser.getTok().isNot(AsmToken::LCurly)) return MatchOperand_NoMatch; Parser.Lex(); // Eat the '{' const MCExpr *Expr; SMLoc Loc = Parser.getTok().getLoc(); if (getParser().parseExpression(Expr)) { Error(Loc, "illegal expression"); return MatchOperand_ParseFail; } const MCConstantExpr *CE = dyn_cast(Expr); if (!CE || CE->getValue() < 0 || CE->getValue() > 255) { Error(Loc, "coprocessor option must be an immediate in range [0, 255]"); return MatchOperand_ParseFail; } int Val = CE->getValue(); // Check for and consume the closing '}' if (Parser.getTok().isNot(AsmToken::RCurly)) return MatchOperand_ParseFail; SMLoc E = Parser.getTok().getEndLoc(); Parser.Lex(); // Eat the '}' Operands.push_back(ARMOperand::CreateCoprocOption(Val, S, E)); return MatchOperand_Success; } // For register list parsing, we need to map from raw GPR register numbering // to the enumeration values. The enumeration values aren't sorted by // register number due to our using "sp", "lr" and "pc" as canonical names. static unsigned getNextRegister(unsigned Reg) { // If this is a GPR, we need to do it manually, otherwise we can rely // on the sort ordering of the enumeration since the other reg-classes // are sane. if (!ARMMCRegisterClasses[ARM::GPRRegClassID].contains(Reg)) return Reg + 1; switch(Reg) { default: llvm_unreachable("Invalid GPR number!"); case ARM::R0: return ARM::R1; case ARM::R1: return ARM::R2; case ARM::R2: return ARM::R3; case ARM::R3: return ARM::R4; case ARM::R4: return ARM::R5; case ARM::R5: return ARM::R6; case ARM::R6: return ARM::R7; case ARM::R7: return ARM::R8; case ARM::R8: return ARM::R9; case ARM::R9: return ARM::R10; case ARM::R10: return ARM::R11; case ARM::R11: return ARM::R12; case ARM::R12: return ARM::SP; case ARM::SP: return ARM::LR; case ARM::LR: return ARM::PC; case ARM::PC: return ARM::R0; } } /// Parse a register list. bool ARMAsmParser::parseRegisterList(OperandVector &Operands, bool EnforceOrder) { MCAsmParser &Parser = getParser(); if (Parser.getTok().isNot(AsmToken::LCurly)) return TokError("Token is not a Left Curly Brace"); SMLoc S = Parser.getTok().getLoc(); Parser.Lex(); // Eat '{' token. SMLoc RegLoc = Parser.getTok().getLoc(); // Check the first register in the list to see what register class // this is a list of. int Reg = tryParseRegister(); if (Reg == -1) return Error(RegLoc, "register expected"); // The reglist instructions have at most 16 registers, so reserve // space for that many. int EReg = 0; SmallVector, 16> Registers; // Allow Q regs and just interpret them as the two D sub-registers. if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(Reg)) { Reg = getDRegFromQReg(Reg); EReg = MRI->getEncodingValue(Reg); Registers.push_back(std::pair(EReg, Reg)); ++Reg; } const MCRegisterClass *RC; if (ARMMCRegisterClasses[ARM::GPRRegClassID].contains(Reg)) RC = &ARMMCRegisterClasses[ARM::GPRRegClassID]; else if (ARMMCRegisterClasses[ARM::DPRRegClassID].contains(Reg)) RC = &ARMMCRegisterClasses[ARM::DPRRegClassID]; else if (ARMMCRegisterClasses[ARM::SPRRegClassID].contains(Reg)) RC = &ARMMCRegisterClasses[ARM::SPRRegClassID]; else if (ARMMCRegisterClasses[ARM::GPRwithAPSRnospRegClassID].contains(Reg)) RC = &ARMMCRegisterClasses[ARM::GPRwithAPSRnospRegClassID]; else return Error(RegLoc, "invalid register in register list"); // Store the register. EReg = MRI->getEncodingValue(Reg); Registers.push_back(std::pair(EReg, Reg)); // This starts immediately after the first register token in the list, // so we can see either a comma or a minus (range separator) as a legal // next token. while (Parser.getTok().is(AsmToken::Comma) || Parser.getTok().is(AsmToken::Minus)) { if (Parser.getTok().is(AsmToken::Minus)) { Parser.Lex(); // Eat the minus. SMLoc AfterMinusLoc = Parser.getTok().getLoc(); int EndReg = tryParseRegister(); if (EndReg == -1) return Error(AfterMinusLoc, "register expected"); // Allow Q regs and just interpret them as the two D sub-registers. if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(EndReg)) EndReg = getDRegFromQReg(EndReg) + 1; // If the register is the same as the start reg, there's nothing // more to do. if (Reg == EndReg) continue; // The register must be in the same register class as the first. if (!RC->contains(EndReg)) return Error(AfterMinusLoc, "invalid register in register list"); // Ranges must go from low to high. if (MRI->getEncodingValue(Reg) > MRI->getEncodingValue(EndReg)) return Error(AfterMinusLoc, "bad range in register list"); // Add all the registers in the range to the register list. while (Reg != EndReg) { Reg = getNextRegister(Reg); EReg = MRI->getEncodingValue(Reg); Registers.push_back(std::pair(EReg, Reg)); } continue; } Parser.Lex(); // Eat the comma. RegLoc = Parser.getTok().getLoc(); int OldReg = Reg; const AsmToken RegTok = Parser.getTok(); Reg = tryParseRegister(); if (Reg == -1) return Error(RegLoc, "register expected"); // Allow Q regs and just interpret them as the two D sub-registers. bool isQReg = false; if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(Reg)) { Reg = getDRegFromQReg(Reg); isQReg = true; } if (!RC->contains(Reg) && RC->getID() == ARMMCRegisterClasses[ARM::GPRRegClassID].getID() && ARMMCRegisterClasses[ARM::GPRwithAPSRnospRegClassID].contains(Reg)) { // switch the register classes, as GPRwithAPSRnospRegClassID is a partial // subset of GPRRegClassId except it contains APSR as well. RC = &ARMMCRegisterClasses[ARM::GPRwithAPSRnospRegClassID]; } if (Reg == ARM::VPR && (RC == &ARMMCRegisterClasses[ARM::SPRRegClassID] || RC == &ARMMCRegisterClasses[ARM::DPRRegClassID])) { RC = &ARMMCRegisterClasses[ARM::FPWithVPRRegClassID]; EReg = MRI->getEncodingValue(Reg); Registers.push_back(std::pair(EReg, Reg)); continue; } // The register must be in the same register class as the first. if (!RC->contains(Reg)) return Error(RegLoc, "invalid register in register list"); // In most cases, the list must be monotonically increasing. An // exception is CLRM, which is order-independent anyway, so // there's no potential for confusion if you write clrm {r2,r1} // instead of clrm {r1,r2}. if (EnforceOrder && MRI->getEncodingValue(Reg) < MRI->getEncodingValue(OldReg)) { if (ARMMCRegisterClasses[ARM::GPRRegClassID].contains(Reg)) Warning(RegLoc, "register list not in ascending order"); else if (!ARMMCRegisterClasses[ARM::GPRwithAPSRnospRegClassID].contains(Reg)) return Error(RegLoc, "register list not in ascending order"); } if (MRI->getEncodingValue(Reg) == MRI->getEncodingValue(OldReg)) { Warning(RegLoc, "duplicated register (" + RegTok.getString() + ") in register list"); continue; } // VFP register lists must also be contiguous. if (RC != &ARMMCRegisterClasses[ARM::GPRRegClassID] && RC != &ARMMCRegisterClasses[ARM::GPRwithAPSRnospRegClassID] && Reg != OldReg + 1) return Error(RegLoc, "non-contiguous register range"); EReg = MRI->getEncodingValue(Reg); Registers.push_back(std::pair(EReg, Reg)); if (isQReg) { EReg = MRI->getEncodingValue(++Reg); Registers.push_back(std::pair(EReg, Reg)); } } if (Parser.getTok().isNot(AsmToken::RCurly)) return Error(Parser.getTok().getLoc(), "'}' expected"); SMLoc E = Parser.getTok().getEndLoc(); Parser.Lex(); // Eat '}' token. // Push the register list operand. Operands.push_back(ARMOperand::CreateRegList(Registers, S, E)); // The ARM system instruction variants for LDM/STM have a '^' token here. if (Parser.getTok().is(AsmToken::Caret)) { Operands.push_back(ARMOperand::CreateToken("^",Parser.getTok().getLoc())); Parser.Lex(); // Eat '^' token. } return false; } // Helper function to parse the lane index for vector lists. OperandMatchResultTy ARMAsmParser:: parseVectorLane(VectorLaneTy &LaneKind, unsigned &Index, SMLoc &EndLoc) { MCAsmParser &Parser = getParser(); Index = 0; // Always return a defined index value. if (Parser.getTok().is(AsmToken::LBrac)) { Parser.Lex(); // Eat the '['. if (Parser.getTok().is(AsmToken::RBrac)) { // "Dn[]" is the 'all lanes' syntax. LaneKind = AllLanes; EndLoc = Parser.getTok().getEndLoc(); Parser.Lex(); // Eat the ']'. return MatchOperand_Success; } // There's an optional '#' token here. Normally there wouldn't be, but // inline assemble puts one in, and it's friendly to accept that. if (Parser.getTok().is(AsmToken::Hash)) Parser.Lex(); // Eat '#' or '$'. const MCExpr *LaneIndex; SMLoc Loc = Parser.getTok().getLoc(); if (getParser().parseExpression(LaneIndex)) { Error(Loc, "illegal expression"); return MatchOperand_ParseFail; } const MCConstantExpr *CE = dyn_cast(LaneIndex); if (!CE) { Error(Loc, "lane index must be empty or an integer"); return MatchOperand_ParseFail; } if (Parser.getTok().isNot(AsmToken::RBrac)) { Error(Parser.getTok().getLoc(), "']' expected"); return MatchOperand_ParseFail; } EndLoc = Parser.getTok().getEndLoc(); Parser.Lex(); // Eat the ']'. int64_t Val = CE->getValue(); // FIXME: Make this range check context sensitive for .8, .16, .32. if (Val < 0 || Val > 7) { Error(Parser.getTok().getLoc(), "lane index out of range"); return MatchOperand_ParseFail; } Index = Val; LaneKind = IndexedLane; return MatchOperand_Success; } LaneKind = NoLanes; return MatchOperand_Success; } // parse a vector register list OperandMatchResultTy ARMAsmParser::parseVectorList(OperandVector &Operands) { MCAsmParser &Parser = getParser(); VectorLaneTy LaneKind; unsigned LaneIndex; SMLoc S = Parser.getTok().getLoc(); // As an extension (to match gas), support a plain D register or Q register // (without encosing curly braces) as a single or double entry list, // respectively. if (!hasMVE() && Parser.getTok().is(AsmToken::Identifier)) { SMLoc E = Parser.getTok().getEndLoc(); int Reg = tryParseRegister(); if (Reg == -1) return MatchOperand_NoMatch; if (ARMMCRegisterClasses[ARM::DPRRegClassID].contains(Reg)) { OperandMatchResultTy Res = parseVectorLane(LaneKind, LaneIndex, E); if (Res != MatchOperand_Success) return Res; switch (LaneKind) { case NoLanes: Operands.push_back(ARMOperand::CreateVectorList(Reg, 1, false, S, E)); break; case AllLanes: Operands.push_back(ARMOperand::CreateVectorListAllLanes(Reg, 1, false, S, E)); break; case IndexedLane: Operands.push_back(ARMOperand::CreateVectorListIndexed(Reg, 1, LaneIndex, false, S, E)); break; } return MatchOperand_Success; } if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(Reg)) { Reg = getDRegFromQReg(Reg); OperandMatchResultTy Res = parseVectorLane(LaneKind, LaneIndex, E); if (Res != MatchOperand_Success) return Res; switch (LaneKind) { case NoLanes: Reg = MRI->getMatchingSuperReg(Reg, ARM::dsub_0, &ARMMCRegisterClasses[ARM::DPairRegClassID]); Operands.push_back(ARMOperand::CreateVectorList(Reg, 2, false, S, E)); break; case AllLanes: Reg = MRI->getMatchingSuperReg(Reg, ARM::dsub_0, &ARMMCRegisterClasses[ARM::DPairRegClassID]); Operands.push_back(ARMOperand::CreateVectorListAllLanes(Reg, 2, false, S, E)); break; case IndexedLane: Operands.push_back(ARMOperand::CreateVectorListIndexed(Reg, 2, LaneIndex, false, S, E)); break; } return MatchOperand_Success; } Error(S, "vector register expected"); return MatchOperand_ParseFail; } if (Parser.getTok().isNot(AsmToken::LCurly)) return MatchOperand_NoMatch; Parser.Lex(); // Eat '{' token. SMLoc RegLoc = Parser.getTok().getLoc(); int Reg = tryParseRegister(); if (Reg == -1) { Error(RegLoc, "register expected"); return MatchOperand_ParseFail; } unsigned Count = 1; int Spacing = 0; unsigned FirstReg = Reg; if (hasMVE() && !ARMMCRegisterClasses[ARM::MQPRRegClassID].contains(Reg)) { Error(Parser.getTok().getLoc(), "vector register in range Q0-Q7 expected"); return MatchOperand_ParseFail; } // The list is of D registers, but we also allow Q regs and just interpret // them as the two D sub-registers. else if (!hasMVE() && ARMMCRegisterClasses[ARM::QPRRegClassID].contains(Reg)) { FirstReg = Reg = getDRegFromQReg(Reg); Spacing = 1; // double-spacing requires explicit D registers, otherwise // it's ambiguous with four-register single spaced. ++Reg; ++Count; } SMLoc E; if (parseVectorLane(LaneKind, LaneIndex, E) != MatchOperand_Success) return MatchOperand_ParseFail; while (Parser.getTok().is(AsmToken::Comma) || Parser.getTok().is(AsmToken::Minus)) { if (Parser.getTok().is(AsmToken::Minus)) { if (!Spacing) Spacing = 1; // Register range implies a single spaced list. else if (Spacing == 2) { Error(Parser.getTok().getLoc(), "sequential registers in double spaced list"); return MatchOperand_ParseFail; } Parser.Lex(); // Eat the minus. SMLoc AfterMinusLoc = Parser.getTok().getLoc(); int EndReg = tryParseRegister(); if (EndReg == -1) { Error(AfterMinusLoc, "register expected"); return MatchOperand_ParseFail; } // Allow Q regs and just interpret them as the two D sub-registers. if (!hasMVE() && ARMMCRegisterClasses[ARM::QPRRegClassID].contains(EndReg)) EndReg = getDRegFromQReg(EndReg) + 1; // If the register is the same as the start reg, there's nothing // more to do. if (Reg == EndReg) continue; // The register must be in the same register class as the first. if ((hasMVE() && !ARMMCRegisterClasses[ARM::MQPRRegClassID].contains(EndReg)) || (!hasMVE() && !ARMMCRegisterClasses[ARM::DPRRegClassID].contains(EndReg))) { Error(AfterMinusLoc, "invalid register in register list"); return MatchOperand_ParseFail; } // Ranges must go from low to high. if (Reg > EndReg) { Error(AfterMinusLoc, "bad range in register list"); return MatchOperand_ParseFail; } // Parse the lane specifier if present. VectorLaneTy NextLaneKind; unsigned NextLaneIndex; if (parseVectorLane(NextLaneKind, NextLaneIndex, E) != MatchOperand_Success) return MatchOperand_ParseFail; if (NextLaneKind != LaneKind || LaneIndex != NextLaneIndex) { Error(AfterMinusLoc, "mismatched lane index in register list"); return MatchOperand_ParseFail; } // Add all the registers in the range to the register list. Count += EndReg - Reg; Reg = EndReg; continue; } Parser.Lex(); // Eat the comma. RegLoc = Parser.getTok().getLoc(); int OldReg = Reg; Reg = tryParseRegister(); if (Reg == -1) { Error(RegLoc, "register expected"); return MatchOperand_ParseFail; } if (hasMVE()) { if (!ARMMCRegisterClasses[ARM::MQPRRegClassID].contains(Reg)) { Error(RegLoc, "vector register in range Q0-Q7 expected"); return MatchOperand_ParseFail; } Spacing = 1; } // vector register lists must be contiguous. // It's OK to use the enumeration values directly here rather, as the // VFP register classes have the enum sorted properly. // // The list is of D registers, but we also allow Q regs and just interpret // them as the two D sub-registers. else if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(Reg)) { if (!Spacing) Spacing = 1; // Register range implies a single spaced list. else if (Spacing == 2) { Error(RegLoc, "invalid register in double-spaced list (must be 'D' register')"); return MatchOperand_ParseFail; } Reg = getDRegFromQReg(Reg); if (Reg != OldReg + 1) { Error(RegLoc, "non-contiguous register range"); return MatchOperand_ParseFail; } ++Reg; Count += 2; // Parse the lane specifier if present. VectorLaneTy NextLaneKind; unsigned NextLaneIndex; SMLoc LaneLoc = Parser.getTok().getLoc(); if (parseVectorLane(NextLaneKind, NextLaneIndex, E) != MatchOperand_Success) return MatchOperand_ParseFail; if (NextLaneKind != LaneKind || LaneIndex != NextLaneIndex) { Error(LaneLoc, "mismatched lane index in register list"); return MatchOperand_ParseFail; } continue; } // Normal D register. // Figure out the register spacing (single or double) of the list if // we don't know it already. if (!Spacing) Spacing = 1 + (Reg == OldReg + 2); // Just check that it's contiguous and keep going. if (Reg != OldReg + Spacing) { Error(RegLoc, "non-contiguous register range"); return MatchOperand_ParseFail; } ++Count; // Parse the lane specifier if present. VectorLaneTy NextLaneKind; unsigned NextLaneIndex; SMLoc EndLoc = Parser.getTok().getLoc(); if (parseVectorLane(NextLaneKind, NextLaneIndex, E) != MatchOperand_Success) return MatchOperand_ParseFail; if (NextLaneKind != LaneKind || LaneIndex != NextLaneIndex) { Error(EndLoc, "mismatched lane index in register list"); return MatchOperand_ParseFail; } } if (Parser.getTok().isNot(AsmToken::RCurly)) { Error(Parser.getTok().getLoc(), "'}' expected"); return MatchOperand_ParseFail; } E = Parser.getTok().getEndLoc(); Parser.Lex(); // Eat '}' token. switch (LaneKind) { case NoLanes: case AllLanes: { // Two-register operands have been converted to the // composite register classes. if (Count == 2 && !hasMVE()) { const MCRegisterClass *RC = (Spacing == 1) ? &ARMMCRegisterClasses[ARM::DPairRegClassID] : &ARMMCRegisterClasses[ARM::DPairSpcRegClassID]; FirstReg = MRI->getMatchingSuperReg(FirstReg, ARM::dsub_0, RC); } auto Create = (LaneKind == NoLanes ? ARMOperand::CreateVectorList : ARMOperand::CreateVectorListAllLanes); Operands.push_back(Create(FirstReg, Count, (Spacing == 2), S, E)); break; } case IndexedLane: Operands.push_back(ARMOperand::CreateVectorListIndexed(FirstReg, Count, LaneIndex, (Spacing == 2), S, E)); break; } return MatchOperand_Success; } /// parseMemBarrierOptOperand - Try to parse DSB/DMB data barrier options. OperandMatchResultTy ARMAsmParser::parseMemBarrierOptOperand(OperandVector &Operands) { MCAsmParser &Parser = getParser(); SMLoc S = Parser.getTok().getLoc(); const AsmToken &Tok = Parser.getTok(); unsigned Opt; if (Tok.is(AsmToken::Identifier)) { StringRef OptStr = Tok.getString(); Opt = StringSwitch(OptStr.slice(0, OptStr.size()).lower()) .Case("sy", ARM_MB::SY) .Case("st", ARM_MB::ST) .Case("ld", ARM_MB::LD) .Case("sh", ARM_MB::ISH) .Case("ish", ARM_MB::ISH) .Case("shst", ARM_MB::ISHST) .Case("ishst", ARM_MB::ISHST) .Case("ishld", ARM_MB::ISHLD) .Case("nsh", ARM_MB::NSH) .Case("un", ARM_MB::NSH) .Case("nshst", ARM_MB::NSHST) .Case("nshld", ARM_MB::NSHLD) .Case("unst", ARM_MB::NSHST) .Case("osh", ARM_MB::OSH) .Case("oshst", ARM_MB::OSHST) .Case("oshld", ARM_MB::OSHLD) .Default(~0U); // ishld, oshld, nshld and ld are only available from ARMv8. if (!hasV8Ops() && (Opt == ARM_MB::ISHLD || Opt == ARM_MB::OSHLD || Opt == ARM_MB::NSHLD || Opt == ARM_MB::LD)) Opt = ~0U; if (Opt == ~0U) return MatchOperand_NoMatch; Parser.Lex(); // Eat identifier token. } else if (Tok.is(AsmToken::Hash) || Tok.is(AsmToken::Dollar) || Tok.is(AsmToken::Integer)) { if (Parser.getTok().isNot(AsmToken::Integer)) Parser.Lex(); // Eat '#' or '$'. SMLoc Loc = Parser.getTok().getLoc(); const MCExpr *MemBarrierID; if (getParser().parseExpression(MemBarrierID)) { Error(Loc, "illegal expression"); return MatchOperand_ParseFail; } const MCConstantExpr *CE = dyn_cast(MemBarrierID); if (!CE) { Error(Loc, "constant expression expected"); return MatchOperand_ParseFail; } int Val = CE->getValue(); if (Val & ~0xf) { Error(Loc, "immediate value out of range"); return MatchOperand_ParseFail; } Opt = ARM_MB::RESERVED_0 + Val; } else return MatchOperand_ParseFail; Operands.push_back(ARMOperand::CreateMemBarrierOpt((ARM_MB::MemBOpt)Opt, S)); return MatchOperand_Success; } OperandMatchResultTy ARMAsmParser::parseTraceSyncBarrierOptOperand(OperandVector &Operands) { MCAsmParser &Parser = getParser(); SMLoc S = Parser.getTok().getLoc(); const AsmToken &Tok = Parser.getTok(); if (Tok.isNot(AsmToken::Identifier)) return MatchOperand_NoMatch; if (!Tok.getString().equals_lower("csync")) return MatchOperand_NoMatch; Parser.Lex(); // Eat identifier token. Operands.push_back(ARMOperand::CreateTraceSyncBarrierOpt(ARM_TSB::CSYNC, S)); return MatchOperand_Success; } /// parseInstSyncBarrierOptOperand - Try to parse ISB inst sync barrier options. OperandMatchResultTy ARMAsmParser::parseInstSyncBarrierOptOperand(OperandVector &Operands) { MCAsmParser &Parser = getParser(); SMLoc S = Parser.getTok().getLoc(); const AsmToken &Tok = Parser.getTok(); unsigned Opt; if (Tok.is(AsmToken::Identifier)) { StringRef OptStr = Tok.getString(); if (OptStr.equals_lower("sy")) Opt = ARM_ISB::SY; else return MatchOperand_NoMatch; Parser.Lex(); // Eat identifier token. } else if (Tok.is(AsmToken::Hash) || Tok.is(AsmToken::Dollar) || Tok.is(AsmToken::Integer)) { if (Parser.getTok().isNot(AsmToken::Integer)) Parser.Lex(); // Eat '#' or '$'. SMLoc Loc = Parser.getTok().getLoc(); const MCExpr *ISBarrierID; if (getParser().parseExpression(ISBarrierID)) { Error(Loc, "illegal expression"); return MatchOperand_ParseFail; } const MCConstantExpr *CE = dyn_cast(ISBarrierID); if (!CE) { Error(Loc, "constant expression expected"); return MatchOperand_ParseFail; } int Val = CE->getValue(); if (Val & ~0xf) { Error(Loc, "immediate value out of range"); return MatchOperand_ParseFail; } Opt = ARM_ISB::RESERVED_0 + Val; } else return MatchOperand_ParseFail; Operands.push_back(ARMOperand::CreateInstSyncBarrierOpt( (ARM_ISB::InstSyncBOpt)Opt, S)); return MatchOperand_Success; } /// parseProcIFlagsOperand - Try to parse iflags from CPS instruction. OperandMatchResultTy ARMAsmParser::parseProcIFlagsOperand(OperandVector &Operands) { MCAsmParser &Parser = getParser(); SMLoc S = Parser.getTok().getLoc(); const AsmToken &Tok = Parser.getTok(); if (!Tok.is(AsmToken::Identifier)) return MatchOperand_NoMatch; StringRef IFlagsStr = Tok.getString(); // An iflags string of "none" is interpreted to mean that none of the AIF // bits are set. Not a terribly useful instruction, but a valid encoding. unsigned IFlags = 0; if (IFlagsStr != "none") { for (int i = 0, e = IFlagsStr.size(); i != e; ++i) { unsigned Flag = StringSwitch(IFlagsStr.substr(i, 1).lower()) .Case("a", ARM_PROC::A) .Case("i", ARM_PROC::I) .Case("f", ARM_PROC::F) .Default(~0U); // If some specific iflag is already set, it means that some letter is // present more than once, this is not acceptable. if (Flag == ~0U || (IFlags & Flag)) return MatchOperand_NoMatch; IFlags |= Flag; } } Parser.Lex(); // Eat identifier token. Operands.push_back(ARMOperand::CreateProcIFlags((ARM_PROC::IFlags)IFlags, S)); return MatchOperand_Success; } /// parseMSRMaskOperand - Try to parse mask flags from MSR instruction. OperandMatchResultTy ARMAsmParser::parseMSRMaskOperand(OperandVector &Operands) { MCAsmParser &Parser = getParser(); SMLoc S = Parser.getTok().getLoc(); const AsmToken &Tok = Parser.getTok(); if (Tok.is(AsmToken::Integer)) { int64_t Val = Tok.getIntVal(); if (Val > 255 || Val < 0) { return MatchOperand_NoMatch; } unsigned SYSmvalue = Val & 0xFF; Parser.Lex(); Operands.push_back(ARMOperand::CreateMSRMask(SYSmvalue, S)); return MatchOperand_Success; } if (!Tok.is(AsmToken::Identifier)) return MatchOperand_NoMatch; StringRef Mask = Tok.getString(); if (isMClass()) { auto TheReg = ARMSysReg::lookupMClassSysRegByName(Mask.lower()); if (!TheReg || !TheReg->hasRequiredFeatures(getSTI().getFeatureBits())) return MatchOperand_NoMatch; unsigned SYSmvalue = TheReg->Encoding & 0xFFF; Parser.Lex(); // Eat identifier token. Operands.push_back(ARMOperand::CreateMSRMask(SYSmvalue, S)); return MatchOperand_Success; } // Split spec_reg from flag, example: CPSR_sxf => "CPSR" and "sxf" size_t Start = 0, Next = Mask.find('_'); StringRef Flags = ""; std::string SpecReg = Mask.slice(Start, Next).lower(); if (Next != StringRef::npos) Flags = Mask.slice(Next+1, Mask.size()); // FlagsVal contains the complete mask: // 3-0: Mask // 4: Special Reg (cpsr, apsr => 0; spsr => 1) unsigned FlagsVal = 0; if (SpecReg == "apsr") { FlagsVal = StringSwitch(Flags) .Case("nzcvq", 0x8) // same as CPSR_f .Case("g", 0x4) // same as CPSR_s .Case("nzcvqg", 0xc) // same as CPSR_fs .Default(~0U); if (FlagsVal == ~0U) { if (!Flags.empty()) return MatchOperand_NoMatch; else FlagsVal = 8; // No flag } } else if (SpecReg == "cpsr" || SpecReg == "spsr") { // cpsr_all is an alias for cpsr_fc, as is plain cpsr. if (Flags == "all" || Flags == "") Flags = "fc"; for (int i = 0, e = Flags.size(); i != e; ++i) { unsigned Flag = StringSwitch(Flags.substr(i, 1)) .Case("c", 1) .Case("x", 2) .Case("s", 4) .Case("f", 8) .Default(~0U); // If some specific flag is already set, it means that some letter is // present more than once, this is not acceptable. if (Flag == ~0U || (FlagsVal & Flag)) return MatchOperand_NoMatch; FlagsVal |= Flag; } } else // No match for special register. return MatchOperand_NoMatch; // Special register without flags is NOT equivalent to "fc" flags. // NOTE: This is a divergence from gas' behavior. Uncommenting the following // two lines would enable gas compatibility at the expense of breaking // round-tripping. // // if (!FlagsVal) // FlagsVal = 0x9; // Bit 4: Special Reg (cpsr, apsr => 0; spsr => 1) if (SpecReg == "spsr") FlagsVal |= 16; Parser.Lex(); // Eat identifier token. Operands.push_back(ARMOperand::CreateMSRMask(FlagsVal, S)); return MatchOperand_Success; } /// parseBankedRegOperand - Try to parse a banked register (e.g. "lr_irq") for /// use in the MRS/MSR instructions added to support virtualization. OperandMatchResultTy ARMAsmParser::parseBankedRegOperand(OperandVector &Operands) { MCAsmParser &Parser = getParser(); SMLoc S = Parser.getTok().getLoc(); const AsmToken &Tok = Parser.getTok(); if (!Tok.is(AsmToken::Identifier)) return MatchOperand_NoMatch; StringRef RegName = Tok.getString(); auto TheReg = ARMBankedReg::lookupBankedRegByName(RegName.lower()); if (!TheReg) return MatchOperand_NoMatch; unsigned Encoding = TheReg->Encoding; Parser.Lex(); // Eat identifier token. Operands.push_back(ARMOperand::CreateBankedReg(Encoding, S)); return MatchOperand_Success; } OperandMatchResultTy ARMAsmParser::parsePKHImm(OperandVector &Operands, StringRef Op, int Low, int High) { MCAsmParser &Parser = getParser(); const AsmToken &Tok = Parser.getTok(); if (Tok.isNot(AsmToken::Identifier)) { Error(Parser.getTok().getLoc(), Op + " operand expected."); return MatchOperand_ParseFail; } StringRef ShiftName = Tok.getString(); std::string LowerOp = Op.lower(); std::string UpperOp = Op.upper(); if (ShiftName != LowerOp && ShiftName != UpperOp) { Error(Parser.getTok().getLoc(), Op + " operand expected."); return MatchOperand_ParseFail; } Parser.Lex(); // Eat shift type token. // There must be a '#' and a shift amount. if (Parser.getTok().isNot(AsmToken::Hash) && Parser.getTok().isNot(AsmToken::Dollar)) { Error(Parser.getTok().getLoc(), "'#' expected"); return MatchOperand_ParseFail; } Parser.Lex(); // Eat hash token. const MCExpr *ShiftAmount; SMLoc Loc = Parser.getTok().getLoc(); SMLoc EndLoc; if (getParser().parseExpression(ShiftAmount, EndLoc)) { Error(Loc, "illegal expression"); return MatchOperand_ParseFail; } const MCConstantExpr *CE = dyn_cast(ShiftAmount); if (!CE) { Error(Loc, "constant expression expected"); return MatchOperand_ParseFail; } int Val = CE->getValue(); if (Val < Low || Val > High) { Error(Loc, "immediate value out of range"); return MatchOperand_ParseFail; } Operands.push_back(ARMOperand::CreateImm(CE, Loc, EndLoc)); return MatchOperand_Success; } OperandMatchResultTy ARMAsmParser::parseSetEndImm(OperandVector &Operands) { MCAsmParser &Parser = getParser(); const AsmToken &Tok = Parser.getTok(); SMLoc S = Tok.getLoc(); if (Tok.isNot(AsmToken::Identifier)) { Error(S, "'be' or 'le' operand expected"); return MatchOperand_ParseFail; } int Val = StringSwitch(Tok.getString().lower()) .Case("be", 1) .Case("le", 0) .Default(-1); Parser.Lex(); // Eat the token. if (Val == -1) { Error(S, "'be' or 'le' operand expected"); return MatchOperand_ParseFail; } Operands.push_back(ARMOperand::CreateImm(MCConstantExpr::create(Val, getContext()), S, Tok.getEndLoc())); return MatchOperand_Success; } /// parseShifterImm - Parse the shifter immediate operand for SSAT/USAT /// instructions. Legal values are: /// lsl #n 'n' in [0,31] /// asr #n 'n' in [1,32] /// n == 32 encoded as n == 0. OperandMatchResultTy ARMAsmParser::parseShifterImm(OperandVector &Operands) { MCAsmParser &Parser = getParser(); const AsmToken &Tok = Parser.getTok(); SMLoc S = Tok.getLoc(); if (Tok.isNot(AsmToken::Identifier)) { Error(S, "shift operator 'asr' or 'lsl' expected"); return MatchOperand_ParseFail; } StringRef ShiftName = Tok.getString(); bool isASR; if (ShiftName == "lsl" || ShiftName == "LSL") isASR = false; else if (ShiftName == "asr" || ShiftName == "ASR") isASR = true; else { Error(S, "shift operator 'asr' or 'lsl' expected"); return MatchOperand_ParseFail; } Parser.Lex(); // Eat the operator. // A '#' and a shift amount. if (Parser.getTok().isNot(AsmToken::Hash) && Parser.getTok().isNot(AsmToken::Dollar)) { Error(Parser.getTok().getLoc(), "'#' expected"); return MatchOperand_ParseFail; } Parser.Lex(); // Eat hash token. SMLoc ExLoc = Parser.getTok().getLoc(); const MCExpr *ShiftAmount; SMLoc EndLoc; if (getParser().parseExpression(ShiftAmount, EndLoc)) { Error(ExLoc, "malformed shift expression"); return MatchOperand_ParseFail; } const MCConstantExpr *CE = dyn_cast(ShiftAmount); if (!CE) { Error(ExLoc, "shift amount must be an immediate"); return MatchOperand_ParseFail; } int64_t Val = CE->getValue(); if (isASR) { // Shift amount must be in [1,32] if (Val < 1 || Val > 32) { Error(ExLoc, "'asr' shift amount must be in range [1,32]"); return MatchOperand_ParseFail; } // asr #32 encoded as asr #0, but is not allowed in Thumb2 mode. if (isThumb() && Val == 32) { Error(ExLoc, "'asr #32' shift amount not allowed in Thumb mode"); return MatchOperand_ParseFail; } if (Val == 32) Val = 0; } else { // Shift amount must be in [1,32] if (Val < 0 || Val > 31) { Error(ExLoc, "'lsr' shift amount must be in range [0,31]"); return MatchOperand_ParseFail; } } Operands.push_back(ARMOperand::CreateShifterImm(isASR, Val, S, EndLoc)); return MatchOperand_Success; } /// parseRotImm - Parse the shifter immediate operand for SXTB/UXTB family /// of instructions. Legal values are: /// ror #n 'n' in {0, 8, 16, 24} OperandMatchResultTy ARMAsmParser::parseRotImm(OperandVector &Operands) { MCAsmParser &Parser = getParser(); const AsmToken &Tok = Parser.getTok(); SMLoc S = Tok.getLoc(); if (Tok.isNot(AsmToken::Identifier)) return MatchOperand_NoMatch; StringRef ShiftName = Tok.getString(); if (ShiftName != "ror" && ShiftName != "ROR") return MatchOperand_NoMatch; Parser.Lex(); // Eat the operator. // A '#' and a rotate amount. if (Parser.getTok().isNot(AsmToken::Hash) && Parser.getTok().isNot(AsmToken::Dollar)) { Error(Parser.getTok().getLoc(), "'#' expected"); return MatchOperand_ParseFail; } Parser.Lex(); // Eat hash token. SMLoc ExLoc = Parser.getTok().getLoc(); const MCExpr *ShiftAmount; SMLoc EndLoc; if (getParser().parseExpression(ShiftAmount, EndLoc)) { Error(ExLoc, "malformed rotate expression"); return MatchOperand_ParseFail; } const MCConstantExpr *CE = dyn_cast(ShiftAmount); if (!CE) { Error(ExLoc, "rotate amount must be an immediate"); return MatchOperand_ParseFail; } int64_t Val = CE->getValue(); // Shift amount must be in {0, 8, 16, 24} (0 is undocumented extension) // normally, zero is represented in asm by omitting the rotate operand // entirely. if (Val != 8 && Val != 16 && Val != 24 && Val != 0) { Error(ExLoc, "'ror' rotate amount must be 8, 16, or 24"); return MatchOperand_ParseFail; } Operands.push_back(ARMOperand::CreateRotImm(Val, S, EndLoc)); return MatchOperand_Success; } OperandMatchResultTy ARMAsmParser::parseModImm(OperandVector &Operands) { MCAsmParser &Parser = getParser(); MCAsmLexer &Lexer = getLexer(); int64_t Imm1, Imm2; SMLoc S = Parser.getTok().getLoc(); // 1) A mod_imm operand can appear in the place of a register name: // add r0, #mod_imm // add r0, r0, #mod_imm // to correctly handle the latter, we bail out as soon as we see an // identifier. // // 2) Similarly, we do not want to parse into complex operands: // mov r0, #mod_imm // mov r0, :lower16:(_foo) if (Parser.getTok().is(AsmToken::Identifier) || Parser.getTok().is(AsmToken::Colon)) return MatchOperand_NoMatch; // Hash (dollar) is optional as per the ARMARM if (Parser.getTok().is(AsmToken::Hash) || Parser.getTok().is(AsmToken::Dollar)) { // Avoid parsing into complex operands (#:) if (Lexer.peekTok().is(AsmToken::Colon)) return MatchOperand_NoMatch; // Eat the hash (dollar) Parser.Lex(); } SMLoc Sx1, Ex1; Sx1 = Parser.getTok().getLoc(); const MCExpr *Imm1Exp; if (getParser().parseExpression(Imm1Exp, Ex1)) { Error(Sx1, "malformed expression"); return MatchOperand_ParseFail; } const MCConstantExpr *CE = dyn_cast(Imm1Exp); if (CE) { // Immediate must fit within 32-bits Imm1 = CE->getValue(); int Enc = ARM_AM::getSOImmVal(Imm1); if (Enc != -1 && Parser.getTok().is(AsmToken::EndOfStatement)) { // We have a match! Operands.push_back(ARMOperand::CreateModImm((Enc & 0xFF), (Enc & 0xF00) >> 7, Sx1, Ex1)); return MatchOperand_Success; } // We have parsed an immediate which is not for us, fallback to a plain // immediate. This can happen for instruction aliases. For an example, // ARMInstrInfo.td defines the alias [mov <-> mvn] which can transform // a mov (mvn) with a mod_imm_neg/mod_imm_not operand into the opposite // instruction with a mod_imm operand. The alias is defined such that the // parser method is shared, that's why we have to do this here. if (Parser.getTok().is(AsmToken::EndOfStatement)) { Operands.push_back(ARMOperand::CreateImm(Imm1Exp, Sx1, Ex1)); return MatchOperand_Success; } } else { // Operands like #(l1 - l2) can only be evaluated at a later stage (via an // MCFixup). Fallback to a plain immediate. Operands.push_back(ARMOperand::CreateImm(Imm1Exp, Sx1, Ex1)); return MatchOperand_Success; } // From this point onward, we expect the input to be a (#bits, #rot) pair if (Parser.getTok().isNot(AsmToken::Comma)) { Error(Sx1, "expected modified immediate operand: #[0, 255], #even[0-30]"); return MatchOperand_ParseFail; } if (Imm1 & ~0xFF) { Error(Sx1, "immediate operand must a number in the range [0, 255]"); return MatchOperand_ParseFail; } // Eat the comma Parser.Lex(); // Repeat for #rot SMLoc Sx2, Ex2; Sx2 = Parser.getTok().getLoc(); // Eat the optional hash (dollar) if (Parser.getTok().is(AsmToken::Hash) || Parser.getTok().is(AsmToken::Dollar)) Parser.Lex(); const MCExpr *Imm2Exp; if (getParser().parseExpression(Imm2Exp, Ex2)) { Error(Sx2, "malformed expression"); return MatchOperand_ParseFail; } CE = dyn_cast(Imm2Exp); if (CE) { Imm2 = CE->getValue(); if (!(Imm2 & ~0x1E)) { // We have a match! Operands.push_back(ARMOperand::CreateModImm(Imm1, Imm2, S, Ex2)); return MatchOperand_Success; } Error(Sx2, "immediate operand must an even number in the range [0, 30]"); return MatchOperand_ParseFail; } else { Error(Sx2, "constant expression expected"); return MatchOperand_ParseFail; } } OperandMatchResultTy ARMAsmParser::parseBitfield(OperandVector &Operands) { MCAsmParser &Parser = getParser(); SMLoc S = Parser.getTok().getLoc(); // The bitfield descriptor is really two operands, the LSB and the width. if (Parser.getTok().isNot(AsmToken::Hash) && Parser.getTok().isNot(AsmToken::Dollar)) { Error(Parser.getTok().getLoc(), "'#' expected"); return MatchOperand_ParseFail; } Parser.Lex(); // Eat hash token. const MCExpr *LSBExpr; SMLoc E = Parser.getTok().getLoc(); if (getParser().parseExpression(LSBExpr)) { Error(E, "malformed immediate expression"); return MatchOperand_ParseFail; } const MCConstantExpr *CE = dyn_cast(LSBExpr); if (!CE) { Error(E, "'lsb' operand must be an immediate"); return MatchOperand_ParseFail; } int64_t LSB = CE->getValue(); // The LSB must be in the range [0,31] if (LSB < 0 || LSB > 31) { Error(E, "'lsb' operand must be in the range [0,31]"); return MatchOperand_ParseFail; } E = Parser.getTok().getLoc(); // Expect another immediate operand. if (Parser.getTok().isNot(AsmToken::Comma)) { Error(Parser.getTok().getLoc(), "too few operands"); return MatchOperand_ParseFail; } Parser.Lex(); // Eat hash token. if (Parser.getTok().isNot(AsmToken::Hash) && Parser.getTok().isNot(AsmToken::Dollar)) { Error(Parser.getTok().getLoc(), "'#' expected"); return MatchOperand_ParseFail; } Parser.Lex(); // Eat hash token. const MCExpr *WidthExpr; SMLoc EndLoc; if (getParser().parseExpression(WidthExpr, EndLoc)) { Error(E, "malformed immediate expression"); return MatchOperand_ParseFail; } CE = dyn_cast(WidthExpr); if (!CE) { Error(E, "'width' operand must be an immediate"); return MatchOperand_ParseFail; } int64_t Width = CE->getValue(); // The LSB must be in the range [1,32-lsb] if (Width < 1 || Width > 32 - LSB) { Error(E, "'width' operand must be in the range [1,32-lsb]"); return MatchOperand_ParseFail; } Operands.push_back(ARMOperand::CreateBitfield(LSB, Width, S, EndLoc)); return MatchOperand_Success; } OperandMatchResultTy ARMAsmParser::parsePostIdxReg(OperandVector &Operands) { // Check for a post-index addressing register operand. Specifically: // postidx_reg := '+' register {, shift} // | '-' register {, shift} // | register {, shift} // This method must return MatchOperand_NoMatch without consuming any tokens // in the case where there is no match, as other alternatives take other // parse methods. MCAsmParser &Parser = getParser(); AsmToken Tok = Parser.getTok(); SMLoc S = Tok.getLoc(); bool haveEaten = false; bool isAdd = true; if (Tok.is(AsmToken::Plus)) { Parser.Lex(); // Eat the '+' token. haveEaten = true; } else if (Tok.is(AsmToken::Minus)) { Parser.Lex(); // Eat the '-' token. isAdd = false; haveEaten = true; } SMLoc E = Parser.getTok().getEndLoc(); int Reg = tryParseRegister(); if (Reg == -1) { if (!haveEaten) return MatchOperand_NoMatch; Error(Parser.getTok().getLoc(), "register expected"); return MatchOperand_ParseFail; } ARM_AM::ShiftOpc ShiftTy = ARM_AM::no_shift; unsigned ShiftImm = 0; if (Parser.getTok().is(AsmToken::Comma)) { Parser.Lex(); // Eat the ','. if (parseMemRegOffsetShift(ShiftTy, ShiftImm)) return MatchOperand_ParseFail; // FIXME: Only approximates end...may include intervening whitespace. E = Parser.getTok().getLoc(); } Operands.push_back(ARMOperand::CreatePostIdxReg(Reg, isAdd, ShiftTy, ShiftImm, S, E)); return MatchOperand_Success; } OperandMatchResultTy ARMAsmParser::parseAM3Offset(OperandVector &Operands) { // Check for a post-index addressing register operand. Specifically: // am3offset := '+' register // | '-' register // | register // | # imm // | # + imm // | # - imm // This method must return MatchOperand_NoMatch without consuming any tokens // in the case where there is no match, as other alternatives take other // parse methods. MCAsmParser &Parser = getParser(); AsmToken Tok = Parser.getTok(); SMLoc S = Tok.getLoc(); // Do immediates first, as we always parse those if we have a '#'. if (Parser.getTok().is(AsmToken::Hash) || Parser.getTok().is(AsmToken::Dollar)) { Parser.Lex(); // Eat '#' or '$'. // Explicitly look for a '-', as we need to encode negative zero // differently. bool isNegative = Parser.getTok().is(AsmToken::Minus); const MCExpr *Offset; SMLoc E; if (getParser().parseExpression(Offset, E)) return MatchOperand_ParseFail; const MCConstantExpr *CE = dyn_cast(Offset); if (!CE) { Error(S, "constant expression expected"); return MatchOperand_ParseFail; } // Negative zero is encoded as the flag value // std::numeric_limits::min(). int32_t Val = CE->getValue(); if (isNegative && Val == 0) Val = std::numeric_limits::min(); Operands.push_back( ARMOperand::CreateImm(MCConstantExpr::create(Val, getContext()), S, E)); return MatchOperand_Success; } bool haveEaten = false; bool isAdd = true; if (Tok.is(AsmToken::Plus)) { Parser.Lex(); // Eat the '+' token. haveEaten = true; } else if (Tok.is(AsmToken::Minus)) { Parser.Lex(); // Eat the '-' token. isAdd = false; haveEaten = true; } Tok = Parser.getTok(); int Reg = tryParseRegister(); if (Reg == -1) { if (!haveEaten) return MatchOperand_NoMatch; Error(Tok.getLoc(), "register expected"); return MatchOperand_ParseFail; } Operands.push_back(ARMOperand::CreatePostIdxReg(Reg, isAdd, ARM_AM::no_shift, 0, S, Tok.getEndLoc())); return MatchOperand_Success; } /// Convert parsed operands to MCInst. Needed here because this instruction /// only has two register operands, but multiplication is commutative so /// assemblers should accept both "mul rD, rN, rD" and "mul rD, rD, rN". void ARMAsmParser::cvtThumbMultiply(MCInst &Inst, const OperandVector &Operands) { ((ARMOperand &)*Operands[3]).addRegOperands(Inst, 1); ((ARMOperand &)*Operands[1]).addCCOutOperands(Inst, 1); // If we have a three-operand form, make sure to set Rn to be the operand // that isn't the same as Rd. unsigned RegOp = 4; if (Operands.size() == 6 && ((ARMOperand &)*Operands[4]).getReg() == ((ARMOperand &)*Operands[3]).getReg()) RegOp = 5; ((ARMOperand &)*Operands[RegOp]).addRegOperands(Inst, 1); Inst.addOperand(Inst.getOperand(0)); ((ARMOperand &)*Operands[2]).addCondCodeOperands(Inst, 2); } void ARMAsmParser::cvtThumbBranches(MCInst &Inst, const OperandVector &Operands) { int CondOp = -1, ImmOp = -1; switch(Inst.getOpcode()) { case ARM::tB: case ARM::tBcc: CondOp = 1; ImmOp = 2; break; case ARM::t2B: case ARM::t2Bcc: CondOp = 1; ImmOp = 3; break; default: llvm_unreachable("Unexpected instruction in cvtThumbBranches"); } // first decide whether or not the branch should be conditional // by looking at it's location relative to an IT block if(inITBlock()) { // inside an IT block we cannot have any conditional branches. any // such instructions needs to be converted to unconditional form switch(Inst.getOpcode()) { case ARM::tBcc: Inst.setOpcode(ARM::tB); break; case ARM::t2Bcc: Inst.setOpcode(ARM::t2B); break; } } else { // outside IT blocks we can only have unconditional branches with AL // condition code or conditional branches with non-AL condition code unsigned Cond = static_cast(*Operands[CondOp]).getCondCode(); switch(Inst.getOpcode()) { case ARM::tB: case ARM::tBcc: Inst.setOpcode(Cond == ARMCC::AL ? ARM::tB : ARM::tBcc); break; case ARM::t2B: case ARM::t2Bcc: Inst.setOpcode(Cond == ARMCC::AL ? ARM::t2B : ARM::t2Bcc); break; } } // now decide on encoding size based on branch target range switch(Inst.getOpcode()) { // classify tB as either t2B or t1B based on range of immediate operand case ARM::tB: { ARMOperand &op = static_cast(*Operands[ImmOp]); if (!op.isSignedOffset<11, 1>() && isThumb() && hasV8MBaseline()) Inst.setOpcode(ARM::t2B); break; } // classify tBcc as either t2Bcc or t1Bcc based on range of immediate operand case ARM::tBcc: { ARMOperand &op = static_cast(*Operands[ImmOp]); if (!op.isSignedOffset<8, 1>() && isThumb() && hasV8MBaseline()) Inst.setOpcode(ARM::t2Bcc); break; } } ((ARMOperand &)*Operands[ImmOp]).addImmOperands(Inst, 1); ((ARMOperand &)*Operands[CondOp]).addCondCodeOperands(Inst, 2); } void ARMAsmParser::cvtMVEVMOVQtoDReg( MCInst &Inst, const OperandVector &Operands) { // mnemonic, condition code, Rt, Rt2, Qd, idx, Qd again, idx2 assert(Operands.size() == 8); ((ARMOperand &)*Operands[2]).addRegOperands(Inst, 1); // Rt ((ARMOperand &)*Operands[3]).addRegOperands(Inst, 1); // Rt2 ((ARMOperand &)*Operands[4]).addRegOperands(Inst, 1); // Qd ((ARMOperand &)*Operands[5]).addMVEPairVectorIndexOperands(Inst, 1); // idx // skip second copy of Qd in Operands[6] ((ARMOperand &)*Operands[7]).addMVEPairVectorIndexOperands(Inst, 1); // idx2 ((ARMOperand &)*Operands[1]).addCondCodeOperands(Inst, 2); // condition code } /// Parse an ARM memory expression, return false if successful else return true /// or an error. The first token must be a '[' when called. bool ARMAsmParser::parseMemory(OperandVector &Operands) { MCAsmParser &Parser = getParser(); SMLoc S, E; if (Parser.getTok().isNot(AsmToken::LBrac)) return TokError("Token is not a Left Bracket"); S = Parser.getTok().getLoc(); Parser.Lex(); // Eat left bracket token. const AsmToken &BaseRegTok = Parser.getTok(); int BaseRegNum = tryParseRegister(); if (BaseRegNum == -1) return Error(BaseRegTok.getLoc(), "register expected"); // The next token must either be a comma, a colon or a closing bracket. const AsmToken &Tok = Parser.getTok(); if (!Tok.is(AsmToken::Colon) && !Tok.is(AsmToken::Comma) && !Tok.is(AsmToken::RBrac)) return Error(Tok.getLoc(), "malformed memory operand"); if (Tok.is(AsmToken::RBrac)) { E = Tok.getEndLoc(); Parser.Lex(); // Eat right bracket token. Operands.push_back(ARMOperand::CreateMem(BaseRegNum, nullptr, 0, ARM_AM::no_shift, 0, 0, false, S, E)); // If there's a pre-indexing writeback marker, '!', just add it as a token // operand. It's rather odd, but syntactically valid. if (Parser.getTok().is(AsmToken::Exclaim)) { Operands.push_back(ARMOperand::CreateToken("!",Parser.getTok().getLoc())); Parser.Lex(); // Eat the '!'. } return false; } assert((Tok.is(AsmToken::Colon) || Tok.is(AsmToken::Comma)) && "Lost colon or comma in memory operand?!"); if (Tok.is(AsmToken::Comma)) { Parser.Lex(); // Eat the comma. } // If we have a ':', it's an alignment specifier. if (Parser.getTok().is(AsmToken::Colon)) { Parser.Lex(); // Eat the ':'. E = Parser.getTok().getLoc(); SMLoc AlignmentLoc = Tok.getLoc(); const MCExpr *Expr; if (getParser().parseExpression(Expr)) return true; // The expression has to be a constant. Memory references with relocations // don't come through here, as they use the