Index: head/sys/dts/arm/overlays/sun8i-h3-sid.dtso
===================================================================
--- head/sys/dts/arm/overlays/sun8i-h3-sid.dtso	(revision 351451)
+++ head/sys/dts/arm/overlays/sun8i-h3-sid.dtso	(revision 351452)
@@ -1,14 +1,19 @@
 /dts-v1/;
 /plugin/;
 
 / {
 	compatible = "allwinner,sun8i-h3";
 };
 
 &{/soc} {
 	sid: eeprom@1c14000 {
 		compatible = "allwinner,sun8i-h3-sid";
 		reg = <0x1c14000 0x400>;
 		status = "okay";
+
+		/* Data cells */
+		ths_calib: calib@234 {
+			reg = <0x234 0x2>;
+		};
 	};
 };
Index: head/sys/dts/arm/overlays/sun8i-h3-ths.dtso
===================================================================
--- head/sys/dts/arm/overlays/sun8i-h3-ths.dtso	(nonexistent)
+++ head/sys/dts/arm/overlays/sun8i-h3-ths.dtso	(revision 351452)
@@ -0,0 +1,27 @@
+/dts-v1/;
+/plugin/;
+
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/clock/sun8i-h3-ccu.h>
+#include <dt-bindings/reset/sun8i-h3-ccu.h>
+
+/ {
+	compatible = "allwinner,sun8i-h3";
+};
+
+&{/soc} {
+	ths: thermal_sensor@1c25000 {
+		 compatible = "allwinner,sun8i-h3-ths";
+		 reg = <0x01c25000 0x100>;
+		 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
+		 clocks = <&ccu CLK_BUS_THS>, <&ccu CLK_THS>;
+		 clock-names = "apb", "ths";
+		 resets = <&ccu RST_BUS_THS>;
+		 reset-names = "apb";
+		 #thermal-sensor-cells = <0>;
+		 status = "okay";
+
+		 nvmem-cells = <&ths_calib>;
+		 nvmem-cell-names = "ths-calib";
+	 };
+};

Property changes on: head/sys/dts/arm/overlays/sun8i-h3-ths.dtso
___________________________________________________________________
Added: fbsd:nokeywords
## -0,0 +1 ##
+yes
\ No newline at end of property
Index: head/sys/modules/dtb/allwinner/Makefile
===================================================================
--- head/sys/modules/dtb/allwinner/Makefile	(revision 351451)
+++ head/sys/modules/dtb/allwinner/Makefile	(revision 351452)
@@ -1,65 +1,66 @@
 # $FreeBSD$
 # All the dts files for allwinner systems we support.
 
 .if ${MACHINE_ARCH} == "armv7"
 DTS=	\
 	sun4i-a10-cubieboard.dts \
 	sun4i-a10-olinuxino-lime.dts \
 	sun6i-a31s-sinovoip-bpi-m2.dts \
 	sun5i-a13-olinuxino.dts \
 	sun5i-r8-chip.dts \
 	sun7i-a20-bananapi.dts \
 	sun7i-a20-cubieboard2.dts \
 	sun7i-a20-lamobo-r1.dts \
 	sun7i-a20-olimex-som-evb.dts \
 	sun7i-a20-pcduino3.dts \
 	sun8i-a83t-bananapi-m3.dts \
 	sun8i-h2-plus-orangepi-r1.dts \
 	sun8i-h2-plus-orangepi-zero.dts \
 	sun8i-h3-nanopi-m1.dts \
 	sun8i-h3-nanopi-m1-plus.dts \
 	sun8i-h3-nanopi-neo.dts \
 	sun8i-h3-orangepi-one.dts \
 	sun8i-h3-orangepi-pc.dts \
 	sun8i-h3-orangepi-plus2e.dts
 
 DTSO=	sun8i-a83t-sid.dtso \
 	sun8i-h3-i2c0.dtso \
-	sun8i-h3-sid.dtso
+	sun8i-h3-sid.dtso \
+	sun8i-h3-ths.dtso
 
 LINKS= \
 	${DTBDIR}/sun4i-a10-cubieboard.dtb ${DTBDIR}/cubieboard.dtb \
 	${DTBDIR}/sun4i-a10-olinuxino-lime.dtb ${DTBDIR}/olinuxino-lime.dtb \
 	${DTBDIR}/sun6i-a31s-sinovoip-bpi-m2.dtb ${DTBDIR}/bananapim2.dtb \
 	${DTBDIR}/sun7i-a20-bananapi.dtb ${DTBDIR}/bananapi.dtb \
 	${DTBDIR}/sun7i-a20-cubieboard2.dtb ${DTBDIR}/cubieboard2.dtb \
 	${DTBDIR}/sun7i-a20-olimex-som-evb.dtb ${DTBDIR}/olimex-a20-som-evb.dtb \
 	${DTBDIR}/sun7i-a20-pcduino3.dtb ${DTBDIR}/pcduino3.dtb \
 	${DTBDIR}/sun8i-a83t-bananapi-m3.dtb ${DTBDIR}/sinovoip-bpi-m3.dtb \
 	${DTBDIR}/sun8i-a83t-bananapi-m3.dtb ${DTBDIR}/sun8i-a83t-sinovoip-bpi-m3.dtb
 .elif ${MACHINE_ARCH} == "aarch64"
 DTS=	\
 	allwinner/sun50i-a64-nanopi-a64.dts \
 	allwinner/sun50i-a64-olinuxino.dts \
 	allwinner/sun50i-a64-pine64-lts.dts \
 	allwinner/sun50i-a64-pine64-plus.dts \
 	allwinner/sun50i-a64-pine64.dts \
 	allwinner/sun50i-a64-pinebook.dts \
 	allwinner/sun50i-a64-sopine-baseboard.dts \
 	allwinner/sun50i-h5-orangepi-pc2.dts \
 	allwinner/sun50i-h5-nanopi-neo2.dts
 
 DTSO=	sun50i-a64-opp.dtso \
 	sun50i-a64-pwm.dtso \
 	sun50i-a64-rpwm.dtso \
 	sun50i-a64-sid.dtso \
 	sun50i-a64-ths.dtso \
 	sun50i-a64-timer.dtso \
 	sun50i-h5-opp.dtso \
 	sun50i-h5-sid.dtso \
 	sun50i-h5-ths.dtso \
 	sun50i-h5-nanopi-neo2-opp.dtso
 
 .endif
 
 .include <bsd.dtb.mk>