Index: head/sys/dev/usb/net/if_aue.c =================================================================== --- head/sys/dev/usb/net/if_aue.c (revision 351249) +++ head/sys/dev/usb/net/if_aue.c (revision 351250) @@ -1,1068 +1,1074 @@ /*- * SPDX-License-Identifier: BSD-4-Clause * * Copyright (c) 1997, 1998, 1999, 2000 * Bill Paul . All rights reserved. * * Copyright (c) 2006 * Alfred Perlstein . All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * 3. All advertising materials mentioning features or use of this software * must display the following acknowledgement: * This product includes software developed by Bill Paul. * 4. Neither the name of the author nor the names of any co-contributors * may be used to endorse or promote products derived from this software * without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF * THE POSSIBILITY OF SUCH DAMAGE. */ #include __FBSDID("$FreeBSD$"); /* * ADMtek AN986 Pegasus and AN8511 Pegasus II USB to ethernet driver. * Datasheet is available from http://www.admtek.com.tw. * * Written by Bill Paul * Electrical Engineering Department * Columbia University, New York City * * SMP locking by Alfred Perlstein . * RED Inc. */ /* * The Pegasus chip uses four USB "endpoints" to provide 10/100 ethernet * support: the control endpoint for reading/writing registers, burst * read endpoint for packet reception, burst write for packet transmission * and one for "interrupts." The chip uses the same RX filter scheme * as the other ADMtek ethernet parts: one perfect filter entry for the * the station address and a 64-bit multicast hash table. The chip supports * both MII and HomePNA attachments. * * Since the maximum data transfer speed of USB is supposed to be 12Mbps, * you're never really going to get 100Mbps speeds from this device. I * think the idea is to allow the device to connect to 10 or 100Mbps * networks, not necessarily to provide 100Mbps performance. Also, since * the controller uses an external PHY chip, it's possible that board * designers might simply choose a 10Mbps PHY. * * Registers are accessed using uether_do_request(). Packet * transfers are done using usbd_transfer() and friends. */ #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include +#include +#include +#include + #include #include #include #include "usbdevs.h" #define USB_DEBUG_VAR aue_debug #include #include #include #include + +#include "miibus_if.h" #ifdef USB_DEBUG static int aue_debug = 0; static SYSCTL_NODE(_hw_usb, OID_AUTO, aue, CTLFLAG_RW, 0, "USB aue"); SYSCTL_INT(_hw_usb_aue, OID_AUTO, debug, CTLFLAG_RWTUN, &aue_debug, 0, "Debug level"); #endif /* * Various supported device vendors/products. */ static const STRUCT_USB_HOST_ID aue_devs[] = { #define AUE_DEV(v,p,i) { USB_VPI(USB_VENDOR_##v, USB_PRODUCT_##v##_##p, i) } AUE_DEV(3COM, 3C460B, AUE_FLAG_PII), AUE_DEV(ABOCOM, DSB650TX_PNA, 0), AUE_DEV(ABOCOM, UFE1000, AUE_FLAG_LSYS), AUE_DEV(ABOCOM, XX10, 0), AUE_DEV(ABOCOM, XX1, AUE_FLAG_PNA | AUE_FLAG_PII), AUE_DEV(ABOCOM, XX2, AUE_FLAG_PII), AUE_DEV(ABOCOM, XX4, AUE_FLAG_PNA), AUE_DEV(ABOCOM, XX5, AUE_FLAG_PNA), AUE_DEV(ABOCOM, XX6, AUE_FLAG_PII), AUE_DEV(ABOCOM, XX7, AUE_FLAG_PII), AUE_DEV(ABOCOM, XX8, AUE_FLAG_PII), AUE_DEV(ABOCOM, XX9, AUE_FLAG_PNA), AUE_DEV(ACCTON, SS1001, AUE_FLAG_PII), AUE_DEV(ACCTON, USB320_EC, 0), AUE_DEV(ADMTEK, PEGASUSII_2, AUE_FLAG_PII), AUE_DEV(ADMTEK, PEGASUSII_3, AUE_FLAG_PII), AUE_DEV(ADMTEK, PEGASUSII_4, AUE_FLAG_PII), AUE_DEV(ADMTEK, PEGASUSII, AUE_FLAG_PII), AUE_DEV(ADMTEK, PEGASUS, AUE_FLAG_PNA | AUE_FLAG_DUAL_PHY), AUE_DEV(AEI, FASTETHERNET, AUE_FLAG_PII), AUE_DEV(ALLIEDTELESYN, ATUSB100, AUE_FLAG_PII), AUE_DEV(ATEN, UC110T, AUE_FLAG_PII), AUE_DEV(BELKIN, USB2LAN, AUE_FLAG_PII), AUE_DEV(BILLIONTON, USB100, 0), AUE_DEV(BILLIONTON, USBE100, AUE_FLAG_PII), AUE_DEV(BILLIONTON, USBEL100, 0), AUE_DEV(BILLIONTON, USBLP100, AUE_FLAG_PNA), AUE_DEV(COREGA, FETHER_USB_TXS, AUE_FLAG_PII), AUE_DEV(COREGA, FETHER_USB_TX, 0), AUE_DEV(DLINK, DSB650TX1, AUE_FLAG_LSYS), AUE_DEV(DLINK, DSB650TX2, AUE_FLAG_LSYS | AUE_FLAG_PII), AUE_DEV(DLINK, DSB650TX3, AUE_FLAG_LSYS | AUE_FLAG_PII), AUE_DEV(DLINK, DSB650TX4, AUE_FLAG_LSYS | AUE_FLAG_PII), AUE_DEV(DLINK, DSB650TX_PNA, AUE_FLAG_PNA), AUE_DEV(DLINK, DSB650TX, AUE_FLAG_LSYS), AUE_DEV(DLINK, DSB650, AUE_FLAG_LSYS), AUE_DEV(ELCON, PLAN, AUE_FLAG_PNA | AUE_FLAG_PII), AUE_DEV(ELECOM, LDUSB20, AUE_FLAG_PII), AUE_DEV(ELECOM, LDUSBLTX, AUE_FLAG_PII), AUE_DEV(ELECOM, LDUSBTX0, 0), AUE_DEV(ELECOM, LDUSBTX1, AUE_FLAG_LSYS), AUE_DEV(ELECOM, LDUSBTX2, 0), AUE_DEV(ELECOM, LDUSBTX3, AUE_FLAG_LSYS), AUE_DEV(ELSA, USB2ETHERNET, 0), AUE_DEV(GIGABYTE, GNBR402W, 0), AUE_DEV(HAWKING, UF100, AUE_FLAG_PII), AUE_DEV(HP, HN210E, AUE_FLAG_PII), AUE_DEV(IODATA, USBETTXS, AUE_FLAG_PII), AUE_DEV(IODATA, USBETTX, 0), AUE_DEV(KINGSTON, KNU101TX, 0), AUE_DEV(LINKSYS, USB100H1, AUE_FLAG_LSYS | AUE_FLAG_PNA), AUE_DEV(LINKSYS, USB100TX, AUE_FLAG_LSYS), AUE_DEV(LINKSYS, USB10TA, AUE_FLAG_LSYS), AUE_DEV(LINKSYS, USB10TX1, AUE_FLAG_LSYS | AUE_FLAG_PII), AUE_DEV(LINKSYS, USB10TX2, AUE_FLAG_LSYS | AUE_FLAG_PII), AUE_DEV(LINKSYS, USB10T, AUE_FLAG_LSYS), AUE_DEV(MELCO, LUA2TX5, AUE_FLAG_PII), AUE_DEV(MELCO, LUATX1, 0), AUE_DEV(MELCO, LUATX5, 0), AUE_DEV(MICROSOFT, MN110, AUE_FLAG_PII), AUE_DEV(NETGEAR, FA101, AUE_FLAG_PII), AUE_DEV(SIEMENS, SPEEDSTREAM, AUE_FLAG_PII), AUE_DEV(SIIG2, USBTOETHER, AUE_FLAG_PII), AUE_DEV(SMARTBRIDGES, SMARTNIC, AUE_FLAG_PII), AUE_DEV(SMC, 2202USB, 0), AUE_DEV(SMC, 2206USB, AUE_FLAG_PII), AUE_DEV(SOHOWARE, NUB100, 0), AUE_DEV(SOHOWARE, NUB110, AUE_FLAG_PII), #undef AUE_DEV }; /* prototypes */ static device_probe_t aue_probe; static device_attach_t aue_attach; static device_detach_t aue_detach; static miibus_readreg_t aue_miibus_readreg; static miibus_writereg_t aue_miibus_writereg; static miibus_statchg_t aue_miibus_statchg; static usb_callback_t aue_intr_callback; static usb_callback_t aue_bulk_read_callback; static usb_callback_t aue_bulk_write_callback; static uether_fn_t aue_attach_post; static uether_fn_t aue_init; static uether_fn_t aue_stop; static uether_fn_t aue_start; static uether_fn_t aue_tick; static uether_fn_t aue_setmulti; static uether_fn_t aue_setpromisc; static uint8_t aue_csr_read_1(struct aue_softc *, uint16_t); static uint16_t aue_csr_read_2(struct aue_softc *, uint16_t); static void aue_csr_write_1(struct aue_softc *, uint16_t, uint8_t); static void aue_csr_write_2(struct aue_softc *, uint16_t, uint16_t); static uint16_t aue_eeprom_getword(struct aue_softc *, int); static void aue_reset(struct aue_softc *); static void aue_reset_pegasus_II(struct aue_softc *); static int aue_ifmedia_upd(struct ifnet *); static void aue_ifmedia_sts(struct ifnet *, struct ifmediareq *); static const struct usb_config aue_config[AUE_N_TRANSFER] = { [AUE_BULK_DT_WR] = { .type = UE_BULK, .endpoint = UE_ADDR_ANY, .direction = UE_DIR_OUT, .bufsize = (MCLBYTES + 2), .flags = {.pipe_bof = 1,.force_short_xfer = 1,}, .callback = aue_bulk_write_callback, .timeout = 10000, /* 10 seconds */ }, [AUE_BULK_DT_RD] = { .type = UE_BULK, .endpoint = UE_ADDR_ANY, .direction = UE_DIR_IN, .bufsize = (MCLBYTES + 4 + ETHER_CRC_LEN), .flags = {.pipe_bof = 1,.short_xfer_ok = 1,}, .callback = aue_bulk_read_callback, }, [AUE_INTR_DT_RD] = { .type = UE_INTERRUPT, .endpoint = UE_ADDR_ANY, .direction = UE_DIR_IN, .flags = {.pipe_bof = 1,.short_xfer_ok = 1,}, .bufsize = 0, /* use wMaxPacketSize */ .callback = aue_intr_callback, }, }; static device_method_t aue_methods[] = { /* Device interface */ DEVMETHOD(device_probe, aue_probe), DEVMETHOD(device_attach, aue_attach), DEVMETHOD(device_detach, aue_detach), /* MII interface */ DEVMETHOD(miibus_readreg, aue_miibus_readreg), DEVMETHOD(miibus_writereg, aue_miibus_writereg), DEVMETHOD(miibus_statchg, aue_miibus_statchg), DEVMETHOD_END }; static driver_t aue_driver = { .name = "aue", .methods = aue_methods, .size = sizeof(struct aue_softc) }; static devclass_t aue_devclass; DRIVER_MODULE(aue, uhub, aue_driver, aue_devclass, NULL, 0); DRIVER_MODULE(miibus, aue, miibus_driver, miibus_devclass, 0, 0); MODULE_DEPEND(aue, uether, 1, 1, 1); MODULE_DEPEND(aue, usb, 1, 1, 1); MODULE_DEPEND(aue, ether, 1, 1, 1); MODULE_DEPEND(aue, miibus, 1, 1, 1); MODULE_VERSION(aue, 1); USB_PNP_HOST_INFO(aue_devs); static const struct usb_ether_methods aue_ue_methods = { .ue_attach_post = aue_attach_post, .ue_start = aue_start, .ue_init = aue_init, .ue_stop = aue_stop, .ue_tick = aue_tick, .ue_setmulti = aue_setmulti, .ue_setpromisc = aue_setpromisc, .ue_mii_upd = aue_ifmedia_upd, .ue_mii_sts = aue_ifmedia_sts, }; #define AUE_SETBIT(sc, reg, x) \ aue_csr_write_1(sc, reg, aue_csr_read_1(sc, reg) | (x)) #define AUE_CLRBIT(sc, reg, x) \ aue_csr_write_1(sc, reg, aue_csr_read_1(sc, reg) & ~(x)) static uint8_t aue_csr_read_1(struct aue_softc *sc, uint16_t reg) { struct usb_device_request req; usb_error_t err; uint8_t val; req.bmRequestType = UT_READ_VENDOR_DEVICE; req.bRequest = AUE_UR_READREG; USETW(req.wValue, 0); USETW(req.wIndex, reg); USETW(req.wLength, 1); err = uether_do_request(&sc->sc_ue, &req, &val, 1000); if (err) return (0); return (val); } static uint16_t aue_csr_read_2(struct aue_softc *sc, uint16_t reg) { struct usb_device_request req; usb_error_t err; uint16_t val; req.bmRequestType = UT_READ_VENDOR_DEVICE; req.bRequest = AUE_UR_READREG; USETW(req.wValue, 0); USETW(req.wIndex, reg); USETW(req.wLength, 2); err = uether_do_request(&sc->sc_ue, &req, &val, 1000); if (err) return (0); return (le16toh(val)); } static void aue_csr_write_1(struct aue_softc *sc, uint16_t reg, uint8_t val) { struct usb_device_request req; req.bmRequestType = UT_WRITE_VENDOR_DEVICE; req.bRequest = AUE_UR_WRITEREG; req.wValue[0] = val; req.wValue[1] = 0; USETW(req.wIndex, reg); USETW(req.wLength, 1); if (uether_do_request(&sc->sc_ue, &req, &val, 1000)) { /* error ignored */ } } static void aue_csr_write_2(struct aue_softc *sc, uint16_t reg, uint16_t val) { struct usb_device_request req; req.bmRequestType = UT_WRITE_VENDOR_DEVICE; req.bRequest = AUE_UR_WRITEREG; USETW(req.wValue, val); USETW(req.wIndex, reg); USETW(req.wLength, 2); val = htole16(val); if (uether_do_request(&sc->sc_ue, &req, &val, 1000)) { /* error ignored */ } } /* * Read a word of data stored in the EEPROM at address 'addr.' */ static uint16_t aue_eeprom_getword(struct aue_softc *sc, int addr) { int i; aue_csr_write_1(sc, AUE_EE_REG, addr); aue_csr_write_1(sc, AUE_EE_CTL, AUE_EECTL_READ); for (i = 0; i != AUE_TIMEOUT; i++) { if (aue_csr_read_1(sc, AUE_EE_CTL) & AUE_EECTL_DONE) break; if (uether_pause(&sc->sc_ue, hz / 100)) break; } if (i == AUE_TIMEOUT) device_printf(sc->sc_ue.ue_dev, "EEPROM read timed out\n"); return (aue_csr_read_2(sc, AUE_EE_DATA)); } /* * Read station address(offset 0) from the EEPROM. */ static void aue_read_mac(struct aue_softc *sc, uint8_t *eaddr) { int i, offset; uint16_t word; for (i = 0, offset = 0; i < ETHER_ADDR_LEN / 2; i++) { word = aue_eeprom_getword(sc, offset + i); eaddr[i * 2] = (uint8_t)word; eaddr[i * 2 + 1] = (uint8_t)(word >> 8); } } static int aue_miibus_readreg(device_t dev, int phy, int reg) { struct aue_softc *sc = device_get_softc(dev); int i, locked; uint16_t val = 0; locked = mtx_owned(&sc->sc_mtx); if (!locked) AUE_LOCK(sc); /* * The Am79C901 HomePNA PHY actually contains two transceivers: a 1Mbps * HomePNA PHY and a 10Mbps full/half duplex ethernet PHY with NWAY * autoneg. However in the ADMtek adapter, only the 1Mbps PHY is * actually connected to anything, so we ignore the 10Mbps one. It * happens to be configured for MII address 3, so we filter that out. */ if (sc->sc_flags & AUE_FLAG_DUAL_PHY) { if (phy == 3) goto done; #if 0 if (phy != 1) goto done; #endif } aue_csr_write_1(sc, AUE_PHY_ADDR, phy); aue_csr_write_1(sc, AUE_PHY_CTL, reg | AUE_PHYCTL_READ); for (i = 0; i != AUE_TIMEOUT; i++) { if (aue_csr_read_1(sc, AUE_PHY_CTL) & AUE_PHYCTL_DONE) break; if (uether_pause(&sc->sc_ue, hz / 100)) break; } if (i == AUE_TIMEOUT) device_printf(sc->sc_ue.ue_dev, "MII read timed out\n"); val = aue_csr_read_2(sc, AUE_PHY_DATA); done: if (!locked) AUE_UNLOCK(sc); return (val); } static int aue_miibus_writereg(device_t dev, int phy, int reg, int data) { struct aue_softc *sc = device_get_softc(dev); int i; int locked; if (phy == 3) return (0); locked = mtx_owned(&sc->sc_mtx); if (!locked) AUE_LOCK(sc); aue_csr_write_2(sc, AUE_PHY_DATA, data); aue_csr_write_1(sc, AUE_PHY_ADDR, phy); aue_csr_write_1(sc, AUE_PHY_CTL, reg | AUE_PHYCTL_WRITE); for (i = 0; i != AUE_TIMEOUT; i++) { if (aue_csr_read_1(sc, AUE_PHY_CTL) & AUE_PHYCTL_DONE) break; if (uether_pause(&sc->sc_ue, hz / 100)) break; } if (i == AUE_TIMEOUT) device_printf(sc->sc_ue.ue_dev, "MII write timed out\n"); if (!locked) AUE_UNLOCK(sc); return (0); } static void aue_miibus_statchg(device_t dev) { struct aue_softc *sc = device_get_softc(dev); struct mii_data *mii = GET_MII(sc); int locked; locked = mtx_owned(&sc->sc_mtx); if (!locked) AUE_LOCK(sc); AUE_CLRBIT(sc, AUE_CTL0, AUE_CTL0_RX_ENB | AUE_CTL0_TX_ENB); if (IFM_SUBTYPE(mii->mii_media_active) == IFM_100_TX) AUE_SETBIT(sc, AUE_CTL1, AUE_CTL1_SPEEDSEL); else AUE_CLRBIT(sc, AUE_CTL1, AUE_CTL1_SPEEDSEL); if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) AUE_SETBIT(sc, AUE_CTL1, AUE_CTL1_DUPLEX); else AUE_CLRBIT(sc, AUE_CTL1, AUE_CTL1_DUPLEX); AUE_SETBIT(sc, AUE_CTL0, AUE_CTL0_RX_ENB | AUE_CTL0_TX_ENB); /* * Set the LED modes on the LinkSys adapter. * This turns on the 'dual link LED' bin in the auxmode * register of the Broadcom PHY. */ if (sc->sc_flags & AUE_FLAG_LSYS) { uint16_t auxmode; auxmode = aue_miibus_readreg(dev, 0, 0x1b); aue_miibus_writereg(dev, 0, 0x1b, auxmode | 0x04); } if (!locked) AUE_UNLOCK(sc); } #define AUE_BITS 6 static void aue_setmulti(struct usb_ether *ue) { struct aue_softc *sc = uether_getsc(ue); struct ifnet *ifp = uether_getifp(ue); struct ifmultiaddr *ifma; uint32_t h = 0; uint32_t i; uint8_t hashtbl[8] = { 0, 0, 0, 0, 0, 0, 0, 0 }; AUE_LOCK_ASSERT(sc, MA_OWNED); if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { AUE_SETBIT(sc, AUE_CTL0, AUE_CTL0_ALLMULTI); return; } AUE_CLRBIT(sc, AUE_CTL0, AUE_CTL0_ALLMULTI); /* now program new ones */ if_maddr_rlock(ifp); CK_STAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { if (ifma->ifma_addr->sa_family != AF_LINK) continue; h = ether_crc32_le(LLADDR((struct sockaddr_dl *) ifma->ifma_addr), ETHER_ADDR_LEN) & ((1 << AUE_BITS) - 1); hashtbl[(h >> 3)] |= 1 << (h & 0x7); } if_maddr_runlock(ifp); /* write the hashtable */ for (i = 0; i != 8; i++) aue_csr_write_1(sc, AUE_MAR0 + i, hashtbl[i]); } static void aue_reset_pegasus_II(struct aue_softc *sc) { /* Magic constants taken from Linux driver. */ aue_csr_write_1(sc, AUE_REG_1D, 0); aue_csr_write_1(sc, AUE_REG_7B, 2); #if 0 if ((sc->sc_flags & HAS_HOME_PNA) && mii_mode) aue_csr_write_1(sc, AUE_REG_81, 6); else #endif aue_csr_write_1(sc, AUE_REG_81, 2); } static void aue_reset(struct aue_softc *sc) { int i; AUE_SETBIT(sc, AUE_CTL1, AUE_CTL1_RESETMAC); for (i = 0; i != AUE_TIMEOUT; i++) { if (!(aue_csr_read_1(sc, AUE_CTL1) & AUE_CTL1_RESETMAC)) break; if (uether_pause(&sc->sc_ue, hz / 100)) break; } if (i == AUE_TIMEOUT) device_printf(sc->sc_ue.ue_dev, "reset failed\n"); /* * The PHY(s) attached to the Pegasus chip may be held * in reset until we flip on the GPIO outputs. Make sure * to set the GPIO pins high so that the PHY(s) will * be enabled. * * NOTE: We used to force all of the GPIO pins low first and then * enable the ones we want. This has been changed to better * match the ADMtek's reference design to avoid setting the * power-down configuration line of the PHY at the same time * it is reset. */ aue_csr_write_1(sc, AUE_GPIO0, AUE_GPIO_SEL0|AUE_GPIO_SEL1); aue_csr_write_1(sc, AUE_GPIO0, AUE_GPIO_SEL0|AUE_GPIO_SEL1|AUE_GPIO_OUT0); if (sc->sc_flags & AUE_FLAG_LSYS) { /* Grrr. LinkSys has to be different from everyone else. */ aue_csr_write_1(sc, AUE_GPIO0, AUE_GPIO_SEL0|AUE_GPIO_SEL1); aue_csr_write_1(sc, AUE_GPIO0, AUE_GPIO_SEL0|AUE_GPIO_SEL1|AUE_GPIO_OUT0); } if (sc->sc_flags & AUE_FLAG_PII) aue_reset_pegasus_II(sc); /* Wait a little while for the chip to get its brains in order: */ uether_pause(&sc->sc_ue, hz / 100); } static void aue_attach_post(struct usb_ether *ue) { struct aue_softc *sc = uether_getsc(ue); /* reset the adapter */ aue_reset(sc); /* get station address from the EEPROM */ aue_read_mac(sc, ue->ue_eaddr); } /* * Probe for a Pegasus chip. */ static int aue_probe(device_t dev) { struct usb_attach_arg *uaa = device_get_ivars(dev); if (uaa->usb_mode != USB_MODE_HOST) return (ENXIO); if (uaa->info.bConfigIndex != AUE_CONFIG_INDEX) return (ENXIO); if (uaa->info.bIfaceIndex != AUE_IFACE_IDX) return (ENXIO); /* * Belkin USB Bluetooth dongles of the F8T012xx1 model series conflict * with older Belkin USB2LAN adapters. Skip if_aue if we detect one of * the devices that look like Bluetooth adapters. */ if (uaa->info.idVendor == USB_VENDOR_BELKIN && uaa->info.idProduct == USB_PRODUCT_BELKIN_F8T012 && uaa->info.bcdDevice == 0x0413) return (ENXIO); return (usbd_lookup_id_by_uaa(aue_devs, sizeof(aue_devs), uaa)); } /* * Attach the interface. Allocate softc structures, do ifmedia * setup and ethernet/BPF attach. */ static int aue_attach(device_t dev) { struct usb_attach_arg *uaa = device_get_ivars(dev); struct aue_softc *sc = device_get_softc(dev); struct usb_ether *ue = &sc->sc_ue; uint8_t iface_index; int error; sc->sc_flags = USB_GET_DRIVER_INFO(uaa); if (uaa->info.bcdDevice >= 0x0201) { /* XXX currently undocumented */ sc->sc_flags |= AUE_FLAG_VER_2; } device_set_usb_desc(dev); mtx_init(&sc->sc_mtx, device_get_nameunit(dev), NULL, MTX_DEF); iface_index = AUE_IFACE_IDX; error = usbd_transfer_setup(uaa->device, &iface_index, sc->sc_xfer, aue_config, AUE_N_TRANSFER, sc, &sc->sc_mtx); if (error) { device_printf(dev, "allocating USB transfers failed\n"); goto detach; } ue->ue_sc = sc; ue->ue_dev = dev; ue->ue_udev = uaa->device; ue->ue_mtx = &sc->sc_mtx; ue->ue_methods = &aue_ue_methods; error = uether_ifattach(ue); if (error) { device_printf(dev, "could not attach interface\n"); goto detach; } return (0); /* success */ detach: aue_detach(dev); return (ENXIO); /* failure */ } static int aue_detach(device_t dev) { struct aue_softc *sc = device_get_softc(dev); struct usb_ether *ue = &sc->sc_ue; usbd_transfer_unsetup(sc->sc_xfer, AUE_N_TRANSFER); uether_ifdetach(ue); mtx_destroy(&sc->sc_mtx); return (0); } static void aue_intr_callback(struct usb_xfer *xfer, usb_error_t error) { struct aue_softc *sc = usbd_xfer_softc(xfer); struct ifnet *ifp = uether_getifp(&sc->sc_ue); struct aue_intrpkt pkt; struct usb_page_cache *pc; int actlen; usbd_xfer_status(xfer, &actlen, NULL, NULL, NULL); switch (USB_GET_STATE(xfer)) { case USB_ST_TRANSFERRED: if ((ifp->if_drv_flags & IFF_DRV_RUNNING) && actlen >= (int)sizeof(pkt)) { pc = usbd_xfer_get_frame(xfer, 0); usbd_copy_out(pc, 0, &pkt, sizeof(pkt)); if (pkt.aue_txstat0) if_inc_counter(ifp, IFCOUNTER_OERRORS, 1); if (pkt.aue_txstat0 & (AUE_TXSTAT0_LATECOLL | AUE_TXSTAT0_EXCESSCOLL)) if_inc_counter(ifp, IFCOUNTER_COLLISIONS, 1); } /* FALLTHROUGH */ case USB_ST_SETUP: tr_setup: usbd_xfer_set_frame_len(xfer, 0, usbd_xfer_max_len(xfer)); usbd_transfer_submit(xfer); return; default: /* Error */ if (error != USB_ERR_CANCELLED) { /* try to clear stall first */ usbd_xfer_set_stall(xfer); goto tr_setup; } return; } } static void aue_bulk_read_callback(struct usb_xfer *xfer, usb_error_t error) { struct aue_softc *sc = usbd_xfer_softc(xfer); struct usb_ether *ue = &sc->sc_ue; struct ifnet *ifp = uether_getifp(ue); struct aue_rxpkt stat; struct usb_page_cache *pc; int actlen; usbd_xfer_status(xfer, &actlen, NULL, NULL, NULL); pc = usbd_xfer_get_frame(xfer, 0); switch (USB_GET_STATE(xfer)) { case USB_ST_TRANSFERRED: DPRINTFN(11, "received %d bytes\n", actlen); if (sc->sc_flags & AUE_FLAG_VER_2) { if (actlen == 0) { if_inc_counter(ifp, IFCOUNTER_IERRORS, 1); goto tr_setup; } } else { if (actlen <= (int)(sizeof(stat) + ETHER_CRC_LEN)) { if_inc_counter(ifp, IFCOUNTER_IERRORS, 1); goto tr_setup; } usbd_copy_out(pc, actlen - sizeof(stat), &stat, sizeof(stat)); /* * turn off all the non-error bits in the rx status * word: */ stat.aue_rxstat &= AUE_RXSTAT_MASK; if (stat.aue_rxstat) { if_inc_counter(ifp, IFCOUNTER_IERRORS, 1); goto tr_setup; } /* No errors; receive the packet. */ actlen -= (sizeof(stat) + ETHER_CRC_LEN); } uether_rxbuf(ue, pc, 0, actlen); /* FALLTHROUGH */ case USB_ST_SETUP: tr_setup: usbd_xfer_set_frame_len(xfer, 0, usbd_xfer_max_len(xfer)); usbd_transfer_submit(xfer); uether_rxflush(ue); return; default: /* Error */ DPRINTF("bulk read error, %s\n", usbd_errstr(error)); if (error != USB_ERR_CANCELLED) { /* try to clear stall first */ usbd_xfer_set_stall(xfer); goto tr_setup; } return; } } static void aue_bulk_write_callback(struct usb_xfer *xfer, usb_error_t error) { struct aue_softc *sc = usbd_xfer_softc(xfer); struct ifnet *ifp = uether_getifp(&sc->sc_ue); struct usb_page_cache *pc; struct mbuf *m; uint8_t buf[2]; int actlen; usbd_xfer_status(xfer, &actlen, NULL, NULL, NULL); pc = usbd_xfer_get_frame(xfer, 0); switch (USB_GET_STATE(xfer)) { case USB_ST_TRANSFERRED: DPRINTFN(11, "transfer of %d bytes complete\n", actlen); if_inc_counter(ifp, IFCOUNTER_OPACKETS, 1); /* FALLTHROUGH */ case USB_ST_SETUP: tr_setup: if ((sc->sc_flags & AUE_FLAG_LINK) == 0) { /* * don't send anything if there is no link ! */ return; } IFQ_DRV_DEQUEUE(&ifp->if_snd, m); if (m == NULL) return; if (m->m_pkthdr.len > MCLBYTES) m->m_pkthdr.len = MCLBYTES; if (sc->sc_flags & AUE_FLAG_VER_2) { usbd_xfer_set_frame_len(xfer, 0, m->m_pkthdr.len); usbd_m_copy_in(pc, 0, m, 0, m->m_pkthdr.len); } else { usbd_xfer_set_frame_len(xfer, 0, (m->m_pkthdr.len + 2)); /* * The ADMtek documentation says that the * packet length is supposed to be specified * in the first two bytes of the transfer, * however it actually seems to ignore this * info and base the frame size on the bulk * transfer length. */ buf[0] = (uint8_t)(m->m_pkthdr.len); buf[1] = (uint8_t)(m->m_pkthdr.len >> 8); usbd_copy_in(pc, 0, buf, 2); usbd_m_copy_in(pc, 2, m, 0, m->m_pkthdr.len); } /* * if there's a BPF listener, bounce a copy * of this frame to him: */ BPF_MTAP(ifp, m); m_freem(m); usbd_transfer_submit(xfer); return; default: /* Error */ DPRINTFN(11, "transfer error, %s\n", usbd_errstr(error)); if_inc_counter(ifp, IFCOUNTER_OERRORS, 1); if (error != USB_ERR_CANCELLED) { /* try to clear stall first */ usbd_xfer_set_stall(xfer); goto tr_setup; } return; } } static void aue_tick(struct usb_ether *ue) { struct aue_softc *sc = uether_getsc(ue); struct mii_data *mii = GET_MII(sc); AUE_LOCK_ASSERT(sc, MA_OWNED); mii_tick(mii); if ((sc->sc_flags & AUE_FLAG_LINK) == 0 && mii->mii_media_status & IFM_ACTIVE && IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) { sc->sc_flags |= AUE_FLAG_LINK; aue_start(ue); } } static void aue_start(struct usb_ether *ue) { struct aue_softc *sc = uether_getsc(ue); /* * start the USB transfers, if not already started: */ usbd_transfer_start(sc->sc_xfer[AUE_INTR_DT_RD]); usbd_transfer_start(sc->sc_xfer[AUE_BULK_DT_RD]); usbd_transfer_start(sc->sc_xfer[AUE_BULK_DT_WR]); } static void aue_init(struct usb_ether *ue) { struct aue_softc *sc = uether_getsc(ue); struct ifnet *ifp = uether_getifp(ue); int i; AUE_LOCK_ASSERT(sc, MA_OWNED); /* * Cancel pending I/O */ aue_reset(sc); /* Set MAC address */ for (i = 0; i != ETHER_ADDR_LEN; i++) aue_csr_write_1(sc, AUE_PAR0 + i, IF_LLADDR(ifp)[i]); /* update promiscuous setting */ aue_setpromisc(ue); /* Load the multicast filter. */ aue_setmulti(ue); /* Enable RX and TX */ aue_csr_write_1(sc, AUE_CTL0, AUE_CTL0_RXSTAT_APPEND | AUE_CTL0_RX_ENB); AUE_SETBIT(sc, AUE_CTL0, AUE_CTL0_TX_ENB); AUE_SETBIT(sc, AUE_CTL2, AUE_CTL2_EP3_CLR); usbd_xfer_set_stall(sc->sc_xfer[AUE_BULK_DT_WR]); ifp->if_drv_flags |= IFF_DRV_RUNNING; aue_start(ue); } static void aue_setpromisc(struct usb_ether *ue) { struct aue_softc *sc = uether_getsc(ue); struct ifnet *ifp = uether_getifp(ue); AUE_LOCK_ASSERT(sc, MA_OWNED); /* if we want promiscuous mode, set the allframes bit: */ if (ifp->if_flags & IFF_PROMISC) AUE_SETBIT(sc, AUE_CTL2, AUE_CTL2_RX_PROMISC); else AUE_CLRBIT(sc, AUE_CTL2, AUE_CTL2_RX_PROMISC); } /* * Set media options. */ static int aue_ifmedia_upd(struct ifnet *ifp) { struct aue_softc *sc = ifp->if_softc; struct mii_data *mii = GET_MII(sc); struct mii_softc *miisc; int error; AUE_LOCK_ASSERT(sc, MA_OWNED); sc->sc_flags &= ~AUE_FLAG_LINK; LIST_FOREACH(miisc, &mii->mii_phys, mii_list) PHY_RESET(miisc); error = mii_mediachg(mii); return (error); } /* * Report current media status. */ static void aue_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) { struct aue_softc *sc = ifp->if_softc; struct mii_data *mii = GET_MII(sc); AUE_LOCK(sc); mii_pollstat(mii); ifmr->ifm_active = mii->mii_media_active; ifmr->ifm_status = mii->mii_media_status; AUE_UNLOCK(sc); } /* * Stop the adapter and free any mbufs allocated to the * RX and TX lists. */ static void aue_stop(struct usb_ether *ue) { struct aue_softc *sc = uether_getsc(ue); struct ifnet *ifp = uether_getifp(ue); AUE_LOCK_ASSERT(sc, MA_OWNED); ifp->if_drv_flags &= ~IFF_DRV_RUNNING; sc->sc_flags &= ~AUE_FLAG_LINK; /* * stop all the transfers, if not already stopped: */ usbd_transfer_stop(sc->sc_xfer[AUE_BULK_DT_WR]); usbd_transfer_stop(sc->sc_xfer[AUE_BULK_DT_RD]); usbd_transfer_stop(sc->sc_xfer[AUE_INTR_DT_RD]); aue_csr_write_1(sc, AUE_CTL0, 0); aue_csr_write_1(sc, AUE_CTL1, 0); aue_reset(sc); } Index: head/sys/dev/usb/net/if_axe.c =================================================================== --- head/sys/dev/usb/net/if_axe.c (revision 351249) +++ head/sys/dev/usb/net/if_axe.c (revision 351250) @@ -1,1507 +1,1509 @@ /*- * SPDX-License-Identifier: BSD-4-Clause * * Copyright (c) 1997, 1998, 1999, 2000-2003 * Bill Paul . All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * 3. All advertising materials mentioning features or use of this software * must display the following acknowledgement: * This product includes software developed by Bill Paul. * 4. Neither the name of the author nor the names of any co-contributors * may be used to endorse or promote products derived from this software * without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF * THE POSSIBILITY OF SUCH DAMAGE. */ #include __FBSDID("$FreeBSD$"); /* * ASIX Electronics AX88172/AX88178/AX88778 USB 2.0 ethernet driver. * Used in the LinkSys USB200M and various other adapters. * * Manuals available from: * http://www.asix.com.tw/datasheet/mac/Ax88172.PDF * Note: you need the manual for the AX88170 chip (USB 1.x ethernet * controller) to find the definitions for the RX control register. * http://www.asix.com.tw/datasheet/mac/Ax88170.PDF * * Written by Bill Paul * Senior Engineer * Wind River Systems */ /* * The AX88172 provides USB ethernet supports at 10 and 100Mbps. * It uses an external PHY (reference designs use a RealTek chip), * and has a 64-bit multicast hash filter. There is some information * missing from the manual which one needs to know in order to make * the chip function: * * - You must set bit 7 in the RX control register, otherwise the * chip won't receive any packets. * - You must initialize all 3 IPG registers, or you won't be able * to send any packets. * * Note that this device appears to only support loading the station * address via autload from the EEPROM (i.e. there's no way to manaully * set it). * * (Adam Weinberger wanted me to name this driver if_gir.c.) */ /* * Ax88178 and Ax88772 support backported from the OpenBSD driver. * 2007/02/12, J.R. Oldroyd, fbsd@opal.com * * Manual here: * http://www.asix.com.tw/FrootAttach/datasheet/AX88178_datasheet_Rev10.pdf * http://www.asix.com.tw/FrootAttach/datasheet/AX88772_datasheet_Rev10.pdf */ #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include "usbdevs.h" #define USB_DEBUG_VAR axe_debug #include #include #include #include +#include "miibus_if.h" + /* * AXE_178_MAX_FRAME_BURST * max frame burst size for Ax88178 and Ax88772 * 0 2048 bytes * 1 4096 bytes * 2 8192 bytes * 3 16384 bytes * use the largest your system can handle without USB stalling. * * NB: 88772 parts appear to generate lots of input errors with * a 2K rx buffer and 8K is only slightly faster than 4K on an * EHCI port on a T42 so change at your own risk. */ #define AXE_178_MAX_FRAME_BURST 1 #define AXE_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP) #ifdef USB_DEBUG static int axe_debug = 0; static SYSCTL_NODE(_hw_usb, OID_AUTO, axe, CTLFLAG_RW, 0, "USB axe"); SYSCTL_INT(_hw_usb_axe, OID_AUTO, debug, CTLFLAG_RWTUN, &axe_debug, 0, "Debug level"); #endif /* * Various supported device vendors/products. */ static const STRUCT_USB_HOST_ID axe_devs[] = { #define AXE_DEV(v,p,i) { USB_VPI(USB_VENDOR_##v, USB_PRODUCT_##v##_##p, i) } AXE_DEV(ABOCOM, UF200, 0), AXE_DEV(ACERCM, EP1427X2, 0), AXE_DEV(APPLE, ETHERNET, AXE_FLAG_772), AXE_DEV(ASIX, AX88172, 0), AXE_DEV(ASIX, AX88178, AXE_FLAG_178), AXE_DEV(ASIX, AX88772, AXE_FLAG_772), AXE_DEV(ASIX, AX88772A, AXE_FLAG_772A), AXE_DEV(ASIX, AX88772B, AXE_FLAG_772B), AXE_DEV(ASIX, AX88772B_1, AXE_FLAG_772B), AXE_DEV(ATEN, UC210T, 0), AXE_DEV(BELKIN, F5D5055, AXE_FLAG_178), AXE_DEV(BILLIONTON, USB2AR, 0), AXE_DEV(CISCOLINKSYS, USB200MV2, AXE_FLAG_772A), AXE_DEV(COREGA, FETHER_USB2_TX, 0), AXE_DEV(DLINK, DUBE100, 0), AXE_DEV(DLINK, DUBE100B1, AXE_FLAG_772), AXE_DEV(DLINK, DUBE100C1, AXE_FLAG_772B), AXE_DEV(GOODWAY, GWUSB2E, 0), AXE_DEV(IODATA, ETGUS2, AXE_FLAG_178), AXE_DEV(JVC, MP_PRX1, 0), AXE_DEV(LENOVO, ETHERNET, AXE_FLAG_772B), AXE_DEV(LINKSYS2, USB200M, 0), AXE_DEV(LINKSYS4, USB1000, AXE_FLAG_178), AXE_DEV(LOGITEC, LAN_GTJU2A, AXE_FLAG_178), AXE_DEV(MELCO, LUAU2KTX, 0), AXE_DEV(MELCO, LUA3U2AGT, AXE_FLAG_178), AXE_DEV(NETGEAR, FA120, 0), AXE_DEV(OQO, ETHER01PLUS, AXE_FLAG_772), AXE_DEV(PLANEX3, GU1000T, AXE_FLAG_178), AXE_DEV(SITECOM, LN029, 0), AXE_DEV(SITECOMEU, LN028, AXE_FLAG_178), AXE_DEV(SITECOMEU, LN031, AXE_FLAG_178), AXE_DEV(SYSTEMTALKS, SGCX2UL, 0), #undef AXE_DEV }; static device_probe_t axe_probe; static device_attach_t axe_attach; static device_detach_t axe_detach; static usb_callback_t axe_bulk_read_callback; static usb_callback_t axe_bulk_write_callback; static miibus_readreg_t axe_miibus_readreg; static miibus_writereg_t axe_miibus_writereg; static miibus_statchg_t axe_miibus_statchg; static uether_fn_t axe_attach_post; static uether_fn_t axe_init; static uether_fn_t axe_stop; static uether_fn_t axe_start; static uether_fn_t axe_tick; static uether_fn_t axe_setmulti; static uether_fn_t axe_setpromisc; static int axe_attach_post_sub(struct usb_ether *); static int axe_ifmedia_upd(struct ifnet *); static void axe_ifmedia_sts(struct ifnet *, struct ifmediareq *); static int axe_cmd(struct axe_softc *, int, int, int, void *); static void axe_ax88178_init(struct axe_softc *); static void axe_ax88772_init(struct axe_softc *); static void axe_ax88772_phywake(struct axe_softc *); static void axe_ax88772a_init(struct axe_softc *); static void axe_ax88772b_init(struct axe_softc *); static int axe_get_phyno(struct axe_softc *, int); static int axe_ioctl(struct ifnet *, u_long, caddr_t); static int axe_rx_frame(struct usb_ether *, struct usb_page_cache *, int); static int axe_rxeof(struct usb_ether *, struct usb_page_cache *, unsigned int offset, unsigned int, struct axe_csum_hdr *); static void axe_csum_cfg(struct usb_ether *); static const struct usb_config axe_config[AXE_N_TRANSFER] = { [AXE_BULK_DT_WR] = { .type = UE_BULK, .endpoint = UE_ADDR_ANY, .direction = UE_DIR_OUT, .frames = 16, .bufsize = 16 * MCLBYTES, .flags = {.pipe_bof = 1,.force_short_xfer = 1,}, .callback = axe_bulk_write_callback, .timeout = 10000, /* 10 seconds */ }, [AXE_BULK_DT_RD] = { .type = UE_BULK, .endpoint = UE_ADDR_ANY, .direction = UE_DIR_IN, .bufsize = 16384, /* bytes */ .flags = {.pipe_bof = 1,.short_xfer_ok = 1,}, .callback = axe_bulk_read_callback, .timeout = 0, /* no timeout */ }, }; static const struct ax88772b_mfb ax88772b_mfb_table[] = { { 0x8000, 0x8001, 2048 }, { 0x8100, 0x8147, 4096}, { 0x8200, 0x81EB, 6144}, { 0x8300, 0x83D7, 8192}, { 0x8400, 0x851E, 16384}, { 0x8500, 0x8666, 20480}, { 0x8600, 0x87AE, 24576}, { 0x8700, 0x8A3D, 32768} }; static device_method_t axe_methods[] = { /* Device interface */ DEVMETHOD(device_probe, axe_probe), DEVMETHOD(device_attach, axe_attach), DEVMETHOD(device_detach, axe_detach), /* MII interface */ DEVMETHOD(miibus_readreg, axe_miibus_readreg), DEVMETHOD(miibus_writereg, axe_miibus_writereg), DEVMETHOD(miibus_statchg, axe_miibus_statchg), DEVMETHOD_END }; static driver_t axe_driver = { .name = "axe", .methods = axe_methods, .size = sizeof(struct axe_softc), }; static devclass_t axe_devclass; DRIVER_MODULE(axe, uhub, axe_driver, axe_devclass, NULL, 0); DRIVER_MODULE(miibus, axe, miibus_driver, miibus_devclass, 0, 0); MODULE_DEPEND(axe, uether, 1, 1, 1); MODULE_DEPEND(axe, usb, 1, 1, 1); MODULE_DEPEND(axe, ether, 1, 1, 1); MODULE_DEPEND(axe, miibus, 1, 1, 1); MODULE_VERSION(axe, 1); USB_PNP_HOST_INFO(axe_devs); static const struct usb_ether_methods axe_ue_methods = { .ue_attach_post = axe_attach_post, .ue_attach_post_sub = axe_attach_post_sub, .ue_start = axe_start, .ue_init = axe_init, .ue_stop = axe_stop, .ue_tick = axe_tick, .ue_setmulti = axe_setmulti, .ue_setpromisc = axe_setpromisc, .ue_mii_upd = axe_ifmedia_upd, .ue_mii_sts = axe_ifmedia_sts, }; static int axe_cmd(struct axe_softc *sc, int cmd, int index, int val, void *buf) { struct usb_device_request req; usb_error_t err; AXE_LOCK_ASSERT(sc, MA_OWNED); req.bmRequestType = (AXE_CMD_IS_WRITE(cmd) ? UT_WRITE_VENDOR_DEVICE : UT_READ_VENDOR_DEVICE); req.bRequest = AXE_CMD_CMD(cmd); USETW(req.wValue, val); USETW(req.wIndex, index); USETW(req.wLength, AXE_CMD_LEN(cmd)); err = uether_do_request(&sc->sc_ue, &req, buf, 1000); return (err); } static int axe_miibus_readreg(device_t dev, int phy, int reg) { struct axe_softc *sc = device_get_softc(dev); uint16_t val; int locked; locked = mtx_owned(&sc->sc_mtx); if (!locked) AXE_LOCK(sc); axe_cmd(sc, AXE_CMD_MII_OPMODE_SW, 0, 0, NULL); axe_cmd(sc, AXE_CMD_MII_READ_REG, reg, phy, &val); axe_cmd(sc, AXE_CMD_MII_OPMODE_HW, 0, 0, NULL); val = le16toh(val); if (AXE_IS_772(sc) && reg == MII_BMSR) { /* * BMSR of AX88772 indicates that it supports extended * capability but the extended status register is * revered for embedded ethernet PHY. So clear the * extended capability bit of BMSR. */ val &= ~BMSR_EXTCAP; } if (!locked) AXE_UNLOCK(sc); return (val); } static int axe_miibus_writereg(device_t dev, int phy, int reg, int val) { struct axe_softc *sc = device_get_softc(dev); int locked; val = htole32(val); locked = mtx_owned(&sc->sc_mtx); if (!locked) AXE_LOCK(sc); axe_cmd(sc, AXE_CMD_MII_OPMODE_SW, 0, 0, NULL); axe_cmd(sc, AXE_CMD_MII_WRITE_REG, reg, phy, &val); axe_cmd(sc, AXE_CMD_MII_OPMODE_HW, 0, 0, NULL); if (!locked) AXE_UNLOCK(sc); return (0); } static void axe_miibus_statchg(device_t dev) { struct axe_softc *sc = device_get_softc(dev); struct mii_data *mii = GET_MII(sc); struct ifnet *ifp; uint16_t val; int err, locked; locked = mtx_owned(&sc->sc_mtx); if (!locked) AXE_LOCK(sc); ifp = uether_getifp(&sc->sc_ue); if (mii == NULL || ifp == NULL || (ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) goto done; sc->sc_flags &= ~AXE_FLAG_LINK; if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) == (IFM_ACTIVE | IFM_AVALID)) { switch (IFM_SUBTYPE(mii->mii_media_active)) { case IFM_10_T: case IFM_100_TX: sc->sc_flags |= AXE_FLAG_LINK; break; case IFM_1000_T: if ((sc->sc_flags & AXE_FLAG_178) == 0) break; sc->sc_flags |= AXE_FLAG_LINK; break; default: break; } } /* Lost link, do nothing. */ if ((sc->sc_flags & AXE_FLAG_LINK) == 0) goto done; val = 0; if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0) { val |= AXE_MEDIA_FULL_DUPLEX; if (AXE_IS_178_FAMILY(sc)) { if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_TXPAUSE) != 0) val |= AXE_178_MEDIA_TXFLOW_CONTROL_EN; if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_RXPAUSE) != 0) val |= AXE_178_MEDIA_RXFLOW_CONTROL_EN; } } if (AXE_IS_178_FAMILY(sc)) { val |= AXE_178_MEDIA_RX_EN | AXE_178_MEDIA_MAGIC; if ((sc->sc_flags & AXE_FLAG_178) != 0) val |= AXE_178_MEDIA_ENCK; switch (IFM_SUBTYPE(mii->mii_media_active)) { case IFM_1000_T: val |= AXE_178_MEDIA_GMII | AXE_178_MEDIA_ENCK; break; case IFM_100_TX: val |= AXE_178_MEDIA_100TX; break; case IFM_10_T: /* doesn't need to be handled */ break; } } err = axe_cmd(sc, AXE_CMD_WRITE_MEDIA, 0, val, NULL); if (err) device_printf(dev, "media change failed, error %d\n", err); done: if (!locked) AXE_UNLOCK(sc); } /* * Set media options. */ static int axe_ifmedia_upd(struct ifnet *ifp) { struct axe_softc *sc = ifp->if_softc; struct mii_data *mii = GET_MII(sc); struct mii_softc *miisc; int error; AXE_LOCK_ASSERT(sc, MA_OWNED); LIST_FOREACH(miisc, &mii->mii_phys, mii_list) PHY_RESET(miisc); error = mii_mediachg(mii); return (error); } /* * Report current media status. */ static void axe_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) { struct axe_softc *sc = ifp->if_softc; struct mii_data *mii = GET_MII(sc); AXE_LOCK(sc); mii_pollstat(mii); ifmr->ifm_active = mii->mii_media_active; ifmr->ifm_status = mii->mii_media_status; AXE_UNLOCK(sc); } static void axe_setmulti(struct usb_ether *ue) { struct axe_softc *sc = uether_getsc(ue); struct ifnet *ifp = uether_getifp(ue); struct ifmultiaddr *ifma; uint32_t h = 0; uint16_t rxmode; uint8_t hashtbl[8] = { 0, 0, 0, 0, 0, 0, 0, 0 }; AXE_LOCK_ASSERT(sc, MA_OWNED); axe_cmd(sc, AXE_CMD_RXCTL_READ, 0, 0, &rxmode); rxmode = le16toh(rxmode); if (ifp->if_flags & (IFF_ALLMULTI | IFF_PROMISC)) { rxmode |= AXE_RXCMD_ALLMULTI; axe_cmd(sc, AXE_CMD_RXCTL_WRITE, 0, rxmode, NULL); return; } rxmode &= ~AXE_RXCMD_ALLMULTI; if_maddr_rlock(ifp); CK_STAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { if (ifma->ifma_addr->sa_family != AF_LINK) continue; h = ether_crc32_be(LLADDR((struct sockaddr_dl *) ifma->ifma_addr), ETHER_ADDR_LEN) >> 26; hashtbl[h / 8] |= 1 << (h % 8); } if_maddr_runlock(ifp); axe_cmd(sc, AXE_CMD_WRITE_MCAST, 0, 0, (void *)&hashtbl); axe_cmd(sc, AXE_CMD_RXCTL_WRITE, 0, rxmode, NULL); } static int axe_get_phyno(struct axe_softc *sc, int sel) { int phyno; switch (AXE_PHY_TYPE(sc->sc_phyaddrs[sel])) { case PHY_TYPE_100_HOME: case PHY_TYPE_GIG: phyno = AXE_PHY_NO(sc->sc_phyaddrs[sel]); break; case PHY_TYPE_SPECIAL: /* FALLTHROUGH */ case PHY_TYPE_RSVD: /* FALLTHROUGH */ case PHY_TYPE_NON_SUP: /* FALLTHROUGH */ default: phyno = -1; break; } return (phyno); } #define AXE_GPIO_WRITE(x, y) do { \ axe_cmd(sc, AXE_CMD_WRITE_GPIO, 0, (x), NULL); \ uether_pause(ue, (y)); \ } while (0) static void axe_ax88178_init(struct axe_softc *sc) { struct usb_ether *ue; int gpio0, ledmode, phymode; uint16_t eeprom, val; ue = &sc->sc_ue; axe_cmd(sc, AXE_CMD_SROM_WR_ENABLE, 0, 0, NULL); /* XXX magic */ axe_cmd(sc, AXE_CMD_SROM_READ, 0, 0x0017, &eeprom); eeprom = le16toh(eeprom); axe_cmd(sc, AXE_CMD_SROM_WR_DISABLE, 0, 0, NULL); /* if EEPROM is invalid we have to use to GPIO0 */ if (eeprom == 0xffff) { phymode = AXE_PHY_MODE_MARVELL; gpio0 = 1; ledmode = 0; } else { phymode = eeprom & 0x7f; gpio0 = (eeprom & 0x80) ? 0 : 1; ledmode = eeprom >> 8; } if (bootverbose) device_printf(sc->sc_ue.ue_dev, "EEPROM data : 0x%04x, phymode : 0x%02x\n", eeprom, phymode); /* Program GPIOs depending on PHY hardware. */ switch (phymode) { case AXE_PHY_MODE_MARVELL: if (gpio0 == 1) { AXE_GPIO_WRITE(AXE_GPIO_RELOAD_EEPROM | AXE_GPIO0_EN, hz / 32); AXE_GPIO_WRITE(AXE_GPIO0_EN | AXE_GPIO2 | AXE_GPIO2_EN, hz / 32); AXE_GPIO_WRITE(AXE_GPIO0_EN | AXE_GPIO2_EN, hz / 4); AXE_GPIO_WRITE(AXE_GPIO0_EN | AXE_GPIO2 | AXE_GPIO2_EN, hz / 32); } else { AXE_GPIO_WRITE(AXE_GPIO_RELOAD_EEPROM | AXE_GPIO1 | AXE_GPIO1_EN, hz / 3); if (ledmode == 1) { AXE_GPIO_WRITE(AXE_GPIO1_EN, hz / 3); AXE_GPIO_WRITE(AXE_GPIO1 | AXE_GPIO1_EN, hz / 3); } else { AXE_GPIO_WRITE(AXE_GPIO1 | AXE_GPIO1_EN | AXE_GPIO2 | AXE_GPIO2_EN, hz / 32); AXE_GPIO_WRITE(AXE_GPIO1 | AXE_GPIO1_EN | AXE_GPIO2_EN, hz / 4); AXE_GPIO_WRITE(AXE_GPIO1 | AXE_GPIO1_EN | AXE_GPIO2 | AXE_GPIO2_EN, hz / 32); } } break; case AXE_PHY_MODE_CICADA: case AXE_PHY_MODE_CICADA_V2: case AXE_PHY_MODE_CICADA_V2_ASIX: if (gpio0 == 1) AXE_GPIO_WRITE(AXE_GPIO_RELOAD_EEPROM | AXE_GPIO0 | AXE_GPIO0_EN, hz / 32); else AXE_GPIO_WRITE(AXE_GPIO_RELOAD_EEPROM | AXE_GPIO1 | AXE_GPIO1_EN, hz / 32); break; case AXE_PHY_MODE_AGERE: AXE_GPIO_WRITE(AXE_GPIO_RELOAD_EEPROM | AXE_GPIO1 | AXE_GPIO1_EN, hz / 32); AXE_GPIO_WRITE(AXE_GPIO1 | AXE_GPIO1_EN | AXE_GPIO2 | AXE_GPIO2_EN, hz / 32); AXE_GPIO_WRITE(AXE_GPIO1 | AXE_GPIO1_EN | AXE_GPIO2_EN, hz / 4); AXE_GPIO_WRITE(AXE_GPIO1 | AXE_GPIO1_EN | AXE_GPIO2 | AXE_GPIO2_EN, hz / 32); break; case AXE_PHY_MODE_REALTEK_8211CL: case AXE_PHY_MODE_REALTEK_8211BN: case AXE_PHY_MODE_REALTEK_8251CL: val = gpio0 == 1 ? AXE_GPIO0 | AXE_GPIO0_EN : AXE_GPIO1 | AXE_GPIO1_EN; AXE_GPIO_WRITE(val, hz / 32); AXE_GPIO_WRITE(val | AXE_GPIO2 | AXE_GPIO2_EN, hz / 32); AXE_GPIO_WRITE(val | AXE_GPIO2_EN, hz / 4); AXE_GPIO_WRITE(val | AXE_GPIO2 | AXE_GPIO2_EN, hz / 32); if (phymode == AXE_PHY_MODE_REALTEK_8211CL) { axe_miibus_writereg(ue->ue_dev, sc->sc_phyno, 0x1F, 0x0005); axe_miibus_writereg(ue->ue_dev, sc->sc_phyno, 0x0C, 0x0000); val = axe_miibus_readreg(ue->ue_dev, sc->sc_phyno, 0x0001); axe_miibus_writereg(ue->ue_dev, sc->sc_phyno, 0x01, val | 0x0080); axe_miibus_writereg(ue->ue_dev, sc->sc_phyno, 0x1F, 0x0000); } break; default: /* Unknown PHY model or no need to program GPIOs. */ break; } /* soft reset */ axe_cmd(sc, AXE_CMD_SW_RESET_REG, 0, AXE_SW_RESET_CLEAR, NULL); uether_pause(ue, hz / 4); axe_cmd(sc, AXE_CMD_SW_RESET_REG, 0, AXE_SW_RESET_PRL | AXE_178_RESET_MAGIC, NULL); uether_pause(ue, hz / 4); /* Enable MII/GMII/RGMII interface to work with external PHY. */ axe_cmd(sc, AXE_CMD_SW_PHY_SELECT, 0, 0, NULL); uether_pause(ue, hz / 4); axe_cmd(sc, AXE_CMD_RXCTL_WRITE, 0, 0, NULL); } static void axe_ax88772_init(struct axe_softc *sc) { axe_cmd(sc, AXE_CMD_WRITE_GPIO, 0, 0x00b0, NULL); uether_pause(&sc->sc_ue, hz / 16); if (sc->sc_phyno == AXE_772_PHY_NO_EPHY) { /* ask for the embedded PHY */ axe_cmd(sc, AXE_CMD_SW_PHY_SELECT, 0, 0x01, NULL); uether_pause(&sc->sc_ue, hz / 64); /* power down and reset state, pin reset state */ axe_cmd(sc, AXE_CMD_SW_RESET_REG, 0, AXE_SW_RESET_CLEAR, NULL); uether_pause(&sc->sc_ue, hz / 16); /* power down/reset state, pin operating state */ axe_cmd(sc, AXE_CMD_SW_RESET_REG, 0, AXE_SW_RESET_IPPD | AXE_SW_RESET_PRL, NULL); uether_pause(&sc->sc_ue, hz / 4); /* power up, reset */ axe_cmd(sc, AXE_CMD_SW_RESET_REG, 0, AXE_SW_RESET_PRL, NULL); /* power up, operating */ axe_cmd(sc, AXE_CMD_SW_RESET_REG, 0, AXE_SW_RESET_IPRL | AXE_SW_RESET_PRL, NULL); } else { /* ask for external PHY */ axe_cmd(sc, AXE_CMD_SW_PHY_SELECT, 0, 0x00, NULL); uether_pause(&sc->sc_ue, hz / 64); /* power down internal PHY */ axe_cmd(sc, AXE_CMD_SW_RESET_REG, 0, AXE_SW_RESET_IPPD | AXE_SW_RESET_PRL, NULL); } uether_pause(&sc->sc_ue, hz / 4); axe_cmd(sc, AXE_CMD_RXCTL_WRITE, 0, 0, NULL); } static void axe_ax88772_phywake(struct axe_softc *sc) { struct usb_ether *ue; ue = &sc->sc_ue; if (sc->sc_phyno == AXE_772_PHY_NO_EPHY) { /* Manually select internal(embedded) PHY - MAC mode. */ axe_cmd(sc, AXE_CMD_SW_PHY_SELECT, 0, AXE_SW_PHY_SELECT_SS_ENB | AXE_SW_PHY_SELECT_EMBEDDED | AXE_SW_PHY_SELECT_SS_MII, NULL); uether_pause(&sc->sc_ue, hz / 32); } else { /* * Manually select external PHY - MAC mode. * Reverse MII/RMII is for AX88772A PHY mode. */ axe_cmd(sc, AXE_CMD_SW_PHY_SELECT, 0, AXE_SW_PHY_SELECT_SS_ENB | AXE_SW_PHY_SELECT_EXT | AXE_SW_PHY_SELECT_SS_MII, NULL); uether_pause(&sc->sc_ue, hz / 32); } /* Take PHY out of power down. */ axe_cmd(sc, AXE_CMD_SW_RESET_REG, 0, AXE_SW_RESET_IPPD | AXE_SW_RESET_IPRL, NULL); uether_pause(&sc->sc_ue, hz / 4); axe_cmd(sc, AXE_CMD_SW_RESET_REG, 0, AXE_SW_RESET_IPRL, NULL); uether_pause(&sc->sc_ue, hz); axe_cmd(sc, AXE_CMD_SW_RESET_REG, 0, AXE_SW_RESET_CLEAR, NULL); uether_pause(&sc->sc_ue, hz / 32); axe_cmd(sc, AXE_CMD_SW_RESET_REG, 0, AXE_SW_RESET_IPRL, NULL); uether_pause(&sc->sc_ue, hz / 32); } static void axe_ax88772a_init(struct axe_softc *sc) { struct usb_ether *ue; ue = &sc->sc_ue; /* Reload EEPROM. */ AXE_GPIO_WRITE(AXE_GPIO_RELOAD_EEPROM, hz / 32); axe_ax88772_phywake(sc); /* Stop MAC. */ axe_cmd(sc, AXE_CMD_RXCTL_WRITE, 0, 0, NULL); } static void axe_ax88772b_init(struct axe_softc *sc) { struct usb_ether *ue; uint16_t eeprom; uint8_t *eaddr; int i; ue = &sc->sc_ue; /* Reload EEPROM. */ AXE_GPIO_WRITE(AXE_GPIO_RELOAD_EEPROM, hz / 32); /* * Save PHY power saving configuration(high byte) and * clear EEPROM checksum value(low byte). */ axe_cmd(sc, AXE_CMD_SROM_READ, 0, AXE_EEPROM_772B_PHY_PWRCFG, &eeprom); sc->sc_pwrcfg = le16toh(eeprom) & 0xFF00; /* * Auto-loaded default station address from internal ROM is * 00:00:00:00:00:00 such that an explicit access to EEPROM * is required to get real station address. */ eaddr = ue->ue_eaddr; for (i = 0; i < ETHER_ADDR_LEN / 2; i++) { axe_cmd(sc, AXE_CMD_SROM_READ, 0, AXE_EEPROM_772B_NODE_ID + i, &eeprom); eeprom = le16toh(eeprom); *eaddr++ = (uint8_t)(eeprom & 0xFF); *eaddr++ = (uint8_t)((eeprom >> 8) & 0xFF); } /* Wakeup PHY. */ axe_ax88772_phywake(sc); /* Stop MAC. */ axe_cmd(sc, AXE_CMD_RXCTL_WRITE, 0, 0, NULL); } #undef AXE_GPIO_WRITE static void axe_reset(struct axe_softc *sc) { struct usb_config_descriptor *cd; usb_error_t err; cd = usbd_get_config_descriptor(sc->sc_ue.ue_udev); err = usbd_req_set_config(sc->sc_ue.ue_udev, &sc->sc_mtx, cd->bConfigurationValue); if (err) DPRINTF("reset failed (ignored)\n"); /* Wait a little while for the chip to get its brains in order. */ uether_pause(&sc->sc_ue, hz / 100); /* Reinitialize controller to achieve full reset. */ if (sc->sc_flags & AXE_FLAG_178) axe_ax88178_init(sc); else if (sc->sc_flags & AXE_FLAG_772) axe_ax88772_init(sc); else if (sc->sc_flags & AXE_FLAG_772A) axe_ax88772a_init(sc); else if (sc->sc_flags & AXE_FLAG_772B) axe_ax88772b_init(sc); } static void axe_attach_post(struct usb_ether *ue) { struct axe_softc *sc = uether_getsc(ue); /* * Load PHY indexes first. Needed by axe_xxx_init(). */ axe_cmd(sc, AXE_CMD_READ_PHYID, 0, 0, sc->sc_phyaddrs); if (bootverbose) device_printf(sc->sc_ue.ue_dev, "PHYADDR 0x%02x:0x%02x\n", sc->sc_phyaddrs[0], sc->sc_phyaddrs[1]); sc->sc_phyno = axe_get_phyno(sc, AXE_PHY_SEL_PRI); if (sc->sc_phyno == -1) sc->sc_phyno = axe_get_phyno(sc, AXE_PHY_SEL_SEC); if (sc->sc_phyno == -1) { device_printf(sc->sc_ue.ue_dev, "no valid PHY address found, assuming PHY address 0\n"); sc->sc_phyno = 0; } /* Initialize controller and get station address. */ if (sc->sc_flags & AXE_FLAG_178) { axe_ax88178_init(sc); axe_cmd(sc, AXE_178_CMD_READ_NODEID, 0, 0, ue->ue_eaddr); } else if (sc->sc_flags & AXE_FLAG_772) { axe_ax88772_init(sc); axe_cmd(sc, AXE_178_CMD_READ_NODEID, 0, 0, ue->ue_eaddr); } else if (sc->sc_flags & AXE_FLAG_772A) { axe_ax88772a_init(sc); axe_cmd(sc, AXE_178_CMD_READ_NODEID, 0, 0, ue->ue_eaddr); } else if (sc->sc_flags & AXE_FLAG_772B) { axe_ax88772b_init(sc); } else axe_cmd(sc, AXE_172_CMD_READ_NODEID, 0, 0, ue->ue_eaddr); /* * Fetch IPG values. */ if (sc->sc_flags & (AXE_FLAG_772A | AXE_FLAG_772B)) { /* Set IPG values. */ sc->sc_ipgs[0] = 0x15; sc->sc_ipgs[1] = 0x16; sc->sc_ipgs[2] = 0x1A; } else axe_cmd(sc, AXE_CMD_READ_IPG012, 0, 0, sc->sc_ipgs); } static int axe_attach_post_sub(struct usb_ether *ue) { struct axe_softc *sc; struct ifnet *ifp; u_int adv_pause; int error; sc = uether_getsc(ue); ifp = ue->ue_ifp; ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; ifp->if_start = uether_start; ifp->if_ioctl = axe_ioctl; ifp->if_init = uether_init; IFQ_SET_MAXLEN(&ifp->if_snd, ifqmaxlen); ifp->if_snd.ifq_drv_maxlen = ifqmaxlen; IFQ_SET_READY(&ifp->if_snd); if (AXE_IS_178_FAMILY(sc)) ifp->if_capabilities |= IFCAP_VLAN_MTU; if (sc->sc_flags & AXE_FLAG_772B) { ifp->if_capabilities |= IFCAP_TXCSUM | IFCAP_RXCSUM; ifp->if_hwassist = AXE_CSUM_FEATURES; /* * Checksum offloading of AX88772B also works with VLAN * tagged frames but there is no way to take advantage * of the feature because vlan(4) assumes * IFCAP_VLAN_HWTAGGING is prerequisite condition to * support checksum offloading with VLAN. VLAN hardware * tagging support of AX88772B is very limited so it's * not possible to announce IFCAP_VLAN_HWTAGGING. */ } ifp->if_capenable = ifp->if_capabilities; if (sc->sc_flags & (AXE_FLAG_772A | AXE_FLAG_772B | AXE_FLAG_178)) adv_pause = MIIF_DOPAUSE; else adv_pause = 0; mtx_lock(&Giant); error = mii_attach(ue->ue_dev, &ue->ue_miibus, ifp, uether_ifmedia_upd, ue->ue_methods->ue_mii_sts, BMSR_DEFCAPMASK, sc->sc_phyno, MII_OFFSET_ANY, adv_pause); mtx_unlock(&Giant); return (error); } /* * Probe for a AX88172 chip. */ static int axe_probe(device_t dev) { struct usb_attach_arg *uaa = device_get_ivars(dev); if (uaa->usb_mode != USB_MODE_HOST) return (ENXIO); if (uaa->info.bConfigIndex != AXE_CONFIG_IDX) return (ENXIO); if (uaa->info.bIfaceIndex != AXE_IFACE_IDX) return (ENXIO); return (usbd_lookup_id_by_uaa(axe_devs, sizeof(axe_devs), uaa)); } /* * Attach the interface. Allocate softc structures, do ifmedia * setup and ethernet/BPF attach. */ static int axe_attach(device_t dev) { struct usb_attach_arg *uaa = device_get_ivars(dev); struct axe_softc *sc = device_get_softc(dev); struct usb_ether *ue = &sc->sc_ue; uint8_t iface_index; int error; sc->sc_flags = USB_GET_DRIVER_INFO(uaa); device_set_usb_desc(dev); mtx_init(&sc->sc_mtx, device_get_nameunit(dev), NULL, MTX_DEF); iface_index = AXE_IFACE_IDX; error = usbd_transfer_setup(uaa->device, &iface_index, sc->sc_xfer, axe_config, AXE_N_TRANSFER, sc, &sc->sc_mtx); if (error) { device_printf(dev, "allocating USB transfers failed\n"); goto detach; } ue->ue_sc = sc; ue->ue_dev = dev; ue->ue_udev = uaa->device; ue->ue_mtx = &sc->sc_mtx; ue->ue_methods = &axe_ue_methods; error = uether_ifattach(ue); if (error) { device_printf(dev, "could not attach interface\n"); goto detach; } return (0); /* success */ detach: axe_detach(dev); return (ENXIO); /* failure */ } static int axe_detach(device_t dev) { struct axe_softc *sc = device_get_softc(dev); struct usb_ether *ue = &sc->sc_ue; usbd_transfer_unsetup(sc->sc_xfer, AXE_N_TRANSFER); uether_ifdetach(ue); mtx_destroy(&sc->sc_mtx); return (0); } #if (AXE_BULK_BUF_SIZE >= 0x10000) #error "Please update axe_bulk_read_callback()!" #endif static void axe_bulk_read_callback(struct usb_xfer *xfer, usb_error_t error) { struct axe_softc *sc = usbd_xfer_softc(xfer); struct usb_ether *ue = &sc->sc_ue; struct usb_page_cache *pc; int actlen; usbd_xfer_status(xfer, &actlen, NULL, NULL, NULL); switch (USB_GET_STATE(xfer)) { case USB_ST_TRANSFERRED: pc = usbd_xfer_get_frame(xfer, 0); axe_rx_frame(ue, pc, actlen); /* FALLTHROUGH */ case USB_ST_SETUP: tr_setup: usbd_xfer_set_frame_len(xfer, 0, usbd_xfer_max_len(xfer)); usbd_transfer_submit(xfer); uether_rxflush(ue); return; default: /* Error */ DPRINTF("bulk read error, %s\n", usbd_errstr(error)); if (error != USB_ERR_CANCELLED) { /* try to clear stall first */ usbd_xfer_set_stall(xfer); goto tr_setup; } return; } } static int axe_rx_frame(struct usb_ether *ue, struct usb_page_cache *pc, int actlen) { struct axe_softc *sc; struct axe_sframe_hdr hdr; struct axe_csum_hdr csum_hdr; int error, len, pos; sc = uether_getsc(ue); pos = 0; len = 0; error = 0; if ((sc->sc_flags & AXE_FLAG_STD_FRAME) != 0) { while (pos < actlen) { if ((int)(pos + sizeof(hdr)) > actlen) { /* too little data */ error = EINVAL; break; } usbd_copy_out(pc, pos, &hdr, sizeof(hdr)); if ((hdr.len ^ hdr.ilen) != sc->sc_lenmask) { /* we lost sync */ error = EINVAL; break; } pos += sizeof(hdr); len = le16toh(hdr.len); if (pos + len > actlen) { /* invalid length */ error = EINVAL; break; } axe_rxeof(ue, pc, pos, len, NULL); pos += len + (len % 2); } } else if ((sc->sc_flags & AXE_FLAG_CSUM_FRAME) != 0) { while (pos < actlen) { if ((int)(pos + sizeof(csum_hdr)) > actlen) { /* too little data */ error = EINVAL; break; } usbd_copy_out(pc, pos, &csum_hdr, sizeof(csum_hdr)); csum_hdr.len = le16toh(csum_hdr.len); csum_hdr.ilen = le16toh(csum_hdr.ilen); csum_hdr.cstatus = le16toh(csum_hdr.cstatus); if ((AXE_CSUM_RXBYTES(csum_hdr.len) ^ AXE_CSUM_RXBYTES(csum_hdr.ilen)) != sc->sc_lenmask) { /* we lost sync */ error = EINVAL; break; } /* * Get total transferred frame length including * checksum header. The length should be multiple * of 4. */ len = sizeof(csum_hdr) + AXE_CSUM_RXBYTES(csum_hdr.len); len = (len + 3) & ~3; if (pos + len > actlen) { /* invalid length */ error = EINVAL; break; } axe_rxeof(ue, pc, pos + sizeof(csum_hdr), AXE_CSUM_RXBYTES(csum_hdr.len), &csum_hdr); pos += len; } } else axe_rxeof(ue, pc, 0, actlen, NULL); if (error != 0) if_inc_counter(ue->ue_ifp, IFCOUNTER_IERRORS, 1); return (error); } static int axe_rxeof(struct usb_ether *ue, struct usb_page_cache *pc, unsigned int offset, unsigned int len, struct axe_csum_hdr *csum_hdr) { struct ifnet *ifp = ue->ue_ifp; struct mbuf *m; if (len < ETHER_HDR_LEN || len > MCLBYTES - ETHER_ALIGN) { if_inc_counter(ifp, IFCOUNTER_IERRORS, 1); return (EINVAL); } m = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR); if (m == NULL) { if_inc_counter(ifp, IFCOUNTER_IQDROPS, 1); return (ENOMEM); } m->m_len = m->m_pkthdr.len = MCLBYTES; m_adj(m, ETHER_ALIGN); usbd_copy_out(pc, offset, mtod(m, uint8_t *), len); if_inc_counter(ifp, IFCOUNTER_IPACKETS, 1); m->m_pkthdr.rcvif = ifp; m->m_pkthdr.len = m->m_len = len; if (csum_hdr != NULL && csum_hdr->cstatus & AXE_CSUM_HDR_L3_TYPE_IPV4) { if ((csum_hdr->cstatus & (AXE_CSUM_HDR_L4_CSUM_ERR | AXE_CSUM_HDR_L3_CSUM_ERR)) == 0) { m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED | CSUM_IP_VALID; if ((csum_hdr->cstatus & AXE_CSUM_HDR_L4_TYPE_MASK) == AXE_CSUM_HDR_L4_TYPE_TCP || (csum_hdr->cstatus & AXE_CSUM_HDR_L4_TYPE_MASK) == AXE_CSUM_HDR_L4_TYPE_UDP) { m->m_pkthdr.csum_flags |= CSUM_DATA_VALID | CSUM_PSEUDO_HDR; m->m_pkthdr.csum_data = 0xffff; } } } _IF_ENQUEUE(&ue->ue_rxq, m); return (0); } #if ((AXE_BULK_BUF_SIZE >= 0x10000) || (AXE_BULK_BUF_SIZE < (MCLBYTES+4))) #error "Please update axe_bulk_write_callback()!" #endif static void axe_bulk_write_callback(struct usb_xfer *xfer, usb_error_t error) { struct axe_softc *sc = usbd_xfer_softc(xfer); struct axe_sframe_hdr hdr; struct ifnet *ifp = uether_getifp(&sc->sc_ue); struct usb_page_cache *pc; struct mbuf *m; int nframes, pos; switch (USB_GET_STATE(xfer)) { case USB_ST_TRANSFERRED: DPRINTFN(11, "transfer complete\n"); ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; /* FALLTHROUGH */ case USB_ST_SETUP: tr_setup: if ((sc->sc_flags & AXE_FLAG_LINK) == 0 || (ifp->if_drv_flags & IFF_DRV_OACTIVE) != 0) { /* * Don't send anything if there is no link or * controller is busy. */ return; } for (nframes = 0; nframes < 16 && !IFQ_DRV_IS_EMPTY(&ifp->if_snd); nframes++) { IFQ_DRV_DEQUEUE(&ifp->if_snd, m); if (m == NULL) break; usbd_xfer_set_frame_offset(xfer, nframes * MCLBYTES, nframes); pos = 0; pc = usbd_xfer_get_frame(xfer, nframes); if (AXE_IS_178_FAMILY(sc)) { hdr.len = htole16(m->m_pkthdr.len); hdr.ilen = ~hdr.len; /* * If upper stack computed checksum, driver * should tell controller not to insert * computed checksum for checksum offloading * enabled controller. */ if (ifp->if_capabilities & IFCAP_TXCSUM) { if ((m->m_pkthdr.csum_flags & AXE_CSUM_FEATURES) != 0) hdr.len |= htole16( AXE_TX_CSUM_PSEUDO_HDR); else hdr.len |= htole16( AXE_TX_CSUM_DIS); } usbd_copy_in(pc, pos, &hdr, sizeof(hdr)); pos += sizeof(hdr); usbd_m_copy_in(pc, pos, m, 0, m->m_pkthdr.len); pos += m->m_pkthdr.len; if ((pos % 512) == 0) { hdr.len = 0; hdr.ilen = 0xffff; usbd_copy_in(pc, pos, &hdr, sizeof(hdr)); pos += sizeof(hdr); } } else { usbd_m_copy_in(pc, pos, m, 0, m->m_pkthdr.len); pos += m->m_pkthdr.len; } /* * XXX * Update TX packet counter here. This is not * correct way but it seems that there is no way * to know how many packets are sent at the end * of transfer because controller combines * multiple writes into single one if there is * room in TX buffer of controller. */ if_inc_counter(ifp, IFCOUNTER_OPACKETS, 1); /* * if there's a BPF listener, bounce a copy * of this frame to him: */ BPF_MTAP(ifp, m); m_freem(m); /* Set frame length. */ usbd_xfer_set_frame_len(xfer, nframes, pos); } if (nframes != 0) { usbd_xfer_set_frames(xfer, nframes); usbd_transfer_submit(xfer); ifp->if_drv_flags |= IFF_DRV_OACTIVE; } return; /* NOTREACHED */ default: /* Error */ DPRINTFN(11, "transfer error, %s\n", usbd_errstr(error)); if_inc_counter(ifp, IFCOUNTER_OERRORS, 1); ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; if (error != USB_ERR_CANCELLED) { /* try to clear stall first */ usbd_xfer_set_stall(xfer); goto tr_setup; } return; } } static void axe_tick(struct usb_ether *ue) { struct axe_softc *sc = uether_getsc(ue); struct mii_data *mii = GET_MII(sc); AXE_LOCK_ASSERT(sc, MA_OWNED); mii_tick(mii); if ((sc->sc_flags & AXE_FLAG_LINK) == 0) { axe_miibus_statchg(ue->ue_dev); if ((sc->sc_flags & AXE_FLAG_LINK) != 0) axe_start(ue); } } static void axe_start(struct usb_ether *ue) { struct axe_softc *sc = uether_getsc(ue); /* * start the USB transfers, if not already started: */ usbd_transfer_start(sc->sc_xfer[AXE_BULK_DT_RD]); usbd_transfer_start(sc->sc_xfer[AXE_BULK_DT_WR]); } static void axe_csum_cfg(struct usb_ether *ue) { struct axe_softc *sc; struct ifnet *ifp; uint16_t csum1, csum2; sc = uether_getsc(ue); AXE_LOCK_ASSERT(sc, MA_OWNED); if ((sc->sc_flags & AXE_FLAG_772B) != 0) { ifp = uether_getifp(ue); csum1 = 0; csum2 = 0; if ((ifp->if_capenable & IFCAP_TXCSUM) != 0) csum1 |= AXE_TXCSUM_IP | AXE_TXCSUM_TCP | AXE_TXCSUM_UDP; axe_cmd(sc, AXE_772B_CMD_WRITE_TXCSUM, csum2, csum1, NULL); csum1 = 0; csum2 = 0; if ((ifp->if_capenable & IFCAP_RXCSUM) != 0) csum1 |= AXE_RXCSUM_IP | AXE_RXCSUM_IPVE | AXE_RXCSUM_TCP | AXE_RXCSUM_UDP | AXE_RXCSUM_ICMP | AXE_RXCSUM_IGMP; axe_cmd(sc, AXE_772B_CMD_WRITE_RXCSUM, csum2, csum1, NULL); } } static void axe_init(struct usb_ether *ue) { struct axe_softc *sc = uether_getsc(ue); struct ifnet *ifp = uether_getifp(ue); uint16_t rxmode; AXE_LOCK_ASSERT(sc, MA_OWNED); if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) return; /* Cancel pending I/O */ axe_stop(ue); axe_reset(sc); /* Set MAC address and transmitter IPG values. */ if (AXE_IS_178_FAMILY(sc)) { axe_cmd(sc, AXE_178_CMD_WRITE_NODEID, 0, 0, IF_LLADDR(ifp)); axe_cmd(sc, AXE_178_CMD_WRITE_IPG012, sc->sc_ipgs[2], (sc->sc_ipgs[1] << 8) | (sc->sc_ipgs[0]), NULL); } else { axe_cmd(sc, AXE_172_CMD_WRITE_NODEID, 0, 0, IF_LLADDR(ifp)); axe_cmd(sc, AXE_172_CMD_WRITE_IPG0, 0, sc->sc_ipgs[0], NULL); axe_cmd(sc, AXE_172_CMD_WRITE_IPG1, 0, sc->sc_ipgs[1], NULL); axe_cmd(sc, AXE_172_CMD_WRITE_IPG2, 0, sc->sc_ipgs[2], NULL); } if (AXE_IS_178_FAMILY(sc)) { sc->sc_flags &= ~(AXE_FLAG_STD_FRAME | AXE_FLAG_CSUM_FRAME); if ((sc->sc_flags & AXE_FLAG_772B) != 0 && (ifp->if_capenable & IFCAP_RXCSUM) != 0) { sc->sc_lenmask = AXE_CSUM_HDR_LEN_MASK; sc->sc_flags |= AXE_FLAG_CSUM_FRAME; } else { sc->sc_lenmask = AXE_HDR_LEN_MASK; sc->sc_flags |= AXE_FLAG_STD_FRAME; } } /* Configure TX/RX checksum offloading. */ axe_csum_cfg(ue); if (sc->sc_flags & AXE_FLAG_772B) { /* AX88772B uses different maximum frame burst configuration. */ axe_cmd(sc, AXE_772B_CMD_RXCTL_WRITE_CFG, ax88772b_mfb_table[AX88772B_MFB_16K].threshold, ax88772b_mfb_table[AX88772B_MFB_16K].byte_cnt, NULL); } /* Enable receiver, set RX mode. */ rxmode = (AXE_RXCMD_MULTICAST | AXE_RXCMD_ENABLE); if (AXE_IS_178_FAMILY(sc)) { if (sc->sc_flags & AXE_FLAG_772B) { /* * Select RX header format type 1. Aligning IP * header on 4 byte boundary is not needed when * checksum offloading feature is not used * because we always copy the received frame in * RX handler. When RX checksum offloading is * active, aligning IP header is required to * reflect actual frame length including RX * header size. */ rxmode |= AXE_772B_RXCMD_HDR_TYPE_1; if ((ifp->if_capenable & IFCAP_RXCSUM) != 0) rxmode |= AXE_772B_RXCMD_IPHDR_ALIGN; } else { /* * Default Rx buffer size is too small to get * maximum performance. */ rxmode |= AXE_178_RXCMD_MFB_16384; } } else { rxmode |= AXE_172_RXCMD_UNICAST; } /* If we want promiscuous mode, set the allframes bit. */ if (ifp->if_flags & IFF_PROMISC) rxmode |= AXE_RXCMD_PROMISC; if (ifp->if_flags & IFF_BROADCAST) rxmode |= AXE_RXCMD_BROADCAST; axe_cmd(sc, AXE_CMD_RXCTL_WRITE, 0, rxmode, NULL); /* Load the multicast filter. */ axe_setmulti(ue); usbd_xfer_set_stall(sc->sc_xfer[AXE_BULK_DT_WR]); ifp->if_drv_flags |= IFF_DRV_RUNNING; /* Switch to selected media. */ axe_ifmedia_upd(ifp); } static void axe_setpromisc(struct usb_ether *ue) { struct axe_softc *sc = uether_getsc(ue); struct ifnet *ifp = uether_getifp(ue); uint16_t rxmode; axe_cmd(sc, AXE_CMD_RXCTL_READ, 0, 0, &rxmode); rxmode = le16toh(rxmode); if (ifp->if_flags & IFF_PROMISC) { rxmode |= AXE_RXCMD_PROMISC; } else { rxmode &= ~AXE_RXCMD_PROMISC; } axe_cmd(sc, AXE_CMD_RXCTL_WRITE, 0, rxmode, NULL); axe_setmulti(ue); } static void axe_stop(struct usb_ether *ue) { struct axe_softc *sc = uether_getsc(ue); struct ifnet *ifp = uether_getifp(ue); AXE_LOCK_ASSERT(sc, MA_OWNED); ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); sc->sc_flags &= ~AXE_FLAG_LINK; /* * stop all the transfers, if not already stopped: */ usbd_transfer_stop(sc->sc_xfer[AXE_BULK_DT_WR]); usbd_transfer_stop(sc->sc_xfer[AXE_BULK_DT_RD]); } static int axe_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data) { struct usb_ether *ue = ifp->if_softc; struct axe_softc *sc; struct ifreq *ifr; int error, mask, reinit; sc = uether_getsc(ue); ifr = (struct ifreq *)data; error = 0; reinit = 0; if (cmd == SIOCSIFCAP) { AXE_LOCK(sc); mask = ifr->ifr_reqcap ^ ifp->if_capenable; if ((mask & IFCAP_TXCSUM) != 0 && (ifp->if_capabilities & IFCAP_TXCSUM) != 0) { ifp->if_capenable ^= IFCAP_TXCSUM; if ((ifp->if_capenable & IFCAP_TXCSUM) != 0) ifp->if_hwassist |= AXE_CSUM_FEATURES; else ifp->if_hwassist &= ~AXE_CSUM_FEATURES; reinit++; } if ((mask & IFCAP_RXCSUM) != 0 && (ifp->if_capabilities & IFCAP_RXCSUM) != 0) { ifp->if_capenable ^= IFCAP_RXCSUM; reinit++; } if (reinit > 0 && ifp->if_drv_flags & IFF_DRV_RUNNING) ifp->if_drv_flags &= ~IFF_DRV_RUNNING; else reinit = 0; AXE_UNLOCK(sc); if (reinit > 0) uether_init(ue); } else error = uether_ioctl(ifp, cmd, data); return (error); } Index: head/sys/dev/usb/net/if_axge.c =================================================================== --- head/sys/dev/usb/net/if_axge.c (revision 351249) +++ head/sys/dev/usb/net/if_axge.c (revision 351250) @@ -1,1061 +1,1067 @@ /*- * SPDX-License-Identifier: BSD-2-Clause-FreeBSD * * Copyright (c) 2013-2014 Kevin Lo * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. */ #include __FBSDID("$FreeBSD$"); /* * ASIX Electronics AX88178A/AX88179 USB 2.0/3.0 gigabit ethernet driver. */ #include #include #include #include #include #include #include #include #include #include #include #include #include #include +#include +#include +#include + #include #include #include #include "usbdevs.h" #define USB_DEBUG_VAR axge_debug #include #include #include #include + +#include "miibus_if.h" /* * Various supported device vendors/products. */ static const STRUCT_USB_HOST_ID axge_devs[] = { #define AXGE_DEV(v,p) { USB_VP(USB_VENDOR_##v, USB_PRODUCT_##v##_##p) } AXGE_DEV(ASIX, AX88178A), AXGE_DEV(ASIX, AX88179), AXGE_DEV(DLINK, DUB1312), AXGE_DEV(LENOVO, GIGALAN), AXGE_DEV(SITECOMEU, LN032), #undef AXGE_DEV }; static const struct { uint8_t ctrl; uint8_t timer_l; uint8_t timer_h; uint8_t size; uint8_t ifg; } __packed axge_bulk_size[] = { { 7, 0x4f, 0x00, 0x12, 0xff }, { 7, 0x20, 0x03, 0x16, 0xff }, { 7, 0xae, 0x07, 0x18, 0xff }, { 7, 0xcc, 0x4c, 0x18, 0x08 } }; /* prototypes */ static device_probe_t axge_probe; static device_attach_t axge_attach; static device_detach_t axge_detach; static usb_callback_t axge_bulk_read_callback; static usb_callback_t axge_bulk_write_callback; static miibus_readreg_t axge_miibus_readreg; static miibus_writereg_t axge_miibus_writereg; static miibus_statchg_t axge_miibus_statchg; static uether_fn_t axge_attach_post; static uether_fn_t axge_init; static uether_fn_t axge_stop; static uether_fn_t axge_start; static uether_fn_t axge_tick; static uether_fn_t axge_rxfilter; static int axge_read_mem(struct axge_softc *, uint8_t, uint16_t, uint16_t, void *, int); static void axge_write_mem(struct axge_softc *, uint8_t, uint16_t, uint16_t, void *, int); static uint8_t axge_read_cmd_1(struct axge_softc *, uint8_t, uint16_t); static uint16_t axge_read_cmd_2(struct axge_softc *, uint8_t, uint16_t, uint16_t); static void axge_write_cmd_1(struct axge_softc *, uint8_t, uint16_t, uint8_t); static void axge_write_cmd_2(struct axge_softc *, uint8_t, uint16_t, uint16_t, uint16_t); static void axge_chip_init(struct axge_softc *); static void axge_reset(struct axge_softc *); static int axge_attach_post_sub(struct usb_ether *); static int axge_ifmedia_upd(struct ifnet *); static void axge_ifmedia_sts(struct ifnet *, struct ifmediareq *); static int axge_ioctl(struct ifnet *, u_long, caddr_t); static void axge_rx_frame(struct usb_ether *, struct usb_page_cache *, int); static void axge_rxeof(struct usb_ether *, struct usb_page_cache *, unsigned int, unsigned int, uint32_t); static void axge_csum_cfg(struct usb_ether *); #define AXGE_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP) #ifdef USB_DEBUG static int axge_debug = 0; static SYSCTL_NODE(_hw_usb, OID_AUTO, axge, CTLFLAG_RW, 0, "USB axge"); SYSCTL_INT(_hw_usb_axge, OID_AUTO, debug, CTLFLAG_RWTUN, &axge_debug, 0, "Debug level"); #endif static const struct usb_config axge_config[AXGE_N_TRANSFER] = { [AXGE_BULK_DT_WR] = { .type = UE_BULK, .endpoint = UE_ADDR_ANY, .direction = UE_DIR_OUT, .frames = AXGE_N_FRAMES, .bufsize = AXGE_N_FRAMES * MCLBYTES, .flags = {.pipe_bof = 1,.force_short_xfer = 1,}, .callback = axge_bulk_write_callback, .timeout = 10000, /* 10 seconds */ }, [AXGE_BULK_DT_RD] = { .type = UE_BULK, .endpoint = UE_ADDR_ANY, .direction = UE_DIR_IN, .bufsize = 65536, .flags = {.pipe_bof = 1,.short_xfer_ok = 1,}, .callback = axge_bulk_read_callback, .timeout = 0, /* no timeout */ }, }; static device_method_t axge_methods[] = { /* Device interface. */ DEVMETHOD(device_probe, axge_probe), DEVMETHOD(device_attach, axge_attach), DEVMETHOD(device_detach, axge_detach), /* MII interface. */ DEVMETHOD(miibus_readreg, axge_miibus_readreg), DEVMETHOD(miibus_writereg, axge_miibus_writereg), DEVMETHOD(miibus_statchg, axge_miibus_statchg), DEVMETHOD_END }; static driver_t axge_driver = { .name = "axge", .methods = axge_methods, .size = sizeof(struct axge_softc), }; static devclass_t axge_devclass; DRIVER_MODULE(axge, uhub, axge_driver, axge_devclass, NULL, NULL); DRIVER_MODULE(miibus, axge, miibus_driver, miibus_devclass, NULL, NULL); MODULE_DEPEND(axge, uether, 1, 1, 1); MODULE_DEPEND(axge, usb, 1, 1, 1); MODULE_DEPEND(axge, ether, 1, 1, 1); MODULE_DEPEND(axge, miibus, 1, 1, 1); MODULE_VERSION(axge, 1); USB_PNP_HOST_INFO(axge_devs); static const struct usb_ether_methods axge_ue_methods = { .ue_attach_post = axge_attach_post, .ue_attach_post_sub = axge_attach_post_sub, .ue_start = axge_start, .ue_init = axge_init, .ue_stop = axge_stop, .ue_tick = axge_tick, .ue_setmulti = axge_rxfilter, .ue_setpromisc = axge_rxfilter, .ue_mii_upd = axge_ifmedia_upd, .ue_mii_sts = axge_ifmedia_sts, }; static int axge_read_mem(struct axge_softc *sc, uint8_t cmd, uint16_t index, uint16_t val, void *buf, int len) { struct usb_device_request req; AXGE_LOCK_ASSERT(sc, MA_OWNED); req.bmRequestType = UT_READ_VENDOR_DEVICE; req.bRequest = cmd; USETW(req.wValue, val); USETW(req.wIndex, index); USETW(req.wLength, len); return (uether_do_request(&sc->sc_ue, &req, buf, 1000)); } static void axge_write_mem(struct axge_softc *sc, uint8_t cmd, uint16_t index, uint16_t val, void *buf, int len) { struct usb_device_request req; AXGE_LOCK_ASSERT(sc, MA_OWNED); req.bmRequestType = UT_WRITE_VENDOR_DEVICE; req.bRequest = cmd; USETW(req.wValue, val); USETW(req.wIndex, index); USETW(req.wLength, len); if (uether_do_request(&sc->sc_ue, &req, buf, 1000)) { /* Error ignored. */ } } static uint8_t axge_read_cmd_1(struct axge_softc *sc, uint8_t cmd, uint16_t reg) { uint8_t val; axge_read_mem(sc, cmd, 1, reg, &val, 1); return (val); } static uint16_t axge_read_cmd_2(struct axge_softc *sc, uint8_t cmd, uint16_t index, uint16_t reg) { uint8_t val[2]; axge_read_mem(sc, cmd, index, reg, &val, 2); return (UGETW(val)); } static void axge_write_cmd_1(struct axge_softc *sc, uint8_t cmd, uint16_t reg, uint8_t val) { axge_write_mem(sc, cmd, 1, reg, &val, 1); } static void axge_write_cmd_2(struct axge_softc *sc, uint8_t cmd, uint16_t index, uint16_t reg, uint16_t val) { uint8_t temp[2]; USETW(temp, val); axge_write_mem(sc, cmd, index, reg, &temp, 2); } static int axge_miibus_readreg(device_t dev, int phy, int reg) { struct axge_softc *sc; uint16_t val; int locked; sc = device_get_softc(dev); locked = mtx_owned(&sc->sc_mtx); if (!locked) AXGE_LOCK(sc); val = axge_read_cmd_2(sc, AXGE_ACCESS_PHY, reg, phy); if (!locked) AXGE_UNLOCK(sc); return (val); } static int axge_miibus_writereg(device_t dev, int phy, int reg, int val) { struct axge_softc *sc; int locked; sc = device_get_softc(dev); locked = mtx_owned(&sc->sc_mtx); if (!locked) AXGE_LOCK(sc); axge_write_cmd_2(sc, AXGE_ACCESS_PHY, reg, phy, val); if (!locked) AXGE_UNLOCK(sc); return (0); } static void axge_miibus_statchg(device_t dev) { struct axge_softc *sc; struct mii_data *mii; struct ifnet *ifp; uint8_t link_status, tmp[5]; uint16_t val; int locked; sc = device_get_softc(dev); mii = GET_MII(sc); locked = mtx_owned(&sc->sc_mtx); if (!locked) AXGE_LOCK(sc); ifp = uether_getifp(&sc->sc_ue); if (mii == NULL || ifp == NULL || (ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) goto done; sc->sc_flags &= ~AXGE_FLAG_LINK; if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) == (IFM_ACTIVE | IFM_AVALID)) { switch (IFM_SUBTYPE(mii->mii_media_active)) { case IFM_10_T: case IFM_100_TX: case IFM_1000_T: sc->sc_flags |= AXGE_FLAG_LINK; break; default: break; } } /* Lost link, do nothing. */ if ((sc->sc_flags & AXGE_FLAG_LINK) == 0) goto done; link_status = axge_read_cmd_1(sc, AXGE_ACCESS_MAC, AXGE_PLSR); val = 0; if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0) { val |= MSR_FD; if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_TXPAUSE) != 0) val |= MSR_TFC; if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_RXPAUSE) != 0) val |= MSR_RFC; } val |= MSR_RE; switch (IFM_SUBTYPE(mii->mii_media_active)) { case IFM_1000_T: val |= MSR_GM | MSR_EN_125MHZ; if (link_status & PLSR_USB_SS) memcpy(tmp, &axge_bulk_size[0], 5); else if (link_status & PLSR_USB_HS) memcpy(tmp, &axge_bulk_size[1], 5); else memcpy(tmp, &axge_bulk_size[3], 5); break; case IFM_100_TX: val |= MSR_PS; if (link_status & (PLSR_USB_SS | PLSR_USB_HS)) memcpy(tmp, &axge_bulk_size[2], 5); else memcpy(tmp, &axge_bulk_size[3], 5); break; case IFM_10_T: memcpy(tmp, &axge_bulk_size[3], 5); break; } /* Rx bulk configuration. */ axge_write_mem(sc, AXGE_ACCESS_MAC, 5, AXGE_RX_BULKIN_QCTRL, tmp, 5); axge_write_cmd_2(sc, AXGE_ACCESS_MAC, 2, AXGE_MSR, val); done: if (!locked) AXGE_UNLOCK(sc); } static void axge_chip_init(struct axge_softc *sc) { /* Power up ethernet PHY. */ axge_write_cmd_2(sc, AXGE_ACCESS_MAC, 2, AXGE_EPPRCR, 0); axge_write_cmd_2(sc, AXGE_ACCESS_MAC, 2, AXGE_EPPRCR, EPPRCR_IPRL); uether_pause(&sc->sc_ue, hz / 4); axge_write_cmd_1(sc, AXGE_ACCESS_MAC, AXGE_CLK_SELECT, AXGE_CLK_SELECT_ACS | AXGE_CLK_SELECT_BCS); uether_pause(&sc->sc_ue, hz / 10); } static void axge_reset(struct axge_softc *sc) { struct usb_config_descriptor *cd; usb_error_t err; cd = usbd_get_config_descriptor(sc->sc_ue.ue_udev); err = usbd_req_set_config(sc->sc_ue.ue_udev, &sc->sc_mtx, cd->bConfigurationValue); if (err) DPRINTF("reset failed (ignored)\n"); /* Wait a little while for the chip to get its brains in order. */ uether_pause(&sc->sc_ue, hz / 100); /* Reinitialize controller to achieve full reset. */ axge_chip_init(sc); } static void axge_attach_post(struct usb_ether *ue) { struct axge_softc *sc; sc = uether_getsc(ue); /* Initialize controller and get station address. */ axge_chip_init(sc); axge_read_mem(sc, AXGE_ACCESS_MAC, ETHER_ADDR_LEN, AXGE_NIDR, ue->ue_eaddr, ETHER_ADDR_LEN); } static int axge_attach_post_sub(struct usb_ether *ue) { struct axge_softc *sc; struct ifnet *ifp; int error; sc = uether_getsc(ue); ifp = ue->ue_ifp; ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; ifp->if_start = uether_start; ifp->if_ioctl = axge_ioctl; ifp->if_init = uether_init; IFQ_SET_MAXLEN(&ifp->if_snd, ifqmaxlen); ifp->if_snd.ifq_drv_maxlen = ifqmaxlen; IFQ_SET_READY(&ifp->if_snd); ifp->if_capabilities |= IFCAP_VLAN_MTU | IFCAP_TXCSUM | IFCAP_RXCSUM; ifp->if_hwassist = AXGE_CSUM_FEATURES; ifp->if_capenable = ifp->if_capabilities; mtx_lock(&Giant); error = mii_attach(ue->ue_dev, &ue->ue_miibus, ifp, uether_ifmedia_upd, ue->ue_methods->ue_mii_sts, BMSR_DEFCAPMASK, AXGE_PHY_ADDR, MII_OFFSET_ANY, MIIF_DOPAUSE); mtx_unlock(&Giant); return (error); } /* * Set media options. */ static int axge_ifmedia_upd(struct ifnet *ifp) { struct axge_softc *sc; struct mii_data *mii; struct mii_softc *miisc; int error; sc = ifp->if_softc; mii = GET_MII(sc); AXGE_LOCK_ASSERT(sc, MA_OWNED); LIST_FOREACH(miisc, &mii->mii_phys, mii_list) PHY_RESET(miisc); error = mii_mediachg(mii); return (error); } /* * Report current media status. */ static void axge_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) { struct axge_softc *sc; struct mii_data *mii; sc = ifp->if_softc; mii = GET_MII(sc); AXGE_LOCK(sc); mii_pollstat(mii); ifmr->ifm_active = mii->mii_media_active; ifmr->ifm_status = mii->mii_media_status; AXGE_UNLOCK(sc); } /* * Probe for a AX88179 chip. */ static int axge_probe(device_t dev) { struct usb_attach_arg *uaa; uaa = device_get_ivars(dev); if (uaa->usb_mode != USB_MODE_HOST) return (ENXIO); if (uaa->info.bConfigIndex != AXGE_CONFIG_IDX) return (ENXIO); if (uaa->info.bIfaceIndex != AXGE_IFACE_IDX) return (ENXIO); return (usbd_lookup_id_by_uaa(axge_devs, sizeof(axge_devs), uaa)); } /* * Attach the interface. Allocate softc structures, do ifmedia * setup and ethernet/BPF attach. */ static int axge_attach(device_t dev) { struct usb_attach_arg *uaa; struct axge_softc *sc; struct usb_ether *ue; uint8_t iface_index; int error; uaa = device_get_ivars(dev); sc = device_get_softc(dev); ue = &sc->sc_ue; device_set_usb_desc(dev); mtx_init(&sc->sc_mtx, device_get_nameunit(dev), NULL, MTX_DEF); iface_index = AXGE_IFACE_IDX; error = usbd_transfer_setup(uaa->device, &iface_index, sc->sc_xfer, axge_config, AXGE_N_TRANSFER, sc, &sc->sc_mtx); if (error) { device_printf(dev, "allocating USB transfers failed\n"); mtx_destroy(&sc->sc_mtx); return (ENXIO); } ue->ue_sc = sc; ue->ue_dev = dev; ue->ue_udev = uaa->device; ue->ue_mtx = &sc->sc_mtx; ue->ue_methods = &axge_ue_methods; error = uether_ifattach(ue); if (error) { device_printf(dev, "could not attach interface\n"); goto detach; } return (0); /* success */ detach: axge_detach(dev); return (ENXIO); /* failure */ } static int axge_detach(device_t dev) { struct axge_softc *sc; struct usb_ether *ue; uint16_t val; sc = device_get_softc(dev); ue = &sc->sc_ue; if (device_is_attached(dev)) { /* wait for any post attach or other command to complete */ usb_proc_drain(&ue->ue_tq); AXGE_LOCK(sc); /* * XXX * ether_ifdetach(9) should be called first. */ axge_stop(ue); /* Force bulk-in to return a zero-length USB packet. */ val = axge_read_cmd_2(sc, AXGE_ACCESS_MAC, 2, AXGE_EPPRCR); val |= EPPRCR_BZ | EPPRCR_IPRL; axge_write_cmd_2(sc, AXGE_ACCESS_MAC, 2, AXGE_EPPRCR, val); /* Change clock. */ axge_write_cmd_1(sc, AXGE_ACCESS_MAC, AXGE_CLK_SELECT, 0); /* Disable MAC. */ axge_write_cmd_2(sc, AXGE_ACCESS_MAC, 2, AXGE_RCR, 0); AXGE_UNLOCK(sc); } usbd_transfer_unsetup(sc->sc_xfer, AXGE_N_TRANSFER); uether_ifdetach(ue); mtx_destroy(&sc->sc_mtx); return (0); } static void axge_bulk_read_callback(struct usb_xfer *xfer, usb_error_t error) { struct axge_softc *sc; struct usb_ether *ue; struct usb_page_cache *pc; int actlen; sc = usbd_xfer_softc(xfer); ue = &sc->sc_ue; usbd_xfer_status(xfer, &actlen, NULL, NULL, NULL); switch (USB_GET_STATE(xfer)) { case USB_ST_TRANSFERRED: pc = usbd_xfer_get_frame(xfer, 0); axge_rx_frame(ue, pc, actlen); /* FALLTHROUGH */ case USB_ST_SETUP: tr_setup: usbd_xfer_set_frame_len(xfer, 0, usbd_xfer_max_len(xfer)); usbd_transfer_submit(xfer); uether_rxflush(ue); break; default: if (error != USB_ERR_CANCELLED) { usbd_xfer_set_stall(xfer); goto tr_setup; } break; } } static void axge_bulk_write_callback(struct usb_xfer *xfer, usb_error_t error) { struct axge_softc *sc; struct ifnet *ifp; struct usb_page_cache *pc; struct mbuf *m; struct axge_frame_txhdr txhdr; int nframes, pos; sc = usbd_xfer_softc(xfer); ifp = uether_getifp(&sc->sc_ue); switch (USB_GET_STATE(xfer)) { case USB_ST_TRANSFERRED: ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; /* FALLTHROUGH */ case USB_ST_SETUP: tr_setup: if ((sc->sc_flags & AXGE_FLAG_LINK) == 0 || (ifp->if_drv_flags & IFF_DRV_OACTIVE) != 0) { /* * Don't send anything if there is no link or * controller is busy. */ return; } for (nframes = 0; nframes < AXGE_N_FRAMES && !IFQ_DRV_IS_EMPTY(&ifp->if_snd); nframes++) { IFQ_DRV_DEQUEUE(&ifp->if_snd, m); if (m == NULL) break; usbd_xfer_set_frame_offset(xfer, nframes * MCLBYTES, nframes); pc = usbd_xfer_get_frame(xfer, nframes); txhdr.mss = 0; txhdr.len = htole32(AXGE_TXBYTES(m->m_pkthdr.len)); if ((ifp->if_capenable & IFCAP_TXCSUM) != 0 && (m->m_pkthdr.csum_flags & AXGE_CSUM_FEATURES) == 0) txhdr.len |= htole32(AXGE_CSUM_DISABLE); pos = 0; usbd_copy_in(pc, pos, &txhdr, sizeof(txhdr)); pos += sizeof(txhdr); usbd_m_copy_in(pc, pos, m, 0, m->m_pkthdr.len); pos += m->m_pkthdr.len; /* * if there's a BPF listener, bounce a copy * of this frame to him: */ BPF_MTAP(ifp, m); m_freem(m); /* Set frame length. */ usbd_xfer_set_frame_len(xfer, nframes, pos); } if (nframes != 0) { /* * XXX * Update TX packet counter here. This is not * correct way but it seems that there is no way * to know how many packets are sent at the end * of transfer because controller combines * multiple writes into single one if there is * room in TX buffer of controller. */ if_inc_counter(ifp, IFCOUNTER_OPACKETS, nframes); usbd_xfer_set_frames(xfer, nframes); usbd_transfer_submit(xfer); ifp->if_drv_flags |= IFF_DRV_OACTIVE; } return; /* NOTREACHED */ default: if_inc_counter(ifp, IFCOUNTER_OERRORS, 1); ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; if (error != USB_ERR_CANCELLED) { usbd_xfer_set_stall(xfer); goto tr_setup; } return; } } static void axge_tick(struct usb_ether *ue) { struct axge_softc *sc; struct mii_data *mii; sc = uether_getsc(ue); mii = GET_MII(sc); AXGE_LOCK_ASSERT(sc, MA_OWNED); mii_tick(mii); } static void axge_rxfilter(struct usb_ether *ue) { struct axge_softc *sc; struct ifnet *ifp; struct ifmultiaddr *ifma; uint32_t h; uint16_t rxmode; uint8_t hashtbl[8] = { 0, 0, 0, 0, 0, 0, 0, 0 }; sc = uether_getsc(ue); ifp = uether_getifp(ue); h = 0; AXGE_LOCK_ASSERT(sc, MA_OWNED); /* * Configure RX settings. * Don't set RCR_IPE(IP header alignment on 32bit boundary) to disable * inserting extra padding bytes. This wastes ethernet to USB host * bandwidth as well as complicating RX handling logic. Current USB * framework requires copying RX frames to mbufs so there is no need * to worry about alignment. */ rxmode = RCR_DROP_CRCERR | RCR_START; if (ifp->if_flags & IFF_BROADCAST) rxmode |= RCR_ACPT_BCAST; if (ifp->if_flags & (IFF_ALLMULTI | IFF_PROMISC)) { if (ifp->if_flags & IFF_PROMISC) rxmode |= RCR_PROMISC; rxmode |= RCR_ACPT_ALL_MCAST; axge_write_cmd_2(sc, AXGE_ACCESS_MAC, 2, AXGE_RCR, rxmode); return; } rxmode |= RCR_ACPT_MCAST; if_maddr_rlock(ifp); CK_STAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { if (ifma->ifma_addr->sa_family != AF_LINK) continue; h = ether_crc32_be(LLADDR((struct sockaddr_dl *) ifma->ifma_addr), ETHER_ADDR_LEN) >> 26; hashtbl[h / 8] |= 1 << (h % 8); } if_maddr_runlock(ifp); axge_write_mem(sc, AXGE_ACCESS_MAC, 8, AXGE_MFA, (void *)&hashtbl, 8); axge_write_cmd_2(sc, AXGE_ACCESS_MAC, 2, AXGE_RCR, rxmode); } static void axge_start(struct usb_ether *ue) { struct axge_softc *sc; sc = uether_getsc(ue); /* * Start the USB transfers, if not already started. */ usbd_transfer_start(sc->sc_xfer[AXGE_BULK_DT_RD]); usbd_transfer_start(sc->sc_xfer[AXGE_BULK_DT_WR]); } static void axge_init(struct usb_ether *ue) { struct axge_softc *sc; struct ifnet *ifp; sc = uether_getsc(ue); ifp = uether_getifp(ue); AXGE_LOCK_ASSERT(sc, MA_OWNED); if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) return; /* * Cancel pending I/O and free all RX/TX buffers. */ axge_stop(ue); axge_reset(sc); /* Set MAC address. */ axge_write_mem(sc, AXGE_ACCESS_MAC, ETHER_ADDR_LEN, AXGE_NIDR, IF_LLADDR(ifp), ETHER_ADDR_LEN); axge_write_cmd_1(sc, AXGE_ACCESS_MAC, AXGE_PWLLR, 0x34); axge_write_cmd_1(sc, AXGE_ACCESS_MAC, AXGE_PWLHR, 0x52); /* Configure TX/RX checksum offloading. */ axge_csum_cfg(ue); /* Configure RX filters. */ axge_rxfilter(ue); /* * XXX * Controller supports wakeup on link change detection, * magic packet and wakeup frame recpetion. But it seems * there is no framework for USB ethernet suspend/wakeup. * Disable all wakeup functions. */ axge_write_cmd_1(sc, AXGE_ACCESS_MAC, AXGE_MMSR, 0); (void)axge_read_cmd_1(sc, AXGE_ACCESS_MAC, AXGE_MMSR); /* Configure default medium type. */ axge_write_cmd_2(sc, AXGE_ACCESS_MAC, 2, AXGE_MSR, MSR_GM | MSR_FD | MSR_RFC | MSR_TFC | MSR_RE); usbd_xfer_set_stall(sc->sc_xfer[AXGE_BULK_DT_WR]); ifp->if_drv_flags |= IFF_DRV_RUNNING; /* Switch to selected media. */ axge_ifmedia_upd(ifp); } static void axge_stop(struct usb_ether *ue) { struct axge_softc *sc; struct ifnet *ifp; uint16_t val; sc = uether_getsc(ue); ifp = uether_getifp(ue); AXGE_LOCK_ASSERT(sc, MA_OWNED); val = axge_read_cmd_2(sc, AXGE_ACCESS_MAC, 2, AXGE_MSR); val &= ~MSR_RE; axge_write_cmd_2(sc, AXGE_ACCESS_MAC, 2, AXGE_MSR, val); if (ifp != NULL) ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); sc->sc_flags &= ~AXGE_FLAG_LINK; /* * Stop all the transfers, if not already stopped: */ usbd_transfer_stop(sc->sc_xfer[AXGE_BULK_DT_WR]); usbd_transfer_stop(sc->sc_xfer[AXGE_BULK_DT_RD]); } static int axge_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data) { struct usb_ether *ue; struct axge_softc *sc; struct ifreq *ifr; int error, mask, reinit; ue = ifp->if_softc; sc = uether_getsc(ue); ifr = (struct ifreq *)data; error = 0; reinit = 0; if (cmd == SIOCSIFCAP) { AXGE_LOCK(sc); mask = ifr->ifr_reqcap ^ ifp->if_capenable; if ((mask & IFCAP_TXCSUM) != 0 && (ifp->if_capabilities & IFCAP_TXCSUM) != 0) { ifp->if_capenable ^= IFCAP_TXCSUM; if ((ifp->if_capenable & IFCAP_TXCSUM) != 0) ifp->if_hwassist |= AXGE_CSUM_FEATURES; else ifp->if_hwassist &= ~AXGE_CSUM_FEATURES; reinit++; } if ((mask & IFCAP_RXCSUM) != 0 && (ifp->if_capabilities & IFCAP_RXCSUM) != 0) { ifp->if_capenable ^= IFCAP_RXCSUM; reinit++; } if (reinit > 0 && ifp->if_drv_flags & IFF_DRV_RUNNING) ifp->if_drv_flags &= ~IFF_DRV_RUNNING; else reinit = 0; AXGE_UNLOCK(sc); if (reinit > 0) uether_init(ue); } else error = uether_ioctl(ifp, cmd, data); return (error); } static void axge_rx_frame(struct usb_ether *ue, struct usb_page_cache *pc, int actlen) { struct axge_frame_rxhdr pkt_hdr; uint32_t rxhdr; uint32_t pos; uint32_t pkt_cnt, pkt_end; uint32_t hdr_off; uint32_t pktlen; /* verify we have enough data */ if (actlen < (int)sizeof(rxhdr)) return; pos = 0; usbd_copy_out(pc, actlen - sizeof(rxhdr), &rxhdr, sizeof(rxhdr)); rxhdr = le32toh(rxhdr); pkt_cnt = rxhdr & 0xFFFF; hdr_off = pkt_end = (rxhdr >> 16) & 0xFFFF; /* * <----------------------- actlen ------------------------> * [frame #0]...[frame #N][pkt_hdr #0]...[pkt_hdr #N][rxhdr] * Each RX frame would be aligned on 8 bytes boundary. If * RCR_IPE bit is set in AXGE_RCR register, there would be 2 * padding bytes and 6 dummy bytes(as the padding also should * be aligned on 8 bytes boundary) for each RX frame to align * IP header on 32bits boundary. Driver don't set RCR_IPE bit * of AXGE_RCR register, so there should be no padding bytes * which simplifies RX logic a lot. */ while (pkt_cnt--) { /* verify the header offset */ if ((int)(hdr_off + sizeof(pkt_hdr)) > actlen) { DPRINTF("End of packet headers\n"); break; } usbd_copy_out(pc, hdr_off, &pkt_hdr, sizeof(pkt_hdr)); pkt_hdr.status = le32toh(pkt_hdr.status); pktlen = AXGE_RXBYTES(pkt_hdr.status); if (pos + pktlen > pkt_end) { DPRINTF("Data position reached end\n"); break; } if (AXGE_RX_ERR(pkt_hdr.status) != 0) { DPRINTF("Dropped a packet\n"); if_inc_counter(ue->ue_ifp, IFCOUNTER_IERRORS, 1); } else axge_rxeof(ue, pc, pos, pktlen, pkt_hdr.status); pos += (pktlen + 7) & ~7; hdr_off += sizeof(pkt_hdr); } } static void axge_rxeof(struct usb_ether *ue, struct usb_page_cache *pc, unsigned int offset, unsigned int len, uint32_t status) { struct ifnet *ifp; struct mbuf *m; ifp = ue->ue_ifp; if (len < ETHER_HDR_LEN || len > MCLBYTES - ETHER_ALIGN) { if_inc_counter(ifp, IFCOUNTER_IERRORS, 1); return; } if (len > MHLEN - ETHER_ALIGN) m = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR); else m = m_gethdr(M_NOWAIT, MT_DATA); if (m == NULL) { if_inc_counter(ifp, IFCOUNTER_IQDROPS, 1); return; } m->m_pkthdr.rcvif = ifp; m->m_len = m->m_pkthdr.len = len; m->m_data += ETHER_ALIGN; usbd_copy_out(pc, offset, mtod(m, uint8_t *), len); if ((ifp->if_capenable & IFCAP_RXCSUM) != 0) { if ((status & AXGE_RX_L3_CSUM_ERR) == 0 && (status & AXGE_RX_L3_TYPE_MASK) == AXGE_RX_L3_TYPE_IPV4) m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED | CSUM_IP_VALID; if ((status & AXGE_RX_L4_CSUM_ERR) == 0 && ((status & AXGE_RX_L4_TYPE_MASK) == AXGE_RX_L4_TYPE_UDP || (status & AXGE_RX_L4_TYPE_MASK) == AXGE_RX_L4_TYPE_TCP)) { m->m_pkthdr.csum_flags |= CSUM_DATA_VALID | CSUM_PSEUDO_HDR; m->m_pkthdr.csum_data = 0xffff; } } if_inc_counter(ifp, IFCOUNTER_IPACKETS, 1); _IF_ENQUEUE(&ue->ue_rxq, m); } static void axge_csum_cfg(struct usb_ether *ue) { struct axge_softc *sc; struct ifnet *ifp; uint8_t csum; sc = uether_getsc(ue); AXGE_LOCK_ASSERT(sc, MA_OWNED); ifp = uether_getifp(ue); csum = 0; if ((ifp->if_capenable & IFCAP_TXCSUM) != 0) csum |= CTCR_IP | CTCR_TCP | CTCR_UDP; axge_write_cmd_1(sc, AXGE_ACCESS_MAC, AXGE_CTCR, csum); csum = 0; if ((ifp->if_capenable & IFCAP_RXCSUM) != 0) csum |= CRCR_IP | CRCR_TCP | CRCR_UDP; axge_write_cmd_1(sc, AXGE_ACCESS_MAC, AXGE_CRCR, csum); } Index: head/sys/dev/usb/net/if_mos.c =================================================================== --- head/sys/dev/usb/net/if_mos.c (revision 351249) +++ head/sys/dev/usb/net/if_mos.c (revision 351250) @@ -1,1032 +1,1038 @@ /*- * SPDX-License-Identifier: (BSD-1-Clause AND BSD-4-Clause) * * Copyright (c) 2011 Rick van der Zwet * * Permission to use, copy, modify, and distribute this software for any * purpose with or without fee is hereby granted, provided that the above * copyright notice and this permission notice appear in all copies. * * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. */ /*- * Copyright (c) 2008 Johann Christian Rode * * Permission to use, copy, modify, and distribute this software for any * purpose with or without fee is hereby granted, provided that the above * copyright notice and this permission notice appear in all copies. * * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. */ /*- * Copyright (c) 2005, 2006, 2007 Jonathan Gray * * Permission to use, copy, modify, and distribute this software for any * purpose with or without fee is hereby granted, provided that the above * copyright notice and this permission notice appear in all copies. * * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. */ /*- * Copyright (c) 1997, 1998, 1999, 2000-2003 * Bill Paul . All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * 3. All advertising materials mentioning features or use of this software * must display the following acknowledgement: * This product includes software developed by Bill Paul. * 4. Neither the name of the author nor the names of any co-contributors * may be used to endorse or promote products derived from this software * without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF * THE POSSIBILITY OF SUCH DAMAGE. */ #include __FBSDID("$FreeBSD$"); /* * Moschip MCS7730/MCS7830/MCS7832 USB to Ethernet controller * The datasheet is available at the following URL: * http://www.moschip.com/data/products/MCS7830/Data%20Sheet_7830.pdf */ /* * The FreeBSD if_mos.c driver is based on various different sources: * The vendor provided driver at the following URL: * http://www.moschip.com/data/products/MCS7830/Driver_FreeBSD_7830.tar.gz * * Mixed together with the OpenBSD if_mos.c driver for validation and checking * and the FreeBSD if_reu.c as reference for the USB Ethernet framework. */ #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include +#include +#include +#include + #include #include #include #include "usbdevs.h" #define USB_DEBUG_VAR mos_debug #include #include #include + +#include "miibus_if.h" //#include #include "if_mosreg.h" #ifdef USB_DEBUG static int mos_debug = 0; static SYSCTL_NODE(_hw_usb, OID_AUTO, mos, CTLFLAG_RW, 0, "USB mos"); SYSCTL_INT(_hw_usb_mos, OID_AUTO, debug, CTLFLAG_RWTUN, &mos_debug, 0, "Debug level"); #endif #define MOS_DPRINTFN(fmt,...) \ DPRINTF("mos: %s: " fmt "\n",__FUNCTION__,## __VA_ARGS__) #define USB_PRODUCT_MOSCHIP_MCS7730 0x7730 #define USB_PRODUCT_SITECOMEU_LN030 0x0021 /* Various supported device vendors/products. */ static const STRUCT_USB_HOST_ID mos_devs[] = { {USB_VPI(USB_VENDOR_MOSCHIP, USB_PRODUCT_MOSCHIP_MCS7730, MCS7730)}, {USB_VPI(USB_VENDOR_MOSCHIP, USB_PRODUCT_MOSCHIP_MCS7830, MCS7830)}, {USB_VPI(USB_VENDOR_MOSCHIP, USB_PRODUCT_MOSCHIP_MCS7832, MCS7832)}, {USB_VPI(USB_VENDOR_SITECOMEU, USB_PRODUCT_SITECOMEU_LN030, MCS7830)}, }; static int mos_probe(device_t dev); static int mos_attach(device_t dev); static void mos_attach_post(struct usb_ether *ue); static int mos_detach(device_t dev); static void mos_bulk_read_callback(struct usb_xfer *xfer, usb_error_t error); static void mos_bulk_write_callback(struct usb_xfer *xfer, usb_error_t error); static void mos_intr_callback(struct usb_xfer *xfer, usb_error_t error); static void mos_tick(struct usb_ether *); static void mos_start(struct usb_ether *); static void mos_init(struct usb_ether *); static void mos_chip_init(struct mos_softc *); static void mos_stop(struct usb_ether *); static int mos_miibus_readreg(device_t, int, int); static int mos_miibus_writereg(device_t, int, int, int); static void mos_miibus_statchg(device_t); static int mos_ifmedia_upd(struct ifnet *); static void mos_ifmedia_sts(struct ifnet *, struct ifmediareq *); static void mos_reset(struct mos_softc *sc); static int mos_reg_read_1(struct mos_softc *, int); static int mos_reg_read_2(struct mos_softc *, int); static int mos_reg_write_1(struct mos_softc *, int, int); static int mos_reg_write_2(struct mos_softc *, int, int); static int mos_readmac(struct mos_softc *, uint8_t *); static int mos_writemac(struct mos_softc *, uint8_t *); static int mos_write_mcast(struct mos_softc *, u_char *); static void mos_setmulti(struct usb_ether *); static void mos_setpromisc(struct usb_ether *); static const struct usb_config mos_config[MOS_ENDPT_MAX] = { [MOS_ENDPT_TX] = { .type = UE_BULK, .endpoint = UE_ADDR_ANY, .direction = UE_DIR_OUT, .bufsize = (MCLBYTES + 2), .flags = {.pipe_bof = 1,.force_short_xfer = 1,}, .callback = mos_bulk_write_callback, .timeout = 10000, }, [MOS_ENDPT_RX] = { .type = UE_BULK, .endpoint = UE_ADDR_ANY, .direction = UE_DIR_IN, .bufsize = (MCLBYTES + 4 + ETHER_CRC_LEN), .flags = {.pipe_bof = 1,.short_xfer_ok = 1,}, .callback = mos_bulk_read_callback, }, [MOS_ENDPT_INTR] = { .type = UE_INTERRUPT, .endpoint = UE_ADDR_ANY, .direction = UE_DIR_IN, .flags = {.pipe_bof = 1,.short_xfer_ok = 1,}, .bufsize = 0, .callback = mos_intr_callback, }, }; static device_method_t mos_methods[] = { /* Device interface */ DEVMETHOD(device_probe, mos_probe), DEVMETHOD(device_attach, mos_attach), DEVMETHOD(device_detach, mos_detach), /* MII interface */ DEVMETHOD(miibus_readreg, mos_miibus_readreg), DEVMETHOD(miibus_writereg, mos_miibus_writereg), DEVMETHOD(miibus_statchg, mos_miibus_statchg), DEVMETHOD_END }; static driver_t mos_driver = { .name = "mos", .methods = mos_methods, .size = sizeof(struct mos_softc) }; static devclass_t mos_devclass; DRIVER_MODULE(mos, uhub, mos_driver, mos_devclass, NULL, 0); DRIVER_MODULE(miibus, mos, miibus_driver, miibus_devclass, 0, 0); MODULE_DEPEND(mos, uether, 1, 1, 1); MODULE_DEPEND(mos, usb, 1, 1, 1); MODULE_DEPEND(mos, ether, 1, 1, 1); MODULE_DEPEND(mos, miibus, 1, 1, 1); USB_PNP_HOST_INFO(mos_devs); static const struct usb_ether_methods mos_ue_methods = { .ue_attach_post = mos_attach_post, .ue_start = mos_start, .ue_init = mos_init, .ue_stop = mos_stop, .ue_tick = mos_tick, .ue_setmulti = mos_setmulti, .ue_setpromisc = mos_setpromisc, .ue_mii_upd = mos_ifmedia_upd, .ue_mii_sts = mos_ifmedia_sts, }; static int mos_reg_read_1(struct mos_softc *sc, int reg) { struct usb_device_request req; usb_error_t err; uByte val = 0; req.bmRequestType = UT_READ_VENDOR_DEVICE; req.bRequest = MOS_UR_READREG; USETW(req.wValue, 0); USETW(req.wIndex, reg); USETW(req.wLength, 1); err = uether_do_request(&sc->sc_ue, &req, &val, 1000); if (err) { MOS_DPRINTFN("mos_reg_read_1 error, reg: %d\n", reg); return (-1); } return (val); } static int mos_reg_read_2(struct mos_softc *sc, int reg) { struct usb_device_request req; usb_error_t err; uWord val; USETW(val, 0); req.bmRequestType = UT_READ_VENDOR_DEVICE; req.bRequest = MOS_UR_READREG; USETW(req.wValue, 0); USETW(req.wIndex, reg); USETW(req.wLength, 2); err = uether_do_request(&sc->sc_ue, &req, &val, 1000); if (err) { MOS_DPRINTFN("mos_reg_read_2 error, reg: %d", reg); return (-1); } return (UGETW(val)); } static int mos_reg_write_1(struct mos_softc *sc, int reg, int aval) { struct usb_device_request req; usb_error_t err; uByte val; val = aval; req.bmRequestType = UT_WRITE_VENDOR_DEVICE; req.bRequest = MOS_UR_WRITEREG; USETW(req.wValue, 0); USETW(req.wIndex, reg); USETW(req.wLength, 1); err = uether_do_request(&sc->sc_ue, &req, &val, 1000); if (err) { MOS_DPRINTFN("mos_reg_write_1 error, reg: %d", reg); return (-1); } return (0); } static int mos_reg_write_2(struct mos_softc *sc, int reg, int aval) { struct usb_device_request req; usb_error_t err; uWord val; USETW(val, aval); req.bmRequestType = UT_WRITE_VENDOR_DEVICE; req.bRequest = MOS_UR_WRITEREG; USETW(req.wValue, 0); USETW(req.wIndex, reg); USETW(req.wLength, 2); err = uether_do_request(&sc->sc_ue, &req, &val, 1000); if (err) { MOS_DPRINTFN("mos_reg_write_2 error, reg: %d", reg); return (-1); } return (0); } static int mos_readmac(struct mos_softc *sc, u_char *mac) { struct usb_device_request req; usb_error_t err; req.bmRequestType = UT_READ_VENDOR_DEVICE; req.bRequest = MOS_UR_READREG; USETW(req.wValue, 0); USETW(req.wIndex, MOS_MAC); USETW(req.wLength, ETHER_ADDR_LEN); err = uether_do_request(&sc->sc_ue, &req, mac, 1000); if (err) { return (-1); } return (0); } static int mos_writemac(struct mos_softc *sc, uint8_t *mac) { struct usb_device_request req; usb_error_t err; req.bmRequestType = UT_WRITE_VENDOR_DEVICE; req.bRequest = MOS_UR_WRITEREG; USETW(req.wValue, 0); USETW(req.wIndex, MOS_MAC); USETW(req.wLength, ETHER_ADDR_LEN); err = uether_do_request(&sc->sc_ue, &req, mac, 1000); if (err) { MOS_DPRINTFN("mos_writemac error"); return (-1); } return (0); } static int mos_write_mcast(struct mos_softc *sc, u_char *hashtbl) { struct usb_device_request req; usb_error_t err; req.bmRequestType = UT_WRITE_VENDOR_DEVICE; req.bRequest = MOS_UR_WRITEREG; USETW(req.wValue, 0); USETW(req.wIndex, MOS_MCAST_TABLE); USETW(req.wLength, 8); err = uether_do_request(&sc->sc_ue, &req, hashtbl, 1000); if (err) { MOS_DPRINTFN("mos_reg_mcast error"); return (-1); } return (0); } static int mos_miibus_readreg(device_t dev, int phy, int reg) { struct mos_softc *sc = device_get_softc(dev); uWord val; int i, res, locked; USETW(val, 0); locked = mtx_owned(&sc->sc_mtx); if (!locked) MOS_LOCK(sc); mos_reg_write_2(sc, MOS_PHY_DATA, 0); mos_reg_write_1(sc, MOS_PHY_CTL, (phy & MOS_PHYCTL_PHYADDR) | MOS_PHYCTL_READ); mos_reg_write_1(sc, MOS_PHY_STS, (reg & MOS_PHYSTS_PHYREG) | MOS_PHYSTS_PENDING); for (i = 0; i < MOS_TIMEOUT; i++) { if (mos_reg_read_1(sc, MOS_PHY_STS) & MOS_PHYSTS_READY) break; } if (i == MOS_TIMEOUT) { MOS_DPRINTFN("MII read timeout"); } res = mos_reg_read_2(sc, MOS_PHY_DATA); if (!locked) MOS_UNLOCK(sc); return (res); } static int mos_miibus_writereg(device_t dev, int phy, int reg, int val) { struct mos_softc *sc = device_get_softc(dev); int i, locked; locked = mtx_owned(&sc->sc_mtx); if (!locked) MOS_LOCK(sc); mos_reg_write_2(sc, MOS_PHY_DATA, val); mos_reg_write_1(sc, MOS_PHY_CTL, (phy & MOS_PHYCTL_PHYADDR) | MOS_PHYCTL_WRITE); mos_reg_write_1(sc, MOS_PHY_STS, (reg & MOS_PHYSTS_PHYREG) | MOS_PHYSTS_PENDING); for (i = 0; i < MOS_TIMEOUT; i++) { if (mos_reg_read_1(sc, MOS_PHY_STS) & MOS_PHYSTS_READY) break; } if (i == MOS_TIMEOUT) MOS_DPRINTFN("MII write timeout"); if (!locked) MOS_UNLOCK(sc); return 0; } static void mos_miibus_statchg(device_t dev) { struct mos_softc *sc = device_get_softc(dev); struct mii_data *mii = GET_MII(sc); int val, err, locked; locked = mtx_owned(&sc->sc_mtx); if (!locked) MOS_LOCK(sc); /* disable RX, TX prior to changing FDX, SPEEDSEL */ val = mos_reg_read_1(sc, MOS_CTL); val &= ~(MOS_CTL_TX_ENB | MOS_CTL_RX_ENB); mos_reg_write_1(sc, MOS_CTL, val); /* reset register which counts dropped frames */ mos_reg_write_1(sc, MOS_FRAME_DROP_CNT, 0); if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) val |= MOS_CTL_FDX_ENB; else val &= ~(MOS_CTL_FDX_ENB); switch (IFM_SUBTYPE(mii->mii_media_active)) { case IFM_100_TX: val |= MOS_CTL_SPEEDSEL; break; case IFM_10_T: val &= ~(MOS_CTL_SPEEDSEL); break; } /* re-enable TX, RX */ val |= (MOS_CTL_TX_ENB | MOS_CTL_RX_ENB); err = mos_reg_write_1(sc, MOS_CTL, val); if (err) MOS_DPRINTFN("media change failed"); if (!locked) MOS_UNLOCK(sc); } /* * Set media options. */ static int mos_ifmedia_upd(struct ifnet *ifp) { struct mos_softc *sc = ifp->if_softc; struct mii_data *mii = GET_MII(sc); struct mii_softc *miisc; int error; MOS_LOCK_ASSERT(sc, MA_OWNED); sc->mos_link = 0; LIST_FOREACH(miisc, &mii->mii_phys, mii_list) PHY_RESET(miisc); error = mii_mediachg(mii); return (error); } /* * Report current media status. */ static void mos_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) { struct mos_softc *sc = ifp->if_softc; struct mii_data *mii = GET_MII(sc); MOS_LOCK(sc); mii_pollstat(mii); ifmr->ifm_active = mii->mii_media_active; ifmr->ifm_status = mii->mii_media_status; MOS_UNLOCK(sc); } static void mos_setpromisc(struct usb_ether *ue) { struct mos_softc *sc = uether_getsc(ue); struct ifnet *ifp = uether_getifp(ue); uint8_t rxmode; MOS_LOCK_ASSERT(sc, MA_OWNED); rxmode = mos_reg_read_1(sc, MOS_CTL); /* If we want promiscuous mode, set the allframes bit. */ if (ifp->if_flags & IFF_PROMISC) { rxmode |= MOS_CTL_RX_PROMISC; } else { rxmode &= ~MOS_CTL_RX_PROMISC; } mos_reg_write_1(sc, MOS_CTL, rxmode); } static void mos_setmulti(struct usb_ether *ue) { struct mos_softc *sc = uether_getsc(ue); struct ifnet *ifp = uether_getifp(ue); struct ifmultiaddr *ifma; uint32_t h = 0; uint8_t rxmode; uint8_t hashtbl[8] = {0, 0, 0, 0, 0, 0, 0, 0}; int allmulti = 0; MOS_LOCK_ASSERT(sc, MA_OWNED); rxmode = mos_reg_read_1(sc, MOS_CTL); if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) allmulti = 1; /* get all new ones */ if_maddr_rlock(ifp); CK_STAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { if (ifma->ifma_addr->sa_family != AF_LINK) { allmulti = 1; continue; } h = ether_crc32_be(LLADDR((struct sockaddr_dl *) ifma->ifma_addr), ETHER_ADDR_LEN) >> 26; hashtbl[h / 8] |= 1 << (h % 8); } if_maddr_runlock(ifp); /* now program new ones */ if (allmulti == 1) { rxmode |= MOS_CTL_ALLMULTI; mos_reg_write_1(sc, MOS_CTL, rxmode); } else { rxmode &= ~MOS_CTL_ALLMULTI; mos_write_mcast(sc, (void *)&hashtbl); mos_reg_write_1(sc, MOS_CTL, rxmode); } } static void mos_reset(struct mos_softc *sc) { uint8_t ctl; ctl = mos_reg_read_1(sc, MOS_CTL); ctl &= ~(MOS_CTL_RX_PROMISC | MOS_CTL_ALLMULTI | MOS_CTL_TX_ENB | MOS_CTL_RX_ENB); /* Disable RX, TX, promiscuous and allmulticast mode */ mos_reg_write_1(sc, MOS_CTL, ctl); /* Reset frame drop counter register to zero */ mos_reg_write_1(sc, MOS_FRAME_DROP_CNT, 0); /* Wait a little while for the chip to get its brains in order. */ usb_pause_mtx(&sc->sc_mtx, hz / 128); return; } static void mos_chip_init(struct mos_softc *sc) { int i; /* * Rev.C devices have a pause threshold register which needs to be set * at startup. */ if (mos_reg_read_1(sc, MOS_PAUSE_TRHD) != -1) { for (i = 0; i < MOS_PAUSE_REWRITES; i++) mos_reg_write_1(sc, MOS_PAUSE_TRHD, 0); } sc->mos_phyaddrs[0] = 1; sc->mos_phyaddrs[1] = 0xFF; } /* * Probe for a MCS7x30 chip. */ static int mos_probe(device_t dev) { struct usb_attach_arg *uaa = device_get_ivars(dev); int retval; if (uaa->usb_mode != USB_MODE_HOST) return (ENXIO); if (uaa->info.bConfigIndex != MOS_CONFIG_IDX) return (ENXIO); if (uaa->info.bIfaceIndex != MOS_IFACE_IDX) return (ENXIO); retval = usbd_lookup_id_by_uaa(mos_devs, sizeof(mos_devs), uaa); return (retval); } /* * Attach the interface. Allocate softc structures, do ifmedia * setup and ethernet/BPF attach. */ static int mos_attach(device_t dev) { struct usb_attach_arg *uaa = device_get_ivars(dev); struct mos_softc *sc = device_get_softc(dev); struct usb_ether *ue = &sc->sc_ue; uint8_t iface_index; int error; sc->mos_flags = USB_GET_DRIVER_INFO(uaa); device_set_usb_desc(dev); mtx_init(&sc->sc_mtx, device_get_nameunit(dev), NULL, MTX_DEF); iface_index = MOS_IFACE_IDX; error = usbd_transfer_setup(uaa->device, &iface_index, sc->sc_xfer, mos_config, MOS_ENDPT_MAX, sc, &sc->sc_mtx); if (error) { device_printf(dev, "allocating USB transfers failed\n"); goto detach; } ue->ue_sc = sc; ue->ue_dev = dev; ue->ue_udev = uaa->device; ue->ue_mtx = &sc->sc_mtx; ue->ue_methods = &mos_ue_methods; if (sc->mos_flags & MCS7730) { MOS_DPRINTFN("model: MCS7730"); } else if (sc->mos_flags & MCS7830) { MOS_DPRINTFN("model: MCS7830"); } else if (sc->mos_flags & MCS7832) { MOS_DPRINTFN("model: MCS7832"); } error = uether_ifattach(ue); if (error) { device_printf(dev, "could not attach interface\n"); goto detach; } return (0); detach: mos_detach(dev); return (ENXIO); } static void mos_attach_post(struct usb_ether *ue) { struct mos_softc *sc = uether_getsc(ue); int err; /* Read MAC address, inform the world. */ err = mos_readmac(sc, ue->ue_eaddr); if (err) MOS_DPRINTFN("couldn't get MAC address"); MOS_DPRINTFN("address: %s", ether_sprintf(ue->ue_eaddr)); mos_chip_init(sc); } static int mos_detach(device_t dev) { struct mos_softc *sc = device_get_softc(dev); struct usb_ether *ue = &sc->sc_ue; usbd_transfer_unsetup(sc->sc_xfer, MOS_ENDPT_MAX); uether_ifdetach(ue); mtx_destroy(&sc->sc_mtx); return (0); } /* * A frame has been uploaded: pass the resulting mbuf chain up to * the higher level protocols. */ static void mos_bulk_read_callback(struct usb_xfer *xfer, usb_error_t error) { struct mos_softc *sc = usbd_xfer_softc(xfer); struct usb_ether *ue = &sc->sc_ue; struct ifnet *ifp = uether_getifp(ue); uint8_t rxstat = 0; uint32_t actlen; uint16_t pktlen = 0; struct usb_page_cache *pc; usbd_xfer_status(xfer, &actlen, NULL, NULL, NULL); pc = usbd_xfer_get_frame(xfer, 0); switch (USB_GET_STATE(xfer)) { case USB_ST_TRANSFERRED: MOS_DPRINTFN("actlen : %d", actlen); if (actlen <= 1) { if_inc_counter(ifp, IFCOUNTER_IERRORS, 1); goto tr_setup; } /* evaluate status byte at the end */ usbd_copy_out(pc, actlen - sizeof(rxstat), &rxstat, sizeof(rxstat)); if (rxstat != MOS_RXSTS_VALID) { MOS_DPRINTFN("erroneous frame received"); if (rxstat & MOS_RXSTS_SHORT_FRAME) MOS_DPRINTFN("frame size less than 64 bytes"); if (rxstat & MOS_RXSTS_LARGE_FRAME) { MOS_DPRINTFN("frame size larger than " "1532 bytes"); } if (rxstat & MOS_RXSTS_CRC_ERROR) MOS_DPRINTFN("CRC error"); if (rxstat & MOS_RXSTS_ALIGN_ERROR) MOS_DPRINTFN("alignment error"); if_inc_counter(ifp, IFCOUNTER_IERRORS, 1); goto tr_setup; } /* Remember the last byte was used for the status fields */ pktlen = actlen - 1; if (pktlen < sizeof(struct ether_header)) { MOS_DPRINTFN("error: pktlen %d is smaller " "than ether_header %zd", pktlen, sizeof(struct ether_header)); if_inc_counter(ifp, IFCOUNTER_IERRORS, 1); goto tr_setup; } uether_rxbuf(ue, pc, 0, actlen); /* FALLTHROUGH */ case USB_ST_SETUP: tr_setup: usbd_xfer_set_frame_len(xfer, 0, usbd_xfer_max_len(xfer)); usbd_transfer_submit(xfer); uether_rxflush(ue); return; default: MOS_DPRINTFN("bulk read error, %s", usbd_errstr(error)); if (error != USB_ERR_CANCELLED) { usbd_xfer_set_stall(xfer); goto tr_setup; } MOS_DPRINTFN("start rx %i", usbd_xfer_max_len(xfer)); return; } } /* * A frame was downloaded to the chip. It's safe for us to clean up * the list buffers. */ static void mos_bulk_write_callback(struct usb_xfer *xfer, usb_error_t error) { struct mos_softc *sc = usbd_xfer_softc(xfer); struct ifnet *ifp = uether_getifp(&sc->sc_ue); struct usb_page_cache *pc; struct mbuf *m; switch (USB_GET_STATE(xfer)) { case USB_ST_TRANSFERRED: MOS_DPRINTFN("transfer of complete"); if_inc_counter(ifp, IFCOUNTER_OPACKETS, 1); /* FALLTHROUGH */ case USB_ST_SETUP: tr_setup: /* * XXX: don't send anything if there is no link? */ IFQ_DRV_DEQUEUE(&ifp->if_snd, m); if (m == NULL) return; pc = usbd_xfer_get_frame(xfer, 0); usbd_m_copy_in(pc, 0, m, 0, m->m_pkthdr.len); usbd_xfer_set_frame_len(xfer, 0, m->m_pkthdr.len); /* * if there's a BPF listener, bounce a copy * of this frame to him: */ BPF_MTAP(ifp, m); m_freem(m); usbd_transfer_submit(xfer); if_inc_counter(ifp, IFCOUNTER_OPACKETS, 1); return; default: MOS_DPRINTFN("usb error on tx: %s\n", usbd_errstr(error)); if_inc_counter(ifp, IFCOUNTER_OERRORS, 1); if (error != USB_ERR_CANCELLED) { usbd_xfer_set_stall(xfer); goto tr_setup; } return; } } static void mos_tick(struct usb_ether *ue) { struct mos_softc *sc = uether_getsc(ue); struct mii_data *mii = GET_MII(sc); MOS_LOCK_ASSERT(sc, MA_OWNED); mii_tick(mii); if (!sc->mos_link && mii->mii_media_status & IFM_ACTIVE && IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) { MOS_DPRINTFN("got link"); sc->mos_link++; mos_start(ue); } } static void mos_start(struct usb_ether *ue) { struct mos_softc *sc = uether_getsc(ue); /* * start the USB transfers, if not already started: */ usbd_transfer_start(sc->sc_xfer[MOS_ENDPT_TX]); usbd_transfer_start(sc->sc_xfer[MOS_ENDPT_RX]); usbd_transfer_start(sc->sc_xfer[MOS_ENDPT_INTR]); } static void mos_init(struct usb_ether *ue) { struct mos_softc *sc = uether_getsc(ue); struct ifnet *ifp = uether_getifp(ue); uint8_t rxmode; MOS_LOCK_ASSERT(sc, MA_OWNED); /* Cancel pending I/O and free all RX/TX buffers. */ mos_reset(sc); /* Write MAC address */ mos_writemac(sc, IF_LLADDR(ifp)); /* Read and set transmitter IPG values */ sc->mos_ipgs[0] = mos_reg_read_1(sc, MOS_IPG0); sc->mos_ipgs[1] = mos_reg_read_1(sc, MOS_IPG1); mos_reg_write_1(sc, MOS_IPG0, sc->mos_ipgs[0]); mos_reg_write_1(sc, MOS_IPG1, sc->mos_ipgs[1]); /* * Enable receiver and transmitter, bridge controls speed/duplex * mode */ rxmode = mos_reg_read_1(sc, MOS_CTL); rxmode |= MOS_CTL_RX_ENB | MOS_CTL_TX_ENB | MOS_CTL_BS_ENB; rxmode &= ~(MOS_CTL_SLEEP); mos_setpromisc(ue); /* XXX: broadcast mode? */ mos_reg_write_1(sc, MOS_CTL, rxmode); /* Load the multicast filter. */ mos_setmulti(ue); ifp->if_drv_flags |= IFF_DRV_RUNNING; mos_start(ue); } static void mos_intr_callback(struct usb_xfer *xfer, usb_error_t error) { struct mos_softc *sc = usbd_xfer_softc(xfer); struct ifnet *ifp = uether_getifp(&sc->sc_ue); struct usb_page_cache *pc; uint32_t pkt; int actlen; if_inc_counter(ifp, IFCOUNTER_OERRORS, 1); usbd_xfer_status(xfer, &actlen, NULL, NULL, NULL); MOS_DPRINTFN("actlen %i", actlen); switch (USB_GET_STATE(xfer)) { case USB_ST_TRANSFERRED: pc = usbd_xfer_get_frame(xfer, 0); usbd_copy_out(pc, 0, &pkt, sizeof(pkt)); /* FALLTHROUGH */ case USB_ST_SETUP: tr_setup: return; default: if (error != USB_ERR_CANCELLED) { usbd_xfer_set_stall(xfer); goto tr_setup; } return; } } /* * Stop the adapter and free any mbufs allocated to the * RX and TX lists. */ static void mos_stop(struct usb_ether *ue) { struct mos_softc *sc = uether_getsc(ue); struct ifnet *ifp = uether_getifp(ue); mos_reset(sc); MOS_LOCK_ASSERT(sc, MA_OWNED); ifp->if_drv_flags &= ~IFF_DRV_RUNNING; /* stop all the transfers, if not already stopped */ usbd_transfer_stop(sc->sc_xfer[MOS_ENDPT_TX]); usbd_transfer_stop(sc->sc_xfer[MOS_ENDPT_RX]); usbd_transfer_stop(sc->sc_xfer[MOS_ENDPT_INTR]); sc->mos_link = 0; } Index: head/sys/dev/usb/net/if_muge.c =================================================================== --- head/sys/dev/usb/net/if_muge.c (revision 351249) +++ head/sys/dev/usb/net/if_muge.c (revision 351250) @@ -1,2282 +1,2288 @@ /*- * SPDX-License-Identifier: BSD-2-Clause-FreeBSD * * Copyright (C) 2012 Ben Gray . * Copyright (C) 2018 The FreeBSD Foundation. * * This software was developed by Arshan Khanifar * under sponsorship from the FreeBSD Foundation. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. * * $FreeBSD$ */ #include __FBSDID("$FreeBSD$"); /* * USB-To-Ethernet adapter driver for Microchip's LAN78XX and related families. * * USB 3.1 to 10/100/1000 Mbps Ethernet * LAN7800 http://www.microchip.com/wwwproducts/en/LAN7800 * * USB 2.0 to 10/100/1000 Mbps Ethernet * LAN7850 http://www.microchip.com/wwwproducts/en/LAN7850 * * USB 2 to 10/100/1000 Mbps Ethernet with built-in USB hub * LAN7515 (no datasheet available, but probes and functions as LAN7800) * * This driver is based on the if_smsc driver, with lan78xx-specific * functionality modelled on Microchip's Linux lan78xx driver. * * UNIMPLEMENTED FEATURES * ------------------ * A number of features supported by the lan78xx are not yet implemented in * this driver: * * - RX/TX checksum offloading: Nothing has been implemented yet for * TX checksumming. RX checksumming works with ICMP messages, but is broken * for TCP/UDP packets. * - Direct address translation filtering: Implemented but untested. * - VLAN tag removal. * - Support for USB interrupt endpoints. * - Latency Tolerance Messaging (LTM) support. * - TCP LSO support. * */ #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include +#include +#include +#include + #include #include #include "opt_platform.h" #ifdef FDT #include #include #include #include #endif #include #include #include #include "usbdevs.h" #define USB_DEBUG_VAR lan78xx_debug #include #include #include #include + +#include "miibus_if.h" #ifdef USB_DEBUG static int muge_debug = 0; SYSCTL_NODE(_hw_usb, OID_AUTO, muge, CTLFLAG_RW, 0, "Microchip LAN78xx USB-GigE"); SYSCTL_INT(_hw_usb_muge, OID_AUTO, debug, CTLFLAG_RWTUN, &muge_debug, 0, "Debug level"); #endif #define MUGE_DEFAULT_RX_CSUM_ENABLE (false) #define MUGE_DEFAULT_TX_CSUM_ENABLE (false) #define MUGE_DEFAULT_TSO_CSUM_ENABLE (false) /* Supported Vendor and Product IDs. */ static const struct usb_device_id lan78xx_devs[] = { #define MUGE_DEV(p,i) { USB_VPI(USB_VENDOR_SMC2, USB_PRODUCT_SMC2_##p, i) } MUGE_DEV(LAN7800_ETH, 0), MUGE_DEV(LAN7801_ETH, 0), MUGE_DEV(LAN7850_ETH, 0), #undef MUGE_DEV }; #ifdef USB_DEBUG #define muge_dbg_printf(sc, fmt, args...) \ do { \ if (muge_debug > 0) \ device_printf((sc)->sc_ue.ue_dev, "debug: " fmt, ##args); \ } while(0) #else #define muge_dbg_printf(sc, fmt, args...) do { } while (0) #endif #define muge_warn_printf(sc, fmt, args...) \ device_printf((sc)->sc_ue.ue_dev, "warning: " fmt, ##args) #define muge_err_printf(sc, fmt, args...) \ device_printf((sc)->sc_ue.ue_dev, "error: " fmt, ##args) #define ETHER_IS_ZERO(addr) \ (!(addr[0] | addr[1] | addr[2] | addr[3] | addr[4] | addr[5])) #define ETHER_IS_VALID(addr) \ (!ETHER_IS_MULTICAST(addr) && !ETHER_IS_ZERO(addr)) /* USB endpoints. */ enum { MUGE_BULK_DT_RD, MUGE_BULK_DT_WR, #if 0 /* Ignore interrupt endpoints for now as we poll on MII status. */ MUGE_INTR_DT_WR, MUGE_INTR_DT_RD, #endif MUGE_N_TRANSFER, }; struct muge_softc { struct usb_ether sc_ue; struct mtx sc_mtx; struct usb_xfer *sc_xfer[MUGE_N_TRANSFER]; int sc_phyno; uint32_t sc_leds; uint16_t sc_led_modes; uint16_t sc_led_modes_mask; /* Settings for the mac control (MAC_CSR) register. */ uint32_t sc_rfe_ctl; uint32_t sc_mdix_ctl; uint16_t chipid; uint16_t chiprev; uint32_t sc_mchash_table[ETH_DP_SEL_VHF_HASH_LEN]; uint32_t sc_pfilter_table[MUGE_NUM_PFILTER_ADDRS_][2]; uint32_t sc_flags; #define MUGE_FLAG_LINK 0x0001 #define MUGE_FLAG_INIT_DONE 0x0002 }; #define MUGE_IFACE_IDX 0 #define MUGE_LOCK(_sc) mtx_lock(&(_sc)->sc_mtx) #define MUGE_UNLOCK(_sc) mtx_unlock(&(_sc)->sc_mtx) #define MUGE_LOCK_ASSERT(_sc, t) mtx_assert(&(_sc)->sc_mtx, t) static device_probe_t muge_probe; static device_attach_t muge_attach; static device_detach_t muge_detach; static usb_callback_t muge_bulk_read_callback; static usb_callback_t muge_bulk_write_callback; static miibus_readreg_t lan78xx_miibus_readreg; static miibus_writereg_t lan78xx_miibus_writereg; static miibus_statchg_t lan78xx_miibus_statchg; static int muge_attach_post_sub(struct usb_ether *ue); static uether_fn_t muge_attach_post; static uether_fn_t muge_init; static uether_fn_t muge_stop; static uether_fn_t muge_start; static uether_fn_t muge_tick; static uether_fn_t muge_setmulti; static uether_fn_t muge_setpromisc; static int muge_ifmedia_upd(struct ifnet *); static void muge_ifmedia_sts(struct ifnet *, struct ifmediareq *); static int lan78xx_chip_init(struct muge_softc *sc); static int muge_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data); static const struct usb_config muge_config[MUGE_N_TRANSFER] = { [MUGE_BULK_DT_WR] = { .type = UE_BULK, .endpoint = UE_ADDR_ANY, .direction = UE_DIR_OUT, .frames = 16, .bufsize = 16 * (MCLBYTES + 16), .flags = {.pipe_bof = 1,.force_short_xfer = 1,}, .callback = muge_bulk_write_callback, .timeout = 10000, /* 10 seconds */ }, [MUGE_BULK_DT_RD] = { .type = UE_BULK, .endpoint = UE_ADDR_ANY, .direction = UE_DIR_IN, .bufsize = 20480, /* bytes */ .flags = {.pipe_bof = 1,.short_xfer_ok = 1,}, .callback = muge_bulk_read_callback, .timeout = 0, /* no timeout */ }, /* * The chip supports interrupt endpoints, however they aren't * needed as we poll on the MII status. */ }; static const struct usb_ether_methods muge_ue_methods = { .ue_attach_post = muge_attach_post, .ue_attach_post_sub = muge_attach_post_sub, .ue_start = muge_start, .ue_ioctl = muge_ioctl, .ue_init = muge_init, .ue_stop = muge_stop, .ue_tick = muge_tick, .ue_setmulti = muge_setmulti, .ue_setpromisc = muge_setpromisc, .ue_mii_upd = muge_ifmedia_upd, .ue_mii_sts = muge_ifmedia_sts, }; /** * lan78xx_read_reg - Read a 32-bit register on the device * @sc: driver soft context * @off: offset of the register * @data: pointer a value that will be populated with the register value * * LOCKING: * The device lock must be held before calling this function. * * RETURNS: * 0 on success, a USB_ERR_?? error code on failure. */ static int lan78xx_read_reg(struct muge_softc *sc, uint32_t off, uint32_t *data) { struct usb_device_request req; uint32_t buf; usb_error_t err; MUGE_LOCK_ASSERT(sc, MA_OWNED); req.bmRequestType = UT_READ_VENDOR_DEVICE; req.bRequest = UVR_READ_REG; USETW(req.wValue, 0); USETW(req.wIndex, off); USETW(req.wLength, 4); err = uether_do_request(&sc->sc_ue, &req, &buf, 1000); if (err != 0) muge_warn_printf(sc, "Failed to read register 0x%0x\n", off); *data = le32toh(buf); return (err); } /** * lan78xx_write_reg - Write a 32-bit register on the device * @sc: driver soft context * @off: offset of the register * @data: the 32-bit value to write into the register * * LOCKING: * The device lock must be held before calling this function. * * RETURNS: * 0 on success, a USB_ERR_?? error code on failure. */ static int lan78xx_write_reg(struct muge_softc *sc, uint32_t off, uint32_t data) { struct usb_device_request req; uint32_t buf; usb_error_t err; MUGE_LOCK_ASSERT(sc, MA_OWNED); buf = htole32(data); req.bmRequestType = UT_WRITE_VENDOR_DEVICE; req.bRequest = UVR_WRITE_REG; USETW(req.wValue, 0); USETW(req.wIndex, off); USETW(req.wLength, 4); err = uether_do_request(&sc->sc_ue, &req, &buf, 1000); if (err != 0) muge_warn_printf(sc, "Failed to write register 0x%0x\n", off); return (err); } /** * lan78xx_wait_for_bits - Poll on a register value until bits are cleared * @sc: soft context * @reg: offset of the register * @bits: if the bits are clear the function returns * * LOCKING: * The device lock must be held before calling this function. * * RETURNS: * 0 on success, or a USB_ERR_?? error code on failure. */ static int lan78xx_wait_for_bits(struct muge_softc *sc, uint32_t reg, uint32_t bits) { usb_ticks_t start_ticks; const usb_ticks_t max_ticks = USB_MS_TO_TICKS(1000); uint32_t val; int err; MUGE_LOCK_ASSERT(sc, MA_OWNED); start_ticks = (usb_ticks_t)ticks; do { if ((err = lan78xx_read_reg(sc, reg, &val)) != 0) return (err); if (!(val & bits)) return (0); uether_pause(&sc->sc_ue, hz / 100); } while (((usb_ticks_t)(ticks - start_ticks)) < max_ticks); return (USB_ERR_TIMEOUT); } /** * lan78xx_eeprom_read_raw - Read the attached EEPROM * @sc: soft context * @off: the eeprom address offset * @buf: stores the bytes * @buflen: the number of bytes to read * * Simply reads bytes from an attached eeprom. * * LOCKING: * The function takes and releases the device lock if not already held. * * RETURNS: * 0 on success, or a USB_ERR_?? error code on failure. */ static int lan78xx_eeprom_read_raw(struct muge_softc *sc, uint16_t off, uint8_t *buf, uint16_t buflen) { usb_ticks_t start_ticks; const usb_ticks_t max_ticks = USB_MS_TO_TICKS(1000); int err, locked; uint32_t val, saved; uint16_t i; locked = mtx_owned(&sc->sc_mtx); /* XXX */ if (!locked) MUGE_LOCK(sc); if (sc->chipid == ETH_ID_REV_CHIP_ID_7800_) { /* EEDO/EECLK muxed with LED0/LED1 on LAN7800. */ err = lan78xx_read_reg(sc, ETH_HW_CFG, &val); saved = val; val &= ~(ETH_HW_CFG_LEDO_EN_ | ETH_HW_CFG_LED1_EN_); err = lan78xx_write_reg(sc, ETH_HW_CFG, val); } err = lan78xx_wait_for_bits(sc, ETH_E2P_CMD, ETH_E2P_CMD_BUSY_); if (err != 0) { muge_warn_printf(sc, "eeprom busy, failed to read data\n"); goto done; } /* Start reading the bytes, one at a time. */ for (i = 0; i < buflen; i++) { val = ETH_E2P_CMD_BUSY_ | ETH_E2P_CMD_READ_; val |= (ETH_E2P_CMD_ADDR_MASK_ & (off + i)); if ((err = lan78xx_write_reg(sc, ETH_E2P_CMD, val)) != 0) goto done; start_ticks = (usb_ticks_t)ticks; do { if ((err = lan78xx_read_reg(sc, ETH_E2P_CMD, &val)) != 0) goto done; if (!(val & ETH_E2P_CMD_BUSY_) || (val & ETH_E2P_CMD_TIMEOUT_)) break; uether_pause(&sc->sc_ue, hz / 100); } while (((usb_ticks_t)(ticks - start_ticks)) < max_ticks); if (val & (ETH_E2P_CMD_BUSY_ | ETH_E2P_CMD_TIMEOUT_)) { muge_warn_printf(sc, "eeprom command failed\n"); err = USB_ERR_IOERROR; break; } if ((err = lan78xx_read_reg(sc, ETH_E2P_DATA, &val)) != 0) goto done; buf[i] = (val & 0xff); } done: if (!locked) MUGE_UNLOCK(sc); if (sc->chipid == ETH_ID_REV_CHIP_ID_7800_) { /* Restore saved LED configuration. */ lan78xx_write_reg(sc, ETH_HW_CFG, saved); } return (err); } static bool lan78xx_eeprom_present(struct muge_softc *sc) { int ret; uint8_t sig; ret = lan78xx_eeprom_read_raw(sc, ETH_E2P_INDICATOR_OFFSET, &sig, 1); return (ret == 0 && sig == ETH_E2P_INDICATOR); } /** * lan78xx_otp_read_raw * @sc: soft context * @off: the otp address offset * @buf: stores the bytes * @buflen: the number of bytes to read * * Simply reads bytes from the OTP. * * LOCKING: * The function takes and releases the device lock if not already held. * * RETURNS: * 0 on success, or a USB_ERR_?? error code on failure. * */ static int lan78xx_otp_read_raw(struct muge_softc *sc, uint16_t off, uint8_t *buf, uint16_t buflen) { int locked, err; uint32_t val; uint16_t i; locked = mtx_owned(&sc->sc_mtx); if (!locked) MUGE_LOCK(sc); err = lan78xx_read_reg(sc, OTP_PWR_DN, &val); /* Checking if bit is set. */ if (val & OTP_PWR_DN_PWRDN_N) { /* Clear it, then wait for it to be cleared. */ lan78xx_write_reg(sc, OTP_PWR_DN, 0); err = lan78xx_wait_for_bits(sc, OTP_PWR_DN, OTP_PWR_DN_PWRDN_N); if (err != 0) { muge_warn_printf(sc, "OTP off? failed to read data\n"); goto done; } } /* Start reading the bytes, one at a time. */ for (i = 0; i < buflen; i++) { err = lan78xx_write_reg(sc, OTP_ADDR1, ((off + i) >> 8) & OTP_ADDR1_15_11); err = lan78xx_write_reg(sc, OTP_ADDR2, ((off + i) & OTP_ADDR2_10_3)); err = lan78xx_write_reg(sc, OTP_FUNC_CMD, OTP_FUNC_CMD_READ_); err = lan78xx_write_reg(sc, OTP_CMD_GO, OTP_CMD_GO_GO_); err = lan78xx_wait_for_bits(sc, OTP_STATUS, OTP_STATUS_BUSY_); if (err != 0) { muge_warn_printf(sc, "OTP busy failed to read data\n"); goto done; } if ((err = lan78xx_read_reg(sc, OTP_RD_DATA, &val)) != 0) goto done; buf[i] = (uint8_t)(val & 0xff); } done: if (!locked) MUGE_UNLOCK(sc); return (err); } /** * lan78xx_otp_read * @sc: soft context * @off: the otp address offset * @buf: stores the bytes * @buflen: the number of bytes to read * * Simply reads bytes from the otp. * * LOCKING: * The function takes and releases device lock if it is not already held. * * RETURNS: * 0 on success, or a USB_ERR_?? error code on failure. */ static int lan78xx_otp_read(struct muge_softc *sc, uint16_t off, uint8_t *buf, uint16_t buflen) { uint8_t sig; int err; err = lan78xx_otp_read_raw(sc, OTP_INDICATOR_OFFSET, &sig, 1); if (err == 0) { if (sig == OTP_INDICATOR_1) { } else if (sig == OTP_INDICATOR_2) { off += 0x100; /* XXX */ } else { err = -EINVAL; } if (!err) err = lan78xx_otp_read_raw(sc, off, buf, buflen); } return (err); } /** * lan78xx_setmacaddress - Set the mac address in the device * @sc: driver soft context * @addr: pointer to array contain at least 6 bytes of the mac * * LOCKING: * Should be called with the MUGE lock held. * * RETURNS: * Returns 0 on success or a negative error code. */ static int lan78xx_setmacaddress(struct muge_softc *sc, const uint8_t *addr) { int err; uint32_t val; muge_dbg_printf(sc, "setting mac address to %02x:%02x:%02x:%02x:%02x:%02x\n", addr[0], addr[1], addr[2], addr[3], addr[4], addr[5]); MUGE_LOCK_ASSERT(sc, MA_OWNED); val = (addr[3] << 24) | (addr[2] << 16) | (addr[1] << 8) | addr[0]; if ((err = lan78xx_write_reg(sc, ETH_RX_ADDRL, val)) != 0) goto done; val = (addr[5] << 8) | addr[4]; err = lan78xx_write_reg(sc, ETH_RX_ADDRH, val); done: return (err); } /** * lan78xx_set_rx_max_frame_length * @sc: driver soft context * @size: pointer to array contain at least 6 bytes of the mac * * Sets the maximum frame length to be received. Frames bigger than * this size are aborted. * * RETURNS: * Returns 0 on success or a negative error code. */ static int lan78xx_set_rx_max_frame_length(struct muge_softc *sc, int size) { int err = 0; uint32_t buf; bool rxenabled; /* First we have to disable rx before changing the length. */ err = lan78xx_read_reg(sc, ETH_MAC_RX, &buf); rxenabled = ((buf & ETH_MAC_RX_EN_) != 0); if (rxenabled) { buf &= ~ETH_MAC_RX_EN_; err = lan78xx_write_reg(sc, ETH_MAC_RX, buf); } /* Setting max frame length. */ buf &= ~ETH_MAC_RX_MAX_FR_SIZE_MASK_; buf |= (((size + 4) << ETH_MAC_RX_MAX_FR_SIZE_SHIFT_) & ETH_MAC_RX_MAX_FR_SIZE_MASK_); err = lan78xx_write_reg(sc, ETH_MAC_RX, buf); /* If it were enabled before, we enable it back. */ if (rxenabled) { buf |= ETH_MAC_RX_EN_; err = lan78xx_write_reg(sc, ETH_MAC_RX, buf); } return (0); } /** * lan78xx_miibus_readreg - Read a MII/MDIO register * @dev: usb ether device * @phy: the number of phy reading from * @reg: the register address * * LOCKING: * Takes and releases the device mutex lock if not already held. * * RETURNS: * Returns the 16-bits read from the MII register, if this function fails * 0 is returned. */ static int lan78xx_miibus_readreg(device_t dev, int phy, int reg) { struct muge_softc *sc = device_get_softc(dev); int locked; uint32_t addr, val; val = 0; locked = mtx_owned(&sc->sc_mtx); if (!locked) MUGE_LOCK(sc); if (lan78xx_wait_for_bits(sc, ETH_MII_ACC, ETH_MII_ACC_MII_BUSY_) != 0) { muge_warn_printf(sc, "MII is busy\n"); goto done; } addr = (phy << 11) | (reg << 6) | ETH_MII_ACC_MII_READ_ | ETH_MII_ACC_MII_BUSY_; lan78xx_write_reg(sc, ETH_MII_ACC, addr); if (lan78xx_wait_for_bits(sc, ETH_MII_ACC, ETH_MII_ACC_MII_BUSY_) != 0) { muge_warn_printf(sc, "MII read timeout\n"); goto done; } lan78xx_read_reg(sc, ETH_MII_DATA, &val); val = le32toh(val); done: if (!locked) MUGE_UNLOCK(sc); return (val & 0xFFFF); } /** * lan78xx_miibus_writereg - Writes a MII/MDIO register * @dev: usb ether device * @phy: the number of phy writing to * @reg: the register address * @val: the value to write * * Attempts to write a PHY register through the usb controller registers. * * LOCKING: * Takes and releases the device mutex lock if not already held. * * RETURNS: * Always returns 0 regardless of success or failure. */ static int lan78xx_miibus_writereg(device_t dev, int phy, int reg, int val) { struct muge_softc *sc = device_get_softc(dev); int locked; uint32_t addr; if (sc->sc_phyno != phy) return (0); locked = mtx_owned(&sc->sc_mtx); if (!locked) MUGE_LOCK(sc); if (lan78xx_wait_for_bits(sc, ETH_MII_ACC, ETH_MII_ACC_MII_BUSY_) != 0) { muge_warn_printf(sc, "MII is busy\n"); goto done; } val = htole32(val); lan78xx_write_reg(sc, ETH_MII_DATA, val); addr = (phy << 11) | (reg << 6) | ETH_MII_ACC_MII_WRITE_ | ETH_MII_ACC_MII_BUSY_; lan78xx_write_reg(sc, ETH_MII_ACC, addr); if (lan78xx_wait_for_bits(sc, ETH_MII_ACC, ETH_MII_ACC_MII_BUSY_) != 0) muge_warn_printf(sc, "MII write timeout\n"); done: if (!locked) MUGE_UNLOCK(sc); return (0); } /* * lan78xx_miibus_statchg - Called to detect phy status change * @dev: usb ether device * * This function is called periodically by the system to poll for status * changes of the link. * * LOCKING: * Takes and releases the device mutex lock if not already held. */ static void lan78xx_miibus_statchg(device_t dev) { struct muge_softc *sc = device_get_softc(dev); struct mii_data *mii = uether_getmii(&sc->sc_ue); struct ifnet *ifp; int locked; int err; uint32_t flow = 0; uint32_t fct_flow = 0; locked = mtx_owned(&sc->sc_mtx); if (!locked) MUGE_LOCK(sc); ifp = uether_getifp(&sc->sc_ue); if (mii == NULL || ifp == NULL || (ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) goto done; /* Use the MII status to determine link status */ sc->sc_flags &= ~MUGE_FLAG_LINK; if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) == (IFM_ACTIVE | IFM_AVALID)) { muge_dbg_printf(sc, "media is active\n"); switch (IFM_SUBTYPE(mii->mii_media_active)) { case IFM_10_T: case IFM_100_TX: sc->sc_flags |= MUGE_FLAG_LINK; muge_dbg_printf(sc, "10/100 ethernet\n"); break; case IFM_1000_T: sc->sc_flags |= MUGE_FLAG_LINK; muge_dbg_printf(sc, "Gigabit ethernet\n"); break; default: break; } } /* Lost link, do nothing. */ if ((sc->sc_flags & MUGE_FLAG_LINK) == 0) { muge_dbg_printf(sc, "link flag not set\n"); goto done; } err = lan78xx_read_reg(sc, ETH_FCT_FLOW, &fct_flow); if (err) { muge_warn_printf(sc, "failed to read initial flow control thresholds, error %d\n", err); goto done; } /* Enable/disable full duplex operation and TX/RX pause. */ if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0) { muge_dbg_printf(sc, "full duplex operation\n"); /* Enable transmit MAC flow control function. */ if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_TXPAUSE) != 0) flow |= ETH_FLOW_CR_TX_FCEN_ | 0xFFFF; if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_RXPAUSE) != 0) flow |= ETH_FLOW_CR_RX_FCEN_; } /* XXX Flow control settings obtained from Microchip's driver. */ switch(usbd_get_speed(sc->sc_ue.ue_udev)) { case USB_SPEED_SUPER: fct_flow = 0x817; break; case USB_SPEED_HIGH: fct_flow = 0x211; break; default: break; } err += lan78xx_write_reg(sc, ETH_FLOW, flow); err += lan78xx_write_reg(sc, ETH_FCT_FLOW, fct_flow); if (err) muge_warn_printf(sc, "media change failed, error %d\n", err); done: if (!locked) MUGE_UNLOCK(sc); } /* * lan78xx_set_mdix_auto - Configure the device to enable automatic * crossover and polarity detection. LAN7800 provides HP Auto-MDIX * functionality for seamless crossover and polarity detection. * * @sc: driver soft context * * LOCKING: * Takes and releases the device mutex lock if not already held. */ static void lan78xx_set_mdix_auto(struct muge_softc *sc) { uint32_t buf, err; err = lan78xx_miibus_writereg(sc->sc_ue.ue_dev, sc->sc_phyno, MUGE_EXT_PAGE_ACCESS, MUGE_EXT_PAGE_SPACE_1); buf = lan78xx_miibus_readreg(sc->sc_ue.ue_dev, sc->sc_phyno, MUGE_EXT_MODE_CTRL); buf &= ~MUGE_EXT_MODE_CTRL_MDIX_MASK_; buf |= MUGE_EXT_MODE_CTRL_AUTO_MDIX_; lan78xx_miibus_readreg(sc->sc_ue.ue_dev, sc->sc_phyno, MII_BMCR); err += lan78xx_miibus_writereg(sc->sc_ue.ue_dev, sc->sc_phyno, MUGE_EXT_MODE_CTRL, buf); err += lan78xx_miibus_writereg(sc->sc_ue.ue_dev, sc->sc_phyno, MUGE_EXT_PAGE_ACCESS, MUGE_EXT_PAGE_SPACE_0); if (err != 0) muge_warn_printf(sc, "error setting PHY's MDIX status\n"); sc->sc_mdix_ctl = buf; } /** * lan78xx_phy_init - Initialises the in-built MUGE phy * @sc: driver soft context * * Resets the PHY part of the chip and then initialises it to default * values. The 'link down' and 'auto-negotiation complete' interrupts * from the PHY are also enabled, however we don't monitor the interrupt * endpoints for the moment. * * RETURNS: * Returns 0 on success or EIO if failed to reset the PHY. */ static int lan78xx_phy_init(struct muge_softc *sc) { muge_dbg_printf(sc, "Initializing PHY.\n"); uint16_t bmcr, lmsr; usb_ticks_t start_ticks; uint32_t hw_reg; const usb_ticks_t max_ticks = USB_MS_TO_TICKS(1000); MUGE_LOCK_ASSERT(sc, MA_OWNED); /* Reset phy and wait for reset to complete. */ lan78xx_miibus_writereg(sc->sc_ue.ue_dev, sc->sc_phyno, MII_BMCR, BMCR_RESET); start_ticks = ticks; do { uether_pause(&sc->sc_ue, hz / 100); bmcr = lan78xx_miibus_readreg(sc->sc_ue.ue_dev, sc->sc_phyno, MII_BMCR); } while ((bmcr & BMCR_RESET) && ((ticks - start_ticks) < max_ticks)); if (((usb_ticks_t)(ticks - start_ticks)) >= max_ticks) { muge_err_printf(sc, "PHY reset timed-out\n"); return (EIO); } /* Setup phy to interrupt upon link down or autoneg completion. */ lan78xx_miibus_readreg(sc->sc_ue.ue_dev, sc->sc_phyno, MUGE_PHY_INTR_STAT); lan78xx_miibus_writereg(sc->sc_ue.ue_dev, sc->sc_phyno, MUGE_PHY_INTR_MASK, (MUGE_PHY_INTR_ANEG_COMP | MUGE_PHY_INTR_LINK_CHANGE)); /* Enable Auto-MDIX for crossover and polarity detection. */ lan78xx_set_mdix_auto(sc); /* Enable all modes. */ lan78xx_miibus_writereg(sc->sc_ue.ue_dev, sc->sc_phyno, MII_ANAR, ANAR_10 | ANAR_10_FD | ANAR_TX | ANAR_TX_FD | ANAR_CSMA | ANAR_FC | ANAR_PAUSE_ASYM); /* Restart auto-negotation. */ bmcr |= BMCR_STARTNEG; bmcr |= BMCR_AUTOEN; lan78xx_miibus_writereg(sc->sc_ue.ue_dev, sc->sc_phyno, MII_BMCR, bmcr); bmcr = lan78xx_miibus_readreg(sc->sc_ue.ue_dev, sc->sc_phyno, MII_BMCR); /* Configure LED Modes. */ if (sc->sc_led_modes_mask != 0) { lmsr = lan78xx_miibus_readreg(sc->sc_ue.ue_dev, sc->sc_phyno, MUGE_PHY_LED_MODE); lmsr &= ~sc->sc_led_modes_mask; lmsr |= sc->sc_led_modes; lan78xx_miibus_writereg(sc->sc_ue.ue_dev, sc->sc_phyno, MUGE_PHY_LED_MODE, lmsr); } /* Enable appropriate LEDs. */ if (sc->sc_leds != 0 && lan78xx_read_reg(sc, ETH_HW_CFG, &hw_reg) == 0) { hw_reg &= ~(ETH_HW_CFG_LEDO_EN_ | ETH_HW_CFG_LED1_EN_ | ETH_HW_CFG_LED2_EN_ | ETH_HW_CFG_LED3_EN_ ); hw_reg |= sc->sc_leds; lan78xx_write_reg(sc, ETH_HW_CFG, hw_reg); } return (0); } /** * lan78xx_chip_init - Initialises the chip after power on * @sc: driver soft context * * This initialisation sequence is modelled on the procedure in the Linux * driver. * * RETURNS: * Returns 0 on success or an error code on failure. */ static int lan78xx_chip_init(struct muge_softc *sc) { int err; uint32_t buf; uint32_t burst_cap; MUGE_LOCK_ASSERT(sc, MA_OWNED); /* Enter H/W config mode. */ lan78xx_write_reg(sc, ETH_HW_CFG, ETH_HW_CFG_LRST_); if ((err = lan78xx_wait_for_bits(sc, ETH_HW_CFG, ETH_HW_CFG_LRST_)) != 0) { muge_warn_printf(sc, "timed-out waiting for lite reset to complete\n"); goto init_failed; } /* Set the mac address. */ if ((err = lan78xx_setmacaddress(sc, sc->sc_ue.ue_eaddr)) != 0) { muge_warn_printf(sc, "failed to set the MAC address\n"); goto init_failed; } /* Read and display the revision register. */ if ((err = lan78xx_read_reg(sc, ETH_ID_REV, &buf)) < 0) { muge_warn_printf(sc, "failed to read ETH_ID_REV (err = %d)\n", err); goto init_failed; } sc->chipid = (buf & ETH_ID_REV_CHIP_ID_MASK_) >> 16; sc->chiprev = buf & ETH_ID_REV_CHIP_REV_MASK_; switch (sc->chipid) { case ETH_ID_REV_CHIP_ID_7800_: case ETH_ID_REV_CHIP_ID_7850_: break; default: muge_warn_printf(sc, "Chip ID 0x%04x not yet supported\n", sc->chipid); goto init_failed; } device_printf(sc->sc_ue.ue_dev, "Chip ID 0x%04x rev %04x\n", sc->chipid, sc->chiprev); /* Respond to BULK-IN tokens with a NAK when RX FIFO is empty. */ if ((err = lan78xx_read_reg(sc, ETH_USB_CFG0, &buf)) != 0) { muge_warn_printf(sc, "failed to read ETH_USB_CFG0 (err=%d)\n", err); goto init_failed; } buf |= ETH_USB_CFG_BIR_; lan78xx_write_reg(sc, ETH_USB_CFG0, buf); /* * XXX LTM support will go here. */ /* Configuring the burst cap. */ switch (usbd_get_speed(sc->sc_ue.ue_udev)) { case USB_SPEED_SUPER: burst_cap = MUGE_DEFAULT_BURST_CAP_SIZE/MUGE_SS_USB_PKT_SIZE; break; case USB_SPEED_HIGH: burst_cap = MUGE_DEFAULT_BURST_CAP_SIZE/MUGE_HS_USB_PKT_SIZE; break; default: burst_cap = MUGE_DEFAULT_BURST_CAP_SIZE/MUGE_FS_USB_PKT_SIZE; } lan78xx_write_reg(sc, ETH_BURST_CAP, burst_cap); /* Set the default bulk in delay (same value from Linux driver). */ lan78xx_write_reg(sc, ETH_BULK_IN_DLY, MUGE_DEFAULT_BULK_IN_DELAY); /* Multiple ethernet frames per USB packets. */ err = lan78xx_read_reg(sc, ETH_HW_CFG, &buf); buf |= ETH_HW_CFG_MEF_; err = lan78xx_write_reg(sc, ETH_HW_CFG, buf); /* Enable burst cap. */ if ((err = lan78xx_read_reg(sc, ETH_USB_CFG0, &buf)) < 0) { muge_warn_printf(sc, "failed to read ETH_USB_CFG0 (err=%d)\n", err); goto init_failed; } buf |= ETH_USB_CFG_BCE_; err = lan78xx_write_reg(sc, ETH_USB_CFG0, buf); /* * Set FCL's RX and TX FIFO sizes: according to data sheet this is * already the default value. But we initialize it to the same value * anyways, as that's what the Linux driver does. * */ buf = (MUGE_MAX_RX_FIFO_SIZE - 512) / 512; err = lan78xx_write_reg(sc, ETH_FCT_RX_FIFO_END, buf); buf = (MUGE_MAX_TX_FIFO_SIZE - 512) / 512; err = lan78xx_write_reg(sc, ETH_FCT_TX_FIFO_END, buf); /* Enabling interrupts. (Not using them for now) */ err = lan78xx_write_reg(sc, ETH_INT_STS, ETH_INT_STS_CLEAR_ALL_); /* * Initializing flow control registers to 0. These registers are * properly set is handled in link-reset function in the Linux driver. */ err = lan78xx_write_reg(sc, ETH_FLOW, 0); err = lan78xx_write_reg(sc, ETH_FCT_FLOW, 0); /* * Settings for the RFE, we enable broadcast and destination address * perfect filtering. */ err = lan78xx_read_reg(sc, ETH_RFE_CTL, &buf); buf |= ETH_RFE_CTL_BCAST_EN_ | ETH_RFE_CTL_DA_PERFECT_; err = lan78xx_write_reg(sc, ETH_RFE_CTL, buf); /* * At this point the Linux driver writes multicast tables, and enables * checksum engines. But in FreeBSD that gets done in muge_init, * which gets called when the interface is brought up. */ /* Reset the PHY. */ lan78xx_write_reg(sc, ETH_PMT_CTL, ETH_PMT_CTL_PHY_RST_); if ((err = lan78xx_wait_for_bits(sc, ETH_PMT_CTL, ETH_PMT_CTL_PHY_RST_)) != 0) { muge_warn_printf(sc, "timed-out waiting for phy reset to complete\n"); goto init_failed; } err = lan78xx_read_reg(sc, ETH_MAC_CR, &buf); if (sc->chipid == ETH_ID_REV_CHIP_ID_7800_ && !lan78xx_eeprom_present(sc)) { /* Set automatic duplex and speed on LAN7800 without EEPROM. */ buf |= ETH_MAC_CR_AUTO_DUPLEX_ | ETH_MAC_CR_AUTO_SPEED_; } err = lan78xx_write_reg(sc, ETH_MAC_CR, buf); /* * Enable PHY interrupts (Not really getting used for now) * ETH_INT_EP_CTL: interrupt endpoint control register * phy events cause interrupts to be issued */ err = lan78xx_read_reg(sc, ETH_INT_EP_CTL, &buf); buf |= ETH_INT_ENP_PHY_INT; err = lan78xx_write_reg(sc, ETH_INT_EP_CTL, buf); /* * Enables mac's transmitter. It will transmit frames from the buffer * onto the cable. */ err = lan78xx_read_reg(sc, ETH_MAC_TX, &buf); buf |= ETH_MAC_TX_TXEN_; err = lan78xx_write_reg(sc, ETH_MAC_TX, buf); /* FIFO is capable of transmitting frames to MAC. */ err = lan78xx_read_reg(sc, ETH_FCT_TX_CTL, &buf); buf |= ETH_FCT_TX_CTL_EN_; err = lan78xx_write_reg(sc, ETH_FCT_TX_CTL, buf); /* * Set max frame length. In linux this is dev->mtu (which by default * is 1500) + VLAN_ETH_HLEN = 1518. */ err = lan78xx_set_rx_max_frame_length(sc, ETHER_MAX_LEN); /* Initialise the PHY. */ if ((err = lan78xx_phy_init(sc)) != 0) goto init_failed; /* Enable MAC RX. */ err = lan78xx_read_reg(sc, ETH_MAC_RX, &buf); buf |= ETH_MAC_RX_EN_; err = lan78xx_write_reg(sc, ETH_MAC_RX, buf); /* Enable FIFO controller RX. */ err = lan78xx_read_reg(sc, ETH_FCT_RX_CTL, &buf); buf |= ETH_FCT_TX_CTL_EN_; err = lan78xx_write_reg(sc, ETH_FCT_RX_CTL, buf); sc->sc_flags |= MUGE_FLAG_INIT_DONE; return (0); init_failed: muge_err_printf(sc, "lan78xx_chip_init failed (err=%d)\n", err); return (err); } static void muge_bulk_read_callback(struct usb_xfer *xfer, usb_error_t error) { struct muge_softc *sc = usbd_xfer_softc(xfer); struct usb_ether *ue = &sc->sc_ue; struct ifnet *ifp = uether_getifp(ue); struct mbuf *m; struct usb_page_cache *pc; uint16_t pktlen; uint32_t rx_cmd_a, rx_cmd_b; uint16_t rx_cmd_c; int off; int actlen; usbd_xfer_status(xfer, &actlen, NULL, NULL, NULL); muge_dbg_printf(sc, "rx : actlen %d\n", actlen); switch (USB_GET_STATE(xfer)) { case USB_ST_TRANSFERRED: /* * There is always a zero length frame after bringing the * interface up. */ if (actlen < (sizeof(rx_cmd_a) + ETHER_CRC_LEN)) goto tr_setup; /* * There may be multiple packets in the USB frame. Each will * have a header and each needs to have its own mbuf allocated * and populated for it. */ pc = usbd_xfer_get_frame(xfer, 0); off = 0; while (off < actlen) { /* The frame header is aligned on a 4 byte boundary. */ off = ((off + 0x3) & ~0x3); /* Extract RX CMD A. */ if (off + sizeof(rx_cmd_a) > actlen) goto tr_setup; usbd_copy_out(pc, off, &rx_cmd_a, sizeof(rx_cmd_a)); off += (sizeof(rx_cmd_a)); rx_cmd_a = le32toh(rx_cmd_a); /* Extract RX CMD B. */ if (off + sizeof(rx_cmd_b) > actlen) goto tr_setup; usbd_copy_out(pc, off, &rx_cmd_b, sizeof(rx_cmd_b)); off += (sizeof(rx_cmd_b)); rx_cmd_b = le32toh(rx_cmd_b); /* Extract RX CMD C. */ if (off + sizeof(rx_cmd_c) > actlen) goto tr_setup; usbd_copy_out(pc, off, &rx_cmd_c, sizeof(rx_cmd_c)); off += (sizeof(rx_cmd_c)); rx_cmd_c = le16toh(rx_cmd_c); if (off > actlen) goto tr_setup; pktlen = (rx_cmd_a & RX_CMD_A_LEN_MASK_); muge_dbg_printf(sc, "rx_cmd_a 0x%08x rx_cmd_b 0x%08x rx_cmd_c 0x%04x " " pktlen %d actlen %d off %d\n", rx_cmd_a, rx_cmd_b, rx_cmd_c, pktlen, actlen, off); if (rx_cmd_a & RX_CMD_A_RED_) { muge_dbg_printf(sc, "rx error (hdr 0x%08x)\n", rx_cmd_a); if_inc_counter(ifp, IFCOUNTER_IERRORS, 1); } else { /* Ethernet frame too big or too small? */ if ((pktlen < ETHER_HDR_LEN) || (pktlen > (actlen - off))) goto tr_setup; /* Create a new mbuf to store the packet. */ m = uether_newbuf(); if (m == NULL) { muge_warn_printf(sc, "failed to create new mbuf\n"); if_inc_counter(ifp, IFCOUNTER_IQDROPS, 1); goto tr_setup; } usbd_copy_out(pc, off, mtod(m, uint8_t *), pktlen); /* * Check if RX checksums are computed, and * offload them */ if ((ifp->if_capabilities & IFCAP_RXCSUM) && !(rx_cmd_a & RX_CMD_A_ICSM_)) { struct ether_header *eh; eh = mtod(m, struct ether_header *); /* * Remove the extra 2 bytes of the csum * * The checksum appears to be * simplistically calculated over the * protocol headers up to the end of the * eth frame. Which means if the eth * frame is padded the csum calculation * is incorrectly performed over the * padding bytes as well. Therefore to * be safe we ignore the H/W csum on * frames less than or equal to * 64 bytes. * * Protocols checksummed: * TCP, UDP, ICMP, IGMP, IP */ if (pktlen > ETHER_MIN_LEN) { m->m_pkthdr.csum_flags |= CSUM_DATA_VALID; /* * Copy the checksum from the * last 2 bytes of the transfer * and put in the csum_data * field. */ usbd_copy_out(pc, (off + pktlen), &m->m_pkthdr.csum_data, 2); /* * The data is copied in network * order, but the csum algorithm * in the kernel expects it to * be in host network order. */ m->m_pkthdr.csum_data = ntohs(m->m_pkthdr.csum_data); muge_dbg_printf(sc, "RX checksum offloaded (0x%04x)\n", m->m_pkthdr.csum_data); } } /* Enqueue the mbuf on the receive queue. */ if (pktlen < (4 + ETHER_HDR_LEN)) { m_freem(m); goto tr_setup; } /* Remove 4 trailing bytes */ uether_rxmbuf(ue, m, pktlen - 4); } /* * Update the offset to move to the next potential * packet. */ off += pktlen; } /* FALLTHROUGH */ case USB_ST_SETUP: tr_setup: usbd_xfer_set_frame_len(xfer, 0, usbd_xfer_max_len(xfer)); usbd_transfer_submit(xfer); uether_rxflush(ue); return; default: if (error != USB_ERR_CANCELLED) { muge_warn_printf(sc, "bulk read error, %s\n", usbd_errstr(error)); usbd_xfer_set_stall(xfer); goto tr_setup; } return; } } /** * muge_bulk_write_callback - Write callback used to send ethernet frame(s) * @xfer: the USB transfer * @error: error code if the transfers is in an errored state * * The main write function that pulls ethernet frames off the queue and * sends them out. * */ static void muge_bulk_write_callback(struct usb_xfer *xfer, usb_error_t error) { struct muge_softc *sc = usbd_xfer_softc(xfer); struct ifnet *ifp = uether_getifp(&sc->sc_ue); struct usb_page_cache *pc; struct mbuf *m; int nframes; uint32_t frm_len = 0, tx_cmd_a = 0, tx_cmd_b = 0; switch (USB_GET_STATE(xfer)) { case USB_ST_TRANSFERRED: muge_dbg_printf(sc, "USB TRANSFER status: USB_ST_TRANSFERRED\n"); ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; /* FALLTHROUGH */ case USB_ST_SETUP: muge_dbg_printf(sc, "USB TRANSFER status: USB_ST_SETUP\n"); tr_setup: if ((sc->sc_flags & MUGE_FLAG_LINK) == 0 || (ifp->if_drv_flags & IFF_DRV_OACTIVE) != 0) { muge_dbg_printf(sc, "sc->sc_flags & MUGE_FLAG_LINK: %d\n", (sc->sc_flags & MUGE_FLAG_LINK)); muge_dbg_printf(sc, "ifp->if_drv_flags & IFF_DRV_OACTIVE: %d\n", (ifp->if_drv_flags & IFF_DRV_OACTIVE)); muge_dbg_printf(sc, "USB TRANSFER not sending: no link or controller is busy \n"); /* * Don't send anything if there is no link or * controller is busy. */ return; } for (nframes = 0; nframes < 16 && !IFQ_DRV_IS_EMPTY(&ifp->if_snd); nframes++) { IFQ_DRV_DEQUEUE(&ifp->if_snd, m); if (m == NULL) break; usbd_xfer_set_frame_offset(xfer, nframes * MCLBYTES, nframes); frm_len = 0; pc = usbd_xfer_get_frame(xfer, nframes); /* * Each frame is prefixed with two 32-bit values * describing the length of the packet and buffer. */ tx_cmd_a = (m->m_pkthdr.len & TX_CMD_A_LEN_MASK_) | TX_CMD_A_FCS_; tx_cmd_a = htole32(tx_cmd_a); usbd_copy_in(pc, 0, &tx_cmd_a, sizeof(tx_cmd_a)); tx_cmd_b = 0; /* TCP LSO Support will probably be implemented here. */ tx_cmd_b = htole32(tx_cmd_b); usbd_copy_in(pc, 4, &tx_cmd_b, sizeof(tx_cmd_b)); frm_len += 8; /* Next copy in the actual packet */ usbd_m_copy_in(pc, frm_len, m, 0, m->m_pkthdr.len); frm_len += m->m_pkthdr.len; if_inc_counter(ifp, IFCOUNTER_OPACKETS, 1); /* * If there's a BPF listener, bounce a copy of this * frame to it. */ BPF_MTAP(ifp, m); m_freem(m); /* Set frame length. */ usbd_xfer_set_frame_len(xfer, nframes, frm_len); } muge_dbg_printf(sc, "USB TRANSFER nframes: %d\n", nframes); if (nframes != 0) { muge_dbg_printf(sc, "USB TRANSFER submit attempt\n"); usbd_xfer_set_frames(xfer, nframes); usbd_transfer_submit(xfer); ifp->if_drv_flags |= IFF_DRV_OACTIVE; } return; default: if_inc_counter(ifp, IFCOUNTER_OERRORS, 1); ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; if (error != USB_ERR_CANCELLED) { muge_err_printf(sc, "usb error on tx: %s\n", usbd_errstr(error)); usbd_xfer_set_stall(xfer); goto tr_setup; } return; } } /** * muge_set_mac_addr - Initiailizes NIC MAC address * @ue: the USB ethernet device * * Tries to obtain MAC address from number of sources: registers, * EEPROM, DTB blob. If all sources fail - generates random MAC. */ static void muge_set_mac_addr(struct usb_ether *ue) { struct muge_softc *sc = uether_getsc(ue); uint32_t mac_h, mac_l; memset(ue->ue_eaddr, 0xff, ETHER_ADDR_LEN); uint32_t val; lan78xx_read_reg(sc, 0, &val); /* Read current MAC address from RX_ADDRx registers. */ if ((lan78xx_read_reg(sc, ETH_RX_ADDRL, &mac_l) == 0) && (lan78xx_read_reg(sc, ETH_RX_ADDRH, &mac_h) == 0)) { ue->ue_eaddr[5] = (uint8_t)((mac_h >> 8) & 0xff); ue->ue_eaddr[4] = (uint8_t)((mac_h) & 0xff); ue->ue_eaddr[3] = (uint8_t)((mac_l >> 24) & 0xff); ue->ue_eaddr[2] = (uint8_t)((mac_l >> 16) & 0xff); ue->ue_eaddr[1] = (uint8_t)((mac_l >> 8) & 0xff); ue->ue_eaddr[0] = (uint8_t)((mac_l) & 0xff); } /* * If RX_ADDRx did not provide a valid MAC address, try EEPROM. If that * doesn't work, try OTP. Whether any of these methods work or not, try * FDT data, because it is allowed to override the EEPROM/OTP values. */ if (ETHER_IS_VALID(ue->ue_eaddr)) { muge_dbg_printf(sc, "MAC assigned from registers\n"); } else if (lan78xx_eeprom_present(sc) && lan78xx_eeprom_read_raw(sc, ETH_E2P_MAC_OFFSET, ue->ue_eaddr, ETHER_ADDR_LEN) == 0 && ETHER_IS_VALID(ue->ue_eaddr)) { muge_dbg_printf(sc, "MAC assigned from EEPROM\n"); } else if (lan78xx_otp_read(sc, OTP_MAC_OFFSET, ue->ue_eaddr, ETHER_ADDR_LEN) == 0 && ETHER_IS_VALID(ue->ue_eaddr)) { muge_dbg_printf(sc, "MAC assigned from OTP\n"); } #ifdef FDT /* ue->ue_eaddr modified only if config exists for this dev instance. */ usb_fdt_get_mac_addr(ue->ue_dev, ue); if (ETHER_IS_VALID(ue->ue_eaddr)) { muge_dbg_printf(sc, "MAC assigned from FDT data\n"); } #endif if (!ETHER_IS_VALID(ue->ue_eaddr)) { muge_dbg_printf(sc, "MAC assigned randomly\n"); arc4rand(ue->ue_eaddr, ETHER_ADDR_LEN, 0); ue->ue_eaddr[0] &= ~0x01; /* unicast */ ue->ue_eaddr[0] |= 0x02; /* locally administered */ } } /** * muge_set_leds - Initializes NIC LEDs pattern * @ue: the USB ethernet device * * Tries to store the LED modes. * Supports only DTB blob like the Linux driver does. */ static void muge_set_leds(struct usb_ether *ue) { #ifdef FDT struct muge_softc *sc = uether_getsc(ue); phandle_t node; pcell_t modes[4]; /* 4 LEDs are possible */ ssize_t proplen; uint32_t count; if ((node = usb_fdt_get_node(ue->ue_dev, ue->ue_udev)) != -1 && (proplen = OF_getencprop(node, "microchip,led-modes", modes, sizeof(modes))) > 0) { count = proplen / sizeof( uint32_t ); sc->sc_leds = (count > 0) * ETH_HW_CFG_LEDO_EN_ | (count > 1) * ETH_HW_CFG_LED1_EN_ | (count > 2) * ETH_HW_CFG_LED2_EN_ | (count > 3) * ETH_HW_CFG_LED3_EN_; while (count-- > 0) { sc->sc_led_modes |= (modes[count] & 0xf) << (4 * count); sc->sc_led_modes_mask |= 0xf << (4 * count); } muge_dbg_printf(sc, "LED modes set from FDT data\n"); } #endif } /** * muge_attach_post - Called after the driver attached to the USB interface * @ue: the USB ethernet device * * This is where the chip is intialised for the first time. This is * different from the muge_init() function in that that one is designed to * setup the H/W to match the UE settings and can be called after a reset. * */ static void muge_attach_post(struct usb_ether *ue) { struct muge_softc *sc = uether_getsc(ue); muge_dbg_printf(sc, "Calling muge_attach_post.\n"); /* Setup some of the basics */ sc->sc_phyno = 1; muge_set_mac_addr(ue); muge_set_leds(ue); /* Initialise the chip for the first time */ lan78xx_chip_init(sc); } /** * muge_attach_post_sub - Called after attach to the USB interface * @ue: the USB ethernet device * * Most of this is boilerplate code and copied from the base USB ethernet * driver. It has been overriden so that we can indicate to the system * that the chip supports H/W checksumming. * * RETURNS: * Returns 0 on success or a negative error code. */ static int muge_attach_post_sub(struct usb_ether *ue) { struct muge_softc *sc; struct ifnet *ifp; int error; sc = uether_getsc(ue); muge_dbg_printf(sc, "Calling muge_attach_post_sub.\n"); ifp = ue->ue_ifp; ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; ifp->if_start = uether_start; ifp->if_ioctl = muge_ioctl; ifp->if_init = uether_init; IFQ_SET_MAXLEN(&ifp->if_snd, ifqmaxlen); ifp->if_snd.ifq_drv_maxlen = ifqmaxlen; IFQ_SET_READY(&ifp->if_snd); /* * The chip supports TCP/UDP checksum offloading on TX and RX paths, * however currently only RX checksum is supported in the driver * (see top of file). */ ifp->if_capabilities |= IFCAP_VLAN_MTU; ifp->if_hwassist = 0; if (MUGE_DEFAULT_RX_CSUM_ENABLE) ifp->if_capabilities |= IFCAP_RXCSUM; if (MUGE_DEFAULT_TX_CSUM_ENABLE) ifp->if_capabilities |= IFCAP_TXCSUM; /* * In the Linux driver they also enable scatter/gather (NETIF_F_SG) * here, that's something related to socket buffers used in Linux. * FreeBSD doesn't have that as an interface feature. */ if (MUGE_DEFAULT_TSO_CSUM_ENABLE) ifp->if_capabilities |= IFCAP_TSO4 | IFCAP_TSO6; #if 0 /* TX checksuming is disabled since not yet implemented. */ ifp->if_capabilities |= IFCAP_TXCSUM; ifp->if_capenable |= IFCAP_TXCSUM; ifp->if_hwassist = CSUM_TCP | CSUM_UDP; #endif ifp->if_capenable = ifp->if_capabilities; mtx_lock(&Giant); error = mii_attach(ue->ue_dev, &ue->ue_miibus, ifp, uether_ifmedia_upd, ue->ue_methods->ue_mii_sts, BMSR_DEFCAPMASK, sc->sc_phyno, MII_OFFSET_ANY, 0); mtx_unlock(&Giant); return (0); } /** * muge_start - Starts communication with the LAN78xx chip * @ue: USB ether interface */ static void muge_start(struct usb_ether *ue) { struct muge_softc *sc = uether_getsc(ue); /* * Start the USB transfers, if not already started. */ usbd_transfer_start(sc->sc_xfer[MUGE_BULK_DT_RD]); usbd_transfer_start(sc->sc_xfer[MUGE_BULK_DT_WR]); } /** * muge_ioctl - ioctl function for the device * @ifp: interface pointer * @cmd: the ioctl command * @data: data passed in the ioctl call, typically a pointer to struct * ifreq. * * The ioctl routine is overridden to detect change requests for the H/W * checksum capabilities. * * RETURNS: * 0 on success and an error code on failure. */ static int muge_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data) { struct usb_ether *ue = ifp->if_softc; struct muge_softc *sc; struct ifreq *ifr; int rc; int mask; int reinit; if (cmd == SIOCSIFCAP) { sc = uether_getsc(ue); ifr = (struct ifreq *)data; MUGE_LOCK(sc); rc = 0; reinit = 0; mask = ifr->ifr_reqcap ^ ifp->if_capenable; /* Modify the RX CSUM enable bits. */ if ((mask & IFCAP_RXCSUM) != 0 && (ifp->if_capabilities & IFCAP_RXCSUM) != 0) { ifp->if_capenable ^= IFCAP_RXCSUM; if (ifp->if_drv_flags & IFF_DRV_RUNNING) { ifp->if_drv_flags &= ~IFF_DRV_RUNNING; reinit = 1; } } MUGE_UNLOCK(sc); if (reinit) uether_init(ue); } else { rc = uether_ioctl(ifp, cmd, data); } return (rc); } /** * muge_reset - Reset the SMSC chip * @sc: device soft context * * LOCKING: * Should be called with the SMSC lock held. */ static void muge_reset(struct muge_softc *sc) { struct usb_config_descriptor *cd; usb_error_t err; cd = usbd_get_config_descriptor(sc->sc_ue.ue_udev); err = usbd_req_set_config(sc->sc_ue.ue_udev, &sc->sc_mtx, cd->bConfigurationValue); if (err) muge_warn_printf(sc, "reset failed (ignored)\n"); /* Wait a little while for the chip to get its brains in order. */ uether_pause(&sc->sc_ue, hz / 100); /* Reinitialize controller to achieve full reset. */ lan78xx_chip_init(sc); } /** * muge_set_addr_filter * * @sc: device soft context * @index: index of the entry to the perfect address table * @addr: address to be written * */ static void muge_set_addr_filter(struct muge_softc *sc, int index, uint8_t addr[ETHER_ADDR_LEN]) { uint32_t tmp; if ((sc) && (index > 0) && (index < MUGE_NUM_PFILTER_ADDRS_)) { tmp = addr[3]; tmp |= addr[2] | (tmp << 8); tmp |= addr[1] | (tmp << 8); tmp |= addr[0] | (tmp << 8); sc->sc_pfilter_table[index][1] = tmp; tmp = addr[5]; tmp |= addr[4] | (tmp << 8); tmp |= ETH_MAF_HI_VALID_ | ETH_MAF_HI_TYPE_DST_; sc->sc_pfilter_table[index][0] = tmp; } } /** * lan78xx_dataport_write - write to the selected RAM * @sc: The device soft context. * @ram_select: Select which RAM to access. * @addr: Starting address to write to. * @buf: word-sized buffer to write to RAM, starting at @addr. * @length: length of @buf * * * RETURNS: * 0 if write successful. */ static int lan78xx_dataport_write(struct muge_softc *sc, uint32_t ram_select, uint32_t addr, uint32_t length, uint32_t *buf) { uint32_t dp_sel; int i, ret; MUGE_LOCK_ASSERT(sc, MA_OWNED); ret = lan78xx_wait_for_bits(sc, ETH_DP_SEL, ETH_DP_SEL_DPRDY_); if (ret < 0) goto done; ret = lan78xx_read_reg(sc, ETH_DP_SEL, &dp_sel); dp_sel &= ~ETH_DP_SEL_RSEL_MASK_; dp_sel |= ram_select; ret = lan78xx_write_reg(sc, ETH_DP_SEL, dp_sel); for (i = 0; i < length; i++) { ret = lan78xx_write_reg(sc, ETH_DP_ADDR, addr + i); ret = lan78xx_write_reg(sc, ETH_DP_DATA, buf[i]); ret = lan78xx_write_reg(sc, ETH_DP_CMD, ETH_DP_CMD_WRITE_); ret = lan78xx_wait_for_bits(sc, ETH_DP_SEL, ETH_DP_SEL_DPRDY_); if (ret != 0) goto done; } done: return (ret); } /** * muge_multicast_write * @sc: device's soft context * * Writes perfect addres filters and hash address filters to their * corresponding registers and RAMs. * */ static void muge_multicast_write(struct muge_softc *sc) { int i, ret; lan78xx_dataport_write(sc, ETH_DP_SEL_RSEL_VLAN_DA_, ETH_DP_SEL_VHF_VLAN_LEN, ETH_DP_SEL_VHF_HASH_LEN, sc->sc_mchash_table); for (i = 1; i < MUGE_NUM_PFILTER_ADDRS_; i++) { ret = lan78xx_write_reg(sc, PFILTER_HI(i), 0); ret = lan78xx_write_reg(sc, PFILTER_LO(i), sc->sc_pfilter_table[i][1]); ret = lan78xx_write_reg(sc, PFILTER_HI(i), sc->sc_pfilter_table[i][0]); } } /** * muge_hash - Calculate the hash of a mac address * @addr: The mac address to calculate the hash on * * This function is used when configuring a range of multicast mac * addresses to filter on. The hash of the mac address is put in the * device's mac hash table. * * RETURNS: * Returns a value from 0-63 value which is the hash of the mac address. */ static inline uint32_t muge_hash(uint8_t addr[ETHER_ADDR_LEN]) { return (ether_crc32_be(addr, ETHER_ADDR_LEN) >> 23) & 0x1ff; } /** * muge_setmulti - Setup multicast * @ue: usb ethernet device context * * Tells the device to either accept frames with a multicast mac address, * a select group of m'cast mac addresses or just the devices mac address. * * LOCKING: * Should be called with the MUGE lock held. */ static void muge_setmulti(struct usb_ether *ue) { struct muge_softc *sc = uether_getsc(ue); struct ifnet *ifp = uether_getifp(ue); uint8_t i, *addr; struct ifmultiaddr *ifma; MUGE_LOCK_ASSERT(sc, MA_OWNED); sc->sc_rfe_ctl &= ~(ETH_RFE_CTL_UCAST_EN_ | ETH_RFE_CTL_MCAST_EN_ | ETH_RFE_CTL_DA_PERFECT_ | ETH_RFE_CTL_MCAST_HASH_); /* Initialize hash filter table. */ for (i = 0; i < ETH_DP_SEL_VHF_HASH_LEN; i++) sc->sc_mchash_table[i] = 0; /* Initialize perfect filter table. */ for (i = 1; i < MUGE_NUM_PFILTER_ADDRS_; i++) { sc->sc_pfilter_table[i][0] = sc->sc_pfilter_table[i][1] = 0; } sc->sc_rfe_ctl |= ETH_RFE_CTL_BCAST_EN_; if (ifp->if_flags & IFF_PROMISC) { muge_dbg_printf(sc, "promiscuous mode enabled\n"); sc->sc_rfe_ctl |= ETH_RFE_CTL_MCAST_EN_ | ETH_RFE_CTL_UCAST_EN_; } else if (ifp->if_flags & IFF_ALLMULTI){ muge_dbg_printf(sc, "receive all multicast enabled\n"); sc->sc_rfe_ctl |= ETH_RFE_CTL_MCAST_EN_; } else { /* Lock the mac address list before hashing each of them. */ if_maddr_rlock(ifp); if (!CK_STAILQ_EMPTY(&ifp->if_multiaddrs)) { i = 1; CK_STAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { /* First fill up the perfect address table. */ addr = LLADDR((struct sockaddr_dl *) ifma->ifma_addr); if (i < 33 /* XXX */) { muge_set_addr_filter(sc, i, addr); } else { uint32_t bitnum = muge_hash(addr); sc->sc_mchash_table[bitnum / 32] |= (1 << (bitnum % 32)); sc->sc_rfe_ctl |= ETH_RFE_CTL_MCAST_HASH_; } i++; } } if_maddr_runlock(ifp); muge_multicast_write(sc); } lan78xx_write_reg(sc, ETH_RFE_CTL, sc->sc_rfe_ctl); } /** * muge_setpromisc - Enables/disables promiscuous mode * @ue: usb ethernet device context * * LOCKING: * Should be called with the MUGE lock held. */ static void muge_setpromisc(struct usb_ether *ue) { struct muge_softc *sc = uether_getsc(ue); struct ifnet *ifp = uether_getifp(ue); muge_dbg_printf(sc, "promiscuous mode %sabled\n", (ifp->if_flags & IFF_PROMISC) ? "en" : "dis"); MUGE_LOCK_ASSERT(sc, MA_OWNED); if (ifp->if_flags & IFF_PROMISC) sc->sc_rfe_ctl |= ETH_RFE_CTL_MCAST_EN_ | ETH_RFE_CTL_UCAST_EN_; else sc->sc_rfe_ctl &= ~(ETH_RFE_CTL_MCAST_EN_); lan78xx_write_reg(sc, ETH_RFE_CTL, sc->sc_rfe_ctl); } /** * muge_sethwcsum - Enable or disable H/W UDP and TCP checksumming * @sc: driver soft context * * LOCKING: * Should be called with the MUGE lock held. * * RETURNS: * Returns 0 on success or a negative error code. */ static int muge_sethwcsum(struct muge_softc *sc) { struct ifnet *ifp = uether_getifp(&sc->sc_ue); int err; if (!ifp) return (-EIO); MUGE_LOCK_ASSERT(sc, MA_OWNED); if (ifp->if_capabilities & IFCAP_RXCSUM) { sc->sc_rfe_ctl |= ETH_RFE_CTL_IGMP_COE_ | ETH_RFE_CTL_ICMP_COE_; sc->sc_rfe_ctl |= ETH_RFE_CTL_TCPUDP_COE_ | ETH_RFE_CTL_IP_COE_; } else { sc->sc_rfe_ctl &= ~(ETH_RFE_CTL_IGMP_COE_ | ETH_RFE_CTL_ICMP_COE_); sc->sc_rfe_ctl &= ~(ETH_RFE_CTL_TCPUDP_COE_ | ETH_RFE_CTL_IP_COE_); } sc->sc_rfe_ctl &= ~ETH_RFE_CTL_VLAN_FILTER_; err = lan78xx_write_reg(sc, ETH_RFE_CTL, sc->sc_rfe_ctl); if (err != 0) { muge_warn_printf(sc, "failed to write ETH_RFE_CTL (err=%d)\n", err); return (err); } return (0); } /** * muge_ifmedia_upd - Set media options * @ifp: interface pointer * * Basically boilerplate code that simply calls the mii functions to set * the media options. * * LOCKING: * The device lock must be held before this function is called. * * RETURNS: * Returns 0 on success or a negative error code. */ static int muge_ifmedia_upd(struct ifnet *ifp) { struct muge_softc *sc = ifp->if_softc; muge_dbg_printf(sc, "Calling muge_ifmedia_upd.\n"); struct mii_data *mii = uether_getmii(&sc->sc_ue); struct mii_softc *miisc; int err; MUGE_LOCK_ASSERT(sc, MA_OWNED); LIST_FOREACH(miisc, &mii->mii_phys, mii_list) PHY_RESET(miisc); err = mii_mediachg(mii); return (err); } /** * muge_init - Initialises the LAN95xx chip * @ue: USB ether interface * * Called when the interface is brought up (i.e. ifconfig ue0 up), this * initialise the interface and the rx/tx pipes. * * LOCKING: * Should be called with the MUGE lock held. */ static void muge_init(struct usb_ether *ue) { struct muge_softc *sc = uether_getsc(ue); muge_dbg_printf(sc, "Calling muge_init.\n"); struct ifnet *ifp = uether_getifp(ue); MUGE_LOCK_ASSERT(sc, MA_OWNED); if (lan78xx_setmacaddress(sc, IF_LLADDR(ifp))) muge_dbg_printf(sc, "setting MAC address failed\n"); if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) return; /* Cancel pending I/O. */ muge_stop(ue); /* Reset the ethernet interface. */ muge_reset(sc); /* Load the multicast filter. */ muge_setmulti(ue); /* TCP/UDP checksum offload engines. */ muge_sethwcsum(sc); usbd_xfer_set_stall(sc->sc_xfer[MUGE_BULK_DT_WR]); /* Indicate we are up and running. */ ifp->if_drv_flags |= IFF_DRV_RUNNING; /* Switch to selected media. */ muge_ifmedia_upd(ifp); muge_start(ue); } /** * muge_stop - Stops communication with the LAN78xx chip * @ue: USB ether interface */ static void muge_stop(struct usb_ether *ue) { struct muge_softc *sc = uether_getsc(ue); struct ifnet *ifp = uether_getifp(ue); MUGE_LOCK_ASSERT(sc, MA_OWNED); ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); sc->sc_flags &= ~MUGE_FLAG_LINK; /* * Stop all the transfers, if not already stopped. */ usbd_transfer_stop(sc->sc_xfer[MUGE_BULK_DT_WR]); usbd_transfer_stop(sc->sc_xfer[MUGE_BULK_DT_RD]); } /** * muge_tick - Called periodically to monitor the state of the LAN95xx chip * @ue: USB ether interface * * Simply calls the mii status functions to check the state of the link. * * LOCKING: * Should be called with the MUGE lock held. */ static void muge_tick(struct usb_ether *ue) { struct muge_softc *sc = uether_getsc(ue); struct mii_data *mii = uether_getmii(&sc->sc_ue); MUGE_LOCK_ASSERT(sc, MA_OWNED); mii_tick(mii); if ((sc->sc_flags & MUGE_FLAG_LINK) == 0) { lan78xx_miibus_statchg(ue->ue_dev); if ((sc->sc_flags & MUGE_FLAG_LINK) != 0) muge_start(ue); } } /** * muge_ifmedia_sts - Report current media status * @ifp: inet interface pointer * @ifmr: interface media request * * Call the mii functions to get the media status. * * LOCKING: * Internally takes and releases the device lock. */ static void muge_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) { struct muge_softc *sc = ifp->if_softc; struct mii_data *mii = uether_getmii(&sc->sc_ue); MUGE_LOCK(sc); mii_pollstat(mii); ifmr->ifm_active = mii->mii_media_active; ifmr->ifm_status = mii->mii_media_status; MUGE_UNLOCK(sc); } /** * muge_probe - Probe the interface. * @dev: muge device handle * * Checks if the device is a match for this driver. * * RETURNS: * Returns 0 on success or an error code on failure. */ static int muge_probe(device_t dev) { struct usb_attach_arg *uaa = device_get_ivars(dev); if (uaa->usb_mode != USB_MODE_HOST) return (ENXIO); if (uaa->info.bConfigIndex != MUGE_CONFIG_INDEX) return (ENXIO); if (uaa->info.bIfaceIndex != MUGE_IFACE_IDX) return (ENXIO); return (usbd_lookup_id_by_uaa(lan78xx_devs, sizeof(lan78xx_devs), uaa)); } /** * muge_attach - Attach the interface. * @dev: muge device handle * * Allocate softc structures, do ifmedia setup and ethernet/BPF attach. * * RETURNS: * Returns 0 on success or a negative error code. */ static int muge_attach(device_t dev) { struct usb_attach_arg *uaa = device_get_ivars(dev); struct muge_softc *sc = device_get_softc(dev); struct usb_ether *ue = &sc->sc_ue; uint8_t iface_index; int err; sc->sc_flags = USB_GET_DRIVER_INFO(uaa); device_set_usb_desc(dev); mtx_init(&sc->sc_mtx, device_get_nameunit(dev), NULL, MTX_DEF); /* Setup the endpoints for the Microchip LAN78xx device. */ iface_index = MUGE_IFACE_IDX; err = usbd_transfer_setup(uaa->device, &iface_index, sc->sc_xfer, muge_config, MUGE_N_TRANSFER, sc, &sc->sc_mtx); if (err) { device_printf(dev, "error: allocating USB transfers failed\n"); goto err; } ue->ue_sc = sc; ue->ue_dev = dev; ue->ue_udev = uaa->device; ue->ue_mtx = &sc->sc_mtx; ue->ue_methods = &muge_ue_methods; err = uether_ifattach(ue); if (err) { device_printf(dev, "error: could not attach interface\n"); goto err_usbd; } /* Wait for lan78xx_chip_init from post-attach callback to complete. */ uether_ifattach_wait(ue); if (!(sc->sc_flags & MUGE_FLAG_INIT_DONE)) goto err_attached; return (0); err_attached: uether_ifdetach(ue); err_usbd: usbd_transfer_unsetup(sc->sc_xfer, MUGE_N_TRANSFER); err: mtx_destroy(&sc->sc_mtx); return (ENXIO); } /** * muge_detach - Detach the interface. * @dev: muge device handle * * RETURNS: * Returns 0. */ static int muge_detach(device_t dev) { struct muge_softc *sc = device_get_softc(dev); struct usb_ether *ue = &sc->sc_ue; usbd_transfer_unsetup(sc->sc_xfer, MUGE_N_TRANSFER); uether_ifdetach(ue); mtx_destroy(&sc->sc_mtx); return (0); } static device_method_t muge_methods[] = { /* Device interface */ DEVMETHOD(device_probe, muge_probe), DEVMETHOD(device_attach, muge_attach), DEVMETHOD(device_detach, muge_detach), /* Bus interface */ DEVMETHOD(bus_print_child, bus_generic_print_child), DEVMETHOD(bus_driver_added, bus_generic_driver_added), /* MII interface */ DEVMETHOD(miibus_readreg, lan78xx_miibus_readreg), DEVMETHOD(miibus_writereg, lan78xx_miibus_writereg), DEVMETHOD(miibus_statchg, lan78xx_miibus_statchg), DEVMETHOD_END }; static driver_t muge_driver = { .name = "muge", .methods = muge_methods, .size = sizeof(struct muge_softc), }; static devclass_t muge_devclass; DRIVER_MODULE(muge, uhub, muge_driver, muge_devclass, NULL, NULL); DRIVER_MODULE(miibus, muge, miibus_driver, miibus_devclass, NULL, NULL); MODULE_DEPEND(muge, uether, 1, 1, 1); MODULE_DEPEND(muge, usb, 1, 1, 1); MODULE_DEPEND(muge, ether, 1, 1, 1); MODULE_DEPEND(muge, miibus, 1, 1, 1); MODULE_VERSION(muge, 1); USB_PNP_HOST_INFO(lan78xx_devs); Index: head/sys/dev/usb/net/if_rue.c =================================================================== --- head/sys/dev/usb/net/if_rue.c (revision 351249) +++ head/sys/dev/usb/net/if_rue.c (revision 351250) @@ -1,924 +1,930 @@ /*- * Copyright (c) 2001-2003, Shunsuke Akiyama . * Copyright (c) 1997, 1998, 1999, 2000 Bill Paul . * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. */ /*- * SPDX-License-Identifier: BSD-4-Clause AND BSD-2-Clause-FreeBSD * * Copyright (c) 1997, 1998, 1999, 2000 * Bill Paul . All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * 3. All advertising materials mentioning features or use of this software * must display the following acknowledgement: * This product includes software developed by Bill Paul. * 4. Neither the name of the author nor the names of any co-contributors * may be used to endorse or promote products derived from this software * without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF * THE POSSIBILITY OF SUCH DAMAGE. */ #include __FBSDID("$FreeBSD$"); /* * RealTek RTL8150 USB to fast ethernet controller driver. * Datasheet is available from * ftp://ftp.realtek.com.tw/lancard/data_sheet/8150/. */ #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include +#include +#include +#include + #include #include #include #include "usbdevs.h" #define USB_DEBUG_VAR rue_debug #include #include #include #include + +#include "miibus_if.h" #ifdef USB_DEBUG static int rue_debug = 0; static SYSCTL_NODE(_hw_usb, OID_AUTO, rue, CTLFLAG_RW, 0, "USB rue"); SYSCTL_INT(_hw_usb_rue, OID_AUTO, debug, CTLFLAG_RWTUN, &rue_debug, 0, "Debug level"); #endif /* * Various supported device vendors/products. */ static const STRUCT_USB_HOST_ID rue_devs[] = { {USB_VPI(USB_VENDOR_MELCO, USB_PRODUCT_MELCO_LUAKTX, 0)}, {USB_VPI(USB_VENDOR_REALTEK, USB_PRODUCT_REALTEK_USBKR100, 0)}, {USB_VPI(USB_VENDOR_OQO, USB_PRODUCT_OQO_ETHER01, 0)}, }; /* prototypes */ static device_probe_t rue_probe; static device_attach_t rue_attach; static device_detach_t rue_detach; static miibus_readreg_t rue_miibus_readreg; static miibus_writereg_t rue_miibus_writereg; static miibus_statchg_t rue_miibus_statchg; static usb_callback_t rue_intr_callback; static usb_callback_t rue_bulk_read_callback; static usb_callback_t rue_bulk_write_callback; static uether_fn_t rue_attach_post; static uether_fn_t rue_init; static uether_fn_t rue_stop; static uether_fn_t rue_start; static uether_fn_t rue_tick; static uether_fn_t rue_setmulti; static uether_fn_t rue_setpromisc; static int rue_read_mem(struct rue_softc *, uint16_t, void *, int); static int rue_write_mem(struct rue_softc *, uint16_t, void *, int); static uint8_t rue_csr_read_1(struct rue_softc *, uint16_t); static uint16_t rue_csr_read_2(struct rue_softc *, uint16_t); static int rue_csr_write_1(struct rue_softc *, uint16_t, uint8_t); static int rue_csr_write_2(struct rue_softc *, uint16_t, uint16_t); static int rue_csr_write_4(struct rue_softc *, int, uint32_t); static void rue_reset(struct rue_softc *); static int rue_ifmedia_upd(struct ifnet *); static void rue_ifmedia_sts(struct ifnet *, struct ifmediareq *); static const struct usb_config rue_config[RUE_N_TRANSFER] = { [RUE_BULK_DT_WR] = { .type = UE_BULK, .endpoint = UE_ADDR_ANY, .direction = UE_DIR_OUT, .bufsize = MCLBYTES, .flags = {.pipe_bof = 1,.force_short_xfer = 1,}, .callback = rue_bulk_write_callback, .timeout = 10000, /* 10 seconds */ }, [RUE_BULK_DT_RD] = { .type = UE_BULK, .endpoint = UE_ADDR_ANY, .direction = UE_DIR_IN, .bufsize = (MCLBYTES + 4), .flags = {.pipe_bof = 1,.short_xfer_ok = 1,}, .callback = rue_bulk_read_callback, .timeout = 0, /* no timeout */ }, [RUE_INTR_DT_RD] = { .type = UE_INTERRUPT, .endpoint = UE_ADDR_ANY, .direction = UE_DIR_IN, .flags = {.pipe_bof = 1,.short_xfer_ok = 1,}, .bufsize = 0, /* use wMaxPacketSize */ .callback = rue_intr_callback, }, }; static device_method_t rue_methods[] = { /* Device interface */ DEVMETHOD(device_probe, rue_probe), DEVMETHOD(device_attach, rue_attach), DEVMETHOD(device_detach, rue_detach), /* MII interface */ DEVMETHOD(miibus_readreg, rue_miibus_readreg), DEVMETHOD(miibus_writereg, rue_miibus_writereg), DEVMETHOD(miibus_statchg, rue_miibus_statchg), DEVMETHOD_END }; static driver_t rue_driver = { .name = "rue", .methods = rue_methods, .size = sizeof(struct rue_softc), }; static devclass_t rue_devclass; DRIVER_MODULE_ORDERED(rue, uhub, rue_driver, rue_devclass, NULL, NULL, SI_ORDER_ANY); DRIVER_MODULE(miibus, rue, miibus_driver, miibus_devclass, NULL, NULL); MODULE_DEPEND(rue, uether, 1, 1, 1); MODULE_DEPEND(rue, usb, 1, 1, 1); MODULE_DEPEND(rue, ether, 1, 1, 1); MODULE_DEPEND(rue, miibus, 1, 1, 1); MODULE_VERSION(rue, 1); USB_PNP_HOST_INFO(rue_devs); static const struct usb_ether_methods rue_ue_methods = { .ue_attach_post = rue_attach_post, .ue_start = rue_start, .ue_init = rue_init, .ue_stop = rue_stop, .ue_tick = rue_tick, .ue_setmulti = rue_setmulti, .ue_setpromisc = rue_setpromisc, .ue_mii_upd = rue_ifmedia_upd, .ue_mii_sts = rue_ifmedia_sts, }; #define RUE_SETBIT(sc, reg, x) \ rue_csr_write_1(sc, reg, rue_csr_read_1(sc, reg) | (x)) #define RUE_CLRBIT(sc, reg, x) \ rue_csr_write_1(sc, reg, rue_csr_read_1(sc, reg) & ~(x)) static int rue_read_mem(struct rue_softc *sc, uint16_t addr, void *buf, int len) { struct usb_device_request req; req.bmRequestType = UT_READ_VENDOR_DEVICE; req.bRequest = UR_SET_ADDRESS; USETW(req.wValue, addr); USETW(req.wIndex, 0); USETW(req.wLength, len); return (uether_do_request(&sc->sc_ue, &req, buf, 1000)); } static int rue_write_mem(struct rue_softc *sc, uint16_t addr, void *buf, int len) { struct usb_device_request req; req.bmRequestType = UT_WRITE_VENDOR_DEVICE; req.bRequest = UR_SET_ADDRESS; USETW(req.wValue, addr); USETW(req.wIndex, 0); USETW(req.wLength, len); return (uether_do_request(&sc->sc_ue, &req, buf, 1000)); } static uint8_t rue_csr_read_1(struct rue_softc *sc, uint16_t reg) { uint8_t val; rue_read_mem(sc, reg, &val, 1); return (val); } static uint16_t rue_csr_read_2(struct rue_softc *sc, uint16_t reg) { uint8_t val[2]; rue_read_mem(sc, reg, &val, 2); return (UGETW(val)); } static int rue_csr_write_1(struct rue_softc *sc, uint16_t reg, uint8_t val) { return (rue_write_mem(sc, reg, &val, 1)); } static int rue_csr_write_2(struct rue_softc *sc, uint16_t reg, uint16_t val) { uint8_t temp[2]; USETW(temp, val); return (rue_write_mem(sc, reg, &temp, 2)); } static int rue_csr_write_4(struct rue_softc *sc, int reg, uint32_t val) { uint8_t temp[4]; USETDW(temp, val); return (rue_write_mem(sc, reg, &temp, 4)); } static int rue_miibus_readreg(device_t dev, int phy, int reg) { struct rue_softc *sc = device_get_softc(dev); uint16_t rval; uint16_t ruereg; int locked; if (phy != 0) /* RTL8150 supports PHY == 0, only */ return (0); locked = mtx_owned(&sc->sc_mtx); if (!locked) RUE_LOCK(sc); switch (reg) { case MII_BMCR: ruereg = RUE_BMCR; break; case MII_BMSR: ruereg = RUE_BMSR; break; case MII_ANAR: ruereg = RUE_ANAR; break; case MII_ANER: ruereg = RUE_AER; break; case MII_ANLPAR: ruereg = RUE_ANLP; break; case MII_PHYIDR1: case MII_PHYIDR2: rval = 0; goto done; default: if (RUE_REG_MIN <= reg && reg <= RUE_REG_MAX) { rval = rue_csr_read_1(sc, reg); goto done; } device_printf(sc->sc_ue.ue_dev, "bad phy register\n"); rval = 0; goto done; } rval = rue_csr_read_2(sc, ruereg); done: if (!locked) RUE_UNLOCK(sc); return (rval); } static int rue_miibus_writereg(device_t dev, int phy, int reg, int data) { struct rue_softc *sc = device_get_softc(dev); uint16_t ruereg; int locked; if (phy != 0) /* RTL8150 supports PHY == 0, only */ return (0); locked = mtx_owned(&sc->sc_mtx); if (!locked) RUE_LOCK(sc); switch (reg) { case MII_BMCR: ruereg = RUE_BMCR; break; case MII_BMSR: ruereg = RUE_BMSR; break; case MII_ANAR: ruereg = RUE_ANAR; break; case MII_ANER: ruereg = RUE_AER; break; case MII_ANLPAR: ruereg = RUE_ANLP; break; case MII_PHYIDR1: case MII_PHYIDR2: goto done; default: if (RUE_REG_MIN <= reg && reg <= RUE_REG_MAX) { rue_csr_write_1(sc, reg, data); goto done; } device_printf(sc->sc_ue.ue_dev, " bad phy register\n"); goto done; } rue_csr_write_2(sc, ruereg, data); done: if (!locked) RUE_UNLOCK(sc); return (0); } static void rue_miibus_statchg(device_t dev) { /* * When the code below is enabled the card starts doing weird * things after link going from UP to DOWN and back UP. * * Looks like some of register writes below messes up PHY * interface. * * No visible regressions were found after commenting this code * out, so that disable it for good. */ #if 0 struct rue_softc *sc = device_get_softc(dev); struct mii_data *mii = GET_MII(sc); uint16_t bmcr; int locked; locked = mtx_owned(&sc->sc_mtx); if (!locked) RUE_LOCK(sc); RUE_CLRBIT(sc, RUE_CR, (RUE_CR_RE | RUE_CR_TE)); bmcr = rue_csr_read_2(sc, RUE_BMCR); if (IFM_SUBTYPE(mii->mii_media_active) == IFM_100_TX) bmcr |= RUE_BMCR_SPD_SET; else bmcr &= ~RUE_BMCR_SPD_SET; if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) bmcr |= RUE_BMCR_DUPLEX; else bmcr &= ~RUE_BMCR_DUPLEX; rue_csr_write_2(sc, RUE_BMCR, bmcr); RUE_SETBIT(sc, RUE_CR, (RUE_CR_RE | RUE_CR_TE)); if (!locked) RUE_UNLOCK(sc); #endif } static void rue_setpromisc(struct usb_ether *ue) { struct rue_softc *sc = uether_getsc(ue); struct ifnet *ifp = uether_getifp(ue); RUE_LOCK_ASSERT(sc, MA_OWNED); /* If we want promiscuous mode, set the allframes bit. */ if (ifp->if_flags & IFF_PROMISC) RUE_SETBIT(sc, RUE_RCR, RUE_RCR_AAP); else RUE_CLRBIT(sc, RUE_RCR, RUE_RCR_AAP); } /* * Program the 64-bit multicast hash filter. */ static void rue_setmulti(struct usb_ether *ue) { struct rue_softc *sc = uether_getsc(ue); struct ifnet *ifp = uether_getifp(ue); uint16_t rxcfg; int h = 0; uint32_t hashes[2] = { 0, 0 }; struct ifmultiaddr *ifma; int mcnt = 0; RUE_LOCK_ASSERT(sc, MA_OWNED); rxcfg = rue_csr_read_2(sc, RUE_RCR); if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { rxcfg |= (RUE_RCR_AAM | RUE_RCR_AAP); rxcfg &= ~RUE_RCR_AM; rue_csr_write_2(sc, RUE_RCR, rxcfg); rue_csr_write_4(sc, RUE_MAR0, 0xFFFFFFFF); rue_csr_write_4(sc, RUE_MAR4, 0xFFFFFFFF); return; } /* first, zot all the existing hash bits */ rue_csr_write_4(sc, RUE_MAR0, 0); rue_csr_write_4(sc, RUE_MAR4, 0); /* now program new ones */ if_maddr_rlock(ifp); CK_STAILQ_FOREACH (ifma, &ifp->if_multiaddrs, ifma_link) { if (ifma->ifma_addr->sa_family != AF_LINK) continue; h = ether_crc32_be(LLADDR((struct sockaddr_dl *) ifma->ifma_addr), ETHER_ADDR_LEN) >> 26; if (h < 32) hashes[0] |= (1 << h); else hashes[1] |= (1 << (h - 32)); mcnt++; } if_maddr_runlock(ifp); if (mcnt) rxcfg |= RUE_RCR_AM; else rxcfg &= ~RUE_RCR_AM; rxcfg &= ~(RUE_RCR_AAM | RUE_RCR_AAP); rue_csr_write_2(sc, RUE_RCR, rxcfg); rue_csr_write_4(sc, RUE_MAR0, hashes[0]); rue_csr_write_4(sc, RUE_MAR4, hashes[1]); } static void rue_reset(struct rue_softc *sc) { int i; rue_csr_write_1(sc, RUE_CR, RUE_CR_SOFT_RST); for (i = 0; i != RUE_TIMEOUT; i++) { if (uether_pause(&sc->sc_ue, hz / 1000)) break; if (!(rue_csr_read_1(sc, RUE_CR) & RUE_CR_SOFT_RST)) break; } if (i == RUE_TIMEOUT) device_printf(sc->sc_ue.ue_dev, "reset never completed\n"); uether_pause(&sc->sc_ue, hz / 100); } static void rue_attach_post(struct usb_ether *ue) { struct rue_softc *sc = uether_getsc(ue); /* reset the adapter */ rue_reset(sc); /* get station address from the EEPROM */ rue_read_mem(sc, RUE_EEPROM_IDR0, ue->ue_eaddr, ETHER_ADDR_LEN); } /* * Probe for a RTL8150 chip. */ static int rue_probe(device_t dev) { struct usb_attach_arg *uaa = device_get_ivars(dev); if (uaa->usb_mode != USB_MODE_HOST) return (ENXIO); if (uaa->info.bConfigIndex != RUE_CONFIG_IDX) return (ENXIO); if (uaa->info.bIfaceIndex != RUE_IFACE_IDX) return (ENXIO); return (usbd_lookup_id_by_uaa(rue_devs, sizeof(rue_devs), uaa)); } /* * Attach the interface. Allocate softc structures, do ifmedia * setup and ethernet/BPF attach. */ static int rue_attach(device_t dev) { struct usb_attach_arg *uaa = device_get_ivars(dev); struct rue_softc *sc = device_get_softc(dev); struct usb_ether *ue = &sc->sc_ue; uint8_t iface_index; int error; device_set_usb_desc(dev); mtx_init(&sc->sc_mtx, device_get_nameunit(dev), NULL, MTX_DEF); iface_index = RUE_IFACE_IDX; error = usbd_transfer_setup(uaa->device, &iface_index, sc->sc_xfer, rue_config, RUE_N_TRANSFER, sc, &sc->sc_mtx); if (error) { device_printf(dev, "allocating USB transfers failed\n"); goto detach; } ue->ue_sc = sc; ue->ue_dev = dev; ue->ue_udev = uaa->device; ue->ue_mtx = &sc->sc_mtx; ue->ue_methods = &rue_ue_methods; error = uether_ifattach(ue); if (error) { device_printf(dev, "could not attach interface\n"); goto detach; } return (0); /* success */ detach: rue_detach(dev); return (ENXIO); /* failure */ } static int rue_detach(device_t dev) { struct rue_softc *sc = device_get_softc(dev); struct usb_ether *ue = &sc->sc_ue; usbd_transfer_unsetup(sc->sc_xfer, RUE_N_TRANSFER); uether_ifdetach(ue); mtx_destroy(&sc->sc_mtx); return (0); } static void rue_intr_callback(struct usb_xfer *xfer, usb_error_t error) { struct rue_softc *sc = usbd_xfer_softc(xfer); struct ifnet *ifp = uether_getifp(&sc->sc_ue); struct rue_intrpkt pkt; struct usb_page_cache *pc; int actlen; usbd_xfer_status(xfer, &actlen, NULL, NULL, NULL); switch (USB_GET_STATE(xfer)) { case USB_ST_TRANSFERRED: if (ifp && (ifp->if_drv_flags & IFF_DRV_RUNNING) && actlen >= (int)sizeof(pkt)) { pc = usbd_xfer_get_frame(xfer, 0); usbd_copy_out(pc, 0, &pkt, sizeof(pkt)); if_inc_counter(ifp, IFCOUNTER_IERRORS, pkt.rue_rxlost_cnt); if_inc_counter(ifp, IFCOUNTER_IERRORS, pkt.rue_crcerr_cnt); if_inc_counter(ifp, IFCOUNTER_COLLISIONS, pkt.rue_col_cnt); } /* FALLTHROUGH */ case USB_ST_SETUP: tr_setup: usbd_xfer_set_frame_len(xfer, 0, usbd_xfer_max_len(xfer)); usbd_transfer_submit(xfer); return; default: /* Error */ if (error != USB_ERR_CANCELLED) { /* try to clear stall first */ usbd_xfer_set_stall(xfer); goto tr_setup; } return; } } static void rue_bulk_read_callback(struct usb_xfer *xfer, usb_error_t error) { struct rue_softc *sc = usbd_xfer_softc(xfer); struct usb_ether *ue = &sc->sc_ue; struct ifnet *ifp = uether_getifp(ue); struct usb_page_cache *pc; uint16_t status; int actlen; usbd_xfer_status(xfer, &actlen, NULL, NULL, NULL); switch (USB_GET_STATE(xfer)) { case USB_ST_TRANSFERRED: if (actlen < 4) { if_inc_counter(ifp, IFCOUNTER_IERRORS, 1); goto tr_setup; } pc = usbd_xfer_get_frame(xfer, 0); usbd_copy_out(pc, actlen - 4, &status, sizeof(status)); actlen -= 4; /* check receive packet was valid or not */ status = le16toh(status); if ((status & RUE_RXSTAT_VALID) == 0) { if_inc_counter(ifp, IFCOUNTER_IERRORS, 1); goto tr_setup; } uether_rxbuf(ue, pc, 0, actlen); /* FALLTHROUGH */ case USB_ST_SETUP: tr_setup: usbd_xfer_set_frame_len(xfer, 0, usbd_xfer_max_len(xfer)); usbd_transfer_submit(xfer); uether_rxflush(ue); return; default: /* Error */ DPRINTF("bulk read error, %s\n", usbd_errstr(error)); if (error != USB_ERR_CANCELLED) { /* try to clear stall first */ usbd_xfer_set_stall(xfer); goto tr_setup; } return; } } static void rue_bulk_write_callback(struct usb_xfer *xfer, usb_error_t error) { struct rue_softc *sc = usbd_xfer_softc(xfer); struct ifnet *ifp = uether_getifp(&sc->sc_ue); struct usb_page_cache *pc; struct mbuf *m; int temp_len; switch (USB_GET_STATE(xfer)) { case USB_ST_TRANSFERRED: DPRINTFN(11, "transfer complete\n"); if_inc_counter(ifp, IFCOUNTER_OPACKETS, 1); /* FALLTHROUGH */ case USB_ST_SETUP: tr_setup: if ((sc->sc_flags & RUE_FLAG_LINK) == 0) { /* * don't send anything if there is no link ! */ return; } IFQ_DRV_DEQUEUE(&ifp->if_snd, m); if (m == NULL) return; if (m->m_pkthdr.len > MCLBYTES) m->m_pkthdr.len = MCLBYTES; temp_len = m->m_pkthdr.len; pc = usbd_xfer_get_frame(xfer, 0); usbd_m_copy_in(pc, 0, m, 0, m->m_pkthdr.len); /* * This is an undocumented behavior. * RTL8150 chip doesn't send frame length smaller than * RUE_MIN_FRAMELEN (60) byte packet. */ if (temp_len < RUE_MIN_FRAMELEN) { usbd_frame_zero(pc, temp_len, RUE_MIN_FRAMELEN - temp_len); temp_len = RUE_MIN_FRAMELEN; } usbd_xfer_set_frame_len(xfer, 0, temp_len); /* * if there's a BPF listener, bounce a copy * of this frame to him: */ BPF_MTAP(ifp, m); m_freem(m); usbd_transfer_submit(xfer); return; default: /* Error */ DPRINTFN(11, "transfer error, %s\n", usbd_errstr(error)); if_inc_counter(ifp, IFCOUNTER_OERRORS, 1); if (error != USB_ERR_CANCELLED) { /* try to clear stall first */ usbd_xfer_set_stall(xfer); goto tr_setup; } return; } } static void rue_tick(struct usb_ether *ue) { struct rue_softc *sc = uether_getsc(ue); struct mii_data *mii = GET_MII(sc); RUE_LOCK_ASSERT(sc, MA_OWNED); mii_tick(mii); if ((sc->sc_flags & RUE_FLAG_LINK) == 0 && mii->mii_media_status & IFM_ACTIVE && IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) { sc->sc_flags |= RUE_FLAG_LINK; rue_start(ue); } } static void rue_start(struct usb_ether *ue) { struct rue_softc *sc = uether_getsc(ue); /* * start the USB transfers, if not already started: */ usbd_transfer_start(sc->sc_xfer[RUE_INTR_DT_RD]); usbd_transfer_start(sc->sc_xfer[RUE_BULK_DT_RD]); usbd_transfer_start(sc->sc_xfer[RUE_BULK_DT_WR]); } static void rue_init(struct usb_ether *ue) { struct rue_softc *sc = uether_getsc(ue); struct ifnet *ifp = uether_getifp(ue); RUE_LOCK_ASSERT(sc, MA_OWNED); /* * Cancel pending I/O */ rue_reset(sc); /* Set MAC address */ rue_write_mem(sc, RUE_IDR0, IF_LLADDR(ifp), ETHER_ADDR_LEN); rue_stop(ue); /* * Set the initial TX and RX configuration. */ rue_csr_write_1(sc, RUE_TCR, RUE_TCR_CONFIG); rue_csr_write_2(sc, RUE_RCR, RUE_RCR_CONFIG|RUE_RCR_AB); /* Load the multicast filter */ rue_setpromisc(ue); /* Load the multicast filter. */ rue_setmulti(ue); /* Enable RX and TX */ rue_csr_write_1(sc, RUE_CR, (RUE_CR_TE | RUE_CR_RE | RUE_CR_EP3CLREN)); usbd_xfer_set_stall(sc->sc_xfer[RUE_BULK_DT_WR]); ifp->if_drv_flags |= IFF_DRV_RUNNING; rue_start(ue); } /* * Set media options. */ static int rue_ifmedia_upd(struct ifnet *ifp) { struct rue_softc *sc = ifp->if_softc; struct mii_data *mii = GET_MII(sc); struct mii_softc *miisc; int error; RUE_LOCK_ASSERT(sc, MA_OWNED); sc->sc_flags &= ~RUE_FLAG_LINK; LIST_FOREACH(miisc, &mii->mii_phys, mii_list) PHY_RESET(miisc); error = mii_mediachg(mii); return (error); } /* * Report current media status. */ static void rue_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) { struct rue_softc *sc = ifp->if_softc; struct mii_data *mii = GET_MII(sc); RUE_LOCK(sc); mii_pollstat(mii); ifmr->ifm_active = mii->mii_media_active; ifmr->ifm_status = mii->mii_media_status; RUE_UNLOCK(sc); } static void rue_stop(struct usb_ether *ue) { struct rue_softc *sc = uether_getsc(ue); struct ifnet *ifp = uether_getifp(ue); RUE_LOCK_ASSERT(sc, MA_OWNED); ifp->if_drv_flags &= ~IFF_DRV_RUNNING; sc->sc_flags &= ~RUE_FLAG_LINK; /* * stop all the transfers, if not already stopped: */ usbd_transfer_stop(sc->sc_xfer[RUE_BULK_DT_WR]); usbd_transfer_stop(sc->sc_xfer[RUE_BULK_DT_RD]); usbd_transfer_stop(sc->sc_xfer[RUE_INTR_DT_RD]); rue_csr_write_1(sc, RUE_CR, 0x00); rue_reset(sc); } Index: head/sys/dev/usb/net/if_smsc.c =================================================================== --- head/sys/dev/usb/net/if_smsc.c (revision 351249) +++ head/sys/dev/usb/net/if_smsc.c (revision 351250) @@ -1,1808 +1,1814 @@ /*- * SPDX-License-Identifier: BSD-2-Clause-FreeBSD * * Copyright (c) 2012 * Ben Gray . * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ #include __FBSDID("$FreeBSD$"); /* * SMSC LAN9xxx devices (http://www.smsc.com/) * * The LAN9500 & LAN9500A devices are stand-alone USB to Ethernet chips that * support USB 2.0 and 10/100 Mbps Ethernet. * * The LAN951x devices are an integrated USB hub and USB to Ethernet adapter. * The driver only covers the Ethernet part, the standard USB hub driver * supports the hub part. * * This driver is closely modelled on the Linux driver written and copyrighted * by SMSC. * * * * * H/W TCP & UDP Checksum Offloading * --------------------------------- * The chip supports both tx and rx offloading of UDP & TCP checksums, this * feature can be dynamically enabled/disabled. * * RX checksuming is performed across bytes after the IPv4 header to the end of * the Ethernet frame, this means if the frame is padded with non-zero values * the H/W checksum will be incorrect, however the rx code compensates for this. * * TX checksuming is more complicated, the device requires a special header to * be prefixed onto the start of the frame which indicates the start and end * positions of the UDP or TCP frame. This requires the driver to manually * go through the packet data and decode the headers prior to sending. * On Linux they generally provide cues to the location of the csum and the * area to calculate it over, on FreeBSD we seem to have to do it all ourselves, * hence this is not as optimal and therefore h/w tX checksum is currently not * implemented. * */ #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include +#include +#include +#include + #include #include #include "opt_platform.h" #ifdef FDT #include #include #include #include #endif #include #include #include #include "usbdevs.h" #define USB_DEBUG_VAR smsc_debug #include #include #include #include + +#include "miibus_if.h" #ifdef USB_DEBUG static int smsc_debug = 0; SYSCTL_NODE(_hw_usb, OID_AUTO, smsc, CTLFLAG_RW, 0, "USB smsc"); SYSCTL_INT(_hw_usb_smsc, OID_AUTO, debug, CTLFLAG_RWTUN, &smsc_debug, 0, "Debug level"); #endif /* * Various supported device vendors/products. */ static const struct usb_device_id smsc_devs[] = { #define SMSC_DEV(p,i) { USB_VPI(USB_VENDOR_SMC2, USB_PRODUCT_SMC2_##p, i) } SMSC_DEV(LAN89530_ETH, 0), SMSC_DEV(LAN9500_ETH, 0), SMSC_DEV(LAN9500_ETH_2, 0), SMSC_DEV(LAN9500A_ETH, 0), SMSC_DEV(LAN9500A_ETH_2, 0), SMSC_DEV(LAN9505_ETH, 0), SMSC_DEV(LAN9505A_ETH, 0), SMSC_DEV(LAN9514_ETH, 0), SMSC_DEV(LAN9514_ETH_2, 0), SMSC_DEV(LAN9530_ETH, 0), SMSC_DEV(LAN9730_ETH, 0), SMSC_DEV(LAN9500_SAL10, 0), SMSC_DEV(LAN9505_SAL10, 0), SMSC_DEV(LAN9500A_SAL10, 0), SMSC_DEV(LAN9505A_SAL10, 0), SMSC_DEV(LAN9514_SAL10, 0), SMSC_DEV(LAN9500A_HAL, 0), SMSC_DEV(LAN9505A_HAL, 0), #undef SMSC_DEV }; #ifdef USB_DEBUG #define smsc_dbg_printf(sc, fmt, args...) \ do { \ if (smsc_debug > 0) \ device_printf((sc)->sc_ue.ue_dev, "debug: " fmt, ##args); \ } while(0) #else #define smsc_dbg_printf(sc, fmt, args...) do { } while (0) #endif #define smsc_warn_printf(sc, fmt, args...) \ device_printf((sc)->sc_ue.ue_dev, "warning: " fmt, ##args) #define smsc_err_printf(sc, fmt, args...) \ device_printf((sc)->sc_ue.ue_dev, "error: " fmt, ##args) #define ETHER_IS_ZERO(addr) \ (!(addr[0] | addr[1] | addr[2] | addr[3] | addr[4] | addr[5])) #define ETHER_IS_VALID(addr) \ (!ETHER_IS_MULTICAST(addr) && !ETHER_IS_ZERO(addr)) static device_probe_t smsc_probe; static device_attach_t smsc_attach; static device_detach_t smsc_detach; static usb_callback_t smsc_bulk_read_callback; static usb_callback_t smsc_bulk_write_callback; static miibus_readreg_t smsc_miibus_readreg; static miibus_writereg_t smsc_miibus_writereg; static miibus_statchg_t smsc_miibus_statchg; #if __FreeBSD_version > 1000000 static int smsc_attach_post_sub(struct usb_ether *ue); #endif static uether_fn_t smsc_attach_post; static uether_fn_t smsc_init; static uether_fn_t smsc_stop; static uether_fn_t smsc_start; static uether_fn_t smsc_tick; static uether_fn_t smsc_setmulti; static uether_fn_t smsc_setpromisc; static int smsc_ifmedia_upd(struct ifnet *); static void smsc_ifmedia_sts(struct ifnet *, struct ifmediareq *); static int smsc_chip_init(struct smsc_softc *sc); static int smsc_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data); static const struct usb_config smsc_config[SMSC_N_TRANSFER] = { [SMSC_BULK_DT_WR] = { .type = UE_BULK, .endpoint = UE_ADDR_ANY, .direction = UE_DIR_OUT, .frames = 16, .bufsize = 16 * (MCLBYTES + 16), .flags = {.pipe_bof = 1,.force_short_xfer = 1,}, .callback = smsc_bulk_write_callback, .timeout = 10000, /* 10 seconds */ }, [SMSC_BULK_DT_RD] = { .type = UE_BULK, .endpoint = UE_ADDR_ANY, .direction = UE_DIR_IN, .bufsize = 20480, /* bytes */ .flags = {.pipe_bof = 1,.short_xfer_ok = 1,}, .callback = smsc_bulk_read_callback, .timeout = 0, /* no timeout */ }, /* The SMSC chip supports an interrupt endpoints, however they aren't * needed as we poll on the MII status. */ }; static const struct usb_ether_methods smsc_ue_methods = { .ue_attach_post = smsc_attach_post, #if __FreeBSD_version > 1000000 .ue_attach_post_sub = smsc_attach_post_sub, #endif .ue_start = smsc_start, .ue_ioctl = smsc_ioctl, .ue_init = smsc_init, .ue_stop = smsc_stop, .ue_tick = smsc_tick, .ue_setmulti = smsc_setmulti, .ue_setpromisc = smsc_setpromisc, .ue_mii_upd = smsc_ifmedia_upd, .ue_mii_sts = smsc_ifmedia_sts, }; /** * smsc_read_reg - Reads a 32-bit register on the device * @sc: driver soft context * @off: offset of the register * @data: pointer a value that will be populated with the register value * * LOCKING: * The device lock must be held before calling this function. * * RETURNS: * 0 on success, a USB_ERR_?? error code on failure. */ static int smsc_read_reg(struct smsc_softc *sc, uint32_t off, uint32_t *data) { struct usb_device_request req; uint32_t buf; usb_error_t err; SMSC_LOCK_ASSERT(sc, MA_OWNED); req.bmRequestType = UT_READ_VENDOR_DEVICE; req.bRequest = SMSC_UR_READ_REG; USETW(req.wValue, 0); USETW(req.wIndex, off); USETW(req.wLength, 4); err = uether_do_request(&sc->sc_ue, &req, &buf, 1000); if (err != 0) smsc_warn_printf(sc, "Failed to read register 0x%0x\n", off); *data = le32toh(buf); return (err); } /** * smsc_write_reg - Writes a 32-bit register on the device * @sc: driver soft context * @off: offset of the register * @data: the 32-bit value to write into the register * * LOCKING: * The device lock must be held before calling this function. * * RETURNS: * 0 on success, a USB_ERR_?? error code on failure. */ static int smsc_write_reg(struct smsc_softc *sc, uint32_t off, uint32_t data) { struct usb_device_request req; uint32_t buf; usb_error_t err; SMSC_LOCK_ASSERT(sc, MA_OWNED); buf = htole32(data); req.bmRequestType = UT_WRITE_VENDOR_DEVICE; req.bRequest = SMSC_UR_WRITE_REG; USETW(req.wValue, 0); USETW(req.wIndex, off); USETW(req.wLength, 4); err = uether_do_request(&sc->sc_ue, &req, &buf, 1000); if (err != 0) smsc_warn_printf(sc, "Failed to write register 0x%0x\n", off); return (err); } /** * smsc_wait_for_bits - Polls on a register value until bits are cleared * @sc: soft context * @reg: offset of the register * @bits: if the bits are clear the function returns * * LOCKING: * The device lock must be held before calling this function. * * RETURNS: * 0 on success, or a USB_ERR_?? error code on failure. */ static int smsc_wait_for_bits(struct smsc_softc *sc, uint32_t reg, uint32_t bits) { usb_ticks_t start_ticks; const usb_ticks_t max_ticks = USB_MS_TO_TICKS(1000); uint32_t val; int err; SMSC_LOCK_ASSERT(sc, MA_OWNED); start_ticks = (usb_ticks_t)ticks; do { if ((err = smsc_read_reg(sc, reg, &val)) != 0) return (err); if (!(val & bits)) return (0); uether_pause(&sc->sc_ue, hz / 100); } while (((usb_ticks_t)(ticks - start_ticks)) < max_ticks); return (USB_ERR_TIMEOUT); } /** * smsc_eeprom_read - Reads the attached EEPROM * @sc: soft context * @off: the eeprom address offset * @buf: stores the bytes * @buflen: the number of bytes to read * * Simply reads bytes from an attached eeprom. * * LOCKING: * The function takes and releases the device lock if it is not already held. * * RETURNS: * 0 on success, or a USB_ERR_?? error code on failure. */ static int smsc_eeprom_read(struct smsc_softc *sc, uint16_t off, uint8_t *buf, uint16_t buflen) { usb_ticks_t start_ticks; const usb_ticks_t max_ticks = USB_MS_TO_TICKS(1000); int err; int locked; uint32_t val; uint16_t i; locked = mtx_owned(&sc->sc_mtx); if (!locked) SMSC_LOCK(sc); err = smsc_wait_for_bits(sc, SMSC_EEPROM_CMD, SMSC_EEPROM_CMD_BUSY); if (err != 0) { smsc_warn_printf(sc, "eeprom busy, failed to read data\n"); goto done; } /* start reading the bytes, one at a time */ for (i = 0; i < buflen; i++) { val = SMSC_EEPROM_CMD_BUSY | (SMSC_EEPROM_CMD_ADDR_MASK & (off + i)); if ((err = smsc_write_reg(sc, SMSC_EEPROM_CMD, val)) != 0) goto done; start_ticks = (usb_ticks_t)ticks; do { if ((err = smsc_read_reg(sc, SMSC_EEPROM_CMD, &val)) != 0) goto done; if (!(val & SMSC_EEPROM_CMD_BUSY) || (val & SMSC_EEPROM_CMD_TIMEOUT)) break; uether_pause(&sc->sc_ue, hz / 100); } while (((usb_ticks_t)(ticks - start_ticks)) < max_ticks); if (val & (SMSC_EEPROM_CMD_BUSY | SMSC_EEPROM_CMD_TIMEOUT)) { smsc_warn_printf(sc, "eeprom command failed\n"); err = USB_ERR_IOERROR; break; } if ((err = smsc_read_reg(sc, SMSC_EEPROM_DATA, &val)) != 0) goto done; buf[i] = (val & 0xff); } done: if (!locked) SMSC_UNLOCK(sc); return (err); } /** * smsc_miibus_readreg - Reads a MII/MDIO register * @dev: usb ether device * @phy: the number of phy reading from * @reg: the register address * * Attempts to read a phy register over the MII bus. * * LOCKING: * Takes and releases the device mutex lock if not already held. * * RETURNS: * Returns the 16-bits read from the MII register, if this function fails 0 * is returned. */ static int smsc_miibus_readreg(device_t dev, int phy, int reg) { struct smsc_softc *sc = device_get_softc(dev); int locked; uint32_t addr; uint32_t val = 0; locked = mtx_owned(&sc->sc_mtx); if (!locked) SMSC_LOCK(sc); if (smsc_wait_for_bits(sc, SMSC_MII_ADDR, SMSC_MII_BUSY) != 0) { smsc_warn_printf(sc, "MII is busy\n"); goto done; } addr = (phy << 11) | (reg << 6) | SMSC_MII_READ | SMSC_MII_BUSY; smsc_write_reg(sc, SMSC_MII_ADDR, addr); if (smsc_wait_for_bits(sc, SMSC_MII_ADDR, SMSC_MII_BUSY) != 0) smsc_warn_printf(sc, "MII read timeout\n"); smsc_read_reg(sc, SMSC_MII_DATA, &val); val = le32toh(val); done: if (!locked) SMSC_UNLOCK(sc); return (val & 0xFFFF); } /** * smsc_miibus_writereg - Writes a MII/MDIO register * @dev: usb ether device * @phy: the number of phy writing to * @reg: the register address * @val: the value to write * * Attempts to write a phy register over the MII bus. * * LOCKING: * Takes and releases the device mutex lock if not already held. * * RETURNS: * Always returns 0 regardless of success or failure. */ static int smsc_miibus_writereg(device_t dev, int phy, int reg, int val) { struct smsc_softc *sc = device_get_softc(dev); int locked; uint32_t addr; if (sc->sc_phyno != phy) return (0); locked = mtx_owned(&sc->sc_mtx); if (!locked) SMSC_LOCK(sc); if (smsc_wait_for_bits(sc, SMSC_MII_ADDR, SMSC_MII_BUSY) != 0) { smsc_warn_printf(sc, "MII is busy\n"); goto done; } val = htole32(val); smsc_write_reg(sc, SMSC_MII_DATA, val); addr = (phy << 11) | (reg << 6) | SMSC_MII_WRITE | SMSC_MII_BUSY; smsc_write_reg(sc, SMSC_MII_ADDR, addr); if (smsc_wait_for_bits(sc, SMSC_MII_ADDR, SMSC_MII_BUSY) != 0) smsc_warn_printf(sc, "MII write timeout\n"); done: if (!locked) SMSC_UNLOCK(sc); return (0); } /** * smsc_miibus_statchg - Called to detect phy status change * @dev: usb ether device * * This function is called periodically by the system to poll for status * changes of the link. * * LOCKING: * Takes and releases the device mutex lock if not already held. */ static void smsc_miibus_statchg(device_t dev) { struct smsc_softc *sc = device_get_softc(dev); struct mii_data *mii = uether_getmii(&sc->sc_ue); struct ifnet *ifp; int locked; int err; uint32_t flow; uint32_t afc_cfg; locked = mtx_owned(&sc->sc_mtx); if (!locked) SMSC_LOCK(sc); ifp = uether_getifp(&sc->sc_ue); if (mii == NULL || ifp == NULL || (ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) goto done; /* Use the MII status to determine link status */ sc->sc_flags &= ~SMSC_FLAG_LINK; if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) == (IFM_ACTIVE | IFM_AVALID)) { switch (IFM_SUBTYPE(mii->mii_media_active)) { case IFM_10_T: case IFM_100_TX: sc->sc_flags |= SMSC_FLAG_LINK; break; case IFM_1000_T: /* Gigabit ethernet not supported by chipset */ break; default: break; } } /* Lost link, do nothing. */ if ((sc->sc_flags & SMSC_FLAG_LINK) == 0) { smsc_dbg_printf(sc, "link flag not set\n"); goto done; } err = smsc_read_reg(sc, SMSC_AFC_CFG, &afc_cfg); if (err) { smsc_warn_printf(sc, "failed to read initial AFC_CFG, error %d\n", err); goto done; } /* Enable/disable full duplex operation and TX/RX pause */ if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0) { smsc_dbg_printf(sc, "full duplex operation\n"); sc->sc_mac_csr &= ~SMSC_MAC_CSR_RCVOWN; sc->sc_mac_csr |= SMSC_MAC_CSR_FDPX; if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_RXPAUSE) != 0) flow = 0xffff0002; else flow = 0; if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_TXPAUSE) != 0) afc_cfg |= 0xf; else afc_cfg &= ~0xf; } else { smsc_dbg_printf(sc, "half duplex operation\n"); sc->sc_mac_csr &= ~SMSC_MAC_CSR_FDPX; sc->sc_mac_csr |= SMSC_MAC_CSR_RCVOWN; flow = 0; afc_cfg |= 0xf; } err = smsc_write_reg(sc, SMSC_MAC_CSR, sc->sc_mac_csr); err += smsc_write_reg(sc, SMSC_FLOW, flow); err += smsc_write_reg(sc, SMSC_AFC_CFG, afc_cfg); if (err) smsc_warn_printf(sc, "media change failed, error %d\n", err); done: if (!locked) SMSC_UNLOCK(sc); } /** * smsc_ifmedia_upd - Set media options * @ifp: interface pointer * * Basically boilerplate code that simply calls the mii functions to set the * media options. * * LOCKING: * The device lock must be held before this function is called. * * RETURNS: * Returns 0 on success or a negative error code. */ static int smsc_ifmedia_upd(struct ifnet *ifp) { struct smsc_softc *sc = ifp->if_softc; struct mii_data *mii = uether_getmii(&sc->sc_ue); struct mii_softc *miisc; int err; SMSC_LOCK_ASSERT(sc, MA_OWNED); LIST_FOREACH(miisc, &mii->mii_phys, mii_list) PHY_RESET(miisc); err = mii_mediachg(mii); return (err); } /** * smsc_ifmedia_sts - Report current media status * @ifp: inet interface pointer * @ifmr: interface media request * * Basically boilerplate code that simply calls the mii functions to get the * media status. * * LOCKING: * Internally takes and releases the device lock. */ static void smsc_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) { struct smsc_softc *sc = ifp->if_softc; struct mii_data *mii = uether_getmii(&sc->sc_ue); SMSC_LOCK(sc); mii_pollstat(mii); ifmr->ifm_active = mii->mii_media_active; ifmr->ifm_status = mii->mii_media_status; SMSC_UNLOCK(sc); } /** * smsc_hash - Calculate the hash of a mac address * @addr: The mac address to calculate the hash on * * This function is used when configuring a range of m'cast mac addresses to * filter on. The hash of the mac address is put in the device's mac hash * table. * * RETURNS: * Returns a value from 0-63 value which is the hash of the mac address. */ static inline uint32_t smsc_hash(uint8_t addr[ETHER_ADDR_LEN]) { return (ether_crc32_be(addr, ETHER_ADDR_LEN) >> 26) & 0x3f; } /** * smsc_setmulti - Setup multicast * @ue: usb ethernet device context * * Tells the device to either accept frames with a multicast mac address, a * select group of m'cast mac addresses or just the devices mac address. * * LOCKING: * Should be called with the SMSC lock held. */ static void smsc_setmulti(struct usb_ether *ue) { struct smsc_softc *sc = uether_getsc(ue); struct ifnet *ifp = uether_getifp(ue); struct ifmultiaddr *ifma; uint32_t hashtbl[2] = { 0, 0 }; uint32_t hash; SMSC_LOCK_ASSERT(sc, MA_OWNED); if (ifp->if_flags & (IFF_ALLMULTI | IFF_PROMISC)) { smsc_dbg_printf(sc, "receive all multicast enabled\n"); sc->sc_mac_csr |= SMSC_MAC_CSR_MCPAS; sc->sc_mac_csr &= ~SMSC_MAC_CSR_HPFILT; } else { /* Take the lock of the mac address list before hashing each of them */ if_maddr_rlock(ifp); if (!CK_STAILQ_EMPTY(&ifp->if_multiaddrs)) { /* We are filtering on a set of address so calculate hashes of each * of the address and set the corresponding bits in the register. */ sc->sc_mac_csr |= SMSC_MAC_CSR_HPFILT; sc->sc_mac_csr &= ~(SMSC_MAC_CSR_PRMS | SMSC_MAC_CSR_MCPAS); CK_STAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { if (ifma->ifma_addr->sa_family != AF_LINK) continue; hash = smsc_hash(LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); hashtbl[hash >> 5] |= 1 << (hash & 0x1F); } } else { /* Only receive packets with destination set to our mac address */ sc->sc_mac_csr &= ~(SMSC_MAC_CSR_MCPAS | SMSC_MAC_CSR_HPFILT); } if_maddr_runlock(ifp); /* Debug */ if (sc->sc_mac_csr & SMSC_MAC_CSR_HPFILT) smsc_dbg_printf(sc, "receive select group of macs\n"); else smsc_dbg_printf(sc, "receive own packets only\n"); } /* Write the hash table and mac control registers */ smsc_write_reg(sc, SMSC_HASHH, hashtbl[1]); smsc_write_reg(sc, SMSC_HASHL, hashtbl[0]); smsc_write_reg(sc, SMSC_MAC_CSR, sc->sc_mac_csr); } /** * smsc_setpromisc - Enables/disables promiscuous mode * @ue: usb ethernet device context * * LOCKING: * Should be called with the SMSC lock held. */ static void smsc_setpromisc(struct usb_ether *ue) { struct smsc_softc *sc = uether_getsc(ue); struct ifnet *ifp = uether_getifp(ue); smsc_dbg_printf(sc, "promiscuous mode %sabled\n", (ifp->if_flags & IFF_PROMISC) ? "en" : "dis"); SMSC_LOCK_ASSERT(sc, MA_OWNED); if (ifp->if_flags & IFF_PROMISC) sc->sc_mac_csr |= SMSC_MAC_CSR_PRMS; else sc->sc_mac_csr &= ~SMSC_MAC_CSR_PRMS; smsc_write_reg(sc, SMSC_MAC_CSR, sc->sc_mac_csr); } /** * smsc_sethwcsum - Enable or disable H/W UDP and TCP checksumming * @sc: driver soft context * * LOCKING: * Should be called with the SMSC lock held. * * RETURNS: * Returns 0 on success or a negative error code. */ static int smsc_sethwcsum(struct smsc_softc *sc) { struct ifnet *ifp = uether_getifp(&sc->sc_ue); uint32_t val; int err; if (!ifp) return (-EIO); SMSC_LOCK_ASSERT(sc, MA_OWNED); err = smsc_read_reg(sc, SMSC_COE_CTRL, &val); if (err != 0) { smsc_warn_printf(sc, "failed to read SMSC_COE_CTRL (err=%d)\n", err); return (err); } /* Enable/disable the Rx checksum */ if ((ifp->if_capabilities & ifp->if_capenable) & IFCAP_RXCSUM) val |= SMSC_COE_CTRL_RX_EN; else val &= ~SMSC_COE_CTRL_RX_EN; /* Enable/disable the Tx checksum (currently not supported) */ if ((ifp->if_capabilities & ifp->if_capenable) & IFCAP_TXCSUM) val |= SMSC_COE_CTRL_TX_EN; else val &= ~SMSC_COE_CTRL_TX_EN; err = smsc_write_reg(sc, SMSC_COE_CTRL, val); if (err != 0) { smsc_warn_printf(sc, "failed to write SMSC_COE_CTRL (err=%d)\n", err); return (err); } return (0); } /** * smsc_setmacaddress - Sets the mac address in the device * @sc: driver soft context * @addr: pointer to array contain at least 6 bytes of the mac * * Writes the MAC address into the device, usually the MAC is programmed with * values from the EEPROM. * * LOCKING: * Should be called with the SMSC lock held. * * RETURNS: * Returns 0 on success or a negative error code. */ static int smsc_setmacaddress(struct smsc_softc *sc, const uint8_t *addr) { int err; uint32_t val; smsc_dbg_printf(sc, "setting mac address to %02x:%02x:%02x:%02x:%02x:%02x\n", addr[0], addr[1], addr[2], addr[3], addr[4], addr[5]); SMSC_LOCK_ASSERT(sc, MA_OWNED); val = (addr[3] << 24) | (addr[2] << 16) | (addr[1] << 8) | addr[0]; if ((err = smsc_write_reg(sc, SMSC_MAC_ADDRL, val)) != 0) goto done; val = (addr[5] << 8) | addr[4]; err = smsc_write_reg(sc, SMSC_MAC_ADDRH, val); done: return (err); } /** * smsc_reset - Reset the SMSC chip * @sc: device soft context * * LOCKING: * Should be called with the SMSC lock held. */ static void smsc_reset(struct smsc_softc *sc) { struct usb_config_descriptor *cd; usb_error_t err; cd = usbd_get_config_descriptor(sc->sc_ue.ue_udev); err = usbd_req_set_config(sc->sc_ue.ue_udev, &sc->sc_mtx, cd->bConfigurationValue); if (err) smsc_warn_printf(sc, "reset failed (ignored)\n"); /* Wait a little while for the chip to get its brains in order. */ uether_pause(&sc->sc_ue, hz / 100); /* Reinitialize controller to achieve full reset. */ smsc_chip_init(sc); } /** * smsc_init - Initialises the LAN95xx chip * @ue: USB ether interface * * Called when the interface is brought up (i.e. ifconfig ue0 up), this * initialise the interface and the rx/tx pipes. * * LOCKING: * Should be called with the SMSC lock held. */ static void smsc_init(struct usb_ether *ue) { struct smsc_softc *sc = uether_getsc(ue); struct ifnet *ifp = uether_getifp(ue); SMSC_LOCK_ASSERT(sc, MA_OWNED); if (smsc_setmacaddress(sc, IF_LLADDR(ifp))) smsc_dbg_printf(sc, "setting MAC address failed\n"); if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) return; /* Cancel pending I/O */ smsc_stop(ue); #if __FreeBSD_version <= 1000000 /* On earlier versions this was the first place we could tell the system * that we supported h/w csuming, however this is only called after the * the interface has been brought up - not ideal. */ if (!(ifp->if_capabilities & IFCAP_RXCSUM)) { ifp->if_capabilities |= IFCAP_RXCSUM; ifp->if_capenable |= IFCAP_RXCSUM; ifp->if_hwassist = 0; } /* TX checksuming is disabled for now ifp->if_capabilities |= IFCAP_TXCSUM; ifp->if_capenable |= IFCAP_TXCSUM; ifp->if_hwassist = CSUM_TCP | CSUM_UDP; */ #endif /* Reset the ethernet interface. */ smsc_reset(sc); /* Load the multicast filter. */ smsc_setmulti(ue); /* TCP/UDP checksum offload engines. */ smsc_sethwcsum(sc); usbd_xfer_set_stall(sc->sc_xfer[SMSC_BULK_DT_WR]); /* Indicate we are up and running. */ ifp->if_drv_flags |= IFF_DRV_RUNNING; /* Switch to selected media. */ smsc_ifmedia_upd(ifp); smsc_start(ue); } /** * smsc_bulk_read_callback - Read callback used to process the USB URB * @xfer: the USB transfer * @error: * * Reads the URB data which can contain one or more ethernet frames, the * frames are copyed into a mbuf and given to the system. * * LOCKING: * No locking required, doesn't access internal driver settings. */ static void smsc_bulk_read_callback(struct usb_xfer *xfer, usb_error_t error) { struct smsc_softc *sc = usbd_xfer_softc(xfer); struct usb_ether *ue = &sc->sc_ue; struct ifnet *ifp = uether_getifp(ue); struct mbuf *m; struct usb_page_cache *pc; uint32_t rxhdr; uint16_t pktlen; int off; int actlen; usbd_xfer_status(xfer, &actlen, NULL, NULL, NULL); smsc_dbg_printf(sc, "rx : actlen %d\n", actlen); switch (USB_GET_STATE(xfer)) { case USB_ST_TRANSFERRED: /* There is always a zero length frame after bringing the IF up */ if (actlen < (sizeof(rxhdr) + ETHER_CRC_LEN)) goto tr_setup; /* There maybe multiple packets in the USB frame, each will have a * header and each needs to have it's own mbuf allocated and populated * for it. */ pc = usbd_xfer_get_frame(xfer, 0); off = 0; while (off < actlen) { /* The frame header is always aligned on a 4 byte boundary */ off = ((off + 0x3) & ~0x3); usbd_copy_out(pc, off, &rxhdr, sizeof(rxhdr)); off += (sizeof(rxhdr) + ETHER_ALIGN); rxhdr = le32toh(rxhdr); pktlen = (uint16_t)SMSC_RX_STAT_FRM_LENGTH(rxhdr); smsc_dbg_printf(sc, "rx : rxhdr 0x%08x : pktlen %d : actlen %d : " "off %d\n", rxhdr, pktlen, actlen, off); if (rxhdr & SMSC_RX_STAT_ERROR) { smsc_dbg_printf(sc, "rx error (hdr 0x%08x)\n", rxhdr); if_inc_counter(ifp, IFCOUNTER_IERRORS, 1); if (rxhdr & SMSC_RX_STAT_COLLISION) if_inc_counter(ifp, IFCOUNTER_COLLISIONS, 1); } else { /* Check if the ethernet frame is too big or too small */ if ((pktlen < ETHER_HDR_LEN) || (pktlen > (actlen - off))) goto tr_setup; /* Create a new mbuf to store the packet in */ m = uether_newbuf(); if (m == NULL) { smsc_warn_printf(sc, "failed to create new mbuf\n"); if_inc_counter(ifp, IFCOUNTER_IQDROPS, 1); goto tr_setup; } usbd_copy_out(pc, off, mtod(m, uint8_t *), pktlen); /* Check if RX TCP/UDP checksumming is being offloaded */ if ((ifp->if_capenable & IFCAP_RXCSUM) != 0) { struct ether_header *eh; eh = mtod(m, struct ether_header *); /* Remove the extra 2 bytes of the csum */ pktlen -= 2; /* The checksum appears to be simplistically calculated * over the udp/tcp header and data up to the end of the * eth frame. Which means if the eth frame is padded * the csum calculation is incorrectly performed over * the padding bytes as well. Therefore to be safe we * ignore the H/W csum on frames less than or equal to * 64 bytes. * * Ignore H/W csum for non-IPv4 packets. */ if ((be16toh(eh->ether_type) == ETHERTYPE_IP) && (pktlen > ETHER_MIN_LEN)) { struct ip *ip; ip = (struct ip *)(eh + 1); if ((ip->ip_v == IPVERSION) && ((ip->ip_p == IPPROTO_TCP) || (ip->ip_p == IPPROTO_UDP))) { /* Indicate the UDP/TCP csum has been calculated */ m->m_pkthdr.csum_flags |= CSUM_DATA_VALID; /* Copy the TCP/UDP checksum from the last 2 bytes * of the transfer and put in the csum_data field. */ usbd_copy_out(pc, (off + pktlen), &m->m_pkthdr.csum_data, 2); /* The data is copied in network order, but the * csum algorithm in the kernel expects it to be * in host network order. */ m->m_pkthdr.csum_data = ntohs(m->m_pkthdr.csum_data); smsc_dbg_printf(sc, "RX checksum offloaded (0x%04x)\n", m->m_pkthdr.csum_data); } } /* Need to adjust the offset as well or we'll be off * by 2 because the csum is removed from the packet * length. */ off += 2; } /* Finally enqueue the mbuf on the receive queue */ /* Remove 4 trailing bytes */ if (pktlen < (4 + ETHER_HDR_LEN)) { m_freem(m); goto tr_setup; } uether_rxmbuf(ue, m, pktlen - 4); } /* Update the offset to move to the next potential packet */ off += pktlen; } /* FALLTHROUGH */ case USB_ST_SETUP: tr_setup: usbd_xfer_set_frame_len(xfer, 0, usbd_xfer_max_len(xfer)); usbd_transfer_submit(xfer); uether_rxflush(ue); return; default: if (error != USB_ERR_CANCELLED) { smsc_warn_printf(sc, "bulk read error, %s\n", usbd_errstr(error)); usbd_xfer_set_stall(xfer); goto tr_setup; } return; } } /** * smsc_bulk_write_callback - Write callback used to send ethernet frame(s) * @xfer: the USB transfer * @error: error code if the transfers is in an errored state * * The main write function that pulls ethernet frames off the queue and sends * them out. * * LOCKING: * */ static void smsc_bulk_write_callback(struct usb_xfer *xfer, usb_error_t error) { struct smsc_softc *sc = usbd_xfer_softc(xfer); struct ifnet *ifp = uether_getifp(&sc->sc_ue); struct usb_page_cache *pc; struct mbuf *m; uint32_t txhdr; uint32_t frm_len = 0; int nframes; switch (USB_GET_STATE(xfer)) { case USB_ST_TRANSFERRED: ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; /* FALLTHROUGH */ case USB_ST_SETUP: tr_setup: if ((sc->sc_flags & SMSC_FLAG_LINK) == 0 || (ifp->if_drv_flags & IFF_DRV_OACTIVE) != 0) { /* Don't send anything if there is no link or controller is busy. */ return; } for (nframes = 0; nframes < 16 && !IFQ_DRV_IS_EMPTY(&ifp->if_snd); nframes++) { IFQ_DRV_DEQUEUE(&ifp->if_snd, m); if (m == NULL) break; usbd_xfer_set_frame_offset(xfer, nframes * MCLBYTES, nframes); frm_len = 0; pc = usbd_xfer_get_frame(xfer, nframes); /* Each frame is prefixed with two 32-bit values describing the * length of the packet and buffer. */ txhdr = SMSC_TX_CTRL_0_BUF_SIZE(m->m_pkthdr.len) | SMSC_TX_CTRL_0_FIRST_SEG | SMSC_TX_CTRL_0_LAST_SEG; txhdr = htole32(txhdr); usbd_copy_in(pc, 0, &txhdr, sizeof(txhdr)); txhdr = SMSC_TX_CTRL_1_PKT_LENGTH(m->m_pkthdr.len); txhdr = htole32(txhdr); usbd_copy_in(pc, 4, &txhdr, sizeof(txhdr)); frm_len += 8; /* Next copy in the actual packet */ usbd_m_copy_in(pc, frm_len, m, 0, m->m_pkthdr.len); frm_len += m->m_pkthdr.len; if_inc_counter(ifp, IFCOUNTER_OPACKETS, 1); /* If there's a BPF listener, bounce a copy of this frame to him */ BPF_MTAP(ifp, m); m_freem(m); /* Set frame length. */ usbd_xfer_set_frame_len(xfer, nframes, frm_len); } if (nframes != 0) { usbd_xfer_set_frames(xfer, nframes); usbd_transfer_submit(xfer); ifp->if_drv_flags |= IFF_DRV_OACTIVE; } return; default: if_inc_counter(ifp, IFCOUNTER_OERRORS, 1); ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; if (error != USB_ERR_CANCELLED) { smsc_err_printf(sc, "usb error on tx: %s\n", usbd_errstr(error)); usbd_xfer_set_stall(xfer); goto tr_setup; } return; } } /** * smsc_tick - Called periodically to monitor the state of the LAN95xx chip * @ue: USB ether interface * * Simply calls the mii status functions to check the state of the link. * * LOCKING: * Should be called with the SMSC lock held. */ static void smsc_tick(struct usb_ether *ue) { struct smsc_softc *sc = uether_getsc(ue); struct mii_data *mii = uether_getmii(&sc->sc_ue); SMSC_LOCK_ASSERT(sc, MA_OWNED); mii_tick(mii); if ((sc->sc_flags & SMSC_FLAG_LINK) == 0) { smsc_miibus_statchg(ue->ue_dev); if ((sc->sc_flags & SMSC_FLAG_LINK) != 0) smsc_start(ue); } } /** * smsc_start - Starts communication with the LAN95xx chip * @ue: USB ether interface * * * */ static void smsc_start(struct usb_ether *ue) { struct smsc_softc *sc = uether_getsc(ue); /* * start the USB transfers, if not already started: */ usbd_transfer_start(sc->sc_xfer[SMSC_BULK_DT_RD]); usbd_transfer_start(sc->sc_xfer[SMSC_BULK_DT_WR]); } /** * smsc_stop - Stops communication with the LAN95xx chip * @ue: USB ether interface * * * */ static void smsc_stop(struct usb_ether *ue) { struct smsc_softc *sc = uether_getsc(ue); struct ifnet *ifp = uether_getifp(ue); SMSC_LOCK_ASSERT(sc, MA_OWNED); ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); sc->sc_flags &= ~SMSC_FLAG_LINK; /* * stop all the transfers, if not already stopped: */ usbd_transfer_stop(sc->sc_xfer[SMSC_BULK_DT_WR]); usbd_transfer_stop(sc->sc_xfer[SMSC_BULK_DT_RD]); } /** * smsc_phy_init - Initialises the in-built SMSC phy * @sc: driver soft context * * Resets the PHY part of the chip and then initialises it to default * values. The 'link down' and 'auto-negotiation complete' interrupts * from the PHY are also enabled, however we don't monitor the interrupt * endpoints for the moment. * * RETURNS: * Returns 0 on success or EIO if failed to reset the PHY. */ static int smsc_phy_init(struct smsc_softc *sc) { int bmcr; usb_ticks_t start_ticks; const usb_ticks_t max_ticks = USB_MS_TO_TICKS(1000); SMSC_LOCK_ASSERT(sc, MA_OWNED); /* Reset phy and wait for reset to complete */ smsc_miibus_writereg(sc->sc_ue.ue_dev, sc->sc_phyno, MII_BMCR, BMCR_RESET); start_ticks = ticks; do { uether_pause(&sc->sc_ue, hz / 100); bmcr = smsc_miibus_readreg(sc->sc_ue.ue_dev, sc->sc_phyno, MII_BMCR); } while ((bmcr & BMCR_RESET) && ((ticks - start_ticks) < max_ticks)); if (((usb_ticks_t)(ticks - start_ticks)) >= max_ticks) { smsc_err_printf(sc, "PHY reset timed-out"); return (EIO); } smsc_miibus_writereg(sc->sc_ue.ue_dev, sc->sc_phyno, MII_ANAR, ANAR_10 | ANAR_10_FD | ANAR_TX | ANAR_TX_FD | /* all modes */ ANAR_CSMA | ANAR_FC | ANAR_PAUSE_ASYM); /* Setup the phy to interrupt when the link goes down or autoneg completes */ smsc_miibus_readreg(sc->sc_ue.ue_dev, sc->sc_phyno, SMSC_PHY_INTR_STAT); smsc_miibus_writereg(sc->sc_ue.ue_dev, sc->sc_phyno, SMSC_PHY_INTR_MASK, (SMSC_PHY_INTR_ANEG_COMP | SMSC_PHY_INTR_LINK_DOWN)); /* Restart auto-negotation */ bmcr = smsc_miibus_readreg(sc->sc_ue.ue_dev, sc->sc_phyno, MII_BMCR); bmcr |= BMCR_STARTNEG; smsc_miibus_writereg(sc->sc_ue.ue_dev, sc->sc_phyno, MII_BMCR, bmcr); return (0); } /** * smsc_chip_init - Initialises the chip after power on * @sc: driver soft context * * This initialisation sequence is modelled on the procedure in the Linux * driver. * * RETURNS: * Returns 0 on success or an error code on failure. */ static int smsc_chip_init(struct smsc_softc *sc) { int err; int locked; uint32_t reg_val; int burst_cap; locked = mtx_owned(&sc->sc_mtx); if (!locked) SMSC_LOCK(sc); /* Enter H/W config mode */ smsc_write_reg(sc, SMSC_HW_CFG, SMSC_HW_CFG_LRST); if ((err = smsc_wait_for_bits(sc, SMSC_HW_CFG, SMSC_HW_CFG_LRST)) != 0) { smsc_warn_printf(sc, "timed-out waiting for reset to complete\n"); goto init_failed; } /* Reset the PHY */ smsc_write_reg(sc, SMSC_PM_CTRL, SMSC_PM_CTRL_PHY_RST); if ((err = smsc_wait_for_bits(sc, SMSC_PM_CTRL, SMSC_PM_CTRL_PHY_RST)) != 0) { smsc_warn_printf(sc, "timed-out waiting for phy reset to complete\n"); goto init_failed; } /* Set the mac address */ if ((err = smsc_setmacaddress(sc, sc->sc_ue.ue_eaddr)) != 0) { smsc_warn_printf(sc, "failed to set the MAC address\n"); goto init_failed; } /* Don't know what the HW_CFG_BIR bit is, but following the reset sequence * as used in the Linux driver. */ if ((err = smsc_read_reg(sc, SMSC_HW_CFG, ®_val)) != 0) { smsc_warn_printf(sc, "failed to read HW_CFG: %d\n", err); goto init_failed; } reg_val |= SMSC_HW_CFG_BIR; smsc_write_reg(sc, SMSC_HW_CFG, reg_val); /* There is a so called 'turbo mode' that the linux driver supports, it * seems to allow you to jam multiple frames per Rx transaction. By default * this driver supports that and therefore allows multiple frames per URB. * * The xfer buffer size needs to reflect this as well, therefore based on * the calculations in the Linux driver the RX bufsize is set to 18944, * bufsz = (16 * 1024 + 5 * 512) * * Burst capability is the number of URBs that can be in a burst of data/ * ethernet frames. */ if (usbd_get_speed(sc->sc_ue.ue_udev) == USB_SPEED_HIGH) burst_cap = 37; else burst_cap = 128; smsc_write_reg(sc, SMSC_BURST_CAP, burst_cap); /* Set the default bulk in delay (magic value from Linux driver) */ smsc_write_reg(sc, SMSC_BULK_IN_DLY, 0x00002000); /* * Initialise the RX interface */ if ((err = smsc_read_reg(sc, SMSC_HW_CFG, ®_val)) < 0) { smsc_warn_printf(sc, "failed to read HW_CFG: (err = %d)\n", err); goto init_failed; } /* Adjust the packet offset in the buffer (designed to try and align IP * header on 4 byte boundary) */ reg_val &= ~SMSC_HW_CFG_RXDOFF; reg_val |= (ETHER_ALIGN << 9) & SMSC_HW_CFG_RXDOFF; /* The following setings are used for 'turbo mode', a.k.a multiple frames * per Rx transaction (again info taken form Linux driver). */ reg_val |= (SMSC_HW_CFG_MEF | SMSC_HW_CFG_BCE); smsc_write_reg(sc, SMSC_HW_CFG, reg_val); /* Clear the status register ? */ smsc_write_reg(sc, SMSC_INTR_STATUS, 0xffffffff); /* Read and display the revision register */ if ((err = smsc_read_reg(sc, SMSC_ID_REV, &sc->sc_rev_id)) < 0) { smsc_warn_printf(sc, "failed to read ID_REV (err = %d)\n", err); goto init_failed; } device_printf(sc->sc_ue.ue_dev, "chip 0x%04lx, rev. %04lx\n", (sc->sc_rev_id & SMSC_ID_REV_CHIP_ID_MASK) >> 16, (sc->sc_rev_id & SMSC_ID_REV_CHIP_REV_MASK)); /* GPIO/LED setup */ reg_val = SMSC_LED_GPIO_CFG_SPD_LED | SMSC_LED_GPIO_CFG_LNK_LED | SMSC_LED_GPIO_CFG_FDX_LED; smsc_write_reg(sc, SMSC_LED_GPIO_CFG, reg_val); /* * Initialise the TX interface */ smsc_write_reg(sc, SMSC_FLOW, 0); smsc_write_reg(sc, SMSC_AFC_CFG, AFC_CFG_DEFAULT); /* Read the current MAC configuration */ if ((err = smsc_read_reg(sc, SMSC_MAC_CSR, &sc->sc_mac_csr)) < 0) { smsc_warn_printf(sc, "failed to read MAC_CSR (err=%d)\n", err); goto init_failed; } /* Vlan */ smsc_write_reg(sc, SMSC_VLAN1, (uint32_t)ETHERTYPE_VLAN); /* * Initialise the PHY */ if ((err = smsc_phy_init(sc)) != 0) goto init_failed; /* * Start TX */ sc->sc_mac_csr |= SMSC_MAC_CSR_TXEN; smsc_write_reg(sc, SMSC_MAC_CSR, sc->sc_mac_csr); smsc_write_reg(sc, SMSC_TX_CFG, SMSC_TX_CFG_ON); /* * Start RX */ sc->sc_mac_csr |= SMSC_MAC_CSR_RXEN; smsc_write_reg(sc, SMSC_MAC_CSR, sc->sc_mac_csr); if (!locked) SMSC_UNLOCK(sc); return (0); init_failed: if (!locked) SMSC_UNLOCK(sc); smsc_err_printf(sc, "smsc_chip_init failed (err=%d)\n", err); return (err); } /** * smsc_ioctl - ioctl function for the device * @ifp: interface pointer * @cmd: the ioctl command * @data: data passed in the ioctl call, typically a pointer to struct ifreq. * * The ioctl routine is overridden to detect change requests for the H/W * checksum capabilities. * * RETURNS: * 0 on success and an error code on failure. */ static int smsc_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data) { struct usb_ether *ue = ifp->if_softc; struct smsc_softc *sc; struct ifreq *ifr; int rc; int mask; int reinit; if (cmd == SIOCSIFCAP) { sc = uether_getsc(ue); ifr = (struct ifreq *)data; SMSC_LOCK(sc); rc = 0; reinit = 0; mask = ifr->ifr_reqcap ^ ifp->if_capenable; /* Modify the RX CSUM enable bits */ if ((mask & IFCAP_RXCSUM) != 0 && (ifp->if_capabilities & IFCAP_RXCSUM) != 0) { ifp->if_capenable ^= IFCAP_RXCSUM; if (ifp->if_drv_flags & IFF_DRV_RUNNING) { ifp->if_drv_flags &= ~IFF_DRV_RUNNING; reinit = 1; } } SMSC_UNLOCK(sc); if (reinit) #if __FreeBSD_version > 1000000 uether_init(ue); #else ifp->if_init(ue); #endif } else { rc = uether_ioctl(ifp, cmd, data); } return (rc); } /** * smsc_attach_post - Called after the driver attached to the USB interface * @ue: the USB ethernet device * * This is where the chip is intialised for the first time. This is different * from the smsc_init() function in that that one is designed to setup the * H/W to match the UE settings and can be called after a reset. * * */ static void smsc_attach_post(struct usb_ether *ue) { struct smsc_softc *sc = uether_getsc(ue); uint32_t mac_h, mac_l; int err; smsc_dbg_printf(sc, "smsc_attach_post\n"); /* Setup some of the basics */ sc->sc_phyno = 1; /* Attempt to get the mac address, if an EEPROM is not attached this * will just return FF:FF:FF:FF:FF:FF, so in such cases we invent a MAC * address based on urandom. */ memset(sc->sc_ue.ue_eaddr, 0xff, ETHER_ADDR_LEN); /* Check if there is already a MAC address in the register */ if ((smsc_read_reg(sc, SMSC_MAC_ADDRL, &mac_l) == 0) && (smsc_read_reg(sc, SMSC_MAC_ADDRH, &mac_h) == 0)) { sc->sc_ue.ue_eaddr[5] = (uint8_t)((mac_h >> 8) & 0xff); sc->sc_ue.ue_eaddr[4] = (uint8_t)((mac_h) & 0xff); sc->sc_ue.ue_eaddr[3] = (uint8_t)((mac_l >> 24) & 0xff); sc->sc_ue.ue_eaddr[2] = (uint8_t)((mac_l >> 16) & 0xff); sc->sc_ue.ue_eaddr[1] = (uint8_t)((mac_l >> 8) & 0xff); sc->sc_ue.ue_eaddr[0] = (uint8_t)((mac_l) & 0xff); } /* MAC address is not set so try to read from EEPROM, if that fails generate * a random MAC address. */ if (!ETHER_IS_VALID(sc->sc_ue.ue_eaddr)) { err = smsc_eeprom_read(sc, 0x01, sc->sc_ue.ue_eaddr, ETHER_ADDR_LEN); #ifdef FDT if ((err != 0) || (!ETHER_IS_VALID(sc->sc_ue.ue_eaddr))) err = usb_fdt_get_mac_addr(sc->sc_ue.ue_dev, &sc->sc_ue); #endif if ((err != 0) || (!ETHER_IS_VALID(sc->sc_ue.ue_eaddr))) { read_random(sc->sc_ue.ue_eaddr, ETHER_ADDR_LEN); sc->sc_ue.ue_eaddr[0] &= ~0x01; /* unicast */ sc->sc_ue.ue_eaddr[0] |= 0x02; /* locally administered */ } } /* Initialise the chip for the first time */ smsc_chip_init(sc); } /** * smsc_attach_post_sub - Called after the driver attached to the USB interface * @ue: the USB ethernet device * * Most of this is boilerplate code and copied from the base USB ethernet * driver. It has been overriden so that we can indicate to the system that * the chip supports H/W checksumming. * * RETURNS: * Returns 0 on success or a negative error code. */ #if __FreeBSD_version > 1000000 static int smsc_attach_post_sub(struct usb_ether *ue) { struct smsc_softc *sc; struct ifnet *ifp; int error; sc = uether_getsc(ue); ifp = ue->ue_ifp; ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; ifp->if_start = uether_start; ifp->if_ioctl = smsc_ioctl; ifp->if_init = uether_init; IFQ_SET_MAXLEN(&ifp->if_snd, ifqmaxlen); ifp->if_snd.ifq_drv_maxlen = ifqmaxlen; IFQ_SET_READY(&ifp->if_snd); /* The chip supports TCP/UDP checksum offloading on TX and RX paths, however * currently only RX checksum is supported in the driver (see top of file). */ ifp->if_capabilities |= IFCAP_RXCSUM | IFCAP_VLAN_MTU; ifp->if_hwassist = 0; /* TX checksuming is disabled (for now?) ifp->if_capabilities |= IFCAP_TXCSUM; ifp->if_capenable |= IFCAP_TXCSUM; ifp->if_hwassist = CSUM_TCP | CSUM_UDP; */ ifp->if_capenable = ifp->if_capabilities; mtx_lock(&Giant); error = mii_attach(ue->ue_dev, &ue->ue_miibus, ifp, uether_ifmedia_upd, ue->ue_methods->ue_mii_sts, BMSR_DEFCAPMASK, sc->sc_phyno, MII_OFFSET_ANY, 0); mtx_unlock(&Giant); return (error); } #endif /* __FreeBSD_version > 1000000 */ /** * smsc_probe - Probe the interface. * @dev: smsc device handle * * Checks if the device is a match for this driver. * * RETURNS: * Returns 0 on success or an error code on failure. */ static int smsc_probe(device_t dev) { struct usb_attach_arg *uaa = device_get_ivars(dev); if (uaa->usb_mode != USB_MODE_HOST) return (ENXIO); if (uaa->info.bConfigIndex != SMSC_CONFIG_INDEX) return (ENXIO); if (uaa->info.bIfaceIndex != SMSC_IFACE_IDX) return (ENXIO); return (usbd_lookup_id_by_uaa(smsc_devs, sizeof(smsc_devs), uaa)); } /** * smsc_attach - Attach the interface. * @dev: smsc device handle * * Allocate softc structures, do ifmedia setup and ethernet/BPF attach. * * RETURNS: * Returns 0 on success or a negative error code. */ static int smsc_attach(device_t dev) { struct usb_attach_arg *uaa = device_get_ivars(dev); struct smsc_softc *sc = device_get_softc(dev); struct usb_ether *ue = &sc->sc_ue; uint8_t iface_index; int err; sc->sc_flags = USB_GET_DRIVER_INFO(uaa); device_set_usb_desc(dev); mtx_init(&sc->sc_mtx, device_get_nameunit(dev), NULL, MTX_DEF); /* Setup the endpoints for the SMSC LAN95xx device(s) */ iface_index = SMSC_IFACE_IDX; err = usbd_transfer_setup(uaa->device, &iface_index, sc->sc_xfer, smsc_config, SMSC_N_TRANSFER, sc, &sc->sc_mtx); if (err) { device_printf(dev, "error: allocating USB transfers failed\n"); goto detach; } ue->ue_sc = sc; ue->ue_dev = dev; ue->ue_udev = uaa->device; ue->ue_mtx = &sc->sc_mtx; ue->ue_methods = &smsc_ue_methods; err = uether_ifattach(ue); if (err) { device_printf(dev, "error: could not attach interface\n"); goto detach; } return (0); /* success */ detach: smsc_detach(dev); return (ENXIO); /* failure */ } /** * smsc_detach - Detach the interface. * @dev: smsc device handle * * RETURNS: * Returns 0. */ static int smsc_detach(device_t dev) { struct smsc_softc *sc = device_get_softc(dev); struct usb_ether *ue = &sc->sc_ue; usbd_transfer_unsetup(sc->sc_xfer, SMSC_N_TRANSFER); uether_ifdetach(ue); mtx_destroy(&sc->sc_mtx); return (0); } static device_method_t smsc_methods[] = { /* Device interface */ DEVMETHOD(device_probe, smsc_probe), DEVMETHOD(device_attach, smsc_attach), DEVMETHOD(device_detach, smsc_detach), /* bus interface */ DEVMETHOD(bus_print_child, bus_generic_print_child), DEVMETHOD(bus_driver_added, bus_generic_driver_added), /* MII interface */ DEVMETHOD(miibus_readreg, smsc_miibus_readreg), DEVMETHOD(miibus_writereg, smsc_miibus_writereg), DEVMETHOD(miibus_statchg, smsc_miibus_statchg), DEVMETHOD_END }; static driver_t smsc_driver = { .name = "smsc", .methods = smsc_methods, .size = sizeof(struct smsc_softc), }; static devclass_t smsc_devclass; DRIVER_MODULE(smsc, uhub, smsc_driver, smsc_devclass, NULL, 0); DRIVER_MODULE(miibus, smsc, miibus_driver, miibus_devclass, 0, 0); MODULE_DEPEND(smsc, uether, 1, 1, 1); MODULE_DEPEND(smsc, usb, 1, 1, 1); MODULE_DEPEND(smsc, ether, 1, 1, 1); MODULE_DEPEND(smsc, miibus, 1, 1, 1); MODULE_VERSION(smsc, 1); USB_PNP_HOST_INFO(smsc_devs); Index: head/sys/dev/usb/net/if_udav.c =================================================================== --- head/sys/dev/usb/net/if_udav.c (revision 351249) +++ head/sys/dev/usb/net/if_udav.c (revision 351250) @@ -1,883 +1,889 @@ /* $NetBSD: if_udav.c,v 1.2 2003/09/04 15:17:38 tsutsui Exp $ */ /* $nabe: if_udav.c,v 1.3 2003/08/21 16:57:19 nabe Exp $ */ /* $FreeBSD$ */ /*- * SPDX-License-Identifier: BSD-3-Clause * * Copyright (c) 2003 * Shingo WATANABE . All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * 3. Neither the name of the author nor the names of any co-contributors * may be used to endorse or promote products derived from this software * without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. * */ /* * DM9601(DAVICOM USB to Ethernet MAC Controller with Integrated 10/100 PHY) * The spec can be found at the following url. * http://ptm2.cc.utu.fi/ftp/network/cards/DM9601/From_NET/DM9601-DS-P01-930914.pdf */ /* * TODO: * Interrupt Endpoint support * External PHYs */ #include __FBSDID("$FreeBSD$"); #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include +#include +#include +#include + #include #include #include #include "usbdevs.h" + +#include "miibus_if.h" #define USB_DEBUG_VAR udav_debug #include #include #include #include /* prototypes */ static device_probe_t udav_probe; static device_attach_t udav_attach; static device_detach_t udav_detach; static usb_callback_t udav_bulk_write_callback; static usb_callback_t udav_bulk_read_callback; static usb_callback_t udav_intr_callback; static uether_fn_t udav_attach_post; static uether_fn_t udav_init; static uether_fn_t udav_stop; static uether_fn_t udav_start; static uether_fn_t udav_tick; static uether_fn_t udav_setmulti; static uether_fn_t udav_setpromisc; static int udav_csr_read(struct udav_softc *, uint16_t, void *, int); static int udav_csr_write(struct udav_softc *, uint16_t, void *, int); static uint8_t udav_csr_read1(struct udav_softc *, uint16_t); static int udav_csr_write1(struct udav_softc *, uint16_t, uint8_t); static void udav_reset(struct udav_softc *); static int udav_ifmedia_upd(struct ifnet *); static void udav_ifmedia_status(struct ifnet *, struct ifmediareq *); static miibus_readreg_t udav_miibus_readreg; static miibus_writereg_t udav_miibus_writereg; static miibus_statchg_t udav_miibus_statchg; static const struct usb_config udav_config[UDAV_N_TRANSFER] = { [UDAV_BULK_DT_WR] = { .type = UE_BULK, .endpoint = UE_ADDR_ANY, .direction = UE_DIR_OUT, .bufsize = (MCLBYTES + 2), .flags = {.pipe_bof = 1,.force_short_xfer = 1,}, .callback = udav_bulk_write_callback, .timeout = 10000, /* 10 seconds */ }, [UDAV_BULK_DT_RD] = { .type = UE_BULK, .endpoint = UE_ADDR_ANY, .direction = UE_DIR_IN, .bufsize = (MCLBYTES + 3), .flags = {.pipe_bof = 1,.short_xfer_ok = 1,}, .callback = udav_bulk_read_callback, .timeout = 0, /* no timeout */ }, [UDAV_INTR_DT_RD] = { .type = UE_INTERRUPT, .endpoint = UE_ADDR_ANY, .direction = UE_DIR_IN, .flags = {.pipe_bof = 1,.short_xfer_ok = 1,}, .bufsize = 0, /* use wMaxPacketSize */ .callback = udav_intr_callback, }, }; static device_method_t udav_methods[] = { /* Device interface */ DEVMETHOD(device_probe, udav_probe), DEVMETHOD(device_attach, udav_attach), DEVMETHOD(device_detach, udav_detach), /* MII interface */ DEVMETHOD(miibus_readreg, udav_miibus_readreg), DEVMETHOD(miibus_writereg, udav_miibus_writereg), DEVMETHOD(miibus_statchg, udav_miibus_statchg), DEVMETHOD_END }; static driver_t udav_driver = { .name = "udav", .methods = udav_methods, .size = sizeof(struct udav_softc), }; static devclass_t udav_devclass; static const STRUCT_USB_HOST_ID udav_devs[] = { /* ShanTou DM9601 USB NIC */ {USB_VPI(USB_VENDOR_SHANTOU, USB_PRODUCT_SHANTOU_DM9601, 0)}, /* ShanTou ST268 USB NIC */ {USB_VPI(USB_VENDOR_SHANTOU, USB_PRODUCT_SHANTOU_ST268, 0)}, /* Corega USB-TXC */ {USB_VPI(USB_VENDOR_COREGA, USB_PRODUCT_COREGA_FETHER_USB_TXC, 0)}, /* ShanTou AMD8515 USB NIC */ {USB_VPI(USB_VENDOR_SHANTOU, USB_PRODUCT_SHANTOU_ADM8515, 0)}, /* Kontron AG USB Ethernet */ {USB_VPI(USB_VENDOR_KONTRON, USB_PRODUCT_KONTRON_DM9601, 0)}, {USB_VPI(USB_VENDOR_KONTRON, USB_PRODUCT_KONTRON_JP1082, UDAV_FLAG_NO_PHY)}, }; DRIVER_MODULE(udav, uhub, udav_driver, udav_devclass, NULL, 0); DRIVER_MODULE(miibus, udav, miibus_driver, miibus_devclass, 0, 0); MODULE_DEPEND(udav, uether, 1, 1, 1); MODULE_DEPEND(udav, usb, 1, 1, 1); MODULE_DEPEND(udav, ether, 1, 1, 1); MODULE_DEPEND(udav, miibus, 1, 1, 1); MODULE_VERSION(udav, 1); USB_PNP_HOST_INFO(udav_devs); static const struct usb_ether_methods udav_ue_methods = { .ue_attach_post = udav_attach_post, .ue_start = udav_start, .ue_init = udav_init, .ue_stop = udav_stop, .ue_tick = udav_tick, .ue_setmulti = udav_setmulti, .ue_setpromisc = udav_setpromisc, .ue_mii_upd = udav_ifmedia_upd, .ue_mii_sts = udav_ifmedia_status, }; static const struct usb_ether_methods udav_ue_methods_nophy = { .ue_attach_post = udav_attach_post, .ue_start = udav_start, .ue_init = udav_init, .ue_stop = udav_stop, .ue_setmulti = udav_setmulti, .ue_setpromisc = udav_setpromisc, }; #ifdef USB_DEBUG static int udav_debug = 0; static SYSCTL_NODE(_hw_usb, OID_AUTO, udav, CTLFLAG_RW, 0, "USB udav"); SYSCTL_INT(_hw_usb_udav, OID_AUTO, debug, CTLFLAG_RWTUN, &udav_debug, 0, "Debug level"); #endif #define UDAV_SETBIT(sc, reg, x) \ udav_csr_write1(sc, reg, udav_csr_read1(sc, reg) | (x)) #define UDAV_CLRBIT(sc, reg, x) \ udav_csr_write1(sc, reg, udav_csr_read1(sc, reg) & ~(x)) static void udav_attach_post(struct usb_ether *ue) { struct udav_softc *sc = uether_getsc(ue); /* reset the adapter */ udav_reset(sc); /* Get Ethernet Address */ udav_csr_read(sc, UDAV_PAR, ue->ue_eaddr, ETHER_ADDR_LEN); } static int udav_probe(device_t dev) { struct usb_attach_arg *uaa = device_get_ivars(dev); if (uaa->usb_mode != USB_MODE_HOST) return (ENXIO); if (uaa->info.bConfigIndex != UDAV_CONFIG_INDEX) return (ENXIO); if (uaa->info.bIfaceIndex != UDAV_IFACE_INDEX) return (ENXIO); return (usbd_lookup_id_by_uaa(udav_devs, sizeof(udav_devs), uaa)); } static int udav_attach(device_t dev) { struct usb_attach_arg *uaa = device_get_ivars(dev); struct udav_softc *sc = device_get_softc(dev); struct usb_ether *ue = &sc->sc_ue; uint8_t iface_index; int error; sc->sc_flags = USB_GET_DRIVER_INFO(uaa); device_set_usb_desc(dev); mtx_init(&sc->sc_mtx, device_get_nameunit(dev), NULL, MTX_DEF); iface_index = UDAV_IFACE_INDEX; error = usbd_transfer_setup(uaa->device, &iface_index, sc->sc_xfer, udav_config, UDAV_N_TRANSFER, sc, &sc->sc_mtx); if (error) { device_printf(dev, "allocating USB transfers failed\n"); goto detach; } /* * The JP1082 has an unusable PHY and provides no link information. */ if (sc->sc_flags & UDAV_FLAG_NO_PHY) { ue->ue_methods = &udav_ue_methods_nophy; sc->sc_flags |= UDAV_FLAG_LINK; } else { ue->ue_methods = &udav_ue_methods; } ue->ue_sc = sc; ue->ue_dev = dev; ue->ue_udev = uaa->device; ue->ue_mtx = &sc->sc_mtx; error = uether_ifattach(ue); if (error) { device_printf(dev, "could not attach interface\n"); goto detach; } return (0); /* success */ detach: udav_detach(dev); return (ENXIO); /* failure */ } static int udav_detach(device_t dev) { struct udav_softc *sc = device_get_softc(dev); struct usb_ether *ue = &sc->sc_ue; usbd_transfer_unsetup(sc->sc_xfer, UDAV_N_TRANSFER); uether_ifdetach(ue); mtx_destroy(&sc->sc_mtx); return (0); } #if 0 static int udav_mem_read(struct udav_softc *sc, uint16_t offset, void *buf, int len) { struct usb_device_request req; len &= 0xff; req.bmRequestType = UT_READ_VENDOR_DEVICE; req.bRequest = UDAV_REQ_MEM_READ; USETW(req.wValue, 0x0000); USETW(req.wIndex, offset); USETW(req.wLength, len); return (uether_do_request(&sc->sc_ue, &req, buf, 1000)); } static int udav_mem_write(struct udav_softc *sc, uint16_t offset, void *buf, int len) { struct usb_device_request req; len &= 0xff; req.bmRequestType = UT_WRITE_VENDOR_DEVICE; req.bRequest = UDAV_REQ_MEM_WRITE; USETW(req.wValue, 0x0000); USETW(req.wIndex, offset); USETW(req.wLength, len); return (uether_do_request(&sc->sc_ue, &req, buf, 1000)); } static int udav_mem_write1(struct udav_softc *sc, uint16_t offset, uint8_t ch) { struct usb_device_request req; req.bmRequestType = UT_WRITE_VENDOR_DEVICE; req.bRequest = UDAV_REQ_MEM_WRITE1; USETW(req.wValue, ch); USETW(req.wIndex, offset); USETW(req.wLength, 0x0000); return (uether_do_request(&sc->sc_ue, &req, NULL, 1000)); } #endif static int udav_csr_read(struct udav_softc *sc, uint16_t offset, void *buf, int len) { struct usb_device_request req; len &= 0xff; req.bmRequestType = UT_READ_VENDOR_DEVICE; req.bRequest = UDAV_REQ_REG_READ; USETW(req.wValue, 0x0000); USETW(req.wIndex, offset); USETW(req.wLength, len); return (uether_do_request(&sc->sc_ue, &req, buf, 1000)); } static int udav_csr_write(struct udav_softc *sc, uint16_t offset, void *buf, int len) { struct usb_device_request req; offset &= 0xff; len &= 0xff; req.bmRequestType = UT_WRITE_VENDOR_DEVICE; req.bRequest = UDAV_REQ_REG_WRITE; USETW(req.wValue, 0x0000); USETW(req.wIndex, offset); USETW(req.wLength, len); return (uether_do_request(&sc->sc_ue, &req, buf, 1000)); } static uint8_t udav_csr_read1(struct udav_softc *sc, uint16_t offset) { uint8_t val; udav_csr_read(sc, offset, &val, 1); return (val); } static int udav_csr_write1(struct udav_softc *sc, uint16_t offset, uint8_t ch) { struct usb_device_request req; offset &= 0xff; req.bmRequestType = UT_WRITE_VENDOR_DEVICE; req.bRequest = UDAV_REQ_REG_WRITE1; USETW(req.wValue, ch); USETW(req.wIndex, offset); USETW(req.wLength, 0x0000); return (uether_do_request(&sc->sc_ue, &req, NULL, 1000)); } static void udav_init(struct usb_ether *ue) { struct udav_softc *sc = ue->ue_sc; struct ifnet *ifp = uether_getifp(&sc->sc_ue); UDAV_LOCK_ASSERT(sc, MA_OWNED); /* * Cancel pending I/O */ udav_stop(ue); /* set MAC address */ udav_csr_write(sc, UDAV_PAR, IF_LLADDR(ifp), ETHER_ADDR_LEN); /* initialize network control register */ /* disable loopback */ UDAV_CLRBIT(sc, UDAV_NCR, UDAV_NCR_LBK0 | UDAV_NCR_LBK1); /* Initialize RX control register */ UDAV_SETBIT(sc, UDAV_RCR, UDAV_RCR_DIS_LONG | UDAV_RCR_DIS_CRC); /* load multicast filter and update promiscious mode bit */ udav_setpromisc(ue); /* enable RX */ UDAV_SETBIT(sc, UDAV_RCR, UDAV_RCR_RXEN); /* clear POWER_DOWN state of internal PHY */ UDAV_SETBIT(sc, UDAV_GPCR, UDAV_GPCR_GEP_CNTL0); UDAV_CLRBIT(sc, UDAV_GPR, UDAV_GPR_GEPIO0); usbd_xfer_set_stall(sc->sc_xfer[UDAV_BULK_DT_WR]); ifp->if_drv_flags |= IFF_DRV_RUNNING; udav_start(ue); } static void udav_reset(struct udav_softc *sc) { int i; /* Select PHY */ #if 1 /* * XXX: force select internal phy. * external phy routines are not tested. */ UDAV_CLRBIT(sc, UDAV_NCR, UDAV_NCR_EXT_PHY); #else if (sc->sc_flags & UDAV_EXT_PHY) UDAV_SETBIT(sc, UDAV_NCR, UDAV_NCR_EXT_PHY); else UDAV_CLRBIT(sc, UDAV_NCR, UDAV_NCR_EXT_PHY); #endif UDAV_SETBIT(sc, UDAV_NCR, UDAV_NCR_RST); for (i = 0; i < UDAV_TX_TIMEOUT; i++) { if (!(udav_csr_read1(sc, UDAV_NCR) & UDAV_NCR_RST)) break; if (uether_pause(&sc->sc_ue, hz / 100)) break; } uether_pause(&sc->sc_ue, hz / 100); } #define UDAV_BITS 6 static void udav_setmulti(struct usb_ether *ue) { struct udav_softc *sc = ue->ue_sc; struct ifnet *ifp = uether_getifp(&sc->sc_ue); struct ifmultiaddr *ifma; uint8_t hashtbl[8] = { 0, 0, 0, 0, 0, 0, 0, 0 }; int h = 0; UDAV_LOCK_ASSERT(sc, MA_OWNED); if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { UDAV_SETBIT(sc, UDAV_RCR, UDAV_RCR_ALL|UDAV_RCR_PRMSC); return; } /* first, zot all the existing hash bits */ memset(hashtbl, 0x00, sizeof(hashtbl)); hashtbl[7] |= 0x80; /* broadcast address */ udav_csr_write(sc, UDAV_MAR, hashtbl, sizeof(hashtbl)); /* now program new ones */ if_maddr_rlock(ifp); CK_STAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { if (ifma->ifma_addr->sa_family != AF_LINK) continue; h = ether_crc32_be(LLADDR((struct sockaddr_dl *) ifma->ifma_addr), ETHER_ADDR_LEN) >> 26; hashtbl[h / 8] |= 1 << (h % 8); } if_maddr_runlock(ifp); /* disable all multicast */ UDAV_CLRBIT(sc, UDAV_RCR, UDAV_RCR_ALL); /* write hash value to the register */ udav_csr_write(sc, UDAV_MAR, hashtbl, sizeof(hashtbl)); } static void udav_setpromisc(struct usb_ether *ue) { struct udav_softc *sc = ue->ue_sc; struct ifnet *ifp = uether_getifp(&sc->sc_ue); uint8_t rxmode; rxmode = udav_csr_read1(sc, UDAV_RCR); rxmode &= ~(UDAV_RCR_ALL | UDAV_RCR_PRMSC); if (ifp->if_flags & IFF_PROMISC) rxmode |= UDAV_RCR_ALL | UDAV_RCR_PRMSC; else if (ifp->if_flags & IFF_ALLMULTI) rxmode |= UDAV_RCR_ALL; /* write new mode bits */ udav_csr_write1(sc, UDAV_RCR, rxmode); } static void udav_start(struct usb_ether *ue) { struct udav_softc *sc = ue->ue_sc; /* * start the USB transfers, if not already started: */ usbd_transfer_start(sc->sc_xfer[UDAV_INTR_DT_RD]); usbd_transfer_start(sc->sc_xfer[UDAV_BULK_DT_RD]); usbd_transfer_start(sc->sc_xfer[UDAV_BULK_DT_WR]); } static void udav_bulk_write_callback(struct usb_xfer *xfer, usb_error_t error) { struct udav_softc *sc = usbd_xfer_softc(xfer); struct ifnet *ifp = uether_getifp(&sc->sc_ue); struct usb_page_cache *pc; struct mbuf *m; int extra_len; int temp_len; uint8_t buf[2]; switch (USB_GET_STATE(xfer)) { case USB_ST_TRANSFERRED: DPRINTFN(11, "transfer complete\n"); if_inc_counter(ifp, IFCOUNTER_OPACKETS, 1); /* FALLTHROUGH */ case USB_ST_SETUP: tr_setup: if ((sc->sc_flags & UDAV_FLAG_LINK) == 0) { /* * don't send anything if there is no link ! */ return; } IFQ_DRV_DEQUEUE(&ifp->if_snd, m); if (m == NULL) return; if (m->m_pkthdr.len > MCLBYTES) m->m_pkthdr.len = MCLBYTES; if (m->m_pkthdr.len < UDAV_MIN_FRAME_LEN) { extra_len = UDAV_MIN_FRAME_LEN - m->m_pkthdr.len; } else { extra_len = 0; } temp_len = (m->m_pkthdr.len + extra_len); /* * the frame length is specified in the first 2 bytes of the * buffer */ buf[0] = (uint8_t)(temp_len); buf[1] = (uint8_t)(temp_len >> 8); temp_len += 2; pc = usbd_xfer_get_frame(xfer, 0); usbd_copy_in(pc, 0, buf, 2); usbd_m_copy_in(pc, 2, m, 0, m->m_pkthdr.len); if (extra_len) usbd_frame_zero(pc, temp_len - extra_len, extra_len); /* * if there's a BPF listener, bounce a copy * of this frame to him: */ BPF_MTAP(ifp, m); m_freem(m); usbd_xfer_set_frame_len(xfer, 0, temp_len); usbd_transfer_submit(xfer); return; default: /* Error */ DPRINTFN(11, "transfer error, %s\n", usbd_errstr(error)); if_inc_counter(ifp, IFCOUNTER_OERRORS, 1); if (error != USB_ERR_CANCELLED) { /* try to clear stall first */ usbd_xfer_set_stall(xfer); goto tr_setup; } return; } } static void udav_bulk_read_callback(struct usb_xfer *xfer, usb_error_t error) { struct udav_softc *sc = usbd_xfer_softc(xfer); struct usb_ether *ue = &sc->sc_ue; struct ifnet *ifp = uether_getifp(ue); struct usb_page_cache *pc; struct udav_rxpkt stat; int len; int actlen; usbd_xfer_status(xfer, &actlen, NULL, NULL, NULL); switch (USB_GET_STATE(xfer)) { case USB_ST_TRANSFERRED: if (actlen < (int)(sizeof(stat) + ETHER_CRC_LEN)) { if_inc_counter(ifp, IFCOUNTER_IERRORS, 1); goto tr_setup; } pc = usbd_xfer_get_frame(xfer, 0); usbd_copy_out(pc, 0, &stat, sizeof(stat)); actlen -= sizeof(stat); len = min(actlen, le16toh(stat.pktlen)); len -= ETHER_CRC_LEN; if (stat.rxstat & UDAV_RSR_LCS) { if_inc_counter(ifp, IFCOUNTER_COLLISIONS, 1); goto tr_setup; } if (stat.rxstat & UDAV_RSR_ERR) { if_inc_counter(ifp, IFCOUNTER_IERRORS, 1); goto tr_setup; } uether_rxbuf(ue, pc, sizeof(stat), len); /* FALLTHROUGH */ case USB_ST_SETUP: tr_setup: usbd_xfer_set_frame_len(xfer, 0, usbd_xfer_max_len(xfer)); usbd_transfer_submit(xfer); uether_rxflush(ue); return; default: /* Error */ DPRINTF("bulk read error, %s\n", usbd_errstr(error)); if (error != USB_ERR_CANCELLED) { /* try to clear stall first */ usbd_xfer_set_stall(xfer); goto tr_setup; } return; } } static void udav_intr_callback(struct usb_xfer *xfer, usb_error_t error) { switch (USB_GET_STATE(xfer)) { case USB_ST_TRANSFERRED: case USB_ST_SETUP: tr_setup: usbd_xfer_set_frame_len(xfer, 0, usbd_xfer_max_len(xfer)); usbd_transfer_submit(xfer); return; default: /* Error */ if (error != USB_ERR_CANCELLED) { /* try to clear stall first */ usbd_xfer_set_stall(xfer); goto tr_setup; } return; } } static void udav_stop(struct usb_ether *ue) { struct udav_softc *sc = ue->ue_sc; struct ifnet *ifp = uether_getifp(&sc->sc_ue); UDAV_LOCK_ASSERT(sc, MA_OWNED); ifp->if_drv_flags &= ~IFF_DRV_RUNNING; if (!(sc->sc_flags & UDAV_FLAG_NO_PHY)) sc->sc_flags &= ~UDAV_FLAG_LINK; /* * stop all the transfers, if not already stopped: */ usbd_transfer_stop(sc->sc_xfer[UDAV_BULK_DT_WR]); usbd_transfer_stop(sc->sc_xfer[UDAV_BULK_DT_RD]); usbd_transfer_stop(sc->sc_xfer[UDAV_INTR_DT_RD]); udav_reset(sc); } static int udav_ifmedia_upd(struct ifnet *ifp) { struct udav_softc *sc = ifp->if_softc; struct mii_data *mii = GET_MII(sc); struct mii_softc *miisc; int error; UDAV_LOCK_ASSERT(sc, MA_OWNED); sc->sc_flags &= ~UDAV_FLAG_LINK; LIST_FOREACH(miisc, &mii->mii_phys, mii_list) PHY_RESET(miisc); error = mii_mediachg(mii); return (error); } static void udav_ifmedia_status(struct ifnet *ifp, struct ifmediareq *ifmr) { struct udav_softc *sc = ifp->if_softc; struct mii_data *mii = GET_MII(sc); UDAV_LOCK(sc); mii_pollstat(mii); ifmr->ifm_active = mii->mii_media_active; ifmr->ifm_status = mii->mii_media_status; UDAV_UNLOCK(sc); } static void udav_tick(struct usb_ether *ue) { struct udav_softc *sc = ue->ue_sc; struct mii_data *mii = GET_MII(sc); UDAV_LOCK_ASSERT(sc, MA_OWNED); mii_tick(mii); if ((sc->sc_flags & UDAV_FLAG_LINK) == 0 && mii->mii_media_status & IFM_ACTIVE && IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) { sc->sc_flags |= UDAV_FLAG_LINK; udav_start(ue); } } static int udav_miibus_readreg(device_t dev, int phy, int reg) { struct udav_softc *sc = device_get_softc(dev); uint16_t data16; uint8_t val[2]; int locked; /* XXX: one PHY only for the internal PHY */ if (phy != 0) return (0); locked = mtx_owned(&sc->sc_mtx); if (!locked) UDAV_LOCK(sc); /* select internal PHY and set PHY register address */ udav_csr_write1(sc, UDAV_EPAR, UDAV_EPAR_PHY_ADR0 | (reg & UDAV_EPAR_EROA_MASK)); /* select PHY operation and start read command */ udav_csr_write1(sc, UDAV_EPCR, UDAV_EPCR_EPOS | UDAV_EPCR_ERPRR); /* XXX: should we wait? */ /* end read command */ UDAV_CLRBIT(sc, UDAV_EPCR, UDAV_EPCR_ERPRR); /* retrieve the result from data registers */ udav_csr_read(sc, UDAV_EPDRL, val, 2); data16 = (val[0] | (val[1] << 8)); DPRINTFN(11, "phy=%d reg=0x%04x => 0x%04x\n", phy, reg, data16); if (!locked) UDAV_UNLOCK(sc); return (data16); } static int udav_miibus_writereg(device_t dev, int phy, int reg, int data) { struct udav_softc *sc = device_get_softc(dev); uint8_t val[2]; int locked; /* XXX: one PHY only for the internal PHY */ if (phy != 0) return (0); locked = mtx_owned(&sc->sc_mtx); if (!locked) UDAV_LOCK(sc); /* select internal PHY and set PHY register address */ udav_csr_write1(sc, UDAV_EPAR, UDAV_EPAR_PHY_ADR0 | (reg & UDAV_EPAR_EROA_MASK)); /* put the value to the data registers */ val[0] = (data & 0xff); val[1] = (data >> 8) & 0xff; udav_csr_write(sc, UDAV_EPDRL, val, 2); /* select PHY operation and start write command */ udav_csr_write1(sc, UDAV_EPCR, UDAV_EPCR_EPOS | UDAV_EPCR_ERPRW); /* XXX: should we wait? */ /* end write command */ UDAV_CLRBIT(sc, UDAV_EPCR, UDAV_EPCR_ERPRW); if (!locked) UDAV_UNLOCK(sc); return (0); } static void udav_miibus_statchg(device_t dev) { /* nothing to do */ } Index: head/sys/dev/usb/net/if_ure.c =================================================================== --- head/sys/dev/usb/net/if_ure.c (revision 351249) +++ head/sys/dev/usb/net/if_ure.c (revision 351250) @@ -1,1277 +1,1283 @@ /*- * Copyright (c) 2015-2016 Kevin Lo * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. */ #include __FBSDID("$FreeBSD$"); #include #include #include #include #include #include #include #include #include #include #include #include #include +#include +#include +#include + #include #include #include #include "usbdevs.h" #define USB_DEBUG_VAR ure_debug #include #include #include #include + +#include "miibus_if.h" #ifdef USB_DEBUG static int ure_debug = 0; static SYSCTL_NODE(_hw_usb, OID_AUTO, ure, CTLFLAG_RW, 0, "USB ure"); SYSCTL_INT(_hw_usb_ure, OID_AUTO, debug, CTLFLAG_RWTUN, &ure_debug, 0, "Debug level"); #endif #define ETHER_IS_ZERO(addr) \ (!(addr[0] | addr[1] | addr[2] | addr[3] | addr[4] | addr[5])) /* * Various supported device vendors/products. */ static const STRUCT_USB_HOST_ID ure_devs[] = { #define URE_DEV(v,p,i) { USB_VPI(USB_VENDOR_##v, USB_PRODUCT_##v##_##p, i) } URE_DEV(LENOVO, RTL8153, 0), URE_DEV(LENOVO, TBT3LAN, 0), URE_DEV(LENOVO, ONELINK, 0), URE_DEV(LENOVO, USBCLAN, 0), URE_DEV(NVIDIA, RTL8153, 0), URE_DEV(REALTEK, RTL8152, URE_FLAG_8152), URE_DEV(REALTEK, RTL8153, 0), URE_DEV(TPLINK, RTL8153, 0), #undef URE_DEV }; static device_probe_t ure_probe; static device_attach_t ure_attach; static device_detach_t ure_detach; static usb_callback_t ure_bulk_read_callback; static usb_callback_t ure_bulk_write_callback; static miibus_readreg_t ure_miibus_readreg; static miibus_writereg_t ure_miibus_writereg; static miibus_statchg_t ure_miibus_statchg; static uether_fn_t ure_attach_post; static uether_fn_t ure_init; static uether_fn_t ure_stop; static uether_fn_t ure_start; static uether_fn_t ure_tick; static uether_fn_t ure_rxfilter; static int ure_ctl(struct ure_softc *, uint8_t, uint16_t, uint16_t, void *, int); static int ure_read_mem(struct ure_softc *, uint16_t, uint16_t, void *, int); static int ure_write_mem(struct ure_softc *, uint16_t, uint16_t, void *, int); static uint8_t ure_read_1(struct ure_softc *, uint16_t, uint16_t); static uint16_t ure_read_2(struct ure_softc *, uint16_t, uint16_t); static uint32_t ure_read_4(struct ure_softc *, uint16_t, uint16_t); static int ure_write_1(struct ure_softc *, uint16_t, uint16_t, uint32_t); static int ure_write_2(struct ure_softc *, uint16_t, uint16_t, uint32_t); static int ure_write_4(struct ure_softc *, uint16_t, uint16_t, uint32_t); static uint16_t ure_ocp_reg_read(struct ure_softc *, uint16_t); static void ure_ocp_reg_write(struct ure_softc *, uint16_t, uint16_t); static void ure_read_chipver(struct ure_softc *); static int ure_attach_post_sub(struct usb_ether *); static void ure_reset(struct ure_softc *); static int ure_ifmedia_upd(struct ifnet *); static void ure_ifmedia_sts(struct ifnet *, struct ifmediareq *); static int ure_ioctl(struct ifnet *, u_long, caddr_t); static void ure_rtl8152_init(struct ure_softc *); static void ure_rtl8153_init(struct ure_softc *); static void ure_disable_teredo(struct ure_softc *); static void ure_init_fifo(struct ure_softc *); static const struct usb_config ure_config[URE_N_TRANSFER] = { [URE_BULK_DT_WR] = { .type = UE_BULK, .endpoint = UE_ADDR_ANY, .direction = UE_DIR_OUT, .bufsize = MCLBYTES, .flags = {.pipe_bof = 1,.force_short_xfer = 1,}, .callback = ure_bulk_write_callback, .timeout = 10000, /* 10 seconds */ }, [URE_BULK_DT_RD] = { .type = UE_BULK, .endpoint = UE_ADDR_ANY, .direction = UE_DIR_IN, .bufsize = 16384, .flags = {.pipe_bof = 1,.short_xfer_ok = 1,}, .callback = ure_bulk_read_callback, .timeout = 0, /* no timeout */ }, }; static device_method_t ure_methods[] = { /* Device interface. */ DEVMETHOD(device_probe, ure_probe), DEVMETHOD(device_attach, ure_attach), DEVMETHOD(device_detach, ure_detach), /* MII interface. */ DEVMETHOD(miibus_readreg, ure_miibus_readreg), DEVMETHOD(miibus_writereg, ure_miibus_writereg), DEVMETHOD(miibus_statchg, ure_miibus_statchg), DEVMETHOD_END }; static driver_t ure_driver = { .name = "ure", .methods = ure_methods, .size = sizeof(struct ure_softc), }; static devclass_t ure_devclass; DRIVER_MODULE(ure, uhub, ure_driver, ure_devclass, NULL, NULL); DRIVER_MODULE(miibus, ure, miibus_driver, miibus_devclass, NULL, NULL); MODULE_DEPEND(ure, uether, 1, 1, 1); MODULE_DEPEND(ure, usb, 1, 1, 1); MODULE_DEPEND(ure, ether, 1, 1, 1); MODULE_DEPEND(ure, miibus, 1, 1, 1); MODULE_VERSION(ure, 1); USB_PNP_HOST_INFO(ure_devs); static const struct usb_ether_methods ure_ue_methods = { .ue_attach_post = ure_attach_post, .ue_attach_post_sub = ure_attach_post_sub, .ue_start = ure_start, .ue_init = ure_init, .ue_stop = ure_stop, .ue_tick = ure_tick, .ue_setmulti = ure_rxfilter, .ue_setpromisc = ure_rxfilter, .ue_mii_upd = ure_ifmedia_upd, .ue_mii_sts = ure_ifmedia_sts, }; static int ure_ctl(struct ure_softc *sc, uint8_t rw, uint16_t val, uint16_t index, void *buf, int len) { struct usb_device_request req; URE_LOCK_ASSERT(sc, MA_OWNED); if (rw == URE_CTL_WRITE) req.bmRequestType = UT_WRITE_VENDOR_DEVICE; else req.bmRequestType = UT_READ_VENDOR_DEVICE; req.bRequest = UR_SET_ADDRESS; USETW(req.wValue, val); USETW(req.wIndex, index); USETW(req.wLength, len); return (uether_do_request(&sc->sc_ue, &req, buf, 1000)); } static int ure_read_mem(struct ure_softc *sc, uint16_t addr, uint16_t index, void *buf, int len) { return (ure_ctl(sc, URE_CTL_READ, addr, index, buf, len)); } static int ure_write_mem(struct ure_softc *sc, uint16_t addr, uint16_t index, void *buf, int len) { return (ure_ctl(sc, URE_CTL_WRITE, addr, index, buf, len)); } static uint8_t ure_read_1(struct ure_softc *sc, uint16_t reg, uint16_t index) { uint32_t val; uint8_t temp[4]; uint8_t shift; shift = (reg & 3) << 3; reg &= ~3; ure_read_mem(sc, reg, index, &temp, 4); val = UGETDW(temp); val >>= shift; return (val & 0xff); } static uint16_t ure_read_2(struct ure_softc *sc, uint16_t reg, uint16_t index) { uint32_t val; uint8_t temp[4]; uint8_t shift; shift = (reg & 2) << 3; reg &= ~3; ure_read_mem(sc, reg, index, &temp, 4); val = UGETDW(temp); val >>= shift; return (val & 0xffff); } static uint32_t ure_read_4(struct ure_softc *sc, uint16_t reg, uint16_t index) { uint8_t temp[4]; ure_read_mem(sc, reg, index, &temp, 4); return (UGETDW(temp)); } static int ure_write_1(struct ure_softc *sc, uint16_t reg, uint16_t index, uint32_t val) { uint16_t byen; uint8_t temp[4]; uint8_t shift; byen = URE_BYTE_EN_BYTE; shift = reg & 3; val &= 0xff; if (reg & 3) { byen <<= shift; val <<= (shift << 3); reg &= ~3; } USETDW(temp, val); return (ure_write_mem(sc, reg, index | byen, &temp, 4)); } static int ure_write_2(struct ure_softc *sc, uint16_t reg, uint16_t index, uint32_t val) { uint16_t byen; uint8_t temp[4]; uint8_t shift; byen = URE_BYTE_EN_WORD; shift = reg & 2; val &= 0xffff; if (reg & 2) { byen <<= shift; val <<= (shift << 3); reg &= ~3; } USETDW(temp, val); return (ure_write_mem(sc, reg, index | byen, &temp, 4)); } static int ure_write_4(struct ure_softc *sc, uint16_t reg, uint16_t index, uint32_t val) { uint8_t temp[4]; USETDW(temp, val); return (ure_write_mem(sc, reg, index | URE_BYTE_EN_DWORD, &temp, 4)); } static uint16_t ure_ocp_reg_read(struct ure_softc *sc, uint16_t addr) { uint16_t reg; ure_write_2(sc, URE_PLA_OCP_GPHY_BASE, URE_MCU_TYPE_PLA, addr & 0xf000); reg = (addr & 0x0fff) | 0xb000; return (ure_read_2(sc, reg, URE_MCU_TYPE_PLA)); } static void ure_ocp_reg_write(struct ure_softc *sc, uint16_t addr, uint16_t data) { uint16_t reg; ure_write_2(sc, URE_PLA_OCP_GPHY_BASE, URE_MCU_TYPE_PLA, addr & 0xf000); reg = (addr & 0x0fff) | 0xb000; ure_write_2(sc, reg, URE_MCU_TYPE_PLA, data); } static int ure_miibus_readreg(device_t dev, int phy, int reg) { struct ure_softc *sc; uint16_t val; int locked; sc = device_get_softc(dev); locked = mtx_owned(&sc->sc_mtx); if (!locked) URE_LOCK(sc); /* Let the rgephy driver read the URE_GMEDIASTAT register. */ if (reg == URE_GMEDIASTAT) { if (!locked) URE_UNLOCK(sc); return (ure_read_1(sc, URE_GMEDIASTAT, URE_MCU_TYPE_PLA)); } val = ure_ocp_reg_read(sc, URE_OCP_BASE_MII + reg * 2); if (!locked) URE_UNLOCK(sc); return (val); } static int ure_miibus_writereg(device_t dev, int phy, int reg, int val) { struct ure_softc *sc; int locked; sc = device_get_softc(dev); if (sc->sc_phyno != phy) return (0); locked = mtx_owned(&sc->sc_mtx); if (!locked) URE_LOCK(sc); ure_ocp_reg_write(sc, URE_OCP_BASE_MII + reg * 2, val); if (!locked) URE_UNLOCK(sc); return (0); } static void ure_miibus_statchg(device_t dev) { struct ure_softc *sc; struct mii_data *mii; struct ifnet *ifp; int locked; sc = device_get_softc(dev); mii = GET_MII(sc); locked = mtx_owned(&sc->sc_mtx); if (!locked) URE_LOCK(sc); ifp = uether_getifp(&sc->sc_ue); if (mii == NULL || ifp == NULL || (ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) goto done; sc->sc_flags &= ~URE_FLAG_LINK; if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) == (IFM_ACTIVE | IFM_AVALID)) { switch (IFM_SUBTYPE(mii->mii_media_active)) { case IFM_10_T: case IFM_100_TX: sc->sc_flags |= URE_FLAG_LINK; break; case IFM_1000_T: if ((sc->sc_flags & URE_FLAG_8152) != 0) break; sc->sc_flags |= URE_FLAG_LINK; break; default: break; } } /* Lost link, do nothing. */ if ((sc->sc_flags & URE_FLAG_LINK) == 0) goto done; done: if (!locked) URE_UNLOCK(sc); } /* * Probe for a RTL8152/RTL8153 chip. */ static int ure_probe(device_t dev) { struct usb_attach_arg *uaa; uaa = device_get_ivars(dev); if (uaa->usb_mode != USB_MODE_HOST) return (ENXIO); if (uaa->info.bConfigIndex != URE_CONFIG_IDX) return (ENXIO); if (uaa->info.bIfaceIndex != URE_IFACE_IDX) return (ENXIO); return (usbd_lookup_id_by_uaa(ure_devs, sizeof(ure_devs), uaa)); } /* * Attach the interface. Allocate softc structures, do ifmedia * setup and ethernet/BPF attach. */ static int ure_attach(device_t dev) { struct usb_attach_arg *uaa = device_get_ivars(dev); struct ure_softc *sc = device_get_softc(dev); struct usb_ether *ue = &sc->sc_ue; uint8_t iface_index; int error; sc->sc_flags = USB_GET_DRIVER_INFO(uaa); device_set_usb_desc(dev); mtx_init(&sc->sc_mtx, device_get_nameunit(dev), NULL, MTX_DEF); iface_index = URE_IFACE_IDX; error = usbd_transfer_setup(uaa->device, &iface_index, sc->sc_xfer, ure_config, URE_N_TRANSFER, sc, &sc->sc_mtx); if (error != 0) { device_printf(dev, "allocating USB transfers failed\n"); goto detach; } ue->ue_sc = sc; ue->ue_dev = dev; ue->ue_udev = uaa->device; ue->ue_mtx = &sc->sc_mtx; ue->ue_methods = &ure_ue_methods; error = uether_ifattach(ue); if (error != 0) { device_printf(dev, "could not attach interface\n"); goto detach; } return (0); /* success */ detach: ure_detach(dev); return (ENXIO); /* failure */ } static int ure_detach(device_t dev) { struct ure_softc *sc = device_get_softc(dev); struct usb_ether *ue = &sc->sc_ue; usbd_transfer_unsetup(sc->sc_xfer, URE_N_TRANSFER); uether_ifdetach(ue); mtx_destroy(&sc->sc_mtx); return (0); } static void ure_bulk_read_callback(struct usb_xfer *xfer, usb_error_t error) { struct ure_softc *sc = usbd_xfer_softc(xfer); struct usb_ether *ue = &sc->sc_ue; struct ifnet *ifp = uether_getifp(ue); struct usb_page_cache *pc; struct ure_rxpkt pkt; int actlen, len; usbd_xfer_status(xfer, &actlen, NULL, NULL, NULL); switch (USB_GET_STATE(xfer)) { case USB_ST_TRANSFERRED: if (actlen < (int)(sizeof(pkt))) { if_inc_counter(ifp, IFCOUNTER_IERRORS, 1); goto tr_setup; } pc = usbd_xfer_get_frame(xfer, 0); usbd_copy_out(pc, 0, &pkt, sizeof(pkt)); len = le32toh(pkt.ure_pktlen) & URE_RXPKT_LEN_MASK; len -= ETHER_CRC_LEN; if (actlen < (int)(len + sizeof(pkt))) { if_inc_counter(ifp, IFCOUNTER_IERRORS, 1); goto tr_setup; } uether_rxbuf(ue, pc, sizeof(pkt), len); /* FALLTHROUGH */ case USB_ST_SETUP: tr_setup: usbd_xfer_set_frame_len(xfer, 0, usbd_xfer_max_len(xfer)); usbd_transfer_submit(xfer); uether_rxflush(ue); return; default: /* Error */ DPRINTF("bulk read error, %s\n", usbd_errstr(error)); if (error != USB_ERR_CANCELLED) { /* try to clear stall first */ usbd_xfer_set_stall(xfer); goto tr_setup; } return; } } static void ure_bulk_write_callback(struct usb_xfer *xfer, usb_error_t error) { struct ure_softc *sc = usbd_xfer_softc(xfer); struct ifnet *ifp = uether_getifp(&sc->sc_ue); struct usb_page_cache *pc; struct mbuf *m; struct ure_txpkt txpkt; int len, pos; switch (USB_GET_STATE(xfer)) { case USB_ST_TRANSFERRED: DPRINTFN(11, "transfer complete\n"); ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; /* FALLTHROUGH */ case USB_ST_SETUP: tr_setup: if ((sc->sc_flags & URE_FLAG_LINK) == 0 || (ifp->if_drv_flags & IFF_DRV_OACTIVE) != 0) { /* * don't send anything if there is no link ! */ return; } IFQ_DRV_DEQUEUE(&ifp->if_snd, m); if (m == NULL) break; pos = 0; len = m->m_pkthdr.len; pc = usbd_xfer_get_frame(xfer, 0); memset(&txpkt, 0, sizeof(txpkt)); txpkt.ure_pktlen = htole32((len & URE_TXPKT_LEN_MASK) | URE_TKPKT_TX_FS | URE_TKPKT_TX_LS); usbd_copy_in(pc, pos, &txpkt, sizeof(txpkt)); pos += sizeof(txpkt); usbd_m_copy_in(pc, pos, m, 0, m->m_pkthdr.len); pos += m->m_pkthdr.len; if_inc_counter(ifp, IFCOUNTER_OPACKETS, 1); /* * If there's a BPF listener, bounce a copy * of this frame to him. */ BPF_MTAP(ifp, m); m_freem(m); /* Set frame length. */ usbd_xfer_set_frame_len(xfer, 0, pos); usbd_transfer_submit(xfer); ifp->if_drv_flags |= IFF_DRV_OACTIVE; return; default: /* Error */ DPRINTFN(11, "transfer error, %s\n", usbd_errstr(error)); if_inc_counter(ifp, IFCOUNTER_OERRORS, 1); ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; if (error != USB_ERR_CANCELLED) { /* try to clear stall first */ usbd_xfer_set_stall(xfer); goto tr_setup; } return; } } static void ure_read_chipver(struct ure_softc *sc) { uint16_t ver; ver = ure_read_2(sc, URE_PLA_TCR1, URE_MCU_TYPE_PLA) & URE_VERSION_MASK; switch (ver) { case 0x4c00: sc->sc_chip |= URE_CHIP_VER_4C00; break; case 0x4c10: sc->sc_chip |= URE_CHIP_VER_4C10; break; case 0x5c00: sc->sc_chip |= URE_CHIP_VER_5C00; break; case 0x5c10: sc->sc_chip |= URE_CHIP_VER_5C10; break; case 0x5c20: sc->sc_chip |= URE_CHIP_VER_5C20; break; case 0x5c30: sc->sc_chip |= URE_CHIP_VER_5C30; break; default: device_printf(sc->sc_ue.ue_dev, "unknown version 0x%04x\n", ver); break; } } static void ure_attach_post(struct usb_ether *ue) { struct ure_softc *sc = uether_getsc(ue); sc->sc_phyno = 0; /* Determine the chip version. */ ure_read_chipver(sc); /* Initialize controller and get station address. */ if (sc->sc_flags & URE_FLAG_8152) ure_rtl8152_init(sc); else ure_rtl8153_init(sc); if ((sc->sc_chip & URE_CHIP_VER_4C00) || (sc->sc_chip & URE_CHIP_VER_4C10)) ure_read_mem(sc, URE_PLA_IDR, URE_MCU_TYPE_PLA, ue->ue_eaddr, 8); else ure_read_mem(sc, URE_PLA_BACKUP, URE_MCU_TYPE_PLA, ue->ue_eaddr, 8); if (ETHER_IS_ZERO(sc->sc_ue.ue_eaddr)) { device_printf(sc->sc_ue.ue_dev, "MAC assigned randomly\n"); arc4rand(sc->sc_ue.ue_eaddr, ETHER_ADDR_LEN, 0); sc->sc_ue.ue_eaddr[0] &= ~0x01; /* unicast */ sc->sc_ue.ue_eaddr[0] |= 0x02; /* locally administered */ } } static int ure_attach_post_sub(struct usb_ether *ue) { struct ure_softc *sc; struct ifnet *ifp; int error; sc = uether_getsc(ue); ifp = ue->ue_ifp; ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; ifp->if_start = uether_start; ifp->if_ioctl = ure_ioctl; ifp->if_init = uether_init; IFQ_SET_MAXLEN(&ifp->if_snd, ifqmaxlen); ifp->if_snd.ifq_drv_maxlen = ifqmaxlen; IFQ_SET_READY(&ifp->if_snd); mtx_lock(&Giant); error = mii_attach(ue->ue_dev, &ue->ue_miibus, ifp, uether_ifmedia_upd, ue->ue_methods->ue_mii_sts, BMSR_DEFCAPMASK, sc->sc_phyno, MII_OFFSET_ANY, 0); mtx_unlock(&Giant); return (error); } static void ure_init(struct usb_ether *ue) { struct ure_softc *sc = uether_getsc(ue); struct ifnet *ifp = uether_getifp(ue); URE_LOCK_ASSERT(sc, MA_OWNED); if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) return; /* Cancel pending I/O. */ ure_stop(ue); ure_reset(sc); /* Set MAC address. */ ure_write_1(sc, URE_PLA_CRWECR, URE_MCU_TYPE_PLA, URE_CRWECR_CONFIG); ure_write_mem(sc, URE_PLA_IDR, URE_MCU_TYPE_PLA | URE_BYTE_EN_SIX_BYTES, IF_LLADDR(ifp), 8); ure_write_1(sc, URE_PLA_CRWECR, URE_MCU_TYPE_PLA, URE_CRWECR_NORAML); /* Reset the packet filter. */ ure_write_2(sc, URE_PLA_FMC, URE_MCU_TYPE_PLA, ure_read_2(sc, URE_PLA_FMC, URE_MCU_TYPE_PLA) & ~URE_FMC_FCR_MCU_EN); ure_write_2(sc, URE_PLA_FMC, URE_MCU_TYPE_PLA, ure_read_2(sc, URE_PLA_FMC, URE_MCU_TYPE_PLA) | URE_FMC_FCR_MCU_EN); /* Enable transmit and receive. */ ure_write_1(sc, URE_PLA_CR, URE_MCU_TYPE_PLA, ure_read_1(sc, URE_PLA_CR, URE_MCU_TYPE_PLA) | URE_CR_RE | URE_CR_TE); ure_write_2(sc, URE_PLA_MISC_1, URE_MCU_TYPE_PLA, ure_read_2(sc, URE_PLA_MISC_1, URE_MCU_TYPE_PLA) & ~URE_RXDY_GATED_EN); /* Configure RX filters. */ ure_rxfilter(ue); usbd_xfer_set_stall(sc->sc_xfer[URE_BULK_DT_WR]); /* Indicate we are up and running. */ ifp->if_drv_flags |= IFF_DRV_RUNNING; /* Switch to selected media. */ ure_ifmedia_upd(ifp); } static void ure_tick(struct usb_ether *ue) { struct ure_softc *sc = uether_getsc(ue); struct mii_data *mii = GET_MII(sc); URE_LOCK_ASSERT(sc, MA_OWNED); mii_tick(mii); if ((sc->sc_flags & URE_FLAG_LINK) == 0 && mii->mii_media_status & IFM_ACTIVE && IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) { sc->sc_flags |= URE_FLAG_LINK; ure_start(ue); } } /* * Program the 64-bit multicast hash filter. */ static void ure_rxfilter(struct usb_ether *ue) { struct ure_softc *sc = uether_getsc(ue); struct ifnet *ifp = uether_getifp(ue); struct ifmultiaddr *ifma; uint32_t h, rxmode; uint32_t hashes[2] = { 0, 0 }; URE_LOCK_ASSERT(sc, MA_OWNED); rxmode = URE_RCR_APM; if (ifp->if_flags & IFF_BROADCAST) rxmode |= URE_RCR_AB; if (ifp->if_flags & (IFF_ALLMULTI | IFF_PROMISC)) { if (ifp->if_flags & IFF_PROMISC) rxmode |= URE_RCR_AAP; rxmode |= URE_RCR_AM; hashes[0] = hashes[1] = 0xffffffff; goto done; } rxmode |= URE_RCR_AM; if_maddr_rlock(ifp); CK_STAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { if (ifma->ifma_addr->sa_family != AF_LINK) continue; h = ether_crc32_be(LLADDR((struct sockaddr_dl *) ifma->ifma_addr), ETHER_ADDR_LEN) >> 26; if (h < 32) hashes[0] |= (1 << h); else hashes[1] |= (1 << (h - 32)); } if_maddr_runlock(ifp); h = bswap32(hashes[0]); hashes[0] = bswap32(hashes[1]); hashes[1] = h; rxmode |= URE_RCR_AM; done: ure_write_4(sc, URE_PLA_MAR0, URE_MCU_TYPE_PLA, hashes[0]); ure_write_4(sc, URE_PLA_MAR4, URE_MCU_TYPE_PLA, hashes[1]); ure_write_4(sc, URE_PLA_RCR, URE_MCU_TYPE_PLA, rxmode); } static void ure_start(struct usb_ether *ue) { struct ure_softc *sc = uether_getsc(ue); /* * start the USB transfers, if not already started: */ usbd_transfer_start(sc->sc_xfer[URE_BULK_DT_RD]); usbd_transfer_start(sc->sc_xfer[URE_BULK_DT_WR]); } static void ure_reset(struct ure_softc *sc) { int i; ure_write_1(sc, URE_PLA_CR, URE_MCU_TYPE_PLA, URE_CR_RST); for (i = 0; i < URE_TIMEOUT; i++) { if (!(ure_read_1(sc, URE_PLA_CR, URE_MCU_TYPE_PLA) & URE_CR_RST)) break; uether_pause(&sc->sc_ue, hz / 100); } if (i == URE_TIMEOUT) device_printf(sc->sc_ue.ue_dev, "reset never completed\n"); } /* * Set media options. */ static int ure_ifmedia_upd(struct ifnet *ifp) { struct ure_softc *sc = ifp->if_softc; struct mii_data *mii = GET_MII(sc); struct mii_softc *miisc; int error; URE_LOCK_ASSERT(sc, MA_OWNED); LIST_FOREACH(miisc, &mii->mii_phys, mii_list) PHY_RESET(miisc); error = mii_mediachg(mii); return (error); } /* * Report current media status. */ static void ure_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) { struct ure_softc *sc; struct mii_data *mii; sc = ifp->if_softc; mii = GET_MII(sc); URE_LOCK(sc); mii_pollstat(mii); ifmr->ifm_active = mii->mii_media_active; ifmr->ifm_status = mii->mii_media_status; URE_UNLOCK(sc); } static int ure_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data) { struct usb_ether *ue = ifp->if_softc; struct ure_softc *sc; struct ifreq *ifr; int error, mask, reinit; sc = uether_getsc(ue); ifr = (struct ifreq *)data; error = 0; reinit = 0; if (cmd == SIOCSIFCAP) { URE_LOCK(sc); mask = ifr->ifr_reqcap ^ ifp->if_capenable; if (reinit > 0 && ifp->if_drv_flags & IFF_DRV_RUNNING) ifp->if_drv_flags &= ~IFF_DRV_RUNNING; else reinit = 0; URE_UNLOCK(sc); if (reinit > 0) uether_init(ue); } else error = uether_ioctl(ifp, cmd, data); return (error); } static void ure_rtl8152_init(struct ure_softc *sc) { uint32_t pwrctrl; /* Disable ALDPS. */ ure_ocp_reg_write(sc, URE_OCP_ALDPS_CONFIG, URE_ENPDNPS | URE_LINKENA | URE_DIS_SDSAVE); uether_pause(&sc->sc_ue, hz / 50); if (sc->sc_chip & URE_CHIP_VER_4C00) { ure_write_2(sc, URE_PLA_LED_FEATURE, URE_MCU_TYPE_PLA, ure_read_2(sc, URE_PLA_LED_FEATURE, URE_MCU_TYPE_PLA) & ~URE_LED_MODE_MASK); } ure_write_2(sc, URE_USB_UPS_CTRL, URE_MCU_TYPE_USB, ure_read_2(sc, URE_USB_UPS_CTRL, URE_MCU_TYPE_USB) & ~URE_POWER_CUT); ure_write_2(sc, URE_USB_PM_CTRL_STATUS, URE_MCU_TYPE_USB, ure_read_2(sc, URE_USB_PM_CTRL_STATUS, URE_MCU_TYPE_USB) & ~URE_RESUME_INDICATE); ure_write_2(sc, URE_PLA_PHY_PWR, URE_MCU_TYPE_PLA, ure_read_2(sc, URE_PLA_PHY_PWR, URE_MCU_TYPE_PLA) | URE_TX_10M_IDLE_EN | URE_PFM_PWM_SWITCH); pwrctrl = ure_read_4(sc, URE_PLA_MAC_PWR_CTRL, URE_MCU_TYPE_PLA); pwrctrl &= ~URE_MCU_CLK_RATIO_MASK; pwrctrl |= URE_MCU_CLK_RATIO | URE_D3_CLK_GATED_EN; ure_write_4(sc, URE_PLA_MAC_PWR_CTRL, URE_MCU_TYPE_PLA, pwrctrl); ure_write_2(sc, URE_PLA_GPHY_INTR_IMR, URE_MCU_TYPE_PLA, URE_GPHY_STS_MSK | URE_SPEED_DOWN_MSK | URE_SPDWN_RXDV_MSK | URE_SPDWN_LINKCHG_MSK); /* Disable Rx aggregation. */ ure_write_2(sc, URE_USB_USB_CTRL, URE_MCU_TYPE_USB, ure_read_2(sc, URE_USB_USB_CTRL, URE_MCU_TYPE_USB) | URE_RX_AGG_DISABLE); /* Disable ALDPS. */ ure_ocp_reg_write(sc, URE_OCP_ALDPS_CONFIG, URE_ENPDNPS | URE_LINKENA | URE_DIS_SDSAVE); uether_pause(&sc->sc_ue, hz / 50); ure_init_fifo(sc); ure_write_1(sc, URE_USB_TX_AGG, URE_MCU_TYPE_USB, URE_TX_AGG_MAX_THRESHOLD); ure_write_4(sc, URE_USB_RX_BUF_TH, URE_MCU_TYPE_USB, URE_RX_THR_HIGH); ure_write_4(sc, URE_USB_TX_DMA, URE_MCU_TYPE_USB, URE_TEST_MODE_DISABLE | URE_TX_SIZE_ADJUST1); } static void ure_rtl8153_init(struct ure_softc *sc) { uint16_t val; uint8_t u1u2[8]; int i; /* Disable ALDPS. */ ure_ocp_reg_write(sc, URE_OCP_POWER_CFG, ure_ocp_reg_read(sc, URE_OCP_POWER_CFG) & ~URE_EN_ALDPS); uether_pause(&sc->sc_ue, hz / 50); memset(u1u2, 0x00, sizeof(u1u2)); ure_write_mem(sc, URE_USB_TOLERANCE, URE_MCU_TYPE_USB | URE_BYTE_EN_SIX_BYTES, u1u2, sizeof(u1u2)); for (i = 0; i < URE_TIMEOUT; i++) { if (ure_read_2(sc, URE_PLA_BOOT_CTRL, URE_MCU_TYPE_PLA) & URE_AUTOLOAD_DONE) break; uether_pause(&sc->sc_ue, hz / 100); } if (i == URE_TIMEOUT) device_printf(sc->sc_ue.ue_dev, "timeout waiting for chip autoload\n"); for (i = 0; i < URE_TIMEOUT; i++) { val = ure_ocp_reg_read(sc, URE_OCP_PHY_STATUS) & URE_PHY_STAT_MASK; if (val == URE_PHY_STAT_LAN_ON || val == URE_PHY_STAT_PWRDN) break; uether_pause(&sc->sc_ue, hz / 100); } if (i == URE_TIMEOUT) device_printf(sc->sc_ue.ue_dev, "timeout waiting for phy to stabilize\n"); ure_write_2(sc, URE_USB_U2P3_CTRL, URE_MCU_TYPE_USB, ure_read_2(sc, URE_USB_U2P3_CTRL, URE_MCU_TYPE_USB) & ~URE_U2P3_ENABLE); if (sc->sc_chip & URE_CHIP_VER_5C10) { val = ure_read_2(sc, URE_USB_SSPHYLINK2, URE_MCU_TYPE_USB); val &= ~URE_PWD_DN_SCALE_MASK; val |= URE_PWD_DN_SCALE(96); ure_write_2(sc, URE_USB_SSPHYLINK2, URE_MCU_TYPE_USB, val); ure_write_1(sc, URE_USB_USB2PHY, URE_MCU_TYPE_USB, ure_read_1(sc, URE_USB_USB2PHY, URE_MCU_TYPE_USB) | URE_USB2PHY_L1 | URE_USB2PHY_SUSPEND); } else if (sc->sc_chip & URE_CHIP_VER_5C20) { ure_write_1(sc, URE_PLA_DMY_REG0, URE_MCU_TYPE_PLA, ure_read_1(sc, URE_PLA_DMY_REG0, URE_MCU_TYPE_PLA) & ~URE_ECM_ALDPS); } if (sc->sc_chip & (URE_CHIP_VER_5C20 | URE_CHIP_VER_5C30)) { val = ure_read_1(sc, URE_USB_CSR_DUMMY1, URE_MCU_TYPE_USB); if (ure_read_2(sc, URE_USB_BURST_SIZE, URE_MCU_TYPE_USB) == 0) val &= ~URE_DYNAMIC_BURST; else val |= URE_DYNAMIC_BURST; ure_write_1(sc, URE_USB_CSR_DUMMY1, URE_MCU_TYPE_USB, val); } ure_write_1(sc, URE_USB_CSR_DUMMY2, URE_MCU_TYPE_USB, ure_read_1(sc, URE_USB_CSR_DUMMY2, URE_MCU_TYPE_USB) | URE_EP4_FULL_FC); ure_write_2(sc, URE_USB_WDT11_CTRL, URE_MCU_TYPE_USB, ure_read_2(sc, URE_USB_WDT11_CTRL, URE_MCU_TYPE_USB) & ~URE_TIMER11_EN); ure_write_2(sc, URE_PLA_LED_FEATURE, URE_MCU_TYPE_PLA, ure_read_2(sc, URE_PLA_LED_FEATURE, URE_MCU_TYPE_PLA) & ~URE_LED_MODE_MASK); if ((sc->sc_chip & URE_CHIP_VER_5C10) && usbd_get_speed(sc->sc_ue.ue_udev) != USB_SPEED_SUPER) val = URE_LPM_TIMER_500MS; else val = URE_LPM_TIMER_500US; ure_write_1(sc, URE_USB_LPM_CTRL, URE_MCU_TYPE_USB, val | URE_FIFO_EMPTY_1FB | URE_ROK_EXIT_LPM); val = ure_read_2(sc, URE_USB_AFE_CTRL2, URE_MCU_TYPE_USB); val &= ~URE_SEN_VAL_MASK; val |= URE_SEN_VAL_NORMAL | URE_SEL_RXIDLE; ure_write_2(sc, URE_USB_AFE_CTRL2, URE_MCU_TYPE_USB, val); ure_write_2(sc, URE_USB_CONNECT_TIMER, URE_MCU_TYPE_USB, 0x0001); ure_write_2(sc, URE_USB_POWER_CUT, URE_MCU_TYPE_USB, ure_read_2(sc, URE_USB_POWER_CUT, URE_MCU_TYPE_USB) & ~(URE_PWR_EN | URE_PHASE2_EN)); ure_write_2(sc, URE_USB_MISC_0, URE_MCU_TYPE_USB, ure_read_2(sc, URE_USB_MISC_0, URE_MCU_TYPE_USB) & ~URE_PCUT_STATUS); memset(u1u2, 0xff, sizeof(u1u2)); ure_write_mem(sc, URE_USB_TOLERANCE, URE_MCU_TYPE_USB | URE_BYTE_EN_SIX_BYTES, u1u2, sizeof(u1u2)); ure_write_2(sc, URE_PLA_MAC_PWR_CTRL, URE_MCU_TYPE_PLA, URE_ALDPS_SPDWN_RATIO); ure_write_2(sc, URE_PLA_MAC_PWR_CTRL2, URE_MCU_TYPE_PLA, URE_EEE_SPDWN_RATIO); ure_write_2(sc, URE_PLA_MAC_PWR_CTRL3, URE_MCU_TYPE_PLA, URE_PKT_AVAIL_SPDWN_EN | URE_SUSPEND_SPDWN_EN | URE_U1U2_SPDWN_EN | URE_L1_SPDWN_EN); ure_write_2(sc, URE_PLA_MAC_PWR_CTRL4, URE_MCU_TYPE_PLA, URE_PWRSAVE_SPDWN_EN | URE_RXDV_SPDWN_EN | URE_TX10MIDLE_EN | URE_TP100_SPDWN_EN | URE_TP500_SPDWN_EN | URE_TP1000_SPDWN_EN | URE_EEE_SPDWN_EN); val = ure_read_2(sc, URE_USB_U2P3_CTRL, URE_MCU_TYPE_USB); if (!(sc->sc_chip & (URE_CHIP_VER_5C00 | URE_CHIP_VER_5C10))) val |= URE_U2P3_ENABLE; else val &= ~URE_U2P3_ENABLE; ure_write_2(sc, URE_USB_U2P3_CTRL, URE_MCU_TYPE_USB, val); memset(u1u2, 0x00, sizeof(u1u2)); ure_write_mem(sc, URE_USB_TOLERANCE, URE_MCU_TYPE_USB | URE_BYTE_EN_SIX_BYTES, u1u2, sizeof(u1u2)); /* Disable ALDPS. */ ure_ocp_reg_write(sc, URE_OCP_POWER_CFG, ure_ocp_reg_read(sc, URE_OCP_POWER_CFG) & ~URE_EN_ALDPS); uether_pause(&sc->sc_ue, hz / 50); ure_init_fifo(sc); /* Disable Rx aggregation. */ ure_write_2(sc, URE_USB_USB_CTRL, URE_MCU_TYPE_USB, ure_read_2(sc, URE_USB_USB_CTRL, URE_MCU_TYPE_USB) | URE_RX_AGG_DISABLE); val = ure_read_2(sc, URE_USB_U2P3_CTRL, URE_MCU_TYPE_USB); if (!(sc->sc_chip & (URE_CHIP_VER_5C00 | URE_CHIP_VER_5C10))) val |= URE_U2P3_ENABLE; else val &= ~URE_U2P3_ENABLE; ure_write_2(sc, URE_USB_U2P3_CTRL, URE_MCU_TYPE_USB, val); memset(u1u2, 0xff, sizeof(u1u2)); ure_write_mem(sc, URE_USB_TOLERANCE, URE_MCU_TYPE_USB | URE_BYTE_EN_SIX_BYTES, u1u2, sizeof(u1u2)); } static void ure_stop(struct usb_ether *ue) { struct ure_softc *sc = uether_getsc(ue); struct ifnet *ifp = uether_getifp(ue); URE_LOCK_ASSERT(sc, MA_OWNED); ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); sc->sc_flags &= ~URE_FLAG_LINK; /* * stop all the transfers, if not already stopped: */ usbd_transfer_stop(sc->sc_xfer[URE_BULK_DT_WR]); usbd_transfer_stop(sc->sc_xfer[URE_BULK_DT_RD]); } static void ure_disable_teredo(struct ure_softc *sc) { ure_write_4(sc, URE_PLA_TEREDO_CFG, URE_MCU_TYPE_PLA, ure_read_4(sc, URE_PLA_TEREDO_CFG, URE_MCU_TYPE_PLA) & ~(URE_TEREDO_SEL | URE_TEREDO_RS_EVENT_MASK | URE_OOB_TEREDO_EN)); ure_write_2(sc, URE_PLA_WDT6_CTRL, URE_MCU_TYPE_PLA, URE_WDT6_SET_MODE); ure_write_2(sc, URE_PLA_REALWOW_TIMER, URE_MCU_TYPE_PLA, 0); ure_write_4(sc, URE_PLA_TEREDO_TIMER, URE_MCU_TYPE_PLA, 0); } static void ure_init_fifo(struct ure_softc *sc) { uint32_t rx_fifo1, rx_fifo2; int i; ure_write_2(sc, URE_PLA_MISC_1, URE_MCU_TYPE_PLA, ure_read_2(sc, URE_PLA_MISC_1, URE_MCU_TYPE_PLA) | URE_RXDY_GATED_EN); ure_disable_teredo(sc); ure_write_4(sc, URE_PLA_RCR, URE_MCU_TYPE_PLA, ure_read_4(sc, URE_PLA_RCR, URE_MCU_TYPE_PLA) & ~URE_RCR_ACPT_ALL); if (!(sc->sc_flags & URE_FLAG_8152)) { if (sc->sc_chip & (URE_CHIP_VER_5C00 | URE_CHIP_VER_5C10 | URE_CHIP_VER_5C20)) { ure_ocp_reg_write(sc, URE_OCP_ADC_CFG, URE_CKADSEL_L | URE_ADC_EN | URE_EN_EMI_L); } if (sc->sc_chip & URE_CHIP_VER_5C00) { ure_ocp_reg_write(sc, URE_OCP_EEE_CFG, ure_ocp_reg_read(sc, URE_OCP_EEE_CFG) & ~URE_CTAP_SHORT_EN); } ure_ocp_reg_write(sc, URE_OCP_POWER_CFG, ure_ocp_reg_read(sc, URE_OCP_POWER_CFG) | URE_EEE_CLKDIV_EN); ure_ocp_reg_write(sc, URE_OCP_DOWN_SPEED, ure_ocp_reg_read(sc, URE_OCP_DOWN_SPEED) | URE_EN_10M_BGOFF); ure_ocp_reg_write(sc, URE_OCP_POWER_CFG, ure_ocp_reg_read(sc, URE_OCP_POWER_CFG) | URE_EN_10M_PLLOFF); ure_ocp_reg_write(sc, URE_OCP_SRAM_ADDR, URE_SRAM_IMPEDANCE); ure_ocp_reg_write(sc, URE_OCP_SRAM_DATA, 0x0b13); ure_write_2(sc, URE_PLA_PHY_PWR, URE_MCU_TYPE_PLA, ure_read_2(sc, URE_PLA_PHY_PWR, URE_MCU_TYPE_PLA) | URE_PFM_PWM_SWITCH); /* Enable LPF corner auto tune. */ ure_ocp_reg_write(sc, URE_OCP_SRAM_ADDR, URE_SRAM_LPF_CFG); ure_ocp_reg_write(sc, URE_OCP_SRAM_DATA, 0xf70f); /* Adjust 10M amplitude. */ ure_ocp_reg_write(sc, URE_OCP_SRAM_ADDR, URE_SRAM_10M_AMP1); ure_ocp_reg_write(sc, URE_OCP_SRAM_DATA, 0x00af); ure_ocp_reg_write(sc, URE_OCP_SRAM_ADDR, URE_SRAM_10M_AMP2); ure_ocp_reg_write(sc, URE_OCP_SRAM_DATA, 0x0208); } ure_reset(sc); ure_write_1(sc, URE_PLA_CR, URE_MCU_TYPE_PLA, 0); ure_write_1(sc, URE_PLA_OOB_CTRL, URE_MCU_TYPE_PLA, ure_read_1(sc, URE_PLA_OOB_CTRL, URE_MCU_TYPE_PLA) & ~URE_NOW_IS_OOB); ure_write_2(sc, URE_PLA_SFF_STS_7, URE_MCU_TYPE_PLA, ure_read_2(sc, URE_PLA_SFF_STS_7, URE_MCU_TYPE_PLA) & ~URE_MCU_BORW_EN); for (i = 0; i < URE_TIMEOUT; i++) { if (ure_read_1(sc, URE_PLA_OOB_CTRL, URE_MCU_TYPE_PLA) & URE_LINK_LIST_READY) break; uether_pause(&sc->sc_ue, hz / 100); } if (i == URE_TIMEOUT) device_printf(sc->sc_ue.ue_dev, "timeout waiting for OOB control\n"); ure_write_2(sc, URE_PLA_SFF_STS_7, URE_MCU_TYPE_PLA, ure_read_2(sc, URE_PLA_SFF_STS_7, URE_MCU_TYPE_PLA) | URE_RE_INIT_LL); for (i = 0; i < URE_TIMEOUT; i++) { if (ure_read_1(sc, URE_PLA_OOB_CTRL, URE_MCU_TYPE_PLA) & URE_LINK_LIST_READY) break; uether_pause(&sc->sc_ue, hz / 100); } if (i == URE_TIMEOUT) device_printf(sc->sc_ue.ue_dev, "timeout waiting for OOB control\n"); ure_write_2(sc, URE_PLA_CPCR, URE_MCU_TYPE_PLA, ure_read_2(sc, URE_PLA_CPCR, URE_MCU_TYPE_PLA) & ~URE_CPCR_RX_VLAN); ure_write_2(sc, URE_PLA_TCR0, URE_MCU_TYPE_PLA, ure_read_2(sc, URE_PLA_TCR0, URE_MCU_TYPE_PLA) | URE_TCR0_AUTO_FIFO); /* Configure Rx FIFO threshold. */ ure_write_4(sc, URE_PLA_RXFIFO_CTRL0, URE_MCU_TYPE_PLA, URE_RXFIFO_THR1_NORMAL); if (usbd_get_speed(sc->sc_ue.ue_udev) == USB_SPEED_FULL) { rx_fifo1 = URE_RXFIFO_THR2_FULL; rx_fifo2 = URE_RXFIFO_THR3_FULL; } else { rx_fifo1 = URE_RXFIFO_THR2_HIGH; rx_fifo2 = URE_RXFIFO_THR3_HIGH; } ure_write_4(sc, URE_PLA_RXFIFO_CTRL1, URE_MCU_TYPE_PLA, rx_fifo1); ure_write_4(sc, URE_PLA_RXFIFO_CTRL2, URE_MCU_TYPE_PLA, rx_fifo2); /* Configure Tx FIFO threshold. */ ure_write_4(sc, URE_PLA_TXFIFO_CTRL, URE_MCU_TYPE_PLA, URE_TXFIFO_THR_NORMAL); }