Index: stable/12/sys/arm/mv/a37x0_gpio.c =================================================================== --- stable/12/sys/arm/mv/a37x0_gpio.c (nonexistent) +++ stable/12/sys/arm/mv/a37x0_gpio.c (revision 351139) @@ -0,0 +1,352 @@ +/*- + * SPDX-License-Identifier: BSD-2-Clause-FreeBSD + * + * Copyright (c) 2018-2019, Rubicon Communications, LLC (Netgate) + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + */ + +#include +__FBSDID("$FreeBSD$"); + +#include +#include +#include + +#include +#include +#include +#include + +#include +#include + +#include +#include +#include + +#include "gpio_if.h" + +static struct resource_spec a37x0_gpio_res_spec[] = { + { SYS_RES_MEMORY, 0, RF_ACTIVE }, /* Pinctl / GPIO */ + { SYS_RES_MEMORY, 1, RF_ACTIVE }, /* Interrupts control */ + { -1, 0, 0 } +}; + +struct a37x0_gpio_softc { + bus_space_tag_t sc_bst; + bus_space_handle_t sc_bsh; + device_t sc_busdev; + int sc_type; + uint32_t sc_max_pins; + uint32_t sc_npins; + struct resource *sc_mem_res[nitems(a37x0_gpio_res_spec) - 1]; +}; + +/* Memory regions. */ +#define A37X0_GPIO 0 +#define A37X0_INTR 1 + +/* North Bridge / South Bridge. */ +#define A37X0_NB_GPIO 1 +#define A37X0_SB_GPIO 2 + +#define A37X0_GPIO_WRITE(_sc, _off, _val) \ + bus_space_write_4((_sc)->sc_bst, (_sc)->sc_bsh, (_off), (_val)) +#define A37X0_GPIO_READ(_sc, _off) \ + bus_space_read_4((_sc)->sc_bst, (_sc)->sc_bsh, (_off)) + +#define A37X0_GPIO_BIT(_p) (1U << ((_p) % 32)) +#define A37X0_GPIO_OUT_EN(_p) (0x0 + ((_p) / 32) * 4) +#define A37X0_GPIO_LATCH(_p) (0x8 + ((_p) / 32) * 4) +#define A37X0_GPIO_INPUT(_p) (0x10 + ((_p) / 32) * 4) +#define A37X0_GPIO_OUTPUT(_p) (0x18 + ((_p) / 32) * 4) +#define A37X0_GPIO_SEL 0x30 + + +static struct ofw_compat_data compat_data[] = { + { "marvell,armada3710-nb-pinctrl", A37X0_NB_GPIO }, + { "marvell,armada3710-sb-pinctrl", A37X0_SB_GPIO }, + { NULL, 0 } +}; + +static phandle_t +a37x0_gpio_get_node(device_t bus, device_t dev) +{ + + return (ofw_bus_get_node(bus)); +} + +static device_t +a37x0_gpio_get_bus(device_t dev) +{ + struct a37x0_gpio_softc *sc; + + sc = device_get_softc(dev); + + return (sc->sc_busdev); +} + +static int +a37x0_gpio_pin_max(device_t dev, int *maxpin) +{ + struct a37x0_gpio_softc *sc; + + sc = device_get_softc(dev); + *maxpin = sc->sc_npins - 1; + + return (0); +} + +static int +a37x0_gpio_pin_getname(device_t dev, uint32_t pin, char *name) +{ + struct a37x0_gpio_softc *sc; + + sc = device_get_softc(dev); + if (pin >= sc->sc_npins) + return (EINVAL); + snprintf(name, GPIOMAXNAME, "pin %d", pin); + + return (0); +} + +static int +a37x0_gpio_pin_getcaps(device_t dev, uint32_t pin, uint32_t *caps) +{ + struct a37x0_gpio_softc *sc; + + sc = device_get_softc(dev); + if (pin >= sc->sc_npins) + return (EINVAL); + *caps = GPIO_PIN_INPUT | GPIO_PIN_OUTPUT; + + return (0); +} + +static int +a37x0_gpio_pin_getflags(device_t dev, uint32_t pin, uint32_t *flags) +{ + struct a37x0_gpio_softc *sc; + uint32_t reg; + + sc = device_get_softc(dev); + if (pin >= sc->sc_npins) + return (EINVAL); + reg = A37X0_GPIO_READ(sc, A37X0_GPIO_OUT_EN(pin)); + if ((reg & A37X0_GPIO_BIT(pin)) != 0) + *flags = GPIO_PIN_OUTPUT; + else + *flags = GPIO_PIN_INPUT; + + return (0); +} + +static int +a37x0_gpio_pin_setflags(device_t dev, uint32_t pin, uint32_t flags) +{ + struct a37x0_gpio_softc *sc; + uint32_t reg; + + sc = device_get_softc(dev); + if (pin >= sc->sc_npins) + return (EINVAL); + + reg = A37X0_GPIO_READ(sc, A37X0_GPIO_OUT_EN(pin)); + if (flags & GPIO_PIN_OUTPUT) + reg |= A37X0_GPIO_BIT(pin); + else + reg &= ~A37X0_GPIO_BIT(pin); + A37X0_GPIO_WRITE(sc, A37X0_GPIO_OUT_EN(pin), reg); + + return (0); +} + +static int +a37x0_gpio_pin_get(device_t dev, uint32_t pin, unsigned int *val) +{ + struct a37x0_gpio_softc *sc; + uint32_t reg; + + sc = device_get_softc(dev); + if (pin >= sc->sc_npins) + return (EINVAL); + + reg = A37X0_GPIO_READ(sc, A37X0_GPIO_OUT_EN(pin)); + if ((reg & A37X0_GPIO_BIT(pin)) != 0) + reg = A37X0_GPIO_READ(sc, A37X0_GPIO_OUTPUT(pin)); + else + reg = A37X0_GPIO_READ(sc, A37X0_GPIO_INPUT(pin)); + *val = ((reg & A37X0_GPIO_BIT(pin)) != 0) ? 1 : 0; + + return (0); +} + +static int +a37x0_gpio_pin_set(device_t dev, uint32_t pin, unsigned int val) +{ + struct a37x0_gpio_softc *sc; + uint32_t reg; + + sc = device_get_softc(dev); + if (pin >= sc->sc_npins) + return (EINVAL); + + reg = A37X0_GPIO_READ(sc, A37X0_GPIO_OUTPUT(pin)); + if (val != 0) + reg |= A37X0_GPIO_BIT(pin); + else + reg &= ~A37X0_GPIO_BIT(pin); + A37X0_GPIO_WRITE(sc, A37X0_GPIO_OUTPUT(pin), reg); + + return (0); +} + +static int +a37x0_gpio_pin_toggle(device_t dev, uint32_t pin) +{ + struct a37x0_gpio_softc *sc; + uint32_t reg; + + sc = device_get_softc(dev); + if (pin >= sc->sc_npins) + return (EINVAL); + + reg = A37X0_GPIO_READ(sc, A37X0_GPIO_OUT_EN(pin)); + if ((reg & A37X0_GPIO_BIT(pin)) == 0) + return (EINVAL); + reg = A37X0_GPIO_READ(sc, A37X0_GPIO_OUTPUT(pin)); + reg ^= A37X0_GPIO_BIT(pin); + A37X0_GPIO_WRITE(sc, A37X0_GPIO_OUTPUT(pin), reg); + + return (0); +} + +static int +a37x0_gpio_probe(device_t dev) +{ + const char *desc; + struct a37x0_gpio_softc *sc; + + if (!OF_hasprop(ofw_bus_get_node(dev), "gpio-controller")) + return (ENXIO); + + sc = device_get_softc(dev); + sc->sc_type = ofw_bus_search_compatible( + device_get_parent(dev), compat_data)->ocd_data; + switch (sc->sc_type) { + case A37X0_NB_GPIO: + sc->sc_max_pins = 36; + desc = "Armada 37x0 North Bridge GPIO Controller"; + break; + case A37X0_SB_GPIO: + sc->sc_max_pins = 30; + desc = "Armada 37x0 South Bridge GPIO Controller"; + break; + default: + return (ENXIO); + } + device_set_desc(dev, desc); + + return (BUS_PROBE_DEFAULT); +} + +static int +a37x0_gpio_attach(device_t dev) +{ + int err, ncells; + pcell_t *ranges; + struct a37x0_gpio_softc *sc; + + sc = device_get_softc(dev); + + /* Read and verify the "gpio-ranges" property. */ + ncells = OF_getencprop_alloc(ofw_bus_get_node(dev), "gpio-ranges", + (void **)&ranges); + if (ncells == -1) + return (ENXIO); + if (ncells != sizeof(*ranges) * 4 || ranges[1] != 0 || ranges[2] != 0) { + OF_prop_free(ranges); + return (ENXIO); + } + sc->sc_npins = ranges[3]; + OF_prop_free(ranges); + + /* Check the number of pins in the DTS vs HW capabilities. */ + if (sc->sc_npins > sc->sc_max_pins) + return (ENXIO); + + err = bus_alloc_resources(dev, a37x0_gpio_res_spec, sc->sc_mem_res); + if (err != 0) { + device_printf(dev, "cannot allocate memory window\n"); + return (ENXIO); + } + sc->sc_bst = rman_get_bustag(sc->sc_mem_res[A37X0_GPIO]); + sc->sc_bsh = rman_get_bushandle(sc->sc_mem_res[A37X0_GPIO]); + + sc->sc_busdev = gpiobus_attach_bus(dev); + if (sc->sc_busdev == NULL) + return (ENXIO); + + return (0); +} + +static int +a37x0_gpio_detach(device_t dev) +{ + + return (EBUSY); +} + +static device_method_t a37x0_gpio_methods[] = { + /* Device interface */ + DEVMETHOD(device_probe, a37x0_gpio_probe), + DEVMETHOD(device_attach, a37x0_gpio_attach), + DEVMETHOD(device_detach, a37x0_gpio_detach), + + /* GPIO interface */ + DEVMETHOD(gpio_get_bus, a37x0_gpio_get_bus), + DEVMETHOD(gpio_pin_max, a37x0_gpio_pin_max), + DEVMETHOD(gpio_pin_getname, a37x0_gpio_pin_getname), + DEVMETHOD(gpio_pin_getcaps, a37x0_gpio_pin_getcaps), + DEVMETHOD(gpio_pin_getflags, a37x0_gpio_pin_getflags), + DEVMETHOD(gpio_pin_setflags, a37x0_gpio_pin_setflags), + DEVMETHOD(gpio_pin_get, a37x0_gpio_pin_get), + DEVMETHOD(gpio_pin_set, a37x0_gpio_pin_set), + DEVMETHOD(gpio_pin_toggle, a37x0_gpio_pin_toggle), + + /* ofw_bus interface */ + DEVMETHOD(ofw_bus_get_node, a37x0_gpio_get_node), + + DEVMETHOD_END +}; + +static devclass_t a37x0_gpio_devclass; +static driver_t a37x0_gpio_driver = { + "gpio", + a37x0_gpio_methods, + sizeof(struct a37x0_gpio_softc), +}; + +EARLY_DRIVER_MODULE(a37x0_gpio, simple_mfd, a37x0_gpio_driver, + a37x0_gpio_devclass, 0, 0, BUS_PASS_INTERRUPT + BUS_PASS_ORDER_LAST); Property changes on: stable/12/sys/arm/mv/a37x0_gpio.c ___________________________________________________________________ Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:keywords ## -0,0 +1 ## +FreeBSD=%H \ No newline at end of property Added: svn:mime-type ## -0,0 +1 ## +text/plain \ No newline at end of property Index: stable/12/sys/arm64/conf/GENERIC =================================================================== --- stable/12/sys/arm64/conf/GENERIC (revision 351138) +++ stable/12/sys/arm64/conf/GENERIC (revision 351139) @@ -1,301 +1,302 @@ # # GENERIC -- Generic kernel configuration file for FreeBSD/arm64 # # For more information on this file, please read the config(5) manual page, # and/or the handbook section on Kernel Configuration Files: # # https://www.FreeBSD.org/doc/en_US.ISO8859-1/books/handbook/kernelconfig-config.html # # The handbook is also available locally in /usr/share/doc/handbook # if you've installed the doc distribution, otherwise always see the # FreeBSD World Wide Web server (https://www.FreeBSD.org/) for the # latest information. # # An exhaustive list of options and more detailed explanations of the # device lines is also present in the ../../conf/NOTES and NOTES files. # If you are in doubt as to the purpose or necessity of a line, check first # in NOTES. # # $FreeBSD$ cpu ARM64 ident GENERIC makeoptions DEBUG=-g # Build kernel with gdb(1) debug symbols makeoptions WITH_CTF=1 # Run ctfconvert(1) for DTrace support options SCHED_ULE # ULE scheduler options PREEMPTION # Enable kernel thread preemption options VIMAGE # Subsystem virtualization, e.g. VNET options INET # InterNETworking options INET6 # IPv6 communications protocols options IPSEC # IP (v4/v6) security options IPSEC_SUPPORT # Allow kldload of ipsec and tcpmd5 options TCP_HHOOK # hhook(9) framework for TCP options TCP_OFFLOAD # TCP offload options TCP_RFC7413 # TCP Fast Open options SCTP # Stream Control Transmission Protocol options FFS # Berkeley Fast Filesystem options SOFTUPDATES # Enable FFS soft updates support options UFS_ACL # Support for access control lists options UFS_DIRHASH # Improve performance on big directories options UFS_GJOURNAL # Enable gjournal-based UFS journaling options QUOTA # Enable disk quotas for UFS options MD_ROOT # MD is a potential root device options NFSCL # Network Filesystem Client options NFSD # Network Filesystem Server options NFSLOCKD # Network Lock Manager options NFS_ROOT # NFS usable as /, requires NFSCL options MSDOSFS # MSDOS Filesystem options CD9660 # ISO 9660 Filesystem options PROCFS # Process filesystem (requires PSEUDOFS) options PSEUDOFS # Pseudo-filesystem framework options GEOM_RAID # Soft RAID functionality. options GEOM_LABEL # Provides labelization options COMPAT_FREEBSD32 # Incomplete, but used by cloudabi32.ko. options COMPAT_FREEBSD11 # Compatible with FreeBSD11 options SCSI_DELAY=5000 # Delay (in ms) before probing SCSI options KTRACE # ktrace(1) support options STACK # stack(9) support options SYSVSHM # SYSV-style shared memory options SYSVMSG # SYSV-style message queues options SYSVSEM # SYSV-style semaphores options _KPOSIX_PRIORITY_SCHEDULING # POSIX P1003_1B real-time extensions options PRINTF_BUFR_SIZE=128 # Prevent printf output being interspersed. options KBD_INSTALL_CDEV # install a CDEV entry in /dev options HWPMC_HOOKS # Necessary kernel hooks for hwpmc(4) options AUDIT # Security event auditing options CAPABILITY_MODE # Capsicum capability mode options CAPABILITIES # Capsicum capabilities options MAC # TrustedBSD MAC Framework options KDTRACE_FRAME # Ensure frames are compiled in options KDTRACE_HOOKS # Kernel DTrace hooks options VFP # Floating-point support options RACCT # Resource accounting framework options RACCT_DEFAULT_TO_DISABLED # Set kern.racct.enable=0 by default options RCTL # Resource limits options SMP options INTRNG # Debugging support. Always need this: options KDB # Enable kernel debugger support. options KDB_TRACE # Print a stack trace for a panic. # Kernel dump features. options EKCD # Support for encrypted kernel dumps options GZIO # gzip-compressed kernel and user dumps options ZSTDIO # zstd-compressed kernel and user dumps options NETDUMP # netdump(4) client support # SoC support options SOC_ALLWINNER_A64 options SOC_ALLWINNER_H5 options SOC_CAVM_THUNDERX options SOC_HISI_HI6220 options SOC_BRCM_BCM2837 options SOC_MARVELL_8K options SOC_ROCKCHIP_RK3328 options SOC_ROCKCHIP_RK3399 options SOC_XILINX_ZYNQ # Timer drivers device a10_timer # Annapurna Alpine drivers device al_ccu # Alpine Cache Coherency Unit device al_nb_service # Alpine North Bridge Service device al_iofic # I/O Fabric Interrupt Controller device al_serdes # Serializer/Deserializer device al_udma # Universal DMA # Qualcomm Snapdragon drivers device qcom_gcc # Global Clock Controller # VirtIO support device virtio device virtio_pci device virtio_mmio device virtio_blk device vtnet # CPU frequency control device cpufreq # Bus drivers device pci device al_pci # Annapurna Alpine PCI-E options PCI_HP # PCI-Express native HotPlug options PCI_IOV # PCI SR-IOV support # PCI/PCI-X/PCIe Ethernet NICs that use iflib infrastructure device iflib device em # Intel PRO/1000 Gigabit Ethernet Family device ix # Intel 10Gb Ethernet Family # Ethernet NICs device mdio device mii device miibus # MII bus support device awg # Allwinner EMAC Gigabit Ethernet device axgbe # AMD Opteron A1100 integrated NIC device msk # Marvell/SysKonnect Yukon II Gigabit Ethernet device neta # Marvell Armada 370/38x/XP/3700 NIC device smc # SMSC LAN91C111 device vnic # Cavium ThunderX NIC device al_eth # Annapurna Alpine Ethernet NIC device dwc_rk # Rockchip Designware # Block devices device ahci device scbus device da # ATA/SCSI peripherals device pass # Passthrough device (direct ATA/SCSI access) # NVM Express (NVMe) support device nvme # base NVMe driver options NVME_USE_NVD=0 # prefer the cam(4) based nda(4) driver device nvd # expose NVMe namespaces as disks, depends on nvme # MMC/SD/SDIO Card slot support device sdhci device sdhci_xenon # Marvell Xenon SD/MMC controller device aw_mmc # Allwinner SD/MMC controller device mmc # mmc/sd bus device mmcsd # mmc/sd flash cards device dwmmc # Serial (COM) ports device uart # Generic UART driver device uart_msm # Qualcomm MSM UART driver device uart_mu # RPI3 aux port device uart_mvebu # Armada 3700 UART driver device uart_ns8250 # ns8250-type UART driver device uart_snps device pl011 # USB support device aw_ehci # Allwinner EHCI USB interface (USB 2.0) device aw_usbphy # Allwinner USB PHY device dwcotg # DWC OTG controller device ohci # OHCI USB interface device ehci # EHCI USB interface (USB 2.0) device ehci_mv # Marvell EHCI USB interface device xhci # XHCI PCI->USB interface (USB 3.0) device usb # USB Bus (required) device ukbd # Keyboard device umass # Disks/Mass storage - Requires scbus and da # USB ethernet support device muge device smcphy device smsc # Sound support device sound device a10_codec # DMA controller device a31_dmac # GPIO / PINCTRL +device a37x0_gpio # Marvell Armada 37x0 GPIO controller device aw_gpio # Allwinner GPIO controller device gpio device gpioled device fdt_pinctrl device gpioregulator device mv_gpio # Marvell GPIO controller device mvebu_pinctrl # Marvell Pinmux Controller device rk_gpio # RockChip GPIO Controller device rk_pinctrl # RockChip Pinmux Controller # I2C device aw_rsb # Allwinner Reduced Serial Bus device bcm2835_bsc # Broadcom BCM283x I2C bus device iicbus device iic device twsi # Allwinner I2C controller device syr827 # Silergy SYR827 PMIC device rk_i2c # RockChip I2C controller # Clock and reset controllers device aw_ccu # Allwinner clock controller # Interrupt controllers device aw_nmi # Allwinner NMI support device mv_cp110_icu # Marvell CP110 ICU device mv_ap806_gicp # Marvell AP806 GICP # Real-time clock support device aw_rtc # Allwinner Real-time Clock device mv_rtc # Marvell Real-time Clock # Watchdog controllers device aw_wdog # Allwinner Watchdog # Power management controllers device axp81x # X-Powers AXP81x PMIC device rk805 # RockChip RK805 PMIC # EFUSE device aw_sid # Allwinner Secure ID EFUSE # Thermal sensors device aw_thermal # Allwinner Thermal Sensor Controller device mv_thermal # Marvell Thermal Sensor Controller # SPI device spibus device bcm2835_spi # Broadcom BCM283x SPI bus # PWM device pwm device aw_pwm # Console device vt device kbdmux device vt_efifb # EVDEV support device evdev # input event device support options EVDEV_SUPPORT # evdev support in legacy drivers device uinput # install /dev/uinput cdev # Pseudo devices. device crypto # core crypto support device loop # Network loopback device random # Entropy device device ether # Ethernet support device vlan # 802.1Q VLAN support device tun # Packet tunnel. device md # Memory "disks" device gif # IPv6 and IPv4 tunneling device firmware # firmware assist module options EFIRT # EFI Runtime Services # EXT_RESOURCES pseudo devices options EXT_RESOURCES device clk device phy device hwreset device nvmem device regulator device syscon device aw_syscon # The `bpf' device enables the Berkeley Packet Filter. # Be aware of the administrative consequences of enabling this! # Note that 'bpf' is required for DHCP. device bpf # Berkeley packet filter # Chip-specific errata options THUNDERX_PASS_1_1_ERRATA options FDT device acpi # DTBs makeoptions MODULES_EXTRA="dtb/allwinner dtb/rockchip dtb/rpi" Index: stable/12/sys/conf/files.arm64 =================================================================== --- stable/12/sys/conf/files.arm64 (revision 351138) +++ stable/12/sys/conf/files.arm64 (revision 351139) @@ -1,290 +1,291 @@ # $FreeBSD$ cloudabi32_vdso.o optional compat_cloudabi32 \ dependency "$S/contrib/cloudabi/cloudabi_vdso_armv6_on_64bit.S" \ compile-with "${CC} -x assembler-with-cpp -m32 -shared -nostdinc -nostdlib -Wl,-T$S/compat/cloudabi/cloudabi_vdso.lds $S/contrib/cloudabi/cloudabi_vdso_armv6_on_64bit.S -o ${.TARGET}" \ no-obj no-implicit-rule \ clean "cloudabi32_vdso.o" # cloudabi32_vdso_blob.o optional compat_cloudabi32 \ dependency "cloudabi32_vdso.o" \ compile-with "${OBJCOPY} --input-target binary --output-target elf64-littleaarch64 --binary-architecture aarch64 cloudabi32_vdso.o ${.TARGET}" \ no-implicit-rule \ clean "cloudabi32_vdso_blob.o" # cloudabi64_vdso.o optional compat_cloudabi64 \ dependency "$S/contrib/cloudabi/cloudabi_vdso_aarch64.S" \ compile-with "${CC} -x assembler-with-cpp -shared -nostdinc -nostdlib -Wl,-T$S/compat/cloudabi/cloudabi_vdso.lds $S/contrib/cloudabi/cloudabi_vdso_aarch64.S -o ${.TARGET}" \ no-obj no-implicit-rule \ clean "cloudabi64_vdso.o" # cloudabi64_vdso_blob.o optional compat_cloudabi64 \ dependency "cloudabi64_vdso.o" \ compile-with "${OBJCOPY} --input-target binary --output-target elf64-littleaarch64 --binary-architecture aarch64 cloudabi64_vdso.o ${.TARGET}" \ no-implicit-rule \ clean "cloudabi64_vdso_blob.o" # # Allwinner common files arm/allwinner/a10_ehci.c optional ehci aw_ehci fdt arm/allwinner/a10_timer.c optional a10_timer fdt arm/allwinner/a10_codec.c optional sound a10_codec arm/allwinner/a31_dmac.c optional a31_dmac arm/allwinner/sunxi_dma_if.m optional a31_dmac arm/allwinner/aw_cir.c optional evdev aw_cir fdt arm/allwinner/aw_gpio.c optional gpio aw_gpio fdt arm/allwinner/aw_mmc.c optional mmc aw_mmc fdt | mmccam aw_mmc fdt arm/allwinner/aw_nmi.c optional aw_nmi fdt \ compile-with "${NORMAL_C} -I$S/gnu/dts/include" arm/allwinner/aw_pwm.c optional aw_pwm fdt arm/allwinner/aw_rsb.c optional aw_rsb fdt arm/allwinner/aw_rtc.c optional aw_rtc fdt arm/allwinner/aw_sid.c optional aw_sid nvmem fdt arm/allwinner/aw_spi.c optional aw_spi fdt arm/allwinner/aw_syscon.c optional aw_syscon ext_resources syscon fdt arm/allwinner/aw_thermal.c optional aw_thermal nvmem fdt arm/allwinner/aw_usbphy.c optional ehci aw_usbphy fdt arm/allwinner/aw_wdog.c optional aw_wdog fdt arm/allwinner/axp81x.c optional axp81x fdt arm/allwinner/if_awg.c optional awg ext_resources syscon aw_sid nvmem fdt # Allwinner clock driver arm/allwinner/clkng/aw_ccung.c optional aw_ccu fdt arm/allwinner/clkng/aw_clk_frac.c optional aw_ccu fdt arm/allwinner/clkng/aw_clk_nkmp.c optional aw_ccu fdt arm/allwinner/clkng/aw_clk_nm.c optional aw_ccu fdt arm/allwinner/clkng/aw_clk_prediv_mux.c optional aw_ccu fdt arm/allwinner/clkng/ccu_a64.c optional soc_allwinner_a64 aw_ccu fdt arm/allwinner/clkng/ccu_h3.c optional soc_allwinner_h5 aw_ccu fdt arm/allwinner/clkng/ccu_sun8i_r.c optional aw_ccu fdt arm/allwinner/clkng/ccu_de2.c optional aw_ccu fdt # Allwinner padconf files arm/allwinner/a64/a64_padconf.c optional soc_allwinner_a64 fdt arm/allwinner/a64/a64_r_padconf.c optional soc_allwinner_a64 fdt arm/allwinner/h3/h3_padconf.c optional soc_allwinner_h5 fdt arm/allwinner/h3/h3_r_padconf.c optional soc_allwinner_h5 fdt arm/annapurna/alpine/alpine_ccu.c optional al_ccu fdt arm/annapurna/alpine/alpine_nb_service.c optional al_nb_service fdt arm/annapurna/alpine/alpine_pci.c optional al_pci fdt arm/annapurna/alpine/alpine_pci_msix.c optional al_pci fdt arm/annapurna/alpine/alpine_serdes.c optional al_serdes fdt \ no-depend \ compile-with "${CC} -c -o ${.TARGET} ${CFLAGS} -I$S/contrib/alpine-hal -I$S/contrib/alpine-hal/eth ${PROF} ${.IMPSRC}" arm/arm/generic_timer.c standard arm/arm/gic.c standard arm/arm/gic_acpi.c optional acpi arm/arm/gic_fdt.c optional fdt arm/arm/pmu.c standard arm/arm/physmem.c standard arm/broadcom/bcm2835/bcm2835_audio.c optional sound vchiq fdt \ compile-with "${NORMAL_C} -DUSE_VCHIQ_ARM -D__VCCOREVER__=0x04000000 -I$S/contrib/vchiq" arm/broadcom/bcm2835/bcm2835_bsc.c optional bcm2835_bsc soc_brcm_bcm2837 fdt arm/broadcom/bcm2835/bcm2835_cpufreq.c optional soc_brcm_bcm2837 fdt arm/broadcom/bcm2835/bcm2835_dma.c optional soc_brcm_bcm2837 fdt arm/broadcom/bcm2835/bcm2835_fbd.c optional vt soc_brcm_bcm2837 fdt arm/broadcom/bcm2835/bcm2835_ft5406.c optional evdev bcm2835_ft5406 soc_brcm_bcm2837 fdt arm/broadcom/bcm2835/bcm2835_gpio.c optional gpio soc_brcm_bcm2837 fdt arm/broadcom/bcm2835/bcm2835_intr.c optional soc_brcm_bcm2837 fdt arm/broadcom/bcm2835/bcm2835_mbox.c optional soc_brcm_bcm2837 fdt arm/broadcom/bcm2835/bcm2835_rng.c optional random soc_brcm_bcm2837 fdt arm/broadcom/bcm2835/bcm2835_sdhci.c optional sdhci soc_brcm_bcm2837 fdt arm/broadcom/bcm2835/bcm2835_sdhost.c optional sdhci soc_brcm_bcm2837 fdt arm/broadcom/bcm2835/bcm2835_spi.c optional bcm2835_spi soc_brcm_bcm2837 fdt arm/broadcom/bcm2835/bcm2835_vcio.c optional soc_brcm_bcm2837 fdt arm/broadcom/bcm2835/bcm2835_wdog.c optional soc_brcm_bcm2837 fdt arm/broadcom/bcm2835/bcm2836.c optional soc_brcm_bcm2837 fdt arm/broadcom/bcm2835/bcm283x_dwc_fdt.c optional dwcotg fdt soc_brcm_bcm2837 +arm/mv/a37x0_gpio.c optional a37x0_gpio gpio fdt arm/mv/gpio.c optional mv_gpio fdt arm/mv/mvebu_pinctrl.c optional mvebu_pinctrl fdt arm/mv/mv_cp110_icu.c optional mv_cp110_icu fdt arm/mv/mv_ap806_gicp.c optional mv_ap806_gicp fdt arm/mv/mv_ap806_clock.c optional SOC_MARVELL_8K fdt arm/mv/mv_cp110_clock.c optional SOC_MARVELL_8K fdt arm/mv/mv_thermal.c optional SOC_MARVELL_8K mv_thermal fdt arm/mv/armada38x/armada38x_rtc.c optional mv_rtc fdt arm/xilinx/uart_dev_cdnc.c optional uart soc_xilinx_zynq arm64/acpica/acpi_machdep.c optional acpi arm64/acpica/OsdEnvironment.c optional acpi arm64/acpica/acpi_wakeup.c optional acpi arm64/acpica/pci_cfgreg.c optional acpi pci arm64/arm64/autoconf.c standard arm64/arm64/bus_machdep.c standard arm64/arm64/bus_space_asm.S standard arm64/arm64/busdma_bounce.c standard arm64/arm64/busdma_machdep.c standard arm64/arm64/bzero.S standard arm64/arm64/clock.c standard arm64/arm64/copyinout.S standard arm64/arm64/copystr.c standard arm64/arm64/cpu_errata.c standard arm64/arm64/cpufunc_asm.S standard arm64/arm64/db_disasm.c optional ddb arm64/arm64/db_interface.c optional ddb arm64/arm64/db_trace.c optional ddb arm64/arm64/debug_monitor.c optional ddb arm64/arm64/disassem.c optional ddb arm64/arm64/dump_machdep.c standard arm64/arm64/efirt_machdep.c optional efirt arm64/arm64/elf32_machdep.c optional compat_freebsd32 arm64/arm64/elf_machdep.c standard arm64/arm64/exception.S standard arm64/arm64/freebsd32_machdep.c optional compat_freebsd32 arm64/arm64/gicv3_its.c optional intrng fdt arm64/arm64/gic_v3.c standard arm64/arm64/gic_v3_acpi.c optional acpi arm64/arm64/gic_v3_fdt.c optional fdt arm64/arm64/identcpu.c standard arm64/arm64/in_cksum.c optional inet | inet6 arm64/arm64/locore.S standard no-obj arm64/arm64/machdep.c standard arm64/arm64/mem.c standard arm64/arm64/memcpy.S standard arm64/arm64/memmove.S standard arm64/arm64/minidump_machdep.c standard arm64/arm64/mp_machdep.c optional smp arm64/arm64/nexus.c standard arm64/arm64/ofw_machdep.c optional fdt arm64/arm64/pmap.c standard arm64/arm64/stack_machdep.c optional ddb | stack arm64/arm64/support.S standard arm64/arm64/swtch.S standard arm64/arm64/sys_machdep.c standard arm64/arm64/trap.c standard arm64/arm64/uio_machdep.c standard arm64/arm64/uma_machdep.c standard arm64/arm64/undefined.c standard arm64/arm64/unwind.c optional ddb | kdtrace_hooks | stack arm64/arm64/vfp.c standard arm64/arm64/vm_machdep.c standard arm64/cavium/thunder_pcie_fdt.c optional soc_cavm_thunderx pci fdt arm64/cavium/thunder_pcie_pem.c optional soc_cavm_thunderx pci arm64/cavium/thunder_pcie_pem_fdt.c optional soc_cavm_thunderx pci fdt arm64/cavium/thunder_pcie_common.c optional soc_cavm_thunderx pci arm64/cloudabi32/cloudabi32_sysvec.c optional compat_cloudabi32 arm64/cloudabi64/cloudabi64_sysvec.c optional compat_cloudabi64 arm64/coresight/coresight.c standard arm64/coresight/coresight_if.m standard arm64/coresight/coresight-cmd.c standard arm64/coresight/coresight-cpu-debug.c standard arm64/coresight/coresight-dynamic-replicator.c standard arm64/coresight/coresight-etm4x.c standard arm64/coresight/coresight-funnel.c standard arm64/coresight/coresight-tmc.c standard arm64/qualcomm/qcom_gcc.c optional qcom_gcc fdt contrib/vchiq/interface/compat/vchi_bsd.c optional vchiq soc_brcm_bcm2837 \ compile-with "${NORMAL_C} -DUSE_VCHIQ_ARM -D__VCCOREVER__=0x04000000 -I$S/contrib/vchiq" contrib/vchiq/interface/vchiq_arm/vchiq_2835_arm.c optional vchiq soc_brcm_bcm2837 \ compile-with "${NORMAL_C} -Wno-unused -DUSE_VCHIQ_ARM -D__VCCOREVER__=0x04000000 -I$S/contrib/vchiq" contrib/vchiq/interface/vchiq_arm/vchiq_arm.c optional vchiq soc_brcm_bcm2837 \ compile-with "${NORMAL_C} -Wno-unused -DUSE_VCHIQ_ARM -D__VCCOREVER__=0x04000000 -I$S/contrib/vchiq" contrib/vchiq/interface/vchiq_arm/vchiq_connected.c optional vchiq soc_brcm_bcm2837 \ compile-with "${NORMAL_C} -DUSE_VCHIQ_ARM -D__VCCOREVER__=0x04000000 -I$S/contrib/vchiq" contrib/vchiq/interface/vchiq_arm/vchiq_core.c optional vchiq soc_brcm_bcm2837 \ compile-with "${NORMAL_C} -DUSE_VCHIQ_ARM -D__VCCOREVER__=0x04000000 -I$S/contrib/vchiq" contrib/vchiq/interface/vchiq_arm/vchiq_kern_lib.c optional vchiq soc_brcm_bcm2837 \ compile-with "${NORMAL_C} -DUSE_VCHIQ_ARM -D__VCCOREVER__=0x04000000 -I$S/contrib/vchiq" contrib/vchiq/interface/vchiq_arm/vchiq_kmod.c optional vchiq soc_brcm_bcm2837 \ compile-with "${NORMAL_C} -DUSE_VCHIQ_ARM -D__VCCOREVER__=0x04000000 -I$S/contrib/vchiq" contrib/vchiq/interface/vchiq_arm/vchiq_shim.c optional vchiq soc_brcm_bcm2837 \ compile-with "${NORMAL_C} -DUSE_VCHIQ_ARM -D__VCCOREVER__=0x04000000 -I$S/contrib/vchiq" contrib/vchiq/interface/vchiq_arm/vchiq_util.c optional vchiq soc_brcm_bcm2837 \ compile-with "${NORMAL_C} -DUSE_VCHIQ_ARM -D__VCCOREVER__=0x04000000 -I$S/contrib/vchiq" crypto/armv8/armv8_crypto.c optional armv8crypto armv8_crypto_wrap.o optional armv8crypto \ dependency "$S/crypto/armv8/armv8_crypto_wrap.c" \ compile-with "${CC} -c ${CFLAGS:C/^-O2$/-O3/:N-nostdinc:N-mgeneral-regs-only} -I$S/crypto/armv8/ ${WERROR} ${NO_WCAST_QUAL} ${PROF} -march=armv8-a+crypto ${.IMPSRC}" \ no-implicit-rule \ clean "armv8_crypto_wrap.o" crypto/blowfish/bf_enc.c optional crypto | ipsec | ipsec_support crypto/des/des_enc.c optional crypto | ipsec | ipsec_support | netsmb dev/acpica/acpi_bus_if.m optional acpi dev/acpica/acpi_if.m optional acpi dev/acpica/acpi_pci_link.c optional acpi pci dev/acpica/acpi_pcib.c optional acpi pci dev/ahci/ahci_generic.c optional ahci dev/axgbe/if_axgbe.c optional axgbe dev/axgbe/xgbe-desc.c optional axgbe dev/axgbe/xgbe-dev.c optional axgbe dev/axgbe/xgbe-drv.c optional axgbe dev/axgbe/xgbe-mdio.c optional axgbe dev/cpufreq/cpufreq_dt.c optional cpufreq fdt dev/iicbus/twsi/mv_twsi.c optional twsi fdt dev/iicbus/twsi/a10_twsi.c optional twsi fdt dev/iicbus/twsi/twsi.c optional twsi fdt dev/hwpmc/hwpmc_arm64.c optional hwpmc dev/hwpmc/hwpmc_arm64_md.c optional hwpmc dev/mbox/mbox_if.m optional soc_brcm_bcm2837 dev/mmc/host/dwmmc.c optional dwmmc fdt dev/mmc/host/dwmmc_hisi.c optional dwmmc fdt soc_hisi_hi6220 dev/mmc/host/dwmmc_rockchip.c optional dwmmc fdt soc_rockchip_rk3328 dev/neta/if_mvneta_fdt.c optional neta fdt dev/neta/if_mvneta.c optional neta mdio mii dev/ofw/ofw_cpu.c optional fdt dev/ofw/ofwpci.c optional fdt pci dev/pci/pci_host_generic.c optional pci dev/pci/pci_host_generic_acpi.c optional pci acpi dev/pci/pci_host_generic_fdt.c optional pci fdt dev/psci/psci.c standard dev/psci/psci_arm64.S standard dev/psci/smccc.c standard dev/sdhci/sdhci_xenon.c optional sdhci_xenon sdhci fdt dev/uart/uart_cpu_arm64.c optional uart dev/uart/uart_dev_mu.c optional uart uart_mu dev/uart/uart_dev_pl011.c optional uart pl011 dev/usb/controller/dwc_otg_hisi.c optional dwcotg fdt soc_hisi_hi6220 dev/usb/controller/ehci_mv.c optional ehci_mv fdt dev/usb/controller/generic_ehci.c optional ehci acpi dev/usb/controller/generic_ohci.c optional ohci fdt dev/usb/controller/generic_usb_if.m optional ohci fdt dev/usb/controller/usb_nop_xceiv.c optional fdt ext_resources dev/usb/controller/generic_xhci.c optional xhci fdt dev/vnic/mrml_bridge.c optional vnic fdt dev/vnic/nic_main.c optional vnic pci dev/vnic/nicvf_main.c optional vnic pci pci_iov dev/vnic/nicvf_queues.c optional vnic pci pci_iov dev/vnic/thunder_bgx_fdt.c optional vnic fdt dev/vnic/thunder_bgx.c optional vnic pci dev/vnic/thunder_mdio_fdt.c optional vnic fdt dev/vnic/thunder_mdio.c optional vnic dev/vnic/lmac_if.m optional inet | inet6 | vnic kern/kern_clocksource.c standard kern/msi_if.m optional intrng kern/pic_if.m optional intrng kern/subr_devmap.c standard kern/subr_intr.c optional intrng libkern/bcmp.c standard libkern/ffs.c standard libkern/ffsl.c standard libkern/ffsll.c standard libkern/fls.c standard libkern/flsl.c standard libkern/flsll.c standard libkern/memcmp.c standard libkern/memset.c standard libkern/arm64/crc32c_armv8.S standard cddl/contrib/opensolaris/common/atomic/aarch64/opensolaris_atomic.S optional zfs | dtrace compile-with "${CDDL_C}" cddl/dev/dtrace/aarch64/dtrace_asm.S optional dtrace compile-with "${DTRACE_S}" cddl/dev/dtrace/aarch64/dtrace_subr.c optional dtrace compile-with "${DTRACE_C}" cddl/dev/fbt/aarch64/fbt_isa.c optional dtrace_fbt | dtraceall compile-with "${FBT_C}" # RockChip Drivers arm64/rockchip/rk_i2c.c optional fdt rk_i2c soc_rockchip_rk3328 | fdt rk_i2c soc_rockchip_rk3399 arm64/rockchip/rk805.c optional fdt rk805 soc_rockchip_rk3328 | fdt rk805 soc_rockchip_rk3399 arm64/rockchip/rk_grf.c optional fdt soc_rockchip_rk3328 | fdt soc_rockchip_rk3399 arm64/rockchip/rk_pinctrl.c optional fdt rk_pinctrl soc_rockchip_rk3328 | fdt rk_pinctrl soc_rockchip_rk3399 arm64/rockchip/rk_gpio.c optional fdt rk_gpio soc_rockchip_rk3328 | fdt rk_gpio soc_rockchip_rk3399 arm64/rockchip/if_dwc_rk.c optional fdt dwc_rk soc_rockchip_rk3328 | fdt dwc_rk soc_rockchip_rk3399 dev/dwc/if_dwc.c optional fdt dwc_rk soc_rockchip_rk3328 | fdt dwc_rk soc_rockchip_rk3399 dev/dwc/if_dwc_if.m optional fdt dwc_rk soc_rockchip_rk3328 | fdt dwc_rk soc_rockchip_rk3399 # RockChip Clock support arm64/rockchip/clk/rk_cru.c optional fdt soc_rockchip_rk3328 | fdt soc_rockchip_rk3399 arm64/rockchip/clk/rk_clk_armclk.c optional fdt soc_rockchip_rk3328 | fdt soc_rockchip_rk3399 arm64/rockchip/clk/rk_clk_composite.c optional fdt soc_rockchip_rk3328 | fdt soc_rockchip_rk3399 arm64/rockchip/clk/rk_clk_gate.c optional fdt soc_rockchip_rk3328 | fdt soc_rockchip_rk3399 arm64/rockchip/clk/rk_clk_mux.c optional fdt soc_rockchip_rk3328 | fdt soc_rockchip_rk3399 arm64/rockchip/clk/rk_clk_pll.c optional fdt soc_rockchip_rk3328 | fdt soc_rockchip_rk3399 arm64/rockchip/clk/rk3328_cru.c optional fdt soc_rockchip_rk3328 arm64/rockchip/clk/rk3399_cru.c optional fdt soc_rockchip_rk3399 arm64/rockchip/clk/rk3399_pmucru.c optional fdt soc_rockchip_rk3399 Index: stable/12/sys/dev/sdhci/sdhci_xenon.c =================================================================== --- stable/12/sys/dev/sdhci/sdhci_xenon.c (revision 351138) +++ stable/12/sys/dev/sdhci/sdhci_xenon.c (revision 351139) @@ -1,556 +1,639 @@ /*- * SPDX-License-Identifier: BSD-2-Clause-FreeBSD * * Copyright (c) 2018 Rubicon Communications, LLC (Netgate) * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* * Marvell Xenon SDHCI controller driver. */ #include __FBSDID("$FreeBSD$"); #include #include #include #include #include #include #include #include #include #include #include #include #include +#include #include #include #include #include #include #include #include +#include #include #include "mmcbr_if.h" #include "sdhci_if.h" #include "opt_mmccam.h" #include "opt_soc.h" #define MAX_SLOTS 6 static struct ofw_compat_data compat_data[] = { { "marvell,armada-3700-sdhci", 1 }, #ifdef SOC_MARVELL_8K { "marvell,armada-cp110-sdhci", 1 }, { "marvell,armada-ap806-sdhci", 1 }, #endif { NULL, 0 } }; struct sdhci_xenon_softc { device_t dev; /* Controller device */ int slot_id; /* Controller ID */ phandle_t node; /* FDT node */ uint32_t quirks; /* Chip specific quirks */ uint32_t caps; /* If we override SDHCI_CAPABILITIES */ uint32_t max_clk; /* Max possible freq */ struct resource *irq_res; /* IRQ resource */ void *intrhand; /* Interrupt handle */ + struct sdhci_fdt_gpio *gpio; /* GPIO pins for CD detection. */ struct sdhci_slot *slot; /* SDHCI internal data */ struct resource *mem_res; /* Memory resource */ + regulator_t reg_vqmmc; /* vqmmc-supply regulator */ uint8_t znr; /* PHY ZNR */ uint8_t zpr; /* PHY ZPR */ bool no_18v; /* No 1.8V support */ bool slow_mode; /* PHY slow mode */ bool wp_inverted; /* WP pin is inverted */ }; static uint8_t sdhci_xenon_read_1(device_t dev, struct sdhci_slot *slot __unused, bus_size_t off) { struct sdhci_xenon_softc *sc = device_get_softc(dev); return (bus_read_1(sc->mem_res, off)); } static void sdhci_xenon_write_1(device_t dev, struct sdhci_slot *slot __unused, bus_size_t off, uint8_t val) { struct sdhci_xenon_softc *sc = device_get_softc(dev); bus_write_1(sc->mem_res, off, val); } static uint16_t sdhci_xenon_read_2(device_t dev, struct sdhci_slot *slot __unused, bus_size_t off) { struct sdhci_xenon_softc *sc = device_get_softc(dev); return (bus_read_2(sc->mem_res, off)); } static void sdhci_xenon_write_2(device_t dev, struct sdhci_slot *slot __unused, bus_size_t off, uint16_t val) { struct sdhci_xenon_softc *sc = device_get_softc(dev); bus_write_2(sc->mem_res, off, val); } static uint32_t sdhci_xenon_read_4(device_t dev, struct sdhci_slot *slot __unused, bus_size_t off) { struct sdhci_xenon_softc *sc = device_get_softc(dev); uint32_t val32; val32 = bus_read_4(sc->mem_res, off); if (off == SDHCI_CAPABILITIES && sc->no_18v) val32 &= ~SDHCI_CAN_VDD_180; return (val32); } static void sdhci_xenon_write_4(device_t dev, struct sdhci_slot *slot __unused, bus_size_t off, uint32_t val) { struct sdhci_xenon_softc *sc = device_get_softc(dev); bus_write_4(sc->mem_res, off, val); } static void sdhci_xenon_read_multi_4(device_t dev, struct sdhci_slot *slot __unused, bus_size_t off, uint32_t *data, bus_size_t count) { struct sdhci_xenon_softc *sc = device_get_softc(dev); bus_read_multi_4(sc->mem_res, off, data, count); } static void sdhci_xenon_write_multi_4(device_t dev, struct sdhci_slot *slot __unused, bus_size_t off, uint32_t *data, bus_size_t count) { struct sdhci_xenon_softc *sc = device_get_softc(dev); bus_write_multi_4(sc->mem_res, off, data, count); } static void sdhci_xenon_intr(void *arg) { struct sdhci_xenon_softc *sc = (struct sdhci_xenon_softc *)arg; sdhci_generic_intr(sc->slot); } static int sdhci_xenon_get_ro(device_t bus, device_t dev) { struct sdhci_xenon_softc *sc = device_get_softc(bus); return (sdhci_generic_get_ro(bus, dev) ^ sc->wp_inverted); } +static bool +sdhci_xenon_get_card_present(device_t dev, struct sdhci_slot *slot) +{ + struct sdhci_xenon_softc *sc = device_get_softc(dev); + + return (sdhci_fdt_gpio_get_present(sc->gpio)); +} + static int sdhci_xenon_phy_init(device_t brdev, struct mmc_ios *ios) { int i; struct sdhci_xenon_softc *sc; uint32_t reg; sc = device_get_softc(brdev); reg = bus_read_4(sc->mem_res, XENON_EMMC_PHY_TIMING_ADJUST); reg |= XENON_SAMPL_INV_QSP_PHASE_SELECT; switch (ios->timing) { case bus_timing_normal: case bus_timing_hs: case bus_timing_uhs_sdr12: case bus_timing_uhs_sdr25: case bus_timing_uhs_sdr50: reg |= XENON_TIMING_ADJUST_SLOW_MODE; break; default: reg &= ~XENON_TIMING_ADJUST_SLOW_MODE; } if (sc->slow_mode) reg |= XENON_TIMING_ADJUST_SLOW_MODE; bus_write_4(sc->mem_res, XENON_EMMC_PHY_TIMING_ADJUST, reg); reg = bus_read_4(sc->mem_res, XENON_EMMC_PHY_TIMING_ADJUST); reg |= XENON_PHY_INITIALIZATION; bus_write_4(sc->mem_res, XENON_EMMC_PHY_TIMING_ADJUST, reg); /* Wait for the eMMC PHY init. */ for (i = 100; i > 0; i--) { DELAY(100); reg = bus_read_4(sc->mem_res, XENON_EMMC_PHY_TIMING_ADJUST); if ((reg & XENON_PHY_INITIALIZATION) == 0) break; } if (i == 0) { device_printf(brdev, "eMMC PHY failed to initialize\n"); return (ETIMEDOUT); } return (0); } static int sdhci_xenon_phy_set(device_t brdev, struct mmc_ios *ios) { struct sdhci_xenon_softc *sc; uint32_t reg; sc = device_get_softc(brdev); /* Setup pad, set bit[28] and bits[26:24] */ reg = bus_read_4(sc->mem_res, XENON_EMMC_PHY_PAD_CONTROL); reg |= (XENON_FC_DQ_RECEN | XENON_FC_CMD_RECEN | XENON_FC_QSP_RECEN | XENON_OEN_QSN); /* All FC_XX_RECEIVCE should be set as CMOS Type */ reg |= XENON_FC_ALL_CMOS_RECEIVER; bus_write_4(sc->mem_res, XENON_EMMC_PHY_PAD_CONTROL, reg); /* Set CMD and DQ Pull Up */ reg = bus_read_4(sc->mem_res, XENON_EMMC_PHY_PAD_CONTROL1); reg |= (XENON_EMMC_FC_CMD_PU | XENON_EMMC_FC_DQ_PU); reg &= ~(XENON_EMMC_FC_CMD_PD | XENON_EMMC_FC_DQ_PD); bus_write_4(sc->mem_res, XENON_EMMC_PHY_PAD_CONTROL1, reg); if (ios->timing == bus_timing_normal) return (sdhci_xenon_phy_init(brdev, ios)); /* Clear SDIO mode, no SDIO support for now. */ reg = bus_read_4(sc->mem_res, XENON_EMMC_PHY_TIMING_ADJUST); reg &= ~XENON_TIMING_ADJUST_SDIO_MODE; bus_write_4(sc->mem_res, XENON_EMMC_PHY_TIMING_ADJUST, reg); /* * Set preferred ZNR and ZPR value. * The ZNR and ZPR value vary between different boards. * Define them both in the DTS for the board! */ reg = bus_read_4(sc->mem_res, XENON_EMMC_PHY_PAD_CONTROL2); reg &= ~((XENON_ZNR_MASK << XENON_ZNR_SHIFT) | XENON_ZPR_MASK); reg |= ((sc->znr << XENON_ZNR_SHIFT) | sc->zpr); bus_write_4(sc->mem_res, XENON_EMMC_PHY_PAD_CONTROL2, reg); /* Disable the SD clock to set EMMC_PHY_FUNC_CONTROL. */ reg = bus_read_4(sc->mem_res, SDHCI_CLOCK_CONTROL); reg &= ~SDHCI_CLOCK_CARD_EN; bus_write_4(sc->mem_res, SDHCI_CLOCK_CONTROL, reg); reg = bus_read_4(sc->mem_res, XENON_EMMC_PHY_FUNC_CONTROL); switch (ios->timing) { case bus_timing_mmc_hs400: reg |= (XENON_DQ_DDR_MODE_MASK << XENON_DQ_DDR_MODE_SHIFT) | XENON_CMD_DDR_MODE; reg &= ~XENON_DQ_ASYNC_MODE; break; case bus_timing_uhs_ddr50: case bus_timing_mmc_ddr52: reg |= (XENON_DQ_DDR_MODE_MASK << XENON_DQ_DDR_MODE_SHIFT) | XENON_CMD_DDR_MODE | XENON_DQ_ASYNC_MODE; break; default: reg &= ~((XENON_DQ_DDR_MODE_MASK << XENON_DQ_DDR_MODE_SHIFT) | XENON_CMD_DDR_MODE); reg |= XENON_DQ_ASYNC_MODE; } bus_write_4(sc->mem_res, XENON_EMMC_PHY_FUNC_CONTROL, reg); /* Enable SD clock. */ reg = bus_read_4(sc->mem_res, SDHCI_CLOCK_CONTROL); reg |= SDHCI_CLOCK_CARD_EN; bus_write_4(sc->mem_res, SDHCI_CLOCK_CONTROL, reg); if (ios->timing == bus_timing_mmc_hs400) bus_write_4(sc->mem_res, XENON_EMMC_PHY_LOGIC_TIMING_ADJUST, XENON_LOGIC_TIMING_VALUE); else { /* Disable both SDHC Data Strobe and Enhanced Strobe. */ reg = bus_read_4(sc->mem_res, XENON_SLOT_EMMC_CTRL); reg &= ~(XENON_ENABLE_DATA_STROBE | XENON_ENABLE_RESP_STROBE); bus_write_4(sc->mem_res, XENON_SLOT_EMMC_CTRL, reg); /* Clear Strobe line Pull down or Pull up. */ reg = bus_read_4(sc->mem_res, XENON_EMMC_PHY_PAD_CONTROL1); reg &= ~(XENON_EMMC_FC_QSP_PD | XENON_EMMC_FC_QSP_PU); bus_write_4(sc->mem_res, XENON_EMMC_PHY_PAD_CONTROL1, reg); } return (sdhci_xenon_phy_init(brdev, ios)); } static int sdhci_xenon_update_ios(device_t brdev, device_t reqdev) { int err; struct sdhci_xenon_softc *sc; struct mmc_ios *ios; struct sdhci_slot *slot; uint32_t reg; err = sdhci_generic_update_ios(brdev, reqdev); if (err != 0) return (err); sc = device_get_softc(brdev); slot = device_get_ivars(reqdev); ios = &slot->host.ios; + switch (ios->power_mode) { + case power_on: + break; + case power_off: + if (bootverbose) + device_printf(sc->dev, "Powering down sd/mmc\n"); + + if (sc->reg_vqmmc) + regulator_disable(sc->reg_vqmmc); + break; + case power_up: + if (bootverbose) + device_printf(sc->dev, "Powering up sd/mmc\n"); + + if (sc->reg_vqmmc) + regulator_enable(sc->reg_vqmmc); + break; + }; + /* Update the PHY settings. */ if (ios->clock != 0) sdhci_xenon_phy_set(brdev, ios); if (ios->clock > SD_MMC_CARD_ID_FREQUENCY) { /* Enable SDCLK_IDLEOFF. */ reg = bus_read_4(sc->mem_res, XENON_SYS_OP_CTRL); reg |= 1 << (XENON_SDCLK_IDLEOFF_ENABLE_SHIFT + sc->slot_id); bus_write_4(sc->mem_res, XENON_SYS_OP_CTRL, reg); } return (0); } static int +sdhci_xenon_switch_vccq(device_t brdev, device_t reqdev) +{ + struct sdhci_xenon_softc *sc; + struct sdhci_slot *slot; + int uvolt, err; + + sc = device_get_softc(brdev); + + if (sc->reg_vqmmc == NULL) + return EOPNOTSUPP; + + slot = device_get_ivars(reqdev); + switch (slot->host.ios.vccq) { + case vccq_180: + uvolt = 1800000; + break; + case vccq_330: + uvolt = 3300000; + break; + default: + return EINVAL; + } + + err = regulator_set_voltage(sc->reg_vqmmc, uvolt, uvolt); + if (err != 0) { + device_printf(sc->dev, + "Cannot set vqmmc to %d<->%d\n", + uvolt, + uvolt); + return (err); + } + + return (0); +} + +static int sdhci_xenon_probe(device_t dev) { struct sdhci_xenon_softc *sc = device_get_softc(dev); pcell_t cid; sc->quirks = 0; sc->slot_id = 0; sc->max_clk = XENON_MMC_MAX_CLK; if (!ofw_bus_status_okay(dev)) return (ENXIO); if (ofw_bus_search_compatible(dev, compat_data)->ocd_data == 0) return (ENXIO); sc->node = ofw_bus_get_node(dev); device_set_desc(dev, "Armada Xenon SDHCI controller"); /* Allow dts to patch quirks, slots, and max-frequency. */ if ((OF_getencprop(sc->node, "quirks", &cid, sizeof(cid))) > 0) sc->quirks = cid; if ((OF_getencprop(sc->node, "max-frequency", &cid, sizeof(cid))) > 0) sc->max_clk = cid; if (OF_hasprop(sc->node, "no-1-8-v")) sc->no_18v = true; if (OF_hasprop(sc->node, "wp-inverted")) sc->wp_inverted = true; if (OF_hasprop(sc->node, "marvell,xenon-phy-slow-mode")) sc->slow_mode = true; sc->znr = XENON_ZNR_DEF_VALUE; if ((OF_getencprop(sc->node, "marvell,xenon-phy-znr", &cid, sizeof(cid))) > 0) sc->znr = cid & XENON_ZNR_MASK; sc->zpr = XENON_ZPR_DEF_VALUE; if ((OF_getencprop(sc->node, "marvell,xenon-phy-zpr", &cid, sizeof(cid))) > 0) sc->zpr = cid & XENON_ZPR_MASK; + if (regulator_get_by_ofw_property(dev, 0, "vqmmc-supply", + &sc->reg_vqmmc) == 0 && bootverbose) { + if (bootverbose) + device_printf(dev, "vqmmc-supply regulator found\n"); + } return (0); } static int sdhci_xenon_attach(device_t dev) { struct sdhci_xenon_softc *sc = device_get_softc(dev); struct sdhci_slot *slot; int err, rid; uint32_t reg; sc->dev = dev; /* Allocate IRQ. */ rid = 0; sc->irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, RF_ACTIVE); if (sc->irq_res == NULL) { device_printf(dev, "Can't allocate IRQ\n"); return (ENOMEM); } /* Allocate memory. */ rid = 0; sc->mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, RF_ACTIVE); if (sc->mem_res == NULL) { bus_release_resource(dev, SYS_RES_IRQ, rman_get_rid(sc->irq_res), sc->irq_res); device_printf(dev, "Can't allocate memory for slot\n"); return (ENOMEM); } slot = malloc(sizeof(*slot), M_DEVBUF, M_ZERO | M_WAITOK); /* Check if the device is flagged as non-removable. */ if (OF_hasprop(sc->node, "non-removable")) { slot->opt |= SDHCI_NON_REMOVABLE; if (bootverbose) device_printf(dev, "Non-removable media\n"); } slot->quirks = sc->quirks; slot->caps = sc->caps; slot->max_clk = sc->max_clk; sc->slot = slot; + /* + * Set up any gpio pin handling described in the FDT data. This cannot + * fail; see comments in sdhci_fdt_gpio.h for details. + */ + sc->gpio = sdhci_fdt_gpio_setup(dev, slot); + if (sdhci_init_slot(dev, sc->slot, 0)) goto fail; /* Activate the interrupt */ err = bus_setup_intr(dev, sc->irq_res, INTR_TYPE_MISC | INTR_MPSAFE, NULL, sdhci_xenon_intr, sc, &sc->intrhand); if (err) { device_printf(dev, "Cannot setup IRQ\n"); goto fail; } /* Disable Auto Clock Gating. */ reg = bus_read_4(sc->mem_res, XENON_SYS_OP_CTRL); reg |= XENON_AUTO_CLKGATE_DISABLE; bus_write_4(sc->mem_res, XENON_SYS_OP_CTRL, reg); /* Enable this SD controller. */ reg |= (1 << sc->slot_id); bus_write_4(sc->mem_res, XENON_SYS_OP_CTRL, reg); /* Enable Parallel Transfer. */ reg = bus_read_4(sc->mem_res, XENON_SYS_EXT_OP_CTRL); reg |= (1 << sc->slot_id); bus_write_4(sc->mem_res, XENON_SYS_EXT_OP_CTRL, reg); /* Enable Auto Clock Gating. */ reg &= ~XENON_AUTO_CLKGATE_DISABLE; bus_write_4(sc->mem_res, XENON_SYS_OP_CTRL, reg); /* Disable SDCLK_IDLEOFF before the card initialization. */ reg = bus_read_4(sc->mem_res, XENON_SYS_OP_CTRL); reg &= ~(1 << (XENON_SDCLK_IDLEOFF_ENABLE_SHIFT + sc->slot_id)); bus_write_4(sc->mem_res, XENON_SYS_OP_CTRL, reg); /* Mask command conflict errors. */ reg = bus_read_4(sc->mem_res, XENON_SYS_EXT_OP_CTRL); reg |= XENON_MASK_CMD_CONFLICT_ERR; bus_write_4(sc->mem_res, XENON_SYS_EXT_OP_CTRL, reg); /* Process cards detection. */ sdhci_start_slot(sc->slot); return (0); fail: bus_release_resource(dev, SYS_RES_IRQ, rman_get_rid(sc->irq_res), sc->irq_res); bus_release_resource(dev, SYS_RES_MEMORY, rman_get_rid(sc->mem_res), sc->mem_res); free(sc->slot, M_DEVBUF); sc->slot = NULL; return (ENXIO); } static int sdhci_xenon_detach(device_t dev) { struct sdhci_xenon_softc *sc = device_get_softc(dev); + if (sc->gpio != NULL) + sdhci_fdt_gpio_teardown(sc->gpio); + bus_generic_detach(dev); bus_teardown_intr(dev, sc->irq_res, sc->intrhand); bus_release_resource(dev, SYS_RES_IRQ, rman_get_rid(sc->irq_res), sc->irq_res); sdhci_cleanup_slot(sc->slot); bus_release_resource(dev, SYS_RES_MEMORY, rman_get_rid(sc->mem_res), sc->mem_res); free(sc->slot, M_DEVBUF); sc->slot = NULL; return (0); } static device_method_t sdhci_xenon_methods[] = { /* device_if */ DEVMETHOD(device_probe, sdhci_xenon_probe), DEVMETHOD(device_attach, sdhci_xenon_attach), DEVMETHOD(device_detach, sdhci_xenon_detach), /* Bus interface */ DEVMETHOD(bus_read_ivar, sdhci_generic_read_ivar), DEVMETHOD(bus_write_ivar, sdhci_generic_write_ivar), /* mmcbr_if */ DEVMETHOD(mmcbr_update_ios, sdhci_xenon_update_ios), DEVMETHOD(mmcbr_request, sdhci_generic_request), DEVMETHOD(mmcbr_get_ro, sdhci_xenon_get_ro), DEVMETHOD(mmcbr_acquire_host, sdhci_generic_acquire_host), DEVMETHOD(mmcbr_release_host, sdhci_generic_release_host), + DEVMETHOD(mmcbr_switch_vccq, sdhci_xenon_switch_vccq), /* SDHCI registers accessors */ DEVMETHOD(sdhci_read_1, sdhci_xenon_read_1), DEVMETHOD(sdhci_read_2, sdhci_xenon_read_2), DEVMETHOD(sdhci_read_4, sdhci_xenon_read_4), DEVMETHOD(sdhci_read_multi_4, sdhci_xenon_read_multi_4), DEVMETHOD(sdhci_write_1, sdhci_xenon_write_1), DEVMETHOD(sdhci_write_2, sdhci_xenon_write_2), DEVMETHOD(sdhci_write_4, sdhci_xenon_write_4), DEVMETHOD(sdhci_write_multi_4, sdhci_xenon_write_multi_4), + DEVMETHOD(sdhci_get_card_present, sdhci_xenon_get_card_present), DEVMETHOD_END }; static driver_t sdhci_xenon_driver = { "sdhci_xenon", sdhci_xenon_methods, sizeof(struct sdhci_xenon_softc), }; static devclass_t sdhci_xenon_devclass; DRIVER_MODULE(sdhci_xenon, simplebus, sdhci_xenon_driver, sdhci_xenon_devclass, NULL, NULL); SDHCI_DEPEND(sdhci_xenon); #ifndef MMCCAM MMC_DECLARE_BRIDGE(sdhci_xenon); #endif Index: stable/12 =================================================================== --- stable/12 (revision 351138) +++ stable/12 (revision 351139) Property changes on: stable/12 ___________________________________________________________________ Modified: svn:mergeinfo ## -0,0 +0,1 ## Merged /head:r348880,348882