Index: head/sys/arm/allwinner/a10_sramc.c =================================================================== --- head/sys/arm/allwinner/a10_sramc.c (revision 350841) +++ head/sys/arm/allwinner/a10_sramc.c (revision 350842) @@ -1,153 +1,153 @@ /*- * SPDX-License-Identifier: BSD-2-Clause-FreeBSD * * Copyright (c) 2013 Ganbold Tsagaankhuu * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. * * $FreeBSD$ */ #include __FBSDID("$FreeBSD$"); #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include "a10_sramc.h" #define SRAM_CTL1_CFG 0x04 #define CTL1_CFG_SRAMD_MAP_USB0 (1 << 0) struct a10_sramc_softc { struct resource *res; bus_space_tag_t bst; bus_space_handle_t bsh; }; static struct a10_sramc_softc *a10_sramc_sc; #define sramc_read_4(sc, reg) \ bus_space_read_4((sc)->bst, (sc)->bsh, (reg)) #define sramc_write_4(sc, reg, val) \ bus_space_write_4((sc)->bst, (sc)->bsh, (reg), (val)) static int a10_sramc_probe(device_t dev) { if (ofw_bus_is_compatible(dev, "allwinner,sun4i-a10-sram-controller")) { device_set_desc(dev, "Allwinner sramc module"); return (BUS_PROBE_DEFAULT); } return (ENXIO); } static int a10_sramc_attach(device_t dev) { struct a10_sramc_softc *sc = device_get_softc(dev); int rid = 0; sc->res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, RF_ACTIVE); if (!sc->res) { device_printf(dev, "could not allocate resource\n"); return (ENXIO); } sc->bst = rman_get_bustag(sc->res); sc->bsh = rman_get_bushandle(sc->res); a10_sramc_sc = sc; return (0); } static device_method_t a10_sramc_methods[] = { DEVMETHOD(device_probe, a10_sramc_probe), DEVMETHOD(device_attach, a10_sramc_attach), { 0, 0 } }; static driver_t a10_sramc_driver = { "a10_sramc", a10_sramc_methods, sizeof(struct a10_sramc_softc), }; static devclass_t a10_sramc_devclass; EARLY_DRIVER_MODULE(a10_sramc, simplebus, a10_sramc_driver, a10_sramc_devclass, - 0, 0, BUS_PASS_RESOURCE + BUS_PASS_ORDER_EARLY); + 0, 0, BUS_PASS_SUPPORTDEV + BUS_PASS_ORDER_FIRST); int a10_map_to_emac(void) { struct a10_sramc_softc *sc = a10_sramc_sc; uint32_t reg_value; if (sc == NULL) return (ENXIO); /* Map SRAM to EMAC, set bit 2 and 4. */ reg_value = sramc_read_4(sc, SRAM_CTL1_CFG); reg_value |= 0x5 << 2; sramc_write_4(sc, SRAM_CTL1_CFG, reg_value); return (0); } int a10_map_to_otg(void) { struct a10_sramc_softc *sc = a10_sramc_sc; uint32_t reg_value; if (sc == NULL) return (ENXIO); /* Map SRAM to OTG */ reg_value = sramc_read_4(sc, SRAM_CTL1_CFG); reg_value |= CTL1_CFG_SRAMD_MAP_USB0; sramc_write_4(sc, SRAM_CTL1_CFG, reg_value); return (0); } Index: head/sys/arm/allwinner/a20/a20_cpu_cfg.c =================================================================== --- head/sys/arm/allwinner/a20/a20_cpu_cfg.c (revision 350841) +++ head/sys/arm/allwinner/a20/a20_cpu_cfg.c (revision 350842) @@ -1,139 +1,139 @@ /*- * SPDX-License-Identifier: BSD-2-Clause-FreeBSD * * Copyright (c) 2013 Ganbold Tsagaankhuu * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. */ /* CPU configuration module for Allwinner A20 */ #include __FBSDID("$FreeBSD$"); #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include "a20_cpu_cfg.h" struct a20_cpu_cfg_softc { struct resource *res; bus_space_tag_t bst; bus_space_handle_t bsh; }; static struct a20_cpu_cfg_softc *a20_cpu_cfg_sc = NULL; #define cpu_cfg_read_4(sc, reg) \ bus_space_read_4((sc)->bst, (sc)->bsh, (reg)) #define cpu_cfg_write_4(sc, reg, val) \ bus_space_write_4((sc)->bst, (sc)->bsh, (reg), (val)) static int a20_cpu_cfg_probe(device_t dev) { if (!ofw_bus_status_okay(dev)) return (ENXIO); if (ofw_bus_is_compatible(dev, "allwinner,sun7i-cpu-cfg")) { device_set_desc(dev, "A20 CPU Configuration Module"); return(BUS_PROBE_DEFAULT); } return (ENXIO); } static int a20_cpu_cfg_attach(device_t dev) { struct a20_cpu_cfg_softc *sc = device_get_softc(dev); int rid = 0; if (a20_cpu_cfg_sc) return (ENXIO); sc->res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, RF_ACTIVE); if (!sc->res) { device_printf(dev, "could not allocate resource\n"); return (ENXIO); } sc->bst = rman_get_bustag(sc->res); sc->bsh = rman_get_bushandle(sc->res); a20_cpu_cfg_sc = sc; return (0); } static device_method_t a20_cpu_cfg_methods[] = { DEVMETHOD(device_probe, a20_cpu_cfg_probe), DEVMETHOD(device_attach, a20_cpu_cfg_attach), { 0, 0 } }; static driver_t a20_cpu_cfg_driver = { "a20_cpu_cfg", a20_cpu_cfg_methods, sizeof(struct a20_cpu_cfg_softc), }; static devclass_t a20_cpu_cfg_devclass; EARLY_DRIVER_MODULE(a20_cpu_cfg, simplebus, a20_cpu_cfg_driver, a20_cpu_cfg_devclass, 0, 0, - BUS_PASS_RESOURCE + BUS_PASS_ORDER_MIDDLE); + BUS_PASS_CPU + BUS_PASS_ORDER_FIRST); uint64_t a20_read_counter64(void) { uint32_t lo, hi; /* Latch counter, wait for it to be ready to read. */ cpu_cfg_write_4(a20_cpu_cfg_sc, OSC24M_CNT64_CTRL_REG, CNT64_RL_EN); while (cpu_cfg_read_4(a20_cpu_cfg_sc, OSC24M_CNT64_CTRL_REG) & CNT64_RL_EN) continue; hi = cpu_cfg_read_4(a20_cpu_cfg_sc, OSC24M_CNT64_HIGH_REG); lo = cpu_cfg_read_4(a20_cpu_cfg_sc, OSC24M_CNT64_LOW_REG); return (((uint64_t)hi << 32) | lo); } Index: head/sys/arm/allwinner/aw_ccu.c =================================================================== --- head/sys/arm/allwinner/aw_ccu.c (revision 350841) +++ head/sys/arm/allwinner/aw_ccu.c (revision 350842) @@ -1,255 +1,255 @@ /*- * Copyright (c) 2016 Jared McNeill * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. * * $FreeBSD$ */ /* * Allwinner oscillator clock */ #include __FBSDID("$FreeBSD$"); #include #include #include #include #include #include #include #include #include #include #include #include #include #include "clkdev_if.h" #define CCU_BASE 0x01c20000 #define CCU_SIZE 0x400 struct aw_ccu_softc { struct simplebus_softc sc; bus_space_tag_t bst; bus_space_handle_t bsh; struct mtx mtx; int flags; }; static struct ofw_compat_data compat_data[] = { { "allwinner,sun7i-a20", 1 }, { "allwinner,sun6i-a31", 1 }, { "allwinner,sun6i-a31s", 1 }, { NULL, 0 } }; static int aw_ccu_check_addr(struct aw_ccu_softc *sc, bus_addr_t addr, bus_space_handle_t *pbsh, bus_size_t *poff) { if (addr >= CCU_BASE && addr < (CCU_BASE + CCU_SIZE)) { *poff = addr - CCU_BASE; *pbsh = sc->bsh; return (0); } return (EINVAL); } static int aw_ccu_write_4(device_t dev, bus_addr_t addr, uint32_t val) { struct aw_ccu_softc *sc; bus_space_handle_t bsh; bus_size_t reg; sc = device_get_softc(dev); if (aw_ccu_check_addr(sc, addr, &bsh, ®) != 0) return (EINVAL); mtx_assert(&sc->mtx, MA_OWNED); bus_space_write_4(sc->bst, bsh, reg, val); return (0); } static int aw_ccu_read_4(device_t dev, bus_addr_t addr, uint32_t *val) { struct aw_ccu_softc *sc; bus_space_handle_t bsh; bus_size_t reg; sc = device_get_softc(dev); if (aw_ccu_check_addr(sc, addr, &bsh, ®) != 0) return (EINVAL); mtx_assert(&sc->mtx, MA_OWNED); *val = bus_space_read_4(sc->bst, bsh, reg); return (0); } static int aw_ccu_modify_4(device_t dev, bus_addr_t addr, uint32_t clr, uint32_t set) { struct aw_ccu_softc *sc; bus_space_handle_t bsh; bus_size_t reg; uint32_t val; sc = device_get_softc(dev); if (aw_ccu_check_addr(sc, addr, &bsh, ®) != 0) return (EINVAL); mtx_assert(&sc->mtx, MA_OWNED); val = bus_space_read_4(sc->bst, bsh, reg); val &= ~clr; val |= set; bus_space_write_4(sc->bst, bsh, reg, val); return (0); } static void aw_ccu_device_lock(device_t dev) { struct aw_ccu_softc *sc; sc = device_get_softc(dev); mtx_lock(&sc->mtx); } static void aw_ccu_device_unlock(device_t dev) { struct aw_ccu_softc *sc; sc = device_get_softc(dev); mtx_unlock(&sc->mtx); } static const struct ofw_compat_data * aw_ccu_search_compatible(void) { const struct ofw_compat_data *compat; phandle_t root; root = OF_finddevice("/"); for (compat = compat_data; compat->ocd_str != NULL; compat++) if (ofw_bus_node_is_compatible(root, compat->ocd_str)) break; return (compat); } static int aw_ccu_probe(device_t dev) { const char *name; name = ofw_bus_get_name(dev); if (name == NULL || strcmp(name, "clocks") != 0) return (ENXIO); if (aw_ccu_search_compatible()->ocd_data == 0) return (ENXIO); device_set_desc(dev, "Allwinner Clock Control Unit"); return (BUS_PROBE_SPECIFIC); } static int aw_ccu_attach(device_t dev) { struct aw_ccu_softc *sc; phandle_t node, child; device_t cdev; int error; sc = device_get_softc(dev); node = ofw_bus_get_node(dev); simplebus_init(dev, node); sc->flags = aw_ccu_search_compatible()->ocd_data; /* * Map registers. The DT doesn't have a "reg" property * for the /clocks node and child nodes have conflicting "reg" * properties. */ sc->bst = bus_get_bus_tag(dev); error = bus_space_map(sc->bst, CCU_BASE, CCU_SIZE, 0, &sc->bsh); if (error != 0) { device_printf(dev, "couldn't map CCU: %d\n", error); return (error); } mtx_init(&sc->mtx, device_get_nameunit(dev), NULL, MTX_DEF); /* Attach child devices */ for (child = OF_child(node); child > 0; child = OF_peer(child)) { cdev = simplebus_add_device(dev, child, 0, NULL, -1, NULL); if (cdev != NULL) device_probe_and_attach(cdev); } return (bus_generic_attach(dev)); } static device_method_t aw_ccu_methods[] = { /* Device interface */ DEVMETHOD(device_probe, aw_ccu_probe), DEVMETHOD(device_attach, aw_ccu_attach), /* clkdev interface */ DEVMETHOD(clkdev_write_4, aw_ccu_write_4), DEVMETHOD(clkdev_read_4, aw_ccu_read_4), DEVMETHOD(clkdev_modify_4, aw_ccu_modify_4), DEVMETHOD(clkdev_device_lock, aw_ccu_device_lock), DEVMETHOD(clkdev_device_unlock, aw_ccu_device_unlock), DEVMETHOD_END }; DEFINE_CLASS_1(aw_ccu, aw_ccu_driver, aw_ccu_methods, sizeof(struct aw_ccu_softc), simplebus_driver); static devclass_t aw_ccu_devclass; EARLY_DRIVER_MODULE(aw_ccu, simplebus, aw_ccu_driver, aw_ccu_devclass, - 0, 0, BUS_PASS_BUS + BUS_PASS_ORDER_MIDDLE); + 0, 0, BUS_PASS_RESOURCE + BUS_PASS_ORDER_MIDDLE); MODULE_VERSION(aw_ccu, 1); Index: head/sys/arm/allwinner/aw_gmacclk.c =================================================================== --- head/sys/arm/allwinner/aw_gmacclk.c (revision 350841) +++ head/sys/arm/allwinner/aw_gmacclk.c (revision 350842) @@ -1,280 +1,280 @@ /*- * Copyright (c) 2016 Jared McNeill * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. * * $FreeBSD$ */ /* * Allwinner GMAC clock */ #include __FBSDID("$FreeBSD$"); #include #include #include #include #include #include #include #include #include #include #include #include #include "clkdev_if.h" #define GMAC_CLK_PIT (0x1 << 2) #define GMAC_CLK_PIT_SHIFT 2 #define GMAC_CLK_PIT_MII 0 #define GMAC_CLK_PIT_RGMII 1 #define GMAC_CLK_SRC (0x3 << 0) #define GMAC_CLK_SRC_SHIFT 0 #define GMAC_CLK_SRC_MII 0 #define GMAC_CLK_SRC_EXT_RGMII 1 #define GMAC_CLK_SRC_RGMII 2 #define EMAC_TXC_DIV_CFG (1 << 15) #define EMAC_TXC_DIV_CFG_SHIFT 15 #define EMAC_TXC_DIV_CFG_125MHZ 0 #define EMAC_TXC_DIV_CFG_25MHZ 1 #define EMAC_PHY_SELECT (1 << 16) #define EMAC_PHY_SELECT_SHIFT 16 #define EMAC_PHY_SELECT_INT 0 #define EMAC_PHY_SELECT_EXT 1 #define EMAC_ETXDC (0x7 << 10) #define EMAC_ETXDC_SHIFT 10 #define EMAC_ERXDC (0x1f << 5) #define EMAC_ERXDC_SHIFT 5 #define CLK_IDX_MII 0 #define CLK_IDX_RGMII 1 #define CLK_IDX_COUNT 2 static struct ofw_compat_data compat_data[] = { { "allwinner,sun7i-a20-gmac-clk", 1 }, { NULL, 0 } }; struct aw_gmacclk_sc { device_t clkdev; bus_addr_t reg; int rx_delay; int tx_delay; }; #define GMACCLK_READ(sc, val) CLKDEV_READ_4((sc)->clkdev, (sc)->reg, (val)) #define GMACCLK_WRITE(sc, val) CLKDEV_WRITE_4((sc)->clkdev, (sc)->reg, (val)) #define DEVICE_LOCK(sc) CLKDEV_DEVICE_LOCK((sc)->clkdev) #define DEVICE_UNLOCK(sc) CLKDEV_DEVICE_UNLOCK((sc)->clkdev) static int aw_gmacclk_init(struct clknode *clk, device_t dev) { struct aw_gmacclk_sc *sc; uint32_t val, index; sc = clknode_get_softc(clk); DEVICE_LOCK(sc); GMACCLK_READ(sc, &val); DEVICE_UNLOCK(sc); switch ((val & GMAC_CLK_SRC) >> GMAC_CLK_SRC_SHIFT) { case GMAC_CLK_SRC_MII: index = CLK_IDX_MII; break; case GMAC_CLK_SRC_RGMII: index = CLK_IDX_RGMII; break; default: return (ENXIO); } clknode_init_parent_idx(clk, index); return (0); } static int aw_gmacclk_set_mux(struct clknode *clk, int index) { struct aw_gmacclk_sc *sc; uint32_t val, clk_src, pit, txc_div; int error; sc = clknode_get_softc(clk); error = 0; switch (index) { case CLK_IDX_MII: clk_src = GMAC_CLK_SRC_MII; pit = GMAC_CLK_PIT_MII; txc_div = EMAC_TXC_DIV_CFG_25MHZ; break; case CLK_IDX_RGMII: clk_src = GMAC_CLK_SRC_RGMII; pit = GMAC_CLK_PIT_RGMII; txc_div = EMAC_TXC_DIV_CFG_125MHZ; break; default: return (ENXIO); } DEVICE_LOCK(sc); GMACCLK_READ(sc, &val); val &= ~(GMAC_CLK_SRC | GMAC_CLK_PIT); val |= (clk_src << GMAC_CLK_SRC_SHIFT); val |= (pit << GMAC_CLK_PIT_SHIFT); GMACCLK_WRITE(sc, val); DEVICE_UNLOCK(sc); return (0); } static clknode_method_t aw_gmacclk_clknode_methods[] = { /* Device interface */ CLKNODEMETHOD(clknode_init, aw_gmacclk_init), CLKNODEMETHOD(clknode_set_mux, aw_gmacclk_set_mux), CLKNODEMETHOD_END }; DEFINE_CLASS_1(aw_gmacclk_clknode, aw_gmacclk_clknode_class, aw_gmacclk_clknode_methods, sizeof(struct aw_gmacclk_sc), clknode_class); static int aw_gmacclk_probe(device_t dev) { if (!ofw_bus_status_okay(dev)) return (ENXIO); if (ofw_bus_search_compatible(dev, compat_data)->ocd_data == 0) return (ENXIO); device_set_desc(dev, "Allwinner GMAC Clock"); return (BUS_PROBE_DEFAULT); } static int aw_gmacclk_attach(device_t dev) { struct clknode_init_def def; struct aw_gmacclk_sc *sc; struct clkdom *clkdom; struct clknode *clk; clk_t clk_parent; bus_addr_t paddr; bus_size_t psize; phandle_t node; int error, ncells, i; node = ofw_bus_get_node(dev); if (ofw_reg_to_paddr(node, 0, &paddr, &psize, NULL) != 0) { device_printf(dev, "cannot parse 'reg' property\n"); return (ENXIO); } error = ofw_bus_parse_xref_list_get_length(node, "clocks", "#clock-cells", &ncells); if (error != 0 || ncells != CLK_IDX_COUNT) { device_printf(dev, "couldn't find parent clocks\n"); return (ENXIO); } clkdom = clkdom_create(dev); memset(&def, 0, sizeof(def)); error = clk_parse_ofw_clk_name(dev, node, &def.name); if (error != 0) { device_printf(dev, "cannot parse clock name\n"); error = ENXIO; goto fail; } def.id = 1; def.parent_names = malloc(sizeof(char *) * ncells, M_OFWPROP, M_WAITOK); for (i = 0; i < ncells; i++) { error = clk_get_by_ofw_index(dev, 0, i, &clk_parent); if (error != 0) { device_printf(dev, "cannot get clock %d\n", error); goto fail; } def.parent_names[i] = clk_get_name(clk_parent); clk_release(clk_parent); } def.parent_cnt = ncells; clk = clknode_create(clkdom, &aw_gmacclk_clknode_class, &def); if (clk == NULL) { device_printf(dev, "cannot create clknode\n"); error = ENXIO; goto fail; } sc = clknode_get_softc(clk); sc->reg = paddr; sc->clkdev = device_get_parent(dev); sc->tx_delay = sc->rx_delay = -1; OF_getencprop(node, "tx-delay", &sc->tx_delay, sizeof(sc->tx_delay)); OF_getencprop(node, "rx-delay", &sc->rx_delay, sizeof(sc->rx_delay)); clknode_register(clkdom, clk); if (clkdom_finit(clkdom) != 0) { device_printf(dev, "cannot finalize clkdom initialization\n"); error = ENXIO; goto fail; } if (bootverbose) clkdom_dump(clkdom); return (0); fail: return (error); } static device_method_t aw_gmacclk_methods[] = { /* Device interface */ DEVMETHOD(device_probe, aw_gmacclk_probe), DEVMETHOD(device_attach, aw_gmacclk_attach), DEVMETHOD_END }; static driver_t aw_gmacclk_driver = { "aw_gmacclk", aw_gmacclk_methods, 0 }; static devclass_t aw_gmacclk_devclass; EARLY_DRIVER_MODULE(aw_gmacclk, simplebus, aw_gmacclk_driver, - aw_gmacclk_devclass, 0, 0, BUS_PASS_BUS + BUS_PASS_ORDER_MIDDLE); + aw_gmacclk_devclass, 0, 0, BUS_PASS_RESOURCE + BUS_PASS_ORDER_MIDDLE); Index: head/sys/arm/allwinner/aw_reset.c =================================================================== --- head/sys/arm/allwinner/aw_reset.c (revision 350841) +++ head/sys/arm/allwinner/aw_reset.c (revision 350842) @@ -1,166 +1,166 @@ /*- * Copyright (c) 2016 Jared McNeill * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. * * $FreeBSD$ */ /* * Allwinner module software reset registers */ #include __FBSDID("$FreeBSD$"); #include #include #include #include #include #include #include #include #include #include #include #include #include "hwreset_if.h" #define RESET_OFFSET(index) ((index / 32) * 4) #define RESET_SHIFT(index) (index % 32) static struct ofw_compat_data compat_data[] = { { "allwinner,sun6i-a31-ahb1-reset", 1 }, { "allwinner,sun6i-a31-clock-reset", 1 }, { NULL, 0 } }; struct aw_reset_softc { struct resource *res; struct mtx mtx; }; static struct resource_spec aw_reset_spec[] = { { SYS_RES_MEMORY, 0, RF_ACTIVE }, { -1, 0 } }; #define RESET_READ(sc, reg) bus_read_4((sc)->res, (reg)) #define RESET_WRITE(sc, reg, val) bus_write_4((sc)->res, (reg), (val)) static int aw_reset_assert(device_t dev, intptr_t id, bool reset) { struct aw_reset_softc *sc; uint32_t reg_value; sc = device_get_softc(dev); mtx_lock(&sc->mtx); reg_value = RESET_READ(sc, RESET_OFFSET(id)); if (reset) reg_value &= ~(1 << RESET_SHIFT(id)); else reg_value |= (1 << RESET_SHIFT(id)); RESET_WRITE(sc, RESET_OFFSET(id), reg_value); mtx_unlock(&sc->mtx); return (0); } static int aw_reset_is_asserted(device_t dev, intptr_t id, bool *reset) { struct aw_reset_softc *sc; uint32_t reg_value; sc = device_get_softc(dev); mtx_lock(&sc->mtx); reg_value = RESET_READ(sc, RESET_OFFSET(id)); mtx_unlock(&sc->mtx); *reset = (reg_value & (1 << RESET_SHIFT(id))) != 0 ? false : true; return (0); } static int aw_reset_probe(device_t dev) { if (!ofw_bus_status_okay(dev)) return (ENXIO); if (ofw_bus_search_compatible(dev, compat_data)->ocd_data == 0) return (ENXIO); device_set_desc(dev, "Allwinner Module Resets"); return (BUS_PROBE_DEFAULT); } static int aw_reset_attach(device_t dev) { struct aw_reset_softc *sc; sc = device_get_softc(dev); if (bus_alloc_resources(dev, aw_reset_spec, &sc->res) != 0) { device_printf(dev, "cannot allocate resources for device\n"); return (ENXIO); } mtx_init(&sc->mtx, device_get_nameunit(dev), NULL, MTX_DEF); hwreset_register_ofw_provider(dev); return (0); } static device_method_t aw_reset_methods[] = { /* Device interface */ DEVMETHOD(device_probe, aw_reset_probe), DEVMETHOD(device_attach, aw_reset_attach), /* Reset interface */ DEVMETHOD(hwreset_assert, aw_reset_assert), DEVMETHOD(hwreset_is_asserted, aw_reset_is_asserted), DEVMETHOD_END }; static driver_t aw_reset_driver = { "aw_reset", aw_reset_methods, sizeof(struct aw_reset_softc), }; static devclass_t aw_reset_devclass; EARLY_DRIVER_MODULE(aw_reset, simplebus, aw_reset_driver, aw_reset_devclass, - 0, 0, BUS_PASS_BUS + BUS_PASS_ORDER_MIDDLE); + 0, 0, BUS_PASS_RESOURCE + BUS_PASS_ORDER_MIDDLE); MODULE_VERSION(aw_reset, 1); Index: head/sys/arm/allwinner/aw_rsb.c =================================================================== --- head/sys/arm/allwinner/aw_rsb.c (revision 350841) +++ head/sys/arm/allwinner/aw_rsb.c (revision 350842) @@ -1,502 +1,502 @@ /*- * Copyright (c) 2016 Jared McNeill * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. * * $FreeBSD$ */ /* * Allwinner RSB (Reduced Serial Bus) and P2WI (Push-Pull Two Wire Interface) */ #include __FBSDID("$FreeBSD$"); #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include "iicbus_if.h" #define RSB_CTRL 0x00 #define START_TRANS (1 << 7) #define GLOBAL_INT_ENB (1 << 1) #define SOFT_RESET (1 << 0) #define RSB_CCR 0x04 #define RSB_INTE 0x08 #define RSB_INTS 0x0c #define INT_TRANS_ERR_ID(x) (((x) >> 8) & 0xf) #define INT_LOAD_BSY (1 << 2) #define INT_TRANS_ERR (1 << 1) #define INT_TRANS_OVER (1 << 0) #define INT_MASK (INT_LOAD_BSY|INT_TRANS_ERR|INT_TRANS_OVER) #define RSB_DADDR0 0x10 #define RSB_DADDR1 0x14 #define RSB_DLEN 0x18 #define DLEN_READ (1 << 4) #define RSB_DATA0 0x1c #define RSB_DATA1 0x20 #define RSB_CMD 0x2c #define CMD_SRTA 0xe8 #define CMD_RD8 0x8b #define CMD_RD16 0x9c #define CMD_RD32 0xa6 #define CMD_WR8 0x4e #define CMD_WR16 0x59 #define CMD_WR32 0x63 #define RSB_DAR 0x30 #define DAR_RTA (0xff << 16) #define DAR_RTA_SHIFT 16 #define DAR_DA (0xffff << 0) #define DAR_DA_SHIFT 0 #define RSB_MAXLEN 8 #define RSB_RESET_RETRY 100 #define RSB_I2C_TIMEOUT hz #define RSB_ADDR_PMIC_PRIMARY 0x3a3 #define RSB_ADDR_PMIC_SECONDARY 0x745 #define RSB_ADDR_PERIPH_IC 0xe89 #define A31_P2WI 1 #define A23_RSB 2 static struct ofw_compat_data compat_data[] = { { "allwinner,sun6i-a31-p2wi", A31_P2WI }, { "allwinner,sun8i-a23-rsb", A23_RSB }, { NULL, 0 } }; static struct resource_spec rsb_spec[] = { { SYS_RES_MEMORY, 0, RF_ACTIVE }, { -1, 0 } }; /* * Device address to Run-time address mappings. * * Run-time address (RTA) is an 8-bit value used to address the device during * a read or write transaction. The following are valid RTAs: * 0x17 0x2d 0x3a 0x4e 0x59 0x63 0x74 0x8b 0x9c 0xa6 0xb1 0xc5 0xd2 0xe8 0xff * * Allwinner uses RTA 0x2d for the primary PMIC, 0x3a for the secondary PMIC, * and 0x4e for the peripheral IC (where applicable). */ static const struct { uint16_t addr; uint8_t rta; } rsb_rtamap[] = { { .addr = RSB_ADDR_PMIC_PRIMARY, .rta = 0x2d }, { .addr = RSB_ADDR_PMIC_SECONDARY, .rta = 0x3a }, { .addr = RSB_ADDR_PERIPH_IC, .rta = 0x4e }, { .addr = 0, .rta = 0 } }; struct rsb_softc { struct resource *res; struct mtx mtx; clk_t clk; hwreset_t rst; device_t iicbus; int busy; uint32_t status; uint16_t cur_addr; int type; struct iic_msg *msg; }; #define RSB_LOCK(sc) mtx_lock(&(sc)->mtx) #define RSB_UNLOCK(sc) mtx_unlock(&(sc)->mtx) #define RSB_ASSERT_LOCKED(sc) mtx_assert(&(sc)->mtx, MA_OWNED) #define RSB_READ(sc, reg) bus_read_4((sc)->res, (reg)) #define RSB_WRITE(sc, reg, val) bus_write_4((sc)->res, (reg), (val)) static phandle_t rsb_get_node(device_t bus, device_t dev) { return (ofw_bus_get_node(bus)); } static int rsb_reset(device_t dev, u_char speed, u_char addr, u_char *oldaddr) { struct rsb_softc *sc; int retry; sc = device_get_softc(dev); RSB_LOCK(sc); /* Write soft-reset bit and wait for it to self-clear. */ RSB_WRITE(sc, RSB_CTRL, SOFT_RESET); for (retry = RSB_RESET_RETRY; retry > 0; retry--) if ((RSB_READ(sc, RSB_CTRL) & SOFT_RESET) == 0) break; RSB_UNLOCK(sc); if (retry == 0) { device_printf(dev, "soft reset timeout\n"); return (ETIMEDOUT); } return (IIC_ENOADDR); } static uint32_t rsb_encode(const uint8_t *buf, u_int len, u_int off) { uint32_t val; u_int n; val = 0; for (n = off; n < MIN(len, 4 + off); n++) val |= ((uint32_t)buf[n] << ((n - off) * NBBY)); return val; } static void rsb_decode(const uint32_t val, uint8_t *buf, u_int len, u_int off) { u_int n; for (n = off; n < MIN(len, 4 + off); n++) buf[n] = (val >> ((n - off) * NBBY)) & 0xff; } static int rsb_start(device_t dev) { struct rsb_softc *sc; int error, retry; sc = device_get_softc(dev); RSB_ASSERT_LOCKED(sc); /* Start the transfer */ RSB_WRITE(sc, RSB_CTRL, GLOBAL_INT_ENB | START_TRANS); /* Wait for transfer to complete */ error = ETIMEDOUT; for (retry = RSB_I2C_TIMEOUT; retry > 0; retry--) { sc->status |= RSB_READ(sc, RSB_INTS); if ((sc->status & INT_TRANS_OVER) != 0) { error = 0; break; } DELAY((1000 * hz) / RSB_I2C_TIMEOUT); } if (error == 0 && (sc->status & INT_TRANS_OVER) == 0) { device_printf(dev, "transfer error, status 0x%08x\n", sc->status); error = EIO; } return (error); } static int rsb_set_rta(device_t dev, uint16_t addr) { struct rsb_softc *sc; uint8_t rta; int i; sc = device_get_softc(dev); RSB_ASSERT_LOCKED(sc); /* Lookup run-time address for given device address */ for (rta = 0, i = 0; rsb_rtamap[i].rta != 0; i++) if (rsb_rtamap[i].addr == addr) { rta = rsb_rtamap[i].rta; break; } if (rta == 0) { device_printf(dev, "RTA not known for address %#x\n", addr); return (ENXIO); } /* Set run-time address */ RSB_WRITE(sc, RSB_INTS, RSB_READ(sc, RSB_INTS)); RSB_WRITE(sc, RSB_DAR, (addr << DAR_DA_SHIFT) | (rta << DAR_RTA_SHIFT)); RSB_WRITE(sc, RSB_CMD, CMD_SRTA); return (rsb_start(dev)); } static int rsb_transfer(device_t dev, struct iic_msg *msgs, uint32_t nmsgs) { struct rsb_softc *sc; uint32_t daddr[2], data[2], dlen; uint16_t device_addr; uint8_t cmd; int error; sc = device_get_softc(dev); /* * P2WI and RSB are not really I2C or SMBus controllers, so there are * some restrictions imposed by the driver. * * Transfers must contain exactly two messages. The first is always * a write, containing a single data byte offset. Data will either * be read from or written to the corresponding data byte in the * second message. The slave address in both messages must be the * same. */ if (nmsgs != 2 || (msgs[0].flags & IIC_M_RD) == IIC_M_RD || (msgs[0].slave >> 1) != (msgs[1].slave >> 1) || msgs[0].len != 1 || msgs[1].len > RSB_MAXLEN) return (EINVAL); /* The RSB controller can read or write 1, 2, or 4 bytes at a time. */ if (sc->type == A23_RSB) { if ((msgs[1].flags & IIC_M_RD) != 0) { switch (msgs[1].len) { case 1: cmd = CMD_RD8; break; case 2: cmd = CMD_RD16; break; case 4: cmd = CMD_RD32; break; default: return (EINVAL); } } else { switch (msgs[1].len) { case 1: cmd = CMD_WR8; break; case 2: cmd = CMD_WR16; break; case 4: cmd = CMD_WR32; break; default: return (EINVAL); } } } RSB_LOCK(sc); while (sc->busy) mtx_sleep(sc, &sc->mtx, 0, "i2cbuswait", 0); sc->busy = 1; sc->status = 0; /* Select current run-time address if necessary */ if (sc->type == A23_RSB) { device_addr = msgs[0].slave >> 1; if (sc->cur_addr != device_addr) { error = rsb_set_rta(dev, device_addr); if (error != 0) goto done; sc->cur_addr = device_addr; sc->status = 0; } } /* Clear interrupt status */ RSB_WRITE(sc, RSB_INTS, RSB_READ(sc, RSB_INTS)); /* Program data access address registers */ daddr[0] = rsb_encode(msgs[0].buf, msgs[0].len, 0); RSB_WRITE(sc, RSB_DADDR0, daddr[0]); /* Write data */ if ((msgs[1].flags & IIC_M_RD) == 0) { data[0] = rsb_encode(msgs[1].buf, msgs[1].len, 0); RSB_WRITE(sc, RSB_DATA0, data[0]); } /* Set command type for RSB */ if (sc->type == A23_RSB) RSB_WRITE(sc, RSB_CMD, cmd); /* Program data length register and transfer direction */ dlen = msgs[0].len - 1; if ((msgs[1].flags & IIC_M_RD) == IIC_M_RD) dlen |= DLEN_READ; RSB_WRITE(sc, RSB_DLEN, dlen); /* Start transfer */ error = rsb_start(dev); if (error != 0) goto done; /* Read data */ if ((msgs[1].flags & IIC_M_RD) == IIC_M_RD) { data[0] = RSB_READ(sc, RSB_DATA0); rsb_decode(data[0], msgs[1].buf, msgs[1].len, 0); } done: sc->msg = NULL; sc->busy = 0; wakeup(sc); RSB_UNLOCK(sc); return (error); } static int rsb_probe(device_t dev) { if (!ofw_bus_status_okay(dev)) return (ENXIO); switch (ofw_bus_search_compatible(dev, compat_data)->ocd_data) { case A23_RSB: device_set_desc(dev, "Allwinner RSB"); break; case A31_P2WI: device_set_desc(dev, "Allwinner P2WI"); break; default: return (ENXIO); } return (BUS_PROBE_DEFAULT); } static int rsb_attach(device_t dev) { struct rsb_softc *sc; int error; sc = device_get_softc(dev); mtx_init(&sc->mtx, device_get_nameunit(dev), "rsb", MTX_DEF); sc->type = ofw_bus_search_compatible(dev, compat_data)->ocd_data; if (clk_get_by_ofw_index(dev, 0, 0, &sc->clk) == 0) { error = clk_enable(sc->clk); if (error != 0) { device_printf(dev, "cannot enable clock\n"); goto fail; } } if (hwreset_get_by_ofw_idx(dev, 0, 0, &sc->rst) == 0) { error = hwreset_deassert(sc->rst); if (error != 0) { device_printf(dev, "cannot de-assert reset\n"); goto fail; } } if (bus_alloc_resources(dev, rsb_spec, &sc->res) != 0) { device_printf(dev, "cannot allocate resources for device\n"); error = ENXIO; goto fail; } sc->iicbus = device_add_child(dev, "iicbus", -1); if (sc->iicbus == NULL) { device_printf(dev, "cannot add iicbus child device\n"); error = ENXIO; goto fail; } bus_generic_attach(dev); return (0); fail: bus_release_resources(dev, rsb_spec, &sc->res); if (sc->rst != NULL) hwreset_release(sc->rst); if (sc->clk != NULL) clk_release(sc->clk); mtx_destroy(&sc->mtx); return (error); } static device_method_t rsb_methods[] = { /* Device interface */ DEVMETHOD(device_probe, rsb_probe), DEVMETHOD(device_attach, rsb_attach), /* Bus interface */ DEVMETHOD(bus_setup_intr, bus_generic_setup_intr), DEVMETHOD(bus_teardown_intr, bus_generic_teardown_intr), DEVMETHOD(bus_alloc_resource, bus_generic_alloc_resource), DEVMETHOD(bus_release_resource, bus_generic_release_resource), DEVMETHOD(bus_activate_resource, bus_generic_activate_resource), DEVMETHOD(bus_deactivate_resource, bus_generic_deactivate_resource), DEVMETHOD(bus_adjust_resource, bus_generic_adjust_resource), DEVMETHOD(bus_set_resource, bus_generic_rl_set_resource), DEVMETHOD(bus_get_resource, bus_generic_rl_get_resource), /* OFW methods */ DEVMETHOD(ofw_bus_get_node, rsb_get_node), /* iicbus interface */ DEVMETHOD(iicbus_callback, iicbus_null_callback), DEVMETHOD(iicbus_reset, rsb_reset), DEVMETHOD(iicbus_transfer, rsb_transfer), DEVMETHOD_END }; static driver_t rsb_driver = { "iichb", rsb_methods, sizeof(struct rsb_softc), }; static devclass_t rsb_devclass; EARLY_DRIVER_MODULE(iicbus, rsb, iicbus_driver, iicbus_devclass, 0, 0, - BUS_PASS_RESOURCE + BUS_PASS_ORDER_MIDDLE); + BUS_PASS_SUPPORTDEV + BUS_PASS_ORDER_MIDDLE); EARLY_DRIVER_MODULE(rsb, simplebus, rsb_driver, rsb_devclass, 0, 0, - BUS_PASS_RESOURCE + BUS_PASS_ORDER_MIDDLE); + BUS_PASS_SUPPORTDEV + BUS_PASS_ORDER_MIDDLE); MODULE_VERSION(rsb, 1); MODULE_DEPEND(rsb, iicbus, 1, 1, 1); SIMPLEBUS_PNP_INFO(compat_data); Index: head/sys/arm/allwinner/aw_rtc.c =================================================================== --- head/sys/arm/allwinner/aw_rtc.c (revision 350841) +++ head/sys/arm/allwinner/aw_rtc.c (revision 350842) @@ -1,367 +1,367 @@ /*- * Copyright (c) 2019 Emmanuel Vadot * Copyright (c) 2016 Vladimir Belian * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. */ #include __FBSDID("$FreeBSD$"); #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include "clock_if.h" #define LOSC_CTRL_REG 0x00 #define A10_RTC_DATE_REG 0x04 #define A10_RTC_TIME_REG 0x08 #define A31_LOSC_AUTO_SWT_STA 0x04 #define A31_RTC_DATE_REG 0x10 #define A31_RTC_TIME_REG 0x14 #define TIME_MASK 0x001f3f3f #define LOSC_OSC_SRC (1 << 0) #define LOSC_GSM (1 << 3) #define LOSC_AUTO_SW_EN (1 << 14) #define LOSC_MAGIC 0x16aa0000 #define LOSC_BUSY_MASK 0x00000380 #define IS_SUN7I (sc->conf->is_a20 == true) #define YEAR_MIN (IS_SUN7I ? 1970 : 2010) #define YEAR_MAX (IS_SUN7I ? 2100 : 2073) #define YEAR_OFFSET (IS_SUN7I ? 1900 : 2010) #define YEAR_MASK (IS_SUN7I ? 0xff : 0x3f) #define LEAP_BIT (IS_SUN7I ? 24 : 22) #define GET_SEC_VALUE(x) ((x) & 0x0000003f) #define GET_MIN_VALUE(x) (((x) & 0x00003f00) >> 8) #define GET_HOUR_VALUE(x) (((x) & 0x001f0000) >> 16) #define GET_DAY_VALUE(x) ((x) & 0x0000001f) #define GET_MON_VALUE(x) (((x) & 0x00000f00) >> 8) #define GET_YEAR_VALUE(x) (((x) >> 16) & YEAR_MASK) #define SET_DAY_VALUE(x) GET_DAY_VALUE(x) #define SET_MON_VALUE(x) (((x) & 0x0000000f) << 8) #define SET_YEAR_VALUE(x) (((x) & YEAR_MASK) << 16) #define SET_LEAP_VALUE(x) (((x) & 0x00000001) << LEAP_BIT) #define SET_SEC_VALUE(x) GET_SEC_VALUE(x) #define SET_MIN_VALUE(x) (((x) & 0x0000003f) << 8) #define SET_HOUR_VALUE(x) (((x) & 0x0000001f) << 16) #define HALF_OF_SEC_NS 500000000 #define RTC_RES_US 1000000 #define RTC_TIMEOUT 70 #define RTC_READ(sc, reg) bus_read_4((sc)->res, (reg)) #define RTC_WRITE(sc, reg, val) bus_write_4((sc)->res, (reg), (val)) #define IS_LEAP_YEAR(y) (((y) % 400) == 0 || (((y) % 100) != 0 && ((y) % 4) == 0)) struct aw_rtc_conf { uint64_t iosc_freq; bus_size_t rtc_date; bus_size_t rtc_time; bus_size_t rtc_losc_sta; bool is_a20; }; struct aw_rtc_conf a10_conf = { .rtc_date = A10_RTC_DATE_REG, .rtc_time = A10_RTC_TIME_REG, .rtc_losc_sta = LOSC_CTRL_REG, }; struct aw_rtc_conf a20_conf = { .rtc_date = A10_RTC_DATE_REG, .rtc_time = A10_RTC_TIME_REG, .rtc_losc_sta = LOSC_CTRL_REG, .is_a20 = true, }; struct aw_rtc_conf a31_conf = { .iosc_freq = 650000, /* between 600 and 700 Khz */ .rtc_date = A31_RTC_DATE_REG, .rtc_time = A31_RTC_TIME_REG, .rtc_losc_sta = A31_LOSC_AUTO_SWT_STA, }; struct aw_rtc_conf h3_conf = { .iosc_freq = 16000000, .rtc_date = A31_RTC_DATE_REG, .rtc_time = A31_RTC_TIME_REG, .rtc_losc_sta = A31_LOSC_AUTO_SWT_STA, }; static struct ofw_compat_data compat_data[] = { { "allwinner,sun4i-a10-rtc", (uintptr_t) &a10_conf }, { "allwinner,sun7i-a20-rtc", (uintptr_t) &a20_conf }, { "allwinner,sun6i-a31-rtc", (uintptr_t) &a31_conf }, { "allwinner,sun8i-h3-rtc", (uintptr_t) &h3_conf }, { "allwinner,sun50i-h5-rtc", (uintptr_t) &h3_conf }, { NULL, 0 } }; struct aw_rtc_softc { struct resource *res; struct aw_rtc_conf *conf; int type; }; static struct clk_fixed_def aw_rtc_osc32k = { .clkdef.id = 0, .freq = 32768, }; static struct clk_fixed_def aw_rtc_iosc = { .clkdef.id = 2, }; static void aw_rtc_install_clocks(struct aw_rtc_softc *sc, device_t dev); static int aw_rtc_probe(device_t dev); static int aw_rtc_attach(device_t dev); static int aw_rtc_detach(device_t dev); static int aw_rtc_gettime(device_t dev, struct timespec *ts); static int aw_rtc_settime(device_t dev, struct timespec *ts); static device_method_t aw_rtc_methods[] = { DEVMETHOD(device_probe, aw_rtc_probe), DEVMETHOD(device_attach, aw_rtc_attach), DEVMETHOD(device_detach, aw_rtc_detach), DEVMETHOD(clock_gettime, aw_rtc_gettime), DEVMETHOD(clock_settime, aw_rtc_settime), DEVMETHOD_END }; static driver_t aw_rtc_driver = { "rtc", aw_rtc_methods, sizeof(struct aw_rtc_softc), }; static devclass_t aw_rtc_devclass; EARLY_DRIVER_MODULE(aw_rtc, simplebus, aw_rtc_driver, aw_rtc_devclass, 0, 0, - BUS_PASS_BUS + BUS_PASS_ORDER_MIDDLE); + BUS_PASS_RESOURCE + BUS_PASS_ORDER_FIRST); MODULE_VERSION(aw_rtc, 1); SIMPLEBUS_PNP_INFO(compat_data); static int aw_rtc_probe(device_t dev) { if (!ofw_bus_status_okay(dev)) return (ENXIO); if (!ofw_bus_search_compatible(dev, compat_data)->ocd_data) return (ENXIO); device_set_desc(dev, "Allwinner RTC"); return (BUS_PROBE_DEFAULT); } static int aw_rtc_attach(device_t dev) { struct aw_rtc_softc *sc = device_get_softc(dev); uint32_t val; int rid = 0; sc->res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, RF_ACTIVE); if (!sc->res) { device_printf(dev, "could not allocate resources\n"); return (ENXIO); } sc->conf = (struct aw_rtc_conf *)ofw_bus_search_compatible(dev, compat_data)->ocd_data; val = RTC_READ(sc, LOSC_CTRL_REG); val |= LOSC_AUTO_SW_EN; val |= LOSC_MAGIC | LOSC_GSM | LOSC_OSC_SRC; RTC_WRITE(sc, LOSC_CTRL_REG, val); DELAY(100); if (bootverbose) { val = RTC_READ(sc, sc->conf->rtc_losc_sta); if ((val & LOSC_OSC_SRC) == 0) device_printf(dev, "Using internal oscillator\n"); else device_printf(dev, "Using external oscillator\n"); } aw_rtc_install_clocks(sc, dev); clock_register(dev, RTC_RES_US); return (0); } static int aw_rtc_detach(device_t dev) { /* can't support detach, since there's no clock_unregister function */ return (EBUSY); } static void aw_rtc_install_clocks(struct aw_rtc_softc *sc, device_t dev) { struct clkdom *clkdom; const char **clknames; phandle_t node; int nclocks; node = ofw_bus_get_node(dev); nclocks = ofw_bus_string_list_to_array(node, "clock-output-names", &clknames); /* No clocks to export */ if (nclocks <= 0) return; if (nclocks != 3) { device_printf(dev, "Having only %d clocks instead of 3, aborting\n", nclocks); return; } clkdom = clkdom_create(dev); aw_rtc_osc32k.clkdef.name = clknames[0]; if (clknode_fixed_register(clkdom, &aw_rtc_osc32k) != 0) device_printf(dev, "Cannot register osc32k clock\n"); aw_rtc_iosc.clkdef.name = clknames[2]; aw_rtc_iosc.freq = sc->conf->iosc_freq; if (clknode_fixed_register(clkdom, &aw_rtc_iosc) != 0) device_printf(dev, "Cannot register iosc clock\n"); clkdom_finit(clkdom); if (bootverbose) clkdom_dump(clkdom); } static int aw_rtc_gettime(device_t dev, struct timespec *ts) { struct aw_rtc_softc *sc = device_get_softc(dev); struct clocktime ct; uint32_t rdate, rtime; rdate = RTC_READ(sc, sc->conf->rtc_date); rtime = RTC_READ(sc, sc->conf->rtc_time); if ((rtime & TIME_MASK) == 0) rdate = RTC_READ(sc, sc->conf->rtc_date); ct.sec = GET_SEC_VALUE(rtime); ct.min = GET_MIN_VALUE(rtime); ct.hour = GET_HOUR_VALUE(rtime); ct.day = GET_DAY_VALUE(rdate); ct.mon = GET_MON_VALUE(rdate); ct.year = GET_YEAR_VALUE(rdate) + YEAR_OFFSET; ct.dow = -1; /* RTC resolution is 1 sec */ ct.nsec = 0; return (clock_ct_to_ts(&ct, ts)); } static int aw_rtc_settime(device_t dev, struct timespec *ts) { struct aw_rtc_softc *sc = device_get_softc(dev); struct clocktime ct; uint32_t clk, rdate, rtime; /* RTC resolution is 1 sec */ if (ts->tv_nsec >= HALF_OF_SEC_NS) ts->tv_sec++; ts->tv_nsec = 0; clock_ts_to_ct(ts, &ct); if ((ct.year < YEAR_MIN) || (ct.year > YEAR_MAX)) { device_printf(dev, "could not set time, year out of range\n"); return (EINVAL); } for (clk = 0; RTC_READ(sc, LOSC_CTRL_REG) & LOSC_BUSY_MASK; clk++) { if (clk > RTC_TIMEOUT) { device_printf(dev, "could not set time, RTC busy\n"); return (EINVAL); } DELAY(1); } /* reset time register to avoid unexpected date increment */ RTC_WRITE(sc, sc->conf->rtc_time, 0); rdate = SET_DAY_VALUE(ct.day) | SET_MON_VALUE(ct.mon) | SET_YEAR_VALUE(ct.year - YEAR_OFFSET) | SET_LEAP_VALUE(IS_LEAP_YEAR(ct.year)); rtime = SET_SEC_VALUE(ct.sec) | SET_MIN_VALUE(ct.min) | SET_HOUR_VALUE(ct.hour); for (clk = 0; RTC_READ(sc, LOSC_CTRL_REG) & LOSC_BUSY_MASK; clk++) { if (clk > RTC_TIMEOUT) { device_printf(dev, "could not set date, RTC busy\n"); return (EINVAL); } DELAY(1); } RTC_WRITE(sc, sc->conf->rtc_date, rdate); for (clk = 0; RTC_READ(sc, LOSC_CTRL_REG) & LOSC_BUSY_MASK; clk++) { if (clk > RTC_TIMEOUT) { device_printf(dev, "could not set time, RTC busy\n"); return (EINVAL); } DELAY(1); } RTC_WRITE(sc, sc->conf->rtc_time, rtime); DELAY(RTC_TIMEOUT); return (0); } Index: head/sys/arm/allwinner/aw_sid.c =================================================================== --- head/sys/arm/allwinner/aw_sid.c (revision 350841) +++ head/sys/arm/allwinner/aw_sid.c (revision 350842) @@ -1,417 +1,417 @@ /*- * Copyright (c) 2016 Jared McNeill * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. * * $FreeBSD$ */ /* * Allwinner secure ID controller */ #include __FBSDID("$FreeBSD$"); #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include "nvmem_if.h" /* * Starting at least from sun8iw6 (A83T) EFUSE starts at 0x200 * There is 3 registers in the low area to read/write protected EFUSE. */ #define SID_PRCTL 0x40 #define SID_PRCTL_OFFSET_MASK 0xff #define SID_PRCTL_OFFSET(n) (((n) & SID_PRCTL_OFFSET_MASK) << 16) #define SID_PRCTL_LOCK (0xac << 8) #define SID_PRCTL_READ (0x01 << 1) #define SID_PRCTL_WRITE (0x01 << 0) #define SID_PRKEY 0x50 #define SID_RDKEY 0x60 #define EFUSE_OFFSET 0x200 #define EFUSE_NAME_SIZE 32 #define EFUSE_DESC_SIZE 64 struct aw_sid_efuse { char name[EFUSE_NAME_SIZE]; char desc[EFUSE_DESC_SIZE]; bus_size_t base; bus_size_t offset; uint32_t size; enum aw_sid_fuse_id id; bool public; }; static struct aw_sid_efuse a10_efuses[] = { { .name = "rootkey", .desc = "Root Key or ChipID", .offset = 0x0, .size = 16, .id = AW_SID_FUSE_ROOTKEY, .public = true, }, }; static struct aw_sid_efuse a64_efuses[] = { { .name = "rootkey", .desc = "Root Key or ChipID", .base = EFUSE_OFFSET, .offset = 0x00, .size = 16, .id = AW_SID_FUSE_ROOTKEY, .public = true, }, { .name = "ths-calib", .desc = "Thermal Sensor Calibration Data", .base = EFUSE_OFFSET, .offset = 0x34, .size = 6, .id = AW_SID_FUSE_THSSENSOR, .public = true, }, }; static struct aw_sid_efuse a83t_efuses[] = { { .name = "rootkey", .desc = "Root Key or ChipID", .base = EFUSE_OFFSET, .offset = 0x00, .size = 16, .id = AW_SID_FUSE_ROOTKEY, .public = true, }, { .name = "ths-calib", .desc = "Thermal Sensor Calibration Data", .base = EFUSE_OFFSET, .offset = 0x34, .size = 8, .id = AW_SID_FUSE_THSSENSOR, .public = true, }, }; static struct aw_sid_efuse h3_efuses[] = { { .name = "rootkey", .desc = "Root Key or ChipID", .base = EFUSE_OFFSET, .offset = 0x00, .size = 16, .id = AW_SID_FUSE_ROOTKEY, .public = true, }, { .name = "ths-calib", .desc = "Thermal Sensor Calibration Data", .base = EFUSE_OFFSET, .offset = 0x34, .size = 2, .id = AW_SID_FUSE_THSSENSOR, .public = false, }, }; static struct aw_sid_efuse h5_efuses[] = { { .name = "rootkey", .desc = "Root Key or ChipID", .base = EFUSE_OFFSET, .offset = 0x00, .size = 16, .id = AW_SID_FUSE_ROOTKEY, .public = true, }, { .name = "ths-calib", .desc = "Thermal Sensor Calibration Data", .base = EFUSE_OFFSET, .offset = 0x34, .size = 4, .id = AW_SID_FUSE_THSSENSOR, .public = true, }, }; struct aw_sid_conf { struct aw_sid_efuse *efuses; size_t nfuses; }; static const struct aw_sid_conf a10_conf = { .efuses = a10_efuses, .nfuses = nitems(a10_efuses), }; static const struct aw_sid_conf a20_conf = { .efuses = a10_efuses, .nfuses = nitems(a10_efuses), }; static const struct aw_sid_conf a64_conf = { .efuses = a64_efuses, .nfuses = nitems(a64_efuses), }; static const struct aw_sid_conf a83t_conf = { .efuses = a83t_efuses, .nfuses = nitems(a83t_efuses), }; static const struct aw_sid_conf h3_conf = { .efuses = h3_efuses, .nfuses = nitems(h3_efuses), }; static const struct aw_sid_conf h5_conf = { .efuses = h5_efuses, .nfuses = nitems(h5_efuses), }; static struct ofw_compat_data compat_data[] = { { "allwinner,sun4i-a10-sid", (uintptr_t)&a10_conf}, { "allwinner,sun7i-a20-sid", (uintptr_t)&a20_conf}, { "allwinner,sun50i-a64-sid", (uintptr_t)&a64_conf}, { "allwinner,sun8i-a83t-sid", (uintptr_t)&a83t_conf}, { "allwinner,sun8i-h3-sid", (uintptr_t)&h3_conf}, { "allwinner,sun50i-h5-sid", (uintptr_t)&h5_conf}, { NULL, 0 } }; struct aw_sid_softc { device_t sid_dev; struct resource *res; struct aw_sid_conf *sid_conf; struct mtx prctl_mtx; }; static struct aw_sid_softc *aw_sid_sc; static struct resource_spec aw_sid_spec[] = { { SYS_RES_MEMORY, 0, RF_ACTIVE }, { -1, 0 } }; #define RD1(sc, reg) bus_read_1((sc)->res, (reg)) #define RD4(sc, reg) bus_read_4((sc)->res, (reg)) #define WR4(sc, reg, val) bus_write_4((sc)->res, (reg), (val)) static int aw_sid_sysctl(SYSCTL_HANDLER_ARGS); static int aw_sid_probe(device_t dev) { if (!ofw_bus_status_okay(dev)) return (ENXIO); if (ofw_bus_search_compatible(dev, compat_data)->ocd_data == 0) return (ENXIO); device_set_desc(dev, "Allwinner Secure ID Controller"); return (BUS_PROBE_DEFAULT); } static int aw_sid_attach(device_t dev) { struct aw_sid_softc *sc; phandle_t node; int i; node = ofw_bus_get_node(dev); sc = device_get_softc(dev); sc->sid_dev = dev; if (bus_alloc_resources(dev, aw_sid_spec, &sc->res) != 0) { device_printf(dev, "cannot allocate resources for device\n"); return (ENXIO); } mtx_init(&sc->prctl_mtx, device_get_nameunit(dev), NULL, MTX_DEF); sc->sid_conf = (struct aw_sid_conf *)ofw_bus_search_compatible(dev, compat_data)->ocd_data; aw_sid_sc = sc; /* Register ourself so device can resolve who we are */ OF_device_register_xref(OF_xref_from_node(node), dev); for (i = 0; i < sc->sid_conf->nfuses ;i++) {\ SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev), SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), OID_AUTO, sc->sid_conf->efuses[i].name, CTLTYPE_STRING | CTLFLAG_RD, dev, sc->sid_conf->efuses[i].id, aw_sid_sysctl, "A", sc->sid_conf->efuses[i].desc); } return (0); } int aw_sid_get_fuse(enum aw_sid_fuse_id id, uint8_t *out, uint32_t *size) { struct aw_sid_softc *sc; uint32_t val; int i, j; sc = aw_sid_sc; if (sc == NULL) return (ENXIO); for (i = 0; i < sc->sid_conf->nfuses; i++) if (id == sc->sid_conf->efuses[i].id) break; if (i == sc->sid_conf->nfuses) return (ENOENT); if (*size != sc->sid_conf->efuses[i].size) { *size = sc->sid_conf->efuses[i].size; return (ENOMEM); } if (out == NULL) return (ENOMEM); if (sc->sid_conf->efuses[i].public == false) mtx_lock(&sc->prctl_mtx); for (j = 0; j < sc->sid_conf->efuses[i].size; j += 4) { if (sc->sid_conf->efuses[i].public == false) { val = SID_PRCTL_OFFSET(sc->sid_conf->efuses[i].offset + j) | SID_PRCTL_LOCK | SID_PRCTL_READ; WR4(sc, SID_PRCTL, val); /* Read bit will be cleared once read has concluded */ while (RD4(sc, SID_PRCTL) & SID_PRCTL_READ) continue; val = RD4(sc, SID_RDKEY); } else val = RD4(sc, sc->sid_conf->efuses[i].base + sc->sid_conf->efuses[i].offset + j); out[j] = val & 0xFF; if (j + 1 < *size) out[j + 1] = (val & 0xFF00) >> 8; if (j + 2 < *size) out[j + 2] = (val & 0xFF0000) >> 16; if (j + 3 < *size) out[j + 3] = (val & 0xFF000000) >> 24; } if (sc->sid_conf->efuses[i].public == false) mtx_unlock(&sc->prctl_mtx); return (0); } static int aw_sid_read(device_t dev, uint32_t offset, uint32_t size, uint8_t *buffer) { struct aw_sid_softc *sc; enum aw_sid_fuse_id fuse_id = 0; int i; sc = device_get_softc(dev); for (i = 0; i < sc->sid_conf->nfuses; i++) if (offset == (sc->sid_conf->efuses[i].base + sc->sid_conf->efuses[i].offset)) { fuse_id = sc->sid_conf->efuses[i].id; break; } if (fuse_id == 0) return (ENOENT); return (aw_sid_get_fuse(fuse_id, buffer, &size)); } static int aw_sid_sysctl(SYSCTL_HANDLER_ARGS) { struct aw_sid_softc *sc; device_t dev = arg1; enum aw_sid_fuse_id fuse = arg2; uint8_t data[32]; char out[128]; uint32_t size; int ret, i; sc = device_get_softc(dev); /* Get the size of the efuse data */ size = 0; aw_sid_get_fuse(fuse, NULL, &size); /* We now have the real size */ ret = aw_sid_get_fuse(fuse, data, &size); if (ret != 0) { device_printf(dev, "Cannot get fuse id %d: %d\n", fuse, ret); return (ENOENT); } for (i = 0; i < size; i++) snprintf(out + (i * 2), sizeof(out) - (i * 2), "%.2x", data[i]); return sysctl_handle_string(oidp, out, sizeof(out), req); } static device_method_t aw_sid_methods[] = { /* Device interface */ DEVMETHOD(device_probe, aw_sid_probe), DEVMETHOD(device_attach, aw_sid_attach), /* NVMEM interface */ DEVMETHOD(nvmem_read, aw_sid_read), DEVMETHOD_END }; static driver_t aw_sid_driver = { "aw_sid", aw_sid_methods, sizeof(struct aw_sid_softc), }; static devclass_t aw_sid_devclass; EARLY_DRIVER_MODULE(aw_sid, simplebus, aw_sid_driver, aw_sid_devclass, 0, 0, - BUS_PASS_RESOURCE + BUS_PASS_ORDER_FIRST); + BUS_PASS_SUPPORTDEV + BUS_PASS_ORDER_FIRST); MODULE_VERSION(aw_sid, 1); SIMPLEBUS_PNP_INFO(compat_data); Index: head/sys/arm/allwinner/aw_syscon.c =================================================================== --- head/sys/arm/allwinner/aw_syscon.c (revision 350841) +++ head/sys/arm/allwinner/aw_syscon.c (revision 350842) @@ -1,86 +1,86 @@ /*- * SPDX-License-Identifier: BSD-2-Clause-FreeBSD * * Copyright (c) 2018 Kyle Evans * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. */ /* * Allwinner syscon driver */ #include __FBSDID("$FreeBSD$"); #include #include #include #include #include #include #include #include #include #include #include #include static struct ofw_compat_data compat_data[] = { {"allwinner,sun50i-a64-system-controller", 1}, {"allwinner,sun50i-a64-system-control", 1}, {"allwinner,sun8i-a83t-system-controller", 1}, {"allwinner,sun8i-h3-system-controller", 1}, {"allwinner,sun8i-h3-system-control", 1}, {"allwinner,sun50i-h5-system-control", 1}, {NULL, 0} }; static int aw_syscon_probe(device_t dev) { if (!ofw_bus_status_okay(dev)) return (ENXIO); if (ofw_bus_search_compatible(dev, compat_data)->ocd_data == 0) return (ENXIO); device_set_desc(dev, "Allwinner syscon"); return (BUS_PROBE_DEFAULT); } static device_method_t aw_syscon_methods[] = { DEVMETHOD(device_probe, aw_syscon_probe), DEVMETHOD_END }; DEFINE_CLASS_1(aw_syscon, aw_syscon_driver, aw_syscon_methods, sizeof(struct syscon_generic_softc), syscon_generic_driver); static devclass_t aw_syscon_devclass; /* aw_syscon needs to attach prior to if_awg */ EARLY_DRIVER_MODULE(aw_syscon, simplebus, aw_syscon_driver, aw_syscon_devclass, - 0, 0, BUS_PASS_SUPPORTDEV + BUS_PASS_ORDER_MIDDLE); + 0, 0, BUS_PASS_SCHEDULER + BUS_PASS_ORDER_LAST); MODULE_VERSION(aw_syscon, 1); Index: head/sys/arm/allwinner/clkng/ccu_a10.c =================================================================== --- head/sys/arm/allwinner/clkng/ccu_a10.c (revision 350841) +++ head/sys/arm/allwinner/clkng/ccu_a10.c (revision 350842) @@ -1,624 +1,624 @@ /*- * SPDX-License-Identifier: BSD-2-Clause-FreeBSD * * Copyright (c) 2018 Kyle Evans * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. * * $FreeBSD$ */ #include __FBSDID("$FreeBSD$"); #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include /* Non-exported resets */ /* Non-exported clocks */ #define CLK_PLL_CORE 2 #define CLK_AXI 3 #define CLK_AHB 4 #define CLK_APB0 5 #define CLK_APB1 6 #define CLK_PLL_VIDEO0 8 #define CLK_PLL_DDR 12 #define CLK_PLL_DDR_OTHER 13 #define CLK_PLL6 14 #define CLK_PLL_PERIPH 15 #define CLK_PLL_SATA 16 #define CLK_PLL_VIDEO1 17 /* Non-exported fixed clocks */ static struct aw_ccung_reset a10_ccu_resets[] = { CCU_RESET(RST_USB_PHY0, 0xcc, 0) CCU_RESET(RST_USB_PHY1, 0xcc, 1) CCU_RESET(RST_USB_PHY2, 0xcc, 2) CCU_RESET(RST_GPS, 0xd0, 0) CCU_RESET(RST_DE_BE0, 0x104, 30) CCU_RESET(RST_DE_BE1, 0x108, 30) CCU_RESET(RST_DE_FE0, 0x10c, 30) CCU_RESET(RST_DE_FE1, 0x110, 30) CCU_RESET(RST_DE_MP, 0x114, 30) CCU_RESET(RST_TVE0, 0x118, 29) CCU_RESET(RST_TCON0, 0x118, 30) CCU_RESET(RST_TVE1, 0x11c, 29) CCU_RESET(RST_TCON1, 0x11c, 30) CCU_RESET(RST_CSI0, 0x134, 30) CCU_RESET(RST_CSI1, 0x138, 30) CCU_RESET(RST_VE, 0x13c, 0) CCU_RESET(RST_ACE, 0x148, 16) CCU_RESET(RST_LVDS, 0x14c, 0) CCU_RESET(RST_GPU, 0x154, 30) CCU_RESET(RST_HDMI_H, 0x170, 0) CCU_RESET(RST_HDMI_SYS, 0x170, 1) CCU_RESET(RST_HDMI_AUDIO_DMA, 0x170, 2) }; static struct aw_ccung_gate a10_ccu_gates[] = { CCU_GATE(CLK_HOSC, "hosc", "osc24M", 0x50, 0) CCU_GATE(CLK_AHB_OTG, "ahb-otg", "ahb", 0x60, 0) CCU_GATE(CLK_AHB_EHCI0, "ahb-ehci0", "ahb", 0x60, 1) CCU_GATE(CLK_AHB_OHCI0, "ahb-ohci0", "ahb", 0x60, 2) CCU_GATE(CLK_AHB_EHCI1, "ahb-ehci1", "ahb", 0x60, 3) CCU_GATE(CLK_AHB_OHCI1, "ahb-ohci1", "ahb", 0x60, 4) CCU_GATE(CLK_AHB_SS, "ahb-ss", "ahb", 0x60, 5) CCU_GATE(CLK_AHB_DMA, "ahb-dma", "ahb", 0x60, 6) CCU_GATE(CLK_AHB_BIST, "ahb-bist", "ahb", 0x60, 7) CCU_GATE(CLK_AHB_MMC0, "ahb-mmc0", "ahb", 0x60, 8) CCU_GATE(CLK_AHB_MMC1, "ahb-mmc1", "ahb", 0x60, 9) CCU_GATE(CLK_AHB_MMC2, "ahb-mmc2", "ahb", 0x60, 10) CCU_GATE(CLK_AHB_MMC3, "ahb-mmc3", "ahb", 0x60, 11) CCU_GATE(CLK_AHB_MS, "ahb-ms", "ahb", 0x60, 12) CCU_GATE(CLK_AHB_NAND, "ahb-nand", "ahb", 0x60, 13) CCU_GATE(CLK_AHB_SDRAM, "ahb-sdram", "ahb", 0x60, 14) CCU_GATE(CLK_AHB_ACE, "ahb-ace", "ahb", 0x60, 16) CCU_GATE(CLK_AHB_EMAC, "ahb-emac", "ahb", 0x60, 17) CCU_GATE(CLK_AHB_TS, "ahb-ts", "ahb", 0x60, 18) CCU_GATE(CLK_AHB_SPI0, "ahb-spi0", "ahb", 0x60, 20) CCU_GATE(CLK_AHB_SPI1, "ahb-spi1", "ahb", 0x60, 21) CCU_GATE(CLK_AHB_SPI2, "ahb-spi2", "ahb", 0x60, 22) CCU_GATE(CLK_AHB_SPI3, "ahb-spi3", "ahb", 0x60, 23) CCU_GATE(CLK_AHB_SATA, "ahb-sata", "ahb", 0x60, 25) CCU_GATE(CLK_AHB_VE, "ahb-ve", "ahb", 0x64, 0) CCU_GATE(CLK_AHB_TVD, "ahb-tvd", "ahb", 0x64, 1) CCU_GATE(CLK_AHB_TVE0, "ahb-tve0", "ahb", 0x64, 2) CCU_GATE(CLK_AHB_TVE1, "ahb-tve1", "ahb", 0x64, 3) CCU_GATE(CLK_AHB_LCD0, "ahb-lcd0", "ahb", 0x64, 4) CCU_GATE(CLK_AHB_LCD1, "ahb-lcd1", "ahb", 0x64, 5) CCU_GATE(CLK_AHB_CSI0, "ahb-csi0", "ahb", 0x64, 8) CCU_GATE(CLK_AHB_CSI1, "ahb-csi1", "ahb", 0x64, 9) CCU_GATE(CLK_AHB_HDMI1, "ahb-hdmi1", "ahb", 0x64, 10) CCU_GATE(CLK_AHB_HDMI0, "ahb-hdmi0", "ahb", 0x64, 11) CCU_GATE(CLK_AHB_DE_BE0, "ahb-de_be0", "ahb", 0x64, 12) CCU_GATE(CLK_AHB_DE_BE1, "ahb-de_be1", "ahb", 0x64, 13) CCU_GATE(CLK_AHB_DE_FE0, "ahb-de_fe0", "ahb", 0x64, 14) CCU_GATE(CLK_AHB_DE_FE1, "ahb-de_fe1", "ahb", 0x64, 15) CCU_GATE(CLK_AHB_GMAC, "ahb-gmac", "ahb", 0x64, 17) CCU_GATE(CLK_AHB_MP, "ahb-mp", "ahb", 0x64, 18) CCU_GATE(CLK_AHB_GPU, "ahb-gpu", "ahb", 0x64, 20) CCU_GATE(CLK_APB0_CODEC, "apb0-codec", "apb0", 0x68, 0) CCU_GATE(CLK_APB0_SPDIF, "apb0-spdif", "apb0", 0x68, 1) CCU_GATE(CLK_APB0_AC97, "apb0-ac97", "apb0", 0x68, 2) CCU_GATE(CLK_APB0_I2S0, "apb0-i2s0", "apb0", 0x68, 3) CCU_GATE(CLK_APB0_I2S1, "apb0-i2s1", "apb0", 0x68, 4) CCU_GATE(CLK_APB0_PIO, "apb0-pi0", "apb0", 0x68, 5) CCU_GATE(CLK_APB0_IR0, "apb0-ir0", "apb0", 0x68, 6) CCU_GATE(CLK_APB0_IR1, "apb0-ir1", "apb0", 0x68, 7) CCU_GATE(CLK_APB0_I2S2, "apb0-i2s2", "apb0",0x68, 8) CCU_GATE(CLK_APB0_KEYPAD, "apb0-keypad", "apb0", 0x68, 10) CCU_GATE(CLK_APB1_I2C0, "apb1-i2c0", "apb1", 0x6c, 0) CCU_GATE(CLK_APB1_I2C1, "apb1-i2c1", "apb1",0x6c, 1) CCU_GATE(CLK_APB1_I2C2, "apb1-i2c2", "apb1",0x6c, 2) CCU_GATE(CLK_APB1_I2C3, "apb1-i2c3", "apb1",0x6c, 3) CCU_GATE(CLK_APB1_CAN, "apb1-can", "apb1",0x6c, 4) CCU_GATE(CLK_APB1_SCR, "apb1-scr", "apb1",0x6c, 5) CCU_GATE(CLK_APB1_PS20, "apb1-ps20", "apb1",0x6c, 6) CCU_GATE(CLK_APB1_PS21, "apb1-ps21", "apb1",0x6c, 7) CCU_GATE(CLK_APB1_I2C4, "apb1-i2c4", "apb1", 0x6c, 15) CCU_GATE(CLK_APB1_UART0, "apb1-uart0", "apb1",0x6c, 16) CCU_GATE(CLK_APB1_UART1, "apb1-uart1", "apb1",0x6c, 17) CCU_GATE(CLK_APB1_UART2, "apb1-uart2", "apb1",0x6c, 18) CCU_GATE(CLK_APB1_UART3, "apb1-uart3", "apb1",0x6c, 19) CCU_GATE(CLK_APB1_UART4, "apb1-uart4", "apb1",0x6c, 20) CCU_GATE(CLK_APB1_UART5, "apb1-uart5", "apb1",0x6c, 21) CCU_GATE(CLK_APB1_UART6, "apb1-uart6", "apb1",0x6c, 22) CCU_GATE(CLK_APB1_UART7, "apb1-uart7", "apb1",0x6c, 23) CCU_GATE(CLK_USB_OHCI0, "usb-ohci0", "ahb", 0xcc, 6) CCU_GATE(CLK_USB_OHCI1, "usb-ohci1", "ahb", 0xcc, 7) CCU_GATE(CLK_USB_PHY, "usb-phy", "ahb", 0xcc, 8) CCU_GATE(CLK_DRAM_VE, "dram-ve", "pll_ddr", 0x100, 0) CCU_GATE(CLK_DRAM_CSI0, "dram-csi0", "pll_ddr", 0x100, 1) CCU_GATE(CLK_DRAM_CSI1, "dram-csi1", "pll_ddr", 0x100, 2) CCU_GATE(CLK_DRAM_TS, "dram-ts", "pll_ddr", 0x100, 3) CCU_GATE(CLK_DRAM_TVD, "dram-tvd", "pll_ddr", 0x100, 4) CCU_GATE(CLK_DRAM_TVE0, "dram-tve0", "pll_ddr", 0x100, 5) CCU_GATE(CLK_DRAM_TVE1, "dram-tve1", "pll_ddr", 0x100, 6) CCU_GATE(CLK_DRAM_OUT, "dram-out", "pll_ddr", 0x100, 15) CCU_GATE(CLK_DRAM_DE_FE1, "dram-de_fe1", "pll_ddr", 0x100, 24) CCU_GATE(CLK_DRAM_DE_FE0, "dram-de_fe0", "pll_ddr", 0x100, 25) CCU_GATE(CLK_DRAM_DE_BE0, "dram-de_be0", "pll_ddr", 0x100, 26) CCU_GATE(CLK_DRAM_DE_BE1, "dram-de_be1", "pll_ddr", 0x100, 27) CCU_GATE(CLK_DRAM_MP, "dram-de_mp", "pll_ddr", 0x100, 28) CCU_GATE(CLK_DRAM_ACE, "dram-ace", "pll_ddr", 0x100, 29) }; static const char *pll_parents[] = {"osc24M"}; NKMP_CLK(pll_core_clk, CLK_PLL_CORE, /* id */ "pll_core", pll_parents, /* name, parents */ 0x00, /* offset */ 8, 5, 0, AW_CLK_FACTOR_ZERO_IS_ONE, /* n factor */ 4, 2, 0, 0, /* k factor */ 0, 2, 0, 0, /* m factor */ 16, 2, 0, AW_CLK_FACTOR_POWER_OF_TWO, /* p factor */ 31, /* gate */ 0, 0, /* lock */ AW_CLK_HAS_GATE); /* flags */ FRAC_CLK(pll_video0_clk, CLK_PLL_VIDEO0, /* id */ "pll_video0", pll_parents, /* name, parents */ 0x10, /* offset */ 0, 7, 0, 0, /* n factor */ 0, 0, 1, AW_CLK_FACTOR_FIXED, /* m factor (fake) */ 31, 0, 0, /* gate, lock, lock retries */ AW_CLK_HAS_GATE, /* flags */ 270000000, 297000000, /* freq0, freq1 */ 15, 14); /* mode sel, freq sel */ static const char *pll_video0_2x_parents[] = {"pll_video0"}; FIXED_CLK(pll_video0_2x_clk, CLK_PLL_VIDEO0_2X, /* id */ "pll_video0-2x", pll_video0_2x_parents, /* name, parents */ 0, /* freq */ 2, /* mult */ 1, /* div */ 0); /* flags */ FRAC_CLK(pll_video1_clk, CLK_PLL_VIDEO1, /* id */ "pll_video1", pll_parents, /* name, parents */ 0x30, /* offset */ 0, 7, 0, 0, /* n factor */ 0, 0, 1, AW_CLK_FACTOR_FIXED, /* m factor (fake) */ 31, 0, 0, /* gate, lock, lock retries */ AW_CLK_HAS_GATE, /* flags */ 270000000, 297000000, /* freq0, freq1 */ 15, 14); /* mode sel, freq sel */ static const char *pll_video1_2x_parents[] = {"pll_video1"}; FIXED_CLK(pll_video1_2x_clk, CLK_PLL_VIDEO1_2X, /* id */ "pll_video1-2x", pll_video1_2x_parents, /* name, parents */ 0, /* freq */ 2, /* mult */ 1, /* div */ 0); /* flags */ static const char *cpu_parents[] = {"osc32k", "osc24M", "pll_core", "pll_periph"}; static const char *axi_parents[] = {"cpu"}; static const char *ahb_parents[] = {"axi", "pll_periph", "pll6"}; static const char *apb0_parents[] = {"ahb"}; static const char *apb1_parents[] = {"osc24M", "pll_periph", "osc32k"}; MUX_CLK(cpu_clk, CLK_CPU, /* id */ "cpu", cpu_parents, /* name, parents */ 0x54, 16, 2); /* offset, shift, width */ NM_CLK(axi_clk, CLK_AXI, /* id */ "axi", axi_parents, /* name, parents */ 0x54, /* offset */ 0, 0, 1, AW_CLK_FACTOR_FIXED, /* n factor (fake) */ 0, 2, 0, 0, /* m factor */ 0, 0, /* mux */ 0, /* gate */ 0); /* flags */ NM_CLK(ahb_clk, CLK_AHB, /* id */ "ahb", ahb_parents, /* name, parents */ 0x54, /* offset */ 0, 0, 1, AW_CLK_FACTOR_FIXED, /* n factor (fake) */ 4, 2, 0, AW_CLK_FACTOR_POWER_OF_TWO, /* m factor */ 6, 2, /* mux */ 0, /* gate */ AW_CLK_HAS_MUX); /* flags */ NM_CLK(apb0_clk, CLK_APB0, /* id */ "apb0", apb0_parents, /* name, parents */ 0x54, /* offset */ 0, 0, 1, AW_CLK_FACTOR_FIXED, /* n factor (fake) */ 8, 2, 0, AW_CLK_FACTOR_POWER_OF_TWO | AW_CLK_FACTOR_ZERO_IS_ONE, /* m factor */ 0, 0, /* mux */ 0, /* gate */ 0); /* flags */ NM_CLK(apb1_clk, CLK_APB1, /* id */ "apb1", apb1_parents, /* name, parents */ 0x58, /* offset */ 16, 2, 0, AW_CLK_FACTOR_POWER_OF_TWO, /* n factor */ 0, 5, 0, 0, /* m factor */ 24, 2, /* mux */ 0, /* gate */ AW_CLK_HAS_MUX); /* flags */ NKMP_CLK(pll_ddr_other_clk, CLK_PLL_DDR_OTHER, /* id */ "pll_ddr_other", pll_parents, /* name, parents */ 0x20, /* offset */ 8, 5, 0, AW_CLK_FACTOR_ZERO_BASED, /* n factor */ 4, 2, 0, 0, /* k factor */ 0, 0, 1, AW_CLK_FACTOR_FIXED, /* m factor (fake) */ 2, 2, 0, AW_CLK_FACTOR_POWER_OF_TWO, /* p factor */ 31, /* gate */ 0, 0, /* lock */ AW_CLK_HAS_GATE); /* flags */ NKMP_CLK(pll_ddr_clk, CLK_PLL_DDR, /* id */ "pll_ddr", pll_parents, /* name, parents */ 0x20, /* offset */ 8, 5, 0, AW_CLK_FACTOR_ZERO_BASED, /* n factor */ 4, 2, 0, 0, /* k factor */ 0, 2, 0, 0, /* m factor */ 0, 0, 1, AW_CLK_FACTOR_FIXED, /* p factor (fake) */ 31, /* gate */ 0, 0, /* lock */ AW_CLK_HAS_GATE); /* flags */ NKMP_CLK(pll6_clk, CLK_PLL6, /* id */ "pll6", pll_parents, /* name, parents */ 0x28, /* offset */ 8, 5, 0, AW_CLK_FACTOR_ZERO_BASED, /* n factor */ 4, 2, 0, 0, /* k factor */ 0, 0, 1, AW_CLK_FACTOR_FIXED, /* m factor (fake) */ 0, 0, 1, AW_CLK_FACTOR_FIXED, /* p factor (fake) */ 31, /* gate */ 0, 0, /* lock */ AW_CLK_HAS_GATE); /* flags */ static const char *pll6_parents[] = {"pll6"}; FIXED_CLK(pll_periph_clk, CLK_PLL_PERIPH, /* id */ "pll_periph", pll6_parents, /* name, parents */ 0, /* freq */ 1, /* mult */ 2, /* div */ 0); /* flags */ NKMP_CLK(pll_periph_sata_clk, CLK_PLL_SATA, /* id */ "pll_periph_sata", pll6_parents, /* name, parents */ 0x28, /* offset */ 0, 0, 1, AW_CLK_FACTOR_FIXED, /* n factor (fake) */ 0, 0, 1, AW_CLK_FACTOR_FIXED, /* k factor (fake) */ 0, 2, 0, 0, /* m factor */ 0, 0, 6, AW_CLK_FACTOR_FIXED, /* p factor (fake, 6) */ 14, /* gate */ 0, 0, /* lock */ AW_CLK_HAS_GATE); /* flags */ static const char *mod_parents[] = {"osc24M", "pll_periph", "pll_ddr_other"}; NM_CLK(nand_clk, CLK_NAND, /* id */ "nand", mod_parents, /* name, parents */ 0x80, /* offset */ 16, 2, 0, AW_CLK_FACTOR_POWER_OF_TWO, /* n factor */ 0, 4, 0, 0, /* m factor */ 24, 2, /* mux */ 31, /* gate */ AW_CLK_HAS_MUX | AW_CLK_HAS_GATE); /* flags */ NM_CLK(ms_clk, CLK_MS, /* id */ "ms", mod_parents, /* name, parents */ 0x84, /* offset */ 16, 2, 0, AW_CLK_FACTOR_POWER_OF_TWO, /* n factor */ 0, 4, 0, 0, /* m factor */ 24, 2, /* mux */ 31, /* gate */ AW_CLK_HAS_MUX | AW_CLK_HAS_GATE); /* flags */ NM_CLK(mmc0_clk, CLK_MMC0, /* id */ "mmc0", mod_parents, /* name, parents */ 0x88, /* offset */ 16, 2, 0, AW_CLK_FACTOR_POWER_OF_TWO, /* n factor */ 0, 4, 0, 0, /* m factor */ 24, 2, /* mux */ 31, /* gate */ AW_CLK_HAS_MUX | AW_CLK_HAS_GATE | AW_CLK_REPARENT); /* flags */ NM_CLK(mmc1_clk, CLK_MMC1, /* id */ "mmc1", mod_parents, /* name, parents */ 0x8c, /* offset */ 16, 2, 0, AW_CLK_FACTOR_POWER_OF_TWO, /* n factor */ 0, 4, 0, 0, /* m factor */ 24, 2, /* mux */ 31, /* gate */ AW_CLK_HAS_MUX | AW_CLK_HAS_GATE | AW_CLK_REPARENT); /* flags */ NM_CLK(mmc2_clk, CLK_MMC2, /* id */ "mmc2", mod_parents, /* name, parents */ 0x90, /* offset */ 16, 2, 0, AW_CLK_FACTOR_POWER_OF_TWO, /* n factor */ 0, 4, 0, 0, /* m factor */ 24, 2, /* mux */ 31, /* gate */ AW_CLK_HAS_MUX | AW_CLK_HAS_GATE | AW_CLK_REPARENT); /* flags */ NM_CLK(mmc3_clk, CLK_MMC3, /* id */ "mmc3", mod_parents, /* name, parents */ 0x94, /* offset */ 16, 2, 0, AW_CLK_FACTOR_POWER_OF_TWO, /* n factor */ 0, 4, 0, 0, /* m factor */ 24, 2, /* mux */ 31, /* gate */ AW_CLK_HAS_MUX | AW_CLK_HAS_GATE | AW_CLK_REPARENT); /* flags */ NM_CLK(ts_clk, CLK_TS, /* id */ "ts", mod_parents, /* name, parents */ 0x94, /* offset */ 16, 2, 0, AW_CLK_FACTOR_POWER_OF_TWO, /* n factor */ 0, 4, 0, 0, /* m factor */ 24, 2, /* mux */ 31, /* gate */ AW_CLK_HAS_MUX | AW_CLK_HAS_GATE); /* flags */ NM_CLK(ss_clk, CLK_SS, /* id */ "ss", mod_parents, /* name, parents */ 0x9c, /* offset */ 16, 2, 0, AW_CLK_FACTOR_POWER_OF_TWO, /* n factor */ 0, 4, 0, 0, /* m factor */ 24, 2, /* mux */ 31, /* gate */ AW_CLK_HAS_MUX | AW_CLK_HAS_GATE); /* flags */ NM_CLK(spi0_clk, CLK_SPI0, /* id */ "spi0", mod_parents, /* name, parents */ 0xa0, /* offset */ 16, 2, 0, AW_CLK_FACTOR_POWER_OF_TWO, /* n factor */ 0, 4, 0, 0, /* m factor */ 24, 2, /* mux */ 31, /* gate */ AW_CLK_HAS_MUX | AW_CLK_HAS_GATE); /* flags */ NM_CLK(spi1_clk, CLK_SPI1, /* id */ "spi1", mod_parents, /* name, parents */ 0xa4, /* offset */ 16, 2, 0, AW_CLK_FACTOR_POWER_OF_TWO, /* n factor */ 0, 4, 0, 0, /* m factor */ 24, 2, /* mux */ 31, /* gate */ AW_CLK_HAS_MUX | AW_CLK_HAS_GATE); /* flags */ NM_CLK(spi2_clk, CLK_SPI2, /* id */ "spi2", mod_parents, /* name, parents */ 0xa8, /* offset */ 16, 2, 0, AW_CLK_FACTOR_POWER_OF_TWO, /* n factor */ 0, 4, 0, 0, /* m factor */ 24, 2, /* mux */ 31, /* gate */ AW_CLK_HAS_MUX | AW_CLK_HAS_GATE); /* flags */ /* MISSING CLK_PATA */ NM_CLK(ir0_clk, CLK_IR0, /* id */ "ir0", mod_parents, /* name, parents */ 0xb0, /* offset */ 16, 2, 0, AW_CLK_FACTOR_POWER_OF_TWO, /* n factor */ 0, 4, 0, 0, /* m factor */ 24, 2, /* mux */ 31, /* gate */ AW_CLK_HAS_MUX | AW_CLK_HAS_GATE); /* flags */ NM_CLK(ir1_clk, CLK_IR1, /* id */ "ir1", mod_parents, /* name, parents */ 0xb4, /* offset */ 16, 2, 0, AW_CLK_FACTOR_POWER_OF_TWO, /* n factor */ 0, 4, 0, 0, /* m factor */ 24, 2, /* mux */ 31, /* gate */ AW_CLK_HAS_MUX | AW_CLK_HAS_GATE); /* flags */ /* MISSING CLK_I2S0, CLK_AC97, CLK_SPDIF */ static const char *keypad_parents[] = {"osc24M", "osc24M", "osc32k"}; NM_CLK(keypad_clk, CLK_KEYPAD, /* id */ "keypad", keypad_parents, /* name, parents */ 0xc4, /* offset */ 16, 2, 0, AW_CLK_FACTOR_POWER_OF_TWO, /* n factor */ 0, 5, 0, 0, /* m factor */ 24, 2, /* mux */ 31, /* gate */ AW_CLK_HAS_MUX | AW_CLK_HAS_GATE); /* flags */ static const char *sata_parents[] = {"pll_periph_sata", "osc32k"}; NM_CLK(sata_clk, CLK_SATA, /* id */ "sata", sata_parents, /* name, parents */ 0xc8, /* offset */ 0, 0, 1, AW_CLK_FACTOR_FIXED, /* n factor (fake) */ 0, 0, 1, AW_CLK_FACTOR_FIXED, /* m factor (fake) */ 24, 1, /* mux */ 31, /* gate */ AW_CLK_HAS_MUX | AW_CLK_HAS_GATE); /* flags */ NM_CLK(spi3_clk, CLK_SPI3, /* id */ "spi3", mod_parents, /* name, parents */ 0xd4, /* offset */ 16, 2, 0, AW_CLK_FACTOR_POWER_OF_TWO, /* n factor */ 0, 4, 0, 0, /* m factor */ 24, 2, /* mux */ 31, /* gate */ AW_CLK_HAS_MUX | AW_CLK_HAS_GATE); /* flags */ /* MISSING CLK_I2S1, CLK_I2S2, DE Clocks */ static struct aw_ccung_clk a10_ccu_clks[] = { { .type = AW_CLK_NKMP, .clk.nkmp = &pll_core_clk}, { .type = AW_CLK_NKMP, .clk.nkmp = &pll_ddr_other_clk}, { .type = AW_CLK_NKMP, .clk.nkmp = &pll_ddr_clk}, { .type = AW_CLK_NKMP, .clk.nkmp = &pll6_clk}, { .type = AW_CLK_NKMP, .clk.nkmp = &pll_periph_sata_clk}, { .type = AW_CLK_NM, .clk.nm = &axi_clk}, { .type = AW_CLK_NM, .clk.nm = &ahb_clk}, { .type = AW_CLK_NM, .clk.nm = &apb0_clk}, { .type = AW_CLK_NM, .clk.nm = &apb1_clk}, { .type = AW_CLK_FRAC, .clk.frac = &pll_video0_clk}, { .type = AW_CLK_FRAC, .clk.frac = &pll_video1_clk}, { .type = AW_CLK_NM, .clk.nm = &nand_clk}, { .type = AW_CLK_NM, .clk.nm = &ms_clk}, { .type = AW_CLK_NM, .clk.nm = &mmc0_clk}, { .type = AW_CLK_NM, .clk.nm = &mmc1_clk}, { .type = AW_CLK_NM, .clk.nm = &mmc2_clk}, { .type = AW_CLK_NM, .clk.nm = &mmc3_clk}, { .type = AW_CLK_NM, .clk.nm = &ts_clk}, { .type = AW_CLK_NM, .clk.nm = &ss_clk}, { .type = AW_CLK_NM, .clk.nm = &spi0_clk}, { .type = AW_CLK_NM, .clk.nm = &spi1_clk}, { .type = AW_CLK_NM, .clk.nm = &spi2_clk}, { .type = AW_CLK_NM, .clk.nm = &ir0_clk}, { .type = AW_CLK_NM, .clk.nm = &ir1_clk}, { .type = AW_CLK_NM, .clk.nm = &keypad_clk}, { .type = AW_CLK_NM, .clk.nm = &sata_clk}, { .type = AW_CLK_NM, .clk.nm = &spi3_clk}, { .type = AW_CLK_MUX, .clk.mux = &cpu_clk}, { .type = AW_CLK_FIXED, .clk.fixed = &pll_periph_clk}, { .type = AW_CLK_FIXED, .clk.fixed = &pll_video0_2x_clk}, { .type = AW_CLK_FIXED, .clk.fixed = &pll_video1_2x_clk}, }; static struct aw_clk_init a10_init_clks[] = { }; static struct ofw_compat_data compat_data[] = { #if defined(SOC_ALLWINNER_A10) { "allwinner,sun4i-a10-ccu", 1 }, #endif #if defined(SOC_ALLWINNER_A20) { "allwinner,sun7i-a20-ccu", 1 }, #endif { NULL, 0}, }; static int ccu_a10_probe(device_t dev) { if (!ofw_bus_status_okay(dev)) return (ENXIO); if (ofw_bus_search_compatible(dev, compat_data)->ocd_data == 0) return (ENXIO); device_set_desc(dev, "Allwinner A10/A20 Clock Control Unit NG"); return (BUS_PROBE_DEFAULT); } static int ccu_a10_attach(device_t dev) { struct aw_ccung_softc *sc; sc = device_get_softc(dev); sc->resets = a10_ccu_resets; sc->nresets = nitems(a10_ccu_resets); sc->gates = a10_ccu_gates; sc->ngates = nitems(a10_ccu_gates); sc->clks = a10_ccu_clks; sc->nclks = nitems(a10_ccu_clks); sc->clk_init = a10_init_clks; sc->n_clk_init = nitems(a10_init_clks); return (aw_ccung_attach(dev)); } static device_method_t ccu_a10ng_methods[] = { /* Device interface */ DEVMETHOD(device_probe, ccu_a10_probe), DEVMETHOD(device_attach, ccu_a10_attach), DEVMETHOD_END }; static devclass_t ccu_a10ng_devclass; DEFINE_CLASS_1(ccu_a10ng, ccu_a10ng_driver, ccu_a10ng_methods, sizeof(struct aw_ccung_softc), aw_ccung_driver); EARLY_DRIVER_MODULE(ccu_a10ng, simplebus, ccu_a10ng_driver, - ccu_a10ng_devclass, 0, 0, BUS_PASS_BUS + BUS_PASS_ORDER_MIDDLE); + ccu_a10ng_devclass, 0, 0, BUS_PASS_RESOURCE + BUS_PASS_ORDER_MIDDLE); Index: head/sys/arm/allwinner/clkng/ccu_a13.c =================================================================== --- head/sys/arm/allwinner/clkng/ccu_a13.c (revision 350841) +++ head/sys/arm/allwinner/clkng/ccu_a13.c (revision 350842) @@ -1,571 +1,571 @@ /*- * SPDX-License-Identifier: BSD-2-Clause-FreeBSD * * Copyright (c) 2017,2018 Emmanuel Vadot * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. * * $FreeBSD$ */ #include __FBSDID("$FreeBSD$"); #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include /* Non-exported clocks */ #define CLK_PLL_CORE 2 #define CLK_PLL_AUDIO_BASE 3 #define CLK_PLL_AUDIO 4 #define CLK_PLL_AUDIO_2X 5 #define CLK_PLL_AUDIO_4X 6 #define CLK_PLL_AUDIO_8X 7 #define CLK_PLL_VIDEO0 8 #define CLK_PLL_VE 10 #define CLK_PLL_DDR_BASE 11 #define CLK_PLL_DDR 12 #define CLK_PLL_DDR_OTHER 13 #define CLK_PLL_PERIPH 14 #define CLK_PLL_VIDEO1 15 #define CLK_AXI 18 #define CLK_AHB 19 #define CLK_APB0 20 #define CLK_APB1 21 #define CLK_DRAM_AXI 22 #define CLK_TCON_CH1_SCLK 91 #define CLK_MBUS 99 static struct aw_ccung_reset a13_ccu_resets[] = { CCU_RESET(RST_USB_PHY0, 0xcc, 0) CCU_RESET(RST_USB_PHY1, 0xcc, 1) CCU_RESET(RST_GPS, 0xd0, 30) CCU_RESET(RST_DE_BE, 0x104, 30) CCU_RESET(RST_DE_FE, 0x10c, 30) CCU_RESET(RST_TVE, 0x118, 29) CCU_RESET(RST_LCD, 0x118, 30) CCU_RESET(RST_CSI, 0x134, 30) CCU_RESET(RST_VE, 0x13c, 0) CCU_RESET(RST_GPU, 0x154, 30) CCU_RESET(RST_IEP, 0x160, 30) }; static struct aw_ccung_gate a13_ccu_gates[] = { CCU_GATE(CLK_HOSC, "hosc", "osc24M", 0x50, 0) CCU_GATE(CLK_DRAM_AXI, "axi-dram", "axi", 0x5c, 0) CCU_GATE(CLK_AHB_OTG, "ahb-otg", "ahb", 0x60, 0) CCU_GATE(CLK_AHB_EHCI, "ahb-ehci", "ahb", 0x60, 1) CCU_GATE(CLK_AHB_OHCI, "ahb-ohci", "ahb", 0x60, 2) CCU_GATE(CLK_AHB_SS, "ahb-ss", "ahb", 0x60, 5) CCU_GATE(CLK_AHB_DMA, "ahb-dma", "ahb", 0x60, 6) CCU_GATE(CLK_AHB_BIST, "ahb-bist", "ahb", 0x60, 7) CCU_GATE(CLK_AHB_MMC0, "ahb-mmc0", "ahb", 0x60, 8) CCU_GATE(CLK_AHB_MMC1, "ahb-mmc1", "ahb", 0x60, 9) CCU_GATE(CLK_AHB_MMC2, "ahb-mmc2", "ahb", 0x60, 10) CCU_GATE(CLK_AHB_NAND, "ahb-nand", "ahb", 0x60, 13) CCU_GATE(CLK_AHB_SDRAM, "ahb-sdram", "ahb", 0x60, 14) CCU_GATE(CLK_AHB_SPI0, "ahb-spi0", "ahb", 0x60, 20) CCU_GATE(CLK_AHB_SPI1, "ahb-spi1", "ahb", 0x60, 21) CCU_GATE(CLK_AHB_SPI2, "ahb-spi2", "ahb", 0x60, 22) CCU_GATE(CLK_AHB_GPS, "ahb-gps", "ahb", 0x60, 26) CCU_GATE(CLK_AHB_HSTIMER, "ahb-hstimer", "ahb", 0x60, 28) CCU_GATE(CLK_AHB_VE, "ahb-ve", "ahb", 0x64, 0) CCU_GATE(CLK_AHB_LCD, "ahb-lcd", "ahb", 0x64, 4) CCU_GATE(CLK_AHB_CSI, "ahb-csi", "ahb", 0x64, 8) CCU_GATE(CLK_AHB_DE_BE, "ahb-de-be", "ahb", 0x64, 12) CCU_GATE(CLK_AHB_DE_FE, "ahb-de-fe", "ahb", 0x64, 14) CCU_GATE(CLK_AHB_IEP, "ahb-iep", "ahb", 0x64, 19) CCU_GATE(CLK_AHB_GPU, "ahb-gpu", "ahb", 0x64, 20) CCU_GATE(CLK_APB0_CODEC, "apb0-codec", "apb0", 0x68, 0) CCU_GATE(CLK_APB0_PIO, "apb0-pio", "apb0", 0x68, 5) CCU_GATE(CLK_APB0_IR, "apb0-ir", "apb0", 0x68, 6) CCU_GATE(CLK_APB1_I2C0, "apb1-i2c0", "apb1", 0x6c, 0) CCU_GATE(CLK_APB1_I2C1, "apb1-i2c1", "apb1", 0x6c, 1) CCU_GATE(CLK_APB1_I2C2, "apb1-i2c2", "apb1", 0x6c, 2) CCU_GATE(CLK_APB1_UART1, "apb1-uart1", "apb1", 0x6c, 17) CCU_GATE(CLK_APB1_UART3, "apb1-uart3", "apb1", 0x6c, 19) CCU_GATE(CLK_DRAM_VE, "dram-ve", "pll-ddr", 0x100, 0) CCU_GATE(CLK_DRAM_CSI, "dram-csi", "pll-ddr", 0x100, 1) CCU_GATE(CLK_DRAM_DE_FE, "dram-de-fe", "pll-ddr", 0x100, 25) CCU_GATE(CLK_DRAM_DE_BE, "dram-de-be", "pll-ddr", 0x100, 26) CCU_GATE(CLK_DRAM_ACE, "dram-ace", "pll-ddr", 0x100, 29) CCU_GATE(CLK_DRAM_IEP, "dram-iep", "pll-ddr", 0x100, 31) CCU_GATE(CLK_CODEC, "codec", "pll-audio", 0x140, 31) CCU_GATE(CLK_AVS, "avs", "hosc", 0x144, 31) }; static const char *pll_parents[] = {"hosc"}; static struct aw_clk_nkmp_def pll_core = { .clkdef = { .id = CLK_PLL_CORE, .name = "pll-core", .parent_names = pll_parents, .parent_cnt = nitems(pll_parents), }, .offset = 0x00, .n = {.shift = 8, .width = 5}, .k = {.shift = 4, .width = 2}, .m = {.shift = 0, .width = 2}, .p = {.shift = 16, .width = 2}, .gate_shift = 31, .flags = AW_CLK_HAS_GATE, }; /* * We only implement pll-audio for now * For pll-audio-2/4/8 x we need a way to change the frequency * of the parent clocks */ static struct aw_clk_nkmp_def pll_audio = { .clkdef = { .id = CLK_PLL_AUDIO, .name = "pll-audio", .parent_names = pll_parents, .parent_cnt = nitems(pll_parents), }, .offset = 0x08, .n = {.shift = 8, .width = 7}, .k = {.value = 1, .flags = AW_CLK_FACTOR_FIXED}, .m = {.shift = 0, .width = 5}, .p = {.shift = 26, .width = 4}, .gate_shift = 31, .flags = AW_CLK_HAS_GATE, }; /* Missing PLL3-Video */ /* Missing PLL4-VE */ static struct aw_clk_nkmp_def pll_ddr_base = { .clkdef = { .id = CLK_PLL_DDR_BASE, .name = "pll-ddr-base", .parent_names = pll_parents, .parent_cnt = nitems(pll_parents), }, .offset = 0x20, .n = {.shift = 8, .width = 5}, .k = {.shift = 4, .width = 2}, .m = {.value = 1, .flags = AW_CLK_FACTOR_FIXED}, .p = {.value = 1, .flags = AW_CLK_FACTOR_FIXED}, .gate_shift = 31, .flags = AW_CLK_HAS_GATE, }; static const char *pll_ddr_parents[] = {"pll-ddr-base"}; static struct clk_div_def pll_ddr = { .clkdef = { .id = CLK_PLL_DDR, .name = "pll-ddr", .parent_names = pll_ddr_parents, .parent_cnt = nitems(pll_ddr_parents), }, .offset = 0x20, .i_shift = 0, .i_width = 2, }; static const char *pll_ddr_other_parents[] = {"pll-ddr-base"}; static struct clk_div_def pll_ddr_other = { .clkdef = { .id = CLK_PLL_DDR_OTHER, .name = "pll-ddr-other", .parent_names = pll_ddr_other_parents, .parent_cnt = nitems(pll_ddr_other_parents), }, .offset = 0x20, .i_shift = 16, .i_width = 2, }; static struct aw_clk_nkmp_def pll_periph = { .clkdef = { .id = CLK_PLL_PERIPH, .name = "pll-periph", .parent_names = pll_parents, .parent_cnt = nitems(pll_parents), }, .offset = 0x28, .n = {.shift = 8, .width = 5}, .k = {.shift = 4, .width = 2}, .m = {.shift = 0, .width = 2}, .p = {.value = 2, .flags = AW_CLK_FACTOR_FIXED}, .gate_shift = 31, .flags = AW_CLK_HAS_GATE, }; /* Missing PLL7-VIDEO1 */ static const char *cpu_parents[] = {"osc32k", "hosc", "pll-core", "pll-periph"}; static struct aw_clk_prediv_mux_def cpu_clk = { .clkdef = { .id = CLK_CPU, .name = "cpu", .parent_names = cpu_parents, .parent_cnt = nitems(cpu_parents), }, .offset = 0x54, .mux_shift = 16, .mux_width = 2, .prediv = { .value = 6, .flags = AW_CLK_FACTOR_FIXED, .cond_shift = 16, .cond_width = 2, .cond_value = 3, }, }; static const char *axi_parents[] = {"cpu"}; static struct clk_div_def axi_clk = { .clkdef = { .id = CLK_AXI, .name = "axi", .parent_names = axi_parents, .parent_cnt = nitems(axi_parents), }, .offset = 0x50, .i_shift = 0, .i_width = 2, }; static const char *ahb_parents[] = {"axi", "cpu", "pll-periph"}; static struct aw_clk_prediv_mux_def ahb_clk = { .clkdef = { .id = CLK_AHB, .name = "ahb", .parent_names = ahb_parents, .parent_cnt = nitems(ahb_parents), }, .offset = 0x54, .mux_shift = 6, .mux_width = 2, .div = { .shift = 4, .width = 2, .flags = AW_CLK_FACTOR_POWER_OF_TWO }, .prediv = { .value = 2, .flags = AW_CLK_FACTOR_FIXED, .cond_shift = 6, .cond_width = 2, .cond_value = 2, }, }; static const char *apb0_parents[] = {"ahb"}; static struct clk_div_table apb0_div_table[] = { { .value = 0, .divider = 2, }, { .value = 1, .divider = 2, }, { .value = 2, .divider = 4, }, { .value = 3, .divider = 8, }, { }, }; static struct clk_div_def apb0_clk = { .clkdef = { .id = CLK_APB0, .name = "apb0", .parent_names = apb0_parents, .parent_cnt = nitems(apb0_parents), }, .offset = 0x54, .i_shift = 8, .i_width = 2, .div_flags = CLK_DIV_WITH_TABLE, .div_table = apb0_div_table, }; static const char *apb1_parents[] = {"hosc", "pll-periph", "osc32k"}; static struct aw_clk_nm_def apb1_clk = { .clkdef = { .id = CLK_APB1, .name = "apb1", .parent_names = apb1_parents, .parent_cnt = nitems(apb1_parents), }, .offset = 0x58, .n = {.shift = 16, .width = 2, .flags = AW_CLK_FACTOR_POWER_OF_TWO, }, .m = {.shift = 0, .width = 5}, .mux_shift = 24, .mux_width = 2, .flags = AW_CLK_HAS_MUX, }; static const char *mod_parents[] = {"hosc", "pll-periph", "pll-ddr-other"}; static struct aw_clk_nm_def nand_clk = { .clkdef = { .id = CLK_NAND, .name = "nand", .parent_names = mod_parents, .parent_cnt = nitems(mod_parents), }, .offset = 0x80, .n = {.shift = 16, .width = 2, .flags = AW_CLK_FACTOR_POWER_OF_TWO, }, .m = {.shift = 0, .width = 4}, .mux_shift = 24, .mux_width = 2, .gate_shift = 31, .flags = AW_CLK_HAS_MUX | AW_CLK_HAS_GATE | AW_CLK_REPARENT }; static struct aw_clk_nm_def mmc0_clk = { .clkdef = { .id = CLK_MMC0, .name = "mmc0", .parent_names = mod_parents, .parent_cnt = nitems(mod_parents), }, .offset = 0x88, .n = {.shift = 16, .width = 2, .flags = AW_CLK_FACTOR_POWER_OF_TWO, }, .m = {.shift = 0, .width = 4}, .mux_shift = 24, .mux_width = 2, .gate_shift = 31, .flags = AW_CLK_HAS_MUX | AW_CLK_HAS_GATE | AW_CLK_REPARENT }; static struct aw_clk_nm_def mmc1_clk = { .clkdef = { .id = CLK_MMC1, .name = "mmc1", .parent_names = mod_parents, .parent_cnt = nitems(mod_parents), }, .offset = 0x8C, .n = {.shift = 16, .width = 2, .flags = AW_CLK_FACTOR_POWER_OF_TWO, }, .m = {.shift = 0, .width = 4}, .mux_shift = 24, .mux_width = 2, .gate_shift = 31, .flags = AW_CLK_HAS_MUX | AW_CLK_HAS_GATE | AW_CLK_REPARENT }; static struct aw_clk_nm_def mmc2_clk = { .clkdef = { .id = CLK_MMC2, .name = "mmc2", .parent_names = mod_parents, .parent_cnt = nitems(mod_parents), }, .offset = 0x90, .n = {.shift = 16, .width = 2, .flags = AW_CLK_FACTOR_POWER_OF_TWO, }, .m = {.shift = 0, .width = 4}, .mux_shift = 24, .mux_width = 2, .gate_shift = 31, .flags = AW_CLK_HAS_MUX | AW_CLK_HAS_GATE | AW_CLK_REPARENT }; static struct aw_clk_nm_def ss_clk = { .clkdef = { .id = CLK_SS, .name = "ss", .parent_names = mod_parents, .parent_cnt = nitems(mod_parents), }, .offset = 0x9C, .n = {.shift = 16, .width = 2, .flags = AW_CLK_FACTOR_POWER_OF_TWO, }, .m = {.shift = 0, .width = 4}, .mux_shift = 24, .mux_width = 2, .gate_shift = 31, .flags = AW_CLK_HAS_MUX | AW_CLK_HAS_GATE | AW_CLK_REPARENT }; static struct aw_clk_nm_def spi0_clk = { .clkdef = { .id = CLK_SPI0, .name = "spi0", .parent_names = mod_parents, .parent_cnt = nitems(mod_parents), }, .offset = 0xA0, .n = {.shift = 16, .width = 2, .flags = AW_CLK_FACTOR_POWER_OF_TWO, }, .m = {.shift = 0, .width = 4}, .mux_shift = 24, .mux_width = 2, .gate_shift = 31, .flags = AW_CLK_HAS_MUX | AW_CLK_HAS_GATE | AW_CLK_REPARENT }; static struct aw_clk_nm_def spi1_clk = { .clkdef = { .id = CLK_SPI1, .name = "spi1", .parent_names = mod_parents, .parent_cnt = nitems(mod_parents), }, .offset = 0xA4, .n = {.shift = 16, .width = 2, .flags = AW_CLK_FACTOR_POWER_OF_TWO, }, .m = {.shift = 0, .width = 4}, .mux_shift = 24, .mux_width = 2, .gate_shift = 31, .flags = AW_CLK_HAS_MUX | AW_CLK_HAS_GATE | AW_CLK_REPARENT }; static struct aw_clk_nm_def spi2_clk = { .clkdef = { .id = CLK_SPI2, .name = "spi2", .parent_names = mod_parents, .parent_cnt = nitems(mod_parents), }, .offset = 0xA8, .n = {.shift = 16, .width = 2, .flags = AW_CLK_FACTOR_POWER_OF_TWO, }, .m = {.shift = 0, .width = 4}, .mux_shift = 24, .mux_width = 2, .gate_shift = 31, .flags = AW_CLK_HAS_MUX | AW_CLK_HAS_GATE | AW_CLK_REPARENT }; static struct aw_clk_nm_def ir_clk = { .clkdef = { .id = CLK_IR, .name = "ir", .parent_names = mod_parents, .parent_cnt = nitems(mod_parents), }, .offset = 0xB0, .n = {.shift = 16, .width = 2, .flags = AW_CLK_FACTOR_POWER_OF_TWO, }, .m = {.shift = 0, .width = 4}, .mux_shift = 24, .mux_width = 2, .gate_shift = 31, .flags = AW_CLK_HAS_MUX | AW_CLK_HAS_GATE | AW_CLK_REPARENT }; /* Missing DE-BE clock */ /* Missing DE-FE clock */ /* Missing LCD CH1 clock */ /* Missing CSI clock */ /* Missing VE clock */ /* Clocks list */ static struct aw_ccung_clk a13_ccu_clks[] = { { .type = AW_CLK_NKMP, .clk.nkmp = &pll_core}, { .type = AW_CLK_NKMP, .clk.nkmp = &pll_audio}, { .type = AW_CLK_NKMP, .clk.nkmp = &pll_ddr_base}, { .type = AW_CLK_NKMP, .clk.nkmp = &pll_periph}, { .type = AW_CLK_NM, .clk.nm = &apb1_clk}, { .type = AW_CLK_NM, .clk.nm = &nand_clk}, { .type = AW_CLK_NM, .clk.nm = &mmc0_clk}, { .type = AW_CLK_NM, .clk.nm = &mmc1_clk}, { .type = AW_CLK_NM, .clk.nm = &mmc2_clk}, { .type = AW_CLK_NM, .clk.nm = &ss_clk}, { .type = AW_CLK_NM, .clk.nm = &spi0_clk}, { .type = AW_CLK_NM, .clk.nm = &spi1_clk}, { .type = AW_CLK_NM, .clk.nm = &spi2_clk}, { .type = AW_CLK_NM, .clk.nm = &ir_clk}, { .type = AW_CLK_PREDIV_MUX, .clk.prediv_mux = &cpu_clk}, { .type = AW_CLK_PREDIV_MUX, .clk.prediv_mux = &ahb_clk}, { .type = AW_CLK_DIV, .clk.div = &pll_ddr}, { .type = AW_CLK_DIV, .clk.div = &pll_ddr_other}, { .type = AW_CLK_DIV, .clk.div = &axi_clk}, { .type = AW_CLK_DIV, .clk.div = &apb0_clk}, }; static int ccu_a13_probe(device_t dev) { if (!ofw_bus_status_okay(dev)) return (ENXIO); if (!ofw_bus_is_compatible(dev, "allwinner,sun5i-a13-ccu")) return (ENXIO); device_set_desc(dev, "Allwinner A13 Clock Control Unit NG"); return (BUS_PROBE_DEFAULT); } static int ccu_a13_attach(device_t dev) { struct aw_ccung_softc *sc; sc = device_get_softc(dev); sc->resets = a13_ccu_resets; sc->nresets = nitems(a13_ccu_resets); sc->gates = a13_ccu_gates; sc->ngates = nitems(a13_ccu_gates); sc->clks = a13_ccu_clks; sc->nclks = nitems(a13_ccu_clks); return (aw_ccung_attach(dev)); } static device_method_t ccu_a13ng_methods[] = { /* Device interface */ DEVMETHOD(device_probe, ccu_a13_probe), DEVMETHOD(device_attach, ccu_a13_attach), DEVMETHOD_END }; static devclass_t ccu_a13ng_devclass; DEFINE_CLASS_1(ccu_a13ng, ccu_a13ng_driver, ccu_a13ng_methods, sizeof(struct aw_ccung_softc), aw_ccung_driver); EARLY_DRIVER_MODULE(ccu_a13ng, simplebus, ccu_a13ng_driver, - ccu_a13ng_devclass, 0, 0, BUS_PASS_BUS + BUS_PASS_ORDER_MIDDLE); + ccu_a13ng_devclass, 0, 0, BUS_PASS_RESOURCE + BUS_PASS_ORDER_MIDDLE); Index: head/sys/arm/allwinner/clkng/ccu_a31.c =================================================================== --- head/sys/arm/allwinner/clkng/ccu_a31.c (revision 350841) +++ head/sys/arm/allwinner/clkng/ccu_a31.c (revision 350842) @@ -1,976 +1,976 @@ /*- * SPDX-License-Identifier: BSD-2-Clause-FreeBSD * * Copyright (c) 2017,2018 Emmanuel Vadot * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. * * $FreeBSD$ */ #include __FBSDID("$FreeBSD$"); #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include /* Non-exported clocks */ #define CLK_PLL_CPU 0 #define CLK_PLL_AUDIO_BASE 1 #define CLK_PLL_AUDIO 2 #define CLK_PLL_AUDIO_2X 3 #define CLK_PLL_AUDIO_4X 4 #define CLK_PLL_AUDIO_8X 5 #define CLK_PLL_VIDEO0 6 #define CLK_PLL_VIDEO0_2X 7 #define CLK_PLL_VE 8 #define CLK_PLL_DDR 9 #define CLK_PLL_PERIPH_2X 11 #define CLK_PLL_VIDEO1 12 #define CLK_PLL_VIDEO1_2X 13 #define CLK_PLL_GPU 14 #define CLK_PLL_MIPI 15 #define CLK_PLL9 16 #define CLK_PLL10 17 #define CLK_AXI 19 #define CLK_AHB1 20 #define CLK_APB1 21 #define CLK_APB2 22 #define CLK_MDFS 107 #define CLK_SDRAM0 108 #define CLK_SDRAM1 109 #define CLK_MBUS0 141 #define CLK_MBUS1 142 static struct aw_ccung_reset a31_ccu_resets[] = { CCU_RESET(RST_USB_PHY0, 0xcc, 0) CCU_RESET(RST_USB_PHY1, 0xcc, 1) CCU_RESET(RST_USB_PHY2, 0xcc, 2) CCU_RESET(RST_AHB1_MIPI_DSI, 0x2c0, 1) CCU_RESET(RST_AHB1_SS, 0x2c0, 5) CCU_RESET(RST_AHB1_DMA, 0x2c0, 6) CCU_RESET(RST_AHB1_MMC0, 0x2c0, 8) CCU_RESET(RST_AHB1_MMC1, 0x2c0, 9) CCU_RESET(RST_AHB1_MMC2, 0x2c0, 10) CCU_RESET(RST_AHB1_MMC3, 0x2c0, 11) CCU_RESET(RST_AHB1_NAND1, 0x2c0, 12) CCU_RESET(RST_AHB1_NAND0, 0x2c0, 13) CCU_RESET(RST_AHB1_SDRAM, 0x2c0, 14) CCU_RESET(RST_AHB1_EMAC, 0x2c0, 17) CCU_RESET(RST_AHB1_TS, 0x2c0, 18) CCU_RESET(RST_AHB1_HSTIMER, 0x2c0, 19) CCU_RESET(RST_AHB1_SPI0, 0x2c0, 20) CCU_RESET(RST_AHB1_SPI1, 0x2c0, 21) CCU_RESET(RST_AHB1_SPI2, 0x2c0, 22) CCU_RESET(RST_AHB1_SPI3, 0x2c0, 23) CCU_RESET(RST_AHB1_OTG, 0x2c0, 24) CCU_RESET(RST_AHB1_EHCI0, 0x2c0, 26) CCU_RESET(RST_AHB1_EHCI1, 0x2c0, 27) CCU_RESET(RST_AHB1_OHCI0, 0x2c0, 29) CCU_RESET(RST_AHB1_OHCI1, 0x2c0, 30) CCU_RESET(RST_AHB1_OHCI2, 0x2c0, 31) CCU_RESET(RST_AHB1_VE, 0x2c4, 0) CCU_RESET(RST_AHB1_LCD0, 0x2c4, 4) CCU_RESET(RST_AHB1_LCD1, 0x2c4, 5) CCU_RESET(RST_AHB1_CSI, 0x2c4, 8) CCU_RESET(RST_AHB1_HDMI, 0x2c4, 11) CCU_RESET(RST_AHB1_BE0, 0x2c4, 12) CCU_RESET(RST_AHB1_BE1, 0x2c4, 13) CCU_RESET(RST_AHB1_FE0, 0x2c4, 14) CCU_RESET(RST_AHB1_FE1, 0x2c4, 15) CCU_RESET(RST_AHB1_MP, 0x2c4, 18) CCU_RESET(RST_AHB1_GPU, 0x2c4, 20) CCU_RESET(RST_AHB1_DEU0, 0x2c4, 23) CCU_RESET(RST_AHB1_DEU1, 0x2c4, 24) CCU_RESET(RST_AHB1_DRC0, 0x2c4, 25) CCU_RESET(RST_AHB1_DRC1, 0x2c4, 26) CCU_RESET(RST_AHB1_LVDS, 0x2c8, 0) CCU_RESET(RST_APB1_CODEC, 0x2d0, 0) CCU_RESET(RST_APB1_SPDIF, 0x2d0, 1) CCU_RESET(RST_APB1_DIGITAL_MIC, 0x2d0, 4) CCU_RESET(RST_APB1_DAUDIO0, 0x2d0, 12) CCU_RESET(RST_APB1_DAUDIO1, 0x2d0, 13) CCU_RESET(RST_APB2_I2C0, 0x2d8, 0) CCU_RESET(RST_APB2_I2C1, 0x2d8, 1) CCU_RESET(RST_APB2_I2C2, 0x2d8, 2) CCU_RESET(RST_APB2_I2C3, 0x2d8, 3) CCU_RESET(RST_APB2_UART0, 0x2d8, 16) CCU_RESET(RST_APB2_UART1, 0x2d8, 17) CCU_RESET(RST_APB2_UART2, 0x2d8, 18) CCU_RESET(RST_APB2_UART3, 0x2d8, 19) CCU_RESET(RST_APB2_UART4, 0x2d8, 20) CCU_RESET(RST_APB2_UART5, 0x2d8, 21) }; static struct aw_ccung_gate a31_ccu_gates[] = { CCU_GATE(CLK_AHB1_MIPIDSI, "ahb1-mipidsi", "ahb1", 0x60, 1) CCU_GATE(CLK_AHB1_SS, "ahb1-ss", "ahb1", 0x60, 5) CCU_GATE(CLK_AHB1_DMA, "ahb1-dma", "ahb1", 0x60, 6) CCU_GATE(CLK_AHB1_MMC0, "ahb1-mmc0", "ahb1", 0x60, 8) CCU_GATE(CLK_AHB1_MMC1, "ahb1-mmc1", "ahb1", 0x60, 9) CCU_GATE(CLK_AHB1_MMC2, "ahb1-mmc2", "ahb1", 0x60, 10) CCU_GATE(CLK_AHB1_MMC3, "ahb1-mmc3", "ahb1", 0x60, 11) CCU_GATE(CLK_AHB1_NAND1, "ahb1-nand1", "ahb1", 0x60, 12) CCU_GATE(CLK_AHB1_NAND0, "ahb1-nand0", "ahb1", 0x60, 13) CCU_GATE(CLK_AHB1_SDRAM, "ahb1-sdram", "ahb1", 0x60, 14) CCU_GATE(CLK_AHB1_EMAC, "ahb1-emac", "ahb1", 0x60, 17) CCU_GATE(CLK_AHB1_TS, "ahb1-ts", "ahb1", 0x60, 18) CCU_GATE(CLK_AHB1_HSTIMER, "ahb1-hstimer", "ahb1", 0x60, 19) CCU_GATE(CLK_AHB1_SPI0, "ahb1-spi0", "ahb1", 0x60, 20) CCU_GATE(CLK_AHB1_SPI1, "ahb1-spi1", "ahb1", 0x60, 21) CCU_GATE(CLK_AHB1_SPI2, "ahb1-spi2", "ahb1", 0x60, 22) CCU_GATE(CLK_AHB1_SPI3, "ahb1-spi3", "ahb1", 0x60, 23) CCU_GATE(CLK_AHB1_OTG, "ahb1-otg", "ahb1", 0x60, 24) CCU_GATE(CLK_AHB1_EHCI0, "ahb1-ehci0", "ahb1", 0x60, 26) CCU_GATE(CLK_AHB1_EHCI1, "ahb1-ehci1", "ahb1", 0x60, 27) CCU_GATE(CLK_AHB1_OHCI0, "ahb1-ohci0", "ahb1", 0x60, 29) CCU_GATE(CLK_AHB1_OHCI1, "ahb1-ohci1", "ahb1", 0x60, 30) CCU_GATE(CLK_AHB1_OHCI2, "ahb1-ohci2", "ahb1", 0x60, 31) CCU_GATE(CLK_AHB1_VE, "ahb1-ve", "ahb1", 0x64, 0) CCU_GATE(CLK_AHB1_LCD0, "ahb1-lcd0", "ahb1", 0x64, 4) CCU_GATE(CLK_AHB1_LCD1, "ahb1-lcd1", "ahb1", 0x64, 5) CCU_GATE(CLK_AHB1_CSI, "ahb1-csi", "ahb1", 0x64, 8) CCU_GATE(CLK_AHB1_HDMI, "ahb1-hdmi", "ahb1", 0x64, 11) CCU_GATE(CLK_AHB1_BE0, "ahb1-be0", "ahb1", 0x64, 12) CCU_GATE(CLK_AHB1_BE1, "ahb1-be1", "ahb1", 0x64, 13) CCU_GATE(CLK_AHB1_FE0, "ahb1-fe0", "ahb1", 0x64, 14) CCU_GATE(CLK_AHB1_FE1, "ahb1-fe1", "ahb1", 0x64, 15) CCU_GATE(CLK_AHB1_MP, "ahb1-mp", "ahb1", 0x64, 18) CCU_GATE(CLK_AHB1_GPU, "ahb1-gpu", "ahb1", 0x64, 20) CCU_GATE(CLK_AHB1_DEU0, "ahb1-deu0", "ahb1", 0x64, 23) CCU_GATE(CLK_AHB1_DEU1, "ahb1-deu1", "ahb1", 0x64, 24) CCU_GATE(CLK_AHB1_DRC0, "ahb1-drc0", "ahb1", 0x64, 25) CCU_GATE(CLK_AHB1_DRC1, "ahb1-drc1", "ahb1", 0x64, 26) CCU_GATE(CLK_APB1_CODEC, "apb1-codec", "apb1", 0x68, 0) CCU_GATE(CLK_APB1_SPDIF, "apb1-spdif", "apb1", 0x68, 1) CCU_GATE(CLK_APB1_DIGITAL_MIC, "apb1-digital-mic", "apb1", 0x68, 4) CCU_GATE(CLK_APB1_PIO, "apb1-pio", "apb1", 0x68, 5) CCU_GATE(CLK_APB1_DAUDIO0, "apb1-daudio0", "apb1", 0x68, 12) CCU_GATE(CLK_APB1_DAUDIO1, "apb1-daudio1", "apb1", 0x68, 13) CCU_GATE(CLK_APB2_I2C0, "apb2-i2c0", "apb2", 0x6c, 0) CCU_GATE(CLK_APB2_I2C1, "apb2-i2c1", "apb2", 0x6c, 1) CCU_GATE(CLK_APB2_I2C2, "apb2-i2c2", "apb2", 0x6c, 2) CCU_GATE(CLK_APB2_I2C3, "apb2-i2c3", "apb2", 0x6c, 3) CCU_GATE(CLK_APB2_UART0, "apb2-uart0", "apb2", 0x6c, 16) CCU_GATE(CLK_APB2_UART1, "apb2-uart1", "apb2", 0x6c, 17) CCU_GATE(CLK_APB2_UART2, "apb2-uart2", "apb2", 0x6c, 18) CCU_GATE(CLK_APB2_UART3, "apb2-uart3", "apb2", 0x6c, 19) CCU_GATE(CLK_APB2_UART4, "apb2-uart4", "apb2", 0x6c, 20) CCU_GATE(CLK_APB2_UART5, "apb2-uart5", "apb2", 0x6c, 21) CCU_GATE(CLK_DAUDIO0, "daudio0", "daudio0mux", 0xb0, 31) CCU_GATE(CLK_DAUDIO1, "daudio1", "daudio1mux", 0xb4, 31) CCU_GATE(CLK_USB_PHY0, "usb-phy0", "osc24M", 0xcc, 8) CCU_GATE(CLK_USB_PHY1, "usb-phy1", "osc24M", 0xcc, 9) CCU_GATE(CLK_USB_PHY2, "usb-phy2", "osc24M", 0xcc, 10) CCU_GATE(CLK_USB_OHCI0, "usb-ohci0", "osc24M", 0xcc, 16) CCU_GATE(CLK_USB_OHCI1, "usb-ohci1", "osc24M", 0xcc, 17) CCU_GATE(CLK_USB_OHCI2, "usb-ohci2", "osc24M", 0xcc, 18) CCU_GATE(CLK_DRAM_VE, "dram-ve", "mdfs", 0x100, 0) CCU_GATE(CLK_DRAM_CSI_ISP, "dram-csi_isp", "mdfs", 0x100, 1) CCU_GATE(CLK_DRAM_TS, "dram-ts", "mdfs", 0x100, 3) CCU_GATE(CLK_DRAM_DRC0, "dram-drc0", "mdfs", 0x100, 16) CCU_GATE(CLK_DRAM_DRC1, "dram-drc1", "mdfs", 0x100, 17) CCU_GATE(CLK_DRAM_DEU0, "dram-deu0", "mdfs", 0x100, 18) CCU_GATE(CLK_DRAM_DEU1, "dram-deu1", "mdfs", 0x100, 19) CCU_GATE(CLK_DRAM_FE0, "dram-fe0", "mdfs", 0x100, 24) CCU_GATE(CLK_DRAM_FE1, "dram-fe1", "mdfs", 0x100, 25) CCU_GATE(CLK_DRAM_BE0, "dram-be0", "mdfs", 0x100, 26) CCU_GATE(CLK_DRAM_BE1, "dram-be1", "mdfs", 0x100, 27) CCU_GATE(CLK_DRAM_MP, "dram-mp", "mdfs", 0x100, 28) CCU_GATE(CLK_CODEC, "codec", "pll_audio", 0x140, 31) CCU_GATE(CLK_AVS, "avs", "pll_audio", 0x144, 31) CCU_GATE(CLK_DIGITAL_MIC, "digital-mic", "pll_audio", 0x148, 31) CCU_GATE(CLK_HDMI_DDC, "hdmi-ddc", "osc24M", 0x150, 30) CCU_GATE(CLK_PS, "ps", "lcd1_ch1", 0x154, 31) }; static const char *pll_parents[] = {"osc24M"}; NKMP_CLK(pll_cpu_clk, CLK_PLL_CPU, /* id */ "pll_cpu", pll_parents, /* name, parents */ 0x00, /* offset */ 8, 5, 0, 0, /* n factor */ 4, 2, 0, 0, /* k factor */ 0, 2, 0, 0, /* m factor */ 0, 0, 1, AW_CLK_FACTOR_FIXED, /* p factor (fake) */ 31, /* gate */ 28, 1000, /* lock */ AW_CLK_HAS_GATE | AW_CLK_HAS_LOCK | AW_CLK_SCALE_CHANGE); /* flags */ NKMP_CLK(pll_audio_clk, CLK_PLL_AUDIO, /* id */ "pll_audio", pll_parents, /* name, parents */ 0x08, /* offset */ 8, 7, 0, 0, /* n factor */ 0, 0, 1, AW_CLK_FACTOR_FIXED, /* k factor (fake) */ 0, 4, 1, 0, /* m factor */ 16, 3, 1, 0, /* p factor */ 31, /* gate */ 28, 1000, /* lock */ AW_CLK_HAS_GATE | AW_CLK_HAS_LOCK); /* flags */ static const char *pll_audio_mult_parents[] = {"pll_audio"}; FIXED_CLK(pll_audio_2x_clk, CLK_PLL_AUDIO_2X, /* id */ "pll_audio-2x", /* name */ pll_audio_mult_parents, /* parent */ 0, /* freq */ 2, /* mult */ 1, /* div */ 0); /* flags */ FIXED_CLK(pll_audio_4x_clk, CLK_PLL_AUDIO_4X, /* id */ "pll_audio-4x", /* name */ pll_audio_mult_parents, /* parent */ 0, /* freq */ 4, /* mult */ 1, /* div */ 0); /* flags */ FIXED_CLK(pll_audio_8x_clk, CLK_PLL_AUDIO_8X, /* id */ "pll_audio-8x", /* name */ pll_audio_mult_parents, /* parent */ 0, /* freq */ 8, /* mult */ 1, /* div */ 0); /* flags */ FRAC_CLK(pll_video0_clk, CLK_PLL_VIDEO0, /* id */ "pll_video0", pll_parents, /* name, parents */ 0x10, /* offset */ 8, 7, 0, 0, /* n factor */ 0, 4, 0, 0, /* m factor */ 31, 28, 1000, /* gate, lock, lock retries */ AW_CLK_HAS_LOCK, /* flags */ 270000000, 297000000, /* freq0, freq1 */ 24, 25); /* mode sel, freq sel */ static const char *pll_video0_2x_parents[] = {"pll_video0"}; FIXED_CLK(pll_video0_2x_clk, CLK_PLL_VIDEO0_2X, /* id */ "pll_video0-2x", /* name */ pll_video0_2x_parents, /* parent */ 0, /* freq */ 2, /* mult */ 1, /* div */ 0); /* flags */ FRAC_CLK(pll_ve_clk, CLK_PLL_VE, /* id */ "pll_ve", pll_parents, /* name, parents */ 0x18, /* offset */ 8, 7, 0, 0, /* n factor */ 0, 4, 0, 0, /* m factor */ 31, 28, 1000, /* gate, lock, lock retries */ AW_CLK_HAS_LOCK, /* flags */ 270000000, 297000000, /* freq0, freq1 */ 24, 25); /* mode sel, freq sel */ NKMP_CLK_WITH_UPDATE(pll_ddr_clk, CLK_PLL_DDR, /* id */ "pll_ddr", pll_parents, /* name, parents */ 0x20, /* offset */ 8, 5, 0, 0, /* n factor */ 4, 2, 0, 0, /* k factor */ 0, 2, 0, 0, /* m factor */ 0, 0, 1, AW_CLK_FACTOR_FIXED, /* p factor (fake) */ 31, /* gate */ 28, 1000, /* lock */ 20, /* update */ AW_CLK_HAS_GATE | AW_CLK_HAS_LOCK); /* flags */ NKMP_CLK(pll_periph_clk, CLK_PLL_PERIPH, /* id */ "pll_periph", pll_parents, /* name, parents */ 0x28, /* offset */ 8, 4, 0, 0, /* n factor */ 5, 2, 1, 0, /* k factor */ 0, 0, 1, AW_CLK_FACTOR_FIXED, /* m factor (fake) */ 0, 0, 1, AW_CLK_FACTOR_FIXED, /* p factor (fake) */ 31, /* gate */ 28, 1000, /* lock */ AW_CLK_HAS_GATE | AW_CLK_HAS_LOCK); /* flags */ static const char *pll_periph_2x_parents[] = {"pll_periph"}; FIXED_CLK(pll_periph_2x_clk, CLK_PLL_PERIPH_2X, /* id */ "pll_periph-2x", /* name */ pll_periph_2x_parents, /* parent */ 0, /* freq */ 2, /* mult */ 1, /* div */ 0); /* flags */ FRAC_CLK(pll_video1_clk, CLK_PLL_VIDEO1, /* id */ "pll_video1", pll_parents, /* name, parents */ 0x30, /* offset */ 8, 7, 0, 0, /* n factor */ 0, 4, 0, 0, /* m factor */ 31, 28, 1000, /* gate, lock, lock retries */ AW_CLK_HAS_LOCK, /* flags */ 270000000, 297000000, /* freq0, freq1 */ 24, 25); /* mode sel, freq sel */ static const char *pll_video1_2x_parents[] = {"pll_video1"}; FIXED_CLK(pll_video1_2x_clk, CLK_PLL_VIDEO1_2X, /* id */ "pll_video1-2x", /* name */ pll_video1_2x_parents, /* parent */ 0, /* freq */ 2, /* mult */ 1, /* div */ 0); /* flags */ FRAC_CLK(pll_gpu_clk, CLK_PLL_GPU, /* id */ "pll_gpu", pll_parents, /* name, parents */ 0x38, /* offset */ 8, 7, 0, 0, /* n factor */ 0, 4, 0, 0, /* m factor */ 31, 28, 1000, /* gate, lock, lock retries */ AW_CLK_HAS_LOCK, /* flags */ 270000000, 297000000, /* freq0, freq1 */ 24, 25); /* mode sel, freq sel */ static const char *pll_mipi_parents[] = {"pll_video0", "pll_video1"}; NKMP_CLK(pll_mipi_clk, CLK_PLL_MIPI, /* id */ "pll_mipi", pll_mipi_parents, /* name, parents */ 0x40, /* offset */ 8, 4, 0, 0, /* n factor */ 4, 2, 1, 0, /* k factor */ 0, 2, 0, 0, /* m factor (fake) */ 0, 0, 1, AW_CLK_FACTOR_FIXED, /* p factor (fake) */ 31, /* gate */ 28, 1000, /* lock */ AW_CLK_HAS_GATE | AW_CLK_HAS_LOCK); /* flags */ FRAC_CLK(pll9_clk, CLK_PLL9, /* id */ "pll9", pll_parents, /* name, parents */ 0x44, /* offset */ 8, 7, 0, 0, /* n factor */ 0, 4, 0, 0, /* m factor */ 31, 28, 1000, /* gate, lock, lock retries */ AW_CLK_HAS_LOCK, /* flags */ 270000000, 297000000, /* freq0, freq1 */ 24, 25); /* mode sel, freq sel */ FRAC_CLK(pll10_clk, CLK_PLL10, /* id */ "pll10", pll_parents, /* name, parents */ 0x48, /* offset */ 8, 7, 0, 0, /* n factor */ 0, 4, 0, 0, /* m factor */ 31, 28, 1000, /* gate, lock, lock retries */ AW_CLK_HAS_LOCK, /* flags */ 270000000, 297000000, /* freq0, freq1 */ 24, 25); /* mode sel, freq sel */ static struct clk_div_table axi_div_table[] = { { .value = 0, .divider = 1, }, { .value = 1, .divider = 2, }, { .value = 2, .divider = 3, }, { .value = 3, .divider = 4, }, { .value = 4, .divider = 4, }, { .value = 5, .divider = 4, }, { .value = 6, .divider = 4, }, { .value = 7, .divider = 4, }, { }, }; static const char *axi_parents[] = {"cpu"}; DIV_CLK(axi_clk, CLK_AXI, /* id */ "axi", axi_parents, /* name, parents */ 0x50, /* offset */ 0, 2, /* shift, mask */ 0, axi_div_table); /* flags, div table */ static const char *cpu_parents[] = {"osc32k", "osc24M", "pll_cpu", "pll_cpu"}; MUX_CLK(cpu_clk, CLK_CPU, /* id */ "cpu", cpu_parents, /* name, parents */ 0x50, 16, 2); /* offset, shift, width */ static const char *ahb1_parents[] = {"osc32k", "osc24M", "axi", "pll_periph"}; PREDIV_CLK(ahb1_clk, CLK_AHB1, /* id */ "ahb1", ahb1_parents, /* name, parents */ 0x54, /* offset */ 12, 2, /* mux */ 4, 2, 0, AW_CLK_FACTOR_POWER_OF_TWO, /* div */ 6, 2, 0, AW_CLK_FACTOR_HAS_COND, /* prediv */ 12, 2, 3); /* prediv condition */ static const char *apb1_parents[] = {"ahb1"}; static struct clk_div_table apb1_div_table[] = { { .value = 0, .divider = 2, }, { .value = 1, .divider = 2, }, { .value = 2, .divider = 4, }, { .value = 3, .divider = 8, }, { }, }; DIV_CLK(apb1_clk, CLK_APB1, /* id */ "apb1", apb1_parents, /* name, parents */ 0x54, /* offset */ 8, 2, /* shift, mask */ CLK_DIV_WITH_TABLE, /* flags */ apb1_div_table); /* div table */ static const char *apb2_parents[] = {"osc32k", "osc24M", "pll_periph", "pll_periph"}; NM_CLK(apb2_clk, CLK_APB2, /* id */ "apb2", apb2_parents, /* name, parents */ 0x58, /* offset */ 16, 2, 0, AW_CLK_FACTOR_POWER_OF_TWO, /* n factor */ 0, 5, 0, 0, /* m factor */ 24, 2, /* mux */ 0, /* gate */ AW_CLK_HAS_MUX); static const char *mod_parents[] = {"osc24M", "pll_periph"}; NM_CLK(nand0_clk, CLK_NAND0, "nand0", mod_parents, /* id, name, parents */ 0x80, /* offset */ 16, 3, 0, AW_CLK_FACTOR_POWER_OF_TWO, /* n factor */ 0, 4, 0, 0, /* m factor */ 24, 2, /* mux */ 31, /* gate */ AW_CLK_HAS_GATE | AW_CLK_HAS_MUX); /* flags */ NM_CLK(nand1_clk, CLK_NAND1, "nand1", mod_parents, /* id, name, parents */ 0x80, /* offset */ 16, 3, 0, AW_CLK_FACTOR_POWER_OF_TWO, /* n factor */ 0, 4, 0, 0, /* m factor */ 24, 2, /* mux */ 31, /* gate */ AW_CLK_HAS_GATE | AW_CLK_HAS_MUX); /* flags */ NM_CLK(mmc0_clk, CLK_MMC0, "mmc0", mod_parents, /* id, name, parents */ 0x88, /* offset */ 16, 2, 0, AW_CLK_FACTOR_POWER_OF_TWO, /* n factor */ 0, 4, 0, 0, /* m factor */ 24, 2, /* mux */ 31, /* gate */ AW_CLK_HAS_GATE | AW_CLK_HAS_MUX | AW_CLK_REPARENT); /* flags */ NM_CLK(mmc1_clk, CLK_MMC1, "mmc1", mod_parents, /* id, name, parents */ 0x8c, /* offset */ 16, 2, 0, AW_CLK_FACTOR_POWER_OF_TWO, /* n factor */ 0, 4, 0, 0, /* m factor */ 24, 2, /* mux */ 31, /* gate */ AW_CLK_HAS_GATE | AW_CLK_HAS_MUX | AW_CLK_REPARENT); /* flags */ NM_CLK(mmc2_clk, CLK_MMC2, "mmc2", mod_parents, /* id, name, parents */ 0x90, /* offset */ 16, 2, 0, AW_CLK_FACTOR_POWER_OF_TWO, /* n factor */ 0, 4, 0, 0, /* m factor */ 24, 2, /* mux */ 31, /* gate */ AW_CLK_HAS_GATE | AW_CLK_HAS_MUX | AW_CLK_REPARENT); /* flags */ NM_CLK(mmc3_clk, CLK_MMC2, "mmc3", mod_parents, /* id, name, parents */ 0x94, /* offset */ 16, 2, 0, AW_CLK_FACTOR_POWER_OF_TWO, /* n factor */ 0, 4, 0, 0, /* m factor */ 24, 2, /* mux */ 31, /* gate */ AW_CLK_HAS_GATE | AW_CLK_HAS_MUX | AW_CLK_REPARENT); /* flags */ static const char *ts_parents[] = {"osc24M", "pll_periph"}; NM_CLK(ts_clk, CLK_TS, "ts", ts_parents, /* id, name, parents */ 0x98, /* offset */ 16, 2, 0, AW_CLK_FACTOR_POWER_OF_TWO, /* n factor */ 0, 4, 0, 0, /* m factor */ 24, 4, /* mux */ 31, /* gate */ AW_CLK_HAS_GATE | AW_CLK_HAS_MUX); /* flags */ NM_CLK(ss_clk, CLK_SS, "ss", mod_parents, /* id, name, parents */ 0x9C, /* offset */ 16, 2, 0, AW_CLK_FACTOR_POWER_OF_TWO, /* n factor */ 0, 4, 0, 0, /* m factor */ 24, 4, /* mux */ 31, /* gate */ AW_CLK_HAS_GATE | AW_CLK_HAS_MUX); /* flags */ NM_CLK(spi0_clk, CLK_SPI0, "spi0", mod_parents, /* id, name, parents */ 0xA0, /* offset */ 16, 2, 0, AW_CLK_FACTOR_POWER_OF_TWO, /* n factor */ 0, 4, 0, 0, /* m factor */ 24, 4, /* mux */ 31, /* gate */ AW_CLK_HAS_GATE | AW_CLK_HAS_MUX); /* flags */ NM_CLK(spi1_clk, CLK_SPI1, "spi1", mod_parents, /* id, name, parents */ 0xA4, /* offset */ 16, 2, 0, AW_CLK_FACTOR_POWER_OF_TWO, /* n factor */ 0, 4, 0, 0, /* m factor */ 24, 4, /* mux */ 31, /* gate */ AW_CLK_HAS_GATE | AW_CLK_HAS_MUX); /* flags */ NM_CLK(spi2_clk, CLK_SPI2, "spi2", mod_parents, /* id, name, parents */ 0xA8, /* offset */ 16, 2, 0, AW_CLK_FACTOR_POWER_OF_TWO, /* n factor */ 0, 4, 0, 0, /* m factor */ 24, 4, /* mux */ 31, /* gate */ AW_CLK_HAS_GATE | AW_CLK_HAS_MUX); /* flags */ NM_CLK(spi3_clk, CLK_SPI3, "spi3", mod_parents, /* id, name, parents */ 0xAC, /* offset */ 16, 2, 0, AW_CLK_FACTOR_POWER_OF_TWO, /* n factor */ 0, 4, 0, 0, /* m factor */ 24, 4, /* mux */ 31, /* gate */ AW_CLK_HAS_GATE | AW_CLK_HAS_MUX); /* flags */ static const char *daudio_parents[] = {"pll_audio-8x", "pll_audio-4x", "pll_audio-2x", "pll_audio"}; MUX_CLK(daudio0mux_clk, 0, "daudio0mux", daudio_parents, 0xb0, 16, 2); MUX_CLK(daudio1mux_clk, 0, "daudio1mux", daudio_parents, 0xb4, 16, 2); static const char *mdfs_parents[] = {"pll_ddr", "pll_periph"}; NM_CLK(mdfs_clk, CLK_MDFS, "mdfs", mdfs_parents, /* id, name, parents */ 0xF0, /* offset */ 16, 2, 0, AW_CLK_FACTOR_POWER_OF_TWO, /* n factor */ 0, 4, 0, 0, /* m factor */ 24, 4, /* mux */ 31, /* gate */ AW_CLK_HAS_GATE | AW_CLK_HAS_MUX); /* flags */ static const char *dram_parents[] = {"pll_ddr", "pll_periph"}; NM_CLK(sdram0_clk, CLK_SDRAM0, "sdram0", dram_parents, /* id, name, parents */ 0xF4, /* offset */ 0, 0, 1, AW_CLK_FACTOR_FIXED, /* n factor (fake) */ 0, 4, 0, 0, /* m factor */ 4, 1, /* mux */ 0, /* gate */ AW_CLK_HAS_MUX); /* flags */ NM_CLK(sdram1_clk, CLK_SDRAM1, "sdram1", dram_parents, /* id, name, parents */ 0xF4, /* offset */ 0, 0, 1, AW_CLK_FACTOR_FIXED, /* n factor (fake) */ 8, 4, 0, 0, /* m factor */ 12, 1, /* mux */ 0, /* gate */ AW_CLK_HAS_MUX); /* flags */ static const char *befe_parents[] = {"pll_video0", "pll_video1", "pll_periph-2x", "pll_gpu", "pll9", "pll10"}; NM_CLK(be0_clk, CLK_BE0, "be0", befe_parents, /* id, name, parents */ 0x104, /* offset */ 0, 0, 1, AW_CLK_FACTOR_FIXED, /* n factor (fake) */ 0, 4, 0, 0, /* m factor */ 24, 3, /* mux */ 31, /* gate */ AW_CLK_HAS_MUX | AW_CLK_HAS_GATE); /* flags */ NM_CLK(be1_clk, CLK_BE1, "be1", befe_parents, /* id, name, parents */ 0x108, /* offset */ 0, 0, 1, AW_CLK_FACTOR_FIXED, /* n factor (fake) */ 0, 4, 0, 0, /* m factor */ 24, 3, /* mux */ 31, /* gate */ AW_CLK_HAS_MUX | AW_CLK_HAS_GATE); /* flags */ NM_CLK(fe0_clk, CLK_FE0, "fe0", befe_parents, /* id, name, parents */ 0x104, /* offset */ 0, 0, 1, AW_CLK_FACTOR_FIXED, /* n factor (fake) */ 0, 4, 0, 0, /* m factor */ 24, 3, /* mux */ 31, /* gate */ AW_CLK_HAS_MUX | AW_CLK_HAS_GATE); /* flags */ NM_CLK(fe1_clk, CLK_FE1, "fe1", befe_parents, /* id, name, parents */ 0x108, /* offset */ 0, 0, 1, AW_CLK_FACTOR_FIXED, /* n factor (fake) */ 0, 4, 0, 0, /* m factor */ 24, 3, /* mux */ 31, /* gate */ AW_CLK_HAS_MUX | AW_CLK_HAS_GATE); /* flags */ static const char *mp_parents[] = {"pll_video0", "pll_video1", "pll9", "pll10"}; NM_CLK(mp_clk, CLK_MP, "mp", mp_parents, /* id, name, parents */ 0x108, /* offset */ 0, 0, 1, AW_CLK_FACTOR_FIXED, /* n factor (fake) */ 0, 4, 0, 0, /* m factor */ 24, 3, /* mux */ 31, /* gate */ AW_CLK_HAS_MUX | AW_CLK_HAS_GATE); /* flags */ static const char *lcd_ch0_parents[] = {"pll_video0", "pll_video1", "pll_video0-2x", "pll_video1-2x", "pll_mipi"}; NM_CLK(lcd0_ch0_clk, CLK_LCD0_CH0, "lcd0_ch0", lcd_ch0_parents, /* id, name, parents */ 0x118, /* offset */ 0, 0, 1, AW_CLK_FACTOR_FIXED, /* n factor (fake) */ 0, 0, 1, AW_CLK_FACTOR_FIXED, /* m factor (fake )*/ 24, 3, /* mux */ 31, /* gate */ AW_CLK_HAS_MUX | AW_CLK_HAS_GATE); /* flags */ NM_CLK(lcd1_ch0_clk, CLK_LCD1_CH0, "lcd1_ch0", lcd_ch0_parents, /* id, name, parents */ 0x11C, /* offset */ 0, 0, 1, AW_CLK_FACTOR_FIXED, /* n factor (fake) */ 0, 0, 1, AW_CLK_FACTOR_FIXED, /* m factor (fake )*/ 24, 3, /* mux */ 31, /* gate */ AW_CLK_HAS_MUX | AW_CLK_HAS_GATE); /* flags */ static const char *lcd_ch1_parents[] = {"pll_video0", "pll_video1", "pll_video0-2x", "pll_video1-2x"}; NM_CLK(lcd0_ch1_clk, CLK_LCD0_CH1, "lcd0_ch1", lcd_ch1_parents, /* id, name, parents */ 0x12C, /* offset */ 0, 0, 1, AW_CLK_FACTOR_FIXED, /* n factor (fake) */ 0, 4, 0, 0, /* m factor */ 24, 3, /* mux */ 31, /* gate */ AW_CLK_HAS_MUX | AW_CLK_HAS_GATE); /* flags */ NM_CLK(lcd1_ch1_clk, CLK_LCD1_CH1, "lcd1_ch1", lcd_ch1_parents, /* id, name, parents */ 0x130, /* offset */ 0, 0, 1, AW_CLK_FACTOR_FIXED, /* n factor (fake) */ 0, 4, 0, 0, /* m factor */ 24, 3, /* mux */ 31, /* gate */ AW_CLK_HAS_MUX | AW_CLK_HAS_GATE); /* flags */ /* CSI0 0x134 Need Mux table */ /* CSI1 0x138 Need Mux table */ static const char *ve_parents[] = {"pll_ve"}; NM_CLK(ve_clk, CLK_VE, "ve", ve_parents, /* id, name, parents */ 0x13C, /* offset */ 16, 3, 0, 0, /* n factor */ 0, 0, 1, AW_CLK_FACTOR_FIXED, /* m factor (fake) */ 0, 0, /* mux */ 31, /* gate */ AW_CLK_HAS_GATE); /* flags */ NM_CLK(hdmi_clk, CLK_HDMI, "hdmi", lcd_ch1_parents, /* id, name, parents */ 0x150, /* offset */ 0, 0, 1, AW_CLK_FACTOR_FIXED, /* n factor (fake) */ 0, 4, 0, 0, /* m factor */ 0, 0, /* mux */ 31, /* gate */ AW_CLK_HAS_GATE); /* flags */ static const char *mbus_parents[] = {"osc24M", "pll_periph", "pll_ddr"}; NM_CLK(mbus0_clk, CLK_MBUS0, "mbus0", mbus_parents, /* id, name, parents */ 0x15C, /* offset */ 16, 2, 0, 0, /* n factor */ 0, 4, 0, 0, /* m factor */ 24, 2, /* mux */ 31, /* gate */ AW_CLK_HAS_MUX | AW_CLK_HAS_GATE); /* flags */ NM_CLK(mbus1_clk, CLK_MBUS1, "mbus1", mbus_parents, /* id, name, parents */ 0x160, /* offset */ 16, 2, 0, 0, /* n factor */ 0, 4, 0, 0, /* m factor */ 24, 2, /* mux */ 31, /* gate */ AW_CLK_HAS_MUX | AW_CLK_HAS_GATE); /* flags */ static const char *mipi_parents[] = {"pll_video0", "pll_video1", "pll_video0-2x", "pll_video1-2x"}; NM_CLK(mipi_dsi_clk, CLK_MIPI_DSI, "mipi_dsi", mipi_parents, /* id, name, parents */ 0x168, /* offset */ 0, 0, 1, AW_CLK_FACTOR_FIXED, /* n factor (fake) */ 16, 4, 0, 0, /* m factor */ 24, 2, /* mux */ 31, /* gate */ AW_CLK_HAS_MUX | AW_CLK_HAS_GATE); /* flags */ NM_CLK(mipi_dsi_dphy_clk, CLK_MIPI_DSI_DPHY, "mipi_dsi_dphy", mipi_parents, /* id, name, parents */ 0x168, /* offset */ 0, 0, 1, AW_CLK_FACTOR_FIXED, /* n factor (fake) */ 0, 4, 0, 0, /* m factor */ 8, 2, /* mux */ 15, /* gate */ AW_CLK_HAS_MUX | AW_CLK_HAS_GATE); /* flags */ NM_CLK(mipi_csi_dphy_clk, CLK_MIPI_CSI_DPHY, "mipi_csi_dphy", mipi_parents, /* id, name, parents */ 0x16C, /* offset */ 0, 0, 1, AW_CLK_FACTOR_FIXED, /* n factor (fake) */ 0, 4, 0, 0, /* m factor */ 8, 2, /* mux */ 15, /* gate */ AW_CLK_HAS_MUX | AW_CLK_HAS_GATE); /* flags */ static const char *iep_parents[] = {"pll_video0", "pll_video1", "pll_periph-2x", "pll_gpu", "pll9", "pll10"}; NM_CLK(iep_drc0_clk, CLK_IEP_DRC0, "iep_drc0", iep_parents, /* id, name, parents */ 0x180, /* offset */ 0, 0, 1, AW_CLK_FACTOR_FIXED, /* n factor (fake) */ 0, 4, 0, 0, /* m factor */ 24, 2, /* mux */ 31, /* gate */ AW_CLK_HAS_MUX | AW_CLK_HAS_GATE); /* flags */ NM_CLK(iep_drc1_clk, CLK_IEP_DRC1, "iep_drc1", iep_parents, /* id, name, parents */ 0x184, /* offset */ 0, 0, 1, AW_CLK_FACTOR_FIXED, /* n factor (fake) */ 0, 4, 0, 0, /* m factor */ 24, 2, /* mux */ 31, /* gate */ AW_CLK_HAS_MUX | AW_CLK_HAS_GATE); /* flags */ NM_CLK(iep_deu0_clk, CLK_IEP_DEU0, "iep_deu0", iep_parents, /* id, name, parents */ 0x188, /* offset */ 0, 0, 1, AW_CLK_FACTOR_FIXED, /* n factor (fake) */ 0, 4, 0, 0, /* m factor */ 24, 2, /* mux */ 31, /* gate */ AW_CLK_HAS_MUX | AW_CLK_HAS_GATE); /* flags */ NM_CLK(iep_deu1_clk, CLK_IEP_DEU1, "iep_deu1", iep_parents, /* id, name, parents */ 0x18C, /* offset */ 0, 0, 1, AW_CLK_FACTOR_FIXED, /* n factor (fake) */ 0, 4, 0, 0, /* m factor */ 24, 2, /* mux */ 31, /* gate */ AW_CLK_HAS_MUX | AW_CLK_HAS_GATE); /* flags */ static const char *gpu_parents[] = {"pll_gpu", "pll_periph-2x", "pll_video0", "pll_video1", "pll9", "pll10"}; PREDIV_CLK(gpu_core_clk, CLK_GPU_CORE, /* id */ "gpu_core", gpu_parents, /* name, parents */ 0x1A0, /* offset */ 24, 3, /* mux */ 0, 3, 0, 0, /* div */ 0, 0, 3, AW_CLK_FACTOR_HAS_COND | AW_CLK_FACTOR_FIXED, /* prediv */ 24, 2, 1); /* prediv condition */ PREDIV_CLK(gpu_memory_clk, CLK_GPU_MEMORY, /* id */ "gpu_memory", gpu_parents, /* name, parents */ 0x1A4, /* offset */ 24, 3, /* mux */ 0, 3, 0, 0, /* div */ 0, 0, 3, AW_CLK_FACTOR_HAS_COND | AW_CLK_FACTOR_FIXED, /* prediv */ 24, 2, 1); /* prediv condition */ PREDIV_CLK(gpu_hyd_clk, CLK_GPU_HYD, /* id */ "gpu_hyd", gpu_parents, /* name, parents */ 0x1A8, /* offset */ 24, 3, /* mux */ 0, 3, 0, 0, /* div */ 0, 0, 3, AW_CLK_FACTOR_HAS_COND | AW_CLK_FACTOR_FIXED, /* prediv */ 24, 2, 1); /* prediv condition */ /* ATS 0x1B0 */ /* Trace 0x1B4 */ static struct aw_ccung_clk a31_ccu_clks[] = { { .type = AW_CLK_NKMP, .clk.nkmp = &pll_cpu_clk}, { .type = AW_CLK_NKMP, .clk.nkmp = &pll_audio_clk}, { .type = AW_CLK_NKMP, .clk.nkmp = &pll_periph_clk}, { .type = AW_CLK_NKMP, .clk.nkmp = &pll_ddr_clk}, { .type = AW_CLK_NKMP, .clk.nkmp = &pll_mipi_clk}, { .type = AW_CLK_FRAC, .clk.frac = &pll_video0_clk}, { .type = AW_CLK_FRAC, .clk.frac = &pll_ve_clk}, { .type = AW_CLK_FRAC, .clk.frac = &pll_video1_clk}, { .type = AW_CLK_FRAC, .clk.frac = &pll_gpu_clk}, { .type = AW_CLK_FRAC, .clk.frac = &pll9_clk}, { .type = AW_CLK_FRAC, .clk.frac = &pll10_clk}, { .type = AW_CLK_NM, .clk.nm = &apb2_clk}, { .type = AW_CLK_NM, .clk.nm = &nand0_clk}, { .type = AW_CLK_NM, .clk.nm = &nand1_clk}, { .type = AW_CLK_NM, .clk.nm = &mmc0_clk}, { .type = AW_CLK_NM, .clk.nm = &mmc1_clk}, { .type = AW_CLK_NM, .clk.nm = &mmc2_clk}, { .type = AW_CLK_NM, .clk.nm = &mmc3_clk}, { .type = AW_CLK_NM, .clk.nm = &ts_clk}, { .type = AW_CLK_NM, .clk.nm = &ss_clk}, { .type = AW_CLK_NM, .clk.nm = &spi0_clk}, { .type = AW_CLK_NM, .clk.nm = &spi1_clk}, { .type = AW_CLK_NM, .clk.nm = &spi2_clk}, { .type = AW_CLK_NM, .clk.nm = &spi3_clk}, { .type = AW_CLK_NM, .clk.nm = &mdfs_clk}, { .type = AW_CLK_NM, .clk.nm = &sdram0_clk}, { .type = AW_CLK_NM, .clk.nm = &sdram1_clk}, { .type = AW_CLK_NM, .clk.nm = &be0_clk}, { .type = AW_CLK_NM, .clk.nm = &be1_clk}, { .type = AW_CLK_NM, .clk.nm = &fe0_clk}, { .type = AW_CLK_NM, .clk.nm = &fe1_clk}, { .type = AW_CLK_NM, .clk.nm = &mp_clk}, { .type = AW_CLK_NM, .clk.nm = &lcd0_ch0_clk}, { .type = AW_CLK_NM, .clk.nm = &lcd1_ch0_clk}, { .type = AW_CLK_NM, .clk.nm = &lcd0_ch1_clk}, { .type = AW_CLK_NM, .clk.nm = &lcd1_ch1_clk}, { .type = AW_CLK_NM, .clk.nm = &ve_clk}, { .type = AW_CLK_NM, .clk.nm = &hdmi_clk}, { .type = AW_CLK_NM, .clk.nm = &mbus0_clk}, { .type = AW_CLK_NM, .clk.nm = &mbus1_clk}, { .type = AW_CLK_NM, .clk.nm = &mipi_dsi_clk}, { .type = AW_CLK_NM, .clk.nm = &mipi_dsi_dphy_clk}, { .type = AW_CLK_NM, .clk.nm = &mipi_csi_dphy_clk}, { .type = AW_CLK_NM, .clk.nm = &iep_drc0_clk}, { .type = AW_CLK_NM, .clk.nm = &iep_drc1_clk}, { .type = AW_CLK_NM, .clk.nm = &iep_deu0_clk}, { .type = AW_CLK_NM, .clk.nm = &iep_deu1_clk}, { .type = AW_CLK_PREDIV_MUX, .clk.prediv_mux = &ahb1_clk}, { .type = AW_CLK_PREDIV_MUX, .clk.prediv_mux = &gpu_core_clk}, { .type = AW_CLK_PREDIV_MUX, .clk.prediv_mux = &gpu_memory_clk}, { .type = AW_CLK_PREDIV_MUX, .clk.prediv_mux = &gpu_hyd_clk}, { .type = AW_CLK_DIV, .clk.div = &axi_clk}, { .type = AW_CLK_DIV, .clk.div = &apb1_clk}, { .type = AW_CLK_MUX, .clk.mux = &cpu_clk}, { .type = AW_CLK_MUX, .clk.mux = &daudio0mux_clk}, { .type = AW_CLK_MUX, .clk.mux = &daudio1mux_clk}, { .type = AW_CLK_FIXED, .clk.fixed = &pll_audio_2x_clk}, { .type = AW_CLK_FIXED, .clk.fixed = &pll_audio_4x_clk}, { .type = AW_CLK_FIXED, .clk.fixed = &pll_audio_8x_clk}, { .type = AW_CLK_FIXED, .clk.fixed = &pll_video0_2x_clk}, { .type = AW_CLK_FIXED, .clk.fixed = &pll_periph_2x_clk}, { .type = AW_CLK_FIXED, .clk.fixed = &pll_video1_2x_clk}, }; static int ccu_a31_probe(device_t dev) { if (!ofw_bus_status_okay(dev)) return (ENXIO); if (!ofw_bus_is_compatible(dev, "allwinner,sun6i-a31-ccu")) return (ENXIO); device_set_desc(dev, "Allwinner A31 Clock Control Unit NG"); return (BUS_PROBE_DEFAULT); } static int ccu_a31_attach(device_t dev) { struct aw_ccung_softc *sc; sc = device_get_softc(dev); sc->resets = a31_ccu_resets; sc->nresets = nitems(a31_ccu_resets); sc->gates = a31_ccu_gates; sc->ngates = nitems(a31_ccu_gates); sc->clks = a31_ccu_clks; sc->nclks = nitems(a31_ccu_clks); return (aw_ccung_attach(dev)); } static device_method_t ccu_a31ng_methods[] = { /* Device interface */ DEVMETHOD(device_probe, ccu_a31_probe), DEVMETHOD(device_attach, ccu_a31_attach), DEVMETHOD_END }; static devclass_t ccu_a31ng_devclass; DEFINE_CLASS_1(ccu_a31ng, ccu_a31ng_driver, ccu_a31ng_methods, sizeof(struct aw_ccung_softc), aw_ccung_driver); EARLY_DRIVER_MODULE(ccu_a31ng, simplebus, ccu_a31ng_driver, - ccu_a31ng_devclass, 0, 0, BUS_PASS_BUS + BUS_PASS_ORDER_LAST); + ccu_a31ng_devclass, 0, 0, BUS_PASS_RESOURCE + BUS_PASS_ORDER_MIDDLE); Index: head/sys/arm/allwinner/clkng/ccu_a64.c =================================================================== --- head/sys/arm/allwinner/clkng/ccu_a64.c (revision 350841) +++ head/sys/arm/allwinner/clkng/ccu_a64.c (revision 350842) @@ -1,830 +1,830 @@ /*- * SPDX-License-Identifier: BSD-2-Clause-FreeBSD * * Copyright (c) 2017,2018 Emmanuel Vadot * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. * * $FreeBSD$ */ #include __FBSDID("$FreeBSD$"); #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include /* Non-exported clocks */ #define CLK_OSC_12M 0 #define CLK_PLL_CPUX 1 #define CLK_PLL_AUDIO_BASE 2 #define CLK_PLL_AUDIO 3 #define CLK_PLL_AUDIO_2X 4 #define CLK_PLL_AUDIO_4X 5 #define CLK_PLL_AUDIO_8X 6 #define CLK_PLL_VIDEO0 7 #define CLK_PLL_VIDEO0_2X 8 #define CLK_PLL_VE 9 #define CLK_PLL_DDR0 10 #define CLK_PLL_PERIPH0_2X 12 #define CLK_PLL_PERIPH1 13 #define CLK_PLL_PERIPH1_2X 14 #define CLK_PLL_VIDEO1 15 #define CLK_PLL_GPU 16 #define CLK_PLL_HSIC 18 #define CLK_PLL_DE 19 #define CLK_PLL_DDR1 20 #define CLK_CPUX 21 #define CLK_AXI 22 #define CLK_APB 23 #define CLK_AHB1 24 #define CLK_APB1 25 #define CLK_APB2 26 #define CLK_AHB2 27 #define CLK_DRAM 94 #define CLK_MBUS 112 static struct aw_ccung_reset a64_ccu_resets[] = { CCU_RESET(RST_USB_PHY0, 0x0cc, 0) CCU_RESET(RST_USB_PHY1, 0x0cc, 1) CCU_RESET(RST_USB_HSIC, 0x0cc, 2) CCU_RESET(RST_BUS_MIPI_DSI, 0x2c0, 1) CCU_RESET(RST_BUS_CE, 0x2c0, 5) CCU_RESET(RST_BUS_DMA, 0x2c0, 6) CCU_RESET(RST_BUS_MMC0, 0x2c0, 8) CCU_RESET(RST_BUS_MMC1, 0x2c0, 9) CCU_RESET(RST_BUS_MMC2, 0x2c0, 10) CCU_RESET(RST_BUS_NAND, 0x2c0, 13) CCU_RESET(RST_BUS_DRAM, 0x2c0, 14) CCU_RESET(RST_BUS_EMAC, 0x2c0, 17) CCU_RESET(RST_BUS_TS, 0x2c0, 18) CCU_RESET(RST_BUS_HSTIMER, 0x2c0, 19) CCU_RESET(RST_BUS_SPI0, 0x2c0, 20) CCU_RESET(RST_BUS_SPI1, 0x2c0, 21) CCU_RESET(RST_BUS_OTG, 0x2c0, 23) CCU_RESET(RST_BUS_EHCI0, 0x2c0, 24) CCU_RESET(RST_BUS_EHCI1, 0x2c0, 25) CCU_RESET(RST_BUS_OHCI0, 0x2c0, 28) CCU_RESET(RST_BUS_OHCI1, 0x2c0, 29) CCU_RESET(RST_BUS_VE, 0x2c4, 0) CCU_RESET(RST_BUS_TCON0, 0x2c4, 3) CCU_RESET(RST_BUS_TCON1, 0x2c4, 4) CCU_RESET(RST_BUS_DEINTERLACE, 0x2c4, 5) CCU_RESET(RST_BUS_CSI, 0x2c4, 8) CCU_RESET(RST_BUS_HDMI0, 0x2c4, 10) CCU_RESET(RST_BUS_HDMI1, 0x2c4, 11) CCU_RESET(RST_BUS_DE, 0x2c4, 12) CCU_RESET(RST_BUS_GPU, 0x2c4, 20) CCU_RESET(RST_BUS_MSGBOX, 0x2c4, 21) CCU_RESET(RST_BUS_SPINLOCK, 0x2c4, 22) CCU_RESET(RST_BUS_DBG, 0x2c4, 31) CCU_RESET(RST_BUS_LVDS, 0x2C8, 31) CCU_RESET(RST_BUS_CODEC, 0x2D0, 0) CCU_RESET(RST_BUS_SPDIF, 0x2D0, 1) CCU_RESET(RST_BUS_THS, 0x2D0, 8) CCU_RESET(RST_BUS_I2S0, 0x2D0, 12) CCU_RESET(RST_BUS_I2S1, 0x2D0, 13) CCU_RESET(RST_BUS_I2S2, 0x2D0, 14) CCU_RESET(RST_BUS_I2C0, 0x2D8, 0) CCU_RESET(RST_BUS_I2C1, 0x2D8, 1) CCU_RESET(RST_BUS_I2C2, 0x2D8, 2) CCU_RESET(RST_BUS_SCR, 0x2D8, 5) CCU_RESET(RST_BUS_UART0, 0x2D8, 16) CCU_RESET(RST_BUS_UART1, 0x2D8, 17) CCU_RESET(RST_BUS_UART2, 0x2D8, 18) CCU_RESET(RST_BUS_UART3, 0x2D8, 19) CCU_RESET(RST_BUS_UART4, 0x2D8, 20) }; static struct aw_ccung_gate a64_ccu_gates[] = { CCU_GATE(CLK_BUS_MIPI_DSI, "bus-mipi-dsi", "ahb1", 0x60, 1) CCU_GATE(CLK_BUS_CE, "bus-ce", "ahb1", 0x60, 5) CCU_GATE(CLK_BUS_DMA, "bus-dma", "ahb1", 0x60, 6) CCU_GATE(CLK_BUS_MMC0, "bus-mmc0", "ahb1", 0x60, 8) CCU_GATE(CLK_BUS_MMC1, "bus-mmc1", "ahb1", 0x60, 9) CCU_GATE(CLK_BUS_MMC2, "bus-mmc2", "ahb1", 0x60, 10) CCU_GATE(CLK_BUS_NAND, "bus-nand", "ahb1", 0x60, 13) CCU_GATE(CLK_BUS_DRAM, "bus-dram", "ahb1", 0x60, 14) CCU_GATE(CLK_BUS_EMAC, "bus-emac", "ahb2", 0x60, 16) CCU_GATE(CLK_BUS_TS, "bus-ts", "ahb1", 0x60, 18) CCU_GATE(CLK_BUS_HSTIMER, "bus-hstimer", "ahb1", 0x60, 19) CCU_GATE(CLK_BUS_SPI0, "bus-spi0", "ahb1", 0x60, 20) CCU_GATE(CLK_BUS_SPI1, "bus-spi1", "ahb1", 0x60, 21) CCU_GATE(CLK_BUS_OTG, "bus-otg", "ahb1", 0x60, 23) CCU_GATE(CLK_BUS_EHCI0, "bus-ehci0", "ahb1", 0x60, 24) CCU_GATE(CLK_BUS_EHCI1, "bus-ehci1", "ahb2", 0x60, 25) CCU_GATE(CLK_BUS_OHCI0, "bus-ohci0", "ahb1", 0x60, 28) CCU_GATE(CLK_BUS_OHCI1, "bus-ohci1", "ahb2", 0x60, 29) CCU_GATE(CLK_BUS_VE, "bus-ve", "ahb1", 0x64, 0) CCU_GATE(CLK_BUS_TCON0, "bus-tcon0", "ahb1", 0x64, 3) CCU_GATE(CLK_BUS_TCON1, "bus-tcon1", "ahb1", 0x64, 4) CCU_GATE(CLK_BUS_DEINTERLACE, "bus-deinterlace", "ahb1", 0x64, 5) CCU_GATE(CLK_BUS_CSI, "bus-csi", "ahb1", 0x64, 8) CCU_GATE(CLK_BUS_HDMI, "bus-hdmi", "ahb1", 0x64, 11) CCU_GATE(CLK_BUS_DE, "bus-de", "ahb1", 0x64, 12) CCU_GATE(CLK_BUS_GPU, "bus-gpu", "ahb1", 0x64, 20) CCU_GATE(CLK_BUS_MSGBOX, "bus-msgbox", "ahb1", 0x64, 21) CCU_GATE(CLK_BUS_SPINLOCK, "bus-spinlock", "ahb1", 0x64, 22) CCU_GATE(CLK_BUS_CODEC, "bus-codec", "apb1", 0x68, 0) CCU_GATE(CLK_BUS_SPDIF, "bus-spdif", "apb1", 0x68, 1) CCU_GATE(CLK_BUS_PIO, "bus-pio", "apb1", 0x68, 5) CCU_GATE(CLK_BUS_THS, "bus-ths", "apb1", 0x68, 8) CCU_GATE(CLK_BUS_I2S0, "bus-i2s0", "apb1", 0x68, 12) CCU_GATE(CLK_BUS_I2S1, "bus-i2s1", "apb1", 0x68, 13) CCU_GATE(CLK_BUS_I2S2, "bus-i2s2", "apb1", 0x68, 14) CCU_GATE(CLK_BUS_I2C0, "bus-i2c0", "apb2", 0x6C, 0) CCU_GATE(CLK_BUS_I2C1, "bus-i2c1", "apb2", 0x6C, 1) CCU_GATE(CLK_BUS_I2C2, "bus-i2c2", "apb2", 0x6C, 2) CCU_GATE(CLK_BUS_SCR, "bus-src", "apb2", 0x6C, 5) CCU_GATE(CLK_BUS_UART0, "bus-uart0", "apb2", 0x6C, 16) CCU_GATE(CLK_BUS_UART1, "bus-uart1", "apb2", 0x6C, 17) CCU_GATE(CLK_BUS_UART2, "bus-uart2", "apb2", 0x6C, 18) CCU_GATE(CLK_BUS_UART3, "bus-uart3", "apb2", 0x6C, 19) CCU_GATE(CLK_BUS_UART4, "bus-uart4", "apb2", 0x6C, 20) CCU_GATE(CLK_BUS_DBG, "bus-dbg", "ahb1", 0x70, 7) CCU_GATE(CLK_THS, "ths", "thsdiv", 0x74, 31) CCU_GATE(CLK_USB_PHY0, "usb-phy0", "osc24M", 0xcc, 8) CCU_GATE(CLK_USB_PHY1, "usb-phy1", "osc24M", 0xcc, 9) CCU_GATE(CLK_USB_HSIC, "usb-hsic", "pll_hsic", 0xcc, 10) CCU_GATE(CLK_USB_HSIC_12M, "usb-hsic-12M", "osc12M", 0xcc, 11) CCU_GATE(CLK_USB_OHCI0, "usb-ohci0", "osc12M", 0xcc, 16) CCU_GATE(CLK_USB_OHCI1, "usb-ohci1", "usb-ohci0", 0xcc, 17) CCU_GATE(CLK_DRAM_VE, "dram-ve", "dram", 0x100, 0) CCU_GATE(CLK_DRAM_CSI, "dram-csi", "dram", 0x100, 1) CCU_GATE(CLK_DRAM_DEINTERLACE, "dram-deinterlace", "dram", 0x100, 2) CCU_GATE(CLK_DRAM_TS, "dram-ts", "dram", 0x100, 3) CCU_GATE(CLK_CSI_MISC, "csi-misc", "osc24M", 0x130, 31) CCU_GATE(CLK_AC_DIG_4X, "ac-dig-4x", "pll_audio-4x", 0x140, 30) CCU_GATE(CLK_AC_DIG, "ac-dig", "pll_audio", 0x140, 31) CCU_GATE(CLK_AVS, "avs", "osc24M", 0x144, 31) CCU_GATE(CLK_HDMI_DDC, "hdmi-ddc", "osc24M", 0x154, 31) }; static const char *osc12m_parents[] = {"osc24M"}; FIXED_CLK(osc12m_clk, CLK_OSC_12M, /* id */ "osc12M", /* name */ osc12m_parents, /* parent */ 0, /* freq */ 1, /* mult */ 2, /* div */ 0); /* flags */ static const char *pll_cpux_parents[] = {"osc24M"}; NKMP_CLK(pll_cpux_clk, CLK_PLL_CPUX, /* id */ "pll_cpux", pll_cpux_parents, /* name, parents */ 0x00, /* offset */ 8, 5, 0, 0, /* n factor */ 4, 2, 0, 0, /* k factor */ 0, 2, 0, 0, /* m factor */ 16, 2, 0, AW_CLK_FACTOR_POWER_OF_TWO, /* p factor */ 31, /* gate */ 28, 1000, /* lock */ AW_CLK_HAS_GATE | AW_CLK_HAS_LOCK | AW_CLK_SCALE_CHANGE); /* flags */ static const char *pll_audio_parents[] = {"osc24M"}; NKMP_CLK(pll_audio_clk, CLK_PLL_AUDIO, /* id */ "pll_audio", pll_audio_parents, /* name, parents */ 0x08, /* offset */ 8, 7, 0, 0, /* n factor */ 0, 0, 1, AW_CLK_FACTOR_FIXED, /* k factor (fake) */ 0, 5, 0, 0, /* m factor */ 16, 4, 0, 0, /* p factor */ 31, /* gate */ 28, 1000, /* lock */ AW_CLK_HAS_GATE | AW_CLK_HAS_LOCK); /* flags */ static const char *pll_audio_mult_parents[] = {"pll_audio"}; FIXED_CLK(pll_audio_2x_clk, CLK_PLL_AUDIO_2X, /* id */ "pll_audio-2x", /* name */ pll_audio_mult_parents, /* parent */ 0, /* freq */ 2, /* mult */ 1, /* div */ 0); /* flags */ FIXED_CLK(pll_audio_4x_clk, CLK_PLL_AUDIO_4X, /* id */ "pll_audio-4x", /* name */ pll_audio_mult_parents, /* parent */ 0, /* freq */ 4, /* mult */ 1, /* div */ 0); /* flags */ FIXED_CLK(pll_audio_8x_clk, CLK_PLL_AUDIO_8X, /* id */ "pll_audio-8x", /* name */ pll_audio_mult_parents, /* parent */ 0, /* freq */ 8, /* mult */ 1, /* div */ 0); /* flags */ static const char *pll_video0_parents[] = {"osc24M"}; FRAC_CLK(pll_video0_clk, CLK_PLL_VIDEO0, /* id */ "pll_video0", pll_video0_parents, /* name, parents */ 0x10, /* offset */ 8, 7, 0, 0, /* n factor */ 0, 4, 0, 0, /* m factor */ 31, 28, 1000, /* gate, lock, lock retries */ AW_CLK_HAS_LOCK, /* flags */ 270000000, 297000000, /* freq0, freq1 */ 24, 25); /* mode sel, freq sel */ static const char *pll_video0_2x_parents[] = {"pll_video0"}; FIXED_CLK(pll_video0_2x_clk, CLK_PLL_VIDEO0_2X, /* id */ "pll_video0-2x", /* name */ pll_video0_2x_parents, /* parent */ 0, /* freq */ 2, /* mult */ 1, /* div */ 0); /* flags */ static const char *pll_ve_parents[] = {"osc24M"}; FRAC_CLK(pll_ve_clk, CLK_PLL_VE, /* id */ "pll_ve", pll_ve_parents, /* name, parents */ 0x18, /* offset */ 8, 7, 0, 0, /* n factor */ 0, 4, 0, 0, /* m factor */ 31, 28, 1000, /* gate, lock, lock retries */ AW_CLK_HAS_LOCK, /* flags */ 270000000, 297000000, /* freq0, freq1 */ 24, 25); /* mode sel, freq sel */ static const char *pll_ddr0_parents[] = {"osc24M"}; NKMP_CLK_WITH_UPDATE(pll_ddr0_clk, CLK_PLL_DDR0, /* id */ "pll_ddr0", pll_ddr0_parents, /* name, parents */ 0x20, /* offset */ 8, 5, 0, 0, /* n factor */ 4, 2, 0, 0, /* k factor */ 0, 2, 0, 0, /* m factor */ 0, 0, 1, AW_CLK_FACTOR_FIXED, /* p factor (fake) */ 31, /* gate */ 28, 1000, /* lock */ 20, /* update */ AW_CLK_HAS_GATE | AW_CLK_HAS_LOCK); /* flags */ static const char *pll_periph0_2x_parents[] = {"osc24M"}; static const char *pll_periph0_parents[] = {"pll_periph0_2x"}; NKMP_CLK(pll_periph0_2x_clk, CLK_PLL_PERIPH0_2X, /* id */ "pll_periph0_2x", pll_periph0_2x_parents, /* name, parents */ 0x28, /* offset */ 8, 5, 0, 0, /* n factor */ 4, 2, 0, 0, /* k factor */ 0, 0, 2, AW_CLK_FACTOR_FIXED, /* m factor (fake) */ 0, 0, 1, AW_CLK_FACTOR_FIXED, /* p factor (fake) */ 31, /* gate */ 28, 1000, /* lock */ AW_CLK_HAS_GATE | AW_CLK_HAS_LOCK); /* flags */ FIXED_CLK(pll_periph0_clk, CLK_PLL_PERIPH0, /* id */ "pll_periph0", /* name */ pll_periph0_parents, /* parent */ 0, /* freq */ 1, /* mult */ 2, /* div */ 0); /* flags */ static const char *pll_periph1_2x_parents[] = {"osc24M"}; static const char *pll_periph1_parents[] = {"pll_periph1_2x"}; NKMP_CLK(pll_periph1_2x_clk, CLK_PLL_PERIPH1_2X, /* id */ "pll_periph1_2x", pll_periph1_2x_parents, /* name, parents */ 0x2C, /* offset */ 8, 5, 0, 0, /* n factor */ 4, 2, 0, 0, /* k factor */ 0, 0, 2, AW_CLK_FACTOR_FIXED, /* m factor (fake) */ 0, 0, 1, AW_CLK_FACTOR_FIXED, /* p factor (fake) */ 31, /* gate */ 28, 1000, /* lock */ AW_CLK_HAS_GATE | AW_CLK_HAS_LOCK); /* flags */ FIXED_CLK(pll_periph1_clk, CLK_PLL_PERIPH1, /* id */ "pll_periph1", /* name */ pll_periph1_parents, /* parent */ 0, /* freq */ 1, /* mult */ 2, /* div */ 0); /* flags */ static const char *pll_video1_parents[] = {"osc24M"}; FRAC_CLK(pll_video1_clk, CLK_PLL_VIDEO1, /* id */ "pll_video1", pll_video1_parents, /* name, parents */ 0x30, /* offset */ 8, 7, 0, 0, /* n factor */ 0, 4, 0, 0, /* m factor */ 31, 28, 1000, /* gate, lock, lock retries */ AW_CLK_HAS_LOCK, /* flags */ 270000000, 297000000, /* freq0, freq1 */ 24, 25); /* mode sel, freq sel */ static const char *pll_gpu_parents[] = {"osc24M"}; FRAC_CLK(pll_gpu_clk, CLK_PLL_GPU, /* id */ "pll_gpu", pll_gpu_parents, /* name, parents */ 0x38, /* offset */ 8, 7, 0, 0, /* n factor */ 0, 4, 0, 0, /* m factor */ 31, 28, 1000, /* gate, lock, lock retries */ AW_CLK_HAS_LOCK, /* flags */ 270000000, 297000000, /* freq0, freq1 */ 24, 25); /* mode sel, freq sel */ /* PLL MIPI is missing */ static const char *pll_hsic_parents[] = {"osc24M"}; FRAC_CLK(pll_hsic_clk, CLK_PLL_HSIC, /* id */ "pll_hsic", pll_hsic_parents, /* name, parents */ 0x44, /* offset */ 8, 7, 0, 0, /* n factor */ 0, 4, 0, 0, /* m factor */ 31, 28, 1000, /* gate, lock, lock retries */ AW_CLK_HAS_LOCK, /* flags */ 270000000, 297000000, /* freq0, freq1 */ 24, 25); /* mode sel, freq sel */ static const char *pll_de_parents[] = {"osc24M"}; FRAC_CLK(pll_de_clk, CLK_PLL_DE, /* id */ "pll_de", pll_de_parents, /* name, parents */ 0x48, /* offset */ 8, 7, 0, 0, /* n factor */ 0, 4, 0, 0, /* m factor */ 31, 28, 1000, /* gate, lock, lock retries */ AW_CLK_HAS_LOCK, /* flags */ 270000000, 297000000, /* freq0, freq1 */ 24, 25); /* mode sel, freq sel */ static const char *pll_ddr1_parents[] = {"osc24M"}; NKMP_CLK_WITH_UPDATE(pll_ddr1_clk, CLK_PLL_DDR1, /* id */ "pll_ddr1", pll_ddr1_parents, /* name, parents */ 0x4C, /* offset */ 8, 7, 0, 0, /* n factor */ 0, 0, 1, AW_CLK_FACTOR_FIXED, /* k factor (fake) */ 0, 2, 0, 0, /* m factor */ 0, 0, 1, AW_CLK_FACTOR_FIXED, /* p factor (fake) */ 31, /* gate */ 28, 1000, /* lock */ 20, /* update */ AW_CLK_HAS_GATE | AW_CLK_HAS_LOCK); /* flags */ static const char *cpux_parents[] = {"osc32k", "osc24M", "pll_cpux"}; MUX_CLK(cpux_clk, CLK_CPUX, /* id */ "cpux", cpux_parents, /* name, parents */ 0x50, 16, 2); /* offset, shift, width */ static const char *axi_parents[] = {"cpux"}; DIV_CLK(axi_clk, CLK_AXI, /* id */ "axi", axi_parents, /* name, parents */ 0x50, /* offset */ 0, 2, /* shift, width */ 0, NULL); /* flags, div table */ static const char *apb_parents[] = {"cpux"}; DIV_CLK(apb_clk, CLK_APB, /* id */ "apb", apb_parents, /* name, parents */ 0x50, /* offset */ 8, 2, /* shift, width */ 0, NULL); /* flags, div table */ static const char *ahb1_parents[] = {"osc32k", "osc24M", "axi", "pll_periph0"}; PREDIV_CLK(ahb1_clk, CLK_AHB1, /* id */ "ahb1", ahb1_parents, /* name, parents */ 0x54, /* offset */ 12, 2, /* mux */ 4, 2, 0, AW_CLK_FACTOR_POWER_OF_TWO, /* div */ 6, 2, 0, AW_CLK_FACTOR_HAS_COND, /* prediv */ 12, 2, 3); /* prediv condition */ static const char *apb1_parents[] = {"ahb1"}; static struct clk_div_table apb1_div_table[] = { { .value = 0, .divider = 2, }, { .value = 1, .divider = 2, }, { .value = 2, .divider = 4, }, { .value = 3, .divider = 8, }, { }, }; DIV_CLK(apb1_clk, CLK_APB1, /* id */ "apb1", apb1_parents, /* name, parents */ 0x54, /* offset */ 8, 2, /* shift, width */ CLK_DIV_WITH_TABLE, /* flags */ apb1_div_table); /* div table */ static const char *apb2_parents[] = {"osc32k", "osc24M", "pll_periph0_2x", "pll_periph0_2x"}; NM_CLK(apb2_clk, CLK_APB2, /* id */ "apb2", apb2_parents, /* name, parents */ 0x58, /* offset */ 16, 2, 0, AW_CLK_FACTOR_POWER_OF_TWO, /* n factor */ 0, 5, 0, 0, /* m factor */ 24, 2, /* mux */ 0, /* gate */ AW_CLK_HAS_MUX); static const char *ahb2_parents[] = {"ahb1", "pll_periph0"}; PREDIV_CLK(ahb2_clk, CLK_AHB2, /* id */ "ahb2", ahb2_parents, /* name, parents */ 0x5c, /* offset */ 0, 2, /* mux */ 0, 0, 1, AW_CLK_FACTOR_FIXED, /* div */ 0, 0, 2, AW_CLK_FACTOR_HAS_COND | AW_CLK_FACTOR_FIXED, /* prediv */ 0, 2, 1); /* prediv condition */ static const char *ths_parents[] = {"osc24M"}; static struct clk_div_table ths_div_table[] = { { .value = 0, .divider = 1, }, { .value = 1, .divider = 2, }, { .value = 2, .divider = 4, }, { .value = 3, .divider = 6, }, { }, }; DIV_CLK(ths_clk, 0, /* id */ "thsdiv", ths_parents, /* name, parents */ 0x74, /* offset */ 0, 2, /* div shift, div width */ CLK_DIV_WITH_TABLE, /* flags */ ths_div_table); /* div table */ static const char *mod_parents[] = {"osc24M", "pll_periph0_2x", "pll_periph1_2x"}; NM_CLK(nand_clk, CLK_NAND, "nand", mod_parents, /* id, name, parents */ 0x80, /* offset */ 16, 2, 0, AW_CLK_FACTOR_POWER_OF_TWO, /* n factor */ 0, 4, 0, 0, /* m factor */ 24, 2, /* mux */ 31, /* gate */ AW_CLK_HAS_GATE | AW_CLK_HAS_MUX); /* flags */ NM_CLK(mmc0_clk, CLK_MMC0, "mmc0", mod_parents, /* id, name, parents */ 0x88, /* offset */ 16, 2, 0, AW_CLK_FACTOR_POWER_OF_TWO, /* n factor */ 0, 4, 0, 0, /* m factor */ 24, 2, /* mux */ 31, /* gate */ AW_CLK_HAS_GATE | AW_CLK_HAS_MUX | AW_CLK_REPARENT); /* flags */ NM_CLK(mmc1_clk, CLK_MMC1, "mmc1", mod_parents, /* id, name, parents */ 0x8c, /* offset */ 16, 2, 0, AW_CLK_FACTOR_POWER_OF_TWO, /* n factor */ 0, 4, 0, 0, /* m factor */ 24, 2, /* mux */ 31, /* gate */ AW_CLK_HAS_GATE | AW_CLK_HAS_MUX | AW_CLK_REPARENT); /* flags */ NM_CLK(mmc2_clk, CLK_MMC2, "mmc2", mod_parents, /* id, name, parents */ 0x90, /* offset */ 16, 2, 0, AW_CLK_FACTOR_POWER_OF_TWO, /* n factor */ 0, 4, 0, 0, /* m factor */ 24, 2, /* mux */ 31, /* gate */ AW_CLK_HAS_GATE | AW_CLK_HAS_MUX | AW_CLK_REPARENT); /* flags */ static const char *ts_parents[] = {"osc24M", "pll_periph0"}; NM_CLK(ts_clk, CLK_TS, "ts", ts_parents, /* id, name, parents */ 0x98, /* offset */ 16, 2, 0, AW_CLK_FACTOR_POWER_OF_TWO, /* n factor */ 0, 4, 0, 0, /* m factor */ 24, 2, /* mux */ 31, /* gate */ AW_CLK_HAS_GATE | AW_CLK_HAS_MUX); /* flags */ NM_CLK(ce_clk, CLK_CE, "ce", mod_parents, /* id, name, parents */ 0x9C, /* offset */ 16, 2, 0, AW_CLK_FACTOR_POWER_OF_TWO, /* n factor */ 0, 4, 0, 0, /* m factor */ 24, 2, /* mux */ 31, /* gate */ AW_CLK_HAS_GATE | AW_CLK_HAS_MUX); /* flags */ NM_CLK(spi0_clk, CLK_SPI0, "spi0", mod_parents, /* id, name, parents */ 0xA0, /* offset */ 16, 2, 0, AW_CLK_FACTOR_POWER_OF_TWO, /* n factor */ 0, 4, 0, 0, /* m factor */ 24, 2, /* mux */ 31, /* gate */ AW_CLK_HAS_GATE | AW_CLK_HAS_MUX | AW_CLK_REPARENT); /* flags */ NM_CLK(spi1_clk, CLK_SPI1, "spi1", mod_parents, /* id, name, parents */ 0xA4, /* offset */ 16, 2, 0, AW_CLK_FACTOR_POWER_OF_TWO, /* n factor */ 0, 4, 0, 0, /* m factor */ 24, 2, /* mux */ 31, /* gate */ AW_CLK_HAS_GATE | AW_CLK_HAS_MUX | AW_CLK_REPARENT); /* flags */ static const char *i2s_parents[] = {"pll_audio-8x", "pll_audio-4x", "pll_audio-2x", "pll_audio"}; MUX_CLK(i2s0mux_clk, 0, "i2s0mux", i2s_parents, /* id, name, parents */ 0xb0, 16, 2); /* offset, mux shift, mux width */ MUX_CLK(i2s1mux_clk, 0, "i2s1mux", i2s_parents, /* id, name, parents */ 0xb4, 16, 2); /* offset, mux shift, mux width */ MUX_CLK(i2s2mux_clk, 0, "i2s2mux", i2s_parents, /* id, name, parents */ 0xb8, 16, 2); /* offset, mux shift, mux width */ static const char *spdif_parents[] = {"pll_audio"}; NM_CLK(spdif_clk, CLK_SPDIF, "spdif", spdif_parents, /* id, name, parents */ 0xC0, /* offset */ 0, 0, 1, AW_CLK_FACTOR_FIXED, /* n factor (fake); */ 0, 4, 0, 0, /* m factor */ 0, 0, /* mux */ 31, /* gate */ AW_CLK_HAS_GATE); /* flags */ /* USBPHY clk sel */ /* DRAM needs update bit */ static const char *dram_parents[] = {"pll_ddr0", "pll_ddr1"}; NM_CLK(dram_clk, CLK_DRAM, "dram", dram_parents, /* id, name, parents */ 0xF4, /* offset */ 0, 0, 1, AW_CLK_FACTOR_FIXED, /* n factor (fake) */ 0, 2, 0, 0, /* m factor */ 20, 2, /* mux */ 0, /* gate */ AW_CLK_HAS_MUX); /* flags */ static const char *de_parents[] = {"pll_periph0_2x", "pll_de"}; NM_CLK(de_clk, CLK_DE, "de", de_parents, /* id, name, parents */ 0x104, /* offset */ 0, 0, 1, AW_CLK_FACTOR_FIXED, /* n factor (fake) */ 0, 4, 0, 0, /* m factor */ 24, 2, /* mux */ 31, /* gate */ AW_CLK_HAS_MUX | AW_CLK_HAS_GATE); /* flags */ /* TCON0/1 Needs mux table */ static const char *tcon1_parents[] = {"pll_video0", "pll_video0", "pll_video1"}; NM_CLK(tcon1_clk, CLK_TCON1, "tcon1", tcon1_parents, 0x11C, 0, 0, 1, AW_CLK_FACTOR_FIXED, 0, 4, 0, 0, 24, 2, 31, AW_CLK_HAS_MUX | AW_CLK_HAS_GATE); static const char *deinterlace_parents[] = {"pll_periph0", "pll_periph1"}; NM_CLK(deinterlace_clk, CLK_DEINTERLACE, "deinterlace", deinterlace_parents, /* id, name, parents */ 0x124, /* offset */ 0, 0, 1, AW_CLK_FACTOR_FIXED, /* n factor (fake) */ 0, 4, 0, 0, /* m factor */ 24, 2, /* mux */ 31, /* gate */ AW_CLK_HAS_MUX | AW_CLK_HAS_GATE); /* flags */ static const char *csi_sclk_parents[] = {"pll_periph0", "pll_periph1"}; NM_CLK(csi_sclk_clk, CLK_CSI_SCLK, "csi-sclk", csi_sclk_parents, /* id, name, parents */ 0x134, /* offset */ 0, 0, 1, AW_CLK_FACTOR_FIXED, /* n factor (fake) */ 16, 4, 0, 0, /* m factor */ 24, 2, /* mux */ 31, /* gate */ AW_CLK_HAS_MUX | AW_CLK_HAS_GATE); /* flags */ static const char *csi_mclk_parents[] = {"osc24M", "pll_video0", "pll_periph1"}; NM_CLK(csi_mclk_clk, CLK_CSI_MCLK, "csi-mclk", csi_mclk_parents, /* id, name, parents */ 0x134, /* offset */ 0, 0, 1, AW_CLK_FACTOR_FIXED, /* n factor (fake) */ 0, 4, 0, 0, /* m factor */ 8, 2, /* mux */ 15, /* gate */ AW_CLK_HAS_MUX | AW_CLK_HAS_GATE); /* flags */ static const char *ve_parents[] = {"pll_ve"}; NM_CLK(ve_clk, CLK_VE, "ve", ve_parents, /* id, name, parents */ 0x13C, /* offset */ 16, 3, 0, 0, /* n factor */ 0, 0, 1, AW_CLK_FACTOR_FIXED, /* m factor (fake) */ 0, 0, /* mux */ 31, /* gate */ AW_CLK_HAS_GATE); /* flags */ static const char *hdmi_parents[] = {"pll_video0"}; NM_CLK(hdmi_clk, CLK_HDMI, "hdmi", hdmi_parents, /* id, name, parents */ 0x150, /* offset */ 0, 0, 1, AW_CLK_FACTOR_FIXED, /* n factor (fake) */ 0, 4, 0, 0, /* m factor */ 24, 2, /* mux */ 31, /* gate */ AW_CLK_HAS_MUX | AW_CLK_HAS_GATE); /* flags */ static const char *mbus_parents[] = {"osc24M", "pll_periph0_2x", "pll_ddr0"}; NM_CLK(mbus_clk, CLK_MBUS, "mbus", mbus_parents, /* id, name, parents */ 0x15C, /* offset */ 0, 0, 1, AW_CLK_FACTOR_FIXED, /* n factor (fake) */ 0, 3, 0, 0, /* m factor */ 24, 2, /* mux */ 31, /* gate */ AW_CLK_HAS_MUX | AW_CLK_HAS_GATE); /* flags */ static const char *gpu_parents[] = {"pll_gpu"}; NM_CLK(gpu_clk, CLK_GPU, "gpu", gpu_parents, /* id, name, parents */ 0x1A0, /* offset */ 0, 2, 0, 0, /* n factor */ 0, 0, 1, AW_CLK_FACTOR_FIXED, /* m factor (fake) */ 0, 0, /* mux */ 31, /* gate */ AW_CLK_HAS_GATE); /* flags */ static struct aw_ccung_clk a64_ccu_clks[] = { { .type = AW_CLK_NKMP, .clk.nkmp = &pll_cpux_clk}, { .type = AW_CLK_NKMP, .clk.nkmp = &pll_audio_clk}, { .type = AW_CLK_FRAC, .clk.frac = &pll_video0_clk}, { .type = AW_CLK_FRAC, .clk.frac = &pll_ve_clk}, { .type = AW_CLK_NKMP, .clk.nkmp = &pll_ddr0_clk}, { .type = AW_CLK_NKMP, .clk.nkmp = &pll_periph0_2x_clk}, { .type = AW_CLK_NKMP, .clk.nkmp = &pll_periph1_2x_clk}, { .type = AW_CLK_FRAC, .clk.frac = &pll_video1_clk}, { .type = AW_CLK_FRAC, .clk.frac = &pll_gpu_clk}, /* PLL_MIPI */ { .type = AW_CLK_FRAC, .clk.frac = &pll_hsic_clk}, { .type = AW_CLK_FRAC, .clk.frac = &pll_de_clk}, { .type = AW_CLK_NKMP, .clk.nkmp = &pll_ddr1_clk}, { .type = AW_CLK_NM, .clk.nm = &apb2_clk}, { .type = AW_CLK_NM, .clk.nm = &nand_clk}, { .type = AW_CLK_NM, .clk.nm = &mmc0_clk}, { .type = AW_CLK_NM, .clk.nm = &mmc1_clk}, { .type = AW_CLK_NM, .clk.nm = &mmc2_clk}, { .type = AW_CLK_NM, .clk.nm = &ts_clk}, { .type = AW_CLK_NM, .clk.nm = &ce_clk}, { .type = AW_CLK_NM, .clk.nm = &spi0_clk}, { .type = AW_CLK_NM, .clk.nm = &spi1_clk}, { .type = AW_CLK_NM, .clk.nm = &spdif_clk}, { .type = AW_CLK_NM, .clk.nm = &dram_clk}, { .type = AW_CLK_NM, .clk.nm = &de_clk}, { .type = AW_CLK_NM, .clk.nm = &tcon1_clk}, { .type = AW_CLK_NM, .clk.nm = &deinterlace_clk}, { .type = AW_CLK_NM, .clk.nm = &csi_sclk_clk}, { .type = AW_CLK_NM, .clk.nm = &csi_mclk_clk}, { .type = AW_CLK_NM, .clk.nm = &ve_clk}, { .type = AW_CLK_NM, .clk.nm = &hdmi_clk}, { .type = AW_CLK_NM, .clk.nm = &mbus_clk}, { .type = AW_CLK_NM, .clk.nm = &gpu_clk}, { .type = AW_CLK_PREDIV_MUX, .clk.prediv_mux = &ahb1_clk}, { .type = AW_CLK_PREDIV_MUX, .clk.prediv_mux = &ahb2_clk}, { .type = AW_CLK_MUX, .clk.mux = &cpux_clk}, { .type = AW_CLK_MUX, .clk.mux = &i2s0mux_clk}, { .type = AW_CLK_MUX, .clk.mux = &i2s1mux_clk}, { .type = AW_CLK_MUX, .clk.mux = &i2s2mux_clk}, { .type = AW_CLK_DIV, .clk.div = &axi_clk}, { .type = AW_CLK_DIV, .clk.div = &apb1_clk}, { .type = AW_CLK_DIV, .clk.div = &apb_clk}, { .type = AW_CLK_DIV, .clk.div = &ths_clk}, { .type = AW_CLK_FIXED, .clk.fixed = &osc12m_clk}, { .type = AW_CLK_FIXED, .clk.fixed = &pll_periph0_clk}, { .type = AW_CLK_FIXED, .clk.fixed = &pll_periph1_clk}, { .type = AW_CLK_FIXED, .clk.fixed = &pll_audio_2x_clk}, { .type = AW_CLK_FIXED, .clk.fixed = &pll_audio_4x_clk}, { .type = AW_CLK_FIXED, .clk.fixed = &pll_audio_8x_clk}, { .type = AW_CLK_FIXED, .clk.fixed = &pll_video0_2x_clk}, }; static struct aw_clk_init a64_init_clks[] = { {"ahb1", "pll_periph0", 0, false}, {"ahb2", "pll_periph0", 0, false}, {"dram", "pll_ddr0", 0, false}, }; static int ccu_a64_probe(device_t dev) { if (!ofw_bus_status_okay(dev)) return (ENXIO); if (!ofw_bus_is_compatible(dev, "allwinner,sun50i-a64-ccu")) return (ENXIO); device_set_desc(dev, "Allwinner A64 Clock Control Unit NG"); return (BUS_PROBE_DEFAULT); } static int ccu_a64_attach(device_t dev) { struct aw_ccung_softc *sc; sc = device_get_softc(dev); sc->resets = a64_ccu_resets; sc->nresets = nitems(a64_ccu_resets); sc->gates = a64_ccu_gates; sc->ngates = nitems(a64_ccu_gates); sc->clks = a64_ccu_clks; sc->nclks = nitems(a64_ccu_clks); sc->clk_init = a64_init_clks; sc->n_clk_init = nitems(a64_init_clks); return (aw_ccung_attach(dev)); } static device_method_t ccu_a64ng_methods[] = { /* Device interface */ DEVMETHOD(device_probe, ccu_a64_probe), DEVMETHOD(device_attach, ccu_a64_attach), DEVMETHOD_END }; static devclass_t ccu_a64ng_devclass; DEFINE_CLASS_1(ccu_a64ng, ccu_a64ng_driver, ccu_a64ng_methods, sizeof(struct aw_ccung_softc), aw_ccung_driver); EARLY_DRIVER_MODULE(ccu_a64ng, simplebus, ccu_a64ng_driver, - ccu_a64ng_devclass, 0, 0, BUS_PASS_BUS + BUS_PASS_ORDER_LAST); + ccu_a64ng_devclass, 0, 0, BUS_PASS_RESOURCE + BUS_PASS_ORDER_MIDDLE); Index: head/sys/arm/allwinner/clkng/ccu_a83t.c =================================================================== --- head/sys/arm/allwinner/clkng/ccu_a83t.c (revision 350841) +++ head/sys/arm/allwinner/clkng/ccu_a83t.c (revision 350842) @@ -1,789 +1,789 @@ /*- * SPDX-License-Identifier: BSD-2-Clause-FreeBSD * * Copyright (c) 2017 Kyle Evans * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. * * $FreeBSD$ */ #include __FBSDID("$FreeBSD$"); #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include /* Non-exported clocks */ #define CLK_PLL_C0CPUX 0 #define CLK_PLL_C1CPUX 1 #define CLK_PLL_AUDIO 2 #define CLK_PLL_VIDEO0 3 #define CLK_PLL_VE 4 #define CLK_PLL_DDR 5 #define CLK_PLL_GPU 7 #define CLK_PLL_HSIC 8 #define CLK_PLL_VIDEO1 10 #define CLK_AXI0 13 #define CLK_AXI1 14 #define CLK_AHB1 15 #define CLK_APB1 16 #define CLK_APB2 17 #define CLK_AHB2 18 #define CLK_CCI400 58 #define CLK_DRAM 82 #define CLK_MBUS 95 /* Non-exported fixed clocks */ #define CLK_OSC_12M 150 static struct aw_ccung_reset a83t_ccu_resets[] = { CCU_RESET(RST_USB_PHY0, 0xcc, 0) CCU_RESET(RST_USB_PHY1, 0xcc, 1) CCU_RESET(RST_USB_HSIC, 0xcc, 2) CCU_RESET(RST_DRAM, 0xf4, 31) CCU_RESET(RST_MBUS, 0xfc, 31) CCU_RESET(RST_BUS_MIPI_DSI, 0x2c0, 1) CCU_RESET(RST_BUS_SS, 0x2c0, 5) CCU_RESET(RST_BUS_DMA, 0x2c0, 6) CCU_RESET(RST_BUS_MMC0, 0x2c0, 8) CCU_RESET(RST_BUS_MMC1, 0x2c0, 9) CCU_RESET(RST_BUS_MMC2, 0x2c0, 10) CCU_RESET(RST_BUS_NAND, 0x2c0, 13) CCU_RESET(RST_BUS_DRAM, 0x2c0, 14) CCU_RESET(RST_BUS_EMAC, 0x2c0, 17) CCU_RESET(RST_BUS_HSTIMER, 0x2c0, 19) CCU_RESET(RST_BUS_SPI0, 0x2c0, 20) CCU_RESET(RST_BUS_SPI1, 0x2c0, 21) CCU_RESET(RST_BUS_OTG, 0x2c0, 24) CCU_RESET(RST_BUS_EHCI0, 0x2c0, 26) CCU_RESET(RST_BUS_EHCI1, 0x2c0, 27) CCU_RESET(RST_BUS_OHCI0, 0x2c0, 29) CCU_RESET(RST_BUS_VE, 0x2c4, 0) CCU_RESET(RST_BUS_TCON0, 0x2c4, 4) CCU_RESET(RST_BUS_TCON1, 0x2c4, 5) CCU_RESET(RST_BUS_CSI, 0x2c4, 8) CCU_RESET(RST_BUS_HDMI0, 0x2c4, 10) CCU_RESET(RST_BUS_HDMI1, 0x2c4, 11) CCU_RESET(RST_BUS_DE, 0x2c4, 12) CCU_RESET(RST_BUS_GPU, 0x2c4, 20) CCU_RESET(RST_BUS_MSGBOX, 0x2c4, 21) CCU_RESET(RST_BUS_SPINLOCK, 0x2c4, 22) CCU_RESET(RST_BUS_LVDS, 0x2c8, 0) CCU_RESET(RST_BUS_SPDIF, 0x2d0, 1) CCU_RESET(RST_BUS_I2S0, 0x2d0, 12) CCU_RESET(RST_BUS_I2S1, 0x2d0, 13) CCU_RESET(RST_BUS_I2S2, 0x2d0, 14) CCU_RESET(RST_BUS_TDM, 0x2d0, 15) CCU_RESET(RST_BUS_I2C0, 0x2d8, 0) CCU_RESET(RST_BUS_I2C1, 0x2d8, 1) CCU_RESET(RST_BUS_I2C2, 0x2d8, 2) CCU_RESET(RST_BUS_UART0, 0x2d8, 16) CCU_RESET(RST_BUS_UART1, 0x2d8, 17) CCU_RESET(RST_BUS_UART2, 0x2d8, 18) CCU_RESET(RST_BUS_UART3, 0x2d8, 19) CCU_RESET(RST_BUS_UART4, 0x2d8, 20) }; static struct aw_ccung_gate a83t_ccu_gates[] = { CCU_GATE(CLK_BUS_MIPI_DSI, "bus-mipi-dsi", "ahb1", 0x60, 1) CCU_GATE(CLK_BUS_SS, "bus-ss", "ahb1", 0x60, 5) CCU_GATE(CLK_BUS_DMA, "bus-dma", "ahb1", 0x60, 6) CCU_GATE(CLK_BUS_MMC0, "bus-mmc0", "ahb1", 0x60, 8) CCU_GATE(CLK_BUS_MMC1, "bus-mmc1", "ahb1", 0x60, 9) CCU_GATE(CLK_BUS_MMC2, "bus-mmc2", "ahb1", 0x60, 10) CCU_GATE(CLK_BUS_NAND, "bus-nand", "ahb1", 0x60, 13) CCU_GATE(CLK_BUS_DRAM, "bus-dram", "ahb1", 0x60, 14) CCU_GATE(CLK_BUS_EMAC, "bus-emac", "ahb1", 0x60, 17) CCU_GATE(CLK_BUS_HSTIMER, "bus-hstimer", "ahb1", 0x60, 19) CCU_GATE(CLK_BUS_SPI0, "bus-spi0", "ahb1", 0x60, 20) CCU_GATE(CLK_BUS_SPI1, "bus-spi1", "ahb1", 0x60, 21) CCU_GATE(CLK_BUS_OTG, "bus-otg", "ahb1", 0x60, 24) CCU_GATE(CLK_BUS_EHCI0, "bus-ehci0", "ahb2", 0x60, 26) CCU_GATE(CLK_BUS_EHCI1, "bus-ehci1", "ahb2", 0x60, 27) CCU_GATE(CLK_BUS_OHCI0, "bus-ohci0", "ahb2", 0x60, 29) CCU_GATE(CLK_BUS_VE, "bus-ve", "ahb1", 0x64, 0) CCU_GATE(CLK_BUS_TCON0, "bus-tcon0", "ahb1", 0x64, 4) CCU_GATE(CLK_BUS_TCON1, "bus-tcon1", "ahb1", 0x64, 5) CCU_GATE(CLK_BUS_CSI, "bus-csi", "ahb1", 0x64, 8) CCU_GATE(CLK_BUS_HDMI, "bus-hdmi", "ahb1", 0x64, 11) CCU_GATE(CLK_BUS_DE, "bus-de", "ahb1", 0x64, 12) CCU_GATE(CLK_BUS_GPU, "bus-gpu", "ahb1", 0x64, 20) CCU_GATE(CLK_BUS_MSGBOX, "bus-msgbox", "ahb1", 0x64, 21) CCU_GATE(CLK_BUS_SPINLOCK, "bus-spinlock", "ahb1", 0x64, 22) CCU_GATE(CLK_BUS_SPDIF, "bus-spdif", "apb1", 0x68, 1) CCU_GATE(CLK_BUS_PIO, "bus-pio", "apb1", 0x68, 5) CCU_GATE(CLK_BUS_I2S0, "bus-i2s0", "apb1", 0x68, 12) CCU_GATE(CLK_BUS_I2S1, "bus-i2s1", "apb1", 0x68, 13) CCU_GATE(CLK_BUS_I2S2, "bus-i2s2", "apb1", 0x68, 14) CCU_GATE(CLK_BUS_TDM, "bus-tdm", "apb1", 0x68, 15) CCU_GATE(CLK_BUS_I2C0, "bus-i2c0", "apb2", 0x6c, 0) CCU_GATE(CLK_BUS_I2C1, "bus-i2c1", "apb2", 0x6c, 1) CCU_GATE(CLK_BUS_I2C2, "bus-i2c2", "apb2", 0x6c, 2) CCU_GATE(CLK_BUS_UART0, "bus-uart0", "apb2", 0x6c, 16) CCU_GATE(CLK_BUS_UART1, "bus-uart1", "apb2", 0x6c, 17) CCU_GATE(CLK_BUS_UART2, "bus-uart2", "apb2", 0x6c, 18) CCU_GATE(CLK_BUS_UART3, "bus-uart3", "apb2", 0x6c, 19) CCU_GATE(CLK_BUS_UART4, "bus-uart4", "apb2", 0x6c, 20) CCU_GATE(CLK_USB_PHY0, "usb-phy0", "osc24M", 0xcc, 8) CCU_GATE(CLK_USB_PHY1, "usb-phy1", "osc24M", 0xcc, 9) CCU_GATE(CLK_USB_HSIC, "usb-hsic", "pll_hsic", 0xcc, 10) CCU_GATE(CLK_USB_HSIC_12M, "usb-hsic-12M", "osc12M", 0xcc, 11) CCU_GATE(CLK_USB_OHCI0, "usb-ohci0", "osc12M", 0xcc, 16) CCU_GATE(CLK_DRAM_VE, "dram-ve", "dram", 0x100, 0) CCU_GATE(CLK_DRAM_CSI, "dram-csi", "dram", 0x100, 1) CCU_GATE(CLK_CSI_MISC, "csi-misc", "osc24M", 0x130, 16) CCU_GATE(CLK_MIPI_CSI, "mipi-csi", "osc24M", 0x130, 31) CCU_GATE(CLK_AVS, "avs", "osc24M", 0x144, 31) CCU_GATE(CLK_HDMI_SLOW, "hdmi-ddc", "osc24M", 0x154, 31) }; static const char *osc12m_parents[] = {"osc24M"}; FIXED_CLK(osc12m_clk, CLK_OSC_12M, /* id */ "osc12M", osc12m_parents, /* name, parents */ 0, /* freq */ 1, /* mult */ 2, /* div */ 0); /* flags */ /* CPU PLL are 24Mhz * N / P */ static const char *pll_c0cpux_parents[] = {"osc24M"}; static const char *pll_c1cpux_parents[] = {"osc24M"}; NKMP_CLK(pll_c0cpux_clk, CLK_PLL_C0CPUX, /* id */ "pll_c0cpux", pll_c0cpux_parents, /* name, parents */ 0x00, /* offset */ 8, 8, 0, AW_CLK_FACTOR_ZERO_BASED, /* n factor */ 0, 0, 1, AW_CLK_FACTOR_FIXED, /* k factor (fake) */ 0, 0, 1, AW_CLK_FACTOR_FIXED, /* m factor */ 0, 0, 1, AW_CLK_FACTOR_FIXED, /* p factor (fake) */ 0, 0, /* lock */ 31, /* gate */ AW_CLK_HAS_GATE | AW_CLK_SCALE_CHANGE); /* flags */ NKMP_CLK(pll_c1cpux_clk, CLK_PLL_C1CPUX, /* id */ "pll_c1cpux", pll_c1cpux_parents, /* name, parents */ 0x04, /* offset */ 8, 8, 0, AW_CLK_FACTOR_ZERO_BASED, /* n factor */ 0, 0, 1, AW_CLK_FACTOR_FIXED, /* k factor (fake) */ 0, 0, 1, AW_CLK_FACTOR_FIXED, /* m factor */ 0, 0, 1, AW_CLK_FACTOR_FIXED, /* p factor (fake) */ 0, 0, /* lock */ 31, /* gate */ AW_CLK_HAS_GATE | AW_CLK_SCALE_CHANGE); /* flags */ static const char *pll_audio_parents[] = {"osc24M"}; NKMP_CLK(pll_audio_clk, CLK_PLL_AUDIO, /* id */ "pll_audio", pll_audio_parents, /* name, parents */ 0x08, /* offset */ 8, 8, 0, AW_CLK_FACTOR_ZERO_BASED, /* n factor */ 0, 0, 1, AW_CLK_FACTOR_FIXED, /* k factor (fake) */ 16, 1, 0, 0, /* m factor */ 18, 1, 0, 0, /* p factor */ 31, /* gate */ 0, 0, /* lock */ AW_CLK_HAS_GATE); /* flags */ static const char *pll_video0_parents[] = {"osc24M"}; NKMP_CLK(pll_video0_clk, CLK_PLL_VIDEO0, /* id */ "pll_video0", pll_video0_parents, /* name, parents */ 0x10, /* offset */ 8, 8, 0, AW_CLK_FACTOR_ZERO_BASED, /* n factor */ 0, 0, 1, AW_CLK_FACTOR_FIXED, /* k factor (fake) */ 16, 1, 0, 0, /* m factor */ 0, 2, 0, AW_CLK_FACTOR_POWER_OF_TWO, /* p factor */ 31, /* gate */ 0, 0, /* lock */ AW_CLK_HAS_GATE); /* flags */ static const char *pll_ve_parents[] = {"osc24M"}; NKMP_CLK(pll_ve_clk, CLK_PLL_VE, /* id */ "pll_ve", pll_ve_parents, /* name, parents */ 0x18, /* offset */ 8, 8, 0, AW_CLK_FACTOR_ZERO_BASED, /* n factor */ 0, 0, 1, AW_CLK_FACTOR_FIXED, /* k factor (fake) */ 16, 1, 0, 0, /* m factor */ 18, 1, 0, 0, /* p factor */ 31, /* gate */ 0, 0, /* lock */ AW_CLK_HAS_GATE); /* flags */ static const char *pll_ddr_parents[] = {"osc24M"}; NKMP_CLK(pll_ddr_clk, CLK_PLL_DDR, /* id */ "pll_ddr", pll_ddr_parents, /* name, parents */ 0x20, /* offset */ 8, 5, 0, 0, /* n factor */ 0, 0, 1, AW_CLK_FACTOR_FIXED, /* k factor (fake) */ 16, 1, 0, 0, /* m factor */ 18, 1, 0, 0, /* p factor */ 31, /* gate */ 0, 0, /* lock */ AW_CLK_HAS_GATE); /* flags */ static const char *pll_periph_parents[] = {"osc24M"}; NKMP_CLK(pll_periph_clk, CLK_PLL_PERIPH, /* id */ "pll_periph", pll_periph_parents, /* name, parents */ 0x28, /* offset */ 8, 8, 0, AW_CLK_FACTOR_ZERO_BASED, /* n factor */ 0, 0, 1, AW_CLK_FACTOR_FIXED, /* k factor (fake) */ 16, 1, 1, 0, /* m factor */ 18, 1, 1, 0, /* p factor */ 31, /* gate */ 0, 0, /* lock */ AW_CLK_HAS_GATE); /* flags */ static const char *pll_gpu_parents[] = {"osc24M"}; NKMP_CLK(pll_gpu_clk, CLK_PLL_GPU, /* id */ "pll_gpu", pll_gpu_parents, /* name, parents */ 0x38, /* offset */ 8, 8, 0, AW_CLK_FACTOR_ZERO_BASED, /* n factor */ 0, 0, 1, AW_CLK_FACTOR_FIXED, /* k factor (fake) */ 16, 1, 1, 0, /* m factor */ 18, 1, 1, 0, /* p factor */ 31, /* gate */ 0, 0, /* lock */ AW_CLK_HAS_GATE); /* flags */ static const char *pll_hsic_parents[] = {"osc24M"}; NKMP_CLK(pll_hsic_clk, CLK_PLL_HSIC, /* id */ "pll_hsic", pll_hsic_parents, /* name, parents */ 0x44, /* offset */ 8, 8, 0, AW_CLK_FACTOR_ZERO_BASED, /* n factor */ 0, 0, 1, AW_CLK_FACTOR_FIXED, /* k factor (fake) */ 16, 1, 1, 0, /* m factor */ 18, 1, 1, 0, /* p factor */ 31, /* gate */ 0, 0, /* lock */ AW_CLK_HAS_GATE); /* flags */ static const char *pll_de_parents[] = {"osc24M"}; NKMP_CLK(pll_de_clk, CLK_PLL_DE, /* id */ "pll_de", pll_de_parents, /* name, parents */ 0x48, /* offset */ 8, 8, 0, AW_CLK_FACTOR_ZERO_BASED, /* n factor */ 0, 0, 1, AW_CLK_FACTOR_FIXED, /* k factor (fake) */ 16, 1, 1, 0, /* m factor */ 18, 1, 1, 0, /* p factor */ 31, /* gate */ 0, 0, /* lock */ AW_CLK_HAS_GATE); /* flags */ static const char *pll_video1_parents[] = {"osc24M"}; NKMP_CLK(pll_video1_clk, CLK_PLL_VIDEO1, /* id */ "pll_video1", pll_video1_parents, /* name, parents */ 0x4c, /* offset */ 8, 8, 0, AW_CLK_FACTOR_ZERO_BASED, /* n factor */ 0, 0, 1, AW_CLK_FACTOR_FIXED, /* k factor (fake) */ 16, 1, 1, 0, /* m factor */ 0, 2, 0, AW_CLK_FACTOR_POWER_OF_TWO, /* p factor */ 31, /* gate */ 0, 0, /* lock */ AW_CLK_HAS_GATE); /* flags */ static const char *c0cpux_parents[] = {"osc24M", "pll_c0cpux"}; MUX_CLK(c0cpux_clk, CLK_C0CPUX, /* id */ "c0cpux", c0cpux_parents, /* name, parents */ 0x50, 12, 1); /* offset, shift, width */ static const char *c1cpux_parents[] = {"osc24M", "pll_c1cpux"}; MUX_CLK(c1cpux_clk, CLK_C1CPUX, /* id */ "c1cpux", c1cpux_parents, /* name, parents */ 0x50, 28, 1); /* offset, shift, width */ static const char *axi0_parents[] = {"c0cpux"}; DIV_CLK(axi0_clk, CLK_AXI0, /* id */ "axi0", axi0_parents, /* name, parents */ 0x50, /* offset */ 0, 2, /* shift, width */ 0, NULL); /* flags, div table */ static const char *axi1_parents[] = {"c1cpux"}; DIV_CLK(axi1_clk, CLK_AXI1, /* id */ "axi1", axi1_parents, /* name, parents */ 0x50, /* offset */ 16, 2, /* shift, width */ 0, NULL); /* flags, div table */ static const char *ahb1_parents[] = {"osc16M-d512", "osc24M", "pll_periph", "pll_periph"}; PREDIV_CLK_WITH_MASK(ahb1_clk, CLK_AHB1, /* id */ "ahb1", ahb1_parents, /* name, parents */ 0x54, /* offset */ 12, 2, /* mux */ 4, 2, 0, AW_CLK_FACTOR_POWER_OF_TWO, /* div */ 6, 2, 0, AW_CLK_FACTOR_HAS_COND, /* prediv */ (2 << 12), (2 << 12)); /* prediv condition */ static const char *apb1_parents[] = {"ahb1"}; DIV_CLK(apb1_clk, CLK_APB1, /* id */ "apb1", apb1_parents, /* name, parents */ 0x54, /* offset */ 8, 2, /* shift, width */ 0, NULL); /* flags, div table */ static const char *apb2_parents[] = {"osc16M-d512", "osc24M", "pll_periph", "pll_periph"}; NM_CLK(apb2_clk, CLK_APB2, /* id */ "apb2", apb2_parents, /* name, parents */ 0x58, /* offset */ 16, 2, 0, AW_CLK_FACTOR_POWER_OF_TWO, /* n factor */ 0, 5, 0, 0, /* m factor */ 24, 2, /* mux */ 0, /* gate */ AW_CLK_HAS_MUX); static const char *ahb2_parents[] = {"ahb1", "pll_periph"}; PREDIV_CLK(ahb2_clk, CLK_AHB2, /* id */ "ahb2", ahb2_parents, /* name, parents */ 0x5c, 0, 2, /* mux */ 0, 0, 1, AW_CLK_FACTOR_FIXED, /* div (fake) */ 0, 0, 2, AW_CLK_FACTOR_HAS_COND | AW_CLK_FACTOR_FIXED, /* prediv */ 0, 2, 1); /* prediv cond */ /* Actually has a divider, but we don't use it */ static const char *cci400_parents[] = {"osc24M", "pll_periph", "pll_hsic"}; MUX_CLK(cci400_clk, CLK_CCI400, /* id */ "cci400", cci400_parents, /* name, parents */ 0x78, 24, 2); /* offset, shift, width */ static const char *mod_parents[] = {"osc24M", "pll_periph"}; NM_CLK(nand_clk, CLK_NAND, /* id */ "nand", mod_parents, /* name, parents */ 0x80, /* offset */ 16, 2, 0, AW_CLK_FACTOR_POWER_OF_TWO, /* n factor */ 0, 4, 0, 0, /* m factor */ 24, 2, /* mux */ 31, /* gate */ AW_CLK_HAS_GATE | AW_CLK_HAS_MUX); NM_CLK(mmc0_clk, CLK_MMC0, /* id */ "mmc0", mod_parents, /* name, parents */ 0x88, /* offset */ 16, 2, 0, AW_CLK_FACTOR_POWER_OF_TWO, /* n factor */ 0, 4, 0, 0, /* m factor */ 24, 2, /* mux */ 31, /* gate */ AW_CLK_HAS_GATE | AW_CLK_HAS_MUX | AW_CLK_REPARENT); NM_CLK(mmc1_clk, CLK_MMC1, /* id */ "mmc1", mod_parents, /* name, parents */ 0x8c, /* offset */ 16, 2, 0, AW_CLK_FACTOR_POWER_OF_TWO, /* n factor */ 0, 4, 0, 0, /* m factor */ 24, 2, /* mux */ 31, /* gate */ AW_CLK_HAS_GATE | AW_CLK_HAS_MUX | AW_CLK_REPARENT); NM_CLK(mmc2_clk, CLK_MMC2, /* id */ "mmc2", mod_parents, /* name, parents */ 0x90, /* offset */ 16, 2, 0, AW_CLK_FACTOR_POWER_OF_TWO, /* n factor */ 0, 4, 0, 0, /* m factor */ 24, 2, /* mux */ 31, /* gate */ AW_CLK_HAS_GATE | AW_CLK_HAS_MUX | AW_CLK_REPARENT); NM_CLK(ss_clk, CLK_SS, /* id */ "ss", mod_parents, /* name, parents */ 0x9c, /* offset */ 16, 2, 0, AW_CLK_FACTOR_POWER_OF_TWO, /* n factor */ 0, 4, 0, 0, /* m factor */ 24, 2, /* mux */ 31, /* gate */ AW_CLK_HAS_GATE | AW_CLK_HAS_MUX); NM_CLK(spi0_clk, CLK_SPI0, /* id */ "spi0", mod_parents, /* name, parents */ 0xa0, /* offset */ 16, 2, 0, AW_CLK_FACTOR_POWER_OF_TWO, /* n factor */ 0, 4, 0, 0, /* m factor */ 24, 2, /* mux */ 31, /* gate */ AW_CLK_HAS_GATE | AW_CLK_HAS_MUX); NM_CLK(spi1_clk, CLK_SPI1, /* id */ "spi1", mod_parents, /* name, parents */ 0xa4, /* offset */ 16, 2, 0, AW_CLK_FACTOR_POWER_OF_TWO, /* n factor */ 0, 4, 0, 0, /* m factor */ 24, 2, /* mux */ 31, /* gate */ AW_CLK_HAS_GATE | AW_CLK_HAS_MUX); static const char *daudio_parents[] = {"pll_audio"}; NM_CLK(i2s0_clk, CLK_I2S0, /* id */ "i2s0", daudio_parents, /* name, parents */ 0xb0, /* offset */ 0, 0, 1, AW_CLK_FACTOR_FIXED, /* n factor (fake) */ 0, 4, 0, 0, /* m factor */ 0, 0, /* mux */ 31, /* gate */ AW_CLK_HAS_GATE); NM_CLK(i2s1_clk, CLK_I2S1, /* id */ "i2s1", daudio_parents, /* name, parents */ 0xb4, /* offset */ 0, 0, 1, AW_CLK_FACTOR_FIXED, /* n factor (fake) */ 0, 4, 0, 0, /* m factor */ 0, 0, /* mux */ 31, /* gate */ AW_CLK_HAS_GATE); NM_CLK(i2s2_clk, CLK_I2S2, /* id */ "i2s2", daudio_parents, /* name, parents */ 0xb8, /* offset */ 0, 0, 1, AW_CLK_FACTOR_FIXED, /* n factor (fake) */ 0, 4, 0, 0, /* m factor */ 0, 0, /* mux */ 31, /* gate */ AW_CLK_HAS_GATE); static const char *tdm_parents[] = {"pll_audio"}; NM_CLK(tdm_clk, CLK_TDM, /* id */ "tdm", tdm_parents, /* name, parents */ 0xbc, /* offset */ 0, 0, 1, AW_CLK_FACTOR_FIXED, /* n factor (fake) */ 0, 4, 0, 0, /* m factor */ 0, 0, /* mux */ 31, /* gate */ AW_CLK_HAS_GATE); static const char *spdif_parents[] = {"pll_audio"}; NM_CLK(spdif_clk, CLK_SPDIF, /* id */ "spdif", spdif_parents, /* name, parents */ 0xc0, /* offset */ 0, 0, 1, AW_CLK_FACTOR_FIXED, /* n factor (fake) */ 0, 4, 0, 0, /* m factor */ 0, 0, /* mux */ 31, /* gate */ AW_CLK_HAS_GATE); static const char *dram_parents[] = {"pll_ddr"}; NM_CLK(dram_clk, CLK_DRAM, /* id */ "dram", dram_parents, /* name, parents */ 0xf4, /* offset */ 0, 0, 1, AW_CLK_FACTOR_FIXED, /* n factor (fake) */ 0, 4, 0, 0, /* m factor */ 0, 0, /* mux */ 0, /* gate */ 0); static const char *tcon0_parents[] = {"pll_video0"}; MUX_CLK(tcon0_clk, CLK_TCON0, /* id */ "tcon0", tcon0_parents, /* name, parents */ 0x118, 24, 2); /* offset, shift, width */ static const char *tcon1_parents[] = {"pll_video1"}; NM_CLK(tcon1_clk, CLK_TCON1, /* id */ "tcon1", tcon1_parents, /* name, parents */ 0x11c, /* offset */ 0, 0, 1, AW_CLK_FACTOR_FIXED, /* n factor (fake) */ 0, 4, 0, 0, /* m factor */ 0, 0, /* mux */ 31, /* gate */ AW_CLK_HAS_GATE); static const char *csi_mclk_parents[] = {"pll_de", "osc24M"}; NM_CLK(csi_mclk_clk, CLK_CSI_MCLK, /* id */ "csi-mclk", csi_mclk_parents, /* name, parents */ 0x134, /* offset */ 0, 0, 1, AW_CLK_FACTOR_FIXED, /* n factor (fake) */ 0, 4, 0, 0, /* m factor */ 8, 3, /* mux */ 15, /* gate */ AW_CLK_HAS_MUX | AW_CLK_HAS_GATE); static const char *csi_sclk_parents[] = {"pll_periph", "pll_ve"}; NM_CLK(csi_sclk_clk, CLK_CSI_SCLK, /* id */ "csi-sclk", csi_sclk_parents, /* name, parents */ 0x134, /* offset */ 0, 0, 1, AW_CLK_FACTOR_FIXED, /* n factor (fake) */ 16, 4, 0, 0, /* m factor */ 24, 3, /* mux */ 31, /* gate */ AW_CLK_HAS_MUX | AW_CLK_HAS_GATE); static const char *ve_parents[] = {"pll_ve"}; NM_CLK(ve_clk, CLK_VE, /* id */ "ve", ve_parents, /* name, parents */ 0x13c, /* offset */ 0, 0, 1, AW_CLK_FACTOR_FIXED, /* n factor (fake) */ 16, 3, 0, 0, /* m factor */ 0, 0, /* mux */ 31, /* gate */ AW_CLK_HAS_GATE); static const char *hdmi_parents[] = {"pll_video1"}; NM_CLK(hdmi_clk, CLK_HDMI, /* id */ "hdmi", hdmi_parents, /* name, parents */ 0x150, /* offset */ 0, 0, 1, AW_CLK_FACTOR_FIXED, /* n factor (fake) */ 0, 4, 0, 0, /* m factor */ 24, 2, /* mux */ 31, /* gate */ AW_CLK_HAS_MUX | AW_CLK_HAS_GATE); static const char *mbus_parents[] = {"osc24M", "pll_periph", "pll_ddr"}; NM_CLK(mbus_clk, CLK_MBUS, /* id */ "mbus", mbus_parents, /* name, parents */ 0x15c, /* offset */ 0, 0, 1, AW_CLK_FACTOR_FIXED, /* n factor (fake) */ 0, 3, 0, 0, /* m factor */ 24, 2, /* mux */ 31, /* gate */ AW_CLK_HAS_MUX | AW_CLK_HAS_GATE); static const char *mipi_dsi0_parents[] = {"pll_video0"}; NM_CLK(mipi_dsi0_clk, CLK_MIPI_DSI0, /* id */ "mipi-dsi0", mipi_dsi0_parents, /* name, parents */ 0x168, /* offset */ 0, 0, 1, AW_CLK_FACTOR_FIXED, /* n factor (fake) */ 0, 4, 0, 0, /* m factor */ 24, 4, /* mux */ 31, /* gate */ AW_CLK_HAS_MUX | AW_CLK_HAS_GATE); static const char *mipi_dsi1_parents[] = {"osc24M", "pll_video0"}; NM_CLK(mipi_dsi1_clk, CLK_MIPI_DSI1, /* id */ "mipi-dsi1", mipi_dsi1_parents, /* name, parents */ 0x16c, /* offset */ 0, 0, 1, AW_CLK_FACTOR_FIXED, /* n factor (fake) */ 0, 4, 0, 0, /* m factor */ 24, 4, /* mux */ 31, /* gate */ AW_CLK_HAS_MUX | AW_CLK_HAS_GATE); static const char *gpu_core_parents[] = {"pll_gpu"}; NM_CLK(gpu_core_clk, CLK_GPU_CORE, /* id */ "gpu-core", gpu_core_parents, /* name, parents */ 0x1a0, /* offset */ 0, 0, 1, AW_CLK_FACTOR_FIXED, /* n factor (fake) */ 0, 3, 0, 0, /* m factor */ 0, 0, /* mux */ 31, /* gate */ AW_CLK_HAS_GATE); static const char *gpu_memory_parents[] = {"pll_gpu", "pll_periph"}; NM_CLK(gpu_memory_clk, CLK_GPU_MEMORY, /* id */ "gpu-memory", gpu_memory_parents, /* name, parents */ 0x1a4, /* offset */ 0, 0, 1, AW_CLK_FACTOR_FIXED, /* n factor (fake) */ 0, 3, 0, 0, /* m factor */ 24, 1, /* mux */ 31, /* gate */ AW_CLK_HAS_MUX | AW_CLK_HAS_GATE); static const char *gpu_hyd_parents[] = {"pll_gpu"}; NM_CLK(gpu_hyd_clk, CLK_GPU_HYD, /* id */ "gpu-hyd", gpu_hyd_parents, /* name, parents */ 0x1a0, /* offset */ 0, 0, 1, AW_CLK_FACTOR_FIXED, /* n factor (fake) */ 0, 3, 0, 0, /* m factor */ 0, 0, /* mux */ 31, /* gate */ AW_CLK_HAS_GATE); static struct aw_ccung_clk a83t_clks[] = { { .type = AW_CLK_NKMP, .clk.nkmp = &pll_audio_clk}, { .type = AW_CLK_NKMP, .clk.nkmp = &pll_video0_clk}, { .type = AW_CLK_NKMP, .clk.nkmp = &pll_ve_clk}, { .type = AW_CLK_NKMP, .clk.nkmp = &pll_ddr_clk}, { .type = AW_CLK_NKMP, .clk.nkmp = &pll_periph_clk}, { .type = AW_CLK_NKMP, .clk.nkmp = &pll_gpu_clk}, { .type = AW_CLK_NKMP, .clk.nkmp = &pll_hsic_clk}, { .type = AW_CLK_NKMP, .clk.nkmp = &pll_de_clk}, { .type = AW_CLK_NKMP, .clk.nkmp = &pll_video1_clk}, { .type = AW_CLK_NKMP, .clk.nkmp = &pll_c0cpux_clk}, { .type = AW_CLK_NKMP, .clk.nkmp = &pll_c1cpux_clk}, { .type = AW_CLK_NM, .clk.nm = &apb2_clk}, { .type = AW_CLK_NM, .clk.nm = &nand_clk}, { .type = AW_CLK_NM, .clk.nm = &mmc0_clk}, { .type = AW_CLK_NM, .clk.nm = &mmc1_clk}, { .type = AW_CLK_NM, .clk.nm = &mmc2_clk}, { .type = AW_CLK_NM, .clk.nm = &ss_clk}, { .type = AW_CLK_NM, .clk.nm = &spi0_clk}, { .type = AW_CLK_NM, .clk.nm = &spi1_clk}, { .type = AW_CLK_NM, .clk.nm = &i2s0_clk}, { .type = AW_CLK_NM, .clk.nm = &i2s1_clk}, { .type = AW_CLK_NM, .clk.nm = &i2s2_clk}, { .type = AW_CLK_NM, .clk.nm = &tdm_clk}, { .type = AW_CLK_NM, .clk.nm = &spdif_clk}, { .type = AW_CLK_NM, .clk.nm = &dram_clk}, { .type = AW_CLK_NM, .clk.nm = &tcon1_clk}, { .type = AW_CLK_NM, .clk.nm = &csi_mclk_clk}, { .type = AW_CLK_NM, .clk.nm = &csi_sclk_clk}, { .type = AW_CLK_NM, .clk.nm = &ve_clk}, { .type = AW_CLK_NM, .clk.nm = &hdmi_clk}, { .type = AW_CLK_NM, .clk.nm = &mbus_clk}, { .type = AW_CLK_NM, .clk.nm = &mipi_dsi0_clk}, { .type = AW_CLK_NM, .clk.nm = &mipi_dsi1_clk}, { .type = AW_CLK_NM, .clk.nm = &gpu_core_clk}, { .type = AW_CLK_NM, .clk.nm = &gpu_memory_clk}, { .type = AW_CLK_NM, .clk.nm = &gpu_hyd_clk}, { .type = AW_CLK_PREDIV_MUX, .clk.prediv_mux = &ahb1_clk}, { .type = AW_CLK_PREDIV_MUX, .clk.prediv_mux = &ahb2_clk}, { .type = AW_CLK_MUX, .clk.mux = &c0cpux_clk}, { .type = AW_CLK_MUX, .clk.mux = &c1cpux_clk}, { .type = AW_CLK_MUX, .clk.mux = &cci400_clk}, { .type = AW_CLK_MUX, .clk.mux = &tcon0_clk}, { .type = AW_CLK_DIV, .clk.div = &axi0_clk}, { .type = AW_CLK_DIV, .clk.div = &axi1_clk}, { .type = AW_CLK_DIV, .clk.div = &apb1_clk}, { .type = AW_CLK_FIXED, .clk.fixed = &osc12m_clk}, }; static struct aw_clk_init a83t_init_clks[] = { {"ahb1", "pll_periph", 0, false}, {"ahb2", "ahb1", 0, false}, {"dram", "pll_ddr", 0, false}, }; static int ccu_a83t_probe(device_t dev) { if (!ofw_bus_status_okay(dev)) return (ENXIO); if (!ofw_bus_is_compatible(dev, "allwinner,sun8i-a83t-ccu")) return (ENXIO); device_set_desc(dev, "Allwinner A83T Clock Control Unit NG"); return (BUS_PROBE_DEFAULT); } static int ccu_a83t_attach(device_t dev) { struct aw_ccung_softc *sc; sc = device_get_softc(dev); sc->resets = a83t_ccu_resets; sc->nresets = nitems(a83t_ccu_resets); sc->gates = a83t_ccu_gates; sc->ngates = nitems(a83t_ccu_gates); sc->clks = a83t_clks; sc->nclks = nitems(a83t_clks); sc->clk_init = a83t_init_clks; sc->n_clk_init = nitems(a83t_init_clks); return (aw_ccung_attach(dev)); } static device_method_t ccu_a83tng_methods[] = { /* Device interface */ DEVMETHOD(device_probe, ccu_a83t_probe), DEVMETHOD(device_attach, ccu_a83t_attach), DEVMETHOD_END }; static devclass_t ccu_a83tng_devclass; DEFINE_CLASS_1(ccu_a83tng, ccu_a83tng_driver, ccu_a83tng_methods, sizeof(struct aw_ccung_softc), aw_ccung_driver); EARLY_DRIVER_MODULE(ccu_a83tng, simplebus, ccu_a83tng_driver, - ccu_a83tng_devclass, 0, 0, BUS_PASS_BUS + BUS_PASS_ORDER_LAST); + ccu_a83tng_devclass, 0, 0, BUS_PASS_RESOURCE + BUS_PASS_ORDER_MIDDLE); Index: head/sys/arm/allwinner/clkng/ccu_de2.c =================================================================== --- head/sys/arm/allwinner/clkng/ccu_de2.c (revision 350841) +++ head/sys/arm/allwinner/clkng/ccu_de2.c (revision 350842) @@ -1,166 +1,166 @@ /*- * SPDX-License-Identifier: BSD-2-Clause-FreeBSD * * Copyright (c) 2018 Emmanuel Vadot * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. * * $FreeBSD$ */ #include __FBSDID("$FreeBSD$"); #include #include #include #include #include #include #include #include #include #include #include "opt_soc.h" #include #include #include #include #include #include /* Non exported clocks */ #define CLK_MIXER0_DIV 3 #define CLK_MIXER1_DIV 4 #define CLK_WB_DIV 5 static struct aw_ccung_reset de2_ccu_resets[] = { CCU_RESET(RST_MIXER0, 0x08, 0) CCU_RESET(RST_MIXER1, 0x08, 1) CCU_RESET(RST_WB, 0x08, 2) }; static struct aw_ccung_gate de2_ccu_gates[] = { CCU_GATE(CLK_BUS_MIXER0, "mixer0", "mixer0-div", 0x00, 0) CCU_GATE(CLK_BUS_MIXER1, "mixer1", "mixer1-div", 0x00, 1) CCU_GATE(CLK_BUS_WB, "wb", "wb-div", 0x00, 2) CCU_GATE(CLK_MIXER0, "bus-mixer0", "bus-de", 0x04, 0) CCU_GATE(CLK_MIXER1, "bus-mixer1", "bus-de", 0x04, 1) CCU_GATE(CLK_WB, "bus-wb", "bus-de", 0x04, 2) }; static const char *div_parents[] = {"de"}; NM_CLK(mixer0_div_clk, CLK_MIXER0_DIV, /* id */ "mixer0-div", div_parents, /* names, parents */ 0x0C, /* offset */ 0, 0, 1, AW_CLK_FACTOR_FIXED, /* N factor (fake)*/ 0, 4, 0, 0, /* M flags */ 0, 0, /* mux */ 0, /* gate */ AW_CLK_SCALE_CHANGE); /* flags */ NM_CLK(mixer1_div_clk, CLK_MIXER1_DIV, /* id */ "mixer1-div", div_parents, /* names, parents */ 0x0C, /* offset */ 0, 0, 1, AW_CLK_FACTOR_FIXED, /* N factor (fake)*/ 4, 4, 0, 0, /* M flags */ 0, 0, /* mux */ 0, /* gate */ AW_CLK_SCALE_CHANGE); /* flags */ NM_CLK(wb_div_clk, CLK_WB_DIV, /* id */ "wb-div", div_parents, /* names, parents */ 0x0C, /* offset */ 0, 0, 1, AW_CLK_FACTOR_FIXED, /* N factor (fake)*/ 8, 4, 0, 0, /* M flags */ 0, 0, /* mux */ 0, /* gate */ AW_CLK_SCALE_CHANGE); /* flags */ static struct aw_ccung_clk de2_ccu_clks[] = { { .type = AW_CLK_NM, .clk.nm = &mixer0_div_clk}, { .type = AW_CLK_NM, .clk.nm = &mixer1_div_clk}, { .type = AW_CLK_NM, .clk.nm = &wb_div_clk}, }; static struct ofw_compat_data compat_data[] = { {"allwinner,sun50i-a64-de2-clk", 1}, {NULL, 0} }; static int ccu_de2_probe(device_t dev) { if (!ofw_bus_status_okay(dev)) return (ENXIO); if (ofw_bus_search_compatible(dev, compat_data)->ocd_data == 0) return (ENXIO); device_set_desc(dev, "Allwinner DE2 Clock Control Unit"); return (BUS_PROBE_DEFAULT); } static int ccu_de2_attach(device_t dev) { struct aw_ccung_softc *sc; sc = device_get_softc(dev); sc->resets = de2_ccu_resets; sc->nresets = nitems(de2_ccu_resets); sc->gates = de2_ccu_gates; sc->ngates = nitems(de2_ccu_gates); sc->clks = de2_ccu_clks; sc->nclks = nitems(de2_ccu_clks); return (aw_ccung_attach(dev)); } static device_method_t ccu_de2_methods[] = { /* Device interface */ DEVMETHOD(device_probe, ccu_de2_probe), DEVMETHOD(device_attach, ccu_de2_attach), DEVMETHOD_END }; static devclass_t ccu_de2ng_devclass; DEFINE_CLASS_1(ccu_de2, ccu_de2_driver, ccu_de2_methods, sizeof(struct aw_ccung_softc), aw_ccung_driver); EARLY_DRIVER_MODULE(ccu_de2, simplebus, ccu_de2_driver, - ccu_de2ng_devclass, 0, 0, BUS_PASS_BUS + BUS_PASS_ORDER_LAST); + ccu_de2ng_devclass, 0, 0, BUS_PASS_RESOURCE + BUS_PASS_ORDER_LAST); Index: head/sys/arm/allwinner/clkng/ccu_h3.c =================================================================== --- head/sys/arm/allwinner/clkng/ccu_h3.c (revision 350841) +++ head/sys/arm/allwinner/clkng/ccu_h3.c (revision 350842) @@ -1,790 +1,790 @@ /*- * SPDX-License-Identifier: BSD-2-Clause-FreeBSD * * Copyright (c) 2017,2018 Emmanuel Vadot * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. * * $FreeBSD$ */ #include __FBSDID("$FreeBSD$"); #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #if defined(__aarch64__) #include "opt_soc.h" #endif #include #include #include /* Non-exported resets */ #define RST_BUS_SCR 53 /* Non-exported clocks */ #define CLK_PLL_CPUX 0 #define CLK_PLL_AUDIO_BASE 1 #define CLK_PLL_AUDIO 2 #define CLK_PLL_AUDIO_2X 3 #define CLK_PLL_AUDIO_4X 4 #define CLK_PLL_AUDIO_8X 5 #define CLK_PLL_VIDEO 6 #define CLK_PLL_VE 7 #define CLK_PLL_DDR 8 #define CLK_PLL_PERIPH0_2X 10 #define CLK_PLL_GPU 11 #define CLK_PLL_PERIPH1 12 #define CLK_PLL_DE 13 #define CLK_AXI 15 #define CLK_AHB1 16 #define CLK_APB1 17 #define CLK_APB2 18 #define CLK_AHB2 19 #define CLK_BUS_SCR 66 #define CLK_USBPHY0 88 #define CLK_USBPHY1 89 #define CLK_USBPHY2 90 #define CLK_USBPHY3 91 #define CLK_USBOHCI0 92 #define CLK_USBOHCI1 93 #define CLK_USBOHCI2 94 #define CLK_USBOHCI3 95 #define CLK_DRAM 96 #define CLK_MBUS 113 static struct aw_ccung_reset h3_ccu_resets[] = { CCU_RESET(RST_USB_PHY0, 0xcc, 0) CCU_RESET(RST_USB_PHY1, 0xcc, 1) CCU_RESET(RST_USB_PHY2, 0xcc, 2) CCU_RESET(RST_USB_PHY3, 0xcc, 3) CCU_RESET(RST_MBUS, 0xfc, 31) CCU_RESET(RST_BUS_CE, 0x2c0, 5) CCU_RESET(RST_BUS_DMA, 0x2c0, 6) CCU_RESET(RST_BUS_MMC0, 0x2c0, 8) CCU_RESET(RST_BUS_MMC1, 0x2c0, 9) CCU_RESET(RST_BUS_MMC2, 0x2c0, 10) CCU_RESET(RST_BUS_NAND, 0x2c0, 13) CCU_RESET(RST_BUS_DRAM, 0x2c0, 14) CCU_RESET(RST_BUS_EMAC, 0x2c0, 17) CCU_RESET(RST_BUS_TS, 0x2c0, 18) CCU_RESET(RST_BUS_HSTIMER, 0x2c0, 19) CCU_RESET(RST_BUS_SPI0, 0x2c0, 20) CCU_RESET(RST_BUS_SPI1, 0x2c0, 21) CCU_RESET(RST_BUS_OTG, 0x2c0, 23) CCU_RESET(RST_BUS_EHCI0, 0x2c0, 24) CCU_RESET(RST_BUS_EHCI1, 0x2c0, 25) CCU_RESET(RST_BUS_EHCI2, 0x2c0, 26) CCU_RESET(RST_BUS_EHCI3, 0x2c0, 27) CCU_RESET(RST_BUS_OHCI0, 0x2c0, 28) CCU_RESET(RST_BUS_OHCI1, 0x2c0, 29) CCU_RESET(RST_BUS_OHCI2, 0x2c0, 30) CCU_RESET(RST_BUS_OHCI3, 0x2c0, 31) CCU_RESET(RST_BUS_VE, 0x2c4, 0) CCU_RESET(RST_BUS_TCON0, 0x2c4, 3) CCU_RESET(RST_BUS_TCON1, 0x2c4, 4) CCU_RESET(RST_BUS_DEINTERLACE, 0x2c4, 5) CCU_RESET(RST_BUS_CSI, 0x2c4, 8) CCU_RESET(RST_BUS_TVE, 0x2c4, 9) CCU_RESET(RST_BUS_HDMI0, 0x2c4, 10) CCU_RESET(RST_BUS_HDMI1, 0x2c4, 11) CCU_RESET(RST_BUS_DE, 0x2c4, 12) CCU_RESET(RST_BUS_GPU, 0x2c4, 20) CCU_RESET(RST_BUS_MSGBOX, 0x2c4, 21) CCU_RESET(RST_BUS_SPINLOCK, 0x2c4, 22) CCU_RESET(RST_BUS_DBG, 0x2c4, 31) CCU_RESET(RST_BUS_EPHY, 0x2c8, 2) CCU_RESET(RST_BUS_CODEC, 0x2d0, 0) CCU_RESET(RST_BUS_SPDIF, 0x2d0, 1) CCU_RESET(RST_BUS_THS, 0x2d0, 8) CCU_RESET(RST_BUS_I2S0, 0x2d0, 12) CCU_RESET(RST_BUS_I2S1, 0x2d0, 13) CCU_RESET(RST_BUS_I2S2, 0x2d0, 14) CCU_RESET(RST_BUS_I2C0, 0x2d8, 0) CCU_RESET(RST_BUS_I2C1, 0x2d8, 1) CCU_RESET(RST_BUS_I2C2, 0x2d8, 2) CCU_RESET(RST_BUS_UART0, 0x2d8, 16) CCU_RESET(RST_BUS_UART1, 0x2d8, 17) CCU_RESET(RST_BUS_UART2, 0x2d8, 18) CCU_RESET(RST_BUS_UART3, 0x2d8, 19) CCU_RESET(RST_BUS_SCR, 0x2d8, 20) }; static struct aw_ccung_gate h3_ccu_gates[] = { CCU_GATE(CLK_BUS_CE, "bus-ce", "ahb1", 0x60, 5) CCU_GATE(CLK_BUS_DMA, "bus-dma", "ahb1", 0x60, 6) CCU_GATE(CLK_BUS_MMC0, "bus-mmc0", "ahb1", 0x60, 8) CCU_GATE(CLK_BUS_MMC1, "bus-mmc1", "ahb1", 0x60, 9) CCU_GATE(CLK_BUS_MMC2, "bus-mmc2", "ahb1", 0x60, 10) CCU_GATE(CLK_BUS_NAND, "bus-nand", "ahb1", 0x60, 13) CCU_GATE(CLK_BUS_DRAM, "bus-dram", "ahb1", 0x60, 14) CCU_GATE(CLK_BUS_EMAC, "bus-emac", "ahb2", 0x60, 17) CCU_GATE(CLK_BUS_TS, "bus-ts", "ahb1", 0x60, 18) CCU_GATE(CLK_BUS_HSTIMER, "bus-hstimer", "ahb1", 0x60, 19) CCU_GATE(CLK_BUS_SPI0, "bus-spi0", "ahb1", 0x60, 20) CCU_GATE(CLK_BUS_SPI1, "bus-spi1", "ahb1", 0x60, 21) CCU_GATE(CLK_BUS_OTG, "bus-otg", "ahb1", 0x60, 23) CCU_GATE(CLK_BUS_EHCI0, "bus-ehci0", "ahb1", 0x60, 24) CCU_GATE(CLK_BUS_EHCI1, "bus-ehci1", "ahb2", 0x60, 25) CCU_GATE(CLK_BUS_EHCI2, "bus-ehci2", "ahb2", 0x60, 26) CCU_GATE(CLK_BUS_EHCI3, "bus-ehci3", "ahb2", 0x60, 27) CCU_GATE(CLK_BUS_OHCI0, "bus-ohci0", "ahb1", 0x60, 28) CCU_GATE(CLK_BUS_OHCI1, "bus-ohci1", "ahb2", 0x60, 29) CCU_GATE(CLK_BUS_OHCI2, "bus-ohci2", "ahb2", 0x60, 30) CCU_GATE(CLK_BUS_OHCI3, "bus-ohci3", "ahb2", 0x60, 31) CCU_GATE(CLK_BUS_VE, "bus-ve", "ahb1", 0x64, 0) CCU_GATE(CLK_BUS_TCON0, "bus-tcon0", "ahb1", 0x64, 3) CCU_GATE(CLK_BUS_TCON1, "bus-tcon1", "ahb1", 0x64, 4) CCU_GATE(CLK_BUS_DEINTERLACE, "bus-deinterlace", "ahb1", 0x64, 5) CCU_GATE(CLK_BUS_CSI, "bus-csi", "ahb1", 0x64, 8) CCU_GATE(CLK_BUS_TVE, "bus-tve", "ahb1", 0x64, 9) CCU_GATE(CLK_BUS_HDMI, "bus-hdmi", "ahb1", 0x64, 11) CCU_GATE(CLK_BUS_DE, "bus-de", "ahb1", 0x64, 12) CCU_GATE(CLK_BUS_GPU, "bus-gpu", "ahb1", 0x64, 20) CCU_GATE(CLK_BUS_MSGBOX, "bus-msgbox", "ahb1", 0x64, 21) CCU_GATE(CLK_BUS_SPINLOCK, "bus-spinlock", "ahb1", 0x64, 22) CCU_GATE(CLK_BUS_CODEC, "bus-codec", "apb1", 0x68, 0) CCU_GATE(CLK_BUS_SPDIF, "bus-spdif", "apb1", 0x68, 1) CCU_GATE(CLK_BUS_PIO, "bus-pio", "apb1", 0x68, 5) CCU_GATE(CLK_BUS_THS, "bus-ths", "apb1", 0x68, 8) CCU_GATE(CLK_BUS_I2S0, "bus-i2s0", "apb1", 0x68, 12) CCU_GATE(CLK_BUS_I2S1, "bus-i2s1", "apb1", 0x68, 13) CCU_GATE(CLK_BUS_I2S2, "bus-i2s2", "apb1", 0x68, 14) CCU_GATE(CLK_BUS_I2C0, "bus-i2c0", "apb2", 0x6c, 0) CCU_GATE(CLK_BUS_I2C1, "bus-i2c1", "apb2", 0x6c, 1) CCU_GATE(CLK_BUS_I2C2, "bus-i2c2", "apb2", 0x6c, 2) CCU_GATE(CLK_BUS_UART0, "bus-uart0", "apb2", 0x6c, 16) CCU_GATE(CLK_BUS_UART1, "bus-uart1", "apb2", 0x6c, 17) CCU_GATE(CLK_BUS_UART2, "bus-uart2", "apb2", 0x6c, 18) CCU_GATE(CLK_BUS_UART3, "bus-uart3", "apb2", 0x6c, 19) CCU_GATE(CLK_BUS_SCR, "bus-scr", "apb2", 0x6c, 20) CCU_GATE(CLK_BUS_EPHY, "bus-ephy", "ahb1", 0x70, 0) CCU_GATE(CLK_BUS_DBG, "bus-dbg", "ahb1", 0x70, 7) CCU_GATE(CLK_USBPHY0, "usb-phy0", "osc24M", 0xcc, 8) CCU_GATE(CLK_USBPHY1, "usb-phy1", "osc24M", 0xcc, 9) CCU_GATE(CLK_USBPHY2, "usb-phy2", "osc24M", 0xcc, 10) CCU_GATE(CLK_USBPHY3, "usb-phy3", "osc24M", 0xcc, 11) CCU_GATE(CLK_USBOHCI0, "usb-ohci0", "osc24M", 0xcc, 16) CCU_GATE(CLK_USBOHCI1, "usb-ohci1", "osc24M", 0xcc, 17) CCU_GATE(CLK_USBOHCI2, "usb-ohci2", "osc24M", 0xcc, 18) CCU_GATE(CLK_USBOHCI3, "usb-ohci3", "osc24M", 0xcc, 19) CCU_GATE(CLK_THS, "ths", "thsdiv", 0x74, 31) CCU_GATE(CLK_I2S0, "i2s0", "i2s0mux", 0xB0, 31) CCU_GATE(CLK_I2S1, "i2s1", "i2s1mux", 0xB4, 31) CCU_GATE(CLK_I2S2, "i2s2", "i2s2mux", 0xB8, 31) CCU_GATE(CLK_DRAM_VE, "dram-ve", "dram", 0x100, 0) CCU_GATE(CLK_DRAM_CSI, "dram-csi", "dram", 0x100, 1) CCU_GATE(CLK_DRAM_DEINTERLACE, "dram-deinterlace", "dram", 0x100, 2) CCU_GATE(CLK_DRAM_TS, "dram-ts", "dram", 0x100, 3) CCU_GATE(CLK_AC_DIG, "ac-dig", "pll_audio", 0x140, 31) CCU_GATE(CLK_AVS, "avs", "osc24M", 0x144, 31) CCU_GATE(CLK_CSI_MISC, "csi-misc", "osc24M", 0x130, 31) CCU_GATE(CLK_HDMI_DDC, "hdmi-ddc", "osc24M", 0x154, 31) }; static const char *pll_cpux_parents[] = {"osc24M"}; NKMP_CLK(pll_cpux_clk, CLK_PLL_CPUX, /* id */ "pll_cpux", pll_cpux_parents, /* name, parents */ 0x00, /* offset */ 8, 5, 0, 0, /* n factor */ 4, 2, 0, 0, /* k factor */ 0, 2, 0, 0, /* m factor */ 16, 2, 0, AW_CLK_FACTOR_POWER_OF_TWO, /* p factor */ 31, /* gate */ 28, 1000, /* lock */ AW_CLK_HAS_GATE | AW_CLK_HAS_LOCK | AW_CLK_SCALE_CHANGE); /* flags */ static const char *pll_audio_parents[] = {"osc24M"}; NKMP_CLK(pll_audio_clk, CLK_PLL_AUDIO, /* id */ "pll_audio", pll_audio_parents, /* name, parents */ 0x08, /* offset */ 8, 7, 0, 0, /* n factor */ 0, 0, 1, AW_CLK_FACTOR_FIXED, /* k factor (fake) */ 0, 5, 0, 0, /* m factor */ 16, 4, 0, 0, /* p factor */ 31, /* gate */ 28, 1000, /* lock */ AW_CLK_HAS_GATE | AW_CLK_HAS_LOCK); /* flags */ static const char *pll_audio_mult_parents[] = {"pll_audio"}; FIXED_CLK(pll_audio_2x_clk, CLK_PLL_AUDIO_2X, /* id */ "pll_audio-2x", /* name */ pll_audio_mult_parents, /* parent */ 0, /* freq */ 2, /* mult */ 1, /* div */ 0); /* flags */ FIXED_CLK(pll_audio_4x_clk, CLK_PLL_AUDIO_4X, /* id */ "pll_audio-4x", /* name */ pll_audio_mult_parents, /* parent */ 0, /* freq */ 4, /* mult */ 1, /* div */ 0); /* flags */ FIXED_CLK(pll_audio_8x_clk, CLK_PLL_AUDIO_8X, /* id */ "pll_audio-8x", /* name */ pll_audio_mult_parents, /* parent */ 0, /* freq */ 8, /* mult */ 1, /* div */ 0); /* flags */ static const char *pll_video_parents[] = {"osc24M"}; FRAC_CLK(pll_video_clk, CLK_PLL_VIDEO, /* id */ "pll_video", pll_video_parents, /* name, parents */ 0x10, /* offset */ 8, 7, 0, 0, /* n factor */ 0, 4, 0, 0, /* m factor */ 31, 28, 1000, /* gate, lock, lock retries */ AW_CLK_HAS_LOCK, /* flags */ 270000000, 297000000, /* freq0, freq1 */ 24, 25); /* mode sel, freq sel */ static const char *pll_ve_parents[] = {"osc24M"}; FRAC_CLK(pll_ve_clk, CLK_PLL_VE, /* id */ "pll_ve", pll_ve_parents, /* name, parents */ 0x18, /* offset */ 8, 7, 0, 0, /* n factor */ 0, 4, 0, 0, /* m factor */ 31, 28, 1000, /* gate, lock, lock retries */ AW_CLK_HAS_LOCK, /* flags */ 270000000, 297000000, /* freq0, freq1 */ 24, 25); /* mode sel, freq sel */ static const char *pll_ddr_parents[] = {"osc24M"}; NKMP_CLK_WITH_UPDATE(pll_ddr_clk, CLK_PLL_DDR, /* id */ "pll_ddr", pll_ddr_parents, /* name, parents */ 0x20, /* offset */ 8, 5, 0, 0, /* n factor */ 4, 2, 0, 0, /* k factor */ 0, 2, 0, 0, /* m factor */ 0, 0, 1, AW_CLK_FACTOR_FIXED, /* p factor (fake) */ 31, /* gate */ 28, 1000, /* lock */ 20, /* update */ AW_CLK_HAS_GATE | AW_CLK_HAS_LOCK); /* flags */ static const char *pll_periph0_parents[] = {"osc24M"}; static const char *pll_periph0_2x_parents[] = {"pll_periph0"}; NKMP_CLK(pll_periph0_clk, CLK_PLL_PERIPH0, /* id */ "pll_periph0", pll_periph0_parents, /* name, parents */ 0x28, /* offset */ 8, 5, 0, 0, /* n factor */ 4, 2, 0, 0, /* k factor */ 0, 0, 2, AW_CLK_FACTOR_FIXED, /* m factor (fake) */ 0, 0, 1, AW_CLK_FACTOR_FIXED, /* p factor (fake) */ 31, /* gate */ 28, 1000, /* lock */ AW_CLK_HAS_GATE | AW_CLK_HAS_LOCK); /* flags */ FIXED_CLK(pll_periph0_2x_clk, CLK_PLL_PERIPH0_2X, /* id */ "pll_periph0-2x", /* name */ pll_periph0_2x_parents, /* parent */ 0, /* freq */ 2, /* mult */ 1, /* div */ 0); /* flags */ static const char *pll_gpu_parents[] = {"osc24M"}; FRAC_CLK(pll_gpu_clk, CLK_PLL_GPU, /* id */ "pll_gpu", pll_gpu_parents, /* name, parents */ 0x38, /* offset */ 8, 7, 0, 0, /* n factor */ 0, 4, 0, 0, /* m factor */ 31, 28, 1000, /* gate, lock, lock retries */ AW_CLK_HAS_LOCK, /* flags */ 270000000, 297000000, /* freq0, freq1 */ 24, 25); /* mode sel, freq sel */ static const char *pll_periph1_parents[] = {"osc24M"}; NKMP_CLK(pll_periph1_clk, CLK_PLL_PERIPH1, /* id */ "pll_periph1", pll_periph1_parents, /* name, parents */ 0x44, /* offset */ 8, 5, 0, 0, /* n factor */ 4, 2, 0, 0, /* k factor */ 0, 0, 2, AW_CLK_FACTOR_FIXED, /* m factor (fake) */ 0, 0, 1, AW_CLK_FACTOR_FIXED, /* p factor (fake) */ 31, /* gate */ 28, 1000, /* lock */ AW_CLK_HAS_GATE | AW_CLK_HAS_LOCK); /* flags */ static const char *pll_de_parents[] = {"osc24M"}; FRAC_CLK(pll_de_clk, CLK_PLL_DE, /* id */ "pll_de", pll_de_parents, /* name, parents */ 0x48, /* offset */ 8, 7, 0, 0, /* n factor */ 0, 4, 0, 0, /* m factor */ 31, 28, 1000, /* gate, lock, lock retries */ AW_CLK_HAS_LOCK, /* flags */ 270000000, 297000000, /* freq0, freq1 */ 24, 25); /* mode sel, freq sel */ static const char *cpux_parents[] = {"osc32k", "osc24M", "pll_cpux", "pll_cpux"}; MUX_CLK(cpux_clk, CLK_CPUX, /* id */ "cpux", cpux_parents, /* name, parents */ 0x50, 16, 2); /* offset, shift, width */ static const char *axi_parents[] = {"cpux"}; DIV_CLK(axi_clk, CLK_AXI, /* id */ "axi", axi_parents, /* name, parents */ 0x50, /* offset */ 0, 2, /* shift, width */ 0, NULL); /* flags, div table */ static const char *ahb1_parents[] = {"osc32k", "osc24M", "axi", "pll_periph0"}; PREDIV_CLK(ahb1_clk, CLK_AHB1, /* id */ "ahb1", ahb1_parents, /* name, parents */ 0x54, /* offset */ 12, 2, /* mux */ 4, 2, 0, AW_CLK_FACTOR_POWER_OF_TWO, /* div */ 6, 2, 0, AW_CLK_FACTOR_HAS_COND, /* prediv */ 12, 2, 3); /* prediv condition */ static const char *apb1_parents[] = {"ahb1"}; static struct clk_div_table apb1_div_table[] = { { .value = 0, .divider = 2, }, { .value = 1, .divider = 2, }, { .value = 2, .divider = 4, }, { .value = 3, .divider = 8, }, { }, }; DIV_CLK(apb1_clk, CLK_APB1, /* id */ "apb1", apb1_parents, /* name, parents */ 0x54, /* offset */ 8, 2, /* shift, width */ CLK_DIV_WITH_TABLE, /* flags */ apb1_div_table); /* div table */ static const char *apb2_parents[] = {"osc32k", "osc24M", "pll_periph0", "pll_periph0"}; NM_CLK(apb2_clk, CLK_APB2, /* id */ "apb2", apb2_parents, /* name, parents */ 0x58, /* offset */ 16, 2, 0, AW_CLK_FACTOR_POWER_OF_TWO, /* n factor */ 0, 5, 0, 0, /* m factor */ 24, 2, /* mux */ 0, /* gate */ AW_CLK_HAS_MUX); static const char *ahb2_parents[] = {"ahb1", "pll_periph0"}; PREDIV_CLK(ahb2_clk, CLK_AHB2, /* id */ "ahb2", ahb2_parents, /* name, parents */ 0x5c, /* offset */ 0, 2, /* mux */ 0, 0, 1, AW_CLK_FACTOR_FIXED, /* div */ 0, 0, 2, AW_CLK_FACTOR_HAS_COND | AW_CLK_FACTOR_FIXED, /* prediv */ 0, 2, 1); /* prediv condition */ static const char *ths_parents[] = {"osc24M"}; static struct clk_div_table ths_div_table[] = { { .value = 0, .divider = 1, }, { .value = 1, .divider = 2, }, { .value = 2, .divider = 4, }, { .value = 3, .divider = 6, }, { }, }; DIV_CLK(thsdiv_clk, 0, /* id */ "thsdiv", ths_parents, /* name, parents */ 0x74, /* offset */ 0, 2, /* shift, width */ CLK_DIV_WITH_TABLE, /* flags */ ths_div_table); /* div table */ static const char *mod_parents[] = {"osc24M", "pll_periph0", "pll_periph1"}; NM_CLK(nand_clk, CLK_NAND, "nand", mod_parents, /* id, name, parents */ 0x80, /* offset */ 16, 2, 0, AW_CLK_FACTOR_POWER_OF_TWO, /* n factor */ 0, 4, 0, 0, /* m factor */ 24, 2, /* mux */ 31, /* gate */ AW_CLK_HAS_GATE | AW_CLK_HAS_MUX); /* flags */ NM_CLK(mmc0_clk, CLK_MMC0, "mmc0", mod_parents, /* id, name, parents */ 0x88, /* offset */ 16, 2, 0, AW_CLK_FACTOR_POWER_OF_TWO, /* n factor */ 0, 4, 0, 0, /* m factor */ 24, 2, /* mux */ 31, /* gate */ AW_CLK_HAS_GATE | AW_CLK_HAS_MUX | AW_CLK_REPARENT); /* flags */ NM_CLK(mmc1_clk, CLK_MMC1, "mmc1", mod_parents, /* id, name, parents */ 0x8c, /* offset */ 16, 2, 0, AW_CLK_FACTOR_POWER_OF_TWO, /* n factor */ 0, 4, 0, 0, /* m factor */ 24, 2, /* mux */ 31, /* gate */ AW_CLK_HAS_GATE | AW_CLK_HAS_MUX | AW_CLK_REPARENT); /* flags */ NM_CLK(mmc2_clk, CLK_MMC2, "mmc2", mod_parents, /* id, name, parents */ 0x90, /* offset */ 16, 2, 0, AW_CLK_FACTOR_POWER_OF_TWO, /* n factor */ 0, 4, 0, 0, /* m factor */ 24, 2, /* mux */ 31, /* gate */ AW_CLK_HAS_GATE | AW_CLK_HAS_MUX | AW_CLK_REPARENT); /* flags */ static const char *ts_parents[] = {"osc24M", "pll_periph0"}; NM_CLK(ts_clk, CLK_TS, "ts", ts_parents, /* id, name, parents */ 0x98, /* offset */ 16, 2, 0, AW_CLK_FACTOR_POWER_OF_TWO, /* n factor */ 0, 4, 0, 0, /* m factor */ 24, 2, /* mux */ 31, /* gate */ AW_CLK_HAS_GATE | AW_CLK_HAS_MUX); /* flags */ NM_CLK(ce_clk, CLK_CE, "ce", mod_parents, /* id, name, parents */ 0x9C, /* offset */ 16, 2, 0, AW_CLK_FACTOR_POWER_OF_TWO, /* n factor */ 0, 4, 0, 0, /* m factor */ 24, 2, /* mux */ 31, /* gate */ AW_CLK_HAS_GATE | AW_CLK_HAS_MUX); /* flags */ NM_CLK(spi0_clk, CLK_SPI0, "spi0", mod_parents, /* id, name, parents */ 0xA0, /* offset */ 16, 2, 0, AW_CLK_FACTOR_POWER_OF_TWO, /* n factor */ 0, 4, 0, 0, /* m factor */ 24, 2, /* mux */ 31, /* gate */ AW_CLK_HAS_GATE | AW_CLK_HAS_MUX | AW_CLK_REPARENT); /* flags */ NM_CLK(spi1_clk, CLK_SPI1, "spi1", mod_parents, /* id, name, parents */ 0xA4, /* offset */ 16, 2, 0, AW_CLK_FACTOR_POWER_OF_TWO, /* n factor */ 0, 4, 0, 0, /* m factor */ 24, 2, /* mux */ 31, /* gate */ AW_CLK_HAS_GATE | AW_CLK_HAS_MUX | AW_CLK_REPARENT); /* flags */ static const char *i2s_parents[] = {"pll_audio-8x", "pll_audio-4x", "pll_audio-2x", "pll_audio"}; MUX_CLK(i2s0mux_clk, 0, "i2s0mux", i2s_parents, /* id, name, parents */ 0xb0, 16, 2); /* offset, mux shift, mux width */ MUX_CLK(i2s1mux_clk, 0, "i2s1mux", i2s_parents, /* id, name, parents */ 0xb4, 16, 2); /* offset, mux shift, mux width */ MUX_CLK(i2s2mux_clk, 0, "i2s2mux", i2s_parents, /* id, name, parents */ 0xb8, 16, 2); /* offset, mux shift, mux width */ static const char *spdif_parents[] = {"pll_audio"}; NM_CLK(spdif_clk, CLK_SPDIF, "spdif", spdif_parents, /* id, name, parents */ 0xC0, /* offset */ 0, 0, 1, AW_CLK_FACTOR_FIXED, /* n factor (fake); */ 0, 4, 0, 0, /* m factor */ 0, 0, /* mux */ 31, /* gate */ AW_CLK_HAS_GATE); /* flags */ static const char *dram_parents[] = {"pll_ddr", "pll_periph0-2x"}; NM_CLK(dram_clk, CLK_DRAM, "dram", dram_parents, /* id, name, parents */ 0xF4, /* offset */ 0, 0, 1, AW_CLK_FACTOR_FIXED, /* n factor (fake) */ 0, 4, 0, 0, /* m factor */ 20, 2, /* mux */ 0, /* gate */ AW_CLK_HAS_MUX); /* flags */ static const char *de_parents[] = {"pll_periph0-2x", "pll_de"}; NM_CLK(de_clk, CLK_DE, "de", de_parents, /* id, name, parents */ 0x104, /* offset */ 0, 0, 1, AW_CLK_FACTOR_FIXED, /* n factor (fake) */ 0, 4, 0, 0, /* m factor */ 24, 2, /* mux */ 31, /* gate */ AW_CLK_HAS_MUX | AW_CLK_HAS_GATE); /* flags */ static const char *tcon0_parents[] = {"pll_video"}; NM_CLK(tcon0_clk, CLK_TCON0, "tcon0", tcon0_parents, /* id, name, parents */ 0x118, /* offset */ 0, 0, 1, AW_CLK_FACTOR_FIXED, /* n factor (fake) */ 0, 4, 0, 0, /* m factor */ 24, 2, /* mux */ 31, /* gate */ AW_CLK_HAS_MUX | AW_CLK_HAS_GATE); /* flags */ static const char *tve_parents[] = {"pll_de", "pll_periph1"}; NM_CLK(tve_clk, CLK_TVE, "tve", tve_parents, /* id, name, parents */ 0x120, /* offset */ 0, 0, 1, AW_CLK_FACTOR_FIXED, /* n factor (fake) */ 0, 4, 0, 0, /* m factor */ 24, 2, /* mux */ 31, /* gate */ AW_CLK_HAS_MUX | AW_CLK_HAS_GATE); /* flags */ static const char *deinterlace_parents[] = {"pll_periph0", "pll_periph1"}; NM_CLK(deinterlace_clk, CLK_DEINTERLACE, "deinterlace", deinterlace_parents, /* id, name, parents */ 0x124, /* offset */ 0, 0, 1, AW_CLK_FACTOR_FIXED, /* n factor (fake) */ 0, 4, 0, 0, /* m factor */ 24, 2, /* mux */ 31, /* gate */ AW_CLK_HAS_MUX | AW_CLK_HAS_GATE); /* flags */ static const char *csi_sclk_parents[] = {"pll_periph0", "pll_periph1"}; NM_CLK(csi_sclk_clk, CLK_CSI_SCLK, "csi-sclk", csi_sclk_parents, /* id, name, parents */ 0x134, /* offset */ 0, 0, 1, AW_CLK_FACTOR_FIXED, /* n factor (fake) */ 16, 4, 0, 0, /* m factor */ 24, 2, /* mux */ 31, /* gate */ AW_CLK_HAS_MUX | AW_CLK_HAS_GATE); /* flags */ static const char *csi_mclk_parents[] = {"osc24M", "pll_video", "pll_periph1"}; NM_CLK(csi_mclk_clk, CLK_CSI_MCLK, "csi-mclk", csi_mclk_parents, /* id, name, parents */ 0x134, /* offset */ 0, 0, 1, AW_CLK_FACTOR_FIXED, /* n factor (fake) */ 0, 4, 0, 0, /* m factor */ 8, 2, /* mux */ 15, /* gate */ AW_CLK_HAS_MUX | AW_CLK_HAS_GATE); /* flags */ static const char *ve_parents[] = {"pll_ve"}; NM_CLK(ve_clk, CLK_VE, "ve", ve_parents, /* id, name, parents */ 0x13C, /* offset */ 16, 3, 0, 0, /* n factor */ 0, 0, 1, AW_CLK_FACTOR_FIXED, /* m factor (fake) */ 0, 0, /* mux */ 31, /* gate */ AW_CLK_HAS_GATE); /* flags */ static const char *hdmi_parents[] = {"pll_video"}; NM_CLK(hdmi_clk, CLK_HDMI, "hdmi", hdmi_parents, /* id, name, parents */ 0x150, /* offset */ 0, 0, 1, AW_CLK_FACTOR_FIXED, /* n factor (fake) */ 0, 4, 0, 0, /* m factor */ 24, 2, /* mux */ 31, /* gate */ AW_CLK_HAS_MUX | AW_CLK_HAS_GATE); /* flags */ static const char *mbus_parents[] = {"osc24M", "pll_periph0-2x", "pll_ddr"}; NM_CLK(mbus_clk, CLK_MBUS, "mbus", mbus_parents, /* id, name, parents */ 0x15C, /* offset */ 0, 0, 1, AW_CLK_FACTOR_FIXED, /* n factor (fake) */ 0, 3, 0, 0, /* m factor */ 24, 2, /* mux */ 31, /* gate */ AW_CLK_HAS_MUX | AW_CLK_HAS_GATE); /* flags */ static const char *gpu_parents[] = {"pll_gpu"}; NM_CLK(gpu_clk, CLK_GPU, "gpu", gpu_parents, /* id, name, parents */ 0x1A0, /* offset */ 0, 2, 0, 0, /* n factor */ 0, 0, 1, AW_CLK_FACTOR_FIXED, /* m factor (fake) */ 0, 0, /* mux */ 31, /* gate */ AW_CLK_HAS_GATE); /* flags */ static struct aw_ccung_clk h3_ccu_clks[] = { { .type = AW_CLK_NKMP, .clk.nkmp = &pll_cpux_clk}, { .type = AW_CLK_NKMP, .clk.nkmp = &pll_audio_clk}, { .type = AW_CLK_NKMP, .clk.nkmp = &pll_periph0_clk}, { .type = AW_CLK_NKMP, .clk.nkmp = &pll_periph1_clk}, { .type = AW_CLK_NKMP, .clk.nkmp = &pll_ddr_clk}, { .type = AW_CLK_FRAC, .clk.frac = &pll_video_clk}, { .type = AW_CLK_FRAC, .clk.frac = &pll_ve_clk}, { .type = AW_CLK_FRAC, .clk.frac = &pll_gpu_clk}, { .type = AW_CLK_FRAC, .clk.frac = &pll_de_clk}, { .type = AW_CLK_NM, .clk.nm = &apb2_clk}, { .type = AW_CLK_NM, .clk.nm = &nand_clk}, { .type = AW_CLK_NM, .clk.nm = &mmc0_clk}, { .type = AW_CLK_NM, .clk.nm = &mmc1_clk}, { .type = AW_CLK_NM, .clk.nm = &mmc2_clk}, { .type = AW_CLK_NM, .clk.nm = &ts_clk}, { .type = AW_CLK_NM, .clk.nm = &ce_clk}, { .type = AW_CLK_NM, .clk.nm = &spi0_clk}, { .type = AW_CLK_NM, .clk.nm = &spi1_clk}, { .type = AW_CLK_NM, .clk.nm = &spdif_clk}, { .type = AW_CLK_NM, .clk.nm = &dram_clk}, { .type = AW_CLK_NM, .clk.nm = &de_clk}, { .type = AW_CLK_NM, .clk.nm = &tcon0_clk}, { .type = AW_CLK_NM, .clk.nm = &tve_clk}, { .type = AW_CLK_NM, .clk.nm = &deinterlace_clk}, { .type = AW_CLK_NM, .clk.nm = &csi_sclk_clk}, { .type = AW_CLK_NM, .clk.nm = &csi_mclk_clk}, { .type = AW_CLK_NM, .clk.nm = &ve_clk}, { .type = AW_CLK_NM, .clk.nm = &hdmi_clk}, { .type = AW_CLK_NM, .clk.nm = &mbus_clk}, { .type = AW_CLK_NM, .clk.nm = &gpu_clk}, { .type = AW_CLK_PREDIV_MUX, .clk.prediv_mux = &ahb1_clk}, { .type = AW_CLK_PREDIV_MUX, .clk.prediv_mux = &ahb2_clk}, { .type = AW_CLK_MUX, .clk.mux = &cpux_clk}, { .type = AW_CLK_MUX, .clk.mux = &i2s0mux_clk}, { .type = AW_CLK_MUX, .clk.mux = &i2s1mux_clk}, { .type = AW_CLK_MUX, .clk.mux = &i2s2mux_clk}, { .type = AW_CLK_DIV, .clk.div = &axi_clk}, { .type = AW_CLK_DIV, .clk.div = &apb1_clk}, { .type = AW_CLK_DIV, .clk.div = &thsdiv_clk}, { .type = AW_CLK_FIXED, .clk.fixed = &pll_periph0_2x_clk}, { .type = AW_CLK_FIXED, .clk.fixed = &pll_audio_2x_clk}, { .type = AW_CLK_FIXED, .clk.fixed = &pll_audio_4x_clk}, { .type = AW_CLK_FIXED, .clk.fixed = &pll_audio_8x_clk}, }; static struct aw_clk_init h3_init_clks[] = { {"ahb1", "pll_periph0", 0, false}, {"ahb2", "pll_periph0", 0, false}, {"dram", "pll_ddr", 0, false}, }; static struct ofw_compat_data compat_data[] = { #if defined(SOC_ALLWINNER_H3) { "allwinner,sun8i-h3-ccu", 1 }, #endif #if defined(SOC_ALLWINNER_H5) { "allwinner,sun50i-h5-ccu", 1 }, #endif { NULL, 0}, }; static int ccu_h3_probe(device_t dev) { if (!ofw_bus_status_okay(dev)) return (ENXIO); if (ofw_bus_search_compatible(dev, compat_data)->ocd_data == 0) return (ENXIO); device_set_desc(dev, "Allwinner H3/H5 Clock Control Unit NG"); return (BUS_PROBE_DEFAULT); } static int ccu_h3_attach(device_t dev) { struct aw_ccung_softc *sc; sc = device_get_softc(dev); sc->resets = h3_ccu_resets; sc->nresets = nitems(h3_ccu_resets); sc->gates = h3_ccu_gates; sc->ngates = nitems(h3_ccu_gates); sc->clks = h3_ccu_clks; sc->nclks = nitems(h3_ccu_clks); sc->clk_init = h3_init_clks; sc->n_clk_init = nitems(h3_init_clks); return (aw_ccung_attach(dev)); } static device_method_t ccu_h3ng_methods[] = { /* Device interface */ DEVMETHOD(device_probe, ccu_h3_probe), DEVMETHOD(device_attach, ccu_h3_attach), DEVMETHOD_END }; static devclass_t ccu_h3ng_devclass; DEFINE_CLASS_1(ccu_h3ng, ccu_h3ng_driver, ccu_h3ng_methods, sizeof(struct aw_ccung_softc), aw_ccung_driver); EARLY_DRIVER_MODULE(ccu_h3ng, simplebus, ccu_h3ng_driver, - ccu_h3ng_devclass, 0, 0, BUS_PASS_BUS + BUS_PASS_ORDER_LAST); + ccu_h3ng_devclass, 0, 0, BUS_PASS_RESOURCE + BUS_PASS_ORDER_MIDDLE); Index: head/sys/arm/allwinner/clkng/ccu_sun8i_r.c =================================================================== --- head/sys/arm/allwinner/clkng/ccu_sun8i_r.c (revision 350841) +++ head/sys/arm/allwinner/clkng/ccu_sun8i_r.c (revision 350842) @@ -1,265 +1,265 @@ /*- * SPDX-License-Identifier: BSD-2-Clause-FreeBSD * * Copyright (c) 2017,2018 Emmanuel Vadot * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. * * $FreeBSD$ */ #include __FBSDID("$FreeBSD$"); #include #include #include #include #include #include #include #include #include #include #if defined(__aarch64__) #include "opt_soc.h" #endif #include #include #include #include #include #include /* Non-exported clocks */ #define CLK_AHB0 1 #define CLK_APB0 2 static struct aw_ccung_reset ccu_sun8i_r_resets[] = { CCU_RESET(RST_APB0_IR, 0xb0, 1) CCU_RESET(RST_APB0_TIMER, 0xb0, 2) CCU_RESET(RST_APB0_RSB, 0xb0, 3) CCU_RESET(RST_APB0_UART, 0xb0, 4) CCU_RESET(RST_APB0_I2C, 0xb0, 6) }; static struct aw_ccung_gate ccu_sun8i_r_gates[] = { CCU_GATE(CLK_APB0_PIO, "apb0-pio", "apb0", 0x28, 0) CCU_GATE(CLK_APB0_IR, "apb0-ir", "apb0", 0x28, 1) CCU_GATE(CLK_APB0_TIMER, "apb0-timer", "apb0", 0x28, 2) CCU_GATE(CLK_APB0_RSB, "apb0-rsb", "apb0", 0x28, 3) CCU_GATE(CLK_APB0_UART, "apb0-uart", "apb0", 0x28, 4) CCU_GATE(CLK_APB0_I2C, "apb0-i2c", "apb0", 0x28, 6) CCU_GATE(CLK_APB0_TWD, "apb0-twd", "apb0", 0x28, 7) }; static const char *ar100_parents[] = {"osc32k", "osc24M", "pll_periph0", "iosc"}; static const char *a83t_ar100_parents[] = {"osc16M-d512", "osc24M", "pll_periph", "osc16M"}; PREDIV_CLK(ar100_clk, CLK_AR100, /* id */ "ar100", ar100_parents, /* name, parents */ 0x00, /* offset */ 16, 2, /* mux */ 4, 2, 0, AW_CLK_FACTOR_POWER_OF_TWO, /* div */ 8, 5, 0, AW_CLK_FACTOR_HAS_COND, /* prediv */ 16, 2, 2); /* prediv condition */ PREDIV_CLK(a83t_ar100_clk, CLK_AR100, /* id */ "ar100", a83t_ar100_parents, /* name, parents */ 0x00, /* offset */ 16, 2, /* mux */ 4, 2, 0, AW_CLK_FACTOR_POWER_OF_TWO, /* div */ 8, 5, 0, AW_CLK_FACTOR_HAS_COND, /* prediv */ 16, 2, 2); /* prediv condition */ static const char *ahb0_parents[] = {"ar100"}; FIXED_CLK(ahb0_clk, CLK_AHB0, /* id */ "ahb0", /* name */ ahb0_parents, /* parent */ 0, /* freq */ 1, /* mult */ 1, /* div */ 0); /* flags */ static const char *apb0_parents[] = {"ahb0"}; DIV_CLK(apb0_clk, CLK_APB0, /* id */ "apb0", apb0_parents, /* name, parents */ 0x0c, /* offset */ 0, 2, /* shift, width */ 0, NULL); /* flags, div table */ static const char *r_ccu_ir_parents[] = {"osc32k", "osc24M"}; NM_CLK(r_ccu_ir_clk, CLK_IR, /* id */ "ir", r_ccu_ir_parents, /* names, parents */ 0x54, /* offset */ 0, 4, 0, 0, /* N factor */ 16, 2, 0, 0, /* M flags */ 24, 2, /* mux */ 31, /* gate */ AW_CLK_HAS_MUX | AW_CLK_REPARENT); /* flags */ static const char *a83t_ir_parents[] = {"osc16M", "osc24M"}; static struct aw_clk_nm_def a83t_ir_clk = { .clkdef = { .id = CLK_IR, .name = "ir", .parent_names = a83t_ir_parents, .parent_cnt = nitems(a83t_ir_parents), }, .offset = 0x54, .n = {.shift = 0, .width = 4, .flags = AW_CLK_FACTOR_POWER_OF_TWO, }, .m = {.shift = 16, .width = 2}, .prediv = { .cond_shift = 24, .cond_width = 2, .cond_value = 0, .value = 16 }, .mux_shift = 24, .mux_width = 2, .flags = AW_CLK_HAS_MUX | AW_CLK_HAS_PREDIV, }; static struct aw_ccung_clk clks[] = { { .type = AW_CLK_PREDIV_MUX, .clk.prediv_mux = &ar100_clk}, { .type = AW_CLK_DIV, .clk.div = &apb0_clk}, { .type = AW_CLK_FIXED, .clk.fixed = &ahb0_clk}, { .type = AW_CLK_NM, .clk.nm = &r_ccu_ir_clk}, }; static struct aw_ccung_clk a83t_clks[] = { { .type = AW_CLK_PREDIV_MUX, .clk.prediv_mux = &a83t_ar100_clk}, { .type = AW_CLK_DIV, .clk.div = &apb0_clk}, { .type = AW_CLK_FIXED, .clk.fixed = &ahb0_clk}, { .type = AW_CLK_NM, .clk.nm = &a83t_ir_clk}, }; static struct ofw_compat_data compat_data[] = { #if defined(SOC_ALLWINNER_H3) || defined(SOC_ALLWINNER_H5) { "allwinner,sun8i-h3-r-ccu", 1 }, #endif #if defined(SOC_ALLWINNER_A64) { "allwinner,sun50i-a64-r-ccu", 1 }, #endif { NULL, 0}, }; static int ccu_sun8i_r_probe(device_t dev) { if (!ofw_bus_status_okay(dev)) return (ENXIO); if (ofw_bus_search_compatible(dev, compat_data)->ocd_data == 0) return (ENXIO); device_set_desc(dev, "Allwinner SUN8I_R Clock Control Unit NG"); return (BUS_PROBE_DEFAULT); } static int ccu_sun8i_r_attach(device_t dev) { struct aw_ccung_softc *sc; sc = device_get_softc(dev); sc->resets = ccu_sun8i_r_resets; sc->nresets = nitems(ccu_sun8i_r_resets); sc->gates = ccu_sun8i_r_gates; sc->ngates = nitems(ccu_sun8i_r_gates); sc->clks = clks; sc->nclks = nitems(clks); return (aw_ccung_attach(dev)); } static device_method_t ccu_sun8i_r_methods[] = { /* Device interface */ DEVMETHOD(device_probe, ccu_sun8i_r_probe), DEVMETHOD(device_attach, ccu_sun8i_r_attach), DEVMETHOD_END }; static devclass_t ccu_sun8i_r_devclass; DEFINE_CLASS_1(ccu_sun8i_r, ccu_sun8i_r_driver, ccu_sun8i_r_methods, sizeof(struct aw_ccung_softc), aw_ccung_driver); EARLY_DRIVER_MODULE(ccu_sun8i_r, simplebus, ccu_sun8i_r_driver, - ccu_sun8i_r_devclass, 0, 0, BUS_PASS_BUS + BUS_PASS_ORDER_LAST); + ccu_sun8i_r_devclass, 0, 0, BUS_PASS_RESOURCE + BUS_PASS_ORDER_MIDDLE); static int ccu_a83t_r_probe(device_t dev) { if (!ofw_bus_status_okay(dev)) return (ENXIO); if (!ofw_bus_is_compatible(dev, "allwinner,sun8i-a83t-r-ccu")) return (ENXIO); device_set_desc(dev, "Allwinner A83T_R Clock Control Unit NG"); return (BUS_PROBE_DEFAULT); } static int ccu_a83t_r_attach(device_t dev) { struct aw_ccung_softc *sc; sc = device_get_softc(dev); sc->resets = ccu_sun8i_r_resets; sc->nresets = nitems(ccu_sun8i_r_resets); sc->gates = ccu_sun8i_r_gates; sc->ngates = nitems(ccu_sun8i_r_gates); sc->clks = a83t_clks; sc->nclks = nitems(a83t_clks); return (aw_ccung_attach(dev)); } static device_method_t ccu_a83t_r_methods[] = { /* Device interface */ DEVMETHOD(device_probe, ccu_a83t_r_probe), DEVMETHOD(device_attach, ccu_a83t_r_attach), DEVMETHOD_END }; static devclass_t ccu_a83t_r_devclass; DEFINE_CLASS_1(ccu_a83t_r, ccu_a83t_r_driver, ccu_a83t_r_methods, sizeof(struct aw_ccung_softc), aw_ccung_driver); EARLY_DRIVER_MODULE(ccu_a83t_r, simplebus, ccu_a83t_r_driver, - ccu_a83t_r_devclass, 0, 0, BUS_PASS_BUS + BUS_PASS_ORDER_LAST); + ccu_a83t_r_devclass, 0, 0, BUS_PASS_RESOURCE + BUS_PASS_ORDER_MIDDLE);