Index: head/sys/arm/allwinner/clkng/ccu_a10.c =================================================================== --- head/sys/arm/allwinner/clkng/ccu_a10.c (revision 348180) +++ head/sys/arm/allwinner/clkng/ccu_a10.c (revision 348181) @@ -1,624 +1,624 @@ /*- * SPDX-License-Identifier: BSD-2-Clause-FreeBSD * * Copyright (c) 2018 Kyle Evans * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. * * $FreeBSD$ */ #include __FBSDID("$FreeBSD$"); #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include /* Non-exported resets */ /* Non-exported clocks */ #define CLK_PLL_CORE 2 #define CLK_AXI 3 #define CLK_AHB 4 #define CLK_APB0 5 #define CLK_APB1 6 #define CLK_PLL_VIDEO0 8 #define CLK_PLL_DDR 12 #define CLK_PLL_DDR_OTHER 13 #define CLK_PLL6 14 #define CLK_PLL_PERIPH 15 #define CLK_PLL_SATA 16 #define CLK_PLL_VIDEO1 17 /* Non-exported fixed clocks */ static struct aw_ccung_reset a10_ccu_resets[] = { CCU_RESET(RST_USB_PHY0, 0xcc, 0) CCU_RESET(RST_USB_PHY1, 0xcc, 1) CCU_RESET(RST_USB_PHY2, 0xcc, 2) CCU_RESET(RST_GPS, 0xd0, 0) CCU_RESET(RST_DE_BE0, 0x104, 30) CCU_RESET(RST_DE_BE1, 0x108, 30) CCU_RESET(RST_DE_FE0, 0x10c, 30) CCU_RESET(RST_DE_FE1, 0x110, 30) CCU_RESET(RST_DE_MP, 0x114, 30) CCU_RESET(RST_TVE0, 0x118, 29) CCU_RESET(RST_TCON0, 0x118, 30) CCU_RESET(RST_TVE1, 0x11c, 29) CCU_RESET(RST_TCON1, 0x11c, 30) CCU_RESET(RST_CSI0, 0x134, 30) CCU_RESET(RST_CSI1, 0x138, 30) CCU_RESET(RST_VE, 0x13c, 0) CCU_RESET(RST_ACE, 0x148, 16) CCU_RESET(RST_LVDS, 0x14c, 0) CCU_RESET(RST_GPU, 0x154, 30) CCU_RESET(RST_HDMI_H, 0x170, 0) CCU_RESET(RST_HDMI_SYS, 0x170, 1) CCU_RESET(RST_HDMI_AUDIO_DMA, 0x170, 2) }; static struct aw_ccung_gate a10_ccu_gates[] = { CCU_GATE(CLK_HOSC, "hosc", "osc24M", 0x50, 0) CCU_GATE(CLK_AHB_OTG, "ahb-otg", "ahb", 0x60, 0) CCU_GATE(CLK_AHB_EHCI0, "ahb-ehci0", "ahb", 0x60, 1) CCU_GATE(CLK_AHB_OHCI0, "ahb-ohci0", "ahb", 0x60, 2) CCU_GATE(CLK_AHB_EHCI1, "ahb-ehci1", "ahb", 0x60, 3) CCU_GATE(CLK_AHB_OHCI1, "ahb-ohci1", "ahb", 0x60, 4) CCU_GATE(CLK_AHB_SS, "ahb-ss", "ahb", 0x60, 5) CCU_GATE(CLK_AHB_DMA, "ahb-dma", "ahb", 0x60, 6) CCU_GATE(CLK_AHB_BIST, "ahb-bist", "ahb", 0x60, 7) CCU_GATE(CLK_AHB_MMC0, "ahb-mmc0", "ahb", 0x60, 8) CCU_GATE(CLK_AHB_MMC1, "ahb-mmc1", "ahb", 0x60, 9) CCU_GATE(CLK_AHB_MMC2, "ahb-mmc2", "ahb", 0x60, 10) CCU_GATE(CLK_AHB_MMC3, "ahb-mmc3", "ahb", 0x60, 11) CCU_GATE(CLK_AHB_MS, "ahb-ms", "ahb", 0x60, 12) CCU_GATE(CLK_AHB_NAND, "ahb-nand", "ahb", 0x60, 13) CCU_GATE(CLK_AHB_SDRAM, "ahb-sdram", "ahb", 0x60, 14) CCU_GATE(CLK_AHB_ACE, "ahb-ace", "ahb", 0x60, 16) CCU_GATE(CLK_AHB_EMAC, "ahb-emac", "ahb", 0x60, 17) CCU_GATE(CLK_AHB_TS, "ahb-ts", "ahb", 0x60, 18) CCU_GATE(CLK_AHB_SPI0, "ahb-spi0", "ahb", 0x60, 20) CCU_GATE(CLK_AHB_SPI1, "ahb-spi1", "ahb", 0x60, 21) CCU_GATE(CLK_AHB_SPI2, "ahb-spi2", "ahb", 0x60, 22) CCU_GATE(CLK_AHB_SPI3, "ahb-spi3", "ahb", 0x60, 23) CCU_GATE(CLK_AHB_SATA, "ahb-sata", "ahb", 0x60, 25) CCU_GATE(CLK_AHB_VE, "ahb-ve", "ahb", 0x64, 0) CCU_GATE(CLK_AHB_TVD, "ahb-tvd", "ahb", 0x64, 1) CCU_GATE(CLK_AHB_TVE0, "ahb-tve0", "ahb", 0x64, 2) CCU_GATE(CLK_AHB_TVE1, "ahb-tve1", "ahb", 0x64, 3) CCU_GATE(CLK_AHB_LCD0, "ahb-lcd0", "ahb", 0x64, 4) CCU_GATE(CLK_AHB_LCD1, "ahb-lcd1", "ahb", 0x64, 5) CCU_GATE(CLK_AHB_CSI0, "ahb-csi0", "ahb", 0x64, 8) CCU_GATE(CLK_AHB_CSI1, "ahb-csi1", "ahb", 0x64, 9) CCU_GATE(CLK_AHB_HDMI1, "ahb-hdmi1", "ahb", 0x64, 10) CCU_GATE(CLK_AHB_HDMI0, "ahb-hdmi0", "ahb", 0x64, 11) CCU_GATE(CLK_AHB_DE_BE0, "ahb-de_be0", "ahb", 0x64, 12) CCU_GATE(CLK_AHB_DE_BE1, "ahb-de_be1", "ahb", 0x64, 13) CCU_GATE(CLK_AHB_DE_FE0, "ahb-de_fe0", "ahb", 0x64, 14) CCU_GATE(CLK_AHB_DE_FE1, "ahb-de_fe1", "ahb", 0x64, 15) CCU_GATE(CLK_AHB_GMAC, "ahb-gmac", "ahb", 0x64, 17) CCU_GATE(CLK_AHB_MP, "ahb-mp", "ahb", 0x64, 18) CCU_GATE(CLK_AHB_GPU, "ahb-gpu", "ahb", 0x64, 20) CCU_GATE(CLK_APB0_CODEC, "apb0-codec", "apb0", 0x68, 0) CCU_GATE(CLK_APB0_SPDIF, "apb0-spdif", "apb0", 0x68, 1) CCU_GATE(CLK_APB0_AC97, "apb0-ac97", "apb0", 0x68, 2) CCU_GATE(CLK_APB0_I2S0, "apb0-i2s0", "apb0", 0x68, 3) CCU_GATE(CLK_APB0_I2S1, "apb0-i2s1", "apb0", 0x68, 4) CCU_GATE(CLK_APB0_PIO, "apb0-pi0", "apb0", 0x68, 5) CCU_GATE(CLK_APB0_IR0, "apb0-ir0", "apb0", 0x68, 6) CCU_GATE(CLK_APB0_IR1, "apb0-ir1", "apb0", 0x68, 7) CCU_GATE(CLK_APB0_I2S2, "apb0-i2s2", "apb0",0x68, 8) CCU_GATE(CLK_APB0_KEYPAD, "apb0-keypad", "apb0", 0x68, 10) CCU_GATE(CLK_APB1_I2C0, "apb1-i2c0", "apb1", 0x6c, 0) CCU_GATE(CLK_APB1_I2C1, "apb1-i2c1", "apb1",0x6c, 1) CCU_GATE(CLK_APB1_I2C2, "apb1-i2c2", "apb1",0x6c, 2) CCU_GATE(CLK_APB1_I2C3, "apb1-i2c3", "apb1",0x6c, 3) CCU_GATE(CLK_APB1_CAN, "apb1-can", "apb1",0x6c, 4) CCU_GATE(CLK_APB1_SCR, "apb1-scr", "apb1",0x6c, 5) CCU_GATE(CLK_APB1_PS20, "apb1-ps20", "apb1",0x6c, 6) CCU_GATE(CLK_APB1_PS21, "apb1-ps21", "apb1",0x6c, 7) CCU_GATE(CLK_APB1_I2C4, "apb1-i2c4", "apb1", 0x6c, 15) CCU_GATE(CLK_APB1_UART0, "apb1-uart0", "apb1",0x6c, 16) CCU_GATE(CLK_APB1_UART1, "apb1-uart1", "apb1",0x6c, 17) CCU_GATE(CLK_APB1_UART2, "apb1-uart2", "apb1",0x6c, 18) CCU_GATE(CLK_APB1_UART3, "apb1-uart3", "apb1",0x6c, 19) CCU_GATE(CLK_APB1_UART4, "apb1-uart4", "apb1",0x6c, 20) CCU_GATE(CLK_APB1_UART5, "apb1-uart5", "apb1",0x6c, 21) CCU_GATE(CLK_APB1_UART6, "apb1-uart6", "apb1",0x6c, 22) CCU_GATE(CLK_APB1_UART7, "apb1-uart7", "apb1",0x6c, 23) CCU_GATE(CLK_USB_OHCI0, "usb-ohci0", "ahb", 0xcc, 6) CCU_GATE(CLK_USB_OHCI1, "usb-ohci1", "ahb", 0xcc, 7) CCU_GATE(CLK_USB_PHY, "usb-phy", "ahb", 0xcc, 8) CCU_GATE(CLK_DRAM_VE, "dram-ve", "pll_ddr", 0x100, 0) CCU_GATE(CLK_DRAM_CSI0, "dram-csi0", "pll_ddr", 0x100, 1) CCU_GATE(CLK_DRAM_CSI1, "dram-csi1", "pll_ddr", 0x100, 2) CCU_GATE(CLK_DRAM_TS, "dram-ts", "pll_ddr", 0x100, 3) CCU_GATE(CLK_DRAM_TVD, "dram-tvd", "pll_ddr", 0x100, 4) CCU_GATE(CLK_DRAM_TVE0, "dram-tve0", "pll_ddr", 0x100, 5) CCU_GATE(CLK_DRAM_TVE1, "dram-tve1", "pll_ddr", 0x100, 6) CCU_GATE(CLK_DRAM_OUT, "dram-out", "pll_ddr", 0x100, 15) CCU_GATE(CLK_DRAM_DE_FE1, "dram-de_fe1", "pll_ddr", 0x100, 24) CCU_GATE(CLK_DRAM_DE_FE0, "dram-de_fe0", "pll_ddr", 0x100, 25) CCU_GATE(CLK_DRAM_DE_BE0, "dram-de_be0", "pll_ddr", 0x100, 26) CCU_GATE(CLK_DRAM_DE_BE1, "dram-de_be1", "pll_ddr", 0x100, 27) CCU_GATE(CLK_DRAM_MP, "dram-de_mp", "pll_ddr", 0x100, 28) CCU_GATE(CLK_DRAM_ACE, "dram-ace", "pll_ddr", 0x100, 29) }; static const char *pll_parents[] = {"osc24M"}; NKMP_CLK(pll_core_clk, CLK_PLL_CORE, /* id */ "pll_core", pll_parents, /* name, parents */ 0x00, /* offset */ 8, 5, 0, AW_CLK_FACTOR_ZERO_IS_ONE, /* n factor */ 4, 2, 0, 0, /* k factor */ 0, 2, 0, 0, /* m factor */ 16, 2, 0, AW_CLK_FACTOR_POWER_OF_TWO, /* p factor */ 31, /* gate */ 0, 0, /* lock */ AW_CLK_HAS_GATE); /* flags */ -NM_CLK_WITH_FRAC(pll_video0_clk, +FRAC_CLK(pll_video0_clk, CLK_PLL_VIDEO0, /* id */ "pll_video0", pll_parents, /* name, parents */ 0x10, /* offset */ 0, 7, 0, 0, /* n factor */ 0, 0, 1, AW_CLK_FACTOR_FIXED, /* m factor (fake) */ 31, 0, 0, /* gate, lock, lock retries */ AW_CLK_HAS_GATE, /* flags */ 270000000, 297000000, /* freq0, freq1 */ 15, 14); /* mode sel, freq sel */ static const char *pll_video0_2x_parents[] = {"pll_video0"}; FIXED_CLK(pll_video0_2x_clk, CLK_PLL_VIDEO0_2X, /* id */ "pll_video0-2x", pll_video0_2x_parents, /* name, parents */ 0, /* freq */ 2, /* mult */ 1, /* div */ 0); /* flags */ -NM_CLK_WITH_FRAC(pll_video1_clk, +FRAC_CLK(pll_video1_clk, CLK_PLL_VIDEO1, /* id */ "pll_video1", pll_parents, /* name, parents */ 0x30, /* offset */ 0, 7, 0, 0, /* n factor */ 0, 0, 1, AW_CLK_FACTOR_FIXED, /* m factor (fake) */ 31, 0, 0, /* gate, lock, lock retries */ AW_CLK_HAS_GATE, /* flags */ 270000000, 297000000, /* freq0, freq1 */ 15, 14); /* mode sel, freq sel */ static const char *pll_video1_2x_parents[] = {"pll_video1"}; FIXED_CLK(pll_video1_2x_clk, CLK_PLL_VIDEO1_2X, /* id */ "pll_video1-2x", pll_video1_2x_parents, /* name, parents */ 0, /* freq */ 2, /* mult */ 1, /* div */ 0); /* flags */ static const char *cpu_parents[] = {"osc32k", "osc24M", "pll_core", "pll_periph"}; static const char *axi_parents[] = {"cpu"}; static const char *ahb_parents[] = {"axi", "pll_periph", "pll6"}; static const char *apb0_parents[] = {"ahb"}; static const char *apb1_parents[] = {"osc24M", "pll_periph", "osc32k"}; MUX_CLK(cpu_clk, CLK_CPU, /* id */ "cpu", cpu_parents, /* name, parents */ 0x54, 16, 2); /* offset, shift, width */ NM_CLK(axi_clk, CLK_AXI, /* id */ "axi", axi_parents, /* name, parents */ 0x54, /* offset */ 0, 0, 1, AW_CLK_FACTOR_FIXED, /* n factor (fake) */ 0, 2, 0, 0, /* m factor */ 0, 0, /* mux */ 0, /* gate */ 0); /* flags */ NM_CLK(ahb_clk, CLK_AHB, /* id */ "ahb", ahb_parents, /* name, parents */ 0x54, /* offset */ 0, 0, 1, AW_CLK_FACTOR_FIXED, /* n factor (fake) */ 4, 2, 0, AW_CLK_FACTOR_POWER_OF_TWO, /* m factor */ 6, 2, /* mux */ 0, /* gate */ AW_CLK_HAS_MUX); /* flags */ NM_CLK(apb0_clk, CLK_APB0, /* id */ "apb0", apb0_parents, /* name, parents */ 0x54, /* offset */ 0, 0, 1, AW_CLK_FACTOR_FIXED, /* n factor (fake) */ 8, 2, 0, AW_CLK_FACTOR_POWER_OF_TWO | AW_CLK_FACTOR_ZERO_IS_ONE, /* m factor */ 0, 0, /* mux */ 0, /* gate */ 0); /* flags */ NM_CLK(apb1_clk, CLK_APB1, /* id */ "apb1", apb1_parents, /* name, parents */ 0x58, /* offset */ 16, 2, 0, AW_CLK_FACTOR_POWER_OF_TWO, /* n factor */ 0, 5, 0, 0, /* m factor */ 24, 2, /* mux */ 0, /* gate */ AW_CLK_HAS_MUX); /* flags */ NKMP_CLK(pll_ddr_other_clk, CLK_PLL_DDR_OTHER, /* id */ "pll_ddr_other", pll_parents, /* name, parents */ 0x20, /* offset */ 8, 5, 0, AW_CLK_FACTOR_ZERO_BASED, /* n factor */ 4, 2, 0, 0, /* k factor */ 0, 0, 1, AW_CLK_FACTOR_FIXED, /* m factor (fake) */ 2, 2, 0, AW_CLK_FACTOR_POWER_OF_TWO, /* p factor */ 31, /* gate */ 0, 0, /* lock */ AW_CLK_HAS_GATE); /* flags */ NKMP_CLK(pll_ddr_clk, CLK_PLL_DDR, /* id */ "pll_ddr", pll_parents, /* name, parents */ 0x20, /* offset */ 8, 5, 0, AW_CLK_FACTOR_ZERO_BASED, /* n factor */ 4, 2, 0, 0, /* k factor */ 0, 2, 0, 0, /* m factor */ 0, 0, 1, AW_CLK_FACTOR_FIXED, /* p factor (fake) */ 31, /* gate */ 0, 0, /* lock */ AW_CLK_HAS_GATE); /* flags */ NKMP_CLK(pll6_clk, CLK_PLL6, /* id */ "pll6", pll_parents, /* name, parents */ 0x28, /* offset */ 8, 5, 0, AW_CLK_FACTOR_ZERO_BASED, /* n factor */ 4, 2, 0, 0, /* k factor */ 0, 0, 1, AW_CLK_FACTOR_FIXED, /* m factor (fake) */ 0, 0, 1, AW_CLK_FACTOR_FIXED, /* p factor (fake) */ 31, /* gate */ 0, 0, /* lock */ AW_CLK_HAS_GATE); /* flags */ static const char *pll6_parents[] = {"pll6"}; FIXED_CLK(pll_periph_clk, CLK_PLL_PERIPH, /* id */ "pll_periph", pll6_parents, /* name, parents */ 0, /* freq */ 1, /* mult */ 2, /* div */ 0); /* flags */ NKMP_CLK(pll_periph_sata_clk, CLK_PLL_SATA, /* id */ "pll_periph_sata", pll6_parents, /* name, parents */ 0x28, /* offset */ 0, 0, 1, AW_CLK_FACTOR_FIXED, /* n factor (fake) */ 0, 0, 1, AW_CLK_FACTOR_FIXED, /* k factor (fake) */ 0, 2, 0, 0, /* m factor */ 0, 0, 6, AW_CLK_FACTOR_FIXED, /* p factor (fake, 6) */ 14, /* gate */ 0, 0, /* lock */ AW_CLK_HAS_GATE); /* flags */ static const char *mod_parents[] = {"osc24M", "pll_periph", "pll_ddr_other"}; NM_CLK(nand_clk, CLK_NAND, /* id */ "nand", mod_parents, /* name, parents */ 0x80, /* offset */ 16, 2, 0, AW_CLK_FACTOR_POWER_OF_TWO, /* n factor */ 0, 4, 0, 0, /* m factor */ 24, 2, /* mux */ 31, /* gate */ AW_CLK_HAS_MUX | AW_CLK_HAS_GATE); /* flags */ NM_CLK(ms_clk, CLK_MS, /* id */ "ms", mod_parents, /* name, parents */ 0x84, /* offset */ 16, 2, 0, AW_CLK_FACTOR_POWER_OF_TWO, /* n factor */ 0, 4, 0, 0, /* m factor */ 24, 2, /* mux */ 31, /* gate */ AW_CLK_HAS_MUX | AW_CLK_HAS_GATE); /* flags */ NM_CLK(mmc0_clk, CLK_MMC0, /* id */ "mmc0", mod_parents, /* name, parents */ 0x88, /* offset */ 16, 2, 0, AW_CLK_FACTOR_POWER_OF_TWO, /* n factor */ 0, 4, 0, 0, /* m factor */ 24, 2, /* mux */ 31, /* gate */ AW_CLK_HAS_MUX | AW_CLK_HAS_GATE | AW_CLK_REPARENT); /* flags */ NM_CLK(mmc1_clk, CLK_MMC1, /* id */ "mmc1", mod_parents, /* name, parents */ 0x8c, /* offset */ 16, 2, 0, AW_CLK_FACTOR_POWER_OF_TWO, /* n factor */ 0, 4, 0, 0, /* m factor */ 24, 2, /* mux */ 31, /* gate */ AW_CLK_HAS_MUX | AW_CLK_HAS_GATE | AW_CLK_REPARENT); /* flags */ NM_CLK(mmc2_clk, CLK_MMC2, /* id */ "mmc2", mod_parents, /* name, parents */ 0x90, /* offset */ 16, 2, 0, AW_CLK_FACTOR_POWER_OF_TWO, /* n factor */ 0, 4, 0, 0, /* m factor */ 24, 2, /* mux */ 31, /* gate */ AW_CLK_HAS_MUX | AW_CLK_HAS_GATE | AW_CLK_REPARENT); /* flags */ NM_CLK(mmc3_clk, CLK_MMC3, /* id */ "mmc3", mod_parents, /* name, parents */ 0x94, /* offset */ 16, 2, 0, AW_CLK_FACTOR_POWER_OF_TWO, /* n factor */ 0, 4, 0, 0, /* m factor */ 24, 2, /* mux */ 31, /* gate */ AW_CLK_HAS_MUX | AW_CLK_HAS_GATE | AW_CLK_REPARENT); /* flags */ NM_CLK(ts_clk, CLK_TS, /* id */ "ts", mod_parents, /* name, parents */ 0x94, /* offset */ 16, 2, 0, AW_CLK_FACTOR_POWER_OF_TWO, /* n factor */ 0, 4, 0, 0, /* m factor */ 24, 2, /* mux */ 31, /* gate */ AW_CLK_HAS_MUX | AW_CLK_HAS_GATE); /* flags */ NM_CLK(ss_clk, CLK_SS, /* id */ "ss", mod_parents, /* name, parents */ 0x9c, /* offset */ 16, 2, 0, AW_CLK_FACTOR_POWER_OF_TWO, /* n factor */ 0, 4, 0, 0, /* m factor */ 24, 2, /* mux */ 31, /* gate */ AW_CLK_HAS_MUX | AW_CLK_HAS_GATE); /* flags */ NM_CLK(spi0_clk, CLK_SPI0, /* id */ "spi0", mod_parents, /* name, parents */ 0xa0, /* offset */ 16, 2, 0, AW_CLK_FACTOR_POWER_OF_TWO, /* n factor */ 0, 4, 0, 0, /* m factor */ 24, 2, /* mux */ 31, /* gate */ AW_CLK_HAS_MUX | AW_CLK_HAS_GATE); /* flags */ NM_CLK(spi1_clk, CLK_SPI1, /* id */ "spi1", mod_parents, /* name, parents */ 0xa4, /* offset */ 16, 2, 0, AW_CLK_FACTOR_POWER_OF_TWO, /* n factor */ 0, 4, 0, 0, /* m factor */ 24, 2, /* mux */ 31, /* gate */ AW_CLK_HAS_MUX | AW_CLK_HAS_GATE); /* flags */ NM_CLK(spi2_clk, CLK_SPI2, /* id */ "spi2", mod_parents, /* name, parents */ 0xa8, /* offset */ 16, 2, 0, AW_CLK_FACTOR_POWER_OF_TWO, /* n factor */ 0, 4, 0, 0, /* m factor */ 24, 2, /* mux */ 31, /* gate */ AW_CLK_HAS_MUX | AW_CLK_HAS_GATE); /* flags */ /* MISSING CLK_PATA */ NM_CLK(ir0_clk, CLK_IR0, /* id */ "ir0", mod_parents, /* name, parents */ 0xb0, /* offset */ 16, 2, 0, AW_CLK_FACTOR_POWER_OF_TWO, /* n factor */ 0, 4, 0, 0, /* m factor */ 24, 2, /* mux */ 31, /* gate */ AW_CLK_HAS_MUX | AW_CLK_HAS_GATE); /* flags */ NM_CLK(ir1_clk, CLK_IR1, /* id */ "ir1", mod_parents, /* name, parents */ 0xb4, /* offset */ 16, 2, 0, AW_CLK_FACTOR_POWER_OF_TWO, /* n factor */ 0, 4, 0, 0, /* m factor */ 24, 2, /* mux */ 31, /* gate */ AW_CLK_HAS_MUX | AW_CLK_HAS_GATE); /* flags */ /* MISSING CLK_I2S0, CLK_AC97, CLK_SPDIF */ static const char *keypad_parents[] = {"osc24M", "osc24M", "osc32k"}; NM_CLK(keypad_clk, CLK_KEYPAD, /* id */ "keypad", keypad_parents, /* name, parents */ 0xc4, /* offset */ 16, 2, 0, AW_CLK_FACTOR_POWER_OF_TWO, /* n factor */ 0, 5, 0, 0, /* m factor */ 24, 2, /* mux */ 31, /* gate */ AW_CLK_HAS_MUX | AW_CLK_HAS_GATE); /* flags */ static const char *sata_parents[] = {"pll_periph_sata", "osc32k"}; NM_CLK(sata_clk, CLK_SATA, /* id */ "sata", sata_parents, /* name, parents */ 0xc8, /* offset */ 0, 0, 1, AW_CLK_FACTOR_FIXED, /* n factor (fake) */ 0, 0, 1, AW_CLK_FACTOR_FIXED, /* m factor (fake) */ 24, 1, /* mux */ 31, /* gate */ AW_CLK_HAS_MUX | AW_CLK_HAS_GATE); /* flags */ NM_CLK(spi3_clk, CLK_SPI3, /* id */ "spi3", mod_parents, /* name, parents */ 0xd4, /* offset */ 16, 2, 0, AW_CLK_FACTOR_POWER_OF_TWO, /* n factor */ 0, 4, 0, 0, /* m factor */ 24, 2, /* mux */ 31, /* gate */ AW_CLK_HAS_MUX | AW_CLK_HAS_GATE); /* flags */ /* MISSING CLK_I2S1, CLK_I2S2, DE Clocks */ static struct aw_ccung_clk a10_ccu_clks[] = { { .type = AW_CLK_NKMP, .clk.nkmp = &pll_core_clk}, { .type = AW_CLK_NKMP, .clk.nkmp = &pll_ddr_other_clk}, { .type = AW_CLK_NKMP, .clk.nkmp = &pll_ddr_clk}, { .type = AW_CLK_NKMP, .clk.nkmp = &pll6_clk}, { .type = AW_CLK_NKMP, .clk.nkmp = &pll_periph_sata_clk}, { .type = AW_CLK_NM, .clk.nm = &axi_clk}, { .type = AW_CLK_NM, .clk.nm = &ahb_clk}, { .type = AW_CLK_NM, .clk.nm = &apb0_clk}, { .type = AW_CLK_NM, .clk.nm = &apb1_clk}, - { .type = AW_CLK_NM, .clk.nm = &pll_video0_clk}, - { .type = AW_CLK_NM, .clk.nm = &pll_video1_clk}, + { .type = AW_CLK_FRAC, .clk.frac = &pll_video0_clk}, + { .type = AW_CLK_FRAC, .clk.frac = &pll_video1_clk}, { .type = AW_CLK_NM, .clk.nm = &nand_clk}, { .type = AW_CLK_NM, .clk.nm = &ms_clk}, { .type = AW_CLK_NM, .clk.nm = &mmc0_clk}, { .type = AW_CLK_NM, .clk.nm = &mmc1_clk}, { .type = AW_CLK_NM, .clk.nm = &mmc2_clk}, { .type = AW_CLK_NM, .clk.nm = &mmc3_clk}, { .type = AW_CLK_NM, .clk.nm = &ts_clk}, { .type = AW_CLK_NM, .clk.nm = &ss_clk}, { .type = AW_CLK_NM, .clk.nm = &spi0_clk}, { .type = AW_CLK_NM, .clk.nm = &spi1_clk}, { .type = AW_CLK_NM, .clk.nm = &spi2_clk}, { .type = AW_CLK_NM, .clk.nm = &ir0_clk}, { .type = AW_CLK_NM, .clk.nm = &ir1_clk}, { .type = AW_CLK_NM, .clk.nm = &keypad_clk}, { .type = AW_CLK_NM, .clk.nm = &sata_clk}, { .type = AW_CLK_NM, .clk.nm = &spi3_clk}, { .type = AW_CLK_MUX, .clk.mux = &cpu_clk}, { .type = AW_CLK_FIXED, .clk.fixed = &pll_periph_clk}, { .type = AW_CLK_FIXED, .clk.fixed = &pll_video0_2x_clk}, { .type = AW_CLK_FIXED, .clk.fixed = &pll_video1_2x_clk}, }; static struct aw_clk_init a10_init_clks[] = { }; static struct ofw_compat_data compat_data[] = { #if defined(SOC_ALLWINNER_A10) { "allwinner,sun4i-a10-ccu", 1 }, #endif #if defined(SOC_ALLWINNER_A20) { "allwinner,sun7i-a20-ccu", 1 }, #endif { NULL, 0}, }; static int ccu_a10_probe(device_t dev) { if (!ofw_bus_status_okay(dev)) return (ENXIO); if (ofw_bus_search_compatible(dev, compat_data)->ocd_data == 0) return (ENXIO); device_set_desc(dev, "Allwinner A10/A20 Clock Control Unit NG"); return (BUS_PROBE_DEFAULT); } static int ccu_a10_attach(device_t dev) { struct aw_ccung_softc *sc; sc = device_get_softc(dev); sc->resets = a10_ccu_resets; sc->nresets = nitems(a10_ccu_resets); sc->gates = a10_ccu_gates; sc->ngates = nitems(a10_ccu_gates); sc->clks = a10_ccu_clks; sc->nclks = nitems(a10_ccu_clks); sc->clk_init = a10_init_clks; sc->n_clk_init = nitems(a10_init_clks); return (aw_ccung_attach(dev)); } static device_method_t ccu_a10ng_methods[] = { /* Device interface */ DEVMETHOD(device_probe, ccu_a10_probe), DEVMETHOD(device_attach, ccu_a10_attach), DEVMETHOD_END }; static devclass_t ccu_a10ng_devclass; DEFINE_CLASS_1(ccu_a10ng, ccu_a10ng_driver, ccu_a10ng_methods, sizeof(struct aw_ccung_softc), aw_ccung_driver); EARLY_DRIVER_MODULE(ccu_a10ng, simplebus, ccu_a10ng_driver, ccu_a10ng_devclass, 0, 0, BUS_PASS_BUS + BUS_PASS_ORDER_MIDDLE); Index: head/sys/arm/allwinner/clkng/ccu_a31.c =================================================================== --- head/sys/arm/allwinner/clkng/ccu_a31.c (revision 348180) +++ head/sys/arm/allwinner/clkng/ccu_a31.c (revision 348181) @@ -1,976 +1,976 @@ /*- * SPDX-License-Identifier: BSD-2-Clause-FreeBSD * * Copyright (c) 2017,2018 Emmanuel Vadot * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. * * $FreeBSD$ */ #include __FBSDID("$FreeBSD$"); #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include /* Non-exported clocks */ #define CLK_PLL_CPU 0 #define CLK_PLL_AUDIO_BASE 1 #define CLK_PLL_AUDIO 2 #define CLK_PLL_AUDIO_2X 3 #define CLK_PLL_AUDIO_4X 4 #define CLK_PLL_AUDIO_8X 5 #define CLK_PLL_VIDEO0 6 #define CLK_PLL_VIDEO0_2X 7 #define CLK_PLL_VE 8 #define CLK_PLL_DDR 9 #define CLK_PLL_PERIPH_2X 11 #define CLK_PLL_VIDEO1 12 #define CLK_PLL_VIDEO1_2X 13 #define CLK_PLL_GPU 14 #define CLK_PLL_MIPI 15 #define CLK_PLL9 16 #define CLK_PLL10 17 #define CLK_AXI 19 #define CLK_AHB1 20 #define CLK_APB1 21 #define CLK_APB2 22 #define CLK_MDFS 107 #define CLK_SDRAM0 108 #define CLK_SDRAM1 109 #define CLK_MBUS0 141 #define CLK_MBUS1 142 static struct aw_ccung_reset a31_ccu_resets[] = { CCU_RESET(RST_USB_PHY0, 0xcc, 0) CCU_RESET(RST_USB_PHY1, 0xcc, 1) CCU_RESET(RST_USB_PHY2, 0xcc, 2) CCU_RESET(RST_AHB1_MIPI_DSI, 0x2c0, 1) CCU_RESET(RST_AHB1_SS, 0x2c0, 5) CCU_RESET(RST_AHB1_DMA, 0x2c0, 6) CCU_RESET(RST_AHB1_MMC0, 0x2c0, 8) CCU_RESET(RST_AHB1_MMC1, 0x2c0, 9) CCU_RESET(RST_AHB1_MMC2, 0x2c0, 10) CCU_RESET(RST_AHB1_MMC3, 0x2c0, 11) CCU_RESET(RST_AHB1_NAND1, 0x2c0, 12) CCU_RESET(RST_AHB1_NAND0, 0x2c0, 13) CCU_RESET(RST_AHB1_SDRAM, 0x2c0, 14) CCU_RESET(RST_AHB1_EMAC, 0x2c0, 17) CCU_RESET(RST_AHB1_TS, 0x2c0, 18) CCU_RESET(RST_AHB1_HSTIMER, 0x2c0, 19) CCU_RESET(RST_AHB1_SPI0, 0x2c0, 20) CCU_RESET(RST_AHB1_SPI1, 0x2c0, 21) CCU_RESET(RST_AHB1_SPI2, 0x2c0, 22) CCU_RESET(RST_AHB1_SPI3, 0x2c0, 23) CCU_RESET(RST_AHB1_OTG, 0x2c0, 24) CCU_RESET(RST_AHB1_EHCI0, 0x2c0, 26) CCU_RESET(RST_AHB1_EHCI1, 0x2c0, 27) CCU_RESET(RST_AHB1_OHCI0, 0x2c0, 29) CCU_RESET(RST_AHB1_OHCI1, 0x2c0, 30) CCU_RESET(RST_AHB1_OHCI2, 0x2c0, 31) CCU_RESET(RST_AHB1_VE, 0x2c4, 0) CCU_RESET(RST_AHB1_LCD0, 0x2c4, 4) CCU_RESET(RST_AHB1_LCD1, 0x2c4, 5) CCU_RESET(RST_AHB1_CSI, 0x2c4, 8) CCU_RESET(RST_AHB1_HDMI, 0x2c4, 11) CCU_RESET(RST_AHB1_BE0, 0x2c4, 12) CCU_RESET(RST_AHB1_BE1, 0x2c4, 13) CCU_RESET(RST_AHB1_FE0, 0x2c4, 14) CCU_RESET(RST_AHB1_FE1, 0x2c4, 15) CCU_RESET(RST_AHB1_MP, 0x2c4, 18) CCU_RESET(RST_AHB1_GPU, 0x2c4, 20) CCU_RESET(RST_AHB1_DEU0, 0x2c4, 23) CCU_RESET(RST_AHB1_DEU1, 0x2c4, 24) CCU_RESET(RST_AHB1_DRC0, 0x2c4, 25) CCU_RESET(RST_AHB1_DRC1, 0x2c4, 26) CCU_RESET(RST_AHB1_LVDS, 0x2c8, 0) CCU_RESET(RST_APB1_CODEC, 0x2d0, 0) CCU_RESET(RST_APB1_SPDIF, 0x2d0, 1) CCU_RESET(RST_APB1_DIGITAL_MIC, 0x2d0, 4) CCU_RESET(RST_APB1_DAUDIO0, 0x2d0, 12) CCU_RESET(RST_APB1_DAUDIO1, 0x2d0, 13) CCU_RESET(RST_APB2_I2C0, 0x2d8, 0) CCU_RESET(RST_APB2_I2C1, 0x2d8, 1) CCU_RESET(RST_APB2_I2C2, 0x2d8, 2) CCU_RESET(RST_APB2_I2C3, 0x2d8, 3) CCU_RESET(RST_APB2_UART0, 0x2d8, 16) CCU_RESET(RST_APB2_UART1, 0x2d8, 17) CCU_RESET(RST_APB2_UART2, 0x2d8, 18) CCU_RESET(RST_APB2_UART3, 0x2d8, 19) CCU_RESET(RST_APB2_UART4, 0x2d8, 20) CCU_RESET(RST_APB2_UART5, 0x2d8, 21) }; static struct aw_ccung_gate a31_ccu_gates[] = { CCU_GATE(CLK_AHB1_MIPIDSI, "ahb1-mipidsi", "ahb1", 0x60, 1) CCU_GATE(CLK_AHB1_SS, "ahb1-ss", "ahb1", 0x60, 5) CCU_GATE(CLK_AHB1_DMA, "ahb1-dma", "ahb1", 0x60, 6) CCU_GATE(CLK_AHB1_MMC0, "ahb1-mmc0", "ahb1", 0x60, 8) CCU_GATE(CLK_AHB1_MMC1, "ahb1-mmc1", "ahb1", 0x60, 9) CCU_GATE(CLK_AHB1_MMC2, "ahb1-mmc2", "ahb1", 0x60, 10) CCU_GATE(CLK_AHB1_MMC3, "ahb1-mmc3", "ahb1", 0x60, 11) CCU_GATE(CLK_AHB1_NAND1, "ahb1-nand1", "ahb1", 0x60, 12) CCU_GATE(CLK_AHB1_NAND0, "ahb1-nand0", "ahb1", 0x60, 13) CCU_GATE(CLK_AHB1_SDRAM, "ahb1-sdram", "ahb1", 0x60, 14) CCU_GATE(CLK_AHB1_EMAC, "ahb1-emac", "ahb1", 0x60, 17) CCU_GATE(CLK_AHB1_TS, "ahb1-ts", "ahb1", 0x60, 18) CCU_GATE(CLK_AHB1_HSTIMER, "ahb1-hstimer", "ahb1", 0x60, 19) CCU_GATE(CLK_AHB1_SPI0, "ahb1-spi0", "ahb1", 0x60, 20) CCU_GATE(CLK_AHB1_SPI1, "ahb1-spi1", "ahb1", 0x60, 21) CCU_GATE(CLK_AHB1_SPI2, "ahb1-spi2", "ahb1", 0x60, 22) CCU_GATE(CLK_AHB1_SPI3, "ahb1-spi3", "ahb1", 0x60, 23) CCU_GATE(CLK_AHB1_OTG, "ahb1-otg", "ahb1", 0x60, 24) CCU_GATE(CLK_AHB1_EHCI0, "ahb1-ehci0", "ahb1", 0x60, 26) CCU_GATE(CLK_AHB1_EHCI1, "ahb1-ehci1", "ahb1", 0x60, 27) CCU_GATE(CLK_AHB1_OHCI0, "ahb1-ohci0", "ahb1", 0x60, 29) CCU_GATE(CLK_AHB1_OHCI1, "ahb1-ohci1", "ahb1", 0x60, 30) CCU_GATE(CLK_AHB1_OHCI2, "ahb1-ohci2", "ahb1", 0x60, 31) CCU_GATE(CLK_AHB1_VE, "ahb1-ve", "ahb1", 0x64, 0) CCU_GATE(CLK_AHB1_LCD0, "ahb1-lcd0", "ahb1", 0x64, 4) CCU_GATE(CLK_AHB1_LCD1, "ahb1-lcd1", "ahb1", 0x64, 5) CCU_GATE(CLK_AHB1_CSI, "ahb1-csi", "ahb1", 0x64, 8) CCU_GATE(CLK_AHB1_HDMI, "ahb1-hdmi", "ahb1", 0x64, 11) CCU_GATE(CLK_AHB1_BE0, "ahb1-be0", "ahb1", 0x64, 12) CCU_GATE(CLK_AHB1_BE1, "ahb1-be1", "ahb1", 0x64, 13) CCU_GATE(CLK_AHB1_FE0, "ahb1-fe0", "ahb1", 0x64, 14) CCU_GATE(CLK_AHB1_FE1, "ahb1-fe1", "ahb1", 0x64, 15) CCU_GATE(CLK_AHB1_MP, "ahb1-mp", "ahb1", 0x64, 18) CCU_GATE(CLK_AHB1_GPU, "ahb1-gpu", "ahb1", 0x64, 20) CCU_GATE(CLK_AHB1_DEU0, "ahb1-deu0", "ahb1", 0x64, 23) CCU_GATE(CLK_AHB1_DEU1, "ahb1-deu1", "ahb1", 0x64, 24) CCU_GATE(CLK_AHB1_DRC0, "ahb1-drc0", "ahb1", 0x64, 25) CCU_GATE(CLK_AHB1_DRC1, "ahb1-drc1", "ahb1", 0x64, 26) CCU_GATE(CLK_APB1_CODEC, "apb1-codec", "apb1", 0x68, 0) CCU_GATE(CLK_APB1_SPDIF, "apb1-spdif", "apb1", 0x68, 1) CCU_GATE(CLK_APB1_DIGITAL_MIC, "apb1-digital-mic", "apb1", 0x68, 4) CCU_GATE(CLK_APB1_PIO, "apb1-pio", "apb1", 0x68, 5) CCU_GATE(CLK_APB1_DAUDIO0, "apb1-daudio0", "apb1", 0x68, 12) CCU_GATE(CLK_APB1_DAUDIO1, "apb1-daudio1", "apb1", 0x68, 13) CCU_GATE(CLK_APB2_I2C0, "apb2-i2c0", "apb2", 0x6c, 0) CCU_GATE(CLK_APB2_I2C1, "apb2-i2c1", "apb2", 0x6c, 1) CCU_GATE(CLK_APB2_I2C2, "apb2-i2c2", "apb2", 0x6c, 2) CCU_GATE(CLK_APB2_I2C3, "apb2-i2c3", "apb2", 0x6c, 3) CCU_GATE(CLK_APB2_UART0, "apb2-uart0", "apb2", 0x6c, 16) CCU_GATE(CLK_APB2_UART1, "apb2-uart1", "apb2", 0x6c, 17) CCU_GATE(CLK_APB2_UART2, "apb2-uart2", "apb2", 0x6c, 18) CCU_GATE(CLK_APB2_UART3, "apb2-uart3", "apb2", 0x6c, 19) CCU_GATE(CLK_APB2_UART4, "apb2-uart4", "apb2", 0x6c, 20) CCU_GATE(CLK_APB2_UART5, "apb2-uart5", "apb2", 0x6c, 21) CCU_GATE(CLK_DAUDIO0, "daudio0", "daudio0mux", 0xb0, 31) CCU_GATE(CLK_DAUDIO1, "daudio1", "daudio1mux", 0xb4, 31) CCU_GATE(CLK_USB_PHY0, "usb-phy0", "osc24M", 0xcc, 8) CCU_GATE(CLK_USB_PHY1, "usb-phy1", "osc24M", 0xcc, 9) CCU_GATE(CLK_USB_PHY2, "usb-phy2", "osc24M", 0xcc, 10) CCU_GATE(CLK_USB_OHCI0, "usb-ohci0", "osc24M", 0xcc, 16) CCU_GATE(CLK_USB_OHCI1, "usb-ohci1", "osc24M", 0xcc, 17) CCU_GATE(CLK_USB_OHCI2, "usb-ohci2", "osc24M", 0xcc, 18) CCU_GATE(CLK_DRAM_VE, "dram-ve", "mdfs", 0x100, 0) CCU_GATE(CLK_DRAM_CSI_ISP, "dram-csi_isp", "mdfs", 0x100, 1) CCU_GATE(CLK_DRAM_TS, "dram-ts", "mdfs", 0x100, 3) CCU_GATE(CLK_DRAM_DRC0, "dram-drc0", "mdfs", 0x100, 16) CCU_GATE(CLK_DRAM_DRC1, "dram-drc1", "mdfs", 0x100, 17) CCU_GATE(CLK_DRAM_DEU0, "dram-deu0", "mdfs", 0x100, 18) CCU_GATE(CLK_DRAM_DEU1, "dram-deu1", "mdfs", 0x100, 19) CCU_GATE(CLK_DRAM_FE0, "dram-fe0", "mdfs", 0x100, 24) CCU_GATE(CLK_DRAM_FE1, "dram-fe1", "mdfs", 0x100, 25) CCU_GATE(CLK_DRAM_BE0, "dram-be0", "mdfs", 0x100, 26) CCU_GATE(CLK_DRAM_BE1, "dram-be1", "mdfs", 0x100, 27) CCU_GATE(CLK_DRAM_MP, "dram-mp", "mdfs", 0x100, 28) CCU_GATE(CLK_CODEC, "codec", "pll_audio", 0x140, 31) CCU_GATE(CLK_AVS, "avs", "pll_audio", 0x144, 31) CCU_GATE(CLK_DIGITAL_MIC, "digital-mic", "pll_audio", 0x148, 31) CCU_GATE(CLK_HDMI_DDC, "hdmi-ddc", "osc24M", 0x150, 30) CCU_GATE(CLK_PS, "ps", "lcd1_ch1", 0x154, 31) }; static const char *pll_parents[] = {"osc24M"}; NKMP_CLK(pll_cpu_clk, CLK_PLL_CPU, /* id */ "pll_cpu", pll_parents, /* name, parents */ 0x00, /* offset */ 8, 5, 0, 0, /* n factor */ 4, 2, 0, 0, /* k factor */ 0, 2, 0, 0, /* m factor */ 0, 0, 1, AW_CLK_FACTOR_FIXED, /* p factor (fake) */ 31, /* gate */ 28, 1000, /* lock */ AW_CLK_HAS_GATE | AW_CLK_HAS_LOCK | AW_CLK_SCALE_CHANGE); /* flags */ NKMP_CLK(pll_audio_clk, CLK_PLL_AUDIO, /* id */ "pll_audio", pll_parents, /* name, parents */ 0x08, /* offset */ 8, 7, 0, 0, /* n factor */ 0, 0, 1, AW_CLK_FACTOR_FIXED, /* k factor (fake) */ 0, 4, 1, 0, /* m factor */ 16, 3, 1, 0, /* p factor */ 31, /* gate */ 28, 1000, /* lock */ AW_CLK_HAS_GATE | AW_CLK_HAS_LOCK); /* flags */ static const char *pll_audio_mult_parents[] = {"pll_audio"}; FIXED_CLK(pll_audio_2x_clk, CLK_PLL_AUDIO_2X, /* id */ "pll_audio-2x", /* name */ pll_audio_mult_parents, /* parent */ 0, /* freq */ 2, /* mult */ 1, /* div */ 0); /* flags */ FIXED_CLK(pll_audio_4x_clk, CLK_PLL_AUDIO_4X, /* id */ "pll_audio-4x", /* name */ pll_audio_mult_parents, /* parent */ 0, /* freq */ 4, /* mult */ 1, /* div */ 0); /* flags */ FIXED_CLK(pll_audio_8x_clk, CLK_PLL_AUDIO_8X, /* id */ "pll_audio-8x", /* name */ pll_audio_mult_parents, /* parent */ 0, /* freq */ 8, /* mult */ 1, /* div */ 0); /* flags */ -NM_CLK_WITH_FRAC(pll_video0_clk, +FRAC_CLK(pll_video0_clk, CLK_PLL_VIDEO0, /* id */ "pll_video0", pll_parents, /* name, parents */ 0x10, /* offset */ 8, 7, 0, 0, /* n factor */ 0, 4, 0, 0, /* m factor */ 31, 28, 1000, /* gate, lock, lock retries */ AW_CLK_HAS_LOCK, /* flags */ 270000000, 297000000, /* freq0, freq1 */ 24, 25); /* mode sel, freq sel */ static const char *pll_video0_2x_parents[] = {"pll_video0"}; FIXED_CLK(pll_video0_2x_clk, CLK_PLL_VIDEO0_2X, /* id */ "pll_video0-2x", /* name */ pll_video0_2x_parents, /* parent */ 0, /* freq */ 2, /* mult */ 1, /* div */ 0); /* flags */ -NM_CLK_WITH_FRAC(pll_ve_clk, +FRAC_CLK(pll_ve_clk, CLK_PLL_VE, /* id */ "pll_ve", pll_parents, /* name, parents */ 0x18, /* offset */ 8, 7, 0, 0, /* n factor */ 0, 4, 0, 0, /* m factor */ 31, 28, 1000, /* gate, lock, lock retries */ AW_CLK_HAS_LOCK, /* flags */ 270000000, 297000000, /* freq0, freq1 */ 24, 25); /* mode sel, freq sel */ NKMP_CLK_WITH_UPDATE(pll_ddr_clk, CLK_PLL_DDR, /* id */ "pll_ddr", pll_parents, /* name, parents */ 0x20, /* offset */ 8, 5, 0, 0, /* n factor */ 4, 2, 0, 0, /* k factor */ 0, 2, 0, 0, /* m factor */ 0, 0, 1, AW_CLK_FACTOR_FIXED, /* p factor (fake) */ 31, /* gate */ 28, 1000, /* lock */ 20, /* update */ AW_CLK_HAS_GATE | AW_CLK_HAS_LOCK); /* flags */ NKMP_CLK(pll_periph_clk, CLK_PLL_PERIPH, /* id */ "pll_periph", pll_parents, /* name, parents */ 0x28, /* offset */ 8, 4, 0, 0, /* n factor */ 5, 2, 1, 0, /* k factor */ 0, 0, 1, AW_CLK_FACTOR_FIXED, /* m factor (fake) */ 0, 0, 1, AW_CLK_FACTOR_FIXED, /* p factor (fake) */ 31, /* gate */ 28, 1000, /* lock */ AW_CLK_HAS_GATE | AW_CLK_HAS_LOCK); /* flags */ static const char *pll_periph_2x_parents[] = {"pll_periph"}; FIXED_CLK(pll_periph_2x_clk, CLK_PLL_PERIPH_2X, /* id */ "pll_periph-2x", /* name */ pll_periph_2x_parents, /* parent */ 0, /* freq */ 2, /* mult */ 1, /* div */ 0); /* flags */ -NM_CLK_WITH_FRAC(pll_video1_clk, +FRAC_CLK(pll_video1_clk, CLK_PLL_VIDEO1, /* id */ "pll_video1", pll_parents, /* name, parents */ 0x30, /* offset */ 8, 7, 0, 0, /* n factor */ 0, 4, 0, 0, /* m factor */ 31, 28, 1000, /* gate, lock, lock retries */ AW_CLK_HAS_LOCK, /* flags */ 270000000, 297000000, /* freq0, freq1 */ 24, 25); /* mode sel, freq sel */ static const char *pll_video1_2x_parents[] = {"pll_video1"}; FIXED_CLK(pll_video1_2x_clk, CLK_PLL_VIDEO1_2X, /* id */ "pll_video1-2x", /* name */ pll_video1_2x_parents, /* parent */ 0, /* freq */ 2, /* mult */ 1, /* div */ 0); /* flags */ -NM_CLK_WITH_FRAC(pll_gpu_clk, +FRAC_CLK(pll_gpu_clk, CLK_PLL_GPU, /* id */ "pll_gpu", pll_parents, /* name, parents */ 0x38, /* offset */ 8, 7, 0, 0, /* n factor */ 0, 4, 0, 0, /* m factor */ 31, 28, 1000, /* gate, lock, lock retries */ AW_CLK_HAS_LOCK, /* flags */ 270000000, 297000000, /* freq0, freq1 */ 24, 25); /* mode sel, freq sel */ static const char *pll_mipi_parents[] = {"pll_video0", "pll_video1"}; NKMP_CLK(pll_mipi_clk, CLK_PLL_MIPI, /* id */ "pll_mipi", pll_mipi_parents, /* name, parents */ 0x40, /* offset */ 8, 4, 0, 0, /* n factor */ 4, 2, 1, 0, /* k factor */ 0, 2, 0, 0, /* m factor (fake) */ 0, 0, 1, AW_CLK_FACTOR_FIXED, /* p factor (fake) */ 31, /* gate */ 28, 1000, /* lock */ AW_CLK_HAS_GATE | AW_CLK_HAS_LOCK); /* flags */ -NM_CLK_WITH_FRAC(pll9_clk, +FRAC_CLK(pll9_clk, CLK_PLL9, /* id */ "pll9", pll_parents, /* name, parents */ 0x44, /* offset */ 8, 7, 0, 0, /* n factor */ 0, 4, 0, 0, /* m factor */ 31, 28, 1000, /* gate, lock, lock retries */ AW_CLK_HAS_LOCK, /* flags */ 270000000, 297000000, /* freq0, freq1 */ 24, 25); /* mode sel, freq sel */ -NM_CLK_WITH_FRAC(pll10_clk, +FRAC_CLK(pll10_clk, CLK_PLL10, /* id */ "pll10", pll_parents, /* name, parents */ 0x48, /* offset */ 8, 7, 0, 0, /* n factor */ 0, 4, 0, 0, /* m factor */ 31, 28, 1000, /* gate, lock, lock retries */ AW_CLK_HAS_LOCK, /* flags */ 270000000, 297000000, /* freq0, freq1 */ 24, 25); /* mode sel, freq sel */ static struct clk_div_table axi_div_table[] = { { .value = 0, .divider = 1, }, { .value = 1, .divider = 2, }, { .value = 2, .divider = 3, }, { .value = 3, .divider = 4, }, { .value = 4, .divider = 4, }, { .value = 5, .divider = 4, }, { .value = 6, .divider = 4, }, { .value = 7, .divider = 4, }, { }, }; static const char *axi_parents[] = {"cpu"}; DIV_CLK(axi_clk, CLK_AXI, /* id */ "axi", axi_parents, /* name, parents */ 0x50, /* offset */ 0, 2, /* shift, mask */ 0, axi_div_table); /* flags, div table */ static const char *cpu_parents[] = {"osc32k", "osc24M", "pll_cpu", "pll_cpu"}; MUX_CLK(cpu_clk, CLK_CPU, /* id */ "cpu", cpu_parents, /* name, parents */ 0x50, 16, 2); /* offset, shift, width */ static const char *ahb1_parents[] = {"osc32k", "osc24M", "axi", "pll_periph"}; PREDIV_CLK(ahb1_clk, CLK_AHB1, /* id */ "ahb1", ahb1_parents, /* name, parents */ 0x54, /* offset */ 12, 2, /* mux */ 4, 2, 0, AW_CLK_FACTOR_POWER_OF_TWO, /* div */ 6, 2, 0, AW_CLK_FACTOR_HAS_COND, /* prediv */ 12, 2, 3); /* prediv condition */ static const char *apb1_parents[] = {"ahb1"}; static struct clk_div_table apb1_div_table[] = { { .value = 0, .divider = 2, }, { .value = 1, .divider = 2, }, { .value = 2, .divider = 4, }, { .value = 3, .divider = 8, }, { }, }; DIV_CLK(apb1_clk, CLK_APB1, /* id */ "apb1", apb1_parents, /* name, parents */ 0x54, /* offset */ 8, 2, /* shift, mask */ CLK_DIV_WITH_TABLE, /* flags */ apb1_div_table); /* div table */ static const char *apb2_parents[] = {"osc32k", "osc24M", "pll_periph", "pll_periph"}; NM_CLK(apb2_clk, CLK_APB2, /* id */ "apb2", apb2_parents, /* name, parents */ 0x58, /* offset */ 16, 2, 0, AW_CLK_FACTOR_POWER_OF_TWO, /* n factor */ 0, 5, 0, 0, /* m factor */ 24, 2, /* mux */ 0, /* gate */ AW_CLK_HAS_MUX); static const char *mod_parents[] = {"osc24M", "pll_periph"}; NM_CLK(nand0_clk, CLK_NAND0, "nand0", mod_parents, /* id, name, parents */ 0x80, /* offset */ 16, 3, 0, AW_CLK_FACTOR_POWER_OF_TWO, /* n factor */ 0, 4, 0, 0, /* m factor */ 24, 2, /* mux */ 31, /* gate */ AW_CLK_HAS_GATE | AW_CLK_HAS_MUX); /* flags */ NM_CLK(nand1_clk, CLK_NAND1, "nand1", mod_parents, /* id, name, parents */ 0x80, /* offset */ 16, 3, 0, AW_CLK_FACTOR_POWER_OF_TWO, /* n factor */ 0, 4, 0, 0, /* m factor */ 24, 2, /* mux */ 31, /* gate */ AW_CLK_HAS_GATE | AW_CLK_HAS_MUX); /* flags */ NM_CLK(mmc0_clk, CLK_MMC0, "mmc0", mod_parents, /* id, name, parents */ 0x88, /* offset */ 16, 2, 0, AW_CLK_FACTOR_POWER_OF_TWO, /* n factor */ 0, 4, 0, 0, /* m factor */ 24, 2, /* mux */ 31, /* gate */ AW_CLK_HAS_GATE | AW_CLK_HAS_MUX | AW_CLK_REPARENT); /* flags */ NM_CLK(mmc1_clk, CLK_MMC1, "mmc1", mod_parents, /* id, name, parents */ 0x8c, /* offset */ 16, 2, 0, AW_CLK_FACTOR_POWER_OF_TWO, /* n factor */ 0, 4, 0, 0, /* m factor */ 24, 2, /* mux */ 31, /* gate */ AW_CLK_HAS_GATE | AW_CLK_HAS_MUX | AW_CLK_REPARENT); /* flags */ NM_CLK(mmc2_clk, CLK_MMC2, "mmc2", mod_parents, /* id, name, parents */ 0x90, /* offset */ 16, 2, 0, AW_CLK_FACTOR_POWER_OF_TWO, /* n factor */ 0, 4, 0, 0, /* m factor */ 24, 2, /* mux */ 31, /* gate */ AW_CLK_HAS_GATE | AW_CLK_HAS_MUX | AW_CLK_REPARENT); /* flags */ NM_CLK(mmc3_clk, CLK_MMC2, "mmc3", mod_parents, /* id, name, parents */ 0x94, /* offset */ 16, 2, 0, AW_CLK_FACTOR_POWER_OF_TWO, /* n factor */ 0, 4, 0, 0, /* m factor */ 24, 2, /* mux */ 31, /* gate */ AW_CLK_HAS_GATE | AW_CLK_HAS_MUX | AW_CLK_REPARENT); /* flags */ static const char *ts_parents[] = {"osc24M", "pll_periph"}; NM_CLK(ts_clk, CLK_TS, "ts", ts_parents, /* id, name, parents */ 0x98, /* offset */ 16, 2, 0, AW_CLK_FACTOR_POWER_OF_TWO, /* n factor */ 0, 4, 0, 0, /* m factor */ 24, 4, /* mux */ 31, /* gate */ AW_CLK_HAS_GATE | AW_CLK_HAS_MUX); /* flags */ NM_CLK(ss_clk, CLK_SS, "ss", mod_parents, /* id, name, parents */ 0x9C, /* offset */ 16, 2, 0, AW_CLK_FACTOR_POWER_OF_TWO, /* n factor */ 0, 4, 0, 0, /* m factor */ 24, 4, /* mux */ 31, /* gate */ AW_CLK_HAS_GATE | AW_CLK_HAS_MUX); /* flags */ NM_CLK(spi0_clk, CLK_SPI0, "spi0", mod_parents, /* id, name, parents */ 0xA0, /* offset */ 16, 2, 0, AW_CLK_FACTOR_POWER_OF_TWO, /* n factor */ 0, 4, 0, 0, /* m factor */ 24, 4, /* mux */ 31, /* gate */ AW_CLK_HAS_GATE | AW_CLK_HAS_MUX); /* flags */ NM_CLK(spi1_clk, CLK_SPI1, "spi1", mod_parents, /* id, name, parents */ 0xA4, /* offset */ 16, 2, 0, AW_CLK_FACTOR_POWER_OF_TWO, /* n factor */ 0, 4, 0, 0, /* m factor */ 24, 4, /* mux */ 31, /* gate */ AW_CLK_HAS_GATE | AW_CLK_HAS_MUX); /* flags */ NM_CLK(spi2_clk, CLK_SPI2, "spi2", mod_parents, /* id, name, parents */ 0xA8, /* offset */ 16, 2, 0, AW_CLK_FACTOR_POWER_OF_TWO, /* n factor */ 0, 4, 0, 0, /* m factor */ 24, 4, /* mux */ 31, /* gate */ AW_CLK_HAS_GATE | AW_CLK_HAS_MUX); /* flags */ NM_CLK(spi3_clk, CLK_SPI3, "spi3", mod_parents, /* id, name, parents */ 0xAC, /* offset */ 16, 2, 0, AW_CLK_FACTOR_POWER_OF_TWO, /* n factor */ 0, 4, 0, 0, /* m factor */ 24, 4, /* mux */ 31, /* gate */ AW_CLK_HAS_GATE | AW_CLK_HAS_MUX); /* flags */ static const char *daudio_parents[] = {"pll_audio-8x", "pll_audio-4x", "pll_audio-2x", "pll_audio"}; MUX_CLK(daudio0mux_clk, 0, "daudio0mux", daudio_parents, 0xb0, 16, 2); MUX_CLK(daudio1mux_clk, 0, "daudio1mux", daudio_parents, 0xb4, 16, 2); static const char *mdfs_parents[] = {"pll_ddr", "pll_periph"}; NM_CLK(mdfs_clk, CLK_MDFS, "mdfs", mdfs_parents, /* id, name, parents */ 0xF0, /* offset */ 16, 2, 0, AW_CLK_FACTOR_POWER_OF_TWO, /* n factor */ 0, 4, 0, 0, /* m factor */ 24, 4, /* mux */ 31, /* gate */ AW_CLK_HAS_GATE | AW_CLK_HAS_MUX); /* flags */ static const char *dram_parents[] = {"pll_ddr", "pll_periph"}; NM_CLK(sdram0_clk, CLK_SDRAM0, "sdram0", dram_parents, /* id, name, parents */ 0xF4, /* offset */ 0, 0, 1, AW_CLK_FACTOR_FIXED, /* n factor (fake) */ 0, 4, 0, 0, /* m factor */ 4, 1, /* mux */ 0, /* gate */ AW_CLK_HAS_MUX); /* flags */ NM_CLK(sdram1_clk, CLK_SDRAM1, "sdram1", dram_parents, /* id, name, parents */ 0xF4, /* offset */ 0, 0, 1, AW_CLK_FACTOR_FIXED, /* n factor (fake) */ 8, 4, 0, 0, /* m factor */ 12, 1, /* mux */ 0, /* gate */ AW_CLK_HAS_MUX); /* flags */ static const char *befe_parents[] = {"pll_video0", "pll_video1", "pll_periph-2x", "pll_gpu", "pll9", "pll10"}; NM_CLK(be0_clk, CLK_BE0, "be0", befe_parents, /* id, name, parents */ 0x104, /* offset */ 0, 0, 1, AW_CLK_FACTOR_FIXED, /* n factor (fake) */ 0, 4, 0, 0, /* m factor */ 24, 3, /* mux */ 31, /* gate */ AW_CLK_HAS_MUX | AW_CLK_HAS_GATE); /* flags */ NM_CLK(be1_clk, CLK_BE1, "be1", befe_parents, /* id, name, parents */ 0x108, /* offset */ 0, 0, 1, AW_CLK_FACTOR_FIXED, /* n factor (fake) */ 0, 4, 0, 0, /* m factor */ 24, 3, /* mux */ 31, /* gate */ AW_CLK_HAS_MUX | AW_CLK_HAS_GATE); /* flags */ NM_CLK(fe0_clk, CLK_FE0, "fe0", befe_parents, /* id, name, parents */ 0x104, /* offset */ 0, 0, 1, AW_CLK_FACTOR_FIXED, /* n factor (fake) */ 0, 4, 0, 0, /* m factor */ 24, 3, /* mux */ 31, /* gate */ AW_CLK_HAS_MUX | AW_CLK_HAS_GATE); /* flags */ NM_CLK(fe1_clk, CLK_FE1, "fe1", befe_parents, /* id, name, parents */ 0x108, /* offset */ 0, 0, 1, AW_CLK_FACTOR_FIXED, /* n factor (fake) */ 0, 4, 0, 0, /* m factor */ 24, 3, /* mux */ 31, /* gate */ AW_CLK_HAS_MUX | AW_CLK_HAS_GATE); /* flags */ static const char *mp_parents[] = {"pll_video0", "pll_video1", "pll9", "pll10"}; NM_CLK(mp_clk, CLK_MP, "mp", mp_parents, /* id, name, parents */ 0x108, /* offset */ 0, 0, 1, AW_CLK_FACTOR_FIXED, /* n factor (fake) */ 0, 4, 0, 0, /* m factor */ 24, 3, /* mux */ 31, /* gate */ AW_CLK_HAS_MUX | AW_CLK_HAS_GATE); /* flags */ static const char *lcd_ch0_parents[] = {"pll_video0", "pll_video1", "pll_video0-2x", "pll_video1-2x", "pll_mipi"}; NM_CLK(lcd0_ch0_clk, CLK_LCD0_CH0, "lcd0_ch0", lcd_ch0_parents, /* id, name, parents */ 0x118, /* offset */ 0, 0, 1, AW_CLK_FACTOR_FIXED, /* n factor (fake) */ 0, 0, 1, AW_CLK_FACTOR_FIXED, /* m factor (fake )*/ 24, 3, /* mux */ 31, /* gate */ AW_CLK_HAS_MUX | AW_CLK_HAS_GATE); /* flags */ NM_CLK(lcd1_ch0_clk, CLK_LCD1_CH0, "lcd1_ch0", lcd_ch0_parents, /* id, name, parents */ 0x11C, /* offset */ 0, 0, 1, AW_CLK_FACTOR_FIXED, /* n factor (fake) */ 0, 0, 1, AW_CLK_FACTOR_FIXED, /* m factor (fake )*/ 24, 3, /* mux */ 31, /* gate */ AW_CLK_HAS_MUX | AW_CLK_HAS_GATE); /* flags */ static const char *lcd_ch1_parents[] = {"pll_video0", "pll_video1", "pll_video0-2x", "pll_video1-2x"}; NM_CLK(lcd0_ch1_clk, CLK_LCD0_CH1, "lcd0_ch1", lcd_ch1_parents, /* id, name, parents */ 0x12C, /* offset */ 0, 0, 1, AW_CLK_FACTOR_FIXED, /* n factor (fake) */ 0, 4, 0, 0, /* m factor */ 24, 3, /* mux */ 31, /* gate */ AW_CLK_HAS_MUX | AW_CLK_HAS_GATE); /* flags */ NM_CLK(lcd1_ch1_clk, CLK_LCD1_CH1, "lcd1_ch1", lcd_ch1_parents, /* id, name, parents */ 0x130, /* offset */ 0, 0, 1, AW_CLK_FACTOR_FIXED, /* n factor (fake) */ 0, 4, 0, 0, /* m factor */ 24, 3, /* mux */ 31, /* gate */ AW_CLK_HAS_MUX | AW_CLK_HAS_GATE); /* flags */ /* CSI0 0x134 Need Mux table */ /* CSI1 0x138 Need Mux table */ static const char *ve_parents[] = {"pll_ve"}; NM_CLK(ve_clk, CLK_VE, "ve", ve_parents, /* id, name, parents */ 0x13C, /* offset */ 16, 3, 0, 0, /* n factor */ 0, 0, 1, AW_CLK_FACTOR_FIXED, /* m factor (fake) */ 0, 0, /* mux */ 31, /* gate */ AW_CLK_HAS_GATE); /* flags */ NM_CLK(hdmi_clk, CLK_HDMI, "hdmi", lcd_ch1_parents, /* id, name, parents */ 0x150, /* offset */ 0, 0, 1, AW_CLK_FACTOR_FIXED, /* n factor (fake) */ 0, 4, 0, 0, /* m factor */ 0, 0, /* mux */ 31, /* gate */ AW_CLK_HAS_GATE); /* flags */ static const char *mbus_parents[] = {"osc24M", "pll_periph", "pll_ddr"}; NM_CLK(mbus0_clk, CLK_MBUS0, "mbus0", mbus_parents, /* id, name, parents */ 0x15C, /* offset */ 16, 2, 0, 0, /* n factor */ 0, 4, 0, 0, /* m factor */ 24, 2, /* mux */ 31, /* gate */ AW_CLK_HAS_MUX | AW_CLK_HAS_GATE); /* flags */ NM_CLK(mbus1_clk, CLK_MBUS1, "mbus1", mbus_parents, /* id, name, parents */ 0x160, /* offset */ 16, 2, 0, 0, /* n factor */ 0, 4, 0, 0, /* m factor */ 24, 2, /* mux */ 31, /* gate */ AW_CLK_HAS_MUX | AW_CLK_HAS_GATE); /* flags */ static const char *mipi_parents[] = {"pll_video0", "pll_video1", "pll_video0-2x", "pll_video1-2x"}; NM_CLK(mipi_dsi_clk, CLK_MIPI_DSI, "mipi_dsi", mipi_parents, /* id, name, parents */ 0x168, /* offset */ 0, 0, 1, AW_CLK_FACTOR_FIXED, /* n factor (fake) */ 16, 4, 0, 0, /* m factor */ 24, 2, /* mux */ 31, /* gate */ AW_CLK_HAS_MUX | AW_CLK_HAS_GATE); /* flags */ NM_CLK(mipi_dsi_dphy_clk, CLK_MIPI_DSI_DPHY, "mipi_dsi_dphy", mipi_parents, /* id, name, parents */ 0x168, /* offset */ 0, 0, 1, AW_CLK_FACTOR_FIXED, /* n factor (fake) */ 0, 4, 0, 0, /* m factor */ 8, 2, /* mux */ 15, /* gate */ AW_CLK_HAS_MUX | AW_CLK_HAS_GATE); /* flags */ NM_CLK(mipi_csi_dphy_clk, CLK_MIPI_CSI_DPHY, "mipi_csi_dphy", mipi_parents, /* id, name, parents */ 0x16C, /* offset */ 0, 0, 1, AW_CLK_FACTOR_FIXED, /* n factor (fake) */ 0, 4, 0, 0, /* m factor */ 8, 2, /* mux */ 15, /* gate */ AW_CLK_HAS_MUX | AW_CLK_HAS_GATE); /* flags */ static const char *iep_parents[] = {"pll_video0", "pll_video1", "pll_periph-2x", "pll_gpu", "pll9", "pll10"}; NM_CLK(iep_drc0_clk, CLK_IEP_DRC0, "iep_drc0", iep_parents, /* id, name, parents */ 0x180, /* offset */ 0, 0, 1, AW_CLK_FACTOR_FIXED, /* n factor (fake) */ 0, 4, 0, 0, /* m factor */ 24, 2, /* mux */ 31, /* gate */ AW_CLK_HAS_MUX | AW_CLK_HAS_GATE); /* flags */ NM_CLK(iep_drc1_clk, CLK_IEP_DRC1, "iep_drc1", iep_parents, /* id, name, parents */ 0x184, /* offset */ 0, 0, 1, AW_CLK_FACTOR_FIXED, /* n factor (fake) */ 0, 4, 0, 0, /* m factor */ 24, 2, /* mux */ 31, /* gate */ AW_CLK_HAS_MUX | AW_CLK_HAS_GATE); /* flags */ NM_CLK(iep_deu0_clk, CLK_IEP_DEU0, "iep_deu0", iep_parents, /* id, name, parents */ 0x188, /* offset */ 0, 0, 1, AW_CLK_FACTOR_FIXED, /* n factor (fake) */ 0, 4, 0, 0, /* m factor */ 24, 2, /* mux */ 31, /* gate */ AW_CLK_HAS_MUX | AW_CLK_HAS_GATE); /* flags */ NM_CLK(iep_deu1_clk, CLK_IEP_DEU1, "iep_deu1", iep_parents, /* id, name, parents */ 0x18C, /* offset */ 0, 0, 1, AW_CLK_FACTOR_FIXED, /* n factor (fake) */ 0, 4, 0, 0, /* m factor */ 24, 2, /* mux */ 31, /* gate */ AW_CLK_HAS_MUX | AW_CLK_HAS_GATE); /* flags */ static const char *gpu_parents[] = {"pll_gpu", "pll_periph-2x", "pll_video0", "pll_video1", "pll9", "pll10"}; PREDIV_CLK(gpu_core_clk, CLK_GPU_CORE, /* id */ "gpu_core", gpu_parents, /* name, parents */ 0x1A0, /* offset */ 24, 3, /* mux */ 0, 3, 0, 0, /* div */ 0, 0, 3, AW_CLK_FACTOR_HAS_COND | AW_CLK_FACTOR_FIXED, /* prediv */ 24, 2, 1); /* prediv condition */ PREDIV_CLK(gpu_memory_clk, CLK_GPU_MEMORY, /* id */ "gpu_memory", gpu_parents, /* name, parents */ 0x1A4, /* offset */ 24, 3, /* mux */ 0, 3, 0, 0, /* div */ 0, 0, 3, AW_CLK_FACTOR_HAS_COND | AW_CLK_FACTOR_FIXED, /* prediv */ 24, 2, 1); /* prediv condition */ PREDIV_CLK(gpu_hyd_clk, CLK_GPU_HYD, /* id */ "gpu_hyd", gpu_parents, /* name, parents */ 0x1A8, /* offset */ 24, 3, /* mux */ 0, 3, 0, 0, /* div */ 0, 0, 3, AW_CLK_FACTOR_HAS_COND | AW_CLK_FACTOR_FIXED, /* prediv */ 24, 2, 1); /* prediv condition */ /* ATS 0x1B0 */ /* Trace 0x1B4 */ static struct aw_ccung_clk a31_ccu_clks[] = { { .type = AW_CLK_NKMP, .clk.nkmp = &pll_cpu_clk}, { .type = AW_CLK_NKMP, .clk.nkmp = &pll_audio_clk}, { .type = AW_CLK_NKMP, .clk.nkmp = &pll_periph_clk}, { .type = AW_CLK_NKMP, .clk.nkmp = &pll_ddr_clk}, { .type = AW_CLK_NKMP, .clk.nkmp = &pll_mipi_clk}, - { .type = AW_CLK_NM, .clk.nm = &pll_video0_clk}, - { .type = AW_CLK_NM, .clk.nm = &pll_ve_clk}, - { .type = AW_CLK_NM, .clk.nm = &pll_video1_clk}, - { .type = AW_CLK_NM, .clk.nm = &pll_gpu_clk}, - { .type = AW_CLK_NM, .clk.nm = &pll9_clk}, - { .type = AW_CLK_NM, .clk.nm = &pll10_clk}, + { .type = AW_CLK_FRAC, .clk.frac = &pll_video0_clk}, + { .type = AW_CLK_FRAC, .clk.frac = &pll_ve_clk}, + { .type = AW_CLK_FRAC, .clk.frac = &pll_video1_clk}, + { .type = AW_CLK_FRAC, .clk.frac = &pll_gpu_clk}, + { .type = AW_CLK_FRAC, .clk.frac = &pll9_clk}, + { .type = AW_CLK_FRAC, .clk.frac = &pll10_clk}, { .type = AW_CLK_NM, .clk.nm = &apb2_clk}, { .type = AW_CLK_NM, .clk.nm = &nand0_clk}, { .type = AW_CLK_NM, .clk.nm = &nand1_clk}, { .type = AW_CLK_NM, .clk.nm = &mmc0_clk}, { .type = AW_CLK_NM, .clk.nm = &mmc1_clk}, { .type = AW_CLK_NM, .clk.nm = &mmc2_clk}, { .type = AW_CLK_NM, .clk.nm = &mmc3_clk}, { .type = AW_CLK_NM, .clk.nm = &ts_clk}, { .type = AW_CLK_NM, .clk.nm = &ss_clk}, { .type = AW_CLK_NM, .clk.nm = &spi0_clk}, { .type = AW_CLK_NM, .clk.nm = &spi1_clk}, { .type = AW_CLK_NM, .clk.nm = &spi2_clk}, { .type = AW_CLK_NM, .clk.nm = &spi3_clk}, { .type = AW_CLK_NM, .clk.nm = &mdfs_clk}, { .type = AW_CLK_NM, .clk.nm = &sdram0_clk}, { .type = AW_CLK_NM, .clk.nm = &sdram1_clk}, { .type = AW_CLK_NM, .clk.nm = &be0_clk}, { .type = AW_CLK_NM, .clk.nm = &be1_clk}, { .type = AW_CLK_NM, .clk.nm = &fe0_clk}, { .type = AW_CLK_NM, .clk.nm = &fe1_clk}, { .type = AW_CLK_NM, .clk.nm = &mp_clk}, { .type = AW_CLK_NM, .clk.nm = &lcd0_ch0_clk}, { .type = AW_CLK_NM, .clk.nm = &lcd1_ch0_clk}, { .type = AW_CLK_NM, .clk.nm = &lcd0_ch1_clk}, { .type = AW_CLK_NM, .clk.nm = &lcd1_ch1_clk}, { .type = AW_CLK_NM, .clk.nm = &ve_clk}, { .type = AW_CLK_NM, .clk.nm = &hdmi_clk}, { .type = AW_CLK_NM, .clk.nm = &mbus0_clk}, { .type = AW_CLK_NM, .clk.nm = &mbus1_clk}, { .type = AW_CLK_NM, .clk.nm = &mipi_dsi_clk}, { .type = AW_CLK_NM, .clk.nm = &mipi_dsi_dphy_clk}, { .type = AW_CLK_NM, .clk.nm = &mipi_csi_dphy_clk}, { .type = AW_CLK_NM, .clk.nm = &iep_drc0_clk}, { .type = AW_CLK_NM, .clk.nm = &iep_drc1_clk}, { .type = AW_CLK_NM, .clk.nm = &iep_deu0_clk}, { .type = AW_CLK_NM, .clk.nm = &iep_deu1_clk}, { .type = AW_CLK_PREDIV_MUX, .clk.prediv_mux = &ahb1_clk}, { .type = AW_CLK_PREDIV_MUX, .clk.prediv_mux = &gpu_core_clk}, { .type = AW_CLK_PREDIV_MUX, .clk.prediv_mux = &gpu_memory_clk}, { .type = AW_CLK_PREDIV_MUX, .clk.prediv_mux = &gpu_hyd_clk}, { .type = AW_CLK_DIV, .clk.div = &axi_clk}, { .type = AW_CLK_DIV, .clk.div = &apb1_clk}, { .type = AW_CLK_MUX, .clk.mux = &cpu_clk}, { .type = AW_CLK_MUX, .clk.mux = &daudio0mux_clk}, { .type = AW_CLK_MUX, .clk.mux = &daudio1mux_clk}, { .type = AW_CLK_FIXED, .clk.fixed = &pll_audio_2x_clk}, { .type = AW_CLK_FIXED, .clk.fixed = &pll_audio_4x_clk}, { .type = AW_CLK_FIXED, .clk.fixed = &pll_audio_8x_clk}, { .type = AW_CLK_FIXED, .clk.fixed = &pll_video0_2x_clk}, { .type = AW_CLK_FIXED, .clk.fixed = &pll_periph_2x_clk}, { .type = AW_CLK_FIXED, .clk.fixed = &pll_video1_2x_clk}, }; static int ccu_a31_probe(device_t dev) { if (!ofw_bus_status_okay(dev)) return (ENXIO); if (!ofw_bus_is_compatible(dev, "allwinner,sun6i-a31-ccu")) return (ENXIO); device_set_desc(dev, "Allwinner A31 Clock Control Unit NG"); return (BUS_PROBE_DEFAULT); } static int ccu_a31_attach(device_t dev) { struct aw_ccung_softc *sc; sc = device_get_softc(dev); sc->resets = a31_ccu_resets; sc->nresets = nitems(a31_ccu_resets); sc->gates = a31_ccu_gates; sc->ngates = nitems(a31_ccu_gates); sc->clks = a31_ccu_clks; sc->nclks = nitems(a31_ccu_clks); return (aw_ccung_attach(dev)); } static device_method_t ccu_a31ng_methods[] = { /* Device interface */ DEVMETHOD(device_probe, ccu_a31_probe), DEVMETHOD(device_attach, ccu_a31_attach), DEVMETHOD_END }; static devclass_t ccu_a31ng_devclass; DEFINE_CLASS_1(ccu_a31ng, ccu_a31ng_driver, ccu_a31ng_methods, sizeof(struct aw_ccung_softc), aw_ccung_driver); EARLY_DRIVER_MODULE(ccu_a31ng, simplebus, ccu_a31ng_driver, ccu_a31ng_devclass, 0, 0, BUS_PASS_BUS + BUS_PASS_ORDER_LAST); Index: head/sys/arm/allwinner/clkng/ccu_a64.c =================================================================== --- head/sys/arm/allwinner/clkng/ccu_a64.c (revision 348180) +++ head/sys/arm/allwinner/clkng/ccu_a64.c (revision 348181) @@ -1,828 +1,830 @@ /*- * SPDX-License-Identifier: BSD-2-Clause-FreeBSD * * Copyright (c) 2017,2018 Emmanuel Vadot * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. * * $FreeBSD$ */ #include __FBSDID("$FreeBSD$"); #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include /* Non-exported clocks */ #define CLK_OSC_12M 0 #define CLK_PLL_CPUX 1 #define CLK_PLL_AUDIO_BASE 2 #define CLK_PLL_AUDIO 3 #define CLK_PLL_AUDIO_2X 4 #define CLK_PLL_AUDIO_4X 5 #define CLK_PLL_AUDIO_8X 6 #define CLK_PLL_VIDEO0 7 #define CLK_PLL_VIDEO0_2X 8 #define CLK_PLL_VE 9 #define CLK_PLL_DDR0 10 #define CLK_PLL_PERIPH0_2X 12 #define CLK_PLL_PERIPH1 13 #define CLK_PLL_PERIPH1_2X 14 #define CLK_PLL_VIDEO1 15 #define CLK_PLL_GPU 16 #define CLK_PLL_HSIC 18 #define CLK_PLL_DE 19 #define CLK_PLL_DDR1 20 #define CLK_CPUX 21 #define CLK_AXI 22 #define CLK_APB 23 #define CLK_AHB1 24 #define CLK_APB1 25 #define CLK_APB2 26 #define CLK_AHB2 27 #define CLK_DRAM 94 #define CLK_MBUS 112 static struct aw_ccung_reset a64_ccu_resets[] = { CCU_RESET(RST_USB_PHY0, 0x0cc, 0) CCU_RESET(RST_USB_PHY1, 0x0cc, 1) CCU_RESET(RST_USB_HSIC, 0x0cc, 2) CCU_RESET(RST_BUS_MIPI_DSI, 0x2c0, 1) CCU_RESET(RST_BUS_CE, 0x2c0, 5) CCU_RESET(RST_BUS_DMA, 0x2c0, 6) CCU_RESET(RST_BUS_MMC0, 0x2c0, 8) CCU_RESET(RST_BUS_MMC1, 0x2c0, 9) CCU_RESET(RST_BUS_MMC2, 0x2c0, 10) CCU_RESET(RST_BUS_NAND, 0x2c0, 13) CCU_RESET(RST_BUS_DRAM, 0x2c0, 14) CCU_RESET(RST_BUS_EMAC, 0x2c0, 17) CCU_RESET(RST_BUS_TS, 0x2c0, 18) CCU_RESET(RST_BUS_HSTIMER, 0x2c0, 19) CCU_RESET(RST_BUS_SPI0, 0x2c0, 20) CCU_RESET(RST_BUS_SPI1, 0x2c0, 21) CCU_RESET(RST_BUS_OTG, 0x2c0, 23) CCU_RESET(RST_BUS_EHCI0, 0x2c0, 24) CCU_RESET(RST_BUS_EHCI1, 0x2c0, 25) CCU_RESET(RST_BUS_OHCI0, 0x2c0, 28) CCU_RESET(RST_BUS_OHCI1, 0x2c0, 29) CCU_RESET(RST_BUS_VE, 0x2c4, 0) CCU_RESET(RST_BUS_TCON0, 0x2c4, 3) CCU_RESET(RST_BUS_TCON1, 0x2c4, 4) CCU_RESET(RST_BUS_DEINTERLACE, 0x2c4, 5) CCU_RESET(RST_BUS_CSI, 0x2c4, 8) CCU_RESET(RST_BUS_HDMI0, 0x2c4, 10) CCU_RESET(RST_BUS_HDMI1, 0x2c4, 11) CCU_RESET(RST_BUS_DE, 0x2c4, 12) CCU_RESET(RST_BUS_GPU, 0x2c4, 20) CCU_RESET(RST_BUS_MSGBOX, 0x2c4, 21) CCU_RESET(RST_BUS_SPINLOCK, 0x2c4, 22) CCU_RESET(RST_BUS_DBG, 0x2c4, 31) CCU_RESET(RST_BUS_LVDS, 0x2C8, 31) CCU_RESET(RST_BUS_CODEC, 0x2D0, 0) CCU_RESET(RST_BUS_SPDIF, 0x2D0, 1) CCU_RESET(RST_BUS_THS, 0x2D0, 8) CCU_RESET(RST_BUS_I2S0, 0x2D0, 12) CCU_RESET(RST_BUS_I2S1, 0x2D0, 13) CCU_RESET(RST_BUS_I2S2, 0x2D0, 14) CCU_RESET(RST_BUS_I2C0, 0x2D8, 0) CCU_RESET(RST_BUS_I2C1, 0x2D8, 1) CCU_RESET(RST_BUS_I2C2, 0x2D8, 2) CCU_RESET(RST_BUS_SCR, 0x2D8, 5) CCU_RESET(RST_BUS_UART0, 0x2D8, 16) CCU_RESET(RST_BUS_UART1, 0x2D8, 17) CCU_RESET(RST_BUS_UART2, 0x2D8, 18) CCU_RESET(RST_BUS_UART3, 0x2D8, 19) CCU_RESET(RST_BUS_UART4, 0x2D8, 20) }; static struct aw_ccung_gate a64_ccu_gates[] = { CCU_GATE(CLK_BUS_MIPI_DSI, "bus-mipi-dsi", "ahb1", 0x60, 1) CCU_GATE(CLK_BUS_CE, "bus-ce", "ahb1", 0x60, 5) CCU_GATE(CLK_BUS_DMA, "bus-dma", "ahb1", 0x60, 6) CCU_GATE(CLK_BUS_MMC0, "bus-mmc0", "ahb1", 0x60, 8) CCU_GATE(CLK_BUS_MMC1, "bus-mmc1", "ahb1", 0x60, 9) CCU_GATE(CLK_BUS_MMC2, "bus-mmc2", "ahb1", 0x60, 10) CCU_GATE(CLK_BUS_NAND, "bus-nand", "ahb1", 0x60, 13) CCU_GATE(CLK_BUS_DRAM, "bus-dram", "ahb1", 0x60, 14) CCU_GATE(CLK_BUS_EMAC, "bus-emac", "ahb2", 0x60, 16) CCU_GATE(CLK_BUS_TS, "bus-ts", "ahb1", 0x60, 18) CCU_GATE(CLK_BUS_HSTIMER, "bus-hstimer", "ahb1", 0x60, 19) CCU_GATE(CLK_BUS_SPI0, "bus-spi0", "ahb1", 0x60, 20) CCU_GATE(CLK_BUS_SPI1, "bus-spi1", "ahb1", 0x60, 21) CCU_GATE(CLK_BUS_OTG, "bus-otg", "ahb1", 0x60, 23) CCU_GATE(CLK_BUS_EHCI0, "bus-ehci0", "ahb1", 0x60, 24) CCU_GATE(CLK_BUS_EHCI1, "bus-ehci1", "ahb2", 0x60, 25) CCU_GATE(CLK_BUS_OHCI0, "bus-ohci0", "ahb1", 0x60, 28) CCU_GATE(CLK_BUS_OHCI1, "bus-ohci1", "ahb2", 0x60, 29) CCU_GATE(CLK_BUS_VE, "bus-ve", "ahb1", 0x64, 0) CCU_GATE(CLK_BUS_TCON0, "bus-tcon0", "ahb1", 0x64, 3) CCU_GATE(CLK_BUS_TCON1, "bus-tcon1", "ahb1", 0x64, 4) CCU_GATE(CLK_BUS_DEINTERLACE, "bus-deinterlace", "ahb1", 0x64, 5) CCU_GATE(CLK_BUS_CSI, "bus-csi", "ahb1", 0x64, 8) CCU_GATE(CLK_BUS_HDMI, "bus-hdmi", "ahb1", 0x64, 11) CCU_GATE(CLK_BUS_DE, "bus-de", "ahb1", 0x64, 12) CCU_GATE(CLK_BUS_GPU, "bus-gpu", "ahb1", 0x64, 20) CCU_GATE(CLK_BUS_MSGBOX, "bus-msgbox", "ahb1", 0x64, 21) CCU_GATE(CLK_BUS_SPINLOCK, "bus-spinlock", "ahb1", 0x64, 22) CCU_GATE(CLK_BUS_CODEC, "bus-codec", "apb1", 0x68, 0) CCU_GATE(CLK_BUS_SPDIF, "bus-spdif", "apb1", 0x68, 1) CCU_GATE(CLK_BUS_PIO, "bus-pio", "apb1", 0x68, 5) CCU_GATE(CLK_BUS_THS, "bus-ths", "apb1", 0x68, 8) CCU_GATE(CLK_BUS_I2S0, "bus-i2s0", "apb1", 0x68, 12) CCU_GATE(CLK_BUS_I2S1, "bus-i2s1", "apb1", 0x68, 13) CCU_GATE(CLK_BUS_I2S2, "bus-i2s2", "apb1", 0x68, 14) CCU_GATE(CLK_BUS_I2C0, "bus-i2c0", "apb2", 0x6C, 0) CCU_GATE(CLK_BUS_I2C1, "bus-i2c1", "apb2", 0x6C, 1) CCU_GATE(CLK_BUS_I2C2, "bus-i2c2", "apb2", 0x6C, 2) CCU_GATE(CLK_BUS_SCR, "bus-src", "apb2", 0x6C, 5) CCU_GATE(CLK_BUS_UART0, "bus-uart0", "apb2", 0x6C, 16) CCU_GATE(CLK_BUS_UART1, "bus-uart1", "apb2", 0x6C, 17) CCU_GATE(CLK_BUS_UART2, "bus-uart2", "apb2", 0x6C, 18) CCU_GATE(CLK_BUS_UART3, "bus-uart3", "apb2", 0x6C, 19) CCU_GATE(CLK_BUS_UART4, "bus-uart4", "apb2", 0x6C, 20) CCU_GATE(CLK_BUS_DBG, "bus-dbg", "ahb1", 0x70, 7) CCU_GATE(CLK_THS, "ths", "thsdiv", 0x74, 31) CCU_GATE(CLK_USB_PHY0, "usb-phy0", "osc24M", 0xcc, 8) CCU_GATE(CLK_USB_PHY1, "usb-phy1", "osc24M", 0xcc, 9) CCU_GATE(CLK_USB_HSIC, "usb-hsic", "pll_hsic", 0xcc, 10) CCU_GATE(CLK_USB_HSIC_12M, "usb-hsic-12M", "osc12M", 0xcc, 11) CCU_GATE(CLK_USB_OHCI0, "usb-ohci0", "osc12M", 0xcc, 16) CCU_GATE(CLK_USB_OHCI1, "usb-ohci1", "usb-ohci0", 0xcc, 17) CCU_GATE(CLK_DRAM_VE, "dram-ve", "dram", 0x100, 0) CCU_GATE(CLK_DRAM_CSI, "dram-csi", "dram", 0x100, 1) CCU_GATE(CLK_DRAM_DEINTERLACE, "dram-deinterlace", "dram", 0x100, 2) CCU_GATE(CLK_DRAM_TS, "dram-ts", "dram", 0x100, 3) CCU_GATE(CLK_CSI_MISC, "csi-misc", "osc24M", 0x130, 31) CCU_GATE(CLK_AC_DIG_4X, "ac-dig-4x", "pll_audio-4x", 0x140, 30) CCU_GATE(CLK_AC_DIG, "ac-dig", "pll_audio", 0x140, 31) CCU_GATE(CLK_AVS, "avs", "osc24M", 0x144, 31) CCU_GATE(CLK_HDMI_DDC, "hdmi-ddc", "osc24M", 0x154, 31) }; static const char *osc12m_parents[] = {"osc24M"}; FIXED_CLK(osc12m_clk, CLK_OSC_12M, /* id */ "osc12M", /* name */ osc12m_parents, /* parent */ 0, /* freq */ 1, /* mult */ 2, /* div */ 0); /* flags */ static const char *pll_cpux_parents[] = {"osc24M"}; NKMP_CLK(pll_cpux_clk, CLK_PLL_CPUX, /* id */ "pll_cpux", pll_cpux_parents, /* name, parents */ 0x00, /* offset */ 8, 5, 0, 0, /* n factor */ 4, 2, 0, 0, /* k factor */ 0, 2, 0, 0, /* m factor */ 16, 2, 0, AW_CLK_FACTOR_POWER_OF_TWO, /* p factor */ 31, /* gate */ 28, 1000, /* lock */ AW_CLK_HAS_GATE | AW_CLK_HAS_LOCK | AW_CLK_SCALE_CHANGE); /* flags */ static const char *pll_audio_parents[] = {"osc24M"}; NKMP_CLK(pll_audio_clk, CLK_PLL_AUDIO, /* id */ "pll_audio", pll_audio_parents, /* name, parents */ 0x08, /* offset */ 8, 7, 0, 0, /* n factor */ 0, 0, 1, AW_CLK_FACTOR_FIXED, /* k factor (fake) */ 0, 5, 0, 0, /* m factor */ 16, 4, 0, 0, /* p factor */ 31, /* gate */ 28, 1000, /* lock */ AW_CLK_HAS_GATE | AW_CLK_HAS_LOCK); /* flags */ static const char *pll_audio_mult_parents[] = {"pll_audio"}; FIXED_CLK(pll_audio_2x_clk, CLK_PLL_AUDIO_2X, /* id */ "pll_audio-2x", /* name */ pll_audio_mult_parents, /* parent */ 0, /* freq */ 2, /* mult */ 1, /* div */ 0); /* flags */ FIXED_CLK(pll_audio_4x_clk, CLK_PLL_AUDIO_4X, /* id */ "pll_audio-4x", /* name */ pll_audio_mult_parents, /* parent */ 0, /* freq */ 4, /* mult */ 1, /* div */ 0); /* flags */ FIXED_CLK(pll_audio_8x_clk, CLK_PLL_AUDIO_8X, /* id */ "pll_audio-8x", /* name */ pll_audio_mult_parents, /* parent */ 0, /* freq */ 8, /* mult */ 1, /* div */ 0); /* flags */ static const char *pll_video0_parents[] = {"osc24M"}; -NM_CLK_WITH_FRAC(pll_video0_clk, +FRAC_CLK(pll_video0_clk, CLK_PLL_VIDEO0, /* id */ "pll_video0", pll_video0_parents, /* name, parents */ 0x10, /* offset */ 8, 7, 0, 0, /* n factor */ 0, 4, 0, 0, /* m factor */ 31, 28, 1000, /* gate, lock, lock retries */ AW_CLK_HAS_LOCK, /* flags */ 270000000, 297000000, /* freq0, freq1 */ 24, 25); /* mode sel, freq sel */ static const char *pll_video0_2x_parents[] = {"pll_video0"}; FIXED_CLK(pll_video0_2x_clk, CLK_PLL_VIDEO0_2X, /* id */ "pll_video0-2x", /* name */ pll_video0_2x_parents, /* parent */ 0, /* freq */ 2, /* mult */ 1, /* div */ 0); /* flags */ static const char *pll_ve_parents[] = {"osc24M"}; -NM_CLK_WITH_FRAC(pll_ve_clk, +FRAC_CLK(pll_ve_clk, CLK_PLL_VE, /* id */ "pll_ve", pll_ve_parents, /* name, parents */ 0x18, /* offset */ 8, 7, 0, 0, /* n factor */ 0, 4, 0, 0, /* m factor */ 31, 28, 1000, /* gate, lock, lock retries */ AW_CLK_HAS_LOCK, /* flags */ 270000000, 297000000, /* freq0, freq1 */ 24, 25); /* mode sel, freq sel */ static const char *pll_ddr0_parents[] = {"osc24M"}; NKMP_CLK_WITH_UPDATE(pll_ddr0_clk, CLK_PLL_DDR0, /* id */ "pll_ddr0", pll_ddr0_parents, /* name, parents */ 0x20, /* offset */ 8, 5, 0, 0, /* n factor */ 4, 2, 0, 0, /* k factor */ 0, 2, 0, 0, /* m factor */ 0, 0, 1, AW_CLK_FACTOR_FIXED, /* p factor (fake) */ 31, /* gate */ 28, 1000, /* lock */ 20, /* update */ AW_CLK_HAS_GATE | AW_CLK_HAS_LOCK); /* flags */ static const char *pll_periph0_2x_parents[] = {"osc24M"}; static const char *pll_periph0_parents[] = {"pll_periph0_2x"}; NKMP_CLK(pll_periph0_2x_clk, CLK_PLL_PERIPH0_2X, /* id */ "pll_periph0_2x", pll_periph0_2x_parents, /* name, parents */ 0x28, /* offset */ 8, 5, 0, 0, /* n factor */ 4, 2, 0, 0, /* k factor */ 0, 0, 2, AW_CLK_FACTOR_FIXED, /* m factor (fake) */ 0, 0, 1, AW_CLK_FACTOR_FIXED, /* p factor (fake) */ 31, /* gate */ 28, 1000, /* lock */ AW_CLK_HAS_GATE | AW_CLK_HAS_LOCK); /* flags */ FIXED_CLK(pll_periph0_clk, CLK_PLL_PERIPH0, /* id */ "pll_periph0", /* name */ pll_periph0_parents, /* parent */ 0, /* freq */ 1, /* mult */ 2, /* div */ 0); /* flags */ static const char *pll_periph1_2x_parents[] = {"osc24M"}; static const char *pll_periph1_parents[] = {"pll_periph1_2x"}; NKMP_CLK(pll_periph1_2x_clk, CLK_PLL_PERIPH1_2X, /* id */ "pll_periph1_2x", pll_periph1_2x_parents, /* name, parents */ 0x2C, /* offset */ 8, 5, 0, 0, /* n factor */ 4, 2, 0, 0, /* k factor */ 0, 0, 2, AW_CLK_FACTOR_FIXED, /* m factor (fake) */ 0, 0, 1, AW_CLK_FACTOR_FIXED, /* p factor (fake) */ 31, /* gate */ 28, 1000, /* lock */ AW_CLK_HAS_GATE | AW_CLK_HAS_LOCK); /* flags */ FIXED_CLK(pll_periph1_clk, CLK_PLL_PERIPH1, /* id */ "pll_periph1", /* name */ pll_periph1_parents, /* parent */ 0, /* freq */ 1, /* mult */ 2, /* div */ 0); /* flags */ static const char *pll_video1_parents[] = {"osc24M"}; -NM_CLK_WITH_FRAC(pll_video1_clk, +FRAC_CLK(pll_video1_clk, CLK_PLL_VIDEO1, /* id */ "pll_video1", pll_video1_parents, /* name, parents */ 0x30, /* offset */ 8, 7, 0, 0, /* n factor */ 0, 4, 0, 0, /* m factor */ 31, 28, 1000, /* gate, lock, lock retries */ AW_CLK_HAS_LOCK, /* flags */ 270000000, 297000000, /* freq0, freq1 */ 24, 25); /* mode sel, freq sel */ static const char *pll_gpu_parents[] = {"osc24M"}; -NM_CLK_WITH_FRAC(pll_gpu_clk, +FRAC_CLK(pll_gpu_clk, CLK_PLL_GPU, /* id */ "pll_gpu", pll_gpu_parents, /* name, parents */ 0x38, /* offset */ 8, 7, 0, 0, /* n factor */ 0, 4, 0, 0, /* m factor */ 31, 28, 1000, /* gate, lock, lock retries */ AW_CLK_HAS_LOCK, /* flags */ 270000000, 297000000, /* freq0, freq1 */ 24, 25); /* mode sel, freq sel */ /* PLL MIPI is missing */ static const char *pll_hsic_parents[] = {"osc24M"}; -NM_CLK_WITH_FRAC(pll_hsic_clk, +FRAC_CLK(pll_hsic_clk, CLK_PLL_HSIC, /* id */ "pll_hsic", pll_hsic_parents, /* name, parents */ 0x44, /* offset */ 8, 7, 0, 0, /* n factor */ 0, 4, 0, 0, /* m factor */ 31, 28, 1000, /* gate, lock, lock retries */ AW_CLK_HAS_LOCK, /* flags */ 270000000, 297000000, /* freq0, freq1 */ 24, 25); /* mode sel, freq sel */ static const char *pll_de_parents[] = {"osc24M"}; -NM_CLK_WITH_FRAC(pll_de_clk, +FRAC_CLK(pll_de_clk, CLK_PLL_DE, /* id */ "pll_de", pll_de_parents, /* name, parents */ 0x48, /* offset */ 8, 7, 0, 0, /* n factor */ 0, 4, 0, 0, /* m factor */ 31, 28, 1000, /* gate, lock, lock retries */ AW_CLK_HAS_LOCK, /* flags */ 270000000, 297000000, /* freq0, freq1 */ 24, 25); /* mode sel, freq sel */ static const char *pll_ddr1_parents[] = {"osc24M"}; NKMP_CLK_WITH_UPDATE(pll_ddr1_clk, CLK_PLL_DDR1, /* id */ "pll_ddr1", pll_ddr1_parents, /* name, parents */ 0x4C, /* offset */ 8, 7, 0, 0, /* n factor */ 0, 0, 1, AW_CLK_FACTOR_FIXED, /* k factor (fake) */ 0, 2, 0, 0, /* m factor */ 0, 0, 1, AW_CLK_FACTOR_FIXED, /* p factor (fake) */ 31, /* gate */ 28, 1000, /* lock */ 20, /* update */ AW_CLK_HAS_GATE | AW_CLK_HAS_LOCK); /* flags */ static const char *cpux_parents[] = {"osc32k", "osc24M", "pll_cpux"}; MUX_CLK(cpux_clk, CLK_CPUX, /* id */ "cpux", cpux_parents, /* name, parents */ 0x50, 16, 2); /* offset, shift, width */ static const char *axi_parents[] = {"cpux"}; DIV_CLK(axi_clk, CLK_AXI, /* id */ "axi", axi_parents, /* name, parents */ 0x50, /* offset */ 0, 2, /* shift, width */ 0, NULL); /* flags, div table */ static const char *apb_parents[] = {"cpux"}; DIV_CLK(apb_clk, CLK_APB, /* id */ "apb", apb_parents, /* name, parents */ 0x50, /* offset */ 8, 2, /* shift, width */ 0, NULL); /* flags, div table */ static const char *ahb1_parents[] = {"osc32k", "osc24M", "axi", "pll_periph0"}; PREDIV_CLK(ahb1_clk, CLK_AHB1, /* id */ "ahb1", ahb1_parents, /* name, parents */ 0x54, /* offset */ 12, 2, /* mux */ 4, 2, 0, AW_CLK_FACTOR_POWER_OF_TWO, /* div */ 6, 2, 0, AW_CLK_FACTOR_HAS_COND, /* prediv */ 12, 2, 3); /* prediv condition */ static const char *apb1_parents[] = {"ahb1"}; static struct clk_div_table apb1_div_table[] = { { .value = 0, .divider = 2, }, { .value = 1, .divider = 2, }, { .value = 2, .divider = 4, }, { .value = 3, .divider = 8, }, { }, }; DIV_CLK(apb1_clk, CLK_APB1, /* id */ "apb1", apb1_parents, /* name, parents */ 0x54, /* offset */ 8, 2, /* shift, width */ CLK_DIV_WITH_TABLE, /* flags */ apb1_div_table); /* div table */ static const char *apb2_parents[] = {"osc32k", "osc24M", "pll_periph0_2x", "pll_periph0_2x"}; NM_CLK(apb2_clk, CLK_APB2, /* id */ "apb2", apb2_parents, /* name, parents */ 0x58, /* offset */ 16, 2, 0, AW_CLK_FACTOR_POWER_OF_TWO, /* n factor */ 0, 5, 0, 0, /* m factor */ 24, 2, /* mux */ 0, /* gate */ AW_CLK_HAS_MUX); static const char *ahb2_parents[] = {"ahb1", "pll_periph0"}; PREDIV_CLK(ahb2_clk, CLK_AHB2, /* id */ "ahb2", ahb2_parents, /* name, parents */ 0x5c, /* offset */ 0, 2, /* mux */ 0, 0, 1, AW_CLK_FACTOR_FIXED, /* div */ 0, 0, 2, AW_CLK_FACTOR_HAS_COND | AW_CLK_FACTOR_FIXED, /* prediv */ 0, 2, 1); /* prediv condition */ static const char *ths_parents[] = {"osc24M"}; static struct clk_div_table ths_div_table[] = { { .value = 0, .divider = 1, }, { .value = 1, .divider = 2, }, { .value = 2, .divider = 4, }, { .value = 3, .divider = 6, }, { }, }; DIV_CLK(ths_clk, 0, /* id */ "thsdiv", ths_parents, /* name, parents */ 0x74, /* offset */ 0, 2, /* div shift, div width */ CLK_DIV_WITH_TABLE, /* flags */ ths_div_table); /* div table */ static const char *mod_parents[] = {"osc24M", "pll_periph0_2x", "pll_periph1_2x"}; NM_CLK(nand_clk, CLK_NAND, "nand", mod_parents, /* id, name, parents */ 0x80, /* offset */ 16, 2, 0, AW_CLK_FACTOR_POWER_OF_TWO, /* n factor */ 0, 4, 0, 0, /* m factor */ 24, 2, /* mux */ 31, /* gate */ AW_CLK_HAS_GATE | AW_CLK_HAS_MUX); /* flags */ NM_CLK(mmc0_clk, CLK_MMC0, "mmc0", mod_parents, /* id, name, parents */ 0x88, /* offset */ 16, 2, 0, AW_CLK_FACTOR_POWER_OF_TWO, /* n factor */ 0, 4, 0, 0, /* m factor */ 24, 2, /* mux */ 31, /* gate */ AW_CLK_HAS_GATE | AW_CLK_HAS_MUX | AW_CLK_REPARENT); /* flags */ NM_CLK(mmc1_clk, CLK_MMC1, "mmc1", mod_parents, /* id, name, parents */ 0x8c, /* offset */ 16, 2, 0, AW_CLK_FACTOR_POWER_OF_TWO, /* n factor */ 0, 4, 0, 0, /* m factor */ 24, 2, /* mux */ 31, /* gate */ AW_CLK_HAS_GATE | AW_CLK_HAS_MUX | AW_CLK_REPARENT); /* flags */ NM_CLK(mmc2_clk, CLK_MMC2, "mmc2", mod_parents, /* id, name, parents */ 0x90, /* offset */ 16, 2, 0, AW_CLK_FACTOR_POWER_OF_TWO, /* n factor */ 0, 4, 0, 0, /* m factor */ 24, 2, /* mux */ 31, /* gate */ AW_CLK_HAS_GATE | AW_CLK_HAS_MUX | AW_CLK_REPARENT); /* flags */ static const char *ts_parents[] = {"osc24M", "pll_periph0"}; NM_CLK(ts_clk, CLK_TS, "ts", ts_parents, /* id, name, parents */ 0x98, /* offset */ 16, 2, 0, AW_CLK_FACTOR_POWER_OF_TWO, /* n factor */ 0, 4, 0, 0, /* m factor */ 24, 2, /* mux */ 31, /* gate */ AW_CLK_HAS_GATE | AW_CLK_HAS_MUX); /* flags */ NM_CLK(ce_clk, CLK_CE, "ce", mod_parents, /* id, name, parents */ 0x9C, /* offset */ 16, 2, 0, AW_CLK_FACTOR_POWER_OF_TWO, /* n factor */ 0, 4, 0, 0, /* m factor */ 24, 2, /* mux */ 31, /* gate */ AW_CLK_HAS_GATE | AW_CLK_HAS_MUX); /* flags */ NM_CLK(spi0_clk, CLK_SPI0, "spi0", mod_parents, /* id, name, parents */ 0xA0, /* offset */ 16, 2, 0, AW_CLK_FACTOR_POWER_OF_TWO, /* n factor */ 0, 4, 0, 0, /* m factor */ 24, 2, /* mux */ 31, /* gate */ AW_CLK_HAS_GATE | AW_CLK_HAS_MUX | AW_CLK_REPARENT); /* flags */ NM_CLK(spi1_clk, CLK_SPI1, "spi1", mod_parents, /* id, name, parents */ 0xA4, /* offset */ 16, 2, 0, AW_CLK_FACTOR_POWER_OF_TWO, /* n factor */ 0, 4, 0, 0, /* m factor */ 24, 2, /* mux */ 31, /* gate */ AW_CLK_HAS_GATE | AW_CLK_HAS_MUX | AW_CLK_REPARENT); /* flags */ static const char *i2s_parents[] = {"pll_audio-8x", "pll_audio-4x", "pll_audio-2x", "pll_audio"}; MUX_CLK(i2s0mux_clk, 0, "i2s0mux", i2s_parents, /* id, name, parents */ 0xb0, 16, 2); /* offset, mux shift, mux width */ MUX_CLK(i2s1mux_clk, 0, "i2s1mux", i2s_parents, /* id, name, parents */ 0xb4, 16, 2); /* offset, mux shift, mux width */ MUX_CLK(i2s2mux_clk, 0, "i2s2mux", i2s_parents, /* id, name, parents */ 0xb8, 16, 2); /* offset, mux shift, mux width */ static const char *spdif_parents[] = {"pll_audio"}; NM_CLK(spdif_clk, CLK_SPDIF, "spdif", spdif_parents, /* id, name, parents */ 0xC0, /* offset */ 0, 0, 1, AW_CLK_FACTOR_FIXED, /* n factor (fake); */ 0, 4, 0, 0, /* m factor */ 0, 0, /* mux */ 31, /* gate */ AW_CLK_HAS_GATE); /* flags */ /* USBPHY clk sel */ /* DRAM needs update bit */ static const char *dram_parents[] = {"pll_ddr0", "pll_ddr1"}; NM_CLK(dram_clk, CLK_DRAM, "dram", dram_parents, /* id, name, parents */ 0xF4, /* offset */ 0, 0, 1, AW_CLK_FACTOR_FIXED, /* n factor (fake) */ 0, 2, 0, 0, /* m factor */ 20, 2, /* mux */ 0, /* gate */ AW_CLK_HAS_MUX); /* flags */ static const char *de_parents[] = {"pll_periph0_2x", "pll_de"}; NM_CLK(de_clk, CLK_DE, "de", de_parents, /* id, name, parents */ 0x104, /* offset */ 0, 0, 1, AW_CLK_FACTOR_FIXED, /* n factor (fake) */ 0, 4, 0, 0, /* m factor */ 24, 2, /* mux */ 31, /* gate */ AW_CLK_HAS_MUX | AW_CLK_HAS_GATE); /* flags */ /* TCON0/1 Needs mux table */ static const char *tcon1_parents[] = {"pll_video0", "pll_video0", "pll_video1"}; NM_CLK(tcon1_clk, CLK_TCON1, "tcon1", tcon1_parents, 0x11C, 0, 0, 1, AW_CLK_FACTOR_FIXED, 0, 4, 0, 0, 24, 2, 31, AW_CLK_HAS_MUX | AW_CLK_HAS_GATE); static const char *deinterlace_parents[] = {"pll_periph0", "pll_periph1"}; NM_CLK(deinterlace_clk, CLK_DEINTERLACE, "deinterlace", deinterlace_parents, /* id, name, parents */ 0x124, /* offset */ 0, 0, 1, AW_CLK_FACTOR_FIXED, /* n factor (fake) */ 0, 4, 0, 0, /* m factor */ 24, 2, /* mux */ 31, /* gate */ AW_CLK_HAS_MUX | AW_CLK_HAS_GATE); /* flags */ static const char *csi_sclk_parents[] = {"pll_periph0", "pll_periph1"}; NM_CLK(csi_sclk_clk, CLK_CSI_SCLK, "csi-sclk", csi_sclk_parents, /* id, name, parents */ 0x134, /* offset */ 0, 0, 1, AW_CLK_FACTOR_FIXED, /* n factor (fake) */ 16, 4, 0, 0, /* m factor */ 24, 2, /* mux */ 31, /* gate */ AW_CLK_HAS_MUX | AW_CLK_HAS_GATE); /* flags */ static const char *csi_mclk_parents[] = {"osc24M", "pll_video0", "pll_periph1"}; NM_CLK(csi_mclk_clk, CLK_CSI_MCLK, "csi-mclk", csi_mclk_parents, /* id, name, parents */ 0x134, /* offset */ 0, 0, 1, AW_CLK_FACTOR_FIXED, /* n factor (fake) */ 0, 4, 0, 0, /* m factor */ 8, 2, /* mux */ 15, /* gate */ AW_CLK_HAS_MUX | AW_CLK_HAS_GATE); /* flags */ static const char *ve_parents[] = {"pll_ve"}; NM_CLK(ve_clk, CLK_VE, "ve", ve_parents, /* id, name, parents */ 0x13C, /* offset */ 16, 3, 0, 0, /* n factor */ 0, 0, 1, AW_CLK_FACTOR_FIXED, /* m factor (fake) */ 0, 0, /* mux */ 31, /* gate */ AW_CLK_HAS_GATE); /* flags */ static const char *hdmi_parents[] = {"pll_video0"}; NM_CLK(hdmi_clk, CLK_HDMI, "hdmi", hdmi_parents, /* id, name, parents */ 0x150, /* offset */ 0, 0, 1, AW_CLK_FACTOR_FIXED, /* n factor (fake) */ 0, 4, 0, 0, /* m factor */ 24, 2, /* mux */ 31, /* gate */ AW_CLK_HAS_MUX | AW_CLK_HAS_GATE); /* flags */ static const char *mbus_parents[] = {"osc24M", "pll_periph0_2x", "pll_ddr0"}; NM_CLK(mbus_clk, CLK_MBUS, "mbus", mbus_parents, /* id, name, parents */ 0x15C, /* offset */ 0, 0, 1, AW_CLK_FACTOR_FIXED, /* n factor (fake) */ 0, 3, 0, 0, /* m factor */ 24, 2, /* mux */ 31, /* gate */ AW_CLK_HAS_MUX | AW_CLK_HAS_GATE); /* flags */ static const char *gpu_parents[] = {"pll_gpu"}; NM_CLK(gpu_clk, CLK_GPU, "gpu", gpu_parents, /* id, name, parents */ 0x1A0, /* offset */ 0, 2, 0, 0, /* n factor */ 0, 0, 1, AW_CLK_FACTOR_FIXED, /* m factor (fake) */ 0, 0, /* mux */ 31, /* gate */ AW_CLK_HAS_GATE); /* flags */ static struct aw_ccung_clk a64_ccu_clks[] = { { .type = AW_CLK_NKMP, .clk.nkmp = &pll_cpux_clk}, { .type = AW_CLK_NKMP, .clk.nkmp = &pll_audio_clk}, + { .type = AW_CLK_FRAC, .clk.frac = &pll_video0_clk}, + { .type = AW_CLK_FRAC, .clk.frac = &pll_ve_clk}, + { .type = AW_CLK_NKMP, .clk.nkmp = &pll_ddr0_clk}, { .type = AW_CLK_NKMP, .clk.nkmp = &pll_periph0_2x_clk}, { .type = AW_CLK_NKMP, .clk.nkmp = &pll_periph1_2x_clk}, - { .type = AW_CLK_NKMP, .clk.nkmp = &pll_ddr0_clk}, + { .type = AW_CLK_FRAC, .clk.frac = &pll_video1_clk}, + { .type = AW_CLK_FRAC, .clk.frac = &pll_gpu_clk}, + /* PLL_MIPI */ + { .type = AW_CLK_FRAC, .clk.frac = &pll_hsic_clk}, + { .type = AW_CLK_FRAC, .clk.frac = &pll_de_clk}, { .type = AW_CLK_NKMP, .clk.nkmp = &pll_ddr1_clk}, - { .type = AW_CLK_NM, .clk.nm = &pll_video0_clk}, - { .type = AW_CLK_NM, .clk.nm = &pll_video1_clk}, - { .type = AW_CLK_NM, .clk.nm = &pll_ve_clk}, - { .type = AW_CLK_NM, .clk.nm = &pll_gpu_clk}, - { .type = AW_CLK_NM, .clk.nm = &pll_de_clk}, - { .type = AW_CLK_NM, .clk.nm = &pll_hsic_clk}, + { .type = AW_CLK_NM, .clk.nm = &apb2_clk}, { .type = AW_CLK_NM, .clk.nm = &nand_clk}, { .type = AW_CLK_NM, .clk.nm = &mmc0_clk}, { .type = AW_CLK_NM, .clk.nm = &mmc1_clk}, { .type = AW_CLK_NM, .clk.nm = &mmc2_clk}, { .type = AW_CLK_NM, .clk.nm = &ts_clk}, { .type = AW_CLK_NM, .clk.nm = &ce_clk}, { .type = AW_CLK_NM, .clk.nm = &spi0_clk}, { .type = AW_CLK_NM, .clk.nm = &spi1_clk}, { .type = AW_CLK_NM, .clk.nm = &spdif_clk}, { .type = AW_CLK_NM, .clk.nm = &dram_clk}, { .type = AW_CLK_NM, .clk.nm = &de_clk}, { .type = AW_CLK_NM, .clk.nm = &tcon1_clk}, { .type = AW_CLK_NM, .clk.nm = &deinterlace_clk}, { .type = AW_CLK_NM, .clk.nm = &csi_sclk_clk}, { .type = AW_CLK_NM, .clk.nm = &csi_mclk_clk}, { .type = AW_CLK_NM, .clk.nm = &ve_clk}, { .type = AW_CLK_NM, .clk.nm = &hdmi_clk}, { .type = AW_CLK_NM, .clk.nm = &mbus_clk}, { .type = AW_CLK_NM, .clk.nm = &gpu_clk}, { .type = AW_CLK_PREDIV_MUX, .clk.prediv_mux = &ahb1_clk}, { .type = AW_CLK_PREDIV_MUX, .clk.prediv_mux = &ahb2_clk}, { .type = AW_CLK_MUX, .clk.mux = &cpux_clk}, { .type = AW_CLK_MUX, .clk.mux = &i2s0mux_clk}, { .type = AW_CLK_MUX, .clk.mux = &i2s1mux_clk}, { .type = AW_CLK_MUX, .clk.mux = &i2s2mux_clk}, { .type = AW_CLK_DIV, .clk.div = &axi_clk}, { .type = AW_CLK_DIV, .clk.div = &apb1_clk}, { .type = AW_CLK_DIV, .clk.div = &apb_clk}, { .type = AW_CLK_DIV, .clk.div = &ths_clk}, { .type = AW_CLK_FIXED, .clk.fixed = &osc12m_clk}, { .type = AW_CLK_FIXED, .clk.fixed = &pll_periph0_clk}, { .type = AW_CLK_FIXED, .clk.fixed = &pll_periph1_clk}, { .type = AW_CLK_FIXED, .clk.fixed = &pll_audio_2x_clk}, { .type = AW_CLK_FIXED, .clk.fixed = &pll_audio_4x_clk}, { .type = AW_CLK_FIXED, .clk.fixed = &pll_audio_8x_clk}, { .type = AW_CLK_FIXED, .clk.fixed = &pll_video0_2x_clk}, }; static struct aw_clk_init a64_init_clks[] = { {"ahb1", "pll_periph0", 0, false}, {"ahb2", "pll_periph0", 0, false}, {"dram", "pll_ddr0", 0, false}, }; static int ccu_a64_probe(device_t dev) { if (!ofw_bus_status_okay(dev)) return (ENXIO); if (!ofw_bus_is_compatible(dev, "allwinner,sun50i-a64-ccu")) return (ENXIO); device_set_desc(dev, "Allwinner A64 Clock Control Unit NG"); return (BUS_PROBE_DEFAULT); } static int ccu_a64_attach(device_t dev) { struct aw_ccung_softc *sc; sc = device_get_softc(dev); sc->resets = a64_ccu_resets; sc->nresets = nitems(a64_ccu_resets); sc->gates = a64_ccu_gates; sc->ngates = nitems(a64_ccu_gates); sc->clks = a64_ccu_clks; sc->nclks = nitems(a64_ccu_clks); sc->clk_init = a64_init_clks; sc->n_clk_init = nitems(a64_init_clks); return (aw_ccung_attach(dev)); } static device_method_t ccu_a64ng_methods[] = { /* Device interface */ DEVMETHOD(device_probe, ccu_a64_probe), DEVMETHOD(device_attach, ccu_a64_attach), DEVMETHOD_END }; static devclass_t ccu_a64ng_devclass; DEFINE_CLASS_1(ccu_a64ng, ccu_a64ng_driver, ccu_a64ng_methods, sizeof(struct aw_ccung_softc), aw_ccung_driver); EARLY_DRIVER_MODULE(ccu_a64ng, simplebus, ccu_a64ng_driver, ccu_a64ng_devclass, 0, 0, BUS_PASS_BUS + BUS_PASS_ORDER_LAST); Index: head/sys/arm/allwinner/clkng/ccu_h3.c =================================================================== --- head/sys/arm/allwinner/clkng/ccu_h3.c (revision 348180) +++ head/sys/arm/allwinner/clkng/ccu_h3.c (revision 348181) @@ -1,790 +1,790 @@ /*- * SPDX-License-Identifier: BSD-2-Clause-FreeBSD * * Copyright (c) 2017,2018 Emmanuel Vadot * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. * * $FreeBSD$ */ #include __FBSDID("$FreeBSD$"); #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #if defined(__aarch64__) #include "opt_soc.h" #endif #include #include #include /* Non-exported resets */ #define RST_BUS_SCR 53 /* Non-exported clocks */ #define CLK_PLL_CPUX 0 #define CLK_PLL_AUDIO_BASE 1 #define CLK_PLL_AUDIO 2 #define CLK_PLL_AUDIO_2X 3 #define CLK_PLL_AUDIO_4X 4 #define CLK_PLL_AUDIO_8X 5 #define CLK_PLL_VIDEO 6 #define CLK_PLL_VE 7 #define CLK_PLL_DDR 8 #define CLK_PLL_PERIPH0_2X 10 #define CLK_PLL_GPU 11 #define CLK_PLL_PERIPH1 12 #define CLK_PLL_DE 13 #define CLK_AXI 15 #define CLK_AHB1 16 #define CLK_APB1 17 #define CLK_APB2 18 #define CLK_AHB2 19 #define CLK_BUS_SCR 66 #define CLK_USBPHY0 88 #define CLK_USBPHY1 89 #define CLK_USBPHY2 90 #define CLK_USBPHY3 91 #define CLK_USBOHCI0 92 #define CLK_USBOHCI1 93 #define CLK_USBOHCI2 94 #define CLK_USBOHCI3 95 #define CLK_DRAM 96 #define CLK_MBUS 113 static struct aw_ccung_reset h3_ccu_resets[] = { CCU_RESET(RST_USB_PHY0, 0xcc, 0) CCU_RESET(RST_USB_PHY1, 0xcc, 1) CCU_RESET(RST_USB_PHY2, 0xcc, 2) CCU_RESET(RST_USB_PHY3, 0xcc, 3) CCU_RESET(RST_MBUS, 0xfc, 31) CCU_RESET(RST_BUS_CE, 0x2c0, 5) CCU_RESET(RST_BUS_DMA, 0x2c0, 6) CCU_RESET(RST_BUS_MMC0, 0x2c0, 8) CCU_RESET(RST_BUS_MMC1, 0x2c0, 9) CCU_RESET(RST_BUS_MMC2, 0x2c0, 10) CCU_RESET(RST_BUS_NAND, 0x2c0, 13) CCU_RESET(RST_BUS_DRAM, 0x2c0, 14) CCU_RESET(RST_BUS_EMAC, 0x2c0, 17) CCU_RESET(RST_BUS_TS, 0x2c0, 18) CCU_RESET(RST_BUS_HSTIMER, 0x2c0, 19) CCU_RESET(RST_BUS_SPI0, 0x2c0, 20) CCU_RESET(RST_BUS_SPI1, 0x2c0, 21) CCU_RESET(RST_BUS_OTG, 0x2c0, 23) CCU_RESET(RST_BUS_EHCI0, 0x2c0, 24) CCU_RESET(RST_BUS_EHCI1, 0x2c0, 25) CCU_RESET(RST_BUS_EHCI2, 0x2c0, 26) CCU_RESET(RST_BUS_EHCI3, 0x2c0, 27) CCU_RESET(RST_BUS_OHCI0, 0x2c0, 28) CCU_RESET(RST_BUS_OHCI1, 0x2c0, 29) CCU_RESET(RST_BUS_OHCI2, 0x2c0, 30) CCU_RESET(RST_BUS_OHCI3, 0x2c0, 31) CCU_RESET(RST_BUS_VE, 0x2c4, 0) CCU_RESET(RST_BUS_TCON0, 0x2c4, 3) CCU_RESET(RST_BUS_TCON1, 0x2c4, 4) CCU_RESET(RST_BUS_DEINTERLACE, 0x2c4, 5) CCU_RESET(RST_BUS_CSI, 0x2c4, 8) CCU_RESET(RST_BUS_TVE, 0x2c4, 9) CCU_RESET(RST_BUS_HDMI0, 0x2c4, 10) CCU_RESET(RST_BUS_HDMI1, 0x2c4, 11) CCU_RESET(RST_BUS_DE, 0x2c4, 12) CCU_RESET(RST_BUS_GPU, 0x2c4, 20) CCU_RESET(RST_BUS_MSGBOX, 0x2c4, 21) CCU_RESET(RST_BUS_SPINLOCK, 0x2c4, 22) CCU_RESET(RST_BUS_DBG, 0x2c4, 31) CCU_RESET(RST_BUS_EPHY, 0x2c8, 2) CCU_RESET(RST_BUS_CODEC, 0x2d0, 0) CCU_RESET(RST_BUS_SPDIF, 0x2d0, 1) CCU_RESET(RST_BUS_THS, 0x2d0, 8) CCU_RESET(RST_BUS_I2S0, 0x2d0, 12) CCU_RESET(RST_BUS_I2S1, 0x2d0, 13) CCU_RESET(RST_BUS_I2S2, 0x2d0, 14) CCU_RESET(RST_BUS_I2C0, 0x2d8, 0) CCU_RESET(RST_BUS_I2C1, 0x2d8, 1) CCU_RESET(RST_BUS_I2C2, 0x2d8, 2) CCU_RESET(RST_BUS_UART0, 0x2d8, 16) CCU_RESET(RST_BUS_UART1, 0x2d8, 17) CCU_RESET(RST_BUS_UART2, 0x2d8, 18) CCU_RESET(RST_BUS_UART3, 0x2d8, 19) CCU_RESET(RST_BUS_SCR, 0x2d8, 20) }; static struct aw_ccung_gate h3_ccu_gates[] = { CCU_GATE(CLK_BUS_CE, "bus-ce", "ahb1", 0x60, 5) CCU_GATE(CLK_BUS_DMA, "bus-dma", "ahb1", 0x60, 6) CCU_GATE(CLK_BUS_MMC0, "bus-mmc0", "ahb1", 0x60, 8) CCU_GATE(CLK_BUS_MMC1, "bus-mmc1", "ahb1", 0x60, 9) CCU_GATE(CLK_BUS_MMC2, "bus-mmc2", "ahb1", 0x60, 10) CCU_GATE(CLK_BUS_NAND, "bus-nand", "ahb1", 0x60, 13) CCU_GATE(CLK_BUS_DRAM, "bus-dram", "ahb1", 0x60, 14) CCU_GATE(CLK_BUS_EMAC, "bus-emac", "ahb2", 0x60, 17) CCU_GATE(CLK_BUS_TS, "bus-ts", "ahb1", 0x60, 18) CCU_GATE(CLK_BUS_HSTIMER, "bus-hstimer", "ahb1", 0x60, 19) CCU_GATE(CLK_BUS_SPI0, "bus-spi0", "ahb1", 0x60, 20) CCU_GATE(CLK_BUS_SPI1, "bus-spi1", "ahb1", 0x60, 21) CCU_GATE(CLK_BUS_OTG, "bus-otg", "ahb1", 0x60, 23) CCU_GATE(CLK_BUS_EHCI0, "bus-ehci0", "ahb1", 0x60, 24) CCU_GATE(CLK_BUS_EHCI1, "bus-ehci1", "ahb2", 0x60, 25) CCU_GATE(CLK_BUS_EHCI2, "bus-ehci2", "ahb2", 0x60, 26) CCU_GATE(CLK_BUS_EHCI3, "bus-ehci3", "ahb2", 0x60, 27) CCU_GATE(CLK_BUS_OHCI0, "bus-ohci0", "ahb1", 0x60, 28) CCU_GATE(CLK_BUS_OHCI1, "bus-ohci1", "ahb2", 0x60, 29) CCU_GATE(CLK_BUS_OHCI2, "bus-ohci2", "ahb2", 0x60, 30) CCU_GATE(CLK_BUS_OHCI3, "bus-ohci3", "ahb2", 0x60, 31) CCU_GATE(CLK_BUS_VE, "bus-ve", "ahb1", 0x64, 0) CCU_GATE(CLK_BUS_TCON0, "bus-tcon0", "ahb1", 0x64, 3) CCU_GATE(CLK_BUS_TCON1, "bus-tcon1", "ahb1", 0x64, 4) CCU_GATE(CLK_BUS_DEINTERLACE, "bus-deinterlace", "ahb1", 0x64, 5) CCU_GATE(CLK_BUS_CSI, "bus-csi", "ahb1", 0x64, 8) CCU_GATE(CLK_BUS_TVE, "bus-tve", "ahb1", 0x64, 9) CCU_GATE(CLK_BUS_HDMI, "bus-hdmi", "ahb1", 0x64, 11) CCU_GATE(CLK_BUS_DE, "bus-de", "ahb1", 0x64, 12) CCU_GATE(CLK_BUS_GPU, "bus-gpu", "ahb1", 0x64, 20) CCU_GATE(CLK_BUS_MSGBOX, "bus-msgbox", "ahb1", 0x64, 21) CCU_GATE(CLK_BUS_SPINLOCK, "bus-spinlock", "ahb1", 0x64, 22) CCU_GATE(CLK_BUS_CODEC, "bus-codec", "apb1", 0x68, 0) CCU_GATE(CLK_BUS_SPDIF, "bus-spdif", "apb1", 0x68, 1) CCU_GATE(CLK_BUS_PIO, "bus-pio", "apb1", 0x68, 5) CCU_GATE(CLK_BUS_THS, "bus-ths", "apb1", 0x68, 8) CCU_GATE(CLK_BUS_I2S0, "bus-i2s0", "apb1", 0x68, 12) CCU_GATE(CLK_BUS_I2S1, "bus-i2s1", "apb1", 0x68, 13) CCU_GATE(CLK_BUS_I2S2, "bus-i2s2", "apb1", 0x68, 14) CCU_GATE(CLK_BUS_I2C0, "bus-i2c0", "apb2", 0x6c, 0) CCU_GATE(CLK_BUS_I2C1, "bus-i2c1", "apb2", 0x6c, 1) CCU_GATE(CLK_BUS_I2C2, "bus-i2c2", "apb2", 0x6c, 2) CCU_GATE(CLK_BUS_UART0, "bus-uart0", "apb2", 0x6c, 16) CCU_GATE(CLK_BUS_UART1, "bus-uart1", "apb2", 0x6c, 17) CCU_GATE(CLK_BUS_UART2, "bus-uart2", "apb2", 0x6c, 18) CCU_GATE(CLK_BUS_UART3, "bus-uart3", "apb2", 0x6c, 19) CCU_GATE(CLK_BUS_SCR, "bus-scr", "apb2", 0x6c, 20) CCU_GATE(CLK_BUS_EPHY, "bus-ephy", "ahb1", 0x70, 0) CCU_GATE(CLK_BUS_DBG, "bus-dbg", "ahb1", 0x70, 7) CCU_GATE(CLK_USBPHY0, "usb-phy0", "osc24M", 0xcc, 8) CCU_GATE(CLK_USBPHY1, "usb-phy1", "osc24M", 0xcc, 9) CCU_GATE(CLK_USBPHY2, "usb-phy2", "osc24M", 0xcc, 10) CCU_GATE(CLK_USBPHY3, "usb-phy3", "osc24M", 0xcc, 11) CCU_GATE(CLK_USBOHCI0, "usb-ohci0", "osc24M", 0xcc, 16) CCU_GATE(CLK_USBOHCI1, "usb-ohci1", "osc24M", 0xcc, 17) CCU_GATE(CLK_USBOHCI2, "usb-ohci2", "osc24M", 0xcc, 18) CCU_GATE(CLK_USBOHCI3, "usb-ohci3", "osc24M", 0xcc, 19) CCU_GATE(CLK_THS, "ths", "thsdiv", 0x74, 31) CCU_GATE(CLK_I2S0, "i2s0", "i2s0mux", 0xB0, 31) CCU_GATE(CLK_I2S1, "i2s1", "i2s1mux", 0xB4, 31) CCU_GATE(CLK_I2S2, "i2s2", "i2s2mux", 0xB8, 31) CCU_GATE(CLK_DRAM_VE, "dram-ve", "dram", 0x100, 0) CCU_GATE(CLK_DRAM_CSI, "dram-csi", "dram", 0x100, 1) CCU_GATE(CLK_DRAM_DEINTERLACE, "dram-deinterlace", "dram", 0x100, 2) CCU_GATE(CLK_DRAM_TS, "dram-ts", "dram", 0x100, 3) CCU_GATE(CLK_AC_DIG, "ac-dig", "pll_audio", 0x140, 31) CCU_GATE(CLK_AVS, "avs", "osc24M", 0x144, 31) CCU_GATE(CLK_CSI_MISC, "csi-misc", "osc24M", 0x130, 31) CCU_GATE(CLK_HDMI_DDC, "hdmi-ddc", "osc24M", 0x154, 31) }; static const char *pll_cpux_parents[] = {"osc24M"}; NKMP_CLK(pll_cpux_clk, CLK_PLL_CPUX, /* id */ "pll_cpux", pll_cpux_parents, /* name, parents */ 0x00, /* offset */ 8, 5, 0, 0, /* n factor */ 4, 2, 0, 0, /* k factor */ 0, 2, 0, 0, /* m factor */ 16, 2, 0, AW_CLK_FACTOR_POWER_OF_TWO, /* p factor */ 31, /* gate */ 28, 1000, /* lock */ AW_CLK_HAS_GATE | AW_CLK_HAS_LOCK | AW_CLK_SCALE_CHANGE); /* flags */ static const char *pll_audio_parents[] = {"osc24M"}; NKMP_CLK(pll_audio_clk, CLK_PLL_AUDIO, /* id */ "pll_audio", pll_audio_parents, /* name, parents */ 0x08, /* offset */ 8, 7, 0, 0, /* n factor */ 0, 0, 1, AW_CLK_FACTOR_FIXED, /* k factor (fake) */ 0, 5, 0, 0, /* m factor */ 16, 4, 0, 0, /* p factor */ 31, /* gate */ 28, 1000, /* lock */ AW_CLK_HAS_GATE | AW_CLK_HAS_LOCK); /* flags */ static const char *pll_audio_mult_parents[] = {"pll_audio"}; FIXED_CLK(pll_audio_2x_clk, CLK_PLL_AUDIO_2X, /* id */ "pll_audio-2x", /* name */ pll_audio_mult_parents, /* parent */ 0, /* freq */ 2, /* mult */ 1, /* div */ 0); /* flags */ FIXED_CLK(pll_audio_4x_clk, CLK_PLL_AUDIO_4X, /* id */ "pll_audio-4x", /* name */ pll_audio_mult_parents, /* parent */ 0, /* freq */ 4, /* mult */ 1, /* div */ 0); /* flags */ FIXED_CLK(pll_audio_8x_clk, CLK_PLL_AUDIO_8X, /* id */ "pll_audio-8x", /* name */ pll_audio_mult_parents, /* parent */ 0, /* freq */ 8, /* mult */ 1, /* div */ 0); /* flags */ static const char *pll_video_parents[] = {"osc24M"}; -NM_CLK_WITH_FRAC(pll_video_clk, +FRAC_CLK(pll_video_clk, CLK_PLL_VIDEO, /* id */ "pll_video", pll_video_parents, /* name, parents */ 0x10, /* offset */ 8, 7, 0, 0, /* n factor */ 0, 4, 0, 0, /* m factor */ 31, 28, 1000, /* gate, lock, lock retries */ AW_CLK_HAS_LOCK, /* flags */ 270000000, 297000000, /* freq0, freq1 */ 24, 25); /* mode sel, freq sel */ static const char *pll_ve_parents[] = {"osc24M"}; -NM_CLK_WITH_FRAC(pll_ve_clk, +FRAC_CLK(pll_ve_clk, CLK_PLL_VE, /* id */ "pll_ve", pll_ve_parents, /* name, parents */ 0x18, /* offset */ 8, 7, 0, 0, /* n factor */ 0, 4, 0, 0, /* m factor */ 31, 28, 1000, /* gate, lock, lock retries */ AW_CLK_HAS_LOCK, /* flags */ 270000000, 297000000, /* freq0, freq1 */ 24, 25); /* mode sel, freq sel */ static const char *pll_ddr_parents[] = {"osc24M"}; NKMP_CLK_WITH_UPDATE(pll_ddr_clk, CLK_PLL_DDR, /* id */ "pll_ddr", pll_ddr_parents, /* name, parents */ 0x20, /* offset */ 8, 5, 0, 0, /* n factor */ 4, 2, 0, 0, /* k factor */ 0, 2, 0, 0, /* m factor */ 0, 0, 1, AW_CLK_FACTOR_FIXED, /* p factor (fake) */ 31, /* gate */ 28, 1000, /* lock */ 20, /* update */ AW_CLK_HAS_GATE | AW_CLK_HAS_LOCK); /* flags */ static const char *pll_periph0_parents[] = {"osc24M"}; static const char *pll_periph0_2x_parents[] = {"pll_periph0"}; NKMP_CLK(pll_periph0_clk, CLK_PLL_PERIPH0, /* id */ "pll_periph0", pll_periph0_parents, /* name, parents */ 0x28, /* offset */ 8, 5, 0, 0, /* n factor */ 4, 2, 0, 0, /* k factor */ 0, 0, 2, AW_CLK_FACTOR_FIXED, /* m factor (fake) */ 0, 0, 1, AW_CLK_FACTOR_FIXED, /* p factor (fake) */ 31, /* gate */ 28, 1000, /* lock */ AW_CLK_HAS_GATE | AW_CLK_HAS_LOCK); /* flags */ FIXED_CLK(pll_periph0_2x_clk, CLK_PLL_PERIPH0_2X, /* id */ "pll_periph0-2x", /* name */ pll_periph0_2x_parents, /* parent */ 0, /* freq */ 2, /* mult */ 1, /* div */ 0); /* flags */ static const char *pll_gpu_parents[] = {"osc24M"}; -NM_CLK_WITH_FRAC(pll_gpu_clk, +FRAC_CLK(pll_gpu_clk, CLK_PLL_GPU, /* id */ "pll_gpu", pll_gpu_parents, /* name, parents */ 0x38, /* offset */ 8, 7, 0, 0, /* n factor */ 0, 4, 0, 0, /* m factor */ 31, 28, 1000, /* gate, lock, lock retries */ AW_CLK_HAS_LOCK, /* flags */ 270000000, 297000000, /* freq0, freq1 */ 24, 25); /* mode sel, freq sel */ static const char *pll_periph1_parents[] = {"osc24M"}; NKMP_CLK(pll_periph1_clk, CLK_PLL_PERIPH1, /* id */ "pll_periph1", pll_periph1_parents, /* name, parents */ 0x44, /* offset */ 8, 5, 0, 0, /* n factor */ 4, 2, 0, 0, /* k factor */ 0, 0, 2, AW_CLK_FACTOR_FIXED, /* m factor (fake) */ 0, 0, 1, AW_CLK_FACTOR_FIXED, /* p factor (fake) */ 31, /* gate */ 28, 1000, /* lock */ AW_CLK_HAS_GATE | AW_CLK_HAS_LOCK); /* flags */ static const char *pll_de_parents[] = {"osc24M"}; -NM_CLK_WITH_FRAC(pll_de_clk, +FRAC_CLK(pll_de_clk, CLK_PLL_DE, /* id */ "pll_de", pll_de_parents, /* name, parents */ 0x48, /* offset */ 8, 7, 0, 0, /* n factor */ 0, 4, 0, 0, /* m factor */ 31, 28, 1000, /* gate, lock, lock retries */ AW_CLK_HAS_LOCK, /* flags */ 270000000, 297000000, /* freq0, freq1 */ 24, 25); /* mode sel, freq sel */ static const char *cpux_parents[] = {"osc32k", "osc24M", "pll_cpux", "pll_cpux"}; MUX_CLK(cpux_clk, CLK_CPUX, /* id */ "cpux", cpux_parents, /* name, parents */ 0x50, 16, 2); /* offset, shift, width */ static const char *axi_parents[] = {"cpux"}; DIV_CLK(axi_clk, CLK_AXI, /* id */ "axi", axi_parents, /* name, parents */ 0x50, /* offset */ 0, 2, /* shift, width */ 0, NULL); /* flags, div table */ static const char *ahb1_parents[] = {"osc32k", "osc24M", "axi", "pll_periph0"}; PREDIV_CLK(ahb1_clk, CLK_AHB1, /* id */ "ahb1", ahb1_parents, /* name, parents */ 0x54, /* offset */ 12, 2, /* mux */ 4, 2, 0, AW_CLK_FACTOR_POWER_OF_TWO, /* div */ 6, 2, 0, AW_CLK_FACTOR_HAS_COND, /* prediv */ 12, 2, 3); /* prediv condition */ static const char *apb1_parents[] = {"ahb1"}; static struct clk_div_table apb1_div_table[] = { { .value = 0, .divider = 2, }, { .value = 1, .divider = 2, }, { .value = 2, .divider = 4, }, { .value = 3, .divider = 8, }, { }, }; DIV_CLK(apb1_clk, CLK_APB1, /* id */ "apb1", apb1_parents, /* name, parents */ 0x54, /* offset */ 8, 2, /* shift, width */ CLK_DIV_WITH_TABLE, /* flags */ apb1_div_table); /* div table */ static const char *apb2_parents[] = {"osc32k", "osc24M", "pll_periph0", "pll_periph0"}; NM_CLK(apb2_clk, CLK_APB2, /* id */ "apb2", apb2_parents, /* name, parents */ 0x58, /* offset */ 16, 2, 0, AW_CLK_FACTOR_POWER_OF_TWO, /* n factor */ 0, 5, 0, 0, /* m factor */ 24, 2, /* mux */ 0, /* gate */ AW_CLK_HAS_MUX); static const char *ahb2_parents[] = {"ahb1", "pll_periph0"}; PREDIV_CLK(ahb2_clk, CLK_AHB2, /* id */ "ahb2", ahb2_parents, /* name, parents */ 0x5c, /* offset */ 0, 2, /* mux */ 0, 0, 1, AW_CLK_FACTOR_FIXED, /* div */ 0, 0, 2, AW_CLK_FACTOR_HAS_COND | AW_CLK_FACTOR_FIXED, /* prediv */ 0, 2, 1); /* prediv condition */ static const char *ths_parents[] = {"osc24M"}; static struct clk_div_table ths_div_table[] = { { .value = 0, .divider = 1, }, { .value = 1, .divider = 2, }, { .value = 2, .divider = 4, }, { .value = 3, .divider = 6, }, { }, }; DIV_CLK(thsdiv_clk, 0, /* id */ "thsdiv", ths_parents, /* name, parents */ 0x74, /* offset */ 0, 2, /* shift, width */ CLK_DIV_WITH_TABLE, /* flags */ ths_div_table); /* div table */ static const char *mod_parents[] = {"osc24M", "pll_periph0", "pll_periph1"}; NM_CLK(nand_clk, CLK_NAND, "nand", mod_parents, /* id, name, parents */ 0x80, /* offset */ 16, 2, 0, AW_CLK_FACTOR_POWER_OF_TWO, /* n factor */ 0, 4, 0, 0, /* m factor */ 24, 2, /* mux */ 31, /* gate */ AW_CLK_HAS_GATE | AW_CLK_HAS_MUX); /* flags */ NM_CLK(mmc0_clk, CLK_MMC0, "mmc0", mod_parents, /* id, name, parents */ 0x88, /* offset */ 16, 2, 0, AW_CLK_FACTOR_POWER_OF_TWO, /* n factor */ 0, 4, 0, 0, /* m factor */ 24, 2, /* mux */ 31, /* gate */ AW_CLK_HAS_GATE | AW_CLK_HAS_MUX | AW_CLK_REPARENT); /* flags */ NM_CLK(mmc1_clk, CLK_MMC1, "mmc1", mod_parents, /* id, name, parents */ 0x8c, /* offset */ 16, 2, 0, AW_CLK_FACTOR_POWER_OF_TWO, /* n factor */ 0, 4, 0, 0, /* m factor */ 24, 2, /* mux */ 31, /* gate */ AW_CLK_HAS_GATE | AW_CLK_HAS_MUX | AW_CLK_REPARENT); /* flags */ NM_CLK(mmc2_clk, CLK_MMC2, "mmc2", mod_parents, /* id, name, parents */ 0x90, /* offset */ 16, 2, 0, AW_CLK_FACTOR_POWER_OF_TWO, /* n factor */ 0, 4, 0, 0, /* m factor */ 24, 2, /* mux */ 31, /* gate */ AW_CLK_HAS_GATE | AW_CLK_HAS_MUX | AW_CLK_REPARENT); /* flags */ static const char *ts_parents[] = {"osc24M", "pll_periph0"}; NM_CLK(ts_clk, CLK_TS, "ts", ts_parents, /* id, name, parents */ 0x98, /* offset */ 16, 2, 0, AW_CLK_FACTOR_POWER_OF_TWO, /* n factor */ 0, 4, 0, 0, /* m factor */ 24, 2, /* mux */ 31, /* gate */ AW_CLK_HAS_GATE | AW_CLK_HAS_MUX); /* flags */ NM_CLK(ce_clk, CLK_CE, "ce", mod_parents, /* id, name, parents */ 0x9C, /* offset */ 16, 2, 0, AW_CLK_FACTOR_POWER_OF_TWO, /* n factor */ 0, 4, 0, 0, /* m factor */ 24, 2, /* mux */ 31, /* gate */ AW_CLK_HAS_GATE | AW_CLK_HAS_MUX); /* flags */ NM_CLK(spi0_clk, CLK_SPI0, "spi0", mod_parents, /* id, name, parents */ 0xA0, /* offset */ 16, 2, 0, AW_CLK_FACTOR_POWER_OF_TWO, /* n factor */ 0, 4, 0, 0, /* m factor */ 24, 2, /* mux */ 31, /* gate */ AW_CLK_HAS_GATE | AW_CLK_HAS_MUX | AW_CLK_REPARENT); /* flags */ NM_CLK(spi1_clk, CLK_SPI1, "spi1", mod_parents, /* id, name, parents */ 0xA4, /* offset */ 16, 2, 0, AW_CLK_FACTOR_POWER_OF_TWO, /* n factor */ 0, 4, 0, 0, /* m factor */ 24, 2, /* mux */ 31, /* gate */ AW_CLK_HAS_GATE | AW_CLK_HAS_MUX | AW_CLK_REPARENT); /* flags */ static const char *i2s_parents[] = {"pll_audio-8x", "pll_audio-4x", "pll_audio-2x", "pll_audio"}; MUX_CLK(i2s0mux_clk, 0, "i2s0mux", i2s_parents, /* id, name, parents */ 0xb0, 16, 2); /* offset, mux shift, mux width */ MUX_CLK(i2s1mux_clk, 0, "i2s1mux", i2s_parents, /* id, name, parents */ 0xb4, 16, 2); /* offset, mux shift, mux width */ MUX_CLK(i2s2mux_clk, 0, "i2s2mux", i2s_parents, /* id, name, parents */ 0xb8, 16, 2); /* offset, mux shift, mux width */ static const char *spdif_parents[] = {"pll_audio"}; NM_CLK(spdif_clk, CLK_SPDIF, "spdif", spdif_parents, /* id, name, parents */ 0xC0, /* offset */ 0, 0, 1, AW_CLK_FACTOR_FIXED, /* n factor (fake); */ 0, 4, 0, 0, /* m factor */ 0, 0, /* mux */ 31, /* gate */ AW_CLK_HAS_GATE); /* flags */ static const char *dram_parents[] = {"pll_ddr", "pll_periph0-2x"}; NM_CLK(dram_clk, CLK_DRAM, "dram", dram_parents, /* id, name, parents */ 0xF4, /* offset */ 0, 0, 1, AW_CLK_FACTOR_FIXED, /* n factor (fake) */ 0, 4, 0, 0, /* m factor */ 20, 2, /* mux */ 0, /* gate */ AW_CLK_HAS_MUX); /* flags */ static const char *de_parents[] = {"pll_periph0-2x", "pll_de"}; NM_CLK(de_clk, CLK_DE, "de", de_parents, /* id, name, parents */ 0x104, /* offset */ 0, 0, 1, AW_CLK_FACTOR_FIXED, /* n factor (fake) */ 0, 4, 0, 0, /* m factor */ 24, 2, /* mux */ 31, /* gate */ AW_CLK_HAS_MUX | AW_CLK_HAS_GATE); /* flags */ static const char *tcon0_parents[] = {"pll_video"}; NM_CLK(tcon0_clk, CLK_TCON0, "tcon0", tcon0_parents, /* id, name, parents */ 0x118, /* offset */ 0, 0, 1, AW_CLK_FACTOR_FIXED, /* n factor (fake) */ 0, 4, 0, 0, /* m factor */ 24, 2, /* mux */ 31, /* gate */ AW_CLK_HAS_MUX | AW_CLK_HAS_GATE); /* flags */ static const char *tve_parents[] = {"pll_de", "pll_periph1"}; NM_CLK(tve_clk, CLK_TVE, "tve", tve_parents, /* id, name, parents */ 0x120, /* offset */ 0, 0, 1, AW_CLK_FACTOR_FIXED, /* n factor (fake) */ 0, 4, 0, 0, /* m factor */ 24, 2, /* mux */ 31, /* gate */ AW_CLK_HAS_MUX | AW_CLK_HAS_GATE); /* flags */ static const char *deinterlace_parents[] = {"pll_periph0", "pll_periph1"}; NM_CLK(deinterlace_clk, CLK_DEINTERLACE, "deinterlace", deinterlace_parents, /* id, name, parents */ 0x124, /* offset */ 0, 0, 1, AW_CLK_FACTOR_FIXED, /* n factor (fake) */ 0, 4, 0, 0, /* m factor */ 24, 2, /* mux */ 31, /* gate */ AW_CLK_HAS_MUX | AW_CLK_HAS_GATE); /* flags */ static const char *csi_sclk_parents[] = {"pll_periph0", "pll_periph1"}; NM_CLK(csi_sclk_clk, CLK_CSI_SCLK, "csi-sclk", csi_sclk_parents, /* id, name, parents */ 0x134, /* offset */ 0, 0, 1, AW_CLK_FACTOR_FIXED, /* n factor (fake) */ 16, 4, 0, 0, /* m factor */ 24, 2, /* mux */ 31, /* gate */ AW_CLK_HAS_MUX | AW_CLK_HAS_GATE); /* flags */ static const char *csi_mclk_parents[] = {"osc24M", "pll_video", "pll_periph1"}; NM_CLK(csi_mclk_clk, CLK_CSI_MCLK, "csi-mclk", csi_mclk_parents, /* id, name, parents */ 0x134, /* offset */ 0, 0, 1, AW_CLK_FACTOR_FIXED, /* n factor (fake) */ 0, 4, 0, 0, /* m factor */ 8, 2, /* mux */ 15, /* gate */ AW_CLK_HAS_MUX | AW_CLK_HAS_GATE); /* flags */ static const char *ve_parents[] = {"pll_ve"}; NM_CLK(ve_clk, CLK_VE, "ve", ve_parents, /* id, name, parents */ 0x13C, /* offset */ 16, 3, 0, 0, /* n factor */ 0, 0, 1, AW_CLK_FACTOR_FIXED, /* m factor (fake) */ 0, 0, /* mux */ 31, /* gate */ AW_CLK_HAS_GATE); /* flags */ static const char *hdmi_parents[] = {"pll_video"}; NM_CLK(hdmi_clk, CLK_HDMI, "hdmi", hdmi_parents, /* id, name, parents */ 0x150, /* offset */ 0, 0, 1, AW_CLK_FACTOR_FIXED, /* n factor (fake) */ 0, 4, 0, 0, /* m factor */ 24, 2, /* mux */ 31, /* gate */ AW_CLK_HAS_MUX | AW_CLK_HAS_GATE); /* flags */ static const char *mbus_parents[] = {"osc24M", "pll_periph0-2x", "pll_ddr"}; NM_CLK(mbus_clk, CLK_MBUS, "mbus", mbus_parents, /* id, name, parents */ 0x15C, /* offset */ 0, 0, 1, AW_CLK_FACTOR_FIXED, /* n factor (fake) */ 0, 3, 0, 0, /* m factor */ 24, 2, /* mux */ 31, /* gate */ AW_CLK_HAS_MUX | AW_CLK_HAS_GATE); /* flags */ static const char *gpu_parents[] = {"pll_gpu"}; NM_CLK(gpu_clk, CLK_GPU, "gpu", gpu_parents, /* id, name, parents */ 0x1A0, /* offset */ 0, 2, 0, 0, /* n factor */ 0, 0, 1, AW_CLK_FACTOR_FIXED, /* m factor (fake) */ 0, 0, /* mux */ 31, /* gate */ AW_CLK_HAS_GATE); /* flags */ static struct aw_ccung_clk h3_ccu_clks[] = { { .type = AW_CLK_NKMP, .clk.nkmp = &pll_cpux_clk}, { .type = AW_CLK_NKMP, .clk.nkmp = &pll_audio_clk}, { .type = AW_CLK_NKMP, .clk.nkmp = &pll_periph0_clk}, { .type = AW_CLK_NKMP, .clk.nkmp = &pll_periph1_clk}, { .type = AW_CLK_NKMP, .clk.nkmp = &pll_ddr_clk}, - { .type = AW_CLK_NM, .clk.nm = &pll_video_clk}, - { .type = AW_CLK_NM, .clk.nm = &pll_ve_clk}, - { .type = AW_CLK_NM, .clk.nm = &pll_gpu_clk}, - { .type = AW_CLK_NM, .clk.nm = &pll_de_clk}, + { .type = AW_CLK_FRAC, .clk.frac = &pll_video_clk}, + { .type = AW_CLK_FRAC, .clk.frac = &pll_ve_clk}, + { .type = AW_CLK_FRAC, .clk.frac = &pll_gpu_clk}, + { .type = AW_CLK_FRAC, .clk.frac = &pll_de_clk}, { .type = AW_CLK_NM, .clk.nm = &apb2_clk}, { .type = AW_CLK_NM, .clk.nm = &nand_clk}, { .type = AW_CLK_NM, .clk.nm = &mmc0_clk}, { .type = AW_CLK_NM, .clk.nm = &mmc1_clk}, { .type = AW_CLK_NM, .clk.nm = &mmc2_clk}, { .type = AW_CLK_NM, .clk.nm = &ts_clk}, { .type = AW_CLK_NM, .clk.nm = &ce_clk}, { .type = AW_CLK_NM, .clk.nm = &spi0_clk}, { .type = AW_CLK_NM, .clk.nm = &spi1_clk}, { .type = AW_CLK_NM, .clk.nm = &spdif_clk}, { .type = AW_CLK_NM, .clk.nm = &dram_clk}, { .type = AW_CLK_NM, .clk.nm = &de_clk}, { .type = AW_CLK_NM, .clk.nm = &tcon0_clk}, { .type = AW_CLK_NM, .clk.nm = &tve_clk}, { .type = AW_CLK_NM, .clk.nm = &deinterlace_clk}, { .type = AW_CLK_NM, .clk.nm = &csi_sclk_clk}, { .type = AW_CLK_NM, .clk.nm = &csi_mclk_clk}, { .type = AW_CLK_NM, .clk.nm = &ve_clk}, { .type = AW_CLK_NM, .clk.nm = &hdmi_clk}, { .type = AW_CLK_NM, .clk.nm = &mbus_clk}, { .type = AW_CLK_NM, .clk.nm = &gpu_clk}, { .type = AW_CLK_PREDIV_MUX, .clk.prediv_mux = &ahb1_clk}, { .type = AW_CLK_PREDIV_MUX, .clk.prediv_mux = &ahb2_clk}, { .type = AW_CLK_MUX, .clk.mux = &cpux_clk}, { .type = AW_CLK_MUX, .clk.mux = &i2s0mux_clk}, { .type = AW_CLK_MUX, .clk.mux = &i2s1mux_clk}, { .type = AW_CLK_MUX, .clk.mux = &i2s2mux_clk}, { .type = AW_CLK_DIV, .clk.div = &axi_clk}, { .type = AW_CLK_DIV, .clk.div = &apb1_clk}, { .type = AW_CLK_DIV, .clk.div = &thsdiv_clk}, { .type = AW_CLK_FIXED, .clk.fixed = &pll_periph0_2x_clk}, { .type = AW_CLK_FIXED, .clk.fixed = &pll_audio_2x_clk}, { .type = AW_CLK_FIXED, .clk.fixed = &pll_audio_4x_clk}, { .type = AW_CLK_FIXED, .clk.fixed = &pll_audio_8x_clk}, }; static struct aw_clk_init h3_init_clks[] = { {"ahb1", "pll_periph0", 0, false}, {"ahb2", "pll_periph0", 0, false}, {"dram", "pll_ddr", 0, false}, }; static struct ofw_compat_data compat_data[] = { #if defined(SOC_ALLWINNER_H3) { "allwinner,sun8i-h3-ccu", 1 }, #endif #if defined(SOC_ALLWINNER_H5) { "allwinner,sun50i-h5-ccu", 1 }, #endif { NULL, 0}, }; static int ccu_h3_probe(device_t dev) { if (!ofw_bus_status_okay(dev)) return (ENXIO); if (ofw_bus_search_compatible(dev, compat_data)->ocd_data == 0) return (ENXIO); device_set_desc(dev, "Allwinner H3/H5 Clock Control Unit NG"); return (BUS_PROBE_DEFAULT); } static int ccu_h3_attach(device_t dev) { struct aw_ccung_softc *sc; sc = device_get_softc(dev); sc->resets = h3_ccu_resets; sc->nresets = nitems(h3_ccu_resets); sc->gates = h3_ccu_gates; sc->ngates = nitems(h3_ccu_gates); sc->clks = h3_ccu_clks; sc->nclks = nitems(h3_ccu_clks); sc->clk_init = h3_init_clks; sc->n_clk_init = nitems(h3_init_clks); return (aw_ccung_attach(dev)); } static device_method_t ccu_h3ng_methods[] = { /* Device interface */ DEVMETHOD(device_probe, ccu_h3_probe), DEVMETHOD(device_attach, ccu_h3_attach), DEVMETHOD_END }; static devclass_t ccu_h3ng_devclass; DEFINE_CLASS_1(ccu_h3ng, ccu_h3ng_driver, ccu_h3ng_methods, sizeof(struct aw_ccung_softc), aw_ccung_driver); EARLY_DRIVER_MODULE(ccu_h3ng, simplebus, ccu_h3ng_driver, ccu_h3ng_devclass, 0, 0, BUS_PASS_BUS + BUS_PASS_ORDER_LAST);