Index: head/share/man/man4/imcsmb.4 =================================================================== --- head/share/man/man4/imcsmb.4 (revision 343582) +++ head/share/man/man4/imcsmb.4 (revision 343583) @@ -1,133 +1,132 @@ .\" .\" SPDX-License-Identifier: BSD-2-Clause-FreeBSD .\" .\" Copyright (c) 2018 Panasas -.\" All rights reserved. .\" .\" Redistribution and use in source and binary forms, with or without .\" modification, are permitted provided that the following conditions .\" are met: .\" 1. Redistributions of source code must retain the above copyright .\" notice, this list of conditions and the following disclaimer. .\" 2. Redistributions in binary form must reproduce the above copyright .\" notice, this list of conditions and the following disclaimer in the .\" documentation and/or other materials provided with the distribution. .\" .\" THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR .\" IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES .\" OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. .\" IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, .\" INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT .\" NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, .\" DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY .\" THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT .\" (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF .\" THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. .\" .\" $FreeBSD$ .\" .Dd March 2, 2018 .Dt IMCSMB 4 .Os .Sh NAME .Nm imcsmb .Nd Intel integrated Memory Controller (iMC) SMBus controller driver .Sh SYNOPSIS .Cd device pci .Cd device smbus .Cd device imcsmb .Pp Alternatively, to load the driver as a module at boot time, place the following line in .Xr loader.conf 5 : .Bd -literal -offset indent imcsmb_load="YES" .Ed .Sh DESCRIPTION The .Nm driver provides .Xr smbus 4 support for the SMBus controller functionality in the integrated Memory Controllers (iMCs) embedded in Intel Sandybridge-Xeon, Ivybridge-Xeon, Haswell-Xeon, and Broadwell-Xeon CPUs. Each CPU implements one or more iMCs, depending on the number of cores; each iMC implements two SMBus controllers (iMC-SMBs). The iMC-SMBs are used by the iMCs to read configuration information from the DIMMs during POST. They may also be used, by motherboard firmware or a BMC, to monitor the temperature of the DIMMs. .Pp The iMC-SMBs are .Sy not general-purpose SMBus controllers. By their nature, they are only ever attached to DIMMs, so they implement only the SMBus operations need for communicating with DIMMs. Specifically: .Pp .Bl -dash -offset indent -compact .It READB .It READW .It WRITEB .It WRITEW .El .Pp A more detailed discussion of the hardware and driver architecture can be found at the top of .Pa sys/dev/imcsmb/imcsmb_pci.c . .Sh WARNINGS As mentioned above, firmware might use the iMC-SMBs to read DIMM temperatures. The public iMC documentation does not describe any sort of coordination mechanism to prevent requests from different sources -- such as the motherboard firmware, a BMC, or the operating system -- from interfering with each other. .Pp .Bf Sy Therefore, it is highly recommended that developers contact the motherboard vendor for any board-specific instructions on how to disable and re-enable DIMM temperature monitoring. .Ef .Pp DIMM temperature monitoring should be disabled before returning from .Fn imcsmb_pci_request_bus , and re-enabled before returning from .Fn imcsmb_pci_release_bus . The driver includes comments to that effect at the appropriate locations. The driver has been tested and shown to work, with only that type of modification, on certain motherboards from Intel. .Po Unfortunately, those modifications were based on material covered under a non-disclosure agreement, and therefore are not included in this driver. .Pc The driver has also been tested and shown to work as-is on various motherboards from SuperMicro. .Pp The .Xr smb 4 driver will connect to the .Xr smbus 4 instances created by .Nm . However, since the IMC-SMBs are not general-purpose SMBus controllers, using .Xr smbmsg 8 with those .Xr smb 4 devices is not supported. .Sh SEE ALSO .Xr jedec_dimm 4 , .Xr smbus 4 .Sh HISTORY The .Nm driver first appeared in .Fx 12.0 . .Sh AUTHORS The .Nm driver was originally written for Panasas by .An Joe Kloss . It was substantially refactored, and this manual page was written, by .An Ravi Pokala Aq Mt rpokala@freebsd.org Index: head/share/man/man4/jedec_dimm.4 =================================================================== --- head/share/man/man4/jedec_dimm.4 (revision 343582) +++ head/share/man/man4/jedec_dimm.4 (revision 343583) @@ -1,242 +1,241 @@ .\" .\" SPDX-License-Identifier: BSD-2-Clause-FreeBSD .\" .\" Copyright (c) 2016 Andriy Gapon .\" Copyright (c) 2018 Ravi Pokala -.\" All rights reserved. .\" .\" Redistribution and use in source and binary forms, with or without .\" modification, are permitted provided that the following conditions .\" are met: .\" 1. Redistributions of source code must retain the above copyright .\" notice, this list of conditions and the following disclaimer. .\" 2. Redistributions in binary form must reproduce the above copyright .\" notice, this list of conditions and the following disclaimer in the .\" documentation and/or other materials provided with the distribution. .\" .\" THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR .\" IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES .\" OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. .\" IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, .\" INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT .\" NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, .\" DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY .\" THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT .\" (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF .\" THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. .\" .\" $FreeBSD$ .\" .Dd July 31, 2018 .Dt JEDEC_DIMM 4 .Os .Sh NAME .Nm jedec_dimm .Nd report asset information and temperatures for JEDEC DDR3 / DDR4 DIMMs .Sh SYNOPSIS .Bd -ragged -offset indent .Cd "device jedec_dimm" .Cd "device smbus" .Ed .Pp Alternatively, to load the driver as a module at boot time, place the following line in .Xr loader.conf 5 : .Bd -literal -offset indent jedec_dimm_load="YES" .Ed .Pp Addressing information must be manually specified in .Pa /boot/device.hints : .Bd -literal -offset indent .Cd hint.jedec_dimm.0.at="smbus0" .Cd hint.jedec_dimm.0.addr="0xa0" .Cd hint.jedec_dimm.0.slotid="Silkscreen" .Ed .Sh DESCRIPTION The .Nm driver reports asset information (Part Number, Serial Number) encoded in the .Dq Serial Presence Detect (SPD) data on JEDEC DDR3 and DDR4 DIMMs. It also calculates and reports the memory capacity of the DIMM, in megabytes. If the DIMM includes a .Dq Thermal Sensor On DIMM (TSOD), the temperature is also reported. .Pp The .Nm driver accesses the SPD and TSOD over the .Xr smbus 4 . .Pp The data is reported via a .Xr sysctl 8 interface; all values are read-only: .Bl -tag -width "dev.jedec_dimm.X.capacity" .It Va dev.jedec_dimm.X.%desc a string description of the DIMM, including TSOD and slotid info if present. .It Va dev.jedec_dimm.X.capacity the DIMM's memory capacity, in megabytes .It Va dev.jedec_dimm.X.part the manufacturer's part number of the DIMM .It Va dev.jedec_dimm.X.serial the manufacturer's serial number of the DIMM .It Va dev.jedec_dimm.X.slotid a copy of the corresponding hint, if set .It Va dev.jedec_dimm.X.temp if a TSOD is present, the reported temperature .It Va dev.jedec_dimm.X.type the DIMM type (DDR3 or DDR4) .El .Pp These values are configurable for .Nm via .Xr device.hints 5 : .Bl -tag -width "hint.jedec_dimm.X.slotid" .It Va hint.jedec_dimm.X.at the .Xr smbus 4 to which the DIMM is connected .It Va hint.jedec_dimm.X.addr the SMBus address of the SPD. JEDEC specifies that the four most-significant bits of the address are the .Dq Device Type Identifier (DTI), and that the DTI of the SPD is 0xa. Since the least-significant bit of an SMBus address is the read/write bit, and is always written as 0, that means the four least-significant bits of the address must be even. .It Va hint.jedec_dimm.X.slotid optional slot identifier. If populated with the DIMM slot name silkscreened on the motherboard, this provides a mapping between the DIMM slot name and the DIMM serial number. That mapping is useful for detailed asset tracking, and makes it easier to physically locate a specific DIMM when doing a replacement. This is useful when assembling multiple identical systems, as might be done by a system vendor. The mapping between bus/address and DIMM slot must first be determined, either through motherboard documentation or trial-and-error. .El .Pp If the DIMMs are on an I2C bus behind an .Xr iicbus 4 controller, then the .Xr iicsmb 4 bridge driver can be used to attach the .Xr smbus 4 . .Sh EXAMPLES Consider two DDR4 DIMMs with the following hints: .Bd -literal -offset indent hint.jedec_dimm.0.at="smbus0" hint.jedec_dimm.0.addr="0xa0" hint.jedec_dimm.0.slotid="A1" hint.jedec_dimm.6.at="smbus1" hint.jedec_dimm.6.addr="0xa8" .Ed .Pp Their .Xr sysctl 8 output (sorted): .Bd -literal -offset indent dev.jedec_dimm.0.%desc: DDR4 DIMM w/ Atmel TSOD (A1) dev.jedec_dimm.0.%driver: jedec_dimm dev.jedec_dimm.0.%location: addr=0xa0 dev.jedec_dimm.0.%parent: smbus0 dev.jedec_dimm.0.%pnpinfo: dev.jedec_dimm.0.capacity: 16384 dev.jedec_dimm.0.part: 36ASF2G72PZ-2G1A2 dev.jedec_dimm.0.serial: 0ea815de dev.jedec_dimm.0.slotid: A1 dev.jedec_dimm.0.temp: 32.7C dev.jedec_dimm.0.type: DDR4 dev.jedec_dimm.6.%desc: DDR4 DIMM w/ TSE2004av compliant TSOD dev.jedec_dimm.6.%driver: jedec_dimm dev.jedec_dimm.6.%location: addr=0xa8 dev.jedec_dimm.6.%parent: smbus1 dev.jedec_dimm.6.%pnpinfo: dev.jedec_dimm.6.capacity: 8192 dev.jedec_dimm.6.part: VRA9MR8B2H1603 dev.jedec_dimm.6.serial: 0c4c46ad dev.jedec_dimm.6.temp: 43.1C dev.jedec_dimm.6.type: DDR4 .Ed .Sh COMPATIBILITY .Nm implements a superset of the functionality of the now-deleted .Xr jedec_ts 4 . Hints for .Xr jedec_ts 4 can be mechanically converted for use with .Nm . Two changes are required: .Bl -enum .It In all .Xr jedec_ts 4 hints, replace .Dq jedec_ts with .Dq jedec_dimm .It In .Xr jedec_ts 4 .Dq addr hints, replace the TSOD DTI .Dq 0x3 with the SPD DTI .Dq 0xa .El .Pp The following .Xr sed 1 script will perform the necessary changes: .Bd -literal -offset indent sed -i ".old" -e 's/jedec_ts/jedec_dimm/' \\ -e '/jedec_dimm/s/addr="0x3/addr="0xa/' /boot/device.hints .Ed .Sh SEE ALSO .Xr iicbus 4 , .Xr iicsmb 4 , .Xr smbus 4 , .Xr sysctl 8 .Sh STANDARDS .Rs (DDR3 SPD) .%A JEDEC .%T Standard 21-C, Annex K .Re .Pp .Rs (DDR3 TSOD) .%A JEDEC .%T Standard 21-C, TSE2002av .Re .Pp .Rs (DDR4 SPD) .%A JEDEC .%T Standard 21-C, Annex L .Re .Pp .Rs (DDR4 TSOD) .%A JEDEC .%T Standard 21-C, TSE2004av .Re .Sh HISTORY The .Nm driver first appeared in .Fx 12.0 . .Sh AUTHORS .An -nosplit The .Nm driver and this manual page were written by .An Ravi Pokala Aq Mt rpokala@freebsd.org . They are both based in part on the now-deleted .Xr jedec_ts 4 driver and manual page, written by .An Andriy Gapon Aq Mt avg@FreeBSD.org . Index: head/sys/dev/imcsmb/imcsmb.c =================================================================== --- head/sys/dev/imcsmb/imcsmb.c (revision 343582) +++ head/sys/dev/imcsmb/imcsmb.c (revision 343583) @@ -1,557 +1,556 @@ /*- * SPDX-License-Identifier: BSD-2-Clause-FreeBSD * * Authors: Joe Kloss; Ravi Pokala (rpokala@freebsd.org) * * Copyright (c) 2017-2018 Panasas - * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. * * $FreeBSD$ */ /* A detailed description of this device is present in imcsmb_pci.c */ #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include "imcsmb_reg.h" #include "imcsmb_var.h" /* Device methods */ static int imcsmb_attach(device_t dev); static int imcsmb_detach(device_t dev); static int imcsmb_probe(device_t dev); /* SMBus methods */ static int imcsmb_callback(device_t dev, int index, void *data); static int imcsmb_readb(device_t dev, u_char slave, char cmd, char *byte); static int imcsmb_readw(device_t dev, u_char slave, char cmd, short *word); static int imcsmb_writeb(device_t dev, u_char slave, char cmd, char byte); static int imcsmb_writew(device_t dev, u_char slave, char cmd, short word); /* All the read/write methods wrap around this. */ static int imcsmb_transfer(device_t dev, u_char slave, char cmd, void *data, int word_op, int write_op); /** * device_attach() method. Set up the softc, including getting the set of the * parent imcsmb_pci's registers that we will use. Create the smbus(4) device, * which any SMBus slave device drivers will connect to. * * @author rpokala * * @param[in,out] dev * Device being attached. */ static int imcsmb_attach(device_t dev) { struct imcsmb_softc *sc; int rc; /* Initialize private state */ sc = device_get_softc(dev); sc->dev = dev; sc->imcsmb_pci = device_get_parent(dev); sc->regs = device_get_ivars(dev); /* Create the smbus child */ sc->smbus = device_add_child(dev, "smbus", -1); if (sc->smbus == NULL) { /* Nothing has been allocated, so there's no cleanup. */ device_printf(dev, "Child smbus not added\n"); rc = ENXIO; goto out; } /* Attach the smbus child. */ if ((rc = bus_generic_attach(dev)) != 0) { device_printf(dev, "Failed to attach smbus: %d\n", rc); } out: return (rc); } /** * device_detach() method. attach() didn't do any allocations, so all that's * needed here is to free up any downstream drivers and children. * * @author Joe Kloss * * @param[in] dev * Device being detached. */ static int imcsmb_detach(device_t dev) { int rc; /* Detach any attached drivers */ rc = bus_generic_detach(dev); if (rc == 0) { /* Remove all children */ rc = device_delete_children(dev); } return (rc); } /** * device_probe() method. All the actual probing was done by the imcsmb_pci * parent, so just report success. * * @author Joe Kloss * * @param[in,out] dev * Device being probed. */ static int imcsmb_probe(device_t dev) { device_set_desc(dev, "iMC SMBus controller"); return (BUS_PROBE_DEFAULT); } /** * smbus_callback() method. Call the parent imcsmb_pci's request or release * function to quiesce / restart firmware tasks which might use the SMBus. * * @author rpokala * * @param[in] dev * Device being requested or released. * * @param[in] index * Either SMB_REQUEST_BUS or SMB_RELEASE_BUS. * * @param[in] data * Tell's the rest of the SMBus subsystem to allow or disallow waiting; * this driver only works with SMB_DONTWAIT. */ static int imcsmb_callback(device_t dev, int index, void *data) { struct imcsmb_softc *sc; int *how; int rc; sc = device_get_softc(dev); how = (int *) data; switch (index) { case SMB_REQUEST_BUS: { if (*how != SMB_DONTWAIT) { rc = EINVAL; goto out; } rc = imcsmb_pci_request_bus(sc->imcsmb_pci); break; } case SMB_RELEASE_BUS: imcsmb_pci_release_bus(sc->imcsmb_pci); rc = 0; break; default: rc = EINVAL; break; } out: return (rc); } /** * smbus_readb() method. Thin wrapper around imcsmb_transfer(). * * @author Joe Kloss * * @param[in] dev * * @param[in] slave * The SMBus address of the target device. * * @param[in] cmd * The SMBus command for the target device; this is the offset for SPDs, * or the register number for TSODs. * * @param[out] byte * The byte which was read. */ static int imcsmb_readb(device_t dev, u_char slave, char cmd, char *byte) { return (imcsmb_transfer(dev, slave, cmd, byte, FALSE, FALSE)); } /** * smbus_readw() method. Thin wrapper around imcsmb_transfer(). * * @author Joe Kloss * * @param[in] dev * * @param[in] slave * The SMBus address of the target device. * * @param[in] cmd * The SMBus command for the target device; this is the offset for SPDs, * or the register number for TSODs. * * @param[out] word * The word which was read. */ static int imcsmb_readw(device_t dev, u_char slave, char cmd, short *word) { return (imcsmb_transfer(dev, slave, cmd, word, TRUE, FALSE)); } /** * smbus_writeb() method. Thin wrapper around imcsmb_transfer(). * * @author Joe Kloss * * @param[in] dev * * @param[in] slave * The SMBus address of the target device. * * @param[in] cmd * The SMBus command for the target device; this is the offset for SPDs, * or the register number for TSODs. * * @param[in] byte * The byte to write. */ static int imcsmb_writeb(device_t dev, u_char slave, char cmd, char byte) { return (imcsmb_transfer(dev, slave, cmd, &byte, FALSE, TRUE)); } /** * smbus_writew() method. Thin wrapper around imcsmb_transfer(). * * @author Joe Kloss * * @param[in] dev * * @param[in] slave * The SMBus address of the target device. * * @param[in] cmd * The SMBus command for the target device; this is the offset for SPDs, * or the register number for TSODs. * * @param[in] word * The word to write. */ static int imcsmb_writew(device_t dev, u_char slave, char cmd, short word) { return (imcsmb_transfer(dev, slave, cmd, &word, TRUE, TRUE)); } /** * Manipulate the PCI control registers to read data from or write data to the * SMBus controller. * * @author Joe Kloss, rpokala * * @param[in] dev * * @param[in] slave * The SMBus address of the target device. * * @param[in] cmd * The SMBus command for the target device; this is the offset for SPDs, * or the register number for TSODs. * * @param[in,out] data * Pointer to either the value to be written, or where to place the value * which was read. * * @param[in] word_op * Bool: is this a word operation? * * @param[in] write_op * Bool: is this a write operation? */ static int imcsmb_transfer(device_t dev, u_char slave, char cmd, void *data, int word_op, int write_op) { struct imcsmb_softc *sc; int i; int rc; uint32_t cmd_val; uint32_t cntl_val; uint32_t orig_cntl_val; uint32_t stat_val; uint16_t *word; uint16_t lword; uint8_t *byte; uint8_t lbyte; sc = device_get_softc(dev); byte = data; word = data; lbyte = *byte; lword = *word; /* We modify the value of the control register; save the original, so * we can restore it later */ orig_cntl_val = pci_read_config(sc->imcsmb_pci, sc->regs->smb_cntl, 4); cntl_val = orig_cntl_val; /* * Set up the SMBCNTL register */ /* [31:28] Clear the existing value of the DTI bits, then set them to * the four high bits of the slave address. */ cntl_val &= ~IMCSMB_CNTL_DTI_MASK; cntl_val |= ((uint32_t) slave & 0xf0) << 24; /* [27:27] Set the CLK_OVERRIDE bit, to enable normal operation */ cntl_val |= IMCSMB_CNTL_CLK_OVERRIDE; /* [26:26] Clear the WRITE_DISABLE bit; the datasheet says this isn't * necessary, but empirically, it is. */ cntl_val &= ~IMCSMB_CNTL_WRITE_DISABLE_BIT; /* [9:9] Clear the POLL_EN bit, to stop the hardware TSOD polling. */ cntl_val &= ~IMCSMB_CNTL_POLL_EN; /* * Set up the SMBCMD register */ /* [31:31] Set the TRIGGER bit; when this gets written, the controller * will issue the command. */ cmd_val = IMCSMB_CMD_TRIGGER_BIT; /* [29:29] For word operations, set the WORD_ACCESS bit. */ if (word_op) { cmd_val |= IMCSMB_CMD_WORD_ACCESS; } /* [27:27] For write operations, set the WRITE bit. */ if (write_op) { cmd_val |= IMCSMB_CMD_WRITE_BIT; } /* [26:24] The three non-DTI, non-R/W bits of the slave address. */ cmd_val |= (uint32_t) ((slave & 0xe) << 23); /* [23:16] The command (offset in the case of an EEPROM, or register in * the case of TSOD or NVDIMM controller). */ cmd_val |= (uint32_t) ((uint8_t) cmd << 16); /* [15:0] The data to be written for a write operation. */ if (write_op) { if (word_op) { /* The datasheet says the controller uses different * endianness for word operations on I2C vs SMBus! * I2C: [15:8] = MSB; [7:0] = LSB * SMB: [15:8] = LSB; [7:0] = MSB * As a practical matter, this controller is very * specifically for use with DIMMs, the SPD (and * NVDIMM controllers) are only accessed as bytes, * the temperature sensor is only accessed as words, and * the temperature sensors are I2C. Thus, byte-swap the * word. */ lword = htobe16(lword); } else { /* For byte operations, the data goes in the LSB, and * the MSB is a don't care. */ lword = (uint16_t) (lbyte & 0xff); } cmd_val |= lword; } /* Write the updated value to the control register first, to disable * the hardware TSOD polling. */ pci_write_config(sc->imcsmb_pci, sc->regs->smb_cntl, cntl_val, 4); /* Poll on the BUSY bit in the status register until clear, or timeout. * We just cleared the auto-poll bit, so we need to make sure the device * is idle before issuing a command. We can safely timeout after 35 ms, * as this is the maximum time the SMBus spec allows for a transaction. */ for (i = 4; i != 0; i--) { stat_val = pci_read_config(sc->imcsmb_pci, sc->regs->smb_stat, 4); if ((stat_val & IMCSMB_STATUS_BUSY_BIT) == 0) { break; } pause("imcsmb", 10 * hz / 1000); } if (i == 0) { device_printf(sc->dev, "transfer: timeout waiting for device to settle\n"); } /* Now that polling has stopped, we can write the command register. This * starts the SMBus command. */ pci_write_config(sc->imcsmb_pci, sc->regs->smb_cmd, cmd_val, 4); /* Wait for WRITE_DATA_DONE/READ_DATA_VALID to be set, or timeout and * fail. We wait up to 35ms. */ for (i = 35000; i != 0; i -= 10) { DELAY(10); stat_val = pci_read_config(sc->imcsmb_pci, sc->regs->smb_stat, 4); /* For a write, the bits holding the data contain the data being * written. You'd think that would cause the READ_DATA_VALID bit * to be cleared, because the data bits no longer contain valid * data from the most recent read operation. While that would be * logical, that's not the case here: READ_DATA_VALID is only * cleared when starting a read operation, and WRITE_DATA_DONE * is only cleared when starting a write operation. */ if (write_op) { if ((stat_val & IMCSMB_STATUS_WRITE_DATA_DONE) != 0) { break; } } else { if ((stat_val & IMCSMB_STATUS_READ_DATA_VALID) != 0) { break; } } } if (i == 0) { rc = SMB_ETIMEOUT; device_printf(dev, "transfer timeout\n"); goto out; } /* It is generally the case that this bit indicates non-ACK, but it * could also indicate other bus errors. There's no way to tell the * difference. */ if ((stat_val & IMCSMB_STATUS_BUS_ERROR_BIT) != 0) { /* While it is not documented, empirically, SPD page-change * commands (writes with DTI = 0x60) always complete with the * error bit set. So, ignore it in those cases. */ if ((slave & 0xf0) != 0x60) { rc = SMB_ENOACK; goto out; } } /* For a read operation, copy the data out */ if (write_op == 0) { if (word_op) { /* The data is returned in bits [15:0]; as discussed * above, byte-swap. */ lword = (uint16_t) (stat_val & 0xffff); lword = htobe16(lword); *word = lword; } else { /* The data is returned in bits [7:0] */ lbyte = (uint8_t) (stat_val & 0xff); *byte = lbyte; } } /* A lack of an error is, de facto, success. */ rc = SMB_ENOERR; out: /* Restore the original value of the control register. */ pci_write_config(sc->imcsmb_pci, sc->regs->smb_cntl, orig_cntl_val, 4); return (rc); } /* Our device class */ static devclass_t imcsmb_devclass; /* Device methods */ static device_method_t imcsmb_methods[] = { /* Device interface */ DEVMETHOD(device_attach, imcsmb_attach), DEVMETHOD(device_detach, imcsmb_detach), DEVMETHOD(device_probe, imcsmb_probe), /* smbus methods */ DEVMETHOD(smbus_callback, imcsmb_callback), DEVMETHOD(smbus_readb, imcsmb_readb), DEVMETHOD(smbus_readw, imcsmb_readw), DEVMETHOD(smbus_writeb, imcsmb_writeb), DEVMETHOD(smbus_writew, imcsmb_writew), DEVMETHOD_END }; static driver_t imcsmb_driver = { .name = "imcsmb", .methods = imcsmb_methods, .size = sizeof(struct imcsmb_softc), }; DRIVER_MODULE(imcsmb, imcsmb_pci, imcsmb_driver, imcsmb_devclass, 0, 0); MODULE_DEPEND(imcsmb, smbus, SMBUS_MINVER, SMBUS_PREFVER, SMBUS_MAXVER); MODULE_VERSION(imcsmb, 1); DRIVER_MODULE(smbus, imcsmb, smbus_driver, smbus_devclass, 0, 0); /* vi: set ts=8 sw=4 sts=8 noet: */ Index: head/sys/dev/imcsmb/imcsmb_pci.c =================================================================== --- head/sys/dev/imcsmb/imcsmb_pci.c (revision 343582) +++ head/sys/dev/imcsmb/imcsmb_pci.c (revision 343583) @@ -1,345 +1,344 @@ /*- * SPDX-License-Identifier: BSD-2-Clause-FreeBSD * * Authors: Joe Kloss; Ravi Pokala (rpokala@freebsd.org) * * Copyright (c) 2017-2018 Panasas - * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. * * $FreeBSD$ */ #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include "imcsmb_reg.h" #include "imcsmb_var.h" /* (Sandy,Ivy)bridge-Xeon and (Has,Broad)well-Xeon CPUs contain one or two * "Integrated Memory Controllers" (iMCs), and each iMC contains two separate * SMBus controllers. These are used for reading SPD data from the DIMMs, and * for reading the "Thermal Sensor on DIMM" (TSODs). The iMC SMBus controllers * are very simple devices, and have limited functionality compared to * full-fledged SMBus controllers, like the one in Intel ICHs and PCHs. * * The publicly available documentation for the iMC SMBus controllers can be * found in the CPU datasheets for (Sandy,Ivy)bridge-Xeon and * (Has,broad)well-Xeon, respectively: * * https://www.intel.com/content/dam/www/public/us/en/documents/datasheets/ * Sandybridge xeon-e5-1600-2600-vol-2-datasheet.pdf * Ivybridge xeon-e5-v2-datasheet-vol-2.pdf * Haswell xeon-e5-v3-datasheet-vol-2.pdf * Broadwell xeon-e5-v4-datasheet-vol-2.pdf * * Another useful resource is the Linux driver. It is not in the main tree. * * https://www.mail-archive.com/linux-kernel@vger.kernel.org/msg840043.html * * The iMC SMBus controllers do not support interrupts (thus, they must be * polled for IO completion). All of the iMC registers are in PCI configuration * space; there is no support for PIO or MMIO. As a result, this driver does * not need to perform and newbus resource manipulation. * * Because there are multiple SMBus controllers sharing the same PCI device, * this driver is actually *two* drivers: * * - "imcsmb" is an smbus(4)-compliant SMBus controller driver * * - "imcsmb_pci" recognizes the PCI device and assigns the appropriate set of * PCI config registers to a specific "imcsmb" instance. */ /* Depending on the motherboard and firmware, the TSODs might be polled by * firmware. Therefore, when this driver accesses these SMBus controllers, the * firmware polling must be disabled as part of requesting the bus, and * re-enabled when releasing the bus. Unfortunately, the details of how to do * this are vendor-specific. Contact your motherboard vendor to get the * information you need to do proper implementations. * * For NVDIMMs which conform to the ACPI "NFIT" standard, the ACPI firmware * manages the NVDIMM; for those which pre-date the standard, the operating * system interacts with the NVDIMM controller using a vendor-proprietary API * over the SMBus. In that case, the NVDIMM driver would be an SMBus slave * device driver, and would interface with the hardware via an SMBus controller * driver such as this one. */ /* PCIe device IDs for (Sandy,Ivy)bridge)-Xeon and (Has,Broad)well-Xeon */ #define PCI_VENDOR_INTEL 0x8086 #define IMCSMB_PCI_DEV_ID_IMC0_SBX 0x3ca8 #define IMCSMB_PCI_DEV_ID_IMC0_IBX 0x0ea8 #define IMCSMB_PCI_DEV_ID_IMC0_HSX 0x2fa8 #define IMCSMB_PCI_DEV_ID_IMC0_BDX 0x6fa8 /* (Sandy,Ivy)bridge-Xeon only have a single memory controller per socket */ #define IMCSMB_PCI_DEV_ID_IMC1_HSX 0x2f68 #define IMCSMB_PCI_DEV_ID_IMC1_BDX 0x6f68 /* There are two SMBus controllers in each device. These define the registers * for each of these devices. */ static struct imcsmb_reg_set imcsmb_regs[] = { { .smb_stat = IMCSMB_REG_STATUS0, .smb_cmd = IMCSMB_REG_COMMAND0, .smb_cntl = IMCSMB_REG_CONTROL0 }, { .smb_stat = IMCSMB_REG_STATUS1, .smb_cmd = IMCSMB_REG_COMMAND1, .smb_cntl = IMCSMB_REG_CONTROL1 }, }; static struct imcsmb_pci_device { uint16_t id; char *name; } imcsmb_pci_devices[] = { {IMCSMB_PCI_DEV_ID_IMC0_SBX, "Intel Sandybridge Xeon iMC 0 SMBus controllers" }, {IMCSMB_PCI_DEV_ID_IMC0_IBX, "Intel Ivybridge Xeon iMC 0 SMBus controllers" }, {IMCSMB_PCI_DEV_ID_IMC0_HSX, "Intel Haswell Xeon iMC 0 SMBus controllers" }, {IMCSMB_PCI_DEV_ID_IMC1_HSX, "Intel Haswell Xeon iMC 1 SMBus controllers" }, {IMCSMB_PCI_DEV_ID_IMC0_BDX, "Intel Broadwell Xeon iMC 0 SMBus controllers" }, {IMCSMB_PCI_DEV_ID_IMC1_BDX, "Intel Broadwell Xeon iMC 1 SMBus controllers" }, {0, NULL}, }; /* Device methods. */ static int imcsmb_pci_attach(device_t dev); static int imcsmb_pci_detach(device_t dev); static int imcsmb_pci_probe(device_t dev); /** * device_attach() method. Set up the PCI device's softc, then explicitly create * children for the actual imcsmbX controllers. Set up the child's ivars to * point to the proper set of the PCI device's config registers. * * @author Joe Kloss, rpokala * * @param[in,out] dev * Device being attached. */ static int imcsmb_pci_attach(device_t dev) { struct imcsmb_pci_softc *sc; device_t child; int rc; int unit; /* Initialize private state */ sc = device_get_softc(dev); sc->dev = dev; sc->semaphore = 0; /* Create the imcsmbX children */ for (unit = 0; unit < 2; unit++) { child = device_add_child(dev, "imcsmb", -1); if (child == NULL) { /* Nothing has been allocated, so there's no cleanup. */ device_printf(dev, "Child imcsmb not added\n"); rc = ENXIO; goto out; } /* Set the child's ivars to point to the appropriate set of * the PCI device's registers. */ device_set_ivars(child, &imcsmb_regs[unit]); } /* Attach the imcsmbX children. */ if ((rc = bus_generic_attach(dev)) != 0) { device_printf(dev, "failed to attach children: %d\n", rc); goto out; } out: return (rc); } /** * device_detach() method. attach() didn't do any allocations, so all that's * needed here is to free up any downstream drivers and children. * * @author Joe Kloss * * @param[in] dev * Device being detached. */ static int imcsmb_pci_detach(device_t dev) { int rc; /* Detach any attached drivers */ rc = bus_generic_detach(dev); if (rc == 0) { /* Remove all children */ rc = device_delete_children(dev); } return (rc); } /** * device_probe() method. Look for the right PCI vendor/device IDs. * * @author Joe Kloss, rpokala * * @param[in,out] dev * Device being probed. */ static int imcsmb_pci_probe(device_t dev) { struct imcsmb_pci_device *pci_device; int rc; uint16_t pci_dev_id; rc = ENXIO; if (pci_get_vendor(dev) != PCI_VENDOR_INTEL) { goto out; } pci_dev_id = pci_get_device(dev); for (pci_device = imcsmb_pci_devices; pci_device->name != NULL; pci_device++) { if (pci_dev_id == pci_device->id) { device_set_desc(dev, pci_device->name); rc = BUS_PROBE_DEFAULT; goto out; } } out: return (rc); } /** * Invoked via smbus_callback() -> imcsmb_callback(); clear the semaphore, and * re-enable motherboard-specific DIMM temperature monitoring if needed. This * gets called after the transaction completes. * * @author Joe Kloss * * @param[in,out] dev * The device whose busses to release. */ void imcsmb_pci_release_bus(device_t dev) { struct imcsmb_pci_softc *sc; sc = device_get_softc(dev); /* * IF NEEDED, INSERT MOTHERBOARD-SPECIFIC CODE TO RE-ENABLE DIMM * TEMPERATURE MONITORING HERE. */ atomic_store_rel_int(&sc->semaphore, 0); } /** * Invoked via smbus_callback() -> imcsmb_callback(); set the semaphore, and * disable motherboard-specific DIMM temperature monitoring if needed. This gets * called before the transaction starts. * * @author Joe Kloss * * @param[in,out] dev * The device whose busses to request. */ int imcsmb_pci_request_bus(device_t dev) { struct imcsmb_pci_softc *sc; int rc; sc = device_get_softc(dev); rc = 0; /* We don't want to block. Use a simple test-and-set semaphore to * protect the bus. */ if (atomic_cmpset_acq_int(&sc->semaphore, 0, 1) == 0) { rc = EWOULDBLOCK; } /* * IF NEEDED, INSERT MOTHERBOARD-SPECIFIC CODE TO DISABLE DIMM * TEMPERATURE MONITORING HERE. */ return (rc); } /* Our device class */ static devclass_t imcsmb_pci_devclass; /* Device methods */ static device_method_t imcsmb_pci_methods[] = { /* Device interface */ DEVMETHOD(device_attach, imcsmb_pci_attach), DEVMETHOD(device_detach, imcsmb_pci_detach), DEVMETHOD(device_probe, imcsmb_pci_probe), DEVMETHOD_END }; static driver_t imcsmb_pci_driver = { .name = "imcsmb_pci", .methods = imcsmb_pci_methods, .size = sizeof(struct imcsmb_pci_softc), }; DRIVER_MODULE(imcsmb_pci, pci, imcsmb_pci_driver, imcsmb_pci_devclass, 0, 0); MODULE_DEPEND(imcsmb_pci, pci, 1, 1, 1); MODULE_VERSION(imcsmb_pci, 1); /* vi: set ts=8 sw=4 sts=8 noet: */ Index: head/sys/dev/imcsmb/imcsmb_reg.h =================================================================== --- head/sys/dev/imcsmb/imcsmb_reg.h (revision 343582) +++ head/sys/dev/imcsmb/imcsmb_reg.h (revision 343583) @@ -1,86 +1,85 @@ /*- * SPDX-License-Identifier: BSD-2-Clause-FreeBSD * * Authors: Joe Kloss; Ravi Pokala (rpokala@freebsd.org) * * Copyright (c) 2017-2018 Panasas - * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. * * $FreeBSD$ */ #ifndef _DEV__IMCSMB__IMCSMB_REG_H_ #define _DEV__IMCSMB__IMCSMB_REG_H_ #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include /* Intel (Sandy,Ivy)bridge and (Has,Broad)well CPUs have integrated memory * controllers (iMCs), each of which having up to two SMBus controllers. They * are programmed via sets of registers in the same PCI device, which are * identical other than the register numbers. * * The full documentation for these registers can be found in volume two of the * datasheets for the CPUs. Refer to the links in imcsmb_pci.c */ #define IMCSMB_REG_STATUS0 0x0180 #define IMCSMB_REG_STATUS1 0x0190 #define IMCSMB_STATUS_BUSY_BIT 0x10000000 #define IMCSMB_STATUS_BUS_ERROR_BIT 0x20000000 #define IMCSMB_STATUS_WRITE_DATA_DONE 0x40000000 #define IMCSMB_STATUS_READ_DATA_VALID 0x80000000 #define IMCSMB_REG_COMMAND0 0x0184 #define IMCSMB_REG_COMMAND1 0x0194 #define IMCSMB_CMD_WORD_ACCESS 0x20000000 #define IMCSMB_CMD_WRITE_BIT 0x08000000 #define IMCSMB_CMD_TRIGGER_BIT 0x80000000 #define IMCSMB_REG_CONTROL0 0x0188 #define IMCSMB_REG_CONTROL1 0x0198 #define IMCSMB_CNTL_POLL_EN 0x00000100 #define IMCSMB_CNTL_CLK_OVERRIDE 0x08000000 #define IMCSMB_CNTL_DTI_MASK 0xf0000000 #define IMCSMB_CNTL_WRITE_DISABLE_BIT 0x04000000 #endif /* _DEV__IMCSMB__IMCSMB_REG_H_ */ /* vi: set ts=8 sw=4 sts=8 noet: */ Index: head/sys/dev/imcsmb/imcsmb_var.h =================================================================== --- head/sys/dev/imcsmb/imcsmb_var.h (revision 343582) +++ head/sys/dev/imcsmb/imcsmb_var.h (revision 343583) @@ -1,107 +1,106 @@ /*- * SPDX-License-Identifier: BSD-2-Clause-FreeBSD * * Authors: Joe Kloss; Ravi Pokala (rpokala@freebsd.org) * * Copyright (c) 2017-2018 Panasas - * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. * * $FreeBSD$ */ #ifndef _DEV__IMCSMB__IMCSMB_VAR_H_ #define _DEV__IMCSMB__IMCSMB_VAR_H_ #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include "smbus_if.h" /* A detailed description of this device is present in imcsmb_pci.c */ /** * The softc for a particular instance of the PCI device associated with a pair * of iMC-SMB controllers. * * Ordinarily, locking would be done with a mutex. However, we might have an * NVDIMM connected to this SMBus, and we might need to issue the SAVE command * to the NVDIMM from a panic context. Mutex operations are not allowed while * the scheduler is stopped, so just use a simple semaphore. * * If, as described in the manpage, additional steps are needed to stop/restart * firmware operations before/after using the controller, then additional fields * can be added to this softc. */ struct imcsmb_pci_softc { device_t dev; volatile int semaphore; }; void imcsmb_pci_release_bus(device_t dev); int imcsmb_pci_request_bus(device_t dev); /** * PCI config registers for each individual SMBus controller within the iMC. * Each iMC-SMB has a separate set of registers. There is an array of these * structures for the PCI device, and one of them is passed to driver for the * actual iMC-SMB as the IVAR. */ struct imcsmb_reg_set { uint16_t smb_stat; uint16_t smb_cmd; uint16_t smb_cntl; }; /** * The softc for the device associated with a particular iMC-SMB controller. * There are two such controllers for each of the PCI devices. The PCI driver * tells the iMC-SMB driver which set of registers to use via the IVAR. This * technique was suggested by John Baldwin (jhb@). */ struct imcsmb_softc { device_t dev; device_t imcsmb_pci; /* The SMBus controller's parent iMC */ device_t smbus; /* The child smbusX interface */ struct imcsmb_reg_set *regs; /* The registers this controller uses */ }; #endif /* _DEV__IMCSMB__IMCSMB_VAR_H_ */ /* vi: set ts=8 sw=4 sts=8 noet: */ Index: head/sys/dev/jedec_dimm/jedec_dimm.c =================================================================== --- head/sys/dev/jedec_dimm/jedec_dimm.c (revision 343582) +++ head/sys/dev/jedec_dimm/jedec_dimm.c (revision 343583) @@ -1,1007 +1,1006 @@ /*- * SPDX-License-Identifier: BSD-2-Clause-FreeBSD * * Authors: Ravi Pokala (rpokala@freebsd.org), Andriy Gapon (avg@FreeBSD.org) * * Copyright (c) 2016 Andriy Gapon * Copyright (c) 2018 Panasas - * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. * * $FreeBSD$ */ /* * This driver is a super-set of the now-deleted jedec_ts(4), and most of the * code for reading and reporting the temperature is either based on that driver, * or copied from it verbatim. */ #include #include #include #include #include #include #include #include #include #include #include #include "smbus_if.h" struct jedec_dimm_softc { device_t dev; device_t smbus; uint8_t spd_addr; /* SMBus address of the SPD EEPROM. */ uint8_t tsod_addr; /* Address of the Thermal Sensor On DIMM */ uint32_t capacity_mb; char type_str[5]; char part_str[21]; /* 18 (DDR3) or 20 (DDR4) chars, plus terminator */ char serial_str[9]; /* 4 bytes = 8 nybble characters, plus terminator */ char *slotid_str; /* Optional DIMM slot identifier (silkscreen) */ }; /* General Thermal Sensor on DIMM (TSOD) identification notes. * * The JEDEC TSE2004av specification defines the device ID that all compliant * devices should use, but very few do in practice. Maybe that's because the * earlier TSE2002av specification was rather vague about that. * Rare examples are IDT TSE2004GB2B0 and Atmel AT30TSE004A, not sure if * they are TSE2004av compliant by design or by accident. * Also, the specification mandates that PCI SIG manufacturer IDs are to be * used, but in practice the JEDEC manufacturer IDs are often used. */ const struct jedec_dimm_tsod_dev { uint16_t vendor_id; uint8_t device_id; const char *description; } known_tsod_devices[] = { /* Analog Devices ADT7408. * http://www.analog.com/media/en/technical-documentation/data-sheets/ADT7408.pdf */ { 0x11d4, 0x08, "Analog Devices TSOD" }, /* Atmel AT30TSE002B, AT30TSE004A. * http://www.atmel.com/images/doc8711.pdf * http://www.atmel.com/images/atmel-8868-dts-at30tse004a-datasheet.pdf * Note how one chip uses the JEDEC Manufacturer ID while the other * uses the PCI SIG one. */ { 0x001f, 0x82, "Atmel TSOD" }, { 0x1114, 0x22, "Atmel TSOD" }, /* Integrated Device Technology (IDT) TS3000B3A, TSE2002B3C, * TSE2004GB2B0 chips and their variants. * http://www.idt.com/sites/default/files/documents/IDT_TSE2002B3C_DST_20100512_120303152056.pdf * http://www.idt.com/sites/default/files/documents/IDT_TS3000B3A_DST_20101129_120303152013.pdf * https://www.idt.com/document/dst/tse2004gb2b0-datasheet */ { 0x00b3, 0x29, "IDT TSOD" }, { 0x00b3, 0x22, "IDT TSOD" }, /* Maxim Integrated MAX6604. * Different document revisions specify different Device IDs. * Document 19-3837; Rev 0; 10/05 has 0x3e00 while * 19-3837; Rev 3; 10/11 has 0x5400. * http://datasheets.maximintegrated.com/en/ds/MAX6604.pdf */ { 0x004d, 0x3e, "Maxim Integrated TSOD" }, { 0x004d, 0x54, "Maxim Integrated TSOD" }, /* Microchip Technology MCP9805, MCP9843, MCP98242, MCP98243 * and their variants. * http://ww1.microchip.com/downloads/en/DeviceDoc/21977b.pdf * Microchip Technology EMC1501. * http://ww1.microchip.com/downloads/en/DeviceDoc/00001605A.pdf */ { 0x0054, 0x00, "Microchip TSOD" }, { 0x0054, 0x20, "Microchip TSOD" }, { 0x0054, 0x21, "Microchip TSOD" }, { 0x1055, 0x08, "Microchip TSOD" }, /* NXP Semiconductors SE97 and SE98. * http://www.nxp.com/docs/en/data-sheet/SE97B.pdf */ { 0x1131, 0xa1, "NXP TSOD" }, { 0x1131, 0xa2, "NXP TSOD" }, /* ON Semiconductor CAT34TS02 revisions B and C, CAT6095 and compatible. * https://www.onsemi.com/pub/Collateral/CAT34TS02-D.PDF * http://www.onsemi.com/pub/Collateral/CAT6095-D.PDF */ { 0x1b09, 0x08, "ON Semiconductor TSOD" }, { 0x1b09, 0x0a, "ON Semiconductor TSOD" }, /* ST[Microelectronics] STTS424E02, STTS2002 and others. * http://www.st.com/resource/en/datasheet/cd00157558.pdf * http://www.st.com/resource/en/datasheet/stts2002.pdf */ { 0x104a, 0x00, "ST Microelectronics TSOD" }, { 0x104a, 0x03, "ST Microelectronics TSOD" }, }; static int jedec_dimm_attach(device_t dev); static int jedec_dimm_capacity(struct jedec_dimm_softc *sc, enum dram_type type, uint32_t *capacity_mb); static int jedec_dimm_detach(device_t dev); static int jedec_dimm_dump(struct jedec_dimm_softc *sc, enum dram_type type); static int jedec_dimm_field_to_str(struct jedec_dimm_softc *sc, char *dst, size_t dstsz, uint16_t offset, uint16_t len, bool ascii); static int jedec_dimm_probe(device_t dev); static int jedec_dimm_readw_be(struct jedec_dimm_softc *sc, uint8_t reg, uint16_t *val); static int jedec_dimm_temp_sysctl(SYSCTL_HANDLER_ARGS); static const char *jedec_dimm_tsod_match(uint16_t vid, uint16_t did); /** * device_attach() method. Read the DRAM type, use that to determine the offsets * and lengths of the asset string fields. Calculate the capacity. If a TSOD is * present, figure out exactly what it is, and update the device description. * If all of that was successful, create the sysctls for the DIMM. If an * optional slotid has been hinted, create a sysctl for that too. * * @author rpokala * * @param[in,out] dev * Device being attached. */ static int jedec_dimm_attach(device_t dev) { uint8_t byte; uint16_t devid; uint16_t partnum_len; uint16_t partnum_offset; uint16_t serial_len; uint16_t serial_offset; uint16_t tsod_present_offset; uint16_t vendorid; bool tsod_present; int rc; int new_desc_len; enum dram_type type; struct jedec_dimm_softc *sc; struct sysctl_ctx_list *ctx; struct sysctl_oid *oid; struct sysctl_oid_list *children; const char *tsod_match; const char *slotid_str; char *new_desc; sc = device_get_softc(dev); ctx = device_get_sysctl_ctx(dev); oid = device_get_sysctl_tree(dev); children = SYSCTL_CHILDREN(oid); bzero(sc, sizeof(*sc)); sc->dev = dev; sc->smbus = device_get_parent(dev); sc->spd_addr = smbus_get_addr(dev); /* The TSOD address has a different DTI from the SPD address, but shares * the LSA bits. */ sc->tsod_addr = JEDEC_DTI_TSOD | (sc->spd_addr & 0x0f); /* Read the DRAM type, and set the various offsets and lengths. */ rc = smbus_readb(sc->smbus, sc->spd_addr, SPD_OFFSET_DRAM_TYPE, &byte); if (rc != 0) { device_printf(dev, "failed to read dram_type: %d\n", rc); goto out; } type = (enum dram_type) byte; switch (type) { case DRAM_TYPE_DDR3_SDRAM: (void) snprintf(sc->type_str, sizeof(sc->type_str), "DDR3"); partnum_len = SPD_LEN_DDR3_PARTNUM; partnum_offset = SPD_OFFSET_DDR3_PARTNUM; serial_len = SPD_LEN_DDR3_SERIAL; serial_offset = SPD_OFFSET_DDR3_SERIAL; tsod_present_offset = SPD_OFFSET_DDR3_TSOD_PRESENT; break; case DRAM_TYPE_DDR4_SDRAM: (void) snprintf(sc->type_str, sizeof(sc->type_str), "DDR4"); partnum_len = SPD_LEN_DDR4_PARTNUM; partnum_offset = SPD_OFFSET_DDR4_PARTNUM; serial_len = SPD_LEN_DDR4_SERIAL; serial_offset = SPD_OFFSET_DDR4_SERIAL; tsod_present_offset = SPD_OFFSET_DDR4_TSOD_PRESENT; break; default: device_printf(dev, "unsupported dram_type 0x%02x\n", type); rc = EINVAL; goto out; } if (bootverbose) { /* bootverbose debuggery is best-effort, so ignore the rc. */ (void) jedec_dimm_dump(sc, type); } /* Read all the required info from the SPD. If any of it fails, error * out without creating the sysctls. */ rc = jedec_dimm_capacity(sc, type, &sc->capacity_mb); if (rc != 0) { goto out; } rc = jedec_dimm_field_to_str(sc, sc->part_str, sizeof(sc->part_str), partnum_offset, partnum_len, true); if (rc != 0) { goto out; } rc = jedec_dimm_field_to_str(sc, sc->serial_str, sizeof(sc->serial_str), serial_offset, serial_len, false); if (rc != 0) { goto out; } /* The MSBit of the TSOD-presence byte reports whether or not the TSOD * is in fact present. If it is, read manufacturer and device info from * it to confirm that it's a valid TSOD device. It's an error if any of * those bytes are unreadable; it's not an error if the device is simply * not known to us (tsod_match == NULL). * While DDR3 and DDR4 don't explicitly require a TSOD, essentially all * DDR3 and DDR4 DIMMs include one. */ rc = smbus_readb(sc->smbus, sc->spd_addr, tsod_present_offset, &byte); if (rc != 0) { device_printf(dev, "failed to read TSOD-present byte: %d\n", rc); goto out; } if (byte & 0x80) { tsod_present = true; rc = jedec_dimm_readw_be(sc, TSOD_REG_MANUFACTURER, &vendorid); if (rc != 0) { device_printf(dev, "failed to read TSOD Manufacturer ID\n"); goto out; } rc = jedec_dimm_readw_be(sc, TSOD_REG_DEV_REV, &devid); if (rc != 0) { device_printf(dev, "failed to read TSOD Device ID\n"); goto out; } tsod_match = jedec_dimm_tsod_match(vendorid, devid); if (bootverbose) { if (tsod_match == NULL) { device_printf(dev, "Unknown TSOD Manufacturer and Device IDs," " 0x%x and 0x%x\n", vendorid, devid); } else { device_printf(dev, "TSOD: %s\n", tsod_match); } } } else { tsod_match = NULL; tsod_present = false; } SYSCTL_ADD_STRING(ctx, children, OID_AUTO, "type", CTLFLAG_RD | CTLFLAG_MPSAFE, sc->type_str, 0, "DIMM type"); SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "capacity", CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, sc->capacity_mb, "DIMM capacity (MB)"); SYSCTL_ADD_STRING(ctx, children, OID_AUTO, "part", CTLFLAG_RD | CTLFLAG_MPSAFE, sc->part_str, 0, "DIMM Part Number"); SYSCTL_ADD_STRING(ctx, children, OID_AUTO, "serial", CTLFLAG_RD | CTLFLAG_MPSAFE, sc->serial_str, 0, "DIMM Serial Number"); /* Create the temperature sysctl IFF the TSOD is present and valid */ if (tsod_present && (tsod_match != NULL)) { SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "temp", CTLTYPE_INT | CTLFLAG_RD | CTLFLAG_MPSAFE, dev, 0, jedec_dimm_temp_sysctl, "IK", "DIMM temperature (deg C)"); } /* If a "slotid" was hinted, add the sysctl for it. */ if (resource_string_value(device_get_name(dev), device_get_unit(dev), "slotid", &slotid_str) == 0) { if (slotid_str != NULL) { sc->slotid_str = strdup(slotid_str, M_DEVBUF); SYSCTL_ADD_STRING(ctx, children, OID_AUTO, "slotid", CTLFLAG_RD | CTLFLAG_MPSAFE, sc->slotid_str, 0, "DIMM Slot Identifier"); } } /* If a TSOD type string or a slotid are present, add them to the * device description. */ if ((tsod_match != NULL) || (sc->slotid_str != NULL)) { new_desc_len = strlen(device_get_desc(dev)); if (tsod_match != NULL) { new_desc_len += strlen(tsod_match); new_desc_len += 4; /* " w/ " */ } if (sc->slotid_str != NULL) { new_desc_len += strlen(sc->slotid_str); new_desc_len += 3; /* space + parens */ } new_desc_len++; /* terminator */ new_desc = malloc(new_desc_len, M_TEMP, (M_WAITOK | M_ZERO)); (void) snprintf(new_desc, new_desc_len, "%s%s%s%s%s%s", device_get_desc(dev), (tsod_match ? " w/ " : ""), (tsod_match ? tsod_match : ""), (sc->slotid_str ? " (" : ""), (sc->slotid_str ? sc->slotid_str : ""), (sc->slotid_str ? ")" : "")); device_set_desc_copy(dev, new_desc); free(new_desc, M_TEMP); } out: return (rc); } /** * Calculate the capacity of a DIMM. Both DDR3 and DDR4 encode "geometry" * information in various SPD bytes. The standards documents codify everything * in look-up tables, but it's trivial to reverse-engineer the the formulas for * most of them. Unless otherwise noted, the same formulas apply for both DDR3 * and DDR4. The SPD offsets of where the data comes from are different between * the two types, because having them be the same would be too easy. * * @author rpokala * * @param[in] sc * Instance-specific context data * * @param[in] dram_type * The locations of the data used to calculate the capacity depends on the * type of the DIMM. * * @param[out] capacity_mb * The calculated capacity, in MB */ static int jedec_dimm_capacity(struct jedec_dimm_softc *sc, enum dram_type type, uint32_t *capacity_mb) { uint8_t bus_width_byte; uint8_t bus_width_offset; uint8_t dimm_ranks_byte; uint8_t dimm_ranks_offset; uint8_t sdram_capacity_byte; uint8_t sdram_capacity_offset; uint8_t sdram_pkg_type_byte; uint8_t sdram_pkg_type_offset; uint8_t sdram_width_byte; uint8_t sdram_width_offset; uint32_t bus_width; uint32_t dimm_ranks; uint32_t sdram_capacity; uint32_t sdram_pkg_type; uint32_t sdram_width; int rc; switch (type) { case DRAM_TYPE_DDR3_SDRAM: bus_width_offset = SPD_OFFSET_DDR3_BUS_WIDTH; dimm_ranks_offset = SPD_OFFSET_DDR3_DIMM_RANKS; sdram_capacity_offset = SPD_OFFSET_DDR3_SDRAM_CAPACITY; sdram_width_offset = SPD_OFFSET_DDR3_SDRAM_WIDTH; break; case DRAM_TYPE_DDR4_SDRAM: bus_width_offset = SPD_OFFSET_DDR4_BUS_WIDTH; dimm_ranks_offset = SPD_OFFSET_DDR4_DIMM_RANKS; sdram_capacity_offset = SPD_OFFSET_DDR4_SDRAM_CAPACITY; sdram_pkg_type_offset = SPD_OFFSET_DDR4_SDRAM_PKG_TYPE; sdram_width_offset = SPD_OFFSET_DDR4_SDRAM_WIDTH; break; default: device_printf(sc->dev, "unsupported dram_type 0x%02x\n", type); rc = EINVAL; goto out; } rc = smbus_readb(sc->smbus, sc->spd_addr, bus_width_offset, &bus_width_byte); if (rc != 0) { device_printf(sc->dev, "failed to read bus_width: %d\n", rc); goto out; } rc = smbus_readb(sc->smbus, sc->spd_addr, dimm_ranks_offset, &dimm_ranks_byte); if (rc != 0) { device_printf(sc->dev, "failed to read dimm_ranks: %d\n", rc); goto out; } rc = smbus_readb(sc->smbus, sc->spd_addr, sdram_capacity_offset, &sdram_capacity_byte); if (rc != 0) { device_printf(sc->dev, "failed to read sdram_capacity: %d\n", rc); goto out; } rc = smbus_readb(sc->smbus, sc->spd_addr, sdram_width_offset, &sdram_width_byte); if (rc != 0) { device_printf(sc->dev, "failed to read sdram_width: %d\n", rc); goto out; } /* The "SDRAM Package Type" is only needed for DDR4 DIMMs. */ if (type == DRAM_TYPE_DDR4_SDRAM) { rc = smbus_readb(sc->smbus, sc->spd_addr, sdram_pkg_type_offset, &sdram_pkg_type_byte); if (rc != 0) { device_printf(sc->dev, "failed to read sdram_pkg_type: %d\n", rc); goto out; } } /* "Primary bus width, in bits" is in bits [2:0]. */ bus_width_byte &= 0x07; if (bus_width_byte <= 3) { bus_width = 1 << bus_width_byte; bus_width *= 8; } else { device_printf(sc->dev, "invalid bus width info\n"); rc = EINVAL; goto out; } /* "Number of ranks per DIMM" is in bits [5:3]. Values 4-7 are only * valid for DDR4. */ dimm_ranks_byte >>= 3; dimm_ranks_byte &= 0x07; if (dimm_ranks_byte <= 7) { dimm_ranks = dimm_ranks_byte + 1; } else { device_printf(sc->dev, "invalid DIMM Rank info\n"); rc = EINVAL; goto out; } if ((dimm_ranks_byte >= 4) && (type != DRAM_TYPE_DDR4_SDRAM)) { device_printf(sc->dev, "invalid DIMM Rank info\n"); rc = EINVAL; goto out; } /* "Total SDRAM capacity per die, in Mb" is in bits [3:0]. There are two * different formulas, for values 0-7 and for values 8-9. Also, values * 7-9 are only valid for DDR4. */ sdram_capacity_byte &= 0x0f; if (sdram_capacity_byte <= 7) { sdram_capacity = 1 << sdram_capacity_byte; sdram_capacity *= 256; } else if (sdram_capacity_byte <= 9) { sdram_capacity = 12 << (sdram_capacity_byte - 8); sdram_capacity *= 1024; } else { device_printf(sc->dev, "invalid SDRAM capacity info\n"); rc = EINVAL; goto out; } if ((sdram_capacity_byte >= 7) && (type != DRAM_TYPE_DDR4_SDRAM)) { device_printf(sc->dev, "invalid SDRAM capacity info\n"); rc = EINVAL; goto out; } /* "SDRAM device width" is in bits [2:0]. */ sdram_width_byte &= 0x7; if (sdram_width_byte <= 3) { sdram_width = 1 << sdram_width_byte; sdram_width *= 4; } else { device_printf(sc->dev, "invalid SDRAM width info\n"); rc = EINVAL; goto out; } /* DDR4 has something called "3DS", which is indicated by [1:0] = 2; * when that is the case, the die count is encoded in [6:4], and * dimm_ranks is multiplied by it. */ if ((type == DRAM_TYPE_DDR4_SDRAM) && ((sdram_pkg_type_byte & 0x3) == 2)) { sdram_pkg_type_byte >>= 4; sdram_pkg_type_byte &= 0x07; sdram_pkg_type = sdram_pkg_type_byte + 1; dimm_ranks *= sdram_pkg_type; } /* Finally, assemble the actual capacity. The formula is the same for * both DDR3 and DDR4. */ *capacity_mb = sdram_capacity / 8 * bus_width / sdram_width * dimm_ranks; out: return (rc); } /** * device_detach() method. If we allocated sc->slotid_str, free it. Even if we * didn't allocate, free it anyway; free(NULL) is safe. * * @author rpokala * * @param[in,out] dev * Device being detached. */ static int jedec_dimm_detach(device_t dev) { struct jedec_dimm_softc *sc; sc = device_get_softc(dev); free(sc->slotid_str, M_DEVBUF); return (0); } /** * Read and dump the entire SPD contents. * * @author rpokala * * @param[in] sc * Instance-specific context data * * @param[in] dram_type * The length of data which needs to be read and dumped differs based on * the type of the DIMM. */ static int jedec_dimm_dump(struct jedec_dimm_softc *sc, enum dram_type type) { int i; int rc; bool page_changed; uint8_t bytes[512]; page_changed = false; for (i = 0; i < 256; i++) { rc = smbus_readb(sc->smbus, sc->spd_addr, i, &bytes[i]); if (rc != 0) { device_printf(sc->dev, "unable to read page0:0x%02x: %d\n", i, rc); goto out; } } /* The DDR4 SPD is 512 bytes, but SMBus only allows for 8-bit offsets. * JEDEC gets around this by defining the "PAGE" DTI and LSAs. */ if (type == DRAM_TYPE_DDR4_SDRAM) { page_changed = true; rc = smbus_writeb(sc->smbus, (JEDEC_DTI_PAGE | JEDEC_LSA_PAGE_SET1), 0, 0); if (rc != 0) { device_printf(sc->dev, "unable to change page: %d\n", rc); goto out; } /* Add 256 to the store location, because we're in the second * page. */ for (i = 0; i < 256; i++) { rc = smbus_readb(sc->smbus, sc->spd_addr, i, &bytes[256 + i]); if (rc != 0) { device_printf(sc->dev, "unable to read page1:0x%02x: %d\n", i, rc); goto out; } } } /* Display the data in a nice hexdump format, with byte offsets. */ hexdump(bytes, (page_changed ? 512 : 256), NULL, 0); out: if (page_changed) { int rc2; /* Switch back to page0 before returning. */ rc2 = smbus_writeb(sc->smbus, (JEDEC_DTI_PAGE | JEDEC_LSA_PAGE_SET0), 0, 0); if (rc2 != 0) { device_printf(sc->dev, "unable to restore page: %d\n", rc2); } } return (rc); } /** * Read a specified range of bytes from the SPD, convert them to a string, and * store them in the provided buffer. Some SPD fields are space-padded ASCII, * and some are just a string of bits that we want to convert to a hex string. * * @author rpokala * * @param[in] sc * Instance-specific context data * * @param[out] dst * The output buffer to populate * * @param[in] dstsz * The size of the output buffer * * @param[in] offset * The starting offset of the field within the SPD * * @param[in] len * The length in bytes of the field within the SPD * * @param[in] ascii * Is the field a sequence of ASCII characters? If not, it is binary data * which should be converted to characters. */ static int jedec_dimm_field_to_str(struct jedec_dimm_softc *sc, char *dst, size_t dstsz, uint16_t offset, uint16_t len, bool ascii) { uint8_t byte; int i; int rc; bool page_changed; /* Change to the proper page. Offsets [0, 255] are in page0; offsets * [256, 512] are in page1. * * *The page must be reset to page0 before returning.* * * For the page-change operation, only the DTI and LSA matter; the * offset and write-value are ignored, so use just 0. * * Mercifully, JEDEC defined the fields such that none of them cross * pages, so we don't need to worry about that complication. */ if (offset < JEDEC_SPD_PAGE_SIZE) { page_changed = false; } else if (offset < (2 * JEDEC_SPD_PAGE_SIZE)) { page_changed = true; rc = smbus_writeb(sc->smbus, (JEDEC_DTI_PAGE | JEDEC_LSA_PAGE_SET1), 0, 0); if (rc != 0) { device_printf(sc->dev, "unable to change page for offset 0x%04x: %d\n", offset, rc); } /* Adjust the offset to account for the page change. */ offset -= JEDEC_SPD_PAGE_SIZE; } else { page_changed = false; rc = EINVAL; device_printf(sc->dev, "invalid offset 0x%04x\n", offset); goto out; } /* Sanity-check (adjusted) offset and length; everything must be within * the same page. */ if (offset >= JEDEC_SPD_PAGE_SIZE) { rc = EINVAL; device_printf(sc->dev, "invalid offset 0x%04x\n", offset); goto out; } if ((offset + len) >= JEDEC_SPD_PAGE_SIZE) { rc = EINVAL; device_printf(sc->dev, "(offset + len) would cross page (0x%04x + 0x%04x)\n", offset, len); goto out; } /* Sanity-check the destination string length. If we're dealing with * ASCII chars, then the destination must be at least the same length; * otherwise, it must be *twice* the length, because each byte must * be converted into two nybble characters. * * And, of course, there needs to be an extra byte for the terminator. */ if (ascii) { if (dstsz < (len + 1)) { rc = EINVAL; device_printf(sc->dev, "destination too short (%u < %u)\n", (uint16_t) dstsz, (len + 1)); goto out; } } else { if (dstsz < ((2 * len) + 1)) { rc = EINVAL; device_printf(sc->dev, "destination too short (%u < %u)\n", (uint16_t) dstsz, ((2 * len) + 1)); goto out; } } /* Read a byte at a time. */ for (i = 0; i < len; i++) { rc = smbus_readb(sc->smbus, sc->spd_addr, (offset + i), &byte); if (rc != 0) { device_printf(sc->dev, "failed to read byte at 0x%02x: %d\n", (offset + i), rc); goto out; } if (ascii) { /* chars can be copied directly. */ dst[i] = byte; } else { /* Raw bytes need to be converted to a two-byte hex * string, plus the terminator. */ (void) snprintf(&dst[(2 * i)], 3, "%02x", byte); } } /* If we're dealing with ASCII, convert trailing spaces to NULs. */ if (ascii) { for (i = dstsz; i > 0; i--) { if (dst[i] == ' ') { dst[i] = 0; } else if (dst[i] == 0) { continue; } else { break; } } } out: if (page_changed) { int rc2; /* Switch back to page0 before returning. */ rc2 = smbus_writeb(sc->smbus, (JEDEC_DTI_PAGE | JEDEC_LSA_PAGE_SET0), 0, 0); if (rc2 != 0) { device_printf(sc->dev, "unable to restore page for offset 0x%04x: %d\n", offset, rc2); } } return (rc); } /** * device_probe() method. Validate the address that was given as a hint, and * display an error if it's bogus. Make sure that we're dealing with one of the * SPD versions that we can handle. * * @author rpokala * * @param[in] dev * Device being probed. */ static int jedec_dimm_probe(device_t dev) { uint8_t addr; uint8_t byte; int rc; enum dram_type type; device_t smbus; smbus = device_get_parent(dev); addr = smbus_get_addr(dev); /* Don't bother if this isn't an SPD address, or if the LSBit is set. */ if (((addr & 0xf0) != JEDEC_DTI_SPD) || ((addr & 0x01) != 0)) { device_printf(dev, "invalid \"addr\" hint; address must start with \"0x%x\"," " and the least-significant bit must be 0\n", JEDEC_DTI_SPD); rc = ENXIO; goto out; } /* Try to read the DRAM_TYPE from the SPD. */ rc = smbus_readb(smbus, addr, SPD_OFFSET_DRAM_TYPE, &byte); if (rc != 0) { device_printf(dev, "failed to read dram_type\n"); goto out; } /* This driver currently only supports DDR3 and DDR4 SPDs. */ type = (enum dram_type) byte; switch (type) { case DRAM_TYPE_DDR3_SDRAM: rc = BUS_PROBE_DEFAULT; device_set_desc(dev, "DDR3 DIMM"); break; case DRAM_TYPE_DDR4_SDRAM: rc = BUS_PROBE_DEFAULT; device_set_desc(dev, "DDR4 DIMM"); break; default: rc = ENXIO; break; } out: return (rc); } /** * SMBus specifies little-endian byte order, but it looks like the TSODs use * big-endian. Read and convert. * * @author avg * * @param[in] sc * Instance-specific context data * * @param[in] reg * The register number to read. * * @param[out] val * Pointer to populate with the value read. */ static int jedec_dimm_readw_be(struct jedec_dimm_softc *sc, uint8_t reg, uint16_t *val) { int rc; rc = smbus_readw(sc->smbus, sc->tsod_addr, reg, val); if (rc != 0) { goto out; } *val = be16toh(*val); out: return (rc); } /** * Read the temperature data from the TSOD and convert it to the deciKelvin * value that the sysctl expects. * * @author avg */ static int jedec_dimm_temp_sysctl(SYSCTL_HANDLER_ARGS) { uint16_t val; int rc; int temp; device_t dev = arg1; struct jedec_dimm_softc *sc; sc = device_get_softc(dev); rc = jedec_dimm_readw_be(sc, TSOD_REG_TEMPERATURE, &val); if (rc != 0) { goto out; } /* The three MSBits are flags, and the next bit is a sign bit. */ temp = val & 0xfff; if ((val & 0x1000) != 0) temp = -temp; /* Each step is 0.0625 degrees, so convert to 1000ths of a degree C. */ temp *= 625; /* ... and then convert to 1000ths of a Kelvin */ temp += 2731500; /* As a practical matter, few (if any) TSODs are more accurate than * about a tenth of a degree, so round accordingly. This correlates with * the "IK" formatting used for this sysctl. */ temp = (temp + 500) / 1000; rc = sysctl_handle_int(oidp, &temp, 0, req); out: return (rc); } /** * Check the TSOD's Vendor ID and Device ID against the list of known TSOD * devices. Return the description, or NULL if this doesn't look like a valid * TSOD. * * @author avg * * @param[in] vid * The Vendor ID of the TSOD device * * @param[in] did * The Device ID of the TSOD device * * @return * The description string, or NULL for a failure to match. */ static const char * jedec_dimm_tsod_match(uint16_t vid, uint16_t did) { const struct jedec_dimm_tsod_dev *d; int i; for (i = 0; i < nitems(known_tsod_devices); i++) { d = &known_tsod_devices[i]; if ((vid == d->vendor_id) && ((did >> 8) == d->device_id)) { return (d->description); } } /* If no matches for a specific device, then check for a generic * TSE2004av-compliant device. */ if ((did >> 8) == 0x22) { return ("TSE2004av compliant TSOD"); } return (NULL); } static device_method_t jedec_dimm_methods[] = { /* Methods from the device interface */ DEVMETHOD(device_probe, jedec_dimm_probe), DEVMETHOD(device_attach, jedec_dimm_attach), DEVMETHOD(device_detach, jedec_dimm_detach), DEVMETHOD_END }; static driver_t jedec_dimm_driver = { .name = "jedec_dimm", .methods = jedec_dimm_methods, .size = sizeof(struct jedec_dimm_softc), }; static devclass_t jedec_dimm_devclass; DRIVER_MODULE(jedec_dimm, smbus, jedec_dimm_driver, jedec_dimm_devclass, 0, 0); MODULE_DEPEND(jedec_dimm, smbus, SMBUS_MINVER, SMBUS_PREFVER, SMBUS_MAXVER); MODULE_VERSION(jedec_dimm, 1); /* vi: set ts=8 sw=4 sts=8 noet: */ Index: head/sys/dev/jedec_dimm/jedec_dimm.h =================================================================== --- head/sys/dev/jedec_dimm/jedec_dimm.h (revision 343582) +++ head/sys/dev/jedec_dimm/jedec_dimm.h (revision 343583) @@ -1,147 +1,146 @@ /*- * SPDX-License-Identifier: BSD-2-Clause-FreeBSD * * Authors: Ravi Pokala (rpokala@freebsd.org) * * Copyright (c) 2018 Panasas - * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. * * $FreeBSD$ */ #ifndef _DEV__JEDEC_DIMM__JEDEC_DIMM_H_ #define _DEV__JEDEC_DIMM__JEDEC_DIMM_H_ /* JEDEC DIMMs include one or more SMBus devices. * * At a minimum, they have an EEPROM containing either 256 bytes (DDR3) or 512 * bytes (DDR4) of "Serial Presence Detect" (SPD) information. The SPD contains * data used by the memory controller to configure itself, and it also includes * asset information. The layout of SPD data is defined in: * * JEDEC Standard 21-C, Annex K (DDR3) * JEDEC Standard 21-C, Annex L (DDR4) * * DIMMs may also include a "Thermal Sensor on DIMM" (TSOD), which reports * temperature data. While not strictly required, the TSOD is so often included * that JEDEC defined standards for single chips which include both SPD and TSOD * functions. They respond on multiple SMBus addresses, depending on the * function. * * JEDEC Standard 21-C, TSE2002av (DDR3) * JEDEC Standard 21-C, TSE2004av (DDR4) */ /* TSE2004av defines several Device Type Identifiers (DTIs), which are the high * nybble of the SMBus address. Addresses with DTIs of PROTECT (or PAGE, which * has the same value) are essentially "broadcast" addresses; all SPD devices * respond to them, changing their mode based on the Logical Serial Address * (LSA) encoded in bits [3:1]. For normal SPD access, bits [3:1] encode the * DIMM slot number. */ #define JEDEC_SPD_PAGE_SIZE 256 #define JEDEC_DTI_SPD 0xa0 #define JEDEC_DTI_TSOD 0x30 #define JEDEC_DTI_PROTECT 0x60 #define JEDEC_LSA_PROTECT_SET0 0x02 #define JEDEC_LSA_PROTECT_SET1 0x08 #define JEDEC_LSA_PROTECT_SET2 0x0a #define JEDEC_LSA_PROTECT_SET3 0x00 #define JEDEC_LSA_PROTECT_CLR 0x06 #define JEDEC_LSA_PROTECT_GET0 0x03 #define JEDEC_LSA_PROTECT_GET1 0x09 #define JEDEC_LSA_PROTECT_GET2 0x0b #define JEDEC_LSA_PROTECT_GET3 0x01 #define JEDEC_DTI_PAGE 0x60 #define JEDEC_LSA_PAGE_SET0 0x0c #define JEDEC_LSA_PAGE_SET1 0x0e #define JEDEC_LSA_PAGE_GET 0x0d /* The offsets and lengths of various SPD bytes are defined in Annex K (DDR3) * and Annex L (DDR4). Conveniently, the DRAM type is at the same offset for * both versions. * * This list only includes information needed to get the asset information and * calculate the DIMM capacity. */ #define SPD_OFFSET_DRAM_TYPE 2 #define SPD_OFFSET_DDR3_SDRAM_CAPACITY 4 #define SPD_OFFSET_DDR3_DIMM_RANKS 7 #define SPD_OFFSET_DDR3_SDRAM_WIDTH 7 #define SPD_OFFSET_DDR3_BUS_WIDTH 8 #define SPD_OFFSET_DDR3_TSOD_PRESENT 32 #define SPD_OFFSET_DDR3_SERIAL 122 #define SPD_LEN_DDR3_SERIAL 4 #define SPD_OFFSET_DDR3_PARTNUM 128 #define SPD_LEN_DDR3_PARTNUM 18 #define SPD_OFFSET_DDR4_SDRAM_CAPACITY 4 #define SPD_OFFSET_DDR4_SDRAM_PKG_TYPE 6 #define SPD_OFFSET_DDR4_DIMM_RANKS 12 #define SPD_OFFSET_DDR4_SDRAM_WIDTH 12 #define SPD_OFFSET_DDR4_BUS_WIDTH 13 #define SPD_OFFSET_DDR4_TSOD_PRESENT 14 #define SPD_OFFSET_DDR4_SERIAL 325 #define SPD_LEN_DDR4_SERIAL 4 #define SPD_OFFSET_DDR4_PARTNUM 329 #define SPD_LEN_DDR4_PARTNUM 20 /* The "DRAM Type" field of the SPD enumerates various memory technologies which * have been used over the years. The list is append-only, so we need only refer * to the latest SPD specification. In this case, Annex L for DDR4. */ enum dram_type { DRAM_TYPE_RESERVED = 0x00, DRAM_TYPE_FAST_PAGE_MODE = 0x01, DRAM_TYPE_EDO = 0x02, DRAM_TYPE_PIPLEINED_NYBBLE = 0x03, DRAM_TYPE_SDRAM = 0x04, DRAM_TYPE_ROM = 0x05, DRAM_TYPE_DDR_SGRAM = 0x06, DRAM_TYPE_DDR_SDRAM = 0x07, DRAM_TYPE_DDR2_SDRAM = 0x08, DRAM_TYPE_DDR2_SDRAM_FBDIMM = 0x09, DRAM_TYPE_DDR2_SDRAM_FBDIMM_PROBE = 0x0a, DRAM_TYPE_DDR3_SDRAM = 0x0b, DRAM_TYPE_DDR4_SDRAM = 0x0c, DRAM_TYPE_RESERVED_0D = 0x0d, DRAM_TYPE_DDR4E_SDRAM = 0x0e, DRAM_TYPE_LPDDR3_SDRAM = 0x0f, DRAM_TYPE_LPDDR4_SDRAM = 0x10, }; /* The TSOD is accessed using a simple word interface, which is identical * between TSE2002av (DDR3) and TSE2004av (DDR4). */ #define TSOD_REG_CAPABILITES 0 #define TSOD_REG_CONFIG 1 #define TSOD_REG_LIM_HIGH 2 #define TSOD_REG_LIM_LOW 3 #define TSOD_REG_LIM_CRIT 4 #define TSOD_REG_TEMPERATURE 5 #define TSOD_REG_MANUFACTURER 6 #define TSOD_REG_DEV_REV 7 #endif /* _DEV__JEDEC_DIMM__JEDEC_DIMM_H_ */ /* vi: set ts=8 sw=4 sts=8 noet: */