Index: stable/12/sys/gnu/dts/include/dt-bindings/bus/ti-sysc.h =================================================================== --- stable/12/sys/gnu/dts/include/dt-bindings/bus/ti-sysc.h (revision 343011) +++ stable/12/sys/gnu/dts/include/dt-bindings/bus/ti-sysc.h (revision 343012) @@ -1,22 +1,24 @@ /* TI sysc interconnect target module defines */ /* Generic sysc found on omap2 and later, also known as type1 */ #define SYSC_OMAP2_CLOCKACTIVITY (3 << 8) #define SYSC_OMAP2_EMUFREE (1 << 5) #define SYSC_OMAP2_ENAWAKEUP (1 << 2) #define SYSC_OMAP2_SOFTRESET (1 << 1) #define SYSC_OMAP2_AUTOIDLE (1 << 0) /* Generic sysc found on omap4 and later, also known as type2 */ #define SYSC_OMAP4_DMADISABLE (1 << 16) #define SYSC_OMAP4_FREEEMU (1 << 1) /* Also known as EMUFREE */ #define SYSC_OMAP4_SOFTRESET (1 << 0) /* SmartReflex sysc found on 36xx and later */ #define SYSC_OMAP3_SR_ENAWAKEUP (1 << 26) +#define SYSC_DRA7_MCAN_ENAWAKEUP (1 << 4) + /* SYSCONFIG STANDBYMODE/MIDLEMODE/SIDLEMODE supported by hardware */ #define SYSC_IDLE_FORCE 0 #define SYSC_IDLE_NO 1 #define SYSC_IDLE_SMART 2 #define SYSC_IDLE_SMART_WKUP 3 Index: stable/12/sys/gnu/dts/include/dt-bindings/clock/exynos5440.h =================================================================== --- stable/12/sys/gnu/dts/include/dt-bindings/clock/exynos5440.h (revision 343011) +++ stable/12/sys/gnu/dts/include/dt-bindings/clock/exynos5440.h (nonexistent) @@ -1,44 +0,0 @@ -/* - * Copyright (c) 2013 Samsung Electronics Co., Ltd. - * Author: Andrzej Hajda - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * Device Tree binding constants for Exynos5440 clock controller. -*/ - -#ifndef _DT_BINDINGS_CLOCK_EXYNOS_5440_H -#define _DT_BINDINGS_CLOCK_EXYNOS_5440_H - -#define CLK_XTAL 1 -#define CLK_ARM_CLK 2 -#define CLK_CPLLA 3 -#define CLK_CPLLB 4 -#define CLK_SPI_BAUD 16 -#define CLK_PB0_250 17 -#define CLK_PR0_250 18 -#define CLK_PR1_250 19 -#define CLK_B_250 20 -#define CLK_B_125 21 -#define CLK_B_200 22 -#define CLK_SATA 23 -#define CLK_USB 24 -#define CLK_GMAC0 25 -#define CLK_CS250 26 -#define CLK_PB0_250_O 27 -#define CLK_PR0_250_O 28 -#define CLK_PR1_250_O 29 -#define CLK_B_250_O 30 -#define CLK_B_125_O 31 -#define CLK_B_200_O 32 -#define CLK_SATA_O 33 -#define CLK_USB_O 34 -#define CLK_GMAC0_O 35 -#define CLK_CS250_O 36 - -/* must be greater than maximal clock id */ -#define CLK_NR_CLKS 37 - -#endif /* _DT_BINDINGS_CLOCK_EXYNOS_5440_H */ Property changes on: stable/12/sys/gnu/dts/include/dt-bindings/clock/exynos5440.h ___________________________________________________________________ Deleted: fbsd:nokeywords ## -1 +0,0 ## -yes \ No newline at end of property Deleted: svn:eol-style ## -1 +0,0 ## -native \ No newline at end of property Deleted: svn:mime-type ## -1 +0,0 ## -text/plain \ No newline at end of property Index: stable/12/sys/gnu/dts/include/dt-bindings/clock/actions,s700-cmu.h =================================================================== --- stable/12/sys/gnu/dts/include/dt-bindings/clock/actions,s700-cmu.h (nonexistent) +++ stable/12/sys/gnu/dts/include/dt-bindings/clock/actions,s700-cmu.h (revision 343012) @@ -0,0 +1,118 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Device Tree binding constants for Actions Semi S700 Clock Management Unit + * + * Copyright (c) 2014 Actions Semi Inc. + * Author: David Liu + * + * Author: Pathiban Nallathambi + * Author: Saravanan Sekar + */ + +#ifndef __DT_BINDINGS_CLOCK_S700_H +#define __DT_BINDINGS_CLOCK_S700_H + +#define CLK_NONE 0 + +/* pll clocks */ +#define CLK_CORE_PLL 1 +#define CLK_DEV_PLL 2 +#define CLK_DDR_PLL 3 +#define CLK_NAND_PLL 4 +#define CLK_DISPLAY_PLL 5 +#define CLK_TVOUT_PLL 6 +#define CLK_CVBS_PLL 7 +#define CLK_AUDIO_PLL 8 +#define CLK_ETHERNET_PLL 9 + +/* system clock */ +#define CLK_CPU 10 +#define CLK_DEV 11 +#define CLK_AHB 12 +#define CLK_APB 13 +#define CLK_DMAC 14 +#define CLK_NOC0_CLK_MUX 15 +#define CLK_NOC1_CLK_MUX 16 +#define CLK_HP_CLK_MUX 17 +#define CLK_HP_CLK_DIV 18 +#define CLK_NOC1_CLK_DIV 19 +#define CLK_NOC0 20 +#define CLK_NOC1 21 +#define CLK_SENOR_SRC 22 + +/* peripheral device clock */ +#define CLK_GPIO 23 +#define CLK_TIMER 24 +#define CLK_DSI 25 +#define CLK_CSI 26 +#define CLK_SI 27 +#define CLK_DE 28 +#define CLK_HDE 29 +#define CLK_VDE 30 +#define CLK_VCE 31 +#define CLK_NAND 32 +#define CLK_SD0 33 +#define CLK_SD1 34 +#define CLK_SD2 35 + +#define CLK_UART0 36 +#define CLK_UART1 37 +#define CLK_UART2 38 +#define CLK_UART3 39 +#define CLK_UART4 40 +#define CLK_UART5 41 +#define CLK_UART6 42 + +#define CLK_PWM0 43 +#define CLK_PWM1 44 +#define CLK_PWM2 45 +#define CLK_PWM3 46 +#define CLK_PWM4 47 +#define CLK_PWM5 48 +#define CLK_GPU3D 49 + +#define CLK_I2C0 50 +#define CLK_I2C1 51 +#define CLK_I2C2 52 +#define CLK_I2C3 53 + +#define CLK_SPI0 54 +#define CLK_SPI1 55 +#define CLK_SPI2 56 +#define CLK_SPI3 57 + +#define CLK_USB3_480MPLL0 58 +#define CLK_USB3_480MPHY0 59 +#define CLK_USB3_5GPHY 60 +#define CLK_USB3_CCE 61 +#define CLK_USB3_MAC 62 + +#define CLK_LCD 63 +#define CLK_HDMI_AUDIO 64 +#define CLK_I2SRX 65 +#define CLK_I2STX 66 + +#define CLK_SENSOR0 67 +#define CLK_SENSOR1 68 + +#define CLK_HDMI_DEV 69 + +#define CLK_ETHERNET 70 +#define CLK_RMII_REF 71 + +#define CLK_USB2H0_PLLEN 72 +#define CLK_USB2H0_PHY 73 +#define CLK_USB2H0_CCE 74 +#define CLK_USB2H1_PLLEN 75 +#define CLK_USB2H1_PHY 76 +#define CLK_USB2H1_CCE 77 + +#define CLK_TVOUT 78 + +#define CLK_THERMAL_SENSOR 79 + +#define CLK_IRC_SWITCH 80 +#define CLK_PCM1 81 +#define CLK_NR_CLKS (CLK_PCM1 + 1) + +#endif /* __DT_BINDINGS_CLOCK_S700_H */ Property changes on: stable/12/sys/gnu/dts/include/dt-bindings/clock/actions,s700-cmu.h ___________________________________________________________________ Added: fbsd:nokeywords ## -0,0 +1 ## +yes \ No newline at end of property Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:mime-type ## -0,0 +1 ## +text/plain \ No newline at end of property Index: stable/12/sys/gnu/dts/include/dt-bindings/clock/aspeed-clock.h =================================================================== --- stable/12/sys/gnu/dts/include/dt-bindings/clock/aspeed-clock.h (revision 343011) +++ stable/12/sys/gnu/dts/include/dt-bindings/clock/aspeed-clock.h (revision 343012) @@ -1,54 +1,54 @@ /* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ #ifndef DT_BINDINGS_ASPEED_CLOCK_H #define DT_BINDINGS_ASPEED_CLOCK_H #define ASPEED_CLK_GATE_ECLK 0 #define ASPEED_CLK_GATE_GCLK 1 #define ASPEED_CLK_GATE_MCLK 2 #define ASPEED_CLK_GATE_VCLK 3 #define ASPEED_CLK_GATE_BCLK 4 #define ASPEED_CLK_GATE_DCLK 5 #define ASPEED_CLK_GATE_REFCLK 6 #define ASPEED_CLK_GATE_USBPORT2CLK 7 #define ASPEED_CLK_GATE_LCLK 8 #define ASPEED_CLK_GATE_USBUHCICLK 9 #define ASPEED_CLK_GATE_D1CLK 10 #define ASPEED_CLK_GATE_YCLK 11 #define ASPEED_CLK_GATE_USBPORT1CLK 12 #define ASPEED_CLK_GATE_UART1CLK 13 #define ASPEED_CLK_GATE_UART2CLK 14 #define ASPEED_CLK_GATE_UART5CLK 15 #define ASPEED_CLK_GATE_ESPICLK 16 #define ASPEED_CLK_GATE_MAC1CLK 17 #define ASPEED_CLK_GATE_MAC2CLK 18 #define ASPEED_CLK_GATE_RSACLK 19 #define ASPEED_CLK_GATE_UART3CLK 20 #define ASPEED_CLK_GATE_UART4CLK 21 -#define ASPEED_CLK_GATE_SDCLKCLK 22 +#define ASPEED_CLK_GATE_SDCLK 22 #define ASPEED_CLK_GATE_LHCCLK 23 #define ASPEED_CLK_HPLL 24 #define ASPEED_CLK_AHB 25 #define ASPEED_CLK_APB 26 #define ASPEED_CLK_UART 27 #define ASPEED_CLK_SDIO 28 #define ASPEED_CLK_ECLK 29 #define ASPEED_CLK_ECLK_MUX 30 #define ASPEED_CLK_LHCLK 31 #define ASPEED_CLK_MAC 32 #define ASPEED_CLK_BCLK 33 #define ASPEED_CLK_MPLL 34 #define ASPEED_CLK_24M 35 #define ASPEED_RESET_XDMA 0 #define ASPEED_RESET_MCTP 1 #define ASPEED_RESET_ADC 2 #define ASPEED_RESET_JTAG_MASTER 3 #define ASPEED_RESET_MIC 4 #define ASPEED_RESET_PWM 5 #define ASPEED_RESET_PECI 6 #define ASPEED_RESET_I2C 7 #define ASPEED_RESET_AHB 8 #define ASPEED_RESET_CRT1 9 #endif Index: stable/12/sys/gnu/dts/include/dt-bindings/clock/axg-audio-clkc.h =================================================================== --- stable/12/sys/gnu/dts/include/dt-bindings/clock/axg-audio-clkc.h (nonexistent) +++ stable/12/sys/gnu/dts/include/dt-bindings/clock/axg-audio-clkc.h (revision 343012) @@ -0,0 +1,94 @@ +/* SPDX-License-Identifier: (GPL-2.0 OR MIT) */ +/* + * Copyright (c) 2018 Baylibre SAS. + * Author: Jerome Brunet + */ + +#ifndef __AXG_AUDIO_CLKC_BINDINGS_H +#define __AXG_AUDIO_CLKC_BINDINGS_H + +#define AUD_CLKID_SLV_SCLK0 9 +#define AUD_CLKID_SLV_SCLK1 10 +#define AUD_CLKID_SLV_SCLK2 11 +#define AUD_CLKID_SLV_SCLK3 12 +#define AUD_CLKID_SLV_SCLK4 13 +#define AUD_CLKID_SLV_SCLK5 14 +#define AUD_CLKID_SLV_SCLK6 15 +#define AUD_CLKID_SLV_SCLK7 16 +#define AUD_CLKID_SLV_SCLK8 17 +#define AUD_CLKID_SLV_SCLK9 18 +#define AUD_CLKID_SLV_LRCLK0 19 +#define AUD_CLKID_SLV_LRCLK1 20 +#define AUD_CLKID_SLV_LRCLK2 21 +#define AUD_CLKID_SLV_LRCLK3 22 +#define AUD_CLKID_SLV_LRCLK4 23 +#define AUD_CLKID_SLV_LRCLK5 24 +#define AUD_CLKID_SLV_LRCLK6 25 +#define AUD_CLKID_SLV_LRCLK7 26 +#define AUD_CLKID_SLV_LRCLK8 27 +#define AUD_CLKID_SLV_LRCLK9 28 +#define AUD_CLKID_DDR_ARB 29 +#define AUD_CLKID_PDM 30 +#define AUD_CLKID_TDMIN_A 31 +#define AUD_CLKID_TDMIN_B 32 +#define AUD_CLKID_TDMIN_C 33 +#define AUD_CLKID_TDMIN_LB 34 +#define AUD_CLKID_TDMOUT_A 35 +#define AUD_CLKID_TDMOUT_B 36 +#define AUD_CLKID_TDMOUT_C 37 +#define AUD_CLKID_FRDDR_A 38 +#define AUD_CLKID_FRDDR_B 39 +#define AUD_CLKID_FRDDR_C 40 +#define AUD_CLKID_TODDR_A 41 +#define AUD_CLKID_TODDR_B 42 +#define AUD_CLKID_TODDR_C 43 +#define AUD_CLKID_LOOPBACK 44 +#define AUD_CLKID_SPDIFIN 45 +#define AUD_CLKID_SPDIFOUT 46 +#define AUD_CLKID_RESAMPLE 47 +#define AUD_CLKID_POWER_DETECT 48 +#define AUD_CLKID_MST_A_MCLK 49 +#define AUD_CLKID_MST_B_MCLK 50 +#define AUD_CLKID_MST_C_MCLK 51 +#define AUD_CLKID_MST_D_MCLK 52 +#define AUD_CLKID_MST_E_MCLK 53 +#define AUD_CLKID_MST_F_MCLK 54 +#define AUD_CLKID_SPDIFOUT_CLK 55 +#define AUD_CLKID_SPDIFIN_CLK 56 +#define AUD_CLKID_PDM_DCLK 57 +#define AUD_CLKID_PDM_SYSCLK 58 +#define AUD_CLKID_MST_A_SCLK 79 +#define AUD_CLKID_MST_B_SCLK 80 +#define AUD_CLKID_MST_C_SCLK 81 +#define AUD_CLKID_MST_D_SCLK 82 +#define AUD_CLKID_MST_E_SCLK 83 +#define AUD_CLKID_MST_F_SCLK 84 +#define AUD_CLKID_MST_A_LRCLK 86 +#define AUD_CLKID_MST_B_LRCLK 87 +#define AUD_CLKID_MST_C_LRCLK 88 +#define AUD_CLKID_MST_D_LRCLK 89 +#define AUD_CLKID_MST_E_LRCLK 90 +#define AUD_CLKID_MST_F_LRCLK 91 +#define AUD_CLKID_TDMIN_A_SCLK_SEL 116 +#define AUD_CLKID_TDMIN_B_SCLK_SEL 117 +#define AUD_CLKID_TDMIN_C_SCLK_SEL 118 +#define AUD_CLKID_TDMIN_LB_SCLK_SEL 119 +#define AUD_CLKID_TDMOUT_A_SCLK_SEL 120 +#define AUD_CLKID_TDMOUT_B_SCLK_SEL 121 +#define AUD_CLKID_TDMOUT_C_SCLK_SEL 122 +#define AUD_CLKID_TDMIN_A_SCLK 123 +#define AUD_CLKID_TDMIN_B_SCLK 124 +#define AUD_CLKID_TDMIN_C_SCLK 125 +#define AUD_CLKID_TDMIN_LB_SCLK 126 +#define AUD_CLKID_TDMOUT_A_SCLK 127 +#define AUD_CLKID_TDMOUT_B_SCLK 128 +#define AUD_CLKID_TDMOUT_C_SCLK 129 +#define AUD_CLKID_TDMIN_A_LRCLK 130 +#define AUD_CLKID_TDMIN_B_LRCLK 131 +#define AUD_CLKID_TDMIN_C_LRCLK 132 +#define AUD_CLKID_TDMIN_LB_LRCLK 133 +#define AUD_CLKID_TDMOUT_A_LRCLK 134 +#define AUD_CLKID_TDMOUT_B_LRCLK 135 +#define AUD_CLKID_TDMOUT_C_LRCLK 136 + +#endif /* __AXG_AUDIO_CLKC_BINDINGS_H */ Property changes on: stable/12/sys/gnu/dts/include/dt-bindings/clock/axg-audio-clkc.h ___________________________________________________________________ Added: fbsd:nokeywords ## -0,0 +1 ## +yes \ No newline at end of property Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:mime-type ## -0,0 +1 ## +text/plain \ No newline at end of property Index: stable/12/sys/gnu/dts/include/dt-bindings/clock/axg-clkc.h =================================================================== --- stable/12/sys/gnu/dts/include/dt-bindings/clock/axg-clkc.h (revision 343011) +++ stable/12/sys/gnu/dts/include/dt-bindings/clock/axg-clkc.h (revision 343012) @@ -1,72 +1,76 @@ /* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ /* * Meson-AXG clock tree IDs * * Copyright (c) 2017 Amlogic, Inc. All rights reserved. */ #ifndef __AXG_CLKC_H #define __AXG_CLKC_H #define CLKID_SYS_PLL 0 #define CLKID_FIXED_PLL 1 #define CLKID_FCLK_DIV2 2 #define CLKID_FCLK_DIV3 3 #define CLKID_FCLK_DIV4 4 #define CLKID_FCLK_DIV5 5 #define CLKID_FCLK_DIV7 6 #define CLKID_GP0_PLL 7 #define CLKID_CLK81 10 #define CLKID_MPLL0 11 #define CLKID_MPLL1 12 #define CLKID_MPLL2 13 #define CLKID_MPLL3 14 #define CLKID_DDR 15 #define CLKID_AUDIO_LOCKER 16 #define CLKID_MIPI_DSI_HOST 17 #define CLKID_ISA 18 #define CLKID_PL301 19 #define CLKID_PERIPHS 20 #define CLKID_SPICC0 21 #define CLKID_I2C 22 #define CLKID_RNG0 23 #define CLKID_UART0 24 #define CLKID_MIPI_DSI_PHY 25 #define CLKID_SPICC1 26 #define CLKID_PCIE_A 27 #define CLKID_PCIE_B 28 #define CLKID_HIU_IFACE 29 #define CLKID_ASSIST_MISC 30 #define CLKID_SD_EMMC_B 31 #define CLKID_SD_EMMC_C 32 #define CLKID_DMA 33 #define CLKID_SPI 34 #define CLKID_AUDIO 35 #define CLKID_ETH 36 #define CLKID_UART1 37 #define CLKID_G2D 38 #define CLKID_USB0 39 #define CLKID_USB1 40 #define CLKID_RESET 41 #define CLKID_USB 42 #define CLKID_AHB_ARB0 43 #define CLKID_EFUSE 44 #define CLKID_BOOT_ROM 45 #define CLKID_AHB_DATA_BUS 46 #define CLKID_AHB_CTRL_BUS 47 #define CLKID_USB1_DDR_BRIDGE 48 #define CLKID_USB0_DDR_BRIDGE 49 #define CLKID_MMC_PCLK 50 #define CLKID_VPU_INTR 51 #define CLKID_SEC_AHB_AHB3_BRIDGE 52 #define CLKID_GIC 53 #define CLKID_AO_MEDIA_CPU 54 #define CLKID_AO_AHB_SRAM 55 #define CLKID_AO_AHB_BUS 56 #define CLKID_AO_IFACE 57 #define CLKID_AO_I2C 58 #define CLKID_SD_EMMC_B_CLK0 59 #define CLKID_SD_EMMC_C_CLK0 60 #define CLKID_HIFI_PLL 69 +#define CLKID_PCIE_CML_EN0 79 +#define CLKID_PCIE_CML_EN1 80 +#define CLKID_MIPI_ENABLE 81 +#define CLKID_GEN_CLK 84 #endif /* __AXG_CLKC_H */ Index: stable/12/sys/gnu/dts/include/dt-bindings/clock/dra7.h =================================================================== --- stable/12/sys/gnu/dts/include/dt-bindings/clock/dra7.h (revision 343011) +++ stable/12/sys/gnu/dts/include/dt-bindings/clock/dra7.h (revision 343012) @@ -1,172 +1,173 @@ /* * Copyright 2017 Texas Instruments, Inc. * * This software is licensed under the terms of the GNU General Public * License version 2, as published by the Free Software Foundation, and * may be copied, distributed, and modified under those terms. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. */ #ifndef __DT_BINDINGS_CLK_DRA7_H #define __DT_BINDINGS_CLK_DRA7_H #define DRA7_CLKCTRL_OFFSET 0x20 #define DRA7_CLKCTRL_INDEX(offset) ((offset) - DRA7_CLKCTRL_OFFSET) /* mpu clocks */ #define DRA7_MPU_CLKCTRL DRA7_CLKCTRL_INDEX(0x20) /* ipu clocks */ #define DRA7_IPU_CLKCTRL_OFFSET 0x40 #define DRA7_IPU_CLKCTRL_INDEX(offset) ((offset) - DRA7_IPU_CLKCTRL_OFFSET) #define DRA7_MCASP1_CLKCTRL DRA7_IPU_CLKCTRL_INDEX(0x50) #define DRA7_TIMER5_CLKCTRL DRA7_IPU_CLKCTRL_INDEX(0x58) #define DRA7_TIMER6_CLKCTRL DRA7_IPU_CLKCTRL_INDEX(0x60) #define DRA7_TIMER7_CLKCTRL DRA7_IPU_CLKCTRL_INDEX(0x68) #define DRA7_TIMER8_CLKCTRL DRA7_IPU_CLKCTRL_INDEX(0x70) #define DRA7_I2C5_CLKCTRL DRA7_IPU_CLKCTRL_INDEX(0x78) #define DRA7_UART6_CLKCTRL DRA7_IPU_CLKCTRL_INDEX(0x80) /* rtc clocks */ #define DRA7_RTC_CLKCTRL_OFFSET 0x40 #define DRA7_RTC_CLKCTRL_INDEX(offset) ((offset) - DRA7_RTC_CLKCTRL_OFFSET) #define DRA7_RTCSS_CLKCTRL DRA7_RTC_CLKCTRL_INDEX(0x44) /* coreaon clocks */ #define DRA7_SMARTREFLEX_MPU_CLKCTRL DRA7_CLKCTRL_INDEX(0x28) #define DRA7_SMARTREFLEX_CORE_CLKCTRL DRA7_CLKCTRL_INDEX(0x38) /* l3main1 clocks */ #define DRA7_L3_MAIN_1_CLKCTRL DRA7_CLKCTRL_INDEX(0x20) #define DRA7_GPMC_CLKCTRL DRA7_CLKCTRL_INDEX(0x28) #define DRA7_TPCC_CLKCTRL DRA7_CLKCTRL_INDEX(0x70) #define DRA7_TPTC0_CLKCTRL DRA7_CLKCTRL_INDEX(0x78) #define DRA7_TPTC1_CLKCTRL DRA7_CLKCTRL_INDEX(0x80) #define DRA7_VCP1_CLKCTRL DRA7_CLKCTRL_INDEX(0x88) #define DRA7_VCP2_CLKCTRL DRA7_CLKCTRL_INDEX(0x90) /* dma clocks */ #define DRA7_DMA_SYSTEM_CLKCTRL DRA7_CLKCTRL_INDEX(0x20) /* emif clocks */ #define DRA7_DMM_CLKCTRL DRA7_CLKCTRL_INDEX(0x20) /* atl clocks */ #define DRA7_ATL_CLKCTRL_OFFSET 0x0 #define DRA7_ATL_CLKCTRL_INDEX(offset) ((offset) - DRA7_ATL_CLKCTRL_OFFSET) #define DRA7_ATL_CLKCTRL DRA7_ATL_CLKCTRL_INDEX(0x0) /* l4cfg clocks */ #define DRA7_L4_CFG_CLKCTRL DRA7_CLKCTRL_INDEX(0x20) #define DRA7_SPINLOCK_CLKCTRL DRA7_CLKCTRL_INDEX(0x28) #define DRA7_MAILBOX1_CLKCTRL DRA7_CLKCTRL_INDEX(0x30) #define DRA7_MAILBOX2_CLKCTRL DRA7_CLKCTRL_INDEX(0x48) #define DRA7_MAILBOX3_CLKCTRL DRA7_CLKCTRL_INDEX(0x50) #define DRA7_MAILBOX4_CLKCTRL DRA7_CLKCTRL_INDEX(0x58) #define DRA7_MAILBOX5_CLKCTRL DRA7_CLKCTRL_INDEX(0x60) #define DRA7_MAILBOX6_CLKCTRL DRA7_CLKCTRL_INDEX(0x68) #define DRA7_MAILBOX7_CLKCTRL DRA7_CLKCTRL_INDEX(0x70) #define DRA7_MAILBOX8_CLKCTRL DRA7_CLKCTRL_INDEX(0x78) #define DRA7_MAILBOX9_CLKCTRL DRA7_CLKCTRL_INDEX(0x80) #define DRA7_MAILBOX10_CLKCTRL DRA7_CLKCTRL_INDEX(0x88) #define DRA7_MAILBOX11_CLKCTRL DRA7_CLKCTRL_INDEX(0x90) #define DRA7_MAILBOX12_CLKCTRL DRA7_CLKCTRL_INDEX(0x98) #define DRA7_MAILBOX13_CLKCTRL DRA7_CLKCTRL_INDEX(0xa0) /* l3instr clocks */ #define DRA7_L3_MAIN_2_CLKCTRL DRA7_CLKCTRL_INDEX(0x20) #define DRA7_L3_INSTR_CLKCTRL DRA7_CLKCTRL_INDEX(0x28) /* dss clocks */ #define DRA7_DSS_CORE_CLKCTRL DRA7_CLKCTRL_INDEX(0x20) #define DRA7_BB2D_CLKCTRL DRA7_CLKCTRL_INDEX(0x30) /* l3init clocks */ #define DRA7_MMC1_CLKCTRL DRA7_CLKCTRL_INDEX(0x28) #define DRA7_MMC2_CLKCTRL DRA7_CLKCTRL_INDEX(0x30) #define DRA7_USB_OTG_SS2_CLKCTRL DRA7_CLKCTRL_INDEX(0x40) #define DRA7_USB_OTG_SS3_CLKCTRL DRA7_CLKCTRL_INDEX(0x48) #define DRA7_USB_OTG_SS4_CLKCTRL DRA7_CLKCTRL_INDEX(0x50) #define DRA7_SATA_CLKCTRL DRA7_CLKCTRL_INDEX(0x88) #define DRA7_PCIE1_CLKCTRL DRA7_CLKCTRL_INDEX(0xb0) #define DRA7_PCIE2_CLKCTRL DRA7_CLKCTRL_INDEX(0xb8) #define DRA7_GMAC_CLKCTRL DRA7_CLKCTRL_INDEX(0xd0) #define DRA7_OCP2SCP1_CLKCTRL DRA7_CLKCTRL_INDEX(0xe0) #define DRA7_OCP2SCP3_CLKCTRL DRA7_CLKCTRL_INDEX(0xe8) #define DRA7_USB_OTG_SS1_CLKCTRL DRA7_CLKCTRL_INDEX(0xf0) /* l4per clocks */ #define DRA7_L4PER_CLKCTRL_OFFSET 0x0 #define DRA7_L4PER_CLKCTRL_INDEX(offset) ((offset) - DRA7_L4PER_CLKCTRL_OFFSET) #define DRA7_L4_PER2_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0xc) #define DRA7_L4_PER3_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x14) #define DRA7_TIMER10_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x28) #define DRA7_TIMER11_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x30) #define DRA7_TIMER2_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x38) #define DRA7_TIMER3_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x40) #define DRA7_TIMER4_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x48) #define DRA7_TIMER9_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x50) #define DRA7_ELM_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x58) #define DRA7_GPIO2_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x60) #define DRA7_GPIO3_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x68) #define DRA7_GPIO4_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x70) #define DRA7_GPIO5_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x78) #define DRA7_GPIO6_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x80) #define DRA7_HDQ1W_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x88) #define DRA7_EPWMSS1_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x90) #define DRA7_EPWMSS2_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x98) #define DRA7_I2C1_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0xa0) #define DRA7_I2C2_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0xa8) #define DRA7_I2C3_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0xb0) #define DRA7_I2C4_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0xb8) #define DRA7_L4_PER1_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0xc0) #define DRA7_EPWMSS0_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0xc4) #define DRA7_TIMER13_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0xc8) #define DRA7_TIMER14_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0xd0) #define DRA7_TIMER15_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0xd8) #define DRA7_MCSPI1_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0xf0) #define DRA7_MCSPI2_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0xf8) #define DRA7_MCSPI3_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x100) #define DRA7_MCSPI4_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x108) #define DRA7_GPIO7_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x110) #define DRA7_GPIO8_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x118) #define DRA7_MMC3_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x120) #define DRA7_MMC4_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x128) #define DRA7_TIMER16_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x130) #define DRA7_QSPI_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x138) #define DRA7_UART1_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x140) #define DRA7_UART2_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x148) #define DRA7_UART3_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x150) #define DRA7_UART4_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x158) #define DRA7_MCASP2_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x160) #define DRA7_MCASP3_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x168) #define DRA7_UART5_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x170) #define DRA7_MCASP5_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x178) #define DRA7_MCASP8_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x190) #define DRA7_MCASP4_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x198) #define DRA7_AES1_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x1a0) #define DRA7_AES2_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x1a8) #define DRA7_DES_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x1b0) #define DRA7_RNG_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x1c0) #define DRA7_SHAM_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x1c8) #define DRA7_UART7_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x1d0) #define DRA7_UART8_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x1e0) #define DRA7_UART9_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x1e8) #define DRA7_DCAN2_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x1f0) #define DRA7_MCASP6_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x204) #define DRA7_MCASP7_CLKCTRL DRA7_L4PER_CLKCTRL_INDEX(0x208) /* wkupaon clocks */ #define DRA7_L4_WKUP_CLKCTRL DRA7_CLKCTRL_INDEX(0x20) #define DRA7_WD_TIMER2_CLKCTRL DRA7_CLKCTRL_INDEX(0x30) #define DRA7_GPIO1_CLKCTRL DRA7_CLKCTRL_INDEX(0x38) #define DRA7_TIMER1_CLKCTRL DRA7_CLKCTRL_INDEX(0x40) #define DRA7_TIMER12_CLKCTRL DRA7_CLKCTRL_INDEX(0x48) #define DRA7_COUNTER_32K_CLKCTRL DRA7_CLKCTRL_INDEX(0x50) #define DRA7_UART10_CLKCTRL DRA7_CLKCTRL_INDEX(0x80) #define DRA7_DCAN1_CLKCTRL DRA7_CLKCTRL_INDEX(0x88) +#define DRA7_ADC_CLKCTRL DRA7_CLKCTRL_INDEX(0xa0) #endif Index: stable/12/sys/gnu/dts/include/dt-bindings/clock/gxbb-clkc.h =================================================================== --- stable/12/sys/gnu/dts/include/dt-bindings/clock/gxbb-clkc.h (revision 343011) +++ stable/12/sys/gnu/dts/include/dt-bindings/clock/gxbb-clkc.h (revision 343012) @@ -1,131 +1,132 @@ /* SPDX-License-Identifier: GPL-2.0 */ /* * GXBB clock tree IDs */ #ifndef __GXBB_CLKC_H #define __GXBB_CLKC_H #define CLKID_SYS_PLL 0 #define CLKID_HDMI_PLL 2 #define CLKID_FIXED_PLL 3 #define CLKID_FCLK_DIV2 4 #define CLKID_FCLK_DIV3 5 #define CLKID_FCLK_DIV4 6 #define CLKID_FCLK_DIV5 7 #define CLKID_FCLK_DIV7 8 #define CLKID_GP0_PLL 9 #define CLKID_CLK81 12 #define CLKID_MPLL0 13 #define CLKID_MPLL1 14 #define CLKID_MPLL2 15 #define CLKID_DDR 16 #define CLKID_DOS 17 #define CLKID_ISA 18 #define CLKID_PL301 19 #define CLKID_PERIPHS 20 #define CLKID_SPICC 21 #define CLKID_I2C 22 #define CLKID_SAR_ADC 23 #define CLKID_SMART_CARD 24 #define CLKID_RNG0 25 #define CLKID_UART0 26 #define CLKID_SDHC 27 #define CLKID_STREAM 28 #define CLKID_ASYNC_FIFO 29 #define CLKID_SDIO 30 #define CLKID_ABUF 31 #define CLKID_HIU_IFACE 32 #define CLKID_ASSIST_MISC 33 #define CLKID_SPI 34 #define CLKID_ETH 36 #define CLKID_I2S_SPDIF 35 #define CLKID_DEMUX 37 #define CLKID_AIU_GLUE 38 #define CLKID_IEC958 39 #define CLKID_I2S_OUT 40 #define CLKID_AMCLK 41 #define CLKID_AIFIFO2 42 #define CLKID_MIXER 43 #define CLKID_MIXER_IFACE 44 #define CLKID_ADC 45 #define CLKID_BLKMV 46 #define CLKID_AIU 47 #define CLKID_UART1 48 #define CLKID_G2D 49 #define CLKID_USB0 50 #define CLKID_USB1 51 #define CLKID_RESET 52 #define CLKID_NAND 53 #define CLKID_DOS_PARSER 54 #define CLKID_USB 55 #define CLKID_VDIN1 56 #define CLKID_AHB_ARB0 57 #define CLKID_EFUSE 58 #define CLKID_BOOT_ROM 59 #define CLKID_AHB_DATA_BUS 60 #define CLKID_AHB_CTRL_BUS 61 #define CLKID_HDMI_INTR_SYNC 62 #define CLKID_HDMI_PCLK 63 #define CLKID_USB1_DDR_BRIDGE 64 #define CLKID_USB0_DDR_BRIDGE 65 #define CLKID_MMC_PCLK 66 #define CLKID_DVIN 67 #define CLKID_UART2 68 #define CLKID_SANA 69 #define CLKID_VPU_INTR 70 #define CLKID_SEC_AHB_AHB3_BRIDGE 71 #define CLKID_CLK81_A53 72 #define CLKID_VCLK2_VENCI0 73 #define CLKID_VCLK2_VENCI1 74 #define CLKID_VCLK2_VENCP0 75 #define CLKID_VCLK2_VENCP1 76 #define CLKID_GCLK_VENCI_INT0 77 #define CLKID_GCLK_VENCI_INT 78 #define CLKID_DAC_CLK 79 #define CLKID_AOCLK_GATE 80 #define CLKID_IEC958_GATE 81 #define CLKID_ENC480P 82 #define CLKID_RNG1 83 #define CLKID_GCLK_VENCI_INT1 84 #define CLKID_VCLK2_VENCLMCC 85 #define CLKID_VCLK2_VENCL 86 #define CLKID_VCLK_OTHER 87 #define CLKID_EDP 88 #define CLKID_AO_MEDIA_CPU 89 #define CLKID_AO_AHB_SRAM 90 #define CLKID_AO_AHB_BUS 91 #define CLKID_AO_IFACE 92 #define CLKID_AO_I2C 93 #define CLKID_SD_EMMC_A 94 #define CLKID_SD_EMMC_B 95 #define CLKID_SD_EMMC_C 96 #define CLKID_SAR_ADC_CLK 97 #define CLKID_SAR_ADC_SEL 98 #define CLKID_MALI_0_SEL 100 #define CLKID_MALI_0 102 #define CLKID_MALI_1_SEL 103 #define CLKID_MALI_1 105 #define CLKID_MALI 106 #define CLKID_CTS_AMCLK 107 #define CLKID_CTS_MCLK_I958 110 #define CLKID_CTS_I958 113 #define CLKID_32K_CLK 114 #define CLKID_SD_EMMC_A_CLK0 119 #define CLKID_SD_EMMC_B_CLK0 122 #define CLKID_SD_EMMC_C_CLK0 125 #define CLKID_VPU_0_SEL 126 #define CLKID_VPU_0 128 #define CLKID_VPU_1_SEL 129 #define CLKID_VPU_1 131 #define CLKID_VPU 132 #define CLKID_VAPB_0_SEL 133 #define CLKID_VAPB_0 135 #define CLKID_VAPB_1_SEL 136 #define CLKID_VAPB_1 138 #define CLKID_VAPB_SEL 139 #define CLKID_VAPB 140 #define CLKID_VDEC_1 153 #define CLKID_VDEC_HEVC 156 +#define CLKID_GEN_CLK 159 #endif /* __GXBB_CLKC_H */ Index: stable/12/sys/gnu/dts/include/dt-bindings/clock/imx6sll-clock.h =================================================================== --- stable/12/sys/gnu/dts/include/dt-bindings/clock/imx6sll-clock.h (revision 343011) +++ stable/12/sys/gnu/dts/include/dt-bindings/clock/imx6sll-clock.h (revision 343012) @@ -1,202 +1,209 @@ // SPDX-License-Identifier: GPL-2.0 /* * Copyright (C) 2016 Freescale Semiconductor, Inc. * Copyright 2017-2018 NXP. * */ #ifndef __DT_BINDINGS_CLOCK_IMX6SLL_H #define __DT_BINDINGS_CLOCK_IMX6SLL_H #define IMX6SLL_CLK_DUMMY 0 #define IMX6SLL_CLK_CKIL 1 #define IMX6SLL_CLK_OSC 2 #define IMX6SLL_PLL1_BYPASS_SRC 3 #define IMX6SLL_PLL2_BYPASS_SRC 4 #define IMX6SLL_PLL3_BYPASS_SRC 5 #define IMX6SLL_PLL4_BYPASS_SRC 6 #define IMX6SLL_PLL5_BYPASS_SRC 7 #define IMX6SLL_PLL6_BYPASS_SRC 8 #define IMX6SLL_PLL7_BYPASS_SRC 9 #define IMX6SLL_CLK_PLL1 10 #define IMX6SLL_CLK_PLL2 11 #define IMX6SLL_CLK_PLL3 12 #define IMX6SLL_CLK_PLL4 13 #define IMX6SLL_CLK_PLL5 14 #define IMX6SLL_CLK_PLL6 15 #define IMX6SLL_CLK_PLL7 16 #define IMX6SLL_PLL1_BYPASS 17 #define IMX6SLL_PLL2_BYPASS 18 #define IMX6SLL_PLL3_BYPASS 19 #define IMX6SLL_PLL4_BYPASS 20 #define IMX6SLL_PLL5_BYPASS 21 #define IMX6SLL_PLL6_BYPASS 22 #define IMX6SLL_PLL7_BYPASS 23 #define IMX6SLL_CLK_PLL1_SYS 24 #define IMX6SLL_CLK_PLL2_BUS 25 #define IMX6SLL_CLK_PLL3_USB_OTG 26 #define IMX6SLL_CLK_PLL4_AUDIO 27 #define IMX6SLL_CLK_PLL5_VIDEO 28 #define IMX6SLL_CLK_PLL6_ENET 29 #define IMX6SLL_CLK_PLL7_USB_HOST 30 #define IMX6SLL_CLK_USBPHY1 31 #define IMX6SLL_CLK_USBPHY2 32 #define IMX6SLL_CLK_USBPHY1_GATE 33 #define IMX6SLL_CLK_USBPHY2_GATE 34 #define IMX6SLL_CLK_PLL2_PFD0 35 #define IMX6SLL_CLK_PLL2_PFD1 36 #define IMX6SLL_CLK_PLL2_PFD2 37 #define IMX6SLL_CLK_PLL2_PFD3 38 #define IMX6SLL_CLK_PLL3_PFD0 39 #define IMX6SLL_CLK_PLL3_PFD1 40 #define IMX6SLL_CLK_PLL3_PFD2 41 #define IMX6SLL_CLK_PLL3_PFD3 42 #define IMX6SLL_CLK_PLL4_POST_DIV 43 #define IMX6SLL_CLK_PLL4_AUDIO_DIV 44 #define IMX6SLL_CLK_PLL5_POST_DIV 45 #define IMX6SLL_CLK_PLL5_VIDEO_DIV 46 #define IMX6SLL_CLK_PLL2_198M 47 #define IMX6SLL_CLK_PLL3_120M 48 #define IMX6SLL_CLK_PLL3_80M 49 #define IMX6SLL_CLK_PLL3_60M 50 #define IMX6SLL_CLK_STEP 51 #define IMX6SLL_CLK_PLL1_SW 52 #define IMX6SLL_CLK_AXI_ALT_SEL 53 #define IMX6SLL_CLK_AXI_SEL 54 #define IMX6SLL_CLK_PERIPH_PRE 55 #define IMX6SLL_CLK_PERIPH2_PRE 56 #define IMX6SLL_CLK_PERIPH_CLK2_SEL 57 #define IMX6SLL_CLK_PERIPH2_CLK2_SEL 58 #define IMX6SLL_CLK_PERCLK_SEL 59 #define IMX6SLL_CLK_USDHC1_SEL 60 #define IMX6SLL_CLK_USDHC2_SEL 61 #define IMX6SLL_CLK_USDHC3_SEL 62 #define IMX6SLL_CLK_SSI1_SEL 63 #define IMX6SLL_CLK_SSI2_SEL 64 #define IMX6SLL_CLK_SSI3_SEL 65 #define IMX6SLL_CLK_PXP_SEL 66 #define IMX6SLL_CLK_LCDIF_PRE_SEL 67 #define IMX6SLL_CLK_LCDIF_SEL 68 #define IMX6SLL_CLK_EPDC_PRE_SEL 69 #define IMX6SLL_CLK_SPDIF_SEL 70 #define IMX6SLL_CLK_ECSPI_SEL 71 #define IMX6SLL_CLK_UART_SEL 72 #define IMX6SLL_CLK_ARM 73 #define IMX6SLL_CLK_PERIPH 74 #define IMX6SLL_CLK_PERIPH2 75 #define IMX6SLL_CLK_PERIPH2_CLK2 76 #define IMX6SLL_CLK_PERIPH_CLK2 77 #define IMX6SLL_CLK_MMDC_PODF 78 #define IMX6SLL_CLK_AXI_PODF 79 #define IMX6SLL_CLK_AHB 80 #define IMX6SLL_CLK_IPG 81 #define IMX6SLL_CLK_PERCLK 82 #define IMX6SLL_CLK_USDHC1_PODF 83 #define IMX6SLL_CLK_USDHC2_PODF 84 #define IMX6SLL_CLK_USDHC3_PODF 85 #define IMX6SLL_CLK_SSI1_PRED 86 #define IMX6SLL_CLK_SSI2_PRED 87 #define IMX6SLL_CLK_SSI3_PRED 88 #define IMX6SLL_CLK_SSI1_PODF 89 #define IMX6SLL_CLK_SSI2_PODF 90 #define IMX6SLL_CLK_SSI3_PODF 91 #define IMX6SLL_CLK_PXP_PODF 92 #define IMX6SLL_CLK_LCDIF_PRED 93 #define IMX6SLL_CLK_LCDIF_PODF 94 #define IMX6SLL_CLK_EPDC_SEL 95 #define IMX6SLL_CLK_EPDC_PODF 96 #define IMX6SLL_CLK_SPDIF_PRED 97 #define IMX6SLL_CLK_SPDIF_PODF 98 #define IMX6SLL_CLK_ECSPI_PODF 99 #define IMX6SLL_CLK_UART_PODF 100 /* CCGR 0 */ #define IMX6SLL_CLK_AIPSTZ1 101 #define IMX6SLL_CLK_AIPSTZ2 102 #define IMX6SLL_CLK_DCP 103 #define IMX6SLL_CLK_UART2_IPG 104 #define IMX6SLL_CLK_UART2_SERIAL 105 /* CCGR 1 */ #define IMX6SLL_CLK_ECSPI1 106 #define IMX6SLL_CLK_ECSPI2 107 #define IMX6SLL_CLK_ECSPI3 108 #define IMX6SLL_CLK_ECSPI4 109 #define IMX6SLL_CLK_UART3_IPG 110 #define IMX6SLL_CLK_UART3_SERIAL 111 #define IMX6SLL_CLK_UART4_IPG 112 #define IMX6SLL_CLK_UART4_SERIAL 113 #define IMX6SLL_CLK_EPIT1 114 #define IMX6SLL_CLK_EPIT2 115 #define IMX6SLL_CLK_GPT_BUS 116 #define IMX6SLL_CLK_GPT_SERIAL 117 /* CCGR2 */ #define IMX6SLL_CLK_CSI 118 #define IMX6SLL_CLK_I2C1 119 #define IMX6SLL_CLK_I2C2 120 #define IMX6SLL_CLK_I2C3 121 #define IMX6SLL_CLK_OCOTP 122 #define IMX6SLL_CLK_LCDIF_APB 123 #define IMX6SLL_CLK_PXP 124 /* CCGR3 */ #define IMX6SLL_CLK_UART5_IPG 125 #define IMX6SLL_CLK_UART5_SERIAL 126 #define IMX6SLL_CLK_EPDC_AXI 127 #define IMX6SLL_CLK_EPDC_PIX 128 #define IMX6SLL_CLK_LCDIF_PIX 129 #define IMX6SLL_CLK_WDOG1 130 #define IMX6SLL_CLK_MMDC_P0_FAST 131 #define IMX6SLL_CLK_MMDC_P0_IPG 132 #define IMX6SLL_CLK_OCRAM 133 /* CCGR4 */ #define IMX6SLL_CLK_PWM1 134 #define IMX6SLL_CLK_PWM2 135 #define IMX6SLL_CLK_PWM3 136 #define IMX6SLL_CLK_PWM4 137 /* CCGR 5 */ #define IMX6SLL_CLK_ROM 138 #define IMX6SLL_CLK_SDMA 139 #define IMX6SLL_CLK_KPP 140 #define IMX6SLL_CLK_WDOG2 141 #define IMX6SLL_CLK_SPBA 142 #define IMX6SLL_CLK_SPDIF 143 #define IMX6SLL_CLK_SPDIF_GCLK 144 #define IMX6SLL_CLK_SSI1 145 #define IMX6SLL_CLK_SSI1_IPG 146 #define IMX6SLL_CLK_SSI2 147 #define IMX6SLL_CLK_SSI2_IPG 148 #define IMX6SLL_CLK_SSI3 149 #define IMX6SLL_CLK_SSI3_IPG 150 #define IMX6SLL_CLK_UART1_IPG 151 #define IMX6SLL_CLK_UART1_SERIAL 152 /* CCGR 6 */ #define IMX6SLL_CLK_USBOH3 153 #define IMX6SLL_CLK_USDHC1 154 #define IMX6SLL_CLK_USDHC2 155 #define IMX6SLL_CLK_USDHC3 156 #define IMX6SLL_CLK_IPP_DI0 157 #define IMX6SLL_CLK_IPP_DI1 158 #define IMX6SLL_CLK_LDB_DI0_SEL 159 #define IMX6SLL_CLK_LDB_DI0_DIV_3_5 160 #define IMX6SLL_CLK_LDB_DI0_DIV_7 161 #define IMX6SLL_CLK_LDB_DI0_DIV_SEL 162 #define IMX6SLL_CLK_LDB_DI0 163 #define IMX6SLL_CLK_LDB_DI1_SEL 164 #define IMX6SLL_CLK_LDB_DI1_DIV_3_5 165 #define IMX6SLL_CLK_LDB_DI1_DIV_7 166 #define IMX6SLL_CLK_LDB_DI1_DIV_SEL 167 #define IMX6SLL_CLK_LDB_DI1 168 #define IMX6SLL_CLK_EXTERN_AUDIO_SEL 169 #define IMX6SLL_CLK_EXTERN_AUDIO_PRED 170 #define IMX6SLL_CLK_EXTERN_AUDIO_PODF 171 #define IMX6SLL_CLK_EXTERN_AUDIO 172 -#define IMX6SLL_CLK_END 173 +#define IMX6SLL_CLK_GPIO1 173 +#define IMX6SLL_CLK_GPIO2 174 +#define IMX6SLL_CLK_GPIO3 175 +#define IMX6SLL_CLK_GPIO4 176 +#define IMX6SLL_CLK_GPIO5 177 +#define IMX6SLL_CLK_GPIO6 178 + +#define IMX6SLL_CLK_END 179 #endif /* __DT_BINDINGS_CLOCK_IMX6SLL_H */ Index: stable/12/sys/gnu/dts/include/dt-bindings/clock/imx6ul-clock.h =================================================================== --- stable/12/sys/gnu/dts/include/dt-bindings/clock/imx6ul-clock.h (revision 343011) +++ stable/12/sys/gnu/dts/include/dt-bindings/clock/imx6ul-clock.h (revision 343012) @@ -1,259 +1,265 @@ /* * Copyright (C) 2015 Freescale Semiconductor, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as * published by the Free Software Foundation. * */ #ifndef __DT_BINDINGS_CLOCK_IMX6UL_H #define __DT_BINDINGS_CLOCK_IMX6UL_H #define IMX6UL_CLK_DUMMY 0 #define IMX6UL_CLK_CKIL 1 #define IMX6UL_CLK_CKIH 2 #define IMX6UL_CLK_OSC 3 #define IMX6UL_PLL1_BYPASS_SRC 4 #define IMX6UL_PLL2_BYPASS_SRC 5 #define IMX6UL_PLL3_BYPASS_SRC 6 #define IMX6UL_PLL4_BYPASS_SRC 7 #define IMX6UL_PLL5_BYPASS_SRC 8 #define IMX6UL_PLL6_BYPASS_SRC 9 #define IMX6UL_PLL7_BYPASS_SRC 10 #define IMX6UL_CLK_PLL1 11 #define IMX6UL_CLK_PLL2 12 #define IMX6UL_CLK_PLL3 13 #define IMX6UL_CLK_PLL4 14 #define IMX6UL_CLK_PLL5 15 #define IMX6UL_CLK_PLL6 16 #define IMX6UL_CLK_PLL7 17 #define IMX6UL_PLL1_BYPASS 18 #define IMX6UL_PLL2_BYPASS 19 #define IMX6UL_PLL3_BYPASS 20 #define IMX6UL_PLL4_BYPASS 21 #define IMX6UL_PLL5_BYPASS 22 #define IMX6UL_PLL6_BYPASS 23 #define IMX6UL_PLL7_BYPASS 24 #define IMX6UL_CLK_PLL1_SYS 25 #define IMX6UL_CLK_PLL2_BUS 26 #define IMX6UL_CLK_PLL3_USB_OTG 27 #define IMX6UL_CLK_PLL4_AUDIO 28 #define IMX6UL_CLK_PLL5_VIDEO 29 #define IMX6UL_CLK_PLL6_ENET 30 #define IMX6UL_CLK_PLL7_USB_HOST 31 #define IMX6UL_CLK_USBPHY1 32 #define IMX6UL_CLK_USBPHY2 33 #define IMX6UL_CLK_USBPHY1_GATE 34 #define IMX6UL_CLK_USBPHY2_GATE 35 #define IMX6UL_CLK_PLL2_PFD0 36 #define IMX6UL_CLK_PLL2_PFD1 37 #define IMX6UL_CLK_PLL2_PFD2 38 #define IMX6UL_CLK_PLL2_PFD3 39 #define IMX6UL_CLK_PLL3_PFD0 40 #define IMX6UL_CLK_PLL3_PFD1 41 #define IMX6UL_CLK_PLL3_PFD2 42 #define IMX6UL_CLK_PLL3_PFD3 43 #define IMX6UL_CLK_ENET_REF 44 #define IMX6UL_CLK_ENET2_REF 45 #define IMX6UL_CLK_ENET2_REF_125M 46 #define IMX6UL_CLK_ENET_PTP_REF 47 #define IMX6UL_CLK_ENET_PTP 48 #define IMX6UL_CLK_PLL4_POST_DIV 49 #define IMX6UL_CLK_PLL4_AUDIO_DIV 50 #define IMX6UL_CLK_PLL5_POST_DIV 51 #define IMX6UL_CLK_PLL5_VIDEO_DIV 52 #define IMX6UL_CLK_PLL2_198M 53 #define IMX6UL_CLK_PLL3_80M 54 #define IMX6UL_CLK_PLL3_60M 55 #define IMX6UL_CLK_STEP 56 #define IMX6UL_CLK_PLL1_SW 57 #define IMX6UL_CLK_AXI_ALT_SEL 58 #define IMX6UL_CLK_AXI_SEL 59 #define IMX6UL_CLK_PERIPH_PRE 60 #define IMX6UL_CLK_PERIPH2_PRE 61 #define IMX6UL_CLK_PERIPH_CLK2_SEL 62 #define IMX6UL_CLK_PERIPH2_CLK2_SEL 63 #define IMX6UL_CLK_USDHC1_SEL 64 #define IMX6UL_CLK_USDHC2_SEL 65 #define IMX6UL_CLK_BCH_SEL 66 #define IMX6UL_CLK_GPMI_SEL 67 #define IMX6UL_CLK_EIM_SLOW_SEL 68 #define IMX6UL_CLK_SPDIF_SEL 69 #define IMX6UL_CLK_SAI1_SEL 70 #define IMX6UL_CLK_SAI2_SEL 71 #define IMX6UL_CLK_SAI3_SEL 72 #define IMX6UL_CLK_LCDIF_PRE_SEL 73 #define IMX6UL_CLK_SIM_PRE_SEL 74 #define IMX6UL_CLK_LDB_DI0_SEL 75 #define IMX6UL_CLK_LDB_DI1_SEL 76 #define IMX6UL_CLK_ENFC_SEL 77 #define IMX6UL_CLK_CAN_SEL 78 #define IMX6UL_CLK_ECSPI_SEL 79 #define IMX6UL_CLK_UART_SEL 80 #define IMX6UL_CLK_QSPI1_SEL 81 #define IMX6UL_CLK_PERCLK_SEL 82 #define IMX6UL_CLK_LCDIF_SEL 83 #define IMX6UL_CLK_SIM_SEL 84 #define IMX6UL_CLK_PERIPH 85 #define IMX6UL_CLK_PERIPH2 86 #define IMX6UL_CLK_LDB_DI0_DIV_3_5 87 #define IMX6UL_CLK_LDB_DI0_DIV_7 88 #define IMX6UL_CLK_LDB_DI1_DIV_3_5 89 #define IMX6UL_CLK_LDB_DI1_DIV_7 90 #define IMX6UL_CLK_LDB_DI0_DIV_SEL 91 #define IMX6UL_CLK_LDB_DI1_DIV_SEL 92 #define IMX6UL_CLK_ARM 93 #define IMX6UL_CLK_PERIPH_CLK2 94 #define IMX6UL_CLK_PERIPH2_CLK2 95 #define IMX6UL_CLK_AHB 96 #define IMX6UL_CLK_MMDC_PODF 97 #define IMX6UL_CLK_AXI_PODF 98 #define IMX6UL_CLK_PERCLK 99 #define IMX6UL_CLK_IPG 100 #define IMX6UL_CLK_USDHC1_PODF 101 #define IMX6UL_CLK_USDHC2_PODF 102 #define IMX6UL_CLK_BCH_PODF 103 #define IMX6UL_CLK_GPMI_PODF 104 #define IMX6UL_CLK_EIM_SLOW_PODF 105 #define IMX6UL_CLK_SPDIF_PRED 106 #define IMX6UL_CLK_SPDIF_PODF 107 #define IMX6UL_CLK_SAI1_PRED 108 #define IMX6UL_CLK_SAI1_PODF 109 #define IMX6UL_CLK_SAI2_PRED 110 #define IMX6UL_CLK_SAI2_PODF 111 #define IMX6UL_CLK_SAI3_PRED 112 #define IMX6UL_CLK_SAI3_PODF 113 #define IMX6UL_CLK_LCDIF_PRED 114 #define IMX6UL_CLK_LCDIF_PODF 115 #define IMX6UL_CLK_SIM_PODF 116 #define IMX6UL_CLK_QSPI1_PDOF 117 #define IMX6UL_CLK_ENFC_PRED 118 #define IMX6UL_CLK_ENFC_PODF 119 #define IMX6UL_CLK_CAN_PODF 120 #define IMX6UL_CLK_ECSPI_PODF 121 #define IMX6UL_CLK_UART_PODF 122 #define IMX6UL_CLK_ADC1 123 #define IMX6UL_CLK_ADC2 124 #define IMX6UL_CLK_AIPSTZ1 125 #define IMX6UL_CLK_AIPSTZ2 126 #define IMX6UL_CLK_AIPSTZ3 127 #define IMX6UL_CLK_APBHDMA 128 #define IMX6UL_CLK_ASRC_IPG 129 #define IMX6UL_CLK_ASRC_MEM 130 #define IMX6UL_CLK_GPMI_BCH_APB 131 #define IMX6UL_CLK_GPMI_BCH 132 #define IMX6UL_CLK_GPMI_IO 133 #define IMX6UL_CLK_GPMI_APB 134 #define IMX6UL_CLK_CAAM_MEM 135 #define IMX6UL_CLK_CAAM_ACLK 136 #define IMX6UL_CLK_CAAM_IPG 137 #define IMX6UL_CLK_CSI 138 #define IMX6UL_CLK_ECSPI1 139 #define IMX6UL_CLK_ECSPI2 140 #define IMX6UL_CLK_ECSPI3 141 #define IMX6UL_CLK_ECSPI4 142 #define IMX6UL_CLK_EIM 143 #define IMX6UL_CLK_ENET 144 #define IMX6UL_CLK_ENET_AHB 145 #define IMX6UL_CLK_EPIT1 146 #define IMX6UL_CLK_EPIT2 147 #define IMX6UL_CLK_CAN1_IPG 148 #define IMX6UL_CLK_CAN1_SERIAL 149 #define IMX6UL_CLK_CAN2_IPG 150 #define IMX6UL_CLK_CAN2_SERIAL 151 #define IMX6UL_CLK_GPT1_BUS 152 #define IMX6UL_CLK_GPT1_SERIAL 153 #define IMX6UL_CLK_GPT2_BUS 154 #define IMX6UL_CLK_GPT2_SERIAL 155 #define IMX6UL_CLK_I2C1 156 #define IMX6UL_CLK_I2C2 157 #define IMX6UL_CLK_I2C3 158 #define IMX6UL_CLK_I2C4 159 #define IMX6UL_CLK_IOMUXC 160 #define IMX6UL_CLK_LCDIF_APB 161 #define IMX6UL_CLK_LCDIF_PIX 162 #define IMX6UL_CLK_MMDC_P0_FAST 163 #define IMX6UL_CLK_MMDC_P0_IPG 164 #define IMX6UL_CLK_OCOTP 165 #define IMX6UL_CLK_OCRAM 166 #define IMX6UL_CLK_PWM1 167 #define IMX6UL_CLK_PWM2 168 #define IMX6UL_CLK_PWM3 169 #define IMX6UL_CLK_PWM4 170 #define IMX6UL_CLK_PWM5 171 #define IMX6UL_CLK_PWM6 172 #define IMX6UL_CLK_PWM7 173 #define IMX6UL_CLK_PWM8 174 #define IMX6UL_CLK_PXP 175 #define IMX6UL_CLK_QSPI 176 #define IMX6UL_CLK_ROM 177 #define IMX6UL_CLK_SAI1 178 #define IMX6UL_CLK_SAI1_IPG 179 #define IMX6UL_CLK_SAI2 180 #define IMX6UL_CLK_SAI2_IPG 181 #define IMX6UL_CLK_SAI3 182 #define IMX6UL_CLK_SAI3_IPG 183 #define IMX6UL_CLK_SDMA 184 #define IMX6UL_CLK_SIM 185 #define IMX6UL_CLK_SIM_S 186 #define IMX6UL_CLK_SPBA 187 #define IMX6UL_CLK_SPDIF 188 #define IMX6UL_CLK_UART1_IPG 189 #define IMX6UL_CLK_UART1_SERIAL 190 #define IMX6UL_CLK_UART2_IPG 191 #define IMX6UL_CLK_UART2_SERIAL 192 #define IMX6UL_CLK_UART3_IPG 193 #define IMX6UL_CLK_UART3_SERIAL 194 #define IMX6UL_CLK_UART4_IPG 195 #define IMX6UL_CLK_UART4_SERIAL 196 #define IMX6UL_CLK_UART5_IPG 197 #define IMX6UL_CLK_UART5_SERIAL 198 #define IMX6UL_CLK_UART6_IPG 199 #define IMX6UL_CLK_UART6_SERIAL 200 #define IMX6UL_CLK_UART7_IPG 201 #define IMX6UL_CLK_UART7_SERIAL 202 #define IMX6UL_CLK_UART8_IPG 203 #define IMX6UL_CLK_UART8_SERIAL 204 #define IMX6UL_CLK_USBOH3 205 #define IMX6UL_CLK_USDHC1 206 #define IMX6UL_CLK_USDHC2 207 #define IMX6UL_CLK_WDOG1 208 #define IMX6UL_CLK_WDOG2 209 #define IMX6UL_CLK_WDOG3 210 #define IMX6UL_CLK_LDB_DI0 211 #define IMX6UL_CLK_AXI 212 #define IMX6UL_CLK_SPDIF_GCLK 213 #define IMX6UL_CLK_GPT_3M 214 #define IMX6UL_CLK_SIM2 215 #define IMX6UL_CLK_SIM1 216 #define IMX6UL_CLK_IPP_DI0 217 #define IMX6UL_CLK_IPP_DI1 218 #define IMX6UL_CA7_SECONDARY_SEL 219 #define IMX6UL_CLK_PER_BCH 220 #define IMX6UL_CLK_CSI_SEL 221 #define IMX6UL_CLK_CSI_PODF 222 #define IMX6UL_CLK_PLL3_120M 223 #define IMX6UL_CLK_KPP 224 #define IMX6ULL_CLK_ESAI_PRED 225 #define IMX6ULL_CLK_ESAI_PODF 226 #define IMX6ULL_CLK_ESAI_EXTAL 227 #define IMX6ULL_CLK_ESAI_MEM 228 #define IMX6ULL_CLK_ESAI_IPG 229 #define IMX6ULL_CLK_DCP_CLK 230 #define IMX6ULL_CLK_EPDC_PRE_SEL 231 #define IMX6ULL_CLK_EPDC_SEL 232 #define IMX6ULL_CLK_EPDC_PODF 233 #define IMX6ULL_CLK_EPDC_ACLK 234 #define IMX6ULL_CLK_EPDC_PIX 235 #define IMX6ULL_CLK_ESAI_SEL 236 #define IMX6UL_CLK_CKO1_SEL 237 #define IMX6UL_CLK_CKO1_PODF 238 #define IMX6UL_CLK_CKO1 239 #define IMX6UL_CLK_CKO2_SEL 240 #define IMX6UL_CLK_CKO2_PODF 241 #define IMX6UL_CLK_CKO2 242 #define IMX6UL_CLK_CKO 243 -#define IMX6UL_CLK_END 244 +#define IMX6UL_CLK_GPIO1 244 +#define IMX6UL_CLK_GPIO2 245 +#define IMX6UL_CLK_GPIO3 246 +#define IMX6UL_CLK_GPIO4 247 +#define IMX6UL_CLK_GPIO5 248 + +#define IMX6UL_CLK_END 249 #endif /* __DT_BINDINGS_CLOCK_IMX6UL_H */ Index: stable/12/sys/gnu/dts/include/dt-bindings/clock/maxim,max9485.h =================================================================== --- stable/12/sys/gnu/dts/include/dt-bindings/clock/maxim,max9485.h (nonexistent) +++ stable/12/sys/gnu/dts/include/dt-bindings/clock/maxim,max9485.h (revision 343012) @@ -0,0 +1,18 @@ +/* + * Copyright (C) 2018 Daniel Mack + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + */ + +#ifndef __DT_BINDINGS_MAX9485_CLK_H +#define __DT_BINDINGS_MAX9485_CLK_H + +#define MAX9485_MCLKOUT 0 +#define MAX9485_CLKOUT 1 +#define MAX9485_CLKOUT1 2 +#define MAX9485_CLKOUT2 3 + +#endif /* __DT_BINDINGS_MAX9485_CLK_H */ Property changes on: stable/12/sys/gnu/dts/include/dt-bindings/clock/maxim,max9485.h ___________________________________________________________________ Added: fbsd:nokeywords ## -0,0 +1 ## +yes \ No newline at end of property Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:mime-type ## -0,0 +1 ## +text/plain \ No newline at end of property Index: stable/12/sys/gnu/dts/include/dt-bindings/clock/px30-cru.h =================================================================== --- stable/12/sys/gnu/dts/include/dt-bindings/clock/px30-cru.h (nonexistent) +++ stable/12/sys/gnu/dts/include/dt-bindings/clock/px30-cru.h (revision 343012) @@ -0,0 +1,389 @@ +/* SPDX-License-Identifier: GPL-2.0 */ + +#ifndef _DT_BINDINGS_CLK_ROCKCHIP_PX30_H +#define _DT_BINDINGS_CLK_ROCKCHIP_PX30_H + +/* core clocks */ +#define PLL_APLL 1 +#define PLL_DPLL 2 +#define PLL_CPLL 3 +#define PLL_NPLL 4 +#define APLL_BOOST_H 5 +#define APLL_BOOST_L 6 +#define ARMCLK 7 + +/* sclk gates (special clocks) */ +#define USB480M 14 +#define SCLK_PDM 15 +#define SCLK_I2S0_TX 16 +#define SCLK_I2S0_TX_OUT 17 +#define SCLK_I2S0_RX 18 +#define SCLK_I2S0_RX_OUT 19 +#define SCLK_I2S1 20 +#define SCLK_I2S1_OUT 21 +#define SCLK_I2S2 22 +#define SCLK_I2S2_OUT 23 +#define SCLK_UART1 24 +#define SCLK_UART2 25 +#define SCLK_UART3 26 +#define SCLK_UART4 27 +#define SCLK_UART5 28 +#define SCLK_I2C0 29 +#define SCLK_I2C1 30 +#define SCLK_I2C2 31 +#define SCLK_I2C3 32 +#define SCLK_I2C4 33 +#define SCLK_PWM0 34 +#define SCLK_PWM1 35 +#define SCLK_SPI0 36 +#define SCLK_SPI1 37 +#define SCLK_TIMER0 38 +#define SCLK_TIMER1 39 +#define SCLK_TIMER2 40 +#define SCLK_TIMER3 41 +#define SCLK_TIMER4 42 +#define SCLK_TIMER5 43 +#define SCLK_TSADC 44 +#define SCLK_SARADC 45 +#define SCLK_OTP 46 +#define SCLK_OTP_USR 47 +#define SCLK_CRYPTO 48 +#define SCLK_CRYPTO_APK 49 +#define SCLK_DDRC 50 +#define SCLK_ISP 51 +#define SCLK_CIF_OUT 52 +#define SCLK_RGA_CORE 53 +#define SCLK_VOPB_PWM 54 +#define SCLK_NANDC 55 +#define SCLK_SDIO 56 +#define SCLK_EMMC 57 +#define SCLK_SFC 58 +#define SCLK_SDMMC 59 +#define SCLK_OTG_ADP 60 +#define SCLK_GMAC_SRC 61 +#define SCLK_GMAC 62 +#define SCLK_GMAC_RX_TX 63 +#define SCLK_MAC_REF 64 +#define SCLK_MAC_REFOUT 65 +#define SCLK_MAC_OUT 66 +#define SCLK_SDMMC_DRV 67 +#define SCLK_SDMMC_SAMPLE 68 +#define SCLK_SDIO_DRV 69 +#define SCLK_SDIO_SAMPLE 70 +#define SCLK_EMMC_DRV 71 +#define SCLK_EMMC_SAMPLE 72 +#define SCLK_GPU 73 +#define SCLK_PVTM 74 +#define SCLK_CORE_VPU 75 +#define SCLK_GMAC_RMII 76 +#define SCLK_UART2_SRC 77 +#define SCLK_NANDC_DIV 78 +#define SCLK_NANDC_DIV50 79 +#define SCLK_SDIO_DIV 80 +#define SCLK_SDIO_DIV50 81 +#define SCLK_EMMC_DIV 82 +#define SCLK_EMMC_DIV50 83 +#define SCLK_DDRCLK 84 +#define SCLK_UART1_SRC 85 + +/* dclk gates */ +#define DCLK_VOPB 150 +#define DCLK_VOPL 151 + +/* aclk gates */ +#define ACLK_GPU 170 +#define ACLK_BUS_PRE 171 +#define ACLK_CRYPTO 172 +#define ACLK_VI_PRE 173 +#define ACLK_VO_PRE 174 +#define ACLK_VPU 175 +#define ACLK_PERI_PRE 176 +#define ACLK_GMAC 178 +#define ACLK_CIF 179 +#define ACLK_ISP 180 +#define ACLK_VOPB 181 +#define ACLK_VOPL 182 +#define ACLK_RGA 183 +#define ACLK_GIC 184 +#define ACLK_DCF 186 +#define ACLK_DMAC 187 +#define ACLK_BUS_SRC 188 +#define ACLK_PERI_SRC 189 + +/* hclk gates */ +#define HCLK_BUS_PRE 240 +#define HCLK_CRYPTO 241 +#define HCLK_VI_PRE 242 +#define HCLK_VO_PRE 243 +#define HCLK_VPU 244 +#define HCLK_PERI_PRE 245 +#define HCLK_MMC_NAND 246 +#define HCLK_SDMMC 247 +#define HCLK_USB 248 +#define HCLK_CIF 249 +#define HCLK_ISP 250 +#define HCLK_VOPB 251 +#define HCLK_VOPL 252 +#define HCLK_RGA 253 +#define HCLK_NANDC 254 +#define HCLK_SDIO 255 +#define HCLK_EMMC 256 +#define HCLK_SFC 257 +#define HCLK_OTG 258 +#define HCLK_HOST 259 +#define HCLK_HOST_ARB 260 +#define HCLK_PDM 261 +#define HCLK_I2S0 262 +#define HCLK_I2S1 263 +#define HCLK_I2S2 264 + +/* pclk gates */ +#define PCLK_BUS_PRE 320 +#define PCLK_DDR 321 +#define PCLK_VO_PRE 322 +#define PCLK_GMAC 323 +#define PCLK_MIPI_DSI 324 +#define PCLK_MIPIDSIPHY 325 +#define PCLK_MIPICSIPHY 326 +#define PCLK_USB_GRF 327 +#define PCLK_DCF 328 +#define PCLK_UART1 329 +#define PCLK_UART2 330 +#define PCLK_UART3 331 +#define PCLK_UART4 332 +#define PCLK_UART5 333 +#define PCLK_I2C0 334 +#define PCLK_I2C1 335 +#define PCLK_I2C2 336 +#define PCLK_I2C3 337 +#define PCLK_I2C4 338 +#define PCLK_PWM0 339 +#define PCLK_PWM1 340 +#define PCLK_SPI0 341 +#define PCLK_SPI1 342 +#define PCLK_SARADC 343 +#define PCLK_TSADC 344 +#define PCLK_TIMER 345 +#define PCLK_OTP_NS 346 +#define PCLK_WDT_NS 347 +#define PCLK_GPIO1 348 +#define PCLK_GPIO2 349 +#define PCLK_GPIO3 350 +#define PCLK_ISP 351 +#define PCLK_CIF 352 +#define PCLK_OTP_PHY 353 + +#define CLK_NR_CLKS (PCLK_OTP_PHY + 1) + +/* pmu-clocks indices */ + +#define PLL_GPLL 1 + +#define SCLK_RTC32K_PMU 4 +#define SCLK_WIFI_PMU 5 +#define SCLK_UART0_PMU 6 +#define SCLK_PVTM_PMU 7 +#define PCLK_PMU_PRE 8 +#define SCLK_REF24M_PMU 9 +#define SCLK_USBPHY_REF 10 +#define SCLK_MIPIDSIPHY_REF 11 + +#define XIN24M_DIV 12 + +#define PCLK_GPIO0_PMU 20 +#define PCLK_UART0_PMU 21 + +#define CLKPMU_NR_CLKS (PCLK_UART0_PMU + 1) + +/* soft-reset indices */ +#define SRST_CORE0_PO 0 +#define SRST_CORE1_PO 1 +#define SRST_CORE2_PO 2 +#define SRST_CORE3_PO 3 +#define SRST_CORE0 4 +#define SRST_CORE1 5 +#define SRST_CORE2 6 +#define SRST_CORE3 7 +#define SRST_CORE0_DBG 8 +#define SRST_CORE1_DBG 9 +#define SRST_CORE2_DBG 10 +#define SRST_CORE3_DBG 11 +#define SRST_TOPDBG 12 +#define SRST_CORE_NOC 13 +#define SRST_STRC_A 14 +#define SRST_L2C 15 + +#define SRST_DAP 16 +#define SRST_CORE_PVTM 17 +#define SRST_GPU 18 +#define SRST_GPU_NIU 19 +#define SRST_UPCTL2 20 +#define SRST_UPCTL2_A 21 +#define SRST_UPCTL2_P 22 +#define SRST_MSCH 23 +#define SRST_MSCH_P 24 +#define SRST_DDRMON_P 25 +#define SRST_DDRSTDBY_P 26 +#define SRST_DDRSTDBY 27 +#define SRST_DDRGRF_p 28 +#define SRST_AXI_SPLIT_A 29 +#define SRST_AXI_CMD_A 30 +#define SRST_AXI_CMD_P 31 + +#define SRST_DDRPHY 32 +#define SRST_DDRPHYDIV 33 +#define SRST_DDRPHY_P 34 +#define SRST_VPU_A 36 +#define SRST_VPU_NIU_A 37 +#define SRST_VPU_H 38 +#define SRST_VPU_NIU_H 39 +#define SRST_VI_NIU_A 40 +#define SRST_VI_NIU_H 41 +#define SRST_ISP_H 42 +#define SRST_ISP 43 +#define SRST_CIF_A 44 +#define SRST_CIF_H 45 +#define SRST_CIF_PCLKIN 46 +#define SRST_MIPICSIPHY_P 47 + +#define SRST_VO_NIU_A 48 +#define SRST_VO_NIU_H 49 +#define SRST_VO_NIU_P 50 +#define SRST_VOPB_A 51 +#define SRST_VOPB_H 52 +#define SRST_VOPB 53 +#define SRST_PWM_VOPB 54 +#define SRST_VOPL_A 55 +#define SRST_VOPL_H 56 +#define SRST_VOPL 57 +#define SRST_RGA_A 58 +#define SRST_RGA_H 59 +#define SRST_RGA 60 +#define SRST_MIPIDSI_HOST_P 61 +#define SRST_MIPIDSIPHY_P 62 +#define SRST_VPU_CORE 63 + +#define SRST_PERI_NIU_A 64 +#define SRST_USB_NIU_H 65 +#define SRST_USB2OTG_H 66 +#define SRST_USB2OTG 67 +#define SRST_USB2OTG_ADP 68 +#define SRST_USB2HOST_H 69 +#define SRST_USB2HOST_ARB_H 70 +#define SRST_USB2HOST_AUX_H 71 +#define SRST_USB2HOST_EHCI 72 +#define SRST_USB2HOST 73 +#define SRST_USBPHYPOR 74 +#define SRST_USBPHY_OTG_PORT 75 +#define SRST_USBPHY_HOST_PORT 76 +#define SRST_USBPHY_GRF 77 +#define SRST_CPU_BOOST_P 78 +#define SRST_CPU_BOOST 79 + +#define SRST_MMC_NAND_NIU_H 80 +#define SRST_SDIO_H 81 +#define SRST_EMMC_H 82 +#define SRST_SFC_H 83 +#define SRST_SFC 84 +#define SRST_SDCARD_NIU_H 85 +#define SRST_SDMMC_H 86 +#define SRST_NANDC_H 89 +#define SRST_NANDC 90 +#define SRST_GMAC_NIU_A 92 +#define SRST_GMAC_NIU_P 93 +#define SRST_GMAC_A 94 + +#define SRST_PMU_NIU_P 96 +#define SRST_PMU_SGRF_P 97 +#define SRST_PMU_GRF_P 98 +#define SRST_PMU 99 +#define SRST_PMU_MEM_P 100 +#define SRST_PMU_GPIO0_P 101 +#define SRST_PMU_UART0_P 102 +#define SRST_PMU_CRU_P 103 +#define SRST_PMU_PVTM 104 +#define SRST_PMU_UART 105 +#define SRST_PMU_NIU_H 106 +#define SRST_PMU_DDR_FAIL_SAVE 107 +#define SRST_PMU_CORE_PERF_A 108 +#define SRST_PMU_CORE_GRF_P 109 +#define SRST_PMU_GPU_PERF_A 110 +#define SRST_PMU_GPU_GRF_P 111 + +#define SRST_CRYPTO_NIU_A 112 +#define SRST_CRYPTO_NIU_H 113 +#define SRST_CRYPTO_A 114 +#define SRST_CRYPTO_H 115 +#define SRST_CRYPTO 116 +#define SRST_CRYPTO_APK 117 +#define SRST_BUS_NIU_H 120 +#define SRST_USB_NIU_P 121 +#define SRST_BUS_TOP_NIU_P 122 +#define SRST_INTMEM_A 123 +#define SRST_GIC_A 124 +#define SRST_ROM_H 126 +#define SRST_DCF_A 127 + +#define SRST_DCF_P 128 +#define SRST_PDM_H 129 +#define SRST_PDM 130 +#define SRST_I2S0_H 131 +#define SRST_I2S0_TX 132 +#define SRST_I2S1_H 133 +#define SRST_I2S1 134 +#define SRST_I2S2_H 135 +#define SRST_I2S2 136 +#define SRST_UART1_P 137 +#define SRST_UART1 138 +#define SRST_UART2_P 139 +#define SRST_UART2 140 +#define SRST_UART3_P 141 +#define SRST_UART3 142 +#define SRST_UART4_P 143 + +#define SRST_UART4 144 +#define SRST_UART5_P 145 +#define SRST_UART5 146 +#define SRST_I2C0_P 147 +#define SRST_I2C0 148 +#define SRST_I2C1_P 149 +#define SRST_I2C1 150 +#define SRST_I2C2_P 151 +#define SRST_I2C2 152 +#define SRST_I2C3_P 153 +#define SRST_I2C3 154 +#define SRST_PWM0_P 157 +#define SRST_PWM0 158 +#define SRST_PWM1_P 159 + +#define SRST_PWM1 160 +#define SRST_SPI0_P 161 +#define SRST_SPI0 162 +#define SRST_SPI1_P 163 +#define SRST_SPI1 164 +#define SRST_SARADC_P 165 +#define SRST_SARADC 166 +#define SRST_TSADC_P 167 +#define SRST_TSADC 168 +#define SRST_TIMER_P 169 +#define SRST_TIMER0 170 +#define SRST_TIMER1 171 +#define SRST_TIMER2 172 +#define SRST_TIMER3 173 +#define SRST_TIMER4 174 +#define SRST_TIMER5 175 + +#define SRST_OTP_NS_P 176 +#define SRST_OTP_NS_SBPI 177 +#define SRST_OTP_NS_USR 178 +#define SRST_OTP_PHY_P 179 +#define SRST_OTP_PHY 180 +#define SRST_WDT_NS_P 181 +#define SRST_GPIO1_P 182 +#define SRST_GPIO2_P 183 +#define SRST_GPIO3_P 184 +#define SRST_SGRF_P 185 +#define SRST_GRF_P 186 +#define SRST_I2S0_RX 191 + +#endif Property changes on: stable/12/sys/gnu/dts/include/dt-bindings/clock/px30-cru.h ___________________________________________________________________ Added: fbsd:nokeywords ## -0,0 +1 ## +yes \ No newline at end of property Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:mime-type ## -0,0 +1 ## +text/plain \ No newline at end of property Index: stable/12/sys/gnu/dts/include/dt-bindings/clock/pxa-clock.h =================================================================== --- stable/12/sys/gnu/dts/include/dt-bindings/clock/pxa-clock.h (revision 343011) +++ stable/12/sys/gnu/dts/include/dt-bindings/clock/pxa-clock.h (revision 343012) @@ -1,77 +1,78 @@ /* * Inspired by original work from pxa2xx-regs.h by Nicolas Pitre * Copyright (C) 2014 Robert Jarzmik * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; either version 2 of the License, or * (at your option) any later version. */ #ifndef __DT_BINDINGS_CLOCK_PXA2XX_H__ #define __DT_BINDINGS_CLOCK_PXA2XX_H__ #define CLK_NONE 0 #define CLK_1WIRE 1 #define CLK_AC97 2 #define CLK_AC97CONF 3 #define CLK_ASSP 4 #define CLK_BOOT 5 #define CLK_BTUART 6 #define CLK_CAMERA 7 #define CLK_CIR 8 #define CLK_CORE 9 #define CLK_DMC 10 #define CLK_FFUART 11 #define CLK_FICP 12 #define CLK_GPIO 13 #define CLK_HSIO2 14 #define CLK_HWUART 15 #define CLK_I2C 16 #define CLK_I2S 17 #define CLK_IM 18 #define CLK_INC 19 #define CLK_ISC 20 #define CLK_KEYPAD 21 #define CLK_LCD 22 #define CLK_MEMC 23 #define CLK_MEMSTK 24 #define CLK_MINI_IM 25 #define CLK_MINI_LCD 26 #define CLK_MMC 27 #define CLK_MMC1 28 #define CLK_MMC2 29 #define CLK_MMC3 30 #define CLK_MSL 31 #define CLK_MSL0 32 #define CLK_MVED 33 #define CLK_NAND 34 #define CLK_NSSP 35 #define CLK_OSTIMER 36 #define CLK_PWM0 37 #define CLK_PWM1 38 #define CLK_PWM2 39 #define CLK_PWM3 40 #define CLK_PWRI2C 41 #define CLK_PXA300_GCU 42 #define CLK_PXA320_GCU 43 #define CLK_SMC 44 #define CLK_SSP 45 #define CLK_SSP1 46 #define CLK_SSP2 47 #define CLK_SSP3 48 #define CLK_SSP4 49 #define CLK_STUART 50 #define CLK_TOUCH 51 #define CLK_TPM 52 #define CLK_UDC 53 #define CLK_USB 54 #define CLK_USB2 55 #define CLK_USBH 56 #define CLK_USBHOST 57 #define CLK_USIM 58 #define CLK_USIM1 59 #define CLK_USMI0 60 -#define CLK_MAX 61 +#define CLK_OSC32k768 61 +#define CLK_MAX 62 #endif Index: stable/12/sys/gnu/dts/include/dt-bindings/clock/qcom,dispcc-sdm845.h =================================================================== --- stable/12/sys/gnu/dts/include/dt-bindings/clock/qcom,dispcc-sdm845.h (nonexistent) +++ stable/12/sys/gnu/dts/include/dt-bindings/clock/qcom,dispcc-sdm845.h (revision 343012) @@ -0,0 +1,45 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (c) 2018, The Linux Foundation. All rights reserved. + */ + +#ifndef _DT_BINDINGS_CLK_SDM_DISP_CC_SDM845_H +#define _DT_BINDINGS_CLK_SDM_DISP_CC_SDM845_H + +/* DISP_CC clock registers */ +#define DISP_CC_MDSS_AHB_CLK 0 +#define DISP_CC_MDSS_AXI_CLK 1 +#define DISP_CC_MDSS_BYTE0_CLK 2 +#define DISP_CC_MDSS_BYTE0_CLK_SRC 3 +#define DISP_CC_MDSS_BYTE0_INTF_CLK 4 +#define DISP_CC_MDSS_BYTE1_CLK 5 +#define DISP_CC_MDSS_BYTE1_CLK_SRC 6 +#define DISP_CC_MDSS_BYTE1_INTF_CLK 7 +#define DISP_CC_MDSS_ESC0_CLK 8 +#define DISP_CC_MDSS_ESC0_CLK_SRC 9 +#define DISP_CC_MDSS_ESC1_CLK 10 +#define DISP_CC_MDSS_ESC1_CLK_SRC 11 +#define DISP_CC_MDSS_MDP_CLK 12 +#define DISP_CC_MDSS_MDP_CLK_SRC 13 +#define DISP_CC_MDSS_MDP_LUT_CLK 14 +#define DISP_CC_MDSS_PCLK0_CLK 15 +#define DISP_CC_MDSS_PCLK0_CLK_SRC 16 +#define DISP_CC_MDSS_PCLK1_CLK 17 +#define DISP_CC_MDSS_PCLK1_CLK_SRC 18 +#define DISP_CC_MDSS_ROT_CLK 19 +#define DISP_CC_MDSS_ROT_CLK_SRC 20 +#define DISP_CC_MDSS_RSCC_AHB_CLK 21 +#define DISP_CC_MDSS_RSCC_VSYNC_CLK 22 +#define DISP_CC_MDSS_VSYNC_CLK 23 +#define DISP_CC_MDSS_VSYNC_CLK_SRC 24 +#define DISP_CC_PLL0 25 +#define DISP_CC_MDSS_BYTE0_DIV_CLK_SRC 26 +#define DISP_CC_MDSS_BYTE1_DIV_CLK_SRC 27 + +/* DISP_CC Reset */ +#define DISP_CC_MDSS_RSCC_BCR 0 + +/* DISP_CC GDSCR */ +#define MDSS_GDSC 0 + +#endif Property changes on: stable/12/sys/gnu/dts/include/dt-bindings/clock/qcom,dispcc-sdm845.h ___________________________________________________________________ Added: fbsd:nokeywords ## -0,0 +1 ## +yes \ No newline at end of property Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:mime-type ## -0,0 +1 ## +text/plain \ No newline at end of property Index: stable/12/sys/gnu/dts/include/dt-bindings/clock/qcom,gcc-sdm845.h =================================================================== --- stable/12/sys/gnu/dts/include/dt-bindings/clock/qcom,gcc-sdm845.h (revision 343011) +++ stable/12/sys/gnu/dts/include/dt-bindings/clock/qcom,gcc-sdm845.h (revision 343012) @@ -1,239 +1,241 @@ /* SPDX-License-Identifier: GPL-2.0 */ /* * Copyright (c) 2018, The Linux Foundation. All rights reserved. */ #ifndef _DT_BINDINGS_CLK_SDM_GCC_SDM845_H #define _DT_BINDINGS_CLK_SDM_GCC_SDM845_H /* GCC clock registers */ #define GCC_AGGRE_NOC_PCIE_TBU_CLK 0 #define GCC_AGGRE_UFS_CARD_AXI_CLK 1 #define GCC_AGGRE_UFS_PHY_AXI_CLK 2 #define GCC_AGGRE_USB3_PRIM_AXI_CLK 3 #define GCC_AGGRE_USB3_SEC_AXI_CLK 4 #define GCC_BOOT_ROM_AHB_CLK 5 #define GCC_CAMERA_AHB_CLK 6 #define GCC_CAMERA_AXI_CLK 7 #define GCC_CAMERA_XO_CLK 8 #define GCC_CE1_AHB_CLK 9 #define GCC_CE1_AXI_CLK 10 #define GCC_CE1_CLK 11 #define GCC_CFG_NOC_USB3_PRIM_AXI_CLK 12 #define GCC_CFG_NOC_USB3_SEC_AXI_CLK 13 #define GCC_CPUSS_AHB_CLK 14 #define GCC_CPUSS_AHB_CLK_SRC 15 #define GCC_CPUSS_RBCPR_CLK 16 #define GCC_CPUSS_RBCPR_CLK_SRC 17 #define GCC_DDRSS_GPU_AXI_CLK 18 #define GCC_DISP_AHB_CLK 19 #define GCC_DISP_AXI_CLK 20 #define GCC_DISP_GPLL0_CLK_SRC 21 #define GCC_DISP_GPLL0_DIV_CLK_SRC 22 #define GCC_DISP_XO_CLK 23 #define GCC_GP1_CLK 24 #define GCC_GP1_CLK_SRC 25 #define GCC_GP2_CLK 26 #define GCC_GP2_CLK_SRC 27 #define GCC_GP3_CLK 28 #define GCC_GP3_CLK_SRC 29 #define GCC_GPU_CFG_AHB_CLK 30 #define GCC_GPU_GPLL0_CLK_SRC 31 #define GCC_GPU_GPLL0_DIV_CLK_SRC 32 #define GCC_GPU_MEMNOC_GFX_CLK 33 #define GCC_GPU_SNOC_DVM_GFX_CLK 34 #define GCC_MSS_AXIS2_CLK 35 #define GCC_MSS_CFG_AHB_CLK 36 #define GCC_MSS_GPLL0_DIV_CLK_SRC 37 #define GCC_MSS_MFAB_AXIS_CLK 38 #define GCC_MSS_Q6_MEMNOC_AXI_CLK 39 #define GCC_MSS_SNOC_AXI_CLK 40 #define GCC_PCIE_0_AUX_CLK 41 #define GCC_PCIE_0_AUX_CLK_SRC 42 #define GCC_PCIE_0_CFG_AHB_CLK 43 #define GCC_PCIE_0_CLKREF_CLK 44 #define GCC_PCIE_0_MSTR_AXI_CLK 45 #define GCC_PCIE_0_PIPE_CLK 46 #define GCC_PCIE_0_SLV_AXI_CLK 47 #define GCC_PCIE_0_SLV_Q2A_AXI_CLK 48 #define GCC_PCIE_1_AUX_CLK 49 #define GCC_PCIE_1_AUX_CLK_SRC 50 #define GCC_PCIE_1_CFG_AHB_CLK 51 #define GCC_PCIE_1_CLKREF_CLK 52 #define GCC_PCIE_1_MSTR_AXI_CLK 53 #define GCC_PCIE_1_PIPE_CLK 54 #define GCC_PCIE_1_SLV_AXI_CLK 55 #define GCC_PCIE_1_SLV_Q2A_AXI_CLK 56 #define GCC_PCIE_PHY_AUX_CLK 57 #define GCC_PCIE_PHY_REFGEN_CLK 58 #define GCC_PCIE_PHY_REFGEN_CLK_SRC 59 #define GCC_PDM2_CLK 60 #define GCC_PDM2_CLK_SRC 61 #define GCC_PDM_AHB_CLK 62 #define GCC_PDM_XO4_CLK 63 #define GCC_PRNG_AHB_CLK 64 #define GCC_QMIP_CAMERA_AHB_CLK 65 #define GCC_QMIP_DISP_AHB_CLK 66 #define GCC_QMIP_VIDEO_AHB_CLK 67 #define GCC_QUPV3_WRAP0_S0_CLK 68 #define GCC_QUPV3_WRAP0_S0_CLK_SRC 69 #define GCC_QUPV3_WRAP0_S1_CLK 70 #define GCC_QUPV3_WRAP0_S1_CLK_SRC 71 #define GCC_QUPV3_WRAP0_S2_CLK 72 #define GCC_QUPV3_WRAP0_S2_CLK_SRC 73 #define GCC_QUPV3_WRAP0_S3_CLK 74 #define GCC_QUPV3_WRAP0_S3_CLK_SRC 75 #define GCC_QUPV3_WRAP0_S4_CLK 76 #define GCC_QUPV3_WRAP0_S4_CLK_SRC 77 #define GCC_QUPV3_WRAP0_S5_CLK 78 #define GCC_QUPV3_WRAP0_S5_CLK_SRC 79 #define GCC_QUPV3_WRAP0_S6_CLK 80 #define GCC_QUPV3_WRAP0_S6_CLK_SRC 81 #define GCC_QUPV3_WRAP0_S7_CLK 82 #define GCC_QUPV3_WRAP0_S7_CLK_SRC 83 #define GCC_QUPV3_WRAP1_S0_CLK 84 #define GCC_QUPV3_WRAP1_S0_CLK_SRC 85 #define GCC_QUPV3_WRAP1_S1_CLK 86 #define GCC_QUPV3_WRAP1_S1_CLK_SRC 87 #define GCC_QUPV3_WRAP1_S2_CLK 88 #define GCC_QUPV3_WRAP1_S2_CLK_SRC 89 #define GCC_QUPV3_WRAP1_S3_CLK 90 #define GCC_QUPV3_WRAP1_S3_CLK_SRC 91 #define GCC_QUPV3_WRAP1_S4_CLK 92 #define GCC_QUPV3_WRAP1_S4_CLK_SRC 93 #define GCC_QUPV3_WRAP1_S5_CLK 94 #define GCC_QUPV3_WRAP1_S5_CLK_SRC 95 #define GCC_QUPV3_WRAP1_S6_CLK 96 #define GCC_QUPV3_WRAP1_S6_CLK_SRC 97 #define GCC_QUPV3_WRAP1_S7_CLK 98 #define GCC_QUPV3_WRAP1_S7_CLK_SRC 99 #define GCC_QUPV3_WRAP_0_M_AHB_CLK 100 #define GCC_QUPV3_WRAP_0_S_AHB_CLK 101 #define GCC_QUPV3_WRAP_1_M_AHB_CLK 102 #define GCC_QUPV3_WRAP_1_S_AHB_CLK 103 #define GCC_SDCC2_AHB_CLK 104 #define GCC_SDCC2_APPS_CLK 105 #define GCC_SDCC2_APPS_CLK_SRC 106 #define GCC_SDCC4_AHB_CLK 107 #define GCC_SDCC4_APPS_CLK 108 #define GCC_SDCC4_APPS_CLK_SRC 109 #define GCC_SYS_NOC_CPUSS_AHB_CLK 110 #define GCC_TSIF_AHB_CLK 111 #define GCC_TSIF_INACTIVITY_TIMERS_CLK 112 #define GCC_TSIF_REF_CLK 113 #define GCC_TSIF_REF_CLK_SRC 114 #define GCC_UFS_CARD_AHB_CLK 115 #define GCC_UFS_CARD_AXI_CLK 116 #define GCC_UFS_CARD_AXI_CLK_SRC 117 #define GCC_UFS_CARD_CLKREF_CLK 118 #define GCC_UFS_CARD_ICE_CORE_CLK 119 #define GCC_UFS_CARD_ICE_CORE_CLK_SRC 120 #define GCC_UFS_CARD_PHY_AUX_CLK 121 #define GCC_UFS_CARD_PHY_AUX_CLK_SRC 122 #define GCC_UFS_CARD_RX_SYMBOL_0_CLK 123 #define GCC_UFS_CARD_RX_SYMBOL_1_CLK 124 #define GCC_UFS_CARD_TX_SYMBOL_0_CLK 125 #define GCC_UFS_CARD_UNIPRO_CORE_CLK 126 #define GCC_UFS_CARD_UNIPRO_CORE_CLK_SRC 127 #define GCC_UFS_MEM_CLKREF_CLK 128 #define GCC_UFS_PHY_AHB_CLK 129 #define GCC_UFS_PHY_AXI_CLK 130 #define GCC_UFS_PHY_AXI_CLK_SRC 131 #define GCC_UFS_PHY_ICE_CORE_CLK 132 #define GCC_UFS_PHY_ICE_CORE_CLK_SRC 133 #define GCC_UFS_PHY_PHY_AUX_CLK 134 #define GCC_UFS_PHY_PHY_AUX_CLK_SRC 135 #define GCC_UFS_PHY_RX_SYMBOL_0_CLK 136 #define GCC_UFS_PHY_RX_SYMBOL_1_CLK 137 #define GCC_UFS_PHY_TX_SYMBOL_0_CLK 138 #define GCC_UFS_PHY_UNIPRO_CORE_CLK 139 #define GCC_UFS_PHY_UNIPRO_CORE_CLK_SRC 140 #define GCC_USB30_PRIM_MASTER_CLK 141 #define GCC_USB30_PRIM_MASTER_CLK_SRC 142 #define GCC_USB30_PRIM_MOCK_UTMI_CLK 143 #define GCC_USB30_PRIM_MOCK_UTMI_CLK_SRC 144 #define GCC_USB30_PRIM_SLEEP_CLK 145 #define GCC_USB30_SEC_MASTER_CLK 146 #define GCC_USB30_SEC_MASTER_CLK_SRC 147 #define GCC_USB30_SEC_MOCK_UTMI_CLK 148 #define GCC_USB30_SEC_MOCK_UTMI_CLK_SRC 149 #define GCC_USB30_SEC_SLEEP_CLK 150 #define GCC_USB3_PRIM_CLKREF_CLK 151 #define GCC_USB3_PRIM_PHY_AUX_CLK 152 #define GCC_USB3_PRIM_PHY_AUX_CLK_SRC 153 #define GCC_USB3_PRIM_PHY_COM_AUX_CLK 154 #define GCC_USB3_PRIM_PHY_PIPE_CLK 155 #define GCC_USB3_SEC_CLKREF_CLK 156 #define GCC_USB3_SEC_PHY_AUX_CLK 157 #define GCC_USB3_SEC_PHY_AUX_CLK_SRC 158 #define GCC_USB3_SEC_PHY_PIPE_CLK 159 #define GCC_USB3_SEC_PHY_COM_AUX_CLK 160 #define GCC_USB_PHY_CFG_AHB2PHY_CLK 161 #define GCC_VIDEO_AHB_CLK 162 #define GCC_VIDEO_AXI_CLK 163 #define GCC_VIDEO_XO_CLK 164 #define GPLL0 165 #define GPLL0_OUT_EVEN 166 #define GPLL0_OUT_MAIN 167 #define GCC_GPU_IREF_CLK 168 #define GCC_SDCC1_AHB_CLK 169 #define GCC_SDCC1_APPS_CLK 170 #define GCC_SDCC1_ICE_CORE_CLK 171 #define GCC_SDCC1_APPS_CLK_SRC 172 #define GCC_SDCC1_ICE_CORE_CLK_SRC 173 #define GCC_APC_VS_CLK 174 #define GCC_GPU_VS_CLK 175 #define GCC_MSS_VS_CLK 176 #define GCC_VDDA_VS_CLK 177 #define GCC_VDDCX_VS_CLK 178 #define GCC_VDDMX_VS_CLK 179 #define GCC_VS_CTRL_AHB_CLK 180 #define GCC_VS_CTRL_CLK 181 #define GCC_VS_CTRL_CLK_SRC 182 #define GCC_VSENSOR_CLK_SRC 183 #define GPLL4 184 +#define GCC_CPUSS_DVM_BUS_CLK 185 +#define GCC_CPUSS_GNOC_CLK 186 /* GCC Resets */ #define GCC_MMSS_BCR 0 #define GCC_PCIE_0_BCR 1 #define GCC_PCIE_1_BCR 2 #define GCC_PCIE_PHY_BCR 3 #define GCC_PDM_BCR 4 #define GCC_PRNG_BCR 5 #define GCC_QUPV3_WRAPPER_0_BCR 6 #define GCC_QUPV3_WRAPPER_1_BCR 7 #define GCC_QUSB2PHY_PRIM_BCR 8 #define GCC_QUSB2PHY_SEC_BCR 9 #define GCC_SDCC2_BCR 10 #define GCC_SDCC4_BCR 11 #define GCC_TSIF_BCR 12 #define GCC_UFS_CARD_BCR 13 #define GCC_UFS_PHY_BCR 14 #define GCC_USB30_PRIM_BCR 15 #define GCC_USB30_SEC_BCR 16 #define GCC_USB3_PHY_PRIM_BCR 17 #define GCC_USB3PHY_PHY_PRIM_BCR 18 #define GCC_USB3_DP_PHY_PRIM_BCR 19 #define GCC_USB3_PHY_SEC_BCR 20 #define GCC_USB3PHY_PHY_SEC_BCR 21 #define GCC_USB3_DP_PHY_SEC_BCR 22 #define GCC_USB_PHY_CFG_AHB2PHY_BCR 23 #define GCC_PCIE_0_PHY_BCR 24 #define GCC_PCIE_1_PHY_BCR 25 /* GCC GDSCRs */ #define PCIE_0_GDSC 0 #define PCIE_1_GDSC 1 #define UFS_CARD_GDSC 2 #define UFS_PHY_GDSC 3 #define USB30_PRIM_GDSC 4 #define USB30_SEC_GDSC 5 #define HLOS1_VOTE_AGGRE_NOC_MMU_AUDIO_TBU_GDSC 6 #define HLOS1_VOTE_AGGRE_NOC_MMU_PCIE_TBU_GDSC 7 #define HLOS1_VOTE_AGGRE_NOC_MMU_TBU1_GDSC 8 #define HLOS1_VOTE_AGGRE_NOC_MMU_TBU2_GDSC 9 #define HLOS1_VOTE_MMNOC_MMU_TBU_HF0_GDSC 10 #define HLOS1_VOTE_MMNOC_MMU_TBU_HF1_GDSC 11 #define HLOS1_VOTE_MMNOC_MMU_TBU_SF_GDSC 12 #endif Index: stable/12/sys/gnu/dts/include/dt-bindings/clock/r9a06g032-sysctrl.h =================================================================== --- stable/12/sys/gnu/dts/include/dt-bindings/clock/r9a06g032-sysctrl.h (nonexistent) +++ stable/12/sys/gnu/dts/include/dt-bindings/clock/r9a06g032-sysctrl.h (revision 343012) @@ -0,0 +1,148 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * R9A06G032 sysctrl IDs + * + * Copyright (C) 2018 Renesas Electronics Europe Limited + * + * Michel Pollet , + */ + +#ifndef __DT_BINDINGS_R9A06G032_SYSCTRL_H__ +#define __DT_BINDINGS_R9A06G032_SYSCTRL_H__ + +#define R9A06G032_CLK_PLL_USB 1 +#define R9A06G032_CLK_48 1 /* AKA CLK_PLL_USB */ +#define R9A06G032_MSEBIS_CLK 3 /* AKA CLKOUT_D16 */ +#define R9A06G032_MSEBIM_CLK 3 /* AKA CLKOUT_D16 */ +#define R9A06G032_CLK_DDRPHY_PLLCLK 5 /* AKA CLKOUT_D1OR2 */ +#define R9A06G032_CLK50 6 /* AKA CLKOUT_D20 */ +#define R9A06G032_CLK25 7 /* AKA CLKOUT_D40 */ +#define R9A06G032_CLK125 9 /* AKA CLKOUT_D8 */ +#define R9A06G032_CLK_P5_PG1 17 /* AKA DIV_P5_PG */ +#define R9A06G032_CLK_REF_SYNC 21 /* AKA DIV_REF_SYNC */ +#define R9A06G032_CLK_25_PG4 26 +#define R9A06G032_CLK_25_PG5 27 +#define R9A06G032_CLK_25_PG6 28 +#define R9A06G032_CLK_25_PG7 29 +#define R9A06G032_CLK_25_PG8 30 +#define R9A06G032_CLK_ADC 31 +#define R9A06G032_CLK_ECAT100 32 +#define R9A06G032_CLK_HSR100 33 +#define R9A06G032_CLK_I2C0 34 +#define R9A06G032_CLK_I2C1 35 +#define R9A06G032_CLK_MII_REF 36 +#define R9A06G032_CLK_NAND 37 +#define R9A06G032_CLK_NOUSBP2_PG6 38 +#define R9A06G032_CLK_P1_PG2 39 +#define R9A06G032_CLK_P1_PG3 40 +#define R9A06G032_CLK_P1_PG4 41 +#define R9A06G032_CLK_P4_PG3 42 +#define R9A06G032_CLK_P4_PG4 43 +#define R9A06G032_CLK_P6_PG1 44 +#define R9A06G032_CLK_P6_PG2 45 +#define R9A06G032_CLK_P6_PG3 46 +#define R9A06G032_CLK_P6_PG4 47 +#define R9A06G032_CLK_PCI_USB 48 +#define R9A06G032_CLK_QSPI0 49 +#define R9A06G032_CLK_QSPI1 50 +#define R9A06G032_CLK_RGMII_REF 51 +#define R9A06G032_CLK_RMII_REF 52 +#define R9A06G032_CLK_SDIO0 53 +#define R9A06G032_CLK_SDIO1 54 +#define R9A06G032_CLK_SERCOS100 55 +#define R9A06G032_CLK_SLCD 56 +#define R9A06G032_CLK_SPI0 57 +#define R9A06G032_CLK_SPI1 58 +#define R9A06G032_CLK_SPI2 59 +#define R9A06G032_CLK_SPI3 60 +#define R9A06G032_CLK_SPI4 61 +#define R9A06G032_CLK_SPI5 62 +#define R9A06G032_CLK_SWITCH 63 +#define R9A06G032_HCLK_ECAT125 65 +#define R9A06G032_HCLK_PINCONFIG 66 +#define R9A06G032_HCLK_SERCOS 67 +#define R9A06G032_HCLK_SGPIO2 68 +#define R9A06G032_HCLK_SGPIO3 69 +#define R9A06G032_HCLK_SGPIO4 70 +#define R9A06G032_HCLK_TIMER0 71 +#define R9A06G032_HCLK_TIMER1 72 +#define R9A06G032_HCLK_USBF 73 +#define R9A06G032_HCLK_USBH 74 +#define R9A06G032_HCLK_USBPM 75 +#define R9A06G032_CLK_48_PG_F 76 +#define R9A06G032_CLK_48_PG4 77 +#define R9A06G032_CLK_DDRPHY_PCLK 81 /* AKA CLK_REF_SYNC_D4 */ +#define R9A06G032_CLK_FW 81 /* AKA CLK_REF_SYNC_D4 */ +#define R9A06G032_CLK_CRYPTO 81 /* AKA CLK_REF_SYNC_D4 */ +#define R9A06G032_CLK_A7MP 84 /* AKA DIV_CA7 */ +#define R9A06G032_HCLK_CAN0 85 +#define R9A06G032_HCLK_CAN1 86 +#define R9A06G032_HCLK_DELTASIGMA 87 +#define R9A06G032_HCLK_PWMPTO 88 +#define R9A06G032_HCLK_RSV 89 +#define R9A06G032_HCLK_SGPIO0 90 +#define R9A06G032_HCLK_SGPIO1 91 +#define R9A06G032_RTOS_MDC 92 +#define R9A06G032_CLK_CM3 93 +#define R9A06G032_CLK_DDRC 94 +#define R9A06G032_CLK_ECAT25 95 +#define R9A06G032_CLK_HSR50 96 +#define R9A06G032_CLK_HW_RTOS 97 +#define R9A06G032_CLK_SERCOS50 98 +#define R9A06G032_HCLK_ADC 99 +#define R9A06G032_HCLK_CM3 100 +#define R9A06G032_HCLK_CRYPTO_EIP150 101 +#define R9A06G032_HCLK_CRYPTO_EIP93 102 +#define R9A06G032_HCLK_DDRC 103 +#define R9A06G032_HCLK_DMA0 104 +#define R9A06G032_HCLK_DMA1 105 +#define R9A06G032_HCLK_GMAC0 106 +#define R9A06G032_HCLK_GMAC1 107 +#define R9A06G032_HCLK_GPIO0 108 +#define R9A06G032_HCLK_GPIO1 109 +#define R9A06G032_HCLK_GPIO2 110 +#define R9A06G032_HCLK_HSR 111 +#define R9A06G032_HCLK_I2C0 112 +#define R9A06G032_HCLK_I2C1 113 +#define R9A06G032_HCLK_LCD 114 +#define R9A06G032_HCLK_MSEBI_M 115 +#define R9A06G032_HCLK_MSEBI_S 116 +#define R9A06G032_HCLK_NAND 117 +#define R9A06G032_HCLK_PG_I 118 +#define R9A06G032_HCLK_PG19 119 +#define R9A06G032_HCLK_PG20 120 +#define R9A06G032_HCLK_PG3 121 +#define R9A06G032_HCLK_PG4 122 +#define R9A06G032_HCLK_QSPI0 123 +#define R9A06G032_HCLK_QSPI1 124 +#define R9A06G032_HCLK_ROM 125 +#define R9A06G032_HCLK_RTC 126 +#define R9A06G032_HCLK_SDIO0 127 +#define R9A06G032_HCLK_SDIO1 128 +#define R9A06G032_HCLK_SEMAP 129 +#define R9A06G032_HCLK_SPI0 130 +#define R9A06G032_HCLK_SPI1 131 +#define R9A06G032_HCLK_SPI2 132 +#define R9A06G032_HCLK_SPI3 133 +#define R9A06G032_HCLK_SPI4 134 +#define R9A06G032_HCLK_SPI5 135 +#define R9A06G032_HCLK_SWITCH 136 +#define R9A06G032_HCLK_SWITCH_RG 137 +#define R9A06G032_HCLK_UART0 138 +#define R9A06G032_HCLK_UART1 139 +#define R9A06G032_HCLK_UART2 140 +#define R9A06G032_HCLK_UART3 141 +#define R9A06G032_HCLK_UART4 142 +#define R9A06G032_HCLK_UART5 143 +#define R9A06G032_HCLK_UART6 144 +#define R9A06G032_HCLK_UART7 145 +#define R9A06G032_CLK_UART0 146 +#define R9A06G032_CLK_UART1 147 +#define R9A06G032_CLK_UART2 148 +#define R9A06G032_CLK_UART3 149 +#define R9A06G032_CLK_UART4 150 +#define R9A06G032_CLK_UART5 151 +#define R9A06G032_CLK_UART6 152 +#define R9A06G032_CLK_UART7 153 + +#endif /* __DT_BINDINGS_R9A06G032_SYSCTRL_H__ */ Property changes on: stable/12/sys/gnu/dts/include/dt-bindings/clock/r9a06g032-sysctrl.h ___________________________________________________________________ Added: fbsd:nokeywords ## -0,0 +1 ## +yes \ No newline at end of property Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:mime-type ## -0,0 +1 ## +text/plain \ No newline at end of property Index: stable/12/sys/gnu/dts/include/dt-bindings/clock/rk3399-ddr.h =================================================================== --- stable/12/sys/gnu/dts/include/dt-bindings/clock/rk3399-ddr.h (nonexistent) +++ stable/12/sys/gnu/dts/include/dt-bindings/clock/rk3399-ddr.h (revision 343012) @@ -0,0 +1,56 @@ +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ + +#ifndef DT_BINDINGS_DDR_H +#define DT_BINDINGS_DDR_H + +/* + * DDR3 SDRAM Standard Speed Bins include tCK, tRCD, tRP, tRAS and tRC for + * each corresponding bin. + */ + +/* DDR3-800 (5-5-5) */ +#define DDR3_800D 0 +/* DDR3-800 (6-6-6) */ +#define DDR3_800E 1 +/* DDR3-1066 (6-6-6) */ +#define DDR3_1066E 2 +/* DDR3-1066 (7-7-7) */ +#define DDR3_1066F 3 +/* DDR3-1066 (8-8-8) */ +#define DDR3_1066G 4 +/* DDR3-1333 (7-7-7) */ +#define DDR3_1333F 5 +/* DDR3-1333 (8-8-8) */ +#define DDR3_1333G 6 +/* DDR3-1333 (9-9-9) */ +#define DDR3_1333H 7 +/* DDR3-1333 (10-10-10) */ +#define DDR3_1333J 8 +/* DDR3-1600 (8-8-8) */ +#define DDR3_1600G 9 +/* DDR3-1600 (9-9-9) */ +#define DDR3_1600H 10 +/* DDR3-1600 (10-10-10) */ +#define DDR3_1600J 11 +/* DDR3-1600 (11-11-11) */ +#define DDR3_1600K 12 +/* DDR3-1600 (10-10-10) */ +#define DDR3_1866J 13 +/* DDR3-1866 (11-11-11) */ +#define DDR3_1866K 14 +/* DDR3-1866 (12-12-12) */ +#define DDR3_1866L 15 +/* DDR3-1866 (13-13-13) */ +#define DDR3_1866M 16 +/* DDR3-2133 (11-11-11) */ +#define DDR3_2133K 17 +/* DDR3-2133 (12-12-12) */ +#define DDR3_2133L 18 +/* DDR3-2133 (13-13-13) */ +#define DDR3_2133M 19 +/* DDR3-2133 (14-14-14) */ +#define DDR3_2133N 20 +/* DDR3 ATF default */ +#define DDR3_DEFAULT 21 + +#endif Property changes on: stable/12/sys/gnu/dts/include/dt-bindings/clock/rk3399-ddr.h ___________________________________________________________________ Added: fbsd:nokeywords ## -0,0 +1 ## +yes \ No newline at end of property Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:mime-type ## -0,0 +1 ## +text/plain \ No newline at end of property Index: stable/12/sys/gnu/dts/include/dt-bindings/clock/sun8i-r40-ccu.h =================================================================== --- stable/12/sys/gnu/dts/include/dt-bindings/clock/sun8i-r40-ccu.h (revision 343011) +++ stable/12/sys/gnu/dts/include/dt-bindings/clock/sun8i-r40-ccu.h (revision 343012) @@ -1,187 +1,191 @@ /* * Copyright (C) 2017 Icenowy Zheng * * This file is dual-licensed: you can use it either under the terms * of the GPL or the X11 license, at your option. Note that this dual * licensing only applies to this file, and not this project as a * whole. * * a) This file is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as * published by the Free Software Foundation; either version 2 of the * License, or (at your option) any later version. * * This file is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * Or, alternatively, * * b) Permission is hereby granted, free of charge, to any person * obtaining a copy of this software and associated documentation * files (the "Software"), to deal in the Software without * restriction, including without limitation the rights to use, * copy, modify, merge, publish, distribute, sublicense, and/or * sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following * conditions: * * The above copyright notice and this permission notice shall be * included in all copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR * OTHER DEALINGS IN THE SOFTWARE. */ #ifndef _DT_BINDINGS_CLK_SUN8I_R40_H_ #define _DT_BINDINGS_CLK_SUN8I_R40_H_ +#define CLK_PLL_VIDEO0 7 + +#define CLK_PLL_VIDEO1 16 + #define CLK_CPU 24 #define CLK_BUS_MIPI_DSI 29 #define CLK_BUS_CE 30 #define CLK_BUS_DMA 31 #define CLK_BUS_MMC0 32 #define CLK_BUS_MMC1 33 #define CLK_BUS_MMC2 34 #define CLK_BUS_MMC3 35 #define CLK_BUS_NAND 36 #define CLK_BUS_DRAM 37 #define CLK_BUS_EMAC 38 #define CLK_BUS_TS 39 #define CLK_BUS_HSTIMER 40 #define CLK_BUS_SPI0 41 #define CLK_BUS_SPI1 42 #define CLK_BUS_SPI2 43 #define CLK_BUS_SPI3 44 #define CLK_BUS_SATA 45 #define CLK_BUS_OTG 46 #define CLK_BUS_EHCI0 47 #define CLK_BUS_EHCI1 48 #define CLK_BUS_EHCI2 49 #define CLK_BUS_OHCI0 50 #define CLK_BUS_OHCI1 51 #define CLK_BUS_OHCI2 52 #define CLK_BUS_VE 53 #define CLK_BUS_MP 54 #define CLK_BUS_DEINTERLACE 55 #define CLK_BUS_CSI0 56 #define CLK_BUS_CSI1 57 #define CLK_BUS_HDMI1 58 #define CLK_BUS_HDMI0 59 #define CLK_BUS_DE 60 #define CLK_BUS_TVE0 61 #define CLK_BUS_TVE1 62 #define CLK_BUS_TVE_TOP 63 #define CLK_BUS_GMAC 64 #define CLK_BUS_GPU 65 #define CLK_BUS_TVD0 66 #define CLK_BUS_TVD1 67 #define CLK_BUS_TVD2 68 #define CLK_BUS_TVD3 69 #define CLK_BUS_TVD_TOP 70 #define CLK_BUS_TCON_LCD0 71 #define CLK_BUS_TCON_LCD1 72 #define CLK_BUS_TCON_TV0 73 #define CLK_BUS_TCON_TV1 74 #define CLK_BUS_TCON_TOP 75 #define CLK_BUS_CODEC 76 #define CLK_BUS_SPDIF 77 #define CLK_BUS_AC97 78 #define CLK_BUS_PIO 79 #define CLK_BUS_IR0 80 #define CLK_BUS_IR1 81 #define CLK_BUS_THS 82 #define CLK_BUS_KEYPAD 83 #define CLK_BUS_I2S0 84 #define CLK_BUS_I2S1 85 #define CLK_BUS_I2S2 86 #define CLK_BUS_I2C0 87 #define CLK_BUS_I2C1 88 #define CLK_BUS_I2C2 89 #define CLK_BUS_I2C3 90 #define CLK_BUS_CAN 91 #define CLK_BUS_SCR 92 #define CLK_BUS_PS20 93 #define CLK_BUS_PS21 94 #define CLK_BUS_I2C4 95 #define CLK_BUS_UART0 96 #define CLK_BUS_UART1 97 #define CLK_BUS_UART2 98 #define CLK_BUS_UART3 99 #define CLK_BUS_UART4 100 #define CLK_BUS_UART5 101 #define CLK_BUS_UART6 102 #define CLK_BUS_UART7 103 #define CLK_BUS_DBG 104 #define CLK_THS 105 #define CLK_NAND 106 #define CLK_MMC0 107 #define CLK_MMC1 108 #define CLK_MMC2 109 #define CLK_MMC3 110 #define CLK_TS 111 #define CLK_CE 112 #define CLK_SPI0 113 #define CLK_SPI1 114 #define CLK_SPI2 115 #define CLK_SPI3 116 #define CLK_I2S0 117 #define CLK_I2S1 118 #define CLK_I2S2 119 #define CLK_AC97 120 #define CLK_SPDIF 121 #define CLK_KEYPAD 122 #define CLK_SATA 123 #define CLK_USB_PHY0 124 #define CLK_USB_PHY1 125 #define CLK_USB_PHY2 126 #define CLK_USB_OHCI0 127 #define CLK_USB_OHCI1 128 #define CLK_USB_OHCI2 129 #define CLK_IR0 130 #define CLK_IR1 131 #define CLK_DRAM_VE 133 #define CLK_DRAM_CSI0 134 #define CLK_DRAM_CSI1 135 #define CLK_DRAM_TS 136 #define CLK_DRAM_TVD 137 #define CLK_DRAM_MP 138 #define CLK_DRAM_DEINTERLACE 139 #define CLK_DE 140 #define CLK_MP 141 #define CLK_TCON_LCD0 142 #define CLK_TCON_LCD1 143 #define CLK_TCON_TV0 144 #define CLK_TCON_TV1 145 #define CLK_DEINTERLACE 146 #define CLK_CSI1_MCLK 147 #define CLK_CSI_SCLK 148 #define CLK_CSI0_MCLK 149 #define CLK_VE 150 #define CLK_CODEC 151 #define CLK_AVS 152 #define CLK_HDMI 153 #define CLK_HDMI_SLOW 154 #define CLK_DSI_DPHY 156 #define CLK_TVE0 157 #define CLK_TVE1 158 #define CLK_TVD0 159 #define CLK_TVD1 160 #define CLK_TVD2 161 #define CLK_TVD3 162 #define CLK_GPU 163 #define CLK_OUTA 164 #define CLK_OUTB 165 #endif /* _DT_BINDINGS_CLK_SUN8I_R40_H_ */ Index: stable/12/sys/gnu/dts/include/dt-bindings/clock/sun8i-tcon-top.h =================================================================== --- stable/12/sys/gnu/dts/include/dt-bindings/clock/sun8i-tcon-top.h (nonexistent) +++ stable/12/sys/gnu/dts/include/dt-bindings/clock/sun8i-tcon-top.h (revision 343012) @@ -0,0 +1,11 @@ +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ +/* Copyright (C) 2018 Jernej Skrabec */ + +#ifndef _DT_BINDINGS_CLOCK_SUN8I_TCON_TOP_H_ +#define _DT_BINDINGS_CLOCK_SUN8I_TCON_TOP_H_ + +#define CLK_TCON_TOP_TV0 0 +#define CLK_TCON_TOP_TV1 1 +#define CLK_TCON_TOP_DSI 2 + +#endif /* _DT_BINDINGS_CLOCK_SUN8I_TCON_TOP_H_ */ Property changes on: stable/12/sys/gnu/dts/include/dt-bindings/clock/sun8i-tcon-top.h ___________________________________________________________________ Added: fbsd:nokeywords ## -0,0 +1 ## +yes \ No newline at end of property Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:mime-type ## -0,0 +1 ## +text/plain \ No newline at end of property Index: stable/12/sys/gnu/dts/include/dt-bindings/dma/jz4780-dma.h =================================================================== --- stable/12/sys/gnu/dts/include/dt-bindings/dma/jz4780-dma.h (nonexistent) +++ stable/12/sys/gnu/dts/include/dt-bindings/dma/jz4780-dma.h (revision 343012) @@ -0,0 +1,49 @@ +#ifndef __DT_BINDINGS_DMA_JZ4780_DMA_H__ +#define __DT_BINDINGS_DMA_JZ4780_DMA_H__ + +/* + * Request type numbers for the JZ4780 DMA controller (written to the DRTn + * register for the channel). + */ +#define JZ4780_DMA_I2S1_TX 0x4 +#define JZ4780_DMA_I2S1_RX 0x5 +#define JZ4780_DMA_I2S0_TX 0x6 +#define JZ4780_DMA_I2S0_RX 0x7 +#define JZ4780_DMA_AUTO 0x8 +#define JZ4780_DMA_SADC_RX 0x9 +#define JZ4780_DMA_UART4_TX 0xc +#define JZ4780_DMA_UART4_RX 0xd +#define JZ4780_DMA_UART3_TX 0xe +#define JZ4780_DMA_UART3_RX 0xf +#define JZ4780_DMA_UART2_TX 0x10 +#define JZ4780_DMA_UART2_RX 0x11 +#define JZ4780_DMA_UART1_TX 0x12 +#define JZ4780_DMA_UART1_RX 0x13 +#define JZ4780_DMA_UART0_TX 0x14 +#define JZ4780_DMA_UART0_RX 0x15 +#define JZ4780_DMA_SSI0_TX 0x16 +#define JZ4780_DMA_SSI0_RX 0x17 +#define JZ4780_DMA_SSI1_TX 0x18 +#define JZ4780_DMA_SSI1_RX 0x19 +#define JZ4780_DMA_MSC0_TX 0x1a +#define JZ4780_DMA_MSC0_RX 0x1b +#define JZ4780_DMA_MSC1_TX 0x1c +#define JZ4780_DMA_MSC1_RX 0x1d +#define JZ4780_DMA_MSC2_TX 0x1e +#define JZ4780_DMA_MSC2_RX 0x1f +#define JZ4780_DMA_PCM0_TX 0x20 +#define JZ4780_DMA_PCM0_RX 0x21 +#define JZ4780_DMA_SMB0_TX 0x24 +#define JZ4780_DMA_SMB0_RX 0x25 +#define JZ4780_DMA_SMB1_TX 0x26 +#define JZ4780_DMA_SMB1_RX 0x27 +#define JZ4780_DMA_SMB2_TX 0x28 +#define JZ4780_DMA_SMB2_RX 0x29 +#define JZ4780_DMA_SMB3_TX 0x2a +#define JZ4780_DMA_SMB3_RX 0x2b +#define JZ4780_DMA_SMB4_TX 0x2c +#define JZ4780_DMA_SMB4_RX 0x2d +#define JZ4780_DMA_DES_TX 0x2e +#define JZ4780_DMA_DES_RX 0x2f + +#endif /* __DT_BINDINGS_DMA_JZ4780_DMA_H__ */ Property changes on: stable/12/sys/gnu/dts/include/dt-bindings/dma/jz4780-dma.h ___________________________________________________________________ Added: fbsd:nokeywords ## -0,0 +1 ## +yes \ No newline at end of property Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:mime-type ## -0,0 +1 ## +text/plain \ No newline at end of property Index: stable/12/sys/gnu/dts/include/dt-bindings/gce/mt8173-gce.h =================================================================== --- stable/12/sys/gnu/dts/include/dt-bindings/gce/mt8173-gce.h (nonexistent) +++ stable/12/sys/gnu/dts/include/dt-bindings/gce/mt8173-gce.h (revision 343012) @@ -0,0 +1,44 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (c) 2018 MediaTek Inc. + * Author: Houlong Wei + * + */ + +#ifndef _DT_BINDINGS_GCE_MT8173_H +#define _DT_BINDINGS_GCE_MT8173_H + +/* GCE HW thread priority */ +#define CMDQ_THR_PRIO_LOWEST 0 +#define CMDQ_THR_PRIO_HIGHEST 1 + +/* GCE SUBSYS */ +#define SUBSYS_1400XXXX 1 +#define SUBSYS_1401XXXX 2 +#define SUBSYS_1402XXXX 3 + +/* GCE HW EVENT */ +#define CMDQ_EVENT_DISP_OVL0_SOF 11 +#define CMDQ_EVENT_DISP_OVL1_SOF 12 +#define CMDQ_EVENT_DISP_RDMA0_SOF 13 +#define CMDQ_EVENT_DISP_RDMA1_SOF 14 +#define CMDQ_EVENT_DISP_RDMA2_SOF 15 +#define CMDQ_EVENT_DISP_WDMA0_SOF 16 +#define CMDQ_EVENT_DISP_WDMA1_SOF 17 +#define CMDQ_EVENT_DISP_OVL0_EOF 39 +#define CMDQ_EVENT_DISP_OVL1_EOF 40 +#define CMDQ_EVENT_DISP_RDMA0_EOF 41 +#define CMDQ_EVENT_DISP_RDMA1_EOF 42 +#define CMDQ_EVENT_DISP_RDMA2_EOF 43 +#define CMDQ_EVENT_DISP_WDMA0_EOF 44 +#define CMDQ_EVENT_DISP_WDMA1_EOF 45 +#define CMDQ_EVENT_MUTEX0_STREAM_EOF 53 +#define CMDQ_EVENT_MUTEX1_STREAM_EOF 54 +#define CMDQ_EVENT_MUTEX2_STREAM_EOF 55 +#define CMDQ_EVENT_MUTEX3_STREAM_EOF 56 +#define CMDQ_EVENT_MUTEX4_STREAM_EOF 57 +#define CMDQ_EVENT_DISP_RDMA0_UNDERRUN 63 +#define CMDQ_EVENT_DISP_RDMA1_UNDERRUN 64 +#define CMDQ_EVENT_DISP_RDMA2_UNDERRUN 65 + +#endif Property changes on: stable/12/sys/gnu/dts/include/dt-bindings/gce/mt8173-gce.h ___________________________________________________________________ Added: fbsd:nokeywords ## -0,0 +1 ## +yes \ No newline at end of property Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:mime-type ## -0,0 +1 ## +text/plain \ No newline at end of property Index: stable/12/sys/gnu/dts/include/dt-bindings/iio/adc/at91-sama5d2_adc.h =================================================================== --- stable/12/sys/gnu/dts/include/dt-bindings/iio/adc/at91-sama5d2_adc.h (nonexistent) +++ stable/12/sys/gnu/dts/include/dt-bindings/iio/adc/at91-sama5d2_adc.h (revision 343012) @@ -0,0 +1,16 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * This header provides constants for configuring the AT91 SAMA5D2 ADC + */ + +#ifndef _DT_BINDINGS_IIO_ADC_AT91_SAMA5D2_ADC_H +#define _DT_BINDINGS_IIO_ADC_AT91_SAMA5D2_ADC_H + +/* X relative position channel index */ +#define AT91_SAMA5D2_ADC_X_CHANNEL 24 +/* Y relative position channel index */ +#define AT91_SAMA5D2_ADC_Y_CHANNEL 25 +/* pressure channel index */ +#define AT91_SAMA5D2_ADC_P_CHANNEL 26 + +#endif Property changes on: stable/12/sys/gnu/dts/include/dt-bindings/iio/adc/at91-sama5d2_adc.h ___________________________________________________________________ Added: fbsd:nokeywords ## -0,0 +1 ## +yes \ No newline at end of property Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:mime-type ## -0,0 +1 ## +text/plain \ No newline at end of property Index: stable/12/sys/gnu/dts/include/dt-bindings/memory/mt2712-larb-port.h =================================================================== --- stable/12/sys/gnu/dts/include/dt-bindings/memory/mt2712-larb-port.h (nonexistent) +++ stable/12/sys/gnu/dts/include/dt-bindings/memory/mt2712-larb-port.h (revision 343012) @@ -0,0 +1,95 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (c) 2017 MediaTek Inc. + * Author: Yong Wu + */ +#ifndef __DTS_IOMMU_PORT_MT2712_H +#define __DTS_IOMMU_PORT_MT2712_H + +#define MTK_M4U_ID(larb, port) (((larb) << 5) | (port)) + +#define M4U_LARB0_ID 0 +#define M4U_LARB1_ID 1 +#define M4U_LARB2_ID 2 +#define M4U_LARB3_ID 3 +#define M4U_LARB4_ID 4 +#define M4U_LARB5_ID 5 +#define M4U_LARB6_ID 6 +#define M4U_LARB7_ID 7 +#define M4U_LARB8_ID 8 +#define M4U_LARB9_ID 9 + +/* larb0 */ +#define M4U_PORT_DISP_OVL0 MTK_M4U_ID(M4U_LARB0_ID, 0) +#define M4U_PORT_DISP_RDMA0 MTK_M4U_ID(M4U_LARB0_ID, 1) +#define M4U_PORT_DISP_WDMA0 MTK_M4U_ID(M4U_LARB0_ID, 2) +#define M4U_PORT_DISP_OD_R MTK_M4U_ID(M4U_LARB0_ID, 3) +#define M4U_PORT_DISP_OD_W MTK_M4U_ID(M4U_LARB0_ID, 4) +#define M4U_PORT_MDP_RDMA0 MTK_M4U_ID(M4U_LARB0_ID, 5) +#define M4U_PORT_MDP_WDMA MTK_M4U_ID(M4U_LARB0_ID, 6) +#define M4U_PORT_DISP_RDMA2 MTK_M4U_ID(M4U_LARB0_ID, 7) + +/* larb1 */ +#define M4U_PORT_HW_VDEC_MC_EXT MTK_M4U_ID(M4U_LARB1_ID, 0) +#define M4U_PORT_HW_VDEC_PP_EXT MTK_M4U_ID(M4U_LARB1_ID, 1) +#define M4U_PORT_HW_VDEC_UFO_EXT MTK_M4U_ID(M4U_LARB1_ID, 2) +#define M4U_PORT_HW_VDEC_VLD_EXT MTK_M4U_ID(M4U_LARB1_ID, 3) +#define M4U_PORT_HW_VDEC_VLD2_EXT MTK_M4U_ID(M4U_LARB1_ID, 4) +#define M4U_PORT_HW_VDEC_AVC_MV_EXT MTK_M4U_ID(M4U_LARB1_ID, 5) +#define M4U_PORT_HW_VDEC_PRED_RD_EXT MTK_M4U_ID(M4U_LARB1_ID, 6) +#define M4U_PORT_HW_VDEC_PRED_WR_EXT MTK_M4U_ID(M4U_LARB1_ID, 7) +#define M4U_PORT_HW_VDEC_PPWRAP_EXT MTK_M4U_ID(M4U_LARB1_ID, 8) +#define M4U_PORT_HW_VDEC_TILE MTK_M4U_ID(M4U_LARB1_ID, 9) +#define M4U_PORT_HW_IMG_RESZ_EXT MTK_M4U_ID(M4U_LARB1_ID, 10) + +/* larb2 */ +#define M4U_PORT_CAM_DMA0 MTK_M4U_ID(M4U_LARB2_ID, 0) +#define M4U_PORT_CAM_DMA1 MTK_M4U_ID(M4U_LARB2_ID, 1) +#define M4U_PORT_CAM_DMA2 MTK_M4U_ID(M4U_LARB2_ID, 2) + +/* larb3 */ +#define M4U_PORT_VENC_RCPU MTK_M4U_ID(M4U_LARB3_ID, 0) +#define M4U_PORT_VENC_REC MTK_M4U_ID(M4U_LARB3_ID, 1) +#define M4U_PORT_VENC_BSDMA MTK_M4U_ID(M4U_LARB3_ID, 2) +#define M4U_PORT_VENC_SV_COMV MTK_M4U_ID(M4U_LARB3_ID, 3) +#define M4U_PORT_VENC_RD_COMV MTK_M4U_ID(M4U_LARB3_ID, 4) +#define M4U_PORT_VENC_CUR_CHROMA MTK_M4U_ID(M4U_LARB3_ID, 5) +#define M4U_PORT_VENC_REF_CHROMA MTK_M4U_ID(M4U_LARB3_ID, 6) +#define M4U_PORT_VENC_CUR_LUMA MTK_M4U_ID(M4U_LARB3_ID, 7) +#define M4U_PORT_VENC_REF_LUMA MTK_M4U_ID(M4U_LARB3_ID, 8) + +/* larb4 */ +#define M4U_PORT_DISP_OVL1 MTK_M4U_ID(M4U_LARB4_ID, 0) +#define M4U_PORT_DISP_RDMA1 MTK_M4U_ID(M4U_LARB4_ID, 1) +#define M4U_PORT_DISP_WDMA1 MTK_M4U_ID(M4U_LARB4_ID, 2) +#define M4U_PORT_DISP_OD1_R MTK_M4U_ID(M4U_LARB4_ID, 3) +#define M4U_PORT_DISP_OD1_W MTK_M4U_ID(M4U_LARB4_ID, 4) +#define M4U_PORT_MDP_RDMA1 MTK_M4U_ID(M4U_LARB4_ID, 5) +#define M4U_PORT_MDP_WROT1 MTK_M4U_ID(M4U_LARB4_ID, 6) + +/* larb5 */ +#define M4U_PORT_DISP_OVL2 MTK_M4U_ID(M4U_LARB5_ID, 0) +#define M4U_PORT_DISP_WDMA2 MTK_M4U_ID(M4U_LARB5_ID, 1) +#define M4U_PORT_MDP_RDMA2 MTK_M4U_ID(M4U_LARB5_ID, 2) +#define M4U_PORT_MDP_WROT0 MTK_M4U_ID(M4U_LARB5_ID, 3) + +/* larb6 */ +#define M4U_PORT_JPGDEC_WDMA_0 MTK_M4U_ID(M4U_LARB6_ID, 0) +#define M4U_PORT_JPGDEC_WDMA_1 MTK_M4U_ID(M4U_LARB6_ID, 1) +#define M4U_PORT_JPGDEC_BSDMA_0 MTK_M4U_ID(M4U_LARB6_ID, 2) +#define M4U_PORT_JPGDEC_BSDMA_1 MTK_M4U_ID(M4U_LARB6_ID, 3) + +/* larb7 */ +#define M4U_PORT_MDP_RDMA3 MTK_M4U_ID(M4U_LARB7_ID, 0) +#define M4U_PORT_MDP_WROT2 MTK_M4U_ID(M4U_LARB7_ID, 1) + +/* larb8 */ +#define M4U_PORT_VDO MTK_M4U_ID(M4U_LARB8_ID, 0) +#define M4U_PORT_NR MTK_M4U_ID(M4U_LARB8_ID, 1) +#define M4U_PORT_WR_CHANNEL0 MTK_M4U_ID(M4U_LARB8_ID, 2) + +/* larb9 */ +#define M4U_PORT_TVD MTK_M4U_ID(M4U_LARB9_ID, 0) +#define M4U_PORT_WR_CHANNEL1 MTK_M4U_ID(M4U_LARB9_ID, 1) + +#endif Property changes on: stable/12/sys/gnu/dts/include/dt-bindings/memory/mt2712-larb-port.h ___________________________________________________________________ Added: fbsd:nokeywords ## -0,0 +1 ## +yes \ No newline at end of property Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:mime-type ## -0,0 +1 ## +text/plain \ No newline at end of property Index: stable/12/sys/gnu/dts/include/dt-bindings/pinctrl/at91.h =================================================================== --- stable/12/sys/gnu/dts/include/dt-bindings/pinctrl/at91.h (revision 343011) +++ stable/12/sys/gnu/dts/include/dt-bindings/pinctrl/at91.h (revision 343012) @@ -1,42 +1,46 @@ /* * This header provides constants for most at91 pinctrl bindings. * * Copyright (C) 2013 Jean-Christophe PLAGNIOL-VILLARD * * GPLv2 only */ #ifndef __DT_BINDINGS_AT91_PINCTRL_H__ #define __DT_BINDINGS_AT91_PINCTRL_H__ #define AT91_PINCTRL_NONE (0 << 0) #define AT91_PINCTRL_PULL_UP (1 << 0) #define AT91_PINCTRL_MULTI_DRIVE (1 << 1) #define AT91_PINCTRL_DEGLITCH (1 << 2) #define AT91_PINCTRL_PULL_DOWN (1 << 3) #define AT91_PINCTRL_DIS_SCHMIT (1 << 4) #define AT91_PINCTRL_OUTPUT (1 << 7) #define AT91_PINCTRL_OUTPUT_VAL(x) ((x & 0x1) << 8) #define AT91_PINCTRL_DEBOUNCE (1 << 16) #define AT91_PINCTRL_DEBOUNCE_VAL(x) (x << 17) #define AT91_PINCTRL_PULL_UP_DEGLITCH (AT91_PINCTRL_PULL_UP | AT91_PINCTRL_DEGLITCH) #define AT91_PINCTRL_DRIVE_STRENGTH_DEFAULT (0x0 << 5) #define AT91_PINCTRL_DRIVE_STRENGTH_LOW (0x1 << 5) #define AT91_PINCTRL_DRIVE_STRENGTH_MED (0x2 << 5) #define AT91_PINCTRL_DRIVE_STRENGTH_HI (0x3 << 5) #define AT91_PIOA 0 #define AT91_PIOB 1 #define AT91_PIOC 2 #define AT91_PIOD 3 #define AT91_PIOE 4 #define AT91_PERIPH_GPIO 0 #define AT91_PERIPH_A 1 #define AT91_PERIPH_B 2 #define AT91_PERIPH_C 3 #define AT91_PERIPH_D 4 +#define ATMEL_PIO_DRVSTR_LO 1 +#define ATMEL_PIO_DRVSTR_ME 2 +#define ATMEL_PIO_DRVSTR_HI 3 + #endif /* __DT_BINDINGS_AT91_PINCTRL_H__ */ Index: stable/12/sys/gnu/dts/include/dt-bindings/pinctrl/samsung.h =================================================================== --- stable/12/sys/gnu/dts/include/dt-bindings/pinctrl/samsung.h (revision 343011) +++ stable/12/sys/gnu/dts/include/dt-bindings/pinctrl/samsung.h (revision 343012) @@ -1,80 +1,77 @@ +/* SPDX-License-Identifier: GPL-2.0 */ /* * Samsung's Exynos pinctrl bindings * * Copyright (c) 2016 Samsung Electronics Co., Ltd. * http://www.samsung.com * Author: Krzysztof Kozlowski - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. -*/ + */ #ifndef __DT_BINDINGS_PINCTRL_SAMSUNG_H__ #define __DT_BINDINGS_PINCTRL_SAMSUNG_H__ #define EXYNOS_PIN_PULL_NONE 0 #define EXYNOS_PIN_PULL_DOWN 1 #define EXYNOS_PIN_PULL_UP 3 #define S3C64XX_PIN_PULL_NONE 0 #define S3C64XX_PIN_PULL_DOWN 1 #define S3C64XX_PIN_PULL_UP 2 /* Pin function in power down mode */ #define EXYNOS_PIN_PDN_OUT0 0 #define EXYNOS_PIN_PDN_OUT1 1 #define EXYNOS_PIN_PDN_INPUT 2 #define EXYNOS_PIN_PDN_PREV 3 /* Drive strengths for Exynos3250, Exynos4 (all) and Exynos5250 */ #define EXYNOS4_PIN_DRV_LV1 0 #define EXYNOS4_PIN_DRV_LV2 2 #define EXYNOS4_PIN_DRV_LV3 1 #define EXYNOS4_PIN_DRV_LV4 3 /* Drive strengths for Exynos5260 */ #define EXYNOS5260_PIN_DRV_LV1 0 #define EXYNOS5260_PIN_DRV_LV2 1 #define EXYNOS5260_PIN_DRV_LV4 2 #define EXYNOS5260_PIN_DRV_LV6 3 /* Drive strengths for Exynos5410, Exynos542x and Exynos5800 */ #define EXYNOS5420_PIN_DRV_LV1 0 #define EXYNOS5420_PIN_DRV_LV2 1 #define EXYNOS5420_PIN_DRV_LV3 2 #define EXYNOS5420_PIN_DRV_LV4 3 /* Drive strengths for Exynos5433 */ #define EXYNOS5433_PIN_DRV_FAST_SR1 0 #define EXYNOS5433_PIN_DRV_FAST_SR2 1 #define EXYNOS5433_PIN_DRV_FAST_SR3 2 #define EXYNOS5433_PIN_DRV_FAST_SR4 3 #define EXYNOS5433_PIN_DRV_FAST_SR5 4 #define EXYNOS5433_PIN_DRV_FAST_SR6 5 #define EXYNOS5433_PIN_DRV_SLOW_SR1 8 #define EXYNOS5433_PIN_DRV_SLOW_SR2 9 #define EXYNOS5433_PIN_DRV_SLOW_SR3 0xa #define EXYNOS5433_PIN_DRV_SLOW_SR4 0xb #define EXYNOS5433_PIN_DRV_SLOW_SR5 0xc #define EXYNOS5433_PIN_DRV_SLOW_SR6 0xf #define EXYNOS_PIN_FUNC_INPUT 0 #define EXYNOS_PIN_FUNC_OUTPUT 1 #define EXYNOS_PIN_FUNC_2 2 #define EXYNOS_PIN_FUNC_3 3 #define EXYNOS_PIN_FUNC_4 4 #define EXYNOS_PIN_FUNC_5 5 #define EXYNOS_PIN_FUNC_6 6 #define EXYNOS_PIN_FUNC_EINT 0xf #define EXYNOS_PIN_FUNC_F EXYNOS_PIN_FUNC_EINT /* Drive strengths for Exynos7 FSYS1 block */ #define EXYNOS7_FSYS1_PIN_DRV_LV1 0 #define EXYNOS7_FSYS1_PIN_DRV_LV2 4 #define EXYNOS7_FSYS1_PIN_DRV_LV3 2 #define EXYNOS7_FSYS1_PIN_DRV_LV4 6 #define EXYNOS7_FSYS1_PIN_DRV_LV5 1 #define EXYNOS7_FSYS1_PIN_DRV_LV6 5 #endif /* __DT_BINDINGS_PINCTRL_SAMSUNG_H__ */ Index: stable/12/sys/gnu/dts/include/dt-bindings/regulator/maxim,max77802.h =================================================================== --- stable/12/sys/gnu/dts/include/dt-bindings/regulator/maxim,max77802.h (revision 343011) +++ stable/12/sys/gnu/dts/include/dt-bindings/regulator/maxim,max77802.h (revision 343012) @@ -1,18 +1,15 @@ +/* SPDX-License-Identifier: GPL-2.0 */ /* * Copyright (C) 2014 Google, Inc - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. * * Device Tree binding constants for the Maxim 77802 PMIC regulators */ #ifndef _DT_BINDINGS_REGULATOR_MAXIM_MAX77802_H #define _DT_BINDINGS_REGULATOR_MAXIM_MAX77802_H /* Regulator operating modes */ #define MAX77802_OPMODE_LP 1 #define MAX77802_OPMODE_NORMAL 3 #endif /* _DT_BINDINGS_REGULATOR_MAXIM_MAX77802_H */ Index: stable/12/sys/gnu/dts/include/dt-bindings/regulator/qcom,rpmh-regulator.h =================================================================== --- stable/12/sys/gnu/dts/include/dt-bindings/regulator/qcom,rpmh-regulator.h (nonexistent) +++ stable/12/sys/gnu/dts/include/dt-bindings/regulator/qcom,rpmh-regulator.h (revision 343012) @@ -0,0 +1,36 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* Copyright (c) 2018, The Linux Foundation. All rights reserved. */ + +#ifndef __QCOM_RPMH_REGULATOR_H +#define __QCOM_RPMH_REGULATOR_H + +/* + * These mode constants may be used to specify modes for various RPMh regulator + * device tree properties (e.g. regulator-initial-mode). Each type of regulator + * supports a subset of the possible modes. + * + * %RPMH_REGULATOR_MODE_RET: Retention mode in which only an extremely small + * load current is allowed. This mode is supported + * by LDO and SMPS type regulators. + * %RPMH_REGULATOR_MODE_LPM: Low power mode in which a small load current is + * allowed. This mode corresponds to PFM for SMPS + * and BOB type regulators. This mode is supported + * by LDO, HFSMPS, BOB, and PMIC4 FTSMPS type + * regulators. + * %RPMH_REGULATOR_MODE_AUTO: Auto mode in which the regulator hardware + * automatically switches between LPM and HPM based + * upon the real-time load current. This mode is + * supported by HFSMPS, BOB, and PMIC4 FTSMPS type + * regulators. + * %RPMH_REGULATOR_MODE_HPM: High power mode in which the full rated current + * of the regulator is allowed. This mode + * corresponds to PWM for SMPS and BOB type + * regulators. This mode is supported by all types + * of regulators. + */ +#define RPMH_REGULATOR_MODE_RET 0 +#define RPMH_REGULATOR_MODE_LPM 1 +#define RPMH_REGULATOR_MODE_AUTO 2 +#define RPMH_REGULATOR_MODE_HPM 3 + +#endif Property changes on: stable/12/sys/gnu/dts/include/dt-bindings/regulator/qcom,rpmh-regulator.h ___________________________________________________________________ Added: fbsd:nokeywords ## -0,0 +1 ## +yes \ No newline at end of property Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:mime-type ## -0,0 +1 ## +text/plain \ No newline at end of property Index: stable/12/sys/gnu/dts/include/dt-bindings/reset/amlogic,meson-axg-audio-arb.h =================================================================== --- stable/12/sys/gnu/dts/include/dt-bindings/reset/amlogic,meson-axg-audio-arb.h (nonexistent) +++ stable/12/sys/gnu/dts/include/dt-bindings/reset/amlogic,meson-axg-audio-arb.h (revision 343012) @@ -0,0 +1,17 @@ +/* SPDX-License-Identifier: (GPL-2.0 OR MIT) + * + * Copyright (c) 2018 Baylibre SAS. + * Author: Jerome Brunet + */ + +#ifndef _DT_BINDINGS_AMLOGIC_MESON_AXG_AUDIO_ARB_H +#define _DT_BINDINGS_AMLOGIC_MESON_AXG_AUDIO_ARB_H + +#define AXG_ARB_TODDR_A 0 +#define AXG_ARB_TODDR_B 1 +#define AXG_ARB_TODDR_C 2 +#define AXG_ARB_FRDDR_A 3 +#define AXG_ARB_FRDDR_B 4 +#define AXG_ARB_FRDDR_C 5 + +#endif /* _DT_BINDINGS_AMLOGIC_MESON_AXG_AUDIO_ARB_H */ Property changes on: stable/12/sys/gnu/dts/include/dt-bindings/reset/amlogic,meson-axg-audio-arb.h ___________________________________________________________________ Added: fbsd:nokeywords ## -0,0 +1 ## +yes \ No newline at end of property Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:mime-type ## -0,0 +1 ## +text/plain \ No newline at end of property Index: stable/12/sys/gnu/dts/include/dt-bindings/reset/qcom,sdm845-aoss.h =================================================================== --- stable/12/sys/gnu/dts/include/dt-bindings/reset/qcom,sdm845-aoss.h (nonexistent) +++ stable/12/sys/gnu/dts/include/dt-bindings/reset/qcom,sdm845-aoss.h (revision 343012) @@ -0,0 +1,17 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2018 The Linux Foundation. All rights reserved. + */ + +#ifndef _DT_BINDINGS_RESET_AOSS_SDM_845_H +#define _DT_BINDINGS_RESET_AOSS_SDM_845_H + +#define AOSS_CC_MSS_RESTART 0 +#define AOSS_CC_CAMSS_RESTART 1 +#define AOSS_CC_VENUS_RESTART 2 +#define AOSS_CC_GPU_RESTART 3 +#define AOSS_CC_DISPSS_RESTART 4 +#define AOSS_CC_WCSS_RESTART 5 +#define AOSS_CC_LPASS_RESTART 6 + +#endif Property changes on: stable/12/sys/gnu/dts/include/dt-bindings/reset/qcom,sdm845-aoss.h ___________________________________________________________________ Added: fbsd:nokeywords ## -0,0 +1 ## +yes \ No newline at end of property Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:mime-type ## -0,0 +1 ## +text/plain \ No newline at end of property Index: stable/12/sys/gnu/dts/include/dt-bindings/soc/qcom,rpmh-rsc.h =================================================================== --- stable/12/sys/gnu/dts/include/dt-bindings/soc/qcom,rpmh-rsc.h (nonexistent) +++ stable/12/sys/gnu/dts/include/dt-bindings/soc/qcom,rpmh-rsc.h (revision 343012) @@ -0,0 +1,14 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (c) 2016-2018, The Linux Foundation. All rights reserved. + */ + +#ifndef __DT_QCOM_RPMH_RSC_H__ +#define __DT_QCOM_RPMH_RSC_H__ + +#define SLEEP_TCS 0 +#define WAKE_TCS 1 +#define ACTIVE_TCS 2 +#define CONTROL_TCS 3 + +#endif /* __DT_QCOM_RPMH_RSC_H__ */ Property changes on: stable/12/sys/gnu/dts/include/dt-bindings/soc/qcom,rpmh-rsc.h ___________________________________________________________________ Added: fbsd:nokeywords ## -0,0 +1 ## +yes \ No newline at end of property Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:mime-type ## -0,0 +1 ## +text/plain \ No newline at end of property Index: stable/12/sys/gnu/dts/include/dt-bindings/usb/pd.h =================================================================== --- stable/12/sys/gnu/dts/include/dt-bindings/usb/pd.h (nonexistent) +++ stable/12/sys/gnu/dts/include/dt-bindings/usb/pd.h (revision 343012) @@ -0,0 +1,62 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef __DT_POWER_DELIVERY_H +#define __DT_POWER_DELIVERY_H + +/* Power delivery Power Data Object definitions */ +#define PDO_TYPE_FIXED 0 +#define PDO_TYPE_BATT 1 +#define PDO_TYPE_VAR 2 +#define PDO_TYPE_APDO 3 + +#define PDO_TYPE_SHIFT 30 +#define PDO_TYPE_MASK 0x3 + +#define PDO_TYPE(t) ((t) << PDO_TYPE_SHIFT) + +#define PDO_VOLT_MASK 0x3ff +#define PDO_CURR_MASK 0x3ff +#define PDO_PWR_MASK 0x3ff + +#define PDO_FIXED_DUAL_ROLE (1 << 29) /* Power role swap supported */ +#define PDO_FIXED_SUSPEND (1 << 28) /* USB Suspend supported (Source) */ +#define PDO_FIXED_HIGHER_CAP (1 << 28) /* Requires more than vSafe5V (Sink) */ +#define PDO_FIXED_EXTPOWER (1 << 27) /* Externally powered */ +#define PDO_FIXED_USB_COMM (1 << 26) /* USB communications capable */ +#define PDO_FIXED_DATA_SWAP (1 << 25) /* Data role swap supported */ +#define PDO_FIXED_VOLT_SHIFT 10 /* 50mV units */ +#define PDO_FIXED_CURR_SHIFT 0 /* 10mA units */ + +#define PDO_FIXED_VOLT(mv) ((((mv) / 50) & PDO_VOLT_MASK) << PDO_FIXED_VOLT_SHIFT) +#define PDO_FIXED_CURR(ma) ((((ma) / 10) & PDO_CURR_MASK) << PDO_FIXED_CURR_SHIFT) + +#define PDO_FIXED(mv, ma, flags) \ + (PDO_TYPE(PDO_TYPE_FIXED) | (flags) | \ + PDO_FIXED_VOLT(mv) | PDO_FIXED_CURR(ma)) + +#define VSAFE5V 5000 /* mv units */ + +#define PDO_BATT_MAX_VOLT_SHIFT 20 /* 50mV units */ +#define PDO_BATT_MIN_VOLT_SHIFT 10 /* 50mV units */ +#define PDO_BATT_MAX_PWR_SHIFT 0 /* 250mW units */ + +#define PDO_BATT_MIN_VOLT(mv) ((((mv) / 50) & PDO_VOLT_MASK) << PDO_BATT_MIN_VOLT_SHIFT) +#define PDO_BATT_MAX_VOLT(mv) ((((mv) / 50) & PDO_VOLT_MASK) << PDO_BATT_MAX_VOLT_SHIFT) +#define PDO_BATT_MAX_POWER(mw) ((((mw) / 250) & PDO_PWR_MASK) << PDO_BATT_MAX_PWR_SHIFT) + +#define PDO_BATT(min_mv, max_mv, max_mw) \ + (PDO_TYPE(PDO_TYPE_BATT) | PDO_BATT_MIN_VOLT(min_mv) | \ + PDO_BATT_MAX_VOLT(max_mv) | PDO_BATT_MAX_POWER(max_mw)) + +#define PDO_VAR_MAX_VOLT_SHIFT 20 /* 50mV units */ +#define PDO_VAR_MIN_VOLT_SHIFT 10 /* 50mV units */ +#define PDO_VAR_MAX_CURR_SHIFT 0 /* 10mA units */ + +#define PDO_VAR_MIN_VOLT(mv) ((((mv) / 50) & PDO_VOLT_MASK) << PDO_VAR_MIN_VOLT_SHIFT) +#define PDO_VAR_MAX_VOLT(mv) ((((mv) / 50) & PDO_VOLT_MASK) << PDO_VAR_MAX_VOLT_SHIFT) +#define PDO_VAR_MAX_CURR(ma) ((((ma) / 10) & PDO_CURR_MASK) << PDO_VAR_MAX_CURR_SHIFT) + +#define PDO_VAR(min_mv, max_mv, max_ma) \ + (PDO_TYPE(PDO_TYPE_VAR) | PDO_VAR_MIN_VOLT(min_mv) | \ + PDO_VAR_MAX_VOLT(max_mv) | PDO_VAR_MAX_CURR(max_ma)) + + #endif /* __DT_POWER_DELIVERY_H */ Property changes on: stable/12/sys/gnu/dts/include/dt-bindings/usb/pd.h ___________________________________________________________________ Added: fbsd:nokeywords ## -0,0 +1 ## +yes \ No newline at end of property Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:mime-type ## -0,0 +1 ## +text/plain \ No newline at end of property Index: stable/12 =================================================================== --- stable/12 (revision 343011) +++ stable/12 (revision 343012) Property changes on: stable/12 ___________________________________________________________________ Modified: svn:mergeinfo ## -0,0 +0,1 ## Merged /head:r342935