Index: stable/12/sys/arm/ti/ti_pruss.c =================================================================== --- stable/12/sys/arm/ti/ti_pruss.c (revision 342148) +++ stable/12/sys/arm/ti/ti_pruss.c (revision 342149) @@ -1,766 +1,766 @@ /*- * SPDX-License-Identifier: BSD-2-Clause-FreeBSD * * Copyright (c) 2013 Rui Paulo * Copyright (c) 2017 Manuel Stuehn * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE * POSSIBILITY OF SUCH DAMAGE. */ #include __FBSDID("$FreeBSD$"); #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #ifdef DEBUG #define DPRINTF(fmt, ...) do { \ printf("%s: ", __func__); \ printf(fmt, __VA_ARGS__); \ } while (0) #else #define DPRINTF(fmt, ...) #endif static d_open_t ti_pruss_irq_open; static d_read_t ti_pruss_irq_read; static d_poll_t ti_pruss_irq_poll; static device_probe_t ti_pruss_probe; static device_attach_t ti_pruss_attach; static device_detach_t ti_pruss_detach; static void ti_pruss_intr(void *); static d_open_t ti_pruss_open; static d_mmap_t ti_pruss_mmap; static void ti_pruss_irq_kqread_detach(struct knote *); static int ti_pruss_irq_kqevent(struct knote *, long); static d_kqfilter_t ti_pruss_irq_kqfilter; static void ti_pruss_privdtor(void *data); #define TI_PRUSS_PRU_IRQS 2 #define TI_PRUSS_HOST_IRQS 8 #define TI_PRUSS_IRQS (TI_PRUSS_HOST_IRQS+TI_PRUSS_PRU_IRQS) #define TI_PRUSS_EVENTS 64 #define NOT_SET_STR "NONE" #define TI_TS_ARRAY 16 struct ctl { size_t cnt; size_t idx; }; struct ts_ring_buf { struct ctl ctl; uint64_t ts[TI_TS_ARRAY]; }; struct ti_pruss_irqsc { struct mtx sc_mtx; struct cdev *sc_pdev; struct selinfo sc_selinfo; int8_t channel; int8_t last; int8_t event; bool enable; struct ts_ring_buf tstamps; }; static struct cdevsw ti_pruss_cdevirq = { .d_version = D_VERSION, .d_name = "ti_pruss_irq", .d_open = ti_pruss_irq_open, .d_read = ti_pruss_irq_read, .d_poll = ti_pruss_irq_poll, .d_kqfilter = ti_pruss_irq_kqfilter, }; struct ti_pruss_softc { struct mtx sc_mtx; struct resource *sc_mem_res; struct resource *sc_irq_res[TI_PRUSS_HOST_IRQS]; void *sc_intr[TI_PRUSS_HOST_IRQS]; struct ti_pruss_irqsc sc_irq_devs[TI_PRUSS_IRQS]; bus_space_tag_t sc_bt; bus_space_handle_t sc_bh; struct cdev *sc_pdev; struct selinfo sc_selinfo; bool sc_glob_irqen; }; static struct cdevsw ti_pruss_cdevsw = { .d_version = D_VERSION, .d_name = "ti_pruss", .d_open = ti_pruss_open, .d_mmap = ti_pruss_mmap, }; static device_method_t ti_pruss_methods[] = { DEVMETHOD(device_probe, ti_pruss_probe), DEVMETHOD(device_attach, ti_pruss_attach), DEVMETHOD(device_detach, ti_pruss_detach), DEVMETHOD_END }; static driver_t ti_pruss_driver = { "ti_pruss", ti_pruss_methods, sizeof(struct ti_pruss_softc) }; static devclass_t ti_pruss_devclass; DRIVER_MODULE(ti_pruss, simplebus, ti_pruss_driver, ti_pruss_devclass, 0, 0); MODULE_DEPEND(ti_pruss, ti_prcm, 1, 1, 1); static struct resource_spec ti_pruss_irq_spec[] = { { SYS_RES_IRQ, 0, RF_ACTIVE }, { SYS_RES_IRQ, 1, RF_ACTIVE }, { SYS_RES_IRQ, 2, RF_ACTIVE }, { SYS_RES_IRQ, 3, RF_ACTIVE }, { SYS_RES_IRQ, 4, RF_ACTIVE }, { SYS_RES_IRQ, 5, RF_ACTIVE }, { SYS_RES_IRQ, 6, RF_ACTIVE }, { SYS_RES_IRQ, 7, RF_ACTIVE }, { -1, 0, 0 } }; CTASSERT(TI_PRUSS_HOST_IRQS == nitems(ti_pruss_irq_spec) - 1); static int ti_pruss_irq_open(struct cdev *dev, int oflags, int devtype, struct thread *td) { struct ctl* irqs; struct ti_pruss_irqsc *sc; sc = dev->si_drv1; irqs = malloc(sizeof(struct ctl), M_DEVBUF, M_WAITOK); if (!irqs) return (ENOMEM); irqs->cnt = sc->tstamps.ctl.cnt; irqs->idx = sc->tstamps.ctl.idx; return devfs_set_cdevpriv(irqs, ti_pruss_privdtor); } static void ti_pruss_privdtor(void *data) { free(data, M_DEVBUF); } static int ti_pruss_irq_poll(struct cdev *dev, int events, struct thread *td) { struct ctl* irqs; struct ti_pruss_irqsc *sc; sc = dev->si_drv1; devfs_get_cdevpriv((void**)&irqs); if (events & (POLLIN | POLLRDNORM)) { if (sc->tstamps.ctl.cnt != irqs->cnt) return events & (POLLIN | POLLRDNORM); else selrecord(td, &sc->sc_selinfo); } return 0; } static int ti_pruss_irq_read(struct cdev *cdev, struct uio *uio, int ioflag) { const size_t ts_len = sizeof(uint64_t); struct ti_pruss_irqsc* irq; struct ctl* priv; int error = 0; size_t idx; ssize_t level; irq = cdev->si_drv1; if (uio->uio_resid < ts_len) return (EINVAL); error = devfs_get_cdevpriv((void**)&priv); if (error) return (error); mtx_lock(&irq->sc_mtx); if (irq->tstamps.ctl.cnt - priv->cnt > TI_TS_ARRAY) { priv->cnt = irq->tstamps.ctl.cnt; priv->idx = irq->tstamps.ctl.idx; mtx_unlock(&irq->sc_mtx); return (ENXIO); } do { idx = priv->idx; level = irq->tstamps.ctl.idx - idx; if (level < 0) level += TI_TS_ARRAY; if (level == 0) { if (ioflag & O_NONBLOCK) { mtx_unlock(&irq->sc_mtx); return (EWOULDBLOCK); } error = msleep(irq, &irq->sc_mtx, PCATCH | PDROP, "pruirq", 0); if (error) return error; mtx_lock(&irq->sc_mtx); } }while(level == 0); mtx_unlock(&irq->sc_mtx); error = uiomove(&irq->tstamps.ts[idx], ts_len, uio); if (++idx == TI_TS_ARRAY) idx = 0; priv->idx = idx; atomic_add_32(&priv->cnt, 1); return (error); } static struct ti_pruss_irq_arg { int irq; struct ti_pruss_softc *sc; } ti_pruss_irq_args[TI_PRUSS_IRQS]; static __inline uint32_t ti_pruss_reg_read(struct ti_pruss_softc *sc, uint32_t reg) { return (bus_space_read_4(sc->sc_bt, sc->sc_bh, reg)); } static __inline void ti_pruss_reg_write(struct ti_pruss_softc *sc, uint32_t reg, uint32_t val) { bus_space_write_4(sc->sc_bt, sc->sc_bh, reg, val); } static __inline void ti_pruss_interrupts_clear(struct ti_pruss_softc *sc) { /* disable global interrupt */ ti_pruss_reg_write(sc, PRUSS_INTC_GER, 0 ); /* clear all events */ ti_pruss_reg_write(sc, PRUSS_INTC_SECR0, 0xFFFFFFFF); ti_pruss_reg_write(sc, PRUSS_INTC_SECR1, 0xFFFFFFFF); /* disable all host interrupts */ ti_pruss_reg_write(sc, PRUSS_INTC_HIER, 0); } static __inline int ti_pruss_interrupts_enable(struct ti_pruss_softc *sc, int8_t irq, bool enable) { if (enable && ((sc->sc_irq_devs[irq].channel == -1) || (sc->sc_irq_devs[irq].event== -1))) { device_printf( sc->sc_pdev->si_drv1, "Interrupt chain not fully configured, not possible to enable\n" ); return (EINVAL); } sc->sc_irq_devs[irq].enable = enable; if (sc->sc_irq_devs[irq].sc_pdev) { destroy_dev(sc->sc_irq_devs[irq].sc_pdev); sc->sc_irq_devs[irq].sc_pdev = NULL; } if (enable) { sc->sc_irq_devs[irq].sc_pdev = make_dev(&ti_pruss_cdevirq, 0, UID_ROOT, GID_WHEEL, 0600, "pruss%d.irq%d", device_get_unit(sc->sc_pdev->si_drv1), irq); sc->sc_irq_devs[irq].sc_pdev->si_drv1 = &sc->sc_irq_devs[irq]; sc->sc_irq_devs[irq].tstamps.ctl.idx = 0; } uint32_t reg = enable ? PRUSS_INTC_HIEISR : PRUSS_INTC_HIDISR; ti_pruss_reg_write(sc, reg, sc->sc_irq_devs[irq].channel); reg = enable ? PRUSS_INTC_EISR : PRUSS_INTC_EICR; ti_pruss_reg_write(sc, reg, sc->sc_irq_devs[irq].event ); return (0); } static __inline void ti_pruss_map_write(struct ti_pruss_softc *sc, uint32_t basereg, uint8_t index, uint8_t content) { const size_t regadr = basereg + index & ~0x03; const size_t bitpos = (index & 0x03) * 8; uint32_t rmw = ti_pruss_reg_read(sc, regadr); rmw = (rmw & ~( 0xF << bitpos)) | ( (content & 0xF) << bitpos); ti_pruss_reg_write(sc, regadr, rmw); } static int ti_pruss_event_map( SYSCTL_HANDLER_ARGS ) { struct ti_pruss_softc *sc; const int8_t irq = arg2; int err; char event[sizeof(NOT_SET_STR)]; sc = arg1; if(sc->sc_irq_devs[irq].event == -1) bcopy(NOT_SET_STR, event, sizeof(event)); else snprintf(event, sizeof(event), "%d", sc->sc_irq_devs[irq].event); err = sysctl_handle_string(oidp, event, sizeof(event), req); if(err != 0) return (err); if (req->newptr) { // write event if (strcmp(NOT_SET_STR, event) == 0) { ti_pruss_interrupts_enable(sc, irq, false); sc->sc_irq_devs[irq].event = -1; } else { if (sc->sc_irq_devs[irq].channel == -1) { device_printf( sc->sc_pdev->si_drv1, "corresponding channel not configured\n"); return (ENXIO); } const int8_t channelnr = sc->sc_irq_devs[irq].channel; const int8_t eventnr = strtol( event, NULL, 10 ); // TODO: check if strol is valid if (eventnr > TI_PRUSS_EVENTS || eventnr < 0) { device_printf( sc->sc_pdev->si_drv1, "Event number %d not valid (0 - %d)", channelnr, TI_PRUSS_EVENTS -1); return (EINVAL); } sc->sc_irq_devs[irq].channel = channelnr; sc->sc_irq_devs[irq].event = eventnr; // event[nr] <= channel ti_pruss_map_write(sc, PRUSS_INTC_CMR_BASE, eventnr, channelnr); } } return (err); } static int ti_pruss_channel_map(SYSCTL_HANDLER_ARGS) { struct ti_pruss_softc *sc; int err; char channel[sizeof(NOT_SET_STR)]; const int8_t irq = arg2; sc = arg1; if (sc->sc_irq_devs[irq].channel == -1) bcopy(NOT_SET_STR, channel, sizeof(channel)); else snprintf(channel, sizeof(channel), "%d", sc->sc_irq_devs[irq].channel); err = sysctl_handle_string(oidp, channel, sizeof(channel), req); if (err != 0) return (err); if (req->newptr) { // write event if (strcmp(NOT_SET_STR, channel) == 0) { ti_pruss_interrupts_enable(sc, irq, false); ti_pruss_reg_write(sc, PRUSS_INTC_HIDISR, sc->sc_irq_devs[irq].channel); sc->sc_irq_devs[irq].channel = -1; } else { const int8_t channelnr = strtol(channel, NULL, 10); // TODO: check if strol is valid if (channelnr > TI_PRUSS_IRQS || channelnr < 0) { device_printf(sc->sc_pdev->si_drv1, "Channel number %d not valid (0 - %d)", channelnr, TI_PRUSS_IRQS-1); return (EINVAL); } sc->sc_irq_devs[irq].channel = channelnr; sc->sc_irq_devs[irq].last = -1; // channel[nr] <= irqnr ti_pruss_map_write(sc, PRUSS_INTC_HMR_BASE, irq, channelnr); } } return (err); } static int ti_pruss_interrupt_enable(SYSCTL_HANDLER_ARGS) { struct ti_pruss_softc *sc; int err; bool irqenable; const int8_t irq = arg2; sc = arg1; irqenable = sc->sc_irq_devs[arg2].enable; err = sysctl_handle_bool(oidp, &irqenable, arg2, req); if (err != 0) return (err); if (req->newptr) // write enable return ti_pruss_interrupts_enable(sc, irq, irqenable); return (err); } static int ti_pruss_global_interrupt_enable(SYSCTL_HANDLER_ARGS) { struct ti_pruss_softc *sc; int err; bool glob_irqen; sc = arg1; glob_irqen = sc->sc_glob_irqen; err = sysctl_handle_bool(oidp, &glob_irqen, arg2, req); if (err != 0) return (err); if (req->newptr) { sc->sc_glob_irqen = glob_irqen; ti_pruss_reg_write(sc, PRUSS_INTC_GER, glob_irqen); } return (err); } static int ti_pruss_probe(device_t dev) { if (!ofw_bus_status_okay(dev)) return (ENXIO); if (ofw_bus_is_compatible(dev, "ti,pruss-v1") || ofw_bus_is_compatible(dev, "ti,pruss-v2")) { device_set_desc(dev, "TI Programmable Realtime Unit Subsystem"); return (BUS_PROBE_DEFAULT); } return (ENXIO); } static int ti_pruss_attach(device_t dev) { struct ti_pruss_softc *sc; int rid, i; if (ti_prcm_clk_enable(PRUSS_CLK) != 0) { device_printf(dev, "could not enable PRUSS clock\n"); return (ENXIO); } sc = device_get_softc(dev); rid = 0; mtx_init(&sc->sc_mtx, "TI PRUSS", NULL, MTX_DEF); sc->sc_mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, RF_ACTIVE); if (sc->sc_mem_res == NULL) { device_printf(dev, "could not allocate memory resource\n"); return (ENXIO); } struct sysctl_ctx_list *clist = device_get_sysctl_ctx(dev); if (!clist) return (EINVAL); struct sysctl_oid *poid; poid = device_get_sysctl_tree( dev ); if (!poid) return (EINVAL); sc->sc_glob_irqen = false; struct sysctl_oid *irq_root = SYSCTL_ADD_NODE(clist, SYSCTL_CHILDREN(poid), OID_AUTO, "irq", CTLFLAG_RD, 0, "PRUSS Host Interrupts"); SYSCTL_ADD_PROC(clist, SYSCTL_CHILDREN(poid), OID_AUTO, "global_interrupt_enable", CTLFLAG_RW | CTLTYPE_U8, sc, 0, ti_pruss_global_interrupt_enable, "CU", "Global interrupt enable"); sc->sc_bt = rman_get_bustag(sc->sc_mem_res); sc->sc_bh = rman_get_bushandle(sc->sc_mem_res); if (bus_alloc_resources(dev, ti_pruss_irq_spec, sc->sc_irq_res) != 0) { device_printf(dev, "could not allocate interrupt resource\n"); ti_pruss_detach(dev); return (ENXIO); } ti_pruss_interrupts_clear(sc); for (i = 0; i < TI_PRUSS_IRQS; i++) { char name[8]; snprintf(name, sizeof(name), "%d", i); struct sysctl_oid *irq_nodes = SYSCTL_ADD_NODE(clist, SYSCTL_CHILDREN(irq_root), OID_AUTO, name, CTLFLAG_RD, 0, "PRUSS Interrupts"); SYSCTL_ADD_PROC(clist, SYSCTL_CHILDREN(irq_nodes), OID_AUTO, "channel", CTLFLAG_RW | CTLTYPE_STRING, sc, i, ti_pruss_channel_map, "A", "Channel attached to this irq"); SYSCTL_ADD_PROC(clist, SYSCTL_CHILDREN(irq_nodes), OID_AUTO, "event", CTLFLAG_RW | CTLTYPE_STRING, sc, i, ti_pruss_event_map, "A", "Event attached to this irq"); SYSCTL_ADD_PROC(clist, SYSCTL_CHILDREN(irq_nodes), OID_AUTO, "enable", CTLFLAG_RW | CTLTYPE_U8, sc, i, ti_pruss_interrupt_enable, "CU", "Enable/Disable interrupt"); sc->sc_irq_devs[i].event = -1; sc->sc_irq_devs[i].channel = -1; sc->sc_irq_devs[i].tstamps.ctl.idx = 0; if (i < TI_PRUSS_HOST_IRQS) { ti_pruss_irq_args[i].irq = i; ti_pruss_irq_args[i].sc = sc; if (bus_setup_intr(dev, sc->sc_irq_res[i], INTR_MPSAFE | INTR_TYPE_MISC, NULL, ti_pruss_intr, &ti_pruss_irq_args[i], &sc->sc_intr[i]) != 0) { device_printf(dev, "unable to setup the interrupt handler\n"); ti_pruss_detach(dev); return (ENXIO); } mtx_init(&sc->sc_irq_devs[i].sc_mtx, "TI PRUSS IRQ", NULL, MTX_DEF); knlist_init_mtx(&sc->sc_irq_devs[i].sc_selinfo.si_note, &sc->sc_irq_devs[i].sc_mtx); } } if (ti_pruss_reg_read(sc, PRUSS_AM33XX_INTC) == PRUSS_AM33XX_REV) device_printf(dev, "AM33xx PRU-ICSS\n"); sc->sc_pdev = make_dev(&ti_pruss_cdevsw, 0, UID_ROOT, GID_WHEEL, 0600, "pruss%d", device_get_unit(dev)); sc->sc_pdev->si_drv1 = dev; /* Acc. to datasheet always write 1 to polarity registers */ ti_pruss_reg_write(sc, PRUSS_INTC_SIPR0, 0xFFFFFFFF); ti_pruss_reg_write(sc, PRUSS_INTC_SIPR1, 0xFFFFFFFF); /* Acc. to datasheet always write 0 to event type registers */ ti_pruss_reg_write(sc, PRUSS_INTC_SITR0, 0); ti_pruss_reg_write(sc, PRUSS_INTC_SITR1, 0); return (0); } static int ti_pruss_detach(device_t dev) { struct ti_pruss_softc *sc = device_get_softc(dev); ti_pruss_interrupts_clear(sc); for (int i = 0; i < TI_PRUSS_HOST_IRQS; i++) { ti_pruss_interrupts_enable( sc, i, false ); if (sc->sc_intr[i]) bus_teardown_intr(dev, sc->sc_irq_res[i], sc->sc_intr[i]); if (sc->sc_irq_res[i]) bus_release_resource(dev, SYS_RES_IRQ, rman_get_rid(sc->sc_irq_res[i]), sc->sc_irq_res[i]); knlist_clear(&sc->sc_irq_devs[i].sc_selinfo.si_note, 0); mtx_lock(&sc->sc_irq_devs[i].sc_mtx); if (!knlist_empty(&sc->sc_irq_devs[i].sc_selinfo.si_note)) printf("IRQ %d KQueue not empty!\n", i ); mtx_unlock(&sc->sc_irq_devs[i].sc_mtx); knlist_destroy(&sc->sc_irq_devs[i].sc_selinfo.si_note); mtx_destroy(&sc->sc_irq_devs[i].sc_mtx); } mtx_destroy(&sc->sc_mtx); if (sc->sc_mem_res) bus_release_resource(dev, SYS_RES_MEMORY, rman_get_rid(sc->sc_mem_res), sc->sc_mem_res); if (sc->sc_pdev) destroy_dev(sc->sc_pdev); return (0); } static void ti_pruss_intr(void *arg) { int val; struct ti_pruss_irq_arg *iap = arg; struct ti_pruss_softc *sc = iap->sc; /* * Interrupts pr1_host_intr[0:7] are mapped to * Host-2 to Host-9 of PRU-ICSS IRQ-controller. */ const int pru_int = iap->irq + TI_PRUSS_PRU_IRQS; const int pru_int_mask = (1 << pru_int); const int pru_channel = sc->sc_irq_devs[pru_int].channel; const int pru_event = sc->sc_irq_devs[pru_channel].event; val = ti_pruss_reg_read(sc, PRUSS_INTC_HIER); if (!(val & pru_int_mask)) return; ti_pruss_reg_write(sc, PRUSS_INTC_HIDISR, pru_int); ti_pruss_reg_write(sc, PRUSS_INTC_SICR, pru_event); ti_pruss_reg_write(sc, PRUSS_INTC_HIEISR, pru_int); struct ti_pruss_irqsc* irq = &sc->sc_irq_devs[pru_channel]; size_t wr = irq->tstamps.ctl.idx; struct timespec ts; nanouptime(&ts); irq->tstamps.ts[wr] = ts.tv_sec * 1000000000 + ts.tv_nsec; if (++wr == TI_TS_ARRAY) wr = 0; atomic_add_32(&irq->tstamps.ctl.cnt, 1); irq->tstamps.ctl.idx = wr; KNOTE_UNLOCKED(&irq->sc_selinfo.si_note, pru_int); wakeup(irq); selwakeup(&irq->sc_selinfo); } static int ti_pruss_open(struct cdev *cdev __unused, int oflags __unused, int devtype __unused, struct thread *td __unused) { return (0); } static int ti_pruss_mmap(struct cdev *cdev, vm_ooffset_t offset, vm_paddr_t *paddr, int nprot, vm_memattr_t *memattr) { device_t dev = cdev->si_drv1; struct ti_pruss_softc *sc = device_get_softc(dev); - if (offset > rman_get_size(sc->sc_mem_res)) + if (offset >= rman_get_size(sc->sc_mem_res)) return (ENOSPC); *paddr = rman_get_start(sc->sc_mem_res) + offset; *memattr = VM_MEMATTR_UNCACHEABLE; return (0); } static struct filterops ti_pruss_kq_read = { .f_isfd = 1, .f_detach = ti_pruss_irq_kqread_detach, .f_event = ti_pruss_irq_kqevent, }; static void ti_pruss_irq_kqread_detach(struct knote *kn) { struct ti_pruss_irqsc *sc = kn->kn_hook; knlist_remove(&sc->sc_selinfo.si_note, kn, 0); } static int ti_pruss_irq_kqevent(struct knote *kn, long hint) { struct ti_pruss_irqsc* irq_sc; int notify; irq_sc = kn->kn_hook; if (hint > 0) kn->kn_data = hint - 2; if (hint > 0 || irq_sc->last > 0) notify = 1; else notify = 0; irq_sc->last = hint; return (notify); } static int ti_pruss_irq_kqfilter(struct cdev *cdev, struct knote *kn) { struct ti_pruss_irqsc *sc = cdev->si_drv1; switch (kn->kn_filter) { case EVFILT_READ: kn->kn_hook = sc; kn->kn_fop = &ti_pruss_kq_read; knlist_add(&sc->sc_selinfo.si_note, kn, 0); break; default: return (EINVAL); } return (0); } Index: stable/12/sys/dev/altera/avgen/altera_avgen.c =================================================================== --- stable/12/sys/dev/altera/avgen/altera_avgen.c (revision 342148) +++ stable/12/sys/dev/altera/avgen/altera_avgen.c (revision 342149) @@ -1,553 +1,554 @@ /*- * SPDX-License-Identifier: BSD-2-Clause-FreeBSD * * Copyright (c) 2012-2013, 2016 Robert N. M. Watson * All rights reserved. * * This software was developed by SRI International and the University of * Cambridge Computer Laboratory under DARPA/AFRL contract (FA8750-10-C-0237) * ("CTSRD"), as part of the DARPA CRASH research programme. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. */ #include __FBSDID("$FreeBSD$"); #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include /* * Generic device driver for allowing read(), write(), and mmap() on * memory-mapped, Avalon-attached devices. There is no actual dependence on * Avalon, so conceivably this should just be soc_dev or similar, since many * system-on-chip bus environments would work fine with the same code. */ devclass_t altera_avgen_devclass; static d_mmap_t altera_avgen_mmap; static d_read_t altera_avgen_read; static d_write_t altera_avgen_write; #define ALTERA_AVGEN_DEVNAME "altera_avgen" #define ALTERA_AVGEN_DEVNAME_FMT (ALTERA_AVGEN_DEVNAME "%d") static struct cdevsw avg_cdevsw = { .d_version = D_VERSION, .d_mmap = altera_avgen_mmap, .d_read = altera_avgen_read, .d_write = altera_avgen_write, .d_name = ALTERA_AVGEN_DEVNAME, }; #define ALTERA_AVGEN_SECTORSIZE 512 /* Not configurable at this time. */ static int altera_avgen_read(struct cdev *dev, struct uio *uio, int flag) { struct altera_avgen_softc *sc; u_long offset, size; #ifdef NOTYET uint64_t v8; #endif uint32_t v4; uint16_t v2; uint8_t v1; u_int width; int error; sc = dev->si_drv1; if ((sc->avg_flags & ALTERA_AVALON_FLAG_READ) == 0) return (EACCES); width = sc->avg_width; if (uio->uio_offset < 0 || uio->uio_offset % width != 0 || uio->uio_resid % width != 0) return (ENODEV); size = rman_get_size(sc->avg_res); if ((uio->uio_offset + uio->uio_resid < 0) || (uio->uio_offset + uio->uio_resid > size)) return (ENODEV); while (uio->uio_resid > 0) { offset = uio->uio_offset; if (offset + width > size) return (ENODEV); switch (width) { case 1: v1 = bus_read_1(sc->avg_res, offset); error = uiomove(&v1, sizeof(v1), uio); break; case 2: v2 = bus_read_2(sc->avg_res, offset); error = uiomove(&v2, sizeof(v2), uio); break; case 4: v4 = bus_read_4(sc->avg_res, offset); error = uiomove(&v4, sizeof(v4), uio); break; #ifdef NOTYET case 8: v8 = bus_read_8(sc->avg_res, offset); error = uiomove(&v8, sizeof(v8), uio); break; #endif default: panic("%s: unexpected widthment %u", __func__, width); } if (error) return (error); } return (0); } static int altera_avgen_write(struct cdev *dev, struct uio *uio, int flag) { struct altera_avgen_softc *sc; u_long offset, size; #ifdef NOTYET uint64_t v8; #endif uint32_t v4; uint16_t v2; uint8_t v1; u_int width; int error; sc = dev->si_drv1; if ((sc->avg_flags & ALTERA_AVALON_FLAG_WRITE) == 0) return (EACCES); width = sc->avg_width; if (uio->uio_offset < 0 || uio->uio_offset % width != 0 || uio->uio_resid % width != 0) return (ENODEV); size = rman_get_size(sc->avg_res); while (uio->uio_resid > 0) { offset = uio->uio_offset; if (offset + width > size) return (ENODEV); switch (width) { case 1: error = uiomove(&v1, sizeof(v1), uio); if (error) return (error); bus_write_1(sc->avg_res, offset, v1); break; case 2: error = uiomove(&v2, sizeof(v2), uio); if (error) return (error); bus_write_2(sc->avg_res, offset, v2); break; case 4: error = uiomove(&v4, sizeof(v4), uio); if (error) return (error); bus_write_4(sc->avg_res, offset, v4); break; #ifdef NOTYET case 8: error = uiomove(&v8, sizeof(v8), uio); if (error) return (error); bus_write_8(sc->avg_res, offset, v8); break; #endif default: panic("%s: unexpected width %u", __func__, width); } } return (0); } static int altera_avgen_mmap(struct cdev *dev, vm_ooffset_t offset, vm_paddr_t *paddr, int nprot, vm_memattr_t *memattr) { struct altera_avgen_softc *sc; sc = dev->si_drv1; if (nprot & VM_PROT_READ) { if ((sc->avg_flags & ALTERA_AVALON_FLAG_MMAP_READ) == 0) return (EACCES); } if (nprot & VM_PROT_WRITE) { if ((sc->avg_flags & ALTERA_AVALON_FLAG_MMAP_WRITE) == 0) return (EACCES); } if (nprot & VM_PROT_EXECUTE) { if ((sc->avg_flags & ALTERA_AVALON_FLAG_MMAP_EXEC) == 0) return (EACCES); } if (trunc_page(offset) == offset && + offset + PAGE_SIZE > offset && rman_get_size(sc->avg_res) >= offset + PAGE_SIZE) { *paddr = rman_get_start(sc->avg_res) + offset; *memattr = VM_MEMATTR_UNCACHEABLE; } else return (ENODEV); return (0); } /* * NB: We serialise block reads and writes in case the OS is generating * concurrent I/O against the same block, in which case we want one I/O (or * another) to win. This is not sufficient to provide atomicity for the * sector in the presence of a fail stop -- however, we're just writing this * to non-persistent DRAM .. right? */ static void altera_avgen_disk_strategy(struct bio *bp) { struct altera_avgen_softc *sc; void *data; long bcount; daddr_t pblkno; sc = bp->bio_disk->d_drv1; data = bp->bio_data; bcount = bp->bio_bcount; pblkno = bp->bio_pblkno; /* * Serialize block reads / writes. */ mtx_lock(&sc->avg_disk_mtx); switch (bp->bio_cmd) { case BIO_READ: if (!(sc->avg_flags & ALTERA_AVALON_FLAG_GEOM_READ)) { biofinish(bp, NULL, EIO); break; } switch (sc->avg_width) { case 1: bus_read_region_1(sc->avg_res, bp->bio_pblkno * ALTERA_AVGEN_SECTORSIZE, (uint8_t *)data, bcount); break; case 2: bus_read_region_2(sc->avg_res, bp->bio_pblkno * ALTERA_AVGEN_SECTORSIZE, (uint16_t *)data, bcount / 2); break; case 4: bus_read_region_4(sc->avg_res, bp->bio_pblkno * ALTERA_AVGEN_SECTORSIZE, (uint32_t *)data, bcount / 4); break; default: panic("%s: unexpected width %u", __func__, sc->avg_width); } break; case BIO_WRITE: if (!(sc->avg_flags & ALTERA_AVALON_FLAG_GEOM_WRITE)) { biofinish(bp, NULL, EROFS); break; } switch (sc->avg_width) { case 1: bus_write_region_1(sc->avg_res, bp->bio_pblkno * ALTERA_AVGEN_SECTORSIZE, (uint8_t *)data, bcount); break; case 2: bus_write_region_2(sc->avg_res, bp->bio_pblkno * ALTERA_AVGEN_SECTORSIZE, (uint16_t *)data, bcount / 2); break; case 4: bus_write_region_4(sc->avg_res, bp->bio_pblkno * ALTERA_AVGEN_SECTORSIZE, (uint32_t *)data, bcount / 4); break; default: panic("%s: unexpected width %u", __func__, sc->avg_width); } break; default: panic("%s: unsupported I/O operation %d", __func__, bp->bio_cmd); } mtx_unlock(&sc->avg_disk_mtx); biofinish(bp, NULL, 0); } static int altera_avgen_process_options(struct altera_avgen_softc *sc, const char *str_fileio, const char *str_geomio, const char *str_mmapio, const char *str_devname, int devunit) { const char *cp; device_t dev = sc->avg_dev; /* * Check for valid combinations of options. */ if (str_fileio == NULL && str_geomio == NULL && str_mmapio == NULL) { device_printf(dev, "at least one of %s, %s, or %s must be specified\n", ALTERA_AVALON_STR_FILEIO, ALTERA_AVALON_STR_GEOMIO, ALTERA_AVALON_STR_MMAPIO); return (ENXIO); } /* * Validity check: a device can either be a GEOM device (in which case * we use GEOM to register the device node), or a special device -- * but not both as that causes a collision in /dev. */ if (str_geomio != NULL && (str_fileio != NULL || str_mmapio != NULL)) { device_printf(dev, "at most one of %s and (%s or %s) may be specified\n", ALTERA_AVALON_STR_GEOMIO, ALTERA_AVALON_STR_FILEIO, ALTERA_AVALON_STR_MMAPIO); return (ENXIO); } /* * Ensure that a unit is specified if a name is also specified. */ if (str_devname == NULL && devunit != -1) { device_printf(dev, "%s requires %s be specified\n", ALTERA_AVALON_STR_DEVUNIT, ALTERA_AVALON_STR_DEVNAME); return (ENXIO); } /* * Extract, digest, and save values. */ switch (sc->avg_width) { case 1: case 2: case 4: #ifdef NOTYET case 8: #endif break; default: device_printf(dev, "%s unsupported value %u\n", ALTERA_AVALON_STR_WIDTH, sc->avg_width); return (ENXIO); } sc->avg_flags = 0; if (str_fileio != NULL) { for (cp = str_fileio; *cp != '\0'; cp++) { switch (*cp) { case ALTERA_AVALON_CHAR_READ: sc->avg_flags |= ALTERA_AVALON_FLAG_READ; break; case ALTERA_AVALON_CHAR_WRITE: sc->avg_flags |= ALTERA_AVALON_FLAG_WRITE; break; default: device_printf(dev, "invalid %s character %c\n", ALTERA_AVALON_STR_FILEIO, *cp); return (ENXIO); } } } if (str_geomio != NULL) { for (cp = str_geomio; *cp != '\0'; cp++){ switch (*cp) { case ALTERA_AVALON_CHAR_READ: sc->avg_flags |= ALTERA_AVALON_FLAG_GEOM_READ; break; case ALTERA_AVALON_CHAR_WRITE: sc->avg_flags |= ALTERA_AVALON_FLAG_GEOM_WRITE; break; default: device_printf(dev, "invalid %s character %c\n", ALTERA_AVALON_STR_GEOMIO, *cp); return (ENXIO); } } } if (str_mmapio != NULL) { for (cp = str_mmapio; *cp != '\0'; cp++) { switch (*cp) { case ALTERA_AVALON_CHAR_READ: sc->avg_flags |= ALTERA_AVALON_FLAG_MMAP_READ; break; case ALTERA_AVALON_CHAR_WRITE: sc->avg_flags |= ALTERA_AVALON_FLAG_MMAP_WRITE; break; case ALTERA_AVALON_CHAR_EXEC: sc->avg_flags |= ALTERA_AVALON_FLAG_MMAP_EXEC; break; default: device_printf(dev, "invalid %s character %c\n", ALTERA_AVALON_STR_MMAPIO, *cp); return (ENXIO); } } } return (0); } int altera_avgen_attach(struct altera_avgen_softc *sc, const char *str_fileio, const char *str_geomio, const char *str_mmapio, const char *str_devname, int devunit) { device_t dev = sc->avg_dev; int error; error = altera_avgen_process_options(sc, str_fileio, str_geomio, str_mmapio, str_devname, devunit); if (error) return (error); if (rman_get_size(sc->avg_res) >= PAGE_SIZE || str_mmapio != NULL) { if (rman_get_size(sc->avg_res) % PAGE_SIZE != 0) { device_printf(dev, "memory region not even multiple of page size\n"); return (ENXIO); } if (rman_get_start(sc->avg_res) % PAGE_SIZE != 0) { device_printf(dev, "memory region not page-aligned\n"); return (ENXIO); } } /* * If a GEOM permission is requested, then create the device via GEOM. * Otherwise, create a special device. We checked during options * processing that both weren't requested a once. */ if (str_devname != NULL) { sc->avg_name = strdup(str_devname, M_TEMP); devunit = sc->avg_unit; } else sc->avg_name = strdup(ALTERA_AVGEN_DEVNAME, M_TEMP); if (sc->avg_flags & (ALTERA_AVALON_FLAG_GEOM_READ | ALTERA_AVALON_FLAG_GEOM_WRITE)) { mtx_init(&sc->avg_disk_mtx, "altera_avgen_disk", NULL, MTX_DEF); sc->avg_disk = disk_alloc(); sc->avg_disk->d_drv1 = sc; sc->avg_disk->d_strategy = altera_avgen_disk_strategy; if (devunit == -1) devunit = 0; sc->avg_disk->d_name = sc->avg_name; sc->avg_disk->d_unit = devunit; /* * NB: As avg_res is a multiple of PAGE_SIZE, it is also a * multiple of ALTERA_AVGEN_SECTORSIZE. */ sc->avg_disk->d_sectorsize = ALTERA_AVGEN_SECTORSIZE; sc->avg_disk->d_mediasize = rman_get_size(sc->avg_res); sc->avg_disk->d_maxsize = ALTERA_AVGEN_SECTORSIZE; disk_create(sc->avg_disk, DISK_VERSION); } else { /* Device node allocation. */ if (str_devname == NULL) { str_devname = ALTERA_AVGEN_DEVNAME_FMT; devunit = sc->avg_unit; } if (devunit != -1) sc->avg_cdev = make_dev(&avg_cdevsw, sc->avg_unit, UID_ROOT, GID_WHEEL, S_IRUSR | S_IWUSR, "%s%d", str_devname, devunit); else sc->avg_cdev = make_dev(&avg_cdevsw, sc->avg_unit, UID_ROOT, GID_WHEEL, S_IRUSR | S_IWUSR, "%s", str_devname); if (sc->avg_cdev == NULL) { device_printf(sc->avg_dev, "%s: make_dev failed\n", __func__); return (ENXIO); } /* XXXRW: Slight race between make_dev(9) and here. */ sc->avg_cdev->si_drv1 = sc; } return (0); } void altera_avgen_detach(struct altera_avgen_softc *sc) { KASSERT((sc->avg_disk != NULL) || (sc->avg_cdev != NULL), ("%s: neither GEOM nor special device", __func__)); if (sc->avg_disk != NULL) { disk_gone(sc->avg_disk); disk_destroy(sc->avg_disk); free(sc->avg_name, M_TEMP); mtx_destroy(&sc->avg_disk_mtx); } else { destroy_dev(sc->avg_cdev); } } Index: stable/12/sys/dev/terasic/mtl/terasic_mtl_reg.c =================================================================== --- stable/12/sys/dev/terasic/mtl/terasic_mtl_reg.c (revision 342148) +++ stable/12/sys/dev/terasic/mtl/terasic_mtl_reg.c (revision 342149) @@ -1,295 +1,296 @@ /*- * SPDX-License-Identifier: BSD-2-Clause-FreeBSD * * Copyright (c) 2012 Robert N. M. Watson * All rights reserved. * * This software was developed by SRI International and the University of * Cambridge Computer Laboratory under DARPA/AFRL contract (FA8750-10-C-0237) * ("CTSRD"), as part of the DARPA CRASH research programme. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. */ #include __FBSDID("$FreeBSD$"); #include #include #include #include /* struct vt_mode */ #include #include /* video_adapter_t */ #include #include #include #include #include #include #include #include #include static d_mmap_t terasic_mtl_reg_mmap; static d_read_t terasic_mtl_reg_read; static d_write_t terasic_mtl_reg_write; static struct cdevsw terasic_mtl_reg_cdevsw = { .d_version = D_VERSION, .d_mmap = terasic_mtl_reg_mmap, .d_read = terasic_mtl_reg_read, .d_write = terasic_mtl_reg_write, .d_name = "terasic_mtl_reg", }; /* * All I/O to/from the MTL register device must be 32-bit, and aligned to * 32-bit. */ static int terasic_mtl_reg_read(struct cdev *dev, struct uio *uio, int flag) { struct terasic_mtl_softc *sc; u_long offset, size; uint32_t v; int error; if (uio->uio_offset < 0 || uio->uio_offset % 4 != 0 || uio->uio_resid % 4 != 0) return (ENODEV); sc = dev->si_drv1; size = rman_get_size(sc->mtl_reg_res); error = 0; if ((uio->uio_offset + uio->uio_resid < 0) || (uio->uio_offset + uio->uio_resid > size)) return (ENODEV); while (uio->uio_resid > 0) { offset = uio->uio_offset; if (offset + sizeof(v) > size) return (ENODEV); v = bus_read_4(sc->mtl_reg_res, offset); error = uiomove(&v, sizeof(v), uio); if (error) return (error); } return (error); } static int terasic_mtl_reg_write(struct cdev *dev, struct uio *uio, int flag) { struct terasic_mtl_softc *sc; u_long offset, size; uint32_t v; int error; if (uio->uio_offset < 0 || uio->uio_offset % 4 != 0 || uio->uio_resid % 4 != 0) return (ENODEV); sc = dev->si_drv1; size = rman_get_size(sc->mtl_reg_res); error = 0; while (uio->uio_resid > 0) { offset = uio->uio_offset; if (offset + sizeof(v) > size) return (ENODEV); error = uiomove(&v, sizeof(v), uio); if (error) return (error); bus_write_4(sc->mtl_reg_res, offset, v); } return (error); } static int terasic_mtl_reg_mmap(struct cdev *dev, vm_ooffset_t offset, vm_paddr_t *paddr, int nprot, vm_memattr_t *memattr) { struct terasic_mtl_softc *sc; int error; sc = dev->si_drv1; error = 0; if (trunc_page(offset) == offset && + offset + PAGE_SIZE > offset && rman_get_size(sc->mtl_reg_res) >= offset + PAGE_SIZE) { *paddr = rman_get_start(sc->mtl_reg_res) + offset; *memattr = VM_MEMATTR_UNCACHEABLE; } else error = ENODEV; return (error); } void terasic_mtl_reg_blend_get(struct terasic_mtl_softc *sc, uint32_t *blendp) { *blendp = le32toh(bus_read_4(sc->mtl_reg_res, TERASIC_MTL_OFF_BLEND)); } void terasic_mtl_reg_blend_set(struct terasic_mtl_softc *sc, uint32_t blend) { bus_write_4(sc->mtl_reg_res, TERASIC_MTL_OFF_BLEND, htole32(blend)); } void terasic_mtl_blend_default_set(struct terasic_mtl_softc *sc, uint8_t colour) { uint32_t v; TERASIC_MTL_LOCK(sc); terasic_mtl_reg_blend_get(sc, &v); v &= ~TERASIC_MTL_BLEND_DEFAULT_MASK; v |= colour << TERASIC_MTL_BLEND_DEFAULT_SHIFT; terasic_mtl_reg_blend_set(sc, v); TERASIC_MTL_UNLOCK(sc); } void terasic_mtl_blend_pixel_set(struct terasic_mtl_softc *sc, uint8_t alpha) { uint32_t v; TERASIC_MTL_LOCK(sc); terasic_mtl_reg_blend_get(sc, &v); v &= ~TERASIC_MTL_BLEND_PIXEL_MASK; v |= alpha << TERASIC_MTL_BLEND_PIXEL_SHIFT; terasic_mtl_reg_blend_set(sc, v); TERASIC_MTL_UNLOCK(sc); } void terasic_mtl_blend_textfg_set(struct terasic_mtl_softc *sc, uint8_t alpha) { uint32_t v; TERASIC_MTL_LOCK(sc); terasic_mtl_reg_blend_get(sc, &v); v &= ~TERASIC_MTL_BLEND_TEXTFG_MASK; v |= alpha << TERASIC_MTL_BLEND_TEXTFG_SHIFT; terasic_mtl_reg_blend_set(sc, v); TERASIC_MTL_UNLOCK(sc); } void terasic_mtl_blend_textbg_set(struct terasic_mtl_softc *sc, uint8_t alpha) { uint32_t v; TERASIC_MTL_LOCK(sc); terasic_mtl_reg_blend_get(sc, &v); v &= ~TERASIC_MTL_BLEND_TEXTBG_MASK; v |= alpha << TERASIC_MTL_BLEND_TEXTBG_SHIFT; terasic_mtl_reg_blend_set(sc, v); TERASIC_MTL_UNLOCK(sc); } void terasic_mtl_reg_pixel_endian_set(struct terasic_mtl_softc *sc, int endian_swap) { uint32_t v; TERASIC_MTL_LOCK(sc); terasic_mtl_reg_blend_get(sc, &v); if (endian_swap) v |= TERASIC_MTL_BLEND_PIXEL_ENDIAN_SWAP; else v &= ~TERASIC_MTL_BLEND_PIXEL_ENDIAN_SWAP; terasic_mtl_reg_blend_set(sc, v); TERASIC_MTL_UNLOCK(sc); } void terasic_mtl_reg_textcursor_get(struct terasic_mtl_softc *sc, uint8_t *colp, uint8_t *rowp) { uint32_t v; v = bus_read_4(sc->mtl_reg_res, TERASIC_MTL_OFF_TEXTCURSOR); v = le32toh(v); *colp = (v & TERASIC_MTL_TEXTCURSOR_COL_MASK) >> TERASIC_MTL_TEXTCURSOR_COL_SHIFT; *rowp = (v & TERASIC_MTL_TEXTCURSOR_ROW_MASK); } void terasic_mtl_reg_textcursor_set(struct terasic_mtl_softc *sc, uint8_t col, uint8_t row) { uint32_t v; v = (col << TERASIC_MTL_TEXTCURSOR_COL_SHIFT) | row; v = htole32(v); bus_write_4(sc->mtl_reg_res, TERASIC_MTL_OFF_TEXTCURSOR, v); } void terasic_mtl_reg_blank(struct terasic_mtl_softc *sc) { device_printf(sc->mtl_dev, "%s: not yet\n", __func__); } void terasic_mtl_reg_textframebufaddr_get(struct terasic_mtl_softc *sc, uint32_t *addrp) { uint32_t addr; addr = bus_read_4(sc->mtl_reg_res, TERASIC_MTL_OFF_TEXTFRAMEBUFADDR); *addrp = le32toh(addr); } void terasic_mtl_reg_textframebufaddr_set(struct terasic_mtl_softc *sc, uint32_t addr) { addr = htole32(addr); bus_write_4(sc->mtl_reg_res, TERASIC_MTL_OFF_TEXTFRAMEBUFADDR, addr); } int terasic_mtl_reg_attach(struct terasic_mtl_softc *sc) { sc->mtl_reg_cdev = make_dev(&terasic_mtl_reg_cdevsw, sc->mtl_unit, UID_ROOT, GID_WHEEL, 0400, "mtl_reg%d", sc->mtl_unit); if (sc->mtl_reg_cdev == NULL) { device_printf(sc->mtl_dev, "%s: make_dev failed\n", __func__); return (ENXIO); } /* XXXRW: Slight race between make_dev(9) and here. */ sc->mtl_reg_cdev->si_drv1 = sc; return (0); } void terasic_mtl_reg_detach(struct terasic_mtl_softc *sc) { if (sc->mtl_reg_cdev != NULL) destroy_dev(sc->mtl_reg_cdev); } Index: stable/12/sys/dev/terasic/mtl/terasic_mtl_text.c =================================================================== --- stable/12/sys/dev/terasic/mtl/terasic_mtl_text.c (revision 342148) +++ stable/12/sys/dev/terasic/mtl/terasic_mtl_text.c (revision 342149) @@ -1,195 +1,196 @@ /*- * SPDX-License-Identifier: BSD-2-Clause-FreeBSD * * Copyright (c) 2012 Robert N. M. Watson * All rights reserved. * * This software was developed by SRI International and the University of * Cambridge Computer Laboratory under DARPA/AFRL contract (FA8750-10-C-0237) * ("CTSRD"), as part of the DARPA CRASH research programme. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. */ #include __FBSDID("$FreeBSD$"); #include #include #include #include /* struct vt_mode */ #include #include /* video_adapter_t */ #include #include #include #include #include #include #include #include #include static d_mmap_t terasic_mtl_text_mmap; static d_read_t terasic_mtl_text_read; static d_write_t terasic_mtl_text_write; static struct cdevsw terasic_mtl_text_cdevsw = { .d_version = D_VERSION, .d_mmap = terasic_mtl_text_mmap, .d_read = terasic_mtl_text_read, .d_write = terasic_mtl_text_write, .d_name = "terasic_mtl_text", }; /* * All I/O to/from the mtl device must be 16-bit, and aligned to 16-bit. */ static int terasic_mtl_text_read(struct cdev *dev, struct uio *uio, int flag) { struct terasic_mtl_softc *sc; u_long offset, size; uint16_t v; int error; if (uio->uio_offset < 0 || uio->uio_offset % 2 != 0 || uio->uio_resid % 2 != 0) return (ENODEV); sc = dev->si_drv1; size = rman_get_size(sc->mtl_text_res); error = 0; if ((uio->uio_offset + uio->uio_resid < 0) || (uio->uio_offset + uio->uio_resid > size)) return (ENODEV); while (uio->uio_resid > 0) { offset = uio->uio_offset; if (offset + sizeof(v) > size) return (ENODEV); v = bus_read_2(sc->mtl_text_res, offset); error = uiomove(&v, sizeof(v), uio); if (error) return (error); } return (error); } static int terasic_mtl_text_write(struct cdev *dev, struct uio *uio, int flag) { struct terasic_mtl_softc *sc; u_long offset, size; uint16_t v; int error; if (uio->uio_offset < 0 || uio->uio_offset % 2 != 0 || uio->uio_resid % 2 != 0) return (ENODEV); sc = dev->si_drv1; size = rman_get_size(sc->mtl_text_res); error = 0; while (uio->uio_resid > 0) { offset = uio->uio_offset; if (offset + sizeof(v) > size) return (ENODEV); error = uiomove(&v, sizeof(v), uio); if (error) return (error); bus_write_2(sc->mtl_text_res, offset, v); } return (error); } static int terasic_mtl_text_mmap(struct cdev *dev, vm_ooffset_t offset, vm_paddr_t *paddr, int nprot, vm_memattr_t *memattr) { struct terasic_mtl_softc *sc; int error; sc = dev->si_drv1; error = 0; if (trunc_page(offset) == offset && + offset + PAGE_SIZE > offset && rman_get_size(sc->mtl_text_res) >= offset + PAGE_SIZE) { *paddr = rman_get_start(sc->mtl_text_res) + offset; *memattr = VM_MEMATTR_UNCACHEABLE; } else error = ENODEV; return (error); } void terasic_mtl_text_putc(struct terasic_mtl_softc *sc, u_int x, u_int y, uint8_t c, uint8_t a) { u_int offset; uint16_t v; KASSERT(x < TERASIC_MTL_COLS, ("%s: TERASIC_MTL_COLS", __func__)); KASSERT(y < TERASIC_MTL_ROWS, ("%s: TERASIC_MTL_ROWS", __func__)); offset = sizeof(uint16_t) * (x + y * TERASIC_MTL_COLS); v = (c << TERASIC_MTL_TEXTFRAMEBUF_CHAR_SHIFT) | (a << TERASIC_MTL_TEXTFRAMEBUF_ATTR_SHIFT); v = htole16(v); bus_write_2(sc->mtl_text_res, offset, v); } int terasic_mtl_text_attach(struct terasic_mtl_softc *sc) { uint32_t v; u_int offset; terasic_mtl_reg_textframebufaddr_get(sc, &v); if (v != TERASIC_MTL_TEXTFRAMEBUF_EXPECTED_ADDR) { device_printf(sc->mtl_dev, "%s: unexpected text frame buffer " "address (%08x); cannot attach\n", __func__, v); return (ENXIO); } for (offset = 0; offset < rman_get_size(sc->mtl_text_res); offset += sizeof(uint16_t)) bus_write_2(sc->mtl_text_res, offset, 0); sc->mtl_text_cdev = make_dev(&terasic_mtl_text_cdevsw, sc->mtl_unit, UID_ROOT, GID_WHEEL, 0400, "mtl_text%d", sc->mtl_unit); if (sc->mtl_text_cdev == NULL) { device_printf(sc->mtl_dev, "%s: make_dev failed\n", __func__); return (ENXIO); } /* XXXRW: Slight race between make_dev(9) and here. */ TERASIC_MTL_LOCK_INIT(sc); sc->mtl_text_cdev->si_drv1 = sc; return (0); } void terasic_mtl_text_detach(struct terasic_mtl_softc *sc) { if (sc->mtl_text_cdev != NULL) { destroy_dev(sc->mtl_text_cdev); TERASIC_MTL_LOCK_DESTROY(sc); } } Index: stable/12 =================================================================== --- stable/12 (revision 342148) +++ stable/12 (revision 342149) Property changes on: stable/12 ___________________________________________________________________ Modified: svn:mergeinfo ## -0,0 +0,1 ## Merged /head:r341402