Index: head/sys/arm/mv/gpio.c =================================================================== --- head/sys/arm/mv/gpio.c (revision 342012) +++ head/sys/arm/mv/gpio.c (revision 342013) @@ -1,1189 +1,1221 @@ /*- * SPDX-License-Identifier: BSD-2-Clause-FreeBSD * * Copyright (c) 2006 Benno Rice. * Copyright (C) 2008 MARVELL INTERNATIONAL LTD. * Copyright (c) 2017 Semihalf. * All rights reserved. * * Adapted and extended for Marvell SoCs by Semihalf. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * * from: FreeBSD: //depot/projects/arm/src/sys/arm/xscale/pxa2x0/pxa2x0_gpio.c, rev 1 */ #include __FBSDID("$FreeBSD$"); #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include "gpio_if.h" +#ifdef __aarch64__ +#include "opt_soc.h" +#endif + #define GPIO_MAX_INTR_COUNT 8 #define GPIO_PINS_PER_REG 32 #define GPIO_GENERIC_CAP (GPIO_PIN_INPUT | GPIO_PIN_OUTPUT | \ GPIO_PIN_OPENDRAIN | GPIO_PIN_PUSHPULL | \ GPIO_PIN_TRISTATE | GPIO_PIN_PULLUP | \ GPIO_PIN_PULLDOWN | GPIO_PIN_INVIN | \ GPIO_PIN_INVOUT) #define DEBOUNCE_CHECK_MS 1 #define DEBOUNCE_LO_HI_MS 2 #define DEBOUNCE_HI_LO_MS 2 #define DEBOUNCE_CHECK_TICKS ((hz / 1000) * DEBOUNCE_CHECK_MS) struct mv_gpio_softc { + device_t dev; device_t sc_busdev; struct resource * mem_res; int mem_rid; struct resource * irq_res[GPIO_MAX_INTR_COUNT]; int irq_rid[GPIO_MAX_INTR_COUNT]; struct intr_event * gpio_events[MV_GPIO_MAX_NPINS]; void *ih_cookie[GPIO_MAX_INTR_COUNT]; bus_space_tag_t bst; bus_space_handle_t bsh; + uint32_t offset; struct mtx mutex; uint8_t pin_num; /* number of GPIO pins */ uint8_t irq_num; /* number of real IRQs occupied by GPIO controller */ struct gpio_pin gpio_setup[MV_GPIO_MAX_NPINS]; /* Used for debouncing. */ uint32_t debounced_state_lo; uint32_t debounced_state_hi; struct callout **debounce_callouts; int *debounce_counters; }; struct mv_gpio_pindev { device_t dev; int pin; }; static int mv_gpio_probe(device_t); static int mv_gpio_attach(device_t); static int mv_gpio_intr(device_t, void *); static void mv_gpio_double_edge_init(device_t, int); static int mv_gpio_debounce_setup(device_t, int); static int mv_gpio_debounce_prepare(device_t, int); static int mv_gpio_debounce_init(device_t, int); static void mv_gpio_debounce_start(device_t, int); static void mv_gpio_debounce(void *); static void mv_gpio_debounced_state_set(device_t, int, uint8_t); static uint32_t mv_gpio_debounced_state_get(device_t, int); static void mv_gpio_exec_intr_handlers(device_t, uint32_t, int); static void mv_gpio_intr_handler(device_t, int); static uint32_t mv_gpio_reg_read(device_t, uint32_t); static void mv_gpio_reg_write(device_t, uint32_t, uint32_t); static void mv_gpio_reg_set(device_t, uint32_t, uint32_t); static void mv_gpio_reg_clear(device_t, uint32_t, uint32_t); static void mv_gpio_blink(device_t, uint32_t, uint8_t); static void mv_gpio_polarity(device_t, uint32_t, uint8_t, uint8_t); static void mv_gpio_level(device_t, uint32_t, uint8_t); static void mv_gpio_edge(device_t, uint32_t, uint8_t); static void mv_gpio_out_en(device_t, uint32_t, uint8_t); static void mv_gpio_int_ack(struct mv_gpio_pindev *); static void mv_gpio_value_set(device_t, uint32_t, uint8_t); static uint32_t mv_gpio_value_get(device_t, uint32_t, uint8_t); static void mv_gpio_intr_mask(struct mv_gpio_pindev *); static void mv_gpio_intr_unmask(struct mv_gpio_pindev *); void mv_gpio_finish_intrhandler(struct mv_gpio_pindev *); int mv_gpio_setup_intrhandler(device_t, const char *, driver_filter_t *, void (*)(void *), void *, int, int, void **); int mv_gpio_configure(device_t, uint32_t, uint32_t, uint32_t); void mv_gpio_out(device_t, uint32_t, uint8_t, uint8_t); uint8_t mv_gpio_in(device_t, uint32_t); /* * GPIO interface */ static device_t mv_gpio_get_bus(device_t); static int mv_gpio_pin_max(device_t, int *); static int mv_gpio_pin_getcaps(device_t, uint32_t, uint32_t *); static int mv_gpio_pin_getflags(device_t, uint32_t, uint32_t *); static int mv_gpio_pin_getname(device_t, uint32_t, char *); static int mv_gpio_pin_setflags(device_t, uint32_t, uint32_t); static int mv_gpio_pin_set(device_t, uint32_t, unsigned int); static int mv_gpio_pin_get(device_t, uint32_t, unsigned int *); static int mv_gpio_pin_toggle(device_t, uint32_t); static int mv_gpio_map_gpios(device_t, phandle_t, phandle_t, int, pcell_t *, uint32_t *, uint32_t *); #define MV_GPIO_LOCK() mtx_lock_spin(&sc->mutex) #define MV_GPIO_UNLOCK() mtx_unlock_spin(&sc->mutex) #define MV_GPIO_ASSERT_LOCKED() mtx_assert(&sc->mutex, MA_OWNED) static device_method_t mv_gpio_methods[] = { DEVMETHOD(device_probe, mv_gpio_probe), DEVMETHOD(device_attach, mv_gpio_attach), /* GPIO protocol */ DEVMETHOD(gpio_get_bus, mv_gpio_get_bus), DEVMETHOD(gpio_pin_max, mv_gpio_pin_max), DEVMETHOD(gpio_pin_getname, mv_gpio_pin_getname), DEVMETHOD(gpio_pin_getflags, mv_gpio_pin_getflags), DEVMETHOD(gpio_pin_getcaps, mv_gpio_pin_getcaps), DEVMETHOD(gpio_pin_setflags, mv_gpio_pin_setflags), DEVMETHOD(gpio_pin_get, mv_gpio_pin_get), DEVMETHOD(gpio_pin_set, mv_gpio_pin_set), DEVMETHOD(gpio_pin_toggle, mv_gpio_pin_toggle), DEVMETHOD(gpio_map_gpios, mv_gpio_map_gpios), DEVMETHOD_END }; static driver_t mv_gpio_driver = { "gpio", mv_gpio_methods, sizeof(struct mv_gpio_softc), }; static devclass_t mv_gpio_devclass; DRIVER_MODULE(mv_gpio, simplebus, mv_gpio_driver, mv_gpio_devclass, 0, 0); -struct ofw_compat_data gpio_controllers[] = { - { "mrvl,gpio", (uintptr_t)true }, - { "marvell,orion-gpio", (uintptr_t)true }, +struct ofw_compat_data compat_data[] = { + { "mrvl,gpio", 1 }, + { "marvell,orion-gpio", 1 }, +#ifdef SOC_MARVELL_8K + { "marvell,armada-8k-gpio", 1 }, +#endif { NULL, 0 } }; static int mv_gpio_probe(device_t dev) { if (!ofw_bus_status_okay(dev)) return (ENXIO); - if (ofw_bus_search_compatible(dev, gpio_controllers)->ocd_data == 0) + if (ofw_bus_search_compatible(dev, compat_data)->ocd_data == 0) return (ENXIO); device_set_desc(dev, "Marvell Integrated GPIO Controller"); return (0); } static int -mv_gpio_attach(device_t dev) +mv_gpio_setup_interrupts(struct mv_gpio_softc *sc, phandle_t node) { - int i, size; - struct mv_gpio_softc *sc; - pcell_t pincnt = 0; - pcell_t irq_cells = 0; phandle_t iparent; + pcell_t irq_cells; + int i, size; - sc = (struct mv_gpio_softc *)device_get_softc(dev); - if (sc == NULL) - return (ENXIO); - - if (OF_getencprop(ofw_bus_get_node(dev), "pin-count", &pincnt, - sizeof(pcell_t)) >= 0 || - OF_getencprop(ofw_bus_get_node(dev), "ngpios", &pincnt, - sizeof(pcell_t)) >= 0) { - sc->pin_num = MIN(pincnt, MV_GPIO_MAX_NPINS); - if (bootverbose) - device_printf(dev, "%d pins available\n", sc->pin_num); - } else { - device_printf(dev, "ERROR: no pin-count or ngpios entry found!\n"); - return (ENXIO); - } - - /* Assign generic capabilities to every gpio pin */ - for(i = 0; i < sc->pin_num; i++) - sc->gpio_setup[i].gp_caps = GPIO_GENERIC_CAP; - /* Find root interrupt controller */ - iparent = ofw_bus_find_iparent(ofw_bus_get_node(dev)); + iparent = ofw_bus_find_iparent(node); if (iparent == 0) { - device_printf(dev, "No interrupt-parrent found. " + device_printf(sc->dev, "No interrupt-parrent found. " "Error in DTB\n"); return (ENXIO); } else { /* While at parent - store interrupt cells prop */ if (OF_searchencprop(OF_node_from_xref(iparent), "#interrupt-cells", &irq_cells, sizeof(irq_cells)) == -1) { - device_printf(dev, "DTB: Missing #interrupt-cells " + device_printf(sc->dev, "DTB: Missing #interrupt-cells " "property in interrupt parent node\n"); return (ENXIO); } } - size = OF_getproplen(ofw_bus_get_node(dev), "interrupts"); + size = OF_getproplen(node, "interrupts"); if (size != -1) { size = size / sizeof(pcell_t); size = size / irq_cells; sc->irq_num = size; - device_printf(dev, "%d IRQs available\n", sc->irq_num); + device_printf(sc->dev, "%d IRQs available\n", sc->irq_num); } else { - device_printf(dev, "ERROR: no interrupts entry found!\n"); + device_printf(sc->dev, "ERROR: no interrupts entry found!\n"); return (ENXIO); } + for (i = 0; i < sc->irq_num; i++) { + sc->irq_rid[i] = i; + sc->irq_res[i] = bus_alloc_resource_any(sc->dev, SYS_RES_IRQ, + &sc->irq_rid[i], RF_ACTIVE); + if (!sc->irq_res[i]) { + mtx_destroy(&sc->mutex); + device_printf(sc->dev, + "could not allocate gpio%d interrupt\n", i+1); + return (ENXIO); + } + } + + device_printf(sc->dev, "Disable interrupts (offset = %x + EDGE(0x18)\n", sc->offset); + /* Disable all interrupts */ + bus_space_write_4(sc->bst, sc->bsh, sc->offset + GPIO_INT_EDGE_MASK, 0); + device_printf(sc->dev, "Disable interrupts (offset = %x + LEV(0x1C))\n", sc->offset); + bus_space_write_4(sc->bst, sc->bsh, sc->offset + GPIO_INT_LEV_MASK, 0); + + for (i = 0; i < sc->irq_num; i++) { + device_printf(sc->dev, "Setup intr %d\n", i); + if (bus_setup_intr(sc->dev, sc->irq_res[i], + INTR_TYPE_MISC, + (driver_filter_t *)mv_gpio_intr, NULL, + sc, &sc->ih_cookie[i]) != 0) { + mtx_destroy(&sc->mutex); + bus_release_resource(sc->dev, SYS_RES_IRQ, + sc->irq_rid[i], sc->irq_res[i]); + device_printf(sc->dev, "could not set up intr %d\n", i); + return (ENXIO); + } + } + + /* Clear interrupt status. */ + device_printf(sc->dev, "Clear int status (offset = %x)\n", sc->offset); + bus_space_write_4(sc->bst, sc->bsh, sc->offset + GPIO_INT_CAUSE, 0); + sc->debounce_callouts = (struct callout **)malloc(sc->pin_num * sizeof(struct callout *), M_DEVBUF, M_WAITOK | M_ZERO); if (sc->debounce_callouts == NULL) return (ENOMEM); sc->debounce_counters = (int *)malloc(sc->pin_num * sizeof(int), M_DEVBUF, M_WAITOK); if (sc->debounce_counters == NULL) return (ENOMEM); + return (0); +} + +static int +mv_gpio_attach(device_t dev) +{ + int i, rv; + struct mv_gpio_softc *sc; + phandle_t node; + pcell_t pincnt = 0; + + sc = (struct mv_gpio_softc *)device_get_softc(dev); + if (sc == NULL) + return (ENXIO); + + node = ofw_bus_get_node(dev); + sc->dev = dev; + + if (OF_getencprop(node, "pin-count", &pincnt, sizeof(pcell_t)) >= 0 || + OF_getencprop(node, "ngpios", &pincnt, sizeof(pcell_t)) >= 0) { + sc->pin_num = MIN(pincnt, MV_GPIO_MAX_NPINS); + if (bootverbose) + device_printf(dev, "%d pins available\n", sc->pin_num); + } else { + device_printf(dev, "ERROR: no pin-count or ngpios entry found!\n"); + return (ENXIO); + } + + if (OF_getencprop(node, "offset", &sc->offset, sizeof(sc->offset)) == -1) + sc->offset = 0; + + /* Assign generic capabilities to every gpio pin */ + for(i = 0; i < sc->pin_num; i++) + sc->gpio_setup[i].gp_caps = GPIO_GENERIC_CAP; + mtx_init(&sc->mutex, device_get_nameunit(dev), NULL, MTX_SPIN); sc->mem_rid = 0; sc->mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &sc->mem_rid, - RF_ACTIVE); + RF_ACTIVE | RF_SHAREABLE ); if (!sc->mem_res) { mtx_destroy(&sc->mutex); device_printf(dev, "could not allocate memory window\n"); return (ENXIO); } sc->bst = rman_get_bustag(sc->mem_res); sc->bsh = rman_get_bushandle(sc->mem_res); - for (i = 0; i < sc->irq_num; i++) { - sc->irq_rid[i] = i; - sc->irq_res[i] = bus_alloc_resource_any(dev, SYS_RES_IRQ, - &sc->irq_rid[i], RF_ACTIVE); - if (!sc->irq_res[i]) { - mtx_destroy(&sc->mutex); - device_printf(dev, - "could not allocate gpio%d interrupt\n", i+1); - return (ENXIO); - } - } + rv = mv_gpio_setup_interrupts(sc, node); + if (rv != 0) + return (rv); - /* Disable all interrupts */ - bus_space_write_4(sc->bst, sc->bsh, GPIO_INT_EDGE_MASK, 0); - bus_space_write_4(sc->bst, sc->bsh, GPIO_INT_LEV_MASK, 0); - - for (i = 0; i < sc->irq_num; i++) { - if (bus_setup_intr(dev, sc->irq_res[i], - INTR_TYPE_MISC, - (driver_filter_t *)mv_gpio_intr, NULL, - sc, &sc->ih_cookie[i]) != 0) { - mtx_destroy(&sc->mutex); - bus_release_resource(dev, SYS_RES_IRQ, - sc->irq_rid[i], sc->irq_res[i]); - device_printf(dev, "could not set up intr %d\n", i); - return (ENXIO); - } - } - - /* Clear interrupt status. */ - bus_space_write_4(sc->bst, sc->bsh, GPIO_INT_CAUSE, 0); - sc->sc_busdev = gpiobus_attach_bus(dev); if (sc->sc_busdev == NULL) { mtx_destroy(&sc->mutex); bus_release_resource(dev, SYS_RES_IRQ, sc->irq_rid[i], sc->irq_res[i]); return (ENXIO); } return (0); } static int mv_gpio_intr(device_t dev, void *arg) { uint32_t int_cause, gpio_val; struct mv_gpio_softc *sc; sc = (struct mv_gpio_softc *)device_get_softc(dev); MV_GPIO_LOCK(); /* * According to documentation, edge sensitive interrupts are asserted * when unmasked GPIO_INT_CAUSE register bits are set. */ int_cause = mv_gpio_reg_read(dev, GPIO_INT_CAUSE); int_cause &= mv_gpio_reg_read(dev, GPIO_INT_EDGE_MASK); /* * Level sensitive interrupts are asserted when unmasked GPIO_DATA_IN * register bits are set. */ gpio_val = mv_gpio_reg_read(dev, GPIO_DATA_IN); gpio_val &= mv_gpio_reg_read(dev, GPIO_INT_LEV_MASK); mv_gpio_exec_intr_handlers(dev, int_cause | gpio_val, 0); MV_GPIO_UNLOCK(); return (FILTER_HANDLED); } /* * GPIO interrupt handling */ void mv_gpio_finish_intrhandler(struct mv_gpio_pindev *s) { /* When we acheive full interrupt support * This function will be opposite to * mv_gpio_setup_intrhandler */ /* Now it exists only to remind that * there should be place to free mv_gpio_pindev * allocated by mv_gpio_setup_intrhandler */ free(s, M_DEVBUF); } int mv_gpio_setup_intrhandler(device_t dev, const char *name, driver_filter_t *filt, void (*hand)(void *), void *arg, int pin, int flags, void **cookiep) { struct intr_event *event; int error; struct mv_gpio_pindev *s; struct mv_gpio_softc *sc; sc = (struct mv_gpio_softc *)device_get_softc(dev); s = malloc(sizeof(struct mv_gpio_pindev), M_DEVBUF, M_NOWAIT | M_ZERO); if (pin < 0 || pin >= sc->pin_num) return (ENXIO); event = sc->gpio_events[pin]; if (event == NULL) { MV_GPIO_LOCK(); if (sc->gpio_setup[pin].gp_flags & MV_GPIO_IN_DEBOUNCE) { error = mv_gpio_debounce_init(dev, pin); if (error != 0) { MV_GPIO_UNLOCK(); return (error); } } else if (sc->gpio_setup[pin].gp_flags & MV_GPIO_IN_IRQ_DOUBLE_EDGE) mv_gpio_double_edge_init(dev, pin); MV_GPIO_UNLOCK(); error = intr_event_create(&event, (void *)s, 0, pin, (void (*)(void *))mv_gpio_intr_mask, (void (*)(void *))mv_gpio_intr_unmask, (void (*)(void *))mv_gpio_int_ack, NULL, "gpio%d:", pin); if (error != 0) return (error); sc->gpio_events[pin] = event; } intr_event_add_handler(event, name, filt, hand, arg, intr_priority(flags), flags, cookiep); return (0); } static void mv_gpio_intr_mask(struct mv_gpio_pindev *s) { struct mv_gpio_softc *sc; sc = (struct mv_gpio_softc *)device_get_softc(s->dev); if (s->pin >= sc->pin_num) return; MV_GPIO_LOCK(); if (sc->gpio_setup[s->pin].gp_flags & (MV_GPIO_IN_IRQ_EDGE | MV_GPIO_IN_IRQ_DOUBLE_EDGE)) mv_gpio_edge(s->dev, s->pin, 0); else mv_gpio_level(s->dev, s->pin, 0); /* * The interrupt has to be acknowledged before scheduling an interrupt * thread. This way we allow for interrupt source to trigger again * (which can happen with shared IRQs e.g. PCI) while processing the * current event. */ mv_gpio_int_ack(s); MV_GPIO_UNLOCK(); return; } static void mv_gpio_intr_unmask(struct mv_gpio_pindev *s) { struct mv_gpio_softc *sc; sc = (struct mv_gpio_softc *)device_get_softc(s->dev); if (s->pin >= sc->pin_num) return; MV_GPIO_LOCK(); if (sc->gpio_setup[s->pin].gp_flags & (MV_GPIO_IN_IRQ_EDGE | MV_GPIO_IN_IRQ_DOUBLE_EDGE)) mv_gpio_edge(s->dev, s->pin, 1); else mv_gpio_level(s->dev, s->pin, 1); MV_GPIO_UNLOCK(); return; } static void mv_gpio_exec_intr_handlers(device_t dev, uint32_t status, int high) { int i, pin; struct mv_gpio_softc *sc; sc = (struct mv_gpio_softc *)device_get_softc(dev); MV_GPIO_ASSERT_LOCKED(); i = 0; while (status != 0) { if (status & 1) { pin = (high ? (i + GPIO_PINS_PER_REG) : i); if (sc->gpio_setup[pin].gp_flags & MV_GPIO_IN_DEBOUNCE) mv_gpio_debounce_start(dev, pin); else if (sc->gpio_setup[pin].gp_flags & MV_GPIO_IN_IRQ_DOUBLE_EDGE) { mv_gpio_polarity(dev, pin, 0, 1); mv_gpio_intr_handler(dev, pin); } else mv_gpio_intr_handler(dev, pin); } status >>= 1; i++; } } static void mv_gpio_intr_handler(device_t dev, int pin) { #ifdef INTRNG struct intr_irqsrc isrc; struct mv_gpio_softc *sc; sc = (struct mv_gpio_softc *)device_get_softc(dev); MV_GPIO_ASSERT_LOCKED(); #ifdef INTR_SOLO isrc.isrc_filter = NULL; #endif isrc.isrc_event = sc->gpio_events[pin]; if (isrc.isrc_event == NULL || CK_SLIST_EMPTY(&isrc.isrc_event->ie_handlers)) return; intr_isrc_dispatch(&isrc, NULL); #endif } int mv_gpio_configure(device_t dev, uint32_t pin, uint32_t flags, uint32_t mask) { int error; struct mv_gpio_softc *sc; sc = (struct mv_gpio_softc *)device_get_softc(dev); error = 0; if (pin >= sc->pin_num) return (EINVAL); /* check flags consistency */ if (((flags & mask) & (GPIO_PIN_INPUT | GPIO_PIN_OUTPUT)) == (GPIO_PIN_INPUT | GPIO_PIN_OUTPUT)) return (EINVAL); if (mask & MV_GPIO_IN_DEBOUNCE) { + if (sc->irq_num == 0) + return (EINVAL); error = mv_gpio_debounce_prepare(dev, pin); if (error != 0) return (error); } MV_GPIO_LOCK(); if ((mask & flags) & GPIO_PIN_INPUT) mv_gpio_out_en(dev, pin, 0); if ((mask & flags) & GPIO_PIN_OUTPUT) { if ((flags & mask) & GPIO_PIN_OPENDRAIN) mv_gpio_value_set(dev, pin, 0); else mv_gpio_value_set(dev, pin, 1); mv_gpio_out_en(dev, pin, 1); } if (mask & MV_GPIO_OUT_BLINK) mv_gpio_blink(dev, pin, flags & MV_GPIO_OUT_BLINK); if (mask & MV_GPIO_IN_POL_LOW) mv_gpio_polarity(dev, pin, flags & MV_GPIO_IN_POL_LOW, 0); if (mask & MV_GPIO_IN_DEBOUNCE) { error = mv_gpio_debounce_setup(dev, pin); if (error) { MV_GPIO_UNLOCK(); return (error); } } sc->gpio_setup[pin].gp_flags &= ~(mask); sc->gpio_setup[pin].gp_flags |= (flags & mask); MV_GPIO_UNLOCK(); return (0); } static void mv_gpio_double_edge_init(device_t dev, int pin) { uint8_t raw_read; struct mv_gpio_softc *sc; sc = (struct mv_gpio_softc *)device_get_softc(dev); MV_GPIO_ASSERT_LOCKED(); raw_read = (mv_gpio_value_get(dev, pin, 1) ? 1 : 0); if (raw_read) mv_gpio_polarity(dev, pin, 1, 0); else mv_gpio_polarity(dev, pin, 0, 0); } static int mv_gpio_debounce_setup(device_t dev, int pin) { struct callout *c; struct mv_gpio_softc *sc; sc = (struct mv_gpio_softc *)device_get_softc(dev); MV_GPIO_ASSERT_LOCKED(); c = sc->debounce_callouts[pin]; if (c == NULL) return (ENXIO); if (callout_active(c)) callout_deactivate(c); callout_stop(c); return (0); } static int mv_gpio_debounce_prepare(device_t dev, int pin) { struct callout *c; struct mv_gpio_softc *sc; sc = (struct mv_gpio_softc *)device_get_softc(dev); c = sc->debounce_callouts[pin]; if (c == NULL) { c = (struct callout *)malloc(sizeof(struct callout), M_DEVBUF, M_WAITOK); sc->debounce_callouts[pin] = c; if (c == NULL) return (ENOMEM); callout_init(c, 1); } return (0); } static int mv_gpio_debounce_init(device_t dev, int pin) { uint8_t raw_read; int *cnt; struct mv_gpio_softc *sc; sc = (struct mv_gpio_softc *)device_get_softc(dev); MV_GPIO_ASSERT_LOCKED(); cnt = &sc->debounce_counters[pin]; raw_read = (mv_gpio_value_get(dev, pin, 1) ? 1 : 0); if (raw_read) { mv_gpio_polarity(dev, pin, 1, 0); *cnt = DEBOUNCE_HI_LO_MS / DEBOUNCE_CHECK_MS; } else { mv_gpio_polarity(dev, pin, 0, 0); *cnt = DEBOUNCE_LO_HI_MS / DEBOUNCE_CHECK_MS; } mv_gpio_debounced_state_set(dev, pin, raw_read); return (0); } static void mv_gpio_debounce_start(device_t dev, int pin) { struct callout *c; struct mv_gpio_pindev s = {dev, pin}; struct mv_gpio_pindev *sd; struct mv_gpio_softc *sc; sc = (struct mv_gpio_softc *)device_get_softc(dev); MV_GPIO_ASSERT_LOCKED(); c = sc->debounce_callouts[pin]; if (c == NULL) { mv_gpio_int_ack(&s); return; } if (callout_pending(c) || callout_active(c)) { mv_gpio_int_ack(&s); return; } sd = (struct mv_gpio_pindev *)malloc(sizeof(struct mv_gpio_pindev), M_DEVBUF, M_WAITOK); if (sd == NULL) { mv_gpio_int_ack(&s); return; } sd->pin = pin; sd->dev = dev; callout_reset(c, DEBOUNCE_CHECK_TICKS, mv_gpio_debounce, sd); } static void mv_gpio_debounce(void *arg) { uint8_t raw_read, last_state; int pin; device_t dev; int *debounce_counter; struct mv_gpio_softc *sc; struct mv_gpio_pindev *s; s = (struct mv_gpio_pindev *)arg; dev = s->dev; pin = s->pin; sc = (struct mv_gpio_softc *)device_get_softc(dev); MV_GPIO_LOCK(); raw_read = (mv_gpio_value_get(dev, pin, 1) ? 1 : 0); last_state = (mv_gpio_debounced_state_get(dev, pin) ? 1 : 0); debounce_counter = &sc->debounce_counters[pin]; if (raw_read == last_state) { if (last_state) *debounce_counter = DEBOUNCE_HI_LO_MS / DEBOUNCE_CHECK_MS; else *debounce_counter = DEBOUNCE_LO_HI_MS / DEBOUNCE_CHECK_MS; callout_reset(sc->debounce_callouts[pin], DEBOUNCE_CHECK_TICKS, mv_gpio_debounce, arg); } else { *debounce_counter = *debounce_counter - 1; if (*debounce_counter != 0) callout_reset(sc->debounce_callouts[pin], DEBOUNCE_CHECK_TICKS, mv_gpio_debounce, arg); else { mv_gpio_debounced_state_set(dev, pin, raw_read); if (last_state) *debounce_counter = DEBOUNCE_HI_LO_MS / DEBOUNCE_CHECK_MS; else *debounce_counter = DEBOUNCE_LO_HI_MS / DEBOUNCE_CHECK_MS; if (((sc->gpio_setup[pin].gp_flags & MV_GPIO_IN_POL_LOW) && (raw_read == 0)) || (((sc->gpio_setup[pin].gp_flags & MV_GPIO_IN_POL_LOW) == 0) && raw_read) || (sc->gpio_setup[pin].gp_flags & MV_GPIO_IN_IRQ_DOUBLE_EDGE)) mv_gpio_intr_handler(dev, pin); /* Toggle polarity for next edge. */ mv_gpio_polarity(dev, pin, 0, 1); free(arg, M_DEVBUF); callout_deactivate(sc->debounce_callouts[pin]); } } MV_GPIO_UNLOCK(); } static void mv_gpio_debounced_state_set(device_t dev, int pin, uint8_t new_state) { uint32_t *old_state; struct mv_gpio_softc *sc; sc = (struct mv_gpio_softc *)device_get_softc(dev); MV_GPIO_ASSERT_LOCKED(); if (pin >= GPIO_PINS_PER_REG) { old_state = &sc->debounced_state_hi; pin -= GPIO_PINS_PER_REG; } else old_state = &sc->debounced_state_lo; if (new_state) *old_state |= (1 << pin); else *old_state &= ~(1 << pin); } static uint32_t mv_gpio_debounced_state_get(device_t dev, int pin) { uint32_t *state; struct mv_gpio_softc *sc; sc = (struct mv_gpio_softc *)device_get_softc(dev); MV_GPIO_ASSERT_LOCKED(); if (pin >= GPIO_PINS_PER_REG) { state = &sc->debounced_state_hi; pin -= GPIO_PINS_PER_REG; } else state = &sc->debounced_state_lo; return (*state & (1 << pin)); } void mv_gpio_out(device_t dev, uint32_t pin, uint8_t val, uint8_t enable) { struct mv_gpio_softc *sc; sc = (struct mv_gpio_softc *)device_get_softc(dev); MV_GPIO_LOCK(); mv_gpio_value_set(dev, pin, val); mv_gpio_out_en(dev, pin, enable); MV_GPIO_UNLOCK(); } uint8_t mv_gpio_in(device_t dev, uint32_t pin) { uint8_t state; struct mv_gpio_softc *sc; sc = (struct mv_gpio_softc *)device_get_softc(dev); MV_GPIO_ASSERT_LOCKED(); if (sc->gpio_setup[pin].gp_flags & MV_GPIO_IN_DEBOUNCE) { if (sc->gpio_setup[pin].gp_flags & MV_GPIO_IN_POL_LOW) state = (mv_gpio_debounced_state_get(dev, pin) ? 0 : 1); else state = (mv_gpio_debounced_state_get(dev, pin) ? 1 : 0); } else if (sc->gpio_setup[pin].gp_flags & MV_GPIO_IN_IRQ_DOUBLE_EDGE) { if (sc->gpio_setup[pin].gp_flags & MV_GPIO_IN_POL_LOW) state = (mv_gpio_value_get(dev, pin, 1) ? 0 : 1); else state = (mv_gpio_value_get(dev, pin, 1) ? 1 : 0); } else state = (mv_gpio_value_get(dev, pin, 0) ? 1 : 0); return (state); } static uint32_t mv_gpio_reg_read(device_t dev, uint32_t reg) { struct mv_gpio_softc *sc; sc = (struct mv_gpio_softc *)device_get_softc(dev); - return (bus_space_read_4(sc->bst, sc->bsh, reg)); + return (bus_space_read_4(sc->bst, sc->bsh, sc->offset + reg)); } static void mv_gpio_reg_write(device_t dev, uint32_t reg, uint32_t val) { struct mv_gpio_softc *sc; sc = (struct mv_gpio_softc *)device_get_softc(dev); - bus_space_write_4(sc->bst, sc->bsh, reg, val); + bus_space_write_4(sc->bst, sc->bsh, sc->offset + reg, val); } static void mv_gpio_reg_set(device_t dev, uint32_t reg, uint32_t pin) { uint32_t reg_val; reg_val = mv_gpio_reg_read(dev, reg); reg_val |= GPIO(pin); mv_gpio_reg_write(dev, reg, reg_val); } static void mv_gpio_reg_clear(device_t dev, uint32_t reg, uint32_t pin) { uint32_t reg_val; reg_val = mv_gpio_reg_read(dev, reg); reg_val &= ~(GPIO(pin)); mv_gpio_reg_write(dev, reg, reg_val); } static void mv_gpio_out_en(device_t dev, uint32_t pin, uint8_t enable) { uint32_t reg; struct mv_gpio_softc *sc; sc = (struct mv_gpio_softc *)device_get_softc(dev); if (pin >= sc->pin_num) return; reg = GPIO_DATA_OUT_EN_CTRL; if (enable) mv_gpio_reg_clear(dev, reg, pin); else mv_gpio_reg_set(dev, reg, pin); } static void mv_gpio_blink(device_t dev, uint32_t pin, uint8_t enable) { uint32_t reg; struct mv_gpio_softc *sc; sc = (struct mv_gpio_softc *)device_get_softc(dev); if (pin >= sc->pin_num) return; reg = GPIO_BLINK_EN; if (enable) mv_gpio_reg_set(dev, reg, pin); else mv_gpio_reg_clear(dev, reg, pin); } static void mv_gpio_polarity(device_t dev, uint32_t pin, uint8_t enable, uint8_t toggle) { uint32_t reg, reg_val; struct mv_gpio_softc *sc; sc = (struct mv_gpio_softc *)device_get_softc(dev); if (pin >= sc->pin_num) return; reg = GPIO_DATA_IN_POLAR; if (toggle) { reg_val = mv_gpio_reg_read(dev, reg) & GPIO(pin); if (reg_val) mv_gpio_reg_clear(dev, reg, pin); else mv_gpio_reg_set(dev, reg, pin); } else if (enable) mv_gpio_reg_set(dev, reg, pin); else mv_gpio_reg_clear(dev, reg, pin); } static void mv_gpio_level(device_t dev, uint32_t pin, uint8_t enable) { uint32_t reg; struct mv_gpio_softc *sc; sc = (struct mv_gpio_softc *)device_get_softc(dev); if (pin >= sc->pin_num) return; reg = GPIO_INT_LEV_MASK; if (enable) mv_gpio_reg_set(dev, reg, pin); else mv_gpio_reg_clear(dev, reg, pin); } static void mv_gpio_edge(device_t dev, uint32_t pin, uint8_t enable) { uint32_t reg; struct mv_gpio_softc *sc; sc = (struct mv_gpio_softc *)device_get_softc(dev); if (pin >= sc->pin_num) return; reg = GPIO_INT_EDGE_MASK; if (enable) mv_gpio_reg_set(dev, reg, pin); else mv_gpio_reg_clear(dev, reg, pin); } static void mv_gpio_int_ack(struct mv_gpio_pindev *s) { uint32_t reg, pin; struct mv_gpio_softc *sc; sc = (struct mv_gpio_softc *)device_get_softc(s->dev); pin = s->pin; if (pin >= sc->pin_num) return; reg = GPIO_INT_CAUSE; mv_gpio_reg_clear(s->dev, reg, pin); } static uint32_t mv_gpio_value_get(device_t dev, uint32_t pin, uint8_t exclude_polar) { uint32_t reg, polar_reg, reg_val, polar_reg_val; struct mv_gpio_softc *sc; sc = (struct mv_gpio_softc *)device_get_softc(dev); if (pin >= sc->pin_num) return (0); reg = GPIO_DATA_IN; polar_reg = GPIO_DATA_IN_POLAR; reg_val = mv_gpio_reg_read(dev, reg); if (exclude_polar) { polar_reg_val = mv_gpio_reg_read(dev, polar_reg); return ((reg_val & GPIO(pin)) ^ (polar_reg_val & GPIO(pin))); } else return (reg_val & GPIO(pin)); } static void mv_gpio_value_set(device_t dev, uint32_t pin, uint8_t val) { uint32_t reg; struct mv_gpio_softc *sc; sc = (struct mv_gpio_softc *)device_get_softc(dev); MV_GPIO_ASSERT_LOCKED(); if (pin >= sc->pin_num) return; reg = GPIO_DATA_OUT; if (val) mv_gpio_reg_set(dev, reg, pin); else mv_gpio_reg_clear(dev, reg, pin); } /* * GPIO interface methods */ static int mv_gpio_pin_max(device_t dev, int *maxpin) { struct mv_gpio_softc *sc; if (maxpin == NULL) return (EINVAL); sc = device_get_softc(dev); *maxpin = sc->pin_num; return (0); } static int mv_gpio_pin_getcaps(device_t dev, uint32_t pin, uint32_t *caps) { struct mv_gpio_softc *sc = device_get_softc(dev); if (caps == NULL) return (EINVAL); if (pin >= sc->pin_num) return (EINVAL); MV_GPIO_LOCK(); *caps = sc->gpio_setup[pin].gp_caps; MV_GPIO_UNLOCK(); return (0); } static int mv_gpio_pin_getflags(device_t dev, uint32_t pin, uint32_t *flags) { struct mv_gpio_softc *sc = device_get_softc(dev); if (flags == NULL) return (EINVAL); if (pin >= sc->pin_num) return (EINVAL); MV_GPIO_LOCK(); *flags = sc->gpio_setup[pin].gp_flags; MV_GPIO_UNLOCK(); return (0); } static int mv_gpio_pin_getname(device_t dev, uint32_t pin, char *name) { struct mv_gpio_softc *sc = device_get_softc(dev); if (name == NULL) return (EINVAL); if (pin >= sc->pin_num) return (EINVAL); MV_GPIO_LOCK(); memcpy(name, sc->gpio_setup[pin].gp_name, GPIOMAXNAME); MV_GPIO_UNLOCK(); return (0); } static int mv_gpio_pin_setflags(device_t dev, uint32_t pin, uint32_t flags) { int ret; struct mv_gpio_softc *sc = device_get_softc(dev); if (pin >= sc->pin_num) return (EINVAL); /* Check for unwanted flags. */ if ((flags & sc->gpio_setup[pin].gp_caps) != flags) return (EINVAL); ret = mv_gpio_configure(dev, pin, flags, ~0); return (ret); } static int mv_gpio_pin_set(device_t dev, uint32_t pin, unsigned int value) { struct mv_gpio_softc *sc = device_get_softc(dev); if (pin >= sc->pin_num) return (EINVAL); MV_GPIO_LOCK(); mv_gpio_value_set(dev, pin, value); MV_GPIO_UNLOCK(); return (0); } static int mv_gpio_pin_get(device_t dev, uint32_t pin, unsigned int *value) { struct mv_gpio_softc *sc = device_get_softc(dev); if (value == NULL) return (EINVAL); if (pin >= sc->pin_num) return (EINVAL); MV_GPIO_LOCK(); *value = mv_gpio_in(dev, pin); MV_GPIO_UNLOCK(); return (0); } static int mv_gpio_pin_toggle(device_t dev, uint32_t pin) { struct mv_gpio_softc *sc = device_get_softc(dev); uint32_t value; if (pin >= sc->pin_num) return (EINVAL); MV_GPIO_LOCK(); value = mv_gpio_in(dev, pin); value = (~value) & 1; mv_gpio_value_set(dev, pin, value); MV_GPIO_UNLOCK(); return (0); } static device_t mv_gpio_get_bus(device_t dev) { struct mv_gpio_softc *sc = device_get_softc(dev); return (sc->sc_busdev); } static int mv_gpio_map_gpios(device_t bus, phandle_t dev, phandle_t gparent, int gcells, pcell_t *gpios, uint32_t *pin, uint32_t *flags) { struct mv_gpio_softc *sc = device_get_softc(bus); if (gpios[0] >= sc->pin_num) return (EINVAL); *pin = gpios[0]; *flags = gpios[1]; mv_gpio_configure(bus, *pin, *flags, ~0); return (0); } Index: head/sys/arm64/conf/GENERIC =================================================================== --- head/sys/arm64/conf/GENERIC (revision 342012) +++ head/sys/arm64/conf/GENERIC (revision 342013) @@ -1,294 +1,295 @@ # # GENERIC -- Generic kernel configuration file for FreeBSD/arm64 # # For more information on this file, please read the config(5) manual page, # and/or the handbook section on Kernel Configuration Files: # # https://www.FreeBSD.org/doc/en_US.ISO8859-1/books/handbook/kernelconfig-config.html # # The handbook is also available locally in /usr/share/doc/handbook # if you've installed the doc distribution, otherwise always see the # FreeBSD World Wide Web server (https://www.FreeBSD.org/) for the # latest information. # # An exhaustive list of options and more detailed explanations of the # device lines is also present in the ../../conf/NOTES and NOTES files. # If you are in doubt as to the purpose or necessity of a line, check first # in NOTES. # # $FreeBSD$ cpu ARM64 ident GENERIC makeoptions DEBUG=-g # Build kernel with gdb(1) debug symbols makeoptions WITH_CTF=1 # Run ctfconvert(1) for DTrace support options SCHED_ULE # ULE scheduler options PREEMPTION # Enable kernel thread preemption options VIMAGE # Subsystem virtualization, e.g. VNET options INET # InterNETworking options INET6 # IPv6 communications protocols options IPSEC # IP (v4/v6) security options IPSEC_SUPPORT # Allow kldload of ipsec and tcpmd5 options TCP_HHOOK # hhook(9) framework for TCP options TCP_OFFLOAD # TCP offload options TCP_RFC7413 # TCP Fast Open options SCTP # Stream Control Transmission Protocol options FFS # Berkeley Fast Filesystem options SOFTUPDATES # Enable FFS soft updates support options UFS_ACL # Support for access control lists options UFS_DIRHASH # Improve performance on big directories options UFS_GJOURNAL # Enable gjournal-based UFS journaling options QUOTA # Enable disk quotas for UFS options MD_ROOT # MD is a potential root device options NFSCL # Network Filesystem Client options NFSD # Network Filesystem Server options NFSLOCKD # Network Lock Manager options NFS_ROOT # NFS usable as /, requires NFSCL options MSDOSFS # MSDOS Filesystem options CD9660 # ISO 9660 Filesystem options PROCFS # Process filesystem (requires PSEUDOFS) options PSEUDOFS # Pseudo-filesystem framework options GEOM_RAID # Soft RAID functionality. options GEOM_LABEL # Provides labelization options COMPAT_FREEBSD32 # Incomplete, but used by cloudabi32.ko. options COMPAT_FREEBSD11 # Compatible with FreeBSD11 options SCSI_DELAY=5000 # Delay (in ms) before probing SCSI options KTRACE # ktrace(1) support options STACK # stack(9) support options SYSVSHM # SYSV-style shared memory options SYSVMSG # SYSV-style message queues options SYSVSEM # SYSV-style semaphores options _KPOSIX_PRIORITY_SCHEDULING # POSIX P1003_1B real-time extensions options PRINTF_BUFR_SIZE=128 # Prevent printf output being interspersed. options KBD_INSTALL_CDEV # install a CDEV entry in /dev options HWPMC_HOOKS # Necessary kernel hooks for hwpmc(4) options AUDIT # Security event auditing options CAPABILITY_MODE # Capsicum capability mode options CAPABILITIES # Capsicum capabilities options MAC # TrustedBSD MAC Framework options KDTRACE_FRAME # Ensure frames are compiled in options KDTRACE_HOOKS # Kernel DTrace hooks options VFP # Floating-point support options RACCT # Resource accounting framework options RACCT_DEFAULT_TO_DISABLED # Set kern.racct.enable=0 by default options RCTL # Resource limits options SMP options INTRNG # Debugging support. Always need this: options KDB # Enable kernel debugger support. options KDB_TRACE # Print a stack trace for a panic. # For full debugger support use (turn off in stable branch): options DDB # Support DDB. #options GDB # Support remote GDB. options DEADLKRES # Enable the deadlock resolver options INVARIANTS # Enable calls of extra sanity checking options INVARIANT_SUPPORT # Extra sanity checks of internal structures, required by INVARIANTS options WITNESS # Enable checks to detect deadlocks and cycles options WITNESS_SKIPSPIN # Don't run witness on spinlocks for speed options MALLOC_DEBUG_MAXZONES=8 # Separate malloc(9) zones options ALT_BREAK_TO_DEBUGGER # Enter debugger on keyboard escape sequence options USB_DEBUG # enable debug msgs options VERBOSE_SYSINIT=0 # Support debug.verbose_sysinit, off by default # Warning: KUBSAN can result in a kernel too large for loader to load #options KUBSAN # Kernel Undefined Behavior Sanitizer # Kernel dump features. options EKCD # Support for encrypted kernel dumps options GZIO # gzip-compressed kernel and user dumps options ZSTDIO # zstd-compressed kernel and user dumps options NETDUMP # netdump(4) client support # SoC support options SOC_ALLWINNER_A64 options SOC_ALLWINNER_H5 options SOC_CAVM_THUNDERX options SOC_HISI_HI6220 options SOC_BRCM_BCM2837 options SOC_MARVELL_8K options SOC_ROCKCHIP_RK3328 options SOC_ROCKCHIP_RK3399 options SOC_XILINX_ZYNQ # Timer drivers device a10_timer # Annapurna Alpine drivers device al_ccu # Alpine Cache Coherency Unit device al_nb_service # Alpine North Bridge Service device al_iofic # I/O Fabric Interrupt Controller device al_serdes # Serializer/Deserializer device al_udma # Universal DMA # Qualcomm Snapdragon drivers device qcom_gcc # Global Clock Controller # VirtIO support device virtio device virtio_pci device virtio_mmio device virtio_blk device vtnet # CPU frequency control device cpufreq # Bus drivers device pci device al_pci # Annapurna Alpine PCI-E options PCI_HP # PCI-Express native HotPlug options PCI_IOV # PCI SR-IOV support # Ethernet NICs device mdio device mii device miibus # MII bus support device awg # Allwinner EMAC Gigabit Ethernet device axgbe # AMD Opteron A1100 integrated NIC device em # Intel PRO/1000 Gigabit Ethernet Family device ix # Intel 10Gb Ethernet Family device msk # Marvell/SysKonnect Yukon II Gigabit Ethernet device neta # Marvell Armada 370/38x/XP/3700 NIC device smc # SMSC LAN91C111 device vnic # Cavium ThunderX NIC device al_eth # Annapurna Alpine Ethernet NIC device dwc_rk # Rockchip Designware # Block devices device ahci device scbus device da # ATA/SCSI peripherals device pass # Passthrough device (direct ATA/SCSI access) # MMC/SD/SDIO Card slot support device sdhci device sdhci_xenon # Marvell Xenon SD/MMC controller device aw_mmc # Allwinner SD/MMC controller device mmc # mmc/sd bus device mmcsd # mmc/sd flash cards device dwmmc # Serial (COM) ports device uart # Generic UART driver device uart_msm # Qualcomm MSM UART driver device uart_mu # RPI3 aux port device uart_mvebu # Armada 3700 UART driver device uart_ns8250 # ns8250-type UART driver device uart_snps device pl011 # USB support device aw_ehci # Allwinner EHCI USB interface (USB 2.0) device aw_usbphy # Allwinner USB PHY device dwcotg # DWC OTG controller device ohci # OHCI USB interface device ehci # EHCI USB interface (USB 2.0) device ehci_mv # Marvell EHCI USB interface device xhci # XHCI PCI->USB interface (USB 3.0) device xhci_mv # Marvell XHCI USB interface device usb # USB Bus (required) device ukbd # Keyboard device umass # Disks/Mass storage - Requires scbus and da # USB ethernet support device muge device smcphy device smsc # GPIO / PINCTRL device aw_gpio # Allwinner GPIO controller device gpio device gpioled device fdt_pinctrl +device mv_gpio # Marvell GPIO controller device mvebu_pinctrl # Marvell Pinmux Controller # I2C device aw_rsb # Allwinner Reduced Serial Bus device bcm2835_bsc # Broadcom BCM283x I2C bus device iicbus device iic device twsi # Allwinner I2C controller device rk_i2c # RockChip I2C controller device syr827 # Silergy SYR827 PMIC # Clock and reset controllers device aw_ccu # Allwinner clock controller # Interrupt controllers device aw_nmi # Allwinner NMI support # Real-time clock support device aw_rtc # Allwinner Real-time Clock device mv_rtc # Marvell Real-time Clock # Watchdog controllers device aw_wdog # Allwinner Watchdog # Power management controllers device axp81x # X-Powers AXP81x PMIC device rk805 # RockChip RK805 PMIC # EFUSE device aw_sid # Allwinner Secure ID EFUSE # Thermal sensors device aw_thermal # Allwinner Thermal Sensor Controller # SPI device spibus device bcm2835_spi # Broadcom BCM283x SPI bus # PWM device pwm device aw_pwm # Console device vt device kbdmux device vt_efifb # EVDEV support device evdev # input event device support options EVDEV_SUPPORT # evdev support in legacy drivers device uinput # install /dev/uinput cdev # Pseudo devices. device crypto # core crypto support device loop # Network loopback device random # Entropy device device ether # Ethernet support device vlan # 802.1Q VLAN support device tun # Packet tunnel. device md # Memory "disks" device gif # IPv6 and IPv4 tunneling device firmware # firmware assist module options EFIRT # EFI Runtime Services # EXT_RESOURCES pseudo devices options EXT_RESOURCES device clk device phy device hwreset device nvmem device regulator device syscon device aw_syscon # The `bpf' device enables the Berkeley Packet Filter. # Be aware of the administrative consequences of enabling this! # Note that 'bpf' is required for DHCP. device bpf # Berkeley packet filter # Chip-specific errata options THUNDERX_PASS_1_1_ERRATA options FDT device acpi # DTBs makeoptions MODULES_EXTRA="dtb/allwinner dtb/rockchip" Index: head/sys/conf/files.arm64 =================================================================== --- head/sys/conf/files.arm64 (revision 342012) +++ head/sys/conf/files.arm64 (revision 342013) @@ -1,275 +1,276 @@ # $FreeBSD$ cloudabi32_vdso.o optional compat_cloudabi32 \ dependency "$S/contrib/cloudabi/cloudabi_vdso_armv6_on_64bit.S" \ compile-with "${CC} -x assembler-with-cpp -m32 -shared -nostdinc -nostdlib -Wl,-T$S/compat/cloudabi/cloudabi_vdso.lds $S/contrib/cloudabi/cloudabi_vdso_armv6_on_64bit.S -o ${.TARGET}" \ no-obj no-implicit-rule \ clean "cloudabi32_vdso.o" # cloudabi32_vdso_blob.o optional compat_cloudabi32 \ dependency "cloudabi32_vdso.o" \ compile-with "${OBJCOPY} --input-target binary --output-target elf64-littleaarch64 --binary-architecture aarch64 cloudabi32_vdso.o ${.TARGET}" \ no-implicit-rule \ clean "cloudabi32_vdso_blob.o" # cloudabi64_vdso.o optional compat_cloudabi64 \ dependency "$S/contrib/cloudabi/cloudabi_vdso_aarch64.S" \ compile-with "${CC} -x assembler-with-cpp -shared -nostdinc -nostdlib -Wl,-T$S/compat/cloudabi/cloudabi_vdso.lds $S/contrib/cloudabi/cloudabi_vdso_aarch64.S -o ${.TARGET}" \ no-obj no-implicit-rule \ clean "cloudabi64_vdso.o" # cloudabi64_vdso_blob.o optional compat_cloudabi64 \ dependency "cloudabi64_vdso.o" \ compile-with "${OBJCOPY} --input-target binary --output-target elf64-littleaarch64 --binary-architecture aarch64 cloudabi64_vdso.o ${.TARGET}" \ no-implicit-rule \ clean "cloudabi64_vdso_blob.o" # # Allwinner common files arm/allwinner/a10_ehci.c optional ehci aw_ehci fdt arm/allwinner/a10_timer.c optional a10_timer fdt arm/allwinner/aw_gpio.c optional gpio aw_gpio fdt arm/allwinner/aw_mmc.c optional mmc aw_mmc fdt | mmccam aw_mmc fdt arm/allwinner/aw_nmi.c optional aw_nmi fdt \ compile-with "${NORMAL_C} -I$S/gnu/dts/include" arm/allwinner/aw_pwm.c optional aw_pwm fdt arm/allwinner/aw_rsb.c optional aw_rsb fdt arm/allwinner/aw_rtc.c optional aw_rtc fdt arm/allwinner/aw_sid.c optional aw_sid nvmem fdt arm/allwinner/aw_spi.c optional aw_spi fdt arm/allwinner/aw_syscon.c optional aw_syscon ext_resources syscon fdt arm/allwinner/aw_thermal.c optional aw_thermal nvmem fdt arm/allwinner/aw_usbphy.c optional ehci aw_usbphy fdt arm/allwinner/aw_wdog.c optional aw_wdog fdt arm/allwinner/axp81x.c optional axp81x fdt arm/allwinner/if_awg.c optional awg ext_resources syscon aw_sid nvmem fdt # Allwinner clock driver arm/allwinner/clkng/aw_ccung.c optional aw_ccu fdt arm/allwinner/clkng/aw_clk_nkmp.c optional aw_ccu fdt arm/allwinner/clkng/aw_clk_nm.c optional aw_ccu fdt arm/allwinner/clkng/aw_clk_prediv_mux.c optional aw_ccu fdt arm/allwinner/clkng/ccu_a64.c optional soc_allwinner_a64 aw_ccu fdt arm/allwinner/clkng/ccu_h3.c optional soc_allwinner_h5 aw_ccu fdt arm/allwinner/clkng/ccu_sun8i_r.c optional aw_ccu fdt # Allwinner padconf files arm/allwinner/a64/a64_padconf.c optional soc_allwinner_a64 fdt arm/allwinner/a64/a64_r_padconf.c optional soc_allwinner_a64 fdt arm/allwinner/h3/h3_padconf.c optional soc_allwinner_h5 fdt arm/allwinner/h3/h3_r_padconf.c optional soc_allwinner_h5 fdt arm/annapurna/alpine/alpine_ccu.c optional al_ccu fdt arm/annapurna/alpine/alpine_nb_service.c optional al_nb_service fdt arm/annapurna/alpine/alpine_pci.c optional al_pci fdt arm/annapurna/alpine/alpine_pci_msix.c optional al_pci fdt arm/annapurna/alpine/alpine_serdes.c optional al_serdes fdt \ no-depend \ compile-with "${CC} -c -o ${.TARGET} ${CFLAGS} -I$S/contrib/alpine-hal -I$S/contrib/alpine-hal/eth ${PROF} ${.IMPSRC}" arm/arm/generic_timer.c standard arm/arm/gic.c standard arm/arm/gic_acpi.c optional acpi arm/arm/gic_fdt.c optional fdt arm/arm/pmu.c standard arm/arm/physmem.c standard arm/broadcom/bcm2835/bcm2835_audio.c optional sound vchiq fdt \ compile-with "${NORMAL_C} -DUSE_VCHIQ_ARM -D__VCCOREVER__=0x04000000 -I$S/contrib/vchiq" arm/broadcom/bcm2835/bcm2835_bsc.c optional bcm2835_bsc soc_brcm_bcm2837 fdt arm/broadcom/bcm2835/bcm2835_cpufreq.c optional soc_brcm_bcm2837 fdt arm/broadcom/bcm2835/bcm2835_dma.c optional soc_brcm_bcm2837 fdt arm/broadcom/bcm2835/bcm2835_fbd.c optional vt soc_brcm_bcm2837 fdt arm/broadcom/bcm2835/bcm2835_ft5406.c optional evdev bcm2835_ft5406 soc_brcm_bcm2837 fdt arm/broadcom/bcm2835/bcm2835_gpio.c optional gpio soc_brcm_bcm2837 fdt arm/broadcom/bcm2835/bcm2835_intr.c optional soc_brcm_bcm2837 fdt arm/broadcom/bcm2835/bcm2835_mbox.c optional soc_brcm_bcm2837 fdt arm/broadcom/bcm2835/bcm2835_rng.c optional random soc_brcm_bcm2837 fdt arm/broadcom/bcm2835/bcm2835_sdhci.c optional sdhci soc_brcm_bcm2837 fdt arm/broadcom/bcm2835/bcm2835_sdhost.c optional sdhci soc_brcm_bcm2837 fdt arm/broadcom/bcm2835/bcm2835_spi.c optional bcm2835_spi soc_brcm_bcm2837 fdt arm/broadcom/bcm2835/bcm2835_vcio.c optional soc_brcm_bcm2837 fdt arm/broadcom/bcm2835/bcm2835_wdog.c optional soc_brcm_bcm2837 fdt arm/broadcom/bcm2835/bcm2836.c optional soc_brcm_bcm2837 fdt arm/broadcom/bcm2835/bcm283x_dwc_fdt.c optional dwcotg fdt soc_brcm_bcm2837 +arm/mv/gpio.c optional mv_gpio fdt arm/mv/mvebu_pinctrl.c optional mvebu_pinctrl fdt arm/mv/mv_ap806_clock.c optional SOC_MARVELL_8K fdt arm/mv/armada38x/armada38x_rtc.c optional mv_rtc fdt arm/xilinx/uart_dev_cdnc.c optional uart soc_xilinx_zynq arm64/acpica/acpi_machdep.c optional acpi arm64/acpica/OsdEnvironment.c optional acpi arm64/acpica/acpi_wakeup.c optional acpi arm64/acpica/pci_cfgreg.c optional acpi pci arm64/arm64/autoconf.c standard arm64/arm64/bus_machdep.c standard arm64/arm64/bus_space_asm.S standard arm64/arm64/busdma_bounce.c standard arm64/arm64/busdma_machdep.c standard arm64/arm64/bzero.S standard arm64/arm64/clock.c standard arm64/arm64/copyinout.S standard arm64/arm64/copystr.c standard arm64/arm64/cpu_errata.c standard arm64/arm64/cpufunc_asm.S standard arm64/arm64/db_disasm.c optional ddb arm64/arm64/db_interface.c optional ddb arm64/arm64/db_trace.c optional ddb arm64/arm64/debug_monitor.c optional ddb arm64/arm64/disassem.c optional ddb arm64/arm64/dump_machdep.c standard arm64/arm64/efirt_machdep.c optional efirt arm64/arm64/elf32_machdep.c optional compat_freebsd32 arm64/arm64/elf_machdep.c standard arm64/arm64/exception.S standard arm64/arm64/freebsd32_machdep.c optional compat_freebsd32 arm64/arm64/gicv3_its.c optional intrng fdt arm64/arm64/gic_v3.c standard arm64/arm64/gic_v3_acpi.c optional acpi arm64/arm64/gic_v3_fdt.c optional fdt arm64/arm64/identcpu.c standard arm64/arm64/in_cksum.c optional inet | inet6 arm64/arm64/locore.S standard no-obj arm64/arm64/machdep.c standard arm64/arm64/mem.c standard arm64/arm64/memcpy.S standard arm64/arm64/memmove.S standard arm64/arm64/minidump_machdep.c standard arm64/arm64/mp_machdep.c optional smp arm64/arm64/nexus.c standard arm64/arm64/ofw_machdep.c optional fdt arm64/arm64/pmap.c standard arm64/arm64/stack_machdep.c optional ddb | stack arm64/arm64/support.S standard arm64/arm64/swtch.S standard arm64/arm64/sys_machdep.c standard arm64/arm64/trap.c standard arm64/arm64/uio_machdep.c standard arm64/arm64/uma_machdep.c standard arm64/arm64/undefined.c standard arm64/arm64/unwind.c optional ddb | kdtrace_hooks | stack arm64/arm64/vfp.c standard arm64/arm64/vm_machdep.c standard arm64/cavium/thunder_pcie_fdt.c optional soc_cavm_thunderx pci fdt arm64/cavium/thunder_pcie_pem.c optional soc_cavm_thunderx pci arm64/cavium/thunder_pcie_pem_fdt.c optional soc_cavm_thunderx pci fdt arm64/cavium/thunder_pcie_common.c optional soc_cavm_thunderx pci arm64/cloudabi32/cloudabi32_sysvec.c optional compat_cloudabi32 arm64/cloudabi64/cloudabi64_sysvec.c optional compat_cloudabi64 arm64/coresight/coresight.c standard arm64/coresight/coresight_if.m standard arm64/coresight/coresight-cmd.c standard arm64/coresight/coresight-cpu-debug.c standard arm64/coresight/coresight-dynamic-replicator.c standard arm64/coresight/coresight-etm4x.c standard arm64/coresight/coresight-funnel.c standard arm64/coresight/coresight-tmc.c standard arm64/qualcomm/qcom_gcc.c optional qcom_gcc fdt contrib/vchiq/interface/compat/vchi_bsd.c optional vchiq soc_brcm_bcm2837 \ compile-with "${NORMAL_C} -DUSE_VCHIQ_ARM -D__VCCOREVER__=0x04000000 -I$S/contrib/vchiq" contrib/vchiq/interface/vchiq_arm/vchiq_2835_arm.c optional vchiq soc_brcm_bcm2837 \ compile-with "${NORMAL_C} -Wno-unused -DUSE_VCHIQ_ARM -D__VCCOREVER__=0x04000000 -I$S/contrib/vchiq" contrib/vchiq/interface/vchiq_arm/vchiq_arm.c optional vchiq soc_brcm_bcm2837 \ compile-with "${NORMAL_C} -Wno-unused -DUSE_VCHIQ_ARM -D__VCCOREVER__=0x04000000 -I$S/contrib/vchiq" contrib/vchiq/interface/vchiq_arm/vchiq_connected.c optional vchiq soc_brcm_bcm2837 \ compile-with "${NORMAL_C} -DUSE_VCHIQ_ARM -D__VCCOREVER__=0x04000000 -I$S/contrib/vchiq" contrib/vchiq/interface/vchiq_arm/vchiq_core.c optional vchiq soc_brcm_bcm2837 \ compile-with "${NORMAL_C} -DUSE_VCHIQ_ARM -D__VCCOREVER__=0x04000000 -I$S/contrib/vchiq" contrib/vchiq/interface/vchiq_arm/vchiq_kern_lib.c optional vchiq soc_brcm_bcm2837 \ compile-with "${NORMAL_C} -DUSE_VCHIQ_ARM -D__VCCOREVER__=0x04000000 -I$S/contrib/vchiq" contrib/vchiq/interface/vchiq_arm/vchiq_kmod.c optional vchiq soc_brcm_bcm2837 \ compile-with "${NORMAL_C} -DUSE_VCHIQ_ARM -D__VCCOREVER__=0x04000000 -I$S/contrib/vchiq" contrib/vchiq/interface/vchiq_arm/vchiq_shim.c optional vchiq soc_brcm_bcm2837 \ compile-with "${NORMAL_C} -DUSE_VCHIQ_ARM -D__VCCOREVER__=0x04000000 -I$S/contrib/vchiq" contrib/vchiq/interface/vchiq_arm/vchiq_util.c optional vchiq soc_brcm_bcm2837 \ compile-with "${NORMAL_C} -DUSE_VCHIQ_ARM -D__VCCOREVER__=0x04000000 -I$S/contrib/vchiq" crypto/armv8/armv8_crypto.c optional armv8crypto armv8_crypto_wrap.o optional armv8crypto \ dependency "$S/crypto/armv8/armv8_crypto_wrap.c" \ compile-with "${CC} -c ${CFLAGS:C/^-O2$/-O3/:N-nostdinc:N-mgeneral-regs-only} -I$S/crypto/armv8/ ${WERROR} ${NO_WCAST_QUAL} ${PROF} -march=armv8-a+crypto ${.IMPSRC}" \ no-implicit-rule \ clean "armv8_crypto_wrap.o" crypto/blowfish/bf_enc.c optional crypto | ipsec | ipsec_support crypto/des/des_enc.c optional crypto | ipsec | ipsec_support | netsmb dev/acpica/acpi_bus_if.m optional acpi dev/acpica/acpi_if.m optional acpi dev/acpica/acpi_pci_link.c optional acpi pci dev/acpica/acpi_pcib.c optional acpi pci dev/acpica/acpi_pxm.c optional acpi dev/ahci/ahci_generic.c optional ahci dev/axgbe/if_axgbe.c optional axgbe dev/axgbe/xgbe-desc.c optional axgbe dev/axgbe/xgbe-dev.c optional axgbe dev/axgbe/xgbe-drv.c optional axgbe dev/axgbe/xgbe-mdio.c optional axgbe dev/cpufreq/cpufreq_dt.c optional cpufreq fdt dev/iicbus/twsi/a10_twsi.c optional twsi fdt dev/iicbus/twsi/twsi.c optional twsi fdt dev/hwpmc/hwpmc_arm64.c optional hwpmc dev/hwpmc/hwpmc_arm64_md.c optional hwpmc dev/mbox/mbox_if.m optional soc_brcm_bcm2837 dev/mmc/host/dwmmc.c optional dwmmc fdt dev/mmc/host/dwmmc_hisi.c optional dwmmc fdt soc_hisi_hi6220 dev/mmc/host/dwmmc_rockchip.c optional dwmmc fdt soc_rockchip_rk3328 dev/neta/if_mvneta_fdt.c optional neta fdt dev/neta/if_mvneta.c optional neta mdio mii dev/ofw/ofw_cpu.c optional fdt dev/ofw/ofwpci.c optional fdt pci dev/pci/pci_host_generic.c optional pci dev/pci/pci_host_generic_acpi.c optional pci acpi dev/pci/pci_host_generic_fdt.c optional pci fdt dev/psci/psci.c standard dev/psci/psci_arm64.S standard dev/psci/smccc.c standard dev/sdhci/sdhci_xenon.c optional sdhci_xenon sdhci fdt dev/uart/uart_cpu_arm64.c optional uart dev/uart/uart_dev_mu.c optional uart uart_mu dev/uart/uart_dev_pl011.c optional uart pl011 dev/usb/controller/dwc_otg_hisi.c optional dwcotg fdt soc_hisi_hi6220 dev/usb/controller/ehci_mv.c optional ehci_mv fdt dev/usb/controller/generic_ehci.c optional ehci acpi dev/usb/controller/generic_ohci.c optional ohci fdt dev/usb/controller/generic_usb_if.m optional ohci fdt dev/usb/controller/xhci_mv.c optional xhci_mv fdt dev/vnic/mrml_bridge.c optional vnic fdt dev/vnic/nic_main.c optional vnic pci dev/vnic/nicvf_main.c optional vnic pci pci_iov dev/vnic/nicvf_queues.c optional vnic pci pci_iov dev/vnic/thunder_bgx_fdt.c optional vnic fdt dev/vnic/thunder_bgx.c optional vnic pci dev/vnic/thunder_mdio_fdt.c optional vnic fdt dev/vnic/thunder_mdio.c optional vnic dev/vnic/lmac_if.m optional inet | inet6 | vnic kern/kern_clocksource.c standard kern/msi_if.m optional intrng kern/pic_if.m optional intrng kern/subr_devmap.c standard kern/subr_intr.c optional intrng libkern/bcmp.c standard libkern/ffs.c standard libkern/ffsl.c standard libkern/ffsll.c standard libkern/fls.c standard libkern/flsl.c standard libkern/flsll.c standard libkern/memcmp.c standard libkern/memset.c standard libkern/arm64/crc32c_armv8.S standard cddl/contrib/opensolaris/common/atomic/aarch64/opensolaris_atomic.S optional zfs | dtrace compile-with "${CDDL_C}" cddl/dev/dtrace/aarch64/dtrace_asm.S optional dtrace compile-with "${DTRACE_S}" cddl/dev/dtrace/aarch64/dtrace_subr.c optional dtrace compile-with "${DTRACE_C}" cddl/dev/fbt/aarch64/fbt_isa.c optional dtrace_fbt | dtraceall compile-with "${FBT_C}" arm64/rockchip/rk_i2c.c optional rk_i2c fdt soc_rockchip_rk3328 soc_rockchip_rk3399 arm64/rockchip/rk805.c optional rk805 fdt soc_rockchip_rk3328 arm64/rockchip/rk_grf.c optional fdt soc_rockchip_rk3328 soc_rockchip_rk3399 arm64/rockchip/rk_pinctrl.c optional fdt soc_rockchip_rk3328 soc_rockchip_rk3399 arm64/rockchip/rk_gpio.c optional fdt soc_rockchip_rk3328 soc_rockchip_rk3399 arm64/rockchip/clk/rk_cru.c optional fdt soc_rockchip_rk3328 soc_rockchip_rk3399 arm64/rockchip/clk/rk_clk_armclk.c optional fdt soc_rockchip_rk3328 soc_rockchip_rk3399 arm64/rockchip/clk/rk_clk_composite.c optional fdt soc_rockchip_rk3328 soc_rockchip_rk3399 arm64/rockchip/clk/rk_clk_gate.c optional fdt soc_rockchip_rk3328 soc_rockchip_rk3399 arm64/rockchip/clk/rk_clk_mux.c optional fdt soc_rockchip_rk3328 soc_rockchip_rk3399 arm64/rockchip/clk/rk_clk_pll.c optional fdt soc_rockchip_rk3328 soc_rockchip_rk3399 arm64/rockchip/clk/rk3328_cru.c optional fdt soc_rockchip_rk3328 arm64/rockchip/clk/rk3399_cru.c optional fdt soc_rockchip_rk3399 arm64/rockchip/clk/rk3399_pmucru.c optional fdt soc_rockchip_rk3399 arm64/rockchip/if_dwc_rk.c optional dwc_rk fdt soc_rockchip_rk3328 soc_rockchip_rk3399 dev/dwc/if_dwc.c optional dwc_rk dev/dwc/if_dwc_if.m optional dwc_rk