Index: head/sys/dev/mlx5/driver.h
===================================================================
--- head/sys/dev/mlx5/driver.h	(revision 341574)
+++ head/sys/dev/mlx5/driver.h	(revision 341575)
@@ -1,1191 +1,1192 @@
 /*-
  * Copyright (c) 2013-2017, Mellanox Technologies, Ltd.  All rights reserved.
  *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions
  * are met:
  * 1. Redistributions of source code must retain the above copyright
  *    notice, this list of conditions and the following disclaimer.
  * 2. Redistributions in binary form must reproduce the above copyright
  *    notice, this list of conditions and the following disclaimer in the
  *    documentation and/or other materials provided with the distribution.
  *
  * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS `AS IS' AND
  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  * ARE DISCLAIMED.  IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE
  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  * SUCH DAMAGE.
  *
  * $FreeBSD$
  */
 
 #ifndef MLX5_DRIVER_H
 #define MLX5_DRIVER_H
 
 #include "opt_ratelimit.h"
 
 #include <linux/kernel.h>
 #include <linux/completion.h>
 #include <linux/pci.h>
 #include <linux/cache.h>
 #include <linux/rbtree.h>
 #include <linux/if_ether.h>
 #include <linux/semaphore.h>
 #include <linux/slab.h>
 #include <linux/vmalloc.h>
 #include <linux/radix-tree.h>
 #include <linux/idr.h>
 
 #include <dev/mlx5/device.h>
 #include <dev/mlx5/doorbell.h>
 #include <dev/mlx5/srq.h>
 
 #define MLX5_QCOUNTER_SETS_NETDEV 64
 #define MLX5_MAX_NUMBER_OF_VFS 128
 
 enum {
 	MLX5_BOARD_ID_LEN = 64,
 	MLX5_MAX_NAME_LEN = 16,
 };
 
 enum {
 	MLX5_CMD_TIMEOUT_MSEC	= 8 * 60 * 1000,
 	MLX5_CMD_WQ_MAX_NAME	= 32,
 };
 
 enum {
 	CMD_OWNER_SW		= 0x0,
 	CMD_OWNER_HW		= 0x1,
 	CMD_STATUS_SUCCESS	= 0,
 };
 
 enum mlx5_sqp_t {
 	MLX5_SQP_SMI		= 0,
 	MLX5_SQP_GSI		= 1,
 	MLX5_SQP_IEEE_1588	= 2,
 	MLX5_SQP_SNIFFER	= 3,
 	MLX5_SQP_SYNC_UMR	= 4,
 };
 
 enum {
 	MLX5_MAX_PORTS	= 2,
 };
 
 enum {
 	MLX5_EQ_VEC_PAGES	 = 0,
 	MLX5_EQ_VEC_CMD		 = 1,
 	MLX5_EQ_VEC_ASYNC	 = 2,
 	MLX5_EQ_VEC_COMP_BASE,
 };
 
 enum {
 	MLX5_MAX_IRQ_NAME	= 32
 };
 
 enum {
 	MLX5_ATOMIC_MODE_OFF		= 16,
 	MLX5_ATOMIC_MODE_NONE		= 0 << MLX5_ATOMIC_MODE_OFF,
 	MLX5_ATOMIC_MODE_IB_COMP	= 1 << MLX5_ATOMIC_MODE_OFF,
 	MLX5_ATOMIC_MODE_CX		= 2 << MLX5_ATOMIC_MODE_OFF,
 	MLX5_ATOMIC_MODE_8B		= 3 << MLX5_ATOMIC_MODE_OFF,
 	MLX5_ATOMIC_MODE_16B		= 4 << MLX5_ATOMIC_MODE_OFF,
 	MLX5_ATOMIC_MODE_32B		= 5 << MLX5_ATOMIC_MODE_OFF,
 	MLX5_ATOMIC_MODE_64B		= 6 << MLX5_ATOMIC_MODE_OFF,
 	MLX5_ATOMIC_MODE_128B		= 7 << MLX5_ATOMIC_MODE_OFF,
 	MLX5_ATOMIC_MODE_256B		= 8 << MLX5_ATOMIC_MODE_OFF,
 };
 
 enum {
 	MLX5_ATOMIC_MODE_DCT_OFF	= 20,
 	MLX5_ATOMIC_MODE_DCT_NONE	= 0 << MLX5_ATOMIC_MODE_DCT_OFF,
 	MLX5_ATOMIC_MODE_DCT_IB_COMP	= 1 << MLX5_ATOMIC_MODE_DCT_OFF,
 	MLX5_ATOMIC_MODE_DCT_CX		= 2 << MLX5_ATOMIC_MODE_DCT_OFF,
 	MLX5_ATOMIC_MODE_DCT_8B		= 3 << MLX5_ATOMIC_MODE_DCT_OFF,
 	MLX5_ATOMIC_MODE_DCT_16B	= 4 << MLX5_ATOMIC_MODE_DCT_OFF,
 	MLX5_ATOMIC_MODE_DCT_32B	= 5 << MLX5_ATOMIC_MODE_DCT_OFF,
 	MLX5_ATOMIC_MODE_DCT_64B	= 6 << MLX5_ATOMIC_MODE_DCT_OFF,
 	MLX5_ATOMIC_MODE_DCT_128B	= 7 << MLX5_ATOMIC_MODE_DCT_OFF,
 	MLX5_ATOMIC_MODE_DCT_256B	= 8 << MLX5_ATOMIC_MODE_DCT_OFF,
 };
 
 enum {
 	MLX5_ATOMIC_OPS_CMP_SWAP		= 1 << 0,
 	MLX5_ATOMIC_OPS_FETCH_ADD		= 1 << 1,
 	MLX5_ATOMIC_OPS_MASKED_CMP_SWAP		= 1 << 2,
 	MLX5_ATOMIC_OPS_MASKED_FETCH_ADD	= 1 << 3,
 };
 
 enum {
 	MLX5_REG_QPTS		 = 0x4002,
 	MLX5_REG_QETCR		 = 0x4005,
 	MLX5_REG_QPDP		 = 0x4007,
 	MLX5_REG_QTCT		 = 0x400A,
 	MLX5_REG_QPDPM		 = 0x4013,
 	MLX5_REG_QHLL		 = 0x4016,
 	MLX5_REG_QCAM		 = 0x4019,
 	MLX5_REG_DCBX_PARAM	 = 0x4020,
 	MLX5_REG_DCBX_APP	 = 0x4021,
 	MLX5_REG_PCAP		 = 0x5001,
 	MLX5_REG_FPGA_CAP	 = 0x4022,
 	MLX5_REG_FPGA_CTRL	 = 0x4023,
 	MLX5_REG_FPGA_ACCESS_REG = 0x4024,
 	MLX5_REG_FPGA_SHELL_CNTR = 0x4025,
 	MLX5_REG_PMTU		 = 0x5003,
 	MLX5_REG_PTYS		 = 0x5004,
 	MLX5_REG_PAOS		 = 0x5006,
 	MLX5_REG_PFCC		 = 0x5007,
 	MLX5_REG_PPCNT		 = 0x5008,
 	MLX5_REG_PMAOS		 = 0x5012,
 	MLX5_REG_PUDE		 = 0x5009,
 	MLX5_REG_PPTB		 = 0x500B,
 	MLX5_REG_PBMC		 = 0x500C,
 	MLX5_REG_PMPE		 = 0x5010,
 	MLX5_REG_PELC		 = 0x500e,
 	MLX5_REG_PVLC		 = 0x500f,
 	MLX5_REG_PMLP		 = 0x5002,
 	MLX5_REG_NODE_DESC	 = 0x6001,
 	MLX5_REG_HOST_ENDIANNESS = 0x7004,
+	MLX5_REG_MTMP		 = 0x900a,
 	MLX5_REG_MCIA		 = 0x9014,
 	MLX5_REG_MPCNT		 = 0x9051,
 };
 
 enum dbg_rsc_type {
 	MLX5_DBG_RSC_QP,
 	MLX5_DBG_RSC_EQ,
 	MLX5_DBG_RSC_CQ,
 };
 
 enum {
 	MLX5_INTERFACE_PROTOCOL_IB  = 0,
 	MLX5_INTERFACE_PROTOCOL_ETH = 1,
 	MLX5_INTERFACE_NUMBER       = 2,
 };
 
 struct mlx5_field_desc {
 	struct dentry	       *dent;
 	int			i;
 };
 
 struct mlx5_rsc_debug {
 	struct mlx5_core_dev   *dev;
 	void		       *object;
 	enum dbg_rsc_type	type;
 	struct dentry	       *root;
 	struct mlx5_field_desc	fields[0];
 };
 
 enum mlx5_dev_event {
 	MLX5_DEV_EVENT_SYS_ERROR,
 	MLX5_DEV_EVENT_PORT_UP,
 	MLX5_DEV_EVENT_PORT_DOWN,
 	MLX5_DEV_EVENT_PORT_INITIALIZED,
 	MLX5_DEV_EVENT_LID_CHANGE,
 	MLX5_DEV_EVENT_PKEY_CHANGE,
 	MLX5_DEV_EVENT_GUID_CHANGE,
 	MLX5_DEV_EVENT_CLIENT_REREG,
 	MLX5_DEV_EVENT_VPORT_CHANGE,
 	MLX5_DEV_EVENT_ERROR_STATE_DCBX,
 	MLX5_DEV_EVENT_REMOTE_CONFIG_CHANGE,
 	MLX5_DEV_EVENT_LOCAL_OPER_CHANGE,
 	MLX5_DEV_EVENT_REMOTE_CONFIG_APPLICATION_PRIORITY_CHANGE,
 };
 
 enum mlx5_port_status {
 	MLX5_PORT_UP        = 1 << 0,
 	MLX5_PORT_DOWN      = 1 << 1,
 };
 
 enum mlx5_link_mode {
 	MLX5_1000BASE_CX_SGMII	= 0,
 	MLX5_1000BASE_KX	= 1,
 	MLX5_10GBASE_CX4	= 2,
 	MLX5_10GBASE_KX4	= 3,
 	MLX5_10GBASE_KR		= 4,
 	MLX5_20GBASE_KR2	= 5,
 	MLX5_40GBASE_CR4	= 6,
 	MLX5_40GBASE_KR4	= 7,
 	MLX5_56GBASE_R4		= 8,
 	MLX5_10GBASE_CR		= 12,
 	MLX5_10GBASE_SR		= 13,
 	MLX5_10GBASE_ER		= 14,
 	MLX5_40GBASE_SR4	= 15,
 	MLX5_40GBASE_LR4	= 16,
 	MLX5_100GBASE_CR4	= 20,
 	MLX5_100GBASE_SR4	= 21,
 	MLX5_100GBASE_KR4	= 22,
 	MLX5_100GBASE_LR4	= 23,
 	MLX5_100BASE_TX		= 24,
 	MLX5_1000BASE_T		= 25,
 	MLX5_10GBASE_T		= 26,
 	MLX5_25GBASE_CR		= 27,
 	MLX5_25GBASE_KR		= 28,
 	MLX5_25GBASE_SR		= 29,
 	MLX5_50GBASE_CR2	= 30,
 	MLX5_50GBASE_KR2	= 31,
 	MLX5_LINK_MODES_NUMBER,
 };
 
 enum {
 	MLX5_VSC_SPACE_SUPPORTED = 0x1,
 	MLX5_VSC_SPACE_OFFSET	 = 0x4,
 	MLX5_VSC_COUNTER_OFFSET	 = 0x8,
 	MLX5_VSC_SEMA_OFFSET	 = 0xC,
 	MLX5_VSC_ADDR_OFFSET	 = 0x10,
 	MLX5_VSC_DATA_OFFSET	 = 0x14,
 	MLX5_VSC_MAX_RETRIES	 = 0x1000,
 };
 
 #define MLX5_PROT_MASK(link_mode) (1 << link_mode)
 
 struct mlx5_uuar_info {
 	struct mlx5_uar	       *uars;
 	int			num_uars;
 	int			num_low_latency_uuars;
 	unsigned long	       *bitmap;
 	unsigned int	       *count;
 	struct mlx5_bf	       *bfs;
 
 	/*
 	 * protect uuar allocation data structs
 	 */
 	struct mutex		lock;
 	u32			ver;
 };
 
 struct mlx5_bf {
 	void __iomem	       *reg;
 	void __iomem	       *regreg;
 	int			buf_size;
 	struct mlx5_uar	       *uar;
 	unsigned long		offset;
 	int			need_lock;
 	/* protect blue flame buffer selection when needed
 	 */
 	spinlock_t		lock;
 
 	/* serialize 64 bit writes when done as two 32 bit accesses
 	 */
 	spinlock_t		lock32;
 	int			uuarn;
 };
 
 struct mlx5_cmd_first {
 	__be32		data[4];
 };
 
 struct cache_ent;
 struct mlx5_fw_page {
 	union {
 		struct rb_node rb_node;
 		struct list_head list;
 	};
 	struct mlx5_cmd_first first;
 	struct mlx5_core_dev *dev;
 	bus_dmamap_t dma_map;
 	bus_addr_t dma_addr;
 	void *virt_addr;
 	struct cache_ent *cache;
 	u32 numpages;
 	u16 load_done;
 #define	MLX5_LOAD_ST_NONE 0
 #define	MLX5_LOAD_ST_SUCCESS 1
 #define	MLX5_LOAD_ST_FAILURE 2
 	u16 func_id;
 };
 #define	mlx5_cmd_msg mlx5_fw_page
 
 struct mlx5_cmd_debug {
 	struct dentry	       *dbg_root;
 	struct dentry	       *dbg_in;
 	struct dentry	       *dbg_out;
 	struct dentry	       *dbg_outlen;
 	struct dentry	       *dbg_status;
 	struct dentry	       *dbg_run;
 	void		       *in_msg;
 	void		       *out_msg;
 	u8			status;
 	u16			inlen;
 	u16			outlen;
 };
 
 struct cache_ent {
 	/* protect block chain allocations
 	 */
 	spinlock_t		lock;
 	struct list_head	head;
 };
 
 struct cmd_msg_cache {
 	struct cache_ent	large;
 	struct cache_ent	med;
 
 };
 
 struct mlx5_traffic_counter {
 	u64         packets;
 	u64         octets;
 };
 
 enum mlx5_cmd_mode {
 	MLX5_CMD_MODE_POLLING,
 	MLX5_CMD_MODE_EVENTS
 };
 
 struct mlx5_cmd_stats {
 	u64		sum;
 	u64		n;
 	struct dentry  *root;
 	struct dentry  *avg;
 	struct dentry  *count;
 	/* protect command average calculations */
 	spinlock_t	lock;
 };
 
 struct mlx5_cmd {
 	struct mlx5_fw_page *cmd_page;
 	bus_dma_tag_t dma_tag;
 	struct sx dma_sx;
 	struct mtx dma_mtx;
 #define	MLX5_DMA_OWNED(dev) mtx_owned(&(dev)->cmd.dma_mtx)
 #define	MLX5_DMA_LOCK(dev) mtx_lock(&(dev)->cmd.dma_mtx)
 #define	MLX5_DMA_UNLOCK(dev) mtx_unlock(&(dev)->cmd.dma_mtx)
 	struct cv dma_cv;
 #define	MLX5_DMA_DONE(dev) cv_broadcast(&(dev)->cmd.dma_cv)
 #define	MLX5_DMA_WAIT(dev) cv_wait(&(dev)->cmd.dma_cv, &(dev)->cmd.dma_mtx)
 	void	       *cmd_buf;
 	dma_addr_t	dma;
 	u16		cmdif_rev;
 	u8		log_sz;
 	u8		log_stride;
 	int		max_reg_cmds;
 	int		events;
 	u32 __iomem    *vector;
 
 	/* protect command queue allocations
 	 */
 	spinlock_t	alloc_lock;
 
 	/* protect token allocations
 	 */
 	spinlock_t	token_lock;
 	u8		token;
 	unsigned long	bitmask;
 	char		wq_name[MLX5_CMD_WQ_MAX_NAME];
 	struct workqueue_struct *wq;
 	struct semaphore sem;
 	struct semaphore pages_sem;
 	enum mlx5_cmd_mode mode;
 	struct mlx5_cmd_work_ent * volatile ent_arr[MLX5_MAX_COMMANDS];
 	volatile enum mlx5_cmd_mode ent_mode[MLX5_MAX_COMMANDS];
 	struct mlx5_cmd_debug dbg;
 	struct cmd_msg_cache cache;
 	int checksum_disabled;
 	struct mlx5_cmd_stats stats[MLX5_CMD_OP_MAX];
 };
 
 struct mlx5_port_caps {
 	int	gid_table_len;
 	int	pkey_table_len;
 	u8	ext_port_cap;
 };
 
 struct mlx5_buf {
 	bus_dma_tag_t		dma_tag;
 	bus_dmamap_t		dma_map;
 	struct mlx5_core_dev   *dev;
 	struct {
 		void	       *buf;
 	} direct;
 	u64		       *page_list;
 	int			npages;
 	int			size;
 	u8			page_shift;
 	u8			load_done;
 };
 
 struct mlx5_frag_buf {
 	struct mlx5_buf_list	*frags;
 	int			npages;
 	int			size;
 	u8			page_shift;
 };
 
 struct mlx5_eq {
 	struct mlx5_core_dev   *dev;
 	__be32 __iomem	       *doorbell;
 	u32			cons_index;
 	struct mlx5_buf		buf;
 	int			size;
 	u8			irqn;
 	u8			eqn;
 	int			nent;
 	u64			mask;
 	struct list_head	list;
 	int			index;
 	struct mlx5_rsc_debug	*dbg;
 };
 
 struct mlx5_core_psv {
 	u32	psv_idx;
 	struct psv_layout {
 		u32	pd;
 		u16	syndrome;
 		u16	reserved;
 		u16	bg;
 		u16	app_tag;
 		u32	ref_tag;
 	} psv;
 };
 
 struct mlx5_core_sig_ctx {
 	struct mlx5_core_psv	psv_memory;
 	struct mlx5_core_psv	psv_wire;
 #if (__FreeBSD_version >= 1100000)
 	struct ib_sig_err       err_item;
 #endif
 	bool			sig_status_checked;
 	bool			sig_err_exists;
 	u32			sigerr_count;
 };
 
 enum {
 	MLX5_MKEY_MR = 1,
 	MLX5_MKEY_MW,
 	MLX5_MKEY_MR_USER,
 };
 
 struct mlx5_core_mkey {
 	u64			iova;
 	u64			size;
 	u32			key;
 	u32			pd;
 	u32			type;
 };
 
 struct mlx5_core_mr {
 	u64			iova;
 	u64			size;
 	u32			key;
 	u32			pd;
 };
 
 enum mlx5_res_type {
 	MLX5_RES_QP	= MLX5_EVENT_QUEUE_TYPE_QP,
 	MLX5_RES_RQ	= MLX5_EVENT_QUEUE_TYPE_RQ,
 	MLX5_RES_SQ	= MLX5_EVENT_QUEUE_TYPE_SQ,
 	MLX5_RES_SRQ	= 3,
 	MLX5_RES_XSRQ	= 4,
 	MLX5_RES_DCT	= 5,
 };
 
 struct mlx5_core_rsc_common {
 	enum mlx5_res_type	res;
 	atomic_t		refcount;
 	struct completion	free;
 };
 
 struct mlx5_core_srq {
 	struct mlx5_core_rsc_common	common; /* must be first */
 	u32				srqn;
 	int				max;
 	size_t				max_gs;
 	size_t				max_avail_gather;
 	int				wqe_shift;
 	void				(*event)(struct mlx5_core_srq *, int);
 	atomic_t			refcount;
 	struct completion		free;
 };
 
 struct mlx5_eq_table {
 	void __iomem	       *update_ci;
 	void __iomem	       *update_arm_ci;
 	struct list_head	comp_eqs_list;
 	struct mlx5_eq		pages_eq;
 	struct mlx5_eq		async_eq;
 	struct mlx5_eq		cmd_eq;
 	int			num_comp_vectors;
 	/* protect EQs list
 	 */
 	spinlock_t		lock;
 };
 
 struct mlx5_uar {
 	u32			index;
 	void __iomem	       *bf_map;
 	void __iomem	       *map;
 };
 
 
 struct mlx5_core_health {
 	struct mlx5_health_buffer __iomem	*health;
 	__be32 __iomem		       *health_counter;
 	struct timer_list		timer;
 	u32				prev;
 	int				miss_counter;
 	u32				fatal_error;
 	/* wq spinlock to synchronize draining */
 	spinlock_t			wq_lock;
 	struct workqueue_struct	       *wq;
 	unsigned long			flags;
 	struct work_struct		work;
 	struct delayed_work		recover_work;
 };
 
 #ifdef RATELIMIT
 #define	MLX5_CQ_LINEAR_ARRAY_SIZE	(128 * 1024)
 #else
 #define	MLX5_CQ_LINEAR_ARRAY_SIZE	1024
 #endif
 
 struct mlx5_cq_linear_array_entry {
 	spinlock_t	lock;
 	struct mlx5_core_cq * volatile cq;
 };
 
 struct mlx5_cq_table {
 	/* protect radix tree
 	 */
 	spinlock_t		lock;
 	struct radix_tree_root	tree;
 	struct mlx5_cq_linear_array_entry linear_array[MLX5_CQ_LINEAR_ARRAY_SIZE];
 };
 
 struct mlx5_qp_table {
 	/* protect radix tree
 	 */
 	spinlock_t		lock;
 	struct radix_tree_root	tree;
 };
 
 struct mlx5_srq_table {
 	/* protect radix tree
 	 */
 	spinlock_t		lock;
 	struct radix_tree_root	tree;
 };
 
 struct mlx5_mr_table {
 	/* protect radix tree
 	 */
 	spinlock_t		lock;
 	struct radix_tree_root	tree;
 };
 
 struct mlx5_irq_info {
 	char name[MLX5_MAX_IRQ_NAME];
 };
 
 #ifdef RATELIMIT
 struct mlx5_rl_entry {
 	u32			rate;
 	u16			burst;
 	u16			index;
 	u32			refcount;
 };
 
 struct mlx5_rl_table {
 	struct mutex		rl_lock;
 	u16			max_size;
 	u32			max_rate;
 	u32			min_rate;
 	struct mlx5_rl_entry   *rl_entry;
 };
 #endif
 
 struct mlx5_priv {
 	char			name[MLX5_MAX_NAME_LEN];
 	struct mlx5_eq_table	eq_table;
 	struct msix_entry	*msix_arr;
 	struct mlx5_irq_info	*irq_info;
 	struct mlx5_uuar_info	uuari;
 	MLX5_DECLARE_DOORBELL_LOCK(cq_uar_lock);
 
 	struct io_mapping	*bf_mapping;
 
 	/* pages stuff */
 	struct workqueue_struct *pg_wq;
 	struct rb_root		page_root;
 	s64			fw_pages;
 	atomic_t		reg_pages;
 	s64			pages_per_func[MLX5_MAX_NUMBER_OF_VFS];
 	struct mlx5_core_health health;
 
 	struct mlx5_srq_table	srq_table;
 
 	/* start: qp staff */
 	struct mlx5_qp_table	qp_table;
 	struct dentry	       *qp_debugfs;
 	struct dentry	       *eq_debugfs;
 	struct dentry	       *cq_debugfs;
 	struct dentry	       *cmdif_debugfs;
 	/* end: qp staff */
 
 	/* start: cq staff */
 	struct mlx5_cq_table	cq_table;
 	/* end: cq staff */
 
 	/* start: mr staff */
 	struct mlx5_mr_table	mr_table;
 	/* end: mr staff */
 
 	/* start: alloc staff */
 	int			numa_node;
 
 	struct mutex   pgdir_mutex;
 	struct list_head        pgdir_list;
 	/* end: alloc staff */
 	struct dentry	       *dbg_root;
 
 	/* protect mkey key part */
 	spinlock_t		mkey_lock;
 	u8			mkey_key;
 
 	struct list_head        dev_list;
 	struct list_head        ctx_list;
 	spinlock_t              ctx_lock;
 	unsigned long		pci_dev_data;
 #ifdef RATELIMIT
 	struct mlx5_rl_table	rl_table;
 #endif
 };
 
 enum mlx5_device_state {
 	MLX5_DEVICE_STATE_UP,
 	MLX5_DEVICE_STATE_INTERNAL_ERROR,
 };
 
 enum mlx5_interface_state {
 	MLX5_INTERFACE_STATE_DOWN = BIT(0),
 	MLX5_INTERFACE_STATE_UP = BIT(1),
 	MLX5_INTERFACE_STATE_SHUTDOWN = BIT(2),
 };
 
 enum mlx5_pci_status {
 	MLX5_PCI_STATUS_DISABLED,
 	MLX5_PCI_STATUS_ENABLED,
 };
 
 #define	MLX5_MAX_RESERVED_GIDS	8
 
 struct mlx5_rsvd_gids {
 	unsigned int start;
 	unsigned int count;
 	struct ida ida;
 };
 
 struct mlx5_special_contexts {
 	int resd_lkey;
 };
 
 struct mlx5_flow_root_namespace;
 struct mlx5_dump_data;
 struct mlx5_core_dev {
 	struct pci_dev	       *pdev;
 	/* sync pci state */
 	struct mutex		pci_status_mutex;
 	enum mlx5_pci_status	pci_status;
 	char			board_id[MLX5_BOARD_ID_LEN];
 	struct mlx5_cmd		cmd;
 	struct mlx5_port_caps	port_caps[MLX5_MAX_PORTS];
 	u32 hca_caps_cur[MLX5_CAP_NUM][MLX5_UN_SZ_DW(hca_cap_union)];
 	u32 hca_caps_max[MLX5_CAP_NUM][MLX5_UN_SZ_DW(hca_cap_union)];
 	struct {
 		u32 qcam[MLX5_ST_SZ_DW(qcam_reg)];
 		u32 fpga[MLX5_ST_SZ_DW(fpga_cap)];
 	} caps;
 	phys_addr_t		iseg_base;
 	struct mlx5_init_seg __iomem *iseg;
 	enum mlx5_device_state	state;
 	/* sync interface state */
 	struct mutex		intf_state_mutex;
 	unsigned long		intf_state;
 	void			(*event) (struct mlx5_core_dev *dev,
 					  enum mlx5_dev_event event,
 					  unsigned long param);
 	struct mlx5_priv	priv;
 	struct mlx5_profile	*profile;
 	atomic_t		num_qps;
 	u32			vsc_addr;
 	u32			issi;
 	struct mlx5_special_contexts special_contexts;
 	unsigned int module_status[MLX5_MAX_PORTS];
 	struct mlx5_flow_root_namespace *root_ns;
 	struct mlx5_flow_root_namespace *fdb_root_ns;
 	struct mlx5_flow_root_namespace *esw_egress_root_ns;
 	struct mlx5_flow_root_namespace *esw_ingress_root_ns;
 	struct mlx5_flow_root_namespace *sniffer_rx_root_ns;
 	struct mlx5_flow_root_namespace *sniffer_tx_root_ns;
 	u32 num_q_counter_allocated[MLX5_INTERFACE_NUMBER];
 	struct mlx5_dump_data	*dump_data;
 
 	struct sysctl_ctx_list	sysctl_ctx;
 	int			msix_eqvec;
 
 	struct {
 		struct mlx5_rsvd_gids	reserved_gids;
 		atomic_t		roce_en;
 	} roce;
 #ifdef CONFIG_MLX5_FPGA
 	struct mlx5_fpga_device	*fpga;
 #endif
 };
 
 enum {
 	MLX5_WOL_DISABLE       = 0,
 	MLX5_WOL_SECURED_MAGIC = 1 << 1,
 	MLX5_WOL_MAGIC         = 1 << 2,
 	MLX5_WOL_ARP           = 1 << 3,
 	MLX5_WOL_BROADCAST     = 1 << 4,
 	MLX5_WOL_MULTICAST     = 1 << 5,
 	MLX5_WOL_UNICAST       = 1 << 6,
 	MLX5_WOL_PHY_ACTIVITY  = 1 << 7,
 };
 
 struct mlx5_db {
 	__be32			*db;
 	union {
 		struct mlx5_db_pgdir		*pgdir;
 		struct mlx5_ib_user_db_page	*user_page;
 	}			u;
 	dma_addr_t		dma;
 	int			index;
 };
 
 struct mlx5_net_counters {
 	u64	packets;
 	u64	octets;
 };
 
 struct mlx5_ptys_reg {
 	u8	an_dis_admin;
 	u8	an_dis_ap;
 	u8	local_port;
 	u8	proto_mask;
 	u32	eth_proto_cap;
 	u16	ib_link_width_cap;
 	u16	ib_proto_cap;
 	u32	eth_proto_admin;
 	u16	ib_link_width_admin;
 	u16	ib_proto_admin;
 	u32	eth_proto_oper;
 	u16	ib_link_width_oper;
 	u16	ib_proto_oper;
 	u32	eth_proto_lp_advertise;
 };
 
 struct mlx5_pvlc_reg {
 	u8	local_port;
 	u8	vl_hw_cap;
 	u8	vl_admin;
 	u8	vl_operational;
 };
 
 struct mlx5_pmtu_reg {
 	u8	local_port;
 	u16	max_mtu;
 	u16	admin_mtu;
 	u16	oper_mtu;
 };
 
 struct mlx5_vport_counters {
 	struct mlx5_net_counters	received_errors;
 	struct mlx5_net_counters	transmit_errors;
 	struct mlx5_net_counters	received_ib_unicast;
 	struct mlx5_net_counters	transmitted_ib_unicast;
 	struct mlx5_net_counters	received_ib_multicast;
 	struct mlx5_net_counters	transmitted_ib_multicast;
 	struct mlx5_net_counters	received_eth_broadcast;
 	struct mlx5_net_counters	transmitted_eth_broadcast;
 	struct mlx5_net_counters	received_eth_unicast;
 	struct mlx5_net_counters	transmitted_eth_unicast;
 	struct mlx5_net_counters	received_eth_multicast;
 	struct mlx5_net_counters	transmitted_eth_multicast;
 };
 
 enum {
 	MLX5_DB_PER_PAGE = MLX5_ADAPTER_PAGE_SIZE / L1_CACHE_BYTES,
 };
 
 struct mlx5_core_dct {
 	struct mlx5_core_rsc_common	common; /* must be first */
 	void (*event)(struct mlx5_core_dct *, int);
 	int			dctn;
 	struct completion	drained;
 	struct mlx5_rsc_debug	*dbg;
 	int			pid;
 };
 
 enum {
 	MLX5_COMP_EQ_SIZE = 1024,
 };
 
 enum {
 	MLX5_PTYS_IB = 1 << 0,
 	MLX5_PTYS_EN = 1 << 2,
 };
 
 struct mlx5_db_pgdir {
 	struct list_head	list;
 	DECLARE_BITMAP(bitmap, MLX5_DB_PER_PAGE);
 	struct mlx5_fw_page    *fw_page;
 	__be32		       *db_page;
 	dma_addr_t		db_dma;
 };
 
 typedef void (*mlx5_cmd_cbk_t)(int status, void *context);
 
 struct mlx5_cmd_work_ent {
 	struct mlx5_cmd_msg    *in;
 	struct mlx5_cmd_msg    *out;
 	int			uin_size;
 	void		       *uout;
 	int			uout_size;
 	mlx5_cmd_cbk_t		callback;
         struct delayed_work     cb_timeout_work;
 	void		       *context;
 	int			idx;
 	struct completion	done;
 	struct mlx5_cmd        *cmd;
 	struct work_struct	work;
 	struct mlx5_cmd_layout *lay;
 	int			ret;
 	int			page_queue;
 	u8			status;
 	u8			token;
 	u64			ts1;
 	u64			ts2;
 	u16			op;
 	u8			busy;
 	bool			polling;
 };
 
 struct mlx5_pas {
 	u64	pa;
 	u8	log_sz;
 };
 
 enum port_state_policy {
 	MLX5_POLICY_DOWN        = 0,
 	MLX5_POLICY_UP          = 1,
 	MLX5_POLICY_FOLLOW      = 2,
 	MLX5_POLICY_INVALID     = 0xffffffff
 };
 
 static inline void *
 mlx5_buf_offset(struct mlx5_buf *buf, int offset)
 {
 	return ((char *)buf->direct.buf + offset);
 }
 
 
 extern struct workqueue_struct *mlx5_core_wq;
 
 #define STRUCT_FIELD(header, field) \
 	.struct_offset_bytes = offsetof(struct ib_unpacked_ ## header, field),      \
 	.struct_size_bytes   = sizeof((struct ib_unpacked_ ## header *)0)->field
 
 static inline struct mlx5_core_dev *pci2mlx5_core_dev(struct pci_dev *pdev)
 {
 	return pci_get_drvdata(pdev);
 }
 
 extern struct dentry *mlx5_debugfs_root;
 
 static inline u16 fw_rev_maj(struct mlx5_core_dev *dev)
 {
 	return ioread32be(&dev->iseg->fw_rev) & 0xffff;
 }
 
 static inline u16 fw_rev_min(struct mlx5_core_dev *dev)
 {
 	return ioread32be(&dev->iseg->fw_rev) >> 16;
 }
 
 static inline u16 fw_rev_sub(struct mlx5_core_dev *dev)
 {
 	return ioread32be(&dev->iseg->cmdif_rev_fw_sub) & 0xffff;
 }
 
 static inline u16 cmdif_rev_get(struct mlx5_core_dev *dev)
 {
 	return ioread32be(&dev->iseg->cmdif_rev_fw_sub) >> 16;
 }
 
 static inline int mlx5_get_gid_table_len(u16 param)
 {
 	if (param > 4) {
 		printf("M4_CORE_DRV_NAME: WARN: ""gid table length is zero\n");
 		return 0;
 	}
 
 	return 8 * (1 << param);
 }
 
 static inline void *mlx5_vzalloc(unsigned long size)
 {
 	void *rtn;
 
 	rtn = kzalloc(size, GFP_KERNEL | __GFP_NOWARN);
 	return rtn;
 }
 
 static inline void *mlx5_vmalloc(unsigned long size)
 {
 	void *rtn;
 
 	rtn = kmalloc(size, GFP_KERNEL | __GFP_NOWARN);
 	if (!rtn)
 		rtn = vmalloc(size);
 	return rtn;
 }
 
 static inline u32 mlx5_base_mkey(const u32 key)
 {
 	return key & 0xffffff00u;
 }
 
 int mlx5_cmd_init(struct mlx5_core_dev *dev);
 void mlx5_cmd_cleanup(struct mlx5_core_dev *dev);
 void mlx5_cmd_use_events(struct mlx5_core_dev *dev);
 void mlx5_cmd_use_polling(struct mlx5_core_dev *dev);
 void mlx5_cmd_mbox_status(void *out, u8 *status, u32 *syndrome);
 int mlx5_core_get_caps(struct mlx5_core_dev *dev, enum mlx5_cap_type cap_type);
 int mlx5_cmd_exec(struct mlx5_core_dev *dev, void *in, int in_size, void *out,
 		  int out_size);
 int mlx5_cmd_exec_cb(struct mlx5_core_dev *dev, void *in, int in_size,
 		     void *out, int out_size, mlx5_cmd_cbk_t callback,
 		     void *context);
 int mlx5_cmd_exec_polling(struct mlx5_core_dev *dev, void *in, int in_size,
 			  void *out, int out_size);
 int mlx5_cmd_alloc_uar(struct mlx5_core_dev *dev, u32 *uarn);
 int mlx5_cmd_free_uar(struct mlx5_core_dev *dev, u32 uarn);
 int mlx5_alloc_uuars(struct mlx5_core_dev *dev, struct mlx5_uuar_info *uuari);
 int mlx5_free_uuars(struct mlx5_core_dev *dev, struct mlx5_uuar_info *uuari);
 int mlx5_alloc_map_uar(struct mlx5_core_dev *mdev, struct mlx5_uar *uar);
 void mlx5_unmap_free_uar(struct mlx5_core_dev *mdev, struct mlx5_uar *uar);
 void mlx5_health_cleanup(struct mlx5_core_dev *dev);
 int mlx5_health_init(struct mlx5_core_dev *dev);
 void mlx5_start_health_poll(struct mlx5_core_dev *dev);
 void mlx5_stop_health_poll(struct mlx5_core_dev *dev, bool disable_health);
 void mlx5_drain_health_wq(struct mlx5_core_dev *dev);
 void mlx5_drain_health_recovery(struct mlx5_core_dev *dev);
 void mlx5_trigger_health_work(struct mlx5_core_dev *dev);
 
 #define	mlx5_buf_alloc_node(dev, size, direct, buf, node) \
 	mlx5_buf_alloc(dev, size, direct, buf)
 int mlx5_buf_alloc(struct mlx5_core_dev *dev, int size, int max_direct,
 		   struct mlx5_buf *buf);
 void mlx5_buf_free(struct mlx5_core_dev *dev, struct mlx5_buf *buf);
 int mlx5_core_create_srq(struct mlx5_core_dev *dev, struct mlx5_core_srq *srq,
 			 struct mlx5_srq_attr *in);
 int mlx5_core_destroy_srq(struct mlx5_core_dev *dev, struct mlx5_core_srq *srq);
 int mlx5_core_query_srq(struct mlx5_core_dev *dev, struct mlx5_core_srq *srq,
 			struct mlx5_srq_attr *out);
 int mlx5_core_query_vendor_id(struct mlx5_core_dev *mdev, u32 *vendor_id);
 int mlx5_core_arm_srq(struct mlx5_core_dev *dev, struct mlx5_core_srq *srq,
 		      u16 lwm, int is_srq);
 void mlx5_init_mr_table(struct mlx5_core_dev *dev);
 void mlx5_cleanup_mr_table(struct mlx5_core_dev *dev);
 int mlx5_core_create_mkey_cb(struct mlx5_core_dev *dev,
 			     struct mlx5_core_mr *mkey,
 			     u32 *in, int inlen,
 			     u32 *out, int outlen,
 			     mlx5_cmd_cbk_t callback, void *context);
 int mlx5_core_create_mkey(struct mlx5_core_dev *dev,
 			  struct mlx5_core_mr *mr,
 			  u32 *in, int inlen);
 int mlx5_core_destroy_mkey(struct mlx5_core_dev *dev, struct mlx5_core_mr *mkey);
 int mlx5_core_query_mkey(struct mlx5_core_dev *dev, struct mlx5_core_mr *mkey,
 			 u32 *out, int outlen);
 int mlx5_core_dump_fill_mkey(struct mlx5_core_dev *dev, struct mlx5_core_mr *mr,
 			     u32 *mkey);
 int mlx5_core_alloc_pd(struct mlx5_core_dev *dev, u32 *pdn);
 int mlx5_core_dealloc_pd(struct mlx5_core_dev *dev, u32 pdn);
 int mlx5_core_mad_ifc(struct mlx5_core_dev *dev, const void *inb, void *outb,
 		      u16 opmod, u8 port);
 void mlx5_fwp_flush(struct mlx5_fw_page *fwp);
 void mlx5_fwp_invalidate(struct mlx5_fw_page *fwp);
 struct mlx5_fw_page *mlx5_fwp_alloc(struct mlx5_core_dev *dev, gfp_t flags, unsigned num);
 void mlx5_fwp_free(struct mlx5_fw_page *fwp);
 u64 mlx5_fwp_get_dma(struct mlx5_fw_page *fwp, size_t offset);
 void *mlx5_fwp_get_virt(struct mlx5_fw_page *fwp, size_t offset);
 void mlx5_pagealloc_init(struct mlx5_core_dev *dev);
 void mlx5_pagealloc_cleanup(struct mlx5_core_dev *dev);
 int mlx5_pagealloc_start(struct mlx5_core_dev *dev);
 void mlx5_pagealloc_stop(struct mlx5_core_dev *dev);
 void mlx5_core_req_pages_handler(struct mlx5_core_dev *dev, u16 func_id,
 				 s32 npages);
 int mlx5_satisfy_startup_pages(struct mlx5_core_dev *dev, int boot);
 int mlx5_reclaim_startup_pages(struct mlx5_core_dev *dev);
 s64 mlx5_wait_for_reclaim_vfs_pages(struct mlx5_core_dev *dev);
 void mlx5_register_debugfs(void);
 void mlx5_unregister_debugfs(void);
 int mlx5_eq_init(struct mlx5_core_dev *dev);
 void mlx5_eq_cleanup(struct mlx5_core_dev *dev);
 void mlx5_fill_page_array(struct mlx5_buf *buf, __be64 *pas);
 void mlx5_cq_completion(struct mlx5_core_dev *dev, u32 cqn);
 void mlx5_rsc_event(struct mlx5_core_dev *dev, u32 rsn, int event_type);
 void mlx5_srq_event(struct mlx5_core_dev *dev, u32 srqn, int event_type);
 struct mlx5_core_srq *mlx5_core_get_srq(struct mlx5_core_dev *dev, u32 srqn);
 void mlx5_cmd_comp_handler(struct mlx5_core_dev *dev, u64 vector, enum mlx5_cmd_mode mode);
 void mlx5_cq_event(struct mlx5_core_dev *dev, u32 cqn, int event_type);
 int mlx5_create_map_eq(struct mlx5_core_dev *dev, struct mlx5_eq *eq, u8 vecidx,
 		       int nent, u64 mask, const char *name, struct mlx5_uar *uar);
 int mlx5_destroy_unmap_eq(struct mlx5_core_dev *dev, struct mlx5_eq *eq);
 int mlx5_start_eqs(struct mlx5_core_dev *dev);
 int mlx5_stop_eqs(struct mlx5_core_dev *dev);
 int mlx5_vector2eqn(struct mlx5_core_dev *dev, int vector, int *eqn, int *irqn);
 int mlx5_core_attach_mcg(struct mlx5_core_dev *dev, union ib_gid *mgid, u32 qpn);
 int mlx5_core_detach_mcg(struct mlx5_core_dev *dev, union ib_gid *mgid, u32 qpn);
 int mlx5_core_set_dc_cnak_trace(struct mlx5_core_dev *dev, int enable,
 				u64 addr);
 
 int mlx5_qp_debugfs_init(struct mlx5_core_dev *dev);
 void mlx5_qp_debugfs_cleanup(struct mlx5_core_dev *dev);
 int mlx5_core_access_reg(struct mlx5_core_dev *dev, void *data_in,
 			 int size_in, void *data_out, int size_out,
 			 u16 reg_num, int arg, int write);
 
 void mlx5_toggle_port_link(struct mlx5_core_dev *dev);
 
 int mlx5_debug_eq_add(struct mlx5_core_dev *dev, struct mlx5_eq *eq);
 void mlx5_debug_eq_remove(struct mlx5_core_dev *dev, struct mlx5_eq *eq);
 int mlx5_core_eq_query(struct mlx5_core_dev *dev, struct mlx5_eq *eq,
 		       u32 *out, int outlen);
 int mlx5_eq_debugfs_init(struct mlx5_core_dev *dev);
 void mlx5_eq_debugfs_cleanup(struct mlx5_core_dev *dev);
 int mlx5_cq_debugfs_init(struct mlx5_core_dev *dev);
 void mlx5_cq_debugfs_cleanup(struct mlx5_core_dev *dev);
 int mlx5_db_alloc(struct mlx5_core_dev *dev, struct mlx5_db *db);
 int mlx5_db_alloc_node(struct mlx5_core_dev *dev, struct mlx5_db *db,
 		       int node);
 void mlx5_db_free(struct mlx5_core_dev *dev, struct mlx5_db *db);
 
 const char *mlx5_command_str(int command);
 int mlx5_cmdif_debugfs_init(struct mlx5_core_dev *dev);
 void mlx5_cmdif_debugfs_cleanup(struct mlx5_core_dev *dev);
 int mlx5_core_create_psv(struct mlx5_core_dev *dev, u32 pdn,
 			 int npsvs, u32 *sig_index);
 int mlx5_core_destroy_psv(struct mlx5_core_dev *dev, int psv_num);
 void mlx5_core_put_rsc(struct mlx5_core_rsc_common *common);
 u8 mlx5_is_wol_supported(struct mlx5_core_dev *dev);
 int mlx5_set_wol(struct mlx5_core_dev *dev, u8 wol_mode);
 int mlx5_set_dropless_mode(struct mlx5_core_dev *dev, u16 timeout);
 int mlx5_query_dropless_mode(struct mlx5_core_dev *dev, u16 *timeout);
 int mlx5_query_wol(struct mlx5_core_dev *dev, u8 *wol_mode);
 int mlx5_core_access_pvlc(struct mlx5_core_dev *dev,
 			  struct mlx5_pvlc_reg *pvlc, int write);
 int mlx5_core_access_ptys(struct mlx5_core_dev *dev,
 			  struct mlx5_ptys_reg *ptys, int write);
 int mlx5_core_access_pmtu(struct mlx5_core_dev *dev,
 			  struct mlx5_pmtu_reg *pmtu, int write);
 int mlx5_vxlan_udp_port_add(struct mlx5_core_dev *dev, u16 port);
 int mlx5_vxlan_udp_port_delete(struct mlx5_core_dev *dev, u16 port);
 int mlx5_query_port_cong_status(struct mlx5_core_dev *mdev, int protocol,
 				int priority, int *is_enable);
 int mlx5_modify_port_cong_status(struct mlx5_core_dev *mdev, int protocol,
 				 int priority, int enable);
 int mlx5_query_port_cong_params(struct mlx5_core_dev *mdev, int protocol,
 				void *out, int out_size);
 int mlx5_modify_port_cong_params(struct mlx5_core_dev *mdev,
 				 void *in, int in_size);
 int mlx5_query_port_cong_statistics(struct mlx5_core_dev *mdev, int clear,
 				    void *out, int out_size);
 int mlx5_set_diagnostic_params(struct mlx5_core_dev *mdev, void *in,
 			       int in_size);
 int mlx5_query_diagnostic_counters(struct mlx5_core_dev *mdev,
 				   u8 num_of_samples, u16 sample_index,
 				   void *out, int out_size);
 int mlx5_vsc_find_cap(struct mlx5_core_dev *mdev);
 int mlx5_vsc_lock(struct mlx5_core_dev *mdev);
 void mlx5_vsc_unlock(struct mlx5_core_dev *mdev);
 int mlx5_vsc_set_space(struct mlx5_core_dev *mdev, u16 space);
 int mlx5_vsc_write(struct mlx5_core_dev *mdev, u32 addr, const u32 *data);
 int mlx5_vsc_read(struct mlx5_core_dev *mdev, u32 addr, u32 *data);
 int mlx5_vsc_lock_addr_space(struct mlx5_core_dev *mdev, u32 addr);
 int mlx5_vsc_unlock_addr_space(struct mlx5_core_dev *mdev, u32 addr);
 
 static inline u32 mlx5_mkey_to_idx(u32 mkey)
 {
 	return mkey >> 8;
 }
 
 static inline u32 mlx5_idx_to_mkey(u32 mkey_idx)
 {
 	return mkey_idx << 8;
 }
 
 static inline u8 mlx5_mkey_variant(u32 mkey)
 {
 	return mkey & 0xff;
 }
 
 enum {
 	MLX5_PROF_MASK_QP_SIZE		= (u64)1 << 0,
 	MLX5_PROF_MASK_MR_CACHE		= (u64)1 << 1,
 };
 
 enum {
 	MAX_MR_CACHE_ENTRIES    = 15,
 };
 
 struct mlx5_interface {
 	void *			(*add)(struct mlx5_core_dev *dev);
 	void			(*remove)(struct mlx5_core_dev *dev, void *context);
 	void			(*event)(struct mlx5_core_dev *dev, void *context,
 					 enum mlx5_dev_event event, unsigned long param);
 	void *                  (*get_dev)(void *context);
 	int			protocol;
 	struct list_head	list;
 };
 
 void *mlx5_get_protocol_dev(struct mlx5_core_dev *mdev, int protocol);
 int mlx5_register_interface(struct mlx5_interface *intf);
 void mlx5_unregister_interface(struct mlx5_interface *intf);
 
 unsigned int mlx5_core_reserved_gids_count(struct mlx5_core_dev *dev);
 int mlx5_core_roce_gid_set(struct mlx5_core_dev *dev, unsigned int index,
     u8 roce_version, u8 roce_l3_type, const u8 *gid,
     const u8 *mac, bool vlan, u16 vlan_id);
 
 struct mlx5_profile {
 	u64	mask;
 	u8	log_max_qp;
 	struct {
 		int	size;
 		int	limit;
 	} mr_cache[MAX_MR_CACHE_ENTRIES];
 };
 
 enum {
 	MLX5_PCI_DEV_IS_VF		= 1 << 0,
 };
 
 enum {
 	MLX5_TRIGGERED_CMD_COMP = (u64)1 << 32,
 };
 
 static inline int mlx5_core_is_pf(struct mlx5_core_dev *dev)
 {
 	return !(dev->priv.pci_dev_data & MLX5_PCI_DEV_IS_VF);
 }
 #ifdef RATELIMIT
 int mlx5_init_rl_table(struct mlx5_core_dev *dev);
 void mlx5_cleanup_rl_table(struct mlx5_core_dev *dev);
 int mlx5_rl_add_rate(struct mlx5_core_dev *dev, u32 rate, u32 burst, u16 *index);
 void mlx5_rl_remove_rate(struct mlx5_core_dev *dev, u32 rate, u32 burst);
 bool mlx5_rl_is_in_range(const struct mlx5_core_dev *dev, u32 rate, u32 burst);
 
 static inline bool mlx5_rl_is_supported(struct mlx5_core_dev *dev)
 {
 	return !!(dev->priv.rl_table.max_size);
 }
 #endif
 
 #endif /* MLX5_DRIVER_H */
Index: head/sys/dev/mlx5/mlx5_fpga/cmd.h
===================================================================
--- head/sys/dev/mlx5/mlx5_fpga/cmd.h	(revision 341574)
+++ head/sys/dev/mlx5/mlx5_fpga/cmd.h	(revision 341575)
@@ -1,82 +1,84 @@
 /*-
  * Copyright (c) 2017, Mellanox Technologies, Ltd.  All rights reserved.
  *
  * This software is available to you under a choice of one of two
  * licenses.  You may choose to be licensed under the terms of the GNU
  * General Public License (GPL) Version 2, available from the file
  * COPYING in the main directory of this source tree, or the
  * OpenIB.org BSD license below:
  *
  *     Redistribution and use in source and binary forms, with or
  *     without modification, are permitted provided that the following
  *     conditions are met:
  *
  *      - Redistributions of source code must retain the above
  *        copyright notice, this list of conditions and the following
  *        disclaimer.
  *
  *      - Redistributions in binary form must reproduce the above
  *        copyright notice, this list of conditions and the following
  *        disclaimer in the documentation and/or other materials
  *        provided with the distribution.
  *
  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  * SOFTWARE.
  *
  * $FreeBSD$
  */
 
 #ifndef __MLX5_FPGA_H__
 #define __MLX5_FPGA_H__
 
 #include <linux/in6.h>
 #include <dev/mlx5/driver.h>
 #include <dev/mlx5/mlx5io.h>
 
 enum mlx5_fpga_qpc_field_select {
 	MLX5_FPGA_QPC_STATE = BIT(0),
 };
 
 struct mlx5_fpga_qp_counters {
 	u64 rx_ack_packets;
 	u64 rx_send_packets;
 	u64 tx_ack_packets;
 	u64 tx_send_packets;
 	u64 rx_total_drop;
 };
 
 struct mlx5_fpga_shell_counters {
 	u64 ddr_read_requests;
 	u64 ddr_write_requests;
 	u64 ddr_read_bytes;
 	u64 ddr_write_bytes;
 };
 
 int mlx5_fpga_caps(struct mlx5_core_dev *dev);
 int mlx5_fpga_query(struct mlx5_core_dev *dev, struct mlx5_fpga_query *query);
+int mlx5_fpga_query_mtmp(struct mlx5_core_dev *dev,
+			 struct mlx5_fpga_temperature *temp);
 int mlx5_fpga_ctrl_op(struct mlx5_core_dev *dev, u8 op);
 int mlx5_fpga_access_reg(struct mlx5_core_dev *dev, u8 size, u64 addr,
 			 void *buf, bool write);
 int mlx5_fpga_sbu_caps(struct mlx5_core_dev *dev, void *caps, int size);
 int mlx5_fpga_load(struct mlx5_core_dev *dev, enum mlx5_fpga_image image);
 int mlx5_fpga_image_select(struct mlx5_core_dev *dev,
 			   enum mlx5_fpga_image image);
 int mlx5_fpga_shell_counters(struct mlx5_core_dev *dev, bool clear,
 			     struct mlx5_fpga_shell_counters *data);
 
 int mlx5_fpga_create_qp(struct mlx5_core_dev *dev, void *fpga_qpc,
 			u32 *fpga_qpn);
 int mlx5_fpga_modify_qp(struct mlx5_core_dev *dev, u32 fpga_qpn,
 			enum mlx5_fpga_qpc_field_select fields, void *fpga_qpc);
 int mlx5_fpga_query_qp(struct mlx5_core_dev *dev, u32 fpga_qpn, void *fpga_qpc);
 int mlx5_fpga_query_qp_counters(struct mlx5_core_dev *dev, u32 fpga_qpn,
 				bool clear, struct mlx5_fpga_qp_counters *data);
 int mlx5_fpga_destroy_qp(struct mlx5_core_dev *dev, u32 fpga_qpn);
 
 #endif /* __MLX5_FPGA_H__ */
Index: head/sys/dev/mlx5/mlx5_fpga/mlx5fpga_cmd.c
===================================================================
--- head/sys/dev/mlx5/mlx5_fpga/mlx5fpga_cmd.c	(revision 341574)
+++ head/sys/dev/mlx5/mlx5_fpga/mlx5fpga_cmd.c	(revision 341575)
@@ -1,289 +1,321 @@
 /*-
  * Copyright (c) 2017, Mellanox Technologies. All rights reserved.
  *
  * This software is available to you under a choice of one of two
  * licenses.  You may choose to be licensed under the terms of the GNU
  * General Public License (GPL) Version 2, available from the file
  * COPYING in the main directory of this source tree, or the
  * OpenIB.org BSD license below:
  *
  *     Redistribution and use in source and binary forms, with or
  *     without modification, are permitted provided that the following
  *     conditions are met:
  *
  *      - Redistributions of source code must retain the above
  *        copyright notice, this list of conditions and the following
  *        disclaimer.
  *
  *      - Redistributions in binary form must reproduce the above
  *        copyright notice, this list of conditions and the following
  *        disclaimer in the documentation and/or other materials
  *        provided with the distribution.
  *
  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  * SOFTWARE.
  *
  * $FreeBSD$
  */
 
 #include <dev/mlx5/cmd.h>
 #include <dev/mlx5/driver.h>
 #include <dev/mlx5/device.h>
 #include <dev/mlx5/mlx5_core/mlx5_core.h>
 #include <dev/mlx5/mlx5_fpga/cmd.h>
 
 #define MLX5_FPGA_ACCESS_REG_SZ (MLX5_ST_SZ_DW(fpga_access_reg) + \
 				 MLX5_FPGA_ACCESS_REG_SIZE_MAX)
 
 int mlx5_fpga_access_reg(struct mlx5_core_dev *dev, u8 size, u64 addr,
 			 void *buf, bool write)
 {
 	u32 in[MLX5_FPGA_ACCESS_REG_SZ] = {0};
 	u32 out[MLX5_FPGA_ACCESS_REG_SZ];
 	int err;
 
 	if (size & 3)
 		return -EINVAL;
 	if (addr & 3)
 		return -EINVAL;
 	if (size > MLX5_FPGA_ACCESS_REG_SIZE_MAX)
 		return -EINVAL;
 
 	MLX5_SET(fpga_access_reg, in, size, size);
 	MLX5_SET64(fpga_access_reg, in, address, addr);
 	if (write)
 		memcpy(MLX5_ADDR_OF(fpga_access_reg, in, data), buf, size);
 
 	err = mlx5_core_access_reg(dev, in, sizeof(in), out, sizeof(out),
 				   MLX5_REG_FPGA_ACCESS_REG, 0, write);
 	if (err)
 		return err;
 
 	if (!write)
 		memcpy(buf, MLX5_ADDR_OF(fpga_access_reg, out, data), size);
 
 	return 0;
 }
 
 int mlx5_fpga_caps(struct mlx5_core_dev *dev)
 {
 	u32 in[MLX5_ST_SZ_DW(fpga_cap)] = {0};
 
 	return mlx5_core_access_reg(dev, in, sizeof(in), dev->caps.fpga,
 				    MLX5_ST_SZ_BYTES(fpga_cap),
 				    MLX5_REG_FPGA_CAP, 0, 0);
 }
 
 int mlx5_fpga_ctrl_op(struct mlx5_core_dev *dev, u8 op)
 {
 	u32 in[MLX5_ST_SZ_DW(fpga_ctrl)] = {0};
 	u32 out[MLX5_ST_SZ_DW(fpga_ctrl)];
 
 	MLX5_SET(fpga_ctrl, in, operation, op);
 
 	return mlx5_core_access_reg(dev, in, sizeof(in), out, sizeof(out),
 				    MLX5_REG_FPGA_CTRL, 0, true);
 }
 
 int mlx5_fpga_sbu_caps(struct mlx5_core_dev *dev, void *caps, int size)
 {
 	unsigned int cap_size = MLX5_CAP_FPGA(dev, sandbox_extended_caps_len);
 	u64 addr = MLX5_CAP64_FPGA(dev, sandbox_extended_caps_addr);
 	unsigned int read;
 	int ret = 0;
 
 	if (cap_size > size) {
 		mlx5_core_warn(dev, "Not enough buffer %u for FPGA SBU caps %u",
 			       size, cap_size);
 		return -EINVAL;
 	}
 
 	while (cap_size > 0) {
 		read = min_t(unsigned int, cap_size,
 			     MLX5_FPGA_ACCESS_REG_SIZE_MAX);
 
 		ret = mlx5_fpga_access_reg(dev, read, addr, caps, false);
 		if (ret) {
 			mlx5_core_warn(dev, "Error reading FPGA SBU caps %u bytes at address %#jx: %d",
 				       read, (uintmax_t)addr, ret);
 			return ret;
 		}
 
 		cap_size -= read;
 		addr += read;
 		caps += read;
 	}
 
 	return ret;
 }
 
 static int mlx5_fpga_ctrl_write(struct mlx5_core_dev *dev, u8 op,
 				enum mlx5_fpga_image image)
 {
 	u32 in[MLX5_ST_SZ_DW(fpga_ctrl)] = {0};
 	u32 out[MLX5_ST_SZ_DW(fpga_ctrl)];
 
 	MLX5_SET(fpga_ctrl, in, operation, op);
 	MLX5_SET(fpga_ctrl, in, flash_select_admin, image);
 
 	return mlx5_core_access_reg(dev, in, sizeof(in), out, sizeof(out),
 				    MLX5_REG_FPGA_CTRL, 0, true);
 }
 
 int mlx5_fpga_load(struct mlx5_core_dev *dev, enum mlx5_fpga_image image)
 {
 	return mlx5_fpga_ctrl_write(dev, MLX5_FPGA_CTRL_OPERATION_LOAD, image);
 }
 
 int mlx5_fpga_image_select(struct mlx5_core_dev *dev,
 			   enum mlx5_fpga_image image)
 {
 	return mlx5_fpga_ctrl_write(dev, MLX5_FPGA_CTRL_OPERATION_FLASH_SELECT, image);
 }
 
 int mlx5_fpga_query(struct mlx5_core_dev *dev, struct mlx5_fpga_query *query)
 {
 	u32 in[MLX5_ST_SZ_DW(fpga_ctrl)] = {0};
 	u32 out[MLX5_ST_SZ_DW(fpga_ctrl)];
 	int err;
 
 	err = mlx5_core_access_reg(dev, in, sizeof(in), out, sizeof(out),
 				   MLX5_REG_FPGA_CTRL, 0, false);
 	if (err)
 		return err;
 
 	query->image_status = MLX5_GET(fpga_ctrl, out, status);
 	query->admin_image = MLX5_GET(fpga_ctrl, out, flash_select_admin);
 	query->oper_image = MLX5_GET(fpga_ctrl, out, flash_select_oper);
 	return 0;
 }
 
+int mlx5_fpga_query_mtmp(struct mlx5_core_dev *dev,
+			 struct mlx5_fpga_temperature *temp)
+{
+	u32 in[MLX5_ST_SZ_DW(mtmp_reg)] = {0};
+	u32 out[MLX5_ST_SZ_DW(mtmp_reg)] = {0};
+	int err;
+
+	MLX5_SET(mtmp_reg, in, sensor_index, temp->index);
+	MLX5_SET(mtmp_reg, in, i,
+		 ((temp->index < MLX5_FPGA_INTERNAL_SENSORS_LOW) ||
+		 (temp->index > MLX5_FPGA_INTERNAL_SENSORS_HIGH)) ? 1 : 0);
+
+	err = mlx5_core_access_reg(dev, in, sizeof(in), out, sizeof(out),
+				   MLX5_REG_MTMP, 0, false);
+	if (err)
+		return err;
+
+	temp->index = MLX5_GET(mtmp_reg, out, sensor_index);
+	temp->temperature = MLX5_GET(mtmp_reg, out, temperature);
+	temp->mte = MLX5_GET(mtmp_reg, out, mte);
+	temp->max_temperature = MLX5_GET(mtmp_reg, out, max_temperature);
+	temp->tee = MLX5_GET(mtmp_reg, out, tee);
+	temp->temperature_threshold_hi = MLX5_GET(mtmp_reg, out,
+		temperature_threshold_hi);
+	temp->temperature_threshold_lo = MLX5_GET(mtmp_reg, out,
+		temperature_threshold_lo);
+	memcpy(temp->sensor_name, MLX5_ADDR_OF(mtmp_reg, out, sensor_name),
+	       MLX5_FLD_SZ_BYTES(mtmp_reg, sensor_name));
+
+	return 0;
+}
+
 int mlx5_fpga_create_qp(struct mlx5_core_dev *dev, void *fpga_qpc,
 			u32 *fpga_qpn)
 {
 	u32 in[MLX5_ST_SZ_DW(fpga_create_qp_in)] = {0};
 	u32 out[MLX5_ST_SZ_DW(fpga_create_qp_out)];
 	int ret;
 
 	MLX5_SET(fpga_create_qp_in, in, opcode, MLX5_CMD_OP_FPGA_CREATE_QP);
 	memcpy(MLX5_ADDR_OF(fpga_create_qp_in, in, fpga_qpc), fpga_qpc,
 	       MLX5_FLD_SZ_BYTES(fpga_create_qp_in, fpga_qpc));
 
 	ret = mlx5_cmd_exec(dev, in, sizeof(in), out, sizeof(out));
 	if (ret)
 		return ret;
 
 	memcpy(fpga_qpc, MLX5_ADDR_OF(fpga_create_qp_out, out, fpga_qpc),
 	       MLX5_FLD_SZ_BYTES(fpga_create_qp_out, fpga_qpc));
 	*fpga_qpn = MLX5_GET(fpga_create_qp_out, out, fpga_qpn);
 	return ret;
 }
 
 int mlx5_fpga_modify_qp(struct mlx5_core_dev *dev, u32 fpga_qpn,
 			enum mlx5_fpga_qpc_field_select fields,
 			void *fpga_qpc)
 {
 	u32 in[MLX5_ST_SZ_DW(fpga_modify_qp_in)] = {0};
 	u32 out[MLX5_ST_SZ_DW(fpga_modify_qp_out)];
 
 	MLX5_SET(fpga_modify_qp_in, in, opcode, MLX5_CMD_OP_FPGA_MODIFY_QP);
 	MLX5_SET(fpga_modify_qp_in, in, field_select, fields);
 	MLX5_SET(fpga_modify_qp_in, in, fpga_qpn, fpga_qpn);
 	memcpy(MLX5_ADDR_OF(fpga_modify_qp_in, in, fpga_qpc), fpga_qpc,
 	       MLX5_FLD_SZ_BYTES(fpga_modify_qp_in, fpga_qpc));
 
 	return mlx5_cmd_exec(dev, in, sizeof(in), out, sizeof(out));
 }
 
 int mlx5_fpga_query_qp(struct mlx5_core_dev *dev,
 		       u32 fpga_qpn, void *fpga_qpc)
 {
 	u32 in[MLX5_ST_SZ_DW(fpga_query_qp_in)] = {0};
 	u32 out[MLX5_ST_SZ_DW(fpga_query_qp_out)];
 	int ret;
 
 	MLX5_SET(fpga_query_qp_in, in, opcode, MLX5_CMD_OP_FPGA_QUERY_QP);
 	MLX5_SET(fpga_query_qp_in, in, fpga_qpn, fpga_qpn);
 
 	ret = mlx5_cmd_exec(dev, in, sizeof(in), out, sizeof(out));
 	if (ret)
 		return ret;
 
 	memcpy(fpga_qpc, MLX5_ADDR_OF(fpga_query_qp_out, out, fpga_qpc),
 	       MLX5_FLD_SZ_BYTES(fpga_query_qp_out, fpga_qpc));
 	return ret;
 }
 
 int mlx5_fpga_destroy_qp(struct mlx5_core_dev *dev, u32 fpga_qpn)
 {
 	u32 in[MLX5_ST_SZ_DW(fpga_destroy_qp_in)] = {0};
 	u32 out[MLX5_ST_SZ_DW(fpga_destroy_qp_out)];
 
 	MLX5_SET(fpga_destroy_qp_in, in, opcode, MLX5_CMD_OP_FPGA_DESTROY_QP);
 	MLX5_SET(fpga_destroy_qp_in, in, fpga_qpn, fpga_qpn);
 
 	return mlx5_cmd_exec(dev, in, sizeof(in), out, sizeof(out));
 }
 
 int mlx5_fpga_query_qp_counters(struct mlx5_core_dev *dev, u32 fpga_qpn,
 				bool clear, struct mlx5_fpga_qp_counters *data)
 {
 	u32 in[MLX5_ST_SZ_DW(fpga_query_qp_counters_in)] = {0};
 	u32 out[MLX5_ST_SZ_DW(fpga_query_qp_counters_out)];
 	int ret;
 
 	MLX5_SET(fpga_query_qp_counters_in, in, opcode,
 		 MLX5_CMD_OP_FPGA_QUERY_QP_COUNTERS);
 	MLX5_SET(fpga_query_qp_counters_in, in, clear, clear);
 	MLX5_SET(fpga_query_qp_counters_in, in, fpga_qpn, fpga_qpn);
 
 	ret = mlx5_cmd_exec(dev, in, sizeof(in), out, sizeof(out));
 	if (ret)
 		return ret;
 
 	data->rx_ack_packets = MLX5_GET64(fpga_query_qp_counters_out, out,
 					  rx_ack_packets);
 	data->rx_send_packets = MLX5_GET64(fpga_query_qp_counters_out, out,
 					   rx_send_packets);
 	data->tx_ack_packets = MLX5_GET64(fpga_query_qp_counters_out, out,
 					  tx_ack_packets);
 	data->tx_send_packets = MLX5_GET64(fpga_query_qp_counters_out, out,
 					   tx_send_packets);
 	data->rx_total_drop = MLX5_GET64(fpga_query_qp_counters_out, out,
 					 rx_total_drop);
 
 	return ret;
 }
 
 int mlx5_fpga_shell_counters(struct mlx5_core_dev *dev, bool clear,
 			     struct mlx5_fpga_shell_counters *data)
 {
 	u32 in[MLX5_ST_SZ_DW(fpga_shell_counters)] = {0};
 	u32 out[MLX5_ST_SZ_DW(fpga_shell_counters)];
 	int err;
 
 	MLX5_SET(fpga_shell_counters, in, clear, clear);
 	err = mlx5_core_access_reg(dev, in, sizeof(in), out, sizeof(out),
 				   MLX5_REG_FPGA_SHELL_CNTR, 0, false);
 	if (err)
 		goto out;
 	if (data) {
 		data->ddr_read_requests = MLX5_GET64(fpga_shell_counters, out,
 						     ddr_read_requests);
 		data->ddr_write_requests = MLX5_GET64(fpga_shell_counters, out,
 						      ddr_write_requests);
 		data->ddr_read_bytes = MLX5_GET64(fpga_shell_counters, out,
 						  ddr_read_bytes);
 		data->ddr_write_bytes = MLX5_GET64(fpga_shell_counters, out,
 						   ddr_write_bytes);
 	}
 
 out:
 	return err;
 }
Index: head/sys/dev/mlx5/mlx5_fpga/mlx5fpga_sdk.c
===================================================================
--- head/sys/dev/mlx5/mlx5_fpga/mlx5fpga_sdk.c	(revision 341574)
+++ head/sys/dev/mlx5/mlx5_fpga/mlx5fpga_sdk.c	(revision 341575)
@@ -1,459 +1,466 @@
 /*-
  * Copyright (c) 2017 Mellanox Technologies. All rights reserved.
  *
  * This software is available to you under a choice of one of two
  * licenses.  You may choose to be licensed under the terms of the GNU
  * General Public License (GPL) Version 2, available from the file
  * COPYING in the main directory of this source tree, or the
  * OpenIB.org BSD license below:
  *
  *     Redistribution and use in source and binary forms, with or
  *     without modification, are permitted provided that the following
  *     conditions are met:
  *
  *      - Redistributions of source code must retain the above
  *        copyright notice, this list of conditions and the following
  *        disclaimer.
  *
  *      - Redistributions in binary form must reproduce the above
  *        copyright notice, this list of conditions and the following
  *        disclaimer in the documentation and/or other materials
  *        provided with the distribution.
  *
  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  * SOFTWARE.
  *
  * $FreeBSD$
  */
 
 #include <linux/errno.h>
 #include <linux/err.h>
 #include <linux/completion.h>
 #include <dev/mlx5/device.h>
 #include <dev/mlx5/mlx5_fpga/core.h>
 #include <dev/mlx5/mlx5_fpga/conn.h>
 #include <dev/mlx5/mlx5_fpga/sdk.h>
 #include <dev/mlx5/mlx5_fpga/xfer.h>
 #include <dev/mlx5/mlx5_core/mlx5_core.h>
 /* #include "accel/ipsec.h" */
 
 #define MLX5_FPGA_LOAD_TIMEOUT 25000 /* msec */
 
 struct mem_transfer {
 	struct mlx5_fpga_transaction t;
 	struct completion comp;
 	u8 status;
 };
 
 struct mlx5_fpga_conn *
 mlx5_fpga_sbu_conn_create(struct mlx5_fpga_device *fdev,
 			  struct mlx5_fpga_conn_attr *attr)
 {
 #ifdef NOT_YET
 	/* XXXKIB */
 	return mlx5_fpga_conn_create(fdev, attr, MLX5_FPGA_QPC_QP_TYPE_SANDBOX_QP);
 #else
 	return (NULL);
 #endif
 }
 EXPORT_SYMBOL(mlx5_fpga_sbu_conn_create);
 
 void mlx5_fpga_sbu_conn_destroy(struct mlx5_fpga_conn *conn)
 {
 #ifdef NOT_YET
 	/* XXXKIB */
 	mlx5_fpga_conn_destroy(conn);
 #endif
 }
 EXPORT_SYMBOL(mlx5_fpga_sbu_conn_destroy);
 
 int mlx5_fpga_sbu_conn_sendmsg(struct mlx5_fpga_conn *conn,
 			       struct mlx5_fpga_dma_buf *buf)
 {
 #ifdef NOT_YET
 	/* XXXKIB */
 	return mlx5_fpga_conn_send(conn, buf);
 #else
 	return (0);
 #endif
 }
 EXPORT_SYMBOL(mlx5_fpga_sbu_conn_sendmsg);
 
 static void mem_complete(const struct mlx5_fpga_transaction *complete,
 			 u8 status)
 {
 	struct mem_transfer *xfer;
 
 	mlx5_fpga_dbg(complete->conn->fdev,
 		      "transaction %p complete status %u", complete, status);
 
 	xfer = container_of(complete, struct mem_transfer, t);
 	xfer->status = status;
 	complete_all(&xfer->comp);
 }
 
 static int mem_transaction(struct mlx5_fpga_device *fdev, size_t size, u64 addr,
 			   void *buf, enum mlx5_fpga_direction direction)
 {
 	int ret;
 	struct mem_transfer xfer;
 
 	if (!fdev->shell_conn) {
 		ret = -ENOTCONN;
 		goto out;
 	}
 
 	xfer.t.data = buf;
 	xfer.t.size = size;
 	xfer.t.addr = addr;
 	xfer.t.conn = fdev->shell_conn;
 	xfer.t.direction = direction;
 	xfer.t.complete1 = mem_complete;
 	init_completion(&xfer.comp);
 	ret = mlx5_fpga_xfer_exec(&xfer.t);
 	if (ret) {
 		mlx5_fpga_dbg(fdev, "Transfer execution failed: %d\n", ret);
 		goto out;
 	}
 	wait_for_completion(&xfer.comp);
 	if (xfer.status != 0)
 		ret = -EIO;
 
 out:
 	return ret;
 }
 
 static int mlx5_fpga_mem_read_i2c(struct mlx5_fpga_device *fdev, size_t size,
 				  u64 addr, u8 *buf)
 {
 	size_t max_size = MLX5_FPGA_ACCESS_REG_SIZE_MAX;
 	size_t bytes_done = 0;
 	u8 actual_size;
 	int err = 0;
 
 	if (!size)
 		return -EINVAL;
 
 	if (!fdev->mdev)
 		return -ENOTCONN;
 
 	while (bytes_done < size) {
 		actual_size = min(max_size, (size - bytes_done));
 
 		err = mlx5_fpga_access_reg(fdev->mdev, actual_size,
 					   addr + bytes_done,
 					   buf + bytes_done, false);
 		if (err) {
 			mlx5_fpga_err(fdev, "Failed to read over I2C: %d\n",
 				      err);
 			break;
 		}
 
 		bytes_done += actual_size;
 	}
 
 	return err;
 }
 
 static int mlx5_fpga_mem_write_i2c(struct mlx5_fpga_device *fdev, size_t size,
 				   u64 addr, u8 *buf)
 {
 	size_t max_size = MLX5_FPGA_ACCESS_REG_SIZE_MAX;
 	size_t bytes_done = 0;
 	u8 actual_size;
 	int err = 0;
 
 	if (!size)
 		return -EINVAL;
 
 	if (!fdev->mdev)
 		return -ENOTCONN;
 
 	while (bytes_done < size) {
 		actual_size = min(max_size, (size - bytes_done));
 
 		err = mlx5_fpga_access_reg(fdev->mdev, actual_size,
 					   addr + bytes_done,
 					   buf + bytes_done, true);
 		if (err) {
 			mlx5_fpga_err(fdev, "Failed to write FPGA crspace\n");
 			break;
 		}
 
 		bytes_done += actual_size;
 	}
 
 	return err;
 }
 
 int mlx5_fpga_mem_read(struct mlx5_fpga_device *fdev, size_t size, u64 addr,
 		       void *buf, enum mlx5_fpga_access_type access_type)
 {
 	int ret;
 
 	if (access_type == MLX5_FPGA_ACCESS_TYPE_DONTCARE)
 		access_type = fdev->shell_conn ? MLX5_FPGA_ACCESS_TYPE_RDMA :
 						 MLX5_FPGA_ACCESS_TYPE_I2C;
 
 	mlx5_fpga_dbg(fdev, "Reading %zu bytes at 0x%jx over %s",
 		      size, (uintmax_t)addr, access_type ? "RDMA" : "I2C");
 
 	switch (access_type) {
 	case MLX5_FPGA_ACCESS_TYPE_RDMA:
 		ret = mem_transaction(fdev, size, addr, buf, MLX5_FPGA_READ);
 		if (ret)
 			return ret;
 		break;
 	case MLX5_FPGA_ACCESS_TYPE_I2C:
 		ret = mlx5_fpga_mem_read_i2c(fdev, size, addr, buf);
 		if (ret)
 			return ret;
 		break;
 	default:
 		mlx5_fpga_warn(fdev, "Unexpected read access_type %u\n",
 			       access_type);
 		return -EACCES;
 	}
 
 	return size;
 }
 EXPORT_SYMBOL(mlx5_fpga_mem_read);
 
 int mlx5_fpga_mem_write(struct mlx5_fpga_device *fdev, size_t size, u64 addr,
 			void *buf, enum mlx5_fpga_access_type access_type)
 {
 	int ret;
 
 	if (access_type == MLX5_FPGA_ACCESS_TYPE_DONTCARE)
 		access_type = fdev->shell_conn ? MLX5_FPGA_ACCESS_TYPE_RDMA :
 						 MLX5_FPGA_ACCESS_TYPE_I2C;
 
 	mlx5_fpga_dbg(fdev, "Writing %zu bytes at 0x%jx over %s",
 		      size, (uintmax_t)addr, access_type ? "RDMA" : "I2C");
 
 	switch (access_type) {
 	case MLX5_FPGA_ACCESS_TYPE_RDMA:
 		ret = mem_transaction(fdev, size, addr, buf, MLX5_FPGA_WRITE);
 		if (ret)
 			return ret;
 		break;
 	case MLX5_FPGA_ACCESS_TYPE_I2C:
 		ret = mlx5_fpga_mem_write_i2c(fdev, size, addr, buf);
 		if (ret)
 			return ret;
 		break;
 	default:
 		mlx5_fpga_warn(fdev, "Unexpected write access_type %u\n",
 			       access_type);
 		return -EACCES;
 	}
 
 	return size;
 }
 EXPORT_SYMBOL(mlx5_fpga_mem_write);
 
 int mlx5_fpga_get_sbu_caps(struct mlx5_fpga_device *fdev, int size, void *buf)
 {
 	return mlx5_fpga_sbu_caps(fdev->mdev, buf, size);
 }
 EXPORT_SYMBOL(mlx5_fpga_get_sbu_caps);
 
 u64 mlx5_fpga_ddr_size_get(struct mlx5_fpga_device *fdev)
 {
 	return (u64)MLX5_CAP_FPGA(fdev->mdev, fpga_ddr_size) << 10;
 }
 EXPORT_SYMBOL(mlx5_fpga_ddr_size_get);
 
 u64 mlx5_fpga_ddr_base_get(struct mlx5_fpga_device *fdev)
 {
 	return MLX5_CAP64_FPGA(fdev->mdev, fpga_ddr_start_addr);
 }
 EXPORT_SYMBOL(mlx5_fpga_ddr_base_get);
 
 void mlx5_fpga_client_data_set(struct mlx5_fpga_device *fdev,
 			       struct mlx5_fpga_client *client, void *data)
 {
 	struct mlx5_fpga_client_data *context;
 
 	list_for_each_entry(context, &fdev->client_data_list, list) {
 		if (context->client != client)
 			continue;
 		context->data = data;
 		return;
 	}
 
 	mlx5_fpga_warn(fdev, "No client context found for %s\n", client->name);
 }
 EXPORT_SYMBOL(mlx5_fpga_client_data_set);
 
 void *mlx5_fpga_client_data_get(struct mlx5_fpga_device *fdev,
 				struct mlx5_fpga_client *client)
 {
 	struct mlx5_fpga_client_data *context;
 	void *ret = NULL;
 
 	list_for_each_entry(context, &fdev->client_data_list, list) {
 		if (context->client != client)
 			continue;
 		ret = context->data;
 		goto out;
 	}
 	mlx5_fpga_warn(fdev, "No client context found for %s\n", client->name);
 
 out:
 	return ret;
 }
 EXPORT_SYMBOL(mlx5_fpga_client_data_get);
 
 void mlx5_fpga_device_query(struct mlx5_fpga_device *fdev,
 			    struct mlx5_fpga_query *query)
 {
 	unsigned long flags;
 
 	spin_lock_irqsave(&fdev->state_lock, flags);
 	query->image_status = fdev->image_status;
 	query->admin_image = fdev->last_admin_image;
 	query->oper_image = fdev->last_oper_image;
 	spin_unlock_irqrestore(&fdev->state_lock, flags);
 }
 EXPORT_SYMBOL(mlx5_fpga_device_query);
 
 int mlx5_fpga_device_reload(struct mlx5_fpga_device *fdev,
 			    enum mlx5_fpga_image image)
 {
 	struct mlx5_core_dev *mdev = fdev->mdev;
 	unsigned long timeout;
 	unsigned long flags;
 	int err = 0;
 
 	spin_lock_irqsave(&fdev->state_lock, flags);
 	switch (fdev->fdev_state) {
 	case MLX5_FDEV_STATE_NONE:
 		err = -ENODEV;
 		break;
 	case MLX5_FDEV_STATE_IN_PROGRESS:
 		err = -EBUSY;
 		break;
 	case MLX5_FDEV_STATE_SUCCESS:
 	case MLX5_FDEV_STATE_FAILURE:
 		break;
 	}
 	spin_unlock_irqrestore(&fdev->state_lock, flags);
 	if (err)
 		return err;
 
 	mutex_lock(&mdev->intf_state_mutex);
 	clear_bit(MLX5_INTERFACE_STATE_UP, &mdev->intf_state);
 
 	mlx5_unregister_device(mdev);
 	/* XXXKIB	mlx5_accel_ipsec_cleanup(mdev); */
 	mlx5_fpga_device_stop(mdev);
 
 	fdev->fdev_state = MLX5_FDEV_STATE_IN_PROGRESS;
 	reinit_completion(&fdev->load_event);
 
 	if (image <= MLX5_FPGA_IMAGE_MAX) {
 		mlx5_fpga_info(fdev, "Loading from flash\n");
 		err = mlx5_fpga_load(mdev, image);
 		if (err) {
 			mlx5_fpga_err(fdev, "Failed to request load: %d\n",
 				      err);
 			goto out;
 		}
 	} else {
 		mlx5_fpga_info(fdev, "Resetting\n");
 		err = mlx5_fpga_ctrl_op(mdev, MLX5_FPGA_CTRL_OPERATION_RESET);
 		if (err) {
 			mlx5_fpga_err(fdev, "Failed to request reset: %d\n",
 				      err);
 			goto out;
 		}
 	}
 
 	timeout = jiffies + msecs_to_jiffies(MLX5_FPGA_LOAD_TIMEOUT);
 	err = wait_for_completion_timeout(&fdev->load_event, timeout - jiffies);
 	if (err < 0) {
 		mlx5_fpga_err(fdev, "Failed waiting for FPGA load: %d\n", err);
 		fdev->fdev_state = MLX5_FDEV_STATE_FAILURE;
 		goto out;
 	}
 
 	err = mlx5_fpga_device_start(mdev);
 	if (err) {
 		mlx5_core_err(mdev, "fpga device start failed %d\n", err);
 		goto out;
 	}
 	/* XXXKIB err = mlx5_accel_ipsec_init(mdev); */
 	if (err) {
 		mlx5_core_err(mdev, "IPSec device start failed %d\n", err);
 		goto err_fpga;
 	}
 
 	err = mlx5_register_device(mdev);
 	if (err) {
 		mlx5_core_err(mdev, "mlx5_register_device failed %d\n", err);
 		fdev->fdev_state = MLX5_FDEV_STATE_FAILURE;
 		goto err_ipsec;
 	}
 
 	set_bit(MLX5_INTERFACE_STATE_UP, &mdev->intf_state);
 	goto out;
 
 err_ipsec:
 	/* XXXKIB mlx5_accel_ipsec_cleanup(mdev); */
 err_fpga:
 	mlx5_fpga_device_stop(mdev);
 out:
 	mutex_unlock(&mdev->intf_state_mutex);
 	return err;
 }
 EXPORT_SYMBOL(mlx5_fpga_device_reload);
 
 int mlx5_fpga_flash_select(struct mlx5_fpga_device *fdev,
 			   enum mlx5_fpga_image image)
 {
 	unsigned long flags;
 	int err;
 
 	spin_lock_irqsave(&fdev->state_lock, flags);
 	switch (fdev->fdev_state) {
 	case MLX5_FDEV_STATE_NONE:
 		spin_unlock_irqrestore(&fdev->state_lock, flags);
 		return -ENODEV;
 	case MLX5_FDEV_STATE_IN_PROGRESS:
 	case MLX5_FDEV_STATE_SUCCESS:
 	case MLX5_FDEV_STATE_FAILURE:
 		break;
 	}
 	spin_unlock_irqrestore(&fdev->state_lock, flags);
 
 	err = mlx5_fpga_image_select(fdev->mdev, image);
 	if (err)
 		mlx5_fpga_err(fdev, "Failed to select flash image: %d\n", err);
 	else
 		fdev->last_admin_image = image;
 	return err;
 }
 EXPORT_SYMBOL(mlx5_fpga_flash_select);
 
+int mlx5_fpga_temperature(struct mlx5_fpga_device *fdev,
+			  struct mlx5_fpga_temperature *temp)
+{
+	return mlx5_fpga_query_mtmp(fdev->mdev, temp);
+}
+EXPORT_SYMBOL(mlx5_fpga_temperature);
+
 struct device *mlx5_fpga_dev(struct mlx5_fpga_device *fdev)
 {
 	return &fdev->mdev->pdev->dev;
 }
 EXPORT_SYMBOL(mlx5_fpga_dev);
 
 void mlx5_fpga_get_cap(struct mlx5_fpga_device *fdev, u32 *fpga_caps)
 {
 	unsigned long flags;
 
 	spin_lock_irqsave(&fdev->state_lock, flags);
 	memcpy(fpga_caps, &fdev->mdev->caps.fpga, sizeof(fdev->mdev->caps.fpga));
 	spin_unlock_irqrestore(&fdev->state_lock, flags);
 }
 EXPORT_SYMBOL(mlx5_fpga_get_cap);
Index: head/sys/dev/mlx5/mlx5_fpga/sdk.h
===================================================================
--- head/sys/dev/mlx5/mlx5_fpga/sdk.h	(revision 341574)
+++ head/sys/dev/mlx5/mlx5_fpga/sdk.h	(revision 341575)
@@ -1,368 +1,378 @@
 /*-
  * Copyright (c) 2017 Mellanox Technologies. All rights reserved.
  *
  * This software is available to you under a choice of one of two
  * licenses.  You may choose to be licensed under the terms of the GNU
  * General Public License (GPL) Version 2, available from the file
  * COPYING in the main directory of this source tree, or the
  * OpenIB.org BSD license below:
  *
  *     Redistribution and use in source and binary forms, with or
  *     without modification, are permitted provided that the following
  *     conditions are met:
  *
  *      - Redistributions of source code must retain the above
  *        copyright notice, this list of conditions and the following
  *        disclaimer.
  *
  *      - Redistributions in binary form must reproduce the above
  *        copyright notice, this list of conditions and the following
  *        disclaimer in the documentation and/or other materials
  *        provided with the distribution.
  *
  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  * SOFTWARE.
  *
  * $FreeBSD$
  */
 
 #ifndef MLX5_FPGA_SDK_H
 #define MLX5_FPGA_SDK_H
 
 #include <dev/mlx5/driver.h>
 #include <linux/types.h>
 #include <linux/list.h>
 /* #include <linux/dma-direction.h> */
 
 #include <dev/mlx5/mlx5_fpga/cmd.h>
 #include <dev/mlx5/mlx5io.h>
 
 /**
  * DOC: Innova SDK
  * This header defines the in-kernel API for Innova FPGA client drivers.
  */
 
 #define MLX5_FPGA_CLIENT_NAME_MAX 64
 
 struct mlx5_fpga_conn;
 struct mlx5_fpga_device;
 
 /**
  * struct mlx5_fpga_client - Describes an Innova client driver
  */
 struct mlx5_fpga_client {
 	/**
 	 * @create: Informs the client that an Innova device was created.
 	 * The device is not yet operational at this stage
 	 * This callback is optional
 	 * @fdev: The FPGA device
 	 */
 	void (*create)(struct mlx5_fpga_device *fdev);
 	/**
 	 * @add: Informs the client that a core device is ready and operational.
 	 * @fdev: The FPGA device
 	 * @param vid SBU Vendor ID
 	 * @param pid SBU Product ID
 	 * Any SBU-specific initialization should happen at this stage
 	 * Return: 0 on success, nonzero error value otherwise
 	 */
 	int  (*add)(struct mlx5_fpga_device *fdev, u32 vid, u16 pid);
 	/**
 	 * @remove: Informs the client that a core device is not operational
 	 *          anymore.
 	 * @fdev: The FPGA device
 	 * SBU-specific cleanup should happen at this stage
 	 * This callback is called once for every successful call to add()
 	 */
 	void (*remove)(struct mlx5_fpga_device *fdev);
 	/**
 	 * @destroy: Informs the client that a core device is being destroyed.
 	 * @fdev: The FPGA device
 	 * The device is not operational at this stage
 	 */
 	void (*destroy)(struct mlx5_fpga_device *fdev);
 	/** The name of this client driver */
 	char name[MLX5_FPGA_CLIENT_NAME_MAX];
 	/** For use by core. A link in the list of client drivers */
 	struct list_head list;
 };
 
 /**
  * struct mlx5_fpga_dma_entry - A scatter-gather DMA entry
  */
 struct mlx5_fpga_dma_entry {
 	/** @data: Virtual address pointer to the data */
 	void *data;
 	/** @size: Size in bytes of the data */
 	unsigned int size;
 	/** @dma_addr: Private member. Physical DMA-mapped address of the data */
 	dma_addr_t dma_addr;
 };
 
 /**
  * struct mlx5_fpga_dma_buf - A packet buffer
  * May contain up to 2 scatter-gather data entries
  */
 struct mlx5_fpga_dma_buf {
 	/** @dma_dir: DMA direction */
 	enum dma_data_direction dma_dir;
 	/** @sg: Scatter-gather entries pointing to the data in memory */
 	struct mlx5_fpga_dma_entry sg[2];
 	/** @list: Item in SQ backlog, for TX packets */
 	struct list_head list;
 	/**
 	 * @complete: Completion routine, for TX packets
 	 * @conn: FPGA Connection this packet was sent to
 	 * @fdev: FPGA device this packet was sent to
 	 * @buf: The packet buffer
 	 * @status: 0 if successful, or an error code otherwise
 	 */
 	void (*complete)(struct mlx5_fpga_conn *conn,
 			 struct mlx5_fpga_device *fdev,
 			 struct mlx5_fpga_dma_buf *buf, u8 status);
 };
 
 /**
  * struct mlx5_fpga_conn_attr - FPGA connection attributes
  * Describes the attributes of a connection
  */
 struct mlx5_fpga_conn_attr {
 	/** @tx_size: Size of connection TX queue, in packets */
 	unsigned int tx_size;
 	/** @rx_size: Size of connection RX queue, in packets */
 	unsigned int rx_size;
 	/**
 	 * @recv_cb: Callback function which is called for received packets
 	 * @cb_arg: The value provided in mlx5_fpga_conn_attr.cb_arg
 	 * @buf: A buffer containing a received packet
 	 *
 	 * buf is guaranteed to only contain a single scatter-gather entry.
 	 * The size of the actual packet received is specified in buf.sg[0].size
 	 * When this callback returns, the packet buffer may be re-used for
 	 * subsequent receives.
 	 */
 	void (*recv_cb)(void *cb_arg, struct mlx5_fpga_dma_buf *buf);
 	void *cb_arg;
 };
 
 /**
  * mlx5_fpga_client_register() - Register a client driver
  * @client: The properties of the client driver
  *
  * Should be called from a client driver's module init routine.
  * Note: The core will immediately callback create() and add() for any existing
  * devices in the system, as well as new ones added later on.
  */
 void mlx5_fpga_client_register(struct mlx5_fpga_client *client);
 /**
  * mlx5_fpga_client_unregister() - Unregister a client driver
  * @client: The client driver to unregister
  *
  * Should be called from a client driver's module exit routine.
  * Note: The core will immediately callback delete() and destroy() for any
  * created/added devices in the system, to clean up their state.
  */
 void mlx5_fpga_client_unregister(struct mlx5_fpga_client *client);
 
 /**
  * mlx5_fpga_device_reload() - Force the FPGA to reload its synthesis from flash
  * @fdev: The FPGA device
  * @image: Which flash image to load
  *
  * This routine attempts graceful teardown of all device resources before
  * loading. This includes a callback to client driver delete().
  * Calls client driver add() once device is operational again.
  * Blocks until the new synthesis is loaded, and the device is fully
  * initialized.
  *
  * Return: 0 if successful, or a negative error value otherwise
  */
 int mlx5_fpga_device_reload(struct mlx5_fpga_device *fdev,
 			    enum mlx5_fpga_image image);
 
 /**
  * mlx5_fpga_flash_select() - Select the current active flash
  * @fdev: The FPGA device
  * @image: Which flash image will be active
  *
  * This routine selects the active flash by programming the relevant MUX.
  * Useful prior to burning a new image on flash.
  * This setting is volatile and is reset upon reboot or power-cycle
  *
  * Return: 0 if successful, or a negative error value otherwise
  */
 int mlx5_fpga_flash_select(struct mlx5_fpga_device *fdev,
 			   enum mlx5_fpga_image image);
 
 /**
  * mlx5_fpga_sbu_conn_create() - Initialize a new FPGA SBU connection
  * @fdev: The FPGA device
  * @attr: Attributes of the new connection
  *
  * Sets up a new FPGA SBU connection with the specified attributes.
  * The receive callback function may be called for incoming messages even
  * before this function returns.
  *
  * The caller must eventually destroy the connection by calling
  * mlx5_fpga_sbu_conn_destroy.
  *
  * Return: A new connection, or ERR_PTR() error value otherwise.
  */
 struct mlx5_fpga_conn *
 mlx5_fpga_sbu_conn_create(struct mlx5_fpga_device *fdev,
 			  struct mlx5_fpga_conn_attr *attr);
 
 /**
  * mlx5_fpga_sbu_conn_destroy() - Destroy an FPGA SBU connection
  * @conn: The FPGA SBU connection to destroy
  *
  * Cleans up an FPGA SBU connection which was previously created with
  * mlx5_fpga_sbu_conn_create.
  */
 void mlx5_fpga_sbu_conn_destroy(struct mlx5_fpga_conn *conn);
 
 /**
  * mlx5_fpga_sbu_conn_sendmsg() - Queue the transmission of a packet
  * @fdev: An FPGA SBU connection
  * @buf: The packet buffer
  *
  * Queues a packet for transmission over an FPGA SBU connection.
  * The buffer should not be modified or freed until completion.
  * Upon completion, the buf's complete() callback is invoked, indicating the
  * success or error status of the transmission.
  *
  * Return: 0 if successful, or an error value otherwise.
  */
 int mlx5_fpga_sbu_conn_sendmsg(struct mlx5_fpga_conn *conn,
 			       struct mlx5_fpga_dma_buf *buf);
 
 /**
  * mlx5_fpga_mem_read() - Read from FPGA memory address space
  * @fdev: The FPGA device
  * @size: Size of chunk to read, in bytes
  * @addr: Starting address to read from, in FPGA address space
  * @buf: Buffer to read into
  * @access_type: Method for reading
  *
  * Reads from the specified address into the specified buffer.
  * The address may point to configuration space or to DDR.
  * Large reads may be performed internally as several non-atomic operations.
  * This function may sleep, so should not be called from atomic contexts.
  *
  * Return: 0 if successful, or an error value otherwise.
  */
 int mlx5_fpga_mem_read(struct mlx5_fpga_device *fdev, size_t size, u64 addr,
 		       void *buf, enum mlx5_fpga_access_type access_type);
 
 /**
  * mlx5_fpga_mem_write() - Write to FPGA memory address space
  * @fdev: The FPGA device
  * @size: Size of chunk to write, in bytes
  * @addr: Starting address to write to, in FPGA address space
  * @buf: Buffer which contains data to write
  * @access_type: Method for writing
  *
  * Writes the specified buffer data to FPGA memory at the specified address.
  * The address may point to configuration space or to DDR.
  * Large writes may be performed internally as several non-atomic operations.
  * This function may sleep, so should not be called from atomic contexts.
  *
  * Return: 0 if successful, or an error value otherwise.
  */
 int mlx5_fpga_mem_write(struct mlx5_fpga_device *fdev, size_t size, u64 addr,
 			void *buf, enum mlx5_fpga_access_type access_type);
 
 /**
  * mlx5_fpga_get_sbu_caps() - Read the SBU capabilities
  * @fdev: The FPGA device
  * @size: Size of the buffer to read into
  * @buf: Buffer to read the capabilities into
  *
  * Reads the FPGA SBU capabilities into the specified buffer.
  * The format of the capabilities buffer is SBU-dependent.
  *
  * Return: 0 if successful
  *         -EINVAL if the buffer is not large enough to contain SBU caps
  *         or any other error value otherwise.
  */
 int mlx5_fpga_get_sbu_caps(struct mlx5_fpga_device *fdev, int size, void *buf);
 
 /**
  * mlx5_fpga_ddr_size_get() - Retrieve the size of FPGA DDR
  * @fdev: The FPGA device
  *
  * Return: Size of DDR avaailable for FPGA, in bytes
  */
 u64 mlx5_fpga_ddr_size_get(struct mlx5_fpga_device *fdev);
 
 /**
  * mlx5_fpga_ddr_base_get() - Retrieve the base address of FPGA DDR
  * @fdev: The FPGA device
  *
  * Return: Base address of DDR in FPGA address space
  */
 u64 mlx5_fpga_ddr_base_get(struct mlx5_fpga_device *fdev);
 
 /**
  * mlx5_fpga_client_data_set() - Attach client-defined private value to a device
  * @fdev: The FPGA device
  * @client: The client driver
  * @data: Opaque private value
  *
  * Client driver may use the private value for storing device-specific
  * state and configuration information, and may retrieve it with a call to
  * mlx5_fpga_client_data_get().
  */
 void mlx5_fpga_client_data_set(struct mlx5_fpga_device *fdev,
 			       struct mlx5_fpga_client *client,
 			       void *data);
 
 /**
  * mlx5_fpga_client_data_get() - Retrieve client-defined private value
  * @fdev: The FPGA device
  * @client: The client driver
  *
  * Client driver may use the private value for storing device-specific
  * state and configuration information by calling mlx5_fpga_client_data_set()
  *
  * Return: The private value
  */
 void *mlx5_fpga_client_data_get(struct mlx5_fpga_device *fdev,
 				struct mlx5_fpga_client *client);
 
 /**
  * mlx5_fpga_device_query() - Query FPGA device state information
  * @fdev: The FPGA device
  * @query: Returns the device state
  *
  * Queries the device state and returns it in *query
  */
 void mlx5_fpga_device_query(struct mlx5_fpga_device *fdev,
 			    struct mlx5_fpga_query *query);
 
 /**
  * mlx5_fpga_dev() - Retrieve FPGA device structure
  * @fdev: The FPGA device
 
  * Return: A pointer to a struct device, which may be used with dev_* logging,
  *         sysfs extensions, etc.
  */
 struct device *mlx5_fpga_dev(struct mlx5_fpga_device *fdev);
 
 /**
+ * mlx5_fpga_temperature() - Retrieve FPGA sensor of temperature
+ * @fdev: The FPGA device
+
+ * Return: 0 if successful
+ *         or any other error value otherwise.
+ */
+int mlx5_fpga_temperature(struct mlx5_fpga_device *fdev,
+			  struct mlx5_fpga_temperature *temp);
+
+/**
  * mlx5_fpga_get_cap() - Returns the FPGA cap mailbox from FW without parsing.
  * @fdev: The FPGA device
  * @fpga_caps: Is an array with a length of according to the size of
  *           mlx5_ifc_fpga_cap_bits/32
  *
  * Returns a copy of the FPGA caps mailbox and returns it in fpga_caps
  */
 void mlx5_fpga_get_cap(struct mlx5_fpga_device *fdev, u32 *fpga_caps);
 
 #endif /* MLX5_FPGA_SDK_H */
Index: head/sys/dev/mlx5/mlx5_fpga_tools/mlx5fpga_tools_char.c
===================================================================
--- head/sys/dev/mlx5/mlx5_fpga_tools/mlx5fpga_tools_char.c	(revision 341574)
+++ head/sys/dev/mlx5/mlx5_fpga_tools/mlx5fpga_tools_char.c	(revision 341575)
@@ -1,325 +1,331 @@
 /*-
  * Copyright (c) 2017 Mellanox Technologies. All rights reserved.
  *
  * This software is available to you under a choice of one of two
  * licenses.  You may choose to be licensed under the terms of the GNU
  * General Public License (GPL) Version 2, available from the file
  * COPYING in the main directory of this source tree, or the
  * OpenIB.org BSD license below:
  *
  *     Redistribution and use in source and binary forms, with or
  *     without modification, are permitted provided that the following
  *     conditions are met:
  *
  *      - Redistributions of source code must retain the above
  *        copyright notice, this list of conditions and the following
  *        disclaimer.
  *
  *      - Redistributions in binary form must reproduce the above
  *        copyright notice, this list of conditions and the following
  *        disclaimer in the documentation and/or other materials
  *        provided with the distribution.
  *
  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  * SOFTWARE.
  *
  * $FreeBSD$
  */
 
 #include <sys/param.h>
 #include <sys/systm.h>
 #include <sys/conf.h>
 #include <dev/mlx5/mlx5io.h>
 #include <dev/mlx5/mlx5_fpga_tools/tools_char.h>
 
 #define CHUNK_SIZE (128 * 1024)
 
 struct tools_context {
 	struct mlx5_fpga_tools_dev *tdev;
 	enum mlx5_fpga_access_type access_type;
 };
 
 static void
 tools_char_ctx_dtor(void *data)
 {
 
 	free(data, M_DEVBUF);
 }
 
 static int
 tools_char_open(struct cdev *dev, int oflags, int devtype, struct thread *td)
 {
 	struct tools_context *context;
 
 	context = malloc(sizeof(*context), M_DEVBUF, M_WAITOK);
 	context->tdev = dev->si_drv1;
 	context->access_type = MLX5_FPGA_ACCESS_TYPE_DONTCARE;
 	devfs_set_cdevpriv(context, tools_char_ctx_dtor);
 	return (0);
 }
 
 static int
 mem_read(struct mlx5_fpga_tools_dev *tdev, void *buf, size_t count,
     u64 address, enum mlx5_fpga_access_type access_type, size_t *retcnt)
 {
 	int ret;
 
 	ret = sx_xlock_sig(&tdev->lock);
 	if (ret != 0)
 		return (ret);
 	ret = mlx5_fpga_mem_read(tdev->fdev, count, address, buf, access_type);
 	sx_xunlock(&tdev->lock);
 	if (ret < 0) {
 		dev_dbg(mlx5_fpga_dev(tdev->fdev),
 			"Failed to read %zu bytes at address 0x%jx: %d\n",
 			count, (uintmax_t)address, ret);
 		return (-ret);
 	}
 	*retcnt = ret;
 	return (0);
 }
 
 static int
 mem_write(struct mlx5_fpga_tools_dev *tdev, void *buf, size_t count,
     u64 address, enum mlx5_fpga_access_type access_type, size_t *retcnt)
 {
 	int ret;
 
 	ret = sx_xlock_sig(&tdev->lock);
 	if (ret != 0)
 		return (ret);
 	ret = mlx5_fpga_mem_write(tdev->fdev, count, address, buf, access_type);
 	sx_xunlock(&tdev->lock);
 	if (ret < 0) {
 		dev_dbg(mlx5_fpga_dev(tdev->fdev),
 			"Failed to write %zu bytes at address 0x%jx: %d\n",
 			count, (uintmax_t)address, ret);
 		return (-ret);
 	}
 	*retcnt = ret;
 	return (0);
 }
 
 static void
 tools_char_llseek(struct tools_context *context, struct uio *uio, ssize_t *len)
 {
 	uint64_t fbase, fsize;
 	size_t llen;
 
 	llen = uio->uio_resid;
 	if (llen < 1) {
 		*len = 0;
 		return;
 	}
 	if (llen > CHUNK_SIZE)
 		llen = CHUNK_SIZE;
 	fbase = mlx5_fpga_ddr_base_get(context->tdev->fdev);
 	fsize = mlx5_fpga_ddr_size_get(context->tdev->fdev);
 	if (uio->uio_offset > fbase)
 		*len = 0;
 	else if (uio->uio_offset + *len > fbase + fsize)
 		*len = fbase + fsize - uio->uio_offset;
 	else
 		*len = llen;
 }
 
 static int
 tools_char_read(struct cdev *dev, struct uio *uio, int ioflag)
 {
 	struct tools_context *context;
 	void *kbuf;
 	size_t len, len1;
 	int ret;
 
 	ret = devfs_get_cdevpriv((void **)&context);
 	if (ret != 0)
 		return (ret);
 	dev_dbg(mlx5_fpga_dev(context->tdev->fdev),
 	    "tools char device reading %zu bytes at 0x%jx\n", uio->uio_resid,
 	     (uintmax_t)uio->uio_offset);
 
 	tools_char_llseek(context, uio, &len);
 	if (len == 0)
 		return (0);
 
 	kbuf = malloc(len, M_DEVBUF, M_WAITOK);
 	ret = mem_read(context->tdev, kbuf, len, uio->uio_offset,
 	    context->access_type, &len1);
 	if (ret == 0)
 		ret = uiomove(kbuf, len1, uio);
 	free(kbuf, M_DEVBUF);
 	return (ret);
 }
 
 static int
 tools_char_write(struct cdev *dev, struct uio *uio, int ioflag)
 {
 	struct tools_context *context;
 	void *kbuf;
 	off_t of;
 	size_t len, len1;
 	int ret;
 
 	ret = devfs_get_cdevpriv((void **)&context);
 	if (ret != 0)
 		return (ret);
 	dev_dbg(mlx5_fpga_dev(context->tdev->fdev),
 	    "tools char device reading %zu bytes at 0x%jx\n", uio->uio_resid,
 	    (uintmax_t)uio->uio_offset);
 
 	tools_char_llseek(context, uio, &len);
 	if (len == 0)
 		return (0);
 
 	kbuf = malloc(len, M_DEVBUF, M_WAITOK);
 	len1 = uio->uio_resid;
 	of = uio->uio_offset;
 
 	ret = uiomove(kbuf, len, uio);
 	if (ret == 0) {
 		len1 -= uio->uio_resid;
 		ret = mem_write(context->tdev, kbuf, len, of,
 		    context->access_type, &len1);
 	}
 	free(kbuf, M_DEVBUF);
 	return (ret);
 }
 
 CTASSERT(MLX5_FPGA_CAP_ARR_SZ == MLX5_ST_SZ_DW(fpga_cap));
 
 static int
 tools_char_ioctl(struct cdev *dev, u_long cmd, caddr_t data, int fflag,
     struct thread *td)
 {
 	struct tools_context *context;
 	struct mlx5_fpga_device *fdev;
 	struct mlx5_fpga_query query;
+	struct mlx5_fpga_temperature *temperature;
 	u32 fpga_cap[MLX5_ST_SZ_DW(fpga_cap)] = {0};
 	int arg, err;
 
 	err = devfs_get_cdevpriv((void **)&context);
 	if (err != 0)
 		return (err);
 	fdev = context->tdev->fdev;
 	if (fdev == NULL)
 		return (ENXIO);
 
 	switch (cmd) {
 	case MLX5_FPGA_ACCESS_TYPE:
 		arg = *(int *)data;
 		if (arg > MLX5_FPGA_ACCESS_TYPE_MAX) {
 			dev_err(mlx5_fpga_dev(fdev),
 			    "unknown access type %u\n", arg);
 			err = EINVAL;
 			break;
 		}
 		context->access_type = arg;
 		break;
 	case MLX5_FPGA_LOAD:
 		arg = *(int *)data;
 		if (arg > MLX5_FPGA_IMAGE_MAX) {
 			dev_err(mlx5_fpga_dev(fdev),
 				"unknown image type %u\n", arg);
 			err = EINVAL;
 			break;
 		}
 		err = mlx5_fpga_device_reload(fdev, arg);
 		break;
 	case MLX5_FPGA_RESET:
 		err = mlx5_fpga_device_reload(fdev, MLX5_FPGA_IMAGE_MAX + 1);
 		break;
 	case MLX5_FPGA_IMAGE_SEL:
 		arg = *(int *)data;
 		if (arg > MLX5_FPGA_IMAGE_MAX) {
 			dev_err(mlx5_fpga_dev(fdev),
 			    "unknown image type %u\n", arg);
 			err = EINVAL;
 			break;
 		}
 		err = mlx5_fpga_flash_select(fdev, arg);
 		break;
 	case MLX5_FPGA_QUERY:
 		mlx5_fpga_device_query(fdev, &query);
 		bcopy(&query, data, sizeof(query));
 		err = 0;
 		break;
 	case MLX5_FPGA_CAP:
 		mlx5_fpga_get_cap(fdev, fpga_cap);
 		bcopy(&fpga_cap, data, sizeof(fpga_cap));
 		err = 0;
+		break;
+	case MLX5_FPGA_TEMPERATURE:
+		temperature = (struct mlx5_fpga_temperature *)data;
+		mlx5_fpga_temperature(fdev, temperature);
+		err = 0; /* XXXKIB */
 		break;
 	default:
 		dev_err(mlx5_fpga_dev(fdev),
 			"unknown ioctl command %#08lx\n", cmd);
 		err = ENOTTY;
 	}
 	return (err);
 }
 
 static struct cdevsw mlx5_tools_char_cdevsw = {
 	.d_version =	D_VERSION,
 	.d_name =	"mlx5_tools_char",
 	.d_open =	tools_char_open,
 	.d_read =	tools_char_read,
 	.d_write =	tools_char_write,
 	.d_ioctl =	tools_char_ioctl,
 };
 
 int
 mlx5_fpga_tools_char_add_one(struct mlx5_fpga_tools_dev *tdev)
 {
 	struct make_dev_args mda;
 	struct cdev *cd;
 	device_t bdev;
 	int ret;
 
 	make_dev_args_init(&mda);
 	mda.mda_flags = MAKEDEV_WAITOK | MAKEDEV_CHECKNAME;
 	mda.mda_devsw = &mlx5_tools_char_cdevsw;
 	mda.mda_uid = UID_ROOT;
 	mda.mda_gid = GID_OPERATOR;
 	mda.mda_mode = 0660;
 	mda.mda_si_drv1 = tdev;
 	bdev = mlx5_fpga_dev(tdev->fdev)->bsddev;
 	ret = make_dev_s(&mda, &cd,
 	    "%04x:%02x:%02x.%x" MLX5_FPGA_TOOLS_NAME_SUFFIX,
 	    pci_get_domain(bdev), pci_get_bus(bdev), pci_get_slot(bdev),
 	    pci_get_function(bdev));
 	if (ret != 0) {
 		tdev->char_device = NULL;
 		dev_err(mlx5_fpga_dev(tdev->fdev),
 		    "Failed to create a char device: %d\n", ret);
 		return (-ret);
 	}
 	tdev->char_device = cd;
 
 	dev_dbg(mlx5_fpga_dev(tdev->fdev), "tools char device %s created\n",
 	    cd->si_name);
 	return (0);
 }
 
 void mlx5_fpga_tools_char_remove_one(struct mlx5_fpga_tools_dev *tdev)
 {
 
 	dev_err(mlx5_fpga_dev(tdev->fdev), "tools char device %s destroyed\n",
 	    ((struct cdev *)(tdev->char_device))->si_name);
 	destroy_dev((struct cdev *)(tdev->char_device));
 }
 
 int
 mlx5_fpga_tools_char_init(void)
 {
 
 	return (0);
 }
 
 void
 mlx5_fpga_tools_char_deinit(void)
 {
 }
Index: head/sys/dev/mlx5/mlx5_ifc.h
===================================================================
--- head/sys/dev/mlx5/mlx5_ifc.h	(revision 341574)
+++ head/sys/dev/mlx5/mlx5_ifc.h	(revision 341575)
@@ -1,9772 +1,9797 @@
 /*-
  * Copyright (c) 2013-2017, Mellanox Technologies, Ltd.  All rights reserved.
  *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions
  * are met:
  * 1. Redistributions of source code must retain the above copyright
  *    notice, this list of conditions and the following disclaimer.
  * 2. Redistributions in binary form must reproduce the above copyright
  *    notice, this list of conditions and the following disclaimer in the
  *    documentation and/or other materials provided with the distribution.
  *
  * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS `AS IS' AND
  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  * ARE DISCLAIMED.  IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE
  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  * SUCH DAMAGE.
  *
  * $FreeBSD$
  */
 
 #ifndef MLX5_IFC_H
 #define MLX5_IFC_H
 
 #include <dev/mlx5/mlx5_fpga/mlx5_ifc_fpga.h>
 
 enum {
 	MLX5_EVENT_TYPE_COMP                                       = 0x0,
 	MLX5_EVENT_TYPE_PATH_MIG                                   = 0x1,
 	MLX5_EVENT_TYPE_COMM_EST                                   = 0x2,
 	MLX5_EVENT_TYPE_SQ_DRAINED                                 = 0x3,
 	MLX5_EVENT_TYPE_SRQ_LAST_WQE                               = 0x13,
 	MLX5_EVENT_TYPE_SRQ_RQ_LIMIT                               = 0x14,
 	MLX5_EVENT_TYPE_DCT_DRAINED                                = 0x1c,
 	MLX5_EVENT_TYPE_DCT_KEY_VIOLATION                          = 0x1d,
 	MLX5_EVENT_TYPE_CQ_ERROR                                   = 0x4,
 	MLX5_EVENT_TYPE_WQ_CATAS_ERROR                             = 0x5,
 	MLX5_EVENT_TYPE_PATH_MIG_FAILED                            = 0x7,
 	MLX5_EVENT_TYPE_PAGE_FAULT                                 = 0xc,
 	MLX5_EVENT_TYPE_WQ_INVAL_REQ_ERROR                         = 0x10,
 	MLX5_EVENT_TYPE_WQ_ACCESS_ERROR                            = 0x11,
 	MLX5_EVENT_TYPE_SRQ_CATAS_ERROR                            = 0x12,
 	MLX5_EVENT_TYPE_INTERNAL_ERROR                             = 0x8,
 	MLX5_EVENT_TYPE_PORT_CHANGE                                = 0x9,
 	MLX5_EVENT_TYPE_GPIO_EVENT                                 = 0x15,
 	MLX5_EVENT_TYPE_CODING_PORT_MODULE_EVENT                   = 0x16,
 	MLX5_EVENT_TYPE_CODING_TEMP_WARNING_EVENT                  = 0x17,
 	MLX5_EVENT_TYPE_REMOTE_CONFIG                              = 0x19,
 	MLX5_EVENT_TYPE_CODING_DCBX_CHANGE_EVENT                   = 0x1e,
 	MLX5_EVENT_TYPE_CODING_PPS_EVENT                           = 0x25,
 	MLX5_EVENT_TYPE_CODING_GENERAL_NOTIFICATION_EVENT          = 0x22,
 	MLX5_EVENT_TYPE_DB_BF_CONGESTION                           = 0x1a,
 	MLX5_EVENT_TYPE_STALL_EVENT                                = 0x1b,
 	MLX5_EVENT_TYPE_DROPPED_PACKET_LOGGED_EVENT                = 0x1f,
 	MLX5_EVENT_TYPE_CMD                                        = 0xa,
 	MLX5_EVENT_TYPE_PAGE_REQUEST                               = 0xb,
 	MLX5_EVENT_TYPE_NIC_VPORT_CHANGE                           = 0xd,
 	MLX5_EVENT_TYPE_FPGA_ERROR                                 = 0x20,
 	MLX5_EVENT_TYPE_FPGA_QP_ERROR                              = 0x21,
 };
 
 enum {
 	MLX5_MODIFY_TIR_BITMASK_LRO                                = 0x0,
 	MLX5_MODIFY_TIR_BITMASK_INDIRECT_TABLE                     = 0x1,
 	MLX5_MODIFY_TIR_BITMASK_HASH                               = 0x2,
 	MLX5_MODIFY_TIR_BITMASK_TUNNELED_OFFLOAD_EN                = 0x3,
 	MLX5_MODIFY_TIR_BITMASK_SELF_LB_EN                         = 0x4
 };
 
 enum {
 	MLX5_MODIFY_RQT_BITMASK_RQN_LIST          = 0x1,
 };
 
 enum {
 	MLX5_SET_HCA_CAP_OP_MOD_GENERAL_DEVICE        = 0x0,
 	MLX5_SET_HCA_CAP_OP_MOD_ATOMIC                = 0x3,
 };
 
 enum {
 	MLX5_CMD_OP_QUERY_HCA_CAP                 = 0x100,
 	MLX5_CMD_OP_QUERY_ADAPTER                 = 0x101,
 	MLX5_CMD_OP_INIT_HCA                      = 0x102,
 	MLX5_CMD_OP_TEARDOWN_HCA                  = 0x103,
 	MLX5_CMD_OP_ENABLE_HCA                    = 0x104,
 	MLX5_CMD_OP_DISABLE_HCA                   = 0x105,
 	MLX5_CMD_OP_QUERY_PAGES                   = 0x107,
 	MLX5_CMD_OP_MANAGE_PAGES                  = 0x108,
 	MLX5_CMD_OP_SET_HCA_CAP                   = 0x109,
 	MLX5_CMD_OP_QUERY_ISSI                    = 0x10a,
 	MLX5_CMD_OP_SET_ISSI                      = 0x10b,
 	MLX5_CMD_OP_SET_DRIVER_VERSION            = 0x10d,
 	MLX5_CMD_OP_QUERY_OTHER_HCA_CAP           = 0x10e,
 	MLX5_CMD_OP_MODIFY_OTHER_HCA_CAP          = 0x10f,
 	MLX5_CMD_OP_CREATE_MKEY                   = 0x200,
 	MLX5_CMD_OP_QUERY_MKEY                    = 0x201,
 	MLX5_CMD_OP_DESTROY_MKEY                  = 0x202,
 	MLX5_CMD_OP_QUERY_SPECIAL_CONTEXTS        = 0x203,
 	MLX5_CMD_OP_PAGE_FAULT_RESUME             = 0x204,
 	MLX5_CMD_OP_CREATE_EQ                     = 0x301,
 	MLX5_CMD_OP_DESTROY_EQ                    = 0x302,
 	MLX5_CMD_OP_QUERY_EQ                      = 0x303,
 	MLX5_CMD_OP_GEN_EQE                       = 0x304,
 	MLX5_CMD_OP_CREATE_CQ                     = 0x400,
 	MLX5_CMD_OP_DESTROY_CQ                    = 0x401,
 	MLX5_CMD_OP_QUERY_CQ                      = 0x402,
 	MLX5_CMD_OP_MODIFY_CQ                     = 0x403,
 	MLX5_CMD_OP_CREATE_QP                     = 0x500,
 	MLX5_CMD_OP_DESTROY_QP                    = 0x501,
 	MLX5_CMD_OP_RST2INIT_QP                   = 0x502,
 	MLX5_CMD_OP_INIT2RTR_QP                   = 0x503,
 	MLX5_CMD_OP_RTR2RTS_QP                    = 0x504,
 	MLX5_CMD_OP_RTS2RTS_QP                    = 0x505,
 	MLX5_CMD_OP_SQERR2RTS_QP                  = 0x506,
 	MLX5_CMD_OP_2ERR_QP                       = 0x507,
 	MLX5_CMD_OP_2RST_QP                       = 0x50a,
 	MLX5_CMD_OP_QUERY_QP                      = 0x50b,
 	MLX5_CMD_OP_SQD_RTS_QP                    = 0x50c,
 	MLX5_CMD_OP_INIT2INIT_QP                  = 0x50e,
 	MLX5_CMD_OP_CREATE_PSV                    = 0x600,
 	MLX5_CMD_OP_DESTROY_PSV                   = 0x601,
 	MLX5_CMD_OP_CREATE_SRQ                    = 0x700,
 	MLX5_CMD_OP_DESTROY_SRQ                   = 0x701,
 	MLX5_CMD_OP_QUERY_SRQ                     = 0x702,
 	MLX5_CMD_OP_ARM_RQ                        = 0x703,
 	MLX5_CMD_OP_CREATE_XRC_SRQ                = 0x705,
 	MLX5_CMD_OP_DESTROY_XRC_SRQ               = 0x706,
 	MLX5_CMD_OP_QUERY_XRC_SRQ                 = 0x707,
 	MLX5_CMD_OP_ARM_XRC_SRQ                   = 0x708,
 	MLX5_CMD_OP_CREATE_DCT                    = 0x710,
 	MLX5_CMD_OP_DESTROY_DCT                   = 0x711,
 	MLX5_CMD_OP_DRAIN_DCT                     = 0x712,
 	MLX5_CMD_OP_QUERY_DCT                     = 0x713,
 	MLX5_CMD_OP_ARM_DCT_FOR_KEY_VIOLATION     = 0x714,
 	MLX5_CMD_OP_SET_DC_CNAK_TRACE             = 0x715,
 	MLX5_CMD_OP_QUERY_DC_CNAK_TRACE           = 0x716,
 	MLX5_CMD_OP_QUERY_VPORT_STATE             = 0x750,
 	MLX5_CMD_OP_MODIFY_VPORT_STATE            = 0x751,
 	MLX5_CMD_OP_QUERY_ESW_VPORT_CONTEXT       = 0x752,
 	MLX5_CMD_OP_MODIFY_ESW_VPORT_CONTEXT      = 0x753,
 	MLX5_CMD_OP_QUERY_NIC_VPORT_CONTEXT       = 0x754,
 	MLX5_CMD_OP_MODIFY_NIC_VPORT_CONTEXT      = 0x755,
 	MLX5_CMD_OP_QUERY_ROCE_ADDRESS            = 0x760,
 	MLX5_CMD_OP_SET_ROCE_ADDRESS              = 0x761,
 	MLX5_CMD_OP_QUERY_HCA_VPORT_CONTEXT       = 0x762,
 	MLX5_CMD_OP_MODIFY_HCA_VPORT_CONTEXT      = 0x763,
 	MLX5_CMD_OP_QUERY_HCA_VPORT_GID           = 0x764,
 	MLX5_CMD_OP_QUERY_HCA_VPORT_PKEY          = 0x765,
 	MLX5_CMD_OP_QUERY_VPORT_COUNTER           = 0x770,
 	MLX5_CMD_OP_ALLOC_Q_COUNTER               = 0x771,
 	MLX5_CMD_OP_DEALLOC_Q_COUNTER             = 0x772,
 	MLX5_CMD_OP_QUERY_Q_COUNTER               = 0x773,
 	MLX5_CMD_OP_SET_RATE_LIMIT                = 0x780,
 	MLX5_CMD_OP_QUERY_RATE_LIMIT              = 0x781,
 	MLX5_CMD_OP_CREATE_SCHEDULING_ELEMENT     = 0x782,
 	MLX5_CMD_OP_DESTROY_SCHEDULING_ELEMENT    = 0x783,
 	MLX5_CMD_OP_QUERY_SCHEDULING_ELEMENT      = 0x784,
 	MLX5_CMD_OP_MODIFY_SCHEDULING_ELEMENT     = 0x785,
 	MLX5_CMD_OP_CREATE_QOS_PARA_VPORT         = 0x786,
 	MLX5_CMD_OP_DESTROY_QOS_PARA_VPORT        = 0x787,
 	MLX5_CMD_OP_ALLOC_PD                      = 0x800,
 	MLX5_CMD_OP_DEALLOC_PD                    = 0x801,
 	MLX5_CMD_OP_ALLOC_UAR                     = 0x802,
 	MLX5_CMD_OP_DEALLOC_UAR                   = 0x803,
 	MLX5_CMD_OP_CONFIG_INT_MODERATION         = 0x804,
 	MLX5_CMD_OP_ACCESS_REG                    = 0x805,
 	MLX5_CMD_OP_ATTACH_TO_MCG                 = 0x806,
 	MLX5_CMD_OP_DETACH_FROM_MCG               = 0x807,
 	MLX5_CMD_OP_GET_DROPPED_PACKET_LOG        = 0x80a,
 	MLX5_CMD_OP_MAD_IFC                       = 0x50d,
 	MLX5_CMD_OP_QUERY_MAD_DEMUX               = 0x80b,
 	MLX5_CMD_OP_SET_MAD_DEMUX                 = 0x80c,
 	MLX5_CMD_OP_NOP                           = 0x80d,
 	MLX5_CMD_OP_ALLOC_XRCD                    = 0x80e,
 	MLX5_CMD_OP_DEALLOC_XRCD                  = 0x80f,
 	MLX5_CMD_OP_SET_BURST_SIZE                = 0x812,
 	MLX5_CMD_OP_QUERY_BURST_SIZE              = 0x813,
 	MLX5_CMD_OP_ACTIVATE_TRACER               = 0x814,
 	MLX5_CMD_OP_DEACTIVATE_TRACER             = 0x815,
 	MLX5_CMD_OP_ALLOC_TRANSPORT_DOMAIN        = 0x816,
 	MLX5_CMD_OP_DEALLOC_TRANSPORT_DOMAIN      = 0x817,
 	MLX5_CMD_OP_SET_DIAGNOSTICS               = 0x820,
 	MLX5_CMD_OP_QUERY_DIAGNOSTICS             = 0x821,
 	MLX5_CMD_OP_QUERY_CONG_STATUS             = 0x822,
 	MLX5_CMD_OP_MODIFY_CONG_STATUS            = 0x823,
 	MLX5_CMD_OP_QUERY_CONG_PARAMS             = 0x824,
 	MLX5_CMD_OP_MODIFY_CONG_PARAMS            = 0x825,
 	MLX5_CMD_OP_QUERY_CONG_STATISTICS         = 0x826,
 	MLX5_CMD_OP_ADD_VXLAN_UDP_DPORT           = 0x827,
 	MLX5_CMD_OP_DELETE_VXLAN_UDP_DPORT        = 0x828,
 	MLX5_CMD_OP_SET_L2_TABLE_ENTRY            = 0x829,
 	MLX5_CMD_OP_QUERY_L2_TABLE_ENTRY          = 0x82a,
 	MLX5_CMD_OP_DELETE_L2_TABLE_ENTRY         = 0x82b,
 	MLX5_CMD_OP_SET_WOL_ROL                   = 0x830,
 	MLX5_CMD_OP_QUERY_WOL_ROL                 = 0x831,
 	MLX5_CMD_OP_CREATE_LAG                    = 0x840,
 	MLX5_CMD_OP_MODIFY_LAG                    = 0x841,
 	MLX5_CMD_OP_QUERY_LAG                     = 0x842,
 	MLX5_CMD_OP_DESTROY_LAG                   = 0x843,
 	MLX5_CMD_OP_CREATE_VPORT_LAG              = 0x844,
 	MLX5_CMD_OP_DESTROY_VPORT_LAG             = 0x845,
 	MLX5_CMD_OP_CREATE_TIR                    = 0x900,
 	MLX5_CMD_OP_MODIFY_TIR                    = 0x901,
 	MLX5_CMD_OP_DESTROY_TIR                   = 0x902,
 	MLX5_CMD_OP_QUERY_TIR                     = 0x903,
 	MLX5_CMD_OP_CREATE_SQ                     = 0x904,
 	MLX5_CMD_OP_MODIFY_SQ                     = 0x905,
 	MLX5_CMD_OP_DESTROY_SQ                    = 0x906,
 	MLX5_CMD_OP_QUERY_SQ                      = 0x907,
 	MLX5_CMD_OP_CREATE_RQ                     = 0x908,
 	MLX5_CMD_OP_MODIFY_RQ                     = 0x909,
 	MLX5_CMD_OP_DESTROY_RQ                    = 0x90a,
 	MLX5_CMD_OP_QUERY_RQ                      = 0x90b,
 	MLX5_CMD_OP_CREATE_RMP                    = 0x90c,
 	MLX5_CMD_OP_MODIFY_RMP                    = 0x90d,
 	MLX5_CMD_OP_DESTROY_RMP                   = 0x90e,
 	MLX5_CMD_OP_QUERY_RMP                     = 0x90f,
 	MLX5_CMD_OP_SET_DELAY_DROP_PARAMS         = 0x910,
 	MLX5_CMD_OP_QUERY_DELAY_DROP_PARAMS       = 0x911,
 	MLX5_CMD_OP_CREATE_TIS                    = 0x912,
 	MLX5_CMD_OP_MODIFY_TIS                    = 0x913,
 	MLX5_CMD_OP_DESTROY_TIS                   = 0x914,
 	MLX5_CMD_OP_QUERY_TIS                     = 0x915,
 	MLX5_CMD_OP_CREATE_RQT                    = 0x916,
 	MLX5_CMD_OP_MODIFY_RQT                    = 0x917,
 	MLX5_CMD_OP_DESTROY_RQT                   = 0x918,
 	MLX5_CMD_OP_QUERY_RQT                     = 0x919,
 	MLX5_CMD_OP_SET_FLOW_TABLE_ROOT           = 0x92f,
 	MLX5_CMD_OP_CREATE_FLOW_TABLE             = 0x930,
 	MLX5_CMD_OP_DESTROY_FLOW_TABLE            = 0x931,
 	MLX5_CMD_OP_QUERY_FLOW_TABLE              = 0x932,
 	MLX5_CMD_OP_CREATE_FLOW_GROUP             = 0x933,
 	MLX5_CMD_OP_DESTROY_FLOW_GROUP            = 0x934,
 	MLX5_CMD_OP_QUERY_FLOW_GROUP              = 0x935,
 	MLX5_CMD_OP_SET_FLOW_TABLE_ENTRY          = 0x936,
 	MLX5_CMD_OP_QUERY_FLOW_TABLE_ENTRY        = 0x937,
 	MLX5_CMD_OP_DELETE_FLOW_TABLE_ENTRY       = 0x938,
 	MLX5_CMD_OP_ALLOC_FLOW_COUNTER            = 0x939,
 	MLX5_CMD_OP_DEALLOC_FLOW_COUNTER          = 0x93a,
 	MLX5_CMD_OP_QUERY_FLOW_COUNTER            = 0x93b,
 	MLX5_CMD_OP_MODIFY_FLOW_TABLE             = 0x93c,
 	MLX5_CMD_OP_ALLOC_ENCAP_HEADER            = 0x93d,
 	MLX5_CMD_OP_DEALLOC_ENCAP_HEADER          = 0x93e,
 	MLX5_CMD_OP_FPGA_CREATE_QP                = 0x960,
 	MLX5_CMD_OP_FPGA_MODIFY_QP                = 0x961,
 	MLX5_CMD_OP_FPGA_QUERY_QP                 = 0x962,
 	MLX5_CMD_OP_FPGA_DESTROY_QP               = 0x963,
 	MLX5_CMD_OP_FPGA_QUERY_QP_COUNTERS        = 0x964,
 };
 
 enum {
 	MLX5_ICMD_CMDS_OPCODE_ICMD_OPCODE_QUERY_FW_INFO     = 0x8007,
 	MLX5_ICMD_CMDS_OPCODE_ICMD_QUERY_CAPABILITY         = 0x8400,
 	MLX5_ICMD_CMDS_OPCODE_ICMD_ACCESS_REGISTER          = 0x9001,
 	MLX5_ICMD_CMDS_OPCODE_ICMD_QUERY_VIRTUAL_MAC        = 0x9003,
 	MLX5_ICMD_CMDS_OPCODE_ICMD_SET_VIRTUAL_MAC          = 0x9004,
 	MLX5_ICMD_CMDS_OPCODE_ICMD_QUERY_WOL_ROL            = 0x9005,
 	MLX5_ICMD_CMDS_OPCODE_ICMD_SET_WOL_ROL              = 0x9006,
 	MLX5_ICMD_CMDS_OPCODE_ICMD_OCBB_INIT                = 0x9007,
 	MLX5_ICMD_CMDS_OPCODE_ICMD_OCBB_QUERY_HEADER_STATUS = 0x9008,
 	MLX5_ICMD_CMDS_OPCODE_ICMD_OCBB_QUERY_ETOC_STATUS   = 0x9009,
 	MLX5_ICMD_CMDS_OPCODE_ICMD_OCBB_SET_EVENT           = 0x900a,
 	MLX5_ICMD_CMDS_OPCODE_ICMD_OPCODE_INIT_OCSD         = 0xf004
 };
 
 struct mlx5_ifc_flow_table_fields_supported_bits {
 	u8         outer_dmac[0x1];
 	u8         outer_smac[0x1];
 	u8         outer_ether_type[0x1];
 	u8         reserved_0[0x1];
 	u8         outer_first_prio[0x1];
 	u8         outer_first_cfi[0x1];
 	u8         outer_first_vid[0x1];
 	u8         reserved_1[0x1];
 	u8         outer_second_prio[0x1];
 	u8         outer_second_cfi[0x1];
 	u8         outer_second_vid[0x1];
 	u8         outer_ipv6_flow_label[0x1];
 	u8         outer_sip[0x1];
 	u8         outer_dip[0x1];
 	u8         outer_frag[0x1];
 	u8         outer_ip_protocol[0x1];
 	u8         outer_ip_ecn[0x1];
 	u8         outer_ip_dscp[0x1];
 	u8         outer_udp_sport[0x1];
 	u8         outer_udp_dport[0x1];
 	u8         outer_tcp_sport[0x1];
 	u8         outer_tcp_dport[0x1];
 	u8         outer_tcp_flags[0x1];
 	u8         outer_gre_protocol[0x1];
 	u8         outer_gre_key[0x1];
 	u8         outer_vxlan_vni[0x1];
 	u8         outer_geneve_vni[0x1];
 	u8         outer_geneve_oam[0x1];
 	u8         outer_geneve_protocol_type[0x1];
 	u8         outer_geneve_opt_len[0x1];
 	u8         reserved_2[0x1];
 	u8         source_eswitch_port[0x1];
 
 	u8         inner_dmac[0x1];
 	u8         inner_smac[0x1];
 	u8         inner_ether_type[0x1];
 	u8         reserved_3[0x1];
 	u8         inner_first_prio[0x1];
 	u8         inner_first_cfi[0x1];
 	u8         inner_first_vid[0x1];
 	u8         reserved_4[0x1];
 	u8         inner_second_prio[0x1];
 	u8         inner_second_cfi[0x1];
 	u8         inner_second_vid[0x1];
 	u8         inner_ipv6_flow_label[0x1];
 	u8         inner_sip[0x1];
 	u8         inner_dip[0x1];
 	u8         inner_frag[0x1];
 	u8         inner_ip_protocol[0x1];
 	u8         inner_ip_ecn[0x1];
 	u8         inner_ip_dscp[0x1];
 	u8         inner_udp_sport[0x1];
 	u8         inner_udp_dport[0x1];
 	u8         inner_tcp_sport[0x1];
 	u8         inner_tcp_dport[0x1];
 	u8         inner_tcp_flags[0x1];
 	u8         reserved_5[0x9];
 
 	u8         reserved_6[0x1a];
 	u8         bth_dst_qp[0x1];
 	u8         reserved_7[0x4];
 	u8         source_sqn[0x1];
 
 	u8         reserved_8[0x20];
 };
 
 struct mlx5_ifc_eth_discard_cntrs_grp_bits {
 	u8         ingress_general_high[0x20];
 
 	u8         ingress_general_low[0x20];
 
 	u8         ingress_policy_engine_high[0x20];
 
 	u8         ingress_policy_engine_low[0x20];
 
 	u8         ingress_vlan_membership_high[0x20];
 
 	u8         ingress_vlan_membership_low[0x20];
 
 	u8         ingress_tag_frame_type_high[0x20];
 
 	u8         ingress_tag_frame_type_low[0x20];
 
 	u8         egress_vlan_membership_high[0x20];
 
 	u8         egress_vlan_membership_low[0x20];
 
 	u8         loopback_filter_high[0x20];
 
 	u8         loopback_filter_low[0x20];
 
 	u8         egress_general_high[0x20];
 
 	u8         egress_general_low[0x20];
 
 	u8         reserved_at_1c0[0x40];
 
 	u8         egress_hoq_high[0x20];
 
 	u8         egress_hoq_low[0x20];
 
 	u8         port_isolation_high[0x20];
 
 	u8         port_isolation_low[0x20];
 
 	u8         egress_policy_engine_high[0x20];
 
 	u8         egress_policy_engine_low[0x20];
 
 	u8         ingress_tx_link_down_high[0x20];
 
 	u8         ingress_tx_link_down_low[0x20];
 
 	u8         egress_stp_filter_high[0x20];
 
 	u8         egress_stp_filter_low[0x20];
 
 	u8         egress_hoq_stall_high[0x20];
 
 	u8         egress_hoq_stall_low[0x20];
 
 	u8         reserved_at_340[0x440];
 };
 struct mlx5_ifc_flow_table_prop_layout_bits {
 	u8         ft_support[0x1];
 	u8         flow_tag[0x1];
 	u8         flow_counter[0x1];
 	u8         flow_modify_en[0x1];
 	u8         modify_root[0x1];
 	u8         identified_miss_table[0x1];
 	u8         flow_table_modify[0x1];
 	u8         encap[0x1];
 	u8         decap[0x1];
 	u8         reset_root_to_default[0x1];
 	u8         reserved_at_a[0x16];
 
 	u8         reserved_at_20[0x2];
 	u8         log_max_ft_size[0x6];
 	u8         reserved_at_28[0x10];
 	u8         max_ft_level[0x8];
 
 	u8         reserved_at_40[0x20];
 
 	u8         reserved_at_60[0x18];
 	u8         log_max_ft_num[0x8];
 
 	u8         reserved_at_80[0x10];
 	u8         log_max_flow_counter[0x8];
 	u8         log_max_destination[0x8];
 
 	u8         reserved_at_a0[0x18];
 	u8         log_max_flow[0x8];
 
 	u8         reserved_at_c0[0x40];
 
 	struct mlx5_ifc_flow_table_fields_supported_bits ft_field_support;
 
 	struct mlx5_ifc_flow_table_fields_supported_bits ft_field_bitmask_support;
 };
 
 struct mlx5_ifc_odp_per_transport_service_cap_bits {
 	u8         send[0x1];
 	u8         receive[0x1];
 	u8         write[0x1];
 	u8         read[0x1];
 	u8         atomic[0x1];
 	u8         srq_receive[0x1];
 	u8         reserved_0[0x1a];
 };
 
 struct mlx5_ifc_flow_counter_list_bits {
 	u8         reserved_0[0x10];
 	u8         flow_counter_id[0x10];
 
 	u8         reserved_1[0x20];
 };
 
 enum {
 	MLX5_FLOW_CONTEXT_DEST_TYPE_VPORT                    = 0x0,
 	MLX5_FLOW_CONTEXT_DEST_TYPE_FLOW_TABLE               = 0x1,
 	MLX5_FLOW_CONTEXT_DEST_TYPE_TIR                      = 0x2,
 	MLX5_FLOW_CONTEXT_DEST_TYPE_QP                       = 0x3,
 };
 
 struct mlx5_ifc_dest_format_struct_bits {
 	u8         destination_type[0x8];
 	u8         destination_id[0x18];
 
 	u8         reserved_0[0x20];
 };
 
 struct mlx5_ifc_ipv4_layout_bits {
 	u8         reserved_at_0[0x60];
 
 	u8         ipv4[0x20];
 };
 
 struct mlx5_ifc_ipv6_layout_bits {
 	u8         ipv6[16][0x8];
 };
 
 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits {
 	struct mlx5_ifc_ipv6_layout_bits ipv6_layout;
 	struct mlx5_ifc_ipv4_layout_bits ipv4_layout;
 	u8         reserved_at_0[0x80];
 };
 
 struct mlx5_ifc_fte_match_set_lyr_2_4_bits {
 	u8         smac_47_16[0x20];
 
 	u8         smac_15_0[0x10];
 	u8         ethertype[0x10];
 
 	u8         dmac_47_16[0x20];
 
 	u8         dmac_15_0[0x10];
 	u8         first_prio[0x3];
 	u8         first_cfi[0x1];
 	u8         first_vid[0xc];
 
 	u8         ip_protocol[0x8];
 	u8         ip_dscp[0x6];
 	u8         ip_ecn[0x2];
 	u8         cvlan_tag[0x1];
 	u8         svlan_tag[0x1];
 	u8         frag[0x1];
 	u8         reserved_1[0x4];
 	u8         tcp_flags[0x9];
 
 	u8         tcp_sport[0x10];
 	u8         tcp_dport[0x10];
 
 	u8         reserved_2[0x20];
 
 	u8         udp_sport[0x10];
 	u8         udp_dport[0x10];
 
 	union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits src_ipv4_src_ipv6;
 
 	union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits dst_ipv4_dst_ipv6;
 };
 
 struct mlx5_ifc_fte_match_set_misc_bits {
 	u8         reserved_0[0x8];
 	u8         source_sqn[0x18];
 
 	u8         reserved_1[0x10];
 	u8         source_port[0x10];
 
 	u8         outer_second_prio[0x3];
 	u8         outer_second_cfi[0x1];
 	u8         outer_second_vid[0xc];
 	u8         inner_second_prio[0x3];
 	u8         inner_second_cfi[0x1];
 	u8         inner_second_vid[0xc];
 
 	u8         outer_second_vlan_tag[0x1];
 	u8         inner_second_vlan_tag[0x1];
 	u8         reserved_2[0xe];
 	u8         gre_protocol[0x10];
 
 	u8         gre_key_h[0x18];
 	u8         gre_key_l[0x8];
 
 	u8         vxlan_vni[0x18];
 	u8         reserved_3[0x8];
 
 	u8         geneve_vni[0x18];
 	u8         reserved4[0x7];
 	u8         geneve_oam[0x1];
 
 	u8         reserved_5[0xc];
 	u8         outer_ipv6_flow_label[0x14];
 
 	u8         reserved_6[0xc];
 	u8         inner_ipv6_flow_label[0x14];
 
 	u8         reserved_7[0xa];
 	u8         geneve_opt_len[0x6];
 	u8         geneve_protocol_type[0x10];
 
 	u8         reserved_8[0x8];
 	u8         bth_dst_qp[0x18];
 
 	u8         reserved_9[0xa0];
 };
 
 struct mlx5_ifc_cmd_pas_bits {
 	u8         pa_h[0x20];
 
 	u8         pa_l[0x14];
 	u8         reserved_0[0xc];
 };
 
 struct mlx5_ifc_uint64_bits {
 	u8         hi[0x20];
 
 	u8         lo[0x20];
 };
 
 struct mlx5_ifc_application_prio_entry_bits {
 	u8         reserved_0[0x8];
 	u8         priority[0x3];
 	u8         reserved_1[0x2];
 	u8         sel[0x3];
 	u8         protocol_id[0x10];
 };
 
 struct mlx5_ifc_nodnic_ring_doorbell_bits {
 	u8         reserved_0[0x8];
 	u8         ring_pi[0x10];
 	u8         reserved_1[0x8];
 };
 
 enum {
 	MLX5_ADS_STAT_RATE_NO_LIMIT  = 0x0,
 	MLX5_ADS_STAT_RATE_2_5GBPS   = 0x7,
 	MLX5_ADS_STAT_RATE_10GBPS    = 0x8,
 	MLX5_ADS_STAT_RATE_30GBPS    = 0x9,
 	MLX5_ADS_STAT_RATE_5GBPS     = 0xa,
 	MLX5_ADS_STAT_RATE_20GBPS    = 0xb,
 	MLX5_ADS_STAT_RATE_40GBPS    = 0xc,
 	MLX5_ADS_STAT_RATE_60GBPS    = 0xd,
 	MLX5_ADS_STAT_RATE_80GBPS    = 0xe,
 	MLX5_ADS_STAT_RATE_120GBPS   = 0xf,
 };
 
 struct mlx5_ifc_ads_bits {
 	u8         fl[0x1];
 	u8         free_ar[0x1];
 	u8         reserved_0[0xe];
 	u8         pkey_index[0x10];
 
 	u8         reserved_1[0x8];
 	u8         grh[0x1];
 	u8         mlid[0x7];
 	u8         rlid[0x10];
 
 	u8         ack_timeout[0x5];
 	u8         reserved_2[0x3];
 	u8         src_addr_index[0x8];
 	u8         log_rtm[0x4];
 	u8         stat_rate[0x4];
 	u8         hop_limit[0x8];
 
 	u8         reserved_3[0x4];
 	u8         tclass[0x8];
 	u8         flow_label[0x14];
 
 	u8         rgid_rip[16][0x8];
 
 	u8         reserved_4[0x4];
 	u8         f_dscp[0x1];
 	u8         f_ecn[0x1];
 	u8         reserved_5[0x1];
 	u8         f_eth_prio[0x1];
 	u8         ecn[0x2];
 	u8         dscp[0x6];
 	u8         udp_sport[0x10];
 
 	u8         dei_cfi[0x1];
 	u8         eth_prio[0x3];
 	u8         sl[0x4];
 	u8         port[0x8];
 	u8         rmac_47_32[0x10];
 
 	u8         rmac_31_0[0x20];
 };
 
 struct mlx5_ifc_diagnostic_counter_cap_bits {
 	u8         sync[0x1];
 	u8         reserved_0[0xf];
 	u8         counter_id[0x10];
 };
 
 struct mlx5_ifc_debug_cap_bits {
 	u8         reserved_0[0x18];
 	u8         log_max_samples[0x8];
 
 	u8         single[0x1];
 	u8         repetitive[0x1];
 	u8         health_mon_rx_activity[0x1];
 	u8         reserved_1[0x15];
 	u8         log_min_sample_period[0x8];
 
 	u8         reserved_2[0x1c0];
 
 	struct mlx5_ifc_diagnostic_counter_cap_bits diagnostic_counter[0x1f0];
 };
 
 struct mlx5_ifc_qos_cap_bits {
 	u8         packet_pacing[0x1];
 	u8         esw_scheduling[0x1];
 	u8         esw_bw_share[0x1];
 	u8         esw_rate_limit[0x1];
 	u8         hll[0x1];
 	u8         packet_pacing_burst_bound[0x1];
 	u8         reserved_at_6[0x1a];
 
 	u8         reserved_at_20[0x20];
 
 	u8         packet_pacing_max_rate[0x20];
 
 	u8         packet_pacing_min_rate[0x20];
 
 	u8         reserved_at_80[0x10];
 	u8         packet_pacing_rate_table_size[0x10];
 
 	u8         esw_element_type[0x10];
 	u8         esw_tsar_type[0x10];
 
 	u8         reserved_at_c0[0x10];
 	u8         max_qos_para_vport[0x10];
 
 	u8         max_tsar_bw_share[0x20];
 
 	u8         reserved_at_100[0x700];
 };
 
 struct mlx5_ifc_snapshot_cap_bits {
 	u8         reserved_0[0x1d];
 	u8         suspend_qp_uc[0x1];
 	u8         suspend_qp_ud[0x1];
 	u8         suspend_qp_rc[0x1];
 
 	u8         reserved_1[0x1c];
 	u8         restore_pd[0x1];
 	u8         restore_uar[0x1];
 	u8         restore_mkey[0x1];
 	u8         restore_qp[0x1];
 
 	u8         reserved_2[0x1e];
 	u8         named_mkey[0x1];
 	u8         named_qp[0x1];
 
 	u8         reserved_3[0x7a0];
 };
 
 struct mlx5_ifc_e_switch_cap_bits {
 	u8         vport_svlan_strip[0x1];
 	u8         vport_cvlan_strip[0x1];
 	u8         vport_svlan_insert[0x1];
 	u8         vport_cvlan_insert_if_not_exist[0x1];
 	u8         vport_cvlan_insert_overwrite[0x1];
 
 	u8         reserved_0[0x19];
 
 	u8         nic_vport_node_guid_modify[0x1];
 	u8         nic_vport_port_guid_modify[0x1];
 
 	u8         reserved_1[0x7e0];
 };
 
 struct mlx5_ifc_flow_table_eswitch_cap_bits {
 	u8         reserved_0[0x200];
 
 	struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_esw_fdb;
 
 	struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_ingress;
 
 	struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_egress;
 
 	u8         reserved_1[0x7800];
 };
 
 struct mlx5_ifc_flow_table_nic_cap_bits {
 	u8         nic_rx_multi_path_tirs[0x1];
 	u8         nic_rx_multi_path_tirs_fts[0x1];
 	u8         allow_sniffer_and_nic_rx_shared_tir[0x1];
 	u8         reserved_at_3[0x1fd];
 
 	struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive;
 
 	struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive_rdma;
 
 	struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive_sniffer;
 
 	struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit;
 
 	struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit_rdma;
 
 	struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit_sniffer;
 
 	u8         reserved_1[0x7200];
 };
 
 struct mlx5_ifc_per_protocol_networking_offload_caps_bits {
 	u8         csum_cap[0x1];
 	u8         vlan_cap[0x1];
 	u8         lro_cap[0x1];
 	u8         lro_psh_flag[0x1];
 	u8         lro_time_stamp[0x1];
 	u8         lro_max_msg_sz_mode[0x2];
 	u8         wqe_vlan_insert[0x1];
 	u8         self_lb_en_modifiable[0x1];
 	u8         self_lb_mc[0x1];
 	u8         self_lb_uc[0x1];
 	u8         max_lso_cap[0x5];
 	u8         multi_pkt_send_wqe[0x2];
 	u8         wqe_inline_mode[0x2];
 	u8         rss_ind_tbl_cap[0x4];
 	u8         scatter_fcs[0x1];
 	u8         reserved_1[0x2];
 	u8         tunnel_lso_const_out_ip_id[0x1];
 	u8         tunnel_lro_gre[0x1];
 	u8         tunnel_lro_vxlan[0x1];
 	u8         tunnel_statless_gre[0x1];
 	u8         tunnel_stateless_vxlan[0x1];
 
 	u8         swp[0x1];
 	u8         swp_csum[0x1];
 	u8         swp_lso[0x1];
 	u8         reserved_2[0x1b];
 	u8         max_geneve_opt_len[0x1];
 	u8         tunnel_stateless_geneve_rx[0x1];
 
 	u8         reserved_3[0x10];
 	u8         lro_min_mss_size[0x10];
 
 	u8         reserved_4[0x120];
 
 	u8         lro_timer_supported_periods[4][0x20];
 
 	u8         reserved_5[0x600];
 };
 
 enum {
 	MLX5_ROCE_CAP_L3_TYPE_GRH   = 0x1,
 	MLX5_ROCE_CAP_L3_TYPE_IPV4  = 0x2,
 	MLX5_ROCE_CAP_L3_TYPE_IPV6  = 0x4,
 };
 
 struct mlx5_ifc_roce_cap_bits {
 	u8         roce_apm[0x1];
 	u8         rts2rts_primary_eth_prio[0x1];
 	u8         roce_rx_allow_untagged[0x1];
 	u8         rts2rts_src_addr_index_for_vlan_valid_vlan_id[0x1];
 
 	u8         reserved_0[0x1c];
 
 	u8         reserved_1[0x60];
 
 	u8         reserved_2[0xc];
 	u8         l3_type[0x4];
 	u8         reserved_3[0x8];
 	u8         roce_version[0x8];
 
 	u8         reserved_4[0x10];
 	u8         r_roce_dest_udp_port[0x10];
 
 	u8         r_roce_max_src_udp_port[0x10];
 	u8         r_roce_min_src_udp_port[0x10];
 
 	u8         reserved_5[0x10];
 	u8         roce_address_table_size[0x10];
 
 	u8         reserved_6[0x700];
 };
 
 enum {
 	MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_1_BYTE     = 0x1,
 	MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_2_BYTES    = 0x2,
 	MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_4_BYTES    = 0x4,
 	MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_8_BYTES    = 0x8,
 	MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_16_BYTES   = 0x10,
 	MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_32_BYTES   = 0x20,
 	MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_64_BYTES   = 0x40,
 	MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_128_BYTES  = 0x80,
 	MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_256_BYTES  = 0x100,
 };
 
 enum {
 	MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_1_BYTE     = 0x1,
 	MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_2_BYTES    = 0x2,
 	MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_4_BYTES    = 0x4,
 	MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_8_BYTES    = 0x8,
 	MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_16_BYTES   = 0x10,
 	MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_32_BYTES   = 0x20,
 	MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_64_BYTES   = 0x40,
 	MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_128_BYTES  = 0x80,
 	MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_256_BYTES  = 0x100,
 };
 
 struct mlx5_ifc_atomic_caps_bits {
 	u8         reserved_0[0x40];
 
 	u8         atomic_req_8B_endianess_mode[0x2];
 	u8         reserved_1[0x4];
 	u8         supported_atomic_req_8B_endianess_mode_1[0x1];
 
 	u8         reserved_2[0x19];
 
 	u8         reserved_3[0x20];
 
 	u8         reserved_4[0x10];
 	u8         atomic_operations[0x10];
 
 	u8         reserved_5[0x10];
 	u8         atomic_size_qp[0x10];
 
 	u8         reserved_6[0x10];
 	u8         atomic_size_dc[0x10];
 
 	u8         reserved_7[0x720];
 };
 
 struct mlx5_ifc_odp_cap_bits {
 	u8         reserved_0[0x40];
 
 	u8         sig[0x1];
 	u8         reserved_1[0x1f];
 
 	u8         reserved_2[0x20];
 
 	struct mlx5_ifc_odp_per_transport_service_cap_bits rc_odp_caps;
 
 	struct mlx5_ifc_odp_per_transport_service_cap_bits uc_odp_caps;
 
 	struct mlx5_ifc_odp_per_transport_service_cap_bits ud_odp_caps;
 
 	struct mlx5_ifc_odp_per_transport_service_cap_bits xrc_odp_caps;
 
 	struct mlx5_ifc_odp_per_transport_service_cap_bits dc_odp_caps;
 
 	u8         reserved_3[0x6e0];
 };
 
 enum {
 	MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_8_GID_ENTRIES    = 0x0,
 	MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_16_GID_ENTRIES   = 0x1,
 	MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_32_GID_ENTRIES   = 0x2,
 	MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_64_GID_ENTRIES   = 0x3,
 	MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_128_GID_ENTRIES  = 0x4,
 };
 
 enum {
 	MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_128_ENTRIES  = 0x0,
 	MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_256_ENTRIES  = 0x1,
 	MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_512_ENTRIES  = 0x2,
 	MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_1K_ENTRIES   = 0x3,
 	MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_2K_ENTRIES   = 0x4,
 	MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_4K_ENTRIES   = 0x5,
 };
 
 enum {
 	MLX5_CMD_HCA_CAP_PORT_TYPE_IB        = 0x0,
 	MLX5_CMD_HCA_CAP_PORT_TYPE_ETHERNET  = 0x1,
 };
 
 enum {
 	MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_DISABLED       = 0x0,
 	MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_INITIAL_STATE  = 0x1,
 	MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_ENABLED        = 0x3,
 };
 
 struct mlx5_ifc_cmd_hca_cap_bits {
 	u8         reserved_0[0x80];
 
 	u8         log_max_srq_sz[0x8];
 	u8         log_max_qp_sz[0x8];
 	u8         reserved_1[0xb];
 	u8         log_max_qp[0x5];
 
 	u8         reserved_2[0xb];
 	u8         log_max_srq[0x5];
 	u8         reserved_3[0x10];
 
 	u8         reserved_4[0x8];
 	u8         log_max_cq_sz[0x8];
 	u8         reserved_5[0xb];
 	u8         log_max_cq[0x5];
 
 	u8         log_max_eq_sz[0x8];
 	u8         relaxed_ordering_write[1];
 	u8         reserved_6[0x1];
 	u8         log_max_mkey[0x6];
 	u8         reserved_7[0xc];
 	u8         log_max_eq[0x4];
 
 	u8         max_indirection[0x8];
 	u8         reserved_8[0x1];
 	u8         log_max_mrw_sz[0x7];
 	u8	   force_teardown[0x1];
 	u8         reserved_9[0x1];
 	u8         log_max_bsf_list_size[0x6];
 	u8         reserved_10[0x2];
 	u8         log_max_klm_list_size[0x6];
 
 	u8         reserved_11[0xa];
 	u8         log_max_ra_req_dc[0x6];
 	u8         reserved_12[0xa];
 	u8         log_max_ra_res_dc[0x6];
 
 	u8         reserved_13[0xa];
 	u8         log_max_ra_req_qp[0x6];
 	u8         reserved_14[0xa];
 	u8         log_max_ra_res_qp[0x6];
 
 	u8         pad_cap[0x1];
 	u8         cc_query_allowed[0x1];
 	u8         cc_modify_allowed[0x1];
 	u8         start_pad[0x1];
 	u8         cache_line_128byte[0x1];
 	u8         reserved_at_165[0xa];
 	u8         qcam_reg[0x1];
 	u8         gid_table_size[0x10];
 
 	u8         out_of_seq_cnt[0x1];
 	u8         vport_counters[0x1];
 	u8         retransmission_q_counters[0x1];
 	u8         debug[0x1];
 	u8         modify_rq_counters_set_id[0x1];
 	u8         rq_delay_drop[0x1];
 	u8         max_qp_cnt[0xa];
 	u8         pkey_table_size[0x10];
 
 	u8         vport_group_manager[0x1];
 	u8         vhca_group_manager[0x1];
 	u8         ib_virt[0x1];
 	u8         eth_virt[0x1];
 	u8         reserved_17[0x1];
 	u8         ets[0x1];
 	u8         nic_flow_table[0x1];
 	u8         eswitch_flow_table[0x1];
 	u8         reserved_18[0x3];
 	u8         local_ca_ack_delay[0x5];
 	u8         port_module_event[0x1];
 	u8         reserved_19[0x5];
 	u8         port_type[0x2];
 	u8         num_ports[0x8];
 
 	u8         snapshot[0x1];
 	u8         reserved_20[0x2];
 	u8         log_max_msg[0x5];
 	u8         reserved_21[0x4];
 	u8         max_tc[0x4];
 	u8         temp_warn_event[0x1];
 	u8         dcbx[0x1];
 	u8         general_notification_event[0x1];
 	u8         reserved_at_1d3[0x2];
 	u8         fpga[0x1];
 	u8         rol_s[0x1];
 	u8         rol_g[0x1];
 	u8         reserved_23[0x1];
 	u8         wol_s[0x1];
 	u8         wol_g[0x1];
 	u8         wol_a[0x1];
 	u8         wol_b[0x1];
 	u8         wol_m[0x1];
 	u8         wol_u[0x1];
 	u8         wol_p[0x1];
 
 	u8         stat_rate_support[0x10];
 	u8         reserved_24[0xc];
 	u8         cqe_version[0x4];
 
 	u8         compact_address_vector[0x1];
 	u8         striding_rq[0x1];
 	u8         reserved_25[0x1];
 	u8         ipoib_enhanced_offloads[0x1];
 	u8         ipoib_ipoib_offloads[0x1];
 	u8         reserved_26[0x8];
 	u8         dc_connect_qp[0x1];
 	u8         dc_cnak_trace[0x1];
 	u8         drain_sigerr[0x1];
 	u8         cmdif_checksum[0x2];
 	u8         sigerr_cqe[0x1];
 	u8         reserved_27[0x1];
 	u8         wq_signature[0x1];
 	u8         sctr_data_cqe[0x1];
 	u8         reserved_28[0x1];
 	u8         sho[0x1];
 	u8         tph[0x1];
 	u8         rf[0x1];
 	u8         dct[0x1];
 	u8         qos[0x1];
 	u8         eth_net_offloads[0x1];
 	u8         roce[0x1];
 	u8         atomic[0x1];
 	u8         reserved_30[0x1];
 
 	u8         cq_oi[0x1];
 	u8         cq_resize[0x1];
 	u8         cq_moderation[0x1];
 	u8         cq_period_mode_modify[0x1];
 	u8         cq_invalidate[0x1];
 	u8         reserved_at_225[0x1];
 	u8         cq_eq_remap[0x1];
 	u8         pg[0x1];
 	u8         block_lb_mc[0x1];
 	u8         exponential_backoff[0x1];
 	u8         scqe_break_moderation[0x1];
 	u8         cq_period_start_from_cqe[0x1];
 	u8         cd[0x1];
 	u8         atm[0x1];
 	u8         apm[0x1];
 	u8	   imaicl[0x1];
 	u8         reserved_32[0x6];
 	u8         qkv[0x1];
 	u8         pkv[0x1];
 	u8	   set_deth_sqpn[0x1];
 	u8         reserved_33[0x3];
 	u8         xrc[0x1];
 	u8         ud[0x1];
 	u8         uc[0x1];
 	u8         rc[0x1];
 
 	u8         reserved_34[0xa];
 	u8         uar_sz[0x6];
 	u8         reserved_35[0x8];
 	u8         log_pg_sz[0x8];
 
 	u8         bf[0x1];
 	u8         driver_version[0x1];
 	u8         pad_tx_eth_packet[0x1];
 	u8         reserved_36[0x8];
 	u8         log_bf_reg_size[0x5];
 	u8         reserved_37[0x10];
 
 	u8         num_of_diagnostic_counters[0x10];
 	u8         max_wqe_sz_sq[0x10];
 
 	u8         reserved_38[0x10];
 	u8         max_wqe_sz_rq[0x10];
 
 	u8         reserved_39[0x10];
 	u8         max_wqe_sz_sq_dc[0x10];
 
 	u8         reserved_40[0x7];
 	u8         max_qp_mcg[0x19];
 
 	u8         reserved_41[0x18];
 	u8         log_max_mcg[0x8];
 
 	u8         reserved_42[0x3];
 	u8         log_max_transport_domain[0x5];
 	u8         reserved_43[0x3];
 	u8         log_max_pd[0x5];
 	u8         reserved_44[0xb];
 	u8         log_max_xrcd[0x5];
 
 	u8         reserved_45[0x10];
 	u8         max_flow_counter[0x10];
 
 	u8         reserved_46[0x3];
 	u8         log_max_rq[0x5];
 	u8         reserved_47[0x3];
 	u8         log_max_sq[0x5];
 	u8         reserved_48[0x3];
 	u8         log_max_tir[0x5];
 	u8         reserved_49[0x3];
 	u8         log_max_tis[0x5];
 
 	u8         basic_cyclic_rcv_wqe[0x1];
 	u8         reserved_50[0x2];
 	u8         log_max_rmp[0x5];
 	u8         reserved_51[0x3];
 	u8         log_max_rqt[0x5];
 	u8         reserved_52[0x3];
 	u8         log_max_rqt_size[0x5];
 	u8         reserved_53[0x3];
 	u8         log_max_tis_per_sq[0x5];
 
 	u8         reserved_54[0x3];
 	u8         log_max_stride_sz_rq[0x5];
 	u8         reserved_55[0x3];
 	u8         log_min_stride_sz_rq[0x5];
 	u8         reserved_56[0x3];
 	u8         log_max_stride_sz_sq[0x5];
 	u8         reserved_57[0x3];
 	u8         log_min_stride_sz_sq[0x5];
 
 	u8         reserved_58[0x1b];
 	u8         log_max_wq_sz[0x5];
 
 	u8         nic_vport_change_event[0x1];
 	u8         disable_local_lb[0x1];
 	u8         reserved_59[0x9];
 	u8         log_max_vlan_list[0x5];
 	u8         reserved_60[0x3];
 	u8         log_max_current_mc_list[0x5];
 	u8         reserved_61[0x3];
 	u8         log_max_current_uc_list[0x5];
 
 	u8         reserved_62[0x80];
 
 	u8         reserved_63[0x3];
 	u8         log_max_l2_table[0x5];
 	u8         reserved_64[0x8];
 	u8         log_uar_page_sz[0x10];
 
 	u8         reserved_65[0x20];
 
 	u8         device_frequency_mhz[0x20];
 
 	u8         device_frequency_khz[0x20];
 
 	u8         reserved_66[0x80];
 
 	u8         log_max_atomic_size_qp[0x8];
 	u8         reserved_67[0x10];
 	u8         log_max_atomic_size_dc[0x8];
 
 	u8         reserved_68[0x1f];
 	u8         cqe_compression[0x1];
 
 	u8         cqe_compression_timeout[0x10];
 	u8         cqe_compression_max_num[0x10];
 
 	u8         reserved_69[0x220];
 };
 
 enum mlx5_flow_destination_type {
 	MLX5_FLOW_DESTINATION_TYPE_VPORT	= 0x0,
 	MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE	= 0x1,
 	MLX5_FLOW_DESTINATION_TYPE_TIR		= 0x2,
 };
 
 union mlx5_ifc_dest_format_struct_flow_counter_list_auto_bits {
 	struct mlx5_ifc_dest_format_struct_bits dest_format_struct;
 	struct mlx5_ifc_flow_counter_list_bits flow_counter_list;
 	u8         reserved_0[0x40];
 };
 
 struct mlx5_ifc_fte_match_param_bits {
 	struct mlx5_ifc_fte_match_set_lyr_2_4_bits outer_headers;
 
 	struct mlx5_ifc_fte_match_set_misc_bits misc_parameters;
 
 	struct mlx5_ifc_fte_match_set_lyr_2_4_bits inner_headers;
 
 	u8         reserved_0[0xa00];
 };
 
 enum {
 	MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_SRC_IP     = 0x0,
 	MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_DST_IP     = 0x1,
 	MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_SPORT   = 0x2,
 	MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_DPORT   = 0x3,
 	MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_IPSEC_SPI  = 0x4,
 };
 
 struct mlx5_ifc_rx_hash_field_select_bits {
 	u8         l3_prot_type[0x1];
 	u8         l4_prot_type[0x1];
 	u8         selected_fields[0x1e];
 };
 
 enum {
 	MLX5_WQ_TYPE_LINKED_LIST                 = 0x0,
 	MLX5_WQ_TYPE_CYCLIC                      = 0x1,
 	MLX5_WQ_TYPE_STRQ_LINKED_LIST            = 0x2,
 	MLX5_WQ_TYPE_STRQ_CYCLIC                 = 0x3,
 };
 
 enum rq_type {
 	RQ_TYPE_NONE,
 	RQ_TYPE_STRIDE,
 };
 
 enum {
 	MLX5_WQ_END_PAD_MODE_NONE               = 0x0,
 	MLX5_WQ_END_PAD_MODE_ALIGN              = 0x1,
 };
 
 struct mlx5_ifc_wq_bits {
 	u8         wq_type[0x4];
 	u8         wq_signature[0x1];
 	u8         end_padding_mode[0x2];
 	u8         cd_slave[0x1];
 	u8         reserved_0[0x18];
 
 	u8         hds_skip_first_sge[0x1];
 	u8         log2_hds_buf_size[0x3];
 	u8         reserved_1[0x7];
 	u8         page_offset[0x5];
 	u8         lwm[0x10];
 
 	u8         reserved_2[0x8];
 	u8         pd[0x18];
 
 	u8         reserved_3[0x8];
 	u8         uar_page[0x18];
 
 	u8         dbr_addr[0x40];
 
 	u8         hw_counter[0x20];
 
 	u8         sw_counter[0x20];
 
 	u8         reserved_4[0xc];
 	u8         log_wq_stride[0x4];
 	u8         reserved_5[0x3];
 	u8         log_wq_pg_sz[0x5];
 	u8         reserved_6[0x3];
 	u8         log_wq_sz[0x5];
 
 	u8         reserved_7[0x15];
 	u8         single_wqe_log_num_of_strides[0x3];
 	u8         two_byte_shift_en[0x1];
 	u8         reserved_8[0x4];
 	u8         single_stride_log_num_of_bytes[0x3];
 
 	u8         reserved_9[0x4c0];
 
 	struct mlx5_ifc_cmd_pas_bits pas[0];
 };
 
 struct mlx5_ifc_rq_num_bits {
 	u8         reserved_0[0x8];
 	u8         rq_num[0x18];
 };
 
 struct mlx5_ifc_mac_address_layout_bits {
 	u8         reserved_0[0x10];
 	u8         mac_addr_47_32[0x10];
 
 	u8         mac_addr_31_0[0x20];
 };
 
 struct mlx5_ifc_cong_control_r_roce_ecn_np_bits {
 	u8         reserved_0[0xa0];
 
 	u8         min_time_between_cnps[0x20];
 
 	u8         reserved_1[0x12];
 	u8         cnp_dscp[0x6];
 	u8         reserved_2[0x4];
 	u8         cnp_prio_mode[0x1];
 	u8         cnp_802p_prio[0x3];
 
 	u8         reserved_3[0x720];
 };
 
 struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits {
 	u8         reserved_0[0x60];
 
 	u8         reserved_1[0x4];
 	u8         clamp_tgt_rate[0x1];
 	u8         reserved_2[0x3];
 	u8         clamp_tgt_rate_after_time_inc[0x1];
 	u8         reserved_3[0x17];
 
 	u8         reserved_4[0x20];
 
 	u8         rpg_time_reset[0x20];
 
 	u8         rpg_byte_reset[0x20];
 
 	u8         rpg_threshold[0x20];
 
 	u8         rpg_max_rate[0x20];
 
 	u8         rpg_ai_rate[0x20];
 
 	u8         rpg_hai_rate[0x20];
 
 	u8         rpg_gd[0x20];
 
 	u8         rpg_min_dec_fac[0x20];
 
 	u8         rpg_min_rate[0x20];
 
 	u8         reserved_5[0xe0];
 
 	u8         rate_to_set_on_first_cnp[0x20];
 
 	u8         dce_tcp_g[0x20];
 
 	u8         dce_tcp_rtt[0x20];
 
 	u8         rate_reduce_monitor_period[0x20];
 
 	u8         reserved_6[0x20];
 
 	u8         initial_alpha_value[0x20];
 
 	u8         reserved_7[0x4a0];
 };
 
 struct mlx5_ifc_cong_control_802_1qau_rp_bits {
 	u8         reserved_0[0x80];
 
 	u8         rppp_max_rps[0x20];
 
 	u8         rpg_time_reset[0x20];
 
 	u8         rpg_byte_reset[0x20];
 
 	u8         rpg_threshold[0x20];
 
 	u8         rpg_max_rate[0x20];
 
 	u8         rpg_ai_rate[0x20];
 
 	u8         rpg_hai_rate[0x20];
 
 	u8         rpg_gd[0x20];
 
 	u8         rpg_min_dec_fac[0x20];
 
 	u8         rpg_min_rate[0x20];
 
 	u8         reserved_1[0x640];
 };
 
 enum {
 	MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_CQ_SIZE    = 0x1,
 	MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_PAGE_OFFSET    = 0x2,
 	MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_PAGE_SIZE  = 0x4,
 };
 
 struct mlx5_ifc_resize_field_select_bits {
 	u8         resize_field_select[0x20];
 };
 
 enum {
 	MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_PERIOD     = 0x1,
 	MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_MAX_COUNT  = 0x2,
 	MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_OI            = 0x4,
 	MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_C_EQN         = 0x8,
 	MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_PERIOD_MODE  = 0x10,
 	MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_STATUS          = 0x20,
 };
 
 struct mlx5_ifc_modify_field_select_bits {
 	u8         modify_field_select[0x20];
 };
 
 struct mlx5_ifc_field_select_r_roce_np_bits {
 	u8         field_select_r_roce_np[0x20];
 };
 
 enum {
 	MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_CLAMP_TGT_RATE                 = 0x2,
 	MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_CLAMP_TGT_RATE_AFTER_TIME_INC  = 0x4,
 	MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_RPG_TIME_RESET                 = 0x8,
 	MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_RPG_BYTE_RESET                 = 0x10,
 	MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_RPG_THRESHOLD                  = 0x20,
 	MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_RPG_MAX_RATE                   = 0x40,
 	MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_RPG_AI_RATE                    = 0x80,
 	MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_RPG_HAI_RATE                   = 0x100,
 	MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_RPG_MIN_DEC_FAC                = 0x200,
 	MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_RPG_MIN_RATE                   = 0x400,
 	MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_RATE_TO_SET_ON_FIRST_CNP       = 0x800,
 	MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_DCE_TCP_G                      = 0x1000,
 	MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_DCE_TCP_RTT                    = 0x2000,
 	MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_RATE_REDUCE_MONITOR_PERIOD     = 0x4000,
 	MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_INITIAL_ALPHA_VALUE            = 0x8000,
 };
 
 struct mlx5_ifc_field_select_r_roce_rp_bits {
 	u8         field_select_r_roce_rp[0x20];
 };
 
 enum {
 	MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPPP_MAX_RPS     = 0x4,
 	MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_TIME_RESET   = 0x8,
 	MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_BYTE_RESET   = 0x10,
 	MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_THRESHOLD    = 0x20,
 	MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MAX_RATE     = 0x40,
 	MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_AI_RATE      = 0x80,
 	MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_HAI_RATE     = 0x100,
 	MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_GD           = 0x200,
 	MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_DEC_FAC  = 0x400,
 	MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_RATE     = 0x800,
 };
 
 struct mlx5_ifc_field_select_802_1qau_rp_bits {
 	u8         field_select_8021qaurp[0x20];
 };
 
 struct mlx5_ifc_pptb_reg_bits {
 	u8         reserved_0[0x2];
 	u8         mm[0x2];
 	u8         reserved_1[0x4];
 	u8         local_port[0x8];
 	u8         reserved_2[0x6];
 	u8         cm[0x1];
 	u8         um[0x1];
 	u8         pm[0x8];
 
 	u8         prio7buff[0x4];
 	u8         prio6buff[0x4];
 	u8         prio5buff[0x4];
 	u8         prio4buff[0x4];
 	u8         prio3buff[0x4];
 	u8         prio2buff[0x4];
 	u8         prio1buff[0x4];
 	u8         prio0buff[0x4];
 
 	u8         pm_msb[0x8];
 	u8         reserved_3[0x10];
 	u8         ctrl_buff[0x4];
 	u8         untagged_buff[0x4];
 };
 
 struct mlx5_ifc_dcbx_app_reg_bits {
 	u8         reserved_0[0x8];
 	u8         port_number[0x8];
 	u8         reserved_1[0x10];
 
 	u8         reserved_2[0x1a];
 	u8         num_app_prio[0x6];
 
 	u8         reserved_3[0x40];
 
 	struct mlx5_ifc_application_prio_entry_bits app_prio[0];
 };
 
 struct mlx5_ifc_dcbx_param_reg_bits {
 	u8         dcbx_cee_cap[0x1];
 	u8         dcbx_ieee_cap[0x1];
 	u8         dcbx_standby_cap[0x1];
 	u8         reserved_0[0x5];
 	u8         port_number[0x8];
 	u8         reserved_1[0xa];
 	u8         max_application_table_size[0x6];
 
 	u8         reserved_2[0x15];
 	u8         version_oper[0x3];
 	u8         reserved_3[0x5];
 	u8         version_admin[0x3];
 
 	u8         willing_admin[0x1];
 	u8         reserved_4[0x3];
 	u8         pfc_cap_oper[0x4];
 	u8         reserved_5[0x4];
 	u8         pfc_cap_admin[0x4];
 	u8         reserved_6[0x4];
 	u8         num_of_tc_oper[0x4];
 	u8         reserved_7[0x4];
 	u8         num_of_tc_admin[0x4];
 
 	u8         remote_willing[0x1];
 	u8         reserved_8[0x3];
 	u8         remote_pfc_cap[0x4];
 	u8         reserved_9[0x14];
 	u8         remote_num_of_tc[0x4];
 
 	u8         reserved_10[0x18];
 	u8         error[0x8];
 
 	u8         reserved_11[0x160];
 };
 
 struct mlx5_ifc_qhll_bits {
 	u8         reserved_at_0[0x8];
 	u8         local_port[0x8];
 	u8         reserved_at_10[0x10];
 
 	u8         reserved_at_20[0x1b];
 	u8         hll_time[0x5];
 
 	u8         stall_en[0x1];
 	u8         reserved_at_41[0x1c];
 	u8         stall_cnt[0x3];
 };
 
 struct mlx5_ifc_qetcr_reg_bits {
 	u8         operation_type[0x2];
 	u8         cap_local_admin[0x1];
 	u8         cap_remote_admin[0x1];
 	u8         reserved_0[0x4];
 	u8         port_number[0x8];
 	u8         reserved_1[0x10];
 
 	u8         reserved_2[0x20];
 
 	u8         tc[8][0x40];
 
 	u8         global_configuration[0x40];
 };
 
 struct mlx5_ifc_nodnic_ring_config_reg_bits {
 	u8         queue_address_63_32[0x20];
 
 	u8         queue_address_31_12[0x14];
 	u8         reserved_0[0x6];
 	u8         log_size[0x6];
 
 	struct mlx5_ifc_nodnic_ring_doorbell_bits doorbell;
 
 	u8         reserved_1[0x8];
 	u8         queue_number[0x18];
 
 	u8         q_key[0x20];
 
 	u8         reserved_2[0x10];
 	u8         pkey_index[0x10];
 
 	u8         reserved_3[0x40];
 };
 
 struct mlx5_ifc_nodnic_cq_arming_word_bits {
 	u8         reserved_0[0x8];
 	u8         cq_ci[0x10];
 	u8         reserved_1[0x8];
 };
 
 enum {
 	MLX5_NODNIC_EVENT_WORD_LINK_TYPE_INFINIBAND  = 0x0,
 	MLX5_NODNIC_EVENT_WORD_LINK_TYPE_ETHERNET    = 0x1,
 };
 
 enum {
 	MLX5_NODNIC_EVENT_WORD_PORT_STATE_DOWN        = 0x0,
 	MLX5_NODNIC_EVENT_WORD_PORT_STATE_INITIALIZE  = 0x1,
 	MLX5_NODNIC_EVENT_WORD_PORT_STATE_ARMED       = 0x2,
 	MLX5_NODNIC_EVENT_WORD_PORT_STATE_ACTIVE      = 0x3,
 };
 
 struct mlx5_ifc_nodnic_event_word_bits {
 	u8         driver_reset_needed[0x1];
 	u8         port_management_change_event[0x1];
 	u8         reserved_0[0x19];
 	u8         link_type[0x1];
 	u8         port_state[0x4];
 };
 
 struct mlx5_ifc_nic_vport_change_event_bits {
 	u8         reserved_0[0x10];
 	u8         vport_num[0x10];
 
 	u8         reserved_1[0xc0];
 };
 
 struct mlx5_ifc_pages_req_event_bits {
 	u8         reserved_0[0x10];
 	u8         function_id[0x10];
 
 	u8         num_pages[0x20];
 
 	u8         reserved_1[0xa0];
 };
 
 struct mlx5_ifc_cmd_inter_comp_event_bits {
 	u8         command_completion_vector[0x20];
 
 	u8         reserved_0[0xc0];
 };
 
 struct mlx5_ifc_stall_vl_event_bits {
 	u8         reserved_0[0x18];
 	u8         port_num[0x1];
 	u8         reserved_1[0x3];
 	u8         vl[0x4];
 
 	u8         reserved_2[0xa0];
 };
 
 struct mlx5_ifc_db_bf_congestion_event_bits {
 	u8         event_subtype[0x8];
 	u8         reserved_0[0x8];
 	u8         congestion_level[0x8];
 	u8         reserved_1[0x8];
 
 	u8         reserved_2[0xa0];
 };
 
 struct mlx5_ifc_gpio_event_bits {
 	u8         reserved_0[0x60];
 
 	u8         gpio_event_hi[0x20];
 
 	u8         gpio_event_lo[0x20];
 
 	u8         reserved_1[0x40];
 };
 
 struct mlx5_ifc_port_state_change_event_bits {
 	u8         reserved_0[0x40];
 
 	u8         port_num[0x4];
 	u8         reserved_1[0x1c];
 
 	u8         reserved_2[0x80];
 };
 
 struct mlx5_ifc_dropped_packet_logged_bits {
 	u8         reserved_0[0xe0];
 };
 
 enum {
 	MLX5_CQ_ERROR_SYNDROME_CQ_OVERRUN                 = 0x1,
 	MLX5_CQ_ERROR_SYNDROME_CQ_ACCESS_VIOLATION_ERROR  = 0x2,
 };
 
 struct mlx5_ifc_cq_error_bits {
 	u8         reserved_0[0x8];
 	u8         cqn[0x18];
 
 	u8         reserved_1[0x20];
 
 	u8         reserved_2[0x18];
 	u8         syndrome[0x8];
 
 	u8         reserved_3[0x80];
 };
 
 struct mlx5_ifc_rdma_page_fault_event_bits {
 	u8         bytes_commited[0x20];
 
 	u8         r_key[0x20];
 
 	u8         reserved_0[0x10];
 	u8         packet_len[0x10];
 
 	u8         rdma_op_len[0x20];
 
 	u8         rdma_va[0x40];
 
 	u8         reserved_1[0x5];
 	u8         rdma[0x1];
 	u8         write[0x1];
 	u8         requestor[0x1];
 	u8         qp_number[0x18];
 };
 
 struct mlx5_ifc_wqe_associated_page_fault_event_bits {
 	u8         bytes_committed[0x20];
 
 	u8         reserved_0[0x10];
 	u8         wqe_index[0x10];
 
 	u8         reserved_1[0x10];
 	u8         len[0x10];
 
 	u8         reserved_2[0x60];
 
 	u8         reserved_3[0x5];
 	u8         rdma[0x1];
 	u8         write_read[0x1];
 	u8         requestor[0x1];
 	u8         qpn[0x18];
 };
 
 enum {
 	MLX5_QP_EVENTS_TYPE_QP  = 0x0,
 	MLX5_QP_EVENTS_TYPE_RQ  = 0x1,
 	MLX5_QP_EVENTS_TYPE_SQ  = 0x2,
 };
 
 struct mlx5_ifc_qp_events_bits {
 	u8         reserved_0[0xa0];
 
 	u8         type[0x8];
 	u8         reserved_1[0x18];
 
 	u8         reserved_2[0x8];
 	u8         qpn_rqn_sqn[0x18];
 };
 
 struct mlx5_ifc_dct_events_bits {
 	u8         reserved_0[0xc0];
 
 	u8         reserved_1[0x8];
 	u8         dct_number[0x18];
 };
 
 struct mlx5_ifc_comp_event_bits {
 	u8         reserved_0[0xc0];
 
 	u8         reserved_1[0x8];
 	u8         cq_number[0x18];
 };
 
 struct mlx5_ifc_fw_version_bits {
 	u8         major[0x10];
 	u8         reserved_0[0x10];
 
 	u8         minor[0x10];
 	u8         subminor[0x10];
 
 	u8         second[0x8];
 	u8         minute[0x8];
 	u8         hour[0x8];
 	u8         reserved_1[0x8];
 
 	u8         year[0x10];
 	u8         month[0x8];
 	u8         day[0x8];
 };
 
 enum {
 	MLX5_QPC_STATE_RST        = 0x0,
 	MLX5_QPC_STATE_INIT       = 0x1,
 	MLX5_QPC_STATE_RTR        = 0x2,
 	MLX5_QPC_STATE_RTS        = 0x3,
 	MLX5_QPC_STATE_SQER       = 0x4,
 	MLX5_QPC_STATE_SQD        = 0x5,
 	MLX5_QPC_STATE_ERR        = 0x6,
 	MLX5_QPC_STATE_SUSPENDED  = 0x9,
 };
 
 enum {
 	MLX5_QPC_ST_RC            = 0x0,
 	MLX5_QPC_ST_UC            = 0x1,
 	MLX5_QPC_ST_UD            = 0x2,
 	MLX5_QPC_ST_XRC           = 0x3,
 	MLX5_QPC_ST_DCI           = 0x5,
 	MLX5_QPC_ST_QP0           = 0x7,
 	MLX5_QPC_ST_QP1           = 0x8,
 	MLX5_QPC_ST_RAW_DATAGRAM  = 0x9,
 	MLX5_QPC_ST_REG_UMR       = 0xc,
 };
 
 enum {
 	MLX5_QP_PM_ARMED            = 0x0,
 	MLX5_QP_PM_REARM            = 0x1,
 	MLX5_QPC_PM_STATE_RESERVED  = 0x2,
 	MLX5_QP_PM_MIGRATED         = 0x3,
 };
 
 enum {
 	MLX5_QPC_END_PADDING_MODE_SCATTER_AS_IS                = 0x0,
 	MLX5_QPC_END_PADDING_MODE_PAD_TO_CACHE_LINE_ALIGNMENT  = 0x1,
 };
 
 enum {
 	MLX5_QPC_MTU_256_BYTES        = 0x1,
 	MLX5_QPC_MTU_512_BYTES        = 0x2,
 	MLX5_QPC_MTU_1K_BYTES         = 0x3,
 	MLX5_QPC_MTU_2K_BYTES         = 0x4,
 	MLX5_QPC_MTU_4K_BYTES         = 0x5,
 	MLX5_QPC_MTU_RAW_ETHERNET_QP  = 0x7,
 };
 
 enum {
 	MLX5_QPC_ATOMIC_MODE_IB_SPEC     = 0x1,
 	MLX5_QPC_ATOMIC_MODE_ONLY_8B     = 0x2,
 	MLX5_QPC_ATOMIC_MODE_UP_TO_8B    = 0x3,
 	MLX5_QPC_ATOMIC_MODE_UP_TO_16B   = 0x4,
 	MLX5_QPC_ATOMIC_MODE_UP_TO_32B   = 0x5,
 	MLX5_QPC_ATOMIC_MODE_UP_TO_64B   = 0x6,
 	MLX5_QPC_ATOMIC_MODE_UP_TO_128B  = 0x7,
 	MLX5_QPC_ATOMIC_MODE_UP_TO_256B  = 0x8,
 };
 
 enum {
 	MLX5_QPC_CS_REQ_DISABLE    = 0x0,
 	MLX5_QPC_CS_REQ_UP_TO_32B  = 0x11,
 	MLX5_QPC_CS_REQ_UP_TO_64B  = 0x22,
 };
 
 enum {
 	MLX5_QPC_CS_RES_DISABLE    = 0x0,
 	MLX5_QPC_CS_RES_UP_TO_32B  = 0x1,
 	MLX5_QPC_CS_RES_UP_TO_64B  = 0x2,
 };
 
 struct mlx5_ifc_qpc_bits {
 	u8         state[0x4];
 	u8         lag_tx_port_affinity[0x4];
 	u8         st[0x8];
 	u8         reserved_1[0x3];
 	u8         pm_state[0x2];
 	u8         reserved_2[0x7];
 	u8         end_padding_mode[0x2];
 	u8         reserved_3[0x2];
 
 	u8         wq_signature[0x1];
 	u8         block_lb_mc[0x1];
 	u8         atomic_like_write_en[0x1];
 	u8         latency_sensitive[0x1];
 	u8         reserved_4[0x1];
 	u8         drain_sigerr[0x1];
 	u8         reserved_5[0x2];
 	u8         pd[0x18];
 
 	u8         mtu[0x3];
 	u8         log_msg_max[0x5];
 	u8         reserved_6[0x1];
 	u8         log_rq_size[0x4];
 	u8         log_rq_stride[0x3];
 	u8         no_sq[0x1];
 	u8         log_sq_size[0x4];
 	u8         reserved_7[0x6];
 	u8         rlky[0x1];
 	u8         ulp_stateless_offload_mode[0x4];
 
 	u8         counter_set_id[0x8];
 	u8         uar_page[0x18];
 
 	u8         reserved_8[0x8];
 	u8         user_index[0x18];
 
 	u8         reserved_9[0x3];
 	u8         log_page_size[0x5];
 	u8         remote_qpn[0x18];
 
 	struct mlx5_ifc_ads_bits primary_address_path;
 
 	struct mlx5_ifc_ads_bits secondary_address_path;
 
 	u8         log_ack_req_freq[0x4];
 	u8         reserved_10[0x4];
 	u8         log_sra_max[0x3];
 	u8         reserved_11[0x2];
 	u8         retry_count[0x3];
 	u8         rnr_retry[0x3];
 	u8         reserved_12[0x1];
 	u8         fre[0x1];
 	u8         cur_rnr_retry[0x3];
 	u8         cur_retry_count[0x3];
 	u8         reserved_13[0x5];
 
 	u8         reserved_14[0x20];
 
 	u8         reserved_15[0x8];
 	u8         next_send_psn[0x18];
 
 	u8         reserved_16[0x8];
 	u8         cqn_snd[0x18];
 
 	u8         reserved_at_400[0x8];
 
 	u8         deth_sqpn[0x18];
 	u8         reserved_17[0x20];
 
 	u8         reserved_18[0x8];
 	u8         last_acked_psn[0x18];
 
 	u8         reserved_19[0x8];
 	u8         ssn[0x18];
 
 	u8         reserved_20[0x8];
 	u8         log_rra_max[0x3];
 	u8         reserved_21[0x1];
 	u8         atomic_mode[0x4];
 	u8         rre[0x1];
 	u8         rwe[0x1];
 	u8         rae[0x1];
 	u8         reserved_22[0x1];
 	u8         page_offset[0x6];
 	u8         reserved_23[0x3];
 	u8         cd_slave_receive[0x1];
 	u8         cd_slave_send[0x1];
 	u8         cd_master[0x1];
 
 	u8         reserved_24[0x3];
 	u8         min_rnr_nak[0x5];
 	u8         next_rcv_psn[0x18];
 
 	u8         reserved_25[0x8];
 	u8         xrcd[0x18];
 
 	u8         reserved_26[0x8];
 	u8         cqn_rcv[0x18];
 
 	u8         dbr_addr[0x40];
 
 	u8         q_key[0x20];
 
 	u8         reserved_27[0x5];
 	u8         rq_type[0x3];
 	u8         srqn_rmpn[0x18];
 
 	u8         reserved_28[0x8];
 	u8         rmsn[0x18];
 
 	u8         hw_sq_wqebb_counter[0x10];
 	u8         sw_sq_wqebb_counter[0x10];
 
 	u8         hw_rq_counter[0x20];
 
 	u8         sw_rq_counter[0x20];
 
 	u8         reserved_29[0x20];
 
 	u8         reserved_30[0xf];
 	u8         cgs[0x1];
 	u8         cs_req[0x8];
 	u8         cs_res[0x8];
 
 	u8         dc_access_key[0x40];
 
 	u8         rdma_active[0x1];
 	u8         comm_est[0x1];
 	u8         suspended[0x1];
 	u8         reserved_31[0x5];
 	u8         send_msg_psn[0x18];
 
 	u8         reserved_32[0x8];
 	u8         rcv_msg_psn[0x18];
 
 	u8         rdma_va[0x40];
 
 	u8         rdma_key[0x20];
 
 	u8         reserved_33[0x20];
 };
 
 struct mlx5_ifc_roce_addr_layout_bits {
 	u8         source_l3_address[16][0x8];
 
 	u8         reserved_0[0x3];
 	u8         vlan_valid[0x1];
 	u8         vlan_id[0xc];
 	u8         source_mac_47_32[0x10];
 
 	u8         source_mac_31_0[0x20];
 
 	u8         reserved_1[0x14];
 	u8         roce_l3_type[0x4];
 	u8         roce_version[0x8];
 
 	u8         reserved_2[0x20];
 };
 
 struct mlx5_ifc_rdbc_bits {
 	u8         reserved_0[0x1c];
 	u8         type[0x4];
 
 	u8         reserved_1[0x20];
 
 	u8         reserved_2[0x8];
 	u8         psn[0x18];
 
 	u8         rkey[0x20];
 
 	u8         address[0x40];
 
 	u8         byte_count[0x20];
 
 	u8         reserved_3[0x20];
 
 	u8         atomic_resp[32][0x8];
 };
 
 enum {
 	MLX5_FLOW_CONTEXT_ACTION_ALLOW     = 0x1,
 	MLX5_FLOW_CONTEXT_ACTION_DROP      = 0x2,
 	MLX5_FLOW_CONTEXT_ACTION_FWD_DEST  = 0x4,
 	MLX5_FLOW_CONTEXT_ACTION_COUNT     = 0x8,
 };
 
 struct mlx5_ifc_flow_context_bits {
 	u8         reserved_0[0x20];
 
 	u8         group_id[0x20];
 
 	u8         reserved_1[0x8];
 	u8         flow_tag[0x18];
 
 	u8         reserved_2[0x10];
 	u8         action[0x10];
 
 	u8         reserved_3[0x8];
 	u8         destination_list_size[0x18];
 
 	u8         reserved_4[0x8];
 	u8         flow_counter_list_size[0x18];
 
 	u8         reserved_5[0x140];
 
 	struct mlx5_ifc_fte_match_param_bits match_value;
 
 	u8         reserved_6[0x600];
 
 	union mlx5_ifc_dest_format_struct_flow_counter_list_auto_bits destination[0];
 };
 
 enum {
 	MLX5_XRC_SRQC_STATE_GOOD   = 0x0,
 	MLX5_XRC_SRQC_STATE_ERROR  = 0x1,
 };
 
 struct mlx5_ifc_xrc_srqc_bits {
 	u8         state[0x4];
 	u8         log_xrc_srq_size[0x4];
 	u8         reserved_0[0x18];
 
 	u8         wq_signature[0x1];
 	u8         cont_srq[0x1];
 	u8         reserved_1[0x1];
 	u8         rlky[0x1];
 	u8         basic_cyclic_rcv_wqe[0x1];
 	u8         log_rq_stride[0x3];
 	u8         xrcd[0x18];
 
 	u8         page_offset[0x6];
 	u8         reserved_2[0x2];
 	u8         cqn[0x18];
 
 	u8         reserved_3[0x20];
 
 	u8         reserved_4[0x2];
 	u8         log_page_size[0x6];
 	u8         user_index[0x18];
 
 	u8         reserved_5[0x20];
 
 	u8         reserved_6[0x8];
 	u8         pd[0x18];
 
 	u8         lwm[0x10];
 	u8         wqe_cnt[0x10];
 
 	u8         reserved_7[0x40];
 
 	u8         db_record_addr_h[0x20];
 
 	u8         db_record_addr_l[0x1e];
 	u8         reserved_8[0x2];
 
 	u8         reserved_9[0x80];
 };
 
 struct mlx5_ifc_traffic_counter_bits {
 	u8         packets[0x40];
 
 	u8         octets[0x40];
 };
 
 struct mlx5_ifc_tisc_bits {
 	u8         strict_lag_tx_port_affinity[0x1];
 	u8         reserved_at_1[0x3];
 	u8         lag_tx_port_affinity[0x04];
 
 	u8         reserved_at_8[0x4];
 	u8         prio[0x4];
 	u8         reserved_1[0x10];
 
 	u8         reserved_2[0x100];
 
 	u8         reserved_3[0x8];
 	u8         transport_domain[0x18];
 
 	u8         reserved_4[0x8];
 	u8         underlay_qpn[0x18];
 
 	u8         reserved_5[0x3a0];
 };
 
 enum {
 	MLX5_TIRC_DISP_TYPE_DIRECT    = 0x0,
 	MLX5_TIRC_DISP_TYPE_INDIRECT  = 0x1,
 };
 
 enum {
 	MLX5_TIRC_LRO_ENABLE_MASK_IPV4_LRO  = 0x1,
 	MLX5_TIRC_LRO_ENABLE_MASK_IPV6_LRO  = 0x2,
 };
 
 enum {
 	MLX5_TIRC_RX_HASH_FN_HASH_NONE           = 0x0,
 	MLX5_TIRC_RX_HASH_FN_HASH_INVERTED_XOR8  = 0x1,
 	MLX5_TIRC_RX_HASH_FN_HASH_TOEPLITZ       = 0x2,
 };
 
 enum {
 	MLX5_TIRC_SELF_LB_EN_ENABLE_UNICAST    = 0x1,
 	MLX5_TIRC_SELF_LB_EN_ENABLE_MULTICAST  = 0x2,
 };
 
 struct mlx5_ifc_tirc_bits {
 	u8         reserved_0[0x20];
 
 	u8         disp_type[0x4];
 	u8         reserved_1[0x1c];
 
 	u8         reserved_2[0x40];
 
 	u8         reserved_3[0x4];
 	u8         lro_timeout_period_usecs[0x10];
 	u8         lro_enable_mask[0x4];
 	u8         lro_max_msg_sz[0x8];
 
 	u8         reserved_4[0x40];
 
 	u8         reserved_5[0x8];
 	u8         inline_rqn[0x18];
 
 	u8         rx_hash_symmetric[0x1];
 	u8         reserved_6[0x1];
 	u8         tunneled_offload_en[0x1];
 	u8         reserved_7[0x5];
 	u8         indirect_table[0x18];
 
 	u8         rx_hash_fn[0x4];
 	u8         reserved_8[0x2];
 	u8         self_lb_en[0x2];
 	u8         transport_domain[0x18];
 
 	u8         rx_hash_toeplitz_key[10][0x20];
 
 	struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_outer;
 
 	struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_inner;
 
 	u8         reserved_9[0x4c0];
 };
 
 enum {
 	MLX5_SRQC_STATE_GOOD   = 0x0,
 	MLX5_SRQC_STATE_ERROR  = 0x1,
 };
 
 struct mlx5_ifc_srqc_bits {
 	u8         state[0x4];
 	u8         log_srq_size[0x4];
 	u8         reserved_0[0x18];
 
 	u8         wq_signature[0x1];
 	u8         cont_srq[0x1];
 	u8         reserved_1[0x1];
 	u8         rlky[0x1];
 	u8         reserved_2[0x1];
 	u8         log_rq_stride[0x3];
 	u8         xrcd[0x18];
 
 	u8         page_offset[0x6];
 	u8         reserved_3[0x2];
 	u8         cqn[0x18];
 
 	u8         reserved_4[0x20];
 
 	u8         reserved_5[0x2];
 	u8         log_page_size[0x6];
 	u8         reserved_6[0x18];
 
 	u8         reserved_7[0x20];
 
 	u8         reserved_8[0x8];
 	u8         pd[0x18];
 
 	u8         lwm[0x10];
 	u8         wqe_cnt[0x10];
 
 	u8         reserved_9[0x40];
 
 	u8	   dbr_addr[0x40];
 
 	u8	   reserved_10[0x80];
 };
 
 enum {
 	MLX5_SQC_STATE_RST  = 0x0,
 	MLX5_SQC_STATE_RDY  = 0x1,
 	MLX5_SQC_STATE_ERR  = 0x3,
 };
 
 struct mlx5_ifc_sqc_bits {
 	u8         rlkey[0x1];
 	u8         cd_master[0x1];
 	u8         fre[0x1];
 	u8         flush_in_error_en[0x1];
 	u8         allow_multi_pkt_send_wqe[0x1];
 	u8         min_wqe_inline_mode[0x3];
 	u8         state[0x4];
 	u8         reg_umr[0x1];
 	u8         allow_swp[0x1];
 	u8         reserved_0[0x12];
 
 	u8         reserved_1[0x8];
 	u8         user_index[0x18];
 
 	u8         reserved_2[0x8];
 	u8         cqn[0x18];
 
 	u8         reserved_3[0x80];
 
 	u8         qos_para_vport_number[0x10];
 	u8         packet_pacing_rate_limit_index[0x10];
 
 	u8         tis_lst_sz[0x10];
 	u8         reserved_4[0x10];
 
 	u8         reserved_5[0x40];
 
 	u8         reserved_6[0x8];
 	u8         tis_num_0[0x18];
 
 	struct mlx5_ifc_wq_bits wq;
 };
 
 enum {
 	MLX5_TSAR_TYPE_DWRR = 0,
 	MLX5_TSAR_TYPE_ROUND_ROUBIN = 1,
 	MLX5_TSAR_TYPE_ETS = 2
 };
 
 struct mlx5_ifc_tsar_element_attributes_bits {
 	u8         reserved_0[0x8];
 	u8         tsar_type[0x8];
 	u8	   reserved_1[0x10];
 };
 
 struct mlx5_ifc_vport_element_attributes_bits {
 	u8         reserved_0[0x10];
 	u8         vport_number[0x10];
 };
 
 struct mlx5_ifc_vport_tc_element_attributes_bits {
 	u8         traffic_class[0x10];
 	u8         vport_number[0x10];
 };
 
 struct mlx5_ifc_para_vport_tc_element_attributes_bits {
 	u8         reserved_0[0x0C];
 	u8         traffic_class[0x04];
 	u8         qos_para_vport_number[0x10];
 };
 
 enum {
 	MLX5_SCHEDULING_CONTEXT_ELEMENT_TYPE_TSAR           = 0x0,
 	MLX5_SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT          = 0x1,
 	MLX5_SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT_TC       = 0x2,
 	MLX5_SCHEDULING_CONTEXT_ELEMENT_TYPE_PARA_VPORT_TC  = 0x3,
 };
 
 struct mlx5_ifc_scheduling_context_bits {
 	u8         element_type[0x8];
 	u8         reserved_at_8[0x18];
 
 	u8         element_attributes[0x20];
 
 	u8         parent_element_id[0x20];
 
 	u8         reserved_at_60[0x40];
 
 	u8         bw_share[0x20];
 
 	u8         max_average_bw[0x20];
 
 	u8         reserved_at_e0[0x120];
 };
 
 struct mlx5_ifc_rqtc_bits {
 	u8         reserved_0[0xa0];
 
 	u8         reserved_1[0x10];
 	u8         rqt_max_size[0x10];
 
 	u8         reserved_2[0x10];
 	u8         rqt_actual_size[0x10];
 
 	u8         reserved_3[0x6a0];
 
 	struct mlx5_ifc_rq_num_bits rq_num[0];
 };
 
 enum {
 	MLX5_RQC_RQ_TYPE_MEMORY_RQ_INLINE      = 0x0,
 	MLX5_RQC_RQ_TYPE_MEMORY_RQ_RMP         = 0x1,
 };
 
 enum {
 	MLX5_RQC_STATE_RST  = 0x0,
 	MLX5_RQC_STATE_RDY  = 0x1,
 	MLX5_RQC_STATE_ERR  = 0x3,
 };
 
 enum {
 	MLX5_RQC_DROPLESS_MODE_DISABLE        = 0x0,
 	MLX5_RQC_DROPLESS_MODE_ENABLE         = 0x1,
 };
 
 struct mlx5_ifc_rqc_bits {
 	u8         rlkey[0x1];
 	u8         delay_drop_en[0x1];
 	u8         scatter_fcs[0x1];
 	u8         vlan_strip_disable[0x1];
 	u8         mem_rq_type[0x4];
 	u8         state[0x4];
 	u8         reserved_1[0x1];
 	u8         flush_in_error_en[0x1];
 	u8         reserved_2[0x12];
 
 	u8         reserved_3[0x8];
 	u8         user_index[0x18];
 
 	u8         reserved_4[0x8];
 	u8         cqn[0x18];
 
 	u8         counter_set_id[0x8];
 	u8         reserved_5[0x18];
 
 	u8         reserved_6[0x8];
 	u8         rmpn[0x18];
 
 	u8         reserved_7[0xe0];
 
 	struct mlx5_ifc_wq_bits wq;
 };
 
 enum {
 	MLX5_RMPC_STATE_RDY  = 0x1,
 	MLX5_RMPC_STATE_ERR  = 0x3,
 };
 
 struct mlx5_ifc_rmpc_bits {
 	u8         reserved_0[0x8];
 	u8         state[0x4];
 	u8         reserved_1[0x14];
 
 	u8         basic_cyclic_rcv_wqe[0x1];
 	u8         reserved_2[0x1f];
 
 	u8         reserved_3[0x140];
 
 	struct mlx5_ifc_wq_bits wq;
 };
 
 enum {
 	MLX5_NIC_VPORT_CONTEXT_ALLOWED_LIST_TYPE_CURRENT_UC_MAC_ADDRESS  = 0x0,
 	MLX5_NIC_VPORT_CONTEXT_ALLOWED_LIST_TYPE_CURRENT_MC_MAC_ADDRESS  = 0x1,
 	MLX5_NIC_VPORT_CONTEXT_ALLOWED_LIST_TYPE_VLAN_LIST               = 0x2,
 };
 
 struct mlx5_ifc_nic_vport_context_bits {
 	u8         reserved_0[0x5];
 	u8         min_wqe_inline_mode[0x3];
 	u8         reserved_1[0x15];
 	u8         disable_mc_local_lb[0x1];
 	u8         disable_uc_local_lb[0x1];
 	u8         roce_en[0x1];
 
 	u8         arm_change_event[0x1];
 	u8         reserved_2[0x1a];
 	u8         event_on_mtu[0x1];
 	u8         event_on_promisc_change[0x1];
 	u8         event_on_vlan_change[0x1];
 	u8         event_on_mc_address_change[0x1];
 	u8         event_on_uc_address_change[0x1];
 
 	u8         reserved_3[0xe0];
 
 	u8         reserved_4[0x10];
 	u8         mtu[0x10];
 
 	u8         system_image_guid[0x40];
 
 	u8         port_guid[0x40];
 
 	u8         node_guid[0x40];
 
 	u8         reserved_5[0x140];
 
 	u8         qkey_violation_counter[0x10];
 	u8         reserved_6[0x10];
 
 	u8         reserved_7[0x420];
 
 	u8         promisc_uc[0x1];
 	u8         promisc_mc[0x1];
 	u8         promisc_all[0x1];
 	u8         reserved_8[0x2];
 	u8         allowed_list_type[0x3];
 	u8         reserved_9[0xc];
 	u8         allowed_list_size[0xc];
 
 	struct mlx5_ifc_mac_address_layout_bits permanent_address;
 
 	u8         reserved_10[0x20];
 
 	u8         current_uc_mac_address[0][0x40];
 };
 
 enum {
 	MLX5_ACCESS_MODE_PA        = 0x0,
 	MLX5_ACCESS_MODE_MTT       = 0x1,
 	MLX5_ACCESS_MODE_KLM       = 0x2,
 };
 
 struct mlx5_ifc_mkc_bits {
 	u8         reserved_at_0[0x1];
 	u8         free[0x1];
 	u8         reserved_at_2[0x1];
 	u8         access_mode_4_2[0x3];
 	u8         reserved_at_6[0x7];
 	u8         relaxed_ordering_write[0x1];
 	u8         reserved_at_e[0x1];
 	u8         small_fence_on_rdma_read_response[0x1];
 	u8         umr_en[0x1];
 	u8         a[0x1];
 	u8         rw[0x1];
 	u8         rr[0x1];
 	u8         lw[0x1];
 	u8         lr[0x1];
 	u8         access_mode[0x2];
 	u8         reserved_2[0x8];
 
 	u8         qpn[0x18];
 	u8         mkey_7_0[0x8];
 
 	u8         reserved_3[0x20];
 
 	u8         length64[0x1];
 	u8         bsf_en[0x1];
 	u8         sync_umr[0x1];
 	u8         reserved_4[0x2];
 	u8         expected_sigerr_count[0x1];
 	u8         reserved_5[0x1];
 	u8         en_rinval[0x1];
 	u8         pd[0x18];
 
 	u8         start_addr[0x40];
 
 	u8         len[0x40];
 
 	u8         bsf_octword_size[0x20];
 
 	u8         reserved_6[0x80];
 
 	u8         translations_octword_size[0x20];
 
 	u8         reserved_7[0x1b];
 	u8         log_page_size[0x5];
 
 	u8         reserved_8[0x20];
 };
 
 struct mlx5_ifc_pkey_bits {
 	u8         reserved_0[0x10];
 	u8         pkey[0x10];
 };
 
 struct mlx5_ifc_array128_auto_bits {
 	u8         array128_auto[16][0x8];
 };
 
 enum {
 	MLX5_HCA_VPORT_CONTEXT_FIELD_SELECT_PORT_GUID           = 0x0,
 	MLX5_HCA_VPORT_CONTEXT_FIELD_SELECT_NODE_GUID           = 0x1,
 	MLX5_HCA_VPORT_CONTEXT_FIELD_SELECT_VPORT_STATE_POLICY  = 0x2,
 };
 
 enum {
 	MLX5_HCA_VPORT_CONTEXT_PORT_PHYSICAL_STATE_SLEEP                      = 0x1,
 	MLX5_HCA_VPORT_CONTEXT_PORT_PHYSICAL_STATE_POLLING                    = 0x2,
 	MLX5_HCA_VPORT_CONTEXT_PORT_PHYSICAL_STATE_DISABLED                   = 0x3,
 	MLX5_HCA_VPORT_CONTEXT_PORT_PHYSICAL_STATE_PORTCONFIGURATIONTRAINING  = 0x4,
 	MLX5_HCA_VPORT_CONTEXT_PORT_PHYSICAL_STATE_LINKUP                     = 0x5,
 	MLX5_HCA_VPORT_CONTEXT_PORT_PHYSICAL_STATE_LINKERRORRECOVERY          = 0x6,
 	MLX5_HCA_VPORT_CONTEXT_PORT_PHYSICAL_STATE_PHYTEST                    = 0x7,
 };
 
 enum {
 	MLX5_HCA_VPORT_CONTEXT_VPORT_STATE_POLICY_DOWN    = 0x0,
 	MLX5_HCA_VPORT_CONTEXT_VPORT_STATE_POLICY_UP      = 0x1,
 	MLX5_HCA_VPORT_CONTEXT_VPORT_STATE_POLICY_FOLLOW  = 0x2,
 };
 
 enum {
 	MLX5_HCA_VPORT_CONTEXT_PORT_STATE_DOWN    = 0x1,
 	MLX5_HCA_VPORT_CONTEXT_PORT_STATE_INIT    = 0x2,
 	MLX5_HCA_VPORT_CONTEXT_PORT_STATE_ARM     = 0x3,
 	MLX5_HCA_VPORT_CONTEXT_PORT_STATE_ACTIVE  = 0x4,
 };
 
 enum {
 	MLX5_HCA_VPORT_CONTEXT_VPORT_STATE_DOWN    = 0x1,
 	MLX5_HCA_VPORT_CONTEXT_VPORT_STATE_INIT    = 0x2,
 	MLX5_HCA_VPORT_CONTEXT_VPORT_STATE_ARM     = 0x3,
 	MLX5_HCA_VPORT_CONTEXT_VPORT_STATE_ACTIVE  = 0x4,
 };
 
 struct mlx5_ifc_hca_vport_context_bits {
 	u8         field_select[0x20];
 
 	u8         reserved_0[0xe0];
 
 	u8         sm_virt_aware[0x1];
 	u8         has_smi[0x1];
 	u8         has_raw[0x1];
 	u8         grh_required[0x1];
 	u8         reserved_1[0x1];
 	u8         min_wqe_inline_mode[0x3];
 	u8         reserved_2[0x8];
 	u8         port_physical_state[0x4];
 	u8         vport_state_policy[0x4];
 	u8         port_state[0x4];
 	u8         vport_state[0x4];
 
 	u8         reserved_3[0x20];
 
 	u8         system_image_guid[0x40];
 
 	u8         port_guid[0x40];
 
 	u8         node_guid[0x40];
 
 	u8         cap_mask1[0x20];
 
 	u8         cap_mask1_field_select[0x20];
 
 	u8         cap_mask2[0x20];
 
 	u8         cap_mask2_field_select[0x20];
 
 	u8         reserved_4[0x80];
 
 	u8         lid[0x10];
 	u8         reserved_5[0x4];
 	u8         init_type_reply[0x4];
 	u8         lmc[0x3];
 	u8         subnet_timeout[0x5];
 
 	u8         sm_lid[0x10];
 	u8         sm_sl[0x4];
 	u8         reserved_6[0xc];
 
 	u8         qkey_violation_counter[0x10];
 	u8         pkey_violation_counter[0x10];
 
 	u8         reserved_7[0xca0];
 };
 
 union mlx5_ifc_hca_cap_union_bits {
 	struct mlx5_ifc_cmd_hca_cap_bits cmd_hca_cap;
 	struct mlx5_ifc_odp_cap_bits odp_cap;
 	struct mlx5_ifc_atomic_caps_bits atomic_caps;
 	struct mlx5_ifc_roce_cap_bits roce_cap;
 	struct mlx5_ifc_per_protocol_networking_offload_caps_bits per_protocol_networking_offload_caps;
 	struct mlx5_ifc_flow_table_nic_cap_bits flow_table_nic_cap;
 	struct mlx5_ifc_flow_table_eswitch_cap_bits flow_table_eswitch_cap;
 	struct mlx5_ifc_e_switch_cap_bits e_switch_cap;
 	struct mlx5_ifc_snapshot_cap_bits snapshot_cap;
 	struct mlx5_ifc_debug_cap_bits diagnostic_counters_cap;
 	struct mlx5_ifc_qos_cap_bits qos_cap;
 	u8         reserved_0[0x8000];
 };
 
 enum {
 	MLX5_FLOW_TABLE_CONTEXT_TABLE_MISS_ACTION_DEFAULT = 0x0,
 	MLX5_FLOW_TABLE_CONTEXT_TABLE_MISS_ACTION_IDENTIFIED = 0x1,
 };
 
 struct mlx5_ifc_flow_table_context_bits {
 	u8         encap_en[0x1];
 	u8         decap_en[0x1];
 	u8         reserved_at_2[0x2];
 	u8         table_miss_action[0x4];
 	u8         level[0x8];
 	u8         reserved_at_10[0x8];
 	u8         log_size[0x8];
 
 	u8         reserved_at_20[0x8];
 	u8         table_miss_id[0x18];
 
 	u8         reserved_at_40[0x8];
 	u8         lag_master_next_table_id[0x18];
 
 	u8         reserved_at_60[0xe0];
 };
 
 struct mlx5_ifc_esw_vport_context_bits {
 	u8         reserved_0[0x3];
 	u8         vport_svlan_strip[0x1];
 	u8         vport_cvlan_strip[0x1];
 	u8         vport_svlan_insert[0x1];
 	u8         vport_cvlan_insert[0x2];
 	u8         reserved_1[0x18];
 
 	u8         reserved_2[0x20];
 
 	u8         svlan_cfi[0x1];
 	u8         svlan_pcp[0x3];
 	u8         svlan_id[0xc];
 	u8         cvlan_cfi[0x1];
 	u8         cvlan_pcp[0x3];
 	u8         cvlan_id[0xc];
 
 	u8         reserved_3[0x7a0];
 };
 
 enum {
 	MLX5_EQC_STATUS_OK                = 0x0,
 	MLX5_EQC_STATUS_EQ_WRITE_FAILURE  = 0xa,
 };
 
 enum {
 	MLX5_EQ_STATE_ARMED = 0x9,
 	MLX5_EQ_STATE_FIRED = 0xa,
 };
 
 struct mlx5_ifc_eqc_bits {
 	u8         status[0x4];
 	u8         reserved_0[0x9];
 	u8         ec[0x1];
 	u8         oi[0x1];
 	u8         reserved_1[0x5];
 	u8         st[0x4];
 	u8         reserved_2[0x8];
 
 	u8         reserved_3[0x20];
 
 	u8         reserved_4[0x14];
 	u8         page_offset[0x6];
 	u8         reserved_5[0x6];
 
 	u8         reserved_6[0x3];
 	u8         log_eq_size[0x5];
 	u8         uar_page[0x18];
 
 	u8         reserved_7[0x20];
 
 	u8         reserved_8[0x18];
 	u8         intr[0x8];
 
 	u8         reserved_9[0x3];
 	u8         log_page_size[0x5];
 	u8         reserved_10[0x18];
 
 	u8         reserved_11[0x60];
 
 	u8         reserved_12[0x8];
 	u8         consumer_counter[0x18];
 
 	u8         reserved_13[0x8];
 	u8         producer_counter[0x18];
 
 	u8         reserved_14[0x80];
 };
 
 enum {
 	MLX5_DCTC_STATE_ACTIVE    = 0x0,
 	MLX5_DCTC_STATE_DRAINING  = 0x1,
 	MLX5_DCTC_STATE_DRAINED   = 0x2,
 };
 
 enum {
 	MLX5_DCTC_CS_RES_DISABLE    = 0x0,
 	MLX5_DCTC_CS_RES_NA         = 0x1,
 	MLX5_DCTC_CS_RES_UP_TO_64B  = 0x2,
 };
 
 enum {
 	MLX5_DCTC_MTU_256_BYTES  = 0x1,
 	MLX5_DCTC_MTU_512_BYTES  = 0x2,
 	MLX5_DCTC_MTU_1K_BYTES   = 0x3,
 	MLX5_DCTC_MTU_2K_BYTES   = 0x4,
 	MLX5_DCTC_MTU_4K_BYTES   = 0x5,
 };
 
 struct mlx5_ifc_dctc_bits {
 	u8         reserved_0[0x4];
 	u8         state[0x4];
 	u8         reserved_1[0x18];
 
 	u8         reserved_2[0x8];
 	u8         user_index[0x18];
 
 	u8         reserved_3[0x8];
 	u8         cqn[0x18];
 
 	u8         counter_set_id[0x8];
 	u8         atomic_mode[0x4];
 	u8         rre[0x1];
 	u8         rwe[0x1];
 	u8         rae[0x1];
 	u8         atomic_like_write_en[0x1];
 	u8         latency_sensitive[0x1];
 	u8         rlky[0x1];
 	u8         reserved_4[0xe];
 
 	u8         reserved_5[0x8];
 	u8         cs_res[0x8];
 	u8         reserved_6[0x3];
 	u8         min_rnr_nak[0x5];
 	u8         reserved_7[0x8];
 
 	u8         reserved_8[0x8];
 	u8         srqn[0x18];
 
 	u8         reserved_9[0x8];
 	u8         pd[0x18];
 
 	u8         tclass[0x8];
 	u8         reserved_10[0x4];
 	u8         flow_label[0x14];
 
 	u8         dc_access_key[0x40];
 
 	u8         reserved_11[0x5];
 	u8         mtu[0x3];
 	u8         port[0x8];
 	u8         pkey_index[0x10];
 
 	u8         reserved_12[0x8];
 	u8         my_addr_index[0x8];
 	u8         reserved_13[0x8];
 	u8         hop_limit[0x8];
 
 	u8         dc_access_key_violation_count[0x20];
 
 	u8         reserved_14[0x14];
 	u8         dei_cfi[0x1];
 	u8         eth_prio[0x3];
 	u8         ecn[0x2];
 	u8         dscp[0x6];
 
 	u8         reserved_15[0x40];
 };
 
 enum {
 	MLX5_CQC_STATUS_OK             = 0x0,
 	MLX5_CQC_STATUS_CQ_OVERFLOW    = 0x9,
 	MLX5_CQC_STATUS_CQ_WRITE_FAIL  = 0xa,
 };
 
 enum {
 	CQE_SIZE_64                = 0x0,
 	CQE_SIZE_128               = 0x1,
 };
 
 enum {
 	MLX5_CQ_PERIOD_MODE_START_FROM_EQE  = 0x0,
 	MLX5_CQ_PERIOD_MODE_START_FROM_CQE  = 0x1,
 };
 
 enum {
 	MLX5_CQ_STATE_SOLICITED_ARMED                     = 0x6,
 	MLX5_CQ_STATE_ARMED                               = 0x9,
 	MLX5_CQ_STATE_FIRED                               = 0xa,
 };
 
 struct mlx5_ifc_cqc_bits {
 	u8         status[0x4];
 	u8         reserved_0[0x4];
 	u8         cqe_sz[0x3];
 	u8         cc[0x1];
 	u8         reserved_1[0x1];
 	u8         scqe_break_moderation_en[0x1];
 	u8         oi[0x1];
 	u8         cq_period_mode[0x2];
 	u8         cqe_compression_en[0x1];
 	u8         mini_cqe_res_format[0x2];
 	u8         st[0x4];
 	u8         reserved_2[0x8];
 
 	u8         reserved_3[0x20];
 
 	u8         reserved_4[0x14];
 	u8         page_offset[0x6];
 	u8         reserved_5[0x6];
 
 	u8         reserved_6[0x3];
 	u8         log_cq_size[0x5];
 	u8         uar_page[0x18];
 
 	u8         reserved_7[0x4];
 	u8         cq_period[0xc];
 	u8         cq_max_count[0x10];
 
 	u8         reserved_8[0x18];
 	u8         c_eqn[0x8];
 
 	u8         reserved_9[0x3];
 	u8         log_page_size[0x5];
 	u8         reserved_10[0x18];
 
 	u8         reserved_11[0x20];
 
 	u8         reserved_12[0x8];
 	u8         last_notified_index[0x18];
 
 	u8         reserved_13[0x8];
 	u8         last_solicit_index[0x18];
 
 	u8         reserved_14[0x8];
 	u8         consumer_counter[0x18];
 
 	u8         reserved_15[0x8];
 	u8         producer_counter[0x18];
 
 	u8         reserved_16[0x40];
 
 	u8         dbr_addr[0x40];
 };
 
 union mlx5_ifc_cong_control_roce_ecn_auto_bits {
 	struct mlx5_ifc_cong_control_802_1qau_rp_bits cong_control_802_1qau_rp;
 	struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits cong_control_r_roce_ecn_rp;
 	struct mlx5_ifc_cong_control_r_roce_ecn_np_bits cong_control_r_roce_ecn_np;
 	u8         reserved_0[0x800];
 };
 
 struct mlx5_ifc_query_adapter_param_block_bits {
 	u8         reserved_0[0xc0];
 
 	u8         reserved_1[0x8];
 	u8         ieee_vendor_id[0x18];
 
 	u8         reserved_2[0x10];
 	u8         vsd_vendor_id[0x10];
 
 	u8         vsd[208][0x8];
 
 	u8         vsd_contd_psid[16][0x8];
 };
 
 union mlx5_ifc_modify_field_select_resize_field_select_auto_bits {
 	struct mlx5_ifc_modify_field_select_bits modify_field_select;
 	struct mlx5_ifc_resize_field_select_bits resize_field_select;
 	u8         reserved_0[0x20];
 };
 
 union mlx5_ifc_field_select_802_1_r_roce_auto_bits {
 	struct mlx5_ifc_field_select_802_1qau_rp_bits field_select_802_1qau_rp;
 	struct mlx5_ifc_field_select_r_roce_rp_bits field_select_r_roce_rp;
 	struct mlx5_ifc_field_select_r_roce_np_bits field_select_r_roce_np;
 	u8         reserved_0[0x20];
 };
 
 struct mlx5_ifc_bufferx_reg_bits {
 	u8         reserved_0[0x6];
 	u8         lossy[0x1];
 	u8         epsb[0x1];
 	u8         reserved_1[0xc];
 	u8         size[0xc];
 
 	u8         xoff_threshold[0x10];
 	u8         xon_threshold[0x10];
 };
 
 struct mlx5_ifc_config_item_bits {
 	u8         valid[0x2];
 	u8         reserved_0[0x2];
 	u8         header_type[0x2];
 	u8         reserved_1[0x2];
 	u8         default_location[0x1];
 	u8         reserved_2[0x7];
 	u8         version[0x4];
 	u8         reserved_3[0x3];
 	u8         length[0x9];
 
 	u8         type[0x20];
 
 	u8         reserved_4[0x10];
 	u8         crc16[0x10];
 };
 
 struct mlx5_ifc_nodnic_port_config_reg_bits {
 	struct mlx5_ifc_nodnic_event_word_bits event;
 
 	u8         network_en[0x1];
 	u8         dma_en[0x1];
 	u8         promisc_en[0x1];
 	u8         promisc_multicast_en[0x1];
 	u8         reserved_0[0x17];
 	u8         receive_filter_en[0x5];
 
 	u8         reserved_1[0x10];
 	u8         mac_47_32[0x10];
 
 	u8         mac_31_0[0x20];
 
 	u8         receive_filters_mgid_mac[64][0x8];
 
 	u8         gid[16][0x8];
 
 	u8         reserved_2[0x10];
 	u8         lid[0x10];
 
 	u8         reserved_3[0xc];
 	u8         sm_sl[0x4];
 	u8         sm_lid[0x10];
 
 	u8         completion_address_63_32[0x20];
 
 	u8         completion_address_31_12[0x14];
 	u8         reserved_4[0x6];
 	u8         log_cq_size[0x6];
 
 	u8         working_buffer_address_63_32[0x20];
 
 	u8         working_buffer_address_31_12[0x14];
 	u8         reserved_5[0xc];
 
 	struct mlx5_ifc_nodnic_cq_arming_word_bits arm_cq;
 
 	u8         pkey_index[0x10];
 	u8         pkey[0x10];
 
 	struct mlx5_ifc_nodnic_ring_config_reg_bits send_ring0;
 
 	struct mlx5_ifc_nodnic_ring_config_reg_bits send_ring1;
 
 	struct mlx5_ifc_nodnic_ring_config_reg_bits receive_ring0;
 
 	struct mlx5_ifc_nodnic_ring_config_reg_bits receive_ring1;
 
 	u8         reserved_6[0x400];
 };
 
 union mlx5_ifc_event_auto_bits {
 	struct mlx5_ifc_comp_event_bits comp_event;
 	struct mlx5_ifc_dct_events_bits dct_events;
 	struct mlx5_ifc_qp_events_bits qp_events;
 	struct mlx5_ifc_wqe_associated_page_fault_event_bits wqe_associated_page_fault_event;
 	struct mlx5_ifc_rdma_page_fault_event_bits rdma_page_fault_event;
 	struct mlx5_ifc_cq_error_bits cq_error;
 	struct mlx5_ifc_dropped_packet_logged_bits dropped_packet_logged;
 	struct mlx5_ifc_port_state_change_event_bits port_state_change_event;
 	struct mlx5_ifc_gpio_event_bits gpio_event;
 	struct mlx5_ifc_db_bf_congestion_event_bits db_bf_congestion_event;
 	struct mlx5_ifc_stall_vl_event_bits stall_vl_event;
 	struct mlx5_ifc_cmd_inter_comp_event_bits cmd_inter_comp_event;
 	struct mlx5_ifc_pages_req_event_bits pages_req_event;
 	struct mlx5_ifc_nic_vport_change_event_bits nic_vport_change_event;
 	u8         reserved_0[0xe0];
 };
 
 struct mlx5_ifc_health_buffer_bits {
 	u8         reserved_0[0x100];
 
 	u8         assert_existptr[0x20];
 
 	u8         assert_callra[0x20];
 
 	u8         reserved_1[0x40];
 
 	u8         fw_version[0x20];
 
 	u8         hw_id[0x20];
 
 	u8         reserved_2[0x20];
 
 	u8         irisc_index[0x8];
 	u8         synd[0x8];
 	u8         ext_synd[0x10];
 };
 
 struct mlx5_ifc_register_loopback_control_bits {
 	u8         no_lb[0x1];
 	u8         reserved_0[0x7];
 	u8         port[0x8];
 	u8         reserved_1[0x10];
 
 	u8         reserved_2[0x60];
 };
 
 struct mlx5_ifc_lrh_bits {
 	u8	vl[4];
 	u8	lver[4];
 	u8	sl[4];
 	u8	reserved2[2];
 	u8	lnh[2];
 	u8	dlid[16];
 	u8	reserved5[5];
 	u8	pkt_len[11];
 	u8	slid[16];
 };
 
 struct mlx5_ifc_icmd_set_wol_rol_out_bits {
 	u8         reserved_0[0x40];
 
 	u8         reserved_1[0x10];
 	u8         rol_mode[0x8];
 	u8         wol_mode[0x8];
 };
 
 struct mlx5_ifc_icmd_set_wol_rol_in_bits {
 	u8         reserved_0[0x40];
 
 	u8         rol_mode_valid[0x1];
 	u8         wol_mode_valid[0x1];
 	u8         reserved_1[0xe];
 	u8         rol_mode[0x8];
 	u8         wol_mode[0x8];
 
 	u8         reserved_2[0x7a0];
 };
 
 struct mlx5_ifc_icmd_set_virtual_mac_in_bits {
 	u8         virtual_mac_en[0x1];
 	u8         mac_aux_v[0x1];
 	u8         reserved_0[0x1e];
 
 	u8         reserved_1[0x40];
 
 	struct mlx5_ifc_mac_address_layout_bits virtual_mac;
 
 	u8         reserved_2[0x760];
 };
 
 struct mlx5_ifc_icmd_query_virtual_mac_out_bits {
 	u8         virtual_mac_en[0x1];
 	u8         mac_aux_v[0x1];
 	u8         reserved_0[0x1e];
 
 	struct mlx5_ifc_mac_address_layout_bits permanent_mac;
 
 	struct mlx5_ifc_mac_address_layout_bits virtual_mac;
 
 	u8         reserved_1[0x760];
 };
 
 struct mlx5_ifc_icmd_query_fw_info_out_bits {
 	struct mlx5_ifc_fw_version_bits fw_version;
 
 	u8         reserved_0[0x10];
 	u8         hash_signature[0x10];
 
 	u8         psid[16][0x8];
 
 	u8         reserved_1[0x6e0];
 };
 
 struct mlx5_ifc_icmd_query_cap_in_bits {
 	u8         reserved_0[0x10];
 	u8         capability_group[0x10];
 };
 
 struct mlx5_ifc_icmd_query_cap_general_bits {
 	u8         nv_access[0x1];
 	u8         fw_info_psid[0x1];
 	u8         reserved_0[0x1e];
 
 	u8         reserved_1[0x16];
 	u8         rol_s[0x1];
 	u8         rol_g[0x1];
 	u8         reserved_2[0x1];
 	u8         wol_s[0x1];
 	u8         wol_g[0x1];
 	u8         wol_a[0x1];
 	u8         wol_b[0x1];
 	u8         wol_m[0x1];
 	u8         wol_u[0x1];
 	u8         wol_p[0x1];
 };
 
 struct mlx5_ifc_icmd_ocbb_query_header_stats_out_bits {
 	u8         status[0x8];
 	u8         reserved_0[0x18];
 
 	u8         reserved_1[0x7e0];
 };
 
 struct mlx5_ifc_icmd_ocbb_query_etoc_stats_out_bits {
 	u8         status[0x8];
 	u8         reserved_0[0x18];
 
 	u8         reserved_1[0x7e0];
 };
 
 struct mlx5_ifc_icmd_ocbb_init_in_bits {
 	u8         address_hi[0x20];
 
 	u8         address_lo[0x20];
 
 	u8         reserved_0[0x7c0];
 };
 
 struct mlx5_ifc_icmd_init_ocsd_in_bits {
 	u8         reserved_0[0x20];
 
 	u8         address_hi[0x20];
 
 	u8         address_lo[0x20];
 
 	u8         reserved_1[0x7a0];
 };
 
 struct mlx5_ifc_icmd_access_reg_out_bits {
 	u8         reserved_0[0x11];
 	u8         status[0x7];
 	u8         reserved_1[0x8];
 
 	u8         register_id[0x10];
 	u8         reserved_2[0x10];
 
 	u8         reserved_3[0x40];
 
 	u8         reserved_4[0x5];
 	u8         len[0xb];
 	u8         reserved_5[0x10];
 
 	u8         register_data[0][0x20];
 };
 
 enum {
 	MLX5_ICMD_ACCESS_REG_IN_METHOD_QUERY  = 0x1,
 	MLX5_ICMD_ACCESS_REG_IN_METHOD_WRITE  = 0x2,
 };
 
 struct mlx5_ifc_icmd_access_reg_in_bits {
 	u8         constant_1[0x5];
 	u8         constant_2[0xb];
 	u8         reserved_0[0x10];
 
 	u8         register_id[0x10];
 	u8         reserved_1[0x1];
 	u8         method[0x7];
 	u8         constant_3[0x8];
 
 	u8         reserved_2[0x40];
 
 	u8         constant_4[0x5];
 	u8         len[0xb];
 	u8         reserved_3[0x10];
 
 	u8         register_data[0][0x20];
 };
 
 enum {
 	MLX5_TEARDOWN_HCA_OUT_FORCE_STATE_SUCCESS = 0x0,
 	MLX5_TEARDOWN_HCA_OUT_FORCE_STATE_FAIL = 0x1,
 };
 
 struct mlx5_ifc_teardown_hca_out_bits {
 	u8         status[0x8];
 	u8         reserved_0[0x18];
 
 	u8         syndrome[0x20];
 
 	u8         reserved_1[0x3f];
 
 	u8	   force_state[0x1];
 };
 
 enum {
 	MLX5_TEARDOWN_HCA_IN_PROFILE_GRACEFUL_CLOSE  = 0x0,
 	MLX5_TEARDOWN_HCA_IN_PROFILE_FORCE_CLOSE     = 0x1,
 };
 
 struct mlx5_ifc_teardown_hca_in_bits {
 	u8         opcode[0x10];
 	u8         reserved_0[0x10];
 
 	u8         reserved_1[0x10];
 	u8         op_mod[0x10];
 
 	u8         reserved_2[0x10];
 	u8         profile[0x10];
 
 	u8         reserved_3[0x20];
 };
 
 struct mlx5_ifc_set_delay_drop_params_out_bits {
 	u8         status[0x8];
 	u8         reserved_at_8[0x18];
 
 	u8         syndrome[0x20];
 
 	u8         reserved_at_40[0x40];
 };
 
 struct mlx5_ifc_set_delay_drop_params_in_bits {
 	u8         opcode[0x10];
 	u8         reserved_at_10[0x10];
 
 	u8         reserved_at_20[0x10];
 	u8         op_mod[0x10];
 
 	u8         reserved_at_40[0x20];
 
 	u8         reserved_at_60[0x10];
 	u8         delay_drop_timeout[0x10];
 };
 
 struct mlx5_ifc_query_delay_drop_params_out_bits {
 	u8         status[0x8];
 	u8         reserved_at_8[0x18];
 
 	u8         syndrome[0x20];
 
 	u8         reserved_at_40[0x20];
 
 	u8         reserved_at_60[0x10];
 	u8         delay_drop_timeout[0x10];
 };
 
 struct mlx5_ifc_query_delay_drop_params_in_bits {
 	u8         opcode[0x10];
 	u8         reserved_at_10[0x10];
 
 	u8         reserved_at_20[0x10];
 	u8         op_mod[0x10];
 
 	u8         reserved_at_40[0x40];
 };
 
 struct mlx5_ifc_suspend_qp_out_bits {
 	u8         status[0x8];
 	u8         reserved_0[0x18];
 
 	u8         syndrome[0x20];
 
 	u8         reserved_1[0x40];
 };
 
 struct mlx5_ifc_suspend_qp_in_bits {
 	u8         opcode[0x10];
 	u8         reserved_0[0x10];
 
 	u8         reserved_1[0x10];
 	u8         op_mod[0x10];
 
 	u8         reserved_2[0x8];
 	u8         qpn[0x18];
 
 	u8         reserved_3[0x20];
 };
 
 struct mlx5_ifc_sqerr2rts_qp_out_bits {
 	u8         status[0x8];
 	u8         reserved_0[0x18];
 
 	u8         syndrome[0x20];
 
 	u8         reserved_1[0x40];
 };
 
 struct mlx5_ifc_sqerr2rts_qp_in_bits {
 	u8         opcode[0x10];
 	u8         reserved_0[0x10];
 
 	u8         reserved_1[0x10];
 	u8         op_mod[0x10];
 
 	u8         reserved_2[0x8];
 	u8         qpn[0x18];
 
 	u8         reserved_3[0x20];
 
 	u8         opt_param_mask[0x20];
 
 	u8         reserved_4[0x20];
 
 	struct mlx5_ifc_qpc_bits qpc;
 
 	u8         reserved_5[0x80];
 };
 
 struct mlx5_ifc_sqd2rts_qp_out_bits {
 	u8         status[0x8];
 	u8         reserved_0[0x18];
 
 	u8         syndrome[0x20];
 
 	u8         reserved_1[0x40];
 };
 
 struct mlx5_ifc_sqd2rts_qp_in_bits {
 	u8         opcode[0x10];
 	u8         reserved_0[0x10];
 
 	u8         reserved_1[0x10];
 	u8         op_mod[0x10];
 
 	u8         reserved_2[0x8];
 	u8         qpn[0x18];
 
 	u8         reserved_3[0x20];
 
 	u8         opt_param_mask[0x20];
 
 	u8         reserved_4[0x20];
 
 	struct mlx5_ifc_qpc_bits qpc;
 
 	u8         reserved_5[0x80];
 };
 
 struct mlx5_ifc_set_wol_rol_out_bits {
 	u8         status[0x8];
 	u8         reserved_0[0x18];
 
 	u8         syndrome[0x20];
 
 	u8         reserved_1[0x40];
 };
 
 struct mlx5_ifc_set_wol_rol_in_bits {
 	u8         opcode[0x10];
 	u8         reserved_0[0x10];
 
 	u8         reserved_1[0x10];
 	u8         op_mod[0x10];
 
 	u8         rol_mode_valid[0x1];
 	u8         wol_mode_valid[0x1];
 	u8         reserved_2[0xe];
 	u8         rol_mode[0x8];
 	u8         wol_mode[0x8];
 
 	u8         reserved_3[0x20];
 };
 
 struct mlx5_ifc_set_roce_address_out_bits {
 	u8         status[0x8];
 	u8         reserved_0[0x18];
 
 	u8         syndrome[0x20];
 
 	u8         reserved_1[0x40];
 };
 
 struct mlx5_ifc_set_roce_address_in_bits {
 	u8         opcode[0x10];
 	u8         reserved_0[0x10];
 
 	u8         reserved_1[0x10];
 	u8         op_mod[0x10];
 
 	u8         roce_address_index[0x10];
 	u8         reserved_2[0x10];
 
 	u8         reserved_3[0x20];
 
 	struct mlx5_ifc_roce_addr_layout_bits roce_address;
 };
 
 struct mlx5_ifc_set_rdb_out_bits {
 	u8         status[0x8];
 	u8         reserved_0[0x18];
 
 	u8         syndrome[0x20];
 
 	u8         reserved_1[0x40];
 };
 
 struct mlx5_ifc_set_rdb_in_bits {
 	u8         opcode[0x10];
 	u8         reserved_0[0x10];
 
 	u8         reserved_1[0x10];
 	u8         op_mod[0x10];
 
 	u8         reserved_2[0x8];
 	u8         qpn[0x18];
 
 	u8         reserved_3[0x18];
 	u8         rdb_list_size[0x8];
 
 	struct mlx5_ifc_rdbc_bits rdb_context[0];
 };
 
 struct mlx5_ifc_set_mad_demux_out_bits {
 	u8         status[0x8];
 	u8         reserved_0[0x18];
 
 	u8         syndrome[0x20];
 
 	u8         reserved_1[0x40];
 };
 
 enum {
 	MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_PASS_ALL   = 0x0,
 	MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_SELECTIVE  = 0x2,
 };
 
 struct mlx5_ifc_set_mad_demux_in_bits {
 	u8         opcode[0x10];
 	u8         reserved_0[0x10];
 
 	u8         reserved_1[0x10];
 	u8         op_mod[0x10];
 
 	u8         reserved_2[0x20];
 
 	u8         reserved_3[0x6];
 	u8         demux_mode[0x2];
 	u8         reserved_4[0x18];
 };
 
 struct mlx5_ifc_set_l2_table_entry_out_bits {
 	u8         status[0x8];
 	u8         reserved_0[0x18];
 
 	u8         syndrome[0x20];
 
 	u8         reserved_1[0x40];
 };
 
 struct mlx5_ifc_set_l2_table_entry_in_bits {
 	u8         opcode[0x10];
 	u8         reserved_0[0x10];
 
 	u8         reserved_1[0x10];
 	u8         op_mod[0x10];
 
 	u8         reserved_2[0x60];
 
 	u8         reserved_3[0x8];
 	u8         table_index[0x18];
 
 	u8         reserved_4[0x20];
 
 	u8         reserved_5[0x13];
 	u8         vlan_valid[0x1];
 	u8         vlan[0xc];
 
 	struct mlx5_ifc_mac_address_layout_bits mac_address;
 
 	u8         reserved_6[0xc0];
 };
 
 struct mlx5_ifc_set_issi_out_bits {
 	u8         status[0x8];
 	u8         reserved_0[0x18];
 
 	u8         syndrome[0x20];
 
 	u8         reserved_1[0x40];
 };
 
 struct mlx5_ifc_set_issi_in_bits {
 	u8         opcode[0x10];
 	u8         reserved_0[0x10];
 
 	u8         reserved_1[0x10];
 	u8         op_mod[0x10];
 
 	u8         reserved_2[0x10];
 	u8         current_issi[0x10];
 
 	u8         reserved_3[0x20];
 };
 
 struct mlx5_ifc_set_hca_cap_out_bits {
 	u8         status[0x8];
 	u8         reserved_0[0x18];
 
 	u8         syndrome[0x20];
 
 	u8         reserved_1[0x40];
 };
 
 struct mlx5_ifc_set_hca_cap_in_bits {
 	u8         opcode[0x10];
 	u8         reserved_0[0x10];
 
 	u8         reserved_1[0x10];
 	u8         op_mod[0x10];
 
 	u8         reserved_2[0x40];
 
 	union mlx5_ifc_hca_cap_union_bits capability;
 };
 
 enum {
 	MLX5_SET_FTE_MODIFY_ENABLE_MASK_ACTION			= 0x0,
 	MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_TAG		= 0x1,
 	MLX5_SET_FTE_MODIFY_ENABLE_MASK_DESTINATION_LIST	= 0x2,
 	MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_COUNTERS		= 0x3
 };
 
 struct mlx5_ifc_set_flow_table_root_out_bits {
 	u8         status[0x8];
 	u8         reserved_0[0x18];
 
 	u8         syndrome[0x20];
 
 	u8         reserved_1[0x40];
 };
 
 struct mlx5_ifc_set_flow_table_root_in_bits {
 	u8         opcode[0x10];
 	u8         reserved_0[0x10];
 
 	u8         reserved_1[0x10];
 	u8         op_mod[0x10];
 
 	u8         other_vport[0x1];
 	u8         reserved_2[0xf];
 	u8         vport_number[0x10];
 
 	u8         reserved_3[0x20];
 
 	u8         table_type[0x8];
 	u8         reserved_4[0x18];
 
 	u8         reserved_5[0x8];
 	u8         table_id[0x18];
 
 	u8         reserved_6[0x8];
 	u8         underlay_qpn[0x18];
 
 	u8         reserved_7[0x120];
 };
 
 struct mlx5_ifc_set_fte_out_bits {
 	u8         status[0x8];
 	u8         reserved_0[0x18];
 
 	u8         syndrome[0x20];
 
 	u8         reserved_1[0x40];
 };
 
 struct mlx5_ifc_set_fte_in_bits {
 	u8         opcode[0x10];
 	u8         reserved_0[0x10];
 
 	u8         reserved_1[0x10];
 	u8         op_mod[0x10];
 
 	u8         other_vport[0x1];
 	u8         reserved_2[0xf];
 	u8         vport_number[0x10];
 
 	u8         reserved_3[0x20];
 
 	u8         table_type[0x8];
 	u8         reserved_4[0x18];
 
 	u8         reserved_5[0x8];
 	u8         table_id[0x18];
 
 	u8         reserved_6[0x18];
 	u8         modify_enable_mask[0x8];
 
 	u8         reserved_7[0x20];
 
 	u8         flow_index[0x20];
 
 	u8         reserved_8[0xe0];
 
 	struct mlx5_ifc_flow_context_bits flow_context;
 };
 
 struct mlx5_ifc_set_driver_version_out_bits {
 	u8         status[0x8];
 	u8         reserved_0[0x18];
 
 	u8         syndrome[0x20];
 
 	u8         reserved_1[0x40];
 };
 
 struct mlx5_ifc_set_driver_version_in_bits {
 	u8         opcode[0x10];
 	u8         reserved_0[0x10];
 
 	u8         reserved_1[0x10];
 	u8         op_mod[0x10];
 
 	u8         reserved_2[0x40];
 
 	u8         driver_version[64][0x8];
 };
 
 struct mlx5_ifc_set_dc_cnak_trace_out_bits {
 	u8         status[0x8];
 	u8         reserved_0[0x18];
 
 	u8         syndrome[0x20];
 
 	u8         reserved_1[0x40];
 };
 
 struct mlx5_ifc_set_dc_cnak_trace_in_bits {
 	u8         opcode[0x10];
 	u8         reserved_0[0x10];
 
 	u8         reserved_1[0x10];
 	u8         op_mod[0x10];
 
 	u8         enable[0x1];
 	u8         reserved_2[0x1f];
 
 	u8         reserved_3[0x160];
 
 	struct mlx5_ifc_cmd_pas_bits pas;
 };
 
 struct mlx5_ifc_set_burst_size_out_bits {
 	u8         status[0x8];
 	u8         reserved_0[0x18];
 
 	u8         syndrome[0x20];
 
 	u8         reserved_1[0x40];
 };
 
 struct mlx5_ifc_set_burst_size_in_bits {
 	u8         opcode[0x10];
 	u8         reserved_0[0x10];
 
 	u8         reserved_1[0x10];
 	u8         op_mod[0x10];
 
 	u8         reserved_2[0x20];
 
 	u8         reserved_3[0x9];
 	u8         device_burst_size[0x17];
 };
 
 struct mlx5_ifc_rts2rts_qp_out_bits {
 	u8         status[0x8];
 	u8         reserved_0[0x18];
 
 	u8         syndrome[0x20];
 
 	u8         reserved_1[0x40];
 };
 
 struct mlx5_ifc_rts2rts_qp_in_bits {
 	u8         opcode[0x10];
 	u8         reserved_0[0x10];
 
 	u8         reserved_1[0x10];
 	u8         op_mod[0x10];
 
 	u8         reserved_2[0x8];
 	u8         qpn[0x18];
 
 	u8         reserved_3[0x20];
 
 	u8         opt_param_mask[0x20];
 
 	u8         reserved_4[0x20];
 
 	struct mlx5_ifc_qpc_bits qpc;
 
 	u8         reserved_5[0x80];
 };
 
 struct mlx5_ifc_rtr2rts_qp_out_bits {
 	u8         status[0x8];
 	u8         reserved_0[0x18];
 
 	u8         syndrome[0x20];
 
 	u8         reserved_1[0x40];
 };
 
 struct mlx5_ifc_rtr2rts_qp_in_bits {
 	u8         opcode[0x10];
 	u8         reserved_0[0x10];
 
 	u8         reserved_1[0x10];
 	u8         op_mod[0x10];
 
 	u8         reserved_2[0x8];
 	u8         qpn[0x18];
 
 	u8         reserved_3[0x20];
 
 	u8         opt_param_mask[0x20];
 
 	u8         reserved_4[0x20];
 
 	struct mlx5_ifc_qpc_bits qpc;
 
 	u8         reserved_5[0x80];
 };
 
 struct mlx5_ifc_rst2init_qp_out_bits {
 	u8         status[0x8];
 	u8         reserved_0[0x18];
 
 	u8         syndrome[0x20];
 
 	u8         reserved_1[0x40];
 };
 
 struct mlx5_ifc_rst2init_qp_in_bits {
 	u8         opcode[0x10];
 	u8         reserved_0[0x10];
 
 	u8         reserved_1[0x10];
 	u8         op_mod[0x10];
 
 	u8         reserved_2[0x8];
 	u8         qpn[0x18];
 
 	u8         reserved_3[0x20];
 
 	u8         opt_param_mask[0x20];
 
 	u8         reserved_4[0x20];
 
 	struct mlx5_ifc_qpc_bits qpc;
 
 	u8         reserved_5[0x80];
 };
 
 struct mlx5_ifc_resume_qp_out_bits {
 	u8         status[0x8];
 	u8         reserved_0[0x18];
 
 	u8         syndrome[0x20];
 
 	u8         reserved_1[0x40];
 };
 
 struct mlx5_ifc_resume_qp_in_bits {
 	u8         opcode[0x10];
 	u8         reserved_0[0x10];
 
 	u8         reserved_1[0x10];
 	u8         op_mod[0x10];
 
 	u8         reserved_2[0x8];
 	u8         qpn[0x18];
 
 	u8         reserved_3[0x20];
 };
 
 struct mlx5_ifc_query_xrc_srq_out_bits {
 	u8         status[0x8];
 	u8         reserved_0[0x18];
 
 	u8         syndrome[0x20];
 
 	u8         reserved_1[0x40];
 
 	struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry;
 
 	u8         reserved_2[0x600];
 
 	u8         pas[0][0x40];
 };
 
 struct mlx5_ifc_query_xrc_srq_in_bits {
 	u8         opcode[0x10];
 	u8         reserved_0[0x10];
 
 	u8         reserved_1[0x10];
 	u8         op_mod[0x10];
 
 	u8         reserved_2[0x8];
 	u8         xrc_srqn[0x18];
 
 	u8         reserved_3[0x20];
 };
 
 struct mlx5_ifc_query_wol_rol_out_bits {
 	u8         status[0x8];
 	u8         reserved_0[0x18];
 
 	u8         syndrome[0x20];
 
 	u8         reserved_1[0x10];
 	u8         rol_mode[0x8];
 	u8         wol_mode[0x8];
 
 	u8         reserved_2[0x20];
 };
 
 struct mlx5_ifc_query_wol_rol_in_bits {
 	u8         opcode[0x10];
 	u8         reserved_0[0x10];
 
 	u8         reserved_1[0x10];
 	u8         op_mod[0x10];
 
 	u8         reserved_2[0x40];
 };
 
 enum {
 	MLX5_QUERY_VPORT_STATE_OUT_STATE_DOWN  = 0x0,
 	MLX5_QUERY_VPORT_STATE_OUT_STATE_UP    = 0x1,
 };
 
 struct mlx5_ifc_query_vport_state_out_bits {
 	u8         status[0x8];
 	u8         reserved_0[0x18];
 
 	u8         syndrome[0x20];
 
 	u8         reserved_1[0x20];
 
 	u8         reserved_2[0x18];
 	u8         admin_state[0x4];
 	u8         state[0x4];
 };
 
 enum {
 	MLX5_QUERY_VPORT_STATE_IN_OP_MOD_VNIC_VPORT  = 0x0,
 	MLX5_QUERY_VPORT_STATE_IN_OP_MOD_ESW_VPORT   = 0x1,
 	MLX5_QUERY_VPORT_STATE_IN_OP_MOD_UPLINK      = 0x2,
 };
 
 struct mlx5_ifc_query_vport_state_in_bits {
 	u8         opcode[0x10];
 	u8         reserved_0[0x10];
 
 	u8         reserved_1[0x10];
 	u8         op_mod[0x10];
 
 	u8         other_vport[0x1];
 	u8         reserved_2[0xf];
 	u8         vport_number[0x10];
 
 	u8         reserved_3[0x20];
 };
 
 struct mlx5_ifc_query_vport_counter_out_bits {
 	u8         status[0x8];
 	u8         reserved_0[0x18];
 
 	u8         syndrome[0x20];
 
 	u8         reserved_1[0x40];
 
 	struct mlx5_ifc_traffic_counter_bits received_errors;
 
 	struct mlx5_ifc_traffic_counter_bits transmit_errors;
 
 	struct mlx5_ifc_traffic_counter_bits received_ib_unicast;
 
 	struct mlx5_ifc_traffic_counter_bits transmitted_ib_unicast;
 
 	struct mlx5_ifc_traffic_counter_bits received_ib_multicast;
 
 	struct mlx5_ifc_traffic_counter_bits transmitted_ib_multicast;
 
 	struct mlx5_ifc_traffic_counter_bits received_eth_broadcast;
 
 	struct mlx5_ifc_traffic_counter_bits transmitted_eth_broadcast;
 
 	struct mlx5_ifc_traffic_counter_bits received_eth_unicast;
 
 	struct mlx5_ifc_traffic_counter_bits transmitted_eth_unicast;
 
 	struct mlx5_ifc_traffic_counter_bits received_eth_multicast;
 
 	struct mlx5_ifc_traffic_counter_bits transmitted_eth_multicast;
 
 	u8         reserved_2[0xa00];
 };
 
 enum {
 	MLX5_QUERY_VPORT_COUNTER_IN_OP_MOD_VPORT_COUNTERS  = 0x0,
 };
 
 struct mlx5_ifc_query_vport_counter_in_bits {
 	u8         opcode[0x10];
 	u8         reserved_0[0x10];
 
 	u8         reserved_1[0x10];
 	u8         op_mod[0x10];
 
 	u8         other_vport[0x1];
 	u8         reserved_2[0xb];
 	u8         port_num[0x4];
 	u8         vport_number[0x10];
 
 	u8         reserved_3[0x60];
 
 	u8         clear[0x1];
 	u8         reserved_4[0x1f];
 
 	u8         reserved_5[0x20];
 };
 
 struct mlx5_ifc_query_tis_out_bits {
 	u8         status[0x8];
 	u8         reserved_0[0x18];
 
 	u8         syndrome[0x20];
 
 	u8         reserved_1[0x40];
 
 	struct mlx5_ifc_tisc_bits tis_context;
 };
 
 struct mlx5_ifc_query_tis_in_bits {
 	u8         opcode[0x10];
 	u8         reserved_0[0x10];
 
 	u8         reserved_1[0x10];
 	u8         op_mod[0x10];
 
 	u8         reserved_2[0x8];
 	u8         tisn[0x18];
 
 	u8         reserved_3[0x20];
 };
 
 struct mlx5_ifc_query_tir_out_bits {
 	u8         status[0x8];
 	u8         reserved_0[0x18];
 
 	u8         syndrome[0x20];
 
 	u8         reserved_1[0xc0];
 
 	struct mlx5_ifc_tirc_bits tir_context;
 };
 
 struct mlx5_ifc_query_tir_in_bits {
 	u8         opcode[0x10];
 	u8         reserved_0[0x10];
 
 	u8         reserved_1[0x10];
 	u8         op_mod[0x10];
 
 	u8         reserved_2[0x8];
 	u8         tirn[0x18];
 
 	u8         reserved_3[0x20];
 };
 
 struct mlx5_ifc_query_srq_out_bits {
 	u8         status[0x8];
 	u8         reserved_0[0x18];
 
 	u8         syndrome[0x20];
 
 	u8         reserved_1[0x40];
 
 	struct mlx5_ifc_srqc_bits srq_context_entry;
 
 	u8         reserved_2[0x600];
 
 	u8         pas[0][0x40];
 };
 
 struct mlx5_ifc_query_srq_in_bits {
 	u8         opcode[0x10];
 	u8         reserved_0[0x10];
 
 	u8         reserved_1[0x10];
 	u8         op_mod[0x10];
 
 	u8         reserved_2[0x8];
 	u8         srqn[0x18];
 
 	u8         reserved_3[0x20];
 };
 
 struct mlx5_ifc_query_sq_out_bits {
 	u8         status[0x8];
 	u8         reserved_0[0x18];
 
 	u8         syndrome[0x20];
 
 	u8         reserved_1[0xc0];
 
 	struct mlx5_ifc_sqc_bits sq_context;
 };
 
 struct mlx5_ifc_query_sq_in_bits {
 	u8         opcode[0x10];
 	u8         reserved_0[0x10];
 
 	u8         reserved_1[0x10];
 	u8         op_mod[0x10];
 
 	u8         reserved_2[0x8];
 	u8         sqn[0x18];
 
 	u8         reserved_3[0x20];
 };
 
 struct mlx5_ifc_query_special_contexts_out_bits {
 	u8         status[0x8];
 	u8         reserved_0[0x18];
 
 	u8         syndrome[0x20];
 
 	u8	   dump_fill_mkey[0x20];
 
 	u8         resd_lkey[0x20];
 };
 
 struct mlx5_ifc_query_special_contexts_in_bits {
 	u8         opcode[0x10];
 	u8         reserved_0[0x10];
 
 	u8         reserved_1[0x10];
 	u8         op_mod[0x10];
 
 	u8         reserved_2[0x40];
 };
 
 struct mlx5_ifc_query_scheduling_element_out_bits {
 	u8         status[0x8];
 	u8         reserved_at_8[0x18];
 
 	u8         syndrome[0x20];
 
 	u8         reserved_at_40[0xc0];
 
 	struct mlx5_ifc_scheduling_context_bits scheduling_context;
 
 	u8         reserved_at_300[0x100];
 };
 
 enum {
 	MLX5_SCHEDULING_ELEMENT_IN_HIERARCHY_E_SWITCH = 0x2,
 };
 
 struct mlx5_ifc_query_scheduling_element_in_bits {
 	u8         opcode[0x10];
 	u8         reserved_at_10[0x10];
 
 	u8         reserved_at_20[0x10];
 	u8         op_mod[0x10];
 
 	u8         scheduling_hierarchy[0x8];
 	u8         reserved_at_48[0x18];
 
 	u8         scheduling_element_id[0x20];
 
 	u8         reserved_at_80[0x180];
 };
 
 struct mlx5_ifc_query_rqt_out_bits {
 	u8         status[0x8];
 	u8         reserved_0[0x18];
 
 	u8         syndrome[0x20];
 
 	u8         reserved_1[0xc0];
 
 	struct mlx5_ifc_rqtc_bits rqt_context;
 };
 
 struct mlx5_ifc_query_rqt_in_bits {
 	u8         opcode[0x10];
 	u8         reserved_0[0x10];
 
 	u8         reserved_1[0x10];
 	u8         op_mod[0x10];
 
 	u8         reserved_2[0x8];
 	u8         rqtn[0x18];
 
 	u8         reserved_3[0x20];
 };
 
 struct mlx5_ifc_query_rq_out_bits {
 	u8         status[0x8];
 	u8         reserved_0[0x18];
 
 	u8         syndrome[0x20];
 
 	u8         reserved_1[0xc0];
 
 	struct mlx5_ifc_rqc_bits rq_context;
 };
 
 struct mlx5_ifc_query_rq_in_bits {
 	u8         opcode[0x10];
 	u8         reserved_0[0x10];
 
 	u8         reserved_1[0x10];
 	u8         op_mod[0x10];
 
 	u8         reserved_2[0x8];
 	u8         rqn[0x18];
 
 	u8         reserved_3[0x20];
 };
 
 struct mlx5_ifc_query_roce_address_out_bits {
 	u8         status[0x8];
 	u8         reserved_0[0x18];
 
 	u8         syndrome[0x20];
 
 	u8         reserved_1[0x40];
 
 	struct mlx5_ifc_roce_addr_layout_bits roce_address;
 };
 
 struct mlx5_ifc_query_roce_address_in_bits {
 	u8         opcode[0x10];
 	u8         reserved_0[0x10];
 
 	u8         reserved_1[0x10];
 	u8         op_mod[0x10];
 
 	u8         roce_address_index[0x10];
 	u8         reserved_2[0x10];
 
 	u8         reserved_3[0x20];
 };
 
 struct mlx5_ifc_query_rmp_out_bits {
 	u8         status[0x8];
 	u8         reserved_0[0x18];
 
 	u8         syndrome[0x20];
 
 	u8         reserved_1[0xc0];
 
 	struct mlx5_ifc_rmpc_bits rmp_context;
 };
 
 struct mlx5_ifc_query_rmp_in_bits {
 	u8         opcode[0x10];
 	u8         reserved_0[0x10];
 
 	u8         reserved_1[0x10];
 	u8         op_mod[0x10];
 
 	u8         reserved_2[0x8];
 	u8         rmpn[0x18];
 
 	u8         reserved_3[0x20];
 };
 
 struct mlx5_ifc_query_rdb_out_bits {
 	u8         status[0x8];
 	u8         reserved_0[0x18];
 
 	u8         syndrome[0x20];
 
 	u8         reserved_1[0x20];
 
 	u8         reserved_2[0x18];
 	u8         rdb_list_size[0x8];
 
 	struct mlx5_ifc_rdbc_bits rdb_context[0];
 };
 
 struct mlx5_ifc_query_rdb_in_bits {
 	u8         opcode[0x10];
 	u8         reserved_0[0x10];
 
 	u8         reserved_1[0x10];
 	u8         op_mod[0x10];
 
 	u8         reserved_2[0x8];
 	u8         qpn[0x18];
 
 	u8         reserved_3[0x20];
 };
 
 struct mlx5_ifc_query_qp_out_bits {
 	u8         status[0x8];
 	u8         reserved_0[0x18];
 
 	u8         syndrome[0x20];
 
 	u8         reserved_1[0x40];
 
 	u8         opt_param_mask[0x20];
 
 	u8         reserved_2[0x20];
 
 	struct mlx5_ifc_qpc_bits qpc;
 
 	u8         reserved_3[0x80];
 
 	u8         pas[0][0x40];
 };
 
 struct mlx5_ifc_query_qp_in_bits {
 	u8         opcode[0x10];
 	u8         reserved_0[0x10];
 
 	u8         reserved_1[0x10];
 	u8         op_mod[0x10];
 
 	u8         reserved_2[0x8];
 	u8         qpn[0x18];
 
 	u8         reserved_3[0x20];
 };
 
 struct mlx5_ifc_query_q_counter_out_bits {
 	u8         status[0x8];
 	u8         reserved_0[0x18];
 
 	u8         syndrome[0x20];
 
 	u8         reserved_1[0x40];
 
 	u8         rx_write_requests[0x20];
 
 	u8         reserved_2[0x20];
 
 	u8         rx_read_requests[0x20];
 
 	u8         reserved_3[0x20];
 
 	u8         rx_atomic_requests[0x20];
 
 	u8         reserved_4[0x20];
 
 	u8         rx_dct_connect[0x20];
 
 	u8         reserved_5[0x20];
 
 	u8         out_of_buffer[0x20];
 
 	u8         reserved_7[0x20];
 
 	u8         out_of_sequence[0x20];
 
 	u8         reserved_8[0x20];
 
 	u8         duplicate_request[0x20];
 
 	u8         reserved_9[0x20];
 
 	u8         rnr_nak_retry_err[0x20];
 
 	u8         reserved_10[0x20];
 
 	u8         packet_seq_err[0x20];
 
 	u8         reserved_11[0x20];
 
 	u8         implied_nak_seq_err[0x20];
 
 	u8         reserved_12[0x20];
 
 	u8         local_ack_timeout_err[0x20];
 
 	u8         reserved_13[0x20];
 
 	u8         resp_rnr_nak[0x20];
 
 	u8         reserved_14[0x20];
 
 	u8         req_rnr_retries_exceeded[0x20];
 
 	u8         reserved_15[0x460];
 };
 
 struct mlx5_ifc_query_q_counter_in_bits {
 	u8         opcode[0x10];
 	u8         reserved_0[0x10];
 
 	u8         reserved_1[0x10];
 	u8         op_mod[0x10];
 
 	u8         reserved_2[0x80];
 
 	u8         clear[0x1];
 	u8         reserved_3[0x1f];
 
 	u8         reserved_4[0x18];
 	u8         counter_set_id[0x8];
 };
 
 struct mlx5_ifc_query_pages_out_bits {
 	u8         status[0x8];
 	u8         reserved_0[0x18];
 
 	u8         syndrome[0x20];
 
 	u8         reserved_1[0x10];
 	u8         function_id[0x10];
 
 	u8         num_pages[0x20];
 };
 
 enum {
 	MLX5_QUERY_PAGES_IN_OP_MOD_BOOT_PAGES	  = 0x1,
 	MLX5_QUERY_PAGES_IN_OP_MOD_INIT_PAGES	  = 0x2,
 	MLX5_QUERY_PAGES_IN_OP_MOD_REGULAR_PAGES  = 0x3,
 };
 
 struct mlx5_ifc_query_pages_in_bits {
 	u8         opcode[0x10];
 	u8         reserved_0[0x10];
 
 	u8         reserved_1[0x10];
 	u8         op_mod[0x10];
 
 	u8         reserved_2[0x10];
 	u8         function_id[0x10];
 
 	u8         reserved_3[0x20];
 };
 
 struct mlx5_ifc_query_nic_vport_context_out_bits {
 	u8         status[0x8];
 	u8         reserved_0[0x18];
 
 	u8         syndrome[0x20];
 
 	u8         reserved_1[0x40];
 
 	struct mlx5_ifc_nic_vport_context_bits nic_vport_context;
 };
 
 struct mlx5_ifc_query_nic_vport_context_in_bits {
 	u8         opcode[0x10];
 	u8         reserved_0[0x10];
 
 	u8         reserved_1[0x10];
 	u8         op_mod[0x10];
 
 	u8         other_vport[0x1];
 	u8         reserved_2[0xf];
 	u8         vport_number[0x10];
 
 	u8         reserved_3[0x5];
 	u8         allowed_list_type[0x3];
 	u8         reserved_4[0x18];
 };
 
 struct mlx5_ifc_query_mkey_out_bits {
 	u8         status[0x8];
 	u8         reserved_0[0x18];
 
 	u8         syndrome[0x20];
 
 	u8         reserved_1[0x40];
 
 	struct mlx5_ifc_mkc_bits memory_key_mkey_entry;
 
 	u8         reserved_2[0x600];
 
 	u8         bsf0_klm0_pas_mtt0_1[16][0x8];
 
 	u8         bsf1_klm1_pas_mtt2_3[16][0x8];
 };
 
 struct mlx5_ifc_query_mkey_in_bits {
 	u8         opcode[0x10];
 	u8         reserved_0[0x10];
 
 	u8         reserved_1[0x10];
 	u8         op_mod[0x10];
 
 	u8         reserved_2[0x8];
 	u8         mkey_index[0x18];
 
 	u8         pg_access[0x1];
 	u8         reserved_3[0x1f];
 };
 
 struct mlx5_ifc_query_mad_demux_out_bits {
 	u8         status[0x8];
 	u8         reserved_0[0x18];
 
 	u8         syndrome[0x20];
 
 	u8         reserved_1[0x40];
 
 	u8         mad_dumux_parameters_block[0x20];
 };
 
 struct mlx5_ifc_query_mad_demux_in_bits {
 	u8         opcode[0x10];
 	u8         reserved_0[0x10];
 
 	u8         reserved_1[0x10];
 	u8         op_mod[0x10];
 
 	u8         reserved_2[0x40];
 };
 
 struct mlx5_ifc_query_l2_table_entry_out_bits {
 	u8         status[0x8];
 	u8         reserved_0[0x18];
 
 	u8         syndrome[0x20];
 
 	u8         reserved_1[0xa0];
 
 	u8         reserved_2[0x13];
 	u8         vlan_valid[0x1];
 	u8         vlan[0xc];
 
 	struct mlx5_ifc_mac_address_layout_bits mac_address;
 
 	u8         reserved_3[0xc0];
 };
 
 struct mlx5_ifc_query_l2_table_entry_in_bits {
 	u8         opcode[0x10];
 	u8         reserved_0[0x10];
 
 	u8         reserved_1[0x10];
 	u8         op_mod[0x10];
 
 	u8         reserved_2[0x60];
 
 	u8         reserved_3[0x8];
 	u8         table_index[0x18];
 
 	u8         reserved_4[0x140];
 };
 
 struct mlx5_ifc_query_issi_out_bits {
 	u8         status[0x8];
 	u8         reserved_0[0x18];
 
 	u8         syndrome[0x20];
 
 	u8         reserved_1[0x10];
 	u8         current_issi[0x10];
 
 	u8         reserved_2[0xa0];
 
 	u8         supported_issi_reserved[76][0x8];
 	u8         supported_issi_dw0[0x20];
 };
 
 struct mlx5_ifc_query_issi_in_bits {
 	u8         opcode[0x10];
 	u8         reserved_0[0x10];
 
 	u8         reserved_1[0x10];
 	u8         op_mod[0x10];
 
 	u8         reserved_2[0x40];
 };
 
 struct mlx5_ifc_query_hca_vport_pkey_out_bits {
 	u8         status[0x8];
 	u8         reserved_0[0x18];
 
 	u8         syndrome[0x20];
 
 	u8         reserved_1[0x40];
 
 	struct mlx5_ifc_pkey_bits pkey[0];
 };
 
 struct mlx5_ifc_query_hca_vport_pkey_in_bits {
 	u8         opcode[0x10];
 	u8         reserved_0[0x10];
 
 	u8         reserved_1[0x10];
 	u8         op_mod[0x10];
 
 	u8         other_vport[0x1];
 	u8         reserved_2[0xb];
 	u8         port_num[0x4];
 	u8         vport_number[0x10];
 
 	u8         reserved_3[0x10];
 	u8         pkey_index[0x10];
 };
 
 struct mlx5_ifc_query_hca_vport_gid_out_bits {
 	u8         status[0x8];
 	u8         reserved_0[0x18];
 
 	u8         syndrome[0x20];
 
 	u8         reserved_1[0x20];
 
 	u8         gids_num[0x10];
 	u8         reserved_2[0x10];
 
 	struct mlx5_ifc_array128_auto_bits gid[0];
 };
 
 struct mlx5_ifc_query_hca_vport_gid_in_bits {
 	u8         opcode[0x10];
 	u8         reserved_0[0x10];
 
 	u8         reserved_1[0x10];
 	u8         op_mod[0x10];
 
 	u8         other_vport[0x1];
 	u8         reserved_2[0xb];
 	u8         port_num[0x4];
 	u8         vport_number[0x10];
 
 	u8         reserved_3[0x10];
 	u8         gid_index[0x10];
 };
 
 struct mlx5_ifc_query_hca_vport_context_out_bits {
 	u8         status[0x8];
 	u8         reserved_0[0x18];
 
 	u8         syndrome[0x20];
 
 	u8         reserved_1[0x40];
 
 	struct mlx5_ifc_hca_vport_context_bits hca_vport_context;
 };
 
 struct mlx5_ifc_query_hca_vport_context_in_bits {
 	u8         opcode[0x10];
 	u8         reserved_0[0x10];
 
 	u8         reserved_1[0x10];
 	u8         op_mod[0x10];
 
 	u8         other_vport[0x1];
 	u8         reserved_2[0xb];
 	u8         port_num[0x4];
 	u8         vport_number[0x10];
 
 	u8         reserved_3[0x20];
 };
 
 struct mlx5_ifc_query_hca_cap_out_bits {
 	u8         status[0x8];
 	u8         reserved_0[0x18];
 
 	u8         syndrome[0x20];
 
 	u8         reserved_1[0x40];
 
 	union mlx5_ifc_hca_cap_union_bits capability;
 };
 
 struct mlx5_ifc_query_hca_cap_in_bits {
 	u8         opcode[0x10];
 	u8         reserved_0[0x10];
 
 	u8         reserved_1[0x10];
 	u8         op_mod[0x10];
 
 	u8         reserved_2[0x40];
 };
 
 struct mlx5_ifc_query_flow_table_out_bits {
 	u8         status[0x8];
 	u8         reserved_at_8[0x18];
 
 	u8         syndrome[0x20];
 
 	u8         reserved_at_40[0x80];
 
 	struct mlx5_ifc_flow_table_context_bits flow_table_context;
 };
 
 struct mlx5_ifc_query_flow_table_in_bits {
 	u8         opcode[0x10];
 	u8         reserved_0[0x10];
 
 	u8         reserved_1[0x10];
 	u8         op_mod[0x10];
 
 	u8         other_vport[0x1];
 	u8         reserved_2[0xf];
 	u8         vport_number[0x10];
 
 	u8         reserved_3[0x20];
 
 	u8         table_type[0x8];
 	u8         reserved_4[0x18];
 
 	u8         reserved_5[0x8];
 	u8         table_id[0x18];
 
 	u8         reserved_6[0x140];
 };
 
 struct mlx5_ifc_query_fte_out_bits {
 	u8         status[0x8];
 	u8         reserved_0[0x18];
 
 	u8         syndrome[0x20];
 
 	u8         reserved_1[0x1c0];
 
 	struct mlx5_ifc_flow_context_bits flow_context;
 };
 
 struct mlx5_ifc_query_fte_in_bits {
 	u8         opcode[0x10];
 	u8         reserved_0[0x10];
 
 	u8         reserved_1[0x10];
 	u8         op_mod[0x10];
 
 	u8         other_vport[0x1];
 	u8         reserved_2[0xf];
 	u8         vport_number[0x10];
 
 	u8         reserved_3[0x20];
 
 	u8         table_type[0x8];
 	u8         reserved_4[0x18];
 
 	u8         reserved_5[0x8];
 	u8         table_id[0x18];
 
 	u8         reserved_6[0x40];
 
 	u8         flow_index[0x20];
 
 	u8         reserved_7[0xe0];
 };
 
 enum {
 	MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_OUTER_HEADERS    = 0x0,
 	MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS  = 0x1,
 	MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_INNER_HEADERS    = 0x2,
 };
 
 struct mlx5_ifc_query_flow_group_out_bits {
 	u8         status[0x8];
 	u8         reserved_0[0x18];
 
 	u8         syndrome[0x20];
 
 	u8         reserved_1[0xa0];
 
 	u8         start_flow_index[0x20];
 
 	u8         reserved_2[0x20];
 
 	u8         end_flow_index[0x20];
 
 	u8         reserved_3[0xa0];
 
 	u8         reserved_4[0x18];
 	u8         match_criteria_enable[0x8];
 
 	struct mlx5_ifc_fte_match_param_bits match_criteria;
 
 	u8         reserved_5[0xe00];
 };
 
 struct mlx5_ifc_query_flow_group_in_bits {
 	u8         opcode[0x10];
 	u8         reserved_0[0x10];
 
 	u8         reserved_1[0x10];
 	u8         op_mod[0x10];
 
 	u8         other_vport[0x1];
 	u8         reserved_2[0xf];
 	u8         vport_number[0x10];
 
 	u8         reserved_3[0x20];
 
 	u8         table_type[0x8];
 	u8         reserved_4[0x18];
 
 	u8         reserved_5[0x8];
 	u8         table_id[0x18];
 
 	u8         group_id[0x20];
 
 	u8         reserved_6[0x120];
 };
 
 struct mlx5_ifc_query_flow_counter_out_bits {
 	u8         status[0x8];
 	u8         reserved_at_8[0x18];
 
 	u8         syndrome[0x20];
 
 	u8         reserved_at_40[0x40];
 
 	struct mlx5_ifc_traffic_counter_bits flow_statistics[0];
 };
 
 struct mlx5_ifc_query_flow_counter_in_bits {
 	u8         opcode[0x10];
 	u8         reserved_at_10[0x10];
 
 	u8         reserved_at_20[0x10];
 	u8         op_mod[0x10];
 
 	u8         reserved_at_40[0x80];
 
 	u8         clear[0x1];
 	u8         reserved_at_c1[0xf];
 	u8         num_of_counters[0x10];
 
 	u8         reserved_at_e0[0x10];
 	u8         flow_counter_id[0x10];
 };
 
 struct mlx5_ifc_query_esw_vport_context_out_bits {
 	u8         status[0x8];
 	u8         reserved_0[0x18];
 
 	u8         syndrome[0x20];
 
 	u8         reserved_1[0x40];
 
 	struct mlx5_ifc_esw_vport_context_bits esw_vport_context;
 };
 
 struct mlx5_ifc_query_esw_vport_context_in_bits {
 	u8         opcode[0x10];
 	u8         reserved_0[0x10];
 
 	u8         reserved_1[0x10];
 	u8         op_mod[0x10];
 
 	u8         other_vport[0x1];
 	u8         reserved_2[0xf];
 	u8         vport_number[0x10];
 
 	u8         reserved_3[0x20];
 };
 
 struct mlx5_ifc_query_eq_out_bits {
 	u8         status[0x8];
 	u8         reserved_0[0x18];
 
 	u8         syndrome[0x20];
 
 	u8         reserved_1[0x40];
 
 	struct mlx5_ifc_eqc_bits eq_context_entry;
 
 	u8         reserved_2[0x40];
 
 	u8         event_bitmask[0x40];
 
 	u8         reserved_3[0x580];
 
 	u8         pas[0][0x40];
 };
 
 struct mlx5_ifc_query_eq_in_bits {
 	u8         opcode[0x10];
 	u8         reserved_0[0x10];
 
 	u8         reserved_1[0x10];
 	u8         op_mod[0x10];
 
 	u8         reserved_2[0x18];
 	u8         eq_number[0x8];
 
 	u8         reserved_3[0x20];
 };
 
 struct mlx5_ifc_query_dct_out_bits {
 	u8         status[0x8];
 	u8         reserved_0[0x18];
 
 	u8         syndrome[0x20];
 
 	u8         reserved_1[0x40];
 
 	struct mlx5_ifc_dctc_bits dct_context_entry;
 
 	u8         reserved_2[0x180];
 };
 
 struct mlx5_ifc_query_dct_in_bits {
 	u8         opcode[0x10];
 	u8         reserved_0[0x10];
 
 	u8         reserved_1[0x10];
 	u8         op_mod[0x10];
 
 	u8         reserved_2[0x8];
 	u8         dctn[0x18];
 
 	u8         reserved_3[0x20];
 };
 
 struct mlx5_ifc_query_dc_cnak_trace_out_bits {
 	u8         status[0x8];
 	u8         reserved_0[0x18];
 
 	u8         syndrome[0x20];
 
 	u8         enable[0x1];
 	u8         reserved_1[0x1f];
 
 	u8         reserved_2[0x160];
 
 	struct mlx5_ifc_cmd_pas_bits pas;
 };
 
 struct mlx5_ifc_query_dc_cnak_trace_in_bits {
 	u8         opcode[0x10];
 	u8         reserved_0[0x10];
 
 	u8         reserved_1[0x10];
 	u8         op_mod[0x10];
 
 	u8         reserved_2[0x40];
 };
 
 struct mlx5_ifc_query_cq_out_bits {
 	u8         status[0x8];
 	u8         reserved_0[0x18];
 
 	u8         syndrome[0x20];
 
 	u8         reserved_1[0x40];
 
 	struct mlx5_ifc_cqc_bits cq_context;
 
 	u8         reserved_2[0x600];
 
 	u8         pas[0][0x40];
 };
 
 struct mlx5_ifc_query_cq_in_bits {
 	u8         opcode[0x10];
 	u8         reserved_0[0x10];
 
 	u8         reserved_1[0x10];
 	u8         op_mod[0x10];
 
 	u8         reserved_2[0x8];
 	u8         cqn[0x18];
 
 	u8         reserved_3[0x20];
 };
 
 struct mlx5_ifc_query_cong_status_out_bits {
 	u8         status[0x8];
 	u8         reserved_0[0x18];
 
 	u8         syndrome[0x20];
 
 	u8         reserved_1[0x20];
 
 	u8         enable[0x1];
 	u8         tag_enable[0x1];
 	u8         reserved_2[0x1e];
 };
 
 struct mlx5_ifc_query_cong_status_in_bits {
 	u8         opcode[0x10];
 	u8         reserved_0[0x10];
 
 	u8         reserved_1[0x10];
 	u8         op_mod[0x10];
 
 	u8         reserved_2[0x18];
 	u8         priority[0x4];
 	u8         cong_protocol[0x4];
 
 	u8         reserved_3[0x20];
 };
 
 struct mlx5_ifc_query_cong_statistics_out_bits {
 	u8         status[0x8];
 	u8         reserved_0[0x18];
 
 	u8         syndrome[0x20];
 
 	u8         reserved_1[0x40];
 
 	u8         rp_cur_flows[0x20];
 
 	u8         sum_flows[0x20];
 
 	u8         rp_cnp_ignored_high[0x20];
 
 	u8         rp_cnp_ignored_low[0x20];
 
 	u8         rp_cnp_handled_high[0x20];
 
 	u8         rp_cnp_handled_low[0x20];
 
 	u8         reserved_2[0x100];
 
 	u8         time_stamp_high[0x20];
 
 	u8         time_stamp_low[0x20];
 
 	u8         accumulators_period[0x20];
 
 	u8         np_ecn_marked_roce_packets_high[0x20];
 
 	u8         np_ecn_marked_roce_packets_low[0x20];
 
 	u8         np_cnp_sent_high[0x20];
 
 	u8         np_cnp_sent_low[0x20];
 
 	u8         reserved_3[0x560];
 };
 
 struct mlx5_ifc_query_cong_statistics_in_bits {
 	u8         opcode[0x10];
 	u8         reserved_0[0x10];
 
 	u8         reserved_1[0x10];
 	u8         op_mod[0x10];
 
 	u8         clear[0x1];
 	u8         reserved_2[0x1f];
 
 	u8         reserved_3[0x20];
 };
 
 struct mlx5_ifc_query_cong_params_out_bits {
 	u8         status[0x8];
 	u8         reserved_0[0x18];
 
 	u8         syndrome[0x20];
 
 	u8         reserved_1[0x40];
 
 	union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters;
 };
 
 struct mlx5_ifc_query_cong_params_in_bits {
 	u8         opcode[0x10];
 	u8         reserved_0[0x10];
 
 	u8         reserved_1[0x10];
 	u8         op_mod[0x10];
 
 	u8         reserved_2[0x1c];
 	u8         cong_protocol[0x4];
 
 	u8         reserved_3[0x20];
 };
 
 struct mlx5_ifc_query_burst_size_out_bits {
 	u8         status[0x8];
 	u8         reserved_0[0x18];
 
 	u8         syndrome[0x20];
 
 	u8         reserved_1[0x20];
 
 	u8         reserved_2[0x9];
 	u8         device_burst_size[0x17];
 };
 
 struct mlx5_ifc_query_burst_size_in_bits {
 	u8         opcode[0x10];
 	u8         reserved_0[0x10];
 
 	u8         reserved_1[0x10];
 	u8         op_mod[0x10];
 
 	u8         reserved_2[0x40];
 };
 
 struct mlx5_ifc_query_adapter_out_bits {
 	u8         status[0x8];
 	u8         reserved_0[0x18];
 
 	u8         syndrome[0x20];
 
 	u8         reserved_1[0x40];
 
 	struct mlx5_ifc_query_adapter_param_block_bits query_adapter_struct;
 };
 
 struct mlx5_ifc_query_adapter_in_bits {
 	u8         opcode[0x10];
 	u8         reserved_0[0x10];
 
 	u8         reserved_1[0x10];
 	u8         op_mod[0x10];
 
 	u8         reserved_2[0x40];
 };
 
 struct mlx5_ifc_qp_2rst_out_bits {
 	u8         status[0x8];
 	u8         reserved_0[0x18];
 
 	u8         syndrome[0x20];
 
 	u8         reserved_1[0x40];
 };
 
 struct mlx5_ifc_qp_2rst_in_bits {
 	u8         opcode[0x10];
 	u8         reserved_0[0x10];
 
 	u8         reserved_1[0x10];
 	u8         op_mod[0x10];
 
 	u8         reserved_2[0x8];
 	u8         qpn[0x18];
 
 	u8         reserved_3[0x20];
 };
 
 struct mlx5_ifc_qp_2err_out_bits {
 	u8         status[0x8];
 	u8         reserved_0[0x18];
 
 	u8         syndrome[0x20];
 
 	u8         reserved_1[0x40];
 };
 
 struct mlx5_ifc_qp_2err_in_bits {
 	u8         opcode[0x10];
 	u8         reserved_0[0x10];
 
 	u8         reserved_1[0x10];
 	u8         op_mod[0x10];
 
 	u8         reserved_2[0x8];
 	u8         qpn[0x18];
 
 	u8         reserved_3[0x20];
 };
 
 struct mlx5_ifc_para_vport_element_bits {
 	u8         reserved_at_0[0xc];
 	u8         traffic_class[0x4];
 	u8         qos_para_vport_number[0x10];
 };
 
 struct mlx5_ifc_page_fault_resume_out_bits {
 	u8         status[0x8];
 	u8         reserved_0[0x18];
 
 	u8         syndrome[0x20];
 
 	u8         reserved_1[0x40];
 };
 
 struct mlx5_ifc_page_fault_resume_in_bits {
 	u8         opcode[0x10];
 	u8         reserved_0[0x10];
 
 	u8         reserved_1[0x10];
 	u8         op_mod[0x10];
 
 	u8         error[0x1];
 	u8         reserved_2[0x4];
 	u8         rdma[0x1];
 	u8         read_write[0x1];
 	u8         req_res[0x1];
 	u8         qpn[0x18];
 
 	u8         reserved_3[0x20];
 };
 
 struct mlx5_ifc_nop_out_bits {
 	u8         status[0x8];
 	u8         reserved_0[0x18];
 
 	u8         syndrome[0x20];
 
 	u8         reserved_1[0x40];
 };
 
 struct mlx5_ifc_nop_in_bits {
 	u8         opcode[0x10];
 	u8         reserved_0[0x10];
 
 	u8         reserved_1[0x10];
 	u8         op_mod[0x10];
 
 	u8         reserved_2[0x40];
 };
 
 struct mlx5_ifc_modify_vport_state_out_bits {
 	u8         status[0x8];
 	u8         reserved_0[0x18];
 
 	u8         syndrome[0x20];
 
 	u8         reserved_1[0x40];
 };
 
 enum {
 	MLX5_MODIFY_VPORT_STATE_IN_OP_MOD_NIC_VPORT  = 0x0,
 	MLX5_MODIFY_VPORT_STATE_IN_OP_MOD_ESW_VPORT  = 0x1,
 	MLX5_MODIFY_VPORT_STATE_IN_OP_MOD_UPLINK     = 0x2,
 };
 
 enum {
 	MLX5_MODIFY_VPORT_STATE_IN_ADMIN_STATE_DOWN    = 0x0,
 	MLX5_MODIFY_VPORT_STATE_IN_ADMIN_STATE_UP      = 0x1,
 	MLX5_MODIFY_VPORT_STATE_IN_ADMIN_STATE_FOLLOW  = 0x2,
 };
 
 struct mlx5_ifc_modify_vport_state_in_bits {
 	u8         opcode[0x10];
 	u8         reserved_0[0x10];
 
 	u8         reserved_1[0x10];
 	u8         op_mod[0x10];
 
 	u8         other_vport[0x1];
 	u8         reserved_2[0xf];
 	u8         vport_number[0x10];
 
 	u8         reserved_3[0x18];
 	u8         admin_state[0x4];
 	u8         reserved_4[0x4];
 };
 
 struct mlx5_ifc_modify_tis_out_bits {
 	u8         status[0x8];
 	u8         reserved_0[0x18];
 
 	u8         syndrome[0x20];
 
 	u8         reserved_1[0x40];
 };
 
 struct mlx5_ifc_modify_tis_bitmask_bits {
 	u8         reserved_at_0[0x20];
 
 	u8         reserved_at_20[0x1d];
 	u8         lag_tx_port_affinity[0x1];
 	u8         strict_lag_tx_port_affinity[0x1];
 	u8         prio[0x1];
 };
 
 struct mlx5_ifc_modify_tis_in_bits {
 	u8         opcode[0x10];
 	u8         reserved_0[0x10];
 
 	u8         reserved_1[0x10];
 	u8         op_mod[0x10];
 
 	u8         reserved_2[0x8];
 	u8         tisn[0x18];
 
 	u8         reserved_3[0x20];
 
 	struct mlx5_ifc_modify_tis_bitmask_bits bitmask;
 
 	u8         reserved_4[0x40];
 
 	struct mlx5_ifc_tisc_bits ctx;
 };
 
 struct mlx5_ifc_modify_tir_out_bits {
 	u8         status[0x8];
 	u8         reserved_0[0x18];
 
 	u8         syndrome[0x20];
 
 	u8         reserved_1[0x40];
 };
 
 enum
 {
 	MLX5_MODIFY_SQ_BITMASK_PACKET_PACING_RATE_LIMIT_INDEX = 0x1 << 0,
 	MLX5_MODIFY_SQ_BITMASK_QOS_PARA_VPORT_NUMBER =		0x1 << 1
 };
 
 struct mlx5_ifc_modify_tir_in_bits {
 	u8         opcode[0x10];
 	u8         reserved_0[0x10];
 
 	u8         reserved_1[0x10];
 	u8         op_mod[0x10];
 
 	u8         reserved_2[0x8];
 	u8         tirn[0x18];
 
 	u8         reserved_3[0x20];
 
 	u8         modify_bitmask[0x40];
 
 	u8         reserved_4[0x40];
 
 	struct mlx5_ifc_tirc_bits tir_context;
 };
 
 struct mlx5_ifc_modify_sq_out_bits {
 	u8         status[0x8];
 	u8         reserved_0[0x18];
 
 	u8         syndrome[0x20];
 
 	u8         reserved_1[0x40];
 };
 
 struct mlx5_ifc_modify_sq_in_bits {
 	u8         opcode[0x10];
 	u8         reserved_0[0x10];
 
 	u8         reserved_1[0x10];
 	u8         op_mod[0x10];
 
 	u8         sq_state[0x4];
 	u8         reserved_2[0x4];
 	u8         sqn[0x18];
 
 	u8         reserved_3[0x20];
 
 	u8         modify_bitmask[0x40];
 
 	u8         reserved_4[0x40];
 
 	struct mlx5_ifc_sqc_bits ctx;
 };
 
 struct mlx5_ifc_modify_scheduling_element_out_bits {
 	u8         status[0x8];
 	u8         reserved_at_8[0x18];
 
 	u8         syndrome[0x20];
 
 	u8         reserved_at_40[0x1c0];
 };
 
 enum {
 	MLX5_MODIFY_SCHEDULING_ELEMENT_IN_SCHEDULING_HIERARCHY_E_SWITCH  = 0x2,
 };
 
 enum {
 	MLX5_MODIFY_SCHEDULING_ELEMENT_BITMASK_BW_SHARE        = 0x1,
 	MLX5_MODIFY_SCHEDULING_ELEMENT_BITMASK_MAX_AVERAGE_BW  = 0x2,
 };
 
 struct mlx5_ifc_modify_scheduling_element_in_bits {
 	u8         opcode[0x10];
 	u8         reserved_at_10[0x10];
 
 	u8         reserved_at_20[0x10];
 	u8         op_mod[0x10];
 
 	u8         scheduling_hierarchy[0x8];
 	u8         reserved_at_48[0x18];
 
 	u8         scheduling_element_id[0x20];
 
 	u8         reserved_at_80[0x20];
 
 	u8         modify_bitmask[0x20];
 
 	u8         reserved_at_c0[0x40];
 
 	struct mlx5_ifc_scheduling_context_bits scheduling_context;
 
 	u8         reserved_at_300[0x100];
 };
 
 struct mlx5_ifc_modify_rqt_out_bits {
 	u8         status[0x8];
 	u8         reserved_0[0x18];
 
 	u8         syndrome[0x20];
 
 	u8         reserved_1[0x40];
 };
 
 struct mlx5_ifc_modify_rqt_in_bits {
 	u8         opcode[0x10];
 	u8         reserved_0[0x10];
 
 	u8         reserved_1[0x10];
 	u8         op_mod[0x10];
 
 	u8         reserved_2[0x8];
 	u8         rqtn[0x18];
 
 	u8         reserved_3[0x20];
 
 	u8         modify_bitmask[0x40];
 
 	u8         reserved_4[0x40];
 
 	struct mlx5_ifc_rqtc_bits ctx;
 };
 
 struct mlx5_ifc_modify_rq_out_bits {
 	u8         status[0x8];
 	u8         reserved_0[0x18];
 
 	u8         syndrome[0x20];
 
 	u8         reserved_1[0x40];
 };
 
 enum {
 	MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD = 1ULL << 1,
 	MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_MODIFY_RQ_COUNTER_SET_ID = 1ULL << 3,
 };
 
 struct mlx5_ifc_modify_rq_in_bits {
 	u8         opcode[0x10];
 	u8         reserved_0[0x10];
 
 	u8         reserved_1[0x10];
 	u8         op_mod[0x10];
 
 	u8         rq_state[0x4];
 	u8         reserved_2[0x4];
 	u8         rqn[0x18];
 
 	u8         reserved_3[0x20];
 
 	u8         modify_bitmask[0x40];
 
 	u8         reserved_4[0x40];
 
 	struct mlx5_ifc_rqc_bits ctx;
 };
 
 struct mlx5_ifc_modify_rmp_out_bits {
 	u8         status[0x8];
 	u8         reserved_0[0x18];
 
 	u8         syndrome[0x20];
 
 	u8         reserved_1[0x40];
 };
 
 struct mlx5_ifc_rmp_bitmask_bits {
 	u8	   reserved[0x20];
 
 	u8         reserved1[0x1f];
 	u8         lwm[0x1];
 };
 
 struct mlx5_ifc_modify_rmp_in_bits {
 	u8         opcode[0x10];
 	u8         reserved_0[0x10];
 
 	u8         reserved_1[0x10];
 	u8         op_mod[0x10];
 
 	u8         rmp_state[0x4];
 	u8         reserved_2[0x4];
 	u8         rmpn[0x18];
 
 	u8         reserved_3[0x20];
 
 	struct mlx5_ifc_rmp_bitmask_bits bitmask;
 
 	u8         reserved_4[0x40];
 
 	struct mlx5_ifc_rmpc_bits ctx;
 };
 
 struct mlx5_ifc_modify_nic_vport_context_out_bits {
 	u8         status[0x8];
 	u8         reserved_0[0x18];
 
 	u8         syndrome[0x20];
 
 	u8         reserved_1[0x40];
 };
 
 struct mlx5_ifc_modify_nic_vport_field_select_bits {
 	u8         reserved_0[0x14];
 	u8         disable_uc_local_lb[0x1];
 	u8         disable_mc_local_lb[0x1];
 	u8         node_guid[0x1];
 	u8         port_guid[0x1];
 	u8         min_wqe_inline_mode[0x1];
 	u8         mtu[0x1];
 	u8         change_event[0x1];
 	u8         promisc[0x1];
 	u8         permanent_address[0x1];
 	u8         addresses_list[0x1];
 	u8         roce_en[0x1];
 	u8         reserved_1[0x1];
 };
 
 struct mlx5_ifc_modify_nic_vport_context_in_bits {
 	u8         opcode[0x10];
 	u8         reserved_0[0x10];
 
 	u8         reserved_1[0x10];
 	u8         op_mod[0x10];
 
 	u8         other_vport[0x1];
 	u8         reserved_2[0xf];
 	u8         vport_number[0x10];
 
 	struct mlx5_ifc_modify_nic_vport_field_select_bits field_select;
 
 	u8         reserved_3[0x780];
 
 	struct mlx5_ifc_nic_vport_context_bits nic_vport_context;
 };
 
 struct mlx5_ifc_modify_hca_vport_context_out_bits {
 	u8         status[0x8];
 	u8         reserved_0[0x18];
 
 	u8         syndrome[0x20];
 
 	u8         reserved_1[0x40];
 };
 
 struct mlx5_ifc_grh_bits {
 	u8	ip_version[4];
 	u8	traffic_class[8];
 	u8	flow_label[20];
 	u8	payload_length[16];
 	u8	next_header[8];
 	u8	hop_limit[8];
 	u8	sgid[128];
 	u8	dgid[128];
 };
 
 struct mlx5_ifc_bth_bits {
 	u8	opcode[8];
 	u8	se[1];
 	u8	migreq[1];
 	u8	pad_count[2];
 	u8	tver[4];
 	u8	p_key[16];
 	u8	reserved8[8];
 	u8	dest_qp[24];
 	u8	ack_req[1];
 	u8	reserved7[7];
 	u8	psn[24];
 };
 
 struct mlx5_ifc_aeth_bits {
 	u8	syndrome[8];
 	u8	msn[24];
 };
 
 struct mlx5_ifc_dceth_bits {
 	u8	reserved0[8];
 	u8	session_id[24];
 	u8	reserved1[8];
 	u8	dci_dct[24];
 };
 
 struct mlx5_ifc_modify_hca_vport_context_in_bits {
 	u8         opcode[0x10];
 	u8         reserved_0[0x10];
 
 	u8         reserved_1[0x10];
 	u8         op_mod[0x10];
 
 	u8         other_vport[0x1];
 	u8         reserved_2[0xb];
 	u8         port_num[0x4];
 	u8         vport_number[0x10];
 
 	u8         reserved_3[0x20];
 
 	struct mlx5_ifc_hca_vport_context_bits hca_vport_context;
 };
 
 struct mlx5_ifc_modify_flow_table_out_bits {
 	u8         status[0x8];
 	u8         reserved_at_8[0x18];
 
 	u8         syndrome[0x20];
 
 	u8         reserved_at_40[0x40];
 };
 
 enum {
 	MLX5_MODIFY_FLOW_TABLE_SELECT_MISS_ACTION_AND_ID = 0x1,
 	MLX5_MODIFY_FLOW_TABLE_SELECT_LAG_MASTER_NEXT_TABLE_ID = 0x8000,
 };
 
 struct mlx5_ifc_modify_flow_table_in_bits {
 	u8         opcode[0x10];
 	u8         reserved_at_10[0x10];
 
 	u8         reserved_at_20[0x10];
 	u8         op_mod[0x10];
 
 	u8         other_vport[0x1];
 	u8         reserved_at_41[0xf];
 	u8         vport_number[0x10];
 
 	u8         reserved_at_60[0x10];
 	u8         modify_field_select[0x10];
 
 	u8         table_type[0x8];
 	u8         reserved_at_88[0x18];
 
 	u8         reserved_at_a0[0x8];
 	u8         table_id[0x18];
 
 	struct mlx5_ifc_flow_table_context_bits flow_table_context;
 };
 
 struct mlx5_ifc_modify_esw_vport_context_out_bits {
 	u8         status[0x8];
 	u8         reserved_0[0x18];
 
 	u8         syndrome[0x20];
 
 	u8         reserved_1[0x40];
 };
 
 struct mlx5_ifc_esw_vport_context_fields_select_bits {
 	u8         reserved[0x1c];
 	u8         vport_cvlan_insert[0x1];
 	u8         vport_svlan_insert[0x1];
 	u8         vport_cvlan_strip[0x1];
 	u8         vport_svlan_strip[0x1];
 };
 
 struct mlx5_ifc_modify_esw_vport_context_in_bits {
 	u8         opcode[0x10];
 	u8         reserved_0[0x10];
 
 	u8         reserved_1[0x10];
 	u8         op_mod[0x10];
 
 	u8         other_vport[0x1];
 	u8         reserved_2[0xf];
 	u8         vport_number[0x10];
 
 	struct mlx5_ifc_esw_vport_context_fields_select_bits field_select;
 
 	struct mlx5_ifc_esw_vport_context_bits esw_vport_context;
 };
 
 struct mlx5_ifc_modify_cq_out_bits {
 	u8         status[0x8];
 	u8         reserved_0[0x18];
 
 	u8         syndrome[0x20];
 
 	u8         reserved_1[0x40];
 };
 
 enum {
 	MLX5_MODIFY_CQ_IN_OP_MOD_MODIFY_CQ  = 0x0,
 	MLX5_MODIFY_CQ_IN_OP_MOD_RESIZE_CQ  = 0x1,
 };
 
 struct mlx5_ifc_modify_cq_in_bits {
 	u8         opcode[0x10];
 	u8         reserved_0[0x10];
 
 	u8         reserved_1[0x10];
 	u8         op_mod[0x10];
 
 	u8         reserved_2[0x8];
 	u8         cqn[0x18];
 
 	union mlx5_ifc_modify_field_select_resize_field_select_auto_bits modify_field_select_resize_field_select;
 
 	struct mlx5_ifc_cqc_bits cq_context;
 
 	u8         reserved_3[0x600];
 
 	u8         pas[0][0x40];
 };
 
 struct mlx5_ifc_modify_cong_status_out_bits {
 	u8         status[0x8];
 	u8         reserved_0[0x18];
 
 	u8         syndrome[0x20];
 
 	u8         reserved_1[0x40];
 };
 
 struct mlx5_ifc_modify_cong_status_in_bits {
 	u8         opcode[0x10];
 	u8         reserved_0[0x10];
 
 	u8         reserved_1[0x10];
 	u8         op_mod[0x10];
 
 	u8         reserved_2[0x18];
 	u8         priority[0x4];
 	u8         cong_protocol[0x4];
 
 	u8         enable[0x1];
 	u8         tag_enable[0x1];
 	u8         reserved_3[0x1e];
 };
 
 struct mlx5_ifc_modify_cong_params_out_bits {
 	u8         status[0x8];
 	u8         reserved_0[0x18];
 
 	u8         syndrome[0x20];
 
 	u8         reserved_1[0x40];
 };
 
 struct mlx5_ifc_modify_cong_params_in_bits {
 	u8         opcode[0x10];
 	u8         reserved_0[0x10];
 
 	u8         reserved_1[0x10];
 	u8         op_mod[0x10];
 
 	u8         reserved_2[0x1c];
 	u8         cong_protocol[0x4];
 
 	union mlx5_ifc_field_select_802_1_r_roce_auto_bits field_select;
 
 	u8         reserved_3[0x80];
 
 	union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters;
 };
 
 struct mlx5_ifc_manage_pages_out_bits {
 	u8         status[0x8];
 	u8         reserved_0[0x18];
 
 	u8         syndrome[0x20];
 
 	u8         output_num_entries[0x20];
 
 	u8         reserved_1[0x20];
 
 	u8         pas[0][0x40];
 };
 
 enum {
 	MLX5_PAGES_CANT_GIVE                            = 0x0,
 	MLX5_PAGES_GIVE                                 = 0x1,
 	MLX5_PAGES_TAKE                                 = 0x2,
 };
 
 struct mlx5_ifc_manage_pages_in_bits {
 	u8         opcode[0x10];
 	u8         reserved_0[0x10];
 
 	u8         reserved_1[0x10];
 	u8         op_mod[0x10];
 
 	u8         reserved_2[0x10];
 	u8         function_id[0x10];
 
 	u8         input_num_entries[0x20];
 
 	u8         pas[0][0x40];
 };
 
 struct mlx5_ifc_mad_ifc_out_bits {
 	u8         status[0x8];
 	u8         reserved_0[0x18];
 
 	u8         syndrome[0x20];
 
 	u8         reserved_1[0x40];
 
 	u8         response_mad_packet[256][0x8];
 };
 
 struct mlx5_ifc_mad_ifc_in_bits {
 	u8         opcode[0x10];
 	u8         reserved_0[0x10];
 
 	u8         reserved_1[0x10];
 	u8         op_mod[0x10];
 
 	u8         remote_lid[0x10];
 	u8         reserved_2[0x8];
 	u8         port[0x8];
 
 	u8         reserved_3[0x20];
 
 	u8         mad[256][0x8];
 };
 
 struct mlx5_ifc_init_hca_out_bits {
 	u8         status[0x8];
 	u8         reserved_0[0x18];
 
 	u8         syndrome[0x20];
 
 	u8         reserved_1[0x40];
 };
 
 enum {
 	MLX5_INIT_HCA_IN_OP_MOD_INIT      = 0x0,
 	MLX5_INIT_HCA_IN_OP_MOD_PRE_INIT  = 0x1,
 };
 
 struct mlx5_ifc_init_hca_in_bits {
 	u8         opcode[0x10];
 	u8         reserved_0[0x10];
 
 	u8         reserved_1[0x10];
 	u8         op_mod[0x10];
 
 	u8         reserved_2[0x40];
 };
 
 struct mlx5_ifc_init2rtr_qp_out_bits {
 	u8         status[0x8];
 	u8         reserved_0[0x18];
 
 	u8         syndrome[0x20];
 
 	u8         reserved_1[0x40];
 };
 
 struct mlx5_ifc_init2rtr_qp_in_bits {
 	u8         opcode[0x10];
 	u8         reserved_0[0x10];
 
 	u8         reserved_1[0x10];
 	u8         op_mod[0x10];
 
 	u8         reserved_2[0x8];
 	u8         qpn[0x18];
 
 	u8         reserved_3[0x20];
 
 	u8         opt_param_mask[0x20];
 
 	u8         reserved_4[0x20];
 
 	struct mlx5_ifc_qpc_bits qpc;
 
 	u8         reserved_5[0x80];
 };
 
 struct mlx5_ifc_init2init_qp_out_bits {
 	u8         status[0x8];
 	u8         reserved_0[0x18];
 
 	u8         syndrome[0x20];
 
 	u8         reserved_1[0x40];
 };
 
 struct mlx5_ifc_init2init_qp_in_bits {
 	u8         opcode[0x10];
 	u8         reserved_0[0x10];
 
 	u8         reserved_1[0x10];
 	u8         op_mod[0x10];
 
 	u8         reserved_2[0x8];
 	u8         qpn[0x18];
 
 	u8         reserved_3[0x20];
 
 	u8         opt_param_mask[0x20];
 
 	u8         reserved_4[0x20];
 
 	struct mlx5_ifc_qpc_bits qpc;
 
 	u8         reserved_5[0x80];
 };
 
 struct mlx5_ifc_get_dropped_packet_log_out_bits {
 	u8         status[0x8];
 	u8         reserved_0[0x18];
 
 	u8         syndrome[0x20];
 
 	u8         reserved_1[0x40];
 
 	u8         packet_headers_log[128][0x8];
 
 	u8         packet_syndrome[64][0x8];
 };
 
 struct mlx5_ifc_get_dropped_packet_log_in_bits {
 	u8         opcode[0x10];
 	u8         reserved_0[0x10];
 
 	u8         reserved_1[0x10];
 	u8         op_mod[0x10];
 
 	u8         reserved_2[0x40];
 };
 
 struct mlx5_ifc_gen_eqe_in_bits {
 	u8         opcode[0x10];
 	u8         reserved_0[0x10];
 
 	u8         reserved_1[0x10];
 	u8         op_mod[0x10];
 
 	u8         reserved_2[0x18];
 	u8         eq_number[0x8];
 
 	u8         reserved_3[0x20];
 
 	u8         eqe[64][0x8];
 };
 
 struct mlx5_ifc_gen_eq_out_bits {
 	u8         status[0x8];
 	u8         reserved_0[0x18];
 
 	u8         syndrome[0x20];
 
 	u8         reserved_1[0x40];
 };
 
 struct mlx5_ifc_enable_hca_out_bits {
 	u8         status[0x8];
 	u8         reserved_0[0x18];
 
 	u8         syndrome[0x20];
 
 	u8         reserved_1[0x20];
 };
 
 struct mlx5_ifc_enable_hca_in_bits {
 	u8         opcode[0x10];
 	u8         reserved_0[0x10];
 
 	u8         reserved_1[0x10];
 	u8         op_mod[0x10];
 
 	u8         reserved_2[0x10];
 	u8         function_id[0x10];
 
 	u8         reserved_3[0x20];
 };
 
 struct mlx5_ifc_drain_dct_out_bits {
 	u8         status[0x8];
 	u8         reserved_0[0x18];
 
 	u8         syndrome[0x20];
 
 	u8         reserved_1[0x40];
 };
 
 struct mlx5_ifc_drain_dct_in_bits {
 	u8         opcode[0x10];
 	u8         reserved_0[0x10];
 
 	u8         reserved_1[0x10];
 	u8         op_mod[0x10];
 
 	u8         reserved_2[0x8];
 	u8         dctn[0x18];
 
 	u8         reserved_3[0x20];
 };
 
 struct mlx5_ifc_disable_hca_out_bits {
 	u8         status[0x8];
 	u8         reserved_0[0x18];
 
 	u8         syndrome[0x20];
 
 	u8         reserved_1[0x20];
 };
 
 struct mlx5_ifc_disable_hca_in_bits {
 	u8         opcode[0x10];
 	u8         reserved_0[0x10];
 
 	u8         reserved_1[0x10];
 	u8         op_mod[0x10];
 
 	u8         reserved_2[0x10];
 	u8         function_id[0x10];
 
 	u8         reserved_3[0x20];
 };
 
 struct mlx5_ifc_detach_from_mcg_out_bits {
 	u8         status[0x8];
 	u8         reserved_0[0x18];
 
 	u8         syndrome[0x20];
 
 	u8         reserved_1[0x40];
 };
 
 struct mlx5_ifc_detach_from_mcg_in_bits {
 	u8         opcode[0x10];
 	u8         reserved_0[0x10];
 
 	u8         reserved_1[0x10];
 	u8         op_mod[0x10];
 
 	u8         reserved_2[0x8];
 	u8         qpn[0x18];
 
 	u8         reserved_3[0x20];
 
 	u8         multicast_gid[16][0x8];
 };
 
 struct mlx5_ifc_destroy_xrc_srq_out_bits {
 	u8         status[0x8];
 	u8         reserved_0[0x18];
 
 	u8         syndrome[0x20];
 
 	u8         reserved_1[0x40];
 };
 
 struct mlx5_ifc_destroy_xrc_srq_in_bits {
 	u8         opcode[0x10];
 	u8         reserved_0[0x10];
 
 	u8         reserved_1[0x10];
 	u8         op_mod[0x10];
 
 	u8         reserved_2[0x8];
 	u8         xrc_srqn[0x18];
 
 	u8         reserved_3[0x20];
 };
 
 struct mlx5_ifc_destroy_tis_out_bits {
 	u8         status[0x8];
 	u8         reserved_0[0x18];
 
 	u8         syndrome[0x20];
 
 	u8         reserved_1[0x40];
 };
 
 struct mlx5_ifc_destroy_tis_in_bits {
 	u8         opcode[0x10];
 	u8         reserved_0[0x10];
 
 	u8         reserved_1[0x10];
 	u8         op_mod[0x10];
 
 	u8         reserved_2[0x8];
 	u8         tisn[0x18];
 
 	u8         reserved_3[0x20];
 };
 
 struct mlx5_ifc_destroy_tir_out_bits {
 	u8         status[0x8];
 	u8         reserved_0[0x18];
 
 	u8         syndrome[0x20];
 
 	u8         reserved_1[0x40];
 };
 
 struct mlx5_ifc_destroy_tir_in_bits {
 	u8         opcode[0x10];
 	u8         reserved_0[0x10];
 
 	u8         reserved_1[0x10];
 	u8         op_mod[0x10];
 
 	u8         reserved_2[0x8];
 	u8         tirn[0x18];
 
 	u8         reserved_3[0x20];
 };
 
 struct mlx5_ifc_destroy_srq_out_bits {
 	u8         status[0x8];
 	u8         reserved_0[0x18];
 
 	u8         syndrome[0x20];
 
 	u8         reserved_1[0x40];
 };
 
 struct mlx5_ifc_destroy_srq_in_bits {
 	u8         opcode[0x10];
 	u8         reserved_0[0x10];
 
 	u8         reserved_1[0x10];
 	u8         op_mod[0x10];
 
 	u8         reserved_2[0x8];
 	u8         srqn[0x18];
 
 	u8         reserved_3[0x20];
 };
 
 struct mlx5_ifc_destroy_sq_out_bits {
 	u8         status[0x8];
 	u8         reserved_0[0x18];
 
 	u8         syndrome[0x20];
 
 	u8         reserved_1[0x40];
 };
 
 struct mlx5_ifc_destroy_sq_in_bits {
 	u8         opcode[0x10];
 	u8         reserved_0[0x10];
 
 	u8         reserved_1[0x10];
 	u8         op_mod[0x10];
 
 	u8         reserved_2[0x8];
 	u8         sqn[0x18];
 
 	u8         reserved_3[0x20];
 };
 
 struct mlx5_ifc_destroy_scheduling_element_out_bits {
 	u8         status[0x8];
 	u8         reserved_at_8[0x18];
 
 	u8         syndrome[0x20];
 
 	u8         reserved_at_40[0x1c0];
 };
 
 enum {
 	MLX5_DESTROY_SCHEDULING_ELEMENT_IN_SCHEDULING_HIERARCHY_E_SWITCH  = 0x2,
 };
 
 struct mlx5_ifc_destroy_scheduling_element_in_bits {
 	u8         opcode[0x10];
 	u8         reserved_at_10[0x10];
 
 	u8         reserved_at_20[0x10];
 	u8         op_mod[0x10];
 
 	u8         scheduling_hierarchy[0x8];
 	u8         reserved_at_48[0x18];
 
 	u8         scheduling_element_id[0x20];
 
 	u8         reserved_at_80[0x180];
 };
 
 struct mlx5_ifc_destroy_rqt_out_bits {
 	u8         status[0x8];
 	u8         reserved_0[0x18];
 
 	u8         syndrome[0x20];
 
 	u8         reserved_1[0x40];
 };
 
 struct mlx5_ifc_destroy_rqt_in_bits {
 	u8         opcode[0x10];
 	u8         reserved_0[0x10];
 
 	u8         reserved_1[0x10];
 	u8         op_mod[0x10];
 
 	u8         reserved_2[0x8];
 	u8         rqtn[0x18];
 
 	u8         reserved_3[0x20];
 };
 
 struct mlx5_ifc_destroy_rq_out_bits {
 	u8         status[0x8];
 	u8         reserved_0[0x18];
 
 	u8         syndrome[0x20];
 
 	u8         reserved_1[0x40];
 };
 
 struct mlx5_ifc_destroy_rq_in_bits {
 	u8         opcode[0x10];
 	u8         reserved_0[0x10];
 
 	u8         reserved_1[0x10];
 	u8         op_mod[0x10];
 
 	u8         reserved_2[0x8];
 	u8         rqn[0x18];
 
 	u8         reserved_3[0x20];
 };
 
 struct mlx5_ifc_destroy_rmp_out_bits {
 	u8         status[0x8];
 	u8         reserved_0[0x18];
 
 	u8         syndrome[0x20];
 
 	u8         reserved_1[0x40];
 };
 
 struct mlx5_ifc_destroy_rmp_in_bits {
 	u8         opcode[0x10];
 	u8         reserved_0[0x10];
 
 	u8         reserved_1[0x10];
 	u8         op_mod[0x10];
 
 	u8         reserved_2[0x8];
 	u8         rmpn[0x18];
 
 	u8         reserved_3[0x20];
 };
 
 struct mlx5_ifc_destroy_qp_out_bits {
 	u8         status[0x8];
 	u8         reserved_0[0x18];
 
 	u8         syndrome[0x20];
 
 	u8         reserved_1[0x40];
 };
 
 struct mlx5_ifc_destroy_qp_in_bits {
 	u8         opcode[0x10];
 	u8         reserved_0[0x10];
 
 	u8         reserved_1[0x10];
 	u8         op_mod[0x10];
 
 	u8         reserved_2[0x8];
 	u8         qpn[0x18];
 
 	u8         reserved_3[0x20];
 };
 
 struct mlx5_ifc_destroy_qos_para_vport_out_bits {
 	u8         status[0x8];
 	u8         reserved_at_8[0x18];
 
 	u8         syndrome[0x20];
 
 	u8         reserved_at_40[0x1c0];
 };
 
 struct mlx5_ifc_destroy_qos_para_vport_in_bits {
 	u8         opcode[0x10];
 	u8         reserved_at_10[0x10];
 
 	u8         reserved_at_20[0x10];
 	u8         op_mod[0x10];
 
 	u8         reserved_at_40[0x20];
 
 	u8         reserved_at_60[0x10];
 	u8         qos_para_vport_number[0x10];
 
 	u8         reserved_at_80[0x180];
 };
 
 struct mlx5_ifc_destroy_psv_out_bits {
 	u8         status[0x8];
 	u8         reserved_0[0x18];
 
 	u8         syndrome[0x20];
 
 	u8         reserved_1[0x40];
 };
 
 struct mlx5_ifc_destroy_psv_in_bits {
 	u8         opcode[0x10];
 	u8         reserved_0[0x10];
 
 	u8         reserved_1[0x10];
 	u8         op_mod[0x10];
 
 	u8         reserved_2[0x8];
 	u8         psvn[0x18];
 
 	u8         reserved_3[0x20];
 };
 
 struct mlx5_ifc_destroy_mkey_out_bits {
 	u8         status[0x8];
 	u8         reserved_0[0x18];
 
 	u8         syndrome[0x20];
 
 	u8         reserved_1[0x40];
 };
 
 struct mlx5_ifc_destroy_mkey_in_bits {
 	u8         opcode[0x10];
 	u8         reserved_0[0x10];
 
 	u8         reserved_1[0x10];
 	u8         op_mod[0x10];
 
 	u8         reserved_2[0x8];
 	u8         mkey_index[0x18];
 
 	u8         reserved_3[0x20];
 };
 
 struct mlx5_ifc_destroy_flow_table_out_bits {
 	u8         status[0x8];
 	u8         reserved_0[0x18];
 
 	u8         syndrome[0x20];
 
 	u8         reserved_1[0x40];
 };
 
 struct mlx5_ifc_destroy_flow_table_in_bits {
 	u8         opcode[0x10];
 	u8         reserved_0[0x10];
 
 	u8         reserved_1[0x10];
 	u8         op_mod[0x10];
 
 	u8         other_vport[0x1];
 	u8         reserved_2[0xf];
 	u8         vport_number[0x10];
 
 	u8         reserved_3[0x20];
 
 	u8         table_type[0x8];
 	u8         reserved_4[0x18];
 
 	u8         reserved_5[0x8];
 	u8         table_id[0x18];
 
 	u8         reserved_6[0x140];
 };
 
 struct mlx5_ifc_destroy_flow_group_out_bits {
 	u8         status[0x8];
 	u8         reserved_0[0x18];
 
 	u8         syndrome[0x20];
 
 	u8         reserved_1[0x40];
 };
 
 struct mlx5_ifc_destroy_flow_group_in_bits {
 	u8         opcode[0x10];
 	u8         reserved_0[0x10];
 
 	u8         reserved_1[0x10];
 	u8         op_mod[0x10];
 
 	u8         other_vport[0x1];
 	u8         reserved_2[0xf];
 	u8         vport_number[0x10];
 
 	u8         reserved_3[0x20];
 
 	u8         table_type[0x8];
 	u8         reserved_4[0x18];
 
 	u8         reserved_5[0x8];
 	u8         table_id[0x18];
 
 	u8         group_id[0x20];
 
 	u8         reserved_6[0x120];
 };
 
 struct mlx5_ifc_destroy_eq_out_bits {
 	u8         status[0x8];
 	u8         reserved_0[0x18];
 
 	u8         syndrome[0x20];
 
 	u8         reserved_1[0x40];
 };
 
 struct mlx5_ifc_destroy_eq_in_bits {
 	u8         opcode[0x10];
 	u8         reserved_0[0x10];
 
 	u8         reserved_1[0x10];
 	u8         op_mod[0x10];
 
 	u8         reserved_2[0x18];
 	u8         eq_number[0x8];
 
 	u8         reserved_3[0x20];
 };
 
 struct mlx5_ifc_destroy_dct_out_bits {
 	u8         status[0x8];
 	u8         reserved_0[0x18];
 
 	u8         syndrome[0x20];
 
 	u8         reserved_1[0x40];
 };
 
 struct mlx5_ifc_destroy_dct_in_bits {
 	u8         opcode[0x10];
 	u8         reserved_0[0x10];
 
 	u8         reserved_1[0x10];
 	u8         op_mod[0x10];
 
 	u8         reserved_2[0x8];
 	u8         dctn[0x18];
 
 	u8         reserved_3[0x20];
 };
 
 struct mlx5_ifc_destroy_cq_out_bits {
 	u8         status[0x8];
 	u8         reserved_0[0x18];
 
 	u8         syndrome[0x20];
 
 	u8         reserved_1[0x40];
 };
 
 struct mlx5_ifc_destroy_cq_in_bits {
 	u8         opcode[0x10];
 	u8         reserved_0[0x10];
 
 	u8         reserved_1[0x10];
 	u8         op_mod[0x10];
 
 	u8         reserved_2[0x8];
 	u8         cqn[0x18];
 
 	u8         reserved_3[0x20];
 };
 
 struct mlx5_ifc_delete_vxlan_udp_dport_out_bits {
 	u8         status[0x8];
 	u8         reserved_0[0x18];
 
 	u8         syndrome[0x20];
 
 	u8         reserved_1[0x40];
 };
 
 struct mlx5_ifc_delete_vxlan_udp_dport_in_bits {
 	u8         opcode[0x10];
 	u8         reserved_0[0x10];
 
 	u8         reserved_1[0x10];
 	u8         op_mod[0x10];
 
 	u8         reserved_2[0x20];
 
 	u8         reserved_3[0x10];
 	u8         vxlan_udp_port[0x10];
 };
 
 struct mlx5_ifc_delete_l2_table_entry_out_bits {
 	u8         status[0x8];
 	u8         reserved_0[0x18];
 
 	u8         syndrome[0x20];
 
 	u8         reserved_1[0x40];
 };
 
 struct mlx5_ifc_delete_l2_table_entry_in_bits {
 	u8         opcode[0x10];
 	u8         reserved_0[0x10];
 
 	u8         reserved_1[0x10];
 	u8         op_mod[0x10];
 
 	u8         reserved_2[0x60];
 
 	u8         reserved_3[0x8];
 	u8         table_index[0x18];
 
 	u8         reserved_4[0x140];
 };
 
 struct mlx5_ifc_delete_fte_out_bits {
 	u8         status[0x8];
 	u8         reserved_0[0x18];
 
 	u8         syndrome[0x20];
 
 	u8         reserved_1[0x40];
 };
 
 struct mlx5_ifc_delete_fte_in_bits {
 	u8         opcode[0x10];
 	u8         reserved_0[0x10];
 
 	u8         reserved_1[0x10];
 	u8         op_mod[0x10];
 
 	u8         other_vport[0x1];
 	u8         reserved_2[0xf];
 	u8         vport_number[0x10];
 
 	u8         reserved_3[0x20];
 
 	u8         table_type[0x8];
 	u8         reserved_4[0x18];
 
 	u8         reserved_5[0x8];
 	u8         table_id[0x18];
 
 	u8         reserved_6[0x40];
 
 	u8         flow_index[0x20];
 
 	u8         reserved_7[0xe0];
 };
 
 struct mlx5_ifc_dealloc_xrcd_out_bits {
 	u8         status[0x8];
 	u8         reserved_0[0x18];
 
 	u8         syndrome[0x20];
 
 	u8         reserved_1[0x40];
 };
 
 struct mlx5_ifc_dealloc_xrcd_in_bits {
 	u8         opcode[0x10];
 	u8         reserved_0[0x10];
 
 	u8         reserved_1[0x10];
 	u8         op_mod[0x10];
 
 	u8         reserved_2[0x8];
 	u8         xrcd[0x18];
 
 	u8         reserved_3[0x20];
 };
 
 struct mlx5_ifc_dealloc_uar_out_bits {
 	u8         status[0x8];
 	u8         reserved_0[0x18];
 
 	u8         syndrome[0x20];
 
 	u8         reserved_1[0x40];
 };
 
 struct mlx5_ifc_dealloc_uar_in_bits {
 	u8         opcode[0x10];
 	u8         reserved_0[0x10];
 
 	u8         reserved_1[0x10];
 	u8         op_mod[0x10];
 
 	u8         reserved_2[0x8];
 	u8         uar[0x18];
 
 	u8         reserved_3[0x20];
 };
 
 struct mlx5_ifc_dealloc_transport_domain_out_bits {
 	u8         status[0x8];
 	u8         reserved_0[0x18];
 
 	u8         syndrome[0x20];
 
 	u8         reserved_1[0x40];
 };
 
 struct mlx5_ifc_dealloc_transport_domain_in_bits {
 	u8         opcode[0x10];
 	u8         reserved_0[0x10];
 
 	u8         reserved_1[0x10];
 	u8         op_mod[0x10];
 
 	u8         reserved_2[0x8];
 	u8         transport_domain[0x18];
 
 	u8         reserved_3[0x20];
 };
 
 struct mlx5_ifc_dealloc_q_counter_out_bits {
 	u8         status[0x8];
 	u8         reserved_0[0x18];
 
 	u8         syndrome[0x20];
 
 	u8         reserved_1[0x40];
 };
 
 struct mlx5_ifc_counter_id_bits {
 	u8         reserved[0x10];
 	u8         counter_id[0x10];
 };
 
 struct mlx5_ifc_diagnostic_params_context_bits {
 	u8         num_of_counters[0x10];
 	u8         reserved_2[0x8];
 	u8         log_num_of_samples[0x8];
 
 	u8         single[0x1];
 	u8         repetitive[0x1];
 	u8         sync[0x1];
 	u8         clear[0x1];
 	u8         on_demand[0x1];
 	u8         enable[0x1];
 	u8         reserved_3[0x12];
 	u8         log_sample_period[0x8];
 
 	u8         reserved_4[0x80];
 
 	struct mlx5_ifc_counter_id_bits counter_id[0];
 };
 
 struct mlx5_ifc_set_diagnostic_params_in_bits {
 	u8         opcode[0x10];
 	u8         reserved_0[0x10];
 
 	u8         reserved_1[0x10];
 	u8         op_mod[0x10];
 
 	struct mlx5_ifc_diagnostic_params_context_bits diagnostic_params_ctx;
 };
 
 struct mlx5_ifc_set_diagnostic_params_out_bits {
 	u8         status[0x8];
 	u8         reserved_0[0x18];
 
 	u8         syndrome[0x20];
 
 	u8         reserved_1[0x40];
 };
 
 struct mlx5_ifc_query_diagnostic_counters_in_bits {
 	u8         opcode[0x10];
 	u8         reserved_0[0x10];
 
 	u8         reserved_1[0x10];
 	u8         op_mod[0x10];
 
 	u8         num_of_samples[0x10];
 	u8         sample_index[0x10];
 
 	u8         reserved_2[0x20];
 };
 
 struct mlx5_ifc_diagnostic_counter_bits {
 	u8         counter_id[0x10];
 	u8         sample_id[0x10];
 
 	u8         time_stamp_31_0[0x20];
 
 	u8         counter_value_h[0x20];
 
 	u8         counter_value_l[0x20];
 };
 
 struct mlx5_ifc_query_diagnostic_counters_out_bits {
 	u8         status[0x8];
 	u8         reserved_0[0x18];
 
 	u8         syndrome[0x20];
 
 	u8         reserved_1[0x40];
 
 	struct mlx5_ifc_diagnostic_counter_bits diag_counter[0];
 };
 
 struct mlx5_ifc_dealloc_q_counter_in_bits {
 	u8         opcode[0x10];
 	u8         reserved_0[0x10];
 
 	u8         reserved_1[0x10];
 	u8         op_mod[0x10];
 
 	u8         reserved_2[0x18];
 	u8         counter_set_id[0x8];
 
 	u8         reserved_3[0x20];
 };
 
 struct mlx5_ifc_dealloc_pd_out_bits {
 	u8         status[0x8];
 	u8         reserved_0[0x18];
 
 	u8         syndrome[0x20];
 
 	u8         reserved_1[0x40];
 };
 
 struct mlx5_ifc_dealloc_pd_in_bits {
 	u8         opcode[0x10];
 	u8         reserved_0[0x10];
 
 	u8         reserved_1[0x10];
 	u8         op_mod[0x10];
 
 	u8         reserved_2[0x8];
 	u8         pd[0x18];
 
 	u8         reserved_3[0x20];
 };
 
 struct mlx5_ifc_dealloc_flow_counter_out_bits {
 	u8         status[0x8];
 	u8         reserved_0[0x18];
 
 	u8         syndrome[0x20];
 
 	u8         reserved_1[0x40];
 };
 
 struct mlx5_ifc_dealloc_flow_counter_in_bits {
 	u8         opcode[0x10];
 	u8         reserved_0[0x10];
 
 	u8         reserved_1[0x10];
 	u8         op_mod[0x10];
 
 	u8         reserved_2[0x10];
 	u8         flow_counter_id[0x10];
 
 	u8         reserved_3[0x20];
 };
 
 struct mlx5_ifc_deactivate_tracer_out_bits {
 	u8         status[0x8];
 	u8         reserved_0[0x18];
 
 	u8         syndrome[0x20];
 
 	u8         reserved_1[0x40];
 };
 
 struct mlx5_ifc_deactivate_tracer_in_bits {
 	u8         opcode[0x10];
 	u8         reserved_0[0x10];
 
 	u8         reserved_1[0x10];
 	u8         op_mod[0x10];
 
 	u8         mkey[0x20];
 
 	u8         reserved_2[0x20];
 };
 
 struct mlx5_ifc_create_xrc_srq_out_bits {
 	u8         status[0x8];
 	u8         reserved_0[0x18];
 
 	u8         syndrome[0x20];
 
 	u8         reserved_1[0x8];
 	u8         xrc_srqn[0x18];
 
 	u8         reserved_2[0x20];
 };
 
 struct mlx5_ifc_create_xrc_srq_in_bits {
 	u8         opcode[0x10];
 	u8         reserved_0[0x10];
 
 	u8         reserved_1[0x10];
 	u8         op_mod[0x10];
 
 	u8         reserved_2[0x40];
 
 	struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry;
 
 	u8         reserved_3[0x600];
 
 	u8         pas[0][0x40];
 };
 
 struct mlx5_ifc_create_tis_out_bits {
 	u8         status[0x8];
 	u8         reserved_0[0x18];
 
 	u8         syndrome[0x20];
 
 	u8         reserved_1[0x8];
 	u8         tisn[0x18];
 
 	u8         reserved_2[0x20];
 };
 
 struct mlx5_ifc_create_tis_in_bits {
 	u8         opcode[0x10];
 	u8         reserved_0[0x10];
 
 	u8         reserved_1[0x10];
 	u8         op_mod[0x10];
 
 	u8         reserved_2[0xc0];
 
 	struct mlx5_ifc_tisc_bits ctx;
 };
 
 struct mlx5_ifc_create_tir_out_bits {
 	u8         status[0x8];
 	u8         reserved_0[0x18];
 
 	u8         syndrome[0x20];
 
 	u8         reserved_1[0x8];
 	u8         tirn[0x18];
 
 	u8         reserved_2[0x20];
 };
 
 struct mlx5_ifc_create_tir_in_bits {
 	u8         opcode[0x10];
 	u8         reserved_0[0x10];
 
 	u8         reserved_1[0x10];
 	u8         op_mod[0x10];
 
 	u8         reserved_2[0xc0];
 
 	struct mlx5_ifc_tirc_bits tir_context;
 };
 
 struct mlx5_ifc_create_srq_out_bits {
 	u8         status[0x8];
 	u8         reserved_0[0x18];
 
 	u8         syndrome[0x20];
 
 	u8         reserved_1[0x8];
 	u8         srqn[0x18];
 
 	u8         reserved_2[0x20];
 };
 
 struct mlx5_ifc_create_srq_in_bits {
 	u8         opcode[0x10];
 	u8         reserved_0[0x10];
 
 	u8         reserved_1[0x10];
 	u8         op_mod[0x10];
 
 	u8         reserved_2[0x40];
 
 	struct mlx5_ifc_srqc_bits srq_context_entry;
 
 	u8         reserved_3[0x600];
 
 	u8         pas[0][0x40];
 };
 
 struct mlx5_ifc_create_sq_out_bits {
 	u8         status[0x8];
 	u8         reserved_0[0x18];
 
 	u8         syndrome[0x20];
 
 	u8         reserved_1[0x8];
 	u8         sqn[0x18];
 
 	u8         reserved_2[0x20];
 };
 
 struct mlx5_ifc_create_sq_in_bits {
 	u8         opcode[0x10];
 	u8         reserved_0[0x10];
 
 	u8         reserved_1[0x10];
 	u8         op_mod[0x10];
 
 	u8         reserved_2[0xc0];
 
 	struct mlx5_ifc_sqc_bits ctx;
 };
 
 struct mlx5_ifc_create_scheduling_element_out_bits {
 	u8         status[0x8];
 	u8         reserved_at_8[0x18];
 
 	u8         syndrome[0x20];
 
 	u8         reserved_at_40[0x40];
 
 	u8         scheduling_element_id[0x20];
 
 	u8         reserved_at_a0[0x160];
 };
 
 enum {
 	MLX5_CREATE_SCHEDULING_ELEMENT_IN_SCHEDULING_HIERARCHY_E_SWITCH  = 0x2,
 };
 
 struct mlx5_ifc_create_scheduling_element_in_bits {
 	u8         opcode[0x10];
 	u8         reserved_at_10[0x10];
 
 	u8         reserved_at_20[0x10];
 	u8         op_mod[0x10];
 
 	u8         scheduling_hierarchy[0x8];
 	u8         reserved_at_48[0x18];
 
 	u8         reserved_at_60[0xa0];
 
 	struct mlx5_ifc_scheduling_context_bits scheduling_context;
 
 	u8         reserved_at_300[0x100];
 };
 
 struct mlx5_ifc_create_rqt_out_bits {
 	u8         status[0x8];
 	u8         reserved_0[0x18];
 
 	u8         syndrome[0x20];
 
 	u8         reserved_1[0x8];
 	u8         rqtn[0x18];
 
 	u8         reserved_2[0x20];
 };
 
 struct mlx5_ifc_create_rqt_in_bits {
 	u8         opcode[0x10];
 	u8         reserved_0[0x10];
 
 	u8         reserved_1[0x10];
 	u8         op_mod[0x10];
 
 	u8         reserved_2[0xc0];
 
 	struct mlx5_ifc_rqtc_bits rqt_context;
 };
 
 struct mlx5_ifc_create_rq_out_bits {
 	u8         status[0x8];
 	u8         reserved_0[0x18];
 
 	u8         syndrome[0x20];
 
 	u8         reserved_1[0x8];
 	u8         rqn[0x18];
 
 	u8         reserved_2[0x20];
 };
 
 struct mlx5_ifc_create_rq_in_bits {
 	u8         opcode[0x10];
 	u8         reserved_0[0x10];
 
 	u8         reserved_1[0x10];
 	u8         op_mod[0x10];
 
 	u8         reserved_2[0xc0];
 
 	struct mlx5_ifc_rqc_bits ctx;
 };
 
 struct mlx5_ifc_create_rmp_out_bits {
 	u8         status[0x8];
 	u8         reserved_0[0x18];
 
 	u8         syndrome[0x20];
 
 	u8         reserved_1[0x8];
 	u8         rmpn[0x18];
 
 	u8         reserved_2[0x20];
 };
 
 struct mlx5_ifc_create_rmp_in_bits {
 	u8         opcode[0x10];
 	u8         reserved_0[0x10];
 
 	u8         reserved_1[0x10];
 	u8         op_mod[0x10];
 
 	u8         reserved_2[0xc0];
 
 	struct mlx5_ifc_rmpc_bits ctx;
 };
 
 struct mlx5_ifc_create_qp_out_bits {
 	u8         status[0x8];
 	u8         reserved_0[0x18];
 
 	u8         syndrome[0x20];
 
 	u8         reserved_1[0x8];
 	u8         qpn[0x18];
 
 	u8         reserved_2[0x20];
 };
 
 struct mlx5_ifc_create_qp_in_bits {
 	u8         opcode[0x10];
 	u8         reserved_0[0x10];
 
 	u8         reserved_1[0x10];
 	u8         op_mod[0x10];
 
 	u8         reserved_2[0x8];
 	u8         input_qpn[0x18];
 
 	u8         reserved_3[0x20];
 
 	u8         opt_param_mask[0x20];
 
 	u8         reserved_4[0x20];
 
 	struct mlx5_ifc_qpc_bits qpc;
 
 	u8         reserved_5[0x80];
 
 	u8         pas[0][0x40];
 };
 
 struct mlx5_ifc_create_qos_para_vport_out_bits {
 	u8         status[0x8];
 	u8         reserved_at_8[0x18];
 
 	u8         syndrome[0x20];
 
 	u8         reserved_at_40[0x20];
 
 	u8         reserved_at_60[0x10];
 	u8         qos_para_vport_number[0x10];
 
 	u8         reserved_at_80[0x180];
 };
 
 struct mlx5_ifc_create_qos_para_vport_in_bits {
 	u8         opcode[0x10];
 	u8         reserved_at_10[0x10];
 
 	u8         reserved_at_20[0x10];
 	u8         op_mod[0x10];
 
 	u8         reserved_at_40[0x1c0];
 };
 
 struct mlx5_ifc_create_psv_out_bits {
 	u8         status[0x8];
 	u8         reserved_0[0x18];
 
 	u8         syndrome[0x20];
 
 	u8         reserved_1[0x40];
 
 	u8         reserved_2[0x8];
 	u8         psv0_index[0x18];
 
 	u8         reserved_3[0x8];
 	u8         psv1_index[0x18];
 
 	u8         reserved_4[0x8];
 	u8         psv2_index[0x18];
 
 	u8         reserved_5[0x8];
 	u8         psv3_index[0x18];
 };
 
 struct mlx5_ifc_create_psv_in_bits {
 	u8         opcode[0x10];
 	u8         reserved_0[0x10];
 
 	u8         reserved_1[0x10];
 	u8         op_mod[0x10];
 
 	u8         num_psv[0x4];
 	u8         reserved_2[0x4];
 	u8         pd[0x18];
 
 	u8         reserved_3[0x20];
 };
 
 struct mlx5_ifc_create_mkey_out_bits {
 	u8         status[0x8];
 	u8         reserved_0[0x18];
 
 	u8         syndrome[0x20];
 
 	u8         reserved_1[0x8];
 	u8         mkey_index[0x18];
 
 	u8         reserved_2[0x20];
 };
 
 struct mlx5_ifc_create_mkey_in_bits {
 	u8         opcode[0x10];
 	u8         reserved_0[0x10];
 
 	u8         reserved_1[0x10];
 	u8         op_mod[0x10];
 
 	u8         reserved_2[0x20];
 
 	u8         pg_access[0x1];
 	u8         reserved_3[0x1f];
 
 	struct mlx5_ifc_mkc_bits memory_key_mkey_entry;
 
 	u8         reserved_4[0x80];
 
 	u8         translations_octword_actual_size[0x20];
 
 	u8         reserved_5[0x560];
 
 	u8         klm_pas_mtt[0][0x20];
 };
 
 struct mlx5_ifc_create_flow_table_out_bits {
 	u8         status[0x8];
 	u8         reserved_0[0x18];
 
 	u8         syndrome[0x20];
 
 	u8         reserved_1[0x8];
 	u8         table_id[0x18];
 
 	u8         reserved_2[0x20];
 };
 
 struct mlx5_ifc_create_flow_table_in_bits {
 	u8         opcode[0x10];
 	u8         reserved_at_10[0x10];
 
 	u8         reserved_at_20[0x10];
 	u8         op_mod[0x10];
 
 	u8         other_vport[0x1];
 	u8         reserved_at_41[0xf];
 	u8         vport_number[0x10];
 
 	u8         reserved_at_60[0x20];
 
 	u8         table_type[0x8];
 	u8         reserved_at_88[0x18];
 
 	u8         reserved_at_a0[0x20];
 
 	struct mlx5_ifc_flow_table_context_bits flow_table_context;
 };
 
 struct mlx5_ifc_create_flow_group_out_bits {
 	u8         status[0x8];
 	u8         reserved_0[0x18];
 
 	u8         syndrome[0x20];
 
 	u8         reserved_1[0x8];
 	u8         group_id[0x18];
 
 	u8         reserved_2[0x20];
 };
 
 enum {
 	MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_OUTER_HEADERS    = 0x0,
 	MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS  = 0x1,
 	MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_INNER_HEADERS    = 0x2,
 };
 
 struct mlx5_ifc_create_flow_group_in_bits {
 	u8         opcode[0x10];
 	u8         reserved_0[0x10];
 
 	u8         reserved_1[0x10];
 	u8         op_mod[0x10];
 
 	u8         other_vport[0x1];
 	u8         reserved_2[0xf];
 	u8         vport_number[0x10];
 
 	u8         reserved_3[0x20];
 
 	u8         table_type[0x8];
 	u8         reserved_4[0x18];
 
 	u8         reserved_5[0x8];
 	u8         table_id[0x18];
 
 	u8         reserved_6[0x20];
 
 	u8         start_flow_index[0x20];
 
 	u8         reserved_7[0x20];
 
 	u8         end_flow_index[0x20];
 
 	u8         reserved_8[0xa0];
 
 	u8         reserved_9[0x18];
 	u8         match_criteria_enable[0x8];
 
 	struct mlx5_ifc_fte_match_param_bits match_criteria;
 
 	u8         reserved_10[0xe00];
 };
 
 struct mlx5_ifc_create_eq_out_bits {
 	u8         status[0x8];
 	u8         reserved_0[0x18];
 
 	u8         syndrome[0x20];
 
 	u8         reserved_1[0x18];
 	u8         eq_number[0x8];
 
 	u8         reserved_2[0x20];
 };
 
 struct mlx5_ifc_create_eq_in_bits {
 	u8         opcode[0x10];
 	u8         reserved_0[0x10];
 
 	u8         reserved_1[0x10];
 	u8         op_mod[0x10];
 
 	u8         reserved_2[0x40];
 
 	struct mlx5_ifc_eqc_bits eq_context_entry;
 
 	u8         reserved_3[0x40];
 
 	u8         event_bitmask[0x40];
 
 	u8         reserved_4[0x580];
 
 	u8         pas[0][0x40];
 };
 
 struct mlx5_ifc_create_dct_out_bits {
 	u8         status[0x8];
 	u8         reserved_0[0x18];
 
 	u8         syndrome[0x20];
 
 	u8         reserved_1[0x8];
 	u8         dctn[0x18];
 
 	u8         reserved_2[0x20];
 };
 
 struct mlx5_ifc_create_dct_in_bits {
 	u8         opcode[0x10];
 	u8         reserved_0[0x10];
 
 	u8         reserved_1[0x10];
 	u8         op_mod[0x10];
 
 	u8         reserved_2[0x40];
 
 	struct mlx5_ifc_dctc_bits dct_context_entry;
 
 	u8         reserved_3[0x180];
 };
 
 struct mlx5_ifc_create_cq_out_bits {
 	u8         status[0x8];
 	u8         reserved_0[0x18];
 
 	u8         syndrome[0x20];
 
 	u8         reserved_1[0x8];
 	u8         cqn[0x18];
 
 	u8         reserved_2[0x20];
 };
 
 struct mlx5_ifc_create_cq_in_bits {
 	u8         opcode[0x10];
 	u8         reserved_0[0x10];
 
 	u8         reserved_1[0x10];
 	u8         op_mod[0x10];
 
 	u8         reserved_2[0x40];
 
 	struct mlx5_ifc_cqc_bits cq_context;
 
 	u8         reserved_3[0x600];
 
 	u8         pas[0][0x40];
 };
 
 struct mlx5_ifc_config_int_moderation_out_bits {
 	u8         status[0x8];
 	u8         reserved_0[0x18];
 
 	u8         syndrome[0x20];
 
 	u8         reserved_1[0x4];
 	u8         min_delay[0xc];
 	u8         int_vector[0x10];
 
 	u8         reserved_2[0x20];
 };
 
 enum {
 	MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_WRITE  = 0x0,
 	MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_READ   = 0x1,
 };
 
 struct mlx5_ifc_config_int_moderation_in_bits {
 	u8         opcode[0x10];
 	u8         reserved_0[0x10];
 
 	u8         reserved_1[0x10];
 	u8         op_mod[0x10];
 
 	u8         reserved_2[0x4];
 	u8         min_delay[0xc];
 	u8         int_vector[0x10];
 
 	u8         reserved_3[0x20];
 };
 
 struct mlx5_ifc_attach_to_mcg_out_bits {
 	u8         status[0x8];
 	u8         reserved_0[0x18];
 
 	u8         syndrome[0x20];
 
 	u8         reserved_1[0x40];
 };
 
 struct mlx5_ifc_attach_to_mcg_in_bits {
 	u8         opcode[0x10];
 	u8         reserved_0[0x10];
 
 	u8         reserved_1[0x10];
 	u8         op_mod[0x10];
 
 	u8         reserved_2[0x8];
 	u8         qpn[0x18];
 
 	u8         reserved_3[0x20];
 
 	u8         multicast_gid[16][0x8];
 };
 
 struct mlx5_ifc_arm_xrc_srq_out_bits {
 	u8         status[0x8];
 	u8         reserved_0[0x18];
 
 	u8         syndrome[0x20];
 
 	u8         reserved_1[0x40];
 };
 
 enum {
 	MLX5_ARM_XRC_SRQ_IN_OP_MOD_XRC_SRQ  = 0x1,
 };
 
 struct mlx5_ifc_arm_xrc_srq_in_bits {
 	u8         opcode[0x10];
 	u8         reserved_0[0x10];
 
 	u8         reserved_1[0x10];
 	u8         op_mod[0x10];
 
 	u8         reserved_2[0x8];
 	u8         xrc_srqn[0x18];
 
 	u8         reserved_3[0x10];
 	u8         lwm[0x10];
 };
 
 struct mlx5_ifc_arm_rq_out_bits {
 	u8         status[0x8];
 	u8         reserved_0[0x18];
 
 	u8         syndrome[0x20];
 
 	u8         reserved_1[0x40];
 };
 
 enum {
 	MLX5_ARM_RQ_IN_OP_MOD_SRQ  = 0x1,
 };
 
 struct mlx5_ifc_arm_rq_in_bits {
 	u8         opcode[0x10];
 	u8         reserved_0[0x10];
 
 	u8         reserved_1[0x10];
 	u8         op_mod[0x10];
 
 	u8         reserved_2[0x8];
 	u8         srq_number[0x18];
 
 	u8         reserved_3[0x10];
 	u8         lwm[0x10];
 };
 
 struct mlx5_ifc_arm_dct_out_bits {
 	u8         status[0x8];
 	u8         reserved_0[0x18];
 
 	u8         syndrome[0x20];
 
 	u8         reserved_1[0x40];
 };
 
 struct mlx5_ifc_arm_dct_in_bits {
 	u8         opcode[0x10];
 	u8         reserved_0[0x10];
 
 	u8         reserved_1[0x10];
 	u8         op_mod[0x10];
 
 	u8         reserved_2[0x8];
 	u8         dctn[0x18];
 
 	u8         reserved_3[0x20];
 };
 
 struct mlx5_ifc_alloc_xrcd_out_bits {
 	u8         status[0x8];
 	u8         reserved_0[0x18];
 
 	u8         syndrome[0x20];
 
 	u8         reserved_1[0x8];
 	u8         xrcd[0x18];
 
 	u8         reserved_2[0x20];
 };
 
 struct mlx5_ifc_alloc_xrcd_in_bits {
 	u8         opcode[0x10];
 	u8         reserved_0[0x10];
 
 	u8         reserved_1[0x10];
 	u8         op_mod[0x10];
 
 	u8         reserved_2[0x40];
 };
 
 struct mlx5_ifc_alloc_uar_out_bits {
 	u8         status[0x8];
 	u8         reserved_0[0x18];
 
 	u8         syndrome[0x20];
 
 	u8         reserved_1[0x8];
 	u8         uar[0x18];
 
 	u8         reserved_2[0x20];
 };
 
 struct mlx5_ifc_alloc_uar_in_bits {
 	u8         opcode[0x10];
 	u8         reserved_0[0x10];
 
 	u8         reserved_1[0x10];
 	u8         op_mod[0x10];
 
 	u8         reserved_2[0x40];
 };
 
 struct mlx5_ifc_alloc_transport_domain_out_bits {
 	u8         status[0x8];
 	u8         reserved_0[0x18];
 
 	u8         syndrome[0x20];
 
 	u8         reserved_1[0x8];
 	u8         transport_domain[0x18];
 
 	u8         reserved_2[0x20];
 };
 
 struct mlx5_ifc_alloc_transport_domain_in_bits {
 	u8         opcode[0x10];
 	u8         reserved_0[0x10];
 
 	u8         reserved_1[0x10];
 	u8         op_mod[0x10];
 
 	u8         reserved_2[0x40];
 };
 
 struct mlx5_ifc_alloc_q_counter_out_bits {
 	u8         status[0x8];
 	u8         reserved_0[0x18];
 
 	u8         syndrome[0x20];
 
 	u8         reserved_1[0x18];
 	u8         counter_set_id[0x8];
 
 	u8         reserved_2[0x20];
 };
 
 struct mlx5_ifc_alloc_q_counter_in_bits {
 	u8         opcode[0x10];
 	u8         reserved_0[0x10];
 
 	u8         reserved_1[0x10];
 	u8         op_mod[0x10];
 
 	u8         reserved_2[0x40];
 };
 
 struct mlx5_ifc_alloc_pd_out_bits {
 	u8         status[0x8];
 	u8         reserved_0[0x18];
 
 	u8         syndrome[0x20];
 
 	u8         reserved_1[0x8];
 	u8         pd[0x18];
 
 	u8         reserved_2[0x20];
 };
 
 struct mlx5_ifc_alloc_pd_in_bits {
 	u8         opcode[0x10];
 	u8         reserved_0[0x10];
 
 	u8         reserved_1[0x10];
 	u8         op_mod[0x10];
 
 	u8         reserved_2[0x40];
 };
 
 struct mlx5_ifc_alloc_flow_counter_out_bits {
 	u8         status[0x8];
 	u8         reserved_0[0x18];
 
 	u8         syndrome[0x20];
 
 	u8         reserved_1[0x10];
 	u8         flow_counter_id[0x10];
 
 	u8         reserved_2[0x20];
 };
 
 struct mlx5_ifc_alloc_flow_counter_in_bits {
 	u8         opcode[0x10];
 	u8         reserved_0[0x10];
 
 	u8         reserved_1[0x10];
 	u8         op_mod[0x10];
 
 	u8         reserved_2[0x40];
 };
 
 struct mlx5_ifc_add_vxlan_udp_dport_out_bits {
 	u8         status[0x8];
 	u8         reserved_0[0x18];
 
 	u8         syndrome[0x20];
 
 	u8         reserved_1[0x40];
 };
 
 struct mlx5_ifc_add_vxlan_udp_dport_in_bits {
 	u8         opcode[0x10];
 	u8         reserved_0[0x10];
 
 	u8         reserved_1[0x10];
 	u8         op_mod[0x10];
 
 	u8         reserved_2[0x20];
 
 	u8         reserved_3[0x10];
 	u8         vxlan_udp_port[0x10];
 };
 
 struct mlx5_ifc_activate_tracer_out_bits {
 	u8         status[0x8];
 	u8         reserved_0[0x18];
 
 	u8         syndrome[0x20];
 
 	u8         reserved_1[0x40];
 };
 
 struct mlx5_ifc_activate_tracer_in_bits {
 	u8         opcode[0x10];
 	u8         reserved_0[0x10];
 
 	u8         reserved_1[0x10];
 	u8         op_mod[0x10];
 
 	u8         mkey[0x20];
 
 	u8         reserved_2[0x20];
 };
 
 struct mlx5_ifc_set_rate_limit_out_bits {
 	u8         status[0x8];
 	u8         reserved_at_8[0x18];
 
 	u8         syndrome[0x20];
 
 	u8         reserved_at_40[0x40];
 };
 
 struct mlx5_ifc_set_rate_limit_in_bits {
 	u8         opcode[0x10];
 	u8         reserved_at_10[0x10];
 
 	u8         reserved_at_20[0x10];
 	u8         op_mod[0x10];
 
 	u8         reserved_at_40[0x10];
 	u8         rate_limit_index[0x10];
 
 	u8         reserved_at_60[0x20];
 
 	u8         rate_limit[0x20];
 	u8         burst_upper_bound[0x20];
 };
 
 struct mlx5_ifc_access_register_out_bits {
 	u8         status[0x8];
 	u8         reserved_0[0x18];
 
 	u8         syndrome[0x20];
 
 	u8         reserved_1[0x40];
 
 	u8         register_data[0][0x20];
 };
 
 enum {
 	MLX5_ACCESS_REGISTER_IN_OP_MOD_WRITE  = 0x0,
 	MLX5_ACCESS_REGISTER_IN_OP_MOD_READ   = 0x1,
 };
 
 struct mlx5_ifc_access_register_in_bits {
 	u8         opcode[0x10];
 	u8         reserved_0[0x10];
 
 	u8         reserved_1[0x10];
 	u8         op_mod[0x10];
 
 	u8         reserved_2[0x10];
 	u8         register_id[0x10];
 
 	u8         argument[0x20];
 
 	u8         register_data[0][0x20];
 };
 
 struct mlx5_ifc_sltp_reg_bits {
 	u8         status[0x4];
 	u8         version[0x4];
 	u8         local_port[0x8];
 	u8         pnat[0x2];
 	u8         reserved_0[0x2];
 	u8         lane[0x4];
 	u8         reserved_1[0x8];
 
 	u8         reserved_2[0x20];
 
 	u8         reserved_3[0x7];
 	u8         polarity[0x1];
 	u8         ob_tap0[0x8];
 	u8         ob_tap1[0x8];
 	u8         ob_tap2[0x8];
 
 	u8         reserved_4[0xc];
 	u8         ob_preemp_mode[0x4];
 	u8         ob_reg[0x8];
 	u8         ob_bias[0x8];
 
 	u8         reserved_5[0x20];
 };
 
 struct mlx5_ifc_slrp_reg_bits {
 	u8         status[0x4];
 	u8         version[0x4];
 	u8         local_port[0x8];
 	u8         pnat[0x2];
 	u8         reserved_0[0x2];
 	u8         lane[0x4];
 	u8         reserved_1[0x8];
 
 	u8         ib_sel[0x2];
 	u8         reserved_2[0x11];
 	u8         dp_sel[0x1];
 	u8         dp90sel[0x4];
 	u8         mix90phase[0x8];
 
 	u8         ffe_tap0[0x8];
 	u8         ffe_tap1[0x8];
 	u8         ffe_tap2[0x8];
 	u8         ffe_tap3[0x8];
 
 	u8         ffe_tap4[0x8];
 	u8         ffe_tap5[0x8];
 	u8         ffe_tap6[0x8];
 	u8         ffe_tap7[0x8];
 
 	u8         ffe_tap8[0x8];
 	u8         mixerbias_tap_amp[0x8];
 	u8         reserved_3[0x7];
 	u8         ffe_tap_en[0x9];
 
 	u8         ffe_tap_offset0[0x8];
 	u8         ffe_tap_offset1[0x8];
 	u8         slicer_offset0[0x10];
 
 	u8         mixer_offset0[0x10];
 	u8         mixer_offset1[0x10];
 
 	u8         mixerbgn_inp[0x8];
 	u8         mixerbgn_inn[0x8];
 	u8         mixerbgn_refp[0x8];
 	u8         mixerbgn_refn[0x8];
 
 	u8         sel_slicer_lctrl_h[0x1];
 	u8         sel_slicer_lctrl_l[0x1];
 	u8         reserved_4[0x1];
 	u8         ref_mixer_vreg[0x5];
 	u8         slicer_gctrl[0x8];
 	u8         lctrl_input[0x8];
 	u8         mixer_offset_cm1[0x8];
 
 	u8         common_mode[0x6];
 	u8         reserved_5[0x1];
 	u8         mixer_offset_cm0[0x9];
 	u8         reserved_6[0x7];
 	u8         slicer_offset_cm[0x9];
 };
 
 struct mlx5_ifc_slrg_reg_bits {
 	u8         status[0x4];
 	u8         version[0x4];
 	u8         local_port[0x8];
 	u8         pnat[0x2];
 	u8         reserved_0[0x2];
 	u8         lane[0x4];
 	u8         reserved_1[0x8];
 
 	u8         time_to_link_up[0x10];
 	u8         reserved_2[0xc];
 	u8         grade_lane_speed[0x4];
 
 	u8         grade_version[0x8];
 	u8         grade[0x18];
 
 	u8         reserved_3[0x4];
 	u8         height_grade_type[0x4];
 	u8         height_grade[0x18];
 
 	u8         height_dz[0x10];
 	u8         height_dv[0x10];
 
 	u8         reserved_4[0x10];
 	u8         height_sigma[0x10];
 
 	u8         reserved_5[0x20];
 
 	u8         reserved_6[0x4];
 	u8         phase_grade_type[0x4];
 	u8         phase_grade[0x18];
 
 	u8         reserved_7[0x8];
 	u8         phase_eo_pos[0x8];
 	u8         reserved_8[0x8];
 	u8         phase_eo_neg[0x8];
 
 	u8         ffe_set_tested[0x10];
 	u8         test_errors_per_lane[0x10];
 };
 
 struct mlx5_ifc_pvlc_reg_bits {
 	u8         reserved_0[0x8];
 	u8         local_port[0x8];
 	u8         reserved_1[0x10];
 
 	u8         reserved_2[0x1c];
 	u8         vl_hw_cap[0x4];
 
 	u8         reserved_3[0x1c];
 	u8         vl_admin[0x4];
 
 	u8         reserved_4[0x1c];
 	u8         vl_operational[0x4];
 };
 
 struct mlx5_ifc_pude_reg_bits {
 	u8         swid[0x8];
 	u8         local_port[0x8];
 	u8         reserved_0[0x4];
 	u8         admin_status[0x4];
 	u8         reserved_1[0x4];
 	u8         oper_status[0x4];
 
 	u8         reserved_2[0x60];
 };
 
 enum {
 	MLX5_PTYS_REG_PROTO_MASK_INFINIBAND  = 0x1,
 	MLX5_PTYS_REG_PROTO_MASK_ETHERNET    = 0x4,
 };
 
 struct mlx5_ifc_ptys_reg_bits {
 	u8         reserved_0[0x1];
 	u8         an_disable_admin[0x1];
 	u8         an_disable_cap[0x1];
 	u8         reserved_1[0x4];
 	u8         force_tx_aba_param[0x1];
 	u8         local_port[0x8];
 	u8         reserved_2[0xd];
 	u8         proto_mask[0x3];
 
 	u8         an_status[0x4];
 	u8         reserved_3[0xc];
 	u8         data_rate_oper[0x10];
 
 	u8         fc_proto_capability[0x20];
 
 	u8         eth_proto_capability[0x20];
 
 	u8         ib_link_width_capability[0x10];
 	u8         ib_proto_capability[0x10];
 
 	u8         fc_proto_admin[0x20];
 
 	u8         eth_proto_admin[0x20];
 
 	u8         ib_link_width_admin[0x10];
 	u8         ib_proto_admin[0x10];
 
 	u8         fc_proto_oper[0x20];
 
 	u8         eth_proto_oper[0x20];
 
 	u8         ib_link_width_oper[0x10];
 	u8         ib_proto_oper[0x10];
 
 	u8         reserved_4[0x20];
 
 	u8         eth_proto_lp_advertise[0x20];
 
 	u8         reserved_5[0x60];
 };
 
 struct mlx5_ifc_ptas_reg_bits {
 	u8         reserved_0[0x20];
 
 	u8         algorithm_options[0x10];
 	u8         reserved_1[0x4];
 	u8         repetitions_mode[0x4];
 	u8         num_of_repetitions[0x8];
 
 	u8         grade_version[0x8];
 	u8         height_grade_type[0x4];
 	u8         phase_grade_type[0x4];
 	u8         height_grade_weight[0x8];
 	u8         phase_grade_weight[0x8];
 
 	u8         gisim_measure_bits[0x10];
 	u8         adaptive_tap_measure_bits[0x10];
 
 	u8         ber_bath_high_error_threshold[0x10];
 	u8         ber_bath_mid_error_threshold[0x10];
 
 	u8         ber_bath_low_error_threshold[0x10];
 	u8         one_ratio_high_threshold[0x10];
 
 	u8         one_ratio_high_mid_threshold[0x10];
 	u8         one_ratio_low_mid_threshold[0x10];
 
 	u8         one_ratio_low_threshold[0x10];
 	u8         ndeo_error_threshold[0x10];
 
 	u8         mixer_offset_step_size[0x10];
 	u8         reserved_2[0x8];
 	u8         mix90_phase_for_voltage_bath[0x8];
 
 	u8         mixer_offset_start[0x10];
 	u8         mixer_offset_end[0x10];
 
 	u8         reserved_3[0x15];
 	u8         ber_test_time[0xb];
 };
 
 struct mlx5_ifc_pspa_reg_bits {
 	u8         swid[0x8];
 	u8         local_port[0x8];
 	u8         sub_port[0x8];
 	u8         reserved_0[0x8];
 
 	u8         reserved_1[0x20];
 };
 
 struct mlx5_ifc_ppsc_reg_bits {
 	u8         reserved_0[0x8];
 	u8         local_port[0x8];
 	u8         reserved_1[0x10];
 
 	u8         reserved_2[0x60];
 
 	u8         reserved_3[0x1c];
 	u8         wrps_admin[0x4];
 
 	u8         reserved_4[0x1c];
 	u8         wrps_status[0x4];
 
 	u8         up_th_vld[0x1];
 	u8         down_th_vld[0x1];
 	u8         reserved_5[0x6];
 	u8         up_threshold[0x8];
 	u8         reserved_6[0x8];
 	u8         down_threshold[0x8];
 
 	u8         reserved_7[0x20];
 
 	u8         reserved_8[0x1c];
 	u8         srps_admin[0x4];
 
 	u8         reserved_9[0x60];
 };
 
 struct mlx5_ifc_pplr_reg_bits {
 	u8         reserved_0[0x8];
 	u8         local_port[0x8];
 	u8         reserved_1[0x10];
 
 	u8         reserved_2[0x8];
 	u8         lb_cap[0x8];
 	u8         reserved_3[0x8];
 	u8         lb_en[0x8];
 };
 
 struct mlx5_ifc_pplm_reg_bits {
 	u8         reserved_0[0x8];
 	u8         local_port[0x8];
 	u8         reserved_1[0x10];
 
 	u8         reserved_2[0x20];
 
 	u8         port_profile_mode[0x8];
 	u8         static_port_profile[0x8];
 	u8         active_port_profile[0x8];
 	u8         reserved_3[0x8];
 
 	u8         retransmission_active[0x8];
 	u8         fec_mode_active[0x18];
 
 	u8         reserved_4[0x10];
 	u8         v_100g_fec_override_cap[0x4];
 	u8         v_50g_fec_override_cap[0x4];
 	u8         v_25g_fec_override_cap[0x4];
 	u8         v_10g_40g_fec_override_cap[0x4];
 
 	u8         reserved_5[0x10];
 	u8         v_100g_fec_override_admin[0x4];
 	u8         v_50g_fec_override_admin[0x4];
 	u8         v_25g_fec_override_admin[0x4];
 	u8         v_10g_40g_fec_override_admin[0x4];
 };
 
 struct mlx5_ifc_ppll_reg_bits {
 	u8         num_pll_groups[0x8];
 	u8         pll_group[0x8];
 	u8         reserved_0[0x4];
 	u8         num_plls[0x4];
 	u8         reserved_1[0x8];
 
 	u8         reserved_2[0x1f];
 	u8         ae[0x1];
 
 	u8         pll_status[4][0x40];
 };
 
 struct mlx5_ifc_ppad_reg_bits {
 	u8         reserved_0[0x3];
 	u8         single_mac[0x1];
 	u8         reserved_1[0x4];
 	u8         local_port[0x8];
 	u8         mac_47_32[0x10];
 
 	u8         mac_31_0[0x20];
 
 	u8         reserved_2[0x40];
 };
 
 struct mlx5_ifc_pmtu_reg_bits {
 	u8         reserved_0[0x8];
 	u8         local_port[0x8];
 	u8         reserved_1[0x10];
 
 	u8         max_mtu[0x10];
 	u8         reserved_2[0x10];
 
 	u8         admin_mtu[0x10];
 	u8         reserved_3[0x10];
 
 	u8         oper_mtu[0x10];
 	u8         reserved_4[0x10];
 };
 
 struct mlx5_ifc_pmpr_reg_bits {
 	u8         reserved_0[0x8];
 	u8         module[0x8];
 	u8         reserved_1[0x10];
 
 	u8         reserved_2[0x18];
 	u8         attenuation_5g[0x8];
 
 	u8         reserved_3[0x18];
 	u8         attenuation_7g[0x8];
 
 	u8         reserved_4[0x18];
 	u8         attenuation_12g[0x8];
 };
 
 struct mlx5_ifc_pmpe_reg_bits {
 	u8         reserved_0[0x8];
 	u8         module[0x8];
 	u8         reserved_1[0xc];
 	u8         module_status[0x4];
 
 	u8         reserved_2[0x14];
 	u8         error_type[0x4];
 	u8         reserved_3[0x8];
 
 	u8         reserved_4[0x40];
 };
 
 struct mlx5_ifc_pmpc_reg_bits {
 	u8         module_state_updated[32][0x8];
 };
 
 struct mlx5_ifc_pmlpn_reg_bits {
 	u8         reserved_0[0x4];
 	u8         mlpn_status[0x4];
 	u8         local_port[0x8];
 	u8         reserved_1[0x10];
 
 	u8         e[0x1];
 	u8         reserved_2[0x1f];
 };
 
 struct mlx5_ifc_pmlp_reg_bits {
 	u8         rxtx[0x1];
 	u8         reserved_0[0x7];
 	u8         local_port[0x8];
 	u8         reserved_1[0x8];
 	u8         width[0x8];
 
 	u8         lane0_module_mapping[0x20];
 
 	u8         lane1_module_mapping[0x20];
 
 	u8         lane2_module_mapping[0x20];
 
 	u8         lane3_module_mapping[0x20];
 
 	u8         reserved_2[0x160];
 };
 
 struct mlx5_ifc_pmaos_reg_bits {
 	u8         reserved_0[0x8];
 	u8         module[0x8];
 	u8         reserved_1[0x4];
 	u8         admin_status[0x4];
 	u8         reserved_2[0x4];
 	u8         oper_status[0x4];
 
 	u8         ase[0x1];
 	u8         ee[0x1];
 	u8         reserved_3[0x12];
 	u8         error_type[0x4];
 	u8         reserved_4[0x6];
 	u8         e[0x2];
 
 	u8         reserved_5[0x40];
 };
 
 struct mlx5_ifc_plpc_reg_bits {
 	u8         reserved_0[0x4];
 	u8         profile_id[0xc];
 	u8         reserved_1[0x4];
 	u8         proto_mask[0x4];
 	u8         reserved_2[0x8];
 
 	u8         reserved_3[0x10];
 	u8         lane_speed[0x10];
 
 	u8         reserved_4[0x17];
 	u8         lpbf[0x1];
 	u8         fec_mode_policy[0x8];
 
 	u8         retransmission_capability[0x8];
 	u8         fec_mode_capability[0x18];
 
 	u8         retransmission_support_admin[0x8];
 	u8         fec_mode_support_admin[0x18];
 
 	u8         retransmission_request_admin[0x8];
 	u8         fec_mode_request_admin[0x18];
 
 	u8         reserved_5[0x80];
 };
 
 struct mlx5_ifc_pll_status_data_bits {
 	u8         reserved_0[0x1];
 	u8         lock_cal[0x1];
 	u8         lock_status[0x2];
 	u8         reserved_1[0x2];
 	u8         algo_f_ctrl[0xa];
 	u8         analog_algo_num_var[0x6];
 	u8         f_ctrl_measure[0xa];
 
 	u8         reserved_2[0x2];
 	u8         analog_var[0x6];
 	u8         reserved_3[0x2];
 	u8         high_var[0x6];
 	u8         reserved_4[0x2];
 	u8         low_var[0x6];
 	u8         reserved_5[0x2];
 	u8         mid_val[0x6];
 };
 
 struct mlx5_ifc_plib_reg_bits {
 	u8         reserved_0[0x8];
 	u8         local_port[0x8];
 	u8         reserved_1[0x8];
 	u8         ib_port[0x8];
 
 	u8         reserved_2[0x60];
 };
 
 struct mlx5_ifc_plbf_reg_bits {
 	u8         reserved_0[0x8];
 	u8         local_port[0x8];
 	u8         reserved_1[0xd];
 	u8         lbf_mode[0x3];
 
 	u8         reserved_2[0x20];
 };
 
 struct mlx5_ifc_pipg_reg_bits {
 	u8         reserved_0[0x8];
 	u8         local_port[0x8];
 	u8         reserved_1[0x10];
 
 	u8         dic[0x1];
 	u8         reserved_2[0x19];
 	u8         ipg[0x4];
 	u8         reserved_3[0x2];
 };
 
 struct mlx5_ifc_pifr_reg_bits {
 	u8         reserved_0[0x8];
 	u8         local_port[0x8];
 	u8         reserved_1[0x10];
 
 	u8         reserved_2[0xe0];
 
 	u8         port_filter[8][0x20];
 
 	u8         port_filter_update_en[8][0x20];
 };
 
 struct mlx5_ifc_phys_layer_cntrs_bits {
 	u8         time_since_last_clear_high[0x20];
 
 	u8         time_since_last_clear_low[0x20];
 
 	u8         symbol_errors_high[0x20];
 
 	u8         symbol_errors_low[0x20];
 
 	u8         sync_headers_errors_high[0x20];
 
 	u8         sync_headers_errors_low[0x20];
 
 	u8         edpl_bip_errors_lane0_high[0x20];
 
 	u8         edpl_bip_errors_lane0_low[0x20];
 
 	u8         edpl_bip_errors_lane1_high[0x20];
 
 	u8         edpl_bip_errors_lane1_low[0x20];
 
 	u8         edpl_bip_errors_lane2_high[0x20];
 
 	u8         edpl_bip_errors_lane2_low[0x20];
 
 	u8         edpl_bip_errors_lane3_high[0x20];
 
 	u8         edpl_bip_errors_lane3_low[0x20];
 
 	u8         fc_fec_corrected_blocks_lane0_high[0x20];
 
 	u8         fc_fec_corrected_blocks_lane0_low[0x20];
 
 	u8         fc_fec_corrected_blocks_lane1_high[0x20];
 
 	u8         fc_fec_corrected_blocks_lane1_low[0x20];
 
 	u8         fc_fec_corrected_blocks_lane2_high[0x20];
 
 	u8         fc_fec_corrected_blocks_lane2_low[0x20];
 
 	u8         fc_fec_corrected_blocks_lane3_high[0x20];
 
 	u8         fc_fec_corrected_blocks_lane3_low[0x20];
 
 	u8         fc_fec_uncorrectable_blocks_lane0_high[0x20];
 
 	u8         fc_fec_uncorrectable_blocks_lane0_low[0x20];
 
 	u8         fc_fec_uncorrectable_blocks_lane1_high[0x20];
 
 	u8         fc_fec_uncorrectable_blocks_lane1_low[0x20];
 
 	u8         fc_fec_uncorrectable_blocks_lane2_high[0x20];
 
 	u8         fc_fec_uncorrectable_blocks_lane2_low[0x20];
 
 	u8         fc_fec_uncorrectable_blocks_lane3_high[0x20];
 
 	u8         fc_fec_uncorrectable_blocks_lane3_low[0x20];
 
 	u8         rs_fec_corrected_blocks_high[0x20];
 
 	u8         rs_fec_corrected_blocks_low[0x20];
 
 	u8         rs_fec_uncorrectable_blocks_high[0x20];
 
 	u8         rs_fec_uncorrectable_blocks_low[0x20];
 
 	u8         rs_fec_no_errors_blocks_high[0x20];
 
 	u8         rs_fec_no_errors_blocks_low[0x20];
 
 	u8         rs_fec_single_error_blocks_high[0x20];
 
 	u8         rs_fec_single_error_blocks_low[0x20];
 
 	u8         rs_fec_corrected_symbols_total_high[0x20];
 
 	u8         rs_fec_corrected_symbols_total_low[0x20];
 
 	u8         rs_fec_corrected_symbols_lane0_high[0x20];
 
 	u8         rs_fec_corrected_symbols_lane0_low[0x20];
 
 	u8         rs_fec_corrected_symbols_lane1_high[0x20];
 
 	u8         rs_fec_corrected_symbols_lane1_low[0x20];
 
 	u8         rs_fec_corrected_symbols_lane2_high[0x20];
 
 	u8         rs_fec_corrected_symbols_lane2_low[0x20];
 
 	u8         rs_fec_corrected_symbols_lane3_high[0x20];
 
 	u8         rs_fec_corrected_symbols_lane3_low[0x20];
 
 	u8         link_down_events[0x20];
 
 	u8         successful_recovery_events[0x20];
 
 	u8         reserved_0[0x180];
 };
 
 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits {
 	u8	   symbol_error_counter[0x10];
 
 	u8         link_error_recovery_counter[0x8];
 
 	u8         link_downed_counter[0x8];
 
 	u8         port_rcv_errors[0x10];
 
 	u8         port_rcv_remote_physical_errors[0x10];
 
 	u8         port_rcv_switch_relay_errors[0x10];
 
 	u8         port_xmit_discards[0x10];
 
 	u8         port_xmit_constraint_errors[0x8];
 
 	u8         port_rcv_constraint_errors[0x8];
 
 	u8         reserved_at_70[0x8];
 
 	u8         link_overrun_errors[0x8];
 
 	u8	   reserved_at_80[0x10];
 
 	u8         vl_15_dropped[0x10];
 
 	u8	   reserved_at_a0[0xa0];
 };
 
 struct mlx5_ifc_phys_layer_statistical_cntrs_bits {
 	u8         time_since_last_clear_high[0x20];
 
 	u8         time_since_last_clear_low[0x20];
 
 	u8         phy_received_bits_high[0x20];
 
 	u8         phy_received_bits_low[0x20];
 
 	u8         phy_symbol_errors_high[0x20];
 
 	u8         phy_symbol_errors_low[0x20];
 
 	u8         phy_corrected_bits_high[0x20];
 
 	u8         phy_corrected_bits_low[0x20];
 
 	u8         phy_corrected_bits_lane0_high[0x20];
 
 	u8         phy_corrected_bits_lane0_low[0x20];
 
 	u8         phy_corrected_bits_lane1_high[0x20];
 
 	u8         phy_corrected_bits_lane1_low[0x20];
 
 	u8         phy_corrected_bits_lane2_high[0x20];
 
 	u8         phy_corrected_bits_lane2_low[0x20];
 
 	u8         phy_corrected_bits_lane3_high[0x20];
 
 	u8         phy_corrected_bits_lane3_low[0x20];
 
 	u8         reserved_at_200[0x5c0];
 };
 
 struct mlx5_ifc_infiniband_port_cntrs_bits {
 	u8         symbol_error_counter[0x10];
 	u8         link_error_recovery_counter[0x8];
 	u8         link_downed_counter[0x8];
 
 	u8         port_rcv_errors[0x10];
 	u8         port_rcv_remote_physical_errors[0x10];
 
 	u8         port_rcv_switch_relay_errors[0x10];
 	u8         port_xmit_discards[0x10];
 
 	u8         port_xmit_constraint_errors[0x8];
 	u8         port_rcv_constraint_errors[0x8];
 	u8         reserved_0[0x8];
 	u8         local_link_integrity_errors[0x4];
 	u8         excessive_buffer_overrun_errors[0x4];
 
 	u8         reserved_1[0x10];
 	u8         vl_15_dropped[0x10];
 
 	u8         port_xmit_data[0x20];
 
 	u8         port_rcv_data[0x20];
 
 	u8         port_xmit_pkts[0x20];
 
 	u8         port_rcv_pkts[0x20];
 
 	u8         port_xmit_wait[0x20];
 
 	u8         reserved_2[0x680];
 };
 
 struct mlx5_ifc_phrr_reg_bits {
 	u8         clr[0x1];
 	u8         reserved_0[0x7];
 	u8         local_port[0x8];
 	u8         reserved_1[0x10];
 
 	u8         hist_group[0x8];
 	u8         reserved_2[0x10];
 	u8         hist_id[0x8];
 
 	u8         reserved_3[0x40];
 
 	u8         time_since_last_clear_high[0x20];
 
 	u8         time_since_last_clear_low[0x20];
 
 	u8         bin[10][0x20];
 };
 
 struct mlx5_ifc_phbr_for_prio_reg_bits {
 	u8         reserved_0[0x18];
 	u8         prio[0x8];
 };
 
 struct mlx5_ifc_phbr_for_port_tclass_reg_bits {
 	u8         reserved_0[0x18];
 	u8         tclass[0x8];
 };
 
 struct mlx5_ifc_phbr_binding_reg_bits {
 	u8         opcode[0x4];
 	u8         reserved_0[0x4];
 	u8         local_port[0x8];
 	u8         pnat[0x2];
 	u8         reserved_1[0xe];
 
 	u8         hist_group[0x8];
 	u8         reserved_2[0x10];
 	u8         hist_id[0x8];
 
 	u8         reserved_3[0x10];
 	u8         hist_type[0x10];
 
 	u8         hist_parameters[0x20];
 
 	u8         hist_min_value[0x20];
 
 	u8         hist_max_value[0x20];
 
 	u8         sample_time[0x20];
 };
 
 enum {
 	MLX5_PFCC_REG_PPAN_DISABLED  = 0x0,
 	MLX5_PFCC_REG_PPAN_ENABLED   = 0x1,
 };
 
 struct mlx5_ifc_pfcc_reg_bits {
 	u8         dcbx_operation_type[0x2];
 	u8         cap_local_admin[0x1];
 	u8         cap_remote_admin[0x1];
 	u8         reserved_0[0x4];
 	u8         local_port[0x8];
 	u8         pnat[0x2];
 	u8         reserved_1[0xc];
 	u8         shl_cap[0x1];
 	u8         shl_opr[0x1];
 
 	u8         ppan[0x4];
 	u8         reserved_2[0x4];
 	u8         prio_mask_tx[0x8];
 	u8         reserved_3[0x8];
 	u8         prio_mask_rx[0x8];
 
 	u8         pptx[0x1];
 	u8         aptx[0x1];
 	u8         reserved_4[0x6];
 	u8         pfctx[0x8];
 	u8         reserved_5[0x8];
 	u8         cbftx[0x8];
 
 	u8         pprx[0x1];
 	u8         aprx[0x1];
 	u8         reserved_6[0x6];
 	u8         pfcrx[0x8];
 	u8         reserved_7[0x8];
 	u8         cbfrx[0x8];
 
 	u8         device_stall_minor_watermark[0x10];
 	u8         device_stall_critical_watermark[0x10];
 
 	u8         reserved_8[0x60];
 };
 
 struct mlx5_ifc_pelc_reg_bits {
 	u8         op[0x4];
 	u8         reserved_0[0x4];
 	u8         local_port[0x8];
 	u8         reserved_1[0x10];
 
 	u8         op_admin[0x8];
 	u8         op_capability[0x8];
 	u8         op_request[0x8];
 	u8         op_active[0x8];
 
 	u8         admin[0x40];
 
 	u8         capability[0x40];
 
 	u8         request[0x40];
 
 	u8         active[0x40];
 
 	u8         reserved_2[0x80];
 };
 
 struct mlx5_ifc_peir_reg_bits {
 	u8         reserved_0[0x8];
 	u8         local_port[0x8];
 	u8         reserved_1[0x10];
 
 	u8         reserved_2[0xc];
 	u8         error_count[0x4];
 	u8         reserved_3[0x10];
 
 	u8         reserved_4[0xc];
 	u8         lane[0x4];
 	u8         reserved_5[0x8];
 	u8         error_type[0x8];
 };
 
 struct mlx5_ifc_qcam_access_reg_cap_mask {
 	u8         qcam_access_reg_cap_mask_127_to_20[0x6C];
 	u8         qpdpm[0x1];
 	u8         qcam_access_reg_cap_mask_18_to_4[0x0F];
 	u8         qdpm[0x1];
 	u8         qpts[0x1];
 	u8         qcap[0x1];
 	u8         qcam_access_reg_cap_mask_0[0x1];
 };
 
 struct mlx5_ifc_qcam_qos_feature_cap_mask {
 	u8         qcam_qos_feature_cap_mask_127_to_1[0x7F];
 	u8         qpts_trust_both[0x1];
 };
 
 struct mlx5_ifc_qcam_reg_bits {
 	u8         reserved_at_0[0x8];
 	u8         feature_group[0x8];
 	u8         reserved_at_10[0x8];
 	u8         access_reg_group[0x8];
 	u8         reserved_at_20[0x20];
 
 	union {
 		struct mlx5_ifc_qcam_access_reg_cap_mask reg_cap;
 		u8  reserved_at_0[0x80];
 	} qos_access_reg_cap_mask;
 
 	u8         reserved_at_c0[0x80];
 
 	union {
 		struct mlx5_ifc_qcam_qos_feature_cap_mask feature_cap;
 		u8  reserved_at_0[0x80];
 	} qos_feature_cap_mask;
 
 	u8         reserved_at_1c0[0x80];
 };
 
 struct mlx5_ifc_pcap_reg_bits {
 	u8         reserved_0[0x8];
 	u8         local_port[0x8];
 	u8         reserved_1[0x10];
 
 	u8         port_capability_mask[4][0x20];
 };
 
 struct mlx5_ifc_pbmc_reg_bits {
 	u8         reserved_0[0x8];
 	u8         local_port[0x8];
 	u8         reserved_1[0x10];
 
 	u8         xoff_timer_value[0x10];
 	u8         xoff_refresh[0x10];
 
 	u8         reserved_2[0x10];
 	u8         port_buffer_size[0x10];
 
 	struct mlx5_ifc_bufferx_reg_bits buffer[10];
 
 	u8         reserved_3[0x40];
 
 	u8         port_shared_buffer[0x40];
 };
 
 struct mlx5_ifc_paos_reg_bits {
 	u8         swid[0x8];
 	u8         local_port[0x8];
 	u8         reserved_0[0x4];
 	u8         admin_status[0x4];
 	u8         reserved_1[0x4];
 	u8         oper_status[0x4];
 
 	u8         ase[0x1];
 	u8         ee[0x1];
 	u8         reserved_2[0x1c];
 	u8         e[0x2];
 
 	u8         reserved_3[0x40];
 };
 
 struct mlx5_ifc_pamp_reg_bits {
 	u8         reserved_0[0x8];
 	u8         opamp_group[0x8];
 	u8         reserved_1[0xc];
 	u8         opamp_group_type[0x4];
 
 	u8         start_index[0x10];
 	u8         reserved_2[0x4];
 	u8         num_of_indices[0xc];
 
 	u8         index_data[18][0x10];
 };
 
 struct mlx5_ifc_link_level_retrans_cntr_grp_date_bits {
 	u8         llr_rx_cells_high[0x20];
 
 	u8         llr_rx_cells_low[0x20];
 
 	u8         llr_rx_error_high[0x20];
 
 	u8         llr_rx_error_low[0x20];
 
 	u8         llr_rx_crc_error_high[0x20];
 
 	u8         llr_rx_crc_error_low[0x20];
 
 	u8         llr_tx_cells_high[0x20];
 
 	u8         llr_tx_cells_low[0x20];
 
 	u8         llr_tx_ret_cells_high[0x20];
 
 	u8         llr_tx_ret_cells_low[0x20];
 
 	u8         llr_tx_ret_events_high[0x20];
 
 	u8         llr_tx_ret_events_low[0x20];
 
 	u8         reserved_0[0x640];
 };
 
+struct mlx5_ifc_mtmp_reg_bits {
+	u8         i[0x1];
+	u8         reserved_at_1[0x18];
+	u8         sensor_index[0x7];
+
+	u8         reserved_at_20[0x10];
+	u8         temperature[0x10];
+
+	u8         mte[0x1];
+	u8         mtr[0x1];
+	u8         reserved_at_42[0x0e];
+	u8         max_temperature[0x10];
+
+	u8         tee[0x2];
+	u8         reserved_at_62[0x0e];
+	u8         temperature_threshold_hi[0x10];
+
+	u8         reserved_at_80[0x10];
+	u8         temperature_threshold_lo[0x10];
+
+	u8         reserved_at_100[0x20];
+
+	u8         sensor_name[0x40];
+};
+
 struct mlx5_ifc_lane_2_module_mapping_bits {
 	u8         reserved_0[0x6];
 	u8         rx_lane[0x2];
 	u8         reserved_1[0x6];
 	u8         tx_lane[0x2];
 	u8         reserved_2[0x8];
 	u8         module[0x8];
 };
 
 struct mlx5_ifc_eth_per_traffic_class_layout_bits {
 	u8         transmit_queue_high[0x20];
 
 	u8         transmit_queue_low[0x20];
 
 	u8         reserved_0[0x780];
 };
 
 struct mlx5_ifc_eth_per_traffic_class_cong_layout_bits {
 	u8         no_buffer_discard_uc_high[0x20];
 
 	u8         no_buffer_discard_uc_low[0x20];
 
 	u8         wred_discard_high[0x20];
 
 	u8         wred_discard_low[0x20];
 
 	u8         reserved_0[0x740];
 };
 
 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits {
 	u8         rx_octets_high[0x20];
 
 	u8         rx_octets_low[0x20];
 
 	u8         reserved_0[0xc0];
 
 	u8         rx_frames_high[0x20];
 
 	u8         rx_frames_low[0x20];
 
 	u8         tx_octets_high[0x20];
 
 	u8         tx_octets_low[0x20];
 
 	u8         reserved_1[0xc0];
 
 	u8         tx_frames_high[0x20];
 
 	u8         tx_frames_low[0x20];
 
 	u8         rx_pause_high[0x20];
 
 	u8         rx_pause_low[0x20];
 
 	u8         rx_pause_duration_high[0x20];
 
 	u8         rx_pause_duration_low[0x20];
 
 	u8         tx_pause_high[0x20];
 
 	u8         tx_pause_low[0x20];
 
 	u8         tx_pause_duration_high[0x20];
 
 	u8         tx_pause_duration_low[0x20];
 
 	u8         rx_pause_transition_high[0x20];
 
 	u8         rx_pause_transition_low[0x20];
 
 	u8         rx_discards_high[0x20];
 
 	u8         rx_discards_low[0x20];
 
 	u8         device_stall_minor_watermark_cnt_high[0x20];
 
 	u8         device_stall_minor_watermark_cnt_low[0x20];
 
 	u8         device_stall_critical_watermark_cnt_high[0x20];
 
 	u8         device_stall_critical_watermark_cnt_low[0x20];
 
 	u8         reserved_2[0x340];
 };
 
 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits {
 	u8         port_transmit_wait_high[0x20];
 
 	u8         port_transmit_wait_low[0x20];
 
 	u8         ecn_marked_high[0x20];
 
 	u8         ecn_marked_low[0x20];
 
 	u8         no_buffer_discard_mc_high[0x20];
 
 	u8         no_buffer_discard_mc_low[0x20];
 
 	u8         reserved_0[0x700];
 };
 
 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits {
 	u8         a_frames_transmitted_ok_high[0x20];
 
 	u8         a_frames_transmitted_ok_low[0x20];
 
 	u8         a_frames_received_ok_high[0x20];
 
 	u8         a_frames_received_ok_low[0x20];
 
 	u8         a_frame_check_sequence_errors_high[0x20];
 
 	u8         a_frame_check_sequence_errors_low[0x20];
 
 	u8         a_alignment_errors_high[0x20];
 
 	u8         a_alignment_errors_low[0x20];
 
 	u8         a_octets_transmitted_ok_high[0x20];
 
 	u8         a_octets_transmitted_ok_low[0x20];
 
 	u8         a_octets_received_ok_high[0x20];
 
 	u8         a_octets_received_ok_low[0x20];
 
 	u8         a_multicast_frames_xmitted_ok_high[0x20];
 
 	u8         a_multicast_frames_xmitted_ok_low[0x20];
 
 	u8         a_broadcast_frames_xmitted_ok_high[0x20];
 
 	u8         a_broadcast_frames_xmitted_ok_low[0x20];
 
 	u8         a_multicast_frames_received_ok_high[0x20];
 
 	u8         a_multicast_frames_received_ok_low[0x20];
 
 	u8         a_broadcast_frames_recieved_ok_high[0x20];
 
 	u8         a_broadcast_frames_recieved_ok_low[0x20];
 
 	u8         a_in_range_length_errors_high[0x20];
 
 	u8         a_in_range_length_errors_low[0x20];
 
 	u8         a_out_of_range_length_field_high[0x20];
 
 	u8         a_out_of_range_length_field_low[0x20];
 
 	u8         a_frame_too_long_errors_high[0x20];
 
 	u8         a_frame_too_long_errors_low[0x20];
 
 	u8         a_symbol_error_during_carrier_high[0x20];
 
 	u8         a_symbol_error_during_carrier_low[0x20];
 
 	u8         a_mac_control_frames_transmitted_high[0x20];
 
 	u8         a_mac_control_frames_transmitted_low[0x20];
 
 	u8         a_mac_control_frames_received_high[0x20];
 
 	u8         a_mac_control_frames_received_low[0x20];
 
 	u8         a_unsupported_opcodes_received_high[0x20];
 
 	u8         a_unsupported_opcodes_received_low[0x20];
 
 	u8         a_pause_mac_ctrl_frames_received_high[0x20];
 
 	u8         a_pause_mac_ctrl_frames_received_low[0x20];
 
 	u8         a_pause_mac_ctrl_frames_transmitted_high[0x20];
 
 	u8         a_pause_mac_ctrl_frames_transmitted_low[0x20];
 
 	u8         reserved_0[0x300];
 };
 
 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits {
 	u8         dot3stats_alignment_errors_high[0x20];
 
 	u8         dot3stats_alignment_errors_low[0x20];
 
 	u8         dot3stats_fcs_errors_high[0x20];
 
 	u8         dot3stats_fcs_errors_low[0x20];
 
 	u8         dot3stats_single_collision_frames_high[0x20];
 
 	u8         dot3stats_single_collision_frames_low[0x20];
 
 	u8         dot3stats_multiple_collision_frames_high[0x20];
 
 	u8         dot3stats_multiple_collision_frames_low[0x20];
 
 	u8         dot3stats_sqe_test_errors_high[0x20];
 
 	u8         dot3stats_sqe_test_errors_low[0x20];
 
 	u8         dot3stats_deferred_transmissions_high[0x20];
 
 	u8         dot3stats_deferred_transmissions_low[0x20];
 
 	u8         dot3stats_late_collisions_high[0x20];
 
 	u8         dot3stats_late_collisions_low[0x20];
 
 	u8         dot3stats_excessive_collisions_high[0x20];
 
 	u8         dot3stats_excessive_collisions_low[0x20];
 
 	u8         dot3stats_internal_mac_transmit_errors_high[0x20];
 
 	u8         dot3stats_internal_mac_transmit_errors_low[0x20];
 
 	u8         dot3stats_carrier_sense_errors_high[0x20];
 
 	u8         dot3stats_carrier_sense_errors_low[0x20];
 
 	u8         dot3stats_frame_too_longs_high[0x20];
 
 	u8         dot3stats_frame_too_longs_low[0x20];
 
 	u8         dot3stats_internal_mac_receive_errors_high[0x20];
 
 	u8         dot3stats_internal_mac_receive_errors_low[0x20];
 
 	u8         dot3stats_symbol_errors_high[0x20];
 
 	u8         dot3stats_symbol_errors_low[0x20];
 
 	u8         dot3control_in_unknown_opcodes_high[0x20];
 
 	u8         dot3control_in_unknown_opcodes_low[0x20];
 
 	u8         dot3in_pause_frames_high[0x20];
 
 	u8         dot3in_pause_frames_low[0x20];
 
 	u8         dot3out_pause_frames_high[0x20];
 
 	u8         dot3out_pause_frames_low[0x20];
 
 	u8         reserved_0[0x3c0];
 };
 
 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits {
 	u8         if_in_octets_high[0x20];
 
 	u8         if_in_octets_low[0x20];
 
 	u8         if_in_ucast_pkts_high[0x20];
 
 	u8         if_in_ucast_pkts_low[0x20];
 
 	u8         if_in_discards_high[0x20];
 
 	u8         if_in_discards_low[0x20];
 
 	u8         if_in_errors_high[0x20];
 
 	u8         if_in_errors_low[0x20];
 
 	u8         if_in_unknown_protos_high[0x20];
 
 	u8         if_in_unknown_protos_low[0x20];
 
 	u8         if_out_octets_high[0x20];
 
 	u8         if_out_octets_low[0x20];
 
 	u8         if_out_ucast_pkts_high[0x20];
 
 	u8         if_out_ucast_pkts_low[0x20];
 
 	u8         if_out_discards_high[0x20];
 
 	u8         if_out_discards_low[0x20];
 
 	u8         if_out_errors_high[0x20];
 
 	u8         if_out_errors_low[0x20];
 
 	u8         if_in_multicast_pkts_high[0x20];
 
 	u8         if_in_multicast_pkts_low[0x20];
 
 	u8         if_in_broadcast_pkts_high[0x20];
 
 	u8         if_in_broadcast_pkts_low[0x20];
 
 	u8         if_out_multicast_pkts_high[0x20];
 
 	u8         if_out_multicast_pkts_low[0x20];
 
 	u8         if_out_broadcast_pkts_high[0x20];
 
 	u8         if_out_broadcast_pkts_low[0x20];
 
 	u8         reserved_0[0x480];
 };
 
 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits {
 	u8         ether_stats_drop_events_high[0x20];
 
 	u8         ether_stats_drop_events_low[0x20];
 
 	u8         ether_stats_octets_high[0x20];
 
 	u8         ether_stats_octets_low[0x20];
 
 	u8         ether_stats_pkts_high[0x20];
 
 	u8         ether_stats_pkts_low[0x20];
 
 	u8         ether_stats_broadcast_pkts_high[0x20];
 
 	u8         ether_stats_broadcast_pkts_low[0x20];
 
 	u8         ether_stats_multicast_pkts_high[0x20];
 
 	u8         ether_stats_multicast_pkts_low[0x20];
 
 	u8         ether_stats_crc_align_errors_high[0x20];
 
 	u8         ether_stats_crc_align_errors_low[0x20];
 
 	u8         ether_stats_undersize_pkts_high[0x20];
 
 	u8         ether_stats_undersize_pkts_low[0x20];
 
 	u8         ether_stats_oversize_pkts_high[0x20];
 
 	u8         ether_stats_oversize_pkts_low[0x20];
 
 	u8         ether_stats_fragments_high[0x20];
 
 	u8         ether_stats_fragments_low[0x20];
 
 	u8         ether_stats_jabbers_high[0x20];
 
 	u8         ether_stats_jabbers_low[0x20];
 
 	u8         ether_stats_collisions_high[0x20];
 
 	u8         ether_stats_collisions_low[0x20];
 
 	u8         ether_stats_pkts64octets_high[0x20];
 
 	u8         ether_stats_pkts64octets_low[0x20];
 
 	u8         ether_stats_pkts65to127octets_high[0x20];
 
 	u8         ether_stats_pkts65to127octets_low[0x20];
 
 	u8         ether_stats_pkts128to255octets_high[0x20];
 
 	u8         ether_stats_pkts128to255octets_low[0x20];
 
 	u8         ether_stats_pkts256to511octets_high[0x20];
 
 	u8         ether_stats_pkts256to511octets_low[0x20];
 
 	u8         ether_stats_pkts512to1023octets_high[0x20];
 
 	u8         ether_stats_pkts512to1023octets_low[0x20];
 
 	u8         ether_stats_pkts1024to1518octets_high[0x20];
 
 	u8         ether_stats_pkts1024to1518octets_low[0x20];
 
 	u8         ether_stats_pkts1519to2047octets_high[0x20];
 
 	u8         ether_stats_pkts1519to2047octets_low[0x20];
 
 	u8         ether_stats_pkts2048to4095octets_high[0x20];
 
 	u8         ether_stats_pkts2048to4095octets_low[0x20];
 
 	u8         ether_stats_pkts4096to8191octets_high[0x20];
 
 	u8         ether_stats_pkts4096to8191octets_low[0x20];
 
 	u8         ether_stats_pkts8192to10239octets_high[0x20];
 
 	u8         ether_stats_pkts8192to10239octets_low[0x20];
 
 	u8         reserved_0[0x280];
 };
 
 struct mlx5_ifc_ib_portcntrs_attribute_grp_data_bits {
 	u8         symbol_error_counter[0x10];
 	u8         link_error_recovery_counter[0x8];
 	u8         link_downed_counter[0x8];
 
 	u8         port_rcv_errors[0x10];
 	u8         port_rcv_remote_physical_errors[0x10];
 
 	u8         port_rcv_switch_relay_errors[0x10];
 	u8         port_xmit_discards[0x10];
 
 	u8         port_xmit_constraint_errors[0x8];
 	u8         port_rcv_constraint_errors[0x8];
 	u8         reserved_0[0x8];
 	u8         local_link_integrity_errors[0x4];
 	u8         excessive_buffer_overrun_errors[0x4];
 
 	u8         reserved_1[0x10];
 	u8         vl_15_dropped[0x10];
 
 	u8         port_xmit_data[0x20];
 
 	u8         port_rcv_data[0x20];
 
 	u8         port_xmit_pkts[0x20];
 
 	u8         port_rcv_pkts[0x20];
 
 	u8         port_xmit_wait[0x20];
 
 	u8         reserved_2[0x680];
 };
 
 struct mlx5_ifc_trc_tlb_reg_bits {
 	u8         reserved_0[0x80];
 
 	u8         tlb_addr[0][0x40];
 };
 
 struct mlx5_ifc_trc_read_fifo_reg_bits {
 	u8         reserved_0[0x10];
 	u8         requested_event_num[0x10];
 
 	u8         reserved_1[0x20];
 
 	u8         reserved_2[0x10];
 	u8         acual_event_num[0x10];
 
 	u8         reserved_3[0x20];
 
 	u8         event[0][0x40];
 };
 
 struct mlx5_ifc_trc_lock_reg_bits {
 	u8         reserved_0[0x1f];
 	u8         lock[0x1];
 
 	u8         reserved_1[0x60];
 };
 
 struct mlx5_ifc_trc_filter_reg_bits {
 	u8         status[0x1];
 	u8         reserved_0[0xf];
 	u8         filter_index[0x10];
 
 	u8         reserved_1[0x20];
 
 	u8         filter_val[0x20];
 
 	u8         reserved_2[0x1a0];
 };
 
 struct mlx5_ifc_trc_event_reg_bits {
 	u8         status[0x1];
 	u8         reserved_0[0xf];
 	u8         event_index[0x10];
 
 	u8         reserved_1[0x20];
 
 	u8         event_id[0x20];
 
 	u8         event_selector_val[0x10];
 	u8         event_selector_size[0x10];
 
 	u8         reserved_2[0x180];
 };
 
 struct mlx5_ifc_trc_conf_reg_bits {
 	u8         limit_en[0x1];
 	u8         reserved_0[0x3];
 	u8         dump_mode[0x4];
 	u8         reserved_1[0x15];
 	u8         state[0x3];
 
 	u8         reserved_2[0x20];
 
 	u8         limit_event_index[0x20];
 
 	u8         mkey[0x20];
 
 	u8         fifo_ready_ev_num[0x20];
 
 	u8         reserved_3[0x160];
 };
 
 struct mlx5_ifc_trc_cap_reg_bits {
 	u8         reserved_0[0x18];
 	u8         dump_mode[0x8];
 
 	u8         reserved_1[0x20];
 
 	u8         num_of_events[0x10];
 	u8         num_of_filters[0x10];
 
 	u8         fifo_size[0x20];
 
 	u8         tlb_size[0x10];
 	u8         event_size[0x10];
 
 	u8         reserved_2[0x160];
 };
 
 struct mlx5_ifc_set_node_in_bits {
 	u8         node_description[64][0x8];
 };
 
 struct mlx5_ifc_register_power_settings_bits {
 	u8         reserved_0[0x18];
 	u8         power_settings_level[0x8];
 
 	u8         reserved_1[0x60];
 };
 
 struct mlx5_ifc_register_host_endianess_bits {
 	u8         he[0x1];
 	u8         reserved_0[0x1f];
 
 	u8         reserved_1[0x60];
 };
 
 struct mlx5_ifc_register_diag_buffer_ctrl_bits {
 	u8         physical_address[0x40];
 };
 
 struct mlx5_ifc_qtct_reg_bits {
 	u8         operation_type[0x2];
 	u8         cap_local_admin[0x1];
 	u8         cap_remote_admin[0x1];
 	u8         reserved_0[0x4];
 	u8         port_number[0x8];
 	u8         reserved_1[0xd];
 	u8         prio[0x3];
 
 	u8         reserved_2[0x1d];
 	u8         tclass[0x3];
 };
 
 struct mlx5_ifc_qpdp_reg_bits {
 	u8         reserved_0[0x8];
 	u8         port_number[0x8];
 	u8         reserved_1[0x10];
 
 	u8         reserved_2[0x1d];
 	u8         pprio[0x3];
 };
 
 struct mlx5_ifc_port_info_ro_fields_param_bits {
 	u8         reserved_0[0x8];
 	u8         port[0x8];
 	u8         max_gid[0x10];
 
 	u8         reserved_1[0x20];
 
 	u8         port_guid[0x40];
 };
 
 struct mlx5_ifc_nvqc_reg_bits {
 	u8         type[0x20];
 
 	u8         reserved_0[0x18];
 	u8         version[0x4];
 	u8         reserved_1[0x2];
 	u8         support_wr[0x1];
 	u8         support_rd[0x1];
 };
 
 struct mlx5_ifc_nvia_reg_bits {
 	u8         reserved_0[0x1d];
 	u8         target[0x3];
 
 	u8         reserved_1[0x20];
 };
 
 struct mlx5_ifc_nvdi_reg_bits {
 	struct mlx5_ifc_config_item_bits configuration_item_header;
 };
 
 struct mlx5_ifc_nvda_reg_bits {
 	struct mlx5_ifc_config_item_bits configuration_item_header;
 
 	u8         configuration_item_data[0x20];
 };
 
 struct mlx5_ifc_node_info_ro_fields_param_bits {
 	u8         system_image_guid[0x40];
 
 	u8         reserved_0[0x40];
 
 	u8         node_guid[0x40];
 
 	u8         reserved_1[0x10];
 	u8         max_pkey[0x10];
 
 	u8         reserved_2[0x20];
 };
 
 struct mlx5_ifc_ets_tcn_config_reg_bits {
 	u8         g[0x1];
 	u8         b[0x1];
 	u8         r[0x1];
 	u8         reserved_0[0x9];
 	u8         group[0x4];
 	u8         reserved_1[0x9];
 	u8         bw_allocation[0x7];
 
 	u8         reserved_2[0xc];
 	u8         max_bw_units[0x4];
 	u8         reserved_3[0x8];
 	u8         max_bw_value[0x8];
 };
 
 struct mlx5_ifc_ets_global_config_reg_bits {
 	u8         reserved_0[0x2];
 	u8         r[0x1];
 	u8         reserved_1[0x1d];
 
 	u8         reserved_2[0xc];
 	u8         max_bw_units[0x4];
 	u8         reserved_3[0x8];
 	u8         max_bw_value[0x8];
 };
 
 struct mlx5_ifc_qetc_reg_bits {
 	u8                                         reserved_at_0[0x8];
 	u8                                         port_number[0x8];
 	u8                                         reserved_at_10[0x30];
 
 	struct mlx5_ifc_ets_tcn_config_reg_bits    tc_configuration[0x8];
 	struct mlx5_ifc_ets_global_config_reg_bits global_configuration;
 };
 
 struct mlx5_ifc_nodnic_mac_filters_bits {
 	struct mlx5_ifc_mac_address_layout_bits mac_filter0;
 
 	struct mlx5_ifc_mac_address_layout_bits mac_filter1;
 
 	struct mlx5_ifc_mac_address_layout_bits mac_filter2;
 
 	struct mlx5_ifc_mac_address_layout_bits mac_filter3;
 
 	struct mlx5_ifc_mac_address_layout_bits mac_filter4;
 
 	u8         reserved_0[0xc0];
 };
 
 struct mlx5_ifc_nodnic_gid_filters_bits {
 	u8         mgid_filter0[16][0x8];
 
 	u8         mgid_filter1[16][0x8];
 
 	u8         mgid_filter2[16][0x8];
 
 	u8         mgid_filter3[16][0x8];
 };
 
 enum {
 	MLX5_NODNIC_CONFIG_REG_NUM_PORTS_SINGLE_PORT  = 0x0,
 	MLX5_NODNIC_CONFIG_REG_NUM_PORTS_DUAL_PORT    = 0x1,
 };
 
 enum {
 	MLX5_NODNIC_CONFIG_REG_CQE_FORMAT_LEGACY_CQE  = 0x0,
 	MLX5_NODNIC_CONFIG_REG_CQE_FORMAT_NEW_CQE     = 0x1,
 };
 
 struct mlx5_ifc_nodnic_config_reg_bits {
 	u8         no_dram_nic_revision[0x8];
 	u8         hardware_format[0x8];
 	u8         support_receive_filter[0x1];
 	u8         support_promisc_filter[0x1];
 	u8         support_promisc_multicast_filter[0x1];
 	u8         reserved_0[0x2];
 	u8         log_working_buffer_size[0x3];
 	u8         log_pkey_table_size[0x4];
 	u8         reserved_1[0x3];
 	u8         num_ports[0x1];
 
 	u8         reserved_2[0x2];
 	u8         log_max_ring_size[0x6];
 	u8         reserved_3[0x18];
 
 	u8         lkey[0x20];
 
 	u8         cqe_format[0x4];
 	u8         reserved_4[0x1c];
 
 	u8         node_guid[0x40];
 
 	u8         reserved_5[0x740];
 
 	struct mlx5_ifc_nodnic_port_config_reg_bits port1_settings;
 
 	struct mlx5_ifc_nodnic_port_config_reg_bits port2_settings;
 };
 
 struct mlx5_ifc_vlan_layout_bits {
 	u8         reserved_0[0x14];
 	u8         vlan[0xc];
 
 	u8         reserved_1[0x20];
 };
 
 struct mlx5_ifc_umr_pointer_desc_argument_bits {
 	u8         reserved_0[0x20];
 
 	u8         mkey[0x20];
 
 	u8         addressh_63_32[0x20];
 
 	u8         addressl_31_0[0x20];
 };
 
 struct mlx5_ifc_ud_adrs_vector_bits {
 	u8         dc_key[0x40];
 
 	u8         ext[0x1];
 	u8         reserved_0[0x7];
 	u8         destination_qp_dct[0x18];
 
 	u8         static_rate[0x4];
 	u8         sl_eth_prio[0x4];
 	u8         fl[0x1];
 	u8         mlid[0x7];
 	u8         rlid_udp_sport[0x10];
 
 	u8         reserved_1[0x20];
 
 	u8         rmac_47_16[0x20];
 
 	u8         rmac_15_0[0x10];
 	u8         tclass[0x8];
 	u8         hop_limit[0x8];
 
 	u8         reserved_2[0x1];
 	u8         grh[0x1];
 	u8         reserved_3[0x2];
 	u8         src_addr_index[0x8];
 	u8         flow_label[0x14];
 
 	u8         rgid_rip[16][0x8];
 };
 
 struct mlx5_ifc_port_module_event_bits {
 	u8         reserved_0[0x8];
 	u8         module[0x8];
 	u8         reserved_1[0xc];
 	u8         module_status[0x4];
 
 	u8         reserved_2[0x14];
 	u8         error_type[0x4];
 	u8         reserved_3[0x8];
 
 	u8         reserved_4[0xa0];
 };
 
 struct mlx5_ifc_icmd_control_bits {
 	u8         opcode[0x10];
 	u8         status[0x8];
 	u8         reserved_0[0x7];
 	u8         busy[0x1];
 };
 
 struct mlx5_ifc_eqe_bits {
 	u8         reserved_0[0x8];
 	u8         event_type[0x8];
 	u8         reserved_1[0x8];
 	u8         event_sub_type[0x8];
 
 	u8         reserved_2[0xe0];
 
 	union mlx5_ifc_event_auto_bits event_data;
 
 	u8         reserved_3[0x10];
 	u8         signature[0x8];
 	u8         reserved_4[0x7];
 	u8         owner[0x1];
 };
 
 enum {
 	MLX5_CMD_QUEUE_ENTRY_TYPE_PCIE_CMD_IF_TRANSPORT  = 0x7,
 };
 
 struct mlx5_ifc_cmd_queue_entry_bits {
 	u8         type[0x8];
 	u8         reserved_0[0x18];
 
 	u8         input_length[0x20];
 
 	u8         input_mailbox_pointer_63_32[0x20];
 
 	u8         input_mailbox_pointer_31_9[0x17];
 	u8         reserved_1[0x9];
 
 	u8         command_input_inline_data[16][0x8];
 
 	u8         command_output_inline_data[16][0x8];
 
 	u8         output_mailbox_pointer_63_32[0x20];
 
 	u8         output_mailbox_pointer_31_9[0x17];
 	u8         reserved_2[0x9];
 
 	u8         output_length[0x20];
 
 	u8         token[0x8];
 	u8         signature[0x8];
 	u8         reserved_3[0x8];
 	u8         status[0x7];
 	u8         ownership[0x1];
 };
 
 struct mlx5_ifc_cmd_out_bits {
 	u8         status[0x8];
 	u8         reserved_0[0x18];
 
 	u8         syndrome[0x20];
 
 	u8         command_output[0x20];
 };
 
 struct mlx5_ifc_cmd_in_bits {
 	u8         opcode[0x10];
 	u8         reserved_0[0x10];
 
 	u8         reserved_1[0x10];
 	u8         op_mod[0x10];
 
 	u8         command[0][0x20];
 };
 
 struct mlx5_ifc_cmd_if_box_bits {
 	u8         mailbox_data[512][0x8];
 
 	u8         reserved_0[0x180];
 
 	u8         next_pointer_63_32[0x20];
 
 	u8         next_pointer_31_10[0x16];
 	u8         reserved_1[0xa];
 
 	u8         block_number[0x20];
 
 	u8         reserved_2[0x8];
 	u8         token[0x8];
 	u8         ctrl_signature[0x8];
 	u8         signature[0x8];
 };
 
 struct mlx5_ifc_mtt_bits {
 	u8         ptag_63_32[0x20];
 
 	u8         ptag_31_8[0x18];
 	u8         reserved_0[0x6];
 	u8         wr_en[0x1];
 	u8         rd_en[0x1];
 };
 
 /* Vendor Specific Capabilities, VSC */
 enum {
 	MLX5_VSC_DOMAIN_ICMD			= 0x1,
 	MLX5_VSC_DOMAIN_PROTECTED_CRSPACE	= 0x6,
 	MLX5_VSC_DOMAIN_SEMAPHORES		= 0xA,
 };
 
 struct mlx5_ifc_vendor_specific_cap_bits {
 	u8         type[0x8];
 	u8         length[0x8];
 	u8         next_pointer[0x8];
 	u8         capability_id[0x8];
 
 	u8         status[0x3];
 	u8         reserved_0[0xd];
 	u8         space[0x10];
 
 	u8         counter[0x20];
 
 	u8         semaphore[0x20];
 
 	u8         flag[0x1];
 	u8         reserved_1[0x1];
 	u8         address[0x1e];
 
 	u8         data[0x20];
 };
 
 enum {
 	MLX5_INITIAL_SEG_NIC_INTERFACE_FULL_DRIVER  = 0x0,
 	MLX5_INITIAL_SEG_NIC_INTERFACE_DISABLED     = 0x1,
 	MLX5_INITIAL_SEG_NIC_INTERFACE_NO_DRAM_NIC  = 0x2,
 };
 
 enum {
 	MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_FULL_DRIVER  = 0x0,
 	MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_DISABLED     = 0x1,
 	MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_NO_DRAM_NIC  = 0x2,
 };
 
 enum {
 	MLX5_HEALTH_SYNDR_FW_ERR                                      = 0x1,
 	MLX5_HEALTH_SYNDR_IRISC_ERR                                   = 0x7,
 	MLX5_HEALTH_SYNDR_HW_UNRECOVERABLE_ERR                        = 0x8,
 	MLX5_HEALTH_SYNDR_CRC_ERR                                     = 0x9,
 	MLX5_HEALTH_SYNDR_FETCH_PCI_ERR                               = 0xa,
 	MLX5_HEALTH_SYNDR_HW_FTL_ERR                                  = 0xb,
 	MLX5_HEALTH_SYNDR_ASYNC_EQ_OVERRUN_ERR                        = 0xc,
 	MLX5_HEALTH_SYNDR_EQ_ERR                                      = 0xd,
 	MLX5_HEALTH_SYNDR_EQ_INV                                      = 0xe,
 	MLX5_HEALTH_SYNDR_FFSER_ERR                                   = 0xf,
 	MLX5_HEALTH_SYNDR_HIGH_TEMP                                   = 0x10,
 };
 
 struct mlx5_ifc_initial_seg_bits {
 	u8         fw_rev_minor[0x10];
 	u8         fw_rev_major[0x10];
 
 	u8         cmd_interface_rev[0x10];
 	u8         fw_rev_subminor[0x10];
 
 	u8         reserved_0[0x40];
 
 	u8         cmdq_phy_addr_63_32[0x20];
 
 	u8         cmdq_phy_addr_31_12[0x14];
 	u8         reserved_1[0x2];
 	u8         nic_interface[0x2];
 	u8         log_cmdq_size[0x4];
 	u8         log_cmdq_stride[0x4];
 
 	u8         command_doorbell_vector[0x20];
 
 	u8         reserved_2[0xf00];
 
 	u8         initializing[0x1];
 	u8         reserved_3[0x4];
 	u8         nic_interface_supported[0x3];
 	u8         reserved_4[0x18];
 
 	struct mlx5_ifc_health_buffer_bits health_buffer;
 
 	u8         no_dram_nic_offset[0x20];
 
 	u8         reserved_5[0x6de0];
 
 	u8         internal_timer_h[0x20];
 
 	u8         internal_timer_l[0x20];
 
 	u8         reserved_6[0x20];
 
 	u8         reserved_7[0x1f];
 	u8         clear_int[0x1];
 
 	u8         health_syndrome[0x8];
 	u8         health_counter[0x18];
 
 	u8         reserved_8[0x17fc0];
 };
 
 union mlx5_ifc_icmd_interface_document_bits {
 	struct mlx5_ifc_fw_version_bits fw_version;
 	struct mlx5_ifc_icmd_access_reg_in_bits icmd_access_reg_in;
 	struct mlx5_ifc_icmd_access_reg_out_bits icmd_access_reg_out;
 	struct mlx5_ifc_icmd_init_ocsd_in_bits icmd_init_ocsd_in;
 	struct mlx5_ifc_icmd_ocbb_init_in_bits icmd_ocbb_init_in;
 	struct mlx5_ifc_icmd_ocbb_query_etoc_stats_out_bits icmd_ocbb_query_etoc_stats_out;
 	struct mlx5_ifc_icmd_ocbb_query_header_stats_out_bits icmd_ocbb_query_header_stats_out;
 	struct mlx5_ifc_icmd_query_cap_general_bits icmd_query_cap_general;
 	struct mlx5_ifc_icmd_query_cap_in_bits icmd_query_cap_in;
 	struct mlx5_ifc_icmd_query_fw_info_out_bits icmd_query_fw_info_out;
 	struct mlx5_ifc_icmd_query_virtual_mac_out_bits icmd_query_virtual_mac_out;
 	struct mlx5_ifc_icmd_set_virtual_mac_in_bits icmd_set_virtual_mac_in;
 	struct mlx5_ifc_icmd_set_wol_rol_in_bits icmd_set_wol_rol_in;
 	struct mlx5_ifc_icmd_set_wol_rol_out_bits icmd_set_wol_rol_out;
 	u8         reserved_0[0x42c0];
 };
 
 union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits {
 	struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout;
 	struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout;
 	struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout;
 	struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout;
 	struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout;
 	struct mlx5_ifc_eth_discard_cntrs_grp_bits eth_discard_cntrs_grp;
 	struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout;
 	struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs;
 	struct mlx5_ifc_phys_layer_statistical_cntrs_bits phys_layer_statistical_cntrs;
 	struct mlx5_ifc_infiniband_port_cntrs_bits infiniband_port_cntrs;
 	u8         reserved_0[0x7c0];
 };
 
 struct mlx5_ifc_ppcnt_reg_bits {
 	u8         swid[0x8];
 	u8         local_port[0x8];
 	u8         pnat[0x2];
 	u8         reserved_0[0x8];
 	u8         grp[0x6];
 
 	u8         clr[0x1];
 	u8         reserved_1[0x1c];
 	u8         prio_tc[0x3];
 
 	union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits counter_set;
 };
 
 struct mlx5_ifc_pcie_performance_counters_data_layout_bits {
 	u8         life_time_counter_high[0x20];
 
 	u8         life_time_counter_low[0x20];
 
 	u8         rx_errors[0x20];
 
 	u8         tx_errors[0x20];
 
 	u8         l0_to_recovery_eieos[0x20];
 
 	u8         l0_to_recovery_ts[0x20];
 
 	u8         l0_to_recovery_framing[0x20];
 
 	u8         l0_to_recovery_retrain[0x20];
 
 	u8         crc_error_dllp[0x20];
 
 	u8         crc_error_tlp[0x20];
 
 	u8         reserved_0[0x680];
 };
 
 struct mlx5_ifc_pcie_timers_and_states_data_layout_bits {
 	u8         life_time_counter_high[0x20];
 
 	u8         life_time_counter_low[0x20];
 
 	u8         time_to_boot_image_start[0x20];
 
 	u8         time_to_link_image[0x20];
 
 	u8         calibration_time[0x20];
 
 	u8         time_to_first_perst[0x20];
 
 	u8         time_to_detect_state[0x20];
 
 	u8         time_to_l0[0x20];
 
 	u8         time_to_crs_en[0x20];
 
 	u8         time_to_plastic_image_start[0x20];
 
 	u8         time_to_iron_image_start[0x20];
 
 	u8         perst_handler[0x20];
 
 	u8         times_in_l1[0x20];
 
 	u8         times_in_l23[0x20];
 
 	u8         dl_down[0x20];
 
 	u8         config_cycle1usec[0x20];
 
 	u8         config_cycle2to7usec[0x20];
 
 	u8         config_cycle8to15usec[0x20];
 
 	u8         config_cycle16to63usec[0x20];
 
 	u8         config_cycle64usec[0x20];
 
 	u8         correctable_err_msg_sent[0x20];
 
 	u8         non_fatal_err_msg_sent[0x20];
 
 	u8         fatal_err_msg_sent[0x20];
 
 	u8         reserved_0[0x4e0];
 };
 
 struct mlx5_ifc_pcie_lanes_counters_data_layout_bits {
 	u8         life_time_counter_high[0x20];
 
 	u8         life_time_counter_low[0x20];
 
 	u8         error_counter_lane0[0x20];
 
 	u8         error_counter_lane1[0x20];
 
 	u8         error_counter_lane2[0x20];
 
 	u8         error_counter_lane3[0x20];
 
 	u8         error_counter_lane4[0x20];
 
 	u8         error_counter_lane5[0x20];
 
 	u8         error_counter_lane6[0x20];
 
 	u8         error_counter_lane7[0x20];
 
 	u8         error_counter_lane8[0x20];
 
 	u8         error_counter_lane9[0x20];
 
 	u8         error_counter_lane10[0x20];
 
 	u8         error_counter_lane11[0x20];
 
 	u8         error_counter_lane12[0x20];
 
 	u8         error_counter_lane13[0x20];
 
 	u8         error_counter_lane14[0x20];
 
 	u8         error_counter_lane15[0x20];
 
 	u8         reserved_0[0x580];
 };
 
 union mlx5_ifc_mpcnt_cntrs_grp_data_layout_bits {
 	struct mlx5_ifc_pcie_performance_counters_data_layout_bits pcie_performance_counters_data_layout;
 	struct mlx5_ifc_pcie_timers_and_states_data_layout_bits pcie_timers_and_states_data_layout;
 	struct mlx5_ifc_pcie_lanes_counters_data_layout_bits pcie_lanes_counters_data_layout;
 	u8         reserved_0[0xf8];
 };
 
 struct mlx5_ifc_mpcnt_reg_bits {
 	u8         reserved_0[0x8];
 	u8         pcie_index[0x8];
 	u8         reserved_1[0xa];
 	u8         grp[0x6];
 
 	u8         clr[0x1];
 	u8         reserved_2[0x1f];
 
 	union mlx5_ifc_mpcnt_cntrs_grp_data_layout_bits counter_set;
 };
 
 union mlx5_ifc_ports_control_registers_document_bits {
 	struct mlx5_ifc_ib_portcntrs_attribute_grp_data_bits ib_portcntrs_attribute_grp_data;
 	struct mlx5_ifc_bufferx_reg_bits bufferx_reg;
 	struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout;
 	struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout;
 	struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout;
 	struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout;
 	struct mlx5_ifc_eth_discard_cntrs_grp_bits eth_discard_cntrs_grp;
 	struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout;
 	struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout;
 	struct mlx5_ifc_eth_per_traffic_class_cong_layout_bits eth_per_traffic_class_cong_layout;
 	struct mlx5_ifc_eth_per_traffic_class_layout_bits eth_per_traffic_class_layout;
 	struct mlx5_ifc_lane_2_module_mapping_bits lane_2_module_mapping;
 	struct mlx5_ifc_link_level_retrans_cntr_grp_date_bits link_level_retrans_cntr_grp_date;
 	struct mlx5_ifc_pamp_reg_bits pamp_reg;
 	struct mlx5_ifc_paos_reg_bits paos_reg;
 	struct mlx5_ifc_pbmc_reg_bits pbmc_reg;
 	struct mlx5_ifc_pcap_reg_bits pcap_reg;
 	struct mlx5_ifc_peir_reg_bits peir_reg;
 	struct mlx5_ifc_pelc_reg_bits pelc_reg;
 	struct mlx5_ifc_pfcc_reg_bits pfcc_reg;
 	struct mlx5_ifc_phbr_binding_reg_bits phbr_binding_reg;
 	struct mlx5_ifc_phbr_for_port_tclass_reg_bits phbr_for_port_tclass_reg;
 	struct mlx5_ifc_phbr_for_prio_reg_bits phbr_for_prio_reg;
 	struct mlx5_ifc_phrr_reg_bits phrr_reg;
 	struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs;
 	struct mlx5_ifc_pifr_reg_bits pifr_reg;
 	struct mlx5_ifc_pipg_reg_bits pipg_reg;
 	struct mlx5_ifc_plbf_reg_bits plbf_reg;
 	struct mlx5_ifc_plib_reg_bits plib_reg;
 	struct mlx5_ifc_pll_status_data_bits pll_status_data;
 	struct mlx5_ifc_plpc_reg_bits plpc_reg;
 	struct mlx5_ifc_pmaos_reg_bits pmaos_reg;
 	struct mlx5_ifc_pmlp_reg_bits pmlp_reg;
 	struct mlx5_ifc_pmlpn_reg_bits pmlpn_reg;
 	struct mlx5_ifc_pmpc_reg_bits pmpc_reg;
 	struct mlx5_ifc_pmpe_reg_bits pmpe_reg;
 	struct mlx5_ifc_pmpr_reg_bits pmpr_reg;
 	struct mlx5_ifc_pmtu_reg_bits pmtu_reg;
 	struct mlx5_ifc_ppad_reg_bits ppad_reg;
 	struct mlx5_ifc_ppcnt_reg_bits ppcnt_reg;
 	struct mlx5_ifc_ppll_reg_bits ppll_reg;
 	struct mlx5_ifc_pplm_reg_bits pplm_reg;
 	struct mlx5_ifc_pplr_reg_bits pplr_reg;
 	struct mlx5_ifc_ppsc_reg_bits ppsc_reg;
 	struct mlx5_ifc_pspa_reg_bits pspa_reg;
 	struct mlx5_ifc_ptas_reg_bits ptas_reg;
 	struct mlx5_ifc_ptys_reg_bits ptys_reg;
 	struct mlx5_ifc_pude_reg_bits pude_reg;
 	struct mlx5_ifc_pvlc_reg_bits pvlc_reg;
 	struct mlx5_ifc_slrg_reg_bits slrg_reg;
 	struct mlx5_ifc_slrp_reg_bits slrp_reg;
 	struct mlx5_ifc_sltp_reg_bits sltp_reg;
 	u8         reserved_0[0x7880];
 };
 
 union mlx5_ifc_debug_enhancements_document_bits {
 	struct mlx5_ifc_health_buffer_bits health_buffer;
 	u8         reserved_0[0x200];
 };
 
 union mlx5_ifc_no_dram_nic_document_bits {
 	struct mlx5_ifc_nodnic_config_reg_bits nodnic_config_reg;
 	struct mlx5_ifc_nodnic_cq_arming_word_bits nodnic_cq_arming_word;
 	struct mlx5_ifc_nodnic_event_word_bits nodnic_event_word;
 	struct mlx5_ifc_nodnic_gid_filters_bits nodnic_gid_filters;
 	struct mlx5_ifc_nodnic_mac_filters_bits nodnic_mac_filters;
 	struct mlx5_ifc_nodnic_port_config_reg_bits nodnic_port_config_reg;
 	struct mlx5_ifc_nodnic_ring_config_reg_bits nodnic_ring_config_reg;
 	struct mlx5_ifc_nodnic_ring_doorbell_bits nodnic_ring_doorbell;
 	u8         reserved_0[0x3160];
 };
 
 union mlx5_ifc_uplink_pci_interface_document_bits {
 	struct mlx5_ifc_initial_seg_bits initial_seg;
 	struct mlx5_ifc_vendor_specific_cap_bits vendor_specific_cap;
 	u8         reserved_0[0x20120];
 };
 
 struct mlx5_ifc_qpdpm_dscp_reg_bits {
 	u8         e[0x1];
 	u8         reserved_at_01[0x0b];
 	u8         prio[0x04];
 };
 
 struct mlx5_ifc_qpdpm_reg_bits {
 	u8                                     reserved_at_0[0x8];
 	u8                                     local_port[0x8];
 	u8                                     reserved_at_10[0x10];
 	struct mlx5_ifc_qpdpm_dscp_reg_bits    dscp[64];
 };
 
 struct mlx5_ifc_qpts_reg_bits {
 	u8         reserved_at_0[0x8];
 	u8         local_port[0x8];
 	u8         reserved_at_10[0x2d];
 	u8         trust_state[0x3];
 };
 
 #endif /* MLX5_IFC_H */
Index: head/sys/dev/mlx5/mlx5io.h
===================================================================
--- head/sys/dev/mlx5/mlx5io.h	(revision 341574)
+++ head/sys/dev/mlx5/mlx5io.h	(revision 341575)
@@ -1,112 +1,134 @@
 /*-
  * Copyright (c) 2018, Mellanox Technologies, Ltd.  All rights reserved.
  *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions
  * are met:
  * 1. Redistributions of source code must retain the above copyright
  *    notice, this list of conditions and the following disclaimer.
  * 2. Redistributions in binary form must reproduce the above copyright
  *    notice, this list of conditions and the following disclaimer in the
  *    documentation and/or other materials provided with the distribution.
  *
  * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS `AS IS' AND
  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  * ARE DISCLAIMED.  IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE
  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  * SUCH DAMAGE.
  *
  * $FreeBSD$
  */
 
 #ifndef _DEV_MLX5_MLX5IO_H_
 #define _DEV_MLX5_MLX5IO_H_
 
 #include <sys/ioccom.h>
 
 struct mlx5_fwdump_reg {
 	uint32_t addr;
 	uint32_t val;
 };
 
 struct mlx5_fwdump_addr {
 	uint32_t domain;
 	uint8_t bus;
 	uint8_t slot;
 	uint8_t func;
 };
 
 struct mlx5_fwdump_get {
 	struct mlx5_fwdump_addr devaddr;
 	struct mlx5_fwdump_reg *buf;
 	size_t reg_cnt;
 	size_t reg_filled; /* out */
 };
 
 #define	MLX5_FWDUMP_GET		_IOWR('m', 1, struct mlx5_fwdump_get)
 #define	MLX5_FWDUMP_RESET	_IOW('m', 2, struct mlx5_fwdump_addr)
 #define	MLX5_FWDUMP_FORCE	_IOW('m', 3, struct mlx5_fwdump_addr)
 
 #ifndef _KERNEL
 #define	MLX5_DEV_PATH	_PATH_DEV"mlx5ctl"
 #endif
 
 enum mlx5_fpga_id {
 	MLX5_FPGA_NEWTON = 0,
 	MLX5_FPGA_EDISON = 1,
 	MLX5_FPGA_MORSE = 2,
 	MLX5_FPGA_MORSEQ = 3,
 };
 
 enum mlx5_fpga_image {
 	MLX5_FPGA_IMAGE_USER = 0,
 	MLX5_FPGA_IMAGE_FACTORY = 1,
 	MLX5_FPGA_IMAGE_MAX = MLX5_FPGA_IMAGE_FACTORY,
 	MLX5_FPGA_IMAGE_FACTORY_FAILOVER = 2,
 };
 
 enum mlx5_fpga_status {
 	MLX5_FPGA_STATUS_SUCCESS = 0,
 	MLX5_FPGA_STATUS_FAILURE = 1,
 	MLX5_FPGA_STATUS_IN_PROGRESS = 2,
 	MLX5_FPGA_STATUS_DISCONNECTED = 3,
 };
 
 struct mlx5_fpga_query {
 	enum mlx5_fpga_image admin_image;
 	enum mlx5_fpga_image oper_image;
 	enum mlx5_fpga_status image_status;
 };
 
+enum mlx5_fpga_tee {
+	MLX5_FPGA_TEE_DISABLE = 0,
+	MLX5_FPGA_TEE_GENERATE_EVENT = 1,
+	MLX5_FPGA_TEE_GENERATE_SINGLE_EVENT = 2,
+};
+
 /**
  * enum mlx5_fpga_access_type - Enumerated the different methods possible for
  * accessing the device memory address space
  */
 enum mlx5_fpga_access_type {
 	/** Use the slow CX-FPGA I2C bus*/
 	MLX5_FPGA_ACCESS_TYPE_I2C = 0x0,
 	/** Use the fast 'shell QP' */
 	MLX5_FPGA_ACCESS_TYPE_RDMA,
 	/** Use the fastest available method */
 	MLX5_FPGA_ACCESS_TYPE_DONTCARE,
 	MLX5_FPGA_ACCESS_TYPE_MAX = MLX5_FPGA_ACCESS_TYPE_DONTCARE,
 };
 
+#define MLX5_FPGA_INTERNAL_SENSORS_LOW 63
+#define MLX5_FPGA_INTERNAL_SENSORS_HIGH 63
+
+struct mlx5_fpga_temperature {
+	uint32_t temperature;
+	uint32_t index;
+	uint32_t tee;
+	uint32_t max_temperature;
+	uint32_t temperature_threshold_hi;
+	uint32_t temperature_threshold_lo;
+	uint32_t mte;
+	uint32_t mtr;
+	char sensor_name[16];
+};
+
 #define	MLX5_FPGA_CAP_ARR_SZ 0x40
 
 #define	MLX5_FPGA_ACCESS_TYPE	_IOWINT('m', 0x80)
 #define	MLX5_FPGA_LOAD		_IOWINT('m', 0x81)
 #define	MLX5_FPGA_RESET		_IO('m', 0x82)
 #define	MLX5_FPGA_IMAGE_SEL	_IOWINT('m', 0x83)
 #define	MLX5_FPGA_QUERY		_IOR('m', 0x84, struct mlx5_fpga_query)
 #define	MLX5_FPGA_CAP		_IOR('m', 0x85, u32[MLX5_FPGA_CAP_ARR_SZ])
+#define	MLX5_FPGA_TEMPERATURE	_IOWR('m', 0x86, struct mlx5_fpga_temperature)
 
 #define	MLX5_FPGA_TOOLS_NAME_SUFFIX	"_mlx5_fpga_tools"
 
 #endif