Index: head/sys/arm64/conf/GENERIC =================================================================== --- head/sys/arm64/conf/GENERIC (revision 341381) +++ head/sys/arm64/conf/GENERIC (revision 341382) @@ -1,286 +1,287 @@ # # GENERIC -- Generic kernel configuration file for FreeBSD/arm64 # # For more information on this file, please read the config(5) manual page, # and/or the handbook section on Kernel Configuration Files: # # https://www.FreeBSD.org/doc/en_US.ISO8859-1/books/handbook/kernelconfig-config.html # # The handbook is also available locally in /usr/share/doc/handbook # if you've installed the doc distribution, otherwise always see the # FreeBSD World Wide Web server (https://www.FreeBSD.org/) for the # latest information. # # An exhaustive list of options and more detailed explanations of the # device lines is also present in the ../../conf/NOTES and NOTES files. # If you are in doubt as to the purpose or necessity of a line, check first # in NOTES. # # $FreeBSD$ cpu ARM64 ident GENERIC makeoptions DEBUG=-g # Build kernel with gdb(1) debug symbols makeoptions WITH_CTF=1 # Run ctfconvert(1) for DTrace support options SCHED_ULE # ULE scheduler options PREEMPTION # Enable kernel thread preemption options VIMAGE # Subsystem virtualization, e.g. VNET options INET # InterNETworking options INET6 # IPv6 communications protocols options IPSEC # IP (v4/v6) security options IPSEC_SUPPORT # Allow kldload of ipsec and tcpmd5 options TCP_HHOOK # hhook(9) framework for TCP options TCP_OFFLOAD # TCP offload options TCP_RFC7413 # TCP Fast Open options SCTP # Stream Control Transmission Protocol options FFS # Berkeley Fast Filesystem options SOFTUPDATES # Enable FFS soft updates support options UFS_ACL # Support for access control lists options UFS_DIRHASH # Improve performance on big directories options UFS_GJOURNAL # Enable gjournal-based UFS journaling options QUOTA # Enable disk quotas for UFS options MD_ROOT # MD is a potential root device options NFSCL # Network Filesystem Client options NFSD # Network Filesystem Server options NFSLOCKD # Network Lock Manager options NFS_ROOT # NFS usable as /, requires NFSCL options MSDOSFS # MSDOS Filesystem options CD9660 # ISO 9660 Filesystem options PROCFS # Process filesystem (requires PSEUDOFS) options PSEUDOFS # Pseudo-filesystem framework options GEOM_RAID # Soft RAID functionality. options GEOM_LABEL # Provides labelization options COMPAT_FREEBSD32 # Incomplete, but used by cloudabi32.ko. options COMPAT_FREEBSD11 # Compatible with FreeBSD11 options SCSI_DELAY=5000 # Delay (in ms) before probing SCSI options KTRACE # ktrace(1) support options STACK # stack(9) support options SYSVSHM # SYSV-style shared memory options SYSVMSG # SYSV-style message queues options SYSVSEM # SYSV-style semaphores options _KPOSIX_PRIORITY_SCHEDULING # POSIX P1003_1B real-time extensions options PRINTF_BUFR_SIZE=128 # Prevent printf output being interspersed. options KBD_INSTALL_CDEV # install a CDEV entry in /dev options HWPMC_HOOKS # Necessary kernel hooks for hwpmc(4) options AUDIT # Security event auditing options CAPABILITY_MODE # Capsicum capability mode options CAPABILITIES # Capsicum capabilities options MAC # TrustedBSD MAC Framework options KDTRACE_FRAME # Ensure frames are compiled in options KDTRACE_HOOKS # Kernel DTrace hooks options VFP # Floating-point support options RACCT # Resource accounting framework options RACCT_DEFAULT_TO_DISABLED # Set kern.racct.enable=0 by default options RCTL # Resource limits options SMP options INTRNG # Debugging support. Always need this: options KDB # Enable kernel debugger support. options KDB_TRACE # Print a stack trace for a panic. # For full debugger support use (turn off in stable branch): options DDB # Support DDB. #options GDB # Support remote GDB. options DEADLKRES # Enable the deadlock resolver options INVARIANTS # Enable calls of extra sanity checking options INVARIANT_SUPPORT # Extra sanity checks of internal structures, required by INVARIANTS options WITNESS # Enable checks to detect deadlocks and cycles options WITNESS_SKIPSPIN # Don't run witness on spinlocks for speed options MALLOC_DEBUG_MAXZONES=8 # Separate malloc(9) zones options ALT_BREAK_TO_DEBUGGER # Enter debugger on keyboard escape sequence options USB_DEBUG # enable debug msgs options VERBOSE_SYSINIT=0 # Support debug.verbose_sysinit, off by default # Warning: KUBSAN can result in a kernel too large for loader to load #options KUBSAN # Kernel Undefined Behavior Sanitizer # Kernel dump features. options EKCD # Support for encrypted kernel dumps options GZIO # gzip-compressed kernel and user dumps options ZSTDIO # zstd-compressed kernel and user dumps options NETDUMP # netdump(4) client support # SoC support options SOC_ALLWINNER_A64 options SOC_ALLWINNER_H5 options SOC_CAVM_THUNDERX options SOC_HISI_HI6220 options SOC_BRCM_BCM2837 options SOC_ROCKCHIP_RK3328 +options SOC_ROCKCHIP_RK3399 options SOC_XILINX_ZYNQ # Timer drivers device a10_timer # Annapurna Alpine drivers device al_ccu # Alpine Cache Coherency Unit device al_nb_service # Alpine North Bridge Service device al_iofic # I/O Fabric Interrupt Controller device al_serdes # Serializer/Deserializer device al_udma # Universal DMA # Qualcomm Snapdragon drivers device qcom_gcc # Global Clock Controller # VirtIO support device virtio device virtio_pci device virtio_mmio device virtio_blk device vtnet # CPU frequency control device cpufreq # Bus drivers device pci device al_pci # Annapurna Alpine PCI-E options PCI_HP # PCI-Express native HotPlug options PCI_IOV # PCI SR-IOV support # Ethernet NICs device mdio device mii device miibus # MII bus support device awg # Allwinner EMAC Gigabit Ethernet device axgbe # AMD Opteron A1100 integrated NIC device em # Intel PRO/1000 Gigabit Ethernet Family device ix # Intel 10Gb Ethernet Family device msk # Marvell/SysKonnect Yukon II Gigabit Ethernet device neta # Marvell Armada 370/38x/XP/3700 NIC device smc # SMSC LAN91C111 device vnic # Cavium ThunderX NIC device al_eth # Annapurna Alpine Ethernet NIC device dwc_rk # Rockchip Designware # Block devices device ahci device scbus device da # ATA/SCSI peripherals device pass # Passthrough device (direct ATA/SCSI access) # MMC/SD/SDIO Card slot support device sdhci device sdhci_xenon # Marvell Xenon SD/MMC controller device aw_mmc # Allwinner SD/MMC controller device mmc # mmc/sd bus device mmcsd # mmc/sd flash cards device dwmmc # Serial (COM) ports device uart # Generic UART driver device uart_msm # Qualcomm MSM UART driver device uart_mu # RPI3 aux port device uart_mvebu # Armada 3700 UART driver device uart_ns8250 # ns8250-type UART driver device uart_snps device pl011 # USB support device aw_ehci # Allwinner EHCI USB interface (USB 2.0) device aw_usbphy # Allwinner USB PHY device dwcotg # DWC OTG controller device ohci # OHCI USB interface device ehci # EHCI USB interface (USB 2.0) device ehci_mv # Marvell EHCI USB interface device xhci # XHCI PCI->USB interface (USB 3.0) device xhci_mv # Marvell XHCI USB interface device usb # USB Bus (required) device ukbd # Keyboard device umass # Disks/Mass storage - Requires scbus and da # USB ethernet support device muge device smcphy device smsc # GPIO device aw_gpio # Allwinner GPIO controller device gpio device gpioled device fdt_pinctrl # I2C device aw_rsb # Allwinner Reduced Serial Bus device bcm2835_bsc # Broadcom BCM283x I2C bus device iicbus device iic device twsi # Allwinner I2C controller device rk_i2c # RockChip I2C controller # Clock and reset controllers device aw_ccu # Allwinner clock controller # Interrupt controllers device aw_nmi # Allwinner NMI support # Real-time clock support device aw_rtc # Allwinner Real-time Clock device mv_rtc # Marvell Real-time Clock # Watchdog controllers device aw_wdog # Allwinner Watchdog # Power management controllers device axp81x # X-Powers AXP81x PMIC device rk805 # RockChip RK805 PMIC # EFUSE device aw_sid # Allwinner Secure ID EFUSE # Thermal sensors device aw_thermal # Allwinner Thermal Sensor Controller # SPI device spibus device bcm2835_spi # Broadcom BCM283x SPI bus # Console device vt device kbdmux device vt_efifb # EVDEV support device evdev # input event device support options EVDEV_SUPPORT # evdev support in legacy drivers device uinput # install /dev/uinput cdev # Pseudo devices. device crypto # core crypto support device loop # Network loopback device random # Entropy device device ether # Ethernet support device vlan # 802.1Q VLAN support device tun # Packet tunnel. device md # Memory "disks" device gif # IPv6 and IPv4 tunneling device firmware # firmware assist module options EFIRT # EFI Runtime Services # EXT_RESOURCES pseudo devices options EXT_RESOURCES device clk device phy device hwreset device nvmem device regulator device syscon device aw_syscon # The `bpf' device enables the Berkeley Packet Filter. # Be aware of the administrative consequences of enabling this! # Note that 'bpf' is required for DHCP. device bpf # Berkeley packet filter # Chip-specific errata options THUNDERX_PASS_1_1_ERRATA options FDT device acpi # DTBs makeoptions MODULES_EXTRA="dtb/allwinner" Index: head/sys/arm64/rockchip/clk/rk3399_cru.c =================================================================== --- head/sys/arm64/rockchip/clk/rk3399_cru.c (nonexistent) +++ head/sys/arm64/rockchip/clk/rk3399_cru.c (revision 341382) @@ -0,0 +1,1535 @@ +/*- + * SPDX-License-Identifier: BSD-2-Clause-FreeBSD + * + * Copyright (c) 2018 Emmanuel Vadot + * Copyright (c) 2018 Greg V + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * $FreeBSD$ + */ + +#include +__FBSDID("$FreeBSD$"); + +#include +#include +#include +#include +#include +#include +#include + +#include + +#include +#include + +#include +#include +#include + +#include + +/* GATES */ + +#define PCLK_GPIO2 336 +#define PCLK_GPIO3 337 +#define PCLK_GPIO4 338 +#define PCLK_I2C1 341 +#define PCLK_I2C2 342 +#define PCLK_I2C3 343 +#define PCLK_I2C5 344 +#define PCLK_I2C6 345 +#define PCLK_I2C7 346 + +static struct rk_cru_gate rk3399_gates[] = { + /* CRU_CLKGATE_CON0 */ + CRU_GATE(0, "clk_core_l_lpll_src", "lpll", 0x300, 0) + CRU_GATE(0, "clk_core_l_bpll_src", "bpll", 0x300, 1) + CRU_GATE(0, "clk_core_l_dpll_src", "dpll", 0x300, 2) + CRU_GATE(0, "clk_core_l_gpll_src", "gpll", 0x300, 3) + + /* CRU_CLKGATE_CON1 */ + CRU_GATE(0, "clk_core_b_lpll_src", "lpll", 0x304, 0) + CRU_GATE(0, "clk_core_b_bpll_src", "bpll", 0x304, 1) + CRU_GATE(0, "clk_core_b_dpll_src", "dpll", 0x304, 2) + CRU_GATE(0, "clk_core_b_gpll_src", "gpll", 0x304, 3) + + /* CRU_CLKGATE_CON5 */ + CRU_GATE(0, "cpll_aclk_perihp_src", "cpll", 0x314, 0) + CRU_GATE(0, "gpll_aclk_perihp_src", "gpll", 0x314, 1) + + /* CRU_CLKGATE_CON7 */ + CRU_GATE(0, "gpll_aclk_perilp0_src", "gpll", 0x31C, 0) + CRU_GATE(0, "cpll_aclk_perilp0_src", "cpll", 0x31C, 1) + + /* CRU_CLKGATE_CON8 */ + CRU_GATE(0, "hclk_perilp1_cpll_src", "cpll", 0x320, 1) + CRU_GATE(0, "hclk_perilp1_gpll_src", "gpll", 0x320, 0) + + /* CRU_CLKGATE_CON22 */ + CRU_GATE(PCLK_I2C7, "pclk_rki2c7", "pclk_perilp1", 0x358, 5) + CRU_GATE(PCLK_I2C1, "pclk_rki2c1", "pclk_perilp1", 0x358, 6) + CRU_GATE(PCLK_I2C5, "pclk_rki2c5", "pclk_perilp1", 0x358, 7) + CRU_GATE(PCLK_I2C6, "pclk_rki2c6", "pclk_perilp1", 0x358, 8) + CRU_GATE(PCLK_I2C2, "pclk_rki2c2", "pclk_perilp1", 0x358, 9) + CRU_GATE(PCLK_I2C3, "pclk_rki2c3", "pclk_perilp1", 0x358, 10) + + /* CRU_CLKGATE_CON31 */ + CRU_GATE(PCLK_GPIO2, "pclk_gpio2", "pclk_alive", 0x37c, 3) + CRU_GATE(PCLK_GPIO3, "pclk_gpio3", "pclk_alive", 0x37c, 4) + CRU_GATE(PCLK_GPIO4, "pclk_gpio4", "pclk_alive", 0x37c, 5) +}; + + +/* + * PLLs + */ + +#define PLL_APLLL 1 +#define PLL_APLLB 2 +#define PLL_DPLL 3 +#define PLL_CPLL 4 +#define PLL_GPLL 5 +#define PLL_NPLL 6 +#define PLL_VPLL 7 + +static struct rk_clk_pll_rate rk3399_pll_rates[] = { + { + .freq = 2208000000, + .refdiv = 1, + .fbdiv = 92, + .postdiv1 = 1, + .postdiv2 = 1, + .dsmpd = 1, + }, + { + .freq = 2184000000, + .refdiv = 1, + .fbdiv = 91, + .postdiv1 = 1, + .postdiv2 = 1, + .dsmpd = 1, + }, + { + .freq = 2160000000, + .refdiv = 1, + .fbdiv = 90, + .postdiv1 = 1, + .postdiv2 = 1, + .dsmpd = 1, + }, + { + .freq = 2136000000, + .refdiv = 1, + .fbdiv = 89, + .postdiv1 = 1, + .postdiv2 = 1, + .dsmpd = 1, + }, + { + .freq = 2112000000, + .refdiv = 1, + .fbdiv = 88, + .postdiv1 = 1, + .postdiv2 = 1, + .dsmpd = 1, + }, + { + .freq = 2088000000, + .refdiv = 1, + .fbdiv = 87, + .postdiv1 = 1, + .postdiv2 = 1, + .dsmpd = 1, + }, + { + .freq = 2064000000, + .refdiv = 1, + .fbdiv = 86, + .postdiv1 = 1, + .postdiv2 = 1, + .dsmpd = 1, + }, + { + .freq = 2040000000, + .refdiv = 1, + .fbdiv = 85, + .postdiv1 = 1, + .postdiv2 = 1, + .dsmpd = 1, + }, + { + .freq = 2016000000, + .refdiv = 1, + .fbdiv = 84, + .postdiv1 = 1, + .postdiv2 = 1, + .dsmpd = 1, + }, + { + .freq = 1992000000, + .refdiv = 1, + .fbdiv = 83, + .postdiv1 = 1, + .postdiv2 = 1, + .dsmpd = 1, + }, + { + .freq = 1968000000, + .refdiv = 1, + .fbdiv = 82, + .postdiv1 = 1, + .postdiv2 = 1, + .dsmpd = 1, + }, + { + .freq = 1944000000, + .refdiv = 1, + .fbdiv = 81, + .postdiv1 = 1, + .postdiv2 = 1, + .dsmpd = 1, + }, + { + .freq = 1920000000, + .refdiv = 1, + .fbdiv = 80, + .postdiv1 = 1, + .postdiv2 = 1, + .dsmpd = 1, + }, + { + .freq = 1896000000, + .refdiv = 1, + .fbdiv = 79, + .postdiv1 = 1, + .postdiv2 = 1, + .dsmpd = 1, + }, + { + .freq = 1872000000, + .refdiv = 1, + .fbdiv = 78, + .postdiv1 = 1, + .postdiv2 = 1, + .dsmpd = 1, + }, + { + .freq = 1848000000, + .refdiv = 1, + .fbdiv = 77, + .postdiv1 = 1, + .postdiv2 = 1, + .dsmpd = 1, + }, + { + .freq = 1824000000, + .refdiv = 1, + .fbdiv = 76, + .postdiv1 = 1, + .postdiv2 = 1, + .dsmpd = 1, + }, + { + .freq = 1800000000, + .refdiv = 1, + .fbdiv = 75, + .postdiv1 = 1, + .postdiv2 = 1, + .dsmpd = 1, + }, + { + .freq = 1776000000, + .refdiv = 1, + .fbdiv = 74, + .postdiv1 = 1, + .postdiv2 = 1, + .dsmpd = 1, + }, + { + .freq = 1752000000, + .refdiv = 1, + .fbdiv = 73, + .postdiv1 = 1, + .postdiv2 = 1, + .dsmpd = 1, + }, + { + .freq = 1728000000, + .refdiv = 1, + .fbdiv = 72, + .postdiv1 = 1, + .postdiv2 = 1, + .dsmpd = 1, + }, + { + .freq = 1704000000, + .refdiv = 1, + .fbdiv = 71, + .postdiv1 = 1, + .postdiv2 = 1, + .dsmpd = 1, + }, + { + .freq = 1680000000, + .refdiv = 1, + .fbdiv = 70, + .postdiv1 = 1, + .postdiv2 = 1, + .dsmpd = 1, + }, + { + .freq = 1656000000, + .refdiv = 1, + .fbdiv = 69, + .postdiv1 = 1, + .postdiv2 = 1, + .dsmpd = 1, + }, + { + .freq = 1632000000, + .refdiv = 1, + .fbdiv = 68, + .postdiv1 = 1, + .postdiv2 = 1, + .dsmpd = 1, + }, + { + .freq = 1608000000, + .refdiv = 1, + .fbdiv = 67, + .postdiv1 = 1, + .postdiv2 = 1, + .dsmpd = 1, + }, + { + .freq = 1600000000, + .refdiv = 3, + .fbdiv = 200, + .postdiv1 = 1, + .postdiv2 = 1, + .dsmpd = 1, + }, + { + .freq = 1584000000, + .refdiv = 1, + .fbdiv = 66, + .postdiv1 = 1, + .postdiv2 = 1, + .dsmpd = 1, + }, + { + .freq = 1560000000, + .refdiv = 1, + .fbdiv = 65, + .postdiv1 = 1, + .postdiv2 = 1, + .dsmpd = 1, + }, + { + .freq = 1536000000, + .refdiv = 1, + .fbdiv = 64, + .postdiv1 = 1, + .postdiv2 = 1, + .dsmpd = 1, + }, + { + .freq = 1512000000, + .refdiv = 1, + .fbdiv = 63, + .postdiv1 = 1, + .postdiv2 = 1, + .dsmpd = 1, + }, + { + .freq = 1488000000, + .refdiv = 1, + .fbdiv = 62, + .postdiv1 = 1, + .postdiv2 = 1, + .dsmpd = 1, + }, + { + .freq = 1464000000, + .refdiv = 1, + .fbdiv = 61, + .postdiv1 = 1, + .postdiv2 = 1, + .dsmpd = 1, + }, + { + .freq = 1440000000, + .refdiv = 1, + .fbdiv = 60, + .postdiv1 = 1, + .postdiv2 = 1, + .dsmpd = 1, + }, + { + .freq = 1416000000, + .refdiv = 1, + .fbdiv = 59, + .postdiv1 = 1, + .postdiv2 = 1, + .dsmpd = 1, + }, + { + .freq = 1392000000, + .refdiv = 1, + .fbdiv = 58, + .postdiv1 = 1, + .postdiv2 = 1, + .dsmpd = 1, + }, + { + .freq = 1368000000, + .refdiv = 1, + .fbdiv = 57, + .postdiv1 = 1, + .postdiv2 = 1, + .dsmpd = 1, + }, + { + .freq = 1344000000, + .refdiv = 1, + .fbdiv = 56, + .postdiv1 = 1, + .postdiv2 = 1, + .dsmpd = 1, + }, + { + .freq = 1320000000, + .refdiv = 1, + .fbdiv = 55, + .postdiv1 = 1, + .postdiv2 = 1, + .dsmpd = 1, + }, + { + .freq = 1296000000, + .refdiv = 1, + .fbdiv = 54, + .postdiv1 = 1, + .postdiv2 = 1, + .dsmpd = 1, + }, + { + .freq = 1272000000, + .refdiv = 1, + .fbdiv = 53, + .postdiv1 = 1, + .postdiv2 = 1, + .dsmpd = 1, + }, + { + .freq = 1248000000, + .refdiv = 1, + .fbdiv = 52, + .postdiv1 = 1, + .postdiv2 = 1, + .dsmpd = 1, + }, + { + .freq = 1200000000, + .refdiv = 1, + .fbdiv = 50, + .postdiv1 = 1, + .postdiv2 = 1, + .dsmpd = 1, + }, + { + .freq = 1188000000, + .refdiv = 2, + .fbdiv = 99, + .postdiv1 = 1, + .postdiv2 = 1, + .dsmpd = 1, + }, + { + .freq = 1104000000, + .refdiv = 1, + .fbdiv = 46, + .postdiv1 = 1, + .postdiv2 = 1, + .dsmpd = 1, + }, + { + .freq = 1100000000, + .refdiv = 12, + .fbdiv = 550, + .postdiv1 = 1, + .postdiv2 = 1, + .dsmpd = 1, + }, + { + .freq = 1008000000, + .refdiv = 1, + .fbdiv = 84, + .postdiv1 = 2, + .postdiv2 = 1, + .dsmpd = 1, + }, + { + .freq = 1000000000, + .refdiv = 1, + .fbdiv = 125, + .postdiv1 = 3, + .postdiv2 = 1, + .dsmpd = 1, + }, + { + .freq = 984000000, + .refdiv = 1, + .fbdiv = 82, + .postdiv1 = 2, + .postdiv2 = 1, + .dsmpd = 1, + }, + { + .freq = 960000000, + .refdiv = 1, + .fbdiv = 80, + .postdiv1 = 2, + .postdiv2 = 1, + .dsmpd = 1, + }, + { + .freq = 936000000, + .refdiv = 1, + .fbdiv = 78, + .postdiv1 = 2, + .postdiv2 = 1, + .dsmpd = 1, + }, + { + .freq = 912000000, + .refdiv = 1, + .fbdiv = 76, + .postdiv1 = 2, + .postdiv2 = 1, + .dsmpd = 1, + }, + { + .freq = 900000000, + .refdiv = 4, + .fbdiv = 300, + .postdiv1 = 2, + .postdiv2 = 1, + .dsmpd = 1, + }, + { + .freq = 888000000, + .refdiv = 1, + .fbdiv = 74, + .postdiv1 = 2, + .postdiv2 = 1, + .dsmpd = 1, + }, + { + .freq = 864000000, + .refdiv = 1, + .fbdiv = 72, + .postdiv1 = 2, + .postdiv2 = 1, + .dsmpd = 1, + }, + { + .freq = 840000000, + .refdiv = 1, + .fbdiv = 70, + .postdiv1 = 2, + .postdiv2 = 1, + .dsmpd = 1, + }, + { + .freq = 816000000, + .refdiv = 1, + .fbdiv = 68, + .postdiv1 = 2, + .postdiv2 = 1, + .dsmpd = 1, + }, + { + .freq = 800000000, + .refdiv = 1, + .fbdiv = 100, + .postdiv1 = 3, + .postdiv2 = 1, + .dsmpd = 1, + }, + { + .freq = 700000000, + .refdiv = 6, + .fbdiv = 350, + .postdiv1 = 2, + .postdiv2 = 1, + .dsmpd = 1, + }, + { + .freq = 696000000, + .refdiv = 1, + .fbdiv = 58, + .postdiv1 = 2, + .postdiv2 = 1, + .dsmpd = 1, + }, + { + .freq = 676000000, + .refdiv = 3, + .fbdiv = 169, + .postdiv1 = 2, + .postdiv2 = 1, + .dsmpd = 1, + }, + { + .freq = 600000000, + .refdiv = 1, + .fbdiv = 75, + .postdiv1 = 3, + .postdiv2 = 1, + .dsmpd = 1, + }, + { + .freq = 594000000, + .refdiv = 1, + .fbdiv = 99, + .postdiv1 = 4, + .postdiv2 = 1, + .dsmpd = 1, + }, + { + .freq = 533250000, + .refdiv = 8, + .fbdiv = 711, + .postdiv1 = 4, + .postdiv2 = 1, + .dsmpd = 1, + }, + { + .freq = 504000000, + .refdiv = 1, + .fbdiv = 63, + .postdiv1 = 3, + .postdiv2 = 1, + .dsmpd = 1, + }, + { + .freq = 500000000, + .refdiv = 6, + .fbdiv = 250, + .postdiv1 = 2, + .postdiv2 = 1, + .dsmpd = 1, + }, + { + .freq = 408000000, + .refdiv = 1, + .fbdiv = 68, + .postdiv1 = 2, + .postdiv2 = 2, + .dsmpd = 1, + }, + { + .freq = 312000000, + .refdiv = 1, + .fbdiv = 52, + .postdiv1 = 2, + .postdiv2 = 2, + .dsmpd = 1, + }, + { + .freq = 297000000, + .refdiv = 1, + .fbdiv = 99, + .postdiv1 = 4, + .postdiv2 = 2, + .dsmpd = 1, + }, + { + .freq = 216000000, + .refdiv = 1, + .fbdiv = 72, + .postdiv1 = 4, + .postdiv2 = 2, + .dsmpd = 1, + }, + { + .freq = 148500000, + .refdiv = 1, + .fbdiv = 99, + .postdiv1 = 4, + .postdiv2 = 4, + .dsmpd = 1, + }, + { + .freq = 106500000, + .refdiv = 1, + .fbdiv = 71, + .postdiv1 = 4, + .postdiv2 = 4, + .dsmpd = 1, + }, + { + .freq = 96000000, + .refdiv = 1, + .fbdiv = 64, + .postdiv1 = 4, + .postdiv2 = 4, + .dsmpd = 1, + }, + { + .freq = 74250000, + .refdiv = 2, + .fbdiv = 99, + .postdiv1 = 4, + .postdiv2 = 4, + .dsmpd = 1, + }, + { + .freq = 65000000, + .refdiv = 1, + .fbdiv = 65, + .postdiv1 = 6, + .postdiv2 = 4, + .dsmpd = 1, + }, + { + .freq = 54000000, + .refdiv = 1, + .fbdiv = 54, + .postdiv1 = 6, + .postdiv2 = 4, + .dsmpd = 1, + }, + { + .freq = 27000000, + .refdiv = 1, + .fbdiv = 27, + .postdiv1 = 6, + .postdiv2 = 4, + .dsmpd = 1, + }, + {}, +}; + +static const char *pll_parents[] = {"xin24m"}; + +static struct rk_clk_pll_def lpll = { + .clkdef = { + .id = PLL_APLLL, + .name = "lpll", + .parent_names = pll_parents, + .parent_cnt = nitems(pll_parents), + }, + .base_offset = 0x00, + .gate_offset = 0x300, + .gate_shift = 0, + .flags = RK_CLK_PLL_HAVE_GATE, + .rates = rk3399_pll_rates, +}; + +static struct rk_clk_pll_def bpll = { + .clkdef = { + .id = PLL_APLLB, + .name = "bpll", + .parent_names = pll_parents, + .parent_cnt = nitems(pll_parents), + }, + .base_offset = 0x20, + .gate_offset = 0x300, + .gate_shift = 1, + .flags = RK_CLK_PLL_HAVE_GATE, + .rates = rk3399_pll_rates, +}; + +static struct rk_clk_pll_def dpll = { + .clkdef = { + .id = PLL_DPLL, + .name = "dpll", + .parent_names = pll_parents, + .parent_cnt = nitems(pll_parents), + }, + .base_offset = 0x40, + .gate_offset = 0x300, + .gate_shift = 2, + .flags = RK_CLK_PLL_HAVE_GATE, + .rates = rk3399_pll_rates, +}; + + +static struct rk_clk_pll_def cpll = { + .clkdef = { + .id = PLL_CPLL, + .name = "cpll", + .parent_names = pll_parents, + .parent_cnt = nitems(pll_parents), + }, + .base_offset = 0x60, + .rates = rk3399_pll_rates, +}; + +static struct rk_clk_pll_def gpll = { + .clkdef = { + .id = PLL_GPLL, + .name = "gpll", + .parent_names = pll_parents, + .parent_cnt = nitems(pll_parents), + }, + .base_offset = 0x80, + .gate_offset = 0x300, + .gate_shift = 3, + .flags = RK_CLK_PLL_HAVE_GATE, + .rates = rk3399_pll_rates, +}; + +static struct rk_clk_pll_def npll = { + .clkdef = { + .id = PLL_NPLL, + .name = "npll", + .parent_names = pll_parents, + .parent_cnt = nitems(pll_parents), + }, + .base_offset = 0xa0, + .rates = rk3399_pll_rates, +}; + +static struct rk_clk_pll_def vpll = { + .clkdef = { + .id = PLL_VPLL, + .name = "vpll", + .parent_names = pll_parents, + .parent_cnt = nitems(pll_parents), + }, + .base_offset = 0xc0, + .rates = rk3399_pll_rates, +}; + +#define ACLK_PERIHP 192 +#define HCLK_PERIHP 448 +#define PCLK_PERIHP 320 + +static const char *aclk_perihp_parents[] = {"cpll_aclk_perihp_src", "gpll_aclk_perihp_src"}; + +static struct rk_clk_composite_def aclk_perihp = { + .clkdef = { + .id = ACLK_PERIHP, + .name = "aclk_perihp", + .parent_names = aclk_perihp_parents, + .parent_cnt = nitems(aclk_perihp_parents), + }, + /* CRU_CLKSEL_CON14 */ + .muxdiv_offset = 0x138, + + .mux_shift = 7, + .mux_width = 1, + + .div_shift = 0, + .div_width = 5, + + /* CRU_CLKGATE_CON5 */ + .gate_offset = 0x314, + .gate_shift = 2, + + .flags = RK_CLK_COMPOSITE_HAVE_MUX | RK_CLK_COMPOSITE_HAVE_GATE, +}; + +static const char *hclk_pclk_perihp_parents[] = {"aclk_perihp"}; + +static struct rk_clk_composite_def hclk_perihp = { + .clkdef = { + .id = HCLK_PERIHP, + .name = "hclk_perihp", + .parent_names = hclk_pclk_perihp_parents, + .parent_cnt = nitems(hclk_pclk_perihp_parents), + }, + /* CRU_CLKSEL_CON14 */ + .muxdiv_offset = 0x138, + + .div_shift = 8, + .div_width = 2, + + /* CRU_CLKGATE_CON5 */ + .gate_offset = 0x314, + .gate_shift = 3, + + .flags = RK_CLK_COMPOSITE_HAVE_MUX | RK_CLK_COMPOSITE_HAVE_GATE, +}; + +static struct rk_clk_composite_def pclk_perihp = { + .clkdef = { + .id = PCLK_PERIHP, + .name = "pclk_perihp", + .parent_names = hclk_pclk_perihp_parents, + .parent_cnt = nitems(hclk_pclk_perihp_parents), + }, + /* CRU_CLKSEL_CON14 */ + .muxdiv_offset = 0x138, + + .div_shift = 12, + .div_width = 3, + + /* CRU_CLKGATE_CON5 */ + .gate_offset = 0x314, + .gate_shift = 4, + + .flags = RK_CLK_COMPOSITE_HAVE_MUX | RK_CLK_COMPOSITE_HAVE_GATE, +}; + +#define ACLK_PERILP0 194 +#define HCLK_PERILP0 449 +#define PCLK_PERILP0 322 + +static const char *aclk_perilp0_parents[] = {"cpll_aclk_perilp0_src", "gpll_aclk_perilp0_src"}; + +static struct rk_clk_composite_def aclk_perilp0 = { + .clkdef = { + .id = ACLK_PERILP0, + .name = "aclk_perilp0", + .parent_names = aclk_perilp0_parents, + .parent_cnt = nitems(aclk_perilp0_parents), + }, + /* CRU_CLKSEL_CON14 */ + .muxdiv_offset = 0x15C, + + .mux_shift = 7, + .mux_width = 1, + + .div_shift = 0, + .div_width = 5, + + /* CRU_CLKGATE_CON7 */ + .gate_offset = 0x31C, + .gate_shift = 2, + + .flags = RK_CLK_COMPOSITE_HAVE_MUX | RK_CLK_COMPOSITE_HAVE_GATE, +}; + +static const char *hclk_pclk_perilp0_parents[] = {"aclk_perilp0"}; + +static struct rk_clk_composite_def hclk_perilp0 = { + .clkdef = { + .id = HCLK_PERILP0, + .name = "hclk_perilp0", + .parent_names = hclk_pclk_perilp0_parents, + .parent_cnt = nitems(hclk_pclk_perilp0_parents), + }, + /* CRU_CLKSEL_CON23 */ + .muxdiv_offset = 0x15C, + + .div_shift = 8, + .div_width = 2, + + /* CRU_CLKGATE_CON7 */ + .gate_offset = 0x31C, + .gate_shift = 3, + + .flags = RK_CLK_COMPOSITE_HAVE_MUX | RK_CLK_COMPOSITE_HAVE_GATE, +}; + +static struct rk_clk_composite_def pclk_perilp0 = { + .clkdef = { + .id = PCLK_PERILP0, + .name = "pclk_perilp0", + .parent_names = hclk_pclk_perilp0_parents, + .parent_cnt = nitems(hclk_pclk_perilp0_parents), + }, + /* CRU_CLKSEL_CON23 */ + .muxdiv_offset = 0x15C, + + .div_shift = 12, + .div_width = 3, + + /* CRU_CLKGATE_CON7 */ + .gate_offset = 0x31C, + .gate_shift = 4, + + .flags = RK_CLK_COMPOSITE_HAVE_MUX | RK_CLK_COMPOSITE_HAVE_GATE, +}; + +/* + * misc + */ +#define PCLK_ALIVE 390 + +static const char *alive_parents[] = {"gpll"}; + +static struct rk_clk_composite_def pclk_alive = { + .clkdef = { + .id = PCLK_ALIVE, + .name = "pclk_alive", + .parent_names = alive_parents, + .parent_cnt = nitems(alive_parents), + }, + /* CRU_CLKSEL_CON57 */ + .muxdiv_offset = 0x01e4, + + .div_shift = 0, + .div_width = 5, +}; + +#define HCLK_PERILP1 450 +#define PCLK_PERILP1 323 + +static const char *hclk_perilp1_parents[] = {"cpll", "gpll"}; + +static struct rk_clk_composite_def hclk_perilp1 = { + .clkdef = { + .id = HCLK_PERILP1, + .name = "hclk_perilp1", + .parent_names = hclk_perilp1_parents, + .parent_cnt = nitems(hclk_perilp1_parents), + }, + /* CRU_CLKSEL_CON25 */ + .muxdiv_offset = 0x164, + .mux_shift = 7, + .mux_width = 1, + + .div_shift = 0, + .div_width = 5, + + .flags = RK_CLK_COMPOSITE_HAVE_MUX, +}; + +static const char *pclk_perilp1_parents[] = {"hclk_perilp1"}; + +static struct rk_clk_composite_def pclk_perilp1 = { + .clkdef = { + .id = PCLK_PERILP1, + .name = "pclk_perilp1", + .parent_names = pclk_perilp1_parents, + .parent_cnt = nitems(pclk_perilp1_parents), + }, + /* CRU_CLKSEL_CON25 */ + .muxdiv_offset = 0x164, + + .div_shift = 8, + .div_width = 3, + + /* CRU_CLKGATE_CON8 */ + .gate_offset = 0x320, + .gate_shift = 2, + + .flags = RK_CLK_COMPOSITE_HAVE_GATE, +}; + +/* + * i2c + */ +static const char *i2c_parents[] = {"cpll", "gpll"}; + +#define SCLK_I2C1 65 +#define SCLK_I2C2 66 +#define SCLK_I2C3 67 +#define SCLK_I2C5 68 +#define SCLK_I2C6 69 +#define SCLK_I2C7 70 + +static struct rk_clk_composite_def i2c1 = { + .clkdef = { + .id = SCLK_I2C1, + .name = "clk_i2c1", + .parent_names = i2c_parents, + .parent_cnt = nitems(i2c_parents), + }, + /* CRU_CLKSEL_CON61 */ + .muxdiv_offset = 0x01f4, + .mux_shift = 7, + .mux_width = 1, + + .div_shift = 0, + .div_width = 7, + + /* CRU_CLKGATE_CON10 */ + .gate_offset = 0x0328, + .gate_shift = 0, + + .flags = RK_CLK_COMPOSITE_HAVE_MUX | RK_CLK_COMPOSITE_HAVE_GATE, +}; + +static struct rk_clk_composite_def i2c2 = { + .clkdef = { + .id = SCLK_I2C2, + .name = "clk_i2c2", + .parent_names = i2c_parents, + .parent_cnt = nitems(i2c_parents), + }, + /* CRU_CLKSEL_CON62 */ + .muxdiv_offset = 0x01f8, + .mux_shift = 7, + .mux_width = 1, + + .div_shift = 0, + .div_width = 7, + + /* CRU_CLKGATE_CON10 */ + .gate_offset = 0x0328, + .gate_shift = 2, + + .flags = RK_CLK_COMPOSITE_HAVE_MUX | RK_CLK_COMPOSITE_HAVE_GATE, +}; + +static struct rk_clk_composite_def i2c3 = { + .clkdef = { + .id = SCLK_I2C3, + .name = "clk_i2c3", + .parent_names = i2c_parents, + .parent_cnt = nitems(i2c_parents), + }, + /* CRU_CLKSEL_CON63 */ + .muxdiv_offset = 0x01fc, + .mux_shift = 7, + .mux_width = 1, + + .div_shift = 0, + .div_width = 7, + + /* CRU_CLKGATE_CON10 */ + .gate_offset = 0x0328, + .gate_shift = 4, + + .flags = RK_CLK_COMPOSITE_HAVE_MUX | RK_CLK_COMPOSITE_HAVE_GATE, +}; + +static struct rk_clk_composite_def i2c5 = { + .clkdef = { + .id = SCLK_I2C5, + .name = "clk_i2c5", + .parent_names = i2c_parents, + .parent_cnt = nitems(i2c_parents), + }, + /* CRU_CLKSEL_CON61 */ + .muxdiv_offset = 0x01f4, + .mux_shift = 15, + .mux_width = 1, + + .div_shift = 8, + .div_width = 7, + + /* CRU_CLKGATE_CON10 */ + .gate_offset = 0x0328, + .gate_shift = 1, + + .flags = RK_CLK_COMPOSITE_HAVE_MUX | RK_CLK_COMPOSITE_HAVE_GATE, +}; + +static struct rk_clk_composite_def i2c6 = { + .clkdef = { + .id = SCLK_I2C6, + .name = "clk_i2c6", + .parent_names = i2c_parents, + .parent_cnt = nitems(i2c_parents), + }, + /* CRU_CLKSEL_CON62 */ + .muxdiv_offset = 0x01f8, + .mux_shift = 15, + .mux_width = 1, + + .div_shift = 8, + .div_width = 7, + + /* CRU_CLKGATE_CON10 */ + .gate_offset = 0x0328, + .gate_shift = 3, + + .flags = RK_CLK_COMPOSITE_HAVE_MUX | RK_CLK_COMPOSITE_HAVE_GATE, +}; + +static struct rk_clk_composite_def i2c7 = { + .clkdef = { + .id = SCLK_I2C7, + .name = "clk_i2c7", + .parent_names = i2c_parents, + .parent_cnt = nitems(i2c_parents), + }, + /* CRU_CLKSEL_CON63 */ + .muxdiv_offset = 0x01fc, + .mux_shift = 15, + .mux_width = 1, + + .div_shift = 8, + .div_width = 7, + + /* CRU_CLKGATE_CON10 */ + .gate_offset = 0x0328, + .gate_shift = 5, + + .flags = RK_CLK_COMPOSITE_HAVE_MUX | RK_CLK_COMPOSITE_HAVE_GATE, +}; + +/* + * ARM CPU clocks (LITTLE and big) + */ +#define ARMCLKL 8 +#define ARMCLKB 9 + +static const char *armclk_parents[] = {"lpll", "bpll", "dpll", "gpll"}; + +static struct rk_clk_armclk_rates rk3399_armclkl_rates[] = { + { + .freq = 1800000000, + .div = 1, + }, + { + .freq = 1704000000, + .div = 1, + }, + { + .freq = 1608000000, + .div = 1, + }, + { + .freq = 1512000000, + .div = 1, + }, + { + .freq = 1488000000, + .div = 1, + }, + { + .freq = 1416000000, + .div = 1, + }, + { + .freq = 1200000000, + .div = 1, + }, + { + .freq = 1008000000, + .div = 1, + }, + { + .freq = 816000000, + .div = 1, + }, + { + .freq = 696000000, + .div = 1, + }, + { + .freq = 600000000, + .div = 1, + }, + { + .freq = 408000000, + .div = 1, + }, + { + .freq = 312000000, + .div = 1, + }, + { + .freq = 216000000, + .div = 1, + }, + { + .freq = 96000000, + .div = 1, + }, +}; + +static struct rk_clk_armclk_def armclk_l = { + .clkdef = { + .id = ARMCLKL, + .name = "armclkl", + .parent_names = armclk_parents, + .parent_cnt = nitems(armclk_parents), + }, + /* CRU_CLKSEL_CON0 */ + .muxdiv_offset = 0x100, + .mux_shift = 6, + .mux_width = 2, + + .div_shift = 0, + .div_width = 5, + + .flags = RK_CLK_COMPOSITE_HAVE_MUX, + .main_parent = 0, + .alt_parent = 3, + + .rates = rk3399_armclkl_rates, + .nrates = nitems(rk3399_armclkl_rates), +}; + +static struct rk_clk_armclk_rates rk3399_armclkb_rates[] = { + { + .freq = 2208000000, + .div = 1, + }, + { + .freq = 2184000000, + .div = 1, + }, + { + .freq = 2088000000, + .div = 1, + }, + { + .freq = 2040000000, + .div = 1, + }, + { + .freq = 2016000000, + .div = 1, + }, + { + .freq = 1992000000, + .div = 1, + }, + { + .freq = 1896000000, + .div = 1, + }, + { + .freq = 1800000000, + .div = 1, + }, + { + .freq = 1704000000, + .div = 1, + }, + { + .freq = 1608000000, + .div = 1, + }, + { + .freq = 1512000000, + .div = 1, + }, + { + .freq = 1488000000, + .div = 1, + }, + { + .freq = 1416000000, + .div = 1, + }, + { + .freq = 1200000000, + .div = 1, + }, + { + .freq = 1008000000, + .div = 1, + }, + { + .freq = 816000000, + .div = 1, + }, + { + .freq = 696000000, + .div = 1, + }, + { + .freq = 600000000, + .div = 1, + }, + { + .freq = 408000000, + .div = 1, + }, + { + .freq = 312000000, + .div = 1, + }, + { + .freq = 216000000, + .div = 1, + }, + { + .freq = 96000000, + .div = 1, + }, +}; + +static struct rk_clk_armclk_def armclk_b = { + .clkdef = { + .id = ARMCLKB, + .name = "armclkb", + .parent_names = armclk_parents, + .parent_cnt = nitems(armclk_parents), + }, + .muxdiv_offset = 0x108, + .mux_shift = 6, + .mux_width = 2, + + .div_shift = 0, + .div_width = 5, + + .flags = RK_CLK_COMPOSITE_HAVE_MUX, + .main_parent = 1, + .alt_parent = 3, + + .rates = rk3399_armclkb_rates, + .nrates = nitems(rk3399_armclkb_rates), +}; + +static struct rk_clk rk3399_clks[] = { + { + .type = RK3399_CLK_PLL, + .clk.pll = &lpll + }, + { + .type = RK3399_CLK_PLL, + .clk.pll = &bpll + }, + { + .type = RK3399_CLK_PLL, + .clk.pll = &dpll + }, + { + .type = RK3399_CLK_PLL, + .clk.pll = &cpll + }, + { + .type = RK3399_CLK_PLL, + .clk.pll = &gpll + }, + { + .type = RK3399_CLK_PLL, + .clk.pll = &npll + }, + { + .type = RK3399_CLK_PLL, + .clk.pll = &vpll + }, + + { + .type = RK_CLK_COMPOSITE, + .clk.composite = &aclk_perihp, + }, + { + .type = RK_CLK_COMPOSITE, + .clk.composite = &hclk_perihp, + }, + { + .type = RK_CLK_COMPOSITE, + .clk.composite = &pclk_perihp, + }, + { + .type = RK_CLK_COMPOSITE, + .clk.composite = &aclk_perilp0, + }, + { + .type = RK_CLK_COMPOSITE, + .clk.composite = &hclk_perilp0, + }, + { + .type = RK_CLK_COMPOSITE, + .clk.composite = &pclk_perilp0, + }, + { + .type = RK_CLK_COMPOSITE, + .clk.composite = &pclk_alive, + }, + { + .type = RK_CLK_COMPOSITE, + .clk.composite = &hclk_perilp1, + }, + { + .type = RK_CLK_COMPOSITE, + .clk.composite = &pclk_perilp1, + }, + { + .type = RK_CLK_COMPOSITE, + .clk.composite = &i2c1, + }, + { + .type = RK_CLK_COMPOSITE, + .clk.composite = &i2c2, + }, + { + .type = RK_CLK_COMPOSITE, + .clk.composite = &i2c3, + }, + { + .type = RK_CLK_COMPOSITE, + .clk.composite = &i2c5, + }, + { + .type = RK_CLK_COMPOSITE, + .clk.composite = &i2c6, + }, + { + .type = RK_CLK_COMPOSITE, + .clk.composite = &i2c7, + }, + + { + .type = RK_CLK_ARMCLK, + .clk.armclk = &armclk_l, + }, + { + .type = RK_CLK_ARMCLK, + .clk.armclk = &armclk_b, + }, +}; + +static int +rk3399_cru_probe(device_t dev) +{ + + if (!ofw_bus_status_okay(dev)) + return (ENXIO); + + if (ofw_bus_is_compatible(dev, "rockchip,rk3399-cru")) { + device_set_desc(dev, "Rockchip RK3399 Clock and Reset Unit"); + return (BUS_PROBE_DEFAULT); + } + + return (ENXIO); +} + +static int +rk3399_cru_attach(device_t dev) +{ + struct rk_cru_softc *sc; + + sc = device_get_softc(dev); + sc->dev = dev; + + sc->gates = rk3399_gates; + sc->ngates = nitems(rk3399_gates); + + sc->clks = rk3399_clks; + sc->nclks = nitems(rk3399_clks); + + return (rk_cru_attach(dev)); +} + +static device_method_t rk3399_cru_methods[] = { + /* Device interface */ + DEVMETHOD(device_probe, rk3399_cru_probe), + DEVMETHOD(device_attach, rk3399_cru_attach), + + DEVMETHOD_END +}; + +static devclass_t rk3399_cru_devclass; + +DEFINE_CLASS_1(rk3399_cru, rk3399_cru_driver, rk3399_cru_methods, + sizeof(struct rk_cru_softc), rk_cru_driver); + +EARLY_DRIVER_MODULE(rk3399_cru, simplebus, rk3399_cru_driver, + rk3399_cru_devclass, 0, 0, BUS_PASS_BUS + BUS_PASS_ORDER_MIDDLE); Property changes on: head/sys/arm64/rockchip/clk/rk3399_cru.c ___________________________________________________________________ Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:keywords ## -0,0 +1 ## +FreeBSD=%H \ No newline at end of property Added: svn:mime-type ## -0,0 +1 ## +text/plain \ No newline at end of property Index: head/sys/arm64/rockchip/clk/rk3399_pmucru.c =================================================================== --- head/sys/arm64/rockchip/clk/rk3399_pmucru.c (nonexistent) +++ head/sys/arm64/rockchip/clk/rk3399_pmucru.c (revision 341382) @@ -0,0 +1,866 @@ +/*- + * SPDX-License-Identifier: BSD-2-Clause-FreeBSD + * + * Copyright (c) 2018 Emmanuel Vadot + * Copyright (c) 2018 Greg V + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * $FreeBSD$ + */ + +#include +__FBSDID("$FreeBSD$"); + +#include +#include +#include +#include +#include +#include +#include + +#include + +#include +#include + +#include +#include +#include + +#include + +/* GATES */ + +#define PCLK_PMU 20 +#define PCLK_GPIO0_PMU 23 +#define PCLK_GPIO1_PMU 24 +#define PCLK_I2C0_PMU 27 +#define PCLK_I2C4_PMU 28 +#define PCLK_I2C8_PMU 29 + +static struct rk_cru_gate rk3399_pmu_gates[] = { + /* PMUCRU_CLKGATE_CON1 */ + CRU_GATE(PCLK_PMU, "pclk_pmu", "pclk_pmu_src", 0x104, 0) + CRU_GATE(PCLK_GPIO0_PMU, "pclk_gpio0_pmu", "pclk_pmu_src", 0x104, 3) + CRU_GATE(PCLK_GPIO1_PMU, "pclk_gpio1_pmu", "pclk_pmu_src", 0x104, 4) + CRU_GATE(PCLK_I2C0_PMU, "pclk_i2c0_pmu", "pclk_pmu_src", 0x104, 7) + CRU_GATE(PCLK_I2C4_PMU, "pclk_i2c4_pmu", "pclk_pmu_src", 0x104, 8) + CRU_GATE(PCLK_I2C8_PMU, "pclk_i2c8_pmu", "pclk_pmu_src", 0x104, 9) +}; + + +/* + * PLLs + */ + +#define PLL_PPLL 1 + +static struct rk_clk_pll_rate rk3399_pll_rates[] = { + { + .freq = 2208000000, + .refdiv = 1, + .fbdiv = 92, + .postdiv1 = 1, + .postdiv2 = 1, + .dsmpd = 1, + }, + { + .freq = 2184000000, + .refdiv = 1, + .fbdiv = 91, + .postdiv1 = 1, + .postdiv2 = 1, + .dsmpd = 1, + }, + { + .freq = 2160000000, + .refdiv = 1, + .fbdiv = 90, + .postdiv1 = 1, + .postdiv2 = 1, + .dsmpd = 1, + }, + { + .freq = 2136000000, + .refdiv = 1, + .fbdiv = 89, + .postdiv1 = 1, + .postdiv2 = 1, + .dsmpd = 1, + }, + { + .freq = 2112000000, + .refdiv = 1, + .fbdiv = 88, + .postdiv1 = 1, + .postdiv2 = 1, + .dsmpd = 1, + }, + { + .freq = 2088000000, + .refdiv = 1, + .fbdiv = 87, + .postdiv1 = 1, + .postdiv2 = 1, + .dsmpd = 1, + }, + { + .freq = 2064000000, + .refdiv = 1, + .fbdiv = 86, + .postdiv1 = 1, + .postdiv2 = 1, + .dsmpd = 1, + }, + { + .freq = 2040000000, + .refdiv = 1, + .fbdiv = 85, + .postdiv1 = 1, + .postdiv2 = 1, + .dsmpd = 1, + }, + { + .freq = 2016000000, + .refdiv = 1, + .fbdiv = 84, + .postdiv1 = 1, + .postdiv2 = 1, + .dsmpd = 1, + }, + { + .freq = 1992000000, + .refdiv = 1, + .fbdiv = 83, + .postdiv1 = 1, + .postdiv2 = 1, + .dsmpd = 1, + }, + { + .freq = 1968000000, + .refdiv = 1, + .fbdiv = 82, + .postdiv1 = 1, + .postdiv2 = 1, + .dsmpd = 1, + }, + { + .freq = 1944000000, + .refdiv = 1, + .fbdiv = 81, + .postdiv1 = 1, + .postdiv2 = 1, + .dsmpd = 1, + }, + { + .freq = 1920000000, + .refdiv = 1, + .fbdiv = 80, + .postdiv1 = 1, + .postdiv2 = 1, + .dsmpd = 1, + }, + { + .freq = 1896000000, + .refdiv = 1, + .fbdiv = 79, + .postdiv1 = 1, + .postdiv2 = 1, + .dsmpd = 1, + }, + { + .freq = 1872000000, + .refdiv = 1, + .fbdiv = 78, + .postdiv1 = 1, + .postdiv2 = 1, + .dsmpd = 1, + }, + { + .freq = 1848000000, + .refdiv = 1, + .fbdiv = 77, + .postdiv1 = 1, + .postdiv2 = 1, + .dsmpd = 1, + }, + { + .freq = 1824000000, + .refdiv = 1, + .fbdiv = 76, + .postdiv1 = 1, + .postdiv2 = 1, + .dsmpd = 1, + }, + { + .freq = 1800000000, + .refdiv = 1, + .fbdiv = 75, + .postdiv1 = 1, + .postdiv2 = 1, + .dsmpd = 1, + }, + { + .freq = 1776000000, + .refdiv = 1, + .fbdiv = 74, + .postdiv1 = 1, + .postdiv2 = 1, + .dsmpd = 1, + }, + { + .freq = 1752000000, + .refdiv = 1, + .fbdiv = 73, + .postdiv1 = 1, + .postdiv2 = 1, + .dsmpd = 1, + }, + { + .freq = 1728000000, + .refdiv = 1, + .fbdiv = 72, + .postdiv1 = 1, + .postdiv2 = 1, + .dsmpd = 1, + }, + { + .freq = 1704000000, + .refdiv = 1, + .fbdiv = 71, + .postdiv1 = 1, + .postdiv2 = 1, + .dsmpd = 1, + }, + { + .freq = 1680000000, + .refdiv = 1, + .fbdiv = 70, + .postdiv1 = 1, + .postdiv2 = 1, + .dsmpd = 1, + }, + { + .freq = 1656000000, + .refdiv = 1, + .fbdiv = 69, + .postdiv1 = 1, + .postdiv2 = 1, + .dsmpd = 1, + }, + { + .freq = 1632000000, + .refdiv = 1, + .fbdiv = 68, + .postdiv1 = 1, + .postdiv2 = 1, + .dsmpd = 1, + }, + { + .freq = 1608000000, + .refdiv = 1, + .fbdiv = 67, + .postdiv1 = 1, + .postdiv2 = 1, + .dsmpd = 1, + }, + { + .freq = 1600000000, + .refdiv = 3, + .fbdiv = 200, + .postdiv1 = 1, + .postdiv2 = 1, + .dsmpd = 1, + }, + { + .freq = 1584000000, + .refdiv = 1, + .fbdiv = 66, + .postdiv1 = 1, + .postdiv2 = 1, + .dsmpd = 1, + }, + { + .freq = 1560000000, + .refdiv = 1, + .fbdiv = 65, + .postdiv1 = 1, + .postdiv2 = 1, + .dsmpd = 1, + }, + { + .freq = 1536000000, + .refdiv = 1, + .fbdiv = 64, + .postdiv1 = 1, + .postdiv2 = 1, + .dsmpd = 1, + }, + { + .freq = 1512000000, + .refdiv = 1, + .fbdiv = 63, + .postdiv1 = 1, + .postdiv2 = 1, + .dsmpd = 1, + }, + { + .freq = 1488000000, + .refdiv = 1, + .fbdiv = 62, + .postdiv1 = 1, + .postdiv2 = 1, + .dsmpd = 1, + }, + { + .freq = 1464000000, + .refdiv = 1, + .fbdiv = 61, + .postdiv1 = 1, + .postdiv2 = 1, + .dsmpd = 1, + }, + { + .freq = 1440000000, + .refdiv = 1, + .fbdiv = 60, + .postdiv1 = 1, + .postdiv2 = 1, + .dsmpd = 1, + }, + { + .freq = 1416000000, + .refdiv = 1, + .fbdiv = 59, + .postdiv1 = 1, + .postdiv2 = 1, + .dsmpd = 1, + }, + { + .freq = 1392000000, + .refdiv = 1, + .fbdiv = 58, + .postdiv1 = 1, + .postdiv2 = 1, + .dsmpd = 1, + }, + { + .freq = 1368000000, + .refdiv = 1, + .fbdiv = 57, + .postdiv1 = 1, + .postdiv2 = 1, + .dsmpd = 1, + }, + { + .freq = 1344000000, + .refdiv = 1, + .fbdiv = 56, + .postdiv1 = 1, + .postdiv2 = 1, + .dsmpd = 1, + }, + { + .freq = 1320000000, + .refdiv = 1, + .fbdiv = 55, + .postdiv1 = 1, + .postdiv2 = 1, + .dsmpd = 1, + }, + { + .freq = 1296000000, + .refdiv = 1, + .fbdiv = 54, + .postdiv1 = 1, + .postdiv2 = 1, + .dsmpd = 1, + }, + { + .freq = 1272000000, + .refdiv = 1, + .fbdiv = 53, + .postdiv1 = 1, + .postdiv2 = 1, + .dsmpd = 1, + }, + { + .freq = 1248000000, + .refdiv = 1, + .fbdiv = 52, + .postdiv1 = 1, + .postdiv2 = 1, + .dsmpd = 1, + }, + { + .freq = 1200000000, + .refdiv = 1, + .fbdiv = 50, + .postdiv1 = 1, + .postdiv2 = 1, + .dsmpd = 1, + }, + { + .freq = 1188000000, + .refdiv = 2, + .fbdiv = 99, + .postdiv1 = 1, + .postdiv2 = 1, + .dsmpd = 1, + }, + { + .freq = 1104000000, + .refdiv = 1, + .fbdiv = 46, + .postdiv1 = 1, + .postdiv2 = 1, + .dsmpd = 1, + }, + { + .freq = 1100000000, + .refdiv = 12, + .fbdiv = 550, + .postdiv1 = 1, + .postdiv2 = 1, + .dsmpd = 1, + }, + { + .freq = 1008000000, + .refdiv = 1, + .fbdiv = 84, + .postdiv1 = 2, + .postdiv2 = 1, + .dsmpd = 1, + }, + { + .freq = 1000000000, + .refdiv = 1, + .fbdiv = 125, + .postdiv1 = 3, + .postdiv2 = 1, + .dsmpd = 1, + }, + { + .freq = 984000000, + .refdiv = 1, + .fbdiv = 82, + .postdiv1 = 2, + .postdiv2 = 1, + .dsmpd = 1, + }, + { + .freq = 960000000, + .refdiv = 1, + .fbdiv = 80, + .postdiv1 = 2, + .postdiv2 = 1, + .dsmpd = 1, + }, + { + .freq = 936000000, + .refdiv = 1, + .fbdiv = 78, + .postdiv1 = 2, + .postdiv2 = 1, + .dsmpd = 1, + }, + { + .freq = 912000000, + .refdiv = 1, + .fbdiv = 76, + .postdiv1 = 2, + .postdiv2 = 1, + .dsmpd = 1, + }, + { + .freq = 900000000, + .refdiv = 4, + .fbdiv = 300, + .postdiv1 = 2, + .postdiv2 = 1, + .dsmpd = 1, + }, + { + .freq = 888000000, + .refdiv = 1, + .fbdiv = 74, + .postdiv1 = 2, + .postdiv2 = 1, + .dsmpd = 1, + }, + { + .freq = 864000000, + .refdiv = 1, + .fbdiv = 72, + .postdiv1 = 2, + .postdiv2 = 1, + .dsmpd = 1, + }, + { + .freq = 840000000, + .refdiv = 1, + .fbdiv = 70, + .postdiv1 = 2, + .postdiv2 = 1, + .dsmpd = 1, + }, + { + .freq = 816000000, + .refdiv = 1, + .fbdiv = 68, + .postdiv1 = 2, + .postdiv2 = 1, + .dsmpd = 1, + }, + { + .freq = 800000000, + .refdiv = 1, + .fbdiv = 100, + .postdiv1 = 3, + .postdiv2 = 1, + .dsmpd = 1, + }, + { + .freq = 700000000, + .refdiv = 6, + .fbdiv = 350, + .postdiv1 = 2, + .postdiv2 = 1, + .dsmpd = 1, + }, + { + .freq = 696000000, + .refdiv = 1, + .fbdiv = 58, + .postdiv1 = 2, + .postdiv2 = 1, + .dsmpd = 1, + }, + { + .freq = 676000000, + .refdiv = 3, + .fbdiv = 169, + .postdiv1 = 2, + .postdiv2 = 1, + .dsmpd = 1, + }, + { + .freq = 600000000, + .refdiv = 1, + .fbdiv = 75, + .postdiv1 = 3, + .postdiv2 = 1, + .dsmpd = 1, + }, + { + .freq = 594000000, + .refdiv = 1, + .fbdiv = 99, + .postdiv1 = 4, + .postdiv2 = 1, + .dsmpd = 1, + }, + { + .freq = 533250000, + .refdiv = 8, + .fbdiv = 711, + .postdiv1 = 4, + .postdiv2 = 1, + .dsmpd = 1, + }, + { + .freq = 504000000, + .refdiv = 1, + .fbdiv = 63, + .postdiv1 = 3, + .postdiv2 = 1, + .dsmpd = 1, + }, + { + .freq = 500000000, + .refdiv = 6, + .fbdiv = 250, + .postdiv1 = 2, + .postdiv2 = 1, + .dsmpd = 1, + }, + { + .freq = 408000000, + .refdiv = 1, + .fbdiv = 68, + .postdiv1 = 2, + .postdiv2 = 2, + .dsmpd = 1, + }, + { + .freq = 312000000, + .refdiv = 1, + .fbdiv = 52, + .postdiv1 = 2, + .postdiv2 = 2, + .dsmpd = 1, + }, + { + .freq = 297000000, + .refdiv = 1, + .fbdiv = 99, + .postdiv1 = 4, + .postdiv2 = 2, + .dsmpd = 1, + }, + { + .freq = 216000000, + .refdiv = 1, + .fbdiv = 72, + .postdiv1 = 4, + .postdiv2 = 2, + .dsmpd = 1, + }, + { + .freq = 148500000, + .refdiv = 1, + .fbdiv = 99, + .postdiv1 = 4, + .postdiv2 = 4, + .dsmpd = 1, + }, + { + .freq = 106500000, + .refdiv = 1, + .fbdiv = 71, + .postdiv1 = 4, + .postdiv2 = 4, + .dsmpd = 1, + }, + { + .freq = 96000000, + .refdiv = 1, + .fbdiv = 64, + .postdiv1 = 4, + .postdiv2 = 4, + .dsmpd = 1, + }, + { + .freq = 74250000, + .refdiv = 2, + .fbdiv = 99, + .postdiv1 = 4, + .postdiv2 = 4, + .dsmpd = 1, + }, + { + .freq = 65000000, + .refdiv = 1, + .fbdiv = 65, + .postdiv1 = 6, + .postdiv2 = 4, + .dsmpd = 1, + }, + { + .freq = 54000000, + .refdiv = 1, + .fbdiv = 54, + .postdiv1 = 6, + .postdiv2 = 4, + .dsmpd = 1, + }, + { + .freq = 27000000, + .refdiv = 1, + .fbdiv = 27, + .postdiv1 = 6, + .postdiv2 = 4, + .dsmpd = 1, + }, + {}, +}; + +static const char *pll_parents[] = {"xin24m"}; + +static struct rk_clk_pll_def ppll = { + .clkdef = { + .id = PLL_PPLL, + .name = "ppll", + .parent_names = pll_parents, + .parent_cnt = nitems(pll_parents), + }, + .base_offset = 0x00, + + .rates = rk3399_pll_rates, +}; + +static const char *pmu_parents[] = {"ppll"}; + +#define PCLK_PMU_SRC 19 + +static struct rk_clk_composite_def pclk_pmu_src = { + .clkdef = { + .id = PCLK_PMU_SRC, + .name = "pclk_pmu_src", + .parent_names = pmu_parents, + .parent_cnt = nitems(pmu_parents), + }, + /* PMUCRU_CLKSEL_CON0 */ + .muxdiv_offset = 0x80, + + .div_shift = 0, + .div_width = 5, +}; + + +#define SCLK_I2C0_PMU 9 +#define SCLK_I2C4_PMU 10 +#define SCLK_I2C8_PMU 11 + +static struct rk_clk_composite_def i2c0 = { + .clkdef = { + .id = SCLK_I2C0_PMU, + .name = "clk_i2c0_pmu", + .parent_names = pmu_parents, + .parent_cnt = nitems(pmu_parents), + }, + /* PMUCRU_CLKSEL_CON2 */ + .muxdiv_offset = 0x88, + + .div_shift = 0, + .div_width = 7, + + /* PMUCRU_CLKGATE_CON0 */ + .gate_offset = 0x100, + .gate_shift = 9, + + .flags = RK_CLK_COMPOSITE_HAVE_GATE, +}; + +static struct rk_clk_composite_def i2c8 = { + .clkdef = { + .id = SCLK_I2C8_PMU, + .name = "clk_i2c8_pmu", + .parent_names = pmu_parents, + .parent_cnt = nitems(pmu_parents), + }, + /* PMUCRU_CLKSEL_CON2 */ + .muxdiv_offset = 0x88, + + .div_shift = 8, + .div_width = 7, + + /* PMUCRU_CLKGATE_CON0 */ + .gate_offset = 0x100, + .gate_shift = 11, + + .flags = RK_CLK_COMPOSITE_HAVE_GATE, +}; + +static struct rk_clk_composite_def i2c4 = { + .clkdef = { + .id = SCLK_I2C4_PMU, + .name = "clk_i2c4_pmu", + .parent_names = pmu_parents, + .parent_cnt = nitems(pmu_parents), + }, + /* PMUCRU_CLKSEL_CON3 */ + .muxdiv_offset = 0x8c, + + .div_shift = 0, + .div_width = 7, + + /* PMUCRU_CLKGATE_CON0 */ + .gate_offset = 0x100, + .gate_shift = 10, + + .flags = RK_CLK_COMPOSITE_HAVE_GATE, +}; + +static struct rk_clk rk3399_pmu_clks[] = { + { + .type = RK3399_CLK_PLL, + .clk.pll = &ppll + }, + + { + .type = RK_CLK_COMPOSITE, + .clk.composite = &pclk_pmu_src + }, + { + .type = RK_CLK_COMPOSITE, + .clk.composite = &i2c0 + }, + { + .type = RK_CLK_COMPOSITE, + .clk.composite = &i2c4 + }, + { + .type = RK_CLK_COMPOSITE, + .clk.composite = &i2c8 + }, +}; + +static int +rk3399_pmucru_probe(device_t dev) +{ + + if (!ofw_bus_status_okay(dev)) + return (ENXIO); + + if (ofw_bus_is_compatible(dev, "rockchip,rk3399-pmucru")) { + device_set_desc(dev, "Rockchip RK3399 PMU Clock and Reset Unit"); + return (BUS_PROBE_DEFAULT); + } + + return (ENXIO); +} + +static int +rk3399_pmucru_attach(device_t dev) +{ + struct rk_cru_softc *sc; + + sc = device_get_softc(dev); + sc->dev = dev; + + sc->gates = rk3399_pmu_gates; + sc->ngates = nitems(rk3399_pmu_gates); + + sc->clks = rk3399_pmu_clks; + sc->nclks = nitems(rk3399_pmu_clks); + + return (rk_cru_attach(dev)); +} + +static device_method_t rk3399_pmucru_methods[] = { + /* Device interface */ + DEVMETHOD(device_probe, rk3399_pmucru_probe), + DEVMETHOD(device_attach, rk3399_pmucru_attach), + + DEVMETHOD_END +}; + +static devclass_t rk3399_pmucru_devclass; + +DEFINE_CLASS_1(rk3399_pmucru, rk3399_pmucru_driver, rk3399_pmucru_methods, + sizeof(struct rk_cru_softc), rk_cru_driver); + +EARLY_DRIVER_MODULE(rk3399_pmucru, simplebus, rk3399_pmucru_driver, + rk3399_pmucru_devclass, 0, 0, BUS_PASS_BUS + BUS_PASS_ORDER_MIDDLE); Property changes on: head/sys/arm64/rockchip/clk/rk3399_pmucru.c ___________________________________________________________________ Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:keywords ## -0,0 +1 ## +FreeBSD=%H \ No newline at end of property Added: svn:mime-type ## -0,0 +1 ## +text/plain \ No newline at end of property Index: head/sys/arm64/rockchip/if_dwc_rk.c =================================================================== --- head/sys/arm64/rockchip/if_dwc_rk.c (revision 341381) +++ head/sys/arm64/rockchip/if_dwc_rk.c (revision 341382) @@ -1,153 +1,182 @@ /*- * SPDX-License-Identifier: BSD-2-Clause-FreeBSD * * Copyright (c) 2018 Emmanuel Vadot * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. */ #include __FBSDID("$FreeBSD$"); #include #include #include #include #include #include #include #include #include #include #include #include #include #include "syscon_if.h" #include "if_dwc_if.h" #define RK3328_GRF_MAC_CON0 0x0900 #define RK3328_GRF_MAC_CON0_TX_MASK 0x7F #define RK3328_GRF_MAC_CON0_TX_SHIFT 0 #define RK3328_GRF_MAC_CON0_RX_MASK 0x7F #define RK3328_GRF_MAC_CON0_RX_SHIFT 7 #define RK3328_GRF_MAC_CON1 0x0904 #define RK3328_GRF_MAC_CON2 0x0908 #define RK3328_GRF_MACPHY_CON0 0x0B00 #define RK3328_GRF_MACPHY_CON1 0x0B04 #define RK3328_GRF_MACPHY_CON2 0x0B08 #define RK3328_GRF_MACPHY_CON3 0x0B0C #define RK3328_GRF_MACPHY_STATUS 0x0B10 static void rk3328_set_delays(struct syscon *grf, phandle_t node) { uint32_t tx, rx; if (OF_getencprop(node, "tx_delay", &tx, sizeof(tx)) <= 0) tx = 0x30; if (OF_getencprop(node, "rx_delay", &rx, sizeof(rx)) <= 0) rx = 0x10; tx = ((tx & RK3328_GRF_MAC_CON0_TX_MASK) << RK3328_GRF_MAC_CON0_TX_SHIFT); rx = ((rx & RK3328_GRF_MAC_CON0_TX_MASK) << RK3328_GRF_MAC_CON0_RX_SHIFT); - /* Disable delays as values conflict between DTS */ - /* SYSCON_WRITE_4(grf, RK3328_GRF_MAC_CON0, tx | rx | 0xFFFF0000); */ + SYSCON_WRITE_4(grf, RK3328_GRF_MAC_CON0, tx | rx | 0xFFFF0000); } +#define RK3399_GRF_SOC_CON6 0xc218 +#define RK3399_GRF_SOC_CON6_TX_MASK 0x7F +#define RK3399_GRF_SOC_CON6_TX_SHIFT 0 +#define RK3399_GRF_SOC_CON6_RX_MASK 0x7F +#define RK3399_GRF_SOC_CON6_RX_SHIFT 8 + +static void +rk3399_set_delays(struct syscon *grf, phandle_t node) +{ + uint32_t tx, rx; + + if (OF_getencprop(node, "tx_delay", &tx, sizeof(tx)) <= 0) + tx = 0x30; + if (OF_getencprop(node, "rx_delay", &rx, sizeof(rx)) <= 0) + rx = 0x10; + + tx = ((tx & RK3399_GRF_SOC_CON6_TX_MASK) << + RK3399_GRF_SOC_CON6_TX_SHIFT); + rx = ((rx & RK3399_GRF_SOC_CON6_TX_MASK) << + RK3399_GRF_SOC_CON6_RX_SHIFT); + + SYSCON_WRITE_4(grf, RK3399_GRF_SOC_CON6, tx | rx | 0xFFFF0000); +} + static int if_dwc_rk_probe(device_t dev) { if (!ofw_bus_status_okay(dev)) return (ENXIO); - if (!ofw_bus_is_compatible(dev, "rockchip,rk3328-gmac")) + if (!(ofw_bus_is_compatible(dev, "rockchip,rk3328-gmac") || + ofw_bus_is_compatible(dev, "rockchip,rk3399-gmac"))) return (ENXIO); device_set_desc(dev, "Rockchip Gigabit Ethernet Controller"); return (BUS_PROBE_DEFAULT); } static int if_dwc_rk_init(device_t dev) { phandle_t node; struct syscon *grf = NULL; node = ofw_bus_get_node(dev); if (OF_hasprop(node, "rockchip,grf") && syscon_get_by_ofw_property(dev, node, "rockchip,grf", &grf) != 0) { device_printf(dev, "cannot get grf driver handle\n"); return (ENXIO); } - rk3328_set_delays(grf, node); +#ifdef notyet + if (ofw_bus_is_compatible(dev, "rockchip,rk3399-gmac")) + rk3399_set_delays(grf, node); + else if (ofw_bus_is_compatible(dev, "rockchip,rk3328-gmac")) + rk3328_set_delays(grf, node); +#endif /* Mode should be set according to dtb property */ return (0); } static int if_dwc_rk_mac_type(device_t dev) { return (DWC_GMAC_ALT_DESC); } static int if_dwc_rk_mii_clk(device_t dev) { /* Should be calculated from the clock */ return (GMAC_MII_CLK_150_250M_DIV102); } static device_method_t if_dwc_rk_methods[] = { DEVMETHOD(device_probe, if_dwc_rk_probe), DEVMETHOD(if_dwc_init, if_dwc_rk_init), DEVMETHOD(if_dwc_mac_type, if_dwc_rk_mac_type), DEVMETHOD(if_dwc_mii_clk, if_dwc_rk_mii_clk), DEVMETHOD_END }; static devclass_t dwc_rk_devclass; extern driver_t dwc_driver; DEFINE_CLASS_1(dwc, dwc_rk_driver, if_dwc_rk_methods, sizeof(struct dwc_softc), dwc_driver); DRIVER_MODULE(dwc_rk, simplebus, dwc_rk_driver, dwc_rk_devclass, 0, 0); MODULE_DEPEND(dwc_rk, dwc, 1, 1, 1); Index: head/sys/arm64/rockchip/rk_grf.c =================================================================== --- head/sys/arm64/rockchip/rk_grf.c (revision 341381) +++ head/sys/arm64/rockchip/rk_grf.c (revision 341382) @@ -1,81 +1,85 @@ /*- * SPDX-License-Identifier: BSD-2-Clause-FreeBSD * * Copyright (c) 2018 Emmanuel Vadot * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. */ #include __FBSDID("$FreeBSD$"); #include #include #include #include #include #include #include #include #include #include #include #include #include "opt_soc.h" static struct ofw_compat_data compat_data[] = { #ifdef SOC_ROCKCHIP_RK3328 {"rockchip,rk3328-grf", 1}, #endif +#ifdef SOC_ROCKCHIP_RK3399 + {"rockchip,rk3399-grf", 1}, + {"rockchip,rk3399-pmugrf", 1}, +#endif {NULL, 0} }; static int rk_grf_probe(device_t dev) { if (!ofw_bus_status_okay(dev)) return (ENXIO); if (ofw_bus_search_compatible(dev, compat_data)->ocd_data == 0) return (ENXIO); device_set_desc(dev, "RockChip General Register Files"); return (BUS_PROBE_DEFAULT); } static device_method_t rk_grf_methods[] = { DEVMETHOD(device_probe, rk_grf_probe), DEVMETHOD_END }; DEFINE_CLASS_1(rk_grf, rk_grf_driver, rk_grf_methods, sizeof(struct syscon_generic_softc), syscon_generic_driver); static devclass_t rk_grf_devclass; EARLY_DRIVER_MODULE(rk_grf, simplebus, rk_grf_driver, rk_grf_devclass, 0, 0, BUS_PASS_BUS + BUS_PASS_ORDER_MIDDLE); MODULE_VERSION(rk_grf, 1); Index: head/sys/arm64/rockchip/rk_pinctrl.c =================================================================== --- head/sys/arm64/rockchip/rk_pinctrl.c (revision 341381) +++ head/sys/arm64/rockchip/rk_pinctrl.c (revision 341382) @@ -1,477 +1,777 @@ /*- * SPDX-License-Identifier: BSD-2-Clause-FreeBSD * * Copyright (c) 2018 Emmanuel Vadot * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. * */ #include __FBSDID("$FreeBSD$"); #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include "syscon_if.h" #include "opt_soc.h" struct rk_pinctrl_pin_drive { + uint32_t bank; + uint32_t subbank; + uint32_t offset; uint32_t value; uint32_t ma; }; struct rk_pinctrl_bank { uint32_t bank_num; uint32_t subbank_num; uint32_t offset; uint32_t nbits; }; struct rk_pinctrl_pin_fixup { uint32_t bank; uint32_t subbank; uint32_t pin; uint32_t reg; uint32_t bit; uint32_t mask; }; +struct rk_pinctrl_softc; + struct rk_pinctrl_conf { struct rk_pinctrl_bank *iomux_conf; uint32_t iomux_nbanks; struct rk_pinctrl_pin_fixup *pin_fixup; uint32_t npin_fixup; struct rk_pinctrl_pin_drive *pin_drive; uint32_t npin_drive; - uint32_t pd_offset; - uint32_t drive_offset; + uint32_t (*get_pd_offset)(struct rk_pinctrl_softc *, uint32_t); + struct syscon *(*get_syscon)(struct rk_pinctrl_softc *, uint32_t); }; struct rk_pinctrl_softc { struct simplebus_softc simplebus_sc; device_t dev; struct syscon *grf; + struct syscon *pmu; struct rk_pinctrl_conf *conf; }; static struct rk_pinctrl_bank rk3328_iomux_bank[] = { { .bank_num = 0, .subbank_num = 0, .offset = 0x00, .nbits = 2, }, { .bank_num = 0, .subbank_num = 1, .offset = 0x04, .nbits = 2, }, { .bank_num = 0, .subbank_num = 2, .offset = 0x08, .nbits = 2, }, { .bank_num = 0, .subbank_num = 3, .offset = 0xc, .nbits = 2, }, { .bank_num = 1, .subbank_num = 0, .offset = 0x10, .nbits = 2, }, { .bank_num = 1, .subbank_num = 1, .offset = 0x14, .nbits = 2, }, { .bank_num = 1, .subbank_num = 2, .offset = 0x18, .nbits = 2, }, { .bank_num = 1, .subbank_num = 3, .offset = 0x1C, .nbits = 2, }, { .bank_num = 2, .subbank_num = 0, .offset = 0x20, .nbits = 2, }, { .bank_num = 2, .subbank_num = 1, .offset = 0x24, .nbits = 3, }, { .bank_num = 2, .subbank_num = 2, .offset = 0x2c, .nbits = 3, }, { .bank_num = 2, .subbank_num = 3, .offset = 0x34, .nbits = 2, }, { .bank_num = 3, .subbank_num = 0, .offset = 0x38, .nbits = 3, }, { .bank_num = 3, .subbank_num = 1, .offset = 0x40, .nbits = 3, }, { .bank_num = 3, .subbank_num = 2, .offset = 0x48, .nbits = 3, }, { .bank_num = 3, .subbank_num = 3, .offset = 0x4c, .nbits = 3, }, }; static struct rk_pinctrl_pin_fixup rk3328_pin_fixup[] = { { .bank = 2, .pin = 12, .reg = 0x24, .bit = 8, .mask = 0x300, }, { .bank = 2, .pin = 15, .reg = 0x28, .bit = 0, .mask = 0x7, }, { .bank = 2, .pin = 23, .reg = 0x30, .bit = 14, .mask = 0x6000, }, }; +#define RK_PINDRIVE(_bank, _subbank, _offset, _value, _ma) \ + { \ + .bank = _bank, \ + .subbank = _subbank, \ + .offset = _offset, \ + .value = _value, \ + .ma = _ma, \ + }, + static struct rk_pinctrl_pin_drive rk3328_pin_drive[] = { + RK_PINDRIVE(0, 0, 0x200, 0, 2) + RK_PINDRIVE(0, 0, 0x200, 1, 4) + RK_PINDRIVE(0, 0, 0x200, 2, 8) + RK_PINDRIVE(0, 0, 0x200, 3, 12) + + RK_PINDRIVE(0, 1, 0x204, 0, 2) + RK_PINDRIVE(0, 1, 0x204, 1, 4) + RK_PINDRIVE(0, 1, 0x204, 2, 8) + RK_PINDRIVE(0, 1, 0x204, 3, 12) + + RK_PINDRIVE(0, 2, 0x208, 0, 2) + RK_PINDRIVE(0, 2, 0x208, 1, 4) + RK_PINDRIVE(0, 2, 0x208, 2, 8) + RK_PINDRIVE(0, 2, 0x208, 3, 12) + + RK_PINDRIVE(0, 3, 0x20C, 0, 2) + RK_PINDRIVE(0, 3, 0x20C, 1, 4) + RK_PINDRIVE(0, 3, 0x20C, 2, 8) + RK_PINDRIVE(0, 3, 0x20C, 3, 12) + + RK_PINDRIVE(1, 0, 0x210, 0, 2) + RK_PINDRIVE(1, 0, 0x210, 1, 4) + RK_PINDRIVE(1, 0, 0x210, 2, 8) + RK_PINDRIVE(1, 0, 0x210, 3, 12) + + RK_PINDRIVE(1, 1, 0x214, 0, 2) + RK_PINDRIVE(1, 1, 0x214, 1, 4) + RK_PINDRIVE(1, 1, 0x214, 2, 8) + RK_PINDRIVE(1, 1, 0x214, 3, 12) + + RK_PINDRIVE(1, 2, 0x218, 0, 2) + RK_PINDRIVE(1, 2, 0x218, 1, 4) + RK_PINDRIVE(1, 2, 0x218, 2, 8) + RK_PINDRIVE(1, 2, 0x218, 3, 12) + + RK_PINDRIVE(1, 3, 0x21C, 0, 2) + RK_PINDRIVE(1, 3, 0x21C, 1, 4) + RK_PINDRIVE(1, 3, 0x21C, 2, 8) + RK_PINDRIVE(1, 3, 0x21C, 3, 12) + + RK_PINDRIVE(2, 0, 0x220, 0, 2) + RK_PINDRIVE(2, 0, 0x220, 1, 4) + RK_PINDRIVE(2, 0, 0x220, 2, 8) + RK_PINDRIVE(2, 0, 0x220, 3, 12) + + RK_PINDRIVE(2, 1, 0x224, 0, 2) + RK_PINDRIVE(2, 1, 0x224, 1, 4) + RK_PINDRIVE(2, 1, 0x224, 2, 8) + RK_PINDRIVE(2, 1, 0x224, 3, 12) + + RK_PINDRIVE(2, 2, 0x228, 0, 2) + RK_PINDRIVE(2, 2, 0x228, 1, 4) + RK_PINDRIVE(2, 2, 0x228, 2, 8) + RK_PINDRIVE(2, 2, 0x228, 3, 12) + + RK_PINDRIVE(2, 3, 0x22C, 0, 2) + RK_PINDRIVE(2, 3, 0x22C, 1, 4) + RK_PINDRIVE(2, 3, 0x22C, 2, 8) + RK_PINDRIVE(2, 3, 0x22C, 3, 12) + + RK_PINDRIVE(3, 0, 0x230, 0, 2) + RK_PINDRIVE(3, 0, 0x230, 1, 4) + RK_PINDRIVE(3, 0, 0x230, 2, 8) + RK_PINDRIVE(3, 0, 0x230, 3, 12) + + RK_PINDRIVE(3, 1, 0x234, 0, 2) + RK_PINDRIVE(3, 1, 0x234, 1, 4) + RK_PINDRIVE(3, 1, 0x234, 2, 8) + RK_PINDRIVE(3, 1, 0x234, 3, 12) + + RK_PINDRIVE(3, 2, 0x238, 0, 2) + RK_PINDRIVE(3, 2, 0x238, 1, 4) + RK_PINDRIVE(3, 2, 0x238, 2, 8) + RK_PINDRIVE(3, 2, 0x238, 3, 12) + + RK_PINDRIVE(3, 3, 0x23C, 0, 2) + RK_PINDRIVE(3, 3, 0x23C, 1, 4) + RK_PINDRIVE(3, 3, 0x23C, 2, 8) + RK_PINDRIVE(3, 3, 0x23C, 3, 12) +}; + +static uint32_t +rk3328_get_pd_offset(struct rk_pinctrl_softc *sc, uint32_t bank) +{ + return (0x100); +} + +static struct syscon * +rk3328_get_syscon(struct rk_pinctrl_softc *sc, uint32_t bank) +{ + return (sc->grf); +} + +struct rk_pinctrl_conf rk3328_conf = { + .iomux_conf = rk3328_iomux_bank, + .iomux_nbanks = nitems(rk3328_iomux_bank), + .pin_fixup = rk3328_pin_fixup, + .npin_fixup = nitems(rk3328_pin_fixup), + .pin_drive = rk3328_pin_drive, + .npin_drive = nitems(rk3328_pin_drive), + .get_pd_offset = rk3328_get_pd_offset, + .get_syscon = rk3328_get_syscon, +}; + +static struct rk_pinctrl_bank rk3399_iomux_bank[] = { { - .value = 0, - .ma = 2, + .bank_num = 0, + .subbank_num = 0, + .offset = 0x00, + .nbits = 2, }, { - .value = 1, - .ma = 4, + .bank_num = 0, + .subbank_num = 1, + .offset = 0x04, + .nbits = 2, }, { - .value = 2, - .ma = 8, + .bank_num = 0, + .subbank_num = 2, + .offset = 0x08, + .nbits = 2, }, { - .value = 3, - .ma = 12, + .bank_num = 0, + .subbank_num = 3, + .offset = 0x0c, + .nbits = 2, }, + { + .bank_num = 1, + .subbank_num = 0, + .offset = 0x10, + .nbits = 2, + }, + { + .bank_num = 1, + .subbank_num = 1, + .offset = 0x14, + .nbits = 2, + }, + { + .bank_num = 1, + .subbank_num = 2, + .offset = 0x18, + .nbits = 2, + }, + { + .bank_num = 1, + .subbank_num = 3, + .offset = 0x1c, + .nbits = 2, + }, + { + .bank_num = 2, + .subbank_num = 0, + .offset = 0xe000, + .nbits = 2, + }, + { + .bank_num = 2, + .subbank_num = 1, + .offset = 0xe004, + .nbits = 2, + }, + { + .bank_num = 2, + .subbank_num = 2, + .offset = 0xe008, + .nbits = 2, + }, + { + .bank_num = 2, + .subbank_num = 3, + .offset = 0xe00c, + .nbits = 2, + }, + { + .bank_num = 3, + .subbank_num = 0, + .offset = 0xe010, + .nbits = 2, + }, + { + .bank_num = 3, + .subbank_num = 1, + .offset = 0xe014, + .nbits = 2, + }, + { + .bank_num = 3, + .subbank_num = 2, + .offset = 0xe018, + .nbits = 2, + }, + { + .bank_num = 3, + .subbank_num = 3, + .offset = 0xe01c, + .nbits = 2, + }, + { + .bank_num = 4, + .subbank_num = 0, + .offset = 0xe020, + .nbits = 2, + }, + { + .bank_num = 4, + .subbank_num = 1, + .offset = 0xe024, + .nbits = 2, + }, + { + .bank_num = 4, + .subbank_num = 2, + .offset = 0xe028, + .nbits = 2, + }, + { + .bank_num = 4, + .subbank_num = 3, + .offset = 0xe02c, + .nbits = 2, + }, }; -struct rk_pinctrl_conf rk3328_conf = { - .iomux_conf = rk3328_iomux_bank, - .iomux_nbanks = nitems(rk3328_iomux_bank), - .pin_fixup = rk3328_pin_fixup, - .npin_fixup = nitems(rk3328_pin_fixup), - .pin_drive = rk3328_pin_drive, - .npin_drive = nitems(rk3328_pin_drive), - .pd_offset = 0x100, - .drive_offset = 0x200, +static struct rk_pinctrl_pin_fixup rk3399_pin_fixup[] = {}; + +static struct rk_pinctrl_pin_drive rk3399_pin_drive[] = { + /* GPIO0A */ + RK_PINDRIVE(0, 0, 0x80, 0, 5) + RK_PINDRIVE(0, 0, 0x80, 1, 10) + RK_PINDRIVE(0, 0, 0x80, 2, 15) + RK_PINDRIVE(0, 0, 0x80, 3, 20) + + /* GPIOB */ + RK_PINDRIVE(0, 1, 0x88, 0, 5) + RK_PINDRIVE(0, 1, 0x88, 1, 10) + RK_PINDRIVE(0, 1, 0x88, 2, 15) + RK_PINDRIVE(0, 1, 0x88, 3, 20) + + /* GPIO1A */ + RK_PINDRIVE(1, 0, 0xA0, 0, 3) + RK_PINDRIVE(1, 0, 0xA0, 1, 6) + RK_PINDRIVE(1, 0, 0xA0, 2, 9) + RK_PINDRIVE(1, 0, 0xA0, 3, 12) + + /* GPIO1B */ + RK_PINDRIVE(1, 1, 0xA8, 0, 3) + RK_PINDRIVE(1, 1, 0xA8, 1, 6) + RK_PINDRIVE(1, 1, 0xA8, 2, 9) + RK_PINDRIVE(1, 1, 0xA8, 3, 12) + + /* GPIO1C */ + RK_PINDRIVE(1, 2, 0xB0, 0, 3) + RK_PINDRIVE(1, 2, 0xB0, 1, 6) + RK_PINDRIVE(1, 2, 0xB0, 2, 9) + RK_PINDRIVE(1, 2, 0xB0, 3, 12) + + /* GPIO1D */ + RK_PINDRIVE(1, 3, 0xB8, 0, 3) + RK_PINDRIVE(1, 3, 0xB8, 1, 6) + RK_PINDRIVE(1, 3, 0xB8, 2, 9) + RK_PINDRIVE(1, 3, 0xB8, 3, 12) }; +static uint32_t +rk3399_get_pd_offset(struct rk_pinctrl_softc *sc, uint32_t bank) +{ + if (bank < 2) + return (0x40); + + return (0xe040); +} + +static struct syscon * +rk3399_get_syscon(struct rk_pinctrl_softc *sc, uint32_t bank) +{ + if (bank < 2) + return (sc->pmu); + + return (sc->grf); +} + +struct rk_pinctrl_conf rk3399_conf = { + .iomux_conf = rk3399_iomux_bank, + .iomux_nbanks = nitems(rk3399_iomux_bank), + .pin_fixup = rk3399_pin_fixup, + .npin_fixup = nitems(rk3399_pin_fixup), + .pin_drive = rk3399_pin_drive, + .npin_drive = nitems(rk3399_pin_drive), + .get_pd_offset = rk3399_get_pd_offset, + .get_syscon = rk3399_get_syscon, +}; + static struct ofw_compat_data compat_data[] = { #ifdef SOC_ROCKCHIP_RK3328 {"rockchip,rk3328-pinctrl", (uintptr_t)&rk3328_conf}, #endif +#ifdef SOC_ROCKCHIP_RK3399 + {"rockchip,rk3399-pinctrl", (uintptr_t)&rk3399_conf}, +#endif {NULL, 0} }; static int rk_pinctrl_parse_bias(phandle_t node) { if (OF_hasprop(node, "bias-disable")) return (0); if (OF_hasprop(node, "bias-pull-up")) return (1); if (OF_hasprop(node, "bias-pull-down")) return (2); return (-1); } static int rk_pinctrl_parse_drive(struct rk_pinctrl_softc *sc, phandle_t node, - uint32_t *drive) + uint32_t bank, uint32_t subbank, uint32_t *drive, uint32_t *offset) { uint32_t value; int i; if (OF_getencprop(node, "drive-strength", &value, sizeof(value)) != 0) return (-1); /* Map to the correct drive value */ - for (i = 0; i < sc->conf->npin_drive; i++) + for (i = 0; i < sc->conf->npin_drive; i++) { + if (sc->conf->pin_drive[i].bank != bank && + sc->conf->pin_drive[i].subbank != subbank) + continue; if (sc->conf->pin_drive[i].ma == value) { *drive = sc->conf->pin_drive[i].value; return (0); } + } return (-1); } static void rk_pinctrl_get_fixup(struct rk_pinctrl_softc *sc, uint32_t bank, uint32_t pin, uint32_t *reg, uint32_t *mask, uint32_t *bit) { int i; for (i = 0; i < sc->conf->npin_fixup; i++) if (sc->conf->pin_fixup[i].bank == bank && sc->conf->pin_fixup[i].pin == pin) { *reg = sc->conf->pin_fixup[i].reg; *mask = sc->conf->pin_fixup[i].mask; *bit = sc->conf->pin_fixup[i].bit; return; } } static void rk_pinctrl_configure_pin(struct rk_pinctrl_softc *sc, uint32_t *pindata) { phandle_t pin_conf; + struct syscon *syscon; uint32_t bank, subbank, pin, function, bias; uint32_t bit, mask, reg, drive; int i; bank = pindata[0]; pin = pindata[1]; function = pindata[2]; pin_conf = OF_node_from_xref(pindata[3]); subbank = pin / 8; for (i = 0; i < sc->conf->iomux_nbanks; i++) if (sc->conf->iomux_conf[i].bank_num == bank && sc->conf->iomux_conf[i].subbank_num == subbank) break; if (i == sc->conf->iomux_nbanks) { device_printf(sc->dev, "Unknown pin %d in bank %d\n", pin, bank); return; } + /* Find syscon */ + syscon = sc->conf->get_syscon(sc, bank); + /* Parse pin function */ reg = sc->conf->iomux_conf[i].offset; switch (sc->conf->iomux_conf[i].nbits) { case 3: if ((pin % 8) >= 5) reg += 4; bit = (pin % 8 % 5) * 3; mask = (0x7 << bit) << 16; break; case 2: default: bit = (pin % 8) * 2; mask = (0x3 << bit) << 16; break; } rk_pinctrl_get_fixup(sc, bank, pin, ®, &mask, &bit); - SYSCON_WRITE_4(sc->grf, reg, function << bit | mask); + SYSCON_WRITE_4(syscon, reg, function << bit | mask); /* Pull-Up/Down */ bias = rk_pinctrl_parse_bias(pin_conf); if (bias >= 0) { - reg = sc->conf->pd_offset; + reg = sc->conf->get_pd_offset(sc, bank); reg += bank * 0x10 + ((pin / 8) * 0x4); bit = (pin % 8) * 2; mask = (0x3 << bit) << 16; - SYSCON_WRITE_4(sc->grf, reg, bias << bit | mask); + SYSCON_WRITE_4(syscon, reg, bias << bit | mask); } /* Drive Strength */ - if (rk_pinctrl_parse_drive(sc, pin_conf, &drive) == 0) { - reg = sc->conf->drive_offset; - - reg += bank * 0x10 + ((pin / 8) * 0x4); + if (rk_pinctrl_parse_drive(sc, pin_conf, bank, subbank, &drive, ®) == 0) { bit = (pin % 8) * 2; mask = (0x3 << bit) << 16; - SYSCON_WRITE_4(sc->grf, reg, bias << bit | mask); + SYSCON_WRITE_4(syscon, reg, bias << bit | mask); } } static int rk_pinctrl_configure_pins(device_t dev, phandle_t cfgxref) { struct rk_pinctrl_softc *sc; phandle_t node; uint32_t *pins; int i, npins; sc = device_get_softc(dev); node = OF_node_from_xref(cfgxref); npins = OF_getencprop_alloc_multi(node, "rockchip,pins", sizeof(*pins), (void **)&pins); if (npins <= 0) return (ENOENT); for (i = 0; i != npins; i += 4) rk_pinctrl_configure_pin(sc, pins + i); return (0); } static int rk_pinctrl_probe(device_t dev) { if (!ofw_bus_status_okay(dev)) return (ENXIO); if (ofw_bus_search_compatible(dev, compat_data)->ocd_data == 0) return (ENXIO); device_set_desc(dev, "RockChip Pinctrl controller"); return (BUS_PROBE_DEFAULT); } static int rk_pinctrl_attach(device_t dev) { struct rk_pinctrl_softc *sc; phandle_t node; device_t cdev; sc = device_get_softc(dev); sc->dev = dev; node = ofw_bus_get_node(dev); if (OF_hasprop(node, "rockchip,grf") && syscon_get_by_ofw_property(dev, node, "rockchip,grf", &sc->grf) != 0) { device_printf(dev, "cannot get grf driver handle\n"); return (ENXIO); + } + + // RK3399 has banks in PMU. RK3328 does not have a PMU. + if (ofw_bus_node_is_compatible(node, "rockchip,rk3399-pinctrl")) { + if (OF_hasprop(node, "rockchip,pmu") && + syscon_get_by_ofw_property(dev, node, + "rockchip,pmu", &sc->pmu) != 0) { + device_printf(dev, "cannot get pmu driver handle\n"); + return (ENXIO); + } } sc->conf = (struct rk_pinctrl_conf *)ofw_bus_search_compatible(dev, compat_data)->ocd_data; fdt_pinctrl_register(dev, "rockchip,pins"); fdt_pinctrl_configure_tree(dev); simplebus_init(dev, node); bus_generic_probe(dev); /* Attach child devices */ for (node = OF_child(node); node > 0; node = OF_peer(node)) { if (!ofw_bus_node_is_compatible(node, "rockchip,gpio-bank")) continue; cdev = simplebus_add_device(dev, node, 0, NULL, -1, NULL); if (cdev != NULL) device_probe_and_attach(cdev); } return (bus_generic_attach(dev)); } static int rk_pinctrl_detach(device_t dev) { return (EBUSY); } static device_method_t rk_pinctrl_methods[] = { /* Device interface */ DEVMETHOD(device_probe, rk_pinctrl_probe), DEVMETHOD(device_attach, rk_pinctrl_attach), DEVMETHOD(device_detach, rk_pinctrl_detach), /* fdt_pinctrl interface */ DEVMETHOD(fdt_pinctrl_configure,rk_pinctrl_configure_pins), DEVMETHOD_END }; static devclass_t rk_pinctrl_devclass; DEFINE_CLASS_1(rk_pinctrl, rk_pinctrl_driver, rk_pinctrl_methods, sizeof(struct rk_pinctrl_softc), simplebus_driver); EARLY_DRIVER_MODULE(rk_pinctrl, simplebus, rk_pinctrl_driver, rk_pinctrl_devclass, 0, 0, BUS_PASS_INTERRUPT + BUS_PASS_ORDER_MIDDLE); MODULE_VERSION(rk_pinctrl, 1); Index: head/sys/conf/files.arm64 =================================================================== --- head/sys/conf/files.arm64 (revision 341381) +++ head/sys/conf/files.arm64 (revision 341382) @@ -1,269 +1,271 @@ # $FreeBSD$ cloudabi32_vdso.o optional compat_cloudabi32 \ dependency "$S/contrib/cloudabi/cloudabi_vdso_armv6_on_64bit.S" \ compile-with "${CC} -x assembler-with-cpp -m32 -shared -nostdinc -nostdlib -Wl,-T$S/compat/cloudabi/cloudabi_vdso.lds $S/contrib/cloudabi/cloudabi_vdso_armv6_on_64bit.S -o ${.TARGET}" \ no-obj no-implicit-rule \ clean "cloudabi32_vdso.o" # cloudabi32_vdso_blob.o optional compat_cloudabi32 \ dependency "cloudabi32_vdso.o" \ compile-with "${OBJCOPY} --input-target binary --output-target elf64-littleaarch64 --binary-architecture aarch64 cloudabi32_vdso.o ${.TARGET}" \ no-implicit-rule \ clean "cloudabi32_vdso_blob.o" # cloudabi64_vdso.o optional compat_cloudabi64 \ dependency "$S/contrib/cloudabi/cloudabi_vdso_aarch64.S" \ compile-with "${CC} -x assembler-with-cpp -shared -nostdinc -nostdlib -Wl,-T$S/compat/cloudabi/cloudabi_vdso.lds $S/contrib/cloudabi/cloudabi_vdso_aarch64.S -o ${.TARGET}" \ no-obj no-implicit-rule \ clean "cloudabi64_vdso.o" # cloudabi64_vdso_blob.o optional compat_cloudabi64 \ dependency "cloudabi64_vdso.o" \ compile-with "${OBJCOPY} --input-target binary --output-target elf64-littleaarch64 --binary-architecture aarch64 cloudabi64_vdso.o ${.TARGET}" \ no-implicit-rule \ clean "cloudabi64_vdso_blob.o" # # Allwinner common files arm/allwinner/a10_ehci.c optional ehci aw_ehci fdt arm/allwinner/a10_timer.c optional a10_timer fdt arm/allwinner/aw_gpio.c optional gpio aw_gpio fdt arm/allwinner/aw_mmc.c optional mmc aw_mmc fdt | mmccam aw_mmc fdt arm/allwinner/aw_nmi.c optional aw_nmi fdt \ compile-with "${NORMAL_C} -I$S/gnu/dts/include" arm/allwinner/aw_rsb.c optional aw_rsb fdt arm/allwinner/aw_rtc.c optional aw_rtc fdt arm/allwinner/aw_sid.c optional aw_sid nvmem fdt arm/allwinner/aw_spi.c optional aw_spi fdt arm/allwinner/aw_syscon.c optional aw_syscon ext_resources syscon fdt arm/allwinner/aw_thermal.c optional aw_thermal nvmem fdt arm/allwinner/aw_usbphy.c optional ehci aw_usbphy fdt arm/allwinner/aw_wdog.c optional aw_wdog fdt arm/allwinner/axp81x.c optional axp81x fdt arm/allwinner/if_awg.c optional awg ext_resources syscon aw_sid nvmem fdt # Allwinner clock driver arm/allwinner/clkng/aw_ccung.c optional aw_ccu fdt arm/allwinner/clkng/aw_clk_nkmp.c optional aw_ccu fdt arm/allwinner/clkng/aw_clk_nm.c optional aw_ccu fdt arm/allwinner/clkng/aw_clk_prediv_mux.c optional aw_ccu fdt arm/allwinner/clkng/ccu_a64.c optional soc_allwinner_a64 aw_ccu fdt arm/allwinner/clkng/ccu_h3.c optional soc_allwinner_h5 aw_ccu fdt arm/allwinner/clkng/ccu_sun8i_r.c optional aw_ccu fdt # Allwinner padconf files arm/allwinner/a64/a64_padconf.c optional soc_allwinner_a64 fdt arm/allwinner/a64/a64_r_padconf.c optional soc_allwinner_a64 fdt arm/allwinner/h3/h3_padconf.c optional soc_allwinner_h5 fdt arm/allwinner/h3/h3_r_padconf.c optional soc_allwinner_h5 fdt arm/annapurna/alpine/alpine_ccu.c optional al_ccu fdt arm/annapurna/alpine/alpine_nb_service.c optional al_nb_service fdt arm/annapurna/alpine/alpine_pci.c optional al_pci fdt arm/annapurna/alpine/alpine_pci_msix.c optional al_pci fdt arm/annapurna/alpine/alpine_serdes.c optional al_serdes fdt \ no-depend \ compile-with "${CC} -c -o ${.TARGET} ${CFLAGS} -I$S/contrib/alpine-hal -I$S/contrib/alpine-hal/eth ${PROF} ${.IMPSRC}" arm/arm/generic_timer.c standard arm/arm/gic.c standard arm/arm/gic_acpi.c optional acpi arm/arm/gic_fdt.c optional fdt arm/arm/pmu.c standard arm/arm/physmem.c standard arm/broadcom/bcm2835/bcm2835_audio.c optional sound vchiq fdt \ compile-with "${NORMAL_C} -DUSE_VCHIQ_ARM -D__VCCOREVER__=0x04000000 -I$S/contrib/vchiq" arm/broadcom/bcm2835/bcm2835_bsc.c optional bcm2835_bsc soc_brcm_bcm2837 fdt arm/broadcom/bcm2835/bcm2835_cpufreq.c optional soc_brcm_bcm2837 fdt arm/broadcom/bcm2835/bcm2835_dma.c optional soc_brcm_bcm2837 fdt arm/broadcom/bcm2835/bcm2835_fbd.c optional vt soc_brcm_bcm2837 fdt arm/broadcom/bcm2835/bcm2835_ft5406.c optional evdev bcm2835_ft5406 soc_brcm_bcm2837 fdt arm/broadcom/bcm2835/bcm2835_gpio.c optional gpio soc_brcm_bcm2837 fdt arm/broadcom/bcm2835/bcm2835_intr.c optional soc_brcm_bcm2837 fdt arm/broadcom/bcm2835/bcm2835_mbox.c optional soc_brcm_bcm2837 fdt arm/broadcom/bcm2835/bcm2835_rng.c optional random soc_brcm_bcm2837 fdt arm/broadcom/bcm2835/bcm2835_sdhci.c optional sdhci soc_brcm_bcm2837 fdt arm/broadcom/bcm2835/bcm2835_sdhost.c optional sdhci soc_brcm_bcm2837 fdt arm/broadcom/bcm2835/bcm2835_spi.c optional bcm2835_spi soc_brcm_bcm2837 fdt arm/broadcom/bcm2835/bcm2835_vcio.c optional soc_brcm_bcm2837 fdt arm/broadcom/bcm2835/bcm2835_wdog.c optional soc_brcm_bcm2837 fdt arm/broadcom/bcm2835/bcm2836.c optional soc_brcm_bcm2837 fdt arm/broadcom/bcm2835/bcm283x_dwc_fdt.c optional dwcotg fdt soc_brcm_bcm2837 arm/mv/armada38x/armada38x_rtc.c optional mv_rtc fdt arm/xilinx/uart_dev_cdnc.c optional uart soc_xilinx_zynq arm64/acpica/acpi_machdep.c optional acpi arm64/acpica/OsdEnvironment.c optional acpi arm64/acpica/acpi_wakeup.c optional acpi arm64/acpica/pci_cfgreg.c optional acpi pci arm64/arm64/autoconf.c standard arm64/arm64/bus_machdep.c standard arm64/arm64/bus_space_asm.S standard arm64/arm64/busdma_bounce.c standard arm64/arm64/busdma_machdep.c standard arm64/arm64/bzero.S standard arm64/arm64/clock.c standard arm64/arm64/copyinout.S standard arm64/arm64/copystr.c standard arm64/arm64/cpu_errata.c standard arm64/arm64/cpufunc_asm.S standard arm64/arm64/db_disasm.c optional ddb arm64/arm64/db_interface.c optional ddb arm64/arm64/db_trace.c optional ddb arm64/arm64/debug_monitor.c optional ddb arm64/arm64/disassem.c optional ddb arm64/arm64/dump_machdep.c standard arm64/arm64/efirt_machdep.c optional efirt arm64/arm64/elf32_machdep.c optional compat_freebsd32 arm64/arm64/elf_machdep.c standard arm64/arm64/exception.S standard arm64/arm64/freebsd32_machdep.c optional compat_freebsd32 arm64/arm64/gicv3_its.c optional intrng fdt arm64/arm64/gic_v3.c standard arm64/arm64/gic_v3_acpi.c optional acpi arm64/arm64/gic_v3_fdt.c optional fdt arm64/arm64/identcpu.c standard arm64/arm64/in_cksum.c optional inet | inet6 arm64/arm64/locore.S standard no-obj arm64/arm64/machdep.c standard arm64/arm64/mem.c standard arm64/arm64/memcpy.S standard arm64/arm64/memmove.S standard arm64/arm64/minidump_machdep.c standard arm64/arm64/mp_machdep.c optional smp arm64/arm64/nexus.c standard arm64/arm64/ofw_machdep.c optional fdt arm64/arm64/pmap.c standard arm64/arm64/stack_machdep.c optional ddb | stack arm64/arm64/support.S standard arm64/arm64/swtch.S standard arm64/arm64/sys_machdep.c standard arm64/arm64/trap.c standard arm64/arm64/uio_machdep.c standard arm64/arm64/uma_machdep.c standard arm64/arm64/undefined.c standard arm64/arm64/unwind.c optional ddb | kdtrace_hooks | stack arm64/arm64/vfp.c standard arm64/arm64/vm_machdep.c standard arm64/cavium/thunder_pcie_fdt.c optional soc_cavm_thunderx pci fdt arm64/cavium/thunder_pcie_pem.c optional soc_cavm_thunderx pci arm64/cavium/thunder_pcie_pem_fdt.c optional soc_cavm_thunderx pci fdt arm64/cavium/thunder_pcie_common.c optional soc_cavm_thunderx pci arm64/cloudabi32/cloudabi32_sysvec.c optional compat_cloudabi32 arm64/cloudabi64/cloudabi64_sysvec.c optional compat_cloudabi64 arm64/coresight/coresight.c standard arm64/coresight/coresight_if.m standard arm64/coresight/coresight-cmd.c standard arm64/coresight/coresight-cpu-debug.c standard arm64/coresight/coresight-dynamic-replicator.c standard arm64/coresight/coresight-etm4x.c standard arm64/coresight/coresight-funnel.c standard arm64/coresight/coresight-tmc.c standard arm64/qualcomm/qcom_gcc.c optional qcom_gcc fdt contrib/vchiq/interface/compat/vchi_bsd.c optional vchiq soc_brcm_bcm2837 \ compile-with "${NORMAL_C} -DUSE_VCHIQ_ARM -D__VCCOREVER__=0x04000000 -I$S/contrib/vchiq" contrib/vchiq/interface/vchiq_arm/vchiq_2835_arm.c optional vchiq soc_brcm_bcm2837 \ compile-with "${NORMAL_C} -Wno-unused -DUSE_VCHIQ_ARM -D__VCCOREVER__=0x04000000 -I$S/contrib/vchiq" contrib/vchiq/interface/vchiq_arm/vchiq_arm.c optional vchiq soc_brcm_bcm2837 \ compile-with "${NORMAL_C} -Wno-unused -DUSE_VCHIQ_ARM -D__VCCOREVER__=0x04000000 -I$S/contrib/vchiq" contrib/vchiq/interface/vchiq_arm/vchiq_connected.c optional vchiq soc_brcm_bcm2837 \ compile-with "${NORMAL_C} -DUSE_VCHIQ_ARM -D__VCCOREVER__=0x04000000 -I$S/contrib/vchiq" contrib/vchiq/interface/vchiq_arm/vchiq_core.c optional vchiq soc_brcm_bcm2837 \ compile-with "${NORMAL_C} -DUSE_VCHIQ_ARM -D__VCCOREVER__=0x04000000 -I$S/contrib/vchiq" contrib/vchiq/interface/vchiq_arm/vchiq_kern_lib.c optional vchiq soc_brcm_bcm2837 \ compile-with "${NORMAL_C} -DUSE_VCHIQ_ARM -D__VCCOREVER__=0x04000000 -I$S/contrib/vchiq" contrib/vchiq/interface/vchiq_arm/vchiq_kmod.c optional vchiq soc_brcm_bcm2837 \ compile-with "${NORMAL_C} -DUSE_VCHIQ_ARM -D__VCCOREVER__=0x04000000 -I$S/contrib/vchiq" contrib/vchiq/interface/vchiq_arm/vchiq_shim.c optional vchiq soc_brcm_bcm2837 \ compile-with "${NORMAL_C} -DUSE_VCHIQ_ARM -D__VCCOREVER__=0x04000000 -I$S/contrib/vchiq" contrib/vchiq/interface/vchiq_arm/vchiq_util.c optional vchiq soc_brcm_bcm2837 \ compile-with "${NORMAL_C} -DUSE_VCHIQ_ARM -D__VCCOREVER__=0x04000000 -I$S/contrib/vchiq" crypto/armv8/armv8_crypto.c optional armv8crypto armv8_crypto_wrap.o optional armv8crypto \ dependency "$S/crypto/armv8/armv8_crypto_wrap.c" \ compile-with "${CC} -c ${CFLAGS:C/^-O2$/-O3/:N-nostdinc:N-mgeneral-regs-only} -I$S/crypto/armv8/ ${WERROR} ${NO_WCAST_QUAL} ${PROF} -march=armv8-a+crypto ${.IMPSRC}" \ no-implicit-rule \ clean "armv8_crypto_wrap.o" crypto/blowfish/bf_enc.c optional crypto | ipsec | ipsec_support crypto/des/des_enc.c optional crypto | ipsec | ipsec_support | netsmb dev/acpica/acpi_bus_if.m optional acpi dev/acpica/acpi_if.m optional acpi dev/acpica/acpi_pci_link.c optional acpi pci dev/acpica/acpi_pcib.c optional acpi pci dev/ahci/ahci_generic.c optional ahci dev/axgbe/if_axgbe.c optional axgbe dev/axgbe/xgbe-desc.c optional axgbe dev/axgbe/xgbe-dev.c optional axgbe dev/axgbe/xgbe-drv.c optional axgbe dev/axgbe/xgbe-mdio.c optional axgbe dev/cpufreq/cpufreq_dt.c optional cpufreq fdt dev/iicbus/twsi/a10_twsi.c optional twsi fdt dev/iicbus/twsi/twsi.c optional twsi fdt dev/hwpmc/hwpmc_arm64.c optional hwpmc dev/hwpmc/hwpmc_arm64_md.c optional hwpmc dev/mbox/mbox_if.m optional soc_brcm_bcm2837 dev/mmc/host/dwmmc.c optional dwmmc fdt dev/mmc/host/dwmmc_hisi.c optional dwmmc fdt soc_hisi_hi6220 dev/mmc/host/dwmmc_rockchip.c optional dwmmc fdt soc_rockchip_rk3328 dev/neta/if_mvneta_fdt.c optional neta fdt dev/neta/if_mvneta.c optional neta mdio mii dev/ofw/ofw_cpu.c optional fdt dev/ofw/ofwpci.c optional fdt pci dev/pci/pci_host_generic.c optional pci dev/pci/pci_host_generic_acpi.c optional pci acpi dev/pci/pci_host_generic_fdt.c optional pci fdt dev/psci/psci.c standard dev/psci/psci_arm64.S standard dev/psci/smccc.c standard dev/sdhci/sdhci_xenon.c optional sdhci_xenon sdhci fdt dev/uart/uart_cpu_arm64.c optional uart dev/uart/uart_dev_mu.c optional uart uart_mu dev/uart/uart_dev_pl011.c optional uart pl011 dev/usb/controller/dwc_otg_hisi.c optional dwcotg fdt soc_hisi_hi6220 dev/usb/controller/ehci_mv.c optional ehci_mv fdt dev/usb/controller/generic_ehci.c optional ehci acpi dev/usb/controller/generic_ohci.c optional ohci fdt dev/usb/controller/generic_usb_if.m optional ohci fdt dev/usb/controller/xhci_mv.c optional xhci_mv fdt dev/vnic/mrml_bridge.c optional vnic fdt dev/vnic/nic_main.c optional vnic pci dev/vnic/nicvf_main.c optional vnic pci pci_iov dev/vnic/nicvf_queues.c optional vnic pci pci_iov dev/vnic/thunder_bgx_fdt.c optional vnic fdt dev/vnic/thunder_bgx.c optional vnic pci dev/vnic/thunder_mdio_fdt.c optional vnic fdt dev/vnic/thunder_mdio.c optional vnic dev/vnic/lmac_if.m optional inet | inet6 | vnic kern/kern_clocksource.c standard kern/msi_if.m optional intrng kern/pic_if.m optional intrng kern/subr_devmap.c standard kern/subr_intr.c optional intrng libkern/bcmp.c standard libkern/ffs.c standard libkern/ffsl.c standard libkern/ffsll.c standard libkern/fls.c standard libkern/flsl.c standard libkern/flsll.c standard libkern/memcmp.c standard libkern/memset.c standard libkern/arm64/crc32c_armv8.S standard cddl/contrib/opensolaris/common/atomic/aarch64/opensolaris_atomic.S optional zfs | dtrace compile-with "${CDDL_C}" cddl/dev/dtrace/aarch64/dtrace_asm.S optional dtrace compile-with "${DTRACE_S}" cddl/dev/dtrace/aarch64/dtrace_subr.c optional dtrace compile-with "${DTRACE_C}" cddl/dev/fbt/aarch64/fbt_isa.c optional dtrace_fbt | dtraceall compile-with "${FBT_C}" -arm64/rockchip/rk_i2c.c optional rk_i2c fdt soc_rockchip_rk3328 +arm64/rockchip/rk_i2c.c optional rk_i2c fdt soc_rockchip_rk3328 soc_rockchip_rk3399 arm64/rockchip/rk805.c optional rk805 fdt soc_rockchip_rk3328 -arm64/rockchip/rk_grf.c optional fdt soc_rockchip_rk3328 -arm64/rockchip/rk_pinctrl.c optional fdt soc_rockchip_rk3328 -arm64/rockchip/rk_gpio.c optional fdt soc_rockchip_rk3328 -arm64/rockchip/clk/rk_cru.c optional fdt soc_rockchip_rk3328 -arm64/rockchip/clk/rk_clk_armclk.c optional fdt soc_rockchip_rk3328 -arm64/rockchip/clk/rk_clk_composite.c optional fdt soc_rockchip_rk3328 -arm64/rockchip/clk/rk_clk_gate.c optional fdt soc_rockchip_rk3328 -arm64/rockchip/clk/rk_clk_mux.c optional fdt soc_rockchip_rk3328 -arm64/rockchip/clk/rk_clk_pll.c optional fdt soc_rockchip_rk3328 +arm64/rockchip/rk_grf.c optional fdt soc_rockchip_rk3328 soc_rockchip_rk3399 +arm64/rockchip/rk_pinctrl.c optional fdt soc_rockchip_rk3328 soc_rockchip_rk3399 +arm64/rockchip/rk_gpio.c optional fdt soc_rockchip_rk3328 soc_rockchip_rk3399 +arm64/rockchip/clk/rk_cru.c optional fdt soc_rockchip_rk3328 soc_rockchip_rk3399 +arm64/rockchip/clk/rk_clk_armclk.c optional fdt soc_rockchip_rk3328 soc_rockchip_rk3399 +arm64/rockchip/clk/rk_clk_composite.c optional fdt soc_rockchip_rk3328 soc_rockchip_rk3399 +arm64/rockchip/clk/rk_clk_gate.c optional fdt soc_rockchip_rk3328 soc_rockchip_rk3399 +arm64/rockchip/clk/rk_clk_mux.c optional fdt soc_rockchip_rk3328 soc_rockchip_rk3399 +arm64/rockchip/clk/rk_clk_pll.c optional fdt soc_rockchip_rk3328 soc_rockchip_rk3399 arm64/rockchip/clk/rk3328_cru.c optional fdt soc_rockchip_rk3328 -arm64/rockchip/if_dwc_rk.c optional dwc_rk fdt soc_rockchip_rk3328 +arm64/rockchip/clk/rk3399_cru.c optional fdt soc_rockchip_rk3399 +arm64/rockchip/clk/rk3399_pmucru.c optional fdt soc_rockchip_rk3399 +arm64/rockchip/if_dwc_rk.c optional dwc_rk fdt soc_rockchip_rk3328 soc_rockchip_rk3399 dev/dwc/if_dwc.c optional dwc_rk dev/dwc/if_dwc_if.m optional dwc_rk Index: head/sys/conf/options.arm64 =================================================================== --- head/sys/conf/options.arm64 (revision 341381) +++ head/sys/conf/options.arm64 (revision 341382) @@ -1,23 +1,24 @@ # $FreeBSD$ ARM64 opt_global.h INTRNG opt_global.h SOCDEV_PA opt_global.h SOCDEV_VA opt_global.h THUNDERX_PASS_1_1_ERRATA opt_global.h VFP opt_global.h # Binary compatibility COMPAT_FREEBSD32 opt_global.h # EFI Runtime services support EFIRT opt_efirt.h # SoC Support SOC_ALLWINNER_A64 opt_soc.h SOC_ALLWINNER_H5 opt_soc.h SOC_BRCM_BCM2837 opt_soc.h SOC_CAVM_THUNDERX opt_soc.h SOC_HISI_HI6220 opt_soc.h SOC_ROCKCHIP_RK3328 opt_soc.h +SOC_ROCKCHIP_RK3399 opt_soc.h SOC_XILINX_ZYNQ opt_soc.h