Index: head/lib/libpmc/libpmc_pmu_util.c =================================================================== --- head/lib/libpmc/libpmc_pmu_util.c (revision 340107) +++ head/lib/libpmc/libpmc_pmu_util.c (revision 340108) @@ -1,598 +1,621 @@ /*- * SPDX-License-Identifier: BSD-2-Clause-FreeBSD * * Copyright (c) 2018, Matthew Macy * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. * * $FreeBSD$ * */ #include #include #include #include #include #include #include #include #include #include #include #include "pmu-events/pmu-events.h" #if defined(__amd64__) || defined(__i386__) struct pmu_alias { const char *pa_alias; const char *pa_name; }; typedef enum { PMU_INVALID, PMU_INTEL, PMU_AMD, } pmu_mfr_t; static struct pmu_alias pmu_intel_alias_table[] = { {"UNHALTED_CORE_CYCLES", "CPU_CLK_UNHALTED.THREAD_P_ANY"}, {"UNHALTED-CORE-CYCLES", "CPU_CLK_UNHALTED.THREAD_P_ANY"}, {"LLC_MISSES", "LONGEST_LAT_CACHE.MISS"}, {"LLC-MISSES", "LONGEST_LAT_CACHE.MISS"}, {"LLC_REFERENCE", "LONGEST_LAT_CACHE.REFERENCE"}, {"LLC-REFERENCE", "LONGEST_LAT_CACHE.REFERENCE"}, {"LLC_MISS_RHITM", "mem_load_l3_miss_retired.remote_hitm"}, {"LLC-MISS-RHITM", "mem_load_l3_miss_retired.remote_hitm"}, {"RESOURCE_STALL", "RESOURCE_STALLS.ANY"}, {"RESOURCE_STALLS_ANY", "RESOURCE_STALLS.ANY"}, {"BRANCH_INSTRUCTION_RETIRED", "BR_INST_RETIRED.ALL_BRANCHES"}, {"BRANCH-INSTRUCTION-RETIRED", "BR_INST_RETIRED.ALL_BRANCHES"}, {"BRANCH_MISSES_RETIRED", "BR_MISP_RETIRED.ALL_BRANCHES"}, {"BRANCH-MISSES-RETIRED", "BR_MISP_RETIRED.ALL_BRANCHES"}, {"cycles", "tsc-tsc"}, {"instructions", "inst-retired.any_p"}, {"branch-mispredicts", "br_misp_retired.all_branches"}, {"branches", "br_inst_retired.all_branches"}, {"interrupts", "hw_interrupts.received"}, {"ic-misses", "frontend_retired.l1i_miss"}, {NULL, NULL}, }; static struct pmu_alias pmu_amd_alias_table[] = { {"UNHALTED_CORE_CYCLES", "ls_not_halted_cyc"}, {"UNHALTED-CORE-CYCLES", "ls_not_halted_cyc"}, {NULL, NULL}, }; static pmu_mfr_t pmu_events_mfr(void) { char *buf; size_t s; pmu_mfr_t mfr; if (sysctlbyname("kern.hwpmc.cpuid", (void *)NULL, &s, (void *)NULL, 0) == -1) return (PMU_INVALID); if ((buf = malloc(s + 1)) == NULL) return (PMU_INVALID); if (sysctlbyname("kern.hwpmc.cpuid", buf, &s, (void *)NULL, 0) == -1) { free(buf); return (PMU_INVALID); } if (strcasestr(buf, "AuthenticAMD") != NULL) mfr = PMU_AMD; else if (strcasestr(buf, "GenuineIntel") != NULL) mfr = PMU_INTEL; else mfr = PMU_INVALID; free(buf); return (mfr); } /* * The Intel fixed mode counters are: * "inst_retired.any", * "cpu_clk_unhalted.thread", * "cpu_clk_unhalted.thread_any", * "cpu_clk_unhalted.ref_tsc", * */ static const char * pmu_alias_get(const char *name) { pmu_mfr_t mfr; struct pmu_alias *pa; struct pmu_alias *pmu_alias_table; if ((mfr = pmu_events_mfr()) == PMU_INVALID) return (name); if (mfr == PMU_AMD) pmu_alias_table = pmu_amd_alias_table; else if (mfr == PMU_INTEL) pmu_alias_table = pmu_intel_alias_table; else return (name); for (pa = pmu_alias_table; pa->pa_alias != NULL; pa++) if (strcasecmp(name, pa->pa_alias) == 0) return (pa->pa_name); return (name); } struct pmu_event_desc { uint64_t ped_period; uint64_t ped_offcore_rsp; + uint64_t ped_l3_thread; + uint64_t ped_l3_slice; uint32_t ped_event; uint32_t ped_frontend; uint32_t ped_ldlat; uint32_t ped_config1; int16_t ped_umask; uint8_t ped_cmask; uint8_t ped_any; uint8_t ped_inv; uint8_t ped_edge; uint8_t ped_fc_mask; uint8_t ped_ch_mask; }; static const struct pmu_events_map * pmu_events_map_get(const char *cpuid) { size_t s; char buf[64]; const struct pmu_events_map *pme; if (cpuid != NULL) { memcpy(buf, cpuid, 64); } else { if (sysctlbyname("kern.hwpmc.cpuid", (void *)NULL, &s, (void *)NULL, 0) == -1) return (NULL); if (sysctlbyname("kern.hwpmc.cpuid", buf, &s, (void *)NULL, 0) == -1) return (NULL); } for (pme = pmu_events_map; pme->cpuid != NULL; pme++) if (strcmp(buf, pme->cpuid) == 0) return (pme); return (NULL); } static const struct pmu_event * pmu_event_get(const char *cpuid, const char *event_name, int *idx) { const struct pmu_events_map *pme; const struct pmu_event *pe; int i; if ((pme = pmu_events_map_get(cpuid)) == NULL) return (NULL); for (i = 0, pe = pme->table; pe->name || pe->desc || pe->event; pe++, i++) { if (pe->name == NULL) continue; if (strcasecmp(pe->name, event_name) == 0) { if (idx) *idx = i; return (pe); } } return (NULL); } int pmc_pmu_idx_get_by_event(const char *cpuid, const char *event) { int idx; const char *realname; realname = pmu_alias_get(event); if (pmu_event_get(cpuid, realname, &idx) == NULL) return (-1); return (idx); } const char * pmc_pmu_event_get_by_idx(const char *cpuid, int idx) { const struct pmu_events_map *pme; if ((pme = pmu_events_map_get(cpuid)) == NULL) return (NULL); assert(pme->table[idx].name); return (pme->table[idx].name); } static int pmu_parse_event(struct pmu_event_desc *ped, const char *eventin) { char *event; char *kvp, *key, *value, *r; char *debug; if ((event = strdup(eventin)) == NULL) return (ENOMEM); r = event; bzero(ped, sizeof(*ped)); ped->ped_period = DEFAULT_SAMPLE_COUNT; ped->ped_umask = -1; while ((kvp = strsep(&event, ",")) != NULL) { key = strsep(&kvp, "="); if (key == NULL) abort(); value = kvp; if (strcmp(key, "umask") == 0) ped->ped_umask = strtol(value, NULL, 16); else if (strcmp(key, "event") == 0) ped->ped_event = strtol(value, NULL, 16); else if (strcmp(key, "period") == 0) ped->ped_period = strtol(value, NULL, 10); else if (strcmp(key, "offcore_rsp") == 0) ped->ped_offcore_rsp = strtol(value, NULL, 16); else if (strcmp(key, "any") == 0) ped->ped_any = strtol(value, NULL, 10); else if (strcmp(key, "cmask") == 0) ped->ped_cmask = strtol(value, NULL, 10); else if (strcmp(key, "inv") == 0) ped->ped_inv = strtol(value, NULL, 10); else if (strcmp(key, "edge") == 0) ped->ped_edge = strtol(value, NULL, 10); else if (strcmp(key, "frontend") == 0) ped->ped_frontend = strtol(value, NULL, 16); else if (strcmp(key, "ldlat") == 0) ped->ped_ldlat = strtol(value, NULL, 16); else if (strcmp(key, "fc_mask") == 0) ped->ped_fc_mask = strtol(value, NULL, 16); else if (strcmp(key, "ch_mask") == 0) ped->ped_ch_mask = strtol(value, NULL, 16); else if (strcmp(key, "config1") == 0) ped->ped_config1 = strtol(value, NULL, 16); + else if (strcmp(key, "l3_thread_mask") == 0) + ped->ped_l3_thread = strtol(value, NULL, 16); + else if (strcmp(key, "l3_slice_mask") == 0) + ped->ped_l3_slice = strtol(value, NULL, 16); else { debug = getenv("PMUDEBUG"); if (debug != NULL && strcmp(debug, "true") == 0 && value != NULL) printf("unrecognized kvpair: %s:%s\n", key, value); } } free(r); return (0); } uint64_t pmc_pmu_sample_rate_get(const char *event_name) { const struct pmu_event *pe; struct pmu_event_desc ped; event_name = pmu_alias_get(event_name); if ((pe = pmu_event_get(NULL, event_name, NULL)) == NULL) return (DEFAULT_SAMPLE_COUNT); if (pe->alias && (pe = pmu_event_get(NULL, pe->alias, NULL)) == NULL) return (DEFAULT_SAMPLE_COUNT); if (pe->event == NULL) return (DEFAULT_SAMPLE_COUNT); if (pmu_parse_event(&ped, pe->event)) return (DEFAULT_SAMPLE_COUNT); return (ped.ped_period); } int pmc_pmu_enabled(void) { return (pmu_events_map_get(NULL) != NULL); } void pmc_pmu_print_counters(const char *event_name) { const struct pmu_events_map *pme; const struct pmu_event *pe; struct pmu_event_desc ped; char *debug; int do_debug; debug = getenv("PMUDEBUG"); do_debug = 0; if (debug != NULL && strcmp(debug, "true") == 0) do_debug = 1; if ((pme = pmu_events_map_get(NULL)) == NULL) return; for (pe = pme->table; pe->name || pe->desc || pe->event; pe++) { if (pe->name == NULL) continue; if (event_name != NULL && strcasestr(pe->name, event_name) == NULL) continue; printf("\t%s\n", pe->name); if (do_debug) pmu_parse_event(&ped, pe->event); } } void pmc_pmu_print_counter_desc(const char *ev) { const struct pmu_events_map *pme; const struct pmu_event *pe; if ((pme = pmu_events_map_get(NULL)) == NULL) return; for (pe = pme->table; pe->name || pe->desc || pe->event; pe++) { if (pe->name == NULL) continue; if (strcasestr(pe->name, ev) != NULL && pe->desc != NULL) printf("%s:\t%s\n", pe->name, pe->desc); } } void pmc_pmu_print_counter_desc_long(const char *ev) { const struct pmu_events_map *pme; const struct pmu_event *pe; if ((pme = pmu_events_map_get(NULL)) == NULL) return; for (pe = pme->table; pe->name || pe->desc || pe->event; pe++) { if (pe->name == NULL) continue; if (strcasestr(pe->name, ev) != NULL) { if (pe->long_desc != NULL) printf("%s:\n%s\n", pe->name, pe->long_desc); else if (pe->desc != NULL) printf("%s:\t%s\n", pe->name, pe->desc); } } } void pmc_pmu_print_counter_full(const char *ev) { const struct pmu_events_map *pme; const struct pmu_event *pe; if ((pme = pmu_events_map_get(NULL)) == NULL) return; for (pe = pme->table; pe->name || pe->desc || pe->event; pe++) { if (pe->name == NULL) continue; if (strcasestr(pe->name, ev) == NULL) continue; printf("name: %s\n", pe->name); if (pe->long_desc != NULL) printf("desc: %s\n", pe->long_desc); else if (pe->desc != NULL) printf("desc: %s\n", pe->desc); if (pe->event != NULL) printf("event: %s\n", pe->event); if (pe->topic != NULL) printf("topic: %s\n", pe->topic); if (pe->pmu != NULL) printf("pmu: %s\n", pe->pmu); if (pe->unit != NULL) printf("unit: %s\n", pe->unit); if (pe->perpkg != NULL) printf("perpkg: %s\n", pe->perpkg); if (pe->metric_expr != NULL) printf("metric_expr: %s\n", pe->metric_expr); if (pe->metric_name != NULL) printf("metric_name: %s\n", pe->metric_name); if (pe->metric_group != NULL) printf("metric_group: %s\n", pe->metric_group); } } static int -pmc_pmu_amd_pmcallocate(const char *event_name __unused, struct pmc_op_pmcallocate *pm, +pmc_pmu_amd_pmcallocate(const char *event_name, struct pmc_op_pmcallocate *pm, struct pmu_event_desc *ped) { struct pmc_md_amd_op_pmcallocate *amd; + const struct pmu_event *pe; + int idx = -1; amd = &pm->pm_md.pm_amd; - amd->pm_amd_config = AMD_PMC_TO_EVENTMASK(ped->ped_event); if (ped->ped_umask > 0) { pm->pm_caps |= PMC_CAP_QUALIFIER; amd->pm_amd_config |= AMD_PMC_TO_UNITMASK(ped->ped_umask); } pm->pm_class = PMC_CLASS_K8; + pe = pmu_event_get(NULL, event_name, &idx); - if ((pm->pm_caps & (PMC_CAP_USER|PMC_CAP_SYSTEM)) == 0 || - (pm->pm_caps & (PMC_CAP_USER|PMC_CAP_SYSTEM)) == - (PMC_CAP_USER|PMC_CAP_SYSTEM)) - amd->pm_amd_config |= (AMD_PMC_USR | AMD_PMC_OS); - else if (pm->pm_caps & PMC_CAP_USER) - amd->pm_amd_config |= AMD_PMC_USR; - else if (pm->pm_caps & PMC_CAP_SYSTEM) - amd->pm_amd_config |= AMD_PMC_OS; - if (ped->ped_edge) - amd->pm_amd_config |= AMD_PMC_EDGE; - if (ped->ped_inv) - amd->pm_amd_config |= AMD_PMC_EDGE; - if (pm->pm_caps & PMC_CAP_INTERRUPT) - amd->pm_amd_config |= AMD_PMC_INT; + if (strcmp("l3cache", pe->topic) == 0){ + amd->pm_amd_config |= AMD_PMC_TO_EVENTMASK(ped->ped_event); + amd->pm_amd_sub_class = PMC_AMD_SUB_CLASS_L3_CACHE; + amd->pm_amd_config |= AMD_PMC_TO_L3SLICE(ped->ped_l3_slice); + amd->pm_amd_config |= AMD_PMC_TO_L3CORE(ped->ped_l3_thread); + } + else if (strcmp("data fabric", pe->topic) == 0){ + + amd->pm_amd_config |= AMD_PMC_TO_EVENTMASK_DF(ped->ped_event); + amd->pm_amd_sub_class = PMC_AMD_SUB_CLASS_DATA_FABRIC; + } + else{ + amd->pm_amd_config |= AMD_PMC_TO_EVENTMASK(ped->ped_event); + amd->pm_amd_sub_class = PMC_AMD_SUB_CLASS_CORE; + if ((pm->pm_caps & (PMC_CAP_USER|PMC_CAP_SYSTEM)) == 0 || + (pm->pm_caps & (PMC_CAP_USER|PMC_CAP_SYSTEM)) == + (PMC_CAP_USER|PMC_CAP_SYSTEM)) + amd->pm_amd_config |= (AMD_PMC_USR | AMD_PMC_OS); + else if (pm->pm_caps & PMC_CAP_USER) + amd->pm_amd_config |= AMD_PMC_USR; + else if (pm->pm_caps & PMC_CAP_SYSTEM) + amd->pm_amd_config |= AMD_PMC_OS; + if (ped->ped_edge) + amd->pm_amd_config |= AMD_PMC_EDGE; + if (ped->ped_inv) + amd->pm_amd_config |= AMD_PMC_EDGE; + if (pm->pm_caps & PMC_CAP_INTERRUPT) + amd->pm_amd_config |= AMD_PMC_INT; + } return (0); } static int pmc_pmu_intel_pmcallocate(const char *event_name, struct pmc_op_pmcallocate *pm, struct pmu_event_desc *ped) { struct pmc_md_iap_op_pmcallocate *iap; int isfixed; isfixed = 0; iap = &pm->pm_md.pm_iap; if (strcasestr(event_name, "UNC_") == event_name || strcasestr(event_name, "uncore") != NULL) { pm->pm_class = PMC_CLASS_UCP; pm->pm_caps |= PMC_CAP_QUALIFIER; } else if ((ped->ped_umask == -1) || (ped->ped_event == 0x0 && ped->ped_umask == 0x3)) { pm->pm_class = PMC_CLASS_IAF; } else { pm->pm_class = PMC_CLASS_IAP; pm->pm_caps |= PMC_CAP_QUALIFIER; } iap->pm_iap_config |= IAP_EVSEL(ped->ped_event); if (ped->ped_umask > 0) iap->pm_iap_config |= IAP_UMASK(ped->ped_umask); iap->pm_iap_config |= IAP_CMASK(ped->ped_cmask); iap->pm_iap_rsp = ped->ped_offcore_rsp; if ((pm->pm_caps & (PMC_CAP_USER|PMC_CAP_SYSTEM)) == 0 || (pm->pm_caps & (PMC_CAP_USER|PMC_CAP_SYSTEM)) == (PMC_CAP_USER|PMC_CAP_SYSTEM)) iap->pm_iap_config |= (IAP_USR | IAP_OS); else if (pm->pm_caps & PMC_CAP_USER) iap->pm_iap_config |= IAP_USR; else if (pm->pm_caps & PMC_CAP_SYSTEM) iap->pm_iap_config |= IAP_OS; if (ped->ped_edge) iap->pm_iap_config |= IAP_EDGE; if (ped->ped_any) iap->pm_iap_config |= IAP_ANY; if (ped->ped_inv) iap->pm_iap_config |= IAP_EDGE; if (pm->pm_caps & PMC_CAP_INTERRUPT) iap->pm_iap_config |= IAP_INT; return (0); } int pmc_pmu_pmcallocate(const char *event_name, struct pmc_op_pmcallocate *pm) { const struct pmu_event *pe; struct pmu_event_desc ped; pmu_mfr_t mfr; int idx = -1; if ((mfr = pmu_events_mfr()) == PMU_INVALID) return (ENOENT); bzero(&pm->pm_md, sizeof(pm->pm_md)); pm->pm_caps |= (PMC_CAP_READ | PMC_CAP_WRITE); event_name = pmu_alias_get(event_name); if ((pe = pmu_event_get(NULL, event_name, &idx)) == NULL) return (ENOENT); if (pe->alias && (pe = pmu_event_get(NULL, pe->alias, &idx)) == NULL) return (ENOENT); assert(idx >= 0); pm->pm_ev = idx; if (pe->event == NULL) return (ENOENT); if (pmu_parse_event(&ped, pe->event)) return (ENOENT); if (mfr == PMU_INTEL) return (pmc_pmu_intel_pmcallocate(event_name, pm, &ped)); else return (pmc_pmu_amd_pmcallocate(event_name, pm, &ped)); } /* * Ultimately rely on AMD calling theirs the same */ static const char *stat_mode_cntrs[] = { "cpu_clk_unhalted.thread", "inst_retired.any", "br_inst_retired.all_branches", "br_misp_retired.all_branches", "longest_lat_cache.reference", "longest_lat_cache.miss", }; int pmc_pmu_stat_mode(const char ***cntrs) { if (pmc_pmu_enabled()) { *cntrs = stat_mode_cntrs; return (0); } return (EOPNOTSUPP); } #else uint64_t pmc_pmu_sample_rate_get(const char *event_name __unused) { return (DEFAULT_SAMPLE_COUNT); } void pmc_pmu_print_counters(const char *event_name __unused) { } void pmc_pmu_print_counter_desc(const char *e __unused) { } void pmc_pmu_print_counter_desc_long(const char *e __unused) { } void pmc_pmu_print_counter_full(const char *e __unused) { } int pmc_pmu_enabled(void) { return (0); } int pmc_pmu_pmcallocate(const char *e __unused, struct pmc_op_pmcallocate *p __unused) { return (EOPNOTSUPP); } const char * pmc_pmu_event_get_by_idx(const char *c __unused, int idx __unused) { return (NULL); } int pmc_pmu_stat_mode(const char ***a __unused) { return (EOPNOTSUPP); } int pmc_pmu_idx_get_by_event(const char *c __unused, const char *e __unused) { return (-1); } #endif Index: head/lib/libpmc/pmu-events/arch/x86/amdfam17h/data-fabric.json =================================================================== --- head/lib/libpmc/pmu-events/arch/x86/amdfam17h/data-fabric.json (nonexistent) +++ head/lib/libpmc/pmu-events/arch/x86/amdfam17h/data-fabric.json (revision 340108) @@ -0,0 +1,2668 @@ +[ + { + "EventName": "df_ccm_reqa.Node0.anydram", + "EventCode": "0x8B", + "BriefDescription": "Data Fabric CCM Performance Monitor Event DF CCM Request Any DRAM transaction", + "UMask": "0x0F" + }, + { + "EventName": "df_ccm_reqa.Node1.anydram", + "EventCode": "0x8B", + "BriefDescription": "Data Fabric CCM Performance Monitor Event DF CCM Request Any DRAM transaction", + "UMask": "0x2F" + }, + { + "EventName": "df_ccm_reqa.Node2.anydram", + "EventCode": "0x8B", + "BriefDescription": "Data Fabric CCM Performance Monitor Event DF CCM Request Any DRAM transaction", + "UMask": "0x4F" + }, + { + "EventName": "df_ccm_reqa.Node3.anydram", + "EventCode": "0x8B", + "BriefDescription": "Data Fabric CCM Performance Monitor Event DF CCM Request Any DRAM transaction", + "UMask": "0x6F" + }, + { + "EventName": "df_ccm_reqa.Node4.anydram", + "EventCode": "0x8B", + "BriefDescription": "Data Fabric CCM Performance Monitor Event DF CCM Request Any DRAM transaction", + "UMask": "0x8F" + }, + { + "EventName": "df_ccm_reqa.Node5.anydram", + "EventCode": "0x8B", + "BriefDescription": "Data Fabric CCM Performance Monitor Event DF CCM Request Any DRAM transaction", + "UMask": "0xAF" + }, + { + "EventName": "df_ccm_reqa.Node6.anydram", + "EventCode": "0x8B", + "BriefDescription": "Data Fabric CCM Performance Monitor Event DF CCM Request Any DRAM transaction", + "UMask": "0xCF" + }, + { + "EventName": "df_ccm_reqa.Node7.anydram", + "EventCode": "0x8B", + "BriefDescription": "Data Fabric CCM Performance Monitor Event DF CCM Request Any DRAM transaction", + "UMask": "0xEF" + }, + { + "EventName": "df_ccm_reqa.Node0.wrsizedfullzero", + "EventCode": "0x8B", + "BriefDescription": "Data Fabric CCM Performance Monitor Event DF CCM Request Ordered WrSizedFullZero", + "UMask": "0x0E" + }, + { + "EventName": "df_ccm_reqa.Node1.wrsizedfullzero", + "EventCode": "0x8B", + "BriefDescription": "Data Fabric CCM Performance Monitor Event DF CCM Request Ordered WrSizedFullZero", + "UMask": "0x2E" + }, + { + "EventName": "df_ccm_reqa.Node2.wrsizedfullzero", + "EventCode": "0x8B", + "BriefDescription": "Data Fabric CCM Performance Monitor Event DF CCM Request Ordered WrSizedFullZero", + "UMask": "0x4E" + }, + { + "EventName": "df_ccm_reqa.Node3.wrsizedfullzero", + "EventCode": "0x8E", + "BriefDescription": "Data Fabric CCM Performance Monitor Event DF CCM Request Ordered WrSizedFullZero", + "UMask": "0x6E" + }, + { + "EventName": "df_ccm_reqa.Node4.wrsizedfullzero", + "EventCode": "0x8B", + "BriefDescription": "Data Fabric CCM Performance Monitor Event DF CCM Request Ordered WrSizedFullZero", + "UMask": "0x8E" + }, + { + "EventName": "df_ccm_reqa.Node5.wrsizedfullzero", + "EventCode": "0x8B", + "BriefDescription": "Data Fabric CCM Performance Monitor Event DF CCM Request Ordered WrSizedFullZero", + "UMask": "0xAE" + }, + { + "EventName": "df_ccm_reqa.Node6.wrsizedfullzero", + "EventCode": "0x8B", + "BriefDescription": "Data Fabric CCM Performance Monitor Event DF CCM Request Ordered WrSizedFullZero", + "UMask": "0xCE" + }, + { + "EventName": "df_ccm_reqa.Node7.wrsizedfullzero", + "EventCode": "0x8B", + "BriefDescription": "Data Fabric CCM Performance Monitor Event DF CCM Request Ordered WrSizedFullZero", + "UMask": "0xEE" + }, + { + "EventName": "df_ccm_reqa.Node0.wrsizedfullnc", + "EventCode": "0x8B", + "BriefDescription": "Data Fabric CCM Performance Monitor Event DF CCM Request Ordered wrsizedfullnc", + "UMask": "0x0D" + }, + { + "EventName": "df_ccm_reqa.Node1.wrsizedfullnc", + "EventCode": "0x8A", + "BriefDescription": "Data Fabric CCM Performance Monitor Event DF CCM Request Ordered wrsizedfullnc", + "UMask": "0x2D" + }, + { + "EventName": "df_ccm_reqa.Node2.wrsizedfullnc", + "EventCode": "0x8B", + "BriefDescription": "Data Fabric CCM Performance Monitor Event DF CCM Request Ordered wrsizedfullnc", + "UMask": "0x4D" + }, + { + "EventName": "df_ccm_reqa.Node3.wrsizedfullnc", + "EventCode": "0x8B", + "BriefDescription": "Data Fabric CCM Performance Monitor Event DF CCM Request Ordered wrsizedfullnc", + "UMask": "0x6D" + }, + { + "EventName": "df_ccm_reqa.Node4.wrsizedfullnc", + "EventCode": "0x8B", + "BriefDescription": "Data Fabric CCM Performance Monitor Event DF CCM Request Ordered wrsizedfullnc", + "UMask": "0x8D" + }, + { + "EventName": "df_ccm_reqa.Node5.wrsizedfullnc", + "EventCode": "0x8B", + "BriefDescription": "Data Fabric CCM Performance Monitor Event DF CCM Request Ordered wrsizedfullnc", + "UMask": "0xAD" + }, + { + "EventName": "df_ccm_reqa.Node6.wrsizedfullnc", + "EventCode": "0x8B", + "BriefDescription": "Data Fabric CCM Performance Monitor Event DF CCM Request Ordered wrsizedfullnc", + "UMask": "0xCD" + }, + { + "EventName": "df_ccm_reqa.Node7.wrsizedfullnc", + "EventCode": "0x8B", + "BriefDescription": "Data Fabric CCM Performance Monitor Event DF CCM Request Ordered wrsizedfullnc", + "UMask": "0xED" + }, + { + "EventName": "df_ccm_reqa.Node0.wrsized", + "EventCode": "0x8B", + "BriefDescription": "Data Fabric CCM Performance Monitor Event DF CCM Request Ordered wrsized", + "UMask": "0x0C" + }, + { + "EventName": "df_ccm_reqa.Node1.wrsized", + "EventCode": "0x8B", + "BriefDescription": "Data Fabric CCM Performance Monitor Event DF CCM Request Ordered wrsized", + "UMask": "0x2C" + }, + { + "EventName": "df_ccm_reqa.Node2.wrsized", + "EventCode": "0x8B", + "BriefDescription": "Data Fabric CCM Performance Monitor Event DF CCM Request Ordered wrsized", + "UMask": "0x4C" + }, + { + "EventName": "df_ccm_reqa.Node3.wrsized", + "EventCode": "0x8B", + "BriefDescription": "Data Fabric CCM Performance Monitor Event DF CCM Request Ordered wrsized", + "UMask": "0x6C" + }, + { + "EventName": "df_ccm_reqa.Node4.wrsized", + "EventCode": "0x8B", + "BriefDescription": "Data Fabric CCM Performance Monitor Event DF CCM Request Ordered wrsized", + "UMask": "0x8C" + }, + { + "EventName": "df_ccm_reqa.Node5.wrsized", + "EventCode": "0x8B", + "BriefDescription": "Data Fabric CCM Performance Monitor Event DF CCM Request Ordered wrsized", + "UMask": "0xAC" + }, + { + "EventName": "df_ccm_reqa.Node6.wrsized", + "EventCode": "0x8B", + "BriefDescription": "Data Fabric CCM Performance Monitor Event DF CCM Request Ordered wrsized", + "UMask": "0xCC" + }, + { + "EventName": "df_ccm_reqa.Node7.wrsized", + "EventCode": "0x8B", + "BriefDescription": "Data Fabric CCM Performance Monitor Event DF CCM Request Ordered wrsized", + "UMask": "0xEC" + }, + { + "EventName": "df_ccm_reqa.Node0.wrsizedfullzero", + "EventCode": "0x8B", + "BriefDescription": "Data Fabric CCM Performance Monitor Event DF CCM Request Ordered wrsizedfullzero", + "UMask": "0x0B" + }, + { + "EventName": "df_ccm_reqa.Node1.wrsizedfullzero", + "EventCode": "0x8B", + "BriefDescription": "Data Fabric CCM Performance Monitor Event DF CCM Request Ordered wrsizedfullzero", + "UMask": "0x2B" + }, + { + "EventName": "df_ccm_reqa.Node2.wrsizedfullzero", + "EventCode": "0x8B", + "BriefDescription": "Data Fabric CCM Performance Monitor Event DF CCM Request Ordered wrsizedfullzero", + "UMask": "0x4B" + }, + { + "EventName": "df_ccm_reqa.Node3.wrsizedfullzero", + "EventCode": "0x8B", + "BriefDescription": "Data Fabric CCM Performance Monitor Event DF CCM Request Ordered wrsizedfullzero", + "UMask": "0x6B" + }, + { + "EventName": "df_ccm_reqa.Node4.wrsizedfullzero", + "EventCode": "0x8B", + "BriefDescription": "Data Fabric CCM Performance Monitor Event DF CCM Request Ordered wrsizedfullzero", + "UMask": "0x8B" + }, + { + "EventName": "df_ccm_reqa.Node5.wrsizedfullzero", + "EventCode": "0x8B", + "BriefDescription": "Data Fabric CCM Performance Monitor Event DF CCM Request Ordered wrsizedfullzero", + "UMask": "0xAB" + }, + { + "EventName": "df_ccm_reqa.Node6.wrsizedfullzero", + "EventCode": "0x8B", + "BriefDescription": "Data Fabric CCM Performance Monitor Event DF CCM Request Ordered wrsizedfullzero", + "UMask": "0xCB" + }, + { + "EventName": "df_ccm_reqa.Node7.wrsizedfullzero", + "EventCode": "0x8B", + "BriefDescription": "Data Fabric CCM Performance Monitor Event DF CCM Request Ordered wrsizedfullzero", + "UMask": "0xEB" + }, + { + "EventName": "df_ccm_reqa.Node0.wrsizedfullnc", + "EventCode": "0x8B", + "BriefDescription": "Data Fabric CCM Performance Monitor Event DF CCM Request Ordered wrsizedfullnc", + "UMask": "0x0A" + }, + { + "EventName": "df_ccm_reqa.Node1.wrsizedfullnc", + "EventCode": "0x8B", + "BriefDescription": "Data Fabric CCM Performance Monitor Event DF CCM Request Ordered wrsizedfullnc", + "UMask": "0x2A" + }, + { + "EventName": "df_ccm_reqa.Node2.wrsizedfullnc", + "EventCode": "0x8B", + "BriefDescription": "Data Fabric CCM Performance Monitor Event DF CCM Request Ordered wrsizedfullnc", + "UMask": "0x4A" + }, + { + "EventName": "df_ccm_reqa.Node3.wrsizedfullnc", + "EventCode": "0x8B", + "BriefDescription": "Data Fabric CCM Performance Monitor Event DF CCM Request Ordered wrsizedfullnc", + "UMask": "0x6A" + }, + { + "EventName": "df_ccm_reqa.Node4.wrsizedfullnc", + "EventCode": "0x8B", + "BriefDescription": "Data Fabric CCM Performance Monitor Event DF CCM Request Ordered wrsizedfullnc", + "UMask": "0x8A" + }, + { + "EventName": "df_ccm_reqa.Node5.wrsizedfullnc", + "EventCode": "0x8B", + "BriefDescription": "Data Fabric CCM Performance Monitor Event DF CCM Request Ordered wrsizedfullnc", + "UMask": "0xAA" + }, + { + "EventName": "df_ccm_reqa.Node6.wrsizedfullnc", + "EventCode": "0x8B", + "BriefDescription": "Data Fabric CCM Performance Monitor Event DF CCM Request Ordered wrsizedfullnc", + "UMask": "0xCA" + }, + { + "EventName": "df_ccm_reqa.Node7.wrsizedfullnc", + "EventCode": "0x8B", + "BriefDescription": "Data Fabric CCM Performance Monitor Event DF CCM Request Ordered wrsizedfullnc", + "UMask": "0xEA" + }, + { + "EventName": "df_ccm_reqa.Node0.wrsized", + "EventCode": "0x8B", + "BriefDescription": "Data Fabric CCM Performance Monitor Event DF CCM Request Ordered wrsized", + "UMask": "0x09" + }, + { + "EventName": "df_ccm_reqa.Node1.wrsized", + "EventCode": "0x8B", + "BriefDescription": "Data Fabric CCM Performance Monitor Event DF CCM Request Ordered wrsized", + "UMask": "0x29" + }, + { + "EventName": "df_ccm_reqa.Node2.wrsized", + "EventCode": "0x8B", + "BriefDescription": "Data Fabric CCM Performance Monitor Event DF CCM Request Ordered wrsized", + "UMask": "0x49" + }, + { + "EventName": "df_ccm_reqa.Node3.wrsized", + "EventCode": "0x8B", + "BriefDescription": "Data Fabric CCM Performance Monitor Event DF CCM Request Ordered wrsized", + "UMask": "0x69" + }, + { + "EventName": "df_ccm_reqa.Node4.wrsized", + "EventCode": "0x8B", + "BriefDescription": "Data Fabric CCM Performance Monitor Event DF CCM Request Ordered wrsized", + "UMask": "0x89" + }, + { + "EventName": "df_ccm_reqa.Node5.wrsized", + "EventCode": "0x8B", + "BriefDescription": "Data Fabric CCM Performance Monitor Event DF CCM Request Ordered wrsized", + "UMask": "0xA9" + }, + { + "EventName": "df_ccm_reqa.Node6.wrsized", + "EventCode": "0x8B", + "BriefDescription": "Data Fabric CCM Performance Monitor Event DF CCM Request Ordered wrsized", + "UMask": "0xC9" + }, + { + "EventName": "df_ccm_reqa.Node7.wrsized", + "EventCode": "0x8B", + "BriefDescription": "Data Fabric CCM Performance Monitor Event DF CCM Request Ordered wrsized", + "UMask": "0xE9" + }, + { + "EventName": "df_ccm_reqa.Node0.rdsizednc", + "EventCode": "0x8B", + "BriefDescription": "Data Fabric CCM Performance Monitor Event DF CCM Request Ordered rdsizednc", + "UMask": "0x08" + }, + { + "EventName": "df_ccm_reqa.Node1.rdsizednc", + "EventCode": "0x8B", + "BriefDescription": "Data Fabric CCM Performance Monitor Event DF CCM Request Ordered rdsizednc", + "UMask": "0x28" + }, + { + "EventName": "df_ccm_reqa.Node2.rdsizednc", + "EventCode": "0x8B", + "BriefDescription": "Data Fabric CCM Performance Monitor Event DF CCM Request Ordered rdsizednc", + "UMask": "0x48" + }, + { + "EventName": "df_ccm_reqa.Node3.rdsizednc", + "EventCode": "0x8B", + "BriefDescription": "Data Fabric CCM Performance Monitor Event DF CCM Request Ordered rdsizednc", + "UMask": "0x68" + }, + { + "EventName": "df_ccm_reqa.Node4.rdsizednc", + "EventCode": "0x8B", + "BriefDescription": "Data Fabric CCM Performance Monitor Event DF CCM Request Ordered rdsizednc", + "UMask": "0x88" + }, + { + "EventName": "df_ccm_reqa.Node5.rdsizednc", + "EventCode": "0x8B", + "BriefDescription": "Data Fabric CCM Performance Monitor Event DF CCM Request Ordered rdsizednc", + "UMask": "0xA8" + }, + { + "EventName": "df_ccm_reqa.Node6.rdsizednc", + "EventCode": "0x8B", + "BriefDescription": "Data Fabric CCM Performance Monitor Event DF CCM Request Ordered rdsizednc", + "UMask": "0xC8" + }, + { + "EventName": "df_ccm_reqa.Node7.rdsizednc", + "EventCode": "0x8B", + "BriefDescription": "Data Fabric CCM Performance Monitor Event DF CCM Request Ordered rdsizednc", + "UMask": "0xE8" + }, + { + "EventName": "df_ccm_reqa.Node0.rdsized", + "EventCode": "0x8B", + "BriefDescription": "Data Fabric CCM Performance Monitor Event DF CCM Request Ordered rdsized", + "UMask": "0x07" + }, + { + "EventName": "df_ccm_reqa.Node1.rdsized", + "EventCode": "0x8B", + "BriefDescription": "Data Fabric CCM Performance Monitor Event DF CCM Request Ordered rdsized", + "UMask": "0x27" + }, + { + "EventName": "df_ccm_reqa.Node2.rdsized", + "EventCode": "0x8B", + "BriefDescription": "Data Fabric CCM Performance Monitor Event DF CCM Request Ordered rdsized", + "UMask": "0x47" + }, + { + "EventName": "df_ccm_reqa.Node3.rdsized", + "EventCode": "0x8B", + "BriefDescription": "Data Fabric CCM Performance Monitor Event DF CCM Request Ordered rdsized", + "UMask": "0x67" + }, + { + "EventName": "df_ccm_reqa.Node4.rdsized", + "EventCode": "0x8B", + "BriefDescription": "Data Fabric CCM Performance Monitor Event DF CCM Request Ordered rdsized", + "UMask": "0x87" + }, + { + "EventName": "df_ccm_reqa.Node5.rdsized", + "EventCode": "0x8B", + "BriefDescription": "Data Fabric CCM Performance Monitor Event DF CCM Request Ordered rdsized", + "UMask": "0xA7" + }, + { + "EventName": "df_ccm_reqa.Node6.rdsized", + "EventCode": "0x8B", + "BriefDescription": "Data Fabric CCM Performance Monitor Event DF CCM Request Ordered rdsized", + "UMask": "0xC7" + }, + { + "EventName": "df_ccm_reqa.Node7.rdsized", + "EventCode": "0x8B", + "BriefDescription": "Data Fabric CCM Performance Monitor Event DF CCM Request Ordered rdsized", + "UMask": "0xE7" + }, + { + "EventName": "df_ccm_reqa.Node0.specdramrd", + "EventCode": "0x8B", + "BriefDescription": "Data Fabric CCM Performance Monitor Event DF CCM Request Ordered specdramrd", + "UMask": "0x06" + }, + { + "EventName": "df_ccm_reqa.Node1.specdramrd", + "EventCode": "0x8B", + "BriefDescription": "Data Fabric CCM Performance Monitor Event DF CCM Request Ordered specdramrd", + "UMask": "0x26" + }, + { + "EventName": "df_ccm_reqa.Node2.specdramrd", + "EventCode": "0x8B", + "BriefDescription": "Data Fabric CCM Performance Monitor Event DF CCM Request Ordered specdramrd", + "UMask": "0x46" + }, + { + "EventName": "df_ccm_reqa.Node3.specdramrd", + "EventCode": "0x8B", + "BriefDescription": "Data Fabric CCM Performance Monitor Event DF CCM Request Ordered specdramrd", + "UMask": "0x66" + }, + { + "EventName": "df_ccm_reqa.Node4.specdramrd", + "EventCode": "0x8B", + "BriefDescription": "Data Fabric CCM Performance Monitor Event DF CCM Request Ordered specdramrd", + "UMask": "0x86" + }, + { + "EventName": "df_ccm_reqa.Node5.specdramrd", + "EventCode": "0x8B", + "BriefDescription": "Data Fabric CCM Performance Monitor Event DF CCM Request Ordered specdramrd", + "UMask": "0xA6" + }, + { + "EventName": "df_ccm_reqa.Node6.specdramrd", + "EventCode": "0x8B", + "BriefDescription": "Data Fabric CCM Performance Monitor Event DF CCM Request Ordered specdramrd", + "UMask": "0xC6" + }, + { + "EventName": "df_ccm_reqa.Node7.specdramrd", + "EventCode": "0x8B", + "BriefDescription": "Data Fabric CCM Performance Monitor Event DF CCM Request Ordered specdramrd", + "UMask": "0xE6" + }, + { + "EventName": "df_ccm_reqa.Node0.anyrdblk", + "EventCode": "0x8B", + "BriefDescription": "Data Fabric CCM Performance Monitor Event DF CCM Request Ordered anyrdblk", + "UMask": "0x05" + }, + { + "EventName": "df_ccm_reqa.Node1.anyrdblk", + "EventCode": "0x8B", + "BriefDescription": "Data Fabric CCM Performance Monitor Event DF CCM Request Ordered anyrdblk", + "UMask": "0x25" + }, + { + "EventName": "df_ccm_reqa.Node2.anyrdblk", + "EventCode": "0x8B", + "BriefDescription": "Data Fabric CCM Performance Monitor Event DF CCM Request Ordered anyrdblk", + "UMask": "0x45" + }, + { + "EventName": "df_ccm_reqa.Node3.anyrdblk", + "EventCode": "0x8B", + "BriefDescription": "Data Fabric CCM Performance Monitor Event DF CCM Request Ordered anyrdblk", + "UMask": "0x65" + }, + { + "EventName": "df_ccm_reqa.Node4.anyrdblk", + "EventCode": "0x8B", + "BriefDescription": "Data Fabric CCM Performance Monitor Event DF CCM Request Ordered anyrdblk", + "UMask": "0x85" + }, + { + "EventName": "df_ccm_reqa.Node5.anyrdblk", + "EventCode": "0x8B", + "BriefDescription": "Data Fabric CCM Performance Monitor Event DF CCM Request Ordered anyrdblk", + "UMask": "0xA5" + }, + { + "EventName": "df_ccm_reqa.Node6.anyrdblk", + "EventCode": "0x8B", + "BriefDescription": "Data Fabric CCM Performance Monitor Event DF CCM Request Ordered anyrdblk", + "UMask": "0xC5" + }, + { + "EventName": "df_ccm_reqa.Node7.anyrdblk", + "EventCode": "0x8B", + "BriefDescription": "Data Fabric CCM Performance Monitor Event DF CCM Request Ordered anyrdblk", + "UMask": "0xE5" + }, + { + "EventName": "df_ccm_reqa.Node0.rdvlkc", + "EventCode": "0x8B", + "BriefDescription": "Data Fabric CCM Performance Monitor Event DF CCM Request Ordered rdvlkc", + "UMask": "0x04" + }, + { + "EventName": "df_ccm_reqa.Node1.rdvlkc", + "EventCode": "0x8B", + "BriefDescription": "Data Fabric CCM Performance Monitor Event DF CCM Request Ordered rdvlkc", + "UMask": "0x24" + }, + { + "EventName": "df_ccm_reqa.Node2.rdvlkc", + "EventCode": "0x8B", + "BriefDescription": "Data Fabric CCM Performance Monitor Event DF CCM Request Ordered rdvlkc", + "UMask": "0x44" + }, + { + "EventName": "df_ccm_reqa.Node3.rdvlkc", + "EventCode": "0x8B", + "BriefDescription": "Data Fabric CCM Performance Monitor Event DF CCM Request Ordered rdvlkc", + "UMask": "0x64" + }, + { + "EventName": "df_ccm_reqa.Node4.rdvlkc", + "EventCode": "0x8B", + "BriefDescription": "Data Fabric CCM Performance Monitor Event DF CCM Request Ordered rdvlkc", + "UMask": "0x84" + }, + { + "EventName": "df_ccm_reqa.Node5.rdvlkc", + "EventCode": "0x8B", + "BriefDescription": "Data Fabric CCM Performance Monitor Event DF CCM Request Ordered rdvlkc", + "UMask": "0xA4" + }, + { + "EventName": "df_ccm_reqa.Node6.rdvlkc", + "EventCode": "0x8B", + "BriefDescription": "Data Fabric CCM Performance Monitor Event DF CCM Request Ordered rdvlkc", + "UMask": "0xC4" + }, + { + "EventName": "df_ccm_reqa.Node7.rdvlkc", + "EventCode": "0x8B", + "BriefDescription": "Data Fabric CCM Performance Monitor Event DF CCM Request Ordered rdvlkc", + "UMask": "0xE4" + }, + { + "EventName": "df_ccm_reqa.Node0.rdvlkx", + "EventCode": "0x8B", + "BriefDescription": "Data Fabric CCM Performance Monitor Event DF CCM Request Ordered rdvlkx", + "UMask": "0x03" + }, + { + "EventName": "df_ccm_reqa.Node1.rdvlkx", + "EventCode": "0x8B", + "BriefDescription": "Data Fabric CCM Performance Monitor Event DF CCM Request Ordered rdvlkx", + "UMask": "0x23" + }, + { + "EventName": "df_ccm_reqa.Node2.rdvlkx", + "EventCode": "0x8B", + "BriefDescription": "Data Fabric CCM Performance Monitor Event DF CCM Request Ordered rdvlkx", + "UMask": "0x43" + }, + { + "EventName": "df_ccm_reqa.Node3.rdvlkx", + "EventCode": "0x8B", + "BriefDescription": "Data Fabric CCM Performance Monitor Event DF CCM Request Ordered rdvlkx", + "UMask": "0x63" + }, + { + "EventName": "df_ccm_reqa.Node4.rdvlkx", + "EventCode": "0x8B", + "BriefDescription": "Data Fabric CCM Performance Monitor Event DF CCM Request Ordered rdvlkx", + "UMask": "0x83" + }, + { + "EventName": "df_ccm_reqa.Node5.rdvlkx", + "EventCode": "0x8B", + "BriefDescription": "Data Fabric CCM Performance Monitor Event DF CCM Request Ordered rdvlkx", + "UMask": "0xA3" + }, + { + "EventName": "df_ccm_reqa.Node6.rdvlkx", + "EventCode": "0x8B", + "BriefDescription": "Data Fabric CCM Performance Monitor Event DF CCM Request Ordered rdvlkx", + "UMask": "0xC3" + }, + { + "EventName": "df_ccm_reqa.Node7.rdvlkx", + "EventCode": "0x8B", + "BriefDescription": "Data Fabric CCM Performance Monitor Event DF CCM Request Ordered rdvlkx", + "UMask": "0xE3" + }, + { + "EventName": "df_ccm_reqa.Node0.rdvlks", + "EventCode": "0x8B", + "BriefDescription": "Data Fabric CCM Performance Monitor Event DF CCM Request Ordered rdvlks", + "UMask": "0x02" + }, + { + "EventName": "df_ccm_reqa.Node1.rdvlks", + "EventCode": "0x8B", + "BriefDescription": "Data Fabric CCM Performance Monitor Event DF CCM Request Ordered rdvlks", + "UMask": "0x22" + }, + { + "EventName": "df_ccm_reqa.Node2.rdvlks", + "EventCode": "0x8B", + "BriefDescription": "Data Fabric CCM Performance Monitor Event DF CCM Request Ordered rdvlks", + "UMask": "0x42" + }, + { + "EventName": "df_ccm_reqa.Node3.rdvlks", + "EventCode": "0x8B", + "BriefDescription": "Data Fabric CCM Performance Monitor Event DF CCM Request Ordered rdvlks", + "UMask": "0x62" + }, + { + "EventName": "df_ccm_reqa.Node4.rdvlks", + "EventCode": "0x8B", + "BriefDescription": "Data Fabric CCM Performance Monitor Event DF CCM Request Ordered rdvlks", + "UMask": "0x82" + }, + { + "EventName": "df_ccm_reqa.Node5.rdvlks", + "EventCode": "0x8B", + "BriefDescription": "Data Fabric CCM Performance Monitor Event DF CCM Request Ordered rdvlks", + "UMask": "0xA2" + }, + { + "EventName": "df_ccm_reqa.Node6.rdvlks", + "EventCode": "0x8B", + "BriefDescription": "Data Fabric CCM Performance Monitor Event DF CCM Request Ordered rdvlks", + "UMask": "0xC2" + }, + { + "EventName": "df_ccm_reqa.Node7.rdvlks", + "EventCode": "0x8B", + "BriefDescription": "Data Fabric CCM Performance Monitor Event DF CCM Request Ordered rdvlks", + "UMask": "0xE2" + }, + { + "EventName": "df_ccm_reqa.Node0.rdvlkl", + "EventCode": "0x8B", + "BriefDescription": "Data Fabric CCM Performance Monitor Event DF CCM Request Ordered rdvlkl", + "UMask": "0x01" + }, + { + "EventName": "df_ccm_reqa.Node1.rdvlkl", + "EventCode": "0x8B", + "BriefDescription": "Data Fabric CCM Performance Monitor Event DF CCM Request Ordered rdvlkl", + "UMask": "0x21" + }, + { + "EventName": "df_ccm_reqa.Node2.rdvlkl", + "EventCode": "0x8B", + "BriefDescription": "Data Fabric CCM Performance Monitor Event DF CCM Request Ordered rdvlkl", + "UMask": "0x41" + }, + { + "EventName": "df_ccm_reqa.Node3.rdvlkl", + "EventCode": "0x8B", + "BriefDescription": "Data Fabric CCM Performance Monitor Event DF CCM Request Ordered rdvlkl", + "UMask": "0x61" + }, + { + "EventName": "df_ccm_reqa.Node4.rdvlkl", + "EventCode": "0x8B", + "BriefDescription": "Data Fabric CCM Performance Monitor Event DF CCM Request Ordered rdvlkl", + "UMask": "0x81" + }, + { + "EventName": "df_ccm_reqa.Node5.rdvlkl", + "EventCode": "0x8B", + "BriefDescription": "Data Fabric CCM Performance Monitor Event DF CCM Request Ordered rdvlkl", + "UMask": "0xA1" + }, + { + "EventName": "df_ccm_reqa.Node6.rdvlkl", + "EventCode": "0x8B", + "BriefDescription": "Data Fabric CCM Performance Monitor Event DF CCM Request Ordered rdvlkl", + "UMask": "0xC1" + }, + { + "EventName": "df_ccm_reqa.Node7.rdvlkl", + "EventCode": "0x8B", + "BriefDescription": "Data Fabric CCM Performance Monitor Event DF CCM Request Ordered rdvlkl", + "UMask": "0xE1" + }, + { + "EventName": "df_ccm_reqb.Node0.chgtox", + "EventCode": "0x8c", + "BriefDescription": "Data Fabric CCM Performance Monitor Event DF CCM Request Ordered chgtox", + "UMask": "0x0E" + }, + { + "EventName": "df_ccm_reqb.Node1.chgtox", + "EventCode": "0x8c", + "BriefDescription": "Data Fabric CCM Performance Monitor Event DF CCM Request Ordered chgtox", + "UMask": "0x2E" + }, + { + "EventName": "df_ccm_reqb.Node2.chgtox", + "EventCode": "0x8c", + "BriefDescription": "Data Fabric CCM Performance Monitor Event DF CCM Request Ordered chgtox", + "UMask": "0x4E" + }, + { + "EventName": "df_ccm_reqb.Node3.chgtox", + "EventCode": "0x8E", + "BriefDescription": "Data Fabric CCM Performance Monitor Event DF CCM Request Ordered chgtox", + "UMask": "0x6E" + }, + { + "EventName": "df_ccm_reqb.Node4.chgtox", + "EventCode": "0x8c", + "BriefDescription": "Data Fabric CCM Performance Monitor Event DF CCM Request Ordered chgtox", + "UMask": "0x8E" + }, + { + "EventName": "df_ccm_reqb.Node5.chgtox", + "EventCode": "0x8c", + "BriefDescription": "Data Fabric CCM Performance Monitor Event DF CCM Request Ordered chgtox", + "UMask": "0xAE" + }, + { + "EventName": "df_ccm_reqb.Node6.chgtox", + "EventCode": "0x8c", + "BriefDescription": "Data Fabric CCM Performance Monitor Event DF CCM Request Ordered chgtox", + "UMask": "0xCE" + }, + { + "EventName": "df_ccm_reqb.Node7.chgtox", + "EventCode": "0x8c", + "BriefDescription": "Data Fabric CCM Performance Monitor Event DF CCM Request Ordered chgtox", + "UMask": "0xEE" + }, + { + "EventName": "df_ccm_reqb.Node0.vicblkfull.", + "EventCode": "0x8c", + "BriefDescription": "Data Fabric CCM Performance Monitor Event DF CCM Request Ordered vicblkfull.", + "UMask": "0x0D" + }, + { + "EventName": "df_ccm_reqb.Node1.vicblkfull.", + "EventCode": "0x8A", + "BriefDescription": "Data Fabric CCM Performance Monitor Event DF CCM Request Ordered vicblkfull.", + "UMask": "0x2D" + }, + { + "EventName": "df_ccm_reqb.Node2.vicblkfull.", + "EventCode": "0x8c", + "BriefDescription": "Data Fabric CCM Performance Monitor Event DF CCM Request Ordered vicblkfull.", + "UMask": "0x4D" + }, + { + "EventName": "df_ccm_reqb.Node3.vicblkfull.", + "EventCode": "0x8c", + "BriefDescription": "Data Fabric CCM Performance Monitor Event DF CCM Request Ordered vicblkfull.", + "UMask": "0x6D" + }, + { + "EventName": "df_ccm_reqb.Node4.vicblkfull.", + "EventCode": "0x8c", + "BriefDescription": "Data Fabric CCM Performance Monitor Event DF CCM Request Ordered vicblkfull.", + "UMask": "0x8D" + }, + { + "EventName": "df_ccm_reqb.Node5.vicblkfull.", + "EventCode": "0x8c", + "BriefDescription": "Data Fabric CCM Performance Monitor Event DF CCM Request Ordered vicblkfull.", + "UMask": "0xAD" + }, + { + "EventName": "df_ccm_reqb.Node6.vicblkfull.", + "EventCode": "0x8c", + "BriefDescription": "Data Fabric CCM Performance Monitor Event DF CCM Request Ordered vicblkfull.", + "UMask": "0xCD" + }, + { + "EventName": "df_ccm_reqb.Node7.vicblkfull.", + "EventCode": "0x8c", + "BriefDescription": "Data Fabric CCM Performance Monitor Event DF CCM Request Ordered vicblkfull.", + "UMask": "0xED" + }, + { + "EventName": "df_ccm_reqb.Node0.wbinvblkall", + "EventCode": "0x8c", + "BriefDescription": "Data Fabric CCM Performance Monitor Event DF CCM Request Ordered wbinvblkall", + "UMask": "0x0C" + }, + { + "EventName": "df_ccm_reqb.Node1.wbinvblkall", + "EventCode": "0x8c", + "BriefDescription": "Data Fabric CCM Performance Monitor Event DF CCM Request Ordered wbinvblkall", + "UMask": "0x2C" + }, + { + "EventName": "df_ccm_reqb.Node2.wbinvblkall", + "EventCode": "0x8c", + "BriefDescription": "Data Fabric CCM Performance Monitor Event DF CCM Request Ordered wbinvblkall", + "UMask": "0x4C" + }, + { + "EventName": "df_ccm_reqb.Node3.wbinvblkall", + "EventCode": "0x8c", + "BriefDescription": "Data Fabric CCM Performance Monitor Event DF CCM Request Ordered wbinvblkall", + "UMask": "0x6C" + }, + { + "EventName": "df_ccm_reqb.Node4.wbinvblkall", + "EventCode": "0x8c", + "BriefDescription": "Data Fabric CCM Performance Monitor Event DF CCM Request Ordered wbinvblkall", + "UMask": "0x8C" + }, + { + "EventName": "df_ccm_reqb.Node5.wbinvblkall", + "EventCode": "0x8c", + "BriefDescription": "Data Fabric CCM Performance Monitor Event DF CCM Request Ordered wbinvblkall", + "UMask": "0xAC" + }, + { + "EventName": "df_ccm_reqb.Node6.wbinvblkall", + "EventCode": "0x8c", + "BriefDescription": "Data Fabric CCM Performance Monitor Event DF CCM Request Ordered wbinvblkall", + "UMask": "0xCC" + }, + { + "EventName": "df_ccm_reqb.Node7.wbinvblkall", + "EventCode": "0x8c", + "BriefDescription": "Data Fabric CCM Performance Monitor Event DF CCM Request Ordered wbinvblkall", + "UMask": "0xEC" + }, + { + "EventName": "df_ccm_reqb.Node0.vicblkfullzero", + "EventCode": "0x8c", + "BriefDescription": "Data Fabric CCM Performance Monitor Event DF CCM Request Ordered vicblkfullzero", + "UMask": "0x0B" + }, + { + "EventName": "df_ccm_reqb.Node1.vicblkfullzero", + "EventCode": "0x8c", + "BriefDescription": "Data Fabric CCM Performance Monitor Event DF CCM Request Ordered vicblkfullzero", + "UMask": "0x2B" + }, + { + "EventName": "df_ccm_reqb.Node2.vicblkfullzero", + "EventCode": "0x8c", + "BriefDescription": "Data Fabric CCM Performance Monitor Event DF CCM Request Ordered vicblkfullzero", + "UMask": "0x4B" + }, + { + "EventName": "df_ccm_reqb.Node3.vicblkfullzero", + "EventCode": "0x8c", + "BriefDescription": "Data Fabric CCM Performance Monitor Event DF CCM Request Ordered vicblkfullzero", + "UMask": "0x6B" + }, + { + "EventName": "df_ccm_reqb.Node4.vicblkfullzero", + "EventCode": "0x8c", + "BriefDescription": "Data Fabric CCM Performance Monitor Event DF CCM Request Ordered vicblkfullzero", + "UMask": "0x8B" + }, + { + "EventName": "df_ccm_reqb.Node5.vicblkfullzero", + "EventCode": "0x8c", + "BriefDescription": "Data Fabric CCM Performance Monitor Event DF CCM Request Ordered vicblkfullzero", + "UMask": "0xAB" + }, + { + "EventName": "df_ccm_reqb.Node6.vicblkfullzero", + "EventCode": "0x8c", + "BriefDescription": "Data Fabric CCM Performance Monitor Event DF CCM Request Ordered vicblkfullzero", + "UMask": "0xCB" + }, + { + "EventName": "df_ccm_reqb.Node7.vicblkfullzero", + "EventCode": "0x8c", + "BriefDescription": "Data Fabric CCM Performance Monitor Event DF CCM Request Ordered vicblkfullzero", + "UMask": "0xEB" + }, + { + "EventName": "df_ccm_reqb.Node0.vicblkfull.", + "EventCode": "0x8c", + "BriefDescription": "Data Fabric CCM Performance Monitor Event DF CCM Request Ordered vicblkfull.", + "UMask": "0x0A" + }, + { + "EventName": "df_ccm_reqb.Node1.vicblkfull.", + "EventCode": "0x8c", + "BriefDescription": "Data Fabric CCM Performance Monitor Event DF CCM Request Ordered vicblkfull.", + "UMask": "0x2A" + }, + { + "EventName": "df_ccm_reqb.Node2.vicblkfull.", + "EventCode": "0x8c", + "BriefDescription": "Data Fabric CCM Performance Monitor Event DF CCM Request Ordered vicblkfull.", + "UMask": "0x4A" + }, + { + "EventName": "df_ccm_reqb.Node3.vicblkfull.", + "EventCode": "0x8c", + "BriefDescription": "Data Fabric CCM Performance Monitor Event DF CCM Request Ordered vicblkfull.", + "UMask": "0x6A" + }, + { + "EventName": "df_ccm_reqb.Node4.vicblkfull.", + "EventCode": "0x8c", + "BriefDescription": "Data Fabric CCM Performance Monitor Event DF CCM Request Ordered vicblkfull.", + "UMask": "0x8A" + }, + { + "EventName": "df_ccm_reqb.Node5.vicblkfull.", + "EventCode": "0x8c", + "BriefDescription": "Data Fabric CCM Performance Monitor Event DF CCM Request Ordered vicblkfull.", + "UMask": "0xAA" + }, + { + "EventName": "df_ccm_reqb.Node6.vicblkfull.", + "EventCode": "0x8c", + "BriefDescription": "Data Fabric CCM Performance Monitor Event DF CCM Request Ordered vicblkfull.", + "UMask": "0xCA" + }, + { + "EventName": "df_ccm_reqb.Node7.vicblkfull.", + "EventCode": "0x8c", + "BriefDescription": "Data Fabric CCM Performance Monitor Event DF CCM Request Ordered vicblkfull.", + "UMask": "0xEA" + }, + { + "EventName": "df_ccm_reqb.Node0.vicblkcln", + "EventCode": "0x8c", + "BriefDescription": "Data Fabric CCM Performance Monitor Event DF CCM Request Ordered vicblkcln", + "UMask": "0x09" + }, + { + "EventName": "df_ccm_reqb.Node1.vicblkcln", + "EventCode": "0x8c", + "BriefDescription": "Data Fabric CCM Performance Monitor Event DF CCM Request Ordered vicblkcln", + "UMask": "0x29" + }, + { + "EventName": "df_ccm_reqb.Node2.vicblkcln", + "EventCode": "0x8c", + "BriefDescription": "Data Fabric CCM Performance Monitor Event DF CCM Request Ordered vicblkcln", + "UMask": "0x49" + }, + { + "EventName": "df_ccm_reqb.Node3.vicblkcln", + "EventCode": "0x8c", + "BriefDescription": "Data Fabric CCM Performance Monitor Event DF CCM Request Ordered vicblkcln", + "UMask": "0x69" + }, + { + "EventName": "df_ccm_reqb.Node4.vicblkcln", + "EventCode": "0x8c", + "BriefDescription": "Data Fabric CCM Performance Monitor Event DF CCM Request Ordered vicblkcln", + "UMask": "0x89" + }, + { + "EventName": "df_ccm_reqb.Node5.vicblkcln", + "EventCode": "0x8c", + "BriefDescription": "Data Fabric CCM Performance Monitor Event DF CCM Request Ordered vicblkcln", + "UMask": "0xA9" + }, + { + "EventName": "df_ccm_reqb.Node6.vicblkcln", + "EventCode": "0x8c", + "BriefDescription": "Data Fabric CCM Performance Monitor Event DF CCM Request Ordered vicblkcln", + "UMask": "0xC9" + }, + { + "EventName": "df_ccm_reqb.Node7.vicblkcln", + "EventCode": "0x8c", + "BriefDescription": "Data Fabric CCM Performance Monitor Event DF CCM Request Ordered vicblkcln", + "UMask": "0xE9" + }, + { + "EventName": "df_ccm_reqb.Node0.anyiorequest.", + "EventCode": "0x8c", + "BriefDescription": "Data Fabric CCM Performance Monitor Event DF CCM Request Ordered anyiorequest.", + "UMask": "0x07" + }, + { + "EventName": "df_ccm_reqb.Node1.anyiorequest.", + "EventCode": "0x8c", + "BriefDescription": "Data Fabric CCM Performance Monitor Event DF CCM Request Ordered anyiorequest.", + "UMask": "0x27" + }, + { + "EventName": "df_ccm_reqb.Node2.anyiorequest.", + "EventCode": "0x8c", + "BriefDescription": "Data Fabric CCM Performance Monitor Event DF CCM Request Ordered anyiorequest.", + "UMask": "0x47" + }, + { + "EventName": "df_ccm_reqb.Node3.anyiorequest.", + "EventCode": "0x8c", + "BriefDescription": "Data Fabric CCM Performance Monitor Event DF CCM Request Ordered anyiorequest.", + "UMask": "0x67" + }, + { + "EventName": "df_ccm_reqb.Node4.anyiorequest.", + "EventCode": "0x8c", + "BriefDescription": "Data Fabric CCM Performance Monitor Event DF CCM Request Ordered anyiorequest.", + "UMask": "0x87" + }, + { + "EventName": "df_ccm_reqb.Node5.anyiorequest.", + "EventCode": "0x8c", + "BriefDescription": "Data Fabric CCM Performance Monitor Event DF CCM Request Ordered anyiorequest.", + "UMask": "0xA7" + }, + { + "EventName": "df_ccm_reqb.Node6.anyiorequest.", + "EventCode": "0x8c", + "BriefDescription": "Data Fabric CCM Performance Monitor Event DF CCM Request Ordered anyiorequest.", + "UMask": "0xC7" + }, + { + "EventName": "df_ccm_reqb.Node7.anyiorequest.", + "EventCode": "0x8c", + "BriefDescription": "Data Fabric CCM Performance Monitor Event DF CCM Request Ordered anyiorequest.", + "UMask": "0xE7" + }, + { + "EventName": "df_ccm_reqb.Node0.anywrsized", + "EventCode": "0x8c", + "BriefDescription": "Data Fabric CCM Performance Monitor Event DF CCM Request Ordered anywrsized", + "UMask": "0x06" + }, + { + "EventName": "df_ccm_reqb.Node1.anywrsized", + "EventCode": "0x8c", + "BriefDescription": "Data Fabric CCM Performance Monitor Event DF CCM Request Ordered anywrsized", + "UMask": "0x26" + }, + { + "EventName": "df_ccm_reqb.Node2.anywrsized", + "EventCode": "0x8c", + "BriefDescription": "Data Fabric CCM Performance Monitor Event DF CCM Request Ordered anywrsized", + "UMask": "0x46" + }, + { + "EventName": "df_ccm_reqb.Node3.anywrsized", + "EventCode": "0x8c", + "BriefDescription": "Data Fabric CCM Performance Monitor Event DF CCM Request Ordered anywrsized", + "UMask": "0x66" + }, + { + "EventName": "df_ccm_reqb.Node4.anywrsized", + "EventCode": "0x8c", + "BriefDescription": "Data Fabric CCM Performance Monitor Event DF CCM Request Ordered anywrsized", + "UMask": "0x86" + }, + { + "EventName": "df_ccm_reqb.Node5.anywrsized", + "EventCode": "0x8c", + "BriefDescription": "Data Fabric CCM Performance Monitor Event DF CCM Request Ordered anywrsized", + "UMask": "0xA6" + }, + { + "EventName": "df_ccm_reqb.Node6.anywrsized", + "EventCode": "0x8c", + "BriefDescription": "Data Fabric CCM Performance Monitor Event DF CCM Request Ordered anywrsized", + "UMask": "0xC6" + }, + { + "EventName": "df_ccm_reqb.Node7.anywrsized", + "EventCode": "0x8c", + "BriefDescription": "Data Fabric CCM Performance Monitor Event DF CCM Request Ordered anywrsized", + "UMask": "0xE6" + }, + { + "EventName": "df_ccm_reqb.Node0.wrsizedfullnc", + "EventCode": "0x8c", + "BriefDescription": "Data Fabric CCM Performance Monitor Event DF CCM Request Ordered wrsizedfullnc", + "UMask": "0x05" + }, + { + "EventName": "df_ccm_reqb.Node1.wrsizedfullnc", + "EventCode": "0x8c", + "BriefDescription": "Data Fabric CCM Performance Monitor Event DF CCM Request Ordered wrsizedfullnc", + "UMask": "0x25" + }, + { + "EventName": "df_ccm_reqb.Node2.wrsizedfullnc", + "EventCode": "0x8c", + "BriefDescription": "Data Fabric CCM Performance Monitor Event DF CCM Request Ordered wrsizedfullnc", + "UMask": "0x45" + }, + { + "EventName": "df_ccm_reqb.Node3.wrsizedfullnc", + "EventCode": "0x8c", + "BriefDescription": "Data Fabric CCM Performance Monitor Event DF CCM Request Ordered wrsizedfullnc", + "UMask": "0x65" + }, + { + "EventName": "df_ccm_reqb.Node4.wrsizedfullnc", + "EventCode": "0x8c", + "BriefDescription": "Data Fabric CCM Performance Monitor Event DF CCM Request Ordered wrsizedfullnc", + "UMask": "0x85" + }, + { + "EventName": "df_ccm_reqb.Node5.wrsizedfullnc", + "EventCode": "0x8c", + "BriefDescription": "Data Fabric CCM Performance Monitor Event DF CCM Request Ordered wrsizedfullnc", + "UMask": "0xA5" + }, + { + "EventName": "df_ccm_reqb.Node6.wrsizedfullnc", + "EventCode": "0x8c", + "BriefDescription": "Data Fabric CCM Performance Monitor Event DF CCM Request Ordered wrsizedfullnc", + "UMask": "0xC5" + }, + { + "EventName": "df_ccm_reqb.Node7.wrsizedfullnc", + "EventCode": "0x8c", + "BriefDescription": "Data Fabric CCM Performance Monitor Event DF CCM Request Ordered wrsizedfullnc", + "UMask": "0xE5" + }, + { + "EventName": "df_ccm_reqb.Node0.wrsizednc", + "EventCode": "0x8c", + "BriefDescription": "Data Fabric CCM Performance Monitor Event DF CCM Request Ordered wrsizednc", + "UMask": "0x04" + }, + { + "EventName": "df_ccm_reqb.Node1.wrsizednc", + "EventCode": "0x8c", + "BriefDescription": "Data Fabric CCM Performance Monitor Event DF CCM Request Ordered wrsizednc", + "UMask": "0x24" + }, + { + "EventName": "df_ccm_reqb.Node2.wrsizednc", + "EventCode": "0x8c", + "BriefDescription": "Data Fabric CCM Performance Monitor Event DF CCM Request Ordered wrsizednc", + "UMask": "0x44" + }, + { + "EventName": "df_ccm_reqb.Node3.wrsizednc", + "EventCode": "0x8c", + "BriefDescription": "Data Fabric CCM Performance Monitor Event DF CCM Request Ordered wrsizednc", + "UMask": "0x64" + }, + { + "EventName": "df_ccm_reqb.Node4.wrsizednc", + "EventCode": "0x8c", + "BriefDescription": "Data Fabric CCM Performance Monitor Event DF CCM Request Ordered wrsizednc", + "UMask": "0x84" + }, + { + "EventName": "df_ccm_reqb.Node5.wrsizednc", + "EventCode": "0x8c", + "BriefDescription": "Data Fabric CCM Performance Monitor Event DF CCM Request Ordered wrsizednc", + "UMask": "0xA4" + }, + { + "EventName": "df_ccm_reqb.Node6.wrsizednc", + "EventCode": "0x8c", + "BriefDescription": "Data Fabric CCM Performance Monitor Event DF CCM Request Ordered wrsizednc", + "UMask": "0xC4" + }, + { + "EventName": "df_ccm_reqb.Node7.wrsizednc", + "EventCode": "0x8c", + "BriefDescription": "Data Fabric CCM Performance Monitor Event DF CCM Request Ordered wrsizednc", + "UMask": "0xE4" + }, + { + "EventName": "df_ccm_reqb.Node0.wrsizedfullncposted", + "EventCode": "0x8c", + "BriefDescription": "Data Fabric CCM Performance Monitor Event DF CCM Request Ordered wrsizedfullncposted", + "UMask": "0x03" + }, + { + "EventName": "df_ccm_reqb.Node1.wrsizedfullncposted", + "EventCode": "0x8c", + "BriefDescription": "Data Fabric CCM Performance Monitor Event DF CCM Request Ordered wrsizedfullncposted", + "UMask": "0x23" + }, + { + "EventName": "df_ccm_reqb.Node2.wrsizedfullncposted", + "EventCode": "0x8c", + "BriefDescription": "Data Fabric CCM Performance Monitor Event DF CCM Request Ordered wrsizedfullncposted", + "UMask": "0x43" + }, + { + "EventName": "df_ccm_reqb.Node3.wrsizedfullncposted", + "EventCode": "0x8c", + "BriefDescription": "Data Fabric CCM Performance Monitor Event DF CCM Request Ordered wrsizedfullncposted", + "UMask": "0x63" + }, + { + "EventName": "df_ccm_reqb.Node4.wrsizedfullncposted", + "EventCode": "0x8c", + "BriefDescription": "Data Fabric CCM Performance Monitor Event DF CCM Request Ordered wrsizedfullncposted", + "UMask": "0x83" + }, + { + "EventName": "df_ccm_reqb.Node5.wrsizedfullncposted", + "EventCode": "0x8c", + "BriefDescription": "Data Fabric CCM Performance Monitor Event DF CCM Request Ordered wrsizedfullncposted", + "UMask": "0xA3" + }, + { + "EventName": "df_ccm_reqb.Node6.wrsizedfullncposted", + "EventCode": "0x8c", + "BriefDescription": "Data Fabric CCM Performance Monitor Event DF CCM Request Ordered wrsizedfullncposted", + "UMask": "0xC3" + }, + { + "EventName": "df_ccm_reqb.Node7.wrsizedfullncposted", + "EventCode": "0x8c", + "BriefDescription": "Data Fabric CCM Performance Monitor Event DF CCM Request Ordered wrsizedfullncposted", + "UMask": "0xE3" + }, + { + "EventName": "df_ccm_reqb.Node0.wrsizedncposted", + "EventCode": "0x8c", + "BriefDescription": "Data Fabric CCM Performance Monitor Event DF CCM Request Ordered wrsizedncposted", + "UMask": "0x02" + }, + { + "EventName": "df_ccm_reqb.Node1.wrsizedncposted", + "EventCode": "0x8c", + "BriefDescription": "Data Fabric CCM Performance Monitor Event DF CCM Request Ordered wrsizedncposted", + "UMask": "0x22" + }, + { + "EventName": "df_ccm_reqb.Node2.wrsizedncposted", + "EventCode": "0x8c", + "BriefDescription": "Data Fabric CCM Performance Monitor Event DF CCM Request Ordered wrsizedncposted", + "UMask": "0x42" + }, + { + "EventName": "df_ccm_reqb.Node3.wrsizedncposted", + "EventCode": "0x8c", + "BriefDescription": "Data Fabric CCM Performance Monitor Event DF CCM Request Ordered wrsizedncposted", + "UMask": "0x62" + }, + { + "EventName": "df_ccm_reqb.Node4.wrsizedncposted", + "EventCode": "0x8c", + "BriefDescription": "Data Fabric CCM Performance Monitor Event DF CCM Request Ordered wrsizedncposted", + "UMask": "0x82" + }, + { + "EventName": "df_ccm_reqb.Node5.wrsizedncposted", + "EventCode": "0x8c", + "BriefDescription": "Data Fabric CCM Performance Monitor Event DF CCM Request Ordered wrsizedncposted", + "UMask": "0xA2" + }, + { + "EventName": "df_ccm_reqb.Node6.wrsizedncposted", + "EventCode": "0x8c", + "BriefDescription": "Data Fabric CCM Performance Monitor Event DF CCM Request Ordered wrsizedncposted", + "UMask": "0xC2" + }, + { + "EventName": "df_ccm_reqb.Node7.wrsizedncposted", + "EventCode": "0x8c", + "BriefDescription": "Data Fabric CCM Performance Monitor Event DF CCM Request Ordered wrsizedncposted", + "UMask": "0xE2" + }, + { + "EventName": "df_ccm_reqb.Node0.rdsized", + "EventCode": "0x8c", + "BriefDescription": "Data Fabric CCM Performance Monitor Event DF CCM Request Ordered rdsized", + "UMask": "0x01" + }, + { + "EventName": "df_ccm_reqb.Node1.rdsized", + "EventCode": "0x8c", + "BriefDescription": "Data Fabric CCM Performance Monitor Event DF CCM Request Ordered rdsized", + "UMask": "0x21" + }, + { + "EventName": "df_ccm_reqb.Node2.rdsized", + "EventCode": "0x8c", + "BriefDescription": "Data Fabric CCM Performance Monitor Event DF CCM Request Ordered rdsized", + "UMask": "0x41" + }, + { + "EventName": "df_ccm_reqb.Node3.rdsized", + "EventCode": "0x8c", + "BriefDescription": "Data Fabric CCM Performance Monitor Event DF CCM Request Ordered rdsized", + "UMask": "0x61" + }, + { + "EventName": "df_ccm_reqb.Node4.rdsized", + "EventCode": "0x8c", + "BriefDescription": "Data Fabric CCM Performance Monitor Event DF CCM Request Ordered rdsized", + "UMask": "0x81" + }, + { + "EventName": "df_ccm_reqb.Node5.rdsized", + "EventCode": "0x8c", + "BriefDescription": "Data Fabric CCM Performance Monitor Event DF CCM Request Ordered rdsized", + "UMask": "0xA1" + }, + { + "EventName": "df_ccm_reqb.Node6.rdsized", + "EventCode": "0x8c", + "BriefDescription": "Data Fabric CCM Performance Monitor Event DF CCM Request Ordered rdsized", + "UMask": "0xC1" + }, + { + "EventName": "df_ccm_reqb.Node7.rdsized", + "EventCode": "0x8c", + "BriefDescription": "Data Fabric CCM Performance Monitor Event DF CCM Request Ordered rdsized", + "UMask": "0xE1" + }, + { + "EventName": "df_ccm_reqc.apicaccess", + "EventCode": "0x08D", + "BriefDescription": "Data Fabric CCM Performance Monitor Event DF CCM Request Type C (PIE Requests)APIC access", + "UMask": "0x01" + }, + { + "EventName": "df_ccm_reqc.apicucodeaccess", + "EventCode": "0x08D", + "BriefDescription": "Data Fabric CCM Performance Monitor Event DF CCM Request Type C (PIE Requests)APIC ucode access", + "UMask": "0x02" + }, + { + "EventName": "df_ccm_reqc.fasttprwrite", + "EventCode": "0x08D", + "BriefDescription": "Data Fabric CCM Performance Monitor Event DF CCM Request Type C (PIE Requests)Fast TPR write", + "UMask": "0x03" + }, + { + "EventName": "df_ccm_reqc.anybuslockrequest", + "EventCode": "0x08D", + "BriefDescription": "Data Fabric CCM Performance Monitor Event DF CCM Request Type C (PIE Requests)APIC access Any Bus Lock request", + "UMask": "0x04" + }, + { + "EventName": "df_ioms_reqa.Node0.masterabort", + "EventCode": "0x108", + "BriefDescription": "Data Fabric CCM Performance Monitor Event DF IOMS Request Type A (DRAM) masterabort", + "UMask": "0x0C" + }, + { + "EventName": "df_ioms_reqa.Node1.masterabort", + "EventCode": "0x108", + "BriefDescription": "Data Fabric CCM Performance Monitor Event DF IOMS Request Type A (DRAM) masterabort", + "UMask": "0x2C" + }, + { + "EventName": "df_ioms_reqa.Node2.masterabort", + "EventCode": "0x108", + "BriefDescription": "Data Fabric CCM Performance Monitor Event DF IOMS Request Type A (DRAM) masterabort", + "UMask": "0x4C" + }, + { + "EventName": "df_ioms_reqa.Node3.masterabort", + "EventCode": "0x108", + "BriefDescription": "Data Fabric CCM Performance Monitor Event DF IOMS Request Type A (DRAM) masterabort", + "UMask": "0x6C" + }, + { + "EventName": "df_ioms_reqa.Node4.masterabort", + "EventCode": "0x108", + "BriefDescription": "Data Fabric CCM Performance Monitor Event DF IOMS Request Type A (DRAM) masterabort", + "UMask": "0x8C" + }, + { + "EventName": "df_ioms_reqa.Node5.masterabort", + "EventCode": "0x108", + "BriefDescription": "Data Fabric CCM Performance Monitor Event DF IOMS Request Type A (DRAM) masterabort", + "UMask": "0xAC" + }, + { + "EventName": "df_ioms_reqa.Node6.masterabort", + "EventCode": "0x108", + "BriefDescription": "Data Fabric CCM Performance Monitor Event DF IOMS Request Type A (DRAM) masterabort", + "UMask": "0xCC" + }, + { + "EventName": "df_ioms_reqa.Node7.masterabort", + "EventCode": "0x108", + "BriefDescription": "Data Fabric CCM Performance Monitor Event DF IOMS Request Type A (DRAM) masterabort", + "UMask": "0xEC" + }, + { + "EventName": "df_ioms_reqa.Node0.ios_resp", + "EventCode": "0x108", + "BriefDescription": "Data Fabric CCM Performance Monitor Event DF IOMS Request Type A (DRAM) ios_resp", + "UMask": "0x0B" + }, + { + "EventName": "df_ioms_reqa.Node1.ios_resp", + "EventCode": "0x108", + "BriefDescription": "Data Fabric CCM Performance Monitor Event DF IOMS Request Type A (DRAM) ios_resp", + "UMask": "0x2B" + }, + { + "EventName": "df_ioms_reqa.Node2.ios_resp", + "EventCode": "0x108", + "BriefDescription": "Data Fabric CCM Performance Monitor Event DF IOMS Request Type A (DRAM) ios_resp", + "UMask": "0x4B" + }, + { + "EventName": "df_ioms_reqa.Node3.ios_resp", + "EventCode": "0x108", + "BriefDescription": "Data Fabric CCM Performance Monitor Event DF IOMS Request Type A (DRAM) ios_resp", + "UMask": "0x6B" + }, + { + "EventName": "df_ioms_reqa.Node4.ios_resp", + "EventCode": "0x108", + "BriefDescription": "Data Fabric CCM Performance Monitor Event DF IOMS Request Type A (DRAM) ios_resp", + "UMask": "0x8B" + }, + { + "EventName": "df_ioms_reqa.Node5.ios_resp", + "EventCode": "0x108", + "BriefDescription": "Data Fabric CCM Performance Monitor Event DF IOMS Request Type A (DRAM) ios_resp", + "UMask": "0xAB" + }, + { + "EventName": "df_ioms_reqa.Node6.ios_resp", + "EventCode": "0x108", + "BriefDescription": "Data Fabric CCM Performance Monitor Event DF IOMS Request Type A (DRAM) ios_resp", + "UMask": "0xCB" + }, + { + "EventName": "df_ioms_reqa.Node7.ios_resp", + "EventCode": "0x108", + "BriefDescription": "Data Fabric CCM Performance Monitor Event DF IOMS Request Type A (DRAM) ios_resp", + "UMask": "0xEB" + }, + { + "EventName": "df_ioms_reqa.Node0.flush", + "EventCode": "0x108", + "BriefDescription": "Data Fabric CCM Performance Monitor Event DF IOMS Request Type A (DRAM) flush", + "UMask": "0x0A" + }, + { + "EventName": "df_ioms_reqa.Node1.flush", + "EventCode": "0x108", + "BriefDescription": "Data Fabric CCM Performance Monitor Event DF IOMS Request Type A (DRAM) flush", + "UMask": "0x2A" + }, + { + "EventName": "df_ioms_reqa.Node2.flush", + "EventCode": "0x108", + "BriefDescription": "Data Fabric CCM Performance Monitor Event DF IOMS Request Type A (DRAM) flush", + "UMask": "0x4A" + }, + { + "EventName": "df_ioms_reqa.Node3.flush", + "EventCode": "0x108", + "BriefDescription": "Data Fabric CCM Performance Monitor Event DF IOMS Request Type A (DRAM) flush", + "UMask": "0x6A" + }, + { + "EventName": "df_ioms_reqa.Node4.flush", + "EventCode": "0x108", + "BriefDescription": "Data Fabric CCM Performance Monitor Event DF IOMS Request Type A (DRAM) flush", + "UMask": "0x8A" + }, + { + "EventName": "df_ioms_reqa.Node5.flush", + "EventCode": "0x108", + "BriefDescription": "Data Fabric CCM Performance Monitor Event DF IOMS Request Type A (DRAM) flush", + "UMask": "0xAA" + }, + { + "EventName": "df_ioms_reqa.Node6.flush", + "EventCode": "0x108", + "BriefDescription": "Data Fabric CCM Performance Monitor Event DF IOMS Request Type A (DRAM) flush", + "UMask": "0xCA" + }, + { + "EventName": "df_ioms_reqa.Node7.flush", + "EventCode": "0x108", + "BriefDescription": "Data Fabric CCM Performance Monitor Event DF IOMS Request Type A (DRAM) flush", + "UMask": "0xEA" + }, + { + "EventName": "df_ioms_reqa.Node0.fence", + "EventCode": "0x108", + "BriefDescription": "Data Fabric CCM Performance Monitor Event DF IOMS Request Type A (DRAM) fence", + "UMask": "0x09" + }, + { + "EventName": "df_ioms_reqa.Node1.fence", + "EventCode": "0x108", + "BriefDescription": "Data Fabric CCM Performance Monitor Event DF IOMS Request Type A (DRAM) fence", + "UMask": "0x29" + }, + { + "EventName": "df_ioms_reqa.Node2.fence", + "EventCode": "0x108", + "BriefDescription": "Data Fabric CCM Performance Monitor Event DF IOMS Request Type A (DRAM) fence", + "UMask": "0x49" + }, + { + "EventName": "df_ioms_reqa.Node3.fence", + "EventCode": "0x108", + "BriefDescription": "Data Fabric CCM Performance Monitor Event DF IOMS Request Type A (DRAM) fence", + "UMask": "0x69" + }, + { + "EventName": "df_ioms_reqa.Node4.fence", + "EventCode": "0x108", + "BriefDescription": "Data Fabric CCM Performance Monitor Event DF IOMS Request Type A (DRAM) fence", + "UMask": "0x89" + }, + { + "EventName": "df_ioms_reqa.Node5.fence", + "EventCode": "0x108", + "BriefDescription": "Data Fabric CCM Performance Monitor Event DF IOMS Request Type A (DRAM) fence", + "UMask": "0xA9" + }, + { + "EventName": "df_ioms_reqa.Node6.fence", + "EventCode": "0x108", + "BriefDescription": "Data Fabric CCM Performance Monitor Event DF IOMS Request Type A (DRAM) fence", + "UMask": "0xC9" + }, + { + "EventName": "df_ioms_reqa.Node7.fence", + "EventCode": "0x108", + "BriefDescription": "Data Fabric CCM Performance Monitor Event DF IOMS Request Type A (DRAM) fence", + "UMask": "0xE9" + }, + { + "EventName": "df_ioms_reqa.Node0.anydramtransaction", + "EventCode": "0x108", + "BriefDescription": "Data Fabric CCM Performance Monitor Event DF IOMS Request Type A (DRAM) anydramtransaction", + "UMask": "0x08" + }, + { + "EventName": "df_ioms_reqa.Node1.anydramtransaction", + "EventCode": "0x108", + "BriefDescription": "Data Fabric CCM Performance Monitor Event DF IOMS Request Type A (DRAM) anydramtransaction", + "UMask": "0x28" + }, + { + "EventName": "df_ioms_reqa.Node2.anydramtransaction", + "EventCode": "0x108", + "BriefDescription": "Data Fabric CCM Performance Monitor Event DF IOMS Request Type A (DRAM) anydramtransaction", + "UMask": "0x48" + }, + { + "EventName": "df_ioms_reqa.Node3.anydramtransaction", + "EventCode": "0x108", + "BriefDescription": "Data Fabric CCM Performance Monitor Event DF IOMS Request Type A (DRAM) anydramtransaction", + "UMask": "0x68" + }, + { + "EventName": "df_ioms_reqa.Node4.anydramtransaction", + "EventCode": "0x108", + "BriefDescription": "Data Fabric CCM Performance Monitor Event DF IOMS Request Type A (DRAM) anydramtransaction", + "UMask": "0x88" + }, + { + "EventName": "df_ioms_reqa.Node5.anydramtransaction", + "EventCode": "0x108", + "BriefDescription": "Data Fabric CCM Performance Monitor Event DF IOMS Request Type A (DRAM) anydramtransaction", + "UMask": "0xA8" + }, + { + "EventName": "df_ioms_reqa.Node6.anydramtransaction", + "EventCode": "0x108", + "BriefDescription": "Data Fabric CCM Performance Monitor Event DF IOMS Request Type A (DRAM) anydramtransaction", + "UMask": "0xC8" + }, + { + "EventName": "df_ioms_reqa.Node7.anydramtransaction", + "EventCode": "0x108", + "BriefDescription": "Data Fabric CCM Performance Monitor Event DF IOMS Request Type A (DRAM) anydramtransaction", + "UMask": "0xE8" + }, + { + "EventName": "df_ioms_reqa.Node0.anyatomic", + "EventCode": "0x108", + "BriefDescription": "Data Fabric CCM Performance Monitor Event DF IOMS Request Type A (DRAM) anyatomic", + "UMask": "0x07" + }, + { + "EventName": "df_ioms_reqa.Node1.anyatomic", + "EventCode": "0x108", + "BriefDescription": "Data Fabric CCM Performance Monitor Event DF IOMS Request Type A (DRAM) anyatomic", + "UMask": "0x27" + }, + { + "EventName": "df_ioms_reqa.Node2.anyatomic", + "EventCode": "0x108", + "BriefDescription": "Data Fabric CCM Performance Monitor Event DF IOMS Request Type A (DRAM) anyatomic", + "UMask": "0x47" + }, + { + "EventName": "df_ioms_reqa.Node3.anyatomic", + "EventCode": "0x108", + "BriefDescription": "Data Fabric CCM Performance Monitor Event DF IOMS Request Type A (DRAM) anyatomic", + "UMask": "0x67" + }, + { + "EventName": "df_ioms_reqa.Node4.anyatomic", + "EventCode": "0x108", + "BriefDescription": "Data Fabric CCM Performance Monitor Event DF IOMS Request Type A (DRAM) anyatomic", + "UMask": "0x87" + }, + { + "EventName": "df_ioms_reqa.Node5.anyatomic", + "EventCode": "0x108", + "BriefDescription": "Data Fabric CCM Performance Monitor Event DF IOMS Request Type A (DRAM) anyatomic", + "UMask": "0xA7" + }, + { + "EventName": "df_ioms_reqa.Node6.anyatomic", + "EventCode": "0x108", + "BriefDescription": "Data Fabric CCM Performance Monitor Event DF IOMS Request Type A (DRAM) anyatomic", + "UMask": "0xC7" + }, + { + "EventName": "df_ioms_reqa.Node7.anyatomic", + "EventCode": "0x108", + "BriefDescription": "Data Fabric CCM Performance Monitor Event DF IOMS Request Type A (DRAM) anyatomic", + "UMask": "0xE7" + }, + { + "EventName": "df_ioms_reqa.Node0.anywrsized=64b", + "EventCode": "0x108", + "BriefDescription": "Data Fabric CCM Performance Monitor Event DF IOMS Request Type A (DRAM) anywrsized=64b", + "UMask": "0x06" + }, + { + "EventName": "df_ioms_reqa.Node1.anywrsized=64b", + "EventCode": "0x108", + "BriefDescription": "Data Fabric CCM Performance Monitor Event DF IOMS Request Type A (DRAM) anywrsized=64b", + "UMask": "0x26" + }, + { + "EventName": "df_ioms_reqa.Node2.anywrsized=64b", + "EventCode": "0x108", + "BriefDescription": "Data Fabric CCM Performance Monitor Event DF IOMS Request Type A (DRAM) anywrsized=64b", + "UMask": "0x46" + }, + { + "EventName": "df_ioms_reqa.Node3.anywrsized=64b", + "EventCode": "0x108", + "BriefDescription": "Data Fabric CCM Performance Monitor Event DF IOMS Request Type A (DRAM) anywrsized=64b", + "UMask": "0x66" + }, + { + "EventName": "df_ioms_reqa.Node4.anywrsized=64b", + "EventCode": "0x108", + "BriefDescription": "Data Fabric CCM Performance Monitor Event DF IOMS Request Type A (DRAM) anywrsized=64b", + "UMask": "0x86" + }, + { + "EventName": "df_ioms_reqa.Node5.anywrsized=64b", + "EventCode": "0x108", + "BriefDescription": "Data Fabric CCM Performance Monitor Event DF IOMS Request Type A (DRAM) anywrsized=64b", + "UMask": "0xA6" + }, + { + "EventName": "df_ioms_reqa.Node6.anywrsized=64b", + "EventCode": "0x108", + "BriefDescription": "Data Fabric CCM Performance Monitor Event DF IOMS Request Type A (DRAM) anywrsized=64b", + "UMask": "0xC6" + }, + { + "EventName": "df_ioms_reqa.Node7.anywrsized=64b", + "EventCode": "0x108", + "BriefDescription": "Data Fabric CCM Performance Monitor Event DF IOMS Request Type A (DRAM) anywrsized=64b", + "UMask": "0xE6" + }, + { + "EventName": "df_ioms_reqa.Node0.anywrsized>32band<64b", + "EventCode": "0x108", + "BriefDescription": "Data Fabric CCM Performance Monitor Event DF IOMS Request Type A (DRAM) anywrsized>32band<64b", + "UMask": "0x05" + }, + { + "EventName": "df_ioms_reqa.Node1.anywrsized>32band<64b", + "EventCode": "0x108", + "BriefDescription": "Data Fabric CCM Performance Monitor Event DF IOMS Request Type A (DRAM) anywrsized>32band<64b", + "UMask": "0x25" + }, + { + "EventName": "df_ioms_reqa.Node2.anywrsized>32band<64b", + "EventCode": "0x108", + "BriefDescription": "Data Fabric CCM Performance Monitor Event DF IOMS Request Type A (DRAM) anywrsized>32band<64b", + "UMask": "0x45" + }, + { + "EventName": "df_ioms_reqa.Node3.anywrsized>32band<64b", + "EventCode": "0x108", + "BriefDescription": "Data Fabric CCM Performance Monitor Event DF IOMS Request Type A (DRAM) anywrsized>32band<64b", + "UMask": "0x65" + }, + { + "EventName": "df_ioms_reqa.Node4.anywrsized>32band<64b", + "EventCode": "0x108", + "BriefDescription": "Data Fabric CCM Performance Monitor Event DF IOMS Request Type A (DRAM) anywrsized>32band<64b", + "UMask": "0x85" + }, + { + "EventName": "df_ioms_reqa.Node5.anywrsized>32band<64b", + "EventCode": "0x108", + "BriefDescription": "Data Fabric CCM Performance Monitor Event DF IOMS Request Type A (DRAM) anywrsized>32band<64b", + "UMask": "0xA5" + }, + { + "EventName": "df_ioms_reqa.Node6.anywrsized>32band<64b", + "EventCode": "0x108", + "BriefDescription": "Data Fabric CCM Performance Monitor Event DF IOMS Request Type A (DRAM) anywrsized>32band<64b", + "UMask": "0xC5" + }, + { + "EventName": "df_ioms_reqa.Node7.anywrsized>32band<64b", + "EventCode": "0x108", + "BriefDescription": "Data Fabric CCM Performance Monitor Event DF IOMS Request Type A (DRAM) anywrsized>32band<64b", + "UMask": "0xE5" + }, + { + "EventName": "df_ioms_reqa.Node0.anywrsized=32b", + "EventCode": "0x108", + "BriefDescription": "Data Fabric CCM Performance Monitor Event DF IOMS Request Type A (DRAM) anywrsized=32b", + "UMask": "0x04" + }, + { + "EventName": "df_ioms_reqa.Node1.anywrsized=32b", + "EventCode": "0x108", + "BriefDescription": "Data Fabric CCM Performance Monitor Event DF IOMS Request Type A (DRAM) anywrsized=32b", + "UMask": "0x24" + }, + { + "EventName": "df_ioms_reqa.Node2.anywrsized=32b", + "EventCode": "0x108", + "BriefDescription": "Data Fabric CCM Performance Monitor Event DF IOMS Request Type A (DRAM) anywrsized=32b", + "UMask": "0x44" + }, + { + "EventName": "df_ioms_reqa.Node3.anywrsized=32b", + "EventCode": "0x108", + "BriefDescription": "Data Fabric CCM Performance Monitor Event DF IOMS Request Type A (DRAM) anywrsized=32b", + "UMask": "0x64" + }, + { + "EventName": "df_ioms_reqa.Node4.anywrsized=32b", + "EventCode": "0x108", + "BriefDescription": "Data Fabric CCM Performance Monitor Event DF IOMS Request Type A (DRAM) anywrsized=32b", + "UMask": "0x84" + }, + { + "EventName": "df_ioms_reqa.Node5.anywrsized=32b", + "EventCode": "0x108", + "BriefDescription": "Data Fabric CCM Performance Monitor Event DF IOMS Request Type A (DRAM) anywrsized=32b", + "UMask": "0xA4" + }, + { + "EventName": "df_ioms_reqa.Node6.anywrsized=32b", + "EventCode": "0x108", + "BriefDescription": "Data Fabric CCM Performance Monitor Event DF IOMS Request Type A (DRAM) anywrsized=32b", + "UMask": "0xC4" + }, + { + "EventName": "df_ioms_reqa.Node7.anywrsized=32b", + "EventCode": "0x108", + "BriefDescription": "Data Fabric CCM Performance Monitor Event DF IOMS Request Type A (DRAM) anywrsized=32b", + "UMask": "0xE4" + }, + { + "EventName": "df_ioms_reqa.Node0.anywrsized<32b", + "EventCode": "0x108", + "BriefDescription": "Data Fabric CCM Performance Monitor Event DF IOMS Request Type A (DRAM) anywrsized<32b", + "UMask": "0x03" + }, + { + "EventName": "df_ioms_reqa.Node1.anywrsized<32b", + "EventCode": "0x108", + "BriefDescription": "Data Fabric CCM Performance Monitor Event DF IOMS Request Type A (DRAM) anywrsized<32b", + "UMask": "0x23" + }, + { + "EventName": "df_ioms_reqa.Node2.anywrsized<32b", + "EventCode": "0x108", + "BriefDescription": "Data Fabric CCM Performance Monitor Event DF IOMS Request Type A (DRAM) anywrsized<32b", + "UMask": "0x43" + }, + { + "EventName": "df_ioms_reqa.Node3.anywrsized<32b", + "EventCode": "0x108", + "BriefDescription": "Data Fabric CCM Performance Monitor Event DF IOMS Request Type A (DRAM) anywrsized<32b", + "UMask": "0x63" + }, + { + "EventName": "df_ioms_reqa.Node4.anywrsized<32b", + "EventCode": "0x108", + "BriefDescription": "Data Fabric CCM Performance Monitor Event DF IOMS Request Type A (DRAM) anywrsized<32b", + "UMask": "0x83" + }, + { + "EventName": "df_ioms_reqa.Node5.anywrsized<32b", + "EventCode": "0x108", + "BriefDescription": "Data Fabric CCM Performance Monitor Event DF IOMS Request Type A (DRAM) anywrsized<32b", + "UMask": "0xA3" + }, + { + "EventName": "df_ioms_reqa.Node6.anywrsized<32b", + "EventCode": "0x108", + "BriefDescription": "Data Fabric CCM Performance Monitor Event DF IOMS Request Type A (DRAM) anywrsized<32b", + "UMask": "0xC3" + }, + { + "EventName": "df_ioms_reqa.Node7.anywrsized<32b", + "EventCode": "0x108", + "BriefDescription": "Data Fabric CCM Performance Monitor Event DF IOMS Request Type A (DRAM) anywrsized<32b", + "UMask": "0xE3" + }, + { + "EventName": "df_ioms_reqa.Node0.anyrdsized", + "EventCode": "0x108", + "BriefDescription": "Data Fabric CCM Performance Monitor Event DF IOMS Request Type A (DRAM) anyrdsized", + "UMask": "0x02" + }, + { + "EventName": "df_ioms_reqa.Node1.anyrdsized", + "EventCode": "0x108", + "BriefDescription": "Data Fabric CCM Performance Monitor Event DF IOMS Request Type A (DRAM) anyrdsized", + "UMask": "0x22" + }, + { + "EventName": "df_ioms_reqa.Node2.anyrdsized", + "EventCode": "0x108", + "BriefDescription": "Data Fabric CCM Performance Monitor Event DF IOMS Request Type A (DRAM) anyrdsized", + "UMask": "0x42" + }, + { + "EventName": "df_ioms_reqa.Node3.anyrdsized", + "EventCode": "0x108", + "BriefDescription": "Data Fabric CCM Performance Monitor Event DF IOMS Request Type A (DRAM) anyrdsized", + "UMask": "0x62" + }, + { + "EventName": "df_ioms_reqa.Node4.anyrdsized", + "EventCode": "0x108", + "BriefDescription": "Data Fabric CCM Performance Monitor Event DF IOMS Request Type A (DRAM) anyrdsized", + "UMask": "0x82" + }, + { + "EventName": "df_ioms_reqa.Node5.anyrdsized", + "EventCode": "0x108", + "BriefDescription": "Data Fabric CCM Performance Monitor Event DF IOMS Request Type A (DRAM) anyrdsized", + "UMask": "0xA2" + }, + { + "EventName": "df_ioms_reqa.Node6.anyrdsized", + "EventCode": "0x108", + "BriefDescription": "Data Fabric CCM Performance Monitor Event DF IOMS Request Type A (DRAM) anyrdsized", + "UMask": "0xC2" + }, + { + "EventName": "df_ioms_reqa.Node7.anyrdsized", + "EventCode": "0x108", + "BriefDescription": "Data Fabric CCM Performance Monitor Event DF IOMS Request Type A (DRAM) anyrdsized", + "UMask": "0xE2" + }, + { + "EventName": "df_ioms_reqa.Node0.largeread", + "EventCode": "0x108", + "BriefDescription": "Data Fabric CCM Performance Monitor Event DF IOMS Request Type A (DRAM) largeread", + "UMask": "0x01" + }, + { + "EventName": "df_ioms_reqa.Node1.largeread", + "EventCode": "0x108", + "BriefDescription": "Data Fabric CCM Performance Monitor Event DF IOMS Request Type A (DRAM) largeread", + "UMask": "0x21" + }, + { + "EventName": "df_ioms_reqa.Node2.largeread", + "EventCode": "0x108", + "BriefDescription": "Data Fabric CCM Performance Monitor Event DF IOMS Request Type A (DRAM) largeread", + "UMask": "0x41" + }, + { + "EventName": "df_ioms_reqa.Node3.largeread", + "EventCode": "0x108", + "BriefDescription": "Data Fabric CCM Performance Monitor Event DF IOMS Request Type A (DRAM) largeread", + "UMask": "0x61" + }, + { + "EventName": "df_ioms_reqa.Node4.largeread", + "EventCode": "0x108", + "BriefDescription": "Data Fabric CCM Performance Monitor Event DF IOMS Request Type A (DRAM) largeread", + "UMask": "0x81" + }, + { + "EventName": "df_ioms_reqa.Node5.largeread", + "EventCode": "0x108", + "BriefDescription": "Data Fabric CCM Performance Monitor Event DF IOMS Request Type A (DRAM) largeread", + "UMask": "0xA1" + }, + { + "EventName": "df_ioms_reqa.Node6.largeread", + "EventCode": "0x108", + "BriefDescription": "Data Fabric CCM Performance Monitor Event DF IOMS Request Type A (DRAM) largeread", + "UMask": "0xC1" + }, + { + "EventName": "df_ioms_reqa.Node7.largeread", + "EventCode": "0x108", + "BriefDescription": "Data Fabric CCM Performance Monitor Event DF IOMS Request Type A (DRAM) largeread", + "UMask": "0xE1" + }, + { + "EventName": "df_ioms_reqb.Node0.pieiorequest", + "EventCode": "0x109", + "BriefDescription": "Data Fabric CCM Performance Monitor Event DF IOMS Request Type B (IO and PIE Requests) Any DRAM transaction", + "UMask": "0x0F" + }, + { + "EventName": "df_ioms_reqb.Node1.pieiorequest", + "EventCode": "0x109", + "BriefDescription": "Data Fabric CCM Performance Monitor Event DF IOMS Request Type B (IO and PIE Requests) Any DRAM transaction", + "UMask": "0x2F" + }, + { + "EventName": "df_ioms_reqb.Node2.pieiorequest", + "EventCode": "0x109", + "BriefDescription": "Data Fabric CCM Performance Monitor Event DF IOMS Request Type B (IO and PIE Requests) Any DRAM transaction", + "UMask": "0x4F" + }, + { + "EventName": "df_ioms_reqb.Node3.pieiorequest", + "EventCode": "0x109", + "BriefDescription": "Data Fabric CCM Performance Monitor Event DF IOMS Request Type B (IO and PIE Requests) Any DRAM transaction", + "UMask": "0x6F" + }, + { + "EventName": "df_ioms_reqb.Node4.pieiorequest", + "EventCode": "0x109", + "BriefDescription": "Data Fabric CCM Performance Monitor Event DF IOMS Request Type B (IO and PIE Requests) Any DRAM transaction", + "UMask": "0x8F" + }, + { + "EventName": "df_ioms_reqb.Node5.pieiorequest", + "EventCode": "0x109", + "BriefDescription": "Data Fabric CCM Performance Monitor Event DF IOMS Request Type B (IO and PIE Requests) Any DRAM transaction", + "UMask": "0xAF" + }, + { + "EventName": "df_ioms_reqb.Node6.pieiorequest", + "EventCode": "0x109", + "BriefDescription": "Data Fabric CCM Performance Monitor Event DF IOMS Request Type B (IO and PIE Requests) Any DRAM transaction", + "UMask": "0xCF" + }, + { + "EventName": "df_ioms_reqb.Node7.pieiorequest", + "EventCode": "0x109", + "BriefDescription": "Data Fabric CCM Performance Monitor Event DF IOMS Request Type B (IO and PIE Requests) Any DRAM transaction", + "UMask": "0xEF" + }, + { + "EventName": "df_ioms_reqb.Node0.piesystemmanagement", + "EventCode": "0x109", + "BriefDescription": "Data Fabric CCM Performance Monitor Event DF IOMS Request Type B (IO and PIE Requests) Ordered piesystemmanagement", + "UMask": "0x0E" + }, + { + "EventName": "df_ioms_reqb.Node1.piesystemmanagement", + "EventCode": "0x109", + "BriefDescription": "Data Fabric CCM Performance Monitor Event DF IOMS Request Type B (IO and PIE Requests) Ordered piesystemmanagement", + "UMask": "0x2E" + }, + { + "EventName": "df_ioms_reqb.Node2.piesystemmanagement", + "EventCode": "0x109", + "BriefDescription": "Data Fabric CCM Performance Monitor Event DF IOMS Request Type B (IO and PIE Requests) Ordered piesystemmanagement", + "UMask": "0x4E" + }, + { + "EventName": "df_ioms_reqb.Node3.piesystemmanagement", + "EventCode": "0x109", + "BriefDescription": "Data Fabric CCM Performance Monitor Event DF IOMS Request Type B (IO and PIE Requests) Ordered piesystemmanagement", + "UMask": "0x6E" + }, + { + "EventName": "df_ioms_reqb.Node4.piesystemmanagement", + "EventCode": "0x109", + "BriefDescription": "Data Fabric CCM Performance Monitor Event DF IOMS Request Type B (IO and PIE Requests) Ordered piesystemmanagement", + "UMask": "0x8E" + }, + { + "EventName": "df_ioms_reqb.Node5.piesystemmanagement", + "EventCode": "0x109", + "BriefDescription": "Data Fabric CCM Performance Monitor Event DF IOMS Request Type B (IO and PIE Requests) Ordered piesystemmanagement", + "UMask": "0xAE" + }, + { + "EventName": "df_ioms_reqb.Node6.piesystemmanagement", + "EventCode": "0x109", + "BriefDescription": "Data Fabric CCM Performance Monitor Event DF IOMS Request Type B (IO and PIE Requests) Ordered piesystemmanagement", + "UMask": "0xCE" + }, + { + "EventName": "df_ioms_reqb.Node7.piesystemmanagement", + "EventCode": "0x109", + "BriefDescription": "Data Fabric CCM Performance Monitor Event DF IOMS Request Type B (IO and PIE Requests) Ordered piesystemmanagement", + "UMask": "0xEE" + }, + { + "EventName": "df_ioms_reqb.Node0.pieinterrupt", + "EventCode": "0x109", + "BriefDescription": "Data Fabric CCM Performance Monitor Event DF IOMS Request Type B (IO and PIE Requests) Ordered pieinterrupt", + "UMask": "0x0D" + }, + { + "EventName": "df_ioms_reqb.Node1.pieinterrupt", + "EventCode": "0x109", + "BriefDescription": "Data Fabric CCM Performance Monitor Event DF IOMS Request Type B (IO and PIE Requests) Ordered pieinterrupt", + "UMask": "0x2D" + }, + { + "EventName": "df_ioms_reqb.Node2.pieinterrupt", + "EventCode": "0x109", + "BriefDescription": "Data Fabric CCM Performance Monitor Event DF IOMS Request Type B (IO and PIE Requests) Ordered pieinterrupt", + "UMask": "0x4D" + }, + { + "EventName": "df_ioms_reqb.Node3.pieinterrupt", + "EventCode": "0x109", + "BriefDescription": "Data Fabric CCM Performance Monitor Event DF IOMS Request Type B (IO and PIE Requests) Ordered pieinterrupt", + "UMask": "0x6D" + }, + { + "EventName": "df_ioms_reqb.Node4.pieinterrupt", + "EventCode": "0x109", + "BriefDescription": "Data Fabric CCM Performance Monitor Event DF IOMS Request Type B (IO and PIE Requests) Ordered pieinterrupt", + "UMask": "0x8D" + }, + { + "EventName": "df_ioms_reqb.Node5.pieinterrupt", + "EventCode": "0x109", + "BriefDescription": "Data Fabric CCM Performance Monitor Event DF IOMS Request Type B (IO and PIE Requests) Ordered pieinterrupt", + "UMask": "0xAD" + }, + { + "EventName": "df_ioms_reqb.Node6.pieinterrupt", + "EventCode": "0x109", + "BriefDescription": "Data Fabric CCM Performance Monitor Event DF IOMS Request Type B (IO and PIE Requests) Ordered pieinterrupt", + "UMask": "0xCD" + }, + { + "EventName": "df_ioms_reqb.Node7.pieinterrupt", + "EventCode": "0x109", + "BriefDescription": "Data Fabric CCM Performance Monitor Event DF IOMS Request Type B (IO and PIE Requests) Ordered pieinterrupt", + "UMask": "0xED" + }, + { + "EventName": "df_ioms_reqb.Node0.anyiotransaction", + "EventCode": "0x109", + "BriefDescription": "Data Fabric CCM Performance Monitor Event DF IOMS Request Type B (IO and PIE Requests) Ordered anyiotransaction", + "UMask": "0x0C" + }, + { + "EventName": "df_ioms_reqb.Node1.anyiotransaction", + "EventCode": "0x109", + "BriefDescription": "Data Fabric CCM Performance Monitor Event DF IOMS Request Type B (IO and PIE Requests) Ordered anyiotransaction", + "UMask": "0x2C" + }, + { + "EventName": "df_ioms_reqb.Node2.anyiotransaction", + "EventCode": "0x109", + "BriefDescription": "Data Fabric CCM Performance Monitor Event DF IOMS Request Type B (IO and PIE Requests) Ordered anyiotransaction", + "UMask": "0x4C" + }, + { + "EventName": "df_ioms_reqb.Node3.anyiotransaction", + "EventCode": "0x109", + "BriefDescription": "Data Fabric CCM Performance Monitor Event DF IOMS Request Type B (IO and PIE Requests) Ordered anyiotransaction", + "UMask": "0x6C" + }, + { + "EventName": "df_ioms_reqb.Node4.anyiotransaction", + "EventCode": "0x109", + "BriefDescription": "Data Fabric CCM Performance Monitor Event DF IOMS Request Type B (IO and PIE Requests) Ordered anyiotransaction", + "UMask": "0x8C" + }, + { + "EventName": "df_ioms_reqb.Node5.anyiotransaction", + "EventCode": "0x109", + "BriefDescription": "Data Fabric CCM Performance Monitor Event DF IOMS Request Type B (IO and PIE Requests) Ordered anyiotransaction", + "UMask": "0xAC" + }, + { + "EventName": "df_ioms_reqb.Node6.anyiotransaction", + "EventCode": "0x109", + "BriefDescription": "Data Fabric CCM Performance Monitor Event DF IOMS Request Type B (IO and PIE Requests) Ordered anyiotransaction", + "UMask": "0xCC" + }, + { + "EventName": "df_ioms_reqb.Node7.anyiotransaction", + "EventCode": "0x109", + "BriefDescription": "Data Fabric CCM Performance Monitor Event DF IOMS Request Type B (IO and PIE Requests) Ordered anyiotransaction", + "UMask": "0xEC" + }, + { + "EventName": "df_ioms_reqb.Node0.ioanyatomic", + "EventCode": "0x109", + "BriefDescription": "Data Fabric CCM Performance Monitor Event DF IOMS Request Type B (IO and PIE Requests) Ordered ioanyatomic", + "UMask": "0x0B" + }, + { + "EventName": "df_ioms_reqb.Node1.ioanyatomic", + "EventCode": "0x109", + "BriefDescription": "Data Fabric CCM Performance Monitor Event DF IOMS Request Type B (IO and PIE Requests) Ordered ioanyatomic", + "UMask": "0x2B" + }, + { + "EventName": "df_ioms_reqb.Node2.ioanyatomic", + "EventCode": "0x109", + "BriefDescription": "Data Fabric CCM Performance Monitor Event DF IOMS Request Type B (IO and PIE Requests) Ordered ioanyatomic", + "UMask": "0x4B" + }, + { + "EventName": "df_ioms_reqb.Node3.ioanyatomic", + "EventCode": "0x109", + "BriefDescription": "Data Fabric CCM Performance Monitor Event DF IOMS Request Type B (IO and PIE Requests) Ordered ioanyatomic", + "UMask": "0x6B" + }, + { + "EventName": "df_ioms_reqb.Node4.ioanyatomic", + "EventCode": "0x109", + "BriefDescription": "Data Fabric CCM Performance Monitor Event DF IOMS Request Type B (IO and PIE Requests) Ordered ioanyatomic", + "UMask": "0x8B" + }, + { + "EventName": "df_ioms_reqb.Node5.ioanyatomic", + "EventCode": "0x109", + "BriefDescription": "Data Fabric CCM Performance Monitor Event DF IOMS Request Type B (IO and PIE Requests) Ordered ioanyatomic", + "UMask": "0xAB" + }, + { + "EventName": "df_ioms_reqb.Node6.ioanyatomic", + "EventCode": "0x109", + "BriefDescription": "Data Fabric CCM Performance Monitor Event DF IOMS Request Type B (IO and PIE Requests) Ordered ioanyatomic", + "UMask": "0xCB" + }, + { + "EventName": "df_ioms_reqb.Node7.ioanyatomic", + "EventCode": "0x109", + "BriefDescription": "Data Fabric CCM Performance Monitor Event DF IOMS Request Type B (IO and PIE Requests) Ordered ioanyatomic", + "UMask": "0xEB" + }, + { + "EventName": "df_ioms_reqb.Node0.ioanynon-postedwrsized=64b", + "EventCode": "0x109", + "BriefDescription": "Data Fabric CCM Performance Monitor Event DF IOMS Request Type B (IO and PIE Requests) Ordered ioanynon-postedwrsized=64b", + "UMask": "0x0A" + }, + { + "EventName": "df_ioms_reqb.Node1.ioanynon-postedwrsized=64b", + "EventCode": "0x109", + "BriefDescription": "Data Fabric CCM Performance Monitor Event DF IOMS Request Type B (IO and PIE Requests) Ordered ioanynon-postedwrsized=64b", + "UMask": "0x2A" + }, + { + "EventName": "df_ioms_reqb.Node2.ioanynon-postedwrsized=64b", + "EventCode": "0x109", + "BriefDescription": "Data Fabric CCM Performance Monitor Event DF IOMS Request Type B (IO and PIE Requests) Ordered ioanynon-postedwrsized=64b", + "UMask": "0x4A" + }, + { + "EventName": "df_ioms_reqb.Node3.ioanynon-postedwrsized=64b", + "EventCode": "0x109", + "BriefDescription": "Data Fabric CCM Performance Monitor Event DF IOMS Request Type B (IO and PIE Requests) Ordered ioanynon-postedwrsized=64b", + "UMask": "0x6A" + }, + { + "EventName": "df_ioms_reqb.Node4.ioanynon-postedwrsized=64b", + "EventCode": "0x109", + "BriefDescription": "Data Fabric CCM Performance Monitor Event DF IOMS Request Type B (IO and PIE Requests) Ordered ioanynon-postedwrsized=64b", + "UMask": "0x8A" + }, + { + "EventName": "df_ioms_reqb.Node5.ioanynon-postedwrsized=64b", + "EventCode": "0x109", + "BriefDescription": "Data Fabric CCM Performance Monitor Event DF IOMS Request Type B (IO and PIE Requests) Ordered ioanynon-postedwrsized=64b", + "UMask": "0xAA" + }, + { + "EventName": "df_ioms_reqb.Node6.ioanynon-postedwrsized=64b", + "EventCode": "0x109", + "BriefDescription": "Data Fabric CCM Performance Monitor Event DF IOMS Request Type B (IO and PIE Requests) Ordered ioanynon-postedwrsized=64b", + "UMask": "0xCA" + }, + { + "EventName": "df_ioms_reqb.Node7.ioanynon-postedwrsized=64b", + "EventCode": "0x109", + "BriefDescription": "Data Fabric CCM Performance Monitor Event DF IOMS Request Type B (IO and PIE Requests) Ordered ioanynon-postedwrsized=64b", + "UMask": "0xEA" + }, + { + "EventName": "df_ioms_reqb.Node0.ioanynon-postedwrsized>32band<64b", + "EventCode": "0x109", + "BriefDescription": "Data Fabric CCM Performance Monitor Event DF IOMS Request Type B (IO and PIE Requests) Ordered ioanynon-postedwrsized>32band<64b", + "UMask": "0x09" + }, + { + "EventName": "df_ioms_reqb.Node1.ioanynon-postedwrsized>32band<64b", + "EventCode": "0x109", + "BriefDescription": "Data Fabric CCM Performance Monitor Event DF IOMS Request Type B (IO and PIE Requests) Ordered ioanynon-postedwrsized>32band<64b", + "UMask": "0x29" + }, + { + "EventName": "df_ioms_reqb.Node2.ioanynon-postedwrsized>32band<64b", + "EventCode": "0x109", + "BriefDescription": "Data Fabric CCM Performance Monitor Event DF IOMS Request Type B (IO and PIE Requests) Ordered ioanynon-postedwrsized>32band<64b", + "UMask": "0x49" + }, + { + "EventName": "df_ioms_reqb.Node3.ioanynon-postedwrsized>32band<64b", + "EventCode": "0x109", + "BriefDescription": "Data Fabric CCM Performance Monitor Event DF IOMS Request Type B (IO and PIE Requests) Ordered ioanynon-postedwrsized>32band<64b", + "UMask": "0x69" + }, + { + "EventName": "df_ioms_reqb.Node4.ioanynon-postedwrsized>32band<64b", + "EventCode": "0x109", + "BriefDescription": "Data Fabric CCM Performance Monitor Event DF IOMS Request Type B (IO and PIE Requests) Ordered ioanynon-postedwrsized>32band<64b", + "UMask": "0x89" + }, + { + "EventName": "df_ioms_reqb.Node5.ioanynon-postedwrsized>32band<64b", + "EventCode": "0x109", + "BriefDescription": "Data Fabric CCM Performance Monitor Event DF IOMS Request Type B (IO and PIE Requests) Ordered ioanynon-postedwrsized>32band<64b", + "UMask": "0xA9" + }, + { + "EventName": "df_ioms_reqb.Node6.ioanynon-postedwrsized>32band<64b", + "EventCode": "0x109", + "BriefDescription": "Data Fabric CCM Performance Monitor Event DF IOMS Request Type B (IO and PIE Requests) Ordered ioanynon-postedwrsized>32band<64b", + "UMask": "0xC9" + }, + { + "EventName": "df_ioms_reqb.Node7.ioanynon-postedwrsized>32band<64b", + "EventCode": "0x109", + "BriefDescription": "Data Fabric CCM Performance Monitor Event DF IOMS Request Type B (IO and PIE Requests) Ordered ioanynon-postedwrsized>32band<64b", + "UMask": "0xE9" + }, + { + "EventName": "df_ioms_reqb.Node0.ioanynon-postedwrsized=32b", + "EventCode": "0x109", + "BriefDescription": "Data Fabric CCM Performance Monitor Event DF IOMS Request Type B (IO and PIE Requests) Ordered ioanynon-postedwrsized=32b", + "UMask": "0x08" + }, + { + "EventName": "df_ioms_reqb.Node1.ioanynon-postedwrsized=32b", + "EventCode": "0x109", + "BriefDescription": "Data Fabric CCM Performance Monitor Event DF IOMS Request Type B (IO and PIE Requests) Ordered ioanynon-postedwrsized=32b", + "UMask": "0x28" + }, + { + "EventName": "df_ioms_reqb.Node2.ioanynon-postedwrsized=32b", + "EventCode": "0x109", + "BriefDescription": "Data Fabric CCM Performance Monitor Event DF IOMS Request Type B (IO and PIE Requests) Ordered ioanynon-postedwrsized=32b", + "UMask": "0x48" + }, + { + "EventName": "df_ioms_reqb.Node3.ioanynon-postedwrsized=32b", + "EventCode": "0x109", + "BriefDescription": "Data Fabric CCM Performance Monitor Event DF IOMS Request Type B (IO and PIE Requests) Ordered ioanynon-postedwrsized=32b", + "UMask": "0x68" + }, + { + "EventName": "df_ioms_reqb.Node4.ioanynon-postedwrsized=32b", + "EventCode": "0x109", + "BriefDescription": "Data Fabric CCM Performance Monitor Event DF IOMS Request Type B (IO and PIE Requests) Ordered ioanynon-postedwrsized=32b", + "UMask": "0x88" + }, + { + "EventName": "df_ioms_reqb.Node5.ioanynon-postedwrsized=32b", + "EventCode": "0x109", + "BriefDescription": "Data Fabric CCM Performance Monitor Event DF IOMS Request Type B (IO and PIE Requests) Ordered ioanynon-postedwrsized=32b", + "UMask": "0xA8" + }, + { + "EventName": "df_ioms_reqb.Node6.ioanynon-postedwrsized=32b", + "EventCode": "0x109", + "BriefDescription": "Data Fabric CCM Performance Monitor Event DF IOMS Request Type B (IO and PIE Requests) Ordered ioanynon-postedwrsized=32b", + "UMask": "0xC8" + }, + { + "EventName": "df_ioms_reqb.Node7.ioanynon-postedwrsized=32b", + "EventCode": "0x109", + "BriefDescription": "Data Fabric CCM Performance Monitor Event DF IOMS Request Type B (IO and PIE Requests) Ordered ioanynon-postedwrsized=32b", + "UMask": "0xE8" + }, + { + "EventName": "df_ioms_reqb.Node0.ioanynon-postedwrsized<32b", + "EventCode": "0x109", + "BriefDescription": "Data Fabric CCM Performance Monitor Event DF IOMS Request Type B (IO and PIE Requests) Ordered ioanynon-postedwrsized<32b", + "UMask": "0x07" + }, + { + "EventName": "df_ioms_reqb.Node1.ioanynon-postedwrsized<32b", + "EventCode": "0x109", + "BriefDescription": "Data Fabric CCM Performance Monitor Event DF IOMS Request Type B (IO and PIE Requests) Ordered ioanynon-postedwrsized<32b", + "UMask": "0x27" + }, + { + "EventName": "df_ioms_reqb.Node2.ioanynon-postedwrsized<32b", + "EventCode": "0x109", + "BriefDescription": "Data Fabric CCM Performance Monitor Event DF IOMS Request Type B (IO and PIE Requests) Ordered ioanynon-postedwrsized<32b", + "UMask": "0x47" + }, + { + "EventName": "df_ioms_reqb.Node3.ioanynon-postedwrsized<32b", + "EventCode": "0x109", + "BriefDescription": "Data Fabric CCM Performance Monitor Event DF IOMS Request Type B (IO and PIE Requests) Ordered ioanynon-postedwrsized<32b", + "UMask": "0x67" + }, + { + "EventName": "df_ioms_reqb.Node4.ioanynon-postedwrsized<32b", + "EventCode": "0x109", + "BriefDescription": "Data Fabric CCM Performance Monitor Event DF IOMS Request Type B (IO and PIE Requests) Ordered ioanynon-postedwrsized<32b", + "UMask": "0x87" + }, + { + "EventName": "df_ioms_reqb.Node5.ioanynon-postedwrsized<32b", + "EventCode": "0x109", + "BriefDescription": "Data Fabric CCM Performance Monitor Event DF IOMS Request Type B (IO and PIE Requests) Ordered ioanynon-postedwrsized<32b", + "UMask": "0xA7" + }, + { + "EventName": "df_ioms_reqb.Node6.ioanynon-postedwrsized<32b", + "EventCode": "0x109", + "BriefDescription": "Data Fabric CCM Performance Monitor Event DF IOMS Request Type B (IO and PIE Requests) Ordered ioanynon-postedwrsized<32b", + "UMask": "0xC7" + }, + { + "EventName": "df_ioms_reqb.Node7.ioanynon-postedwrsized<32b", + "EventCode": "0x109", + "BriefDescription": "Data Fabric CCM Performance Monitor Event DF IOMS Request Type B (IO and PIE Requests) Ordered ioanynon-postedwrsized<32b", + "UMask": "0xE7" + }, + { + "EventName": "df_ioms_reqb.Node0.ioanypostedwrsized=64b", + "EventCode": "0x109", + "BriefDescription": "Data Fabric CCM Performance Monitor Event DF IOMS Request Type B (IO and PIE Requests) Ordered ioanypostedwrsized=64b", + "UMask": "0x06" + }, + { + "EventName": "df_ioms_reqb.Node1.ioanypostedwrsized=64b", + "EventCode": "0x109", + "BriefDescription": "Data Fabric CCM Performance Monitor Event DF IOMS Request Type B (IO and PIE Requests) Ordered ioanypostedwrsized=64b", + "UMask": "0x26" + }, + { + "EventName": "df_ioms_reqb.Node2.ioanypostedwrsized=64b", + "EventCode": "0x109", + "BriefDescription": "Data Fabric CCM Performance Monitor Event DF IOMS Request Type B (IO and PIE Requests) Ordered ioanypostedwrsized=64b", + "UMask": "0x46" + }, + { + "EventName": "df_ioms_reqb.Node3.ioanypostedwrsized=64b", + "EventCode": "0x109", + "BriefDescription": "Data Fabric CCM Performance Monitor Event DF IOMS Request Type B (IO and PIE Requests) Ordered ioanypostedwrsized=64b", + "UMask": "0x66" + }, + { + "EventName": "df_ioms_reqb.Node4.ioanypostedwrsized=64b", + "EventCode": "0x109", + "BriefDescription": "Data Fabric CCM Performance Monitor Event DF IOMS Request Type B (IO and PIE Requests) Ordered ioanypostedwrsized=64b", + "UMask": "0x86" + }, + { + "EventName": "df_ioms_reqb.Node5.ioanypostedwrsized=64b", + "EventCode": "0x109", + "BriefDescription": "Data Fabric CCM Performance Monitor Event DF IOMS Request Type B (IO and PIE Requests) Ordered ioanypostedwrsized=64b", + "UMask": "0xA6" + }, + { + "EventName": "df_ioms_reqb.Node6.ioanypostedwrsized=64b", + "EventCode": "0x109", + "BriefDescription": "Data Fabric CCM Performance Monitor Event DF IOMS Request Type B (IO and PIE Requests) Ordered ioanypostedwrsized=64b", + "UMask": "0xC6" + }, + { + "EventName": "df_ioms_reqb.Node7.ioanypostedwrsized=64b", + "EventCode": "0x109", + "BriefDescription": "Data Fabric CCM Performance Monitor Event DF IOMS Request Type B (IO and PIE Requests) Ordered ioanypostedwrsized=64b", + "UMask": "0xE6" + }, + { + "EventName": "df_ioms_reqb.Node0.ioanypostedwrsized>32band<64b", + "EventCode": "0x109", + "BriefDescription": "Data Fabric CCM Performance Monitor Event DF IOMS Request Type B (IO and PIE Requests) Ordered ioanypostedwrsized>32band<64b", + "UMask": "0x05" + }, + { + "EventName": "df_ioms_reqb.Node1.ioanypostedwrsized>32band<64b", + "EventCode": "0x109", + "BriefDescription": "Data Fabric CCM Performance Monitor Event DF IOMS Request Type B (IO and PIE Requests) Ordered ioanypostedwrsized>32band<64b", + "UMask": "0x25" + }, + { + "EventName": "df_ioms_reqb.Node2.ioanypostedwrsized>32band<64b", + "EventCode": "0x109", + "BriefDescription": "Data Fabric CCM Performance Monitor Event DF IOMS Request Type B (IO and PIE Requests) Ordered ioanypostedwrsized>32band<64b", + "UMask": "0x45" + }, + { + "EventName": "df_ioms_reqb.Node3.ioanypostedwrsized>32band<64b", + "EventCode": "0x109", + "BriefDescription": "Data Fabric CCM Performance Monitor Event DF IOMS Request Type B (IO and PIE Requests) Ordered ioanypostedwrsized>32band<64b", + "UMask": "0x65" + }, + { + "EventName": "df_ioms_reqb.Node4.ioanypostedwrsized>32band<64b", + "EventCode": "0x109", + "BriefDescription": "Data Fabric CCM Performance Monitor Event DF IOMS Request Type B (IO and PIE Requests) Ordered ioanypostedwrsized>32band<64b", + "UMask": "0x85" + }, + { + "EventName": "df_ioms_reqb.Node5.ioanypostedwrsized>32band<64b", + "EventCode": "0x109", + "BriefDescription": "Data Fabric CCM Performance Monitor Event DF IOMS Request Type B (IO and PIE Requests) Ordered ioanypostedwrsized>32band<64b", + "UMask": "0xA5" + }, + { + "EventName": "df_ioms_reqb.Node6.ioanypostedwrsized>32band<64b", + "EventCode": "0x109", + "BriefDescription": "Data Fabric CCM Performance Monitor Event DF IOMS Request Type B (IO and PIE Requests) Ordered ioanypostedwrsized>32band<64b", + "UMask": "0xC5" + }, + { + "EventName": "df_ioms_reqb.Node7.ioanypostedwrsized>32band<64b", + "EventCode": "0x109", + "BriefDescription": "Data Fabric CCM Performance Monitor Event DF IOMS Request Type B (IO and PIE Requests) Ordered ioanypostedwrsized>32band<64b", + "UMask": "0xE5" + }, + { + "EventName": "df_ioms_reqb.Node0.ioanypostedwrsized=32", + "EventCode": "0x109", + "BriefDescription": "Data Fabric CCM Performance Monitor Event DF IOMS Request Type B (IO and PIE Requests) Ordered ioanypostedwrsized=32", + "UMask": "0x04" + }, + { + "EventName": "df_ioms_reqb.Node1.ioanypostedwrsized=32", + "EventCode": "0x109", + "BriefDescription": "Data Fabric CCM Performance Monitor Event DF IOMS Request Type B (IO and PIE Requests) Ordered ioanypostedwrsized=32", + "UMask": "0x24" + }, + { + "EventName": "df_ioms_reqb.Node2.ioanypostedwrsized=32", + "EventCode": "0x109", + "BriefDescription": "Data Fabric CCM Performance Monitor Event DF IOMS Request Type B (IO and PIE Requests) Ordered ioanypostedwrsized=32", + "UMask": "0x44" + }, + { + "EventName": "df_ioms_reqb.Node3.ioanypostedwrsized=32", + "EventCode": "0x109", + "BriefDescription": "Data Fabric CCM Performance Monitor Event DF IOMS Request Type B (IO and PIE Requests) Ordered ioanypostedwrsized=32", + "UMask": "0x64" + }, + { + "EventName": "df_ioms_reqb.Node4.ioanypostedwrsized=32", + "EventCode": "0x109", + "BriefDescription": "Data Fabric CCM Performance Monitor Event DF IOMS Request Type B (IO and PIE Requests) Ordered ioanypostedwrsized=32", + "UMask": "0x84" + }, + { + "EventName": "df_ioms_reqb.Node5.ioanypostedwrsized=32", + "EventCode": "0x109", + "BriefDescription": "Data Fabric CCM Performance Monitor Event DF IOMS Request Type B (IO and PIE Requests) Ordered ioanypostedwrsized=32", + "UMask": "0xA4" + }, + { + "EventName": "df_ioms_reqb.Node6.ioanypostedwrsized=32", + "EventCode": "0x109", + "BriefDescription": "Data Fabric CCM Performance Monitor Event DF IOMS Request Type B (IO and PIE Requests) Ordered ioanypostedwrsized=32", + "UMask": "0xC4" + }, + { + "EventName": "df_ioms_reqb.Node7.ioanypostedwrsized=32", + "EventCode": "0x109", + "BriefDescription": "Data Fabric CCM Performance Monitor Event DF IOMS Request Type B (IO and PIE Requests) Ordered ioanypostedwrsized=32", + "UMask": "0xE4" + }, + { + "EventName": "df_ioms_reqb.Node0.ioanypostedwrsized<32", + "EventCode": "0x109", + "BriefDescription": "Data Fabric CCM Performance Monitor Event DF IOMS Request Type B (IO and PIE Requests) Ordered ioanypostedwrsized<32", + "UMask": "0x03" + }, + { + "EventName": "df_ioms_reqb.Node1.ioanypostedwrsized<32", + "EventCode": "0x109", + "BriefDescription": "Data Fabric CCM Performance Monitor Event DF IOMS Request Type B (IO and PIE Requests) Ordered ioanypostedwrsized<32", + "UMask": "0x23" + }, + { + "EventName": "df_ioms_reqb.Node2.ioanypostedwrsized<32", + "EventCode": "0x109", + "BriefDescription": "Data Fabric CCM Performance Monitor Event DF IOMS Request Type B (IO and PIE Requests) Ordered ioanypostedwrsized<32", + "UMask": "0x43" + }, + { + "EventName": "df_ioms_reqb.Node3.ioanypostedwrsized<32", + "EventCode": "0x109", + "BriefDescription": "Data Fabric CCM Performance Monitor Event DF IOMS Request Type B (IO and PIE Requests) Ordered ioanypostedwrsized<32", + "UMask": "0x63" + }, + { + "EventName": "df_ioms_reqb.Node4.ioanypostedwrsized<32", + "EventCode": "0x109", + "BriefDescription": "Data Fabric CCM Performance Monitor Event DF IOMS Request Type B (IO and PIE Requests) Ordered ioanypostedwrsized<32", + "UMask": "0x83" + }, + { + "EventName": "df_ioms_reqb.Node5.ioanypostedwrsized<32", + "EventCode": "0x109", + "BriefDescription": "Data Fabric CCM Performance Monitor Event DF IOMS Request Type B (IO and PIE Requests) Ordered ioanypostedwrsized<32", + "UMask": "0xA3" + }, + { + "EventName": "df_ioms_reqb.Node6.ioanypostedwrsized<32", + "EventCode": "0x109", + "BriefDescription": "Data Fabric CCM Performance Monitor Event DF IOMS Request Type B (IO and PIE Requests) Ordered ioanypostedwrsized<32", + "UMask": "0xC3" + }, + { + "EventName": "df_ioms_reqb.Node7.ioanypostedwrsized<32", + "EventCode": "0x109", + "BriefDescription": "Data Fabric CCM Performance Monitor Event DF IOMS Request Type B (IO and PIE Requests) Ordered ioanypostedwrsized<32", + "UMask": "0xE3" + }, + { + "EventName": "df_ioms_reqb.Node0.ioanyrdsized", + "EventCode": "0x109", + "BriefDescription": "Data Fabric CCM Performance Monitor Event DF IOMS Request Type B (IO and PIE Requests) Ordered ioanyrdsized", + "UMask": "0x02" + }, + { + "EventName": "df_ioms_reqb.Node1.ioanyrdsized", + "EventCode": "0x109", + "BriefDescription": "Data Fabric CCM Performance Monitor Event DF IOMS Request Type B (IO and PIE Requests) Ordered ioanyrdsized", + "UMask": "0x22" + }, + { + "EventName": "df_ioms_reqb.Node2.ioanyrdsized", + "EventCode": "0x109", + "BriefDescription": "Data Fabric CCM Performance Monitor Event DF IOMS Request Type B (IO and PIE Requests) Ordered ioanyrdsized", + "UMask": "0x42" + }, + { + "EventName": "df_ioms_reqb.Node3.ioanyrdsized", + "EventCode": "0x109", + "BriefDescription": "Data Fabric CCM Performance Monitor Event DF IOMS Request Type B (IO and PIE Requests) Ordered ioanyrdsized", + "UMask": "0x62" + }, + { + "EventName": "df_ioms_reqb.Node4.ioanyrdsized", + "EventCode": "0x109", + "BriefDescription": "Data Fabric CCM Performance Monitor Event DF IOMS Request Type B (IO and PIE Requests) Ordered ioanyrdsized", + "UMask": "0x82" + }, + { + "EventName": "df_ioms_reqb.Node5.ioanyrdsized", + "EventCode": "0x109", + "BriefDescription": "Data Fabric CCM Performance Monitor Event DF IOMS Request Type B (IO and PIE Requests) Ordered ioanyrdsized", + "UMask": "0xA2" + }, + { + "EventName": "df_ioms_reqb.Node6.ioanyrdsized", + "EventCode": "0x109", + "BriefDescription": "Data Fabric CCM Performance Monitor Event DF IOMS Request Type B (IO and PIE Requests) Ordered ioanyrdsized", + "UMask": "0xC2" + }, + { + "EventName": "df_ioms_reqb.Node7.ioanyrdsized", + "EventCode": "0x109", + "BriefDescription": "Data Fabric CCM Performance Monitor Event DF IOMS Request Type B (IO and PIE Requests) Ordered ioanyrdsized", + "UMask": "0xE2" + }, + { + "EventName": "df_ioms_reqb.Node0.iolargeread", + "EventCode": "0x109", + "BriefDescription": "Data Fabric CCM Performance Monitor Event DF IOMS Request Type B (IO and PIE Requests) Ordered iolargeread", + "UMask": "0x01" + }, + { + "EventName": "df_ioms_reqb.Node1.iolargeread", + "EventCode": "0x109", + "BriefDescription": "Data Fabric CCM Performance Monitor Event DF IOMS Request Type B (IO and PIE Requests) Ordered iolargeread", + "UMask": "0x21" + }, + { + "EventName": "df_ioms_reqb.Node2.iolargeread", + "EventCode": "0x109", + "BriefDescription": "Data Fabric CCM Performance Monitor Event DF IOMS Request Type B (IO and PIE Requests) Ordered iolargeread", + "UMask": "0x41" + }, + { + "EventName": "df_ioms_reqb.Node3.iolargeread", + "EventCode": "0x109", + "BriefDescription": "Data Fabric CCM Performance Monitor Event DF IOMS Request Type B (IO and PIE Requests) Ordered iolargeread", + "UMask": "0x61" + }, + { + "EventName": "df_ioms_reqb.Node4.iolargeread", + "EventCode": "0x109", + "BriefDescription": "Data Fabric CCM Performance Monitor Event DF IOMS Request Type B (IO and PIE Requests) Ordered iolargeread", + "UMask": "0x81" + }, + { + "EventName": "df_ioms_reqb.Node5.iolargeread", + "EventCode": "0x109", + "BriefDescription": "Data Fabric CCM Performance Monitor Event DF IOMS Request Type B (IO and PIE Requests) Ordered iolargeread", + "UMask": "0xA1" + }, + { + "EventName": "df_ioms_reqb.Node6.iolargeread", + "EventCode": "0x109", + "BriefDescription": "Data Fabric CCM Performance Monitor Event DF IOMS Request Type B (IO and PIE Requests) Ordered iolargeread", + "UMask": "0xC1" + }, + { + "EventName": "df_ioms_reqb.Node7.iolargeread", + "EventCode": "0x109", + "BriefDescription": "Data Fabric CCM Performance Monitor Event DF IOMS Request Type B (IO and PIE Requests) Ordered iolargeread", + "UMask": "0xE1" + } +] + + Property changes on: head/lib/libpmc/pmu-events/arch/x86/amdfam17h/data-fabric.json ___________________________________________________________________ Added: fbsd:nokeywords ## -0,0 +1 ## +yes \ No newline at end of property Index: head/lib/libpmc/pmu-events/arch/x86/amdfam17h/l3cache.json =================================================================== --- head/lib/libpmc/pmu-events/arch/x86/amdfam17h/l3cache.json (nonexistent) +++ head/lib/libpmc/pmu-events/arch/x86/amdfam17h/l3cache.json (revision 340108) @@ -0,0 +1,5411 @@ +[ + { + "EventName": "l3_request_g1.t0.s0.wrsizednc", + "EventCode": "0x01", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 Cache Accesses ", + "L3ThreadMask": "0x01", + "L3SliceMask": "0x01", + "UMask": "0x02" + }, + { + "EventName": "l3_request_g1.t1.s0.wrsizednc", + "EventCode": "0x01", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 Cache Accesses", + "L3ThreadMask": "0x02", + "L3SliceMask": "0x01", + "UMask": "0x02" + }, + { + "EventName": "l3_request_g1.t2.s0.wrsizednc", + "EventCode": "0x01", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 Cache Accesses", + "L3ThreadMask": "0x04", + "L3SliceMask": "0x01", + "UMask": "0x02" + }, + { + "EventName": "l3_request_g1.t3.s0.wrsizednc", + "EventCode": "0x01", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 Cache Accesses", + "L3ThreadMask": "0x08", + "L3SliceMask": "0x01", + "UMask": "0x02" + }, + { + "EventName": "l3_request_g1.t4.s0.wrsizednc", + "EventCode": "0x01", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 Cache Accesses", + "L3ThreadMask": "0x10", + "L3SliceMask": "0x01", + "UMask": "0x02" + }, + { + "EventName": "l3_request_g1.t5.s0.wrsizednc", + "EventCode": "0x01", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 Cache Accesses", + "L3ThreadMask": "0x20", + "L3SliceMask": "0x01", + "UMask": "0x02" + }, + { + "EventName": "l3_request_g1.t6.s0.wrsizednc", + "EventCode": "0x01", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 Cache Accesses", + "L3ThreadMask": "0x40", + "L3SliceMask": "0x01", + "UMask": "0x02" + }, + + { + "EventName": "l3_request_g1.t7.s0.wrsizednc", + "EventCode": "0x01", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 Cache Accesses", + "L3ThreadMask": "0x80", + "L3SliceMask": "0x01", + "UMask": "0x02" + }, + { + "EventName": "l3_request_g1.t0.s1.wrsizednc", + "EventCode": "0x01", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 Cache Accesses", + "L3ThreadMask": "0x01", + "L3SliceMask": "0x02", + "UMask": "0x02" + }, + { + "EventName": "l3_request_g1.t1.s1.wrsizednc", + "EventCode": "0x01", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 Cache Accesses", + "L3ThreadMask": "0x02", + "L3SliceMask": "0x02", + "UMask": "0x02" + }, + { + "EventName": "l3_request_g1.t2.s1.wrsizednc", + "EventCode": "0x01", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 Cache Accesses", + "L3ThreadMask": "0x04", + "L3SliceMask": "0x02", + "UMask": "0x02" + }, + { + "EventName": "l3_request_g1.t3.s1.wrsizednc", + "EventCode": "0x01", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 Cache Accesses", + "L3ThreadMask": "0x08", + "L3SliceMask": "0x02", + "UMask": "0x02" + }, + { + "EventName": "l3_request_g1.t4.s1.wrsizednc", + "EventCode": "0x01", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 Cache Accesses", + "L3ThreadMask": "0x10", + "L3SliceMask": "0x02", + "UMask": "0x02" + }, + { + "EventName": "l3_request_g1.t5.s1.wrsizednc", + "EventCode": "0x01", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 Cache Accesses", + "L3ThreadMask": "0x20", + "L3SliceMask": "0x02", + "UMask": "0x02" + }, + { + "EventName": "l3_request_g1.t6.s1.wrsizednc", + "EventCode": "0x01", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 Cache Accesses", + "L3ThreadMask": "0x40", + "L3SliceMask": "0x02", + "UMask": "0x02" + }, + { + "EventName": "l3_request_g1.t7.s1.wrsizednc", + "EventCode": "0x01", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 Cache Accesses", + "L3ThreadMask": "0x80", + "L3SliceMask": "0x02", + "UMask": "0x02" + }, + { + "EventName": "l3_request_g1.t0.s2.wrsizednc", + "EventCode": "0x01", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 Cache Accesses", + "L3ThreadMask": "0x01", + "L3SliceMask": "0x04", + "UMask": "0x02" + }, + { + "EventName": "l3_request_g1.t1.s2.wrsizednc", + "EventCode": "0x01", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 Cache Accesses", + "L3ThreadMask": "0x02", + "L3SliceMask": "0x04", + "UMask": "0x02" + }, + { + "EventName": "l3_request_g1.t2.s2.wrsizednc", + "EventCode": "0x01", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 Cache Accesses", + "L3ThreadMask": "0x04", + "L3SliceMask": "0x04", + "UMask": "0x02" + }, + { + "EventName": "l3_request_g1.t3.s2.wrsizednc", + "EventCode": "0x01", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 Cache Accesses", + "L3ThreadMask": "0x08", + "L3SliceMask": "0x04", + "UMask": "0x02" + }, + { + "EventName": "l3_request_g1.t4.s2.wrsizednc", + "EventCode": "0x01", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 Cache Accesses", + "L3ThreadMask": "0x10", + "L3SliceMask": "0x04", + "UMask": "0x02" + }, + { + "EventName": "l3_request_g1.t5.s2.wrsizednc", + "EventCode": "0x01", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 Cache Accesses", + "L3ThreadMask": "0x20", + "L3SliceMask": "0x04", + "UMask": "0x02" + }, + { + "EventName": "l3_request_g1.t6.s2.wrsizednc", + "EventCode": "0x01", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 Cache Accesses", + "L3ThreadMask": "0x40", + "L3SliceMask": "0x04", + "UMask": "0x02" + }, + + { + "EventName": "l3_request_g1.t7.s2.wrsizednc", + "EventCode": "0x01", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 Cache Accesses", + "L3ThreadMask": "0x80", + "L3SliceMask": "0x04", + "UMask": "0x02" + }, + { + "EventName": "l3_request_g1.t0.s3.wrsizednc", + "EventCode": "0x01", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 Cache Accesses", + "L3ThreadMask": "0x01", + "L3SliceMask": "0x08", + "UMask": "0x02" + }, + { + "EventName": "l3_request_g1.t1.s3.wrsizednc", + "EventCode": "0x01", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 Cache Accesses", + "L3ThreadMask": "0x02", + "L3SliceMask": "0x08", + "UMask": "0x02" + }, + { + "EventName": "l3_request_g1.t2.s3.wrsizednc", + "EventCode": "0x01", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 Cache Accesses", + "L3ThreadMask": "0x04", + "L3SliceMask": "0x08", + "UMask": "0x02" + }, + { + "EventName": "l3_request_g1.t3.s3.wrsizednc", + "EventCode": "0x01", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 Cache Accesses", + "L3ThreadMask": "0x08", + "L3SliceMask": "0x08", + "UMask": "0x02" + }, + { + "EventName": "l3_request_g1.t4.s3.wrsizednc", + "EventCode": "0x01", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 Cache Accesses", + "L3ThreadMask": "0x10", + "L3SliceMask": "0x08", + "UMask": "0x02" + }, + { + "EventName": "l3_request_g1.t5.s3.wrsizednc", + "EventCode": "0x01", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 Cache Accesses", + "L3ThreadMask": "0x20", + "L3SliceMask": "0x08", + "UMask": "0x02" + }, + { + "EventName": "l3_request_g1.t6.s3.wrsizednc", + "EventCode": "0x01", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 Cache Accesses", + "L3ThreadMask": "0x40", + "L3SliceMask": "0x08", + "UMask": "0x02" + }, + { + "EventName": "l3_request_g1.t7.s3.wrsizednc", + "EventCode": "0x01", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 Cache Accesses", + "L3ThreadMask": "0x80", + "L3SliceMask": "0x08", + "UMask": "0x02" + }, + { + "EventName": "l3_request_g1.t0.s0.wrsized", + "EventCode": "0x01", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 Cache Accesses", + "L3ThreadMask": "0x01", + "L3SliceMask": "0x01", + "UMask": "0x04" + }, + { + "EventName": "l3_request_g1.t1.s0.wrsized", + "EventCode": "0x01", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 Cache Accesses", + "L3ThreadMask": "0x02", + "L3SliceMask": "0x01", + "UMask": "0x04" + }, + { + "EventName": "l3_request_g1.t2.s0.wrsized", + "EventCode": "0x01", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 Cache Accesses", + "L3ThreadMask": "0x04", + "L3SliceMask": "0x01", + "UMask": "0x04" + }, + { + "EventName": "l3_request_g1.t3.s0.wrsized", + "EventCode": "0x01", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 Cache Accesses", + "L3ThreadMask": "0x08", + "L3SliceMask": "0x01", + "UMask": "0x04" + }, + { + "EventName": "l3_request_g1.t4.s0.wrsized", + "EventCode": "0x01", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 Cache Accesses", + "L3ThreadMask": "0x10", + "L3SliceMask": "0x01", + "UMask": "0x04" + }, + { + "EventName": "l3_request_g1.t5.s0.wrsized", + "EventCode": "0x01", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 Cache Accesses", + "L3ThreadMask": "0x20", + "L3SliceMask": "0x01", + "UMask": "0x04" + }, + { + "EventName": "l3_request_g1.t6.s0.wrsized", + "EventCode": "0x01", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 Cache Accesses", + "L3ThreadMask": "0x40", + "L3SliceMask": "0x01", + "UMask": "0x04" + }, + { + "EventName": "l3_request_g1.t7.s0.wrsized", + "EventCode": "0x01", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 Cache Accesses", + "L3ThreadMask": "0x80", + "L3SliceMask": "0x01", + "UMask": "0x04" + }, + { + "EventName": "l3_request_g1.t0.s1.wrsized", + "EventCode": "0x01", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 Cache Accesses", + "L3ThreadMask": "0x01", + "L3SliceMask": "0x02", + "UMask": "0x04" + }, + { + "EventName": "l3_request_g1.t1.s1.wrsized", + "EventCode": "0x01", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 Cache Accesses", + "L3ThreadMask": "0x02", + "L3SliceMask": "0x02", + "UMask": "0x04" + }, + { + "EventName": "l3_request_g1.t2.s1.wrsized", + "EventCode": "0x01", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 Cache Accesses", + "L3ThreadMask": "0x04", + "L3SliceMask": "0x02", + "UMask": "0x04" + }, + { + "EventName": "l3_request_g1.t3.s1.wrsized", + "EventCode": "0x01", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 Cache Accesses", + "L3ThreadMask": "0x08", + "L3SliceMask": "0x02", + "UMask": "0x04" + }, + { + "EventName": "l3_request_g1.t4.s1.wrsized", + "EventCode": "0x01", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 Cache Accesses", + "L3ThreadMask": "0x10", + "L3SliceMask": "0x02", + "UMask": "0x04" + }, + { + "EventName": "l3_request_g1.t5.s1.wrsized", + "EventCode": "0x01", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 Cache Accesses", + "L3ThreadMask": "0x20", + "L3SliceMask": "0x02", + "UMask": "0x04" + }, + { + "EventName": "l3_request_g1.t6.s1.wrsized", + "EventCode": "0x01", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 Cache Accesses", + "L3ThreadMask": "0x40", + "L3SliceMask": "0x02", + "UMask": "0x04" + }, + { + "EventName": "l3_request_g1.t7.s1.wrsized", + "EventCode": "0x01", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 Cache Accesses", + "L3ThreadMask": "0x80", + "L3SliceMask": "0x02", + "UMask": "0x04" + }, + { + "EventName": "l3_request_g1.t0.s2.wrsized", + "EventCode": "0x01", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 Cache Accesses", + "L3ThreadMask": "0x01", + "L3SliceMask": "0x04", + "UMask": "0x04" + }, + { + "EventName": "l3_request_g1.t1.s2.wrsized", + "EventCode": "0x01", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 Cache Accesses", + "L3ThreadMask": "0x02", + "L3SliceMask": "0x04", + "UMask": "0x04" + }, + { + "EventName": "l3_request_g1.t2.s2.wrsized", + "EventCode": "0x01", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 Cache Accesses", + "L3ThreadMask": "0x04", + "L3SliceMask": "0x04", + "UMask": "0x04" + }, + { + "EventName": "l3_request_g1.t3.s2.wrsized", + "EventCode": "0x01", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 Cache Accesses", + "L3ThreadMask": "0x08", + "L3SliceMask": "0x04", + "UMask": "0x04" + }, + { + "EventName": "l3_request_g1.t4.s2.wrsized", + "EventCode": "0x01", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 Cache Accesses", + "L3ThreadMask": "0x10", + "L3SliceMask": "0x04", + "UMask": "0x04" + }, + { + "EventName": "l3_request_g1.t5.s2.wrsized", + "EventCode": "0x01", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 Cache Accesses", + "L3ThreadMask": "0x20", + "L3SliceMask": "0x04", + "UMask": "0x04" + }, + { + "EventName": "l3_request_g1.t6.s2.wrsized", + "EventCode": "0x01", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 Cache Accesses", + "L3ThreadMask": "0x40", + "L3SliceMask": "0x04", + "UMask": "0x04" + }, + { + "EventName": "l3_request_g1.t7.s2.wrsized", + "EventCode": "0x01", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 Cache Accesses", + "L3ThreadMask": "0x80", + "L3SliceMask": "0x04", + "UMask": "0x04" + }, + { + "EventName": "l3_request_g1.t0.s3.wrsized", + "EventCode": "0x01", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 Cache Accesses", + "L3ThreadMask": "0x01", + "L3SliceMask": "0x08", + "UMask": "0x04" + }, + { + "EventName": "l3_request_g1.t1.s3.wrsized", + "EventCode": "0x01", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 Cache Accesses", + "L3ThreadMask": "0x02", + "L3SliceMask": "0x08", + "UMask": "0x04" + }, + { + "EventName": "l3_request_g1.t2.s3.wrsized", + "EventCode": "0x01", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 Cache Accesses", + "L3ThreadMask": "0x04", + "L3SliceMask": "0x08", + "UMask": "0x04" + }, + { + "EventName": "l3_request_g1.t3.s3.wrsized", + "EventCode": "0x01", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 Cache Accesses", + "L3ThreadMask": "0x08", + "L3SliceMask": "0x08", + "UMask": "0x04" + }, + { + "EventName": "l3_request_g1.t4.s3.wrsized", + "EventCode": "0x01", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 Cache Accesses", + "L3ThreadMask": "0x10", + "L3SliceMask": "0x08", + "UMask": "0x04" + }, + { + "EventName": "l3_request_g1.t5.s3.wrsized", + "EventCode": "0x01", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 Cache Accesses", + "L3ThreadMask": "0x20", + "L3SliceMask": "0x08", + "UMask": "0x04" + }, + { + "EventName": "l3_request_g1.t6.s3.wrsized", + "EventCode": "0x01", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 Cache Accesses", + "L3ThreadMask": "0x40", + "L3SliceMask": "0x08", + "UMask": "0x04" + }, + { + "EventName": "l3_request_g1.t7.s3.wrsized", + "EventCode": "0x01", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 Cache Accesses", + "L3ThreadMask": "0x80", + "L3SliceMask": "0x08", + "UMask": "0x04" + }, + { + "EventName": "l3_request_g1.t0.s0.RdSizedNC", + "EventCode": "0x01", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 Cache Accesses", + "L3ThreadMask": "0x01", + "L3SliceMask": "0x01", + "UMask": "0x20" + }, + { + "EventName": "l3_request_g1.t1.s0.RdSizedNC", + "EventCode": "0x01", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 Cache Accesses", + "L3ThreadMask": "0x02", + "L3SliceMask": "0x01", + "UMask": "0x20" + }, + { + "EventName": "l3_request_g1.t2.s0.RdSizedNC", + "EventCode": "0x01", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 Cache Accesses", + "L3ThreadMask": "0x04", + "L3SliceMask": "0x01", + "UMask": "0x20" + }, + { + "EventName": "l3_request_g1.t3.s0.RdSizedNC", + "EventCode": "0x01", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 Cache Accesses", + "L3ThreadMask": "0x08", + "L3SliceMask": "0x01", + "UMask": "0x20" + }, + { + "EventName": "l3_request_g1.t4.s0.RdSizedNC", + "EventCode": "0x01", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 Cache Accesses", + "L3ThreadMask": "0x10", + "L3SliceMask": "0x01", + "UMask": "0x20" + }, + { + "EventName": "l3_request_g1.t5.s0.RdSizedNC", + "EventCode": "0x01", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 Cache Accesses", + "L3ThreadMask": "0x20", + "L3SliceMask": "0x01", + "UMask": "0x20" + }, + { + "EventName": "l3_request_g1.t6.s0.RdSizedNC", + "EventCode": "0x01", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 Cache Accesses", + "L3ThreadMask": "0x40", + "L3SliceMask": "0x01", + "UMask": "0x20" + }, + { + "EventName": "l3_request_g1.t7.s0.RdSizedNC", + "EventCode": "0x01", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 Cache Accesses", + "L3ThreadMask": "0x80", + "L3SliceMask": "0x01", + "UMask": "0x20" + }, + { + "EventName": "l3_request_g1.t0.s1.RdSizedNC", + "EventCode": "0x01", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 Cache Accesses", + "L3ThreadMask": "0x01", + "L3SliceMask": "0x02", + "UMask": "0x20" + }, + { + "EventName": "l3_request_g1.t1.s1.RdSizedNC", + "EventCode": "0x01", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 Cache Accesses", + "L3ThreadMask": "0x02", + "L3SliceMask": "0x02", + "UMask": "0x20" + }, + { + "EventName": "l3_request_g1.t2.s1.RdSizedNC", + "EventCode": "0x01", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 Cache Accesses", + "L3ThreadMask": "0x04", + "L3SliceMask": "0x02", + "UMask": "0x20" + }, + { + "EventName": "l3_request_g1.t3.s1.RdSizedNC", + "EventCode": "0x01", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 Cache Accesses", + "L3ThreadMask": "0x08", + "L3SliceMask": "0x02", + "UMask": "0x20" + }, + { + "EventName": "l3_request_g1.t4.s1.RdSizedNC", + "EventCode": "0x01", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 Cache Accesses", + "L3ThreadMask": "0x10", + "L3SliceMask": "0x02", + "UMask": "0x20" + }, + { + "EventName": "l3_request_g1.t5.s1.RdSizedNC", + "EventCode": "0x01", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 Cache Accesses", + "L3ThreadMask": "0x20", + "L3SliceMask": "0x02", + "UMask": "0x20" + }, + { + "EventName": "l3_request_g1.t6.s1.RdSizedNC", + "EventCode": "0x01", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 Cache Accesses", + "L3ThreadMask": "0x40", + "L3SliceMask": "0x02", + "UMask": "0x20" + }, + { + "EventName": "l3_request_g1.t7.s1.RdSizedNC", + "EventCode": "0x01", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 Cache Accesses", + "L3ThreadMask": "0x80", + "L3SliceMask": "0x02", + "UMask": "0x20" + }, + +{ + "EventName": "l3_request_g1.t0.s2.RdSizedNC", + "EventCode": "0x01", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 Cache Accesses", + "L3ThreadMask": "0x01", + "L3SliceMask": "0x04", + "UMask": "0x20" + }, + { + "EventName": "l3_request_g1.t1.s2.RdSizedNC", + "EventCode": "0x01", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 Cache Accesses", + "L3ThreadMask": "0x02", + "L3SliceMask": "0x04", + "UMask": "0x20" + }, + { + "EventName": "l3_request_g1.t2.s2.RdSizedNC", + "EventCode": "0x01", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 Cache Accesses", + "L3ThreadMask": "0x04", + "L3SliceMask": "0x04", + "UMask": "0x20" + }, + { + "EventName": "l3_request_g1.t3.s2.RdSizedNC", + "EventCode": "0x01", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 Cache Accesses", + "L3ThreadMask": "0x08", + "L3SliceMask": "0x04", + "UMask": "0x20" + }, + { + "EventName": "l3_request_g1.t4.s2.RdSizedNC", + "EventCode": "0x01", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 Cache Accesses", + "L3ThreadMask": "0x10", + "L3SliceMask": "0x04", + "UMask": "0x20" + }, + { + "EventName": "l3_request_g1.t5.s2.RdSizedNC", + "EventCode": "0x01", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 Cache Accesses", + "L3ThreadMask": "0x20", + "L3SliceMask": "0x04", + "UMask": "0x20" + }, + { + "EventName": "l3_request_g1.t6.s2.RdSizedNC", + "EventCode": "0x01", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 Cache Accesses", + "L3ThreadMask": "0x40", + "L3SliceMask": "0x04", + "UMask": "0x20" + }, + { + "EventName": "l3_request_g1.t7.s2.RdSizedNC", + "EventCode": "0x01", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 Cache Accesses", + "L3ThreadMask": "0x80", + "L3SliceMask": "0x04", + "UMask": "0x20" + }, + +{ + "EventName": "l3_request_g1.t0.s3.RdSizedNC", + "EventCode": "0x01", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 Cache Accesses", + "L3ThreadMask": "0x01", + "L3SliceMask": "0x08", + "UMask": "0x20" + }, + { + "EventName": "l3_request_g1.t1.s3.RdSizedNC", + "EventCode": "0x01", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 Cache Accesses", + "L3ThreadMask": "0x02", + "L3SliceMask": "0x08", + "UMask": "0x20" + }, + { + "EventName": "l3_request_g1.t2.s3.RdSizedNC", + "EventCode": "0x01", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 Cache Accesses", + "L3ThreadMask": "0x04", + "L3SliceMask": "0x08", + "UMask": "0x20" + }, + { + "EventName": "l3_request_g1.t3.s3.RdSizedNC", + "EventCode": "0x01", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 Cache Accesses", + "L3ThreadMask": "0x08", + "L3SliceMask": "0x08", + "UMask": "0x20" + }, + { + "EventName": "l3_request_g1.t4.s3.RdSizedNC", + "EventCode": "0x01", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 Cache Accesses", + "L3ThreadMask": "0x10", + "L3SliceMask": "0x08", + "UMask": "0x20" + }, + { + "EventName": "l3_request_g1.t5.s3.RdSizedNC", + "EventCode": "0x01", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 Cache Accesses", + "L3ThreadMask": "0x20", + "L3SliceMask": "0x08", + "UMask": "0x20" + }, + { + "EventName": "l3_request_g1.t6.s3.RdSizedNC", + "EventCode": "0x01", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 Cache Accesses", + "L3ThreadMask": "0x40", + "L3SliceMask": "0x08", + "UMask": "0x20" + }, + { + "EventName": "l3_request_g1.t7.s3.RdSizedNC", + "EventCode": "0x01", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 Cache Accesses", + "L3ThreadMask": "0x80", + "L3SliceMask": "0x08", + "UMask": "0x20" + }, + { + "EventName": "l3_request_g1.t0.s0.RdSized", + "EventCode": "0x01", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 Cache Accesses", + "L3ThreadMask": "0x01", + "L3SliceMask": "0x01", + "UMask": "0x40" + }, + { + "EventName": "l3_request_g1.t1.s0.RdSized", + "EventCode": "0x01", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 Cache Accesses", + "L3ThreadMask": "0x01", + "L3SliceMask": "0x02", + "UMask": "0x40" + }, + { + "EventName": "l3_request_g1.t2.s0.RdSized", + "EventCode": "0x01", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 Cache Accesses", + "L3ThreadMask": "0x04", + "L3SliceMask": "0x01", + "UMask": "0x40" + }, + { + "EventName": "l3_request_g1.t3.s0.RdSized", + "EventCode": "0x01", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 Cache Accesses", + "L3ThreadMask": "0x08", + "L3SliceMask": "0x01", + "UMask": "0x40" + }, + { + "EventName": "l3_request_g1.t4.s0.RdSized", + "EventCode": "0x01", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 Cache Accesses", + "L3ThreadMask": "0x10", + "L3SliceMask": "0x01", + "UMask": "0x40" + }, + { + "EventName": "l3_request_g1.t5.s0.RdSized", + "EventCode": "0x01", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 Cache Accesses", + "L3ThreadMask": "0x20", + "L3SliceMask": "0x01", + "UMask": "0x40" + }, + { + "EventName": "l3_request_g1.t6.s0.RdSized", + "EventCode": "0x01", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 Cache Accesses", + "L3ThreadMask": "0x40", + "L3SliceMask": "0x01", + "UMask": "0x40" + }, + { + "EventName": "l3_request_g1.t7.s0.RdSized", + "EventCode": "0x01", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 Cache Accesses", + "L3ThreadMask": "0x80", + "L3SliceMask": "0x01", + "UMask": "0x40" + }, + { + "EventName": "l3_request_g1.t0.s1.RdSized", + "EventCode": "0x01", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 Cache Accesses", + "L3ThreadMask": "0x01", + "L3SliceMask": "0x02", + "UMask": "0x40" + }, + { + "EventName": "l3_request_g1.t1.s1.RdSized", + "EventCode": "0x01", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 Cache Accesses", + "L3ThreadMask": "0x01", + "L3SliceMask": "0x02", + "UMask": "0x40" + }, + { + "EventName": "l3_request_g1.t2.s1.RdSized", + "EventCode": "0x01", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 Cache Accesses", + "L3ThreadMask": "0x04", + "L3SliceMask": "0x02", + "UMask": "0x40" + }, + { + "EventName": "l3_request_g1.t3.s1.RdSized", + "EventCode": "0x01", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 Cache Accesses", + "L3ThreadMask": "0x08", + "L3SliceMask": "0x02", + "UMask": "0x40" + }, + { + "EventName": "l3_request_g1.t4.s1.RdSized", + "EventCode": "0x01", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 Cache Accesses", + "L3ThreadMask": "0x10", + "L3SliceMask": "0x02", + "UMask": "0x40" + }, + { + "EventName": "l3_request_g1.t5.s1.RdSized", + "EventCode": "0x01", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 Cache Accesses", + "L3ThreadMask": "0x20", + "L3SliceMask": "0x02", + "UMask": "0x40" + }, + { + "EventName": "l3_request_g1.t6.s1.RdSized", + "EventCode": "0x01", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 Cache Accesses", + "L3ThreadMask": "0x40", + "L3SliceMask": "0x02", + "UMask": "0x40" + }, + { + "EventName": "l3_request_g1.t7.s1.RdSized", + "EventCode": "0x01", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 Cache Accesses", + "L3ThreadMask": "0x80", + "L3SliceMask": "0x02", + "UMask": "0x40" + }, + +{ + "EventName": "l3_request_g1.t0.s2.RdSized", + "EventCode": "0x01", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 Cache Accesses", + "L3ThreadMask": "0x01", + "L3SliceMask": "0x04", + "UMask": "0x40" + }, + { + "EventName": "l3_request_g1.t1.s2.RdSized", + "EventCode": "0x01", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 Cache Accesses", + "L3ThreadMask": "0x01", + "L3SliceMask": "0x04", + "UMask": "0x40" + }, + { + "EventName": "l3_request_g1.t2.s2.RdSized", + "EventCode": "0x01", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 Cache Accesses", + "L3ThreadMask": "0x04", + "L3SliceMask": "0x04", + "UMask": "0x40" + }, + { + "EventName": "l3_request_g1.t3.s2.RdSized", + "EventCode": "0x01", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 Cache Accesses", + "L3ThreadMask": "0x08", + "L3SliceMask": "0x04", + "UMask": "0x40" + }, + { + "EventName": "l3_request_g1.t4.s2.RdSized", + "EventCode": "0x01", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 Cache Accesses", + "L3ThreadMask": "0x10", + "L3SliceMask": "0x04", + "UMask": "0x40" + }, + { + "EventName": "l3_request_g1.t5.s2.RdSized", + "EventCode": "0x01", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 Cache Accesses", + "L3ThreadMask": "0x20", + "L3SliceMask": "0x04", + "UMask": "0x40" + }, + { + "EventName": "l3_request_g1.t6.s2.RdSized", + "EventCode": "0x01", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 Cache Accesses", + "L3ThreadMask": "0x40", + "L3SliceMask": "0x04", + "UMask": "0x40" + }, + { + "EventName": "l3_request_g1.t7.s2.RdSized", + "EventCode": "0x01", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 Cache Accesses", + "L3ThreadMask": "0x80", + "L3SliceMask": "0x04", + "UMask": "0x40" + }, + +{ + "EventName": "l3_request_g1.t0.s3.RdSized", + "EventCode": "0x01", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 Cache Accesses", + "L3ThreadMask": "0x01", + "L3SliceMask": "0x08", + "UMask": "0x40" + }, + { + "EventName": "l3_request_g1.t1.s3.RdSized", + "EventCode": "0x01", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 Cache Accesses", + "L3ThreadMask": "0x02", + "L3SliceMask": "0x08", + "UMask": "0x40" + }, + { + "EventName": "l3_request_g1.t2.s3.RdSized", + "EventCode": "0x01", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 Cache Accesses", + "L3ThreadMask": "0x04", + "L3SliceMask": "0x08", + "UMask": "0x40" + }, + { + "EventName": "l3_request_g1.t3.s3.RdSized", + "EventCode": "0x01", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 Cache Accesses", + "L3ThreadMask": "0x08", + "L3SliceMask": "0x08", + "UMask": "0x40" + }, + { + "EventName": "l3_request_g1.t4.s3.RdSized", + "EventCode": "0x01", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 Cache Accesses", + "L3ThreadMask": "0x10", + "L3SliceMask": "0x08", + "UMask": "0x40" + }, + { + "EventName": "l3_request_g1.t5.s3.RdSized", + "EventCode": "0x01", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 Cache Accesses", + "L3ThreadMask": "0x20", + "L3SliceMask": "0x08", + "UMask": "0x40" + }, + { + "EventName": "l3_request_g1.t6.s3.RdSized", + "EventCode": "0x01", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 Cache Accesses", + "L3ThreadMask": "0x40", + "L3SliceMask": "0x08", + "UMask": "0x40" + }, + { + "EventName": "l3_request_g1.t7.s3.RdSized", + "EventCode": "0x01", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 Cache Accesses", + "L3ThreadMask": "0x80", + "L3SliceMask": "0x08", + "UMask": "0x40" + }, + { + "EventName": "l3_request_g1.t0.s0.caching", + "EventCode": "0x01", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 Cache Accesses", + "L3ThreadMask": "0x01", + "L3SliceMask": "0x01", + "UMask": "0x80" + }, + { + "EventName": "l3_request_g1.t1.s0.caching", + "EventCode": "0x01", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 Cache Accesses", + "L3ThreadMask": "0x02", + "L3SliceMask": "0x01", + "UMask": "0x80" + }, +{ + "EventName": "l3_request_g1.t2.s0.caching", + "EventCode": "0x01", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 Cache Accesses", + "L3ThreadMask": "0x04", + "L3SliceMask": "0x01", + "UMask": "0x80" + }, +{ + "EventName": "l3_request_g1.t3.s0.caching", + "EventCode": "0x01", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 Cache Accesses", + "L3ThreadMask": "0x08", + "L3SliceMask": "0x01", + "UMask": "0x80" + }, +{ + "EventName": "l3_request_g1.t4.s0.caching", + "EventCode": "0x01", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 Cache Accesses", + "L3ThreadMask": "0x10", + "L3SliceMask": "0x01", + "UMask": "0x80" + }, +{ + "EventName": "l3_request_g1.t5.s0.caching", + "EventCode": "0x01", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 Cache Accesses", + "L3ThreadMask": "0x20", + "L3SliceMask": "0x01", + "UMask": "0x80" + }, +{ + "EventName": "l3_request_g1.t6.s0.caching", + "EventCode": "0x01", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 Cache Accesses", + "L3ThreadMask": "0x40", + "L3SliceMask": "0x01", + "UMask": "0x80" + }, +{ + "EventName": "l3_request_g1.t7.s0.caching", + "EventCode": "0x01", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 Cache Accesses", + "L3ThreadMask": "0x80", + "L3SliceMask": "0x01", + "UMask": "0x80" + }, + { + "EventName": "l3_request_g1.t0.s1.caching", + "EventCode": "0x01", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 Cache Accesses", + "L3ThreadMask": "0x01", + "L3SliceMask": "0x02", + "UMask": "0x80" + }, + { + "EventName": "l3_request_g1.t1.s1.caching", + "EventCode": "0x01", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 Cache Accesses", + "L3ThreadMask": "0x02", + "L3SliceMask": "0x02", + "UMask": "0x80" + }, +{ + "EventName": "l3_request_g1.t2.s1.caching", + "EventCode": "0x01", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 Cache Accesses", + "L3ThreadMask": "0x04", + "L3SliceMask": "0x02", + "UMask": "0x80" + }, +{ + "EventName": "l3_request_g1.t3.s1.caching", + "EventCode": "0x01", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 Cache Accesses", + "L3ThreadMask": "0x08", + "L3SliceMask": "0x02", + "UMask": "0x80" + }, +{ + "EventName": "l3_request_g1.t4.s1.caching", + "EventCode": "0x01", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 Cache Accesses", + "L3ThreadMask": "0x10", + "L3SliceMask": "0x02", + "UMask": "0x80" + }, +{ + "EventName": "l3_request_g1.t5.s1.caching", + "EventCode": "0x01", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 Cache Accesses", + "L3ThreadMask": "0x20", + "L3SliceMask": "0x02", + "UMask": "0x80" + }, +{ + "EventName": "l3_request_g1.t6.s1.caching", + "EventCode": "0x01", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 Cache Accesses", + "L3ThreadMask": "0x40", + "L3SliceMask": "0x02", + "UMask": "0x80" + }, +{ + "EventName": "l3_request_g1.t7.s1.caching", + "EventCode": "0x01", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 Cache Accesses", + "L3ThreadMask": "0x80", + "L3SliceMask": "0x02", + "UMask": "0x80" + }, + +{ + "EventName": "l3_request_g1.t0.s2.caching", + "EventCode": "0x01", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 Cache Accesses", + "L3ThreadMask": "0x01", + "L3SliceMask": "0x04", + "UMask": "0x80" + }, + { + "EventName": "l3_request_g1.t1.s2.caching", + "EventCode": "0x01", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 Cache Accesses", + "L3ThreadMask": "0x02", + "L3SliceMask": "0x04", + "UMask": "0x80" + }, +{ + "EventName": "l3_request_g1.t2.s2.caching", + "EventCode": "0x01", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 Cache Accesses", + "L3ThreadMask": "0x04", + "L3SliceMask": "0x04", + "UMask": "0x80" + }, +{ + "EventName": "l3_request_g1.t3.s2.caching", + "EventCode": "0x01", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 Cache Accesses", + "L3ThreadMask": "0x08", + "L3SliceMask": "0x04", + "UMask": "0x80" + }, +{ + "EventName": "l3_request_g1.t4.s2.caching", + "EventCode": "0x01", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 Cache Accesses", + "L3ThreadMask": "0x10", + "L3SliceMask": "0x04", + "UMask": "0x80" + }, +{ + "EventName": "l3_request_g1.t5.s2.caching", + "EventCode": "0x01", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 Cache Accesses", + "L3ThreadMask": "0x20", + "L3SliceMask": "0x04", + "UMask": "0x80" + }, +{ + "EventName": "l3_request_g1.t6.s2.caching", + "EventCode": "0x01", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 Cache Accesses", + "L3ThreadMask": "0x40", + "L3SliceMask": "0x04", + "UMask": "0x80" + }, +{ + "EventName": "l3_request_g1.t7.s2.caching", + "EventCode": "0x01", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 Cache Accesses", + "L3ThreadMask": "0x80", + "L3SliceMask": "0x04", + "UMask": "0x80" + }, + +{ + "EventName": "l3_request_g1.t0.s3.caching", + "EventCode": "0x01", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 Cache Accesses", + "L3ThreadMask": "0x01", + "L3SliceMask": "0x08", + "UMask": "0x80" + }, + { + "EventName": "l3_request_g1.t1.s3.caching", + "EventCode": "0x01", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 Cache Accesses", + "L3ThreadMask": "0x02", + "L3SliceMask": "0x08", + "UMask": "0x80" + }, +{ + "EventName": "l3_request_g1.t2.s3.caching", + "EventCode": "0x01", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 Cache Accesses", + "L3ThreadMask": "0x04", + "L3SliceMask": "0x08", + "UMask": "0x80" + }, +{ + "EventName": "l3_request_g1.t3.s3.caching", + "EventCode": "0x01", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 Cache Accesses", + "L3ThreadMask": "0x08", + "L3SliceMask": "0x08", + "UMask": "0x80" + }, +{ + "EventName": "l3_request_g1.t4.s3.caching", + "EventCode": "0x01", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 Cache Accesses", + "L3ThreadMask": "0x10", + "L3SliceMask": "0x08", + "UMask": "0x80" + }, +{ + "EventName": "l3_request_g1.t5.s3.caching", + "EventCode": "0x01", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 Cache Accesses", + "L3ThreadMask": "0x20", + "L3SliceMask": "0x08", + "UMask": "0x80" + }, +{ + "EventName": "l3_request_g1.t6.s3.caching", + "EventCode": "0x01", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 Cache Accesses", + "L3ThreadMask": "0x40", + "L3SliceMask": "0x08", + "UMask": "0x80" + }, +{ + "EventName": "l3_request_g1.t7.s3.caching", + "EventCode": "0x01", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 Cache Accesses", + "L3ThreadMask": "0x80", + "L3SliceMask": "0x08", + "UMask": "0x80" + }, + { + "EventName": "l3fillvicreq.t0.s0.vicblk", + "EventCode": "0x03", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 cache access types", + "L3ThreadMask": "0x01", + "L3SliceMask": "0x01", + "UMask": "0x01" + }, + { + "EventName": "l3fillvicreq.t1.s0.vicblk", + "EventCode": "0x03", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 cache access types", + "L3ThreadMask": "0x02", + "L3SliceMask": "0x01", + "UMask": "0x01" + }, + { + "EventName": "l3fillvicreq.t2.s0.vicblk", + "EventCode": "0x03", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 cache access types", + "L3ThreadMask": "0x04", + "L3SliceMask": "0x01", + "UMask": "0x01" + }, + { + "EventName": "l3fillvicreq.t3.s0.vicblk", + "EventCode": "0x03", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 cache access types", + "L3ThreadMask": "0x08", + "L3SliceMask": "0x01", + "UMask": "0x01" + }, + { + "EventName": "l3fillvicreq.t4.s0.vicblk", + "EventCode": "0x03", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 cache access types", + "L3ThreadMask": "0x10", + "L3SliceMask": "0x01", + "UMask": "0x01" + }, + { + "EventName": "l3fillvicreq.t5.s0.vicblk", + "EventCode": "0x03", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 cache access types", + "L3ThreadMask": "0x20", + "L3SliceMask": "0x01", + "UMask": "0x01" + }, + { + "EventName": "l3fillvicreq.t6.s0.vicblk", + "EventCode": "0x03", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 cache access types", + "L3ThreadMask": "0x40", + "L3SliceMask": "0x01", + "UMask": "0x01" + }, + { + "EventName": "l3fillvicreq.t7.s0.vicblk", + "EventCode": "0x03", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 cache access types", + "L3ThreadMask": "0x80", + "L3SliceMask": "0x01", + "UMask": "0x01" + }, + + { + "EventName": "l3fillvicreq.t0.s1.vicblk", + "EventCode": "0x03", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 cache access types", + "L3ThreadMask": "0x01", + "L3SliceMask": "0x02", + "UMask": "0x01" + }, + { + "EventName": "l3fillvicreq.t1.s1.vicblk", + "EventCode": "0x03", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 cache access types", + "L3ThreadMask": "0x02", + "L3SliceMask": "0x02", + "UMask": "0x01" + }, + { + "EventName": "l3fillvicreq.t2.s1.vicblk", + "EventCode": "0x03", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 cache access types", + "L3ThreadMask": "0x04", + "L3SliceMask": "0x02", + "UMask": "0x01" + }, + { + "EventName": "l3fillvicreq.t3.s1.vicblk", + "EventCode": "0x03", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 cache access types", + "L3ThreadMask": "0x08", + "L3SliceMask": "0x02", + "UMask": "0x01" + }, + { + "EventName": "l3fillvicreq.t4.s1.vicblk", + "EventCode": "0x03", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 cache access types", + "L3ThreadMask": "0x10", + "L3SliceMask": "0x02", + "UMask": "0x01" + }, + { + "EventName": "l3fillvicreq.t5.s1.vicblk", + "EventCode": "0x03", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 cache access types", + "L3ThreadMask": "0x20", + "L3SliceMask": "0x02", + "UMask": "0x01" + }, + { + "EventName": "l3fillvicreq.t6.s1.vicblk", + "EventCode": "0x03", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 cache access types", + "L3ThreadMask": "0x40", + "L3SliceMask": "0x02", + "UMask": "0x01" + }, + { + "EventName": "l3fillvicreq.t7.s1.vicblk", + "EventCode": "0x03", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 cache access types", + "L3ThreadMask": "0x80", + "L3SliceMask": "0x02", + "UMask": "0x01" + }, + + + { + "EventName": "l3fillvicreq.t0.s2.vicblk", + "EventCode": "0x03", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 cache access types", + "L3ThreadMask": "0x01", + "L3SliceMask": "0x04", + "UMask": "0x01" + }, + { + "EventName": "l3fillvicreq.t1.s2.vicblk", + "EventCode": "0x03", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 cache access types", + "L3ThreadMask": "0x04", + "L3SliceMask": "0x01", + "UMask": "0x01" + }, + { + "EventName": "l3fillvicreq.t2.s2.vicblk", + "EventCode": "0x03", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 cache access types", + "L3ThreadMask": "0x04", + "L3SliceMask": "0x04", + "UMask": "0x01" + }, + { + "EventName": "l3fillvicreq.t3.s2.vicblk", + "EventCode": "0x03", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 cache access types", + "L3ThreadMask": "0x08", + "L3SliceMask": "0x04", + "UMask": "0x01" + }, + { + "EventName": "l3fillvicreq.t4.s2.vicblk", + "EventCode": "0x03", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 cache access types", + "L3ThreadMask": "0x10", + "L3SliceMask": "0x04", + "UMask": "0x01" + }, + { + "EventName": "l3fillvicreq.t5.s2.vicblk", + "EventCode": "0x03", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 cache access types", + "L3ThreadMask": "0x20", + "L3SliceMask": "0x04", + "UMask": "0x01" + }, + { + "EventName": "l3fillvicreq.t6.s2.vicblk", + "EventCode": "0x03", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 cache access types", + "L3ThreadMask": "0x40", + "L3SliceMask": "0x04", + "UMask": "0x01" + }, + { + "EventName": "l3fillvicreq.t7.s2.vicblk", + "EventCode": "0x03", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 cache access types", + "L3ThreadMask": "0x80", + "L3SliceMask": "0x04", + "UMask": "0x01" + }, + { + "EventName": "l3fillvicreq.t0.s3.vicblk", + "EventCode": "0x03", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 cache access types", + "L3ThreadMask": "0x01", + "L3SliceMask": "0x08", + "UMask": "0x01" + }, + { + "EventName": "l3fillvicreq.t1.s3.vicblk", + "EventCode": "0x03", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 cache access types", + "L3ThreadMask": "0x02", + "L3SliceMask": "0x08", + "UMask": "0x01" + }, + { + "EventName": "l3fillvicreq.t2.s3.vicblk", + "EventCode": "0x03", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 cache access types", + "L3ThreadMask": "0x04", + "L3SliceMask": "0x08", + "UMask": "0x01" + }, + { + "EventName": "l3fillvicreq.t3.s3.vicblk", + "EventCode": "0x03", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 cache access types", + "L3ThreadMask": "0x08", + "L3SliceMask": "0x08", + "UMask": "0x01" + }, + { + "EventName": "l3fillvicreq.t4.s3.vicblk", + "EventCode": "0x03", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 cache access types", + "L3ThreadMask": "0x10", + "L3SliceMask": "0x08", + "UMask": "0x01" + }, + { + "EventName": "l3fillvicreq.t5.s3.vicblk", + "EventCode": "0x03", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 cache access types", + "L3ThreadMask": "0x20", + "L3SliceMask": "0x08", + "UMask": "0x01" + }, + { + "EventName": "l3fillvicreq.t6.s3.vicblk", + "EventCode": "0x03", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 cache access types", + "L3ThreadMask": "0x40", + "L3SliceMask": "0x08", + "UMask": "0x01" + }, + { + "EventName": "l3fillvicreq.t7.s3.vicblk", + "EventCode": "0x03", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 cache access types", + "L3ThreadMask": "0x80", + "L3SliceMask": "0x08", + "UMask": "0x01" + }, + { + "EventName": "l3fillvicreq.t0.s0.chgtox", + "EventCode": "0x03", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 cache access types", + "L3ThreadMask": "0x01", + "L3SliceMask": "0x01", + "UMask": "0x02" + }, + { + "EventName": "l3fillvicreq.t1.s0.chgtox", + "EventCode": "0x03", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 cache access types", + "L3ThreadMask": "0x02", + "L3SliceMask": "0x01", + "UMask": "0x02" + }, + { + "EventName": "l3fillvicreq.t2.s0.chgtox", + "EventCode": "0x03", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 cache access types", + "L3ThreadMask": "0x04", + "L3SliceMask": "0x01", + "UMask": "0x02" + }, + { + "EventName": "l3fillvicreq.t3.s0.chgtox", + "EventCode": "0x03", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 cache access types", + "L3ThreadMask": "0x08", + "L3SliceMask": "0x01", + "UMask": "0x02" + }, + { + "EventName": "l3fillvicreq.t4.s0.chgtox", + "EventCode": "0x03", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 cache access types", + "L3ThreadMask": "0x10", + "L3SliceMask": "0x01", + "UMask": "0x02" + }, + { + "EventName": "l3fillvicreq.t5.s0.chgtox", + "EventCode": "0x03", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 cache access types", + "L3ThreadMask": "0x20", + "L3SliceMask": "0x01", + "UMask": "0x02" + }, + { + "EventName": "l3fillvicreq.t6.s0.chgtox", + "EventCode": "0x03", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 cache access types", + "L3ThreadMask": "0x40", + "L3SliceMask": "0x01", + "UMask": "0x02" + }, + { + "EventName": "l3fillvicreq.t7.s0.chgtox", + "EventCode": "0x03", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 cache access types", + "L3ThreadMask": "0x80", + "L3SliceMask": "0x01", + "UMask": "0x02" + }, + + { + "EventName": "l3fillvicreq.t0.s1.chgtox", + "EventCode": "0x03", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 cache access types", + "L3ThreadMask": "0x01", + "L3SliceMask": "0x02", + "UMask": "0x02" + }, + { + "EventName": "l3fillvicreq.t1.s1.chgtox", + "EventCode": "0x03", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 cache access types", + "L3ThreadMask": "0x02", + "L3SliceMask": "0x02", + "UMask": "0x02" + }, + { + "EventName": "l3fillvicreq.t2.s1.chgtox", + "EventCode": "0x03", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 cache access types", + "L3ThreadMask": "0x04", + "L3SliceMask": "0x02", + "UMask": "0x02" + }, + { + "EventName": "l3fillvicreq.t3.s1.chgtox", + "EventCode": "0x03", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 cache access types", + "L3ThreadMask": "0x08", + "L3SliceMask": "0x02", + "UMask": "0x02" + }, + { + "EventName": "l3fillvicreq.t4.s1.chgtox", + "EventCode": "0x03", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 cache access types", + "L3ThreadMask": "0x10", + "L3SliceMask": "0x02", + "UMask": "0x02" + }, + { + "EventName": "l3fillvicreq.t5.s1.chgtox", + "EventCode": "0x03", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 cache access types", + "L3ThreadMask": "0x20", + "L3SliceMask": "0x02", + "UMask": "0x02" + }, + { + "EventName": "l3fillvicreq.t6.s1.chgtox", + "EventCode": "0x03", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 cache access types", + "L3ThreadMask": "0x40", + "L3SliceMask": "0x02", + "UMask": "0x02" + }, + { + "EventName": "l3fillvicreq.t7.s1.chgtox", + "EventCode": "0x03", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 cache access types", + "L3ThreadMask": "0x80", + "L3SliceMask": "0x02", + "UMask": "0x02" + }, + { + "EventName": "l3fillvicreq.t0.s2.chgtox", + "EventCode": "0x03", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 cache access types", + "L3ThreadMask": "0x01", + "L3SliceMask": "0x04", + "UMask": "0x02" + }, + { + "EventName": "l3fillvicreq.t1.s2.chgtox", + "EventCode": "0x03", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 cache access types", + "L3ThreadMask": "0x02", + "L3SliceMask": "0x04", + "UMask": "0x02" + }, + { + "EventName": "l3fillvicreq.t2.s2.chgtox", + "EventCode": "0x03", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 cache access types", + "L3ThreadMask": "0x04", + "L3SliceMask": "0x04", + "UMask": "0x02" + }, + { + "EventName": "l3fillvicreq.t3.s2.chgtox", + "EventCode": "0x03", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 cache access types", + "L3ThreadMask": "0x08", + "L3SliceMask": "0x04", + "UMask": "0x02" + }, + { + "EventName": "l3fillvicreq.t4.s2.chgtox", + "EventCode": "0x03", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 cache access types", + "L3ThreadMask": "0x10", + "L3SliceMask": "0x04", + "UMask": "0x02" + }, + { + "EventName": "l3fillvicreq.t5.s2.chgtox", + "EventCode": "0x03", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 cache access types", + "L3ThreadMask": "0x20", + "L3SliceMask": "0x04", + "UMask": "0x02" + }, + { + "EventName": "l3fillvicreq.t6.s2.chgtox", + "EventCode": "0x03", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 cache access types", + "L3ThreadMask": "0x40", + "L3SliceMask": "0x04", + "UMask": "0x02" + }, + { + "EventName": "l3fillvicreq.t7.s2.chgtox", + "EventCode": "0x03", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 cache access types", + "L3ThreadMask": "0x80", + "L3SliceMask": "0x04", + "UMask": "0x02" + }, + { + "EventName": "l3fillvicreq.t0.s3.chgtox", + "EventCode": "0x03", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 cache access types", + "L3ThreadMask": "0x01", + "L3SliceMask": "0x08", + "UMask": "0x02" + }, + { + "EventName": "l3fillvicreq.t1.s3.chgtox", + "EventCode": "0x03", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 cache access types", + "L3ThreadMask": "0x02", + "L3SliceMask": "0x08", + "UMask": "0x02" + }, + { + "EventName": "l3fillvicreq.t2.s3.chgtox", + "EventCode": "0x03", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 cache access types", + "L3ThreadMask": "0x04", + "L3SliceMask": "0x08", + "UMask": "0x02" + }, + { + "EventName": "l3fillvicreq.t3.s3.chgtox", + "EventCode": "0x03", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 cache access types", + "L3ThreadMask": "0x08", + "L3SliceMask": "0x08", + "UMask": "0x02" + }, + { + "EventName": "l3fillvicreq.t4.s3.chgtox", + "EventCode": "0x03", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 cache access types", + "L3ThreadMask": "0x10", + "L3SliceMask": "0x08", + "UMask": "0x02" + }, + { + "EventName": "l3fillvicreq.t5.s3.chgtox", + "EventCode": "0x03", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 cache access types", + "L3ThreadMask": "0x20", + "L3SliceMask": "0x08", + "UMask": "0x02" + }, + { + "EventName": "l3fillvicreq.t6.s3.chgtox", + "EventCode": "0x03", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 cache access types", + "L3ThreadMask": "0x40", + "L3SliceMask": "0x08", + "UMask": "0x02" + }, + { + "EventName": "l3fillvicreq.t7.s3.chgtox", + "EventCode": "0x03", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 cache access types", + "L3ThreadMask": "0x80", + "L3SliceMask": "0x08", + "UMask": "0x02" + }, + { + "EventName": "l3fillvicreq.t0.s0.rdblkc_s_vic", + "EventCode": "0x03", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 cache access types", + "L3ThreadMask": "0x01", + "L3SliceMask": "0x01", + "UMask": "0x04" + }, + { + "EventName": "l3fillvicreq.t1.s0.rdblkc_s_vic", + "EventCode": "0x03", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 cache access types", + "L3ThreadMask": "0x02", + "L3SliceMask": "0x01", + "UMask": "0x04" + }, + { + "EventName": "l3fillvicreq.t2.s0.rdblkc_s_vic", + "EventCode": "0x03", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 cache access types", + "L3ThreadMask": "0x04", + "L3SliceMask": "0x01", + "UMask": "0x04" + }, + { + "EventName": "l3fillvicreq.t3.s0.rdblkc_s_vic", + "EventCode": "0x03", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 cache access types", + "L3ThreadMask": "0x08", + "L3SliceMask": "0x01", + "UMask": "0x04" + }, + { + "EventName": "l3fillvicreq.t4.s0.rdblkc_s_vic", + "EventCode": "0x03", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 cache access types", + "L3ThreadMask": "0x10", + "L3SliceMask": "0x01", + "UMask": "0x04" + }, + { + "EventName": "l3fillvicreq.t5.s0.rdblkc_s_vic", + "EventCode": "0x03", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 cache access types", + "L3ThreadMask": "0x20", + "L3SliceMask": "0x01", + "UMask": "0x04" + }, + { + "EventName": "l3fillvicreq.t6.s0.rdblkc_s_vic", + "EventCode": "0x03", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 cache access types", + "L3ThreadMask": "0x40", + "L3SliceMask": "0x01", + "UMask": "0x04" + }, + { + "EventName": "l3fillvicreq.t7.s0.rdblkc_s_vic", + "EventCode": "0x03", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 cache access types", + "L3ThreadMask": "0x80", + "L3SliceMask": "0x01", + "UMask": "0x04" + }, + + { + "EventName": "l3fillvicreq.t0.s1.rdblkc_s_vic", + "EventCode": "0x03", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 cache access types", + "L3ThreadMask": "0x01", + "L3SliceMask": "0x02", + "UMask": "0x04" + }, + { + "EventName": "l3fillvicreq.t1.s1.rdblkc_s_vic", + "EventCode": "0x03", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 cache access types", + "L3ThreadMask": "0x02", + "L3SliceMask": "0x02", + "UMask": "0x04" + }, + { + "EventName": "l3fillvicreq.t2.s1.rdblkc_s_vic", + "EventCode": "0x03", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 cache access types", + "L3ThreadMask": "0x04", + "L3SliceMask": "0x02", + "UMask": "0x04" + }, + { + "EventName": "l3fillvicreq.t3.s1.rdblkc_s_vic", + "EventCode": "0x03", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 cache access types", + "L3ThreadMask": "0x08", + "L3SliceMask": "0x02", + "UMask": "0x04" + }, + { + "EventName": "l3fillvicreq.t4.s1.rdblkc_s_vic", + "EventCode": "0x03", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 cache access types", + "L3ThreadMask": "0x10", + "L3SliceMask": "0x02", + "UMask": "0x04" + }, + { + "EventName": "l3fillvicreq.t5.s1.rdblkc_s_vic", + "EventCode": "0x03", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 cache access types", + "L3ThreadMask": "0x20", + "L3SliceMask": "0x02", + "UMask": "0x04" + }, + { + "EventName": "l3fillvicreq.t6.s1.rdblkc_s_vic", + "EventCode": "0x03", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 cache access types", + "L3ThreadMask": "0x40", + "L3SliceMask": "0x02", + "UMask": "0x04" + }, + { + "EventName": "l3fillvicreq.t7.s1.rdblkc_s_vic", + "EventCode": "0x03", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 cache access types", + "L3ThreadMask": "0x80", + "L3SliceMask": "0x02", + "UMask": "0x04" + }, + { + "EventName": "l3fillvicreq.t0.s2.rdblkc_s_vic", + "EventCode": "0x03", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 cache access types", + "L3ThreadMask": "0x01", + "L3SliceMask": "0x04", + "UMask": "0x04" + }, + { + "EventName": "l3fillvicreq.t1.s2.rdblkc_s_vic", + "EventCode": "0x03", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 cache access types", + "L3ThreadMask": "0x02", + "L3SliceMask": "0x04", + "UMask": "0x04" + }, + { + "EventName": "l3fillvicreq.t2.s2.rdblkc_s_vic", + "EventCode": "0x03", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 cache access types", + "L3ThreadMask": "0x04", + "L3SliceMask": "0x04", + "UMask": "0x04" + }, + { + "EventName": "l3fillvicreq.t3.s2.rdblkc_s_vic", + "EventCode": "0x03", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 cache access types", + "L3ThreadMask": "0x08", + "L3SliceMask": "0x04", + "UMask": "0x04" + }, + { + "EventName": "l3fillvicreq.t4.s2.rdblkc_s_vic", + "EventCode": "0x03", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 cache access types", + "L3ThreadMask": "0x10", + "L3SliceMask": "0x04", + "UMask": "0x04" + }, + { + "EventName": "l3fillvicreq.t5.s2.rdblkc_s_vic", + "EventCode": "0x03", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 cache access types", + "L3ThreadMask": "0x20", + "L3SliceMask": "0x04", + "UMask": "0x04" + }, + { + "EventName": "l3fillvicreq.t6.s2.rdblkc_s_vic", + "EventCode": "0x03", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 cache access types", + "L3ThreadMask": "0x40", + "L3SliceMask": "0x04", + "UMask": "0x04" + }, + { + "EventName": "l3fillvicreq.t7.s2.rdblkc_s_vic", + "EventCode": "0x03", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 cache access types", + "L3ThreadMask": "0x80", + "L3SliceMask": "0x04", + "UMask": "0x04" + }, + { + "EventName": "l3fillvicreq.t0.s3.rdblkc_s_vic", + "EventCode": "0x03", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 cache access types", + "L3ThreadMask": "0x01", + "L3SliceMask": "0x08", + "UMask": "0x04" + }, + { + "EventName": "l3fillvicreq.t1.s3.rdblkc_s_vic", + "EventCode": "0x03", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 cache access types", + "L3ThreadMask": "0x02", + "L3SliceMask": "0x08", + "UMask": "0x04" + }, + { + "EventName": "l3fillvicreq.t2.s3.rdblkc_s_vic", + "EventCode": "0x03", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 cache access types", + "L3ThreadMask": "0x04", + "L3SliceMask": "0x08", + "UMask": "0x04" + }, + { + "EventName": "l3fillvicreq.t3.s3.rdblkc_s_vic", + "EventCode": "0x03", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 cache access types", + "L3ThreadMask": "0x08", + "L3SliceMask": "0x08", + "UMask": "0x04" + }, + { + "EventName": "l3fillvicreq.t4.s3.rdblkc_s_vic", + "EventCode": "0x03", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 cache access types", + "L3ThreadMask": "0x10", + "L3SliceMask": "0x08", + "UMask": "0x04" + }, + { + "EventName": "l3fillvicreq.t5.s3.rdblkc_s_vic", + "EventCode": "0x03", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 cache access types", + "L3ThreadMask": "0x20", + "L3SliceMask": "0x08", + "UMask": "0x04" + }, + { + "EventName": "l3fillvicreq.t6.s3.rdblkc_s_vic", + "EventCode": "0x03", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 cache access types", + "L3ThreadMask": "0x40", + "L3SliceMask": "0x08", + "UMask": "0x04" + }, + { + "EventName": "l3fillvicreq.t7.s3.rdblkc_s_vic", + "EventCode": "0x03", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 cache access types", + "L3ThreadMask": "0x80", + "L3SliceMask": "0x08", + "UMask": "0x04" + }, + { + "EventName": "l3fillvicreq.t0.s0.rdblkc_s", + "EventCode": "0x03", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 cache access types", + "L3ThreadMask": "0x01", + "L3SliceMask": "0x01", + "UMask": "0x08" + }, + { + "EventName": "l3fillvicreq.t1.s0.rdblkc_s", + "EventCode": "0x03", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 cache access types", + "L3ThreadMask": "0x02", + "L3SliceMask": "0x01", + "UMask": "0x08" + }, + { + "EventName": "l3fillvicreq.t2.s0.rdblkc_s", + "EventCode": "0x03", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 cache access types", + "L3ThreadMask": "0x04", + "L3SliceMask": "0x01", + "UMask": "0x08" + }, + { + "EventName": "l3fillvicreq.t3.s0.rdblkc_s", + "EventCode": "0x03", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 cache access types", + "L3ThreadMask": "0x08", + "L3SliceMask": "0x01", + "UMask": "0x08" + }, + { + "EventName": "l3fillvicreq.t4.s0.rdblkc_s", + "EventCode": "0x03", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 cache access types", + "L3ThreadMask": "0x10", + "L3SliceMask": "0x01", + "UMask": "0x08" + }, + { + "EventName": "l3fillvicreq.t5.s0.rdblkc_s", + "EventCode": "0x03", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 cache access types", + "L3ThreadMask": "0x20", + "L3SliceMask": "0x01", + "UMask": "0x08" + }, + { + "EventName": "l3fillvicreq.t6.s0.rdblkc_s", + "EventCode": "0x03", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 cache access types", + "L3ThreadMask": "0x40", + "L3SliceMask": "0x01", + "UMask": "0x08" + }, + { + "EventName": "l3fillvicreq.t7.s0.rdblkc_s", + "EventCode": "0x03", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 cache access types", + "L3ThreadMask": "0x80", + "L3SliceMask": "0x01", + "UMask": "0x08" + }, + + { + "EventName": "l3fillvicreq.t0.s1.rdblkc_s", + "EventCode": "0x03", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 cache access types", + "L3ThreadMask": "0x01", + "L3SliceMask": "0x02", + "UMask": "0x08" + }, + { + "EventName": "l3fillvicreq.t1.s1.rdblkc_s", + "EventCode": "0x03", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 cache access types", + "L3ThreadMask": "0x02", + "L3SliceMask": "0x02", + "UMask": "0x08" + }, + { + "EventName": "l3fillvicreq.t2.s1.rdblkc_s", + "EventCode": "0x03", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 cache access types", + "L3ThreadMask": "0x04", + "L3SliceMask": "0x02", + "UMask": "0x08" + }, + { + "EventName": "l3fillvicreq.t3.s1.rdblkc_s", + "EventCode": "0x03", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 cache access types", + "L3ThreadMask": "0x08", + "L3SliceMask": "0x02", + "UMask": "0x08" + }, + { + "EventName": "l3fillvicreq.t4.s1.rdblkc_s", + "EventCode": "0x03", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 cache access types", + "L3ThreadMask": "0x10", + "L3SliceMask": "0x02", + "UMask": "0x08" + }, + { + "EventName": "l3fillvicreq.t5.s1.rdblkc_s", + "EventCode": "0x03", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 cache access types", + "L3ThreadMask": "0x20", + "L3SliceMask": "0x02", + "UMask": "0x08" + }, + { + "EventName": "l3fillvicreq.t6.s1.rdblkc_s", + "EventCode": "0x03", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 cache access types", + "L3ThreadMask": "0x40", + "L3SliceMask": "0x02", + "UMask": "0x08" + }, + { + "EventName": "l3fillvicreq.t7.s1.rdblkc_s", + "EventCode": "0x03", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 cache access types", + "L3ThreadMask": "0x80", + "L3SliceMask": "0x02", + "UMask": "0x08" + }, + { + "EventName": "l3fillvicreq.t0.s2.rdblkc_s", + "EventCode": "0x03", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 cache access types", + "L3ThreadMask": "0x01", + "L3SliceMask": "0x04", + "UMask": "0x08" + }, + { + "EventName": "l3fillvicreq.t1.s2.rdblkc_s", + "EventCode": "0x03", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 cache access types", + "L3ThreadMask": "0x02", + "L3SliceMask": "0x04", + "UMask": "0x08" + }, + { + "EventName": "l3fillvicreq.t2.s2.rdblkc_s", + "EventCode": "0x03", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 cache access types", + "L3ThreadMask": "0x04", + "L3SliceMask": "0x04", + "UMask": "0x08" + }, + { + "EventName": "l3fillvicreq.t3.s2.rdblkc_s", + "EventCode": "0x03", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 cache access types", + "L3ThreadMask": "0x08", + "L3SliceMask": "0x04", + "UMask": "0x08" + }, + { + "EventName": "l3fillvicreq.t4.s2.rdblkc_s", + "EventCode": "0x03", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 cache access types", + "L3ThreadMask": "0x10", + "L3SliceMask": "0x04", + "UMask": "0x08" + }, + { + "EventName": "l3fillvicreq.t5.s2.rdblkc_s", + "EventCode": "0x03", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 cache access types", + "L3ThreadMask": "0x20", + "L3SliceMask": "0x04", + "UMask": "0x08" + }, + { + "EventName": "l3fillvicreq.t6.s2.rdblkc_s", + "EventCode": "0x03", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 cache access types", + "L3ThreadMask": "0x40", + "L3SliceMask": "0x04", + "UMask": "0x08" + }, + { + "EventName": "l3fillvicreq.t7.s2.rdblkc_s", + "EventCode": "0x03", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 cache access types", + "L3ThreadMask": "0x80", + "L3SliceMask": "0x04", + "UMask": "0x08" + }, + { + "EventName": "l3fillvicreq.t0.s3.rdblkc_s", + "EventCode": "0x03", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 cache access types", + "L3ThreadMask": "0x01", + "L3SliceMask": "0x08", + "UMask": "0x08" + }, + { + "EventName": "l3fillvicreq.t1.s3.rdblkc_s", + "EventCode": "0x03", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 cache access types", + "L3ThreadMask": "0x02", + "L3SliceMask": "0x08", + "UMask": "0x08" + }, + { + "EventName": "l3fillvicreq.t2.s3.rdblkc_s", + "EventCode": "0x03", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 cache access types", + "L3ThreadMask": "0x04", + "L3SliceMask": "0x08", + "UMask": "0x08" + }, + { + "EventName": "l3fillvicreq.t3.s3.rdblkc_s", + "EventCode": "0x03", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 cache access types", + "L3ThreadMask": "0x08", + "L3SliceMask": "0x08", + "UMask": "0x08" + }, + { + "EventName": "l3fillvicreq.t4.s3.rdblkc_s", + "EventCode": "0x03", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 cache access types", + "L3ThreadMask": "0x10", + "L3SliceMask": "0x08", + "UMask": "0x08" + }, + { + "EventName": "l3fillvicreq.t5.s3.rdblkc_s", + "EventCode": "0x03", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 cache access types", + "L3ThreadMask": "0x20", + "L3SliceMask": "0x08", + "UMask": "0x08" + }, + { + "EventName": "l3fillvicreq.t6.s3.rdblkc_s", + "EventCode": "0x03", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 cache access types", + "L3ThreadMask": "0x40", + "L3SliceMask": "0x08", + "UMask": "0x08" + }, + { + "EventName": "l3fillvicreq.t7.s3.rdblkc_s", + "EventCode": "0x03", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 cache access types", + "L3ThreadMask": "0x80", + "L3SliceMask": "0x08", + "UMask": "0x08" + }, + { + "EventName": "l3fillvicreq.t0.s0.rdblkx_vic", + "EventCode": "0x03", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 cache access types", + "L3ThreadMask": "0x01", + "L3SliceMask": "0x01", + "UMask": "0x10" + }, + { + "EventName": "l3fillvicreq.t1.s0.rdblkx_vic", + "EventCode": "0x03", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 cache access types", + "L3ThreadMask": "0x02", + "L3SliceMask": "0x01", + "UMask": "0x10" + }, + { + "EventName": "l3fillvicreq.t2.s0.rdblkx_vic", + "EventCode": "0x03", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 cache access types", + "L3ThreadMask": "0x04", + "L3SliceMask": "0x01", + "UMask": "0x10" + }, + { + "EventName": "l3fillvicreq.t3.s0.rdblkx_vic", + "EventCode": "0x03", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 cache access types", + "L3ThreadMask": "0x08", + "L3SliceMask": "0x01", + "UMask": "0x10" + }, + { + "EventName": "l3fillvicreq.t4.s0.rdblkx_vic", + "EventCode": "0x03", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 cache access types", + "L3ThreadMask": "0x10", + "L3SliceMask": "0x01", + "UMask": "0x10" + }, + { + "EventName": "l3fillvicreq.t5.s0.rdblkx_vic", + "EventCode": "0x03", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 cache access types", + "L3ThreadMask": "0x20", + "L3SliceMask": "0x01", + "UMask": "0x10" + }, + { + "EventName": "l3fillvicreq.t6.s0.rdblkx_vic", + "EventCode": "0x03", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 cache access types", + "L3ThreadMask": "0x40", + "L3SliceMask": "0x01", + "UMask": "0x10" + }, + { + "EventName": "l3fillvicreq.t7.s0.rdblkx_vic", + "EventCode": "0x03", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 cache access types", + "L3ThreadMask": "0x80", + "L3SliceMask": "0x01", + "UMask": "0x10" + }, + + { + "EventName": "l3fillvicreq.t0.s1.rdblkx_vic", + "EventCode": "0x03", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 cache access types", + "L3ThreadMask": "0x01", + "L3SliceMask": "0x02", + "UMask": "0x10" + }, + { + "EventName": "l3fillvicreq.t1.s1.rdblkx_vic", + "EventCode": "0x03", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 cache access types", + "L3ThreadMask": "0x02", + "L3SliceMask": "0x02", + "UMask": "0x10" + }, + { + "EventName": "l3fillvicreq.t2.s1.rdblkx_vic", + "EventCode": "0x03", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 cache access types", + "L3ThreadMask": "0x04", + "L3SliceMask": "0x02", + "UMask": "0x10" + }, + { + "EventName": "l3fillvicreq.t3.s1.rdblkx_vic", + "EventCode": "0x03", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 cache access types", + "L3ThreadMask": "0x08", + "L3SliceMask": "0x02", + "UMask": "0x10" + }, + { + "EventName": "l3fillvicreq.t4.s1.rdblkx_vic", + "EventCode": "0x03", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 cache access types", + "L3ThreadMask": "0x10", + "L3SliceMask": "0x02", + "UMask": "0x10" + }, + { + "EventName": "l3fillvicreq.t5.s1.rdblkx_vic", + "EventCode": "0x03", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 cache access types", + "L3ThreadMask": "0x20", + "L3SliceMask": "0x02", + "UMask": "0x10" + }, + { + "EventName": "l3fillvicreq.t6.s1.rdblkx_vic", + "EventCode": "0x03", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 cache access types", + "L3ThreadMask": "0x40", + "L3SliceMask": "0x02", + "UMask": "0x10" + }, + { + "EventName": "l3fillvicreq.t7.s1.rdblkx_vic", + "EventCode": "0x03", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 cache access types", + "L3ThreadMask": "0x80", + "L3SliceMask": "0x02", + "UMask": "0x10" + }, + { + "EventName": "l3fillvicreq.t0.s2.rdblkx_vic", + "EventCode": "0x03", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 cache access types", + "L3ThreadMask": "0x01", + "L3SliceMask": "0x04", + "UMask": "0x10" + }, + { + "EventName": "l3fillvicreq.t1.s2.rdblkx_vic", + "EventCode": "0x03", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 cache access types", + "L3ThreadMask": "0x02", + "L3SliceMask": "0x04", + "UMask": "0x10" + }, + { + "EventName": "l3fillvicreq.t2.s2.rdblkx_vic", + "EventCode": "0x03", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 cache access types", + "L3ThreadMask": "0x04", + "L3SliceMask": "0x04", + "UMask": "0x10" + }, + { + "EventName": "l3fillvicreq.t3.s2.rdblkx_vic", + "EventCode": "0x03", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 cache access types", + "L3ThreadMask": "0x08", + "L3SliceMask": "0x04", + "UMask": "0x10" + }, + { + "EventName": "l3fillvicreq.t4.s2.rdblkx_vic", + "EventCode": "0x03", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 cache access types", + "L3ThreadMask": "0x10", + "L3SliceMask": "0x04", + "UMask": "0x10" + }, + { + "EventName": "l3fillvicreq.t5.s2.rdblkx_vic", + "EventCode": "0x03", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 cache access types", + "L3ThreadMask": "0x20", + "L3SliceMask": "0x04", + "UMask": "0x10" + }, + { + "EventName": "l3fillvicreq.t6.s2.rdblkx_vic", + "EventCode": "0x03", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 cache access types", + "L3ThreadMask": "0x40", + "L3SliceMask": "0x04", + "UMask": "0x10" + }, + { + "EventName": "l3fillvicreq.t7.s2.rdblkx_vic", + "EventCode": "0x03", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 cache access types", + "L3ThreadMask": "0x80", + "L3SliceMask": "0x04", + "UMask": "0x10" + }, + { + "EventName": "l3fillvicreq.t0.s3.rdblkx_vic", + "EventCode": "0x03", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 cache access types", + "L3ThreadMask": "0x01", + "L3SliceMask": "0x08", + "UMask": "0x10" + }, + { + "EventName": "l3fillvicreq.t1.s3.rdblkx_vic", + "EventCode": "0x03", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 cache access types", + "L3ThreadMask": "0x02", + "L3SliceMask": "0x08", + "UMask": "0x10" + }, + { + "EventName": "l3fillvicreq.t2.s3.rdblkx_vic", + "EventCode": "0x03", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 cache access types", + "L3ThreadMask": "0x04", + "L3SliceMask": "0x08", + "UMask": "0x10" + }, + { + "EventName": "l3fillvicreq.t3.s3.rdblkx_vic", + "EventCode": "0x03", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 cache access types", + "L3ThreadMask": "0x08", + "L3SliceMask": "0x08", + "UMask": "0x10" + }, + { + "EventName": "l3fillvicreq.t4.s3.rdblkx_vic", + "EventCode": "0x03", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 cache access types", + "L3ThreadMask": "0x10", + "L3SliceMask": "0x08", + "UMask": "0x10" + }, + { + "EventName": "l3fillvicreq.t5.s3.rdblkx_vic", + "EventCode": "0x03", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 cache access types", + "L3ThreadMask": "0x20", + "L3SliceMask": "0x08", + "UMask": "0x10" + }, + { + "EventName": "l3fillvicreq.t6.s3.rdblkx_vic", + "EventCode": "0x03", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 cache access types", + "L3ThreadMask": "0x40", + "L3SliceMask": "0x08", + "UMask": "0x10" + }, + { + "EventName": "l3fillvicreq.t7.s3.rdblkx_vic", + "EventCode": "0x03", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 cache access types", + "L3ThreadMask": "0x80", + "L3SliceMask": "0x08", + "UMask": "0x10" + }, + { + "EventName": "l3fillvicreq.t0.s0.rdblkx", + "EventCode": "0x03", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 cache access types", + "L3ThreadMask": "0x01", + "L3SliceMask": "0x01", + "UMask": "0x20" + }, + { + "EventName": "l3fillvicreq.t1.s0.rdblkx", + "EventCode": "0x03", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 cache access types", + "L3ThreadMask": "0x02", + "L3SliceMask": "0x01", + "UMask": "0x20" + }, + { + "EventName": "l3fillvicreq.t2.s0.rdblkx", + "EventCode": "0x03", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 cache access types", + "L3ThreadMask": "0x04", + "L3SliceMask": "0x01", + "UMask": "0x20" + }, + { + "EventName": "l3fillvicreq.t3.s0.rdblkx", + "EventCode": "0x03", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 cache access types", + "L3ThreadMask": "0x08", + "L3SliceMask": "0x01", + "UMask": "0x20" + }, + { + "EventName": "l3fillvicreq.t4.s0.rdblkx", + "EventCode": "0x03", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 cache access types", + "L3ThreadMask": "0x10", + "L3SliceMask": "0x01", + "UMask": "0x20" + }, + { + "EventName": "l3fillvicreq.t5.s0.rdblkx", + "EventCode": "0x03", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 cache access types", + "L3ThreadMask": "0x20", + "L3SliceMask": "0x01", + "UMask": "0x20" + }, + { + "EventName": "l3fillvicreq.t6.s0.rdblkx", + "EventCode": "0x03", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 cache access types", + "L3ThreadMask": "0x40", + "L3SliceMask": "0x01", + "UMask": "0x20" + }, + { + "EventName": "l3fillvicreq.t7.s0.rdblkx", + "EventCode": "0x03", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 cache access types", + "L3ThreadMask": "0x80", + "L3SliceMask": "0x01", + "UMask": "0x20" + }, + + { + "EventName": "l3fillvicreq.t0.s1.rdblkx", + "EventCode": "0x03", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 cache access types", + "L3ThreadMask": "0x01", + "L3SliceMask": "0x02", + "UMask": "0x20" + }, + { + "EventName": "l3fillvicreq.t1.s1.rdblkx", + "EventCode": "0x03", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 cache access types", + "L3ThreadMask": "0x02", + "L3SliceMask": "0x02", + "UMask": "0x20" + }, + { + "EventName": "l3fillvicreq.t2.s1.rdblkx", + "EventCode": "0x03", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 cache access types", + "L3ThreadMask": "0x04", + "L3SliceMask": "0x02", + "UMask": "0x20" + }, + { + "EventName": "l3fillvicreq.t3.s1.rdblkx", + "EventCode": "0x03", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 cache access types", + "L3ThreadMask": "0x08", + "L3SliceMask": "0x02", + "UMask": "0x20" + }, + { + "EventName": "l3fillvicreq.t4.s1.rdblkx", + "EventCode": "0x03", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 cache access types", + "L3ThreadMask": "0x10", + "L3SliceMask": "0x02", + "UMask": "0x20" + }, + { + "EventName": "l3fillvicreq.t5.s1.rdblkx", + "EventCode": "0x03", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 cache access types", + "L3ThreadMask": "0x20", + "L3SliceMask": "0x02", + "UMask": "0x20" + }, + { + "EventName": "l3fillvicreq.t6.s1.rdblkx", + "EventCode": "0x03", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 cache access types", + "L3ThreadMask": "0x40", + "L3SliceMask": "0x02", + "UMask": "0x20" + }, + { + "EventName": "l3fillvicreq.t7.s1.rdblkx", + "EventCode": "0x03", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 cache access types", + "L3ThreadMask": "0x80", + "L3SliceMask": "0x02", + "UMask": "0x20" + }, + { + "EventName": "l3fillvicreq.t0.s2.rdblkx", + "EventCode": "0x03", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 cache access types", + "L3ThreadMask": "0x01", + "L3SliceMask": "0x04", + "UMask": "0x20" + }, + { + "EventName": "l3fillvicreq.t1.s2.rdblkx", + "EventCode": "0x03", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 cache access types", + "L3ThreadMask": "0x02", + "L3SliceMask": "0x04", + "UMask": "0x20" + }, + { + "EventName": "l3fillvicreq.t2.s2.rdblkx", + "EventCode": "0x03", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 cache access types", + "L3ThreadMask": "0x04", + "L3SliceMask": "0x04", + "UMask": "0x20" + }, + { + "EventName": "l3fillvicreq.t3.s2.rdblkx", + "EventCode": "0x03", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 cache access types", + "L3ThreadMask": "0x08", + "L3SliceMask": "0x04", + "UMask": "0x20" + }, + { + "EventName": "l3fillvicreq.t4.s2.rdblkx", + "EventCode": "0x03", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 cache access types", + "L3ThreadMask": "0x10", + "L3SliceMask": "0x04", + "UMask": "0x20" + }, + { + "EventName": "l3fillvicreq.t5.s2.rdblkx", + "EventCode": "0x03", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 cache access types", + "L3ThreadMask": "0x20", + "L3SliceMask": "0x04", + "UMask": "0x20" + }, + { + "EventName": "l3fillvicreq.t6.s2.rdblkx", + "EventCode": "0x03", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 cache access types", + "L3ThreadMask": "0x40", + "L3SliceMask": "0x04", + "UMask": "0x20" + }, + { + "EventName": "l3fillvicreq.t7.s2.rdblkx", + "EventCode": "0x03", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 cache access types", + "L3ThreadMask": "0x80", + "L3SliceMask": "0x04", + "UMask": "0x20" + }, + { + "EventName": "l3fillvicreq.t0.s3.rdblkx", + "EventCode": "0x03", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 cache access types", + "L3ThreadMask": "0x01", + "L3SliceMask": "0x08", + "UMask": "0x20" + }, + { + "EventName": "l3fillvicreq.t1.s3.rdblkx", + "EventCode": "0x03", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 cache access types", + "L3ThreadMask": "0x02", + "L3SliceMask": "0x08", + "UMask": "0x20" + }, + { + "EventName": "l3fillvicreq.t2.s3.rdblkx", + "EventCode": "0x03", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 cache access types", + "L3ThreadMask": "0x04", + "L3SliceMask": "0x08", + "UMask": "0x20" + }, + { + "EventName": "l3fillvicreq.t3.s3.rdblkx", + "EventCode": "0x03", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 cache access types", + "L3ThreadMask": "0x08", + "L3SliceMask": "0x08", + "UMask": "0x20" + }, + { + "EventName": "l3fillvicreq.t4.s3.rdblkx", + "EventCode": "0x03", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 cache access types", + "L3ThreadMask": "0x10", + "L3SliceMask": "0x08", + "UMask": "0x20" + }, + { + "EventName": "l3fillvicreq.t5.s3.rdblkx", + "EventCode": "0x03", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 cache access types", + "L3ThreadMask": "0x20", + "L3SliceMask": "0x08", + "UMask": "0x20" + }, + { + "EventName": "l3fillvicreq.t6.s3.rdblkx", + "EventCode": "0x03", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 cache access types", + "L3ThreadMask": "0x40", + "L3SliceMask": "0x08", + "UMask": "0x20" + }, + { + "EventName": "l3fillvicreq.t7.s3.rdblkx", + "EventCode": "0x03", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 cache access types", + "L3ThreadMask": "0x80", + "L3SliceMask": "0x08", + "UMask": "0x20" + }, + { + "EventName": "l3fillvicreq.t0.s0.rdblkl_vic", + "EventCode": "0x03", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 cache access types", + "L3ThreadMask": "0x01", + "L3SliceMask": "0x01", + "UMask": "0x40" + }, + { + "EventName": "l3fillvicreq.t1.s0.rdblkl_vic", + "EventCode": "0x03", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 cache access types", + "L3ThreadMask": "0x02", + "L3SliceMask": "0x01", + "UMask": "0x40" + }, + { + "EventName": "l3fillvicreq.t2.s0.rdblkl_vic", + "EventCode": "0x03", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 cache access types", + "L3ThreadMask": "0x04", + "L3SliceMask": "0x01", + "UMask": "0x40" + }, + { + "EventName": "l3fillvicreq.t3.s0.rdblkl_vic", + "EventCode": "0x03", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 cache access types", + "L3ThreadMask": "0x08", + "L3SliceMask": "0x01", + "UMask": "0x40" + }, + { + "EventName": "l3fillvicreq.t4.s0.rdblkl_vic", + "EventCode": "0x03", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 cache access types", + "L3ThreadMask": "0x10", + "L3SliceMask": "0x01", + "UMask": "0x40" + }, + { + "EventName": "l3fillvicreq.t5.s0.rdblkl_vic", + "EventCode": "0x03", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 cache access types", + "L3ThreadMask": "0x20", + "L3SliceMask": "0x01", + "UMask": "0x40" + }, + { + "EventName": "l3fillvicreq.t6.s0.rdblkl_vic", + "EventCode": "0x03", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 cache access types", + "L3ThreadMask": "0x40", + "L3SliceMask": "0x01", + "UMask": "0x40" + }, + { + "EventName": "l3fillvicreq.t7.s0.rdblkl_vic", + "EventCode": "0x03", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 cache access types", + "L3ThreadMask": "0x80", + "L3SliceMask": "0x01", + "UMask": "0x40" + }, + + { + "EventName": "l3fillvicreq.t0.s1.rdblkl_vic", + "EventCode": "0x03", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 cache access types", + "L3ThreadMask": "0x01", + "L3SliceMask": "0x02", + "UMask": "0x40" + }, + { + "EventName": "l3fillvicreq.t1.s1.rdblkl_vic", + "EventCode": "0x03", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 cache access types", + "L3ThreadMask": "0x02", + "L3SliceMask": "0x02", + "UMask": "0x40" + }, + { + "EventName": "l3fillvicreq.t2.s1.rdblkl_vic", + "EventCode": "0x03", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 cache access types", + "L3ThreadMask": "0x04", + "L3SliceMask": "0x02", + "UMask": "0x40" + }, + { + "EventName": "l3fillvicreq.t3.s1.rdblkl_vic", + "EventCode": "0x03", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 cache access types", + "L3ThreadMask": "0x08", + "L3SliceMask": "0x02", + "UMask": "0x40" + }, + { + "EventName": "l3fillvicreq.t4.s1.rdblkl_vic", + "EventCode": "0x03", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 cache access types", + "L3ThreadMask": "0x10", + "L3SliceMask": "0x02", + "UMask": "0x40" + }, + { + "EventName": "l3fillvicreq.t5.s1.rdblkl_vic", + "EventCode": "0x03", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 cache access types", + "L3ThreadMask": "0x20", + "L3SliceMask": "0x02", + "UMask": "0x40" + }, + { + "EventName": "l3fillvicreq.t6.s1.rdblkl_vic", + "EventCode": "0x03", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 cache access types", + "L3ThreadMask": "0x40", + "L3SliceMask": "0x02", + "UMask": "0x40" + }, + { + "EventName": "l3fillvicreq.t7.s1.rdblkl_vic", + "EventCode": "0x03", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 cache access types", + "L3ThreadMask": "0x80", + "L3SliceMask": "0x02", + "UMask": "0x40" + }, + { + "EventName": "l3fillvicreq.t0.s2.rdblkl_vic", + "EventCode": "0x03", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 cache access types", + "L3ThreadMask": "0x01", + "L3SliceMask": "0x04", + "UMask": "0x40" + }, + { + "EventName": "l3fillvicreq.t1.s2.rdblkl_vic", + "EventCode": "0x03", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 cache access types", + "L3ThreadMask": "0x02", + "L3SliceMask": "0x04", + "UMask": "0x40" + }, + { + "EventName": "l3fillvicreq.t2.s2.rdblkl_vic", + "EventCode": "0x03", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 cache access types", + "L3ThreadMask": "0x04", + "L3SliceMask": "0x04", + "UMask": "0x40" + }, + { + "EventName": "l3fillvicreq.t3.s2.rdblkl_vic", + "EventCode": "0x03", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 cache access types", + "L3ThreadMask": "0x08", + "L3SliceMask": "0x04", + "UMask": "0x40" + }, + { + "EventName": "l3fillvicreq.t4.s2.rdblkl_vic", + "EventCode": "0x03", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 cache access types", + "L3ThreadMask": "0x10", + "L3SliceMask": "0x04", + "UMask": "0x40" + }, + { + "EventName": "l3fillvicreq.t5.s2.rdblkl_vic", + "EventCode": "0x03", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 cache access types", + "L3ThreadMask": "0x20", + "L3SliceMask": "0x04", + "UMask": "0x40" + }, + { + "EventName": "l3fillvicreq.t6.s2.rdblkl_vic", + "EventCode": "0x03", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 cache access types", + "L3ThreadMask": "0x40", + "L3SliceMask": "0x04", + "UMask": "0x40" + }, + { + "EventName": "l3fillvicreq.t7.s2.rdblkl_vic", + "EventCode": "0x03", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 cache access types", + "L3ThreadMask": "0x80", + "L3SliceMask": "0x04", + "UMask": "0x40" + }, + { + "EventName": "l3fillvicreq.t0.s3.rdblkl_vic", + "EventCode": "0x03", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 cache access types", + "L3ThreadMask": "0x01", + "L3SliceMask": "0x08", + "UMask": "0x40" + }, + { + "EventName": "l3fillvicreq.t1.s3.rdblkl_vic", + "EventCode": "0x03", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 cache access types", + "L3ThreadMask": "0x02", + "L3SliceMask": "0x08", + "UMask": "0x40" + }, + { + "EventName": "l3fillvicreq.t2.s3.rdblkl_vic", + "EventCode": "0x03", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 cache access types", + "L3ThreadMask": "0x04", + "L3SliceMask": "0x08", + "UMask": "0x40" + }, + { + "EventName": "l3fillvicreq.t3.s3.rdblkl_vic", + "EventCode": "0x03", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 cache access types", + "L3ThreadMask": "0x08", + "L3SliceMask": "0x08", + "UMask": "0x40" + }, + { + "EventName": "l3fillvicreq.t4.s3.rdblkl_vic", + "EventCode": "0x03", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 cache access types", + "L3ThreadMask": "0x10", + "L3SliceMask": "0x08", + "UMask": "0x40" + }, + { + "EventName": "l3fillvicreq.t5.s3.rdblkl_vic", + "EventCode": "0x03", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 cache access types", + "L3ThreadMask": "0x20", + "L3SliceMask": "0x08", + "UMask": "0x40" + }, + { + "EventName": "l3fillvicreq.t6.s3.rdblkl_vic", + "EventCode": "0x03", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 cache access types", + "L3ThreadMask": "0x40", + "L3SliceMask": "0x08", + "UMask": "0x40" + }, + { + "EventName": "l3fillvicreq.t7.s3.rdblkl_vic", + "EventCode": "0x03", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 cache access types", + "L3ThreadMask": "0x80", + "L3SliceMask": "0x08", + "UMask": "0x40" + }, + { + "EventName": "l3fillvicreq.t0.s0.rdblkl", + "EventCode": "0x03", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 cache access types", + "L3ThreadMask": "0x01", + "L3SliceMask": "0x01", + "UMask": "0x80" + }, + { + "EventName": "l3fillvicreq.t1.s0.rdblkl", + "EventCode": "0x03", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 cache access types", + "L3ThreadMask": "0x02", + "L3SliceMask": "0x01", + "UMask": "0x80" + }, + { + "EventName": "l3fillvicreq.t2.s0.rdblkl", + "EventCode": "0x03", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 cache access types", + "L3ThreadMask": "0x04", + "L3SliceMask": "0x01", + "UMask": "0x80" + }, + { + "EventName": "l3fillvicreq.t3.s0.rdblkl", + "EventCode": "0x03", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 cache access types", + "L3ThreadMask": "0x08", + "L3SliceMask": "0x01", + "UMask": "0x80" + }, + { + "EventName": "l3fillvicreq.t4.s0.rdblkl", + "EventCode": "0x03", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 cache access types", + "L3ThreadMask": "0x10", + "L3SliceMask": "0x01", + "UMask": "0x80" + }, + { + "EventName": "l3fillvicreq.t5.s0.rdblkl", + "EventCode": "0x03", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 cache access types", + "L3ThreadMask": "0x20", + "L3SliceMask": "0x01", + "UMask": "0x80" + }, + { + "EventName": "l3fillvicreq.t6.s0.rdblkl", + "EventCode": "0x03", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 cache access types", + "L3ThreadMask": "0x40", + "L3SliceMask": "0x01", + "UMask": "0x80" + }, + { + "EventName": "l3fillvicreq.t7.s0.rdblkl", + "EventCode": "0x03", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 cache access types", + "L3ThreadMask": "0x80", + "L3SliceMask": "0x01", + "UMask": "0x80" + }, + + { + "EventName": "l3fillvicreq.t0.s1.rdblkl", + "EventCode": "0x03", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 cache access types", + "L3ThreadMask": "0x01", + "L3SliceMask": "0x02", + "UMask": "0x80" + }, + { + "EventName": "l3fillvicreq.t1.s1.rdblkl", + "EventCode": "0x03", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 cache access types", + "L3ThreadMask": "0x02", + "L3SliceMask": "0x02", + "UMask": "0x80" + }, + { + "EventName": "l3fillvicreq.t2.s1.rdblkl", + "EventCode": "0x03", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 cache access types", + "L3ThreadMask": "0x04", + "L3SliceMask": "0x02", + "UMask": "0x80" + }, + { + "EventName": "l3fillvicreq.t3.s1.rdblkl", + "EventCode": "0x03", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 cache access types", + "L3ThreadMask": "0x08", + "L3SliceMask": "0x02", + "UMask": "0x80" + }, + { + "EventName": "l3fillvicreq.t4.s1.rdblkl", + "EventCode": "0x03", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 cache access types", + "L3ThreadMask": "0x10", + "L3SliceMask": "0x02", + "UMask": "0x80" + }, + { + "EventName": "l3fillvicreq.t5.s1.rdblkl", + "EventCode": "0x03", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 cache access types", + "L3ThreadMask": "0x20", + "L3SliceMask": "0x02", + "UMask": "0x80" + }, + { + "EventName": "l3fillvicreq.t6.s1.rdblkl", + "EventCode": "0x03", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 cache access types", + "L3ThreadMask": "0x40", + "L3SliceMask": "0x02", + "UMask": "0x80" + }, + { + "EventName": "l3fillvicreq.t7.s1.rdblkl", + "EventCode": "0x03", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 cache access types", + "L3ThreadMask": "0x80", + "L3SliceMask": "0x02", + "UMask": "0x80" + }, + { + "EventName": "l3fillvicreq.t0.s2.rdblkl", + "EventCode": "0x03", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 cache access types", + "L3ThreadMask": "0x01", + "L3SliceMask": "0x04", + "UMask": "0x80" + }, + { + "EventName": "l3fillvicreq.t1.s2.rdblkl", + "EventCode": "0x03", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 cache access types", + "L3ThreadMask": "0x02", + "L3SliceMask": "0x04", + "UMask": "0x80" + }, + { + "EventName": "l3fillvicreq.t2.s2.rdblkl", + "EventCode": "0x03", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 cache access types", + "L3ThreadMask": "0x04", + "L3SliceMask": "0x04", + "UMask": "0x80" + }, + { + "EventName": "l3fillvicreq.t3.s2.rdblkl", + "EventCode": "0x03", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 cache access types", + "L3ThreadMask": "0x08", + "L3SliceMask": "0x04", + "UMask": "0x80" + }, + { + "EventName": "l3fillvicreq.t4.s2.rdblkl", + "EventCode": "0x03", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 cache access types", + "L3ThreadMask": "0x10", + "L3SliceMask": "0x04", + "UMask": "0x80" + }, + { + "EventName": "l3fillvicreq.t5.s2.rdblkl", + "EventCode": "0x03", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 cache access types", + "L3ThreadMask": "0x20", + "L3SliceMask": "0x04", + "UMask": "0x80" + }, + { + "EventName": "l3fillvicreq.t6.s2.rdblkl", + "EventCode": "0x03", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 cache access types", + "L3ThreadMask": "0x40", + "L3SliceMask": "0x04", + "UMask": "0x80" + }, + { + "EventName": "l3fillvicreq.t7.s2.rdblkl", + "EventCode": "0x03", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 cache access types", + "L3ThreadMask": "0x80", + "L3SliceMask": "0x04", + "UMask": "0x80" + }, + { + "EventName": "l3fillvicreq.t0.s3.rdblkl", + "EventCode": "0x03", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 cache access types", + "L3ThreadMask": "0x01", + "L3SliceMask": "0x08", + "UMask": "0x80" + }, + { + "EventName": "l3fillvicreq.t1.s3.rdblkl", + "EventCode": "0x03", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 cache access types", + "L3ThreadMask": "0x02", + "L3SliceMask": "0x08", + "UMask": "0x80" + }, + { + "EventName": "l3fillvicreq.t2.s3.rdblkl", + "EventCode": "0x03", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 cache access types", + "L3ThreadMask": "0x04", + "L3SliceMask": "0x08", + "UMask": "0x80" + }, + { + "EventName": "l3fillvicreq.t3.s3.rdblkl", + "EventCode": "0x03", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 cache access types", + "L3ThreadMask": "0x08", + "L3SliceMask": "0x08", + "UMask": "0x80" + }, + { + "EventName": "l3fillvicreq.t4.s3.rdblkl", + "EventCode": "0x03", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 cache access types", + "L3ThreadMask": "0x10", + "L3SliceMask": "0x08", + "UMask": "0x80" + }, + { + "EventName": "l3fillvicreq.t5.s3.rdblkl", + "EventCode": "0x03", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 cache access types", + "L3ThreadMask": "0x20", + "L3SliceMask": "0x08", + "UMask": "0x80" + }, + { + "EventName": "l3fillvicreq.t6.s3.rdblkl", + "EventCode": "0x03", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 cache access types", + "L3ThreadMask": "0x40", + "L3SliceMask": "0x08", + "UMask": "0x80" + }, + { + "EventName": "l3fillvicreq.t7.s3.rdblkl", + "EventCode": "0x03", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 cache access types", + "L3ThreadMask": "0x80", + "L3SliceMask": "0x08", + "UMask": "0x80" + }, + { + "EventName": "l3combclstrstate", + "EventCode": "0x06", + "BriefDescription": "L3 Cache Performance Monitor Counters RequestMiss: L3 miss", + "UMask": "0x01" + }, + { + "EventName": "l3victimstate.t0.s0.nol3victimline", + "EventCode": "0x09", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 Victim State", + "L3ThreadMask": "0x01", + "L3SliceMask": "0x01", + "UMask": "0x01" + }, + { + "EventName": "l3victimstate.t1.s0.nol3victimline", + "EventCode": "0x09", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 Victim State", + "L3ThreadMask": "0x02", + "L3SliceMask": "0x01", + "UMask": "0x01" + }, + { + "EventName": "l3victimstate.t2.s0.nol3victimline", + "EventCode": "0x09", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 Victim State", + "L3ThreadMask": "0x04", + "L3SliceMask": "0x01", + "UMask": "0x01" + }, + { + "EventName": "l3victimstate.t3.s0.nol3victimline", + "EventCode": "0x09", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 Victim State", + "L3ThreadMask": "0x08", + "L3SliceMask": "0x01", + "UMask": "0x01" + }, + { + "EventName": "l3victimstate.t4.s0.nol3victimline", + "EventCode": "0x09", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 Victim State", + "L3ThreadMask": "0x10", + "L3SliceMask": "0x01", + "UMask": "0x01" + }, + { + "EventName": "l3victimstate.t5.s0.nol3victimline", + "EventCode": "0x09", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 Victim State", + "L3ThreadMask": "0x20", + "L3SliceMask": "0x01", + "UMask": "0x01" + }, + { + "EventName": "l3victimstate.t6.s0.nol3victimline", + "EventCode": "0x09", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 Victim State", + "L3ThreadMask": "0x40", + "L3SliceMask": "0x01", + "UMask": "0x01" + }, + { + "EventName": "l3victimstate.t7.s0.nol3victimline", + "EventCode": "0x09", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 Victim State", + "L3ThreadMask": "0x80", + "L3SliceMask": "0x01", + "UMask": "0x01" + }, + + { + "EventName": "l3victimstate.t0.s1.nol3victimline", + "EventCode": "0x09", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 Victim State", + "L3ThreadMask": "0x01", + "L3SliceMask": "0x02", + "UMask": "0x01" + }, + { + "EventName": "l3victimstate.t1.s1.nol3victimline", + "EventCode": "0x09", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 Victim State", + "L3ThreadMask": "0x02", + "L3SliceMask": "0x02", + "UMask": "0x01" + }, + { + "EventName": "l3victimstate.t2.s1.nol3victimline", + "EventCode": "0x09", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 Victim State", + "L3ThreadMask": "0x04", + "L3SliceMask": "0x02", + "UMask": "0x01" + }, + { + "EventName": "l3victimstate.t3.s1.nol3victimline", + "EventCode": "0x09", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 Victim State", + "L3ThreadMask": "0x08", + "L3SliceMask": "0x02", + "UMask": "0x01" + }, + { + "EventName": "l3victimstate.t4.s1.nol3victimline", + "EventCode": "0x09", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 Victim State", + "L3ThreadMask": "0x10", + "L3SliceMask": "0x02", + "UMask": "0x01" + }, + { + "EventName": "l3victimstate.t5.s1.nol3victimline", + "EventCode": "0x09", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 Victim State", + "L3ThreadMask": "0x20", + "L3SliceMask": "0x02", + "UMask": "0x01" + }, + { + "EventName": "l3victimstate.t6.s1.nol3victimline", + "EventCode": "0x09", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 Victim State", + "L3ThreadMask": "0x40", + "L3SliceMask": "0x02", + "UMask": "0x01" + }, + { + "EventName": "l3victimstate.t7.s1.nol3victimline", + "EventCode": "0x09", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 Victim State", + "L3ThreadMask": "0x80", + "L3SliceMask": "0x02", + "UMask": "0x01" + }, + { + "EventName": "l3victimstate.t0.s2.nol3victimline", + "EventCode": "0x09", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 Victim State", + "L3ThreadMask": "0x01", + "L3SliceMask": "0x04", + "UMask": "0x01" + }, + { + "EventName": "l3victimstate.t1.s2.nol3victimline", + "EventCode": "0x09", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 Victim State", + "L3ThreadMask": "0x02", + "L3SliceMask": "0x04", + "UMask": "0x01" + }, + { + "EventName": "l3victimstate.t2.s2.nol3victimline", + "EventCode": "0x09", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 Victim State", + "L3ThreadMask": "0x04", + "L3SliceMask": "0x04", + "UMask": "0x01" + }, + { + "EventName": "l3victimstate.t3.s2.nol3victimline", + "EventCode": "0x09", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 Victim State", + "L3ThreadMask": "0x08", + "L3SliceMask": "0x04", + "UMask": "0x01" + }, + { + "EventName": "l3victimstate.t4.s2.nol3victimline", + "EventCode": "0x09", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 Victim State", + "L3ThreadMask": "0x10", + "L3SliceMask": "0x04", + "UMask": "0x01" + }, + { + "EventName": "l3victimstate.t5.s2.nol3victimline", + "EventCode": "0x09", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 Victim State", + "L3ThreadMask": "0x20", + "L3SliceMask": "0x04", + "UMask": "0x01" + }, + { + "EventName": "l3victimstate.t6.s2.nol3victimline", + "EventCode": "0x09", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 Victim State", + "L3ThreadMask": "0x40", + "L3SliceMask": "0x04", + "UMask": "0x01" + }, + { + "EventName": "l3victimstate.t7.s2.nol3victimline", + "EventCode": "0x09", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 Victim State", + "L3ThreadMask": "0x80", + "L3SliceMask": "0x04", + "UMask": "0x01" + }, + { + "EventName": "l3victimstate.t0.s3.nol3victimline", + "EventCode": "0x09", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 Victim State", + "L3ThreadMask": "0x01", + "L3SliceMask": "0x08", + "UMask": "0x01" + }, + { + "EventName": "l3victimstate.t1.s3.nol3victimline", + "EventCode": "0x09", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 Victim State", + "L3ThreadMask": "0x02", + "L3SliceMask": "0x08", + "UMask": "0x01" + }, + { + "EventName": "l3victimstate.t2.s3.nol3victimline", + "EventCode": "0x09", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 Victim State", + "L3ThreadMask": "0x04", + "L3SliceMask": "0x08", + "UMask": "0x01" + }, + { + "EventName": "l3victimstate.t3.s3.nol3victimline", + "EventCode": "0x09", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 Victim State", + "L3ThreadMask": "0x08", + "L3SliceMask": "0x08", + "UMask": "0x01" + }, + { + "EventName": "l3victimstate.t4.s3.nol3victimline", + "EventCode": "0x09", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 Victim State", + "L3ThreadMask": "0x10", + "L3SliceMask": "0x08", + "UMask": "0x01" + }, + { + "EventName": "l3victimstate.t5.s3.nol3victimline", + "EventCode": "0x09", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 Victim State", + "L3ThreadMask": "0x20", + "L3SliceMask": "0x08", + "UMask": "0x01" + }, + { + "EventName": "l3victimstate.t6.s3.nol3victimline", + "EventCode": "0x09", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 Victim State", + "L3ThreadMask": "0x40", + "L3SliceMask": "0x08", + "UMask": "0x01" + }, + { + "EventName": "l3victimstate.t7.s3.nol3victimline", + "EventCode": "0x09", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 Victim State", + "L3ThreadMask": "0x80", + "L3SliceMask": "0x08", + "UMask": "0x01" + }, + { + "EventName": "l3victimstate.t0.s0.none_nol3victimline", + "EventCode": "0x09", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 Victim State", + "L3ThreadMask": "0x01", + "L3SliceMask": "0x01", + "UMask": "0x02" + }, + { + "EventName": "l3victimstate.t1.s0.none_nol3victimline", + "EventCode": "0x09", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 Victim State", + "L3ThreadMask": "0x02", + "L3SliceMask": "0x01", + "UMask": "0x02" + }, + { + "EventName": "l3victimstate.t2.s0.none_nol3victimline", + "EventCode": "0x09", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 Victim State", + "L3ThreadMask": "0x04", + "L3SliceMask": "0x01", + "UMask": "0x02" + }, + { + "EventName": "l3victimstate.t3.s0.none_nol3victimline", + "EventCode": "0x09", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 Victim State", + "L3ThreadMask": "0x08", + "L3SliceMask": "0x01", + "UMask": "0x02" + }, + { + "EventName": "l3victimstate.t4.s0.none_nol3victimline", + "EventCode": "0x09", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 Victim State", + "L3ThreadMask": "0x10", + "L3SliceMask": "0x01", + "UMask": "0x02" + }, + { + "EventName": "l3victimstate.t5.s0.none_nol3victimline", + "EventCode": "0x09", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 Victim State", + "L3ThreadMask": "0x20", + "L3SliceMask": "0x01", + "UMask": "0x02" + }, + { + "EventName": "l3victimstate.t6.s0.none_nol3victimline", + "EventCode": "0x09", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 Victim State", + "L3ThreadMask": "0x40", + "L3SliceMask": "0x01", + "UMask": "0x02" + }, + { + "EventName": "l3victimstate.t7.s0.none_nol3victimline", + "EventCode": "0x09", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 Victim State", + "L3ThreadMask": "0x80", + "L3SliceMask": "0x01", + "UMask": "0x02" + }, + + { + "EventName": "l3victimstate.t0.s1.none_nol3victimline", + "EventCode": "0x09", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 Victim State", + "L3ThreadMask": "0x01", + "L3SliceMask": "0x02", + "UMask": "0x02" + }, + { + "EventName": "l3victimstate.t1.s1.none_nol3victimline", + "EventCode": "0x09", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 Victim State", + "L3ThreadMask": "0x02", + "L3SliceMask": "0x02", + "UMask": "0x02" + }, + { + "EventName": "l3victimstate.t2.s1.none_nol3victimline", + "EventCode": "0x09", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 Victim State", + "L3ThreadMask": "0x04", + "L3SliceMask": "0x02", + "UMask": "0x02" + }, + { + "EventName": "l3victimstate.t3.s1.none_nol3victimline", + "EventCode": "0x09", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 Victim State", + "L3ThreadMask": "0x08", + "L3SliceMask": "0x02", + "UMask": "0x02" + }, + { + "EventName": "l3victimstate.t4.s1.none_nol3victimline", + "EventCode": "0x09", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 Victim State", + "L3ThreadMask": "0x10", + "L3SliceMask": "0x02", + "UMask": "0x02" + }, + { + "EventName": "l3victimstate.t5.s1.none_nol3victimline", + "EventCode": "0x09", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 Victim State", + "L3ThreadMask": "0x20", + "L3SliceMask": "0x02", + "UMask": "0x02" + }, + { + "EventName": "l3victimstate.t6.s1.none_nol3victimline", + "EventCode": "0x09", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 Victim State", + "L3ThreadMask": "0x40", + "L3SliceMask": "0x02", + "UMask": "0x02" + }, + { + "EventName": "l3victimstate.t7.s1.none_nol3victimline", + "EventCode": "0x09", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 Victim State", + "L3ThreadMask": "0x80", + "L3SliceMask": "0x02", + "UMask": "0x02" + }, + { + "EventName": "l3victimstate.t0.s2.none_nol3victimline", + "EventCode": "0x09", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 Victim State", + "L3ThreadMask": "0x01", + "L3SliceMask": "0x04", + "UMask": "0x02" + }, + { + "EventName": "l3victimstate.t1.s2.none_nol3victimline", + "EventCode": "0x09", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 Victim State", + "L3ThreadMask": "0x02", + "L3SliceMask": "0x04", + "UMask": "0x02" + }, + { + "EventName": "l3victimstate.t2.s2.none_nol3victimline", + "EventCode": "0x09", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 Victim State", + "L3ThreadMask": "0x04", + "L3SliceMask": "0x04", + "UMask": "0x02" + }, + { + "EventName": "l3victimstate.t3.s2.none_nol3victimline", + "EventCode": "0x09", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 Victim State", + "L3ThreadMask": "0x08", + "L3SliceMask": "0x04", + "UMask": "0x02" + }, + { + "EventName": "l3victimstate.t4.s2.none_nol3victimline", + "EventCode": "0x09", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 Victim State", + "L3ThreadMask": "0x10", + "L3SliceMask": "0x04", + "UMask": "0x02" + }, + { + "EventName": "l3victimstate.t5.s2.none_nol3victimline", + "EventCode": "0x09", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 Victim State", + "L3ThreadMask": "0x20", + "L3SliceMask": "0x04", + "UMask": "0x02" + }, + { + "EventName": "l3victimstate.t6.s2.none_nol3victimline", + "EventCode": "0x09", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 Victim State", + "L3ThreadMask": "0x40", + "L3SliceMask": "0x04", + "UMask": "0x02" + }, + { + "EventName": "l3victimstate.t7.s2.none_nol3victimline", + "EventCode": "0x09", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 Victim State", + "L3ThreadMask": "0x80", + "L3SliceMask": "0x04", + "UMask": "0x02" + }, + { + "EventName": "l3victimstate.t0.s3.none_nol3victimline", + "EventCode": "0x09", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 Victim State", + "L3ThreadMask": "0x01", + "L3SliceMask": "0x08", + "UMask": "0x02" + }, + { + "EventName": "l3victimstate.t1.s3.none_nol3victimline", + "EventCode": "0x09", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 Victim State", + "L3ThreadMask": "0x02", + "L3SliceMask": "0x08", + "UMask": "0x02" + }, + { + "EventName": "l3victimstate.t2.s3.none_nol3victimline", + "EventCode": "0x09", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 Victim State", + "L3ThreadMask": "0x04", + "L3SliceMask": "0x08", + "UMask": "0x02" + }, + { + "EventName": "l3victimstate.t3.s3.none_nol3victimline", + "EventCode": "0x09", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 Victim State", + "L3ThreadMask": "0x08", + "L3SliceMask": "0x08", + "UMask": "0x02" + }, + { + "EventName": "l3victimstate.t4.s3.none_nol3victimline", + "EventCode": "0x09", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 Victim State", + "L3ThreadMask": "0x10", + "L3SliceMask": "0x08", + "UMask": "0x02" + }, + { + "EventName": "l3victimstate.t5.s3.none_nol3victimline", + "EventCode": "0x09", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 Victim State", + "L3ThreadMask": "0x20", + "L3SliceMask": "0x08", + "UMask": "0x02" + }, + { + "EventName": "l3victimstate.t6.s3.none_nol3victimline", + "EventCode": "0x09", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 Victim State", + "L3ThreadMask": "0x40", + "L3SliceMask": "0x08", + "UMask": "0x02" + }, + { + "EventName": "l3victimstate.t7.s3.none_nol3victimline", + "EventCode": "0x09", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 Victim State", + "L3ThreadMask": "0x80", + "L3SliceMask": "0x08", + "UMask": "0x02" + }, + { + "EventName": "l3victimstate.t0.s0.F_S", + "EventCode": "0x09", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 Victim State", + "L3ThreadMask": "0x01", + "L3SliceMask": "0x01", + "UMask": "0x04" + }, + { + "EventName": "l3victimstate.t1.s0.F_S", + "EventCode": "0x09", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 Victim State", + "L3ThreadMask": "0x02", + "L3SliceMask": "0x01", + "UMask": "0x04" + }, + { + "EventName": "l3victimstate.t2.s0.F_S", + "EventCode": "0x09", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 Victim State", + "L3ThreadMask": "0x04", + "L3SliceMask": "0x01", + "UMask": "0x04" + }, + { + "EventName": "l3victimstate.t3.s0.F_S", + "EventCode": "0x09", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 Victim State", + "L3ThreadMask": "0x08", + "L3SliceMask": "0x01", + "UMask": "0x04" + }, + { + "EventName": "l3victimstate.t4.s0.F_S", + "EventCode": "0x09", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 Victim State", + "L3ThreadMask": "0x10", + "L3SliceMask": "0x01", + "UMask": "0x04" + }, + { + "EventName": "l3victimstate.t5.s0.F_S", + "EventCode": "0x09", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 Victim State", + "L3ThreadMask": "0x20", + "L3SliceMask": "0x01", + "UMask": "0x04" + }, + { + "EventName": "l3victimstate.t6.s0.F_S", + "EventCode": "0x09", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 Victim State", + "L3ThreadMask": "0x40", + "L3SliceMask": "0x01", + "UMask": "0x04" + }, + { + "EventName": "l3victimstate.t7.s0.F_S", + "EventCode": "0x09", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 Victim State", + "L3ThreadMask": "0x80", + "L3SliceMask": "0x01", + "UMask": "0x04" + }, + + { + "EventName": "l3victimstate.t0.s1.F_S", + "EventCode": "0x09", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 Victim State", + "L3ThreadMask": "0x01", + "L3SliceMask": "0x02", + "UMask": "0x04" + }, + { + "EventName": "l3victimstate.t1.s1.F_S", + "EventCode": "0x09", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 Victim State", + "L3ThreadMask": "0x02", + "L3SliceMask": "0x02", + "UMask": "0x04" + }, + { + "EventName": "l3victimstate.t2.s1.F_S", + "EventCode": "0x09", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 Victim State", + "L3ThreadMask": "0x04", + "L3SliceMask": "0x02", + "UMask": "0x04" + }, + { + "EventName": "l3victimstate.t3.s1.F_S", + "EventCode": "0x09", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 Victim State", + "L3ThreadMask": "0x08", + "L3SliceMask": "0x02", + "UMask": "0x04" + }, + { + "EventName": "l3victimstate.t4.s1.F_S", + "EventCode": "0x09", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 Victim State", + "L3ThreadMask": "0x10", + "L3SliceMask": "0x02", + "UMask": "0x04" + }, + { + "EventName": "l3victimstate.t5.s1.F_S", + "EventCode": "0x09", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 Victim State", + "L3ThreadMask": "0x20", + "L3SliceMask": "0x02", + "UMask": "0x04" + }, + { + "EventName": "l3victimstate.t6.s1.F_S", + "EventCode": "0x09", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 Victim State", + "L3ThreadMask": "0x40", + "L3SliceMask": "0x02", + "UMask": "0x04" + }, + { + "EventName": "l3victimstate.t7.s1.F_S", + "EventCode": "0x09", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 Victim State", + "L3ThreadMask": "0x80", + "L3SliceMask": "0x02", + "UMask": "0x04" + }, + { + "EventName": "l3victimstate.t0.s2.F_S", + "EventCode": "0x09", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 Victim State", + "L3ThreadMask": "0x01", + "L3SliceMask": "0x04", + "UMask": "0x04" + }, + { + "EventName": "l3victimstate.t1.s2.F_S", + "EventCode": "0x09", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 Victim State", + "L3ThreadMask": "0x02", + "L3SliceMask": "0x04", + "UMask": "0x04" + }, + { + "EventName": "l3victimstate.t2.s2.F_S", + "EventCode": "0x09", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 Victim State", + "L3ThreadMask": "0x04", + "L3SliceMask": "0x04", + "UMask": "0x04" + }, + { + "EventName": "l3victimstate.t3.s2.F_S", + "EventCode": "0x09", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 Victim State", + "L3ThreadMask": "0x08", + "L3SliceMask": "0x04", + "UMask": "0x04" + }, + { + "EventName": "l3victimstate.t4.s2.F_S", + "EventCode": "0x09", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 Victim State", + "L3ThreadMask": "0x10", + "L3SliceMask": "0x04", + "UMask": "0x04" + }, + { + "EventName": "l3victimstate.t5.s2.F_S", + "EventCode": "0x09", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 Victim State", + "L3ThreadMask": "0x20", + "L3SliceMask": "0x04", + "UMask": "0x04" + }, + { + "EventName": "l3victimstate.t6.s2.F_S", + "EventCode": "0x09", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 Victim State", + "L3ThreadMask": "0x40", + "L3SliceMask": "0x04", + "UMask": "0x04" + }, + { + "EventName": "l3victimstate.t7.s2.F_S", + "EventCode": "0x09", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 Victim State", + "L3ThreadMask": "0x80", + "L3SliceMask": "0x04", + "UMask": "0x04" + }, + { + "EventName": "l3victimstate.t0.s3.F_S", + "EventCode": "0x09", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 Victim State", + "L3ThreadMask": "0x01", + "L3SliceMask": "0x08", + "UMask": "0x04" + }, + { + "EventName": "l3victimstate.t1.s3.F_S", + "EventCode": "0x09", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 Victim State", + "L3ThreadMask": "0x02", + "L3SliceMask": "0x08", + "UMask": "0x04" + }, + { + "EventName": "l3victimstate.t2.s3.F_S", + "EventCode": "0x09", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 Victim State", + "L3ThreadMask": "0x04", + "L3SliceMask": "0x08", + "UMask": "0x04" + }, + { + "EventName": "l3victimstate.t3.s3.F_S", + "EventCode": "0x09", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 Victim State", + "L3ThreadMask": "0x08", + "L3SliceMask": "0x08", + "UMask": "0x04" + }, + { + "EventName": "l3victimstate.t4.s3.F_S", + "EventCode": "0x09", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 Victim State", + "L3ThreadMask": "0x10", + "L3SliceMask": "0x08", + "UMask": "0x04" + }, + { + "EventName": "l3victimstate.t5.s3.F_S", + "EventCode": "0x09", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 Victim State", + "L3ThreadMask": "0x20", + "L3SliceMask": "0x08", + "UMask": "0x04" + }, + { + "EventName": "l3victimstate.t6.s3.F_S", + "EventCode": "0x09", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 Victim State", + "L3ThreadMask": "0x40", + "L3SliceMask": "0x08", + "UMask": "0x04" + }, + { + "EventName": "l3victimstate.t7.s3.F_S", + "EventCode": "0x09", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 Victim State", + "L3ThreadMask": "0x80", + "L3SliceMask": "0x08", + "UMask": "0x04" + }, + { + "EventName": "l3victimstate.t0.s0.o", + "EventCode": "0x09", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 Victim State", + "L3ThreadMask": "0x01", + "L3SliceMask": "0x01", + "UMask": "0x08" + }, + { + "EventName": "l3victimstate.t1.s0.o", + "EventCode": "0x09", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 Victim State", + "L3ThreadMask": "0x02", + "L3SliceMask": "0x01", + "UMask": "0x08" + }, + { + "EventName": "l3victimstate.t2.s0.o", + "EventCode": "0x09", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 Victim State", + "L3ThreadMask": "0x04", + "L3SliceMask": "0x01", + "UMask": "0x08" + }, + { + "EventName": "l3victimstate.t3.s0.o", + "EventCode": "0x09", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 Victim State", + "L3ThreadMask": "0x08", + "L3SliceMask": "0x01", + "UMask": "0x08" + }, + { + "EventName": "l3victimstate.t4.s0.o", + "EventCode": "0x09", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 Victim State", + "L3ThreadMask": "0x10", + "L3SliceMask": "0x01", + "UMask": "0x08" + }, + { + "EventName": "l3victimstate.t5.s0.o", + "EventCode": "0x09", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 Victim State", + "L3ThreadMask": "0x20", + "L3SliceMask": "0x01", + "UMask": "0x08" + }, + { + "EventName": "l3victimstate.t6.s0.o", + "EventCode": "0x09", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 Victim State", + "L3ThreadMask": "0x40", + "L3SliceMask": "0x01", + "UMask": "0x08" + }, + { + "EventName": "l3victimstate.t7.s0.o", + "EventCode": "0x09", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 Victim State", + "L3ThreadMask": "0x80", + "L3SliceMask": "0x01", + "UMask": "0x08" + }, + + { + "EventName": "l3victimstate.t0.s1.o", + "EventCode": "0x09", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 Victim State", + "L3ThreadMask": "0x01", + "L3SliceMask": "0x02", + "UMask": "0x08" + }, + { + "EventName": "l3victimstate.t1.s1.o", + "EventCode": "0x09", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 Victim State", + "L3ThreadMask": "0x02", + "L3SliceMask": "0x02", + "UMask": "0x08" + }, + { + "EventName": "l3victimstate.t2.s1.o", + "EventCode": "0x09", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 Victim State", + "L3ThreadMask": "0x04", + "L3SliceMask": "0x02", + "UMask": "0x08" + }, + { + "EventName": "l3victimstate.t3.s1.o", + "EventCode": "0x09", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 Victim State", + "L3ThreadMask": "0x08", + "L3SliceMask": "0x02", + "UMask": "0x08" + }, + { + "EventName": "l3victimstate.t4.s1.o", + "EventCode": "0x09", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 Victim State", + "L3ThreadMask": "0x10", + "L3SliceMask": "0x02", + "UMask": "0x08" + }, + { + "EventName": "l3victimstate.t5.s1.o", + "EventCode": "0x09", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 Victim State", + "L3ThreadMask": "0x20", + "L3SliceMask": "0x02", + "UMask": "0x08" + }, + { + "EventName": "l3victimstate.t6.s1.o", + "EventCode": "0x09", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 Victim State", + "L3ThreadMask": "0x40", + "L3SliceMask": "0x02", + "UMask": "0x08" + }, + { + "EventName": "l3victimstate.t7.s1.o", + "EventCode": "0x09", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 Victim State", + "L3ThreadMask": "0x80", + "L3SliceMask": "0x02", + "UMask": "0x08" + }, + { + "EventName": "l3victimstate.t0.s2.o", + "EventCode": "0x09", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 Victim State", + "L3ThreadMask": "0x01", + "L3SliceMask": "0x04", + "UMask": "0x08" + }, + { + "EventName": "l3victimstate.t1.s2.o", + "EventCode": "0x09", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 Victim State", + "L3ThreadMask": "0x02", + "L3SliceMask": "0x04", + "UMask": "0x08" + }, + { + "EventName": "l3victimstate.t2.s2.o", + "EventCode": "0x09", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 Victim State", + "L3ThreadMask": "0x04", + "L3SliceMask": "0x04", + "UMask": "0x08" + }, + { + "EventName": "l3victimstate.t3.s2.o", + "EventCode": "0x09", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 Victim State", + "L3ThreadMask": "0x08", + "L3SliceMask": "0x04", + "UMask": "0x08" + }, + { + "EventName": "l3victimstate.t4.s2.o", + "EventCode": "0x09", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 Victim State", + "L3ThreadMask": "0x10", + "L3SliceMask": "0x04", + "UMask": "0x08" + }, + { + "EventName": "l3victimstate.t5.s2.o", + "EventCode": "0x09", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 Victim State", + "L3ThreadMask": "0x20", + "L3SliceMask": "0x04", + "UMask": "0x08" + }, + { + "EventName": "l3victimstate.t6.s2.o", + "EventCode": "0x09", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 Victim State", + "L3ThreadMask": "0x40", + "L3SliceMask": "0x04", + "UMask": "0x08" + }, + { + "EventName": "l3victimstate.t7.s2.o", + "EventCode": "0x09", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 Victim State", + "L3ThreadMask": "0x80", + "L3SliceMask": "0x04", + "UMask": "0x08" + }, + { + "EventName": "l3victimstate.t0.s3.o", + "EventCode": "0x09", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 Victim State", + "L3ThreadMask": "0x01", + "L3SliceMask": "0x08", + "UMask": "0x08" + }, + { + "EventName": "l3victimstate.t1.s3.o", + "EventCode": "0x09", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 Victim State", + "L3ThreadMask": "0x02", + "L3SliceMask": "0x08", + "UMask": "0x08" + }, + { + "EventName": "l3victimstate.t2.s3.o", + "EventCode": "0x09", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 Victim State", + "L3ThreadMask": "0x04", + "L3SliceMask": "0x08", + "UMask": "0x08" + }, + { + "EventName": "l3victimstate.t3.s3.o", + "EventCode": "0x09", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 Victim State", + "L3ThreadMask": "0x08", + "L3SliceMask": "0x08", + "UMask": "0x08" + }, + { + "EventName": "l3victimstate.t4.s3.o", + "EventCode": "0x09", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 Victim State", + "L3ThreadMask": "0x10", + "L3SliceMask": "0x08", + "UMask": "0x08" + }, + { + "EventName": "l3victimstate.t5.s3.o", + "EventCode": "0x09", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 Victim State", + "L3ThreadMask": "0x20", + "L3SliceMask": "0x08", + "UMask": "0x08" + }, + { + "EventName": "l3victimstate.t6.s3.o", + "EventCode": "0x09", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 Victim State", + "L3ThreadMask": "0x40", + "L3SliceMask": "0x08", + "UMask": "0x08" + }, + { + "EventName": "l3victimstate.t7.s3.o", + "EventCode": "0x09", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 Victim State", + "L3ThreadMask": "0x80", + "L3SliceMask": "0x08", + "UMask": "0x08" + }, + { + "EventName": "l3victimstate.t0.s0.e_fe", + "EventCode": "0x09", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 Victim State", + "L3ThreadMask": "0x01", + "L3SliceMask": "0x01", + "UMask": "0x10" + }, + { + "EventName": "l3victimstate.t1.s0.e_fe", + "EventCode": "0x09", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 Victim State", + "L3ThreadMask": "0x02", + "L3SliceMask": "0x01", + "UMask": "0x10" + }, + { + "EventName": "l3victimstate.t2.s0.e_fe", + "EventCode": "0x09", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 Victim State", + "L3ThreadMask": "0x04", + "L3SliceMask": "0x01", + "UMask": "0x10" + }, + { + "EventName": "l3victimstate.t3.s0.e_fe", + "EventCode": "0x09", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 Victim State", + "L3ThreadMask": "0x08", + "L3SliceMask": "0x01", + "UMask": "0x10" + }, + { + "EventName": "l3victimstate.t4.s0.e_fe", + "EventCode": "0x09", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 Victim State", + "L3ThreadMask": "0x10", + "L3SliceMask": "0x01", + "UMask": "0x10" + }, + { + "EventName": "l3victimstate.t5.s0.e_fe", + "EventCode": "0x09", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 Victim State", + "L3ThreadMask": "0x20", + "L3SliceMask": "0x01", + "UMask": "0x10" + }, + { + "EventName": "l3victimstate.t6.s0.e_fe", + "EventCode": "0x09", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 Victim State", + "L3ThreadMask": "0x40", + "L3SliceMask": "0x01", + "UMask": "0x10" + }, + { + "EventName": "l3victimstate.t7.s0.e_fe", + "EventCode": "0x09", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 Victim State", + "L3ThreadMask": "0x80", + "L3SliceMask": "0x01", + "UMask": "0x10" + }, + + { + "EventName": "l3victimstate.t0.s1.e_fe", + "EventCode": "0x09", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 Victim State", + "L3ThreadMask": "0x01", + "L3SliceMask": "0x02", + "UMask": "0x10" + }, + { + "EventName": "l3victimstate.t1.s1.e_fe", + "EventCode": "0x09", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 Victim State", + "L3ThreadMask": "0x02", + "L3SliceMask": "0x02", + "UMask": "0x10" + }, + { + "EventName": "l3victimstate.t2.s1.e_fe", + "EventCode": "0x09", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 Victim State", + "L3ThreadMask": "0x04", + "L3SliceMask": "0x02", + "UMask": "0x10" + }, + { + "EventName": "l3victimstate.t3.s1.e_fe", + "EventCode": "0x09", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 Victim State", + "L3ThreadMask": "0x08", + "L3SliceMask": "0x02", + "UMask": "0x10" + }, + { + "EventName": "l3victimstate.t4.s1.e_fe", + "EventCode": "0x09", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 Victim State", + "L3ThreadMask": "0x10", + "L3SliceMask": "0x02", + "UMask": "0x10" + }, + { + "EventName": "l3victimstate.t5.s1.e_fe", + "EventCode": "0x09", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 Victim State", + "L3ThreadMask": "0x20", + "L3SliceMask": "0x02", + "UMask": "0x10" + }, + { + "EventName": "l3victimstate.t6.s1.e_fe", + "EventCode": "0x09", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 Victim State", + "L3ThreadMask": "0x40", + "L3SliceMask": "0x02", + "UMask": "0x10" + }, + { + "EventName": "l3victimstate.t7.s1.e_fe", + "EventCode": "0x09", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 Victim State", + "L3ThreadMask": "0x80", + "L3SliceMask": "0x02", + "UMask": "0x10" + }, + { + "EventName": "l3victimstate.t0.s2.e_fe", + "EventCode": "0x09", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 Victim State", + "L3ThreadMask": "0x01", + "L3SliceMask": "0x04", + "UMask": "0x10" + }, + { + "EventName": "l3victimstate.t1.s2.e_fe", + "EventCode": "0x09", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 Victim State", + "L3ThreadMask": "0x02", + "L3SliceMask": "0x04", + "UMask": "0x10" + }, + { + "EventName": "l3victimstate.t2.s2.e_fe", + "EventCode": "0x09", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 Victim State", + "L3ThreadMask": "0x04", + "L3SliceMask": "0x04", + "UMask": "0x10" + }, + { + "EventName": "l3victimstate.t3.s2.e_fe", + "EventCode": "0x09", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 Victim State", + "L3ThreadMask": "0x08", + "L3SliceMask": "0x04", + "UMask": "0x10" + }, + { + "EventName": "l3victimstate.t4.s2.e_fe", + "EventCode": "0x09", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 Victim State", + "L3ThreadMask": "0x10", + "L3SliceMask": "0x04", + "UMask": "0x10" + }, + { + "EventName": "l3victimstate.t5.s2.e_fe", + "EventCode": "0x09", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 Victim State", + "L3ThreadMask": "0x20", + "L3SliceMask": "0x04", + "UMask": "0x10" + }, + { + "EventName": "l3victimstate.t6.s2.e_fe", + "EventCode": "0x09", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 Victim State", + "L3ThreadMask": "0x40", + "L3SliceMask": "0x04", + "UMask": "0x10" + }, + { + "EventName": "l3victimstate.t7.s2.e_fe", + "EventCode": "0x09", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 Victim State", + "L3ThreadMask": "0x80", + "L3SliceMask": "0x04", + "UMask": "0x10" + }, + { + "EventName": "l3victimstate.t0.s3.e_fe", + "EventCode": "0x09", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 Victim State", + "L3ThreadMask": "0x01", + "L3SliceMask": "0x08", + "UMask": "0x10" + }, + { + "EventName": "l3victimstate.t1.s3.e_fe", + "EventCode": "0x09", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 Victim State", + "L3ThreadMask": "0x02", + "L3SliceMask": "0x08", + "UMask": "0x10" + }, + { + "EventName": "l3victimstate.t2.s3.e_fe", + "EventCode": "0x09", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 Victim State", + "L3ThreadMask": "0x04", + "L3SliceMask": "0x08", + "UMask": "0x10" + }, + { + "EventName": "l3victimstate.t3.s3.e_fe", + "EventCode": "0x09", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 Victim State", + "L3ThreadMask": "0x08", + "L3SliceMask": "0x08", + "UMask": "0x10" + }, + { + "EventName": "l3victimstate.t4.s3.e_fe", + "EventCode": "0x09", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 Victim State", + "L3ThreadMask": "0x10", + "L3SliceMask": "0x08", + "UMask": "0x10" + }, + { + "EventName": "l3victimstate.t5.s3.e_fe", + "EventCode": "0x09", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 Victim State", + "L3ThreadMask": "0x20", + "L3SliceMask": "0x08", + "UMask": "0x10" + }, + { + "EventName": "l3victimstate.t6.s3.e_fe", + "EventCode": "0x09", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 Victim State", + "L3ThreadMask": "0x40", + "L3SliceMask": "0x08", + "UMask": "0x10" + }, + { + "EventName": "l3victimstate.t7.s3.e_fe", + "EventCode": "0x09", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 Victim State", + "L3ThreadMask": "0x80", + "L3SliceMask": "0x08" + }, + { + "EventName": "l3victimstate.t0.s0.m", + "EventCode": "0x09", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 Victim State", + "L3ThreadMask": "0x01", + "L3SliceMask": "0x01", + "UMask": "0x20" + }, + { + "EventName": "l3victimstate.t1.s0.m", + "EventCode": "0x09", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 Victim State", + "L3ThreadMask": "0x02", + "L3SliceMask": "0x01", + "UMask": "0x20" + }, + { + "EventName": "l3victimstate.t2.s0.m", + "EventCode": "0x09", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 Victim State", + "L3ThreadMask": "0x04", + "L3SliceMask": "0x01", + "UMask": "0x20" + }, + { + "EventName": "l3victimstate.t3.s0.m", + "EventCode": "0x09", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 Victim State", + "L3ThreadMask": "0x08", + "L3SliceMask": "0x01", + "UMask": "0x20" + }, + { + "EventName": "l3victimstate.t4.s0.m", + "EventCode": "0x09", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 Victim State", + "L3ThreadMask": "0x10", + "L3SliceMask": "0x01", + "UMask": "0x20" + }, + { + "EventName": "l3victimstate.t5.s0.m", + "EventCode": "0x09", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 Victim State", + "L3ThreadMask": "0x20", + "L3SliceMask": "0x01", + "UMask": "0x20" + }, + { + "EventName": "l3victimstate.t6.s0.m", + "EventCode": "0x09", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 Victim State", + "L3ThreadMask": "0x40", + "L3SliceMask": "0x01", + "UMask": "0x20" + }, + { + "EventName": "l3victimstate.t7.s0.m", + "EventCode": "0x09", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 Victim State", + "L3ThreadMask": "0x80", + "L3SliceMask": "0x01", + "UMask": "0x20" + }, + + { + "EventName": "l3victimstate.t0.s1.m", + "EventCode": "0x09", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 Victim State", + "L3ThreadMask": "0x01", + "L3SliceMask": "0x02", + "UMask": "0x20" + }, + { + "EventName": "l3victimstate.t1.s1.m", + "EventCode": "0x09", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 Victim State", + "L3ThreadMask": "0x02", + "L3SliceMask": "0x02", + "UMask": "0x20" + }, + { + "EventName": "l3victimstate.t2.s1.m", + "EventCode": "0x09", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 Victim State", + "L3ThreadMask": "0x04", + "L3SliceMask": "0x02", + "UMask": "0x20" + }, + { + "EventName": "l3victimstate.t3.s1.m", + "EventCode": "0x09", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 Victim State", + "L3ThreadMask": "0x08", + "L3SliceMask": "0x02", + "UMask": "0x20" + }, + { + "EventName": "l3victimstate.t4.s1.m", + "EventCode": "0x09", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 Victim State", + "L3ThreadMask": "0x10", + "L3SliceMask": "0x02", + "UMask": "0x20" + }, + { + "EventName": "l3victimstate.t5.s1.m", + "EventCode": "0x09", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 Victim State", + "L3ThreadMask": "0x20", + "L3SliceMask": "0x02", + "UMask": "0x20" + }, + { + "EventName": "l3victimstate.t6.s1.m", + "EventCode": "0x09", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 Victim State", + "L3ThreadMask": "0x40", + "L3SliceMask": "0x02", + "UMask": "0x20" + }, + { + "EventName": "l3victimstate.t7.s1.m", + "EventCode": "0x09", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 Victim State", + "L3ThreadMask": "0x80", + "L3SliceMask": "0x02", + "UMask": "0x20" + }, + { + "EventName": "l3victimstate.t0.s2.m", + "EventCode": "0x09", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 Victim State", + "L3ThreadMask": "0x01", + "L3SliceMask": "0x04", + "UMask": "0x20" + }, + { + "EventName": "l3victimstate.t1.s2.m", + "EventCode": "0x09", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 Victim State", + "L3ThreadMask": "0x02", + "L3SliceMask": "0x04", + "UMask": "0x20" + }, + { + "EventName": "l3victimstate.t2.s2.m", + "EventCode": "0x09", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 Victim State", + "L3ThreadMask": "0x04", + "L3SliceMask": "0x04", + "UMask": "0x20" + }, + { + "EventName": "l3victimstate.t3.s2.m", + "EventCode": "0x09", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 Victim State", + "L3ThreadMask": "0x08", + "L3SliceMask": "0x04", + "UMask": "0x20" + }, + { + "EventName": "l3victimstate.t4.s2.m", + "EventCode": "0x09", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 Victim State", + "L3ThreadMask": "0x10", + "L3SliceMask": "0x04", + "UMask": "0x20" + }, + { + "EventName": "l3victimstate.t5.s2.m", + "EventCode": "0x09", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 Victim State", + "L3ThreadMask": "0x20", + "L3SliceMask": "0x04", + "UMask": "0x20" + }, + { + "EventName": "l3victimstate.t6.s2.m", + "EventCode": "0x09", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 Victim State", + "L3ThreadMask": "0x40", + "L3SliceMask": "0x04", + "UMask": "0x20" + }, + { + "EventName": "l3victimstate.t7.s2.m", + "EventCode": "0x09", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 Victim State", + "L3ThreadMask": "0x80", + "L3SliceMask": "0x04", + "UMask": "0x20" + }, + { + "EventName": "l3victimstate.t0.s3.m", + "EventCode": "0x09", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 Victim State", + "L3ThreadMask": "0x01", + "L3SliceMask": "0x08", + "UMask": "0x20" + }, + { + "EventName": "l3victimstate.t1.s3.m", + "EventCode": "0x09", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 Victim State", + "L3ThreadMask": "0x02", + "L3SliceMask": "0x08", + "UMask": "0x20" + }, + { + "EventName": "l3victimstate.t2.s3.m", + "EventCode": "0x09", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 Victim State", + "L3ThreadMask": "0x04", + "L3SliceMask": "0x08", + "UMask": "0x20" + }, + { + "EventName": "l3victimstate.t3.s3.m", + "EventCode": "0x09", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 Victim State", + "L3ThreadMask": "0x08", + "L3SliceMask": "0x08", + "UMask": "0x20" + }, + { + "EventName": "l3victimstate.t4.s3.m", + "EventCode": "0x09", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 Victim State", + "L3ThreadMask": "0x10", + "L3SliceMask": "0x08", + "UMask": "0x20" + }, + { + "EventName": "l3victimstate.t5.s3.m", + "EventCode": "0x09", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 Victim State", + "L3ThreadMask": "0x20", + "L3SliceMask": "0x08", + "UMask": "0x20" + }, + { + "EventName": "l3victimstate.t6.s3.m", + "EventCode": "0x09", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 Victim State", + "L3ThreadMask": "0x40", + "L3SliceMask": "0x08", + "UMask": "0x20" + }, + { + "EventName": "l3victimstate.t7.s3.m", + "EventCode": "0x09", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 Victim State", + "L3ThreadMask": "0x80", + "L3SliceMask": "0x08", + "UMask": "0x20" + }, + { + "EventName": "l3victimstate.t0.s0.d", + "EventCode": "0x09", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 Victim State", + "L3ThreadMask": "0x01", + "L3SliceMask": "0x01", + "UMask": "0x40" + }, + { + "EventName": "l3victimstate.t1.s0.d", + "EventCode": "0x09", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 Victim State", + "L3ThreadMask": "0x02", + "L3SliceMask": "0x01", + "UMask": "0x40" + }, + { + "EventName": "l3victimstate.t2.s0.d", + "EventCode": "0x09", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 Victim State", + "L3ThreadMask": "0x04", + "L3SliceMask": "0x01", + "UMask": "0x40" + }, + { + "EventName": "l3victimstate.t3.s0.d", + "EventCode": "0x09", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 Victim State", + "L3ThreadMask": "0x08", + "L3SliceMask": "0x01", + "UMask": "0x40" + }, + { + "EventName": "l3victimstate.t4.s0.d", + "EventCode": "0x09", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 Victim State", + "L3ThreadMask": "0x10", + "L3SliceMask": "0x01", + "UMask": "0x40" + }, + { + "EventName": "l3victimstate.t5.s0.d", + "EventCode": "0x09", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 Victim State", + "L3ThreadMask": "0x20", + "L3SliceMask": "0x01", + "UMask": "0x40" + }, + { + "EventName": "l3victimstate.t6.s0.d", + "EventCode": "0x09", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 Victim State", + "L3ThreadMask": "0x40", + "L3SliceMask": "0x01", + "UMask": "0x40" + }, + { + "EventName": "l3victimstate.t7.s0.d", + "EventCode": "0x09", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 Victim State", + "L3ThreadMask": "0x80", + "L3SliceMask": "0x01", + "UMask": "0x40" + }, + + { + "EventName": "l3victimstate.t0.s1.d", + "EventCode": "0x09", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 Victim State", + "L3ThreadMask": "0x01", + "L3SliceMask": "0x02", + "UMask": "0x40" + }, + { + "EventName": "l3victimstate.t1.s1.d", + "EventCode": "0x09", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 Victim State", + "L3ThreadMask": "0x02", + "L3SliceMask": "0x02", + "UMask": "0x40" + }, + { + "EventName": "l3victimstate.t2.s1.d", + "EventCode": "0x09", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 Victim State", + "L3ThreadMask": "0x04", + "L3SliceMask": "0x02", + "UMask": "0x40" + }, + { + "EventName": "l3victimstate.t3.s1.d", + "EventCode": "0x09", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 Victim State", + "L3ThreadMask": "0x08", + "L3SliceMask": "0x02", + "UMask": "0x40" + }, + { + "EventName": "l3victimstate.t4.s1.d", + "EventCode": "0x09", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 Victim State", + "L3ThreadMask": "0x10", + "L3SliceMask": "0x02", + "UMask": "0x40" + }, + { + "EventName": "l3victimstate.t5.s1.d", + "EventCode": "0x09", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 Victim State", + "L3ThreadMask": "0x20", + "L3SliceMask": "0x02", + "UMask": "0x40" + }, + { + "EventName": "l3victimstate.t6.s1.d", + "EventCode": "0x09", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 Victim State", + "L3ThreadMask": "0x40", + "L3SliceMask": "0x02", + "UMask": "0x40" + }, + { + "EventName": "l3victimstate.t7.s1.d", + "EventCode": "0x09", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 Victim State", + "L3ThreadMask": "0x80", + "L3SliceMask": "0x02", + "UMask": "0x40" + }, + { + "EventName": "l3victimstate.t0.s2.d", + "EventCode": "0x09", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 Victim State", + "L3ThreadMask": "0x01", + "L3SliceMask": "0x04", + "UMask": "0x40" + }, + { + "EventName": "l3victimstate.t1.s2.d", + "EventCode": "0x09", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 Victim State", + "L3ThreadMask": "0x02", + "L3SliceMask": "0x04", + "UMask": "0x40" + }, + { + "EventName": "l3victimstate.t2.s2.d", + "EventCode": "0x09", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 Victim State", + "L3ThreadMask": "0x04", + "L3SliceMask": "0x04", + "UMask": "0x40" + }, + { + "EventName": "l3victimstate.t3.s2.d", + "EventCode": "0x09", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 Victim State", + "L3ThreadMask": "0x08", + "L3SliceMask": "0x04", + "UMask": "0x40" + }, + { + "EventName": "l3victimstate.t4.s2.d", + "EventCode": "0x09", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 Victim State", + "L3ThreadMask": "0x10", + "L3SliceMask": "0x04", + "UMask": "0x40" + }, + { + "EventName": "l3victimstate.t5.s2.d", + "EventCode": "0x09", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 Victim State", + "L3ThreadMask": "0x20", + "L3SliceMask": "0x04", + "UMask": "0x40" + }, + { + "EventName": "l3victimstate.t6.s2.d", + "EventCode": "0x09", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 Victim State", + "L3ThreadMask": "0x40", + "L3SliceMask": "0x04", + "UMask": "0x40" + }, + { + "EventName": "l3victimstate.t7.s2.d", + "EventCode": "0x09", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 Victim State", + "L3ThreadMask": "0x80", + "L3SliceMask": "0x04", + "UMask": "0x40" + }, + { + "EventName": "l3victimstate.t0.s3.d", + "EventCode": "0x09", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 Victim State", + "L3ThreadMask": "0x01", + "L3SliceMask": "0x08", + "UMask": "0x40" + }, + { + "EventName": "l3victimstate.t1.s3.d", + "EventCode": "0x09", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 Victim State", + "L3ThreadMask": "0x02", + "L3SliceMask": "0x08", + "UMask": "0x40" + }, + { + "EventName": "l3victimstate.t2.s3.d", + "EventCode": "0x09", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 Victim State", + "L3ThreadMask": "0x04", + "L3SliceMask": "0x08", + "UMask": "0x40" + }, + { + "EventName": "l3victimstate.t3.s3.d", + "EventCode": "0x09", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 Victim State", + "L3ThreadMask": "0x08", + "L3SliceMask": "0x08", + "UMask": "0x40" + }, + { + "EventName": "l3victimstate.t4.s3.d", + "EventCode": "0x09", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 Victim State", + "L3ThreadMask": "0x10", + "L3SliceMask": "0x08", + "UMask": "0x40" + }, + { + "EventName": "l3victimstate.t5.s3.d", + "EventCode": "0x09", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 Victim State", + "L3ThreadMask": "0x20", + "L3SliceMask": "0x08", + "UMask": "0x40" + }, + { + "EventName": "l3victimstate.t6.s3.d", + "EventCode": "0x09", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 Victim State", + "L3ThreadMask": "0x40", + "L3SliceMask": "0x08", + "UMask": "0x40" + }, + { + "EventName": "l3victimstate.t7.s3.d", + "EventCode": "0x09", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 Victim State", + "L3ThreadMask": "0x80", + "L3SliceMask": "0x08", + "UMask": "0x40" + }, + { + "EventName": "l3victimstate.t0.s0.od", + "EventCode": "0x09", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 Victim State", + "L3ThreadMask": "0x01", + "L3SliceMask": "0x01", + "UMask": "0x80" + }, + { + "EventName": "l3victimstate.t1.s0.od", + "EventCode": "0x09", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 Victim State", + "L3ThreadMask": "0x02", + "L3SliceMask": "0x01", + "UMask": "0x80" + }, + { + "EventName": "l3victimstate.t2.s0.od", + "EventCode": "0x09", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 Victim State", + "L3ThreadMask": "0x04", + "L3SliceMask": "0x01", + "UMask": "0x80" + }, + { + "EventName": "l3victimstate.t3.s0.od", + "EventCode": "0x09", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 Victim State", + "L3ThreadMask": "0x08", + "L3SliceMask": "0x01", + "UMask": "0x80" + }, + { + "EventName": "l3victimstate.t4.s0.od", + "EventCode": "0x09", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 Victim State", + "L3ThreadMask": "0x10", + "L3SliceMask": "0x01", + "UMask": "0x80" + }, + { + "EventName": "l3victimstate.t5.s0.od", + "EventCode": "0x09", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 Victim State", + "L3ThreadMask": "0x20", + "L3SliceMask": "0x01", + "UMask": "0x80" + }, + { + "EventName": "l3victimstate.t6.s0.od", + "EventCode": "0x09", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 Victim State", + "L3ThreadMask": "0x40", + "L3SliceMask": "0x01", + "UMask": "0x80" + }, + { + "EventName": "l3victimstate.t7.s0.od", + "EventCode": "0x09", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 Victim State", + "L3ThreadMask": "0x80", + "L3SliceMask": "0x01", + "UMask": "0x80" + }, + + { + "EventName": "l3victimstate.t0.s1.od", + "EventCode": "0x09", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 Victim State", + "L3ThreadMask": "0x01", + "L3SliceMask": "0x02", + "UMask": "0x80" + }, + { + "EventName": "l3victimstate.t1.s1.od", + "EventCode": "0x09", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 Victim State", + "L3ThreadMask": "0x02", + "L3SliceMask": "0x02", + "UMask": "0x80" + }, + { + "EventName": "l3victimstate.t2.s1.od", + "EventCode": "0x09", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 Victim State", + "L3ThreadMask": "0x04", + "L3SliceMask": "0x02", + "UMask": "0x80" + }, + { + "EventName": "l3victimstate.t3.s1.od", + "EventCode": "0x09", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 Victim State", + "L3ThreadMask": "0x08", + "L3SliceMask": "0x02", + "UMask": "0x80" + }, + { + "EventName": "l3victimstate.t4.s1.od", + "EventCode": "0x09", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 Victim State", + "L3ThreadMask": "0x10", + "L3SliceMask": "0x02", + "UMask": "0x80" + }, + { + "EventName": "l3victimstate.t5.s1.od", + "EventCode": "0x09", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 Victim State", + "L3ThreadMask": "0x20", + "L3SliceMask": "0x02", + "UMask": "0x80" + }, + { + "EventName": "l3victimstate.t6.s1.od", + "EventCode": "0x09", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 Victim State", + "L3ThreadMask": "0x40", + "L3SliceMask": "0x02", + "UMask": "0x80" + }, + { + "EventName": "l3victimstate.t7.s1.od", + "EventCode": "0x09", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 Victim State", + "L3ThreadMask": "0x80", + "L3SliceMask": "0x02", + "UMask": "0x80" + }, + { + "EventName": "l3victimstate.t0.s2.od", + "EventCode": "0x09", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 Victim State", + "L3ThreadMask": "0x01", + "L3SliceMask": "0x04", + "UMask": "0x80" + }, + { + "EventName": "l3victimstate.t1.s2.od", + "EventCode": "0x09", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 Victim State", + "L3ThreadMask": "0x02", + "L3SliceMask": "0x04", + "UMask": "0x80" + }, + { + "EventName": "l3victimstate.t2.s2.od", + "EventCode": "0x09", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 Victim State", + "L3ThreadMask": "0x04", + "L3SliceMask": "0x04", + "UMask": "0x80" + }, + { + "EventName": "l3victimstate.t3.s2.od", + "EventCode": "0x09", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 Victim State", + "L3ThreadMask": "0x08", + "L3SliceMask": "0x04", + "UMask": "0x80" + }, + { + "EventName": "l3victimstate.t4.s2.od", + "EventCode": "0x09", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 Victim State", + "L3ThreadMask": "0x10", + "L3SliceMask": "0x04", + "UMask": "0x80" + }, + { + "EventName": "l3victimstate.t5.s2.od", + "EventCode": "0x09", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 Victim State", + "L3ThreadMask": "0x20", + "L3SliceMask": "0x04", + "UMask": "0x80" + }, + { + "EventName": "l3victimstate.t6.s2.od", + "EventCode": "0x09", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 Victim State", + "L3ThreadMask": "0x40", + "L3SliceMask": "0x04", + "UMask": "0x80" + }, + { + "EventName": "l3victimstate.t7.s2.od", + "EventCode": "0x09", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 Victim State", + "L3ThreadMask": "0x80", + "L3SliceMask": "0x04", + "UMask": "0x80" + }, + { + "EventName": "l3victimstate.t0.s3.od", + "EventCode": "0x09", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 Victim State", + "L3ThreadMask": "0x01", + "L3SliceMask": "0x08", + "UMask": "0x80" + }, + { + "EventName": "l3victimstate.t1.s3.od", + "EventCode": "0x09", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 Victim State", + "L3ThreadMask": "0x02", + "L3SliceMask": "0x08", + "UMask": "0x80" + }, + { + "EventName": "l3victimstate.t2.s3.od", + "EventCode": "0x09", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 Victim State", + "L3ThreadMask": "0x04", + "L3SliceMask": "0x08", + "UMask": "0x80" + }, + { + "EventName": "l3victimstate.t3.s3.od", + "EventCode": "0x09", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 Victim State", + "L3ThreadMask": "0x08", + "L3SliceMask": "0x08", + "UMask": "0x80" + }, + { + "EventName": "l3victimstate.t4.s3.od", + "EventCode": "0x09", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 Victim State", + "L3ThreadMask": "0x10", + "L3SliceMask": "0x08", + "UMask": "0x80" + }, + { + "EventName": "l3victimstate.t5.s3.od", + "EventCode": "0x09", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 Victim State", + "L3ThreadMask": "0x20", + "L3SliceMask": "0x08", + "UMask": "0x80" + }, + { + "EventName": "l3victimstate.t6.s3.od", + "EventCode": "0x09", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 Victim State", + "L3ThreadMask": "0x40", + "L3SliceMask": "0x08", + "UMask": "0x80" + }, + { + "EventName": "l3victimstate.t7.s3.od", + "EventCode": "0x09", + "BriefDescription": "L3 Cache Performance Monitor Counters L3 Victim State", + "L3ThreadMask": "0x80", + "L3SliceMask": "0x08", + "UMask": "0x80" + } + +] + Property changes on: head/lib/libpmc/pmu-events/arch/x86/amdfam17h/l3cache.json ___________________________________________________________________ Added: fbsd:nokeywords ## -0,0 +1 ## +yes \ No newline at end of property Index: head/lib/libpmc/pmu-events/jevents.c =================================================================== --- head/lib/libpmc/pmu-events/jevents.c (revision 340107) +++ head/lib/libpmc/pmu-events/jevents.c (revision 340108) @@ -1,1169 +1,1171 @@ #define _XOPEN_SOURCE 500 /* needed for nftw() */ #define __BSD_VISIBLE 1 /* needed for asprintf() */ /* Parse event JSON files */ /* * Copyright (c) 2014, Intel Corporation * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: * * 1. Redistributions of source code must retain the above copyright notice, * this list of conditions and the following disclaimer. * * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE * COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED * OF THE POSSIBILITY OF SUCH DAMAGE. * * $FreeBSD$ * */ #include #include #include #include #include #include #include #include #include #include #include #include /* getrlimit */ #include /* getrlimit */ #include #include #include "list.h" #include "jsmn.h" #include "json.h" #include "jevents.h" _Noreturn void _Exit(int); int verbose; static char *prog; int eprintf(int level, int var, const char *fmt, ...) { int ret; va_list args; if (var < level) return 0; va_start(args, fmt); ret = vfprintf(stderr, fmt, args); va_end(args); return ret; } __attribute__((weak)) char *get_cpu_str(void) { return NULL; } static void addfield(char *map, char **dst, const char *sep, const char *a, jsmntok_t *bt) { unsigned int len = strlen(a) + 1 + strlen(sep); int olen = *dst ? strlen(*dst) : 0; int blen = bt ? json_len(bt) : 0; char *out; out = realloc(*dst, len + olen + blen); if (!out) { /* Don't add field in this case */ return; } *dst = out; if (!olen) *(*dst) = 0; else strcat(*dst, sep); strcat(*dst, a); if (bt) strncat(*dst, map + bt->start, blen); } static void fixname(char *s) { for (; *s; s++) *s = tolower(*s); } static void fixdesc(char *s) { char *e = s + strlen(s); /* Remove trailing dots that look ugly in perf list */ --e; while (e >= s && isspace(*e)) --e; if (*e == '.') *e = 0; } /* Add escapes for '\' so they are proper C strings. */ static char *fixregex(char *s) { int len = 0; int esc_count = 0; char *fixed = NULL; char *p, *q; /* Count the number of '\' in string */ for (p = s; *p; p++) { ++len; if (*p == '\\') ++esc_count; } if (esc_count == 0) return s; /* allocate space for a new string */ fixed = (char *) malloc(len + 1); if (!fixed) return NULL; /* copy over the characters */ q = fixed; for (p = s; *p; p++) { if (*p == '\\') { *q = '\\'; ++q; } *q = *p; ++q; } *q = '\0'; return fixed; } static struct msrmap { const char *num; const char *pname; } msrmap[] = { { "0x3F6", "ldlat=" }, { "0x1A6", "offcore_rsp=" }, { "0x1A7", "offcore_rsp=" }, { "0x3F7", "frontend=" }, { NULL, NULL } }; static struct field { const char *field; const char *kernel; } fields[] = { { "UMask", "umask=" }, { "CounterMask", "cmask=" }, { "Invert", "inv=" }, { "AnyThread", "any=" }, { "EdgeDetect", "edge=" }, { "SampleAfterValue", "period=" }, { "FCMask", "fc_mask=" }, { "PortMask", "ch_mask=" }, + { "L3ThreadMask", "l3_thread_mask=" }, + { "L3SliceMask", "l3_slice_mask=" }, { NULL, NULL } }; static void cut_comma(char *map, jsmntok_t *newval) { int i; /* Cut off everything after comma */ for (i = newval->start; i < newval->end; i++) { if (map[i] == ',') newval->end = i; } } static int match_field(char *map, jsmntok_t *field, int nz, char **event, jsmntok_t *val) { struct field *f; jsmntok_t newval = *val; for (f = fields; f->field; f++) if (json_streq(map, field, f->field) && nz) { cut_comma(map, &newval); addfield(map, event, ",", f->kernel, &newval); return 1; } return 0; } static struct msrmap *lookup_msr(char *map, jsmntok_t *val) { jsmntok_t newval = *val; static bool warned; int i; cut_comma(map, &newval); for (i = 0; msrmap[i].num; i++) if (json_streq(map, &newval, msrmap[i].num)) return &msrmap[i]; if (!warned) { warned = true; pr_err("%s: Unknown MSR in event file %.*s\n", prog, json_len(val), map + val->start); } return NULL; } static struct map { const char *json; const char *perf; } unit_to_pmu[] = { { "CBO", "uncore_cbox" }, { "QPI LL", "uncore_qpi" }, { "SBO", "uncore_sbox" }, { "iMPH-U", "uncore_arb" }, {} }; static const char *field_to_perf(struct map *table, char *map, jsmntok_t *val) { int i; for (i = 0; table[i].json; i++) { if (json_streq(map, val, table[i].json)) return table[i].perf; } return NULL; } #define EXPECT(e, t, m) do { if (!(e)) { \ jsmntok_t *loc = (t); \ if (!(t)->start && (t) > tokens) \ loc = (t) - 1; \ pr_err("%s:%d: " m ", got %s\n", fn, \ json_line(map, loc), \ json_name(t)); \ err = -EIO; \ goto out_free; \ } } while (0) static char *topic; static char *get_topic(void) { char *tp; int i; /* tp is free'd in process_one_file() */ i = asprintf(&tp, "%s", topic); if (i < 0) { pr_info("%s: asprintf() error %s\n", prog); return NULL; } for (i = 0; i < (int) strlen(tp); i++) { char c = tp[i]; if (c == '-') tp[i] = ' '; else if (c == '.') { tp[i] = '\0'; break; } } return tp; } static int add_topic(const char *bname) { free(topic); topic = strdup(bname); if (!topic) { pr_info("%s: strdup() error %s for file %s\n", prog, strerror(errno), bname); return -ENOMEM; } return 0; } struct perf_entry_data { FILE *outfp; char *topic; }; static int close_table; static void print_events_table_prefix(FILE *fp, const char *tblname) { fprintf(fp, "static struct pmu_event %s[] = {\n", tblname); close_table = 1; } static int print_events_table_entry(void *data, char *name, const char *event, char *desc, char *long_desc, char *pmu, char *unit, char *perpkg, char *metric_expr, char *metric_name, char *metric_group) { struct perf_entry_data *pd = data; FILE *outfp = pd->outfp; char *etopic = pd->topic; /* * TODO: Remove formatting chars after debugging to reduce * string lengths. */ fprintf(outfp, "{\n"); if (name) fprintf(outfp, "\t.name = \"%s\",\n", name); if (event) fprintf(outfp, "\t.event = \"%s\",\n", event); fprintf(outfp, "\t.desc = \"%s\",\n", desc); fprintf(outfp, "\t.topic = \"%s\",\n", etopic); if (long_desc && long_desc[0]) fprintf(outfp, "\t.long_desc = \"%s\",\n", long_desc); if (pmu) fprintf(outfp, "\t.pmu = \"%s\",\n", pmu); if (unit) fprintf(outfp, "\t.unit = \"%s\",\n", unit); if (perpkg) fprintf(outfp, "\t.perpkg = \"%s\",\n", perpkg); if (metric_expr) fprintf(outfp, "\t.metric_expr = \"%s\",\n", metric_expr); if (metric_name) fprintf(outfp, "\t.metric_name = \"%s\",\n", metric_name); if (metric_group) fprintf(outfp, "\t.metric_group = \"%s\",\n", metric_group); fprintf(outfp, "},\n"); return 0; } struct event_struct { struct list_head list; char *name; char *event; char *desc; char *long_desc; char *pmu; char *unit; char *perpkg; char *metric_expr; char *metric_name; char *metric_group; }; #define ADD_EVENT_FIELD(field) do { if (field) { \ es->field = strdup(field); \ if (!es->field) \ goto out_free; \ } } while (0) #define FREE_EVENT_FIELD(field) free(es->field) #define TRY_FIXUP_FIELD(field) do { if (es->field && !*field) {\ *field = strdup(es->field); \ if (!*field) \ return -ENOMEM; \ } } while (0) #define FOR_ALL_EVENT_STRUCT_FIELDS(op) do { \ op(name); \ op(event); \ op(desc); \ op(long_desc); \ op(pmu); \ op(unit); \ op(perpkg); \ op(metric_expr); \ op(metric_name); \ op(metric_group); \ } while (0) static LIST_HEAD(arch_std_events); static void free_arch_std_events(void) { struct event_struct *es, *next; list_for_each_entry_safe(es, next, &arch_std_events, list) { FOR_ALL_EVENT_STRUCT_FIELDS(FREE_EVENT_FIELD); list_del(&es->list); free(es); } } static int save_arch_std_events(void *data __unused, char *name, const char *event, char *desc, char *long_desc, char *pmu, char *unit, char *perpkg, char *metric_expr, char *metric_name, char *metric_group) { struct event_struct *es; es = malloc(sizeof(*es)); if (!es) return -ENOMEM; memset(es, 0, sizeof(*es)); FOR_ALL_EVENT_STRUCT_FIELDS(ADD_EVENT_FIELD); list_add_tail(&es->list, &arch_std_events); return 0; out_free: FOR_ALL_EVENT_STRUCT_FIELDS(FREE_EVENT_FIELD); free(es); return -ENOMEM; } static void print_events_table_suffix(FILE *outfp) { fprintf(outfp, "{\n"); fprintf(outfp, "\t.name = 0,\n"); fprintf(outfp, "\t.event = 0,\n"); fprintf(outfp, "\t.desc = 0,\n"); fprintf(outfp, "},\n"); fprintf(outfp, "};\n"); close_table = 0; } static struct fixed { const char *name; const char *event; } fixed[] = { { "inst_retired.any", "event=0xc0" }, { "inst_retired.any_p", "event=0xc0" }, { "cpu_clk_unhalted.ref", "event=0x0,umask=0x03" }, { "cpu_clk_unhalted.thread", "event=0x3c" }, { "cpu_clk_unhalted.thread_any", "event=0x3c,any=1" }, { NULL, NULL}, }; /* * Handle different fixed counter encodings between JSON and perf. */ static const char *real_event(const char *name, char *event) { int i; if (!name) return NULL; for (i = 0; fixed[i].name; i++) if (!strcasecmp(name, fixed[i].name)) return fixed[i].event; return event; } static int try_fixup(const char *fn, char *arch_std, char **event, char **desc, char **name, char **long_desc, char **pmu, char **filter __unused, char **perpkg, char **unit, char **metric_expr, char **metric_name, char **metric_group, unsigned long long eventcode) { /* try to find matching event from arch standard values */ struct event_struct *es; list_for_each_entry(es, &arch_std_events, list) { if (!strcmp(arch_std, es->name)) { if (!eventcode && es->event) { /* allow EventCode to be overridden */ free(*event); *event = NULL; } FOR_ALL_EVENT_STRUCT_FIELDS(TRY_FIXUP_FIELD); return 0; } } pr_err("%s: could not find matching %s for %s\n", prog, arch_std, fn); return -1; } /* Call func with each event in the json file */ int json_events(const char *fn, int (*func)(void *data, char *name, const char *event, char *desc, char *long_desc, char *pmu, char *unit, char *perpkg, char *metric_expr, char *metric_name, char *metric_group), void *data) { int err; size_t size; jsmntok_t *tokens, *tok; int i, j, len; char *map; char buf[128]; if (!fn) return -ENOENT; tokens = parse_json(fn, &map, &size, &len); if (!tokens) return -EIO; EXPECT(tokens->type == JSMN_ARRAY, tokens, "expected top level array"); tok = tokens + 1; for (i = 0; i < tokens->size; i++) { char *event = NULL, *desc = NULL, *name = NULL; char *long_desc = NULL; char *extra_desc = NULL; char *pmu = NULL; char *filter = NULL; char *perpkg = NULL; char *unit = NULL; char *metric_expr = NULL; char *metric_name = NULL; char *metric_group = NULL; char *arch_std = NULL; unsigned long long eventcode = 0; struct msrmap *msr = NULL; jsmntok_t *msrval = NULL; jsmntok_t *precise = NULL; jsmntok_t *obj = tok++; EXPECT(obj->type == JSMN_OBJECT, obj, "expected object"); for (j = 0; j < obj->size; j += 2) { jsmntok_t *field, *val; int nz; char *s; field = tok + j; EXPECT(field->type == JSMN_STRING, tok + j, "Expected field name"); val = tok + j + 1; EXPECT(val->type == JSMN_STRING, tok + j + 1, "Expected string value"); nz = !json_streq(map, val, "0"); if (match_field(map, field, nz, &event, val)) { /* ok */ } else if (json_streq(map, field, "EventCode")) { char *code = NULL; addfield(map, &code, "", "", val); eventcode |= strtoul(code, NULL, 0); free(code); } else if (json_streq(map, field, "ExtSel")) { char *code = NULL; addfield(map, &code, "", "", val); eventcode |= strtoul(code, NULL, 0) << 21; free(code); } else if (json_streq(map, field, "EventName")) { addfield(map, &name, "", "", val); } else if (json_streq(map, field, "BriefDescription")) { addfield(map, &desc, "", "", val); fixdesc(desc); } else if (json_streq(map, field, "PublicDescription")) { addfield(map, &long_desc, "", "", val); fixdesc(long_desc); } else if (json_streq(map, field, "PEBS") && nz) { precise = val; } else if (json_streq(map, field, "MSRIndex") && nz) { msr = lookup_msr(map, val); } else if (json_streq(map, field, "MSRValue")) { msrval = val; } else if (json_streq(map, field, "Errata") && !json_streq(map, val, "null")) { addfield(map, &extra_desc, ". ", " Spec update: ", val); } else if (json_streq(map, field, "Data_LA") && nz) { addfield(map, &extra_desc, ". ", " Supports address when precise", NULL); } else if (json_streq(map, field, "Unit")) { const char *ppmu; ppmu = field_to_perf(unit_to_pmu, map, val); if (ppmu) { pmu = strdup(ppmu); } else { if (!pmu) pmu = strdup("uncore_"); addfield(map, &pmu, "", "", val); for (s = pmu; *s; s++) *s = tolower(*s); } addfield(map, &desc, ". ", "Unit: ", NULL); addfield(map, &desc, "", pmu, NULL); addfield(map, &desc, "", " ", NULL); } else if (json_streq(map, field, "Filter")) { addfield(map, &filter, "", "", val); } else if (json_streq(map, field, "ScaleUnit")) { addfield(map, &unit, "", "", val); } else if (json_streq(map, field, "PerPkg")) { addfield(map, &perpkg, "", "", val); } else if (json_streq(map, field, "MetricName")) { addfield(map, &metric_name, "", "", val); } else if (json_streq(map, field, "MetricGroup")) { addfield(map, &metric_group, "", "", val); } else if (json_streq(map, field, "MetricExpr")) { addfield(map, &metric_expr, "", "", val); for (s = metric_expr; *s; s++) *s = tolower(*s); } else if (json_streq(map, field, "ArchStdEvent")) { addfield(map, &arch_std, "", "", val); for (s = arch_std; *s; s++) *s = tolower(*s); } /* ignore unknown fields */ } if (precise && desc && !strstr(desc, "(Precise Event)")) { if (json_streq(map, precise, "2")) addfield(map, &extra_desc, " ", "(Must be precise)", NULL); else addfield(map, &extra_desc, " ", "(Precise event)", NULL); } snprintf(buf, sizeof buf, "event=%#llx", eventcode); addfield(map, &event, ",", buf, NULL); if (desc && extra_desc) addfield(map, &desc, " ", extra_desc, NULL); if (long_desc && extra_desc) addfield(map, &long_desc, " ", extra_desc, NULL); if (filter) addfield(map, &event, ",", filter, NULL); if (msr != NULL) addfield(map, &event, ",", msr->pname, msrval); if (name) fixname(name); if (arch_std) { /* * An arch standard event is referenced, so try to * fixup any unassigned values. */ err = try_fixup(fn, arch_std, &event, &desc, &name, &long_desc, &pmu, &filter, &perpkg, &unit, &metric_expr, &metric_name, &metric_group, eventcode); if (err) goto free_strings; } err = func(data, name, real_event(name, event), desc, long_desc, pmu, unit, perpkg, metric_expr, metric_name, metric_group); free_strings: free(event); free(desc); free(name); free(long_desc); free(extra_desc); free(pmu); free(filter); free(perpkg); free(unit); free(metric_expr); free(metric_name); free(metric_group); free(arch_std); if (err) break; tok += j; } EXPECT(tok - tokens == len, tok, "unexpected objects at end"); err = 0; out_free: free_json(map, size, tokens); return err; } static char *file_name_to_table_name(const char *fname) { unsigned int i; int n; int c; char *tblname; /* * Ensure tablename starts with alphabetic character. * Derive rest of table name from basename of the JSON file, * replacing hyphens and stripping out .json suffix. */ n = asprintf(&tblname, "pme_%s", fname); if (n < 0) { pr_info("%s: asprintf() error %s for file %s\n", prog, strerror(errno), fname); return NULL; } for (i = 0; i < strlen(tblname); i++) { c = tblname[i]; if (c == '-' || c == '/') tblname[i] = '_'; else if (c == '.') { tblname[i] = '\0'; break; } else if (!isalnum(c) && c != '_') { char *tmp = strdup(fname); pr_err("%s: Invalid character '%c' in file name %s\n", prog, c, basename(tmp)); free(tblname); free(tmp); tblname = NULL; break; } } return tblname; } static void print_mapping_table_prefix(FILE *outfp) { fprintf(outfp, "struct pmu_events_map pmu_events_map[] = {\n"); } static void print_mapping_table_suffix(FILE *outfp) { /* * Print the terminating, NULL entry. */ fprintf(outfp, "{\n"); fprintf(outfp, "\t.cpuid = 0,\n"); fprintf(outfp, "\t.version = 0,\n"); fprintf(outfp, "\t.type = 0,\n"); fprintf(outfp, "\t.table = 0,\n"); fprintf(outfp, "},\n"); /* and finally, the closing curly bracket for the struct */ fprintf(outfp, "};\n"); } static int process_mapfile(FILE *outfp, char *fpath) { int n = 16384; FILE *mapfp; char *save = NULL; char *line, *p; int line_num; char *tblname; pr_info("%s: Processing mapfile %s\n", prog, fpath); line = malloc(n); if (!line) return -1; mapfp = fopen(fpath, "r"); if (!mapfp) { pr_info("%s: Error %s opening %s\n", prog, strerror(errno), fpath); return -1; } print_mapping_table_prefix(outfp); /* Skip first line (header) */ p = fgets(line, n, mapfp); if (!p) goto out; line_num = 1; while (1) { char *cpuid, *version, *type, *fname; line_num++; p = fgets(line, n, mapfp); if (!p) break; if (line[0] == '#' || line[0] == '\n') continue; if (line[strlen(line)-1] != '\n') { /* TODO Deal with lines longer than 16K */ pr_info("%s: Mapfile %s: line %d too long, aborting\n", prog, fpath, line_num); return -1; } line[strlen(line)-1] = '\0'; cpuid = fixregex(strtok_r(p, ",", &save)); version = strtok_r(NULL, ",", &save); fname = strtok_r(NULL, ",", &save); type = strtok_r(NULL, ",", &save); tblname = file_name_to_table_name(fname); fprintf(outfp, "{\n"); fprintf(outfp, "\t.cpuid = \"%s\",\n", cpuid); fprintf(outfp, "\t.version = \"%s\",\n", version); fprintf(outfp, "\t.type = \"%s\",\n", type); /* * CHECK: We can't use the type (eg "core") field in the * table name. For us to do that, we need to somehow tweak * the other caller of file_name_to_table(), process_json() * to determine the type. process_json() file has no way * of knowing these are "core" events unless file name has * core in it. If filename has core in it, we can safely * ignore the type field here also. */ fprintf(outfp, "\t.table = %s\n", tblname); fprintf(outfp, "},\n"); } out: print_mapping_table_suffix(outfp); return 0; } /* * If we fail to locate/process JSON and map files, create a NULL mapping * table. This would at least allow perf to build even if we can't find/use * the aliases. */ static void create_empty_mapping(const char *output_file) { FILE *outfp; pr_info("%s: Creating empty pmu_events_map[] table\n", prog); /* Truncate file to clear any partial writes to it */ outfp = fopen(output_file, "w"); if (!outfp) { perror("fopen()"); _Exit(1); } fprintf(outfp, "#include \"pmu-events/pmu-events.h\"\n"); print_mapping_table_prefix(outfp); print_mapping_table_suffix(outfp); fclose(outfp); } static int get_maxfds(void) { struct rlimit rlim; if (getrlimit(RLIMIT_NOFILE, &rlim) == 0) { if (rlim.rlim_max == RLIM_INFINITY) return 512; return min((unsigned)rlim.rlim_max / 2, 512); } return 512; } /* * nftw() doesn't let us pass an argument to the processing function, * so use a global variables. */ static FILE *eventsfp; static char *mapfile; static int is_leaf_dir(const char *fpath) { DIR *d; struct dirent *dir; int res = 1; d = opendir(fpath); if (!d) return 0; while ((dir = readdir(d)) != NULL) { if (!strcmp(dir->d_name, ".") || !strcmp(dir->d_name, "..")) continue; if (dir->d_type == DT_DIR) { res = 0; break; } else if (dir->d_type == DT_UNKNOWN) { char path[PATH_MAX]; struct stat st; sprintf(path, "%s/%s", fpath, dir->d_name); if (stat(path, &st)) break; if (S_ISDIR(st.st_mode)) { res = 0; break; } } } closedir(d); return res; } static int is_json_file(const char *name) { const char *suffix; if (strlen(name) < 5) return 0; suffix = name + strlen(name) - 5; if (strncmp(suffix, ".json", 5) == 0) return 1; return 0; } static int preprocess_arch_std_files(const char *fpath, const struct stat *sb, int typeflag, struct FTW *ftwbuf) { int level = ftwbuf->level; int is_file = typeflag == FTW_F; if (level == 1 && is_file && is_json_file(fpath)) return json_events(fpath, save_arch_std_events, (void *)(uintptr_t)sb); return 0; } static int process_one_file(const char *fpath, const struct stat *sb, int typeflag, struct FTW *ftwbuf) { char *tblname; const char *bname; int is_dir = typeflag == FTW_D; int is_file = typeflag == FTW_F; int level = ftwbuf->level; int err = 0; if (level == 2 && is_dir) { /* * For level 2 directory, bname will include parent name, * like vendor/platform. So search back from platform dir * to find this. */ bname = fpath + ftwbuf->base - 2; for (;;) { if (*bname == '/') break; bname--; } bname++; } else bname = fpath + ftwbuf->base; pr_debug("%s %d %7jd %-20s %s\n", is_file ? "f" : is_dir ? "d" : "x", level, sb->st_size, bname, fpath); /* base dir or too deep */ if (level == 0 || level > 3) return 0; /* model directory, reset topic */ if ((level == 1 && is_dir && is_leaf_dir(fpath)) || (level == 2 && is_dir)) { if (close_table) print_events_table_suffix(eventsfp); /* * Drop file name suffix. Replace hyphens with underscores. * Fail if file name contains any alphanum characters besides * underscores. */ tblname = file_name_to_table_name(bname); if (!tblname) { pr_info("%s: Error determining table name for %s\n", prog, bname); return -1; } print_events_table_prefix(eventsfp, tblname); return 0; } /* * Save the mapfile name for now. We will process mapfile * after processing all JSON files (so we can write out the * mapping table after all PMU events tables). * */ if (level == 1 && is_file) { if (!strcmp(bname, "mapfile.csv")) { mapfile = strdup(fpath); return 0; } pr_info("%s: Ignoring file %s\n", prog, fpath); return 0; } /* * If the file name does not have a .json extension, * ignore it. It could be a readme.txt for instance. */ if (is_file) { if (!is_json_file(bname)) { pr_info("%s: Ignoring file without .json suffix %s\n", prog, fpath); return 0; } } if (level > 1 && add_topic(bname)) return -ENOMEM; /* * Assume all other files are JSON files. * * If mapfile refers to 'power7_core.json', we create a table * named 'power7_core'. Any inconsistencies between the mapfile * and directory tree could result in build failure due to table * names not being found. * * Atleast for now, be strict with processing JSON file names. * i.e. if JSON file name cannot be mapped to C-style table name, * fail. */ if (is_file) { struct perf_entry_data data = { .topic = get_topic(), .outfp = eventsfp, }; err = json_events(fpath, print_events_table_entry, &data); free(data.topic); } return err; } #ifndef PATH_MAX #define PATH_MAX 4096 #endif /* * Starting in directory 'start_dirname', find the "mapfile.csv" and * the set of JSON files for the architecture 'arch'. * * From each JSON file, create a C-style "PMU events table" from the * JSON file (see struct pmu_event). * * From the mapfile, create a mapping between the CPU revisions and * PMU event tables (see struct pmu_events_map). * * Write out the PMU events tables and the mapping table to pmu-event.c. */ int main(int argc, char *argv[]) { int rc; int maxfds; char ldirname[PATH_MAX]; const char *arch; const char *output_file; const char *start_dirname; struct stat stbuf; prog = basename(argv[0]); if (argc < 4) { pr_err("Usage: %s \n", prog); return 1; } arch = argv[1]; start_dirname = argv[2]; output_file = argv[3]; if (argc > 4) verbose = atoi(argv[4]); eventsfp = fopen(output_file, "w"); if (!eventsfp) { pr_err("%s Unable to create required file %s (%s)\n", prog, output_file, strerror(errno)); return 2; } sprintf(ldirname, "%s/%s", start_dirname, arch); /* If architecture does not have any event lists, bail out */ if (stat(ldirname, &stbuf) < 0) { pr_info("%s: Arch %s has no PMU event lists\n", prog, arch); goto empty_map; } /* Include pmu-events.h first */ fprintf(eventsfp, "#include \"pmu-events/pmu-events.h\"\n"); /* * The mapfile allows multiple CPUids to point to the same JSON file, * so, not sure if there is a need for symlinks within the pmu-events * directory. * * For now, treat symlinks of JSON files as regular files and create * separate tables for each symlink (presumably, each symlink refers * to specific version of the CPU). */ maxfds = get_maxfds(); mapfile = NULL; rc = nftw(ldirname, preprocess_arch_std_files, maxfds, 0); if (rc && verbose) { pr_info("%s: Error preprocessing arch standard files %s: %s\n", prog, ldirname, strerror(errno)); goto empty_map; } else if (rc < 0) { /* Make build fail */ free_arch_std_events(); return 1; } else if (rc) { goto empty_map; } rc = nftw(ldirname, process_one_file, maxfds, 0); if (rc && verbose) { pr_info("%s: Error walking file tree %s\n", prog, ldirname); goto empty_map; } else if (rc < 0) { /* Make build fail */ free_arch_std_events(); return 1; } else if (rc) { goto empty_map; } if (close_table) print_events_table_suffix(eventsfp); if (!mapfile) { pr_info("%s: No CPU->JSON mapping?\n", prog); goto empty_map; } if (process_mapfile(eventsfp, mapfile)) { pr_info("%s: Error processing mapfile %s\n", prog, mapfile); /* Make build fail */ return 1; } return 0; empty_map: fclose(eventsfp); create_empty_mapping(output_file); free_arch_std_events(); return 0; } Index: head/sys/dev/hwpmc/hwpmc_amd.c =================================================================== --- head/sys/dev/hwpmc/hwpmc_amd.c (revision 340107) +++ head/sys/dev/hwpmc/hwpmc_amd.c (revision 340108) @@ -1,1049 +1,1188 @@ /*- * SPDX-License-Identifier: BSD-2-Clause-FreeBSD * * Copyright (c) 2003-2008 Joseph Koshy * Copyright (c) 2007 The FreeBSD Foundation * All rights reserved. * * Portions of this software were developed by A. Joseph Koshy under * sponsorship from the FreeBSD Foundation and Google, Inc. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. */ #include __FBSDID("$FreeBSD$"); /* Support for the AMD K7 and later processors */ #include #include #include #include #include #include #include #include #include #include #include #include #ifdef HWPMC_DEBUG enum pmc_class amd_pmc_class; #endif /* AMD K7 & K8 PMCs */ struct amd_descr { struct pmc_descr pm_descr; /* "base class" */ uint32_t pm_evsel; /* address of EVSEL register */ uint32_t pm_perfctr; /* address of PERFCTR register */ }; static struct amd_descr amd_pmcdesc[AMD_NPMCS] = { { .pm_descr = { .pd_name = "", .pd_class = -1, .pd_caps = AMD_PMC_CAPS, .pd_width = 48 }, .pm_evsel = AMD_PMC_EVSEL_0, .pm_perfctr = AMD_PMC_PERFCTR_0 }, { .pm_descr = { .pd_name = "", .pd_class = -1, .pd_caps = AMD_PMC_CAPS, .pd_width = 48 }, .pm_evsel = AMD_PMC_EVSEL_1, .pm_perfctr = AMD_PMC_PERFCTR_1 }, { .pm_descr = { .pd_name = "", .pd_class = -1, .pd_caps = AMD_PMC_CAPS, .pd_width = 48 }, .pm_evsel = AMD_PMC_EVSEL_2, .pm_perfctr = AMD_PMC_PERFCTR_2 }, { .pm_descr = { .pd_name = "", .pd_class = -1, .pd_caps = AMD_PMC_CAPS, .pd_width = 48 }, .pm_evsel = AMD_PMC_EVSEL_3, .pm_perfctr = AMD_PMC_PERFCTR_3 - } + }, + { + .pm_descr = + { + .pd_name = "", + .pd_class = -1, + .pd_caps = AMD_PMC_CAPS, + .pd_width = 48 + }, + .pm_evsel = AMD_PMC_EVSEL_4, + .pm_perfctr = AMD_PMC_PERFCTR_4 + }, + { + .pm_descr = + { + .pd_name = "", + .pd_class = -1, + .pd_caps = AMD_PMC_CAPS, + .pd_width = 48 + }, + .pm_evsel = AMD_PMC_EVSEL_5, + .pm_perfctr = AMD_PMC_PERFCTR_5 + }, + { + .pm_descr = + { + .pd_name = "", + .pd_class = -1, + .pd_caps = AMD_PMC_CAPS, + .pd_width = 48 + }, + .pm_evsel = AMD_PMC_EVSEL_EP_L3_0, + .pm_perfctr = AMD_PMC_PERFCTR_EP_L3_0 + }, + { + .pm_descr = + { + .pd_name = "", + .pd_class = -1, + .pd_caps = AMD_PMC_CAPS, + .pd_width = 48 + }, + .pm_evsel = AMD_PMC_EVSEL_EP_L3_1, + .pm_perfctr = AMD_PMC_PERFCTR_EP_L3_1 + }, + { + .pm_descr = + { + .pd_name = "", + .pd_class = -1, + .pd_caps = AMD_PMC_CAPS, + .pd_width = 48 + }, + .pm_evsel = AMD_PMC_EVSEL_EP_L3_2, + .pm_perfctr = AMD_PMC_PERFCTR_EP_L3_2 + }, + { + .pm_descr = + { + .pd_name = "", + .pd_class = -1, + .pd_caps = AMD_PMC_CAPS, + .pd_width = 48 + }, + .pm_evsel = AMD_PMC_EVSEL_EP_L3_3, + .pm_perfctr = AMD_PMC_PERFCTR_EP_L3_3 + }, + { + .pm_descr = + { + .pd_name = "", + .pd_class = -1, + .pd_caps = AMD_PMC_CAPS, + .pd_width = 48 + }, + .pm_evsel = AMD_PMC_EVSEL_EP_L3_4, + .pm_perfctr = AMD_PMC_PERFCTR_EP_L3_4 + }, + { + .pm_descr = + { + .pd_name = "", + .pd_class = -1, + .pd_caps = AMD_PMC_CAPS, + .pd_width = 48 + }, + .pm_evsel = AMD_PMC_EVSEL_EP_L3_5, + .pm_perfctr = AMD_PMC_PERFCTR_EP_L3_5 + }, + { + .pm_descr = + { + .pd_name = "", + .pd_class = -1, + .pd_caps = AMD_PMC_CAPS, + .pd_width = 48 + }, + .pm_evsel = AMD_PMC_EVSEL_EP_DF_0, + .pm_perfctr = AMD_PMC_PERFCTR_EP_DF_0 + }, + { + .pm_descr = + { + .pd_name = "", + .pd_class = -1, + .pd_caps = AMD_PMC_CAPS, + .pd_width = 48 + }, + .pm_evsel = AMD_PMC_EVSEL_EP_DF_1, + .pm_perfctr = AMD_PMC_PERFCTR_EP_DF_1 + }, + { + .pm_descr = + { + .pd_name = "", + .pd_class = -1, + .pd_caps = AMD_PMC_CAPS, + .pd_width = 48 + }, + .pm_evsel = AMD_PMC_EVSEL_EP_DF_2, + .pm_perfctr = AMD_PMC_PERFCTR_EP_DF_2 + }, + { + .pm_descr = + { + .pd_name = "", + .pd_class = -1, + .pd_caps = AMD_PMC_CAPS, + .pd_width = 48 + }, + .pm_evsel = AMD_PMC_EVSEL_EP_DF_3, + .pm_perfctr = AMD_PMC_PERFCTR_EP_DF_3 + } }; struct amd_event_code_map { enum pmc_event pe_ev; /* enum value */ uint16_t pe_code; /* encoded event mask */ uint8_t pe_mask; /* bits allowed in unit mask */ }; const struct amd_event_code_map amd_event_codes[] = { #if defined(__i386__) /* 32 bit Athlon (K7) only */ { PMC_EV_K7_DC_ACCESSES, 0x40, 0 }, { PMC_EV_K7_DC_MISSES, 0x41, 0 }, { PMC_EV_K7_DC_REFILLS_FROM_L2, 0x42, AMD_PMC_UNITMASK_MOESI }, { PMC_EV_K7_DC_REFILLS_FROM_SYSTEM, 0x43, AMD_PMC_UNITMASK_MOESI }, { PMC_EV_K7_DC_WRITEBACKS, 0x44, AMD_PMC_UNITMASK_MOESI }, { PMC_EV_K7_L1_DTLB_MISS_AND_L2_DTLB_HITS, 0x45, 0 }, { PMC_EV_K7_L1_AND_L2_DTLB_MISSES, 0x46, 0 }, { PMC_EV_K7_MISALIGNED_REFERENCES, 0x47, 0 }, { PMC_EV_K7_IC_FETCHES, 0x80, 0 }, { PMC_EV_K7_IC_MISSES, 0x81, 0 }, { PMC_EV_K7_L1_ITLB_MISSES, 0x84, 0 }, { PMC_EV_K7_L1_L2_ITLB_MISSES, 0x85, 0 }, { PMC_EV_K7_RETIRED_INSTRUCTIONS, 0xC0, 0 }, { PMC_EV_K7_RETIRED_OPS, 0xC1, 0 }, { PMC_EV_K7_RETIRED_BRANCHES, 0xC2, 0 }, { PMC_EV_K7_RETIRED_BRANCHES_MISPREDICTED, 0xC3, 0 }, { PMC_EV_K7_RETIRED_TAKEN_BRANCHES, 0xC4, 0 }, { PMC_EV_K7_RETIRED_TAKEN_BRANCHES_MISPREDICTED, 0xC5, 0 }, { PMC_EV_K7_RETIRED_FAR_CONTROL_TRANSFERS, 0xC6, 0 }, { PMC_EV_K7_RETIRED_RESYNC_BRANCHES, 0xC7, 0 }, { PMC_EV_K7_INTERRUPTS_MASKED_CYCLES, 0xCD, 0 }, { PMC_EV_K7_INTERRUPTS_MASKED_WHILE_PENDING_CYCLES, 0xCE, 0 }, { PMC_EV_K7_HARDWARE_INTERRUPTS, 0xCF, 0 }, #endif { PMC_EV_K8_FP_DISPATCHED_FPU_OPS, 0x00, 0x3F }, { PMC_EV_K8_FP_CYCLES_WITH_NO_FPU_OPS_RETIRED, 0x01, 0x00 }, { PMC_EV_K8_FP_DISPATCHED_FPU_FAST_FLAG_OPS, 0x02, 0x00 }, { PMC_EV_K8_LS_SEGMENT_REGISTER_LOAD, 0x20, 0x7F }, { PMC_EV_K8_LS_MICROARCHITECTURAL_RESYNC_BY_SELF_MODIFYING_CODE, 0x21, 0x00 }, { PMC_EV_K8_LS_MICROARCHITECTURAL_RESYNC_BY_SNOOP, 0x22, 0x00 }, { PMC_EV_K8_LS_BUFFER2_FULL, 0x23, 0x00 }, { PMC_EV_K8_LS_LOCKED_OPERATION, 0x24, 0x07 }, { PMC_EV_K8_LS_MICROARCHITECTURAL_LATE_CANCEL, 0x25, 0x00 }, { PMC_EV_K8_LS_RETIRED_CFLUSH_INSTRUCTIONS, 0x26, 0x00 }, { PMC_EV_K8_LS_RETIRED_CPUID_INSTRUCTIONS, 0x27, 0x00 }, { PMC_EV_K8_DC_ACCESS, 0x40, 0x00 }, { PMC_EV_K8_DC_MISS, 0x41, 0x00 }, { PMC_EV_K8_DC_REFILL_FROM_L2, 0x42, 0x1F }, { PMC_EV_K8_DC_REFILL_FROM_SYSTEM, 0x43, 0x1F }, { PMC_EV_K8_DC_COPYBACK, 0x44, 0x1F }, { PMC_EV_K8_DC_L1_DTLB_MISS_AND_L2_DTLB_HIT, 0x45, 0x00 }, { PMC_EV_K8_DC_L1_DTLB_MISS_AND_L2_DTLB_MISS, 0x46, 0x00 }, { PMC_EV_K8_DC_MISALIGNED_DATA_REFERENCE, 0x47, 0x00 }, { PMC_EV_K8_DC_MICROARCHITECTURAL_LATE_CANCEL, 0x48, 0x00 }, { PMC_EV_K8_DC_MICROARCHITECTURAL_EARLY_CANCEL, 0x49, 0x00 }, { PMC_EV_K8_DC_ONE_BIT_ECC_ERROR, 0x4A, 0x03 }, { PMC_EV_K8_DC_DISPATCHED_PREFETCH_INSTRUCTIONS, 0x4B, 0x07 }, { PMC_EV_K8_DC_DCACHE_ACCESSES_BY_LOCKS, 0x4C, 0x03 }, { PMC_EV_K8_BU_CPU_CLK_UNHALTED, 0x76, 0x00 }, { PMC_EV_K8_BU_INTERNAL_L2_REQUEST, 0x7D, 0x1F }, { PMC_EV_K8_BU_FILL_REQUEST_L2_MISS, 0x7E, 0x07 }, { PMC_EV_K8_BU_FILL_INTO_L2, 0x7F, 0x03 }, { PMC_EV_K8_IC_FETCH, 0x80, 0x00 }, { PMC_EV_K8_IC_MISS, 0x81, 0x00 }, { PMC_EV_K8_IC_REFILL_FROM_L2, 0x82, 0x00 }, { PMC_EV_K8_IC_REFILL_FROM_SYSTEM, 0x83, 0x00 }, { PMC_EV_K8_IC_L1_ITLB_MISS_AND_L2_ITLB_HIT, 0x84, 0x00 }, { PMC_EV_K8_IC_L1_ITLB_MISS_AND_L2_ITLB_MISS, 0x85, 0x00 }, { PMC_EV_K8_IC_MICROARCHITECTURAL_RESYNC_BY_SNOOP, 0x86, 0x00 }, { PMC_EV_K8_IC_INSTRUCTION_FETCH_STALL, 0x87, 0x00 }, { PMC_EV_K8_IC_RETURN_STACK_HIT, 0x88, 0x00 }, { PMC_EV_K8_IC_RETURN_STACK_OVERFLOW, 0x89, 0x00 }, { PMC_EV_K8_FR_RETIRED_X86_INSTRUCTIONS, 0xC0, 0x00 }, { PMC_EV_K8_FR_RETIRED_UOPS, 0xC1, 0x00 }, { PMC_EV_K8_FR_RETIRED_BRANCHES, 0xC2, 0x00 }, { PMC_EV_K8_FR_RETIRED_BRANCHES_MISPREDICTED, 0xC3, 0x00 }, { PMC_EV_K8_FR_RETIRED_TAKEN_BRANCHES, 0xC4, 0x00 }, { PMC_EV_K8_FR_RETIRED_TAKEN_BRANCHES_MISPREDICTED, 0xC5, 0x00 }, { PMC_EV_K8_FR_RETIRED_FAR_CONTROL_TRANSFERS, 0xC6, 0x00 }, { PMC_EV_K8_FR_RETIRED_RESYNCS, 0xC7, 0x00 }, { PMC_EV_K8_FR_RETIRED_NEAR_RETURNS, 0xC8, 0x00 }, { PMC_EV_K8_FR_RETIRED_NEAR_RETURNS_MISPREDICTED, 0xC9, 0x00 }, { PMC_EV_K8_FR_RETIRED_TAKEN_BRANCHES_MISPREDICTED_BY_ADDR_MISCOMPARE, 0xCA, 0x00 }, { PMC_EV_K8_FR_RETIRED_FPU_INSTRUCTIONS, 0xCB, 0x0F }, { PMC_EV_K8_FR_RETIRED_FASTPATH_DOUBLE_OP_INSTRUCTIONS, 0xCC, 0x07 }, { PMC_EV_K8_FR_INTERRUPTS_MASKED_CYCLES, 0xCD, 0x00 }, { PMC_EV_K8_FR_INTERRUPTS_MASKED_WHILE_PENDING_CYCLES, 0xCE, 0x00 }, { PMC_EV_K8_FR_TAKEN_HARDWARE_INTERRUPTS, 0xCF, 0x00 }, { PMC_EV_K8_FR_DECODER_EMPTY, 0xD0, 0x00 }, { PMC_EV_K8_FR_DISPATCH_STALLS, 0xD1, 0x00 }, { PMC_EV_K8_FR_DISPATCH_STALL_FROM_BRANCH_ABORT_TO_RETIRE, 0xD2, 0x00 }, { PMC_EV_K8_FR_DISPATCH_STALL_FOR_SERIALIZATION, 0xD3, 0x00 }, { PMC_EV_K8_FR_DISPATCH_STALL_FOR_SEGMENT_LOAD, 0xD4, 0x00 }, { PMC_EV_K8_FR_DISPATCH_STALL_WHEN_REORDER_BUFFER_IS_FULL, 0xD5, 0x00 }, { PMC_EV_K8_FR_DISPATCH_STALL_WHEN_RESERVATION_STATIONS_ARE_FULL, 0xD6, 0x00 }, { PMC_EV_K8_FR_DISPATCH_STALL_WHEN_FPU_IS_FULL, 0xD7, 0x00 }, { PMC_EV_K8_FR_DISPATCH_STALL_WHEN_LS_IS_FULL, 0xD8, 0x00 }, { PMC_EV_K8_FR_DISPATCH_STALL_WHEN_WAITING_FOR_ALL_TO_BE_QUIET, 0xD9, 0x00 }, { PMC_EV_K8_FR_DISPATCH_STALL_WHEN_FAR_XFER_OR_RESYNC_BRANCH_PENDING, 0xDA, 0x00 }, { PMC_EV_K8_FR_FPU_EXCEPTIONS, 0xDB, 0x0F }, { PMC_EV_K8_FR_NUMBER_OF_BREAKPOINTS_FOR_DR0, 0xDC, 0x00 }, { PMC_EV_K8_FR_NUMBER_OF_BREAKPOINTS_FOR_DR1, 0xDD, 0x00 }, { PMC_EV_K8_FR_NUMBER_OF_BREAKPOINTS_FOR_DR2, 0xDE, 0x00 }, { PMC_EV_K8_FR_NUMBER_OF_BREAKPOINTS_FOR_DR3, 0xDF, 0x00 }, { PMC_EV_K8_NB_MEMORY_CONTROLLER_PAGE_ACCESS_EVENT, 0xE0, 0x7 }, { PMC_EV_K8_NB_MEMORY_CONTROLLER_PAGE_TABLE_OVERFLOW, 0xE1, 0x00 }, { PMC_EV_K8_NB_MEMORY_CONTROLLER_DRAM_COMMAND_SLOTS_MISSED, 0xE2, 0x00 }, { PMC_EV_K8_NB_MEMORY_CONTROLLER_TURNAROUND, 0xE3, 0x07 }, { PMC_EV_K8_NB_MEMORY_CONTROLLER_BYPASS_SATURATION, 0xE4, 0x0F }, { PMC_EV_K8_NB_SIZED_COMMANDS, 0xEB, 0x7F }, { PMC_EV_K8_NB_PROBE_RESULT, 0xEC, 0x0F }, { PMC_EV_K8_NB_HT_BUS0_BANDWIDTH, 0xF6, 0x0F }, { PMC_EV_K8_NB_HT_BUS1_BANDWIDTH, 0xF7, 0x0F }, { PMC_EV_K8_NB_HT_BUS2_BANDWIDTH, 0xF8, 0x0F } }; const int amd_event_codes_size = nitems(amd_event_codes); /* * Per-processor information */ struct amd_cpu { struct pmc_hw pc_amdpmcs[AMD_NPMCS]; }; static struct amd_cpu **amd_pcpu; /* * read a pmc register */ static int amd_read_pmc(int cpu, int ri, pmc_value_t *v) { enum pmc_mode mode; const struct amd_descr *pd; struct pmc *pm; pmc_value_t tmp; KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), ("[amd,%d] illegal CPU value %d", __LINE__, cpu)); KASSERT(ri >= 0 && ri < AMD_NPMCS, ("[amd,%d] illegal row-index %d", __LINE__, ri)); KASSERT(amd_pcpu[cpu], ("[amd,%d] null per-cpu, cpu %d", __LINE__, cpu)); pm = amd_pcpu[cpu]->pc_amdpmcs[ri].phw_pmc; pd = &amd_pmcdesc[ri]; KASSERT(pm != NULL, ("[amd,%d] No owner for HWPMC [cpu%d,pmc%d]", __LINE__, cpu, ri)); mode = PMC_TO_MODE(pm); PMCDBG2(MDP,REA,1,"amd-read id=%d class=%d", ri, pd->pm_descr.pd_class); #ifdef HWPMC_DEBUG KASSERT(pd->pm_descr.pd_class == amd_pmc_class, ("[amd,%d] unknown PMC class (%d)", __LINE__, pd->pm_descr.pd_class)); #endif tmp = rdmsr(pd->pm_perfctr); /* RDMSR serializes */ PMCDBG2(MDP,REA,2,"amd-read (pre-munge) id=%d -> %jd", ri, tmp); if (PMC_IS_SAMPLING_MODE(mode)) { /* Sign extend 48 bit value to 64 bits. */ tmp = (pmc_value_t) (((int64_t) tmp << 16) >> 16); tmp = AMD_PERFCTR_VALUE_TO_RELOAD_COUNT(tmp); } *v = tmp; PMCDBG2(MDP,REA,2,"amd-read (post-munge) id=%d -> %jd", ri, *v); return 0; } /* * Write a PMC MSR. */ static int amd_write_pmc(int cpu, int ri, pmc_value_t v) { const struct amd_descr *pd; enum pmc_mode mode; struct pmc *pm; KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), ("[amd,%d] illegal CPU value %d", __LINE__, cpu)); KASSERT(ri >= 0 && ri < AMD_NPMCS, ("[amd,%d] illegal row-index %d", __LINE__, ri)); pm = amd_pcpu[cpu]->pc_amdpmcs[ri].phw_pmc; pd = &amd_pmcdesc[ri]; KASSERT(pm != NULL, ("[amd,%d] PMC not owned (cpu%d,pmc%d)", __LINE__, cpu, ri)); mode = PMC_TO_MODE(pm); #ifdef HWPMC_DEBUG KASSERT(pd->pm_descr.pd_class == amd_pmc_class, ("[amd,%d] unknown PMC class (%d)", __LINE__, pd->pm_descr.pd_class)); #endif /* use 2's complement of the count for sampling mode PMCs */ if (PMC_IS_SAMPLING_MODE(mode)) v = AMD_RELOAD_COUNT_TO_PERFCTR_VALUE(v); PMCDBG3(MDP,WRI,1,"amd-write cpu=%d ri=%d v=%jx", cpu, ri, v); /* write the PMC value */ wrmsr(pd->pm_perfctr, v); return 0; } /* * configure hardware pmc according to the configuration recorded in * pmc 'pm'. */ static int amd_config_pmc(int cpu, int ri, struct pmc *pm) { struct pmc_hw *phw; PMCDBG3(MDP,CFG,1, "cpu=%d ri=%d pm=%p", cpu, ri, pm); KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), ("[amd,%d] illegal CPU value %d", __LINE__, cpu)); KASSERT(ri >= 0 && ri < AMD_NPMCS, ("[amd,%d] illegal row-index %d", __LINE__, ri)); phw = &amd_pcpu[cpu]->pc_amdpmcs[ri]; KASSERT(pm == NULL || phw->phw_pmc == NULL, ("[amd,%d] pm=%p phw->pm=%p hwpmc not unconfigured", __LINE__, pm, phw->phw_pmc)); phw->phw_pmc = pm; return 0; } /* * Retrieve a configured PMC pointer from hardware state. */ static int amd_get_config(int cpu, int ri, struct pmc **ppm) { *ppm = amd_pcpu[cpu]->pc_amdpmcs[ri].phw_pmc; return 0; } /* * Machine dependent actions taken during the context switch in of a * thread. */ static int amd_switch_in(struct pmc_cpu *pc, struct pmc_process *pp) { (void) pc; PMCDBG3(MDP,SWI,1, "pc=%p pp=%p enable-msr=%d", pc, pp, (pp->pp_flags & PMC_PP_ENABLE_MSR_ACCESS) != 0); /* enable the RDPMC instruction if needed */ if (pp->pp_flags & PMC_PP_ENABLE_MSR_ACCESS) load_cr4(rcr4() | CR4_PCE); return 0; } /* * Machine dependent actions taken during the context switch out of a * thread. */ static int amd_switch_out(struct pmc_cpu *pc, struct pmc_process *pp) { (void) pc; (void) pp; /* can be NULL */ PMCDBG3(MDP,SWO,1, "pc=%p pp=%p enable-msr=%d", pc, pp, pp ? (pp->pp_flags & PMC_PP_ENABLE_MSR_ACCESS) == 1 : 0); /* always turn off the RDPMC instruction */ load_cr4(rcr4() & ~CR4_PCE); return 0; } /* * Check if a given allocation is feasible. */ static int amd_allocate_pmc(int cpu, int ri, struct pmc *pm, const struct pmc_op_pmcallocate *a) { int i; - uint32_t allowed_unitmask, caps, config, unitmask; + uint64_t allowed_unitmask, caps, config, unitmask; enum pmc_event pe; const struct pmc_descr *pd; (void) cpu; KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), ("[amd,%d] illegal CPU value %d", __LINE__, cpu)); KASSERT(ri >= 0 && ri < AMD_NPMCS, ("[amd,%d] illegal row index %d", __LINE__, ri)); pd = &amd_pmcdesc[ri].pm_descr; /* check class match */ if (pd->pd_class != a->pm_class) return EINVAL; caps = pm->pm_caps; PMCDBG2(MDP,ALL,1,"amd-allocate ri=%d caps=0x%x", ri, caps); + if((ri >= 0 && ri < 6) && !(a->pm_md.pm_amd.pm_amd_sub_class == PMC_AMD_SUB_CLASS_CORE)) + return EINVAL; + if((ri >= 6 && ri < 12) && !(a->pm_md.pm_amd.pm_amd_sub_class == PMC_AMD_SUB_CLASS_L3_CACHE)) + return EINVAL; + if((ri >= 12 && ri < 16) && !(a->pm_md.pm_amd.pm_amd_sub_class == PMC_AMD_SUB_CLASS_DATA_FABRIC)) + return EINVAL; + if ((pd->pd_caps & caps) != caps) return EPERM; if (strlen(pmc_cpuid) != 0) { pm->pm_md.pm_amd.pm_amd_evsel = a->pm_md.pm_amd.pm_amd_config; PMCDBG2(MDP,ALL,2,"amd-allocate ri=%d -> config=0x%x", ri, a->pm_md.pm_amd.pm_amd_config); return (0); } pe = a->pm_ev; /* map ev to the correct event mask code */ config = allowed_unitmask = 0; for (i = 0; i < amd_event_codes_size; i++) if (amd_event_codes[i].pe_ev == pe) { config = AMD_PMC_TO_EVENTMASK(amd_event_codes[i].pe_code); allowed_unitmask = AMD_PMC_TO_UNITMASK(amd_event_codes[i].pe_mask); break; } if (i == amd_event_codes_size) return EINVAL; unitmask = a->pm_md.pm_amd.pm_amd_config & AMD_PMC_UNITMASK; if (unitmask & ~allowed_unitmask) /* disallow reserved bits */ return EINVAL; if (unitmask && (caps & PMC_CAP_QUALIFIER)) config |= unitmask; if (caps & PMC_CAP_THRESHOLD) config |= a->pm_md.pm_amd.pm_amd_config & AMD_PMC_COUNTERMASK; /* set at least one of the 'usr' or 'os' caps */ if (caps & PMC_CAP_USER) config |= AMD_PMC_USR; if (caps & PMC_CAP_SYSTEM) config |= AMD_PMC_OS; if ((caps & (PMC_CAP_USER|PMC_CAP_SYSTEM)) == 0) config |= (AMD_PMC_USR|AMD_PMC_OS); if (caps & PMC_CAP_EDGE) config |= AMD_PMC_EDGE; if (caps & PMC_CAP_INVERT) config |= AMD_PMC_INVERT; if (caps & PMC_CAP_INTERRUPT) config |= AMD_PMC_INT; pm->pm_md.pm_amd.pm_amd_evsel = config; /* save config value */ PMCDBG2(MDP,ALL,2,"amd-allocate ri=%d -> config=0x%x", ri, config); return 0; } /* * Release machine dependent state associated with a PMC. This is a * no-op on this architecture. * */ /* ARGSUSED0 */ static int amd_release_pmc(int cpu, int ri, struct pmc *pmc) { #ifdef HWPMC_DEBUG const struct amd_descr *pd; #endif struct pmc_hw *phw; (void) pmc; KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), ("[amd,%d] illegal CPU value %d", __LINE__, cpu)); KASSERT(ri >= 0 && ri < AMD_NPMCS, ("[amd,%d] illegal row-index %d", __LINE__, ri)); phw = &amd_pcpu[cpu]->pc_amdpmcs[ri]; KASSERT(phw->phw_pmc == NULL, ("[amd,%d] PHW pmc %p non-NULL", __LINE__, phw->phw_pmc)); #ifdef HWPMC_DEBUG pd = &amd_pmcdesc[ri]; if (pd->pm_descr.pd_class == amd_pmc_class) KASSERT(AMD_PMC_IS_STOPPED(pd->pm_evsel), ("[amd,%d] PMC %d released while active", __LINE__, ri)); #endif return 0; } /* * start a PMC. */ static int amd_start_pmc(int cpu, int ri) { - uint32_t config; + uint64_t config; struct pmc *pm; struct pmc_hw *phw; const struct amd_descr *pd; KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), ("[amd,%d] illegal CPU value %d", __LINE__, cpu)); KASSERT(ri >= 0 && ri < AMD_NPMCS, ("[amd,%d] illegal row-index %d", __LINE__, ri)); phw = &amd_pcpu[cpu]->pc_amdpmcs[ri]; pm = phw->phw_pmc; pd = &amd_pmcdesc[ri]; KASSERT(pm != NULL, ("[amd,%d] starting cpu%d,pmc%d with null pmc record", __LINE__, cpu, ri)); PMCDBG2(MDP,STA,1,"amd-start cpu=%d ri=%d", cpu, ri); KASSERT(AMD_PMC_IS_STOPPED(pd->pm_evsel), ("[amd,%d] pmc%d,cpu%d: Starting active PMC \"%s\"", __LINE__, ri, cpu, pd->pm_descr.pd_name)); /* turn on the PMC ENABLE bit */ config = pm->pm_md.pm_amd.pm_amd_evsel | AMD_PMC_ENABLE; PMCDBG1(MDP,STA,2,"amd-start config=0x%x", config); wrmsr(pd->pm_evsel, config); return 0; } /* * Stop a PMC. */ static int amd_stop_pmc(int cpu, int ri) { struct pmc *pm; struct pmc_hw *phw; const struct amd_descr *pd; uint64_t config; KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), ("[amd,%d] illegal CPU value %d", __LINE__, cpu)); KASSERT(ri >= 0 && ri < AMD_NPMCS, ("[amd,%d] illegal row-index %d", __LINE__, ri)); phw = &amd_pcpu[cpu]->pc_amdpmcs[ri]; pm = phw->phw_pmc; pd = &amd_pmcdesc[ri]; KASSERT(pm != NULL, ("[amd,%d] cpu%d,pmc%d no PMC to stop", __LINE__, cpu, ri)); KASSERT(!AMD_PMC_IS_STOPPED(pd->pm_evsel), ("[amd,%d] PMC%d, CPU%d \"%s\" already stopped", __LINE__, ri, cpu, pd->pm_descr.pd_name)); PMCDBG1(MDP,STO,1,"amd-stop ri=%d", ri); /* turn off the PMC ENABLE bit */ config = pm->pm_md.pm_amd.pm_amd_evsel & ~AMD_PMC_ENABLE; wrmsr(pd->pm_evsel, config); return 0; } /* * Interrupt handler. This function needs to return '1' if the * interrupt was this CPU's PMCs or '0' otherwise. It is not allowed * to sleep or do anything a 'fast' interrupt handler is not allowed * to do. */ static int amd_intr(struct trapframe *tf) { int i, error, retval, cpu; - uint32_t config, evsel, perfctr; + uint64_t config, evsel, perfctr; struct pmc *pm; struct amd_cpu *pac; pmc_value_t v; cpu = curcpu; KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), ("[amd,%d] out of range CPU %d", __LINE__, cpu)); PMCDBG3(MDP,INT,1, "cpu=%d tf=%p um=%d", cpu, (void *) tf, TRAPF_USERMODE(tf)); retval = 0; pac = amd_pcpu[cpu]; /* * look for all PMCs that have interrupted: * - look for a running, sampling PMC which has overflowed * and which has a valid 'struct pmc' association * * If found, we call a helper to process the interrupt. * * If multiple PMCs interrupt at the same time, the AMD64 * processor appears to deliver as many NMIs as there are * outstanding PMC interrupts. So we process only one NMI * interrupt at a time. */ for (i = 0; retval == 0 && i < AMD_NPMCS; i++) { if ((pm = pac->pc_amdpmcs[i].phw_pmc) == NULL || !PMC_IS_SAMPLING_MODE(PMC_TO_MODE(pm))) { continue; } if (!AMD_PMC_HAS_OVERFLOWED(i)) continue; retval = 1; /* Found an interrupting PMC. */ if (pm->pm_state != PMC_STATE_RUNNING) continue; /* Stop the PMC, reload count. */ evsel = AMD_PMC_EVSEL_0 + i; perfctr = AMD_PMC_PERFCTR_0 + i; v = pm->pm_sc.pm_reloadcount; config = rdmsr(evsel); KASSERT((config & ~AMD_PMC_ENABLE) == (pm->pm_md.pm_amd.pm_amd_evsel & ~AMD_PMC_ENABLE), - ("[amd,%d] config mismatch reg=0x%x pm=0x%x", __LINE__, - config, pm->pm_md.pm_amd.pm_amd_evsel)); + ("[amd,%d] config mismatch reg=0x%jx pm=0x%jx", __LINE__, + (uintmax_t)config, (uintmax_t)pm->pm_md.pm_amd.pm_amd_evsel)); wrmsr(evsel, config & ~AMD_PMC_ENABLE); wrmsr(perfctr, AMD_RELOAD_COUNT_TO_PERFCTR_VALUE(v)); /* Restart the counter if logging succeeded. */ error = pmc_process_interrupt(PMC_HR, pm, tf); if (error == 0) wrmsr(evsel, config); } if (retval) counter_u64_add(pmc_stats.pm_intr_processed, 1); else counter_u64_add(pmc_stats.pm_intr_ignored, 1); PMCDBG1(MDP,INT,2, "retval=%d", retval); return (retval); } /* * describe a PMC */ static int amd_describe(int cpu, int ri, struct pmc_info *pi, struct pmc **ppmc) { int error; size_t copied; const struct amd_descr *pd; struct pmc_hw *phw; KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), ("[amd,%d] illegal CPU %d", __LINE__, cpu)); KASSERT(ri >= 0 && ri < AMD_NPMCS, ("[amd,%d] row-index %d out of range", __LINE__, ri)); phw = &amd_pcpu[cpu]->pc_amdpmcs[ri]; pd = &amd_pmcdesc[ri]; if ((error = copystr(pd->pm_descr.pd_name, pi->pm_name, PMC_NAME_MAX, &copied)) != 0) return error; pi->pm_class = pd->pm_descr.pd_class; if (phw->phw_state & PMC_PHW_FLAG_IS_ENABLED) { pi->pm_enabled = TRUE; *ppmc = phw->phw_pmc; } else { pi->pm_enabled = FALSE; *ppmc = NULL; } return 0; } /* * i386 specific entry points */ /* * return the MSR address of the given PMC. */ static int amd_get_msr(int ri, uint32_t *msr) { KASSERT(ri >= 0 && ri < AMD_NPMCS, ("[amd,%d] ri %d out of range", __LINE__, ri)); *msr = amd_pmcdesc[ri].pm_perfctr - AMD_PMC_PERFCTR_0; return (0); } /* * processor dependent initialization. */ static int amd_pcpu_init(struct pmc_mdep *md, int cpu) { int classindex, first_ri, n; struct pmc_cpu *pc; struct amd_cpu *pac; struct pmc_hw *phw; KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), ("[amd,%d] insane cpu number %d", __LINE__, cpu)); PMCDBG1(MDP,INI,1,"amd-init cpu=%d", cpu); amd_pcpu[cpu] = pac = malloc(sizeof(struct amd_cpu), M_PMC, M_WAITOK|M_ZERO); /* * Set the content of the hardware descriptors to a known * state and initialize pointers in the MI per-cpu descriptor. */ pc = pmc_pcpu[cpu]; #if defined(__amd64__) classindex = PMC_MDEP_CLASS_INDEX_K8; #elif defined(__i386__) classindex = md->pmd_cputype == PMC_CPU_AMD_K8 ? PMC_MDEP_CLASS_INDEX_K8 : PMC_MDEP_CLASS_INDEX_K7; #endif first_ri = md->pmd_classdep[classindex].pcd_ri; KASSERT(pc != NULL, ("[amd,%d] NULL per-cpu pointer", __LINE__)); for (n = 0, phw = pac->pc_amdpmcs; n < AMD_NPMCS; n++, phw++) { phw->phw_state = PMC_PHW_FLAG_IS_ENABLED | PMC_PHW_CPU_TO_STATE(cpu) | PMC_PHW_INDEX_TO_STATE(n); phw->phw_pmc = NULL; pc->pc_hwpmcs[n + first_ri] = phw; } return (0); } /* * processor dependent cleanup prior to the KLD * being unloaded */ static int amd_pcpu_fini(struct pmc_mdep *md, int cpu) { int classindex, first_ri, i; uint32_t evsel; struct pmc_cpu *pc; struct amd_cpu *pac; KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), ("[amd,%d] insane cpu number (%d)", __LINE__, cpu)); PMCDBG1(MDP,INI,1,"amd-cleanup cpu=%d", cpu); /* * First, turn off all PMCs on this CPU. */ for (i = 0; i < 4; i++) { /* XXX this loop is now not needed */ evsel = rdmsr(AMD_PMC_EVSEL_0 + i); evsel &= ~AMD_PMC_ENABLE; wrmsr(AMD_PMC_EVSEL_0 + i, evsel); } /* * Next, free up allocated space. */ if ((pac = amd_pcpu[cpu]) == NULL) return (0); amd_pcpu[cpu] = NULL; #ifdef HWPMC_DEBUG for (i = 0; i < AMD_NPMCS; i++) { KASSERT(pac->pc_amdpmcs[i].phw_pmc == NULL, ("[amd,%d] CPU%d/PMC%d in use", __LINE__, cpu, i)); KASSERT(AMD_PMC_IS_STOPPED(AMD_PMC_EVSEL_0 + i), ("[amd,%d] CPU%d/PMC%d not stopped", __LINE__, cpu, i)); } #endif pc = pmc_pcpu[cpu]; KASSERT(pc != NULL, ("[amd,%d] NULL per-cpu state", __LINE__)); #if defined(__amd64__) classindex = PMC_MDEP_CLASS_INDEX_K8; #elif defined(__i386__) classindex = md->pmd_cputype == PMC_CPU_AMD_K8 ? PMC_MDEP_CLASS_INDEX_K8 : PMC_MDEP_CLASS_INDEX_K7; #endif first_ri = md->pmd_classdep[classindex].pcd_ri; /* * Reset pointers in the MI 'per-cpu' state. */ for (i = 0; i < AMD_NPMCS; i++) { pc->pc_hwpmcs[i + first_ri] = NULL; } free(pac, M_PMC); return (0); } /* * Initialize ourselves. */ struct pmc_mdep * pmc_amd_initialize(void) { int classindex, error, i, ncpus; struct pmc_classdep *pcd; enum pmc_cputype cputype; struct pmc_mdep *pmc_mdep; enum pmc_class class; int model; char *name; /* * The presence of hardware performance counters on the AMD * Athlon, Duron or later processors, is _not_ indicated by * any of the processor feature flags set by the 'CPUID' * instruction, so we only check the 'instruction family' * field returned by CPUID for instruction family >= 6. */ name = NULL; model = ((cpu_id & 0xF0000) >> 12) | ((cpu_id & 0xF0) >> 4); if (CPUID_TO_FAMILY(cpu_id) == 0x17) snprintf(pmc_cpuid, sizeof(pmc_cpuid), "AuthenticAMD-%d-%02X", CPUID_TO_FAMILY(cpu_id), model); switch (cpu_id & 0xF00) { #if defined(__i386__) case 0x600: /* Athlon(tm) processor */ classindex = PMC_MDEP_CLASS_INDEX_K7; cputype = PMC_CPU_AMD_K7; class = PMC_CLASS_K7; name = "K7"; break; #endif case 0xF00: /* Athlon64/Opteron processor */ classindex = PMC_MDEP_CLASS_INDEX_K8; cputype = PMC_CPU_AMD_K8; class = PMC_CLASS_K8; name = "K8"; break; default: (void) printf("pmc: Unknown AMD CPU %x %d-%d.\n", cpu_id, (cpu_id & 0xF00) >> 8, model); return NULL; } #ifdef HWPMC_DEBUG amd_pmc_class = class; #endif /* * Allocate space for pointers to PMC HW descriptors and for * the MDEP structure used by MI code. */ amd_pcpu = malloc(sizeof(struct amd_cpu *) * pmc_cpu_max(), M_PMC, M_WAITOK|M_ZERO); /* * These processors have two classes of PMCs: the TSC and * programmable PMCs. */ pmc_mdep = pmc_mdep_alloc(2); pmc_mdep->pmd_cputype = cputype; ncpus = pmc_cpu_max(); /* Initialize the TSC. */ error = pmc_tsc_initialize(pmc_mdep, ncpus); if (error) goto error; /* Initialize AMD K7 and K8 PMC handling. */ pcd = &pmc_mdep->pmd_classdep[classindex]; pcd->pcd_caps = AMD_PMC_CAPS; pcd->pcd_class = class; pcd->pcd_num = AMD_NPMCS; pcd->pcd_ri = pmc_mdep->pmd_npmc; pcd->pcd_width = 48; /* fill in the correct pmc name and class */ for (i = 0; i < AMD_NPMCS; i++) { (void) snprintf(amd_pmcdesc[i].pm_descr.pd_name, sizeof(amd_pmcdesc[i].pm_descr.pd_name), "%s-%d", name, i); amd_pmcdesc[i].pm_descr.pd_class = class; } pcd->pcd_allocate_pmc = amd_allocate_pmc; pcd->pcd_config_pmc = amd_config_pmc; pcd->pcd_describe = amd_describe; pcd->pcd_get_config = amd_get_config; pcd->pcd_get_msr = amd_get_msr; pcd->pcd_pcpu_fini = amd_pcpu_fini; pcd->pcd_pcpu_init = amd_pcpu_init; pcd->pcd_read_pmc = amd_read_pmc; pcd->pcd_release_pmc = amd_release_pmc; pcd->pcd_start_pmc = amd_start_pmc; pcd->pcd_stop_pmc = amd_stop_pmc; pcd->pcd_write_pmc = amd_write_pmc; pmc_mdep->pmd_pcpu_init = NULL; pmc_mdep->pmd_pcpu_fini = NULL; pmc_mdep->pmd_intr = amd_intr; pmc_mdep->pmd_switch_in = amd_switch_in; pmc_mdep->pmd_switch_out = amd_switch_out; pmc_mdep->pmd_npmc += AMD_NPMCS; PMCDBG0(MDP,INI,0,"amd-initialize"); return (pmc_mdep); error: if (error) { free(pmc_mdep, M_PMC); pmc_mdep = NULL; } return (NULL); } /* * Finalization code for AMD CPUs. */ void pmc_amd_finalize(struct pmc_mdep *md) { #if defined(INVARIANTS) int classindex, i, ncpus, pmcclass; #endif pmc_tsc_finalize(md); KASSERT(amd_pcpu != NULL, ("[amd,%d] NULL per-cpu array pointer", __LINE__)); #if defined(INVARIANTS) switch (md->pmd_cputype) { #if defined(__i386__) case PMC_CPU_AMD_K7: classindex = PMC_MDEP_CLASS_INDEX_K7; pmcclass = PMC_CLASS_K7; break; #endif default: classindex = PMC_MDEP_CLASS_INDEX_K8; pmcclass = PMC_CLASS_K8; } KASSERT(md->pmd_classdep[classindex].pcd_class == pmcclass, ("[amd,%d] pmc class mismatch", __LINE__)); ncpus = pmc_cpu_max(); for (i = 0; i < ncpus; i++) KASSERT(amd_pcpu[i] == NULL, ("[amd,%d] non-null pcpu", __LINE__)); #endif free(amd_pcpu, M_PMC); amd_pcpu = NULL; } Index: head/sys/dev/hwpmc/hwpmc_amd.h =================================================================== --- head/sys/dev/hwpmc/hwpmc_amd.h (revision 340107) +++ head/sys/dev/hwpmc/hwpmc_amd.h (revision 340108) @@ -1,99 +1,141 @@ /*- * SPDX-License-Identifier: BSD-2-Clause-FreeBSD * * Copyright (c) 2005, Joseph Koshy * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. * * $FreeBSD$ */ /* Machine dependent interfaces */ #ifndef _DEV_HWPMC_AMD_H_ #define _DEV_HWPMC_AMD_H_ 1 /* AMD K7 and K8 PMCs */ #define AMD_PMC_EVSEL_0 0xC0010000 #define AMD_PMC_EVSEL_1 0xC0010001 #define AMD_PMC_EVSEL_2 0xC0010002 #define AMD_PMC_EVSEL_3 0xC0010003 #define AMD_PMC_PERFCTR_0 0xC0010004 #define AMD_PMC_PERFCTR_1 0xC0010005 #define AMD_PMC_PERFCTR_2 0xC0010006 #define AMD_PMC_PERFCTR_3 0xC0010007 +/* CORE */ +#define AMD_PMC_EVSEL_4 0xC0010208 +#define AMD_PMC_EVSEL_5 0xC001020A +#define AMD_PMC_PERFCTR_4 0xC0010209 +#define AMD_PMC_PERFCTR_5 0xC001020B +/* L3 */ +#define AMD_PMC_EVSEL_EP_L3_0 0xC0010230 +#define AMD_PMC_EVSEL_EP_L3_1 0xC0010232 +#define AMD_PMC_EVSEL_EP_L3_2 0xC0010234 +#define AMD_PMC_EVSEL_EP_L3_3 0xC0010236 +#define AMD_PMC_EVSEL_EP_L3_4 0xC0010238 +#define AMD_PMC_EVSEL_EP_L3_5 0xC001023A -#define AMD_NPMCS 4 +#define AMD_PMC_PERFCTR_EP_L3_0 0xC0010231 +#define AMD_PMC_PERFCTR_EP_L3_1 0xC0010233 +#define AMD_PMC_PERFCTR_EP_L3_2 0xC0010235 +#define AMD_PMC_PERFCTR_EP_L3_3 0xC0010237 +#define AMD_PMC_PERFCTR_EP_L3_4 0xC0010239 +#define AMD_PMC_PERFCTR_EP_L3_5 0xC001023B +/* DF */ +#define AMD_PMC_EVSEL_EP_DF_0 0xC0010240 +#define AMD_PMC_EVSEL_EP_DF_1 0xC0010242 +#define AMD_PMC_EVSEL_EP_DF_2 0xC0010244 +#define AMD_PMC_EVSEL_EP_DF_3 0xC0010246 +#define AMD_PMC_PERFCTR_EP_DF_0 0xC0010241 +#define AMD_PMC_PERFCTR_EP_DF_1 0xC0010243 +#define AMD_PMC_PERFCTR_EP_DF_2 0xC0010245 +#define AMD_PMC_PERFCTR_EP_DF_3 0xC0010247 + +#define AMD_NPMCS 16 + + #define AMD_PMC_COUNTERMASK 0xFF000000 #define AMD_PMC_TO_COUNTER(x) (((x) << 24) & AMD_PMC_COUNTERMASK) #define AMD_PMC_INVERT (1 << 23) #define AMD_PMC_ENABLE (1 << 22) #define AMD_PMC_INT (1 << 20) #define AMD_PMC_PC (1 << 19) #define AMD_PMC_EDGE (1 << 18) #define AMD_PMC_OS (1 << 17) #define AMD_PMC_USR (1 << 16) +#define AMD_PMC_L3SLICEMASK (0x000F000000000000) +#define AMD_PMC_L3COREMASK (0xFF00000000000000) +#define AMD_PMC_TO_L3SLICE(x) (((x) << 48) & AMD_PMC_L3SLICEMASK) +#define AMD_PMC_TO_L3CORE(x) (((x) << 56) & AMD_PMC_L3COREMASK) #define AMD_PMC_UNITMASK_M 0x10 #define AMD_PMC_UNITMASK_O 0x08 #define AMD_PMC_UNITMASK_E 0x04 #define AMD_PMC_UNITMASK_S 0x02 #define AMD_PMC_UNITMASK_I 0x01 #define AMD_PMC_UNITMASK_MOESI 0x1F #define AMD_PMC_UNITMASK 0xFF00 #define AMD_PMC_EVENTMASK 0xF000000FF #define AMD_PMC_TO_UNITMASK(x) (((x) << 8) & AMD_PMC_UNITMASK) #define AMD_PMC_TO_EVENTMASK(x) (((x) & 0xFF) | (((uint64_t)(x) & 0xF00) << 24)) +#define AMD_PMC_TO_EVENTMASK_DF(x) (((x) & 0xFF) | (((uint64_t)(x) & 0x0F00) << 24)) | (((uint64_t)(x) & 0x3000) << 47) #define AMD_VALID_BITS (AMD_PMC_COUNTERMASK | AMD_PMC_INVERT | \ AMD_PMC_ENABLE | AMD_PMC_INT | AMD_PMC_PC | AMD_PMC_EDGE | \ AMD_PMC_OS | AMD_PMC_USR | AMD_PMC_UNITMASK | AMD_PMC_EVENTMASK) #define AMD_PMC_CAPS (PMC_CAP_INTERRUPT | PMC_CAP_USER | \ PMC_CAP_SYSTEM | PMC_CAP_EDGE | PMC_CAP_THRESHOLD | \ PMC_CAP_READ | PMC_CAP_WRITE | PMC_CAP_INVERT | PMC_CAP_QUALIFIER) #define AMD_PMC_IS_STOPPED(evsel) ((rdmsr((evsel)) & AMD_PMC_ENABLE) == 0) #define AMD_PMC_HAS_OVERFLOWED(pmc) ((rdpmc(pmc) & (1ULL << 47)) == 0) #define AMD_RELOAD_COUNT_TO_PERFCTR_VALUE(V) (-(V)) #define AMD_PERFCTR_VALUE_TO_RELOAD_COUNT(P) (-(P)) +enum sub_class{ + PMC_AMD_SUB_CLASS_CORE, + PMC_AMD_SUB_CLASS_L3_CACHE, + PMC_AMD_SUB_CLASS_DATA_FABRIC +}; + struct pmc_md_amd_op_pmcallocate { - uint32_t pm_amd_config; + uint64_t pm_amd_config; + uint32_t pm_amd_sub_class; }; #ifdef _KERNEL /* MD extension for 'struct pmc' */ struct pmc_md_amd_pmc { - uint32_t pm_amd_evsel; + uint64_t pm_amd_evsel; }; #endif /* _KERNEL */ #endif /* _DEV_HWPMC_AMD_H_ */