Index: head/sys/arm64/rockchip/rk_i2c.c =================================================================== --- head/sys/arm64/rockchip/rk_i2c.c (nonexistent) +++ head/sys/arm64/rockchip/rk_i2c.c (revision 335114) @@ -0,0 +1,607 @@ +/*- + * SPDX-License-Identifier: BSD-2-Clause-FreeBSD + * + * Copyright (c) 2018 Emmanuel Vadot + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + +#include +__FBSDID("$FreeBSD$"); + +#include +#include +#include +#include +#include +#include +#include + +#include +#include + +#include +#include + +#include + +#include "iicbus_if.h" + +#include "opt_soc.h" + + +#define RK_I2C_CON 0x00 +#define RK_I2C_CON_EN (1 << 0) +#define RK_I2C_CON_MODE_SHIFT 1 +#define RK_I2C_CON_MODE_TX 0 +#define RK_I2C_CON_MODE_RRX 1 +#define RK_I2C_CON_MODE_RX 2 +#define RK_I2C_CON_MODE_RTX 3 +#define RK_I2C_CON_MODE_MASK 0x6 +#define RK_I2C_CON_START (1 << 3) +#define RK_I2C_CON_STOP (1 << 4) +#define RK_I2C_CON_LASTACK (1 << 5) +#define RK_I2C_CON_NAKSTOP (1 << 6) + +#define RK_I2C_CLKDIV 0x04 +#define RK_I2C_CLKDIVL_MASK 0xFFFF +#define RK_I2C_CLKDIVL_SHIFT 0 +#define RK_I2C_CLKDIVH_MASK 0xFFFF0000 +#define RK_I2C_CLKDIVH_SHIFT 16 +#define RK_I2C_CLKDIV_MUL 8 + +#define RK_I2C_MRXADDR 0x08 +#define RK_I2C_MRXADDR_SADDR_MASK 0xFFFFFF +#define RK_I2C_MRXADDR_VALID(x) (1 << (24 + x)) + +#define RK_I2C_MRXRADDR 0x0C +#define RK_I2C_MRXRADDR_SRADDR_MASK 0xFFFFFF +#define RK_I2C_MRXRADDR_VALID(x) (1 << (24 + x)) + +#define RK_I2C_MTXCNT 0x10 +#define RK_I2C_MTXCNT_MASK 0x3F + +#define RK_I2C_MRXCNT 0x14 +#define RK_I2C_MRXCNT_MASK 0x3F + +#define RK_I2C_IEN 0x18 +#define RK_I2C_IEN_BTFIEN (1 << 0) +#define RK_I2C_IEN_BRFIEN (1 << 1) +#define RK_I2C_IEN_MBTFIEN (1 << 2) +#define RK_I2C_IEN_MBRFIEN (1 << 3) +#define RK_I2C_IEN_STARTIEN (1 << 4) +#define RK_I2C_IEN_STOPIEN (1 << 5) +#define RK_I2C_IEN_NAKRCVIEN (1 << 6) +#define RK_I2C_IEN_ALL (RK_I2C_IEN_BTFIEN | \ + RK_I2C_IEN_BRFIEN | RK_I2C_IEN_MBTFIEN | RK_I2C_IEN_MBRFIEN | \ + RK_I2C_IEN_STARTIEN | RK_I2C_IEN_STOPIEN | RK_I2C_IEN_NAKRCVIEN) + +#define RK_I2C_IPD 0x1C +#define RK_I2C_IPD_BTFIPD (1 << 0) +#define RK_I2C_IPD_BRFIPD (1 << 1) +#define RK_I2C_IPD_MBTFIPD (1 << 2) +#define RK_I2C_IPD_MBRFIPD (1 << 3) +#define RK_I2C_IPD_STARTIPD (1 << 4) +#define RK_I2C_IPD_STOPIPD (1 << 5) +#define RK_I2C_IPD_NAKRCVIPD (1 << 6) +#define RK_I2C_IPD_ALL (RK_I2C_IPD_BTFIPD | \ + RK_I2C_IPD_BRFIPD | RK_I2C_IPD_MBTFIPD | RK_I2C_IPD_MBRFIPD | \ + RK_I2C_IPD_STARTIPD | RK_I2C_IPD_STOPIPD | RK_I2C_IPD_NAKRCVIPD) + +#define RK_I2C_FNCT 0x20 +#define RK_I2C_FNCT_MASK 0x3F + +#define RK_I2C_TXDATA_BASE 0x100 + +#define RK_I2C_RXDATA_BASE 0x200 + +enum rk_i2c_state { + STATE_IDLE = 0, + STATE_START, + STATE_READ, + STATE_WRITE, + STATE_STOP +}; + +struct rk_i2c_softc { + device_t dev; + struct resource *res[2]; + struct mtx mtx; + clk_t sclk; + clk_t pclk; + int busy; + void * intrhand; + uint32_t intr; + uint32_t ipd; + struct iic_msg *msg; + size_t cnt; + int transfer_done; + int nak_recv; + uint8_t mode; + uint8_t state; + + device_t iicbus; +}; + +static struct ofw_compat_data compat_data[] = { +#ifdef SOC_ROCKCHIP_RK3328 + {"rockchip,rk3328-i2c", 1}, +#endif + {NULL, 0} +}; + +static struct resource_spec rk_i2c_spec[] = { + { SYS_RES_MEMORY, 0, RF_ACTIVE }, + { SYS_RES_IRQ, 0, RF_ACTIVE | RF_SHAREABLE }, + { -1, 0 } +}; + +static int rk_i2c_probe(device_t dev); +static int rk_i2c_attach(device_t dev); +static int rk_i2c_detach(device_t dev); + +#define RK_I2C_LOCK(sc) mtx_lock(&(sc)->mtx) +#define RK_I2C_UNLOCK(sc) mtx_unlock(&(sc)->mtx) +#define RK_I2C_ASSERT_LOCKED(sc) mtx_assert(&(sc)->mtx, MA_OWNED) +#define RK_I2C_READ(sc, reg) bus_read_4((sc)->res[0], (reg)) +#define RK_I2C_WRITE(sc, reg, val) bus_write_4((sc)->res[0], (reg), (val)) + +static uint32_t +rk_i2c_get_clkdiv(struct rk_i2c_softc *sc, uint64_t speed) +{ + uint64_t pclk_freq; + uint32_t clkdiv; + int err; + + err = clk_get_freq(sc->pclk, &pclk_freq); + if (err != 0) + return (err); + + clkdiv = (pclk_freq / speed / RK_I2C_CLKDIV_MUL / 2) - 1; + clkdiv &= RK_I2C_CLKDIVL_MASK; + + clkdiv = clkdiv << RK_I2C_CLKDIVH_SHIFT | clkdiv; + + return (clkdiv); +} + +static int +rk_i2c_reset(device_t dev, u_char speed, u_char addr, u_char *oldaddr) +{ + struct rk_i2c_softc *sc; + uint32_t clkdiv; + u_int busfreq; + + sc = device_get_softc(dev); + + busfreq = IICBUS_GET_FREQUENCY(sc->iicbus, speed); + + clkdiv = rk_i2c_get_clkdiv(sc, busfreq); + + RK_I2C_LOCK(sc); + + /* Set the clock divider */ + RK_I2C_WRITE(sc, RK_I2C_CLKDIV, clkdiv); + + /* Disable the module */ + RK_I2C_WRITE(sc, RK_I2C_CON, 0); + + RK_I2C_UNLOCK(sc); + + return (0); +} + +static void +rk_i2c_fill_tx(struct rk_i2c_softc *sc) +{ + uint32_t buf32; + uint8_t buf; + int i, j, len; + + if (sc->msg == NULL || sc->msg->len == sc->cnt) + return; + + len = sc->msg->len - sc->cnt; + if (len > 8) + len = 8; + + for (i = 0; i < len; i++) { + buf32 = 0; + for (j = 0; j < 4 ; j++) { + if (sc->cnt == sc->msg->len) + break; + + /* Fill the addr if needed */ + if (sc->cnt == 0) { + buf = sc->msg->slave; + } + else + buf = sc->msg->buf[sc->cnt - 1]; + + buf32 |= buf << (j * 8); + + sc->cnt++; + } + + RK_I2C_WRITE(sc, RK_I2C_TXDATA_BASE + 4 * i, buf32); + + if (sc->cnt == sc->msg->len) + break; + } +} + +static void +rk_i2c_drain_rx(struct rk_i2c_softc *sc) +{ + uint32_t buf32 = 0; + uint8_t buf8; + int len; + int i; + + if (sc->msg == NULL) { + device_printf(sc->dev, "No current iic msg\n"); + return; + } + + len = sc->msg->len - sc->cnt; + if (len > 32) + len = 32; + + for (i = 0; i < len; i++) { + if (i % 4 == 0) + buf32 = RK_I2C_READ(sc, RK_I2C_RXDATA_BASE + (i / 4) * 4); + + buf8 = (buf32 >> ((i % 4) * 8)) & 0xFF; + + sc->msg->buf[sc->cnt++] = buf8; + } +} + +static void +rk_i2c_send_start(struct rk_i2c_softc *sc) +{ + uint32_t reg; + + RK_I2C_WRITE(sc, RK_I2C_IEN, RK_I2C_IEN_STARTIEN); + + sc->state = STATE_START; + + reg = RK_I2C_READ(sc, RK_I2C_CON); + reg |= RK_I2C_CON_START; + reg |= RK_I2C_CON_EN; + reg &= ~RK_I2C_CON_MODE_MASK; + reg |= sc->mode << RK_I2C_CON_MODE_SHIFT; + RK_I2C_WRITE(sc, RK_I2C_CON, reg); +} + +static void +rk_i2c_send_stop(struct rk_i2c_softc *sc) +{ + uint32_t reg; + + RK_I2C_WRITE(sc, RK_I2C_IEN, RK_I2C_IEN_STOPIEN); + + sc->state = STATE_STOP; + + reg = RK_I2C_READ(sc, RK_I2C_CON); + reg |= RK_I2C_CON_STOP; + RK_I2C_WRITE(sc, RK_I2C_CON, reg); +} + +static void +rk_i2c_intr(void *arg) +{ + struct rk_i2c_softc *sc; + uint32_t reg; + + sc = (struct rk_i2c_softc *)arg; + + RK_I2C_LOCK(sc); + + sc->ipd = RK_I2C_READ(sc, RK_I2C_IPD); + RK_I2C_WRITE(sc, RK_I2C_IPD, sc->ipd); + + switch (sc->state) { + case STATE_START: + /* Disable start bit */ + reg = RK_I2C_READ(sc, RK_I2C_CON); + reg &= ~RK_I2C_CON_START; + RK_I2C_WRITE(sc, RK_I2C_CON, reg); + + if (sc->mode == RK_I2C_CON_MODE_RRX || + sc->mode == RK_I2C_CON_MODE_RX) { + sc->state = STATE_READ; + RK_I2C_WRITE(sc, RK_I2C_IEN, RK_I2C_IEN_MBRFIEN | + RK_I2C_IEN_NAKRCVIEN); + + reg = RK_I2C_READ(sc, RK_I2C_CON); + reg |= RK_I2C_CON_LASTACK; + RK_I2C_WRITE(sc, RK_I2C_CON, reg); + + RK_I2C_WRITE(sc, RK_I2C_MRXCNT, sc->msg->len); + } else { + sc->state = STATE_WRITE; + RK_I2C_WRITE(sc, RK_I2C_IEN, RK_I2C_IEN_MBTFIEN | + RK_I2C_IEN_NAKRCVIEN); + + sc->msg->len += 1; + rk_i2c_fill_tx(sc); + RK_I2C_WRITE(sc, RK_I2C_MTXCNT, sc->msg->len); + } + break; + case STATE_READ: + rk_i2c_drain_rx(sc); + + if (sc->cnt == sc->msg->len) + rk_i2c_send_stop(sc); + + break; + case STATE_WRITE: + if (sc->cnt == sc->msg->len) + rk_i2c_send_stop(sc); + + break; + case STATE_STOP: + /* Disable stop bit */ + reg = RK_I2C_READ(sc, RK_I2C_CON); + reg &= ~RK_I2C_CON_STOP; + RK_I2C_WRITE(sc, RK_I2C_CON, reg); + + sc->transfer_done = 1; + sc->state = STATE_IDLE; + break; + case STATE_IDLE: + break; + } + + wakeup(sc); + RK_I2C_UNLOCK(sc); +} + +static int +rk_i2c_transfer(device_t dev, struct iic_msg *msgs, uint32_t nmsgs) +{ + struct rk_i2c_softc *sc; + uint32_t reg; + int i, j, msgskip, err = 0; + + sc = device_get_softc(dev); + + while (sc->busy) + mtx_sleep(sc, &sc->mtx, 0, "i2cbuswait", 0); + + sc->busy = 1; + + err = clk_enable(sc->pclk); + if (err != 0) { + device_printf(dev, "cannot enable pclk clock\n"); + goto out; + } + err = clk_enable(sc->sclk); + if (err != 0) { + device_printf(dev, "cannot enable i2c clock\n"); + goto out; + } + + RK_I2C_LOCK(sc); + + /* Clean stale interrupts */ + RK_I2C_WRITE(sc, RK_I2C_IPD, RK_I2C_IPD_ALL); + + for (i = 0; i < nmsgs; i += msgskip) { + if (nmsgs - i >= 2 && !(msgs[i].flags & IIC_M_RD) && + msgs[i + 1].flags & IIC_M_RD && msgs[i].len <= 4) { + sc->mode = RK_I2C_CON_MODE_RRX; + msgskip = 2; + sc->msg = &msgs[i + 1]; + + /* Write slave address */ + reg = msgs[i].slave | RK_I2C_MRXADDR_VALID(0); + RK_I2C_WRITE(sc, RK_I2C_MRXADDR, reg); + + /* Write slave register address */ + for (j = 0, reg = 0; j < msgs[i].len; j++) { + reg |= (msgs[i].buf[j] & 0xff) << (j * 8); + reg |= RK_I2C_MRXADDR_VALID(j); + } + + RK_I2C_WRITE(sc, RK_I2C_MRXRADDR, reg); + } else { + if (msgs[i].flags & IIC_M_RD) { + sc->mode = RK_I2C_CON_MODE_RX; + msgs[i].slave |= LSB; + } + else { + sc->mode = RK_I2C_CON_MODE_TX; + msgs[i].slave &= ~LSB; + } + msgskip = 1; + sc->msg = &msgs[i]; + } + + sc->transfer_done = 0; + sc->cnt = 0; + sc->state = STATE_IDLE; + rk_i2c_send_start(sc); + + while (err == 0 && sc->transfer_done != 1) { + err = msleep(sc, &sc->mtx, 0, "rk_i2c", 10 * hz); + } + } + + /* Disable the module and interrupts */ + RK_I2C_WRITE(sc, RK_I2C_CON, 0); + RK_I2C_WRITE(sc, RK_I2C_IEN, 0); + + sc->busy = 0; + + RK_I2C_UNLOCK(sc); + + err = clk_disable(sc->pclk); + if (err != 0) { + device_printf(dev, "cannot enable pclk clock\n"); + goto out; + } + err = clk_disable(sc->sclk); + if (err != 0) { + device_printf(dev, "cannot enable i2c clock\n"); + goto out; + } + +out: + return (err); +} + +static int +rk_i2c_probe(device_t dev) +{ + + if (!ofw_bus_status_okay(dev)) + return (ENXIO); + if (ofw_bus_search_compatible(dev, compat_data)->ocd_data == 0) + return (ENXIO); + + device_set_desc(dev, "RockChip I2C"); + return (BUS_PROBE_DEFAULT); +} + +static int +rk_i2c_attach(device_t dev) +{ + struct rk_i2c_softc *sc; + int error; + + sc = device_get_softc(dev); + sc->dev = dev; + + mtx_init(&sc->mtx, device_get_nameunit(dev), "rk_i2c", MTX_DEF); + + if (bus_alloc_resources(dev, rk_i2c_spec, sc->res) != 0) { + device_printf(dev, "cannot allocate resources for device\n"); + error = ENXIO; + goto fail; + } + + if (bus_setup_intr(dev, sc->res[1], + INTR_TYPE_MISC | INTR_MPSAFE, NULL, rk_i2c_intr, sc, + &sc->intrhand)) { + bus_release_resources(dev, rk_i2c_spec, sc->res); + device_printf(dev, "cannot setup interrupt handler\n"); + return (ENXIO); + } + + /* Activate the module clocks. */ + error = clk_get_by_ofw_name(dev, 0, "i2c", &sc->sclk); + if (error != 0) { + device_printf(dev, "cannot get i2c clock\n"); + goto fail; + } + error = clk_get_by_ofw_name(dev, 0, "pclk", &sc->pclk); + if (error != 0) { + device_printf(dev, "cannot get pclk clock\n"); + goto fail; + } + + sc->iicbus = device_add_child(dev, "iicbus", -1); + if (sc->iicbus == NULL) { + device_printf(dev, "cannot add iicbus child device\n"); + error = ENXIO; + goto fail; + } + + bus_generic_attach(dev); + + return (0); + +fail: + if (rk_i2c_detach(dev) != 0) + device_printf(dev, "Failed to detach\n"); + return (error); +} + +static int +rk_i2c_detach(device_t dev) +{ + struct rk_i2c_softc *sc; + int error; + + sc = device_get_softc(dev); + + if ((error = bus_generic_detach(dev)) != 0) + return (error); + + if (sc->iicbus != NULL) + if ((error = device_delete_child(dev, sc->iicbus)) != 0) + return (error); + + if (sc->sclk != NULL) + clk_release(sc->sclk); + if (sc->pclk != NULL) + clk_release(sc->pclk); + + if (sc->intrhand != NULL) + bus_teardown_intr(sc->dev, sc->res[1], sc->intrhand); + + bus_release_resources(dev, rk_i2c_spec, sc->res); + + mtx_destroy(&sc->mtx); + + return (0); +} + +static phandle_t +rk_i2c_get_node(device_t bus, device_t dev) +{ + + return ofw_bus_get_node(bus); +} + +static device_method_t rk_i2c_methods[] = { + DEVMETHOD(device_probe, rk_i2c_probe), + DEVMETHOD(device_attach, rk_i2c_attach), + DEVMETHOD(device_detach, rk_i2c_detach), + + /* OFW methods */ + DEVMETHOD(ofw_bus_get_node, rk_i2c_get_node), + + DEVMETHOD(iicbus_callback, iicbus_null_callback), + DEVMETHOD(iicbus_reset, rk_i2c_reset), + DEVMETHOD(iicbus_transfer, rk_i2c_transfer), + + DEVMETHOD_END +}; + +static driver_t rk_i2c_driver = { + "rk_i2c", + rk_i2c_methods, + sizeof(struct rk_i2c_softc), +}; + +static devclass_t rk_i2c_devclass; + +EARLY_DRIVER_MODULE(rk_i2c, simplebus, rk_i2c_driver, rk_i2c_devclass, 0, 0, + BUS_PASS_INTERRUPT + BUS_PASS_ORDER_LATE); +EARLY_DRIVER_MODULE(ofw_iicbus, rk_i2c, ofw_iicbus_driver, ofw_iicbus_devclass, + 0, 0, BUS_PASS_INTERRUPT + BUS_PASS_ORDER_LATE); +MODULE_DEPEND(rk_i2c, iicbus, 1, 1, 1); +MODULE_DEPEND(rk_i2c, ofw_iicbus, 1, 1, 1); +MODULE_VERSION(rk_i2c, 1); Property changes on: head/sys/arm64/rockchip/rk_i2c.c ___________________________________________________________________ Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:keywords ## -0,0 +1 ## +FreeBSD=%H \ No newline at end of property Added: svn:mime-type ## -0,0 +1 ## +text/plain \ No newline at end of property Index: head/sys/conf/files.arm64 =================================================================== --- head/sys/conf/files.arm64 (revision 335113) +++ head/sys/conf/files.arm64 (revision 335114) @@ -1,261 +1,262 @@ # $FreeBSD$ cloudabi32_vdso.o optional compat_cloudabi32 \ dependency "$S/contrib/cloudabi/cloudabi_vdso_armv6_on_64bit.S" \ compile-with "${CC} -x assembler-with-cpp -m32 -shared -nostdinc -nostdlib -Wl,-T$S/compat/cloudabi/cloudabi_vdso.lds $S/contrib/cloudabi/cloudabi_vdso_armv6_on_64bit.S -o ${.TARGET}" \ no-obj no-implicit-rule \ clean "cloudabi32_vdso.o" # cloudabi32_vdso_blob.o optional compat_cloudabi32 \ dependency "cloudabi32_vdso.o" \ compile-with "${OBJCOPY} --input-target binary --output-target elf64-littleaarch64 --binary-architecture aarch64 cloudabi32_vdso.o ${.TARGET}" \ no-implicit-rule \ clean "cloudabi32_vdso_blob.o" # cloudabi64_vdso.o optional compat_cloudabi64 \ dependency "$S/contrib/cloudabi/cloudabi_vdso_aarch64.S" \ compile-with "${CC} -x assembler-with-cpp -shared -nostdinc -nostdlib -Wl,-T$S/compat/cloudabi/cloudabi_vdso.lds $S/contrib/cloudabi/cloudabi_vdso_aarch64.S -o ${.TARGET}" \ no-obj no-implicit-rule \ clean "cloudabi64_vdso.o" # cloudabi64_vdso_blob.o optional compat_cloudabi64 \ dependency "cloudabi64_vdso.o" \ compile-with "${OBJCOPY} --input-target binary --output-target elf64-littleaarch64 --binary-architecture aarch64 cloudabi64_vdso.o ${.TARGET}" \ no-implicit-rule \ clean "cloudabi64_vdso_blob.o" # # Allwinner common files arm/allwinner/a10_ehci.c optional ehci aw_ehci fdt arm/allwinner/aw_gpio.c optional gpio aw_gpio fdt arm/allwinner/aw_mmc.c optional mmc aw_mmc fdt arm/allwinner/aw_nmi.c optional aw_nmi fdt \ compile-with "${NORMAL_C} -I$S/gnu/dts/include" arm/allwinner/aw_rsb.c optional aw_rsb fdt arm/allwinner/aw_rtc.c optional aw_rtc fdt arm/allwinner/aw_sid.c optional aw_sid fdt arm/allwinner/aw_spi.c optional aw_spi fdt arm/allwinner/aw_thermal.c optional aw_thermal fdt arm/allwinner/aw_usbphy.c optional ehci aw_usbphy fdt arm/allwinner/aw_wdog.c optional aw_wdog fdt arm/allwinner/axp81x.c optional axp81x fdt arm/allwinner/if_awg.c optional awg ext_resources syscon fdt # Allwinner clock driver arm/allwinner/clkng/aw_ccung.c optional aw_ccu fdt arm/allwinner/clkng/aw_clk_nkmp.c optional aw_ccu fdt arm/allwinner/clkng/aw_clk_nm.c optional aw_ccu fdt arm/allwinner/clkng/aw_clk_prediv_mux.c optional aw_ccu fdt arm/allwinner/clkng/ccu_a64.c optional soc_allwinner_a64 aw_ccu fdt arm/allwinner/clkng/ccu_h3.c optional soc_allwinner_h5 aw_ccu fdt arm/allwinner/clkng/ccu_sun8i_r.c optional aw_ccu fdt # Allwinner padconf files arm/allwinner/a64/a64_padconf.c optional soc_allwinner_a64 fdt arm/allwinner/a64/a64_r_padconf.c optional soc_allwinner_a64 fdt arm/allwinner/h3/h3_padconf.c optional soc_allwinner_h5 fdt arm/allwinner/h3/h3_r_padconf.c optional soc_allwinner_h5 fdt arm/annapurna/alpine/alpine_ccu.c optional al_ccu fdt arm/annapurna/alpine/alpine_nb_service.c optional al_nb_service fdt arm/annapurna/alpine/alpine_pci.c optional al_pci fdt arm/annapurna/alpine/alpine_pci_msix.c optional al_pci fdt arm/annapurna/alpine/alpine_serdes.c optional al_serdes fdt \ no-depend \ compile-with "${CC} -c -o ${.TARGET} ${CFLAGS} -I$S/contrib/alpine-hal -I$S/contrib/alpine-hal/eth ${PROF} ${.IMPSRC}" arm/arm/generic_timer.c standard arm/arm/gic.c standard arm/arm/gic_acpi.c optional acpi arm/arm/gic_fdt.c optional fdt arm/arm/pmu.c standard arm/arm/physmem.c standard arm/broadcom/bcm2835/bcm2835_audio.c optional sound vchiq fdt \ compile-with "${NORMAL_C} -DUSE_VCHIQ_ARM -D__VCCOREVER__=0x04000000 -I$S/contrib/vchiq" arm/broadcom/bcm2835/bcm2835_bsc.c optional bcm2835_bsc soc_brcm_bcm2837 fdt arm/broadcom/bcm2835/bcm2835_cpufreq.c optional soc_brcm_bcm2837 fdt arm/broadcom/bcm2835/bcm2835_dma.c optional soc_brcm_bcm2837 fdt arm/broadcom/bcm2835/bcm2835_fbd.c optional vt soc_brcm_bcm2837 fdt arm/broadcom/bcm2835/bcm2835_ft5406.c optional evdev bcm2835_ft5406 soc_brcm_bcm2837 fdt arm/broadcom/bcm2835/bcm2835_gpio.c optional gpio soc_brcm_bcm2837 fdt arm/broadcom/bcm2835/bcm2835_intr.c optional soc_brcm_bcm2837 fdt arm/broadcom/bcm2835/bcm2835_mbox.c optional soc_brcm_bcm2837 fdt arm/broadcom/bcm2835/bcm2835_rng.c optional random soc_brcm_bcm2837 fdt arm/broadcom/bcm2835/bcm2835_sdhci.c optional sdhci soc_brcm_bcm2837 fdt arm/broadcom/bcm2835/bcm2835_spi.c optional bcm2835_spi soc_brcm_bcm2837 fdt arm/broadcom/bcm2835/bcm2835_vcio.c optional soc_brcm_bcm2837 fdt arm/broadcom/bcm2835/bcm2835_wdog.c optional soc_brcm_bcm2837 fdt arm/broadcom/bcm2835/bcm2836.c optional soc_brcm_bcm2837 fdt arm/broadcom/bcm2835/bcm283x_dwc_fdt.c optional dwcotg fdt soc_brcm_bcm2837 arm/mv/armada38x/armada38x_rtc.c optional mv_rtc fdt arm64/acpica/acpi_machdep.c optional acpi arm64/acpica/OsdEnvironment.c optional acpi arm64/acpica/acpi_wakeup.c optional acpi arm64/acpica/pci_cfgreg.c optional acpi pci arm64/arm64/autoconf.c standard arm64/arm64/bus_machdep.c standard arm64/arm64/bus_space_asm.S standard arm64/arm64/busdma_bounce.c standard arm64/arm64/busdma_machdep.c standard arm64/arm64/bzero.S standard arm64/arm64/clock.c standard arm64/arm64/copyinout.S standard arm64/arm64/copystr.c standard arm64/arm64/cpu_errata.c standard arm64/arm64/cpufunc_asm.S standard arm64/arm64/db_disasm.c optional ddb arm64/arm64/db_interface.c optional ddb arm64/arm64/db_trace.c optional ddb arm64/arm64/debug_monitor.c optional ddb arm64/arm64/disassem.c optional ddb arm64/arm64/dump_machdep.c standard arm64/arm64/efirt_machdep.c optional efirt arm64/arm64/elf32_machdep.c optional compat_freebsd32 arm64/arm64/elf_machdep.c standard arm64/arm64/exception.S standard arm64/arm64/freebsd32_machdep.c optional compat_freebsd32 arm64/arm64/gicv3_its.c optional intrng fdt arm64/arm64/gic_v3.c standard arm64/arm64/gic_v3_acpi.c optional acpi arm64/arm64/gic_v3_fdt.c optional fdt arm64/arm64/identcpu.c standard arm64/arm64/in_cksum.c optional inet | inet6 arm64/arm64/locore.S standard no-obj arm64/arm64/machdep.c standard arm64/arm64/mem.c standard arm64/arm64/memcpy.S standard arm64/arm64/memmove.S standard arm64/arm64/minidump_machdep.c standard arm64/arm64/mp_machdep.c optional smp arm64/arm64/nexus.c standard arm64/arm64/ofw_machdep.c optional fdt arm64/arm64/pmap.c standard arm64/arm64/stack_machdep.c optional ddb | stack arm64/arm64/support.S standard arm64/arm64/swtch.S standard arm64/arm64/sys_machdep.c standard arm64/arm64/trap.c standard arm64/arm64/uio_machdep.c standard arm64/arm64/uma_machdep.c standard arm64/arm64/undefined.c standard arm64/arm64/unwind.c optional ddb | kdtrace_hooks | stack arm64/arm64/vfp.c standard arm64/arm64/vm_machdep.c standard arm64/cavium/thunder_pcie_fdt.c optional soc_cavm_thunderx pci fdt arm64/cavium/thunder_pcie_pem.c optional soc_cavm_thunderx pci arm64/cavium/thunder_pcie_pem_fdt.c optional soc_cavm_thunderx pci fdt arm64/cavium/thunder_pcie_common.c optional soc_cavm_thunderx pci arm64/cloudabi32/cloudabi32_sysvec.c optional compat_cloudabi32 arm64/cloudabi64/cloudabi64_sysvec.c optional compat_cloudabi64 arm64/coresight/coresight.c standard arm64/coresight/coresight_if.m standard arm64/coresight/coresight-cmd.c standard arm64/coresight/coresight-cpu-debug.c standard arm64/coresight/coresight-dynamic-replicator.c standard arm64/coresight/coresight-etm4x.c standard arm64/coresight/coresight-funnel.c standard arm64/coresight/coresight-tmc.c standard arm64/qualcomm/qcom_gcc.c optional qcom_gcc fdt contrib/vchiq/interface/compat/vchi_bsd.c optional vchiq soc_brcm_bcm2837 \ compile-with "${NORMAL_C} -DUSE_VCHIQ_ARM -D__VCCOREVER__=0x04000000 -I$S/contrib/vchiq" contrib/vchiq/interface/vchiq_arm/vchiq_2835_arm.c optional vchiq soc_brcm_bcm2837 \ compile-with "${NORMAL_C} -Wno-unused -DUSE_VCHIQ_ARM -D__VCCOREVER__=0x04000000 -I$S/contrib/vchiq" contrib/vchiq/interface/vchiq_arm/vchiq_arm.c optional vchiq soc_brcm_bcm2837 \ compile-with "${NORMAL_C} -Wno-unused -DUSE_VCHIQ_ARM -D__VCCOREVER__=0x04000000 -I$S/contrib/vchiq" contrib/vchiq/interface/vchiq_arm/vchiq_connected.c optional vchiq soc_brcm_bcm2837 \ compile-with "${NORMAL_C} -DUSE_VCHIQ_ARM -D__VCCOREVER__=0x04000000 -I$S/contrib/vchiq" contrib/vchiq/interface/vchiq_arm/vchiq_core.c optional vchiq soc_brcm_bcm2837 \ compile-with "${NORMAL_C} -DUSE_VCHIQ_ARM -D__VCCOREVER__=0x04000000 -I$S/contrib/vchiq" contrib/vchiq/interface/vchiq_arm/vchiq_kern_lib.c optional vchiq soc_brcm_bcm2837 \ compile-with "${NORMAL_C} -DUSE_VCHIQ_ARM -D__VCCOREVER__=0x04000000 -I$S/contrib/vchiq" contrib/vchiq/interface/vchiq_arm/vchiq_kmod.c optional vchiq soc_brcm_bcm2837 \ compile-with "${NORMAL_C} -DUSE_VCHIQ_ARM -D__VCCOREVER__=0x04000000 -I$S/contrib/vchiq" contrib/vchiq/interface/vchiq_arm/vchiq_shim.c optional vchiq soc_brcm_bcm2837 \ compile-with "${NORMAL_C} -DUSE_VCHIQ_ARM -D__VCCOREVER__=0x04000000 -I$S/contrib/vchiq" contrib/vchiq/interface/vchiq_arm/vchiq_util.c optional vchiq soc_brcm_bcm2837 \ compile-with "${NORMAL_C} -DUSE_VCHIQ_ARM -D__VCCOREVER__=0x04000000 -I$S/contrib/vchiq" crypto/armv8/armv8_crypto.c optional armv8crypto armv8_crypto_wrap.o optional armv8crypto \ dependency "$S/crypto/armv8/armv8_crypto_wrap.c" \ compile-with "${CC} -c ${CFLAGS:C/^-O2$/-O3/:N-nostdinc:N-mgeneral-regs-only} ${WERROR} ${NO_WCAST_QUAL} ${PROF} -march=armv8-a+crypto ${.IMPSRC}" \ no-implicit-rule \ clean "armv8_crypto_wrap.o" crypto/blowfish/bf_enc.c optional crypto | ipsec | ipsec_support crypto/des/des_enc.c optional crypto | ipsec | ipsec_support | netsmb dev/acpica/acpi_bus_if.m optional acpi dev/acpica/acpi_if.m optional acpi dev/acpica/acpi_pci_link.c optional acpi pci dev/acpica/acpi_pcib.c optional acpi pci dev/ahci/ahci_generic.c optional ahci dev/axgbe/if_axgbe.c optional axgbe dev/axgbe/xgbe-desc.c optional axgbe dev/axgbe/xgbe-dev.c optional axgbe dev/axgbe/xgbe-drv.c optional axgbe dev/axgbe/xgbe-mdio.c optional axgbe dev/cpufreq/cpufreq_dt.c optional cpufreq fdt dev/iicbus/twsi/a10_twsi.c optional twsi fdt dev/iicbus/twsi/twsi.c optional twsi fdt dev/hwpmc/hwpmc_arm64.c optional hwpmc dev/hwpmc/hwpmc_arm64_md.c optional hwpmc dev/mbox/mbox_if.m optional soc_brcm_bcm2837 dev/mmc/host/dwmmc.c optional dwmmc fdt dev/mmc/host/dwmmc_hisi.c optional dwmmc fdt soc_hisi_hi6220 dev/mmc/host/dwmmc_rockchip.c optional dwmmc fdt soc_rockchip_rk3328 dev/neta/if_mvneta_fdt.c optional neta fdt dev/neta/if_mvneta.c optional neta mdio mii dev/ofw/ofw_cpu.c optional fdt dev/ofw/ofwpci.c optional fdt pci dev/pci/pci_host_generic.c optional pci dev/pci/pci_host_generic_acpi.c optional pci acpi dev/pci/pci_host_generic_fdt.c optional pci fdt dev/psci/psci.c standard dev/psci/psci_arm64.S standard dev/psci/smccc.c standard dev/uart/uart_cpu_arm64.c optional uart dev/uart/uart_dev_mu.c optional uart uart_mu dev/uart/uart_dev_pl011.c optional uart pl011 dev/usb/controller/dwc_otg_hisi.c optional dwcotg fdt soc_hisi_hi6220 dev/usb/controller/ehci_mv.c optional ehci_mv fdt dev/usb/controller/generic_ehci.c optional ehci acpi dev/usb/controller/generic_ohci.c optional ohci fdt dev/usb/controller/generic_usb_if.m optional ohci fdt dev/usb/controller/xhci_mv.c optional xhci_mv fdt dev/vnic/mrml_bridge.c optional vnic fdt dev/vnic/nic_main.c optional vnic pci dev/vnic/nicvf_main.c optional vnic pci pci_iov dev/vnic/nicvf_queues.c optional vnic pci pci_iov dev/vnic/thunder_bgx_fdt.c optional vnic fdt dev/vnic/thunder_bgx.c optional vnic pci dev/vnic/thunder_mdio_fdt.c optional vnic fdt dev/vnic/thunder_mdio.c optional vnic dev/vnic/lmac_if.m optional inet | inet6 | vnic kern/kern_clocksource.c standard kern/msi_if.m optional intrng kern/pic_if.m optional intrng kern/subr_devmap.c standard kern/subr_intr.c optional intrng libkern/bcmp.c standard libkern/ffs.c standard libkern/ffsl.c standard libkern/ffsll.c standard libkern/fls.c standard libkern/flsl.c standard libkern/flsll.c standard libkern/memset.c standard libkern/arm64/crc32c_armv8.S standard cddl/contrib/opensolaris/common/atomic/aarch64/opensolaris_atomic.S optional zfs | dtrace compile-with "${CDDL_C}" cddl/dev/dtrace/aarch64/dtrace_asm.S optional dtrace compile-with "${DTRACE_S}" cddl/dev/dtrace/aarch64/dtrace_subr.c optional dtrace compile-with "${DTRACE_C}" cddl/dev/fbt/aarch64/fbt_isa.c optional dtrace_fbt | dtraceall compile-with "${FBT_C}" +arm64/rockchip/rk_i2c.c optional rk_i2c fdt soc_rockchip_rk3328 arm64/rockchip/rk_grf.c optional fdt soc_rockchip_rk3328 arm64/rockchip/rk_pinctrl.c optional fdt soc_rockchip_rk3328 arm64/rockchip/rk_gpio.c optional fdt soc_rockchip_rk3328 arm64/rockchip/clk/rk_cru.c optional fdt soc_rockchip_rk3328 arm64/rockchip/clk/rk_clk_armclk.c optional fdt soc_rockchip_rk3328 arm64/rockchip/clk/rk_clk_composite.c optional fdt soc_rockchip_rk3328 arm64/rockchip/clk/rk_clk_gate.c optional fdt soc_rockchip_rk3328 arm64/rockchip/clk/rk_clk_mux.c optional fdt soc_rockchip_rk3328 arm64/rockchip/clk/rk_clk_pll.c optional fdt soc_rockchip_rk3328 arm64/rockchip/clk/rk3328_cru.c optional fdt soc_rockchip_rk3328 arm64/rockchip/if_dwc_rk.c optional dwc_rk fdt soc_rockchip_rk3328 dev/dwc/if_dwc.c optional dwc_rk dev/dwc/if_dwc_if.m optional dwc_rk