Index: head/lib/libc/riscv/Makefile.inc =================================================================== --- head/lib/libc/riscv/Makefile.inc (revision 332791) +++ head/lib/libc/riscv/Makefile.inc (revision 332792) @@ -1,13 +1,9 @@ # $FreeBSD$ # # Machine dependent definitions for the RISC-V architecture. # -.if ${MACHINE_ARCH:Mriscv*sf} != "" -CFLAGS+=-DSOFTFLOAT -.endif - # Long double is quad precision GDTOASRCS+=strtorQ.c SRCS+=machdep_ldisQ.c SYM_MAPS+=${LIBC_SRCTOP}/riscv/Symbol.map Index: head/lib/libc/riscv/gen/_setjmp.S =================================================================== --- head/lib/libc/riscv/gen/_setjmp.S (revision 332791) +++ head/lib/libc/riscv/gen/_setjmp.S (revision 332792) @@ -1,145 +1,145 @@ /*- * Copyright (c) 2015-2016 Ruslan Bukin * All rights reserved. * * Portions of this software were developed by SRI International and the * University of Cambridge Computer Laboratory under DARPA/AFRL contract * FA8750-10-C-0237 ("CTSRD"), as part of the DARPA CRASH research programme. * * Portions of this software were developed by the University of Cambridge * Computer Laboratory as part of the CTSRD Project, with support from the * UK Higher Education Innovation Fund (HEIF). * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. */ #include __FBSDID("$FreeBSD$"); #include ENTRY(_setjmp) /* Store the magic value and stack pointer */ la t0, .Lmagic ld t0, 0(t0) sd t0, (0 * 8)(a0) sd sp, (1 * 8)(a0) addi a0, a0, (2 * 8) /* Store the general purpose registers and ra */ sd s0, (0 * 8)(a0) sd s1, (1 * 8)(a0) sd s2, (2 * 8)(a0) sd s3, (3 * 8)(a0) sd s4, (4 * 8)(a0) sd s5, (5 * 8)(a0) sd s6, (6 * 8)(a0) sd s7, (7 * 8)(a0) sd s8, (8 * 8)(a0) sd s9, (9 * 8)(a0) sd s10, (10 * 8)(a0) sd s11, (11 * 8)(a0) sd ra, (12 * 8)(a0) addi a0, a0, (13 * 8) -#if !defined(_STANDALONE) && !defined(SOFTFLOAT) +#if !defined(_STANDALONE) && defined(__riscv_float_abi_double) /* Store the fpe registers */ fsd fs0, (0 * 16)(a0) fsd fs1, (1 * 16)(a0) fsd fs2, (2 * 16)(a0) fsd fs3, (3 * 16)(a0) fsd fs4, (4 * 16)(a0) fsd fs5, (5 * 16)(a0) fsd fs6, (6 * 16)(a0) fsd fs7, (7 * 16)(a0) fsd fs8, (8 * 16)(a0) fsd fs9, (9 * 16)(a0) fsd fs10, (10 * 16)(a0) fsd fs11, (11 * 16)(a0) addi a0, a0, (12 * 16) #endif /* Return value */ li a0, 0 ret .align 3 .Lmagic: .quad _JB_MAGIC__SETJMP END(_setjmp) ENTRY(_longjmp) /* Check the magic value */ ld t0, 0(a0) la t1, .Lmagic ld t1, 0(t1) bne t0, t1, botch /* Restore the stack pointer */ ld t0, 8(a0) mv sp, t0 addi a0, a0, (2 * 8) /* Restore the general purpose registers and ra */ ld s0, (0 * 8)(a0) ld s1, (1 * 8)(a0) ld s2, (2 * 8)(a0) ld s3, (3 * 8)(a0) ld s4, (4 * 8)(a0) ld s5, (5 * 8)(a0) ld s6, (6 * 8)(a0) ld s7, (7 * 8)(a0) ld s8, (8 * 8)(a0) ld s9, (9 * 8)(a0) ld s10, (10 * 8)(a0) ld s11, (11 * 8)(a0) ld ra, (12 * 8)(a0) addi a0, a0, (13 * 8) -#if !defined(_STANDALONE) && !defined(SOFTFLOAT) +#if !defined(_STANDALONE) && defined(__riscv_float_abi_double) /* Restore the fpe registers */ fld fs0, (0 * 16)(a0) fld fs1, (1 * 16)(a0) fld fs2, (2 * 16)(a0) fld fs3, (3 * 16)(a0) fld fs4, (4 * 16)(a0) fld fs5, (5 * 16)(a0) fld fs6, (6 * 16)(a0) fld fs7, (7 * 16)(a0) fld fs8, (8 * 16)(a0) fld fs9, (9 * 16)(a0) fld fs10, (10 * 16)(a0) fld fs11, (11 * 16)(a0) addi a0, a0, (12 * 16) #endif /* Load the return value */ mv a0, a1 ret botch: #ifdef _STANDALONE j botch #else call _C_LABEL(longjmperror) call _C_LABEL(abort) #endif END(_longjmp) Index: head/lib/libc/riscv/gen/fabs.S =================================================================== --- head/lib/libc/riscv/gen/fabs.S (revision 332791) +++ head/lib/libc/riscv/gen/fabs.S (revision 332792) @@ -1,43 +1,43 @@ /*- * Copyright (c) 2015-2017 Ruslan Bukin * All rights reserved. * * Portions of this software were developed by SRI International and the * University of Cambridge Computer Laboratory under DARPA/AFRL contract * FA8750-10-C-0237 ("CTSRD"), as part of the DARPA CRASH research programme. * * Portions of this software were developed by the University of Cambridge * Computer Laboratory as part of the CTSRD Project, with support from the * UK Higher Education Innovation Fund (HEIF). * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. */ #include __FBSDID("$FreeBSD$"); -#ifndef SOFTFLOAT +#ifdef __riscv_float_abi_double ENTRY(fabs) fabs.d fa0, fa0 ret END(fabs) #endif Index: head/lib/libc/riscv/gen/flt_rounds.c =================================================================== --- head/lib/libc/riscv/gen/flt_rounds.c (revision 332791) +++ head/lib/libc/riscv/gen/flt_rounds.c (revision 332792) @@ -1,72 +1,72 @@ /*- * Copyright (c) 2015-2016 Ruslan Bukin * All rights reserved. * * Portions of this software were developed by SRI International and the * University of Cambridge Computer Laboratory under DARPA/AFRL contract * FA8750-10-C-0237 ("CTSRD"), as part of the DARPA CRASH research programme. * * Portions of this software were developed by the University of Cambridge * Computer Laboratory as part of the CTSRD Project, with support from the * UK Higher Education Innovation Fund (HEIF). * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. */ #include __FBSDID("$FreeBSD$"); #include #include #include -#ifdef SOFTFLOAT +#ifdef __riscv_float_abi_soft #include "softfloat-for-gcc.h" #include "milieu.h" #include "softfloat.h" #endif int __flt_rounds(void) { uint64_t mode; -#ifdef SOFTFLOAT +#ifdef __riscv_float_abi_soft mode = __softfloat_float_rounding_mode; #else __asm __volatile("csrr %0, fcsr" : "=r" (mode)); #endif switch (mode & _ROUND_MASK) { case FE_TOWARDZERO: return (0); case FE_TONEAREST: return (1); case FE_UPWARD: return (2); case FE_DOWNWARD: return (3); } return (-1); } Index: head/lib/libc/riscv/gen/setjmp.S =================================================================== --- head/lib/libc/riscv/gen/setjmp.S (revision 332791) +++ head/lib/libc/riscv/gen/setjmp.S (revision 332792) @@ -1,171 +1,171 @@ /*- * Copyright (c) 2015-2016 Ruslan Bukin * All rights reserved. * * Portions of this software were developed by SRI International and the * University of Cambridge Computer Laboratory under DARPA/AFRL contract * FA8750-10-C-0237 ("CTSRD"), as part of the DARPA CRASH research programme. * * Portions of this software were developed by the University of Cambridge * Computer Laboratory as part of the CTSRD Project, with support from the * UK Higher Education Innovation Fund (HEIF). * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. */ #include __FBSDID("$FreeBSD$"); #include ENTRY(setjmp) addi sp, sp, -(2 * 8) sd a0, 0(sp) sd ra, 8(sp) /* Store the signal mask */ addi a2, a0, (_JB_SIGMASK * 8) /* oset */ li a1, 0 /* set */ li a0, 1 /* SIG_BLOCK */ jal sigprocmask ld a0, 0(sp) ld ra, 8(sp) addi sp, sp, (2 * 8) /* Store the magic value and stack pointer */ la t0, .Lmagic ld t0, 0(t0) sd t0, (0 * 8)(a0) sd sp, (1 * 8)(a0) addi a0, a0, (2 * 8) /* Store the general purpose registers and ra */ sd s0, (0 * 8)(a0) sd s1, (1 * 8)(a0) sd s2, (2 * 8)(a0) sd s3, (3 * 8)(a0) sd s4, (4 * 8)(a0) sd s5, (5 * 8)(a0) sd s6, (6 * 8)(a0) sd s7, (7 * 8)(a0) sd s8, (8 * 8)(a0) sd s9, (9 * 8)(a0) sd s10, (10 * 8)(a0) sd s11, (11 * 8)(a0) sd ra, (12 * 8)(a0) addi a0, a0, (13 * 8) -#ifndef SOFTFLOAT +#ifdef __riscv_float_abi_double /* Store the fpe registers */ fsd fs0, (0 * 16)(a0) fsd fs1, (1 * 16)(a0) fsd fs2, (2 * 16)(a0) fsd fs3, (3 * 16)(a0) fsd fs4, (4 * 16)(a0) fsd fs5, (5 * 16)(a0) fsd fs6, (6 * 16)(a0) fsd fs7, (7 * 16)(a0) fsd fs8, (8 * 16)(a0) fsd fs9, (9 * 16)(a0) fsd fs10, (10 * 16)(a0) fsd fs11, (11 * 16)(a0) addi a0, a0, (12 * 16) #endif /* Return value */ li a0, 0 ret .align 3 .Lmagic: .quad _JB_MAGIC_SETJMP END(setjmp) ENTRY(longjmp) addi sp, sp, -(4 * 8) sd a0, (0 * 8)(sp) sd ra, (1 * 8)(sp) sd a1, (2 * 8)(sp) /* Restore the signal mask */ li a2, 0 /* oset */ addi a1, a0, (_JB_SIGMASK * 8) /* set */ li a0, 3 /* SIG_BLOCK */ jal sigprocmask ld a1, (2 * 8)(sp) ld ra, (1 * 8)(sp) ld a0, (0 * 8)(sp) addi sp, sp, (4 * 8) /* Check the magic value */ ld t0, 0(a0) la t1, .Lmagic ld t1, 0(t1) bne t0, t1, botch /* Restore the stack pointer */ ld t0, 8(a0) mv sp, t0 addi a0, a0, (2 * 8) /* Restore the general purpose registers and ra */ ld s0, (0 * 8)(a0) ld s1, (1 * 8)(a0) ld s2, (2 * 8)(a0) ld s3, (3 * 8)(a0) ld s4, (4 * 8)(a0) ld s5, (5 * 8)(a0) ld s6, (6 * 8)(a0) ld s7, (7 * 8)(a0) ld s8, (8 * 8)(a0) ld s9, (9 * 8)(a0) ld s10, (10 * 8)(a0) ld s11, (11 * 8)(a0) ld ra, (12 * 8)(a0) addi a0, a0, (13 * 8) -#ifndef SOFTFLOAT +#ifdef __riscv_float_abi_double /* Restore the fpe registers */ fld fs0, (0 * 16)(a0) fld fs1, (1 * 16)(a0) fld fs2, (2 * 16)(a0) fld fs3, (3 * 16)(a0) fld fs4, (4 * 16)(a0) fld fs5, (5 * 16)(a0) fld fs6, (6 * 16)(a0) fld fs7, (7 * 16)(a0) fld fs8, (8 * 16)(a0) fld fs9, (9 * 16)(a0) fld fs10, (10 * 16)(a0) fld fs11, (11 * 16)(a0) addi a0, a0, (12 * 16) #endif /* Load the return value */ mv a0, a1 ret botch: call _C_LABEL(longjmperror) call _C_LABEL(abort) END(longjmp) Index: head/lib/msun/riscv/Makefile.inc =================================================================== --- head/lib/msun/riscv/Makefile.inc (revision 332791) +++ head/lib/msun/riscv/Makefile.inc (revision 332792) @@ -1,8 +1,4 @@ # $FreeBSD$ -.if ${MACHINE_ARCH:Mriscv*sf} != "" -CFLAGS+=-DSOFTFLOAT -.endif - LDBL_PREC = 113 SYM_MAPS += ${.CURDIR}/riscv/Symbol.map Index: head/lib/msun/riscv/fenv.c =================================================================== --- head/lib/msun/riscv/fenv.c (revision 332791) +++ head/lib/msun/riscv/fenv.c (revision 332792) @@ -1,63 +1,63 @@ /*- * Copyright (c) 2004 David Schultz * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. * * $FreeBSD$ */ #define __fenv_static #include "fenv.h" #ifdef __GNUC_GNU_INLINE__ #error "This file must be compiled with C99 'inline' semantics" #endif /* * Hopefully the system ID byte is immutable, so it's valid to use * this as a default environment. */ const fenv_t __fe_dfl_env = 0; -#ifdef SOFTFLOAT +#ifdef __riscv_float_abi_soft #define __set_env(env, flags, mask, rnd) env = ((flags) | (rnd) << 5) #define __env_flags(env) ((env) & FE_ALL_EXCEPT) #define __env_mask(env) (0) /* No exception traps. */ #define __env_round(env) (((env) >> 5) & _ROUND_MASK) #include "fenv-softfloat.h" #endif extern inline int feclearexcept(int __excepts); extern inline int fegetexceptflag(fexcept_t *__flagp, int __excepts); extern inline int fesetexceptflag(const fexcept_t *__flagp, int __excepts); extern inline int feraiseexcept(int __excepts); extern inline int fetestexcept(int __excepts); extern inline int fegetround(void); extern inline int fesetround(int __round); extern inline int fegetenv(fenv_t *__envp); extern inline int feholdexcept(fenv_t *__envp); extern inline int fesetenv(const fenv_t *__envp); extern inline int feupdateenv(const fenv_t *__envp); extern inline int feenableexcept(int __mask); extern inline int fedisableexcept(int __mask); extern inline int fegetexcept(void); Index: head/lib/msun/riscv/fenv.h =================================================================== --- head/lib/msun/riscv/fenv.h (revision 332791) +++ head/lib/msun/riscv/fenv.h (revision 332792) @@ -1,252 +1,260 @@ /*- * Copyright (c) 2004-2005 David Schultz * Copyright (c) 2015-2016 Ruslan Bukin * All rights reserved. * * Portions of this software were developed by SRI International and the * University of Cambridge Computer Laboratory under DARPA/AFRL contract * FA8750-10-C-0237 ("CTSRD"), as part of the DARPA CRASH research programme. * * Portions of this software were developed by the University of Cambridge * Computer Laboratory as part of the CTSRD Project, with support from the * UK Higher Education Innovation Fund (HEIF). * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. * * $FreeBSD$ */ #ifndef _FENV_H_ #define _FENV_H_ #include #ifndef __fenv_static #define __fenv_static static #endif typedef __uint64_t fenv_t; typedef __uint64_t fexcept_t; /* Exception flags */ #define FE_INVALID 0x0010 #define FE_DIVBYZERO 0x0008 #define FE_OVERFLOW 0x0004 #define FE_UNDERFLOW 0x0002 #define FE_INEXACT 0x0001 #define FE_ALL_EXCEPT (FE_DIVBYZERO | FE_INEXACT | \ FE_INVALID | FE_OVERFLOW | FE_UNDERFLOW) /* * RISC-V Rounding modes */ #define _ROUND_SHIFT 5 #define FE_TONEAREST (0x00 << _ROUND_SHIFT) #define FE_TOWARDZERO (0x01 << _ROUND_SHIFT) #define FE_DOWNWARD (0x02 << _ROUND_SHIFT) #define FE_UPWARD (0x03 << _ROUND_SHIFT) #define _ROUND_MASK (FE_TONEAREST | FE_DOWNWARD | \ FE_UPWARD | FE_TOWARDZERO) __BEGIN_DECLS /* Default floating-point environment */ extern const fenv_t __fe_dfl_env; #define FE_DFL_ENV (&__fe_dfl_env) -#ifndef SOFTFLOAT +#if !defined(__riscv_float_abi_soft) && !defined(__riscv_float_abi_double) +#if defined(__riscv_float_abi_single) +#error single precision floating point ABI not supported +#else +#error compiler did not set soft/hard float macros +#endif +#endif + +#ifndef __riscv_float_abi_soft #define __rfs(__fcsr) __asm __volatile("csrr %0, fcsr" : "=r" (__fcsr)) #define __wfs(__fcsr) __asm __volatile("csrw fcsr, %0" :: "r" (__fcsr)) #endif -#ifdef SOFTFLOAT +#ifdef __riscv_float_abi_soft int feclearexcept(int __excepts); int fegetexceptflag(fexcept_t *__flagp, int __excepts); int fesetexceptflag(const fexcept_t *__flagp, int __excepts); int feraiseexcept(int __excepts); int fetestexcept(int __excepts); int fegetround(void); int fesetround(int __round); int fegetenv(fenv_t *__envp); int feholdexcept(fenv_t *__envp); int fesetenv(const fenv_t *__envp); int feupdateenv(const fenv_t *__envp); #else __fenv_static inline int feclearexcept(int __excepts) { __asm __volatile("csrc fflags, %0" :: "r"(__excepts)); return (0); } __fenv_static inline int fegetexceptflag(fexcept_t *__flagp, int __excepts) { fexcept_t __fcsr; __rfs(__fcsr); *__flagp = __fcsr & __excepts; return (0); } __fenv_static inline int fesetexceptflag(const fexcept_t *__flagp, int __excepts) { fexcept_t __fcsr; __fcsr = *__flagp; __asm __volatile("csrc fflags, %0" :: "r"(__excepts)); __asm __volatile("csrs fflags, %0" :: "r"(__fcsr & __excepts)); return (0); } __fenv_static inline int feraiseexcept(int __excepts) { __asm __volatile("csrs fflags, %0" :: "r"(__excepts)); return (0); } __fenv_static inline int fetestexcept(int __excepts) { fexcept_t __fcsr; __rfs(__fcsr); return (__fcsr & __excepts); } __fenv_static inline int fegetround(void) { fexcept_t __fcsr; __rfs(__fcsr); return (__fcsr & _ROUND_MASK); } __fenv_static inline int fesetround(int __round) { fexcept_t __fcsr; if (__round & ~_ROUND_MASK) return (-1); __rfs(__fcsr); __fcsr &= ~_ROUND_MASK; __fcsr |= __round; __wfs(__fcsr); return (0); } __fenv_static inline int fegetenv(fenv_t *__envp) { __rfs(*__envp); return (0); } __fenv_static inline int feholdexcept(fenv_t *__envp) { /* No exception traps. */ return (-1); } __fenv_static inline int fesetenv(const fenv_t *__envp) { __wfs(*__envp); return (0); } __fenv_static inline int feupdateenv(const fenv_t *__envp) { fexcept_t __fcsr; __rfs(__fcsr); __wfs(*__envp); feraiseexcept(__fcsr & FE_ALL_EXCEPT); return (0); } -#endif /* !SOFTFLOAT */ +#endif /* !__riscv_float_abi_soft */ #if __BSD_VISIBLE /* We currently provide no external definitions of the functions below. */ -#ifdef SOFTFLOAT +#ifdef __riscv_float_abi_soft int feenableexcept(int __mask); int fedisableexcept(int __mask); int fegetexcept(void); #else static inline int feenableexcept(int __mask) { /* No exception traps. */ return (-1); } static inline int fedisableexcept(int __mask) { /* No exception traps. */ return (0); } static inline int fegetexcept(void) { /* No exception traps. */ return (0); } -#endif /* !SOFTFLOAT */ +#endif /* !__riscv_float_abi_soft */ #endif /* __BSD_VISIBLE */ __END_DECLS #endif /* !_FENV_H_ */