Index: head/sys/arm/mv/armada/wdt.c =================================================================== --- head/sys/arm/mv/armada/wdt.c (revision 332010) +++ head/sys/arm/mv/armada/wdt.c (revision 332011) @@ -1,371 +1,378 @@ /*- * Copyright (c) 2006 Benno Rice. * Copyright (C) 2007-2008 MARVELL INTERNATIONAL LTD. * All rights reserved. * * Adapted to Marvell SoC by Semihalf. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * * from: FreeBSD: //depot/projects/arm/src/sys/arm/xscale/pxa2x0/pxa2x0_timer.c, rev 1 */ #include __FBSDID("$FreeBSD$"); #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #define INITIAL_TIMECOUNTER (0xffffffff) #define MAX_WATCHDOG_TICKS (0xffffffff) #define WD_RST_OUT_EN 0x00000002 #define MV_CLOCK_SRC_ARMV7 25000000 /* Timers' 25MHz mode */ struct mv_wdt_config { enum soc_family wdt_soc; uint32_t wdt_timer; void (*wdt_enable)(void); void (*wdt_disable)(void); unsigned int wdt_clock_src; }; static void mv_wdt_enable_armv5(void); static void mv_wdt_enable_armada_38x(void); static void mv_wdt_enable_armada_xp(void); static void mv_wdt_disable_armv5(void); static void mv_wdt_disable_armada_38x(void); static void mv_wdt_disable_armada_xp(void); static struct mv_wdt_config mv_wdt_armada_38x_config = { .wdt_soc = MV_SOC_ARMADA_38X, .wdt_timer = 4, .wdt_enable = &mv_wdt_enable_armada_38x, .wdt_disable = &mv_wdt_disable_armada_38x, .wdt_clock_src = MV_CLOCK_SRC_ARMV7, }; static struct mv_wdt_config mv_wdt_armada_xp_config = { .wdt_soc = MV_SOC_ARMADA_XP, .wdt_timer = 2, .wdt_enable = &mv_wdt_enable_armada_xp, .wdt_disable = &mv_wdt_disable_armada_xp, .wdt_clock_src = MV_CLOCK_SRC_ARMV7, }; static struct mv_wdt_config mv_wdt_armv5_config = { .wdt_soc = MV_SOC_ARMV5, .wdt_timer = 2, .wdt_enable = &mv_wdt_enable_armv5, .wdt_disable = &mv_wdt_disable_armv5, .wdt_clock_src = 0, }; struct mv_wdt_softc { struct resource * wdt_res; struct mtx wdt_mtx; struct mv_wdt_config * wdt_config; }; static struct resource_spec mv_wdt_spec[] = { { SYS_RES_MEMORY, 0, RF_ACTIVE }, { -1, 0 } }; static struct ofw_compat_data mv_wdt_compat[] = { {"marvell,armada-380-wdt", (uintptr_t)&mv_wdt_armada_38x_config}, {"marvell,armada-xp-wdt", (uintptr_t)&mv_wdt_armada_xp_config}, {"marvell,orion-wdt", (uintptr_t)&mv_wdt_armv5_config}, {NULL, (uintptr_t)NULL} }; static struct mv_wdt_softc *wdt_softc = NULL; int timers_initialized = 0; static int mv_wdt_probe(device_t); static int mv_wdt_attach(device_t); static uint32_t mv_get_timer_control(void); static void mv_set_timer_control(uint32_t); static void mv_set_timer(uint32_t, uint32_t); static void mv_watchdog_event(void *, unsigned int, int *); static device_method_t mv_wdt_methods[] = { DEVMETHOD(device_probe, mv_wdt_probe), DEVMETHOD(device_attach, mv_wdt_attach), { 0, 0 } }; static driver_t mv_wdt_driver = { "wdt", mv_wdt_methods, sizeof(struct mv_wdt_softc), }; static devclass_t mv_wdt_devclass; DRIVER_MODULE(wdt, simplebus, mv_wdt_driver, mv_wdt_devclass, 0, 0); static int mv_wdt_probe(device_t dev) { if (!ofw_bus_status_okay(dev)) return (ENXIO); if (!ofw_bus_search_compatible(dev, mv_wdt_compat)->ocd_data) return (ENXIO); device_set_desc(dev, "Marvell Watchdog Timer"); return (0); } static int mv_wdt_attach(device_t dev) { struct mv_wdt_softc *sc; int error; if (wdt_softc != NULL) return (ENXIO); sc = device_get_softc(dev); wdt_softc = sc; error = bus_alloc_resources(dev, mv_wdt_spec, &sc->wdt_res); if (error) { device_printf(dev, "could not allocate resources\n"); return (ENXIO); } mtx_init(&sc->wdt_mtx, "watchdog", NULL, MTX_DEF); sc->wdt_config = (struct mv_wdt_config *) ofw_bus_search_compatible(dev, mv_wdt_compat)->ocd_data; if (sc->wdt_config->wdt_clock_src == 0) sc->wdt_config->wdt_clock_src = get_tclk(); if (wdt_softc->wdt_config->wdt_disable != NULL) wdt_softc->wdt_config->wdt_disable(); EVENTHANDLER_REGISTER(watchdog_list, mv_watchdog_event, sc, 0); return (0); } static __inline uint32_t mv_get_timer_control(void) { return (bus_read_4(wdt_softc->wdt_res, CPU_TIMER_CONTROL)); } static __inline void mv_set_timer_control(uint32_t val) { bus_write_4(wdt_softc->wdt_res, CPU_TIMER_CONTROL, val); } static __inline void mv_set_timer(uint32_t timer, uint32_t val) { bus_write_4(wdt_softc->wdt_res, CPU_TIMER0 + timer * 0x8, val); } static void mv_wdt_enable_armv5(void) { uint32_t val, irq_cause, irq_mask; irq_cause = read_cpu_ctrl(BRIDGE_IRQ_CAUSE); irq_cause &= IRQ_TIMER_WD_CLR; write_cpu_ctrl(BRIDGE_IRQ_CAUSE, irq_cause); irq_mask = read_cpu_ctrl(BRIDGE_IRQ_MASK); irq_mask |= IRQ_TIMER_WD_MASK; write_cpu_ctrl(BRIDGE_IRQ_MASK, irq_mask); val = read_cpu_ctrl(RSTOUTn_MASK); val |= WD_RST_OUT_EN; write_cpu_ctrl(RSTOUTn_MASK, val); val = mv_get_timer_control(); val |= CPU_TIMER2_EN | CPU_TIMER2_AUTO; mv_set_timer_control(val); } static inline void mv_wdt_enable_armada_38x_xp_helper() { uint32_t val, irq_cause; irq_cause = read_cpu_ctrl(BRIDGE_IRQ_CAUSE); irq_cause &= IRQ_TIMER_WD_CLR; write_cpu_ctrl(BRIDGE_IRQ_CAUSE, irq_cause); val = read_cpu_mp_clocks(WD_RSTOUTn_MASK); val |= (WD_GLOBAL_MASK | WD_CPU0_MASK); write_cpu_mp_clocks(WD_RSTOUTn_MASK, val); val = read_cpu_misc(RSTOUTn_MASK_ARMV7); val &= ~RSTOUTn_MASK_WD; write_cpu_misc(RSTOUTn_MASK_ARMV7, val); } static void mv_wdt_enable_armada_38x(void) { - uint32_t val; + uint32_t val, irq_cause; + irq_cause = read_cpu_ctrl(BRIDGE_IRQ_CAUSE); + irq_cause &= IRQ_TIMER_WD_CLR; + write_cpu_ctrl(BRIDGE_IRQ_CAUSE, irq_cause); + mv_wdt_enable_armada_38x_xp_helper(); val = mv_get_timer_control(); val |= CPU_TIMER_WD_EN | CPU_TIMER_WD_AUTO | CPU_TIMER_WD_25MHZ_EN; mv_set_timer_control(val); } static void mv_wdt_enable_armada_xp(void) { - uint32_t val; + uint32_t val, irq_cause; + irq_cause = read_cpu_ctrl(BRIDGE_IRQ_CAUSE_ARMADAXP); + irq_cause &= IRQ_TIMER_WD_CLR_ARMADAXP; + write_cpu_ctrl(BRIDGE_IRQ_CAUSE_ARMADAXP, irq_cause); mv_wdt_enable_armada_38x_xp_helper(); val = mv_get_timer_control(); val |= CPU_TIMER2_EN | CPU_TIMER2_AUTO | CPU_TIMER_WD_25MHZ_EN; mv_set_timer_control(val); } static void mv_wdt_disable_armv5(void) { uint32_t val, irq_cause, irq_mask; val = mv_get_timer_control(); val &= ~(CPU_TIMER2_EN | CPU_TIMER2_AUTO); mv_set_timer_control(val); val = read_cpu_ctrl(RSTOUTn_MASK); val &= ~WD_RST_OUT_EN; write_cpu_ctrl(RSTOUTn_MASK, val); irq_mask = read_cpu_ctrl(BRIDGE_IRQ_MASK); irq_mask &= ~(IRQ_TIMER_WD_MASK); write_cpu_ctrl(BRIDGE_IRQ_MASK, irq_mask); irq_cause = read_cpu_ctrl(BRIDGE_IRQ_CAUSE); irq_cause &= IRQ_TIMER_WD_CLR; write_cpu_ctrl(BRIDGE_IRQ_CAUSE, irq_cause); } static __inline void mv_wdt_disable_armada_38x_xp_helper(void) { uint32_t val; val = read_cpu_mp_clocks(WD_RSTOUTn_MASK); val &= ~(WD_GLOBAL_MASK | WD_CPU0_MASK); write_cpu_mp_clocks(WD_RSTOUTn_MASK, val); val = read_cpu_misc(RSTOUTn_MASK_ARMV7); val |= RSTOUTn_MASK_WD; write_cpu_misc(RSTOUTn_MASK_ARMV7, RSTOUTn_MASK_WD); } static void mv_wdt_disable_armada_38x(void) { uint32_t val; val = mv_get_timer_control(); val &= ~(CPU_TIMER_WD_EN | CPU_TIMER_WD_AUTO); mv_set_timer_control(val); mv_wdt_disable_armada_38x_xp_helper(); } static void mv_wdt_disable_armada_xp(void) { uint32_t val; val = mv_get_timer_control(); val &= ~(CPU_TIMER2_EN | CPU_TIMER2_AUTO); mv_set_timer_control(val); mv_wdt_disable_armada_38x_xp_helper(); } /* * Watchdog event handler. */ static void mv_watchdog_event(void *arg, unsigned int cmd, int *error) { struct mv_wdt_softc *sc; uint64_t ns; uint64_t ticks; sc = arg; mtx_lock(&sc->wdt_mtx); if (cmd == 0) { if (wdt_softc->wdt_config->wdt_disable != NULL) wdt_softc->wdt_config->wdt_disable(); } else { /* * Watchdog timeout is in nanosecs, calculation according to * watchdog(9) */ ns = (uint64_t)1 << (cmd & WD_INTERVAL); ticks = (uint64_t)(ns * sc->wdt_config->wdt_clock_src) / 1000000000; if (ticks > MAX_WATCHDOG_TICKS) { if (wdt_softc->wdt_config->wdt_disable != NULL) wdt_softc->wdt_config->wdt_disable(); } else { mv_set_timer(wdt_softc->wdt_config->wdt_timer, ticks); if (wdt_softc->wdt_config->wdt_enable != NULL) wdt_softc->wdt_config->wdt_enable(); *error = 0; } } mtx_unlock(&sc->wdt_mtx); } Index: head/sys/arm/mv/mvreg.h =================================================================== --- head/sys/arm/mv/mvreg.h (revision 332010) +++ head/sys/arm/mv/mvreg.h (revision 332011) @@ -1,450 +1,450 @@ /*- * SPDX-License-Identifier: BSD-3-Clause * * Copyright (C) 2007-2011 MARVELL INTERNATIONAL LTD. * All rights reserved. * * Developed by Semihalf. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * 3. Neither the name of MARVELL nor the names of contributors * may be used to endorse or promote products derived from this software * without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. * * $FreeBSD$ */ #ifndef _MVREG_H_ #define _MVREG_H_ #include #if defined(SOC_MV_DISCOVERY) #define IRQ_CAUSE_ERROR 0x0 #define IRQ_CAUSE 0x4 #define IRQ_CAUSE_HI 0x8 #define IRQ_MASK_ERROR 0xC #define IRQ_MASK 0x10 #define IRQ_MASK_HI 0x14 #define IRQ_CAUSE_SELECT 0x18 #define FIQ_MASK_ERROR 0x1C #define FIQ_MASK 0x20 #define FIQ_MASK_HI 0x24 #define FIQ_CAUSE_SELECT 0x28 #define ENDPOINT_IRQ_MASK_ERROR(n) 0x2C #define ENDPOINT_IRQ_MASK(n) 0x30 #define ENDPOINT_IRQ_MASK_HI(n) 0x34 #define ENDPOINT_IRQ_CAUSE_SELECT 0x38 #else #define IRQ_CAUSE 0x0 #define IRQ_MASK 0x4 #define FIQ_MASK 0x8 #define ENDPOINT_IRQ_MASK(n) 0xC #define IRQ_CAUSE_HI 0x10 #define IRQ_MASK_HI 0x14 #define FIQ_MASK_HI 0x18 #define ENDPOINT_IRQ_MASK_HI(n) 0x1C #define ENDPOINT_IRQ_MASK_ERROR(n) (-1) #define IRQ_CAUSE_ERROR (-1) /* Fake defines for unified */ #define IRQ_MASK_ERROR (-1) /* interrupt controller code */ #endif #define MAIN_IRQ_NUM 116 #define ERR_IRQ_NUM 32 #define ERR_IRQ (MAIN_IRQ_NUM) #define MSI_IRQ (ERR_IRQ + ERR_IRQ_NUM) #define MSI_IRQ_NUM 32 #define IRQ_CPU_SELF 0x00000001 -#if defined(SOC_MV_ARMADAXP) -#define BRIDGE_IRQ_CAUSE 0x68 -#define IRQ_TIMER0 0x00000001 -#define IRQ_TIMER1 0x00000002 -#define IRQ_TIMER_WD 0x00000004 -#else +#define BRIDGE_IRQ_CAUSE_ARMADAXP 0x68 +#define IRQ_TIMER0_ARMADAXP 0x00000001 +#define IRQ_TIMER1_ARMADAXP 0x00000002 +#define IRQ_TIMER_WD_ARMADAXP 0x00000004 + #define BRIDGE_IRQ_CAUSE 0x10 #define IRQ_CPU_SELF 0x00000001 #define IRQ_TIMER0 0x00000002 #define IRQ_TIMER1 0x00000004 #define IRQ_TIMER_WD 0x00000008 -#endif #define BRIDGE_IRQ_MASK 0x14 #define IRQ_CPU_MASK 0x00000001 #define IRQ_TIMER0_MASK 0x00000002 #define IRQ_TIMER1_MASK 0x00000004 #define IRQ_TIMER_WD_MASK 0x00000008 #define IRQ_CPU_SELF_CLR (~IRQ_CPU_SELF) #define IRQ_TIMER0_CLR (~IRQ_TIMER0) -#define IRQ_TIMER1_CLR (~IRQ_TIMER1) #define IRQ_TIMER_WD_CLR (~IRQ_TIMER_WD) + +#define IRQ_TIMER0_CLR_ARMADAXP (~IRQ_TIMER0_ARMADAXP) +#define IRQ_TIMER_WD_CLR_ARMADAXP (~IRQ_TIMER_WD_ARMADAXP) /* * System reset */ #define RSTOUTn_MASK_ARMV7 0x60 #define SYSTEM_SOFT_RESET_ARMV7 0x64 #define SOFT_RST_OUT_EN_ARMV7 0x00000001 #define SYS_SOFT_RST_ARMV7 0x00000001 #define RSTOUTn_MASK 0x8 #define SOFT_RST_OUT_EN 0x00000004 #define SYSTEM_SOFT_RESET 0xc #define SYS_SOFT_RST 0x00000001 #define RSTOUTn_MASK_WD 0x400 #define WD_RSTOUTn_MASK 0x4 #define WD_GLOBAL_MASK 0x00000100 #define WD_CPU0_MASK 0x00000001 #define WD_RST_OUT_EN 0x00000002 /* * Power Control */ #if defined(SOC_MV_KIRKWOOD) #define CPU_PM_CTRL 0x18 #else #define CPU_PM_CTRL 0x1C #endif #define CPU_PM_CTRL_NONE 0 #define CPU_PM_CTRL_ALL ~0x0 #if defined(SOC_MV_KIRKWOOD) #define CPU_PM_CTRL_GE0 (1 << 0) #define CPU_PM_CTRL_PEX0_PHY (1 << 1) #define CPU_PM_CTRL_PEX0 (1 << 2) #define CPU_PM_CTRL_USB0 (1 << 3) #define CPU_PM_CTRL_SDIO (1 << 4) #define CPU_PM_CTRL_TSU (1 << 5) #define CPU_PM_CTRL_DUNIT (1 << 6) #define CPU_PM_CTRL_RUNIT (1 << 7) #define CPU_PM_CTRL_XOR0 (1 << 8) #define CPU_PM_CTRL_AUDIO (1 << 9) #define CPU_PM_CTRL_SATA0 (1 << 14) #define CPU_PM_CTRL_SATA1 (1 << 15) #define CPU_PM_CTRL_XOR1 (1 << 16) #define CPU_PM_CTRL_CRYPTO (1 << 17) #define CPU_PM_CTRL_GE1 (1 << 19) #define CPU_PM_CTRL_TDM (1 << 20) #define CPU_PM_CTRL_XOR (CPU_PM_CTRL_XOR0 | CPU_PM_CTRL_XOR1) #define CPU_PM_CTRL_USB(u) (CPU_PM_CTRL_USB0) #define CPU_PM_CTRL_SATA (CPU_PM_CTRL_SATA0 | CPU_PM_CTRL_SATA1) #define CPU_PM_CTRL_GE(u) (CPU_PM_CTRL_GE1 * (u) | CPU_PM_CTRL_GE0 * \ (1 - (u))) #define CPU_PM_CTRL_IDMA (CPU_PM_CTRL_NONE) #elif defined(SOC_MV_DISCOVERY) #define CPU_PM_CTRL_GE0 (1 << 1) #define CPU_PM_CTRL_GE1 (1 << 2) #define CPU_PM_CTRL_PEX00 (1 << 5) #define CPU_PM_CTRL_PEX01 (1 << 6) #define CPU_PM_CTRL_PEX02 (1 << 7) #define CPU_PM_CTRL_PEX03 (1 << 8) #define CPU_PM_CTRL_PEX10 (1 << 9) #define CPU_PM_CTRL_PEX11 (1 << 10) #define CPU_PM_CTRL_PEX12 (1 << 11) #define CPU_PM_CTRL_PEX13 (1 << 12) #define CPU_PM_CTRL_SATA0_PHY (1 << 13) #define CPU_PM_CTRL_SATA0 (1 << 14) #define CPU_PM_CTRL_SATA1_PHY (1 << 15) #define CPU_PM_CTRL_SATA1 (1 << 16) #define CPU_PM_CTRL_USB0 (1 << 17) #define CPU_PM_CTRL_USB1 (1 << 18) #define CPU_PM_CTRL_USB2 (1 << 19) #define CPU_PM_CTRL_IDMA (1 << 20) #define CPU_PM_CTRL_XOR (1 << 21) #define CPU_PM_CTRL_CRYPTO (1 << 22) #define CPU_PM_CTRL_DEVICE (1 << 23) #define CPU_PM_CTRL_USB(u) (1 << (17 + (u))) #define CPU_PM_CTRL_SATA (CPU_PM_CTRL_SATA0 | CPU_PM_CTRL_SATA1) #define CPU_PM_CTRL_GE(u) (CPU_PM_CTRL_GE1 * (u) | CPU_PM_CTRL_GE0 * \ (1 - (u))) #else #define CPU_PM_CTRL_CRYPTO (CPU_PM_CTRL_NONE) #define CPU_PM_CTRL_IDMA (CPU_PM_CTRL_NONE) #define CPU_PM_CTRL_XOR (CPU_PM_CTRL_NONE) #define CPU_PM_CTRL_SATA (CPU_PM_CTRL_NONE) #define CPU_PM_CTRL_USB(u) (CPU_PM_CTRL_NONE) #define CPU_PM_CTRL_GE(u) (CPU_PM_CTRL_NONE) #endif /* * Timers */ #define CPU_TIMERS_BASE 0x300 #define CPU_TIMER_CONTROL 0x0 #define CPU_TIMER0_EN 0x00000001 #define CPU_TIMER0_AUTO 0x00000002 #define CPU_TIMER1_EN 0x00000004 #define CPU_TIMER1_AUTO 0x00000008 #define CPU_TIMER2_EN 0x00000010 #define CPU_TIMER2_AUTO 0x00000020 #define CPU_TIMER_WD_EN 0x00000100 #define CPU_TIMER_WD_AUTO 0x00000200 /* 25MHz mode is Armada XP - specific */ #define CPU_TIMER_WD_25MHZ_EN 0x00000400 #define CPU_TIMER0_25MHZ_EN 0x00000800 #define CPU_TIMER1_25MHZ_EN 0x00001000 #define CPU_TIMER0_REL 0x10 #define CPU_TIMER0 0x14 /* * SATA */ #define SATA_CHAN_NUM 2 #define EDMA_REGISTERS_OFFSET 0x2000 #define EDMA_REGISTERS_SIZE 0x2000 #define SATA_EDMA_BASE(ch) (EDMA_REGISTERS_OFFSET + \ ((ch) * EDMA_REGISTERS_SIZE)) /* SATAHC registers */ #define SATA_CR 0x000 /* Configuration Reg. */ #define SATA_CR_NODMABS (1 << 8) #define SATA_CR_NOEDMABS (1 << 9) #define SATA_CR_NOPRDPBS (1 << 10) #define SATA_CR_COALDIS(ch) (1 << (24 + ch)) /* Interrupt Coalescing Threshold Reg. */ #define SATA_ICTR 0x00C #define SATA_ICTR_MAX ((1 << 8) - 1) /* Interrupt Time Threshold Reg. */ #define SATA_ITTR 0x010 #define SATA_ITTR_MAX ((1 << 24) - 1) #define SATA_ICR 0x014 /* Interrupt Cause Reg. */ #define SATA_ICR_DMADONE(ch) (1 << (ch)) #define SATA_ICR_COAL (1 << 4) #define SATA_ICR_DEV(ch) (1 << (8 + ch)) #define SATA_MICR 0x020 /* Main Interrupt Cause Reg. */ #define SATA_MICR_ERR(ch) (1 << (2 * ch)) #define SATA_MICR_DONE(ch) (1 << ((2 * ch) + 1)) #define SATA_MICR_DMADONE(ch) (1 << (4 + ch)) #define SATA_MICR_COAL (1 << 8) #define SATA_MIMR 0x024 /* Main Interrupt Mask Reg. */ /* Shadow registers */ #define SATA_SHADOWR_BASE(ch) (SATA_EDMA_BASE(ch) + 0x100) #define SATA_SHADOWR_CONTROL(ch) (SATA_EDMA_BASE(ch) + 0x120) /* SATA registers */ #define SATA_SATA_SSTATUS(ch) (SATA_EDMA_BASE(ch) + 0x300) #define SATA_SATA_SERROR(ch) (SATA_EDMA_BASE(ch) + 0x304) #define SATA_SATA_SCONTROL(ch) (SATA_EDMA_BASE(ch) + 0x308) #define SATA_SATA_FISICR(ch) (SATA_EDMA_BASE(ch) + 0x364) /* EDMA registers */ #define SATA_EDMA_CFG(ch) (SATA_EDMA_BASE(ch) + 0x000) #define SATA_EDMA_CFG_QL128 (1 << 19) #define SATA_EDMA_CFG_HQCACHE (1 << 22) #define SATA_EDMA_IECR(ch) (SATA_EDMA_BASE(ch) + 0x008) #define SATA_EDMA_IEMR(ch) (SATA_EDMA_BASE(ch) + 0x00C) #define SATA_EDMA_REQBAHR(ch) (SATA_EDMA_BASE(ch) + 0x010) #define SATA_EDMA_REQIPR(ch) (SATA_EDMA_BASE(ch) + 0x014) #define SATA_EDMA_REQOPR(ch) (SATA_EDMA_BASE(ch) + 0x018) #define SATA_EDMA_RESBAHR(ch) (SATA_EDMA_BASE(ch) + 0x01C) #define SATA_EDMA_RESIPR(ch) (SATA_EDMA_BASE(ch) + 0x020) #define SATA_EDMA_RESOPR(ch) (SATA_EDMA_BASE(ch) + 0x024) #define SATA_EDMA_CMD(ch) (SATA_EDMA_BASE(ch) + 0x028) #define SATA_EDMA_CMD_ENABLE (1 << 0) #define SATA_EDMA_CMD_DISABLE (1 << 1) #define SATA_EDMA_CMD_RESET (1 << 2) #define SATA_EDMA_STATUS(ch) (SATA_EDMA_BASE(ch) + 0x030) #define SATA_EDMA_STATUS_IDLE (1 << 7) /* Offset to extract input slot from REQIPR register */ #define SATA_EDMA_REQIS_OFS 5 /* Offset to extract input slot from RESOPR register */ #define SATA_EDMA_RESOS_OFS 3 /* * GPIO */ #define GPIO_DATA_OUT 0x00 #define GPIO_DATA_OUT_EN_CTRL 0x04 #define GPIO_BLINK_EN 0x08 #define GPIO_DATA_IN_POLAR 0x0c #define GPIO_DATA_IN 0x10 #define GPIO_INT_CAUSE 0x14 #define GPIO_INT_EDGE_MASK 0x18 #define GPIO_INT_LEV_MASK 0x1c #define GPIO_HI_DATA_OUT 0x40 #define GPIO_HI_DATA_OUT_EN_CTRL 0x44 #define GPIO_HI_BLINK_EN 0x48 #define GPIO_HI_DATA_IN_POLAR 0x4c #define GPIO_HI_DATA_IN 0x50 #define GPIO_HI_INT_CAUSE 0x54 #define GPIO_HI_INT_EDGE_MASK 0x58 #define GPIO_HI_INT_LEV_MASK 0x5c #define GPIO(n) (1 << (n)) #define MV_GPIO_MAX_NPINS 64 #define MV_GPIO_IN_NONE 0x0 #define MV_GPIO_IN_POL_LOW (1 << 16) #define MV_GPIO_IN_IRQ_EDGE (2 << 16) #define MV_GPIO_IN_IRQ_LEVEL (4 << 16) #define MV_GPIO_OUT_NONE 0x0 #define MV_GPIO_OUT_BLINK 0x1 #define MV_GPIO_OUT_OPEN_DRAIN 0x2 #define MV_GPIO_OUT_OPEN_SRC 0x4 #define IS_GPIO_IRQ(irq) ((irq) >= NIRQ && (irq) < NIRQ + MV_GPIO_MAX_NPINS) #define GPIO2IRQ(gpio) ((gpio) + NIRQ) #define IRQ2GPIO(irq) ((irq) - NIRQ) #if defined(SOC_MV_ORION) #define SAMPLE_AT_RESET 0x10 #elif defined(SOC_MV_KIRKWOOD) #define SAMPLE_AT_RESET 0x30 #endif #define SAMPLE_AT_RESET_ARMADA38X 0x400 #define SAMPLE_AT_RESET_LO 0x30 #define SAMPLE_AT_RESET_HI 0x34 /* * Clocks */ #if defined(SOC_MV_ORION) #define TCLK_MASK 0x00000300 #define TCLK_SHIFT 0x08 #elif defined(SOC_MV_DISCOVERY) #define TCLK_MASK 0x00000180 #define TCLK_SHIFT 0x07 #endif #define TCLK_MASK_ARMADA38X 0x00008000 #define TCLK_SHIFT_ARMADA38X 15 #define TCLK_100MHZ 100000000 #define TCLK_125MHZ 125000000 #define TCLK_133MHZ 133333333 #define TCLK_150MHZ 150000000 #define TCLK_166MHZ 166666667 #define TCLK_200MHZ 200000000 #define TCLK_250MHZ 250000000 #define TCLK_300MHZ 300000000 #define TCLK_667MHZ 667000000 #define A38X_CPU_DDR_CLK_MASK 0x00007c00 #define A38X_CPU_DDR_CLK_SHIFT 10 /* * CPU Cache Configuration */ #define CPU_CONFIG 0x00000000 #define CPU_CONFIG_IC_PREF 0x00010000 #define CPU_CONFIG_DC_PREF 0x00020000 #define CPU_CONTROL 0x00000004 #define CPU_CONTROL_L2_SIZE 0x00200000 /* Only on Discovery */ #define CPU_CONTROL_L2_MODE 0x00020000 /* Only on Discovery */ #define CPU_L2_CONFIG 0x00000028 /* Only on Kirkwood */ #define CPU_L2_CONFIG_MODE 0x00000010 /* Only on Kirkwood */ /* * PCI Express port control (CPU Control registers) */ #define CPU_CONTROL_PCIE_DISABLE(n) (1 << (3 * (n))) /* * Vendor ID */ #define PCI_VENDORID_MRVL 0x11AB #define PCI_VENDORID_MRVL2 0x1B4B /* * Chip ID */ #define MV_DEV_88F5181 0x5181 #define MV_DEV_88F5182 0x5182 #define MV_DEV_88F5281 0x5281 #define MV_DEV_88F6281 0x6281 #define MV_DEV_88F6282 0x6282 #define MV_DEV_88F6781 0x6781 #define MV_DEV_88F6828 0x6828 #define MV_DEV_88F6820 0x6820 #define MV_DEV_88F6810 0x6810 #define MV_DEV_MV78100_Z0 0x6381 #define MV_DEV_MV78100 0x7810 #define MV_DEV_MV78130 0x7813 #define MV_DEV_MV78160 0x7816 #define MV_DEV_MV78230 0x7823 #define MV_DEV_MV78260 0x7826 #define MV_DEV_MV78460 0x7846 #define MV_DEV_88RC8180 0x8180 #define MV_DEV_88RC9480 0x9480 #define MV_DEV_88RC9580 0x9580 #define MV_DEV_FAMILY_MASK 0xff00 #define MV_DEV_DISCOVERY 0x7800 #define MV_DEV_ARMADA38X 0x6800 /* * Doorbell register control */ #define MV_DRBL_PCIE_TO_CPU 0 #define MV_DRBL_CPU_TO_PCIE 1 #define MV_DRBL_CAUSE(d,u) (0x10 * (u) + 0x8 * (d)) #define MV_DRBL_MASK(d,u) (0x10 * (u) + 0x8 * (d) + 0x4) #define MV_DRBL_MSG(m,d,u) (0x10 * (u) + 0x8 * (d) + 0x4 * (m) + 0x30) /* * SCU */ #define MV_SCU_BASE (MV_BASE + 0xc000) #define MV_SCU_REGS_LEN 0x100 #define MV_SCU_REG_CTRL 0x00 #define MV_SCU_REG_CONFIG 0x04 #define MV_SCU_ENABLE (1 << 0) #define MV_SCU_SL_L2_ENABLE (1 << 3) #define SCU_CFG_REG_NCPU_MASK 0x3 /* * PMSU */ #define MV_PMSU_BASE (MV_BASE + 0x22000) #define MV_PMSU_REGS_LEN 0x1000 #define PMSU_BOOT_ADDR_REDIRECT_OFFSET(cpu) (((cpu) * 0x100) + 0x124) /* * CPU RESET */ #define MV_CPU_RESET_BASE (MV_BASE + 0x20800) #define MV_CPU_RESET_REGS_LEN 0x8 #define CPU_RESET_OFFSET(cpu) ((cpu) * 0x8) #define CPU_RESET_ASSERT 0x1 #define MV_MBUS_CTRL_BASE (MV_BASE + 0x20420) #define MV_MBUS_CTRL_REGS_LEN 0x10 #endif /* _MVREG_H_ */ Index: head/sys/arm/mv/timer.c =================================================================== --- head/sys/arm/mv/timer.c (revision 332010) +++ head/sys/arm/mv/timer.c (revision 332011) @@ -1,559 +1,568 @@ /*- * SPDX-License-Identifier: BSD-2-Clause-FreeBSD * * Copyright (c) 2006 Benno Rice. * Copyright (C) 2007-2008 MARVELL INTERNATIONAL LTD. * All rights reserved. * * Adapted to Marvell SoC by Semihalf. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * * from: FreeBSD: //depot/projects/arm/src/sys/arm/xscale/pxa2x0/pxa2x0_timer.c, rev 1 */ #include __FBSDID("$FreeBSD$"); #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #define INITIAL_TIMECOUNTER (0xffffffff) #define MAX_WATCHDOG_TICKS (0xffffffff) #define MV_TMR 0x1 #define MV_WDT 0x2 #define MV_NONE 0x0 #define MV_CLOCK_SRC_ARMV7 25000000 /* Timers' 25MHz mode */ #define WATCHDOG_TIMER_ARMV5 2 typedef void (*mv_watchdog_enable_t)(void); typedef void (*mv_watchdog_disable_t)(void); struct mv_timer_config { enum soc_family soc_family; mv_watchdog_enable_t watchdog_enable; mv_watchdog_disable_t watchdog_disable; unsigned int clock_src; + uint32_t bridge_irq_cause; + uint32_t irq_timer0_clr; + uint32_t irq_timer_wd_clr; }; struct mv_timer_softc { struct resource * timer_res[2]; bus_space_tag_t timer_bst; bus_space_handle_t timer_bsh; struct mtx timer_mtx; struct eventtimer et; boolean_t has_wdt; struct mv_timer_config* config; }; static struct resource_spec mv_timer_spec[] = { { SYS_RES_MEMORY, 0, RF_ACTIVE }, { SYS_RES_IRQ, 0, RF_ACTIVE | RF_OPTIONAL }, { -1, 0 } }; /* Interrupt is not required by MV_WDT devices */ static struct ofw_compat_data mv_timer_compat[] = { {"marvell,armada-380-timer", MV_NONE }, {"marvell,armada-xp-timer", MV_TMR | MV_WDT }, {"mrvl,timer", MV_TMR | MV_WDT }, {NULL, MV_NONE } }; static struct mv_timer_softc *timer_softc = NULL; static int timers_initialized = 0; static int mv_timer_probe(device_t); static int mv_timer_attach(device_t); static int mv_hardclock(void *); static unsigned mv_timer_get_timecount(struct timecounter *); static uint32_t mv_get_timer_control(void); static void mv_set_timer_control(uint32_t); static uint32_t mv_get_timer(uint32_t); static void mv_set_timer(uint32_t, uint32_t); static void mv_set_timer_rel(uint32_t, uint32_t); static void mv_watchdog_event(void *, unsigned int, int *); static int mv_timer_start(struct eventtimer *et, sbintime_t first, sbintime_t period); static int mv_timer_stop(struct eventtimer *et); static void mv_setup_timers(void); static void mv_watchdog_enable_armv5(void); static void mv_watchdog_enable_armadaxp(void); static void mv_watchdog_disable_armv5(void); static void mv_watchdog_disable_armadaxp(void); static void mv_delay(int usec, void* arg); static struct mv_timer_config timer_armadaxp_config = { MV_SOC_ARMADA_XP, &mv_watchdog_enable_armadaxp, &mv_watchdog_disable_armadaxp, MV_CLOCK_SRC_ARMV7, + BRIDGE_IRQ_CAUSE_ARMADAXP, + IRQ_TIMER0_CLR_ARMADAXP, + IRQ_TIMER_WD_CLR_ARMADAXP, }; static struct mv_timer_config timer_armv5_config = { MV_SOC_ARMV5, &mv_watchdog_enable_armv5, &mv_watchdog_disable_armv5, 0, + BRIDGE_IRQ_CAUSE, + IRQ_TIMER0_CLR, + IRQ_TIMER_WD_CLR, }; static struct ofw_compat_data mv_timer_soc_config[] = { {"marvell,armada-xp-timer", (uintptr_t)&timer_armadaxp_config }, {"mrvl,timer", (uintptr_t)&timer_armv5_config }, {NULL, (uintptr_t)NULL }, }; static struct timecounter mv_timer_timecounter = { .tc_get_timecount = mv_timer_get_timecount, .tc_name = "CPUTimer1", .tc_frequency = 0, /* This is assigned on the fly in the init sequence */ .tc_counter_mask = ~0u, .tc_quality = 1000, }; static int mv_timer_probe(device_t dev) { if (!ofw_bus_status_okay(dev)) return (ENXIO); if (ofw_bus_search_compatible(dev, mv_timer_compat)->ocd_data == MV_NONE) return (ENXIO); device_set_desc(dev, "Marvell CPU Timer"); return (0); } static int mv_timer_attach(device_t dev) { int error; void *ihl; struct mv_timer_softc *sc; uint32_t irq_cause, irq_mask; if (timer_softc != NULL) return (ENXIO); sc = (struct mv_timer_softc *)device_get_softc(dev); timer_softc = sc; sc->config = (struct mv_timer_config*) ofw_bus_search_compatible(dev, mv_timer_soc_config)->ocd_data; if (sc->config->clock_src == 0) sc->config->clock_src = get_tclk(); error = bus_alloc_resources(dev, mv_timer_spec, sc->timer_res); if (error) { device_printf(dev, "could not allocate resources\n"); return (ENXIO); } sc->timer_bst = rman_get_bustag(sc->timer_res[0]); sc->timer_bsh = rman_get_bushandle(sc->timer_res[0]); sc->has_wdt = ofw_bus_has_prop(dev, "mrvl,has-wdt"); mtx_init(&timer_softc->timer_mtx, "watchdog", NULL, MTX_DEF); if (sc->has_wdt) { if (sc->config->watchdog_disable) sc->config->watchdog_disable(); EVENTHANDLER_REGISTER(watchdog_list, mv_watchdog_event, sc, 0); } if (ofw_bus_search_compatible(dev, mv_timer_compat)->ocd_data == MV_WDT) { /* Don't set timers for wdt-only entry. */ device_printf(dev, "only watchdog attached\n"); return (0); } else if (sc->timer_res[1] == NULL) { device_printf(dev, "no interrupt resource\n"); bus_release_resources(dev, mv_timer_spec, sc->timer_res); return (ENXIO); } if (bus_setup_intr(dev, sc->timer_res[1], INTR_TYPE_CLK, mv_hardclock, NULL, sc, &ihl) != 0) { bus_release_resources(dev, mv_timer_spec, sc->timer_res); device_printf(dev, "Could not setup interrupt.\n"); return (ENXIO); } mv_setup_timers(); if (sc->config->soc_family != MV_SOC_ARMADA_XP ) { - irq_cause = read_cpu_ctrl(BRIDGE_IRQ_CAUSE); - irq_cause &= IRQ_TIMER0_CLR; + irq_cause = read_cpu_ctrl(sc->config->bridge_irq_cause); + irq_cause &= sc->config->irq_timer0_clr; - write_cpu_ctrl(BRIDGE_IRQ_CAUSE, irq_cause); + write_cpu_ctrl(sc->config->bridge_irq_cause, irq_cause); irq_mask = read_cpu_ctrl(BRIDGE_IRQ_MASK); irq_mask |= IRQ_TIMER0_MASK; irq_mask &= ~IRQ_TIMER1_MASK; write_cpu_ctrl(BRIDGE_IRQ_MASK, irq_mask); } sc->et.et_name = "CPUTimer0"; sc->et.et_flags = ET_FLAGS_PERIODIC | ET_FLAGS_ONESHOT; sc->et.et_quality = 1000; sc->et.et_frequency = sc->config->clock_src; sc->et.et_min_period = (0x00000002LLU << 32) / sc->et.et_frequency; sc->et.et_max_period = (0xfffffffeLLU << 32) / sc->et.et_frequency; sc->et.et_start = mv_timer_start; sc->et.et_stop = mv_timer_stop; sc->et.et_priv = sc; et_register(&sc->et); mv_timer_timecounter.tc_frequency = sc->config->clock_src; tc_init(&mv_timer_timecounter); #ifdef PLATFORM arm_set_delay(mv_delay, NULL); #endif return (0); } static int mv_hardclock(void *arg) { struct mv_timer_softc *sc; uint32_t irq_cause; - irq_cause = read_cpu_ctrl(BRIDGE_IRQ_CAUSE); - irq_cause &= IRQ_TIMER0_CLR; - write_cpu_ctrl(BRIDGE_IRQ_CAUSE, irq_cause); + irq_cause = read_cpu_ctrl(timer_softc->config->bridge_irq_cause); + irq_cause &= timer_softc->config->irq_timer0_clr; + write_cpu_ctrl(timer_softc->config->bridge_irq_cause, irq_cause); sc = (struct mv_timer_softc *)arg; if (sc->et.et_active) sc->et.et_event_cb(&sc->et, sc->et.et_arg); return (FILTER_HANDLED); } static device_method_t mv_timer_methods[] = { DEVMETHOD(device_probe, mv_timer_probe), DEVMETHOD(device_attach, mv_timer_attach), { 0, 0 } }; static driver_t mv_timer_driver = { "timer", mv_timer_methods, sizeof(struct mv_timer_softc), }; static devclass_t mv_timer_devclass; DRIVER_MODULE(timer_mv, simplebus, mv_timer_driver, mv_timer_devclass, 0, 0); static unsigned mv_timer_get_timecount(struct timecounter *tc) { return (INITIAL_TIMECOUNTER - mv_get_timer(1)); } static void mv_delay(int usec, void* arg) { uint32_t val, val_temp; int32_t nticks; val = mv_get_timer(1); nticks = ((timer_softc->config->clock_src / 1000000 + 1) * usec); while (nticks > 0) { val_temp = mv_get_timer(1); if (val > val_temp) nticks -= (val - val_temp); else nticks -= (val + (INITIAL_TIMECOUNTER - val_temp)); val = val_temp; } } #ifndef PLATFORM void DELAY(int usec) { uint32_t val; if (!timers_initialized) { for (; usec > 0; usec--) for (val = 100; val > 0; val--) __asm __volatile("nop" ::: "memory"); } else { TSENTER(); mv_delay(usec, NULL); TSEXIT(); } } #endif static uint32_t mv_get_timer_control(void) { return (bus_space_read_4(timer_softc->timer_bst, timer_softc->timer_bsh, CPU_TIMER_CONTROL)); } static void mv_set_timer_control(uint32_t val) { bus_space_write_4(timer_softc->timer_bst, timer_softc->timer_bsh, CPU_TIMER_CONTROL, val); } static uint32_t mv_get_timer(uint32_t timer) { return (bus_space_read_4(timer_softc->timer_bst, timer_softc->timer_bsh, CPU_TIMER0 + timer * 0x8)); } static void mv_set_timer(uint32_t timer, uint32_t val) { bus_space_write_4(timer_softc->timer_bst, timer_softc->timer_bsh, CPU_TIMER0 + timer * 0x8, val); } static void mv_set_timer_rel(uint32_t timer, uint32_t val) { bus_space_write_4(timer_softc->timer_bst, timer_softc->timer_bsh, CPU_TIMER0_REL + timer * 0x8, val); } static void mv_watchdog_enable_armv5(void) { uint32_t val, irq_cause, irq_mask; - irq_cause = read_cpu_ctrl(BRIDGE_IRQ_CAUSE); - irq_cause &= IRQ_TIMER_WD_CLR; - write_cpu_ctrl(BRIDGE_IRQ_CAUSE, irq_cause); + irq_cause = read_cpu_ctrl(timer_softc->config->bridge_irq_cause); + irq_cause &= timer_softc->config->irq_timer_wd_clr; + write_cpu_ctrl(timer_softc->config->bridge_irq_cause, irq_cause); irq_mask = read_cpu_ctrl(BRIDGE_IRQ_MASK); irq_mask |= IRQ_TIMER_WD_MASK; write_cpu_ctrl(BRIDGE_IRQ_MASK, irq_mask); val = read_cpu_ctrl(RSTOUTn_MASK); val |= WD_RST_OUT_EN; write_cpu_ctrl(RSTOUTn_MASK, val); val = mv_get_timer_control(); val |= CPU_TIMER2_EN | CPU_TIMER2_AUTO; mv_set_timer_control(val); } static void mv_watchdog_enable_armadaxp(void) { uint32_t irq_cause, val; - irq_cause = read_cpu_ctrl(BRIDGE_IRQ_CAUSE); - irq_cause &= IRQ_TIMER_WD_CLR; - write_cpu_ctrl(BRIDGE_IRQ_CAUSE, irq_cause); + irq_cause = read_cpu_ctrl(timer_softc->config->bridge_irq_cause); + irq_cause &= timer_softc->config->irq_timer_wd_clr; + write_cpu_ctrl(timer_softc->config->bridge_irq_cause, irq_cause); val = read_cpu_mp_clocks(WD_RSTOUTn_MASK); val |= (WD_GLOBAL_MASK | WD_CPU0_MASK); write_cpu_mp_clocks(WD_RSTOUTn_MASK, val); val = read_cpu_misc(RSTOUTn_MASK_ARMV7); val &= ~RSTOUTn_MASK_WD; write_cpu_misc(RSTOUTn_MASK_ARMV7, val); val = mv_get_timer_control(); val |= CPU_TIMER2_EN | CPU_TIMER2_AUTO | CPU_TIMER_WD_25MHZ_EN; mv_set_timer_control(val); } static void mv_watchdog_disable_armv5(void) { uint32_t val, irq_cause,irq_mask; val = mv_get_timer_control(); val &= ~(CPU_TIMER2_EN | CPU_TIMER2_AUTO); mv_set_timer_control(val); val = read_cpu_ctrl(RSTOUTn_MASK); val &= ~WD_RST_OUT_EN; write_cpu_ctrl(RSTOUTn_MASK, val); irq_mask = read_cpu_ctrl(BRIDGE_IRQ_MASK); irq_mask &= ~(IRQ_TIMER_WD_MASK); write_cpu_ctrl(BRIDGE_IRQ_MASK, irq_mask); - irq_cause = read_cpu_ctrl(BRIDGE_IRQ_CAUSE); - irq_cause &= IRQ_TIMER_WD_CLR; - write_cpu_ctrl(BRIDGE_IRQ_CAUSE, irq_cause); + irq_cause = read_cpu_ctrl(timer_softc->config->bridge_irq_cause); + irq_cause &= timer_softc->config->irq_timer_wd_clr; + write_cpu_ctrl(timer_softc->config->bridge_irq_cause, irq_cause); } static void mv_watchdog_disable_armadaxp(void) { uint32_t val, irq_cause; val = read_cpu_mp_clocks(WD_RSTOUTn_MASK); val &= ~(WD_GLOBAL_MASK | WD_CPU0_MASK); write_cpu_mp_clocks(WD_RSTOUTn_MASK, val); val = read_cpu_misc(RSTOUTn_MASK_ARMV7); val |= RSTOUTn_MASK_WD; write_cpu_misc(RSTOUTn_MASK_ARMV7, RSTOUTn_MASK_WD); - irq_cause = read_cpu_ctrl(BRIDGE_IRQ_CAUSE); - irq_cause &= IRQ_TIMER_WD_CLR; - write_cpu_ctrl(BRIDGE_IRQ_CAUSE, irq_cause); + irq_cause = read_cpu_ctrl(timer_softc->config->bridge_irq_cause); + irq_cause &= timer_softc->config->irq_timer_wd_clr; + write_cpu_ctrl(timer_softc->config->bridge_irq_cause, irq_cause); val = mv_get_timer_control(); val &= ~(CPU_TIMER2_EN | CPU_TIMER2_AUTO); mv_set_timer_control(val); } /* * Watchdog event handler. */ static void mv_watchdog_event(void *arg, unsigned int cmd, int *error) { uint64_t ns; uint64_t ticks; mtx_lock(&timer_softc->timer_mtx); if (cmd == 0) { if (timer_softc->config->watchdog_disable != NULL) timer_softc->config->watchdog_disable(); } else { /* * Watchdog timeout is in nanosecs, calculation according to * watchdog(9) */ ns = (uint64_t)1 << (cmd & WD_INTERVAL); ticks = (uint64_t)(ns * timer_softc->config->clock_src) / 1000000000; if (ticks > MAX_WATCHDOG_TICKS) { if (timer_softc->config->watchdog_disable != NULL) timer_softc->config->watchdog_disable(); } else { mv_set_timer(WATCHDOG_TIMER_ARMV5, ticks); if (timer_softc->config->watchdog_enable != NULL) timer_softc->config->watchdog_enable(); *error = 0; } } mtx_unlock(&timer_softc->timer_mtx); } static int mv_timer_start(struct eventtimer *et, sbintime_t first, sbintime_t period) { struct mv_timer_softc *sc; uint32_t val, val1; /* Calculate dividers. */ sc = (struct mv_timer_softc *)et->et_priv; if (period != 0) val = ((uint32_t)sc->et.et_frequency * period) >> 32; else val = 0; if (first != 0) val1 = ((uint32_t)sc->et.et_frequency * first) >> 32; else val1 = val; /* Apply configuration. */ mv_set_timer_rel(0, val); mv_set_timer(0, val1); val = mv_get_timer_control(); val |= CPU_TIMER0_EN; if (period != 0) val |= CPU_TIMER0_AUTO; else val &= ~CPU_TIMER0_AUTO; mv_set_timer_control(val); return (0); } static int mv_timer_stop(struct eventtimer *et) { uint32_t val; val = mv_get_timer_control(); val &= ~(CPU_TIMER0_EN | CPU_TIMER0_AUTO); mv_set_timer_control(val); return (0); } static void mv_setup_timers(void) { uint32_t val; mv_set_timer_rel(1, INITIAL_TIMECOUNTER); mv_set_timer(1, INITIAL_TIMECOUNTER); val = mv_get_timer_control(); val &= ~(CPU_TIMER0_EN | CPU_TIMER0_AUTO); val |= CPU_TIMER1_EN | CPU_TIMER1_AUTO; if (timer_softc->config->soc_family == MV_SOC_ARMADA_XP) { /* Enable 25MHz mode */ val |= CPU_TIMER0_25MHZ_EN | CPU_TIMER1_25MHZ_EN; } mv_set_timer_control(val); timers_initialized = 1; }