Index: head/sys/arm/conf/ARMADA38X =================================================================== --- head/sys/arm/conf/ARMADA38X (revision 331994) +++ head/sys/arm/conf/ARMADA38X (revision 331995) @@ -1,100 +1,99 @@ # # Kernel configuration for Marvell Armada38x # # $FreeBSD$ # include "../mv/armada38x/std.armada38x" include "std.armv7" ident ARMADA38X options SOC_MV_ARMADA38X makeoptions WERROR="-Werror" makeoptions MODULES_EXTRA="dtb/mv" options MD_ROOT #makeoptions MFS_IMAGE=/path/to/miniroot #options ROOTDEVNAME=\"ufs:md0\" options ROOTDEVNAME=\"/dev/da0s1a\" options SCHED_ULE # ULE scheduler options SMP options VM_KMEM_SIZE_MAX=0x9CCD000 # Pseudo devices device random device pty device loop device md # Serial ports device uart device uart_snps # Network device ether device vlan device mii device bpf device re device mdio device etherswitch device e6000sw device neta # PCI device pci -# RTC -device mv_rtc - # Interrupt controllers device gic options INTRNG # Timers device mpcore_timer # USB device usb device ehci device xhci device umass device scbus device pass device da # MMC/SD/SDIO Card slot support device mmc # mmc/sd bus device mmcsd # mmc/sd flash cards device sdhci # mmc/sd host controller # SATA device ahci # I2C device iic device iicbus device twsi # Wireless NIC cards device wlan # 802.11 support device ath # Atheros NIC's device ath_pci # Atheros pci/cardbus glue device ath_hal device ath_rate_sample options ATH_ENABLE_11N # CESA device cesa device crypto device cryptodev # L2 Cache device pl310 + +options PLATFORM # FDT options FDT Index: head/sys/arm/conf/ARMADAXP =================================================================== --- head/sys/arm/conf/ARMADAXP (revision 331994) +++ head/sys/arm/conf/ARMADAXP (revision 331995) @@ -1,92 +1,94 @@ # # Custom kernel for Marvell Armada XP # # For more information on this file, please read the config(5) manual page, # and/or the handbook section on Kernel Configuration Files: # # https://www.FreeBSD.org/doc/en_US.ISO8859-1/books/handbook/kernelconfig-config.html # # The handbook is also available locally in /usr/share/doc/handbook # if you've installed the doc distribution, otherwise always see the # FreeBSD World Wide Web server (https://www.FreeBSD.org/) for the # latest information. # # An exhaustive list of options and more detailed explanations of the # device lines is also present in the ../../conf/NOTES and NOTES files. # If you are in doubt as to the purpose or necessity of a line, check first # in NOTES. # # $FreeBSD$ # TODO: Port to INTRNG #NO_UNIVERSE ident MV-88F78XX0 include "std.armv7" include "../mv/armadaxp/std.mv78x60" options SOC_MV_ARMADAXP makeoptions WERROR="-Werror" options SCHED_ULE # ULE scheduler options SMP # Enable multiple cores # NFS root from boopt/dhcp options BOOTP options BOOTP_NFSROOT options BOOTP_NFSV3 options BOOTP_WIRED_TO=mge0 options ROOTDEVNAME=\"ufs:/dev/da0p1\" options MUTEX_NOINLINE options RWLOCK_NOINLINE options NO_FFS_SNAPSHOT options NO_SWAPPING # Pseudo devices device random device pty device loop device md # USB device usb device ehci device umass device scbus device pass device da # SATA device mvs # Serial ports device uart # I2C (TWSI) device iic device iicbus device twsi #Network device ether device mge # Marvell Gigabit Ethernet controller device mii device mdio device e1000phy device bpf options DEVICE_POLLING device vlan #PCI/PCIE device pci # Flattened Device Tree options FDT # Configure using FDT/DTB data options FDT_DTB_STATIC makeoptions FDT_DTS_FILE=db78460.dts options INTRNG + +options PLATFORM Index: head/sys/arm/mv/mv_machdep.c =================================================================== --- head/sys/arm/mv/mv_machdep.c (revision 331994) +++ head/sys/arm/mv/mv_machdep.c (nonexistent) @@ -1,561 +0,0 @@ -/*- - * SPDX-License-Identifier: BSD-2-Clause-FreeBSD - * - * Copyright (c) 1994-1998 Mark Brinicombe. - * Copyright (c) 1994 Brini. - * All rights reserved. - * - * This code is derived from software written for Brini by Mark Brinicombe - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. All advertising materials mentioning features or use of this software - * must display the following acknowledgement: - * This product includes software developed by Brini. - * 4. The name of the company nor the name of the author may be used to - * endorse or promote products derived from this software without specific - * prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY BRINI ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - * IN NO EVENT SHALL BRINI OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, - * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - * - * from: FreeBSD: //depot/projects/arm/src/sys/arm/at91/kb920x_machdep.c, rev 45 - */ - -#include "opt_ddb.h" -#include "opt_platform.h" - -#include -__FBSDID("$FreeBSD$"); - -#define _ARM32_BUS_DMA_PRIVATE -#include -#include -#include -#include -#include - -#include -#include - -#include -#include - -#include -#include -#include -#include - -#if __ARM_ARCH < 6 -#include -#else -#include -#include -#endif - -#include /* XXX */ -#include /* XXX eventually this should be eliminated */ -#include - -#include -#include - -static int platform_mpp_init(void); -#if defined(SOC_MV_ARMADAXP) -void armadaxp_init_coher_fabric(void); -void armadaxp_l2_init(void); -#endif -#if defined(SOC_MV_ARMADA38X) -int armada38x_win_set_iosync_barrier(void); -int armada38x_scu_enable(void); -int armada38x_open_bootrom_win(void); -int armada38x_mbus_optimization(void); -#endif - -#define MPP_PIN_MAX 68 -#define MPP_PIN_CELLS 2 -#define MPP_PINS_PER_REG 8 -#define MPP_SEL(pin,func) (((func) & 0xf) << \ - (((pin) % MPP_PINS_PER_REG) * 4)) - -static void -mv_busdma_tag_init(void *arg __unused) -{ - phandle_t node; - bus_dma_tag_t dmat; - - /* - * If this platform has coherent DMA, create the parent DMA tag to pass - * down the coherent flag to all busses and devices on the platform, - * otherwise return without doing anything. By default create tag - * for all A38x-based platforms only. - */ - if ((node = OF_finddevice("/")) == -1) - return; - if (ofw_bus_node_is_compatible(node, "marvell,armada380") == 0) - return; - - bus_dma_tag_create(NULL, /* No parent tag */ - 1, 0, /* alignment, bounds */ - BUS_SPACE_MAXADDR, /* lowaddr */ - BUS_SPACE_MAXADDR, /* highaddr */ - NULL, NULL, /* filter, filterarg */ - BUS_SPACE_MAXSIZE, /* maxsize */ - BUS_SPACE_UNRESTRICTED, /* nsegments */ - BUS_SPACE_MAXSIZE, /* maxsegsize */ - BUS_DMA_COHERENT, /* flags */ - NULL, NULL, /* lockfunc, lockarg */ - &dmat); - - nexus_set_dma_tag(dmat); -} -SYSINIT(mv_busdma_tag, SI_SUB_DRIVERS, SI_ORDER_ANY, mv_busdma_tag_init, NULL); - -static int -platform_mpp_init(void) -{ - pcell_t pinmap[MPP_PIN_MAX * MPP_PIN_CELLS]; - int mpp[MPP_PIN_MAX]; - uint32_t ctrl_val, ctrl_offset; - pcell_t reg[4]; - u_long start, size; - phandle_t node; - pcell_t pin_cells, *pinmap_ptr, pin_count; - ssize_t len; - int par_addr_cells, par_size_cells; - int tuple_size, tuples, rv, pins, i, j; - int mpp_pin, mpp_function; - - /* - * Try to access the MPP node directly i.e. through /aliases/mpp. - */ - if ((node = OF_finddevice("mpp")) != -1) - if (ofw_bus_node_is_compatible(node, "mrvl,mpp")) - goto moveon; - /* - * Find the node the long way. - */ - if ((node = OF_finddevice("/")) == -1) - return (ENXIO); - - if ((node = fdt_find_compatible(node, "simple-bus", 0)) == 0) - return (ENXIO); - - if ((node = fdt_find_compatible(node, "mrvl,mpp", 0)) == 0) - /* - * No MPP node. Fall back to how MPP got set by the - * first-stage loader and try to continue booting. - */ - return (0); -moveon: - /* - * Process 'reg' prop. - */ - if ((rv = fdt_addrsize_cells(OF_parent(node), &par_addr_cells, - &par_size_cells)) != 0) - return(ENXIO); - - tuple_size = sizeof(pcell_t) * (par_addr_cells + par_size_cells); - len = OF_getprop(node, "reg", reg, sizeof(reg)); - tuples = len / tuple_size; - if (tuple_size <= 0) - return (EINVAL); - - /* - * Get address/size. XXX we assume only the first 'reg' tuple is used. - */ - rv = fdt_data_to_res(reg, par_addr_cells, par_size_cells, - &start, &size); - if (rv != 0) - return (rv); - start += fdt_immr_va; - - /* - * Process 'pin-count' and 'pin-map' props. - */ - if (OF_getencprop(node, "pin-count", &pin_count, sizeof(pin_count)) <= 0) - return (ENXIO); - if (pin_count > MPP_PIN_MAX) - return (ERANGE); - - if (OF_getencprop(node, "#pin-cells", &pin_cells, sizeof(pin_cells)) <= 0) - pin_cells = MPP_PIN_CELLS; - if (pin_cells > MPP_PIN_CELLS) - return (ERANGE); - tuple_size = sizeof(pcell_t) * pin_cells; - - bzero(pinmap, sizeof(pinmap)); - len = OF_getencprop(node, "pin-map", pinmap, sizeof(pinmap)); - if (len <= 0) - return (ERANGE); - if (len % tuple_size) - return (ERANGE); - pins = len / tuple_size; - if (pins > pin_count) - return (ERANGE); - /* - * Fill out a "mpp[pin] => function" table. All pins unspecified in - * the 'pin-map' property are defaulted to 0 function i.e. GPIO. - */ - bzero(mpp, sizeof(mpp)); - pinmap_ptr = pinmap; - for (i = 0; i < pins; i++) { - mpp_pin = *pinmap_ptr; - mpp_function = *(pinmap_ptr + 1); - mpp[mpp_pin] = mpp_function; - pinmap_ptr += pin_cells; - } - - /* - * Prepare and program MPP control register values. - */ - ctrl_offset = 0; - for (i = 0; i < pin_count;) { - ctrl_val = 0; - - for (j = 0; j < MPP_PINS_PER_REG; j++) { - if (i + j == pin_count - 1) - break; - ctrl_val |= MPP_SEL(i + j, mpp[i + j]); - } - i += MPP_PINS_PER_REG; - bus_space_write_4(fdtbus_bs_tag, start, ctrl_offset, - ctrl_val); - -#if defined(SOC_MV_ORION) - /* - * Third MPP reg on Orion SoC is placed - * non-linearly (with different offset). - */ - if (i == (2 * MPP_PINS_PER_REG)) - ctrl_offset = 0x50; - else -#endif - ctrl_offset += 4; - } - - return (0); -} - -vm_offset_t -platform_lastaddr(void) -{ - - return (fdt_immr_va); -} - -void -platform_probe_and_attach(void) -{ - - if (fdt_immr_addr(MV_BASE) != 0) - while (1); -} - -void -platform_gpio_init(void) -{ - - /* - * Re-initialise MPP. It is important to call this prior to using - * console as the physical connection can be routed via MPP. - */ - if (platform_mpp_init() != 0) - while (1); -} - -void -platform_late_init(void) -{ - /* - * Re-initialise decode windows - */ - if (mv_check_soc_family() == MV_SOC_UNSUPPORTED) - panic("Unsupported SoC family\n"); - - if (soc_decode_win() != 0) - printf("WARNING: could not re-initialise decode windows! " - "Running with existing settings...\n"); -#if defined(SOC_MV_ARMADAXP) -#if !defined(SMP) - /* For SMP case it should be initialized after APs are booted */ - armadaxp_init_coher_fabric(); -#endif - armadaxp_l2_init(); -#endif - -#if defined(SOC_MV_ARMADA38X) - /* Configure timers' base frequency */ - arm_tmr_change_frequency(get_cpu_freq() / 2); - - /* - * Workaround for Marvell Armada38X family HW issue - * between Cortex-A9 CPUs and on-chip devices that may - * cause hang on heavy load. - * To avoid that, map all registers including PCIe IO - * as strongly ordered instead of device memory. - */ - pmap_remap_vm_attr(VM_MEMATTR_DEVICE, VM_MEMATTR_SO); - - /* Set IO Sync Barrier bit for all Mbus devices */ - if (armada38x_win_set_iosync_barrier() != 0) - printf("WARNING: could not map CPU Subsystem registers\n"); - if (armada38x_mbus_optimization() != 0) - printf("WARNING: could not enable mbus optimization\n"); - if (armada38x_scu_enable() != 0) - printf("WARNING: could not enable SCU\n"); -#ifdef SMP - /* Open window to bootROM memory - needed for SMP */ - if (armada38x_open_bootrom_win() != 0) - printf("WARNING: could not open window to bootROM\n"); -#endif -#endif -} -#if defined(SOC_MV_ARMADAXP) || defined(SOC_MV_ARMADA38X) -#define FDT_DEVMAP_MAX (MV_WIN_CPU_MAX_ARMV7 + 2) -#else -#define FDT_DEVMAP_MAX (MV_WIN_CPU_MAX + 2) -#endif -static struct devmap_entry fdt_devmap[FDT_DEVMAP_MAX] = { - { 0, 0, 0, } -}; - -static int -platform_sram_devmap(struct devmap_entry *map) -{ -#if !defined(SOC_MV_ARMADAXP) && !defined(SOC_MV_ARMADA38X) - phandle_t child, root; - u_long base, size; - /* - * SRAM range. - */ - if ((child = OF_finddevice("/sram")) != 0) - if (ofw_bus_node_is_compatible(child, "mrvl,cesa-sram") || - ofw_bus_node_is_compatible(child, "mrvl,scratchpad")) - goto moveon; - - if ((root = OF_finddevice("/")) == 0) - return (ENXIO); - - if ((child = fdt_find_compatible(root, "mrvl,cesa-sram", 0)) == 0 && - (child = fdt_find_compatible(root, "mrvl,scratchpad", 0)) == 0) - goto out; - -moveon: - if (fdt_regsize(child, &base, &size) != 0) - return (EINVAL); - - map->pd_va = MV_CESA_SRAM_BASE; /* XXX */ - map->pd_pa = base; - map->pd_size = size; - - return (0); -out: -#endif - return (ENOENT); - -} - -/* - * Supply a default do-nothing implementation of mv_pci_devmap() via a weak - * alias. Many Marvell platforms don't support a PCI interface, but to support - * those that do, we end up with a reference to this function below, in - * platform_devmap_init(). If "device pci" appears in the kernel config, the - * real implementation of this function in arm/mv/mv_pci.c overrides the weak - * alias defined here. - */ -int mv_default_fdt_pci_devmap(phandle_t node, struct devmap_entry *devmap, - vm_offset_t io_va, vm_offset_t mem_va); -int -mv_default_fdt_pci_devmap(phandle_t node, struct devmap_entry *devmap, - vm_offset_t io_va, vm_offset_t mem_va) -{ - - return (0); -} -__weak_reference(mv_default_fdt_pci_devmap, mv_pci_devmap); - -/* - * XXX: When device entry in devmap has pd_size smaller than section size, - * system will freeze during initialization - */ - -/* - * Construct devmap table with DT-derived config data. - */ -int -platform_devmap_init(void) -{ - phandle_t root, child; - pcell_t bank_count; - int i, num_mapped; - - i = 0; - devmap_register_table(&fdt_devmap[0]); - -#ifdef SOC_MV_ARMADAXP - vm_paddr_t cur_immr_pa; - - /* - * Acquire SoC registers' base passed by u-boot and fill devmap - * accordingly. DTB is going to be modified basing on this data - * later. - */ - __asm __volatile("mrc p15, 4, %0, c15, c0, 0" : "=r" (cur_immr_pa)); - cur_immr_pa = (cur_immr_pa << 13) & 0xff000000; - if (cur_immr_pa != 0) - fdt_immr_pa = cur_immr_pa; -#endif - /* - * IMMR range. - */ - fdt_devmap[i].pd_va = fdt_immr_va; - fdt_devmap[i].pd_pa = fdt_immr_pa; - fdt_devmap[i].pd_size = fdt_immr_size; - i++; - - /* - * SRAM range. - */ - if (i < FDT_DEVMAP_MAX) - if (platform_sram_devmap(&fdt_devmap[i]) == 0) - i++; - - /* - * PCI range(s). - * PCI range(s) and localbus. - */ - if ((root = OF_finddevice("/")) == -1) - return (ENXIO); - for (child = OF_child(root); child != 0; child = OF_peer(child)) { - if (fdt_is_type(child, "pci") || fdt_is_type(child, "pciep")) { - /* - * Check space: each PCI node will consume 2 devmap - * entries. - */ - if (i + 1 >= FDT_DEVMAP_MAX) - return (ENOMEM); - - /* - * XXX this should account for PCI and multiple ranges - * of a given kind. - */ - if (mv_pci_devmap(child, &fdt_devmap[i], MV_PCI_VA_IO_BASE, - MV_PCI_VA_MEM_BASE) != 0) - return (ENXIO); - i += 2; - } - - if (ofw_bus_node_is_compatible(child, "mrvl,lbc")) { - /* Check available space */ - if (OF_getencprop(child, "bank-count", &bank_count, - sizeof(bank_count)) <= 0) - /* If no property, use default value */ - bank_count = 1; - - if ((i + bank_count) >= FDT_DEVMAP_MAX) - return (ENOMEM); - - /* Add all localbus ranges to device map */ - num_mapped = 0; - - if (fdt_localbus_devmap(child, &fdt_devmap[i], - (int)bank_count, &num_mapped) != 0) - return (ENXIO); - - i += num_mapped; - } - } - - return (0); -} - -#if __ARM_ARCH < 6 -struct arm32_dma_range * -bus_dma_get_range(void) -{ - - return (NULL); -} - -int -bus_dma_get_range_nb(void) -{ - - return (0); -} -#endif - -#if defined(CPU_MV_PJ4B) -#ifdef DDB -#include - -DB_SHOW_COMMAND(cp15, db_show_cp15) -{ - u_int reg; - - __asm __volatile("mrc p15, 0, %0, c0, c0, 0" : "=r" (reg)); - db_printf("Cpu ID: 0x%08x\n", reg); - __asm __volatile("mrc p15, 0, %0, c0, c0, 1" : "=r" (reg)); - db_printf("Current Cache Lvl ID: 0x%08x\n",reg); - - reg = cp15_sctlr_get(); - db_printf("Ctrl: 0x%08x\n",reg); - reg = cp15_actlr_get(); - db_printf("Aux Ctrl: 0x%08x\n",reg); - - __asm __volatile("mrc p15, 0, %0, c0, c1, 0" : "=r" (reg)); - db_printf("Processor Feat 0: 0x%08x\n", reg); - __asm __volatile("mrc p15, 0, %0, c0, c1, 1" : "=r" (reg)); - db_printf("Processor Feat 1: 0x%08x\n", reg); - __asm __volatile("mrc p15, 0, %0, c0, c1, 2" : "=r" (reg)); - db_printf("Debug Feat 0: 0x%08x\n", reg); - __asm __volatile("mrc p15, 0, %0, c0, c1, 3" : "=r" (reg)); - db_printf("Auxiliary Feat 0: 0x%08x\n", reg); - __asm __volatile("mrc p15, 0, %0, c0, c1, 4" : "=r" (reg)); - db_printf("Memory Model Feat 0: 0x%08x\n", reg); - __asm __volatile("mrc p15, 0, %0, c0, c1, 5" : "=r" (reg)); - db_printf("Memory Model Feat 1: 0x%08x\n", reg); - __asm __volatile("mrc p15, 0, %0, c0, c1, 6" : "=r" (reg)); - db_printf("Memory Model Feat 2: 0x%08x\n", reg); - __asm __volatile("mrc p15, 0, %0, c0, c1, 7" : "=r" (reg)); - db_printf("Memory Model Feat 3: 0x%08x\n", reg); - - __asm __volatile("mrc p15, 1, %0, c15, c2, 0" : "=r" (reg)); - db_printf("Aux Func Modes Ctrl 0: 0x%08x\n",reg); - __asm __volatile("mrc p15, 1, %0, c15, c2, 1" : "=r" (reg)); - db_printf("Aux Func Modes Ctrl 1: 0x%08x\n",reg); - - __asm __volatile("mrc p15, 1, %0, c15, c12, 0" : "=r" (reg)); - db_printf("CPU ID code extension: 0x%08x\n",reg); -} - -DB_SHOW_COMMAND(vtop, db_show_vtop) -{ - u_int reg; - - if (have_addr) { - __asm __volatile("mcr p15, 0, %0, c7, c8, 0" : : "r" (addr)); - __asm __volatile("mrc p15, 0, %0, c7, c4, 0" : "=r" (reg)); - db_printf("Physical address reg: 0x%08x\n",reg); - } else - db_printf("show vtop \n"); -} -#endif /* DDB */ -#endif /* CPU_MV_PJ4B */ - Property changes on: head/sys/arm/mv/mv_machdep.c ___________________________________________________________________ Deleted: svn:eol-style ## -1 +0,0 ## -native \ No newline at end of property Deleted: svn:keywords ## -1 +0,0 ## -FreeBSD=%H \ No newline at end of property Deleted: svn:mime-type ## -1 +0,0 ## -text/plain \ No newline at end of property Index: head/sys/arm/mv/armada38x/armada38x_mp.c =================================================================== --- head/sys/arm/mv/armada38x/armada38x_mp.c (revision 331994) +++ head/sys/arm/mv/armada38x/armada38x_mp.c (revision 331995) @@ -1,145 +1,148 @@ /*- * Copyright (c) 2015 Semihalf. * Copyright (c) 2015 Stormshield. * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. */ #include __FBSDID("$FreeBSD$"); #include #include #include #include #include #include #include +#include #include #include #include #include "pmsu.h" -int cpu_reset_deassert(void); +static int cpu_reset_deassert(void); +void mv_a38x_platform_mp_setmaxid(platform_t plate); +void mv_a38x_platform_mp_start_ap(platform_t plate); -int +static int cpu_reset_deassert(void) { bus_space_handle_t vaddr; uint32_t reg; int rv; rv = bus_space_map(fdtbus_bs_tag, (bus_addr_t)MV_CPU_RESET_BASE, MV_CPU_RESET_REGS_LEN, 0, &vaddr); if (rv != 0) return (rv); /* CPU1 is held at reset by default - clear assert bit to release it */ reg = bus_space_read_4(fdtbus_bs_tag, vaddr, CPU_RESET_OFFSET(1)); reg &= ~CPU_RESET_ASSERT; bus_space_write_4(fdtbus_bs_tag, vaddr, CPU_RESET_OFFSET(1), reg); bus_space_unmap(fdtbus_bs_tag, vaddr, MV_CPU_RESET_REGS_LEN); return (0); } static int platform_cnt_cpus(void) { bus_space_handle_t vaddr_scu; phandle_t cpus_node, child; char device_type[16]; int fdt_cpu_count = 0; int reg_cpu_count = 0; uint32_t val; int rv; cpus_node = OF_finddevice("/cpus"); if (cpus_node == -1) { /* Default is one core */ mp_ncpus = 1; return (0); } /* Get number of 'cpu' nodes from FDT */ for (child = OF_child(cpus_node); child != 0; child = OF_peer(child)) { /* Check if child is a CPU */ memset(device_type, 0, sizeof(device_type)); rv = OF_getprop(child, "device_type", device_type, sizeof(device_type) - 1); if (rv < 0) continue; if (strcmp(device_type, "cpu") != 0) continue; fdt_cpu_count++; } /* Get number of CPU cores from SCU register to cross-check with FDT */ rv = bus_space_map(fdtbus_bs_tag, (bus_addr_t)MV_SCU_BASE, MV_SCU_REGS_LEN, 0, &vaddr_scu); if (rv != 0) { /* Default is one core */ mp_ncpus = 1; return (0); } val = bus_space_read_4(fdtbus_bs_tag, vaddr_scu, MV_SCU_REG_CONFIG); bus_space_unmap(fdtbus_bs_tag, vaddr_scu, MV_SCU_REGS_LEN); reg_cpu_count = (val & SCU_CFG_REG_NCPU_MASK) + 1; /* Set mp_ncpus to number of cpus in FDT unless SOC contains only one */ mp_ncpus = min(reg_cpu_count, fdt_cpu_count); /* mp_ncpus must be at least 1 */ mp_ncpus = max(1, mp_ncpus); return (mp_ncpus); } void -platform_mp_setmaxid(void) +mv_a38x_platform_mp_setmaxid(platform_t plate) { /* Armada38x family supports maximum 2 cores */ mp_ncpus = platform_cnt_cpus(); mp_maxid = mp_ncpus - 1; } void -platform_mp_start_ap(void) +mv_a38x_platform_mp_start_ap(platform_t plate) { int rv; /* Write secondary entry address to PMSU register */ rv = pmsu_boot_secondary_cpu(); if (rv != 0) return; /* Release CPU1 from reset */ cpu_reset_deassert(); } Index: head/sys/arm/mv/armada38x/armada38x_pl310.c =================================================================== --- head/sys/arm/mv/armada38x/armada38x_pl310.c (revision 331994) +++ head/sys/arm/mv/armada38x/armada38x_pl310.c (revision 331995) @@ -1,77 +1,82 @@ /*- * Copyright (c) 2017 Stormshield. * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ #include __FBSDID("$FreeBSD$"); /* * The machine-dependent part of the arm/pl310 driver for Armada 38x SoCs. */ #include #include #include #include #include #include #include #include #include +#include +#include +#include "armada38x_pl310.h" +#include "platform_pl310_if.h" + void -platform_pl310_init(struct pl310_softc *sc) +mv_a38x_platform_pl310_init(platform_t plat, struct pl310_softc *sc) { uint32_t reg; /* * Enable power saving modes: * - Dynamic Gating stops the clock when the controller is idle. */ reg = pl310_read4(sc, PL310_POWER_CTRL); reg |= POWER_CTRL_ENABLE_GATING; pl310_write4(sc, PL310_POWER_CTRL, reg); pl310_write4(sc, PL310_PREFETCH_CTRL, PREFETCH_CTRL_DL | PREFETCH_CTRL_DATA_PREFETCH | PREFETCH_CTRL_INCR_DL | PREFETCH_CTRL_DL_ON_WRAP); /* Disable L2 cache sync for IO coherent operation */ sc->sc_io_coherent = true; } void -platform_pl310_write_ctrl(struct pl310_softc *sc, uint32_t val) +mv_a38x_platform_pl310_write_ctrl(platform_t plat, struct pl310_softc *sc, uint32_t val) { pl310_write4(sc, PL310_CTRL, val); } void -platform_pl310_write_debug(struct pl310_softc *sc, uint32_t val) +mv_a38x_platform_pl310_write_debug(platform_t plat, struct pl310_softc *sc, uint32_t val) { pl310_write4(sc, PL310_DEBUG_CTRL, val); } Index: head/sys/arm/mv/armada38x/armada38x_pl310.h =================================================================== --- head/sys/arm/mv/armada38x/armada38x_pl310.h (nonexistent) +++ head/sys/arm/mv/armada38x/armada38x_pl310.h (revision 331995) @@ -0,0 +1,37 @@ +/*- + * Copyright (c) 2017 Semihalf. + * Copyright (c) 2017 Stormshield. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * $FreeBSD$ + */ + +#ifndef ARMADA38X_PL310_H +#define ARMADA38X_PL310_H +#include + +void mv_a38x_platform_pl310_init(platform_t plat, struct pl310_softc *sc); +void mv_a38x_platform_pl310_write_ctrl(platform_t plat, struct pl310_softc *sc, uint32_t val); +void mv_a38x_platform_pl310_write_debug(platform_t plat, struct pl310_softc *sc, uint32_t val); + +#endif Property changes on: head/sys/arm/mv/armada38x/armada38x_pl310.h ___________________________________________________________________ Added: svn:keywords ## -0,0 +1 ## +FreeBSD=%H \ No newline at end of property Index: head/sys/arm/mv/armada38x/std.armada38x =================================================================== --- head/sys/arm/mv/armada38x/std.armada38x (revision 331994) +++ head/sys/arm/mv/armada38x/std.armada38x (revision 331995) @@ -1,11 +1,9 @@ # $FreeBSD$ -files "../mv/armada38x/files.armada38x" -files "../mv/files.mv" files "../mv/files.arm7" cpu CPU_CORTEXA machine arm armv7 makeoptions CONF_CFLAGS="-march=armv7a" options IPI_IRQ_START=0 options IPI_IRQ_END=15 Index: head/sys/arm/mv/armadaxp/armadaxp_mp.c =================================================================== --- head/sys/arm/mv/armadaxp/armadaxp_mp.c (revision 331994) +++ head/sys/arm/mv/armadaxp/armadaxp_mp.c (revision 331995) @@ -1,178 +1,183 @@ /*- * SPDX-License-Identifier: BSD-2-Clause-FreeBSD * * Copyright (c) 2011 Semihalf. * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. * * $FreeBSD$ */ #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include +#include + #define MV_AXP_CPU_DIVCLK_BASE (MV_BASE + 0x18700) #define CPU_DIVCLK_CTRL0 0x00 #define CPU_DIVCLK_CTRL2_RATIO_FULL0 0x08 #define CPU_DIVCLK_CTRL2_RATIO_FULL1 0x0c #define CPU_DIVCLK_MASK(x) (~(0xff << (8 * (x)))) #define CPU_PMU(x) (MV_BASE + 0x22100 + (0x100 * (x))) #define CPU_PMU_BOOT 0x24 #define MP (MV_BASE + 0x20800) #define MP_SW_RESET(x) ((x) * 8) #define CPU_RESUME_CONTROL (0x20988) void armadaxp_init_coher_fabric(void); int platform_get_ncpus(void); +void mv_axp_platform_mp_setmaxid(platform_t plat); +void mv_axp_platform_mp_start_ap(platform_t plat); + /* Coherency Fabric registers */ static uint32_t read_cpu_clkdiv(uint32_t reg) { return (bus_space_read_4(fdtbus_bs_tag, MV_AXP_CPU_DIVCLK_BASE, reg)); } static void write_cpu_clkdiv(uint32_t reg, uint32_t val) { bus_space_write_4(fdtbus_bs_tag, MV_AXP_CPU_DIVCLK_BASE, reg, val); } void -platform_mp_setmaxid(void) +mv_axp_platform_mp_setmaxid(platform_t plat) { mp_ncpus = platform_get_ncpus(); mp_maxid = mp_ncpus - 1; } void mptramp(void); void mptramp_end(void); extern vm_offset_t mptramp_pmu_boot; void -platform_mp_start_ap(void) +mv_axp_platform_mp_start_ap(platform_t plat) { uint32_t reg, *src, *dst, cpu_num, div_val, cputype; vm_offset_t pmu_boot_off; /* * Initialization procedure depends on core revision, * in this step CHIP ID is checked to choose proper procedure */ cputype = cpu_ident(); cputype &= CPU_ID_CPU_MASK; /* * Set the PA of CPU0 Boot Address Redirect register used in * mptramp according to the actual SoC registers' base address. */ pmu_boot_off = (CPU_PMU(0) - MV_BASE) + CPU_PMU_BOOT; mptramp_pmu_boot = fdt_immr_pa + pmu_boot_off; dst = pmap_mapdev(0xffff0000, PAGE_SIZE); for (src = (uint32_t *)mptramp; src < (uint32_t *)mptramp_end; src++, dst++) { *dst = *src; } pmap_unmapdev((vm_offset_t)dst, PAGE_SIZE); if (cputype == CPU_ID_MV88SV584X_V7) { /* Core rev A0 */ div_val = read_cpu_clkdiv(CPU_DIVCLK_CTRL2_RATIO_FULL1); div_val &= 0x3f; for (cpu_num = 1; cpu_num < mp_ncpus; cpu_num++ ) { reg = read_cpu_clkdiv(CPU_DIVCLK_CTRL2_RATIO_FULL1); reg &= CPU_DIVCLK_MASK(cpu_num); reg |= div_val << (cpu_num * 8); write_cpu_clkdiv(CPU_DIVCLK_CTRL2_RATIO_FULL1, reg); } } else { /* Core rev Z1 */ div_val = 0x01; if (mp_ncpus > 1) { reg = read_cpu_clkdiv(CPU_DIVCLK_CTRL2_RATIO_FULL0); reg &= CPU_DIVCLK_MASK(3); reg |= div_val << 24; write_cpu_clkdiv(CPU_DIVCLK_CTRL2_RATIO_FULL0, reg); } for (cpu_num = 2; cpu_num < mp_ncpus; cpu_num++ ) { reg = read_cpu_clkdiv(CPU_DIVCLK_CTRL2_RATIO_FULL1); reg &= CPU_DIVCLK_MASK(cpu_num); reg |= div_val << (cpu_num * 8); write_cpu_clkdiv(CPU_DIVCLK_CTRL2_RATIO_FULL1, reg); } } reg = read_cpu_clkdiv(CPU_DIVCLK_CTRL0); reg |= ((0x1 << (mp_ncpus - 1)) - 1) << 21; write_cpu_clkdiv(CPU_DIVCLK_CTRL0, reg); reg = read_cpu_clkdiv(CPU_DIVCLK_CTRL0); reg |= 0x01000000; write_cpu_clkdiv(CPU_DIVCLK_CTRL0, reg); DELAY(100); reg &= ~(0xf << 21); write_cpu_clkdiv(CPU_DIVCLK_CTRL0, reg); DELAY(100); bus_space_write_4(fdtbus_bs_tag, MV_BASE, CPU_RESUME_CONTROL, 0); for (cpu_num = 1; cpu_num < mp_ncpus; cpu_num++ ) bus_space_write_4(fdtbus_bs_tag, CPU_PMU(cpu_num), CPU_PMU_BOOT, pmap_kextract((vm_offset_t)mpentry)); dcache_wbinv_poc_all(); for (cpu_num = 1; cpu_num < mp_ncpus; cpu_num++ ) bus_space_write_4(fdtbus_bs_tag, MP, MP_SW_RESET(cpu_num), 0); /* XXX: Temporary workaround for hangup after releasing AP's */ wmb(); DELAY(10); armadaxp_init_coher_fabric(); } Index: head/sys/arm/mv/armadaxp/std.mv78x60 =================================================================== --- head/sys/arm/mv/armadaxp/std.mv78x60 (revision 331994) +++ head/sys/arm/mv/armadaxp/std.mv78x60 (revision 331995) @@ -1,5 +1,4 @@ # $FreeBSD$ include "../mv/std-pj4b.mv" include "../mv/armadaxp/std.armadaxp" -files "../mv/armadaxp/files.armadaxp" Index: head/sys/arm/mv/armv5_machdep.c =================================================================== --- head/sys/arm/mv/armv5_machdep.c (nonexistent) +++ head/sys/arm/mv/armv5_machdep.c (revision 331995) @@ -0,0 +1,499 @@ +/*- + * SPDX-License-Identifier: BSD-2-Clause-FreeBSD + * + * Copyright (c) 1994-1998 Mark Brinicombe. + * Copyright (c) 1994 Brini. + * All rights reserved. + * + * This code is derived from software written for Brini by Mark Brinicombe + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. All advertising materials mentioning features or use of this software + * must display the following acknowledgement: + * This product includes software developed by Brini. + * 4. The name of the company nor the name of the author may be used to + * endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY BRINI ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL BRINI OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, + * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * from: FreeBSD: //depot/projects/arm/src/sys/arm/at91/kb920x_machdep.c, rev 45 + */ + +#include "opt_ddb.h" +#include "opt_platform.h" + +#include +__FBSDID("$FreeBSD$"); + +#define _ARM32_BUS_DMA_PRIVATE +#include +#include +#include +#include +#include + +#include +#include + +#include +#include + +#include +#include +#include +#include + +#include + +#include /* XXX */ +#include /* XXX eventually this should be eliminated */ +#include + +#include +#include + +static int platform_mpp_init(void); +void cpu_reset(void); + +#define MPP_PIN_MAX 68 +#define MPP_PIN_CELLS 2 +#define MPP_PINS_PER_REG 8 +#define MPP_SEL(pin,func) (((func) & 0xf) << \ + (((pin) % MPP_PINS_PER_REG) * 4)) + +static void +mv_busdma_tag_init(void *arg __unused) +{ + phandle_t node; + bus_dma_tag_t dmat; + + /* + * If this platform has coherent DMA, create the parent DMA tag to pass + * down the coherent flag to all busses and devices on the platform, + * otherwise return without doing anything. By default create tag + * for all A38x-based platforms only. + */ + if ((node = OF_finddevice("/")) == -1) + return; + if (ofw_bus_node_is_compatible(node, "marvell,armada380") == 0) + return; + + bus_dma_tag_create(NULL, /* No parent tag */ + 1, 0, /* alignment, bounds */ + BUS_SPACE_MAXADDR, /* lowaddr */ + BUS_SPACE_MAXADDR, /* highaddr */ + NULL, NULL, /* filter, filterarg */ + BUS_SPACE_MAXSIZE, /* maxsize */ + BUS_SPACE_UNRESTRICTED, /* nsegments */ + BUS_SPACE_MAXSIZE, /* maxsegsize */ + BUS_DMA_COHERENT, /* flags */ + NULL, NULL, /* lockfunc, lockarg */ + &dmat); + + nexus_set_dma_tag(dmat); +} +SYSINIT(mv_busdma_tag, SI_SUB_DRIVERS, SI_ORDER_ANY, mv_busdma_tag_init, NULL); + +static int +platform_mpp_init(void) +{ + pcell_t pinmap[MPP_PIN_MAX * MPP_PIN_CELLS]; + int mpp[MPP_PIN_MAX]; + uint32_t ctrl_val, ctrl_offset; + pcell_t reg[4]; + u_long start, size; + phandle_t node; + pcell_t pin_cells, *pinmap_ptr, pin_count; + ssize_t len; + int par_addr_cells, par_size_cells; + int tuple_size, tuples, rv, pins, i, j; + int mpp_pin, mpp_function; + + /* + * Try to access the MPP node directly i.e. through /aliases/mpp. + */ + if ((node = OF_finddevice("mpp")) != -1) + if (ofw_bus_node_is_compatible(node, "mrvl,mpp")) + goto moveon; + /* + * Find the node the long way. + */ + if ((node = OF_finddevice("/")) == -1) + return (ENXIO); + + if ((node = fdt_find_compatible(node, "simple-bus", 0)) == 0) + return (ENXIO); + + if ((node = fdt_find_compatible(node, "mrvl,mpp", 0)) == 0) + /* + * No MPP node. Fall back to how MPP got set by the + * first-stage loader and try to continue booting. + */ + return (0); +moveon: + /* + * Process 'reg' prop. + */ + if ((rv = fdt_addrsize_cells(OF_parent(node), &par_addr_cells, + &par_size_cells)) != 0) + return(ENXIO); + + tuple_size = sizeof(pcell_t) * (par_addr_cells + par_size_cells); + len = OF_getprop(node, "reg", reg, sizeof(reg)); + tuples = len / tuple_size; + if (tuple_size <= 0) + return (EINVAL); + + /* + * Get address/size. XXX we assume only the first 'reg' tuple is used. + */ + rv = fdt_data_to_res(reg, par_addr_cells, par_size_cells, + &start, &size); + if (rv != 0) + return (rv); + start += fdt_immr_va; + + /* + * Process 'pin-count' and 'pin-map' props. + */ + if (OF_getencprop(node, "pin-count", &pin_count, sizeof(pin_count)) <= 0) + return (ENXIO); + if (pin_count > MPP_PIN_MAX) + return (ERANGE); + + if (OF_getencprop(node, "#pin-cells", &pin_cells, sizeof(pin_cells)) <= 0) + pin_cells = MPP_PIN_CELLS; + if (pin_cells > MPP_PIN_CELLS) + return (ERANGE); + tuple_size = sizeof(pcell_t) * pin_cells; + + bzero(pinmap, sizeof(pinmap)); + len = OF_getencprop(node, "pin-map", pinmap, sizeof(pinmap)); + if (len <= 0) + return (ERANGE); + if (len % tuple_size) + return (ERANGE); + pins = len / tuple_size; + if (pins > pin_count) + return (ERANGE); + /* + * Fill out a "mpp[pin] => function" table. All pins unspecified in + * the 'pin-map' property are defaulted to 0 function i.e. GPIO. + */ + bzero(mpp, sizeof(mpp)); + pinmap_ptr = pinmap; + for (i = 0; i < pins; i++) { + mpp_pin = *pinmap_ptr; + mpp_function = *(pinmap_ptr + 1); + mpp[mpp_pin] = mpp_function; + pinmap_ptr += pin_cells; + } + + /* + * Prepare and program MPP control register values. + */ + ctrl_offset = 0; + for (i = 0; i < pin_count;) { + ctrl_val = 0; + + for (j = 0; j < MPP_PINS_PER_REG; j++) { + if (i + j == pin_count - 1) + break; + ctrl_val |= MPP_SEL(i + j, mpp[i + j]); + } + i += MPP_PINS_PER_REG; + bus_space_write_4(fdtbus_bs_tag, start, ctrl_offset, + ctrl_val); + +#if defined(SOC_MV_ORION) + /* + * Third MPP reg on Orion SoC is placed + * non-linearly (with different offset). + */ + if (i == (2 * MPP_PINS_PER_REG)) + ctrl_offset = 0x50; + else +#endif + ctrl_offset += 4; + } + + return (0); +} + +vm_offset_t +platform_lastaddr(void) +{ + + return (fdt_immr_va); +} + +void +platform_probe_and_attach(void) +{ + + if (fdt_immr_addr(MV_BASE) != 0) + while (1); +} + +void +platform_gpio_init(void) +{ + + /* + * Re-initialise MPP. It is important to call this prior to using + * console as the physical connection can be routed via MPP. + */ + if (platform_mpp_init() != 0) + while (1); +} + +void +platform_late_init(void) +{ + /* + * Re-initialise decode windows + */ + if (mv_check_soc_family() == MV_SOC_UNSUPPORTED) + panic("Unsupported SoC family\n"); + + if (soc_decode_win() != 0) + printf("WARNING: could not re-initialise decode windows! " + "Running with existing settings...\n"); +} +#define FDT_DEVMAP_MAX (MV_WIN_CPU_MAX + 2) +static struct devmap_entry fdt_devmap[FDT_DEVMAP_MAX] = { + { 0, 0, 0, } +}; + +static int +platform_sram_devmap(struct devmap_entry *map) +{ + phandle_t child, root; + u_long base, size; + /* + * SRAM range. + */ + if ((root = OF_finddevice("/")) == 0) + return (ENXIO); + + if ((child = OF_finddevice("/sram")) != 0) + if (ofw_bus_node_is_compatible(child, "mrvl,cesa-sram") || + ofw_bus_node_is_compatible(child, "mrvl,scratchpad")) + goto moveon; + + if ((child = fdt_find_compatible(root, "mrvl,cesa-sram", 0)) == 0 && + (child = fdt_find_compatible(root, "mrvl,scratchpad", 0)) == 0) + goto out; + +moveon: + if (fdt_regsize(child, &base, &size) != 0) + return (EINVAL); + + map->pd_va = MV_CESA_SRAM_BASE; /* XXX */ + map->pd_pa = base; + map->pd_size = size; + + return (0); +out: + return (ENOENT); + +} + +/* + * Supply a default do-nothing implementation of mv_pci_devmap() via a weak + * alias. Many Marvell platforms don't support a PCI interface, but to support + * those that do, we end up with a reference to this function below, in + * platform_devmap_init(). If "device pci" appears in the kernel config, the + * real implementation of this function in arm/mv/mv_pci.c overrides the weak + * alias defined here. + */ +int mv_default_fdt_pci_devmap(phandle_t node, struct devmap_entry *devmap, + vm_offset_t io_va, vm_offset_t mem_va); +int +mv_default_fdt_pci_devmap(phandle_t node, struct devmap_entry *devmap, + vm_offset_t io_va, vm_offset_t mem_va) +{ + + return (0); +} +__weak_reference(mv_default_fdt_pci_devmap, mv_pci_devmap); + +/* + * XXX: When device entry in devmap has pd_size smaller than section size, + * system will freeze during initialization + */ + +/* + * Construct devmap table with DT-derived config data. + */ +int +platform_devmap_init(void) +{ + phandle_t root, child; + pcell_t bank_count; + int i, num_mapped; + + i = 0; + devmap_register_table(&fdt_devmap[0]); + + if ((root = OF_finddevice("/")) == -1) + return (ENXIO); + + /* + * IMMR range. + */ + fdt_devmap[i].pd_va = fdt_immr_va; + fdt_devmap[i].pd_pa = fdt_immr_pa; + fdt_devmap[i].pd_size = fdt_immr_size; + i++; + + /* + * SRAM range. + */ + if (i < FDT_DEVMAP_MAX) + if (platform_sram_devmap(&fdt_devmap[i]) == 0) + i++; + + /* + * PCI range(s). + * PCI range(s) and localbus. + */ + for (child = OF_child(root); child != 0; child = OF_peer(child)) { + if (fdt_is_type(child, "pci") || fdt_is_type(child, "pciep")) { + /* + * Check space: each PCI node will consume 2 devmap + * entries. + */ + if (i + 1 >= FDT_DEVMAP_MAX) + return (ENOMEM); + + /* + * XXX this should account for PCI and multiple ranges + * of a given kind. + */ + if (mv_pci_devmap(child, &fdt_devmap[i], MV_PCI_VA_IO_BASE, + MV_PCI_VA_MEM_BASE) != 0) + return (ENXIO); + i += 2; + } + + if (ofw_bus_node_is_compatible(child, "mrvl,lbc")) { + /* Check available space */ + if (OF_getencprop(child, "bank-count", &bank_count, + sizeof(bank_count)) <= 0) + /* If no property, use default value */ + bank_count = 1; + + if ((i + bank_count) >= FDT_DEVMAP_MAX) + return (ENOMEM); + + /* Add all localbus ranges to device map */ + num_mapped = 0; + + if (fdt_localbus_devmap(child, &fdt_devmap[i], + (int)bank_count, &num_mapped) != 0) + return (ENXIO); + + i += num_mapped; + } + } + + return (0); +} + +struct arm32_dma_range * +bus_dma_get_range(void) +{ + + return (NULL); +} + +int +bus_dma_get_range_nb(void) +{ + + return (0); +} + +void +cpu_reset(void) +{ + + write_cpu_ctrl(RSTOUTn_MASK, SOFT_RST_OUT_EN); + write_cpu_ctrl(SYSTEM_SOFT_RESET, SYS_SOFT_RST); + while(1); +} + +#ifdef DDB +#include + +DB_SHOW_COMMAND(cp15, db_show_cp15) +{ + u_int reg; + + __asm __volatile("mrc p15, 0, %0, c0, c0, 0" : "=r" (reg)); + db_printf("Cpu ID: 0x%08x\n", reg); + __asm __volatile("mrc p15, 0, %0, c0, c0, 1" : "=r" (reg)); + db_printf("Current Cache Lvl ID: 0x%08x\n",reg); + + reg = cp15_sctlr_get(); + db_printf("Ctrl: 0x%08x\n",reg); + reg = cp15_actlr_get(); + db_printf("Aux Ctrl: 0x%08x\n",reg); + + __asm __volatile("mrc p15, 0, %0, c0, c1, 0" : "=r" (reg)); + db_printf("Processor Feat 0: 0x%08x\n", reg); + __asm __volatile("mrc p15, 0, %0, c0, c1, 1" : "=r" (reg)); + db_printf("Processor Feat 1: 0x%08x\n", reg); + __asm __volatile("mrc p15, 0, %0, c0, c1, 2" : "=r" (reg)); + db_printf("Debug Feat 0: 0x%08x\n", reg); + __asm __volatile("mrc p15, 0, %0, c0, c1, 3" : "=r" (reg)); + db_printf("Auxiliary Feat 0: 0x%08x\n", reg); + __asm __volatile("mrc p15, 0, %0, c0, c1, 4" : "=r" (reg)); + db_printf("Memory Model Feat 0: 0x%08x\n", reg); + __asm __volatile("mrc p15, 0, %0, c0, c1, 5" : "=r" (reg)); + db_printf("Memory Model Feat 1: 0x%08x\n", reg); + __asm __volatile("mrc p15, 0, %0, c0, c1, 6" : "=r" (reg)); + db_printf("Memory Model Feat 2: 0x%08x\n", reg); + __asm __volatile("mrc p15, 0, %0, c0, c1, 7" : "=r" (reg)); + db_printf("Memory Model Feat 3: 0x%08x\n", reg); + + __asm __volatile("mrc p15, 1, %0, c15, c2, 0" : "=r" (reg)); + db_printf("Aux Func Modes Ctrl 0: 0x%08x\n",reg); + __asm __volatile("mrc p15, 1, %0, c15, c2, 1" : "=r" (reg)); + db_printf("Aux Func Modes Ctrl 1: 0x%08x\n",reg); + + __asm __volatile("mrc p15, 1, %0, c15, c12, 0" : "=r" (reg)); + db_printf("CPU ID code extension: 0x%08x\n",reg); +} + +DB_SHOW_COMMAND(vtop, db_show_vtop) +{ + u_int reg; + + if (have_addr) { + __asm __volatile("mcr p15, 0, %0, c7, c8, 0" : : "r" (addr)); + __asm __volatile("mrc p15, 0, %0, c7, c4, 0" : "=r" (reg)); + db_printf("Physical address reg: 0x%08x\n",reg); + } else + db_printf("show vtop \n"); +} +#endif /* DDB */ Property changes on: head/sys/arm/mv/armv5_machdep.c ___________________________________________________________________ Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:keywords ## -0,0 +1 ## +FreeBSD=%H \ No newline at end of property Added: svn:mime-type ## -0,0 +1 ## +text/plain \ No newline at end of property Index: head/sys/arm/mv/files.arm7 =================================================================== --- head/sys/arm/mv/files.arm7 (revision 331994) +++ head/sys/arm/mv/files.arm7 (revision 331995) @@ -1,3 +1,39 @@ # $FreeBSD$ arm/mv/armada38x/armada38x.c standard arm/mv/armadaxp/armadaxp.c standard + +arm/mv/gpio.c optional gpio +arm/mv/mv_common.c standard +arm/mv/mv_localbus.c standard +arm/mv/mv_armv7_machdep.c standard +arm/mv/mv_pci_ctrl.c optional pci | fdt +arm/mv/mv_pci.c optional pci +arm/mv/mv_ts.c standard +arm/mv/timer.c standard + +arm/mv/mpic.c standard +arm/mv/armada/thermal.c optional fdt +arm/mv/armada/wdt.c optional fdt +arm/mv/armada38x/armada38x_mp.c optional smp +arm/mv/armada38x/pmsu.c standard +arm/mv/armada38x/armada38x_rtc.c standard +arm/mv/armada38x/armada38x_pl310.c optional pl310 +dev/sdhci/sdhci_fdt.c optional sdhci + +arm/mv/rtc.c standard +arm/mv/armadaxp/armadaxp_mp.c optional smp +arm/mv/armadaxp/mptramp.S optional smp +dev/cesa/cesa.c optional cesa +dev/iicbus/twsi/mv_twsi.c optional twsi +dev/mge/if_mge.c optional mge +dev/neta/if_mvneta_fdt.c optional neta fdt +dev/neta/if_mvneta.c optional neta mdio mii +dev/nand/nfc_mv.c optional nand +dev/mvs/mvs_soc.c optional mvs +dev/uart/uart_dev_ns8250.c optional uart +dev/uart/uart_dev_snps.c optional uart +dev/usb/controller/ehci_mv.c optional ehci +dev/usb/controller/xhci_mv.c optional xhci +dev/ahci/ahci_mv_fdt.c optional ahci + +kern/kern_clocksource.c standard Index: head/sys/arm/mv/files.mv =================================================================== --- head/sys/arm/mv/files.mv (revision 331994) +++ head/sys/arm/mv/files.mv (revision 331995) @@ -1,37 +1,37 @@ # $FreeBSD$ # # The Marvell CPU cores # - Compliant with V5TE architecture # - Super scalar dual issue CPU # - Big/Little Endian # - MMU/MPU # - L1 Cache: Supports streaming and write allocate # - Variable pipeline stages # - Out-of-order execution # - Branch Prediction # - JTAG/ICE # - Vector Floating Point (VFP) unit # arm/mv/gpio.c optional gpio arm/mv/mv_common.c standard arm/mv/mv_localbus.c standard -arm/mv/mv_machdep.c standard +arm/mv/armv5_machdep.c standard arm/mv/mv_pci_ctrl.c optional pci | fdt arm/mv/mv_pci.c optional pci arm/mv/mv_ts.c standard arm/mv/timer.c optional !soc_mv_armada38x dev/cesa/cesa.c optional cesa dev/iicbus/twsi/mv_twsi.c optional twsi dev/mge/if_mge.c optional mge dev/neta/if_mvneta_fdt.c optional neta fdt dev/neta/if_mvneta.c optional neta mdio mii dev/nand/nfc_mv.c optional nand dev/mvs/mvs_soc.c optional mvs dev/uart/uart_dev_ns8250.c optional uart dev/uart/uart_dev_snps.c optional uart dev/usb/controller/ehci_mv.c optional ehci dev/usb/controller/xhci_mv.c optional xhci dev/ahci/ahci_mv_fdt.c optional ahci kern/kern_clocksource.c standard Index: head/sys/arm/mv/mv_armv7_machdep.c =================================================================== --- head/sys/arm/mv/mv_armv7_machdep.c (nonexistent) +++ head/sys/arm/mv/mv_armv7_machdep.c (revision 331995) @@ -0,0 +1,482 @@ +/*- + * SPDX-License-Identifier: BSD-2-Clause-FreeBSD + * + * Copyright (c) 2017 Semihalf. + * Copyright (c) 1994-1998 Mark Brinicombe. + * Copyright (c) 1994 Brini. + * All rights reserved. + * + * This code is derived from software written for Brini by Mark Brinicombe + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. All advertising materials mentioning features or use of this software + * must display the following acknowledgement: + * This product includes software developed by Brini. + * 4. The name of the company nor the name of the author may be used to + * endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY BRINI ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL BRINI OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, + * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * from: FreeBSD: //depot/projects/arm/src/sys/arm/at91/kb920x_machdep.c, rev 45 + */ + +#include "opt_ddb.h" +#include "opt_platform.h" + +#include +__FBSDID("$FreeBSD$"); + +#define _ARM32_BUS_DMA_PRIVATE +#include +#include +#include +#include +#include + +#include +#include + +#include +#include + +#include +#include +#include +#include +#include +#include + +#include +#include +#include + +#include +#include + +#include "opt_platform.h" +#include "platform_if.h" + +#if defined(SOC_MV_ARMADA38X) +#include "platform_pl310_if.h" +#include "armada38x/armada38x_pl310.h" +#endif + +static int platform_mpp_init(void); +int armada38x_win_set_iosync_barrier(void); +int armada38x_scu_enable(void); +int armada38x_open_bootrom_win(void); +int armada38x_mbus_optimization(void); + +static vm_offset_t mv_platform_lastaddr(platform_t plate); +static int mv_platform_probe_and_attach(platform_t plate); +static void mv_platform_gpio_init(platform_t plate); +static void mv_cpu_reset(platform_t plat); + +static void mv_a38x_platform_late_init(platform_t plate); +static int mv_a38x_platform_devmap_init(platform_t plate); +static void mv_axp_platform_late_init(platform_t plate); +static int mv_axp_platform_devmap_init(platform_t plate); + +void armadaxp_init_coher_fabric(void); +void armadaxp_l2_init(void); + +#ifdef SMP +void mv_a38x_platform_mp_setmaxid(platform_t plate); +void mv_a38x_platform_mp_start_ap(platform_t plate); +void mv_axp_platform_mp_setmaxid(platform_t plate); +void mv_axp_platform_mp_start_ap(platform_t plate); +#endif + +#define MPP_PIN_MAX 68 +#define MPP_PIN_CELLS 2 +#define MPP_PINS_PER_REG 8 +#define MPP_SEL(pin,func) (((func) & 0xf) << \ + (((pin) % MPP_PINS_PER_REG) * 4)) + +static void +mv_busdma_tag_init(void *arg __unused) +{ + phandle_t node; + bus_dma_tag_t dmat; + + /* + * If this platform has coherent DMA, create the parent DMA tag to pass + * down the coherent flag to all busses and devices on the platform, + * otherwise return without doing anything. By default create tag + * for all A38x-based platforms only. + */ + if ((node = OF_finddevice("/")) == -1){ + printf("no tree\n"); + return; + } + + if (ofw_bus_node_is_compatible(node, "marvell,armada380") == 0) + return; + + bus_dma_tag_create(NULL, /* No parent tag */ + 1, 0, /* alignment, bounds */ + BUS_SPACE_MAXADDR, /* lowaddr */ + BUS_SPACE_MAXADDR, /* highaddr */ + NULL, NULL, /* filter, filterarg */ + BUS_SPACE_MAXSIZE, /* maxsize */ + BUS_SPACE_UNRESTRICTED, /* nsegments */ + BUS_SPACE_MAXSIZE, /* maxsegsize */ + BUS_DMA_COHERENT, /* flags */ + NULL, NULL, /* lockfunc, lockarg */ + &dmat); + + nexus_set_dma_tag(dmat); + +} +SYSINIT(mv_busdma_tag, SI_SUB_DRIVERS, SI_ORDER_ANY, mv_busdma_tag_init, NULL); + +static int +platform_mpp_init(void) +{ + pcell_t pinmap[MPP_PIN_MAX * MPP_PIN_CELLS]; + int mpp[MPP_PIN_MAX]; + uint32_t ctrl_val, ctrl_offset; + pcell_t reg[4]; + u_long start, size; + phandle_t node; + pcell_t pin_cells, *pinmap_ptr, pin_count; + ssize_t len; + int par_addr_cells, par_size_cells; + int tuple_size, tuples, rv, pins, i, j; + int mpp_pin, mpp_function; + + /* + * Try to access the MPP node directly i.e. through /aliases/mpp. + */ + if ((node = OF_finddevice("mpp")) != -1) + if (ofw_bus_node_is_compatible(node, "mrvl,mpp")) + goto moveon; + /* + * Find the node the long way. + */ + if ((node = OF_finddevice("/")) == -1) + return (ENXIO); + + if ((node = fdt_find_compatible(node, "simple-bus", 0)) == 0) + return (ENXIO); + + if ((node = fdt_find_compatible(node, "mrvl,mpp", 0)) == 0) + /* + * No MPP node. Fall back to how MPP got set by the + * first-stage loader and try to continue booting. + */ + return (0); +moveon: + /* + * Process 'reg' prop. + */ + if ((rv = fdt_addrsize_cells(OF_parent(node), &par_addr_cells, + &par_size_cells)) != 0) + return(ENXIO); + + tuple_size = sizeof(pcell_t) * (par_addr_cells + par_size_cells); + len = OF_getprop(node, "reg", reg, sizeof(reg)); + tuples = len / tuple_size; + if (tuple_size <= 0) + return (EINVAL); + + rv = fdt_data_to_res(reg, par_addr_cells, par_size_cells, + &start, &size); + if (rv != 0) + return (rv); + start += fdt_immr_va; + + /* + * Process 'pin-count' and 'pin-map' props. + */ + if (OF_getencprop(node, "pin-count", &pin_count, sizeof(pin_count)) <= 0) + return (ENXIO); + if (pin_count > MPP_PIN_MAX) + return (ERANGE); + + if (OF_getencprop(node, "#pin-cells", &pin_cells, sizeof(pin_cells)) <= 0) + pin_cells = MPP_PIN_CELLS; + if (pin_cells > MPP_PIN_CELLS) + return (ERANGE); + tuple_size = sizeof(pcell_t) * pin_cells; + + bzero(pinmap, sizeof(pinmap)); + len = OF_getencprop(node, "pin-map", pinmap, sizeof(pinmap)); + if (len <= 0) + return (ERANGE); + if (len % tuple_size) + return (ERANGE); + pins = len / tuple_size; + if (pins > pin_count) + return (ERANGE); + /* + * Fill out a "mpp[pin] => function" table. All pins unspecified in + * the 'pin-map' property are defaulted to 0 function i.e. GPIO. + */ + bzero(mpp, sizeof(mpp)); + pinmap_ptr = pinmap; + for (i = 0; i < pins; i++) { + mpp_pin = *pinmap_ptr; + mpp_function = *(pinmap_ptr + 1); + mpp[mpp_pin] = mpp_function; + pinmap_ptr += pin_cells; + } + + /* + * Prepare and program MPP control register values. + */ + ctrl_offset = 0; + for (i = 0; i < pin_count;) { + ctrl_val = 0; + + for (j = 0; j < MPP_PINS_PER_REG; j++) { + if (i + j == pin_count - 1) + break; + ctrl_val |= MPP_SEL(i + j, mpp[i + j]); + } + i += MPP_PINS_PER_REG; + bus_space_write_4(fdtbus_bs_tag, start, ctrl_offset, + ctrl_val); + + ctrl_offset += 4; + } + + return (0); +} + +static vm_offset_t +mv_platform_lastaddr(platform_t plat) +{ + + return (fdt_immr_va); +} + +static int +mv_platform_probe_and_attach(platform_t plate) +{ + + if (fdt_immr_addr(MV_BASE) != 0) + while (1); + return (0); +} + +static void +mv_platform_gpio_init(platform_t plate) +{ + + /* + * Re-initialise MPP. It is important to call this prior to using + * console as the physical connection can be routed via MPP. + */ + if (platform_mpp_init() != 0) + while (1); +} + +static void +mv_a38x_platform_late_init(platform_t plate) +{ + + /* + * Re-initialise decode windows + */ + if (mv_check_soc_family() == MV_SOC_UNSUPPORTED) + panic("Unsupported SoC family\n"); + + if (soc_decode_win() != 0) + printf("WARNING: could not re-initialise decode windows! " + "Running with existing settings...\n"); + + /* Configure timers' base frequency */ + arm_tmr_change_frequency(get_cpu_freq() / 2); + + /* + * Workaround for Marvell Armada38X family HW issue + * between Cortex-A9 CPUs and on-chip devices that may + * cause hang on heavy load. + * To avoid that, map all registers including PCIe IO + * as strongly ordered instead of device memory. + */ + pmap_remap_vm_attr(VM_MEMATTR_DEVICE, VM_MEMATTR_SO); + + /* Set IO Sync Barrier bit for all Mbus devices */ + if (armada38x_win_set_iosync_barrier() != 0) + printf("WARNING: could not map CPU Subsystem registers\n"); + if (armada38x_mbus_optimization() != 0) + printf("WARNING: could not enable mbus optimization\n"); + if (armada38x_scu_enable() != 0) + printf("WARNING: could not enable SCU\n"); +#ifdef SMP + /* Open window to bootROM memory - needed for SMP */ + if (armada38x_open_bootrom_win() != 0) + printf("WARNING: could not open window to bootROM\n"); +#endif +} + +static void +mv_axp_platform_late_init(platform_t plate) +{ + phandle_t node; + /* + * Re-initialise decode windows + */ + if (soc_decode_win() != 0) + printf("WARNING: could not re-initialise decode windows! " + "Running with existing settings...\n"); + if ((node = OF_finddevice("/")) == -1) + return; + +#if !defined(SMP) + /* For SMP case it should be initialized after APs are booted */ + armadaxp_init_coher_fabric(); +#endif + armadaxp_l2_init(); +} + +#define FDT_DEVMAP_MAX (MV_WIN_CPU_MAX_ARMV7 + 2) +static struct devmap_entry fdt_devmap[FDT_DEVMAP_MAX] = { + { 0, 0, 0, } +}; + +static int +platform_sram_devmap(struct devmap_entry *map) +{ + + return (ENOENT); +} + +/* + * Construct devmap table with DT-derived config data. + */ +static int +mv_a38x_platform_devmap_init(platform_t plat) +{ + phandle_t root, child; + int i; + + i = 0; + devmap_register_table(&fdt_devmap[0]); + + if ((root = OF_finddevice("/")) == -1) + return (ENXIO); + + /* + * IMMR range. + */ + fdt_devmap[i].pd_va = fdt_immr_va; + fdt_devmap[i].pd_pa = fdt_immr_pa; + fdt_devmap[i].pd_size = fdt_immr_size; + i++; + + /* + * SRAM range. + */ + if (i < FDT_DEVMAP_MAX) + if (platform_sram_devmap(&fdt_devmap[i]) == 0) + i++; + + /* + * PCI range(s). + * PCI range(s) and localbus. + */ + for (child = OF_child(root); child != 0; child = OF_peer(child)) { + if (fdt_is_type(child, "pci") || fdt_is_type(child, "pciep")) { + /* + * Check space: each PCI node will consume 2 devmap + * entries. + */ + if (i + 1 >= FDT_DEVMAP_MAX) + return (ENOMEM); + + if (mv_pci_devmap(child, &fdt_devmap[i], MV_PCI_VA_IO_BASE, + MV_PCI_VA_MEM_BASE) != 0) + return (ENXIO); + i += 2; + } + } + + return (0); +} + +static int +mv_axp_platform_devmap_init(platform_t plate) +{ + vm_paddr_t cur_immr_pa; + + /* + * Acquire SoC registers' base passed by u-boot and fill devmap + * accordingly. DTB is going to be modified basing on this data + * later. + */ + __asm __volatile("mrc p15, 4, %0, c15, c0, 0" : "=r" (cur_immr_pa)); + cur_immr_pa = (cur_immr_pa << 13) & 0xff000000; + if (cur_immr_pa != 0) + fdt_immr_pa = cur_immr_pa; + + mv_a38x_platform_devmap_init(plate); + + return (0); +} + +static void +mv_cpu_reset(platform_t plat) +{ + + write_cpu_misc(RSTOUTn_MASK, SOFT_RST_OUT_EN); + write_cpu_misc(SYSTEM_SOFT_RESET, SYS_SOFT_RST); +} + +#if defined(SOC_MV_ARMADA38X) +static platform_method_t mv_a38x_methods[] = { + PLATFORMMETHOD(platform_devmap_init, mv_a38x_platform_devmap_init), + PLATFORMMETHOD(platform_cpu_reset, mv_cpu_reset), + PLATFORMMETHOD(platform_lastaddr, mv_platform_lastaddr), + PLATFORMMETHOD(platform_attach, mv_platform_probe_and_attach), + PLATFORMMETHOD(platform_gpio_init, mv_platform_gpio_init), + PLATFORMMETHOD(platform_late_init, mv_a38x_platform_late_init), + PLATFORMMETHOD(platform_pl310_init, mv_a38x_platform_pl310_init), + PLATFORMMETHOD(platform_pl310_write_ctrl, mv_a38x_platform_pl310_write_ctrl), + PLATFORMMETHOD(platform_pl310_write_debug, mv_a38x_platform_pl310_write_debug), +#ifdef SMP + PLATFORMMETHOD(platform_mp_start_ap, mv_a38x_platform_mp_start_ap), + PLATFORMMETHOD(platform_mp_setmaxid, mv_a38x_platform_mp_setmaxid), +#endif + + PLATFORMMETHOD_END, +}; +FDT_PLATFORM_DEF(mv_a38x, "mv_a38x", 0, "marvell,armada380", 100); +#endif + +static platform_method_t mv_axp_methods[] = { + PLATFORMMETHOD(platform_devmap_init, mv_axp_platform_devmap_init), + PLATFORMMETHOD(platform_cpu_reset, mv_cpu_reset), + PLATFORMMETHOD(platform_lastaddr, mv_platform_lastaddr), + PLATFORMMETHOD(platform_attach, mv_platform_probe_and_attach), + PLATFORMMETHOD(platform_gpio_init, mv_platform_gpio_init), + PLATFORMMETHOD(platform_late_init, mv_axp_platform_late_init), +#ifdef SMP + PLATFORMMETHOD(platform_mp_start_ap, mv_axp_platform_mp_start_ap), + PLATFORMMETHOD(platform_mp_setmaxid, mv_axp_platform_mp_setmaxid), +#endif + + PLATFORMMETHOD_END, +}; +FDT_PLATFORM_DEF(mv_axp, "mv_axp", 0, "marvell,armadaxp", 100); + Property changes on: head/sys/arm/mv/mv_armv7_machdep.c ___________________________________________________________________ Added: svn:keywords ## -0,0 +1 ## +FreeBSD=%H \ No newline at end of property Index: head/sys/arm/mv/mv_common.c =================================================================== --- head/sys/arm/mv/mv_common.c (revision 331994) +++ head/sys/arm/mv/mv_common.c (revision 331995) @@ -1,3015 +1,3001 @@ /*- * SPDX-License-Identifier: BSD-3-Clause * * Copyright (C) 2008-2011 MARVELL INTERNATIONAL LTD. * All rights reserved. * * Developed by Semihalf. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * 3. Neither the name of MARVELL nor the names of contributors * may be used to endorse or promote products derived from this software * without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. */ #include __FBSDID("$FreeBSD$"); #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include MALLOC_DEFINE(M_IDMA, "idma", "idma dma test memory"); #define IDMA_DEBUG #undef IDMA_DEBUG #define MAX_CPU_WIN 5 #ifdef DEBUG #define debugf(fmt, args...) do { printf("%s(): ", __func__); \ printf(fmt,##args); } while (0) #else #define debugf(fmt, args...) #endif #ifdef DEBUG #define MV_DUMP_WIN 1 #else #define MV_DUMP_WIN 0 #endif static enum soc_family soc_family; static int mv_win_cesa_attr(int wng_sel); static int mv_win_cesa_attr_armv5(int eng_sel); static int mv_win_cesa_attr_armada38x(int eng_sel); static int mv_win_cesa_attr_armadaxp(int eng_sel); uint32_t read_cpu_ctrl_armv5(uint32_t reg); uint32_t read_cpu_ctrl_armv7(uint32_t reg); void write_cpu_ctrl_armv5(uint32_t reg, uint32_t val); void write_cpu_ctrl_armv7(uint32_t reg, uint32_t val); static int win_eth_can_remap(int i); static int decode_win_cesa_valid(void); static int decode_win_cpu_valid(void); static int decode_win_usb_valid(void); static int decode_win_usb3_valid(void); static int decode_win_eth_valid(void); static int decode_win_pcie_valid(void); static int decode_win_sata_valid(void); static int decode_win_sdhci_valid(void); static int decode_win_idma_valid(void); static int decode_win_xor_valid(void); static void decode_win_cpu_setup(void); static int decode_win_sdram_fixup(void); static void decode_win_cesa_setup(u_long); static void decode_win_usb_setup(u_long); static void decode_win_usb3_setup(u_long); static void decode_win_eth_setup(u_long); static void decode_win_neta_setup(u_long); static void decode_win_sata_setup(u_long); static void decode_win_ahci_setup(u_long); static void decode_win_sdhci_setup(u_long); static void decode_win_idma_setup(u_long); static void decode_win_xor_setup(u_long); static void decode_win_cesa_dump(u_long); static void decode_win_usb_dump(u_long); static void decode_win_usb3_dump(u_long); static void decode_win_eth_dump(u_long base); static void decode_win_neta_dump(u_long base); static void decode_win_idma_dump(u_long base); static void decode_win_xor_dump(u_long base); static void decode_win_ahci_dump(u_long base); static void decode_win_sdhci_dump(u_long); static void decode_win_pcie_dump(u_long); static uint32_t win_cpu_cr_read(int); static uint32_t win_cpu_armv5_cr_read(int); static uint32_t win_cpu_armv7_cr_read(int); static uint32_t win_cpu_br_read(int); static uint32_t win_cpu_armv5_br_read(int); static uint32_t win_cpu_armv7_br_read(int); static uint32_t win_cpu_remap_l_read(int); static uint32_t win_cpu_armv5_remap_l_read(int); static uint32_t win_cpu_armv7_remap_l_read(int); static uint32_t win_cpu_remap_h_read(int); static uint32_t win_cpu_armv5_remap_h_read(int); static uint32_t win_cpu_armv7_remap_h_read(int); static void win_cpu_cr_write(int, uint32_t); static void win_cpu_armv5_cr_write(int, uint32_t); static void win_cpu_armv7_cr_write(int, uint32_t); static void win_cpu_br_write(int, uint32_t); static void win_cpu_armv5_br_write(int, uint32_t); static void win_cpu_armv7_br_write(int, uint32_t); static void win_cpu_remap_l_write(int, uint32_t); static void win_cpu_armv5_remap_l_write(int, uint32_t); static void win_cpu_armv7_remap_l_write(int, uint32_t); static void win_cpu_remap_h_write(int, uint32_t); static void win_cpu_armv5_remap_h_write(int, uint32_t); static void win_cpu_armv7_remap_h_write(int, uint32_t); static uint32_t ddr_br_read(int); static uint32_t ddr_sz_read(int); static uint32_t ddr_armv5_br_read(int); static uint32_t ddr_armv5_sz_read(int); static uint32_t ddr_armv7_br_read(int); static uint32_t ddr_armv7_sz_read(int); static void ddr_br_write(int, uint32_t); static void ddr_sz_write(int, uint32_t); static void ddr_armv5_br_write(int, uint32_t); static void ddr_armv5_sz_write(int, uint32_t); static void ddr_armv7_br_write(int, uint32_t); static void ddr_armv7_sz_write(int, uint32_t); static int fdt_get_ranges(const char *, void *, int, int *, int *); int gic_decode_fdt(phandle_t iparent, pcell_t *intr, int *interrupt, int *trig, int *pol); static int win_cpu_from_dt(void); static int fdt_win_setup(void); static uint32_t dev_mask = 0; static int cpu_wins_no = 0; static int eth_port = 0; static int usb_port = 0; static boolean_t platform_io_coherent = false; static struct decode_win cpu_win_tbl[MAX_CPU_WIN]; const struct decode_win *cpu_wins = cpu_win_tbl; typedef void (*decode_win_setup_t)(u_long); typedef void (*dump_win_t)(u_long); typedef int (*valid_t)(void); /* * The power status of device feature is only supported on * Kirkwood and Discovery SoCs. */ #if defined(SOC_MV_KIRKWOOD) || defined(SOC_MV_DISCOVERY) #define SOC_MV_POWER_STAT_SUPPORTED 1 #else #define SOC_MV_POWER_STAT_SUPPORTED 0 #endif struct soc_node_spec { const char *compat; decode_win_setup_t decode_handler; dump_win_t dump_handler; valid_t valid_handler; }; static struct soc_node_spec soc_nodes[] = { { "mrvl,ge", &decode_win_eth_setup, &decode_win_eth_dump, &decode_win_eth_valid}, { "marvell,armada-370-neta", &decode_win_neta_setup, &decode_win_neta_dump, NULL }, { "mrvl,usb-ehci", &decode_win_usb_setup, &decode_win_usb_dump, &decode_win_usb_valid}, { "marvell,orion-ehci", &decode_win_usb_setup, &decode_win_usb_dump, &decode_win_usb_valid }, { "marvell,armada-380-xhci", &decode_win_usb3_setup, &decode_win_usb3_dump, &decode_win_usb3_valid }, { "marvell,armada-380-ahci", &decode_win_ahci_setup, &decode_win_ahci_dump, NULL }, { "marvell,armada-380-sdhci", &decode_win_sdhci_setup, &decode_win_sdhci_dump, &decode_win_sdhci_valid}, { "mrvl,sata", &decode_win_sata_setup, NULL, &decode_win_sata_valid}, { "mrvl,xor", &decode_win_xor_setup, &decode_win_xor_dump, &decode_win_xor_valid}, { "mrvl,idma", &decode_win_idma_setup, &decode_win_idma_dump, &decode_win_idma_valid}, { "mrvl,cesa", &decode_win_cesa_setup, &decode_win_cesa_dump, &decode_win_cesa_valid}, { "mrvl,pcie", &decode_win_pcie_setup, &decode_win_pcie_dump, &decode_win_pcie_valid}, { NULL, NULL, NULL, NULL }, }; typedef uint32_t(*read_cpu_ctrl_t)(uint32_t); typedef void(*write_cpu_ctrl_t)(uint32_t, uint32_t); typedef uint32_t (*win_read_t)(int); typedef void (*win_write_t)(int, uint32_t); typedef int (*win_cesa_attr_t)(int); typedef uint32_t (*get_t)(void); struct decode_win_spec { read_cpu_ctrl_t read_cpu_ctrl; write_cpu_ctrl_t write_cpu_ctrl; win_read_t cr_read; win_read_t br_read; win_read_t remap_l_read; win_read_t remap_h_read; win_write_t cr_write; win_write_t br_write; win_write_t remap_l_write; win_write_t remap_h_write; uint32_t mv_win_cpu_max; win_cesa_attr_t win_cesa_attr; int win_cesa_target; win_read_t ddr_br_read; win_read_t ddr_sz_read; win_write_t ddr_br_write; win_write_t ddr_sz_write; #if __ARM_ARCH >= 6 get_t get_tclk; get_t get_cpu_freq; #endif }; struct decode_win_spec *soc_decode_win_spec; static struct decode_win_spec decode_win_specs[] = { { &read_cpu_ctrl_armv7, &write_cpu_ctrl_armv7, &win_cpu_armv7_cr_read, &win_cpu_armv7_br_read, &win_cpu_armv7_remap_l_read, &win_cpu_armv7_remap_h_read, &win_cpu_armv7_cr_write, &win_cpu_armv7_br_write, &win_cpu_armv7_remap_l_write, &win_cpu_armv7_remap_h_write, MV_WIN_CPU_MAX_ARMV7, &mv_win_cesa_attr_armada38x, MV_WIN_CESA_TARGET_ARMADA38X, &ddr_armv7_br_read, &ddr_armv7_sz_read, &ddr_armv7_br_write, &ddr_armv7_sz_write, #if __ARM_ARCH >= 6 &get_tclk_armada38x, &get_cpu_freq_armada38x, #endif }, { &read_cpu_ctrl_armv7, &write_cpu_ctrl_armv7, &win_cpu_armv7_cr_read, &win_cpu_armv7_br_read, &win_cpu_armv7_remap_l_read, &win_cpu_armv7_remap_h_read, &win_cpu_armv7_cr_write, &win_cpu_armv7_br_write, &win_cpu_armv7_remap_l_write, &win_cpu_armv7_remap_h_write, MV_WIN_CPU_MAX_ARMV7, &mv_win_cesa_attr_armadaxp, MV_WIN_CESA_TARGET_ARMADAXP, &ddr_armv7_br_read, &ddr_armv7_sz_read, &ddr_armv7_br_write, &ddr_armv7_sz_write, #if __ARM_ARCH >= 6 &get_tclk_armadaxp, &get_cpu_freq_armadaxp, #endif }, { &read_cpu_ctrl_armv5, &write_cpu_ctrl_armv5, &win_cpu_armv5_cr_read, &win_cpu_armv5_br_read, &win_cpu_armv5_remap_l_read, &win_cpu_armv5_remap_h_read, &win_cpu_armv5_cr_write, &win_cpu_armv5_br_write, &win_cpu_armv5_remap_l_write, &win_cpu_armv5_remap_h_write, MV_WIN_CPU_MAX, &mv_win_cesa_attr_armv5, MV_WIN_CESA_TARGET, &ddr_armv5_br_read, &ddr_armv5_sz_read, &ddr_armv5_br_write, &ddr_armv5_sz_write, #if __ARM_ARCH >= 6 NULL, NULL, #endif }, }; struct fdt_pm_mask_entry { char *compat; uint32_t mask; }; static struct fdt_pm_mask_entry fdt_pm_mask_table[] = { { "mrvl,ge", CPU_PM_CTRL_GE(0) }, { "mrvl,ge", CPU_PM_CTRL_GE(1) }, { "mrvl,usb-ehci", CPU_PM_CTRL_USB(0) }, { "mrvl,usb-ehci", CPU_PM_CTRL_USB(1) }, { "mrvl,usb-ehci", CPU_PM_CTRL_USB(2) }, { "mrvl,xor", CPU_PM_CTRL_XOR }, { "mrvl,sata", CPU_PM_CTRL_SATA }, { NULL, 0 } }; static __inline int pm_is_disabled(uint32_t mask) { #if SOC_MV_POWER_STAT_SUPPORTED return (soc_power_ctrl_get(mask) == mask ? 0 : 1); #else return (0); #endif } /* * Disable device using power management register. * 1 - Device Power On * 0 - Device Power Off * Mask can be set in loader. * EXAMPLE: * loader> set hw.pm-disable-mask=0x2 * * Common mask: * |-------------------------------| * | Device | Kirkwood | Discovery | * |-------------------------------| * | USB0 | 0x00008 | 0x020000 | * |-------------------------------| * | USB1 | - | 0x040000 | * |-------------------------------| * | USB2 | - | 0x080000 | * |-------------------------------| * | GE0 | 0x00001 | 0x000002 | * |-------------------------------| * | GE1 | - | 0x000004 | * |-------------------------------| * | IDMA | - | 0x100000 | * |-------------------------------| * | XOR | 0x10000 | 0x200000 | * |-------------------------------| * | CESA | 0x20000 | 0x400000 | * |-------------------------------| * | SATA | 0x04000 | 0x004000 | * --------------------------------| * This feature can be used only on Kirkwood and Discovery * machines. */ static int mv_win_cesa_attr(int eng_sel) { if (soc_decode_win_spec->win_cesa_attr != NULL) return (soc_decode_win_spec->win_cesa_attr(eng_sel)); return (-1); } static int mv_win_cesa_attr_armv5(int eng_sel) { return MV_WIN_CESA_ATTR(eng_sel); } static int mv_win_cesa_attr_armada38x(int eng_sel) { return MV_WIN_CESA_ATTR_ARMADA38X(eng_sel); } static int mv_win_cesa_attr_armadaxp(int eng_sel) { return MV_WIN_CESA_ATTR_ARMADAXP(eng_sel); } enum soc_family mv_check_soc_family() { uint32_t dev, rev; soc_id(&dev, &rev); switch (dev) { case MV_DEV_MV78230: case MV_DEV_MV78260: case MV_DEV_MV78460: soc_decode_win_spec = &decode_win_specs[MV_SOC_ARMADA_XP]; soc_family = MV_SOC_ARMADA_XP; return (MV_SOC_ARMADA_XP); case MV_DEV_88F6828: case MV_DEV_88F6820: case MV_DEV_88F6810: soc_decode_win_spec = &decode_win_specs[MV_SOC_ARMADA_38X]; soc_family = MV_SOC_ARMADA_38X; return (MV_SOC_ARMADA_38X); case MV_DEV_88F5181: case MV_DEV_88F5182: case MV_DEV_88F5281: case MV_DEV_88F6281: case MV_DEV_88RC8180: case MV_DEV_88RC9480: case MV_DEV_88RC9580: case MV_DEV_88F6781: case MV_DEV_88F6282: case MV_DEV_MV78100_Z0: case MV_DEV_MV78100: case MV_DEV_MV78160: soc_decode_win_spec = &decode_win_specs[MV_SOC_ARMV5]; soc_family = MV_SOC_ARMV5; return (MV_SOC_ARMV5); default: soc_family = MV_SOC_UNSUPPORTED; return (MV_SOC_UNSUPPORTED); } } static __inline void pm_disable_device(int mask) { #ifdef DIAGNOSTIC uint32_t reg; reg = soc_power_ctrl_get(CPU_PM_CTRL_ALL); printf("Power Management Register: 0%x\n", reg); reg &= ~mask; soc_power_ctrl_set(reg); printf("Device %x is disabled\n", mask); reg = soc_power_ctrl_get(CPU_PM_CTRL_ALL); printf("Power Management Register: 0%x\n", reg); #endif } int fdt_pm(phandle_t node) { uint32_t cpu_pm_ctrl; int i, ena, compat; ena = 1; cpu_pm_ctrl = read_cpu_ctrl(CPU_PM_CTRL); for (i = 0; fdt_pm_mask_table[i].compat != NULL; i++) { if (dev_mask & (1 << i)) continue; compat = ofw_bus_node_is_compatible(node, fdt_pm_mask_table[i].compat); #if defined(SOC_MV_KIRKWOOD) if (compat && (cpu_pm_ctrl & fdt_pm_mask_table[i].mask)) { dev_mask |= (1 << i); ena = 0; break; } else if (compat) { dev_mask |= (1 << i); break; } #else if (compat && (~cpu_pm_ctrl & fdt_pm_mask_table[i].mask)) { dev_mask |= (1 << i); ena = 0; break; } else if (compat) { dev_mask |= (1 << i); break; } #endif } return (ena); } uint32_t read_cpu_ctrl(uint32_t reg) { if (soc_decode_win_spec->read_cpu_ctrl != NULL) return (soc_decode_win_spec->read_cpu_ctrl(reg)); return (-1); } uint32_t read_cpu_ctrl_armv5(uint32_t reg) { return (bus_space_read_4(fdtbus_bs_tag, MV_CPU_CONTROL_BASE, reg)); } uint32_t read_cpu_ctrl_armv7(uint32_t reg) { return (bus_space_read_4(fdtbus_bs_tag, MV_CPU_CONTROL_BASE_ARMV7, reg)); } void write_cpu_ctrl(uint32_t reg, uint32_t val) { if (soc_decode_win_spec->write_cpu_ctrl != NULL) soc_decode_win_spec->write_cpu_ctrl(reg, val); } void write_cpu_ctrl_armv5(uint32_t reg, uint32_t val) { bus_space_write_4(fdtbus_bs_tag, MV_CPU_CONTROL_BASE, reg, val); } void write_cpu_ctrl_armv7(uint32_t reg, uint32_t val) { bus_space_write_4(fdtbus_bs_tag, MV_CPU_CONTROL_BASE_ARMV7, reg, val); } uint32_t read_cpu_mp_clocks(uint32_t reg) { return (bus_space_read_4(fdtbus_bs_tag, MV_MP_CLOCKS_BASE, reg)); } void write_cpu_mp_clocks(uint32_t reg, uint32_t val) { bus_space_write_4(fdtbus_bs_tag, MV_MP_CLOCKS_BASE, reg, val); } uint32_t read_cpu_misc(uint32_t reg) { return (bus_space_read_4(fdtbus_bs_tag, MV_MISC_BASE, reg)); } void write_cpu_misc(uint32_t reg, uint32_t val) { bus_space_write_4(fdtbus_bs_tag, MV_MISC_BASE, reg, val); } -void -cpu_reset(void) -{ - -#if defined(SOC_MV_ARMADAXP) || defined (SOC_MV_ARMADA38X) - write_cpu_misc(RSTOUTn_MASK, SOFT_RST_OUT_EN); - write_cpu_misc(SYSTEM_SOFT_RESET, SYS_SOFT_RST); -#else - write_cpu_ctrl(RSTOUTn_MASK, SOFT_RST_OUT_EN); - write_cpu_ctrl(SYSTEM_SOFT_RESET, SYS_SOFT_RST); -#endif - while (1); -} - uint32_t cpu_extra_feat(void) { uint32_t dev, rev; uint32_t ef = 0; soc_id(&dev, &rev); switch (dev) { case MV_DEV_88F6281: case MV_DEV_88F6282: case MV_DEV_88RC8180: case MV_DEV_MV78100_Z0: case MV_DEV_MV78100: __asm __volatile("mrc p15, 1, %0, c15, c1, 0" : "=r" (ef)); break; case MV_DEV_88F5182: case MV_DEV_88F5281: __asm __volatile("mrc p15, 0, %0, c14, c0, 0" : "=r" (ef)); break; default: if (bootverbose) printf("This ARM Core does not support any extra features\n"); } return (ef); } /* * Get the power status of device. This feature is only supported on * Kirkwood and Discovery SoCs. */ uint32_t soc_power_ctrl_get(uint32_t mask) { #if SOC_MV_POWER_STAT_SUPPORTED if (mask != CPU_PM_CTRL_NONE) mask &= read_cpu_ctrl(CPU_PM_CTRL); return (mask); #else return (mask); #endif } /* * Set the power status of device. This feature is only supported on * Kirkwood and Discovery SoCs. */ void soc_power_ctrl_set(uint32_t mask) { #if !defined(SOC_MV_ORION) if (mask != CPU_PM_CTRL_NONE) write_cpu_ctrl(CPU_PM_CTRL, mask); #endif } void soc_id(uint32_t *dev, uint32_t *rev) { uint64_t mv_pcie_base = MV_PCIE_BASE; phandle_t node; /* * Notice: system identifiers are available in the registers range of * PCIE controller, so using this function is only allowed (and * possible) after the internal registers range has been mapped in via * devmap_bootstrap(). */ *dev = 0; *rev = 0; if ((node = OF_finddevice("/")) == -1) return; if (ofw_bus_node_is_compatible(node, "marvell,armada380")) mv_pcie_base = MV_PCIE_BASE_ARMADA38X; *dev = bus_space_read_4(fdtbus_bs_tag, mv_pcie_base, 0) >> 16; *rev = bus_space_read_4(fdtbus_bs_tag, mv_pcie_base, 8) & 0xff; } static void soc_identify(void) { uint32_t d, r, size, mode, freq; const char *dev; const char *rev; soc_id(&d, &r); printf("SOC: "); if (bootverbose) printf("(0x%4x:0x%02x) ", d, r); rev = ""; switch (d) { case MV_DEV_88F5181: dev = "Marvell 88F5181"; if (r == 3) rev = "B1"; break; case MV_DEV_88F5182: dev = "Marvell 88F5182"; if (r == 2) rev = "A2"; break; case MV_DEV_88F5281: dev = "Marvell 88F5281"; if (r == 4) rev = "D0"; else if (r == 5) rev = "D1"; else if (r == 6) rev = "D2"; break; case MV_DEV_88F6281: dev = "Marvell 88F6281"; if (r == 0) rev = "Z0"; else if (r == 2) rev = "A0"; else if (r == 3) rev = "A1"; break; case MV_DEV_88RC8180: dev = "Marvell 88RC8180"; break; case MV_DEV_88RC9480: dev = "Marvell 88RC9480"; break; case MV_DEV_88RC9580: dev = "Marvell 88RC9580"; break; case MV_DEV_88F6781: dev = "Marvell 88F6781"; if (r == 2) rev = "Y0"; break; case MV_DEV_88F6282: dev = "Marvell 88F6282"; if (r == 0) rev = "A0"; else if (r == 1) rev = "A1"; break; case MV_DEV_88F6828: dev = "Marvell 88F6828"; break; case MV_DEV_88F6820: dev = "Marvell 88F6820"; break; case MV_DEV_88F6810: dev = "Marvell 88F6810"; break; case MV_DEV_MV78100_Z0: dev = "Marvell MV78100 Z0"; break; case MV_DEV_MV78100: dev = "Marvell MV78100"; break; case MV_DEV_MV78160: dev = "Marvell MV78160"; break; case MV_DEV_MV78260: dev = "Marvell MV78260"; break; case MV_DEV_MV78460: dev = "Marvell MV78460"; break; default: dev = "UNKNOWN"; break; } printf("%s", dev); if (*rev != '\0') printf(" rev %s", rev); printf(", TClock %dMHz", get_tclk() / 1000 / 1000); freq = get_cpu_freq(); if (freq != 0) printf(", Frequency %dMHz", freq / 1000 / 1000); printf("\n"); mode = read_cpu_ctrl(CPU_CONFIG); printf(" Instruction cache prefetch %s, data cache prefetch %s\n", (mode & CPU_CONFIG_IC_PREF) ? "enabled" : "disabled", (mode & CPU_CONFIG_DC_PREF) ? "enabled" : "disabled"); switch (d) { case MV_DEV_88F6281: case MV_DEV_88F6282: mode = read_cpu_ctrl(CPU_L2_CONFIG) & CPU_L2_CONFIG_MODE; printf(" 256KB 4-way set-associative %s unified L2 cache\n", mode ? "write-through" : "write-back"); break; case MV_DEV_MV78100: mode = read_cpu_ctrl(CPU_CONTROL); size = mode & CPU_CONTROL_L2_SIZE; mode = mode & CPU_CONTROL_L2_MODE; printf(" %s set-associative %s unified L2 cache\n", size ? "256KB 4-way" : "512KB 8-way", mode ? "write-through" : "write-back"); break; default: break; } } static void platform_identify(void *dummy) { soc_identify(); /* * XXX Board identification e.g. read out from FPGA or similar should * go here */ } SYSINIT(platform_identify, SI_SUB_CPU, SI_ORDER_SECOND, platform_identify, NULL); #ifdef KDB static void mv_enter_debugger(void *dummy) { if (boothowto & RB_KDB) kdb_enter(KDB_WHY_BOOTFLAGS, "Boot flags requested debugger"); } SYSINIT(mv_enter_debugger, SI_SUB_CPU, SI_ORDER_ANY, mv_enter_debugger, NULL); #endif int soc_decode_win(void) { uint32_t dev, rev; int mask, err; mask = 0; TUNABLE_INT_FETCH("hw.pm-disable-mask", &mask); if (mask != 0) pm_disable_device(mask); /* Retrieve data about physical addresses from device tree. */ if ((err = win_cpu_from_dt()) != 0) return (err); /* Retrieve our ID: some windows facilities vary between SoC models */ soc_id(&dev, &rev); if (soc_family == MV_SOC_ARMADA_XP) if ((err = decode_win_sdram_fixup()) != 0) return(err); decode_win_cpu_setup(); if (MV_DUMP_WIN) soc_dump_decode_win(); eth_port = 0; usb_port = 0; if ((err = fdt_win_setup()) != 0) return (err); return (0); } /************************************************************************** * Decode windows registers accessors **************************************************************************/ WIN_REG_IDX_RD(win_cpu_armv5, cr, MV_WIN_CPU_CTRL_ARMV5, MV_MBUS_BRIDGE_BASE) WIN_REG_IDX_RD(win_cpu_armv5, br, MV_WIN_CPU_BASE_ARMV5, MV_MBUS_BRIDGE_BASE) WIN_REG_IDX_RD(win_cpu_armv5, remap_l, MV_WIN_CPU_REMAP_LO_ARMV5, MV_MBUS_BRIDGE_BASE) WIN_REG_IDX_RD(win_cpu_armv5, remap_h, MV_WIN_CPU_REMAP_HI_ARMV5, MV_MBUS_BRIDGE_BASE) WIN_REG_IDX_WR(win_cpu_armv5, cr, MV_WIN_CPU_CTRL_ARMV5, MV_MBUS_BRIDGE_BASE) WIN_REG_IDX_WR(win_cpu_armv5, br, MV_WIN_CPU_BASE_ARMV5, MV_MBUS_BRIDGE_BASE) WIN_REG_IDX_WR(win_cpu_armv5, remap_l, MV_WIN_CPU_REMAP_LO_ARMV5, MV_MBUS_BRIDGE_BASE) WIN_REG_IDX_WR(win_cpu_armv5, remap_h, MV_WIN_CPU_REMAP_HI_ARMV5, MV_MBUS_BRIDGE_BASE) WIN_REG_IDX_RD(win_cpu_armv7, cr, MV_WIN_CPU_CTRL_ARMV7, MV_MBUS_BRIDGE_BASE) WIN_REG_IDX_RD(win_cpu_armv7, br, MV_WIN_CPU_BASE_ARMV7, MV_MBUS_BRIDGE_BASE) WIN_REG_IDX_RD(win_cpu_armv7, remap_l, MV_WIN_CPU_REMAP_LO_ARMV7, MV_MBUS_BRIDGE_BASE) WIN_REG_IDX_RD(win_cpu_armv7, remap_h, MV_WIN_CPU_REMAP_HI_ARMV7, MV_MBUS_BRIDGE_BASE) WIN_REG_IDX_WR(win_cpu_armv7, cr, MV_WIN_CPU_CTRL_ARMV7, MV_MBUS_BRIDGE_BASE) WIN_REG_IDX_WR(win_cpu_armv7, br, MV_WIN_CPU_BASE_ARMV7, MV_MBUS_BRIDGE_BASE) WIN_REG_IDX_WR(win_cpu_armv7, remap_l, MV_WIN_CPU_REMAP_LO_ARMV7, MV_MBUS_BRIDGE_BASE) WIN_REG_IDX_WR(win_cpu_armv7, remap_h, MV_WIN_CPU_REMAP_HI_ARMV7, MV_MBUS_BRIDGE_BASE) static uint32_t win_cpu_cr_read(int i) { if (soc_decode_win_spec->cr_read != NULL) return (soc_decode_win_spec->cr_read(i)); return (-1); } static uint32_t win_cpu_br_read(int i) { if (soc_decode_win_spec->br_read != NULL) return (soc_decode_win_spec->br_read(i)); return (-1); } static uint32_t win_cpu_remap_l_read(int i) { if (soc_decode_win_spec->remap_l_read != NULL) return (soc_decode_win_spec->remap_l_read(i)); return (-1); } static uint32_t win_cpu_remap_h_read(int i) { if (soc_decode_win_spec->remap_h_read != NULL) return soc_decode_win_spec->remap_h_read(i); return (-1); } static void win_cpu_cr_write(int i, uint32_t val) { if (soc_decode_win_spec->cr_write != NULL) soc_decode_win_spec->cr_write(i, val); } static void win_cpu_br_write(int i, uint32_t val) { if (soc_decode_win_spec->br_write != NULL) soc_decode_win_spec->br_write(i, val); } static void win_cpu_remap_l_write(int i, uint32_t val) { if (soc_decode_win_spec->remap_l_write != NULL) soc_decode_win_spec->remap_l_write(i, val); } static void win_cpu_remap_h_write(int i, uint32_t val) { if (soc_decode_win_spec->remap_h_write != NULL) soc_decode_win_spec->remap_h_write(i, val); } WIN_REG_BASE_IDX_RD(win_cesa, cr, MV_WIN_CESA_CTRL) WIN_REG_BASE_IDX_RD(win_cesa, br, MV_WIN_CESA_BASE) WIN_REG_BASE_IDX_WR(win_cesa, cr, MV_WIN_CESA_CTRL) WIN_REG_BASE_IDX_WR(win_cesa, br, MV_WIN_CESA_BASE) WIN_REG_BASE_IDX_RD(win_usb, cr, MV_WIN_USB_CTRL) WIN_REG_BASE_IDX_RD(win_usb, br, MV_WIN_USB_BASE) WIN_REG_BASE_IDX_WR(win_usb, cr, MV_WIN_USB_CTRL) WIN_REG_BASE_IDX_WR(win_usb, br, MV_WIN_USB_BASE) WIN_REG_BASE_IDX_RD(win_usb3, cr, MV_WIN_USB3_CTRL) WIN_REG_BASE_IDX_RD(win_usb3, br, MV_WIN_USB3_BASE) WIN_REG_BASE_IDX_WR(win_usb3, cr, MV_WIN_USB3_CTRL) WIN_REG_BASE_IDX_WR(win_usb3, br, MV_WIN_USB3_BASE) WIN_REG_BASE_IDX_RD(win_eth, br, MV_WIN_ETH_BASE) WIN_REG_BASE_IDX_RD(win_eth, sz, MV_WIN_ETH_SIZE) WIN_REG_BASE_IDX_RD(win_eth, har, MV_WIN_ETH_REMAP) WIN_REG_BASE_IDX_WR(win_eth, br, MV_WIN_ETH_BASE) WIN_REG_BASE_IDX_WR(win_eth, sz, MV_WIN_ETH_SIZE) WIN_REG_BASE_IDX_WR(win_eth, har, MV_WIN_ETH_REMAP) WIN_REG_BASE_IDX_RD2(win_xor, br, MV_WIN_XOR_BASE) WIN_REG_BASE_IDX_RD2(win_xor, sz, MV_WIN_XOR_SIZE) WIN_REG_BASE_IDX_RD2(win_xor, har, MV_WIN_XOR_REMAP) WIN_REG_BASE_IDX_RD2(win_xor, ctrl, MV_WIN_XOR_CTRL) WIN_REG_BASE_IDX_WR2(win_xor, br, MV_WIN_XOR_BASE) WIN_REG_BASE_IDX_WR2(win_xor, sz, MV_WIN_XOR_SIZE) WIN_REG_BASE_IDX_WR2(win_xor, har, MV_WIN_XOR_REMAP) WIN_REG_BASE_IDX_WR2(win_xor, ctrl, MV_WIN_XOR_CTRL) WIN_REG_BASE_RD(win_eth, bare, 0x290) WIN_REG_BASE_RD(win_eth, epap, 0x294) WIN_REG_BASE_WR(win_eth, bare, 0x290) WIN_REG_BASE_WR(win_eth, epap, 0x294) WIN_REG_BASE_IDX_RD(win_pcie, cr, MV_WIN_PCIE_CTRL); WIN_REG_BASE_IDX_RD(win_pcie, br, MV_WIN_PCIE_BASE); WIN_REG_BASE_IDX_RD(win_pcie, remap, MV_WIN_PCIE_REMAP); WIN_REG_BASE_IDX_WR(win_pcie, cr, MV_WIN_PCIE_CTRL); WIN_REG_BASE_IDX_WR(win_pcie, br, MV_WIN_PCIE_BASE); WIN_REG_BASE_IDX_WR(win_pcie, remap, MV_WIN_PCIE_REMAP); WIN_REG_BASE_IDX_RD(pcie_bar, br, MV_PCIE_BAR_BASE); WIN_REG_BASE_IDX_RD(pcie_bar, brh, MV_PCIE_BAR_BASE_H); WIN_REG_BASE_IDX_RD(pcie_bar, cr, MV_PCIE_BAR_CTRL); WIN_REG_BASE_IDX_WR(pcie_bar, br, MV_PCIE_BAR_BASE); WIN_REG_BASE_IDX_WR(pcie_bar, brh, MV_PCIE_BAR_BASE_H); WIN_REG_BASE_IDX_WR(pcie_bar, cr, MV_PCIE_BAR_CTRL); WIN_REG_BASE_IDX_RD(win_idma, br, MV_WIN_IDMA_BASE) WIN_REG_BASE_IDX_RD(win_idma, sz, MV_WIN_IDMA_SIZE) WIN_REG_BASE_IDX_RD(win_idma, har, MV_WIN_IDMA_REMAP) WIN_REG_BASE_IDX_RD(win_idma, cap, MV_WIN_IDMA_CAP) WIN_REG_BASE_IDX_WR(win_idma, br, MV_WIN_IDMA_BASE) WIN_REG_BASE_IDX_WR(win_idma, sz, MV_WIN_IDMA_SIZE) WIN_REG_BASE_IDX_WR(win_idma, har, MV_WIN_IDMA_REMAP) WIN_REG_BASE_IDX_WR(win_idma, cap, MV_WIN_IDMA_CAP) WIN_REG_BASE_RD(win_idma, bare, 0xa80) WIN_REG_BASE_WR(win_idma, bare, 0xa80) WIN_REG_BASE_IDX_RD(win_sata, cr, MV_WIN_SATA_CTRL); WIN_REG_BASE_IDX_RD(win_sata, br, MV_WIN_SATA_BASE); WIN_REG_BASE_IDX_WR(win_sata, cr, MV_WIN_SATA_CTRL); WIN_REG_BASE_IDX_WR(win_sata, br, MV_WIN_SATA_BASE); WIN_REG_BASE_IDX_RD(win_sata_armada38x, sz, MV_WIN_SATA_SIZE_ARMADA38X); WIN_REG_BASE_IDX_WR(win_sata_armada38x, sz, MV_WIN_SATA_SIZE_ARMADA38X); WIN_REG_BASE_IDX_RD(win_sata_armada38x, cr, MV_WIN_SATA_CTRL_ARMADA38X); WIN_REG_BASE_IDX_RD(win_sata_armada38x, br, MV_WIN_SATA_BASE_ARMADA38X); WIN_REG_BASE_IDX_WR(win_sata_armada38x, cr, MV_WIN_SATA_CTRL_ARMADA38X); WIN_REG_BASE_IDX_WR(win_sata_armada38x, br, MV_WIN_SATA_BASE_ARMADA38X); WIN_REG_BASE_IDX_RD(win_sdhci, cr, MV_WIN_SDHCI_CTRL); WIN_REG_BASE_IDX_RD(win_sdhci, br, MV_WIN_SDHCI_BASE); WIN_REG_BASE_IDX_WR(win_sdhci, cr, MV_WIN_SDHCI_CTRL); WIN_REG_BASE_IDX_WR(win_sdhci, br, MV_WIN_SDHCI_BASE); #ifndef SOC_MV_DOVE WIN_REG_IDX_RD(ddr_armv5, br, MV_WIN_DDR_BASE, MV_DDR_CADR_BASE) WIN_REG_IDX_RD(ddr_armv5, sz, MV_WIN_DDR_SIZE, MV_DDR_CADR_BASE) WIN_REG_IDX_WR(ddr_armv5, br, MV_WIN_DDR_BASE, MV_DDR_CADR_BASE) WIN_REG_IDX_WR(ddr_armv5, sz, MV_WIN_DDR_SIZE, MV_DDR_CADR_BASE) WIN_REG_IDX_RD(ddr_armv7, br, MV_WIN_DDR_BASE, MV_DDR_CADR_BASE_ARMV7) WIN_REG_IDX_RD(ddr_armv7, sz, MV_WIN_DDR_SIZE, MV_DDR_CADR_BASE_ARMV7) WIN_REG_IDX_WR(ddr_armv7, br, MV_WIN_DDR_BASE, MV_DDR_CADR_BASE_ARMV7) WIN_REG_IDX_WR(ddr_armv7, sz, MV_WIN_DDR_SIZE, MV_DDR_CADR_BASE_ARMV7) static inline uint32_t ddr_br_read(int i) { if (soc_decode_win_spec->ddr_br_read != NULL) return (soc_decode_win_spec->ddr_br_read(i)); return (-1); } static inline uint32_t ddr_sz_read(int i) { if (soc_decode_win_spec->ddr_sz_read != NULL) return (soc_decode_win_spec->ddr_sz_read(i)); return (-1); } static inline void ddr_br_write(int i, uint32_t val) { if (soc_decode_win_spec->ddr_br_write != NULL) soc_decode_win_spec->ddr_br_write(i, val); } static inline void ddr_sz_write(int i, uint32_t val) { if (soc_decode_win_spec->ddr_sz_write != NULL) soc_decode_win_spec->ddr_sz_write(i, val); } #else /* * On 88F6781 (Dove) SoC DDR Controller is accessed through * single MBUS <-> AXI bridge. In this case we provide emulated * ddr_br_read() and ddr_sz_read() functions to keep compatibility * with common decoding windows setup code. */ static inline uint32_t ddr_br_read(int i) { uint32_t mmap; /* Read Memory Address Map Register for CS i */ mmap = bus_space_read_4(fdtbus_bs_tag, MV_DDR_CADR_BASE + (i * 0x10), 0); /* Return CS i base address */ return (mmap & 0xFF000000); } static inline uint32_t ddr_sz_read(int i) { uint32_t mmap, size; /* Read Memory Address Map Register for CS i */ mmap = bus_space_read_4(fdtbus_bs_tag, MV_DDR_CADR_BASE + (i * 0x10), 0); /* Extract size of CS space in 64kB units */ size = (1 << ((mmap >> 16) & 0x0F)); /* Return CS size and enable/disable status */ return (((size - 1) << 16) | (mmap & 0x01)); } #endif /************************************************************************** * Decode windows helper routines **************************************************************************/ void soc_dump_decode_win(void) { int i; for (i = 0; i < soc_decode_win_spec->mv_win_cpu_max; i++) { printf("CPU window#%d: c 0x%08x, b 0x%08x", i, win_cpu_cr_read(i), win_cpu_br_read(i)); if (win_cpu_can_remap(i)) printf(", rl 0x%08x, rh 0x%08x", win_cpu_remap_l_read(i), win_cpu_remap_h_read(i)); printf("\n"); } printf("Internal regs base: 0x%08x\n", bus_space_read_4(fdtbus_bs_tag, MV_INTREGS_BASE, 0)); for (i = 0; i < MV_WIN_DDR_MAX; i++) printf("DDR CS#%d: b 0x%08x, s 0x%08x\n", i, ddr_br_read(i), ddr_sz_read(i)); } /************************************************************************** * CPU windows routines **************************************************************************/ int win_cpu_can_remap(int i) { uint32_t dev, rev; soc_id(&dev, &rev); /* Depending on the SoC certain windows have remap capability */ if ((dev == MV_DEV_88F5182 && i < 2) || (dev == MV_DEV_88F5281 && i < 4) || (dev == MV_DEV_88F6281 && i < 4) || (dev == MV_DEV_88F6282 && i < 4) || (dev == MV_DEV_88F6828 && i < 20) || (dev == MV_DEV_88F6820 && i < 20) || (dev == MV_DEV_88F6810 && i < 20) || (dev == MV_DEV_88RC8180 && i < 2) || (dev == MV_DEV_88F6781 && i < 4) || (dev == MV_DEV_MV78100_Z0 && i < 8) || ((dev & MV_DEV_FAMILY_MASK) == MV_DEV_DISCOVERY && i < 8)) return (1); return (0); } /* XXX This should check for overlapping remap fields too.. */ int decode_win_overlap(int win, int win_no, const struct decode_win *wintab) { const struct decode_win *tab; int i; tab = wintab; for (i = 0; i < win_no; i++, tab++) { if (i == win) /* Skip self */ continue; if ((tab->base + tab->size - 1) < (wintab + win)->base) continue; else if (((wintab + win)->base + (wintab + win)->size - 1) < tab->base) continue; else return (i); } return (-1); } static int decode_win_cpu_valid(void) { int i, j, rv; uint32_t b, e, s; if (cpu_wins_no > soc_decode_win_spec->mv_win_cpu_max) { printf("CPU windows: too many entries: %d\n", cpu_wins_no); return (0); } rv = 1; for (i = 0; i < cpu_wins_no; i++) { if (cpu_wins[i].target == 0) { printf("CPU window#%d: DDR target window is not " "supposed to be reprogrammed!\n", i); rv = 0; } if (cpu_wins[i].remap != ~0 && win_cpu_can_remap(i) != 1) { printf("CPU window#%d: not capable of remapping, but " "val 0x%08x defined\n", i, cpu_wins[i].remap); rv = 0; } s = cpu_wins[i].size; b = cpu_wins[i].base; e = b + s - 1; if (s > (0xFFFFFFFF - b + 1)) { /* * XXX this boundary check should account for 64bit * and remapping.. */ printf("CPU window#%d: no space for size 0x%08x at " "0x%08x\n", i, s, b); rv = 0; continue; } if (b != rounddown2(b, s)) { printf("CPU window#%d: address 0x%08x is not aligned " "to 0x%08x\n", i, b, s); rv = 0; continue; } j = decode_win_overlap(i, cpu_wins_no, &cpu_wins[0]); if (j >= 0) { printf("CPU window#%d: (0x%08x - 0x%08x) overlaps " "with #%d (0x%08x - 0x%08x)\n", i, b, e, j, cpu_wins[j].base, cpu_wins[j].base + cpu_wins[j].size - 1); rv = 0; } } return (rv); } int decode_win_cpu_set(int target, int attr, vm_paddr_t base, uint32_t size, vm_paddr_t remap) { uint32_t br, cr; int win, i; if (remap == ~0) { win = soc_decode_win_spec->mv_win_cpu_max - 1; i = -1; } else { win = 0; i = 1; } while ((win >= 0) && (win < soc_decode_win_spec->mv_win_cpu_max)) { cr = win_cpu_cr_read(win); if ((cr & MV_WIN_CPU_ENABLE_BIT) == 0) break; if ((cr & ((0xff << MV_WIN_CPU_ATTR_SHIFT) | (0x1f << MV_WIN_CPU_TARGET_SHIFT))) == ((attr << MV_WIN_CPU_ATTR_SHIFT) | (target << MV_WIN_CPU_TARGET_SHIFT))) break; win += i; } if ((win < 0) || (win >= soc_decode_win_spec->mv_win_cpu_max) || ((remap != ~0) && (win_cpu_can_remap(win) == 0))) return (-1); br = base & 0xffff0000; win_cpu_br_write(win, br); if (win_cpu_can_remap(win)) { if (remap != ~0) { win_cpu_remap_l_write(win, remap & 0xffff0000); win_cpu_remap_h_write(win, 0); } else { /* * Remap function is not used for a given window * (capable of remapping) - set remap field with the * same value as base. */ win_cpu_remap_l_write(win, base & 0xffff0000); win_cpu_remap_h_write(win, 0); } } cr = ((size - 1) & 0xffff0000) | (attr << MV_WIN_CPU_ATTR_SHIFT) | (target << MV_WIN_CPU_TARGET_SHIFT) | MV_WIN_CPU_ENABLE_BIT; win_cpu_cr_write(win, cr); return (0); } static void decode_win_cpu_setup(void) { int i; /* Disable all CPU windows */ for (i = 0; i < soc_decode_win_spec->mv_win_cpu_max; i++) { win_cpu_cr_write(i, 0); win_cpu_br_write(i, 0); if (win_cpu_can_remap(i)) { win_cpu_remap_l_write(i, 0); win_cpu_remap_h_write(i, 0); } } for (i = 0; i < cpu_wins_no; i++) if (cpu_wins[i].target > 0) decode_win_cpu_set(cpu_wins[i].target, cpu_wins[i].attr, cpu_wins[i].base, cpu_wins[i].size, cpu_wins[i].remap); } static int decode_win_sdram_fixup(void) { struct mem_region mr[FDT_MEM_REGIONS]; uint8_t window_valid[MV_WIN_DDR_MAX]; int mr_cnt, err, i, j; uint32_t valid_win_num = 0; /* Grab physical memory regions information from device tree. */ err = fdt_get_mem_regions(mr, &mr_cnt, NULL); if (err != 0) return (err); for (i = 0; i < MV_WIN_DDR_MAX; i++) window_valid[i] = 0; /* Try to match entries from device tree with settings from u-boot */ for (i = 0; i < mr_cnt; i++) { for (j = 0; j < MV_WIN_DDR_MAX; j++) { if (ddr_is_active(j) && (ddr_base(j) == mr[i].mr_start) && (ddr_size(j) == mr[i].mr_size)) { window_valid[j] = 1; valid_win_num++; } } } if (mr_cnt != valid_win_num) return (EINVAL); /* Destroy windows without corresponding device tree entry */ for (j = 0; j < MV_WIN_DDR_MAX; j++) { if (ddr_is_active(j) && (window_valid[j] != 1)) { printf("Disabling SDRAM decoding window: %d\n", j); ddr_disable(j); } } return (0); } /* * Check if we're able to cover all active DDR banks. */ static int decode_win_can_cover_ddr(int max) { int i, c; c = 0; for (i = 0; i < MV_WIN_DDR_MAX; i++) if (ddr_is_active(i)) c++; if (c > max) { printf("Unable to cover all active DDR banks: " "%d, available windows: %d\n", c, max); return (0); } return (1); } /************************************************************************** * DDR windows routines **************************************************************************/ int ddr_is_active(int i) { if (ddr_sz_read(i) & 0x1) return (1); return (0); } void ddr_disable(int i) { ddr_sz_write(i, 0); ddr_br_write(i, 0); } uint32_t ddr_base(int i) { return (ddr_br_read(i) & 0xff000000); } uint32_t ddr_size(int i) { return ((ddr_sz_read(i) | 0x00ffffff) + 1); } uint32_t ddr_attr(int i) { uint32_t dev, rev, attr; soc_id(&dev, &rev); if (dev == MV_DEV_88RC8180) return ((ddr_sz_read(i) & 0xf0) >> 4); if (dev == MV_DEV_88F6781) return (0); attr = (i == 0 ? 0xe : (i == 1 ? 0xd : (i == 2 ? 0xb : (i == 3 ? 0x7 : 0xff)))); if (platform_io_coherent) attr |= 0x10; return (attr); } uint32_t ddr_target(int i) { uint32_t dev, rev; soc_id(&dev, &rev); if (dev == MV_DEV_88RC8180) { i = (ddr_sz_read(i) & 0xf0) >> 4; return (i == 0xe ? 0xc : (i == 0xd ? 0xd : (i == 0xb ? 0xe : (i == 0x7 ? 0xf : 0xc)))); } /* * On SOCs other than 88RC8180 Mbus unit ID for * DDR SDRAM controller is always 0x0. */ return (0); } /************************************************************************** * CESA windows routines **************************************************************************/ static int decode_win_cesa_valid(void) { return (decode_win_can_cover_ddr(MV_WIN_CESA_MAX)); } static void decode_win_cesa_dump(u_long base) { int i; for (i = 0; i < MV_WIN_CESA_MAX; i++) printf("CESA window#%d: c 0x%08x, b 0x%08x\n", i, win_cesa_cr_read(base, i), win_cesa_br_read(base, i)); } /* * Set CESA decode windows. */ static void decode_win_cesa_setup(u_long base) { uint32_t br, cr; uint64_t size; int i, j; for (i = 0; i < MV_WIN_CESA_MAX; i++) { win_cesa_cr_write(base, i, 0); win_cesa_br_write(base, i, 0); } /* Only access to active DRAM banks is required */ for (i = 0; i < MV_WIN_DDR_MAX; i++) { if (ddr_is_active(i)) { br = ddr_base(i); size = ddr_size(i); /* * Armada 38x SoC's equipped with 4GB DRAM * suffer freeze during CESA operation, if * MBUS window opened at given DRAM CS reaches * end of the address space. Apply a workaround * by setting the window size to the closest possible * value, i.e. divide it by 2. */ if ((soc_family == MV_SOC_ARMADA_38X) && (size + ddr_base(i) == 0x100000000ULL)) size /= 2; cr = (((size - 1) & 0xffff0000) | (ddr_attr(i) << IO_WIN_ATTR_SHIFT) | (ddr_target(i) << IO_WIN_TGT_SHIFT) | IO_WIN_ENA_MASK); /* Set the first free CESA window */ for (j = 0; j < MV_WIN_CESA_MAX; j++) { if (win_cesa_cr_read(base, j) & 0x1) continue; win_cesa_br_write(base, j, br); win_cesa_cr_write(base, j, cr); break; } } } } /************************************************************************** * USB windows routines **************************************************************************/ static int decode_win_usb_valid(void) { return (decode_win_can_cover_ddr(MV_WIN_USB_MAX)); } static void decode_win_usb_dump(u_long base) { int i; if (pm_is_disabled(CPU_PM_CTRL_USB(usb_port - 1))) return; for (i = 0; i < MV_WIN_USB_MAX; i++) printf("USB window#%d: c 0x%08x, b 0x%08x\n", i, win_usb_cr_read(base, i), win_usb_br_read(base, i)); } /* * Set USB decode windows. */ static void decode_win_usb_setup(u_long base) { uint32_t br, cr; int i, j; if (pm_is_disabled(CPU_PM_CTRL_USB(usb_port))) return; usb_port++; for (i = 0; i < MV_WIN_USB_MAX; i++) { win_usb_cr_write(base, i, 0); win_usb_br_write(base, i, 0); } /* Only access to active DRAM banks is required */ for (i = 0; i < MV_WIN_DDR_MAX; i++) { if (ddr_is_active(i)) { br = ddr_base(i); /* * XXX for 6281 we should handle Mbus write * burst limit field in the ctrl reg */ cr = (((ddr_size(i) - 1) & 0xffff0000) | (ddr_attr(i) << 8) | (ddr_target(i) << 4) | 1); /* Set the first free USB window */ for (j = 0; j < MV_WIN_USB_MAX; j++) { if (win_usb_cr_read(base, j) & 0x1) continue; win_usb_br_write(base, j, br); win_usb_cr_write(base, j, cr); break; } } } } /************************************************************************** * USB3 windows routines **************************************************************************/ static int decode_win_usb3_valid(void) { return (decode_win_can_cover_ddr(MV_WIN_USB3_MAX)); } static void decode_win_usb3_dump(u_long base) { int i; for (i = 0; i < MV_WIN_USB3_MAX; i++) printf("USB3.0 window#%d: c 0x%08x, b 0x%08x\n", i, win_usb3_cr_read(base, i), win_usb3_br_read(base, i)); } /* * Set USB3 decode windows */ static void decode_win_usb3_setup(u_long base) { uint32_t br, cr; int i, j; for (i = 0; i < MV_WIN_USB3_MAX; i++) { win_usb3_cr_write(base, i, 0); win_usb3_br_write(base, i, 0); } /* Only access to active DRAM banks is required */ for (i = 0; i < MV_WIN_DDR_MAX; i++) { if (ddr_is_active(i)) { br = ddr_base(i); cr = (((ddr_size(i) - 1) & (IO_WIN_SIZE_MASK << IO_WIN_SIZE_SHIFT)) | (ddr_attr(i) << IO_WIN_ATTR_SHIFT) | (ddr_target(i) << IO_WIN_TGT_SHIFT) | IO_WIN_ENA_MASK); /* Set the first free USB3.0 window */ for (j = 0; j < MV_WIN_USB3_MAX; j++) { if (win_usb3_cr_read(base, j) & IO_WIN_ENA_MASK) continue; win_usb3_br_write(base, j, br); win_usb3_cr_write(base, j, cr); break; } } } } /************************************************************************** * ETH windows routines **************************************************************************/ static int win_eth_can_remap(int i) { /* ETH encode windows 0-3 have remap capability */ if (i < 4) return (1); return (0); } static int eth_bare_read(uint32_t base, int i) { uint32_t v; v = win_eth_bare_read(base); v &= (1 << i); return (v >> i); } static void eth_bare_write(uint32_t base, int i, int val) { uint32_t v; v = win_eth_bare_read(base); v &= ~(1 << i); v |= (val << i); win_eth_bare_write(base, v); } static void eth_epap_write(uint32_t base, int i, int val) { uint32_t v; v = win_eth_epap_read(base); v &= ~(0x3 << (i * 2)); v |= (val << (i * 2)); win_eth_epap_write(base, v); } static void decode_win_eth_dump(u_long base) { int i; if (pm_is_disabled(CPU_PM_CTRL_GE(eth_port - 1))) return; for (i = 0; i < MV_WIN_ETH_MAX; i++) { printf("ETH window#%d: b 0x%08x, s 0x%08x", i, win_eth_br_read(base, i), win_eth_sz_read(base, i)); if (win_eth_can_remap(i)) printf(", ha 0x%08x", win_eth_har_read(base, i)); printf("\n"); } printf("ETH windows: bare 0x%08x, epap 0x%08x\n", win_eth_bare_read(base), win_eth_epap_read(base)); } #define MV_WIN_ETH_DDR_TRGT(n) ddr_target(n) static void decode_win_eth_setup(u_long base) { uint32_t br, sz; int i, j; if (pm_is_disabled(CPU_PM_CTRL_GE(eth_port))) return; eth_port++; /* Disable, clear and revoke protection for all ETH windows */ for (i = 0; i < MV_WIN_ETH_MAX; i++) { eth_bare_write(base, i, 1); eth_epap_write(base, i, 0); win_eth_br_write(base, i, 0); win_eth_sz_write(base, i, 0); if (win_eth_can_remap(i)) win_eth_har_write(base, i, 0); } /* Only access to active DRAM banks is required */ for (i = 0; i < MV_WIN_DDR_MAX; i++) if (ddr_is_active(i)) { br = ddr_base(i) | (ddr_attr(i) << 8) | MV_WIN_ETH_DDR_TRGT(i); sz = ((ddr_size(i) - 1) & 0xffff0000); /* Set the first free ETH window */ for (j = 0; j < MV_WIN_ETH_MAX; j++) { if (eth_bare_read(base, j) == 0) continue; win_eth_br_write(base, j, br); win_eth_sz_write(base, j, sz); /* XXX remapping ETH windows not supported */ /* Set protection RW */ eth_epap_write(base, j, 0x3); /* Enable window */ eth_bare_write(base, j, 0); break; } } } static void decode_win_neta_dump(u_long base) { decode_win_eth_dump(base + MV_WIN_NETA_OFFSET); } static void decode_win_neta_setup(u_long base) { decode_win_eth_setup(base + MV_WIN_NETA_OFFSET); } static int decode_win_eth_valid(void) { return (decode_win_can_cover_ddr(MV_WIN_ETH_MAX)); } /************************************************************************** * PCIE windows routines **************************************************************************/ static void decode_win_pcie_dump(u_long base) { int i; printf("PCIE windows base 0x%08lx\n", base); for (i = 0; i < MV_WIN_PCIE_MAX; i++) printf("PCIE window#%d: cr 0x%08x br 0x%08x remap 0x%08x\n", i, win_pcie_cr_read(base, i), win_pcie_br_read(base, i), win_pcie_remap_read(base, i)); for (i = 0; i < MV_PCIE_BAR_MAX; i++) printf("PCIE bar#%d: cr 0x%08x br 0x%08x brh 0x%08x\n", i, pcie_bar_cr_read(base, i), pcie_bar_br_read(base, i), pcie_bar_brh_read(base, i)); } void decode_win_pcie_setup(u_long base) { uint32_t size = 0, ddrbase = ~0; uint32_t cr, br; int i, j; for (i = 0; i < MV_PCIE_BAR_MAX; i++) { pcie_bar_br_write(base, i, MV_PCIE_BAR_64BIT | MV_PCIE_BAR_PREFETCH_EN); if (i < 3) pcie_bar_brh_write(base, i, 0); if (i > 0) pcie_bar_cr_write(base, i, 0); } for (i = 0; i < MV_WIN_PCIE_MAX; i++) { win_pcie_cr_write(base, i, 0); win_pcie_br_write(base, i, 0); win_pcie_remap_write(base, i, 0); } /* On End-Point only set BAR size to 1MB regardless of DDR size */ if ((bus_space_read_4(fdtbus_bs_tag, base, MV_PCIE_CONTROL) & MV_PCIE_ROOT_CMPLX) == 0) { pcie_bar_cr_write(base, 1, 0xf0000 | 1); return; } for (i = 0; i < MV_WIN_DDR_MAX; i++) { if (ddr_is_active(i)) { /* Map DDR to BAR 1 */ cr = (ddr_size(i) - 1) & 0xffff0000; size += ddr_size(i) & 0xffff0000; cr |= (ddr_attr(i) << 8) | (ddr_target(i) << 4) | 1; br = ddr_base(i); if (br < ddrbase) ddrbase = br; /* Use the first available PCIE window */ for (j = 0; j < MV_WIN_PCIE_MAX; j++) { if (win_pcie_cr_read(base, j) != 0) continue; win_pcie_br_write(base, j, br); win_pcie_cr_write(base, j, cr); break; } } } /* * Upper 16 bits in BAR register is interpreted as BAR size * (in 64 kB units) plus 64kB, so subtract 0x10000 * form value passed to register to get correct value. */ size -= 0x10000; pcie_bar_cr_write(base, 1, size | 1); pcie_bar_br_write(base, 1, ddrbase | MV_PCIE_BAR_64BIT | MV_PCIE_BAR_PREFETCH_EN); pcie_bar_br_write(base, 0, fdt_immr_pa | MV_PCIE_BAR_64BIT | MV_PCIE_BAR_PREFETCH_EN); } static int decode_win_pcie_valid(void) { return (decode_win_can_cover_ddr(MV_WIN_PCIE_MAX)); } /************************************************************************** * IDMA windows routines **************************************************************************/ #if defined(SOC_MV_ORION) || defined(SOC_MV_DISCOVERY) static int idma_bare_read(u_long base, int i) { uint32_t v; v = win_idma_bare_read(base); v &= (1 << i); return (v >> i); } static void idma_bare_write(u_long base, int i, int val) { uint32_t v; v = win_idma_bare_read(base); v &= ~(1 << i); v |= (val << i); win_idma_bare_write(base, v); } /* * Sets channel protection 'val' for window 'w' on channel 'c' */ static void idma_cap_write(u_long base, int c, int w, int val) { uint32_t v; v = win_idma_cap_read(base, c); v &= ~(0x3 << (w * 2)); v |= (val << (w * 2)); win_idma_cap_write(base, c, v); } /* * Set protection 'val' on all channels for window 'w' */ static void idma_set_prot(u_long base, int w, int val) { int c; for (c = 0; c < MV_IDMA_CHAN_MAX; c++) idma_cap_write(base, c, w, val); } static int win_idma_can_remap(int i) { /* IDMA decode windows 0-3 have remap capability */ if (i < 4) return (1); return (0); } void decode_win_idma_setup(u_long base) { uint32_t br, sz; int i, j; if (pm_is_disabled(CPU_PM_CTRL_IDMA)) return; /* * Disable and clear all IDMA windows, revoke protection for all channels */ for (i = 0; i < MV_WIN_IDMA_MAX; i++) { idma_bare_write(base, i, 1); win_idma_br_write(base, i, 0); win_idma_sz_write(base, i, 0); if (win_idma_can_remap(i) == 1) win_idma_har_write(base, i, 0); } for (i = 0; i < MV_IDMA_CHAN_MAX; i++) win_idma_cap_write(base, i, 0); /* * Set up access to all active DRAM banks */ for (i = 0; i < MV_WIN_DDR_MAX; i++) if (ddr_is_active(i)) { br = ddr_base(i) | (ddr_attr(i) << 8) | ddr_target(i); sz = ((ddr_size(i) - 1) & 0xffff0000); /* Place DDR entries in non-remapped windows */ for (j = 0; j < MV_WIN_IDMA_MAX; j++) if (win_idma_can_remap(j) != 1 && idma_bare_read(base, j) == 1) { /* Configure window */ win_idma_br_write(base, j, br); win_idma_sz_write(base, j, sz); /* Set protection RW on all channels */ idma_set_prot(base, j, 0x3); /* Enable window */ idma_bare_write(base, j, 0); break; } } /* * Remaining targets -- from statically defined table */ for (i = 0; i < idma_wins_no; i++) if (idma_wins[i].target > 0) { br = (idma_wins[i].base & 0xffff0000) | (idma_wins[i].attr << 8) | idma_wins[i].target; sz = ((idma_wins[i].size - 1) & 0xffff0000); /* Set the first free IDMA window */ for (j = 0; j < MV_WIN_IDMA_MAX; j++) { if (idma_bare_read(base, j) == 0) continue; /* Configure window */ win_idma_br_write(base, j, br); win_idma_sz_write(base, j, sz); if (win_idma_can_remap(j) && idma_wins[j].remap >= 0) win_idma_har_write(base, j, idma_wins[j].remap); /* Set protection RW on all channels */ idma_set_prot(base, j, 0x3); /* Enable window */ idma_bare_write(base, j, 0); break; } } } int decode_win_idma_valid(void) { const struct decode_win *wintab; int c, i, j, rv; uint32_t b, e, s; if (idma_wins_no > MV_WIN_IDMA_MAX) { printf("IDMA windows: too many entries: %d\n", idma_wins_no); return (0); } for (i = 0, c = 0; i < MV_WIN_DDR_MAX; i++) if (ddr_is_active(i)) c++; if (idma_wins_no > (MV_WIN_IDMA_MAX - c)) { printf("IDMA windows: too many entries: %d, available: %d\n", idma_wins_no, MV_WIN_IDMA_MAX - c); return (0); } wintab = idma_wins; rv = 1; for (i = 0; i < idma_wins_no; i++, wintab++) { if (wintab->target == 0) { printf("IDMA window#%d: DDR target window is not " "supposed to be reprogrammed!\n", i); rv = 0; } if (wintab->remap >= 0 && win_cpu_can_remap(i) != 1) { printf("IDMA window#%d: not capable of remapping, but " "val 0x%08x defined\n", i, wintab->remap); rv = 0; } s = wintab->size; b = wintab->base; e = b + s - 1; if (s > (0xFFFFFFFF - b + 1)) { /* XXX this boundary check should account for 64bit and * remapping.. */ printf("IDMA window#%d: no space for size 0x%08x at " "0x%08x\n", i, s, b); rv = 0; continue; } j = decode_win_overlap(i, idma_wins_no, &idma_wins[0]); if (j >= 0) { printf("IDMA window#%d: (0x%08x - 0x%08x) overlaps " "with #%d (0x%08x - 0x%08x)\n", i, b, e, j, idma_wins[j].base, idma_wins[j].base + idma_wins[j].size - 1); rv = 0; } } return (rv); } void decode_win_idma_dump(u_long base) { int i; if (pm_is_disabled(CPU_PM_CTRL_IDMA)) return; for (i = 0; i < MV_WIN_IDMA_MAX; i++) { printf("IDMA window#%d: b 0x%08x, s 0x%08x", i, win_idma_br_read(base, i), win_idma_sz_read(base, i)); if (win_idma_can_remap(i)) printf(", ha 0x%08x", win_idma_har_read(base, i)); printf("\n"); } for (i = 0; i < MV_IDMA_CHAN_MAX; i++) printf("IDMA channel#%d: ap 0x%08x\n", i, win_idma_cap_read(base, i)); printf("IDMA windows: bare 0x%08x\n", win_idma_bare_read(base)); } #else /* Provide dummy functions to satisfy the build for SoCs not equipped with IDMA */ int decode_win_idma_valid(void) { return (1); } void decode_win_idma_setup(u_long base) { } void decode_win_idma_dump(u_long base) { } #endif /************************************************************************** * XOR windows routines **************************************************************************/ #if defined(SOC_MV_KIRKWOOD) || defined(SOC_MV_DISCOVERY) static int xor_ctrl_read(u_long base, int i, int c, int e) { uint32_t v; v = win_xor_ctrl_read(base, c, e); v &= (1 << i); return (v >> i); } static void xor_ctrl_write(u_long base, int i, int c, int e, int val) { uint32_t v; v = win_xor_ctrl_read(base, c, e); v &= ~(1 << i); v |= (val << i); win_xor_ctrl_write(base, c, e, v); } /* * Set channel protection 'val' for window 'w' on channel 'c' */ static void xor_chan_write(u_long base, int c, int e, int w, int val) { uint32_t v; v = win_xor_ctrl_read(base, c, e); v &= ~(0x3 << (w * 2 + 16)); v |= (val << (w * 2 + 16)); win_xor_ctrl_write(base, c, e, v); } /* * Set protection 'val' on all channels for window 'w' on engine 'e' */ static void xor_set_prot(u_long base, int w, int e, int val) { int c; for (c = 0; c < MV_XOR_CHAN_MAX; c++) xor_chan_write(base, c, e, w, val); } static int win_xor_can_remap(int i) { /* XOR decode windows 0-3 have remap capability */ if (i < 4) return (1); return (0); } static int xor_max_eng(void) { uint32_t dev, rev; soc_id(&dev, &rev); switch (dev) { case MV_DEV_88F6281: case MV_DEV_88F6282: case MV_DEV_MV78130: case MV_DEV_MV78160: case MV_DEV_MV78230: case MV_DEV_MV78260: case MV_DEV_MV78460: return (2); case MV_DEV_MV78100: case MV_DEV_MV78100_Z0: return (1); default: return (0); } } static void xor_active_dram(u_long base, int c, int e, int *window) { uint32_t br, sz; int i, m, w; /* * Set up access to all active DRAM banks */ m = xor_max_eng(); for (i = 0; i < m; i++) if (ddr_is_active(i)) { br = ddr_base(i) | (ddr_attr(i) << 8) | ddr_target(i); sz = ((ddr_size(i) - 1) & 0xffff0000); /* Place DDR entries in non-remapped windows */ for (w = 0; w < MV_WIN_XOR_MAX; w++) if (win_xor_can_remap(w) != 1 && (xor_ctrl_read(base, w, c, e) == 0) && w > *window) { /* Configure window */ win_xor_br_write(base, w, e, br); win_xor_sz_write(base, w, e, sz); /* Set protection RW on all channels */ xor_set_prot(base, w, e, 0x3); /* Enable window */ xor_ctrl_write(base, w, c, e, 1); (*window)++; break; } } } void decode_win_xor_setup(u_long base) { uint32_t br, sz; int i, j, z, e = 1, m, window; if (pm_is_disabled(CPU_PM_CTRL_XOR)) return; /* * Disable and clear all XOR windows, revoke protection for all * channels */ m = xor_max_eng(); for (j = 0; j < m; j++, e--) { /* Number of non-remaped windows */ window = MV_XOR_NON_REMAP - 1; for (i = 0; i < MV_WIN_XOR_MAX; i++) { win_xor_br_write(base, i, e, 0); win_xor_sz_write(base, i, e, 0); } if (win_xor_can_remap(i) == 1) win_xor_har_write(base, i, e, 0); for (i = 0; i < MV_XOR_CHAN_MAX; i++) { win_xor_ctrl_write(base, i, e, 0); xor_active_dram(base, i, e, &window); } /* * Remaining targets -- from a statically defined table */ for (i = 0; i < xor_wins_no; i++) if (xor_wins[i].target > 0) { br = (xor_wins[i].base & 0xffff0000) | (xor_wins[i].attr << 8) | xor_wins[i].target; sz = ((xor_wins[i].size - 1) & 0xffff0000); /* Set the first free XOR window */ for (z = 0; z < MV_WIN_XOR_MAX; z++) { if (xor_ctrl_read(base, z, 0, e) && xor_ctrl_read(base, z, 1, e)) continue; /* Configure window */ win_xor_br_write(base, z, e, br); win_xor_sz_write(base, z, e, sz); if (win_xor_can_remap(z) && xor_wins[z].remap >= 0) win_xor_har_write(base, z, e, xor_wins[z].remap); /* Set protection RW on all channels */ xor_set_prot(base, z, e, 0x3); /* Enable window */ xor_ctrl_write(base, z, 0, e, 1); xor_ctrl_write(base, z, 1, e, 1); break; } } } } int decode_win_xor_valid(void) { const struct decode_win *wintab; int c, i, j, rv; uint32_t b, e, s; if (xor_wins_no > MV_WIN_XOR_MAX) { printf("XOR windows: too many entries: %d\n", xor_wins_no); return (0); } for (i = 0, c = 0; i < MV_WIN_DDR_MAX; i++) if (ddr_is_active(i)) c++; if (xor_wins_no > (MV_WIN_XOR_MAX - c)) { printf("XOR windows: too many entries: %d, available: %d\n", xor_wins_no, MV_WIN_IDMA_MAX - c); return (0); } wintab = xor_wins; rv = 1; for (i = 0; i < xor_wins_no; i++, wintab++) { if (wintab->target == 0) { printf("XOR window#%d: DDR target window is not " "supposed to be reprogrammed!\n", i); rv = 0; } if (wintab->remap >= 0 && win_cpu_can_remap(i) != 1) { printf("XOR window#%d: not capable of remapping, but " "val 0x%08x defined\n", i, wintab->remap); rv = 0; } s = wintab->size; b = wintab->base; e = b + s - 1; if (s > (0xFFFFFFFF - b + 1)) { /* * XXX this boundary check should account for 64bit * and remapping.. */ printf("XOR window#%d: no space for size 0x%08x at " "0x%08x\n", i, s, b); rv = 0; continue; } j = decode_win_overlap(i, xor_wins_no, &xor_wins[0]); if (j >= 0) { printf("XOR window#%d: (0x%08x - 0x%08x) overlaps " "with #%d (0x%08x - 0x%08x)\n", i, b, e, j, xor_wins[j].base, xor_wins[j].base + xor_wins[j].size - 1); rv = 0; } } return (rv); } void decode_win_xor_dump(u_long base) { int i, j; int e = 1; if (pm_is_disabled(CPU_PM_CTRL_XOR)) return; for (j = 0; j < xor_max_eng(); j++, e--) { for (i = 0; i < MV_WIN_XOR_MAX; i++) { printf("XOR window#%d: b 0x%08x, s 0x%08x", i, win_xor_br_read(base, i, e), win_xor_sz_read(base, i, e)); if (win_xor_can_remap(i)) printf(", ha 0x%08x", win_xor_har_read(base, i, e)); printf("\n"); } for (i = 0; i < MV_XOR_CHAN_MAX; i++) printf("XOR control#%d: 0x%08x\n", i, win_xor_ctrl_read(base, i, e)); } } #else /* Provide dummy functions to satisfy the build for SoCs not equipped with XOR */ static int decode_win_xor_valid(void) { return (1); } static void decode_win_xor_setup(u_long base) { } static void decode_win_xor_dump(u_long base) { } #endif /************************************************************************** * SATA windows routines **************************************************************************/ static void decode_win_sata_setup(u_long base) { uint32_t cr, br; int i, j; if (pm_is_disabled(CPU_PM_CTRL_SATA)) return; for (i = 0; i < MV_WIN_SATA_MAX; i++) { win_sata_cr_write(base, i, 0); win_sata_br_write(base, i, 0); } for (i = 0; i < MV_WIN_DDR_MAX; i++) if (ddr_is_active(i)) { cr = ((ddr_size(i) - 1) & 0xffff0000) | (ddr_attr(i) << 8) | (ddr_target(i) << 4) | 1; br = ddr_base(i); /* Use the first available SATA window */ for (j = 0; j < MV_WIN_SATA_MAX; j++) { if ((win_sata_cr_read(base, j) & 1) != 0) continue; win_sata_br_write(base, j, br); win_sata_cr_write(base, j, cr); break; } } } /* * Configure AHCI decoding windows */ static void decode_win_ahci_setup(u_long base) { uint32_t br, cr, sz; int i, j; for (i = 0; i < MV_WIN_SATA_MAX_ARMADA38X; i++) { win_sata_armada38x_cr_write(base, i, 0); win_sata_armada38x_br_write(base, i, 0); win_sata_armada38x_sz_write(base, i, 0); } for (i = 0; i < MV_WIN_DDR_MAX; i++) { if (ddr_is_active(i)) { cr = (ddr_attr(i) << IO_WIN_ATTR_SHIFT) | (ddr_target(i) << IO_WIN_TGT_SHIFT) | IO_WIN_ENA_MASK; br = ddr_base(i); sz = (ddr_size(i) - 1) & (IO_WIN_SIZE_MASK << IO_WIN_SIZE_SHIFT); /* Use first available SATA window */ for (j = 0; j < MV_WIN_SATA_MAX_ARMADA38X; j++) { if (win_sata_armada38x_cr_read(base, j) & IO_WIN_ENA_MASK) continue; /* BASE is set to DRAM base (0x00000000) */ win_sata_armada38x_br_write(base, j, br); /* CTRL targets DRAM ctrl with 0x0E or 0x0D */ win_sata_armada38x_cr_write(base, j, cr); /* SIZE is set to 16MB - max value */ win_sata_armada38x_sz_write(base, j, sz); break; } } } } static void decode_win_ahci_dump(u_long base) { int i; for (i = 0; i < MV_WIN_SATA_MAX_ARMADA38X; i++) printf("SATA window#%d: cr 0x%08x, br 0x%08x, sz 0x%08x\n", i, win_sata_armada38x_cr_read(base, i), win_sata_br_read(base, i), win_sata_armada38x_sz_read(base,i)); } static int decode_win_sata_valid(void) { uint32_t dev, rev; soc_id(&dev, &rev); if (dev == MV_DEV_88F5281) return (1); return (decode_win_can_cover_ddr(MV_WIN_SATA_MAX)); } static void decode_win_sdhci_setup(u_long base) { uint32_t cr, br; int i, j; for (i = 0; i < MV_WIN_SDHCI_MAX; i++) { win_sdhci_cr_write(base, i, 0); win_sdhci_br_write(base, i, 0); } for (i = 0; i < MV_WIN_DDR_MAX; i++) if (ddr_is_active(i)) { br = ddr_base(i); cr = (((ddr_size(i) - 1) & (IO_WIN_SIZE_MASK << IO_WIN_SIZE_SHIFT)) | (ddr_attr(i) << IO_WIN_ATTR_SHIFT) | (ddr_target(i) << IO_WIN_TGT_SHIFT) | IO_WIN_ENA_MASK); /* Use the first available SDHCI window */ for (j = 0; j < MV_WIN_SDHCI_MAX; j++) { if (win_sdhci_cr_read(base, j) & IO_WIN_ENA_MASK) continue; win_sdhci_cr_write(base, j, cr); win_sdhci_br_write(base, j, br); break; } } } static void decode_win_sdhci_dump(u_long base) { int i; for (i = 0; i < MV_WIN_SDHCI_MAX; i++) printf("SDHCI window#%d: c 0x%08x, b 0x%08x\n", i, win_sdhci_cr_read(base, i), win_sdhci_br_read(base, i)); } static int decode_win_sdhci_valid(void) { return (decode_win_can_cover_ddr(MV_WIN_SDHCI_MAX)); } /************************************************************************** * FDT parsing routines. **************************************************************************/ static int fdt_get_ranges(const char *nodename, void *buf, int size, int *tuples, int *tuplesize) { phandle_t node; pcell_t addr_cells, par_addr_cells, size_cells; int len, tuple_size, tuples_count; node = OF_finddevice(nodename); if (node == -1) return (EINVAL); if ((fdt_addrsize_cells(node, &addr_cells, &size_cells)) != 0) return (ENXIO); par_addr_cells = fdt_parent_addr_cells(node); if (par_addr_cells > 2) return (ERANGE); tuple_size = sizeof(pcell_t) * (addr_cells + par_addr_cells + size_cells); /* Note the OF_getprop_alloc() cannot be used at this early stage. */ len = OF_getprop(node, "ranges", buf, size); /* * XXX this does not handle the empty 'ranges;' case, which is * legitimate and should be allowed. */ tuples_count = len / tuple_size; if (tuples_count <= 0) return (ERANGE); if (par_addr_cells > 2 || addr_cells > 2 || size_cells > 2) return (ERANGE); *tuples = tuples_count; *tuplesize = tuple_size; return (0); } static int win_cpu_from_dt(void) { pcell_t ranges[48]; phandle_t node; int i, entry_size, err, t, tuple_size, tuples; u_long sram_base, sram_size; t = 0; /* Retrieve 'ranges' property of '/localbus' node. */ if ((err = fdt_get_ranges("/localbus", ranges, sizeof(ranges), &tuples, &tuple_size)) == 0) { /* * Fill CPU decode windows table. */ bzero((void *)&cpu_win_tbl, sizeof(cpu_win_tbl)); entry_size = tuple_size / sizeof(pcell_t); cpu_wins_no = tuples; /* Check range */ if (tuples > nitems(cpu_win_tbl)) { debugf("too many tuples to fit into cpu_win_tbl\n"); return (ENOMEM); } for (i = 0, t = 0; t < tuples; i += entry_size, t++) { cpu_win_tbl[t].target = 1; cpu_win_tbl[t].attr = fdt32_to_cpu(ranges[i + 1]); cpu_win_tbl[t].base = fdt32_to_cpu(ranges[i + 2]); cpu_win_tbl[t].size = fdt32_to_cpu(ranges[i + 3]); cpu_win_tbl[t].remap = ~0; debugf("target = 0x%0x attr = 0x%0x base = 0x%0x " "size = 0x%0x remap = 0x%0x\n", cpu_win_tbl[t].target, cpu_win_tbl[t].attr, cpu_win_tbl[t].base, cpu_win_tbl[t].size, cpu_win_tbl[t].remap); } } /* * Retrieve CESA SRAM data. */ if ((node = OF_finddevice("sram")) != -1) if (ofw_bus_node_is_compatible(node, "mrvl,cesa-sram")) goto moveon; if ((node = OF_finddevice("/")) == -1) return (ENXIO); if ((node = fdt_find_compatible(node, "mrvl,cesa-sram", 0)) == 0) /* SRAM block is not always present. */ return (0); moveon: sram_base = sram_size = 0; if (fdt_regsize(node, &sram_base, &sram_size) != 0) return (EINVAL); /* Check range */ if (t >= nitems(cpu_win_tbl)) { debugf("cannot fit CESA tuple into cpu_win_tbl\n"); return (ENOMEM); } cpu_win_tbl[t].target = soc_decode_win_spec->win_cesa_target; if (soc_family == MV_SOC_ARMADA_38X) cpu_win_tbl[t].attr = soc_decode_win_spec->win_cesa_attr(0); else cpu_win_tbl[t].attr = soc_decode_win_spec->win_cesa_attr(1); cpu_win_tbl[t].base = sram_base; cpu_win_tbl[t].size = sram_size; cpu_win_tbl[t].remap = ~0; cpu_wins_no++; debugf("sram: base = 0x%0lx size = 0x%0lx\n", sram_base, sram_size); /* Check if there is a second CESA node */ while ((node = OF_peer(node)) != 0) { if (ofw_bus_node_is_compatible(node, "mrvl,cesa-sram")) { if (fdt_regsize(node, &sram_base, &sram_size) != 0) return (EINVAL); break; } } if (node == 0) return (0); t++; if (t >= nitems(cpu_win_tbl)) { debugf("cannot fit CESA tuple into cpu_win_tbl\n"); return (ENOMEM); } /* Configure window for CESA1 */ cpu_win_tbl[t].target = soc_decode_win_spec->win_cesa_target; cpu_win_tbl[t].attr = soc_decode_win_spec->win_cesa_attr(1); cpu_win_tbl[t].base = sram_base; cpu_win_tbl[t].size = sram_size; cpu_win_tbl[t].remap = ~0; cpu_wins_no++; debugf("sram: base = 0x%0lx size = 0x%0lx\n", sram_base, sram_size); return (0); } static int fdt_win_process(phandle_t child) { int i; struct soc_node_spec *soc_node; int addr_cells, size_cells; pcell_t reg[8]; u_long size, base; for (i = 0; soc_nodes[i].compat != NULL; i++) { soc_node = &soc_nodes[i]; /* Setup only for enabled devices */ if (ofw_bus_node_status_okay(child) == 0) continue; if (!ofw_bus_node_is_compatible(child, soc_node->compat)) continue; if (fdt_addrsize_cells(OF_parent(child), &addr_cells, &size_cells)) return (ENXIO); if ((sizeof(pcell_t) * (addr_cells + size_cells)) > sizeof(reg)) return (ENOMEM); if (OF_getprop(child, "reg", ®, sizeof(reg)) <= 0) return (EINVAL); if (addr_cells <= 2) base = fdt_data_get(®[0], addr_cells); else base = fdt_data_get(®[addr_cells - 2], 2); size = fdt_data_get(®[addr_cells], size_cells); if (soc_node->valid_handler != NULL) if (!soc_node->valid_handler()) return (EINVAL); base = (base & 0x000fffff) | fdt_immr_va; if (soc_node->decode_handler != NULL) soc_node->decode_handler(base); else return (ENXIO); if (MV_DUMP_WIN && (soc_node->dump_handler != NULL)) soc_node->dump_handler(base); } return (0); } static int fdt_win_setup(void) { phandle_t node, child, sb; phandle_t child_pci; int err; sb = 0; node = OF_finddevice("/"); if (node == -1) panic("fdt_win_setup: no root node"); /* Allow for coherent transactions on the A38x MBUS */ if (ofw_bus_node_is_compatible(node, "marvell,armada380")) platform_io_coherent = true; /* * Traverse through all children of root and simple-bus nodes. * For each found device retrieve decode windows data (if applicable). */ child = OF_child(node); while (child != 0) { /* Lookup for callback and run */ err = fdt_win_process(child); if (err != 0) return (err); /* Process Marvell Armada-XP/38x PCIe controllers */ if (ofw_bus_node_is_compatible(child, "marvell,armada-370-pcie")) { child_pci = OF_child(child); while (child_pci != 0) { err = fdt_win_process(child_pci); if (err != 0) return (err); child_pci = OF_peer(child_pci); } } /* * Once done with root-level children let's move down to * simple-bus and its children. */ child = OF_peer(child); if ((child == 0) && (node == OF_finddevice("/"))) { sb = node = fdt_find_compatible(node, "simple-bus", 0); if (node == 0) return (ENXIO); child = OF_child(node); } /* * Next, move one more level down to internal-regs node (if * it is present) and its children. This node also have * "simple-bus" compatible. */ if ((child == 0) && (node == sb)) { node = fdt_find_compatible(node, "simple-bus", 0); if (node == 0) return (0); child = OF_child(node); } } return (0); } static void fdt_fixup_busfreq(phandle_t root) { phandle_t sb; pcell_t freq; freq = cpu_to_fdt32(get_tclk()); /* * Fix bus speed in cpu node */ if ((sb = OF_finddevice("cpu")) != -1) if (fdt_is_compatible_strict(sb, "ARM,88VS584")) OF_setprop(sb, "bus-frequency", (void *)&freq, sizeof(freq)); /* * This fixup sets the simple-bus bus-frequency property. */ if ((sb = fdt_find_compatible(root, "simple-bus", 1)) != 0) OF_setprop(sb, "bus-frequency", (void *)&freq, sizeof(freq)); } static void fdt_fixup_ranges(phandle_t root) { phandle_t node; pcell_t par_addr_cells, addr_cells, size_cells; pcell_t ranges[3], reg[2], *rangesptr; int len, tuple_size, tuples_count; uint32_t base; /* Fix-up SoC ranges according to real fdt_immr_pa */ if ((node = fdt_find_compatible(root, "simple-bus", 1)) != 0) { if (fdt_addrsize_cells(node, &addr_cells, &size_cells) == 0 && (par_addr_cells = fdt_parent_addr_cells(node) <= 2)) { tuple_size = sizeof(pcell_t) * (par_addr_cells + addr_cells + size_cells); len = OF_getprop(node, "ranges", ranges, sizeof(ranges)); tuples_count = len / tuple_size; /* Unexpected settings are not supported */ if (tuples_count != 1) goto fixup_failed; rangesptr = &ranges[0]; rangesptr += par_addr_cells; base = fdt_data_get((void *)rangesptr, addr_cells); *rangesptr = cpu_to_fdt32(fdt_immr_pa); if (OF_setprop(node, "ranges", (void *)&ranges[0], sizeof(ranges)) < 0) goto fixup_failed; } } /* Fix-up PCIe reg according to real PCIe registers' PA */ if ((node = fdt_find_compatible(root, "mrvl,pcie", 1)) != 0) { if (fdt_addrsize_cells(OF_parent(node), &par_addr_cells, &size_cells) == 0) { tuple_size = sizeof(pcell_t) * (par_addr_cells + size_cells); len = OF_getprop(node, "reg", reg, sizeof(reg)); tuples_count = len / tuple_size; /* Unexpected settings are not supported */ if (tuples_count != 1) goto fixup_failed; base = fdt_data_get((void *)®[0], par_addr_cells); base &= ~0xFF000000; base |= fdt_immr_pa; reg[0] = cpu_to_fdt32(base); if (OF_setprop(node, "reg", (void *)®[0], sizeof(reg)) < 0) goto fixup_failed; } } /* Fix-up succeeded. May return and continue */ return; fixup_failed: while (1) { /* * In case of any error while fixing ranges just hang. * 1. No message can be displayed yet since console * is not initialized. * 2. Going further will cause failure on bus_space_map() * relying on the wrong ranges or data abort when * accessing PCIe registers. */ } } struct fdt_fixup_entry fdt_fixup_table[] = { { "mrvl,DB-88F6281", &fdt_fixup_busfreq }, { "mrvl,DB-78460", &fdt_fixup_busfreq }, { "mrvl,DB-78460", &fdt_fixup_ranges }, { NULL, NULL } }; #if __ARM_ARCH >= 6 uint32_t get_tclk(void) { if (soc_decode_win_spec->get_tclk != NULL) return soc_decode_win_spec->get_tclk(); else return -1; } uint32_t get_cpu_freq(void) { if (soc_decode_win_spec->get_cpu_freq != NULL) return soc_decode_win_spec->get_cpu_freq(); else return -1; } #endif #ifndef INTRNG static int fdt_pic_decode_ic(phandle_t node, pcell_t *intr, int *interrupt, int *trig, int *pol) { if (!ofw_bus_node_is_compatible(node, "mrvl,pic") && !ofw_bus_node_is_compatible(node, "mrvl,mpic")) return (ENXIO); *interrupt = fdt32_to_cpu(intr[0]); *trig = INTR_TRIGGER_CONFORM; *pol = INTR_POLARITY_CONFORM; return (0); } fdt_pic_decode_t fdt_pic_table[] = { &fdt_pic_decode_ic, NULL }; #endif Index: head/sys/arm/mv/std-pj4b.mv =================================================================== --- head/sys/arm/mv/std-pj4b.mv (revision 331994) +++ head/sys/arm/mv/std-pj4b.mv (revision 331995) @@ -1,13 +1,12 @@ # $FreeBSD$ -files "../mv/files.mv" files "../mv/files.arm7" cpu CPU_MV_PJ4B machine arm armv7 makeoptions CONF_CFLAGS="-march=armv7a" # This was originally defined as "(KERNBASE-(1024*1024*1024))" but that # (in opt_global.h) clashed with the value emitted by genassym which # reduces the original macro text to its numeric value. The only way # to avoid that is to define it here as the numeric value genassym emits. options VM_MAXUSER_ADDRESS="0x80000000"