Index: stable/11/sys/arm/at91/at91_spi.c =================================================================== --- stable/11/sys/arm/at91/at91_spi.c (revision 331505) +++ stable/11/sys/arm/at91/at91_spi.c (revision 331506) @@ -1,460 +1,462 @@ /*- * SPDX-License-Identifier: BSD-2-Clause-FreeBSD * * Copyright (c) 2006 M. Warner Losh. * Copyright (c) 2011-2012 Ian Lepore. * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. */ #include "opt_platform.h" #include __FBSDID("$FreeBSD$"); #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #ifdef FDT #include #include #include #endif #include "spibus_if.h" struct at91_spi_softc { device_t dev; /* Myself */ void *intrhand; /* Interrupt handle */ struct resource *irq_res; /* IRQ resource */ struct resource *mem_res; /* Memory resource */ bus_dma_tag_t dmatag; /* bus dma tag for transfers */ bus_dmamap_t map[4]; /* Maps for the transaction */ struct sx xfer_mtx; /* Enforce one transfer at a time */ uint32_t xfer_done; /* interrupt<->mainthread signaling */ }; #define CS_TO_MR(cs) ((~(1 << (cs)) & 0x0f) << 16) static inline uint32_t RD4(struct at91_spi_softc *sc, bus_size_t off) { return (bus_read_4(sc->mem_res, off)); } static inline void WR4(struct at91_spi_softc *sc, bus_size_t off, uint32_t val) { bus_write_4(sc->mem_res, off, val); } /* bus entry points */ static int at91_spi_attach(device_t dev); static int at91_spi_detach(device_t dev); static int at91_spi_probe(device_t dev); static int at91_spi_transfer(device_t dev, device_t child, struct spi_command *cmd); /* helper routines */ static void at91_getaddr(void *arg, bus_dma_segment_t *segs, int nsegs, int error); static int at91_spi_activate(device_t dev); static void at91_spi_deactivate(device_t dev); static void at91_spi_intr(void *arg); static int at91_spi_probe(device_t dev) { #ifdef FDT if (!ofw_bus_is_compatible(dev, "atmel,at91rm9200-spi")) return (ENXIO); #endif device_set_desc(dev, "AT91 SPI"); return (0); } static int at91_spi_attach(device_t dev) { struct at91_spi_softc *sc; int err; uint32_t csr; sc = device_get_softc(dev); sc->dev = dev; sx_init(&sc->xfer_mtx, device_get_nameunit(dev)); /* * Allocate resources. */ err = at91_spi_activate(dev); if (err) goto out; #ifdef FDT /* * Disable devices need to hold their resources, so return now and not attach * the spibus, setup interrupt handlers, etc. */ if (!ofw_bus_status_okay(dev)) return 0; #endif /* * Set up the hardware. */ WR4(sc, SPI_CR, SPI_CR_SWRST); /* "Software Reset must be Written Twice" erratum */ WR4(sc, SPI_CR, SPI_CR_SWRST); WR4(sc, SPI_IDR, 0xffffffff); WR4(sc, SPI_MR, (0xf << 24) | SPI_MR_MSTR | SPI_MR_MODFDIS | CS_TO_MR(0)); /* * For now, run the bus at the slowest speed possible as otherwise we * may encounter data corruption on transmit as seen with ETHERNUT5 * and AT45DB321D even though both board and slave device can take * more. * This also serves as a work-around for the "NPCSx rises if no data * data is to be transmitted" erratum. The ideal workaround for the * latter is to take the chip select control away from the peripheral * and manage it directly as a GPIO line. The easy solution is to * slow down the bus so dramatically that it just never gets starved * as may be seen when the OCHI controller is running and consuming * memory and APB bandwidth. * Also, currently we lack a way for lettting both the board and the * slave devices take their maximum supported SPI clocks into account. * Also, we hard-wire SPI mode to 3. */ csr = SPI_CSR_CPOL | (4 << 16) | (0xff << 8); WR4(sc, SPI_CSR0, csr); WR4(sc, SPI_CSR1, csr); WR4(sc, SPI_CSR2, csr); WR4(sc, SPI_CSR3, csr); WR4(sc, SPI_CR, SPI_CR_SPIEN); WR4(sc, PDC_PTCR, PDC_PTCR_TXTDIS); WR4(sc, PDC_PTCR, PDC_PTCR_RXTDIS); WR4(sc, PDC_RNPR, 0); WR4(sc, PDC_RNCR, 0); WR4(sc, PDC_TNPR, 0); WR4(sc, PDC_TNCR, 0); WR4(sc, PDC_RPR, 0); WR4(sc, PDC_RCR, 0); WR4(sc, PDC_TPR, 0); WR4(sc, PDC_TCR, 0); RD4(sc, SPI_RDR); RD4(sc, SPI_SR); device_add_child(dev, "spibus", -1); bus_generic_attach(dev); out: if (err) at91_spi_deactivate(dev); return (err); } static int at91_spi_detach(device_t dev) { return (EBUSY); /* XXX */ } static int at91_spi_activate(device_t dev) { struct at91_spi_softc *sc; int err, i, rid; sc = device_get_softc(dev); err = ENOMEM; rid = 0; sc->mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, RF_ACTIVE); if (sc->mem_res == NULL) goto out; rid = 0; sc->irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, RF_ACTIVE); if (sc->irq_res == NULL) goto out; err = bus_setup_intr(dev, sc->irq_res, INTR_TYPE_MISC | INTR_MPSAFE, NULL, at91_spi_intr, sc, &sc->intrhand); if (err != 0) goto out; err = bus_dma_tag_create(bus_get_dma_tag(dev), 1, 0, BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, 2048, 1, 2048, BUS_DMA_ALLOCNOW, NULL, NULL, &sc->dmatag); if (err != 0) goto out; for (i = 0; i < 4; i++) { err = bus_dmamap_create(sc->dmatag, 0, &sc->map[i]); if (err != 0) goto out; } out: if (err != 0) at91_spi_deactivate(dev); return (err); } static void at91_spi_deactivate(device_t dev) { struct at91_spi_softc *sc; int i; sc = device_get_softc(dev); bus_generic_detach(dev); for (i = 0; i < 4; i++) if (sc->map[i]) bus_dmamap_destroy(sc->dmatag, sc->map[i]); if (sc->dmatag) bus_dma_tag_destroy(sc->dmatag); if (sc->intrhand) bus_teardown_intr(dev, sc->irq_res, sc->intrhand); sc->intrhand = NULL; if (sc->irq_res) bus_release_resource(dev, SYS_RES_IRQ, rman_get_rid(sc->irq_res), sc->irq_res); sc->irq_res = NULL; if (sc->mem_res) bus_release_resource(dev, SYS_RES_MEMORY, rman_get_rid(sc->mem_res), sc->mem_res); sc->mem_res = NULL; } static void at91_getaddr(void *arg, bus_dma_segment_t *segs, int nsegs __unused, int error) { if (error != 0) return; *(bus_addr_t *)arg = segs[0].ds_addr; } static int at91_spi_transfer(device_t dev, device_t child, struct spi_command *cmd) { struct at91_spi_softc *sc; bus_addr_t addr; int err, i, j, mode[4]; uint32_t cs; KASSERT(cmd->tx_cmd_sz == cmd->rx_cmd_sz, ("%s: TX/RX command sizes should be equal", __func__)); KASSERT(cmd->tx_data_sz == cmd->rx_data_sz, ("%s: TX/RX data sizes should be equal", __func__)); /* get the proper chip select */ spibus_get_cs(child, &cs); + cs &= ~SPIBUS_CS_HIGH; + sc = device_get_softc(dev); i = 0; sx_xlock(&sc->xfer_mtx); /* * Disable transfers while we set things up. */ WR4(sc, PDC_PTCR, PDC_PTCR_TXTDIS | PDC_PTCR_RXTDIS); /* * PSCDEC = 0 has a range of 0..3 for chip select. We * don't support PSCDEC = 1 which has a range of 0..15. */ if (cs > 3) { device_printf(dev, "Invalid chip select %d requested by %s\n", cs, device_get_nameunit(child)); err = EINVAL; goto out; } #ifdef SPI_CHIP_SELECT_HIGH_SUPPORT /* * The AT91RM9200 couldn't do CS high for CS 0. Other chips can, but we * don't support that yet, or other spi modes. */ if (at91_is_rm92() && cs == 0 && (cmd->flags & SPI_CHIP_SELECT_HIGH) != 0) { device_printf(dev, "Invalid chip select high requested by %s for cs 0.\n", device_get_nameunit(child)); err = EINVAL; goto out; } #endif err = (RD4(sc, SPI_MR) & ~0x000f0000) | CS_TO_MR(cs); WR4(sc, SPI_MR, err); /* * Set up the TX side of the transfer. */ if ((err = bus_dmamap_load(sc->dmatag, sc->map[i], cmd->tx_cmd, cmd->tx_cmd_sz, at91_getaddr, &addr, 0)) != 0) goto out; WR4(sc, PDC_TPR, addr); WR4(sc, PDC_TCR, cmd->tx_cmd_sz); bus_dmamap_sync(sc->dmatag, sc->map[i], BUS_DMASYNC_PREWRITE); mode[i++] = BUS_DMASYNC_POSTWRITE; if (cmd->tx_data_sz > 0) { if ((err = bus_dmamap_load(sc->dmatag, sc->map[i], cmd->tx_data, cmd->tx_data_sz, at91_getaddr, &addr, 0)) != 0) goto out; WR4(sc, PDC_TNPR, addr); WR4(sc, PDC_TNCR, cmd->tx_data_sz); bus_dmamap_sync(sc->dmatag, sc->map[i], BUS_DMASYNC_PREWRITE); mode[i++] = BUS_DMASYNC_POSTWRITE; } /* * Set up the RX side of the transfer. */ if ((err = bus_dmamap_load(sc->dmatag, sc->map[i], cmd->rx_cmd, cmd->rx_cmd_sz, at91_getaddr, &addr, 0)) != 0) goto out; WR4(sc, PDC_RPR, addr); WR4(sc, PDC_RCR, cmd->rx_cmd_sz); bus_dmamap_sync(sc->dmatag, sc->map[i], BUS_DMASYNC_PREREAD); mode[i++] = BUS_DMASYNC_POSTREAD; if (cmd->rx_data_sz > 0) { if ((err = bus_dmamap_load(sc->dmatag, sc->map[i], cmd->rx_data, cmd->rx_data_sz, at91_getaddr, &addr, 0)) != 0) goto out; WR4(sc, PDC_RNPR, addr); WR4(sc, PDC_RNCR, cmd->rx_data_sz); bus_dmamap_sync(sc->dmatag, sc->map[i], BUS_DMASYNC_PREREAD); mode[i++] = BUS_DMASYNC_POSTREAD; } /* * Start the transfer, wait for it to complete. */ sc->xfer_done = 0; WR4(sc, SPI_IER, SPI_SR_RXBUFF); WR4(sc, PDC_PTCR, PDC_PTCR_TXTEN | PDC_PTCR_RXTEN); do err = tsleep(&sc->xfer_done, PCATCH | PZERO, "at91_spi", hz); while (sc->xfer_done == 0 && err != EINTR); /* * Stop the transfer and clean things up. */ WR4(sc, PDC_PTCR, PDC_PTCR_TXTDIS | PDC_PTCR_RXTDIS); if (err == 0) for (j = 0; j < i; j++) bus_dmamap_sync(sc->dmatag, sc->map[j], mode[j]); out: for (j = 0; j < i; j++) bus_dmamap_unload(sc->dmatag, sc->map[j]); sx_xunlock(&sc->xfer_mtx); return (err); } static void at91_spi_intr(void *arg) { struct at91_spi_softc *sc; uint32_t sr; sc = (struct at91_spi_softc*)arg; sr = RD4(sc, SPI_SR) & RD4(sc, SPI_IMR); if ((sr & SPI_SR_RXBUFF) != 0) { sc->xfer_done = 1; WR4(sc, SPI_IDR, SPI_SR_RXBUFF); wakeup(&sc->xfer_done); } if ((sr & ~SPI_SR_RXBUFF) != 0) { device_printf(sc->dev, "Unexpected ISR %#x\n", sr); WR4(sc, SPI_IDR, sr & ~SPI_SR_RXBUFF); } } static devclass_t at91_spi_devclass; static device_method_t at91_spi_methods[] = { /* Device interface */ DEVMETHOD(device_probe, at91_spi_probe), DEVMETHOD(device_attach, at91_spi_attach), DEVMETHOD(device_detach, at91_spi_detach), /* spibus interface */ DEVMETHOD(spibus_transfer, at91_spi_transfer), DEVMETHOD_END }; static driver_t at91_spi_driver = { "spi", at91_spi_methods, sizeof(struct at91_spi_softc), }; #ifdef FDT DRIVER_MODULE(at91_spi, simplebus, at91_spi_driver, at91_spi_devclass, NULL, NULL); #else DRIVER_MODULE(at91_spi, atmelarm, at91_spi_driver, at91_spi_devclass, NULL, NULL); #endif Index: stable/11/sys/arm/broadcom/bcm2835/bcm2835_spi.c =================================================================== --- stable/11/sys/arm/broadcom/bcm2835/bcm2835_spi.c (revision 331505) +++ stable/11/sys/arm/broadcom/bcm2835/bcm2835_spi.c (revision 331506) @@ -1,528 +1,531 @@ /*- * SPDX-License-Identifier: BSD-2-Clause-FreeBSD * * Copyright (c) 2012 Oleksandr Tymoshenko * Copyright (c) 2013 Luiz Otavio O Souza * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. * */ #include __FBSDID("$FreeBSD$"); #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include "spibus_if.h" static struct ofw_compat_data compat_data[] = { {"broadcom,bcm2835-spi", 1}, {"brcm,bcm2835-spi", 1}, {NULL, 0} }; static void bcm_spi_intr(void *); #ifdef BCM_SPI_DEBUG static void bcm_spi_printr(device_t dev) { struct bcm_spi_softc *sc; uint32_t reg; sc = device_get_softc(dev); reg = BCM_SPI_READ(sc, SPI_CS); device_printf(dev, "CS=%b\n", reg, "\20\1CS0\2CS1\3CPHA\4CPOL\7CSPOL" "\10TA\11DMAEN\12INTD\13INTR\14ADCS\15REN\16LEN" "\21DONE\22RXD\23TXD\24RXR\25RXF\26CSPOL0\27CSPOL1" "\30CSPOL2\31DMA_LEN\32LEN_LONG"); reg = BCM_SPI_READ(sc, SPI_CLK) & SPI_CLK_MASK; if (reg % 2) reg--; if (reg == 0) reg = 65536; device_printf(dev, "CLK=%uMhz/%d=%luhz\n", SPI_CORE_CLK / 1000000, reg, SPI_CORE_CLK / reg); reg = BCM_SPI_READ(sc, SPI_DLEN) & SPI_DLEN_MASK; device_printf(dev, "DLEN=%d\n", reg); reg = BCM_SPI_READ(sc, SPI_LTOH) & SPI_LTOH_MASK; device_printf(dev, "LTOH=%d\n", reg); reg = BCM_SPI_READ(sc, SPI_DC); device_printf(dev, "DC=RPANIC=%#x RDREQ=%#x TPANIC=%#x TDREQ=%#x\n", (reg & SPI_DC_RPANIC_MASK) >> SPI_DC_RPANIC_SHIFT, (reg & SPI_DC_RDREQ_MASK) >> SPI_DC_RDREQ_SHIFT, (reg & SPI_DC_TPANIC_MASK) >> SPI_DC_TPANIC_SHIFT, (reg & SPI_DC_TDREQ_MASK) >> SPI_DC_TDREQ_SHIFT); } #endif static void bcm_spi_modifyreg(struct bcm_spi_softc *sc, uint32_t off, uint32_t mask, uint32_t value) { uint32_t reg; mtx_assert(&sc->sc_mtx, MA_OWNED); reg = BCM_SPI_READ(sc, off); reg &= ~mask; reg |= value; BCM_SPI_WRITE(sc, off, reg); } static int bcm_spi_clock_proc(SYSCTL_HANDLER_ARGS) { struct bcm_spi_softc *sc; uint32_t clk; int error; sc = (struct bcm_spi_softc *)arg1; BCM_SPI_LOCK(sc); clk = BCM_SPI_READ(sc, SPI_CLK); BCM_SPI_UNLOCK(sc); clk &= 0xffff; if (clk == 0) clk = 65536; clk = SPI_CORE_CLK / clk; error = sysctl_handle_int(oidp, &clk, sizeof(clk), req); if (error != 0 || req->newptr == NULL) return (error); clk = SPI_CORE_CLK / clk; if (clk <= 1) clk = 2; else if (clk % 2) clk--; if (clk > 0xffff) clk = 0; BCM_SPI_LOCK(sc); BCM_SPI_WRITE(sc, SPI_CLK, clk); BCM_SPI_UNLOCK(sc); return (0); } static int bcm_spi_cs_bit_proc(SYSCTL_HANDLER_ARGS, uint32_t bit) { struct bcm_spi_softc *sc; uint32_t reg; int error; sc = (struct bcm_spi_softc *)arg1; BCM_SPI_LOCK(sc); reg = BCM_SPI_READ(sc, SPI_CS); BCM_SPI_UNLOCK(sc); reg = (reg & bit) ? 1 : 0; error = sysctl_handle_int(oidp, ®, sizeof(reg), req); if (error != 0 || req->newptr == NULL) return (error); if (reg) reg = bit; BCM_SPI_LOCK(sc); bcm_spi_modifyreg(sc, SPI_CS, bit, reg); BCM_SPI_UNLOCK(sc); return (0); } static int bcm_spi_cpol_proc(SYSCTL_HANDLER_ARGS) { return (bcm_spi_cs_bit_proc(oidp, arg1, arg2, req, SPI_CS_CPOL)); } static int bcm_spi_cpha_proc(SYSCTL_HANDLER_ARGS) { return (bcm_spi_cs_bit_proc(oidp, arg1, arg2, req, SPI_CS_CPHA)); } static int bcm_spi_cspol0_proc(SYSCTL_HANDLER_ARGS) { return (bcm_spi_cs_bit_proc(oidp, arg1, arg2, req, SPI_CS_CSPOL0)); } static int bcm_spi_cspol1_proc(SYSCTL_HANDLER_ARGS) { return (bcm_spi_cs_bit_proc(oidp, arg1, arg2, req, SPI_CS_CSPOL1)); } static void bcm_spi_sysctl_init(struct bcm_spi_softc *sc) { struct sysctl_ctx_list *ctx; struct sysctl_oid *tree_node; struct sysctl_oid_list *tree; /* * Add system sysctl tree/handlers. */ ctx = device_get_sysctl_ctx(sc->sc_dev); tree_node = device_get_sysctl_tree(sc->sc_dev); tree = SYSCTL_CHILDREN(tree_node); SYSCTL_ADD_PROC(ctx, tree, OID_AUTO, "clock", CTLFLAG_RW | CTLTYPE_UINT, sc, sizeof(*sc), bcm_spi_clock_proc, "IU", "SPI BUS clock frequency"); SYSCTL_ADD_PROC(ctx, tree, OID_AUTO, "cpol", CTLFLAG_RW | CTLTYPE_UINT, sc, sizeof(*sc), bcm_spi_cpol_proc, "IU", "SPI BUS clock polarity"); SYSCTL_ADD_PROC(ctx, tree, OID_AUTO, "cpha", CTLFLAG_RW | CTLTYPE_UINT, sc, sizeof(*sc), bcm_spi_cpha_proc, "IU", "SPI BUS clock phase"); SYSCTL_ADD_PROC(ctx, tree, OID_AUTO, "cspol0", CTLFLAG_RW | CTLTYPE_UINT, sc, sizeof(*sc), bcm_spi_cspol0_proc, "IU", "SPI BUS chip select 0 polarity"); SYSCTL_ADD_PROC(ctx, tree, OID_AUTO, "cspol1", CTLFLAG_RW | CTLTYPE_UINT, sc, sizeof(*sc), bcm_spi_cspol1_proc, "IU", "SPI BUS chip select 1 polarity"); } static int bcm_spi_probe(device_t dev) { if (!ofw_bus_status_okay(dev)) return (ENXIO); if (ofw_bus_search_compatible(dev, compat_data)->ocd_data == 0) return (ENXIO); device_set_desc(dev, "BCM2708/2835 SPI controller"); return (BUS_PROBE_DEFAULT); } static int bcm_spi_attach(device_t dev) { struct bcm_spi_softc *sc; device_t gpio; int i, rid; if (device_get_unit(dev) != 0) { device_printf(dev, "only one SPI controller supported\n"); return (ENXIO); } sc = device_get_softc(dev); sc->sc_dev = dev; /* Configure the GPIO pins to ALT0 function to enable SPI the pins. */ gpio = devclass_get_device(devclass_find("gpio"), 0); if (!gpio) { device_printf(dev, "cannot find gpio0\n"); return (ENXIO); } for (i = 0; i < nitems(bcm_spi_pins); i++) bcm_gpio_set_alternate(gpio, bcm_spi_pins[i], BCM_GPIO_ALT0); rid = 0; sc->sc_mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, RF_ACTIVE); if (!sc->sc_mem_res) { device_printf(dev, "cannot allocate memory window\n"); return (ENXIO); } sc->sc_bst = rman_get_bustag(sc->sc_mem_res); sc->sc_bsh = rman_get_bushandle(sc->sc_mem_res); rid = 0; sc->sc_irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, RF_ACTIVE); if (!sc->sc_irq_res) { bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->sc_mem_res); device_printf(dev, "cannot allocate interrupt\n"); return (ENXIO); } /* Hook up our interrupt handler. */ if (bus_setup_intr(dev, sc->sc_irq_res, INTR_TYPE_MISC | INTR_MPSAFE, NULL, bcm_spi_intr, sc, &sc->sc_intrhand)) { bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sc_irq_res); bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->sc_mem_res); device_printf(dev, "cannot setup the interrupt handler\n"); return (ENXIO); } mtx_init(&sc->sc_mtx, "bcm_spi", NULL, MTX_DEF); /* Add sysctl nodes. */ bcm_spi_sysctl_init(sc); #ifdef BCM_SPI_DEBUG bcm_spi_printr(dev); #endif /* * Enable the SPI controller. Clear the rx and tx FIFO. * Defaults to SPI mode 0. */ BCM_SPI_WRITE(sc, SPI_CS, SPI_CS_CLEAR_RXFIFO | SPI_CS_CLEAR_TXFIFO); /* Set the SPI clock to 500Khz. */ BCM_SPI_WRITE(sc, SPI_CLK, SPI_CORE_CLK / 500000); #ifdef BCM_SPI_DEBUG bcm_spi_printr(dev); #endif device_add_child(dev, "spibus", -1); return (bus_generic_attach(dev)); } static int bcm_spi_detach(device_t dev) { struct bcm_spi_softc *sc; bus_generic_detach(dev); sc = device_get_softc(dev); mtx_destroy(&sc->sc_mtx); if (sc->sc_intrhand) bus_teardown_intr(dev, sc->sc_irq_res, sc->sc_intrhand); if (sc->sc_irq_res) bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sc_irq_res); if (sc->sc_mem_res) bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->sc_mem_res); return (0); } static void bcm_spi_fill_fifo(struct bcm_spi_softc *sc) { struct spi_command *cmd; uint32_t cs, written; uint8_t *data; cmd = sc->sc_cmd; cs = BCM_SPI_READ(sc, SPI_CS) & (SPI_CS_TA | SPI_CS_TXD); while (sc->sc_written < sc->sc_len && cs == (SPI_CS_TA | SPI_CS_TXD)) { data = (uint8_t *)cmd->tx_cmd; written = sc->sc_written++; if (written >= cmd->tx_cmd_sz) { data = (uint8_t *)cmd->tx_data; written -= cmd->tx_cmd_sz; } BCM_SPI_WRITE(sc, SPI_FIFO, data[written]); cs = BCM_SPI_READ(sc, SPI_CS) & (SPI_CS_TA | SPI_CS_TXD); } } static void bcm_spi_drain_fifo(struct bcm_spi_softc *sc) { struct spi_command *cmd; uint32_t cs, read; uint8_t *data; cmd = sc->sc_cmd; cs = BCM_SPI_READ(sc, SPI_CS) & SPI_CS_RXD; while (sc->sc_read < sc->sc_len && cs == SPI_CS_RXD) { data = (uint8_t *)cmd->rx_cmd; read = sc->sc_read++; if (read >= cmd->rx_cmd_sz) { data = (uint8_t *)cmd->rx_data; read -= cmd->rx_cmd_sz; } data[read] = BCM_SPI_READ(sc, SPI_FIFO) & 0xff; cs = BCM_SPI_READ(sc, SPI_CS) & SPI_CS_RXD; } } static void bcm_spi_intr(void *arg) { struct bcm_spi_softc *sc; sc = (struct bcm_spi_softc *)arg; BCM_SPI_LOCK(sc); /* Filter stray interrupts. */ if ((sc->sc_flags & BCM_SPI_BUSY) == 0) { BCM_SPI_UNLOCK(sc); return; } /* TX - Fill up the FIFO. */ bcm_spi_fill_fifo(sc); /* RX - Drain the FIFO. */ bcm_spi_drain_fifo(sc); /* Check for end of transfer. */ if (sc->sc_written == sc->sc_len && sc->sc_read == sc->sc_len) { /* Disable interrupts and the SPI engine. */ bcm_spi_modifyreg(sc, SPI_CS, SPI_CS_TA | SPI_CS_INTR | SPI_CS_INTD, 0); wakeup(sc->sc_dev); } BCM_SPI_UNLOCK(sc); } static int bcm_spi_transfer(device_t dev, device_t child, struct spi_command *cmd) { struct bcm_spi_softc *sc; uint32_t cs; int err; sc = device_get_softc(dev); KASSERT(cmd->tx_cmd_sz == cmd->rx_cmd_sz, ("TX/RX command sizes should be equal")); KASSERT(cmd->tx_data_sz == cmd->rx_data_sz, ("TX/RX data sizes should be equal")); /* Get the proper chip select for this child. */ spibus_get_cs(child, &cs); + + cs &= ~SPIBUS_CS_HIGH; + if (cs > 2) { device_printf(dev, "Invalid chip select %d requested by %s\n", cs, device_get_nameunit(child)); return (EINVAL); } BCM_SPI_LOCK(sc); /* If the controller is in use wait until it is available. */ while (sc->sc_flags & BCM_SPI_BUSY) mtx_sleep(dev, &sc->sc_mtx, 0, "bcm_spi", 0); /* Now we have control over SPI controller. */ sc->sc_flags = BCM_SPI_BUSY; /* Clear the FIFO. */ bcm_spi_modifyreg(sc, SPI_CS, SPI_CS_CLEAR_RXFIFO | SPI_CS_CLEAR_TXFIFO, SPI_CS_CLEAR_RXFIFO | SPI_CS_CLEAR_TXFIFO); /* Save a pointer to the SPI command. */ sc->sc_cmd = cmd; sc->sc_read = 0; sc->sc_written = 0; sc->sc_len = cmd->tx_cmd_sz + cmd->tx_data_sz; /* * Set the CS for this transaction, enable interrupts and announce * we're ready to tx. This will kick off the first interrupt. */ bcm_spi_modifyreg(sc, SPI_CS, SPI_CS_MASK | SPI_CS_TA | SPI_CS_INTR | SPI_CS_INTD, cs | SPI_CS_TA | SPI_CS_INTR | SPI_CS_INTD); /* Wait for the transaction to complete. */ err = mtx_sleep(dev, &sc->sc_mtx, 0, "bcm_spi", hz * 2); /* Make sure the SPI engine and interrupts are disabled. */ bcm_spi_modifyreg(sc, SPI_CS, SPI_CS_TA | SPI_CS_INTR | SPI_CS_INTD, 0); /* Release the controller and wakeup the next thread waiting for it. */ sc->sc_flags = 0; wakeup_one(dev); BCM_SPI_UNLOCK(sc); /* * Check for transfer timeout. The SPI controller doesn't * return errors. */ if (err == EWOULDBLOCK) { device_printf(sc->sc_dev, "SPI error\n"); err = EIO; } return (err); } static phandle_t bcm_spi_get_node(device_t bus, device_t dev) { /* We only have one child, the SPI bus, which needs our own node. */ return (ofw_bus_get_node(bus)); } static device_method_t bcm_spi_methods[] = { /* Device interface */ DEVMETHOD(device_probe, bcm_spi_probe), DEVMETHOD(device_attach, bcm_spi_attach), DEVMETHOD(device_detach, bcm_spi_detach), /* SPI interface */ DEVMETHOD(spibus_transfer, bcm_spi_transfer), /* ofw_bus interface */ DEVMETHOD(ofw_bus_get_node, bcm_spi_get_node), DEVMETHOD_END }; static devclass_t bcm_spi_devclass; static driver_t bcm_spi_driver = { "spi", bcm_spi_methods, sizeof(struct bcm_spi_softc), }; DRIVER_MODULE(bcm2835_spi, simplebus, bcm_spi_driver, bcm_spi_devclass, 0, 0); Index: stable/11/sys/arm/freescale/imx/files.imx5 =================================================================== --- stable/11/sys/arm/freescale/imx/files.imx5 (revision 331505) +++ stable/11/sys/arm/freescale/imx/files.imx5 (revision 331506) @@ -1,54 +1,57 @@ # $FreeBSD$ kern/kern_clocksource.c standard # Init arm/freescale/imx/imx_common.c standard arm/freescale/imx/imx_machdep.c standard arm/freescale/imx/imx51_machdep.c optional soc_imx51 arm/freescale/imx/imx53_machdep.c optional soc_imx53 # Special serial console for debuging early boot code #arm/freescale/imx/console.c standard # UART driver (includes serial console support) dev/uart/uart_dev_imx.c optional uart # TrustZone Interrupt Controller arm/freescale/imx/tzic.c standard # IOMUX - external pins multiplexor arm/freescale/imx/imx_iomux.c standard # GPIO arm/freescale/imx/imx_gpio.c optional gpio # Generic Periodic Timer arm/freescale/imx/imx_gpt.c standard # Clock Configuration Manager arm/freescale/imx/imx51_ccm.c standard # i.MX5xx PATA controller dev/ata/chipsets/ata-fsl.c optional imxata # SDHCI/MMC dev/sdhci/fsl_sdhci.c optional sdhci # USB OH3 controller (1 OTG, 3 EHCI) arm/freescale/imx/imx_nop_usbphy.c optional ehci dev/usb/controller/ehci_imx.c optional ehci # Watchdog arm/freescale/imx/imx_wdog.c optional imxwdt # i2c arm/freescale/imx/imx_i2c.c optional fsliic # IPU - Image Processing Unit (frame buffer also) arm/freescale/imx/imx51_ipuv3.c optional sc arm/freescale/imx/imx51_ipuv3_fbd.c optional vt dev/vt/hw/fb/vt_early_fb.c optional vt # Fast Ethernet Controller dev/ffec/if_ffec.c optional ffec +# SPI +arm/freescale/imx/imx_spi.c optional imx_spi + Index: stable/11/sys/arm/freescale/imx/files.imx6 =================================================================== --- stable/11/sys/arm/freescale/imx/files.imx6 (revision 331505) +++ stable/11/sys/arm/freescale/imx/files.imx6 (revision 331506) @@ -1,73 +1,74 @@ # $FreeBSD$ # # Standard ARM support. # kern/kern_clocksource.c standard # # Standard imx6 devices and support. # arm/freescale/fsl_ocotp.c standard arm/freescale/imx/imx6_anatop.c standard arm/freescale/imx/imx6_ccm.c standard arm/freescale/imx/imx6_machdep.c standard arm/freescale/imx/imx6_mp.c optional smp arm/freescale/imx/imx6_pl310.c standard arm/freescale/imx/imx6_snvs.c optional imx6_snvs arm/freescale/imx/imx6_src.c standard arm/freescale/imx/imx_epit.c standard arm/freescale/imx/imx_iomux.c standard arm/freescale/imx/imx_machdep.c standard arm/freescale/imx/imx_gpt.c optional imx_gpt arm/freescale/imx/imx_gpio.c optional gpio arm/freescale/imx/imx_i2c.c optional fsliic +arm/freescale/imx/imx_spi.c optional imx_spi arm/freescale/imx/imx6_sdma.c optional sdma arm/freescale/imx/imx6_audmux.c optional sound arm/freescale/imx/imx6_ssi.c optional sound arm/freescale/imx/imx6_ahci.c optional ahci arm/arm/hdmi_if.m optional hdmi arm/freescale/imx/imx6_hdmi.c optional hdmi arm/freescale/imx/imx6_ipu.c optional vt # # Optional devices. # dev/sdhci/fsl_sdhci.c optional sdhci arm/freescale/imx/imx_wdog.c optional imxwdt dev/ffec/if_ffec.c optional ffec dev/uart/uart_dev_imx.c optional uart dev/usb/controller/ehci_imx.c optional ehci arm/freescale/imx/imx6_usbphy.c optional ehci # # Low-level serial console for debugging early kernel startup. # #arm/freescale/imx/console.c standard # # Not ready yet... # #arm/freescale/imx/imx51_ipuv3.c optional sc # SDMA firmware sdma_fw.c optional sdma_fw \ compile-with "${AWK} -f $S/tools/fw_stub.awk sdma-imx6q-to1.bin:sdma_fw -msdma -c${.TARGET}" \ no-implicit-rule before-depend local \ clean "sdma_fw.c" sdma-imx6q-to1.fwo optional sdma_fw \ dependency "sdma-imx6q-to1.bin" \ compile-with "${LD} -b binary -d -warn-common -r -d -o ${.TARGET} sdma-imx6q-to1.bin" \ no-implicit-rule \ clean "sdma-imx6q-to1.fwo" sdma-imx6q-to1.bin optional sdma_fw \ dependency "$S/contrib/dev/imx/sdma-imx6q-to1.bin.uu" \ compile-with "uudecode < $S/contrib/dev/imx/sdma-imx6q-to1.bin.uu" \ no-obj no-implicit-rule \ clean "sdma-imx6q-to1.bin" Index: stable/11/sys/arm/freescale/imx/imx51_ccm.c =================================================================== --- stable/11/sys/arm/freescale/imx/imx51_ccm.c (revision 331505) +++ stable/11/sys/arm/freescale/imx/imx51_ccm.c (revision 331506) @@ -1,657 +1,665 @@ /* $NetBSD: imx51_ccm.c,v 1.1 2012/04/17 09:33:31 bsh Exp $ */ /*- * SPDX-License-Identifier: BSD-2-Clause AND BSD-2-Clause-FreeBSD * * Copyright (c) 2010, 2011, 2012 Genetec Corporation. All rights reserved. * Written by Hashimoto Kenichi for Genetec Corporation. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY GENETEC CORPORATION ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL GENETEC CORPORATION * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE * POSSIBILITY OF SUCH DAMAGE. */ /*- * Copyright (c) 2012, 2013 The FreeBSD Foundation * All rights reserved. * * Portions of this software were developed by Oleksandr Rybalko * under sponsorship from the FreeBSD Foundation. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. */ /* * Clock Controller Module (CCM) */ #include __FBSDID("$FreeBSD$"); #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #define IMXCCMDEBUG #undef IMXCCMDEBUG #ifndef IMX51_OSC_FREQ #define IMX51_OSC_FREQ (24 * 1000 * 1000) /* 24MHz */ #endif #ifndef IMX51_CKIL_FREQ #define IMX51_CKIL_FREQ 32768 #endif /* * The fdt data does not provide reg properties describing the DPLL register * blocks we need to access, presumably because the needed addresses are * hard-coded within the linux driver. That leaves us with no choice but to do * the same thing, if we want to run with vendor-supplied fdt data. So here we * have tables of the physical addresses we need for each soc, and we'll use * bus_space_map() at attach() time to get access to them. */ static uint32_t imx51_dpll_addrs[IMX51_N_DPLLS] = { 0x83f80000, /* DPLL1 */ 0x83f84000, /* DPLL2 */ 0x83f88000, /* DPLL3 */ }; static uint32_t imx53_dpll_addrs[IMX51_N_DPLLS] = { 0x63f80000, /* DPLL1 */ 0x63f84000, /* DPLL2 */ 0x63f88000, /* DPLL3 */ }; #define DPLL_REGS_SZ (16 * 1024) struct imxccm_softc { device_t sc_dev; struct resource *ccmregs; u_int64_t pll_freq[IMX51_N_DPLLS]; bus_space_tag_t pllbst; bus_space_handle_t pllbsh[IMX51_N_DPLLS]; }; struct imxccm_softc *ccm_softc = NULL; static uint64_t imx51_get_pll_freq(u_int); static int imxccm_match(device_t); static int imxccm_attach(device_t); static device_method_t imxccm_methods[] = { DEVMETHOD(device_probe, imxccm_match), DEVMETHOD(device_attach, imxccm_attach), DEVMETHOD_END }; static driver_t imxccm_driver = { "imxccm", imxccm_methods, sizeof(struct imxccm_softc), }; static devclass_t imxccm_devclass; EARLY_DRIVER_MODULE(imxccm, simplebus, imxccm_driver, imxccm_devclass, 0, 0, BUS_PASS_CPU); static inline uint32_t pll_read_4(struct imxccm_softc *sc, int pll, int reg) { return (bus_space_read_4(sc->pllbst, sc->pllbsh[pll - 1], reg)); } static inline uint32_t ccm_read_4(struct imxccm_softc *sc, int reg) { return (bus_read_4(sc->ccmregs, reg)); } static inline void ccm_write_4(struct imxccm_softc *sc, int reg, uint32_t val) { bus_write_4(sc->ccmregs, reg, val); } static int imxccm_match(device_t dev) { if (!ofw_bus_status_okay(dev)) return (ENXIO); if (!ofw_bus_is_compatible(dev, "fsl,imx51-ccm") && !ofw_bus_is_compatible(dev, "fsl,imx53-ccm")) return (ENXIO); device_set_desc(dev, "Freescale Clock Control Module"); return (BUS_PROBE_DEFAULT); } static int imxccm_attach(device_t dev) { struct imxccm_softc *sc; int idx; u_int soc; uint32_t *pll_addrs; sc = device_get_softc(dev); sc->sc_dev = dev; switch ((soc = imx_soc_type())) { case IMXSOC_51: pll_addrs = imx51_dpll_addrs; break; case IMXSOC_53: pll_addrs = imx53_dpll_addrs; break; default: device_printf(dev, "No support for SoC type 0x%08x\n", soc); goto noclocks; } idx = 0; sc->ccmregs = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &idx, RF_ACTIVE); if (sc->ccmregs == NULL) { device_printf(dev, "could not allocate resources\n"); goto noclocks; } sc->pllbst = fdtbus_bs_tag; for (idx = 0; idx < IMX51_N_DPLLS; ++idx) { if (bus_space_map(sc->pllbst, pll_addrs[idx], DPLL_REGS_SZ, 0, &sc->pllbsh[idx]) != 0) { device_printf(dev, "Cannot map DPLL registers\n"); goto noclocks; } } ccm_softc = sc; imx51_get_pll_freq(1); imx51_get_pll_freq(2); imx51_get_pll_freq(3); device_printf(dev, "PLL1=%lluMHz, PLL2=%lluMHz, PLL3=%lluMHz\n", sc->pll_freq[0] / 1000000, sc->pll_freq[1] / 1000000, sc->pll_freq[2] / 1000000); device_printf(dev, "CPU clock=%d, UART clock=%d\n", imx51_get_clock(IMX51CLK_ARM_ROOT), imx51_get_clock(IMX51CLK_UART_CLK_ROOT)); device_printf(dev, "mainbus clock=%d, ahb clock=%d ipg clock=%d perclk=%d\n", imx51_get_clock(IMX51CLK_MAIN_BUS_CLK), imx51_get_clock(IMX51CLK_AHB_CLK_ROOT), imx51_get_clock(IMX51CLK_IPG_CLK_ROOT), imx51_get_clock(IMX51CLK_PERCLK_ROOT)); return (0); noclocks: panic("Cannot continue without clock support"); } u_int imx51_get_clock(enum imx51_clock clk) { u_int freq; u_int sel; uint32_t cacrr; /* ARM clock root register */ uint32_t ccsr; uint32_t cscdr1; uint32_t cscmr1; uint32_t cbcdr; uint32_t cbcmr; uint32_t cdcr; if (ccm_softc == NULL) return (0); switch (clk) { case IMX51CLK_PLL1: case IMX51CLK_PLL2: case IMX51CLK_PLL3: return ccm_softc->pll_freq[clk-IMX51CLK_PLL1]; case IMX51CLK_PLL1SW: ccsr = ccm_read_4(ccm_softc, CCMC_CCSR); if ((ccsr & CCSR_PLL1_SW_CLK_SEL) == 0) return ccm_softc->pll_freq[1-1]; /* step clock */ /* FALLTHROUGH */ case IMX51CLK_PLL1STEP: ccsr = ccm_read_4(ccm_softc, CCMC_CCSR); switch ((ccsr & CCSR_STEP_SEL_MASK) >> CCSR_STEP_SEL_SHIFT) { case 0: return imx51_get_clock(IMX51CLK_LP_APM); case 1: return 0; /* XXX PLL bypass clock */ case 2: return ccm_softc->pll_freq[2-1] / (1 + ((ccsr & CCSR_PLL2_DIV_PODF_MASK) >> CCSR_PLL2_DIV_PODF_SHIFT)); case 3: return ccm_softc->pll_freq[3-1] / (1 + ((ccsr & CCSR_PLL3_DIV_PODF_MASK) >> CCSR_PLL3_DIV_PODF_SHIFT)); } /*NOTREACHED*/ case IMX51CLK_PLL2SW: ccsr = ccm_read_4(ccm_softc, CCMC_CCSR); if ((ccsr & CCSR_PLL2_SW_CLK_SEL) == 0) return imx51_get_clock(IMX51CLK_PLL2); return 0; /* XXX PLL2 bypass clk */ case IMX51CLK_PLL3SW: ccsr = ccm_read_4(ccm_softc, CCMC_CCSR); if ((ccsr & CCSR_PLL3_SW_CLK_SEL) == 0) return imx51_get_clock(IMX51CLK_PLL3); return 0; /* XXX PLL3 bypass clk */ case IMX51CLK_LP_APM: ccsr = ccm_read_4(ccm_softc, CCMC_CCSR); return (ccsr & CCSR_LP_APM) ? imx51_get_clock(IMX51CLK_FPM) : IMX51_OSC_FREQ; case IMX51CLK_ARM_ROOT: freq = imx51_get_clock(IMX51CLK_PLL1SW); cacrr = ccm_read_4(ccm_softc, CCMC_CACRR); return freq / (cacrr + 1); /* ... */ case IMX51CLK_MAIN_BUS_CLK_SRC: cbcdr = ccm_read_4(ccm_softc, CCMC_CBCDR); if ((cbcdr & CBCDR_PERIPH_CLK_SEL) == 0) freq = imx51_get_clock(IMX51CLK_PLL2SW); else { freq = 0; cbcmr = ccm_read_4(ccm_softc, CCMC_CBCMR); switch ((cbcmr & CBCMR_PERIPH_APM_SEL_MASK) >> CBCMR_PERIPH_APM_SEL_SHIFT) { case 0: freq = imx51_get_clock(IMX51CLK_PLL1SW); break; case 1: freq = imx51_get_clock(IMX51CLK_PLL3SW); break; case 2: freq = imx51_get_clock(IMX51CLK_LP_APM); break; case 3: /* XXX: error */ break; } } return freq; case IMX51CLK_MAIN_BUS_CLK: freq = imx51_get_clock(IMX51CLK_MAIN_BUS_CLK_SRC); cdcr = ccm_read_4(ccm_softc, CCMC_CDCR); return freq / (1 + ((cdcr & CDCR_PERIPH_CLK_DVFS_PODF_MASK) >> CDCR_PERIPH_CLK_DVFS_PODF_SHIFT)); case IMX51CLK_AHB_CLK_ROOT: freq = imx51_get_clock(IMX51CLK_MAIN_BUS_CLK); cbcdr = ccm_read_4(ccm_softc, CCMC_CBCDR); return freq / (1 + ((cbcdr & CBCDR_AHB_PODF_MASK) >> CBCDR_AHB_PODF_SHIFT)); case IMX51CLK_IPG_CLK_ROOT: freq = imx51_get_clock(IMX51CLK_AHB_CLK_ROOT); cbcdr = ccm_read_4(ccm_softc, CCMC_CBCDR); return freq / (1 + ((cbcdr & CBCDR_IPG_PODF_MASK) >> CBCDR_IPG_PODF_SHIFT)); case IMX51CLK_PERCLK_ROOT: cbcmr = ccm_read_4(ccm_softc, CCMC_CBCMR); if (cbcmr & CBCMR_PERCLK_IPG_SEL) return imx51_get_clock(IMX51CLK_IPG_CLK_ROOT); if (cbcmr & CBCMR_PERCLK_LP_APM_SEL) freq = imx51_get_clock(IMX51CLK_LP_APM); else freq = imx51_get_clock(IMX51CLK_MAIN_BUS_CLK_SRC); cbcdr = ccm_read_4(ccm_softc, CCMC_CBCDR); #ifdef IMXCCMDEBUG printf("cbcmr=%x cbcdr=%x\n", cbcmr, cbcdr); #endif freq /= 1 + ((cbcdr & CBCDR_PERCLK_PRED1_MASK) >> CBCDR_PERCLK_PRED1_SHIFT); freq /= 1 + ((cbcdr & CBCDR_PERCLK_PRED2_MASK) >> CBCDR_PERCLK_PRED2_SHIFT); freq /= 1 + ((cbcdr & CBCDR_PERCLK_PODF_MASK) >> CBCDR_PERCLK_PODF_SHIFT); return freq; case IMX51CLK_UART_CLK_ROOT: cscdr1 = ccm_read_4(ccm_softc, CCMC_CSCDR1); cscmr1 = ccm_read_4(ccm_softc, CCMC_CSCMR1); #ifdef IMXCCMDEBUG printf("cscdr1=%x cscmr1=%x\n", cscdr1, cscmr1); #endif sel = (cscmr1 & CSCMR1_UART_CLK_SEL_MASK) >> CSCMR1_UART_CLK_SEL_SHIFT; freq = 0; /* shut up GCC */ switch (sel) { case 0: case 1: case 2: freq = imx51_get_clock(IMX51CLK_PLL1SW + sel); break; case 3: freq = imx51_get_clock(IMX51CLK_LP_APM); break; } return freq / (1 + ((cscdr1 & CSCDR1_UART_CLK_PRED_MASK) >> CSCDR1_UART_CLK_PRED_SHIFT)) / (1 + ((cscdr1 & CSCDR1_UART_CLK_PODF_MASK) >> CSCDR1_UART_CLK_PODF_SHIFT)); case IMX51CLK_IPU_HSP_CLK_ROOT: freq = 0; cbcmr = ccm_read_4(ccm_softc, CCMC_CBCMR); switch ((cbcmr & CBCMR_IPU_HSP_CLK_SEL_MASK) >> CBCMR_IPU_HSP_CLK_SEL_SHIFT) { case 0: freq = imx51_get_clock(IMX51CLK_ARM_AXI_A_CLK); break; case 1: freq = imx51_get_clock(IMX51CLK_ARM_AXI_B_CLK); break; case 2: freq = imx51_get_clock( IMX51CLK_EMI_SLOW_CLK_ROOT); break; case 3: freq = imx51_get_clock(IMX51CLK_AHB_CLK_ROOT); break; } return freq; default: device_printf(ccm_softc->sc_dev, "clock %d: not supported yet\n", clk); return 0; } } static uint64_t imx51_get_pll_freq(u_int pll_no) { uint32_t dp_ctrl; uint32_t dp_op; uint32_t dp_mfd; uint32_t dp_mfn; uint32_t mfi; int32_t mfn; uint32_t mfd; uint32_t pdf; uint32_t ccr; uint64_t freq = 0; u_int ref = 0; KASSERT(1 <= pll_no && pll_no <= IMX51_N_DPLLS, ("Wrong PLL id")); dp_ctrl = pll_read_4(ccm_softc, pll_no, DPLL_DP_CTL); if (dp_ctrl & DP_CTL_HFSM) { dp_op = pll_read_4(ccm_softc, pll_no, DPLL_DP_HFS_OP); dp_mfd = pll_read_4(ccm_softc, pll_no, DPLL_DP_HFS_MFD); dp_mfn = pll_read_4(ccm_softc, pll_no, DPLL_DP_HFS_MFN); } else { dp_op = pll_read_4(ccm_softc, pll_no, DPLL_DP_OP); dp_mfd = pll_read_4(ccm_softc, pll_no, DPLL_DP_MFD); dp_mfn = pll_read_4(ccm_softc, pll_no, DPLL_DP_MFN); } pdf = dp_op & DP_OP_PDF_MASK; mfi = max(5, (dp_op & DP_OP_MFI_MASK) >> DP_OP_MFI_SHIFT); mfd = dp_mfd; if (dp_mfn & 0x04000000) /* 27bit signed value */ mfn = (uint32_t)(0xf8000000 | dp_mfn); else mfn = dp_mfn; switch (dp_ctrl & DP_CTL_REF_CLK_SEL_MASK) { case DP_CTL_REF_CLK_SEL_COSC: /* Internal Oscillator */ /* TODO: get from FDT "fsl,imx-osc" */ ref = 24000000; /* IMX51_OSC_FREQ */ break; case DP_CTL_REF_CLK_SEL_FPM: ccr = ccm_read_4(ccm_softc, CCMC_CCR); if (ccr & CCR_FPM_MULT) /* TODO: get from FDT "fsl,imx-ckil" */ ref = 32768 * 1024; else /* TODO: get from FDT "fsl,imx-ckil" */ ref = 32768 * 512; break; default: ref = 0; } if (dp_ctrl & DP_CTL_REF_CLK_DIV) ref /= 2; ref *= 4; freq = (int64_t)ref * mfi + (int64_t)ref * mfn / (mfd + 1); freq /= pdf + 1; if (!(dp_ctrl & DP_CTL_DPDCK0_2_EN)) freq /= 2; #ifdef IMXCCMDEBUG printf("ref: %dKHz ", ref); printf("dp_ctl: %08x ", dp_ctrl); printf("pdf: %3d ", pdf); printf("mfi: %3d ", mfi); printf("mfd: %3d ", mfd); printf("mfn: %3d ", mfn); printf("pll: %d\n", (uint32_t)freq); #endif ccm_softc->pll_freq[pll_no-1] = freq; return (freq); } void imx51_clk_gating(int clk_src, int mode) { int field, group; uint32_t reg; group = CCMR_CCGR_MODULE(clk_src); field = clk_src % CCMR_CCGR_NSOURCE; reg = ccm_read_4(ccm_softc, CCMC_CCGR(group)); reg &= ~(0x03 << field * 2); reg |= (mode << field * 2); ccm_write_4(ccm_softc, CCMC_CCGR(group), reg); } int imx51_get_clk_gating(int clk_src) { uint32_t reg; reg = ccm_read_4(ccm_softc, CCMC_CCGR(CCMR_CCGR_MODULE(clk_src))); return ((reg >> (clk_src % CCMR_CCGR_NSOURCE) * 2) & 0x03); } /* * Code from here down is temporary, in lieu of a SoC-independent clock API. */ void imx_ccm_usb_enable(device_t dev) { uint32_t regval; /* * Select PLL2 as the source for the USB clock. * The default is PLL3, but U-boot changes it to PLL2. */ regval = ccm_read_4(ccm_softc, CCMC_CSCMR1); regval &= ~CSCMR1_USBOH3_CLK_SEL_MASK; regval |= 1 << CSCMR1_USBOH3_CLK_SEL_SHIFT; ccm_write_4(ccm_softc, CCMC_CSCMR1, regval); /* * Set the USB clock pre-divider to div-by-5, post-divider to div-by-2. */ regval = ccm_read_4(ccm_softc, CCMC_CSCDR1); regval &= ~CSCDR1_USBOH3_CLK_PODF_MASK; regval &= ~CSCDR1_USBOH3_CLK_PRED_MASK; regval |= 4 << CSCDR1_USBOH3_CLK_PRED_SHIFT; regval |= 1 << CSCDR1_USBOH3_CLK_PODF_SHIFT; ccm_write_4(ccm_softc, CCMC_CSCDR1, regval); /* * The same two clocks gates are used on imx51 and imx53. */ imx51_clk_gating(CCGR_USBOH3_IPG_AHB_CLK, CCGR_CLK_MODE_ALWAYS); imx51_clk_gating(CCGR_USBOH3_60M_CLK, CCGR_CLK_MODE_ALWAYS); } void imx_ccm_usbphy_enable(device_t dev) { uint32_t regval; /* * Select PLL3 as the source for the USBPHY clock. U-boot does this * only for imx53, but the bit exists on imx51. That seems a bit * strange, but we'll go with it until more is known. */ if (imx_soc_type() == IMXSOC_53) { regval = ccm_read_4(ccm_softc, CCMC_CSCMR1); regval |= 1 << CSCMR1_USBPHY_CLK_SEL_SHIFT; ccm_write_4(ccm_softc, CCMC_CSCMR1, regval); } /* * For the imx51 there's just one phy gate control, enable it. */ if (imx_soc_type() == IMXSOC_51) { imx51_clk_gating(CCGR_USB_PHY_CLK, CCGR_CLK_MODE_ALWAYS); return; } /* * For imx53 we don't have a full set of clock defines yet, but the * datasheet says: * gate reg 4, bits 13-12 usb ph2 clock (usb_phy2_clk_enable) * gate reg 4, bits 11-10 usb ph1 clock (usb_phy1_clk_enable) * * We should use the fdt data for the device to figure out which of * the two we're working on, but for now just turn them both on. */ if (imx_soc_type() == IMXSOC_53) { imx51_clk_gating(__CCGR_NUM(4, 5), CCGR_CLK_MODE_ALWAYS); imx51_clk_gating(__CCGR_NUM(4, 6), CCGR_CLK_MODE_ALWAYS); return; } } uint32_t +imx_ccm_ecspi_hz(void) +{ + + return (imx51_get_clock(IMX51CLK_CSPI_CLK_ROOT)); +} + +uint32_t imx_ccm_ipg_hz(void) { return (imx51_get_clock(IMX51CLK_IPG_CLK_ROOT)); } uint32_t imx_ccm_sdhci_hz(void) { return (imx51_get_clock(IMX51CLK_ESDHC1_CLK_ROOT)); } uint32_t imx_ccm_perclk_hz(void) { return (imx51_get_clock(IMX51CLK_PERCLK_ROOT)); } uint32_t imx_ccm_uart_hz(void) { return (imx51_get_clock(IMX51CLK_UART_CLK_ROOT)); } uint32_t imx_ccm_ahb_hz(void) { return (imx51_get_clock(IMX51CLK_AHB_CLK_ROOT)); } + Index: stable/11/sys/arm/freescale/imx/imx6_ccm.c =================================================================== --- stable/11/sys/arm/freescale/imx/imx6_ccm.c (revision 331505) +++ stable/11/sys/arm/freescale/imx/imx6_ccm.c (revision 331506) @@ -1,458 +1,466 @@ /*- * SPDX-License-Identifier: BSD-2-Clause-FreeBSD * * Copyright (c) 2013 Ian Lepore * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. */ #include __FBSDID("$FreeBSD$"); /* * Clocks and power control driver for Freescale i.MX6 family of SoCs. */ #include #include #include #include #include #include #include #include #include #include #include #include #include #include #ifndef CCGR_CLK_MODE_ALWAYS #define CCGR_CLK_MODE_OFF 0 #define CCGR_CLK_MODE_RUNMODE 1 #define CCGR_CLK_MODE_ALWAYS 3 #endif struct ccm_softc { device_t dev; struct resource *mem_res; }; static struct ccm_softc *ccm_sc; static inline uint32_t RD4(struct ccm_softc *sc, bus_size_t off) { return (bus_read_4(sc->mem_res, off)); } static inline void WR4(struct ccm_softc *sc, bus_size_t off, uint32_t val) { bus_write_4(sc->mem_res, off, val); } /* * Until we have a fully functional ccm driver which implements the fdt_clock * interface, use the age-old workaround of unconditionally enabling the clocks * for devices we might need to use. The SoC defaults to most clocks enabled, * but the rom boot code and u-boot disable a few of them. We turn on only * what's needed to run the chip plus devices we have drivers for, and turn off * devices we don't yet have drivers for. (Note that USB is not turned on here * because that is one we do when the driver asks for it.) */ static void ccm_init_gates(struct ccm_softc *sc) { uint32_t reg; /* ahpbdma, aipstz 1 & 2 busses */ reg = CCGR0_AIPS_TZ1 | CCGR0_AIPS_TZ2 | CCGR0_ABPHDMA; WR4(sc, CCM_CCGR0, reg); - /* enet, epit, gpt */ - reg = CCGR1_ENET | CCGR1_EPIT1 | CCGR1_GPT; + /* enet, epit, gpt, spi */ + reg = CCGR1_ENET | CCGR1_EPIT1 | CCGR1_GPT | CCGR1_ECSPI1 | + CCGR1_ECSPI2 | CCGR1_ECSPI3 | CCGR1_ECSPI4 | CCGR1_ECSPI5; WR4(sc, CCM_CCGR1, reg); /* ipmux & ipsync (bridges), iomux, i2c */ reg = CCGR2_I2C1 | CCGR2_I2C2 | CCGR2_I2C3 | CCGR2_IIM | CCGR2_IOMUX_IPT | CCGR2_IPMUX1 | CCGR2_IPMUX2 | CCGR2_IPMUX3 | CCGR2_IPSYNC_IP2APB_TZASC1 | CCGR2_IPSYNC_IP2APB_TZASC2 | CCGR2_IPSYNC_VDOA; WR4(sc, CCM_CCGR2, reg); /* DDR memory controller */ reg = CCGR3_OCRAM | CCGR3_MMDC_CORE_IPG | CCGR3_MMDC_CORE_ACLK_FAST | CCGR3_CG11 | CCGR3_CG13; WR4(sc, CCM_CCGR3, reg); /* pl301 bus crossbar */ reg = CCGR4_PL301_MX6QFAST1_S133 | CCGR4_PL301_MX6QPER1_BCH | CCGR4_PL301_MX6QPER2_MAIN; WR4(sc, CCM_CCGR4, reg); /* uarts, ssi, sdma */ reg = CCGR5_SDMA | CCGR5_SSI1 | CCGR5_SSI2 | CCGR5_SSI3 | CCGR5_UART | CCGR5_UART_SERIAL; WR4(sc, CCM_CCGR5, reg); /* usdhc 1-4, usboh3 */ reg = CCGR6_USBOH3 | CCGR6_USDHC1 | CCGR6_USDHC2 | CCGR6_USDHC3 | CCGR6_USDHC4; WR4(sc, CCM_CCGR6, reg); } static int ccm_detach(device_t dev) { struct ccm_softc *sc; sc = device_get_softc(dev); if (sc->mem_res != NULL) bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->mem_res); return (0); } static int ccm_attach(device_t dev) { struct ccm_softc *sc; int err, rid; uint32_t reg; sc = device_get_softc(dev); err = 0; /* Allocate bus_space resources. */ rid = 0; sc->mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, RF_ACTIVE); if (sc->mem_res == NULL) { device_printf(dev, "Cannot allocate memory resources\n"); err = ENXIO; goto out; } ccm_sc = sc; /* * Configure the Low Power Mode setting to leave the ARM core power on * when a WFI instruction is executed. This lets the MPCore timers and * GIC continue to run, which is helpful when the only thing that can * wake you up is an MPCore Private Timer interrupt delivered via GIC. * * XXX Based on the docs, setting CCM_CGPR_INT_MEM_CLK_LPM shouldn't be * required when the LPM bits are set to LPM_RUN. But experimentally * I've experienced a fairly rare lockup when not setting it. I was * unable to prove conclusively that the lockup was related to power * management or that this definitively fixes it. Revisit this. */ reg = RD4(sc, CCM_CGPR); reg |= CCM_CGPR_INT_MEM_CLK_LPM; WR4(sc, CCM_CGPR, reg); reg = RD4(sc, CCM_CLPCR); reg = (reg & ~CCM_CLPCR_LPM_MASK) | CCM_CLPCR_LPM_RUN; WR4(sc, CCM_CLPCR, reg); ccm_init_gates(sc); err = 0; out: if (err != 0) ccm_detach(dev); return (err); } static int ccm_probe(device_t dev) { if (!ofw_bus_status_okay(dev)) return (ENXIO); if (ofw_bus_is_compatible(dev, "fsl,imx6q-ccm") == 0) return (ENXIO); device_set_desc(dev, "Freescale i.MX6 Clock Control Module"); return (BUS_PROBE_DEFAULT); } void imx_ccm_ssi_configure(device_t _ssidev) { struct ccm_softc *sc; uint32_t reg; sc = ccm_sc; /* * Select PLL4 (Audio PLL) clock multiplexer as source. * PLL output frequency = Fref * (DIV_SELECT + NUM/DENOM). */ reg = RD4(sc, CCM_CSCMR1); reg &= ~(SSI_CLK_SEL_M << SSI1_CLK_SEL_S); reg |= (SSI_CLK_SEL_PLL4 << SSI1_CLK_SEL_S); reg &= ~(SSI_CLK_SEL_M << SSI2_CLK_SEL_S); reg |= (SSI_CLK_SEL_PLL4 << SSI2_CLK_SEL_S); reg &= ~(SSI_CLK_SEL_M << SSI3_CLK_SEL_S); reg |= (SSI_CLK_SEL_PLL4 << SSI3_CLK_SEL_S); WR4(sc, CCM_CSCMR1, reg); /* * Ensure we have set hardware-default values * for pre and post dividers. */ /* SSI1 and SSI3 */ reg = RD4(sc, CCM_CS1CDR); /* Divide by 2 */ reg &= ~(SSI_CLK_PODF_MASK << SSI1_CLK_PODF_SHIFT); reg &= ~(SSI_CLK_PODF_MASK << SSI3_CLK_PODF_SHIFT); reg |= (0x1 << SSI1_CLK_PODF_SHIFT); reg |= (0x1 << SSI3_CLK_PODF_SHIFT); /* Divide by 4 */ reg &= ~(SSI_CLK_PRED_MASK << SSI1_CLK_PRED_SHIFT); reg &= ~(SSI_CLK_PRED_MASK << SSI3_CLK_PRED_SHIFT); reg |= (0x3 << SSI1_CLK_PRED_SHIFT); reg |= (0x3 << SSI3_CLK_PRED_SHIFT); WR4(sc, CCM_CS1CDR, reg); /* SSI2 */ reg = RD4(sc, CCM_CS2CDR); /* Divide by 2 */ reg &= ~(SSI_CLK_PODF_MASK << SSI2_CLK_PODF_SHIFT); reg |= (0x1 << SSI2_CLK_PODF_SHIFT); /* Divide by 4 */ reg &= ~(SSI_CLK_PRED_MASK << SSI2_CLK_PRED_SHIFT); reg |= (0x3 << SSI2_CLK_PRED_SHIFT); WR4(sc, CCM_CS2CDR, reg); } void imx_ccm_usb_enable(device_t _usbdev) { /* * For imx6, the USBOH3 clock gate is bits 0-1 of CCGR6, so no need for * shifting and masking here, just set the low-order two bits to ALWAYS. */ WR4(ccm_sc, CCM_CCGR6, RD4(ccm_sc, CCM_CCGR6) | CCGR_CLK_MODE_ALWAYS); } void imx_ccm_usbphy_enable(device_t _phydev) { /* * XXX Which unit? * Right now it's not clear how to figure from fdt data which phy unit * we're supposed to operate on. Until this is worked out, just enable * both PHYs. */ #if 0 int phy_num, regoff; phy_num = 0; /* XXX */ switch (phy_num) { case 0: regoff = 0; break; case 1: regoff = 0x10; break; default: device_printf(ccm_sc->dev, "Bad PHY number %u,\n", phy_num); return; } imx6_anatop_write_4(IMX6_ANALOG_CCM_PLL_USB1 + regoff, IMX6_ANALOG_CCM_PLL_USB_ENABLE | IMX6_ANALOG_CCM_PLL_USB_POWER | IMX6_ANALOG_CCM_PLL_USB_EN_USB_CLKS); #else imx6_anatop_write_4(IMX6_ANALOG_CCM_PLL_USB1 + 0, IMX6_ANALOG_CCM_PLL_USB_ENABLE | IMX6_ANALOG_CCM_PLL_USB_POWER | IMX6_ANALOG_CCM_PLL_USB_EN_USB_CLKS); imx6_anatop_write_4(IMX6_ANALOG_CCM_PLL_USB1 + 0x10, IMX6_ANALOG_CCM_PLL_USB_ENABLE | IMX6_ANALOG_CCM_PLL_USB_POWER | IMX6_ANALOG_CCM_PLL_USB_EN_USB_CLKS); #endif } int imx6_ccm_sata_enable(void) { uint32_t v; int timeout; /* Un-gate the sata controller. */ WR4(ccm_sc, CCM_CCGR5, RD4(ccm_sc, CCM_CCGR5) | CCGR5_SATA); /* Power up the PLL that feeds ENET/SATA/PCI phys, wait for lock. */ v = RD4(ccm_sc, CCM_ANALOG_PLL_ENET); v &= ~CCM_ANALOG_PLL_ENET_POWERDOWN; WR4(ccm_sc, CCM_ANALOG_PLL_ENET, v); for (timeout = 100000; timeout > 0; timeout--) { if (RD4(ccm_sc, CCM_ANALOG_PLL_ENET) & CCM_ANALOG_PLL_ENET_LOCK) { break; } } if (timeout <= 0) { return ETIMEDOUT; } /* Enable the PLL, and enable its 100mhz output. */ v |= CCM_ANALOG_PLL_ENET_ENABLE; v &= ~CCM_ANALOG_PLL_ENET_BYPASS; WR4(ccm_sc, CCM_ANALOG_PLL_ENET, v); v |= CCM_ANALOG_PLL_ENET_ENABLE_100M; WR4(ccm_sc, CCM_ANALOG_PLL_ENET, v); return 0; +} + +uint32_t +imx_ccm_ecspi_hz(void) +{ + + return (60000000); } uint32_t imx_ccm_ipg_hz(void) { return (66000000); } uint32_t imx_ccm_perclk_hz(void) { return (66000000); } uint32_t imx_ccm_sdhci_hz(void) { return (200000000); } uint32_t imx_ccm_uart_hz(void) { return (80000000); } uint32_t imx_ccm_ahb_hz(void) { return (132000000); } void imx_ccm_ipu_enable(int ipu) { struct ccm_softc *sc; uint32_t reg; sc = ccm_sc; reg = RD4(sc, CCM_CCGR3); if (ipu == 1) reg |= CCGR3_IPU1_IPU | CCGR3_IPU1_DI0; else reg |= CCGR3_IPU2_IPU | CCGR3_IPU2_DI0; WR4(sc, CCM_CCGR3, reg); } void imx_ccm_hdmi_enable(void) { struct ccm_softc *sc; uint32_t reg; sc = ccm_sc; reg = RD4(sc, CCM_CCGR2); reg |= CCGR2_HDMI_TX | CCGR2_HDMI_TX_ISFR; WR4(sc, CCM_CCGR2, reg); /* Set HDMI clock to 280MHz */ reg = RD4(sc, CCM_CHSCCDR); reg &= ~(CHSCCDR_IPU1_DI0_PRE_CLK_SEL_MASK | CHSCCDR_IPU1_DI0_PODF_MASK | CHSCCDR_IPU1_DI0_CLK_SEL_MASK); reg |= (CHSCCDR_PODF_DIVIDE_BY_3 << CHSCCDR_IPU1_DI0_PODF_SHIFT); reg |= (CHSCCDR_IPU_PRE_CLK_540M_PFD << CHSCCDR_IPU1_DI0_PRE_CLK_SEL_SHIFT); WR4(sc, CCM_CHSCCDR, reg); reg |= (CHSCCDR_CLK_SEL_LDB_DI0 << CHSCCDR_IPU1_DI0_CLK_SEL_SHIFT); WR4(sc, CCM_CHSCCDR, reg); } uint32_t imx_ccm_get_cacrr(void) { return (RD4(ccm_sc, CCM_CACCR)); } void imx_ccm_set_cacrr(uint32_t divisor) { WR4(ccm_sc, CCM_CACCR, divisor); } static device_method_t ccm_methods[] = { /* Device interface */ DEVMETHOD(device_probe, ccm_probe), DEVMETHOD(device_attach, ccm_attach), DEVMETHOD(device_detach, ccm_detach), DEVMETHOD_END }; static driver_t ccm_driver = { "ccm", ccm_methods, sizeof(struct ccm_softc) }; static devclass_t ccm_devclass; EARLY_DRIVER_MODULE(ccm, simplebus, ccm_driver, ccm_devclass, 0, 0, BUS_PASS_CPU + BUS_PASS_ORDER_EARLY); Index: stable/11/sys/arm/freescale/imx/imx6_ccmreg.h =================================================================== --- stable/11/sys/arm/freescale/imx/imx6_ccmreg.h (revision 331505) +++ stable/11/sys/arm/freescale/imx/imx6_ccmreg.h (revision 331506) @@ -1,143 +1,149 @@ /*- * SPDX-License-Identifier: BSD-2-Clause-FreeBSD * * Copyright (c) 2013 Ian Lepore * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. * * $FreeBSD$ */ #ifndef IMX6_CCMREG_H #define IMX6_CCMREG_H #define CCM_CACCR 0x010 #define CCM_CBCDR 0x014 #define CBCDR_MMDC_CH1_AXI_PODF_SHIFT 3 #define CBCDR_MMDC_CH1_AXI_PODF_MASK (7 << 3) #define CCM_CSCMR1 0x01C #define SSI1_CLK_SEL_S 10 #define SSI2_CLK_SEL_S 12 #define SSI3_CLK_SEL_S 14 #define SSI_CLK_SEL_M 0x3 #define SSI_CLK_SEL_508_PFD 0 #define SSI_CLK_SEL_454_PFD 1 #define SSI_CLK_SEL_PLL4 2 #define CCM_CSCMR2 0x020 #define CSCMR2_LDB_DI0_IPU_DIV_SHIFT 10 #define CCM_CS1CDR 0x028 #define SSI1_CLK_PODF_SHIFT 0 #define SSI1_CLK_PRED_SHIFT 6 #define SSI3_CLK_PODF_SHIFT 16 #define SSI3_CLK_PRED_SHIFT 22 #define SSI_CLK_PODF_MASK 0x3f #define SSI_CLK_PRED_MASK 0x7 #define CCM_CS2CDR 0x02C #define SSI2_CLK_PODF_SHIFT 0 #define SSI2_CLK_PRED_SHIFT 6 #define LDB_DI0_CLK_SEL_SHIFT 9 #define LDB_DI0_CLK_SEL_MASK (3 << LDB_DI0_CLK_SEL_SHIFT) #define CCM_CHSCCDR 0x034 #define CHSCCDR_IPU1_DI0_PRE_CLK_SEL_MASK (0x7 << 6) #define CHSCCDR_IPU1_DI0_PRE_CLK_SEL_SHIFT 6 #define CHSCCDR_IPU1_DI0_PODF_MASK (0x7 << 3) #define CHSCCDR_IPU1_DI0_PODF_SHIFT 3 #define CHSCCDR_IPU1_DI0_CLK_SEL_MASK (0x7) #define CHSCCDR_IPU1_DI0_CLK_SEL_SHIFT 0 #define CHSCCDR_CLK_SEL_LDB_DI0 3 #define CHSCCDR_PODF_DIVIDE_BY_3 2 #define CHSCCDR_IPU_PRE_CLK_540M_PFD 5 #define CCM_CSCDR2 0x038 #define CCM_CLPCR 0x054 #define CCM_CLPCR_LPM_MASK 0x03 #define CCM_CLPCR_LPM_RUN 0x00 #define CCM_CLPCR_LPM_WAIT 0x01 #define CCM_CLPCR_LPM_STOP 0x02 #define CCM_CGPR 0x064 #define CCM_CGPR_INT_MEM_CLK_LPM (1 << 17) #define CCM_CCGR0 0x068 #define CCGR0_AIPS_TZ1 (0x3 << 0) #define CCGR0_AIPS_TZ2 (0x3 << 2) #define CCGR0_ABPHDMA (0x3 << 4) #define CCM_CCGR1 0x06C +#define CCGR1_ECSPI1 (0x3 << 0) +#define CCGR1_ECSPI2 (0x3 << 2) +#define CCGR1_ECSPI3 (0x3 << 4) +#define CCGR1_ECSPI4 (0x3 << 6) +#define CCGR1_ECSPI5 (0x3 << 8) #define CCGR1_ENET (0x3 << 10) #define CCGR1_EPIT1 (0x3 << 12) #define CCGR1_EPIT2 (0x3 << 14) +#define CCGR1_ESAI (0x3 << 16) #define CCGR1_GPT (0x3 << 20) #define CCGR1_GPT_SERIAL (0x3 << 22) #define CCM_CCGR2 0x070 #define CCGR2_HDMI_TX (0x3 << 0) #define CCGR2_HDMI_TX_ISFR (0x3 << 4) #define CCGR2_I2C1 (0x3 << 6) #define CCGR2_I2C2 (0x3 << 8) #define CCGR2_I2C3 (0x3 << 10) #define CCGR2_IIM (0x3 << 12) #define CCGR2_IOMUX_IPT (0x3 << 14) #define CCGR2_IPMUX1 (0x3 << 16) #define CCGR2_IPMUX2 (0x3 << 18) #define CCGR2_IPMUX3 (0x3 << 20) #define CCGR2_IPSYNC_IP2APB_TZASC1 (0x3 << 22) #define CCGR2_IPSYNC_IP2APB_TZASC2 (0x3 << 24) #define CCGR2_IPSYNC_VDOA (0x3 << 26) #define CCM_CCGR3 0x074 #define CCGR3_IPU1_IPU (0x3 << 0) #define CCGR3_IPU1_DI0 (0x3 << 2) #define CCGR3_IPU1_DI1 (0x3 << 4) #define CCGR3_IPU2_IPU (0x3 << 6) #define CCGR3_IPU2_DI0 (0x3 << 8) #define CCGR3_IPU2_DI1 (0x3 << 10) #define CCGR3_LDB_DI0 (0x3 << 12) #define CCGR3_LDB_DI1 (0x3 << 14) #define CCGR3_MMDC_CORE_ACLK_FAST (0x3 << 20) #define CCGR3_CG11 (0x3 << 22) #define CCGR3_MMDC_CORE_IPG (0x3 << 24) #define CCGR3_CG13 (0x3 << 26) #define CCGR3_OCRAM (0x3 << 28) #define CCM_CCGR4 0x078 #define CCGR4_PL301_MX6QFAST1_S133 (0x3 << 8) #define CCGR4_PL301_MX6QPER1_BCH (0x3 << 12) #define CCGR4_PL301_MX6QPER2_MAIN (0x3 << 14) #define CCM_CCGR5 0x07C #define CCGR5_SATA (0x3 << 4) #define CCGR5_SDMA (0x3 << 6) #define CCGR5_SSI1 (0x3 << 18) #define CCGR5_SSI2 (0x3 << 20) #define CCGR5_SSI3 (0x3 << 22) #define CCGR5_UART (0x3 << 24) #define CCGR5_UART_SERIAL (0x3 << 26) #define CCM_CCGR6 0x080 #define CCGR6_USBOH3 (0x3 << 0) #define CCGR6_USDHC1 (0x3 << 2) #define CCGR6_USDHC2 (0x3 << 4) #define CCGR6_USDHC3 (0x3 << 6) #define CCGR6_USDHC4 (0x3 << 8) #define CCM_CMEOR 0x088 #define CCM_ANALOG_PLL_ENET 0x000040e0 #define CCM_ANALOG_PLL_ENET_LOCK (1u << 31) #define CCM_ANALOG_PLL_ENET_ENABLE_100M (1u << 20) /* SATA */ #define CCM_ANALOG_PLL_ENET_BYPASS (1u << 16) #define CCM_ANALOG_PLL_ENET_ENABLE (1u << 13) /* Ether */ #define CCM_ANALOG_PLL_ENET_POWERDOWN (1u << 12) #endif Index: stable/11/sys/arm/freescale/imx/imx_ccmvar.h =================================================================== --- stable/11/sys/arm/freescale/imx/imx_ccmvar.h (revision 331505) +++ stable/11/sys/arm/freescale/imx/imx_ccmvar.h (revision 331506) @@ -1,63 +1,64 @@ /*- * Copyright (c) 2014 Ian Lepore * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. * * $FreeBSD$ */ #ifndef IMX_CCMVAR_H #define IMX_CCMVAR_H /* * We need a clock management system that works across unrelated SoCs and * devices. For now, to keep imx development moving, define some barebones * functionality that can be shared within the imx family by having each SoC * implement functions with a common name. * * The usb enable functions are best-effort. They turn on the usb otg, host, * and phy clocks in a SoC-specific manner, but it may take a lot more than that * to make usb work on a given board. In particular, it can require specific * pinmux setup of gpio pins connected to external phy parts, voltage regulators * and overcurrent detectors, and so on. On such boards, u-boot or other early * board setup code has to handle those things. */ +uint32_t imx_ccm_ecspi_hz(void); uint32_t imx_ccm_ipg_hz(void); uint32_t imx_ccm_perclk_hz(void); uint32_t imx_ccm_sdhci_hz(void); uint32_t imx_ccm_uart_hz(void); uint32_t imx_ccm_ahb_hz(void); void imx_ccm_usb_enable(device_t _usbdev); void imx_ccm_usbphy_enable(device_t _phydev); void imx_ccm_ssi_configure(device_t _ssidev); void imx_ccm_hdmi_enable(void); void imx_ccm_ipu_enable(int ipu); int imx6_ccm_sata_enable(void); /* Routines to get and set the arm clock root divisor register. */ uint32_t imx_ccm_get_cacrr(void); void imx_ccm_set_cacrr(uint32_t _divisor); #endif Index: stable/11/sys/arm/freescale/imx/imx_spi.c =================================================================== --- stable/11/sys/arm/freescale/imx/imx_spi.c (nonexistent) +++ stable/11/sys/arm/freescale/imx/imx_spi.c (revision 331506) @@ -0,0 +1,604 @@ +/*- + * SPDX-License-Identifier: BSD-2-Clause-FreeBSD + * + * Copyright (c) 2018 Ian Lepore + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + +#include +__FBSDID("$FreeBSD$"); + +/* + * Driver for imx Enhanced Configurable SPI; master-mode only. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +#include +#include +#include +#include +#include +#include + +#include "spibus_if.h" + +#define ECSPI_RXDATA 0x00 +#define ECSPI_TXDATA 0x04 +#define ECSPI_CTLREG 0x08 +#define CTLREG_BLEN_SHIFT 20 +#define CTLREG_BLEN_MASK 0x0fff +#define CTLREG_CSEL_SHIFT 18 +#define CTLREG_CSEL_MASK 0x03 +#define CTLREG_DRCTL_SHIFT 16 +#define CTLREG_DRCTL_MASK 0x03 +#define CTLREG_PREDIV_SHIFT 12 +#define CTLREG_PREDIV_MASK 0x0f +#define CTLREG_POSTDIV_SHIFT 8 +#define CTLREG_POSTDIV_MASK 0x0f +#define CTLREG_CMODE_SHIFT 4 +#define CTLREG_CMODE_MASK 0x0f +#define CTLREG_CMODES_MASTER (CTLREG_CMODE_MASK << CTLREG_CMODE_SHIFT) +#define CTLREG_SMC (1u << 3) +#define CTLREG_XCH (1u << 2) +#define CTLREG_HT (1u << 1) +#define CTLREG_EN (1u << 0) +#define ECSPI_CFGREG 0x0c +#define CFGREG_HTLEN_SHIFT 24 +#define CFGREG_SCLKCTL_SHIFT 20 +#define CFGREG_DATACTL_SHIFT 16 +#define CFGREG_SSPOL_SHIFT 12 +#define CFGREG_SSCTL_SHIFT 8 +#define CFGREG_SCLKPOL_SHIFT 4 +#define CFGREG_SCLKPHA_SHIFT 0 +#define CFGREG_MASK 0x0f /* all CFGREG fields are 4 bits */ +#define ECSPI_INTREG 0x10 +#define INTREG_TCEN (1u << 7) +#define INTREG_ROEN (1u << 6) +#define INTREG_RFEN (1u << 5) +#define INTREG_RDREN (1u << 4) +#define INTREG_RREN (1u << 3) +#define INTREG_TFEN (1u << 2) +#define INTREG_TDREN (1u << 1) +#define INTREG_TEEN (1u << 0) +#define ECSPI_DMAREG 0x14 +#define DMA_RX_THRESH_SHIFT 16 +#define DMA_RX_THRESH_MASK 0x3f +#define DMA_TX_THRESH_SHIFT 0 +#define DMA_TX_THRESH_MASK 0x3f +#define ECSPI_STATREG 0x18 +#define SREG_TC (1u << 7) +#define SREG_RO (1u << 6) +#define SREG_RF (1u << 5) +#define SREG_RDR (1u << 4) +#define SREG_RR (1u << 3) +#define SREG_TF (1u << 2) +#define SREG_TDR (1u << 1) +#define SREG_TE (1u << 0) +#define ECSPI_PERIODREG 0x1c +#define ECSPI_TESTREG 0x20 + +#define CS_MAX 4 /* Max number of chip selects. */ +#define CS_MASK 0x03 /* Mask flag bits out of chipsel. */ + +#define FIFO_SIZE 64 +#define FIFO_RXTHRESH 32 +#define FIFO_TXTHRESH 32 + +struct spi_softc { + device_t dev; + device_t spibus; + struct mtx mtx; + struct resource *memres; + struct resource *intres; + void *inthandle; + gpio_pin_t cspins[CS_MAX]; + u_int debug; + u_int basefreq; + uint32_t ctlreg; + uint32_t intreg; + uint32_t fifocnt; + uint8_t *rxbuf; + uint32_t rxidx; + uint32_t rxlen; + uint8_t *txbuf; + uint32_t txidx; + uint32_t txlen; +}; + +static struct ofw_compat_data compat_data[] = { + {"fsl,imx51-ecspi", true}, + {"fsl,imx53-ecspi", true}, + {"fsl,imx6dl-ecspi", true}, + {"fsl,imx6q-ecspi", true}, + {"fsl,imx6sx-ecspi", true}, + {"fsl,imx6ul-ecspi", true}, + {NULL, false} +}; + +static inline uint32_t +RD4(struct spi_softc *sc, bus_size_t offset) +{ + + return (bus_read_4(sc->memres, offset)); +} + +static inline void +WR4(struct spi_softc *sc, bus_size_t offset, uint32_t value) +{ + + bus_write_4(sc->memres, offset, value); +} + +static u_int +spi_calc_clockdiv(struct spi_softc *sc, u_int busfreq) +{ + u_int post, pre; + + /* Returning 0 effectively sets both dividers to 1. */ + if (sc->basefreq <= busfreq) + return (0); + + /* + * Brute-force this; all real-world bus speeds are going to be found on + * the 1st or 2nd time through this loop. + */ + for (post = 0; post < 16; ++post) { + pre = ((sc->basefreq >> post) / busfreq) - 1; + if (pre < 16) + break; + } + if (post == 16) { + /* The lowest we can go is ~115 Hz. */ + pre = 15; + post = 15; + } + + if (sc->debug >= 2) { + device_printf(sc->dev, + "base %u bus %u; pre %u, post %u; actual busfreq %u\n", + sc->basefreq, busfreq, pre, post, + (sc->basefreq / (pre + 1)) / (1 << post)); + } + + return (pre << CTLREG_PREDIV_SHIFT) | (post << CTLREG_POSTDIV_SHIFT); +} + +static void +spi_set_chipsel(struct spi_softc *sc, u_int cs, bool active) +{ + bool pinactive; + + /* + * This is kinda crazy... the gpio pins for chipsel are defined as + * active-high in the dts, but are supposed to be treated as active-low + * by this driver. So to turn on chipsel we have to invert the value + * passed to gpio_pin_set_active(). Then, to make it more fun, any + * slave can say its chipsel is active-high, so if that option is + * on, we have to invert the value again. + */ + pinactive = !active ^ (bool)(cs & SPIBUS_CS_HIGH); + + if (sc->debug >= 2) { + device_printf(sc->dev, "chipsel %u changed to %u\n", + (cs & ~SPIBUS_CS_HIGH), pinactive); + } + + /* + * Change the pin, then do a dummy read of its current state to ensure + * that the state change reaches the hardware before proceeding. + */ + gpio_pin_set_active(sc->cspins[cs & ~SPIBUS_CS_HIGH], pinactive); + gpio_pin_is_active(sc->cspins[cs & ~SPIBUS_CS_HIGH], &pinactive); +} + +static void +spi_hw_setup(struct spi_softc *sc, u_int cs, u_int mode, u_int freq) +{ + uint32_t reg; + + /* + * Set up control register, and write it first to bring the device out + * of reset. + */ + sc->ctlreg = CTLREG_EN | CTLREG_CMODES_MASTER | CTLREG_SMC; + sc->ctlreg |= spi_calc_clockdiv(sc, freq); + sc->ctlreg |= 7 << CTLREG_BLEN_SHIFT; /* XXX byte at a time */ + WR4(sc, ECSPI_CTLREG, sc->ctlreg); + + /* + * Set up the config register. Note that we do all transfers with the + * SPI hardware's chip-select set to zero. The actual chip select is + * handled with a gpio pin. + */ + reg = 0; + if (cs & SPIBUS_CS_HIGH) + reg |= 1u << CFGREG_SSPOL_SHIFT; + if (mode & SPIBUS_MODE_CPHA) + reg |= 1u << CFGREG_SCLKPHA_SHIFT; + if (mode & SPIBUS_MODE_CPOL) { + reg |= 1u << CFGREG_SCLKPOL_SHIFT; + reg |= 1u << CFGREG_SCLKCTL_SHIFT; + } + WR4(sc, ECSPI_CFGREG, reg); + + /* + * Set up the rx/tx FIFO interrupt thresholds. + */ + reg = (FIFO_RXTHRESH << DMA_RX_THRESH_SHIFT); + reg |= (FIFO_TXTHRESH << DMA_TX_THRESH_SHIFT); + WR4(sc, ECSPI_DMAREG, reg); + + /* + * Do a dummy read, to make sure the preceding writes reach the spi + * hardware before we assert any gpio chip select. + */ + (void)RD4(sc, ECSPI_CFGREG); +} + +static void +spi_empty_rxfifo(struct spi_softc *sc) +{ + + while (sc->rxidx < sc->rxlen && (RD4(sc, ECSPI_STATREG) & SREG_RR)) { + sc->rxbuf[sc->rxidx++] = (uint8_t)RD4(sc, ECSPI_RXDATA); + --sc->fifocnt; + } +} + +static void +spi_fill_txfifo(struct spi_softc *sc) +{ + + while (sc->txidx < sc->txlen && sc->fifocnt < FIFO_SIZE) { + WR4(sc, ECSPI_TXDATA, sc->txbuf[sc->txidx++]); + ++sc->fifocnt; + } + + /* + * If we're out of data, disable tx data ready (threshold) interrupts, + * and enable tx fifo empty interrupts. + */ + if (sc->txidx == sc->txlen) + sc->intreg = (sc->intreg & ~INTREG_TDREN) | INTREG_TEEN; +} + +static void +spi_intr(void *arg) +{ + struct spi_softc *sc = arg; + uint32_t intreg, status; + + mtx_lock(&sc->mtx); + + sc = arg; + intreg = sc->intreg; + status = RD4(sc, ECSPI_STATREG); + WR4(sc, ECSPI_STATREG, status); /* Clear w1c bits. */ + + /* + * If we get an overflow error, just signal that the transfer is done + * and wakeup the waiting thread, which will see that txidx != txlen and + * return an IO error to the caller. + */ + if (__predict_false(status & SREG_RO)) { + if (sc->debug || bootverbose) { + device_printf(sc->dev, "rxoverflow rxidx %u txidx %u\n", + sc->rxidx, sc->txidx); + } + sc->intreg = 0; + wakeup(sc); + mtx_unlock(&sc->mtx); + return; + } + + if (status & SREG_RR) + spi_empty_rxfifo(sc); + + if (status & SREG_TDR) + spi_fill_txfifo(sc); + + /* + * If we're out of bytes to send... + * - If Transfer Complete is set (shift register is empty) and we've + * received everything we expect, we're all done. + * - Else if Tx Fifo Empty is set, we need to stop waiting for that and + * switch to waiting for Transfer Complete (wait for shift register + * to empty out), and also for Receive Ready (last of incoming data). + */ + if (sc->txidx == sc->txlen) { + if ((status & SREG_TC) && sc->fifocnt == 0) { + sc->intreg = 0; + wakeup(sc); + } else if (status & SREG_TE) { + sc->intreg &= ~(sc->intreg & ~INTREG_TEEN); + sc->intreg |= INTREG_TCEN | INTREG_RREN; + } + } + + /* + * If interrupt flags changed, write the new flags to the hardware and + * do a dummy readback to ensure the changes reach the hardware before + * we exit the isr. + */ + if (sc->intreg != intreg) { + WR4(sc, ECSPI_INTREG, sc->intreg); + (void)RD4(sc, ECSPI_INTREG); + } + + if (sc->debug >= 3) { + device_printf(sc->dev, + "spi_intr, sreg 0x%08x intreg was 0x%08x now 0x%08x\n", + status, intreg, sc->intreg); + } + + mtx_unlock(&sc->mtx); +} + +static int +spi_xfer_buf(struct spi_softc *sc, void *rxbuf, void *txbuf, uint32_t len) +{ + int err; + + if (sc->debug >= 1) { + device_printf(sc->dev, + "spi_xfer_buf, rxbuf %p txbuf %p len %u\n", + rxbuf, txbuf, len); + } + + if (len == 0) + return (0); + + sc->rxbuf = rxbuf; + sc->rxlen = len; + sc->rxidx = 0; + sc->txbuf = txbuf; + sc->txlen = len; + sc->txidx = 0; + sc->intreg = INTREG_RDREN | INTREG_TDREN; + spi_fill_txfifo(sc); + + /* Enable interrupts last; spi_fill_txfifo() can change sc->intreg */ + WR4(sc, ECSPI_INTREG, sc->intreg); + + err = 0; + while (err == 0 && sc->intreg != 0) + err = msleep(sc, &sc->mtx, 0, "imxspi", 10 * hz); + + if (sc->rxidx != sc->rxlen || sc->txidx != sc->txlen) + err = EIO; + + return (err); +} + +static int +spi_transfer(device_t dev, device_t child, struct spi_command *cmd) +{ + struct spi_softc *sc = device_get_softc(dev); + uint32_t cs, mode, clock; + int err; + + spibus_get_cs(child, &cs); + spibus_get_clock(child, &clock); + spibus_get_mode(child, &mode); + + if (cs > CS_MAX || sc->cspins[cs] == NULL) { + if (sc->debug || bootverbose) + device_printf(sc->dev, "Invalid chip select %u\n", cs); + return (EINVAL); + } + + mtx_lock(&sc->mtx); + + if (sc->debug >= 1) { + device_printf(sc->dev, + "spi_transfer, cs 0x%x clock %u mode %u\n", + cs, clock, mode); + } + + /* Set up the hardware and select the device. */ + spi_hw_setup(sc, cs, mode, clock); + spi_set_chipsel(sc, cs, true); + + /* Transfer command then data bytes. */ + err = 0; + if (cmd->tx_cmd_sz > 0) + err = spi_xfer_buf(sc, cmd->rx_cmd, cmd->tx_cmd, + cmd->tx_cmd_sz); + if (cmd->tx_data_sz > 0 && err == 0) + err = spi_xfer_buf(sc, cmd->rx_data, cmd->tx_data, + cmd->tx_data_sz); + + /* Deselect the device, turn off (and reset) hardware. */ + spi_set_chipsel(sc, cs, false); + WR4(sc, ECSPI_CTLREG, 0); + + mtx_unlock(&sc->mtx); + + return (err); +} + +static phandle_t +spi_get_node(device_t bus, device_t dev) +{ + + /* + * Share our controller node with our spibus child; it instantiates + * devices by walking the children contained within our node. + */ + return ofw_bus_get_node(bus); +} + +static int +spi_detach(device_t dev) +{ + struct spi_softc *sc = device_get_softc(dev); + int idx; + + mtx_lock(&sc->mtx); + + bus_generic_detach(sc->dev); + if (sc->spibus != NULL) + device_delete_child(dev, sc->spibus); + + for (idx = 0; idx < nitems(sc->cspins); ++idx) { + if (sc->cspins[idx] != NULL) + gpio_pin_release(sc->cspins[idx]); + } + + if (sc->inthandle != NULL) + bus_teardown_intr(sc->dev, sc->intres, sc->inthandle); + if (sc->intres != NULL) + bus_release_resource(sc->dev, SYS_RES_IRQ, 0, sc->intres); + if (sc->memres != NULL) + bus_release_resource(sc->dev, SYS_RES_MEMORY, 0, sc->memres); + + mtx_unlock(&sc->mtx); + mtx_destroy(&sc->mtx); + + return (0); +} + +static int +spi_attach(device_t dev) +{ + struct spi_softc *sc = device_get_softc(dev); + phandle_t node; + int err, idx, rid; + + sc->dev = dev; + sc->basefreq = imx_ccm_ecspi_hz(); + + mtx_init(&sc->mtx, device_get_nameunit(dev), NULL, MTX_DEF); + + /* Set up debug-enable sysctl. */ + SYSCTL_ADD_INT(device_get_sysctl_ctx(sc->dev), + SYSCTL_CHILDREN(device_get_sysctl_tree(sc->dev)), + OID_AUTO, "debug", CTLFLAG_RWTUN, &sc->debug, 0, + "Enable debug, higher values = more info"); + + /* Allocate mmio register access resources. */ + rid = 0; + sc->memres = bus_alloc_resource_any(sc->dev, SYS_RES_MEMORY, &rid, + RF_ACTIVE); + if (sc->memres == NULL) { + device_printf(sc->dev, "could not allocate registers\n"); + spi_detach(sc->dev); + return (ENXIO); + } + + /* Allocate interrupt resources and set up handler. */ + rid = 0; + sc->intres = bus_alloc_resource_any(sc->dev, SYS_RES_IRQ, &rid, + RF_ACTIVE); + if (sc->intres == NULL) { + device_printf(sc->dev, "could not allocate interrupt\n"); + device_detach(sc->dev); + return (ENXIO); + } + err = bus_setup_intr(sc->dev, sc->intres, INTR_TYPE_MISC | INTR_MPSAFE, + NULL, spi_intr, sc, &sc->inthandle); + if (err != 0) { + device_printf(sc->dev, "could not setup interrupt handler"); + device_detach(sc->dev); + return (ENXIO); + } + + /* Allocate gpio pins for configured chip selects. */ + node = ofw_bus_get_node(sc->dev); + for (err = 0, idx = 0; err == 0 && idx < nitems(sc->cspins); ++idx) { + err = gpio_pin_get_by_ofw_propidx(sc->dev, node, "cs-gpios", + idx, &sc->cspins[idx]); + if (err == 0) { + gpio_pin_setflags(sc->cspins[idx], GPIO_PIN_OUTPUT); + } else if (sc->debug >= 2) { + device_printf(sc->dev, + "cannot configure gpio for chip select %u\n", idx); + } + } + + /* + * Hardware init: put all channels into Master mode, turn off the enable + * bit (gates off clocks); we only enable the hardware while xfers run. + */ + WR4(sc, ECSPI_CTLREG, CTLREG_CMODES_MASTER); + + /* Attach the bus driver. */ + sc->spibus = device_add_child(dev, "spibus", -1); + return (bus_generic_attach(sc->dev)); +} + +static int +spi_probe(device_t dev) +{ + + if (!ofw_bus_status_okay(dev)) + return (ENXIO); + + if (!ofw_bus_search_compatible(dev, compat_data)->ocd_data) + return (ENXIO); + + device_set_desc(dev, "i.MX ECSPI Master"); + return (BUS_PROBE_DEFAULT); +} + +static device_method_t spi_methods[] = { + DEVMETHOD(device_probe, spi_probe), + DEVMETHOD(device_attach, spi_attach), + DEVMETHOD(device_detach, spi_detach), + + /* spibus_if */ + DEVMETHOD(spibus_transfer, spi_transfer), + + /* ofw_bus_if */ + DEVMETHOD(ofw_bus_get_node, spi_get_node), + + DEVMETHOD_END +}; + +static driver_t spi_driver = { + "imx_spi", + spi_methods, + sizeof(struct spi_softc), +}; + +static devclass_t spi_devclass; + +DRIVER_MODULE(imx_spi, simplebus, spi_driver, spi_devclass, 0, 0); +DRIVER_MODULE(ofw_spibus, imx_spi, ofw_spibus_driver, ofw_spibus_devclass, 0, 0); +MODULE_DEPEND(imx_spi, ofw_spibus, 1, 1, 1); Property changes on: stable/11/sys/arm/freescale/imx/imx_spi.c ___________________________________________________________________ Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:keywords ## -0,0 +1 ## +FreeBSD=%H \ No newline at end of property Added: svn:mime-type ## -0,0 +1 ## +text/plain \ No newline at end of property Index: stable/11/sys/arm/freescale/vybrid/vf_spi.c =================================================================== --- stable/11/sys/arm/freescale/vybrid/vf_spi.c (revision 331505) +++ stable/11/sys/arm/freescale/vybrid/vf_spi.c (revision 331506) @@ -1,292 +1,294 @@ /*- * Copyright (c) 2014 Ruslan Bukin * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. */ /* * Vybrid Family Serial Peripheral Interface (SPI) * Chapter 47, Vybrid Reference Manual, Rev. 5, 07/2013 */ #include __FBSDID("$FreeBSD$"); #include #include #include #include #include #include #include #include #include #include #include #include #include "spibus_if.h" #include #include #include #include #include #include #include #include #define SPI_FIFO_SIZE 4 #define SPI_MCR 0x00 /* Module Configuration */ #define MCR_MSTR (1 << 31) /* Master/Slave Mode Select */ #define MCR_CONT_SCKE (1 << 30) /* Continuous SCK Enable */ #define MCR_FRZ (1 << 27) /* Freeze */ #define MCR_PCSIS_S 16 /* Peripheral Chip Select */ #define MCR_PCSIS_M 0x3f #define MCR_MDIS (1 << 14) /* Module Disable */ #define MCR_CLR_TXF (1 << 11) /* Clear TX FIFO */ #define MCR_CLR_RXF (1 << 10) /* Clear RX FIFO */ #define MCR_HALT (1 << 0) /* Starts and stops SPI transfers */ #define SPI_TCR 0x08 /* Transfer Count */ #define SPI_CTAR0 0x0C /* Clock and Transfer Attributes */ #define SPI_CTAR0_SLAVE 0x0C /* Clock and Transfer Attributes */ #define SPI_CTAR1 0x10 /* Clock and Transfer Attributes */ #define SPI_CTAR2 0x14 /* Clock and Transfer Attributes */ #define SPI_CTAR3 0x18 /* Clock and Transfer Attributes */ #define CTAR_FMSZ_M 0xf #define CTAR_FMSZ_S 27 /* Frame Size */ #define CTAR_FMSZ_8 0x7 /* 8 bits */ #define CTAR_CPOL (1 << 26) /* Clock Polarity */ #define CTAR_CPHA (1 << 25) /* Clock Phase */ #define CTAR_LSBFE (1 << 24) /* Less significant bit first */ #define CTAR_PCSSCK_M 0x3 #define CTAR_PCSSCK_S 22 /* PCS to SCK Delay Prescaler */ #define CTAR_PBR_M 0x3 #define CTAR_PBR_S 16 /* Baud Rate Prescaler */ #define CTAR_PBR_7 0x3 /* Divide by 7 */ #define CTAR_CSSCK_M 0xf #define CTAR_CSSCK_S 12 /* PCS to SCK Delay Scaler */ #define CTAR_BR_M 0xf #define CTAR_BR_S 0 /* Baud Rate Scaler */ #define SPI_SR 0x2C /* Status Register */ #define SR_TCF (1 << 31) /* Transfer Complete Flag */ #define SR_EOQF (1 << 28) /* End of Queue Flag */ #define SR_TFFF (1 << 25) /* Transmit FIFO Fill Flag */ #define SR_RFDF (1 << 17) /* Receive FIFO Drain Flag */ #define SPI_RSER 0x30 /* DMA/Interrupt Select */ #define RSER_EOQF_RE (1 << 28) /* Finished Request Enable */ #define SPI_PUSHR 0x34 /* PUSH TX FIFO In Master Mode */ #define PUSHR_CONT (1 << 31) /* Continuous Peripheral CS */ #define PUSHR_EOQ (1 << 27) /* End Of Queue */ #define PUSHR_CTCNT (1 << 26) /* Clear Transfer Counter */ #define PUSHR_PCS_M 0x3f #define PUSHR_PCS_S 16 /* Select PCS signals */ #define SPI_PUSHR_SLAVE 0x34 /* PUSH TX FIFO Register In Slave Mode */ #define SPI_POPR 0x38 /* POP RX FIFO Register */ #define SPI_TXFR0 0x3C /* Transmit FIFO Registers */ #define SPI_TXFR1 0x40 #define SPI_TXFR2 0x44 #define SPI_TXFR3 0x48 #define SPI_RXFR0 0x7C /* Receive FIFO Registers */ #define SPI_RXFR1 0x80 #define SPI_RXFR2 0x84 #define SPI_RXFR3 0x88 struct spi_softc { struct resource *res[2]; bus_space_tag_t bst; bus_space_handle_t bsh; void *ih; }; static struct resource_spec spi_spec[] = { { SYS_RES_MEMORY, 0, RF_ACTIVE }, { SYS_RES_IRQ, 0, RF_ACTIVE }, { -1, 0 } }; static int spi_probe(device_t dev) { if (!ofw_bus_status_okay(dev)) return (ENXIO); if (!ofw_bus_is_compatible(dev, "fsl,mvf600-spi")) return (ENXIO); device_set_desc(dev, "Vybrid Family Serial Peripheral Interface"); return (BUS_PROBE_DEFAULT); } static int spi_attach(device_t dev) { struct spi_softc *sc; uint32_t reg; sc = device_get_softc(dev); if (bus_alloc_resources(dev, spi_spec, sc->res)) { device_printf(dev, "could not allocate resources\n"); return (ENXIO); } /* Memory interface */ sc->bst = rman_get_bustag(sc->res[0]); sc->bsh = rman_get_bushandle(sc->res[0]); reg = READ4(sc, SPI_MCR); reg |= MCR_MSTR; reg &= ~(MCR_CONT_SCKE | MCR_MDIS | MCR_FRZ); reg &= ~(MCR_PCSIS_M << MCR_PCSIS_S); reg |= (MCR_PCSIS_M << MCR_PCSIS_S); /* PCS Active low */ reg |= (MCR_CLR_TXF | MCR_CLR_RXF); WRITE4(sc, SPI_MCR, reg); reg = READ4(sc, SPI_RSER); reg |= RSER_EOQF_RE; WRITE4(sc, SPI_RSER, reg); reg = READ4(sc, SPI_MCR); reg &= ~MCR_HALT; WRITE4(sc, SPI_MCR, reg); reg = READ4(sc, SPI_CTAR0); reg &= ~(CTAR_FMSZ_M << CTAR_FMSZ_S); reg |= (CTAR_FMSZ_8 << CTAR_FMSZ_S); /* * TODO: calculate BR * SCK baud rate = ( fsys / PBR ) * (1 + DBR) / BR * * reg &= ~(CTAR_BR_M << CTAR_BR_S); */ reg &= ~CTAR_CPOL; /* Polarity */ reg |= CTAR_CPHA; /* * Set LSB (Less significant bit first) * must be used for some applications, e.g. some LCDs */ reg |= CTAR_LSBFE; WRITE4(sc, SPI_CTAR0, reg); reg = READ4(sc, SPI_CTAR0); reg &= ~(CTAR_PBR_M << CTAR_PBR_S); reg |= (CTAR_PBR_7 << CTAR_PBR_S); WRITE4(sc, SPI_CTAR0, reg); device_add_child(dev, "spibus", 0); return (bus_generic_attach(dev)); } static int spi_txrx(struct spi_softc *sc, uint8_t *out_buf, uint8_t *in_buf, int bufsz, int cs) { uint32_t reg, wreg; uint32_t txcnt; uint32_t i; txcnt = 0; for (i = 0; i < bufsz; i++) { txcnt++; wreg = out_buf[i]; wreg |= PUSHR_CONT; wreg |= (cs << PUSHR_PCS_S); if (i == 0) wreg |= PUSHR_CTCNT; if (i == (bufsz - 1) || txcnt == SPI_FIFO_SIZE) wreg |= PUSHR_EOQ; WRITE4(sc, SPI_PUSHR, wreg); if (i == (bufsz - 1) || txcnt == SPI_FIFO_SIZE) { txcnt = 0; /* Wait last entry in a queue to be transmitted */ while((READ4(sc, SPI_SR) & SR_EOQF) == 0) continue; reg = READ4(sc, SPI_SR); reg |= (SR_TCF | SR_EOQF); WRITE4(sc, SPI_SR, reg); } /* Wait until RX FIFO is empty */ while((READ4(sc, SPI_SR) & SR_RFDF) == 0) continue; in_buf[i] = READ1(sc, SPI_POPR); } return (0); } static int spi_transfer(device_t dev, device_t child, struct spi_command *cmd) { struct spi_softc *sc; uint32_t cs; sc = device_get_softc(dev); KASSERT(cmd->tx_cmd_sz == cmd->rx_cmd_sz, ("%s: TX/RX command sizes should be equal", __func__)); KASSERT(cmd->tx_data_sz == cmd->rx_data_sz, ("%s: TX/RX data sizes should be equal", __func__)); /* get the proper chip select */ spibus_get_cs(child, &cs); + cs &= ~SPIBUS_CS_HIGH; + /* Command */ spi_txrx(sc, cmd->tx_cmd, cmd->rx_cmd, cmd->tx_cmd_sz, cs); /* Data */ spi_txrx(sc, cmd->tx_data, cmd->rx_data, cmd->tx_data_sz, cs); return (0); } static device_method_t spi_methods[] = { /* Device interface */ DEVMETHOD(device_probe, spi_probe), DEVMETHOD(device_attach, spi_attach), /* SPI interface */ DEVMETHOD(spibus_transfer, spi_transfer), { 0, 0 } }; static driver_t spi_driver = { "spi", spi_methods, sizeof(struct spi_softc), }; static devclass_t spi_devclass; DRIVER_MODULE(spi, simplebus, spi_driver, spi_devclass, 0, 0); Index: stable/11/sys/arm/lpc/lpc_spi.c =================================================================== --- stable/11/sys/arm/lpc/lpc_spi.c (revision 331505) +++ stable/11/sys/arm/lpc/lpc_spi.c (revision 331506) @@ -1,200 +1,202 @@ /*- * SPDX-License-Identifier: BSD-2-Clause-FreeBSD * * Copyright (c) 2011 Jakub Wojciech Klama * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. * */ #include __FBSDID("$FreeBSD$"); #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include "spibus_if.h" struct lpc_spi_softc { device_t ls_dev; struct resource * ls_mem_res; struct resource * ls_irq_res; bus_space_tag_t ls_bst; bus_space_handle_t ls_bsh; }; static int lpc_spi_probe(device_t); static int lpc_spi_attach(device_t); static int lpc_spi_detach(device_t); static int lpc_spi_transfer(device_t, device_t, struct spi_command *); #define lpc_spi_read_4(_sc, _reg) \ bus_space_read_4(_sc->ls_bst, _sc->ls_bsh, _reg) #define lpc_spi_write_4(_sc, _reg, _val) \ bus_space_write_4(_sc->ls_bst, _sc->ls_bsh, _reg, _val) static int lpc_spi_probe(device_t dev) { if (!ofw_bus_status_okay(dev)) return (ENXIO); if (!ofw_bus_is_compatible(dev, "lpc,spi")) return (ENXIO); device_set_desc(dev, "LPC32x0 PL022 SPI/SSP controller"); return (BUS_PROBE_DEFAULT); } static int lpc_spi_attach(device_t dev) { struct lpc_spi_softc *sc = device_get_softc(dev); int rid; sc->ls_dev = dev; rid = 0; sc->ls_mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, RF_ACTIVE); if (!sc->ls_mem_res) { device_printf(dev, "cannot allocate memory window\n"); return (ENXIO); } sc->ls_bst = rman_get_bustag(sc->ls_mem_res); sc->ls_bsh = rman_get_bushandle(sc->ls_mem_res); rid = 0; sc->ls_irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, RF_ACTIVE); if (!sc->ls_irq_res) { device_printf(dev, "cannot allocate interrupt\n"); return (ENXIO); } bus_space_write_4(sc->ls_bst, 0xd0028100, 0, (1<<12)|(1<<10)|(1<<9)|(1<<8)|(1<<6)|(1<<5)); lpc_pwr_write(dev, LPC_CLKPWR_SSP_CTRL, LPC_CLKPWR_SSP_CTRL_SSP0EN); lpc_spi_write_4(sc, LPC_SSP_CR0, LPC_SSP_CR0_DSS(8)); lpc_spi_write_4(sc, LPC_SSP_CR1, LPC_SSP_CR1_SSE); lpc_spi_write_4(sc, LPC_SSP_CPSR, 128); device_add_child(dev, "spibus", 0); return (bus_generic_attach(dev)); } static int lpc_spi_detach(device_t dev) { return (EBUSY); } static int lpc_spi_transfer(device_t dev, device_t child, struct spi_command *cmd) { struct lpc_spi_softc *sc = device_get_softc(dev); uint32_t cs; uint8_t *in_buf, *out_buf; int i; spibus_get_cs(child, &cs); + cs &= ~SPIBUS_CS_HIGH; + /* Set CS active */ lpc_gpio_set_state(child, cs, 0); /* Wait for FIFO to be ready */ while ((lpc_spi_read_4(sc, LPC_SSP_SR) & LPC_SSP_SR_TNF) == 0); /* Command */ in_buf = cmd->rx_cmd; out_buf = cmd->tx_cmd; for (i = 0; i < cmd->tx_cmd_sz; i++) { lpc_spi_write_4(sc, LPC_SSP_DR, out_buf[i]); in_buf[i] = lpc_spi_read_4(sc, LPC_SSP_DR); } /* Data */ in_buf = cmd->rx_data; out_buf = cmd->tx_data; for (i = 0; i < cmd->tx_data_sz; i++) { lpc_spi_write_4(sc, LPC_SSP_DR, out_buf[i]); in_buf[i] = lpc_spi_read_4(sc, LPC_SSP_DR); } /* Set CS inactive */ lpc_gpio_set_state(child, cs, 1); return (0); } static device_method_t lpc_spi_methods[] = { /* Device interface */ DEVMETHOD(device_probe, lpc_spi_probe), DEVMETHOD(device_attach, lpc_spi_attach), DEVMETHOD(device_detach, lpc_spi_detach), /* SPI interface */ DEVMETHOD(spibus_transfer, lpc_spi_transfer), { 0, 0 } }; static devclass_t lpc_spi_devclass; static driver_t lpc_spi_driver = { "spi", lpc_spi_methods, sizeof(struct lpc_spi_softc), }; DRIVER_MODULE(lpcspi, simplebus, lpc_spi_driver, lpc_spi_devclass, 0, 0); Index: stable/11/sys/arm/samsung/exynos/exynos5_spi.c =================================================================== --- stable/11/sys/arm/samsung/exynos/exynos5_spi.c (revision 331505) +++ stable/11/sys/arm/samsung/exynos/exynos5_spi.c (revision 331506) @@ -1,234 +1,236 @@ /*- * Copyright (c) 2014 Ruslan Bukin * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. */ /* * Exynos 5 Serial Peripheral Interface (SPI) */ #include __FBSDID("$FreeBSD$"); #include #include #include #include #include #include #include #include #include #include #include #include #include "spibus_if.h" #include #include #include #include #include #include #include #define CH_CFG 0x00 /* SPI configuration */ #define SW_RST (1 << 5) /* Reset */ #define RX_CH_ON (1 << 1) /* SPI Rx Channel On */ #define TX_CH_ON (1 << 0) /* SPI Tx Channel On */ #define MODE_CFG 0x08 /* FIFO control */ #define CS_REG 0x0C /* slave selection control */ #define NSSOUT (1 << 0) #define SPI_INT_EN 0x10 /* interrupt enable */ #define SPI_STATUS 0x14 /* SPI status */ #define TX_FIFO_LVL_S 6 #define TX_FIFO_LVL_M 0x1ff #define RX_FIFO_LVL_S 15 #define RX_FIFO_LVL_M 0x1ff #define SPI_TX_DATA 0x18 /* Tx data */ #define SPI_RX_DATA 0x1C /* Rx data */ #define PACKET_CNT_REG 0x20 /* packet count */ #define PENDING_CLR_REG 0x24 /* interrupt pending clear */ #define SWAP_CFG 0x28 /* swap configuration */ #define FB_CLK_SEL 0x2C /* feedback clock selection */ #define FB_CLK_180 0x2 /* 180 degree phase lagging */ struct spi_softc { struct resource *res[2]; bus_space_tag_t bst; bus_space_handle_t bsh; device_t dev; }; struct spi_softc *spi_sc; static struct resource_spec spi_spec[] = { { SYS_RES_MEMORY, 0, RF_ACTIVE }, { SYS_RES_IRQ, 0, RF_ACTIVE }, { -1, 0 } }; static int spi_probe(device_t dev) { if (!ofw_bus_status_okay(dev)) return (ENXIO); if (!ofw_bus_is_compatible(dev, "samsung,exynos5-spi")) return (ENXIO); device_set_desc(dev, "Exynos 5 Serial Peripheral Interface (SPI)"); return (BUS_PROBE_DEFAULT); } static int spi_attach(device_t dev) { struct spi_softc *sc; int reg; sc = device_get_softc(dev); sc->dev = dev; if (bus_alloc_resources(dev, spi_spec, sc->res)) { device_printf(dev, "could not allocate resources\n"); return (ENXIO); } /* Memory interface */ sc->bst = rman_get_bustag(sc->res[0]); sc->bsh = rman_get_bushandle(sc->res[0]); spi_sc = sc; WRITE4(sc, FB_CLK_SEL, FB_CLK_180); reg = READ4(sc, CH_CFG); reg |= (RX_CH_ON | TX_CH_ON); WRITE4(sc, CH_CFG, reg); device_add_child(dev, "spibus", 0); return (bus_generic_attach(dev)); } static int spi_txrx(struct spi_softc *sc, uint8_t *out_buf, uint8_t *in_buf, int bufsz, int cs) { uint32_t reg; uint32_t i; if (bufsz == 0) { /* Nothing to transfer */ return (0); } /* Reset registers */ reg = READ4(sc, CH_CFG); reg |= SW_RST; WRITE4(sc, CH_CFG, reg); reg &= ~SW_RST; WRITE4(sc, CH_CFG, reg); /* Assert CS */ reg = READ4(sc, CS_REG); reg &= ~NSSOUT; WRITE4(sc, CS_REG, reg); for (i = 0; i < bufsz; i++) { /* TODO: Implement FIFO operation */ /* Wait all the data shifted out */ while (READ4(sc, SPI_STATUS) & \ (TX_FIFO_LVL_M << TX_FIFO_LVL_S)) continue; WRITE1(sc, SPI_TX_DATA, out_buf[i]); /* Wait until no data available */ while ((READ4(sc, SPI_STATUS) & \ (RX_FIFO_LVL_M << RX_FIFO_LVL_S)) == 0) continue; in_buf[i] = READ1(sc, SPI_RX_DATA); } /* Deassert CS */ reg = READ4(sc, CS_REG); reg |= NSSOUT; WRITE4(sc, CS_REG, reg); return (0); } static int spi_transfer(device_t dev, device_t child, struct spi_command *cmd) { struct spi_softc *sc; uint32_t cs; sc = device_get_softc(dev); KASSERT(cmd->tx_cmd_sz == cmd->rx_cmd_sz, ("%s: TX/RX command sizes should be equal", __func__)); KASSERT(cmd->tx_data_sz == cmd->rx_data_sz, ("%s: TX/RX data sizes should be equal", __func__)); /* get the proper chip select */ spibus_get_cs(child, &cs); + cs &= ~SPIBUS_CS_HIGH; + /* Command */ spi_txrx(sc, cmd->tx_cmd, cmd->rx_cmd, cmd->tx_cmd_sz, cs); /* Data */ spi_txrx(sc, cmd->tx_data, cmd->rx_data, cmd->tx_data_sz, cs); return (0); } static device_method_t spi_methods[] = { DEVMETHOD(device_probe, spi_probe), DEVMETHOD(device_attach, spi_attach), /* SPI interface */ DEVMETHOD(spibus_transfer, spi_transfer), { 0, 0 } }; static driver_t spi_driver = { "spi", spi_methods, sizeof(struct spi_softc), }; static devclass_t spi_devclass; DRIVER_MODULE(spi, simplebus, spi_driver, spi_devclass, 0, 0); Index: stable/11/sys/arm/ti/ti_spi.c =================================================================== --- stable/11/sys/arm/ti/ti_spi.c (revision 331505) +++ stable/11/sys/arm/ti/ti_spi.c (revision 331506) @@ -1,582 +1,585 @@ /*- * Copyright (c) 2016 Rubicon Communications, LLC (Netgate) * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. * */ #include __FBSDID("$FreeBSD$"); #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include "spibus_if.h" static void ti_spi_intr(void *); static int ti_spi_detach(device_t); #undef TI_SPI_DEBUG #ifdef TI_SPI_DEBUG #define IRQSTATUSBITS \ "\020\1TX0_EMPTY\2TX0_UNDERFLOW\3RX0_FULL\4RX0_OVERFLOW" \ "\5TX1_EMPTY\6TX1_UNDERFLOW\7RX1_FULL\11TX2_EMPTY" \ "\12TX1_UNDERFLOW\13RX2_FULL\15TX3_EMPTY\16TX3_UNDERFLOW" \ "\17RX3_FULL\22EOW" #define CONFBITS \ "\020\1PHA\2POL\7EPOL\17DMAW\20DMAR\21DPE0\22DPE1\23IS" \ "\24TURBO\25FORCE\30SBE\31SBPOL\34FFEW\35FFER\36CLKG" #define STATBITS \ "\020\1RXS\2TXS\3EOT\4TXFFE\5TXFFF\6RXFFE\7RXFFFF" #define MODULCTRLBITS \ "\020\1SINGLE\2NOSPIEN\3SLAVE\4SYST\10MOA\11FDAA" #define CTRLBITS \ "\020\1ENABLED" static void ti_spi_printr(device_t dev) { int clk, conf, ctrl, div, i, j, wl; struct ti_spi_softc *sc; uint32_t reg; sc = device_get_softc(dev); reg = TI_SPI_READ(sc, MCSPI_SYSCONFIG); device_printf(dev, "SYSCONFIG: %#x\n", reg); reg = TI_SPI_READ(sc, MCSPI_SYSSTATUS); device_printf(dev, "SYSSTATUS: %#x\n", reg); reg = TI_SPI_READ(sc, MCSPI_IRQSTATUS); device_printf(dev, "IRQSTATUS: 0x%b\n", reg, IRQSTATUSBITS); reg = TI_SPI_READ(sc, MCSPI_IRQENABLE); device_printf(dev, "IRQENABLE: 0x%b\n", reg, IRQSTATUSBITS); reg = TI_SPI_READ(sc, MCSPI_MODULCTRL); device_printf(dev, "MODULCTRL: 0x%b\n", reg, MODULCTRLBITS); for (i = 0; i < sc->sc_numcs; i++) { ctrl = TI_SPI_READ(sc, MCSPI_CTRL_CH(i)); conf = TI_SPI_READ(sc, MCSPI_CONF_CH(i)); device_printf(dev, "CH%dCONF: 0x%b\n", i, conf, CONFBITS); if (conf & MCSPI_CONF_CLKG) { div = (conf >> MCSPI_CONF_CLK_SHIFT) & MCSPI_CONF_CLK_MSK; div |= ((ctrl >> MCSPI_CTRL_EXTCLK_SHIFT) & MCSPI_CTRL_EXTCLK_MSK) << 4; } else { div = 1; j = (conf >> MCSPI_CONF_CLK_SHIFT) & MCSPI_CONF_CLK_MSK; while (j-- > 0) div <<= 1; } clk = TI_SPI_GCLK / div; wl = ((conf >> MCSPI_CONF_WL_SHIFT) & MCSPI_CONF_WL_MSK) + 1; device_printf(dev, "wordlen: %-2d clock: %d\n", wl, clk); reg = TI_SPI_READ(sc, MCSPI_STAT_CH(i)); device_printf(dev, "CH%dSTAT: 0x%b\n", i, reg, STATBITS); device_printf(dev, "CH%dCTRL: 0x%b\n", i, ctrl, CTRLBITS); } reg = TI_SPI_READ(sc, MCSPI_XFERLEVEL); device_printf(dev, "XFERLEVEL: %#x\n", reg); } #endif static void ti_spi_set_clock(struct ti_spi_softc *sc, int ch, int freq) { uint32_t clkdiv, conf, div, extclk, reg; clkdiv = TI_SPI_GCLK / freq; if (clkdiv > MCSPI_EXTCLK_MSK) { extclk = 0; clkdiv = 0; div = 1; while (TI_SPI_GCLK / div > freq && clkdiv <= 0xf) { clkdiv++; div <<= 1; } conf = clkdiv << MCSPI_CONF_CLK_SHIFT; } else { extclk = clkdiv >> 4; clkdiv &= MCSPI_CONF_CLK_MSK; conf = MCSPI_CONF_CLKG | clkdiv << MCSPI_CONF_CLK_SHIFT; } reg = TI_SPI_READ(sc, MCSPI_CTRL_CH(ch)); reg &= ~(MCSPI_CTRL_EXTCLK_MSK << MCSPI_CTRL_EXTCLK_SHIFT); reg |= extclk << MCSPI_CTRL_EXTCLK_SHIFT; TI_SPI_WRITE(sc, MCSPI_CTRL_CH(ch), reg); reg = TI_SPI_READ(sc, MCSPI_CONF_CH(ch)); reg &= ~(MCSPI_CONF_CLKG | MCSPI_CONF_CLK_MSK << MCSPI_CONF_CLK_SHIFT); TI_SPI_WRITE(sc, MCSPI_CONF_CH(ch), reg | conf); } static int ti_spi_probe(device_t dev) { if (!ofw_bus_status_okay(dev)) return (ENXIO); if (!ofw_bus_is_compatible(dev, "ti,omap4-mcspi")) return (ENXIO); device_set_desc(dev, "TI McSPI controller"); return (BUS_PROBE_DEFAULT); } static int ti_spi_attach(device_t dev) { int clk_id, err, i, rid, timeout; struct ti_spi_softc *sc; uint32_t rev; sc = device_get_softc(dev); sc->sc_dev = dev; /* * Get the MMCHS device id from FDT. If it's not there use the newbus * unit number (which will work as long as the devices are in order and * none are skipped in the fdt). Note that this is a property we made * up and added in freebsd, it doesn't exist in the published bindings. */ clk_id = ti_hwmods_get_clock(dev); if (clk_id == INVALID_CLK_IDENT) { device_printf(dev, "failed to get clock based on hwmods property\n"); return (EINVAL); } /* Activate the McSPI module. */ err = ti_prcm_clk_enable(clk_id); if (err) { device_printf(dev, "Error: failed to activate source clock\n"); return (err); } /* Get the number of available channels. */ if ((OF_getencprop(ofw_bus_get_node(dev), "ti,spi-num-cs", &sc->sc_numcs, sizeof(sc->sc_numcs))) <= 0) { sc->sc_numcs = 2; } rid = 0; sc->sc_mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, RF_ACTIVE); if (!sc->sc_mem_res) { device_printf(dev, "cannot allocate memory window\n"); return (ENXIO); } sc->sc_bst = rman_get_bustag(sc->sc_mem_res); sc->sc_bsh = rman_get_bushandle(sc->sc_mem_res); rid = 0; sc->sc_irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, RF_ACTIVE); if (!sc->sc_irq_res) { bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->sc_mem_res); device_printf(dev, "cannot allocate interrupt\n"); return (ENXIO); } /* Hook up our interrupt handler. */ if (bus_setup_intr(dev, sc->sc_irq_res, INTR_TYPE_MISC | INTR_MPSAFE, NULL, ti_spi_intr, sc, &sc->sc_intrhand)) { bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sc_irq_res); bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->sc_mem_res); device_printf(dev, "cannot setup the interrupt handler\n"); return (ENXIO); } mtx_init(&sc->sc_mtx, "ti_spi", NULL, MTX_DEF); /* Issue a softreset to the controller */ TI_SPI_WRITE(sc, MCSPI_SYSCONFIG, MCSPI_SYSCONFIG_SOFTRESET); timeout = 1000; while (!(TI_SPI_READ(sc, MCSPI_SYSSTATUS) & MCSPI_SYSSTATUS_RESETDONE)) { if (--timeout == 0) { device_printf(dev, "Error: Controller reset operation timed out\n"); ti_spi_detach(dev); return (ENXIO); } DELAY(100); } /* Print the McSPI module revision. */ rev = TI_SPI_READ(sc, MCSPI_REVISION); device_printf(dev, "scheme: %#x func: %#x rtl: %d rev: %d.%d custom rev: %d\n", (rev >> MCSPI_REVISION_SCHEME_SHIFT) & MCSPI_REVISION_SCHEME_MSK, (rev >> MCSPI_REVISION_FUNC_SHIFT) & MCSPI_REVISION_FUNC_MSK, (rev >> MCSPI_REVISION_RTL_SHIFT) & MCSPI_REVISION_RTL_MSK, (rev >> MCSPI_REVISION_MAJOR_SHIFT) & MCSPI_REVISION_MAJOR_MSK, (rev >> MCSPI_REVISION_MINOR_SHIFT) & MCSPI_REVISION_MINOR_MSK, (rev >> MCSPI_REVISION_CUSTOM_SHIFT) & MCSPI_REVISION_CUSTOM_MSK); /* Set Master mode, single channel. */ TI_SPI_WRITE(sc, MCSPI_MODULCTRL, MCSPI_MODULCTRL_SINGLE); /* Clear pending interrupts and disable interrupts. */ TI_SPI_WRITE(sc, MCSPI_IRQENABLE, 0x0); TI_SPI_WRITE(sc, MCSPI_IRQSTATUS, 0xffff); for (i = 0; i < sc->sc_numcs; i++) { /* * Default to SPI mode 0, CS active low, 8 bits word length and * 500kHz clock. */ TI_SPI_WRITE(sc, MCSPI_CONF_CH(i), MCSPI_CONF_DPE0 | MCSPI_CONF_EPOL | (8 - 1) << MCSPI_CONF_WL_SHIFT); /* Set initial clock - 500kHz. */ ti_spi_set_clock(sc, i, 500000); } #ifdef TI_SPI_DEBUG ti_spi_printr(dev); #endif device_add_child(dev, "spibus", -1); return (bus_generic_attach(dev)); } static int ti_spi_detach(device_t dev) { struct ti_spi_softc *sc; sc = device_get_softc(dev); /* Clear pending interrupts and disable interrupts. */ TI_SPI_WRITE(sc, MCSPI_IRQENABLE, 0); TI_SPI_WRITE(sc, MCSPI_IRQSTATUS, 0xffff); /* Reset controller. */ TI_SPI_WRITE(sc, MCSPI_SYSCONFIG, MCSPI_SYSCONFIG_SOFTRESET); bus_generic_detach(dev); mtx_destroy(&sc->sc_mtx); if (sc->sc_intrhand) bus_teardown_intr(dev, sc->sc_irq_res, sc->sc_intrhand); if (sc->sc_irq_res) bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sc_irq_res); if (sc->sc_mem_res) bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->sc_mem_res); return (0); } static int ti_spi_fill_fifo(struct ti_spi_softc *sc) { int bytes, timeout; struct spi_command *cmd; uint32_t written; uint8_t *data; cmd = sc->sc_cmd; bytes = min(sc->sc_len - sc->sc_written, sc->sc_fifolvl); while (bytes-- > 0) { data = (uint8_t *)cmd->tx_cmd; written = sc->sc_written++; if (written >= cmd->tx_cmd_sz) { data = (uint8_t *)cmd->tx_data; written -= cmd->tx_cmd_sz; } if (sc->sc_fifolvl == 1) { /* FIFO disabled. */ timeout = 1000; while (--timeout > 0 && (TI_SPI_READ(sc, MCSPI_STAT_CH(sc->sc_cs)) & MCSPI_STAT_TXS) == 0) { DELAY(100); } if (timeout == 0) return (-1); } TI_SPI_WRITE(sc, MCSPI_TX_CH(sc->sc_cs), data[written]); } return (0); } static int ti_spi_drain_fifo(struct ti_spi_softc *sc) { int bytes, timeout; struct spi_command *cmd; uint32_t read; uint8_t *data; cmd = sc->sc_cmd; bytes = min(sc->sc_len - sc->sc_read, sc->sc_fifolvl); while (bytes-- > 0) { data = (uint8_t *)cmd->rx_cmd; read = sc->sc_read++; if (read >= cmd->rx_cmd_sz) { data = (uint8_t *)cmd->rx_data; read -= cmd->rx_cmd_sz; } if (sc->sc_fifolvl == 1) { /* FIFO disabled. */ timeout = 1000; while (--timeout > 0 && (TI_SPI_READ(sc, MCSPI_STAT_CH(sc->sc_cs)) & MCSPI_STAT_RXS) == 0) { DELAY(100); } if (timeout == 0) return (-1); } data[read] = TI_SPI_READ(sc, MCSPI_RX_CH(sc->sc_cs)); } return (0); } static void ti_spi_intr(void *arg) { int eow; struct ti_spi_softc *sc; uint32_t status; eow = 0; sc = (struct ti_spi_softc *)arg; TI_SPI_LOCK(sc); status = TI_SPI_READ(sc, MCSPI_IRQSTATUS); /* * No new TX_empty or RX_full event will be asserted while the CPU has * not performed the number of writes or reads defined by * MCSPI_XFERLEVEL[AEL] and MCSPI_XFERLEVEL[AFL]. It is responsibility * of CPU perform the right number of writes and reads. */ if (status & MCSPI_IRQ_TX0_EMPTY) ti_spi_fill_fifo(sc); if (status & MCSPI_IRQ_RX0_FULL) ti_spi_drain_fifo(sc); if (status & MCSPI_IRQ_EOW) eow = 1; /* Clear interrupt status. */ TI_SPI_WRITE(sc, MCSPI_IRQSTATUS, status); /* Check for end of transfer. */ if (sc->sc_written == sc->sc_len && sc->sc_read == sc->sc_len) { sc->sc_flags |= TI_SPI_DONE; wakeup(sc->sc_dev); } TI_SPI_UNLOCK(sc); } static int ti_spi_pio_transfer(struct ti_spi_softc *sc) { while (sc->sc_len - sc->sc_written > 0) { if (ti_spi_fill_fifo(sc) == -1) return (EIO); if (ti_spi_drain_fifo(sc) == -1) return (EIO); } return (0); } static int ti_spi_gcd(int a, int b) { int m; while ((m = a % b) != 0) { a = b; b = m; } return (b); } static int ti_spi_transfer(device_t dev, device_t child, struct spi_command *cmd) { int err; struct ti_spi_softc *sc; uint32_t reg, cs; sc = device_get_softc(dev); KASSERT(cmd->tx_cmd_sz == cmd->rx_cmd_sz, ("TX/RX command sizes should be equal")); KASSERT(cmd->tx_data_sz == cmd->rx_data_sz, ("TX/RX data sizes should be equal")); /* Get the proper chip select for this child. */ spibus_get_cs(child, &cs); + + cs &= ~SPIBUS_CS_HIGH; + if (cs > sc->sc_numcs) { device_printf(dev, "Invalid chip select %d requested by %s\n", cs, device_get_nameunit(child)); return (EINVAL); } TI_SPI_LOCK(sc); /* If the controller is in use wait until it is available. */ while (sc->sc_flags & TI_SPI_BUSY) mtx_sleep(dev, &sc->sc_mtx, 0, "ti_spi", 0); /* Now we have control over SPI controller. */ sc->sc_flags = TI_SPI_BUSY; /* Save the SPI command data. */ sc->sc_cs = cs; sc->sc_cmd = cmd; sc->sc_read = 0; sc->sc_written = 0; sc->sc_len = cmd->tx_cmd_sz + cmd->tx_data_sz; sc->sc_fifolvl = ti_spi_gcd(sc->sc_len, TI_SPI_FIFOSZ); if (sc->sc_fifolvl < 2 || sc->sc_len > 0xffff) sc->sc_fifolvl = 1; /* FIFO disabled. */ /* Disable FIFO for now. */ sc->sc_fifolvl = 1; /* Use a safe clock - 500kHz. */ ti_spi_set_clock(sc, sc->sc_cs, 500000); /* Disable the FIFO. */ TI_SPI_WRITE(sc, MCSPI_XFERLEVEL, 0); /* 8 bits word, d0 miso, d1 mosi, mode 0 and CS active low. */ reg = TI_SPI_READ(sc, MCSPI_CONF_CH(sc->sc_cs)); reg &= ~(MCSPI_CONF_FFER | MCSPI_CONF_FFEW | MCSPI_CONF_SBPOL | MCSPI_CONF_SBE | MCSPI_CONF_TURBO | MCSPI_CONF_IS | MCSPI_CONF_DPE1 | MCSPI_CONF_DPE0 | MCSPI_CONF_DMAR | MCSPI_CONF_DMAW | MCSPI_CONF_EPOL); reg |= MCSPI_CONF_DPE0 | MCSPI_CONF_EPOL | MCSPI_CONF_WL8BITS; TI_SPI_WRITE(sc, MCSPI_CONF_CH(sc->sc_cs), reg); #if 0 /* Enable channel interrupts. */ reg = TI_SPI_READ(sc, MCSPI_IRQENABLE); reg |= 0xf; TI_SPI_WRITE(sc, MCSPI_IRQENABLE, reg); #endif /* Start the transfer. */ reg = TI_SPI_READ(sc, MCSPI_CTRL_CH(sc->sc_cs)); TI_SPI_WRITE(sc, MCSPI_CTRL_CH(sc->sc_cs), reg | MCSPI_CTRL_ENABLE); /* Force CS on. */ reg = TI_SPI_READ(sc, MCSPI_CONF_CH(sc->sc_cs)); TI_SPI_WRITE(sc, MCSPI_CONF_CH(sc->sc_cs), reg |= MCSPI_CONF_FORCE); err = 0; if (sc->sc_fifolvl == 1) err = ti_spi_pio_transfer(sc); /* Force CS off. */ reg = TI_SPI_READ(sc, MCSPI_CONF_CH(sc->sc_cs)); reg &= ~MCSPI_CONF_FORCE; TI_SPI_WRITE(sc, MCSPI_CONF_CH(sc->sc_cs), reg); /* Disable IRQs. */ reg = TI_SPI_READ(sc, MCSPI_IRQENABLE); reg &= ~0xf; TI_SPI_WRITE(sc, MCSPI_IRQENABLE, reg); TI_SPI_WRITE(sc, MCSPI_IRQSTATUS, 0xf); /* Disable the SPI channel. */ reg = TI_SPI_READ(sc, MCSPI_CTRL_CH(sc->sc_cs)); reg &= ~MCSPI_CTRL_ENABLE; TI_SPI_WRITE(sc, MCSPI_CTRL_CH(sc->sc_cs), reg); /* Disable FIFO. */ reg = TI_SPI_READ(sc, MCSPI_CONF_CH(sc->sc_cs)); reg &= ~(MCSPI_CONF_FFER | MCSPI_CONF_FFEW); TI_SPI_WRITE(sc, MCSPI_CONF_CH(sc->sc_cs), reg); /* Release the controller and wakeup the next thread waiting for it. */ sc->sc_flags = 0; wakeup_one(dev); TI_SPI_UNLOCK(sc); return (err); } static phandle_t ti_spi_get_node(device_t bus, device_t dev) { /* Share controller node with spibus. */ return (ofw_bus_get_node(bus)); } static device_method_t ti_spi_methods[] = { /* Device interface */ DEVMETHOD(device_probe, ti_spi_probe), DEVMETHOD(device_attach, ti_spi_attach), DEVMETHOD(device_detach, ti_spi_detach), /* SPI interface */ DEVMETHOD(spibus_transfer, ti_spi_transfer), /* ofw_bus interface */ DEVMETHOD(ofw_bus_get_node, ti_spi_get_node), DEVMETHOD_END }; static devclass_t ti_spi_devclass; static driver_t ti_spi_driver = { "spi", ti_spi_methods, sizeof(struct ti_spi_softc), }; DRIVER_MODULE(ti_spi, simplebus, ti_spi_driver, ti_spi_devclass, 0, 0); Index: stable/11/sys/dev/flash/at45d.c =================================================================== --- stable/11/sys/dev/flash/at45d.c (revision 331505) +++ stable/11/sys/dev/flash/at45d.c (revision 331506) @@ -1,452 +1,453 @@ /*- * SPDX-License-Identifier: BSD-2-Clause-FreeBSD * * Copyright (c) 2006 M. Warner Losh * Copyright (c) 2011-2012 Ian Lepore * Copyright (c) 2012 Marius Strobl * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ #include __FBSDID("$FreeBSD$"); #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include "spibus_if.h" struct at45d_flash_ident { const char *name; uint32_t jedec; uint16_t pagecount; uint16_t pageoffset; uint16_t pagesize; uint16_t pagesize2n; }; struct at45d_softc { struct bio_queue_head bio_queue; struct mtx sc_mtx; struct disk *disk; struct proc *p; struct intr_config_hook config_intrhook; device_t dev; uint16_t pagecount; uint16_t pageoffset; uint16_t pagesize; }; #define AT45D_LOCK(_sc) mtx_lock(&(_sc)->sc_mtx) #define AT45D_UNLOCK(_sc) mtx_unlock(&(_sc)->sc_mtx) #define AT45D_LOCK_INIT(_sc) \ mtx_init(&_sc->sc_mtx, device_get_nameunit(_sc->dev), \ "at45d", MTX_DEF) #define AT45D_LOCK_DESTROY(_sc) mtx_destroy(&_sc->sc_mtx); #define AT45D_ASSERT_LOCKED(_sc) mtx_assert(&_sc->sc_mtx, MA_OWNED); #define AT45D_ASSERT_UNLOCKED(_sc) mtx_assert(&_sc->sc_mtx, MA_NOTOWNED); /* bus entry points */ static device_attach_t at45d_attach; static device_detach_t at45d_detach; static device_probe_t at45d_probe; /* disk routines */ static int at45d_close(struct disk *dp); static int at45d_open(struct disk *dp); static void at45d_strategy(struct bio *bp); static void at45d_task(void *arg); /* helper routines */ static void at45d_delayed_attach(void *xsc); static int at45d_get_mfg_info(device_t dev, uint8_t *resp); static int at45d_get_status(device_t dev, uint8_t *status); static int at45d_wait_ready(device_t dev, uint8_t *status); #define BUFFER_TRANSFER 0x53 #define BUFFER_COMPARE 0x60 #define PROGRAM_THROUGH_BUFFER 0x82 #define MANUFACTURER_ID 0x9f #define STATUS_REGISTER_READ 0xd7 #define CONTINUOUS_ARRAY_READ 0xe8 /* * A sectorsize2n != 0 is used to indicate that a device optionally supports * 2^N byte pages. If support for the latter is enabled, the sector offset * has to be reduced by one. */ static const struct at45d_flash_ident at45d_flash_devices[] = { { "AT45DB011B", 0x1f2200, 512, 9, 264, 256 }, { "AT45DB021B", 0x1f2300, 1024, 9, 264, 256 }, { "AT45DB041x", 0x1f2400, 2028, 9, 264, 256 }, { "AT45DB081B", 0x1f2500, 4096, 9, 264, 256 }, { "AT45DB161x", 0x1f2600, 4096, 10, 528, 512 }, { "AT45DB321x", 0x1f2700, 8192, 10, 528, 0 }, { "AT45DB321x", 0x1f2701, 8192, 10, 528, 512 }, { "AT45DB642x", 0x1f2800, 8192, 11, 1056, 1024 } }; static int at45d_get_status(device_t dev, uint8_t *status) { uint8_t rxBuf[8], txBuf[8]; struct spi_command cmd; int err; memset(&cmd, 0, sizeof(cmd)); memset(txBuf, 0, sizeof(txBuf)); memset(rxBuf, 0, sizeof(rxBuf)); txBuf[0] = STATUS_REGISTER_READ; cmd.tx_cmd = txBuf; cmd.rx_cmd = rxBuf; cmd.rx_cmd_sz = cmd.tx_cmd_sz = 2; err = SPIBUS_TRANSFER(device_get_parent(dev), dev, &cmd); *status = rxBuf[1]; return (err); } static int at45d_get_mfg_info(device_t dev, uint8_t *resp) { uint8_t rxBuf[8], txBuf[8]; struct spi_command cmd; int err; memset(&cmd, 0, sizeof(cmd)); memset(txBuf, 0, sizeof(txBuf)); memset(rxBuf, 0, sizeof(rxBuf)); txBuf[0] = MANUFACTURER_ID; cmd.tx_cmd = &txBuf; cmd.rx_cmd = &rxBuf; cmd.tx_cmd_sz = cmd.rx_cmd_sz = 5; err = SPIBUS_TRANSFER(device_get_parent(dev), dev, &cmd); if (err) return (err); memcpy(resp, rxBuf + 1, 4); return (0); } static int at45d_wait_ready(device_t dev, uint8_t *status) { struct timeval now, tout; int err; getmicrouptime(&tout); tout.tv_sec += 3; do { getmicrouptime(&now); if (now.tv_sec > tout.tv_sec) err = ETIMEDOUT; else err = at45d_get_status(dev, status); } while (err == 0 && (*status & 0x80) == 0); return (err); } static int at45d_probe(device_t dev) { device_set_desc(dev, "AT45D Flash Family"); return (0); } static int at45d_attach(device_t dev) { struct at45d_softc *sc; sc = device_get_softc(dev); sc->dev = dev; AT45D_LOCK_INIT(sc); /* We'll see what kind of flash we have later... */ sc->config_intrhook.ich_func = at45d_delayed_attach; sc->config_intrhook.ich_arg = sc; if (config_intrhook_establish(&sc->config_intrhook) != 0) { device_printf(dev, "config_intrhook_establish failed\n"); return (ENOMEM); } return (0); } static int at45d_detach(device_t dev) { return (EBUSY) /* XXX */; } static void at45d_delayed_attach(void *xsc) { struct at45d_softc *sc; const struct at45d_flash_ident *ident; u_int i; uint32_t jedec; uint16_t pagesize; uint8_t buf[4], status; sc = xsc; ident = NULL; jedec = 0; if (at45d_wait_ready(sc->dev, &status) != 0) device_printf(sc->dev, "Error waiting for device-ready.\n"); else if (at45d_get_mfg_info(sc->dev, buf) != 0) device_printf(sc->dev, "Failed to get ID.\n"); else { jedec = buf[0] << 16 | buf[1] << 8 | buf[2]; for (i = 0; i < nitems(at45d_flash_devices); i++) { if (at45d_flash_devices[i].jedec == jedec) { ident = &at45d_flash_devices[i]; break; } } } if (ident == NULL) device_printf(sc->dev, "JEDEC 0x%x not in list.\n", jedec); else { sc->pagecount = ident->pagecount; sc->pageoffset = ident->pageoffset; if (ident->pagesize2n != 0 && (status & 0x01) != 0) { sc->pageoffset -= 1; pagesize = ident->pagesize2n; } else pagesize = ident->pagesize; sc->pagesize = pagesize; sc->disk = disk_alloc(); sc->disk->d_open = at45d_open; sc->disk->d_close = at45d_close; sc->disk->d_strategy = at45d_strategy; sc->disk->d_name = "flash/spi"; sc->disk->d_drv1 = sc; sc->disk->d_maxsize = DFLTPHYS; sc->disk->d_sectorsize = pagesize; sc->disk->d_mediasize = pagesize * ident->pagecount; sc->disk->d_unit = device_get_unit(sc->dev); disk_create(sc->disk, DISK_VERSION); bioq_init(&sc->bio_queue); kproc_create(&at45d_task, sc, &sc->p, 0, 0, "task: at45d flash"); device_printf(sc->dev, "%s, %d bytes per page, %d pages\n", ident->name, pagesize, ident->pagecount); } config_intrhook_disestablish(&sc->config_intrhook); } static int at45d_open(struct disk *dp) { return (0); } static int at45d_close(struct disk *dp) { return (0); } static void at45d_strategy(struct bio *bp) { struct at45d_softc *sc; sc = (struct at45d_softc *)bp->bio_disk->d_drv1; AT45D_LOCK(sc); bioq_disksort(&sc->bio_queue, bp); wakeup(sc); AT45D_UNLOCK(sc); } static void at45d_task(void *arg) { uint8_t rxBuf[8], txBuf[8]; struct at45d_softc *sc; struct bio *bp; struct spi_command cmd; device_t dev, pdev; caddr_t buf; u_long len, resid; u_int addr, berr, err, offset, page; uint8_t status; sc = (struct at45d_softc*)arg; dev = sc->dev; pdev = device_get_parent(dev); memset(&cmd, 0, sizeof(cmd)); memset(txBuf, 0, sizeof(txBuf)); memset(rxBuf, 0, sizeof(rxBuf)); cmd.tx_cmd = txBuf; cmd.rx_cmd = rxBuf; for (;;) { AT45D_LOCK(sc); do { bp = bioq_takefirst(&sc->bio_queue); if (bp == NULL) msleep(sc, &sc->sc_mtx, PRIBIO, "jobqueue", 0); } while (bp == NULL); AT45D_UNLOCK(sc); berr = 0; buf = bp->bio_data; len = resid = bp->bio_bcount; page = bp->bio_offset / sc->pagesize; offset = bp->bio_offset % sc->pagesize; switch (bp->bio_cmd) { case BIO_READ: txBuf[0] = CONTINUOUS_ARRAY_READ; cmd.tx_cmd_sz = cmd.rx_cmd_sz = 8; cmd.tx_data = cmd.rx_data = buf; break; case BIO_WRITE: cmd.tx_cmd_sz = cmd.rx_cmd_sz = 4; cmd.tx_data = cmd.rx_data = buf; if (resid + offset > sc->pagesize) len = sc->pagesize - offset; break; default: berr = EINVAL; goto out; } /* * NB: for BIO_READ, this loop is only traversed once. */ while (resid > 0) { if (page > sc->pagecount) { berr = EINVAL; goto out; } addr = page << sc->pageoffset; if (bp->bio_cmd == BIO_WRITE) { if (len != sc->pagesize) { txBuf[0] = BUFFER_TRANSFER; txBuf[1] = ((addr >> 16) & 0xff); txBuf[2] = ((addr >> 8) & 0xff); txBuf[3] = 0; cmd.tx_data_sz = cmd.rx_data_sz = 0; err = SPIBUS_TRANSFER(pdev, dev, &cmd); if (err == 0) err = at45d_wait_ready(dev, &status); if (err != 0) { berr = EIO; goto out; } } txBuf[0] = PROGRAM_THROUGH_BUFFER; } addr += offset; txBuf[1] = ((addr >> 16) & 0xff); txBuf[2] = ((addr >> 8) & 0xff); txBuf[3] = (addr & 0xff); cmd.tx_data_sz = cmd.rx_data_sz = len; err = SPIBUS_TRANSFER(pdev, dev, &cmd); if (err == 0 && bp->bio_cmd != BIO_READ) err = at45d_wait_ready(dev, &status); if (err != 0) { berr = EIO; goto out; } if (bp->bio_cmd == BIO_WRITE) { addr = page << sc->pageoffset; txBuf[0] = BUFFER_COMPARE; txBuf[1] = ((addr >> 16) & 0xff); txBuf[2] = ((addr >> 8) & 0xff); txBuf[3] = 0; cmd.tx_data_sz = cmd.rx_data_sz = 0; err = SPIBUS_TRANSFER(pdev, dev, &cmd); if (err == 0) err = at45d_wait_ready(dev, &status); if (err != 0 || (status & 0x40) != 0) { device_printf(dev, "comparing page " "%d failed (status=0x%x)\n", addr, status); berr = EIO; goto out; } } page++; buf += len; offset = 0; resid -= len; if (resid > sc->pagesize) len = sc->pagesize; else len = resid; cmd.tx_data = cmd.rx_data = buf; } out: if (berr != 0) { bp->bio_flags |= BIO_ERROR; bp->bio_error = berr; } bp->bio_resid = resid; biodone(bp); } } static devclass_t at45d_devclass; static device_method_t at45d_methods[] = { /* Device interface */ DEVMETHOD(device_probe, at45d_probe), DEVMETHOD(device_attach, at45d_attach), DEVMETHOD(device_detach, at45d_detach), DEVMETHOD_END }; static driver_t at45d_driver = { "at45d", at45d_methods, sizeof(struct at45d_softc), }; DRIVER_MODULE(at45d, spibus, at45d_driver, at45d_devclass, NULL, NULL); +MODULE_DEPEND(at45d, spibus, 1, 1, 1); Index: stable/11/sys/dev/flash/mx25l.c =================================================================== --- stable/11/sys/dev/flash/mx25l.c (revision 331505) +++ stable/11/sys/dev/flash/mx25l.c (revision 331506) @@ -1,650 +1,689 @@ /*- * SPDX-License-Identifier: BSD-2-Clause-FreeBSD * * Copyright (c) 2006 M. Warner Losh. All rights reserved. * Copyright (c) 2009 Oleksandr Tymoshenko. All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ #include __FBSDID("$FreeBSD$"); #include "opt_platform.h" #include #include #include #include #include #include #include #include #include #include #include #include #include #ifdef FDT #include #include #include #endif #include #include "spibus_if.h" #include #define FL_NONE 0x00 #define FL_ERASE_4K 0x01 #define FL_ERASE_32K 0x02 #define FL_ENABLE_4B_ADDR 0x04 #define FL_DISABLE_4B_ADDR 0x08 /* * Define the sectorsize to be a smaller size rather than the flash * sector size. Trying to run FFS off of a 64k flash sector size * results in a completely un-usable system. */ #define MX25L_SECTORSIZE 512 struct mx25l_flash_ident { const char *name; uint8_t manufacturer_id; uint16_t device_id; unsigned int sectorsize; unsigned int sectorcount; unsigned int flags; }; struct mx25l_softc { device_t sc_dev; uint8_t sc_manufacturer_id; uint16_t sc_device_id; unsigned int sc_sectorsize; struct mtx sc_mtx; struct disk *sc_disk; struct proc *sc_p; struct bio_queue_head sc_bio_queue; unsigned int sc_flags; + unsigned int sc_taskstate; }; +#define TSTATE_STOPPED 0 +#define TSTATE_STOPPING 1 +#define TSTATE_RUNNING 2 + #define M25PXX_LOCK(_sc) mtx_lock(&(_sc)->sc_mtx) #define M25PXX_UNLOCK(_sc) mtx_unlock(&(_sc)->sc_mtx) #define M25PXX_LOCK_INIT(_sc) \ mtx_init(&_sc->sc_mtx, device_get_nameunit(_sc->sc_dev), \ "mx25l", MTX_DEF) #define M25PXX_LOCK_DESTROY(_sc) mtx_destroy(&_sc->sc_mtx); #define M25PXX_ASSERT_LOCKED(_sc) mtx_assert(&_sc->sc_mtx, MA_OWNED); #define M25PXX_ASSERT_UNLOCKED(_sc) mtx_assert(&_sc->sc_mtx, MA_NOTOWNED); /* disk routines */ static int mx25l_open(struct disk *dp); static int mx25l_close(struct disk *dp); static int mx25l_ioctl(struct disk *, u_long, void *, int, struct thread *); static void mx25l_strategy(struct bio *bp); static int mx25l_getattr(struct bio *bp); static void mx25l_task(void *arg); struct mx25l_flash_ident flash_devices[] = { { "en25f32", 0x1c, 0x3116, 64 * 1024, 64, FL_NONE }, { "en25p32", 0x1c, 0x2016, 64 * 1024, 64, FL_NONE }, { "en25p64", 0x1c, 0x2017, 64 * 1024, 128, FL_NONE }, { "en25q32", 0x1c, 0x3016, 64 * 1024, 64, FL_NONE }, { "en25q64", 0x1c, 0x3017, 64 * 1024, 128, FL_ERASE_4K }, { "m25p32", 0x20, 0x2016, 64 * 1024, 64, FL_NONE }, { "m25p64", 0x20, 0x2017, 64 * 1024, 128, FL_NONE }, { "mx25ll32", 0xc2, 0x2016, 64 * 1024, 64, FL_NONE }, { "mx25ll64", 0xc2, 0x2017, 64 * 1024, 128, FL_NONE }, { "mx25ll128", 0xc2, 0x2018, 64 * 1024, 256, FL_ERASE_4K | FL_ERASE_32K }, { "mx25ll256", 0xc2, 0x2019, 64 * 1024, 512, FL_ERASE_4K | FL_ERASE_32K | FL_ENABLE_4B_ADDR }, { "s25fl032", 0x01, 0x0215, 64 * 1024, 64, FL_NONE }, { "s25fl064", 0x01, 0x0216, 64 * 1024, 128, FL_NONE }, { "s25fl128", 0x01, 0x2018, 64 * 1024, 256, FL_NONE }, { "s25fl256s", 0x01, 0x0219, 64 * 1024, 512, FL_NONE }, { "SST25VF010A", 0xbf, 0x2549, 4 * 1024, 32, FL_ERASE_4K | FL_ERASE_32K }, { "SST25VF032B", 0xbf, 0x254a, 64 * 1024, 64, FL_ERASE_4K | FL_ERASE_32K }, /* Winbond -- w25x "blocks" are 64K, "sectors" are 4KiB */ { "w25x32", 0xef, 0x3016, 64 * 1024, 64, FL_ERASE_4K }, { "w25x64", 0xef, 0x3017, 64 * 1024, 128, FL_ERASE_4K }, { "w25q32", 0xef, 0x4016, 64 * 1024, 64, FL_ERASE_4K }, { "w25q64", 0xef, 0x4017, 64 * 1024, 128, FL_ERASE_4K }, { "w25q64bv", 0xef, 0x4017, 64 * 1024, 128, FL_ERASE_4K }, { "w25q128", 0xef, 0x4018, 64 * 1024, 256, FL_ERASE_4K }, { "w25q256", 0xef, 0x4019, 64 * 1024, 512, FL_ERASE_4K }, /* Atmel */ { "at25df641", 0x1f, 0x4800, 64 * 1024, 128, FL_ERASE_4K }, /* GigaDevice */ { "gd25q64", 0xc8, 0x4017, 64 * 1024, 128, FL_ERASE_4K }, }; static uint8_t mx25l_get_status(device_t dev) { uint8_t txBuf[2], rxBuf[2]; struct spi_command cmd; int err; memset(&cmd, 0, sizeof(cmd)); memset(txBuf, 0, sizeof(txBuf)); memset(rxBuf, 0, sizeof(rxBuf)); txBuf[0] = CMD_READ_STATUS; cmd.tx_cmd = txBuf; cmd.rx_cmd = rxBuf; cmd.rx_cmd_sz = 2; cmd.tx_cmd_sz = 2; err = SPIBUS_TRANSFER(device_get_parent(dev), dev, &cmd); return (rxBuf[1]); } static void mx25l_wait_for_device_ready(device_t dev) { while ((mx25l_get_status(dev) & STATUS_WIP)) continue; } static struct mx25l_flash_ident* mx25l_get_device_ident(struct mx25l_softc *sc) { device_t dev = sc->sc_dev; uint8_t txBuf[8], rxBuf[8]; struct spi_command cmd; uint8_t manufacturer_id; uint16_t dev_id; int err, i; memset(&cmd, 0, sizeof(cmd)); memset(txBuf, 0, sizeof(txBuf)); memset(rxBuf, 0, sizeof(rxBuf)); txBuf[0] = CMD_READ_IDENT; cmd.tx_cmd = &txBuf; cmd.rx_cmd = &rxBuf; /* * Some compatible devices has extended two-bytes ID * We'll use only manufacturer/deviceid atm */ cmd.tx_cmd_sz = 4; cmd.rx_cmd_sz = 4; err = SPIBUS_TRANSFER(device_get_parent(dev), dev, &cmd); if (err) return (NULL); manufacturer_id = rxBuf[1]; dev_id = (rxBuf[2] << 8) | (rxBuf[3]); for (i = 0; i < nitems(flash_devices); i++) { if ((flash_devices[i].manufacturer_id == manufacturer_id) && (flash_devices[i].device_id == dev_id)) return &flash_devices[i]; } printf("Unknown SPI flash device. Vendor: %02x, device id: %04x\n", manufacturer_id, dev_id); return (NULL); } static void mx25l_set_writable(device_t dev, int writable) { uint8_t txBuf[1], rxBuf[1]; struct spi_command cmd; int err; memset(&cmd, 0, sizeof(cmd)); memset(txBuf, 0, sizeof(txBuf)); memset(rxBuf, 0, sizeof(rxBuf)); txBuf[0] = writable ? CMD_WRITE_ENABLE : CMD_WRITE_DISABLE; cmd.tx_cmd = txBuf; cmd.rx_cmd = rxBuf; cmd.rx_cmd_sz = 1; cmd.tx_cmd_sz = 1; err = SPIBUS_TRANSFER(device_get_parent(dev), dev, &cmd); } static void mx25l_erase_cmd(device_t dev, off_t sector, uint8_t ecmd) { struct mx25l_softc *sc; uint8_t txBuf[5], rxBuf[5]; struct spi_command cmd; int err; sc = device_get_softc(dev); mx25l_wait_for_device_ready(dev); mx25l_set_writable(dev, 1); memset(&cmd, 0, sizeof(cmd)); memset(txBuf, 0, sizeof(txBuf)); memset(rxBuf, 0, sizeof(rxBuf)); txBuf[0] = ecmd; cmd.tx_cmd = txBuf; cmd.rx_cmd = rxBuf; if (sc->sc_flags & FL_ENABLE_4B_ADDR) { cmd.rx_cmd_sz = 5; cmd.tx_cmd_sz = 5; txBuf[1] = ((sector >> 24) & 0xff); txBuf[2] = ((sector >> 16) & 0xff); txBuf[3] = ((sector >> 8) & 0xff); txBuf[4] = (sector & 0xff); } else { cmd.rx_cmd_sz = 4; cmd.tx_cmd_sz = 4; txBuf[1] = ((sector >> 16) & 0xff); txBuf[2] = ((sector >> 8) & 0xff); txBuf[3] = (sector & 0xff); } err = SPIBUS_TRANSFER(device_get_parent(dev), dev, &cmd); } static int mx25l_write(device_t dev, off_t offset, caddr_t data, off_t count) { struct mx25l_softc *sc; uint8_t txBuf[8], rxBuf[8]; struct spi_command cmd; off_t write_offset; long bytes_to_write, bytes_writen; device_t pdev; int err = 0; pdev = device_get_parent(dev); sc = device_get_softc(dev); if (sc->sc_flags & FL_ENABLE_4B_ADDR) { cmd.tx_cmd_sz = 5; cmd.rx_cmd_sz = 5; } else { cmd.tx_cmd_sz = 4; cmd.rx_cmd_sz = 4; } bytes_writen = 0; write_offset = offset; /* * Use the erase sectorsize here since blocks are fully erased * first before they're written to. */ if (count % sc->sc_sectorsize != 0 || offset % sc->sc_sectorsize != 0) return (EIO); /* * Assume here that we write per-sector only * and sector size should be 256 bytes aligned */ KASSERT(write_offset % FLASH_PAGE_SIZE == 0, ("offset for BIO_WRITE is not page size (%d bytes) aligned", FLASH_PAGE_SIZE)); /* * Maximum write size for CMD_PAGE_PROGRAM is * FLASH_PAGE_SIZE, so split data to chunks * FLASH_PAGE_SIZE bytes eash and write them * one by one */ while (bytes_writen < count) { /* * If we crossed sector boundary - erase next sector */ if (((offset + bytes_writen) % sc->sc_sectorsize) == 0) mx25l_erase_cmd(dev, offset + bytes_writen, CMD_SECTOR_ERASE); txBuf[0] = CMD_PAGE_PROGRAM; if (sc->sc_flags & FL_ENABLE_4B_ADDR) { txBuf[1] = ((write_offset >> 24) & 0xff); txBuf[2] = ((write_offset >> 16) & 0xff); txBuf[3] = ((write_offset >> 8) & 0xff); txBuf[4] = (write_offset & 0xff); } else { txBuf[1] = ((write_offset >> 16) & 0xff); txBuf[2] = ((write_offset >> 8) & 0xff); txBuf[3] = (write_offset & 0xff); } bytes_to_write = MIN(FLASH_PAGE_SIZE, count - bytes_writen); cmd.tx_cmd = txBuf; cmd.rx_cmd = rxBuf; cmd.tx_data = data + bytes_writen; cmd.tx_data_sz = bytes_to_write; cmd.rx_data = data + bytes_writen; cmd.rx_data_sz = bytes_to_write; /* * Eash completed write operation resets WEL * (write enable latch) to disabled state, * so we re-enable it here */ mx25l_wait_for_device_ready(dev); mx25l_set_writable(dev, 1); err = SPIBUS_TRANSFER(pdev, dev, &cmd); if (err) break; bytes_writen += bytes_to_write; write_offset += bytes_to_write; } return (err); } static int mx25l_read(device_t dev, off_t offset, caddr_t data, off_t count) { struct mx25l_softc *sc; uint8_t txBuf[8], rxBuf[8]; struct spi_command cmd; device_t pdev; int err = 0; pdev = device_get_parent(dev); sc = device_get_softc(dev); /* * Enforce the disk read sectorsize not the erase sectorsize. * In this way, smaller read IO is possible,dramatically * speeding up filesystem/geom_compress access. */ if (count % sc->sc_disk->d_sectorsize != 0 || offset % sc->sc_disk->d_sectorsize != 0) return (EIO); txBuf[0] = CMD_FAST_READ; if (sc->sc_flags & FL_ENABLE_4B_ADDR) { cmd.tx_cmd_sz = 6; cmd.rx_cmd_sz = 6; txBuf[1] = ((offset >> 24) & 0xff); txBuf[2] = ((offset >> 16) & 0xff); txBuf[3] = ((offset >> 8) & 0xff); txBuf[4] = (offset & 0xff); /* Dummy byte */ txBuf[5] = 0; } else { cmd.tx_cmd_sz = 5; cmd.rx_cmd_sz = 5; txBuf[1] = ((offset >> 16) & 0xff); txBuf[2] = ((offset >> 8) & 0xff); txBuf[3] = (offset & 0xff); /* Dummy byte */ txBuf[4] = 0; } cmd.tx_cmd = txBuf; cmd.rx_cmd = rxBuf; cmd.tx_data = data; cmd.tx_data_sz = count; cmd.rx_data = data; cmd.rx_data_sz = count; err = SPIBUS_TRANSFER(pdev, dev, &cmd); return (err); } static int mx25l_set_4b_mode(device_t dev, uint8_t command) { uint8_t txBuf[1], rxBuf[1]; struct spi_command cmd; device_t pdev; int err; memset(&cmd, 0, sizeof(cmd)); memset(txBuf, 0, sizeof(txBuf)); memset(rxBuf, 0, sizeof(rxBuf)); pdev = device_get_parent(dev); cmd.tx_cmd_sz = cmd.rx_cmd_sz = 1; cmd.tx_cmd = txBuf; cmd.rx_cmd = rxBuf; txBuf[0] = command; err = SPIBUS_TRANSFER(pdev, dev, &cmd); mx25l_wait_for_device_ready(dev); return (err); } #ifdef FDT static struct ofw_compat_data compat_data[] = { { "st,m25p", 1 }, { "jedec,spi-nor", 1 }, { NULL, 0 }, }; #endif static int mx25l_probe(device_t dev) { #ifdef FDT int i; if (!ofw_bus_status_okay(dev)) return (ENXIO); /* First try to match the compatible property to the compat_data */ if (ofw_bus_search_compatible(dev, compat_data)->ocd_data == 1) goto found; /* * Next, try to find a compatible device using the names in the * flash_devices structure */ for (i = 0; i < nitems(flash_devices); i++) if (ofw_bus_is_compatible(dev, flash_devices[i].name)) goto found; return (ENXIO); found: #endif device_set_desc(dev, "M25Pxx Flash Family"); return (0); } static int mx25l_attach(device_t dev) { struct mx25l_softc *sc; struct mx25l_flash_ident *ident; sc = device_get_softc(dev); sc->sc_dev = dev; M25PXX_LOCK_INIT(sc); ident = mx25l_get_device_ident(sc); if (ident == NULL) return (ENXIO); mx25l_wait_for_device_ready(sc->sc_dev); sc->sc_disk = disk_alloc(); sc->sc_disk->d_open = mx25l_open; sc->sc_disk->d_close = mx25l_close; sc->sc_disk->d_strategy = mx25l_strategy; sc->sc_disk->d_getattr = mx25l_getattr; sc->sc_disk->d_ioctl = mx25l_ioctl; sc->sc_disk->d_name = "flash/spi"; sc->sc_disk->d_drv1 = sc; sc->sc_disk->d_maxsize = DFLTPHYS; sc->sc_disk->d_sectorsize = MX25L_SECTORSIZE; sc->sc_disk->d_mediasize = ident->sectorsize * ident->sectorcount; sc->sc_disk->d_unit = device_get_unit(sc->sc_dev); sc->sc_disk->d_dump = NULL; /* NB: no dumps */ /* Sectorsize for erase operations */ sc->sc_sectorsize = ident->sectorsize; sc->sc_flags = ident->flags; if (sc->sc_flags & FL_ENABLE_4B_ADDR) mx25l_set_4b_mode(dev, CMD_ENTER_4B_MODE); if (sc->sc_flags & FL_DISABLE_4B_ADDR) mx25l_set_4b_mode(dev, CMD_EXIT_4B_MODE); /* NB: use stripesize to hold the erase/region size for RedBoot */ sc->sc_disk->d_stripesize = ident->sectorsize; disk_create(sc->sc_disk, DISK_VERSION); bioq_init(&sc->sc_bio_queue); kproc_create(&mx25l_task, sc, &sc->sc_p, 0, 0, "task: mx25l flash"); + sc->sc_taskstate = TSTATE_RUNNING; + device_printf(sc->sc_dev, "%s, sector %d bytes, %d sectors\n", ident->name, ident->sectorsize, ident->sectorcount); return (0); } static int mx25l_detach(device_t dev) { + struct mx25l_softc *sc; + int err; - return (EIO); + sc = device_get_softc(dev); + err = 0; + + M25PXX_LOCK(sc); + if (sc->sc_taskstate == TSTATE_RUNNING) { + sc->sc_taskstate = TSTATE_STOPPING; + wakeup(sc); + while (err == 0 && sc->sc_taskstate != TSTATE_STOPPED) { + err = msleep(sc, &sc->sc_mtx, 0, "mx25dt", hz * 3); + if (err != 0) { + sc->sc_taskstate = TSTATE_RUNNING; + device_printf(dev, + "Failed to stop queue task\n"); + } + } + } + M25PXX_UNLOCK(sc); + + if (err == 0 && sc->sc_taskstate == TSTATE_STOPPED) { + disk_destroy(sc->sc_disk); + bioq_flush(&sc->sc_bio_queue, NULL, ENXIO); + M25PXX_LOCK_DESTROY(sc); + } + return (err); } static int mx25l_open(struct disk *dp) { return (0); } static int mx25l_close(struct disk *dp) { return (0); } static int mx25l_ioctl(struct disk *dp, u_long cmd, void *data, int fflag, struct thread *td) { return (EINVAL); } static void mx25l_strategy(struct bio *bp) { struct mx25l_softc *sc; sc = (struct mx25l_softc *)bp->bio_disk->d_drv1; M25PXX_LOCK(sc); bioq_disksort(&sc->sc_bio_queue, bp); wakeup(sc); M25PXX_UNLOCK(sc); } static int mx25l_getattr(struct bio *bp) { struct mx25l_softc *sc; device_t dev; if (bp->bio_disk == NULL || bp->bio_disk->d_drv1 == NULL) return (ENXIO); sc = bp->bio_disk->d_drv1; dev = sc->sc_dev; if (strcmp(bp->bio_attribute, "SPI::device") == 0) { if (bp->bio_length != sizeof(dev)) return (EFAULT); bcopy(&dev, bp->bio_data, sizeof(dev)); } else return (-1); return (0); } static void mx25l_task(void *arg) { struct mx25l_softc *sc = (struct mx25l_softc*)arg; struct bio *bp; device_t dev; for (;;) { dev = sc->sc_dev; M25PXX_LOCK(sc); do { + if (sc->sc_taskstate == TSTATE_STOPPING) { + sc->sc_taskstate = TSTATE_STOPPED; + M25PXX_UNLOCK(sc); + wakeup(sc); + kproc_exit(0); + } bp = bioq_first(&sc->sc_bio_queue); if (bp == NULL) - msleep(sc, &sc->sc_mtx, PRIBIO, "jobqueue", 0); + msleep(sc, &sc->sc_mtx, PRIBIO, "mx25jq", 0); } while (bp == NULL); bioq_remove(&sc->sc_bio_queue, bp); M25PXX_UNLOCK(sc); switch (bp->bio_cmd) { case BIO_READ: bp->bio_error = mx25l_read(dev, bp->bio_offset, bp->bio_data, bp->bio_bcount); break; case BIO_WRITE: bp->bio_error = mx25l_write(dev, bp->bio_offset, bp->bio_data, bp->bio_bcount); break; default: bp->bio_error = EINVAL; } biodone(bp); } } static devclass_t mx25l_devclass; static device_method_t mx25l_methods[] = { /* Device interface */ DEVMETHOD(device_probe, mx25l_probe), DEVMETHOD(device_attach, mx25l_attach), DEVMETHOD(device_detach, mx25l_detach), { 0, 0 } }; static driver_t mx25l_driver = { "mx25l", mx25l_methods, sizeof(struct mx25l_softc), }; DRIVER_MODULE(mx25l, spibus, mx25l_driver, mx25l_devclass, 0, 0); +MODULE_DEPEND(mx25l, spibus, 1, 1, 1); Index: stable/11/sys/dev/spibus/ofw_spibus.c =================================================================== --- stable/11/sys/dev/spibus/ofw_spibus.c (revision 331505) +++ stable/11/sys/dev/spibus/ofw_spibus.c (revision 331506) @@ -1,203 +1,223 @@ /*- - * SPDX-License-Identifier: BSD-4-Clause-FreeBSD + * SPDX-License-Identifier: BSD-2-Clause-FreeBSD * * Copyright (c) 2009, Nathan Whitehorn * Copyright (c) 2013 The FreeBSD Foundation * All rights reserved. * * Portions of this software were developed by Oleksandr Rybalko * under sponsorship from the FreeBSD Foundation. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice unmodified, this list of conditions, and the following * disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ #include __FBSDID("$FreeBSD$"); #include #include #include #include #include #include #include #include #include #include #include #include #include #include "spibus_if.h" struct ofw_spibus_devinfo { struct spibus_ivar opd_dinfo; struct ofw_bus_devinfo opd_obdinfo; }; /* Methods */ static device_probe_t ofw_spibus_probe; static device_attach_t ofw_spibus_attach; static device_t ofw_spibus_add_child(device_t dev, u_int order, const char *name, int unit); static const struct ofw_bus_devinfo *ofw_spibus_get_devinfo(device_t bus, device_t dev); static int ofw_spibus_probe(device_t dev) { if (ofw_bus_get_node(dev) == -1) return (ENXIO); device_set_desc(dev, "OFW SPI bus"); return (0); } static int ofw_spibus_attach(device_t dev) { struct spibus_softc *sc = device_get_softc(dev); struct ofw_spibus_devinfo *dinfo; phandle_t child; pcell_t clock, paddr; device_t childdev; + uint32_t mode = SPIBUS_MODE_NONE; sc->dev = dev; bus_generic_probe(dev); bus_enumerate_hinted_children(dev); /* * Attach those children represented in the device tree. */ for (child = OF_child(ofw_bus_get_node(dev)); child != 0; child = OF_peer(child)) { /* * Try to get the CS number first from the spi-chipselect * property, then try the reg property. */ if (OF_getencprop(child, "spi-chipselect", &paddr, sizeof(paddr)) == -1) { if (OF_getencprop(child, "reg", &paddr, sizeof(paddr)) == -1) continue; } /* + * Try to get the cpol/cpha mode + */ + if (OF_hasprop(child, "spi-cpol")) + mode = SPIBUS_MODE_CPOL; + if (OF_hasprop(child, "spi-cpha")) { + if (mode == SPIBUS_MODE_CPOL) + mode = SPIBUS_MODE_CPOL_CPHA; + else + mode = SPIBUS_MODE_CPHA; + } + + /* + * Try to get the CS polarity + */ + if (OF_hasprop(child, "spi-cs-high")) + paddr |= SPIBUS_CS_HIGH; + + /* * Get the maximum clock frequency for device, zero means * use the default bus speed. */ if (OF_getencprop(child, "spi-max-frequency", &clock, sizeof(clock)) == -1) clock = 0; /* * Now set up the SPI and OFW bus layer devinfo and add it * to the bus. */ dinfo = malloc(sizeof(struct ofw_spibus_devinfo), M_DEVBUF, M_NOWAIT | M_ZERO); if (dinfo == NULL) continue; dinfo->opd_dinfo.cs = paddr; dinfo->opd_dinfo.clock = clock; + dinfo->opd_dinfo.mode = mode; if (ofw_bus_gen_setup_devinfo(&dinfo->opd_obdinfo, child) != 0) { free(dinfo, M_DEVBUF); continue; } childdev = device_add_child(dev, NULL, -1); device_set_ivars(childdev, dinfo); } return (bus_generic_attach(dev)); } static device_t ofw_spibus_add_child(device_t dev, u_int order, const char *name, int unit) { device_t child; struct ofw_spibus_devinfo *devi; child = device_add_child_ordered(dev, order, name, unit); if (child == NULL) return (child); devi = malloc(sizeof(struct ofw_spibus_devinfo), M_DEVBUF, M_NOWAIT | M_ZERO); if (devi == NULL) { device_delete_child(dev, child); return (0); } /* * NULL all the OFW-related parts of the ivars for non-OFW * children. */ devi->opd_obdinfo.obd_node = -1; devi->opd_obdinfo.obd_name = NULL; devi->opd_obdinfo.obd_compat = NULL; devi->opd_obdinfo.obd_type = NULL; devi->opd_obdinfo.obd_model = NULL; device_set_ivars(child, devi); return (child); } static const struct ofw_bus_devinfo * ofw_spibus_get_devinfo(device_t bus, device_t dev) { struct ofw_spibus_devinfo *dinfo; dinfo = device_get_ivars(dev); return (&dinfo->opd_obdinfo); } static device_method_t ofw_spibus_methods[] = { /* Device interface */ DEVMETHOD(device_probe, ofw_spibus_probe), DEVMETHOD(device_attach, ofw_spibus_attach), /* Bus interface */ DEVMETHOD(bus_child_pnpinfo_str, ofw_bus_gen_child_pnpinfo_str), DEVMETHOD(bus_add_child, ofw_spibus_add_child), /* ofw_bus interface */ DEVMETHOD(ofw_bus_get_devinfo, ofw_spibus_get_devinfo), DEVMETHOD(ofw_bus_get_compat, ofw_bus_gen_get_compat), DEVMETHOD(ofw_bus_get_model, ofw_bus_gen_get_model), DEVMETHOD(ofw_bus_get_name, ofw_bus_gen_get_name), DEVMETHOD(ofw_bus_get_node, ofw_bus_gen_get_node), DEVMETHOD(ofw_bus_get_type, ofw_bus_gen_get_type), DEVMETHOD_END }; -static devclass_t ofwspibus_devclass; +devclass_t ofw_spibus_devclass; DEFINE_CLASS_1(spibus, ofw_spibus_driver, ofw_spibus_methods, sizeof(struct spibus_softc), spibus_driver); -DRIVER_MODULE(ofw_spibus, spi, ofw_spibus_driver, ofwspibus_devclass, 0, 0); +DRIVER_MODULE(ofw_spibus, spi, ofw_spibus_driver, ofw_spibus_devclass, 0, 0); MODULE_VERSION(ofw_spibus, 1); MODULE_DEPEND(ofw_spibus, spibus, 1, 1, 1); Index: stable/11/sys/dev/spibus/spibusvar.h =================================================================== --- stable/11/sys/dev/spibus/spibusvar.h (revision 331505) +++ stable/11/sys/dev/spibus/spibusvar.h (revision 331506) @@ -1,68 +1,72 @@ /*- * Copyright (c) 2006 M. Warner Losh * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. * * $FreeBSD$ */ #define SPIBUS_IVAR(d) (struct spibus_ivar *) device_get_ivars(d) #define SPIBUS_SOFTC(d) (struct spibus_softc *) device_get_softc(d) struct spibus_softc { device_t dev; }; #define SPIBUS_MODE_NONE 0 #define SPIBUS_MODE_CPHA 1 #define SPIBUS_MODE_CPOL 2 #define SPIBUS_MODE_CPOL_CPHA 3 struct spibus_ivar { uint32_t cs; uint32_t mode; uint32_t clock; }; +#define SPIBUS_CS_HIGH (1U << 31) + enum { SPIBUS_IVAR_CS, /* chip select that we're on */ SPIBUS_IVAR_MODE, /* SPI mode (0-3) */ SPIBUS_IVAR_CLOCK, /* maximum clock freq for device */ }; #define SPIBUS_ACCESSOR(A, B, T) \ static inline int \ spibus_get_ ## A(device_t dev, T *t) \ { \ return BUS_READ_IVAR(device_get_parent(dev), dev, \ SPIBUS_IVAR_ ## B, (uintptr_t *) t); \ } SPIBUS_ACCESSOR(cs, CS, uint32_t) SPIBUS_ACCESSOR(mode, MODE, uint32_t) SPIBUS_ACCESSOR(clock, CLOCK, uint32_t) extern driver_t spibus_driver; extern devclass_t spibus_devclass; +extern driver_t ofw_spibus_driver; +extern devclass_t ofw_spibus_devclass; Index: stable/11/sys/dev/xilinx/axi_quad_spi.c =================================================================== --- stable/11/sys/dev/xilinx/axi_quad_spi.c (revision 331505) +++ stable/11/sys/dev/xilinx/axi_quad_spi.c (revision 331506) @@ -1,233 +1,235 @@ /*- * Copyright (c) 2016 Ruslan Bukin * All rights reserved. * * Portions of this software were developed by SRI International and the * University of Cambridge Computer Laboratory under DARPA/AFRL contract * FA8750-10-C-0237 ("CTSRD"), as part of the DARPA CRASH research programme. * * Portions of this software were developed by the University of Cambridge * Computer Laboratory as part of the CTSRD Project, with support from the * UK Higher Education Innovation Fund (HEIF). * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. */ /* * Xilinx AXI_QUAD_SPI */ #include __FBSDID("$FreeBSD$"); #include #include #include #include #include #include #include #include #include #include #include #include #include "spibus_if.h" #include #include #include #include #include #include #include #define READ4(_sc, _reg) \ bus_space_read_4(_sc->bst, _sc->bsh, _reg) #define WRITE4(_sc, _reg, _val) \ bus_space_write_4(_sc->bst, _sc->bsh, _reg, _val) #define SPI_SRR 0x40 /* Software reset register */ #define SRR_RESET 0x0A /* The only reset value */ #define SPI_CR 0x60 /* Control register */ #define CR_LSB_FIRST (1 << 9) /* LSB first */ #define CR_MASTER_TI (1 << 8) /* Master Transaction Inhibit */ #define CR_MSS (1 << 7) /* Manual Slave Select */ #define CR_RST_RX (1 << 6) /* RX FIFO Reset */ #define CR_RST_TX (1 << 5) /* TX FIFO Reset */ #define CR_CPHA (1 << 4) /* Clock phase */ #define CR_CPOL (1 << 3) /* Clock polarity */ #define CR_MASTER (1 << 2) /* Master (SPI master mode) */ #define CR_SPE (1 << 1) /* SPI system enable */ #define CR_LOOP (1 << 0) /* Local loopback mode */ #define SPI_SR 0x64 /* Status register */ #define SR_TX_FULL (1 << 3) /* Transmit full */ #define SR_TX_EMPTY (1 << 2) /* Transmit empty */ #define SR_RX_FULL (1 << 1) /* Receive full */ #define SR_RX_EMPTY (1 << 0) /* Receive empty */ #define SPI_DTR 0x68 /* Data transmit register */ #define SPI_DRR 0x6C /* Data receive register */ #define SPI_SSR 0x70 /* Slave select register */ #define SPI_TFOR 0x74 /* Transmit FIFO Occupancy Register */ #define SPI_RFOR 0x78 /* Receive FIFO Occupancy Register */ #define SPI_DGIER 0x1C /* Device global interrupt enable register */ #define SPI_IPISR 0x20 /* IP interrupt status register */ #define SPI_IPIER 0x28 /* IP interrupt enable register */ struct spi_softc { struct resource *res[1]; bus_space_tag_t bst; bus_space_handle_t bsh; void *ih; }; static struct resource_spec spi_spec[] = { { SYS_RES_MEMORY, 0, RF_ACTIVE }, { -1, 0 } }; static int spi_probe(device_t dev) { if (!ofw_bus_status_okay(dev)) return (ENXIO); if (!ofw_bus_is_compatible(dev, "xlnx,xps-spi-3.2")) return (ENXIO); device_set_desc(dev, "Xilinx Quad SPI"); return (BUS_PROBE_DEFAULT); } static int spi_attach(device_t dev) { struct spi_softc *sc; uint32_t reg; sc = device_get_softc(dev); if (bus_alloc_resources(dev, spi_spec, sc->res)) { device_printf(dev, "could not allocate resources\n"); return (ENXIO); } /* Memory interface */ sc->bst = rman_get_bustag(sc->res[0]); sc->bsh = rman_get_bushandle(sc->res[0]); /* Reset */ WRITE4(sc, SPI_SRR, SRR_RESET); DELAY(1000); reg = (CR_MASTER | CR_MSS | CR_RST_RX | CR_RST_TX); WRITE4(sc, SPI_CR, reg); WRITE4(sc, SPI_DGIER, 0); /* Disable interrupts */ reg = (CR_MASTER | CR_MSS | CR_SPE); WRITE4(sc, SPI_CR, reg); device_add_child(dev, "spibus", 0); return (bus_generic_attach(dev)); } static int spi_txrx(struct spi_softc *sc, uint8_t *out_buf, uint8_t *in_buf, int bufsz, int cs) { uint32_t data; uint32_t i; for (i = 0; i < bufsz; i++) { WRITE4(sc, SPI_DTR, out_buf[i]); while(!(READ4(sc, SPI_SR) & SR_TX_EMPTY)) continue; data = READ4(sc, SPI_DRR); if (in_buf) in_buf[i] = (data & 0xff); } return (0); } static int spi_transfer(device_t dev, device_t child, struct spi_command *cmd) { struct spi_softc *sc; uint32_t reg; uint32_t cs; sc = device_get_softc(dev); KASSERT(cmd->tx_cmd_sz == cmd->rx_cmd_sz, ("%s: TX/RX command sizes should be equal", __func__)); KASSERT(cmd->tx_data_sz == cmd->rx_data_sz, ("%s: TX/RX data sizes should be equal", __func__)); /* get the proper chip select */ spibus_get_cs(child, &cs); + cs &= ~SPIBUS_CS_HIGH; + /* Assert CS */ reg = READ4(sc, SPI_SSR); reg &= ~(1 << cs); WRITE4(sc, SPI_SSR, reg); /* Command */ spi_txrx(sc, cmd->tx_cmd, cmd->rx_cmd, cmd->tx_cmd_sz, cs); /* Data */ spi_txrx(sc, cmd->tx_data, cmd->rx_data, cmd->tx_data_sz, cs); /* Deassert CS */ reg = READ4(sc, SPI_SSR); reg |= (1 << cs); WRITE4(sc, SPI_SSR, reg); return (0); } static device_method_t spi_methods[] = { /* Device interface */ DEVMETHOD(device_probe, spi_probe), DEVMETHOD(device_attach, spi_attach), /* SPI interface */ DEVMETHOD(spibus_transfer, spi_transfer), DEVMETHOD_END }; static driver_t spi_driver = { "spi", spi_methods, sizeof(struct spi_softc), }; static devclass_t spi_devclass; DRIVER_MODULE(spi, simplebus, spi_driver, spi_devclass, 0, 0); Index: stable/11/sys/mips/atheros/ar71xx_spi.c =================================================================== --- stable/11/sys/mips/atheros/ar71xx_spi.c (revision 331505) +++ stable/11/sys/mips/atheros/ar71xx_spi.c (revision 331506) @@ -1,295 +1,297 @@ /*- * SPDX-License-Identifier: BSD-2-Clause-FreeBSD * * Copyright (c) 2009, Oleksandr Tymoshenko * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice unmodified, this list of conditions, and the following * disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. */ #include __FBSDID("$FreeBSD$"); #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include "spibus_if.h" #include #undef AR71XX_SPI_DEBUG #ifdef AR71XX_SPI_DEBUG #define dprintf printf #else #define dprintf(x, arg...) #endif /* * register space access macros */ #define SPI_BARRIER_WRITE(sc) bus_barrier((sc)->sc_mem_res, 0, 0, \ BUS_SPACE_BARRIER_WRITE) #define SPI_BARRIER_READ(sc) bus_barrier((sc)->sc_mem_res, 0, 0, \ BUS_SPACE_BARRIER_READ) #define SPI_BARRIER_RW(sc) bus_barrier((sc)->sc_mem_res, 0, 0, \ BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE) #define SPI_WRITE(sc, reg, val) do { \ bus_write_4(sc->sc_mem_res, (reg), (val)); \ } while (0) #define SPI_READ(sc, reg) bus_read_4(sc->sc_mem_res, (reg)) #define SPI_SET_BITS(sc, reg, bits) \ SPI_WRITE(sc, reg, SPI_READ(sc, (reg)) | (bits)) #define SPI_CLEAR_BITS(sc, reg, bits) \ SPI_WRITE(sc, reg, SPI_READ(sc, (reg)) & ~(bits)) struct ar71xx_spi_softc { device_t sc_dev; struct resource *sc_mem_res; uint32_t sc_reg_ctrl; }; static int ar71xx_spi_probe(device_t dev) { device_set_desc(dev, "AR71XX SPI"); return (BUS_PROBE_NOWILDCARD); } static int ar71xx_spi_attach(device_t dev) { struct ar71xx_spi_softc *sc = device_get_softc(dev); int rid; sc->sc_dev = dev; rid = 0; sc->sc_mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, RF_ACTIVE); if (!sc->sc_mem_res) { device_printf(dev, "Could not map memory\n"); return (ENXIO); } SPI_WRITE(sc, AR71XX_SPI_FS, 1); /* Flush out read before reading the control register */ SPI_BARRIER_WRITE(sc); sc->sc_reg_ctrl = SPI_READ(sc, AR71XX_SPI_CTRL); /* * XXX TODO: document what the SPI control register does. */ SPI_WRITE(sc, AR71XX_SPI_CTRL, 0x43); /* * Ensure the config register write has gone out before configuring * the chip select mask. */ SPI_BARRIER_WRITE(sc); SPI_WRITE(sc, AR71XX_SPI_IO_CTRL, SPI_IO_CTRL_CSMASK); /* * .. and ensure the write has gone out before continuing. */ SPI_BARRIER_WRITE(sc); device_add_child(dev, "spibus", -1); return (bus_generic_attach(dev)); } static void ar71xx_spi_chip_activate(struct ar71xx_spi_softc *sc, int cs) { uint32_t ioctrl = SPI_IO_CTRL_CSMASK; /* * Put respective CSx to low */ ioctrl &= ~(SPI_IO_CTRL_CS0 << cs); /* * Make sure any other writes have gone out to the * device before changing the chip select line; * then ensure that it has made it out to the device * before continuing. */ SPI_BARRIER_WRITE(sc); SPI_WRITE(sc, AR71XX_SPI_IO_CTRL, ioctrl); SPI_BARRIER_WRITE(sc); } static void ar71xx_spi_chip_deactivate(struct ar71xx_spi_softc *sc, int cs) { /* * Put all CSx to high */ SPI_WRITE(sc, AR71XX_SPI_IO_CTRL, SPI_IO_CTRL_CSMASK); } static uint8_t ar71xx_spi_txrx(struct ar71xx_spi_softc *sc, int cs, uint8_t data) { int bit; /* CS0 */ uint32_t ioctrl = SPI_IO_CTRL_CSMASK; /* * low-level for selected CS */ ioctrl &= ~(SPI_IO_CTRL_CS0 << cs); uint32_t iod, rds; for (bit = 7; bit >=0; bit--) { if (data & (1 << bit)) iod = ioctrl | SPI_IO_CTRL_DO; else iod = ioctrl & ~SPI_IO_CTRL_DO; SPI_BARRIER_WRITE(sc); SPI_WRITE(sc, AR71XX_SPI_IO_CTRL, iod); SPI_BARRIER_WRITE(sc); SPI_WRITE(sc, AR71XX_SPI_IO_CTRL, iod | SPI_IO_CTRL_CLK); } /* * Provide falling edge for connected device by clear clock bit. */ SPI_BARRIER_WRITE(sc); SPI_WRITE(sc, AR71XX_SPI_IO_CTRL, iod); SPI_BARRIER_WRITE(sc); rds = SPI_READ(sc, AR71XX_SPI_RDS); return (rds & 0xff); } static int ar71xx_spi_transfer(device_t dev, device_t child, struct spi_command *cmd) { struct ar71xx_spi_softc *sc; uint32_t cs; uint8_t *buf_in, *buf_out; int i; sc = device_get_softc(dev); spibus_get_cs(child, &cs); + cs &= ~SPIBUS_CS_HIGH; + ar71xx_spi_chip_activate(sc, cs); KASSERT(cmd->tx_cmd_sz == cmd->rx_cmd_sz, ("TX/RX command sizes should be equal")); KASSERT(cmd->tx_data_sz == cmd->rx_data_sz, ("TX/RX data sizes should be equal")); /* * Transfer command */ buf_out = (uint8_t *)cmd->tx_cmd; buf_in = (uint8_t *)cmd->rx_cmd; for (i = 0; i < cmd->tx_cmd_sz; i++) buf_in[i] = ar71xx_spi_txrx(sc, cs, buf_out[i]); /* * Receive/transmit data (depends on command) */ buf_out = (uint8_t *)cmd->tx_data; buf_in = (uint8_t *)cmd->rx_data; for (i = 0; i < cmd->tx_data_sz; i++) buf_in[i] = ar71xx_spi_txrx(sc, cs, buf_out[i]); ar71xx_spi_chip_deactivate(sc, cs); return (0); } static int ar71xx_spi_detach(device_t dev) { struct ar71xx_spi_softc *sc = device_get_softc(dev); /* * Ensure any other writes to the device are finished * before we tear down the SPI device. */ SPI_BARRIER_WRITE(sc); /* * Restore the control register; ensure it has hit the * hardware before continuing. */ SPI_WRITE(sc, AR71XX_SPI_CTRL, sc->sc_reg_ctrl); SPI_BARRIER_WRITE(sc); /* * And now, put the flash back into mapped IO mode and * ensure _that_ has completed before we finish up. */ SPI_WRITE(sc, AR71XX_SPI_FS, 0); SPI_BARRIER_WRITE(sc); if (sc->sc_mem_res) bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->sc_mem_res); return (0); } static device_method_t ar71xx_spi_methods[] = { /* Device interface */ DEVMETHOD(device_probe, ar71xx_spi_probe), DEVMETHOD(device_attach, ar71xx_spi_attach), DEVMETHOD(device_detach, ar71xx_spi_detach), DEVMETHOD(spibus_transfer, ar71xx_spi_transfer), {0, 0} }; static driver_t ar71xx_spi_driver = { "spi", ar71xx_spi_methods, sizeof(struct ar71xx_spi_softc), }; static devclass_t ar71xx_spi_devclass; DRIVER_MODULE(ar71xx_spi, nexus, ar71xx_spi_driver, ar71xx_spi_devclass, 0, 0); Index: stable/11/sys/mips/mediatek/mtk_spi_v1.c =================================================================== --- stable/11/sys/mips/mediatek/mtk_spi_v1.c (revision 331505) +++ stable/11/sys/mips/mediatek/mtk_spi_v1.c (revision 331506) @@ -1,348 +1,350 @@ /*- * Copyright (c) 2009, Oleksandr Tymoshenko * Copyright (c) 2011, Aleksandr Rybalko * Copyright (c) 2013, Alexander A. Mityaev * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice unmodified, this list of conditions, and the following * disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. */ #include __FBSDID("$FreeBSD$"); #include #include #include #include #include #include #include #include #include #include #include #include #include "spibus_if.h" #include "opt_platform.h" #include #include #include #include #include #undef MTK_SPI_DEBUG #ifdef MTK_SPI_DEBUG #define dprintf printf #else #define dprintf(x, arg...) #endif /* * register space access macros */ #define SPI_WRITE(sc, reg, val) do { \ bus_write_4(sc->sc_mem_res, (reg), (val)); \ } while (0) #define SPI_READ(sc, reg) bus_read_4(sc->sc_mem_res, (reg)) #define SPI_SET_BITS(sc, reg, bits) \ SPI_WRITE(sc, reg, SPI_READ(sc, (reg)) | (bits)) #define SPI_CLEAR_BITS(sc, reg, bits) \ SPI_WRITE(sc, reg, SPI_READ(sc, (reg)) & ~(bits)) struct mtk_spi_softc { device_t sc_dev; struct resource *sc_mem_res; }; static int mtk_spi_probe(device_t); static int mtk_spi_attach(device_t); static int mtk_spi_detach(device_t); static int mtk_spi_wait(struct mtk_spi_softc *); static void mtk_spi_chip_activate(struct mtk_spi_softc *); static void mtk_spi_chip_deactivate(struct mtk_spi_softc *); static uint8_t mtk_spi_txrx(struct mtk_spi_softc *, uint8_t *, int); static int mtk_spi_transfer(device_t, device_t, struct spi_command *); static phandle_t mtk_spi_get_node(device_t, device_t); static struct ofw_compat_data compat_data[] = { { "ralink,rt2880-spi", 1 }, { "ralink,rt3050-spi", 1 }, { "ralink,rt3352-spi", 1 }, { "ralink,rt3883-spi", 1 }, { "ralink,rt5350-spi", 1 }, { "ralink,mt7620a-spi", 1 }, { NULL, 0 } }; static int mtk_spi_probe(device_t dev) { if (!ofw_bus_status_okay(dev)) return (ENXIO); if (ofw_bus_search_compatible(dev, compat_data)->ocd_data == 0) return(ENXIO); device_set_desc(dev, "MTK SPI Controller (v1)"); return (0); } static int mtk_spi_attach(device_t dev) { struct mtk_spi_softc *sc = device_get_softc(dev); int rid; sc->sc_dev = dev; rid = 0; sc->sc_mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, RF_ACTIVE); if (!sc->sc_mem_res) { device_printf(dev, "Could not map memory\n"); return (ENXIO); } if (mtk_spi_wait(sc)) { bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->sc_mem_res); return (EBUSY); } SPI_WRITE(sc, MTK_SPICFG, MSBFIRST | SPICLKPOL | TX_ON_CLK_FALL | SPI_CLK_DIV8); /* XXX: make it configurable */ /* * W25Q64CV max 104MHz, bus 120-192 MHz, so divide by 2. * Update: divide by 4, DEV2 to fast for flash. */ device_add_child(dev, "spibus", 0); return (bus_generic_attach(dev)); } static int mtk_spi_detach(device_t dev) { struct mtk_spi_softc *sc = device_get_softc(dev); SPI_SET_BITS(sc, MTK_SPICTL, HIZSMOSI | CS_HIGH); if (sc->sc_mem_res) bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->sc_mem_res); return (0); } static void mtk_spi_chip_activate(struct mtk_spi_softc *sc) { mtk_spi_wait(sc); /* * Put all CSx to low */ SPI_CLEAR_BITS(sc, MTK_SPICTL, CS_HIGH | HIZSMOSI); } static void mtk_spi_chip_deactivate(struct mtk_spi_softc *sc) { mtk_spi_wait(sc); /* * Put all CSx to high */ SPI_SET_BITS(sc, MTK_SPICTL, CS_HIGH | HIZSMOSI); } static int mtk_spi_wait(struct mtk_spi_softc *sc) { int i = 1000; while (i--) { if (!SPI_READ(sc, MTK_SPIBUSY)) break; } if (i == 0) { printf("busy\n"); return (1); } return (0); } static uint8_t mtk_spi_txrx(struct mtk_spi_softc *sc, uint8_t *data, int write) { if (mtk_spi_wait(sc)) return (EBUSY); if (write == MTK_SPI_WRITE) { SPI_WRITE(sc, MTK_SPIDATA, *data); SPI_SET_BITS(sc, MTK_SPICTL, START_WRITE); } else {/* MTK_SPI_READ */ SPI_SET_BITS(sc, MTK_SPICTL, START_READ); if (mtk_spi_wait(sc)) return (EBUSY); *data = SPI_READ(sc, MTK_SPIDATA) & 0xff; } return (0); } static int mtk_spi_transfer(device_t dev, device_t child, struct spi_command *cmd) { struct mtk_spi_softc *sc; uint8_t *buf, byte, *tx_buf; uint32_t cs; int i, sz, error = 0, write = 0; sc = device_get_softc(dev); spibus_get_cs(child, &cs); + cs &= ~SPIBUS_CS_HIGH; + if (cs != 0) /* Only 1 CS */ return (ENXIO); /* There is always a command to transfer. */ tx_buf = (uint8_t *)(cmd->tx_cmd); /* Perform some fixup because MTK dont support duplex SPI */ switch(tx_buf[0]) { case CMD_READ_IDENT: cmd->tx_cmd_sz = 1; cmd->rx_cmd_sz = 3; break; case CMD_ENTER_4B_MODE: case CMD_EXIT_4B_MODE: case CMD_WRITE_ENABLE: case CMD_WRITE_DISABLE: cmd->tx_cmd_sz = 1; cmd->rx_cmd_sz = 0; break; case CMD_READ_STATUS: cmd->tx_cmd_sz = 1; cmd->rx_cmd_sz = 1; break; case CMD_READ: case CMD_FAST_READ: cmd->rx_cmd_sz = cmd->tx_data_sz = 0; break; case CMD_SECTOR_ERASE: cmd->rx_cmd_sz = 0; break; case CMD_PAGE_PROGRAM: cmd->rx_cmd_sz = cmd->rx_data_sz = 0; break; } mtk_spi_chip_activate(sc); if (cmd->tx_cmd_sz + cmd->rx_cmd_sz) { buf = (uint8_t *)(cmd->rx_cmd); tx_buf = (uint8_t *)(cmd->tx_cmd); sz = cmd->tx_cmd_sz + cmd->rx_cmd_sz; for (i = 0; i < sz; i++) { if(i < cmd->tx_cmd_sz) { byte = tx_buf[i]; error = mtk_spi_txrx(sc, &byte, MTK_SPI_WRITE); if (error) goto mtk_spi_transfer_fail; continue; } error = mtk_spi_txrx(sc, &byte, MTK_SPI_READ); if (error) goto mtk_spi_transfer_fail; buf[i] = byte; } } /* * Transfer/Receive data */ if (cmd->tx_data_sz + cmd->rx_data_sz) { write = (cmd->tx_data_sz > 0)?1:0; buf = (uint8_t *)(write ? cmd->tx_data : cmd->rx_data); sz = write ? cmd->tx_data_sz : cmd->rx_data_sz; for (i = 0; i < sz; i++) { byte = buf[i]; error = mtk_spi_txrx(sc, &byte, write ? MTK_SPI_WRITE : MTK_SPI_READ); if (error) goto mtk_spi_transfer_fail; buf[i] = byte; } } mtk_spi_transfer_fail: mtk_spi_chip_deactivate(sc); return (error); } static phandle_t mtk_spi_get_node(device_t bus, device_t dev) { /* We only have one child, the SPI bus, which needs our own node. */ return (ofw_bus_get_node(bus)); } static device_method_t mtk_spi_methods[] = { /* Device interface */ DEVMETHOD(device_probe, mtk_spi_probe), DEVMETHOD(device_attach, mtk_spi_attach), DEVMETHOD(device_detach, mtk_spi_detach), DEVMETHOD(spibus_transfer, mtk_spi_transfer), /* ofw_bus interface */ DEVMETHOD(ofw_bus_get_node, mtk_spi_get_node), DEVMETHOD_END }; static driver_t mtk_spi_driver = { .name = "spi", .methods = mtk_spi_methods, .size = sizeof(struct mtk_spi_softc), }; static devclass_t mtk_spi_devclass; DRIVER_MODULE(mtk_spi_v1, simplebus, mtk_spi_driver, mtk_spi_devclass, 0, 0); Index: stable/11/sys/mips/mediatek/mtk_spi_v2.c =================================================================== --- stable/11/sys/mips/mediatek/mtk_spi_v2.c (revision 331505) +++ stable/11/sys/mips/mediatek/mtk_spi_v2.c (revision 331506) @@ -1,353 +1,355 @@ /*- * Copyright (c) 2009, Oleksandr Tymoshenko * Copyright (c) 2011, Aleksandr Rybalko * Copyright (c) 2013, Alexander A. Mityaev * Copyright (c) 2016, Stanislav Galabov * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice unmodified, this list of conditions, and the following * disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. */ #include __FBSDID("$FreeBSD$"); #include #include #include #include #include #include #include #include #include #include #include #include #include "spibus_if.h" #include "opt_platform.h" #include #include #include #include #include #undef MTK_SPI_DEBUG #ifdef MTK_SPI_DEBUG #define dprintf printf #else #define dprintf(x, arg...) #endif /* * register space access macros */ #define SPI_WRITE(sc, reg, val) do { \ bus_write_4(sc->sc_mem_res, (reg), (val)); \ } while (0) #define SPI_READ(sc, reg) bus_read_4(sc->sc_mem_res, (reg)) #define SPI_SET_BITS(sc, reg, bits) \ SPI_WRITE(sc, reg, SPI_READ(sc, (reg)) | (bits)) #define SPI_CLEAR_BITS(sc, reg, bits) \ SPI_WRITE(sc, reg, SPI_READ(sc, (reg)) & ~(bits)) struct mtk_spi_softc { device_t sc_dev; struct resource *sc_mem_res; }; static int mtk_spi_probe(device_t); static int mtk_spi_attach(device_t); static int mtk_spi_detach(device_t); static int mtk_spi_wait(struct mtk_spi_softc *); static void mtk_spi_chip_activate(struct mtk_spi_softc *); static void mtk_spi_chip_deactivate(struct mtk_spi_softc *); static uint8_t mtk_spi_txrx(struct mtk_spi_softc *, uint8_t *, int); static int mtk_spi_transfer(device_t, device_t, struct spi_command *); static phandle_t mtk_spi_get_node(device_t, device_t); static struct ofw_compat_data compat_data[] = { { "ralink,mt7621-spi", 1 }, { "ralink,mtk7628an-spi", 1 }, { NULL, 0 } }; static int mtk_spi_probe(device_t dev) { if (!ofw_bus_status_okay(dev)) return (ENXIO); if (ofw_bus_search_compatible(dev, compat_data)->ocd_data == 0) return(ENXIO); device_set_desc(dev, "MTK SPI Controller (v2)"); return (0); } static int mtk_spi_attach(device_t dev) { struct mtk_spi_softc *sc = device_get_softc(dev); uint32_t val; int rid; sc->sc_dev = dev; rid = 0; sc->sc_mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, RF_ACTIVE); if (!sc->sc_mem_res) { device_printf(dev, "Could not map memory\n"); return (ENXIO); } if (mtk_spi_wait(sc)) { bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->sc_mem_res); return (EBUSY); } val = SPI_READ(sc, MTK_SPIMASTER); val &= ~(0xfff << 16); val |= 13 << 16; val |= 7 << 29; val |= 1 << 2; SPI_WRITE(sc, MTK_SPIMASTER, val); /* * W25Q64CV max 104MHz, bus 120-192 MHz, so divide by 2. * Update: divide by 4, DEV2 to fast for flash. */ device_add_child(dev, "spibus", 0); return (bus_generic_attach(dev)); } static int mtk_spi_detach(device_t dev) { struct mtk_spi_softc *sc = device_get_softc(dev); if (sc->sc_mem_res) bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->sc_mem_res); return (0); } static void mtk_spi_chip_activate(struct mtk_spi_softc *sc) { mtk_spi_wait(sc); /* * Put all CSx to low */ SPI_SET_BITS(sc, MTK_SPIPOLAR, 1); } static void mtk_spi_chip_deactivate(struct mtk_spi_softc *sc) { mtk_spi_wait(sc); /* * Put all CSx to high */ SPI_CLEAR_BITS(sc, MTK_SPIPOLAR, 1); } static int mtk_spi_wait(struct mtk_spi_softc *sc) { int i = 1000; while (i--) { if (!(SPI_READ(sc, MTK_SPITRANS) & SPIBUSY)) break; } if (i == 0) { return (1); } return (0); } static uint8_t mtk_spi_txrx(struct mtk_spi_softc *sc, uint8_t *data, int write) { if (mtk_spi_wait(sc)) return (0xff); if (write == MTK_SPI_WRITE) { SPI_WRITE(sc, MTK_SPIOPCODE, (*data)); SPI_WRITE(sc, MTK_SPIMOREBUF, (8<<24)); } else { SPI_WRITE(sc, MTK_SPIMOREBUF, (8<<12)); } SPI_SET_BITS(sc, MTK_SPITRANS, SPISTART); if (mtk_spi_wait(sc)) return (0xff); if (write == MTK_SPI_READ) { *data = SPI_READ(sc, MTK_SPIDATA) & 0xff; } return (0); } static int mtk_spi_transfer(device_t dev, device_t child, struct spi_command *cmd) { struct mtk_spi_softc *sc; uint8_t *buf, byte, *tx_buf; uint32_t cs; int i, sz, error, write = 0; sc = device_get_softc(dev); spibus_get_cs(child, &cs); + cs &= ~SPIBUS_CS_HIGH; + if (cs != 0) /* Only 1 CS */ return (ENXIO); /* There is always a command to transfer. */ tx_buf = (uint8_t *)(cmd->tx_cmd); /* Perform some fixup because MTK dont support duplex SPI */ switch(tx_buf[0]) { case CMD_READ_IDENT: cmd->tx_cmd_sz = 1; cmd->rx_cmd_sz = 3; break; case CMD_ENTER_4B_MODE: case CMD_EXIT_4B_MODE: case CMD_WRITE_ENABLE: case CMD_WRITE_DISABLE: cmd->tx_cmd_sz = 1; cmd->rx_cmd_sz = 0; break; case CMD_READ_STATUS: cmd->tx_cmd_sz = 1; cmd->rx_cmd_sz = 1; break; case CMD_READ: case CMD_FAST_READ: cmd->rx_cmd_sz = cmd->tx_data_sz = 0; break; case CMD_SECTOR_ERASE: cmd->rx_cmd_sz = 0; break; case CMD_PAGE_PROGRAM: cmd->rx_cmd_sz = cmd->rx_data_sz = 0; break; } mtk_spi_chip_activate(sc); if (cmd->tx_cmd_sz + cmd->rx_cmd_sz) { buf = (uint8_t *)(cmd->rx_cmd); tx_buf = (uint8_t *)(cmd->tx_cmd); sz = cmd->tx_cmd_sz + cmd->rx_cmd_sz; for (i = 0; i < sz; i++) { if(i < cmd->tx_cmd_sz) { byte = tx_buf[i]; error = mtk_spi_txrx(sc, &byte, MTK_SPI_WRITE); if (error) goto mtk_spi_transfer_fail; continue; } error = mtk_spi_txrx(sc, &byte, MTK_SPI_READ); if (error) goto mtk_spi_transfer_fail; buf[i] = byte; } } /* * Transfer/Receive data */ if (cmd->tx_data_sz + cmd->rx_data_sz) { write = (cmd->tx_data_sz > 0)?1:0; buf = (uint8_t *)(write ? cmd->tx_data : cmd->rx_data); sz = write ? cmd->tx_data_sz : cmd->rx_data_sz; for (i = 0; i < sz; i++) { byte = buf[i]; error = mtk_spi_txrx(sc, &byte, write ? MTK_SPI_WRITE : MTK_SPI_READ); if (error) goto mtk_spi_transfer_fail; buf[i] = byte; } } mtk_spi_transfer_fail: mtk_spi_chip_deactivate(sc); return (0); } static phandle_t mtk_spi_get_node(device_t bus, device_t dev) { /* We only have one child, the SPI bus, which needs our own node. */ return (ofw_bus_get_node(bus)); } static device_method_t mtk_spi_methods[] = { /* Device interface */ DEVMETHOD(device_probe, mtk_spi_probe), DEVMETHOD(device_attach, mtk_spi_attach), DEVMETHOD(device_detach, mtk_spi_detach), DEVMETHOD(spibus_transfer, mtk_spi_transfer), /* ofw_bus interface */ DEVMETHOD(ofw_bus_get_node, mtk_spi_get_node), DEVMETHOD_END }; static driver_t mtk_spi_driver = { .name = "spi", .methods = mtk_spi_methods, .size = sizeof(struct mtk_spi_softc), }; static devclass_t mtk_spi_devclass; DRIVER_MODULE(mtk_spi_v2, simplebus, mtk_spi_driver, mtk_spi_devclass, 0, 0); Index: stable/11/sys/mips/rt305x/rt305x_spi.c =================================================================== --- stable/11/sys/mips/rt305x/rt305x_spi.c (revision 331505) +++ stable/11/sys/mips/rt305x/rt305x_spi.c (revision 331506) @@ -1,352 +1,354 @@ /*- * Copyright (c) 2009, Oleksandr Tymoshenko * Copyright (c) 2011, Aleksandr Rybalko * Copyright (c) 2013, Alexander A. Mityaev * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice unmodified, this list of conditions, and the following * disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. */ #include __FBSDID("$FreeBSD$"); #include #include #include #include #include #include #include #include #include #include //#include #include #include #include "spibus_if.h" #include "opt_platform.h" #ifdef FDT #include #include #include #endif #include #include #undef RT305X_SPI_DEBUG #ifdef RT305X_SPI_DEBUG #define dprintf printf #else #define dprintf(x, arg...) #endif /* * register space access macros */ #define SPI_WRITE(sc, reg, val) do { \ bus_write_4(sc->sc_mem_res, (reg), (val)); \ } while (0) #define SPI_READ(sc, reg) bus_read_4(sc->sc_mem_res, (reg)) #define SPI_SET_BITS(sc, reg, bits) \ SPI_WRITE(sc, reg, SPI_READ(sc, (reg)) | (bits)) #define SPI_CLEAR_BITS(sc, reg, bits) \ SPI_WRITE(sc, reg, SPI_READ(sc, (reg)) & ~(bits)) struct rt305x_spi_softc { device_t sc_dev; struct resource *sc_mem_res; }; static int rt305x_spi_probe(device_t); static int rt305x_spi_attach(device_t); static int rt305x_spi_detach(device_t); static int rt305x_spi_wait(struct rt305x_spi_softc *); static void rt305x_spi_chip_activate(struct rt305x_spi_softc *); static void rt305x_spi_chip_deactivate(struct rt305x_spi_softc *); static uint8_t rt305x_spi_txrx(struct rt305x_spi_softc *, uint8_t *, int); static int rt305x_spi_transfer(device_t, device_t, struct spi_command *); #ifdef FDT static phandle_t rt305x_spi_get_node(device_t, device_t); #endif static int rt305x_spi_probe(device_t dev) { #ifdef FDT if (!ofw_bus_is_compatible(dev, "ralink,rt305x-spi")) return(ENXIO); #endif device_set_desc(dev, "RT305X SPI"); return (0); } static int rt305x_spi_attach(device_t dev) { struct rt305x_spi_softc *sc = device_get_softc(dev); int rid; sc->sc_dev = dev; rid = 0; sc->sc_mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, RF_ACTIVE); if (!sc->sc_mem_res) { device_printf(dev, "Could not map memory\n"); return (ENXIO); } if (rt305x_spi_wait(sc)) { bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->sc_mem_res); return (EBUSY); } SPI_WRITE(sc, RT305X_SPICFG, MSBFIRST | SPICLKPOL | TX_ON_CLK_FALL | SPI_CLK_DIV8); /* XXX: make it configurable */ /* * W25Q64CV max 104MHz, bus 120-192 MHz, so divide by 2. * Update: divide by 4, DEV2 to fast for flash. */ device_add_child(dev, "spibus", 0); return (bus_generic_attach(dev)); } static int rt305x_spi_detach(device_t dev) { struct rt305x_spi_softc *sc = device_get_softc(dev); SPI_SET_BITS(sc, RT305X_SPICTL, HIZSMOSI | CS_HIGH); if (sc->sc_mem_res) bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->sc_mem_res); return (0); } static void rt305x_spi_chip_activate(struct rt305x_spi_softc *sc) { // printf("%s\n", __func__); rt305x_spi_wait(sc); /* * Put all CSx to low */ SPI_CLEAR_BITS(sc, RT305X_SPICTL, CS_HIGH | HIZSMOSI); } static void rt305x_spi_chip_deactivate(struct rt305x_spi_softc *sc) { // printf("%s\n", __func__); rt305x_spi_wait(sc); /* * Put all CSx to high */ SPI_SET_BITS(sc, RT305X_SPICTL, CS_HIGH | HIZSMOSI); } static int rt305x_spi_wait(struct rt305x_spi_softc *sc) { int i = 1000; while (i--) { if (!SPI_READ(sc, RT305X_SPIBUSY)) break; } if (i == 0) { printf("busy\n"); return (1); } return (0); } static uint8_t rt305x_spi_txrx(struct rt305x_spi_softc *sc, uint8_t *data, int write) { if (rt305x_spi_wait(sc)) return (EBUSY); if (write == RT305X_SPI_WRITE) { SPI_WRITE(sc, RT305X_SPIDATA, *data); SPI_SET_BITS(sc, RT305X_SPICTL, START_WRITE); //printf("%s(W:%d)\n", __func__, *data); } else {/* RT305X_SPI_READ */ SPI_SET_BITS(sc, RT305X_SPICTL, START_READ); if (rt305x_spi_wait(sc)) return (EBUSY); *data = SPI_READ(sc, RT305X_SPIDATA) & 0xff; //printf("%s(R:%d)\n", __func__, *data); } return (0); } static int rt305x_spi_transfer(device_t dev, device_t child, struct spi_command *cmd) { struct rt305x_spi_softc *sc; uint32_t cs; uint8_t *buf, byte, *tx_buf; int i, sz, error = 0, write = 0; sc = device_get_softc(dev); spibus_get_cs(child, &cs); + cs &= ~SPIBUS_CS_HIGH; + if (cs != 0) /* Only 1 CS */ return (ENXIO); /* There is always a command to transfer. */ tx_buf = (uint8_t *)(cmd->tx_cmd); /* Perform some fixup because RT305X dont support duplex SPI */ switch(tx_buf[0]) { case CMD_READ_IDENT: cmd->tx_cmd_sz = 1; cmd->rx_cmd_sz = 3; break; case CMD_WRITE_ENABLE: case CMD_WRITE_DISABLE: cmd->tx_cmd_sz = 1; cmd->rx_cmd_sz = 0; break; case CMD_READ_STATUS: cmd->tx_cmd_sz = 1; cmd->rx_cmd_sz = 1; break; case CMD_READ: cmd->tx_cmd_sz = 4; case CMD_FAST_READ: cmd->tx_cmd_sz = 5; cmd->rx_cmd_sz = cmd->tx_data_sz = 0; break; case CMD_SECTOR_ERASE: cmd->tx_cmd_sz = 4; cmd->rx_cmd_sz = cmd->tx_data_sz = 0; break; case CMD_PAGE_PROGRAM: cmd->tx_cmd_sz = 4; cmd->rx_cmd_sz = cmd->rx_data_sz = 0; break; } rt305x_spi_chip_activate(sc); if (cmd->tx_cmd_sz + cmd->rx_cmd_sz) { buf = (uint8_t *)(cmd->rx_cmd); tx_buf = (uint8_t *)(cmd->tx_cmd); sz = cmd->tx_cmd_sz + cmd->rx_cmd_sz; for (i = 0; i < sz; i++) { if(i < cmd->tx_cmd_sz) { byte = tx_buf[i]; error = rt305x_spi_txrx(sc, &byte, RT305X_SPI_WRITE); if (error) goto rt305x_spi_transfer_fail; continue; } error = rt305x_spi_txrx(sc, &byte, RT305X_SPI_READ); if (error) goto rt305x_spi_transfer_fail; buf[i] = byte; } } /* * Transfer/Receive data */ if (cmd->tx_data_sz + cmd->rx_data_sz) { write = (cmd->tx_data_sz > 0)?1:0; buf = (uint8_t *)(write ? cmd->tx_data : cmd->rx_data); sz = write ? cmd->tx_data_sz : cmd->rx_data_sz; for (i = 0; i < sz; i++) { byte = buf[i]; error = rt305x_spi_txrx(sc, &byte, write?RT305X_SPI_WRITE:RT305X_SPI_READ); if (error) goto rt305x_spi_transfer_fail; buf[i] = byte; } } rt305x_spi_transfer_fail: rt305x_spi_chip_deactivate(sc); return (error); } #ifdef FDT static phandle_t rt305x_spi_get_node(device_t bus, device_t dev) { /* We only have one child, the SPI bus, which needs our own node. */ return (ofw_bus_get_node(bus)); } #endif static device_method_t rt305x_spi_methods[] = { /* Device interface */ DEVMETHOD(device_probe, rt305x_spi_probe), DEVMETHOD(device_attach, rt305x_spi_attach), DEVMETHOD(device_detach, rt305x_spi_detach), DEVMETHOD(spibus_transfer, rt305x_spi_transfer), #ifdef FDT /* ofw_bus interface */ DEVMETHOD(ofw_bus_get_node, rt305x_spi_get_node), #endif DEVMETHOD_END }; static driver_t rt305x_spi_driver = { .name = "spi", .methods = rt305x_spi_methods, .size = sizeof(struct rt305x_spi_softc), }; static devclass_t rt305x_spi_devclass; DRIVER_MODULE(rt305x_spi, obio, rt305x_spi_driver, rt305x_spi_devclass, 0, 0); #ifdef FDT DRIVER_MODULE(rt305x_spi, simplebus, rt305x_spi_driver, rt305x_spi_devclass, 0, 0); #endif Index: stable/11/sys/modules/Makefile =================================================================== --- stable/11/sys/modules/Makefile (revision 331505) +++ stable/11/sys/modules/Makefile (revision 331506) @@ -1,852 +1,852 @@ # $FreeBSD$ SYSDIR?=${SRCTOP}/sys .include "${SYSDIR}/conf/kern.opts.mk" SUBDIR_PARALLEL= # Modules that include binary-only blobs of microcode should be selectable by # MK_SOURCELESS_UCODE option (see below). .if defined(MODULES_OVERRIDE) && !defined(ALL_MODULES) SUBDIR=${MODULES_OVERRIDE} .else SUBDIR= \ ${_3dfx} \ ${_3dfx_linux} \ ${_aac} \ ${_aacraid} \ accf_data \ accf_dns \ accf_http \ acl_nfs4 \ acl_posix1e \ ${_acpi} \ ae \ ${_aesni} \ age \ ${_agp} \ aha \ ${_ahb} \ ahci \ ${_aic} \ aic7xxx \ alc \ ale \ alq \ ${_amd_ecc_inject} \ ${_amdsbwd} \ ${_amdsmn} \ ${_amdtemp} \ amr \ ${_an} \ ${_aout} \ ${_apm} \ ${_arcmsr} \ ${_arcnet} \ ${_asmc} \ ata \ ath \ ath_pci \ ${_autofs} \ ${_auxio} \ ${_bce} \ bfe \ bge \ bhnd \ ${_bxe} \ ${_bios} \ ${_bktr} \ ${_bm} \ bnxt \ bridgestp \ bwi \ bwn \ bwn_pci \ ${_bytgpio} \ cam \ ${_canbepm} \ ${_canbus} \ ${_cardbus} \ ${_carp} \ cas \ ${_cbb} \ cc \ cd9660 \ cd9660_iconv \ ${_ce} \ ${_cfi} \ ${_chromebook_platform} \ ${_ciss} \ cloudabi \ ${_cloudabi32} \ ${_cloudabi64} \ ${_cm} \ ${_cmx} \ ${_coff} \ ${_coretemp} \ ${_cp} \ ${_cpsw} \ ${_cpuctl} \ ${_cpufreq} \ ${_crypto} \ ${_cryptodev} \ ${_cs} \ ${_ct} \ ${_ctau} \ ctl \ ${_cxgb} \ ${_cxgbe} \ dc \ dcons \ dcons_crom \ de \ ${_dpms} \ ${_dpt} \ ${_drm} \ ${_drm2} \ dummynet \ ${_ed} \ ${_efirt} \ ${_elink} \ ${_em} \ ${_ena} \ en \ ${_ep} \ ${_epic} \ esp \ ${_et} \ evdev \ ${_ex} \ ${_exca} \ ext2fs \ ${_fatm} \ fdc \ fdescfs \ ${_fe} \ ${_ffec} \ filemon \ firewire \ firmware \ fuse \ ${_fxp} \ gem \ geom \ ${_glxiic} \ ${_glxsb} \ gpio \ hatm \ hifn \ hme \ ${_hpt27xx} \ ${_hptiop} \ ${_hptmv} \ ${_hptnr} \ ${_hptrr} \ hwpmc \ ${_hyperv} \ i2c \ ${_ibcore} \ ${_ibcs2} \ ${_ichwd} \ ${_ida} \ ${_ie} \ if_bridge \ if_disc \ if_edsc \ ${_if_enc} \ if_epair \ ${_if_gif} \ ${_if_gre} \ ${_if_me} \ if_lagg \ ${_if_ndis} \ ${_if_stf} \ if_tap \ if_tun \ if_vlan \ if_vxlan \ ${_igb} \ ${_iir} \ imgact_binmisc \ ${_intelspi} \ ${_io} \ ${_ioat} \ ${_ipoib} \ ${_ipdivert} \ ${_ipfilter} \ ${_ipfw} \ ipfw_nat \ ${_ipfw_nat64} \ ${_ipfw_nptv6} \ ${_ipfw_pmod} \ ${_ipmi} \ ip6_mroute_mod \ ip_mroute_mod \ ${_ips} \ ${_ipsec} \ ${_ipw} \ ${_ipwfw} \ ${_isci} \ ${_iser} \ isp \ ${_ispfw} \ ${_iwi} \ ${_iwifw} \ ${_iwm} \ ${_iwmfw} \ ${_iwn} \ ${_iwnfw} \ ${_ix} \ ${_ixv} \ ${_ixgb} \ ${_ixl} \ ${_ixlv} \ jme \ joy \ kbdmux \ kgssapi \ kgssapi_krb5 \ khelp \ krpc \ ksyms \ le \ lge \ libalias \ libiconv \ libmbpool \ libmchain \ ${_linprocfs} \ ${_linsysfs} \ ${_linux} \ ${_linux_common} \ ${_linux64} \ linuxkpi \ ${_lio} \ lmc \ lpt \ mac_biba \ mac_bsdextended \ mac_ifoff \ mac_lomac \ mac_mls \ mac_none \ mac_partition \ mac_portacl \ mac_seeotheruids \ mac_stub \ mac_test \ malo \ mcd \ md \ mdio \ mem \ mfi \ mii \ mlx \ ${_mlx4} \ ${_mlx4ib} \ ${_mlx4en} \ ${_mlx5} \ ${_mlx5en} \ ${_mlx5ib} \ ${_mly} \ mmc \ mmcsd \ mpr \ mps \ mpt \ mqueue \ mrsas \ msdosfs \ msdosfs_iconv \ ${_mse} \ msk \ ${_mthca} \ mvs \ mwl \ ${_mwlfw} \ mxge \ my \ ${_nandfs} \ ${_nandsim} \ ${_ncr} \ ${_nctgpio} \ ${_ncv} \ ${_ndis} \ netfpga10g \ ${_netgraph} \ ${_nfe} \ nfscl \ nfscommon \ nfsd \ nfslock \ nfslockd \ nfssvc \ nge \ nmdm \ ${_nsp} \ nullfs \ ${_ntb} \ ${_nvd} \ ${_nvme} \ ${_nvram} \ ${_nxge} \ oce \ otus \ ${_otusfw} \ ow \ ${_padlock} \ ${_padlock_rng} \ patm \ ${_pccard} \ ${_pcfclock} \ pcn \ ${_pf} \ ${_pflog} \ ${_pfsync} \ plip \ ${_pmc} \ ${_pms} \ ppbus \ ppc \ ppi \ pps \ procfs \ proto \ pseudofs \ ${_pst} \ pty \ puc \ ${_qlxge} \ ${_qlxgb} \ ${_qlxgbe} \ ${_qlnx} \ ral \ ${_ralfw} \ ${_random_fortuna} \ ${_random_yarrow} \ ${_random_other} \ rc4 \ ${_rdma} \ ${_rdrand_rng} \ re \ rl \ rtwn \ ${_rtwnfw} \ ${_s3} \ ${_safe} \ ${_sbni} \ scc \ scd \ ${_scsi_low} \ sdhci \ ${_sdhci_acpi} \ sdhci_pci \ sem \ send \ ${_sf} \ ${_sfxge} \ sge \ ${_si} \ siba_bwn \ siftr \ siis \ sis \ sk \ smbfs \ sn \ ${_snc} \ snp \ sound \ ${_speaker} \ - spigen \ + spi \ ${_splash} \ ${_sppp} \ ste \ ${_stg} \ stge \ ${_streams} \ ${_svr4} \ ${_sym} \ ${_syscons} \ sysvipc \ tcp \ ${_ti} \ tl \ tmpfs \ ${_toecore} \ ${_tpm} \ trm \ ${_twa} \ twe \ tws \ tx \ ${_txp} \ uart \ ubsec \ udf \ udf_iconv \ ufs \ uinput \ unionfs \ urtwn \ ${_urtwnfw} \ usb \ utopia \ ${_vesa} \ ${_virtio} \ vge \ ${_viawd} \ videomode \ vkbd \ ${_vmm} \ ${_vmware} \ ${_vpo} \ vr \ vte \ vx \ ${_vxge} \ wb \ ${_wbwd} \ ${_wds} \ ${_wi} \ ${_wl} \ wlan \ wlan_acl \ wlan_amrr \ wlan_ccmp \ wlan_rssadapt \ wlan_tkip \ wlan_wep \ wlan_xauth \ ${_wpi} \ ${_wpifw} \ ${_x86bios} \ ${_xe} \ xl \ zlib .if ${MK_AUTOFS} != "no" || defined(ALL_MODULES) _autofs= autofs .endif .if ${MK_CDDL} != "no" || defined(ALL_MODULES) .if (${MACHINE_CPUARCH} != "arm" || ${MACHINE_ARCH:Marmv6*} != "") && \ ${MACHINE_CPUARCH} != "mips" && \ ${MACHINE_CPUARCH} != "sparc64" SUBDIR+= dtrace .endif SUBDIR+= opensolaris .endif .if ${MK_CRYPT} != "no" || defined(ALL_MODULES) .if exists(${SRCTOP}/sys/opencrypto) _crypto= crypto _cryptodev= cryptodev _random_fortuna=random_fortuna _random_yarrow= random_yarrow _random_other= random_other .endif .endif .if ${MK_CUSE} != "no" || defined(ALL_MODULES) SUBDIR+= cuse .endif .if (${MK_INET_SUPPORT} != "no" || ${MK_INET6_SUPPORT} != "no") || \ defined(ALL_MODULES) _carp= carp _toecore= toecore _if_enc= if_enc _if_gif= if_gif _if_gre= if_gre _ipfw_pmod= ipfw_pmod .if ${MK_IPSEC_SUPPORT} != "no" _ipsec= ipsec .endif .endif .if (${MK_INET_SUPPORT} != "no" && ${MK_INET6_SUPPORT} != "no") || \ defined(ALL_MODULES) _if_stf= if_stf .endif .if ${MK_INET_SUPPORT} != "no" || defined(ALL_MODULES) _if_me= if_me _ipdivert= ipdivert _ipfw= ipfw .if ${MK_INET6_SUPPORT} != "no" || defined(ALL_MODULES) _ipfw_nat64= ipfw_nat64 .endif .endif .if ${MK_INET6_SUPPORT} != "no" || defined(ALL_MODULES) _ipfw_nptv6= ipfw_nptv6 .endif .if ${MK_IPFILTER} != "no" || defined(ALL_MODULES) _ipfilter= ipfilter .endif .if ${MK_ISCSI} != "no" || defined(ALL_MODULES) SUBDIR+= cfiscsi SUBDIR+= iscsi SUBDIR+= iscsi_initiator .endif .if ${MK_NAND} != "no" || defined(ALL_MODULES) _nandfs= nandfs _nandsim= nandsim .endif .if ${MK_NETGRAPH} != "no" || defined(ALL_MODULES) _netgraph= netgraph .endif .if (${MK_PF} != "no" && (${MK_INET_SUPPORT} != "no" || \ ${MK_INET6_SUPPORT} != "no")) || defined(ALL_MODULES) _pf= pf _pflog= pflog .if ${MK_INET_SUPPORT} != "no" _pfsync= pfsync .endif .endif .if ${MK_SOURCELESS_UCODE} != "no" _bce= bce _fatm= fatm _fxp= fxp _ispfw= ispfw _mwlfw= mwlfw _otusfw= otusfw _ralfw= ralfw _rtwnfw= rtwnfw _urtwnfw= urtwnfw _sf= sf _ti= ti _txp= txp .endif .if ${MK_SOURCELESS_UCODE} != "no" && ${MACHINE_CPUARCH} != "arm" && \ ${MACHINE_ARCH:C/mips(el)?/mips/} != "mips" && \ ${MACHINE_ARCH} != "powerpc" && ${MACHINE_CPUARCH} != "riscv" _cxgbe= cxgbe .endif .if ${MK_TESTS} != "no" || defined(ALL_MODULES) SUBDIR+= tests .endif .if ${MK_ZFS} != "no" || defined(ALL_MODULES) SUBDIR+= zfs .endif .if ${MACHINE_CPUARCH} != "aarch64" && ${MACHINE_CPUARCH} != "arm" && \ ${MACHINE_CPUARCH} != "mips" && ${MACHINE_CPUARCH} != "powerpc" && \ ${MACHINE_CPUARCH} != "riscv" _syscons= syscons _vpo= vpo .endif .if ${MACHINE_CPUARCH} != "mips" # no BUS_SPACE_UNSPECIFIED # No barrier instruction support (specific to this driver) _sym= sym # intr_disable() is a macro, causes problems .if ${MK_SOURCELESS_UCODE} != "no" _cxgb= cxgb .endif .endif .if ${MACHINE_CPUARCH} == "aarch64" _em= em _igb= igb .endif .if ${MACHINE_CPUARCH} == "i386" || ${MACHINE_CPUARCH} == "amd64" _agp= agp _an= an _aout= aout _bios= bios _bktr= bktr .if ${MK_SOURCELESS_UCODE} != "no" _bxe= bxe .endif _cardbus= cardbus _cbb= cbb _cpuctl= cpuctl _cpufreq= cpufreq _cs= cs _dpms= dpms _drm= drm _drm2= drm2 _ed= ed _em= em _ena= ena _ep= ep _et= et _exca= exca _fe= fe .if ${MK_OFED} != "no" || defined(ALL_MODULES) _ibcore= ibcore .endif _if_ndis= if_ndis _igb= igb _io= io .if ${MK_OFED} != "no" || defined(ALL_MODULES) _ipoib= ipoib _iser= iser .endif _ix= ix _ixv= ixv _linprocfs= linprocfs _linsysfs= linsysfs _linux= linux .if ${MK_SOURCELESS_UCODE} != "no" _lio= lio .endif _nctgpio= nctgpio _ndis= ndis _pccard= pccard .if ${MK_OFED} != "no" || defined(ALL_MODULES) _rdma= rdma .endif _safe= safe _scsi_low= scsi_low _si= si _speaker= speaker _splash= splash _sppp= sppp _vmware= vmware _vxge= vxge _wbwd= wbwd _wi= wi _xe= xe .if ${MACHINE} != "pc98" _aac= aac _aacraid= aacraid _acpi= acpi .if ${MK_CRYPT} != "no" || defined(ALL_MODULES) _aesni= aesni .endif _amd_ecc_inject=amd_ecc_inject _amdsbwd= amdsbwd _amdsmn= amdsmn _amdtemp= amdtemp _arcmsr= arcmsr _asmc= asmc _bytgpio= bytgpio _ciss= ciss _chromebook_platform= chromebook_platform _cmx= cmx _coretemp= coretemp .if ${MK_SOURCELESS_HOST} != "no" _hpt27xx= hpt27xx .endif _hptiop= hptiop .if ${MK_SOURCELESS_HOST} != "no" _hptmv= hptmv _hptnr= hptnr _hptrr= hptrr .endif _hyperv= hyperv _ichwd= ichwd _ida= ida _iir= iir _intelspi= intelspi _ipmi= ipmi _ips= ips _isci= isci _ipw= ipw _iwi= iwi _iwm= iwm _iwn= iwn _ixgb= ixgb .if ${MK_SOURCELESS_UCODE} != "no" _ipwfw= ipwfw _iwifw= iwifw _iwmfw= iwmfw _iwnfw= iwnfw .endif _mlx4= mlx4 _mlx5= mlx5 .if (${MK_INET_SUPPORT} != "no" && ${MK_INET6_SUPPORT} != "no") || \ defined(ALL_MODULES) _mlx4en= mlx4en _mlx5en= mlx5en .endif .if ${MK_OFED} != "no" || defined(ALL_MODULES) _mlx4ib= mlx4ib _mlx5ib= mlx5ib .endif _mly= mly .if ${MK_OFED} != "no" || defined(ALL_MODULES) _mthca= mthca .endif _nfe= nfe _nvd= nvd _nvme= nvme _nvram= nvram _nxge= nxge .if ${MK_CRYPT} != "no" || defined(ALL_MODULES) _padlock= padlock _padlock_rng= padlock_rng _rdrand_rng= rdrand_rng .endif _s3= s3 _sdhci_acpi= sdhci_acpi _tpm= tpm _twa= twa _vesa= vesa _viawd= viawd _virtio= virtio _wpi= wpi .if ${MK_SOURCELESS_UCODE} != "no" _wpifw= wpifw .endif _x86bios= x86bios .endif .endif .if ${MACHINE_CPUARCH} == "amd64" _efirt= efirt _ioat= ioat _ixl= ixl _ixlv= ixlv _linux64= linux64 _linux_common= linux_common _ntb= ntb _pms= pms _qlxge= qlxge _qlxgb= qlxgb .if ${MK_SOURCELESS_UCODE} != "no" _qlxgbe= qlxgbe _qlnx= qlnx .endif _sfxge= sfxge .if ${MK_BHYVE} != "no" || defined(ALL_MODULES) _vmm= vmm .endif .endif .if ${MACHINE_CPUARCH} == "i386" # XXX some of these can move to the general case when de-i386'ed # XXX some of these can move now, but are untested on other architectures. _3dfx= 3dfx _3dfx_linux= 3dfx_linux _aic= aic _apm= apm _arcnet= arcnet .if ${MK_SOURCELESS_UCODE} != "no" _ce= ce .endif _coff= coff .if ${MK_SOURCELESS_UCODE} != "no" _cp= cp .endif _elink= elink _glxiic= glxiic _glxsb= glxsb #_ibcs2= ibcs2 _ie= ie _mse= mse _ncr= ncr _ncv= ncv _nsp= nsp _pcfclock= pcfclock _pst= pst _sbni= sbni _streams= streams _stg= stg _svr4= svr4 _wds= wds .if ${MACHINE} == "i386" .if ${MK_EISA} != "no" _ahb= ahb .endif _cm= cm .if ${MK_SOURCELESS_UCODE} != "no" _ctau= ctau .endif _dpt= dpt _ex= ex _wl= wl .elif ${MACHINE} == "pc98" _canbepm= canbepm _canbus= canbus _ct= ct _pmc= pmc _snc= snc .endif .endif .if ${MACHINE_CPUARCH} == "arm" _cfi= cfi _cpsw= cpsw .endif .if ${MACHINE_CPUARCH} == "powerpc" _agp= agp _an= an _bm= bm _cardbus= cardbus _cbb= cbb _cfi= cfi _cpufreq= cpufreq _drm= drm _exca= exca _nvram= powermac_nvram _ffec= ffec _pccard= pccard _wi= wi .endif .if ${MACHINE_ARCH} == "powerpc64" _drm2= drm2 .endif .if ${MACHINE_CPUARCH} == "sparc64" _auxio= auxio _em= em _epic= epic _igb= igb .endif .if (${MACHINE_CPUARCH} == "amd64" || ${MACHINE_ARCH} == "armv6" || \ ${MACHINE_CPUARCH} == "i386") _cloudabi32= cloudabi32 .endif .if ${MACHINE_CPUARCH} == "aarch64" || ${MACHINE_CPUARCH} == "amd64" _cloudabi64= cloudabi64 .endif .endif .if ${MACHINE_ARCH:Marmv[67]*} != "" || ${MACHINE_CPUARCH} == "aarch64" _bcm283x_clkman= bcm283x_clkman _bcm283x_pwm= bcm283x_pwm .endif SUBDIR+=${MODULES_EXTRA} .for reject in ${WITHOUT_MODULES} SUBDIR:= ${SUBDIR:N${reject}} .endfor # Calling kldxref(8) for each module is expensive. .if !defined(NO_XREF) .MAKEFLAGS+= -DNO_XREF afterinstall: .PHONY @if type kldxref >/dev/null 2>&1; then \ ${ECHO} kldxref ${DESTDIR}${KMODDIR}; \ kldxref ${DESTDIR}${KMODDIR}; \ fi .endif .include "${SYSDIR}/conf/config.mk" SUBDIR:= ${SUBDIR:u:O} .include Index: stable/11/sys/modules/imx/Makefile =================================================================== --- stable/11/sys/modules/imx/Makefile (revision 331505) +++ stable/11/sys/modules/imx/Makefile (revision 331506) @@ -1,8 +1,9 @@ # $FreeBSD$ # Build modules specific to freescale/nxp imx-family SoCs. SUBDIR = \ ../ffec \ imx_i2c \ + imx_spi \ .include Index: stable/11/sys/modules/imx/imx_spi/Makefile =================================================================== --- stable/11/sys/modules/imx/imx_spi/Makefile (nonexistent) +++ stable/11/sys/modules/imx/imx_spi/Makefile (revision 331506) @@ -0,0 +1,16 @@ +# $FreeBSD$ + +.PATH: ${SRCTOP}/sys/arm/freescale/imx + +KMOD= imx_spi +SRCS= imx_spi.c + +# Generated files... +SRCS+= \ + bus_if.h \ + device_if.h \ + ofw_bus_if.h \ + opt_platform.h \ + spibus_if.h \ + +.include Property changes on: stable/11/sys/modules/imx/imx_spi/Makefile ___________________________________________________________________ Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:keywords ## -0,0 +1 ## +FreeBSD=%H \ No newline at end of property Added: svn:mime-type ## -0,0 +1 ## +text/plain \ No newline at end of property Index: stable/11/sys/modules/spi/at45d/Makefile =================================================================== --- stable/11/sys/modules/spi/at45d/Makefile (nonexistent) +++ stable/11/sys/modules/spi/at45d/Makefile (revision 331506) @@ -0,0 +1,18 @@ +# $FreeBSD$ + +.PATH: ${SRCTOP}/sys/dev/flash + +KMOD= at45d +SRCS= at45d.c + +# Generated files... +SRCS+= \ + bus_if.h \ + device_if.h \ + spibus_if.h \ + +.if !empty(OPT_FDT) +SRCS+= ofw_bus_if.h +.endif + +.include Property changes on: stable/11/sys/modules/spi/at45d/Makefile ___________________________________________________________________ Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:keywords ## -0,0 +1 ## +FreeBSD=%H \ No newline at end of property Added: svn:mime-type ## -0,0 +1 ## +text/plain \ No newline at end of property Index: stable/11/sys/modules/spi/mx25l/Makefile =================================================================== --- stable/11/sys/modules/spi/mx25l/Makefile (nonexistent) +++ stable/11/sys/modules/spi/mx25l/Makefile (revision 331506) @@ -0,0 +1,18 @@ +# $FreeBSD$ + +.PATH: ${SRCTOP}/sys/dev/flash + +KMOD= mx25l +SRCS= mx25l.c + +# Generated files... +SRCS+= \ + bus_if.h \ + device_if.h \ + spibus_if.h \ + +.if !empty(OPT_FDT) +SRCS+= ofw_bus_if.h +.endif + +.include Property changes on: stable/11/sys/modules/spi/mx25l/Makefile ___________________________________________________________________ Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:keywords ## -0,0 +1 ## +FreeBSD=%H \ No newline at end of property Added: svn:mime-type ## -0,0 +1 ## +text/plain \ No newline at end of property Index: stable/11/sys/modules/spi/Makefile =================================================================== --- stable/11/sys/modules/spi/Makefile (nonexistent) +++ stable/11/sys/modules/spi/Makefile (revision 331506) @@ -0,0 +1,9 @@ +# $FreeBSD$ + +SUBDIR = \ + ../spigen \ + at45d \ + mx25l \ + spibus \ + +.include Property changes on: stable/11/sys/modules/spi/Makefile ___________________________________________________________________ Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:keywords ## -0,0 +1 ## +FreeBSD=%H \ No newline at end of property Added: svn:mime-type ## -0,0 +1 ## +text/plain \ No newline at end of property Index: stable/11/sys/modules/spi/spibus/Makefile =================================================================== --- stable/11/sys/modules/spi/spibus/Makefile (nonexistent) +++ stable/11/sys/modules/spi/spibus/Makefile (revision 331506) @@ -0,0 +1,19 @@ +# $FreeBSD$ + +.PATH: ${SRCTOP}/sys/dev/spibus + +KMOD= spibus +SRCS= spibus.c + +.if !empty(OPT_FDT) +SRCS+= ofw_spibus.c ofw_bus_if.h +.endif + +# Generated files... +SRCS+= \ + bus_if.h \ + device_if.h \ + spibus_if.c \ + spibus_if.h \ + +.include Property changes on: stable/11/sys/modules/spi/spibus/Makefile ___________________________________________________________________ Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:keywords ## -0,0 +1 ## +FreeBSD=%H \ No newline at end of property Added: svn:mime-type ## -0,0 +1 ## +text/plain \ No newline at end of property Index: stable/11 =================================================================== --- stable/11 (revision 331505) +++ stable/11 (revision 331506) Property changes on: stable/11 ___________________________________________________________________ Modified: svn:mergeinfo ## -0,0 +0,1 ## Merged /head:r310017,310229,312289,327260,329539,329544-329546,329620,329729,329911,329999