Index: head/sys/arm/amlogic/aml8726/aml8726_clkmsr.c =================================================================== --- head/sys/arm/amlogic/aml8726/aml8726_clkmsr.c (revision 331228) +++ head/sys/arm/amlogic/aml8726/aml8726_clkmsr.c (revision 331229) @@ -1,300 +1,300 @@ /*- * Copyright 2014-2015 John Wehle * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. * */ /* * Amlogic aml8726 clock measurement driver. * * This allows various clock rates to be determine at runtime. * The measurements are done once and are not expected to change * (i.e. FDT fixup provides clk81 as bus-frequency to the MMC * and UART drivers which use the value when programming the * hardware). */ #include __FBSDID("$FreeBSD$"); #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include static struct aml8726_clkmsr_clk { const char * name; uint32_t mux; } aml8726_clkmsr_clks[] = { { "clk81", 7 }, }; #define AML_CLKMSR_CLK81 0 #define AML_CLKMSR_NCLKS nitems(aml8726_clkmsr_clks) struct aml8726_clkmsr_softc { device_t dev; struct resource * res[1]; }; static struct resource_spec aml8726_clkmsr_spec[] = { { SYS_RES_MEMORY, 0, RF_ACTIVE }, { -1, 0 } }; /* * Duration can range from 1uS to 65535 uS and should be chosen * based on the expected frequency result so to maximize resolution * and avoid overflowing the 16 bit result counter. */ #define AML_CLKMSR_DURATION 32 #define AML_CLKMSR_DUTY_REG 0 #define AML_CLKMSR_0_REG 4 #define AML_CLKMSR_0_BUSY (1U << 31) #define AML_CLKMSR_0_MUX_MASK (0x3f << 20) #define AML_CLKMSR_0_MUX_SHIFT 20 #define AML_CLKMSR_0_MUX_EN (1 << 19) #define AML_CLKMSR_0_MEASURE (1 << 16) #define AML_CLKMSR_0_DURATION_MASK 0xffff #define AML_CLKMSR_0_DURATION_SHIFT 0 #define AML_CLKMSR_1_REG 8 #define AML_CLKMSR_2_REG 12 #define AML_CLKMSR_2_RESULT_MASK 0xffff #define AML_CLKMSR_2_RESULT_SHIFT 0 #define CSR_WRITE_4(sc, reg, val) bus_write_4((sc)->res[0], reg, (val)) #define CSR_READ_4(sc, reg) bus_read_4((sc)->res[0], reg) #define CSR_BARRIER(sc, reg) bus_barrier((sc)->res[0], reg, 4, \ (BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE)) static int aml8726_clkmsr_clock_frequency(struct aml8726_clkmsr_softc *sc, unsigned clock) { uint32_t value; if (clock >= AML_CLKMSR_NCLKS) return (0); /* * Locking is not used as this is only expected to be called from * FDT fixup (which occurs prior to driver initialization) or attach. */ CSR_WRITE_4(sc, AML_CLKMSR_0_REG, 0); CSR_BARRIER(sc, AML_CLKMSR_0_REG); value = (aml8726_clkmsr_clks[clock].mux << AML_CLKMSR_0_MUX_SHIFT) | ((AML_CLKMSR_DURATION - 1) << AML_CLKMSR_0_DURATION_SHIFT) | AML_CLKMSR_0_MUX_EN | AML_CLKMSR_0_MEASURE; CSR_WRITE_4(sc, AML_CLKMSR_0_REG, value); CSR_BARRIER(sc, AML_CLKMSR_0_REG); while ((CSR_READ_4(sc, AML_CLKMSR_0_REG) & AML_CLKMSR_0_BUSY) != 0) cpu_spinwait(); value &= ~AML_CLKMSR_0_MEASURE; CSR_WRITE_4(sc, AML_CLKMSR_0_REG, value); CSR_BARRIER(sc, AML_CLKMSR_0_REG); value = (((CSR_READ_4(sc, AML_CLKMSR_2_REG) & AML_CLKMSR_2_RESULT_MASK) >> AML_CLKMSR_2_RESULT_SHIFT) + AML_CLKMSR_DURATION / 2) / AML_CLKMSR_DURATION; return value; } static void aml8726_clkmsr_fixup_clk81(struct aml8726_clkmsr_softc *sc, int freq) { pcell_t prop; ssize_t len; phandle_t clk_node; phandle_t node; node = ofw_bus_get_node(sc->dev); len = OF_getencprop(node, "clocks", &prop, sizeof(prop)); if ((len / sizeof(prop)) != 1 || prop == 0 || (clk_node = OF_node_from_xref(prop)) == 0) return; len = OF_getencprop(clk_node, "clock-frequency", &prop, sizeof(prop)); if ((len / sizeof(prop)) != 1 || prop != 0) return; freq = cpu_to_fdt32(freq); OF_setprop(clk_node, "clock-frequency", (void *)&freq, sizeof(freq)); } static int aml8726_clkmsr_probe(device_t dev) { if (!ofw_bus_status_okay(dev)) return (ENXIO); if (!ofw_bus_is_compatible(dev, "amlogic,aml8726-clkmsr")) return (ENXIO); device_set_desc(dev, "Amlogic aml8726 clkmsr"); return (BUS_PROBE_DEFAULT); } static int aml8726_clkmsr_attach(device_t dev) { struct aml8726_clkmsr_softc *sc = device_get_softc(dev); int freq; sc->dev = dev; if (bus_alloc_resources(dev, aml8726_clkmsr_spec, sc->res)) { device_printf(dev, "can not allocate resources for device\n"); return (ENXIO); } freq = aml8726_clkmsr_clock_frequency(sc, AML_CLKMSR_CLK81); device_printf(sc->dev, "bus clock %u MHz\n", freq); aml8726_clkmsr_fixup_clk81(sc, freq * 1000000); return (0); } static int aml8726_clkmsr_detach(device_t dev) { struct aml8726_clkmsr_softc *sc = device_get_softc(dev); bus_release_resources(dev, aml8726_clkmsr_spec, sc->res); return (0); } static device_method_t aml8726_clkmsr_methods[] = { /* Device interface */ DEVMETHOD(device_probe, aml8726_clkmsr_probe), DEVMETHOD(device_attach, aml8726_clkmsr_attach), DEVMETHOD(device_detach, aml8726_clkmsr_detach), DEVMETHOD_END }; static driver_t aml8726_clkmsr_driver = { "clkmsr", aml8726_clkmsr_methods, sizeof(struct aml8726_clkmsr_softc), }; static devclass_t aml8726_clkmsr_devclass; EARLY_DRIVER_MODULE(clkmsr, simplebus, aml8726_clkmsr_driver, aml8726_clkmsr_devclass, 0, 0, BUS_PASS_CPU + BUS_PASS_ORDER_EARLY); int aml8726_clkmsr_bus_frequency() { struct resource mem; struct aml8726_clkmsr_softc sc; phandle_t node; u_long pbase, psize; u_long start, size; int freq; KASSERT(aml8726_soc_hw_rev != AML_SOC_HW_REV_UNKNOWN, ("aml8726_soc_hw_rev isn't initialized")); /* * Try to access the clkmsr node directly i.e. through /aliases/. */ - if ((node = OF_finddevice("clkmsr")) != 0) + if ((node = OF_finddevice("clkmsr")) != -1) if (fdt_is_compatible_strict(node, "amlogic,aml8726-clkmsr")) goto moveon; /* * Find the node the long way. */ - if ((node = OF_finddevice("/soc")) == 0) + if ((node = OF_finddevice("/soc")) == -1) return (0); if ((node = fdt_find_compatible(node, "amlogic,aml8726-clkmsr", 1)) == 0) return (0); moveon: if (fdt_get_range(OF_parent(node), 0, &pbase, &psize) != 0 || fdt_regsize(node, &start, &size) != 0) return (0); start += pbase; memset(&mem, 0, sizeof(mem)); mem.r_bustag = fdtbus_bs_tag; if (bus_space_map(mem.r_bustag, start, size, 0, &mem.r_bushandle) != 0) return (0); /* * Build an incomplete (however sufficient for the purpose * of calling aml8726_clkmsr_clock_frequency) softc. */ memset(&sc, 0, sizeof(sc)); sc.res[0] = &mem; freq = aml8726_clkmsr_clock_frequency(&sc, AML_CLKMSR_CLK81) * 1000000; bus_space_unmap(mem.r_bustag, mem.r_bushandle, size); return (freq); } Index: head/sys/arm/amlogic/aml8726/aml8726_mp.c =================================================================== --- head/sys/arm/amlogic/aml8726/aml8726_mp.c (revision 331228) +++ head/sys/arm/amlogic/aml8726/aml8726_mp.c (revision 331229) @@ -1,628 +1,628 @@ /*- * Copyright 2015 John Wehle * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. */ /* * Amlogic aml8726 multiprocessor support. * * Some processors require powering on which involves poking registers * on the aobus and cbus ... it's expected that these locations are set * in stone. * * Locking is not used as these routines should only be called by the BP * during startup and should complete prior to the APs being released (the * issue being to ensure that a register such as AML_SOC_CPU_CLK_CNTL_REG * is not concurrently modified). */ #include __FBSDID("$FreeBSD$"); #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include static const char *scu_compatible[] = { "arm,cortex-a5-scu", "arm,cortex-a9-scu", NULL }; static const char *scu_errata_764369[] = { "arm,cortex-a9-scu", NULL }; static const char *cpucfg_compatible[] = { "amlogic,aml8726-cpuconfig", NULL }; static struct { boolean_t errata_764369; u_long scu_size; struct resource scu_res; u_long cpucfg_size; struct resource cpucfg_res; struct resource aobus_res; struct resource cbus_res; } aml8726_smp; #define AML_SCU_CONTROL_REG 0 #define AML_SCU_CONTROL_ENABLE 1 #define AML_SCU_CONFIG_REG 4 #define AML_SCU_CONFIG_NCPU_MASK 0x3 #define AML_SCU_CPU_PWR_STATUS_REG 8 #define AML_SCU_CPU_PWR_STATUS_CPU3_MASK (3 << 24) #define AML_SCU_CPU_PWR_STATUS_CPU2_MASK (3 << 16) #define AML_SCU_CPU_PWR_STATUS_CPU1_MASK (3 << 8) #define AML_SCU_CPU_PWR_STATUS_CPU0_MASK 3 #define AML_SCU_INV_TAGS_REG 12 #define AML_SCU_DIAG_CONTROL_REG 48 #define AML_SCU_DIAG_CONTROL_DISABLE_MIGBIT 1 #define AML_CPUCONF_CONTROL_REG 0 #define AML_CPUCONF_CPU1_ADDR_REG 4 #define AML_CPUCONF_CPU2_ADDR_REG 8 #define AML_CPUCONF_CPU3_ADDR_REG 12 /* aobus */ #define AML_M8_CPU_PWR_CNTL0_REG 0xe0 #define AML_M8B_CPU_PWR_CNTL0_MODE_CPU3_MASK (3 << 22) #define AML_M8B_CPU_PWR_CNTL0_MODE_CPU2_MASK (3 << 20) #define AML_M8B_CPU_PWR_CNTL0_MODE_CPU1_MASK (3 << 18) #define AML_M8_CPU_PWR_CNTL0_ISO_CPU3 (1 << 3) #define AML_M8_CPU_PWR_CNTL0_ISO_CPU2 (1 << 2) #define AML_M8_CPU_PWR_CNTL0_ISO_CPU1 (1 << 1) #define AML_M8_CPU_PWR_CNTL1_REG 0xe4 #define AML_M8B_CPU_PWR_CNTL1_PWR_CPU3 (1 << 19) #define AML_M8B_CPU_PWR_CNTL1_PWR_CPU2 (1 << 18) #define AML_M8B_CPU_PWR_CNTL1_PWR_CPU1 (1 << 17) #define AML_M8_CPU_PWR_CNTL1_MODE_CPU3_MASK (3 << 8) #define AML_M8_CPU_PWR_CNTL1_MODE_CPU2_MASK (3 << 6) #define AML_M8_CPU_PWR_CNTL1_MODE_CPU1_MASK (3 << 4) #define AML_M8B_CPU_PWR_MEM_PD0_REG 0xf4 #define AML_M8B_CPU_PWR_MEM_PD0_CPU3 (0xf << 20) #define AML_M8B_CPU_PWR_MEM_PD0_CPU2 (0xf << 24) #define AML_M8B_CPU_PWR_MEM_PD0_CPU1 (0xf << 28) /* cbus */ #define AML_SOC_CPU_CLK_CNTL_REG 0x419c #define AML_M8_CPU_CLK_CNTL_RESET_CPU3 (1 << 27) #define AML_M8_CPU_CLK_CNTL_RESET_CPU2 (1 << 26) #define AML_M8_CPU_CLK_CNTL_RESET_CPU1 (1 << 25) #define SCU_WRITE_4(reg, value) bus_write_4(&aml8726_smp.scu_res, \ (reg), (value)) #define SCU_READ_4(reg) bus_read_4(&aml8726_smp.scu_res, (reg)) #define SCU_BARRIER(reg) bus_barrier(&aml8726_smp.scu_res, \ (reg), 4, (BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE)) #define CPUCONF_WRITE_4(reg, value) bus_write_4(&aml8726_smp.cpucfg_res, \ (reg), (value)) #define CPUCONF_READ_4(reg) bus_read_4(&aml8726_smp.cpucfg_res, \ (reg)) #define CPUCONF_BARRIER(reg) bus_barrier(&aml8726_smp.cpucfg_res, \ (reg), 4, (BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE)) #define AOBUS_WRITE_4(reg, value) bus_write_4(&aml8726_smp.aobus_res, \ (reg), (value)) #define AOBUS_READ_4(reg) bus_read_4(&aml8726_smp.aobus_res, \ (reg)) #define AOBUS_BARRIER(reg) bus_barrier(&aml8726_smp.aobus_res, \ (reg), 4, (BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE)) #define CBUS_WRITE_4(reg, value) bus_write_4(&aml8726_smp.cbus_res, \ (reg), (value)) #define CBUS_READ_4(reg) bus_read_4(&aml8726_smp.cbus_res, \ (reg)) #define CBUS_BARRIER(reg) bus_barrier(&aml8726_smp.cbus_res, \ (reg), 4, (BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE)) static phandle_t find_node_for_device(const char *device, const char **compatible) { int i; phandle_t node; /* * Try to access the node directly i.e. through /aliases/. */ - if ((node = OF_finddevice(device)) != 0) + if ((node = OF_finddevice(device)) != -1) for (i = 0; compatible[i]; i++) if (fdt_is_compatible_strict(node, compatible[i])) return node; /* * Find the node the long way. */ for (i = 0; compatible[i]; i++) { - if ((node = OF_finddevice("/soc")) == 0) + if ((node = OF_finddevice("/soc")) == -1) return (0); if ((node = fdt_find_compatible(node, compatible[i], 1)) != 0) return node; } return (0); } static int alloc_resource_for_node(phandle_t node, struct resource *res, u_long *size) { int err; u_long pbase, psize; u_long start; if ((err = fdt_get_range(OF_parent(node), 0, &pbase, &psize)) != 0 || (err = fdt_regsize(node, &start, size)) != 0) return (err); start += pbase; memset(res, 0, sizeof(*res)); res->r_bustag = fdtbus_bs_tag; err = bus_space_map(res->r_bustag, start, *size, 0, &res->r_bushandle); return (err); } static void power_on_cpu(int cpu) { uint32_t scpsr; uint32_t value; if (cpu <= 0) return; /* * Power on the CPU if the intricate details are known, otherwise * just hope for the best (it may have already be powered on by * the hardware / firmware). */ switch (aml8726_soc_hw_rev) { case AML_SOC_HW_REV_M8: case AML_SOC_HW_REV_M8B: /* * Set the SCU power status for the CPU to normal mode. */ scpsr = SCU_READ_4(AML_SCU_CPU_PWR_STATUS_REG); scpsr &= ~(AML_SCU_CPU_PWR_STATUS_CPU1_MASK << ((cpu - 1) * 8)); SCU_WRITE_4(AML_SCU_CPU_PWR_STATUS_REG, scpsr); SCU_BARRIER(AML_SCU_CPU_PWR_STATUS_REG); if (aml8726_soc_hw_rev == AML_SOC_HW_REV_M8B) { /* * Reset may cause the current power status from the * actual CPU to be written to the SCU (over-writing * the value we've just written) so set it to normal * mode as well. */ value = AOBUS_READ_4(AML_M8_CPU_PWR_CNTL0_REG); value &= ~(AML_M8B_CPU_PWR_CNTL0_MODE_CPU1_MASK << ((cpu - 1) * 2)); AOBUS_WRITE_4(AML_M8_CPU_PWR_CNTL0_REG, value); AOBUS_BARRIER(AML_M8_CPU_PWR_CNTL0_REG); } DELAY(5); /* * Assert reset. */ value = CBUS_READ_4(AML_SOC_CPU_CLK_CNTL_REG); value |= AML_M8_CPU_CLK_CNTL_RESET_CPU1 << (cpu - 1); CBUS_WRITE_4(AML_SOC_CPU_CLK_CNTL_REG, value); CBUS_BARRIER(AML_SOC_CPU_CLK_CNTL_REG); if (aml8726_soc_hw_rev == AML_SOC_HW_REV_M8B) { /* * Release RAM pull-down. */ value = AOBUS_READ_4(AML_M8B_CPU_PWR_MEM_PD0_REG); value &= ~((uint32_t)AML_M8B_CPU_PWR_MEM_PD0_CPU1 >> ((cpu - 1) * 4)); AOBUS_WRITE_4(AML_M8B_CPU_PWR_MEM_PD0_REG, value); AOBUS_BARRIER(AML_M8B_CPU_PWR_MEM_PD0_REG); } /* * Power on CPU. */ value = AOBUS_READ_4(AML_M8_CPU_PWR_CNTL1_REG); value &= ~(AML_M8_CPU_PWR_CNTL1_MODE_CPU1_MASK << ((cpu - 1) * 2)); AOBUS_WRITE_4(AML_M8_CPU_PWR_CNTL1_REG, value); AOBUS_BARRIER(AML_M8_CPU_PWR_CNTL1_REG); DELAY(10); if (aml8726_soc_hw_rev == AML_SOC_HW_REV_M8B) { /* * Wait for power on confirmation. */ for ( ; ; ) { value = AOBUS_READ_4(AML_M8_CPU_PWR_CNTL1_REG); value &= AML_M8B_CPU_PWR_CNTL1_PWR_CPU1 << (cpu - 1); if (value) break; DELAY(10); } } /* * Release peripheral clamp. */ value = AOBUS_READ_4(AML_M8_CPU_PWR_CNTL0_REG); value &= ~(AML_M8_CPU_PWR_CNTL0_ISO_CPU1 << (cpu - 1)); AOBUS_WRITE_4(AML_M8_CPU_PWR_CNTL0_REG, value); AOBUS_BARRIER(AML_M8_CPU_PWR_CNTL0_REG); /* * Release reset. */ value = CBUS_READ_4(AML_SOC_CPU_CLK_CNTL_REG); value &= ~(AML_M8_CPU_CLK_CNTL_RESET_CPU1 << (cpu - 1)); CBUS_WRITE_4(AML_SOC_CPU_CLK_CNTL_REG, value); CBUS_BARRIER(AML_SOC_CPU_CLK_CNTL_REG); if (aml8726_soc_hw_rev == AML_SOC_HW_REV_M8B) { /* * The Amlogic Linux platform code sets the SCU power * status for the CPU again for some reason so we * follow suit (perhaps in case the reset caused * a stale power status from the actual CPU to be * written to the SCU). */ SCU_WRITE_4(AML_SCU_CPU_PWR_STATUS_REG, scpsr); SCU_BARRIER(AML_SCU_CPU_PWR_STATUS_REG); } break; default: break; } } void platform_mp_setmaxid(void) { int err; int i; int ncpu; phandle_t cpucfg_node; phandle_t scu_node; uint32_t value; if (mp_ncpus != 0) return; ncpu = 1; /* * Is the hardware necessary for SMP present? */ if ((scu_node = find_node_for_device("scu", scu_compatible)) == 0) goto moveon; if ((cpucfg_node = find_node_for_device("cpuconfig", cpucfg_compatible)) == 0) goto moveon; if (alloc_resource_for_node(scu_node, &aml8726_smp.scu_res, &aml8726_smp.scu_size) != 0) panic("Could not allocate resource for SCU"); if (alloc_resource_for_node(cpucfg_node, &aml8726_smp.cpucfg_res, &aml8726_smp.cpucfg_size) != 0) panic("Could not allocate resource for CPUCONFIG"); /* * Strictly speaking the aobus and cbus may not be required in * order to start an AP (it depends on the processor), however * always mapping them in simplifies the code. */ aml8726_smp.aobus_res.r_bustag = fdtbus_bs_tag; err = bus_space_map(aml8726_smp.aobus_res.r_bustag, AML_SOC_AOBUS_BASE_ADDR, 0x100000, 0, &aml8726_smp.aobus_res.r_bushandle); if (err) panic("Could not allocate resource for AOBUS"); aml8726_smp.cbus_res.r_bustag = fdtbus_bs_tag; err = bus_space_map(aml8726_smp.cbus_res.r_bustag, AML_SOC_CBUS_BASE_ADDR, 0x100000, 0, &aml8726_smp.cbus_res.r_bushandle); if (err) panic("Could not allocate resource for CBUS"); aml8726_smp.errata_764369 = false; for (i = 0; scu_errata_764369[i]; i++) if (fdt_is_compatible_strict(scu_node, scu_errata_764369[i])) { aml8726_smp.errata_764369 = true; break; } /* * Read the number of CPUs present. */ value = SCU_READ_4(AML_SCU_CONFIG_REG); ncpu = (value & AML_SCU_CONFIG_NCPU_MASK) + 1; moveon: mp_ncpus = ncpu; mp_maxid = ncpu - 1; } void platform_mp_start_ap(void) { int i; uint32_t reg; uint32_t value; vm_paddr_t paddr; if (mp_ncpus < 2) return; /* * Invalidate SCU cache tags. The 0x0000ffff constant invalidates * all ways on all cores 0-3. Per the ARM docs, it's harmless to * write to the bits for cores that are not present. */ SCU_WRITE_4(AML_SCU_INV_TAGS_REG, 0x0000ffff); if (aml8726_smp.errata_764369) { /* * Erratum ARM/MP: 764369 (problems with cache maintenance). * Setting the "disable-migratory bit" in the undocumented SCU * Diagnostic Control Register helps work around the problem. */ value = SCU_READ_4(AML_SCU_DIAG_CONTROL_REG); value |= AML_SCU_DIAG_CONTROL_DISABLE_MIGBIT; SCU_WRITE_4(AML_SCU_DIAG_CONTROL_REG, value); } /* * Enable the SCU, then clean the cache on this core. After these * two operations the cache tag ram in the SCU is coherent with * the contents of the cache on this core. The other cores aren't * running yet so their caches can't contain valid data yet, however * we've initialized their SCU tag ram above, so they will be * coherent from startup. */ value = SCU_READ_4(AML_SCU_CONTROL_REG); value |= AML_SCU_CONTROL_ENABLE; SCU_WRITE_4(AML_SCU_CONTROL_REG, value); SCU_BARRIER(AML_SCU_CONTROL_REG); dcache_wbinv_poc_all(); /* Set the boot address and power on each AP. */ paddr = pmap_kextract((vm_offset_t)mpentry); for (i = 1; i < mp_ncpus; i++) { reg = AML_CPUCONF_CPU1_ADDR_REG + ((i - 1) * 4); CPUCONF_WRITE_4(reg, paddr); CPUCONF_BARRIER(reg); power_on_cpu(i); } /* * Enable the APs. * * The Amlogic Linux platform code sets the lsb for some reason * in addition to the enable bit for each AP so we follow suit * (the lsb may be the enable bit for the BP, though in that case * it should already be set since it's currently running). */ value = CPUCONF_READ_4(AML_CPUCONF_CONTROL_REG); value |= 1; for (i = 1; i < mp_ncpus; i++) value |= (1 << i); CPUCONF_WRITE_4(AML_CPUCONF_CONTROL_REG, value); CPUCONF_BARRIER(AML_CPUCONF_CONTROL_REG); /* Wakeup the now enabled APs */ dsb(); sev(); /* * Free the resources which are not needed after startup. */ bus_space_unmap(aml8726_smp.scu_res.r_bustag, aml8726_smp.scu_res.r_bushandle, aml8726_smp.scu_size); bus_space_unmap(aml8726_smp.cpucfg_res.r_bustag, aml8726_smp.cpucfg_res.r_bushandle, aml8726_smp.cpucfg_size); bus_space_unmap(aml8726_smp.aobus_res.r_bustag, aml8726_smp.aobus_res.r_bushandle, 0x100000); bus_space_unmap(aml8726_smp.cbus_res.r_bustag, aml8726_smp.cbus_res.r_bushandle, 0x100000); memset(&aml8726_smp, 0, sizeof(aml8726_smp)); } /* * Stub drivers for cosmetic purposes. */ struct aml8726_scu_softc { device_t dev; }; static int aml8726_scu_probe(device_t dev) { int i; for (i = 0; scu_compatible[i]; i++) if (ofw_bus_is_compatible(dev, scu_compatible[i])) break; if (!scu_compatible[i]) return (ENXIO); device_set_desc(dev, "ARM Snoop Control Unit"); return (BUS_PROBE_DEFAULT); } static int aml8726_scu_attach(device_t dev) { struct aml8726_scu_softc *sc = device_get_softc(dev); sc->dev = dev; return (0); } static int aml8726_scu_detach(device_t dev) { return (0); } static device_method_t aml8726_scu_methods[] = { /* Device interface */ DEVMETHOD(device_probe, aml8726_scu_probe), DEVMETHOD(device_attach, aml8726_scu_attach), DEVMETHOD(device_detach, aml8726_scu_detach), DEVMETHOD_END }; static driver_t aml8726_scu_driver = { "scu", aml8726_scu_methods, sizeof(struct aml8726_scu_softc), }; static devclass_t aml8726_scu_devclass; EARLY_DRIVER_MODULE(scu, simplebus, aml8726_scu_driver, aml8726_scu_devclass, 0, 0, BUS_PASS_CPU + BUS_PASS_ORDER_MIDDLE); struct aml8726_cpucfg_softc { device_t dev; }; static int aml8726_cpucfg_probe(device_t dev) { int i; for (i = 0; cpucfg_compatible[i]; i++) if (ofw_bus_is_compatible(dev, cpucfg_compatible[i])) break; if (!cpucfg_compatible[i]) return (ENXIO); device_set_desc(dev, "Amlogic CPU Config"); return (BUS_PROBE_DEFAULT); } static int aml8726_cpucfg_attach(device_t dev) { struct aml8726_cpucfg_softc *sc = device_get_softc(dev); sc->dev = dev; return (0); } static int aml8726_cpucfg_detach(device_t dev) { return (0); } static device_method_t aml8726_cpucfg_methods[] = { /* Device interface */ DEVMETHOD(device_probe, aml8726_cpucfg_probe), DEVMETHOD(device_attach, aml8726_cpucfg_attach), DEVMETHOD(device_detach, aml8726_cpucfg_detach), DEVMETHOD_END }; static driver_t aml8726_cpucfg_driver = { "cpuconfig", aml8726_cpucfg_methods, sizeof(struct aml8726_cpucfg_softc), }; static devclass_t aml8726_cpucfg_devclass; EARLY_DRIVER_MODULE(cpuconfig, simplebus, aml8726_cpucfg_driver, aml8726_cpucfg_devclass, 0, 0, BUS_PASS_CPU + BUS_PASS_ORDER_MIDDLE); Index: head/sys/arm/amlogic/aml8726/aml8726_usb_phy-m3.c =================================================================== --- head/sys/arm/amlogic/aml8726/aml8726_usb_phy-m3.c (revision 331228) +++ head/sys/arm/amlogic/aml8726/aml8726_usb_phy-m3.c (revision 331229) @@ -1,428 +1,428 @@ /*- * Copyright 2014-2015 John Wehle * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. */ /* * Amlogic aml8726-m3 USB physical layer driver. * * Both USB physical interfaces share the same configuration register. */ #include __FBSDID("$FreeBSD$"); #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include "gpio_if.h" struct aml8726_usb_phy_gpio { device_t dev; uint32_t pin; uint32_t pol; }; struct aml8726_usb_phy_softc { device_t dev; struct resource *res[1]; uint32_t npwr_en; struct aml8726_usb_phy_gpio *pwr_en; }; static struct resource_spec aml8726_usb_phy_spec[] = { { SYS_RES_MEMORY, 0, RF_ACTIVE }, { -1, 0 } }; #define AML_USB_PHY_CFG_REG 0 #define AML_USB_PHY_CFG_A_CLK_DETECTED (1U << 31) #define AML_USB_PHY_CFG_CLK_DIV_MASK (0x7f << 24) #define AML_USB_PHY_CFG_CLK_DIV_SHIFT 24 #define AML_USB_PHY_CFG_B_CLK_DETECTED (1 << 22) #define AML_USB_PHY_CFG_A_PLL_RST (1 << 19) #define AML_USB_PHY_CFG_A_PHYS_RST (1 << 18) #define AML_USB_PHY_CFG_A_RST (1 << 17) #define AML_USB_PHY_CFG_B_PLL_RST (1 << 13) #define AML_USB_PHY_CFG_B_PHYS_RST (1 << 12) #define AML_USB_PHY_CFG_B_RST (1 << 11) #define AML_USB_PHY_CFG_CLK_EN (1 << 8) #define AML_USB_PHY_CFG_CLK_SEL_MASK (7 << 5) #define AML_USB_PHY_CFG_CLK_SEL_XTAL (0 << 5) #define AML_USB_PHY_CFG_CLK_SEL_XTAL_DIV2 (1 << 5) #define AML_USB_PHY_CFG_B_POR (1 << 1) #define AML_USB_PHY_CFG_A_POR (1 << 0) #define AML_USB_PHY_CFG_CLK_DETECTED \ (AML_USB_PHY_CFG_A_CLK_DETECTED | AML_USB_PHY_CFG_B_CLK_DETECTED) #define AML_USB_PHY_MISC_A_REG 12 #define AML_USB_PHY_MISC_B_REG 16 #define AML_USB_PHY_MISC_ID_OVERIDE_EN (1 << 23) #define AML_USB_PHY_MISC_ID_OVERIDE_DEVICE (1 << 22) #define AML_USB_PHY_MISC_ID_OVERIDE_HOST (0 << 22) #define CSR_WRITE_4(sc, reg, val) bus_write_4((sc)->res[0], reg, (val)) #define CSR_READ_4(sc, reg) bus_read_4((sc)->res[0], reg) #define CSR_BARRIER(sc, reg) bus_barrier((sc)->res[0], reg, 4, \ (BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE)) #define PIN_ON_FLAG(pol) ((pol) == 0 ? \ GPIO_PIN_LOW : GPIO_PIN_HIGH) #define PIN_OFF_FLAG(pol) ((pol) == 0 ? \ GPIO_PIN_HIGH : GPIO_PIN_LOW) static int aml8726_usb_phy_mode(const char *dwcotg_path, uint32_t *mode) { char *usb_mode; phandle_t node; ssize_t len; - if ((node = OF_finddevice(dwcotg_path)) == 0) + if ((node = OF_finddevice(dwcotg_path)) == -1) return (ENXIO); if (fdt_is_compatible_strict(node, "synopsys,designware-hs-otg2") == 0) return (ENXIO); *mode = 0; len = OF_getprop_alloc(node, "dr_mode", sizeof(char), (void **)&usb_mode); if (len <= 0) return (0); if (strcasecmp(usb_mode, "host") == 0) { *mode = AML_USB_PHY_MISC_ID_OVERIDE_EN | AML_USB_PHY_MISC_ID_OVERIDE_HOST; } else if (strcasecmp(usb_mode, "peripheral") == 0) { *mode = AML_USB_PHY_MISC_ID_OVERIDE_EN | AML_USB_PHY_MISC_ID_OVERIDE_DEVICE; } OF_prop_free(usb_mode); return (0); } static int aml8726_usb_phy_probe(device_t dev) { if (!ofw_bus_status_okay(dev)) return (ENXIO); if (!ofw_bus_is_compatible(dev, "amlogic,aml8726-m3-usb-phy")) return (ENXIO); device_set_desc(dev, "Amlogic aml8726-m3 USB PHY"); return (BUS_PROBE_DEFAULT); } static int aml8726_usb_phy_attach(device_t dev) { struct aml8726_usb_phy_softc *sc = device_get_softc(dev); int err; int npwr_en; pcell_t *prop; phandle_t node; ssize_t len; uint32_t div; uint32_t i; uint32_t mode_a; uint32_t mode_b; uint32_t value; sc->dev = dev; if (aml8726_usb_phy_mode("/soc/usb@c9040000", &mode_a) != 0) { device_printf(dev, "missing usb@c9040000 node in FDT\n"); return (ENXIO); } if (aml8726_usb_phy_mode("/soc/usb@c90c0000", &mode_b) != 0) { device_printf(dev, "missing usb@c90c0000 node in FDT\n"); return (ENXIO); } if (bus_alloc_resources(dev, aml8726_usb_phy_spec, sc->res)) { device_printf(dev, "can not allocate resources for device\n"); return (ENXIO); } node = ofw_bus_get_node(dev); err = 0; len = OF_getencprop_alloc(node, "usb-pwr-en", 3 * sizeof(pcell_t), (void **)&prop); npwr_en = (len > 0) ? len : 0; sc->npwr_en = 0; sc->pwr_en = (struct aml8726_usb_phy_gpio *) malloc(npwr_en * sizeof (*sc->pwr_en), M_DEVBUF, M_WAITOK); for (i = 0; i < npwr_en; i++) { sc->pwr_en[i].dev = OF_device_from_xref(prop[i * 3]); sc->pwr_en[i].pin = prop[i * 3 + 1]; sc->pwr_en[i].pol = prop[i * 3 + 2]; if (sc->pwr_en[i].dev == NULL) { err = 1; break; } } OF_prop_free(prop); if (err) { device_printf(dev, "unable to parse gpio\n"); goto fail; } /* Turn on power by setting pin and then enabling output driver. */ for (i = 0; i < npwr_en; i++) { if (GPIO_PIN_SET(sc->pwr_en[i].dev, sc->pwr_en[i].pin, PIN_ON_FLAG(sc->pwr_en[i].pol)) != 0 || GPIO_PIN_SETFLAGS(sc->pwr_en[i].dev, sc->pwr_en[i].pin, GPIO_PIN_OUTPUT) != 0) { device_printf(dev, "could not use gpio to control power\n"); goto fail; } sc->npwr_en++; } /* * Configure the clock source and divider. */ div = 2; value = CSR_READ_4(sc, AML_USB_PHY_CFG_REG); value &= ~(AML_USB_PHY_CFG_CLK_DIV_MASK | AML_USB_PHY_CFG_CLK_SEL_MASK); value &= ~(AML_USB_PHY_CFG_A_RST | AML_USB_PHY_CFG_B_RST); value &= ~(AML_USB_PHY_CFG_A_PLL_RST | AML_USB_PHY_CFG_B_PLL_RST); value &= ~(AML_USB_PHY_CFG_A_PHYS_RST | AML_USB_PHY_CFG_B_PHYS_RST); value &= ~(AML_USB_PHY_CFG_A_POR | AML_USB_PHY_CFG_B_POR); value |= AML_USB_PHY_CFG_CLK_SEL_XTAL; value |= ((div - 1) << AML_USB_PHY_CFG_CLK_DIV_SHIFT) & AML_USB_PHY_CFG_CLK_DIV_MASK; value |= AML_USB_PHY_CFG_CLK_EN; CSR_WRITE_4(sc, AML_USB_PHY_CFG_REG, value); CSR_BARRIER(sc, AML_USB_PHY_CFG_REG); /* * Issue the reset sequence. */ value |= (AML_USB_PHY_CFG_A_RST | AML_USB_PHY_CFG_B_RST); CSR_WRITE_4(sc, AML_USB_PHY_CFG_REG, value); CSR_BARRIER(sc, AML_USB_PHY_CFG_REG); DELAY(200); value &= ~(AML_USB_PHY_CFG_A_RST | AML_USB_PHY_CFG_B_RST); CSR_WRITE_4(sc, AML_USB_PHY_CFG_REG, value); CSR_BARRIER(sc, AML_USB_PHY_CFG_REG); DELAY(200); value |= (AML_USB_PHY_CFG_A_PLL_RST | AML_USB_PHY_CFG_B_PLL_RST); CSR_WRITE_4(sc, AML_USB_PHY_CFG_REG, value); CSR_BARRIER(sc, AML_USB_PHY_CFG_REG); DELAY(200); value &= ~(AML_USB_PHY_CFG_A_PLL_RST | AML_USB_PHY_CFG_B_PLL_RST); CSR_WRITE_4(sc, AML_USB_PHY_CFG_REG, value); CSR_BARRIER(sc, AML_USB_PHY_CFG_REG); DELAY(200); value |= (AML_USB_PHY_CFG_A_PHYS_RST | AML_USB_PHY_CFG_B_PHYS_RST); CSR_WRITE_4(sc, AML_USB_PHY_CFG_REG, value); CSR_BARRIER(sc, AML_USB_PHY_CFG_REG); DELAY(200); value &= ~(AML_USB_PHY_CFG_A_PHYS_RST | AML_USB_PHY_CFG_B_PHYS_RST); CSR_WRITE_4(sc, AML_USB_PHY_CFG_REG, value); CSR_BARRIER(sc, AML_USB_PHY_CFG_REG); DELAY(200); value |= (AML_USB_PHY_CFG_A_POR | AML_USB_PHY_CFG_B_POR); CSR_WRITE_4(sc, AML_USB_PHY_CFG_REG, value); CSR_BARRIER(sc, AML_USB_PHY_CFG_REG); DELAY(200); /* * Enable by clearing the power on reset. */ value &= ~(AML_USB_PHY_CFG_A_POR | AML_USB_PHY_CFG_B_POR); CSR_WRITE_4(sc, AML_USB_PHY_CFG_REG, value); CSR_BARRIER(sc, AML_USB_PHY_CFG_REG); DELAY(200); /* * Check if the clock was detected. */ value = CSR_READ_4(sc, AML_USB_PHY_CFG_REG); if ((value & AML_USB_PHY_CFG_CLK_DETECTED) != AML_USB_PHY_CFG_CLK_DETECTED) device_printf(dev, "PHY Clock not detected\n"); /* * Configure the mode for each port. */ value = CSR_READ_4(sc, AML_USB_PHY_MISC_A_REG); value &= ~(AML_USB_PHY_MISC_ID_OVERIDE_EN | AML_USB_PHY_MISC_ID_OVERIDE_DEVICE | AML_USB_PHY_MISC_ID_OVERIDE_HOST); value |= mode_a; CSR_WRITE_4(sc, AML_USB_PHY_MISC_A_REG, value); value = CSR_READ_4(sc, AML_USB_PHY_MISC_B_REG); value &= ~(AML_USB_PHY_MISC_ID_OVERIDE_EN | AML_USB_PHY_MISC_ID_OVERIDE_DEVICE | AML_USB_PHY_MISC_ID_OVERIDE_HOST); value |= mode_b; CSR_WRITE_4(sc, AML_USB_PHY_MISC_B_REG, value); CSR_BARRIER(sc, AML_USB_PHY_MISC_B_REG); return (0); fail: /* In the event of problems attempt to turn things back off. */ i = sc->npwr_en; while (i-- != 0) { GPIO_PIN_SET(sc->pwr_en[i].dev, sc->pwr_en[i].pin, PIN_OFF_FLAG(sc->pwr_en[i].pol)); } free (sc->pwr_en, M_DEVBUF); sc->pwr_en = NULL; bus_release_resources(dev, aml8726_usb_phy_spec, sc->res); return (ENXIO); } static int aml8726_usb_phy_detach(device_t dev) { struct aml8726_usb_phy_softc *sc = device_get_softc(dev); uint32_t i; uint32_t value; /* * Disable by issuing a power on reset. */ value = CSR_READ_4(sc, AML_USB_PHY_CFG_REG); value |= (AML_USB_PHY_CFG_A_POR | AML_USB_PHY_CFG_B_POR); CSR_WRITE_4(sc, AML_USB_PHY_CFG_REG, value); CSR_BARRIER(sc, AML_USB_PHY_CFG_REG); /* Turn off power */ i = sc->npwr_en; while (i-- != 0) { (void)GPIO_PIN_SET(sc->pwr_en[i].dev, sc->pwr_en[i].pin, PIN_OFF_FLAG(sc->pwr_en[i].pol)); } free (sc->pwr_en, M_DEVBUF); sc->pwr_en = NULL; bus_release_resources(dev, aml8726_usb_phy_spec, sc->res); return (0); } static device_method_t aml8726_usb_phy_methods[] = { /* Device interface */ DEVMETHOD(device_probe, aml8726_usb_phy_probe), DEVMETHOD(device_attach, aml8726_usb_phy_attach), DEVMETHOD(device_detach, aml8726_usb_phy_detach), DEVMETHOD_END }; static driver_t aml8726_usb_phy_driver = { "usbphy", aml8726_usb_phy_methods, sizeof(struct aml8726_usb_phy_softc), }; static devclass_t aml8726_usb_phy_devclass; DRIVER_MODULE(aml8726_m3usbphy, simplebus, aml8726_usb_phy_driver, aml8726_usb_phy_devclass, 0, 0); MODULE_DEPEND(aml8726_m3usbphy, aml8726_gpio, 1, 1, 1); Index: head/sys/arm/annapurna/alpine/alpine_machdep.c =================================================================== --- head/sys/arm/annapurna/alpine/alpine_machdep.c (revision 331228) +++ head/sys/arm/annapurna/alpine/alpine_machdep.c (revision 331229) @@ -1,162 +1,162 @@ /*- * Copyright (c) 2013 Ruslan Bukin * Copyright (c) 2015 Semihalf * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. * */ #include "opt_ddb.h" #include "opt_platform.h" #include __FBSDID("$FreeBSD$"); #include #include #include #include #include #include #include #include #include #include #include #include #include "platform_if.h" #define WDTLOAD 0x000 #define LOAD_MIN 0x00000001 #define LOAD_MAX 0xFFFFFFFF #define WDTVALUE 0x004 #define WDTCONTROL 0x008 /* control register masks */ #define INT_ENABLE (1 << 0) #define RESET_ENABLE (1 << 1) #define WDTLOCK 0xC00 #define UNLOCK 0x1ACCE551 #define LOCK 0x00000001 bus_addr_t al_devmap_pa; bus_addr_t al_devmap_size; static int alpine_get_devmap_base(bus_addr_t *pa, bus_addr_t *size) { phandle_t node; - if ((node = OF_finddevice("/")) == 0) + if ((node = OF_finddevice("/")) == -1) return (ENXIO); if ((node = fdt_find_compatible(node, "simple-bus", 1)) == 0) return (ENXIO); return fdt_get_range(node, 0, pa, size); } static int alpine_get_wdt_base(uint32_t *pbase, uint32_t *psize) { phandle_t node; u_long base = 0; u_long size = 0; if (pbase == NULL || psize == NULL) return (EINVAL); if ((node = OF_finddevice("/")) == -1) return (EFAULT); if ((node = fdt_find_compatible(node, "simple-bus", 1)) == 0) return (EFAULT); if ((node = fdt_find_compatible(node, "arm,sp805", 1)) == 0) return (EFAULT); if (fdt_regsize(node, &base, &size)) return (EFAULT); *pbase = base; *psize = size; return (0); } /* * Construct devmap table with DT-derived config data. */ static int alpine_devmap_init(platform_t plat) { alpine_get_devmap_base(&al_devmap_pa, &al_devmap_size); devmap_add_entry(al_devmap_pa, al_devmap_size); return (0); } static void alpine_cpu_reset(platform_t plat) { uint32_t wdbase, wdsize; bus_addr_t wdbaddr; int ret; ret = alpine_get_wdt_base(&wdbase, &wdsize); if (ret) { printf("Unable to get WDT base, do power down manually..."); goto infinite; } ret = bus_space_map(fdtbus_bs_tag, al_devmap_pa + wdbase, wdsize, 0, &wdbaddr); if (ret) { printf("Unable to map WDT base, do power down manually..."); goto infinite; } bus_space_write_4(fdtbus_bs_tag, wdbaddr, WDTLOCK, UNLOCK); bus_space_write_4(fdtbus_bs_tag, wdbaddr, WDTLOAD, LOAD_MIN); bus_space_write_4(fdtbus_bs_tag, wdbaddr, WDTCONTROL, INT_ENABLE | RESET_ENABLE); infinite: while (1) {} } static platform_method_t alpine_methods[] = { PLATFORMMETHOD(platform_devmap_init, alpine_devmap_init), PLATFORMMETHOD(platform_cpu_reset, alpine_cpu_reset), #ifdef SMP PLATFORMMETHOD(platform_mp_start_ap, alpine_mp_start_ap), PLATFORMMETHOD(platform_mp_setmaxid, alpine_mp_setmaxid), #endif PLATFORMMETHOD_END, }; FDT_PLATFORM_DEF(alpine, "alpine", 0, "annapurna,alpine", 200); Index: head/sys/arm/broadcom/bcm2835/bcm2835_fb.c =================================================================== --- head/sys/arm/broadcom/bcm2835/bcm2835_fb.c (revision 331228) +++ head/sys/arm/broadcom/bcm2835/bcm2835_fb.c (revision 331229) @@ -1,871 +1,871 @@ /*- * SPDX-License-Identifier: BSD-2-Clause-FreeBSD * * Copyright (c) 2012 Oleksandr Tymoshenko * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. * */ #include __FBSDID("$FreeBSD$"); #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include "mbox_if.h" struct argb { uint8_t a; uint8_t r; uint8_t g; uint8_t b; }; static struct argb bcmfb_palette[16] = { {0x00, 0x00, 0x00, 0x00}, {0x00, 0x00, 0x00, 0xaa}, {0x00, 0x00, 0xaa, 0x00}, {0x00, 0x00, 0xaa, 0xaa}, {0x00, 0xaa, 0x00, 0x00}, {0x00, 0xaa, 0x00, 0xaa}, {0x00, 0xaa, 0x55, 0x00}, {0x00, 0xaa, 0xaa, 0xaa}, {0x00, 0x55, 0x55, 0x55}, {0x00, 0x55, 0x55, 0xff}, {0x00, 0x55, 0xff, 0x55}, {0x00, 0x55, 0xff, 0xff}, {0x00, 0xff, 0x55, 0x55}, {0x00, 0xff, 0x55, 0xff}, {0x00, 0xff, 0xff, 0x55}, {0x00, 0xff, 0xff, 0xff} }; /* mouse pointer from dev/syscons/scgfbrndr.c */ static u_char mouse_pointer[16] = { 0x00, 0x40, 0x60, 0x70, 0x78, 0x7c, 0x7e, 0x68, 0x0c, 0x0c, 0x06, 0x06, 0x00, 0x00, 0x00, 0x00 }; #define BCMFB_FONT_HEIGHT 16 #define BCMFB_FONT_WIDTH 8 #define FB_WIDTH 640 #define FB_HEIGHT 480 #define FB_DEPTH 24 struct bcmsc_softc { /* Videoadpater part */ video_adapter_t va; intptr_t fb_addr; intptr_t fb_paddr; unsigned int fb_size; unsigned int height; unsigned int width; unsigned int depth; unsigned int stride; unsigned int xmargin; unsigned int ymargin; unsigned char *font; int fbswap; int initialized; }; static struct bcmsc_softc bcmsc; static struct ofw_compat_data compat_data[] = { {"broadcom,bcm2835-fb", 1}, {"brcm,bcm2708-fb", 1}, {NULL, 0} }; static int bcm_fb_probe(device_t); static int bcm_fb_attach(device_t); static void bcmfb_update_margins(video_adapter_t *adp); static int bcmfb_configure(int); static int bcm_fb_probe(device_t dev) { int error; if (ofw_bus_search_compatible(dev, compat_data)->ocd_data == 0) return (ENXIO); device_set_desc(dev, "BCM2835 framebuffer device"); error = sc_probe_unit(device_get_unit(dev), device_get_flags(dev) | SC_AUTODETECT_KBD); if (error != 0) return (error); return (BUS_PROBE_DEFAULT); } static int bcm_fb_attach(device_t dev) { struct bcm2835_fb_config fb; struct bcmsc_softc *sc; sc = (struct bcmsc_softc *)vid_get_adapter(vid_find_adapter( "bcmfb", 0)); if (sc != NULL) device_set_softc(dev, sc); else sc = device_get_softc(dev); memset(&fb, 0, sizeof(fb)); if (bcm2835_mbox_fb_get_w_h(&fb) != 0) return (ENXIO); fb.bpp = FB_DEPTH; fb.vxres = fb.xres; fb.vyres = fb.yres; fb.xoffset = fb.yoffset = 0; if (bcm2835_mbox_fb_init(&fb) != 0) return (ENXIO); sc->fb_addr = (intptr_t)pmap_mapdev(fb.base, fb.size); sc->fb_paddr = fb.base; sc->fb_size = fb.size; sc->depth = fb.bpp; sc->stride = fb.pitch; sc->width = fb.xres; sc->height = fb.yres; bcmfb_update_margins(&sc->va); if (sc_attach_unit(device_get_unit(dev), device_get_flags(dev) | SC_AUTODETECT_KBD) != 0) { device_printf(dev, "failed to attach syscons\n"); return (ENXIO); } device_printf(dev, "%dx%d(%dx%d@%d,%d) %dbpp\n", fb.xres, fb.yres, fb.vxres, fb.vyres, fb.xoffset, fb.yoffset, fb.bpp); device_printf(dev, "fbswap: %d, pitch %d, base 0x%08x, screen_size %d\n", sc->fbswap, fb.pitch, fb.base, fb.size); return (0); } static device_method_t bcm_fb_methods[] = { /* Device interface */ DEVMETHOD(device_probe, bcm_fb_probe), DEVMETHOD(device_attach, bcm_fb_attach), { 0, 0 } }; static devclass_t bcm_fb_devclass; static driver_t bcm_fb_driver = { "fb", bcm_fb_methods, sizeof(struct bcmsc_softc), }; DRIVER_MODULE(bcm2835fb, ofwbus, bcm_fb_driver, bcm_fb_devclass, 0, 0); DRIVER_MODULE(bcm2835fb, simplebus, bcm_fb_driver, bcm_fb_devclass, 0, 0); /* * Video driver routines and glue. */ static vi_probe_t bcmfb_probe; static vi_init_t bcmfb_init; static vi_get_info_t bcmfb_get_info; static vi_query_mode_t bcmfb_query_mode; static vi_set_mode_t bcmfb_set_mode; static vi_save_font_t bcmfb_save_font; static vi_load_font_t bcmfb_load_font; static vi_show_font_t bcmfb_show_font; static vi_save_palette_t bcmfb_save_palette; static vi_load_palette_t bcmfb_load_palette; static vi_set_border_t bcmfb_set_border; static vi_save_state_t bcmfb_save_state; static vi_load_state_t bcmfb_load_state; static vi_set_win_org_t bcmfb_set_win_org; static vi_read_hw_cursor_t bcmfb_read_hw_cursor; static vi_set_hw_cursor_t bcmfb_set_hw_cursor; static vi_set_hw_cursor_shape_t bcmfb_set_hw_cursor_shape; static vi_blank_display_t bcmfb_blank_display; static vi_mmap_t bcmfb_mmap; static vi_ioctl_t bcmfb_ioctl; static vi_clear_t bcmfb_clear; static vi_fill_rect_t bcmfb_fill_rect; static vi_bitblt_t bcmfb_bitblt; static vi_diag_t bcmfb_diag; static vi_save_cursor_palette_t bcmfb_save_cursor_palette; static vi_load_cursor_palette_t bcmfb_load_cursor_palette; static vi_copy_t bcmfb_copy; static vi_putp_t bcmfb_putp; static vi_putc_t bcmfb_putc; static vi_puts_t bcmfb_puts; static vi_putm_t bcmfb_putm; static video_switch_t bcmfbvidsw = { .probe = bcmfb_probe, .init = bcmfb_init, .get_info = bcmfb_get_info, .query_mode = bcmfb_query_mode, .set_mode = bcmfb_set_mode, .save_font = bcmfb_save_font, .load_font = bcmfb_load_font, .show_font = bcmfb_show_font, .save_palette = bcmfb_save_palette, .load_palette = bcmfb_load_palette, .set_border = bcmfb_set_border, .save_state = bcmfb_save_state, .load_state = bcmfb_load_state, .set_win_org = bcmfb_set_win_org, .read_hw_cursor = bcmfb_read_hw_cursor, .set_hw_cursor = bcmfb_set_hw_cursor, .set_hw_cursor_shape = bcmfb_set_hw_cursor_shape, .blank_display = bcmfb_blank_display, .mmap = bcmfb_mmap, .ioctl = bcmfb_ioctl, .clear = bcmfb_clear, .fill_rect = bcmfb_fill_rect, .bitblt = bcmfb_bitblt, .diag = bcmfb_diag, .save_cursor_palette = bcmfb_save_cursor_palette, .load_cursor_palette = bcmfb_load_cursor_palette, .copy = bcmfb_copy, .putp = bcmfb_putp, .putc = bcmfb_putc, .puts = bcmfb_puts, .putm = bcmfb_putm, }; VIDEO_DRIVER(bcmfb, bcmfbvidsw, bcmfb_configure); static vr_init_t bcmrend_init; static vr_clear_t bcmrend_clear; static vr_draw_border_t bcmrend_draw_border; static vr_draw_t bcmrend_draw; static vr_set_cursor_t bcmrend_set_cursor; static vr_draw_cursor_t bcmrend_draw_cursor; static vr_blink_cursor_t bcmrend_blink_cursor; static vr_set_mouse_t bcmrend_set_mouse; static vr_draw_mouse_t bcmrend_draw_mouse; /* * We use our own renderer; this is because we must emulate a hardware * cursor. */ static sc_rndr_sw_t bcmrend = { bcmrend_init, bcmrend_clear, bcmrend_draw_border, bcmrend_draw, bcmrend_set_cursor, bcmrend_draw_cursor, bcmrend_blink_cursor, bcmrend_set_mouse, bcmrend_draw_mouse }; RENDERER(bcmfb, 0, bcmrend, gfb_set); RENDERER_MODULE(bcmfb, gfb_set); static void bcmrend_init(scr_stat* scp) { } static void bcmrend_clear(scr_stat* scp, int c, int attr) { } static void bcmrend_draw_border(scr_stat* scp, int color) { } static void bcmrend_draw(scr_stat* scp, int from, int count, int flip) { video_adapter_t* adp = scp->sc->adp; int i, c, a; if (!flip) { /* Normal printing */ vidd_puts(adp, from, (uint16_t*)sc_vtb_pointer(&scp->vtb, from), count); } else { /* This is for selections and such: invert the color attribute */ for (i = count; i-- > 0; ++from) { c = sc_vtb_getc(&scp->vtb, from); a = sc_vtb_geta(&scp->vtb, from) >> 8; vidd_putc(adp, from, c, (a >> 4) | ((a & 0xf) << 4)); } } } static void bcmrend_set_cursor(scr_stat* scp, int base, int height, int blink) { } static void bcmrend_draw_cursor(scr_stat* scp, int off, int blink, int on, int flip) { int bytes, col, i, j, row; struct bcmsc_softc *sc; uint8_t *addr; video_adapter_t *adp; adp = scp->sc->adp; sc = (struct bcmsc_softc *)adp; if (scp->curs_attr.height <= 0) return; if (sc->fb_addr == 0) return; if (off >= adp->va_info.vi_width * adp->va_info.vi_height) return; /* calculate the coordinates in the video buffer */ row = (off / adp->va_info.vi_width) * adp->va_info.vi_cheight; col = (off % adp->va_info.vi_width) * adp->va_info.vi_cwidth; addr = (uint8_t *)sc->fb_addr + (row + sc->ymargin)*(sc->stride) + (sc->depth/8) * (col + sc->xmargin); bytes = sc->depth / 8; /* our cursor consists of simply inverting the char under it */ for (i = 0; i < adp->va_info.vi_cheight; i++) { for (j = 0; j < adp->va_info.vi_cwidth; j++) { switch (sc->depth) { case 32: case 24: addr[bytes*j + 2] ^= 0xff; /* FALLTHROUGH */ case 16: addr[bytes*j + 1] ^= 0xff; addr[bytes*j] ^= 0xff; break; default: break; } } addr += sc->stride; } } static void bcmrend_blink_cursor(scr_stat* scp, int at, int flip) { } static void bcmrend_set_mouse(scr_stat* scp) { } static void bcmrend_draw_mouse(scr_stat* scp, int x, int y, int on) { vidd_putm(scp->sc->adp, x, y, mouse_pointer, 0xffffffff, 16, 8); } static uint16_t bcmfb_static_window[ROW*COL]; extern u_char dflt_font_16[]; /* * Update videoadapter settings after changing resolution */ static void bcmfb_update_margins(video_adapter_t *adp) { struct bcmsc_softc *sc; video_info_t *vi; sc = (struct bcmsc_softc *)adp; vi = &adp->va_info; sc->xmargin = (sc->width - (vi->vi_width * vi->vi_cwidth)) / 2; sc->ymargin = (sc->height - (vi->vi_height * vi->vi_cheight)) / 2; } static int bcmfb_configure(int flags) { char bootargs[2048], *n, *p, *v; pcell_t cell; phandle_t chosen, display, root; struct bcmsc_softc *sc; sc = &bcmsc; if (sc->initialized) return (0); sc->width = 0; sc->height = 0; /* * It seems there is no way to let syscons framework know * that framebuffer resolution has changed. So just try * to fetch data from FDT bootargs, FDT display data and * finally go with defaults if everything else has failed. */ chosen = OF_finddevice("/chosen"); - if (chosen != 0 && + if (chosen != -1 && OF_getprop(chosen, "bootargs", &bootargs, sizeof(bootargs)) > 0) { p = bootargs; while ((v = strsep(&p, " ")) != NULL) { if (*v == '\0') continue; n = strsep(&v, "="); if (strcmp(n, "bcm2708_fb.fbwidth") == 0 && v != NULL) sc->width = (unsigned int)strtol(v, NULL, 0); else if (strcmp(n, "bcm2708_fb.fbheight") == 0 && v != NULL) sc->height = (unsigned int)strtol(v, NULL, 0); else if (strcmp(n, "bcm2708_fb.fbswap") == 0 && v != NULL) if (*v == '1') sc->fbswap = 1; } } root = OF_finddevice("/"); - if ((root != 0) && + if ((root != -1) && (display = fdt_find_compatible(root, "broadcom,bcm2835-fb", 1))) { if (sc->width == 0) { if ((OF_getencprop(display, "broadcom,width", &cell, sizeof(cell))) > 0) sc->width = cell; } if (sc->height == 0) { if ((OF_getencprop(display, "broadcom,height", &cell, sizeof(cell))) > 0) sc->height = cell; } } if (sc->width == 0) sc->width = FB_WIDTH; if (sc->height == 0) sc->height = FB_HEIGHT; bcmfb_init(0, &sc->va, 0); sc->initialized = 1; return (0); } static int bcmfb_probe(int unit, video_adapter_t **adp, void *arg, int flags) { return (0); } static int bcmfb_init(int unit, video_adapter_t *adp, int flags) { struct bcmsc_softc *sc; video_info_t *vi; sc = (struct bcmsc_softc *)adp; vi = &adp->va_info; vid_init_struct(adp, "bcmfb", -1, unit); sc->font = dflt_font_16; vi->vi_cheight = BCMFB_FONT_HEIGHT; vi->vi_cwidth = BCMFB_FONT_WIDTH; vi->vi_width = sc->width / vi->vi_cwidth; vi->vi_height = sc->height / vi->vi_cheight; /* * Clamp width/height to syscons maximums */ if (vi->vi_width > COL) vi->vi_width = COL; if (vi->vi_height > ROW) vi->vi_height = ROW; sc->xmargin = (sc->width - (vi->vi_width * vi->vi_cwidth)) / 2; sc->ymargin = (sc->height - (vi->vi_height * vi->vi_cheight)) / 2; adp->va_window = (vm_offset_t) bcmfb_static_window; adp->va_flags |= V_ADP_FONT /* | V_ADP_COLOR | V_ADP_MODECHANGE */; vid_register(&sc->va); return (0); } static int bcmfb_get_info(video_adapter_t *adp, int mode, video_info_t *info) { bcopy(&adp->va_info, info, sizeof(*info)); return (0); } static int bcmfb_query_mode(video_adapter_t *adp, video_info_t *info) { return (0); } static int bcmfb_set_mode(video_adapter_t *adp, int mode) { return (0); } static int bcmfb_save_font(video_adapter_t *adp, int page, int size, int width, u_char *data, int c, int count) { return (0); } static int bcmfb_load_font(video_adapter_t *adp, int page, int size, int width, u_char *data, int c, int count) { struct bcmsc_softc *sc; sc = (struct bcmsc_softc *)adp; sc->font = data; return (0); } static int bcmfb_show_font(video_adapter_t *adp, int page) { return (0); } static int bcmfb_save_palette(video_adapter_t *adp, u_char *palette) { return (0); } static int bcmfb_load_palette(video_adapter_t *adp, u_char *palette) { return (0); } static int bcmfb_set_border(video_adapter_t *adp, int border) { return (bcmfb_blank_display(adp, border)); } static int bcmfb_save_state(video_adapter_t *adp, void *p, size_t size) { return (0); } static int bcmfb_load_state(video_adapter_t *adp, void *p) { return (0); } static int bcmfb_set_win_org(video_adapter_t *adp, off_t offset) { return (0); } static int bcmfb_read_hw_cursor(video_adapter_t *adp, int *col, int *row) { *col = *row = 0; return (0); } static int bcmfb_set_hw_cursor(video_adapter_t *adp, int col, int row) { return (0); } static int bcmfb_set_hw_cursor_shape(video_adapter_t *adp, int base, int height, int celsize, int blink) { return (0); } static int bcmfb_blank_display(video_adapter_t *adp, int mode) { struct bcmsc_softc *sc; sc = (struct bcmsc_softc *)adp; if (sc && sc->fb_addr) memset((void*)sc->fb_addr, 0, sc->fb_size); return (0); } static int bcmfb_mmap(video_adapter_t *adp, vm_ooffset_t offset, vm_paddr_t *paddr, int prot, vm_memattr_t *memattr) { struct bcmsc_softc *sc; sc = (struct bcmsc_softc *)adp; /* * This might be a legacy VGA mem request: if so, just point it at the * framebuffer, since it shouldn't be touched */ if (offset < sc->stride*sc->height) { *paddr = sc->fb_paddr + offset; return (0); } return (EINVAL); } static int bcmfb_ioctl(video_adapter_t *adp, u_long cmd, caddr_t data) { struct bcmsc_softc *sc; struct fbtype *fb; sc = (struct bcmsc_softc *)adp; switch (cmd) { case FBIOGTYPE: fb = (struct fbtype *)data; fb->fb_type = FBTYPE_PCIMISC; fb->fb_height = sc->height; fb->fb_width = sc->width; fb->fb_depth = sc->depth; if (sc->depth <= 1 || sc->depth > 8) fb->fb_cmsize = 0; else fb->fb_cmsize = 1 << sc->depth; fb->fb_size = sc->fb_size; break; default: return (fb_commonioctl(adp, cmd, data)); } return (0); } static int bcmfb_clear(video_adapter_t *adp) { return (bcmfb_blank_display(adp, 0)); } static int bcmfb_fill_rect(video_adapter_t *adp, int val, int x, int y, int cx, int cy) { return (0); } static int bcmfb_bitblt(video_adapter_t *adp, ...) { return (0); } static int bcmfb_diag(video_adapter_t *adp, int level) { return (0); } static int bcmfb_save_cursor_palette(video_adapter_t *adp, u_char *palette) { return (0); } static int bcmfb_load_cursor_palette(video_adapter_t *adp, u_char *palette) { return (0); } static int bcmfb_copy(video_adapter_t *adp, vm_offset_t src, vm_offset_t dst, int n) { return (0); } static int bcmfb_putp(video_adapter_t *adp, vm_offset_t off, uint32_t p, uint32_t a, int size, int bpp, int bit_ltor, int byte_ltor) { return (0); } static int bcmfb_putc(video_adapter_t *adp, vm_offset_t off, uint8_t c, uint8_t a) { int bytes, col, i, j, k, row; struct bcmsc_softc *sc; u_char *p; uint8_t *addr, fg, bg, color; uint16_t rgb; sc = (struct bcmsc_softc *)adp; if (sc->fb_addr == 0) return (0); row = (off / adp->va_info.vi_width) * adp->va_info.vi_cheight; col = (off % adp->va_info.vi_width) * adp->va_info.vi_cwidth; p = sc->font + c*BCMFB_FONT_HEIGHT; addr = (uint8_t *)sc->fb_addr + (row + sc->ymargin)*(sc->stride) + (sc->depth/8) * (col + sc->xmargin); fg = a & 0xf ; bg = (a >> 4) & 0xf; bytes = sc->depth / 8; for (i = 0; i < BCMFB_FONT_HEIGHT; i++) { for (j = 0, k = 7; j < 8; j++, k--) { if ((p[i] & (1 << k)) == 0) color = bg; else color = fg; switch (sc->depth) { case 32: case 24: if (sc->fbswap) { addr[bytes * j + 0] = bcmfb_palette[color].b; addr[bytes * j + 1] = bcmfb_palette[color].g; addr[bytes * j + 2] = bcmfb_palette[color].r; } else { addr[bytes * j + 0] = bcmfb_palette[color].r; addr[bytes * j + 1] = bcmfb_palette[color].g; addr[bytes * j + 2] = bcmfb_palette[color].b; } if (sc->depth == 32) addr[bytes * j + 3] = bcmfb_palette[color].a; break; case 16: rgb = (bcmfb_palette[color].r >> 3) << 11; rgb |= (bcmfb_palette[color].g >> 2) << 5; rgb |= (bcmfb_palette[color].b >> 3); addr[bytes * j] = rgb & 0xff; addr[bytes * j + 1] = (rgb >> 8) & 0xff; default: /* Not supported yet */ break; } } addr += (sc->stride); } return (0); } static int bcmfb_puts(video_adapter_t *adp, vm_offset_t off, u_int16_t *s, int len) { int i; for (i = 0; i < len; i++) bcmfb_putc(adp, off + i, s[i] & 0xff, (s[i] & 0xff00) >> 8); return (0); } static int bcmfb_putm(video_adapter_t *adp, int x, int y, uint8_t *pixel_image, uint32_t pixel_mask, int size, int width) { return (0); } /* * Define a stub keyboard driver in case one hasn't been * compiled into the kernel */ #include #include static int dummy_kbd_configure(int flags); keyboard_switch_t bcmdummysw; static int dummy_kbd_configure(int flags) { return (0); } KEYBOARD_DRIVER(bcmdummy, bcmdummysw, dummy_kbd_configure); Index: head/sys/arm/broadcom/bcm2835/bcm2835_fbd.c =================================================================== --- head/sys/arm/broadcom/bcm2835/bcm2835_fbd.c (revision 331228) +++ head/sys/arm/broadcom/bcm2835/bcm2835_fbd.c (revision 331229) @@ -1,278 +1,278 @@ /*- * SPDX-License-Identifier: BSD-2-Clause-FreeBSD * * Copyright (c) 2012 Oleksandr Tymoshenko * Copyright (c) 2012, 2013 The FreeBSD Foundation * All rights reserved. * * Portions of this software were developed by Oleksandr Rybalko * under sponsorship from the FreeBSD Foundation. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. * */ #include __FBSDID("$FreeBSD$"); #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include "fb_if.h" #include "mbox_if.h" #define FB_DEPTH 24 struct bcmsc_softc { struct fb_info info; int fbswap; struct bcm2835_fb_config fb; device_t dev; }; static struct ofw_compat_data compat_data[] = { {"broadcom,bcm2835-fb", 1}, {"brcm,bcm2708-fb", 1}, {NULL, 0} }; static int bcm_fb_probe(device_t); static int bcm_fb_attach(device_t); static int bcm_fb_init(struct bcmsc_softc *sc, struct bcm2835_fb_config *fb) { int err; err = 0; memset(fb, 0, sizeof(*fb)); if (bcm2835_mbox_fb_get_w_h(fb) != 0) return (ENXIO); fb->bpp = FB_DEPTH; fb->vxres = fb->xres; fb->vyres = fb->yres; fb->xoffset = fb->yoffset = 0; if ((err = bcm2835_mbox_fb_init(fb)) != 0) { device_printf(sc->dev, "bcm2835_mbox_fb_init failed, err=%d\n", err); return (ENXIO); } return (0); } static int bcm_fb_setup_fbd(struct bcmsc_softc *sc) { struct bcm2835_fb_config fb; device_t fbd; int err; err = bcm_fb_init(sc, &fb); if (err) return (err); memset(&sc->info, 0, sizeof(sc->info)); sc->info.fb_name = device_get_nameunit(sc->dev); sc->info.fb_vbase = (intptr_t)pmap_mapdev(fb.base, fb.size); sc->info.fb_pbase = fb.base; sc->info.fb_size = fb.size; sc->info.fb_bpp = sc->info.fb_depth = fb.bpp; sc->info.fb_stride = fb.pitch; sc->info.fb_width = fb.xres; sc->info.fb_height = fb.yres; #ifdef VM_MEMATTR_WRITE_COMBINING sc->info.fb_flags = FB_FLAG_MEMATTR; sc->info.fb_memattr = VM_MEMATTR_WRITE_COMBINING; #endif if (sc->fbswap) { switch (sc->info.fb_bpp) { case 24: vt_generate_cons_palette(sc->info.fb_cmap, COLOR_FORMAT_RGB, 0xff, 0, 0xff, 8, 0xff, 16); sc->info.fb_cmsize = 16; break; case 32: vt_generate_cons_palette(sc->info.fb_cmap, COLOR_FORMAT_RGB, 0xff, 16, 0xff, 8, 0xff, 0); sc->info.fb_cmsize = 16; break; } } fbd = device_add_child(sc->dev, "fbd", device_get_unit(sc->dev)); if (fbd == NULL) { device_printf(sc->dev, "Failed to add fbd child\n"); pmap_unmapdev(sc->info.fb_vbase, sc->info.fb_size); return (ENXIO); } else if (device_probe_and_attach(fbd) != 0) { device_printf(sc->dev, "Failed to attach fbd device\n"); device_delete_child(sc->dev, fbd); pmap_unmapdev(sc->info.fb_vbase, sc->info.fb_size); return (ENXIO); } device_printf(sc->dev, "%dx%d(%dx%d@%d,%d) %dbpp\n", fb.xres, fb.yres, fb.vxres, fb.vyres, fb.xoffset, fb.yoffset, fb.bpp); device_printf(sc->dev, "fbswap: %d, pitch %d, base 0x%08x, screen_size %d\n", sc->fbswap, fb.pitch, fb.base, fb.size); return (0); } static int bcm_fb_resync_sysctl(SYSCTL_HANDLER_ARGS) { struct bcmsc_softc *sc = arg1; struct bcm2835_fb_config fb; int val; int err; val = 0; err = sysctl_handle_int(oidp, &val, 0, req); if (err || !req->newptr) /* error || read request */ return (err); bcm_fb_init(sc, &fb); return (0); } static void bcm_fb_sysctl_init(struct bcmsc_softc *sc) { struct sysctl_ctx_list *ctx; struct sysctl_oid *tree_node; struct sysctl_oid_list *tree; /* * Add system sysctl tree/handlers. */ ctx = device_get_sysctl_ctx(sc->dev); tree_node = device_get_sysctl_tree(sc->dev); tree = SYSCTL_CHILDREN(tree_node); SYSCTL_ADD_PROC(ctx, tree, OID_AUTO, "resync", CTLFLAG_RW | CTLTYPE_UINT, sc, sizeof(*sc), bcm_fb_resync_sysctl, "IU", "Set to resync framebuffer with VC"); } static int bcm_fb_probe(device_t dev) { if (ofw_bus_search_compatible(dev, compat_data)->ocd_data == 0) return (ENXIO); device_set_desc(dev, "BCM2835 VT framebuffer driver"); return (BUS_PROBE_DEFAULT); } static int bcm_fb_attach(device_t dev) { char bootargs[2048], *n, *p, *v; int err; phandle_t chosen; struct bcmsc_softc *sc; sc = device_get_softc(dev); sc->dev = dev; /* Newer firmware versions needs an inverted color palette. */ sc->fbswap = 0; chosen = OF_finddevice("/chosen"); - if (chosen != 0 && + if (chosen != -1 && OF_getprop(chosen, "bootargs", &bootargs, sizeof(bootargs)) > 0) { p = bootargs; while ((v = strsep(&p, " ")) != NULL) { if (*v == '\0') continue; n = strsep(&v, "="); if (strcmp(n, "bcm2708_fb.fbswap") == 0 && v != NULL) if (*v == '1') sc->fbswap = 1; } } bcm_fb_sysctl_init(sc); err = bcm_fb_setup_fbd(sc); if (err) return (err); return (0); } static struct fb_info * bcm_fb_helper_getinfo(device_t dev) { struct bcmsc_softc *sc; sc = device_get_softc(dev); return (&sc->info); } static device_method_t bcm_fb_methods[] = { /* Device interface */ DEVMETHOD(device_probe, bcm_fb_probe), DEVMETHOD(device_attach, bcm_fb_attach), /* Framebuffer service methods */ DEVMETHOD(fb_getinfo, bcm_fb_helper_getinfo), DEVMETHOD_END }; static devclass_t bcm_fb_devclass; static driver_t bcm_fb_driver = { "fb", bcm_fb_methods, sizeof(struct bcmsc_softc), }; DRIVER_MODULE(bcm2835fb, ofwbus, bcm_fb_driver, bcm_fb_devclass, 0, 0); DRIVER_MODULE(bcm2835fb, simplebus, bcm_fb_driver, bcm_fb_devclass, 0, 0); Index: head/sys/arm/broadcom/bcm2835/bcm2835_machdep.c =================================================================== --- head/sys/arm/broadcom/bcm2835/bcm2835_machdep.c (revision 331228) +++ head/sys/arm/broadcom/bcm2835/bcm2835_machdep.c (revision 331229) @@ -1,157 +1,157 @@ /*- * SPDX-License-Identifier: BSD-4-Clause * * Copyright (c) 2012 Oleksandr Tymoshenko. * Copyright (c) 1994-1998 Mark Brinicombe. * Copyright (c) 1994 Brini. * All rights reserved. * * This code is derived from software written for Brini by Mark Brinicombe * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * 3. All advertising materials mentioning features or use of this software * must display the following acknowledgement: * This product includes software developed by Brini. * 4. The name of the company nor the name of the author may be used to * endorse or promote products derived from this software without specific * prior written permission. * * THIS SOFTWARE IS PROVIDED BY BRINI ``AS IS'' AND ANY EXPRESS OR IMPLIED * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. * IN NO EVENT SHALL BRINI OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. * * from: FreeBSD: //depot/projects/arm/src/sys/arm/at91/kb920x_machdep.c, rev 45 */ #include "opt_ddb.h" #include "opt_platform.h" #include __FBSDID("$FreeBSD$"); #include #include #include #include #include #include #include #include #include #include #include #include #include #include "platform_if.h" #ifdef SOC_BCM2835 static platform_devmap_init_t bcm2835_devmap_init; #endif #ifdef SOC_BCM2836 static platform_devmap_init_t bcm2836_devmap_init; #endif static platform_late_init_t bcm2835_late_init; static platform_cpu_reset_t bcm2835_cpu_reset; static void bcm2835_late_init(platform_t plat) { phandle_t system; pcell_t cells[2]; int len; system = OF_finddevice("/system"); - if (system != 0) { + if (system != -1) { len = OF_getencprop(system, "linux,serial", cells, sizeof(cells)); if (len > 0) board_set_serial(((uint64_t)cells[0]) << 32 | cells[1]); len = OF_getencprop(system, "linux,revision", cells, sizeof(cells)); if (len > 0) board_set_revision(cells[0]); } } #ifdef SOC_BCM2835 /* * Set up static device mappings. * All on-chip peripherals exist in a 16MB range starting at 0x20000000. * Map the entire range using 1MB section mappings. */ static int bcm2835_devmap_init(platform_t plat) { devmap_add_entry(0x20000000, 0x01000000); return (0); } #endif #ifdef SOC_BCM2836 static int bcm2836_devmap_init(platform_t plat) { devmap_add_entry(0x3f000000, 0x01000000); return (0); } #endif static void bcm2835_cpu_reset(platform_t plat) { bcmwd_watchdog_reset(); } #ifdef SOC_BCM2835 static platform_method_t bcm2835_methods[] = { PLATFORMMETHOD(platform_devmap_init, bcm2835_devmap_init), PLATFORMMETHOD(platform_late_init, bcm2835_late_init), PLATFORMMETHOD(platform_cpu_reset, bcm2835_cpu_reset), PLATFORMMETHOD_END, }; FDT_PLATFORM_DEF2(bcm2835, bcm2835_legacy, "bcm2835 (legacy)", 0, "raspberrypi,model-b", 100); FDT_PLATFORM_DEF2(bcm2835, bcm2835, "bcm2835", 0, "brcm,bcm2835", 100); #endif #ifdef SOC_BCM2836 static platform_method_t bcm2836_methods[] = { PLATFORMMETHOD(platform_devmap_init, bcm2836_devmap_init), PLATFORMMETHOD(platform_late_init, bcm2835_late_init), PLATFORMMETHOD(platform_cpu_reset, bcm2835_cpu_reset), #ifdef SMP PLATFORMMETHOD(platform_mp_start_ap, bcm2836_mp_start_ap), PLATFORMMETHOD(platform_mp_setmaxid, bcm2836_mp_setmaxid), #endif PLATFORMMETHOD_END, }; FDT_PLATFORM_DEF2(bcm2836, bcm2836_legacy, "bcm2836 (legacy)", 0, "brcm,bcm2709", 100); FDT_PLATFORM_DEF2(bcm2836, bcm2836, "bcm2836", 0, "brcm,bcm2836", 100); #endif Index: head/sys/arm/freescale/fsl_ocotp.c =================================================================== --- head/sys/arm/freescale/fsl_ocotp.c (revision 331228) +++ head/sys/arm/freescale/fsl_ocotp.c (revision 331229) @@ -1,207 +1,207 @@ /*- * SPDX-License-Identifier: BSD-2-Clause-FreeBSD * * Copyright (c) 2014 Steven Lawrance * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. */ #include __FBSDID("$FreeBSD$"); /* * Access to the Freescale i.MX6 On-Chip One-Time-Programmable Memory */ #include #include #include #include #include #include #include #include #include #include #include /* * Find the physical address and size of the ocotp registers and devmap them, * returning a pointer to the virtual address of the base. * * XXX This is temporary until we've worked out all the details of controlling * the load order of devices. In an ideal world this device would be up and * running before anything that needs it. When we're at a point to make that * happen, this little block of code, and the few lines in fsl_ocotp_read_4() * that refer to it can be deleted. */ #include #include #include #include static uint32_t *ocotp_regs; static vm_size_t ocotp_size; static void fsl_ocotp_devmap(void) { phandle_t child, root; u_long base, size; - if ((root = OF_finddevice("/")) == 0) + if ((root = OF_finddevice("/")) == -1) goto fatal; if ((child = fdt_depth_search_compatible(root, "fsl,imx6q-ocotp", 0)) == 0) goto fatal; if (fdt_regsize(child, &base, &size) != 0) goto fatal; ocotp_size = (vm_size_t)size; if ((ocotp_regs = pmap_mapdev((vm_offset_t)base, ocotp_size)) == NULL) goto fatal; return; fatal: panic("cannot find/map the ocotp registers"); } /* XXX end of temporary code */ struct ocotp_softc { device_t dev; struct resource *mem_res; }; static struct ocotp_softc *ocotp_sc; static inline uint32_t RD4(struct ocotp_softc *sc, bus_size_t off) { return (bus_read_4(sc->mem_res, off)); } static int ocotp_detach(device_t dev) { /* The ocotp registers are always accessible. */ return (EBUSY); } static int ocotp_attach(device_t dev) { struct ocotp_softc *sc; int err, rid; sc = device_get_softc(dev); sc->dev = dev; /* Allocate bus_space resources. */ rid = 0; sc->mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, RF_ACTIVE); if (sc->mem_res == NULL) { device_printf(dev, "Cannot allocate memory resources\n"); err = ENXIO; goto out; } ocotp_sc = sc; /* We're done with the temporary mapping now. */ if (ocotp_regs != NULL) pmap_unmapdev((vm_offset_t)ocotp_regs, ocotp_size); err = 0; out: if (err != 0) ocotp_detach(dev); return (err); } static int ocotp_probe(device_t dev) { if (!ofw_bus_status_okay(dev)) return (ENXIO); if (ofw_bus_is_compatible(dev, "fsl,imx6q-ocotp") == 0) return (ENXIO); device_set_desc(dev, "Freescale On-Chip One-Time-Programmable Memory"); return (BUS_PROBE_DEFAULT); } uint32_t fsl_ocotp_read_4(bus_size_t off) { if (off > FSL_OCOTP_LAST_REG) panic("fsl_ocotp_read_4: offset out of range"); /* If we have a softcontext use the regular bus_space read. */ if (ocotp_sc != NULL) return (RD4(ocotp_sc, off)); /* * Otherwise establish a tempory device mapping if necessary, and read * the device without any help from bus_space. * * XXX Eventually the code from there down can be deleted. */ if (ocotp_regs == NULL) fsl_ocotp_devmap(); return (ocotp_regs[off / 4]); } static device_method_t ocotp_methods[] = { /* Device interface */ DEVMETHOD(device_probe, ocotp_probe), DEVMETHOD(device_attach, ocotp_attach), DEVMETHOD(device_detach, ocotp_detach), DEVMETHOD_END }; static driver_t ocotp_driver = { "ocotp", ocotp_methods, sizeof(struct ocotp_softc) }; static devclass_t ocotp_devclass; EARLY_DRIVER_MODULE(ocotp, simplebus, ocotp_driver, ocotp_devclass, 0, 0, BUS_PASS_CPU + BUS_PASS_ORDER_FIRST); Index: head/sys/arm/freescale/vybrid/vf_machdep.c =================================================================== --- head/sys/arm/freescale/vybrid/vf_machdep.c (revision 331228) +++ head/sys/arm/freescale/vybrid/vf_machdep.c (revision 331229) @@ -1,88 +1,88 @@ /*- * SPDX-License-Identifier: BSD-2-Clause-FreeBSD * * Copyright (c) 2013 Ruslan Bukin * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. */ #include "opt_platform.h" #include __FBSDID("$FreeBSD$"); #include #include #include #include #include #include #include #include #include #include #include "platform_if.h" static int vf_devmap_init(platform_t plat) { devmap_add_entry(0x40000000, 0x100000); return (0); } static void vf_cpu_reset(platform_t plat) { phandle_t src; uint32_t paddr; bus_addr_t vaddr; if (src_swreset() == 0) goto end; src = OF_finddevice("src"); - if ((src != 0) && (OF_getencprop(src, "reg", &paddr, sizeof(paddr))) > 0) { + if ((src != -1) && (OF_getencprop(src, "reg", &paddr, sizeof(paddr))) > 0) { if (bus_space_map(fdtbus_bs_tag, paddr, 0x10, 0, &vaddr) == 0) { bus_space_write_4(fdtbus_bs_tag, vaddr, 0x00, SW_RST); } } end: while (1); } static platform_method_t vf_methods[] = { PLATFORMMETHOD(platform_devmap_init, vf_devmap_init), PLATFORMMETHOD(platform_cpu_reset, vf_cpu_reset), PLATFORMMETHOD_END, }; FDT_PLATFORM_DEF(vf, "vybrid", 0, "freescale,vybrid", 200); Index: head/sys/arm/mv/mv_common.c =================================================================== --- head/sys/arm/mv/mv_common.c (revision 331228) +++ head/sys/arm/mv/mv_common.c (revision 331229) @@ -1,2691 +1,2691 @@ /*- * SPDX-License-Identifier: BSD-3-Clause * * Copyright (C) 2008-2011 MARVELL INTERNATIONAL LTD. * All rights reserved. * * Developed by Semihalf. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * 3. Neither the name of MARVELL nor the names of contributors * may be used to endorse or promote products derived from this software * without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. */ #include __FBSDID("$FreeBSD$"); #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include MALLOC_DEFINE(M_IDMA, "idma", "idma dma test memory"); #define IDMA_DEBUG #undef IDMA_DEBUG #define MAX_CPU_WIN 5 #ifdef DEBUG #define debugf(fmt, args...) do { printf("%s(): ", __func__); \ printf(fmt,##args); } while (0) #else #define debugf(fmt, args...) #endif #ifdef DEBUG #define MV_DUMP_WIN 1 #else #define MV_DUMP_WIN 0 #endif static int win_eth_can_remap(int i); static int decode_win_cesa_valid(void); static int decode_win_cpu_valid(void); static int decode_win_usb_valid(void); static int decode_win_usb3_valid(void); static int decode_win_eth_valid(void); static int decode_win_pcie_valid(void); static int decode_win_sata_valid(void); static int decode_win_sdhci_valid(void); static int decode_win_idma_valid(void); static int decode_win_xor_valid(void); static void decode_win_cpu_setup(void); #ifdef SOC_MV_ARMADAXP static int decode_win_sdram_fixup(void); #endif static void decode_win_cesa_setup(u_long); static void decode_win_usb_setup(u_long); static void decode_win_usb3_setup(u_long); static void decode_win_eth_setup(u_long); static void decode_win_neta_setup(u_long); static void decode_win_sata_setup(u_long); static void decode_win_ahci_setup(u_long); static void decode_win_sdhci_setup(u_long); static void decode_win_idma_setup(u_long); static void decode_win_xor_setup(u_long); static void decode_win_cesa_dump(u_long); static void decode_win_usb_dump(u_long); static void decode_win_usb3_dump(u_long); static void decode_win_eth_dump(u_long base); static void decode_win_neta_dump(u_long base); static void decode_win_idma_dump(u_long base); static void decode_win_xor_dump(u_long base); static void decode_win_ahci_dump(u_long base); static void decode_win_sdhci_dump(u_long); static void decode_win_pcie_dump(u_long); static int fdt_get_ranges(const char *, void *, int, int *, int *); #ifdef SOC_MV_ARMADA38X int gic_decode_fdt(phandle_t iparent, pcell_t *intr, int *interrupt, int *trig, int *pol); #endif static int win_cpu_from_dt(void); static int fdt_win_setup(void); static uint32_t dev_mask = 0; static int cpu_wins_no = 0; static int eth_port = 0; static int usb_port = 0; static boolean_t platform_io_coherent = false; static struct decode_win cpu_win_tbl[MAX_CPU_WIN]; const struct decode_win *cpu_wins = cpu_win_tbl; typedef void (*decode_win_setup_t)(u_long); typedef void (*dump_win_t)(u_long); /* * The power status of device feature is only supported on * Kirkwood and Discovery SoCs. */ #if defined(SOC_MV_KIRKWOOD) || defined(SOC_MV_DISCOVERY) #define SOC_MV_POWER_STAT_SUPPORTED 1 #else #define SOC_MV_POWER_STAT_SUPPORTED 0 #endif struct soc_node_spec { const char *compat; decode_win_setup_t decode_handler; dump_win_t dump_handler; }; static struct soc_node_spec soc_nodes[] = { { "mrvl,ge", &decode_win_eth_setup, &decode_win_eth_dump }, { "marvell,armada-370-neta", &decode_win_neta_setup, &decode_win_neta_dump }, { "mrvl,usb-ehci", &decode_win_usb_setup, &decode_win_usb_dump }, { "marvell,orion-ehci", &decode_win_usb_setup, &decode_win_usb_dump }, { "marvell,armada-380-xhci", &decode_win_usb3_setup, &decode_win_usb3_dump }, { "marvell,armada-380-ahci", &decode_win_ahci_setup, &decode_win_ahci_dump }, { "marvell,armada-380-sdhci", &decode_win_sdhci_setup, &decode_win_sdhci_dump }, { "mrvl,sata", &decode_win_sata_setup, NULL }, { "mrvl,xor", &decode_win_xor_setup, &decode_win_xor_dump }, { "mrvl,idma", &decode_win_idma_setup, &decode_win_idma_dump }, { "mrvl,cesa", &decode_win_cesa_setup, &decode_win_cesa_dump }, { "mrvl,pcie", &decode_win_pcie_setup, &decode_win_pcie_dump }, { NULL, NULL, NULL }, }; struct fdt_pm_mask_entry { char *compat; uint32_t mask; }; static struct fdt_pm_mask_entry fdt_pm_mask_table[] = { { "mrvl,ge", CPU_PM_CTRL_GE(0) }, { "mrvl,ge", CPU_PM_CTRL_GE(1) }, { "mrvl,usb-ehci", CPU_PM_CTRL_USB(0) }, { "mrvl,usb-ehci", CPU_PM_CTRL_USB(1) }, { "mrvl,usb-ehci", CPU_PM_CTRL_USB(2) }, { "mrvl,xor", CPU_PM_CTRL_XOR }, { "mrvl,sata", CPU_PM_CTRL_SATA }, { NULL, 0 } }; static __inline int pm_is_disabled(uint32_t mask) { #if SOC_MV_POWER_STAT_SUPPORTED return (soc_power_ctrl_get(mask) == mask ? 0 : 1); #else return (0); #endif } /* * Disable device using power management register. * 1 - Device Power On * 0 - Device Power Off * Mask can be set in loader. * EXAMPLE: * loader> set hw.pm-disable-mask=0x2 * * Common mask: * |-------------------------------| * | Device | Kirkwood | Discovery | * |-------------------------------| * | USB0 | 0x00008 | 0x020000 | * |-------------------------------| * | USB1 | - | 0x040000 | * |-------------------------------| * | USB2 | - | 0x080000 | * |-------------------------------| * | GE0 | 0x00001 | 0x000002 | * |-------------------------------| * | GE1 | - | 0x000004 | * |-------------------------------| * | IDMA | - | 0x100000 | * |-------------------------------| * | XOR | 0x10000 | 0x200000 | * |-------------------------------| * | CESA | 0x20000 | 0x400000 | * |-------------------------------| * | SATA | 0x04000 | 0x004000 | * --------------------------------| * This feature can be used only on Kirkwood and Discovery * machines. */ static __inline void pm_disable_device(int mask) { #ifdef DIAGNOSTIC uint32_t reg; reg = soc_power_ctrl_get(CPU_PM_CTRL_ALL); printf("Power Management Register: 0%x\n", reg); reg &= ~mask; soc_power_ctrl_set(reg); printf("Device %x is disabled\n", mask); reg = soc_power_ctrl_get(CPU_PM_CTRL_ALL); printf("Power Management Register: 0%x\n", reg); #endif } int fdt_pm(phandle_t node) { uint32_t cpu_pm_ctrl; int i, ena, compat; ena = 1; cpu_pm_ctrl = read_cpu_ctrl(CPU_PM_CTRL); for (i = 0; fdt_pm_mask_table[i].compat != NULL; i++) { if (dev_mask & (1 << i)) continue; compat = ofw_bus_node_is_compatible(node, fdt_pm_mask_table[i].compat); #if defined(SOC_MV_KIRKWOOD) if (compat && (cpu_pm_ctrl & fdt_pm_mask_table[i].mask)) { dev_mask |= (1 << i); ena = 0; break; } else if (compat) { dev_mask |= (1 << i); break; } #else if (compat && (~cpu_pm_ctrl & fdt_pm_mask_table[i].mask)) { dev_mask |= (1 << i); ena = 0; break; } else if (compat) { dev_mask |= (1 << i); break; } #endif } return (ena); } uint32_t read_cpu_ctrl(uint32_t reg) { return (bus_space_read_4(fdtbus_bs_tag, MV_CPU_CONTROL_BASE, reg)); } void write_cpu_ctrl(uint32_t reg, uint32_t val) { bus_space_write_4(fdtbus_bs_tag, MV_CPU_CONTROL_BASE, reg, val); } #if defined(SOC_MV_ARMADAXP) || defined(SOC_MV_ARMADA38X) uint32_t read_cpu_mp_clocks(uint32_t reg) { return (bus_space_read_4(fdtbus_bs_tag, MV_MP_CLOCKS_BASE, reg)); } void write_cpu_mp_clocks(uint32_t reg, uint32_t val) { bus_space_write_4(fdtbus_bs_tag, MV_MP_CLOCKS_BASE, reg, val); } uint32_t read_cpu_misc(uint32_t reg) { return (bus_space_read_4(fdtbus_bs_tag, MV_MISC_BASE, reg)); } void write_cpu_misc(uint32_t reg, uint32_t val) { bus_space_write_4(fdtbus_bs_tag, MV_MISC_BASE, reg, val); } #endif void cpu_reset(void) { #if defined(SOC_MV_ARMADAXP) || defined (SOC_MV_ARMADA38X) write_cpu_misc(RSTOUTn_MASK, SOFT_RST_OUT_EN); write_cpu_misc(SYSTEM_SOFT_RESET, SYS_SOFT_RST); #else write_cpu_ctrl(RSTOUTn_MASK, SOFT_RST_OUT_EN); write_cpu_ctrl(SYSTEM_SOFT_RESET, SYS_SOFT_RST); #endif while (1); } uint32_t cpu_extra_feat(void) { uint32_t dev, rev; uint32_t ef = 0; soc_id(&dev, &rev); switch (dev) { case MV_DEV_88F6281: case MV_DEV_88F6282: case MV_DEV_88RC8180: case MV_DEV_MV78100_Z0: case MV_DEV_MV78100: __asm __volatile("mrc p15, 1, %0, c15, c1, 0" : "=r" (ef)); break; case MV_DEV_88F5182: case MV_DEV_88F5281: __asm __volatile("mrc p15, 0, %0, c14, c0, 0" : "=r" (ef)); break; default: if (bootverbose) printf("This ARM Core does not support any extra features\n"); } return (ef); } /* * Get the power status of device. This feature is only supported on * Kirkwood and Discovery SoCs. */ uint32_t soc_power_ctrl_get(uint32_t mask) { #if SOC_MV_POWER_STAT_SUPPORTED if (mask != CPU_PM_CTRL_NONE) mask &= read_cpu_ctrl(CPU_PM_CTRL); return (mask); #else return (mask); #endif } /* * Set the power status of device. This feature is only supported on * Kirkwood and Discovery SoCs. */ void soc_power_ctrl_set(uint32_t mask) { #if !defined(SOC_MV_ORION) if (mask != CPU_PM_CTRL_NONE) write_cpu_ctrl(CPU_PM_CTRL, mask); #endif } void soc_id(uint32_t *dev, uint32_t *rev) { /* * Notice: system identifiers are available in the registers range of * PCIE controller, so using this function is only allowed (and * possible) after the internal registers range has been mapped in via * devmap_bootstrap(). */ *dev = bus_space_read_4(fdtbus_bs_tag, MV_PCIE_BASE, 0) >> 16; *rev = bus_space_read_4(fdtbus_bs_tag, MV_PCIE_BASE, 8) & 0xff; } static void soc_identify(void) { uint32_t d, r, size, mode, freq; const char *dev; const char *rev; soc_id(&d, &r); printf("SOC: "); if (bootverbose) printf("(0x%4x:0x%02x) ", d, r); rev = ""; switch (d) { case MV_DEV_88F5181: dev = "Marvell 88F5181"; if (r == 3) rev = "B1"; break; case MV_DEV_88F5182: dev = "Marvell 88F5182"; if (r == 2) rev = "A2"; break; case MV_DEV_88F5281: dev = "Marvell 88F5281"; if (r == 4) rev = "D0"; else if (r == 5) rev = "D1"; else if (r == 6) rev = "D2"; break; case MV_DEV_88F6281: dev = "Marvell 88F6281"; if (r == 0) rev = "Z0"; else if (r == 2) rev = "A0"; else if (r == 3) rev = "A1"; break; case MV_DEV_88RC8180: dev = "Marvell 88RC8180"; break; case MV_DEV_88RC9480: dev = "Marvell 88RC9480"; break; case MV_DEV_88RC9580: dev = "Marvell 88RC9580"; break; case MV_DEV_88F6781: dev = "Marvell 88F6781"; if (r == 2) rev = "Y0"; break; case MV_DEV_88F6282: dev = "Marvell 88F6282"; if (r == 0) rev = "A0"; else if (r == 1) rev = "A1"; break; case MV_DEV_88F6828: dev = "Marvell 88F6828"; break; case MV_DEV_88F6820: dev = "Marvell 88F6820"; break; case MV_DEV_88F6810: dev = "Marvell 88F6810"; break; case MV_DEV_MV78100_Z0: dev = "Marvell MV78100 Z0"; break; case MV_DEV_MV78100: dev = "Marvell MV78100"; break; case MV_DEV_MV78160: dev = "Marvell MV78160"; break; case MV_DEV_MV78260: dev = "Marvell MV78260"; break; case MV_DEV_MV78460: dev = "Marvell MV78460"; break; default: dev = "UNKNOWN"; break; } printf("%s", dev); if (*rev != '\0') printf(" rev %s", rev); printf(", TClock %dMHz", get_tclk() / 1000 / 1000); freq = get_cpu_freq(); if (freq != 0) printf(", Frequency %dMHz", freq / 1000 / 1000); printf("\n"); mode = read_cpu_ctrl(CPU_CONFIG); printf(" Instruction cache prefetch %s, data cache prefetch %s\n", (mode & CPU_CONFIG_IC_PREF) ? "enabled" : "disabled", (mode & CPU_CONFIG_DC_PREF) ? "enabled" : "disabled"); switch (d) { case MV_DEV_88F6281: case MV_DEV_88F6282: mode = read_cpu_ctrl(CPU_L2_CONFIG) & CPU_L2_CONFIG_MODE; printf(" 256KB 4-way set-associative %s unified L2 cache\n", mode ? "write-through" : "write-back"); break; case MV_DEV_MV78100: mode = read_cpu_ctrl(CPU_CONTROL); size = mode & CPU_CONTROL_L2_SIZE; mode = mode & CPU_CONTROL_L2_MODE; printf(" %s set-associative %s unified L2 cache\n", size ? "256KB 4-way" : "512KB 8-way", mode ? "write-through" : "write-back"); break; default: break; } } static void platform_identify(void *dummy) { soc_identify(); /* * XXX Board identification e.g. read out from FPGA or similar should * go here */ } SYSINIT(platform_identify, SI_SUB_CPU, SI_ORDER_SECOND, platform_identify, NULL); #ifdef KDB static void mv_enter_debugger(void *dummy) { if (boothowto & RB_KDB) kdb_enter(KDB_WHY_BOOTFLAGS, "Boot flags requested debugger"); } SYSINIT(mv_enter_debugger, SI_SUB_CPU, SI_ORDER_ANY, mv_enter_debugger, NULL); #endif int soc_decode_win(void) { uint32_t dev, rev; int mask, err; mask = 0; TUNABLE_INT_FETCH("hw.pm-disable-mask", &mask); if (mask != 0) pm_disable_device(mask); /* Retrieve data about physical addresses from device tree. */ if ((err = win_cpu_from_dt()) != 0) return (err); /* Retrieve our ID: some windows facilities vary between SoC models */ soc_id(&dev, &rev); #ifdef SOC_MV_ARMADAXP if ((err = decode_win_sdram_fixup()) != 0) return(err); #endif if (!decode_win_cpu_valid() || !decode_win_usb_valid() || !decode_win_eth_valid() || !decode_win_idma_valid() || !decode_win_pcie_valid() || !decode_win_sata_valid() || !decode_win_xor_valid() || !decode_win_usb3_valid() || !decode_win_sdhci_valid() || !decode_win_cesa_valid()) return (EINVAL); decode_win_cpu_setup(); if (MV_DUMP_WIN) soc_dump_decode_win(); eth_port = 0; usb_port = 0; if ((err = fdt_win_setup()) != 0) return (err); return (0); } /************************************************************************** * Decode windows registers accessors **************************************************************************/ WIN_REG_IDX_RD(win_cpu, cr, MV_WIN_CPU_CTRL, MV_MBUS_BRIDGE_BASE) WIN_REG_IDX_RD(win_cpu, br, MV_WIN_CPU_BASE, MV_MBUS_BRIDGE_BASE) WIN_REG_IDX_RD(win_cpu, remap_l, MV_WIN_CPU_REMAP_LO, MV_MBUS_BRIDGE_BASE) WIN_REG_IDX_RD(win_cpu, remap_h, MV_WIN_CPU_REMAP_HI, MV_MBUS_BRIDGE_BASE) WIN_REG_IDX_WR(win_cpu, cr, MV_WIN_CPU_CTRL, MV_MBUS_BRIDGE_BASE) WIN_REG_IDX_WR(win_cpu, br, MV_WIN_CPU_BASE, MV_MBUS_BRIDGE_BASE) WIN_REG_IDX_WR(win_cpu, remap_l, MV_WIN_CPU_REMAP_LO, MV_MBUS_BRIDGE_BASE) WIN_REG_IDX_WR(win_cpu, remap_h, MV_WIN_CPU_REMAP_HI, MV_MBUS_BRIDGE_BASE) WIN_REG_BASE_IDX_RD(win_cesa, cr, MV_WIN_CESA_CTRL) WIN_REG_BASE_IDX_RD(win_cesa, br, MV_WIN_CESA_BASE) WIN_REG_BASE_IDX_WR(win_cesa, cr, MV_WIN_CESA_CTRL) WIN_REG_BASE_IDX_WR(win_cesa, br, MV_WIN_CESA_BASE) WIN_REG_BASE_IDX_RD(win_usb, cr, MV_WIN_USB_CTRL) WIN_REG_BASE_IDX_RD(win_usb, br, MV_WIN_USB_BASE) WIN_REG_BASE_IDX_WR(win_usb, cr, MV_WIN_USB_CTRL) WIN_REG_BASE_IDX_WR(win_usb, br, MV_WIN_USB_BASE) #ifdef SOC_MV_ARMADA38X WIN_REG_BASE_IDX_RD(win_usb3, cr, MV_WIN_USB3_CTRL) WIN_REG_BASE_IDX_RD(win_usb3, br, MV_WIN_USB3_BASE) WIN_REG_BASE_IDX_WR(win_usb3, cr, MV_WIN_USB3_CTRL) WIN_REG_BASE_IDX_WR(win_usb3, br, MV_WIN_USB3_BASE) #endif WIN_REG_BASE_IDX_RD(win_eth, br, MV_WIN_ETH_BASE) WIN_REG_BASE_IDX_RD(win_eth, sz, MV_WIN_ETH_SIZE) WIN_REG_BASE_IDX_RD(win_eth, har, MV_WIN_ETH_REMAP) WIN_REG_BASE_IDX_WR(win_eth, br, MV_WIN_ETH_BASE) WIN_REG_BASE_IDX_WR(win_eth, sz, MV_WIN_ETH_SIZE) WIN_REG_BASE_IDX_WR(win_eth, har, MV_WIN_ETH_REMAP) WIN_REG_BASE_IDX_RD2(win_xor, br, MV_WIN_XOR_BASE) WIN_REG_BASE_IDX_RD2(win_xor, sz, MV_WIN_XOR_SIZE) WIN_REG_BASE_IDX_RD2(win_xor, har, MV_WIN_XOR_REMAP) WIN_REG_BASE_IDX_RD2(win_xor, ctrl, MV_WIN_XOR_CTRL) WIN_REG_BASE_IDX_WR2(win_xor, br, MV_WIN_XOR_BASE) WIN_REG_BASE_IDX_WR2(win_xor, sz, MV_WIN_XOR_SIZE) WIN_REG_BASE_IDX_WR2(win_xor, har, MV_WIN_XOR_REMAP) WIN_REG_BASE_IDX_WR2(win_xor, ctrl, MV_WIN_XOR_CTRL) WIN_REG_BASE_RD(win_eth, bare, 0x290) WIN_REG_BASE_RD(win_eth, epap, 0x294) WIN_REG_BASE_WR(win_eth, bare, 0x290) WIN_REG_BASE_WR(win_eth, epap, 0x294) WIN_REG_BASE_IDX_RD(win_pcie, cr, MV_WIN_PCIE_CTRL); WIN_REG_BASE_IDX_RD(win_pcie, br, MV_WIN_PCIE_BASE); WIN_REG_BASE_IDX_RD(win_pcie, remap, MV_WIN_PCIE_REMAP); WIN_REG_BASE_IDX_WR(win_pcie, cr, MV_WIN_PCIE_CTRL); WIN_REG_BASE_IDX_WR(win_pcie, br, MV_WIN_PCIE_BASE); WIN_REG_BASE_IDX_WR(win_pcie, remap, MV_WIN_PCIE_REMAP); WIN_REG_BASE_IDX_RD(pcie_bar, br, MV_PCIE_BAR_BASE); WIN_REG_BASE_IDX_RD(pcie_bar, brh, MV_PCIE_BAR_BASE_H); WIN_REG_BASE_IDX_RD(pcie_bar, cr, MV_PCIE_BAR_CTRL); WIN_REG_BASE_IDX_WR(pcie_bar, br, MV_PCIE_BAR_BASE); WIN_REG_BASE_IDX_WR(pcie_bar, brh, MV_PCIE_BAR_BASE_H); WIN_REG_BASE_IDX_WR(pcie_bar, cr, MV_PCIE_BAR_CTRL); WIN_REG_BASE_IDX_RD(win_idma, br, MV_WIN_IDMA_BASE) WIN_REG_BASE_IDX_RD(win_idma, sz, MV_WIN_IDMA_SIZE) WIN_REG_BASE_IDX_RD(win_idma, har, MV_WIN_IDMA_REMAP) WIN_REG_BASE_IDX_RD(win_idma, cap, MV_WIN_IDMA_CAP) WIN_REG_BASE_IDX_WR(win_idma, br, MV_WIN_IDMA_BASE) WIN_REG_BASE_IDX_WR(win_idma, sz, MV_WIN_IDMA_SIZE) WIN_REG_BASE_IDX_WR(win_idma, har, MV_WIN_IDMA_REMAP) WIN_REG_BASE_IDX_WR(win_idma, cap, MV_WIN_IDMA_CAP) WIN_REG_BASE_RD(win_idma, bare, 0xa80) WIN_REG_BASE_WR(win_idma, bare, 0xa80) WIN_REG_BASE_IDX_RD(win_sata, cr, MV_WIN_SATA_CTRL); WIN_REG_BASE_IDX_RD(win_sata, br, MV_WIN_SATA_BASE); WIN_REG_BASE_IDX_WR(win_sata, cr, MV_WIN_SATA_CTRL); WIN_REG_BASE_IDX_WR(win_sata, br, MV_WIN_SATA_BASE); #if defined(SOC_MV_ARMADA38X) WIN_REG_BASE_IDX_RD(win_sata, sz, MV_WIN_SATA_SIZE); WIN_REG_BASE_IDX_WR(win_sata, sz, MV_WIN_SATA_SIZE); #endif WIN_REG_BASE_IDX_RD(win_sdhci, cr, MV_WIN_SDHCI_CTRL); WIN_REG_BASE_IDX_RD(win_sdhci, br, MV_WIN_SDHCI_BASE); WIN_REG_BASE_IDX_WR(win_sdhci, cr, MV_WIN_SDHCI_CTRL); WIN_REG_BASE_IDX_WR(win_sdhci, br, MV_WIN_SDHCI_BASE); #ifndef SOC_MV_DOVE WIN_REG_IDX_RD(ddr, br, MV_WIN_DDR_BASE, MV_DDR_CADR_BASE) WIN_REG_IDX_RD(ddr, sz, MV_WIN_DDR_SIZE, MV_DDR_CADR_BASE) WIN_REG_IDX_WR(ddr, br, MV_WIN_DDR_BASE, MV_DDR_CADR_BASE) WIN_REG_IDX_WR(ddr, sz, MV_WIN_DDR_SIZE, MV_DDR_CADR_BASE) #else /* * On 88F6781 (Dove) SoC DDR Controller is accessed through * single MBUS <-> AXI bridge. In this case we provide emulated * ddr_br_read() and ddr_sz_read() functions to keep compatibility * with common decoding windows setup code. */ static inline uint32_t ddr_br_read(int i) { uint32_t mmap; /* Read Memory Address Map Register for CS i */ mmap = bus_space_read_4(fdtbus_bs_tag, MV_DDR_CADR_BASE + (i * 0x10), 0); /* Return CS i base address */ return (mmap & 0xFF000000); } static inline uint32_t ddr_sz_read(int i) { uint32_t mmap, size; /* Read Memory Address Map Register for CS i */ mmap = bus_space_read_4(fdtbus_bs_tag, MV_DDR_CADR_BASE + (i * 0x10), 0); /* Extract size of CS space in 64kB units */ size = (1 << ((mmap >> 16) & 0x0F)); /* Return CS size and enable/disable status */ return (((size - 1) << 16) | (mmap & 0x01)); } #endif /************************************************************************** * Decode windows helper routines **************************************************************************/ void soc_dump_decode_win(void) { uint32_t dev, rev; int i; soc_id(&dev, &rev); for (i = 0; i < MV_WIN_CPU_MAX; i++) { printf("CPU window#%d: c 0x%08x, b 0x%08x", i, win_cpu_cr_read(i), win_cpu_br_read(i)); if (win_cpu_can_remap(i)) printf(", rl 0x%08x, rh 0x%08x", win_cpu_remap_l_read(i), win_cpu_remap_h_read(i)); printf("\n"); } printf("Internal regs base: 0x%08x\n", bus_space_read_4(fdtbus_bs_tag, MV_INTREGS_BASE, 0)); for (i = 0; i < MV_WIN_DDR_MAX; i++) printf("DDR CS#%d: b 0x%08x, s 0x%08x\n", i, ddr_br_read(i), ddr_sz_read(i)); } /************************************************************************** * CPU windows routines **************************************************************************/ int win_cpu_can_remap(int i) { uint32_t dev, rev; soc_id(&dev, &rev); /* Depending on the SoC certain windows have remap capability */ if ((dev == MV_DEV_88F5182 && i < 2) || (dev == MV_DEV_88F5281 && i < 4) || (dev == MV_DEV_88F6281 && i < 4) || (dev == MV_DEV_88F6282 && i < 4) || (dev == MV_DEV_88F6828 && i < 20) || (dev == MV_DEV_88F6820 && i < 20) || (dev == MV_DEV_88F6810 && i < 20) || (dev == MV_DEV_88RC8180 && i < 2) || (dev == MV_DEV_88F6781 && i < 4) || (dev == MV_DEV_MV78100_Z0 && i < 8) || ((dev & MV_DEV_FAMILY_MASK) == MV_DEV_DISCOVERY && i < 8)) return (1); return (0); } /* XXX This should check for overlapping remap fields too.. */ int decode_win_overlap(int win, int win_no, const struct decode_win *wintab) { const struct decode_win *tab; int i; tab = wintab; for (i = 0; i < win_no; i++, tab++) { if (i == win) /* Skip self */ continue; if ((tab->base + tab->size - 1) < (wintab + win)->base) continue; else if (((wintab + win)->base + (wintab + win)->size - 1) < tab->base) continue; else return (i); } return (-1); } static int decode_win_cpu_valid(void) { int i, j, rv; uint32_t b, e, s; if (cpu_wins_no > MV_WIN_CPU_MAX) { printf("CPU windows: too many entries: %d\n", cpu_wins_no); return (0); } rv = 1; for (i = 0; i < cpu_wins_no; i++) { if (cpu_wins[i].target == 0) { printf("CPU window#%d: DDR target window is not " "supposed to be reprogrammed!\n", i); rv = 0; } if (cpu_wins[i].remap != ~0 && win_cpu_can_remap(i) != 1) { printf("CPU window#%d: not capable of remapping, but " "val 0x%08x defined\n", i, cpu_wins[i].remap); rv = 0; } s = cpu_wins[i].size; b = cpu_wins[i].base; e = b + s - 1; if (s > (0xFFFFFFFF - b + 1)) { /* * XXX this boundary check should account for 64bit * and remapping.. */ printf("CPU window#%d: no space for size 0x%08x at " "0x%08x\n", i, s, b); rv = 0; continue; } if (b != rounddown2(b, s)) { printf("CPU window#%d: address 0x%08x is not aligned " "to 0x%08x\n", i, b, s); rv = 0; continue; } j = decode_win_overlap(i, cpu_wins_no, &cpu_wins[0]); if (j >= 0) { printf("CPU window#%d: (0x%08x - 0x%08x) overlaps " "with #%d (0x%08x - 0x%08x)\n", i, b, e, j, cpu_wins[j].base, cpu_wins[j].base + cpu_wins[j].size - 1); rv = 0; } } return (rv); } int decode_win_cpu_set(int target, int attr, vm_paddr_t base, uint32_t size, vm_paddr_t remap) { uint32_t br, cr; int win, i; if (remap == ~0) { win = MV_WIN_CPU_MAX - 1; i = -1; } else { win = 0; i = 1; } while ((win >= 0) && (win < MV_WIN_CPU_MAX)) { cr = win_cpu_cr_read(win); if ((cr & MV_WIN_CPU_ENABLE_BIT) == 0) break; if ((cr & ((0xff << MV_WIN_CPU_ATTR_SHIFT) | (0x1f << MV_WIN_CPU_TARGET_SHIFT))) == ((attr << MV_WIN_CPU_ATTR_SHIFT) | (target << MV_WIN_CPU_TARGET_SHIFT))) break; win += i; } if ((win < 0) || (win >= MV_WIN_CPU_MAX) || ((remap != ~0) && (win_cpu_can_remap(win) == 0))) return (-1); br = base & 0xffff0000; win_cpu_br_write(win, br); if (win_cpu_can_remap(win)) { if (remap != ~0) { win_cpu_remap_l_write(win, remap & 0xffff0000); win_cpu_remap_h_write(win, 0); } else { /* * Remap function is not used for a given window * (capable of remapping) - set remap field with the * same value as base. */ win_cpu_remap_l_write(win, base & 0xffff0000); win_cpu_remap_h_write(win, 0); } } cr = ((size - 1) & 0xffff0000) | (attr << MV_WIN_CPU_ATTR_SHIFT) | (target << MV_WIN_CPU_TARGET_SHIFT) | MV_WIN_CPU_ENABLE_BIT; win_cpu_cr_write(win, cr); return (0); } static void decode_win_cpu_setup(void) { int i; /* Disable all CPU windows */ for (i = 0; i < MV_WIN_CPU_MAX; i++) { win_cpu_cr_write(i, 0); win_cpu_br_write(i, 0); if (win_cpu_can_remap(i)) { win_cpu_remap_l_write(i, 0); win_cpu_remap_h_write(i, 0); } } for (i = 0; i < cpu_wins_no; i++) if (cpu_wins[i].target > 0) decode_win_cpu_set(cpu_wins[i].target, cpu_wins[i].attr, cpu_wins[i].base, cpu_wins[i].size, cpu_wins[i].remap); } #ifdef SOC_MV_ARMADAXP static int decode_win_sdram_fixup(void) { struct mem_region mr[FDT_MEM_REGIONS]; uint8_t window_valid[MV_WIN_DDR_MAX]; int mr_cnt, err, i, j; uint32_t valid_win_num = 0; /* Grab physical memory regions information from device tree. */ err = fdt_get_mem_regions(mr, &mr_cnt, NULL); if (err != 0) return (err); for (i = 0; i < MV_WIN_DDR_MAX; i++) window_valid[i] = 0; /* Try to match entries from device tree with settings from u-boot */ for (i = 0; i < mr_cnt; i++) { for (j = 0; j < MV_WIN_DDR_MAX; j++) { if (ddr_is_active(j) && (ddr_base(j) == mr[i].mr_start) && (ddr_size(j) == mr[i].mr_size)) { window_valid[j] = 1; valid_win_num++; } } } if (mr_cnt != valid_win_num) return (EINVAL); /* Destroy windows without corresponding device tree entry */ for (j = 0; j < MV_WIN_DDR_MAX; j++) { if (ddr_is_active(j) && (window_valid[j] != 1)) { printf("Disabling SDRAM decoding window: %d\n", j); ddr_disable(j); } } return (0); } #endif /* * Check if we're able to cover all active DDR banks. */ static int decode_win_can_cover_ddr(int max) { int i, c; c = 0; for (i = 0; i < MV_WIN_DDR_MAX; i++) if (ddr_is_active(i)) c++; if (c > max) { printf("Unable to cover all active DDR banks: " "%d, available windows: %d\n", c, max); return (0); } return (1); } /************************************************************************** * DDR windows routines **************************************************************************/ int ddr_is_active(int i) { if (ddr_sz_read(i) & 0x1) return (1); return (0); } void ddr_disable(int i) { ddr_sz_write(i, 0); ddr_br_write(i, 0); } uint32_t ddr_base(int i) { return (ddr_br_read(i) & 0xff000000); } uint32_t ddr_size(int i) { return ((ddr_sz_read(i) | 0x00ffffff) + 1); } uint32_t ddr_attr(int i) { uint32_t dev, rev, attr; soc_id(&dev, &rev); if (dev == MV_DEV_88RC8180) return ((ddr_sz_read(i) & 0xf0) >> 4); if (dev == MV_DEV_88F6781) return (0); attr = (i == 0 ? 0xe : (i == 1 ? 0xd : (i == 2 ? 0xb : (i == 3 ? 0x7 : 0xff)))); if (platform_io_coherent) attr |= 0x10; return (attr); } uint32_t ddr_target(int i) { uint32_t dev, rev; soc_id(&dev, &rev); if (dev == MV_DEV_88RC8180) { i = (ddr_sz_read(i) & 0xf0) >> 4; return (i == 0xe ? 0xc : (i == 0xd ? 0xd : (i == 0xb ? 0xe : (i == 0x7 ? 0xf : 0xc)))); } /* * On SOCs other than 88RC8180 Mbus unit ID for * DDR SDRAM controller is always 0x0. */ return (0); } /************************************************************************** * CESA windows routines **************************************************************************/ static int decode_win_cesa_valid(void) { return (decode_win_can_cover_ddr(MV_WIN_CESA_MAX)); } static void decode_win_cesa_dump(u_long base) { int i; for (i = 0; i < MV_WIN_CESA_MAX; i++) printf("CESA window#%d: c 0x%08x, b 0x%08x\n", i, win_cesa_cr_read(base, i), win_cesa_br_read(base, i)); } /* * Set CESA decode windows. */ static void decode_win_cesa_setup(u_long base) { uint32_t br, cr; uint64_t size; int i, j; for (i = 0; i < MV_WIN_CESA_MAX; i++) { win_cesa_cr_write(base, i, 0); win_cesa_br_write(base, i, 0); } /* Only access to active DRAM banks is required */ for (i = 0; i < MV_WIN_DDR_MAX; i++) { if (ddr_is_active(i)) { br = ddr_base(i); size = ddr_size(i); #ifdef SOC_MV_ARMADA38X /* * Armada 38x SoC's equipped with 4GB DRAM * suffer freeze during CESA operation, if * MBUS window opened at given DRAM CS reaches * end of the address space. Apply a workaround * by setting the window size to the closest possible * value, i.e. divide it by 2. */ if (size + ddr_base(i) == 0x100000000ULL) size /= 2; #endif cr = (((size - 1) & 0xffff0000) | (ddr_attr(i) << IO_WIN_ATTR_SHIFT) | (ddr_target(i) << IO_WIN_TGT_SHIFT) | IO_WIN_ENA_MASK); /* Set the first free CESA window */ for (j = 0; j < MV_WIN_CESA_MAX; j++) { if (win_cesa_cr_read(base, j) & 0x1) continue; win_cesa_br_write(base, j, br); win_cesa_cr_write(base, j, cr); break; } } } } /************************************************************************** * USB windows routines **************************************************************************/ static int decode_win_usb_valid(void) { return (decode_win_can_cover_ddr(MV_WIN_USB_MAX)); } static void decode_win_usb_dump(u_long base) { int i; if (pm_is_disabled(CPU_PM_CTRL_USB(usb_port - 1))) return; for (i = 0; i < MV_WIN_USB_MAX; i++) printf("USB window#%d: c 0x%08x, b 0x%08x\n", i, win_usb_cr_read(base, i), win_usb_br_read(base, i)); } /* * Set USB decode windows. */ static void decode_win_usb_setup(u_long base) { uint32_t br, cr; int i, j; if (pm_is_disabled(CPU_PM_CTRL_USB(usb_port))) return; usb_port++; for (i = 0; i < MV_WIN_USB_MAX; i++) { win_usb_cr_write(base, i, 0); win_usb_br_write(base, i, 0); } /* Only access to active DRAM banks is required */ for (i = 0; i < MV_WIN_DDR_MAX; i++) { if (ddr_is_active(i)) { br = ddr_base(i); /* * XXX for 6281 we should handle Mbus write * burst limit field in the ctrl reg */ cr = (((ddr_size(i) - 1) & 0xffff0000) | (ddr_attr(i) << 8) | (ddr_target(i) << 4) | 1); /* Set the first free USB window */ for (j = 0; j < MV_WIN_USB_MAX; j++) { if (win_usb_cr_read(base, j) & 0x1) continue; win_usb_br_write(base, j, br); win_usb_cr_write(base, j, cr); break; } } } } /************************************************************************** * USB3 windows routines **************************************************************************/ #ifdef SOC_MV_ARMADA38X static int decode_win_usb3_valid(void) { return (decode_win_can_cover_ddr(MV_WIN_USB3_MAX)); } static void decode_win_usb3_dump(u_long base) { int i; for (i = 0; i < MV_WIN_USB3_MAX; i++) printf("USB3.0 window#%d: c 0x%08x, b 0x%08x\n", i, win_usb3_cr_read(base, i), win_usb3_br_read(base, i)); } /* * Set USB3 decode windows */ static void decode_win_usb3_setup(u_long base) { uint32_t br, cr; int i, j; for (i = 0; i < MV_WIN_USB3_MAX; i++) { win_usb3_cr_write(base, i, 0); win_usb3_br_write(base, i, 0); } /* Only access to active DRAM banks is required */ for (i = 0; i < MV_WIN_DDR_MAX; i++) { if (ddr_is_active(i)) { br = ddr_base(i); cr = (((ddr_size(i) - 1) & (IO_WIN_SIZE_MASK << IO_WIN_SIZE_SHIFT)) | (ddr_attr(i) << IO_WIN_ATTR_SHIFT) | (ddr_target(i) << IO_WIN_TGT_SHIFT) | IO_WIN_ENA_MASK); /* Set the first free USB3.0 window */ for (j = 0; j < MV_WIN_USB3_MAX; j++) { if (win_usb3_cr_read(base, j) & IO_WIN_ENA_MASK) continue; win_usb3_br_write(base, j, br); win_usb3_cr_write(base, j, cr); break; } } } } #else /* * Provide dummy functions to satisfy the build * for SoCs not equipped with USB3 */ static int decode_win_usb3_valid(void) { return (1); } static void decode_win_usb3_setup(u_long base) { } static void decode_win_usb3_dump(u_long base) { } #endif /************************************************************************** * ETH windows routines **************************************************************************/ static int win_eth_can_remap(int i) { /* ETH encode windows 0-3 have remap capability */ if (i < 4) return (1); return (0); } static int eth_bare_read(uint32_t base, int i) { uint32_t v; v = win_eth_bare_read(base); v &= (1 << i); return (v >> i); } static void eth_bare_write(uint32_t base, int i, int val) { uint32_t v; v = win_eth_bare_read(base); v &= ~(1 << i); v |= (val << i); win_eth_bare_write(base, v); } static void eth_epap_write(uint32_t base, int i, int val) { uint32_t v; v = win_eth_epap_read(base); v &= ~(0x3 << (i * 2)); v |= (val << (i * 2)); win_eth_epap_write(base, v); } static void decode_win_eth_dump(u_long base) { int i; if (pm_is_disabled(CPU_PM_CTRL_GE(eth_port - 1))) return; for (i = 0; i < MV_WIN_ETH_MAX; i++) { printf("ETH window#%d: b 0x%08x, s 0x%08x", i, win_eth_br_read(base, i), win_eth_sz_read(base, i)); if (win_eth_can_remap(i)) printf(", ha 0x%08x", win_eth_har_read(base, i)); printf("\n"); } printf("ETH windows: bare 0x%08x, epap 0x%08x\n", win_eth_bare_read(base), win_eth_epap_read(base)); } #define MV_WIN_ETH_DDR_TRGT(n) ddr_target(n) static void decode_win_eth_setup(u_long base) { uint32_t br, sz; int i, j; if (pm_is_disabled(CPU_PM_CTRL_GE(eth_port))) return; eth_port++; /* Disable, clear and revoke protection for all ETH windows */ for (i = 0; i < MV_WIN_ETH_MAX; i++) { eth_bare_write(base, i, 1); eth_epap_write(base, i, 0); win_eth_br_write(base, i, 0); win_eth_sz_write(base, i, 0); if (win_eth_can_remap(i)) win_eth_har_write(base, i, 0); } /* Only access to active DRAM banks is required */ for (i = 0; i < MV_WIN_DDR_MAX; i++) if (ddr_is_active(i)) { br = ddr_base(i) | (ddr_attr(i) << 8) | MV_WIN_ETH_DDR_TRGT(i); sz = ((ddr_size(i) - 1) & 0xffff0000); /* Set the first free ETH window */ for (j = 0; j < MV_WIN_ETH_MAX; j++) { if (eth_bare_read(base, j) == 0) continue; win_eth_br_write(base, j, br); win_eth_sz_write(base, j, sz); /* XXX remapping ETH windows not supported */ /* Set protection RW */ eth_epap_write(base, j, 0x3); /* Enable window */ eth_bare_write(base, j, 0); break; } } } static void decode_win_neta_dump(u_long base) { decode_win_eth_dump(base + MV_WIN_NETA_OFFSET); } static void decode_win_neta_setup(u_long base) { decode_win_eth_setup(base + MV_WIN_NETA_OFFSET); } static int decode_win_eth_valid(void) { return (decode_win_can_cover_ddr(MV_WIN_ETH_MAX)); } /************************************************************************** * PCIE windows routines **************************************************************************/ static void decode_win_pcie_dump(u_long base) { int i; printf("PCIE windows base 0x%08lx\n", base); for (i = 0; i < MV_WIN_PCIE_MAX; i++) printf("PCIE window#%d: cr 0x%08x br 0x%08x remap 0x%08x\n", i, win_pcie_cr_read(base, i), win_pcie_br_read(base, i), win_pcie_remap_read(base, i)); for (i = 0; i < MV_PCIE_BAR_MAX; i++) printf("PCIE bar#%d: cr 0x%08x br 0x%08x brh 0x%08x\n", i, pcie_bar_cr_read(base, i), pcie_bar_br_read(base, i), pcie_bar_brh_read(base, i)); } void decode_win_pcie_setup(u_long base) { uint32_t size = 0, ddrbase = ~0; uint32_t cr, br; int i, j; for (i = 0; i < MV_PCIE_BAR_MAX; i++) { pcie_bar_br_write(base, i, MV_PCIE_BAR_64BIT | MV_PCIE_BAR_PREFETCH_EN); if (i < 3) pcie_bar_brh_write(base, i, 0); if (i > 0) pcie_bar_cr_write(base, i, 0); } for (i = 0; i < MV_WIN_PCIE_MAX; i++) { win_pcie_cr_write(base, i, 0); win_pcie_br_write(base, i, 0); win_pcie_remap_write(base, i, 0); } /* On End-Point only set BAR size to 1MB regardless of DDR size */ if ((bus_space_read_4(fdtbus_bs_tag, base, MV_PCIE_CONTROL) & MV_PCIE_ROOT_CMPLX) == 0) { pcie_bar_cr_write(base, 1, 0xf0000 | 1); return; } for (i = 0; i < MV_WIN_DDR_MAX; i++) { if (ddr_is_active(i)) { /* Map DDR to BAR 1 */ cr = (ddr_size(i) - 1) & 0xffff0000; size += ddr_size(i) & 0xffff0000; cr |= (ddr_attr(i) << 8) | (ddr_target(i) << 4) | 1; br = ddr_base(i); if (br < ddrbase) ddrbase = br; /* Use the first available PCIE window */ for (j = 0; j < MV_WIN_PCIE_MAX; j++) { if (win_pcie_cr_read(base, j) != 0) continue; win_pcie_br_write(base, j, br); win_pcie_cr_write(base, j, cr); break; } } } /* * Upper 16 bits in BAR register is interpreted as BAR size * (in 64 kB units) plus 64kB, so subtract 0x10000 * form value passed to register to get correct value. */ size -= 0x10000; pcie_bar_cr_write(base, 1, size | 1); pcie_bar_br_write(base, 1, ddrbase | MV_PCIE_BAR_64BIT | MV_PCIE_BAR_PREFETCH_EN); pcie_bar_br_write(base, 0, fdt_immr_pa | MV_PCIE_BAR_64BIT | MV_PCIE_BAR_PREFETCH_EN); } static int decode_win_pcie_valid(void) { return (decode_win_can_cover_ddr(MV_WIN_PCIE_MAX)); } /************************************************************************** * IDMA windows routines **************************************************************************/ #if defined(SOC_MV_ORION) || defined(SOC_MV_DISCOVERY) static int idma_bare_read(u_long base, int i) { uint32_t v; v = win_idma_bare_read(base); v &= (1 << i); return (v >> i); } static void idma_bare_write(u_long base, int i, int val) { uint32_t v; v = win_idma_bare_read(base); v &= ~(1 << i); v |= (val << i); win_idma_bare_write(base, v); } /* * Sets channel protection 'val' for window 'w' on channel 'c' */ static void idma_cap_write(u_long base, int c, int w, int val) { uint32_t v; v = win_idma_cap_read(base, c); v &= ~(0x3 << (w * 2)); v |= (val << (w * 2)); win_idma_cap_write(base, c, v); } /* * Set protection 'val' on all channels for window 'w' */ static void idma_set_prot(u_long base, int w, int val) { int c; for (c = 0; c < MV_IDMA_CHAN_MAX; c++) idma_cap_write(base, c, w, val); } static int win_idma_can_remap(int i) { /* IDMA decode windows 0-3 have remap capability */ if (i < 4) return (1); return (0); } void decode_win_idma_setup(u_long base) { uint32_t br, sz; int i, j; if (pm_is_disabled(CPU_PM_CTRL_IDMA)) return; /* * Disable and clear all IDMA windows, revoke protection for all channels */ for (i = 0; i < MV_WIN_IDMA_MAX; i++) { idma_bare_write(base, i, 1); win_idma_br_write(base, i, 0); win_idma_sz_write(base, i, 0); if (win_idma_can_remap(i) == 1) win_idma_har_write(base, i, 0); } for (i = 0; i < MV_IDMA_CHAN_MAX; i++) win_idma_cap_write(base, i, 0); /* * Set up access to all active DRAM banks */ for (i = 0; i < MV_WIN_DDR_MAX; i++) if (ddr_is_active(i)) { br = ddr_base(i) | (ddr_attr(i) << 8) | ddr_target(i); sz = ((ddr_size(i) - 1) & 0xffff0000); /* Place DDR entries in non-remapped windows */ for (j = 0; j < MV_WIN_IDMA_MAX; j++) if (win_idma_can_remap(j) != 1 && idma_bare_read(base, j) == 1) { /* Configure window */ win_idma_br_write(base, j, br); win_idma_sz_write(base, j, sz); /* Set protection RW on all channels */ idma_set_prot(base, j, 0x3); /* Enable window */ idma_bare_write(base, j, 0); break; } } /* * Remaining targets -- from statically defined table */ for (i = 0; i < idma_wins_no; i++) if (idma_wins[i].target > 0) { br = (idma_wins[i].base & 0xffff0000) | (idma_wins[i].attr << 8) | idma_wins[i].target; sz = ((idma_wins[i].size - 1) & 0xffff0000); /* Set the first free IDMA window */ for (j = 0; j < MV_WIN_IDMA_MAX; j++) { if (idma_bare_read(base, j) == 0) continue; /* Configure window */ win_idma_br_write(base, j, br); win_idma_sz_write(base, j, sz); if (win_idma_can_remap(j) && idma_wins[j].remap >= 0) win_idma_har_write(base, j, idma_wins[j].remap); /* Set protection RW on all channels */ idma_set_prot(base, j, 0x3); /* Enable window */ idma_bare_write(base, j, 0); break; } } } int decode_win_idma_valid(void) { const struct decode_win *wintab; int c, i, j, rv; uint32_t b, e, s; if (idma_wins_no > MV_WIN_IDMA_MAX) { printf("IDMA windows: too many entries: %d\n", idma_wins_no); return (0); } for (i = 0, c = 0; i < MV_WIN_DDR_MAX; i++) if (ddr_is_active(i)) c++; if (idma_wins_no > (MV_WIN_IDMA_MAX - c)) { printf("IDMA windows: too many entries: %d, available: %d\n", idma_wins_no, MV_WIN_IDMA_MAX - c); return (0); } wintab = idma_wins; rv = 1; for (i = 0; i < idma_wins_no; i++, wintab++) { if (wintab->target == 0) { printf("IDMA window#%d: DDR target window is not " "supposed to be reprogrammed!\n", i); rv = 0; } if (wintab->remap >= 0 && win_cpu_can_remap(i) != 1) { printf("IDMA window#%d: not capable of remapping, but " "val 0x%08x defined\n", i, wintab->remap); rv = 0; } s = wintab->size; b = wintab->base; e = b + s - 1; if (s > (0xFFFFFFFF - b + 1)) { /* XXX this boundary check should account for 64bit and * remapping.. */ printf("IDMA window#%d: no space for size 0x%08x at " "0x%08x\n", i, s, b); rv = 0; continue; } j = decode_win_overlap(i, idma_wins_no, &idma_wins[0]); if (j >= 0) { printf("IDMA window#%d: (0x%08x - 0x%08x) overlaps " "with #%d (0x%08x - 0x%08x)\n", i, b, e, j, idma_wins[j].base, idma_wins[j].base + idma_wins[j].size - 1); rv = 0; } } return (rv); } void decode_win_idma_dump(u_long base) { int i; if (pm_is_disabled(CPU_PM_CTRL_IDMA)) return; for (i = 0; i < MV_WIN_IDMA_MAX; i++) { printf("IDMA window#%d: b 0x%08x, s 0x%08x", i, win_idma_br_read(base, i), win_idma_sz_read(base, i)); if (win_idma_can_remap(i)) printf(", ha 0x%08x", win_idma_har_read(base, i)); printf("\n"); } for (i = 0; i < MV_IDMA_CHAN_MAX; i++) printf("IDMA channel#%d: ap 0x%08x\n", i, win_idma_cap_read(base, i)); printf("IDMA windows: bare 0x%08x\n", win_idma_bare_read(base)); } #else /* Provide dummy functions to satisfy the build for SoCs not equipped with IDMA */ int decode_win_idma_valid(void) { return (1); } void decode_win_idma_setup(u_long base) { } void decode_win_idma_dump(u_long base) { } #endif /************************************************************************** * XOR windows routines **************************************************************************/ #if defined(SOC_MV_KIRKWOOD) || defined(SOC_MV_DISCOVERY) static int xor_ctrl_read(u_long base, int i, int c, int e) { uint32_t v; v = win_xor_ctrl_read(base, c, e); v &= (1 << i); return (v >> i); } static void xor_ctrl_write(u_long base, int i, int c, int e, int val) { uint32_t v; v = win_xor_ctrl_read(base, c, e); v &= ~(1 << i); v |= (val << i); win_xor_ctrl_write(base, c, e, v); } /* * Set channel protection 'val' for window 'w' on channel 'c' */ static void xor_chan_write(u_long base, int c, int e, int w, int val) { uint32_t v; v = win_xor_ctrl_read(base, c, e); v &= ~(0x3 << (w * 2 + 16)); v |= (val << (w * 2 + 16)); win_xor_ctrl_write(base, c, e, v); } /* * Set protection 'val' on all channels for window 'w' on engine 'e' */ static void xor_set_prot(u_long base, int w, int e, int val) { int c; for (c = 0; c < MV_XOR_CHAN_MAX; c++) xor_chan_write(base, c, e, w, val); } static int win_xor_can_remap(int i) { /* XOR decode windows 0-3 have remap capability */ if (i < 4) return (1); return (0); } static int xor_max_eng(void) { uint32_t dev, rev; soc_id(&dev, &rev); switch (dev) { case MV_DEV_88F6281: case MV_DEV_88F6282: case MV_DEV_MV78130: case MV_DEV_MV78160: case MV_DEV_MV78230: case MV_DEV_MV78260: case MV_DEV_MV78460: return (2); case MV_DEV_MV78100: case MV_DEV_MV78100_Z0: return (1); default: return (0); } } static void xor_active_dram(u_long base, int c, int e, int *window) { uint32_t br, sz; int i, m, w; /* * Set up access to all active DRAM banks */ m = xor_max_eng(); for (i = 0; i < m; i++) if (ddr_is_active(i)) { br = ddr_base(i) | (ddr_attr(i) << 8) | ddr_target(i); sz = ((ddr_size(i) - 1) & 0xffff0000); /* Place DDR entries in non-remapped windows */ for (w = 0; w < MV_WIN_XOR_MAX; w++) if (win_xor_can_remap(w) != 1 && (xor_ctrl_read(base, w, c, e) == 0) && w > *window) { /* Configure window */ win_xor_br_write(base, w, e, br); win_xor_sz_write(base, w, e, sz); /* Set protection RW on all channels */ xor_set_prot(base, w, e, 0x3); /* Enable window */ xor_ctrl_write(base, w, c, e, 1); (*window)++; break; } } } void decode_win_xor_setup(u_long base) { uint32_t br, sz; int i, j, z, e = 1, m, window; if (pm_is_disabled(CPU_PM_CTRL_XOR)) return; /* * Disable and clear all XOR windows, revoke protection for all * channels */ m = xor_max_eng(); for (j = 0; j < m; j++, e--) { /* Number of non-remaped windows */ window = MV_XOR_NON_REMAP - 1; for (i = 0; i < MV_WIN_XOR_MAX; i++) { win_xor_br_write(base, i, e, 0); win_xor_sz_write(base, i, e, 0); } if (win_xor_can_remap(i) == 1) win_xor_har_write(base, i, e, 0); for (i = 0; i < MV_XOR_CHAN_MAX; i++) { win_xor_ctrl_write(base, i, e, 0); xor_active_dram(base, i, e, &window); } /* * Remaining targets -- from a statically defined table */ for (i = 0; i < xor_wins_no; i++) if (xor_wins[i].target > 0) { br = (xor_wins[i].base & 0xffff0000) | (xor_wins[i].attr << 8) | xor_wins[i].target; sz = ((xor_wins[i].size - 1) & 0xffff0000); /* Set the first free XOR window */ for (z = 0; z < MV_WIN_XOR_MAX; z++) { if (xor_ctrl_read(base, z, 0, e) && xor_ctrl_read(base, z, 1, e)) continue; /* Configure window */ win_xor_br_write(base, z, e, br); win_xor_sz_write(base, z, e, sz); if (win_xor_can_remap(z) && xor_wins[z].remap >= 0) win_xor_har_write(base, z, e, xor_wins[z].remap); /* Set protection RW on all channels */ xor_set_prot(base, z, e, 0x3); /* Enable window */ xor_ctrl_write(base, z, 0, e, 1); xor_ctrl_write(base, z, 1, e, 1); break; } } } } int decode_win_xor_valid(void) { const struct decode_win *wintab; int c, i, j, rv; uint32_t b, e, s; if (xor_wins_no > MV_WIN_XOR_MAX) { printf("XOR windows: too many entries: %d\n", xor_wins_no); return (0); } for (i = 0, c = 0; i < MV_WIN_DDR_MAX; i++) if (ddr_is_active(i)) c++; if (xor_wins_no > (MV_WIN_XOR_MAX - c)) { printf("XOR windows: too many entries: %d, available: %d\n", xor_wins_no, MV_WIN_IDMA_MAX - c); return (0); } wintab = xor_wins; rv = 1; for (i = 0; i < xor_wins_no; i++, wintab++) { if (wintab->target == 0) { printf("XOR window#%d: DDR target window is not " "supposed to be reprogrammed!\n", i); rv = 0; } if (wintab->remap >= 0 && win_cpu_can_remap(i) != 1) { printf("XOR window#%d: not capable of remapping, but " "val 0x%08x defined\n", i, wintab->remap); rv = 0; } s = wintab->size; b = wintab->base; e = b + s - 1; if (s > (0xFFFFFFFF - b + 1)) { /* * XXX this boundary check should account for 64bit * and remapping.. */ printf("XOR window#%d: no space for size 0x%08x at " "0x%08x\n", i, s, b); rv = 0; continue; } j = decode_win_overlap(i, xor_wins_no, &xor_wins[0]); if (j >= 0) { printf("XOR window#%d: (0x%08x - 0x%08x) overlaps " "with #%d (0x%08x - 0x%08x)\n", i, b, e, j, xor_wins[j].base, xor_wins[j].base + xor_wins[j].size - 1); rv = 0; } } return (rv); } void decode_win_xor_dump(u_long base) { int i, j; int e = 1; if (pm_is_disabled(CPU_PM_CTRL_XOR)) return; for (j = 0; j < xor_max_eng(); j++, e--) { for (i = 0; i < MV_WIN_XOR_MAX; i++) { printf("XOR window#%d: b 0x%08x, s 0x%08x", i, win_xor_br_read(base, i, e), win_xor_sz_read(base, i, e)); if (win_xor_can_remap(i)) printf(", ha 0x%08x", win_xor_har_read(base, i, e)); printf("\n"); } for (i = 0; i < MV_XOR_CHAN_MAX; i++) printf("XOR control#%d: 0x%08x\n", i, win_xor_ctrl_read(base, i, e)); } } #else /* Provide dummy functions to satisfy the build for SoCs not equipped with XOR */ static int decode_win_xor_valid(void) { return (1); } static void decode_win_xor_setup(u_long base) { } static void decode_win_xor_dump(u_long base) { } #endif /************************************************************************** * SATA windows routines **************************************************************************/ static void decode_win_sata_setup(u_long base) { uint32_t cr, br; int i, j; if (pm_is_disabled(CPU_PM_CTRL_SATA)) return; for (i = 0; i < MV_WIN_SATA_MAX; i++) { win_sata_cr_write(base, i, 0); win_sata_br_write(base, i, 0); } for (i = 0; i < MV_WIN_DDR_MAX; i++) if (ddr_is_active(i)) { cr = ((ddr_size(i) - 1) & 0xffff0000) | (ddr_attr(i) << 8) | (ddr_target(i) << 4) | 1; br = ddr_base(i); /* Use the first available SATA window */ for (j = 0; j < MV_WIN_SATA_MAX; j++) { if ((win_sata_cr_read(base, j) & 1) != 0) continue; win_sata_br_write(base, j, br); win_sata_cr_write(base, j, cr); break; } } } #ifdef SOC_MV_ARMADA38X /* * Configure AHCI decoding windows */ static void decode_win_ahci_setup(u_long base) { uint32_t br, cr, sz; int i, j; for (i = 0; i < MV_WIN_SATA_MAX; i++) { win_sata_cr_write(base, i, 0); win_sata_br_write(base, i, 0); win_sata_sz_write(base, i, 0); } for (i = 0; i < MV_WIN_DDR_MAX; i++) { if (ddr_is_active(i)) { cr = (ddr_attr(i) << IO_WIN_ATTR_SHIFT) | (ddr_target(i) << IO_WIN_TGT_SHIFT) | IO_WIN_ENA_MASK; br = ddr_base(i); sz = (ddr_size(i) - 1) & (IO_WIN_SIZE_MASK << IO_WIN_SIZE_SHIFT); /* Use first available SATA window */ for (j = 0; j < MV_WIN_SATA_MAX; j++) { if (win_sata_cr_read(base, j) & IO_WIN_ENA_MASK) continue; /* BASE is set to DRAM base (0x00000000) */ win_sata_br_write(base, j, br); /* CTRL targets DRAM ctrl with 0x0E or 0x0D */ win_sata_cr_write(base, j, cr); /* SIZE is set to 16MB - max value */ win_sata_sz_write(base, j, sz); break; } } } } static void decode_win_ahci_dump(u_long base) { int i; for (i = 0; i < MV_WIN_SATA_MAX; i++) printf("SATA window#%d: cr 0x%08x, br 0x%08x, sz 0x%08x\n", i, win_sata_cr_read(base, i), win_sata_br_read(base, i), win_sata_sz_read(base,i)); } #else /* * Provide dummy functions to satisfy the build * for SoC's not equipped with AHCI controller */ static void decode_win_ahci_setup(u_long base) { } static void decode_win_ahci_dump(u_long base) { } #endif static int decode_win_sata_valid(void) { uint32_t dev, rev; soc_id(&dev, &rev); if (dev == MV_DEV_88F5281) return (1); return (decode_win_can_cover_ddr(MV_WIN_SATA_MAX)); } static void decode_win_sdhci_setup(u_long base) { uint32_t cr, br; int i, j; for (i = 0; i < MV_WIN_SDHCI_MAX; i++) { win_sdhci_cr_write(base, i, 0); win_sdhci_br_write(base, i, 0); } for (i = 0; i < MV_WIN_DDR_MAX; i++) if (ddr_is_active(i)) { br = ddr_base(i); cr = (((ddr_size(i) - 1) & (IO_WIN_SIZE_MASK << IO_WIN_SIZE_SHIFT)) | (ddr_attr(i) << IO_WIN_ATTR_SHIFT) | (ddr_target(i) << IO_WIN_TGT_SHIFT) | IO_WIN_ENA_MASK); /* Use the first available SDHCI window */ for (j = 0; j < MV_WIN_SDHCI_MAX; j++) { if (win_sdhci_cr_read(base, j) & IO_WIN_ENA_MASK) continue; win_sdhci_cr_write(base, j, cr); win_sdhci_br_write(base, j, br); break; } } } static void decode_win_sdhci_dump(u_long base) { int i; for (i = 0; i < MV_WIN_SDHCI_MAX; i++) printf("SDHCI window#%d: c 0x%08x, b 0x%08x\n", i, win_sdhci_cr_read(base, i), win_sdhci_br_read(base, i)); } static int decode_win_sdhci_valid(void) { #ifdef SOC_MV_ARMADA38X return (decode_win_can_cover_ddr(MV_WIN_SDHCI_MAX)); #endif /* Satisfy platforms not equipped with this controller. */ return (1); } /************************************************************************** * FDT parsing routines. **************************************************************************/ static int fdt_get_ranges(const char *nodename, void *buf, int size, int *tuples, int *tuplesize) { phandle_t node; pcell_t addr_cells, par_addr_cells, size_cells; int len, tuple_size, tuples_count; node = OF_finddevice(nodename); if (node == -1) return (EINVAL); if ((fdt_addrsize_cells(node, &addr_cells, &size_cells)) != 0) return (ENXIO); par_addr_cells = fdt_parent_addr_cells(node); if (par_addr_cells > 2) return (ERANGE); tuple_size = sizeof(pcell_t) * (addr_cells + par_addr_cells + size_cells); /* Note the OF_getprop_alloc() cannot be used at this early stage. */ len = OF_getprop(node, "ranges", buf, size); /* * XXX this does not handle the empty 'ranges;' case, which is * legitimate and should be allowed. */ tuples_count = len / tuple_size; if (tuples_count <= 0) return (ERANGE); if (par_addr_cells > 2 || addr_cells > 2 || size_cells > 2) return (ERANGE); *tuples = tuples_count; *tuplesize = tuple_size; return (0); } static int win_cpu_from_dt(void) { pcell_t ranges[48]; phandle_t node; int i, entry_size, err, t, tuple_size, tuples; u_long sram_base, sram_size; t = 0; /* Retrieve 'ranges' property of '/localbus' node. */ if ((err = fdt_get_ranges("/localbus", ranges, sizeof(ranges), &tuples, &tuple_size)) == 0) { /* * Fill CPU decode windows table. */ bzero((void *)&cpu_win_tbl, sizeof(cpu_win_tbl)); entry_size = tuple_size / sizeof(pcell_t); cpu_wins_no = tuples; /* Check range */ if (tuples > nitems(cpu_win_tbl)) { debugf("too many tuples to fit into cpu_win_tbl\n"); return (ENOMEM); } for (i = 0, t = 0; t < tuples; i += entry_size, t++) { cpu_win_tbl[t].target = 1; cpu_win_tbl[t].attr = fdt32_to_cpu(ranges[i + 1]); cpu_win_tbl[t].base = fdt32_to_cpu(ranges[i + 2]); cpu_win_tbl[t].size = fdt32_to_cpu(ranges[i + 3]); cpu_win_tbl[t].remap = ~0; debugf("target = 0x%0x attr = 0x%0x base = 0x%0x " "size = 0x%0x remap = 0x%0x\n", cpu_win_tbl[t].target, cpu_win_tbl[t].attr, cpu_win_tbl[t].base, cpu_win_tbl[t].size, cpu_win_tbl[t].remap); } } /* * Retrieve CESA SRAM data. */ if ((node = OF_finddevice("sram")) != -1) if (ofw_bus_node_is_compatible(node, "mrvl,cesa-sram")) goto moveon; - if ((node = OF_finddevice("/")) == 0) + if ((node = OF_finddevice("/")) == -1) return (ENXIO); if ((node = fdt_find_compatible(node, "mrvl,cesa-sram", 0)) == 0) /* SRAM block is not always present. */ return (0); moveon: sram_base = sram_size = 0; if (fdt_regsize(node, &sram_base, &sram_size) != 0) return (EINVAL); /* Check range */ if (t >= nitems(cpu_win_tbl)) { debugf("cannot fit CESA tuple into cpu_win_tbl\n"); return (ENOMEM); } cpu_win_tbl[t].target = MV_WIN_CESA_TARGET; #ifdef SOC_MV_ARMADA38X cpu_win_tbl[t].attr = MV_WIN_CESA_ATTR(0); #else cpu_win_tbl[t].attr = MV_WIN_CESA_ATTR(1); #endif cpu_win_tbl[t].base = sram_base; cpu_win_tbl[t].size = sram_size; cpu_win_tbl[t].remap = ~0; cpu_wins_no++; debugf("sram: base = 0x%0lx size = 0x%0lx\n", sram_base, sram_size); /* Check if there is a second CESA node */ while ((node = OF_peer(node)) != 0) { if (ofw_bus_node_is_compatible(node, "mrvl,cesa-sram")) { if (fdt_regsize(node, &sram_base, &sram_size) != 0) return (EINVAL); break; } } if (node == 0) return (0); t++; if (t >= nitems(cpu_win_tbl)) { debugf("cannot fit CESA tuple into cpu_win_tbl\n"); return (ENOMEM); } /* Configure window for CESA1 */ cpu_win_tbl[t].target = MV_WIN_CESA_TARGET; cpu_win_tbl[t].attr = MV_WIN_CESA_ATTR(1); cpu_win_tbl[t].base = sram_base; cpu_win_tbl[t].size = sram_size; cpu_win_tbl[t].remap = ~0; cpu_wins_no++; debugf("sram: base = 0x%0lx size = 0x%0lx\n", sram_base, sram_size); return (0); } static int fdt_win_process(phandle_t child) { int i; struct soc_node_spec *soc_node; int addr_cells, size_cells; pcell_t reg[8]; u_long size, base; for (i = 0; soc_nodes[i].compat != NULL; i++) { soc_node = &soc_nodes[i]; /* Setup only for enabled devices */ if (ofw_bus_node_status_okay(child) == 0) continue; if (!ofw_bus_node_is_compatible(child, soc_node->compat)) continue; if (fdt_addrsize_cells(OF_parent(child), &addr_cells, &size_cells)) return (ENXIO); if ((sizeof(pcell_t) * (addr_cells + size_cells)) > sizeof(reg)) return (ENOMEM); if (OF_getprop(child, "reg", ®, sizeof(reg)) <= 0) return (EINVAL); if (addr_cells <= 2) base = fdt_data_get(®[0], addr_cells); else base = fdt_data_get(®[addr_cells - 2], 2); size = fdt_data_get(®[addr_cells], size_cells); base = (base & 0x000fffff) | fdt_immr_va; if (soc_node->decode_handler != NULL) soc_node->decode_handler(base); else return (ENXIO); if (MV_DUMP_WIN && (soc_node->dump_handler != NULL)) soc_node->dump_handler(base); } return (0); } static int fdt_win_setup(void) { phandle_t node, child, sb; phandle_t child_pci; int err; sb = 0; node = OF_finddevice("/"); if (node == -1) panic("fdt_win_setup: no root node"); /* Allow for coherent transactions on the A38x MBUS */ if (ofw_bus_node_is_compatible(node, "marvell,armada380")) platform_io_coherent = true; /* * Traverse through all children of root and simple-bus nodes. * For each found device retrieve decode windows data (if applicable). */ child = OF_child(node); while (child != 0) { /* Lookup for callback and run */ err = fdt_win_process(child); if (err != 0) return (err); /* Process Marvell Armada-XP/38x PCIe controllers */ if (ofw_bus_node_is_compatible(child, "marvell,armada-370-pcie")) { child_pci = OF_child(child); while (child_pci != 0) { err = fdt_win_process(child_pci); if (err != 0) return (err); child_pci = OF_peer(child_pci); } } /* * Once done with root-level children let's move down to * simple-bus and its children. */ child = OF_peer(child); if ((child == 0) && (node == OF_finddevice("/"))) { sb = node = fdt_find_compatible(node, "simple-bus", 0); if (node == 0) return (ENXIO); child = OF_child(node); } /* * Next, move one more level down to internal-regs node (if * it is present) and its children. This node also have * "simple-bus" compatible. */ if ((child == 0) && (node == sb)) { node = fdt_find_compatible(node, "simple-bus", 0); if (node == 0) return (0); child = OF_child(node); } } return (0); } static void fdt_fixup_busfreq(phandle_t root) { phandle_t sb; pcell_t freq; freq = cpu_to_fdt32(get_tclk()); /* * Fix bus speed in cpu node */ - if ((sb = OF_finddevice("cpu")) != 0) + if ((sb = OF_finddevice("cpu")) != -1) if (fdt_is_compatible_strict(sb, "ARM,88VS584")) OF_setprop(sb, "bus-frequency", (void *)&freq, sizeof(freq)); /* * This fixup sets the simple-bus bus-frequency property. */ if ((sb = fdt_find_compatible(root, "simple-bus", 1)) != 0) OF_setprop(sb, "bus-frequency", (void *)&freq, sizeof(freq)); } static void fdt_fixup_ranges(phandle_t root) { phandle_t node; pcell_t par_addr_cells, addr_cells, size_cells; pcell_t ranges[3], reg[2], *rangesptr; int len, tuple_size, tuples_count; uint32_t base; /* Fix-up SoC ranges according to real fdt_immr_pa */ if ((node = fdt_find_compatible(root, "simple-bus", 1)) != 0) { if (fdt_addrsize_cells(node, &addr_cells, &size_cells) == 0 && (par_addr_cells = fdt_parent_addr_cells(node) <= 2)) { tuple_size = sizeof(pcell_t) * (par_addr_cells + addr_cells + size_cells); len = OF_getprop(node, "ranges", ranges, sizeof(ranges)); tuples_count = len / tuple_size; /* Unexpected settings are not supported */ if (tuples_count != 1) goto fixup_failed; rangesptr = &ranges[0]; rangesptr += par_addr_cells; base = fdt_data_get((void *)rangesptr, addr_cells); *rangesptr = cpu_to_fdt32(fdt_immr_pa); if (OF_setprop(node, "ranges", (void *)&ranges[0], sizeof(ranges)) < 0) goto fixup_failed; } } /* Fix-up PCIe reg according to real PCIe registers' PA */ if ((node = fdt_find_compatible(root, "mrvl,pcie", 1)) != 0) { if (fdt_addrsize_cells(OF_parent(node), &par_addr_cells, &size_cells) == 0) { tuple_size = sizeof(pcell_t) * (par_addr_cells + size_cells); len = OF_getprop(node, "reg", reg, sizeof(reg)); tuples_count = len / tuple_size; /* Unexpected settings are not supported */ if (tuples_count != 1) goto fixup_failed; base = fdt_data_get((void *)®[0], par_addr_cells); base &= ~0xFF000000; base |= fdt_immr_pa; reg[0] = cpu_to_fdt32(base); if (OF_setprop(node, "reg", (void *)®[0], sizeof(reg)) < 0) goto fixup_failed; } } /* Fix-up succeeded. May return and continue */ return; fixup_failed: while (1) { /* * In case of any error while fixing ranges just hang. * 1. No message can be displayed yet since console * is not initialized. * 2. Going further will cause failure on bus_space_map() * relying on the wrong ranges or data abort when * accessing PCIe registers. */ } } struct fdt_fixup_entry fdt_fixup_table[] = { { "mrvl,DB-88F6281", &fdt_fixup_busfreq }, { "mrvl,DB-78460", &fdt_fixup_busfreq }, { "mrvl,DB-78460", &fdt_fixup_ranges }, { NULL, NULL } }; #ifndef INTRNG static int fdt_pic_decode_ic(phandle_t node, pcell_t *intr, int *interrupt, int *trig, int *pol) { if (!ofw_bus_node_is_compatible(node, "mrvl,pic") && !ofw_bus_node_is_compatible(node, "mrvl,mpic")) return (ENXIO); *interrupt = fdt32_to_cpu(intr[0]); *trig = INTR_TRIGGER_CONFORM; *pol = INTR_POLARITY_CONFORM; return (0); } fdt_pic_decode_t fdt_pic_table[] = { #ifdef SOC_MV_ARMADA38X &gic_decode_fdt, #endif &fdt_pic_decode_ic, NULL }; #endif uint64_t get_sar_value(void) { uint32_t sar_low, sar_high; #if defined(SOC_MV_ARMADAXP) sar_high = bus_space_read_4(fdtbus_bs_tag, MV_MISC_BASE, SAMPLE_AT_RESET_HI); sar_low = bus_space_read_4(fdtbus_bs_tag, MV_MISC_BASE, SAMPLE_AT_RESET_LO); #elif defined(SOC_MV_ARMADA38X) sar_high = 0; sar_low = bus_space_read_4(fdtbus_bs_tag, MV_MISC_BASE, SAMPLE_AT_RESET); #else /* * TODO: Add getting proper values for other SoC configurations */ sar_high = 0; sar_low = 0; #endif return (((uint64_t)sar_high << 32) | sar_low); } Index: head/sys/arm/samsung/exynos/chrome_ec.c =================================================================== --- head/sys/arm/samsung/exynos/chrome_ec.c (revision 331228) +++ head/sys/arm/samsung/exynos/chrome_ec.c (revision 331229) @@ -1,301 +1,301 @@ /*- * Copyright (c) 2014 Ruslan Bukin * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND * ANY EXPREC OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNEC FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINEC INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. */ /* * Samsung Chromebook Embedded Controller */ #include __FBSDID("$FreeBSD$"); #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include "iicbus_if.h" #include "gpio_if.h" #include struct ec_softc { device_t dev; int have_arbitrator; pcell_t our_gpio; pcell_t ec_gpio; }; struct ec_softc *ec_sc; /* * bus_claim, bus_release * both functions used for bus arbitration * in multi-master mode */ static int bus_claim(struct ec_softc *sc) { device_t gpio_dev; int status; if (sc->our_gpio == 0 || sc->ec_gpio == 0) { device_printf(sc->dev, "i2c arbitrator is not configured\n"); return (1); } gpio_dev = devclass_get_device(devclass_find("gpio"), 0); if (gpio_dev == NULL) { device_printf(sc->dev, "cant find gpio_dev\n"); return (1); } /* Say we want the bus */ GPIO_PIN_SET(gpio_dev, sc->our_gpio, GPIO_PIN_LOW); /* TODO: insert a delay to allow EC to react. */ /* Check EC decision */ GPIO_PIN_GET(gpio_dev, sc->ec_gpio, &status); if (status == 1) { /* Okay. We have bus */ return (0); } /* EC is master */ return (-1); } static int bus_release(struct ec_softc *sc) { device_t gpio_dev; if (sc->our_gpio == 0 || sc->ec_gpio == 0) { device_printf(sc->dev, "i2c arbitrator is not configured\n"); return (1); } gpio_dev = devclass_get_device(devclass_find("gpio"), 0); if (gpio_dev == NULL) { device_printf(sc->dev, "cant find gpio_dev\n"); return (1); } GPIO_PIN_SET(gpio_dev, sc->our_gpio, GPIO_PIN_HIGH); return (0); } static int ec_probe(device_t dev) { device_set_desc(dev, "Chromebook Embedded Controller"); return (BUS_PROBE_DEFAULT); } static int fill_checksum(uint8_t *data_out, int len) { int res; int i; res = 0; for (i = 0; i < len; i++) { res += data_out[i]; } data_out[len] = (res & 0xff); return (0); } int ec_command(uint8_t cmd, uint8_t *dout, uint8_t dout_len, uint8_t *dinp, uint8_t dinp_len) { struct ec_softc *sc; uint8_t *msg_dout; uint8_t *msg_dinp; int ret; int i; msg_dout = malloc(dout_len + 4, M_DEVBUF, M_NOWAIT); msg_dinp = malloc(dinp_len + 3, M_DEVBUF, M_NOWAIT); if (ec_sc == NULL) return (-1); sc = ec_sc; msg_dout[0] = EC_CMD_VERSION0; msg_dout[1] = cmd; msg_dout[2] = dout_len; for (i = 0; i < dout_len; i++) { msg_dout[i + 3] = dout[i]; } fill_checksum(msg_dout, dout_len + 3); struct iic_msg msgs[] = { { 0x1e, IIC_M_WR, dout_len + 4, msg_dout, }, { 0x1e, IIC_M_RD, dinp_len + 3, msg_dinp, }, }; ret = iicbus_transfer(sc->dev, msgs, 2); if (ret != 0) { device_printf(sc->dev, "i2c transfer returned %d\n", ret); free(msg_dout, M_DEVBUF); free(msg_dinp, M_DEVBUF); return (-1); } for (i = 0; i < dinp_len; i++) { dinp[i] = msg_dinp[i + 2]; } free(msg_dout, M_DEVBUF); free(msg_dinp, M_DEVBUF); return (0); } int ec_hello(void) { uint8_t data_in[4]; uint8_t data_out[4]; data_in[0] = 0x40; data_in[1] = 0x30; data_in[2] = 0x20; data_in[3] = 0x10; ec_command(EC_CMD_HELLO, data_in, 4, data_out, 4); return (0); } static void configure_i2c_arbitrator(struct ec_softc *sc) { phandle_t arbitrator; /* TODO: look for compatible entry instead of hard-coded path */ arbitrator = OF_finddevice("/i2c-arbitrator"); - if (arbitrator > 0 && + if (arbitrator != -1 && OF_hasprop(arbitrator, "freebsd,our-gpio") && OF_hasprop(arbitrator, "freebsd,ec-gpio")) { sc->have_arbitrator = 1; OF_getencprop(arbitrator, "freebsd,our-gpio", &sc->our_gpio, sizeof(sc->our_gpio)); OF_getencprop(arbitrator, "freebsd,ec-gpio", &sc->ec_gpio, sizeof(sc->ec_gpio)); } else { sc->have_arbitrator = 0; sc->our_gpio = 0; sc->ec_gpio = 0; } } static int ec_attach(device_t dev) { struct ec_softc *sc; sc = device_get_softc(dev); sc->dev = dev; ec_sc = sc; configure_i2c_arbitrator(sc); /* * Claim the bus. * * We don't know cases when EC is master, * so hold the bus forever for us. * */ if (sc->have_arbitrator && bus_claim(sc) != 0) { return (ENXIO); } return (0); } static int ec_detach(device_t dev) { struct ec_softc *sc; sc = device_get_softc(dev); if (sc->have_arbitrator) { bus_release(sc); } return (0); } static device_method_t ec_methods[] = { DEVMETHOD(device_probe, ec_probe), DEVMETHOD(device_attach, ec_attach), DEVMETHOD(device_detach, ec_detach), { 0, 0 } }; static driver_t ec_driver = { "chrome_ec", ec_methods, sizeof(struct ec_softc), }; static devclass_t ec_devclass; DRIVER_MODULE(chrome_ec, iicbus, ec_driver, ec_devclass, 0, 0); MODULE_VERSION(chrome_ec, 1); MODULE_DEPEND(chrome_ec, iicbus, 1, 1, 1); Index: head/sys/arm/samsung/exynos/exynos5_ehci.c =================================================================== --- head/sys/arm/samsung/exynos/exynos5_ehci.c (revision 331228) +++ head/sys/arm/samsung/exynos/exynos5_ehci.c (revision 331229) @@ -1,398 +1,398 @@ /*- * Copyright (c) 2013-2014 Ruslan Bukin * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. */ #ifdef USB_GLOBAL_INCLUDE_FILE #include USB_GLOBAL_INCLUDE_FILE #else #include __FBSDID("$FreeBSD$"); #include "opt_bus.h" #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include "gpio_if.h" #include "opt_platform.h" #endif /* GPIO control */ #define GPIO_OUTPUT 1 #define GPIO_INPUT 0 #define PIN_USB 161 /* SYSREG */ #define EXYNOS5_SYSREG_USB2_PHY 0x0 #define USB2_MODE_HOST 0x1 /* USB HOST */ #define HOST_CTRL_CLK_24MHZ (5 << 16) #define HOST_CTRL_CLK_MASK (7 << 16) #define HOST_CTRL_SIDDQ (1 << 6) #define HOST_CTRL_SLEEP (1 << 5) #define HOST_CTRL_SUSPEND (1 << 4) #define HOST_CTRL_RESET_LINK (1 << 1) #define HOST_CTRL_RESET_PHY (1 << 0) #define HOST_CTRL_RESET_PHY_ALL (1U << 31) /* Forward declarations */ static int exynos_ehci_attach(device_t dev); static int exynos_ehci_detach(device_t dev); static int exynos_ehci_probe(device_t dev); struct exynos_ehci_softc { device_t dev; ehci_softc_t base; struct resource *res[4]; bus_space_tag_t host_bst; bus_space_tag_t sysreg_bst; bus_space_handle_t host_bsh; bus_space_handle_t sysreg_bsh; }; static struct resource_spec exynos_ehci_spec[] = { { SYS_RES_MEMORY, 0, RF_ACTIVE }, { SYS_RES_MEMORY, 1, RF_ACTIVE }, { SYS_RES_MEMORY, 2, RF_ACTIVE }, { SYS_RES_IRQ, 0, RF_ACTIVE }, { -1, 0 } }; static device_method_t ehci_methods[] = { /* Device interface */ DEVMETHOD(device_probe, exynos_ehci_probe), DEVMETHOD(device_attach, exynos_ehci_attach), DEVMETHOD(device_detach, exynos_ehci_detach), DEVMETHOD(device_suspend, bus_generic_suspend), DEVMETHOD(device_resume, bus_generic_resume), DEVMETHOD(device_shutdown, bus_generic_shutdown), /* Bus interface */ DEVMETHOD(bus_print_child, bus_generic_print_child), { 0, 0 } }; /* kobj_class definition */ static driver_t ehci_driver = { "ehci", ehci_methods, sizeof(struct exynos_ehci_softc) }; static devclass_t ehci_devclass; DRIVER_MODULE(ehci, simplebus, ehci_driver, ehci_devclass, 0, 0); MODULE_DEPEND(ehci, usb, 1, 1, 1); /* * Public methods */ static int exynos_ehci_probe(device_t dev) { if (!ofw_bus_status_okay(dev)) return (ENXIO); if (ofw_bus_is_compatible(dev, "exynos,usb-ehci") == 0) return (ENXIO); device_set_desc(dev, "Exynos integrated USB controller"); return (BUS_PROBE_DEFAULT); } static int gpio_ctrl(struct exynos_ehci_softc *esc, int dir, int power) { device_t gpio_dev; /* Get the GPIO device, we need this to give power to USB */ gpio_dev = devclass_get_device(devclass_find("gpio"), 0); if (gpio_dev == NULL) { device_printf(esc->dev, "cant find gpio_dev\n"); return (1); } if (power) GPIO_PIN_SET(gpio_dev, PIN_USB, GPIO_PIN_HIGH); else GPIO_PIN_SET(gpio_dev, PIN_USB, GPIO_PIN_LOW); if (dir) GPIO_PIN_SETFLAGS(gpio_dev, PIN_USB, GPIO_PIN_OUTPUT); else GPIO_PIN_SETFLAGS(gpio_dev, PIN_USB, GPIO_PIN_INPUT); return (0); } static int reset_hsic_hub(struct exynos_ehci_softc *esc, phandle_t hub) { device_t gpio_dev; pcell_t pin; /* TODO: check that hub is compatible with "smsc,usb3503" */ if (!OF_hasprop(hub, "freebsd,reset-gpio")) { return (1); } if (OF_getencprop(hub, "freebsd,reset-gpio", &pin, sizeof(pin)) < 0) { device_printf(esc->dev, "failed to decode reset GPIO pin number for HSIC hub\n"); return (1); } /* Get the GPIO device, we need this to give power to USB */ gpio_dev = devclass_get_device(devclass_find("gpio"), 0); if (gpio_dev == NULL) { device_printf(esc->dev, "Cant find gpio device\n"); return (1); } GPIO_PIN_SET(gpio_dev, pin, GPIO_PIN_LOW); DELAY(100); GPIO_PIN_SET(gpio_dev, pin, GPIO_PIN_HIGH); return (0); } static int phy_init(struct exynos_ehci_softc *esc) { int reg; phandle_t hub; gpio_ctrl(esc, GPIO_INPUT, 1); /* set USB HOST mode */ bus_space_write_4(esc->sysreg_bst, esc->sysreg_bsh, EXYNOS5_SYSREG_USB2_PHY, USB2_MODE_HOST); /* Power ON phy */ usb2_phy_power_on(); reg = bus_space_read_4(esc->host_bst, esc->host_bsh, 0x0); reg &= ~(HOST_CTRL_CLK_MASK | HOST_CTRL_RESET_PHY | HOST_CTRL_RESET_PHY_ALL | HOST_CTRL_SIDDQ | HOST_CTRL_SUSPEND | HOST_CTRL_SLEEP); reg |= (HOST_CTRL_CLK_24MHZ | HOST_CTRL_RESET_LINK); bus_space_write_4(esc->host_bst, esc->host_bsh, 0x0, reg); DELAY(10); reg = bus_space_read_4(esc->host_bst, esc->host_bsh, 0x0); reg &= ~(HOST_CTRL_RESET_LINK); bus_space_write_4(esc->host_bst, esc->host_bsh, 0x0, reg); - if ((hub = OF_finddevice("/hsichub")) != 0) { + if ((hub = OF_finddevice("/hsichub")) != -1) { reset_hsic_hub(esc, hub); } gpio_ctrl(esc, GPIO_OUTPUT, 1); return (0); } static int exynos_ehci_attach(device_t dev) { struct exynos_ehci_softc *esc; ehci_softc_t *sc; bus_space_handle_t bsh; int err; esc = device_get_softc(dev); esc->dev = dev; sc = &esc->base; sc->sc_bus.parent = dev; sc->sc_bus.devices = sc->sc_devices; sc->sc_bus.devices_max = EHCI_MAX_DEVICES; sc->sc_bus.dma_bits = 32; if (bus_alloc_resources(dev, exynos_ehci_spec, esc->res)) { device_printf(dev, "could not allocate resources\n"); return (ENXIO); } /* EHCI registers */ sc->sc_io_tag = rman_get_bustag(esc->res[0]); bsh = rman_get_bushandle(esc->res[0]); sc->sc_io_size = rman_get_size(esc->res[0]); /* EHCI HOST ctrl registers */ esc->host_bst = rman_get_bustag(esc->res[1]); esc->host_bsh = rman_get_bushandle(esc->res[1]); /* SYSREG */ esc->sysreg_bst = rman_get_bustag(esc->res[2]); esc->sysreg_bsh = rman_get_bushandle(esc->res[2]); /* get all DMA memory */ if (usb_bus_mem_alloc_all(&sc->sc_bus, USB_GET_DMA_TAG(dev), &ehci_iterate_hw_softc)) return (ENXIO); /* * Set handle to USB related registers subregion used by * generic EHCI driver. */ err = bus_space_subregion(sc->sc_io_tag, bsh, 0x0, sc->sc_io_size, &sc->sc_io_hdl); if (err != 0) return (ENXIO); phy_init(esc); /* Setup interrupt handler */ err = bus_setup_intr(dev, esc->res[3], INTR_TYPE_BIO | INTR_MPSAFE, NULL, (driver_intr_t *)ehci_interrupt, sc, &sc->sc_intr_hdl); if (err) { device_printf(dev, "Could not setup irq, " "%d\n", err); return (1); } /* Add USB device */ sc->sc_bus.bdev = device_add_child(dev, "usbus", -1); if (!sc->sc_bus.bdev) { device_printf(dev, "Could not add USB device\n"); err = bus_teardown_intr(dev, esc->res[3], sc->sc_intr_hdl); if (err) device_printf(dev, "Could not tear down irq," " %d\n", err); return (1); } device_set_ivars(sc->sc_bus.bdev, &sc->sc_bus); strlcpy(sc->sc_vendor, "Samsung", sizeof(sc->sc_vendor)); err = ehci_init(sc); if (!err) { sc->sc_flags |= EHCI_SCFLG_DONEINIT; err = device_probe_and_attach(sc->sc_bus.bdev); } else { device_printf(dev, "USB init failed err=%d\n", err); device_delete_child(dev, sc->sc_bus.bdev); sc->sc_bus.bdev = NULL; err = bus_teardown_intr(dev, esc->res[3], sc->sc_intr_hdl); if (err) device_printf(dev, "Could not tear down irq," " %d\n", err); return (1); } return (0); } static int exynos_ehci_detach(device_t dev) { struct exynos_ehci_softc *esc; ehci_softc_t *sc; int err; esc = device_get_softc(dev); sc = &esc->base; if (sc->sc_flags & EHCI_SCFLG_DONEINIT) return (0); /* * only call ehci_detach() after ehci_init() */ if (sc->sc_flags & EHCI_SCFLG_DONEINIT) { ehci_detach(sc); sc->sc_flags &= ~EHCI_SCFLG_DONEINIT; } /* * Disable interrupts that might have been switched on in * ehci_init. */ if (sc->sc_io_tag && sc->sc_io_hdl) bus_space_write_4(sc->sc_io_tag, sc->sc_io_hdl, EHCI_USBINTR, 0); if (esc->res[3] && sc->sc_intr_hdl) { err = bus_teardown_intr(dev, esc->res[3], sc->sc_intr_hdl); if (err) { device_printf(dev, "Could not tear down irq," " %d\n", err); return (err); } sc->sc_intr_hdl = NULL; } if (sc->sc_bus.bdev) { device_delete_child(dev, sc->sc_bus.bdev); sc->sc_bus.bdev = NULL; } /* During module unload there are lots of children leftover */ device_delete_children(dev); bus_release_resources(dev, exynos_ehci_spec, esc->res); return (0); } Index: head/sys/arm/ti/am335x/am335x_lcd.c =================================================================== --- head/sys/arm/ti/am335x/am335x_lcd.c (revision 331228) +++ head/sys/arm/ti/am335x/am335x_lcd.c (revision 331229) @@ -1,1082 +1,1082 @@ /*- * SPDX-License-Identifier: BSD-2-Clause-FreeBSD * * Copyright 2013 Oleksandr Tymoshenko * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. */ #include __FBSDID("$FreeBSD$"); #include "opt_syscons.h" #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #ifdef DEV_SC #include #else /* VT */ #include #endif #include #include #include "am335x_lcd.h" #include "am335x_pwm.h" #include "fb_if.h" #include "hdmi_if.h" #define LCD_PID 0x00 #define LCD_CTRL 0x04 #define CTRL_DIV_MASK 0xff #define CTRL_DIV_SHIFT 8 #define CTRL_AUTO_UFLOW_RESTART (1 << 1) #define CTRL_RASTER_MODE 1 #define CTRL_LIDD_MODE 0 #define LCD_LIDD_CTRL 0x0C #define LCD_LIDD_CS0_CONF 0x10 #define LCD_LIDD_CS0_ADDR 0x14 #define LCD_LIDD_CS0_DATA 0x18 #define LCD_LIDD_CS1_CONF 0x1C #define LCD_LIDD_CS1_ADDR 0x20 #define LCD_LIDD_CS1_DATA 0x24 #define LCD_RASTER_CTRL 0x28 #define RASTER_CTRL_TFT24_UNPACKED (1 << 26) #define RASTER_CTRL_TFT24 (1 << 25) #define RASTER_CTRL_STN565 (1 << 24) #define RASTER_CTRL_TFTPMAP (1 << 23) #define RASTER_CTRL_NIBMODE (1 << 22) #define RASTER_CTRL_PALMODE_SHIFT 20 #define PALETTE_PALETTE_AND_DATA 0x00 #define PALETTE_PALETTE_ONLY 0x01 #define PALETTE_DATA_ONLY 0x02 #define RASTER_CTRL_REQDLY_SHIFT 12 #define RASTER_CTRL_MONO8B (1 << 9) #define RASTER_CTRL_RBORDER (1 << 8) #define RASTER_CTRL_LCDTFT (1 << 7) #define RASTER_CTRL_LCDBW (1 << 1) #define RASTER_CTRL_LCDEN (1 << 0) #define LCD_RASTER_TIMING_0 0x2C #define RASTER_TIMING_0_HBP_SHIFT 24 #define RASTER_TIMING_0_HFP_SHIFT 16 #define RASTER_TIMING_0_HSW_SHIFT 10 #define RASTER_TIMING_0_PPLLSB_SHIFT 4 #define RASTER_TIMING_0_PPLMSB_SHIFT 3 #define LCD_RASTER_TIMING_1 0x30 #define RASTER_TIMING_1_VBP_SHIFT 24 #define RASTER_TIMING_1_VFP_SHIFT 16 #define RASTER_TIMING_1_VSW_SHIFT 10 #define RASTER_TIMING_1_LPP_SHIFT 0 #define LCD_RASTER_TIMING_2 0x34 #define RASTER_TIMING_2_HSWHI_SHIFT 27 #define RASTER_TIMING_2_LPP_B10_SHIFT 26 #define RASTER_TIMING_2_PHSVS (1 << 25) #define RASTER_TIMING_2_PHSVS_RISE (1 << 24) #define RASTER_TIMING_2_PHSVS_FALL (0 << 24) #define RASTER_TIMING_2_IOE (1 << 23) #define RASTER_TIMING_2_IPC (1 << 22) #define RASTER_TIMING_2_IHS (1 << 21) #define RASTER_TIMING_2_IVS (1 << 20) #define RASTER_TIMING_2_ACBI_SHIFT 16 #define RASTER_TIMING_2_ACB_SHIFT 8 #define RASTER_TIMING_2_HBPHI_SHIFT 4 #define RASTER_TIMING_2_HFPHI_SHIFT 0 #define LCD_RASTER_SUBPANEL 0x38 #define LCD_RASTER_SUBPANEL2 0x3C #define LCD_LCDDMA_CTRL 0x40 #define LCDDMA_CTRL_DMA_MASTER_PRIO_SHIFT 16 #define LCDDMA_CTRL_TH_FIFO_RDY_SHIFT 8 #define LCDDMA_CTRL_BURST_SIZE_SHIFT 4 #define LCDDMA_CTRL_BYTES_SWAP (1 << 3) #define LCDDMA_CTRL_BE (1 << 1) #define LCDDMA_CTRL_FB0_ONLY 0 #define LCDDMA_CTRL_FB0_FB1 (1 << 0) #define LCD_LCDDMA_FB0_BASE 0x44 #define LCD_LCDDMA_FB0_CEILING 0x48 #define LCD_LCDDMA_FB1_BASE 0x4C #define LCD_LCDDMA_FB1_CEILING 0x50 #define LCD_SYSCONFIG 0x54 #define SYSCONFIG_STANDBY_FORCE (0 << 4) #define SYSCONFIG_STANDBY_NONE (1 << 4) #define SYSCONFIG_STANDBY_SMART (2 << 4) #define SYSCONFIG_IDLE_FORCE (0 << 2) #define SYSCONFIG_IDLE_NONE (1 << 2) #define SYSCONFIG_IDLE_SMART (2 << 2) #define LCD_IRQSTATUS_RAW 0x58 #define LCD_IRQSTATUS 0x5C #define LCD_IRQENABLE_SET 0x60 #define LCD_IRQENABLE_CLEAR 0x64 #define IRQ_EOF1 (1 << 9) #define IRQ_EOF0 (1 << 8) #define IRQ_PL (1 << 6) #define IRQ_FUF (1 << 5) #define IRQ_ACB (1 << 3) #define IRQ_SYNC_LOST (1 << 2) #define IRQ_RASTER_DONE (1 << 1) #define IRQ_FRAME_DONE (1 << 0) #define LCD_END_OF_INT_IND 0x68 #define LCD_CLKC_ENABLE 0x6C #define CLKC_ENABLE_DMA (1 << 2) #define CLKC_ENABLE_LDID (1 << 1) #define CLKC_ENABLE_CORE (1 << 0) #define LCD_CLKC_RESET 0x70 #define CLKC_RESET_MAIN (1 << 3) #define CLKC_RESET_DMA (1 << 2) #define CLKC_RESET_LDID (1 << 1) #define CLKC_RESET_CORE (1 << 0) #define LCD_LOCK(_sc) mtx_lock(&(_sc)->sc_mtx) #define LCD_UNLOCK(_sc) mtx_unlock(&(_sc)->sc_mtx) #define LCD_LOCK_INIT(_sc) mtx_init(&(_sc)->sc_mtx, \ device_get_nameunit(_sc->sc_dev), "am335x_lcd", MTX_DEF) #define LCD_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->sc_mtx); #define LCD_READ4(_sc, reg) bus_read_4((_sc)->sc_mem_res, reg); #define LCD_WRITE4(_sc, reg, value) \ bus_write_4((_sc)->sc_mem_res, reg, value); /* Backlight is controlled by eCAS interface on PWM unit 0 */ #define PWM_UNIT 0 #define PWM_PERIOD 100 #define MODE_HBP(mode) ((mode)->htotal - (mode)->hsync_end) #define MODE_HFP(mode) ((mode)->hsync_start - (mode)->hdisplay) #define MODE_HSW(mode) ((mode)->hsync_end - (mode)->hsync_start) #define MODE_VBP(mode) ((mode)->vtotal - (mode)->vsync_end) #define MODE_VFP(mode) ((mode)->vsync_start - (mode)->vdisplay) #define MODE_VSW(mode) ((mode)->vsync_end - (mode)->vsync_start) #define MAX_PIXEL_CLOCK 126000 #define MAX_BANDWIDTH (1280*1024*60) struct am335x_lcd_softc { device_t sc_dev; struct fb_info sc_fb_info; struct resource *sc_mem_res; struct resource *sc_irq_res; void *sc_intr_hl; struct mtx sc_mtx; int sc_backlight; struct sysctl_oid *sc_oid; struct panel_info sc_panel; /* Framebuffer */ bus_dma_tag_t sc_dma_tag; bus_dmamap_t sc_dma_map; size_t sc_fb_size; bus_addr_t sc_fb_phys; uint8_t *sc_fb_base; /* HDMI framer */ phandle_t sc_hdmi_framer; eventhandler_tag sc_hdmi_evh; }; static void am335x_fb_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nseg, int err) { bus_addr_t *addr; if (err) return; addr = (bus_addr_t*)arg; *addr = segs[0].ds_addr; } static uint32_t am335x_lcd_calc_divisor(uint32_t reference, uint32_t freq) { uint32_t div, i; uint32_t delta, min_delta; min_delta = freq; div = 255; /* Raster mode case: divisors are in range from 2 to 255 */ for (i = 2; i < 255; i++) { delta = abs(reference/i - freq); if (delta < min_delta) { div = i; min_delta = delta; } } return (div); } static int am335x_lcd_sysctl_backlight(SYSCTL_HANDLER_ARGS) { struct am335x_lcd_softc *sc = (struct am335x_lcd_softc*)arg1; int error; int backlight; backlight = sc->sc_backlight; error = sysctl_handle_int(oidp, &backlight, 0, req); if (error != 0 || req->newptr == NULL) return (error); if (backlight < 0) backlight = 0; if (backlight > 100) backlight = 100; LCD_LOCK(sc); error = am335x_pwm_config_ecap(PWM_UNIT, PWM_PERIOD, backlight*PWM_PERIOD/100); if (error == 0) sc->sc_backlight = backlight; LCD_UNLOCK(sc); return (error); } static uint32_t am335x_mode_vrefresh(const struct videomode *mode) { uint32_t refresh; /* Calculate vertical refresh rate */ refresh = (mode->dot_clock * 1000 / mode->htotal); refresh = (refresh + mode->vtotal / 2) / mode->vtotal; if (mode->flags & VID_INTERLACE) refresh *= 2; if (mode->flags & VID_DBLSCAN) refresh /= 2; return refresh; } static int am335x_mode_is_valid(const struct videomode *mode) { uint32_t hbp, hfp, hsw; uint32_t vbp, vfp, vsw; if (mode->dot_clock > MAX_PIXEL_CLOCK) return (0); if (mode->hdisplay & 0xf) return (0); if (mode->vdisplay > 2048) return (0); /* Check ranges for timing parameters */ hbp = MODE_HBP(mode) - 1; hfp = MODE_HFP(mode) - 1; hsw = MODE_HSW(mode) - 1; vbp = MODE_VBP(mode); vfp = MODE_VFP(mode); vsw = MODE_VSW(mode) - 1; if (hbp > 0x3ff) return (0); if (hfp > 0x3ff) return (0); if (hsw > 0x3ff) return (0); if (vbp > 0xff) return (0); if (vfp > 0xff) return (0); if (vsw > 0x3f) return (0); if (mode->vdisplay*mode->hdisplay*am335x_mode_vrefresh(mode) > MAX_BANDWIDTH) return (0); return (1); } static void am335x_read_hdmi_property(device_t dev) { phandle_t node, xref; phandle_t endpoint; phandle_t hdmi_xref; struct am335x_lcd_softc *sc; sc = device_get_softc(dev); node = ofw_bus_get_node(dev); sc->sc_hdmi_framer = 0; /* * Old FreeBSD way of referencing to HDMI framer */ if (OF_getencprop(node, "hdmi", &hdmi_xref, sizeof(hdmi_xref)) != -1) { sc->sc_hdmi_framer = hdmi_xref; return; } /* * Use bindings described in Linux docs: * bindings/media/video-interfaces.txt * We assume that the only endpoint in LCDC node * is HDMI framer. */ node = ofw_bus_find_child(node, "port"); /* No media bindings */ if (node == 0) return; for (endpoint = OF_child(node); endpoint != 0; endpoint = OF_peer(endpoint)) { if (OF_getencprop(endpoint, "remote-endpoint", &xref, sizeof(xref)) != -1) { /* port/port@0/endpoint@0 */ node = OF_node_from_xref(xref); /* port/port@0 */ node = OF_parent(node); /* port */ node = OF_parent(node); /* actual owner of port, in our case HDMI framer */ sc->sc_hdmi_framer = OF_xref_from_node(OF_parent(node)); if (sc->sc_hdmi_framer != 0) return; } } } static int am335x_read_property(device_t dev, phandle_t node, const char *name, uint32_t *val) { pcell_t cell; if ((OF_getencprop(node, name, &cell, sizeof(cell))) <= 0) { device_printf(dev, "missing '%s' attribute in LCD panel info\n", name); return (ENXIO); } *val = cell; return (0); } static int am335x_read_timing(device_t dev, phandle_t node, struct panel_info *panel) { int error; phandle_t timings_node, timing_node, native; timings_node = ofw_bus_find_child(node, "display-timings"); if (timings_node == 0) { device_printf(dev, "no \"display-timings\" node\n"); return (-1); } if (OF_searchencprop(timings_node, "native-mode", &native, sizeof(native)) == -1) { device_printf(dev, "no \"native-mode\" reference in \"timings\" node\n"); return (-1); } timing_node = OF_node_from_xref(native); error = 0; if ((error = am335x_read_property(dev, timing_node, "hactive", &panel->panel_width))) goto out; if ((error = am335x_read_property(dev, timing_node, "vactive", &panel->panel_height))) goto out; if ((error = am335x_read_property(dev, timing_node, "hfront-porch", &panel->panel_hfp))) goto out; if ((error = am335x_read_property(dev, timing_node, "hback-porch", &panel->panel_hbp))) goto out; if ((error = am335x_read_property(dev, timing_node, "hsync-len", &panel->panel_hsw))) goto out; if ((error = am335x_read_property(dev, timing_node, "vfront-porch", &panel->panel_vfp))) goto out; if ((error = am335x_read_property(dev, timing_node, "vback-porch", &panel->panel_vbp))) goto out; if ((error = am335x_read_property(dev, timing_node, "vsync-len", &panel->panel_vsw))) goto out; if ((error = am335x_read_property(dev, timing_node, "clock-frequency", &panel->panel_pxl_clk))) goto out; if ((error = am335x_read_property(dev, timing_node, "pixelclk-active", &panel->pixelclk_active))) goto out; if ((error = am335x_read_property(dev, timing_node, "hsync-active", &panel->hsync_active))) goto out; if ((error = am335x_read_property(dev, timing_node, "vsync-active", &panel->vsync_active))) goto out; out: return (error); } static int am335x_read_panel_info(device_t dev, phandle_t node, struct panel_info *panel) { phandle_t panel_info_node; panel_info_node = ofw_bus_find_child(node, "panel-info"); if (panel_info_node == 0) return (-1); am335x_read_property(dev, panel_info_node, "ac-bias", &panel->ac_bias); am335x_read_property(dev, panel_info_node, "ac-bias-intrpt", &panel->ac_bias_intrpt); am335x_read_property(dev, panel_info_node, "dma-burst-sz", &panel->dma_burst_sz); am335x_read_property(dev, panel_info_node, "bpp", &panel->bpp); am335x_read_property(dev, panel_info_node, "fdd", &panel->fdd); am335x_read_property(dev, panel_info_node, "sync-edge", &panel->sync_edge); am335x_read_property(dev, panel_info_node, "sync-ctrl", &panel->sync_ctrl); return (0); } static void am335x_lcd_intr(void *arg) { struct am335x_lcd_softc *sc = arg; uint32_t reg; reg = LCD_READ4(sc, LCD_IRQSTATUS); LCD_WRITE4(sc, LCD_IRQSTATUS, reg); /* Read value back to make sure it reached the hardware */ reg = LCD_READ4(sc, LCD_IRQSTATUS); if (reg & IRQ_SYNC_LOST) { reg = LCD_READ4(sc, LCD_RASTER_CTRL); reg &= ~RASTER_CTRL_LCDEN; LCD_WRITE4(sc, LCD_RASTER_CTRL, reg); reg = LCD_READ4(sc, LCD_RASTER_CTRL); reg |= RASTER_CTRL_LCDEN; LCD_WRITE4(sc, LCD_RASTER_CTRL, reg); goto done; } if (reg & IRQ_PL) { reg = LCD_READ4(sc, LCD_RASTER_CTRL); reg &= ~RASTER_CTRL_LCDEN; LCD_WRITE4(sc, LCD_RASTER_CTRL, reg); reg = LCD_READ4(sc, LCD_RASTER_CTRL); reg |= RASTER_CTRL_LCDEN; LCD_WRITE4(sc, LCD_RASTER_CTRL, reg); goto done; } if (reg & IRQ_EOF0) { LCD_WRITE4(sc, LCD_LCDDMA_FB0_BASE, sc->sc_fb_phys); LCD_WRITE4(sc, LCD_LCDDMA_FB0_CEILING, sc->sc_fb_phys + sc->sc_fb_size - 1); reg &= ~IRQ_EOF0; } if (reg & IRQ_EOF1) { LCD_WRITE4(sc, LCD_LCDDMA_FB1_BASE, sc->sc_fb_phys); LCD_WRITE4(sc, LCD_LCDDMA_FB1_CEILING, sc->sc_fb_phys + sc->sc_fb_size - 1); reg &= ~IRQ_EOF1; } if (reg & IRQ_FUF) { /* TODO: Handle FUF */ } if (reg & IRQ_ACB) { /* TODO: Handle ACB */ } done: LCD_WRITE4(sc, LCD_END_OF_INT_IND, 0); /* Read value back to make sure it reached the hardware */ reg = LCD_READ4(sc, LCD_END_OF_INT_IND); } static const struct videomode * am335x_lcd_pick_mode(struct edid_info *ei) { const struct videomode *videomode; const struct videomode *m; int n; /* Get standard VGA as default */ videomode = NULL; /* * Pick a mode. */ if (ei->edid_preferred_mode != NULL) { if (am335x_mode_is_valid(ei->edid_preferred_mode)) videomode = ei->edid_preferred_mode; } if (videomode == NULL) { m = ei->edid_modes; sort_modes(ei->edid_modes, &ei->edid_preferred_mode, ei->edid_nmodes); for (n = 0; n < ei->edid_nmodes; n++) if (am335x_mode_is_valid(&m[n])) { videomode = &m[n]; break; } } return videomode; } static int am335x_lcd_configure(struct am335x_lcd_softc *sc) { int div; uint32_t reg, timing0, timing1, timing2; uint32_t burst_log; size_t dma_size; uint32_t hbp, hfp, hsw; uint32_t vbp, vfp, vsw; uint32_t width, height; unsigned int ref_freq; int err; /* * try to adjust clock to get double of requested frequency * HDMI/DVI displays are very sensitive to error in frequncy value */ if (ti_prcm_clk_set_source_freq(LCDC_CLK, sc->sc_panel.panel_pxl_clk*2)) { device_printf(sc->sc_dev, "can't set source frequency\n"); return (ENXIO); } if (ti_prcm_clk_get_source_freq(LCDC_CLK, &ref_freq)) { device_printf(sc->sc_dev, "can't get reference frequency\n"); return (ENXIO); } /* Panle initialization */ dma_size = round_page(sc->sc_panel.panel_width*sc->sc_panel.panel_height*sc->sc_panel.bpp/8); /* * Now allocate framebuffer memory */ err = bus_dma_tag_create( bus_get_dma_tag(sc->sc_dev), 4, 0, /* alignment, boundary */ BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ BUS_SPACE_MAXADDR, /* highaddr */ NULL, NULL, /* filter, filterarg */ dma_size, 1, /* maxsize, nsegments */ dma_size, 0, /* maxsegsize, flags */ NULL, NULL, /* lockfunc, lockarg */ &sc->sc_dma_tag); if (err) goto done; err = bus_dmamem_alloc(sc->sc_dma_tag, (void **)&sc->sc_fb_base, BUS_DMA_COHERENT, &sc->sc_dma_map); if (err) { device_printf(sc->sc_dev, "cannot allocate framebuffer\n"); goto done; } err = bus_dmamap_load(sc->sc_dma_tag, sc->sc_dma_map, sc->sc_fb_base, dma_size, am335x_fb_dmamap_cb, &sc->sc_fb_phys, BUS_DMA_NOWAIT); if (err) { device_printf(sc->sc_dev, "cannot load DMA map\n"); goto done; } /* Make sure it's blank */ memset(sc->sc_fb_base, 0x0, dma_size); /* Calculate actual FB Size */ sc->sc_fb_size = sc->sc_panel.panel_width*sc->sc_panel.panel_height*sc->sc_panel.bpp/8; /* Only raster mode is supported */ reg = CTRL_RASTER_MODE; div = am335x_lcd_calc_divisor(ref_freq, sc->sc_panel.panel_pxl_clk); reg |= (div << CTRL_DIV_SHIFT); LCD_WRITE4(sc, LCD_CTRL, reg); /* Set timing */ timing0 = timing1 = timing2 = 0; hbp = sc->sc_panel.panel_hbp - 1; hfp = sc->sc_panel.panel_hfp - 1; hsw = sc->sc_panel.panel_hsw - 1; vbp = sc->sc_panel.panel_vbp; vfp = sc->sc_panel.panel_vfp; vsw = sc->sc_panel.panel_vsw - 1; height = sc->sc_panel.panel_height - 1; width = sc->sc_panel.panel_width - 1; /* Horizontal back porch */ timing0 |= (hbp & 0xff) << RASTER_TIMING_0_HBP_SHIFT; timing2 |= ((hbp >> 8) & 3) << RASTER_TIMING_2_HBPHI_SHIFT; /* Horizontal front porch */ timing0 |= (hfp & 0xff) << RASTER_TIMING_0_HFP_SHIFT; timing2 |= ((hfp >> 8) & 3) << RASTER_TIMING_2_HFPHI_SHIFT; /* Horizontal sync width */ timing0 |= (hsw & 0x3f) << RASTER_TIMING_0_HSW_SHIFT; timing2 |= ((hsw >> 6) & 0xf) << RASTER_TIMING_2_HSWHI_SHIFT; /* Vertical back porch, front porch, sync width */ timing1 |= (vbp & 0xff) << RASTER_TIMING_1_VBP_SHIFT; timing1 |= (vfp & 0xff) << RASTER_TIMING_1_VFP_SHIFT; timing1 |= (vsw & 0x3f) << RASTER_TIMING_1_VSW_SHIFT; /* Pixels per line */ timing0 |= ((width >> 10) & 1) << RASTER_TIMING_0_PPLMSB_SHIFT; timing0 |= ((width >> 4) & 0x3f) << RASTER_TIMING_0_PPLLSB_SHIFT; /* Lines per panel */ timing1 |= (height & 0x3ff) << RASTER_TIMING_1_LPP_SHIFT; timing2 |= ((height >> 10 ) & 1) << RASTER_TIMING_2_LPP_B10_SHIFT; /* clock signal settings */ if (sc->sc_panel.sync_ctrl) timing2 |= RASTER_TIMING_2_PHSVS; if (sc->sc_panel.sync_edge) timing2 |= RASTER_TIMING_2_PHSVS_RISE; else timing2 |= RASTER_TIMING_2_PHSVS_FALL; if (sc->sc_panel.hsync_active == 0) timing2 |= RASTER_TIMING_2_IHS; if (sc->sc_panel.vsync_active == 0) timing2 |= RASTER_TIMING_2_IVS; if (sc->sc_panel.pixelclk_active == 0) timing2 |= RASTER_TIMING_2_IPC; /* AC bias */ timing2 |= (sc->sc_panel.ac_bias << RASTER_TIMING_2_ACB_SHIFT); timing2 |= (sc->sc_panel.ac_bias_intrpt << RASTER_TIMING_2_ACBI_SHIFT); LCD_WRITE4(sc, LCD_RASTER_TIMING_0, timing0); LCD_WRITE4(sc, LCD_RASTER_TIMING_1, timing1); LCD_WRITE4(sc, LCD_RASTER_TIMING_2, timing2); /* DMA settings */ reg = LCDDMA_CTRL_FB0_FB1; /* Find power of 2 for current burst size */ switch (sc->sc_panel.dma_burst_sz) { case 1: burst_log = 0; break; case 2: burst_log = 1; break; case 4: burst_log = 2; break; case 8: burst_log = 3; break; case 16: default: burst_log = 4; break; } reg |= (burst_log << LCDDMA_CTRL_BURST_SIZE_SHIFT); /* XXX: FIFO TH */ reg |= (0 << LCDDMA_CTRL_TH_FIFO_RDY_SHIFT); LCD_WRITE4(sc, LCD_LCDDMA_CTRL, reg); LCD_WRITE4(sc, LCD_LCDDMA_FB0_BASE, sc->sc_fb_phys); LCD_WRITE4(sc, LCD_LCDDMA_FB0_CEILING, sc->sc_fb_phys + sc->sc_fb_size - 1); LCD_WRITE4(sc, LCD_LCDDMA_FB1_BASE, sc->sc_fb_phys); LCD_WRITE4(sc, LCD_LCDDMA_FB1_CEILING, sc->sc_fb_phys + sc->sc_fb_size - 1); /* Enable LCD */ reg = RASTER_CTRL_LCDTFT; reg |= (sc->sc_panel.fdd << RASTER_CTRL_REQDLY_SHIFT); reg |= (PALETTE_DATA_ONLY << RASTER_CTRL_PALMODE_SHIFT); if (sc->sc_panel.bpp >= 24) reg |= RASTER_CTRL_TFT24; if (sc->sc_panel.bpp == 32) reg |= RASTER_CTRL_TFT24_UNPACKED; LCD_WRITE4(sc, LCD_RASTER_CTRL, reg); LCD_WRITE4(sc, LCD_CLKC_ENABLE, CLKC_ENABLE_DMA | CLKC_ENABLE_LDID | CLKC_ENABLE_CORE); LCD_WRITE4(sc, LCD_CLKC_RESET, CLKC_RESET_MAIN); DELAY(100); LCD_WRITE4(sc, LCD_CLKC_RESET, 0); reg = IRQ_EOF1 | IRQ_EOF0 | IRQ_FUF | IRQ_PL | IRQ_ACB | IRQ_SYNC_LOST | IRQ_RASTER_DONE | IRQ_FRAME_DONE; LCD_WRITE4(sc, LCD_IRQENABLE_SET, reg); reg = LCD_READ4(sc, LCD_RASTER_CTRL); reg |= RASTER_CTRL_LCDEN; LCD_WRITE4(sc, LCD_RASTER_CTRL, reg); LCD_WRITE4(sc, LCD_SYSCONFIG, SYSCONFIG_STANDBY_SMART | SYSCONFIG_IDLE_SMART); sc->sc_fb_info.fb_name = device_get_nameunit(sc->sc_dev); sc->sc_fb_info.fb_vbase = (intptr_t)sc->sc_fb_base; sc->sc_fb_info.fb_pbase = sc->sc_fb_phys; sc->sc_fb_info.fb_size = sc->sc_fb_size; sc->sc_fb_info.fb_bpp = sc->sc_fb_info.fb_depth = sc->sc_panel.bpp; sc->sc_fb_info.fb_stride = sc->sc_panel.panel_width*sc->sc_panel.bpp / 8; sc->sc_fb_info.fb_width = sc->sc_panel.panel_width; sc->sc_fb_info.fb_height = sc->sc_panel.panel_height; #ifdef DEV_SC err = (sc_attach_unit(device_get_unit(sc->sc_dev), device_get_flags(sc->sc_dev) | SC_AUTODETECT_KBD)); if (err) { device_printf(sc->sc_dev, "failed to attach syscons\n"); goto fail; } am335x_lcd_syscons_setup((vm_offset_t)sc->sc_fb_base, sc->sc_fb_phys, &panel); #else /* VT */ device_t fbd = device_add_child(sc->sc_dev, "fbd", device_get_unit(sc->sc_dev)); if (fbd != NULL) { if (device_probe_and_attach(fbd) != 0) device_printf(sc->sc_dev, "failed to attach fbd device\n"); } else device_printf(sc->sc_dev, "failed to add fbd child\n"); #endif done: return (err); } static void am335x_lcd_hdmi_event(void *arg, device_t hdmi, int event) { struct am335x_lcd_softc *sc; const struct videomode *videomode; struct videomode hdmi_mode; device_t hdmi_dev; uint8_t *edid; uint32_t edid_len; struct edid_info ei; sc = arg; /* Nothing to work with */ if (!sc->sc_hdmi_framer) { device_printf(sc->sc_dev, "HDMI event without HDMI framer set\n"); return; } hdmi_dev = OF_device_from_xref(sc->sc_hdmi_framer); if (!hdmi_dev) { device_printf(sc->sc_dev, "no actual device for \"hdmi\" property\n"); return; } edid = NULL; edid_len = 0; if (HDMI_GET_EDID(hdmi_dev, &edid, &edid_len) != 0) { device_printf(sc->sc_dev, "failed to get EDID info from HDMI framer\n"); return; } videomode = NULL; if (edid_parse(edid, &ei) == 0) { edid_print(&ei); videomode = am335x_lcd_pick_mode(&ei); } else device_printf(sc->sc_dev, "failed to parse EDID\n"); /* Use standard VGA as fallback */ if (videomode == NULL) videomode = pick_mode_by_ref(640, 480, 60); if (videomode == NULL) { device_printf(sc->sc_dev, "failed to find usable videomode"); return; } device_printf(sc->sc_dev, "detected videomode: %dx%d @ %dKHz\n", videomode->hdisplay, videomode->vdisplay, am335x_mode_vrefresh(videomode)); sc->sc_panel.panel_width = videomode->hdisplay; sc->sc_panel.panel_height = videomode->vdisplay; sc->sc_panel.panel_hfp = videomode->hsync_start - videomode->hdisplay; sc->sc_panel.panel_hbp = videomode->htotal - videomode->hsync_end; sc->sc_panel.panel_hsw = videomode->hsync_end - videomode->hsync_start; sc->sc_panel.panel_vfp = videomode->vsync_start - videomode->vdisplay; sc->sc_panel.panel_vbp = videomode->vtotal - videomode->vsync_end; sc->sc_panel.panel_vsw = videomode->vsync_end - videomode->vsync_start; sc->sc_panel.pixelclk_active = 1; /* logic for HSYNC should be reversed */ if (videomode->flags & VID_NHSYNC) sc->sc_panel.hsync_active = 1; else sc->sc_panel.hsync_active = 0; if (videomode->flags & VID_NVSYNC) sc->sc_panel.vsync_active = 0; else sc->sc_panel.vsync_active = 1; sc->sc_panel.panel_pxl_clk = videomode->dot_clock * 1000; am335x_lcd_configure(sc); memcpy(&hdmi_mode, videomode, sizeof(hdmi_mode)); hdmi_mode.hskew = videomode->hsync_end - videomode->hsync_start; hdmi_mode.flags |= VID_HSKEW; HDMI_SET_VIDEOMODE(hdmi_dev, &hdmi_mode); } static int am335x_lcd_probe(device_t dev) { #ifdef DEV_SC int err; #endif if (!ofw_bus_status_okay(dev)) return (ENXIO); if (!ofw_bus_is_compatible(dev, "ti,am33xx-tilcdc")) return (ENXIO); device_set_desc(dev, "AM335x LCD controller"); #ifdef DEV_SC err = sc_probe_unit(device_get_unit(dev), device_get_flags(dev) | SC_AUTODETECT_KBD); if (err != 0) return (err); #endif return (BUS_PROBE_DEFAULT); } static int am335x_lcd_attach(device_t dev) { struct am335x_lcd_softc *sc; int err; int rid; struct sysctl_ctx_list *ctx; struct sysctl_oid *tree; phandle_t root, panel_node; err = 0; sc = device_get_softc(dev); sc->sc_dev = dev; am335x_read_hdmi_property(dev); root = OF_finddevice("/"); - if (root == 0) { + if (root == -1) { device_printf(dev, "failed to get FDT root node\n"); return (ENXIO); } sc->sc_panel.ac_bias = 255; sc->sc_panel.ac_bias_intrpt = 0; sc->sc_panel.dma_burst_sz = 16; sc->sc_panel.bpp = 16; sc->sc_panel.fdd = 128; sc->sc_panel.sync_edge = 0; sc->sc_panel.sync_ctrl = 1; panel_node = fdt_find_compatible(root, "ti,tilcdc,panel", 1); if (panel_node != 0) { device_printf(dev, "using static panel info\n"); if (am335x_read_panel_info(dev, panel_node, &sc->sc_panel)) { device_printf(dev, "failed to read panel info\n"); return (ENXIO); } if (am335x_read_timing(dev, panel_node, &sc->sc_panel)) { device_printf(dev, "failed to read timings\n"); return (ENXIO); } } ti_prcm_clk_enable(LCDC_CLK); rid = 0; sc->sc_mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, RF_ACTIVE); if (!sc->sc_mem_res) { device_printf(dev, "cannot allocate memory window\n"); return (ENXIO); } rid = 0; sc->sc_irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, RF_ACTIVE); if (!sc->sc_irq_res) { bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->sc_mem_res); device_printf(dev, "cannot allocate interrupt\n"); return (ENXIO); } if (bus_setup_intr(dev, sc->sc_irq_res, INTR_TYPE_MISC | INTR_MPSAFE, NULL, am335x_lcd_intr, sc, &sc->sc_intr_hl) != 0) { bus_release_resource(dev, SYS_RES_IRQ, rid, sc->sc_irq_res); bus_release_resource(dev, SYS_RES_MEMORY, rid, sc->sc_mem_res); device_printf(dev, "Unable to setup the irq handler.\n"); return (ENXIO); } LCD_LOCK_INIT(sc); /* Init backlight interface */ ctx = device_get_sysctl_ctx(sc->sc_dev); tree = device_get_sysctl_tree(sc->sc_dev); sc->sc_oid = SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, "backlight", CTLTYPE_INT | CTLFLAG_RW, sc, 0, am335x_lcd_sysctl_backlight, "I", "LCD backlight"); sc->sc_backlight = 0; /* Check if eCAS interface is available at this point */ if (am335x_pwm_config_ecap(PWM_UNIT, PWM_PERIOD, PWM_PERIOD) == 0) sc->sc_backlight = 100; if (panel_node != 0) am335x_lcd_configure(sc); else sc->sc_hdmi_evh = EVENTHANDLER_REGISTER(hdmi_event, am335x_lcd_hdmi_event, sc, EVENTHANDLER_PRI_ANY); return (0); } static int am335x_lcd_detach(device_t dev) { /* Do not let unload driver */ return (EBUSY); } static struct fb_info * am335x_lcd_fb_getinfo(device_t dev) { struct am335x_lcd_softc *sc; sc = device_get_softc(dev); return (&sc->sc_fb_info); } static device_method_t am335x_lcd_methods[] = { DEVMETHOD(device_probe, am335x_lcd_probe), DEVMETHOD(device_attach, am335x_lcd_attach), DEVMETHOD(device_detach, am335x_lcd_detach), /* Framebuffer service methods */ DEVMETHOD(fb_getinfo, am335x_lcd_fb_getinfo), DEVMETHOD_END }; static driver_t am335x_lcd_driver = { "fb", am335x_lcd_methods, sizeof(struct am335x_lcd_softc), }; static devclass_t am335x_lcd_devclass; DRIVER_MODULE(am335x_lcd, simplebus, am335x_lcd_driver, am335x_lcd_devclass, 0, 0); MODULE_VERSION(am335x_lcd, 1); MODULE_DEPEND(am335x_lcd, simplebus, 1, 1, 1); Index: head/sys/arm/ti/am335x/am335x_lcd_syscons.c =================================================================== --- head/sys/arm/ti/am335x/am335x_lcd_syscons.c (revision 331228) +++ head/sys/arm/ti/am335x/am335x_lcd_syscons.c (revision 331229) @@ -1,791 +1,791 @@ /*- * SPDX-License-Identifier: BSD-2-Clause-FreeBSD * * Copyright (c) 2013 Oleksandr Tymoshenko * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. */ #include __FBSDID("$FreeBSD$"); #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include "am335x_lcd.h" struct video_adapter_softc { /* Videoadpater part */ video_adapter_t va; int console; intptr_t fb_addr; intptr_t fb_paddr; unsigned int fb_size; unsigned int height; unsigned int width; unsigned int depth; unsigned int stride; unsigned int xmargin; unsigned int ymargin; unsigned char *font; int initialized; }; struct argb { uint8_t a; uint8_t r; uint8_t g; uint8_t b; }; static struct argb am335x_syscons_palette[16] = { {0x00, 0x00, 0x00, 0x00}, {0x00, 0x00, 0x00, 0xaa}, {0x00, 0x00, 0xaa, 0x00}, {0x00, 0x00, 0xaa, 0xaa}, {0x00, 0xaa, 0x00, 0x00}, {0x00, 0xaa, 0x00, 0xaa}, {0x00, 0xaa, 0x55, 0x00}, {0x00, 0xaa, 0xaa, 0xaa}, {0x00, 0x55, 0x55, 0x55}, {0x00, 0x55, 0x55, 0xff}, {0x00, 0x55, 0xff, 0x55}, {0x00, 0x55, 0xff, 0xff}, {0x00, 0xff, 0x55, 0x55}, {0x00, 0xff, 0x55, 0xff}, {0x00, 0xff, 0xff, 0x55}, {0x00, 0xff, 0xff, 0xff} }; /* mouse pointer from dev/syscons/scgfbrndr.c */ static u_char mouse_pointer[16] = { 0x00, 0x40, 0x60, 0x70, 0x78, 0x7c, 0x7e, 0x68, 0x0c, 0x0c, 0x06, 0x06, 0x00, 0x00, 0x00, 0x00 }; #define AM335X_FONT_HEIGHT 16 #define FB_WIDTH 640 #define FB_HEIGHT 480 #define FB_DEPTH 24 static struct video_adapter_softc va_softc; static int am335x_syscons_configure(int flags); /* * Video driver routines and glue. */ static vi_probe_t am335x_syscons_probe; static vi_init_t am335x_syscons_init; static vi_get_info_t am335x_syscons_get_info; static vi_query_mode_t am335x_syscons_query_mode; static vi_set_mode_t am335x_syscons_set_mode; static vi_save_font_t am335x_syscons_save_font; static vi_load_font_t am335x_syscons_load_font; static vi_show_font_t am335x_syscons_show_font; static vi_save_palette_t am335x_syscons_save_palette; static vi_load_palette_t am335x_syscons_load_palette; static vi_set_border_t am335x_syscons_set_border; static vi_save_state_t am335x_syscons_save_state; static vi_load_state_t am335x_syscons_load_state; static vi_set_win_org_t am335x_syscons_set_win_org; static vi_read_hw_cursor_t am335x_syscons_read_hw_cursor; static vi_set_hw_cursor_t am335x_syscons_set_hw_cursor; static vi_set_hw_cursor_shape_t am335x_syscons_set_hw_cursor_shape; static vi_blank_display_t am335x_syscons_blank_display; static vi_mmap_t am335x_syscons_mmap; static vi_ioctl_t am335x_syscons_ioctl; static vi_clear_t am335x_syscons_clear; static vi_fill_rect_t am335x_syscons_fill_rect; static vi_bitblt_t am335x_syscons_bitblt; static vi_diag_t am335x_syscons_diag; static vi_save_cursor_palette_t am335x_syscons_save_cursor_palette; static vi_load_cursor_palette_t am335x_syscons_load_cursor_palette; static vi_copy_t am335x_syscons_copy; static vi_putp_t am335x_syscons_putp; static vi_putc_t am335x_syscons_putc; static vi_puts_t am335x_syscons_puts; static vi_putm_t am335x_syscons_putm; static video_switch_t am335x_sysconsvidsw = { .probe = am335x_syscons_probe, .init = am335x_syscons_init, .get_info = am335x_syscons_get_info, .query_mode = am335x_syscons_query_mode, .set_mode = am335x_syscons_set_mode, .save_font = am335x_syscons_save_font, .load_font = am335x_syscons_load_font, .show_font = am335x_syscons_show_font, .save_palette = am335x_syscons_save_palette, .load_palette = am335x_syscons_load_palette, .set_border = am335x_syscons_set_border, .save_state = am335x_syscons_save_state, .load_state = am335x_syscons_load_state, .set_win_org = am335x_syscons_set_win_org, .read_hw_cursor = am335x_syscons_read_hw_cursor, .set_hw_cursor = am335x_syscons_set_hw_cursor, .set_hw_cursor_shape = am335x_syscons_set_hw_cursor_shape, .blank_display = am335x_syscons_blank_display, .mmap = am335x_syscons_mmap, .ioctl = am335x_syscons_ioctl, .clear = am335x_syscons_clear, .fill_rect = am335x_syscons_fill_rect, .bitblt = am335x_syscons_bitblt, .diag = am335x_syscons_diag, .save_cursor_palette = am335x_syscons_save_cursor_palette, .load_cursor_palette = am335x_syscons_load_cursor_palette, .copy = am335x_syscons_copy, .putp = am335x_syscons_putp, .putc = am335x_syscons_putc, .puts = am335x_syscons_puts, .putm = am335x_syscons_putm, }; VIDEO_DRIVER(am335x_syscons, am335x_sysconsvidsw, am335x_syscons_configure); static vr_init_t am335x_rend_init; static vr_clear_t am335x_rend_clear; static vr_draw_border_t am335x_rend_draw_border; static vr_draw_t am335x_rend_draw; static vr_set_cursor_t am335x_rend_set_cursor; static vr_draw_cursor_t am335x_rend_draw_cursor; static vr_blink_cursor_t am335x_rend_blink_cursor; static vr_set_mouse_t am335x_rend_set_mouse; static vr_draw_mouse_t am335x_rend_draw_mouse; /* * We use our own renderer; this is because we must emulate a hardware * cursor. */ static sc_rndr_sw_t am335x_rend = { am335x_rend_init, am335x_rend_clear, am335x_rend_draw_border, am335x_rend_draw, am335x_rend_set_cursor, am335x_rend_draw_cursor, am335x_rend_blink_cursor, am335x_rend_set_mouse, am335x_rend_draw_mouse }; RENDERER(am335x_syscons, 0, am335x_rend, gfb_set); RENDERER_MODULE(am335x_syscons, gfb_set); static void am335x_rend_init(scr_stat* scp) { } static void am335x_rend_clear(scr_stat* scp, int c, int attr) { } static void am335x_rend_draw_border(scr_stat* scp, int color) { } static void am335x_rend_draw(scr_stat* scp, int from, int count, int flip) { video_adapter_t* adp = scp->sc->adp; int i, c, a; if (!flip) { /* Normal printing */ vidd_puts(adp, from, (uint16_t*)sc_vtb_pointer(&scp->vtb, from), count); } else { /* This is for selections and such: invert the color attribute */ for (i = count; i-- > 0; ++from) { c = sc_vtb_getc(&scp->vtb, from); a = sc_vtb_geta(&scp->vtb, from) >> 8; vidd_putc(adp, from, c, (a >> 4) | ((a & 0xf) << 4)); } } } static void am335x_rend_set_cursor(scr_stat* scp, int base, int height, int blink) { } static void am335x_rend_draw_cursor(scr_stat* scp, int off, int blink, int on, int flip) { video_adapter_t* adp = scp->sc->adp; struct video_adapter_softc *sc; int row, col; uint8_t *addr; int i, j, bytes; sc = (struct video_adapter_softc *)adp; if (scp->curs_attr.height <= 0) return; if (sc->fb_addr == 0) return; if (off >= adp->va_info.vi_width * adp->va_info.vi_height) return; /* calculate the coordinates in the video buffer */ row = (off / adp->va_info.vi_width) * adp->va_info.vi_cheight; col = (off % adp->va_info.vi_width) * adp->va_info.vi_cwidth; addr = (uint8_t *)sc->fb_addr + (row + sc->ymargin)*(sc->stride) + (sc->depth/8) * (col + sc->xmargin); bytes = sc->depth/8; /* our cursor consists of simply inverting the char under it */ for (i = 0; i < adp->va_info.vi_cheight; i++) { for (j = 0; j < adp->va_info.vi_cwidth; j++) { switch (sc->depth) { case 32: case 24: addr[bytes*j + 2] ^= 0xff; /* FALLTHROUGH */ case 16: addr[bytes*j + 1] ^= 0xff; addr[bytes*j] ^= 0xff; break; default: break; } } addr += sc->stride; } } static void am335x_rend_blink_cursor(scr_stat* scp, int at, int flip) { } static void am335x_rend_set_mouse(scr_stat* scp) { } static void am335x_rend_draw_mouse(scr_stat* scp, int x, int y, int on) { vidd_putm(scp->sc->adp, x, y, mouse_pointer, 0xffffffff, 16, 8); } static uint16_t am335x_syscons_static_window[ROW*COL]; extern u_char dflt_font_16[]; /* * Update videoadapter settings after changing resolution */ static void am335x_syscons_update_margins(video_adapter_t *adp) { struct video_adapter_softc *sc; video_info_t *vi; sc = (struct video_adapter_softc *)adp; vi = &adp->va_info; sc->xmargin = (sc->width - (vi->vi_width * vi->vi_cwidth)) / 2; sc->ymargin = (sc->height - (vi->vi_height * vi->vi_cheight))/2; } static phandle_t am335x_syscons_find_panel_node(phandle_t start) { phandle_t child; phandle_t result; for (child = OF_child(start); child != 0; child = OF_peer(child)) { if (ofw_bus_node_is_compatible(child, "ti,am335x-lcd")) return (child); if ((result = am335x_syscons_find_panel_node(child))) return (result); } return (0); } static int am335x_syscons_configure(int flags) { struct video_adapter_softc *va_sc; va_sc = &va_softc; phandle_t display, root; pcell_t cell; if (va_sc->initialized) return (0); va_sc->width = 0; va_sc->height = 0; /* * It seems there is no way to let syscons framework know * that framebuffer resolution has changed. So just try * to fetch data from FDT and go with defaults if failed */ root = OF_finddevice("/"); - if ((root != 0) && + if ((root != -1) && (display = am335x_syscons_find_panel_node(root))) { if ((OF_getencprop(display, "panel_width", &cell, sizeof(cell))) > 0) va_sc->width = cell; if ((OF_getencprop(display, "panel_height", &cell, sizeof(cell))) > 0) va_sc->height = cell; } if (va_sc->width == 0) va_sc->width = FB_WIDTH; if (va_sc->height == 0) va_sc->height = FB_HEIGHT; am335x_syscons_init(0, &va_sc->va, 0); va_sc->initialized = 1; return (0); } static int am335x_syscons_probe(int unit, video_adapter_t **adp, void *arg, int flags) { return (0); } static int am335x_syscons_init(int unit, video_adapter_t *adp, int flags) { struct video_adapter_softc *sc; video_info_t *vi; sc = (struct video_adapter_softc *)adp; vi = &adp->va_info; vid_init_struct(adp, "am335x_syscons", -1, unit); sc->font = dflt_font_16; vi->vi_cheight = AM335X_FONT_HEIGHT; vi->vi_cwidth = 8; vi->vi_width = sc->width/8; vi->vi_height = sc->height/vi->vi_cheight; /* * Clamp width/height to syscons maximums */ if (vi->vi_width > COL) vi->vi_width = COL; if (vi->vi_height > ROW) vi->vi_height = ROW; sc->xmargin = (sc->width - (vi->vi_width * vi->vi_cwidth)) / 2; sc->ymargin = (sc->height - (vi->vi_height * vi->vi_cheight))/2; adp->va_window = (vm_offset_t) am335x_syscons_static_window; adp->va_flags |= V_ADP_FONT /* | V_ADP_COLOR | V_ADP_MODECHANGE */; vid_register(&sc->va); return (0); } static int am335x_syscons_get_info(video_adapter_t *adp, int mode, video_info_t *info) { bcopy(&adp->va_info, info, sizeof(*info)); return (0); } static int am335x_syscons_query_mode(video_adapter_t *adp, video_info_t *info) { return (0); } static int am335x_syscons_set_mode(video_adapter_t *adp, int mode) { return (0); } static int am335x_syscons_save_font(video_adapter_t *adp, int page, int size, int width, u_char *data, int c, int count) { return (0); } static int am335x_syscons_load_font(video_adapter_t *adp, int page, int size, int width, u_char *data, int c, int count) { struct video_adapter_softc *sc = (struct video_adapter_softc *)adp; sc->font = data; return (0); } static int am335x_syscons_show_font(video_adapter_t *adp, int page) { return (0); } static int am335x_syscons_save_palette(video_adapter_t *adp, u_char *palette) { return (0); } static int am335x_syscons_load_palette(video_adapter_t *adp, u_char *palette) { return (0); } static int am335x_syscons_set_border(video_adapter_t *adp, int border) { return (am335x_syscons_blank_display(adp, border)); } static int am335x_syscons_save_state(video_adapter_t *adp, void *p, size_t size) { return (0); } static int am335x_syscons_load_state(video_adapter_t *adp, void *p) { return (0); } static int am335x_syscons_set_win_org(video_adapter_t *adp, off_t offset) { return (0); } static int am335x_syscons_read_hw_cursor(video_adapter_t *adp, int *col, int *row) { *col = *row = 0; return (0); } static int am335x_syscons_set_hw_cursor(video_adapter_t *adp, int col, int row) { return (0); } static int am335x_syscons_set_hw_cursor_shape(video_adapter_t *adp, int base, int height, int celsize, int blink) { return (0); } static int am335x_syscons_blank_display(video_adapter_t *adp, int mode) { struct video_adapter_softc *sc; sc = (struct video_adapter_softc *)adp; if (sc && sc->fb_addr) memset((void*)sc->fb_addr, 0, sc->fb_size); return (0); } static int am335x_syscons_mmap(video_adapter_t *adp, vm_ooffset_t offset, vm_paddr_t *paddr, int prot, vm_memattr_t *memattr) { struct video_adapter_softc *sc; sc = (struct video_adapter_softc *)adp; /* * This might be a legacy VGA mem request: if so, just point it at the * framebuffer, since it shouldn't be touched */ if (offset < sc->stride*sc->height) { *paddr = sc->fb_paddr + offset; return (0); } return (EINVAL); } static int am335x_syscons_ioctl(video_adapter_t *adp, u_long cmd, caddr_t data) { struct video_adapter_softc *sc; struct fbtype *fb; sc = (struct video_adapter_softc *)adp; switch (cmd) { case FBIOGTYPE: fb = (struct fbtype *)data; fb->fb_type = FBTYPE_PCIMISC; fb->fb_height = sc->height; fb->fb_width = sc->width; fb->fb_depth = sc->depth; if (sc->depth <= 1 || sc->depth > 8) fb->fb_cmsize = 0; else fb->fb_cmsize = 1 << sc->depth; fb->fb_size = sc->fb_size; break; default: return (fb_commonioctl(adp, cmd, data)); } return (0); } static int am335x_syscons_clear(video_adapter_t *adp) { return (am335x_syscons_blank_display(adp, 0)); } static int am335x_syscons_fill_rect(video_adapter_t *adp, int val, int x, int y, int cx, int cy) { return (0); } static int am335x_syscons_bitblt(video_adapter_t *adp, ...) { return (0); } static int am335x_syscons_diag(video_adapter_t *adp, int level) { return (0); } static int am335x_syscons_save_cursor_palette(video_adapter_t *adp, u_char *palette) { return (0); } static int am335x_syscons_load_cursor_palette(video_adapter_t *adp, u_char *palette) { return (0); } static int am335x_syscons_copy(video_adapter_t *adp, vm_offset_t src, vm_offset_t dst, int n) { return (0); } static int am335x_syscons_putp(video_adapter_t *adp, vm_offset_t off, uint32_t p, uint32_t a, int size, int bpp, int bit_ltor, int byte_ltor) { return (0); } static int am335x_syscons_putc(video_adapter_t *adp, vm_offset_t off, uint8_t c, uint8_t a) { struct video_adapter_softc *sc; int row; int col; int i, j, k; uint8_t *addr; u_char *p; uint8_t fg, bg, color; uint16_t rgb; sc = (struct video_adapter_softc *)adp; if (sc->fb_addr == 0) return (0); row = (off / adp->va_info.vi_width) * adp->va_info.vi_cheight; col = (off % adp->va_info.vi_width) * adp->va_info.vi_cwidth; p = sc->font + c*AM335X_FONT_HEIGHT; addr = (uint8_t *)sc->fb_addr + (row + sc->ymargin)*(sc->stride) + (sc->depth/8) * (col + sc->xmargin); fg = a & 0xf ; bg = (a >> 4) & 0xf; for (i = 0; i < AM335X_FONT_HEIGHT; i++) { for (j = 0, k = 7; j < 8; j++, k--) { if ((p[i] & (1 << k)) == 0) color = bg; else color = fg; switch (sc->depth) { case 32: addr[4*j+0] = am335x_syscons_palette[color].r; addr[4*j+1] = am335x_syscons_palette[color].g; addr[4*j+2] = am335x_syscons_palette[color].b; addr[4*j+3] = am335x_syscons_palette[color].a; break; case 24: addr[3*j] = am335x_syscons_palette[color].r; addr[3*j+1] = am335x_syscons_palette[color].g; addr[3*j+2] = am335x_syscons_palette[color].b; break; case 16: rgb = (am335x_syscons_palette[color].r >> 3) << 11; rgb |= (am335x_syscons_palette[color].g >> 2) << 5; rgb |= (am335x_syscons_palette[color].b >> 3); addr[2*j] = rgb & 0xff; addr[2*j + 1] = (rgb >> 8) & 0xff; default: /* Not supported yet */ break; } } addr += (sc->stride); } return (0); } static int am335x_syscons_puts(video_adapter_t *adp, vm_offset_t off, u_int16_t *s, int len) { int i; for (i = 0; i < len; i++) am335x_syscons_putc(adp, off + i, s[i] & 0xff, (s[i] & 0xff00) >> 8); return (0); } static int am335x_syscons_putm(video_adapter_t *adp, int x, int y, uint8_t *pixel_image, uint32_t pixel_mask, int size, int width) { return (0); } /* Initialization function */ int am335x_lcd_syscons_setup(vm_offset_t vaddr, vm_paddr_t paddr, struct panel_info *panel) { struct video_adapter_softc *va_sc = &va_softc; va_sc->fb_addr = vaddr; va_sc->fb_paddr = paddr; va_sc->depth = panel->bpp; va_sc->stride = panel->bpp*panel->panel_width/8; va_sc->width = panel->panel_width; va_sc->height = panel->panel_height; va_sc->fb_size = va_sc->width * va_sc->height * va_sc->depth/8; am335x_syscons_update_margins(&va_sc->va); return (0); } /* * Define a stub keyboard driver in case one hasn't been * compiled into the kernel */ #include #include static int dummy_kbd_configure(int flags); keyboard_switch_t am335x_dummysw; static int dummy_kbd_configure(int flags) { return (0); } KEYBOARD_DRIVER(am335x_dummy, am335x_dummysw, dummy_kbd_configure); Index: head/sys/dev/fdt/fdt_common.c =================================================================== --- head/sys/dev/fdt/fdt_common.c (revision 331228) +++ head/sys/dev/fdt/fdt_common.c (revision 331229) @@ -1,737 +1,737 @@ /*- * SPDX-License-Identifier: BSD-2-Clause-FreeBSD * * Copyright (c) 2009-2014 The FreeBSD Foundation * All rights reserved. * * This software was developed by Andrew Turner under sponsorship from * the FreeBSD Foundation. * This software was developed by Semihalf under sponsorship from * the FreeBSD Foundation. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. */ #include __FBSDID("$FreeBSD$"); #include #include #include #include #include #include #include #include #include #include #include #include #include "ofw_bus_if.h" #ifdef DEBUG #define debugf(fmt, args...) do { printf("%s(): ", __func__); \ printf(fmt,##args); } while (0) #else #define debugf(fmt, args...) #endif #define FDT_COMPAT_LEN 255 #define FDT_TYPE_LEN 64 #define FDT_REG_CELLS 4 #define FDT_RANGES_SIZE 48 SYSCTL_NODE(_hw, OID_AUTO, fdt, CTLFLAG_RD, 0, "Flattened Device Tree"); vm_paddr_t fdt_immr_pa; vm_offset_t fdt_immr_va; vm_offset_t fdt_immr_size; struct fdt_ic_list fdt_ic_list_head = SLIST_HEAD_INITIALIZER(fdt_ic_list_head); static int fdt_is_compatible(phandle_t, const char *); static int fdt_get_range_by_busaddr(phandle_t node, u_long addr, u_long *base, u_long *size) { pcell_t ranges[32], *rangesptr; pcell_t addr_cells, size_cells, par_addr_cells; u_long bus_addr, par_bus_addr, pbase, psize; int err, i, len, tuple_size, tuples; if (node == 0) { *base = 0; *size = ULONG_MAX; return (0); } if ((fdt_addrsize_cells(node, &addr_cells, &size_cells)) != 0) return (ENXIO); /* * Process 'ranges' property. */ par_addr_cells = fdt_parent_addr_cells(node); if (par_addr_cells > 2) { return (ERANGE); } len = OF_getproplen(node, "ranges"); if (len < 0) return (-1); if (len > sizeof(ranges)) return (ENOMEM); if (len == 0) { return (fdt_get_range_by_busaddr(OF_parent(node), addr, base, size)); } if (OF_getprop(node, "ranges", ranges, sizeof(ranges)) <= 0) return (EINVAL); tuple_size = addr_cells + par_addr_cells + size_cells; tuples = len / (tuple_size * sizeof(cell_t)); if (par_addr_cells > 2 || addr_cells > 2 || size_cells > 2) return (ERANGE); *base = 0; *size = 0; for (i = 0; i < tuples; i++) { rangesptr = &ranges[i * tuple_size]; bus_addr = fdt_data_get((void *)rangesptr, addr_cells); if (bus_addr != addr) continue; rangesptr += addr_cells; par_bus_addr = fdt_data_get((void *)rangesptr, par_addr_cells); rangesptr += par_addr_cells; err = fdt_get_range_by_busaddr(OF_parent(node), par_bus_addr, &pbase, &psize); if (err > 0) return (err); if (err == 0) *base = pbase; else *base = par_bus_addr; *size = fdt_data_get((void *)rangesptr, size_cells); return (0); } return (EINVAL); } int fdt_get_range(phandle_t node, int range_id, u_long *base, u_long *size) { pcell_t ranges[FDT_RANGES_SIZE], *rangesptr; pcell_t addr_cells, size_cells, par_addr_cells; u_long par_bus_addr, pbase, psize; int err, len; if ((fdt_addrsize_cells(node, &addr_cells, &size_cells)) != 0) return (ENXIO); /* * Process 'ranges' property. */ par_addr_cells = fdt_parent_addr_cells(node); if (par_addr_cells > 2) return (ERANGE); len = OF_getproplen(node, "ranges"); if (len > sizeof(ranges)) return (ENOMEM); if (len == 0) { *base = 0; *size = ULONG_MAX; return (0); } if (!(range_id < len)) return (ERANGE); if (OF_getprop(node, "ranges", ranges, sizeof(ranges)) <= 0) return (EINVAL); if (par_addr_cells > 2 || addr_cells > 2 || size_cells > 2) return (ERANGE); *base = 0; *size = 0; rangesptr = &ranges[range_id]; *base = fdt_data_get((void *)rangesptr, addr_cells); rangesptr += addr_cells; par_bus_addr = fdt_data_get((void *)rangesptr, par_addr_cells); rangesptr += par_addr_cells; err = fdt_get_range_by_busaddr(OF_parent(node), par_bus_addr, &pbase, &psize); if (err == 0) *base += pbase; else *base += par_bus_addr; *size = fdt_data_get((void *)rangesptr, size_cells); return (0); } int fdt_immr_addr(vm_offset_t immr_va) { phandle_t node; u_long base, size; int r; /* * Try to access the SOC node directly i.e. through /aliases/. */ - if ((node = OF_finddevice("soc")) != 0) + if ((node = OF_finddevice("soc")) != -1) if (fdt_is_compatible(node, "simple-bus")) goto moveon; /* * Find the node the long way. */ - if ((node = OF_finddevice("/")) == 0) + if ((node = OF_finddevice("/")) == -1) return (ENXIO); if ((node = fdt_find_compatible(node, "simple-bus", 0)) == 0) return (ENXIO); moveon: if ((r = fdt_get_range(node, 0, &base, &size)) == 0) { fdt_immr_pa = base; fdt_immr_va = immr_va; fdt_immr_size = size; } return (r); } /* * This routine is an early-usage version of the ofw_bus_is_compatible() when * the ofw_bus I/F is not available (like early console routines and similar). * Note the buffer has to be on the stack since malloc() is usually not * available in such cases either. */ static int fdt_is_compatible(phandle_t node, const char *compatstr) { char buf[FDT_COMPAT_LEN]; char *compat; int len, onelen, l, rv; if ((len = OF_getproplen(node, "compatible")) <= 0) return (0); compat = (char *)&buf; bzero(compat, FDT_COMPAT_LEN); if (OF_getprop(node, "compatible", compat, FDT_COMPAT_LEN) < 0) return (0); onelen = strlen(compatstr); rv = 0; while (len > 0) { if (strncasecmp(compat, compatstr, onelen) == 0) { /* Found it. */ rv = 1; break; } /* Slide to the next sub-string. */ l = strlen(compat) + 1; compat += l; len -= l; } return (rv); } int fdt_is_compatible_strict(phandle_t node, const char *compatible) { char compat[FDT_COMPAT_LEN]; if (OF_getproplen(node, "compatible") <= 0) return (0); if (OF_getprop(node, "compatible", compat, FDT_COMPAT_LEN) < 0) return (0); if (strncasecmp(compat, compatible, FDT_COMPAT_LEN) == 0) /* This fits. */ return (1); return (0); } phandle_t fdt_find_compatible(phandle_t start, const char *compat, int strict) { phandle_t child; /* * Traverse all children of 'start' node, and find first with * matching 'compatible' property. */ for (child = OF_child(start); child != 0; child = OF_peer(child)) if (fdt_is_compatible(child, compat)) { if (strict) if (!fdt_is_compatible_strict(child, compat)) continue; return (child); } return (0); } phandle_t fdt_depth_search_compatible(phandle_t start, const char *compat, int strict) { phandle_t child, node; /* * Depth-search all descendants of 'start' node, and find first with * matching 'compatible' property. */ for (node = OF_child(start); node != 0; node = OF_peer(node)) { if (fdt_is_compatible(node, compat) && (strict == 0 || fdt_is_compatible_strict(node, compat))) { return (node); } child = fdt_depth_search_compatible(node, compat, strict); if (child != 0) return (child); } return (0); } int fdt_is_enabled(phandle_t node) { char *stat; int ena, len; len = OF_getprop_alloc(node, "status", sizeof(char), (void **)&stat); if (len <= 0) /* It is OK if no 'status' property. */ return (1); /* Anything other than 'okay' means disabled. */ ena = 0; if (strncmp((char *)stat, "okay", len) == 0) ena = 1; OF_prop_free(stat); return (ena); } int fdt_is_type(phandle_t node, const char *typestr) { char type[FDT_TYPE_LEN]; if (OF_getproplen(node, "device_type") <= 0) return (0); if (OF_getprop(node, "device_type", type, FDT_TYPE_LEN) < 0) return (0); if (strncasecmp(type, typestr, FDT_TYPE_LEN) == 0) /* This fits. */ return (1); return (0); } int fdt_parent_addr_cells(phandle_t node) { pcell_t addr_cells; /* Find out #address-cells of the superior bus. */ if (OF_searchprop(OF_parent(node), "#address-cells", &addr_cells, sizeof(addr_cells)) <= 0) return (2); return ((int)fdt32_to_cpu(addr_cells)); } int fdt_pm_is_enabled(phandle_t node) { int ret; ret = 1; #if defined(SOC_MV_KIRKWOOD) || defined(SOC_MV_DISCOVERY) ret = fdt_pm(node); #endif return (ret); } u_long fdt_data_get(void *data, int cells) { if (cells == 1) return (fdt32_to_cpu(*((uint32_t *)data))); return (fdt64_to_cpu(*((uint64_t *)data))); } int fdt_addrsize_cells(phandle_t node, int *addr_cells, int *size_cells) { pcell_t cell; int cell_size; /* * Retrieve #{address,size}-cells. */ cell_size = sizeof(cell); if (OF_getencprop(node, "#address-cells", &cell, cell_size) < cell_size) cell = 2; *addr_cells = (int)cell; if (OF_getencprop(node, "#size-cells", &cell, cell_size) < cell_size) cell = 1; *size_cells = (int)cell; if (*addr_cells > 3 || *size_cells > 2) return (ERANGE); return (0); } int fdt_data_to_res(pcell_t *data, int addr_cells, int size_cells, u_long *start, u_long *count) { /* Address portion. */ if (addr_cells > 2) return (ERANGE); *start = fdt_data_get((void *)data, addr_cells); data += addr_cells; /* Size portion. */ if (size_cells > 2) return (ERANGE); *count = fdt_data_get((void *)data, size_cells); return (0); } int fdt_regsize(phandle_t node, u_long *base, u_long *size) { pcell_t reg[4]; int addr_cells, len, size_cells; if (fdt_addrsize_cells(OF_parent(node), &addr_cells, &size_cells)) return (ENXIO); if ((sizeof(pcell_t) * (addr_cells + size_cells)) > sizeof(reg)) return (ENOMEM); len = OF_getprop(node, "reg", ®, sizeof(reg)); if (len <= 0) return (EINVAL); *base = fdt_data_get(®[0], addr_cells); *size = fdt_data_get(®[addr_cells], size_cells); return (0); } int fdt_reg_to_rl(phandle_t node, struct resource_list *rl) { u_long end, count, start; pcell_t *reg, *regptr; pcell_t addr_cells, size_cells; int tuple_size, tuples; int i, rv; long busaddr, bussize; if (fdt_addrsize_cells(OF_parent(node), &addr_cells, &size_cells) != 0) return (ENXIO); if (fdt_get_range(OF_parent(node), 0, &busaddr, &bussize)) { busaddr = 0; bussize = 0; } tuple_size = sizeof(pcell_t) * (addr_cells + size_cells); tuples = OF_getprop_alloc(node, "reg", tuple_size, (void **)®); debugf("addr_cells = %d, size_cells = %d\n", addr_cells, size_cells); debugf("tuples = %d, tuple size = %d\n", tuples, tuple_size); if (tuples <= 0) /* No 'reg' property in this node. */ return (0); regptr = reg; for (i = 0; i < tuples; i++) { rv = fdt_data_to_res(reg, addr_cells, size_cells, &start, &count); if (rv != 0) { resource_list_free(rl); goto out; } reg += addr_cells + size_cells; /* Calculate address range relative to base. */ start += busaddr; end = start + count - 1; debugf("reg addr start = %lx, end = %lx, count = %lx\n", start, end, count); resource_list_add(rl, SYS_RES_MEMORY, i, start, end, count); } rv = 0; out: OF_prop_free(regptr); return (rv); } int fdt_get_phyaddr(phandle_t node, device_t dev, int *phy_addr, void **phy_sc) { phandle_t phy_node; pcell_t phy_handle, phy_reg; uint32_t i; device_t parent, child; if (OF_getencprop(node, "phy-handle", (void *)&phy_handle, sizeof(phy_handle)) <= 0) return (ENXIO); phy_node = OF_node_from_xref(phy_handle); if (OF_getencprop(phy_node, "reg", (void *)&phy_reg, sizeof(phy_reg)) <= 0) return (ENXIO); *phy_addr = phy_reg; /* * Search for softc used to communicate with phy. */ /* * Step 1: Search for ancestor of the phy-node with a "phy-handle" * property set. */ phy_node = OF_parent(phy_node); while (phy_node != 0) { if (OF_getprop(phy_node, "phy-handle", (void *)&phy_handle, sizeof(phy_handle)) > 0) break; phy_node = OF_parent(phy_node); } if (phy_node == 0) return (ENXIO); /* * Step 2: For each device with the same parent and name as ours * compare its node with the one found in step 1, ancestor of phy * node (stored in phy_node). */ parent = device_get_parent(dev); i = 0; child = device_find_child(parent, device_get_name(dev), i); while (child != NULL) { if (ofw_bus_get_node(child) == phy_node) break; i++; child = device_find_child(parent, device_get_name(dev), i); } if (child == NULL) return (ENXIO); /* * Use softc of the device found. */ *phy_sc = (void *)device_get_softc(child); return (0); } int fdt_get_reserved_regions(struct mem_region *mr, int *mrcnt) { pcell_t reserve[FDT_REG_CELLS * FDT_MEM_REGIONS]; pcell_t *reservep; phandle_t memory, root; int addr_cells, size_cells; int i, res_len, rv, tuple_size, tuples; root = OF_finddevice("/"); memory = OF_finddevice("/memory"); if (memory == -1) { rv = ENXIO; goto out; } if ((rv = fdt_addrsize_cells(OF_parent(memory), &addr_cells, &size_cells)) != 0) goto out; if (addr_cells > 2) { rv = ERANGE; goto out; } tuple_size = sizeof(pcell_t) * (addr_cells + size_cells); res_len = OF_getproplen(root, "memreserve"); if (res_len <= 0 || res_len > sizeof(reserve)) { rv = ERANGE; goto out; } if (OF_getprop(root, "memreserve", reserve, res_len) <= 0) { rv = ENXIO; goto out; } tuples = res_len / tuple_size; reservep = (pcell_t *)&reserve; for (i = 0; i < tuples; i++) { rv = fdt_data_to_res(reservep, addr_cells, size_cells, (u_long *)&mr[i].mr_start, (u_long *)&mr[i].mr_size); if (rv != 0) goto out; reservep += addr_cells + size_cells; } *mrcnt = i; rv = 0; out: return (rv); } int fdt_get_mem_regions(struct mem_region *mr, int *mrcnt, uint64_t *memsize) { pcell_t reg[FDT_REG_CELLS * FDT_MEM_REGIONS]; pcell_t *regp; phandle_t memory; uint64_t memory_size; int addr_cells, size_cells; int i, reg_len, rv, tuple_size, tuples; memory = OF_finddevice("/memory"); if (memory == -1) { rv = ENXIO; goto out; } if ((rv = fdt_addrsize_cells(OF_parent(memory), &addr_cells, &size_cells)) != 0) goto out; if (addr_cells > 2) { rv = ERANGE; goto out; } tuple_size = sizeof(pcell_t) * (addr_cells + size_cells); reg_len = OF_getproplen(memory, "reg"); if (reg_len <= 0 || reg_len > sizeof(reg)) { rv = ERANGE; goto out; } if (OF_getprop(memory, "reg", reg, reg_len) <= 0) { rv = ENXIO; goto out; } memory_size = 0; tuples = reg_len / tuple_size; regp = (pcell_t *)® for (i = 0; i < tuples; i++) { rv = fdt_data_to_res(regp, addr_cells, size_cells, (u_long *)&mr[i].mr_start, (u_long *)&mr[i].mr_size); if (rv != 0) goto out; regp += addr_cells + size_cells; memory_size += mr[i].mr_size; } if (memory_size == 0) { rv = ERANGE; goto out; } *mrcnt = i; if (memsize != NULL) *memsize = memory_size; rv = 0; out: return (rv); } int fdt_get_unit(device_t dev) { const char * name; name = ofw_bus_get_name(dev); name = strchr(name, '@') + 1; return (strtol(name,NULL,0)); } int fdt_get_chosen_bootargs(char *bootargs, size_t max_size) { phandle_t chosen; chosen = OF_finddevice("/chosen"); if (chosen == -1) return (ENXIO); if (OF_getprop(chosen, "bootargs", bootargs, max_size) == -1) return (ENXIO); return (0); } Index: head/sys/dev/ofw/ofw_subr.c =================================================================== --- head/sys/dev/ofw/ofw_subr.c (revision 331228) +++ head/sys/dev/ofw/ofw_subr.c (revision 331229) @@ -1,244 +1,244 @@ /*- * Copyright (c) 2015 Ian Lepore * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. * * The initial ofw_reg_to_paddr() implementation has been copied from powerpc * ofw_machdep.c OF_decode_addr(). It was added by Marcel Moolenaar, who did not * assert copyright with the addition but still deserves credit for the work. */ #include __FBSDID("$FreeBSD$"); #include #include #include #include #include #include #include #include #include static void get_addr_props(phandle_t node, uint32_t *addrp, uint32_t *sizep, int *pcip) { char type[64]; uint32_t addr, size; int pci, res; res = OF_getencprop(node, "#address-cells", &addr, sizeof(addr)); if (res == -1) addr = 2; res = OF_getencprop(node, "#size-cells", &size, sizeof(size)); if (res == -1) size = 1; pci = 0; if (addr == 3 && size == 2) { res = OF_getprop(node, "device_type", type, sizeof(type)); if (res != -1) { type[sizeof(type) - 1] = '\0'; pci = (strcmp(type, "pci") == 0) ? 1 : 0; } } if (addrp != NULL) *addrp = addr; if (sizep != NULL) *sizep = size; if (pcip != NULL) *pcip = pci; } int ofw_reg_to_paddr(phandle_t dev, int regno, bus_addr_t *paddr, bus_size_t *psize, pcell_t *ppci_hi) { pcell_t cell[32], pci_hi; uint64_t addr, raddr, baddr; uint64_t size, rsize; uint32_t c, nbridge, naddr, nsize; phandle_t bridge, parent; u_int spc, rspc; int pci, pcib, res; /* Sanity checking. */ if (dev == 0) return (EINVAL); bridge = OF_parent(dev); if (bridge == 0) return (EINVAL); if (regno < 0) return (EINVAL); if (paddr == NULL || psize == NULL) return (EINVAL); get_addr_props(bridge, &naddr, &nsize, &pci); res = OF_getencprop(dev, (pci) ? "assigned-addresses" : "reg", cell, sizeof(cell)); if (res == -1) return (ENXIO); if (res % sizeof(cell[0])) return (ENXIO); res /= sizeof(cell[0]); regno *= naddr + nsize; if (regno + naddr + nsize > res) return (EINVAL); pci_hi = pci ? cell[regno] : OFW_PADDR_NOT_PCI; spc = pci_hi & OFW_PCI_PHYS_HI_SPACEMASK; addr = 0; for (c = 0; c < naddr; c++) addr = ((uint64_t)addr << 32) | cell[regno++]; size = 0; for (c = 0; c < nsize; c++) size = ((uint64_t)size << 32) | cell[regno++]; /* * Map the address range in the bridge's decoding window as given * by the "ranges" property. If a node doesn't have such property * or the property is empty, we assume an identity mapping. The * standard says a missing property indicates no possible mapping. * This code is more liberal since the intended use is to get a * console running early, and a printf to warn of malformed data * is probably futile before the console is fully set up. */ parent = OF_parent(bridge); while (parent != 0) { get_addr_props(parent, &nbridge, NULL, &pcib); res = OF_getencprop(bridge, "ranges", cell, sizeof(cell)); if (res < 1) goto next; if (res % sizeof(cell[0])) return (ENXIO); /* Capture pci_hi if we just transitioned onto a PCI bus. */ if (pcib && pci_hi == OFW_PADDR_NOT_PCI) { pci_hi = cell[0]; spc = pci_hi & OFW_PCI_PHYS_HI_SPACEMASK; } res /= sizeof(cell[0]); regno = 0; while (regno < res) { rspc = (pci ? cell[regno] : OFW_PADDR_NOT_PCI) & OFW_PCI_PHYS_HI_SPACEMASK; if (rspc != spc) { regno += naddr + nbridge + nsize; continue; } raddr = 0; for (c = 0; c < naddr; c++) raddr = ((uint64_t)raddr << 32) | cell[regno++]; rspc = (pcib) ? cell[regno] & OFW_PCI_PHYS_HI_SPACEMASK : OFW_PADDR_NOT_PCI; baddr = 0; for (c = 0; c < nbridge; c++) baddr = ((uint64_t)baddr << 32) | cell[regno++]; rsize = 0; for (c = 0; c < nsize; c++) rsize = ((uint64_t)rsize << 32) | cell[regno++]; if (addr < raddr || addr >= raddr + rsize) continue; addr = addr - raddr + baddr; if (rspc != OFW_PADDR_NOT_PCI) spc = rspc; } next: bridge = parent; parent = OF_parent(bridge); get_addr_props(bridge, &naddr, &nsize, &pci); } KASSERT(addr <= BUS_SPACE_MAXADDR, ("Bus sddress is too large: %jx", (uintmax_t)addr)); KASSERT(size <= BUS_SPACE_MAXSIZE, ("Bus size is too large: %jx", (uintmax_t)size)); *paddr = addr; *psize = size; if (ppci_hi != NULL) *ppci_hi = pci_hi; return (0); } /* Parse cmd line args as env - copied from xlp_machdep. */ /* XXX-BZ this should really be centrally provided for all (boot) code. */ static void _parse_bootargs(char *cmdline) { char *n, *v; while ((v = strsep(&cmdline, " \n")) != NULL) { if (*v == '\0') continue; if (*v == '-') { while (*v != '\0') { v++; switch (*v) { case 'a': boothowto |= RB_ASKNAME; break; /* Someone should simulate that ;-) */ case 'C': boothowto |= RB_CDROM; break; case 'd': boothowto |= RB_KDB; break; case 'D': boothowto |= RB_MULTIPLE; break; case 'm': boothowto |= RB_MUTE; break; case 'g': boothowto |= RB_GDB; break; case 'h': boothowto |= RB_SERIAL; break; case 'p': boothowto |= RB_PAUSE; break; case 'r': boothowto |= RB_DFLTROOT; break; case 's': boothowto |= RB_SINGLE; break; case 'v': boothowto |= RB_VERBOSE; break; } } } else { n = strsep(&v, "="); if (v == NULL) kern_setenv(n, "1"); else kern_setenv(n, v); } } } /* * This is intended to be called early on, right after the OF system is * initialized, so pmap may not be up yet. */ int ofw_parse_bootargs(void) { phandle_t chosen; char buf[2048]; /* early stack supposedly big enough */ int err; chosen = OF_finddevice("/chosen"); - if (chosen <= 0) + if (chosen == -1) return (chosen); if ((err = OF_getprop(chosen, "bootargs", buf, sizeof(buf))) != -1) { _parse_bootargs(buf); return (0); } return (err); } Index: head/sys/dev/ofw/openfirmio.c =================================================================== --- head/sys/dev/ofw/openfirmio.c (revision 331228) +++ head/sys/dev/ofw/openfirmio.c (revision 331229) @@ -1,295 +1,295 @@ /* $NetBSD: openfirmio.c,v 1.4 2002/09/06 13:23:19 gehenna Exp $ */ #include __FBSDID("$FreeBSD$"); /*- * SPDX-License-Identifier: BSD-3-Clause * * Copyright (c) 1992, 1993 * The Regents of the University of California. All rights reserved. * * This software was developed by the Computer Systems Engineering group * at Lawrence Berkeley Laboratory under DARPA contract BG 91-66 and * contributed to Berkeley. * * All advertising materials mentioning features or use of this software * must display the following acknowledgement: * This product includes software developed by the University of * California, Lawrence Berkeley Laboratory. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * 3. Neither the name of the University nor the names of its contributors * may be used to endorse or promote products derived from this software * without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. * * @(#)openfirm.c 8.1 (Berkeley) 6/11/93 * */ #include #include #include #include #include #include #include #include #include #include static struct cdev *openfirm_dev; static d_ioctl_t openfirm_ioctl; #define OPENFIRM_MINOR 0 static struct cdevsw openfirm_cdevsw = { .d_version = D_VERSION, .d_flags = D_NEEDGIANT, .d_ioctl = openfirm_ioctl, .d_name = "openfirm", }; static phandle_t lastnode; /* speed hack */ static int openfirm_checkid(phandle_t, phandle_t); static int openfirm_getstr(int, const char *, char **); /* * Verify target ID is valid (exists in the OPENPROM tree), as * listed from node ID sid forward. */ static int openfirm_checkid(phandle_t sid, phandle_t tid) { for (; sid != 0; sid = OF_peer(sid)) if (sid == tid || openfirm_checkid(OF_child(sid), tid)) return (1); return (0); } static int openfirm_getstr(int len, const char *user, char **cpp) { int error; char *cp; /* Reject obvious bogus requests. */ if ((u_int)len > OFIOCMAXNAME) return (ENAMETOOLONG); *cpp = cp = malloc(len + 1, M_TEMP, M_WAITOK); error = copyin(user, cp, len); cp[len] = '\0'; return (error); } int openfirm_ioctl(struct cdev *dev, u_long cmd, caddr_t data, int flags, struct thread *td) { struct ofiocdesc *of; phandle_t node; int len, ok, error; char *name, *value; char newname[32]; if ((flags & FREAD) == 0) return (EBADF); of = (struct ofiocdesc *)data; switch (cmd) { case OFIOCGETOPTNODE: *(phandle_t *) data = OF_finddevice("/options"); return (0); case OFIOCGET: case OFIOCSET: case OFIOCNEXTPROP: case OFIOCFINDDEVICE: case OFIOCGETPROPLEN: node = of->of_nodeid; break; case OFIOCGETNEXT: case OFIOCGETCHILD: node = *(phandle_t *)data; break; default: return (ENOIOCTL); } if (node != 0 && node != lastnode) { /* Not an easy one, we must search for it. */ ok = openfirm_checkid(OF_peer(0), node); if (!ok) return (EINVAL); lastnode = node; } name = value = NULL; error = 0; switch (cmd) { case OFIOCGET: case OFIOCGETPROPLEN: if (node == 0) return (EINVAL); error = openfirm_getstr(of->of_namelen, of->of_name, &name); if (error) break; len = OF_getproplen(node, name); if (cmd == OFIOCGETPROPLEN) { of->of_buflen = len; break; } if (len > of->of_buflen) { error = ENOMEM; break; } of->of_buflen = len; /* -1 means no entry; 0 means no value. */ if (len <= 0) break; value = malloc(len, M_TEMP, M_WAITOK); len = OF_getprop(node, name, (void *)value, len); error = copyout(value, of->of_buf, len); break; case OFIOCSET: /* * Note: Text string values for at least the /options node * have to be null-terminated and the length parameter must * include this terminating null. However, like OF_getprop(), * OF_setprop() will return the actual length of the text * string, i.e. omitting the terminating null. */ if ((flags & FWRITE) == 0) return (EBADF); if (node == 0) return (EINVAL); if ((u_int)of->of_buflen > OFIOCMAXVALUE) return (ENAMETOOLONG); error = openfirm_getstr(of->of_namelen, of->of_name, &name); if (error) break; value = malloc(of->of_buflen, M_TEMP, M_WAITOK); error = copyin(of->of_buf, value, of->of_buflen); if (error) break; len = OF_setprop(node, name, value, of->of_buflen); if (len < 0) error = EINVAL; of->of_buflen = len; break; case OFIOCNEXTPROP: if (node == 0 || of->of_buflen < 0) return (EINVAL); if (of->of_namelen != 0) { error = openfirm_getstr(of->of_namelen, of->of_name, &name); if (error) break; } ok = OF_nextprop(node, name, newname, sizeof(newname)); if (ok == 0) { error = ENOENT; break; } if (ok == -1) { error = EINVAL; break; } len = strlen(newname) + 1; if (len > of->of_buflen) len = of->of_buflen; else of->of_buflen = len; error = copyout(newname, of->of_buf, len); break; case OFIOCGETNEXT: node = OF_peer(node); *(phandle_t *)data = lastnode = node; break; case OFIOCGETCHILD: if (node == 0) return (EINVAL); node = OF_child(node); *(phandle_t *)data = lastnode = node; break; case OFIOCFINDDEVICE: error = openfirm_getstr(of->of_namelen, of->of_name, &name); if (error) break; node = OF_finddevice(name); - if (node == 0 || node == -1) { + if (node == -1) { error = ENOENT; break; } of->of_nodeid = lastnode = node; break; } if (name != NULL) free(name, M_TEMP); if (value != NULL) free(value, M_TEMP); return (error); } static int openfirm_modevent(module_t mod, int type, void *data) { switch(type) { case MOD_LOAD: if (bootverbose) printf("openfirm: \n"); /* * Allow only root access by default; this device may allow * users to peek into firmware passwords, and likely to crash * the machine on some boxen due to firmware quirks. */ openfirm_dev = make_dev(&openfirm_cdevsw, OPENFIRM_MINOR, UID_ROOT, GID_WHEEL, 0600, "openfirm"); return 0; case MOD_UNLOAD: destroy_dev(openfirm_dev); return 0; case MOD_SHUTDOWN: return 0; default: return EOPNOTSUPP; } } DEV_MODULE(openfirm, openfirm_modevent, NULL); Index: head/sys/dev/ow/owc_gpiobus.c =================================================================== --- head/sys/dev/ow/owc_gpiobus.c (revision 331228) +++ head/sys/dev/ow/owc_gpiobus.c (revision 331229) @@ -1,420 +1,420 @@ /*- * Copyright (c) 2015 M. Warner Losh * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. */ #include __FBSDID("$FreeBSD$"); #include "opt_platform.h" #include #include #include #include #include #include #include #include #include #ifdef FDT #include #include #include #endif #include #include "gpiobus_if.h" #include #define OW_PIN 0 #define OWC_GPIOBUS_LOCK(_sc) mtx_lock(&(_sc)->sc_mtx) #define OWC_GPIOBUS_UNLOCK(_sc) mtx_unlock(&(_sc)->sc_mtx) #define OWC_GPIOBUS_LOCK_INIT(_sc) \ mtx_init(&_sc->sc_mtx, device_get_nameunit(_sc->sc_dev), \ "owc_gpiobus", MTX_DEF) #define OWC_GPIOBUS_LOCK_DESTROY(_sc) mtx_destroy(&_sc->sc_mtx); struct owc_gpiobus_softc { device_t sc_dev; device_t sc_busdev; struct mtx sc_mtx; }; static int owc_gpiobus_probe(device_t); static int owc_gpiobus_attach(device_t); static int owc_gpiobus_detach(device_t); #ifdef FDT static void owc_gpiobus_identify(driver_t *driver, device_t bus) { phandle_t w1, root; /* * Find all the 1-wire bus pseudo-nodes that are * at the top level of the FDT. Would be nice to * somehow preserve the node name of these busses, * but there's no good place to put it. The driver's * name is used for the device name, and the 1-wire * bus overwrites the description. */ root = OF_finddevice("/"); - if (root == 0) + if (root == -1) return; for (w1 = OF_child(root); w1 != 0; w1 = OF_peer(w1)) { if (!fdt_is_compatible_strict(w1, "w1-gpio")) continue; if (!OF_hasprop(w1, "gpios")) continue; ofw_gpiobus_add_fdt_child(bus, driver->name, w1); } } #endif static int owc_gpiobus_probe(device_t dev) { #ifdef FDT if (!ofw_bus_status_okay(dev)) return (ENXIO); if (ofw_bus_is_compatible(dev, "w1-gpio")) { device_set_desc(dev, "FDT GPIO attached one-wire bus"); return (BUS_PROBE_DEFAULT); } return (ENXIO); #else device_set_desc(dev, "GPIO attached one-wire bus"); return 0; #endif } static int owc_gpiobus_attach(device_t dev) { struct owc_gpiobus_softc *sc; device_t *kids; int nkid; sc = device_get_softc(dev); sc->sc_dev = dev; sc->sc_busdev = device_get_parent(dev); OWC_GPIOBUS_LOCK_INIT(sc); nkid = 0; if (device_get_children(dev, &kids, &nkid) == 0) free(kids, M_TEMP); if (nkid == 0) device_add_child(dev, "ow", -1); bus_generic_attach(dev); return (0); } static int owc_gpiobus_detach(device_t dev) { struct owc_gpiobus_softc *sc; sc = device_get_softc(dev); OWC_GPIOBUS_LOCK_DESTROY(sc); bus_generic_detach(dev); return (0); } /* * In the diagrams below, R is driven by the resistor pullup, M is driven by the * master, and S is driven by the slave / target. */ /* * These macros let what why we're doing stuff shine in the code * below, and let the how be confined to here. */ #define GETBUS(sc) GPIOBUS_ACQUIRE_BUS((sc)->sc_busdev, \ (sc)->sc_dev, GPIOBUS_WAIT) #define RELBUS(sc) GPIOBUS_RELEASE_BUS((sc)->sc_busdev, \ (sc)->sc_dev) #define OUTPIN(sc) GPIOBUS_PIN_SETFLAGS((sc)->sc_busdev, \ (sc)->sc_dev, OW_PIN, GPIO_PIN_OUTPUT) #define INPIN(sc) GPIOBUS_PIN_SETFLAGS((sc)->sc_busdev, \ (sc)->sc_dev, OW_PIN, GPIO_PIN_INPUT) #define GETPIN(sc, bit) GPIOBUS_PIN_GET((sc)->sc_busdev, \ (sc)->sc_dev, OW_PIN, bit) #define LOW(sc) GPIOBUS_PIN_SET((sc)->sc_busdev, \ (sc)->sc_dev, OW_PIN, GPIO_PIN_LOW) /* * WRITE-ONE (see owll_if.m for timings) From Figure 4-1 AN-937 * * |<---------tSLOT---->|<-tREC->| * High RRRRM | RRRRRRRRRRRR|RRRRRRRRM * M | R | | | M * M| R | | | M * Low MMMMMMM | | | MMMMMM... * |<-tLOW1->| | | * |<------15us--->| | * |<--------60us---->| */ static int owc_gpiobus_write_one(device_t dev, struct ow_timing *t) { struct owc_gpiobus_softc *sc; int error; sc = device_get_softc(dev); error = GETBUS(sc); if (error != 0) return error; critical_enter(); /* Force low */ OUTPIN(sc); LOW(sc); DELAY(t->t_low1); /* Allow resistor to float line high */ INPIN(sc); DELAY(t->t_slot - t->t_low1 + t->t_rec); critical_exit(); RELBUS(sc); return 0; } /* * WRITE-ZERO (see owll_if.m for timings) From Figure 4-2 AN-937 * * |<---------tSLOT------>|<-tREC->| * High RRRRM | | |RRRRRRRM * M | | R M * M| | | |R M * Low MMMMMMMMMMMMMMMMMMMMMR MMMMMM... * |<--15us->| | | * |<------60us--->| | * |<-------tLOW0------>| */ static int owc_gpiobus_write_zero(device_t dev, struct ow_timing *t) { struct owc_gpiobus_softc *sc; int error; sc = device_get_softc(dev); error = GETBUS(sc); if (error != 0) return error; critical_enter(); /* Force low */ OUTPIN(sc); LOW(sc); DELAY(t->t_low0); /* Allow resistor to float line high */ INPIN(sc); DELAY(t->t_slot - t->t_low0 + t->t_rec); critical_exit(); RELBUS(sc); return 0; } /* * READ-DATA (see owll_if.m for timings) From Figure 4-3 AN-937 * * |<---------tSLOT------>|<-tREC->| * High RRRRM | rrrrrrrrrrrrrrrRRRRRRRM * M | r | R M * M| r | |R M * Low MMMMMMMSSSSSSSSSSSSSSR MMMMMM... * |< sample > | * |<------tRDV---->| | * ->| |<-tRELEASE * * r -- allowed to pull high via the resitor when slave writes a 1-bit * */ static int owc_gpiobus_read_data(device_t dev, struct ow_timing *t, int *bit) { struct owc_gpiobus_softc *sc; int error, sample; sbintime_t then, now; sc = device_get_softc(dev); error = GETBUS(sc); if (error != 0) return error; /* Force low for t_lowr microseconds */ then = sbinuptime(); OUTPIN(sc); LOW(sc); DELAY(t->t_lowr); /* * Slave is supposed to hold the line low for t_rdv microseconds for 0 * and immediately float it high for a 1. This is measured from the * master's pushing the line low. */ INPIN(sc); critical_enter(); do { now = sbinuptime(); GETPIN(sc, &sample); } while (sbttous(now - then) < t->t_rdv + 2 && sample == 0); critical_exit(); if (sbttons(now - then) < t->t_rdv * 1000) *bit = 1; else *bit = 0; /* Wait out the rest of t_slot */ do { now = sbinuptime(); } while ((now - then) / SBT_1US < t->t_slot); RELBUS(sc); return 0; } /* * RESET AND PRESENCE PULSE (see owll_if.m for timings) From Figure 4-4 AN-937 * * |<---------tRSTH------------>| * High RRRM | | RRRRRRRS | RRRR RRM * M | |R| |S | R M * M| R | | S |R M * Low MMMMMMMM MMMMMM| | | SSSSSSSSSS MMMMMM * |<----tRSTL--->| | |<-tPDL---->| * | ->| |<-tR | | * || * * Note: for Regular Speed operations, tRSTL + tR should be less than 960us to * avoid interferring with other devices on the bus */ static int owc_gpiobus_reset_and_presence(device_t dev, struct ow_timing *t, int *bit) { struct owc_gpiobus_softc *sc; int error; int buf = -1; sc = device_get_softc(dev); error = GETBUS(sc); if (error != 0) return error; /* * Read the current state of the bus. The steady state of an idle bus is * high. Badly wired buses that are missing the required pull up, or * that have a short circuit to ground cause all kinds of mischief when * we try to read them later. Return EIO and release the bus if the bus * is currently low. */ INPIN(sc); GETPIN(sc, &buf); if (buf == 0) { *bit = -1; RELBUS(sc); return EIO; } critical_enter(); /* Force low */ OUTPIN(sc); LOW(sc); DELAY(t->t_rstl); /* Allow resistor to float line high and then wait for reset pulse */ INPIN(sc); DELAY(t->t_pdh + t->t_pdl / 2); /* Read presence pulse */ GETPIN(sc, &buf); *bit = !!buf; critical_exit(); DELAY(t->t_rsth - (t->t_pdh + t->t_pdl / 2)); /* Timing not critical for this one */ /* * Read the state of the bus after we've waited past the end of the rest * window. It should return to high. If it is low, then we have some * problem and should abort the reset. */ GETPIN(sc, &buf); if (buf == 0) { *bit = -1; RELBUS(sc); return EIO; } RELBUS(sc); return 0; } static devclass_t owc_gpiobus_devclass; static device_method_t owc_gpiobus_methods[] = { /* Device interface */ #ifdef FDT DEVMETHOD(device_identify, owc_gpiobus_identify), #endif DEVMETHOD(device_probe, owc_gpiobus_probe), DEVMETHOD(device_attach, owc_gpiobus_attach), DEVMETHOD(device_detach, owc_gpiobus_detach), DEVMETHOD(owll_write_one, owc_gpiobus_write_one), DEVMETHOD(owll_write_zero, owc_gpiobus_write_zero), DEVMETHOD(owll_read_data, owc_gpiobus_read_data), DEVMETHOD(owll_reset_and_presence, owc_gpiobus_reset_and_presence), { 0, 0 } }; static driver_t owc_gpiobus_driver = { "owc", owc_gpiobus_methods, sizeof(struct owc_gpiobus_softc), }; DRIVER_MODULE(owc_gpiobus_fdt, gpiobus, owc_gpiobus_driver, owc_gpiobus_devclass, 0, 0); MODULE_DEPEND(owc_gpiobus_fdt, ow, 1, 1, 1); Index: head/sys/dev/vnic/thunder_bgx_fdt.c =================================================================== --- head/sys/dev/vnic/thunder_bgx_fdt.c (revision 331228) +++ head/sys/dev/vnic/thunder_bgx_fdt.c (revision 331229) @@ -1,460 +1,460 @@ /*- * Copyright (c) 2015 The FreeBSD Foundation * All rights reserved. * * This software was developed by Semihalf under * the sponsorship of the FreeBSD Foundation. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. */ #include __FBSDID("$FreeBSD$"); #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include "thunder_bgx.h" #include "thunder_bgx_var.h" #define CONN_TYPE_MAXLEN 16 #define CONN_TYPE_OFFSET 2 #define BGX_NODE_NAME "bgx" #define BGX_MAXID 9 /* BGX func. 0, i.e.: reg = <0x8000 0 0 0 0>; DEVFN = 0x80 */ #define BGX_DEVFN_0 0x80 #define FDT_NAME_MAXLEN 31 int bgx_fdt_init_phy(struct bgx *); static void bgx_fdt_get_macaddr(phandle_t phy, uint8_t *hwaddr) { uint8_t addr[ETHER_ADDR_LEN]; if (OF_getprop(phy, "local-mac-address", addr, ETHER_ADDR_LEN) == -1) { /* Missing MAC address should be marked by clearing it */ memset(hwaddr, 0, ETHER_ADDR_LEN); } else memcpy(hwaddr, addr, ETHER_ADDR_LEN); } static boolean_t bgx_fdt_phy_mode_match(struct bgx *bgx, char *qlm_mode, ssize_t size) { const char *type; ssize_t sz; ssize_t offset; switch (bgx->qlm_mode) { case QLM_MODE_SGMII: type = "sgmii"; sz = sizeof("sgmii") - 1; offset = size - sz; break; case QLM_MODE_XAUI_1X4: type = "xaui"; sz = sizeof("xaui") - 1; offset = size - sz; if (offset < 0) return (FALSE); if (strncmp(&qlm_mode[offset], type, sz) == 0) return (TRUE); type = "dxaui"; sz = sizeof("dxaui") - 1; offset = size - sz; break; case QLM_MODE_RXAUI_2X2: type = "raui"; sz = sizeof("raui") - 1; offset = size - sz; break; case QLM_MODE_XFI_4X1: type = "xfi"; sz = sizeof("xfi") - 1; offset = size - sz; break; case QLM_MODE_XLAUI_1X4: type = "xlaui"; sz = sizeof("xlaui") - 1; offset = size - sz; break; case QLM_MODE_10G_KR_4X1: type = "xfi-10g-kr"; sz = sizeof("xfi-10g-kr") - 1; offset = size - sz; break; case QLM_MODE_40G_KR4_1X4: type = "xlaui-40g-kr"; sz = sizeof("xlaui-40g-kr") - 1; offset = size - sz; break; default: return (FALSE); } if (offset < 0) return (FALSE); if (strncmp(&qlm_mode[offset], type, sz) == 0) return (TRUE); return (FALSE); } static boolean_t bgx_fdt_phy_name_match(struct bgx *bgx, char *phy_name, ssize_t size) { const char *type; ssize_t sz; switch (bgx->qlm_mode) { case QLM_MODE_SGMII: type = "sgmii"; sz = sizeof("sgmii") - 1; break; case QLM_MODE_XAUI_1X4: type = "xaui"; sz = sizeof("xaui") - 1; if (sz < size) return (FALSE); if (strncmp(phy_name, type, sz) == 0) return (TRUE); type = "dxaui"; sz = sizeof("dxaui") - 1; break; case QLM_MODE_RXAUI_2X2: type = "raui"; sz = sizeof("raui") - 1; break; case QLM_MODE_XFI_4X1: type = "xfi"; sz = sizeof("xfi") - 1; break; case QLM_MODE_XLAUI_1X4: type = "xlaui"; sz = sizeof("xlaui") - 1; break; case QLM_MODE_10G_KR_4X1: type = "xfi-10g-kr"; sz = sizeof("xfi-10g-kr") - 1; break; case QLM_MODE_40G_KR4_1X4: type = "xlaui-40g-kr"; sz = sizeof("xlaui-40g-kr") - 1; break; default: return (FALSE); } if (sz > size) return (FALSE); if (strncmp(phy_name, type, sz) == 0) return (TRUE); return (FALSE); } static phandle_t bgx_fdt_traverse_nodes(uint8_t unit, phandle_t start, char *name, size_t len) { phandle_t node, ret; uint32_t *reg; size_t buf_size; ssize_t proplen; char *node_name; int err; /* * Traverse all subordinate nodes of 'start' to find BGX instance. * This supports both old (by name) and new (by reg) methods. */ buf_size = sizeof(*node_name) * FDT_NAME_MAXLEN; if (len > buf_size) { /* * This is an erroneous situation since the string * to compare cannot be longer than FDT_NAME_MAXLEN. */ return (0); } node_name = malloc(buf_size, M_BGX, M_WAITOK); for (node = OF_child(start); node != 0; node = OF_peer(node)) { /* Clean-up the buffer */ memset(node_name, 0, buf_size); /* Recurse to children */ if (OF_child(node) != 0) { ret = bgx_fdt_traverse_nodes(unit, node, name, len); if (ret != 0) { free(node_name, M_BGX); return (ret); } } /* * Old way - by name */ proplen = OF_getproplen(node, "name"); if ((proplen <= 0) || (proplen < len)) continue; err = OF_getprop(node, "name", node_name, proplen); if (err <= 0) continue; if (strncmp(node_name, name, len) == 0) { free(node_name, M_BGX); return (node); } /* * New way - by reg */ /* Check if even BGX */ if (strncmp(node_name, BGX_NODE_NAME, sizeof(BGX_NODE_NAME) - 1) != 0) continue; /* Get reg */ err = OF_getencprop_alloc(node, "reg", sizeof(*reg), (void **)®); if (err == -1) { free(reg, M_OFWPROP); continue; } /* Match BGX device function */ if ((BGX_DEVFN_0 + unit) == (reg[0] >> 8)) { free(reg, M_OFWPROP); free(node_name, M_BGX); return (node); } free(reg, M_OFWPROP); } free(node_name, M_BGX); return (0); } /* * Similar functionality to pci_find_pcie_root_port() * but this one works for ThunderX. */ static device_t bgx_find_root_pcib(device_t dev) { devclass_t pci_class; device_t pcib, bus; pci_class = devclass_find("pci"); KASSERT(device_get_devclass(device_get_parent(dev)) == pci_class, ("%s: non-pci device %s", __func__, device_get_nameunit(dev))); /* Walk the bridge hierarchy until we find a non-PCI device */ for (;;) { bus = device_get_parent(dev); KASSERT(bus != NULL, ("%s: null parent of %s", __func__, device_get_nameunit(dev))); if (device_get_devclass(bus) != pci_class) return (NULL); pcib = device_get_parent(bus); KASSERT(pcib != NULL, ("%s: null bridge of %s", __func__, device_get_nameunit(bus))); /* * If the parent of this PCIB is not PCI * then we found our root PCIB. */ if (device_get_devclass(device_get_parent(pcib)) != pci_class) return (pcib); dev = pcib; } } static __inline phandle_t bgx_fdt_find_node(struct bgx *bgx) { device_t root_pcib; phandle_t node; char *bgx_sel; size_t len; KASSERT(bgx->bgx_id <= BGX_MAXID, ("Invalid BGX ID: %d, max: %d", bgx->bgx_id, BGX_MAXID)); len = sizeof(BGX_NODE_NAME) + 1; /* ++<\0> */ /* Allocate memory for BGX node name + "/" character */ bgx_sel = malloc(sizeof(*bgx_sel) * (len + 1), M_BGX, M_ZERO | M_WAITOK); /* Prepare node's name */ snprintf(bgx_sel, len + 1, "/"BGX_NODE_NAME"%d", bgx->bgx_id); /* First try the root node */ node = OF_finddevice(bgx_sel); - if ((int)node > 0) { + if (node != -1) { /* Found relevant node */ goto out; } /* * Clean-up and try to find BGX in DT * starting from the parent PCI bridge node. */ memset(bgx_sel, 0, sizeof(*bgx_sel) * (len + 1)); snprintf(bgx_sel, len, BGX_NODE_NAME"%d", bgx->bgx_id); /* Find PCI bridge that we are connected to */ root_pcib = bgx_find_root_pcib(bgx->dev); if (root_pcib == NULL) { device_printf(bgx->dev, "Unable to find BGX root bridge\n"); node = 0; goto out; } node = ofw_bus_get_node(root_pcib); if ((int)node <= 0) { device_printf(bgx->dev, "No parent FDT node for BGX\n"); goto out; } node = bgx_fdt_traverse_nodes(bgx->bgx_id, node, bgx_sel, len); out: free(bgx_sel, M_BGX); return (node); } int bgx_fdt_init_phy(struct bgx *bgx) { char *node_name; phandle_t node, child; phandle_t phy, mdio; ssize_t len; uint8_t lmac; char qlm_mode[CONN_TYPE_MAXLEN]; node = bgx_fdt_find_node(bgx); if (node == 0) { device_printf(bgx->dev, "Could not find bgx%d node in FDT\n", bgx->bgx_id); return (ENXIO); } lmac = 0; for (child = OF_child(node); child > 0; child = OF_peer(child)) { len = OF_getprop(child, "qlm-mode", qlm_mode, sizeof(qlm_mode)); if (len > 0) { if (!bgx_fdt_phy_mode_match(bgx, qlm_mode, len)) { /* * Connection type not match with BGX mode. */ continue; } } else { len = OF_getprop_alloc(child, "name", 1, (void **)&node_name); if (len <= 0) { continue; } if (!bgx_fdt_phy_name_match(bgx, node_name, len)) { free(node_name, M_OFWPROP); continue; } free(node_name, M_OFWPROP); } /* Acquire PHY address */ if (OF_getencprop(child, "reg", &bgx->lmac[lmac].phyaddr, sizeof(bgx->lmac[lmac].phyaddr)) <= 0) { if (bootverbose) { device_printf(bgx->dev, "Could not retrieve PHY address\n"); } bgx->lmac[lmac].phyaddr = MII_PHY_ANY; } if (OF_getencprop(child, "phy-handle", &phy, sizeof(phy)) <= 0) { if (bootverbose) { device_printf(bgx->dev, "No phy-handle in PHY node. Skipping...\n"); } continue; } phy = OF_instance_to_package(phy); /* * Get PHY interface (MDIO bus) device. * Driver must be already attached. */ mdio = OF_parent(phy); bgx->lmac[lmac].phy_if_dev = OF_device_from_xref(OF_xref_from_node(mdio)); if (bgx->lmac[lmac].phy_if_dev == NULL) { if (bootverbose) { device_printf(bgx->dev, "Could not find interface to PHY\n"); } continue; } /* Get mac address from FDT */ bgx_fdt_get_macaddr(child, bgx->lmac[lmac].mac); bgx->lmac[lmac].lmacid = lmac; lmac++; if (lmac == MAX_LMAC_PER_BGX) break; } if (lmac == 0) { device_printf(bgx->dev, "Could not find matching PHY\n"); return (ENXIO); } return (0); } Index: head/sys/powerpc/cpufreq/mpc85xx_jog.c =================================================================== --- head/sys/powerpc/cpufreq/mpc85xx_jog.c (revision 331228) +++ head/sys/powerpc/cpufreq/mpc85xx_jog.c (revision 331229) @@ -1,343 +1,343 @@ /*- * Copyright (c) 2017 Justin Hibbits * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. */ #include __FBSDID("$FreeBSD$"); #include #include #include #include #include #include #include #include #include #include #include #include "cpufreq_if.h" /* No worries about uint32_t math overflow in here, because the highest * multiplier supported is 4, and the highest speed part is still well below * 2GHz. */ #define GUTS_PORPLLSR (CCSRBAR_VA + 0xe0000) #define GUTS_PMJCR (CCSRBAR_VA + 0xe007c) #define PMJCR_RATIO_M 0x3f #define PMJCR_CORE_MULT(x,y) ((x) << (16 + ((y) * 8))) #define PMJCR_GET_CORE_MULT(x,y) (((x) >> (16 + ((y) * 8))) & 0x3f) #define GUTS_POWMGTCSR (CCSRBAR_VA + 0xe0080) #define POWMGTCSR_JOG 0x00200000 #define POWMGTCSR_INT_MASK 0x00000f00 #define MHZ 1000000 struct mpc85xx_jog_softc { device_t dev; int cpu; int low; int high; int min_freq; }; static struct ofw_compat_data *mpc85xx_jog_devcompat(void); static void mpc85xx_jog_identify(driver_t *driver, device_t parent); static int mpc85xx_jog_probe(device_t dev); static int mpc85xx_jog_attach(device_t dev); static int mpc85xx_jog_settings(device_t dev, struct cf_setting *sets, int *count); static int mpc85xx_jog_set(device_t dev, const struct cf_setting *set); static int mpc85xx_jog_get(device_t dev, struct cf_setting *set); static int mpc85xx_jog_type(device_t dev, int *type); static device_method_t mpc85xx_jog_methods[] = { /* Device interface */ DEVMETHOD(device_identify, mpc85xx_jog_identify), DEVMETHOD(device_probe, mpc85xx_jog_probe), DEVMETHOD(device_attach, mpc85xx_jog_attach), /* cpufreq interface */ DEVMETHOD(cpufreq_drv_set, mpc85xx_jog_set), DEVMETHOD(cpufreq_drv_get, mpc85xx_jog_get), DEVMETHOD(cpufreq_drv_type, mpc85xx_jog_type), DEVMETHOD(cpufreq_drv_settings, mpc85xx_jog_settings), {0, 0} }; static driver_t mpc85xx_jog_driver = { "jog", mpc85xx_jog_methods, sizeof(struct mpc85xx_jog_softc) }; static devclass_t mpc85xx_jog_devclass; DRIVER_MODULE(mpc85xx_jog, cpu, mpc85xx_jog_driver, mpc85xx_jog_devclass, 0, 0); struct mpc85xx_constraints { int threshold; /* Threshold frequency, in MHz, for setting CORE_SPD bit. */ int min_mult; /* Minimum PLL multiplier. */ }; static struct mpc85xx_constraints mpc8536_constraints = { 800, 3 }; static struct mpc85xx_constraints p1022_constraints = { 500, 2 }; static struct ofw_compat_data jog_compat[] = { {"fsl,mpc8536-guts", (uintptr_t)&mpc8536_constraints}, {"fsl,p1022-guts", (uintptr_t)&p1022_constraints}, {NULL, 0} }; static struct ofw_compat_data * mpc85xx_jog_devcompat() { phandle_t node; int i; node = OF_finddevice("/soc"); - if (node <= 0) + if (node == -1) return (NULL); for (i = 0; jog_compat[i].ocd_str != NULL; i++) if (ofw_bus_find_compatible(node, jog_compat[i].ocd_str) > 0) break; if (jog_compat[i].ocd_str == NULL) return (NULL); return (&jog_compat[i]); } static void mpc85xx_jog_identify(driver_t *driver, device_t parent) { struct ofw_compat_data *compat; /* Make sure we're not being doubly invoked. */ if (device_find_child(parent, "mpc85xx_jog", -1) != NULL) return; compat = mpc85xx_jog_devcompat(); if (compat == NULL) return; /* * We attach a child for every CPU since settings need to * be performed on every CPU in the SMP case. */ if (BUS_ADD_CHILD(parent, 10, "jog", -1) == NULL) device_printf(parent, "add jog child failed\n"); } static int mpc85xx_jog_probe(device_t dev) { struct ofw_compat_data *compat; compat = mpc85xx_jog_devcompat(); if (compat == NULL || compat->ocd_str == NULL) return (ENXIO); device_set_desc(dev, "Freescale CPU Jogger"); return (0); } static int mpc85xx_jog_attach(device_t dev) { struct ofw_compat_data *compat; struct mpc85xx_jog_softc *sc; struct mpc85xx_constraints *constraints; phandle_t cpu; uint32_t reg; sc = device_get_softc(dev); sc->dev = dev; compat = mpc85xx_jog_devcompat(); constraints = (struct mpc85xx_constraints *)compat->ocd_data; cpu = ofw_bus_get_node(device_get_parent(dev)); if (cpu <= 0) { device_printf(dev,"No CPU device tree node!\n"); return (ENXIO); } OF_getencprop(cpu, "reg", &sc->cpu, sizeof(sc->cpu)); reg = ccsr_read4(GUTS_PORPLLSR); /* * Assume power-on PLL is the highest PLL config supported on the * board. */ sc->high = PMJCR_GET_CORE_MULT(reg, sc->cpu); sc->min_freq = constraints->threshold; sc->low = constraints->min_mult; cpufreq_register(dev); return (0); } static int mpc85xx_jog_settings(device_t dev, struct cf_setting *sets, int *count) { struct mpc85xx_jog_softc *sc; uint32_t sysclk; int i; sc = device_get_softc(dev); if (sets == NULL || count == NULL) return (EINVAL); if (*count < sc->high - 1) return (E2BIG); sysclk = mpc85xx_get_system_clock(); /* Return a list of valid settings for this driver. */ memset(sets, CPUFREQ_VAL_UNKNOWN, sizeof(*sets) * sc->high); for (i = sc->high; i >= sc->low; --i) { sets[sc->high - i].freq = sysclk * i / MHZ; sets[sc->high - i].dev = dev; sets[sc->high - i].spec[0] = i; } *count = sc->high - sc->low + 1; return (0); } struct jog_rv_args { int cpu; int mult; int slow; volatile int inprogress; }; static void mpc85xx_jog_set_int(void *arg) { struct jog_rv_args *args = arg; uint32_t reg; if (PCPU_GET(cpuid) == args->cpu) { reg = ccsr_read4(GUTS_PMJCR); reg &= ~PMJCR_CORE_MULT(PMJCR_RATIO_M, args->cpu); reg |= PMJCR_CORE_MULT(args->mult, args->cpu); if (args->slow) reg &= ~(1 << (12 + args->cpu)); else reg |= (1 << (12 + args->cpu)); ccsr_write4(GUTS_PMJCR, reg); reg = ccsr_read4(GUTS_POWMGTCSR); reg |= POWMGTCSR_JOG | POWMGTCSR_INT_MASK; ccsr_write4(GUTS_POWMGTCSR, reg); /* Wait for completion */ do { DELAY(100); reg = ccsr_read4(GUTS_POWMGTCSR); } while (reg & POWMGTCSR_JOG); reg = ccsr_read4(GUTS_POWMGTCSR); ccsr_write4(GUTS_POWMGTCSR, reg & ~POWMGTCSR_INT_MASK); ccsr_read4(GUTS_POWMGTCSR); args->inprogress = 0; } else { while (args->inprogress) cpu_spinwait(); } } static int mpc85xx_jog_set(device_t dev, const struct cf_setting *set) { struct mpc85xx_jog_softc *sc; struct jog_rv_args args; if (set == NULL) return (EINVAL); sc = device_get_softc(dev); args.slow = (set->freq <= sc->min_freq); args.mult = set->spec[0]; args.cpu = PCPU_GET(cpuid); args.inprogress = 1; smp_rendezvous(smp_no_rendezvous_barrier, mpc85xx_jog_set_int, smp_no_rendezvous_barrier, &args); return (0); } static int mpc85xx_jog_get(device_t dev, struct cf_setting *set) { struct mpc85xx_jog_softc *sc; uint32_t pmjcr; uint32_t freq; if (set == NULL) return (EINVAL); sc = device_get_softc(dev); memset(set, CPUFREQ_VAL_UNKNOWN, sizeof(*set)); pmjcr = ccsr_read4(GUTS_PORPLLSR); freq = PMJCR_GET_CORE_MULT(pmjcr, sc->cpu); freq *= mpc85xx_get_system_clock(); freq /= MHZ; set->freq = freq; set->dev = dev; return (0); } static int mpc85xx_jog_type(device_t dev, int *type) { if (type == NULL) return (EINVAL); *type = CPUFREQ_TYPE_ABSOLUTE; return (0); } Index: head/sys/powerpc/pseries/platform_chrp.c =================================================================== --- head/sys/powerpc/pseries/platform_chrp.c (revision 331228) +++ head/sys/powerpc/pseries/platform_chrp.c (revision 331229) @@ -1,513 +1,513 @@ /*- * SPDX-License-Identifier: BSD-2-Clause-FreeBSD * * Copyright (c) 2008 Marcel Moolenaar * Copyright (c) 2009 Nathan Whitehorn * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ #include __FBSDID("$FreeBSD$"); #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include "platform_if.h" #ifdef SMP extern void *ap_pcpu; #endif #ifdef __powerpc64__ static uint8_t splpar_vpa[MAXCPU][640] __aligned(128); /* XXX: dpcpu */ #endif static vm_offset_t realmaxaddr = VM_MAX_ADDRESS; static int chrp_probe(platform_t); static int chrp_attach(platform_t); void chrp_mem_regions(platform_t, struct mem_region *phys, int *physsz, struct mem_region *avail, int *availsz); static vm_offset_t chrp_real_maxaddr(platform_t); static u_long chrp_timebase_freq(platform_t, struct cpuref *cpuref); static int chrp_smp_first_cpu(platform_t, struct cpuref *cpuref); static int chrp_smp_next_cpu(platform_t, struct cpuref *cpuref); static int chrp_smp_get_bsp(platform_t, struct cpuref *cpuref); static void chrp_smp_ap_init(platform_t); static int chrp_cpuref_init(void); #ifdef SMP static int chrp_smp_start_cpu(platform_t, struct pcpu *cpu); static struct cpu_group *chrp_smp_topo(platform_t plat); #endif static void chrp_reset(platform_t); #ifdef __powerpc64__ #include "phyp-hvcall.h" static void phyp_cpu_idle(sbintime_t sbt); #endif static struct cpuref platform_cpuref[MAXCPU]; static int platform_cpuref_cnt; static int platform_cpuref_valid; static platform_method_t chrp_methods[] = { PLATFORMMETHOD(platform_probe, chrp_probe), PLATFORMMETHOD(platform_attach, chrp_attach), PLATFORMMETHOD(platform_mem_regions, chrp_mem_regions), PLATFORMMETHOD(platform_real_maxaddr, chrp_real_maxaddr), PLATFORMMETHOD(platform_timebase_freq, chrp_timebase_freq), PLATFORMMETHOD(platform_smp_ap_init, chrp_smp_ap_init), PLATFORMMETHOD(platform_smp_first_cpu, chrp_smp_first_cpu), PLATFORMMETHOD(platform_smp_next_cpu, chrp_smp_next_cpu), PLATFORMMETHOD(platform_smp_get_bsp, chrp_smp_get_bsp), #ifdef SMP PLATFORMMETHOD(platform_smp_start_cpu, chrp_smp_start_cpu), PLATFORMMETHOD(platform_smp_topo, chrp_smp_topo), #endif PLATFORMMETHOD(platform_reset, chrp_reset), { 0, 0 } }; static platform_def_t chrp_platform = { "chrp", chrp_methods, 0 }; PLATFORM_DEF(chrp_platform); static int chrp_probe(platform_t plat) { if (OF_finddevice("/memory") != -1 || OF_finddevice("/memory@0") != -1) return (BUS_PROBE_GENERIC); return (ENXIO); } static int chrp_attach(platform_t plat) { #ifdef __powerpc64__ int i; /* XXX: check for /rtas/ibm,hypertas-functions? */ if (!(mfmsr() & PSL_HV)) { struct mem_region *phys, *avail; int nphys, navail; mem_regions(&phys, &nphys, &avail, &navail); realmaxaddr = phys[0].mr_size; pmap_mmu_install("mmu_phyp", BUS_PROBE_SPECIFIC); cpu_idle_hook = phyp_cpu_idle; /* Set up important VPA fields */ for (i = 0; i < MAXCPU; i++) { bzero(splpar_vpa[i], sizeof(splpar_vpa)); /* First two: VPA size */ splpar_vpa[i][4] = (uint8_t)((sizeof(splpar_vpa[i]) >> 8) & 0xff); splpar_vpa[i][5] = (uint8_t)(sizeof(splpar_vpa[i]) & 0xff); splpar_vpa[i][0xba] = 1; /* Maintain FPRs */ splpar_vpa[i][0xbb] = 1; /* Maintain PMCs */ splpar_vpa[i][0xfc] = 0xff; /* Maintain full SLB */ splpar_vpa[i][0xfd] = 0xff; splpar_vpa[i][0xff] = 1; /* Maintain Altivec */ } mb(); /* Set up hypervisor CPU stuff */ chrp_smp_ap_init(plat); } #endif chrp_cpuref_init(); /* Some systems (e.g. QEMU) need Open Firmware to stand down */ ofw_quiesce(); return (0); } static int parse_drconf_memory(struct mem_region *ofmem, int *msz, struct mem_region *ofavail, int *asz) { phandle_t phandle; vm_offset_t base; int i, idx, len, lasz, lmsz, res; uint32_t flags, lmb_size[2]; uint32_t *dmem; lmsz = *msz; lasz = *asz; phandle = OF_finddevice("/ibm,dynamic-reconfiguration-memory"); if (phandle == -1) /* No drconf node, return. */ return (0); res = OF_getencprop(phandle, "ibm,lmb-size", lmb_size, sizeof(lmb_size)); if (res == -1) return (0); printf("Logical Memory Block size: %d MB\n", lmb_size[1] >> 20); /* Parse the /ibm,dynamic-memory. The first position gives the # of entries. The next two words reflect the address of the memory block. The next four words are the DRC index, reserved, list index and flags. (see PAPR C.6.6.2 ibm,dynamic-reconfiguration-memory) #el Addr DRC-idx res list-idx flags ------------------------------------------------- | 4 | 8 | 4 | 4 | 4 | 4 |.... ------------------------------------------------- */ len = OF_getproplen(phandle, "ibm,dynamic-memory"); if (len > 0) { /* We have to use a variable length array on the stack since we have very limited stack space. */ cell_t arr[len/sizeof(cell_t)]; res = OF_getencprop(phandle, "ibm,dynamic-memory", arr, sizeof(arr)); if (res == -1) return (0); /* Number of elements */ idx = arr[0]; /* First address, in arr[1], arr[2]*/ dmem = &arr[1]; for (i = 0; i < idx; i++) { base = ((uint64_t)dmem[0] << 32) + dmem[1]; dmem += 4; flags = dmem[1]; /* Use region only if available and not reserved. */ if ((flags & 0x8) && !(flags & 0x80)) { ofmem[lmsz].mr_start = base; ofmem[lmsz].mr_size = (vm_size_t)lmb_size[1]; ofavail[lasz].mr_start = base; ofavail[lasz].mr_size = (vm_size_t)lmb_size[1]; lmsz++; lasz++; } dmem += 2; } } *msz = lmsz; *asz = lasz; return (1); } void chrp_mem_regions(platform_t plat, struct mem_region *phys, int *physsz, struct mem_region *avail, int *availsz) { vm_offset_t maxphysaddr; int i; ofw_mem_regions(phys, physsz, avail, availsz); parse_drconf_memory(phys, physsz, avail, availsz); /* * On some firmwares (SLOF), some memory may be marked available that * doesn't actually exist. This manifests as an extension of the last * available segment past the end of physical memory, so truncate that * one. */ maxphysaddr = 0; for (i = 0; i < *physsz; i++) if (phys[i].mr_start + phys[i].mr_size > maxphysaddr) maxphysaddr = phys[i].mr_start + phys[i].mr_size; for (i = 0; i < *availsz; i++) if (avail[i].mr_start + avail[i].mr_size > maxphysaddr) avail[i].mr_size = maxphysaddr - avail[i].mr_start; } static vm_offset_t chrp_real_maxaddr(platform_t plat) { return (realmaxaddr); } static u_long chrp_timebase_freq(platform_t plat, struct cpuref *cpuref) { phandle_t cpus, cpunode; int32_t ticks = -1; int res; char buf[8]; cpus = OF_finddevice("/cpus"); - if (cpus <= 0) + if (cpus == -1) panic("CPU tree not found on Open Firmware\n"); for (cpunode = OF_child(cpus); cpunode != 0; cpunode = OF_peer(cpunode)) { res = OF_getprop(cpunode, "device_type", buf, sizeof(buf)); if (res > 0 && strcmp(buf, "cpu") == 0) break; } if (cpunode <= 0) panic("CPU node not found on Open Firmware\n"); OF_getencprop(cpunode, "timebase-frequency", &ticks, sizeof(ticks)); if (ticks <= 0) panic("Unable to determine timebase frequency!"); return (ticks); } static int chrp_smp_first_cpu(platform_t plat, struct cpuref *cpuref) { if (platform_cpuref_valid == 0) return (EINVAL); cpuref->cr_cpuid = 0; cpuref->cr_hwref = platform_cpuref[0].cr_hwref; return (0); } static int chrp_smp_next_cpu(platform_t plat, struct cpuref *cpuref) { int id; if (platform_cpuref_valid == 0) return (EINVAL); id = cpuref->cr_cpuid + 1; if (id >= platform_cpuref_cnt) return (ENOENT); cpuref->cr_cpuid = platform_cpuref[id].cr_cpuid; cpuref->cr_hwref = platform_cpuref[id].cr_hwref; return (0); } static int chrp_smp_get_bsp(platform_t plat, struct cpuref *cpuref) { cpuref->cr_cpuid = platform_cpuref[0].cr_cpuid; cpuref->cr_hwref = platform_cpuref[0].cr_hwref; return (0); } static int chrp_cpuref_init(void) { phandle_t cpu, dev; char buf[32]; int a, res; cell_t interrupt_servers[32]; uint64_t bsp; if (platform_cpuref_valid) return (0); dev = OF_peer(0); dev = OF_child(dev); while (dev != 0) { res = OF_getprop(dev, "name", buf, sizeof(buf)); if (res > 0 && strcmp(buf, "cpus") == 0) break; dev = OF_peer(dev); } bsp = 0; for (cpu = OF_child(dev); cpu != 0; cpu = OF_peer(cpu)) { res = OF_getprop(cpu, "device_type", buf, sizeof(buf)); if (res > 0 && strcmp(buf, "cpu") == 0) { res = OF_getproplen(cpu, "ibm,ppc-interrupt-server#s"); if (res > 0) { OF_getencprop(cpu, "ibm,ppc-interrupt-server#s", interrupt_servers, res); for (a = 0; a < res/sizeof(cell_t); a++) { platform_cpuref[platform_cpuref_cnt].cr_hwref = interrupt_servers[a]; platform_cpuref[platform_cpuref_cnt].cr_cpuid = platform_cpuref_cnt; platform_cpuref_cnt++; } } } } platform_cpuref_valid = 1; return (0); } #ifdef SMP static int chrp_smp_start_cpu(platform_t plat, struct pcpu *pc) { cell_t start_cpu; int result, err, timeout; if (!rtas_exists()) { printf("RTAS uninitialized: unable to start AP %d\n", pc->pc_cpuid); return (ENXIO); } start_cpu = rtas_token_lookup("start-cpu"); if (start_cpu == -1) { printf("RTAS unknown method: unable to start AP %d\n", pc->pc_cpuid); return (ENXIO); } ap_pcpu = pc; powerpc_sync(); result = rtas_call_method(start_cpu, 3, 1, pc->pc_hwref, EXC_RST, pc, &err); if (result < 0 || err != 0) { printf("RTAS error (%d/%d): unable to start AP %d\n", result, err, pc->pc_cpuid); return (ENXIO); } timeout = 10000; while (!pc->pc_awake && timeout--) DELAY(100); return ((pc->pc_awake) ? 0 : EBUSY); } static struct cpu_group * chrp_smp_topo(platform_t plat) { struct pcpu *pc, *last_pc; int i, ncores, ncpus; ncores = ncpus = 0; last_pc = NULL; for (i = 0; i <= mp_maxid; i++) { pc = pcpu_find(i); if (pc == NULL) continue; if (last_pc == NULL || pc->pc_hwref != last_pc->pc_hwref) ncores++; last_pc = pc; ncpus++; } if (ncpus % ncores != 0) { printf("WARNING: Irregular SMP topology. Performance may be " "suboptimal (%d CPUS, %d cores)\n", ncpus, ncores); return (smp_topo_none()); } /* Don't do anything fancier for non-threaded SMP */ if (ncpus == ncores) return (smp_topo_none()); return (smp_topo_1level(CG_SHARE_L1, ncpus / ncores, CG_FLAG_SMT)); } #endif static void chrp_reset(platform_t platform) { OF_reboot(); } #ifdef __powerpc64__ static void phyp_cpu_idle(sbintime_t sbt) { register_t msr; msr = mfmsr(); mtmsr(msr & ~PSL_EE); if (sched_runnable()) { mtmsr(msr); return; } phyp_hcall(H_CEDE); /* Re-enables interrupts internally */ mtmsr(msr); } static void chrp_smp_ap_init(platform_t platform) { if (!(mfmsr() & PSL_HV)) { /* Register VPA */ phyp_hcall(H_REGISTER_VPA, 1UL, PCPU_GET(hwref), splpar_vpa[PCPU_GET(hwref)]); /* Set interrupt priority */ phyp_hcall(H_CPPR, 0xff); } } #else static void chrp_smp_ap_init(platform_t platform) { } #endif