Index: head/sys/arm/broadcom/bcm2835/bcm2835_intr.c =================================================================== --- head/sys/arm/broadcom/bcm2835/bcm2835_intr.c (revision 330071) +++ head/sys/arm/broadcom/bcm2835/bcm2835_intr.c (revision 330072) @@ -1,448 +1,455 @@ /*- * SPDX-License-Identifier: BSD-2-Clause-FreeBSD * * Copyright (c) 2012 Damjan Marion * All rights reserved. * * Based on OMAP3 INTC code by Ben Gray * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. */ #include __FBSDID("$FreeBSD$"); #include "opt_platform.h" #include #include #include #include #include #include #include #include #include #include #include #include #include #include "pic_if.h" #define INTC_PENDING_BASIC 0x00 #define INTC_PENDING_BANK1 0x04 #define INTC_PENDING_BANK2 0x08 #define INTC_FIQ_CONTROL 0x0C #define INTC_ENABLE_BANK1 0x10 #define INTC_ENABLE_BANK2 0x14 #define INTC_ENABLE_BASIC 0x18 #define INTC_DISABLE_BANK1 0x1C #define INTC_DISABLE_BANK2 0x20 #define INTC_DISABLE_BASIC 0x24 #define INTC_PENDING_BASIC_ARM 0x0000FF #define INTC_PENDING_BASIC_GPU1_PEND 0x000100 #define INTC_PENDING_BASIC_GPU2_PEND 0x000200 #define INTC_PENDING_BASIC_GPU1_7 0x000400 #define INTC_PENDING_BASIC_GPU1_9 0x000800 #define INTC_PENDING_BASIC_GPU1_10 0x001000 #define INTC_PENDING_BASIC_GPU1_18 0x002000 #define INTC_PENDING_BASIC_GPU1_19 0x004000 #define INTC_PENDING_BASIC_GPU2_21 0x008000 #define INTC_PENDING_BASIC_GPU2_22 0x010000 #define INTC_PENDING_BASIC_GPU2_23 0x020000 #define INTC_PENDING_BASIC_GPU2_24 0x040000 #define INTC_PENDING_BASIC_GPU2_25 0x080000 #define INTC_PENDING_BASIC_GPU2_30 0x100000 #define INTC_PENDING_BASIC_MASK 0x1FFFFF #define INTC_PENDING_BASIC_GPU1_MASK (INTC_PENDING_BASIC_GPU1_7 | \ INTC_PENDING_BASIC_GPU1_9 | \ INTC_PENDING_BASIC_GPU1_10 | \ INTC_PENDING_BASIC_GPU1_18 | \ INTC_PENDING_BASIC_GPU1_19) #define INTC_PENDING_BASIC_GPU2_MASK (INTC_PENDING_BASIC_GPU2_21 | \ INTC_PENDING_BASIC_GPU2_22 | \ INTC_PENDING_BASIC_GPU2_23 | \ INTC_PENDING_BASIC_GPU2_24 | \ INTC_PENDING_BASIC_GPU2_25 | \ INTC_PENDING_BASIC_GPU2_30) #define INTC_PENDING_BANK1_MASK (~((1 << 7) | (1 << 9) | (1 << 10) | \ (1 << 18) | (1 << 19))) #define INTC_PENDING_BANK2_MASK (~((1 << 21) | (1 << 22) | (1 << 23) | \ (1 << 24) | (1 << 25) | (1 << 30))) #define BANK1_START 8 #define BANK1_END (BANK1_START + 32 - 1) #define BANK2_START (BANK1_START + 32) #define BANK2_END (BANK2_START + 32 - 1) #define IS_IRQ_BASIC(n) (((n) >= 0) && ((n) < BANK1_START)) #define IS_IRQ_BANK1(n) (((n) >= BANK1_START) && ((n) <= BANK1_END)) #define IS_IRQ_BANK2(n) (((n) >= BANK2_START) && ((n) <= BANK2_END)) #define IRQ_BANK1(n) ((n) - BANK1_START) #define IRQ_BANK2(n) ((n) - BANK2_START) #ifdef DEBUG #define dprintf(fmt, args...) printf(fmt, ##args) #else #define dprintf(fmt, args...) #endif #define BCM_INTC_NIRQS 72 /* 8 + 32 + 32 */ struct bcm_intc_irqsrc { struct intr_irqsrc bii_isrc; u_int bii_irq; uint16_t bii_disable_reg; uint16_t bii_enable_reg; uint32_t bii_mask; }; struct bcm_intc_softc { device_t sc_dev; struct resource * intc_res; bus_space_tag_t intc_bst; bus_space_handle_t intc_bsh; struct resource * intc_irq_res; void * intc_irq_hdl; struct bcm_intc_irqsrc intc_isrcs[BCM_INTC_NIRQS]; }; +static struct ofw_compat_data compat_data[] = { + {"broadcom,bcm2835-armctrl-ic", 1}, + {"brcm,bcm2835-armctrl-ic", 1}, + {"brcm,bcm2836-armctrl-ic", 1}, + {NULL, 0} +}; + static struct bcm_intc_softc *bcm_intc_sc = NULL; #define intc_read_4(_sc, reg) \ bus_space_read_4((_sc)->intc_bst, (_sc)->intc_bsh, (reg)) #define intc_write_4(_sc, reg, val) \ bus_space_write_4((_sc)->intc_bst, (_sc)->intc_bsh, (reg), (val)) static inline void bcm_intc_isrc_mask(struct bcm_intc_softc *sc, struct bcm_intc_irqsrc *bii) { intc_write_4(sc, bii->bii_disable_reg, bii->bii_mask); } static inline void bcm_intc_isrc_unmask(struct bcm_intc_softc *sc, struct bcm_intc_irqsrc *bii) { intc_write_4(sc, bii->bii_enable_reg, bii->bii_mask); } static inline int bcm2835_intc_active_intr(struct bcm_intc_softc *sc) { uint32_t pending, pending_gpu; pending = intc_read_4(sc, INTC_PENDING_BASIC) & INTC_PENDING_BASIC_MASK; if (pending == 0) return (-1); if (pending & INTC_PENDING_BASIC_ARM) return (ffs(pending) - 1); if (pending & INTC_PENDING_BASIC_GPU1_MASK) { if (pending & INTC_PENDING_BASIC_GPU1_7) return (BANK1_START + 7); if (pending & INTC_PENDING_BASIC_GPU1_9) return (BANK1_START + 9); if (pending & INTC_PENDING_BASIC_GPU1_10) return (BANK1_START + 10); if (pending & INTC_PENDING_BASIC_GPU1_18) return (BANK1_START + 18); if (pending & INTC_PENDING_BASIC_GPU1_19) return (BANK1_START + 19); } if (pending & INTC_PENDING_BASIC_GPU2_MASK) { if (pending & INTC_PENDING_BASIC_GPU2_21) return (BANK2_START + 21); if (pending & INTC_PENDING_BASIC_GPU2_22) return (BANK2_START + 22); if (pending & INTC_PENDING_BASIC_GPU2_23) return (BANK2_START + 23); if (pending & INTC_PENDING_BASIC_GPU2_24) return (BANK2_START + 24); if (pending & INTC_PENDING_BASIC_GPU2_25) return (BANK2_START + 25); if (pending & INTC_PENDING_BASIC_GPU2_30) return (BANK2_START + 30); } if (pending & INTC_PENDING_BASIC_GPU1_PEND) { pending_gpu = intc_read_4(sc, INTC_PENDING_BANK1); pending_gpu &= INTC_PENDING_BANK1_MASK; if (pending_gpu != 0) return (BANK1_START + ffs(pending_gpu) - 1); } if (pending & INTC_PENDING_BASIC_GPU2_PEND) { pending_gpu = intc_read_4(sc, INTC_PENDING_BANK2); pending_gpu &= INTC_PENDING_BANK2_MASK; if (pending_gpu != 0) return (BANK2_START + ffs(pending_gpu) - 1); } return (-1); /* It shouldn't end here, but it's hardware. */ } static int bcm2835_intc_intr(void *arg) { int irq, num; struct bcm_intc_softc *sc = arg; for (num = 0; ; num++) { irq = bcm2835_intc_active_intr(sc); if (irq == -1) break; if (intr_isrc_dispatch(&sc->intc_isrcs[irq].bii_isrc, curthread->td_intr_frame) != 0) { bcm_intc_isrc_mask(sc, &sc->intc_isrcs[irq]); device_printf(sc->sc_dev, "Stray irq %u disabled\n", irq); } arm_irq_memory_barrier(0); /* XXX */ } if (num == 0) device_printf(sc->sc_dev, "Spurious interrupt detected\n"); return (FILTER_HANDLED); } static void bcm_intc_enable_intr(device_t dev, struct intr_irqsrc *isrc) { struct bcm_intc_irqsrc *bii = (struct bcm_intc_irqsrc *)isrc; arm_irq_memory_barrier(bii->bii_irq); bcm_intc_isrc_unmask(device_get_softc(dev), bii); } static void bcm_intc_disable_intr(device_t dev, struct intr_irqsrc *isrc) { bcm_intc_isrc_mask(device_get_softc(dev), (struct bcm_intc_irqsrc *)isrc); } static int bcm_intc_map_intr(device_t dev, struct intr_map_data *data, struct intr_irqsrc **isrcp) { u_int irq; struct intr_map_data_fdt *daf; struct bcm_intc_softc *sc; bool valid; if (data->type != INTR_MAP_DATA_FDT) return (ENOTSUP); daf = (struct intr_map_data_fdt *)data; if (daf->ncells == 1) irq = daf->cells[0]; else if (daf->ncells == 2) { valid = true; switch (daf->cells[0]) { case 0: irq = daf->cells[1]; if (irq >= BANK1_START) valid = false; break; case 1: irq = daf->cells[1] + BANK1_START; if (irq > BANK1_END) valid = false; break; case 2: irq = daf->cells[1] + BANK2_START; if (irq > BANK2_END) valid = false; break; default: valid = false; break; } if (!valid) { device_printf(dev, "invalid IRQ config: bank=%d, irq=%d\n", daf->cells[0], daf->cells[1]); return (EINVAL); } } else return (EINVAL); if (irq >= BCM_INTC_NIRQS) return (EINVAL); sc = device_get_softc(dev); *isrcp = &sc->intc_isrcs[irq].bii_isrc; return (0); } static void bcm_intc_pre_ithread(device_t dev, struct intr_irqsrc *isrc) { bcm_intc_disable_intr(dev, isrc); } static void bcm_intc_post_ithread(device_t dev, struct intr_irqsrc *isrc) { bcm_intc_enable_intr(dev, isrc); } static void bcm_intc_post_filter(device_t dev, struct intr_irqsrc *isrc) { } static int bcm_intc_pic_register(struct bcm_intc_softc *sc, intptr_t xref) { struct bcm_intc_irqsrc *bii; int error; uint32_t irq; const char *name; name = device_get_nameunit(sc->sc_dev); for (irq = 0; irq < BCM_INTC_NIRQS; irq++) { bii = &sc->intc_isrcs[irq]; bii->bii_irq = irq; if (IS_IRQ_BASIC(irq)) { bii->bii_disable_reg = INTC_DISABLE_BASIC; bii->bii_enable_reg = INTC_ENABLE_BASIC; bii->bii_mask = 1 << irq; } else if (IS_IRQ_BANK1(irq)) { bii->bii_disable_reg = INTC_DISABLE_BANK1; bii->bii_enable_reg = INTC_ENABLE_BANK1; bii->bii_mask = 1 << IRQ_BANK1(irq); } else if (IS_IRQ_BANK2(irq)) { bii->bii_disable_reg = INTC_DISABLE_BANK2; bii->bii_enable_reg = INTC_ENABLE_BANK2; bii->bii_mask = 1 << IRQ_BANK2(irq); } else return (ENXIO); error = intr_isrc_register(&bii->bii_isrc, sc->sc_dev, 0, "%s,%u", name, irq); if (error != 0) return (error); } if (intr_pic_register(sc->sc_dev, xref) == NULL) return (ENXIO); return (0); } static int bcm_intc_probe(device_t dev) { if (!ofw_bus_status_okay(dev)) return (ENXIO); - if (!ofw_bus_is_compatible(dev, "broadcom,bcm2835-armctrl-ic") && - !ofw_bus_is_compatible(dev, "brcm,bcm2836-armctrl-ic")) + if (ofw_bus_search_compatible(dev, compat_data)->ocd_data == 0) return (ENXIO); + device_set_desc(dev, "BCM2835 Interrupt Controller"); return (BUS_PROBE_DEFAULT); } static int bcm_intc_attach(device_t dev) { struct bcm_intc_softc *sc = device_get_softc(dev); int rid = 0; intptr_t xref; sc->sc_dev = dev; if (bcm_intc_sc) return (ENXIO); sc->intc_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, RF_ACTIVE); if (sc->intc_res == NULL) { device_printf(dev, "could not allocate memory resource\n"); return (ENXIO); } xref = OF_xref_from_node(ofw_bus_get_node(dev)); if (bcm_intc_pic_register(sc, xref) != 0) { bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->intc_res); device_printf(dev, "could not register PIC\n"); return (ENXIO); } rid = 0; sc->intc_irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, RF_ACTIVE); if (sc->intc_irq_res == NULL) { if (intr_pic_claim_root(dev, xref, bcm2835_intc_intr, sc, 0) != 0) { /* XXX clean up */ device_printf(dev, "could not set PIC as a root\n"); return (ENXIO); } } else { if (bus_setup_intr(dev, sc->intc_irq_res, INTR_TYPE_CLK, bcm2835_intc_intr, NULL, sc, &sc->intc_irq_hdl)) { /* XXX clean up */ device_printf(dev, "could not setup irq handler\n"); return (ENXIO); } } sc->intc_bst = rman_get_bustag(sc->intc_res); sc->intc_bsh = rman_get_bushandle(sc->intc_res); bcm_intc_sc = sc; return (0); } static device_method_t bcm_intc_methods[] = { DEVMETHOD(device_probe, bcm_intc_probe), DEVMETHOD(device_attach, bcm_intc_attach), DEVMETHOD(pic_disable_intr, bcm_intc_disable_intr), DEVMETHOD(pic_enable_intr, bcm_intc_enable_intr), DEVMETHOD(pic_map_intr, bcm_intc_map_intr), DEVMETHOD(pic_post_filter, bcm_intc_post_filter), DEVMETHOD(pic_post_ithread, bcm_intc_post_ithread), DEVMETHOD(pic_pre_ithread, bcm_intc_pre_ithread), { 0, 0 } }; static driver_t bcm_intc_driver = { "intc", bcm_intc_methods, sizeof(struct bcm_intc_softc), }; static devclass_t bcm_intc_devclass; EARLY_DRIVER_MODULE(intc, simplebus, bcm_intc_driver, bcm_intc_devclass, 0, 0, BUS_PASS_INTERRUPT + BUS_PASS_ORDER_LATE); Index: head/sys/arm/broadcom/bcm2835/bcm2835_sdhci.c =================================================================== --- head/sys/arm/broadcom/bcm2835/bcm2835_sdhci.c (revision 330071) +++ head/sys/arm/broadcom/bcm2835/bcm2835_sdhci.c (revision 330072) @@ -1,688 +1,689 @@ /*- * SPDX-License-Identifier: BSD-2-Clause-FreeBSD * * Copyright (c) 2012 Oleksandr Tymoshenko * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. * */ #include __FBSDID("$FreeBSD$"); #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include "mmcbr_if.h" #include "sdhci_if.h" #include "opt_mmccam.h" #include "bcm2835_dma.h" #include #include "bcm2835_vcbus.h" #define BCM2835_DEFAULT_SDHCI_FREQ 50 #define BCM_SDHCI_BUFFER_SIZE 512 #define NUM_DMA_SEGS 2 #ifdef DEBUG #define dprintf(fmt, args...) do { printf("%s(): ", __func__); \ printf(fmt,##args); } while (0) #else #define dprintf(fmt, args...) #endif static int bcm2835_sdhci_hs = 1; static int bcm2835_sdhci_pio_mode = 0; static struct ofw_compat_data compat_data[] = { {"broadcom,bcm2835-sdhci", 1}, + {"brcm,bcm2835-sdhci", 1}, {"brcm,bcm2835-mmc", 1}, {NULL, 0} }; TUNABLE_INT("hw.bcm2835.sdhci.hs", &bcm2835_sdhci_hs); TUNABLE_INT("hw.bcm2835.sdhci.pio_mode", &bcm2835_sdhci_pio_mode); struct bcm_sdhci_softc { device_t sc_dev; struct resource * sc_mem_res; struct resource * sc_irq_res; bus_space_tag_t sc_bst; bus_space_handle_t sc_bsh; void * sc_intrhand; struct mmc_request * sc_req; struct sdhci_slot sc_slot; int sc_dma_ch; bus_dma_tag_t sc_dma_tag; bus_dmamap_t sc_dma_map; vm_paddr_t sc_sdhci_buffer_phys; uint32_t cmd_and_mode; bus_addr_t dmamap_seg_addrs[NUM_DMA_SEGS]; bus_size_t dmamap_seg_sizes[NUM_DMA_SEGS]; int dmamap_seg_count; int dmamap_seg_index; int dmamap_status; }; static int bcm_sdhci_probe(device_t); static int bcm_sdhci_attach(device_t); static int bcm_sdhci_detach(device_t); static void bcm_sdhci_intr(void *); static int bcm_sdhci_get_ro(device_t, device_t); static void bcm_sdhci_dma_intr(int ch, void *arg); static void bcm_sdhci_dmacb(void *arg, bus_dma_segment_t *segs, int nseg, int err) { struct bcm_sdhci_softc *sc = arg; int i; sc->dmamap_status = err; sc->dmamap_seg_count = nseg; /* Note nseg is guaranteed to be zero if err is non-zero. */ for (i = 0; i < nseg; i++) { sc->dmamap_seg_addrs[i] = segs[i].ds_addr; sc->dmamap_seg_sizes[i] = segs[i].ds_len; } } static int bcm_sdhci_probe(device_t dev) { if (!ofw_bus_status_okay(dev)) return (ENXIO); if (ofw_bus_search_compatible(dev, compat_data)->ocd_data == 0) return (ENXIO); device_set_desc(dev, "Broadcom 2708 SDHCI controller"); return (BUS_PROBE_DEFAULT); } static int bcm_sdhci_attach(device_t dev) { struct bcm_sdhci_softc *sc = device_get_softc(dev); int rid, err; phandle_t node; pcell_t cell; u_int default_freq; sc->sc_dev = dev; sc->sc_req = NULL; err = bcm2835_mbox_set_power_state(BCM2835_MBOX_POWER_ID_EMMC, TRUE); if (err != 0) { if (bootverbose) device_printf(dev, "Unable to enable the power\n"); return (err); } default_freq = 0; err = bcm2835_mbox_get_clock_rate(BCM2835_MBOX_CLOCK_ID_EMMC, &default_freq); if (err == 0) { /* Convert to MHz */ default_freq /= 1000000; } if (default_freq == 0) { node = ofw_bus_get_node(sc->sc_dev); if ((OF_getencprop(node, "clock-frequency", &cell, sizeof(cell))) > 0) default_freq = cell / 1000000; } if (default_freq == 0) default_freq = BCM2835_DEFAULT_SDHCI_FREQ; if (bootverbose) device_printf(dev, "SDHCI frequency: %dMHz\n", default_freq); rid = 0; sc->sc_mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, RF_ACTIVE); if (!sc->sc_mem_res) { device_printf(dev, "cannot allocate memory window\n"); err = ENXIO; goto fail; } sc->sc_bst = rman_get_bustag(sc->sc_mem_res); sc->sc_bsh = rman_get_bushandle(sc->sc_mem_res); rid = 0; sc->sc_irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, RF_ACTIVE); if (!sc->sc_irq_res) { device_printf(dev, "cannot allocate interrupt\n"); err = ENXIO; goto fail; } if (bus_setup_intr(dev, sc->sc_irq_res, INTR_TYPE_BIO | INTR_MPSAFE, NULL, bcm_sdhci_intr, sc, &sc->sc_intrhand)) { device_printf(dev, "cannot setup interrupt handler\n"); err = ENXIO; goto fail; } if (!bcm2835_sdhci_pio_mode) sc->sc_slot.opt = SDHCI_PLATFORM_TRANSFER; sc->sc_slot.caps = SDHCI_CAN_VDD_330 | SDHCI_CAN_VDD_180; if (bcm2835_sdhci_hs) sc->sc_slot.caps |= SDHCI_CAN_DO_HISPD; sc->sc_slot.caps |= (default_freq << SDHCI_CLOCK_BASE_SHIFT); sc->sc_slot.quirks = SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK | SDHCI_QUIRK_BROKEN_TIMEOUT_VAL | SDHCI_QUIRK_DONT_SET_HISPD_BIT | SDHCI_QUIRK_MISSING_CAPS; sdhci_init_slot(dev, &sc->sc_slot, 0); sc->sc_dma_ch = bcm_dma_allocate(BCM_DMA_CH_ANY); if (sc->sc_dma_ch == BCM_DMA_CH_INVALID) goto fail; bcm_dma_setup_intr(sc->sc_dma_ch, bcm_sdhci_dma_intr, sc); /* Allocate bus_dma resources. */ err = bus_dma_tag_create(bus_get_dma_tag(dev), 1, 0, BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, BCM_SDHCI_BUFFER_SIZE, NUM_DMA_SEGS, BCM_SDHCI_BUFFER_SIZE, BUS_DMA_ALLOCNOW, NULL, NULL, &sc->sc_dma_tag); if (err) { device_printf(dev, "failed allocate DMA tag"); goto fail; } err = bus_dmamap_create(sc->sc_dma_tag, 0, &sc->sc_dma_map); if (err) { device_printf(dev, "bus_dmamap_create failed\n"); goto fail; } /* FIXME: Fix along with other BUS_SPACE_PHYSADDR instances */ sc->sc_sdhci_buffer_phys = rman_get_start(sc->sc_mem_res) + SDHCI_BUFFER; bus_generic_probe(dev); bus_generic_attach(dev); sdhci_start_slot(&sc->sc_slot); return (0); fail: if (sc->sc_intrhand) bus_teardown_intr(dev, sc->sc_irq_res, sc->sc_intrhand); if (sc->sc_irq_res) bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sc_irq_res); if (sc->sc_mem_res) bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->sc_mem_res); return (err); } static int bcm_sdhci_detach(device_t dev) { return (EBUSY); } static void bcm_sdhci_intr(void *arg) { struct bcm_sdhci_softc *sc = arg; sdhci_generic_intr(&sc->sc_slot); } static int bcm_sdhci_get_ro(device_t bus, device_t child) { return (0); } static inline uint32_t RD4(struct bcm_sdhci_softc *sc, bus_size_t off) { uint32_t val = bus_space_read_4(sc->sc_bst, sc->sc_bsh, off); return val; } static inline void WR4(struct bcm_sdhci_softc *sc, bus_size_t off, uint32_t val) { bus_space_write_4(sc->sc_bst, sc->sc_bsh, off, val); /* * The Arasan HC has a bug where it may lose the content of * consecutive writes to registers that are within two SD-card * clock cycles of each other (a clock domain crossing problem). */ if (sc->sc_slot.clock > 0) DELAY(((2 * 1000000) / sc->sc_slot.clock) + 1); } static uint8_t bcm_sdhci_read_1(device_t dev, struct sdhci_slot *slot, bus_size_t off) { struct bcm_sdhci_softc *sc = device_get_softc(dev); uint32_t val = RD4(sc, off & ~3); return ((val >> (off & 3)*8) & 0xff); } static uint16_t bcm_sdhci_read_2(device_t dev, struct sdhci_slot *slot, bus_size_t off) { struct bcm_sdhci_softc *sc = device_get_softc(dev); uint32_t val = RD4(sc, off & ~3); /* * Standard 32-bit handling of command and transfer mode. */ if (off == SDHCI_TRANSFER_MODE) { return (sc->cmd_and_mode >> 16); } else if (off == SDHCI_COMMAND_FLAGS) { return (sc->cmd_and_mode & 0x0000ffff); } return ((val >> (off & 3)*8) & 0xffff); } static uint32_t bcm_sdhci_read_4(device_t dev, struct sdhci_slot *slot, bus_size_t off) { struct bcm_sdhci_softc *sc = device_get_softc(dev); return RD4(sc, off); } static void bcm_sdhci_read_multi_4(device_t dev, struct sdhci_slot *slot, bus_size_t off, uint32_t *data, bus_size_t count) { struct bcm_sdhci_softc *sc = device_get_softc(dev); bus_space_read_multi_4(sc->sc_bst, sc->sc_bsh, off, data, count); } static void bcm_sdhci_write_1(device_t dev, struct sdhci_slot *slot, bus_size_t off, uint8_t val) { struct bcm_sdhci_softc *sc = device_get_softc(dev); uint32_t val32 = RD4(sc, off & ~3); val32 &= ~(0xff << (off & 3)*8); val32 |= (val << (off & 3)*8); WR4(sc, off & ~3, val32); } static void bcm_sdhci_write_2(device_t dev, struct sdhci_slot *slot, bus_size_t off, uint16_t val) { struct bcm_sdhci_softc *sc = device_get_softc(dev); uint32_t val32; if (off == SDHCI_COMMAND_FLAGS) val32 = sc->cmd_and_mode; else val32 = RD4(sc, off & ~3); val32 &= ~(0xffff << (off & 3)*8); val32 |= (val << (off & 3)*8); if (off == SDHCI_TRANSFER_MODE) sc->cmd_and_mode = val32; else { WR4(sc, off & ~3, val32); if (off == SDHCI_COMMAND_FLAGS) sc->cmd_and_mode = val32; } } static void bcm_sdhci_write_4(device_t dev, struct sdhci_slot *slot, bus_size_t off, uint32_t val) { struct bcm_sdhci_softc *sc = device_get_softc(dev); WR4(sc, off, val); } static void bcm_sdhci_write_multi_4(device_t dev, struct sdhci_slot *slot, bus_size_t off, uint32_t *data, bus_size_t count) { struct bcm_sdhci_softc *sc = device_get_softc(dev); bus_space_write_multi_4(sc->sc_bst, sc->sc_bsh, off, data, count); } static void bcm_sdhci_start_dma_seg(struct bcm_sdhci_softc *sc) { struct sdhci_slot *slot; vm_paddr_t pdst, psrc; int err, idx, len, sync_op; slot = &sc->sc_slot; idx = sc->dmamap_seg_index++; len = sc->dmamap_seg_sizes[idx]; slot->offset += len; if (slot->curcmd->data->flags & MMC_DATA_READ) { bcm_dma_setup_src(sc->sc_dma_ch, BCM_DMA_DREQ_EMMC, BCM_DMA_SAME_ADDR, BCM_DMA_32BIT); bcm_dma_setup_dst(sc->sc_dma_ch, BCM_DMA_DREQ_NONE, BCM_DMA_INC_ADDR, (len & 0xf) ? BCM_DMA_32BIT : BCM_DMA_128BIT); psrc = sc->sc_sdhci_buffer_phys; pdst = sc->dmamap_seg_addrs[idx]; sync_op = BUS_DMASYNC_PREREAD; } else { bcm_dma_setup_src(sc->sc_dma_ch, BCM_DMA_DREQ_NONE, BCM_DMA_INC_ADDR, (len & 0xf) ? BCM_DMA_32BIT : BCM_DMA_128BIT); bcm_dma_setup_dst(sc->sc_dma_ch, BCM_DMA_DREQ_EMMC, BCM_DMA_SAME_ADDR, BCM_DMA_32BIT); psrc = sc->dmamap_seg_addrs[idx]; pdst = sc->sc_sdhci_buffer_phys; sync_op = BUS_DMASYNC_PREWRITE; } /* * When starting a new DMA operation do the busdma sync operation, and * disable SDCHI data interrrupts because we'll be driven by DMA * interrupts (or SDHCI error interrupts) until the IO is done. */ if (idx == 0) { bus_dmamap_sync(sc->sc_dma_tag, sc->sc_dma_map, sync_op); slot->intmask &= ~(SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL | SDHCI_INT_DATA_END); bcm_sdhci_write_4(sc->sc_dev, &sc->sc_slot, SDHCI_SIGNAL_ENABLE, slot->intmask); } /* * Start the DMA transfer. Only programming errors (like failing to * allocate a channel) cause a non-zero return from bcm_dma_start(). */ err = bcm_dma_start(sc->sc_dma_ch, psrc, pdst, len); KASSERT((err == 0), ("bcm2835_sdhci: failed DMA start")); } static void bcm_sdhci_dma_intr(int ch, void *arg) { struct bcm_sdhci_softc *sc = (struct bcm_sdhci_softc *)arg; struct sdhci_slot *slot = &sc->sc_slot; uint32_t reg, mask; int left, sync_op; mtx_lock(&slot->mtx); /* * If there are more segments for the current dma, start the next one. * Otherwise unload the dma map and decide what to do next based on the * status of the sdhci controller and whether there's more data left. */ if (sc->dmamap_seg_index < sc->dmamap_seg_count) { bcm_sdhci_start_dma_seg(sc); mtx_unlock(&slot->mtx); return; } if (slot->curcmd->data->flags & MMC_DATA_READ) { sync_op = BUS_DMASYNC_POSTREAD; mask = SDHCI_INT_DATA_AVAIL; } else { sync_op = BUS_DMASYNC_POSTWRITE; mask = SDHCI_INT_SPACE_AVAIL; } bus_dmamap_sync(sc->sc_dma_tag, sc->sc_dma_map, sync_op); bus_dmamap_unload(sc->sc_dma_tag, sc->sc_dma_map); sc->dmamap_seg_count = 0; sc->dmamap_seg_index = 0; left = min(BCM_SDHCI_BUFFER_SIZE, slot->curcmd->data->len - slot->offset); /* DATA END? */ reg = bcm_sdhci_read_4(slot->bus, slot, SDHCI_INT_STATUS); if (reg & SDHCI_INT_DATA_END) { /* ACK for all outstanding interrupts */ bcm_sdhci_write_4(slot->bus, slot, SDHCI_INT_STATUS, reg); /* enable INT */ slot->intmask |= SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL | SDHCI_INT_DATA_END; bcm_sdhci_write_4(slot->bus, slot, SDHCI_SIGNAL_ENABLE, slot->intmask); /* finish this data */ sdhci_finish_data(slot); } else { /* already available? */ if (reg & mask) { /* ACK for DATA_AVAIL or SPACE_AVAIL */ bcm_sdhci_write_4(slot->bus, slot, SDHCI_INT_STATUS, mask); /* continue next DMA transfer */ if (bus_dmamap_load(sc->sc_dma_tag, sc->sc_dma_map, (uint8_t *)slot->curcmd->data->data + slot->offset, left, bcm_sdhci_dmacb, sc, BUS_DMA_NOWAIT) != 0 || sc->dmamap_status != 0) { slot->curcmd->error = MMC_ERR_NO_MEMORY; sdhci_finish_data(slot); } else { bcm_sdhci_start_dma_seg(sc); } } else { /* wait for next data by INT */ /* enable INT */ slot->intmask |= SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL | SDHCI_INT_DATA_END; bcm_sdhci_write_4(slot->bus, slot, SDHCI_SIGNAL_ENABLE, slot->intmask); } } mtx_unlock(&slot->mtx); } static void bcm_sdhci_read_dma(device_t dev, struct sdhci_slot *slot) { struct bcm_sdhci_softc *sc = device_get_softc(slot->bus); size_t left; if (sc->dmamap_seg_count != 0) { device_printf(sc->sc_dev, "DMA in use\n"); return; } left = min(BCM_SDHCI_BUFFER_SIZE, slot->curcmd->data->len - slot->offset); KASSERT((left & 3) == 0, ("%s: len = %zu, not word-aligned", __func__, left)); if (bus_dmamap_load(sc->sc_dma_tag, sc->sc_dma_map, (uint8_t *)slot->curcmd->data->data + slot->offset, left, bcm_sdhci_dmacb, sc, BUS_DMA_NOWAIT) != 0 || sc->dmamap_status != 0) { slot->curcmd->error = MMC_ERR_NO_MEMORY; return; } /* DMA start */ bcm_sdhci_start_dma_seg(sc); } static void bcm_sdhci_write_dma(device_t dev, struct sdhci_slot *slot) { struct bcm_sdhci_softc *sc = device_get_softc(slot->bus); size_t left; if (sc->dmamap_seg_count != 0) { device_printf(sc->sc_dev, "DMA in use\n"); return; } left = min(BCM_SDHCI_BUFFER_SIZE, slot->curcmd->data->len - slot->offset); KASSERT((left & 3) == 0, ("%s: len = %zu, not word-aligned", __func__, left)); if (bus_dmamap_load(sc->sc_dma_tag, sc->sc_dma_map, (uint8_t *)slot->curcmd->data->data + slot->offset, left, bcm_sdhci_dmacb, sc, BUS_DMA_NOWAIT) != 0 || sc->dmamap_status != 0) { slot->curcmd->error = MMC_ERR_NO_MEMORY; return; } /* DMA start */ bcm_sdhci_start_dma_seg(sc); } static int bcm_sdhci_will_handle_transfer(device_t dev, struct sdhci_slot *slot) { size_t left; /* * Do not use DMA for transfers less than block size or with a length * that is not a multiple of four. */ left = min(BCM_DMA_BLOCK_SIZE, slot->curcmd->data->len - slot->offset); if (left < BCM_DMA_BLOCK_SIZE) return (0); if (left & 0x03) return (0); return (1); } static void bcm_sdhci_start_transfer(device_t dev, struct sdhci_slot *slot, uint32_t *intmask) { /* DMA transfer FIFO 1KB */ if (slot->curcmd->data->flags & MMC_DATA_READ) bcm_sdhci_read_dma(dev, slot); else bcm_sdhci_write_dma(dev, slot); } static void bcm_sdhci_finish_transfer(device_t dev, struct sdhci_slot *slot) { sdhci_finish_data(slot); } static device_method_t bcm_sdhci_methods[] = { /* Device interface */ DEVMETHOD(device_probe, bcm_sdhci_probe), DEVMETHOD(device_attach, bcm_sdhci_attach), DEVMETHOD(device_detach, bcm_sdhci_detach), /* Bus interface */ DEVMETHOD(bus_read_ivar, sdhci_generic_read_ivar), DEVMETHOD(bus_write_ivar, sdhci_generic_write_ivar), /* MMC bridge interface */ DEVMETHOD(mmcbr_update_ios, sdhci_generic_update_ios), DEVMETHOD(mmcbr_request, sdhci_generic_request), DEVMETHOD(mmcbr_get_ro, bcm_sdhci_get_ro), DEVMETHOD(mmcbr_acquire_host, sdhci_generic_acquire_host), DEVMETHOD(mmcbr_release_host, sdhci_generic_release_host), /* Platform transfer methods */ DEVMETHOD(sdhci_platform_will_handle, bcm_sdhci_will_handle_transfer), DEVMETHOD(sdhci_platform_start_transfer, bcm_sdhci_start_transfer), DEVMETHOD(sdhci_platform_finish_transfer, bcm_sdhci_finish_transfer), /* SDHCI registers accessors */ DEVMETHOD(sdhci_read_1, bcm_sdhci_read_1), DEVMETHOD(sdhci_read_2, bcm_sdhci_read_2), DEVMETHOD(sdhci_read_4, bcm_sdhci_read_4), DEVMETHOD(sdhci_read_multi_4, bcm_sdhci_read_multi_4), DEVMETHOD(sdhci_write_1, bcm_sdhci_write_1), DEVMETHOD(sdhci_write_2, bcm_sdhci_write_2), DEVMETHOD(sdhci_write_4, bcm_sdhci_write_4), DEVMETHOD(sdhci_write_multi_4, bcm_sdhci_write_multi_4), DEVMETHOD_END }; static devclass_t bcm_sdhci_devclass; static driver_t bcm_sdhci_driver = { "sdhci_bcm", bcm_sdhci_methods, sizeof(struct bcm_sdhci_softc), }; DRIVER_MODULE(sdhci_bcm, simplebus, bcm_sdhci_driver, bcm_sdhci_devclass, NULL, NULL); MODULE_DEPEND(sdhci_bcm, sdhci, 1, 1, 1); #ifndef MMCCAM MMC_DECLARE_BRIDGE(sdhci_bcm); #endif Index: head/sys/arm/broadcom/bcm2835/bcm2835_systimer.c =================================================================== --- head/sys/arm/broadcom/bcm2835/bcm2835_systimer.c (revision 330071) +++ head/sys/arm/broadcom/bcm2835/bcm2835_systimer.c (revision 330072) @@ -1,314 +1,318 @@ /* * SPDX-License-Identifier: BSD-2-Clause-FreeBSD * * Copyright (c) 2012 Oleksandr Tymoshenko * Copyright (c) 2012 Damjan Marion * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. */ #include __FBSDID("$FreeBSD$"); #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #define BCM2835_NUM_TIMERS 4 #define DEFAULT_TIMER 3 #define DEFAULT_TIMER_NAME "BCM2835-3" #define DEFAULT_FREQUENCY 1000000 #define MIN_PERIOD 5LLU #define SYSTIMER_CS 0x00 #define SYSTIMER_CLO 0x04 #define SYSTIMER_CHI 0x08 #define SYSTIMER_C0 0x0C #define SYSTIMER_C1 0x10 #define SYSTIMER_C2 0x14 #define SYSTIMER_C3 0x18 struct systimer { int index; bool enabled; struct eventtimer et; }; struct bcm_systimer_softc { struct resource* mem_res; struct resource* irq_res[BCM2835_NUM_TIMERS]; void* intr_hl[BCM2835_NUM_TIMERS]; uint32_t sysclk_freq; bus_space_tag_t bst; bus_space_handle_t bsh; struct systimer st[BCM2835_NUM_TIMERS]; }; static struct resource_spec bcm_systimer_irq_spec[] = { { SYS_RES_IRQ, 0, RF_ACTIVE }, { SYS_RES_IRQ, 1, RF_ACTIVE }, { SYS_RES_IRQ, 2, RF_ACTIVE }, { SYS_RES_IRQ, 3, RF_ACTIVE }, { -1, 0, 0 } }; +static struct ofw_compat_data compat_data[] = { + {"broadcom,bcm2835-system-timer", 1}, + {"brcm,bcm2835-system-timer", 1}, + {NULL, 0} +}; + static struct bcm_systimer_softc *bcm_systimer_sc = NULL; /* Read/Write macros for Timer used as timecounter */ #define bcm_systimer_tc_read_4(reg) \ bus_space_read_4(bcm_systimer_sc->bst, \ bcm_systimer_sc->bsh, reg) #define bcm_systimer_tc_write_4(reg, val) \ bus_space_write_4(bcm_systimer_sc->bst, \ bcm_systimer_sc->bsh, reg, val) static unsigned bcm_systimer_tc_get_timecount(struct timecounter *); static delay_func bcm_systimer_delay; static struct timecounter bcm_systimer_tc = { .tc_name = DEFAULT_TIMER_NAME, .tc_get_timecount = bcm_systimer_tc_get_timecount, .tc_poll_pps = NULL, .tc_counter_mask = ~0u, .tc_frequency = 0, .tc_quality = 1000, }; static unsigned bcm_systimer_tc_get_timecount(struct timecounter *tc) { if (bcm_systimer_sc == NULL) return (0); return bcm_systimer_tc_read_4(SYSTIMER_CLO); } static int bcm_systimer_start(struct eventtimer *et, sbintime_t first, sbintime_t period) { struct systimer *st = et->et_priv; uint32_t clo, clo1; uint32_t count; register_t s; if (first != 0) { count = ((uint32_t)et->et_frequency * first) >> 32; s = intr_disable(); clo = bcm_systimer_tc_read_4(SYSTIMER_CLO); restart: clo += count; /* * Clear pending interrupts */ bcm_systimer_tc_write_4(SYSTIMER_CS, (1 << st->index)); bcm_systimer_tc_write_4(SYSTIMER_C0 + st->index*4, clo); clo1 = bcm_systimer_tc_read_4(SYSTIMER_CLO); if ((int32_t)(clo1 - clo) >= 0) { count *= 2; clo = clo1; goto restart; } st->enabled = 1; intr_restore(s); return (0); } return (EINVAL); } static int bcm_systimer_stop(struct eventtimer *et) { struct systimer *st = et->et_priv; st->enabled = 0; return (0); } static int bcm_systimer_intr(void *arg) { struct systimer *st = (struct systimer *)arg; uint32_t cs; cs = bcm_systimer_tc_read_4(SYSTIMER_CS); if ((cs & (1 << st->index)) == 0) return (FILTER_STRAY); /* ACK interrupt */ bcm_systimer_tc_write_4(SYSTIMER_CS, (1 << st->index)); if (st->enabled) { if (st->et.et_active) { st->et.et_event_cb(&st->et, st->et.et_arg); } } return (FILTER_HANDLED); } static int bcm_systimer_probe(device_t dev) { if (!ofw_bus_status_okay(dev)) return (ENXIO); - if (ofw_bus_is_compatible(dev, "broadcom,bcm2835-system-timer")) { - device_set_desc(dev, "BCM2835 System Timer"); - return (BUS_PROBE_DEFAULT); - } + if (ofw_bus_search_compatible(dev, compat_data)->ocd_data == 0) + return (ENXIO); - return (ENXIO); + return (BUS_PROBE_DEFAULT); } static int bcm_systimer_attach(device_t dev) { struct bcm_systimer_softc *sc = device_get_softc(dev); int err; int rid = 0; if (bcm_systimer_sc != NULL) return (EINVAL); sc->mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, RF_ACTIVE); if (sc->mem_res == NULL) { device_printf(dev, "could not allocate memory resource\n"); return (ENXIO); } sc->bst = rman_get_bustag(sc->mem_res); sc->bsh = rman_get_bushandle(sc->mem_res); /* Request the IRQ resources */ err = bus_alloc_resources(dev, bcm_systimer_irq_spec, sc->irq_res); if (err) { device_printf(dev, "Error: could not allocate irq resources\n"); return (ENXIO); } /* TODO: get frequency from FDT */ sc->sysclk_freq = DEFAULT_FREQUENCY; /* Setup and enable the timer */ if (bus_setup_intr(dev, sc->irq_res[DEFAULT_TIMER], INTR_TYPE_CLK, bcm_systimer_intr, NULL, &sc->st[DEFAULT_TIMER], &sc->intr_hl[DEFAULT_TIMER]) != 0) { bus_release_resources(dev, bcm_systimer_irq_spec, sc->irq_res); device_printf(dev, "Unable to setup the clock irq handler.\n"); return (ENXIO); } sc->st[DEFAULT_TIMER].index = DEFAULT_TIMER; sc->st[DEFAULT_TIMER].enabled = 0; sc->st[DEFAULT_TIMER].et.et_name = DEFAULT_TIMER_NAME; sc->st[DEFAULT_TIMER].et.et_flags = ET_FLAGS_ONESHOT; sc->st[DEFAULT_TIMER].et.et_quality = 1000; sc->st[DEFAULT_TIMER].et.et_frequency = sc->sysclk_freq; sc->st[DEFAULT_TIMER].et.et_min_period = (MIN_PERIOD << 32) / sc->st[DEFAULT_TIMER].et.et_frequency + 1; sc->st[DEFAULT_TIMER].et.et_max_period = (0x7ffffffeLLU << 32) / sc->st[DEFAULT_TIMER].et.et_frequency; sc->st[DEFAULT_TIMER].et.et_start = bcm_systimer_start; sc->st[DEFAULT_TIMER].et.et_stop = bcm_systimer_stop; sc->st[DEFAULT_TIMER].et.et_priv = &sc->st[DEFAULT_TIMER]; et_register(&sc->st[DEFAULT_TIMER].et); bcm_systimer_sc = sc; if (device_get_unit(dev) == 0) arm_set_delay(bcm_systimer_delay, sc); bcm_systimer_tc.tc_frequency = DEFAULT_FREQUENCY; tc_init(&bcm_systimer_tc); return (0); } static device_method_t bcm_systimer_methods[] = { DEVMETHOD(device_probe, bcm_systimer_probe), DEVMETHOD(device_attach, bcm_systimer_attach), { 0, 0 } }; static driver_t bcm_systimer_driver = { "systimer", bcm_systimer_methods, sizeof(struct bcm_systimer_softc), }; static devclass_t bcm_systimer_devclass; DRIVER_MODULE(bcm_systimer, simplebus, bcm_systimer_driver, bcm_systimer_devclass, 0, 0); static void bcm_systimer_delay(int usec, void *arg) { struct bcm_systimer_softc *sc; int32_t counts; uint32_t first, last; sc = (struct bcm_systimer_softc *) arg; /* Get the number of times to count */ counts = usec * (bcm_systimer_tc.tc_frequency / 1000000) + 1; first = bcm_systimer_tc_read_4(SYSTIMER_CLO); while (counts > 0) { last = bcm_systimer_tc_read_4(SYSTIMER_CLO); if (last == first) continue; if (last>first) { counts -= (int32_t)(last - first); } else { counts -= (int32_t)((0xFFFFFFFF - first) + last); } first = last; } } Index: head/sys/arm/broadcom/bcm2835/bcm283x_dwc_fdt.c =================================================================== --- head/sys/arm/broadcom/bcm2835/bcm283x_dwc_fdt.c (revision 330071) +++ head/sys/arm/broadcom/bcm2835/bcm283x_dwc_fdt.c (revision 330072) @@ -1,104 +1,105 @@ /* * Copyright 2015 Andrew Turner. * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are * met: * * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ #include __FBSDID("$FreeBSD$"); #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include static struct ofw_compat_data compat_data[] = { {"broadcom,bcm2835-usb", 1}, + {"brcm,bcm2835-usb", 1}, {"brcm,bcm2708-usb", 1}, {NULL, 0} }; static device_probe_t bcm283x_dwc_otg_probe; static device_attach_t bcm283x_dwc_otg_attach; static int bcm283x_dwc_otg_probe(device_t dev) { if (!ofw_bus_status_okay(dev)) return (ENXIO); if (ofw_bus_search_compatible(dev, compat_data)->ocd_data == 0) return (ENXIO); device_set_desc(dev, "DWC OTG 2.0 integrated USB controller (bcm283x)"); return (BUS_PROBE_VENDOR); } static int bcm283x_dwc_otg_attach(device_t dev) { int err; err = bcm2835_mbox_set_power_state(BCM2835_MBOX_POWER_ID_USB_HCD, TRUE); if (err) device_printf(dev, "failed to set power state, err=%d\n", err); return (dwc_otg_attach(dev)); } static device_method_t bcm283x_dwc_otg_methods[] = { /* bus interface */ DEVMETHOD(device_probe, bcm283x_dwc_otg_probe), DEVMETHOD(device_attach, bcm283x_dwc_otg_attach), DEVMETHOD_END }; static devclass_t bcm283x_dwc_otg_devclass; DEFINE_CLASS_1(bcm283x_dwcotg, bcm283x_dwc_otg_driver, bcm283x_dwc_otg_methods, sizeof(struct dwc_otg_fdt_softc), dwc_otg_driver); DRIVER_MODULE(bcm283x_dwcotg, simplebus, bcm283x_dwc_otg_driver, bcm283x_dwc_otg_devclass, 0, 0); MODULE_DEPEND(bcm283x_dwcotg, usb, 1, 1, 1); Index: head/sys/dts/arm/rpi.dts =================================================================== --- head/sys/dts/arm/rpi.dts (revision 330071) +++ head/sys/dts/arm/rpi.dts (revision 330072) @@ -1,401 +1,96 @@ /* * Copyright (c) 2012 Oleksandr Tymoshenko * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. * * $FreeBSD$ */ -/dts-v1/; + +#include "bcm2835-rpi-b.dts" -/include/ "bcm2835.dtsi" - / { - model = "Raspberry Pi (BCM2835)"; - compatible = "raspberrypi,model-a", "raspberrypi,model-b", - "broadcom,bcm2835-vc", "broadcom,bcm2708-vc"; - - memreserve = <0x08000000 0x08000000>; /* Set by VideoCore */ - - cpus { - #address-cells = <1>; - #size-cells = <0>; - cpu@0 { - compatible = "arm,1176jzf-s"; - device_type = "cpu"; - reg = <0>; /* CPU ID=0 */ - clock-frequency = <700000000>; /* 700MHz */ - }; - }; - + /* This is only necessary for FDT_DTB_STATIC */ memory { device_type = "memory"; reg = <0 0x8000000>; /* 128MB, Set by VideoCore */ }; - system { - revision = <0>; /* Set by VideoCore */ - serial = <0 0>; /* Set by VideoCore */ - }; - - axi { - gpio: gpio { - /* BSC0 */ - pins_bsc0_a: bsc0_a { - broadcom,function = "ALT0"; - }; - - pins_bsc0_b: bsc0_b { - broadcom,function = "ALT0"; - }; - - pins_bsc0_c: bsc0_c { - broadcom,function = "ALT1"; - }; - - /* BSC1 */ - pins_bsc1_a: bsc1_a { - broadcom,function = "ALT0"; - }; - - pins_bsc1_b: bsc1_b { - broadcom,function = "ALT2"; - }; - - /* GPCLK0 */ - pins_gpclk0_a: gpclk0_a { - broadcom,function = "ALT0"; - }; - - pins_gpclk0_b: gpclk0_b { - broadcom,function = "ALT5"; - }; - - pins_gpclk0_c: gpclk0_c { - broadcom,function = "ALT0"; - }; - - pins_gpclk0_d: gpclk0_d { - broadcom,function = "ALT0"; - }; - - /* GPCLK1 */ - pins_gpclk1_a: gpclk1_a { - broadcom,function = "ALT0"; - }; - - pins_gpclk1_b: gpclk1_b { - broadcom,function = "ALT5"; - }; - - pins_gpclk1_c: gpclk1_c { - broadcom,function = "ALT0"; - }; - - pins_gpclk1_d: gpclk1_d { - broadcom,function = "ALT0"; - }; - - /* GPCLK2 */ - pins_gpclk2_a: gpclk2_a { - broadcom,function = "ALT0"; - }; - - pins_gpclk2_b: gpclk2_b { - broadcom,function = "ALT0"; - }; - - /* SPI0 */ - pins_spi0_a: spi0_a { - broadcom,function = "ALT0"; - }; - - pins_spi0_b: spi0_b { - broadcom,function = "ALT0"; - }; - - /* PWM */ - pins_pwm0_a: pwm0_a { - broadcom,function = "ALT0"; - }; - - pins_pwm0_b: pwm0_b { - broadcom,function = "ALT5"; - }; - - pins_pwm0_c: pwm0_c { - broadcom,function = "ALT0"; - }; - - pins_pwm1_a: pwm1_a { - broadcom,function = "ALT0"; - }; - - pins_pwm1_b: pwm1_b { - broadcom,function = "ALT5"; - }; - - pins_pwm1_c: pwm1_c { - broadcom,function = "ALT0"; - }; - - pins_pwm1_d: pwm1_d { - broadcom,function = "ALT0"; - }; - - /* UART0 */ - pins_uart0_a: uart0_a { - broadcom,function = "ALT0"; - }; - - pins_uart0_b: uart0_b { - broadcom,function = "ALT3"; - }; - - pins_uart0_c: uart0_c { - broadcom,function = "ALT2"; - }; - - pins_uart0_fc_a: uart0_fc_a { - broadcom,function = "ALT3"; - }; - - pins_uart0_fc_b: uart0_fc_b { - broadcom,function = "ALT3"; - }; - - pins_uart0_fc_c: uart0_fc_c { - broadcom,function = "ALT2"; - }; - - /* PCM */ - pins_pcm_a: pcm_a { - broadcom,function = "ALT0"; - }; - - pins_pcm_b: pcm_b { - broadcom,function = "ALT2"; - }; - - /* Secondary Address Bus */ - pins_sm_addr_a: sm_addr_a { - broadcom,function = "ALT1"; - }; - - pins_sm_addr_b: sm_addr_b { - broadcom,function = "ALT1"; - }; - - pins_sm_ctl_a: sm_ctl_a { - broadcom,function = "ALT1"; - }; - - pins_sm_ctl_b: sm_ctl_b { - broadcom,function = "ALT1"; - }; - - pins_sm_data_8bit_a: sm_data_8bit_a { - broadcom,function = "ALT1"; - }; - - pins_sm_data_8bit_b: sm_data_8bit_b { - broadcom,function = "ALT1"; - }; - - pins_sm_data_16bit: sm_data_16bit { - broadcom,function = "ALT1"; - }; - - pins_sm_data_18bit: sm_data_18bit { - broadcom,function = "ALT1"; - }; - - /* BSCSL */ - pins_bscsl: bscsl { - broadcom,function = "ALT3"; - }; - - /* SPISL */ - pins_spisl: spisl { - broadcom,function = "ALT3"; - }; - - /* SPI1 */ - pins_spi1: spi1 { - broadcom,function = "ALT4"; - }; - - /* UART1 */ - pins_uart1_a: uart1_a { - broadcom,function = "ALT5"; - }; - - pins_uart1_b: uart1_b { - broadcom,function = "ALT5"; - }; - - pins_uart1_c: uart1_c { - broadcom,function = "ALT5"; - }; - - pins_uart1_fc_a: uart1_fc_a { - broadcom,function = "ALT5"; - }; - - pins_uart1_fc_b: uart1_fc_b { - broadcom,function = "ALT5"; - }; - - pins_uart1_fc_c: uart1_fc_c { - broadcom,function = "ALT5"; - }; - - /* SPI2 */ - pins_spi2: spi2 { - broadcom,function = "ALT4"; - }; - - /* ARM JTAG */ - pins_arm_jtag_trst: arm_jtag_trst { - broadcom,function = "ALT4"; - }; - - pins_arm_jtag_a: arm_jtag_a { - broadcom,function = "ALT5"; - }; - - pins_arm_jtag_b: arm_jtag_b { - broadcom,function = "ALT4"; - }; - - /* Reserved */ - pins_reserved: reserved { - broadcom,function = "ALT3"; - }; - }; - usb { - hub { - compatible = "usb,hub", "usb,device"; - reg = <0x00000001>; - #address-cells = <1>; - #size-cells = <0>; - ethernet: ethernet { - compatible = "net,ethernet", - "usb,device"; - reg = <0x00000001>; - mac-address = [00 00 00 00 00 00]; - }; - }; - - }; - - - }; - - display { - compatible = "broadcom,bcm2835-fb", "broadcom,bcm2708-fb"; - - broadcom,vc-mailbox = <&vc_mbox>; - broadcom,vc-channel = <1>; - - broadcom,width = <0>; /* Set by VideoCore */ - broadcom,height = <0>; /* Set by VideoCore */ - broadcom,depth = <0>; /* Set by VideoCore */ - }; - rpi_ft5406 { compatible = "rpi,rpi-ft5406"; status = "okay"; }; - leds { - compatible = "gpio-leds"; - ok { - label = "ok"; - gpios = <&gpio 16 1>; + /* Temporary patches */ + soc { + sdhost: mmc@7e202000 { + status = "disabled"; + } - /* Don't change this - it configures - * how the led driver determines if - * the led is on or off when it loads. - */ - default-state = "keep"; - - /* This is the real default state. */ - linux,default-trigger = "default-on"; + sdhci@7e300000 { + status = "okay"; }; - }; - power: regulator { - compatible = "broadcom,bcm2835-power-mgr", - "broadcom,bcm2708-power-mgr", - "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; + rng@7e104000 { + interrupts = <2 29>; + } - broadcom,vc-mailbox = <&vc_mbox>; - broadcom,vc-channel = <0>; + spi@7e204000 { + status = "okay"; + }; - regulator-name = "VideoCore"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on = <1>; - - sd_card_power: regulator@0 { - compatible = "broadcom,bcm2835-power-dev", - "broadcom,bcm2708-power-dev"; - reg = <0>; - - vin-supply = <&power>; - regulator-name = "SD Card"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; + gpio@7e200000 { + /* Pins that can short 3.3V to GND in output mode: 46-47 + * Pins used by VideoCore: 48-53 + */ + broadcom,read-only = <46>, <47>, <48>, <49>, <50>, + <51>, <52>, <53>; + + /* Reserved */ + pins_reserved: reserved { + broadcom,pins = <48>, <49>, <50>, <51>, <52>, + <53>; + }; + } + + vchiq { + compatible = "brcm,bcm2835-vchiq"; + reg = <0x7e00b840 0xf>; + interrupts = <0 2>; + cache-line-size = <32>; }; - /* This is for the controller itself, not the root port */ - usb_hcd_power: regulator@3 { - compatible = "broadcom,bcm2835-power-dev", - "broadcom,bcm2708-power-dev"; - reg = <3>; + display { + compatible = "broadcom,bcm2835-fb", "broadcom,bcm2708-fb"; - vin-supply = <&power>; - regulator-name = "USB HCD"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; + broadcom,vc-mailbox = <&mailbox>; + broadcom,vc-channel = <1>; + + broadcom,width = <0>; /* Set by VideoCore */ + broadcom,height = <0>; /* Set by VideoCore */ + broadcom,depth = <0>; /* Set by VideoCore */ }; - }; - aliases { - uart0 = &uart0; - ethernet0 = ðernet; }; - - chosen { - bootargs = ""; /* Set by VideoCore */ - stdin = "uart0"; - stdout = "uart0"; - }; - - __overrides__ { - cache_line_size = <&vchiq>, "cache-line-size:0"; - }; }; + Index: head/sys/dts/arm/rpi2.dts =================================================================== --- head/sys/dts/arm/rpi2.dts (revision 330071) +++ head/sys/dts/arm/rpi2.dts (revision 330072) @@ -1,412 +1,95 @@ /* * Copyright (c) 2012 Oleksandr Tymoshenko * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. * * $FreeBSD$ */ -/dts-v1/; -/include/ "bcm2836.dtsi" +#include "bcm2836-rpi-2-b.dts" / { - model = "Raspberry Pi 2 Model B"; - compatible = "brcm,bcm2836"; - - memreserve = <0x08000000 0x08000000>; /* Set by VideoCore */ - - cpus { - #address-cells = <1>; - #size-cells = <0>; - cpu@0 { - compatible = "arm,cortex-a7"; - device_type = "cpu"; - reg = <0xf00>; /* CPU ID=0xf00 */ - clock-frequency = <800000000>; /* 800MHz */ - }; - cpu@1 { - compatible = "arm,cortex-a7"; - device_type = "cpu"; - reg = <0xf01>; /* CPU ID=0xf01 */ - clock-frequency = <800000000>; /* 800MHz */ - }; - cpu@2 { - compatible = "arm,cortex-a7"; - device_type = "cpu"; - reg = <0xf02>; /* CPU ID=0xf02 */ - clock-frequency = <800000000>; /* 800MHz */ - }; - cpu@3 { - compatible = "arm,cortex-a7"; - device_type = "cpu"; - reg = <0xf03>; /* CPU ID=0xf03 */ - clock-frequency = <800000000>; /* 800MHz */ - }; - }; - + /* This is only necessary for FDT_DTB_STATIC */ memory { device_type = "memory"; reg = <0 0x8000000>; /* 128MB, Set by VideoCore */ }; - system { - revision = <0>; /* Set by VideoCore */ - serial = <0 0>; /* Set by VideoCore */ - }; - - axi { - gpio: gpio { - /* BSC0 */ - pins_bsc0_a: bsc0_a { - broadcom,function = "ALT0"; - }; - - pins_bsc0_b: bsc0_b { - broadcom,function = "ALT0"; - }; - - pins_bsc0_c: bsc0_c { - broadcom,function = "ALT1"; - }; - - /* BSC1 */ - pins_bsc1_a: bsc1_a { - broadcom,function = "ALT0"; - }; - - pins_bsc1_b: bsc1_b { - broadcom,function = "ALT2"; - }; - - /* GPCLK0 */ - pins_gpclk0_a: gpclk0_a { - broadcom,function = "ALT0"; - }; - - pins_gpclk0_b: gpclk0_b { - broadcom,function = "ALT5"; - }; - - pins_gpclk0_c: gpclk0_c { - broadcom,function = "ALT0"; - }; - - pins_gpclk0_d: gpclk0_d { - broadcom,function = "ALT0"; - }; - - /* GPCLK1 */ - pins_gpclk1_a: gpclk1_a { - broadcom,function = "ALT0"; - }; - - pins_gpclk1_b: gpclk1_b { - broadcom,function = "ALT5"; - }; - - pins_gpclk1_c: gpclk1_c { - broadcom,function = "ALT0"; - }; - - pins_gpclk1_d: gpclk1_d { - broadcom,function = "ALT0"; - }; - - /* GPCLK2 */ - pins_gpclk2_a: gpclk2_a { - broadcom,function = "ALT0"; - }; - - pins_gpclk2_b: gpclk2_b { - broadcom,function = "ALT0"; - }; - - /* SPI0 */ - pins_spi0_a: spi0_a { - broadcom,function = "ALT0"; - }; - - pins_spi0_b: spi0_b { - broadcom,function = "ALT0"; - }; - - /* PWM */ - pins_pwm0_a: pwm0_a { - broadcom,function = "ALT0"; - }; - - pins_pwm0_b: pwm0_b { - broadcom,function = "ALT5"; - }; - - pins_pwm0_c: pwm0_c { - broadcom,function = "ALT0"; - }; - - pins_pwm1_a: pwm1_a { - broadcom,function = "ALT0"; - }; - - pins_pwm1_b: pwm1_b { - broadcom,function = "ALT5"; - }; - - pins_pwm1_c: pwm1_c { - broadcom,function = "ALT0"; - }; - - pins_pwm1_d: pwm1_d { - broadcom,function = "ALT0"; - }; - - /* UART0 */ - pins_uart0_a: uart0_a { - broadcom,function = "ALT0"; - }; - - pins_uart0_b: uart0_b { - broadcom,function = "ALT3"; - }; - - pins_uart0_c: uart0_c { - broadcom,function = "ALT2"; - }; - - pins_uart0_fc_a: uart0_fc_a { - broadcom,function = "ALT3"; - }; - - pins_uart0_fc_b: uart0_fc_b { - broadcom,function = "ALT3"; - }; - - pins_uart0_fc_c: uart0_fc_c { - broadcom,function = "ALT2"; - }; - - /* PCM */ - pins_pcm_a: pcm_a { - broadcom,function = "ALT0"; - }; - - pins_pcm_b: pcm_b { - broadcom,function = "ALT2"; - }; - - /* Secondary Address Bus */ - pins_sm_addr_a: sm_addr_a { - broadcom,function = "ALT1"; - }; - - pins_sm_addr_b: sm_addr_b { - broadcom,function = "ALT1"; - }; - - pins_sm_ctl_a: sm_ctl_a { - broadcom,function = "ALT1"; - }; - - pins_sm_ctl_b: sm_ctl_b { - broadcom,function = "ALT1"; - }; - - pins_sm_data_8bit_a: sm_data_8bit_a { - broadcom,function = "ALT1"; - }; - - pins_sm_data_8bit_b: sm_data_8bit_b { - broadcom,function = "ALT1"; - }; - - pins_sm_data_16bit: sm_data_16bit { - broadcom,function = "ALT1"; - }; - - pins_sm_data_18bit: sm_data_18bit { - broadcom,function = "ALT1"; - }; - - /* BSCSL */ - pins_bscsl: bscsl { - broadcom,function = "ALT3"; - }; - - /* SPISL */ - pins_spisl: spisl { - broadcom,function = "ALT3"; - }; - - /* SPI1 */ - pins_spi1: spi1 { - broadcom,function = "ALT4"; - }; - - /* UART1 */ - pins_uart1_a: uart1_a { - broadcom,function = "ALT5"; - }; - - pins_uart1_b: uart1_b { - broadcom,function = "ALT5"; - }; - - pins_uart1_c: uart1_c { - broadcom,function = "ALT5"; - }; - - pins_uart1_fc_a: uart1_fc_a { - broadcom,function = "ALT5"; - }; - - pins_uart1_fc_b: uart1_fc_b { - broadcom,function = "ALT5"; - }; - - pins_uart1_fc_c: uart1_fc_c { - broadcom,function = "ALT5"; - }; - - /* SPI2 */ - pins_spi2: spi2 { - broadcom,function = "ALT4"; - }; - - /* ARM JTAG */ - pins_arm_jtag_trst: arm_jtag_trst { - broadcom,function = "ALT4"; - }; - - pins_arm_jtag_a: arm_jtag_a { - broadcom,function = "ALT5"; - }; - - pins_arm_jtag_b: arm_jtag_b { - broadcom,function = "ALT4"; - }; - - /* Reserved */ - pins_reserved: reserved { - broadcom,function = "ALT3"; - }; - }; - usb { - hub { - compatible = "usb,hub", "usb,device"; - reg = <0x00000001>; - #address-cells = <1>; - #size-cells = <0>; - ethernet: ethernet { - compatible = "net,ethernet", - "usb,device"; - reg = <0x00000001>; - mac-address = [00 00 00 00 00 00]; - }; - }; - - }; - }; - - display { - compatible = "broadcom,bcm2835-fb", "broadcom,bcm2708-fb"; - - broadcom,vc-mailbox = <&vc_mbox>; - broadcom,vc-channel = <1>; - - broadcom,width = <0>; /* Set by VideoCore */ - broadcom,height = <0>; /* Set by VideoCore */ - broadcom,depth = <0>; /* Set by VideoCore */ - }; - rpi_ft5406 { compatible = "rpi,rpi-ft5406"; status = "okay"; }; - leds { - compatible = "gpio-leds"; - pwr { - label = "pwr"; - gpios = <&gpio 35 0>; - }; + /* Temporary patches */ + soc { + sdhost: mmc@7e202000 { + status = "disabled"; + } - act { - label = "act"; - gpios = <&gpio 47 0>; + sdhci@7e300000 { + status = "okay"; }; - }; - power: regulator { - compatible = "broadcom,bcm2835-power-mgr", - "broadcom,bcm2708-power-mgr", - "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; + rng@7e104000 { + interrupts = <2 29>; + } - broadcom,vc-mailbox = <&vc_mbox>; - broadcom,vc-channel = <0>; + spi@7e204000 { + status = "okay"; + }; - regulator-name = "VideoCore"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on = <1>; + gpio@7e200000 { + /* Pins that can short 3.3V to GND in output mode: 46-47 + * Pins used by VideoCore: 48-53 + */ + broadcom,read-only = <46>, <47>, <48>, <49>, <50>, + <51>, <52>, <53>; + + /* Reserved */ + pins_reserved: reserved { + broadcom,pins = <48>, <49>, <50>, <51>, <52>, + <53>; + }; + } - sd_card_power: regulator@0 { - compatible = "broadcom,bcm2835-power-dev", - "broadcom,bcm2708-power-dev"; - reg = <0>; + vchiq { + compatible = "brcm,bcm2835-vchiq"; + reg = <0x7e00b840 0xf>; + interrupts = <0 2>; + cache-line-size = <32>; + }; - vin-supply = <&power>; - regulator-name = "SD Card"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; + display { + compatible = "broadcom,bcm2835-fb", "broadcom,bcm2708-fb"; - /* This is for the controller itself, not the root port */ - usb_hcd_power: regulator@3 { - compatible = "broadcom,bcm2835-power-dev", - "broadcom,bcm2708-power-dev"; - reg = <3>; + broadcom,vc-mailbox = <&mailbox>; + broadcom,vc-channel = <1>; - vin-supply = <&power>; - regulator-name = "USB HCD"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; + broadcom,width = <0>; /* Set by VideoCore */ + broadcom,height = <0>; /* Set by VideoCore */ + broadcom,depth = <0>; /* Set by VideoCore */ }; - }; - aliases { - uart0 = &uart0; - ethernet0 = ðernet; - }; - - chosen { - bootargs = ""; /* Set by VideoCore */ - stdin = "uart0"; - stdout = "uart0"; - }; - - __overrides__ { - cache_line_size = <&vchiq>, "cache-line-size:0"; }; };