Index: head/sys/arm/freescale/imx/files.imx5 =================================================================== --- head/sys/arm/freescale/imx/files.imx5 (revision 329998) +++ head/sys/arm/freescale/imx/files.imx5 (revision 329999) @@ -1,54 +1,57 @@ # $FreeBSD$ kern/kern_clocksource.c standard # Init arm/freescale/imx/imx_common.c standard arm/freescale/imx/imx_machdep.c standard arm/freescale/imx/imx51_machdep.c optional soc_imx51 arm/freescale/imx/imx53_machdep.c optional soc_imx53 # Special serial console for debuging early boot code #arm/freescale/imx/imx_console.c standard # UART driver (includes serial console support) dev/uart/uart_dev_imx.c optional uart # TrustZone Interrupt Controller arm/freescale/imx/tzic.c standard # IOMUX - external pins multiplexor arm/freescale/imx/imx_iomux.c standard # GPIO arm/freescale/imx/imx_gpio.c optional gpio # Generic Periodic Timer arm/freescale/imx/imx_gpt.c standard # Clock Configuration Manager arm/freescale/imx/imx51_ccm.c standard # i.MX5xx PATA controller dev/ata/chipsets/ata-fsl.c optional imxata # SDHCI/MMC dev/sdhci/fsl_sdhci.c optional sdhci # USB OH3 controller (1 OTG, 3 EHCI) arm/freescale/imx/imx_nop_usbphy.c optional ehci dev/usb/controller/ehci_imx.c optional ehci # Watchdog arm/freescale/imx/imx_wdog.c optional imxwdt # i2c arm/freescale/imx/imx_i2c.c optional fsliic # IPU - Image Processing Unit (frame buffer also) arm/freescale/imx/imx51_ipuv3.c optional sc arm/freescale/imx/imx51_ipuv3_fbd.c optional vt dev/vt/hw/fb/vt_early_fb.c optional vt # Fast Ethernet Controller dev/ffec/if_ffec.c optional ffec +# SPI +arm/freescale/imx/imx_spi.c optional imx_spi + Index: head/sys/arm/freescale/imx/files.imx6 =================================================================== --- head/sys/arm/freescale/imx/files.imx6 (revision 329998) +++ head/sys/arm/freescale/imx/files.imx6 (revision 329999) @@ -1,73 +1,74 @@ # $FreeBSD$ # # Standard ARM support. # kern/kern_clocksource.c standard # # Standard imx6 devices and support. # arm/freescale/fsl_ocotp.c standard arm/freescale/imx/imx6_anatop.c standard arm/freescale/imx/imx6_ccm.c standard arm/freescale/imx/imx6_machdep.c standard arm/freescale/imx/imx6_mp.c optional smp arm/freescale/imx/imx6_pl310.c standard arm/freescale/imx/imx6_snvs.c optional imx6_snvs arm/freescale/imx/imx6_src.c standard arm/freescale/imx/imx_epit.c standard arm/freescale/imx/imx_iomux.c standard arm/freescale/imx/imx_machdep.c standard arm/freescale/imx/imx_gpt.c optional imx_gpt arm/freescale/imx/imx_gpio.c optional gpio arm/freescale/imx/imx_i2c.c optional fsliic +arm/freescale/imx/imx_spi.c optional imx_spi arm/freescale/imx/imx6_sdma.c optional fslsdma arm/freescale/imx/imx6_audmux.c optional sound arm/freescale/imx/imx6_ssi.c optional sound arm/freescale/imx/imx6_ahci.c optional ahci dev/hdmi/dwc_hdmi.c optional hdmi arm/freescale/imx/imx6_hdmi.c optional hdmi arm/freescale/imx/imx6_ipu.c optional vt # # Optional devices. # dev/sdhci/fsl_sdhci.c optional sdhci arm/freescale/imx/imx_wdog.c optional imxwdt dev/ffec/if_ffec.c optional ffec dev/uart/uart_dev_imx.c optional uart dev/usb/controller/ehci_imx.c optional ehci arm/freescale/imx/imx6_usbphy.c optional ehci # # Low-level serial console for debugging early kernel startup. # #arm/freescale/imx/imx_console.c standard # # Not ready yet... # #arm/freescale/imx/imx51_ipuv3.c optional sc # SDMA firmware sdma_fw.c optional sdma_fw \ compile-with "${AWK} -f $S/tools/fw_stub.awk sdma-imx6q-to1.bin:sdma_fw -msdma -c${.TARGET}" \ no-implicit-rule before-depend local \ clean "sdma_fw.c" sdma-imx6q-to1.fwo optional sdma_fw \ dependency "sdma-imx6q-to1.bin" \ compile-with "${LD} -b binary -d -warn-common -r -d -o ${.TARGET} sdma-imx6q-to1.bin" \ no-implicit-rule \ clean "sdma-imx6q-to1.fwo" sdma-imx6q-to1.bin optional sdma_fw \ dependency "$S/contrib/dev/imx/sdma-imx6q-to1.bin.uu" \ compile-with "uudecode < $S/contrib/dev/imx/sdma-imx6q-to1.bin.uu" \ no-obj no-implicit-rule \ clean "sdma-imx6q-to1.bin" Index: head/sys/arm/freescale/imx/imx51_ccm.c =================================================================== --- head/sys/arm/freescale/imx/imx51_ccm.c (revision 329998) +++ head/sys/arm/freescale/imx/imx51_ccm.c (revision 329999) @@ -1,656 +1,664 @@ /* $NetBSD: imx51_ccm.c,v 1.1 2012/04/17 09:33:31 bsh Exp $ */ /*- * SPDX-License-Identifier: BSD-2-Clause AND BSD-2-Clause-FreeBSD * * Copyright (c) 2010, 2011, 2012 Genetec Corporation. All rights reserved. * Written by Hashimoto Kenichi for Genetec Corporation. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY GENETEC CORPORATION ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL GENETEC CORPORATION * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE * POSSIBILITY OF SUCH DAMAGE. */ /*- * Copyright (c) 2012, 2013 The FreeBSD Foundation * All rights reserved. * * Portions of this software were developed by Oleksandr Rybalko * under sponsorship from the FreeBSD Foundation. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. */ /* * Clock Controller Module (CCM) */ #include __FBSDID("$FreeBSD$"); #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #define IMXCCMDEBUG #undef IMXCCMDEBUG #ifndef IMX51_OSC_FREQ #define IMX51_OSC_FREQ (24 * 1000 * 1000) /* 24MHz */ #endif #ifndef IMX51_CKIL_FREQ #define IMX51_CKIL_FREQ 32768 #endif /* * The fdt data does not provide reg properties describing the DPLL register * blocks we need to access, presumably because the needed addresses are * hard-coded within the linux driver. That leaves us with no choice but to do * the same thing, if we want to run with vendor-supplied fdt data. So here we * have tables of the physical addresses we need for each soc, and we'll use * bus_space_map() at attach() time to get access to them. */ static uint32_t imx51_dpll_addrs[IMX51_N_DPLLS] = { 0x83f80000, /* DPLL1 */ 0x83f84000, /* DPLL2 */ 0x83f88000, /* DPLL3 */ }; static uint32_t imx53_dpll_addrs[IMX51_N_DPLLS] = { 0x63f80000, /* DPLL1 */ 0x63f84000, /* DPLL2 */ 0x63f88000, /* DPLL3 */ }; #define DPLL_REGS_SZ (16 * 1024) struct imxccm_softc { device_t sc_dev; struct resource *ccmregs; u_int64_t pll_freq[IMX51_N_DPLLS]; bus_space_tag_t pllbst; bus_space_handle_t pllbsh[IMX51_N_DPLLS]; }; struct imxccm_softc *ccm_softc = NULL; static uint64_t imx51_get_pll_freq(u_int); static int imxccm_match(device_t); static int imxccm_attach(device_t); static device_method_t imxccm_methods[] = { DEVMETHOD(device_probe, imxccm_match), DEVMETHOD(device_attach, imxccm_attach), DEVMETHOD_END }; static driver_t imxccm_driver = { "imxccm", imxccm_methods, sizeof(struct imxccm_softc), }; static devclass_t imxccm_devclass; EARLY_DRIVER_MODULE(imxccm, simplebus, imxccm_driver, imxccm_devclass, 0, 0, BUS_PASS_CPU); static inline uint32_t pll_read_4(struct imxccm_softc *sc, int pll, int reg) { return (bus_space_read_4(sc->pllbst, sc->pllbsh[pll - 1], reg)); } static inline uint32_t ccm_read_4(struct imxccm_softc *sc, int reg) { return (bus_read_4(sc->ccmregs, reg)); } static inline void ccm_write_4(struct imxccm_softc *sc, int reg, uint32_t val) { bus_write_4(sc->ccmregs, reg, val); } static int imxccm_match(device_t dev) { if (!ofw_bus_status_okay(dev)) return (ENXIO); if (!ofw_bus_is_compatible(dev, "fsl,imx51-ccm") && !ofw_bus_is_compatible(dev, "fsl,imx53-ccm")) return (ENXIO); device_set_desc(dev, "Freescale Clock Control Module"); return (BUS_PROBE_DEFAULT); } static int imxccm_attach(device_t dev) { struct imxccm_softc *sc; int idx; u_int soc; uint32_t *pll_addrs; sc = device_get_softc(dev); sc->sc_dev = dev; switch ((soc = imx_soc_type())) { case IMXSOC_51: pll_addrs = imx51_dpll_addrs; break; case IMXSOC_53: pll_addrs = imx53_dpll_addrs; break; default: device_printf(dev, "No support for SoC type 0x%08x\n", soc); goto noclocks; } idx = 0; sc->ccmregs = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &idx, RF_ACTIVE); if (sc->ccmregs == NULL) { device_printf(dev, "could not allocate resources\n"); goto noclocks; } sc->pllbst = fdtbus_bs_tag; for (idx = 0; idx < IMX51_N_DPLLS; ++idx) { if (bus_space_map(sc->pllbst, pll_addrs[idx], DPLL_REGS_SZ, 0, &sc->pllbsh[idx]) != 0) { device_printf(dev, "Cannot map DPLL registers\n"); goto noclocks; } } ccm_softc = sc; imx51_get_pll_freq(1); imx51_get_pll_freq(2); imx51_get_pll_freq(3); device_printf(dev, "PLL1=%lluMHz, PLL2=%lluMHz, PLL3=%lluMHz\n", sc->pll_freq[0] / 1000000, sc->pll_freq[1] / 1000000, sc->pll_freq[2] / 1000000); device_printf(dev, "CPU clock=%d, UART clock=%d\n", imx51_get_clock(IMX51CLK_ARM_ROOT), imx51_get_clock(IMX51CLK_UART_CLK_ROOT)); device_printf(dev, "mainbus clock=%d, ahb clock=%d ipg clock=%d perclk=%d\n", imx51_get_clock(IMX51CLK_MAIN_BUS_CLK), imx51_get_clock(IMX51CLK_AHB_CLK_ROOT), imx51_get_clock(IMX51CLK_IPG_CLK_ROOT), imx51_get_clock(IMX51CLK_PERCLK_ROOT)); return (0); noclocks: panic("Cannot continue without clock support"); } u_int imx51_get_clock(enum imx51_clock clk) { u_int freq; u_int sel; uint32_t cacrr; /* ARM clock root register */ uint32_t ccsr; uint32_t cscdr1; uint32_t cscmr1; uint32_t cbcdr; uint32_t cbcmr; uint32_t cdcr; if (ccm_softc == NULL) return (0); switch (clk) { case IMX51CLK_PLL1: case IMX51CLK_PLL2: case IMX51CLK_PLL3: return ccm_softc->pll_freq[clk-IMX51CLK_PLL1]; case IMX51CLK_PLL1SW: ccsr = ccm_read_4(ccm_softc, CCMC_CCSR); if ((ccsr & CCSR_PLL1_SW_CLK_SEL) == 0) return ccm_softc->pll_freq[1-1]; /* step clock */ /* FALLTHROUGH */ case IMX51CLK_PLL1STEP: ccsr = ccm_read_4(ccm_softc, CCMC_CCSR); switch ((ccsr & CCSR_STEP_SEL_MASK) >> CCSR_STEP_SEL_SHIFT) { case 0: return imx51_get_clock(IMX51CLK_LP_APM); case 1: return 0; /* XXX PLL bypass clock */ case 2: return ccm_softc->pll_freq[2-1] / (1 + ((ccsr & CCSR_PLL2_DIV_PODF_MASK) >> CCSR_PLL2_DIV_PODF_SHIFT)); case 3: return ccm_softc->pll_freq[3-1] / (1 + ((ccsr & CCSR_PLL3_DIV_PODF_MASK) >> CCSR_PLL3_DIV_PODF_SHIFT)); } /*NOTREACHED*/ case IMX51CLK_PLL2SW: ccsr = ccm_read_4(ccm_softc, CCMC_CCSR); if ((ccsr & CCSR_PLL2_SW_CLK_SEL) == 0) return imx51_get_clock(IMX51CLK_PLL2); return 0; /* XXX PLL2 bypass clk */ case IMX51CLK_PLL3SW: ccsr = ccm_read_4(ccm_softc, CCMC_CCSR); if ((ccsr & CCSR_PLL3_SW_CLK_SEL) == 0) return imx51_get_clock(IMX51CLK_PLL3); return 0; /* XXX PLL3 bypass clk */ case IMX51CLK_LP_APM: ccsr = ccm_read_4(ccm_softc, CCMC_CCSR); return (ccsr & CCSR_LP_APM) ? imx51_get_clock(IMX51CLK_FPM) : IMX51_OSC_FREQ; case IMX51CLK_ARM_ROOT: freq = imx51_get_clock(IMX51CLK_PLL1SW); cacrr = ccm_read_4(ccm_softc, CCMC_CACRR); return freq / (cacrr + 1); /* ... */ case IMX51CLK_MAIN_BUS_CLK_SRC: cbcdr = ccm_read_4(ccm_softc, CCMC_CBCDR); if ((cbcdr & CBCDR_PERIPH_CLK_SEL) == 0) freq = imx51_get_clock(IMX51CLK_PLL2SW); else { freq = 0; cbcmr = ccm_read_4(ccm_softc, CCMC_CBCMR); switch ((cbcmr & CBCMR_PERIPH_APM_SEL_MASK) >> CBCMR_PERIPH_APM_SEL_SHIFT) { case 0: freq = imx51_get_clock(IMX51CLK_PLL1SW); break; case 1: freq = imx51_get_clock(IMX51CLK_PLL3SW); break; case 2: freq = imx51_get_clock(IMX51CLK_LP_APM); break; case 3: /* XXX: error */ break; } } return freq; case IMX51CLK_MAIN_BUS_CLK: freq = imx51_get_clock(IMX51CLK_MAIN_BUS_CLK_SRC); cdcr = ccm_read_4(ccm_softc, CCMC_CDCR); return freq / (1 + ((cdcr & CDCR_PERIPH_CLK_DVFS_PODF_MASK) >> CDCR_PERIPH_CLK_DVFS_PODF_SHIFT)); case IMX51CLK_AHB_CLK_ROOT: freq = imx51_get_clock(IMX51CLK_MAIN_BUS_CLK); cbcdr = ccm_read_4(ccm_softc, CCMC_CBCDR); return freq / (1 + ((cbcdr & CBCDR_AHB_PODF_MASK) >> CBCDR_AHB_PODF_SHIFT)); case IMX51CLK_IPG_CLK_ROOT: freq = imx51_get_clock(IMX51CLK_AHB_CLK_ROOT); cbcdr = ccm_read_4(ccm_softc, CCMC_CBCDR); return freq / (1 + ((cbcdr & CBCDR_IPG_PODF_MASK) >> CBCDR_IPG_PODF_SHIFT)); case IMX51CLK_PERCLK_ROOT: cbcmr = ccm_read_4(ccm_softc, CCMC_CBCMR); if (cbcmr & CBCMR_PERCLK_IPG_SEL) return imx51_get_clock(IMX51CLK_IPG_CLK_ROOT); if (cbcmr & CBCMR_PERCLK_LP_APM_SEL) freq = imx51_get_clock(IMX51CLK_LP_APM); else freq = imx51_get_clock(IMX51CLK_MAIN_BUS_CLK_SRC); cbcdr = ccm_read_4(ccm_softc, CCMC_CBCDR); #ifdef IMXCCMDEBUG printf("cbcmr=%x cbcdr=%x\n", cbcmr, cbcdr); #endif freq /= 1 + ((cbcdr & CBCDR_PERCLK_PRED1_MASK) >> CBCDR_PERCLK_PRED1_SHIFT); freq /= 1 + ((cbcdr & CBCDR_PERCLK_PRED2_MASK) >> CBCDR_PERCLK_PRED2_SHIFT); freq /= 1 + ((cbcdr & CBCDR_PERCLK_PODF_MASK) >> CBCDR_PERCLK_PODF_SHIFT); return freq; case IMX51CLK_UART_CLK_ROOT: cscdr1 = ccm_read_4(ccm_softc, CCMC_CSCDR1); cscmr1 = ccm_read_4(ccm_softc, CCMC_CSCMR1); #ifdef IMXCCMDEBUG printf("cscdr1=%x cscmr1=%x\n", cscdr1, cscmr1); #endif sel = (cscmr1 & CSCMR1_UART_CLK_SEL_MASK) >> CSCMR1_UART_CLK_SEL_SHIFT; freq = 0; /* shut up GCC */ switch (sel) { case 0: case 1: case 2: freq = imx51_get_clock(IMX51CLK_PLL1SW + sel); break; case 3: freq = imx51_get_clock(IMX51CLK_LP_APM); break; } return freq / (1 + ((cscdr1 & CSCDR1_UART_CLK_PRED_MASK) >> CSCDR1_UART_CLK_PRED_SHIFT)) / (1 + ((cscdr1 & CSCDR1_UART_CLK_PODF_MASK) >> CSCDR1_UART_CLK_PODF_SHIFT)); case IMX51CLK_IPU_HSP_CLK_ROOT: freq = 0; cbcmr = ccm_read_4(ccm_softc, CCMC_CBCMR); switch ((cbcmr & CBCMR_IPU_HSP_CLK_SEL_MASK) >> CBCMR_IPU_HSP_CLK_SEL_SHIFT) { case 0: freq = imx51_get_clock(IMX51CLK_ARM_AXI_A_CLK); break; case 1: freq = imx51_get_clock(IMX51CLK_ARM_AXI_B_CLK); break; case 2: freq = imx51_get_clock( IMX51CLK_EMI_SLOW_CLK_ROOT); break; case 3: freq = imx51_get_clock(IMX51CLK_AHB_CLK_ROOT); break; } return freq; default: device_printf(ccm_softc->sc_dev, "clock %d: not supported yet\n", clk); return 0; } } static uint64_t imx51_get_pll_freq(u_int pll_no) { uint32_t dp_ctrl; uint32_t dp_op; uint32_t dp_mfd; uint32_t dp_mfn; uint32_t mfi; int32_t mfn; uint32_t mfd; uint32_t pdf; uint32_t ccr; uint64_t freq = 0; u_int ref = 0; KASSERT(1 <= pll_no && pll_no <= IMX51_N_DPLLS, ("Wrong PLL id")); dp_ctrl = pll_read_4(ccm_softc, pll_no, DPLL_DP_CTL); if (dp_ctrl & DP_CTL_HFSM) { dp_op = pll_read_4(ccm_softc, pll_no, DPLL_DP_HFS_OP); dp_mfd = pll_read_4(ccm_softc, pll_no, DPLL_DP_HFS_MFD); dp_mfn = pll_read_4(ccm_softc, pll_no, DPLL_DP_HFS_MFN); } else { dp_op = pll_read_4(ccm_softc, pll_no, DPLL_DP_OP); dp_mfd = pll_read_4(ccm_softc, pll_no, DPLL_DP_MFD); dp_mfn = pll_read_4(ccm_softc, pll_no, DPLL_DP_MFN); } pdf = dp_op & DP_OP_PDF_MASK; mfi = max(5, (dp_op & DP_OP_MFI_MASK) >> DP_OP_MFI_SHIFT); mfd = dp_mfd; if (dp_mfn & 0x04000000) /* 27bit signed value */ mfn = (uint32_t)(0xf8000000 | dp_mfn); else mfn = dp_mfn; switch (dp_ctrl & DP_CTL_REF_CLK_SEL_MASK) { case DP_CTL_REF_CLK_SEL_COSC: /* Internal Oscillator */ /* TODO: get from FDT "fsl,imx-osc" */ ref = 24000000; /* IMX51_OSC_FREQ */ break; case DP_CTL_REF_CLK_SEL_FPM: ccr = ccm_read_4(ccm_softc, CCMC_CCR); if (ccr & CCR_FPM_MULT) /* TODO: get from FDT "fsl,imx-ckil" */ ref = 32768 * 1024; else /* TODO: get from FDT "fsl,imx-ckil" */ ref = 32768 * 512; break; default: ref = 0; } if (dp_ctrl & DP_CTL_REF_CLK_DIV) ref /= 2; ref *= 4; freq = (int64_t)ref * mfi + (int64_t)ref * mfn / (mfd + 1); freq /= pdf + 1; if (!(dp_ctrl & DP_CTL_DPDCK0_2_EN)) freq /= 2; #ifdef IMXCCMDEBUG printf("ref: %dKHz ", ref); printf("dp_ctl: %08x ", dp_ctrl); printf("pdf: %3d ", pdf); printf("mfi: %3d ", mfi); printf("mfd: %3d ", mfd); printf("mfn: %3d ", mfn); printf("pll: %d\n", (uint32_t)freq); #endif ccm_softc->pll_freq[pll_no-1] = freq; return (freq); } void imx51_clk_gating(int clk_src, int mode) { int field, group; uint32_t reg; group = CCMR_CCGR_MODULE(clk_src); field = clk_src % CCMR_CCGR_NSOURCE; reg = ccm_read_4(ccm_softc, CCMC_CCGR(group)); reg &= ~(0x03 << field * 2); reg |= (mode << field * 2); ccm_write_4(ccm_softc, CCMC_CCGR(group), reg); } int imx51_get_clk_gating(int clk_src) { uint32_t reg; reg = ccm_read_4(ccm_softc, CCMC_CCGR(CCMR_CCGR_MODULE(clk_src))); return ((reg >> (clk_src % CCMR_CCGR_NSOURCE) * 2) & 0x03); } /* * Code from here down is temporary, in lieu of a SoC-independent clock API. */ void imx_ccm_usb_enable(device_t dev) { uint32_t regval; /* * Select PLL2 as the source for the USB clock. * The default is PLL3, but U-boot changes it to PLL2. */ regval = ccm_read_4(ccm_softc, CCMC_CSCMR1); regval &= ~CSCMR1_USBOH3_CLK_SEL_MASK; regval |= 1 << CSCMR1_USBOH3_CLK_SEL_SHIFT; ccm_write_4(ccm_softc, CCMC_CSCMR1, regval); /* * Set the USB clock pre-divider to div-by-5, post-divider to div-by-2. */ regval = ccm_read_4(ccm_softc, CCMC_CSCDR1); regval &= ~CSCDR1_USBOH3_CLK_PODF_MASK; regval &= ~CSCDR1_USBOH3_CLK_PRED_MASK; regval |= 4 << CSCDR1_USBOH3_CLK_PRED_SHIFT; regval |= 1 << CSCDR1_USBOH3_CLK_PODF_SHIFT; ccm_write_4(ccm_softc, CCMC_CSCDR1, regval); /* * The same two clocks gates are used on imx51 and imx53. */ imx51_clk_gating(CCGR_USBOH3_IPG_AHB_CLK, CCGR_CLK_MODE_ALWAYS); imx51_clk_gating(CCGR_USBOH3_60M_CLK, CCGR_CLK_MODE_ALWAYS); } void imx_ccm_usbphy_enable(device_t dev) { uint32_t regval; /* * Select PLL3 as the source for the USBPHY clock. U-boot does this * only for imx53, but the bit exists on imx51. That seems a bit * strange, but we'll go with it until more is known. */ if (imx_soc_type() == IMXSOC_53) { regval = ccm_read_4(ccm_softc, CCMC_CSCMR1); regval |= 1 << CSCMR1_USBPHY_CLK_SEL_SHIFT; ccm_write_4(ccm_softc, CCMC_CSCMR1, regval); } /* * For the imx51 there's just one phy gate control, enable it. */ if (imx_soc_type() == IMXSOC_51) { imx51_clk_gating(CCGR_USB_PHY_CLK, CCGR_CLK_MODE_ALWAYS); return; } /* * For imx53 we don't have a full set of clock defines yet, but the * datasheet says: * gate reg 4, bits 13-12 usb ph2 clock (usb_phy2_clk_enable) * gate reg 4, bits 11-10 usb ph1 clock (usb_phy1_clk_enable) * * We should use the fdt data for the device to figure out which of * the two we're working on, but for now just turn them both on. */ if (imx_soc_type() == IMXSOC_53) { imx51_clk_gating(__CCGR_NUM(4, 5), CCGR_CLK_MODE_ALWAYS); imx51_clk_gating(__CCGR_NUM(4, 6), CCGR_CLK_MODE_ALWAYS); return; } } uint32_t +imx_ccm_ecspi_hz(void) +{ + + return (imx51_get_clock(IMX51CLK_CSPI_CLK_ROOT)); +} + +uint32_t imx_ccm_ipg_hz(void) { return (imx51_get_clock(IMX51CLK_IPG_CLK_ROOT)); } uint32_t imx_ccm_sdhci_hz(void) { return (imx51_get_clock(IMX51CLK_ESDHC1_CLK_ROOT)); } uint32_t imx_ccm_perclk_hz(void) { return (imx51_get_clock(IMX51CLK_PERCLK_ROOT)); } uint32_t imx_ccm_uart_hz(void) { return (imx51_get_clock(IMX51CLK_UART_CLK_ROOT)); } uint32_t imx_ccm_ahb_hz(void) { return (imx51_get_clock(IMX51CLK_AHB_CLK_ROOT)); } + Index: head/sys/arm/freescale/imx/imx6_ccm.c =================================================================== --- head/sys/arm/freescale/imx/imx6_ccm.c (revision 329998) +++ head/sys/arm/freescale/imx/imx6_ccm.c (revision 329999) @@ -1,458 +1,466 @@ /*- * SPDX-License-Identifier: BSD-2-Clause-FreeBSD * * Copyright (c) 2013 Ian Lepore * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. */ #include __FBSDID("$FreeBSD$"); /* * Clocks and power control driver for Freescale i.MX6 family of SoCs. */ #include #include #include #include #include #include #include #include #include #include #include #include #include #include #ifndef CCGR_CLK_MODE_ALWAYS #define CCGR_CLK_MODE_OFF 0 #define CCGR_CLK_MODE_RUNMODE 1 #define CCGR_CLK_MODE_ALWAYS 3 #endif struct ccm_softc { device_t dev; struct resource *mem_res; }; static struct ccm_softc *ccm_sc; static inline uint32_t RD4(struct ccm_softc *sc, bus_size_t off) { return (bus_read_4(sc->mem_res, off)); } static inline void WR4(struct ccm_softc *sc, bus_size_t off, uint32_t val) { bus_write_4(sc->mem_res, off, val); } /* * Until we have a fully functional ccm driver which implements the fdt_clock * interface, use the age-old workaround of unconditionally enabling the clocks * for devices we might need to use. The SoC defaults to most clocks enabled, * but the rom boot code and u-boot disable a few of them. We turn on only * what's needed to run the chip plus devices we have drivers for, and turn off * devices we don't yet have drivers for. (Note that USB is not turned on here * because that is one we do when the driver asks for it.) */ static void ccm_init_gates(struct ccm_softc *sc) { uint32_t reg; /* ahpbdma, aipstz 1 & 2 buses */ reg = CCGR0_AIPS_TZ1 | CCGR0_AIPS_TZ2 | CCGR0_ABPHDMA; WR4(sc, CCM_CCGR0, reg); - /* enet, epit, gpt */ - reg = CCGR1_ENET | CCGR1_EPIT1 | CCGR1_GPT; + /* enet, epit, gpt, spi */ + reg = CCGR1_ENET | CCGR1_EPIT1 | CCGR1_GPT | CCGR1_ECSPI1 | + CCGR1_ECSPI2 | CCGR1_ECSPI3 | CCGR1_ECSPI4 | CCGR1_ECSPI5; WR4(sc, CCM_CCGR1, reg); /* ipmux & ipsync (bridges), iomux, i2c */ reg = CCGR2_I2C1 | CCGR2_I2C2 | CCGR2_I2C3 | CCGR2_IIM | CCGR2_IOMUX_IPT | CCGR2_IPMUX1 | CCGR2_IPMUX2 | CCGR2_IPMUX3 | CCGR2_IPSYNC_IP2APB_TZASC1 | CCGR2_IPSYNC_IP2APB_TZASC2 | CCGR2_IPSYNC_VDOA; WR4(sc, CCM_CCGR2, reg); /* DDR memory controller */ reg = CCGR3_OCRAM | CCGR3_MMDC_CORE_IPG | CCGR3_MMDC_CORE_ACLK_FAST | CCGR3_CG11 | CCGR3_CG13; WR4(sc, CCM_CCGR3, reg); /* pl301 bus crossbar */ reg = CCGR4_PL301_MX6QFAST1_S133 | CCGR4_PL301_MX6QPER1_BCH | CCGR4_PL301_MX6QPER2_MAIN; WR4(sc, CCM_CCGR4, reg); /* uarts, ssi, sdma */ reg = CCGR5_SDMA | CCGR5_SSI1 | CCGR5_SSI2 | CCGR5_SSI3 | CCGR5_UART | CCGR5_UART_SERIAL; WR4(sc, CCM_CCGR5, reg); /* usdhc 1-4, usboh3 */ reg = CCGR6_USBOH3 | CCGR6_USDHC1 | CCGR6_USDHC2 | CCGR6_USDHC3 | CCGR6_USDHC4; WR4(sc, CCM_CCGR6, reg); } static int ccm_detach(device_t dev) { struct ccm_softc *sc; sc = device_get_softc(dev); if (sc->mem_res != NULL) bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->mem_res); return (0); } static int ccm_attach(device_t dev) { struct ccm_softc *sc; int err, rid; uint32_t reg; sc = device_get_softc(dev); err = 0; /* Allocate bus_space resources. */ rid = 0; sc->mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, RF_ACTIVE); if (sc->mem_res == NULL) { device_printf(dev, "Cannot allocate memory resources\n"); err = ENXIO; goto out; } ccm_sc = sc; /* * Configure the Low Power Mode setting to leave the ARM core power on * when a WFI instruction is executed. This lets the MPCore timers and * GIC continue to run, which is helpful when the only thing that can * wake you up is an MPCore Private Timer interrupt delivered via GIC. * * XXX Based on the docs, setting CCM_CGPR_INT_MEM_CLK_LPM shouldn't be * required when the LPM bits are set to LPM_RUN. But experimentally * I've experienced a fairly rare lockup when not setting it. I was * unable to prove conclusively that the lockup was related to power * management or that this definitively fixes it. Revisit this. */ reg = RD4(sc, CCM_CGPR); reg |= CCM_CGPR_INT_MEM_CLK_LPM; WR4(sc, CCM_CGPR, reg); reg = RD4(sc, CCM_CLPCR); reg = (reg & ~CCM_CLPCR_LPM_MASK) | CCM_CLPCR_LPM_RUN; WR4(sc, CCM_CLPCR, reg); ccm_init_gates(sc); err = 0; out: if (err != 0) ccm_detach(dev); return (err); } static int ccm_probe(device_t dev) { if (!ofw_bus_status_okay(dev)) return (ENXIO); if (ofw_bus_is_compatible(dev, "fsl,imx6q-ccm") == 0) return (ENXIO); device_set_desc(dev, "Freescale i.MX6 Clock Control Module"); return (BUS_PROBE_DEFAULT); } void imx_ccm_ssi_configure(device_t _ssidev) { struct ccm_softc *sc; uint32_t reg; sc = ccm_sc; /* * Select PLL4 (Audio PLL) clock multiplexer as source. * PLL output frequency = Fref * (DIV_SELECT + NUM/DENOM). */ reg = RD4(sc, CCM_CSCMR1); reg &= ~(SSI_CLK_SEL_M << SSI1_CLK_SEL_S); reg |= (SSI_CLK_SEL_PLL4 << SSI1_CLK_SEL_S); reg &= ~(SSI_CLK_SEL_M << SSI2_CLK_SEL_S); reg |= (SSI_CLK_SEL_PLL4 << SSI2_CLK_SEL_S); reg &= ~(SSI_CLK_SEL_M << SSI3_CLK_SEL_S); reg |= (SSI_CLK_SEL_PLL4 << SSI3_CLK_SEL_S); WR4(sc, CCM_CSCMR1, reg); /* * Ensure we have set hardware-default values * for pre and post dividers. */ /* SSI1 and SSI3 */ reg = RD4(sc, CCM_CS1CDR); /* Divide by 2 */ reg &= ~(SSI_CLK_PODF_MASK << SSI1_CLK_PODF_SHIFT); reg &= ~(SSI_CLK_PODF_MASK << SSI3_CLK_PODF_SHIFT); reg |= (0x1 << SSI1_CLK_PODF_SHIFT); reg |= (0x1 << SSI3_CLK_PODF_SHIFT); /* Divide by 4 */ reg &= ~(SSI_CLK_PRED_MASK << SSI1_CLK_PRED_SHIFT); reg &= ~(SSI_CLK_PRED_MASK << SSI3_CLK_PRED_SHIFT); reg |= (0x3 << SSI1_CLK_PRED_SHIFT); reg |= (0x3 << SSI3_CLK_PRED_SHIFT); WR4(sc, CCM_CS1CDR, reg); /* SSI2 */ reg = RD4(sc, CCM_CS2CDR); /* Divide by 2 */ reg &= ~(SSI_CLK_PODF_MASK << SSI2_CLK_PODF_SHIFT); reg |= (0x1 << SSI2_CLK_PODF_SHIFT); /* Divide by 4 */ reg &= ~(SSI_CLK_PRED_MASK << SSI2_CLK_PRED_SHIFT); reg |= (0x3 << SSI2_CLK_PRED_SHIFT); WR4(sc, CCM_CS2CDR, reg); } void imx_ccm_usb_enable(device_t _usbdev) { /* * For imx6, the USBOH3 clock gate is bits 0-1 of CCGR6, so no need for * shifting and masking here, just set the low-order two bits to ALWAYS. */ WR4(ccm_sc, CCM_CCGR6, RD4(ccm_sc, CCM_CCGR6) | CCGR_CLK_MODE_ALWAYS); } void imx_ccm_usbphy_enable(device_t _phydev) { /* * XXX Which unit? * Right now it's not clear how to figure from fdt data which phy unit * we're supposed to operate on. Until this is worked out, just enable * both PHYs. */ #if 0 int phy_num, regoff; phy_num = 0; /* XXX */ switch (phy_num) { case 0: regoff = 0; break; case 1: regoff = 0x10; break; default: device_printf(ccm_sc->dev, "Bad PHY number %u,\n", phy_num); return; } imx6_anatop_write_4(IMX6_ANALOG_CCM_PLL_USB1 + regoff, IMX6_ANALOG_CCM_PLL_USB_ENABLE | IMX6_ANALOG_CCM_PLL_USB_POWER | IMX6_ANALOG_CCM_PLL_USB_EN_USB_CLKS); #else imx6_anatop_write_4(IMX6_ANALOG_CCM_PLL_USB1 + 0, IMX6_ANALOG_CCM_PLL_USB_ENABLE | IMX6_ANALOG_CCM_PLL_USB_POWER | IMX6_ANALOG_CCM_PLL_USB_EN_USB_CLKS); imx6_anatop_write_4(IMX6_ANALOG_CCM_PLL_USB1 + 0x10, IMX6_ANALOG_CCM_PLL_USB_ENABLE | IMX6_ANALOG_CCM_PLL_USB_POWER | IMX6_ANALOG_CCM_PLL_USB_EN_USB_CLKS); #endif } int imx6_ccm_sata_enable(void) { uint32_t v; int timeout; /* Un-gate the sata controller. */ WR4(ccm_sc, CCM_CCGR5, RD4(ccm_sc, CCM_CCGR5) | CCGR5_SATA); /* Power up the PLL that feeds ENET/SATA/PCI phys, wait for lock. */ v = RD4(ccm_sc, CCM_ANALOG_PLL_ENET); v &= ~CCM_ANALOG_PLL_ENET_POWERDOWN; WR4(ccm_sc, CCM_ANALOG_PLL_ENET, v); for (timeout = 100000; timeout > 0; timeout--) { if (RD4(ccm_sc, CCM_ANALOG_PLL_ENET) & CCM_ANALOG_PLL_ENET_LOCK) { break; } } if (timeout <= 0) { return ETIMEDOUT; } /* Enable the PLL, and enable its 100mhz output. */ v |= CCM_ANALOG_PLL_ENET_ENABLE; v &= ~CCM_ANALOG_PLL_ENET_BYPASS; WR4(ccm_sc, CCM_ANALOG_PLL_ENET, v); v |= CCM_ANALOG_PLL_ENET_ENABLE_100M; WR4(ccm_sc, CCM_ANALOG_PLL_ENET, v); return 0; +} + +uint32_t +imx_ccm_ecspi_hz(void) +{ + + return (60000000); } uint32_t imx_ccm_ipg_hz(void) { return (66000000); } uint32_t imx_ccm_perclk_hz(void) { return (66000000); } uint32_t imx_ccm_sdhci_hz(void) { return (200000000); } uint32_t imx_ccm_uart_hz(void) { return (80000000); } uint32_t imx_ccm_ahb_hz(void) { return (132000000); } void imx_ccm_ipu_enable(int ipu) { struct ccm_softc *sc; uint32_t reg; sc = ccm_sc; reg = RD4(sc, CCM_CCGR3); if (ipu == 1) reg |= CCGR3_IPU1_IPU | CCGR3_IPU1_DI0; else reg |= CCGR3_IPU2_IPU | CCGR3_IPU2_DI0; WR4(sc, CCM_CCGR3, reg); } void imx_ccm_hdmi_enable(void) { struct ccm_softc *sc; uint32_t reg; sc = ccm_sc; reg = RD4(sc, CCM_CCGR2); reg |= CCGR2_HDMI_TX | CCGR2_HDMI_TX_ISFR; WR4(sc, CCM_CCGR2, reg); /* Set HDMI clock to 280MHz */ reg = RD4(sc, CCM_CHSCCDR); reg &= ~(CHSCCDR_IPU1_DI0_PRE_CLK_SEL_MASK | CHSCCDR_IPU1_DI0_PODF_MASK | CHSCCDR_IPU1_DI0_CLK_SEL_MASK); reg |= (CHSCCDR_PODF_DIVIDE_BY_3 << CHSCCDR_IPU1_DI0_PODF_SHIFT); reg |= (CHSCCDR_IPU_PRE_CLK_540M_PFD << CHSCCDR_IPU1_DI0_PRE_CLK_SEL_SHIFT); WR4(sc, CCM_CHSCCDR, reg); reg |= (CHSCCDR_CLK_SEL_LDB_DI0 << CHSCCDR_IPU1_DI0_CLK_SEL_SHIFT); WR4(sc, CCM_CHSCCDR, reg); } uint32_t imx_ccm_get_cacrr(void) { return (RD4(ccm_sc, CCM_CACCR)); } void imx_ccm_set_cacrr(uint32_t divisor) { WR4(ccm_sc, CCM_CACCR, divisor); } static device_method_t ccm_methods[] = { /* Device interface */ DEVMETHOD(device_probe, ccm_probe), DEVMETHOD(device_attach, ccm_attach), DEVMETHOD(device_detach, ccm_detach), DEVMETHOD_END }; static driver_t ccm_driver = { "ccm", ccm_methods, sizeof(struct ccm_softc) }; static devclass_t ccm_devclass; EARLY_DRIVER_MODULE(ccm, simplebus, ccm_driver, ccm_devclass, 0, 0, BUS_PASS_CPU + BUS_PASS_ORDER_EARLY); Index: head/sys/arm/freescale/imx/imx6_ccmreg.h =================================================================== --- head/sys/arm/freescale/imx/imx6_ccmreg.h (revision 329998) +++ head/sys/arm/freescale/imx/imx6_ccmreg.h (revision 329999) @@ -1,143 +1,149 @@ /*- * SPDX-License-Identifier: BSD-2-Clause-FreeBSD * * Copyright (c) 2013 Ian Lepore * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. * * $FreeBSD$ */ #ifndef IMX6_CCMREG_H #define IMX6_CCMREG_H #define CCM_CACCR 0x010 #define CCM_CBCDR 0x014 #define CBCDR_MMDC_CH1_AXI_PODF_SHIFT 3 #define CBCDR_MMDC_CH1_AXI_PODF_MASK (7 << 3) #define CCM_CSCMR1 0x01C #define SSI1_CLK_SEL_S 10 #define SSI2_CLK_SEL_S 12 #define SSI3_CLK_SEL_S 14 #define SSI_CLK_SEL_M 0x3 #define SSI_CLK_SEL_508_PFD 0 #define SSI_CLK_SEL_454_PFD 1 #define SSI_CLK_SEL_PLL4 2 #define CCM_CSCMR2 0x020 #define CSCMR2_LDB_DI0_IPU_DIV_SHIFT 10 #define CCM_CS1CDR 0x028 #define SSI1_CLK_PODF_SHIFT 0 #define SSI1_CLK_PRED_SHIFT 6 #define SSI3_CLK_PODF_SHIFT 16 #define SSI3_CLK_PRED_SHIFT 22 #define SSI_CLK_PODF_MASK 0x3f #define SSI_CLK_PRED_MASK 0x7 #define CCM_CS2CDR 0x02C #define SSI2_CLK_PODF_SHIFT 0 #define SSI2_CLK_PRED_SHIFT 6 #define LDB_DI0_CLK_SEL_SHIFT 9 #define LDB_DI0_CLK_SEL_MASK (3 << LDB_DI0_CLK_SEL_SHIFT) #define CCM_CHSCCDR 0x034 #define CHSCCDR_IPU1_DI0_PRE_CLK_SEL_MASK (0x7 << 6) #define CHSCCDR_IPU1_DI0_PRE_CLK_SEL_SHIFT 6 #define CHSCCDR_IPU1_DI0_PODF_MASK (0x7 << 3) #define CHSCCDR_IPU1_DI0_PODF_SHIFT 3 #define CHSCCDR_IPU1_DI0_CLK_SEL_MASK (0x7) #define CHSCCDR_IPU1_DI0_CLK_SEL_SHIFT 0 #define CHSCCDR_CLK_SEL_LDB_DI0 3 #define CHSCCDR_PODF_DIVIDE_BY_3 2 #define CHSCCDR_IPU_PRE_CLK_540M_PFD 5 #define CCM_CSCDR2 0x038 #define CCM_CLPCR 0x054 #define CCM_CLPCR_LPM_MASK 0x03 #define CCM_CLPCR_LPM_RUN 0x00 #define CCM_CLPCR_LPM_WAIT 0x01 #define CCM_CLPCR_LPM_STOP 0x02 #define CCM_CGPR 0x064 #define CCM_CGPR_INT_MEM_CLK_LPM (1 << 17) #define CCM_CCGR0 0x068 #define CCGR0_AIPS_TZ1 (0x3 << 0) #define CCGR0_AIPS_TZ2 (0x3 << 2) #define CCGR0_ABPHDMA (0x3 << 4) #define CCM_CCGR1 0x06C +#define CCGR1_ECSPI1 (0x3 << 0) +#define CCGR1_ECSPI2 (0x3 << 2) +#define CCGR1_ECSPI3 (0x3 << 4) +#define CCGR1_ECSPI4 (0x3 << 6) +#define CCGR1_ECSPI5 (0x3 << 8) #define CCGR1_ENET (0x3 << 10) #define CCGR1_EPIT1 (0x3 << 12) #define CCGR1_EPIT2 (0x3 << 14) +#define CCGR1_ESAI (0x3 << 16) #define CCGR1_GPT (0x3 << 20) #define CCGR1_GPT_SERIAL (0x3 << 22) #define CCM_CCGR2 0x070 #define CCGR2_HDMI_TX (0x3 << 0) #define CCGR2_HDMI_TX_ISFR (0x3 << 4) #define CCGR2_I2C1 (0x3 << 6) #define CCGR2_I2C2 (0x3 << 8) #define CCGR2_I2C3 (0x3 << 10) #define CCGR2_IIM (0x3 << 12) #define CCGR2_IOMUX_IPT (0x3 << 14) #define CCGR2_IPMUX1 (0x3 << 16) #define CCGR2_IPMUX2 (0x3 << 18) #define CCGR2_IPMUX3 (0x3 << 20) #define CCGR2_IPSYNC_IP2APB_TZASC1 (0x3 << 22) #define CCGR2_IPSYNC_IP2APB_TZASC2 (0x3 << 24) #define CCGR2_IPSYNC_VDOA (0x3 << 26) #define CCM_CCGR3 0x074 #define CCGR3_IPU1_IPU (0x3 << 0) #define CCGR3_IPU1_DI0 (0x3 << 2) #define CCGR3_IPU1_DI1 (0x3 << 4) #define CCGR3_IPU2_IPU (0x3 << 6) #define CCGR3_IPU2_DI0 (0x3 << 8) #define CCGR3_IPU2_DI1 (0x3 << 10) #define CCGR3_LDB_DI0 (0x3 << 12) #define CCGR3_LDB_DI1 (0x3 << 14) #define CCGR3_MMDC_CORE_ACLK_FAST (0x3 << 20) #define CCGR3_CG11 (0x3 << 22) #define CCGR3_MMDC_CORE_IPG (0x3 << 24) #define CCGR3_CG13 (0x3 << 26) #define CCGR3_OCRAM (0x3 << 28) #define CCM_CCGR4 0x078 #define CCGR4_PL301_MX6QFAST1_S133 (0x3 << 8) #define CCGR4_PL301_MX6QPER1_BCH (0x3 << 12) #define CCGR4_PL301_MX6QPER2_MAIN (0x3 << 14) #define CCM_CCGR5 0x07C #define CCGR5_SATA (0x3 << 4) #define CCGR5_SDMA (0x3 << 6) #define CCGR5_SSI1 (0x3 << 18) #define CCGR5_SSI2 (0x3 << 20) #define CCGR5_SSI3 (0x3 << 22) #define CCGR5_UART (0x3 << 24) #define CCGR5_UART_SERIAL (0x3 << 26) #define CCM_CCGR6 0x080 #define CCGR6_USBOH3 (0x3 << 0) #define CCGR6_USDHC1 (0x3 << 2) #define CCGR6_USDHC2 (0x3 << 4) #define CCGR6_USDHC3 (0x3 << 6) #define CCGR6_USDHC4 (0x3 << 8) #define CCM_CMEOR 0x088 #define CCM_ANALOG_PLL_ENET 0x000040e0 #define CCM_ANALOG_PLL_ENET_LOCK (1u << 31) #define CCM_ANALOG_PLL_ENET_ENABLE_100M (1u << 20) /* SATA */ #define CCM_ANALOG_PLL_ENET_BYPASS (1u << 16) #define CCM_ANALOG_PLL_ENET_ENABLE (1u << 13) /* Ether */ #define CCM_ANALOG_PLL_ENET_POWERDOWN (1u << 12) #endif Index: head/sys/arm/freescale/imx/imx_ccmvar.h =================================================================== --- head/sys/arm/freescale/imx/imx_ccmvar.h (revision 329998) +++ head/sys/arm/freescale/imx/imx_ccmvar.h (revision 329999) @@ -1,63 +1,64 @@ /*- * Copyright (c) 2014 Ian Lepore * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. * * $FreeBSD$ */ #ifndef IMX_CCMVAR_H #define IMX_CCMVAR_H /* * We need a clock management system that works across unrelated SoCs and * devices. For now, to keep imx development moving, define some barebones * functionality that can be shared within the imx family by having each SoC * implement functions with a common name. * * The usb enable functions are best-effort. They turn on the usb otg, host, * and phy clocks in a SoC-specific manner, but it may take a lot more than that * to make usb work on a given board. In particular, it can require specific * pinmux setup of gpio pins connected to external phy parts, voltage regulators * and overcurrent detectors, and so on. On such boards, u-boot or other early * board setup code has to handle those things. */ +uint32_t imx_ccm_ecspi_hz(void); uint32_t imx_ccm_ipg_hz(void); uint32_t imx_ccm_perclk_hz(void); uint32_t imx_ccm_sdhci_hz(void); uint32_t imx_ccm_uart_hz(void); uint32_t imx_ccm_ahb_hz(void); void imx_ccm_usb_enable(device_t _usbdev); void imx_ccm_usbphy_enable(device_t _phydev); void imx_ccm_ssi_configure(device_t _ssidev); void imx_ccm_hdmi_enable(void); void imx_ccm_ipu_enable(int ipu); int imx6_ccm_sata_enable(void); /* Routines to get and set the arm clock root divisor register. */ uint32_t imx_ccm_get_cacrr(void); void imx_ccm_set_cacrr(uint32_t _divisor); #endif Index: head/sys/arm/freescale/imx/imx_spi.c =================================================================== --- head/sys/arm/freescale/imx/imx_spi.c (nonexistent) +++ head/sys/arm/freescale/imx/imx_spi.c (revision 329999) @@ -0,0 +1,604 @@ +/*- + * SPDX-License-Identifier: BSD-2-Clause-FreeBSD + * + * Copyright (c) 2018 Ian Lepore + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + +#include +__FBSDID("$FreeBSD$"); + +/* + * Driver for imx Enhanced Configurable SPI; master-mode only. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +#include +#include +#include +#include +#include +#include + +#include "spibus_if.h" + +#define ECSPI_RXDATA 0x00 +#define ECSPI_TXDATA 0x04 +#define ECSPI_CTLREG 0x08 +#define CTLREG_BLEN_SHIFT 20 +#define CTLREG_BLEN_MASK 0x0fff +#define CTLREG_CSEL_SHIFT 18 +#define CTLREG_CSEL_MASK 0x03 +#define CTLREG_DRCTL_SHIFT 16 +#define CTLREG_DRCTL_MASK 0x03 +#define CTLREG_PREDIV_SHIFT 12 +#define CTLREG_PREDIV_MASK 0x0f +#define CTLREG_POSTDIV_SHIFT 8 +#define CTLREG_POSTDIV_MASK 0x0f +#define CTLREG_CMODE_SHIFT 4 +#define CTLREG_CMODE_MASK 0x0f +#define CTLREG_CMODES_MASTER (CTLREG_CMODE_MASK << CTLREG_CMODE_SHIFT) +#define CTLREG_SMC (1u << 3) +#define CTLREG_XCH (1u << 2) +#define CTLREG_HT (1u << 1) +#define CTLREG_EN (1u << 0) +#define ECSPI_CFGREG 0x0c +#define CFGREG_HTLEN_SHIFT 24 +#define CFGREG_SCLKCTL_SHIFT 20 +#define CFGREG_DATACTL_SHIFT 16 +#define CFGREG_SSPOL_SHIFT 12 +#define CFGREG_SSCTL_SHIFT 8 +#define CFGREG_SCLKPOL_SHIFT 4 +#define CFGREG_SCLKPHA_SHIFT 0 +#define CFGREG_MASK 0x0f /* all CFGREG fields are 4 bits */ +#define ECSPI_INTREG 0x10 +#define INTREG_TCEN (1u << 7) +#define INTREG_ROEN (1u << 6) +#define INTREG_RFEN (1u << 5) +#define INTREG_RDREN (1u << 4) +#define INTREG_RREN (1u << 3) +#define INTREG_TFEN (1u << 2) +#define INTREG_TDREN (1u << 1) +#define INTREG_TEEN (1u << 0) +#define ECSPI_DMAREG 0x14 +#define DMA_RX_THRESH_SHIFT 16 +#define DMA_RX_THRESH_MASK 0x3f +#define DMA_TX_THRESH_SHIFT 0 +#define DMA_TX_THRESH_MASK 0x3f +#define ECSPI_STATREG 0x18 +#define SREG_TC (1u << 7) +#define SREG_RO (1u << 6) +#define SREG_RF (1u << 5) +#define SREG_RDR (1u << 4) +#define SREG_RR (1u << 3) +#define SREG_TF (1u << 2) +#define SREG_TDR (1u << 1) +#define SREG_TE (1u << 0) +#define ECSPI_PERIODREG 0x1c +#define ECSPI_TESTREG 0x20 + +#define CS_MAX 4 /* Max number of chip selects. */ +#define CS_MASK 0x03 /* Mask flag bits out of chipsel. */ + +#define FIFO_SIZE 64 +#define FIFO_RXTHRESH 32 +#define FIFO_TXTHRESH 32 + +struct spi_softc { + device_t dev; + device_t spibus; + struct mtx mtx; + struct resource *memres; + struct resource *intres; + void *inthandle; + gpio_pin_t cspins[CS_MAX]; + u_int debug; + u_int basefreq; + uint32_t ctlreg; + uint32_t intreg; + uint32_t fifocnt; + uint8_t *rxbuf; + uint32_t rxidx; + uint32_t rxlen; + uint8_t *txbuf; + uint32_t txidx; + uint32_t txlen; +}; + +static struct ofw_compat_data compat_data[] = { + {"fsl,imx51-ecspi", true}, + {"fsl,imx53-ecspi", true}, + {"fsl,imx6dl-ecspi", true}, + {"fsl,imx6q-ecspi", true}, + {"fsl,imx6sx-ecspi", true}, + {"fsl,imx6ul-ecspi", true}, + {NULL, false} +}; + +static inline uint32_t +RD4(struct spi_softc *sc, bus_size_t offset) +{ + + return (bus_read_4(sc->memres, offset)); +} + +static inline void +WR4(struct spi_softc *sc, bus_size_t offset, uint32_t value) +{ + + bus_write_4(sc->memres, offset, value); +} + +static u_int +spi_calc_clockdiv(struct spi_softc *sc, u_int busfreq) +{ + u_int post, pre; + + /* Returning 0 effectively sets both dividers to 1. */ + if (sc->basefreq <= busfreq) + return (0); + + /* + * Brute-force this; all real-world bus speeds are going to be found on + * the 1st or 2nd time through this loop. + */ + for (post = 0; post < 16; ++post) { + pre = ((sc->basefreq >> post) / busfreq) - 1; + if (pre < 16) + break; + } + if (post == 16) { + /* The lowest we can go is ~115 Hz. */ + pre = 15; + post = 15; + } + + if (sc->debug >= 2) { + device_printf(sc->dev, + "base %u bus %u; pre %u, post %u; actual busfreq %u\n", + sc->basefreq, busfreq, pre, post, + (sc->basefreq / (pre + 1)) / (1 << post)); + } + + return (pre << CTLREG_PREDIV_SHIFT) | (post << CTLREG_POSTDIV_SHIFT); +} + +static void +spi_set_chipsel(struct spi_softc *sc, u_int cs, bool active) +{ + bool pinactive; + + /* + * This is kinda crazy... the gpio pins for chipsel are defined as + * active-high in the dts, but are supposed to be treated as active-low + * by this driver. So to turn on chipsel we have to invert the value + * passed to gpio_pin_set_active(). Then, to make it more fun, any + * slave can say its chipsel is active-high, so if that option is + * on, we have to invert the value again. + */ + pinactive = !active ^ (bool)(cs & SPIBUS_CS_HIGH); + + if (sc->debug >= 2) { + device_printf(sc->dev, "chipsel %u changed to %u\n", + (cs & ~SPIBUS_CS_HIGH), pinactive); + } + + /* + * Change the pin, then do a dummy read of its current state to ensure + * that the state change reaches the hardware before proceeding. + */ + gpio_pin_set_active(sc->cspins[cs & ~SPIBUS_CS_HIGH], pinactive); + gpio_pin_is_active(sc->cspins[cs & ~SPIBUS_CS_HIGH], &pinactive); +} + +static void +spi_hw_setup(struct spi_softc *sc, u_int cs, u_int mode, u_int freq) +{ + uint32_t reg; + + /* + * Set up control register, and write it first to bring the device out + * of reset. + */ + sc->ctlreg = CTLREG_EN | CTLREG_CMODES_MASTER | CTLREG_SMC; + sc->ctlreg |= spi_calc_clockdiv(sc, freq); + sc->ctlreg |= 7 << CTLREG_BLEN_SHIFT; /* XXX byte at a time */ + WR4(sc, ECSPI_CTLREG, sc->ctlreg); + + /* + * Set up the config register. Note that we do all transfers with the + * SPI hardware's chip-select set to zero. The actual chip select is + * handled with a gpio pin. + */ + reg = 0; + if (cs & SPIBUS_CS_HIGH) + reg |= 1u << CFGREG_SSPOL_SHIFT; + if (mode & SPIBUS_MODE_CPHA) + reg |= 1u << CFGREG_SCLKPHA_SHIFT; + if (mode & SPIBUS_MODE_CPOL) { + reg |= 1u << CFGREG_SCLKPOL_SHIFT; + reg |= 1u << CFGREG_SCLKCTL_SHIFT; + } + WR4(sc, ECSPI_CFGREG, reg); + + /* + * Set up the rx/tx FIFO interrupt thresholds. + */ + reg = (FIFO_RXTHRESH << DMA_RX_THRESH_SHIFT); + reg |= (FIFO_TXTHRESH << DMA_TX_THRESH_SHIFT); + WR4(sc, ECSPI_DMAREG, reg); + + /* + * Do a dummy read, to make sure the preceding writes reach the spi + * hardware before we assert any gpio chip select. + */ + (void)RD4(sc, ECSPI_CFGREG); +} + +static void +spi_empty_rxfifo(struct spi_softc *sc) +{ + + while (sc->rxidx < sc->rxlen && (RD4(sc, ECSPI_STATREG) & SREG_RR)) { + sc->rxbuf[sc->rxidx++] = (uint8_t)RD4(sc, ECSPI_RXDATA); + --sc->fifocnt; + } +} + +static void +spi_fill_txfifo(struct spi_softc *sc) +{ + + while (sc->txidx < sc->txlen && sc->fifocnt < FIFO_SIZE) { + WR4(sc, ECSPI_TXDATA, sc->txbuf[sc->txidx++]); + ++sc->fifocnt; + } + + /* + * If we're out of data, disable tx data ready (threshold) interrupts, + * and enable tx fifo empty interrupts. + */ + if (sc->txidx == sc->txlen) + sc->intreg = (sc->intreg & ~INTREG_TDREN) | INTREG_TEEN; +} + +static void +spi_intr(void *arg) +{ + struct spi_softc *sc = arg; + uint32_t intreg, status; + + mtx_lock(&sc->mtx); + + sc = arg; + intreg = sc->intreg; + status = RD4(sc, ECSPI_STATREG); + WR4(sc, ECSPI_STATREG, status); /* Clear w1c bits. */ + + /* + * If we get an overflow error, just signal that the transfer is done + * and wakeup the waiting thread, which will see that txidx != txlen and + * return an IO error to the caller. + */ + if (__predict_false(status & SREG_RO)) { + if (sc->debug || bootverbose) { + device_printf(sc->dev, "rxoverflow rxidx %u txidx %u\n", + sc->rxidx, sc->txidx); + } + sc->intreg = 0; + wakeup(sc); + mtx_unlock(&sc->mtx); + return; + } + + if (status & SREG_RR) + spi_empty_rxfifo(sc); + + if (status & SREG_TDR) + spi_fill_txfifo(sc); + + /* + * If we're out of bytes to send... + * - If Transfer Complete is set (shift register is empty) and we've + * received everything we expect, we're all done. + * - Else if Tx Fifo Empty is set, we need to stop waiting for that and + * switch to waiting for Transfer Complete (wait for shift register + * to empty out), and also for Receive Ready (last of incoming data). + */ + if (sc->txidx == sc->txlen) { + if ((status & SREG_TC) && sc->fifocnt == 0) { + sc->intreg = 0; + wakeup(sc); + } else if (status & SREG_TE) { + sc->intreg &= ~(sc->intreg & ~INTREG_TEEN); + sc->intreg |= INTREG_TCEN | INTREG_RREN; + } + } + + /* + * If interrupt flags changed, write the new flags to the hardware and + * do a dummy readback to ensure the changes reach the hardware before + * we exit the isr. + */ + if (sc->intreg != intreg) { + WR4(sc, ECSPI_INTREG, sc->intreg); + (void)RD4(sc, ECSPI_INTREG); + } + + if (sc->debug >= 3) { + device_printf(sc->dev, + "spi_intr, sreg 0x%08x intreg was 0x%08x now 0x%08x\n", + status, intreg, sc->intreg); + } + + mtx_unlock(&sc->mtx); +} + +static int +spi_xfer_buf(struct spi_softc *sc, void *rxbuf, void *txbuf, uint32_t len) +{ + int err; + + if (sc->debug >= 1) { + device_printf(sc->dev, + "spi_xfer_buf, rxbuf %p txbuf %p len %u\n", + rxbuf, txbuf, len); + } + + if (len == 0) + return (0); + + sc->rxbuf = rxbuf; + sc->rxlen = len; + sc->rxidx = 0; + sc->txbuf = txbuf; + sc->txlen = len; + sc->txidx = 0; + sc->intreg = INTREG_RDREN | INTREG_TDREN; + spi_fill_txfifo(sc); + + /* Enable interrupts last; spi_fill_txfifo() can change sc->intreg */ + WR4(sc, ECSPI_INTREG, sc->intreg); + + err = 0; + while (err == 0 && sc->intreg != 0) + err = msleep(sc, &sc->mtx, 0, "imxspi", 10 * hz); + + if (sc->rxidx != sc->rxlen || sc->txidx != sc->txlen) + err = EIO; + + return (err); +} + +static int +spi_transfer(device_t dev, device_t child, struct spi_command *cmd) +{ + struct spi_softc *sc = device_get_softc(dev); + uint32_t cs, mode, clock; + int err; + + spibus_get_cs(child, &cs); + spibus_get_clock(child, &clock); + spibus_get_mode(child, &mode); + + if (cs > CS_MAX || sc->cspins[cs] == NULL) { + if (sc->debug || bootverbose) + device_printf(sc->dev, "Invalid chip select %u\n", cs); + return (EINVAL); + } + + mtx_lock(&sc->mtx); + + if (sc->debug >= 1) { + device_printf(sc->dev, + "spi_transfer, cs 0x%x clock %u mode %u\n", + cs, clock, mode); + } + + /* Set up the hardware and select the device. */ + spi_hw_setup(sc, cs, mode, clock); + spi_set_chipsel(sc, cs, true); + + /* Transfer command then data bytes. */ + err = 0; + if (cmd->tx_cmd_sz > 0) + err = spi_xfer_buf(sc, cmd->rx_cmd, cmd->tx_cmd, + cmd->tx_cmd_sz); + if (cmd->tx_data_sz > 0 && err == 0) + err = spi_xfer_buf(sc, cmd->rx_data, cmd->tx_data, + cmd->tx_data_sz); + + /* Deselect the device, turn off (and reset) hardware. */ + spi_set_chipsel(sc, cs, false); + WR4(sc, ECSPI_CTLREG, 0); + + mtx_unlock(&sc->mtx); + + return (err); +} + +static phandle_t +spi_get_node(device_t bus, device_t dev) +{ + + /* + * Share our controller node with our spibus child; it instantiates + * devices by walking the children contained within our node. + */ + return ofw_bus_get_node(bus); +} + +static int +spi_detach(device_t dev) +{ + struct spi_softc *sc = device_get_softc(dev); + int idx; + + mtx_lock(&sc->mtx); + + bus_generic_detach(sc->dev); + if (sc->spibus != NULL) + device_delete_child(dev, sc->spibus); + + for (idx = 0; idx < nitems(sc->cspins); ++idx) { + if (sc->cspins[idx] != NULL) + gpio_pin_release(sc->cspins[idx]); + } + + if (sc->inthandle != NULL) + bus_teardown_intr(sc->dev, sc->intres, sc->inthandle); + if (sc->intres != NULL) + bus_release_resource(sc->dev, SYS_RES_IRQ, 0, sc->intres); + if (sc->memres != NULL) + bus_release_resource(sc->dev, SYS_RES_MEMORY, 0, sc->memres); + + mtx_unlock(&sc->mtx); + mtx_destroy(&sc->mtx); + + return (0); +} + +static int +spi_attach(device_t dev) +{ + struct spi_softc *sc = device_get_softc(dev); + phandle_t node; + int err, idx, rid; + + sc->dev = dev; + sc->basefreq = imx_ccm_ecspi_hz(); + + mtx_init(&sc->mtx, device_get_nameunit(dev), NULL, MTX_DEF); + + /* Set up debug-enable sysctl. */ + SYSCTL_ADD_INT(device_get_sysctl_ctx(sc->dev), + SYSCTL_CHILDREN(device_get_sysctl_tree(sc->dev)), + OID_AUTO, "debug", CTLFLAG_RWTUN, &sc->debug, 0, + "Enable debug, higher values = more info"); + + /* Allocate mmio register access resources. */ + rid = 0; + sc->memres = bus_alloc_resource_any(sc->dev, SYS_RES_MEMORY, &rid, + RF_ACTIVE); + if (sc->memres == NULL) { + device_printf(sc->dev, "could not allocate registers\n"); + spi_detach(sc->dev); + return (ENXIO); + } + + /* Allocate interrupt resources and set up handler. */ + rid = 0; + sc->intres = bus_alloc_resource_any(sc->dev, SYS_RES_IRQ, &rid, + RF_ACTIVE); + if (sc->intres == NULL) { + device_printf(sc->dev, "could not allocate interrupt\n"); + device_detach(sc->dev); + return (ENXIO); + } + err = bus_setup_intr(sc->dev, sc->intres, INTR_TYPE_MISC | INTR_MPSAFE, + NULL, spi_intr, sc, &sc->inthandle); + if (err != 0) { + device_printf(sc->dev, "could not setup interrupt handler"); + device_detach(sc->dev); + return (ENXIO); + } + + /* Allocate gpio pins for configured chip selects. */ + node = ofw_bus_get_node(sc->dev); + for (err = 0, idx = 0; err == 0 && idx < nitems(sc->cspins); ++idx) { + err = gpio_pin_get_by_ofw_propidx(sc->dev, node, "cs-gpios", + idx, &sc->cspins[idx]); + if (err == 0) { + gpio_pin_setflags(sc->cspins[idx], GPIO_PIN_OUTPUT); + } else if (sc->debug >= 2) { + device_printf(sc->dev, + "cannot configure gpio for chip select %u\n", idx); + } + } + + /* + * Hardware init: put all channels into Master mode, turn off the enable + * bit (gates off clocks); we only enable the hardware while xfers run. + */ + WR4(sc, ECSPI_CTLREG, CTLREG_CMODES_MASTER); + + /* Attach the bus driver. */ + sc->spibus = device_add_child(dev, "spibus", -1); + return (bus_generic_attach(sc->dev)); +} + +static int +spi_probe(device_t dev) +{ + + if (!ofw_bus_status_okay(dev)) + return (ENXIO); + + if (!ofw_bus_search_compatible(dev, compat_data)->ocd_data) + return (ENXIO); + + device_set_desc(dev, "i.MX ECSPI Master"); + return (BUS_PROBE_DEFAULT); +} + +static device_method_t spi_methods[] = { + DEVMETHOD(device_probe, spi_probe), + DEVMETHOD(device_attach, spi_attach), + DEVMETHOD(device_detach, spi_detach), + + /* spibus_if */ + DEVMETHOD(spibus_transfer, spi_transfer), + + /* ofw_bus_if */ + DEVMETHOD(ofw_bus_get_node, spi_get_node), + + DEVMETHOD_END +}; + +static driver_t spi_driver = { + "imx_spi", + spi_methods, + sizeof(struct spi_softc), +}; + +static devclass_t spi_devclass; + +DRIVER_MODULE(imx_spi, simplebus, spi_driver, spi_devclass, 0, 0); +DRIVER_MODULE(ofw_spibus, imx_spi, ofw_spibus_driver, ofw_spibus_devclass, 0, 0); +MODULE_DEPEND(imx_spi, ofw_spibus, 1, 1, 1); Property changes on: head/sys/arm/freescale/imx/imx_spi.c ___________________________________________________________________ Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:keywords ## -0,0 +1 ## +FreeBSD=%H \ No newline at end of property Added: svn:mime-type ## -0,0 +1 ## +text/plain \ No newline at end of property Index: head/sys/modules/imx/Makefile =================================================================== --- head/sys/modules/imx/Makefile (revision 329998) +++ head/sys/modules/imx/Makefile (revision 329999) @@ -1,8 +1,9 @@ # $FreeBSD$ # Build modules specific to freescale/nxp imx-family SoCs. SUBDIR = \ ../ffec \ imx_i2c \ + imx_spi \ .include Index: head/sys/modules/imx/imx_spi/Makefile =================================================================== --- head/sys/modules/imx/imx_spi/Makefile (nonexistent) +++ head/sys/modules/imx/imx_spi/Makefile (revision 329999) @@ -0,0 +1,16 @@ +# $FreeBSD$ + +.PATH: ${SRCTOP}/sys/arm/freescale/imx + +KMOD= imx_spi +SRCS= imx_spi.c + +# Generated files... +SRCS+= \ + bus_if.h \ + device_if.h \ + ofw_bus_if.h \ + opt_platform.h \ + spibus_if.h \ + +.include Property changes on: head/sys/modules/imx/imx_spi/Makefile ___________________________________________________________________ Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:keywords ## -0,0 +1 ## +FreeBSD=%H \ No newline at end of property Added: svn:mime-type ## -0,0 +1 ## +text/plain \ No newline at end of property