Index: head/share/man/man4/bwn.4 =================================================================== --- head/share/man/man4/bwn.4 (revision 328911) +++ head/share/man/man4/bwn.4 (revision 328912) @@ -1,159 +1,171 @@ .\" Copyright (c) 2009 Christian Brueffer .\" All rights reserved. .\" .\" Redistribution and use in source and binary forms, with or without .\" modification, are permitted provided that the following conditions .\" are met: .\" 1. Redistributions of source code must retain the above copyright .\" notice, this list of conditions and the following disclaimer. .\" 2. Redistributions in binary form must reproduce the above copyright .\" notice, this list of conditions and the following disclaimer in the .\" documentation and/or other materials provided with the distribution. .\" .\" THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND .\" ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE .\" IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE .\" ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE .\" FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL .\" DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS .\" OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) .\" HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT .\" LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY .\" OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF .\" SUCH DAMAGE. .\" .\" $FreeBSD$ .\" -.Dd June 11, 2015 +.Dd December 16, 2017 .Dt BWN 4 .Os .Sh NAME .Nm bwn -.Nd Broadcom BCM43xx IEEE 802.11b/g wireless network driver +.Nd Broadcom BCM43xx SoftMAC IEEE 802.11 wireless network driver .Sh SYNOPSIS -To compile this driver into the kernel, -place the following lines in your -kernel configuration file: +To compile this driver into the kernel, add the following lines to the kernel +configuration file: .Bd -ragged -offset indent -.Cd "device siba_bwn" .Cd "device bwn" +.Cd "device bhnd" +.Cd "device bhndb" +.Cd "device bhndb_pci" +.Cd "device bcma" +.Cd "device siba" +.Cd "device gpio" .Cd "device wlan" .Cd "device wlan_amrr" .Cd "device firmware" .Ed .Pp -Alternatively, to load the driver as a -module at boot time, place the following line in +To load the driver as a module at boot, add the following lines to .Xr loader.conf 5 : .Bd -literal -offset indent if_bwn_load="YES" .Ed .Sh DESCRIPTION The .Nm driver provides support for Broadcom BCM43xx based PCI/CardBus network adapters. .Pp It supports .Cm station and .Cm monitor mode operation. Only one virtual interface may be configured at any time. For more information on configuring this device, see .Xr ifconfig 8 . .Pp This driver requires firmware to be loaded before it will work. The .Pa ports/net/bwn-firmware-kmod port needs to be installed before .Xr ifconfig 8 will work. In most cases the .Pa bwn_v4_ucode kernel module from the port should be used. However, if an LP (low power) PHY is being used, the .Pa bwn_v4_lp_ucode module should be used. .Sh HARDWARE The .Nm driver supports Broadcom BCM43xx based wireless devices, including: .Bl -column "Apple Airport Extreme" "BCM4306" "Mini PCI" "a/b/g" .It Em "Card" Ta Em "Chip" Ta Em "Bus" Ta Em "Standard" .It "Apple Airport Extreme BCM4318 PCI b/g" .It "ASUS WL-138g BCM4318 PCI b/g" .It "Buffalo WLI-CB-G54S BCM4318 CardBus b/g" .It "Dell Wireless 1390 BCM4311 Mini PCI b/g" .It "Dell Wireless 1470 BCM4318 Mini PCI b/g" .It "Dell Truemobile 1400 BCM4309 Mini PCI b/g" .It "HP Compaq 6715b BCM4312 PCI b/g" .It "HP nx6125 BCM4319 PCI b/g" .It "Linksys WPC54G Ver 3 BCM4318 CardBus b/g" .It "Linksys WPC54GS Ver 2 BCM4318 CardBus b/g" .It "US Robotics 5411 BCM4318 CardBus b/g" .El .Pp Users of older Broadcom chipsets (BCM4301, BCM4303 and BCM4306 rev 2) must use .Xr bwi 4 because the v4 version of the firmware does not support these chips. The newer firmware is too big to fit into these old chips. .Sh EXAMPLES Join an existing BSS network (i.e., connect to an access point): .Bd -literal -offset indent ifconfig wlan create wlandev bwn0 inet 192.168.0.20 \e netmask 0xffffff00 .Ed .Pp Join a specific BSS network with network name .Dq Li my_net : .Pp .Dl "ifconfig wlan create wlandev bwn0 ssid my_net up" .Pp Join a specific BSS network with 64-bit WEP encryption: .Bd -literal -offset indent ifconfig wlan create wlandev bwn0 ssid my_net \e wepmode on wepkey 0x1234567890 weptxkey 1 up .Ed .Sh LOADER TUNABLES Tunables can be set at the .Xr loader 8 prompt before booting the kernel or stored in .Xr loader.conf 5 . .Bl -tag -width indent -.It Va hw.bwn.msi_disable -This tunable disables MSI support on the hardware. -The default value is 0. .It Va hw.bwn.usedma This tunable enables DMA operations on the hardware. If the value is 0, PIO mode would be used. The default value is 1. .El .Sh SEE ALSO .Xr arp 4 , +.Xr bcma 4 , +.Xr bhnd 4 , +.Xr bhndb 4 , .Xr bwi 4 , .Xr cardbus 4 , .Xr intro 4 , .Xr pci 4 , +.Xr siba 4 , .Xr wlan 4 , .Xr wlan_amrr 4 , .Xr ifconfig 8 , .Xr wpa_supplicant 8 .Sh HISTORY The .Nm driver first appeared in .Fx 8.1 . +The driver was updated to support the common Broadcom +.Xr bhnd 4 +bus interface in +.Fx 12.0 . .Sh AUTHORS .An -nosplit The .Nm driver was written by .An Weongyo Jeong Aq Mt weongyo@FreeBSD.org . +Support for +.Xr bhnd 4 +was added by +.An Landon Fuller Aq Mt landonf@FreeBSD.org . .\".Sh BUGS .\"Some card based on the BCM4306 and BCM4309 chips do not work properly .\"on channel 1, 2 and 3. .Sh CAVEATS Some LP PHY devices have DMA operation problems that in that case try to use PIO mode. Index: head/sys/conf/files =================================================================== --- head/sys/conf/files (revision 328911) +++ head/sys/conf/files (revision 328912) @@ -1,4874 +1,4869 @@ # $FreeBSD$ # # The long compile-with and dependency lines are required because of # limitations in config: backslash-newline doesn't work in strings, and # dependency lines other than the first are silently ignored. # acpi_quirks.h optional acpi \ dependency "$S/tools/acpi_quirks2h.awk $S/dev/acpica/acpi_quirks" \ compile-with "${AWK} -f $S/tools/acpi_quirks2h.awk $S/dev/acpica/acpi_quirks" \ no-obj no-implicit-rule before-depend \ clean "acpi_quirks.h" bhnd_nvram_map.h optional bhnd \ dependency "$S/dev/bhnd/tools/nvram_map_gen.sh $S/dev/bhnd/tools/nvram_map_gen.awk $S/dev/bhnd/nvram/nvram_map" \ compile-with "sh $S/dev/bhnd/tools/nvram_map_gen.sh $S/dev/bhnd/nvram/nvram_map -h" \ no-obj no-implicit-rule before-depend \ clean "bhnd_nvram_map.h" bhnd_nvram_map_data.h optional bhnd \ dependency "$S/dev/bhnd/tools/nvram_map_gen.sh $S/dev/bhnd/tools/nvram_map_gen.awk $S/dev/bhnd/nvram/nvram_map" \ compile-with "sh $S/dev/bhnd/tools/nvram_map_gen.sh $S/dev/bhnd/nvram/nvram_map -d" \ no-obj no-implicit-rule before-depend \ clean "bhnd_nvram_map_data.h" # # The 'fdt_dtb_file' target covers an actual DTB file name, which is derived # from the specified source (DTS) file: .dts -> .dtb # fdt_dtb_file optional fdt fdt_dtb_static \ compile-with "sh -c 'MACHINE=${MACHINE} $S/tools/fdt/make_dtb.sh $S ${FDT_DTS_FILE} ${.CURDIR}'" \ no-obj no-implicit-rule before-depend \ clean "${FDT_DTS_FILE:R}.dtb" fdt_static_dtb.h optional fdt fdt_dtb_static \ compile-with "sh -c 'MACHINE=${MACHINE} $S/tools/fdt/make_dtbh.sh ${FDT_DTS_FILE} ${.CURDIR}'" \ dependency "fdt_dtb_file" \ no-obj no-implicit-rule before-depend \ clean "fdt_static_dtb.h" feeder_eq_gen.h optional sound \ dependency "$S/tools/sound/feeder_eq_mkfilter.awk" \ compile-with "${AWK} -f $S/tools/sound/feeder_eq_mkfilter.awk -- ${FEEDER_EQ_PRESETS} > feeder_eq_gen.h" \ no-obj no-implicit-rule before-depend \ clean "feeder_eq_gen.h" feeder_rate_gen.h optional sound \ dependency "$S/tools/sound/feeder_rate_mkfilter.awk" \ compile-with "${AWK} -f $S/tools/sound/feeder_rate_mkfilter.awk -- ${FEEDER_RATE_PRESETS} > feeder_rate_gen.h" \ no-obj no-implicit-rule before-depend \ clean "feeder_rate_gen.h" snd_fxdiv_gen.h optional sound \ dependency "$S/tools/sound/snd_fxdiv_gen.awk" \ compile-with "${AWK} -f $S/tools/sound/snd_fxdiv_gen.awk -- > snd_fxdiv_gen.h" \ no-obj no-implicit-rule before-depend \ clean "snd_fxdiv_gen.h" miidevs.h optional miibus | mii \ dependency "$S/tools/miidevs2h.awk $S/dev/mii/miidevs" \ compile-with "${AWK} -f $S/tools/miidevs2h.awk $S/dev/mii/miidevs" \ no-obj no-implicit-rule before-depend \ clean "miidevs.h" pccarddevs.h standard \ dependency "$S/tools/pccarddevs2h.awk $S/dev/pccard/pccarddevs" \ compile-with "${AWK} -f $S/tools/pccarddevs2h.awk $S/dev/pccard/pccarddevs" \ no-obj no-implicit-rule before-depend \ clean "pccarddevs.h" kbdmuxmap.h optional kbdmux_dflt_keymap \ compile-with "kbdcontrol -P ${S:S/sys$/share/}/vt/keymaps -P ${S:S/sys$/share/}/syscons/keymaps -L ${KBDMUX_DFLT_KEYMAP} | sed -e 's/^static keymap_t.* = /static keymap_t key_map = /' -e 's/^static accentmap_t.* = /static accentmap_t accent_map = /' > kbdmuxmap.h" \ no-obj no-implicit-rule before-depend \ clean "kbdmuxmap.h" teken_state.h optional sc | vt \ dependency "$S/teken/gensequences $S/teken/sequences" \ compile-with "${AWK} -f $S/teken/gensequences $S/teken/sequences > teken_state.h" \ no-obj no-implicit-rule before-depend \ clean "teken_state.h" usbdevs.h optional usb \ dependency "$S/tools/usbdevs2h.awk $S/dev/usb/usbdevs" \ compile-with "${AWK} -f $S/tools/usbdevs2h.awk $S/dev/usb/usbdevs -h" \ no-obj no-implicit-rule before-depend \ clean "usbdevs.h" usbdevs_data.h optional usb \ dependency "$S/tools/usbdevs2h.awk $S/dev/usb/usbdevs" \ compile-with "${AWK} -f $S/tools/usbdevs2h.awk $S/dev/usb/usbdevs -d" \ no-obj no-implicit-rule before-depend \ clean "usbdevs_data.h" cam/cam.c optional scbus cam/cam_compat.c optional scbus cam/cam_iosched.c optional scbus cam/cam_periph.c optional scbus cam/cam_queue.c optional scbus cam/cam_sim.c optional scbus cam/cam_xpt.c optional scbus cam/ata/ata_all.c optional scbus cam/ata/ata_xpt.c optional scbus cam/ata/ata_pmp.c optional scbus cam/nvme/nvme_all.c optional scbus nvme cam/nvme/nvme_da.c optional scbus nvme da cam/nvme/nvme_xpt.c optional scbus nvme cam/scsi/scsi_xpt.c optional scbus cam/scsi/scsi_all.c optional scbus cam/scsi/scsi_cd.c optional cd cam/scsi/scsi_ch.c optional ch cam/ata/ata_da.c optional ada | da cam/ctl/ctl.c optional ctl cam/ctl/ctl_backend.c optional ctl cam/ctl/ctl_backend_block.c optional ctl cam/ctl/ctl_backend_ramdisk.c optional ctl cam/ctl/ctl_cmd_table.c optional ctl cam/ctl/ctl_frontend.c optional ctl cam/ctl/ctl_frontend_cam_sim.c optional ctl cam/ctl/ctl_frontend_ioctl.c optional ctl cam/ctl/ctl_frontend_iscsi.c optional ctl cfiscsi cam/ctl/ctl_ha.c optional ctl cam/ctl/ctl_scsi_all.c optional ctl cam/ctl/ctl_tpc.c optional ctl cam/ctl/ctl_tpc_local.c optional ctl cam/ctl/ctl_error.c optional ctl cam/ctl/ctl_util.c optional ctl cam/ctl/scsi_ctl.c optional ctl cam/mmc/mmc_xpt.c optional scbus mmccam cam/mmc/mmc_da.c optional scbus mmccam da cam/scsi/scsi_da.c optional da cam/scsi/scsi_low.c optional ncv | nsp | stg cam/scsi/scsi_pass.c optional pass cam/scsi/scsi_pt.c optional pt cam/scsi/scsi_sa.c optional sa cam/scsi/scsi_enc.c optional ses cam/scsi/scsi_enc_ses.c optional ses cam/scsi/scsi_enc_safte.c optional ses cam/scsi/scsi_sg.c optional sg cam/scsi/scsi_targ_bh.c optional targbh cam/scsi/scsi_target.c optional targ cam/scsi/smp_all.c optional scbus # shared between zfs and dtrace cddl/compat/opensolaris/kern/opensolaris.c optional zfs | dtrace compile-with "${CDDL_C}" cddl/compat/opensolaris/kern/opensolaris_cmn_err.c optional zfs | dtrace compile-with "${CDDL_C}" cddl/compat/opensolaris/kern/opensolaris_kmem.c optional zfs | dtrace compile-with "${CDDL_C}" cddl/compat/opensolaris/kern/opensolaris_misc.c optional zfs | dtrace compile-with "${CDDL_C}" cddl/compat/opensolaris/kern/opensolaris_proc.c optional zfs | dtrace compile-with "${CDDL_C}" cddl/compat/opensolaris/kern/opensolaris_sunddi.c optional zfs | dtrace compile-with "${CDDL_C}" cddl/compat/opensolaris/kern/opensolaris_taskq.c optional zfs | dtrace compile-with "${CDDL_C}" # zfs specific cddl/compat/opensolaris/kern/opensolaris_acl.c optional zfs compile-with "${ZFS_C}" cddl/compat/opensolaris/kern/opensolaris_dtrace.c optional zfs compile-with "${ZFS_C}" cddl/compat/opensolaris/kern/opensolaris_kobj.c optional zfs compile-with "${ZFS_C}" cddl/compat/opensolaris/kern/opensolaris_kstat.c optional zfs compile-with "${ZFS_C}" cddl/compat/opensolaris/kern/opensolaris_lookup.c optional zfs compile-with "${ZFS_C}" cddl/compat/opensolaris/kern/opensolaris_policy.c optional zfs compile-with "${ZFS_C}" cddl/compat/opensolaris/kern/opensolaris_string.c optional zfs compile-with "${ZFS_C}" cddl/compat/opensolaris/kern/opensolaris_sysevent.c optional zfs compile-with "${ZFS_C}" cddl/compat/opensolaris/kern/opensolaris_uio.c optional zfs compile-with "${ZFS_C}" cddl/compat/opensolaris/kern/opensolaris_vfs.c optional zfs compile-with "${ZFS_C}" cddl/compat/opensolaris/kern/opensolaris_vm.c optional zfs compile-with "${ZFS_C}" cddl/compat/opensolaris/kern/opensolaris_zone.c optional zfs compile-with "${ZFS_C}" cddl/contrib/opensolaris/common/acl/acl_common.c optional zfs compile-with "${ZFS_C}" cddl/contrib/opensolaris/common/avl/avl.c optional zfs compile-with "${ZFS_C}" cddl/contrib/opensolaris/common/nvpair/opensolaris_fnvpair.c optional zfs compile-with "${ZFS_C}" cddl/contrib/opensolaris/common/nvpair/opensolaris_nvpair.c optional zfs compile-with "${ZFS_C}" cddl/contrib/opensolaris/common/nvpair/opensolaris_nvpair_alloc_fixed.c optional zfs compile-with "${ZFS_C}" cddl/contrib/opensolaris/common/unicode/u8_textprep.c optional zfs compile-with "${ZFS_C}" cddl/contrib/opensolaris/common/zfs/zfeature_common.c optional zfs compile-with "${ZFS_C}" cddl/contrib/opensolaris/common/zfs/zfs_comutil.c optional zfs compile-with "${ZFS_C}" cddl/contrib/opensolaris/common/zfs/zfs_deleg.c optional zfs compile-with "${ZFS_C}" cddl/contrib/opensolaris/common/zfs/zfs_fletcher.c optional zfs compile-with "${ZFS_C}" cddl/contrib/opensolaris/common/zfs/zfs_ioctl_compat.c optional zfs compile-with "${ZFS_C}" cddl/contrib/opensolaris/common/zfs/zfs_namecheck.c optional zfs compile-with "${ZFS_C}" cddl/contrib/opensolaris/common/zfs/zfs_prop.c optional zfs compile-with "${ZFS_C}" cddl/contrib/opensolaris/common/zfs/zpool_prop.c optional zfs compile-with "${ZFS_C}" cddl/contrib/opensolaris/common/zfs/zprop_common.c optional zfs compile-with "${ZFS_C}" cddl/contrib/opensolaris/uts/common/fs/vnode.c optional zfs compile-with "${ZFS_C}" cddl/contrib/opensolaris/uts/common/fs/zfs/abd.c optional zfs compile-with "${ZFS_C}" cddl/contrib/opensolaris/uts/common/fs/zfs/arc.c optional zfs compile-with "${ZFS_C}" cddl/contrib/opensolaris/uts/common/fs/zfs/blkptr.c optional zfs compile-with "${ZFS_C}" cddl/contrib/opensolaris/uts/common/fs/zfs/bplist.c optional zfs compile-with "${ZFS_C}" cddl/contrib/opensolaris/uts/common/fs/zfs/bpobj.c optional zfs compile-with "${ZFS_C}" cddl/contrib/opensolaris/uts/common/fs/zfs/bptree.c optional zfs compile-with "${ZFS_C}" cddl/contrib/opensolaris/uts/common/fs/zfs/bqueue.c optional zfs compile-with "${ZFS_C}" cddl/contrib/opensolaris/uts/common/fs/zfs/dbuf.c optional zfs compile-with "${ZFS_C}" cddl/contrib/opensolaris/uts/common/fs/zfs/ddt.c optional zfs compile-with "${ZFS_C}" cddl/contrib/opensolaris/uts/common/fs/zfs/ddt_zap.c optional zfs compile-with "${ZFS_C}" cddl/contrib/opensolaris/uts/common/fs/zfs/dmu.c optional zfs compile-with "${ZFS_C}" cddl/contrib/opensolaris/uts/common/fs/zfs/dmu_diff.c optional zfs compile-with "${ZFS_C}" cddl/contrib/opensolaris/uts/common/fs/zfs/dmu_object.c optional zfs compile-with "${ZFS_C}" cddl/contrib/opensolaris/uts/common/fs/zfs/dmu_objset.c optional zfs compile-with "${ZFS_C}" cddl/contrib/opensolaris/uts/common/fs/zfs/dmu_send.c optional zfs compile-with "${ZFS_C}" cddl/contrib/opensolaris/uts/common/fs/zfs/dmu_traverse.c optional zfs compile-with "${ZFS_C}" cddl/contrib/opensolaris/uts/common/fs/zfs/dmu_tx.c optional zfs compile-with "${ZFS_C}" cddl/contrib/opensolaris/uts/common/fs/zfs/dmu_zfetch.c optional zfs compile-with "${ZFS_C}" cddl/contrib/opensolaris/uts/common/fs/zfs/dnode.c optional zfs compile-with "${ZFS_C}" \ warning "kernel contains CDDL licensed ZFS filesystem" cddl/contrib/opensolaris/uts/common/fs/zfs/dnode_sync.c optional zfs compile-with "${ZFS_C}" cddl/contrib/opensolaris/uts/common/fs/zfs/dsl_bookmark.c optional zfs compile-with "${ZFS_C}" cddl/contrib/opensolaris/uts/common/fs/zfs/dsl_dataset.c optional zfs compile-with "${ZFS_C}" cddl/contrib/opensolaris/uts/common/fs/zfs/dsl_deadlist.c optional zfs compile-with "${ZFS_C}" cddl/contrib/opensolaris/uts/common/fs/zfs/dsl_deleg.c optional zfs compile-with "${ZFS_C}" cddl/contrib/opensolaris/uts/common/fs/zfs/dsl_destroy.c optional zfs compile-with "${ZFS_C}" cddl/contrib/opensolaris/uts/common/fs/zfs/dsl_dir.c optional zfs compile-with "${ZFS_C}" cddl/contrib/opensolaris/uts/common/fs/zfs/dsl_pool.c optional zfs compile-with "${ZFS_C}" cddl/contrib/opensolaris/uts/common/fs/zfs/dsl_prop.c optional zfs compile-with "${ZFS_C}" cddl/contrib/opensolaris/uts/common/fs/zfs/dsl_scan.c optional zfs compile-with "${ZFS_C}" cddl/contrib/opensolaris/uts/common/fs/zfs/dsl_userhold.c optional zfs compile-with "${ZFS_C}" cddl/contrib/opensolaris/uts/common/fs/zfs/dsl_synctask.c optional zfs compile-with "${ZFS_C}" cddl/contrib/opensolaris/uts/common/fs/zfs/gzip.c optional zfs compile-with "${ZFS_C}" cddl/contrib/opensolaris/uts/common/fs/zfs/lz4.c optional zfs compile-with "${ZFS_C}" cddl/contrib/opensolaris/uts/common/fs/zfs/lzjb.c optional zfs compile-with "${ZFS_C}" cddl/contrib/opensolaris/uts/common/fs/zfs/metaslab.c optional zfs compile-with "${ZFS_C}" cddl/contrib/opensolaris/uts/common/fs/zfs/multilist.c optional zfs compile-with "${ZFS_C}" cddl/contrib/opensolaris/uts/common/fs/zfs/range_tree.c optional zfs compile-with "${ZFS_C}" cddl/contrib/opensolaris/uts/common/fs/zfs/refcount.c optional zfs compile-with "${ZFS_C}" cddl/contrib/opensolaris/uts/common/fs/zfs/rrwlock.c optional zfs compile-with "${ZFS_C}" cddl/contrib/opensolaris/uts/common/fs/zfs/sa.c optional zfs compile-with "${ZFS_C}" cddl/contrib/opensolaris/uts/common/fs/zfs/sha256.c optional zfs compile-with "${ZFS_C}" cddl/contrib/opensolaris/uts/common/fs/zfs/skein_zfs.c optional zfs compile-with "${ZFS_C}" cddl/contrib/opensolaris/uts/common/fs/zfs/spa.c optional zfs compile-with "${ZFS_C}" cddl/contrib/opensolaris/uts/common/fs/zfs/spa_config.c optional zfs compile-with "${ZFS_C}" cddl/contrib/opensolaris/uts/common/fs/zfs/spa_errlog.c optional zfs compile-with "${ZFS_C}" cddl/contrib/opensolaris/uts/common/fs/zfs/spa_history.c optional zfs compile-with "${ZFS_C}" cddl/contrib/opensolaris/uts/common/fs/zfs/spa_misc.c optional zfs compile-with "${ZFS_C}" cddl/contrib/opensolaris/uts/common/fs/zfs/space_map.c optional zfs compile-with "${ZFS_C}" cddl/contrib/opensolaris/uts/common/fs/zfs/space_reftree.c optional zfs compile-with "${ZFS_C}" cddl/contrib/opensolaris/uts/common/fs/zfs/trim_map.c optional zfs compile-with "${ZFS_C}" cddl/contrib/opensolaris/uts/common/fs/zfs/txg.c optional zfs compile-with "${ZFS_C}" cddl/contrib/opensolaris/uts/common/fs/zfs/uberblock.c optional zfs compile-with "${ZFS_C}" cddl/contrib/opensolaris/uts/common/fs/zfs/unique.c optional zfs compile-with "${ZFS_C}" cddl/contrib/opensolaris/uts/common/fs/zfs/vdev.c optional zfs compile-with "${ZFS_C}" cddl/contrib/opensolaris/uts/common/fs/zfs/vdev_cache.c optional zfs compile-with "${ZFS_C}" cddl/contrib/opensolaris/uts/common/fs/zfs/vdev_file.c optional zfs compile-with "${ZFS_C}" cddl/contrib/opensolaris/uts/common/fs/zfs/vdev_geom.c optional zfs compile-with "${ZFS_C}" cddl/contrib/opensolaris/uts/common/fs/zfs/vdev_label.c optional zfs compile-with "${ZFS_C}" cddl/contrib/opensolaris/uts/common/fs/zfs/vdev_mirror.c optional zfs compile-with "${ZFS_C}" cddl/contrib/opensolaris/uts/common/fs/zfs/vdev_missing.c optional zfs compile-with "${ZFS_C}" cddl/contrib/opensolaris/uts/common/fs/zfs/vdev_queue.c optional zfs compile-with "${ZFS_C}" cddl/contrib/opensolaris/uts/common/fs/zfs/vdev_raidz.c optional zfs compile-with "${ZFS_C}" cddl/contrib/opensolaris/uts/common/fs/zfs/vdev_root.c optional zfs compile-with "${ZFS_C}" cddl/contrib/opensolaris/uts/common/fs/zfs/zap.c optional zfs compile-with "${ZFS_C}" cddl/contrib/opensolaris/uts/common/fs/zfs/zap_leaf.c optional zfs compile-with "${ZFS_C}" cddl/contrib/opensolaris/uts/common/fs/zfs/zap_micro.c optional zfs compile-with "${ZFS_C}" cddl/contrib/opensolaris/uts/common/fs/zfs/zcp.c optional zfs compile-with "${ZFS_C}" cddl/contrib/opensolaris/uts/common/fs/zfs/zcp_get.c optional zfs compile-with "${ZFS_C}" cddl/contrib/opensolaris/uts/common/fs/zfs/zcp_global.c optional zfs compile-with "${ZFS_C}" cddl/contrib/opensolaris/uts/common/fs/zfs/zcp_iter.c optional zfs compile-with "${ZFS_C}" cddl/contrib/opensolaris/uts/common/fs/zfs/zcp_synctask.c optional zfs compile-with "${ZFS_C}" cddl/contrib/opensolaris/uts/common/fs/zfs/zfeature.c optional zfs compile-with "${ZFS_C}" cddl/contrib/opensolaris/uts/common/fs/zfs/zfs_acl.c optional zfs compile-with "${ZFS_C}" cddl/contrib/opensolaris/uts/common/fs/zfs/zfs_byteswap.c optional zfs compile-with "${ZFS_C}" cddl/contrib/opensolaris/uts/common/fs/zfs/zfs_ctldir.c optional zfs compile-with "${ZFS_C}" cddl/contrib/opensolaris/uts/common/fs/zfs/zfs_debug.c optional zfs compile-with "${ZFS_C}" cddl/contrib/opensolaris/uts/common/fs/zfs/zfs_dir.c optional zfs compile-with "${ZFS_C}" cddl/contrib/opensolaris/uts/common/fs/zfs/zfs_fm.c optional zfs compile-with "${ZFS_C}" cddl/contrib/opensolaris/uts/common/fs/zfs/zfs_fuid.c optional zfs compile-with "${ZFS_C}" cddl/contrib/opensolaris/uts/common/fs/zfs/zfs_ioctl.c optional zfs compile-with "${ZFS_C}" cddl/contrib/opensolaris/uts/common/fs/zfs/zfs_log.c optional zfs compile-with "${ZFS_C}" cddl/contrib/opensolaris/uts/common/fs/zfs/zfs_onexit.c optional zfs compile-with "${ZFS_C}" cddl/contrib/opensolaris/uts/common/fs/zfs/zfs_replay.c optional zfs compile-with "${ZFS_C}" cddl/contrib/opensolaris/uts/common/fs/zfs/zfs_rlock.c optional zfs compile-with "${ZFS_C}" cddl/contrib/opensolaris/uts/common/fs/zfs/zfs_sa.c optional zfs compile-with "${ZFS_C}" cddl/contrib/opensolaris/uts/common/fs/zfs/zfs_vfsops.c optional zfs compile-with "${ZFS_C}" cddl/contrib/opensolaris/uts/common/fs/zfs/zfs_vnops.c optional zfs compile-with "${ZFS_C}" cddl/contrib/opensolaris/uts/common/fs/zfs/zfs_znode.c optional zfs compile-with "${ZFS_C}" cddl/contrib/opensolaris/uts/common/fs/zfs/zil.c optional zfs compile-with "${ZFS_C}" cddl/contrib/opensolaris/uts/common/fs/zfs/zio.c optional zfs compile-with "${ZFS_C}" cddl/contrib/opensolaris/uts/common/fs/zfs/zio_checksum.c optional zfs compile-with "${ZFS_C}" cddl/contrib/opensolaris/uts/common/fs/zfs/zio_compress.c optional zfs compile-with "${ZFS_C}" cddl/contrib/opensolaris/uts/common/fs/zfs/zio_inject.c optional zfs compile-with "${ZFS_C}" cddl/contrib/opensolaris/uts/common/fs/zfs/zle.c optional zfs compile-with "${ZFS_C}" cddl/contrib/opensolaris/uts/common/fs/zfs/zrlock.c optional zfs compile-with "${ZFS_C}" cddl/contrib/opensolaris/uts/common/fs/zfs/zvol.c optional zfs compile-with "${ZFS_C}" cddl/contrib/opensolaris/uts/common/os/callb.c optional zfs compile-with "${ZFS_C}" cddl/contrib/opensolaris/uts/common/os/fm.c optional zfs compile-with "${ZFS_C}" cddl/contrib/opensolaris/uts/common/os/list.c optional zfs compile-with "${ZFS_C}" cddl/contrib/opensolaris/uts/common/os/nvpair_alloc_system.c optional zfs compile-with "${ZFS_C}" cddl/contrib/opensolaris/uts/common/zmod/adler32.c optional zfs compile-with "${ZFS_C}" cddl/contrib/opensolaris/uts/common/zmod/deflate.c optional zfs compile-with "${ZFS_C}" cddl/contrib/opensolaris/uts/common/zmod/inffast.c optional zfs compile-with "${ZFS_C}" cddl/contrib/opensolaris/uts/common/zmod/inflate.c optional zfs compile-with "${ZFS_C}" cddl/contrib/opensolaris/uts/common/zmod/inftrees.c optional zfs compile-with "${ZFS_C}" cddl/contrib/opensolaris/uts/common/zmod/opensolaris_crc32.c optional zfs compile-with "${ZFS_C}" cddl/contrib/opensolaris/uts/common/zmod/trees.c optional zfs compile-with "${ZFS_C}" cddl/contrib/opensolaris/uts/common/zmod/zmod.c optional zfs compile-with "${ZFS_C}" cddl/contrib/opensolaris/uts/common/zmod/zmod_subr.c optional zfs compile-with "${ZFS_C}" cddl/contrib/opensolaris/uts/common/zmod/zutil.c optional zfs compile-with "${ZFS_C}" # zfs lua support cddl/contrib/opensolaris/uts/common/fs/zfs/lua/lapi.c optional zfs compile-with "${ZFS_C}" cddl/contrib/opensolaris/uts/common/fs/zfs/lua/lauxlib.c optional zfs compile-with "${ZFS_C}" cddl/contrib/opensolaris/uts/common/fs/zfs/lua/lbaselib.c optional zfs compile-with "${ZFS_C}" cddl/contrib/opensolaris/uts/common/fs/zfs/lua/lbitlib.c optional zfs compile-with "${ZFS_C}" cddl/contrib/opensolaris/uts/common/fs/zfs/lua/lcode.c optional zfs compile-with "${ZFS_C}" cddl/contrib/opensolaris/uts/common/fs/zfs/lua/lcompat.c optional zfs compile-with "${ZFS_C}" cddl/contrib/opensolaris/uts/common/fs/zfs/lua/lcorolib.c optional zfs compile-with "${ZFS_C}" cddl/contrib/opensolaris/uts/common/fs/zfs/lua/lctype.c optional zfs compile-with "${ZFS_C}" cddl/contrib/opensolaris/uts/common/fs/zfs/lua/ldebug.c optional zfs compile-with "${ZFS_C}" cddl/contrib/opensolaris/uts/common/fs/zfs/lua/ldo.c optional zfs compile-with "${ZFS_C}" cddl/contrib/opensolaris/uts/common/fs/zfs/lua/ldump.c optional zfs compile-with "${ZFS_C}" cddl/contrib/opensolaris/uts/common/fs/zfs/lua/lfunc.c optional zfs compile-with "${ZFS_C}" cddl/contrib/opensolaris/uts/common/fs/zfs/lua/lgc.c optional zfs compile-with "${ZFS_C}" cddl/contrib/opensolaris/uts/common/fs/zfs/lua/llex.c optional zfs compile-with "${ZFS_C}" cddl/contrib/opensolaris/uts/common/fs/zfs/lua/lmem.c optional zfs compile-with "${ZFS_C}" cddl/contrib/opensolaris/uts/common/fs/zfs/lua/lobject.c optional zfs compile-with "${ZFS_C}" cddl/contrib/opensolaris/uts/common/fs/zfs/lua/lopcodes.c optional zfs compile-with "${ZFS_C}" cddl/contrib/opensolaris/uts/common/fs/zfs/lua/lparser.c optional zfs compile-with "${ZFS_C}" cddl/contrib/opensolaris/uts/common/fs/zfs/lua/lstate.c optional zfs compile-with "${ZFS_C}" cddl/contrib/opensolaris/uts/common/fs/zfs/lua/lstring.c optional zfs compile-with "${ZFS_C}" cddl/contrib/opensolaris/uts/common/fs/zfs/lua/lstrlib.c optional zfs compile-with "${ZFS_C}" cddl/contrib/opensolaris/uts/common/fs/zfs/lua/ltable.c optional zfs compile-with "${ZFS_C}" cddl/contrib/opensolaris/uts/common/fs/zfs/lua/ltablib.c optional zfs compile-with "${ZFS_C}" cddl/contrib/opensolaris/uts/common/fs/zfs/lua/ltm.c optional zfs compile-with "${ZFS_C}" cddl/contrib/opensolaris/uts/common/fs/zfs/lua/lundump.c optional zfs compile-with "${ZFS_C}" cddl/contrib/opensolaris/uts/common/fs/zfs/lua/lvm.c optional zfs compile-with "${ZFS_C}" cddl/contrib/opensolaris/uts/common/fs/zfs/lua/lzio.c optional zfs compile-with "${ZFS_C}" # dtrace specific cddl/contrib/opensolaris/uts/common/dtrace/dtrace.c optional dtrace compile-with "${DTRACE_C}" \ warning "kernel contains CDDL licensed DTRACE" cddl/contrib/opensolaris/uts/common/dtrace/dtrace_xoroshiro128_plus.c optional dtrace compile-with "${DTRACE_C}" cddl/dev/dtmalloc/dtmalloc.c optional dtmalloc | dtraceall compile-with "${CDDL_C}" cddl/dev/profile/profile.c optional dtrace_profile | dtraceall compile-with "${CDDL_C}" cddl/dev/sdt/sdt.c optional dtrace_sdt | dtraceall compile-with "${CDDL_C}" cddl/dev/fbt/fbt.c optional dtrace_fbt | dtraceall compile-with "${FBT_C}" cddl/dev/systrace/systrace.c optional dtrace_systrace | dtraceall compile-with "${CDDL_C}" cddl/dev/prototype.c optional dtrace_prototype | dtraceall compile-with "${CDDL_C}" fs/nfsclient/nfs_clkdtrace.c optional dtnfscl nfscl | dtraceall nfscl compile-with "${CDDL_C}" compat/cloudabi/cloudabi_clock.c optional compat_cloudabi32 | compat_cloudabi64 compat/cloudabi/cloudabi_errno.c optional compat_cloudabi32 | compat_cloudabi64 compat/cloudabi/cloudabi_fd.c optional compat_cloudabi32 | compat_cloudabi64 compat/cloudabi/cloudabi_file.c optional compat_cloudabi32 | compat_cloudabi64 compat/cloudabi/cloudabi_futex.c optional compat_cloudabi32 | compat_cloudabi64 compat/cloudabi/cloudabi_mem.c optional compat_cloudabi32 | compat_cloudabi64 compat/cloudabi/cloudabi_proc.c optional compat_cloudabi32 | compat_cloudabi64 compat/cloudabi/cloudabi_random.c optional compat_cloudabi32 | compat_cloudabi64 compat/cloudabi/cloudabi_sock.c optional compat_cloudabi32 | compat_cloudabi64 compat/cloudabi/cloudabi_thread.c optional compat_cloudabi32 | compat_cloudabi64 compat/cloudabi/cloudabi_vdso.c optional compat_cloudabi32 | compat_cloudabi64 compat/cloudabi32/cloudabi32_fd.c optional compat_cloudabi32 compat/cloudabi32/cloudabi32_module.c optional compat_cloudabi32 compat/cloudabi32/cloudabi32_poll.c optional compat_cloudabi32 compat/cloudabi32/cloudabi32_sock.c optional compat_cloudabi32 compat/cloudabi32/cloudabi32_syscalls.c optional compat_cloudabi32 compat/cloudabi32/cloudabi32_sysent.c optional compat_cloudabi32 compat/cloudabi32/cloudabi32_thread.c optional compat_cloudabi32 compat/cloudabi64/cloudabi64_fd.c optional compat_cloudabi64 compat/cloudabi64/cloudabi64_module.c optional compat_cloudabi64 compat/cloudabi64/cloudabi64_poll.c optional compat_cloudabi64 compat/cloudabi64/cloudabi64_sock.c optional compat_cloudabi64 compat/cloudabi64/cloudabi64_syscalls.c optional compat_cloudabi64 compat/cloudabi64/cloudabi64_sysent.c optional compat_cloudabi64 compat/cloudabi64/cloudabi64_thread.c optional compat_cloudabi64 compat/freebsd32/freebsd32_capability.c optional compat_freebsd32 compat/freebsd32/freebsd32_ioctl.c optional compat_freebsd32 compat/freebsd32/freebsd32_misc.c optional compat_freebsd32 compat/freebsd32/freebsd32_syscalls.c optional compat_freebsd32 compat/freebsd32/freebsd32_sysent.c optional compat_freebsd32 contrib/ck/src/ck_array.c standard compile-with "${NORMAL_C} -I$S/contrib/ck/include" contrib/ck/src/ck_barrier_centralized.c standard compile-with "${NORMAL_C} -I$S/contrib/ck/include" contrib/ck/src/ck_barrier_combining.c standard compile-with "${NORMAL_C} -I$S/contrib/ck/include" contrib/ck/src/ck_barrier_dissemination.c standard compile-with "${NORMAL_C} -I$S/contrib/ck/include" contrib/ck/src/ck_barrier_mcs.c standard compile-with "${NORMAL_C} -I$S/contrib/ck/include" contrib/ck/src/ck_barrier_tournament.c standard compile-with "${NORMAL_C} -I$S/contrib/ck/include" contrib/ck/src/ck_epoch.c standard compile-with "${NORMAL_C} -I$S/contrib/ck/include" contrib/ck/src/ck_hp.c standard compile-with "${NORMAL_C} -I$S/contrib/ck/include" contrib/ck/src/ck_hs.c standard compile-with "${NORMAL_C} -I$S/contrib/ck/include" contrib/ck/src/ck_ht.c standard compile-with "${NORMAL_C} -I$S/contrib/ck/include" contrib/ck/src/ck_rhs.c standard compile-with "${NORMAL_C} -I$S/contrib/ck/include" contrib/dev/acpica/common/ahids.c optional acpi acpi_debug contrib/dev/acpica/common/ahuuids.c optional acpi acpi_debug contrib/dev/acpica/components/debugger/dbcmds.c optional acpi acpi_debug contrib/dev/acpica/components/debugger/dbconvert.c optional acpi acpi_debug contrib/dev/acpica/components/debugger/dbdisply.c optional acpi acpi_debug contrib/dev/acpica/components/debugger/dbexec.c optional acpi acpi_debug contrib/dev/acpica/components/debugger/dbhistry.c optional acpi acpi_debug contrib/dev/acpica/components/debugger/dbinput.c optional acpi acpi_debug contrib/dev/acpica/components/debugger/dbmethod.c optional acpi acpi_debug contrib/dev/acpica/components/debugger/dbnames.c optional acpi acpi_debug contrib/dev/acpica/components/debugger/dbobject.c optional acpi acpi_debug contrib/dev/acpica/components/debugger/dbstats.c optional acpi acpi_debug contrib/dev/acpica/components/debugger/dbtest.c optional acpi acpi_debug contrib/dev/acpica/components/debugger/dbutils.c optional acpi acpi_debug contrib/dev/acpica/components/debugger/dbxface.c optional acpi acpi_debug contrib/dev/acpica/components/disassembler/dmbuffer.c optional acpi acpi_debug contrib/dev/acpica/components/disassembler/dmcstyle.c optional acpi acpi_debug contrib/dev/acpica/components/disassembler/dmdeferred.c optional acpi acpi_debug contrib/dev/acpica/components/disassembler/dmnames.c optional acpi acpi_debug contrib/dev/acpica/components/disassembler/dmopcode.c optional acpi acpi_debug contrib/dev/acpica/components/disassembler/dmresrc.c optional acpi acpi_debug contrib/dev/acpica/components/disassembler/dmresrcl.c optional acpi acpi_debug contrib/dev/acpica/components/disassembler/dmresrcl2.c optional acpi acpi_debug contrib/dev/acpica/components/disassembler/dmresrcs.c optional acpi acpi_debug contrib/dev/acpica/components/disassembler/dmutils.c optional acpi acpi_debug contrib/dev/acpica/components/disassembler/dmwalk.c optional acpi acpi_debug contrib/dev/acpica/components/dispatcher/dsargs.c optional acpi contrib/dev/acpica/components/dispatcher/dscontrol.c optional acpi contrib/dev/acpica/components/dispatcher/dsdebug.c optional acpi contrib/dev/acpica/components/dispatcher/dsfield.c optional acpi contrib/dev/acpica/components/dispatcher/dsinit.c optional acpi contrib/dev/acpica/components/dispatcher/dsmethod.c optional acpi contrib/dev/acpica/components/dispatcher/dsmthdat.c optional acpi contrib/dev/acpica/components/dispatcher/dsobject.c optional acpi contrib/dev/acpica/components/dispatcher/dsopcode.c optional acpi contrib/dev/acpica/components/dispatcher/dspkginit.c optional acpi contrib/dev/acpica/components/dispatcher/dsutils.c optional acpi contrib/dev/acpica/components/dispatcher/dswexec.c optional acpi contrib/dev/acpica/components/dispatcher/dswload.c optional acpi contrib/dev/acpica/components/dispatcher/dswload2.c optional acpi contrib/dev/acpica/components/dispatcher/dswscope.c optional acpi contrib/dev/acpica/components/dispatcher/dswstate.c optional acpi contrib/dev/acpica/components/events/evevent.c optional acpi contrib/dev/acpica/components/events/evglock.c optional acpi contrib/dev/acpica/components/events/evgpe.c optional acpi contrib/dev/acpica/components/events/evgpeblk.c optional acpi contrib/dev/acpica/components/events/evgpeinit.c optional acpi contrib/dev/acpica/components/events/evgpeutil.c optional acpi contrib/dev/acpica/components/events/evhandler.c optional acpi contrib/dev/acpica/components/events/evmisc.c optional acpi contrib/dev/acpica/components/events/evregion.c optional acpi contrib/dev/acpica/components/events/evrgnini.c optional acpi contrib/dev/acpica/components/events/evsci.c optional acpi contrib/dev/acpica/components/events/evxface.c optional acpi contrib/dev/acpica/components/events/evxfevnt.c optional acpi contrib/dev/acpica/components/events/evxfgpe.c optional acpi contrib/dev/acpica/components/events/evxfregn.c optional acpi contrib/dev/acpica/components/executer/exconcat.c optional acpi contrib/dev/acpica/components/executer/exconfig.c optional acpi contrib/dev/acpica/components/executer/exconvrt.c optional acpi contrib/dev/acpica/components/executer/excreate.c optional acpi contrib/dev/acpica/components/executer/exdebug.c optional acpi contrib/dev/acpica/components/executer/exdump.c optional acpi contrib/dev/acpica/components/executer/exfield.c optional acpi contrib/dev/acpica/components/executer/exfldio.c optional acpi contrib/dev/acpica/components/executer/exmisc.c optional acpi contrib/dev/acpica/components/executer/exmutex.c optional acpi contrib/dev/acpica/components/executer/exnames.c optional acpi contrib/dev/acpica/components/executer/exoparg1.c optional acpi contrib/dev/acpica/components/executer/exoparg2.c optional acpi contrib/dev/acpica/components/executer/exoparg3.c optional acpi contrib/dev/acpica/components/executer/exoparg6.c optional acpi contrib/dev/acpica/components/executer/exprep.c optional acpi contrib/dev/acpica/components/executer/exregion.c optional acpi contrib/dev/acpica/components/executer/exresnte.c optional acpi contrib/dev/acpica/components/executer/exresolv.c optional acpi contrib/dev/acpica/components/executer/exresop.c optional acpi contrib/dev/acpica/components/executer/exstore.c optional acpi contrib/dev/acpica/components/executer/exstoren.c optional acpi contrib/dev/acpica/components/executer/exstorob.c optional acpi contrib/dev/acpica/components/executer/exsystem.c optional acpi contrib/dev/acpica/components/executer/extrace.c optional acpi contrib/dev/acpica/components/executer/exutils.c optional acpi contrib/dev/acpica/components/hardware/hwacpi.c optional acpi contrib/dev/acpica/components/hardware/hwesleep.c optional acpi contrib/dev/acpica/components/hardware/hwgpe.c optional acpi contrib/dev/acpica/components/hardware/hwpci.c optional acpi contrib/dev/acpica/components/hardware/hwregs.c optional acpi contrib/dev/acpica/components/hardware/hwsleep.c optional acpi contrib/dev/acpica/components/hardware/hwtimer.c optional acpi contrib/dev/acpica/components/hardware/hwvalid.c optional acpi contrib/dev/acpica/components/hardware/hwxface.c optional acpi contrib/dev/acpica/components/hardware/hwxfsleep.c optional acpi contrib/dev/acpica/components/namespace/nsaccess.c optional acpi contrib/dev/acpica/components/namespace/nsalloc.c optional acpi contrib/dev/acpica/components/namespace/nsarguments.c optional acpi contrib/dev/acpica/components/namespace/nsconvert.c optional acpi contrib/dev/acpica/components/namespace/nsdump.c optional acpi contrib/dev/acpica/components/namespace/nseval.c optional acpi contrib/dev/acpica/components/namespace/nsinit.c optional acpi contrib/dev/acpica/components/namespace/nsload.c optional acpi contrib/dev/acpica/components/namespace/nsnames.c optional acpi contrib/dev/acpica/components/namespace/nsobject.c optional acpi contrib/dev/acpica/components/namespace/nsparse.c optional acpi contrib/dev/acpica/components/namespace/nspredef.c optional acpi contrib/dev/acpica/components/namespace/nsprepkg.c optional acpi contrib/dev/acpica/components/namespace/nsrepair.c optional acpi contrib/dev/acpica/components/namespace/nsrepair2.c optional acpi contrib/dev/acpica/components/namespace/nssearch.c optional acpi contrib/dev/acpica/components/namespace/nsutils.c optional acpi contrib/dev/acpica/components/namespace/nswalk.c optional acpi contrib/dev/acpica/components/namespace/nsxfeval.c optional acpi contrib/dev/acpica/components/namespace/nsxfname.c optional acpi contrib/dev/acpica/components/namespace/nsxfobj.c optional acpi contrib/dev/acpica/components/parser/psargs.c optional acpi contrib/dev/acpica/components/parser/psloop.c optional acpi contrib/dev/acpica/components/parser/psobject.c optional acpi contrib/dev/acpica/components/parser/psopcode.c optional acpi contrib/dev/acpica/components/parser/psopinfo.c optional acpi contrib/dev/acpica/components/parser/psparse.c optional acpi contrib/dev/acpica/components/parser/psscope.c optional acpi contrib/dev/acpica/components/parser/pstree.c optional acpi contrib/dev/acpica/components/parser/psutils.c optional acpi contrib/dev/acpica/components/parser/pswalk.c optional acpi contrib/dev/acpica/components/parser/psxface.c optional acpi contrib/dev/acpica/components/resources/rsaddr.c optional acpi contrib/dev/acpica/components/resources/rscalc.c optional acpi contrib/dev/acpica/components/resources/rscreate.c optional acpi contrib/dev/acpica/components/resources/rsdump.c optional acpi acpi_debug contrib/dev/acpica/components/resources/rsdumpinfo.c optional acpi contrib/dev/acpica/components/resources/rsinfo.c optional acpi contrib/dev/acpica/components/resources/rsio.c optional acpi contrib/dev/acpica/components/resources/rsirq.c optional acpi contrib/dev/acpica/components/resources/rslist.c optional acpi contrib/dev/acpica/components/resources/rsmemory.c optional acpi contrib/dev/acpica/components/resources/rsmisc.c optional acpi contrib/dev/acpica/components/resources/rsserial.c optional acpi contrib/dev/acpica/components/resources/rsutils.c optional acpi contrib/dev/acpica/components/resources/rsxface.c optional acpi contrib/dev/acpica/components/tables/tbdata.c optional acpi contrib/dev/acpica/components/tables/tbfadt.c optional acpi contrib/dev/acpica/components/tables/tbfind.c optional acpi contrib/dev/acpica/components/tables/tbinstal.c optional acpi contrib/dev/acpica/components/tables/tbprint.c optional acpi contrib/dev/acpica/components/tables/tbutils.c optional acpi contrib/dev/acpica/components/tables/tbxface.c optional acpi contrib/dev/acpica/components/tables/tbxfload.c optional acpi contrib/dev/acpica/components/tables/tbxfroot.c optional acpi contrib/dev/acpica/components/utilities/utaddress.c optional acpi contrib/dev/acpica/components/utilities/utalloc.c optional acpi contrib/dev/acpica/components/utilities/utascii.c optional acpi contrib/dev/acpica/components/utilities/utbuffer.c optional acpi contrib/dev/acpica/components/utilities/utcache.c optional acpi contrib/dev/acpica/components/utilities/utcopy.c optional acpi contrib/dev/acpica/components/utilities/utdebug.c optional acpi contrib/dev/acpica/components/utilities/utdecode.c optional acpi contrib/dev/acpica/components/utilities/utdelete.c optional acpi contrib/dev/acpica/components/utilities/uterror.c optional acpi contrib/dev/acpica/components/utilities/uteval.c optional acpi contrib/dev/acpica/components/utilities/utexcep.c optional acpi contrib/dev/acpica/components/utilities/utglobal.c optional acpi contrib/dev/acpica/components/utilities/uthex.c optional acpi contrib/dev/acpica/components/utilities/utids.c optional acpi contrib/dev/acpica/components/utilities/utinit.c optional acpi contrib/dev/acpica/components/utilities/utlock.c optional acpi contrib/dev/acpica/components/utilities/utmath.c optional acpi contrib/dev/acpica/components/utilities/utmisc.c optional acpi contrib/dev/acpica/components/utilities/utmutex.c optional acpi contrib/dev/acpica/components/utilities/utnonansi.c optional acpi contrib/dev/acpica/components/utilities/utobject.c optional acpi contrib/dev/acpica/components/utilities/utosi.c optional acpi contrib/dev/acpica/components/utilities/utownerid.c optional acpi contrib/dev/acpica/components/utilities/utpredef.c optional acpi contrib/dev/acpica/components/utilities/utresdecode.c optional acpi acpi_debug contrib/dev/acpica/components/utilities/utresrc.c optional acpi contrib/dev/acpica/components/utilities/utstate.c optional acpi contrib/dev/acpica/components/utilities/utstring.c optional acpi contrib/dev/acpica/components/utilities/utstrsuppt.c optional acpi contrib/dev/acpica/components/utilities/utstrtoul64.c optional acpi contrib/dev/acpica/components/utilities/utuuid.c optional acpi acpi_debug contrib/dev/acpica/components/utilities/utxface.c optional acpi contrib/dev/acpica/components/utilities/utxferror.c optional acpi contrib/dev/acpica/components/utilities/utxfinit.c optional acpi contrib/dev/acpica/os_specific/service_layers/osgendbg.c optional acpi acpi_debug contrib/ipfilter/netinet/fil.c optional ipfilter inet \ compile-with "${NORMAL_C} ${NO_WSELF_ASSIGN} -Wno-unused -I$S/contrib/ipfilter" contrib/ipfilter/netinet/ip_auth.c optional ipfilter inet \ compile-with "${NORMAL_C} -Wno-unused -I$S/contrib/ipfilter" contrib/ipfilter/netinet/ip_fil_freebsd.c optional ipfilter inet \ compile-with "${NORMAL_C} -Wno-unused -I$S/contrib/ipfilter" contrib/ipfilter/netinet/ip_frag.c optional ipfilter inet \ compile-with "${NORMAL_C} -Wno-unused -I$S/contrib/ipfilter" contrib/ipfilter/netinet/ip_log.c optional ipfilter inet \ compile-with "${NORMAL_C} -I$S/contrib/ipfilter" contrib/ipfilter/netinet/ip_nat.c optional ipfilter inet \ compile-with "${NORMAL_C} -Wno-unused -I$S/contrib/ipfilter" contrib/ipfilter/netinet/ip_proxy.c optional ipfilter inet \ compile-with "${NORMAL_C} ${NO_WSELF_ASSIGN} -Wno-unused -I$S/contrib/ipfilter" contrib/ipfilter/netinet/ip_state.c optional ipfilter inet \ compile-with "${NORMAL_C} -Wno-unused -I$S/contrib/ipfilter" contrib/ipfilter/netinet/ip_lookup.c optional ipfilter inet \ compile-with "${NORMAL_C} ${NO_WSELF_ASSIGN} -Wno-unused -Wno-error -I$S/contrib/ipfilter" contrib/ipfilter/netinet/ip_pool.c optional ipfilter inet \ compile-with "${NORMAL_C} -Wno-unused -I$S/contrib/ipfilter" contrib/ipfilter/netinet/ip_htable.c optional ipfilter inet \ compile-with "${NORMAL_C} -Wno-unused -I$S/contrib/ipfilter" contrib/ipfilter/netinet/ip_sync.c optional ipfilter inet \ compile-with "${NORMAL_C} -Wno-unused -I$S/contrib/ipfilter" contrib/ipfilter/netinet/mlfk_ipl.c optional ipfilter inet \ compile-with "${NORMAL_C} -I$S/contrib/ipfilter" contrib/ipfilter/netinet/ip_nat6.c optional ipfilter inet \ compile-with "${NORMAL_C} -Wno-unused -I$S/contrib/ipfilter" contrib/ipfilter/netinet/ip_rules.c optional ipfilter inet \ compile-with "${NORMAL_C} -I$S/contrib/ipfilter" contrib/ipfilter/netinet/ip_scan.c optional ipfilter inet \ compile-with "${NORMAL_C} -Wno-unused -I$S/contrib/ipfilter" contrib/ipfilter/netinet/ip_dstlist.c optional ipfilter inet \ compile-with "${NORMAL_C} -Wno-unused -I$S/contrib/ipfilter" contrib/ipfilter/netinet/radix_ipf.c optional ipfilter inet \ compile-with "${NORMAL_C} -I$S/contrib/ipfilter" contrib/libfdt/fdt.c optional fdt contrib/libfdt/fdt_ro.c optional fdt contrib/libfdt/fdt_rw.c optional fdt contrib/libfdt/fdt_strerror.c optional fdt contrib/libfdt/fdt_sw.c optional fdt contrib/libfdt/fdt_wip.c optional fdt contrib/libnv/cnvlist.c standard contrib/libnv/dnvlist.c standard contrib/libnv/nvlist.c standard contrib/libnv/nvpair.c standard contrib/ngatm/netnatm/api/cc_conn.c optional ngatm_ccatm \ compile-with "${NORMAL_C_NOWERROR} -I$S/contrib/ngatm" contrib/ngatm/netnatm/api/cc_data.c optional ngatm_ccatm \ compile-with "${NORMAL_C} -I$S/contrib/ngatm" contrib/ngatm/netnatm/api/cc_dump.c optional ngatm_ccatm \ compile-with "${NORMAL_C} -I$S/contrib/ngatm" contrib/ngatm/netnatm/api/cc_port.c optional ngatm_ccatm \ compile-with "${NORMAL_C} -I$S/contrib/ngatm" contrib/ngatm/netnatm/api/cc_sig.c optional ngatm_ccatm \ compile-with "${NORMAL_C} -I$S/contrib/ngatm" contrib/ngatm/netnatm/api/cc_user.c optional ngatm_ccatm \ compile-with "${NORMAL_C} -I$S/contrib/ngatm" contrib/ngatm/netnatm/api/unisap.c optional ngatm_ccatm \ compile-with "${NORMAL_C} -I$S/contrib/ngatm" contrib/ngatm/netnatm/misc/straddr.c optional ngatm_atmbase \ compile-with "${NORMAL_C} -I$S/contrib/ngatm" contrib/ngatm/netnatm/misc/unimsg_common.c optional ngatm_atmbase \ compile-with "${NORMAL_C} -I$S/contrib/ngatm" contrib/ngatm/netnatm/msg/traffic.c optional ngatm_atmbase \ compile-with "${NORMAL_C} -I$S/contrib/ngatm" contrib/ngatm/netnatm/msg/uni_ie.c optional ngatm_atmbase \ compile-with "${NORMAL_C} -I$S/contrib/ngatm" contrib/ngatm/netnatm/msg/uni_msg.c optional ngatm_atmbase \ compile-with "${NORMAL_C} -I$S/contrib/ngatm" contrib/ngatm/netnatm/saal/saal_sscfu.c optional ngatm_sscfu \ compile-with "${NORMAL_C} -I$S/contrib/ngatm" contrib/ngatm/netnatm/saal/saal_sscop.c optional ngatm_sscop \ compile-with "${NORMAL_C} -I$S/contrib/ngatm" contrib/ngatm/netnatm/sig/sig_call.c optional ngatm_uni \ compile-with "${NORMAL_C} -I$S/contrib/ngatm" contrib/ngatm/netnatm/sig/sig_coord.c optional ngatm_uni \ compile-with "${NORMAL_C} -I$S/contrib/ngatm" contrib/ngatm/netnatm/sig/sig_party.c optional ngatm_uni \ compile-with "${NORMAL_C} -I$S/contrib/ngatm" contrib/ngatm/netnatm/sig/sig_print.c optional ngatm_uni \ compile-with "${NORMAL_C} -I$S/contrib/ngatm" contrib/ngatm/netnatm/sig/sig_reset.c optional ngatm_uni \ compile-with "${NORMAL_C} -I$S/contrib/ngatm" contrib/ngatm/netnatm/sig/sig_uni.c optional ngatm_uni \ compile-with "${NORMAL_C} -I$S/contrib/ngatm" contrib/ngatm/netnatm/sig/sig_unimsgcpy.c optional ngatm_uni \ compile-with "${NORMAL_C} -I$S/contrib/ngatm" contrib/ngatm/netnatm/sig/sig_verify.c optional ngatm_uni \ compile-with "${NORMAL_C} -I$S/contrib/ngatm" # Zstd contrib/zstd/lib/freebsd/zstd_kmalloc.c standard compile-with ${ZSTD_C} contrib/zstd/lib/common/zstd_common.c standard compile-with ${ZSTD_C} contrib/zstd/lib/common/fse_decompress.c standard compile-with ${ZSTD_C} contrib/zstd/lib/common/entropy_common.c standard compile-with ${ZSTD_C} contrib/zstd/lib/common/error_private.c standard compile-with ${ZSTD_C} contrib/zstd/lib/common/xxhash.c standard compile-with ${ZSTD_C} contrib/zstd/lib/compress/zstd_compress.c standard compile-with ${ZSTD_C} contrib/zstd/lib/compress/fse_compress.c standard compile-with ${ZSTD_C} contrib/zstd/lib/compress/huf_compress.c standard compile-with ${ZSTD_C} contrib/zstd/lib/compress/zstd_double_fast.c standard compile-with ${ZSTD_C} contrib/zstd/lib/compress/zstd_fast.c standard compile-with ${ZSTD_C} contrib/zstd/lib/compress/zstd_lazy.c standard compile-with ${ZSTD_C} contrib/zstd/lib/compress/zstd_ldm.c standard compile-with ${ZSTD_C} contrib/zstd/lib/compress/zstd_opt.c standard compile-with ${ZSTD_C} contrib/zstd/lib/decompress/zstd_decompress.c standard compile-with ${ZSTD_C} contrib/zstd/lib/decompress/huf_decompress.c standard compile-with ${ZSTD_C} crypto/blowfish/bf_ecb.c optional ipsec | ipsec_support crypto/blowfish/bf_skey.c optional crypto | ipsec | ipsec_support crypto/camellia/camellia.c optional crypto | ipsec | ipsec_support crypto/camellia/camellia-api.c optional crypto | ipsec | ipsec_support crypto/chacha20/chacha20.c optional chacha20 crypto/des/des_ecb.c optional crypto | ipsec | ipsec_support | netsmb crypto/des/des_setkey.c optional crypto | ipsec | ipsec_support | netsmb crypto/rc4/rc4.c optional netgraph_mppc_encryption | kgssapi crypto/rijndael/rijndael-alg-fst.c optional crypto | ekcd | geom_bde | \ ipsec | ipsec_support | random !random_loadable | wlan_ccmp crypto/rijndael/rijndael-api-fst.c optional ekcd | geom_bde | random !random_loadable crypto/rijndael/rijndael-api.c optional crypto | ipsec | ipsec_support | \ wlan_ccmp crypto/sha1.c optional carp | crypto | ipsec | \ ipsec_support | netgraph_mppc_encryption | sctp crypto/sha2/sha256c.c optional crypto | ekcd | geom_bde | ipsec | \ ipsec_support | random !random_loadable | sctp | zfs crypto/sha2/sha512c.c optional crypto | geom_bde | ipsec | \ ipsec_support | zfs crypto/skein/skein.c optional crypto | zfs crypto/skein/skein_block.c optional crypto | zfs crypto/siphash/siphash.c optional inet | inet6 crypto/siphash/siphash_test.c optional inet | inet6 ddb/db_access.c optional ddb ddb/db_break.c optional ddb ddb/db_capture.c optional ddb ddb/db_command.c optional ddb ddb/db_examine.c optional ddb ddb/db_expr.c optional ddb ddb/db_input.c optional ddb ddb/db_lex.c optional ddb ddb/db_main.c optional ddb ddb/db_output.c optional ddb ddb/db_print.c optional ddb ddb/db_ps.c optional ddb ddb/db_run.c optional ddb ddb/db_script.c optional ddb ddb/db_sym.c optional ddb ddb/db_thread.c optional ddb ddb/db_textdump.c optional ddb ddb/db_variables.c optional ddb ddb/db_watch.c optional ddb ddb/db_write_cmd.c optional ddb dev/aac/aac.c optional aac dev/aac/aac_cam.c optional aacp aac dev/aac/aac_debug.c optional aac dev/aac/aac_disk.c optional aac dev/aac/aac_linux.c optional aac compat_linux dev/aac/aac_pci.c optional aac pci dev/aacraid/aacraid.c optional aacraid dev/aacraid/aacraid_cam.c optional aacraid scbus dev/aacraid/aacraid_debug.c optional aacraid dev/aacraid/aacraid_linux.c optional aacraid compat_linux dev/aacraid/aacraid_pci.c optional aacraid pci dev/acpi_support/acpi_wmi.c optional acpi_wmi acpi dev/acpi_support/acpi_asus.c optional acpi_asus acpi dev/acpi_support/acpi_asus_wmi.c optional acpi_asus_wmi acpi dev/acpi_support/acpi_fujitsu.c optional acpi_fujitsu acpi dev/acpi_support/acpi_hp.c optional acpi_hp acpi dev/acpi_support/acpi_ibm.c optional acpi_ibm acpi dev/acpi_support/acpi_panasonic.c optional acpi_panasonic acpi dev/acpi_support/acpi_sony.c optional acpi_sony acpi dev/acpi_support/acpi_toshiba.c optional acpi_toshiba acpi dev/acpi_support/atk0110.c optional aibs acpi dev/acpica/Osd/OsdDebug.c optional acpi dev/acpica/Osd/OsdHardware.c optional acpi dev/acpica/Osd/OsdInterrupt.c optional acpi dev/acpica/Osd/OsdMemory.c optional acpi dev/acpica/Osd/OsdSchedule.c optional acpi dev/acpica/Osd/OsdStream.c optional acpi dev/acpica/Osd/OsdSynch.c optional acpi dev/acpica/Osd/OsdTable.c optional acpi dev/acpica/acpi.c optional acpi dev/acpica/acpi_acad.c optional acpi dev/acpica/acpi_battery.c optional acpi dev/acpica/acpi_button.c optional acpi dev/acpica/acpi_cmbat.c optional acpi dev/acpica/acpi_cpu.c optional acpi dev/acpica/acpi_ec.c optional acpi dev/acpica/acpi_isab.c optional acpi isa dev/acpica/acpi_lid.c optional acpi dev/acpica/acpi_package.c optional acpi dev/acpica/acpi_perf.c optional acpi dev/acpica/acpi_powerres.c optional acpi dev/acpica/acpi_quirk.c optional acpi dev/acpica/acpi_resource.c optional acpi dev/acpica/acpi_container.c optional acpi dev/acpica/acpi_smbat.c optional acpi dev/acpica/acpi_thermal.c optional acpi dev/acpica/acpi_throttle.c optional acpi dev/acpica/acpi_video.c optional acpi_video acpi dev/acpica/acpi_dock.c optional acpi_dock acpi dev/adlink/adlink.c optional adlink dev/advansys/adv_pci.c optional adv pci dev/advansys/advansys.c optional adv dev/advansys/advlib.c optional adv dev/advansys/advmcode.c optional adv dev/advansys/adw_pci.c optional adw pci dev/advansys/adwcam.c optional adw dev/advansys/adwlib.c optional adw dev/advansys/adwmcode.c optional adw dev/ae/if_ae.c optional ae pci dev/age/if_age.c optional age pci dev/agp/agp.c optional agp pci dev/agp/agp_if.m optional agp pci dev/aha/aha.c optional aha dev/aha/aha_isa.c optional aha isa dev/ahci/ahci.c optional ahci dev/ahci/ahciem.c optional ahci dev/ahci/ahci_pci.c optional ahci pci dev/aic/aic.c optional aic dev/aic/aic_pccard.c optional aic pccard dev/aic7xxx/ahc_isa.c optional ahc isa dev/aic7xxx/ahc_pci.c optional ahc pci \ compile-with "${NORMAL_C} ${NO_WCONSTANT_CONVERSION}" dev/aic7xxx/ahd_pci.c optional ahd pci \ compile-with "${NORMAL_C} ${NO_WCONSTANT_CONVERSION}" dev/aic7xxx/aic7770.c optional ahc dev/aic7xxx/aic79xx.c optional ahd pci dev/aic7xxx/aic79xx_osm.c optional ahd pci dev/aic7xxx/aic79xx_pci.c optional ahd pci dev/aic7xxx/aic79xx_reg_print.c optional ahd pci ahd_reg_pretty_print dev/aic7xxx/aic7xxx.c optional ahc dev/aic7xxx/aic7xxx_93cx6.c optional ahc dev/aic7xxx/aic7xxx_osm.c optional ahc dev/aic7xxx/aic7xxx_pci.c optional ahc pci dev/aic7xxx/aic7xxx_reg_print.c optional ahc ahc_reg_pretty_print dev/al_eth/al_eth.c optional al_eth fdt \ no-depend \ compile-with "${CC} -c -o ${.TARGET} ${CFLAGS} -I$S/contrib/alpine-hal -I$S/contrib/alpine-hal/eth ${PROF} ${.IMPSRC}" dev/al_eth/al_init_eth_lm.c optional al_eth fdt \ no-depend \ compile-with "${CC} -c -o ${.TARGET} ${CFLAGS} -I$S/contrib/alpine-hal -I$S/contrib/alpine-hal/eth ${PROF} ${.IMPSRC}" dev/al_eth/al_init_eth_kr.c optional al_eth fdt \ no-depend \ compile-with "${CC} -c -o ${.TARGET} ${CFLAGS} -I$S/contrib/alpine-hal -I$S/contrib/alpine-hal/eth ${PROF} ${.IMPSRC}" contrib/alpine-hal/al_hal_iofic.c optional al_iofic \ no-depend \ compile-with "${CC} -c -o ${.TARGET} ${CFLAGS} -I$S/contrib/alpine-hal -I$S/contrib/alpine-hal/eth ${PROF} ${.IMPSRC}" contrib/alpine-hal/al_hal_serdes_25g.c optional al_serdes \ no-depend \ compile-with "${CC} -c -o ${.TARGET} ${CFLAGS} -I$S/contrib/alpine-hal -I$S/contrib/alpine-hal/eth ${PROF} ${.IMPSRC}" contrib/alpine-hal/al_hal_serdes_hssp.c optional al_serdes \ no-depend \ compile-with "${CC} -c -o ${.TARGET} ${CFLAGS} -I$S/contrib/alpine-hal -I$S/contrib/alpine-hal/eth ${PROF} ${.IMPSRC}" contrib/alpine-hal/al_hal_udma_config.c optional al_udma \ no-depend \ compile-with "${CC} -c -o ${.TARGET} ${CFLAGS} -I$S/contrib/alpine-hal -I$S/contrib/alpine-hal/eth ${PROF} ${.IMPSRC}" contrib/alpine-hal/al_hal_udma_debug.c optional al_udma \ no-depend \ compile-with "${CC} -c -o ${.TARGET} ${CFLAGS} -I$S/contrib/alpine-hal -I$S/contrib/alpine-hal/eth ${PROF} ${.IMPSRC}" contrib/alpine-hal/al_hal_udma_iofic.c optional al_udma \ no-depend \ compile-with "${CC} -c -o ${.TARGET} ${CFLAGS} -I$S/contrib/alpine-hal -I$S/contrib/alpine-hal/eth ${PROF} ${.IMPSRC}" contrib/alpine-hal/al_hal_udma_main.c optional al_udma \ no-depend \ compile-with "${CC} -c -o ${.TARGET} ${CFLAGS} -I$S/contrib/alpine-hal -I$S/contrib/alpine-hal/eth ${PROF} ${.IMPSRC}" contrib/alpine-hal/al_serdes.c optional al_serdes \ no-depend \ compile-with "${CC} -c -o ${.TARGET} ${CFLAGS} -I$S/contrib/alpine-hal -I$S/contrib/alpine-hal/eth ${PROF} ${.IMPSRC}" contrib/alpine-hal/eth/al_hal_eth_kr.c optional al_eth \ no-depend \ compile-with "${CC} -c -o ${.TARGET} ${CFLAGS} -I$S/contrib/alpine-hal -I$S/contrib/alpine-hal/eth ${PROF} ${.IMPSRC}" contrib/alpine-hal/eth/al_hal_eth_main.c optional al_eth \ no-depend \ compile-with "${CC} -c -o ${.TARGET} ${CFLAGS} -I$S/contrib/alpine-hal -I$S/contrib/alpine-hal/eth ${PROF} ${.IMPSRC}" dev/alc/if_alc.c optional alc pci dev/ale/if_ale.c optional ale pci dev/alpm/alpm.c optional alpm pci dev/altera/avgen/altera_avgen.c optional altera_avgen dev/altera/avgen/altera_avgen_fdt.c optional altera_avgen fdt dev/altera/avgen/altera_avgen_nexus.c optional altera_avgen dev/altera/sdcard/altera_sdcard.c optional altera_sdcard dev/altera/sdcard/altera_sdcard_disk.c optional altera_sdcard dev/altera/sdcard/altera_sdcard_io.c optional altera_sdcard dev/altera/sdcard/altera_sdcard_fdt.c optional altera_sdcard fdt dev/altera/sdcard/altera_sdcard_nexus.c optional altera_sdcard dev/altera/pio/pio.c optional altera_pio dev/altera/pio/pio_if.m optional altera_pio dev/amdpm/amdpm.c optional amdpm pci | nfpm pci dev/amdsmb/amdsmb.c optional amdsmb pci dev/amr/amr.c optional amr dev/amr/amr_cam.c optional amrp amr dev/amr/amr_disk.c optional amr dev/amr/amr_linux.c optional amr compat_linux dev/amr/amr_pci.c optional amr pci dev/an/if_an.c optional an dev/an/if_an_isa.c optional an isa dev/an/if_an_pccard.c optional an pccard dev/an/if_an_pci.c optional an pci # dev/ata/ata_if.m optional ata | atacore dev/ata/ata-all.c optional ata | atacore dev/ata/ata-dma.c optional ata | atacore dev/ata/ata-lowlevel.c optional ata | atacore dev/ata/ata-sata.c optional ata | atacore dev/ata/ata-card.c optional ata pccard | atapccard dev/ata/ata-isa.c optional ata isa | ataisa dev/ata/ata-pci.c optional ata pci | atapci dev/ata/chipsets/ata-acard.c optional ata pci | ataacard dev/ata/chipsets/ata-acerlabs.c optional ata pci | ataacerlabs dev/ata/chipsets/ata-amd.c optional ata pci | ataamd dev/ata/chipsets/ata-ati.c optional ata pci | ataati dev/ata/chipsets/ata-cenatek.c optional ata pci | atacenatek dev/ata/chipsets/ata-cypress.c optional ata pci | atacypress dev/ata/chipsets/ata-cyrix.c optional ata pci | atacyrix dev/ata/chipsets/ata-highpoint.c optional ata pci | atahighpoint dev/ata/chipsets/ata-intel.c optional ata pci | ataintel dev/ata/chipsets/ata-ite.c optional ata pci | ataite dev/ata/chipsets/ata-jmicron.c optional ata pci | atajmicron dev/ata/chipsets/ata-marvell.c optional ata pci | atamarvell dev/ata/chipsets/ata-micron.c optional ata pci | atamicron dev/ata/chipsets/ata-national.c optional ata pci | atanational dev/ata/chipsets/ata-netcell.c optional ata pci | atanetcell dev/ata/chipsets/ata-nvidia.c optional ata pci | atanvidia dev/ata/chipsets/ata-promise.c optional ata pci | atapromise dev/ata/chipsets/ata-serverworks.c optional ata pci | ataserverworks dev/ata/chipsets/ata-siliconimage.c optional ata pci | atasiliconimage | ataati dev/ata/chipsets/ata-sis.c optional ata pci | atasis dev/ata/chipsets/ata-via.c optional ata pci | atavia # dev/ath/if_ath_pci.c optional ath_pci pci \ compile-with "${NORMAL_C} -I$S/dev/ath" # dev/ath/if_ath_ahb.c optional ath_ahb \ compile-with "${NORMAL_C} -I$S/dev/ath" # dev/ath/if_ath.c optional ath \ compile-with "${NORMAL_C} -I$S/dev/ath" dev/ath/if_ath_alq.c optional ath \ compile-with "${NORMAL_C} -I$S/dev/ath" dev/ath/if_ath_beacon.c optional ath \ compile-with "${NORMAL_C} -I$S/dev/ath" dev/ath/if_ath_btcoex.c optional ath \ compile-with "${NORMAL_C} -I$S/dev/ath" dev/ath/if_ath_btcoex_mci.c optional ath \ compile-with "${NORMAL_C} -I$S/dev/ath" dev/ath/if_ath_debug.c optional ath \ compile-with "${NORMAL_C} -I$S/dev/ath" dev/ath/if_ath_descdma.c optional ath \ compile-with "${NORMAL_C} -I$S/dev/ath" dev/ath/if_ath_keycache.c optional ath \ compile-with "${NORMAL_C} -I$S/dev/ath" dev/ath/if_ath_ioctl.c optional ath \ compile-with "${NORMAL_C} -I$S/dev/ath" dev/ath/if_ath_led.c optional ath \ compile-with "${NORMAL_C} -I$S/dev/ath" dev/ath/if_ath_lna_div.c optional ath \ compile-with "${NORMAL_C} -I$S/dev/ath" dev/ath/if_ath_tx.c optional ath \ compile-with "${NORMAL_C} -I$S/dev/ath" dev/ath/if_ath_tx_edma.c optional ath \ compile-with "${NORMAL_C} -I$S/dev/ath" dev/ath/if_ath_tx_ht.c optional ath \ compile-with "${NORMAL_C} -I$S/dev/ath" dev/ath/if_ath_tdma.c optional ath \ compile-with "${NORMAL_C} -I$S/dev/ath" dev/ath/if_ath_sysctl.c optional ath \ compile-with "${NORMAL_C} -I$S/dev/ath" dev/ath/if_ath_rx.c optional ath \ compile-with "${NORMAL_C} -I$S/dev/ath" dev/ath/if_ath_rx_edma.c optional ath \ compile-with "${NORMAL_C} -I$S/dev/ath" dev/ath/if_ath_spectral.c optional ath \ compile-with "${NORMAL_C} -I$S/dev/ath" dev/ath/ah_osdep.c optional ath \ compile-with "${NORMAL_C} -I$S/dev/ath" # dev/ath/ath_hal/ah.c optional ath \ compile-with "${NORMAL_C} -I$S/dev/ath" dev/ath/ath_hal/ah_eeprom_v1.c optional ath_hal | ath_ar5210 \ compile-with "${NORMAL_C} -I$S/dev/ath" dev/ath/ath_hal/ah_eeprom_v3.c optional ath_hal | ath_ar5211 | ath_ar5212 \ compile-with "${NORMAL_C} -I$S/dev/ath" dev/ath/ath_hal/ah_eeprom_v14.c \ optional ath_hal | ath_ar5416 | ath_ar9160 | ath_ar9280 \ compile-with "${NORMAL_C} -I$S/dev/ath" dev/ath/ath_hal/ah_eeprom_v4k.c \ optional ath_hal | ath_ar9285 \ compile-with "${NORMAL_C} -I$S/dev/ath" dev/ath/ath_hal/ah_eeprom_9287.c \ optional ath_hal | ath_ar9287 \ compile-with "${NORMAL_C} -I$S/dev/ath" dev/ath/ath_hal/ah_regdomain.c optional ath \ compile-with "${NORMAL_C} ${NO_WSHIFT_COUNT_NEGATIVE} ${NO_WSHIFT_COUNT_OVERFLOW} -I$S/dev/ath" # ar5210 dev/ath/ath_hal/ar5210/ar5210_attach.c optional ath_hal | ath_ar5210 \ compile-with "${NORMAL_C} -I$S/dev/ath -I$S/dev/ath/ath_hal" dev/ath/ath_hal/ar5210/ar5210_beacon.c optional ath_hal | ath_ar5210 \ compile-with "${NORMAL_C} -I$S/dev/ath -I$S/dev/ath/ath_hal" dev/ath/ath_hal/ar5210/ar5210_interrupts.c optional ath_hal | ath_ar5210 \ compile-with "${NORMAL_C} -I$S/dev/ath -I$S/dev/ath/ath_hal" dev/ath/ath_hal/ar5210/ar5210_keycache.c optional ath_hal | ath_ar5210 \ compile-with "${NORMAL_C} -I$S/dev/ath -I$S/dev/ath/ath_hal" dev/ath/ath_hal/ar5210/ar5210_misc.c optional ath_hal | ath_ar5210 \ compile-with "${NORMAL_C} -I$S/dev/ath -I$S/dev/ath/ath_hal" dev/ath/ath_hal/ar5210/ar5210_phy.c optional ath_hal | ath_ar5210 \ compile-with "${NORMAL_C} -I$S/dev/ath -I$S/dev/ath/ath_hal" dev/ath/ath_hal/ar5210/ar5210_power.c optional ath_hal | ath_ar5210 \ compile-with "${NORMAL_C} -I$S/dev/ath -I$S/dev/ath/ath_hal" dev/ath/ath_hal/ar5210/ar5210_recv.c optional ath_hal | ath_ar5210 \ compile-with "${NORMAL_C} -I$S/dev/ath -I$S/dev/ath/ath_hal" dev/ath/ath_hal/ar5210/ar5210_reset.c optional ath_hal | ath_ar5210 \ compile-with "${NORMAL_C} -I$S/dev/ath -I$S/dev/ath/ath_hal" dev/ath/ath_hal/ar5210/ar5210_xmit.c optional ath_hal | ath_ar5210 \ compile-with "${NORMAL_C} -I$S/dev/ath -I$S/dev/ath/ath_hal" # ar5211 dev/ath/ath_hal/ar5211/ar5211_attach.c optional ath_hal | ath_ar5211 \ compile-with "${NORMAL_C} -I$S/dev/ath -I$S/dev/ath/ath_hal" dev/ath/ath_hal/ar5211/ar5211_beacon.c optional ath_hal | ath_ar5211 \ compile-with "${NORMAL_C} -I$S/dev/ath -I$S/dev/ath/ath_hal" dev/ath/ath_hal/ar5211/ar5211_interrupts.c optional ath_hal | ath_ar5211 \ compile-with "${NORMAL_C} -I$S/dev/ath -I$S/dev/ath/ath_hal" dev/ath/ath_hal/ar5211/ar5211_keycache.c optional ath_hal | ath_ar5211 \ compile-with "${NORMAL_C} -I$S/dev/ath -I$S/dev/ath/ath_hal" dev/ath/ath_hal/ar5211/ar5211_misc.c optional ath_hal | ath_ar5211 \ compile-with "${NORMAL_C} -I$S/dev/ath -I$S/dev/ath/ath_hal" dev/ath/ath_hal/ar5211/ar5211_phy.c optional ath_hal | ath_ar5211 \ compile-with "${NORMAL_C} -I$S/dev/ath -I$S/dev/ath/ath_hal" dev/ath/ath_hal/ar5211/ar5211_power.c optional ath_hal | ath_ar5211 \ compile-with "${NORMAL_C} -I$S/dev/ath -I$S/dev/ath/ath_hal" dev/ath/ath_hal/ar5211/ar5211_recv.c optional ath_hal | ath_ar5211 \ compile-with "${NORMAL_C} -I$S/dev/ath -I$S/dev/ath/ath_hal" dev/ath/ath_hal/ar5211/ar5211_reset.c optional ath_hal | ath_ar5211 \ compile-with "${NORMAL_C} -I$S/dev/ath -I$S/dev/ath/ath_hal" dev/ath/ath_hal/ar5211/ar5211_xmit.c optional ath_hal | ath_ar5211 \ compile-with "${NORMAL_C} -I$S/dev/ath -I$S/dev/ath/ath_hal" # ar5212 dev/ath/ath_hal/ar5212/ar5212_ani.c \ optional ath_hal | ath_ar5212 | ath_ar5416 | ath_ar9160 | ath_ar9280 | \ ath_ar9285 ath_ar9287 \ compile-with "${NORMAL_C} -I$S/dev/ath -I$S/dev/ath/ath_hal" dev/ath/ath_hal/ar5212/ar5212_attach.c \ optional ath_hal | ath_ar5212 | ath_ar5416 | ath_ar9160 | ath_ar9280 | \ ath_ar9285 ath_ar9287 \ compile-with "${NORMAL_C} -I$S/dev/ath -I$S/dev/ath/ath_hal" dev/ath/ath_hal/ar5212/ar5212_beacon.c \ optional ath_hal | ath_ar5212 | ath_ar5416 | ath_ar9160 | ath_ar9280 | \ ath_ar9285 ath_ar9287 \ compile-with "${NORMAL_C} -I$S/dev/ath -I$S/dev/ath/ath_hal" dev/ath/ath_hal/ar5212/ar5212_eeprom.c \ optional ath_hal | ath_ar5212 | ath_ar5416 | ath_ar9160 | ath_ar9280 | \ ath_ar9285 ath_ar9287 \ compile-with "${NORMAL_C} -I$S/dev/ath -I$S/dev/ath/ath_hal" dev/ath/ath_hal/ar5212/ar5212_gpio.c \ optional ath_hal | ath_ar5212 | ath_ar5416 | ath_ar9160 | ath_ar9280 | \ ath_ar9285 ath_ar9287 \ compile-with "${NORMAL_C} -I$S/dev/ath -I$S/dev/ath/ath_hal" dev/ath/ath_hal/ar5212/ar5212_interrupts.c \ optional ath_hal | ath_ar5212 | ath_ar5416 | ath_ar9160 | ath_ar9280 | \ ath_ar9285 ath_ar9287 \ compile-with "${NORMAL_C} -I$S/dev/ath -I$S/dev/ath/ath_hal" dev/ath/ath_hal/ar5212/ar5212_keycache.c \ optional ath_hal | ath_ar5212 | ath_ar5416 | ath_ar9160 | ath_ar9280 | \ ath_ar9285 ath_ar9287 \ compile-with "${NORMAL_C} -I$S/dev/ath -I$S/dev/ath/ath_hal" dev/ath/ath_hal/ar5212/ar5212_misc.c \ optional ath_hal | ath_ar5212 | ath_ar5416 | ath_ar9160 | ath_ar9280 | \ ath_ar9285 ath_ar9287 \ compile-with "${NORMAL_C} -I$S/dev/ath -I$S/dev/ath/ath_hal" dev/ath/ath_hal/ar5212/ar5212_phy.c \ optional ath_hal | ath_ar5212 | ath_ar5416 | ath_ar9160 | ath_ar9280 | \ ath_ar9285 ath_ar9287 \ compile-with "${NORMAL_C} -I$S/dev/ath -I$S/dev/ath/ath_hal" dev/ath/ath_hal/ar5212/ar5212_power.c \ optional ath_hal | ath_ar5212 | ath_ar5416 | ath_ar9160 | ath_ar9280 | \ ath_ar9285 ath_ar9287 \ compile-with "${NORMAL_C} -I$S/dev/ath -I$S/dev/ath/ath_hal" dev/ath/ath_hal/ar5212/ar5212_recv.c \ optional ath_hal | ath_ar5212 | ath_ar5416 | ath_ar9160 | ath_ar9280 | \ ath_ar9285 ath_ar9287 \ compile-with "${NORMAL_C} -I$S/dev/ath -I$S/dev/ath/ath_hal" dev/ath/ath_hal/ar5212/ar5212_reset.c \ optional ath_hal | ath_ar5212 | ath_ar5416 | ath_ar9160 | ath_ar9280 | \ ath_ar9285 ath_ar9287 \ compile-with "${NORMAL_C} -I$S/dev/ath -I$S/dev/ath/ath_hal" dev/ath/ath_hal/ar5212/ar5212_rfgain.c \ optional ath_hal | ath_ar5212 | ath_ar5416 | ath_ar9160 | ath_ar9280 | \ ath_ar9285 ath_ar9287 \ compile-with "${NORMAL_C} -I$S/dev/ath -I$S/dev/ath/ath_hal" dev/ath/ath_hal/ar5212/ar5212_xmit.c \ optional ath_hal | ath_ar5212 | ath_ar5416 | ath_ar9160 | ath_ar9280 | \ ath_ar9285 ath_ar9287 \ compile-with "${NORMAL_C} -I$S/dev/ath -I$S/dev/ath/ath_hal" # ar5416 (depends on ar5212) dev/ath/ath_hal/ar5416/ar5416_ani.c \ optional ath_hal | ath_ar5416 | ath_ar9160 | ath_ar9280 | ath_ar9285 | \ ath_ar9287 \ compile-with "${NORMAL_C} -I$S/dev/ath -I$S/dev/ath/ath_hal" dev/ath/ath_hal/ar5416/ar5416_attach.c \ optional ath_hal | ath_ar5416 | ath_ar9160 | ath_ar9280 | ath_ar9285 | \ ath_ar9287 \ compile-with "${NORMAL_C} -I$S/dev/ath -I$S/dev/ath/ath_hal" dev/ath/ath_hal/ar5416/ar5416_beacon.c \ optional ath_hal | ath_ar5416 | ath_ar9160 | ath_ar9280 | ath_ar9285 | \ ath_ar9287 \ compile-with "${NORMAL_C} -I$S/dev/ath -I$S/dev/ath/ath_hal" dev/ath/ath_hal/ar5416/ar5416_btcoex.c \ optional ath_hal | ath_ar5416 | ath_ar9160 | ath_ar9280 | ath_ar9285 | \ ath_ar9287 \ compile-with "${NORMAL_C} -I$S/dev/ath -I$S/dev/ath/ath_hal" dev/ath/ath_hal/ar5416/ar5416_cal.c \ optional ath_hal | ath_ar5416 | ath_ar9160 | ath_ar9280 | ath_ar9285 | \ ath_ar9287 \ compile-with "${NORMAL_C} -I$S/dev/ath -I$S/dev/ath/ath_hal" dev/ath/ath_hal/ar5416/ar5416_cal_iq.c \ optional ath_hal | ath_ar5416 | ath_ar9160 | ath_ar9280 | ath_ar9285 | \ ath_ar9287 \ compile-with "${NORMAL_C} -I$S/dev/ath -I$S/dev/ath/ath_hal" dev/ath/ath_hal/ar5416/ar5416_cal_adcgain.c \ optional ath_hal | ath_ar5416 | ath_ar9160 | ath_ar9280 | ath_ar9285 | \ ath_ar9287 \ compile-with "${NORMAL_C} -I$S/dev/ath -I$S/dev/ath/ath_hal" dev/ath/ath_hal/ar5416/ar5416_cal_adcdc.c \ optional ath_hal | ath_ar5416 | ath_ar9160 | ath_ar9280 | ath_ar9285 | \ ath_ar9287 \ compile-with "${NORMAL_C} -I$S/dev/ath -I$S/dev/ath/ath_hal" dev/ath/ath_hal/ar5416/ar5416_eeprom.c \ optional ath_hal | ath_ar5416 | ath_ar9160 | ath_ar9280 | ath_ar9285 | \ ath_ar9287 \ compile-with "${NORMAL_C} -I$S/dev/ath -I$S/dev/ath/ath_hal" dev/ath/ath_hal/ar5416/ar5416_gpio.c \ optional ath_hal | ath_ar5416 | ath_ar9160 | ath_ar9280 | ath_ar9285 | \ ath_ar9287 \ compile-with "${NORMAL_C} -I$S/dev/ath -I$S/dev/ath/ath_hal" dev/ath/ath_hal/ar5416/ar5416_interrupts.c \ optional ath_hal | ath_ar5416 | ath_ar9160 | ath_ar9280 | ath_ar9285 | \ ath_ar9287 \ compile-with "${NORMAL_C} -I$S/dev/ath -I$S/dev/ath/ath_hal" dev/ath/ath_hal/ar5416/ar5416_keycache.c \ optional ath_hal | ath_ar5416 | ath_ar9160 | ath_ar9280 | ath_ar9285 | \ ath_ar9287 \ compile-with "${NORMAL_C} -I$S/dev/ath -I$S/dev/ath/ath_hal" dev/ath/ath_hal/ar5416/ar5416_misc.c \ optional ath_hal | ath_ar5416 | ath_ar9160 | ath_ar9280 | ath_ar9285 | \ ath_ar9287 \ compile-with "${NORMAL_C} -I$S/dev/ath -I$S/dev/ath/ath_hal" dev/ath/ath_hal/ar5416/ar5416_phy.c \ optional ath_hal | ath_ar5416 | ath_ar9160 | ath_ar9280 | ath_ar9285 | \ ath_ar9287 \ compile-with "${NORMAL_C} -I$S/dev/ath -I$S/dev/ath/ath_hal" dev/ath/ath_hal/ar5416/ar5416_power.c \ optional ath_hal | ath_ar5416 | ath_ar9160 | ath_ar9280 | ath_ar9285 | \ ath_ar9287 \ compile-with "${NORMAL_C} -I$S/dev/ath -I$S/dev/ath/ath_hal" dev/ath/ath_hal/ar5416/ar5416_radar.c \ optional ath_hal | ath_ar5416 | ath_ar9160 | ath_ar9280 | ath_ar9285 | \ ath_ar9287 \ compile-with "${NORMAL_C} -I$S/dev/ath -I$S/dev/ath/ath_hal" dev/ath/ath_hal/ar5416/ar5416_recv.c \ optional ath_hal | ath_ar5416 | ath_ar9160 | ath_ar9280 | ath_ar9285 | \ ath_ar9287 \ compile-with "${NORMAL_C} -I$S/dev/ath -I$S/dev/ath/ath_hal" dev/ath/ath_hal/ar5416/ar5416_reset.c \ optional ath_hal | ath_ar5416 | ath_ar9160 | ath_ar9280 | ath_ar9285 | \ ath_ar9287 \ compile-with "${NORMAL_C} -I$S/dev/ath -I$S/dev/ath/ath_hal" dev/ath/ath_hal/ar5416/ar5416_spectral.c \ optional ath_hal | ath_ar5416 | ath_ar9160 | ath_ar9280 | ath_ar9285 | \ ath_ar9287 \ compile-with "${NORMAL_C} -I$S/dev/ath -I$S/dev/ath/ath_hal" dev/ath/ath_hal/ar5416/ar5416_xmit.c \ optional ath_hal | ath_ar5416 | ath_ar9160 | ath_ar9280 | ath_ar9285 | \ ath_ar9287 \ compile-with "${NORMAL_C} -I$S/dev/ath -I$S/dev/ath/ath_hal" # ar9130 (depends upon ar5416) - also requires AH_SUPPORT_AR9130 # # Since this is an embedded MAC SoC, there's no need to compile it into the # default HAL. dev/ath/ath_hal/ar9001/ar9130_attach.c optional ath_ar9130 \ compile-with "${NORMAL_C} -I$S/dev/ath -I$S/dev/ath/ath_hal" dev/ath/ath_hal/ar9001/ar9130_phy.c optional ath_ar9130 \ compile-with "${NORMAL_C} -I$S/dev/ath -I$S/dev/ath/ath_hal" dev/ath/ath_hal/ar9001/ar9130_eeprom.c optional ath_ar9130 \ compile-with "${NORMAL_C} -I$S/dev/ath -I$S/dev/ath/ath_hal" # ar9160 (depends on ar5416) dev/ath/ath_hal/ar9001/ar9160_attach.c optional ath_hal | ath_ar9160 \ compile-with "${NORMAL_C} -I$S/dev/ath -I$S/dev/ath/ath_hal" # ar9280 (depends on ar5416) dev/ath/ath_hal/ar9002/ar9280_attach.c optional ath_hal | ath_ar9280 | \ ath_ar9285 \ compile-with "${NORMAL_C} -I$S/dev/ath -I$S/dev/ath/ath_hal" dev/ath/ath_hal/ar9002/ar9280_olc.c optional ath_hal | ath_ar9280 | \ ath_ar9285 \ compile-with "${NORMAL_C} -I$S/dev/ath -I$S/dev/ath/ath_hal" # ar9285 (depends on ar5416 and ar9280) dev/ath/ath_hal/ar9002/ar9285_attach.c optional ath_hal | ath_ar9285 \ compile-with "${NORMAL_C} -I$S/dev/ath -I$S/dev/ath/ath_hal" dev/ath/ath_hal/ar9002/ar9285_btcoex.c optional ath_hal | ath_ar9285 \ compile-with "${NORMAL_C} -I$S/dev/ath -I$S/dev/ath/ath_hal" dev/ath/ath_hal/ar9002/ar9285_reset.c optional ath_hal | ath_ar9285 \ compile-with "${NORMAL_C} -I$S/dev/ath -I$S/dev/ath/ath_hal" dev/ath/ath_hal/ar9002/ar9285_cal.c optional ath_hal | ath_ar9285 \ compile-with "${NORMAL_C} -I$S/dev/ath -I$S/dev/ath/ath_hal" dev/ath/ath_hal/ar9002/ar9285_phy.c optional ath_hal | ath_ar9285 \ compile-with "${NORMAL_C} -I$S/dev/ath -I$S/dev/ath/ath_hal" dev/ath/ath_hal/ar9002/ar9285_diversity.c optional ath_hal | ath_ar9285 \ compile-with "${NORMAL_C} -I$S/dev/ath -I$S/dev/ath/ath_hal" # ar9287 (depends on ar5416) dev/ath/ath_hal/ar9002/ar9287_attach.c optional ath_hal | ath_ar9287 \ compile-with "${NORMAL_C} -I$S/dev/ath -I$S/dev/ath/ath_hal" dev/ath/ath_hal/ar9002/ar9287_reset.c optional ath_hal | ath_ar9287 \ compile-with "${NORMAL_C} -I$S/dev/ath -I$S/dev/ath/ath_hal" dev/ath/ath_hal/ar9002/ar9287_cal.c optional ath_hal | ath_ar9287 \ compile-with "${NORMAL_C} -I$S/dev/ath -I$S/dev/ath/ath_hal" dev/ath/ath_hal/ar9002/ar9287_olc.c optional ath_hal | ath_ar9287 \ compile-with "${NORMAL_C} -I$S/dev/ath -I$S/dev/ath/ath_hal" # ar9300 contrib/dev/ath/ath_hal/ar9300/ar9300_ani.c optional ath_hal | ath_ar9300 \ compile-with "${NORMAL_C} -I$S/dev/ath -I$S/dev/ath/ath_hal -I$S/contrib/dev/ath/ath_hal" contrib/dev/ath/ath_hal/ar9300/ar9300_attach.c optional ath_hal | ath_ar9300 \ compile-with "${NORMAL_C} -I$S/dev/ath -I$S/dev/ath/ath_hal -I$S/contrib/dev/ath/ath_hal" contrib/dev/ath/ath_hal/ar9300/ar9300_beacon.c optional ath_hal | ath_ar9300 \ compile-with "${NORMAL_C} -I$S/dev/ath -I$S/dev/ath/ath_hal -I$S/contrib/dev/ath/ath_hal" contrib/dev/ath/ath_hal/ar9300/ar9300_eeprom.c optional ath_hal | ath_ar9300 \ compile-with "${NORMAL_C} -I$S/dev/ath -I$S/dev/ath/ath_hal -I$S/contrib/dev/ath/ath_hal ${NO_WCONSTANT_CONVERSION}" contrib/dev/ath/ath_hal/ar9300/ar9300_freebsd.c optional ath_hal | ath_ar9300 \ compile-with "${NORMAL_C} -I$S/dev/ath -I$S/dev/ath/ath_hal -I$S/contrib/dev/ath/ath_hal" contrib/dev/ath/ath_hal/ar9300/ar9300_gpio.c optional ath_hal | ath_ar9300 \ compile-with "${NORMAL_C} -I$S/dev/ath -I$S/dev/ath/ath_hal -I$S/contrib/dev/ath/ath_hal" contrib/dev/ath/ath_hal/ar9300/ar9300_interrupts.c optional ath_hal | ath_ar9300 \ compile-with "${NORMAL_C} -I$S/dev/ath -I$S/dev/ath/ath_hal -I$S/contrib/dev/ath/ath_hal" contrib/dev/ath/ath_hal/ar9300/ar9300_keycache.c optional ath_hal | ath_ar9300 \ compile-with "${NORMAL_C} -I$S/dev/ath -I$S/dev/ath/ath_hal -I$S/contrib/dev/ath/ath_hal" contrib/dev/ath/ath_hal/ar9300/ar9300_mci.c optional ath_hal | ath_ar9300 \ compile-with "${NORMAL_C} -I$S/dev/ath -I$S/dev/ath/ath_hal -I$S/contrib/dev/ath/ath_hal" contrib/dev/ath/ath_hal/ar9300/ar9300_misc.c optional ath_hal | ath_ar9300 \ compile-with "${NORMAL_C} -I$S/dev/ath -I$S/dev/ath/ath_hal -I$S/contrib/dev/ath/ath_hal" contrib/dev/ath/ath_hal/ar9300/ar9300_paprd.c optional ath_hal | ath_ar9300 \ compile-with "${NORMAL_C} -I$S/dev/ath -I$S/dev/ath/ath_hal -I$S/contrib/dev/ath/ath_hal" contrib/dev/ath/ath_hal/ar9300/ar9300_phy.c optional ath_hal | ath_ar9300 \ compile-with "${NORMAL_C} -I$S/dev/ath -I$S/dev/ath/ath_hal -I$S/contrib/dev/ath/ath_hal" contrib/dev/ath/ath_hal/ar9300/ar9300_power.c optional ath_hal | ath_ar9300 \ compile-with "${NORMAL_C} -I$S/dev/ath -I$S/dev/ath/ath_hal -I$S/contrib/dev/ath/ath_hal" contrib/dev/ath/ath_hal/ar9300/ar9300_radar.c optional ath_hal | ath_ar9300 \ compile-with "${NORMAL_C} -I$S/dev/ath -I$S/dev/ath/ath_hal -I$S/contrib/dev/ath/ath_hal" contrib/dev/ath/ath_hal/ar9300/ar9300_radio.c optional ath_hal | ath_ar9300 \ compile-with "${NORMAL_C} -I$S/dev/ath -I$S/dev/ath/ath_hal -I$S/contrib/dev/ath/ath_hal" contrib/dev/ath/ath_hal/ar9300/ar9300_recv.c optional ath_hal | ath_ar9300 \ compile-with "${NORMAL_C} -I$S/dev/ath -I$S/dev/ath/ath_hal -I$S/contrib/dev/ath/ath_hal" contrib/dev/ath/ath_hal/ar9300/ar9300_recv_ds.c optional ath_hal | ath_ar9300 \ compile-with "${NORMAL_C} -I$S/dev/ath -I$S/dev/ath/ath_hal -I$S/contrib/dev/ath/ath_hal" contrib/dev/ath/ath_hal/ar9300/ar9300_reset.c optional ath_hal | ath_ar9300 \ compile-with "${NORMAL_C} -I$S/dev/ath -I$S/dev/ath/ath_hal -I$S/contrib/dev/ath/ath_hal ${NO_WSOMETIMES_UNINITIALIZED} -Wno-unused-function" contrib/dev/ath/ath_hal/ar9300/ar9300_stub.c optional ath_hal | ath_ar9300 \ compile-with "${NORMAL_C} -I$S/dev/ath -I$S/dev/ath/ath_hal -I$S/contrib/dev/ath/ath_hal" contrib/dev/ath/ath_hal/ar9300/ar9300_stub_funcs.c optional ath_hal | ath_ar9300 \ compile-with "${NORMAL_C} -I$S/dev/ath -I$S/dev/ath/ath_hal -I$S/contrib/dev/ath/ath_hal" contrib/dev/ath/ath_hal/ar9300/ar9300_spectral.c optional ath_hal | ath_ar9300 \ compile-with "${NORMAL_C} -I$S/dev/ath -I$S/dev/ath/ath_hal -I$S/contrib/dev/ath/ath_hal" contrib/dev/ath/ath_hal/ar9300/ar9300_timer.c optional ath_hal | ath_ar9300 \ compile-with "${NORMAL_C} -I$S/dev/ath -I$S/dev/ath/ath_hal -I$S/contrib/dev/ath/ath_hal" contrib/dev/ath/ath_hal/ar9300/ar9300_xmit.c optional ath_hal | ath_ar9300 \ compile-with "${NORMAL_C} -I$S/dev/ath -I$S/dev/ath/ath_hal -I$S/contrib/dev/ath/ath_hal" contrib/dev/ath/ath_hal/ar9300/ar9300_xmit_ds.c optional ath_hal | ath_ar9300 \ compile-with "${NORMAL_C} -I$S/dev/ath -I$S/dev/ath/ath_hal -I$S/contrib/dev/ath/ath_hal" # rf backends dev/ath/ath_hal/ar5212/ar2316.c optional ath_rf2316 \ compile-with "${NORMAL_C} -I$S/dev/ath -I$S/dev/ath/ath_hal" dev/ath/ath_hal/ar5212/ar2317.c optional ath_rf2317 \ compile-with "${NORMAL_C} -I$S/dev/ath -I$S/dev/ath/ath_hal" dev/ath/ath_hal/ar5212/ar2413.c optional ath_hal | ath_rf2413 \ compile-with "${NORMAL_C} -I$S/dev/ath -I$S/dev/ath/ath_hal" dev/ath/ath_hal/ar5212/ar2425.c optional ath_hal | ath_rf2425 | ath_rf2417 \ compile-with "${NORMAL_C} -I$S/dev/ath -I$S/dev/ath/ath_hal" dev/ath/ath_hal/ar5212/ar5111.c optional ath_hal | ath_rf5111 \ compile-with "${NORMAL_C} -I$S/dev/ath -I$S/dev/ath/ath_hal" dev/ath/ath_hal/ar5212/ar5112.c optional ath_hal | ath_rf5112 \ compile-with "${NORMAL_C} -I$S/dev/ath -I$S/dev/ath/ath_hal" dev/ath/ath_hal/ar5212/ar5413.c optional ath_hal | ath_rf5413 \ compile-with "${NORMAL_C} -I$S/dev/ath -I$S/dev/ath/ath_hal" dev/ath/ath_hal/ar5416/ar2133.c optional ath_hal | ath_ar5416 | \ ath_ar9130 | ath_ar9160 | ath_ar9280 \ compile-with "${NORMAL_C} -I$S/dev/ath -I$S/dev/ath/ath_hal" dev/ath/ath_hal/ar9002/ar9280.c optional ath_hal | ath_ar9280 | ath_ar9285 \ compile-with "${NORMAL_C} -I$S/dev/ath -I$S/dev/ath/ath_hal" dev/ath/ath_hal/ar9002/ar9285.c optional ath_hal | ath_ar9285 \ compile-with "${NORMAL_C} -I$S/dev/ath -I$S/dev/ath/ath_hal" dev/ath/ath_hal/ar9002/ar9287.c optional ath_hal | ath_ar9287 \ compile-with "${NORMAL_C} -I$S/dev/ath -I$S/dev/ath/ath_hal" # ath rate control algorithms dev/ath/ath_rate/amrr/amrr.c optional ath_rate_amrr \ compile-with "${NORMAL_C} -I$S/dev/ath" dev/ath/ath_rate/onoe/onoe.c optional ath_rate_onoe \ compile-with "${NORMAL_C} -I$S/dev/ath" dev/ath/ath_rate/sample/sample.c optional ath_rate_sample \ compile-with "${NORMAL_C} -I$S/dev/ath" # ath DFS modules dev/ath/ath_dfs/null/dfs_null.c optional ath \ compile-with "${NORMAL_C} -I$S/dev/ath" # dev/bce/if_bce.c optional bce dev/bfe/if_bfe.c optional bfe dev/bge/if_bge.c optional bge dev/bhnd/bhnd.c optional bhnd dev/bhnd/bhnd_erom.c optional bhnd dev/bhnd/bhnd_erom_if.m optional bhnd dev/bhnd/bhnd_subr.c optional bhnd dev/bhnd/bhnd_bus_if.m optional bhnd dev/bhnd/bhndb/bhnd_bhndb.c optional bhndb bhnd dev/bhnd/bhndb/bhndb.c optional bhndb bhnd dev/bhnd/bhndb/bhndb_bus_if.m optional bhndb bhnd dev/bhnd/bhndb/bhndb_hwdata.c optional bhndb bhnd dev/bhnd/bhndb/bhndb_if.m optional bhndb bhnd -dev/bhnd/bhndb/bhndb_pci.c optional bhndb bhnd pci -dev/bhnd/bhndb/bhndb_pci_hwdata.c optional bhndb bhnd pci -dev/bhnd/bhndb/bhndb_pci_sprom.c optional bhndb bhnd pci +dev/bhnd/bhndb/bhndb_pci.c optional bhndb_pci bhndb bhnd pci +dev/bhnd/bhndb/bhndb_pci_hwdata.c optional bhndb_pci bhndb bhnd pci +dev/bhnd/bhndb/bhndb_pci_sprom.c optional bhndb_pci bhndb bhnd pci dev/bhnd/bhndb/bhndb_subr.c optional bhndb bhnd dev/bhnd/bcma/bcma.c optional bcma bhnd dev/bhnd/bcma/bcma_bhndb.c optional bcma bhnd bhndb dev/bhnd/bcma/bcma_erom.c optional bcma bhnd dev/bhnd/bcma/bcma_subr.c optional bcma bhnd dev/bhnd/cores/chipc/bhnd_chipc_if.m optional bhnd dev/bhnd/cores/chipc/bhnd_sprom_chipc.c optional bhnd dev/bhnd/cores/chipc/bhnd_pmu_chipc.c optional bhnd dev/bhnd/cores/chipc/chipc.c optional bhnd dev/bhnd/cores/chipc/chipc_cfi.c optional bhnd cfi dev/bhnd/cores/chipc/chipc_gpio.c optional bhnd gpio dev/bhnd/cores/chipc/chipc_slicer.c optional bhnd cfi | bhnd spibus dev/bhnd/cores/chipc/chipc_spi.c optional bhnd spibus dev/bhnd/cores/chipc/chipc_subr.c optional bhnd dev/bhnd/cores/chipc/pwrctl/bhnd_pwrctl.c optional bhnd dev/bhnd/cores/chipc/pwrctl/bhnd_pwrctl_if.m optional bhnd dev/bhnd/cores/chipc/pwrctl/bhnd_pwrctl_hostb_if.m optional bhnd dev/bhnd/cores/chipc/pwrctl/bhnd_pwrctl_subr.c optional bhnd dev/bhnd/cores/pci/bhnd_pci.c optional bhnd pci dev/bhnd/cores/pci/bhnd_pci_hostb.c optional bhndb bhnd pci dev/bhnd/cores/pci/bhnd_pcib.c optional bhnd_pcib bhnd pci dev/bhnd/cores/pcie2/bhnd_pcie2.c optional bhnd pci dev/bhnd/cores/pcie2/bhnd_pcie2_hostb.c optional bhndb bhnd pci dev/bhnd/cores/pcie2/bhnd_pcie2b.c optional bhnd_pcie2b bhnd pci dev/bhnd/cores/pmu/bhnd_pmu.c optional bhnd dev/bhnd/cores/pmu/bhnd_pmu_core.c optional bhnd dev/bhnd/cores/pmu/bhnd_pmu_if.m optional bhnd dev/bhnd/cores/pmu/bhnd_pmu_subr.c optional bhnd dev/bhnd/nvram/bhnd_nvram_data.c optional bhnd dev/bhnd/nvram/bhnd_nvram_data_bcm.c optional bhnd dev/bhnd/nvram/bhnd_nvram_data_bcmraw.c optional bhnd dev/bhnd/nvram/bhnd_nvram_data_btxt.c optional bhnd dev/bhnd/nvram/bhnd_nvram_data_sprom.c optional bhnd dev/bhnd/nvram/bhnd_nvram_data_sprom_subr.c optional bhnd dev/bhnd/nvram/bhnd_nvram_data_tlv.c optional bhnd dev/bhnd/nvram/bhnd_nvram_if.m optional bhnd dev/bhnd/nvram/bhnd_nvram_io.c optional bhnd dev/bhnd/nvram/bhnd_nvram_iobuf.c optional bhnd dev/bhnd/nvram/bhnd_nvram_ioptr.c optional bhnd dev/bhnd/nvram/bhnd_nvram_iores.c optional bhnd dev/bhnd/nvram/bhnd_nvram_plist.c optional bhnd dev/bhnd/nvram/bhnd_nvram_store.c optional bhnd dev/bhnd/nvram/bhnd_nvram_store_subr.c optional bhnd dev/bhnd/nvram/bhnd_nvram_subr.c optional bhnd dev/bhnd/nvram/bhnd_nvram_value.c optional bhnd dev/bhnd/nvram/bhnd_nvram_value_fmts.c optional bhnd dev/bhnd/nvram/bhnd_nvram_value_prf.c optional bhnd dev/bhnd/nvram/bhnd_nvram_value_subr.c optional bhnd dev/bhnd/nvram/bhnd_sprom.c optional bhnd dev/bhnd/siba/siba.c optional siba bhnd dev/bhnd/siba/siba_bhndb.c optional siba bhnd bhndb dev/bhnd/siba/siba_erom.c optional siba bhnd dev/bhnd/siba/siba_subr.c optional siba bhnd # dev/bktr/bktr_audio.c optional bktr pci dev/bktr/bktr_card.c optional bktr pci dev/bktr/bktr_core.c optional bktr pci dev/bktr/bktr_i2c.c optional bktr pci smbus dev/bktr/bktr_os.c optional bktr pci dev/bktr/bktr_tuner.c optional bktr pci dev/bktr/msp34xx.c optional bktr pci dev/bnxt/bnxt_hwrm.c optional bnxt iflib pci dev/bnxt/bnxt_sysctl.c optional bnxt iflib pci dev/bnxt/bnxt_txrx.c optional bnxt iflib pci dev/bnxt/if_bnxt.c optional bnxt iflib pci dev/buslogic/bt.c optional bt dev/buslogic/bt_isa.c optional bt isa dev/buslogic/bt_pci.c optional bt pci dev/bwi/bwimac.c optional bwi dev/bwi/bwiphy.c optional bwi dev/bwi/bwirf.c optional bwi dev/bwi/if_bwi.c optional bwi dev/bwi/if_bwi_pci.c optional bwi pci # XXX Work around clang warnings, until maintainer approves fix. -dev/bwn/if_bwn.c optional bwn siba_bwn \ +dev/bwn/if_bwn.c optional bwn bhnd \ compile-with "${NORMAL_C} ${NO_WSOMETIMES_UNINITIALIZED}" -dev/bwn/if_bwn_bhnd.c optional bwn bhnd -dev/bwn/if_bwn_pci.c optional bwn pci bhnd bhndb -dev/bwn/if_bwn_phy_common.c optional bwn siba_bwn -dev/bwn/if_bwn_phy_g.c optional bwn siba_bwn \ +dev/bwn/if_bwn_pci.c optional bwn pci bhnd bhndb bhndb_pci +dev/bwn/if_bwn_phy_common.c optional bwn bhnd +dev/bwn/if_bwn_phy_g.c optional bwn bhnd \ compile-with "${NORMAL_C} ${NO_WSOMETIMES_UNINITIALIZED} ${NO_WCONSTANT_CONVERSION}" -dev/bwn/if_bwn_phy_lp.c optional bwn siba_bwn \ +dev/bwn/if_bwn_phy_lp.c optional bwn bhnd \ compile-with "${NORMAL_C} ${NO_WSOMETIMES_UNINITIALIZED}" -dev/bwn/if_bwn_phy_n.c optional bwn siba_bwn -dev/bwn/if_bwn_siba.c optional bwn siba_bwn -dev/bwn/if_bwn_siba_compat.c optional bwn bhnd !bwn_use_siba -dev/bwn/if_bwn_util.c optional bwn siba_bwn +dev/bwn/if_bwn_phy_n.c optional bwn bhnd +dev/bwn/if_bwn_util.c optional bwn bhnd dev/cardbus/cardbus.c optional cardbus dev/cardbus/cardbus_cis.c optional cardbus dev/cardbus/cardbus_device.c optional cardbus dev/cas/if_cas.c optional cas dev/cfi/cfi_bus_fdt.c optional cfi fdt dev/cfi/cfi_bus_nexus.c optional cfi dev/cfi/cfi_core.c optional cfi dev/cfi/cfi_dev.c optional cfi dev/cfi/cfi_disk.c optional cfid dev/chromebook_platform/chromebook_platform.c optional chromebook_platform dev/ciss/ciss.c optional ciss dev/cm/smc90cx6.c optional cm dev/cmx/cmx.c optional cmx dev/cmx/cmx_pccard.c optional cmx pccard dev/cpufreq/ichss.c optional cpufreq pci dev/cs/if_cs.c optional cs dev/cs/if_cs_isa.c optional cs isa dev/cs/if_cs_pccard.c optional cs pccard dev/cxgb/cxgb_main.c optional cxgb pci \ compile-with "${NORMAL_C} -I$S/dev/cxgb" dev/cxgb/cxgb_sge.c optional cxgb pci \ compile-with "${NORMAL_C} -I$S/dev/cxgb" dev/cxgb/common/cxgb_mc5.c optional cxgb pci \ compile-with "${NORMAL_C} -I$S/dev/cxgb" dev/cxgb/common/cxgb_vsc7323.c optional cxgb pci \ compile-with "${NORMAL_C} -I$S/dev/cxgb" dev/cxgb/common/cxgb_vsc8211.c optional cxgb pci \ compile-with "${NORMAL_C} -I$S/dev/cxgb" dev/cxgb/common/cxgb_ael1002.c optional cxgb pci \ compile-with "${NORMAL_C} -I$S/dev/cxgb" dev/cxgb/common/cxgb_aq100x.c optional cxgb pci \ compile-with "${NORMAL_C} -I$S/dev/cxgb" dev/cxgb/common/cxgb_mv88e1xxx.c optional cxgb pci \ compile-with "${NORMAL_C} -I$S/dev/cxgb" dev/cxgb/common/cxgb_xgmac.c optional cxgb pci \ compile-with "${NORMAL_C} -I$S/dev/cxgb" dev/cxgb/common/cxgb_t3_hw.c optional cxgb pci \ compile-with "${NORMAL_C} -I$S/dev/cxgb" dev/cxgb/common/cxgb_tn1010.c optional cxgb pci \ compile-with "${NORMAL_C} -I$S/dev/cxgb" dev/cxgb/sys/uipc_mvec.c optional cxgb pci \ compile-with "${NORMAL_C} -I$S/dev/cxgb" dev/cxgb/cxgb_t3fw.c optional cxgb cxgb_t3fw \ compile-with "${NORMAL_C} -I$S/dev/cxgb" dev/cxgbe/t4_if.m optional cxgbe pci dev/cxgbe/t4_iov.c optional cxgbe pci \ compile-with "${NORMAL_C} -I$S/dev/cxgbe" dev/cxgbe/t4_mp_ring.c optional cxgbe pci \ compile-with "${NORMAL_C} -I$S/dev/cxgbe" dev/cxgbe/t4_main.c optional cxgbe pci \ compile-with "${NORMAL_C} -I$S/dev/cxgbe" dev/cxgbe/t4_netmap.c optional cxgbe pci \ compile-with "${NORMAL_C} -I$S/dev/cxgbe" dev/cxgbe/t4_sched.c optional cxgbe pci \ compile-with "${NORMAL_C} -I$S/dev/cxgbe" dev/cxgbe/t4_sge.c optional cxgbe pci \ compile-with "${NORMAL_C} -I$S/dev/cxgbe" dev/cxgbe/t4_l2t.c optional cxgbe pci \ compile-with "${NORMAL_C} -I$S/dev/cxgbe" dev/cxgbe/t4_tracer.c optional cxgbe pci \ compile-with "${NORMAL_C} -I$S/dev/cxgbe" dev/cxgbe/t4_vf.c optional cxgbev pci \ compile-with "${NORMAL_C} -I$S/dev/cxgbe" dev/cxgbe/common/t4_hw.c optional cxgbe pci \ compile-with "${NORMAL_C} -I$S/dev/cxgbe" dev/cxgbe/common/t4vf_hw.c optional cxgbev pci \ compile-with "${NORMAL_C} -I$S/dev/cxgbe" dev/cxgbe/cudbg/cudbg_common.c optional cxgbe \ compile-with "${NORMAL_C} -I$S/dev/cxgbe" dev/cxgbe/cudbg/cudbg_flash_utils.c optional cxgbe \ compile-with "${NORMAL_C} -I$S/dev/cxgbe" dev/cxgbe/cudbg/cudbg_lib.c optional cxgbe \ compile-with "${NORMAL_C} -I$S/dev/cxgbe" dev/cxgbe/cudbg/cudbg_wtp.c optional cxgbe \ compile-with "${NORMAL_C} -I$S/dev/cxgbe" dev/cxgbe/cudbg/fastlz.c optional cxgbe \ compile-with "${NORMAL_C} -I$S/dev/cxgbe" dev/cxgbe/cudbg/fastlz_api.c optional cxgbe \ compile-with "${NORMAL_C} -I$S/dev/cxgbe" t4fw_cfg.c optional cxgbe \ compile-with "${AWK} -f $S/tools/fw_stub.awk t4fw_cfg.fw:t4fw_cfg t4fw_cfg_uwire.fw:t4fw_cfg_uwire t4fw.fw:t4fw -mt4fw_cfg -c${.TARGET}" \ no-implicit-rule before-depend local \ clean "t4fw_cfg.c" t4fw_cfg.fwo optional cxgbe \ dependency "t4fw_cfg.fw" \ compile-with "${NORMAL_FWO}" \ no-implicit-rule \ clean "t4fw_cfg.fwo" t4fw_cfg.fw optional cxgbe \ dependency "$S/dev/cxgbe/firmware/t4fw_cfg.txt" \ compile-with "${CP} ${.ALLSRC} ${.TARGET}" \ no-obj no-implicit-rule \ clean "t4fw_cfg.fw" t4fw_cfg_uwire.fwo optional cxgbe \ dependency "t4fw_cfg_uwire.fw" \ compile-with "${NORMAL_FWO}" \ no-implicit-rule \ clean "t4fw_cfg_uwire.fwo" t4fw_cfg_uwire.fw optional cxgbe \ dependency "$S/dev/cxgbe/firmware/t4fw_cfg_uwire.txt" \ compile-with "${CP} ${.ALLSRC} ${.TARGET}" \ no-obj no-implicit-rule \ clean "t4fw_cfg_uwire.fw" t4fw.fwo optional cxgbe \ dependency "t4fw.fw" \ compile-with "${NORMAL_FWO}" \ no-implicit-rule \ clean "t4fw.fwo" t4fw.fw optional cxgbe \ dependency "$S/dev/cxgbe/firmware/t4fw-1.16.63.0.bin.uu" \ compile-with "${NORMAL_FW}" \ no-obj no-implicit-rule \ clean "t4fw.fw" t5fw_cfg.c optional cxgbe \ compile-with "${AWK} -f $S/tools/fw_stub.awk t5fw_cfg.fw:t5fw_cfg t5fw_cfg_uwire.fw:t5fw_cfg_uwire t5fw.fw:t5fw -mt5fw_cfg -c${.TARGET}" \ no-implicit-rule before-depend local \ clean "t5fw_cfg.c" t5fw_cfg.fwo optional cxgbe \ dependency "t5fw_cfg.fw" \ compile-with "${NORMAL_FWO}" \ no-implicit-rule \ clean "t5fw_cfg.fwo" t5fw_cfg.fw optional cxgbe \ dependency "$S/dev/cxgbe/firmware/t5fw_cfg.txt" \ compile-with "${CP} ${.ALLSRC} ${.TARGET}" \ no-obj no-implicit-rule \ clean "t5fw_cfg.fw" t5fw_cfg_uwire.fwo optional cxgbe \ dependency "t5fw_cfg_uwire.fw" \ compile-with "${NORMAL_FWO}" \ no-implicit-rule \ clean "t5fw_cfg_uwire.fwo" t5fw_cfg_uwire.fw optional cxgbe \ dependency "$S/dev/cxgbe/firmware/t5fw_cfg_uwire.txt" \ compile-with "${CP} ${.ALLSRC} ${.TARGET}" \ no-obj no-implicit-rule \ clean "t5fw_cfg_uwire.fw" t5fw.fwo optional cxgbe \ dependency "t5fw.fw" \ compile-with "${NORMAL_FWO}" \ no-implicit-rule \ clean "t5fw.fwo" t5fw.fw optional cxgbe \ dependency "$S/dev/cxgbe/firmware/t5fw-1.16.63.0.bin.uu" \ compile-with "${NORMAL_FW}" \ no-obj no-implicit-rule \ clean "t5fw.fw" t6fw_cfg.c optional cxgbe \ compile-with "${AWK} -f $S/tools/fw_stub.awk t6fw_cfg.fw:t6fw_cfg t6fw_cfg_uwire.fw:t6fw_cfg_uwire t6fw.fw:t6fw -mt6fw_cfg -c${.TARGET}" \ no-implicit-rule before-depend local \ clean "t6fw_cfg.c" t6fw_cfg.fwo optional cxgbe \ dependency "t6fw_cfg.fw" \ compile-with "${NORMAL_FWO}" \ no-implicit-rule \ clean "t6fw_cfg.fwo" t6fw_cfg.fw optional cxgbe \ dependency "$S/dev/cxgbe/firmware/t6fw_cfg.txt" \ compile-with "${CP} ${.ALLSRC} ${.TARGET}" \ no-obj no-implicit-rule \ clean "t6fw_cfg.fw" t6fw_cfg_uwire.fwo optional cxgbe \ dependency "t6fw_cfg_uwire.fw" \ compile-with "${NORMAL_FWO}" \ no-implicit-rule \ clean "t6fw_cfg_uwire.fwo" t6fw_cfg_uwire.fw optional cxgbe \ dependency "$S/dev/cxgbe/firmware/t6fw_cfg_uwire.txt" \ compile-with "${CP} ${.ALLSRC} ${.TARGET}" \ no-obj no-implicit-rule \ clean "t6fw_cfg_uwire.fw" t6fw.fwo optional cxgbe \ dependency "t6fw.fw" \ compile-with "${NORMAL_FWO}" \ no-implicit-rule \ clean "t6fw.fwo" t6fw.fw optional cxgbe \ dependency "$S/dev/cxgbe/firmware/t6fw-1.16.63.0.bin.uu" \ compile-with "${NORMAL_FW}" \ no-obj no-implicit-rule \ clean "t6fw.fw" dev/cxgbe/crypto/t4_crypto.c optional ccr \ compile-with "${NORMAL_C} -I$S/dev/cxgbe" dev/cy/cy.c optional cy dev/cy/cy_isa.c optional cy isa dev/cy/cy_pci.c optional cy pci dev/cyapa/cyapa.c optional cyapa iicbus dev/dc/if_dc.c optional dc pci dev/dc/dcphy.c optional dc pci dev/dc/pnphy.c optional dc pci dev/dcons/dcons.c optional dcons dev/dcons/dcons_crom.c optional dcons_crom dev/dcons/dcons_os.c optional dcons dev/de/if_de.c optional de pci dev/dme/if_dme.c optional dme dev/dpt/dpt_pci.c optional dpt pci dev/dpt/dpt_scsi.c optional dpt dev/drm/ati_pcigart.c optional drm dev/drm/drm_agpsupport.c optional drm dev/drm/drm_auth.c optional drm dev/drm/drm_bufs.c optional drm dev/drm/drm_context.c optional drm dev/drm/drm_dma.c optional drm dev/drm/drm_drawable.c optional drm dev/drm/drm_drv.c optional drm dev/drm/drm_fops.c optional drm dev/drm/drm_hashtab.c optional drm dev/drm/drm_ioctl.c optional drm dev/drm/drm_irq.c optional drm dev/drm/drm_lock.c optional drm dev/drm/drm_memory.c optional drm dev/drm/drm_mm.c optional drm dev/drm/drm_pci.c optional drm dev/drm/drm_scatter.c optional drm dev/drm/drm_sman.c optional drm dev/drm/drm_sysctl.c optional drm dev/drm/drm_vm.c optional drm dev/drm/mach64_dma.c optional mach64drm dev/drm/mach64_drv.c optional mach64drm dev/drm/mach64_irq.c optional mach64drm dev/drm/mach64_state.c optional mach64drm dev/drm/mga_dma.c optional mgadrm dev/drm/mga_drv.c optional mgadrm dev/drm/mga_irq.c optional mgadrm dev/drm/mga_state.c optional mgadrm dev/drm/mga_warp.c optional mgadrm dev/drm/r128_cce.c optional r128drm \ compile-with "${NORMAL_C} ${NO_WCONSTANT_CONVERSION}" dev/drm/r128_drv.c optional r128drm dev/drm/r128_irq.c optional r128drm dev/drm/r128_state.c optional r128drm dev/drm/savage_bci.c optional savagedrm dev/drm/savage_drv.c optional savagedrm dev/drm/savage_state.c optional savagedrm dev/drm/sis_drv.c optional sisdrm dev/drm/sis_ds.c optional sisdrm dev/drm/sis_mm.c optional sisdrm dev/drm/tdfx_drv.c optional tdfxdrm dev/drm/via_dma.c optional viadrm dev/drm/via_dmablit.c optional viadrm dev/drm/via_drv.c optional viadrm dev/drm/via_irq.c optional viadrm dev/drm/via_map.c optional viadrm dev/drm/via_mm.c optional viadrm dev/drm/via_verifier.c optional viadrm dev/drm/via_video.c optional viadrm dev/drm2/drm_agpsupport.c optional drm2 dev/drm2/drm_auth.c optional drm2 dev/drm2/drm_bufs.c optional drm2 dev/drm2/drm_buffer.c optional drm2 dev/drm2/drm_context.c optional drm2 dev/drm2/drm_crtc.c optional drm2 dev/drm2/drm_crtc_helper.c optional drm2 dev/drm2/drm_dma.c optional drm2 dev/drm2/drm_dp_helper.c optional drm2 dev/drm2/drm_dp_iic_helper.c optional drm2 dev/drm2/drm_drv.c optional drm2 dev/drm2/drm_edid.c optional drm2 dev/drm2/drm_fb_helper.c optional drm2 dev/drm2/drm_fops.c optional drm2 dev/drm2/drm_gem.c optional drm2 dev/drm2/drm_gem_names.c optional drm2 dev/drm2/drm_global.c optional drm2 dev/drm2/drm_hashtab.c optional drm2 dev/drm2/drm_ioctl.c optional drm2 dev/drm2/drm_irq.c optional drm2 dev/drm2/drm_linux_list_sort.c optional drm2 dev/drm2/drm_lock.c optional drm2 dev/drm2/drm_memory.c optional drm2 dev/drm2/drm_mm.c optional drm2 dev/drm2/drm_modes.c optional drm2 dev/drm2/drm_pci.c optional drm2 dev/drm2/drm_platform.c optional drm2 dev/drm2/drm_scatter.c optional drm2 dev/drm2/drm_stub.c optional drm2 dev/drm2/drm_sysctl.c optional drm2 dev/drm2/drm_vm.c optional drm2 dev/drm2/drm_os_freebsd.c optional drm2 dev/drm2/ttm/ttm_agp_backend.c optional drm2 dev/drm2/ttm/ttm_lock.c optional drm2 dev/drm2/ttm/ttm_object.c optional drm2 dev/drm2/ttm/ttm_tt.c optional drm2 dev/drm2/ttm/ttm_bo_util.c optional drm2 dev/drm2/ttm/ttm_bo.c optional drm2 dev/drm2/ttm/ttm_bo_manager.c optional drm2 dev/drm2/ttm/ttm_execbuf_util.c optional drm2 dev/drm2/ttm/ttm_memory.c optional drm2 dev/drm2/ttm/ttm_page_alloc.c optional drm2 dev/drm2/ttm/ttm_bo_vm.c optional drm2 dev/drm2/ati_pcigart.c optional drm2 agp pci dev/ed/if_ed.c optional ed dev/ed/if_ed_novell.c optional ed dev/ed/if_ed_rtl80x9.c optional ed dev/ed/if_ed_pccard.c optional ed pccard dev/ed/if_ed_pci.c optional ed pci dev/efidev/efidev.c optional efirt dev/efidev/efirt.c optional efirt dev/efidev/efirtc.c optional efirt dev/e1000/if_em.c optional em \ compile-with "${NORMAL_C} -I$S/dev/e1000" dev/e1000/em_txrx.c optional em \ compile-with "${NORMAL_C} -I$S/dev/e1000" dev/e1000/igb_txrx.c optional em \ compile-with "${NORMAL_C} -I$S/dev/e1000" dev/e1000/e1000_80003es2lan.c optional em \ compile-with "${NORMAL_C} -I$S/dev/e1000" dev/e1000/e1000_82540.c optional em \ compile-with "${NORMAL_C} -I$S/dev/e1000" dev/e1000/e1000_82541.c optional em \ compile-with "${NORMAL_C} -I$S/dev/e1000" dev/e1000/e1000_82542.c optional em \ compile-with "${NORMAL_C} -I$S/dev/e1000" dev/e1000/e1000_82543.c optional em \ compile-with "${NORMAL_C} -I$S/dev/e1000" dev/e1000/e1000_82571.c optional em \ compile-with "${NORMAL_C} -I$S/dev/e1000" dev/e1000/e1000_82575.c optional em \ compile-with "${NORMAL_C} -I$S/dev/e1000" dev/e1000/e1000_ich8lan.c optional em \ compile-with "${NORMAL_C} -I$S/dev/e1000" dev/e1000/e1000_i210.c optional em \ compile-with "${NORMAL_C} -I$S/dev/e1000" dev/e1000/e1000_api.c optional em \ compile-with "${NORMAL_C} -I$S/dev/e1000" dev/e1000/e1000_mac.c optional em \ compile-with "${NORMAL_C} -I$S/dev/e1000" dev/e1000/e1000_manage.c optional em \ compile-with "${NORMAL_C} -I$S/dev/e1000" dev/e1000/e1000_nvm.c optional em \ compile-with "${NORMAL_C} -I$S/dev/e1000" dev/e1000/e1000_phy.c optional em \ compile-with "${NORMAL_C} -I$S/dev/e1000" dev/e1000/e1000_vf.c optional em \ compile-with "${NORMAL_C} -I$S/dev/e1000" dev/e1000/e1000_mbx.c optional em \ compile-with "${NORMAL_C} -I$S/dev/e1000" dev/e1000/e1000_osdep.c optional em \ compile-with "${NORMAL_C} -I$S/dev/e1000" dev/et/if_et.c optional et dev/ena/ena.c optional ena \ compile-with "${NORMAL_C} -I$S/contrib" dev/ena/ena_sysctl.c optional ena \ compile-with "${NORMAL_C} -I$S/contrib" contrib/ena-com/ena_com.c optional ena contrib/ena-com/ena_eth_com.c optional ena dev/ep/if_ep.c optional ep dev/ep/if_ep_isa.c optional ep isa dev/ep/if_ep_pccard.c optional ep pccard dev/esp/esp_pci.c optional esp pci dev/esp/ncr53c9x.c optional esp dev/etherswitch/arswitch/arswitch.c optional arswitch dev/etherswitch/arswitch/arswitch_reg.c optional arswitch dev/etherswitch/arswitch/arswitch_phy.c optional arswitch dev/etherswitch/arswitch/arswitch_8216.c optional arswitch dev/etherswitch/arswitch/arswitch_8226.c optional arswitch dev/etherswitch/arswitch/arswitch_8316.c optional arswitch dev/etherswitch/arswitch/arswitch_8327.c optional arswitch dev/etherswitch/arswitch/arswitch_7240.c optional arswitch dev/etherswitch/arswitch/arswitch_9340.c optional arswitch dev/etherswitch/arswitch/arswitch_vlans.c optional arswitch dev/etherswitch/etherswitch.c optional etherswitch dev/etherswitch/etherswitch_if.m optional etherswitch dev/etherswitch/ip17x/ip17x.c optional ip17x dev/etherswitch/ip17x/ip175c.c optional ip17x dev/etherswitch/ip17x/ip175d.c optional ip17x dev/etherswitch/ip17x/ip17x_phy.c optional ip17x dev/etherswitch/ip17x/ip17x_vlans.c optional ip17x dev/etherswitch/miiproxy.c optional miiproxy dev/etherswitch/rtl8366/rtl8366rb.c optional rtl8366rb dev/etherswitch/e6000sw/e6000sw.c optional e6000sw dev/etherswitch/e6000sw/e6060sw.c optional e6060sw dev/etherswitch/infineon/adm6996fc.c optional adm6996fc dev/etherswitch/micrel/ksz8995ma.c optional ksz8995ma dev/etherswitch/ukswitch/ukswitch.c optional ukswitch dev/evdev/cdev.c optional evdev dev/evdev/evdev.c optional evdev dev/evdev/evdev_mt.c optional evdev dev/evdev/evdev_utils.c optional evdev dev/evdev/uinput.c optional evdev uinput dev/ex/if_ex.c optional ex dev/ex/if_ex_isa.c optional ex isa dev/ex/if_ex_pccard.c optional ex pccard dev/exca/exca.c optional cbb dev/extres/clk/clk.c optional ext_resources clk fdt dev/extres/clk/clkdev_if.m optional ext_resources clk fdt dev/extres/clk/clknode_if.m optional ext_resources clk fdt dev/extres/clk/clk_bus.c optional ext_resources clk fdt dev/extres/clk/clk_div.c optional ext_resources clk fdt dev/extres/clk/clk_fixed.c optional ext_resources clk fdt dev/extres/clk/clk_gate.c optional ext_resources clk fdt dev/extres/clk/clk_mux.c optional ext_resources clk fdt dev/extres/phy/phy.c optional ext_resources phy fdt dev/extres/phy/phydev_if.m optional ext_resources phy fdt dev/extres/phy/phynode_if.m optional ext_resources phy fdt dev/extres/hwreset/hwreset.c optional ext_resources hwreset fdt dev/extres/hwreset/hwreset_if.m optional ext_resources hwreset fdt dev/extres/regulator/regdev_if.m optional ext_resources regulator fdt dev/extres/regulator/regnode_if.m optional ext_resources regulator fdt dev/extres/regulator/regulator.c optional ext_resources regulator fdt dev/extres/regulator/regulator_bus.c optional ext_resources regulator fdt dev/extres/regulator/regulator_fixed.c optional ext_resources regulator fdt dev/extres/syscon/syscon.c optional ext_resources syscon dev/extres/syscon/syscon_generic.c optional ext_resources syscon fdt dev/extres/syscon/syscon_if.m optional ext_resources syscon dev/fb/fbd.c optional fbd | vt dev/fb/fb_if.m standard dev/fb/splash.c optional sc splash dev/fdt/fdt_clock.c optional fdt fdt_clock dev/fdt/fdt_clock_if.m optional fdt fdt_clock dev/fdt/fdt_common.c optional fdt dev/fdt/fdt_pinctrl.c optional fdt fdt_pinctrl dev/fdt/fdt_pinctrl_if.m optional fdt fdt_pinctrl dev/fdt/fdt_slicer.c optional fdt cfi | fdt nand | fdt mx25l dev/fdt/fdt_static_dtb.S optional fdt fdt_dtb_static \ dependency "fdt_dtb_file" dev/fdt/simplebus.c optional fdt dev/fe/if_fe.c optional fe dev/fe/if_fe_pccard.c optional fe pccard dev/filemon/filemon.c optional filemon dev/firewire/firewire.c optional firewire dev/firewire/fwcrom.c optional firewire dev/firewire/fwdev.c optional firewire dev/firewire/fwdma.c optional firewire dev/firewire/fwmem.c optional firewire dev/firewire/fwohci.c optional firewire dev/firewire/fwohci_pci.c optional firewire pci dev/firewire/if_fwe.c optional fwe dev/firewire/if_fwip.c optional fwip dev/firewire/sbp.c optional sbp dev/firewire/sbp_targ.c optional sbp_targ dev/flash/at45d.c optional at45d dev/flash/mx25l.c optional mx25l dev/fxp/if_fxp.c optional fxp dev/fxp/inphy.c optional fxp dev/gem/if_gem.c optional gem dev/gem/if_gem_pci.c optional gem pci dev/gem/if_gem_sbus.c optional gem sbus dev/gpio/gpiobacklight.c optional gpiobacklight fdt dev/gpio/gpiokeys.c optional gpiokeys fdt dev/gpio/gpiokeys_codes.c optional gpiokeys fdt dev/gpio/gpiobus.c optional gpio \ dependency "gpiobus_if.h" dev/gpio/gpioc.c optional gpio \ dependency "gpio_if.h" dev/gpio/gpioiic.c optional gpioiic dev/gpio/gpioled.c optional gpioled !fdt dev/gpio/gpioled_fdt.c optional gpioled fdt dev/gpio/gpiopower.c optional gpiopower fdt dev/gpio/gpioregulator.c optional gpioregulator fdt ext_resources dev/gpio/gpiospi.c optional gpiospi dev/gpio/gpioths.c optional gpioths dev/gpio/gpio_if.m optional gpio dev/gpio/gpiobus_if.m optional gpio dev/gpio/gpiopps.c optional gpiopps dev/gpio/ofw_gpiobus.c optional fdt gpio dev/hifn/hifn7751.c optional hifn dev/hme/if_hme.c optional hme dev/hme/if_hme_pci.c optional hme pci dev/hme/if_hme_sbus.c optional hme sbus dev/hptiop/hptiop.c optional hptiop scbus dev/hwpmc/hwpmc_logging.c optional hwpmc dev/hwpmc/hwpmc_mod.c optional hwpmc dev/hwpmc/hwpmc_soft.c optional hwpmc dev/ichiic/ig4_acpi.c optional ig4 acpi iicbus dev/ichiic/ig4_iic.c optional ig4 iicbus dev/ichiic/ig4_pci.c optional ig4 pci iicbus dev/ichsmb/ichsmb.c optional ichsmb dev/ichsmb/ichsmb_pci.c optional ichsmb pci dev/ida/ida.c optional ida dev/ida/ida_disk.c optional ida dev/ida/ida_pci.c optional ida pci dev/iicbus/ad7418.c optional ad7418 dev/iicbus/ds1307.c optional ds1307 dev/iicbus/ds13rtc.c optional ds13rtc | ds133x | ds1374 dev/iicbus/ds1672.c optional ds1672 dev/iicbus/ds3231.c optional ds3231 dev/iicbus/rtc8583.c optional rtc8583 dev/iicbus/icee.c optional icee dev/iicbus/if_ic.c optional ic dev/iicbus/iic.c optional iic dev/iicbus/iic_recover_bus.c optional iicbus dev/iicbus/iicbb.c optional iicbb dev/iicbus/iicbb_if.m optional iicbb dev/iicbus/iicbus.c optional iicbus dev/iicbus/iicbus_if.m optional iicbus dev/iicbus/iiconf.c optional iicbus dev/iicbus/iicsmb.c optional iicsmb \ dependency "iicbus_if.h" dev/iicbus/iicoc.c optional iicoc dev/iicbus/isl12xx.c optional isl12xx dev/iicbus/lm75.c optional lm75 dev/iicbus/nxprtc.c optional nxprtc | pcf8563 dev/iicbus/ofw_iicbus.c optional fdt iicbus dev/iicbus/s35390a.c optional s35390a dev/iir/iir.c optional iir dev/iir/iir_ctrl.c optional iir dev/iir/iir_pci.c optional iir pci dev/intpm/intpm.c optional intpm pci # XXX Work around clang warning, until maintainer approves fix. dev/ips/ips.c optional ips \ compile-with "${NORMAL_C} ${NO_WSOMETIMES_UNINITIALIZED}" dev/ips/ips_commands.c optional ips dev/ips/ips_disk.c optional ips dev/ips/ips_ioctl.c optional ips dev/ips/ips_pci.c optional ips pci dev/ipw/if_ipw.c optional ipw ipwbssfw.c optional ipwbssfw | ipwfw \ compile-with "${AWK} -f $S/tools/fw_stub.awk ipw_bss.fw:ipw_bss:130 -lintel_ipw -mipw_bss -c${.TARGET}" \ no-implicit-rule before-depend local \ clean "ipwbssfw.c" ipw_bss.fwo optional ipwbssfw | ipwfw \ dependency "ipw_bss.fw" \ compile-with "${NORMAL_FWO}" \ no-implicit-rule \ clean "ipw_bss.fwo" ipw_bss.fw optional ipwbssfw | ipwfw \ dependency "$S/contrib/dev/ipw/ipw2100-1.3.fw.uu" \ compile-with "${NORMAL_FW}" \ no-obj no-implicit-rule \ clean "ipw_bss.fw" ipwibssfw.c optional ipwibssfw | ipwfw \ compile-with "${AWK} -f $S/tools/fw_stub.awk ipw_ibss.fw:ipw_ibss:130 -lintel_ipw -mipw_ibss -c${.TARGET}" \ no-implicit-rule before-depend local \ clean "ipwibssfw.c" ipw_ibss.fwo optional ipwibssfw | ipwfw \ dependency "ipw_ibss.fw" \ compile-with "${NORMAL_FWO}" \ no-implicit-rule \ clean "ipw_ibss.fwo" ipw_ibss.fw optional ipwibssfw | ipwfw \ dependency "$S/contrib/dev/ipw/ipw2100-1.3-i.fw.uu" \ compile-with "${NORMAL_FW}" \ no-obj no-implicit-rule \ clean "ipw_ibss.fw" ipwmonitorfw.c optional ipwmonitorfw | ipwfw \ compile-with "${AWK} -f $S/tools/fw_stub.awk ipw_monitor.fw:ipw_monitor:130 -lintel_ipw -mipw_monitor -c${.TARGET}" \ no-implicit-rule before-depend local \ clean "ipwmonitorfw.c" ipw_monitor.fwo optional ipwmonitorfw | ipwfw \ dependency "ipw_monitor.fw" \ compile-with "${NORMAL_FWO}" \ no-implicit-rule \ clean "ipw_monitor.fwo" ipw_monitor.fw optional ipwmonitorfw | ipwfw \ dependency "$S/contrib/dev/ipw/ipw2100-1.3-p.fw.uu" \ compile-with "${NORMAL_FW}" \ no-obj no-implicit-rule \ clean "ipw_monitor.fw" dev/iscsi/icl.c optional iscsi dev/iscsi/icl_conn_if.m optional cfiscsi | iscsi dev/iscsi/icl_soft.c optional iscsi dev/iscsi/icl_soft_proxy.c optional iscsi dev/iscsi/iscsi.c optional iscsi scbus dev/iscsi_initiator/iscsi.c optional iscsi_initiator scbus dev/iscsi_initiator/iscsi_subr.c optional iscsi_initiator scbus dev/iscsi_initiator/isc_cam.c optional iscsi_initiator scbus dev/iscsi_initiator/isc_soc.c optional iscsi_initiator scbus dev/iscsi_initiator/isc_sm.c optional iscsi_initiator scbus dev/iscsi_initiator/isc_subr.c optional iscsi_initiator scbus dev/ismt/ismt.c optional ismt dev/isl/isl.c optional isl iicbus dev/isp/isp.c optional isp dev/isp/isp_freebsd.c optional isp dev/isp/isp_library.c optional isp dev/isp/isp_pci.c optional isp pci dev/isp/isp_sbus.c optional isp sbus dev/isp/isp_target.c optional isp dev/ispfw/ispfw.c optional ispfw dev/iwi/if_iwi.c optional iwi iwibssfw.c optional iwibssfw | iwifw \ compile-with "${AWK} -f $S/tools/fw_stub.awk iwi_bss.fw:iwi_bss:300 -lintel_iwi -miwi_bss -c${.TARGET}" \ no-implicit-rule before-depend local \ clean "iwibssfw.c" iwi_bss.fwo optional iwibssfw | iwifw \ dependency "iwi_bss.fw" \ compile-with "${NORMAL_FWO}" \ no-implicit-rule \ clean "iwi_bss.fwo" iwi_bss.fw optional iwibssfw | iwifw \ dependency "$S/contrib/dev/iwi/ipw2200-bss.fw.uu" \ compile-with "${NORMAL_FW}" \ no-obj no-implicit-rule \ clean "iwi_bss.fw" iwiibssfw.c optional iwiibssfw | iwifw \ compile-with "${AWK} -f $S/tools/fw_stub.awk iwi_ibss.fw:iwi_ibss:300 -lintel_iwi -miwi_ibss -c${.TARGET}" \ no-implicit-rule before-depend local \ clean "iwiibssfw.c" iwi_ibss.fwo optional iwiibssfw | iwifw \ dependency "iwi_ibss.fw" \ compile-with "${NORMAL_FWO}" \ no-implicit-rule \ clean "iwi_ibss.fwo" iwi_ibss.fw optional iwiibssfw | iwifw \ dependency "$S/contrib/dev/iwi/ipw2200-ibss.fw.uu" \ compile-with "${NORMAL_FW}" \ no-obj no-implicit-rule \ clean "iwi_ibss.fw" iwimonitorfw.c optional iwimonitorfw | iwifw \ compile-with "${AWK} -f $S/tools/fw_stub.awk iwi_monitor.fw:iwi_monitor:300 -lintel_iwi -miwi_monitor -c${.TARGET}" \ no-implicit-rule before-depend local \ clean "iwimonitorfw.c" iwi_monitor.fwo optional iwimonitorfw | iwifw \ dependency "iwi_monitor.fw" \ compile-with "${NORMAL_FWO}" \ no-implicit-rule \ clean "iwi_monitor.fwo" iwi_monitor.fw optional iwimonitorfw | iwifw \ dependency "$S/contrib/dev/iwi/ipw2200-sniffer.fw.uu" \ compile-with "${NORMAL_FW}" \ no-obj no-implicit-rule \ clean "iwi_monitor.fw" dev/iwm/if_iwm.c optional iwm dev/iwm/if_iwm_7000.c optional iwm dev/iwm/if_iwm_8000.c optional iwm dev/iwm/if_iwm_binding.c optional iwm dev/iwm/if_iwm_fw.c optional iwm dev/iwm/if_iwm_led.c optional iwm dev/iwm/if_iwm_mac_ctxt.c optional iwm dev/iwm/if_iwm_notif_wait.c optional iwm dev/iwm/if_iwm_pcie_trans.c optional iwm dev/iwm/if_iwm_phy_ctxt.c optional iwm dev/iwm/if_iwm_phy_db.c optional iwm dev/iwm/if_iwm_power.c optional iwm dev/iwm/if_iwm_scan.c optional iwm dev/iwm/if_iwm_sf.c optional iwm dev/iwm/if_iwm_sta.c optional iwm dev/iwm/if_iwm_time_event.c optional iwm dev/iwm/if_iwm_util.c optional iwm iwm3160fw.c optional iwm3160fw | iwmfw \ compile-with "${AWK} -f $S/tools/fw_stub.awk iwm3160.fw:iwm3160fw -miwm3160fw -c${.TARGET}" \ no-implicit-rule before-depend local \ clean "iwm3160fw.c" iwm3160fw.fwo optional iwm3160fw | iwmfw \ dependency "iwm3160.fw" \ compile-with "${NORMAL_FWO}" \ no-implicit-rule \ clean "iwm3160fw.fwo" iwm3160.fw optional iwm3160fw | iwmfw \ dependency "$S/contrib/dev/iwm/iwm-3160-17.fw.uu" \ compile-with "${NORMAL_FW}" \ no-obj no-implicit-rule \ clean "iwm3160.fw" iwm7260fw.c optional iwm7260fw | iwmfw \ compile-with "${AWK} -f $S/tools/fw_stub.awk iwm7260.fw:iwm7260fw -miwm7260fw -c${.TARGET}" \ no-implicit-rule before-depend local \ clean "iwm7260fw.c" iwm7260fw.fwo optional iwm7260fw | iwmfw \ dependency "iwm7260.fw" \ compile-with "${NORMAL_FWO}" \ no-implicit-rule \ clean "iwm7260fw.fwo" iwm7260.fw optional iwm7260fw | iwmfw \ dependency "$S/contrib/dev/iwm/iwm-7260-17.fw.uu" \ compile-with "${NORMAL_FW}" \ no-obj no-implicit-rule \ clean "iwm7260.fw" iwm7265fw.c optional iwm7265fw | iwmfw \ compile-with "${AWK} -f $S/tools/fw_stub.awk iwm7265.fw:iwm7265fw -miwm7265fw -c${.TARGET}" \ no-implicit-rule before-depend local \ clean "iwm7265fw.c" iwm7265fw.fwo optional iwm7265fw | iwmfw \ dependency "iwm7265.fw" \ compile-with "${NORMAL_FWO}" \ no-implicit-rule \ clean "iwm7265fw.fwo" iwm7265.fw optional iwm7265fw | iwmfw \ dependency "$S/contrib/dev/iwm/iwm-7265-17.fw.uu" \ compile-with "${NORMAL_FW}" \ no-obj no-implicit-rule \ clean "iwm7265.fw" iwm7265Dfw.c optional iwm7265Dfw | iwmfw \ compile-with "${AWK} -f $S/tools/fw_stub.awk iwm7265D.fw:iwm7265Dfw -miwm7265Dfw -c${.TARGET}" \ no-implicit-rule before-depend local \ clean "iwm7265Dfw.c" iwm7265Dfw.fwo optional iwm7265Dfw | iwmfw \ dependency "iwm7265D.fw" \ compile-with "${NORMAL_FWO}" \ no-implicit-rule \ clean "iwm7265Dfw.fwo" iwm7265D.fw optional iwm7265Dfw | iwmfw \ dependency "$S/contrib/dev/iwm/iwm-7265D-17.fw.uu" \ compile-with "${NORMAL_FW}" \ no-obj no-implicit-rule \ clean "iwm7265D.fw" iwm8000Cfw.c optional iwm8000Cfw | iwmfw \ compile-with "${AWK} -f $S/tools/fw_stub.awk iwm8000C.fw:iwm8000Cfw -miwm8000Cfw -c${.TARGET}" \ no-implicit-rule before-depend local \ clean "iwm8000Cfw.c" iwm8000Cfw.fwo optional iwm8000Cfw | iwmfw \ dependency "iwm8000C.fw" \ compile-with "${NORMAL_FWO}" \ no-implicit-rule \ clean "iwm8000Cfw.fwo" iwm8000C.fw optional iwm8000Cfw | iwmfw \ dependency "$S/contrib/dev/iwm/iwm-8000C-16.fw.uu" \ compile-with "${NORMAL_FW}" \ no-obj no-implicit-rule \ clean "iwm8000C.fw" iwm8265.fw optional iwm8265fw | iwmfw \ dependency "$S/contrib/dev/iwm/iwm-8265-22.fw.uu" \ compile-with "${NORMAL_FW}" \ no-obj no-implicit-rule \ clean "iwm8265.fw" iwm8265fw.c optional iwm8265fw | iwmfw \ compile-with "${AWK} -f $S/tools/fw_stub.awk iwm8265.fw:iwm8265fw -miwm8265fw -c${.TARGET}" \ no-implicit-rule before-depend local \ clean "iwm8265fw.c" iwm8265fw.fwo optional iwm8265fw | iwmfw \ dependency "iwm8265.fw" \ compile-with "${NORMAL_FWO}" \ no-implicit-rule \ clean "iwm8265fw.fwo" dev/iwn/if_iwn.c optional iwn iwn1000fw.c optional iwn1000fw | iwnfw \ compile-with "${AWK} -f $S/tools/fw_stub.awk iwn1000.fw:iwn1000fw -miwn1000fw -c${.TARGET}" \ no-implicit-rule before-depend local \ clean "iwn1000fw.c" iwn1000fw.fwo optional iwn1000fw | iwnfw \ dependency "iwn1000.fw" \ compile-with "${NORMAL_FWO}" \ no-implicit-rule \ clean "iwn1000fw.fwo" iwn1000.fw optional iwn1000fw | iwnfw \ dependency "$S/contrib/dev/iwn/iwlwifi-1000-39.31.5.1.fw.uu" \ compile-with "${NORMAL_FW}" \ no-obj no-implicit-rule \ clean "iwn1000.fw" iwn100fw.c optional iwn100fw | iwnfw \ compile-with "${AWK} -f $S/tools/fw_stub.awk iwn100.fw:iwn100fw -miwn100fw -c${.TARGET}" \ no-implicit-rule before-depend local \ clean "iwn100fw.c" iwn100fw.fwo optional iwn100fw | iwnfw \ dependency "iwn100.fw" \ compile-with "${NORMAL_FWO}" \ no-implicit-rule \ clean "iwn100fw.fwo" iwn100.fw optional iwn100fw | iwnfw \ dependency "$S/contrib/dev/iwn/iwlwifi-100-39.31.5.1.fw.uu" \ compile-with "${NORMAL_FW}" \ no-obj no-implicit-rule \ clean "iwn100.fw" iwn105fw.c optional iwn105fw | iwnfw \ compile-with "${AWK} -f $S/tools/fw_stub.awk iwn105.fw:iwn105fw -miwn105fw -c${.TARGET}" \ no-implicit-rule before-depend local \ clean "iwn105fw.c" iwn105fw.fwo optional iwn105fw | iwnfw \ dependency "iwn105.fw" \ compile-with "${NORMAL_FWO}" \ no-implicit-rule \ clean "iwn105fw.fwo" iwn105.fw optional iwn105fw | iwnfw \ dependency "$S/contrib/dev/iwn/iwlwifi-105-6-18.168.6.1.fw.uu" \ compile-with "${NORMAL_FW}" \ no-obj no-implicit-rule \ clean "iwn105.fw" iwn135fw.c optional iwn135fw | iwnfw \ compile-with "${AWK} -f $S/tools/fw_stub.awk iwn135.fw:iwn135fw -miwn135fw -c${.TARGET}" \ no-implicit-rule before-depend local \ clean "iwn135fw.c" iwn135fw.fwo optional iwn135fw | iwnfw \ dependency "iwn135.fw" \ compile-with "${NORMAL_FWO}" \ no-implicit-rule \ clean "iwn135fw.fwo" iwn135.fw optional iwn135fw | iwnfw \ dependency "$S/contrib/dev/iwn/iwlwifi-135-6-18.168.6.1.fw.uu" \ compile-with "${NORMAL_FW}" \ no-obj no-implicit-rule \ clean "iwn135.fw" iwn2000fw.c optional iwn2000fw | iwnfw \ compile-with "${AWK} -f $S/tools/fw_stub.awk iwn2000.fw:iwn2000fw -miwn2000fw -c${.TARGET}" \ no-implicit-rule before-depend local \ clean "iwn2000fw.c" iwn2000fw.fwo optional iwn2000fw | iwnfw \ dependency "iwn2000.fw" \ compile-with "${NORMAL_FWO}" \ no-implicit-rule \ clean "iwn2000fw.fwo" iwn2000.fw optional iwn2000fw | iwnfw \ dependency "$S/contrib/dev/iwn/iwlwifi-2000-18.168.6.1.fw.uu" \ compile-with "${NORMAL_FW}" \ no-obj no-implicit-rule \ clean "iwn2000.fw" iwn2030fw.c optional iwn2030fw | iwnfw \ compile-with "${AWK} -f $S/tools/fw_stub.awk iwn2030.fw:iwn2030fw -miwn2030fw -c${.TARGET}" \ no-implicit-rule before-depend local \ clean "iwn2030fw.c" iwn2030fw.fwo optional iwn2030fw | iwnfw \ dependency "iwn2030.fw" \ compile-with "${NORMAL_FWO}" \ no-implicit-rule \ clean "iwn2030fw.fwo" iwn2030.fw optional iwn2030fw | iwnfw \ dependency "$S/contrib/dev/iwn/iwnwifi-2030-18.168.6.1.fw.uu" \ compile-with "${NORMAL_FW}" \ no-obj no-implicit-rule \ clean "iwn2030.fw" iwn4965fw.c optional iwn4965fw | iwnfw \ compile-with "${AWK} -f $S/tools/fw_stub.awk iwn4965.fw:iwn4965fw -miwn4965fw -c${.TARGET}" \ no-implicit-rule before-depend local \ clean "iwn4965fw.c" iwn4965fw.fwo optional iwn4965fw | iwnfw \ dependency "iwn4965.fw" \ compile-with "${NORMAL_FWO}" \ no-implicit-rule \ clean "iwn4965fw.fwo" iwn4965.fw optional iwn4965fw | iwnfw \ dependency "$S/contrib/dev/iwn/iwlwifi-4965-228.61.2.24.fw.uu" \ compile-with "${NORMAL_FW}" \ no-obj no-implicit-rule \ clean "iwn4965.fw" iwn5000fw.c optional iwn5000fw | iwnfw \ compile-with "${AWK} -f $S/tools/fw_stub.awk iwn5000.fw:iwn5000fw -miwn5000fw -c${.TARGET}" \ no-implicit-rule before-depend local \ clean "iwn5000fw.c" iwn5000fw.fwo optional iwn5000fw | iwnfw \ dependency "iwn5000.fw" \ compile-with "${NORMAL_FWO}" \ no-implicit-rule \ clean "iwn5000fw.fwo" iwn5000.fw optional iwn5000fw | iwnfw \ dependency "$S/contrib/dev/iwn/iwlwifi-5000-8.83.5.1.fw.uu" \ compile-with "${NORMAL_FW}" \ no-obj no-implicit-rule \ clean "iwn5000.fw" iwn5150fw.c optional iwn5150fw | iwnfw \ compile-with "${AWK} -f $S/tools/fw_stub.awk iwn5150.fw:iwn5150fw -miwn5150fw -c${.TARGET}" \ no-implicit-rule before-depend local \ clean "iwn5150fw.c" iwn5150fw.fwo optional iwn5150fw | iwnfw \ dependency "iwn5150.fw" \ compile-with "${NORMAL_FWO}" \ no-implicit-rule \ clean "iwn5150fw.fwo" iwn5150.fw optional iwn5150fw | iwnfw \ dependency "$S/contrib/dev/iwn/iwlwifi-5150-8.24.2.2.fw.uu"\ compile-with "${NORMAL_FW}" \ no-obj no-implicit-rule \ clean "iwn5150.fw" iwn6000fw.c optional iwn6000fw | iwnfw \ compile-with "${AWK} -f $S/tools/fw_stub.awk iwn6000.fw:iwn6000fw -miwn6000fw -c${.TARGET}" \ no-implicit-rule before-depend local \ clean "iwn6000fw.c" iwn6000fw.fwo optional iwn6000fw | iwnfw \ dependency "iwn6000.fw" \ compile-with "${NORMAL_FWO}" \ no-implicit-rule \ clean "iwn6000fw.fwo" iwn6000.fw optional iwn6000fw | iwnfw \ dependency "$S/contrib/dev/iwn/iwlwifi-6000-9.221.4.1.fw.uu" \ compile-with "${NORMAL_FW}" \ no-obj no-implicit-rule \ clean "iwn6000.fw" iwn6000g2afw.c optional iwn6000g2afw | iwnfw \ compile-with "${AWK} -f $S/tools/fw_stub.awk iwn6000g2a.fw:iwn6000g2afw -miwn6000g2afw -c${.TARGET}" \ no-implicit-rule before-depend local \ clean "iwn6000g2afw.c" iwn6000g2afw.fwo optional iwn6000g2afw | iwnfw \ dependency "iwn6000g2a.fw" \ compile-with "${NORMAL_FWO}" \ no-implicit-rule \ clean "iwn6000g2afw.fwo" iwn6000g2a.fw optional iwn6000g2afw | iwnfw \ dependency "$S/contrib/dev/iwn/iwlwifi-6000g2a-18.168.6.1.fw.uu" \ compile-with "${NORMAL_FW}" \ no-obj no-implicit-rule \ clean "iwn6000g2a.fw" iwn6000g2bfw.c optional iwn6000g2bfw | iwnfw \ compile-with "${AWK} -f $S/tools/fw_stub.awk iwn6000g2b.fw:iwn6000g2bfw -miwn6000g2bfw -c${.TARGET}" \ no-implicit-rule before-depend local \ clean "iwn6000g2bfw.c" iwn6000g2bfw.fwo optional iwn6000g2bfw | iwnfw \ dependency "iwn6000g2b.fw" \ compile-with "${NORMAL_FWO}" \ no-implicit-rule \ clean "iwn6000g2bfw.fwo" iwn6000g2b.fw optional iwn6000g2bfw | iwnfw \ dependency "$S/contrib/dev/iwn/iwlwifi-6000g2b-18.168.6.1.fw.uu" \ compile-with "${NORMAL_FW}" \ no-obj no-implicit-rule \ clean "iwn6000g2b.fw" iwn6050fw.c optional iwn6050fw | iwnfw \ compile-with "${AWK} -f $S/tools/fw_stub.awk iwn6050.fw:iwn6050fw -miwn6050fw -c${.TARGET}" \ no-implicit-rule before-depend local \ clean "iwn6050fw.c" iwn6050fw.fwo optional iwn6050fw | iwnfw \ dependency "iwn6050.fw" \ compile-with "${NORMAL_FWO}" \ no-implicit-rule \ clean "iwn6050fw.fwo" iwn6050.fw optional iwn6050fw | iwnfw \ dependency "$S/contrib/dev/iwn/iwlwifi-6050-41.28.5.1.fw.uu" \ compile-with "${NORMAL_FW}" \ no-obj no-implicit-rule \ clean "iwn6050.fw" dev/ixgb/if_ixgb.c optional ixgb dev/ixgb/ixgb_ee.c optional ixgb dev/ixgb/ixgb_hw.c optional ixgb dev/ixgbe/if_ix.c optional ix inet \ compile-with "${NORMAL_C} -I$S/dev/ixgbe -DSMP" dev/ixgbe/if_ixv.c optional ixv inet \ compile-with "${NORMAL_C} -I$S/dev/ixgbe -DSMP" dev/ixgbe/if_bypass.c optional ix inet \ compile-with "${NORMAL_C} -I$S/dev/ixgbe" dev/ixgbe/if_fdir.c optional ix inet | ixv inet \ compile-with "${NORMAL_C} -I$S/dev/ixgbe" dev/ixgbe/if_sriov.c optional ix inet \ compile-with "${NORMAL_C} -I$S/dev/ixgbe" dev/ixgbe/ix_txrx.c optional ix inet | ixv inet \ compile-with "${NORMAL_C} -I$S/dev/ixgbe" dev/ixgbe/ixgbe_osdep.c optional ix inet | ixv inet \ compile-with "${NORMAL_C} -I$S/dev/ixgbe" dev/ixgbe/ixgbe_phy.c optional ix inet | ixv inet \ compile-with "${NORMAL_C} -I$S/dev/ixgbe" dev/ixgbe/ixgbe_api.c optional ix inet | ixv inet \ compile-with "${NORMAL_C} -I$S/dev/ixgbe" dev/ixgbe/ixgbe_common.c optional ix inet | ixv inet \ compile-with "${NORMAL_C} -I$S/dev/ixgbe" dev/ixgbe/ixgbe_mbx.c optional ix inet | ixv inet \ compile-with "${NORMAL_C} -I$S/dev/ixgbe" dev/ixgbe/ixgbe_vf.c optional ix inet | ixv inet \ compile-with "${NORMAL_C} -I$S/dev/ixgbe" dev/ixgbe/ixgbe_82598.c optional ix inet | ixv inet \ compile-with "${NORMAL_C} -I$S/dev/ixgbe" dev/ixgbe/ixgbe_82599.c optional ix inet | ixv inet \ compile-with "${NORMAL_C} -I$S/dev/ixgbe" dev/ixgbe/ixgbe_x540.c optional ix inet | ixv inet \ compile-with "${NORMAL_C} -I$S/dev/ixgbe" dev/ixgbe/ixgbe_x550.c optional ix inet | ixv inet \ compile-with "${NORMAL_C} -I$S/dev/ixgbe" dev/ixgbe/ixgbe_dcb.c optional ix inet | ixv inet \ compile-with "${NORMAL_C} -I$S/dev/ixgbe" dev/ixgbe/ixgbe_dcb_82598.c optional ix inet | ixv inet \ compile-with "${NORMAL_C} -I$S/dev/ixgbe" dev/ixgbe/ixgbe_dcb_82599.c optional ix inet | ixv inet \ compile-with "${NORMAL_C} -I$S/dev/ixgbe" dev/jedec_ts/jedec_ts.c optional jedec_ts smbus dev/jme/if_jme.c optional jme pci dev/joy/joy.c optional joy dev/joy/joy_isa.c optional joy isa dev/kbd/kbd.c optional atkbd | pckbd | sc | ukbd | vt dev/kbdmux/kbdmux.c optional kbdmux dev/ksyms/ksyms.c optional ksyms dev/le/am7990.c optional le dev/le/am79900.c optional le dev/le/if_le_pci.c optional le pci dev/le/lance.c optional le dev/led/led.c standard dev/lge/if_lge.c optional lge dev/liquidio/base/cn23xx_pf_device.c optional lio \ compile-with "${NORMAL_C} \ -I$S/dev/liquidio -I$S/dev/liquidio/base -DSMP" dev/liquidio/base/lio_console.c optional lio \ compile-with "${NORMAL_C} \ -I$S/dev/liquidio -I$S/dev/liquidio/base -DSMP" dev/liquidio/base/lio_ctrl.c optional lio \ compile-with "${NORMAL_C} \ -I$S/dev/liquidio -I$S/dev/liquidio/base -DSMP" dev/liquidio/base/lio_device.c optional lio \ compile-with "${NORMAL_C} \ -I$S/dev/liquidio -I$S/dev/liquidio/base -DSMP" dev/liquidio/base/lio_droq.c optional lio \ compile-with "${NORMAL_C} \ -I$S/dev/liquidio -I$S/dev/liquidio/base -DSMP" dev/liquidio/base/lio_mem_ops.c optional lio \ compile-with "${NORMAL_C} \ -I$S/dev/liquidio -I$S/dev/liquidio/base -DSMP" dev/liquidio/base/lio_request_manager.c optional lio \ compile-with "${NORMAL_C} \ -I$S/dev/liquidio -I$S/dev/liquidio/base -DSMP" dev/liquidio/base/lio_response_manager.c optional lio \ compile-with "${NORMAL_C} \ -I$S/dev/liquidio -I$S/dev/liquidio/base -DSMP" dev/liquidio/lio_core.c optional lio \ compile-with "${NORMAL_C} \ -I$S/dev/liquidio -I$S/dev/liquidio/base -DSMP" dev/liquidio/lio_ioctl.c optional lio \ compile-with "${NORMAL_C} \ -I$S/dev/liquidio -I$S/dev/liquidio/base -DSMP" dev/liquidio/lio_main.c optional lio \ compile-with "${NORMAL_C} \ -I$S/dev/liquidio -I$S/dev/liquidio/base -DSMP" dev/liquidio/lio_rss.c optional lio \ compile-with "${NORMAL_C} \ -I$S/dev/liquidio -I$S/dev/liquidio/base -DSMP" dev/liquidio/lio_rxtx.c optional lio \ compile-with "${NORMAL_C} \ -I$S/dev/liquidio -I$S/dev/liquidio/base -DSMP" dev/liquidio/lio_sysctl.c optional lio \ compile-with "${NORMAL_C} \ -I$S/dev/liquidio -I$S/dev/liquidio/base -DSMP" lio.c optional lio \ compile-with "${AWK} -f $S/tools/fw_stub.awk lio_23xx_nic.bin.fw:lio_23xx_nic.bin -mlio_23xx_nic.bin -c${.TARGET}" \ no-implicit-rule before-depend local \ clean "lio.c" lio_23xx_nic.bin.fw.fwo optional lio \ dependency "lio_23xx_nic.bin.fw" \ compile-with "${NORMAL_FWO}" \ no-implicit-rule \ clean "lio_23xx_nic.bin.fw.fwo" lio_23xx_nic.bin.fw optional lio \ dependency "$S/contrib/dev/liquidio/lio_23xx_nic.bin.uu" \ compile-with "${NORMAL_FW}" \ no-obj no-implicit-rule \ clean "lio_23xx_nic.bin.fw" dev/lmc/if_lmc.c optional lmc dev/malo/if_malo.c optional malo dev/malo/if_malohal.c optional malo dev/malo/if_malo_pci.c optional malo pci dev/mc146818/mc146818.c optional mc146818 dev/md/md.c optional md dev/mdio/mdio_if.m optional miiproxy | mdio dev/mdio/mdio.c optional miiproxy | mdio dev/mem/memdev.c optional mem dev/mem/memutil.c optional mem dev/mfi/mfi.c optional mfi dev/mfi/mfi_debug.c optional mfi dev/mfi/mfi_pci.c optional mfi pci dev/mfi/mfi_disk.c optional mfi dev/mfi/mfi_syspd.c optional mfi dev/mfi/mfi_tbolt.c optional mfi dev/mfi/mfi_linux.c optional mfi compat_linux dev/mfi/mfi_cam.c optional mfip scbus dev/mii/acphy.c optional miibus | acphy dev/mii/amphy.c optional miibus | amphy dev/mii/atphy.c optional miibus | atphy dev/mii/axphy.c optional miibus | axphy dev/mii/bmtphy.c optional miibus | bmtphy dev/mii/brgphy.c optional miibus | brgphy dev/mii/ciphy.c optional miibus | ciphy dev/mii/e1000phy.c optional miibus | e1000phy dev/mii/gentbi.c optional miibus | gentbi dev/mii/icsphy.c optional miibus | icsphy dev/mii/ip1000phy.c optional miibus | ip1000phy dev/mii/jmphy.c optional miibus | jmphy dev/mii/lxtphy.c optional miibus | lxtphy dev/mii/micphy.c optional miibus fdt | micphy fdt dev/mii/mii.c optional miibus | mii dev/mii/mii_bitbang.c optional miibus | mii_bitbang dev/mii/mii_physubr.c optional miibus | mii dev/mii/mii_fdt.c optional miibus fdt | mii fdt dev/mii/miibus_if.m optional miibus | mii dev/mii/mlphy.c optional miibus | mlphy dev/mii/nsgphy.c optional miibus | nsgphy dev/mii/nsphy.c optional miibus | nsphy dev/mii/nsphyter.c optional miibus | nsphyter dev/mii/pnaphy.c optional miibus | pnaphy dev/mii/qsphy.c optional miibus | qsphy dev/mii/rdcphy.c optional miibus | rdcphy dev/mii/rgephy.c optional miibus | rgephy dev/mii/rlphy.c optional miibus | rlphy dev/mii/rlswitch.c optional rlswitch dev/mii/smcphy.c optional miibus | smcphy dev/mii/smscphy.c optional miibus | smscphy dev/mii/tdkphy.c optional miibus | tdkphy dev/mii/tlphy.c optional miibus | tlphy dev/mii/truephy.c optional miibus | truephy dev/mii/ukphy.c optional miibus | mii dev/mii/ukphy_subr.c optional miibus | mii dev/mii/vscphy.c optional miibus | vscphy dev/mii/xmphy.c optional miibus | xmphy dev/mk48txx/mk48txx.c optional mk48txx dev/mlx/mlx.c optional mlx dev/mlx/mlx_disk.c optional mlx dev/mlx/mlx_pci.c optional mlx pci dev/mly/mly.c optional mly dev/mmc/mmc_subr.c optional mmc | mmcsd !mmccam dev/mmc/mmc.c optional mmc !mmccam dev/mmc/mmcbr_if.m standard dev/mmc/mmcbus_if.m standard dev/mmc/mmcsd.c optional mmcsd !mmccam dev/mmcnull/mmcnull.c optional mmcnull dev/mn/if_mn.c optional mn pci dev/mpr/mpr.c optional mpr dev/mpr/mpr_config.c optional mpr # XXX Work around clang warning, until maintainer approves fix. dev/mpr/mpr_mapping.c optional mpr \ compile-with "${NORMAL_C} ${NO_WSOMETIMES_UNINITIALIZED}" dev/mpr/mpr_pci.c optional mpr pci dev/mpr/mpr_sas.c optional mpr \ compile-with "${NORMAL_C} ${NO_WUNNEEDED_INTERNAL_DECL}" dev/mpr/mpr_sas_lsi.c optional mpr dev/mpr/mpr_table.c optional mpr dev/mpr/mpr_user.c optional mpr dev/mps/mps.c optional mps dev/mps/mps_config.c optional mps # XXX Work around clang warning, until maintainer approves fix. dev/mps/mps_mapping.c optional mps \ compile-with "${NORMAL_C} ${NO_WSOMETIMES_UNINITIALIZED}" dev/mps/mps_pci.c optional mps pci dev/mps/mps_sas.c optional mps \ compile-with "${NORMAL_C} ${NO_WUNNEEDED_INTERNAL_DECL}" dev/mps/mps_sas_lsi.c optional mps dev/mps/mps_table.c optional mps dev/mps/mps_user.c optional mps dev/mpt/mpt.c optional mpt dev/mpt/mpt_cam.c optional mpt dev/mpt/mpt_debug.c optional mpt dev/mpt/mpt_pci.c optional mpt pci dev/mpt/mpt_raid.c optional mpt dev/mpt/mpt_user.c optional mpt dev/mrsas/mrsas.c optional mrsas dev/mrsas/mrsas_cam.c optional mrsas dev/mrsas/mrsas_ioctl.c optional mrsas dev/mrsas/mrsas_fp.c optional mrsas dev/msk/if_msk.c optional msk dev/mvs/mvs.c optional mvs dev/mvs/mvs_if.m optional mvs dev/mvs/mvs_pci.c optional mvs pci dev/mwl/if_mwl.c optional mwl dev/mwl/if_mwl_pci.c optional mwl pci dev/mwl/mwlhal.c optional mwl mwlfw.c optional mwlfw \ compile-with "${AWK} -f $S/tools/fw_stub.awk mw88W8363.fw:mw88W8363fw mwlboot.fw:mwlboot -mmwl -c${.TARGET}" \ no-implicit-rule before-depend local \ clean "mwlfw.c" mw88W8363.fwo optional mwlfw \ dependency "mw88W8363.fw" \ compile-with "${NORMAL_FWO}" \ no-implicit-rule \ clean "mw88W8363.fwo" mw88W8363.fw optional mwlfw \ dependency "$S/contrib/dev/mwl/mw88W8363.fw.uu" \ compile-with "${NORMAL_FW}" \ no-obj no-implicit-rule \ clean "mw88W8363.fw" mwlboot.fwo optional mwlfw \ dependency "mwlboot.fw" \ compile-with "${NORMAL_FWO}" \ no-implicit-rule \ clean "mwlboot.fwo" mwlboot.fw optional mwlfw \ dependency "$S/contrib/dev/mwl/mwlboot.fw.uu" \ compile-with "${NORMAL_FW}" \ no-obj no-implicit-rule \ clean "mwlboot.fw" dev/mxge/if_mxge.c optional mxge pci dev/mxge/mxge_eth_z8e.c optional mxge pci dev/mxge/mxge_ethp_z8e.c optional mxge pci dev/mxge/mxge_rss_eth_z8e.c optional mxge pci dev/mxge/mxge_rss_ethp_z8e.c optional mxge pci dev/my/if_my.c optional my dev/nand/nand.c optional nand dev/nand/nand_bbt.c optional nand dev/nand/nand_cdev.c optional nand dev/nand/nand_generic.c optional nand dev/nand/nand_geom.c optional nand dev/nand/nand_id.c optional nand dev/nand/nandbus.c optional nand dev/nand/nandbus_if.m optional nand dev/nand/nand_if.m optional nand dev/nand/nandsim.c optional nandsim nand dev/nand/nandsim_chip.c optional nandsim nand dev/nand/nandsim_ctrl.c optional nandsim nand dev/nand/nandsim_log.c optional nandsim nand dev/nand/nandsim_swap.c optional nandsim nand dev/nand/nfc_if.m optional nand dev/ncr/ncr.c optional ncr pci dev/ncv/ncr53c500.c optional ncv dev/ncv/ncr53c500_pccard.c optional ncv pccard dev/netmap/if_ptnet.c optional netmap inet dev/netmap/netmap.c optional netmap dev/netmap/netmap_freebsd.c optional netmap dev/netmap/netmap_generic.c optional netmap dev/netmap/netmap_mbq.c optional netmap dev/netmap/netmap_mem2.c optional netmap dev/netmap/netmap_monitor.c optional netmap dev/netmap/netmap_offloadings.c optional netmap dev/netmap/netmap_pipe.c optional netmap dev/netmap/netmap_pt.c optional netmap dev/netmap/netmap_vale.c optional netmap # compile-with "${NORMAL_C} -Wconversion -Wextra" dev/nfsmb/nfsmb.c optional nfsmb pci dev/nge/if_nge.c optional nge dev/nxge/if_nxge.c optional nxge \ compile-with "${NORMAL_C} ${NO_WSELF_ASSIGN}" dev/nxge/xgehal/xgehal-device.c optional nxge \ compile-with "${NORMAL_C} ${NO_WSELF_ASSIGN}" dev/nxge/xgehal/xgehal-mm.c optional nxge dev/nxge/xgehal/xge-queue.c optional nxge dev/nxge/xgehal/xgehal-driver.c optional nxge \ compile-with "${NORMAL_C} ${NO_WSELF_ASSIGN}" dev/nxge/xgehal/xgehal-ring.c optional nxge \ compile-with "${NORMAL_C} ${NO_WSELF_ASSIGN}" dev/nxge/xgehal/xgehal-channel.c optional nxge \ compile-with "${NORMAL_C} ${NO_WSELF_ASSIGN}" dev/nxge/xgehal/xgehal-fifo.c optional nxge \ compile-with "${NORMAL_C} ${NO_WSELF_ASSIGN}" dev/nxge/xgehal/xgehal-stats.c optional nxge \ compile-with "${NORMAL_C} ${NO_WSELF_ASSIGN}" dev/nxge/xgehal/xgehal-config.c optional nxge dev/nxge/xgehal/xgehal-mgmt.c optional nxge \ compile-with "${NORMAL_C} ${NO_WSELF_ASSIGN}" dev/nmdm/nmdm.c optional nmdm dev/nsp/nsp.c optional nsp dev/nsp/nsp_pccard.c optional nsp pccard dev/null/null.c standard dev/oce/oce_hw.c optional oce pci dev/oce/oce_if.c optional oce pci dev/oce/oce_mbox.c optional oce pci dev/oce/oce_queue.c optional oce pci dev/oce/oce_sysctl.c optional oce pci dev/oce/oce_util.c optional oce pci dev/ofw/ofw_bus_if.m optional fdt dev/ofw/ofw_bus_subr.c optional fdt dev/ofw/ofw_cpu.c optional fdt dev/ofw/ofw_fdt.c optional fdt dev/ofw/ofw_if.m optional fdt dev/ofw/ofw_subr.c optional fdt dev/ofw/ofwbus.c optional fdt dev/ofw/openfirm.c optional fdt dev/ofw/openfirmio.c optional fdt dev/ow/ow.c optional ow \ dependency "owll_if.h" \ dependency "own_if.h" dev/ow/owll_if.m optional ow dev/ow/own_if.m optional ow dev/ow/ow_temp.c optional ow_temp dev/ow/owc_gpiobus.c optional owc gpio dev/pbio/pbio.c optional pbio isa dev/pccard/card_if.m standard dev/pccard/pccard.c optional pccard dev/pccard/pccard_cis.c optional pccard dev/pccard/pccard_cis_quirks.c optional pccard dev/pccard/pccard_device.c optional pccard dev/pccard/power_if.m standard dev/pccbb/pccbb.c optional cbb dev/pccbb/pccbb_isa.c optional cbb isa dev/pccbb/pccbb_pci.c optional cbb pci dev/pcf/pcf.c optional pcf dev/pci/fixup_pci.c optional pci dev/pci/hostb_pci.c optional pci dev/pci/ignore_pci.c optional pci dev/pci/isa_pci.c optional pci isa dev/pci/pci.c optional pci dev/pci/pci_if.m standard dev/pci/pci_iov.c optional pci pci_iov dev/pci/pci_iov_if.m standard dev/pci/pci_iov_schema.c optional pci pci_iov dev/pci/pci_pci.c optional pci dev/pci/pci_subr.c optional pci dev/pci/pci_user.c optional pci dev/pci/pcib_if.m standard dev/pci/pcib_support.c standard dev/pci/vga_pci.c optional pci dev/pcn/if_pcn.c optional pcn pci dev/pdq/if_fpa.c optional fpa pci dev/pdq/pdq.c optional nowerror fpa pci dev/pdq/pdq_ifsubr.c optional nowerror fpa pci dev/pms/freebsd/driver/ini/src/agtiapi.c optional pmspcv \ compile-with "${NORMAL_C} -Wunused-variable -Woverflow -Wparentheses -w" dev/pms/RefTisa/sallsdk/spc/sadisc.c optional pmspcv \ compile-with "${NORMAL_C} -Wunused-variable -Woverflow -Wparentheses -w" dev/pms/RefTisa/sallsdk/spc/mpi.c optional pmspcv \ compile-with "${NORMAL_C} -Wunused-variable -Woverflow -Wparentheses -w" dev/pms/RefTisa/sallsdk/spc/saframe.c optional pmspcv \ compile-with "${NORMAL_C} -Wunused-variable -Woverflow -Wparentheses -w" dev/pms/RefTisa/sallsdk/spc/sahw.c optional pmspcv \ compile-with "${NORMAL_C} -Wunused-variable -Woverflow -Wparentheses -w" dev/pms/RefTisa/sallsdk/spc/sainit.c optional pmspcv \ compile-with "${NORMAL_C} -Wunused-variable -Woverflow -Wparentheses -w" dev/pms/RefTisa/sallsdk/spc/saint.c optional pmspcv \ compile-with "${NORMAL_C} -Wunused-variable -Woverflow -Wparentheses -w" dev/pms/RefTisa/sallsdk/spc/sampicmd.c optional pmspcv \ compile-with "${NORMAL_C} -Wunused-variable -Woverflow -Wparentheses -w" dev/pms/RefTisa/sallsdk/spc/sampirsp.c optional pmspcv \ compile-with "${NORMAL_C} -Wunused-variable -Woverflow -Wparentheses -w" dev/pms/RefTisa/sallsdk/spc/saphy.c optional pmspcv \ compile-with "${NORMAL_C} -Wunused-variable -Woverflow -Wparentheses -w" dev/pms/RefTisa/sallsdk/spc/saport.c optional pmspcv \ compile-with "${NORMAL_C} -Wunused-variable -Woverflow -Wparentheses -w" dev/pms/RefTisa/sallsdk/spc/sasata.c optional pmspcv \ compile-with "${NORMAL_C} -Wunused-variable -Woverflow -Wparentheses -w" dev/pms/RefTisa/sallsdk/spc/sasmp.c optional pmspcv \ compile-with "${NORMAL_C} -Wunused-variable -Woverflow -Wparentheses -w" dev/pms/RefTisa/sallsdk/spc/sassp.c optional pmspcv \ compile-with "${NORMAL_C} -Wunused-variable -Woverflow -Wparentheses -w" dev/pms/RefTisa/sallsdk/spc/satimer.c optional pmspcv \ compile-with "${NORMAL_C} -Wunused-variable -Woverflow -Wparentheses -w" dev/pms/RefTisa/sallsdk/spc/sautil.c optional pmspcv \ compile-with "${NORMAL_C} -Wunused-variable -Woverflow -Wparentheses -w" dev/pms/RefTisa/sallsdk/spc/saioctlcmd.c optional pmspcv \ compile-with "${NORMAL_C} -Wunused-variable -Woverflow -Wparentheses -w" dev/pms/RefTisa/sallsdk/spc/mpidebug.c optional pmspcv \ compile-with "${NORMAL_C} -Wunused-variable -Woverflow -Wparentheses -w" dev/pms/RefTisa/discovery/dm/dminit.c optional pmspcv \ compile-with "${NORMAL_C} -Wunused-variable -Woverflow -Wparentheses -w" dev/pms/RefTisa/discovery/dm/dmsmp.c optional pmspcv \ compile-with "${NORMAL_C} -Wunused-variable -Woverflow -Wparentheses -w" dev/pms/RefTisa/discovery/dm/dmdisc.c optional pmspcv \ compile-with "${NORMAL_C} -Wunused-variable -Woverflow -Wparentheses -w" dev/pms/RefTisa/discovery/dm/dmport.c optional pmspcv \ compile-with "${NORMAL_C} -Wunused-variable -Woverflow -Wparentheses -w" dev/pms/RefTisa/discovery/dm/dmtimer.c optional pmspcv \ compile-with "${NORMAL_C} -Wunused-variable -Woverflow -Wparentheses -w" dev/pms/RefTisa/discovery/dm/dmmisc.c optional pmspcv \ compile-with "${NORMAL_C} -Wunused-variable -Woverflow -Wparentheses -w" dev/pms/RefTisa/sat/src/sminit.c optional pmspcv \ compile-with "${NORMAL_C} -Wunused-variable -Woverflow -Wparentheses -w" dev/pms/RefTisa/sat/src/smmisc.c optional pmspcv \ compile-with "${NORMAL_C} -Wunused-variable -Woverflow -Wparentheses -w" dev/pms/RefTisa/sat/src/smsat.c optional pmspcv \ compile-with "${NORMAL_C} -Wunused-variable -Woverflow -Wparentheses -w" dev/pms/RefTisa/sat/src/smsatcb.c optional pmspcv \ compile-with "${NORMAL_C} -Wunused-variable -Woverflow -Wparentheses -w" dev/pms/RefTisa/sat/src/smsathw.c optional pmspcv \ compile-with "${NORMAL_C} -Wunused-variable -Woverflow -Wparentheses -w" dev/pms/RefTisa/sat/src/smtimer.c optional pmspcv \ compile-with "${NORMAL_C} -Wunused-variable -Woverflow -Wparentheses -w" dev/pms/RefTisa/tisa/sassata/common/tdinit.c optional pmspcv \ compile-with "${NORMAL_C} -Wunused-variable -Woverflow -Wparentheses -w" dev/pms/RefTisa/tisa/sassata/common/tdmisc.c optional pmspcv \ compile-with "${NORMAL_C} -Wunused-variable -Woverflow -Wparentheses -w" dev/pms/RefTisa/tisa/sassata/common/tdesgl.c optional pmspcv \ compile-with "${NORMAL_C} -Wunused-variable -Woverflow -Wparentheses -w" dev/pms/RefTisa/tisa/sassata/common/tdport.c optional pmspcv \ compile-with "${NORMAL_C} -Wunused-variable -Woverflow -Wparentheses -w" dev/pms/RefTisa/tisa/sassata/common/tdint.c optional pmspcv \ compile-with "${NORMAL_C} -Wunused-variable -Woverflow -Wparentheses -w" dev/pms/RefTisa/tisa/sassata/common/tdioctl.c optional pmspcv \ compile-with "${NORMAL_C} -Wunused-variable -Woverflow -Wparentheses -w" dev/pms/RefTisa/tisa/sassata/common/tdhw.c optional pmspcv \ compile-with "${NORMAL_C} -Wunused-variable -Woverflow -Wparentheses -w" dev/pms/RefTisa/tisa/sassata/common/ossacmnapi.c optional pmspcv \ compile-with "${NORMAL_C} -Wunused-variable -Woverflow -Wparentheses -w" dev/pms/RefTisa/tisa/sassata/common/tddmcmnapi.c optional pmspcv \ compile-with "${NORMAL_C} -Wunused-variable -Woverflow -Wparentheses -w" dev/pms/RefTisa/tisa/sassata/common/tdsmcmnapi.c optional pmspcv \ compile-with "${NORMAL_C} -Wunused-variable -Woverflow -Wparentheses -w" dev/pms/RefTisa/tisa/sassata/common/tdtimers.c optional pmspcv \ compile-with "${NORMAL_C} -Wunused-variable -Woverflow -Wparentheses -w" dev/pms/RefTisa/tisa/sassata/sas/ini/itdio.c optional pmspcv \ compile-with "${NORMAL_C} -Wunused-variable -Woverflow -Wparentheses -w" dev/pms/RefTisa/tisa/sassata/sas/ini/itdcb.c optional pmspcv \ compile-with "${NORMAL_C} -Wunused-variable -Woverflow -Wparentheses -w" dev/pms/RefTisa/tisa/sassata/sas/ini/itdinit.c optional pmspcv \ compile-with "${NORMAL_C} -Wunused-variable -Woverflow -Wparentheses -w" dev/pms/RefTisa/tisa/sassata/sas/ini/itddisc.c optional pmspcv \ compile-with "${NORMAL_C} -Wunused-variable -Woverflow -Wparentheses -w" dev/pms/RefTisa/tisa/sassata/sata/host/sat.c optional pmspcv \ compile-with "${NORMAL_C} -Wunused-variable -Woverflow -Wparentheses -w" dev/pms/RefTisa/tisa/sassata/sata/host/ossasat.c optional pmspcv \ compile-with "${NORMAL_C} -Wunused-variable -Woverflow -Wparentheses -w" dev/pms/RefTisa/tisa/sassata/sata/host/sathw.c optional pmspcv \ compile-with "${NORMAL_C} -Wunused-variable -Woverflow -Wparentheses -w" dev/ppbus/if_plip.c optional plip dev/ppbus/immio.c optional vpo dev/ppbus/lpbb.c optional lpbb dev/ppbus/lpt.c optional lpt dev/ppbus/pcfclock.c optional pcfclock dev/ppbus/ppb_1284.c optional ppbus dev/ppbus/ppb_base.c optional ppbus dev/ppbus/ppb_msq.c optional ppbus dev/ppbus/ppbconf.c optional ppbus dev/ppbus/ppbus_if.m optional ppbus dev/ppbus/ppi.c optional ppi dev/ppbus/pps.c optional pps dev/ppbus/vpo.c optional vpo dev/ppbus/vpoio.c optional vpo dev/ppc/ppc.c optional ppc dev/ppc/ppc_acpi.c optional ppc acpi dev/ppc/ppc_isa.c optional ppc isa dev/ppc/ppc_pci.c optional ppc pci dev/ppc/ppc_puc.c optional ppc puc dev/proto/proto_bus_isa.c optional proto acpi | proto isa dev/proto/proto_bus_pci.c optional proto pci dev/proto/proto_busdma.c optional proto dev/proto/proto_core.c optional proto dev/pst/pst-iop.c optional pst dev/pst/pst-pci.c optional pst pci dev/pst/pst-raid.c optional pst dev/pty/pty.c optional pty dev/puc/puc.c optional puc dev/puc/puc_cfg.c optional puc dev/puc/puc_pccard.c optional puc pccard dev/puc/puc_pci.c optional puc pci dev/puc/pucdata.c optional puc pci dev/quicc/quicc_core.c optional quicc dev/ral/rt2560.c optional ral dev/ral/rt2661.c optional ral dev/ral/rt2860.c optional ral dev/ral/if_ral_pci.c optional ral pci rt2561fw.c optional rt2561fw | ralfw \ compile-with "${AWK} -f $S/tools/fw_stub.awk rt2561.fw:rt2561fw -mrt2561 -c${.TARGET}" \ no-implicit-rule before-depend local \ clean "rt2561fw.c" rt2561fw.fwo optional rt2561fw | ralfw \ dependency "rt2561.fw" \ compile-with "${NORMAL_FWO}" \ no-implicit-rule \ clean "rt2561fw.fwo" rt2561.fw optional rt2561fw | ralfw \ dependency "$S/contrib/dev/ral/rt2561.fw.uu" \ compile-with "${NORMAL_FW}" \ no-obj no-implicit-rule \ clean "rt2561.fw" rt2561sfw.c optional rt2561sfw | ralfw \ compile-with "${AWK} -f $S/tools/fw_stub.awk rt2561s.fw:rt2561sfw -mrt2561s -c${.TARGET}" \ no-implicit-rule before-depend local \ clean "rt2561sfw.c" rt2561sfw.fwo optional rt2561sfw | ralfw \ dependency "rt2561s.fw" \ compile-with "${NORMAL_FWO}" \ no-implicit-rule \ clean "rt2561sfw.fwo" rt2561s.fw optional rt2561sfw | ralfw \ dependency "$S/contrib/dev/ral/rt2561s.fw.uu" \ compile-with "${NORMAL_FW}" \ no-obj no-implicit-rule \ clean "rt2561s.fw" rt2661fw.c optional rt2661fw | ralfw \ compile-with "${AWK} -f $S/tools/fw_stub.awk rt2661.fw:rt2661fw -mrt2661 -c${.TARGET}" \ no-implicit-rule before-depend local \ clean "rt2661fw.c" rt2661fw.fwo optional rt2661fw | ralfw \ dependency "rt2661.fw" \ compile-with "${NORMAL_FWO}" \ no-implicit-rule \ clean "rt2661fw.fwo" rt2661.fw optional rt2661fw | ralfw \ dependency "$S/contrib/dev/ral/rt2661.fw.uu" \ compile-with "${NORMAL_FW}" \ no-obj no-implicit-rule \ clean "rt2661.fw" rt2860fw.c optional rt2860fw | ralfw \ compile-with "${AWK} -f $S/tools/fw_stub.awk rt2860.fw:rt2860fw -mrt2860 -c${.TARGET}" \ no-implicit-rule before-depend local \ clean "rt2860fw.c" rt2860fw.fwo optional rt2860fw | ralfw \ dependency "rt2860.fw" \ compile-with "${NORMAL_FWO}" \ no-implicit-rule \ clean "rt2860fw.fwo" rt2860.fw optional rt2860fw | ralfw \ dependency "$S/contrib/dev/ral/rt2860.fw.uu" \ compile-with "${NORMAL_FW}" \ no-obj no-implicit-rule \ clean "rt2860.fw" dev/random/random_infra.c optional random dev/random/random_harvestq.c optional random dev/random/randomdev.c optional random random_yarrow | \ random !random_yarrow !random_loadable dev/random/yarrow.c optional random random_yarrow dev/random/fortuna.c optional random !random_yarrow !random_loadable dev/random/hash.c optional random random_yarrow | \ random !random_yarrow !random_loadable dev/rc/rc.c optional rc dev/rccgpio/rccgpio.c optional rccgpio gpio dev/re/if_re.c optional re dev/rl/if_rl.c optional rl pci dev/rndtest/rndtest.c optional rndtest dev/rp/rp.c optional rp dev/rp/rp_isa.c optional rp isa dev/rp/rp_pci.c optional rp pci # dev/rtwn/if_rtwn.c optional rtwn dev/rtwn/if_rtwn_beacon.c optional rtwn dev/rtwn/if_rtwn_calib.c optional rtwn dev/rtwn/if_rtwn_cam.c optional rtwn dev/rtwn/if_rtwn_efuse.c optional rtwn dev/rtwn/if_rtwn_fw.c optional rtwn dev/rtwn/if_rtwn_rx.c optional rtwn dev/rtwn/if_rtwn_task.c optional rtwn dev/rtwn/if_rtwn_tx.c optional rtwn # dev/rtwn/pci/rtwn_pci_attach.c optional rtwn_pci pci dev/rtwn/pci/rtwn_pci_reg.c optional rtwn_pci pci dev/rtwn/pci/rtwn_pci_rx.c optional rtwn_pci pci dev/rtwn/pci/rtwn_pci_tx.c optional rtwn_pci pci # dev/rtwn/usb/rtwn_usb_attach.c optional rtwn_usb dev/rtwn/usb/rtwn_usb_ep.c optional rtwn_usb dev/rtwn/usb/rtwn_usb_reg.c optional rtwn_usb dev/rtwn/usb/rtwn_usb_rx.c optional rtwn_usb dev/rtwn/usb/rtwn_usb_tx.c optional rtwn_usb # RTL8188E dev/rtwn/rtl8188e/r88e_beacon.c optional rtwn dev/rtwn/rtl8188e/r88e_calib.c optional rtwn dev/rtwn/rtl8188e/r88e_chan.c optional rtwn dev/rtwn/rtl8188e/r88e_fw.c optional rtwn dev/rtwn/rtl8188e/r88e_init.c optional rtwn dev/rtwn/rtl8188e/r88e_led.c optional rtwn dev/rtwn/rtl8188e/r88e_tx.c optional rtwn dev/rtwn/rtl8188e/r88e_rf.c optional rtwn dev/rtwn/rtl8188e/r88e_rom.c optional rtwn dev/rtwn/rtl8188e/r88e_rx.c optional rtwn dev/rtwn/rtl8188e/usb/r88eu_attach.c optional rtwn_usb dev/rtwn/rtl8188e/usb/r88eu_init.c optional rtwn_usb dev/rtwn/rtl8188e/usb/r88eu_rx.c optional rtwn_usb # RTL8192C dev/rtwn/rtl8192c/r92c_attach.c optional rtwn dev/rtwn/rtl8192c/r92c_beacon.c optional rtwn dev/rtwn/rtl8192c/r92c_calib.c optional rtwn dev/rtwn/rtl8192c/r92c_chan.c optional rtwn dev/rtwn/rtl8192c/r92c_fw.c optional rtwn dev/rtwn/rtl8192c/r92c_init.c optional rtwn dev/rtwn/rtl8192c/r92c_llt.c optional rtwn dev/rtwn/rtl8192c/r92c_rf.c optional rtwn dev/rtwn/rtl8192c/r92c_rom.c optional rtwn dev/rtwn/rtl8192c/r92c_rx.c optional rtwn dev/rtwn/rtl8192c/r92c_tx.c optional rtwn dev/rtwn/rtl8192c/pci/r92ce_attach.c optional rtwn_pci pci dev/rtwn/rtl8192c/pci/r92ce_calib.c optional rtwn_pci pci dev/rtwn/rtl8192c/pci/r92ce_fw.c optional rtwn_pci pci dev/rtwn/rtl8192c/pci/r92ce_init.c optional rtwn_pci pci dev/rtwn/rtl8192c/pci/r92ce_led.c optional rtwn_pci pci dev/rtwn/rtl8192c/pci/r92ce_rx.c optional rtwn_pci pci dev/rtwn/rtl8192c/pci/r92ce_tx.c optional rtwn_pci pci dev/rtwn/rtl8192c/usb/r92cu_attach.c optional rtwn_usb dev/rtwn/rtl8192c/usb/r92cu_init.c optional rtwn_usb dev/rtwn/rtl8192c/usb/r92cu_led.c optional rtwn_usb dev/rtwn/rtl8192c/usb/r92cu_rx.c optional rtwn_usb dev/rtwn/rtl8192c/usb/r92cu_tx.c optional rtwn_usb # RTL8192E dev/rtwn/rtl8192e/r92e_chan.c optional rtwn dev/rtwn/rtl8192e/r92e_fw.c optional rtwn dev/rtwn/rtl8192e/r92e_init.c optional rtwn dev/rtwn/rtl8192e/r92e_led.c optional rtwn dev/rtwn/rtl8192e/r92e_rf.c optional rtwn dev/rtwn/rtl8192e/r92e_rom.c optional rtwn dev/rtwn/rtl8192e/r92e_rx.c optional rtwn dev/rtwn/rtl8192e/usb/r92eu_attach.c optional rtwn_usb dev/rtwn/rtl8192e/usb/r92eu_init.c optional rtwn_usb # RTL8812A dev/rtwn/rtl8812a/r12a_beacon.c optional rtwn dev/rtwn/rtl8812a/r12a_calib.c optional rtwn dev/rtwn/rtl8812a/r12a_caps.c optional rtwn dev/rtwn/rtl8812a/r12a_chan.c optional rtwn dev/rtwn/rtl8812a/r12a_fw.c optional rtwn dev/rtwn/rtl8812a/r12a_init.c optional rtwn dev/rtwn/rtl8812a/r12a_led.c optional rtwn dev/rtwn/rtl8812a/r12a_rf.c optional rtwn dev/rtwn/rtl8812a/r12a_rom.c optional rtwn dev/rtwn/rtl8812a/r12a_rx.c optional rtwn dev/rtwn/rtl8812a/r12a_tx.c optional rtwn dev/rtwn/rtl8812a/usb/r12au_attach.c optional rtwn_usb dev/rtwn/rtl8812a/usb/r12au_init.c optional rtwn_usb dev/rtwn/rtl8812a/usb/r12au_rx.c optional rtwn_usb dev/rtwn/rtl8812a/usb/r12au_tx.c optional rtwn_usb # RTL8821A dev/rtwn/rtl8821a/r21a_beacon.c optional rtwn dev/rtwn/rtl8821a/r21a_calib.c optional rtwn dev/rtwn/rtl8821a/r21a_chan.c optional rtwn dev/rtwn/rtl8821a/r21a_fw.c optional rtwn dev/rtwn/rtl8821a/r21a_init.c optional rtwn dev/rtwn/rtl8821a/r21a_led.c optional rtwn dev/rtwn/rtl8821a/r21a_rom.c optional rtwn dev/rtwn/rtl8821a/r21a_rx.c optional rtwn dev/rtwn/rtl8821a/usb/r21au_attach.c optional rtwn_usb dev/rtwn/rtl8821a/usb/r21au_dfs.c optional rtwn_usb dev/rtwn/rtl8821a/usb/r21au_init.c optional rtwn_usb rtwn-rtl8188eufw.c optional rtwn-rtl8188eufw | rtwnfw \ compile-with "${AWK} -f $S/tools/fw_stub.awk rtwn-rtl8188eufw.fw:rtwn-rtl8188eufw:111 -mrtwn-rtl8188eufw -c${.TARGET}" \ no-implicit-rule before-depend local \ clean "rtwn-rtl8188eufw.c" rtwn-rtl8188eufw.fwo optional rtwn-rtl8188eufw | rtwnfw \ dependency "rtwn-rtl8188eufw.fw" \ compile-with "${NORMAL_FWO}" \ no-implicit-rule \ clean "rtwn-rtl8188eufw.fwo" rtwn-rtl8188eufw.fw optional rtwn-rtl8188eufw | rtwnfw \ dependency "$S/contrib/dev/rtwn/rtwn-rtl8188eufw.fw.uu" \ compile-with "${NORMAL_FW}" \ no-obj no-implicit-rule \ clean "rtwn-rtl8188eufw.fw" rtwn-rtl8192cfwE.c optional rtwn-rtl8192cfwE | rtwnfw \ compile-with "${AWK} -f $S/tools/fw_stub.awk rtwn-rtl8192cfwE.fw:rtwn-rtl8192cfwE:111 -mrtwn-rtl8192cfwE -c${.TARGET}" \ no-implicit-rule before-depend local \ clean "rtwn-rtl8192cfwE.c" rtwn-rtl8192cfwE.fwo optional rtwn-rtl8192cfwE | rtwnfw \ dependency "rtwn-rtl8192cfwE.fw" \ compile-with "${NORMAL_FWO}" \ no-implicit-rule \ clean "rtwn-rtl8192cfwE.fwo" rtwn-rtl8192cfwE.fw optional rtwn-rtl8192cfwE | rtwnfw \ dependency "$S/contrib/dev/rtwn/rtwn-rtl8192cfwE.fw.uu" \ compile-with "${NORMAL_FW}" \ no-obj no-implicit-rule \ clean "rtwn-rtl8192cfwE.fw" rtwn-rtl8192cfwE_B.c optional rtwn-rtl8192cfwE_B | rtwnfw \ compile-with "${AWK} -f $S/tools/fw_stub.awk rtwn-rtl8192cfwE_B.fw:rtwn-rtl8192cfwE_B:111 -mrtwn-rtl8192cfwE_B -c${.TARGET}" \ no-implicit-rule before-depend local \ clean "rtwn-rtl8192cfwE_B.c" rtwn-rtl8192cfwE_B.fwo optional rtwn-rtl8192cfwE_B | rtwnfw \ dependency "rtwn-rtl8192cfwE_B.fw" \ compile-with "${NORMAL_FWO}" \ no-implicit-rule \ clean "rtwn-rtl8192cfwE_B.fwo" rtwn-rtl8192cfwE_B.fw optional rtwn-rtl8192cfwE_B | rtwnfw \ dependency "$S/contrib/dev/rtwn/rtwn-rtl8192cfwE_B.fw.uu" \ compile-with "${NORMAL_FW}" \ no-obj no-implicit-rule \ clean "rtwn-rtl8192cfwE_B.fw" rtwn-rtl8192cfwT.c optional rtwn-rtl8192cfwT | rtwnfw \ compile-with "${AWK} -f $S/tools/fw_stub.awk rtwn-rtl8192cfwT.fw:rtwn-rtl8192cfwT:111 -mrtwn-rtl8192cfwT -c${.TARGET}" \ no-implicit-rule before-depend local \ clean "rtwn-rtl8192cfwT.c" rtwn-rtl8192cfwT.fwo optional rtwn-rtl8192cfwT | rtwnfw \ dependency "rtwn-rtl8192cfwT.fw" \ compile-with "${NORMAL_FWO}" \ no-implicit-rule \ clean "rtwn-rtl8192cfwT.fwo" rtwn-rtl8192cfwT.fw optional rtwn-rtl8192cfwT | rtwnfw \ dependency "$S/contrib/dev/rtwn/rtwn-rtl8192cfwT.fw.uu" \ compile-with "${NORMAL_FW}" \ no-obj no-implicit-rule \ clean "rtwn-rtl8192cfwT.fw" rtwn-rtl8192cfwU.c optional rtwn-rtl8192cfwU | rtwnfw \ compile-with "${AWK} -f $S/tools/fw_stub.awk rtwn-rtl8192cfwU.fw:rtwn-rtl8192cfwU:111 -mrtwn-rtl8192cfwU -c${.TARGET}" \ no-implicit-rule before-depend local \ clean "rtwn-rtl8192cfwU.c" rtwn-rtl8192cfwU.fwo optional rtwn-rtl8192cfwU | rtwnfw \ dependency "rtwn-rtl8192cfwU.fw" \ compile-with "${NORMAL_FWO}" \ no-implicit-rule \ clean "rtwn-rtl8192cfwU.fwo" rtwn-rtl8192cfwU.fw optional rtwn-rtl8192cfwU | rtwnfw \ dependency "$S/contrib/dev/rtwn/rtwn-rtl8192cfwU.fw.uu" \ compile-with "${NORMAL_FW}" \ no-obj no-implicit-rule \ clean "rtwn-rtl8192cfwU.fw" rtwn-rtl8192eufw.c optional rtwn-rtl8192eufw | rtwnfw \ compile-with "${AWK} -f $S/tools/fw_stub.awk rtwn-rtl8192eufw.fw:rtwn-rtl8192eufw:111 -mrtwn-rtl8192eufw -c${.TARGET}" \ no-implicit-rule before-depend local \ clean "rtwn-rtl8192eufw.c" rtwn-rtl8192eufw.fwo optional rtwn-rtl8192eufw | rtwnfw \ dependency "rtwn-rtl8192eufw.fw" \ compile-with "${NORMAL_FWO}" \ no-implicit-rule \ clean "rtwn-rtl8192eufw.fwo" rtwn-rtl8192eufw.fw optional rtwn-rtl8192eufw | rtwnfw \ dependency "$S/contrib/dev/rtwn/rtwn-rtl8192eufw.fw.uu" \ compile-with "${NORMAL_FW}" \ no-obj no-implicit-rule \ clean "rtwn-rtl8192eufw.fw" rtwn-rtl8812aufw.c optional rtwn-rtl8812aufw | rtwnfw \ compile-with "${AWK} -f $S/tools/fw_stub.awk rtwn-rtl8812aufw.fw:rtwn-rtl8812aufw:111 -mrtwn-rtl8812aufw -c${.TARGET}" \ no-implicit-rule before-depend local \ clean "rtwn-rtl8812aufw.c" rtwn-rtl8812aufw.fwo optional rtwn-rtl8812aufw | rtwnfw \ dependency "rtwn-rtl8812aufw.fw" \ compile-with "${NORMAL_FWO}" \ no-implicit-rule \ clean "rtwn-rtl8812aufw.fwo" rtwn-rtl8812aufw.fw optional rtwn-rtl8812aufw | rtwnfw \ dependency "$S/contrib/dev/rtwn/rtwn-rtl8812aufw.fw.uu" \ compile-with "${NORMAL_FW}" \ no-obj no-implicit-rule \ clean "rtwn-rtl8812aufw.fw" rtwn-rtl8821aufw.c optional rtwn-rtl8821aufw | rtwnfw \ compile-with "${AWK} -f $S/tools/fw_stub.awk rtwn-rtl8821aufw.fw:rtwn-rtl8821aufw:111 -mrtwn-rtl8821aufw -c${.TARGET}" \ no-implicit-rule before-depend local \ clean "rtwn-rtl8821aufw.c" rtwn-rtl8821aufw.fwo optional rtwn-rtl8821aufw | rtwnfw \ dependency "rtwn-rtl8821aufw.fw" \ compile-with "${NORMAL_FWO}" \ no-implicit-rule \ clean "rtwn-rtl8821aufw.fwo" rtwn-rtl8821aufw.fw optional rtwn-rtl8821aufw | rtwnfw \ dependency "$S/contrib/dev/rtwn/rtwn-rtl8821aufw.fw.uu" \ compile-with "${NORMAL_FW}" \ no-obj no-implicit-rule \ clean "rtwn-rtl8821aufw.fw" dev/safe/safe.c optional safe dev/scc/scc_if.m optional scc dev/scc/scc_bfe_ebus.c optional scc ebus dev/scc/scc_bfe_quicc.c optional scc quicc dev/scc/scc_bfe_sbus.c optional scc fhc | scc sbus dev/scc/scc_core.c optional scc dev/scc/scc_dev_quicc.c optional scc quicc dev/scc/scc_dev_sab82532.c optional scc dev/scc/scc_dev_z8530.c optional scc dev/sdhci/sdhci.c optional sdhci dev/sdhci/sdhci_fdt.c optional sdhci fdt dev/sdhci/sdhci_fdt_gpio.c optional sdhci fdt gpio dev/sdhci/sdhci_if.m optional sdhci dev/sdhci/sdhci_acpi.c optional sdhci acpi dev/sdhci/sdhci_pci.c optional sdhci pci dev/sf/if_sf.c optional sf pci dev/sge/if_sge.c optional sge pci -dev/siba/siba_bwn.c optional siba_bwn pci -dev/siba/siba_core.c optional siba_bwn pci dev/siis/siis.c optional siis pci dev/sis/if_sis.c optional sis pci dev/sk/if_sk.c optional sk pci dev/smbus/smb.c optional smb dev/smbus/smbconf.c optional smbus dev/smbus/smbus.c optional smbus dev/smbus/smbus_if.m optional smbus dev/smc/if_smc.c optional smc dev/smc/if_smc_fdt.c optional smc fdt dev/sn/if_sn.c optional sn dev/sn/if_sn_isa.c optional sn isa dev/sn/if_sn_pccard.c optional sn pccard dev/snp/snp.c optional snp dev/sound/clone.c optional sound dev/sound/unit.c optional sound dev/sound/isa/ad1816.c optional snd_ad1816 isa dev/sound/isa/ess.c optional snd_ess isa dev/sound/isa/gusc.c optional snd_gusc isa dev/sound/isa/mss.c optional snd_mss isa dev/sound/isa/sb16.c optional snd_sb16 isa dev/sound/isa/sb8.c optional snd_sb8 isa dev/sound/isa/sbc.c optional snd_sbc isa dev/sound/isa/sndbuf_dma.c optional sound isa dev/sound/pci/als4000.c optional snd_als4000 pci dev/sound/pci/atiixp.c optional snd_atiixp pci dev/sound/pci/cmi.c optional snd_cmi pci dev/sound/pci/cs4281.c optional snd_cs4281 pci dev/sound/pci/csa.c optional snd_csa pci dev/sound/pci/csapcm.c optional snd_csa pci dev/sound/pci/ds1.c optional snd_ds1 pci dev/sound/pci/emu10k1.c optional snd_emu10k1 pci dev/sound/pci/emu10kx.c optional snd_emu10kx pci dev/sound/pci/emu10kx-pcm.c optional snd_emu10kx pci dev/sound/pci/emu10kx-midi.c optional snd_emu10kx pci dev/sound/pci/envy24.c optional snd_envy24 pci dev/sound/pci/envy24ht.c optional snd_envy24ht pci dev/sound/pci/es137x.c optional snd_es137x pci dev/sound/pci/fm801.c optional snd_fm801 pci dev/sound/pci/ich.c optional snd_ich pci dev/sound/pci/maestro.c optional snd_maestro pci dev/sound/pci/maestro3.c optional snd_maestro3 pci dev/sound/pci/neomagic.c optional snd_neomagic pci dev/sound/pci/solo.c optional snd_solo pci dev/sound/pci/spicds.c optional snd_spicds pci dev/sound/pci/t4dwave.c optional snd_t4dwave pci dev/sound/pci/via8233.c optional snd_via8233 pci dev/sound/pci/via82c686.c optional snd_via82c686 pci dev/sound/pci/vibes.c optional snd_vibes pci dev/sound/pci/hda/hdaa.c optional snd_hda pci dev/sound/pci/hda/hdaa_patches.c optional snd_hda pci dev/sound/pci/hda/hdac.c optional snd_hda pci dev/sound/pci/hda/hdac_if.m optional snd_hda pci dev/sound/pci/hda/hdacc.c optional snd_hda pci dev/sound/pci/hdspe.c optional snd_hdspe pci dev/sound/pci/hdspe-pcm.c optional snd_hdspe pci dev/sound/pcm/ac97.c optional sound dev/sound/pcm/ac97_if.m optional sound dev/sound/pcm/ac97_patch.c optional sound dev/sound/pcm/buffer.c optional sound \ dependency "snd_fxdiv_gen.h" dev/sound/pcm/channel.c optional sound dev/sound/pcm/channel_if.m optional sound dev/sound/pcm/dsp.c optional sound dev/sound/pcm/feeder.c optional sound dev/sound/pcm/feeder_chain.c optional sound dev/sound/pcm/feeder_eq.c optional sound \ dependency "feeder_eq_gen.h" \ dependency "snd_fxdiv_gen.h" dev/sound/pcm/feeder_if.m optional sound dev/sound/pcm/feeder_format.c optional sound \ dependency "snd_fxdiv_gen.h" dev/sound/pcm/feeder_matrix.c optional sound \ dependency "snd_fxdiv_gen.h" dev/sound/pcm/feeder_mixer.c optional sound \ dependency "snd_fxdiv_gen.h" dev/sound/pcm/feeder_rate.c optional sound \ dependency "feeder_rate_gen.h" \ dependency "snd_fxdiv_gen.h" dev/sound/pcm/feeder_volume.c optional sound \ dependency "snd_fxdiv_gen.h" dev/sound/pcm/mixer.c optional sound dev/sound/pcm/mixer_if.m optional sound dev/sound/pcm/sndstat.c optional sound dev/sound/pcm/sound.c optional sound dev/sound/pcm/vchan.c optional sound dev/sound/usb/uaudio.c optional snd_uaudio usb dev/sound/usb/uaudio_pcm.c optional snd_uaudio usb dev/sound/midi/midi.c optional sound dev/sound/midi/mpu401.c optional sound dev/sound/midi/mpu_if.m optional sound dev/sound/midi/mpufoi_if.m optional sound dev/sound/midi/sequencer.c optional sound dev/sound/midi/synth_if.m optional sound dev/spibus/ofw_spibus.c optional fdt spibus dev/spibus/spibus.c optional spibus \ dependency "spibus_if.h" dev/spibus/spigen.c optional spigen dev/spibus/spibus_if.m optional spibus dev/ste/if_ste.c optional ste pci dev/stg/tmc18c30.c optional stg dev/stg/tmc18c30_isa.c optional stg isa dev/stg/tmc18c30_pccard.c optional stg pccard dev/stg/tmc18c30_pci.c optional stg pci dev/stg/tmc18c30_subr.c optional stg dev/stge/if_stge.c optional stge dev/sym/sym_hipd.c optional sym \ dependency "$S/dev/sym/sym_{conf,defs}.h" dev/syscons/blank/blank_saver.c optional blank_saver dev/syscons/daemon/daemon_saver.c optional daemon_saver dev/syscons/dragon/dragon_saver.c optional dragon_saver dev/syscons/fade/fade_saver.c optional fade_saver dev/syscons/fire/fire_saver.c optional fire_saver dev/syscons/green/green_saver.c optional green_saver dev/syscons/logo/logo.c optional logo_saver dev/syscons/logo/logo_saver.c optional logo_saver dev/syscons/rain/rain_saver.c optional rain_saver dev/syscons/schistory.c optional sc dev/syscons/scmouse.c optional sc dev/syscons/scterm.c optional sc dev/syscons/scvidctl.c optional sc dev/syscons/snake/snake_saver.c optional snake_saver dev/syscons/star/star_saver.c optional star_saver dev/syscons/syscons.c optional sc dev/syscons/sysmouse.c optional sc dev/syscons/warp/warp_saver.c optional warp_saver dev/tdfx/tdfx_linux.c optional tdfx_linux tdfx compat_linux dev/tdfx/tdfx_pci.c optional tdfx pci dev/ti/if_ti.c optional ti pci dev/tl/if_tl.c optional tl pci dev/trm/trm.c optional trm dev/twa/tw_cl_init.c optional twa \ compile-with "${NORMAL_C} -I$S/dev/twa" dev/twa/tw_cl_intr.c optional twa \ compile-with "${NORMAL_C} -I$S/dev/twa" dev/twa/tw_cl_io.c optional twa \ compile-with "${NORMAL_C} -I$S/dev/twa" dev/twa/tw_cl_misc.c optional twa \ compile-with "${NORMAL_C} -I$S/dev/twa" dev/twa/tw_osl_cam.c optional twa \ compile-with "${NORMAL_C} -I$S/dev/twa" dev/twa/tw_osl_freebsd.c optional twa \ compile-with "${NORMAL_C} -I$S/dev/twa" dev/twe/twe.c optional twe dev/twe/twe_freebsd.c optional twe dev/tws/tws.c optional tws dev/tws/tws_cam.c optional tws dev/tws/tws_hdm.c optional tws dev/tws/tws_services.c optional tws dev/tws/tws_user.c optional tws dev/tx/if_tx.c optional tx dev/txp/if_txp.c optional txp dev/uart/uart_bus_acpi.c optional uart acpi dev/uart/uart_bus_ebus.c optional uart ebus dev/uart/uart_bus_fdt.c optional uart fdt dev/uart/uart_bus_isa.c optional uart isa dev/uart/uart_bus_pccard.c optional uart pccard dev/uart/uart_bus_pci.c optional uart pci dev/uart/uart_bus_puc.c optional uart puc dev/uart/uart_bus_scc.c optional uart scc dev/uart/uart_core.c optional uart dev/uart/uart_dbg.c optional uart gdb dev/uart/uart_dev_msm.c optional uart uart_msm fdt dev/uart/uart_dev_mvebu.c optional uart uart_mvebu dev/uart/uart_dev_ns8250.c optional uart uart_ns8250 | uart uart_snps dev/uart/uart_dev_pl011.c optional uart pl011 dev/uart/uart_dev_quicc.c optional uart quicc dev/uart/uart_dev_sab82532.c optional uart uart_sab82532 dev/uart/uart_dev_sab82532.c optional uart scc dev/uart/uart_dev_snps.c optional uart uart_snps fdt dev/uart/uart_dev_z8530.c optional uart uart_z8530 dev/uart/uart_dev_z8530.c optional uart scc dev/uart/uart_if.m optional uart dev/uart/uart_subr.c optional uart dev/uart/uart_tty.c optional uart dev/ubsec/ubsec.c optional ubsec # # USB controller drivers # dev/usb/controller/at91dci.c optional at91dci dev/usb/controller/at91dci_atmelarm.c optional at91dci at91rm9200 dev/usb/controller/musb_otg.c optional musb dev/usb/controller/musb_otg_atmelarm.c optional musb at91rm9200 dev/usb/controller/dwc_otg.c optional dwcotg dev/usb/controller/dwc_otg_fdt.c optional dwcotg fdt dev/usb/controller/ehci.c optional ehci dev/usb/controller/ehci_msm.c optional ehci_msm fdt dev/usb/controller/ehci_pci.c optional ehci pci dev/usb/controller/ohci.c optional ohci dev/usb/controller/ohci_pci.c optional ohci pci dev/usb/controller/uhci.c optional uhci dev/usb/controller/uhci_pci.c optional uhci pci dev/usb/controller/xhci.c optional xhci dev/usb/controller/xhci_pci.c optional xhci pci dev/usb/controller/saf1761_otg.c optional saf1761otg dev/usb/controller/saf1761_otg_fdt.c optional saf1761otg fdt dev/usb/controller/uss820dci.c optional uss820dci dev/usb/controller/uss820dci_atmelarm.c optional uss820dci at91rm9200 dev/usb/controller/usb_controller.c optional usb # # USB storage drivers # dev/usb/storage/cfumass.c optional cfumass ctl dev/usb/storage/umass.c optional umass dev/usb/storage/urio.c optional urio dev/usb/storage/ustorage_fs.c optional usfs # # USB core # dev/usb/usb_busdma.c optional usb dev/usb/usb_core.c optional usb dev/usb/usb_debug.c optional usb dev/usb/usb_dev.c optional usb dev/usb/usb_device.c optional usb dev/usb/usb_dynamic.c optional usb dev/usb/usb_error.c optional usb dev/usb/usb_generic.c optional usb dev/usb/usb_handle_request.c optional usb dev/usb/usb_hid.c optional usb dev/usb/usb_hub.c optional usb dev/usb/usb_if.m optional usb dev/usb/usb_lookup.c optional usb dev/usb/usb_mbuf.c optional usb dev/usb/usb_msctest.c optional usb dev/usb/usb_parse.c optional usb dev/usb/usb_pf.c optional usb dev/usb/usb_process.c optional usb dev/usb/usb_request.c optional usb dev/usb/usb_transfer.c optional usb dev/usb/usb_util.c optional usb # # USB network drivers # dev/usb/net/if_aue.c optional aue dev/usb/net/if_axe.c optional axe dev/usb/net/if_axge.c optional axge dev/usb/net/if_cdce.c optional cdce dev/usb/net/if_cue.c optional cue dev/usb/net/if_ipheth.c optional ipheth dev/usb/net/if_kue.c optional kue dev/usb/net/if_mos.c optional mos dev/usb/net/if_rue.c optional rue dev/usb/net/if_smsc.c optional smsc dev/usb/net/if_udav.c optional udav dev/usb/net/if_ure.c optional ure dev/usb/net/if_usie.c optional usie dev/usb/net/if_urndis.c optional urndis dev/usb/net/ruephy.c optional rue dev/usb/net/usb_ethernet.c optional uether | aue | axe | axge | cdce | \ cue | ipheth | kue | mos | rue | \ smsc | udav | ure | urndis dev/usb/net/uhso.c optional uhso # # USB WLAN drivers # dev/usb/wlan/if_rsu.c optional rsu rsu-rtl8712fw.c optional rsu-rtl8712fw | rsufw \ compile-with "${AWK} -f $S/tools/fw_stub.awk rsu-rtl8712fw.fw:rsu-rtl8712fw:120 -mrsu-rtl8712fw -c${.TARGET}" \ no-implicit-rule before-depend local \ clean "rsu-rtl8712fw.c" rsu-rtl8712fw.fwo optional rsu-rtl8712fw | rsufw \ dependency "rsu-rtl8712fw.fw" \ compile-with "${NORMAL_FWO}" \ no-implicit-rule \ clean "rsu-rtl8712fw.fwo" rsu-rtl8712fw.fw optional rsu-rtl8712.fw | rsufw \ dependency "$S/contrib/dev/rsu/rsu-rtl8712fw.fw.uu" \ compile-with "${NORMAL_FW}" \ no-obj no-implicit-rule \ clean "rsu-rtl8712fw.fw" dev/usb/wlan/if_rum.c optional rum dev/usb/wlan/if_run.c optional run runfw.c optional runfw \ compile-with "${AWK} -f $S/tools/fw_stub.awk run.fw:runfw -mrunfw -c${.TARGET}" \ no-implicit-rule before-depend local \ clean "runfw.c" runfw.fwo optional runfw \ dependency "run.fw" \ compile-with "${NORMAL_FWO}" \ no-implicit-rule \ clean "runfw.fwo" run.fw optional runfw \ dependency "$S/contrib/dev/run/rt2870.fw.uu" \ compile-with "${NORMAL_FW}" \ no-obj no-implicit-rule \ clean "run.fw" dev/usb/wlan/if_uath.c optional uath dev/usb/wlan/if_upgt.c optional upgt dev/usb/wlan/if_ural.c optional ural dev/usb/wlan/if_urtw.c optional urtw dev/usb/wlan/if_zyd.c optional zyd # # USB serial and parallel port drivers # dev/usb/serial/u3g.c optional u3g dev/usb/serial/uark.c optional uark dev/usb/serial/ubsa.c optional ubsa dev/usb/serial/ubser.c optional ubser dev/usb/serial/uchcom.c optional uchcom dev/usb/serial/ucycom.c optional ucycom dev/usb/serial/ufoma.c optional ufoma dev/usb/serial/uftdi.c optional uftdi dev/usb/serial/ugensa.c optional ugensa dev/usb/serial/uipaq.c optional uipaq dev/usb/serial/ulpt.c optional ulpt dev/usb/serial/umcs.c optional umcs dev/usb/serial/umct.c optional umct dev/usb/serial/umodem.c optional umodem dev/usb/serial/umoscom.c optional umoscom dev/usb/serial/uplcom.c optional uplcom dev/usb/serial/uslcom.c optional uslcom dev/usb/serial/uvisor.c optional uvisor dev/usb/serial/uvscom.c optional uvscom dev/usb/serial/usb_serial.c optional ucom | u3g | uark | ubsa | ubser | \ uchcom | ucycom | ufoma | uftdi | \ ugensa | uipaq | umcs | umct | \ umodem | umoscom | uplcom | usie | \ uslcom | uvisor | uvscom # # USB misc drivers # dev/usb/misc/ufm.c optional ufm dev/usb/misc/udbp.c optional udbp dev/usb/misc/ugold.c optional ugold dev/usb/misc/uled.c optional uled # # USB input drivers # dev/usb/input/atp.c optional atp dev/usb/input/uep.c optional uep dev/usb/input/uhid.c optional uhid dev/usb/input/ukbd.c optional ukbd dev/usb/input/ums.c optional ums dev/usb/input/wmt.c optional wmt dev/usb/input/wsp.c optional wsp # # USB quirks # dev/usb/quirk/usb_quirk.c optional usb # # USB templates # dev/usb/template/usb_template.c optional usb_template dev/usb/template/usb_template_audio.c optional usb_template dev/usb/template/usb_template_cdce.c optional usb_template dev/usb/template/usb_template_kbd.c optional usb_template dev/usb/template/usb_template_modem.c optional usb_template dev/usb/template/usb_template_mouse.c optional usb_template dev/usb/template/usb_template_msc.c optional usb_template dev/usb/template/usb_template_mtp.c optional usb_template dev/usb/template/usb_template_phone.c optional usb_template dev/usb/template/usb_template_serialnet.c optional usb_template dev/usb/template/usb_template_midi.c optional usb_template # # USB video drivers # dev/usb/video/udl.c optional udl # # USB END # dev/videomode/videomode.c optional videomode dev/videomode/edid.c optional videomode dev/videomode/pickmode.c optional videomode dev/videomode/vesagtf.c optional videomode dev/vge/if_vge.c optional vge dev/viapm/viapm.c optional viapm pci dev/virtio/virtio.c optional virtio dev/virtio/virtqueue.c optional virtio dev/virtio/virtio_bus_if.m optional virtio dev/virtio/virtio_if.m optional virtio dev/virtio/pci/virtio_pci.c optional virtio_pci dev/virtio/mmio/virtio_mmio.c optional virtio_mmio fdt dev/virtio/mmio/virtio_mmio_if.m optional virtio_mmio fdt dev/virtio/network/if_vtnet.c optional vtnet dev/virtio/block/virtio_blk.c optional virtio_blk dev/virtio/balloon/virtio_balloon.c optional virtio_balloon dev/virtio/scsi/virtio_scsi.c optional virtio_scsi dev/virtio/random/virtio_random.c optional virtio_random dev/virtio/console/virtio_console.c optional virtio_console dev/vkbd/vkbd.c optional vkbd dev/vr/if_vr.c optional vr pci dev/vt/colors/vt_termcolors.c optional vt dev/vt/font/vt_font_default.c optional vt dev/vt/font/vt_mouse_cursor.c optional vt dev/vt/hw/efifb/efifb.c optional vt_efifb dev/vt/hw/fb/vt_fb.c optional vt dev/vt/hw/vga/vt_vga.c optional vt vt_vga dev/vt/logo/logo_freebsd.c optional vt splash dev/vt/logo/logo_beastie.c optional vt splash dev/vt/vt_buf.c optional vt dev/vt/vt_consolectl.c optional vt dev/vt/vt_core.c optional vt dev/vt/vt_cpulogos.c optional vt splash dev/vt/vt_font.c optional vt dev/vt/vt_sysmouse.c optional vt dev/vte/if_vte.c optional vte pci dev/vx/if_vx.c optional vx dev/vx/if_vx_pci.c optional vx pci dev/vxge/vxge.c optional vxge dev/vxge/vxgehal/vxgehal-ifmsg.c optional vxge dev/vxge/vxgehal/vxgehal-mrpcim.c optional vxge dev/vxge/vxgehal/vxge-queue.c optional vxge dev/vxge/vxgehal/vxgehal-ring.c optional vxge dev/vxge/vxgehal/vxgehal-swapper.c optional vxge dev/vxge/vxgehal/vxgehal-mgmt.c optional vxge dev/vxge/vxgehal/vxgehal-srpcim.c optional vxge dev/vxge/vxgehal/vxgehal-config.c optional vxge dev/vxge/vxgehal/vxgehal-blockpool.c optional vxge dev/vxge/vxgehal/vxgehal-doorbells.c optional vxge dev/vxge/vxgehal/vxgehal-mgmtaux.c optional vxge dev/vxge/vxgehal/vxgehal-device.c optional vxge dev/vxge/vxgehal/vxgehal-mm.c optional vxge dev/vxge/vxgehal/vxgehal-driver.c optional vxge dev/vxge/vxgehal/vxgehal-virtualpath.c optional vxge dev/vxge/vxgehal/vxgehal-channel.c optional vxge dev/vxge/vxgehal/vxgehal-fifo.c optional vxge dev/watchdog/watchdog.c standard dev/wb/if_wb.c optional wb pci dev/wi/if_wi.c optional wi dev/wi/if_wi_pccard.c optional wi pccard dev/wi/if_wi_pci.c optional wi pci dev/wpi/if_wpi.c optional wpi pci wpifw.c optional wpifw \ compile-with "${AWK} -f $S/tools/fw_stub.awk wpi.fw:wpifw:153229 -mwpi -c${.TARGET}" \ no-implicit-rule before-depend local \ clean "wpifw.c" wpifw.fwo optional wpifw \ dependency "wpi.fw" \ compile-with "${NORMAL_FWO}" \ no-implicit-rule \ clean "wpifw.fwo" wpi.fw optional wpifw \ dependency "$S/contrib/dev/wpi/iwlwifi-3945-15.32.2.9.fw.uu" \ compile-with "${NORMAL_FW}" \ no-obj no-implicit-rule \ clean "wpi.fw" dev/xdma/xdma.c optional xdma dev/xdma/xdma_if.m optional xdma dev/xdma/xdma_fdt_test.c optional xdma xdma_test fdt dev/xe/if_xe.c optional xe dev/xe/if_xe_pccard.c optional xe pccard dev/xen/balloon/balloon.c optional xenhvm dev/xen/blkfront/blkfront.c optional xenhvm dev/xen/blkback/blkback.c optional xenhvm dev/xen/console/xen_console.c optional xenhvm dev/xen/control/control.c optional xenhvm dev/xen/grant_table/grant_table.c optional xenhvm dev/xen/netback/netback.c optional xenhvm dev/xen/netfront/netfront.c optional xenhvm dev/xen/xenpci/xenpci.c optional xenpci dev/xen/timer/timer.c optional xenhvm dev/xen/pvcpu/pvcpu.c optional xenhvm dev/xen/xenstore/xenstore.c optional xenhvm dev/xen/xenstore/xenstore_dev.c optional xenhvm dev/xen/xenstore/xenstored_dev.c optional xenhvm dev/xen/evtchn/evtchn_dev.c optional xenhvm dev/xen/privcmd/privcmd.c optional xenhvm dev/xen/gntdev/gntdev.c optional xenhvm dev/xen/debug/debug.c optional xenhvm dev/xl/if_xl.c optional xl pci dev/xl/xlphy.c optional xl pci fs/autofs/autofs.c optional autofs fs/autofs/autofs_vfsops.c optional autofs fs/autofs/autofs_vnops.c optional autofs fs/deadfs/dead_vnops.c standard fs/devfs/devfs_devs.c standard fs/devfs/devfs_dir.c standard fs/devfs/devfs_rule.c standard fs/devfs/devfs_vfsops.c standard fs/devfs/devfs_vnops.c standard fs/fdescfs/fdesc_vfsops.c optional fdescfs fs/fdescfs/fdesc_vnops.c optional fdescfs fs/fifofs/fifo_vnops.c standard fs/cuse/cuse.c optional cuse fs/fuse/fuse_device.c optional fuse fs/fuse/fuse_file.c optional fuse fs/fuse/fuse_internal.c optional fuse fs/fuse/fuse_io.c optional fuse fs/fuse/fuse_ipc.c optional fuse fs/fuse/fuse_main.c optional fuse fs/fuse/fuse_node.c optional fuse fs/fuse/fuse_vfsops.c optional fuse fs/fuse/fuse_vnops.c optional fuse fs/msdosfs/msdosfs_conv.c optional msdosfs fs/msdosfs/msdosfs_denode.c optional msdosfs fs/msdosfs/msdosfs_fat.c optional msdosfs fs/msdosfs/msdosfs_iconv.c optional msdosfs_iconv fs/msdosfs/msdosfs_lookup.c optional msdosfs fs/msdosfs/msdosfs_vfsops.c optional msdosfs fs/msdosfs/msdosfs_vnops.c optional msdosfs fs/nandfs/bmap.c optional nandfs fs/nandfs/nandfs_alloc.c optional nandfs fs/nandfs/nandfs_bmap.c optional nandfs fs/nandfs/nandfs_buffer.c optional nandfs fs/nandfs/nandfs_cleaner.c optional nandfs fs/nandfs/nandfs_cpfile.c optional nandfs fs/nandfs/nandfs_dat.c optional nandfs fs/nandfs/nandfs_dir.c optional nandfs fs/nandfs/nandfs_ifile.c optional nandfs fs/nandfs/nandfs_segment.c optional nandfs fs/nandfs/nandfs_subr.c optional nandfs fs/nandfs/nandfs_sufile.c optional nandfs fs/nandfs/nandfs_vfsops.c optional nandfs fs/nandfs/nandfs_vnops.c optional nandfs fs/nfs/nfs_commonkrpc.c optional nfscl | nfsd fs/nfs/nfs_commonsubs.c optional nfscl | nfsd fs/nfs/nfs_commonport.c optional nfscl | nfsd fs/nfs/nfs_commonacl.c optional nfscl | nfsd fs/nfsclient/nfs_clcomsubs.c optional nfscl fs/nfsclient/nfs_clsubs.c optional nfscl fs/nfsclient/nfs_clstate.c optional nfscl fs/nfsclient/nfs_clkrpc.c optional nfscl fs/nfsclient/nfs_clrpcops.c optional nfscl fs/nfsclient/nfs_clvnops.c optional nfscl fs/nfsclient/nfs_clnode.c optional nfscl fs/nfsclient/nfs_clvfsops.c optional nfscl fs/nfsclient/nfs_clport.c optional nfscl fs/nfsclient/nfs_clbio.c optional nfscl fs/nfsclient/nfs_clnfsiod.c optional nfscl fs/nfsserver/nfs_fha_new.c optional nfsd inet fs/nfsserver/nfs_nfsdsocket.c optional nfsd inet fs/nfsserver/nfs_nfsdsubs.c optional nfsd inet fs/nfsserver/nfs_nfsdstate.c optional nfsd inet fs/nfsserver/nfs_nfsdkrpc.c optional nfsd inet fs/nfsserver/nfs_nfsdserv.c optional nfsd inet fs/nfsserver/nfs_nfsdport.c optional nfsd inet fs/nfsserver/nfs_nfsdcache.c optional nfsd inet fs/nullfs/null_subr.c optional nullfs fs/nullfs/null_vfsops.c optional nullfs fs/nullfs/null_vnops.c optional nullfs fs/procfs/procfs.c optional procfs fs/procfs/procfs_dbregs.c optional procfs fs/procfs/procfs_fpregs.c optional procfs fs/procfs/procfs_ioctl.c optional procfs fs/procfs/procfs_map.c optional procfs fs/procfs/procfs_mem.c optional procfs fs/procfs/procfs_note.c optional procfs fs/procfs/procfs_osrel.c optional procfs fs/procfs/procfs_regs.c optional procfs fs/procfs/procfs_rlimit.c optional procfs fs/procfs/procfs_status.c optional procfs fs/procfs/procfs_type.c optional procfs fs/pseudofs/pseudofs.c optional pseudofs fs/pseudofs/pseudofs_fileno.c optional pseudofs fs/pseudofs/pseudofs_vncache.c optional pseudofs fs/pseudofs/pseudofs_vnops.c optional pseudofs fs/smbfs/smbfs_io.c optional smbfs fs/smbfs/smbfs_node.c optional smbfs fs/smbfs/smbfs_smb.c optional smbfs fs/smbfs/smbfs_subr.c optional smbfs fs/smbfs/smbfs_vfsops.c optional smbfs fs/smbfs/smbfs_vnops.c optional smbfs fs/udf/osta.c optional udf fs/udf/udf_iconv.c optional udf_iconv fs/udf/udf_vfsops.c optional udf fs/udf/udf_vnops.c optional udf fs/unionfs/union_subr.c optional unionfs fs/unionfs/union_vfsops.c optional unionfs fs/unionfs/union_vnops.c optional unionfs fs/tmpfs/tmpfs_vnops.c optional tmpfs fs/tmpfs/tmpfs_fifoops.c optional tmpfs fs/tmpfs/tmpfs_vfsops.c optional tmpfs fs/tmpfs/tmpfs_subr.c optional tmpfs gdb/gdb_cons.c optional gdb gdb/gdb_main.c optional gdb gdb/gdb_packet.c optional gdb geom/bde/g_bde.c optional geom_bde geom/bde/g_bde_crypt.c optional geom_bde geom/bde/g_bde_lock.c optional geom_bde geom/bde/g_bde_work.c optional geom_bde geom/cache/g_cache.c optional geom_cache geom/concat/g_concat.c optional geom_concat geom/eli/g_eli.c optional geom_eli geom/eli/g_eli_crypto.c optional geom_eli geom/eli/g_eli_ctl.c optional geom_eli geom/eli/g_eli_hmac.c optional geom_eli geom/eli/g_eli_integrity.c optional geom_eli geom/eli/g_eli_key.c optional geom_eli geom/eli/g_eli_key_cache.c optional geom_eli geom/eli/g_eli_privacy.c optional geom_eli geom/eli/pkcs5v2.c optional geom_eli geom/gate/g_gate.c optional geom_gate geom/geom_aes.c optional geom_aes geom/geom_bsd.c optional geom_bsd geom/geom_bsd_enc.c optional geom_bsd | geom_part_bsd geom/geom_ccd.c optional ccd | geom_ccd geom/geom_ctl.c standard geom/geom_dev.c standard geom/geom_disk.c standard geom/geom_dump.c standard geom/geom_event.c standard geom/geom_fox.c optional geom_fox geom/geom_flashmap.c optional fdt cfi | fdt nand | fdt mx25l | mmcsd geom/geom_io.c standard geom/geom_kern.c standard geom/geom_map.c optional geom_map geom/geom_mbr.c optional geom_mbr geom/geom_mbr_enc.c optional geom_mbr geom/geom_redboot.c optional geom_redboot geom/geom_slice.c standard geom/geom_subr.c standard geom/geom_sunlabel.c optional geom_sunlabel geom/geom_sunlabel_enc.c optional geom_sunlabel geom/geom_vfs.c standard geom/geom_vol_ffs.c optional geom_vol geom/journal/g_journal.c optional geom_journal geom/journal/g_journal_ufs.c optional geom_journal geom/label/g_label.c optional geom_label | geom_label_gpt geom/label/g_label_ext2fs.c optional geom_label geom/label/g_label_iso9660.c optional geom_label geom/label/g_label_msdosfs.c optional geom_label geom/label/g_label_ntfs.c optional geom_label geom/label/g_label_reiserfs.c optional geom_label geom/label/g_label_ufs.c optional geom_label geom/label/g_label_gpt.c optional geom_label | geom_label_gpt geom/label/g_label_disk_ident.c optional geom_label geom/linux_lvm/g_linux_lvm.c optional geom_linux_lvm geom/mirror/g_mirror.c optional geom_mirror geom/mirror/g_mirror_ctl.c optional geom_mirror geom/mountver/g_mountver.c optional geom_mountver geom/multipath/g_multipath.c optional geom_multipath geom/nop/g_nop.c optional geom_nop geom/part/g_part.c standard geom/part/g_part_if.m standard geom/part/g_part_apm.c optional geom_part_apm geom/part/g_part_bsd.c optional geom_part_bsd geom/part/g_part_bsd64.c optional geom_part_bsd64 geom/part/g_part_ebr.c optional geom_part_ebr geom/part/g_part_gpt.c optional geom_part_gpt geom/part/g_part_ldm.c optional geom_part_ldm geom/part/g_part_mbr.c optional geom_part_mbr geom/part/g_part_vtoc8.c optional geom_part_vtoc8 geom/raid/g_raid.c optional geom_raid geom/raid/g_raid_ctl.c optional geom_raid geom/raid/g_raid_md_if.m optional geom_raid geom/raid/g_raid_tr_if.m optional geom_raid geom/raid/md_ddf.c optional geom_raid geom/raid/md_intel.c optional geom_raid geom/raid/md_jmicron.c optional geom_raid geom/raid/md_nvidia.c optional geom_raid geom/raid/md_promise.c optional geom_raid geom/raid/md_sii.c optional geom_raid geom/raid/tr_concat.c optional geom_raid geom/raid/tr_raid0.c optional geom_raid geom/raid/tr_raid1.c optional geom_raid geom/raid/tr_raid1e.c optional geom_raid geom/raid/tr_raid5.c optional geom_raid geom/raid3/g_raid3.c optional geom_raid3 geom/raid3/g_raid3_ctl.c optional geom_raid3 geom/shsec/g_shsec.c optional geom_shsec geom/stripe/g_stripe.c optional geom_stripe contrib/xz-embedded/freebsd/xz_malloc.c \ optional xz_embedded | geom_uzip \ compile-with "${NORMAL_C} -I$S/contrib/xz-embedded/freebsd/ -I$S/contrib/xz-embedded/linux/lib/xz/ -I$S/contrib/xz-embedded/linux/include/linux/" contrib/xz-embedded/linux/lib/xz/xz_crc32.c \ optional xz_embedded | geom_uzip \ compile-with "${NORMAL_C} -I$S/contrib/xz-embedded/freebsd/ -I$S/contrib/xz-embedded/linux/lib/xz/ -I$S/contrib/xz-embedded/linux/include/linux/" contrib/xz-embedded/linux/lib/xz/xz_dec_bcj.c \ optional xz_embedded | geom_uzip \ compile-with "${NORMAL_C} -I$S/contrib/xz-embedded/freebsd/ -I$S/contrib/xz-embedded/linux/lib/xz/ -I$S/contrib/xz-embedded/linux/include/linux/" contrib/xz-embedded/linux/lib/xz/xz_dec_lzma2.c \ optional xz_embedded | geom_uzip \ compile-with "${NORMAL_C} -I$S/contrib/xz-embedded/freebsd/ -I$S/contrib/xz-embedded/linux/lib/xz/ -I$S/contrib/xz-embedded/linux/include/linux/" contrib/xz-embedded/linux/lib/xz/xz_dec_stream.c \ optional xz_embedded | geom_uzip \ compile-with "${NORMAL_C} -I$S/contrib/xz-embedded/freebsd/ -I$S/contrib/xz-embedded/linux/lib/xz/ -I$S/contrib/xz-embedded/linux/include/linux/" geom/uzip/g_uzip.c optional geom_uzip geom/uzip/g_uzip_lzma.c optional geom_uzip geom/uzip/g_uzip_wrkthr.c optional geom_uzip geom/uzip/g_uzip_zlib.c optional geom_uzip geom/vinum/geom_vinum.c optional geom_vinum geom/vinum/geom_vinum_create.c optional geom_vinum geom/vinum/geom_vinum_drive.c optional geom_vinum geom/vinum/geom_vinum_plex.c optional geom_vinum geom/vinum/geom_vinum_volume.c optional geom_vinum geom/vinum/geom_vinum_subr.c optional geom_vinum geom/vinum/geom_vinum_raid5.c optional geom_vinum geom/vinum/geom_vinum_share.c optional geom_vinum geom/vinum/geom_vinum_list.c optional geom_vinum geom/vinum/geom_vinum_rm.c optional geom_vinum geom/vinum/geom_vinum_init.c optional geom_vinum geom/vinum/geom_vinum_state.c optional geom_vinum geom/vinum/geom_vinum_rename.c optional geom_vinum geom/vinum/geom_vinum_move.c optional geom_vinum geom/vinum/geom_vinum_events.c optional geom_vinum geom/virstor/binstream.c optional geom_virstor geom/virstor/g_virstor.c optional geom_virstor geom/virstor/g_virstor_md.c optional geom_virstor geom/zero/g_zero.c optional geom_zero fs/ext2fs/ext2_acl.c optional ext2fs fs/ext2fs/ext2_alloc.c optional ext2fs fs/ext2fs/ext2_balloc.c optional ext2fs fs/ext2fs/ext2_bmap.c optional ext2fs fs/ext2fs/ext2_csum.c optional ext2fs fs/ext2fs/ext2_extattr.c optional ext2fs fs/ext2fs/ext2_extents.c optional ext2fs fs/ext2fs/ext2_inode.c optional ext2fs fs/ext2fs/ext2_inode_cnv.c optional ext2fs fs/ext2fs/ext2_hash.c optional ext2fs fs/ext2fs/ext2_htree.c optional ext2fs fs/ext2fs/ext2_lookup.c optional ext2fs fs/ext2fs/ext2_subr.c optional ext2fs fs/ext2fs/ext2_vfsops.c optional ext2fs fs/ext2fs/ext2_vnops.c optional ext2fs # isa/isa_if.m standard isa/isa_common.c optional isa isa/isahint.c optional isa isa/pnp.c optional isa isapnp isa/pnpparse.c optional isa isapnp fs/cd9660/cd9660_bmap.c optional cd9660 fs/cd9660/cd9660_lookup.c optional cd9660 fs/cd9660/cd9660_node.c optional cd9660 fs/cd9660/cd9660_rrip.c optional cd9660 fs/cd9660/cd9660_util.c optional cd9660 fs/cd9660/cd9660_vfsops.c optional cd9660 fs/cd9660/cd9660_vnops.c optional cd9660 fs/cd9660/cd9660_iconv.c optional cd9660_iconv kern/bus_if.m standard kern/clock_if.m standard kern/cpufreq_if.m standard kern/device_if.m standard kern/imgact_binmisc.c optional imagact_binmisc kern/imgact_elf.c standard kern/imgact_elf32.c optional compat_freebsd32 kern/imgact_shell.c standard kern/inflate.c optional gzip kern/init_main.c standard kern/init_sysent.c standard kern/ksched.c optional _kposix_priority_scheduling kern/kern_acct.c standard kern/kern_alq.c optional alq kern/kern_clock.c standard kern/kern_condvar.c standard kern/kern_conf.c standard kern/kern_cons.c standard kern/kern_cpu.c standard kern/kern_cpuset.c standard kern/kern_context.c standard kern/kern_descrip.c standard kern/kern_dtrace.c optional kdtrace_hooks kern/kern_dump.c standard kern/kern_environment.c standard kern/kern_et.c standard kern/kern_event.c standard kern/kern_exec.c standard kern/kern_exit.c standard kern/kern_fail.c standard kern/kern_ffclock.c standard kern/kern_fork.c standard kern/kern_hhook.c standard kern/kern_idle.c standard kern/kern_intr.c standard kern/kern_jail.c standard kern/kern_khelp.c standard kern/kern_kthread.c standard kern/kern_ktr.c optional ktr kern/kern_ktrace.c standard kern/kern_linker.c standard kern/kern_lock.c standard kern/kern_lockf.c standard kern/kern_lockstat.c optional kdtrace_hooks kern/kern_loginclass.c standard kern/kern_malloc.c standard kern/kern_mbuf.c standard kern/kern_mib.c standard kern/kern_module.c standard kern/kern_mtxpool.c standard kern/kern_mutex.c standard kern/kern_ntptime.c standard kern/kern_osd.c standard kern/kern_physio.c standard kern/kern_pmc.c standard kern/kern_poll.c optional device_polling kern/kern_priv.c standard kern/kern_proc.c standard kern/kern_procctl.c standard kern/kern_prot.c standard kern/kern_racct.c standard kern/kern_rangelock.c standard kern/kern_rctl.c standard kern/kern_resource.c standard kern/kern_rmlock.c standard kern/kern_rwlock.c standard kern/kern_sdt.c optional kdtrace_hooks kern/kern_sema.c standard kern/kern_sendfile.c standard kern/kern_sharedpage.c standard kern/kern_shutdown.c standard kern/kern_sig.c standard kern/kern_switch.c standard kern/kern_sx.c standard kern/kern_synch.c standard kern/kern_syscalls.c standard kern/kern_sysctl.c standard kern/kern_tc.c standard kern/kern_thr.c standard kern/kern_thread.c standard kern/kern_time.c standard kern/kern_timeout.c standard kern/kern_tslog.c optional tslog kern/kern_umtx.c standard kern/kern_uuid.c standard kern/kern_xxx.c standard kern/link_elf.c standard kern/linker_if.m standard kern/md4c.c optional netsmb kern/md5c.c standard kern/p1003_1b.c standard kern/posix4_mib.c standard kern/sched_4bsd.c optional sched_4bsd kern/sched_ule.c optional sched_ule kern/serdev_if.m standard kern/stack_protector.c standard \ compile-with "${NORMAL_C:N-fstack-protector*}" kern/subr_acl_nfs4.c optional ufs_acl | zfs kern/subr_acl_posix1e.c optional ufs_acl kern/subr_autoconf.c standard kern/subr_blist.c standard kern/subr_bus.c standard kern/subr_bus_dma.c standard kern/subr_bufring.c standard kern/subr_capability.c standard kern/subr_clock.c standard kern/subr_compressor.c standard kern/subr_counter.c standard kern/subr_devstat.c standard kern/subr_disk.c standard kern/subr_eventhandler.c standard kern/subr_fattime.c standard kern/subr_firmware.c optional firmware kern/subr_gtaskqueue.c standard kern/subr_hash.c standard kern/subr_hints.c standard kern/subr_kdb.c standard kern/subr_kobj.c standard kern/subr_lock.c standard kern/subr_log.c standard kern/subr_mchain.c optional libmchain kern/subr_module.c standard kern/subr_msgbuf.c standard kern/subr_param.c standard kern/subr_pcpu.c standard kern/subr_pctrie.c standard kern/subr_power.c standard kern/subr_prf.c standard kern/subr_prof.c standard kern/subr_rman.c standard kern/subr_rtc.c standard kern/subr_sbuf.c standard kern/subr_scanf.c standard kern/subr_sglist.c standard kern/subr_sleepqueue.c standard kern/subr_smp.c standard kern/subr_stack.c optional ddb | stack | ktr kern/subr_taskqueue.c standard kern/subr_terminal.c optional vt kern/subr_trap.c standard kern/subr_turnstile.c standard kern/subr_uio.c standard kern/subr_unit.c standard kern/subr_vmem.c standard kern/subr_witness.c optional witness kern/sys_capability.c standard kern/sys_generic.c standard kern/sys_pipe.c standard kern/sys_procdesc.c standard kern/sys_process.c standard kern/sys_socket.c standard kern/syscalls.c standard kern/sysv_ipc.c standard kern/sysv_msg.c optional sysvmsg kern/sysv_sem.c optional sysvsem kern/sysv_shm.c optional sysvshm kern/tty.c standard kern/tty_compat.c optional compat_43tty kern/tty_info.c standard kern/tty_inq.c standard kern/tty_outq.c standard kern/tty_pts.c standard kern/tty_tty.c standard kern/tty_ttydisc.c standard kern/uipc_accf.c standard kern/uipc_debug.c optional ddb kern/uipc_domain.c standard kern/uipc_mbuf.c standard kern/uipc_mbuf2.c standard kern/uipc_mbufhash.c standard kern/uipc_mqueue.c optional p1003_1b_mqueue kern/uipc_sem.c optional p1003_1b_semaphores kern/uipc_shm.c standard kern/uipc_sockbuf.c standard kern/uipc_socket.c standard kern/uipc_syscalls.c standard kern/uipc_usrreq.c standard kern/vfs_acl.c standard kern/vfs_aio.c standard kern/vfs_bio.c standard kern/vfs_cache.c standard kern/vfs_cluster.c standard kern/vfs_default.c standard kern/vfs_export.c standard kern/vfs_extattr.c standard kern/vfs_hash.c standard kern/vfs_init.c standard kern/vfs_lookup.c standard kern/vfs_mount.c standard kern/vfs_mountroot.c standard kern/vfs_subr.c standard kern/vfs_syscalls.c standard kern/vfs_vnops.c standard # # Kernel GSS-API # gssd.h optional kgssapi \ dependency "$S/kgssapi/gssd.x" \ compile-with "RPCGEN_CPP='${CPP}' rpcgen -hM $S/kgssapi/gssd.x | grep -v pthread.h > gssd.h" \ no-obj no-implicit-rule before-depend local \ clean "gssd.h" gssd_xdr.c optional kgssapi \ dependency "$S/kgssapi/gssd.x gssd.h" \ compile-with "RPCGEN_CPP='${CPP}' rpcgen -c $S/kgssapi/gssd.x -o gssd_xdr.c" \ no-implicit-rule before-depend local \ clean "gssd_xdr.c" gssd_clnt.c optional kgssapi \ dependency "$S/kgssapi/gssd.x gssd.h" \ compile-with "RPCGEN_CPP='${CPP}' rpcgen -lM $S/kgssapi/gssd.x | grep -v string.h > gssd_clnt.c" \ no-implicit-rule before-depend local \ clean "gssd_clnt.c" kgssapi/gss_accept_sec_context.c optional kgssapi kgssapi/gss_add_oid_set_member.c optional kgssapi kgssapi/gss_acquire_cred.c optional kgssapi kgssapi/gss_canonicalize_name.c optional kgssapi kgssapi/gss_create_empty_oid_set.c optional kgssapi kgssapi/gss_delete_sec_context.c optional kgssapi kgssapi/gss_display_status.c optional kgssapi kgssapi/gss_export_name.c optional kgssapi kgssapi/gss_get_mic.c optional kgssapi kgssapi/gss_init_sec_context.c optional kgssapi kgssapi/gss_impl.c optional kgssapi kgssapi/gss_import_name.c optional kgssapi kgssapi/gss_names.c optional kgssapi kgssapi/gss_pname_to_uid.c optional kgssapi kgssapi/gss_release_buffer.c optional kgssapi kgssapi/gss_release_cred.c optional kgssapi kgssapi/gss_release_name.c optional kgssapi kgssapi/gss_release_oid_set.c optional kgssapi kgssapi/gss_set_cred_option.c optional kgssapi kgssapi/gss_test_oid_set_member.c optional kgssapi kgssapi/gss_unwrap.c optional kgssapi kgssapi/gss_verify_mic.c optional kgssapi kgssapi/gss_wrap.c optional kgssapi kgssapi/gss_wrap_size_limit.c optional kgssapi kgssapi/gssd_prot.c optional kgssapi kgssapi/krb5/krb5_mech.c optional kgssapi kgssapi/krb5/kcrypto.c optional kgssapi kgssapi/krb5/kcrypto_aes.c optional kgssapi kgssapi/krb5/kcrypto_arcfour.c optional kgssapi kgssapi/krb5/kcrypto_des.c optional kgssapi kgssapi/krb5/kcrypto_des3.c optional kgssapi kgssapi/kgss_if.m optional kgssapi kgssapi/gsstest.c optional kgssapi_debug # These files in libkern/ are those needed by all architectures. Some # of the files in libkern/ are only needed on some architectures, e.g., # libkern/divdi3.c is needed by i386 but not alpha. Also, some of these # routines may be optimized for a particular platform. In either case, # the file should be moved to conf/files. from here. # libkern/arc4random.c standard crypto/chacha20/chacha.c standard libkern/asprintf.c standard libkern/bcd.c standard libkern/bsearch.c standard libkern/crc32.c standard libkern/explicit_bzero.c standard libkern/fnmatch.c standard libkern/iconv.c optional libiconv libkern/iconv_converter_if.m optional libiconv libkern/iconv_ucs.c optional libiconv libkern/iconv_xlat.c optional libiconv libkern/iconv_xlat16.c optional libiconv libkern/inet_aton.c standard libkern/inet_ntoa.c standard libkern/inet_ntop.c standard libkern/inet_pton.c standard libkern/jenkins_hash.c standard libkern/murmur3_32.c standard libkern/mcount.c optional profiling-routine libkern/memcchr.c standard libkern/memchr.c standard libkern/memcmp.c standard libkern/memmem.c optional gdb libkern/qsort.c standard libkern/qsort_r.c standard libkern/random.c standard libkern/scanc.c standard libkern/strcasecmp.c standard libkern/strcat.c standard libkern/strchr.c standard libkern/strcmp.c standard libkern/strcpy.c standard libkern/strcspn.c standard libkern/strdup.c standard libkern/strndup.c standard libkern/strlcat.c standard libkern/strlcpy.c standard libkern/strlen.c standard libkern/strncat.c standard libkern/strncmp.c standard libkern/strncpy.c standard libkern/strnlen.c standard libkern/strrchr.c standard libkern/strsep.c standard libkern/strspn.c standard libkern/strstr.c standard libkern/strtol.c standard libkern/strtoq.c standard libkern/strtoul.c standard libkern/strtouq.c standard libkern/strvalid.c standard libkern/timingsafe_bcmp.c standard libkern/zlib.c optional crypto | geom_uzip | ipsec | \ ipsec_support | mxge | netgraph_deflate | ddb_ctf | gzio net/altq/altq_cbq.c optional altq net/altq/altq_cdnr.c optional altq net/altq/altq_codel.c optional altq net/altq/altq_hfsc.c optional altq net/altq/altq_fairq.c optional altq net/altq/altq_priq.c optional altq net/altq/altq_red.c optional altq net/altq/altq_rio.c optional altq net/altq/altq_rmclass.c optional altq net/altq/altq_subr.c optional altq net/bpf.c standard net/bpf_buffer.c optional bpf net/bpf_jitter.c optional bpf_jitter net/bpf_filter.c optional bpf | netgraph_bpf net/bpf_zerocopy.c optional bpf net/bridgestp.c optional bridge | if_bridge net/flowtable.c optional flowtable inet | flowtable inet6 net/ieee8023ad_lacp.c optional lagg net/if.c standard net/if_arcsubr.c optional arcnet net/if_bridge.c optional bridge inet | if_bridge inet net/if_clone.c standard net/if_dead.c standard net/if_debug.c optional ddb net/if_disc.c optional disc net/if_edsc.c optional edsc net/if_enc.c optional enc inet | enc inet6 net/if_epair.c optional epair net/if_ethersubr.c optional ether net/if_fddisubr.c optional fddi net/if_fwsubr.c optional fwip net/if_gif.c optional gif inet | gif inet6 | \ netgraph_gif inet | netgraph_gif inet6 net/if_gre.c optional gre inet | gre inet6 net/if_ipsec.c optional inet ipsec | inet6 ipsec net/if_iso88025subr.c optional token net/if_lagg.c optional lagg net/if_loop.c optional loop net/if_llatbl.c standard net/if_me.c optional me inet net/if_media.c standard net/if_mib.c standard net/if_spppfr.c optional sppp | netgraph_sppp net/if_spppsubr.c optional sppp | netgraph_sppp net/if_stf.c optional stf inet inet6 net/if_tun.c optional tun net/if_tap.c optional tap net/if_vlan.c optional vlan net/if_vxlan.c optional vxlan inet | vxlan inet6 net/ifdi_if.m optional ether pci net/iflib.c optional ether pci net/mp_ring.c optional ether net/mppcc.c optional netgraph_mppc_compression net/mppcd.c optional netgraph_mppc_compression net/netisr.c standard net/pfil.c optional ether | inet net/radix.c standard net/radix_mpath.c standard net/raw_cb.c standard net/raw_usrreq.c standard net/route.c standard net/rss_config.c optional inet rss | inet6 rss net/rtsock.c standard net/slcompress.c optional netgraph_vjc | sppp | \ netgraph_sppp net/toeplitz.c optional inet rss | inet6 rss net/vnet.c optional vimage net80211/ieee80211.c optional wlan net80211/ieee80211_acl.c optional wlan wlan_acl net80211/ieee80211_action.c optional wlan net80211/ieee80211_adhoc.c optional wlan \ compile-with "${NORMAL_C} -Wno-unused-function" net80211/ieee80211_ageq.c optional wlan net80211/ieee80211_amrr.c optional wlan | wlan_amrr net80211/ieee80211_crypto.c optional wlan \ compile-with "${NORMAL_C} -Wno-unused-function" net80211/ieee80211_crypto_ccmp.c optional wlan wlan_ccmp net80211/ieee80211_crypto_none.c optional wlan net80211/ieee80211_crypto_tkip.c optional wlan wlan_tkip net80211/ieee80211_crypto_wep.c optional wlan wlan_wep net80211/ieee80211_ddb.c optional wlan ddb net80211/ieee80211_dfs.c optional wlan net80211/ieee80211_freebsd.c optional wlan net80211/ieee80211_hostap.c optional wlan \ compile-with "${NORMAL_C} -Wno-unused-function" net80211/ieee80211_ht.c optional wlan net80211/ieee80211_hwmp.c optional wlan ieee80211_support_mesh net80211/ieee80211_input.c optional wlan net80211/ieee80211_ioctl.c optional wlan net80211/ieee80211_mesh.c optional wlan ieee80211_support_mesh \ compile-with "${NORMAL_C} -Wno-unused-function" net80211/ieee80211_monitor.c optional wlan net80211/ieee80211_node.c optional wlan net80211/ieee80211_output.c optional wlan net80211/ieee80211_phy.c optional wlan net80211/ieee80211_power.c optional wlan net80211/ieee80211_proto.c optional wlan net80211/ieee80211_radiotap.c optional wlan net80211/ieee80211_ratectl.c optional wlan net80211/ieee80211_ratectl_none.c optional wlan net80211/ieee80211_regdomain.c optional wlan net80211/ieee80211_rssadapt.c optional wlan wlan_rssadapt net80211/ieee80211_scan.c optional wlan net80211/ieee80211_scan_sta.c optional wlan net80211/ieee80211_sta.c optional wlan \ compile-with "${NORMAL_C} -Wno-unused-function" net80211/ieee80211_superg.c optional wlan ieee80211_support_superg net80211/ieee80211_scan_sw.c optional wlan net80211/ieee80211_tdma.c optional wlan ieee80211_support_tdma net80211/ieee80211_vht.c optional wlan net80211/ieee80211_wds.c optional wlan net80211/ieee80211_xauth.c optional wlan wlan_xauth net80211/ieee80211_alq.c optional wlan ieee80211_alq netgraph/atm/ccatm/ng_ccatm.c optional ngatm_ccatm \ compile-with "${NORMAL_C} -I$S/contrib/ngatm" netgraph/atm/ngatmbase.c optional ngatm_atmbase \ compile-with "${NORMAL_C} -I$S/contrib/ngatm" netgraph/atm/sscfu/ng_sscfu.c optional ngatm_sscfu \ compile-with "${NORMAL_C} -I$S/contrib/ngatm" netgraph/atm/sscop/ng_sscop.c optional ngatm_sscop \ compile-with "${NORMAL_C} -I$S/contrib/ngatm" netgraph/atm/uni/ng_uni.c optional ngatm_uni \ compile-with "${NORMAL_C} -I$S/contrib/ngatm" netgraph/bluetooth/common/ng_bluetooth.c optional netgraph_bluetooth netgraph/bluetooth/drivers/bt3c/ng_bt3c_pccard.c optional netgraph_bluetooth_bt3c netgraph/bluetooth/drivers/h4/ng_h4.c optional netgraph_bluetooth_h4 netgraph/bluetooth/drivers/ubt/ng_ubt.c optional netgraph_bluetooth_ubt usb netgraph/bluetooth/drivers/ubtbcmfw/ubtbcmfw.c optional netgraph_bluetooth_ubtbcmfw usb netgraph/bluetooth/hci/ng_hci_cmds.c optional netgraph_bluetooth_hci netgraph/bluetooth/hci/ng_hci_evnt.c optional netgraph_bluetooth_hci netgraph/bluetooth/hci/ng_hci_main.c optional netgraph_bluetooth_hci netgraph/bluetooth/hci/ng_hci_misc.c optional netgraph_bluetooth_hci netgraph/bluetooth/hci/ng_hci_ulpi.c optional netgraph_bluetooth_hci netgraph/bluetooth/l2cap/ng_l2cap_cmds.c optional netgraph_bluetooth_l2cap netgraph/bluetooth/l2cap/ng_l2cap_evnt.c optional netgraph_bluetooth_l2cap netgraph/bluetooth/l2cap/ng_l2cap_llpi.c optional netgraph_bluetooth_l2cap netgraph/bluetooth/l2cap/ng_l2cap_main.c optional netgraph_bluetooth_l2cap netgraph/bluetooth/l2cap/ng_l2cap_misc.c optional netgraph_bluetooth_l2cap netgraph/bluetooth/l2cap/ng_l2cap_ulpi.c optional netgraph_bluetooth_l2cap netgraph/bluetooth/socket/ng_btsocket.c optional netgraph_bluetooth_socket netgraph/bluetooth/socket/ng_btsocket_hci_raw.c optional netgraph_bluetooth_socket netgraph/bluetooth/socket/ng_btsocket_l2cap.c optional netgraph_bluetooth_socket netgraph/bluetooth/socket/ng_btsocket_l2cap_raw.c optional netgraph_bluetooth_socket netgraph/bluetooth/socket/ng_btsocket_rfcomm.c optional netgraph_bluetooth_socket netgraph/bluetooth/socket/ng_btsocket_sco.c optional netgraph_bluetooth_socket netgraph/netflow/netflow.c optional netgraph_netflow netgraph/netflow/netflow_v9.c optional netgraph_netflow netgraph/netflow/ng_netflow.c optional netgraph_netflow netgraph/ng_UI.c optional netgraph_UI netgraph/ng_async.c optional netgraph_async netgraph/ng_atmllc.c optional netgraph_atmllc netgraph/ng_base.c optional netgraph netgraph/ng_bpf.c optional netgraph_bpf netgraph/ng_bridge.c optional netgraph_bridge netgraph/ng_car.c optional netgraph_car netgraph/ng_cisco.c optional netgraph_cisco netgraph/ng_deflate.c optional netgraph_deflate netgraph/ng_device.c optional netgraph_device netgraph/ng_echo.c optional netgraph_echo netgraph/ng_eiface.c optional netgraph_eiface netgraph/ng_ether.c optional netgraph_ether netgraph/ng_ether_echo.c optional netgraph_ether_echo netgraph/ng_frame_relay.c optional netgraph_frame_relay netgraph/ng_gif.c optional netgraph_gif inet6 | netgraph_gif inet netgraph/ng_gif_demux.c optional netgraph_gif_demux netgraph/ng_hole.c optional netgraph_hole netgraph/ng_iface.c optional netgraph_iface netgraph/ng_ip_input.c optional netgraph_ip_input netgraph/ng_ipfw.c optional netgraph_ipfw inet ipfirewall netgraph/ng_ksocket.c optional netgraph_ksocket netgraph/ng_l2tp.c optional netgraph_l2tp netgraph/ng_lmi.c optional netgraph_lmi netgraph/ng_mppc.c optional netgraph_mppc_compression | \ netgraph_mppc_encryption netgraph/ng_nat.c optional netgraph_nat inet libalias netgraph/ng_one2many.c optional netgraph_one2many netgraph/ng_parse.c optional netgraph netgraph/ng_patch.c optional netgraph_patch netgraph/ng_pipe.c optional netgraph_pipe netgraph/ng_ppp.c optional netgraph_ppp netgraph/ng_pppoe.c optional netgraph_pppoe netgraph/ng_pptpgre.c optional netgraph_pptpgre netgraph/ng_pred1.c optional netgraph_pred1 netgraph/ng_rfc1490.c optional netgraph_rfc1490 netgraph/ng_socket.c optional netgraph_socket netgraph/ng_split.c optional netgraph_split netgraph/ng_sppp.c optional netgraph_sppp netgraph/ng_tag.c optional netgraph_tag netgraph/ng_tcpmss.c optional netgraph_tcpmss netgraph/ng_tee.c optional netgraph_tee netgraph/ng_tty.c optional netgraph_tty netgraph/ng_vjc.c optional netgraph_vjc netgraph/ng_vlan.c optional netgraph_vlan netinet/accf_data.c optional accept_filter_data inet netinet/accf_dns.c optional accept_filter_dns inet netinet/accf_http.c optional accept_filter_http inet netinet/if_ether.c optional inet ether netinet/igmp.c optional inet netinet/in.c optional inet netinet/in_debug.c optional inet ddb netinet/in_kdtrace.c optional inet | inet6 netinet/ip_carp.c optional inet carp | inet6 carp netinet/in_fib.c optional inet netinet/in_gif.c optional gif inet | netgraph_gif inet netinet/ip_gre.c optional gre inet netinet/ip_id.c optional inet netinet/in_jail.c optional inet netinet/in_mcast.c optional inet netinet/in_pcb.c optional inet | inet6 netinet/in_pcbgroup.c optional inet pcbgroup | inet6 pcbgroup netinet/in_prot.c optional inet | inet6 netinet/in_proto.c optional inet | inet6 netinet/in_rmx.c optional inet netinet/in_rss.c optional inet rss netinet/ip_divert.c optional inet ipdivert ipfirewall netinet/ip_ecn.c optional inet | inet6 netinet/ip_encap.c optional inet | inet6 netinet/ip_fastfwd.c optional inet netinet/ip_icmp.c optional inet | inet6 netinet/ip_input.c optional inet netinet/ip_mroute.c optional mrouting inet netinet/ip_options.c optional inet netinet/ip_output.c optional inet netinet/ip_reass.c optional inet netinet/raw_ip.c optional inet | inet6 netinet/cc/cc.c optional inet | inet6 netinet/cc/cc_newreno.c optional inet | inet6 netinet/sctp_asconf.c optional inet sctp | inet6 sctp netinet/sctp_auth.c optional inet sctp | inet6 sctp netinet/sctp_bsd_addr.c optional inet sctp | inet6 sctp netinet/sctp_cc_functions.c optional inet sctp | inet6 sctp netinet/sctp_crc32.c optional inet | inet6 netinet/sctp_indata.c optional inet sctp | inet6 sctp netinet/sctp_input.c optional inet sctp | inet6 sctp netinet/sctp_output.c optional inet sctp | inet6 sctp netinet/sctp_pcb.c optional inet sctp | inet6 sctp netinet/sctp_peeloff.c optional inet sctp | inet6 sctp netinet/sctp_ss_functions.c optional inet sctp | inet6 sctp netinet/sctp_syscalls.c optional inet sctp | inet6 sctp netinet/sctp_sysctl.c optional inet sctp | inet6 sctp netinet/sctp_timer.c optional inet sctp | inet6 sctp netinet/sctp_usrreq.c optional inet sctp | inet6 sctp netinet/sctputil.c optional inet sctp | inet6 sctp netinet/siftr.c optional inet siftr alq | inet6 siftr alq netinet/tcp_debug.c optional tcpdebug netinet/tcp_fastopen.c optional inet tcp_rfc7413 | inet6 tcp_rfc7413 netinet/tcp_hostcache.c optional inet | inet6 netinet/tcp_input.c optional inet | inet6 netinet/tcp_lro.c optional inet | inet6 netinet/tcp_output.c optional inet | inet6 netinet/tcp_offload.c optional tcp_offload inet | tcp_offload inet6 netinet/tcp_pcap.c optional inet tcppcap | inet6 tcppcap netinet/tcp_reass.c optional inet | inet6 netinet/tcp_sack.c optional inet | inet6 netinet/tcp_subr.c optional inet | inet6 netinet/tcp_syncache.c optional inet | inet6 netinet/tcp_timer.c optional inet | inet6 netinet/tcp_timewait.c optional inet | inet6 netinet/tcp_usrreq.c optional inet | inet6 netinet/udp_usrreq.c optional inet | inet6 netinet/libalias/alias.c optional libalias inet | netgraph_nat inet netinet/libalias/alias_db.c optional libalias inet | netgraph_nat inet netinet/libalias/alias_mod.c optional libalias | netgraph_nat netinet/libalias/alias_proxy.c optional libalias inet | netgraph_nat inet netinet/libalias/alias_util.c optional libalias inet | netgraph_nat inet netinet/libalias/alias_sctp.c optional libalias inet | netgraph_nat inet netinet6/dest6.c optional inet6 netinet6/frag6.c optional inet6 netinet6/icmp6.c optional inet6 netinet6/in6.c optional inet6 netinet6/in6_cksum.c optional inet6 netinet6/in6_fib.c optional inet6 netinet6/in6_gif.c optional gif inet6 | netgraph_gif inet6 netinet6/in6_ifattach.c optional inet6 netinet6/in6_jail.c optional inet6 netinet6/in6_mcast.c optional inet6 netinet6/in6_pcb.c optional inet6 netinet6/in6_pcbgroup.c optional inet6 pcbgroup netinet6/in6_proto.c optional inet6 netinet6/in6_rmx.c optional inet6 netinet6/in6_rss.c optional inet6 rss netinet6/in6_src.c optional inet6 netinet6/ip6_fastfwd.c optional inet6 netinet6/ip6_forward.c optional inet6 netinet6/ip6_gre.c optional gre inet6 netinet6/ip6_id.c optional inet6 netinet6/ip6_input.c optional inet6 netinet6/ip6_mroute.c optional mrouting inet6 netinet6/ip6_output.c optional inet6 netinet6/mld6.c optional inet6 netinet6/nd6.c optional inet6 netinet6/nd6_nbr.c optional inet6 netinet6/nd6_rtr.c optional inet6 netinet6/raw_ip6.c optional inet6 netinet6/route6.c optional inet6 netinet6/scope6.c optional inet6 netinet6/sctp6_usrreq.c optional inet6 sctp netinet6/udp6_usrreq.c optional inet6 netipsec/ipsec.c optional ipsec inet | ipsec inet6 netipsec/ipsec_input.c optional ipsec inet | ipsec inet6 netipsec/ipsec_mbuf.c optional ipsec inet | ipsec inet6 netipsec/ipsec_mod.c optional ipsec inet | ipsec inet6 netipsec/ipsec_output.c optional ipsec inet | ipsec inet6 netipsec/ipsec_pcb.c optional ipsec inet | ipsec inet6 | \ ipsec_support inet | ipsec_support inet6 netipsec/key.c optional ipsec inet | ipsec inet6 | \ ipsec_support inet | ipsec_support inet6 netipsec/key_debug.c optional ipsec inet | ipsec inet6 | \ ipsec_support inet | ipsec_support inet6 netipsec/keysock.c optional ipsec inet | ipsec inet6 | \ ipsec_support inet | ipsec_support inet6 netipsec/subr_ipsec.c optional ipsec inet | ipsec inet6 | \ ipsec_support inet | ipsec_support inet6 netipsec/udpencap.c optional ipsec inet netipsec/xform_ah.c optional ipsec inet | ipsec inet6 netipsec/xform_esp.c optional ipsec inet | ipsec inet6 netipsec/xform_ipcomp.c optional ipsec inet | ipsec inet6 netipsec/xform_tcp.c optional ipsec inet tcp_signature | \ ipsec inet6 tcp_signature | ipsec_support inet tcp_signature | \ ipsec_support inet6 tcp_signature netpfil/ipfw/dn_aqm_codel.c optional inet dummynet netpfil/ipfw/dn_aqm_pie.c optional inet dummynet netpfil/ipfw/dn_heap.c optional inet dummynet netpfil/ipfw/dn_sched_fifo.c optional inet dummynet netpfil/ipfw/dn_sched_fq_codel.c optional inet dummynet netpfil/ipfw/dn_sched_fq_pie.c optional inet dummynet netpfil/ipfw/dn_sched_prio.c optional inet dummynet netpfil/ipfw/dn_sched_qfq.c optional inet dummynet netpfil/ipfw/dn_sched_rr.c optional inet dummynet netpfil/ipfw/dn_sched_wf2q.c optional inet dummynet netpfil/ipfw/ip_dummynet.c optional inet dummynet netpfil/ipfw/ip_dn_io.c optional inet dummynet netpfil/ipfw/ip_dn_glue.c optional inet dummynet netpfil/ipfw/ip_fw2.c optional inet ipfirewall netpfil/ipfw/ip_fw_bpf.c optional inet ipfirewall netpfil/ipfw/ip_fw_dynamic.c optional inet ipfirewall netpfil/ipfw/ip_fw_eaction.c optional inet ipfirewall netpfil/ipfw/ip_fw_log.c optional inet ipfirewall netpfil/ipfw/ip_fw_pfil.c optional inet ipfirewall netpfil/ipfw/ip_fw_sockopt.c optional inet ipfirewall netpfil/ipfw/ip_fw_table.c optional inet ipfirewall netpfil/ipfw/ip_fw_table_algo.c optional inet ipfirewall netpfil/ipfw/ip_fw_table_value.c optional inet ipfirewall netpfil/ipfw/ip_fw_iface.c optional inet ipfirewall netpfil/ipfw/ip_fw_nat.c optional inet ipfirewall_nat netpfil/ipfw/nat64/ip_fw_nat64.c optional inet inet6 ipfirewall \ ipfirewall_nat64 netpfil/ipfw/nat64/nat64lsn.c optional inet inet6 ipfirewall \ ipfirewall_nat64 netpfil/ipfw/nat64/nat64lsn_control.c optional inet inet6 ipfirewall \ ipfirewall_nat64 netpfil/ipfw/nat64/nat64stl.c optional inet inet6 ipfirewall \ ipfirewall_nat64 netpfil/ipfw/nat64/nat64stl_control.c optional inet inet6 ipfirewall \ ipfirewall_nat64 netpfil/ipfw/nat64/nat64_translate.c optional inet inet6 ipfirewall \ ipfirewall_nat64 netpfil/ipfw/nptv6/ip_fw_nptv6.c optional inet inet6 ipfirewall \ ipfirewall_nptv6 netpfil/ipfw/nptv6/nptv6.c optional inet inet6 ipfirewall \ ipfirewall_nptv6 netpfil/ipfw/pmod/ip_fw_pmod.c optional inet ipfirewall_pmod netpfil/ipfw/pmod/tcpmod.c optional inet ipfirewall_pmod netpfil/pf/if_pflog.c optional pflog pf inet netpfil/pf/if_pfsync.c optional pfsync pf inet netpfil/pf/pf.c optional pf inet netpfil/pf/pf_if.c optional pf inet netpfil/pf/pf_ioctl.c optional pf inet netpfil/pf/pf_lb.c optional pf inet netpfil/pf/pf_norm.c optional pf inet netpfil/pf/pf_osfp.c optional pf inet netpfil/pf/pf_ruleset.c optional pf inet netpfil/pf/pf_table.c optional pf inet netpfil/pf/in4_cksum.c optional pf inet netsmb/smb_conn.c optional netsmb netsmb/smb_crypt.c optional netsmb netsmb/smb_dev.c optional netsmb netsmb/smb_iod.c optional netsmb netsmb/smb_rq.c optional netsmb netsmb/smb_smb.c optional netsmb netsmb/smb_subr.c optional netsmb netsmb/smb_trantcp.c optional netsmb netsmb/smb_usr.c optional netsmb nfs/bootp_subr.c optional bootp nfscl nfs/krpc_subr.c optional bootp nfscl nfs/nfs_diskless.c optional nfscl nfs_root nfs/nfs_fha.c optional nfsd nfs/nfs_lock.c optional nfscl | nfslockd | nfsd nfs/nfs_nfssvc.c optional nfscl | nfsd nlm/nlm_advlock.c optional nfslockd | nfsd nlm/nlm_prot_clnt.c optional nfslockd | nfsd nlm/nlm_prot_impl.c optional nfslockd | nfsd nlm/nlm_prot_server.c optional nfslockd | nfsd nlm/nlm_prot_svc.c optional nfslockd | nfsd nlm/nlm_prot_xdr.c optional nfslockd | nfsd nlm/sm_inter_xdr.c optional nfslockd | nfsd # Linux Kernel Programming Interface compat/linuxkpi/common/src/linux_kmod.c optional compat_linuxkpi \ compile-with "${LINUXKPI_C}" compat/linuxkpi/common/src/linux_compat.c optional compat_linuxkpi \ compile-with "${LINUXKPI_C}" compat/linuxkpi/common/src/linux_current.c optional compat_linuxkpi \ compile-with "${LINUXKPI_C}" compat/linuxkpi/common/src/linux_hrtimer.c optional compat_linuxkpi \ compile-with "${LINUXKPI_C}" compat/linuxkpi/common/src/linux_kthread.c optional compat_linuxkpi \ compile-with "${LINUXKPI_C}" compat/linuxkpi/common/src/linux_lock.c optional compat_linuxkpi \ compile-with "${LINUXKPI_C}" compat/linuxkpi/common/src/linux_page.c optional compat_linuxkpi \ compile-with "${LINUXKPI_C}" compat/linuxkpi/common/src/linux_pci.c optional compat_linuxkpi pci \ compile-with "${LINUXKPI_C}" compat/linuxkpi/common/src/linux_tasklet.c optional compat_linuxkpi \ compile-with "${LINUXKPI_C}" compat/linuxkpi/common/src/linux_idr.c optional compat_linuxkpi \ compile-with "${LINUXKPI_C}" compat/linuxkpi/common/src/linux_radix.c optional compat_linuxkpi \ compile-with "${LINUXKPI_C}" compat/linuxkpi/common/src/linux_rcu.c optional compat_linuxkpi \ compile-with "${LINUXKPI_C} -I$S/contrib/ck/include" compat/linuxkpi/common/src/linux_schedule.c optional compat_linuxkpi \ compile-with "${LINUXKPI_C}" compat/linuxkpi/common/src/linux_slab.c optional compat_linuxkpi \ compile-with "${LINUXKPI_C}" compat/linuxkpi/common/src/linux_usb.c optional compat_linuxkpi usb \ compile-with "${LINUXKPI_C}" compat/linuxkpi/common/src/linux_work.c optional compat_linuxkpi \ compile-with "${LINUXKPI_C}" # OpenFabrics Enterprise Distribution (Infiniband) ofed/drivers/infiniband/core/ib_addr.c optional ofed \ compile-with "${OFED_C}" ofed/drivers/infiniband/core/ib_agent.c optional ofed \ compile-with "${OFED_C}" ofed/drivers/infiniband/core/ib_cache.c optional ofed \ compile-with "${OFED_C}" ofed/drivers/infiniband/core/ib_cm.c optional ofed \ compile-with "${OFED_C}" ofed/drivers/infiniband/core/ib_cma.c optional ofed \ compile-with "${OFED_C}" ofed/drivers/infiniband/core/ib_cq.c optional ofed \ compile-with "${OFED_C}" ofed/drivers/infiniband/core/ib_device.c optional ofed \ compile-with "${OFED_C}" ofed/drivers/infiniband/core/ib_fmr_pool.c optional ofed \ compile-with "${OFED_C}" ofed/drivers/infiniband/core/ib_iwcm.c optional ofed \ compile-with "${OFED_C}" ofed/drivers/infiniband/core/ib_iwpm_msg.c optional ofed \ compile-with "${OFED_C}" ofed/drivers/infiniband/core/ib_iwpm_util.c optional ofed \ compile-with "${OFED_C}" ofed/drivers/infiniband/core/ib_mad.c optional ofed \ compile-with "${OFED_C}" ofed/drivers/infiniband/core/ib_mad_rmpp.c optional ofed \ compile-with "${OFED_C}" ofed/drivers/infiniband/core/ib_multicast.c optional ofed \ compile-with "${OFED_C}" ofed/drivers/infiniband/core/ib_packer.c optional ofed \ compile-with "${OFED_C}" ofed/drivers/infiniband/core/ib_roce_gid_mgmt.c optional ofed \ compile-with "${OFED_C}" ofed/drivers/infiniband/core/ib_sa_query.c optional ofed \ compile-with "${OFED_C}" ofed/drivers/infiniband/core/ib_smi.c optional ofed \ compile-with "${OFED_C}" ofed/drivers/infiniband/core/ib_sysfs.c optional ofed \ compile-with "${OFED_C}" ofed/drivers/infiniband/core/ib_ucm.c optional ofed \ compile-with "${OFED_C}" ofed/drivers/infiniband/core/ib_ucma.c optional ofed \ compile-with "${OFED_C}" ofed/drivers/infiniband/core/ib_ud_header.c optional ofed \ compile-with "${OFED_C}" ofed/drivers/infiniband/core/ib_umem.c optional ofed \ compile-with "${OFED_C}" ofed/drivers/infiniband/core/ib_user_mad.c optional ofed \ compile-with "${OFED_C}" ofed/drivers/infiniband/core/ib_uverbs_cmd.c optional ofed \ compile-with "${OFED_C}" ofed/drivers/infiniband/core/ib_uverbs_main.c optional ofed \ compile-with "${OFED_C}" ofed/drivers/infiniband/core/ib_uverbs_marshall.c optional ofed \ compile-with "${OFED_C}" ofed/drivers/infiniband/core/ib_verbs.c optional ofed \ compile-with "${OFED_C}" ofed/drivers/infiniband/ulp/ipoib/ipoib_cm.c optional ipoib \ compile-with "${OFED_C} -I$S/ofed/drivers/infiniband/ulp/ipoib/" #ofed/drivers/infiniband/ulp/ipoib/ipoib_fs.c optional ipoib \ # compile-with "${OFED_C} -I$S/ofed/drivers/infiniband/ulp/ipoib/" ofed/drivers/infiniband/ulp/ipoib/ipoib_ib.c optional ipoib \ compile-with "${OFED_C} -I$S/ofed/drivers/infiniband/ulp/ipoib/" ofed/drivers/infiniband/ulp/ipoib/ipoib_main.c optional ipoib \ compile-with "${OFED_C} -I$S/ofed/drivers/infiniband/ulp/ipoib/" ofed/drivers/infiniband/ulp/ipoib/ipoib_multicast.c optional ipoib \ compile-with "${OFED_C} -I$S/ofed/drivers/infiniband/ulp/ipoib/" ofed/drivers/infiniband/ulp/ipoib/ipoib_verbs.c optional ipoib \ compile-with "${OFED_C} -I$S/ofed/drivers/infiniband/ulp/ipoib/" #ofed/drivers/infiniband/ulp/ipoib/ipoib_vlan.c optional ipoib \ # compile-with "${OFED_C} -I$S/ofed/drivers/infiniband/ulp/ipoib/" ofed/drivers/infiniband/ulp/sdp/sdp_bcopy.c optional sdp inet \ compile-with "${OFED_C} -I$S/ofed/drivers/infiniband/ulp/sdp/" ofed/drivers/infiniband/ulp/sdp/sdp_main.c optional sdp inet \ compile-with "${OFED_C} -I$S/ofed/drivers/infiniband/ulp/sdp/" ofed/drivers/infiniband/ulp/sdp/sdp_rx.c optional sdp inet \ compile-with "${OFED_C} -I$S/ofed/drivers/infiniband/ulp/sdp/" ofed/drivers/infiniband/ulp/sdp/sdp_cma.c optional sdp inet \ compile-with "${OFED_C} -I$S/ofed/drivers/infiniband/ulp/sdp/" ofed/drivers/infiniband/ulp/sdp/sdp_tx.c optional sdp inet \ compile-with "${OFED_C} -I$S/ofed/drivers/infiniband/ulp/sdp/" dev/mlx4/mlx4_ib/mlx4_ib_alias_GUID.c optional mlx4ib pci ofed \ compile-with "${OFED_C}" dev/mlx4/mlx4_ib/mlx4_ib_mcg.c optional mlx4ib pci ofed \ compile-with "${OFED_C}" dev/mlx4/mlx4_ib/mlx4_ib_sysfs.c optional mlx4ib pci ofed \ compile-with "${OFED_C}" dev/mlx4/mlx4_ib/mlx4_ib_cm.c optional mlx4ib pci ofed \ compile-with "${OFED_C}" dev/mlx4/mlx4_ib/mlx4_ib_ah.c optional mlx4ib pci ofed \ compile-with "${OFED_C}" dev/mlx4/mlx4_ib/mlx4_ib_cq.c optional mlx4ib pci ofed \ compile-with "${OFED_C}" dev/mlx4/mlx4_ib/mlx4_ib_doorbell.c optional mlx4ib pci ofed \ compile-with "${OFED_C}" dev/mlx4/mlx4_ib/mlx4_ib_mad.c optional mlx4ib pci ofed \ compile-with "${OFED_C}" dev/mlx4/mlx4_ib/mlx4_ib_main.c optional mlx4ib pci ofed \ compile-with "${OFED_C}" dev/mlx4/mlx4_ib/mlx4_ib_mr.c optional mlx4ib pci ofed \ compile-with "${OFED_C}" dev/mlx4/mlx4_ib/mlx4_ib_qp.c optional mlx4ib pci ofed \ compile-with "${OFED_C}" dev/mlx4/mlx4_ib/mlx4_ib_srq.c optional mlx4ib pci ofed \ compile-with "${OFED_C}" dev/mlx4/mlx4_ib/mlx4_ib_wc.c optional mlx4ib pci ofed \ compile-with "${OFED_C}" dev/mlx4/mlx4_core/mlx4_alloc.c optional mlx4 pci \ compile-with "${OFED_C}" dev/mlx4/mlx4_core/mlx4_catas.c optional mlx4 pci \ compile-with "${OFED_C}" dev/mlx4/mlx4_core/mlx4_cmd.c optional mlx4 pci \ compile-with "${OFED_C}" dev/mlx4/mlx4_core/mlx4_cq.c optional mlx4 pci \ compile-with "${OFED_C}" dev/mlx4/mlx4_core/mlx4_eq.c optional mlx4 pci \ compile-with "${OFED_C}" dev/mlx4/mlx4_core/mlx4_fw.c optional mlx4 pci \ compile-with "${OFED_C}" dev/mlx4/mlx4_core/mlx4_fw_qos.c optional mlx4 pci \ compile-with "${OFED_C}" dev/mlx4/mlx4_core/mlx4_icm.c optional mlx4 pci \ compile-with "${OFED_C}" dev/mlx4/mlx4_core/mlx4_intf.c optional mlx4 pci \ compile-with "${OFED_C}" dev/mlx4/mlx4_core/mlx4_main.c optional mlx4 pci \ compile-with "${OFED_C}" dev/mlx4/mlx4_core/mlx4_mcg.c optional mlx4 pci \ compile-with "${OFED_C}" dev/mlx4/mlx4_core/mlx4_mr.c optional mlx4 pci \ compile-with "${OFED_C}" dev/mlx4/mlx4_core/mlx4_pd.c optional mlx4 pci \ compile-with "${OFED_C}" dev/mlx4/mlx4_core/mlx4_port.c optional mlx4 pci \ compile-with "${OFED_C}" dev/mlx4/mlx4_core/mlx4_profile.c optional mlx4 pci \ compile-with "${OFED_C}" dev/mlx4/mlx4_core/mlx4_qp.c optional mlx4 pci \ compile-with "${OFED_C}" dev/mlx4/mlx4_core/mlx4_reset.c optional mlx4 pci \ compile-with "${OFED_C}" dev/mlx4/mlx4_core/mlx4_sense.c optional mlx4 pci \ compile-with "${OFED_C}" dev/mlx4/mlx4_core/mlx4_srq.c optional mlx4 pci \ compile-with "${OFED_C}" dev/mlx4/mlx4_core/mlx4_resource_tracker.c optional mlx4 pci \ compile-with "${OFED_C}" dev/mlx4/mlx4_en/mlx4_en_cq.c optional mlx4en pci inet inet6 \ compile-with "${OFED_C}" dev/mlx4/mlx4_en/mlx4_en_main.c optional mlx4en pci inet inet6 \ compile-with "${OFED_C}" dev/mlx4/mlx4_en/mlx4_en_netdev.c optional mlx4en pci inet inet6 \ compile-with "${OFED_C}" dev/mlx4/mlx4_en/mlx4_en_port.c optional mlx4en pci inet inet6 \ compile-with "${OFED_C}" dev/mlx4/mlx4_en/mlx4_en_resources.c optional mlx4en pci inet inet6 \ compile-with "${OFED_C}" dev/mlx4/mlx4_en/mlx4_en_rx.c optional mlx4en pci inet inet6 \ compile-with "${OFED_C}" dev/mlx4/mlx4_en/mlx4_en_tx.c optional mlx4en pci inet inet6 \ compile-with "${OFED_C}" dev/mlx5/mlx5_ib/mlx5_ib_ah.c optional mlx5ib pci ofed \ compile-with "${OFED_C}" dev/mlx5/mlx5_ib/mlx5_ib_cq.c optional mlx5ib pci ofed \ compile-with "${OFED_C}" dev/mlx5/mlx5_ib/mlx5_ib_doorbell.c optional mlx5ib pci ofed \ compile-with "${OFED_C}" dev/mlx5/mlx5_ib/mlx5_ib_gsi.c optional mlx5ib pci ofed \ compile-with "${OFED_C}" dev/mlx5/mlx5_ib/mlx5_ib_mad.c optional mlx5ib pci ofed \ compile-with "${OFED_C}" dev/mlx5/mlx5_ib/mlx5_ib_main.c optional mlx5ib pci ofed \ compile-with "${OFED_C}" dev/mlx5/mlx5_ib/mlx5_ib_mem.c optional mlx5ib pci ofed \ compile-with "${OFED_C}" dev/mlx5/mlx5_ib/mlx5_ib_mr.c optional mlx5ib pci ofed \ compile-with "${OFED_C}" dev/mlx5/mlx5_ib/mlx5_ib_qp.c optional mlx5ib pci ofed \ compile-with "${OFED_C}" dev/mlx5/mlx5_ib/mlx5_ib_srq.c optional mlx5ib pci ofed \ compile-with "${OFED_C}" dev/mlx5/mlx5_ib/mlx5_ib_virt.c optional mlx5ib pci ofed \ compile-with "${OFED_C}" dev/mlx5/mlx5_core/mlx5_alloc.c optional mlx5 pci \ compile-with "${OFED_C}" dev/mlx5/mlx5_core/mlx5_cmd.c optional mlx5 pci \ compile-with "${OFED_C}" dev/mlx5/mlx5_core/mlx5_cq.c optional mlx5 pci \ compile-with "${OFED_C}" dev/mlx5/mlx5_core/mlx5_diagnostics.c optional mlx5 pci \ compile-with "${OFED_C}" dev/mlx5/mlx5_core/mlx5_eq.c optional mlx5 pci \ compile-with "${OFED_C}" dev/mlx5/mlx5_core/mlx5_fs_cmd.c optional mlx5 pci \ compile-with "${OFED_C}" dev/mlx5/mlx5_core/mlx5_fs_tree.c optional mlx5 pci \ compile-with "${OFED_C}" dev/mlx5/mlx5_core/mlx5_fw.c optional mlx5 pci \ compile-with "${OFED_C}" dev/mlx5/mlx5_core/mlx5_health.c optional mlx5 pci \ compile-with "${OFED_C}" dev/mlx5/mlx5_core/mlx5_mad.c optional mlx5 pci \ compile-with "${OFED_C}" dev/mlx5/mlx5_core/mlx5_main.c optional mlx5 pci \ compile-with "${OFED_C}" dev/mlx5/mlx5_core/mlx5_mcg.c optional mlx5 pci \ compile-with "${OFED_C}" dev/mlx5/mlx5_core/mlx5_mr.c optional mlx5 pci \ compile-with "${OFED_C}" dev/mlx5/mlx5_core/mlx5_pagealloc.c optional mlx5 pci \ compile-with "${OFED_C}" dev/mlx5/mlx5_core/mlx5_pd.c optional mlx5 pci \ compile-with "${OFED_C}" dev/mlx5/mlx5_core/mlx5_port.c optional mlx5 pci \ compile-with "${OFED_C}" dev/mlx5/mlx5_core/mlx5_qp.c optional mlx5 pci \ compile-with "${OFED_C}" dev/mlx5/mlx5_core/mlx5_srq.c optional mlx5 pci \ compile-with "${OFED_C}" dev/mlx5/mlx5_core/mlx5_transobj.c optional mlx5 pci \ compile-with "${OFED_C}" dev/mlx5/mlx5_core/mlx5_uar.c optional mlx5 pci \ compile-with "${OFED_C}" dev/mlx5/mlx5_core/mlx5_vport.c optional mlx5 pci \ compile-with "${OFED_C}" dev/mlx5/mlx5_core/mlx5_wq.c optional mlx5 pci \ compile-with "${OFED_C}" dev/mlx5/mlx5_en/mlx5_en_ethtool.c optional mlx5en pci inet inet6 \ compile-with "${OFED_C}" dev/mlx5/mlx5_en/mlx5_en_main.c optional mlx5en pci inet inet6 \ compile-with "${OFED_C}" dev/mlx5/mlx5_en/mlx5_en_tx.c optional mlx5en pci inet inet6 \ compile-with "${OFED_C}" dev/mlx5/mlx5_en/mlx5_en_flow_table.c optional mlx5en pci inet inet6 \ compile-with "${OFED_C}" dev/mlx5/mlx5_en/mlx5_en_rx.c optional mlx5en pci inet inet6 \ compile-with "${OFED_C}" dev/mlx5/mlx5_en/mlx5_en_txrx.c optional mlx5en pci inet inet6 \ compile-with "${OFED_C}" # crypto support opencrypto/cast.c optional crypto | ipsec | ipsec_support opencrypto/criov.c optional crypto | ipsec | ipsec_support opencrypto/crypto.c optional crypto | ipsec | ipsec_support opencrypto/cryptodev.c optional cryptodev opencrypto/cryptodev_if.m optional crypto | ipsec | ipsec_support opencrypto/cryptosoft.c optional crypto | ipsec | ipsec_support opencrypto/cryptodeflate.c optional crypto | ipsec | ipsec_support opencrypto/gmac.c optional crypto | ipsec | ipsec_support opencrypto/gfmult.c optional crypto | ipsec | ipsec_support opencrypto/rmd160.c optional crypto | ipsec | ipsec_support opencrypto/skipjack.c optional crypto | ipsec | ipsec_support opencrypto/xform.c optional crypto | ipsec | ipsec_support rpc/auth_none.c optional krpc | nfslockd | nfscl | nfsd rpc/auth_unix.c optional krpc | nfslockd | nfscl | nfsd rpc/authunix_prot.c optional krpc | nfslockd | nfscl | nfsd rpc/clnt_bck.c optional krpc | nfslockd | nfscl | nfsd rpc/clnt_dg.c optional krpc | nfslockd | nfscl | nfsd rpc/clnt_rc.c optional krpc | nfslockd | nfscl | nfsd rpc/clnt_vc.c optional krpc | nfslockd | nfscl | nfsd rpc/getnetconfig.c optional krpc | nfslockd | nfscl | nfsd rpc/replay.c optional krpc | nfslockd | nfscl | nfsd rpc/rpc_callmsg.c optional krpc | nfslockd | nfscl | nfsd rpc/rpc_generic.c optional krpc | nfslockd | nfscl | nfsd rpc/rpc_prot.c optional krpc | nfslockd | nfscl | nfsd rpc/rpcb_clnt.c optional krpc | nfslockd | nfscl | nfsd rpc/rpcb_prot.c optional krpc | nfslockd | nfscl | nfsd rpc/svc.c optional krpc | nfslockd | nfscl | nfsd rpc/svc_auth.c optional krpc | nfslockd | nfscl | nfsd rpc/svc_auth_unix.c optional krpc | nfslockd | nfscl | nfsd rpc/svc_dg.c optional krpc | nfslockd | nfscl | nfsd rpc/svc_generic.c optional krpc | nfslockd | nfscl | nfsd rpc/svc_vc.c optional krpc | nfslockd | nfscl | nfsd rpc/rpcsec_gss/rpcsec_gss.c optional krpc kgssapi | nfslockd kgssapi | nfscl kgssapi | nfsd kgssapi rpc/rpcsec_gss/rpcsec_gss_conf.c optional krpc kgssapi | nfslockd kgssapi | nfscl kgssapi | nfsd kgssapi rpc/rpcsec_gss/rpcsec_gss_misc.c optional krpc kgssapi | nfslockd kgssapi | nfscl kgssapi | nfsd kgssapi rpc/rpcsec_gss/rpcsec_gss_prot.c optional krpc kgssapi | nfslockd kgssapi | nfscl kgssapi | nfsd kgssapi rpc/rpcsec_gss/svc_rpcsec_gss.c optional krpc kgssapi | nfslockd kgssapi | nfscl kgssapi | nfsd kgssapi security/audit/audit.c optional audit security/audit/audit_arg.c optional audit security/audit/audit_bsm.c optional audit security/audit/audit_bsm_db.c optional audit security/audit/audit_bsm_klib.c optional audit security/audit/audit_dtrace.c optional dtaudit audit | dtraceall audit compile-with "${CDDL_C}" security/audit/audit_pipe.c optional audit security/audit/audit_syscalls.c standard security/audit/audit_trigger.c optional audit security/audit/audit_worker.c optional audit security/audit/bsm_domain.c optional audit security/audit/bsm_errno.c optional audit security/audit/bsm_fcntl.c optional audit security/audit/bsm_socket_type.c optional audit security/audit/bsm_token.c optional audit security/mac/mac_audit.c optional mac audit security/mac/mac_cred.c optional mac security/mac/mac_framework.c optional mac security/mac/mac_inet.c optional mac inet | mac inet6 security/mac/mac_inet6.c optional mac inet6 security/mac/mac_label.c optional mac security/mac/mac_net.c optional mac security/mac/mac_pipe.c optional mac security/mac/mac_posix_sem.c optional mac security/mac/mac_posix_shm.c optional mac security/mac/mac_priv.c optional mac security/mac/mac_process.c optional mac security/mac/mac_socket.c optional mac security/mac/mac_syscalls.c standard security/mac/mac_system.c optional mac security/mac/mac_sysv_msg.c optional mac security/mac/mac_sysv_sem.c optional mac security/mac/mac_sysv_shm.c optional mac security/mac/mac_vfs.c optional mac security/mac_biba/mac_biba.c optional mac_biba security/mac_bsdextended/mac_bsdextended.c optional mac_bsdextended security/mac_bsdextended/ugidfw_system.c optional mac_bsdextended security/mac_bsdextended/ugidfw_vnode.c optional mac_bsdextended security/mac_ifoff/mac_ifoff.c optional mac_ifoff security/mac_lomac/mac_lomac.c optional mac_lomac security/mac_mls/mac_mls.c optional mac_mls security/mac_none/mac_none.c optional mac_none security/mac_partition/mac_partition.c optional mac_partition security/mac_portacl/mac_portacl.c optional mac_portacl security/mac_seeotheruids/mac_seeotheruids.c optional mac_seeotheruids security/mac_stub/mac_stub.c optional mac_stub security/mac_test/mac_test.c optional mac_test teken/teken.c optional sc | vt ufs/ffs/ffs_alloc.c optional ffs ufs/ffs/ffs_balloc.c optional ffs ufs/ffs/ffs_inode.c optional ffs ufs/ffs/ffs_snapshot.c optional ffs ufs/ffs/ffs_softdep.c optional ffs ufs/ffs/ffs_subr.c optional ffs | geom_label ufs/ffs/ffs_tables.c optional ffs | geom_label ufs/ffs/ffs_vfsops.c optional ffs ufs/ffs/ffs_vnops.c optional ffs ufs/ffs/ffs_rawread.c optional ffs directio ufs/ffs/ffs_suspend.c optional ffs ufs/ufs/ufs_acl.c optional ffs ufs/ufs/ufs_bmap.c optional ffs ufs/ufs/ufs_dirhash.c optional ffs ufs/ufs/ufs_extattr.c optional ffs ufs/ufs/ufs_gjournal.c optional ffs UFS_GJOURNAL ufs/ufs/ufs_inode.c optional ffs ufs/ufs/ufs_lookup.c optional ffs ufs/ufs/ufs_quota.c optional ffs ufs/ufs/ufs_vfsops.c optional ffs ufs/ufs/ufs_vnops.c optional ffs vm/default_pager.c standard vm/device_pager.c standard vm/phys_pager.c standard vm/redzone.c optional DEBUG_REDZONE vm/sg_pager.c standard vm/swap_pager.c standard vm/uma_core.c standard vm/uma_dbg.c standard vm/memguard.c optional DEBUG_MEMGUARD vm/vm_domainset.c standard vm/vm_fault.c standard vm/vm_glue.c standard vm/vm_init.c standard vm/vm_kern.c standard vm/vm_map.c standard vm/vm_meter.c standard vm/vm_mmap.c standard vm/vm_object.c standard vm/vm_page.c standard vm/vm_pageout.c standard vm/vm_pager.c standard vm/vm_phys.c standard vm/vm_radix.c standard vm/vm_reserv.c standard vm/vm_swapout.c optional !NO_SWAPPING vm/vm_swapout_dummy.c optional NO_SWAPPING vm/vm_unix.c standard vm/vnode_pager.c standard xen/features.c optional xenhvm xen/xenbus/xenbus_if.m optional xenhvm xen/xenbus/xenbus.c optional xenhvm xen/xenbus/xenbusb_if.m optional xenhvm xen/xenbus/xenbusb.c optional xenhvm xen/xenbus/xenbusb_front.c optional xenhvm xen/xenbus/xenbusb_back.c optional xenhvm xen/xenmem/xenmem_if.m optional xenhvm xdr/xdr.c optional krpc | nfslockd | nfscl | nfsd xdr/xdr_array.c optional krpc | nfslockd | nfscl | nfsd xdr/xdr_mbuf.c optional krpc | nfslockd | nfscl | nfsd xdr/xdr_mem.c optional krpc | nfslockd | nfscl | nfsd xdr/xdr_reference.c optional krpc | nfslockd | nfscl | nfsd xdr/xdr_sizeof.c optional krpc | nfslockd | nfscl | nfsd Index: head/sys/dev/siba/siba_core.c =================================================================== --- head/sys/dev/siba/siba_core.c (revision 328911) +++ head/sys/dev/siba/siba_core.c (nonexistent) @@ -1,3036 +0,0 @@ -/*- - * SPDX-License-Identifier: BSD-2-Clause-FreeBSD - * - * Copyright (c) 2009-2010 Weongyo Jeong - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer, - * without modification. - * 2. Redistributions in binary form must reproduce at minimum a disclaimer - * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any - * redistribution must be conditioned upon including a substantially - * similar Disclaimer requirement for further binary redistribution. - * - * NO WARRANTY - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY - * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL - * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, - * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER - * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF - * THE POSSIBILITY OF SUCH DAMAGES. - */ - -#include -__FBSDID("$FreeBSD$"); - -/* - * the Sonics Silicon Backplane driver. - */ - -#include "opt_siba.h" - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include - -#include -#include - -#include -#include -#include - -enum { - SIBA_DEBUG_SCAN = 0x00000001, /* scan */ - SIBA_DEBUG_PMU = 0x00000002, /* PMU */ - SIBA_DEBUG_PLL = 0x00000004, /* PLL */ - SIBA_DEBUG_SWITCHCORE = 0x00000008, /* switching core */ - SIBA_DEBUG_SPROM = 0x00000010, /* SPROM */ - SIBA_DEBUG_CORE = 0x00000020, /* handling cores */ - SIBA_DEBUG_DMA = 0x00000040, /* DMA bits */ - SIBA_DEBUG_ANY = 0xffffffff -}; - -#ifdef SIBA_DEBUG -#define DPRINTF(siba, m, ...) do { \ - if (siba->siba_debug & (m)) \ - device_printf(siba->siba_dev, __VA_ARGS__); \ -} while (0) -#else -#define DPRINTF(siba, m, ...) do { (void) siba; } while (0) -#endif - -#define N(a) (sizeof(a) / sizeof(a[0])) - -static void siba_pci_gpio(struct siba_softc *, uint32_t, int); -static void siba_scan(struct siba_softc *); -static int siba_switchcore(struct siba_softc *, uint8_t); -static int siba_pci_switchcore_sub(struct siba_softc *, uint8_t); -static uint32_t siba_scan_read_4(struct siba_softc *, uint8_t, uint16_t); -static uint16_t siba_dev2chipid(struct siba_softc *); -static uint16_t siba_pci_read_2(struct siba_dev_softc *, uint16_t); -static uint32_t siba_pci_read_4(struct siba_dev_softc *, uint16_t); -static void siba_pci_write_2(struct siba_dev_softc *, uint16_t, uint16_t); -static void siba_pci_write_4(struct siba_dev_softc *, uint16_t, uint32_t); -static void siba_cc_clock(struct siba_cc *, - enum siba_clock); -static void siba_cc_pmu_init(struct siba_cc *); -static void siba_cc_power_init(struct siba_cc *); -static void siba_cc_powerup_delay(struct siba_cc *); -static int siba_cc_clockfreq(struct siba_cc *, int); -static void siba_cc_pmu1_pll0_init(struct siba_cc *, uint32_t); -static void siba_cc_pmu0_pll0_init(struct siba_cc *, uint32_t); -static enum siba_clksrc siba_cc_clksrc(struct siba_cc *); -static const struct siba_cc_pmu1_plltab *siba_cc_pmu1_plltab_find(uint32_t); -static uint32_t siba_cc_pll_read(struct siba_cc *, uint32_t); -static void siba_cc_pll_write(struct siba_cc *, uint32_t, - uint32_t); -static const struct siba_cc_pmu0_plltab * - siba_cc_pmu0_plltab_findentry(uint32_t); -static int siba_pci_sprom(struct siba_softc *, struct siba_sprom *); -static int siba_sprom_read(struct siba_softc *, uint16_t *, uint16_t); -static int sprom_check_crc(const uint16_t *, size_t); -static uint8_t siba_crc8(uint8_t, uint8_t); -static void siba_sprom_r123(struct siba_sprom *, const uint16_t *); -static void siba_sprom_r45(struct siba_sprom *, const uint16_t *); -static void siba_sprom_r8(struct siba_sprom *, const uint16_t *); -static int8_t siba_sprom_r123_antgain(uint8_t, const uint16_t *, uint16_t, - uint16_t); -static uint32_t siba_tmslow_reject_bitmask(struct siba_dev_softc *); -static uint32_t siba_pcicore_read_4(struct siba_pci *, uint16_t); -static void siba_pcicore_write_4(struct siba_pci *, uint16_t, uint32_t); -static uint32_t siba_pcie_read(struct siba_pci *, uint32_t); -static void siba_pcie_write(struct siba_pci *, uint32_t, uint32_t); -static void siba_pcie_mdio_write(struct siba_pci *, uint8_t, uint8_t, - uint16_t); -static void siba_pci_read_multi_1(struct siba_dev_softc *, void *, size_t, - uint16_t); -static void siba_pci_read_multi_2(struct siba_dev_softc *, void *, size_t, - uint16_t); -static void siba_pci_read_multi_4(struct siba_dev_softc *, void *, size_t, - uint16_t); -static void siba_pci_write_multi_1(struct siba_dev_softc *, const void *, - size_t, uint16_t); -static void siba_pci_write_multi_2(struct siba_dev_softc *, const void *, - size_t, uint16_t); -static void siba_pci_write_multi_4(struct siba_dev_softc *, const void *, - size_t, uint16_t); -static const char *siba_core_name(uint16_t); -static void siba_pcicore_init(struct siba_pci *); -static uint32_t siba_read_4_sub(struct siba_dev_softc *, uint16_t); -static void siba_write_4_sub(struct siba_dev_softc *, uint16_t, uint32_t); -static void siba_powerup_sub(struct siba_softc *, int); -static int siba_powerdown_sub(struct siba_softc *); -static int siba_dev_isup_sub(struct siba_dev_softc *); -static void siba_dev_up_sub(struct siba_dev_softc *, uint32_t); -static void siba_dev_down_sub(struct siba_dev_softc *, uint32_t); -int siba_core_attach(struct siba_softc *); -int siba_core_detach(struct siba_softc *); -int siba_core_suspend(struct siba_softc *); -int siba_core_resume(struct siba_softc *); -uint8_t siba_getncores(device_t, uint16_t); - -static const struct siba_bus_ops siba_pci_ops = { - .read_2 = siba_pci_read_2, - .read_4 = siba_pci_read_4, - .write_2 = siba_pci_write_2, - .write_4 = siba_pci_write_4, - .read_multi_1 = siba_pci_read_multi_1, - .read_multi_2 = siba_pci_read_multi_2, - .read_multi_4 = siba_pci_read_multi_4, - .write_multi_1 = siba_pci_write_multi_1, - .write_multi_2 = siba_pci_write_multi_2, - .write_multi_4 = siba_pci_write_multi_4, -}; - -static const struct siba_cc_pmu_res_updown siba_cc_pmu_4325_updown[] = - SIBA_CC_PMU_4325_RES_UPDOWN; -static const struct siba_cc_pmu_res_depend siba_cc_pmu_4325_depend[] = - SIBA_CC_PMU_4325_RES_DEPEND; -static const struct siba_cc_pmu_res_updown siba_cc_pmu_4328_updown[] = - SIBA_CC_PMU_4328_RES_UPDOWN; -static const struct siba_cc_pmu_res_depend siba_cc_pmu_4328_depend[] = - SIBA_CC_PMU_4328_RES_DEPEND; -static const struct siba_cc_pmu0_plltab siba_cc_pmu0_plltab[] = - SIBA_CC_PMU0_PLLTAB_ENTRY; -static const struct siba_cc_pmu1_plltab siba_cc_pmu1_plltab[] = - SIBA_CC_PMU1_PLLTAB_ENTRY; - -int -siba_core_attach(struct siba_softc *siba) -{ - struct siba_cc *scc; - int error; - - KASSERT(siba->siba_type == SIBA_TYPE_PCI, - ("unsupported BUS type (%#x)", siba->siba_type)); - - siba->siba_ops = &siba_pci_ops; - - siba_pci_gpio(siba, SIBA_GPIO_CRYSTAL | SIBA_GPIO_PLL, 1); - siba_scan(siba); - - /* XXX init PCI or PCMCIA host devices */ - - siba_powerup_sub(siba, 0); - - /* init ChipCommon */ - scc = &siba->siba_cc; - if (scc->scc_dev != NULL) { - siba_cc_pmu_init(scc); - siba_cc_power_init(scc); - siba_cc_clock(scc, SIBA_CLOCK_FAST); - siba_cc_powerup_delay(scc); - } - - error = siba_pci_sprom(siba, &siba->siba_sprom); - if (error) { - siba_powerdown_sub(siba); - return (error); - } - - siba_pcicore_init(&siba->siba_pci); - siba_powerdown_sub(siba); - - return (bus_generic_attach(siba->siba_dev)); -} - -int -siba_core_detach(struct siba_softc *siba) -{ - /* detach & delete all children */ - device_delete_children(siba->siba_dev); - return (0); -} - -static void -siba_pci_gpio(struct siba_softc *siba, uint32_t what, int on) -{ - uint32_t in, out; - uint16_t status; - - if (siba->siba_type != SIBA_TYPE_PCI) - return; - - out = pci_read_config(siba->siba_dev, SIBA_GPIO_OUT, 4); - if (on == 0) { - if (what & SIBA_GPIO_PLL) - out |= SIBA_GPIO_PLL; - if (what & SIBA_GPIO_CRYSTAL) - out &= ~SIBA_GPIO_CRYSTAL; - pci_write_config(siba->siba_dev, SIBA_GPIO_OUT, out, 4); - pci_write_config(siba->siba_dev, SIBA_GPIO_OUT_EN, - pci_read_config(siba->siba_dev, - SIBA_GPIO_OUT_EN, 4) | what, 4); - return; - } - - in = pci_read_config(siba->siba_dev, SIBA_GPIO_IN, 4); - if ((in & SIBA_GPIO_CRYSTAL) != SIBA_GPIO_CRYSTAL) { - if (what & SIBA_GPIO_CRYSTAL) { - out |= SIBA_GPIO_CRYSTAL; - if (what & SIBA_GPIO_PLL) - out |= SIBA_GPIO_PLL; - pci_write_config(siba->siba_dev, SIBA_GPIO_OUT, out, 4); - pci_write_config(siba->siba_dev, - SIBA_GPIO_OUT_EN, pci_read_config(siba->siba_dev, - SIBA_GPIO_OUT_EN, 4) | what, 4); - DELAY(1000); - } - if (what & SIBA_GPIO_PLL) { - out &= ~SIBA_GPIO_PLL; - pci_write_config(siba->siba_dev, SIBA_GPIO_OUT, out, 4); - DELAY(5000); - } - } - - status = pci_read_config(siba->siba_dev, PCIR_STATUS, 2); - status &= ~PCIM_STATUS_STABORT; - pci_write_config(siba->siba_dev, PCIR_STATUS, status, 2); -} - -static void -siba_scan(struct siba_softc *siba) -{ - struct siba_dev_softc *sd; - uint32_t idhi, tmp; - device_t child; - int base, dev_i = 0, error, i, is_pcie, n_80211 = 0, n_cc = 0, - n_pci = 0; - - KASSERT(siba->siba_type == SIBA_TYPE_PCI, - ("unsupported BUS type (%#x)", siba->siba_type)); - - siba->siba_ndevs = 0; - error = siba_switchcore(siba, 0); /* need the first core */ - if (error) - return; - - idhi = siba_scan_read_4(siba, 0, SIBA_IDHIGH); - if (SIBA_IDHIGH_CORECODE(idhi) == SIBA_DEVID_CHIPCOMMON) { - tmp = siba_scan_read_4(siba, 0, SIBA_CC_CHIPID); - siba->siba_chipid = SIBA_CC_ID(tmp); - siba->siba_chiprev = SIBA_CC_REV(tmp); - siba->siba_chippkg = SIBA_CC_PKG(tmp); - if (SIBA_IDHIGH_REV(idhi) >= 4) - siba->siba_ndevs = SIBA_CC_NCORES(tmp); - siba->siba_cc.scc_caps = siba_scan_read_4(siba, 0, - SIBA_CC_CAPS); - } else { - if (siba->siba_type == SIBA_TYPE_PCI) { - siba->siba_chipid = siba_dev2chipid(siba); - siba->siba_chiprev = pci_read_config(siba->siba_dev, - PCIR_REVID, 2); - siba->siba_chippkg = 0; - } else { - siba->siba_chipid = 0x4710; - siba->siba_chiprev = 0; - siba->siba_chippkg = 0; - } - } - if (siba->siba_ndevs == 0) - siba->siba_ndevs = siba_getncores(siba->siba_dev, - siba->siba_chipid); - if (siba->siba_ndevs > SIBA_MAX_CORES) { - device_printf(siba->siba_dev, - "too many siba cores (max %d %d)\n", - SIBA_MAX_CORES, siba->siba_ndevs); - return; - } - - /* looking basic information about each cores/devices */ - for (i = 0; i < siba->siba_ndevs; i++) { - error = siba_switchcore(siba, i); - if (error) - return; - sd = &(siba->siba_devs[dev_i]); - idhi = siba_scan_read_4(siba, i, SIBA_IDHIGH); - sd->sd_bus = siba; - sd->sd_id.sd_device = SIBA_IDHIGH_CORECODE(idhi); - sd->sd_id.sd_rev = SIBA_IDHIGH_REV(idhi); - sd->sd_id.sd_vendor = SIBA_IDHIGH_VENDOR(idhi); - sd->sd_ops = siba->siba_ops; - sd->sd_coreidx = i; - - DPRINTF(siba, SIBA_DEBUG_SCAN, - "core %d (%s) found (cc %#x rev %#x vendor %#x)\n", - i, siba_core_name(sd->sd_id.sd_device), - sd->sd_id.sd_device, sd->sd_id.sd_rev, - sd->sd_id.sd_vendor); - - switch (sd->sd_id.sd_device) { - case SIBA_DEVID_CHIPCOMMON: - n_cc++; - if (n_cc > 1) { - device_printf(siba->siba_dev, - "warn: multiple ChipCommon\n"); - break; - } - siba->siba_cc.scc_dev = sd; - break; - case SIBA_DEVID_80211: - n_80211++; - if (n_80211 > 1) { - device_printf(siba->siba_dev, - "warn: multiple 802.11 core\n"); - continue; - } - break; - case SIBA_DEVID_PCI: - case SIBA_DEVID_PCIE: - n_pci++; - error = pci_find_cap(siba->siba_dev, PCIY_EXPRESS, - &base); - is_pcie = (error == 0) ? 1 : 0; - - if (n_pci > 1) { - device_printf(siba->siba_dev, - "warn: multiple PCI(E) cores\n"); - break; - } - if (sd->sd_id.sd_device == SIBA_DEVID_PCI && - is_pcie == 1) - continue; - if (sd->sd_id.sd_device == SIBA_DEVID_PCIE && - is_pcie == 0) - continue; - siba->siba_pci.spc_dev = sd; - break; - case SIBA_DEVID_MODEM: - case SIBA_DEVID_PCMCIA: - break; - default: - device_printf(siba->siba_dev, - "unsupported coreid (%s)\n", - siba_core_name(sd->sd_id.sd_device)); - break; - } - dev_i++; - - child = device_add_child(siba->siba_dev, NULL, -1); - if (child == NULL) { - device_printf(siba->siba_dev, "child attach failed\n"); - continue; - } - - device_set_ivars(child, sd); - } - siba->siba_ndevs = dev_i; -} - -static int -siba_switchcore(struct siba_softc *siba, uint8_t idx) -{ - - switch (siba->siba_type) { - case SIBA_TYPE_PCI: - return (siba_pci_switchcore_sub(siba, idx)); - default: - KASSERT(0 == 1, - ("%s: unsupported bustype %#x", __func__, - siba->siba_type)); - } - return (0); -} - -static int -siba_pci_switchcore_sub(struct siba_softc *siba, uint8_t idx) -{ -#define RETRY_MAX 50 - int i; - uint32_t dir; - - dir = SIBA_REGWIN(idx); - - for (i = 0; i < RETRY_MAX; i++) { - pci_write_config(siba->siba_dev, SIBA_BAR0, dir, 4); - if (pci_read_config(siba->siba_dev, SIBA_BAR0, 4) == dir) - return (0); - DELAY(10); - } - DPRINTF(siba, SIBA_DEBUG_SWITCHCORE, "%s: idx %d, failed\n", __func__, idx); - return (ENODEV); -#undef RETRY_MAX -} - -static int -siba_pci_switchcore(struct siba_softc *siba, struct siba_dev_softc *sd) -{ - int error; - - DPRINTF(siba, SIBA_DEBUG_SWITCHCORE, "Switching to %s core, index %d\n", - siba_core_name(sd->sd_id.sd_device), sd->sd_coreidx); - - error = siba_pci_switchcore_sub(siba, sd->sd_coreidx); - if (error == 0) - siba->siba_curdev = sd; - - return (error); -} - -static uint32_t -siba_scan_read_4(struct siba_softc *siba, uint8_t coreidx, - uint16_t offset) -{ - - (void)coreidx; - KASSERT(siba->siba_type == SIBA_TYPE_PCI, - ("unsupported BUS type (%#x)", siba->siba_type)); - - return (SIBA_READ_4(siba, offset)); -} - -static uint16_t -siba_dev2chipid(struct siba_softc *siba) -{ - uint16_t chipid = 0; - - switch (siba->siba_pci_did) { - case 0x4301: - chipid = 0x4301; - break; - case 0x4305: - case 0x4306: - case 0x4307: - chipid = 0x4307; - break; - case 0x4403: - chipid = 0x4402; - break; - case 0x4610: - case 0x4611: - case 0x4612: - case 0x4613: - case 0x4614: - case 0x4615: - chipid = 0x4610; - break; - case 0x4710: - case 0x4711: - case 0x4712: - case 0x4713: - case 0x4714: - case 0x4715: - chipid = 0x4710; - break; - case 0x4320: - case 0x4321: - case 0x4322: - case 0x4323: - case 0x4324: - case 0x4325: - chipid = 0x4309; - break; - case PCI_DEVICE_ID_BCM4401: - case PCI_DEVICE_ID_BCM4401B0: - case PCI_DEVICE_ID_BCM4401B1: - chipid = 0x4401; - break; - default: - device_printf(siba->siba_dev, "unknown PCI did (%d)\n", - siba->siba_pci_did); - } - - return (chipid); -} - -/* - * Earlier ChipCommon revisions have hardcoded number of cores - * present dependent on the ChipCommon ID. - */ -uint8_t -siba_getncores(device_t dev, uint16_t chipid) -{ - switch (chipid) { - case 0x4401: - case 0x4402: - return (3); - case 0x4301: - case 0x4307: - return (5); - case 0x4306: - return (6); - case SIBA_CCID_SENTRY5: - return (7); - case 0x4310: - return (8); - case SIBA_CCID_BCM4710: - case 0x4610: - case SIBA_CCID_BCM4704: - return (9); - default: - device_printf(dev, "unknown the chipset ID %#x\n", chipid); - } - - return (1); -} - -static const char * -siba_core_name(uint16_t coreid) -{ - - switch (coreid) { - case SIBA_DEVID_CHIPCOMMON: - return ("ChipCommon"); - case SIBA_DEVID_ILINE20: - return ("ILine 20"); - case SIBA_DEVID_SDRAM: - return ("SDRAM"); - case SIBA_DEVID_PCI: - return ("PCI"); - case SIBA_DEVID_MIPS: - return ("MIPS"); - case SIBA_DEVID_ETHERNET: - return ("Fast Ethernet"); - case SIBA_DEVID_MODEM: - return ("Modem"); - case SIBA_DEVID_USB11_HOSTDEV: - return ("USB 1.1 Hostdev"); - case SIBA_DEVID_ADSL: - return ("ADSL"); - case SIBA_DEVID_ILINE100: - return ("ILine 100"); - case SIBA_DEVID_IPSEC: - return ("IPSEC"); - case SIBA_DEVID_PCMCIA: - return ("PCMCIA"); - case SIBA_DEVID_INTERNAL_MEM: - return ("Internal Memory"); - case SIBA_DEVID_SDRAMDDR: - return ("MEMC SDRAM"); - case SIBA_DEVID_EXTIF: - return ("EXTIF"); - case SIBA_DEVID_80211: - return ("IEEE 802.11"); - case SIBA_DEVID_MIPS_3302: - return ("MIPS 3302"); - case SIBA_DEVID_USB11_HOST: - return ("USB 1.1 Host"); - case SIBA_DEVID_USB11_DEV: - return ("USB 1.1 Device"); - case SIBA_DEVID_USB20_HOST: - return ("USB 2.0 Host"); - case SIBA_DEVID_USB20_DEV: - return ("USB 2.0 Device"); - case SIBA_DEVID_SDIO_HOST: - return ("SDIO Host"); - case SIBA_DEVID_ROBOSWITCH: - return ("Roboswitch"); - case SIBA_DEVID_PARA_ATA: - return ("PATA"); - case SIBA_DEVID_SATA_XORDMA: - return ("SATA XOR-DMA"); - case SIBA_DEVID_ETHERNET_GBIT: - return ("GBit Ethernet"); - case SIBA_DEVID_PCIE: - return ("PCI-Express"); - case SIBA_DEVID_MIMO_PHY: - return ("MIMO PHY"); - case SIBA_DEVID_SRAM_CTRLR: - return ("SRAM Controller"); - case SIBA_DEVID_MINI_MACPHY: - return ("Mini MACPHY"); - case SIBA_DEVID_ARM_1176: - return ("ARM 1176"); - case SIBA_DEVID_ARM_7TDMI: - return ("ARM 7TDMI"); - } - return ("unknown"); -} - -static uint16_t -siba_pci_read_2(struct siba_dev_softc *sd, uint16_t offset) -{ - struct siba_softc *siba = sd->sd_bus; - - if (siba->siba_curdev != sd && siba_pci_switchcore(siba, sd) != 0) - return (0xffff); - - return (SIBA_READ_2(siba, offset)); -} - -static uint32_t -siba_pci_read_4(struct siba_dev_softc *sd, uint16_t offset) -{ - struct siba_softc *siba = sd->sd_bus; - - if (siba->siba_curdev != sd && siba_pci_switchcore(siba, sd) != 0) - return (0xffff); - - return (SIBA_READ_4(siba, offset)); -} - -static void -siba_pci_write_2(struct siba_dev_softc *sd, uint16_t offset, uint16_t value) -{ - struct siba_softc *siba = sd->sd_bus; - - if (siba->siba_curdev != sd && siba_pci_switchcore(siba, sd) != 0) - return; - - SIBA_WRITE_2(siba, offset, value); -} - -static void -siba_pci_write_4(struct siba_dev_softc *sd, uint16_t offset, uint32_t value) -{ - struct siba_softc *siba = sd->sd_bus; - - if (siba->siba_curdev != sd && siba_pci_switchcore(siba, sd) != 0) - return; - - SIBA_WRITE_4(siba, offset, value); -} - -static void -siba_pci_read_multi_1(struct siba_dev_softc *sd, void *buffer, size_t count, - uint16_t offset) -{ - struct siba_softc *siba = sd->sd_bus; - - if (siba->siba_curdev != sd && siba_pci_switchcore(siba, sd) != 0) { - memset(buffer, 0xff, count); - return; - } - - SIBA_READ_MULTI_1(siba, offset, buffer, count); -} - -static void -siba_pci_read_multi_2(struct siba_dev_softc *sd, void *buffer, size_t count, - uint16_t offset) -{ - struct siba_softc *siba = sd->sd_bus; - - if (siba->siba_curdev != sd && siba_pci_switchcore(siba, sd) != 0) { - memset(buffer, 0xff, count); - return; - } - - KASSERT(!(count & 1), ("%s:%d: fail", __func__, __LINE__)); - SIBA_READ_MULTI_2(siba, offset, buffer, count >> 1); -} - -static void -siba_pci_read_multi_4(struct siba_dev_softc *sd, void *buffer, size_t count, - uint16_t offset) -{ - struct siba_softc *siba = sd->sd_bus; - - if (siba->siba_curdev != sd && siba_pci_switchcore(siba, sd) != 0) { - memset(buffer, 0xff, count); - return; - } - - KASSERT(!(count & 3), ("%s:%d: fail", __func__, __LINE__)); - SIBA_READ_MULTI_4(siba, offset, buffer, count >> 2); -} - -static void -siba_pci_write_multi_1(struct siba_dev_softc *sd, const void *buffer, - size_t count, uint16_t offset) -{ - struct siba_softc *siba = sd->sd_bus; - - if (siba->siba_curdev != sd && siba_pci_switchcore(siba, sd) != 0) - return; - - SIBA_WRITE_MULTI_1(siba, offset, buffer, count); -} - -static void -siba_pci_write_multi_2(struct siba_dev_softc *sd, const void *buffer, - size_t count, uint16_t offset) -{ - struct siba_softc *siba = sd->sd_bus; - - if (siba->siba_curdev != sd && siba_pci_switchcore(siba, sd) != 0) - return; - - KASSERT(!(count & 1), ("%s:%d: fail", __func__, __LINE__)); - SIBA_WRITE_MULTI_2(siba, offset, buffer, count >> 1); -} - -static void -siba_pci_write_multi_4(struct siba_dev_softc *sd, const void *buffer, - size_t count, uint16_t offset) -{ - struct siba_softc *siba = sd->sd_bus; - - if (siba->siba_curdev != sd && siba_pci_switchcore(siba, sd) != 0) - return; - - KASSERT(!(count & 3), ("%s:%d: fail", __func__, __LINE__)); - SIBA_WRITE_MULTI_4(siba, offset, buffer, count >> 2); -} - -void -siba_powerup(device_t dev, int dynamic) -{ - struct siba_dev_softc *sd = device_get_ivars(dev); - struct siba_softc *siba = sd->sd_bus; - - siba_powerup_sub(siba, dynamic); -} - -static void -siba_powerup_sub(struct siba_softc *siba, int dynamic) -{ - - siba_pci_gpio(siba, SIBA_GPIO_CRYSTAL | SIBA_GPIO_PLL, 1); - siba_cc_clock(&siba->siba_cc, - (dynamic != 0) ? SIBA_CLOCK_DYNAMIC : SIBA_CLOCK_FAST); -} - -static void -siba_cc_clock(struct siba_cc *scc, enum siba_clock clock) -{ - struct siba_dev_softc *sd = scc->scc_dev; - struct siba_softc *siba; - uint32_t tmp; - - if (sd == NULL) - return; - siba = sd->sd_bus; - - /* - * PMU controls clockmode; separate function is needed - */ - if (scc->scc_caps & SIBA_CC_CAPS_PMU) - return; - - /* - * chipcommon < r6 (no dynamic clock control) - * chipcommon >= r10 (unknown) - */ - if (sd->sd_id.sd_rev < 6 || sd->sd_id.sd_rev >= 10 || - (scc->scc_caps & SIBA_CC_CAPS_PWCTL) == 0) - return; - - switch (clock) { - case SIBA_CLOCK_DYNAMIC: - tmp = SIBA_CC_READ32(scc, SIBA_CC_CLKSLOW) & - ~(SIBA_CC_CLKSLOW_ENXTAL | SIBA_CC_CLKSLOW_FSLOW | - SIBA_CC_CLKSLOW_IPLL); - if ((tmp & SIBA_CC_CLKSLOW_SRC) != SIBA_CC_CLKSLOW_SRC_CRYSTAL) - tmp |= SIBA_CC_CLKSLOW_ENXTAL; - SIBA_CC_WRITE32(scc, SIBA_CC_CLKSLOW, tmp); - if (tmp & SIBA_CC_CLKSLOW_ENXTAL) - siba_pci_gpio(siba, SIBA_GPIO_CRYSTAL, 0); - break; - case SIBA_CLOCK_SLOW: - SIBA_CC_WRITE32(scc, SIBA_CC_CLKSLOW, - SIBA_CC_READ32(scc, SIBA_CC_CLKSLOW) | - SIBA_CC_CLKSLOW_FSLOW); - break; - case SIBA_CLOCK_FAST: - /* crystal on */ - siba_pci_gpio(siba, SIBA_GPIO_CRYSTAL, 1); - SIBA_CC_WRITE32(scc, SIBA_CC_CLKSLOW, - (SIBA_CC_READ32(scc, SIBA_CC_CLKSLOW) | - SIBA_CC_CLKSLOW_IPLL) & ~SIBA_CC_CLKSLOW_FSLOW); - break; - default: - KASSERT(0 == 1, - ("%s: unsupported clock %#x", __func__, clock)); - } -} - -uint16_t -siba_read_2(device_t dev, uint16_t offset) -{ - struct siba_dev_softc *sd = device_get_ivars(dev); - - return (sd->sd_ops->read_2(sd, offset)); -} - -uint32_t -siba_read_4(device_t dev, uint16_t offset) -{ - struct siba_dev_softc *sd = device_get_ivars(dev); - - return (siba_read_4_sub(sd, offset)); -} - -static uint32_t -siba_read_4_sub(struct siba_dev_softc *sd, uint16_t offset) -{ - - return (sd->sd_ops->read_4(sd, offset)); -} - -void -siba_write_2(device_t dev, uint16_t offset, uint16_t value) -{ - struct siba_dev_softc *sd = device_get_ivars(dev); - - sd->sd_ops->write_2(sd, offset, value); -} - -void -siba_write_4(device_t dev, uint16_t offset, uint32_t value) -{ - struct siba_dev_softc *sd = device_get_ivars(dev); - - return (siba_write_4_sub(sd, offset, value)); -} - -static void -siba_write_4_sub(struct siba_dev_softc *sd, uint16_t offset, uint32_t value) -{ - - sd->sd_ops->write_4(sd, offset, value); -} - -void -siba_read_multi_1(device_t dev, void *buffer, size_t count, - uint16_t offset) -{ - struct siba_dev_softc *sd = device_get_ivars(dev); - - sd->sd_ops->read_multi_1(sd, buffer, count, offset); -} - -void -siba_read_multi_2(device_t dev, void *buffer, size_t count, - uint16_t offset) -{ - struct siba_dev_softc *sd = device_get_ivars(dev); - - sd->sd_ops->read_multi_2(sd, buffer, count, offset); -} - -void -siba_read_multi_4(device_t dev, void *buffer, size_t count, - uint16_t offset) -{ - struct siba_dev_softc *sd = device_get_ivars(dev); - - sd->sd_ops->read_multi_4(sd, buffer, count, offset); -} - -void -siba_write_multi_1(device_t dev, const void *buffer, size_t count, - uint16_t offset) -{ - struct siba_dev_softc *sd = device_get_ivars(dev); - - sd->sd_ops->write_multi_1(sd, buffer, count, offset); -} - -void -siba_write_multi_2(device_t dev, const void *buffer, size_t count, - uint16_t offset) -{ - struct siba_dev_softc *sd = device_get_ivars(dev); - - sd->sd_ops->write_multi_2(sd, buffer, count, offset); -} - -void -siba_write_multi_4(device_t dev, const void *buffer, size_t count, - uint16_t offset) -{ - struct siba_dev_softc *sd = device_get_ivars(dev); - - sd->sd_ops->write_multi_4(sd, buffer, count, offset); -} - -static void -siba_cc_pmu_init(struct siba_cc *scc) -{ - const struct siba_cc_pmu_res_updown *updown = NULL; - const struct siba_cc_pmu_res_depend *depend = NULL; - struct siba_dev_softc *sd = scc->scc_dev; - struct siba_softc *siba = sd->sd_bus; - uint32_t min = 0, max = 0, pmucap; - unsigned int i, updown_size, depend_size; - - if ((scc->scc_caps & SIBA_CC_CAPS_PMU) == 0) - return; - - pmucap = SIBA_CC_READ32(scc, SIBA_CC_PMUCAPS); - scc->scc_pmu.rev = (pmucap & SIBA_CC_PMUCAPS_REV); - - DPRINTF(siba, SIBA_DEBUG_PMU, "PMU(r%u) found (caps %#x)\n", - scc->scc_pmu.rev, pmucap); - -#if 0 - if (scc->scc_pmu.rev >= 1) { - if (siba->siba_chiprev < 2 && siba->siba_chipid == 0x4325) - SIBA_CC_MASK32(scc, SIBA_CC_PMUCTL, - ~SIBA_CC_PMUCTL_NOILP); - else - SIBA_CC_SET32(scc, SIBA_CC_PMUCTL, - SIBA_CC_PMUCTL_NOILP); - } -#endif - if (scc->scc_pmu.rev == 1) { - SIBA_CC_MASK32(scc, SIBA_CC_PMUCTL, ~SIBA_CC_PMUCTL_NOILP); - } else { - SIBA_CC_SET32(scc, SIBA_CC_PMUCTL, SIBA_CC_PMUCTL_NOILP); - } - - /* initialize PLL & PMU resources */ - switch (siba->siba_chipid) { - case 0x4312: - siba_cc_pmu1_pll0_init(scc, 0 /* use default */); - /* use the default: min = 0xcbb max = 0x7ffff */ - break; - case 0x4322: - if (scc->scc_pmu.rev == 2) { - DPRINTF(siba, SIBA_DEBUG_PMU, "%s: chipid 0x4322; PLLing\n", - __func__); - SIBA_CC_WRITE32(scc, SIBA_CC_PLLCTL_ADDR, 0x0000000a); - SIBA_CC_WRITE32(scc, SIBA_CC_PLLCTL_DATA, 0x380005c0); - } - /* use the default: min = 0xcbb max = 0x7ffff */ - break; - case 43222: - break; - case 0x4325: - siba_cc_pmu1_pll0_init(scc, 0 /* use default */); - - updown = siba_cc_pmu_4325_updown; - updown_size = N(siba_cc_pmu_4325_updown); - depend = siba_cc_pmu_4325_depend; - depend_size = N(siba_cc_pmu_4325_depend); - - min = (1 << SIBA_CC_PMU_4325_BURST) | - (1 << SIBA_CC_PMU_4325_LN); - if (SIBA_CC_READ32(scc, SIBA_CC_CHIPSTAT) & - SIBA_CC_CHST_4325_PMUTOP_2B) - min |= (1 << SIBA_CC_PMU_4325_CLBURST); - max = 0xfffff; - break; - case 0x4328: - siba_cc_pmu0_pll0_init(scc, 0 /* use default */); - - updown = siba_cc_pmu_4328_updown; - updown_size = N(siba_cc_pmu_4328_updown); - depend = siba_cc_pmu_4328_depend; - depend_size = N(siba_cc_pmu_4328_depend); - - min = (1 << SIBA_CC_PMU_4328_EXT_SWITCH_PWM) | - (1 << SIBA_CC_PMU_4328_BB_SWITCH_PWM) | - (1 << SIBA_CC_PMU_4328_CRYSTAL_EN); - - max = 0xfffff; - break; - case 0x5354: - siba_cc_pmu0_pll0_init(scc, 0 /* use default */); - - max = 0xfffff; - break; - default: - device_printf(siba->siba_dev, - "unknown chipid %#x for PLL & PMU init\n", - siba->siba_chipid); - } - - if (updown) { - for (i = 0; i < updown_size; i++) { - SIBA_CC_WRITE32(scc, SIBA_CC_PMU_TABSEL, - updown[i].res); - SIBA_CC_WRITE32(scc, SIBA_CC_PMU_UPDNTM, - updown[i].updown); - } - } - if (depend) { - for (i = 0; i < depend_size; i++) { - SIBA_CC_WRITE32(scc, SIBA_CC_PMU_TABSEL, - depend[i].res); - switch (depend[i].task) { - case SIBA_CC_PMU_DEP_SET: - SIBA_CC_WRITE32(scc, SIBA_CC_PMU_DEPMSK, - depend[i].depend); - break; - case SIBA_CC_PMU_DEP_ADD: - SIBA_CC_SET32(scc, SIBA_CC_PMU_DEPMSK, - depend[i].depend); - break; - case SIBA_CC_PMU_DEP_REMOVE: - SIBA_CC_MASK32(scc, SIBA_CC_PMU_DEPMSK, - ~(depend[i].depend)); - break; - default: - KASSERT(0 == 1, - ("%s:%d: assertion failed", - __func__, __LINE__)); - } - } - } - - if (min) - SIBA_CC_WRITE32(scc, SIBA_CC_PMU_MINRES, min); - if (max) - SIBA_CC_WRITE32(scc, SIBA_CC_PMU_MAXRES, max); -} - -static void -siba_cc_power_init(struct siba_cc *scc) -{ - struct siba_softc *siba = scc->scc_dev->sd_bus; - int maxfreq; - - if (siba->siba_chipid == 0x4321) { - if (siba->siba_chiprev == 0) - SIBA_CC_WRITE32(scc, SIBA_CC_CHIPCTL, 0x3a4); - else if (siba->siba_chiprev == 1) - SIBA_CC_WRITE32(scc, SIBA_CC_CHIPCTL, 0xa4); - } - - if ((scc->scc_caps & SIBA_CC_CAPS_PWCTL) == 0) - return; - - if (scc->scc_dev->sd_id.sd_rev >= 10) - SIBA_CC_WRITE32(scc, SIBA_CC_CLKSYSCTL, - (SIBA_CC_READ32(scc, SIBA_CC_CLKSYSCTL) & - 0xffff) | 0x40000); - else { - maxfreq = siba_cc_clockfreq(scc, 1); - SIBA_CC_WRITE32(scc, SIBA_CC_PLLONDELAY, - (maxfreq * 150 + 999999) / 1000000); - SIBA_CC_WRITE32(scc, SIBA_CC_FREFSELDELAY, - (maxfreq * 15 + 999999) / 1000000); - } -} - -static void -siba_cc_powerup_delay(struct siba_cc *scc) -{ - struct siba_softc *siba = scc->scc_dev->sd_bus; - int min; - - if (siba->siba_type != SIBA_TYPE_PCI) - return; - - if (scc->scc_caps & SIBA_CC_CAPS_PMU) { - if ((siba->siba_chipid == 0x4312) || - (siba->siba_chipid == 0x4322) || - (siba->siba_chipid == 0x4328)) { - scc->scc_powerup_delay = 7000; - } else { - /* 0x4325 is marked as TODO */ - scc->scc_powerup_delay = 15000; - } - return; - } - - if (!(scc->scc_caps & SIBA_CC_CAPS_PWCTL)) - return; - - min = siba_cc_clockfreq(scc, 0); - scc->scc_powerup_delay = - howmany((SIBA_CC_READ32(scc, SIBA_CC_PLLONDELAY) + 2) * 1000000, - min); -} - -static int -siba_cc_clockfreq(struct siba_cc *scc, int max) -{ - enum siba_clksrc src; - int div = 1, limit = 0; - - src = siba_cc_clksrc(scc); - if (scc->scc_dev->sd_id.sd_rev < 6) { - div = (src == SIBA_CC_CLKSRC_PCI) ? 64 : - (src == SIBA_CC_CLKSRC_CRYSTAL) ? 32 : 1; - KASSERT(div != 1, - ("%s: unknown clock %d", __func__, src)); - } else if (scc->scc_dev->sd_id.sd_rev < 10) { - switch (src) { - case SIBA_CC_CLKSRC_CRYSTAL: - case SIBA_CC_CLKSRC_PCI: - div = ((SIBA_CC_READ32(scc, SIBA_CC_CLKSLOW) >> 16) + - 1) * 4; - break; - case SIBA_CC_CLKSRC_LOWPW: - break; - } - } else - div = ((SIBA_CC_READ32(scc, SIBA_CC_CLKSYSCTL) >> 16) + 1) * 4; - - switch (src) { - case SIBA_CC_CLKSRC_CRYSTAL: - limit = (max) ? 20200000 : 19800000; - break; - case SIBA_CC_CLKSRC_LOWPW: - limit = (max) ? 43000 : 25000; - break; - case SIBA_CC_CLKSRC_PCI: - limit = (max) ? 34000000 : 25000000; - break; - } - - return (limit / div); -} - -static void -siba_cc_pmu1_pll0_init(struct siba_cc *scc, uint32_t freq) -{ - struct siba_dev_softc *sd = scc->scc_dev; - struct siba_softc *siba = sd->sd_bus; - const struct siba_cc_pmu1_plltab *e = NULL; - uint32_t bufsth = 0, pll, pmu; - unsigned int i; - - KASSERT(freq == 0, ("%s:%d: assertion vail", __func__, __LINE__)); - if (siba->siba_chipid == 0x4312) { - scc->scc_pmu.freq = 20000; - return; - } - - e = siba_cc_pmu1_plltab_find(SIBA_CC_PMU1_DEFAULT_FREQ); - KASSERT(e != NULL, ("%s:%d: assertion vail", __func__, __LINE__)); - scc->scc_pmu.freq = e->freq; - - pmu = SIBA_CC_READ32(scc, SIBA_CC_PMUCTL); - if (SIBA_CC_PMUCTL_XF_VAL(pmu) == e->xf) - return; - - DPRINTF(siba, SIBA_DEBUG_PLL, "change PLL value to %u.%03u MHz\n", - (e->freq / 1000), (e->freq % 1000)); - - /* turn PLL off */ - switch (siba->siba_chipid) { - case 0x4325: - bufsth = 0x222222; - SIBA_CC_MASK32(scc, SIBA_CC_PMU_MINRES, - ~((1 << SIBA_CC_PMU_4325_BBPLL_PWR) | - (1 << SIBA_CC_PMU_4325_HT))); - SIBA_CC_MASK32(scc, SIBA_CC_PMU_MAXRES, - ~((1 << SIBA_CC_PMU_4325_BBPLL_PWR) | - (1 << SIBA_CC_PMU_4325_HT))); - break; - default: - KASSERT(0 == 1, - ("%s:%d: assertion failed", __func__, __LINE__)); - } - for (i = 0; i < 1500; i++) { - if (!(SIBA_CC_READ32(scc, SIBA_CC_CLKCTLSTATUS) & - SIBA_CC_CLKCTLSTATUS_HT)) - break; - DELAY(10); - } - if (SIBA_CC_READ32(scc, SIBA_CC_CLKCTLSTATUS) & SIBA_CC_CLKCTLSTATUS_HT) - device_printf(siba->siba_dev, "failed to turn PLL off!\n"); - - pll = siba_cc_pll_read(scc, SIBA_CC_PMU1_PLL0); - pll &= ~(SIBA_CC_PMU1_PLL0_P1DIV | SIBA_CC_PMU1_PLL0_P2DIV); - pll |= ((uint32_t)e->p1div << 20) & SIBA_CC_PMU1_PLL0_P1DIV; - pll |= ((uint32_t)e->p2div << 24) & SIBA_CC_PMU1_PLL0_P2DIV; - siba_cc_pll_write(scc, SIBA_CC_PMU1_PLL0, pll); - - pll = siba_cc_pll_read(scc, SIBA_CC_PMU1_PLL2); - pll &= ~(SIBA_CC_PMU1_PLL2_NDIVINT | SIBA_CC_PMU1_PLL2_NDIVMODE); - pll |= ((uint32_t)e->ndiv_int << 20) & SIBA_CC_PMU1_PLL2_NDIVINT; - pll |= (1 << 17) & SIBA_CC_PMU1_PLL2_NDIVMODE; - siba_cc_pll_write(scc, SIBA_CC_PMU1_PLL2, pll); - - pll = siba_cc_pll_read(scc, SIBA_CC_PMU1_PLL3); - pll &= ~SIBA_CC_PMU1_PLL3_NDIVFRAC; - pll |= ((uint32_t)e->ndiv_frac << 0) & SIBA_CC_PMU1_PLL3_NDIVFRAC; - siba_cc_pll_write(scc, SIBA_CC_PMU1_PLL3, pll); - - if (bufsth) { - pll = siba_cc_pll_read(scc, SIBA_CC_PMU1_PLL5); - pll &= ~SIBA_CC_PMU1_PLL5_CLKDRV; - pll |= (bufsth << 8) & SIBA_CC_PMU1_PLL5_CLKDRV; - siba_cc_pll_write(scc, SIBA_CC_PMU1_PLL5, pll); - } - - pmu = SIBA_CC_READ32(scc, SIBA_CC_PMUCTL); - pmu &= ~(SIBA_CC_PMUCTL_ILP | SIBA_CC_PMUCTL_XF); - pmu |= ((((uint32_t)e->freq + 127) / 128 - 1) << 16) & - SIBA_CC_PMUCTL_ILP; - pmu |= ((uint32_t)e->xf << 2) & SIBA_CC_PMUCTL_XF; - SIBA_CC_WRITE32(scc, SIBA_CC_PMUCTL, pmu); -} - -static void -siba_cc_pmu0_pll0_init(struct siba_cc *scc, uint32_t xtalfreq) -{ - struct siba_dev_softc *sd = scc->scc_dev; - struct siba_softc *siba = sd->sd_bus; - const struct siba_cc_pmu0_plltab *e = NULL; - uint32_t pmu, tmp, pll; - unsigned int i; - - if ((siba->siba_chipid == 0x5354) && !xtalfreq) - xtalfreq = 25000; - if (xtalfreq) - e = siba_cc_pmu0_plltab_findentry(xtalfreq); - if (!e) - e = siba_cc_pmu0_plltab_findentry( - SIBA_CC_PMU0_DEFAULT_XTALFREQ); - KASSERT(e != NULL, ("%s:%d: fail", __func__, __LINE__)); - xtalfreq = e->freq; - scc->scc_pmu.freq = e->freq; - - pmu = SIBA_CC_READ32(scc, SIBA_CC_PMUCTL); - if (((pmu & SIBA_CC_PMUCTL_XF) >> 2) == e->xf) - return; - - DPRINTF(siba, SIBA_DEBUG_PLL, "change PLL value to %u.%03u MHz\n", - (xtalfreq / 1000), (xtalfreq % 1000)); - - KASSERT(siba->siba_chipid == 0x4328 || siba->siba_chipid == 0x5354, - ("%s:%d: fail", __func__, __LINE__)); - - switch (siba->siba_chipid) { - case 0x4328: - SIBA_CC_MASK32(scc, SIBA_CC_PMU_MINRES, - ~(1 << SIBA_CC_PMU_4328_BB_PLL_PU)); - SIBA_CC_MASK32(scc, SIBA_CC_PMU_MAXRES, - ~(1 << SIBA_CC_PMU_4328_BB_PLL_PU)); - break; - case 0x5354: - SIBA_CC_MASK32(scc, SIBA_CC_PMU_MINRES, - ~(1 << SIBA_CC_PMU_5354_BB_PLL_PU)); - SIBA_CC_MASK32(scc, SIBA_CC_PMU_MAXRES, - ~(1 << SIBA_CC_PMU_5354_BB_PLL_PU)); - break; - } - for (i = 1500; i; i--) { - tmp = SIBA_CC_READ32(scc, SIBA_CC_CLKCTLSTATUS); - if (!(tmp & SIBA_CC_CLKCTLSTATUS_HT)) - break; - DELAY(10); - } - tmp = SIBA_CC_READ32(scc, SIBA_CC_CLKCTLSTATUS); - if (tmp & SIBA_CC_CLKCTLSTATUS_HT) - device_printf(siba->siba_dev, "failed to turn PLL off!\n"); - - /* set PDIV */ - pll = siba_cc_pll_read(scc, SIBA_CC_PMU0_PLL0); - if (xtalfreq >= SIBA_CC_PMU0_PLL0_PDIV_FREQ) - pll |= SIBA_CC_PMU0_PLL0_PDIV_MSK; - else - pll &= ~SIBA_CC_PMU0_PLL0_PDIV_MSK; - siba_cc_pll_write(scc, SIBA_CC_PMU0_PLL0, pll); - - /* set WILD */ - pll = siba_cc_pll_read(scc, SIBA_CC_PMU0_PLL1); - pll &= ~(SIBA_CC_PMU0_PLL1_STOPMOD | SIBA_CC_PMU0_PLL1_IMSK | - SIBA_CC_PMU0_PLL1_FMSK); - pll |= ((uint32_t)e->wb_int << 28) & SIBA_CC_PMU0_PLL1_IMSK; - pll |= ((uint32_t)e->wb_frac << 8) & SIBA_CC_PMU0_PLL1_FMSK; - if (e->wb_frac == 0) - pll |= SIBA_CC_PMU0_PLL1_STOPMOD; - siba_cc_pll_write(scc, SIBA_CC_PMU0_PLL1, pll); - - /* set WILD */ - pll = siba_cc_pll_read(scc, SIBA_CC_PMU0_PLL2); - pll &= ~SIBA_CC_PMU0_PLL2_IMSKHI; - pll |= (((uint32_t)e->wb_int >> 4) << 0) & SIBA_CC_PMU0_PLL2_IMSKHI; - siba_cc_pll_write(scc, SIBA_CC_PMU0_PLL2, pll); - - /* set freq and divisor. */ - pmu = SIBA_CC_READ32(scc, SIBA_CC_PMUCTL); - pmu &= ~SIBA_CC_PMUCTL_ILP; - pmu |= (((xtalfreq + 127) / 128 - 1) << 16) & SIBA_CC_PMUCTL_ILP; - pmu &= ~SIBA_CC_PMUCTL_XF; - pmu |= ((uint32_t)e->xf << 2) & SIBA_CC_PMUCTL_XF; - SIBA_CC_WRITE32(scc, SIBA_CC_PMUCTL, pmu); -} - -static enum siba_clksrc -siba_cc_clksrc(struct siba_cc *scc) -{ - struct siba_dev_softc *sd = scc->scc_dev; - struct siba_softc *siba = sd->sd_bus; - - if (sd->sd_id.sd_rev < 6) { - if (siba->siba_type == SIBA_TYPE_PCI) { - if (pci_read_config(siba->siba_dev, SIBA_GPIO_OUT, 4) & - 0x10) - return (SIBA_CC_CLKSRC_PCI); - return (SIBA_CC_CLKSRC_CRYSTAL); - } - if (siba->siba_type == SIBA_TYPE_SSB || - siba->siba_type == SIBA_TYPE_PCMCIA) - return (SIBA_CC_CLKSRC_CRYSTAL); - } - if (sd->sd_id.sd_rev < 10) { - switch (SIBA_CC_READ32(scc, SIBA_CC_CLKSLOW) & 0x7) { - case 0: - return (SIBA_CC_CLKSRC_LOWPW); - case 1: - return (SIBA_CC_CLKSRC_CRYSTAL); - case 2: - return (SIBA_CC_CLKSRC_PCI); - default: - break; - } - } - - return (SIBA_CC_CLKSRC_CRYSTAL); -} - -static const struct siba_cc_pmu1_plltab * -siba_cc_pmu1_plltab_find(uint32_t crystalfreq) -{ - const struct siba_cc_pmu1_plltab *e; - unsigned int i; - - for (i = 0; i < N(siba_cc_pmu1_plltab); i++) { - e = &siba_cc_pmu1_plltab[i]; - if (crystalfreq == e->freq) - return (e); - } - - return (NULL); -} - -static uint32_t -siba_cc_pll_read(struct siba_cc *scc, uint32_t offset) -{ - - SIBA_CC_WRITE32(scc, SIBA_CC_PLLCTL_ADDR, offset); - return (SIBA_CC_READ32(scc, SIBA_CC_PLLCTL_DATA)); -} - -static void -siba_cc_pll_write(struct siba_cc *scc, uint32_t offset, uint32_t value) -{ - - SIBA_CC_WRITE32(scc, SIBA_CC_PLLCTL_ADDR, offset); - SIBA_CC_WRITE32(scc, SIBA_CC_PLLCTL_DATA, value); -} - -static const struct siba_cc_pmu0_plltab * -siba_cc_pmu0_plltab_findentry(uint32_t crystalfreq) -{ - const struct siba_cc_pmu0_plltab *e; - unsigned int i; - - for (i = 0; i < N(siba_cc_pmu0_plltab); i++) { - e = &siba_cc_pmu0_plltab[i]; - if (e->freq == crystalfreq) - return (e); - } - - return (NULL); -} - -static int -siba_pci_sprom(struct siba_softc *siba, struct siba_sprom *sprom) -{ - int error = ENOMEM; - uint16_t *buf; - - buf = malloc(SIBA_SPROMSIZE_R123 * sizeof(uint16_t), - M_DEVBUF, M_NOWAIT | M_ZERO); - if (buf == NULL) - return (ENOMEM); - siba_sprom_read(siba, buf, SIBA_SPROMSIZE_R123); - error = sprom_check_crc(buf, siba->siba_spromsize); - if (error) { - free(buf, M_DEVBUF); - buf = malloc(SIBA_SPROMSIZE_R4 * sizeof(uint16_t), - M_DEVBUF, M_NOWAIT | M_ZERO); - if (buf == NULL) - return (ENOMEM); - siba_sprom_read(siba, buf, SIBA_SPROMSIZE_R4); - error = sprom_check_crc(buf, siba->siba_spromsize); - if (error) - device_printf(siba->siba_dev, "warn: bad SPROM CRC\n"); - } - - bzero(sprom, sizeof(*sprom)); - - sprom->rev = buf[siba->siba_spromsize - 1] & 0x00FF; - DPRINTF(siba, SIBA_DEBUG_SPROM, "SPROM rev %d\n", - sprom->rev); - memset(sprom->mac_eth, 0xff, 6); - memset(sprom->mac_80211a, 0xff, 6); - if ((siba->siba_chipid & 0xff00) == 0x4400) { - sprom->rev = 1; - siba_sprom_r123(sprom, buf); - } else if (siba->siba_chipid == 0x4321) { - sprom->rev = 4; - siba_sprom_r45(sprom, buf); - } else { - switch (sprom->rev) { - case 1: - case 2: - case 3: - siba_sprom_r123(sprom, buf); - break; - case 4: - case 5: - siba_sprom_r45(sprom, buf); - break; - case 8: - siba_sprom_r8(sprom, buf); - break; - default: - device_printf(siba->siba_dev, - "unknown SPROM revision %d.\n", sprom->rev); - siba_sprom_r123(sprom, buf); - } - } - - if (sprom->bf_lo == 0xffff) - sprom->bf_lo = 0; - if (sprom->bf_hi == 0xffff) - sprom->bf_hi = 0; - - free(buf, M_DEVBUF); - return (error); -} - -static int -siba_sprom_read(struct siba_softc *siba, uint16_t *sprom, uint16_t len) -{ - int i; - - for (i = 0; i < len; i++) - sprom[i] = SIBA_READ_2(siba, SIBA_SPROM_BASE + (i * 2)); - - siba->siba_spromsize = len; - return (0); -} - -static int -sprom_check_crc(const uint16_t *sprom, size_t size) -{ - int word; - uint8_t crc0, crc1 = 0xff; - - crc0 = (sprom[size - 1] & SIBA_SPROM_REV_CRC) >> 8; - for (word = 0; word < size - 1; word++) { - crc1 = siba_crc8(crc1, sprom[word] & 0x00ff); - crc1 = siba_crc8(crc1, (sprom[word] & 0xff00) >> 8); - } - crc1 = siba_crc8(crc1, sprom[size - 1] & 0x00ff); - crc1 ^= 0xff; - - return ((crc0 != crc1) ? EPROTO : 0); -} - -static uint8_t -siba_crc8(uint8_t crc, uint8_t data) -{ - static const uint8_t ct[] = { - 0x00, 0xf7, 0xb9, 0x4e, 0x25, 0xd2, 0x9c, 0x6b, - 0x4a, 0xbd, 0xf3, 0x04, 0x6f, 0x98, 0xd6, 0x21, - 0x94, 0x63, 0x2d, 0xda, 0xb1, 0x46, 0x08, 0xff, - 0xde, 0x29, 0x67, 0x90, 0xfb, 0x0c, 0x42, 0xb5, - 0x7f, 0x88, 0xc6, 0x31, 0x5a, 0xad, 0xe3, 0x14, - 0x35, 0xc2, 0x8c, 0x7b, 0x10, 0xe7, 0xa9, 0x5e, - 0xeb, 0x1c, 0x52, 0xa5, 0xce, 0x39, 0x77, 0x80, - 0xa1, 0x56, 0x18, 0xef, 0x84, 0x73, 0x3d, 0xca, - 0xfe, 0x09, 0x47, 0xb0, 0xdb, 0x2c, 0x62, 0x95, - 0xb4, 0x43, 0x0d, 0xfa, 0x91, 0x66, 0x28, 0xdf, - 0x6a, 0x9d, 0xd3, 0x24, 0x4f, 0xb8, 0xf6, 0x01, - 0x20, 0xd7, 0x99, 0x6e, 0x05, 0xf2, 0xbc, 0x4b, - 0x81, 0x76, 0x38, 0xcf, 0xa4, 0x53, 0x1d, 0xea, - 0xcb, 0x3c, 0x72, 0x85, 0xee, 0x19, 0x57, 0xa0, - 0x15, 0xe2, 0xac, 0x5b, 0x30, 0xc7, 0x89, 0x7e, - 0x5f, 0xa8, 0xe6, 0x11, 0x7a, 0x8d, 0xc3, 0x34, - 0xab, 0x5c, 0x12, 0xe5, 0x8e, 0x79, 0x37, 0xc0, - 0xe1, 0x16, 0x58, 0xaf, 0xc4, 0x33, 0x7d, 0x8a, - 0x3f, 0xc8, 0x86, 0x71, 0x1a, 0xed, 0xa3, 0x54, - 0x75, 0x82, 0xcc, 0x3b, 0x50, 0xa7, 0xe9, 0x1e, - 0xd4, 0x23, 0x6d, 0x9a, 0xf1, 0x06, 0x48, 0xbf, - 0x9e, 0x69, 0x27, 0xd0, 0xbb, 0x4c, 0x02, 0xf5, - 0x40, 0xb7, 0xf9, 0x0e, 0x65, 0x92, 0xdc, 0x2b, - 0x0a, 0xfd, 0xb3, 0x44, 0x2f, 0xd8, 0x96, 0x61, - 0x55, 0xa2, 0xec, 0x1b, 0x70, 0x87, 0xc9, 0x3e, - 0x1f, 0xe8, 0xa6, 0x51, 0x3a, 0xcd, 0x83, 0x74, - 0xc1, 0x36, 0x78, 0x8f, 0xe4, 0x13, 0x5d, 0xaa, - 0x8b, 0x7c, 0x32, 0xc5, 0xae, 0x59, 0x17, 0xe0, - 0x2a, 0xdd, 0x93, 0x64, 0x0f, 0xf8, 0xb6, 0x41, - 0x60, 0x97, 0xd9, 0x2e, 0x45, 0xb2, 0xfc, 0x0b, - 0xbe, 0x49, 0x07, 0xf0, 0x9b, 0x6c, 0x22, 0xd5, - 0xf4, 0x03, 0x4d, 0xba, 0xd1, 0x26, 0x68, 0x9f, - }; - return (ct[crc ^ data]); -} - -#define SIBA_LOWEST_SET_BIT(__mask) ((((__mask) - 1) & (__mask)) ^ (__mask)) -#define SIBA_OFFSET(offset) \ - (((offset) - SIBA_SPROM_BASE) / sizeof(uint16_t)) -#define SIBA_SHIFTOUT_SUB(__x, __mask) \ - (((__x) & (__mask)) / SIBA_LOWEST_SET_BIT(__mask)) -#define SIBA_SHIFTOUT(_var, _offset, _mask) \ - out->_var = SIBA_SHIFTOUT_SUB(in[SIBA_OFFSET(_offset)], (_mask)) -#define SIBA_SHIFTOUT_4(_var, _offset, _mask, _shift) \ - out->_var = ((((uint32_t)in[SIBA_OFFSET((_offset)+2)] << 16 | \ - in[SIBA_OFFSET(_offset)]) & (_mask)) >> (_shift)) - -static void -siba_sprom_r123(struct siba_sprom *out, const uint16_t *in) -{ - int i; - uint16_t v; - int8_t gain; - uint16_t loc[3]; - - if (out->rev == 3) - loc[0] = SIBA_SPROM3_MAC_80211BG; - else { - loc[0] = SIBA_SPROM1_MAC_80211BG; - loc[1] = SIBA_SPROM1_MAC_ETH; - loc[2] = SIBA_SPROM1_MAC_80211A; - } - for (i = 0; i < 3; i++) { - v = in[SIBA_OFFSET(loc[0]) + i]; - *(((uint16_t *)out->mac_80211bg) + i) = htobe16(v); - } - if (out->rev < 3) { - for (i = 0; i < 3; i++) { - v = in[SIBA_OFFSET(loc[1]) + i]; - *(((uint16_t *)out->mac_eth) + i) = htobe16(v); - } - for (i = 0; i < 3; i++) { - v = in[SIBA_OFFSET(loc[2]) + i]; - *(((uint16_t *)out->mac_80211a) + i) = htobe16(v); - } - } - SIBA_SHIFTOUT(mii_eth0, SIBA_SPROM1_ETHPHY, - SIBA_SPROM1_ETHPHY_MII_ETH0); - SIBA_SHIFTOUT(mii_eth1, SIBA_SPROM1_ETHPHY, - SIBA_SPROM1_ETHPHY_MII_ETH1); - SIBA_SHIFTOUT(mdio_eth0, SIBA_SPROM1_ETHPHY, - SIBA_SPROM1_ETHPHY_MDIO_ETH0); - SIBA_SHIFTOUT(mdio_eth1, SIBA_SPROM1_ETHPHY, - SIBA_SPROM1_ETHPHY_MDIO_ETH1); - SIBA_SHIFTOUT(brev, SIBA_SPROM1_BOARDINFO, SIBA_SPROM1_BOARDINFO_BREV); - SIBA_SHIFTOUT(ccode, SIBA_SPROM1_BOARDINFO, - SIBA_SPROM1_BOARDINFO_CCODE); - SIBA_SHIFTOUT(ant_a, SIBA_SPROM1_BOARDINFO, SIBA_SPROM1_BOARDINFO_ANTA); - SIBA_SHIFTOUT(ant_bg, SIBA_SPROM1_BOARDINFO, - SIBA_SPROM1_BOARDINFO_ANTBG); - SIBA_SHIFTOUT(pa0b0, SIBA_SPROM1_PA0B0, 0xffff); - SIBA_SHIFTOUT(pa0b1, SIBA_SPROM1_PA0B1, 0xffff); - SIBA_SHIFTOUT(pa0b2, SIBA_SPROM1_PA0B2, 0xffff); - SIBA_SHIFTOUT(pa1b0, SIBA_SPROM1_PA1B0, 0xffff); - SIBA_SHIFTOUT(pa1b1, SIBA_SPROM1_PA1B1, 0xffff); - SIBA_SHIFTOUT(pa1b2, SIBA_SPROM1_PA1B2, 0xffff); - SIBA_SHIFTOUT(gpio0, SIBA_SPROM1_GPIOA, SIBA_SPROM1_GPIOA_P0); - SIBA_SHIFTOUT(gpio1, SIBA_SPROM1_GPIOA, SIBA_SPROM1_GPIOA_P1); - SIBA_SHIFTOUT(gpio2, SIBA_SPROM1_GPIOB, SIBA_SPROM1_GPIOB_P2); - SIBA_SHIFTOUT(gpio3, SIBA_SPROM1_GPIOB, SIBA_SPROM1_GPIOB_P3); - - SIBA_SHIFTOUT(maxpwr_a, SIBA_SPROM1_MAXPWR, SIBA_SPROM1_MAXPWR_A); - SIBA_SHIFTOUT(maxpwr_bg, SIBA_SPROM1_MAXPWR, SIBA_SPROM1_MAXPWR_BG); - SIBA_SHIFTOUT(tssi_a, SIBA_SPROM1_TSSI, SIBA_SPROM1_TSSI_A); - SIBA_SHIFTOUT(tssi_bg, SIBA_SPROM1_TSSI, SIBA_SPROM1_TSSI_BG); - SIBA_SHIFTOUT(bf_lo, SIBA_SPROM1_BFLOW, 0xffff); - if (out->rev >= 2) - SIBA_SHIFTOUT(bf_hi, SIBA_SPROM2_BFHIGH, 0xffff); - - /* antenna gain */ - gain = siba_sprom_r123_antgain(out->rev, in, SIBA_SPROM1_AGAIN_BG, 0); - out->again.ghz24.a0 = out->again.ghz24.a1 = gain; - out->again.ghz24.a2 = out->again.ghz24.a3 = gain; - gain = siba_sprom_r123_antgain(out->rev, in, SIBA_SPROM1_AGAIN_A, 8); - out->again.ghz5.a0 = out->again.ghz5.a1 = gain; - out->again.ghz5.a2 = out->again.ghz5.a3 = gain; -} - -static void -siba_sprom_r458(struct siba_sprom *out, const uint16_t *in) -{ - - SIBA_SHIFTOUT(txpid2g[0], SIBA_SPROM4_TXPID2G01, - SIBA_SPROM4_TXPID2G0); - SIBA_SHIFTOUT(txpid2g[1], SIBA_SPROM4_TXPID2G01, - SIBA_SPROM4_TXPID2G1); - SIBA_SHIFTOUT(txpid2g[2], SIBA_SPROM4_TXPID2G23, - SIBA_SPROM4_TXPID2G2); - SIBA_SHIFTOUT(txpid2g[3], SIBA_SPROM4_TXPID2G23, - SIBA_SPROM4_TXPID2G3); - - SIBA_SHIFTOUT(txpid5gl[0], SIBA_SPROM4_TXPID5GL01, - SIBA_SPROM4_TXPID5GL0); - SIBA_SHIFTOUT(txpid5gl[1], SIBA_SPROM4_TXPID5GL01, - SIBA_SPROM4_TXPID5GL1); - SIBA_SHIFTOUT(txpid5gl[2], SIBA_SPROM4_TXPID5GL23, - SIBA_SPROM4_TXPID5GL2); - SIBA_SHIFTOUT(txpid5gl[3], SIBA_SPROM4_TXPID5GL23, - SIBA_SPROM4_TXPID5GL3); - - SIBA_SHIFTOUT(txpid5g[0], SIBA_SPROM4_TXPID5G01, - SIBA_SPROM4_TXPID5G0); - SIBA_SHIFTOUT(txpid5g[1], SIBA_SPROM4_TXPID5G01, - SIBA_SPROM4_TXPID5G1); - SIBA_SHIFTOUT(txpid5g[2], SIBA_SPROM4_TXPID5G23, - SIBA_SPROM4_TXPID5G2); - SIBA_SHIFTOUT(txpid5g[3], SIBA_SPROM4_TXPID5G23, - SIBA_SPROM4_TXPID5G3); - - SIBA_SHIFTOUT(txpid5gh[0], SIBA_SPROM4_TXPID5GH01, - SIBA_SPROM4_TXPID5GH0); - SIBA_SHIFTOUT(txpid5gh[1], SIBA_SPROM4_TXPID5GH01, - SIBA_SPROM4_TXPID5GH1); - SIBA_SHIFTOUT(txpid5gh[2], SIBA_SPROM4_TXPID5GH23, - SIBA_SPROM4_TXPID5GH2); - SIBA_SHIFTOUT(txpid5gh[3], SIBA_SPROM4_TXPID5GH23, - SIBA_SPROM4_TXPID5GH3); -} - -static void -siba_sprom_r45(struct siba_sprom *out, const uint16_t *in) -{ - int i; - uint16_t v; - uint16_t mac_80211bg_offset; - const uint16_t pwr_info_offset[] = { - SIBA_SPROM4_PWR_INFO_CORE0, SIBA_SPROM4_PWR_INFO_CORE1, - SIBA_SPROM4_PWR_INFO_CORE2, SIBA_SPROM4_PWR_INFO_CORE3 - }; - - if (out->rev == 4) - mac_80211bg_offset = SIBA_SPROM4_MAC_80211BG; - else - mac_80211bg_offset = SIBA_SPROM5_MAC_80211BG; - for (i = 0; i < 3; i++) { - v = in[SIBA_OFFSET(mac_80211bg_offset) + i]; - *(((uint16_t *)out->mac_80211bg) + i) = htobe16(v); - } - SIBA_SHIFTOUT(mii_eth0, SIBA_SPROM4_ETHPHY, SIBA_SPROM4_ETHPHY_ET0A); - SIBA_SHIFTOUT(mii_eth1, SIBA_SPROM4_ETHPHY, SIBA_SPROM4_ETHPHY_ET1A); - if (out->rev == 4) { - SIBA_SHIFTOUT(ccode, SIBA_SPROM4_CCODE, 0xffff); - SIBA_SHIFTOUT(bf_lo, SIBA_SPROM4_BFLOW, 0xffff); - SIBA_SHIFTOUT(bf_hi, SIBA_SPROM4_BFHIGH, 0xffff); - } else { - SIBA_SHIFTOUT(ccode, SIBA_SPROM5_CCODE, 0xffff); - SIBA_SHIFTOUT(bf_lo, SIBA_SPROM5_BFLOW, 0xffff); - SIBA_SHIFTOUT(bf_hi, SIBA_SPROM5_BFHIGH, 0xffff); - } - SIBA_SHIFTOUT(ant_a, SIBA_SPROM4_ANTAVAIL, SIBA_SPROM4_ANTAVAIL_A); - SIBA_SHIFTOUT(ant_bg, SIBA_SPROM4_ANTAVAIL, SIBA_SPROM4_ANTAVAIL_BG); - SIBA_SHIFTOUT(maxpwr_bg, SIBA_SPROM4_MAXP_BG, SIBA_SPROM4_MAXP_BG_MASK); - SIBA_SHIFTOUT(tssi_bg, SIBA_SPROM4_MAXP_BG, SIBA_SPROM4_TSSI_BG); - SIBA_SHIFTOUT(maxpwr_a, SIBA_SPROM4_MAXP_A, SIBA_SPROM4_MAXP_A_MASK); - SIBA_SHIFTOUT(tssi_a, SIBA_SPROM4_MAXP_A, SIBA_SPROM4_TSSI_A); - if (out->rev == 4) { - SIBA_SHIFTOUT(gpio0, SIBA_SPROM4_GPIOA, SIBA_SPROM4_GPIOA_P0); - SIBA_SHIFTOUT(gpio1, SIBA_SPROM4_GPIOA, SIBA_SPROM4_GPIOA_P1); - SIBA_SHIFTOUT(gpio2, SIBA_SPROM4_GPIOB, SIBA_SPROM4_GPIOB_P2); - SIBA_SHIFTOUT(gpio3, SIBA_SPROM4_GPIOB, SIBA_SPROM4_GPIOB_P3); - } else { - SIBA_SHIFTOUT(gpio0, SIBA_SPROM5_GPIOA, SIBA_SPROM5_GPIOA_P0); - SIBA_SHIFTOUT(gpio1, SIBA_SPROM5_GPIOA, SIBA_SPROM5_GPIOA_P1); - SIBA_SHIFTOUT(gpio2, SIBA_SPROM5_GPIOB, SIBA_SPROM5_GPIOB_P2); - SIBA_SHIFTOUT(gpio3, SIBA_SPROM5_GPIOB, SIBA_SPROM5_GPIOB_P3); - } - - /* antenna gain */ - SIBA_SHIFTOUT(again.ghz24.a0, SIBA_SPROM4_AGAIN01, SIBA_SPROM4_AGAIN0); - SIBA_SHIFTOUT(again.ghz24.a1, SIBA_SPROM4_AGAIN01, SIBA_SPROM4_AGAIN1); - SIBA_SHIFTOUT(again.ghz24.a2, SIBA_SPROM4_AGAIN23, SIBA_SPROM4_AGAIN2); - SIBA_SHIFTOUT(again.ghz24.a3, SIBA_SPROM4_AGAIN23, SIBA_SPROM4_AGAIN3); - bcopy(&out->again.ghz24, &out->again.ghz5, sizeof(out->again.ghz5)); - - /* Extract core power info */ - for (i = 0; i < nitems(pwr_info_offset); i++) { - uint16_t o = pwr_info_offset[i]; - - SIBA_SHIFTOUT(core_pwr_info[i].itssi_2g, o + SIBA_SPROM4_2G_MAXP_ITSSI, - SIBA_SPROM4_2G_ITSSI); - SIBA_SHIFTOUT(core_pwr_info[i].maxpwr_2g, o + SIBA_SPROM4_2G_MAXP_ITSSI, - SIBA_SPROM4_2G_MAXP); - - SIBA_SHIFTOUT(core_pwr_info[i].pa_2g[0], o + SIBA_SPROM4_2G_PA_0, ~0); - SIBA_SHIFTOUT(core_pwr_info[i].pa_2g[1], o + SIBA_SPROM4_2G_PA_1, ~0); - SIBA_SHIFTOUT(core_pwr_info[i].pa_2g[2], o + SIBA_SPROM4_2G_PA_2, ~0); - SIBA_SHIFTOUT(core_pwr_info[i].pa_2g[3], o + SIBA_SPROM4_2G_PA_3, ~0); - - SIBA_SHIFTOUT(core_pwr_info[i].itssi_5g, o + SIBA_SPROM4_5G_MAXP_ITSSI, - SIBA_SPROM4_5G_ITSSI); - SIBA_SHIFTOUT(core_pwr_info[i].maxpwr_5g, o + SIBA_SPROM4_5G_MAXP_ITSSI, - SIBA_SPROM4_5G_MAXP); - SIBA_SHIFTOUT(core_pwr_info[i].maxpwr_5gh, o + SIBA_SPROM4_5GHL_MAXP, - SIBA_SPROM4_5GH_MAXP); - SIBA_SHIFTOUT(core_pwr_info[i].maxpwr_5gl, o + SIBA_SPROM4_5GHL_MAXP, - SIBA_SPROM4_5GL_MAXP); - - SIBA_SHIFTOUT(core_pwr_info[i].pa_5gl[0], o + SIBA_SPROM4_5GL_PA_0, ~0); - SIBA_SHIFTOUT(core_pwr_info[i].pa_5gl[1], o + SIBA_SPROM4_5GL_PA_1, ~0); - SIBA_SHIFTOUT(core_pwr_info[i].pa_5gl[2], o + SIBA_SPROM4_5GL_PA_2, ~0); - SIBA_SHIFTOUT(core_pwr_info[i].pa_5gl[3], o + SIBA_SPROM4_5GL_PA_3, ~0); - SIBA_SHIFTOUT(core_pwr_info[i].pa_5g[0], o + SIBA_SPROM4_5G_PA_0, ~0); - SIBA_SHIFTOUT(core_pwr_info[i].pa_5g[1], o + SIBA_SPROM4_5G_PA_1, ~0); - SIBA_SHIFTOUT(core_pwr_info[i].pa_5g[2], o + SIBA_SPROM4_5G_PA_2, ~0); - SIBA_SHIFTOUT(core_pwr_info[i].pa_5g[3], o + SIBA_SPROM4_5G_PA_3, ~0); - SIBA_SHIFTOUT(core_pwr_info[i].pa_5gh[0], o + SIBA_SPROM4_5GH_PA_0, ~0); - SIBA_SHIFTOUT(core_pwr_info[i].pa_5gh[1], o + SIBA_SPROM4_5GH_PA_1, ~0); - SIBA_SHIFTOUT(core_pwr_info[i].pa_5gh[2], o + SIBA_SPROM4_5GH_PA_2, ~0); - SIBA_SHIFTOUT(core_pwr_info[i].pa_5gh[3], o + SIBA_SPROM4_5GH_PA_3, ~0); - } - - siba_sprom_r458(out, in); -} - -static void -siba_sprom_r8(struct siba_sprom *out, const uint16_t *in) -{ - int i; - uint16_t v; - uint16_t pwr_info_offset[] = { - SIBA_SROM8_PWR_INFO_CORE0, SIBA_SROM8_PWR_INFO_CORE1, - SIBA_SROM8_PWR_INFO_CORE2, SIBA_SROM8_PWR_INFO_CORE3 - }; - - for (i = 0; i < 3; i++) { - v = in[SIBA_OFFSET(SIBA_SPROM8_MAC_80211BG) + i]; - *(((uint16_t *)out->mac_80211bg) + i) = htobe16(v); - } - SIBA_SHIFTOUT(ccode, SIBA_SPROM8_CCODE, 0xffff); - SIBA_SHIFTOUT(bf_lo, SIBA_SPROM8_BFLOW, 0xffff); - SIBA_SHIFTOUT(bf_hi, SIBA_SPROM8_BFHIGH, 0xffff); - SIBA_SHIFTOUT(bf2_lo, SIBA_SPROM8_BFL2LO, 0xffff); - SIBA_SHIFTOUT(bf2_hi, SIBA_SPROM8_BFL2HI, 0xffff); - SIBA_SHIFTOUT(ant_a, SIBA_SPROM8_ANTAVAIL, SIBA_SPROM8_ANTAVAIL_A); - SIBA_SHIFTOUT(ant_bg, SIBA_SPROM8_ANTAVAIL, SIBA_SPROM8_ANTAVAIL_BG); - SIBA_SHIFTOUT(maxpwr_bg, SIBA_SPROM8_MAXP_BG, SIBA_SPROM8_MAXP_BG_MASK); - SIBA_SHIFTOUT(tssi_bg, SIBA_SPROM8_MAXP_BG, SIBA_SPROM8_TSSI_BG); - SIBA_SHIFTOUT(maxpwr_a, SIBA_SPROM8_MAXP_A, SIBA_SPROM8_MAXP_A_MASK); - SIBA_SHIFTOUT(tssi_a, SIBA_SPROM8_MAXP_A, SIBA_SPROM8_TSSI_A); - SIBA_SHIFTOUT(maxpwr_ah, SIBA_SPROM8_MAXP_AHL, - SIBA_SPROM8_MAXP_AH_MASK); - SIBA_SHIFTOUT(maxpwr_al, SIBA_SPROM8_MAXP_AHL, - SIBA_SPROM8_MAXP_AL_MASK); - SIBA_SHIFTOUT(gpio0, SIBA_SPROM8_GPIOA, SIBA_SPROM8_GPIOA_P0); - SIBA_SHIFTOUT(gpio1, SIBA_SPROM8_GPIOA, SIBA_SPROM8_GPIOA_P1); - SIBA_SHIFTOUT(gpio2, SIBA_SPROM8_GPIOB, SIBA_SPROM8_GPIOB_P2); - SIBA_SHIFTOUT(gpio3, SIBA_SPROM8_GPIOB, SIBA_SPROM8_GPIOB_P3); - SIBA_SHIFTOUT(tri2g, SIBA_SPROM8_TRI25G, SIBA_SPROM8_TRI2G); - SIBA_SHIFTOUT(tri5g, SIBA_SPROM8_TRI25G, SIBA_SPROM8_TRI5G); - SIBA_SHIFTOUT(tri5gl, SIBA_SPROM8_TRI5GHL, SIBA_SPROM8_TRI5GL); - SIBA_SHIFTOUT(tri5gh, SIBA_SPROM8_TRI5GHL, SIBA_SPROM8_TRI5GH); - SIBA_SHIFTOUT(rxpo2g, SIBA_SPROM8_RXPO, SIBA_SPROM8_RXPO2G); - SIBA_SHIFTOUT(rxpo5g, SIBA_SPROM8_RXPO, SIBA_SPROM8_RXPO5G); - - SIBA_SHIFTOUT(rssismf2g, SIBA_SPROM8_RSSIPARM2G, SIBA_SPROM8_RSSISMF2G); - SIBA_SHIFTOUT(rssismc2g, SIBA_SPROM8_RSSIPARM2G, SIBA_SPROM8_RSSISMC2G); - SIBA_SHIFTOUT(rssisav2g, SIBA_SPROM8_RSSIPARM2G, SIBA_SPROM8_RSSISAV2G); - SIBA_SHIFTOUT(bxa2g, SIBA_SPROM8_RSSIPARM2G, SIBA_SPROM8_BXA2G); - SIBA_SHIFTOUT(rssismf5g, SIBA_SPROM8_RSSIPARM5G, SIBA_SPROM8_RSSISMF5G); - SIBA_SHIFTOUT(rssismc5g, SIBA_SPROM8_RSSIPARM5G, SIBA_SPROM8_RSSISMC5G); - SIBA_SHIFTOUT(rssisav5g, SIBA_SPROM8_RSSIPARM5G, SIBA_SPROM8_RSSISAV5G); - SIBA_SHIFTOUT(bxa5g, SIBA_SPROM8_RSSIPARM5G, SIBA_SPROM8_BXA5G); - - SIBA_SHIFTOUT(pa0b0, SIBA_SPROM8_PA0B0, 0xffff); - SIBA_SHIFTOUT(pa0b1, SIBA_SPROM8_PA0B1, 0xffff); - SIBA_SHIFTOUT(pa0b2, SIBA_SPROM8_PA0B2, 0xffff); - SIBA_SHIFTOUT(pa1b0, SIBA_SPROM8_PA1B0, 0xffff); - SIBA_SHIFTOUT(pa1b1, SIBA_SPROM8_PA1B1, 0xffff); - SIBA_SHIFTOUT(pa1b2, SIBA_SPROM8_PA1B2, 0xffff); - SIBA_SHIFTOUT(pa1lob0, SIBA_SPROM8_PA1LOB0, 0xffff); - SIBA_SHIFTOUT(pa1lob1, SIBA_SPROM8_PA1LOB1, 0xffff); - SIBA_SHIFTOUT(pa1lob2, SIBA_SPROM8_PA1LOB2, 0xffff); - SIBA_SHIFTOUT(pa1hib0, SIBA_SPROM8_PA1HIB0, 0xffff); - SIBA_SHIFTOUT(pa1hib1, SIBA_SPROM8_PA1HIB1, 0xffff); - SIBA_SHIFTOUT(pa1hib2, SIBA_SPROM8_PA1HIB2, 0xffff); - SIBA_SHIFTOUT(cck2gpo, SIBA_SPROM8_CCK2GPO, 0xffff); - - SIBA_SHIFTOUT_4(ofdm2gpo, SIBA_SPROM8_OFDM2GPO, 0xffffffff, 0); - SIBA_SHIFTOUT_4(ofdm5glpo, SIBA_SPROM8_OFDM5GLPO, 0xffffffff, 0); - SIBA_SHIFTOUT_4(ofdm5gpo, SIBA_SPROM8_OFDM5GPO, 0xffffffff, 0); - SIBA_SHIFTOUT_4(ofdm5ghpo, SIBA_SPROM8_OFDM5GHPO, 0xffffffff, 0); - - /* antenna gain */ - SIBA_SHIFTOUT(again.ghz24.a0, SIBA_SPROM8_AGAIN01, SIBA_SPROM8_AGAIN0); - SIBA_SHIFTOUT(again.ghz24.a1, SIBA_SPROM8_AGAIN01, SIBA_SPROM8_AGAIN1); - SIBA_SHIFTOUT(again.ghz24.a2, SIBA_SPROM8_AGAIN23, SIBA_SPROM8_AGAIN2); - SIBA_SHIFTOUT(again.ghz24.a3, SIBA_SPROM8_AGAIN23, SIBA_SPROM8_AGAIN3); - bcopy(&out->again.ghz24, &out->again.ghz5, sizeof(out->again.ghz5)); - - /* FEM */ - SIBA_SHIFTOUT(fem.ghz2.tssipos, SIBA_SPROM8_FEM2G, - SIBA_SROM8_FEM_TSSIPOS); - SIBA_SHIFTOUT(fem.ghz2.extpa_gain, SIBA_SPROM8_FEM2G, - SIBA_SROM8_FEM_EXTPA_GAIN); - SIBA_SHIFTOUT(fem.ghz2.pdet_range, SIBA_SPROM8_FEM2G, - SIBA_SROM8_FEM_PDET_RANGE); - SIBA_SHIFTOUT(fem.ghz2.tr_iso, SIBA_SPROM8_FEM2G, - SIBA_SROM8_FEM_TR_ISO); - SIBA_SHIFTOUT(fem.ghz2.antswlut, SIBA_SPROM8_FEM2G, - SIBA_SROM8_FEM_ANTSWLUT); - - SIBA_SHIFTOUT(fem.ghz5.tssipos, SIBA_SPROM8_FEM5G, - SIBA_SROM8_FEM_TSSIPOS); - SIBA_SHIFTOUT(fem.ghz5.extpa_gain, SIBA_SPROM8_FEM5G, - SIBA_SROM8_FEM_EXTPA_GAIN); - SIBA_SHIFTOUT(fem.ghz5.pdet_range, SIBA_SPROM8_FEM5G, - SIBA_SROM8_FEM_PDET_RANGE); - SIBA_SHIFTOUT(fem.ghz5.tr_iso, SIBA_SPROM8_FEM5G, - SIBA_SROM8_FEM_TR_ISO); - SIBA_SHIFTOUT(fem.ghz5.antswlut, SIBA_SPROM8_FEM5G, - SIBA_SROM8_FEM_ANTSWLUT); - - /* Extract cores power info info */ - for (i = 0; i < nitems(pwr_info_offset); i++) { - uint16_t o = pwr_info_offset[i]; - SIBA_SHIFTOUT(core_pwr_info[i].itssi_2g, o + SIBA_SROM8_2G_MAXP_ITSSI, - SIBA_SPROM8_2G_ITSSI); - SIBA_SHIFTOUT(core_pwr_info[i].maxpwr_2g, o + SIBA_SROM8_2G_MAXP_ITSSI, - SIBA_SPROM8_2G_MAXP); - - SIBA_SHIFTOUT(core_pwr_info[i].pa_2g[0], o + SIBA_SROM8_2G_PA_0, ~0); - SIBA_SHIFTOUT(core_pwr_info[i].pa_2g[1], o + SIBA_SROM8_2G_PA_1, ~0); - SIBA_SHIFTOUT(core_pwr_info[i].pa_2g[2], o + SIBA_SROM8_2G_PA_2, ~0); - - SIBA_SHIFTOUT(core_pwr_info[i].itssi_5g, o + SIBA_SROM8_5G_MAXP_ITSSI, - SIBA_SPROM8_5G_ITSSI); - SIBA_SHIFTOUT(core_pwr_info[i].maxpwr_5g, o + SIBA_SROM8_5G_MAXP_ITSSI, - SIBA_SPROM8_5G_MAXP); - SIBA_SHIFTOUT(core_pwr_info[i].maxpwr_5gh, o + SIBA_SPROM8_5GHL_MAXP, - SIBA_SPROM8_5GH_MAXP); - SIBA_SHIFTOUT(core_pwr_info[i].maxpwr_5gl, o + SIBA_SPROM8_5GHL_MAXP, - SIBA_SPROM8_5GL_MAXP); - - SIBA_SHIFTOUT(core_pwr_info[i].pa_5gl[0], o + SIBA_SROM8_5GL_PA_0, ~0); - SIBA_SHIFTOUT(core_pwr_info[i].pa_5gl[1], o + SIBA_SROM8_5GL_PA_1, ~0); - SIBA_SHIFTOUT(core_pwr_info[i].pa_5gl[2], o + SIBA_SROM8_5GL_PA_2, ~0); - SIBA_SHIFTOUT(core_pwr_info[i].pa_5g[0], o + SIBA_SROM8_5G_PA_0, ~0); - SIBA_SHIFTOUT(core_pwr_info[i].pa_5g[1], o + SIBA_SROM8_5G_PA_1, ~0); - SIBA_SHIFTOUT(core_pwr_info[i].pa_5g[2], o + SIBA_SROM8_5G_PA_2, ~0); - SIBA_SHIFTOUT(core_pwr_info[i].pa_5gh[0], o + SIBA_SROM8_5GH_PA_0, ~0); - SIBA_SHIFTOUT(core_pwr_info[i].pa_5gh[1], o + SIBA_SROM8_5GH_PA_1, ~0); - SIBA_SHIFTOUT(core_pwr_info[i].pa_5gh[2], o + SIBA_SROM8_5GH_PA_2, ~0); - } - - SIBA_SHIFTOUT(cddpo, SIBA_SPROM8_CDDPO, ~0); - SIBA_SHIFTOUT(stbcpo, SIBA_SPROM8_STBCPO, ~0); - - siba_sprom_r458(out, in); -} - -static int8_t -siba_sprom_r123_antgain(uint8_t sprom_revision, const uint16_t *in, - uint16_t mask, uint16_t shift) -{ - uint16_t v; - uint8_t gain; - - v = in[SIBA_OFFSET(SIBA_SPROM1_AGAIN)]; - gain = (v & mask) >> shift; - gain = (gain == 0xff) ? 2 : (sprom_revision == 1) ? gain << 2 : - ((gain & 0xc0) >> 6) | ((gain & 0x3f) << 2); - - return ((int8_t)gain); -} - -#undef SIBA_LOWEST_SET_BIT -#undef SIBA_OFFSET -#undef SIBA_SHIFTOUT_SUB -#undef SIBA_SHIFTOUT - -int -siba_powerdown(device_t dev) -{ - struct siba_dev_softc *sd = device_get_ivars(dev); - struct siba_softc *siba = sd->sd_bus; - - return (siba_powerdown_sub(siba)); -} - -static int -siba_powerdown_sub(struct siba_softc *siba) -{ - struct siba_cc *scc; - - if (siba->siba_type == SIBA_TYPE_SSB) - return (0); - - scc = &siba->siba_cc; - if (!scc->scc_dev || scc->scc_dev->sd_id.sd_rev < 5) - return (0); - siba_cc_clock(scc, SIBA_CLOCK_SLOW); - siba_pci_gpio(siba, SIBA_GPIO_CRYSTAL | SIBA_GPIO_PLL, 0); - return (0); -} - -static void -siba_pcicore_init(struct siba_pci *spc) -{ - struct siba_dev_softc *sd = spc->spc_dev; - - if (sd == NULL) - return; - - if (!siba_dev_isup_sub(sd)) - siba_dev_up_sub(sd, 0); - - KASSERT(spc->spc_hostmode == 0, - ("%s:%d: hostmode", __func__, __LINE__)); - /* disable PCI interrupt */ - siba_write_4_sub(spc->spc_dev, SIBA_INTR_MASK, 0); -} - -int -siba_dev_isup(device_t dev) -{ - struct siba_dev_softc *sd = device_get_ivars(dev); - - return (siba_dev_isup_sub(sd)); -} - -static int -siba_dev_isup_sub(struct siba_dev_softc *sd) -{ - uint32_t reject, val; - - reject = siba_tmslow_reject_bitmask(sd); - val = siba_read_4_sub(sd, SIBA_TGSLOW); - val &= SIBA_TGSLOW_CLOCK | SIBA_TGSLOW_RESET | reject; - - return (val == SIBA_TGSLOW_CLOCK); -} - -void -siba_dev_up(device_t dev, uint32_t flags) -{ - struct siba_dev_softc *sd = device_get_ivars(dev); - - siba_dev_up_sub(sd, flags); -} - -static void -siba_dev_up_sub(struct siba_dev_softc *sd, uint32_t flags) -{ - uint32_t val; - - siba_dev_down_sub(sd, flags); - siba_write_4_sub(sd, SIBA_TGSLOW, - SIBA_TGSLOW_RESET | SIBA_TGSLOW_CLOCK | SIBA_TGSLOW_FGC | flags); - siba_read_4_sub(sd, SIBA_TGSLOW); - DELAY(1); - - if (siba_read_4_sub(sd, SIBA_TGSHIGH) & SIBA_TGSHIGH_SERR) - siba_write_4_sub(sd, SIBA_TGSHIGH, 0); - - val = siba_read_4_sub(sd, SIBA_IAS); - if (val & (SIBA_IAS_INBAND_ERR | SIBA_IAS_TIMEOUT)) { - val &= ~(SIBA_IAS_INBAND_ERR | SIBA_IAS_TIMEOUT); - siba_write_4_sub(sd, SIBA_IAS, val); - } - - siba_write_4_sub(sd, SIBA_TGSLOW, - SIBA_TGSLOW_CLOCK | SIBA_TGSLOW_FGC | flags); - siba_read_4_sub(sd, SIBA_TGSLOW); - DELAY(1); - - siba_write_4_sub(sd, SIBA_TGSLOW, SIBA_TGSLOW_CLOCK | flags); - siba_read_4_sub(sd, SIBA_TGSLOW); - DELAY(1); -} - -static uint32_t -siba_tmslow_reject_bitmask(struct siba_dev_softc *sd) -{ - uint32_t rev = siba_read_4_sub(sd, SIBA_IDLOW) & SIBA_IDLOW_SSBREV; - - switch (rev) { - case SIBA_IDLOW_SSBREV_22: - return (SIBA_TGSLOW_REJECT_22); - case SIBA_IDLOW_SSBREV_23: - return (SIBA_TGSLOW_REJECT_23); - case SIBA_IDLOW_SSBREV_24: - case SIBA_IDLOW_SSBREV_25: - case SIBA_IDLOW_SSBREV_26: - case SIBA_IDLOW_SSBREV_27: - return (SIBA_TGSLOW_REJECT_23); - default: - KASSERT(0 == 1, - ("%s:%d: unknown backplane rev %#x\n", - __func__, __LINE__, rev)); - } - return (SIBA_TGSLOW_REJECT_22 | SIBA_TGSLOW_REJECT_23); -} - -void -siba_dev_down(device_t dev, uint32_t flags) -{ - struct siba_dev_softc *sd = device_get_ivars(dev); - - siba_dev_down_sub(sd, flags); -} - -static void -siba_dev_down_sub(struct siba_dev_softc *sd, uint32_t flags) -{ - struct siba_softc *siba = sd->sd_bus; - uint32_t reject, val; - int i; - - if (siba_read_4_sub(sd, SIBA_TGSLOW) & SIBA_TGSLOW_RESET) - return; - - reject = siba_tmslow_reject_bitmask(sd); - siba_write_4_sub(sd, SIBA_TGSLOW, reject | SIBA_TGSLOW_CLOCK); - - for (i = 0; i < 1000; i++) { - val = siba_read_4_sub(sd, SIBA_TGSLOW); - if (val & reject) - break; - DELAY(10); - } - if ((val & reject) == 0) { - device_printf(siba->siba_dev, "timeout (bit %#x reg %#x)\n", - reject, SIBA_TGSLOW); - } - for (i = 0; i < 1000; i++) { - val = siba_read_4_sub(sd, SIBA_TGSHIGH); - if (!(val & SIBA_TGSHIGH_BUSY)) - break; - DELAY(10); - } - if ((val & SIBA_TGSHIGH_BUSY) != 0) { - device_printf(siba->siba_dev, "timeout (bit %#x reg %#x)\n", - SIBA_TGSHIGH_BUSY, SIBA_TGSHIGH); - } - - siba_write_4_sub(sd, SIBA_TGSLOW, SIBA_TGSLOW_FGC | SIBA_TGSLOW_CLOCK | - reject | SIBA_TGSLOW_RESET | flags); - siba_read_4_sub(sd, SIBA_TGSLOW); - DELAY(1); - siba_write_4_sub(sd, SIBA_TGSLOW, reject | SIBA_TGSLOW_RESET | flags); - siba_read_4_sub(sd, SIBA_TGSLOW); - DELAY(1); -} - -static void -siba_pcicore_setup(struct siba_pci *spc, struct siba_dev_softc *sd) -{ - struct siba_dev_softc *psd = spc->spc_dev; - struct siba_softc *siba = psd->sd_bus; - uint32_t tmp; - - if (psd->sd_id.sd_device == SIBA_DEVID_PCI) { - siba_pcicore_write_4(spc, SIBA_PCICORE_SBTOPCI2, - siba_pcicore_read_4(spc, SIBA_PCICORE_SBTOPCI2) | - SIBA_PCICORE_SBTOPCI_PREF | SIBA_PCICORE_SBTOPCI_BURST); - - if (psd->sd_id.sd_rev < 5) { - tmp = siba_read_4_sub(psd, SIBA_IMCFGLO); - tmp &= ~SIBA_IMCFGLO_SERTO; - tmp = (tmp | 2) & ~SIBA_IMCFGLO_REQTO; - tmp |= 3 << 4 /* SIBA_IMCFGLO_REQTO_SHIFT */; - siba_write_4_sub(psd, SIBA_IMCFGLO, tmp); - - /* broadcast value */ - sd = (siba->siba_cc.scc_dev != NULL) ? - siba->siba_cc.scc_dev : siba->siba_pci.spc_dev; - if (sd != NULL) { - siba_write_4_sub(sd, SIBA_PCICORE_BCAST_ADDR, - 0xfd8); - siba_read_4_sub(sd, SIBA_PCICORE_BCAST_ADDR); - siba_write_4_sub(sd, - SIBA_PCICORE_BCAST_DATA, 0); - siba_read_4_sub(sd, SIBA_PCICORE_BCAST_DATA); - } - } else if (psd->sd_id.sd_rev >= 11) { - tmp = siba_pcicore_read_4(spc, SIBA_PCICORE_SBTOPCI2); - tmp |= SIBA_PCICORE_SBTOPCI_MRM; - siba_pcicore_write_4(spc, SIBA_PCICORE_SBTOPCI2, tmp); - } - } else { - KASSERT(psd->sd_id.sd_device == SIBA_DEVID_PCIE, ("only PCIE")); - if ((psd->sd_id.sd_rev == 0) || (psd->sd_id.sd_rev == 1)) - siba_pcie_write(spc, 0x4, - siba_pcie_read(spc, 0x4) | 0x8); - if (psd->sd_id.sd_rev == 0) { - siba_pcie_mdio_write(spc, 0x1f, 2, 0x8128); /* Timer */ - siba_pcie_mdio_write(spc, 0x1f, 6, 0x0100); /* CDR */ - siba_pcie_mdio_write(spc, 0x1f, 7, 0x1466); /* CDR BW */ - } else if (psd->sd_id.sd_rev == 1) - siba_pcie_write(spc, 0x100, - siba_pcie_read(spc, 0x100) | 0x40); - } - spc->spc_inited = 1; -} - -void -siba_pcicore_intr(device_t dev) -{ - struct siba_dev_softc *sd = device_get_ivars(dev); - struct siba_softc *siba = sd->sd_bus; - struct siba_pci *spc = &siba->siba_pci; - struct siba_dev_softc *psd = spc->spc_dev; - uint32_t tmp; - - if (siba->siba_type != SIBA_TYPE_PCI || !psd) - return; - - KASSERT(siba == psd->sd_bus, ("different pointers")); - - /* enable interrupts */ - if (siba->siba_dev != NULL && - (psd->sd_id.sd_rev >= 6 || - psd->sd_id.sd_device == SIBA_DEVID_PCIE)) { - tmp = pci_read_config(siba->siba_dev, SIBA_IRQMASK, 4); - tmp |= (1 << sd->sd_coreidx) << 8; - pci_write_config(siba->siba_dev, SIBA_IRQMASK, tmp, 4); - } else { - tmp = siba_read_4_sub(sd, SIBA_TPS); - tmp &= SIBA_TPS_BPFLAG; - siba_write_4_sub(psd, SIBA_INTR_MASK, - siba_read_4_sub(psd, SIBA_INTR_MASK) | (1 << tmp)); - } - - /* setup PCIcore */ - if (spc->spc_inited == 0) - siba_pcicore_setup(spc, sd); -} - -static uint32_t -siba_pcicore_read_4(struct siba_pci *spc, uint16_t offset) -{ - - return (siba_read_4_sub(spc->spc_dev, offset)); -} - -static void -siba_pcicore_write_4(struct siba_pci *spc, uint16_t offset, uint32_t value) -{ - - siba_write_4_sub(spc->spc_dev, offset, value); -} - -static uint32_t -siba_pcie_read(struct siba_pci *spc, uint32_t address) -{ - - siba_pcicore_write_4(spc, 0x130, address); - return (siba_pcicore_read_4(spc, 0x134)); -} - -static void -siba_pcie_write(struct siba_pci *spc, uint32_t address, uint32_t data) -{ - - siba_pcicore_write_4(spc, 0x130, address); - siba_pcicore_write_4(spc, 0x134, data); -} - -static void -siba_pcie_mdio_write(struct siba_pci *spc, uint8_t device, uint8_t address, - uint16_t data) -{ - int i; - - siba_pcicore_write_4(spc, SIBA_PCICORE_MDIO_CTL, 0x80 | 0x2); - siba_pcicore_write_4(spc, SIBA_PCICORE_MDIO_DATA, - (1 << 30) | (1 << 28) | - ((uint32_t)device << 22) | ((uint32_t)address << 18) | - (1 << 17) | data); - DELAY(10); - for (i = 0; i < 10; i++) { - if (siba_pcicore_read_4(spc, SIBA_PCICORE_MDIO_CTL) & 0x100) - break; - DELAY(1000); - } - siba_pcicore_write_4(spc, SIBA_PCICORE_MDIO_CTL, 0); -} - -uint32_t -siba_dma_translation(device_t dev) -{ -#ifdef INVARIANTS - struct siba_dev_softc *sd = device_get_ivars(dev); - struct siba_softc *siba = sd->sd_bus; - - KASSERT(siba->siba_type == SIBA_TYPE_PCI, - ("unsupported bustype %d\n", siba->siba_type)); -#endif - - /* Default */ - return (SIBA_PCI_DMA); -} - -void -siba_barrier(device_t dev, int flags) -{ - struct siba_dev_softc *sd = device_get_ivars(dev); - struct siba_softc *siba = sd->sd_bus; - - SIBA_BARRIER(siba, flags); -} - -static void -siba_cc_suspend(struct siba_cc *scc) -{ - - siba_cc_clock(scc, SIBA_CLOCK_SLOW); -} - -static void -siba_cc_resume(struct siba_cc *scc) -{ - - siba_cc_power_init(scc); - siba_cc_clock(scc, SIBA_CLOCK_FAST); -} - -int -siba_core_suspend(struct siba_softc *siba) -{ - - siba_cc_suspend(&siba->siba_cc); - siba_pci_gpio(siba, SIBA_GPIO_CRYSTAL | SIBA_GPIO_PLL, 0); - return (0); -} - -int -siba_core_resume(struct siba_softc *siba) -{ - - siba->siba_pci.spc_inited = 0; - siba->siba_curdev = NULL; - - siba_powerup_sub(siba, 0); - /* XXX setup H/W for PCMCIA??? */ - siba_cc_resume(&siba->siba_cc); - siba_powerdown_sub(siba); - - return (0); -} - -static void -siba_cc_regctl_setmask(struct siba_cc *cc, uint32_t offset, uint32_t mask, - uint32_t set) -{ - - SIBA_CC_READ32(cc, SIBA_CC_REGCTL_ADDR); - SIBA_CC_WRITE32(cc, SIBA_CC_REGCTL_ADDR, offset); - SIBA_CC_READ32(cc, SIBA_CC_REGCTL_ADDR); - SIBA_CC_WRITE32(cc, SIBA_CC_REGCTL_DATA, - (SIBA_CC_READ32(cc, SIBA_CC_REGCTL_DATA) & mask) | set); - SIBA_CC_READ32(cc, SIBA_CC_REGCTL_DATA); -} - -void -siba_cc_pmu_set_ldovolt(device_t dev, int id, uint32_t volt) -{ - struct siba_dev_softc *sd = device_get_ivars(dev); - struct siba_softc *siba = sd->sd_bus; - struct siba_cc *scc = &siba->siba_cc; - uint32_t *p = NULL, info[5][3] = { - { 2, 25, 0xf }, - { 3, 1, 0xf }, - { 3, 9, 0xf }, - { 3, 17, 0x3f }, - { 0, 21, 0x3f } - }; - - if (siba->siba_chipid == 0x4312) { - if (id != SIBA_LDO_PAREF) - return; - p = info[4]; - siba_cc_regctl_setmask(scc, p[0], ~(p[2] << p[1]), - (volt & p[2]) << p[1]); - return; - } - if (siba->siba_chipid == 0x4328 || siba->siba_chipid == 0x5354) { - switch (id) { - case SIBA_LDO_PAREF: - p = info[3]; - break; - case SIBA_LDO_VOLT1: - p = info[0]; - break; - case SIBA_LDO_VOLT2: - p = info[1]; - break; - case SIBA_LDO_VOLT3: - p = info[2]; - break; - default: - KASSERT(0 == 1, - ("%s: unsupported voltage ID %#x", __func__, id)); - return; - } - siba_cc_regctl_setmask(scc, p[0], ~(p[2] << p[1]), - (volt & p[2]) << p[1]); - } -} - -void -siba_cc_pmu_set_ldoparef(device_t dev, uint8_t on) -{ - struct siba_dev_softc *sd = device_get_ivars(dev); - struct siba_softc *siba = sd->sd_bus; - struct siba_cc *scc = &siba->siba_cc; - int ldo; - - ldo = ((siba->siba_chipid == 0x4312) ? SIBA_CC_PMU_4312_PA_REF : - ((siba->siba_chipid == 0x4328) ? SIBA_CC_PMU_4328_PA_REF : - ((siba->siba_chipid == 0x5354) ? SIBA_CC_PMU_5354_PA_REF : -1))); - if (ldo == -1) - return; - - if (on) - SIBA_CC_SET32(scc, SIBA_CC_PMU_MINRES, 1 << ldo); - else - SIBA_CC_MASK32(scc, SIBA_CC_PMU_MINRES, ~(1 << ldo)); - SIBA_CC_READ32(scc, SIBA_CC_PMU_MINRES); -} - -int -siba_read_sprom(device_t dev, device_t child, int which, uintptr_t *result) -{ - struct siba_dev_softc *sd = device_get_ivars(child); - struct siba_softc *siba = sd->sd_bus; - - switch (which) { - case SIBA_SPROMVAR_REV: - *result = siba->siba_sprom.rev; - break; - case SIBA_SPROMVAR_MAC_80211BG: - *((uint8_t **) result) = siba->siba_sprom.mac_80211bg; - break; - case SIBA_SPROMVAR_MAC_ETH: - *((uint8_t **) result) = siba->siba_sprom.mac_eth; - break; - case SIBA_SPROMVAR_MAC_80211A: - *((uint8_t **) result) = siba->siba_sprom.mac_80211a; - break; - case SIBA_SPROMVAR_MII_ETH0: - *result = siba->siba_sprom.mii_eth0; - break; - case SIBA_SPROMVAR_MII_ETH1: - *result = siba->siba_sprom.mii_eth1; - break; - case SIBA_SPROMVAR_MDIO_ETH0: - *result = siba->siba_sprom.mdio_eth0; - break; - case SIBA_SPROMVAR_MDIO_ETH1: - *result = siba->siba_sprom.mdio_eth1; - break; - case SIBA_SPROMVAR_BREV: - *result = siba->siba_sprom.brev; - break; - case SIBA_SPROMVAR_CCODE: - *result = siba->siba_sprom.ccode; - break; - case SIBA_SPROMVAR_ANT_A: - *result = siba->siba_sprom.ant_a; - break; - case SIBA_SPROMVAR_ANT_BG: - *result = siba->siba_sprom.ant_bg; - break; - case SIBA_SPROMVAR_PA0B0: - *result = siba->siba_sprom.pa0b0; - break; - case SIBA_SPROMVAR_PA0B1: - *result = siba->siba_sprom.pa0b1; - break; - case SIBA_SPROMVAR_PA0B2: - *result = siba->siba_sprom.pa0b2; - break; - case SIBA_SPROMVAR_PA1B0: - *result = siba->siba_sprom.pa1b0; - break; - case SIBA_SPROMVAR_PA1B1: - *result = siba->siba_sprom.pa1b1; - break; - case SIBA_SPROMVAR_PA1B2: - *result = siba->siba_sprom.pa1b2; - break; - case SIBA_SPROMVAR_PA1LOB0: - *result = siba->siba_sprom.pa1lob0; - break; - case SIBA_SPROMVAR_PA1LOB1: - *result = siba->siba_sprom.pa1lob1; - break; - case SIBA_SPROMVAR_PA1LOB2: - *result = siba->siba_sprom.pa1lob2; - break; - case SIBA_SPROMVAR_PA1HIB0: - *result = siba->siba_sprom.pa1hib0; - break; - case SIBA_SPROMVAR_PA1HIB1: - *result = siba->siba_sprom.pa1hib1; - break; - case SIBA_SPROMVAR_PA1HIB2: - *result = siba->siba_sprom.pa1hib2; - break; - case SIBA_SPROMVAR_GPIO0: - *result = siba->siba_sprom.gpio0; - break; - case SIBA_SPROMVAR_GPIO1: - *result = siba->siba_sprom.gpio1; - break; - case SIBA_SPROMVAR_GPIO2: - *result = siba->siba_sprom.gpio2; - break; - case SIBA_SPROMVAR_GPIO3: - *result = siba->siba_sprom.gpio3; - break; - case SIBA_SPROMVAR_MAXPWR_AL: - *result = siba->siba_sprom.maxpwr_al; - break; - case SIBA_SPROMVAR_MAXPWR_A: - *result = siba->siba_sprom.maxpwr_a; - break; - case SIBA_SPROMVAR_MAXPWR_AH: - *result = siba->siba_sprom.maxpwr_ah; - break; - case SIBA_SPROMVAR_MAXPWR_BG: - *result = siba->siba_sprom.maxpwr_bg; - break; - case SIBA_SPROMVAR_RXPO2G: - *result = siba->siba_sprom.rxpo2g; - break; - case SIBA_SPROMVAR_RXPO5G: - *result = siba->siba_sprom.rxpo5g; - break; - case SIBA_SPROMVAR_TSSI_A: - *result = siba->siba_sprom.tssi_a; - break; - case SIBA_SPROMVAR_TSSI_BG: - *result = siba->siba_sprom.tssi_bg; - break; - case SIBA_SPROMVAR_TRI2G: - *result = siba->siba_sprom.tri2g; - break; - case SIBA_SPROMVAR_TRI5GL: - *result = siba->siba_sprom.tri5gl; - break; - case SIBA_SPROMVAR_TRI5G: - *result = siba->siba_sprom.tri5g; - break; - case SIBA_SPROMVAR_TRI5GH: - *result = siba->siba_sprom.tri5gh; - break; - case SIBA_SPROMVAR_RSSISAV2G: - *result = siba->siba_sprom.rssisav2g; - break; - case SIBA_SPROMVAR_RSSISMC2G: - *result = siba->siba_sprom.rssismc2g; - break; - case SIBA_SPROMVAR_RSSISMF2G: - *result = siba->siba_sprom.rssismf2g; - break; - case SIBA_SPROMVAR_BXA2G: - *result = siba->siba_sprom.bxa2g; - break; - case SIBA_SPROMVAR_RSSISAV5G: - *result = siba->siba_sprom.rssisav5g; - break; - case SIBA_SPROMVAR_RSSISMC5G: - *result = siba->siba_sprom.rssismc5g; - break; - case SIBA_SPROMVAR_RSSISMF5G: - *result = siba->siba_sprom.rssismf5g; - break; - case SIBA_SPROMVAR_BXA5G: - *result = siba->siba_sprom.bxa5g; - break; - case SIBA_SPROMVAR_CCK2GPO: - *result = siba->siba_sprom.cck2gpo; - break; - case SIBA_SPROMVAR_OFDM2GPO: - *result = siba->siba_sprom.ofdm2gpo; - break; - case SIBA_SPROMVAR_OFDM5GLPO: - *result = siba->siba_sprom.ofdm5glpo; - break; - case SIBA_SPROMVAR_OFDM5GPO: - *result = siba->siba_sprom.ofdm5gpo; - break; - case SIBA_SPROMVAR_OFDM5GHPO: - *result = siba->siba_sprom.ofdm5ghpo; - break; - case SIBA_SPROMVAR_BF_LO: - *result = siba->siba_sprom.bf_lo; - break; - case SIBA_SPROMVAR_BF_HI: - *result = siba->siba_sprom.bf_hi; - break; - case SIBA_SPROMVAR_BF2_LO: - *result = siba->siba_sprom.bf2_lo; - break; - case SIBA_SPROMVAR_BF2_HI: - *result = siba->siba_sprom.bf2_hi; - break; - case SIBA_SPROMVAR_FEM_2GHZ_TSSIPOS: - *result = siba->siba_sprom.fem.ghz2.tssipos; - break; - case SIBA_SPROMVAR_FEM_2GHZ_EXTPAGAIN: - *result = siba->siba_sprom.fem.ghz2.extpa_gain; - break; - case SIBA_SPROMVAR_FEM_2GHZ_PDET_RANGE: - *result = siba->siba_sprom.fem.ghz2.pdet_range; - break; - case SIBA_SPROMVAR_FEM_2GHZ_TR_ISO: - *result = siba->siba_sprom.fem.ghz2.tr_iso; - break; - case SIBA_SPROMVAR_FEM_2GHZ_ANTSWLUT: - *result = siba->siba_sprom.fem.ghz2.antswlut; - break; - case SIBA_SPROMVAR_FEM_5GHZ_TSSIPOS: - *result = siba->siba_sprom.fem.ghz5.tssipos; - break; - case SIBA_SPROMVAR_FEM_5GHZ_EXTPAGAIN: - *result = siba->siba_sprom.fem.ghz5.extpa_gain; - break; - case SIBA_SPROMVAR_FEM_5GHZ_PDET_RANGE: - *result = siba->siba_sprom.fem.ghz5.pdet_range; - break; - case SIBA_SPROMVAR_FEM_5GHZ_TR_ISO: - *result = siba->siba_sprom.fem.ghz5.tr_iso; - break; - case SIBA_SPROMVAR_FEM_5GHZ_ANTSWLUT: - *result = siba->siba_sprom.fem.ghz5.antswlut; - break; - case SIBA_SPROMVAR_TXPID_2G_0: - *result = siba->siba_sprom.txpid2g[0]; - break; - case SIBA_SPROMVAR_TXPID_2G_1: - *result = siba->siba_sprom.txpid2g[1]; - break; - case SIBA_SPROMVAR_TXPID_2G_2: - *result = siba->siba_sprom.txpid2g[2]; - break; - case SIBA_SPROMVAR_TXPID_2G_3: - *result = siba->siba_sprom.txpid2g[3]; - break; - case SIBA_SPROMVAR_TXPID_5GL_0: - *result = siba->siba_sprom.txpid5gl[0]; - break; - case SIBA_SPROMVAR_TXPID_5GL_1: - *result = siba->siba_sprom.txpid5gl[1]; - break; - case SIBA_SPROMVAR_TXPID_5GL_2: - *result = siba->siba_sprom.txpid5gl[2]; - break; - case SIBA_SPROMVAR_TXPID_5GL_3: - *result = siba->siba_sprom.txpid5gl[3]; - break; - case SIBA_SPROMVAR_TXPID_5G_0: - *result = siba->siba_sprom.txpid5g[0]; - break; - case SIBA_SPROMVAR_TXPID_5G_1: - *result = siba->siba_sprom.txpid5g[1]; - break; - case SIBA_SPROMVAR_TXPID_5G_2: - *result = siba->siba_sprom.txpid5g[2]; - break; - case SIBA_SPROMVAR_TXPID_5G_3: - *result = siba->siba_sprom.txpid5g[3]; - break; - case SIBA_SPROMVAR_TXPID_5GH_0: - *result = siba->siba_sprom.txpid5gh[0]; - break; - case SIBA_SPROMVAR_TXPID_5GH_1: - *result = siba->siba_sprom.txpid5gh[1]; - break; - case SIBA_SPROMVAR_TXPID_5GH_2: - *result = siba->siba_sprom.txpid5gh[2]; - break; - case SIBA_SPROMVAR_TXPID_5GH_3: - *result = siba->siba_sprom.txpid5gh[3]; - break; - case SIBA_SPROMVAR_STBCPO: - *result = siba->siba_sprom.stbcpo; - break; - case SIBA_SPROMVAR_CDDPO: - *result = siba->siba_sprom.cddpo; - break; - default: - return (ENOENT); - } - return (0); -} - -int -siba_write_sprom(device_t dev, device_t child, int which, uintptr_t value) -{ - struct siba_dev_softc *sd = device_get_ivars(child); - struct siba_softc *siba = sd->sd_bus; - - switch (which) { - case SIBA_SPROMVAR_REV: - siba->siba_sprom.rev = value; - break; - case SIBA_SPROMVAR_MII_ETH0: - siba->siba_sprom.mii_eth0 = value; - break; - case SIBA_SPROMVAR_MII_ETH1: - siba->siba_sprom.mii_eth1 = value; - break; - case SIBA_SPROMVAR_MDIO_ETH0: - siba->siba_sprom.mdio_eth0 = value; - break; - case SIBA_SPROMVAR_MDIO_ETH1: - siba->siba_sprom.mdio_eth1 = value; - break; - case SIBA_SPROMVAR_BREV: - siba->siba_sprom.brev = value; - break; - case SIBA_SPROMVAR_CCODE: - siba->siba_sprom.ccode = value; - break; - case SIBA_SPROMVAR_ANT_A: - siba->siba_sprom.ant_a = value; - break; - case SIBA_SPROMVAR_ANT_BG: - siba->siba_sprom.ant_bg = value; - break; - case SIBA_SPROMVAR_PA0B0: - siba->siba_sprom.pa0b0 = value; - break; - case SIBA_SPROMVAR_PA0B1: - siba->siba_sprom.pa0b1 = value; - break; - case SIBA_SPROMVAR_PA0B2: - siba->siba_sprom.pa0b2 = value; - break; - case SIBA_SPROMVAR_PA1B0: - siba->siba_sprom.pa1b0 = value; - break; - case SIBA_SPROMVAR_PA1B1: - siba->siba_sprom.pa1b1 = value; - break; - case SIBA_SPROMVAR_PA1B2: - siba->siba_sprom.pa1b2 = value; - break; - case SIBA_SPROMVAR_PA1LOB0: - siba->siba_sprom.pa1lob0 = value; - break; - case SIBA_SPROMVAR_PA1LOB1: - siba->siba_sprom.pa1lob1 = value; - break; - case SIBA_SPROMVAR_PA1LOB2: - siba->siba_sprom.pa1lob2 = value; - break; - case SIBA_SPROMVAR_PA1HIB0: - siba->siba_sprom.pa1hib0 = value; - break; - case SIBA_SPROMVAR_PA1HIB1: - siba->siba_sprom.pa1hib1 = value; - break; - case SIBA_SPROMVAR_PA1HIB2: - siba->siba_sprom.pa1hib2 = value; - break; - case SIBA_SPROMVAR_GPIO0: - siba->siba_sprom.gpio0 = value; - break; - case SIBA_SPROMVAR_GPIO1: - siba->siba_sprom.gpio1 = value; - break; - case SIBA_SPROMVAR_GPIO2: - siba->siba_sprom.gpio2 = value; - break; - case SIBA_SPROMVAR_GPIO3: - siba->siba_sprom.gpio3 = value; - break; - case SIBA_SPROMVAR_MAXPWR_AL: - siba->siba_sprom.maxpwr_al = value; - break; - case SIBA_SPROMVAR_MAXPWR_A: - siba->siba_sprom.maxpwr_a = value; - break; - case SIBA_SPROMVAR_MAXPWR_AH: - siba->siba_sprom.maxpwr_ah = value; - break; - case SIBA_SPROMVAR_MAXPWR_BG: - siba->siba_sprom.maxpwr_bg = value; - break; - case SIBA_SPROMVAR_RXPO2G: - siba->siba_sprom.rxpo2g = value; - break; - case SIBA_SPROMVAR_RXPO5G: - siba->siba_sprom.rxpo5g = value; - break; - case SIBA_SPROMVAR_TSSI_A: - siba->siba_sprom.tssi_a = value; - break; - case SIBA_SPROMVAR_TSSI_BG: - siba->siba_sprom.tssi_bg = value; - break; - case SIBA_SPROMVAR_TRI2G: - siba->siba_sprom.tri2g = value; - break; - case SIBA_SPROMVAR_TRI5GL: - siba->siba_sprom.tri5gl = value; - break; - case SIBA_SPROMVAR_TRI5G: - siba->siba_sprom.tri5g = value; - break; - case SIBA_SPROMVAR_TRI5GH: - siba->siba_sprom.tri5gh = value; - break; - case SIBA_SPROMVAR_RSSISAV2G: - siba->siba_sprom.rssisav2g = value; - break; - case SIBA_SPROMVAR_RSSISMC2G: - siba->siba_sprom.rssismc2g = value; - break; - case SIBA_SPROMVAR_RSSISMF2G: - siba->siba_sprom.rssismf2g = value; - break; - case SIBA_SPROMVAR_BXA2G: - siba->siba_sprom.bxa2g = value; - break; - case SIBA_SPROMVAR_RSSISAV5G: - siba->siba_sprom.rssisav5g = value; - break; - case SIBA_SPROMVAR_RSSISMC5G: - siba->siba_sprom.rssismc5g = value; - break; - case SIBA_SPROMVAR_RSSISMF5G: - siba->siba_sprom.rssismf5g = value; - break; - case SIBA_SPROMVAR_BXA5G: - siba->siba_sprom.bxa5g = value; - break; - case SIBA_SPROMVAR_CCK2GPO: - siba->siba_sprom.cck2gpo = value; - break; - case SIBA_SPROMVAR_OFDM2GPO: - siba->siba_sprom.ofdm2gpo = value; - break; - case SIBA_SPROMVAR_OFDM5GLPO: - siba->siba_sprom.ofdm5glpo = value; - break; - case SIBA_SPROMVAR_OFDM5GPO: - siba->siba_sprom.ofdm5gpo = value; - break; - case SIBA_SPROMVAR_OFDM5GHPO: - siba->siba_sprom.ofdm5ghpo = value; - break; - case SIBA_SPROMVAR_BF_LO: - siba->siba_sprom.bf_lo = value; - break; - case SIBA_SPROMVAR_BF_HI: - siba->siba_sprom.bf_hi = value; - break; - case SIBA_SPROMVAR_BF2_LO: - siba->siba_sprom.bf2_lo = value; - break; - case SIBA_SPROMVAR_BF2_HI: - siba->siba_sprom.bf2_hi = value; - break; - default: - return (ENOENT); - } - return (0); -} - -#define SIBA_GPIOCTL 0x06c - -uint32_t -siba_gpio_get(device_t dev) -{ - struct siba_dev_softc *sd = device_get_ivars(dev); - struct siba_softc *siba = sd->sd_bus; - struct siba_dev_softc *gpiodev, *pcidev = NULL; - - pcidev = siba->siba_pci.spc_dev; - gpiodev = siba->siba_cc.scc_dev ? siba->siba_cc.scc_dev : pcidev; - if (!gpiodev) - return (-1); - return (siba_read_4_sub(gpiodev, SIBA_GPIOCTL)); -} - -void -siba_gpio_set(device_t dev, uint32_t value) -{ - struct siba_dev_softc *sd = device_get_ivars(dev); - struct siba_softc *siba = sd->sd_bus; - struct siba_dev_softc *gpiodev, *pcidev = NULL; - - pcidev = siba->siba_pci.spc_dev; - gpiodev = siba->siba_cc.scc_dev ? siba->siba_cc.scc_dev : pcidev; - if (!gpiodev) - return; - siba_write_4_sub(gpiodev, SIBA_GPIOCTL, value); -} - -void -siba_fix_imcfglobug(device_t dev) -{ - struct siba_dev_softc *sd = device_get_ivars(dev); - struct siba_softc *siba = sd->sd_bus; - uint32_t tmp; - - if (siba->siba_pci.spc_dev == NULL) - return; - if (siba->siba_pci.spc_dev->sd_id.sd_device != SIBA_DEVID_PCI || - siba->siba_pci.spc_dev->sd_id.sd_rev > 5) - return; - - tmp = siba_read_4_sub(sd, SIBA_IMCFGLO) & - ~(SIBA_IMCFGLO_REQTO | SIBA_IMCFGLO_SERTO); - switch (siba->siba_type) { - case SIBA_TYPE_PCI: - case SIBA_TYPE_PCMCIA: - tmp |= 0x32; - break; - case SIBA_TYPE_SSB: - tmp |= 0x53; - break; - } - siba_write_4_sub(sd, SIBA_IMCFGLO, tmp); -} - -int -siba_sprom_get_core_power_info(device_t dev, int core, - struct siba_sprom_core_pwr_info *c) -{ - struct siba_dev_softc *sd = device_get_ivars(dev); - struct siba_softc *siba = sd->sd_bus; - - if (core < 0 || core > 3) { - return (EINVAL); - } - memcpy(c, &siba->siba_sprom.core_pwr_info[core], sizeof(*c)); - return (0); -} - -int -siba_sprom_get_mcs2gpo(device_t dev, uint16_t *c) -{ - struct siba_dev_softc *sd = device_get_ivars(dev); - struct siba_softc *siba = sd->sd_bus; - - memcpy(c, &siba->siba_sprom.mcs2gpo, sizeof(uint16_t) * 8); - return (0); -} - -int -siba_sprom_get_mcs5glpo(device_t dev, uint16_t *c) -{ - struct siba_dev_softc *sd = device_get_ivars(dev); - struct siba_softc *siba = sd->sd_bus; - - memcpy(c, &siba->siba_sprom.mcs5glpo, sizeof(uint16_t) * 8); - return (0); -} - -int -siba_sprom_get_mcs5gpo(device_t dev, uint16_t *c) -{ - struct siba_dev_softc *sd = device_get_ivars(dev); - struct siba_softc *siba = sd->sd_bus; - - memcpy(c, &siba->siba_sprom.mcs5gpo, sizeof(uint16_t) * 8); - return (0); -} - -int -siba_sprom_get_mcs5ghpo(device_t dev, uint16_t *c) -{ - struct siba_dev_softc *sd = device_get_ivars(dev); - struct siba_softc *siba = sd->sd_bus; - - memcpy(c, &siba->siba_sprom.mcs5ghpo, sizeof(uint16_t) * 8); - return (0); -} - -void -siba_pmu_spuravoid_pllupdate(device_t dev, int spur_avoid) -{ - struct siba_dev_softc *sd = device_get_ivars(dev); - struct siba_softc *siba = sd->sd_bus; - struct siba_cc *scc; - - scc = &siba->siba_cc; - - if (scc->scc_dev == NULL) { - device_printf(dev, "%s: called; no pmu\n", __func__); - return; - } - - switch (siba_get_chipid(dev)) { - case 0x4322: - siba_cc_pll_write(scc, SIBA_CC_PMU1_PLL0, 0x11100070); - siba_cc_pll_write(scc, SIBA_CC_PMU1_PLL1, 0x1014140a); - siba_cc_pll_write(scc, SIBA_CC_PMU1_PLL5, 0x88888854); - if (spur_avoid == 1) - siba_cc_pll_write(scc, SIBA_CC_PMU1_PLL2, 0x05201828); - else - siba_cc_pll_write(scc, SIBA_CC_PMU1_PLL2, 0x05001828); - break; - case 43222: - if (spur_avoid == 1) { - siba_cc_pll_write(scc, SIBA_CC_PMU1_PLL0, 0x11500008); - siba_cc_pll_write(scc, SIBA_CC_PMU1_PLL1, 0x0C000C06); - siba_cc_pll_write(scc, SIBA_CC_PMU1_PLL2, 0x0F600a08); - siba_cc_pll_write(scc, SIBA_CC_PMU1_PLL3, 0x00000000); - siba_cc_pll_write(scc, SIBA_CC_PMU1_PLL4, 0x2001E920); - siba_cc_pll_write(scc, SIBA_CC_PMU1_PLL5, 0x88888815); - } else { - siba_cc_pll_write(scc, SIBA_CC_PMU1_PLL0, 0x11100008); - siba_cc_pll_write(scc, SIBA_CC_PMU1_PLL1, 0x0c000c06); - siba_cc_pll_write(scc, SIBA_CC_PMU1_PLL2, 0x03000a08); - siba_cc_pll_write(scc, SIBA_CC_PMU1_PLL3, 0x00000000); - siba_cc_pll_write(scc, SIBA_CC_PMU1_PLL4, 0x200005c0); - siba_cc_pll_write(scc, SIBA_CC_PMU1_PLL5, 0x88888855); - } - break; - default: - device_printf(dev, - "%s: unknown spur avoidance settings for chip 0x%04x\n", - __func__, - siba_get_chipid(dev)); - return; - } - - /* Both chips above use the same update */ - SIBA_CC_SET32(scc, SIBA_CC_PMUCTL, SIBA_CC_PMUCTL_PLL_UPD); -} - -void -siba_cc_set32(device_t dev, uint32_t reg, uint32_t val) -{ - struct siba_dev_softc *sd = device_get_ivars(dev); - struct siba_softc *siba = sd->sd_bus; - struct siba_cc *scc; - - scc = &siba->siba_cc; - - if (scc->scc_dev == NULL) { - device_printf(dev, "%s: called; no pmu\n", __func__); - return; - } - - SIBA_CC_SET32(scc, reg, val); -} - -void -siba_cc_mask32(device_t dev, uint32_t reg, uint32_t mask) -{ - struct siba_dev_softc *sd = device_get_ivars(dev); - struct siba_softc *siba = sd->sd_bus; - struct siba_cc *scc; - - scc = &siba->siba_cc; - - if (scc->scc_dev == NULL) { - device_printf(dev, "%s: called; no pmu\n", __func__); - return; - } - - SIBA_CC_MASK32(scc, reg, mask); -} - -uint32_t -siba_cc_read32(device_t dev, uint32_t reg) -{ - struct siba_dev_softc *sd = device_get_ivars(dev); - struct siba_softc *siba = sd->sd_bus; - struct siba_cc *scc; - - scc = &siba->siba_cc; - - if (scc->scc_dev == NULL) { - device_printf(dev, "%s: called; no pmu\n", __func__); - return 0xffffffff; - } - - return SIBA_CC_READ32(scc, reg); -} - -void -siba_cc_write32(device_t dev, uint32_t reg, uint32_t val) -{ - struct siba_dev_softc *sd = device_get_ivars(dev); - struct siba_softc *siba = sd->sd_bus; - struct siba_cc *scc; - - scc = &siba->siba_cc; - - if (scc->scc_dev == NULL) { - device_printf(dev, "%s: called; no pmu\n", __func__); - return; - } - - SIBA_CC_WRITE32(scc, reg, val); -} - Property changes on: head/sys/dev/siba/siba_core.c ___________________________________________________________________ Deleted: svn:eol-style ## -1 +0,0 ## -native \ No newline at end of property Deleted: svn:keywords ## -1 +0,0 ## -FreeBSD=%H \ No newline at end of property Deleted: svn:mime-type ## -1 +0,0 ## -text/plain \ No newline at end of property Index: head/sys/dev/siba/sibareg.h =================================================================== --- head/sys/dev/siba/sibareg.h (revision 328911) +++ head/sys/dev/siba/sibareg.h (nonexistent) @@ -1,582 +0,0 @@ -/*- - * SPDX-License-Identifier: BSD-2-Clause-FreeBSD - * - * Copyright (c) 2007 Bruce M. Simpson. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - * - * $FreeBSD$ - */ - -/* - * TODO: sprom - * TODO: implement dma translation bits (if needed for system bus) - */ - -#ifndef _SIBA_SIBAREG_H_ -#define _SIBA_SIBAREG_H_ - -#define PCI_DEVICE_ID_BCM4401 0x4401 -#define PCI_DEVICE_ID_BCM4401B0 0x4402 -#define PCI_DEVICE_ID_BCM4401B1 0x170c -#define SIBA_PCIR_BAR PCIR_BAR(0) -#define SIBA_CCID_BCM4710 0x4710 -#define SIBA_CCID_BCM4704 0x4704 -#define SIBA_CCID_SENTRY5 0x5365 - -/* - * ChipCommon registers. - */ -#define SIBA_CC_CHIPID 0x0000 -#define SIBA_CC_IDMASK 0x0000ffff -#define SIBA_CC_ID(id) (id & SIBA_CC_IDMASK) -#define SIBA_CC_REVMASK 0x000f0000 -#define SIBA_CC_REVSHIFT 16 -#define SIBA_CC_REV(id) \ - ((id & SIBA_CC_REVMASK) >> SIBA_CC_REVSHIFT) -#define SIBA_CC_PKGMASK 0x00F00000 -#define SIBA_CC_PKGSHIFT 20 -#define SIBA_CC_PKG(id) \ - ((id & SIBA_CC_PKGMASK) >> SIBA_CC_PKGSHIFT) -#define SIBA_CC_NCORESMASK 0x0F000000 -#define SIBA_CC_NCORESSHIFT 24 -#define SIBA_CC_NCORES(id) \ - ((id & SIBA_CC_NCORESMASK) >> SIBA_CC_NCORESSHIFT) -#define SIBA_CC_CAPS 0x0004 -#define SIBA_CC_CAPS_PWCTL 0x00040000 -#define SIBA_CC_CAPS_PMU 0x10000000 /* PMU (rev >= 20) */ -#define SIBA_CC_CHIPCTL 0x0028 /* rev >= 11 */ -#define SIBA_CC_CHIPSTAT 0x002C /* rev >= 11 */ -#define SIBA_CC_BCAST_ADDR 0x0050 /* Broadcast Address */ -#define SIBA_CC_BCAST_DATA 0x0054 /* Broadcast Data */ -#define SIBA_CC_PLLONDELAY 0x00B0 /* Rev >= 4 only */ -#define SIBA_CC_FREFSELDELAY 0x00B4 /* Rev >= 4 only */ -#define SIBA_CC_CLKSLOW 0x00b8 /* 6 <= Rev <= 9 only */ -#define SIBA_CC_CLKSLOW_SRC 0x00000007 -#define SIBA_CC_CLKSLOW_SRC_CRYSTAL 0x00000001 -#define SIBA_CC_CLKSLOW_FSLOW 0x00000800 -#define SIBA_CC_CLKSLOW_IPLL 0x00001000 -#define SIBA_CC_CLKSLOW_ENXTAL 0x00002000 -#define SIBA_CC_CLKSYSCTL 0x00C0 /* Rev >= 3 only */ -#define SIBA_CC_CLKCTLSTATUS 0x01e0 -#define SIBA_CC_CLKCTLSTATUS_HT 0x00010000 -#define SIBA_CC_UART0 0x0300 /* offset of UART0 */ -#define SIBA_CC_UART1 0x0400 /* offset of UART1 */ -#define SIBA_CC_PMUCTL 0x0600 /* PMU control */ -#define SIBA_CC_PMUCTL_PLL_UPD 0x00000400 -#define SIBA_CC_PMUCTL_ILP 0xffff0000 /* mask */ -#define SIBA_CC_PMUCTL_NOILP 0x00000200 -#define SIBA_CC_PMUCTL_XF 0x0000007c /* crystal freq */ -#define SIBA_CC_PMUCTL_XF_VAL(id) ((id & 0x0000007c) >> 2) -#define SIBA_CC_PMUCAPS 0x0604 -#define SIBA_CC_PMUCAPS_REV 0x000000ff -#define SIBA_CC_PMU_MINRES 0x0618 -#define SIBA_CC_PMU_MAXRES 0x061c -#define SIBA_CC_PMU_TABSEL 0x0620 -#define SIBA_CC_PMU_DEPMSK 0x0624 -#define SIBA_CC_PMU_UPDNTM 0x0628 -#define SIBA_CC_CHIPCTL_ADDR 0x0650 -#define SIBA_CC_CHIPCTL_DATA 0x0654 -#define SIBA_CC_REGCTL_ADDR 0x0658 -#define SIBA_CC_REGCTL_DATA 0x065c -#define SIBA_CC_PLLCTL_ADDR 0x0660 -#define SIBA_CC_PLLCTL_DATA 0x0664 - -#define SIBA_CC_PMU0_PLL0 0 -#define SIBA_CC_PMU0_PLL0_PDIV_MSK 0x00000001 -#define SIBA_CC_PMU0_PLL0_PDIV_FREQ 25000 -#define SIBA_CC_PMU0_PLL1 1 -#define SIBA_CC_PMU0_PLL1_IMSK 0xf0000000 -#define SIBA_CC_PMU0_PLL1_FMSK 0x0fffff00 -#define SIBA_CC_PMU0_PLL1_STOPMOD 0x00000040 -#define SIBA_CC_PMU0_PLL2 2 -#define SIBA_CC_PMU0_PLL2_IMSKHI 0x0000000f -#define SIBA_CC_PMU1_PLL0 0 -#define SIBA_CC_PMU1_PLL0_P1DIV 0x00f00000 -#define SIBA_CC_PMU1_PLL0_P2DIV 0x0f000000 -#define SIBA_CC_PMU1_PLL1 1 -#define SIBA_CC_PMU1_PLL2 2 -#define SIBA_CC_PMU1_PLL2_NDIVMODE 0x000e0000 -#define SIBA_CC_PMU1_PLL2_NDIVINT 0x1ff00000 -#define SIBA_CC_PMU1_PLL3 3 -#define SIBA_CC_PMU1_PLL3_NDIVFRAC 0x00ffffff -#define SIBA_CC_PMU1_PLL4 4 -#define SIBA_CC_PMU1_PLL5 5 -#define SIBA_CC_PMU1_PLL5_CLKDRV 0xffffff00 - -#define SIBA_CC_PMU0_DEFAULT_XTALFREQ 20000 -#define SIBA_CC_PMU1_DEFAULT_FREQ 15360 - -#define SIBA_CC_PMU1_PLLTAB_ENTRY \ -{ \ - { 12000, 1, 3, 22, 0x9, 0xffffef }, \ - { 13000, 2, 1, 6, 0xb, 0x483483 }, \ - { 14400, 3, 1, 10, 0xa, 0x1c71c7 }, \ - { 15360, 4, 1, 5, 0xb, 0x755555 }, \ - { 16200, 5, 1, 10, 0x5, 0x6e9e06 }, \ - { 16800, 6, 1, 10, 0x5, 0x3cf3cf }, \ - { 19200, 7, 1, 9, 0x5, 0x17b425 }, \ - { 19800, 8, 1, 11, 0x4, 0xa57eb }, \ - { 20000, 9, 1, 11, 0x4, 0 }, \ - { 24000, 10, 3, 11, 0xa, 0 }, \ - { 25000, 11, 5, 16, 0xb, 0 }, \ - { 26000, 12, 1, 2, 0x10, 0xec4ec4 }, \ - { 30000, 13, 3, 8, 0xb, 0 }, \ - { 38400, 14, 1, 5, 0x4, 0x955555 }, \ - { 40000, 15, 1, 2, 0xb, 0 } \ -} - -#define SIBA_CC_PMU0_PLLTAB_ENTRY \ -{ \ - { 12000, 1, 73, 349525, }, { 13000, 2, 67, 725937, }, \ - { 14400, 3, 61, 116508, }, { 15360, 4, 57, 305834, }, \ - { 16200, 5, 54, 336579, }, { 16800, 6, 52, 399457, }, \ - { 19200, 7, 45, 873813, }, { 19800, 8, 44, 466033, }, \ - { 20000, 9, 44, 0, }, { 25000, 10, 70, 419430, }, \ - { 26000, 11, 67, 725937, }, { 30000, 12, 58, 699050, }, \ - { 38400, 13, 45, 873813, }, { 40000, 14, 45, 0, }, \ -} - -#define SIBA_CC_PMU_4312_PA_REF 2 -#define SIBA_CC_PMU_4325_BURST 1 -#define SIBA_CC_PMU_4325_CLBURST 3 -#define SIBA_CC_PMU_4325_LN 10 -#define SIBA_CC_PMU_4325_CRYSTAL 13 -#define SIBA_CC_PMU_4325_RX_PWR 15 -#define SIBA_CC_PMU_4325_TX_PWR 16 -#define SIBA_CC_PMU_4325_LOGEN_PWR 18 -#define SIBA_CC_PMU_4325_AFE_PWR 19 -#define SIBA_CC_PMU_4325_BBPLL_PWR 20 -#define SIBA_CC_PMU_4325_HT 21 -#define SIBA_CC_PMU_4328_EXT_SWITCH_PWM 0 -#define SIBA_CC_PMU_4328_BB_SWITCH_PWM 1 -#define SIBA_CC_PMU_4328_BB_SWITCH_BURST 2 -#define SIBA_CC_PMU_4328_BB_EXT_SWITCH_BURST 3 -#define SIBA_CC_PMU_4328_ILP_REQUEST 4 -#define SIBA_CC_PMU_4328_RADSWITCH_PWM 5 /* radio switch */ -#define SIBA_CC_PMU_4328_RADSWITCH_BURST 6 -#define SIBA_CC_PMU_4328_ROM_SWITCH 7 -#define SIBA_CC_PMU_4328_PA_REF 8 -#define SIBA_CC_PMU_4328_RADIO 9 -#define SIBA_CC_PMU_4328_AFE 10 -#define SIBA_CC_PMU_4328_PLL 11 -#define SIBA_CC_PMU_4328_BG_FILTBYP 12 -#define SIBA_CC_PMU_4328_TX_FILTBYP 13 -#define SIBA_CC_PMU_4328_RX_FILTBYP 14 -#define SIBA_CC_PMU_4328_CRYSTAL_PU 15 -#define SIBA_CC_PMU_4328_CRYSTAL_EN 16 -#define SIBA_CC_PMU_4328_BB_PLL_FILTBYP 17 -#define SIBA_CC_PMU_4328_RF_PLL_FILTBYP 18 -#define SIBA_CC_PMU_4328_BB_PLL_PU 19 -#define SIBA_CC_PMU_5354_PA_REF 8 -#define SIBA_CC_PMU_5354_BB_PLL_PU 19 - -#define SIBA_CC_PMU_4325_RES_UPDOWN \ -{ \ - { SIBA_CC_PMU_4325_CRYSTAL, 0x1501 } \ -} - -#define SIBA_CC_PMU_4325_RES_DEPEND \ -{ \ - { SIBA_CC_PMU_4325_HT, SIBA_CC_PMU_DEP_ADD, \ - ((1 << SIBA_CC_PMU_4325_RX_PWR) | \ - (1 << SIBA_CC_PMU_4325_TX_PWR) | \ - (1 << SIBA_CC_PMU_4325_LOGEN_PWR) | \ - (1 << SIBA_CC_PMU_4325_AFE_PWR)) } \ -} - -#define SIBA_CC_PMU_4328_RES_UPDOWN \ -{ \ - { SIBA_CC_PMU_4328_EXT_SWITCH_PWM, 0x0101 }, \ - { SIBA_CC_PMU_4328_BB_SWITCH_PWM, 0x1f01 }, \ - { SIBA_CC_PMU_4328_BB_SWITCH_BURST, 0x010f }, \ - { SIBA_CC_PMU_4328_BB_EXT_SWITCH_BURST, 0x0101 }, \ - { SIBA_CC_PMU_4328_ILP_REQUEST, 0x0202 }, \ - { SIBA_CC_PMU_4328_RADSWITCH_PWM, 0x0f01 }, \ - { SIBA_CC_PMU_4328_RADSWITCH_BURST, 0x0f01 }, \ - { SIBA_CC_PMU_4328_ROM_SWITCH, 0x0101 }, \ - { SIBA_CC_PMU_4328_PA_REF, 0x0f01 }, \ - { SIBA_CC_PMU_4328_RADIO, 0x0f01 }, \ - { SIBA_CC_PMU_4328_AFE, 0x0f01 }, \ - { SIBA_CC_PMU_4328_PLL, 0x0f01 }, \ - { SIBA_CC_PMU_4328_BG_FILTBYP, 0x0101 }, \ - { SIBA_CC_PMU_4328_TX_FILTBYP, 0x0101 }, \ - { SIBA_CC_PMU_4328_RX_FILTBYP, 0x0101 }, \ - { SIBA_CC_PMU_4328_CRYSTAL_PU, 0x0101 }, \ - { SIBA_CC_PMU_4328_CRYSTAL_EN, 0xa001 }, \ - { SIBA_CC_PMU_4328_BB_PLL_FILTBYP, 0x0101 }, \ - { SIBA_CC_PMU_4328_RF_PLL_FILTBYP, 0x0101 }, \ - { SIBA_CC_PMU_4328_BB_PLL_PU, 0x0701 }, \ -} - -#define SIBA_CC_PMU_4328_RES_DEPEND \ -{ \ - { SIBA_CC_PMU_4328_ILP_REQUEST, SIBA_CC_PMU_DEP_SET, \ - ((1 << SIBA_CC_PMU_4328_EXT_SWITCH_PWM) | \ - (1 << SIBA_CC_PMU_4328_BB_SWITCH_PWM)) }, \ -} - -#define SIBA_CC_CHST_4325_PMUTOP_2B 0x00000200 - -#define SIBA_BAR0 0x80 -#define SIBA_IRQMASK 0x94 -#define SIBA_GPIO_IN 0xb0 -#define SIBA_GPIO_OUT 0xb4 -#define SIBA_GPIO_OUT_EN 0xb8 -#define SIBA_GPIO_CRYSTAL 0x40 -#define SIBA_GPIO_PLL 0x80 - -#define SIBA_REGWIN(x) \ - (SIBA_ENUM_START + ((x) * SIBA_CORE_LEN)) -#define SIBA_CORE_LEN 0x00001000 /* Size of cfg per core */ -#define SIBA_CFG_END 0x00010000 /* Upper bound of cfg space */ -#define SIBA_MAX_CORES (SIBA_CFG_END/SIBA_CORE_LEN) /* #max cores */ -#define SIBA_ENUM_START 0x18000000U -#define SIBA_ENUM_END 0x18010000U - -#define SIBA_DMA_TRANSLATION_MASK 0xc0000000 - -#define SIBA_PCI_DMA 0x40000000U -#define SIBA_TPS 0x0f18 -#define SIBA_TPS_BPFLAG 0x0000003f -#define SIBA_IAS 0x0f90 /* Initiator Agent State */ -#define SIBA_IAS_INBAND_ERR 0x00020000 -#define SIBA_IAS_TIMEOUT 0x00040000 -#define SIBA_INTR_MASK 0x0f94 -#define SIBA_TGSLOW 0x0f98 -#define SIBA_TGSLOW_RESET 0x00000001 /* target state low */ -#define SIBA_TGSLOW_REJECT_22 0x00000002 -#define SIBA_TGSLOW_REJECT_23 0x00000004 -#define SIBA_TGSLOW_CLOCK 0x00010000 -#define SIBA_TGSLOW_FGC 0x00020000 -#define SIBA_TGSHIGH 0x0f9c -#define SIBA_TGSHIGH_SERR 0x00000001 -#define SIBA_TGSHIGH_BUSY 0x00000004 -#define SIBA_TGSHIGH_DMA64 0x10000000 -#define SIBA_IMCFGLO 0x0fa8 -#define SIBA_IMCFGLO_SERTO 0x00000007 -#define SIBA_IMCFGLO_REQTO 0x00000070 -#define SIBA_IDLOW 0x0ff8 -#define SIBA_IDLOW_SSBREV 0xf0000000 -#define SIBA_IDLOW_SSBREV_22 0x00000000 -#define SIBA_IDLOW_SSBREV_23 0x10000000 -#define SIBA_IDLOW_SSBREV_24 0x40000000 -#define SIBA_IDLOW_SSBREV_25 0x50000000 -#define SIBA_IDLOW_SSBREV_26 0x60000000 -#define SIBA_IDLOW_SSBREV_27 0x70000000 -#define SIBA_IDHIGH 0x0ffc -#define SIBA_IDHIGH_CORECODEMASK 0x00008FF0 /* Core Code */ -#define SIBA_IDHIGH_CORECODE_SHIFT 4 -#define SIBA_IDHIGH_CORECODE(id) \ - ((id & SIBA_IDHIGH_CORECODEMASK) >> SIBA_IDHIGH_CORECODE_SHIFT) -/* Revision Code (low part) */ -#define SIBA_IDHIGH_REVLO 0x0000000f -/* Revision Code (high part) */ -#define SIBA_IDHIGH_REVHI 0x00007000 -#define SIBA_IDHIGH_REVHI_SHIFT 8 -#define SIBA_IDHIGH_REV(id) \ - ((id & SIBA_IDHIGH_REVLO) | ((id & SIBA_IDHIGH_REVHI) >> \ - SIBA_IDHIGH_REVHI_SHIFT)) -#define SIBA_IDHIGH_VENDORMASK 0xFFFF0000 /* Vendor Code */ -#define SIBA_IDHIGH_VENDOR_SHIFT 16 -#define SIBA_IDHIGH_VENDOR(id) \ - ((id & SIBA_IDHIGH_VENDORMASK) >> SIBA_IDHIGH_VENDOR_SHIFT) - -#define SIBA_SPROMSIZE_R123 64 -#define SIBA_SPROMSIZE_R4 220 -#define SIBA_SPROM_BASE 0x1000 -#define SIBA_SPROM_REV_CRC 0xff00 - -#define SIBA_SPROM1_MAC_80211BG 0x1048 -#define SIBA_SPROM1_MAC_ETH 0x104e -#define SIBA_SPROM1_MAC_80211A 0x1054 -#define SIBA_SPROM1_ETHPHY 0x105a -#define SIBA_SPROM1_ETHPHY_MII_ETH0 0x001f -#define SIBA_SPROM1_ETHPHY_MII_ETH1 0x03e0 -#define SIBA_SPROM1_ETHPHY_MDIO_ETH0 (1 << 14) -#define SIBA_SPROM1_ETHPHY_MDIO_ETH1 (1 << 15) -#define SIBA_SPROM1_BOARDINFO 0x105c -#define SIBA_SPROM1_BOARDINFO_BREV 0x00ff -#define SIBA_SPROM1_BOARDINFO_CCODE 0x0f00 -#define SIBA_SPROM1_BOARDINFO_ANTBG 0x3000 -#define SIBA_SPROM1_BOARDINFO_ANTA 0xc000 -#define SIBA_SPROM1_PA0B0 0x105e -#define SIBA_SPROM1_PA0B1 0x1060 -#define SIBA_SPROM1_PA0B2 0x1062 -#define SIBA_SPROM1_GPIOA 0x1064 -#define SIBA_SPROM1_GPIOA_P0 0x00ff -#define SIBA_SPROM1_GPIOA_P1 0xff00 -#define SIBA_SPROM1_GPIOB 0x1066 -#define SIBA_SPROM1_GPIOB_P2 0x00ff -#define SIBA_SPROM1_GPIOB_P3 0xff00 -#define SIBA_SPROM1_MAXPWR 0x1068 -#define SIBA_SPROM1_MAXPWR_BG 0x00ff -#define SIBA_SPROM1_MAXPWR_A 0xff00 -#define SIBA_SPROM1_PA1B0 0x106a -#define SIBA_SPROM1_PA1B1 0x106c -#define SIBA_SPROM1_PA1B2 0x106e -#define SIBA_SPROM1_TSSI 0x1070 -#define SIBA_SPROM1_TSSI_BG 0x00ff -#define SIBA_SPROM1_TSSI_A 0xff00 -#define SIBA_SPROM1_BFLOW 0x1072 -#define SIBA_SPROM1_AGAIN 0x1074 -#define SIBA_SPROM1_AGAIN_BG 0x00ff -#define SIBA_SPROM1_AGAIN_A 0xff00 - -#define SIBA_SPROM2_BFHIGH 0x1038 - -#define SIBA_SPROM3_MAC_80211BG 0x104a - -#define SIBA_SPROM4_MAC_80211BG 0x104c -#define SIBA_SPROM4_ETHPHY 0x105a -#define SIBA_SPROM4_ETHPHY_ET0A 0x001f -#define SIBA_SPROM4_ETHPHY_ET1A 0x03e0 -#define SIBA_SPROM4_CCODE 0x1052 -#define SIBA_SPROM4_ANTAVAIL 0x105d -#define SIBA_SPROM4_ANTAVAIL_A 0x00ff -#define SIBA_SPROM4_ANTAVAIL_BG 0xff00 -#define SIBA_SPROM4_BFLOW 0x1044 -#define SIBA_SPROM4_AGAIN01 0x105e -#define SIBA_SPROM4_AGAIN0 0x00ff -#define SIBA_SPROM4_AGAIN1 0xff00 -#define SIBA_SPROM4_AGAIN23 0x1060 -#define SIBA_SPROM4_AGAIN2 0x00ff -#define SIBA_SPROM4_AGAIN3 0xff00 -#define SIBA_SPROM4_TXPID2G01 0x0062 -#define SIBA_SPROM4_TXPID2G0 0x00ff -#define SIBA_SPROM4_TXPID2G1 0xff00 -#define SIBA_SPROM4_TXPID2G23 0x0064 -#define SIBA_SPROM4_TXPID2G2 0x00ff -#define SIBA_SPROM4_TXPID2G3 0xff00 -#define SIBA_SPROM4_TXPID5G01 0x0066 -#define SIBA_SPROM4_TXPID5G0 0x00ff -#define SIBA_SPROM4_TXPID5G1 0xff00 -#define SIBA_SPROM4_TXPID5G23 0x0068 -#define SIBA_SPROM4_TXPID5G2 0x00ff -#define SIBA_SPROM4_TXPID5G3 0xff00 -#define SIBA_SPROM4_TXPID5GL01 0x006a -#define SIBA_SPROM4_TXPID5GL0 0x00ff -#define SIBA_SPROM4_TXPID5GL1 0xff00 -#define SIBA_SPROM4_TXPID5GL23 0x006c -#define SIBA_SPROM4_TXPID5GL2 0x00ff -#define SIBA_SPROM4_TXPID5GL3 0xff00 -#define SIBA_SPROM4_TXPID5GH01 0x006e -#define SIBA_SPROM4_TXPID5GH0 0x00ff -#define SIBA_SPROM4_TXPID5GH1 0xff00 -#define SIBA_SPROM4_TXPID5GH23 0x0070 -#define SIBA_SPROM4_TXPID5GH2 0x00ff -#define SIBA_SPROM4_TXPID5GH3 0xff00 -#define SIBA_SPROM4_BFHIGH 0x1046 -#define SIBA_SPROM4_MAXP_BG 0x1080 -#define SIBA_SPROM4_MAXP_BG_MASK 0x00ff -#define SIBA_SPROM4_TSSI_BG 0xff00 -#define SIBA_SPROM4_MAXP_A 0x108a -#define SIBA_SPROM4_MAXP_A_MASK 0x00ff -#define SIBA_SPROM4_TSSI_A 0xff00 -#define SIBA_SPROM4_GPIOA 0x1056 -#define SIBA_SPROM4_GPIOA_P0 0x00ff -#define SIBA_SPROM4_GPIOA_P1 0xff00 -#define SIBA_SPROM4_GPIOB 0x1058 -#define SIBA_SPROM4_GPIOB_P2 0x00ff -#define SIBA_SPROM4_GPIOB_P3 0xff00 - -/* The following four blocks share the same structure */ -#define SIBA_SPROM4_PWR_INFO_CORE0 0x1080 -#define SIBA_SPROM4_PWR_INFO_CORE1 0x10AE -#define SIBA_SPROM4_PWR_INFO_CORE2 0x10DC -#define SIBA_SPROM4_PWR_INFO_CORE3 0x110A - -#define SIBA_SPROM4_2G_MAXP_ITSSI 0x00 /* 2 GHz ITSSI and 2 GHz Max Power */ -#define SIBA_SPROM4_2G_MAXP 0x00FF -#define SIBA_SPROM4_2G_ITSSI 0xFF00 -#define SIBA_SPROM4_2G_ITSSI_SHIFT 8 -#define SIBA_SPROM4_2G_PA_0 0x02 /* 2 GHz power amp */ -#define SIBA_SPROM4_2G_PA_1 0x04 -#define SIBA_SPROM4_2G_PA_2 0x06 -#define SIBA_SPROM4_2G_PA_3 0x08 -#define SIBA_SPROM4_5G_MAXP_ITSSI 0x0A /* 5 GHz ITSSI and 5.3 GHz Max Power */ -#define SIBA_SPROM4_5G_MAXP 0x00FF -#define SIBA_SPROM4_5G_ITSSI 0xFF00 -#define SIBA_SPROM4_5G_ITSSI_SHIFT 8 -#define SIBA_SPROM4_5GHL_MAXP 0x0C /* 5.2 GHz and 5.8 GHz Max Power */ -#define SIBA_SPROM4_5GH_MAXP 0x00FF -#define SIBA_SPROM4_5GL_MAXP 0xFF00 -#define SIBA_SPROM4_5GL_MAXP_SHIFT 8 -#define SIBA_SPROM4_5G_PA_0 0x0E /* 5.3 GHz power amp */ -#define SIBA_SPROM4_5G_PA_1 0x10 -#define SIBA_SPROM4_5G_PA_2 0x12 -#define SIBA_SPROM4_5G_PA_3 0x14 -#define SIBA_SPROM4_5GL_PA_0 0x16 /* 5.2 GHz power amp */ -#define SIBA_SPROM4_5GL_PA_1 0x18 -#define SIBA_SPROM4_5GL_PA_2 0x1A -#define SIBA_SPROM4_5GL_PA_3 0x1C -#define SIBA_SPROM4_5GH_PA_0 0x1E /* 5.8 GHz power amp */ -#define SIBA_SPROM4_5GH_PA_1 0x20 -#define SIBA_SPROM4_5GH_PA_2 0x22 -#define SIBA_SPROM4_5GH_PA_3 0x24 - -#define SIBA_SPROM5_BFLOW 0x104a -#define SIBA_SPROM5_BFHIGH 0x104c -#define SIBA_SPROM5_MAC_80211BG 0x1052 -#define SIBA_SPROM5_CCODE 0x1044 -#define SIBA_SPROM5_GPIOA 0x1076 -#define SIBA_SPROM5_GPIOA_P0 0x00ff -#define SIBA_SPROM5_GPIOA_P1 0xff00 -#define SIBA_SPROM5_GPIOB 0x1078 -#define SIBA_SPROM5_GPIOB_P2 0x00ff -#define SIBA_SPROM5_GPIOB_P3 0xff00 - -#define SIBA_SPROM8_BFLOW 0x1084 -#define SIBA_SPROM8_BFHIGH 0x1086 -#define SIBA_SPROM8_BFL2LO 0x1088 -#define SIBA_SPROM8_BFL2HI 0x108a -#define SIBA_SPROM8_MAC_80211BG 0x108c -#define SIBA_SPROM8_CCODE 0x1092 -#define SIBA_SPROM8_ANTAVAIL 0x109c -#define SIBA_SPROM8_ANTAVAIL_A 0xff00 -#define SIBA_SPROM8_ANTAVAIL_BG 0x00ff -#define SIBA_SPROM8_AGAIN01 0x109e -#define SIBA_SPROM8_AGAIN0 0x00ff -#define SIBA_SPROM8_AGAIN1 0xff00 -#define SIBA_SPROM8_GPIOA 0x1096 -#define SIBA_SPROM8_GPIOA_P0 0x00ff -#define SIBA_SPROM8_GPIOA_P1 0xff00 -#define SIBA_SPROM8_GPIOB 0x1098 -#define SIBA_SPROM8_GPIOB_P2 0x00ff -#define SIBA_SPROM8_GPIOB_P3 0xff00 -#define SIBA_SPROM8_AGAIN23 0x10a0 -#define SIBA_SPROM8_AGAIN2 0x00ff -#define SIBA_SPROM8_AGAIN3 0xff00 -#define SIBA_SPROM8_RSSIPARM2G 0x10a4 -#define SIBA_SPROM8_RSSISMF2G 0x000f -#define SIBA_SPROM8_RSSISMC2G 0x00f0 -#define SIBA_SPROM8_RSSISAV2G 0x0700 /* BITMASK */ -#define SIBA_SPROM8_BXA2G 0x1800 /* BITMASK */ -#define SIBA_SPROM8_RSSIPARM5G 0x10a6 -#define SIBA_SPROM8_RSSISMF5G 0x000f -#define SIBA_SPROM8_RSSISMC5G 0x00f0 -#define SIBA_SPROM8_RSSISAV5G 0x0700 /* BITMASK */ -#define SIBA_SPROM8_BXA5G 0x1800 /* BITMASK */ -#define SIBA_SPROM8_TRI25G 0x10a8 -#define SIBA_SPROM8_TRI2G 0x00ff -#define SIBA_SPROM8_TRI5G 0xff00 -#define SIBA_SPROM8_TRI5GHL 0x10aa -#define SIBA_SPROM8_TRI5GL 0x00ff -#define SIBA_SPROM8_TRI5GH 0xff00 -#define SIBA_SPROM8_RXPO 0x10ac -#define SIBA_SPROM8_RXPO2G 0x00ff -#define SIBA_SPROM8_RXPO5G 0xff00 - -/* The FEM blocks share the same structure */ -#define SIBA_SPROM8_FEM2G 0x10ae -#define SIBA_SPROM8_FEM5G 0x10b0 -#define SIBA_SROM8_FEM_TSSIPOS 0x0001 -#define SIBA_SROM8_FEM_EXTPA_GAIN 0x0006 -#define SIBA_SROM8_FEM_PDET_RANGE 0x00F8 -#define SIBA_SROM8_FEM_TR_ISO 0x0700 -#define SIBA_SROM8_FEM_ANTSWLUT 0xF800 - -#define SIBA_SPROM8_MAXP_BG 0x10c0 -#define SIBA_SPROM8_MAXP_BG_MASK 0x00ff -#define SIBA_SPROM8_TSSI_BG 0xff00 -#define SIBA_SPROM8_PA0B0 0x10c2 -#define SIBA_SPROM8_PA0B1 0x10c4 -#define SIBA_SPROM8_PA0B2 0x10c6 -#define SIBA_SPROM8_MAXP_A 0x10c8 -#define SIBA_SPROM8_MAXP_A_MASK 0x00ff -#define SIBA_SPROM8_TSSI_A 0xff00 -#define SIBA_SPROM8_MAXP_AHL 0x10ca -#define SIBA_SPROM8_MAXP_AH_MASK 0x00ff -#define SIBA_SPROM8_MAXP_AL_MASK 0xff00 -#define SIBA_SPROM8_PA1B0 0x10cc -#define SIBA_SPROM8_PA1B1 0x10ce -#define SIBA_SPROM8_PA1B2 0x10d0 -#define SIBA_SPROM8_PA1LOB0 0x10d2 -#define SIBA_SPROM8_PA1LOB1 0x10d4 -#define SIBA_SPROM8_PA1LOB2 0x10d6 -#define SIBA_SPROM8_PA1HIB0 0x10d8 -#define SIBA_SPROM8_PA1HIB1 0x10da -#define SIBA_SPROM8_PA1HIB2 0x10dc -#define SIBA_SPROM8_CCK2GPO 0x1140 -#define SIBA_SPROM8_OFDM2GPO 0x1142 -#define SIBA_SPROM8_OFDM5GPO 0x1146 -#define SIBA_SPROM8_OFDM5GLPO 0x114a -#define SIBA_SPROM8_OFDM5GHPO 0x114e -#define SIBA_SPROM8_CDDPO 0x0192 -#define SIBA_SPROM8_STBCPO 0x0194 -#define SIBA_SPROM8_BW40PO 0x0196 -#define SIBA_SPROM8_BWDUPPO 0x0198 - -/* There are 4 blocks with power info sharing the same layout */ -#define SIBA_SROM8_PWR_INFO_CORE0 0x10C0 -#define SIBA_SROM8_PWR_INFO_CORE1 0x10E0 -#define SIBA_SROM8_PWR_INFO_CORE2 0x1100 -#define SIBA_SROM8_PWR_INFO_CORE3 0x1120 - -#define SIBA_SROM8_2G_MAXP_ITSSI 0x00 -#define SIBA_SPROM8_2G_MAXP 0x00FF -#define SIBA_SPROM8_2G_ITSSI 0xFF00 -#define SIBA_SPROM8_2G_ITSSI_SHIFT 8 -#define SIBA_SROM8_2G_PA_0 0x02 /* 2GHz power amp settings */ -#define SIBA_SROM8_2G_PA_1 0x04 -#define SIBA_SROM8_2G_PA_2 0x06 -#define SIBA_SROM8_5G_MAXP_ITSSI 0x08 /* 5GHz ITSSI and 5.3GHz Max Power */ -#define SIBA_SPROM8_5G_MAXP 0x00FF -#define SIBA_SPROM8_5G_ITSSI 0xFF00 -#define SIBA_SPROM8_5G_ITSSI_SHIFT 8 -#define SIBA_SPROM8_5GHL_MAXP 0x0A /* 5.2GHz and 5.8GHz Max Power */ -#define SIBA_SPROM8_5GH_MAXP 0x00FF -#define SIBA_SPROM8_5GL_MAXP 0xFF00 -#define SIBA_SPROM8_5GL_MAXP_SHIFT 8 -#define SIBA_SROM8_5G_PA_0 0x0C /* 5.3GHz power amp settings */ -#define SIBA_SROM8_5G_PA_1 0x0E -#define SIBA_SROM8_5G_PA_2 0x10 -#define SIBA_SROM8_5GL_PA_0 0x12 /* 5.2GHz power amp settings */ -#define SIBA_SROM8_5GL_PA_1 0x14 -#define SIBA_SROM8_5GL_PA_2 0x16 -#define SIBA_SROM8_5GH_PA_0 0x18 /* 5.8GHz power amp settings */ -#define SIBA_SROM8_5GH_PA_1 0x1A -#define SIBA_SROM8_5GH_PA_2 0x1C - -#define SIBA_BOARDVENDOR_DELL 0x1028 -#define SIBA_BOARDVENDOR_BCM 0x14e4 -#define SIBA_BOARD_BCM4309G 0x0421 -#define SIBA_BOARD_MP4318 0x044a -#define SIBA_BOARD_BU4306 0x0416 -#define SIBA_BOARD_BU4309 0x040a -#define SIBA_BOARD_BCM4321 0x046d - -#define SIBA_PCICORE_BCAST_ADDR SIBA_CC_BCAST_ADDR -#define SIBA_PCICORE_BCAST_DATA SIBA_CC_BCAST_DATA -#define SIBA_PCICORE_SBTOPCI0 0x0100 -#define SIBA_PCICORE_SBTOPCI1 0x0104 -#define SIBA_PCICORE_SBTOPCI2 0x0108 -#define SIBA_PCICORE_MDIO_CTL 0x0128 -#define SIBA_PCICORE_MDIO_DATA 0x012c -#define SIBA_PCICORE_SBTOPCI_PREF 0x00000004 -#define SIBA_PCICORE_SBTOPCI_BURST 0x00000008 -#define SIBA_PCICORE_SBTOPCI_MRM 0x00000020 - -#define SIBA_CHIPPACK_BCM4712S 1 /* Small 200pin 4712 */ - -#endif /* _SIBA_SIBAREG_H_ */ Property changes on: head/sys/dev/siba/sibareg.h ___________________________________________________________________ Deleted: svn:eol-style ## -1 +0,0 ## -native \ No newline at end of property Deleted: svn:keywords ## -1 +0,0 ## -FreeBSD=%H \ No newline at end of property Deleted: svn:mime-type ## -1 +0,0 ## -text/plain \ No newline at end of property Index: head/sys/dev/siba/siba_ids.h =================================================================== --- head/sys/dev/siba/siba_ids.h (revision 328911) +++ head/sys/dev/siba/siba_ids.h (nonexistent) @@ -1,95 +0,0 @@ -/*- - * SPDX-License-Identifier: BSD-2-Clause-FreeBSD - * - * Copyright (c) 2007 Bruce M. Simpson. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - * - * $FreeBSD$ - */ - -#ifndef _SIBA_SIBA_IDS_H_ -#define _SIBA_SIBA_IDS_H_ - -/* - * Constants and structures for SiBa bus enumeration. - */ - -struct siba_devid { - uint16_t sd_vendor; - uint16_t sd_device; - uint8_t sd_rev; - char *sd_desc; -}; -#define SIBA_DEV(_vendor, _cid, _rev, _msg) \ - { SIBA_VID_##_vendor, SIBA_DEVID_##_cid, _rev, _msg } - -/* - * Device IDs - */ -#define SIBA_DEVID_ANY 0xffff -#define SIBA_DEVID_CHIPCOMMON 0x800 -#define SIBA_DEVID_ILINE20 0x801 -#define SIBA_DEVID_SDRAM 0x803 -#define SIBA_DEVID_PCI 0x804 -#define SIBA_DEVID_MIPS 0x805 -#define SIBA_DEVID_ETHERNET 0x806 -#define SIBA_DEVID_MODEM 0x807 -#define SIBA_DEVID_USB11_HOSTDEV 0x808 -#define SIBA_DEVID_ADSL 0x809 -#define SIBA_DEVID_ILINE100 0x80a -#define SIBA_DEVID_IPSEC 0x80b -#define SIBA_DEVID_PCMCIA 0x80d -#define SIBA_DEVID_INTERNAL_MEM 0x80e -#define SIBA_DEVID_SDRAMDDR 0x80f -#define SIBA_DEVID_EXTIF 0x811 -#define SIBA_DEVID_80211 0x812 -#define SIBA_DEVID_MIPS_3302 0x816 -#define SIBA_DEVID_USB11_HOST 0x817 -#define SIBA_DEVID_USB11_DEV 0x818 -#define SIBA_DEVID_USB20_HOST 0x819 -#define SIBA_DEVID_USB20_DEV 0x81a -#define SIBA_DEVID_SDIO_HOST 0x81b -#define SIBA_DEVID_ROBOSWITCH 0x81c -#define SIBA_DEVID_PARA_ATA 0x81d -#define SIBA_DEVID_SATA_XORDMA 0x81e -#define SIBA_DEVID_ETHERNET_GBIT 0x81f -#define SIBA_DEVID_PCIE 0x820 -#define SIBA_DEVID_MIMO_PHY 0x821 -#define SIBA_DEVID_SRAM_CTRLR 0x822 -#define SIBA_DEVID_MINI_MACPHY 0x823 -#define SIBA_DEVID_ARM_1176 0x824 -#define SIBA_DEVID_ARM_7TDMI 0x825 - -/* - * Vendor IDs - */ -#define SIBA_VID_ANY 0xffff -#define SIBA_VID_BROADCOM 0x4243 - -/* - * Revision IDs - */ -#define SIBA_REV_ANY 0xff - -#endif /*_SIBA_SIBA_IDS_H_ */ Property changes on: head/sys/dev/siba/siba_ids.h ___________________________________________________________________ Deleted: svn:eol-style ## -1 +0,0 ## -native \ No newline at end of property Deleted: svn:keywords ## -1 +0,0 ## -FreeBSD=%H \ No newline at end of property Deleted: svn:mime-type ## -1 +0,0 ## -text/plain \ No newline at end of property Index: head/sys/dev/siba/sibavar.h =================================================================== --- head/sys/dev/siba/sibavar.h (revision 328911) +++ head/sys/dev/siba/sibavar.h (nonexistent) @@ -1,676 +0,0 @@ -/*- - * SPDX-License-Identifier: BSD-2-Clause-FreeBSD - * - * Copyright (c) 2007 Bruce M. Simpson. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - * - * $FreeBSD$ - */ - -#ifndef _SIBA_SIBAVAR_H_ -#define _SIBA_SIBAVAR_H_ - -#include - -struct siba_softc; -struct siba_dev_softc; - -enum siba_type { - SIBA_TYPE_SSB, - SIBA_TYPE_PCI, - SIBA_TYPE_PCMCIA, -}; - -enum siba_device_ivars { - SIBA_IVAR_VENDOR, - SIBA_IVAR_DEVICE, - SIBA_IVAR_REVID, - SIBA_IVAR_CORE_INDEX, - SIBA_IVAR_PCI_VENDOR, - SIBA_IVAR_PCI_DEVICE, - SIBA_IVAR_PCI_SUBVENDOR, - SIBA_IVAR_PCI_SUBDEVICE, - SIBA_IVAR_PCI_REVID, - SIBA_IVAR_CHIPID, - SIBA_IVAR_CHIPREV, - SIBA_IVAR_CHIPPKG, - SIBA_IVAR_TYPE, - SIBA_IVAR_CC_PMUFREQ, - SIBA_IVAR_CC_CAPS, - SIBA_IVAR_CC_POWERDELAY, - SIBA_IVAR_PCICORE_REVID -}; - -#define SIBA_ACCESSOR(var, ivar, type) \ - __BUS_ACCESSOR(siba, var, SIBA, ivar, type) - -SIBA_ACCESSOR(vendor, VENDOR, uint16_t) -SIBA_ACCESSOR(device, DEVICE, uint16_t) -SIBA_ACCESSOR(revid, REVID, uint8_t) -SIBA_ACCESSOR(core_index, CORE_INDEX, uint8_t) -SIBA_ACCESSOR(pci_vendor, PCI_VENDOR, uint16_t) -SIBA_ACCESSOR(pci_device, PCI_DEVICE, uint16_t) -SIBA_ACCESSOR(pci_subvendor, PCI_SUBVENDOR, uint16_t) -SIBA_ACCESSOR(pci_subdevice, PCI_SUBDEVICE, uint16_t) -SIBA_ACCESSOR(pci_revid, PCI_REVID, uint8_t) -SIBA_ACCESSOR(chipid, CHIPID, uint16_t) -SIBA_ACCESSOR(chiprev, CHIPREV, uint16_t) -SIBA_ACCESSOR(chippkg, CHIPPKG, uint8_t) -SIBA_ACCESSOR(type, TYPE, enum siba_type) -SIBA_ACCESSOR(cc_pmufreq, CC_PMUFREQ, uint32_t) -SIBA_ACCESSOR(cc_caps, CC_CAPS, uint32_t) -SIBA_ACCESSOR(cc_powerdelay, CC_POWERDELAY, uint16_t) -SIBA_ACCESSOR(pcicore_revid, PCICORE_REVID, uint8_t) - -#undef SIBA_ACCESSOR - -/* XXX just for SPROM1? */ -enum { - SIBA_CCODE_WORLD, - SIBA_CCODE_THAILAND, - SIBA_CCODE_ISRAEL, - SIBA_CCODE_JORDAN, - SIBA_CCODE_CHINA, - SIBA_CCODE_JAPAN, - SIBA_CCODE_USA_CANADA_ANZ, - SIBA_CCODE_EUROPE, - SIBA_CCODE_USA_LOW, - SIBA_CCODE_JAPAN_HIGH, - SIBA_CCODE_ALL, - SIBA_CCODE_NONE, -}; - -#define siba_mips_read_2(sc, core, reg) \ - bus_space_read_2((sc)->siba_mem_bt, (sc)->siba_mem_bh, \ - (core * SIBA_CORE_LEN) + (reg)) - -#define siba_mips_read_4(sc, core, reg) \ - bus_space_read_4((sc)->siba_mem_bt, (sc)->siba_mem_bh, \ - (core * SIBA_CORE_LEN) + (reg)) - -#define siba_mips_write_2(sc, core, reg, val) \ - bus_space_write_2((sc)->siba_mem_bt, (sc)->siba_mem_bh, \ - (core * SIBA_CORE_LEN) + (reg), (val)) - -#define siba_mips_write_4(sc, core, reg, val) \ - bus_space_write_4((sc)->siba_mem_bt, (sc)->siba_mem_bh, \ - (core * SIBA_CORE_LEN) + (reg), (val)) - -#define SIBA_READ_4(siba, reg) \ - bus_space_read_4((siba)->siba_mem_bt, (siba)->siba_mem_bh, (reg)) -#define SIBA_READ_2(siba, reg) \ - bus_space_read_2((siba)->siba_mem_bt, (siba)->siba_mem_bh, (reg)) -#define SIBA_READ_MULTI_1(siba, reg, addr, count) \ - bus_space_read_multi_1((siba)->siba_mem_bt, (siba)->siba_mem_bh,\ - (reg), (addr), (count)) -#define SIBA_READ_MULTI_2(siba, reg, addr, count) \ - bus_space_read_multi_2((siba)->siba_mem_bt, (siba)->siba_mem_bh,\ - (reg), (addr), (count)) -#define SIBA_READ_MULTI_4(siba, reg, addr, count) \ - bus_space_read_multi_4((siba)->siba_mem_bt, (siba)->siba_mem_bh,\ - (reg), (addr), (count)) - -#define SIBA_WRITE_4(siba, reg, val) \ - bus_space_write_4((siba)->siba_mem_bt, (siba)->siba_mem_bh, \ - (reg), (val)) -#define SIBA_WRITE_2(siba, reg, val) \ - bus_space_write_2((siba)->siba_mem_bt, (siba)->siba_mem_bh, \ - (reg), (val)) -#define SIBA_WRITE_MULTI_1(siba, reg, addr, count) \ - bus_space_write_multi_1((siba)->siba_mem_bt, (siba)->siba_mem_bh,\ - (reg), (addr), (count)) -#define SIBA_WRITE_MULTI_2(siba, reg, addr, count) \ - bus_space_write_multi_2((siba)->siba_mem_bt, (siba)->siba_mem_bh,\ - (reg), (addr), (count)) -#define SIBA_WRITE_MULTI_4(siba, reg, addr, count) \ - bus_space_write_multi_4((siba)->siba_mem_bt, (siba)->siba_mem_bh,\ - (reg), (addr), (count)) - -#define SIBA_BARRIER(siba, flags) \ - bus_space_barrier((siba)->siba_mem_bt, (siba)->siba_mem_bh, (0),\ - (0), (flags)) - -#define SIBA_SETBITS_4(siba, reg, bits) \ - SIBA_WRITE_4((siba), (reg), SIBA_READ_4((siba), (reg)) | (bits)) -#define SIBA_SETBITS_2(siba, reg, bits) \ - SIBA_WRITE_2((siba), (reg), SIBA_READ_2((siba), (reg)) | (bits)) - -#define SIBA_FILT_SETBITS_4(siba, reg, filt, bits) \ - SIBA_WRITE_4((siba), (reg), (SIBA_READ_4((siba), \ - (reg)) & (filt)) | (bits)) -#define SIBA_FILT_SETBITS_2(siba, reg, filt, bits) \ - SIBA_WRITE_2((siba), (reg), (SIBA_READ_2((siba), \ - (reg)) & (filt)) | (bits)) - -#define SIBA_CLRBITS_4(siba, reg, bits) \ - SIBA_WRITE_4((siba), (reg), SIBA_READ_4((siba), (reg)) & ~(bits)) -#define SIBA_CLRBITS_2(siba, reg, bits) \ - SIBA_WRITE_2((siba), (reg), SIBA_READ_2((siba), (reg)) & ~(bits)) - -#define SIBA_CC_READ32(scc, offset) \ - siba_read_4_sub((scc)->scc_dev, offset) -#define SIBA_CC_WRITE32(scc, offset, val) \ - siba_write_4_sub((scc)->scc_dev, offset, val) -#define SIBA_CC_MASK32(scc, offset, mask) \ - SIBA_CC_WRITE32(scc, offset, SIBA_CC_READ32(scc, offset) & (mask)) -#define SIBA_CC_SET32(scc, offset, set) \ - SIBA_CC_WRITE32(scc, offset, SIBA_CC_READ32(scc, offset) | (set)) -#define SIBA_CC_MASKSET32(scc, offset, mask, set) \ - SIBA_CC_WRITE32(scc, offset, \ - (SIBA_CC_READ32(scc, offset) & (mask)) | (set)) - -enum siba_clock { - SIBA_CLOCK_DYNAMIC, - SIBA_CLOCK_SLOW, - SIBA_CLOCK_FAST, -}; - -enum siba_clksrc { - SIBA_CC_CLKSRC_PCI, - SIBA_CC_CLKSRC_CRYSTAL, - SIBA_CC_CLKSRC_LOWPW, -}; - -struct siba_cc_pmu0_plltab { - uint16_t freq; /* in kHz.*/ - uint8_t xf; /* crystal frequency */ - uint8_t wb_int; - uint32_t wb_frac; -}; - -struct siba_cc_pmu1_plltab { - uint16_t freq; - uint8_t xf; - uint8_t p1div; - uint8_t p2div; - uint8_t ndiv_int; - uint32_t ndiv_frac; -}; - -struct siba_cc_pmu_res_updown { - uint8_t res; - uint16_t updown; -}; - -#define SIBA_CC_PMU_DEP_SET 1 -#define SIBA_CC_PMU_DEP_ADD 2 -#define SIBA_CC_PMU_DEP_REMOVE 3 - -struct siba_cc_pmu_res_depend { - uint8_t res; - uint8_t task; - uint32_t depend; -}; - -enum siba_sprom_vars { - SIBA_SPROMVAR_REV, - SIBA_SPROMVAR_MAC_80211BG, - SIBA_SPROMVAR_MAC_ETH, - SIBA_SPROMVAR_MAC_80211A, - SIBA_SPROMVAR_MII_ETH0, - SIBA_SPROMVAR_MII_ETH1, - SIBA_SPROMVAR_MDIO_ETH0, - SIBA_SPROMVAR_MDIO_ETH1, - SIBA_SPROMVAR_BREV, - SIBA_SPROMVAR_CCODE, - SIBA_SPROMVAR_ANT_A, - SIBA_SPROMVAR_ANT_BG, - SIBA_SPROMVAR_PA0B0, - SIBA_SPROMVAR_PA0B1, - SIBA_SPROMVAR_PA0B2, - SIBA_SPROMVAR_PA1B0, - SIBA_SPROMVAR_PA1B1, - SIBA_SPROMVAR_PA1B2, - SIBA_SPROMVAR_PA1LOB0, - SIBA_SPROMVAR_PA1LOB1, - SIBA_SPROMVAR_PA1LOB2, - SIBA_SPROMVAR_PA1HIB0, - SIBA_SPROMVAR_PA1HIB1, - SIBA_SPROMVAR_PA1HIB2, - SIBA_SPROMVAR_GPIO0, - SIBA_SPROMVAR_GPIO1, - SIBA_SPROMVAR_GPIO2, - SIBA_SPROMVAR_GPIO3, - SIBA_SPROMVAR_MAXPWR_AL, - SIBA_SPROMVAR_MAXPWR_A, - SIBA_SPROMVAR_MAXPWR_AH, - SIBA_SPROMVAR_MAXPWR_BG, - SIBA_SPROMVAR_RXPO2G, - SIBA_SPROMVAR_RXPO5G, - SIBA_SPROMVAR_TSSI_A, - SIBA_SPROMVAR_TSSI_BG, - SIBA_SPROMVAR_TRI2G, - SIBA_SPROMVAR_TRI5GL, - SIBA_SPROMVAR_TRI5G, - SIBA_SPROMVAR_TRI5GH, - SIBA_SPROMVAR_RSSISAV2G, - SIBA_SPROMVAR_RSSISMC2G, - SIBA_SPROMVAR_RSSISMF2G, - SIBA_SPROMVAR_BXA2G, - SIBA_SPROMVAR_RSSISAV5G, - SIBA_SPROMVAR_RSSISMC5G, - SIBA_SPROMVAR_RSSISMF5G, - SIBA_SPROMVAR_BXA5G, - SIBA_SPROMVAR_CCK2GPO, - SIBA_SPROMVAR_OFDM2GPO, - SIBA_SPROMVAR_OFDM5GLPO, - SIBA_SPROMVAR_OFDM5GPO, - SIBA_SPROMVAR_OFDM5GHPO, - SIBA_SPROMVAR_BF_LO, - SIBA_SPROMVAR_BF_HI, - SIBA_SPROMVAR_BF2_LO, - SIBA_SPROMVAR_BF2_HI, - SIBA_SPROMVAR_FEM_2GHZ_TSSIPOS, - SIBA_SPROMVAR_FEM_2GHZ_EXTPAGAIN, - SIBA_SPROMVAR_FEM_2GHZ_PDET_RANGE, - SIBA_SPROMVAR_FEM_2GHZ_TR_ISO, - SIBA_SPROMVAR_FEM_2GHZ_ANTSWLUT, - SIBA_SPROMVAR_FEM_5GHZ_TSSIPOS, - SIBA_SPROMVAR_FEM_5GHZ_EXTPAGAIN, - SIBA_SPROMVAR_FEM_5GHZ_PDET_RANGE, - SIBA_SPROMVAR_FEM_5GHZ_TR_ISO, - SIBA_SPROMVAR_FEM_5GHZ_ANTSWLUT, - SIBA_SPROMVAR_TXPID_2G_0, - SIBA_SPROMVAR_TXPID_2G_1, - SIBA_SPROMVAR_TXPID_2G_2, - SIBA_SPROMVAR_TXPID_2G_3, - SIBA_SPROMVAR_TXPID_5GL_0, - SIBA_SPROMVAR_TXPID_5GL_1, - SIBA_SPROMVAR_TXPID_5GL_2, - SIBA_SPROMVAR_TXPID_5GL_3, - SIBA_SPROMVAR_TXPID_5G_0, - SIBA_SPROMVAR_TXPID_5G_1, - SIBA_SPROMVAR_TXPID_5G_2, - SIBA_SPROMVAR_TXPID_5G_3, - SIBA_SPROMVAR_TXPID_5GH_0, - SIBA_SPROMVAR_TXPID_5GH_1, - SIBA_SPROMVAR_TXPID_5GH_2, - SIBA_SPROMVAR_TXPID_5GH_3, - SIBA_SPROMVAR_STBCPO, - SIBA_SPROMVAR_CDDPO, -}; - -int siba_read_sprom(device_t, device_t, int, uintptr_t *); -int siba_write_sprom(device_t, device_t, int, uintptr_t); - -/** - * Generic sprom accessor generation macros for siba(4) drivers - */ -#define __SPROM_ACCESSOR(varp, var, ivarp, ivar, type) \ - \ -static __inline type varp ## _get_ ## var(device_t dev) \ -{ \ - uintptr_t v; \ - siba_read_sprom(device_get_parent(dev), dev, \ - ivarp ## _SPROMVAR_ ## ivar, &v); \ - return ((type) v); \ -} \ - \ -static __inline void varp ## _set_ ## var(device_t dev, type t) \ -{ \ - uintptr_t v = (uintptr_t) t; \ - siba_write_sprom(device_get_parent(dev), dev, \ - ivarp ## _SPROMVAR_ ## ivar, v); \ -} - -#define SIBA_SPROM_ACCESSOR(var, ivar, type) \ - __SPROM_ACCESSOR(siba_sprom, var, SIBA, ivar, type) - -SIBA_SPROM_ACCESSOR(rev, REV, uint8_t); -SIBA_SPROM_ACCESSOR(mac_80211bg, MAC_80211BG, uint8_t *); -SIBA_SPROM_ACCESSOR(mac_eth, MAC_ETH, uint8_t *); -SIBA_SPROM_ACCESSOR(mac_80211a, MAC_80211A, uint8_t *); -SIBA_SPROM_ACCESSOR(mii_eth0, MII_ETH0, uint8_t); -SIBA_SPROM_ACCESSOR(mii_eth1, MII_ETH1, uint8_t); -SIBA_SPROM_ACCESSOR(mdio_eth0, MDIO_ETH0, uint8_t); -SIBA_SPROM_ACCESSOR(mdio_eth1, MDIO_ETH1, uint8_t); -SIBA_SPROM_ACCESSOR(brev, BREV, uint8_t); -SIBA_SPROM_ACCESSOR(ccode, CCODE, uint8_t); -SIBA_SPROM_ACCESSOR(ant_a, ANT_A, uint8_t); -SIBA_SPROM_ACCESSOR(ant_bg, ANT_BG, uint8_t); -SIBA_SPROM_ACCESSOR(pa0b0, PA0B0, uint16_t); -SIBA_SPROM_ACCESSOR(pa0b1, PA0B1, uint16_t); -SIBA_SPROM_ACCESSOR(pa0b2, PA0B2, uint16_t); -SIBA_SPROM_ACCESSOR(pa1b0, PA1B0, uint16_t); -SIBA_SPROM_ACCESSOR(pa1b1, PA1B1, uint16_t); -SIBA_SPROM_ACCESSOR(pa1b2, PA1B2, uint16_t); -SIBA_SPROM_ACCESSOR(pa1lob0, PA1LOB0, uint16_t); -SIBA_SPROM_ACCESSOR(pa1lob1, PA1LOB1, uint16_t); -SIBA_SPROM_ACCESSOR(pa1lob2, PA1LOB2, uint16_t); -SIBA_SPROM_ACCESSOR(pa1hib0, PA1HIB0, uint16_t); -SIBA_SPROM_ACCESSOR(pa1hib1, PA1HIB1, uint16_t); -SIBA_SPROM_ACCESSOR(pa1hib2, PA1HIB2, uint16_t); -SIBA_SPROM_ACCESSOR(gpio0, GPIO0, uint8_t); -SIBA_SPROM_ACCESSOR(gpio1, GPIO1, uint8_t); -SIBA_SPROM_ACCESSOR(gpio2, GPIO2, uint8_t); -SIBA_SPROM_ACCESSOR(gpio3, GPIO3, uint8_t); -SIBA_SPROM_ACCESSOR(maxpwr_al, MAXPWR_AL, uint16_t); -SIBA_SPROM_ACCESSOR(maxpwr_a, MAXPWR_A, uint16_t); -SIBA_SPROM_ACCESSOR(maxpwr_ah, MAXPWR_AH, uint16_t); -SIBA_SPROM_ACCESSOR(maxpwr_bg, MAXPWR_BG, uint16_t); -SIBA_SPROM_ACCESSOR(rxpo2g, RXPO2G, uint8_t); -SIBA_SPROM_ACCESSOR(rxpo5g, RXPO5G, uint8_t); -SIBA_SPROM_ACCESSOR(tssi_a, TSSI_A, uint8_t); -SIBA_SPROM_ACCESSOR(tssi_bg, TSSI_BG, uint8_t); -SIBA_SPROM_ACCESSOR(tri2g, TRI2G, uint8_t); -SIBA_SPROM_ACCESSOR(tri5gl, TRI5GL, uint8_t); -SIBA_SPROM_ACCESSOR(tri5g, TRI5G, uint8_t); -SIBA_SPROM_ACCESSOR(tri5gh, TRI5GH, uint8_t); -SIBA_SPROM_ACCESSOR(rssisav2g, RSSISAV2G, uint8_t); -SIBA_SPROM_ACCESSOR(rssismc2g, RSSISMC2G, uint8_t); -SIBA_SPROM_ACCESSOR(rssismf2g, RSSISMF2G, uint8_t); -SIBA_SPROM_ACCESSOR(bxa2g, BXA2G, uint8_t); -SIBA_SPROM_ACCESSOR(rssisav5g, RSSISAV5G, uint8_t); -SIBA_SPROM_ACCESSOR(rssismc5g, RSSISMC5G, uint8_t); -SIBA_SPROM_ACCESSOR(rssismf5g, RSSISMF5G, uint8_t); -SIBA_SPROM_ACCESSOR(bxa5g, BXA5G, uint8_t); -SIBA_SPROM_ACCESSOR(cck2gpo, CCK2GPO, uint16_t); -SIBA_SPROM_ACCESSOR(ofdm2gpo, OFDM2GPO, uint32_t); -SIBA_SPROM_ACCESSOR(ofdm5glpo, OFDM5GLPO, uint32_t); -SIBA_SPROM_ACCESSOR(ofdm5gpo, OFDM5GPO, uint32_t); -SIBA_SPROM_ACCESSOR(ofdm5ghpo, OFDM5GHPO, uint32_t); -SIBA_SPROM_ACCESSOR(bf_lo, BF_LO, uint16_t); -SIBA_SPROM_ACCESSOR(bf_hi, BF_HI, uint16_t); -SIBA_SPROM_ACCESSOR(bf2_lo, BF2_LO, uint16_t); -SIBA_SPROM_ACCESSOR(bf2_hi, BF2_HI, uint16_t); -/* 2GHz FEM */ -SIBA_SPROM_ACCESSOR(fem_2ghz_tssipos, FEM_2GHZ_TSSIPOS, uint8_t); -SIBA_SPROM_ACCESSOR(fem_2ghz_extpa_gain, FEM_2GHZ_EXTPAGAIN, uint8_t); -SIBA_SPROM_ACCESSOR(fem_2ghz_pdet_range, FEM_2GHZ_PDET_RANGE, uint8_t); -SIBA_SPROM_ACCESSOR(fem_2ghz_tr_iso, FEM_2GHZ_TR_ISO, uint8_t); -SIBA_SPROM_ACCESSOR(fem_2ghz_antswlut, FEM_2GHZ_ANTSWLUT, uint8_t); -/* 5GHz FEM */ -SIBA_SPROM_ACCESSOR(fem_5ghz_tssipos, FEM_5GHZ_TSSIPOS, uint8_t); -SIBA_SPROM_ACCESSOR(fem_5ghz_extpa_gain, FEM_5GHZ_EXTPAGAIN, uint8_t); -SIBA_SPROM_ACCESSOR(fem_5ghz_pdet_range, FEM_5GHZ_PDET_RANGE, uint8_t); -SIBA_SPROM_ACCESSOR(fem_5ghz_tr_iso, FEM_5GHZ_TR_ISO, uint8_t); -SIBA_SPROM_ACCESSOR(fem_5ghz_antswlut, FEM_5GHZ_ANTSWLUT, uint8_t); -/* TX power index */ -SIBA_SPROM_ACCESSOR(txpid_2g_0, TXPID_2G_0, uint8_t); -SIBA_SPROM_ACCESSOR(txpid_2g_1, TXPID_2G_1, uint8_t); -SIBA_SPROM_ACCESSOR(txpid_2g_2, TXPID_2G_2, uint8_t); -SIBA_SPROM_ACCESSOR(txpid_2g_3, TXPID_2G_3, uint8_t); -SIBA_SPROM_ACCESSOR(txpid_5gl_0, TXPID_5GL_0, uint8_t); -SIBA_SPROM_ACCESSOR(txpid_5gl_1, TXPID_5GL_1, uint8_t); -SIBA_SPROM_ACCESSOR(txpid_5gl_2, TXPID_5GL_2, uint8_t); -SIBA_SPROM_ACCESSOR(txpid_5gl_3, TXPID_5GL_3, uint8_t); -SIBA_SPROM_ACCESSOR(txpid_5g_0, TXPID_5G_0, uint8_t); -SIBA_SPROM_ACCESSOR(txpid_5g_1, TXPID_5G_1, uint8_t); -SIBA_SPROM_ACCESSOR(txpid_5g_2, TXPID_5G_2, uint8_t); -SIBA_SPROM_ACCESSOR(txpid_5g_3, TXPID_5G_3, uint8_t); -SIBA_SPROM_ACCESSOR(txpid_5gh_0, TXPID_5GH_0, uint8_t); -SIBA_SPROM_ACCESSOR(txpid_5gh_1, TXPID_5GH_1, uint8_t); -SIBA_SPROM_ACCESSOR(txpid_5gh_2, TXPID_5GH_2, uint8_t); -SIBA_SPROM_ACCESSOR(txpid_5gh_3, TXPID_5GH_3, uint8_t); -SIBA_SPROM_ACCESSOR(stbcpo, STBCPO, uint16_t); -SIBA_SPROM_ACCESSOR(cddpo, CDDPO, uint16_t); - -#undef SIBA_SPROM_ACCESSOR - -struct siba_sprom_core_pwr_info { - uint8_t itssi_2g, itssi_5g; - uint8_t maxpwr_2g, maxpwr_5gl, maxpwr_5g, maxpwr_5gh; - uint8_t pa_2g[4], pa_5gl[4], pa_5g[4], pa_5gh[4]; -}; - -struct siba_sprom { - uint8_t rev; /* revision */ - uint8_t mac_80211bg[6]; /* address for 802.11b/g */ - uint8_t mac_eth[6]; /* address for Ethernet */ - uint8_t mac_80211a[6]; /* address for 802.11a */ - uint8_t mii_eth0; /* MII address for eth0 */ - uint8_t mii_eth1; /* MII address for eth1 */ - uint8_t mdio_eth0; /* MDIO for eth0 */ - uint8_t mdio_eth1; /* MDIO for eth1 */ - uint8_t brev; /* board revision */ - uint8_t ccode; /* Country Code */ - uint8_t ant_a; /* A-PHY antenna */ - uint8_t ant_bg; /* B/G-PHY antenna */ - uint16_t pa0b0; - uint16_t pa0b1; - uint16_t pa0b2; - uint16_t pa1b0; - uint16_t pa1b1; - uint16_t pa1b2; - uint16_t pa1lob0; - uint16_t pa1lob1; - uint16_t pa1lob2; - uint16_t pa1hib0; - uint16_t pa1hib1; - uint16_t pa1hib2; - uint8_t gpio0; - uint8_t gpio1; - uint8_t gpio2; - uint8_t gpio3; - uint16_t maxpwr_al; - uint16_t maxpwr_a; /* A-PHY Max Power */ - uint16_t maxpwr_ah; - uint16_t maxpwr_bg; /* BG-PHY Max Power */ - uint8_t rxpo2g; - uint8_t rxpo5g; - uint8_t tssi_a; /* Idle TSSI */ - uint8_t tssi_bg; /* Idle TSSI */ - uint8_t tri2g; - uint8_t tri5gl; - uint8_t tri5g; - uint8_t tri5gh; - uint8_t txpid2g[4]; /* 2GHz TX power index */ - uint8_t txpid5gl[4]; /* 4.9 - 5.1GHz TX power index */ - uint8_t txpid5g[4]; /* 5.1 - 5.5GHz TX power index */ - uint8_t txpid5gh[4]; /* 5.5 - 5.9GHz TX power index */ - uint8_t rssisav2g; - uint8_t rssismc2g; - uint8_t rssismf2g; - uint8_t bxa2g; - uint8_t rssisav5g; - uint8_t rssismc5g; - uint8_t rssismf5g; - uint8_t bxa5g; - uint16_t cck2gpo; - uint32_t ofdm2gpo; - uint32_t ofdm5glpo; - uint32_t ofdm5gpo; - uint32_t ofdm5ghpo; - uint16_t bf_lo; /* boardflags */ - uint16_t bf_hi; /* boardflags */ - uint16_t bf2_lo; - uint16_t bf2_hi; - - struct siba_sprom_core_pwr_info core_pwr_info[4]; - - struct { - struct { - int8_t a0, a1, a2, a3; - } ghz24; - struct { - int8_t a0, a1, a2, a3; - } ghz5; - } again; /* antenna gain */ - - struct { - struct { - uint8_t tssipos, extpa_gain, pdet_range, tr_iso; - uint8_t antswlut; - } ghz2; - struct { - uint8_t tssipos, extpa_gain, pdet_range, tr_iso; - uint8_t antswlut; - } ghz5; - } fem; - - uint16_t mcs2gpo[8]; - uint16_t mcs5gpo[8]; - uint16_t mcs5glpo[8]; - uint16_t mcs5ghpo[8]; - - uint16_t cddpo; - uint16_t stbcpo; -}; - -#define SIBA_LDO_PAREF 0 -#define SIBA_LDO_VOLT1 1 -#define SIBA_LDO_VOLT2 2 -#define SIBA_LDO_VOLT3 3 - -struct siba_cc_pmu { - uint8_t rev; /* PMU rev */ - uint32_t freq; /* crystal freq in kHz */ -}; - -struct siba_cc { - struct siba_dev_softc *scc_dev; - uint32_t scc_caps; - struct siba_cc_pmu scc_pmu; - uint16_t scc_powerup_delay; -}; - -struct siba_pci { - struct siba_dev_softc *spc_dev; - uint8_t spc_inited; - uint8_t spc_hostmode; -}; - -struct siba_bus_ops { - uint16_t (*read_2)(struct siba_dev_softc *, - uint16_t); - uint32_t (*read_4)(struct siba_dev_softc *, - uint16_t); - void (*write_2)(struct siba_dev_softc *, - uint16_t, uint16_t); - void (*write_4)(struct siba_dev_softc *, - uint16_t, uint32_t); - void (*read_multi_1)(struct siba_dev_softc *, - void *, size_t, uint16_t); - void (*read_multi_2)(struct siba_dev_softc *, - void *, size_t, uint16_t); - void (*read_multi_4)(struct siba_dev_softc *, - void *, size_t, uint16_t); - void (*write_multi_1)(struct siba_dev_softc *, - const void *, size_t, uint16_t); - void (*write_multi_2)(struct siba_dev_softc *, - const void *, size_t, uint16_t); - void (*write_multi_4)(struct siba_dev_softc *, - const void *, size_t, uint16_t); -}; - -struct siba_dev_softc { - struct siba_softc *sd_bus; - struct siba_devid sd_id; - const struct siba_bus_ops *sd_ops; - - uint8_t sd_coreidx; -}; - -struct siba_devinfo { - struct resource_list sdi_rl; - /*devhandle_t sdi_devhandle; XXX*/ - /*struct rman sdi_intr_rman;*/ - - /* Accessors are needed for ivars below. */ - uint16_t sdi_vid; - uint16_t sdi_devid; - uint8_t sdi_rev; - uint8_t sdi_idx; /* core index on bus */ - uint8_t sdi_irq; /* TODO */ -}; - -struct siba_softc { - /* - * common variables which used for siba(4) bus and siba_bwn bridge. - */ - device_t siba_dev; /* Device ID */ - struct resource *siba_mem_res; - bus_space_tag_t siba_mem_bt; - bus_space_handle_t siba_mem_bh; - bus_addr_t siba_maddr; - bus_size_t siba_msize; - uint8_t siba_ncores; - uint32_t siba_debug; - - /* - * the following variables are only used for siba_bwn bridge. - */ - - enum siba_type siba_type; - int siba_invalid; - - struct siba_dev_softc *siba_curdev; /* only for PCI */ - struct siba_dev_softc siba_devs[SIBA_MAX_CORES]; - int siba_ndevs; - - uint16_t siba_pci_vid; - uint16_t siba_pci_did; - uint16_t siba_pci_subvid; - uint16_t siba_pci_subdid; - uint8_t siba_pci_revid; - int siba_mem_rid; - - uint16_t siba_chipid; /* for CORE 0 */ - uint16_t siba_chiprev; - uint8_t siba_chippkg; - - struct siba_cc siba_cc; /* ChipCommon */ - struct siba_pci siba_pci; /* PCI-core */ - const struct siba_bus_ops *siba_ops; - - struct siba_sprom siba_sprom; /* SPROM */ - uint16_t siba_spromsize; /* in word size */ -}; - -void siba_powerup(device_t, int); -int siba_powerdown(device_t); -uint16_t siba_read_2(device_t, uint16_t); -void siba_write_2(device_t, uint16_t, uint16_t); -uint32_t siba_read_4(device_t, uint16_t); -void siba_write_4(device_t, uint16_t, uint32_t); -void siba_dev_up(device_t, uint32_t); -void siba_dev_down(device_t, uint32_t); -int siba_dev_isup(device_t); -void siba_pcicore_intr(device_t); -uint32_t siba_dma_translation(device_t); -void siba_read_multi_1(device_t, void *, size_t, uint16_t); -void siba_read_multi_2(device_t, void *, size_t, uint16_t); -void siba_read_multi_4(device_t, void *, size_t, uint16_t); -void siba_write_multi_1(device_t, const void *, size_t, uint16_t); -void siba_write_multi_2(device_t, const void *, size_t, uint16_t); -void siba_write_multi_4(device_t, const void *, size_t, uint16_t); -void siba_barrier(device_t, int); -void siba_cc_pmu_set_ldovolt(device_t, int, uint32_t); -void siba_cc_pmu_set_ldoparef(device_t, uint8_t); -void siba_gpio_set(device_t, uint32_t); -uint32_t siba_gpio_get(device_t); -void siba_fix_imcfglobug(device_t); -int siba_sprom_get_core_power_info(device_t, int, - struct siba_sprom_core_pwr_info *); -int siba_sprom_get_mcs2gpo(device_t, uint16_t *); -int siba_sprom_get_mcs5glpo(device_t, uint16_t *); -int siba_sprom_get_mcs5gpo(device_t, uint16_t *); -int siba_sprom_get_mcs5ghpo(device_t, uint16_t *); -void siba_pmu_spuravoid_pllupdate(device_t, int); -void siba_cc_set32(device_t dev, uint32_t, uint32_t); -void siba_cc_mask32(device_t dev, uint32_t, uint32_t); -uint32_t siba_cc_read32(device_t dev, uint32_t); -void siba_cc_write32(device_t dev, uint32_t, uint32_t); - -#endif /* _SIBA_SIBAVAR_H_ */ Property changes on: head/sys/dev/siba/sibavar.h ___________________________________________________________________ Deleted: svn:eol-style ## -1 +0,0 ## -native \ No newline at end of property Deleted: svn:keywords ## -1 +0,0 ## -FreeBSD=%H \ No newline at end of property Deleted: svn:mime-type ## -1 +0,0 ## -text/plain \ No newline at end of property Index: head/sys/dev/siba/siba_bwn.c =================================================================== --- head/sys/dev/siba/siba_bwn.c (revision 328911) +++ head/sys/dev/siba/siba_bwn.c (nonexistent) @@ -1,411 +0,0 @@ -/*- - * SPDX-License-Identifier: BSD-2-Clause-FreeBSD - * - * Copyright (c) 2009-2010 Weongyo Jeong - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer, - * without modification. - * 2. Redistributions in binary form must reproduce at minimum a disclaimer - * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any - * redistribution must be conditioned upon including a substantially - * similar Disclaimer requirement for further binary redistribution. - * - * NO WARRANTY - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY - * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL - * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, - * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER - * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF - * THE POSSIBILITY OF SUCH DAMAGES. - */ - -#include -__FBSDID("$FreeBSD$"); - -/* - * Sonics Silicon Backplane front-end for bwn(4). - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include - -#include -#include - -#include -#include -#include - -/* - * PCI glue. - */ - -struct siba_bwn_softc { - /* Child driver using MSI. */ - device_t ssc_msi_child; - struct siba_softc ssc_siba; -}; - -#define BS_BAR 0x10 -#define PCI_VENDOR_BROADCOM 0x14e4 -#define N(a) (sizeof(a) / sizeof(a[0])) - -static const struct siba_dev { - uint16_t vid; - uint16_t did; - const char *desc; -} siba_devices[] = { - { PCI_VENDOR_BROADCOM, 0x4301, "Broadcom BCM4301 802.11b Wireless" }, - { PCI_VENDOR_BROADCOM, 0x4306, "Unknown" }, - { PCI_VENDOR_BROADCOM, 0x4307, "Broadcom BCM4307 802.11b Wireless" }, - { PCI_VENDOR_BROADCOM, 0x4311, "Broadcom BCM4311 802.11b/g Wireless" }, - { PCI_VENDOR_BROADCOM, 0x4312, - "Broadcom BCM4312 802.11a/b/g Wireless" }, - { PCI_VENDOR_BROADCOM, 0x4315, "Broadcom BCM4312 802.11b/g Wireless" }, - { PCI_VENDOR_BROADCOM, 0x4318, "Broadcom BCM4318 802.11b/g Wireless" }, - { PCI_VENDOR_BROADCOM, 0x4319, - "Broadcom BCM4318 802.11a/b/g Wireless" }, - { PCI_VENDOR_BROADCOM, 0x4320, "Broadcom BCM4306 802.11b/g Wireless" }, - { PCI_VENDOR_BROADCOM, 0x4321, "Broadcom BCM4306 802.11a Wireless" }, - { PCI_VENDOR_BROADCOM, 0x4324, - "Broadcom BCM4309 802.11a/b/g Wireless" }, - { PCI_VENDOR_BROADCOM, 0x4325, "Broadcom BCM4306 802.11b/g Wireless" }, - { PCI_VENDOR_BROADCOM, 0x4328, "Broadcom BCM4321 802.11a/b/g/n Wireless" }, - { PCI_VENDOR_BROADCOM, 0x4329, "Unknown" }, - { PCI_VENDOR_BROADCOM, 0x432b, "Broadcom BCM4322 802.11a/b/g/n Wireless" } -}; - -int siba_core_attach(struct siba_softc *); -int siba_core_detach(struct siba_softc *); -int siba_core_suspend(struct siba_softc *); -int siba_core_resume(struct siba_softc *); - -static int -siba_bwn_probe(device_t dev) -{ - int i; - uint16_t did, vid; - - did = pci_get_device(dev); - vid = pci_get_vendor(dev); - - for (i = 0; i < N(siba_devices); i++) { - if (siba_devices[i].did == did && siba_devices[i].vid == vid) { - device_set_desc(dev, siba_devices[i].desc); - return (BUS_PROBE_DEFAULT); - } - } - return (ENXIO); -} - -static int -siba_bwn_attach(device_t dev) -{ - struct siba_bwn_softc *ssc = device_get_softc(dev); - struct siba_softc *siba = &ssc->ssc_siba; - - siba->siba_dev = dev; - siba->siba_type = SIBA_TYPE_PCI; - - /* - * Enable bus mastering. - */ - pci_enable_busmaster(dev); - - /* - * Setup memory-mapping of PCI registers. - */ - siba->siba_mem_rid = SIBA_PCIR_BAR; - siba->siba_mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, - &siba->siba_mem_rid, RF_ACTIVE); - if (siba->siba_mem_res == NULL) { - device_printf(dev, "cannot map register space\n"); - return (ENXIO); - } - siba->siba_mem_bt = rman_get_bustag(siba->siba_mem_res); - siba->siba_mem_bh = rman_get_bushandle(siba->siba_mem_res); - - /* Get more PCI information */ - siba->siba_pci_did = pci_get_device(dev); - siba->siba_pci_vid = pci_get_vendor(dev); - siba->siba_pci_subvid = pci_get_subvendor(dev); - siba->siba_pci_subdid = pci_get_subdevice(dev); - siba->siba_pci_revid = pci_get_revid(dev); - - return (siba_core_attach(siba)); -} - -static int -siba_bwn_detach(device_t dev) -{ - struct siba_bwn_softc *ssc = device_get_softc(dev); - struct siba_softc *siba = &ssc->ssc_siba; - - /* check if device was removed */ - siba->siba_invalid = !bus_child_present(dev); - - pci_disable_busmaster(dev); - bus_generic_detach(dev); - siba_core_detach(siba); - - bus_release_resource(dev, SYS_RES_MEMORY, BS_BAR, siba->siba_mem_res); - - return (0); -} - -static int -siba_bwn_suspend(device_t dev) -{ - struct siba_bwn_softc *ssc = device_get_softc(dev); - struct siba_softc *siba = &ssc->ssc_siba; - int error; - - error = bus_generic_suspend(dev); - - if (error != 0) - return (error); - - return (siba_core_suspend(siba)); -} - -static int -siba_bwn_resume(device_t dev) -{ - struct siba_bwn_softc *ssc = device_get_softc(dev); - struct siba_softc *siba = &ssc->ssc_siba; - int error; - - error = siba_core_resume(siba); - if (error != 0) - return (error); - - bus_generic_resume(dev); - - return (0); -} - -/* proxying to the parent */ -static struct resource * -siba_bwn_alloc_resource(device_t dev, device_t child, int type, int *rid, - rman_res_t start, rman_res_t end, rman_res_t count, u_int flags) -{ - - return (BUS_ALLOC_RESOURCE(device_get_parent(dev), dev, - type, rid, start, end, count, flags)); -} - -/* proxying to the parent */ -static int -siba_bwn_release_resource(device_t dev, device_t child, int type, - int rid, struct resource *r) -{ - - return (BUS_RELEASE_RESOURCE(device_get_parent(dev), dev, type, - rid, r)); -} - -/* proxying to the parent */ -static int -siba_bwn_setup_intr(device_t dev, device_t child, struct resource *irq, - int flags, driver_filter_t *filter, driver_intr_t *intr, void *arg, - void **cookiep) -{ - - return (BUS_SETUP_INTR(device_get_parent(dev), dev, irq, flags, - filter, intr, arg, cookiep)); -} - -/* proxying to the parent */ -static int -siba_bwn_teardown_intr(device_t dev, device_t child, struct resource *irq, - void *cookie) -{ - - return (BUS_TEARDOWN_INTR(device_get_parent(dev), dev, irq, cookie)); -} - -static int -siba_bwn_find_cap(device_t dev, device_t child, int capability, - int *capreg) -{ - - return (pci_find_cap(dev, capability, capreg)); -} - -static int -siba_bwn_find_extcap(device_t dev, device_t child, int capability, - int *capreg) -{ - - return (pci_find_extcap(dev, capability, capreg)); -} - -static int -siba_bwn_find_htcap(device_t dev, device_t child, int capability, - int *capreg) -{ - - return (pci_find_htcap(dev, capability, capreg)); -} - -static int -siba_bwn_alloc_msi(device_t dev, device_t child, int *count) -{ - struct siba_bwn_softc *ssc; - int error; - - ssc = device_get_softc(dev); - if (ssc->ssc_msi_child != NULL) - return (EBUSY); - error = pci_alloc_msi(dev, count); - if (error == 0) - ssc->ssc_msi_child = child; - return (error); -} - -static int -siba_bwn_release_msi(device_t dev, device_t child) -{ - struct siba_bwn_softc *ssc; - int error; - - ssc = device_get_softc(dev); - if (ssc->ssc_msi_child != child) - return (ENXIO); - error = pci_release_msi(dev); - if (error == 0) - ssc->ssc_msi_child = NULL; - return (error); -} - -static int -siba_bwn_msi_count(device_t dev, device_t child) -{ - - return (pci_msi_count(dev)); -} - -static int -siba_bwn_read_ivar(device_t dev, device_t child, int which, uintptr_t *result) -{ - struct siba_dev_softc *sd; - struct siba_softc *siba; - - sd = device_get_ivars(child); - siba = sd->sd_bus; - - switch (which) { - case SIBA_IVAR_VENDOR: - *result = sd->sd_id.sd_vendor; - break; - case SIBA_IVAR_DEVICE: - *result = sd->sd_id.sd_device; - break; - case SIBA_IVAR_REVID: - *result = sd->sd_id.sd_rev; - break; - case SIBA_IVAR_PCI_VENDOR: - *result = siba->siba_pci_vid; - break; - case SIBA_IVAR_PCI_DEVICE: - *result = siba->siba_pci_did; - break; - case SIBA_IVAR_PCI_SUBVENDOR: - *result = siba->siba_pci_subvid; - break; - case SIBA_IVAR_PCI_SUBDEVICE: - *result = siba->siba_pci_subdid; - break; - case SIBA_IVAR_PCI_REVID: - *result = siba->siba_pci_revid; - break; - case SIBA_IVAR_CHIPID: - *result = siba->siba_chipid; - break; - case SIBA_IVAR_CHIPREV: - *result = siba->siba_chiprev; - break; - case SIBA_IVAR_CHIPPKG: - *result = siba->siba_chippkg; - break; - case SIBA_IVAR_TYPE: - *result = siba->siba_type; - break; - case SIBA_IVAR_CC_PMUFREQ: - *result = siba->siba_cc.scc_pmu.freq; - break; - case SIBA_IVAR_CC_CAPS: - *result = siba->siba_cc.scc_caps; - break; - case SIBA_IVAR_CC_POWERDELAY: - *result = siba->siba_cc.scc_powerup_delay; - break; - case SIBA_IVAR_PCICORE_REVID: - *result = siba->siba_pci.spc_dev->sd_id.sd_rev; - break; - default: - return (ENOENT); - } - - return (0); -} - -static device_method_t siba_bwn_methods[] = { - /* Device interface */ - DEVMETHOD(device_probe, siba_bwn_probe), - DEVMETHOD(device_attach, siba_bwn_attach), - DEVMETHOD(device_detach, siba_bwn_detach), - DEVMETHOD(device_shutdown, bus_generic_shutdown), - DEVMETHOD(device_suspend, siba_bwn_suspend), - DEVMETHOD(device_resume, siba_bwn_resume), - - /* Bus interface */ - DEVMETHOD(bus_alloc_resource, siba_bwn_alloc_resource), - DEVMETHOD(bus_release_resource, siba_bwn_release_resource), - DEVMETHOD(bus_read_ivar, siba_bwn_read_ivar), - DEVMETHOD(bus_setup_intr, siba_bwn_setup_intr), - DEVMETHOD(bus_teardown_intr, siba_bwn_teardown_intr), - - /* PCI interface */ - DEVMETHOD(pci_find_cap, siba_bwn_find_cap), - DEVMETHOD(pci_find_extcap, siba_bwn_find_extcap), - DEVMETHOD(pci_find_htcap, siba_bwn_find_htcap), - DEVMETHOD(pci_alloc_msi, siba_bwn_alloc_msi), - DEVMETHOD(pci_release_msi, siba_bwn_release_msi), - DEVMETHOD(pci_msi_count, siba_bwn_msi_count), - - DEVMETHOD_END -}; -static driver_t siba_bwn_driver = { - "siba_bwn", - siba_bwn_methods, - sizeof(struct siba_bwn_softc) -}; -static devclass_t siba_bwn_devclass; -DRIVER_MODULE(siba_bwn, pci, siba_bwn_driver, siba_bwn_devclass, 0, 0); -MODULE_VERSION(siba_bwn, 1); Property changes on: head/sys/dev/siba/siba_bwn.c ___________________________________________________________________ Deleted: svn:eol-style ## -1 +0,0 ## -native \ No newline at end of property Deleted: svn:keywords ## -1 +0,0 ## -FreeBSD=%H \ No newline at end of property Deleted: svn:mime-type ## -1 +0,0 ## -text/plain \ No newline at end of property Index: head/sys/dev/bhnd/bhnd_ids.h =================================================================== --- head/sys/dev/bhnd/bhnd_ids.h (revision 328911) +++ head/sys/dev/bhnd/bhnd_ids.h (revision 328912) @@ -1,1133 +1,1136 @@ /*- * SPDX-License-Identifier: ISC * * Copyright (c) 2015-2016 Landon Fuller * Copyright (c) 1999-2015, Broadcom Corporation * * This file is derived from the bcmdevs.h header contributed by Broadcom * to Android's bcmdhd driver module, later revisions of bcmdevs.h distributed * with the dd-wrt project, and the hndsoc.h header distributed with Broadcom's * initial brcm80211 Linux driver release as contributed to the Linux staging * repository. * * Permission to use, copy, modify, and/or distribute this software for any * purpose with or without fee is hereby granted, provided that the above * copyright notice and this permission notice appear in all copies. * * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. * * $FreeBSD$ */ #ifndef _BHND_BHND_IDS_H_ #define _BHND_BHND_IDS_H_ /* * JEDEC JEP-106 Core Vendor IDs * * These are the JEDEC JEP-106 manufacturer ID representions (with ARM's * non-standard 4-bit continutation code), as used in ARM's PrimeCell * identification registers, bcma(4) EROM core descriptors, etc. * * @note * Bus implementations that predate the adoption of ARM IP * will need to convert bus-specific vendor IDs to their BHND_MFGID * JEP-106 equivalents. * * @par ARM 4-bit Continuation Code * * BHND MFGIDs are encoded using ARM's non-standard 4-bit continuation code * format: * * @code{.unparsed} * [11:8 ][7:0 ] * [cont code][mfg id] * @endcode * * The 4-bit continuation code field specifies the number of JEP-106 * continuation codes that prefix the manufacturer's ID code. In the case of * ARM's JEP-106 ID of `0x7F 0x7F 0x7F 0x7F 0x3B`, the four 0x7F continuations * are encoded as '4' in the 4-bit continuation code field (i.e. 0x43B). */ #define BHND_MFGID_ARM 0x043b /**< arm JEP-106 vendor id */ #define BHND_MFGID_BCM 0x04bf /**< broadcom JEP-106 vendor id */ #define BHND_MFGID_MIPS 0x04a7 /**< mips JEP-106 vendor id */ #define BHND_MFGID_INVALID 0x0000 /**< invalid JEP-106 vendor id */ /* * OCP (Open Core Protocol) Vendor IDs. * * OCP-IP assigned vendor codes are used by siba(4) */ #define OCP_VENDOR_BCM 0x4243 /**< Broadcom OCP vendor id */ /* PCI vendor IDs */ +#define PCI_VENDOR_ASUSTEK 0x1043 #define PCI_VENDOR_EPIGRAM 0xfeda #define PCI_VENDOR_BROADCOM 0x14e4 #define PCI_VENDOR_3COM 0x10b7 #define PCI_VENDOR_NETGEAR 0x1385 #define PCI_VENDOR_DIAMOND 0x1092 #define PCI_VENDOR_INTEL 0x8086 #define PCI_VENDOR_DELL 0x1028 #define PCI_VENDOR_HP 0x103c #define PCI_VENDOR_HP_COMPAQ 0x0e11 +#define PCI_VENDOR_LINKSYS 0x1737 +#define PCI_VENDOR_MOTOROLA 0x1057 #define PCI_VENDOR_APPLE 0x106b #define PCI_VENDOR_SI_IMAGE 0x1095 /* Silicon Image, used by Arasan SDIO Host */ #define PCI_VENDOR_BUFFALO 0x1154 /* Buffalo vendor id */ #define PCI_VENDOR_TI 0x104c /* Texas Instruments */ #define PCI_VENDOR_RICOH 0x1180 /* Ricoh */ #define PCI_VENDOR_JMICRON 0x197b /* PCMCIA vendor IDs */ #define PCMCIA_VENDOR_BROADCOM 0x02d0 /* SDIO vendor IDs */ #define SDIO_VENDOR_BROADCOM 0x00BF /* USB dongle VID/PIDs */ #define USB_VID_BROADCOM 0x0a5c #define USB_PID_BCM4328 0xbd12 #define USB_PID_BCM4322 0xbd13 #define USB_PID_BCM4319 0xbd16 #define USB_PID_BCM43236 0xbd17 #define USB_PID_BCM4332 0xbd18 #define USB_PID_BCM4330 0xbd19 #define USB_PID_BCM4334 0xbd1a #define USB_PID_BCM43239 0xbd1b #define USB_PID_BCM4324 0xbd1c #define USB_PID_BCM4360 0xbd1d #define USB_PID_BCM43143 0xbd1e #define USB_PID_BCM43242 0xbd1f #define USB_PID_BCM43342 0xbd21 #define USB_PID_BCM4335 0xbd20 #define USB_PID_BCM4350 0xbd23 #define USB_PID_BCM43341 0xbd22 #define USB_PID_BCM_DNGL_BDC 0x0bdc /* BDC USB device controller IP? */ #define USB_PID_BCM_DNGL_JTAG 0x4a44 /* HW USB BLOCK [CPULESS USB] PIDs */ #define USB_PID_CCM_HWUSB_43239 43239 /* PCI Device IDs */ #define PCI_DEVID_BCM4210 0x1072 /* never used */ #define PCI_DEVID_BCM4230 0x1086 /* never used */ #define PCI_DEVID_BCM4401_ENET 0x170c /* 4401b0 production enet cards */ #define PCI_DEVID_BCM3352 0x3352 /* bcm3352 device id */ #define PCI_DEVID_BCM3360 0x3360 /* bcm3360 device id */ #define PCI_DEVID_BCM4211 0x4211 #define PCI_DEVID_BCM4231 0x4231 #define PCI_DEVID_BCM4301 0x4301 /* 4031 802.11b */ #define PCI_DEVID_BCM4303_D11B 0x4303 /* 4303 802.11b */ #define PCI_DEVID_BCM4306 0x4306 /* 4306 802.11b/g */ #define PCI_DEVID_BCM4307 0x4307 /* 4307 802.11b, 10/100 ethernet, V.92 modem */ #define PCI_DEVID_BCM4311_D11G 0x4311 /* 4311 802.11b/g id */ #define PCI_DEVID_BCM4311_D11DUAL 0x4312 /* 4311 802.11a/b/g id */ #define PCI_DEVID_BCM4311_D11A 0x4313 /* 4311 802.11a id */ #define PCI_DEVID_BCM4328_D11DUAL 0x4314 /* 4328/4312 802.11a/g id */ #define PCI_DEVID_BCM4328_D11G 0x4315 /* 4328/4312 802.11g id */ #define PCI_DEVID_BCM4328_D11A 0x4316 /* 4328/4312 802.11a id */ #define PCI_DEVID_BCM4318_D11G 0x4318 /* 4318 802.11b/g id */ #define PCI_DEVID_BCM4318_D11DUAL 0x4319 /* 4318 802.11a/b/g id */ #define PCI_DEVID_BCM4318_D11A 0x431a /* 4318 802.11a id */ #define PCI_DEVID_BCM4325_D11DUAL 0x431b /* 4325 802.11a/g id */ #define PCI_DEVID_BCM4325_D11G 0x431c /* 4325 802.11g id */ #define PCI_DEVID_BCM4325_D11A 0x431d /* 4325 802.11a id */ #define PCI_DEVID_BCM4306_D11G 0x4320 /* 4306 802.11g */ #define PCI_DEVID_BCM4306_D11A 0x4321 /* 4306 802.11a */ #define PCI_DEVID_BCM4306_UART 0x4322 /* 4306 uart */ #define PCI_DEVID_BCM4306_V90 0x4323 /* 4306 v90 codec */ #define PCI_DEVID_BCM4306_D11DUAL 0x4324 /* 4306 dual A+B */ #define PCI_DEVID_BCM4306_D11G_ID2 0x4325 /* BCM4306_D11G; INF w/loose binding war */ #define PCI_DEVID_BCM4321_D11N 0x4328 /* 4321 802.11n dualband id */ #define PCI_DEVID_BCM4321_D11N2G 0x4329 /* 4321 802.11n 2.4Ghz band id */ #define PCI_DEVID_BCM4321_D11N5G 0x432a /* 4321 802.11n 5Ghz band id */ #define PCI_DEVID_BCM4322_D11N 0x432b /* 4322 802.11n dualband device */ #define PCI_DEVID_BCM4322_D11N2G 0x432c /* 4322 802.11n 2.4GHz device */ #define PCI_DEVID_BCM4322_D11N5G 0x432d /* 4322 802.11n 5GHz device */ #define PCI_DEVID_BCM4329_D11N 0x432e /* 4329 802.11n dualband device */ #define PCI_DEVID_BCM4329_D11N2G 0x432f /* 4329 802.11n 2.4G device */ #define PCI_DEVID_BCM4329_D11N5G 0x4330 /* 4329 802.11n 5G device */ #define PCI_DEVID_BCM4315_D11DUAL 0x4334 /* 4315 802.11a/g id */ #define PCI_DEVID_BCM4315_D11G 0x4335 /* 4315 802.11g id */ #define PCI_DEVID_BCM4315_D11A 0x4336 /* 4315 802.11a id */ #define PCI_DEVID_BCM4319_D11N 0x4337 /* 4319 802.11n dualband device */ #define PCI_DEVID_BCM4319_D11N2G 0x4338 /* 4319 802.11n 2.4G device */ #define PCI_DEVID_BCM4319_D11N5G 0x4339 /* 4319 802.11n 5G device */ #define PCI_DEVID_BCM43231_D11N2G 0x4340 /* 43231 802.11n 2.4GHz device */ #define PCI_DEVID_BCM43221_D11N2G 0x4341 /* 43221 802.11n 2.4GHz device */ #define PCI_DEVID_BCM43222_D11N 0x4350 /* 43222 802.11n dualband device */ #define PCI_DEVID_BCM43222_D11N2G 0x4351 /* 43222 802.11n 2.4GHz device */ #define PCI_DEVID_BCM43222_D11N5G 0x4352 /* 43222 802.11n 5GHz device */ #define PCI_DEVID_BCM43224_D11N 0x4353 /* 43224 802.11n dualband device */ #define PCI_DEVID_BCM43224_D11N_ID_VEN1 0x0576 /* Vendor specific 43224 802.11n db device */ #define PCI_DEVID_BCM43226_D11N 0x4354 /* 43226 802.11n dualband device */ #define PCI_DEVID_BCM43236_D11N 0x4346 /* 43236 802.11n dualband device */ #define PCI_DEVID_BCM43236_D11N2G 0x4347 /* 43236 802.11n 2.4GHz device */ #define PCI_DEVID_BCM43236_D11N5G 0x4348 /* 43236 802.11n 5GHz device */ #define PCI_DEVID_BCM43225_D11N2G 0x4357 /* 43225 802.11n 2.4GHz device */ #define PCI_DEVID_BCM43421_D11N 0xA99D /* 43421 802.11n dualband device */ #define PCI_DEVID_BCM4313_D11N2G 0x4727 /* 4313 802.11n 2.4G device */ #define PCI_DEVID_BCM4330_D11N 0x4360 /* 4330 802.11n dualband device */ #define PCI_DEVID_BCM4330_D11N2G 0x4361 /* 4330 802.11n 2.4G device */ #define PCI_DEVID_BCM4330_D11N5G 0x4362 /* 4330 802.11n 5G device */ #define PCI_DEVID_BCM4336_D11N 0x4343 /* 4336 802.11n 2.4GHz device */ #define PCI_DEVID_BCM6362_D11N 0x435f /* 6362 802.11n dualband device */ #define PCI_DEVID_BCM6362_D11N2G 0x433f /* 6362 802.11n 2.4Ghz band id */ #define PCI_DEVID_BCM6362_D11N5G 0x434f /* 6362 802.11n 5Ghz band id */ #define PCI_DEVID_BCM4331_D11N 0x4331 /* 4331 802.11n dualband id */ #define PCI_DEVID_BCM4331_D11N2G 0x4332 /* 4331 802.11n 2.4Ghz band id */ #define PCI_DEVID_BCM4331_D11N5G 0x4333 /* 4331 802.11n 5Ghz band id */ #define PCI_DEVID_BCM43237_D11N 0x4355 /* 43237 802.11n dualband device */ #define PCI_DEVID_BCM43237_D11N5G 0x4356 /* 43237 802.11n 5GHz device */ #define PCI_DEVID_BCM43227_D11N2G 0x4358 /* 43228 802.11n 2.4GHz device */ #define PCI_DEVID_BCM43228_D11N 0x4359 /* 43228 802.11n DualBand device */ #define PCI_DEVID_BCM43228_D11N5G 0x435a /* 43228 802.11n 5GHz device */ #define PCI_DEVID_BCM43362_D11N 0x4363 /* 43362 802.11n 2.4GHz device */ #define PCI_DEVID_BCM43239_D11N 0x4370 /* 43239 802.11n dualband device */ #define PCI_DEVID_BCM4324_D11N 0x4374 /* 4324 802.11n dualband device */ #define PCI_DEVID_BCM43217_D11N2G 0x43a9 /* 43217 802.11n 2.4GHz device */ #define PCI_DEVID_BCM43131_D11N2G 0x43aa /* 43131 802.11n 2.4GHz device */ #define PCI_DEVID_BCM4314_D11N2G 0x4364 /* 4314 802.11n 2.4G device */ #define PCI_DEVID_BCM43142_D11N2G 0x4365 /* 43142 802.11n 2.4G device */ #define PCI_DEVID_BCM43143_D11N2G 0x4366 /* 43143 802.11n 2.4G device */ #define PCI_DEVID_BCM4334_D11N 0x4380 /* 4334 802.11n dualband device */ #define PCI_DEVID_BCM4334_D11N2G 0x4381 /* 4334 802.11n 2.4G device */ #define PCI_DEVID_BCM4334_D11N5G 0x4382 /* 4334 802.11n 5G device */ #define PCI_DEVID_BCM43342_D11N 0x4383 /* 43342 802.11n dualband device */ #define PCI_DEVID_BCM43342_D11N2G 0x4384 /* 43342 802.11n 2.4G device */ #define PCI_DEVID_BCM43342_D11N5G 0x4385 /* 43342 802.11n 5G device */ #define PCI_DEVID_BCM43341_D11N 0x4386 /* 43341 802.11n dualband device */ #define PCI_DEVID_BCM43341_D11N2G 0x4387 /* 43341 802.11n 2.4G device */ #define PCI_DEVID_BCM43341_D11N5G 0x4388 /* 43341 802.11n 5G device */ #define PCI_DEVID_BCM4360_D11AC 0x43a0 #define PCI_DEVID_BCM4360_D11AC2G 0x43a1 #define PCI_DEVID_BCM4360_D11AC5G 0x43a2 #define PCI_DEVID_BCM4335_D11AC 0x43ae #define PCI_DEVID_BCM4335_D11AC2G 0x43af #define PCI_DEVID_BCM4335_D11AC5G 0x43b0 #define PCI_DEVID_BCM4352_D11AC 0x43b1 /* 4352 802.11ac dualband device */ #define PCI_DEVID_BCM4352_D11AC2G 0x43b2 /* 4352 802.11ac 2.4G device */ #define PCI_DEVID_BCM4352_D11AC5G 0x43b3 /* 4352 802.11ac 5G device */ #define PCI_DEVID_PCIXX21_FLASHMEDIA0 0x8033 /* TI PCI xx21 Standard Host Controller */ #define PCI_DEVID_PCIXX21_SDIOH0 0x8034 /* TI PCI xx21 Standard Host Controller */ /* PCI Subsystem Vendor IDs */ #define PCI_SUBVENDOR_BCM943228HMB 0x0607 #define PCI_SUBVENDOR_BCM94313HMGBL 0x0608 #define PCI_SUBVENDOR_BCM94313HMG 0x0609 #define PCI_SUBVENDOR_BCM943142HM 0x0611 /* PCI Subsystem Device IDs */ #define PCI_SUBDEVID_BCM43143_D11N2G 0x4366 /* 43143 802.11n 2.4G device */ #define PCI_SUBDEVID_BCM43242_D11N 0x4367 /* 43242 802.11n dualband device */ #define PCI_SUBDEVID_BCM43242_D11N2G 0x4368 /* 43242 802.11n 2.4G device */ #define PCI_SUBDEVID_BCM43242_D11N5G 0x4369 /* 43242 802.11n 5G device */ #define PCI_SUBDEVID_BCM4350_D11AC 0x43a3 #define PCI_SUBDEVID_BCM4350_D11AC2G 0x43a4 #define PCI_SUBDEVID_BCM4350_D11AC5G 0x43a5 #define PCI_SUBDEVID_BCMGPRS_UART 0x4333 /* Uart id used by 4306/gprs card */ #define PCI_SUBDEVID_BCMGPRS2_UART 0x4344 /* Uart id used by 4306/gprs card */ #define PCI_SUBDEVID_BCM_FPGA_JTAGM 0x43f0 /* FPGA jtagm device id */ #define PCI_SUBDEVID_BCM_JTAGM 0x43f1 /* BCM jtagm device id */ #define PCI_SUBDEVID_BCM_SDIOH_FPGA 0x43f2 /* sdio host fpga */ #define PCI_SUBDEVID_BCM_SDIOH 0x43f3 /* BCM sdio host id */ #define PCI_SUBDEVID_BCM_SDIOD_FPGA 0x43f4 /* sdio device fpga */ #define PCI_SUBDEVID_BCM_SPIH_FPGA 0x43f5 /* PCI SPI Host Controller FPGA */ #define PCI_SUBDEVID_BCM_SPIH 0x43f6 /* Synopsis SPI Host Controller */ #define PCI_SUBDEVID_BCM_MIMO_FPGA 0x43f8 /* FPGA mimo minimacphy device id */ #define PCI_SUBDEVID_BCM_JTAGM2 0x43f9 /* PCI_SUBDEVID_BCM alternate jtagm device id */ #define PCI_SUBDEVID_BCM_SDHCI_FPGA 0x43fa /* Standard SDIO Host Controller FPGA */ #define PCI_SUBDEVID_BCM4402_ENET 0x4402 /* 4402 enet */ #define PCI_SUBDEVID_BCM4402_V90 0x4403 /* 4402 v90 codec */ #define PCI_SUBDEVID_BCM4410 0x4410 /* bcm44xx family pci iline */ #define PCI_SUBDEVID_BCM4412 0x4412 /* bcm44xx family pci enet */ #define PCI_SUBDEVID_BCM4430 0x4430 /* bcm44xx family cardbus iline */ #define PCI_SUBDEVID_BCM4432 0x4432 /* bcm44xx family cardbus enet */ #define PCI_SUBDEVID_BCM4704_ENET 0x4706 /* 4704 enet (Use 47XX_ENET_ID instead!) */ #define PCI_SUBDEVID_BCM4710 0x4710 /* 4710 primary function 0 */ #define PCI_SUBDEVID_BCM47XX_AUDIO 0x4711 /* 47xx audio codec */ #define PCI_SUBDEVID_BCM47XX_V90 0x4712 /* 47xx v90 codec */ #define PCI_SUBDEVID_BCM47XX_ENET 0x4713 /* 47xx enet */ #define PCI_SUBDEVID_BCM47XX_EXT 0x4714 /* 47xx external i/f */ #define PCI_SUBDEVID_BCM47XX_GMAC 0x4715 /* 47xx Unimac based GbE */ #define PCI_SUBDEVID_BCM47XX_USBH 0x4716 /* 47xx usb host */ #define PCI_SUBDEVID_BCM47XX_USBD 0x4717 /* 47xx usb device */ #define PCI_SUBDEVID_BCM47XX_IPSEC 0x4718 /* 47xx ipsec */ #define PCI_SUBDEVID_BCM47XX_ROBO 0x4719 /* 47xx/53xx roboswitch core */ #define PCI_SUBDEVID_BCM47XX_USB20H 0x471a /* 47xx usb 2.0 host */ #define PCI_SUBDEVID_BCM47XX_USB20D 0x471b /* 47xx usb 2.0 device */ #define PCI_SUBDEVID_BCM47XX_ATA100 0x471d /* 47xx parallel ATA */ #define PCI_SUBDEVID_BCM47XX_SATAXOR 0x471e /* 47xx serial ATA & XOR DMA */ #define PCI_SUBDEVID_BCM47XX_GIGETH 0x471f /* 47xx GbE (5700) */ #define PCI_SUBDEVID_BCM4712_MIPS 0x4720 /* 4712 base devid */ #define PCI_SUBDEVID_BCM4716 0x4722 /* 4716 base devid */ #define PCI_SUBDEVID_BCM47XX_USB30H 0x472a /* 47xx usb 3.0 host */ #define PCI_SUBDEVID_BCM47XX_USB30D 0x472b /* 47xx usb 3.0 device */ #define PCI_SUBDEVID_BCM47XX_SMBUS_EMU 0x47fe /* 47xx emulated SMBus device */ #define PCI_SUBDEVID_BCM47XX_XOR_EMU 0x47ff /* 47xx emulated XOR engine */ #define PCI_SUBDEVID_BCM_EPI41210 0xa0fa /* bcm4210 */ #define PCI_SUBDEVID_BCM_EPI41230 0xa10e /* bcm4230 */ #define PCI_SUBDEVID_BCM_JINVANI_SDIOH 0x4743 /* Jinvani SDIO Gold Host */ #define PCI_SUBDEVID_BCM27XX_SDIOH 0x2702 /* PCI_SUBDEVID_BCM27xx Standard SDIO Host */ #define PCI_SUBDEVID_BCM_PCIXX21_FLASHMEDIA 0x803b /* TI PCI xx21 Standard Host Controller */ #define PCI_SUBDEVID_BCM_PCIXX21_SDIOH 0x803c /* TI PCI xx21 Standard Host Controller */ #define PCI_SUBDEVID_BCM_R5C822_SDIOH 0x0822 /* Ricoh Co Ltd R5C822 SD/SDIO/MMC/MS/MSPro Host */ #define PCI_SUBDEVID_BCM_JMICRON_SDIOH 0x2381 /* JMicron Standard SDIO Host Controller */ /* Broadcom ChipCommon Chip IDs */ #define BHND_CHIPID_BCM4306 0x4306 /* 4306 chipcommon chipid */ #define BHND_CHIPID_BCM4311 0x4311 /* 4311 PCIe 802.11a/b/g */ #define BHND_CHIPID_BCM43111 43111 /* 43111 chipcommon chipid (OTP chipid) */ #define BHND_CHIPID_BCM43112 43112 /* 43112 chipcommon chipid (OTP chipid) */ #define BHND_CHIPID_BCM4312 0x4312 /* 4312 chipcommon chipid */ #define BHND_CHIPID_BCM4313 0x4313 /* 4313 chip id */ #define BHND_CHIPID_BCM43131 43131 /* 43131 chip id (OTP chipid) */ #define BHND_CHIPID_BCM4315 0x4315 /* 4315 chip id */ #define BHND_CHIPID_BCM4318 0x4318 /* 4318 chipcommon chipid */ #define BHND_CHIPID_BCM4319 0x4319 /* 4319 chip id */ #define BHND_CHIPID_BCM4320 0x4320 /* 4320 chipcommon chipid */ #define BHND_CHIPID_BCM4321 0x4321 /* 4321 chipcommon chipid */ #define BHND_CHIPID_BCM43217 43217 /* 43217 chip id (OTP chipid) */ #define BHND_CHIPID_BCM4322 0x4322 /* 4322 chipcommon chipid */ #define BHND_CHIPID_BCM43221 43221 /* 43221 chipcommon chipid (OTP chipid) */ #define BHND_CHIPID_BCM43222 43222 /* 43222 chipcommon chipid */ #define BHND_CHIPID_BCM43224 43224 /* 43224 chipcommon chipid */ #define BHND_CHIPID_BCM43225 43225 /* 43225 chipcommon chipid */ #define BHND_CHIPID_BCM43227 43227 /* 43227 chipcommon chipid */ #define BHND_CHIPID_BCM43228 43228 /* 43228 chipcommon chipid */ #define BHND_CHIPID_BCM43226 43226 /* 43226 chipcommon chipid */ #define BHND_CHIPID_BCM43231 43231 /* 43231 chipcommon chipid (OTP chipid) */ #define BHND_CHIPID_BCM43234 43234 /* 43234 chipcommon chipid */ #define BHND_CHIPID_BCM43235 43235 /* 43235 chipcommon chipid */ #define BHND_CHIPID_BCM43236 43236 /* 43236 chipcommon chipid */ #define BHND_CHIPID_BCM43237 43237 /* 43237 chipcommon chipid */ #define BHND_CHIPID_BCM43238 43238 /* 43238 chipcommon chipid */ #define BHND_CHIPID_BCM43239 43239 /* 43239 chipcommon chipid */ #define BHND_CHIPID_BCM43420 43420 /* 43222 chipcommon chipid (OTP, RBBU) */ #define BHND_CHIPID_BCM43421 43421 /* 43224 chipcommon chipid (OTP, RBBU) */ #define BHND_CHIPID_BCM43428 43428 /* 43228 chipcommon chipid (OTP, RBBU) */ #define BHND_CHIPID_BCM43431 43431 /* 4331 chipcommon chipid (OTP, RBBU) */ #define BHND_CHIPID_BCM43460 43460 /* 4360 chipcommon chipid (OTP, RBBU) */ #define BHND_CHIPID_BCM43462 0xA9C6 /* 43462 chipcommon chipid */ #define BHND_CHIPID_BCM4325 0x4325 /* 4325 chip id */ #define BHND_CHIPID_BCM4328 0x4328 /* 4328 chip id */ #define BHND_CHIPID_BCM4329 0x4329 /* 4329 chipcommon chipid */ #define BHND_CHIPID_BCM4331 0x4331 /* 4331 chipcommon chipid */ #define BHND_CHIPID_BCM4336 0x4336 /* 4336 chipcommon chipid */ #define BHND_CHIPID_BCM43362 43362 /* 43362 chipcommon chipid */ #define BHND_CHIPID_BCM4330 0x4330 /* 4330 chipcommon chipid */ #define BHND_CHIPID_BCM6362 0x6362 /* 6362 chipcommon chipid */ #define BHND_CHIPID_BCM4314 0x4314 /* 4314 chipcommon chipid */ #define BHND_CHIPID_BCM43142 43142 /* 43142 chipcommon chipid */ #define BHND_CHIPID_BCM43143 43143 /* 43143 chipcommon chipid */ #define BHND_CHIPID_BCM4324 0x4324 /* 4324 chipcommon chipid */ #define BHND_CHIPID_BCM43242 43242 /* 43242 chipcommon chipid */ #define BHND_CHIPID_BCM43243 43243 /* 43243 chipcommon chipid */ #define BHND_CHIPID_BCM4334 0x4334 /* 4334 chipcommon chipid */ #define BHND_CHIPID_BCM4335 0x4335 /* 4335 chipcommon chipid */ #define BHND_CHIPID_BCM4360 0x4360 /* 4360 chipcommon chipid */ #define BHND_CHIPID_BCM43602 0xaa52 /* 43602 chipcommon chipid */ #define BHND_CHIPID_BCM4352 0x4352 /* 4352 chipcommon chipid */ #define BHND_CHIPID_BCM43526 0xAA06 #define BHND_CHIPID_BCM43341 43341 /* 43341 chipcommon chipid */ #define BHND_CHIPID_BCM43342 43342 /* 43342 chipcommon chipid */ #define BHND_CHIPID_BCM4335 0x4335 #define BHND_CHIPID_BCM4350 0x4350 /* 4350 chipcommon chipid */ #define BHND_CHIPID_BCM4342 4342 /* 4342 chipcommon chipid (OTP, RBBU) */ #define BHND_CHIPID_BCM4402 0x4402 /* 4402 chipid */ #define BHND_CHIPID_BCM4704 0x4704 /* 4704 chipcommon chipid */ #define BHND_CHIPID_BCM4706 0x5300 /* 4706 chipcommon chipid */ #define BHND_CHIPID_BCM4707 53010 /* 4707 chipcommon chipid */ #define BHND_CHIPID_BCM53018 53018 /* 53018 chipcommon chipid */ #define BHND_CHIPID_IS_BCM4707(chipid) \ (((chipid) == BHND_CHIPID_BCM4707) || \ ((chipid) == BHND_CHIPID_BCM53018)) #define BHND_CHIPID_BCM4710 0x4710 /* 4710 chipid */ #define BHND_CHIPID_BCM4712 0x4712 /* 4712 chipcommon chipid */ #define BHND_CHIPID_BCM4716 0x4716 /* 4716 chipcommon chipid */ #define BHND_CHIPID_BCM47162 47162 /* 47162 chipcommon chipid */ #define BHND_CHIPID_BCM4748 0x4748 /* 4716 chipcommon chipid (OTP, RBBU) */ #define BHND_CHIPID_BCM4749 0x4749 /* 5357 chipcommon chipid (OTP, RBBU) */ #define BHND_CHIPID_BCM4785 0x4785 /* 4785 chipcommon chipid */ #define BHND_CHIPID_BCM5350 0x5350 /* 5350 chipcommon chipid */ #define BHND_CHIPID_BCM5352 0x5352 /* 5352 chipcommon chipid */ #define BHND_CHIPID_BCM5354 0x5354 /* 5354 chipcommon chipid */ #define BHND_CHIPID_BCM5365 0x5365 /* 5365 chipcommon chipid */ #define BHND_CHIPID_BCM5356 0x5356 /* 5356 chipcommon chipid */ #define BHND_CHIPID_BCM5357 0x5357 /* 5357 chipcommon chipid */ #define BHND_CHIPID_BCM53572 53572 /* 53572 chipcommon chipid */ /* Broadcom ChipCommon Package IDs */ #define BHND_PKGID_BCM4303 2 /* 4303 package id */ #define BHND_PKGID_BCM4309 1 /* 4309 package id */ #define BHND_PKGID_BCM4712LARGE 0 /* 340pin 4712 package id */ #define BHND_PKGID_BCM4712SMALL 1 /* 200pin 4712 package id */ #define BHND_PKGID_BCM4712MID 2 /* 225pin 4712 package id */ #define BHND_PKGID_BCM4328USBD11G 2 /* 4328 802.11g USB package id */ #define BHND_PKGID_BCM4328USBDUAL 3 /* 4328 802.11a/g USB package id */ #define BHND_PKGID_BCM4328SDIOD11G 4 /* 4328 802.11g SDIO package id */ #define BHND_PKGID_BCM4328SDIODUAL 5 /* 4328 802.11a/g SDIO package id */ #define BHND_PKGID_BCM4329_289PIN 0 /* 4329 289-pin package id */ #define BHND_PKGID_BCM4329_182PIN 1 /* 4329N 182-pin package id */ #define BHND_PKGID_BCM5354E 1 /* 5354E package id */ #define BHND_PKGID_BCM4716 8 /* 4716 package id */ #define BHND_PKGID_BCM4717 9 /* 4717 package id */ #define BHND_PKGID_BCM4718 10 /* 4718 package id */ #define BHND_PKGID_BCM5356_NONMODE 1 /* 5356 package without nmode suppport */ #define BHND_PKGID_BCM5358U 8 /* 5358U package id */ #define BHND_PKGID_BCM5358 9 /* 5358 package id */ #define BHND_PKGID_BCM47186 10 /* 47186 package id */ #define BHND_PKGID_BCM5357 11 /* 5357 package id */ #define BHND_PKGID_BCM5356U 12 /* 5356U package id */ #define BHND_PKGID_BCM53572 8 /* 53572 package id */ #define BHND_PKGID_BCM5357C0 8 /* 5357c0 package id (the same as 53572) */ #define BHND_PKGID_BCM47188 9 /* 47188 package id */ #define BHND_PKGID_BCM5358C0 0xa /* 5358c0 package id */ #define BHND_PKGID_BCM5356C0 0xb /* 5356c0 package id */ #define BHND_PKGID_BCM4331TT 8 /* 4331 12x12 package id */ #define BHND_PKGID_BCM4331TN 9 /* 4331 12x9 package id */ #define BHND_PKGID_BCM4331TNA0 0xb /* 4331 12x9 package id */ #define BHND_PKGID_BCM4706L 1 /* 4706L package id */ #define BHND_PKGID_HDLSIM5350 1 /* HDL simulator package id for a 5350 */ #define BHND_PKGID_HDLSIM 14 /* HDL simulator package id */ #define BHND_PKGID_HWSIM 15 /* Hardware simulator package id */ #define BHND_PKGID_BCM43224_FAB_CSM 0x8 /* the chip is manufactured by CSM */ #define BHND_PKGID_BCM43224_FAB_SMIC 0xa /* the chip is manufactured by SMIC */ #define BHND_PKGID_BCM4336_WLBGA 0x8 #define BHND_PKGID_BCM4330_WLBGA 0x0 #define BHND_PKGID_BCM4314PCIE_ARM (8 | 0) /* 4314 QFN PCI package id, bit 3 tie high */ #define BHND_PKGID_BCM4314SDIO (8 | 1) /* 4314 QFN SDIO package id */ #define BHND_PKGID_BCM4314PCIE (8 | 2) /* 4314 QFN PCI (ARM-less) package id */ #define BHND_PKGID_BCM4314SDIO_ARM (8 | 3) /* 4314 QFN SDIO (ARM-less) package id */ #define BHND_PKGID_BCM4314SDIO_FPBGA (8 | 4) /* 4314 FpBGA SDIO package id */ #define BHND_PKGID_BCM4314DEV (8 | 6) /* 4314 Development package id */ #define BHND_PKGID_BCM4707 1 /* 4707 package id */ #define BHND_PKGID_BCM4708 2 /* 4708 package id */ #define BHND_PKGID_BCM4709 0 /* 4709 package id */ #define BHND_PKGID_BCM4335_WLCSP (0x0) /* WLCSP Module/Mobile SDIO/HSIC. */ #define BHND_PKGID_BCM4335_FCBGA (0x1) /* FCBGA PC/Embedded/Media PCIE/SDIO */ #define BHND_PKGID_BCM4335_WLBGA (0x2) /* WLBGA COB/Mobile SDIO/HSIC. */ #define BHND_PKGID_BCM4335_FCBGAD (0x3) /* FCBGA Debug Debug/Dev All if's. */ #define BHND_PKGID_PKG_MASK_BCM4335 (0x3) /* Broadcom Core IDs */ #define BHND_COREID_INVALID 0x700 /* Invalid coreid */ #define BHND_COREID_CC 0x800 /* chipcommon core */ #define BHND_COREID_ILINE20 0x801 /* iline20 core */ #define BHND_COREID_SRAM 0x802 /* sram core */ #define BHND_COREID_SDRAM 0x803 /* sdram core */ #define BHND_COREID_PCI 0x804 /* pci core */ #define BHND_COREID_MIPS 0x805 /* mips core */ #define BHND_COREID_ENET 0x806 /* enet mac core */ #define BHND_COREID_V90_CODEC 0x807 /* v90 codec core */ #define BHND_COREID_USB 0x808 /* usb 1.1 host/device core */ #define BHND_COREID_ADSL 0x809 /* ADSL core */ #define BHND_COREID_ILINE100 0x80a /* iline100 core */ #define BHND_COREID_IPSEC 0x80b /* ipsec core */ #define BHND_COREID_UTOPIA 0x80c /* utopia core */ #define BHND_COREID_PCMCIA 0x80d /* pcmcia core */ #define BHND_COREID_SOCRAM 0x80e /* internal memory core */ #define BHND_COREID_MEMC 0x80f /* memc sdram core */ #define BHND_COREID_OFDM 0x810 /* OFDM phy core */ #define BHND_COREID_EXTIF 0x811 /* external interface core */ #define BHND_COREID_D11 0x812 /* 802.11 MAC core */ #define BHND_COREID_APHY 0x813 /* 802.11a phy core */ #define BHND_COREID_BPHY 0x814 /* 802.11b phy core */ #define BHND_COREID_GPHY 0x815 /* 802.11g phy core */ #define BHND_COREID_MIPS33 0x816 /* mips3302 core */ #define BHND_COREID_USB11H 0x817 /* usb 1.1 host core */ #define BHND_COREID_USB11D 0x818 /* usb 1.1 device core */ #define BHND_COREID_USB20H 0x819 /* usb 2.0 host core */ #define BHND_COREID_USB20D 0x81a /* usb 2.0 device core */ #define BHND_COREID_SDIOH 0x81b /* sdio host core */ #define BHND_COREID_ROBO 0x81c /* roboswitch core */ #define BHND_COREID_ATA100 0x81d /* parallel ATA core */ #define BHND_COREID_SATAXOR 0x81e /* serial ATA & XOR DMA core */ #define BHND_COREID_GIGETH 0x81f /* gigabit ethernet core */ #define BHND_COREID_PCIE 0x820 /* pci express core */ #define BHND_COREID_NPHY 0x821 /* 802.11n 2x2 phy core */ #define BHND_COREID_SRAMC 0x822 /* SRAM controller core */ #define BHND_COREID_MINIMAC 0x823 /* MINI MAC/phy core */ #define BHND_COREID_ARM11 0x824 /* ARM 1176 core */ #define BHND_COREID_ARM7S 0x825 /* ARM7tdmi-s core */ #define BHND_COREID_LPPHY 0x826 /* 802.11a/b/g phy core */ #define BHND_COREID_PMU 0x827 /* PMU core */ #define BHND_COREID_SSNPHY 0x828 /* 802.11n single-stream phy core */ #define BHND_COREID_SDIOD 0x829 /* SDIO device core */ #define BHND_COREID_ARMCM3 0x82a /* ARM Cortex M3 core */ #define BHND_COREID_HTPHY 0x82b /* 802.11n 4x4 phy core */ #define BHND_COREID_MIPS74K 0x82c /* mips 74k core */ #define BHND_COREID_GMAC 0x82d /* Gigabit MAC core */ #define BHND_COREID_DMEMC 0x82e /* DDR1/2 memory controller core */ #define BHND_COREID_PCIERC 0x82f /* PCIE Root Complex core */ #define BHND_COREID_OCP 0x830 /* OCP2OCP bridge core */ #define BHND_COREID_SC 0x831 /* shared common core */ #define BHND_COREID_AHB 0x832 /* OCP2AHB bridge core */ #define BHND_COREID_SPIH 0x833 /* SPI host core */ #define BHND_COREID_I2S 0x834 /* I2S core */ #define BHND_COREID_DMEMS 0x835 /* SDR/DDR1 memory controller core */ #define BHND_COREID_UBUS_SHIM 0x837 /* SHIM component in ubus/6362 */ #define BHND_COREID_PCIE2 0x83c /* pci express (gen2) core */ /* ARM/AMBA Core IDs */ #define BHND_COREID_APB_BRIDGE 0x135 /* BP135 AMBA AXI-APB bridge */ #define BHND_COREID_PL301 0x301 /* PL301 AMBA AXI Interconnect */ #define BHND_COREID_EROM 0x366 /* Enumeration ROM */ #define BHND_COREID_OOB_ROUTER 0x367 /* OOB router core ID */ #define BHND_COREID_AXI_UNMAPPED 0xfff /* AXI "Default Slave"; maps all unused address * ranges, returning DECERR on read or write. */ /* Northstar Plus and BCM4706 Core IDs */ #define BHND_COREID_4706_CC 0x500 /* chipcommon core */ #define BHND_COREID_NS_PCIE2 0x501 /* pci express (gen2) core */ #define BHND_COREID_NS_DMA 0x502 /* dma core */ #define BHND_COREID_NS_SDIO 0x503 /* sdio host core */ #define BHND_COREID_NS_USB20H 0x504 /* usb 2.0 host core */ #define BHND_COREID_NS_USB30H 0x505 /* usb 3.0 host core */ #define BHND_COREID_NS_A9JTAG 0x506 /* ARM Cortex A9 JTAG core */ #define BHND_COREID_NS_DDR23_MEMC 0x507 /* DDR2/3 cadence/denali memory controller core () */ #define BHND_COREID_NS_ROM 0x508 /* device ROM core */ #define BHND_COREID_NS_NAND 0x509 /* NAND flash controller core */ #define BHND_COREID_NS_QSPI 0x50a /* QSPI flash controller core */ #define BHND_COREID_NS_CC_B 0x50b /* chipcommon `b' (auxiliary) core */ #define BHND_COREID_4706_SOCRAM 0x50e /* internal memory core */ #define BHND_COREID_IHOST_ARMCA9 0x510 /* ARM Cortex A9 core */ #define BHND_COREID_4706_GMAC_CMN 0x5dc /* Gigabit MAC common core */ #define BHND_COREID_4706_GMAC 0x52d /* Gigabit MAC core */ #define BHND_COREID_AMEMC 0x52e /* DDR1/2 cadence/denali memory controller core */ /* ARM PrimeCell Peripherial IDs. These were derived from inspection of the * PrimeCell-compatible BCM4331 cores, but due to lack of documentation, the * surmised core name/description may be incorrect. */ #define BHND_PRIMEID_EROM 0x364 /* Enumeration ROM's primecell ID */ #define BHND_PRIMEID_SWRAP 0x368 /* PL368 Device Management Interface (Slave) */ #define BHND_PRIMEID_MWRAP 0x369 /* PL369 Device Management Interface (Master) */ /* Core HW Revision Numbers */ #define BHND_HWREV_INVALID 0xFF /* Invalid hardware revision ID */ /* Chip Types */ #define BHND_CHIPTYPE_SIBA 0 /**< siba(4) interconnect */ #define BHND_CHIPTYPE_BCMA 1 /**< bcma(4) interconnect */ #define BHND_CHIPTYPE_UBUS 2 /**< ubus interconnect found in bcm63xx devices */ #define BHND_CHIPTYPE_BCMA_ALT 3 /**< bcma(4) interconnect */ /** Evaluates to true if @p _type is a BCMA or BCMA-compatible interconenct */ #define BHND_CHIPTYPE_IS_BCMA_COMPATIBLE(_type) \ ((_type) == BHND_CHIPTYPE_BCMA || \ (_type) == BHND_CHIPTYPE_BCMA_ALT || \ (_type) == BHND_CHIPTYPE_UBUS) /** Evaluates to true if @p _type uses a BCMA EROM table */ #define BHND_CHIPTYPE_HAS_EROM(_type) \ BHND_CHIPTYPE_IS_BCMA_COMPATIBLE(_type) /* Boardflags */ #define BHND_BFL_BTC2WIRE 0x00000001 /* old 2wire Bluetooth coexistence, OBSOLETE */ #define BHND_BFL_BTCOEX 0x00000001 /* Board supports BTCOEX */ #define BHND_BFL_PACTRL 0x00000002 /* Board has gpio 9 controlling the PA */ #define BHND_BFL_AIRLINEMODE 0x00000004 /* Board implements gpio 13 radio disable indication, UNUSED */ #define BHND_BFL_ADCDIV 0x00000008 /* Board has the rssi ADC divider */ #define BHND_BFL_DIS_256QAM 0x00000008 #define BHND_BFL_ENETROBO 0x00000010 /* Board has robo switch or core */ #define BHND_BFL_NOPLLDOWN 0x00000020 /* Not ok to power down the chip pll and oscillator */ #define BHND_BFL_CCKHIPWR 0x00000040 /* Can do high-power CCK transmission */ #define BHND_BFL_ENETADM 0x00000080 /* Board has ADMtek switch */ #define BHND_BFL_ENETVLAN 0x00000100 /* Board has VLAN capability */ #define BHND_BFL_LTECOEX 0x00000200 /* Board has LTE coex capability */ #define BHND_BFL_NOPCI 0x00000400 /* Board leaves PCI floating */ #define BHND_BFL_FEM 0x00000800 /* Board supports the Front End Module */ #define BHND_BFL_EXTLNA 0x00001000 /* Board has an external LNA in 2.4GHz band */ #define BHND_BFL_HGPA 0x00002000 /* Board has a high gain PA */ #define BHND_BFL_BTC2WIRE_ALTGPIO 0x00004000 /* Board's BTC 2wire is in the alternate gpios OBSLETE */ #define BHND_BFL_ALTIQ 0x00008000 /* Alternate I/Q settings */ #define BHND_BFL_NOPA 0x00010000 /* Board has no PA */ #define BHND_BFL_RSSIINV 0x00020000 /* Board's RSSI uses positive slope(not TSSI) */ #define BHND_BFL_PAREF 0x00040000 /* Board uses the PARef LDO */ #define BHND_BFL_3TSWITCH 0x00080000 /* Board uses a triple throw switch shared with BT */ #define BHND_BFL_PHASESHIFT 0x00100000 /* Board can support phase shifter */ #define BHND_BFL_BUCKBOOST 0x00200000 /* Power topology uses BUCKBOOST */ #define BHND_BFL_FEM_BT 0x00400000 /* Board has FEM and switch to share antenna w/ BT */ #define BHND_BFL_RXCHAIN_OFF_BT 0x00400000 /* one rxchain is to be shut off when BT is active */ #define BHND_BFL_NOCBUCK 0x00800000 /* Power topology doesn't use CBUCK */ #define BHND_BFL_CCKFAVOREVM 0x01000000 /* Favor CCK EVM over spectral mask */ #define BHND_BFL_PALDO 0x02000000 /* Power topology uses PALDO */ #define BHND_BFL_LNLDO2_2P5 0x04000000 /* Select 2.5V as LNLDO2 output voltage */ #define BHND_BFL_FASTPWR 0x08000000 #define BHND_BFL_UCPWRCTL_MININDX 0x08000000 /* Enforce min power index to avoid FEM damage */ -#define BHND_BFL_EXTLNA_5GHz 0x10000000 /* Board has an external LNA in 5GHz band */ -#define BHND_BFL_TRSW_1by2 0x20000000 /* Board has 2 TRSW's in 1by2 designs */ +#define BHND_BFL_EXTLNA_5GHZ 0x10000000 /* Board has an external LNA in 5GHz band */ +#define BHND_BFL_TRSW_1BY2 0x20000000 /* Board has 2 TRSW's in 1by2 designs */ #define BHND_BFL_GAINBOOSTA01 0x20000000 /* 5g Gainboost for core0 and core1 */ -#define BHND_BFL_LO_TRSW_R_5GHz 0x40000000 /* In 5G do not throw TRSW to T for clipLO gain */ +#define BHND_BFL_LO_TRSW_R_5GHZ 0x40000000 /* In 5G do not throw TRSW to T for clipLO gain */ #define BHND_BFL_ELNA_GAINDEF 0x80000000 /* Backoff InitGain based on elna_2g/5g field * when this flag is set */ #define BHND_BFL_EXTLNA_TX 0x20000000 /* Temp boardflag to indicate to */ /* Boardflags2 */ #define BHND_BFL2_RXBB_INT_REG_DIS 0x00000001 /* Board has an external rxbb regulator */ #define BHND_BFL2_APLL_WAR 0x00000002 /* Flag to implement alternative A-band PLL settings */ #define BHND_BFL2_TXPWRCTRL_EN 0x00000004 /* Board permits enabling TX Power Control */ #define BHND_BFL2_2X4_DIV 0x00000008 /* Board supports the 2X4 diversity switch */ #define BHND_BFL2_5G_PWRGAIN 0x00000010 /* Board supports 5G band power gain */ #define BHND_BFL2_PCIEWAR_OVR 0x00000020 /* Board overrides ASPM and Clkreq settings */ #define BHND_BFL2_CAESERS_BRD 0x00000040 /* Board is Caesers brd (unused by sw) */ #define BHND_BFL2_BTC3WIRE 0x00000080 /* Board support legacy 3 wire or 4 wire */ #define BHND_BFL2_BTCLEGACY 0x00000080 /* Board support legacy 3/4 wire, to replace * BHND_BFL2_BTC3WIRE */ #define BHND_BFL2_SKWRKFEM_BRD 0x00000100 /* 4321mcm93 board uses Skyworks FEM */ #define BHND_BFL2_SPUR_WAR 0x00000200 /* Board has a WAR for clock-harmonic spurs */ #define BHND_BFL2_GPLL_WAR 0x00000400 /* Flag to narrow G-band PLL loop b/w */ #define BHND_BFL2_TRISTATE_LED 0x00000800 /* Tri-state the LED */ #define BHND_BFL2_SINGLEANT_CCK 0x00001000 /* Tx CCK pkts on Ant 0 only */ #define BHND_BFL2_2G_SPUR_WAR 0x00002000 /* WAR to reduce and avoid clock-harmonic spurs in 2G */ #define BHND_BFL2_BPHY_ALL_TXCORES 0x00004000 /* Transmit bphy frames using all tx cores */ #define BHND_BFL2_FCC_BANDEDGE_WAR 0x00008000 /* Activates WAR to improve FCC bandedge performance */ #define BHND_BFL2_GPLL_WAR2 0x00010000 /* Flag to widen G-band PLL loop b/w */ #define BHND_BFL2_IPALVLSHIFT_3P3 0x00020000 #define BHND_BFL2_INTERNDET_TXIQCAL 0x00040000 /* Use internal envelope detector for TX IQCAL */ #define BHND_BFL2_XTALBUFOUTEN 0x00080000 /* Keep the buffered Xtal output from radio on */ /* Most drivers will turn it off without this flag */ /* to save power. */ #define BHND_BFL2_ANAPACTRL_2G 0x00100000 /* 2G ext PAs are controlled by analog PA ctrl lines */ #define BHND_BFL2_ANAPACTRL_5G 0x00200000 /* 5G ext PAs are controlled by analog PA ctrl lines */ #define BHND_BFL2_ELNACTRL_TRSW_2G 0x00400000 /* AZW4329: 2G gmode_elna_gain controls TR Switch */ #define BHND_BFL2_BT_SHARE_ANT0 0x00800000 /* WLAN/BT share antenna 0 */ #define BHND_BFL2_BT_SHARE_BM_BIT0 0x00800000 /* bit 0 of WLAN/BT shared core bitmap */ #define BHND_BFL2_TEMPSENSE_HIGHER 0x01000000 /* The tempsense threshold can sustain higher value * than programmed. The exact delta is decided by * driver per chip/boardtype. This can be used * when tempsense qualification happens after shipment */ #define BHND_BFL2_BTC3WIREONLY 0x02000000 /* standard 3 wire btc only. 4 wire not supported */ #define BHND_BFL2_PWR_NOMINAL 0x04000000 /* 0: power reduction on, 1: no power reduction */ #define BHND_BFL2_EXTLNA_PWRSAVE 0x08000000 /* boardflag to enable ucode to apply power save * ucode control of eLNA during Tx */ #define BHND_BFL2_4313_RADIOREG 0x10000000 /* board rework */ #define BHND_BFL2_DYNAMIC_VMID 0x10000000 /* boardflag to enable dynamic Vmid idle TSSI CAL */ #define BHND_BFL2_SDR_EN 0x20000000 /* SDR enabled or disabled */ #define BHND_BFL2_LNA1BYPFORTR2G 0x40000000 /* acphy, enable lna1 bypass for clip gain, 2g */ #define BHND_BFL2_LNA1BYPFORTR5G 0x80000000 /* acphy, enable lna1 bypass for clip gain, 5g */ /* SROM 11 - 11ac boardflag definitions */ #define BHND_BFL_SROM11_BTCOEX 0x00000001 /* Board supports BTCOEX */ #define BHND_BFL_SROM11_WLAN_BT_SH_XTL 0x00000002 /* bluetooth and wlan share same crystal */ #define BHND_BFL_SROM11_EXTLNA 0x00001000 /* Board has an external LNA in 2.4GHz band */ -#define BHND_BFL_SROM11_EXTLNA_5GHz 0x10000000 /* Board has an external LNA in 5GHz band */ +#define BHND_BFL_SROM11_EXTLNA_5GHZ 0x10000000 /* Board has an external LNA in 5GHz band */ #define BHND_BFL_SROM11_GAINBOOSTA01 0x20000000 /* 5g Gainboost for core0 and core1 */ #define BHND_BFL2_SROM11_APLL_WAR 0x00000002 /* Flag to implement alternative A-band PLL settings */ #define BHND_BFL2_SROM11_ANAPACTRL_2G 0x00100000 /* 2G ext PAs are ctrl-ed by analog PA ctrl lines */ #define BHND_BFL2_SROM11_ANAPACTRL_5G 0x00200000 /* 5G ext PAs are ctrl-ed by analog PA ctrl lines */ /* Boardflags3 */ #define BHND_BFL3_FEMCTRL_SUB 0x00000007 /* acphy, subrevs of femctrl on top of srom_femctrl */ #define BHND_BFL3_RCAL_WAR 0x00000008 /* acphy, rcal war active on this board (4335a0) */ #define BHND_BFL3_TXGAINTBLID 0x00000070 /* acphy, txgain table id */ #define BHND_BFL3_TXGAINTBLID_SHIFT 0x4 /* acphy, txgain table id shift bit */ #define BHND_BFL3_TSSI_DIV_WAR 0x00000080 /* acphy, Separate paparam for 20/40/80 */ #define BHND_BFL3_TSSI_DIV_WAR_SHIFT 0x7 /* acphy, Separate paparam for 20/40/80 shift bit */ #define BHND_BFL3_FEMTBL_FROM_NVRAM 0x00000100 /* acphy, femctrl table is read from nvram */ #define BHND_BFL3_FEMTBL_FROM_NVRAM_SHIFT 0x8 /* acphy, femctrl table is read from nvram */ #define BHND_BFL3_AGC_CFG_2G 0x00000200 /* acphy, gain control configuration for 2G */ #define BHND_BFL3_AGC_CFG_5G 0x00000400 /* acphy, gain control configuration for 5G */ #define BHND_BFL3_PPR_BIT_EXT 0x00000800 /* acphy, bit position for 1bit extension for ppr */ #define BHND_BFL3_PPR_BIT_EXT_SHIFT 11 /* acphy, bit shift for 1bit extension for ppr */ #define BHND_BFL3_BBPLL_SPR_MODE_DIS 0x00001000 /* acphy, disables bbpll spur modes */ #define BHND_BFL3_RCAL_OTP_VAL_EN 0x00002000 /* acphy, to read rcal_trim value from otp */ #define BHND_BFL3_2GTXGAINTBL_BLANK 0x00004000 /* acphy, blank the first X ticks of 2g gaintbl */ #define BHND_BFL3_2GTXGAINTBL_BLANK_SHIFT 14 /* acphy, blank the first X ticks of 2g gaintbl */ #define BHND_BFL3_5GTXGAINTBL_BLANK 0x00008000 /* acphy, blank the first X ticks of 5g gaintbl */ #define BHND_BFL3_5GTXGAINTBL_BLANK_SHIFT 15 /* acphy, blank the first X ticks of 5g gaintbl */ #define BHND_BFL3_BT_SHARE_BM_BIT1 0x40000000 /* bit 1 of WLAN/BT shared core bitmap */ #define BHND_BFL3_PHASETRACK_MAX_ALPHABETA 0x00010000 /* acphy, to max out alpha,beta to 511 */ #define BHND_BFL3_PHASETRACK_MAX_ALPHABETA_SHIFT 16 /* acphy, to max out alpha,beta to 511 */ #define BHND_BFL3_BT_SHARE_BM_BIT1 0x40000000 /* bit 1 of WLAN/BT shared core bitmap */ #define BHND_BFL3_EN_NONBRCM_TXBF 0x10000000 /* acphy, enable non-brcm TXBF */ #define BHND_BFL3_EN_P2PLINK_TXBF 0x20000000 /* acphy, enable TXBF in p2p links */ /* board specific GPIO assignment, gpio 0-3 are also customer-configurable led */ #define BHND_GPIO_BOARD_BTC3W_IN 0x850 /* bit 4 is RF_ACTIVE, bit 6 is STATUS, bit 11 is PRI */ #define BHND_GPIO_BOARD_BTC3W_OUT 0x020 /* bit 5 is TX_CONF */ #define BHND_GPIO_BOARD_BTCMOD_IN 0x010 /* bit 4 is the alternate BT Coexistence Input */ #define BHND_GPIO_BOARD_BTCMOD_OUT 0x020 /* bit 5 is the alternate BT Coexistence Out */ #define BHND_GPIO_BOARD_BTC_IN 0x080 /* bit 7 is BT Coexistence Input */ #define BHND_GPIO_BOARD_BTC_OUT 0x100 /* bit 8 is BT Coexistence Out */ #define BHND_GPIO_BOARD_PACTRL 0x200 /* bit 9 controls the PA on new 4306 boards */ #define BHND_GPIO_BOARD_12 0x1000 /* gpio 12 */ #define BHND_GPIO_BOARD_13 0x2000 /* gpio 13 */ #define BHND_GPIO_BOARD_BTC4_IN 0x0800 /* gpio 11, coex4, in */ #define BHND_GPIO_BOARD_BTC4_BT 0x2000 /* gpio 12, coex4, bt active */ #define BHND_GPIO_BOARD_BTC4_STAT 0x4000 /* gpio 14, coex4, status */ #define BHND_GPIO_BOARD_BTC4_WLAN 0x8000 /* gpio 15, coex4, wlan active */ #define BHND_GPIO_BOARD_1_WLAN_PWR 0x02 /* throttle WLAN power on X21 board */ #define BHND_GPIO_BOARD_3_WLAN_PWR 0x08 /* throttle WLAN power on X28 board */ #define BHND_GPIO_BOARD_4_WLAN_PWR 0x10 /* throttle WLAN power on X19 board */ #define BHND_GPIO_BTC4W_OUT_4312 0x010 /* bit 4 is BT_IODISABLE */ #define BHND_GPIO_BTC4W_OUT_43224 0x020 /* bit 5 is BT_IODISABLE */ #define BHND_GPIO_BTC4W_OUT_43224_SHARED 0x0e0 /* bit 5 is BT_IODISABLE */ #define BHND_GPIO_BTC4W_OUT_43225 0x0e0 /* bit 5 BT_IODISABLE, bit 6 SW_BT, bit 7 SW_WL */ #define BHND_GPIO_BTC4W_OUT_43421 0x020 /* bit 5 is BT_IODISABLE */ #define BHND_GPIO_BTC4W_OUT_4313 0x060 /* bit 5 SW_BT, bit 6 SW_WL */ #define BHND_GPIO_BTC4W_OUT_4331_SHARED 0x010 /* GPIO 4 */ /* Board Types */ #define BHND_BOARD_BU4710 0x0400 #define BHND_BOARD_VSIM4710 0x0401 #define BHND_BOARD_QT4710 0x0402 #define BHND_BOARD_BU4309 0x040a #define BHND_BOARD_BCM94309CB 0x040b #define BHND_BOARD_BCM94309MP 0x040c #define BHND_BOARD_BCM4309AP 0x040d #define BHND_BOARD_BCM94302MP 0x040e #define BHND_BOARD_BU4306 0x0416 #define BHND_BOARD_BCM94306CB 0x0417 #define BHND_BOARD_BCM94306MP 0x0418 #define BHND_BOARD_BCM94710D 0x041a #define BHND_BOARD_BCM94710R1 0x041b #define BHND_BOARD_BCM94710R4 0x041c #define BHND_BOARD_BCM94710AP 0x041d #define BHND_BOARD_BU2050 0x041f #define BHND_BOARD_BCM94309G 0x0421 #define BHND_BOARD_BU4704 0x0423 #define BHND_BOARD_BU4702 0x0424 #define BHND_BOARD_BCM94306PC 0x0425 /* pcmcia 3.3v 4306 card */ #define BHND_BOARD_BCM94702MN 0x0428 /* BCM4702 1U CompactPCI Board */ #define BHND_BOARD_BCM94702CPCI 0x0429 /* BCM4702 with BCM95380 VLAN Router */ #define BHND_BOARD_BCM95380RR 0x042a /* cb4306 with SiGe PA */ #define BHND_BOARD_BCM94306CBSG 0x042b /* cb4306 with SiGe PA */ #define BHND_BOARD_PCSG94306 0x042d /* bu4704 with sdram */ #define BHND_BOARD_BU4704SD 0x042e /* Dual 11a/11g Router */ #define BHND_BOARD_BCM94704AGR 0x042f /* 11a-only minipci */ #define BHND_BOARD_BCM94308MP 0x0430 #define BHND_BOARD_BU4712 0x0444 #define BHND_BOARD_BU4712SD 0x045d #define BHND_BOARD_BU4712L 0x045f /* BCM4712 boards */ #define BHND_BOARD_BCM94712AP 0x0445 #define BHND_BOARD_BCM94712P 0x0446 /* BCM4318 boards */ #define BHND_BOARD_BU4318 0x0447 #define BHND_BOARD_CB4318 0x0448 #define BHND_BOARD_MPG4318 0x0449 #define BHND_BOARD_MP4318 0x044a #define BHND_BOARD_SD4318 0x044b /* BCM4313 boards */ #define BHND_BOARD_BCM94313BU 0x050f #define BHND_BOARD_BCM94313HM 0x0510 #define BHND_BOARD_BCM94313EPA 0x0511 #define BHND_BOARD_BCM94313HMG 0x051C /* BCM63XX boards */ #define BHND_BOARD_BCM96338 0x6338 #define BHND_BOARD_BCM96348 0x6348 #define BHND_BOARD_BCM96358 0x6358 #define BHND_BOARD_BCM96368 0x6368 /* Another mp4306 with SiGe */ #define BHND_BOARD_BCM94306P 0x044c /* mp4303 */ #define BHND_BOARD_BCM94303MP 0x044e /* mpsgh4306 */ #define BHND_BOARD_BCM94306MPSGH 0x044f /* BRCM 4306 w/ Front End Modules */ #define BHND_BOARD_BCM94306MPM 0x0450 #define BHND_BOARD_BCM94306MPL 0x0453 /* 4712agr */ #define BHND_BOARD_BCM94712AGR 0x0451 /* pcmcia 4303 */ #define BHND_BOARD_PC4303 0x0454 /* 5350K */ #define BHND_BOARD_BCM95350K 0x0455 /* 5350R */ #define BHND_BOARD_BCM95350R 0x0456 /* 4306mplna */ #define BHND_BOARD_BCM94306MPLNA 0x0457 /* 4320 boards */ #define BHND_BOARD_BU4320 0x0458 #define BHND_BOARD_BU4320S 0x0459 #define BHND_BOARD_BCM94320PH 0x045a /* 4306mph */ #define BHND_BOARD_BCM94306MPH 0x045b /* 4306pciv */ #define BHND_BOARD_BCM94306PCIV 0x045c #define BHND_BOARD_BU4712SD 0x045d #define BHND_BOARD_BCM94320PFLSH 0x045e #define BHND_BOARD_BU4712L 0x045f #define BHND_BOARD_BCM94712LGR 0x0460 #define BHND_BOARD_BCM94320R 0x0461 #define BHND_BOARD_BU5352 0x0462 #define BHND_BOARD_BCM94318MPGH 0x0463 #define BHND_BOARD_BU4311 0x0464 #define BHND_BOARD_BCM94311MC 0x0465 #define BHND_BOARD_BCM94311MCAG 0x0466 #define BHND_BOARD_BCM95352GR 0x0467 /* bcm95351agr */ #define BHND_BOARD_BCM95351AGR 0x0470 /* bcm94704mpcb */ #define BHND_BOARD_BCM94704MPCB 0x0472 /* 4785 boards */ #define BHND_BOARD_BU4785 0x0478 /* 4321 boards */ #define BHND_BOARD_BCM4321BU 0x046b #define BHND_BOARD_BCM4321BUE 0x047c #define BHND_BOARD_BCM4321MP 0x046c #define BHND_BOARD_BCM4321CB2 0x046d #define BHND_BOARD_BCM4321CB2_AG 0x0066 #define BHND_BOARD_BCM4321MC 0x046e /* 4328 boards */ #define BHND_BOARD_BU4328 0x0481 #define BHND_BOARD_BCM4328SDG 0x0482 #define BHND_BOARD_BCM4328SDAG 0x0483 #define BHND_BOARD_BCM4328UG 0x0484 #define BHND_BOARD_BCM4328UAG 0x0485 #define BHND_BOARD_BCM4328PC 0x0486 #define BHND_BOARD_BCM4328CF 0x0487 /* 4325 boards */ #define BHND_BOARD_BCM94325DEVBU 0x0490 #define BHND_BOARD_BCM94325BGABU 0x0491 #define BHND_BOARD_BCM94325SDGWB 0x0492 #define BHND_BOARD_BCM94325SDGMDL 0x04aa #define BHND_BOARD_BCM94325SDGMDL2 0x04c6 #define BHND_BOARD_BCM94325SDGMDL3 0x04c9 #define BHND_BOARD_BCM94325SDABGWBA 0x04e1 /* 4322 boards */ #define BHND_BOARD_BCM94322MC 0x04a4 #define BHND_BOARD_BCM94322USB 0x04a8 /* dualband */ #define BHND_BOARD_BCM94322HM 0x04b0 #define BHND_BOARD_BCM94322USB2D 0x04bf /* single band discrete front end */ /* 4312 boards */ #define BHND_BOARD_BCM4312MCGSG 0x04b5 /* 4315 boards */ #define BHND_BOARD_BCM94315DEVBU 0x04c2 #define BHND_BOARD_BCM94315USBGP 0x04c7 #define BHND_BOARD_BCM94315BGABU 0x04ca #define BHND_BOARD_BCM94315USBGP41 0x04cb /* 4319 boards */ #define BHND_BOARD_BCM94319DEVBU 0X04e5 #define BHND_BOARD_BCM94319USB 0X04e6 #define BHND_BOARD_BCM94319SD 0X04e7 /* 4716 boards */ #define BHND_BOARD_BCM94716NR2 0x04cd /* 4319 boards */ #define BHND_BOARD_BCM94319DEVBU 0X04e5 #define BHND_BOARD_BCM94319USBNP4L 0X04e6 #define BHND_BOARD_BCM94319WLUSBN4L 0X04e7 #define BHND_BOARD_BCM94319SDG 0X04ea #define BHND_BOARD_BCM94319LCUSBSDN4L 0X04eb #define BHND_BOARD_BCM94319USBB 0x04ee #define BHND_BOARD_BCM94319LCSDN4L 0X0507 #define BHND_BOARD_BCM94319LSUSBN4L 0X0508 #define BHND_BOARD_BCM94319SDNA4L 0X0517 #define BHND_BOARD_BCM94319SDELNA4L 0X0518 #define BHND_BOARD_BCM94319SDELNA6L 0X0539 #define BHND_BOARD_BCM94319ARCADYAN 0X0546 #define BHND_BOARD_BCM94319WINDSOR 0x0561 #define BHND_BOARD_BCM94319MLAP 0x0562 #define BHND_BOARD_BCM94319SDNA 0x058b #define BHND_BOARD_BCM94319BHEMU3 0x0563 #define BHND_BOARD_BCM94319SDHMB 0x058c #define BHND_BOARD_BCM94319SDBREF 0x05a1 #define BHND_BOARD_BCM94319USBSDB 0x05a2 /* 4329 boards */ #define BHND_BOARD_BCM94329AGB 0X04b9 #define BHND_BOARD_BCM94329TDKMDL1 0X04ba #define BHND_BOARD_BCM94329TDKMDL11 0X04fc #define BHND_BOARD_BCM94329OLYMPICN18 0X04fd #define BHND_BOARD_BCM94329OLYMPICN90 0X04fe #define BHND_BOARD_BCM94329OLYMPICN90U 0X050c #define BHND_BOARD_BCM94329OLYMPICN90M 0X050b #define BHND_BOARD_BCM94329AGBF 0X04ff #define BHND_BOARD_BCM94329OLYMPICX17 0X0504 #define BHND_BOARD_BCM94329OLYMPICX17M 0X050a #define BHND_BOARD_BCM94329OLYMPICX17U 0X0509 #define BHND_BOARD_BCM94329OLYMPICUNO 0X0564 #define BHND_BOARD_BCM94329MOTOROLA 0X0565 #define BHND_BOARD_BCM94329OLYMPICLOCO 0X0568 /* 4336 SDIO board types */ #define BHND_BOARD_BCM94336SD_WLBGABU 0x0511 #define BHND_BOARD_BCM94336SD_WLBGAREF 0x0519 #define BHND_BOARD_BCM94336SDGP 0x0538 #define BHND_BOARD_BCM94336SDG 0x0519 #define BHND_BOARD_BCM94336SDGN 0x0538 #define BHND_BOARD_BCM94336SDGFC 0x056B /* 4330 SDIO board types */ #define BHND_BOARD_BCM94330SDG 0x0528 #define BHND_BOARD_BCM94330SD_FCBGABU 0x052e #define BHND_BOARD_BCM94330SD_WLBGABU 0x052f #define BHND_BOARD_BCM94330SD_FCBGA 0x0530 #define BHND_BOARD_BCM94330FCSDAGB 0x0532 #define BHND_BOARD_BCM94330OLYMPICAMG 0x0549 #define BHND_BOARD_BCM94330OLYMPICAMGEPA 0x054F #define BHND_BOARD_BCM94330OLYMPICUNO3 0x0551 #define BHND_BOARD_BCM94330WLSDAGB 0x0547 #define BHND_BOARD_BCM94330CSPSDAGBB 0x054A /* 43224 boards */ #define BHND_BOARD_BCM943224X21 0x056e #define BHND_BOARD_BCM943224X21_FCC 0x00d1 #define BHND_BOARD_BCM943224X21B 0x00e9 #define BHND_BOARD_BCM943224M93 0x008b #define BHND_BOARD_BCM943224M93A 0x0090 #define BHND_BOARD_BCM943224X16 0x0093 #define BHND_BOARD_BCM94322X9 0x008d #define BHND_BOARD_BCM94322M35e 0x008e /* 43228 Boards */ #define BHND_BOARD_BCM943228BU8 0x0540 #define BHND_BOARD_BCM943228BU9 0x0541 #define BHND_BOARD_BCM943228BU 0x0542 #define BHND_BOARD_BCM943227HM4L 0x0543 #define BHND_BOARD_BCM943227HMB 0x0544 #define BHND_BOARD_BCM943228HM4L 0x0545 #define BHND_BOARD_BCM943228SD 0x0573 /* 43239 Boards */ #define BHND_BOARD_BCM943239MOD 0x05ac #define BHND_BOARD_BCM943239REF 0x05aa /* 4331 boards */ #define BHND_BOARD_BCM94331X19 0x00D6 /* X19B */ #define BHND_BOARD_BCM94331X28 0x00E4 /* X28 */ #define BHND_BOARD_BCM94331X28B 0x010E /* X28B */ #define BHND_BOARD_BCM94331PCIEBT3Ax BCM94331X28 #define BHND_BOARD_BCM94331X12_2G 0x00EC /* X12 2G */ #define BHND_BOARD_BCM94331X12_5G 0x00ED /* X12 5G */ #define BHND_BOARD_BCM94331X29B 0x00EF /* X29B */ #define BHND_BOARD_BCM94331X29D 0x010F /* X29D */ #define BHND_BOARD_BCM94331CSAX BCM94331X29B #define BHND_BOARD_BCM94331X19C 0x00F5 /* X19C */ #define BHND_BOARD_BCM94331X33 0x00F4 /* X33 */ #define BHND_BOARD_BCM94331BU 0x0523 #define BHND_BOARD_BCM94331S9BU 0x0524 #define BHND_BOARD_BCM94331MC 0x0525 #define BHND_BOARD_BCM94331MCI 0x0526 #define BHND_BOARD_BCM94331PCIEBT4 0x0527 #define BHND_BOARD_BCM94331HM 0x0574 #define BHND_BOARD_BCM94331PCIEDUAL 0x059B #define BHND_BOARD_BCM94331MCH5 0x05A9 #define BHND_BOARD_BCM94331CS 0x05C6 #define BHND_BOARD_BCM94331CD 0x05DA /* 4314 Boards */ #define BHND_BOARD_BCM94314BU 0x05b1 /* 53572 Boards */ #define BHND_BOARD_BCM953572BU 0x058D #define BHND_BOARD_BCM953572NR2 0x058E #define BHND_BOARD_BCM947188NR2 0x058F #define BHND_BOARD_BCM953572SDRNR2 0x0590 /* 43236 boards */ #define BHND_BOARD_BCM943236OLYMPICSULLEY 0x594 #define BHND_BOARD_BCM943236PREPROTOBLU2O3 0x5b9 #define BHND_BOARD_BCM943236USBELNA 0x5f8 /* 4314 Boards */ #define BHND_BOARD_BCM94314BUSDIO 0x05c8 #define BHND_BOARD_BCM94314BGABU 0x05c9 #define BHND_BOARD_BCM94314HMEPA 0x05ca #define BHND_BOARD_BCM94314HMEPABK 0x05cb #define BHND_BOARD_BCM94314SUHMEPA 0x05cc #define BHND_BOARD_BCM94314SUHM 0x05cd #define BHND_BOARD_BCM94314HM 0x05d1 /* 4334 Boards */ #define BHND_BOARD_BCM94334FCAGBI 0x05df #define BHND_BOARD_BCM94334WLAGBI 0x05dd /* 4335 Boards */ #define BHND_BOARD_BCM94335X52 0x0114 /* 4345 Boards */ #define BHND_BOARD_BCM94345 0x0687 /* 4360 Boards */ #define BHND_BOARD_BCM94360X52C 0X0117 #define BHND_BOARD_BCM94360X52D 0X0137 #define BHND_BOARD_BCM94360X29C 0X0112 #define BHND_BOARD_BCM94360X29CP2 0X0134 #define BHND_BOARD_BCM94360X51 0x0111 #define BHND_BOARD_BCM94360X51P2 0x0129 #define BHND_BOARD_BCM94360X51A 0x0135 #define BHND_BOARD_BCM94360X51B 0x0136 #define BHND_BOARD_BCM94360CS 0x061B #define BHND_BOARD_BCM94360J28_D11AC2G 0x0c00 #define BHND_BOARD_BCM94360J28_D11AC5G 0x0c01 #define BHND_BOARD_BCM94360USBH5_D11AC5G 0x06aa /* 4350 Boards */ #define BHND_BOARD_BCM94350X52B 0X0116 #define BHND_BOARD_BCM94350X14 0X0131 /* 43217 Boards */ #define BHND_BOARD_BCM943217BU 0x05d5 #define BHND_BOARD_BCM943217HM2L 0x05d6 #define BHND_BOARD_BCM943217HMITR2L 0x05d7 /* 43142 Boards */ #define BHND_BOARD_BCM943142HM 0x05e0 /* 43341 Boards */ #define BHND_BOARD_BCM943341WLABGS 0x062d /* 43342 Boards */ #define BHND_BOARD_BCM943342FCAGBI 0x0641 /* 43602 Boards, unclear yet what boards will be created. */ #define BHND_BOARD_BCM943602RSVD1 0x06a5 #define BHND_BOARD_BCM943602RSVD2 0x06a6 #define BHND_BOARD_BCM943602X87 0X0133 #define BHND_BOARD_BCM943602X238 0X0132 /* 4354 board types */ #define BHND_BOARD_BCM94354WLSAGBI 0x06db #define BHND_BOARD_BCM94354Z 0x0707 /* # of GPIO pins */ #define BHND_BCM43XX_GPIO_NUMPINS 32 /* These values are used by dhd USB host driver. */ #define BHND_USB_RDL_RAM_BASE_4319 0x60000000 #define BHND_USB_RDL_RAM_BASE_4329 0x60000000 #define BHND_USB_RDL_RAM_SIZE_4319 0x48000 #define BHND_USB_RDL_RAM_SIZE_4329 0x48000 #define BHND_USB_RDL_RAM_SIZE_43236 0x70000 #define BHND_USB_RDL_RAM_BASE_43236 0x60000000 #define BHND_USB_RDL_RAM_SIZE_4328 0x60000 #define BHND_USB_RDL_RAM_BASE_4328 0x80000000 #define BHND_USB_RDL_RAM_SIZE_4322 0x60000 #define BHND_USB_RDL_RAM_BASE_4322 0x60000000 #define BHND_USB_RDL_RAM_SIZE_4360 0xA0000 #define BHND_USB_RDL_RAM_BASE_4360 0x60000000 #define BHND_USB_RDL_RAM_SIZE_43242 0x90000 #define BHND_USB_RDL_RAM_BASE_43242 0x60000000 #define BHND_USB_RDL_RAM_SIZE_43143 0x70000 #define BHND_USB_RDL_RAM_BASE_43143 0x60000000 #define BHND_USB_RDL_RAM_SIZE_4350 0xC0000 #define BHND_USB_RDL_RAM_BASE_4350 0x180800 /* generic defs for nvram "muxenab" bits * Note: these differ for 4335a0. refer bcmchipc.h for specific mux options. */ #define BHND_NVRAM_MUXENAB_UART 0x00000001 #define BHND_NVRAM_MUXENAB_GPIO 0x00000002 #define BHND_NVRAM_MUXENAB_ERCX 0x00000004 /* External Radio BT coex */ #define BHND_NVRAM_MUXENAB_JTAG 0x00000008 #define BHND_NVRAM_MUXENAB_HOST_WAKE 0x00000010 /* configure GPIO for SDIO host_wake */ #define BHND_NVRAM_MUXENAB_I2S_EN 0x00000020 #define BHND_NVRAM_MUXENAB_I2S_MASTER 0x00000040 #define BHND_NVRAM_MUXENAB_I2S_FULL 0x00000080 #define BHND_NVRAM_MUXENAB_SFLASH 0x00000100 #define BHND_NVRAM_MUXENAB_RFSWCTRL0 0x00000200 #define BHND_NVRAM_MUXENAB_RFSWCTRL1 0x00000400 #define BHND_NVRAM_MUXENAB_RFSWCTRL2 0x00000800 #define BHND_NVRAM_MUXENAB_SECI 0x00001000 #define BHND_NVRAM_MUXENAB_BT_LEGACY 0x00002000 #define BHND_NVRAM_MUXENAB_HOST_WAKE1 0x00004000 /* configure alternative GPIO for SDIO host_wake */ /* Boot flags */ #define BHND_BOOTFLAG_FLASH_KERNEL_NFLASH 0x00000001 #define BHND_BOOTFLAG_FLASH_BOOT_NFLASH 0x00000002 #endif /* _BHND_BHND_IDS_H_ */ Index: head/sys/dev/bwn/if_bwn_siba_compat.c =================================================================== --- head/sys/dev/bwn/if_bwn_siba_compat.c (revision 328911) +++ head/sys/dev/bwn/if_bwn_siba_compat.c (nonexistent) @@ -1,2577 +0,0 @@ -/*- - * SPDX-License-Identifier: BSD-2-Clause-FreeBSD - * - * Copyright (c) 2016 Landon Fuller - * Copyright (c) 2017 The FreeBSD Foundation - * All rights reserved. - * - * Portions of this software were developed by Landon Fuller - * under sponsorship from the FreeBSD Foundation. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - */ - -#include -__FBSDID("$FreeBSD$"); - -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include - -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include - -#include -#include -#include -#include -#include - -#include -#include - -#include -#include -#include - -#include "gpio_if.h" - -#include "bhnd_nvram_map.h" - -#include "if_bwn_siba_compat.h" - -static int bwn_bhnd_populate_nvram_data(device_t dev, - struct bwn_bhnd_ctx *ctx); -static inline bool bwn_bhnd_is_siba_reg(device_t dev, uint16_t offset); - -#define BWN_ASSERT_VALID_REG(_dev, _offset) \ - KASSERT(!bwn_bhnd_is_siba_reg(_dev, _offset), \ - ("%s: accessing siba-specific register %#jx", __FUNCTION__, \ - (uintmax_t)(_offset))); - -static int -bwn_bhnd_bus_ops_init(device_t dev) -{ - struct bwn_bhnd_ctx *ctx; - struct bwn_softc *sc; - const struct chipc_caps *ccaps; - int error; - - sc = device_get_softc(dev); - ctx = NULL; - - sc->sc_mem_rid = 0; - sc->sc_mem_res = bhnd_alloc_resource_any(dev, SYS_RES_MEMORY, - &sc->sc_mem_rid, RF_ACTIVE); - if (sc->sc_mem_res == NULL) { - return (ENXIO); - } - - /* Allocate PMU state */ - if ((error = bhnd_alloc_pmu(dev))) { - device_printf(dev, "PMU allocation failed: %d\n", error); - goto failed; - } - - /* Allocate our context */ - ctx = malloc(sizeof(struct bwn_bhnd_ctx), M_DEVBUF, M_WAITOK|M_ZERO); - - /* Locate the ChipCommon device */ - ctx->chipc_dev = bhnd_retain_provider(dev, BHND_SERVICE_CHIPC); - if (ctx->chipc_dev == NULL) { - device_printf(dev, "ChipCommon not found\n"); - error = ENXIO; - goto failed; - } - - /* Locate the GPIO device */ - ctx->gpio_dev = bhnd_retain_provider(dev, BHND_SERVICE_GPIO); - if (ctx->gpio_dev == NULL) { - device_printf(dev, "GPIO not found\n"); - error = ENXIO; - goto failed; - } - - /* Locate the PMU device (if any) */ - ccaps = BHND_CHIPC_GET_CAPS(ctx->chipc_dev); - if (ccaps->pmu) { - ctx->pmu_dev = bhnd_retain_provider(dev, BHND_SERVICE_PMU); - if (ctx->pmu_dev == NULL) { - device_printf(dev, "PMU not found\n"); - error = ENXIO; - goto failed; - } - } - - /* Populate NVRAM data */ - if ((error = bwn_bhnd_populate_nvram_data(dev, ctx))) - goto failed; - - /* Initialize bwn_softc */ - sc->sc_bus_ctx = ctx; - return (0); - -failed: - bhnd_release_resource(dev, SYS_RES_MEMORY, sc->sc_mem_rid, - sc->sc_mem_res); - - if (ctx != NULL) { - if (ctx->chipc_dev != NULL) { - bhnd_release_provider(dev, ctx->chipc_dev, - BHND_SERVICE_CHIPC); - } - - if (ctx->gpio_dev != NULL) { - bhnd_release_provider(dev, ctx->gpio_dev, - BHND_SERVICE_GPIO); - } - - if (ctx->pmu_dev != NULL) { - bhnd_release_provider(dev, ctx->pmu_dev, - BHND_SERVICE_PMU); - } - - free(ctx, M_DEVBUF); - } - - return (error); -} - -static void -bwn_bhnd_bus_ops_fini(device_t dev) -{ - struct bwn_bhnd_ctx *ctx; - struct bwn_softc *sc; - - sc = device_get_softc(dev); - ctx = sc->sc_bus_ctx; - - bhnd_release_pmu(dev); - bhnd_release_resource(dev, SYS_RES_MEMORY, sc->sc_mem_rid, - sc->sc_mem_res); - - bhnd_release_provider(dev, ctx->chipc_dev, BHND_SERVICE_CHIPC); - bhnd_release_provider(dev, ctx->gpio_dev, BHND_SERVICE_GPIO); - - if (ctx->pmu_dev != NULL) - bhnd_release_provider(dev, ctx->pmu_dev, BHND_SERVICE_PMU); - - free(ctx, M_DEVBUF); - sc->sc_bus_ctx = NULL; -} - - -/** - * Return true if @p offset is within a siba-specific configuration register - * block. - */ -static inline bool -bwn_bhnd_is_siba_reg(device_t dev, uint16_t offset) -{ - if (offset >= SIBA_CFG0_OFFSET && - offset <= SIBA_CFG0_OFFSET + SIBA_CFG_SIZE) - return (true); - - if (offset >= SIBA_CFG1_OFFSET && - offset <= SIBA_CFG1_OFFSET + SIBA_CFG_SIZE) - return (true); - - return (false); -} - -/* Populate SPROM values from NVRAM */ -static int -bwn_bhnd_populate_nvram_data(device_t dev, struct bwn_bhnd_ctx *ctx) -{ - const char *mac_80211bg_var, *mac_80211a_var; - int error; - - /* Fetch SROM revision */ - error = bhnd_nvram_getvar_uint8(dev, BHND_NVAR_SROMREV, &ctx->sromrev); - if (error) { - device_printf(dev, "error reading %s: %d\n", BHND_NVAR_SROMREV, - error); - return (error); - } - - /* Fetch board flags */ - error = bhnd_nvram_getvar_uint32(dev, BHND_NVAR_BOARDFLAGS, - &ctx->boardflags); - if (error) { - device_printf(dev, "error reading %s: %d\n", - BHND_NVAR_BOARDFLAGS, error); - return (error); - } - - /* Fetch macaddrs if available; bwn(4) expects any missing macaddr - * values to be initialized with 0xFF octets */ - memset(ctx->mac_80211bg, 0xFF, sizeof(ctx->mac_80211bg)); - memset(ctx->mac_80211a, 0xFF, sizeof(ctx->mac_80211a)); - - if (ctx->sromrev <= 2) { - mac_80211bg_var = BHND_NVAR_IL0MACADDR; - mac_80211a_var = BHND_NVAR_ET1MACADDR; - } else { - mac_80211bg_var = BHND_NVAR_MACADDR; - mac_80211a_var = NULL; - } - - /* Fetch required D11 core 0 macaddr */ - error = bhnd_nvram_getvar_array(dev, mac_80211bg_var, ctx->mac_80211bg, - sizeof(ctx->mac_80211bg), BHND_NVRAM_TYPE_UINT8_ARRAY); - if (error) { - device_printf(dev, "error reading %s: %d\n", mac_80211bg_var, - error); - return (error); - } - - /* Fetch optional D11 core 1 macaddr */ - if (mac_80211a_var != NULL) { - error = bhnd_nvram_getvar_array(dev, mac_80211a_var, - ctx->mac_80211a, sizeof(ctx->mac_80211a), - BHND_NVRAM_TYPE_UINT8_ARRAY); - - if (error && error != ENOENT) { - device_printf(dev, "error reading %s: %d\n", - mac_80211a_var, error); - return (error); - } - }; - - /* Fetch pa0maxpwr; bwn(4) expects to be able to modify it */ - if ((ctx->sromrev >= 1 && ctx->sromrev <= 3) || - (ctx->sromrev >= 8 && ctx->sromrev <= 10)) - { - error = bhnd_nvram_getvar_uint8(dev, BHND_NVAR_PA0MAXPWR, - &ctx->pa0maxpwr); - if (error) { - device_printf(dev, "error reading %s: %d\n", - BHND_NVAR_PA0MAXPWR, error); - return (error); - } - } - - return (0); -} - -/* - * Disable PCI-specific MSI interrupt allocation handling - */ - -/* - * pci_find_cap() - * - * Referenced by: - * bwn_attach() - */ -static int -bhnd_compat_pci_find_cap(device_t dev, int capability, int *capreg) -{ - return (ENODEV); -} - -/* - * pci_alloc_msi() - * - * Referenced by: - * bwn_attach() - */ -static int -bhnd_compat_pci_alloc_msi(device_t dev, int *count) -{ - return (ENODEV); -} - -/* - * pci_release_msi() - * - * Referenced by: - * bwn_attach() - * bwn_detach() - */ -static int -bhnd_compat_pci_release_msi(device_t dev) -{ - return (ENODEV); -} - -/* - * pci_msi_count() - * - * Referenced by: - * bwn_attach() - */ -static int -bhnd_compat_pci_msi_count(device_t dev) -{ - return (0); -} - -/* - * siba_get_vendor() - * - * Referenced by: - * bwn_probe() - */ -static uint16_t -bhnd_compat_get_vendor(device_t dev) -{ - uint16_t vendor = bhnd_get_vendor(dev); - - switch (vendor) { - case BHND_MFGID_BCM: - return (SIBA_VID_BROADCOM); - default: - return (0x0000); - } -} - -/* - * siba_get_device() - * - * Referenced by: - * bwn_probe() - */ -static uint16_t -bhnd_compat_get_device(device_t dev) -{ - return (bhnd_get_device(dev)); -} - -/* - * siba_get_revid() - * - * Referenced by: - * bwn_attach() - * bwn_attach_core() - * bwn_chip_init() - * bwn_chiptest() - * bwn_core_init() - * bwn_core_start() - * bwn_pio_idx2base() - * bwn_pio_set_txqueue() - * bwn_pio_tx_start() - * bwn_probe() - * ... and 19 others - * - */ -static uint8_t -bhnd_compat_get_revid(device_t dev) -{ - return (bhnd_get_hwrev(dev)); -} - -/** - * Return the PCI bridge root device. - * - * Will panic if a PCI bridge root device is not found. - */ -static device_t -bwn_bhnd_get_pci_dev(device_t dev) -{ device_t bridge_root; - - bridge_root = bhnd_find_bridge_root(dev, devclass_find("pci")); - if (bridge_root == NULL) - panic("not a PCI device"); - - return (bridge_root); -} - -/* - * siba_get_pci_vendor() - * - * Referenced by: - * bwn_sprom_bugfixes() - */ -static uint16_t -bhnd_compat_get_pci_vendor(device_t dev) -{ - return (pci_get_vendor(bwn_bhnd_get_pci_dev(dev))); -} - -/* - * siba_get_pci_device() - * - * Referenced by: - * bwn_attach() - * bwn_attach_core() - * bwn_nphy_op_prepare_structs() - * bwn_sprom_bugfixes() - */ -static uint16_t -bhnd_compat_get_pci_device(device_t dev) -{ - return (pci_get_device(bwn_bhnd_get_pci_dev(dev))); -} - -/* - * siba_get_pci_subvendor() - * - * Referenced by: - * bwn_led_attach() - * bwn_nphy_op_prepare_structs() - * bwn_phy_g_prepare_hw() - * bwn_phy_hwpctl_init() - * bwn_phy_init_b5() - * bwn_phy_initn() - * bwn_phy_txpower_check() - * bwn_radio_init2055_post() - * bwn_sprom_bugfixes() - * bwn_wa_init() - */ -static uint16_t -bhnd_compat_get_pci_subvendor(device_t dev) -{ - return (pci_get_subvendor(bwn_bhnd_get_pci_dev(dev))); -} - -/* - * siba_get_pci_subdevice() - * - * Referenced by: - * bwn_nphy_workarounds_rev1_2() - * bwn_phy_g_prepare_hw() - * bwn_phy_hwpctl_init() - * bwn_phy_init_b5() - * bwn_phy_initn() - * bwn_phy_lp_bbinit_r01() - * bwn_phy_txpower_check() - * bwn_radio_init2055_post() - * bwn_sprom_bugfixes() - * bwn_wa_init() - */ -static uint16_t -bhnd_compat_get_pci_subdevice(device_t dev) -{ - return (pci_get_subdevice(bwn_bhnd_get_pci_dev(dev))); -} - -/* - * siba_get_pci_revid() - * - * Referenced by: - * bwn_phy_g_prepare_hw() - * bwn_phy_lp_bbinit_r2() - * bwn_sprom_bugfixes() - * bwn_wa_init() - */ -static uint8_t -bhnd_compat_get_pci_revid(device_t dev) -{ - return (pci_get_revid(bwn_bhnd_get_pci_dev(dev))); -} - -/* - * siba_get_chipid() - * - * Referenced by: - * bwn_attach() - * bwn_gpio_init() - * bwn_mac_switch_freq() - * bwn_phy_g_attach() - * bwn_phy_g_init_sub() - * bwn_phy_g_prepare_hw() - * bwn_phy_getinfo() - * bwn_phy_lp_calib() - * bwn_set_opmode() - * bwn_sprom_bugfixes() - * ... and 9 others - * - */ -static uint16_t -bhnd_compat_get_chipid(device_t dev) -{ - return (bhnd_get_chipid(dev)->chip_id); -} - -/* - * siba_get_chiprev() - * - * Referenced by: - * bwn_phy_getinfo() - * bwn_phy_lp_bbinit_r2() - * bwn_phy_lp_tblinit_r2() - * bwn_set_opmode() - */ -static uint16_t -bhnd_compat_get_chiprev(device_t dev) -{ - return (bhnd_get_chipid(dev)->chip_rev); -} - -/* - * siba_get_chippkg() - * - * Referenced by: - * bwn_phy_g_init_sub() - * bwn_phy_lp_bbinit_r01() - * bwn_radio_2056_setup() - */ -static uint8_t -bhnd_compat_get_chippkg(device_t dev) -{ - return (bhnd_get_chipid(dev)->chip_pkg); -} - -/* - * siba_get_type() - * - * Referenced by: - * bwn_core_init() - * bwn_dma_attach() - * bwn_nphy_op_prepare_structs() - * bwn_sprom_bugfixes() - */ -static enum siba_type -bhnd_compat_get_type(device_t dev) -{ - device_t bus, hostb; - bhnd_devclass_t hostb_devclass; - - bus = device_get_parent(dev); - hostb = bhnd_bus_find_hostb_device(bus); - - if (hostb == NULL) - return (SIBA_TYPE_SSB); - - hostb_devclass = bhnd_get_class(hostb); - switch (hostb_devclass) { - case BHND_DEVCLASS_PCCARD: - return (SIBA_TYPE_PCMCIA); - case BHND_DEVCLASS_PCI: - case BHND_DEVCLASS_PCIE: - return (SIBA_TYPE_PCI); - default: - panic("unsupported hostb devclass: %d\n", hostb_devclass); - } -} - -/* - * siba_get_cc_pmufreq() - * - * Referenced by: - * bwn_phy_lp_b2062_init() - * bwn_phy_lp_b2062_switch_channel() - * bwn_phy_lp_b2063_switch_channel() - * bwn_phy_lp_rxcal_r2() - */ -static uint32_t -bhnd_compat_get_cc_pmufreq(device_t dev) -{ - u_int freq; - int error; - - if ((error = bhnd_get_clock_freq(dev, BHND_CLOCK_ALP, &freq))) - panic("failed to fetch clock frequency: %d", error); - - /* TODO: bwn(4) immediately multiplies the result by 1000 (MHz -> Hz) */ - return (freq / 1000); -} - -/* - * siba_get_cc_caps() - * - * Referenced by: - * bwn_phy_lp_b2062_init() - */ -static uint32_t -bhnd_compat_get_cc_caps(device_t dev) -{ - device_t chipc; - const struct chipc_caps *ccaps; - uint32_t result; - - /* Fetch our ChipCommon device */ - chipc = bhnd_retain_provider(dev, BHND_SERVICE_CHIPC); - if (chipc == NULL) - panic("missing ChipCommon device"); - - /* - * The ChipCommon capability flags are only used in one LP-PHY function, - * to assert that a PMU is in fact available. - * - * We can support this by producing a value containing just that flag. - */ - result = 0; - ccaps = BHND_CHIPC_GET_CAPS(chipc); - if (ccaps->pmu) - result |= SIBA_CC_CAPS_PMU; - - bhnd_release_provider(dev, chipc, BHND_SERVICE_CHIPC); - - return (result); -} - -/* - * siba_get_cc_powerdelay() - * - * Referenced by: - * bwn_chip_init() - */ -static uint16_t -bhnd_compat_get_cc_powerdelay(device_t dev) -{ - u_int delay; - int error; - - if ((error = bhnd_get_clock_latency(dev, BHND_CLOCK_HT, &delay))) - panic("failed to fetch clock latency: %d", error); - - if (delay > UINT16_MAX) - panic("%#x would overflow", delay); - - return (delay); -} - -/* - * siba_get_pcicore_revid() - * - * Referenced by: - * bwn_core_init() - */ -static uint8_t -bhnd_compat_get_pcicore_revid(device_t dev) -{ - device_t hostb; - uint8_t nomatch_revid; - - /* - * This is used by bwn(4) in only bwn_core_init(), where a revid <= 10 - * results in the BWN_HF_PCI_SLOWCLOCK_WORKAROUND workaround being - * enabled. - * - * The quirk should only be applied on siba(4) devices using a PCI - * core; we handle around this by returning a bogus value >= 10 here. - * - * TODO: bwn(4) should match this quirk on: - * - BHND_CHIPTYPE_SIBA - * - BHND_COREID_PCI - * - HWREV_LTE(10) - */ - nomatch_revid = 0xFF; - - hostb = bhnd_bus_find_hostb_device(device_get_parent(dev)); - if (hostb == NULL) { - /* Not a bridged device */ - return (nomatch_revid); - } - - if (bhnd_get_device(hostb) != BHND_COREID_PCI) { - /* Not a PCI core */ - return (nomatch_revid); - } - - /* This is a PCI core; we can return the real core revision */ - return (bhnd_get_hwrev(hostb)); -} - -/* - * siba_sprom_get_rev() - * - * Referenced by: - * bwn_nphy_op_prepare_structs() - * bwn_nphy_tx_power_ctl_setup() - * bwn_nphy_tx_power_fix() - * bwn_nphy_workarounds_rev7plus() - */ -static uint8_t -bhnd_compat_sprom_get_rev(device_t dev) -{ - return (bwn_bhnd_get_ctx(dev)->sromrev); -} - -/* - * siba_sprom_get_mac_80211bg() - * - * Referenced by: - * bwn_attach_post() - */ -static uint8_t * -bhnd_compat_sprom_get_mac_80211bg(device_t dev) -{ - /* 'MAC_80211BG' is il0macaddr or macaddr*/ - return (bwn_bhnd_get_ctx(dev)->mac_80211bg); -} - -/* - * siba_sprom_get_mac_80211a() - * - * Referenced by: - * bwn_attach_post() - */ -static uint8_t * -bhnd_compat_sprom_get_mac_80211a(device_t dev) -{ - /* 'MAC_80211A' is et1macaddr */ - return (bwn_bhnd_get_ctx(dev)->mac_80211a); -} - -/* - * siba_sprom_get_brev() - * - * Referenced by: - * bwn_radio_init2055_post() - */ -static uint8_t -bhnd_compat_sprom_get_brev(device_t dev) -{ - /* TODO: bwn(4) needs to switch to uint16_t */ - BWN_BHND_NVRAM_RETURN_VAR(dev, uint8, BHND_NVAR_BOARDREV); -} - -/* - * siba_sprom_get_ccode() - * - * Referenced by: - * bwn_phy_g_switch_chan() - */ -static uint8_t -bhnd_compat_sprom_get_ccode(device_t dev) -{ - /* This has been replaced with 'ccode' in later SPROM - * revisions, but this API is only called on devices with - * spromrev 1. */ - BWN_BHND_NVRAM_RETURN_VAR(dev, uint8, BHND_NVAR_CC); -} - -/* - * siba_sprom_get_ant_a() - * - * Referenced by: - * bwn_antenna_sanitize() - */ -static uint8_t -bhnd_compat_sprom_get_ant_a(device_t dev) -{ - BWN_BHND_NVRAM_RETURN_VAR(dev, uint8, BHND_NVAR_AA5G); -} - -/* - * siba_sprom_get_ant_bg() - * - * Referenced by: - * bwn_antenna_sanitize() - */ -static uint8_t -bhnd_compat_sprom_get_ant_bg(device_t dev) -{ - BWN_BHND_NVRAM_RETURN_VAR(dev, uint8, BHND_NVAR_AA2G); -} - -/* - * siba_sprom_get_pa0b0() - * - * Referenced by: - * bwn_phy_g_attach() - */ -static uint16_t -bhnd_compat_sprom_get_pa0b0(device_t dev) -{ - int16_t value; - - BWN_BHND_NVRAM_FETCH_VAR(dev, int16, BHND_NVAR_PA0B0, &value); - - /* TODO: bwn(4) immediately casts this back to int16_t */ - return ((uint16_t)value); -} - -/* - * siba_sprom_get_pa0b1() - * - * Referenced by: - * bwn_phy_g_attach() - */ -static uint16_t -bhnd_compat_sprom_get_pa0b1(device_t dev) -{ - int16_t value; - - BWN_BHND_NVRAM_FETCH_VAR(dev, int16, BHND_NVAR_PA0B1, &value); - - /* TODO: bwn(4) immediately casts this back to int16_t */ - return ((uint16_t)value); -} - -/* - * siba_sprom_get_pa0b2() - * - * Referenced by: - * bwn_phy_g_attach() - */ -static uint16_t -bhnd_compat_sprom_get_pa0b2(device_t dev) -{ - int16_t value; - - BWN_BHND_NVRAM_FETCH_VAR(dev, int16, BHND_NVAR_PA0B2, &value); - - /* TODO: bwn(4) immediately casts this back to int16_t */ - return ((uint16_t)value); -} - -/** - * Fetch an led behavior (ledbhX) NVRAM variable value, for use by - * siba_sprom_get_gpioX(). - * - * ('gpioX' are actually the ledbhX NVRAM variables). - */ -static uint8_t -bhnd_compat_sprom_get_ledbh(device_t dev, const char *name) -{ - uint8_t value; - int error; - - error = bhnd_nvram_getvar_uint8(dev, name, &value); - if (error && error != ENOENT) - panic("NVRAM variable %s unreadable: %d", name, error); - - /* For some variables (including ledbhX), a value with all bits set is - * treated as uninitialized in the SPROM format; our SPROM parser - * detects this case and returns ENOENT, but bwn(4) actually expects - * to read the raw value 0xFF value. */ - if (error == ENOENT) - value = 0xFF; - - return (value); -} - -/* - * siba_sprom_get_gpio0() - * - * 'gpioX' are actually the led behavior (ledbh) NVRAM variables. - * - * Referenced by: - * bwn_led_attach() - */ -static uint8_t -bhnd_compat_sprom_get_gpio0(device_t dev) -{ - return (bhnd_compat_sprom_get_ledbh(dev, BHND_NVAR_LEDBH0)); -} - -/* - * siba_sprom_get_gpio1() - * - * Referenced by: - * bwn_led_attach() - */ -static uint8_t -bhnd_compat_sprom_get_gpio1(device_t dev) -{ - return (bhnd_compat_sprom_get_ledbh(dev, BHND_NVAR_LEDBH1)); -} - -/* - * siba_sprom_get_gpio2() - * - * Referenced by: - * bwn_led_attach() - */ -static uint8_t -bhnd_compat_sprom_get_gpio2(device_t dev) -{ - return (bhnd_compat_sprom_get_ledbh(dev, BHND_NVAR_LEDBH2)); -} - -/* - * siba_sprom_get_gpio3() - * - * Referenced by: - * bwn_led_attach() - */ -static uint8_t -bhnd_compat_sprom_get_gpio3(device_t dev) -{ - return (bhnd_compat_sprom_get_ledbh(dev, BHND_NVAR_LEDBH3)); -} - -/* - * siba_sprom_get_maxpwr_bg() - * - * Referenced by: - * bwn_phy_g_recalc_txpwr() - */ -static uint16_t -bhnd_compat_sprom_get_maxpwr_bg(device_t dev) -{ - return (bwn_bhnd_get_ctx(dev)->pa0maxpwr); -} - -/* - * siba_sprom_set_maxpwr_bg() - * - * Referenced by: - * bwn_phy_g_recalc_txpwr() - */ -static void -bhnd_compat_sprom_set_maxpwr_bg(device_t dev, uint16_t t) -{ - KASSERT(t <= UINT8_MAX, ("invalid maxpwr value %hu", t)); - bwn_bhnd_get_ctx(dev)->pa0maxpwr = t; -} - -/* - * siba_sprom_get_rxpo2g() - * - * Referenced by: - * bwn_phy_lp_readsprom() - */ -static uint8_t -bhnd_compat_sprom_get_rxpo2g(device_t dev) -{ - /* Should be signed, but bwn(4) expects an unsigned value */ - BWN_BHND_NVRAM_RETURN_VAR(dev, int8, BHND_NVAR_RXPO2G); -} - -/* - * siba_sprom_get_rxpo5g() - * - * Referenced by: - * bwn_phy_lp_readsprom() - */ -static uint8_t -bhnd_compat_sprom_get_rxpo5g(device_t dev) -{ - /* Should be signed, but bwn(4) expects an unsigned value */ - BWN_BHND_NVRAM_RETURN_VAR(dev, int8, BHND_NVAR_RXPO5G); -} - -/* - * siba_sprom_get_tssi_bg() - * - * Referenced by: - * bwn_phy_g_attach() - */ -static uint8_t -bhnd_compat_sprom_get_tssi_bg(device_t dev) -{ - BWN_BHND_NVRAM_RETURN_VAR(dev, uint8, BHND_NVAR_PA0ITSSIT); -} - -/* - * siba_sprom_get_tri2g() - * - * Referenced by: - * bwn_phy_lp_readsprom() - */ -static uint8_t -bhnd_compat_sprom_get_tri2g(device_t dev) -{ - BWN_BHND_NVRAM_RETURN_VAR(dev, uint8, BHND_NVAR_TRI2G); -} - -/* - * siba_sprom_get_tri5gl() - * - * Referenced by: - * bwn_phy_lp_readsprom() - */ -static uint8_t -bhnd_compat_sprom_get_tri5gl(device_t dev) -{ - BWN_BHND_NVRAM_RETURN_VAR(dev, uint8, BHND_NVAR_TRI5GL); -} - -/* - * siba_sprom_get_tri5g() - * - * Referenced by: - * bwn_phy_lp_readsprom() - */ -static uint8_t -bhnd_compat_sprom_get_tri5g(device_t dev) -{ - BWN_BHND_NVRAM_RETURN_VAR(dev, uint8, BHND_NVAR_TRI5G); -} - -/* - * siba_sprom_get_tri5gh() - * - * Referenced by: - * bwn_phy_lp_readsprom() - */ -static uint8_t -bhnd_compat_sprom_get_tri5gh(device_t dev) -{ - BWN_BHND_NVRAM_RETURN_VAR(dev, uint8, BHND_NVAR_TRI5GH); -} - -/* - * siba_sprom_get_rssisav2g() - * - * Referenced by: - * bwn_phy_lp_readsprom() - */ -static uint8_t -bhnd_compat_sprom_get_rssisav2g(device_t dev) -{ - BWN_BHND_NVRAM_RETURN_VAR(dev, uint8, BHND_NVAR_RSSISAV2G); -} - -/* - * siba_sprom_get_rssismc2g() - * - * Referenced by: - * bwn_phy_lp_readsprom() - */ -static uint8_t -bhnd_compat_sprom_get_rssismc2g(device_t dev) -{ - BWN_BHND_NVRAM_RETURN_VAR(dev, uint8, BHND_NVAR_RSSISMC2G); -} - -/* - * siba_sprom_get_rssismf2g() - * - * Referenced by: - * bwn_phy_lp_readsprom() - */ -static uint8_t -bhnd_compat_sprom_get_rssismf2g(device_t dev) -{ - BWN_BHND_NVRAM_RETURN_VAR(dev, uint8, BHND_NVAR_RSSISMF2G); -} - -/* - * siba_sprom_get_bxa2g() - * - * Referenced by: - * bwn_phy_lp_readsprom() - */ -static uint8_t -bhnd_compat_sprom_get_bxa2g(device_t dev) -{ - BWN_BHND_NVRAM_RETURN_VAR(dev, uint8, BHND_NVAR_BXA2G); -} - -/* - * siba_sprom_get_rssisav5g() - * - * Referenced by: - * bwn_phy_lp_readsprom() - */ -static uint8_t -bhnd_compat_sprom_get_rssisav5g(device_t dev) -{ - BWN_BHND_NVRAM_RETURN_VAR(dev, uint8, BHND_NVAR_RSSISAV5G); -} - -/* - * siba_sprom_get_rssismc5g() - * - * Referenced by: - * bwn_phy_lp_readsprom() - */ -static uint8_t -bhnd_compat_sprom_get_rssismc5g(device_t dev) -{ - BWN_BHND_NVRAM_RETURN_VAR(dev, uint8, BHND_NVAR_RSSISMC5G); -} - -/* - * siba_sprom_get_rssismf5g() - * - * Referenced by: - * bwn_phy_lp_readsprom() - */ -static uint8_t -bhnd_compat_sprom_get_rssismf5g(device_t dev) -{ - BWN_BHND_NVRAM_RETURN_VAR(dev, uint8, BHND_NVAR_RSSISMF5G); -} - -/* - * siba_sprom_get_bxa5g() - * - * Referenced by: - * bwn_phy_lp_readsprom() - */ -static uint8_t -bhnd_compat_sprom_get_bxa5g(device_t dev) -{ - BWN_BHND_NVRAM_RETURN_VAR(dev, uint8, BHND_NVAR_BXA5G); -} - -/* - * siba_sprom_get_cck2gpo() - * - * Referenced by: - * bwn_ppr_load_max_from_sprom() - */ -static uint16_t -bhnd_compat_sprom_get_cck2gpo(device_t dev) -{ - BWN_BHND_NVRAM_RETURN_VAR(dev, uint16, BHND_NVAR_CCK2GPO); -} - -/* - * siba_sprom_get_ofdm2gpo() - * - * Referenced by: - * bwn_ppr_load_max_from_sprom() - */ -static uint32_t -bhnd_compat_sprom_get_ofdm2gpo(device_t dev) -{ - BWN_BHND_NVRAM_RETURN_VAR(dev, uint32, BHND_NVAR_OFDM2GPO); -} - -/* - * siba_sprom_get_ofdm5glpo() - * - * Referenced by: - * bwn_ppr_load_max_from_sprom() - */ -static uint32_t -bhnd_compat_sprom_get_ofdm5glpo(device_t dev) -{ - BWN_BHND_NVRAM_RETURN_VAR(dev, uint32, BHND_NVAR_OFDM5GLPO); -} - -/* - * siba_sprom_get_ofdm5gpo() - * - * Referenced by: - * bwn_ppr_load_max_from_sprom() - */ -static uint32_t -bhnd_compat_sprom_get_ofdm5gpo(device_t dev) -{ - BWN_BHND_NVRAM_RETURN_VAR(dev, uint32, BHND_NVAR_OFDM5GPO); -} - -/* - * siba_sprom_get_ofdm5ghpo() - * - * Referenced by: - * bwn_ppr_load_max_from_sprom() - */ -static uint32_t -bhnd_compat_sprom_get_ofdm5ghpo(device_t dev) -{ - BWN_BHND_NVRAM_RETURN_VAR(dev, uint32, BHND_NVAR_OFDM5GHPO); -} - -/* - * siba_sprom_set_bf_lo() - * - * Referenced by: - * bwn_sprom_bugfixes() - */ -static void -bhnd_compat_sprom_set_bf_lo(device_t dev, uint16_t t) -{ - struct bwn_bhnd_ctx *ctx = bwn_bhnd_get_ctx(dev); - ctx->boardflags &= ~0xFFFF; - ctx->boardflags |= t; -} - -/* - * siba_sprom_get_bf_lo() - * - * Referenced by: - * bwn_bt_enable() - * bwn_core_init() - * bwn_gpio_init() - * bwn_loopback_calcgain() - * bwn_phy_g_init_sub() - * bwn_phy_g_recalc_txpwr() - * bwn_phy_g_set_txpwr() - * bwn_phy_g_task_60s() - * bwn_rx_rssi_calc() - * bwn_sprom_bugfixes() - * ... and 11 others - * - */ -static uint16_t -bhnd_compat_sprom_get_bf_lo(device_t dev) -{ - struct bwn_bhnd_ctx *ctx = bwn_bhnd_get_ctx(dev); - return (ctx->boardflags & UINT16_MAX); -} - -/* - * siba_sprom_get_bf_hi() - * - * Referenced by: - * bwn_nphy_gain_ctl_workarounds_rev3() - * bwn_phy_lp_bbinit_r01() - * bwn_phy_lp_tblinit_txgain() - */ -static uint16_t -bhnd_compat_sprom_get_bf_hi(device_t dev) -{ - struct bwn_bhnd_ctx *ctx = bwn_bhnd_get_ctx(dev); - return (ctx->boardflags >> 16); -} - -/* - * siba_sprom_get_bf2_lo() - * - * Referenced by: - * bwn_nphy_op_prepare_structs() - * bwn_nphy_workarounds_rev1_2() - * bwn_nphy_workarounds_rev3plus() - * bwn_phy_initn() - * bwn_radio_2056_setup() - * bwn_radio_init2055_post() - */ -static uint16_t -bhnd_compat_sprom_get_bf2_lo(device_t dev) -{ - uint32_t bf2; - - BWN_BHND_NVRAM_FETCH_VAR(dev, uint32, BHND_NVAR_BOARDFLAGS2, &bf2); - return (bf2 & UINT16_MAX); -} - -/* - * siba_sprom_get_bf2_hi() - * - * Referenced by: - * bwn_nphy_workarounds_rev7plus() - * bwn_phy_initn() - * bwn_radio_2056_setup() - */ -static uint16_t -bhnd_compat_sprom_get_bf2_hi(device_t dev) -{ - uint32_t bf2; - - BWN_BHND_NVRAM_FETCH_VAR(dev, uint32, BHND_NVAR_BOARDFLAGS2, &bf2); - return (bf2 >> 16); -} - -/* - * siba_sprom_get_fem_2ghz_tssipos() - * - * Referenced by: - * bwn_nphy_tx_power_ctl_setup() - */ -static uint8_t -bhnd_compat_sprom_get_fem_2ghz_tssipos(device_t dev) -{ - BWN_BHND_NVRAM_RETURN_VAR(dev, uint8, BHND_NVAR_TSSIPOS2G); -} - -/* - * siba_sprom_get_fem_2ghz_extpa_gain() - * - * Referenced by: - * bwn_nphy_op_prepare_structs() - */ -static uint8_t -bhnd_compat_sprom_get_fem_2ghz_extpa_gain(device_t dev) -{ - BWN_BHND_NVRAM_RETURN_VAR(dev, uint8, BHND_NVAR_EXTPAGAIN2G); -} - -/* - * siba_sprom_get_fem_2ghz_pdet_range() - * - * Referenced by: - * bwn_nphy_workarounds_rev3plus() - */ -static uint8_t -bhnd_compat_sprom_get_fem_2ghz_pdet_range(device_t dev) -{ - BWN_BHND_NVRAM_RETURN_VAR(dev, uint8, BHND_NVAR_PDETRANGE2G); -} - -/* - * siba_sprom_get_fem_2ghz_tr_iso() - * - * Referenced by: - * bwn_nphy_get_gain_ctl_workaround_ent() - */ -static uint8_t -bhnd_compat_sprom_get_fem_2ghz_tr_iso(device_t dev) -{ - BWN_BHND_NVRAM_RETURN_VAR(dev, uint8, BHND_NVAR_TRISO2G); -} - -/* - * siba_sprom_get_fem_2ghz_antswlut() - * - * Referenced by: - * bwn_nphy_tables_init_rev3() - * bwn_nphy_tables_init_rev7_volatile() - */ -static uint8_t -bhnd_compat_sprom_get_fem_2ghz_antswlut(device_t dev) -{ - BWN_BHND_NVRAM_RETURN_VAR(dev, uint8, BHND_NVAR_ANTSWCTL2G); -} - -/* - * siba_sprom_get_fem_5ghz_extpa_gain() - * - * Referenced by: - * bwn_nphy_get_tx_gain_table() - * bwn_nphy_op_prepare_structs() - */ -static uint8_t -bhnd_compat_sprom_get_fem_5ghz_extpa_gain(device_t dev) -{ - BWN_BHND_NVRAM_RETURN_VAR(dev, uint8, BHND_NVAR_EXTPAGAIN5G); -} - -/* - * siba_sprom_get_fem_5ghz_pdet_range() - * - * Referenced by: - * bwn_nphy_workarounds_rev3plus() - */ -static uint8_t -bhnd_compat_sprom_get_fem_5ghz_pdet_range(device_t dev) -{ - BWN_BHND_NVRAM_RETURN_VAR(dev, uint8, BHND_NVAR_PDETRANGE5G); -} - -/* - * siba_sprom_get_fem_5ghz_antswlut() - * - * Referenced by: - * bwn_nphy_tables_init_rev3() - * bwn_nphy_tables_init_rev7_volatile() - */ -static uint8_t -bhnd_compat_sprom_get_fem_5ghz_antswlut(device_t dev) -{ - BWN_BHND_NVRAM_RETURN_VAR(dev, uint8, BHND_NVAR_ANTSWCTL5G); -} - -/* - * siba_sprom_get_txpid_2g_0() - * - * Referenced by: - * bwn_nphy_tx_power_fix() - */ -static uint8_t -bhnd_compat_sprom_get_txpid_2g_0(device_t dev) -{ - BWN_BHND_NVRAM_RETURN_VAR(dev, uint8, BHND_NVAR_TXPID2GA0); -} - -/* - * siba_sprom_get_txpid_2g_1() - * - * Referenced by: - * bwn_nphy_tx_power_fix() - */ -static uint8_t -bhnd_compat_sprom_get_txpid_2g_1(device_t dev) -{ - BWN_BHND_NVRAM_RETURN_VAR(dev, uint8, BHND_NVAR_TXPID2GA1); -} - -/* - * siba_sprom_get_txpid_5gl_0() - * - * Referenced by: - * bwn_nphy_tx_power_fix() - */ -static uint8_t -bhnd_compat_sprom_get_txpid_5gl_0(device_t dev) -{ - BWN_BHND_NVRAM_RETURN_VAR(dev, uint8, BHND_NVAR_TXPID5GLA0); -} - -/* - * siba_sprom_get_txpid_5gl_1() - * - * Referenced by: - * bwn_nphy_tx_power_fix() - */ -static uint8_t -bhnd_compat_sprom_get_txpid_5gl_1(device_t dev) -{ - BWN_BHND_NVRAM_RETURN_VAR(dev, uint8, BHND_NVAR_TXPID5GLA1); -} - -/* - * siba_sprom_get_txpid_5g_0() - * - * Referenced by: - * bwn_nphy_tx_power_fix() - */ -static uint8_t -bhnd_compat_sprom_get_txpid_5g_0(device_t dev) -{ - BWN_BHND_NVRAM_RETURN_VAR(dev, uint8, BHND_NVAR_TXPID5GA0); -} - -/* - * siba_sprom_get_txpid_5g_1() - * - * Referenced by: - * bwn_nphy_tx_power_fix() - */ -static uint8_t -bhnd_compat_sprom_get_txpid_5g_1(device_t dev) -{ - BWN_BHND_NVRAM_RETURN_VAR(dev, uint8, BHND_NVAR_TXPID5GA1); -} - -/* - * siba_sprom_get_txpid_5gh_0() - * - * Referenced by: - * bwn_nphy_tx_power_fix() - */ -static uint8_t -bhnd_compat_sprom_get_txpid_5gh_0(device_t dev) -{ - BWN_BHND_NVRAM_RETURN_VAR(dev, uint8, BHND_NVAR_TXPID5GHA0); -} - -/* - * siba_sprom_get_txpid_5gh_1() - * - * Referenced by: - * bwn_nphy_tx_power_fix() - */ -static uint8_t -bhnd_compat_sprom_get_txpid_5gh_1(device_t dev) -{ - BWN_BHND_NVRAM_RETURN_VAR(dev, uint8, BHND_NVAR_TXPID5GHA1); -} - -/* - * siba_sprom_get_stbcpo() - * - * Referenced by: - * bwn_ppr_load_max_from_sprom() - */ -static uint16_t -bhnd_compat_sprom_get_stbcpo(device_t dev) -{ - BWN_BHND_NVRAM_RETURN_VAR(dev, uint16, BHND_NVAR_STBCPO); -} - -/* - * siba_sprom_get_cddpo() - * - * Referenced by: - * bwn_ppr_load_max_from_sprom() - */ -static uint16_t -bhnd_compat_sprom_get_cddpo(device_t dev) -{ - BWN_BHND_NVRAM_RETURN_VAR(dev, uint16, BHND_NVAR_CDDPO); -} - -/* - * siba_powerup() - * - * Referenced by: - * bwn_attach_core() - * bwn_core_init() - */ -static void -bhnd_compat_powerup(device_t dev, int dynamic) -{ - struct bwn_bhnd_ctx *ctx; - bhnd_clock clock; - int error; - - ctx = bwn_bhnd_get_ctx(dev); - - /* On PMU equipped devices, we do not need to issue a clock request - * at powerup */ - if (ctx->pmu_dev != NULL) - return; - - /* Issue a PMU clock request */ - if (dynamic) - clock = BHND_CLOCK_DYN; - else - clock = BHND_CLOCK_HT; - - if ((error = bhnd_request_clock(dev, clock))) { - device_printf(dev, "%d clock request failed: %d\n", - clock, error); - } - -} - -/* - * siba_powerdown() - * - * Referenced by: - * bwn_attach_core() - * bwn_core_exit() - * bwn_core_init() - */ -static int -bhnd_compat_powerdown(device_t dev) -{ - int error; - - /* Suspend the core */ - if ((error = bhnd_suspend_hw(dev, 0))) - return (error); - - return (0); -} - -/* - * siba_read_2() - * - * Referenced by: - * bwn_chip_init() - * bwn_chiptest() - * bwn_dummy_transmission() - * bwn_gpio_init() - * bwn_phy_getinfo() - * bwn_pio_read_2() - * bwn_shm_read_2() - * bwn_shm_read_4() - * bwn_wme_init() - * bwn_wme_loadparams() - * ... and 23 others - * - */ -static uint16_t -bhnd_compat_read_2(device_t dev, uint16_t offset) -{ - struct bwn_softc *sc = device_get_softc(dev); - - BWN_ASSERT_VALID_REG(dev, offset); - - return (bhnd_bus_read_2(sc->sc_mem_res, offset)); -} - -/* - * siba_write_2() - * - * Referenced by: - * bwn_chip_init() - * bwn_chiptest() - * bwn_crypt_init() - * bwn_gpio_init() - * bwn_phy_getinfo() - * bwn_pio_tx_start() - * bwn_set_opmode() - * bwn_shm_write_2() - * bwn_shm_write_4() - * bwn_wme_init() - * ... and 43 others - * - */ -static void -bhnd_compat_write_2(device_t dev, uint16_t offset, uint16_t value) -{ - struct bwn_softc *sc = device_get_softc(dev); - - BWN_ASSERT_VALID_REG(dev, offset); - - return (bhnd_bus_write_2(sc->sc_mem_res, offset, value)); -} - -/* - * siba_read_4() - * - * Referenced by: - * bwn_attach_core() - * bwn_chip_init() - * bwn_chiptest() - * bwn_core_exit() - * bwn_core_init() - * bwn_core_start() - * bwn_pio_init() - * bwn_pio_tx_start() - * bwn_reset_core() - * bwn_shm_read_4() - * ... and 42 others - * - */ -static uint32_t -bhnd_compat_read_4(device_t dev, uint16_t offset) -{ - struct bwn_softc *sc = device_get_softc(dev); - uint16_t ioreg; - int error; - - /* bwn(4) fetches IOCTL/IOST values directly from siba-specific target - * state registers; we map these directly to bhnd_read_(ioctl|iost) */ - switch (offset) { - case SB0_REG_ABS(SIBA_CFG0_TMSTATELOW): - if ((error = bhnd_read_ioctl(dev, &ioreg))) - panic("error reading IOCTL: %d\n", error); - - return (((uint32_t)ioreg) << SIBA_TML_SICF_SHIFT); - - case SB0_REG_ABS(SIBA_CFG0_TMSTATEHIGH): - if ((error = bhnd_read_iost(dev, &ioreg))) - panic("error reading IOST: %d\n", error); - - return (((uint32_t)ioreg) << SIBA_TMH_SISF_SHIFT); - } - - /* Otherwise, perform a standard bus read */ - BWN_ASSERT_VALID_REG(dev, offset); - return (bhnd_bus_read_4(sc->sc_mem_res, offset)); -} - -/* - * siba_write_4() - * - * Referenced by: - * bwn_chip_init() - * bwn_chiptest() - * bwn_core_exit() - * bwn_core_start() - * bwn_dma_mask() - * bwn_dma_rxdirectfifo() - * bwn_pio_init() - * bwn_reset_core() - * bwn_shm_ctlword() - * bwn_shm_write_4() - * ... and 37 others - * - */ -static void -bhnd_compat_write_4(device_t dev, uint16_t offset, uint32_t value) -{ - struct bwn_softc *sc = device_get_softc(dev); - uint16_t ioctl; - int error; - - /* bwn(4) writes IOCTL values directly to siba-specific target state - * registers; we map these directly to bhnd_write_ioctl() */ - if (offset == SB0_REG_ABS(SIBA_CFG0_TMSTATELOW)) { - /* shift IOCTL flags back down to their original values */ - if (value & ~SIBA_TML_SICF_MASK) - panic("%s: non-IOCTL flags provided", __FUNCTION__); - - ioctl = (value & SIBA_TML_SICF_MASK) >> SIBA_TML_SICF_SHIFT; - - if ((error = bhnd_write_ioctl(dev, ioctl, UINT16_MAX))) - panic("error writing IOCTL: %d\n", error); - } else { - /* Otherwise, perform a standard bus write */ - BWN_ASSERT_VALID_REG(dev, offset); - - bhnd_bus_write_4(sc->sc_mem_res, offset, value); - } - - return; -} - -/* - * siba_dev_up() - * - * Referenced by: - * bwn_reset_core() - */ -static void -bhnd_compat_dev_up(device_t dev, uint32_t flags) -{ - uint16_t ioctl; - int error; - - /* shift IOCTL flags back down to their original values */ - if (flags & ~SIBA_TML_SICF_MASK) - panic("%s: non-IOCTL flags provided", __FUNCTION__); - - ioctl = (flags & SIBA_TML_SICF_MASK) >> SIBA_TML_SICF_SHIFT; - - /* Perform core reset; note that bwn(4) incorrectly assumes that both - * RESET and post-RESET ioctl flags should be identical */ - if ((error = bhnd_reset_hw(dev, ioctl, ioctl))) - panic("%s: core reset failed: %d", __FUNCTION__, error); -} - -/* - * siba_dev_down() - * - * Referenced by: - * bwn_attach_core() - * bwn_core_exit() - */ -static void -bhnd_compat_dev_down(device_t dev, uint32_t flags) -{ - uint16_t ioctl; - int error; - - /* shift IOCTL flags back down to their original values */ - if (flags & ~SIBA_TML_SICF_MASK) - panic("%s: non-IOCTL flags provided", __FUNCTION__); - - ioctl = (flags & SIBA_TML_SICF_MASK) >> SIBA_TML_SICF_SHIFT; - - /* Put core into RESET state */ - if ((error = bhnd_suspend_hw(dev, ioctl))) - panic("%s: core suspend failed: %d", __FUNCTION__, error); -} - -/* - * siba_dev_isup() - * - * Referenced by: - * bwn_core_init() - */ -static int -bhnd_compat_dev_isup(device_t dev) -{ - return (!bhnd_is_hw_suspended(dev)); -} - -/* - * siba_pcicore_intr() - * - * Referenced by: - * bwn_core_init() - */ -static void -bhnd_compat_pcicore_intr(device_t dev) -{ - /* This is handled by bhnd_bhndb on the first call to - * bus_setup_intr() */ -} - -/* - * siba_dma_translation() - * - * Referenced by: - * bwn_dma_32_setdesc() - * bwn_dma_64_setdesc() - * bwn_dma_setup() - */ -static uint32_t -bhnd_compat_dma_translation(device_t dev) -{ - struct bhnd_dma_translation dt; - struct bwn_softc *sc; - struct bwn_mac *mac; - u_int width; - int error; - - sc = device_get_softc(dev); - mac = sc->sc_curmac; - KASSERT(mac != NULL, ("no MAC")); - - /* - * Use the DMA engine's maximum host address width to determine the - * supported device address width. - */ - switch (mac->mac_method.dma.dmatype) { - case BWN_DMA_32BIT: - case BWN_DMA_30BIT: - /* The 32-bit engine is always capable of addressing - * a full 32-bit device address */ - width = BHND_DMA_ADDR_32BIT; - break; - - case BWN_DMA_64BIT: - width = BHND_DMA_ADDR_64BIT; - break; - - default: - panic("unknown dma type %d", - mac->mac_method.dma.dmatype); - } - - - /* Fetch our DMA translation */ - if ((error = bhnd_get_dma_translation(dev, width, 0, NULL, &dt))) - panic("error requesting DMA translation: %d\n", error); - - /* - * TODO: bwn(4) needs to switch to bhnd_get_dma_translation(). - * - * Currently, bwn(4) incorrectly assumes that: - * - The 32-bit translation mask is always SIBA_DMA_TRANSLATION_MASK. - * - The 32-bit mask can simply be applied to the top 32-bits of a - * 64-bit DMA address. - * - The 64-bit address translation is always derived by shifting the - * 32-bit siba_dma_translation() left by 1 bit. - * - * In practice, these assumptions won't result in any bugs on known - * PCI/PCIe Wi-Fi hardware: - * - The 32-bit mask _is_ always SIBA_DMA_TRANSLATION_MASK on - * the subset of devices supported by bwn(4). - * - The 64-bit mask used by bwn(4) is a superset of the real - * mask, and thus: - * - Our DMA tag will still have valid constraints. - * - Our address translation will not be corrupted by - * applying the mask. - * - The mask falls within the top 16 address bits, and our - * supported 64-bit architectures are all still limited - * to 48-bit addresses anyway; we don't need to worry about - * addressing >= 48-bit host memory. - * - * However, we will need to resolve these issues in bwn(4) if DMA is to - * work on new hardware (e.g. WiSoCs). - */ - switch (width) { - case BHND_DMA_ADDR_32BIT: - KASSERT((~dt.addr_mask & BHND_DMA_ADDR_BITMASK(32)) == - SIBA_DMA_TRANSLATION_MASK, ("unexpected DMA mask: %#jx", - (uintmax_t)dt.addr_mask)); - - return (dt.base_addr); - - case BHND_DMA_ADDR_64BIT: - /* bwn(4) will shift this left by 32+1 bits before applying it - * to the top 32-bits of the DMA address */ - KASSERT((~dt.addr_mask & BHND_DMA_ADDR_BITMASK(33)) == 0, - ("DMA64 translation %#jx masks low 33-bits", - (uintmax_t)dt.addr_mask)); - - return (dt.base_addr >> 33); - - default: - panic("unsupported address width: %u", width); - } -} - -/* - * siba_read_multi_2() - * - * Referenced by: - * bwn_pio_rxeof() - */ -static void -bhnd_compat_read_multi_2(device_t dev, void *buffer, size_t count, - uint16_t offset) -{ - struct bwn_softc *sc = device_get_softc(dev); - - BWN_ASSERT_VALID_REG(dev, offset); - return (bhnd_bus_read_multi_2(sc->sc_mem_res, offset, buffer, count)); -} - -/* - * siba_read_multi_4() - * - * Referenced by: - * bwn_pio_rxeof() - */ -static void -bhnd_compat_read_multi_4(device_t dev, void *buffer, size_t count, - uint16_t offset) -{ - struct bwn_softc *sc = device_get_softc(dev); - - BWN_ASSERT_VALID_REG(dev, offset); - return (bhnd_bus_read_multi_4(sc->sc_mem_res, offset, buffer, count)); -} - -/* - * siba_write_multi_2() - * - * Referenced by: - * bwn_pio_write_multi_2() - */ -static void -bhnd_compat_write_multi_2(device_t dev, const void *buffer, size_t count, - uint16_t offset) -{ - struct bwn_softc *sc = device_get_softc(dev); - - BWN_ASSERT_VALID_REG(dev, offset); - - /* XXX discarding const to maintain API compatibility with - * siba_write_multi_2() */ - bhnd_bus_write_multi_2(sc->sc_mem_res, offset, - __DECONST(void *, buffer), count); -} - -/* - * siba_write_multi_4() - * - * Referenced by: - * bwn_pio_write_multi_4() - */ -static void -bhnd_compat_write_multi_4(device_t dev, const void *buffer, size_t count, - uint16_t offset) -{ - struct bwn_softc *sc = device_get_softc(dev); - - BWN_ASSERT_VALID_REG(dev, offset); - - /* XXX discarding const to maintain API compatibility with - * siba_write_multi_4() */ - bhnd_bus_write_multi_4(sc->sc_mem_res, offset, - __DECONST(void *, buffer), count); -} - -/* - * siba_barrier() - * - * Referenced by: - * bwn_intr() - * bwn_intrtask() - * bwn_ram_write() - */ -static void -bhnd_compat_barrier(device_t dev, int flags) -{ - struct bwn_softc *sc = device_get_softc(dev); - - /* XXX is siba_barrier()'s use of an offset and length of 0 - * correct? */ - BWN_ASSERT_VALID_REG(dev, 0); - bhnd_bus_barrier(sc->sc_mem_res, 0, 0, flags); -} - -/* - * siba_cc_pmu_set_ldovolt() - * - * Referenced by: - * bwn_phy_lp_bbinit_r01() - */ -static void -bhnd_compat_cc_pmu_set_ldovolt(device_t dev, int id, uint32_t volt) -{ - struct bwn_bhnd_ctx *ctx; - int error; - - ctx = bwn_bhnd_get_ctx(dev); - - /* Only ever used to set the PAREF LDO voltage */ - if (id != SIBA_LDO_PAREF) - panic("invalid LDO id: %d", id); - - /* Configuring regulator voltage requires a PMU */ - if (ctx->pmu_dev == NULL) - panic("no PMU; cannot set LDO voltage"); - - error = bhnd_pmu_set_voltage_raw(ctx->pmu_dev, BHND_REGULATOR_PAREF_LDO, - volt); - if (error) - panic("failed to set LDO voltage: %d", error); -} - -/* - * siba_cc_pmu_set_ldoparef() - * - * Referenced by: - * bwn_phy_lp_bbinit_r01() - */ -static void -bhnd_compat_cc_pmu_set_ldoparef(device_t dev, uint8_t on) -{ - struct bwn_bhnd_ctx *ctx; - int error; - - ctx = bwn_bhnd_get_ctx(dev); - - /* Enabling/disabling regulators requires a PMU */ - if (ctx->pmu_dev == NULL) - panic("no PMU; cannot set LDO voltage"); - - if (on) { - error = bhnd_pmu_enable_regulator(ctx->pmu_dev, - BHND_REGULATOR_PAREF_LDO); - } else { - error = bhnd_pmu_disable_regulator(ctx->pmu_dev, - BHND_REGULATOR_PAREF_LDO); - } - - if (error) { - panic("failed to %s PAREF_LDO: %d", on ? "enable" : "disable", - error); - } -} - -/* - * siba_gpio_set() - * - * Referenced by: - * bwn_chip_exit() - * bwn_chip_init() - * bwn_gpio_init() - * bwn_nphy_superswitch_init() - */ -static void -bhnd_compat_gpio_set(device_t dev, uint32_t value) -{ - struct bwn_bhnd_ctx *ctx; - uint32_t flags[32]; - int error; - - ctx = bwn_bhnd_get_ctx(dev); - - for (size_t i = 0; i < nitems(flags); i++) { - if (value & (1 << i)) { - /* Tristate pin */ - flags[i] = (GPIO_PIN_OUTPUT | GPIO_PIN_TRISTATE); - } else { - /* Leave unmodified */ - flags[i] = 0; - } - } - - error = GPIO_PIN_CONFIG_32(ctx->gpio_dev, 0, nitems(flags), flags); - if (error) - panic("error configuring pin flags: %d", error); -} - -/* - * siba_gpio_get() - * - * Referenced by: - * bwn_gpio_init() - */ -static uint32_t -bhnd_compat_gpio_get(device_t dev) -{ - struct bwn_bhnd_ctx *ctx; - uint32_t ctrl; - int npin; - int error; - - /* - * We recreate the expected GPIOCTRL register value for bwn_gpio_init() - * by querying pins individually for GPIO_PIN_TRISTATE. - * - * Once we drop these compatibility shims, the GPIO_PIN_CONFIG_32 method - * can be used to set pin configuration without bwn(4) externally - * implementing RMW. - */ - - /* Fetch the total pin count */ - ctx = bwn_bhnd_get_ctx(dev); - if ((error = GPIO_PIN_MAX(ctx->gpio_dev, &npin))) - panic("failed to fetch max pin: %d", error); - - /* Must be representable within a 32-bit GPIOCTRL register value */ - KASSERT(npin <= 32, ("unsupported pin count: %u", npin)); - - ctrl = 0; - for (uint32_t pin = 0; pin < npin; pin++) { - uint32_t flags; - - if ((error = GPIO_PIN_GETFLAGS(ctx->gpio_dev, pin, &flags))) - panic("error fetching pin%u flags: %d", pin, error); - - if (flags & GPIO_PIN_TRISTATE) - ctrl |= (1 << pin); - } - - return (ctrl); -} - -/* - * siba_fix_imcfglobug() - * - * Referenced by: - * bwn_core_init() - */ -static void -bhnd_compat_fix_imcfglobug(device_t dev) -{ - /* This is handled by siba_bhndb during attach/resume */ -} - - -/* Core power NVRAM variables, indexed by D11 core unit number */ -static const struct bwn_power_vars { - const char *itt2ga; - const char *itt5ga; - const char *maxp2ga; - const char *pa2ga; - const char *pa5ga; -} bwn_power_vars[BWN_BHND_NUM_CORE_PWR] = { -#define BHND_POWER_NVAR(_idx) \ - { BHND_NVAR_ITT2GA ## _idx, BHND_NVAR_ITT5GA ## _idx, \ - BHND_NVAR_MAXP2GA ## _idx, BHND_NVAR_PA2GA ## _idx, \ - BHND_NVAR_PA5GA ## _idx } - BHND_POWER_NVAR(0), - BHND_POWER_NVAR(1), - BHND_POWER_NVAR(2), - BHND_POWER_NVAR(3) -#undef BHND_POWER_NVAR -}; - -static int -bwn_get_core_power_info_r11(device_t dev, const struct bwn_power_vars *v, - struct siba_sprom_core_pwr_info *c) -{ - int16_t pa5ga[12]; - int error; - - /* BHND_NVAR_PA2GA[core] */ - error = bhnd_nvram_getvar_array(dev, v->pa2ga, c->pa_2g, - sizeof(c->pa_2g), BHND_NVRAM_TYPE_INT16); - if (error) - return (error); - - /* - * BHND_NVAR_PA5GA - * - * The NVRAM variable is defined as a single pa5ga[12] array; we have - * to split this into pa_5gl[4], pa_5g[4], and pa_5gh[4] for use - * by bwn(4); - */ - _Static_assert(nitems(pa5ga) == nitems(c->pa_5g) + nitems(c->pa_5gh) + - nitems(c->pa_5gl), "cannot split pa5ga into pa_5gl/pa_5g/pa_5gh"); - - error = bhnd_nvram_getvar_array(dev, v->pa5ga, pa5ga, sizeof(pa5ga), - BHND_NVRAM_TYPE_INT16); - if (error) - return (error); - - memcpy(c->pa_5gl, &pa5ga[0], sizeof(c->pa_5gl)); - memcpy(c->pa_5g, &pa5ga[4], sizeof(c->pa_5g)); - memcpy(c->pa_5gh, &pa5ga[8], sizeof(c->pa_5gh)); - return (0); -} - -static int -bwn_get_core_power_info_r4_r10(device_t dev, - const struct bwn_power_vars *v, struct siba_sprom_core_pwr_info *c) -{ - int error; - - /* BHND_NVAR_ITT2GA[core] */ - if ((error = bhnd_nvram_getvar_uint8(dev, v->itt2ga, &c->itssi_2g))) - return (error); - - /* BHND_NVAR_ITT5GA[core] */ - if ((error = bhnd_nvram_getvar_uint8(dev, v->itt5ga, &c->itssi_5g))) - return (error); - - return (0); -} - -/* - * siba_sprom_get_core_power_info() - * - * Referenced by: - * bwn_nphy_tx_power_ctl_setup() - * bwn_ppr_load_max_from_sprom() - */ -static int -bhnd_compat_sprom_get_core_power_info(device_t dev, int core, - struct siba_sprom_core_pwr_info *c) -{ - struct bwn_bhnd_ctx *ctx; - const struct bwn_power_vars *v; - int error; - - if (core < 0 || core >= nitems(bwn_power_vars)) - return (EINVAL); - - ctx = bwn_bhnd_get_ctx(dev); - if (ctx->sromrev < 4) - return (ENXIO); - - v = &bwn_power_vars[core]; - - /* Any power variables not found in NVRAM (or returning a - * shorter array for a particular NVRAM revision) should be zero - * initialized */ - memset(c, 0x0, sizeof(*c)); - - /* Populate SPROM revision-independent values */ - if ((error = bhnd_nvram_getvar_uint8(dev, v->maxp2ga, &c->maxpwr_2g))) - return (error); - - /* Populate SPROM revision-specific values */ - if (ctx->sromrev >= 4 && ctx->sromrev <= 10) - return (bwn_get_core_power_info_r4_r10(dev, v, c)); - else - return (bwn_get_core_power_info_r11(dev, v, c)); -} - -/* - * siba_sprom_get_mcs2gpo() - * - * Referenced by: - * bwn_ppr_load_max_from_sprom() - */ -static int -bhnd_compat_sprom_get_mcs2gpo(device_t dev, uint16_t *c) -{ - static const char *varnames[] = { - BHND_NVAR_MCS2GPO0, - BHND_NVAR_MCS2GPO1, - BHND_NVAR_MCS2GPO2, - BHND_NVAR_MCS2GPO3, - BHND_NVAR_MCS2GPO4, - BHND_NVAR_MCS2GPO5, - BHND_NVAR_MCS2GPO6, - BHND_NVAR_MCS2GPO7 - }; - - for (size_t i = 0; i < nitems(varnames); i++) { - const char *name = varnames[i]; - BWN_BHND_NVRAM_FETCH_VAR(dev, uint16, name, &c[i]); - } - - return (0); -} - -/* - * siba_sprom_get_mcs5glpo() - * - * Referenced by: - * bwn_ppr_load_max_from_sprom() - */ -static int -bhnd_compat_sprom_get_mcs5glpo(device_t dev, uint16_t *c) -{ - static const char *varnames[] = { - BHND_NVAR_MCS5GLPO0, - BHND_NVAR_MCS5GLPO1, - BHND_NVAR_MCS5GLPO2, - BHND_NVAR_MCS5GLPO3, - BHND_NVAR_MCS5GLPO4, - BHND_NVAR_MCS5GLPO5, - BHND_NVAR_MCS5GLPO6, - BHND_NVAR_MCS5GLPO7 - }; - - for (size_t i = 0; i < nitems(varnames); i++) { - const char *name = varnames[i]; - BWN_BHND_NVRAM_FETCH_VAR(dev, uint16, name, &c[i]); - } - - return (0); -} - -/* - * siba_sprom_get_mcs5gpo() - * - * Referenced by: - * bwn_ppr_load_max_from_sprom() - */ -static int -bhnd_compat_sprom_get_mcs5gpo(device_t dev, uint16_t *c) -{ - static const char *varnames[] = { - BHND_NVAR_MCS5GPO0, - BHND_NVAR_MCS5GPO1, - BHND_NVAR_MCS5GPO2, - BHND_NVAR_MCS5GPO3, - BHND_NVAR_MCS5GPO4, - BHND_NVAR_MCS5GPO5, - BHND_NVAR_MCS5GPO6, - BHND_NVAR_MCS5GPO7 - }; - - for (size_t i = 0; i < nitems(varnames); i++) { - const char *name = varnames[i]; - BWN_BHND_NVRAM_FETCH_VAR(dev, uint16, name, &c[i]); - } - - return (0); -} - -/* - * siba_sprom_get_mcs5ghpo() - * - * Referenced by: - * bwn_ppr_load_max_from_sprom() - */ -static int -bhnd_compat_sprom_get_mcs5ghpo(device_t dev, uint16_t *c) -{ - static const char *varnames[] = { - BHND_NVAR_MCS5GHPO0, - BHND_NVAR_MCS5GHPO1, - BHND_NVAR_MCS5GHPO2, - BHND_NVAR_MCS5GHPO3, - BHND_NVAR_MCS5GHPO4, - BHND_NVAR_MCS5GHPO5, - BHND_NVAR_MCS5GHPO6, - BHND_NVAR_MCS5GHPO7 - }; - - for (size_t i = 0; i < nitems(varnames); i++) { - const char *name = varnames[i]; - BWN_BHND_NVRAM_FETCH_VAR(dev, uint16, name, &c[i]); - } - - return (0); -} - -/* - * siba_pmu_spuravoid_pllupdate() - * - * Referenced by: - * bwn_nphy_pmu_spur_avoid() - */ -static void -bhnd_compat_pmu_spuravoid_pllupdate(device_t dev, int spur_avoid) -{ - struct bwn_bhnd_ctx *ctx; - bhnd_pmu_spuravoid mode; - int error; - - ctx = bwn_bhnd_get_ctx(dev); - - if (ctx->pmu_dev == NULL) - panic("requested spuravoid on non-PMU device"); - - switch (spur_avoid) { - case 0: - mode = BHND_PMU_SPURAVOID_NONE; - break; - case 1: - mode = BHND_PMU_SPURAVOID_M1; - break; - default: - panic("unknown spur_avoid: %d", spur_avoid); - } - - if ((error = bhnd_pmu_request_spuravoid(ctx->pmu_dev, mode))) - panic("spuravoid request failed: %d", error); -} - -/* - * siba_cc_set32() - * - * Referenced by: - * bwn_phy_initn() - * bwn_wireless_core_phy_pll_reset() - */ -static void -bhnd_compat_cc_set32(device_t dev, uint32_t reg, uint32_t val) -{ - struct bwn_bhnd_ctx *ctx = bwn_bhnd_get_ctx(dev); - - /* - * OR with the current value. - * - * This function is only ever used to write to either ChipCommon's - * chipctrl register or chipctl_data register. Note that chipctl_data - * is actually a PMU register; it is not actually mapped by ChipCommon - * on Always-on-Bus (AOB) devices with a standalone PMU core. - */ - if (dev != ctx->chipc_dev) - panic("unsupported device: %s", device_get_nameunit(dev)); - - switch (reg) { - case SIBA_CC_CHIPCTL: - BHND_CHIPC_WRITE_CHIPCTRL(ctx->chipc_dev, val, val); - break; - case SIBA_CC_CHIPCTL_DATA: - bhnd_pmu_write_chipctrl(ctx->pmu_dev, ctx->pmu_cctl_addr, val, - val); - break; - default: - panic("unsupported register: %#x", reg); - } -} - -/* - * siba_cc_mask32() - * - * Referenced by: - * bwn_wireless_core_phy_pll_reset() - */ -static void -bhnd_compat_cc_mask32(device_t dev, uint32_t reg, uint32_t mask) -{ - struct bwn_bhnd_ctx *ctx = bwn_bhnd_get_ctx(dev); - - /* - * AND with the current value. - * - * This function is only ever used to write to ChipCommon's chipctl_data - * register. Note that chipctl_data is actually a PMU register; it is - * not actually mapped by ChipCommon on Always-on-Bus (AOB) devices with - * a standalone PMU core. - */ - if (dev != ctx->chipc_dev) - panic("unsupported device: %s", device_get_nameunit(dev)); - - switch (reg) { - case SIBA_CC_CHIPCTL_DATA: - bhnd_pmu_write_chipctrl(ctx->pmu_dev, ctx->pmu_cctl_addr, 0, - ~mask); - break; - default: - panic("unsupported register: %#x", reg); - } -} - -/* - * siba_cc_write32() - * - * Referenced by: - * bwn_wireless_core_phy_pll_reset() - */ -static void -bhnd_compat_cc_write32(device_t dev, uint32_t reg, uint32_t val) -{ - struct bwn_bhnd_ctx *ctx = bwn_bhnd_get_ctx(dev); - - /* - * This function is only ever used to write to ChipCommon's chipctl_addr - * register; setting chipctl_addr is handled atomically by - * bhnd_pmu_write_chipctrl(), so we merely cache the intended address - * for later use when chipctl_data is written. - * - * Also, note that chipctl_addr is actually a PMU register; it is - * not actually mapped by ChipCommon on Always-on-Bus (AOB) devices with - * a standalone PMU core. - */ - if (dev != ctx->chipc_dev) - panic("unsupported device: %s", device_get_nameunit(dev)); - - switch (reg) { - case SIBA_CC_CHIPCTL_ADDR: - ctx->pmu_cctl_addr = val; - break; - default: - panic("unsupported register: %#x", reg); - } -} - -const struct bwn_bus_ops bwn_bhnd_bus_ops = { - .init = bwn_bhnd_bus_ops_init, - .fini = bwn_bhnd_bus_ops_fini, - .pci_find_cap = bhnd_compat_pci_find_cap, - .pci_alloc_msi = bhnd_compat_pci_alloc_msi, - .pci_release_msi = bhnd_compat_pci_release_msi, - .pci_msi_count = bhnd_compat_pci_msi_count, - .get_vendor = bhnd_compat_get_vendor, - .get_device = bhnd_compat_get_device, - .get_revid = bhnd_compat_get_revid, - .get_pci_vendor = bhnd_compat_get_pci_vendor, - .get_pci_device = bhnd_compat_get_pci_device, - .get_pci_subvendor = bhnd_compat_get_pci_subvendor, - .get_pci_subdevice = bhnd_compat_get_pci_subdevice, - .get_pci_revid = bhnd_compat_get_pci_revid, - .get_chipid = bhnd_compat_get_chipid, - .get_chiprev = bhnd_compat_get_chiprev, - .get_chippkg = bhnd_compat_get_chippkg, - .get_type = bhnd_compat_get_type, - .get_cc_pmufreq = bhnd_compat_get_cc_pmufreq, - .get_cc_caps = bhnd_compat_get_cc_caps, - .get_cc_powerdelay = bhnd_compat_get_cc_powerdelay, - .get_pcicore_revid = bhnd_compat_get_pcicore_revid, - .sprom_get_rev = bhnd_compat_sprom_get_rev, - .sprom_get_mac_80211bg = bhnd_compat_sprom_get_mac_80211bg, - .sprom_get_mac_80211a = bhnd_compat_sprom_get_mac_80211a, - .sprom_get_brev = bhnd_compat_sprom_get_brev, - .sprom_get_ccode = bhnd_compat_sprom_get_ccode, - .sprom_get_ant_a = bhnd_compat_sprom_get_ant_a, - .sprom_get_ant_bg = bhnd_compat_sprom_get_ant_bg, - .sprom_get_pa0b0 = bhnd_compat_sprom_get_pa0b0, - .sprom_get_pa0b1 = bhnd_compat_sprom_get_pa0b1, - .sprom_get_pa0b2 = bhnd_compat_sprom_get_pa0b2, - .sprom_get_gpio0 = bhnd_compat_sprom_get_gpio0, - .sprom_get_gpio1 = bhnd_compat_sprom_get_gpio1, - .sprom_get_gpio2 = bhnd_compat_sprom_get_gpio2, - .sprom_get_gpio3 = bhnd_compat_sprom_get_gpio3, - .sprom_get_maxpwr_bg = bhnd_compat_sprom_get_maxpwr_bg, - .sprom_set_maxpwr_bg = bhnd_compat_sprom_set_maxpwr_bg, - .sprom_get_rxpo2g = bhnd_compat_sprom_get_rxpo2g, - .sprom_get_rxpo5g = bhnd_compat_sprom_get_rxpo5g, - .sprom_get_tssi_bg = bhnd_compat_sprom_get_tssi_bg, - .sprom_get_tri2g = bhnd_compat_sprom_get_tri2g, - .sprom_get_tri5gl = bhnd_compat_sprom_get_tri5gl, - .sprom_get_tri5g = bhnd_compat_sprom_get_tri5g, - .sprom_get_tri5gh = bhnd_compat_sprom_get_tri5gh, - .sprom_get_rssisav2g = bhnd_compat_sprom_get_rssisav2g, - .sprom_get_rssismc2g = bhnd_compat_sprom_get_rssismc2g, - .sprom_get_rssismf2g = bhnd_compat_sprom_get_rssismf2g, - .sprom_get_bxa2g = bhnd_compat_sprom_get_bxa2g, - .sprom_get_rssisav5g = bhnd_compat_sprom_get_rssisav5g, - .sprom_get_rssismc5g = bhnd_compat_sprom_get_rssismc5g, - .sprom_get_rssismf5g = bhnd_compat_sprom_get_rssismf5g, - .sprom_get_bxa5g = bhnd_compat_sprom_get_bxa5g, - .sprom_get_cck2gpo = bhnd_compat_sprom_get_cck2gpo, - .sprom_get_ofdm2gpo = bhnd_compat_sprom_get_ofdm2gpo, - .sprom_get_ofdm5glpo = bhnd_compat_sprom_get_ofdm5glpo, - .sprom_get_ofdm5gpo = bhnd_compat_sprom_get_ofdm5gpo, - .sprom_get_ofdm5ghpo = bhnd_compat_sprom_get_ofdm5ghpo, - .sprom_get_bf_lo = bhnd_compat_sprom_get_bf_lo, - .sprom_set_bf_lo = bhnd_compat_sprom_set_bf_lo, - .sprom_get_bf_hi = bhnd_compat_sprom_get_bf_hi, - .sprom_get_bf2_lo = bhnd_compat_sprom_get_bf2_lo, - .sprom_get_bf2_hi = bhnd_compat_sprom_get_bf2_hi, - .sprom_get_fem_2ghz_tssipos = bhnd_compat_sprom_get_fem_2ghz_tssipos, - .sprom_get_fem_2ghz_extpa_gain = bhnd_compat_sprom_get_fem_2ghz_extpa_gain, - .sprom_get_fem_2ghz_pdet_range = bhnd_compat_sprom_get_fem_2ghz_pdet_range, - .sprom_get_fem_2ghz_tr_iso = bhnd_compat_sprom_get_fem_2ghz_tr_iso, - .sprom_get_fem_2ghz_antswlut = bhnd_compat_sprom_get_fem_2ghz_antswlut, - .sprom_get_fem_5ghz_extpa_gain = bhnd_compat_sprom_get_fem_5ghz_extpa_gain, - .sprom_get_fem_5ghz_pdet_range = bhnd_compat_sprom_get_fem_5ghz_pdet_range, - .sprom_get_fem_5ghz_antswlut = bhnd_compat_sprom_get_fem_5ghz_antswlut, - .sprom_get_txpid_2g_0 = bhnd_compat_sprom_get_txpid_2g_0, - .sprom_get_txpid_2g_1 = bhnd_compat_sprom_get_txpid_2g_1, - .sprom_get_txpid_5gl_0 = bhnd_compat_sprom_get_txpid_5gl_0, - .sprom_get_txpid_5gl_1 = bhnd_compat_sprom_get_txpid_5gl_1, - .sprom_get_txpid_5g_0 = bhnd_compat_sprom_get_txpid_5g_0, - .sprom_get_txpid_5g_1 = bhnd_compat_sprom_get_txpid_5g_1, - .sprom_get_txpid_5gh_0 = bhnd_compat_sprom_get_txpid_5gh_0, - .sprom_get_txpid_5gh_1 = bhnd_compat_sprom_get_txpid_5gh_1, - .sprom_get_stbcpo = bhnd_compat_sprom_get_stbcpo, - .sprom_get_cddpo = bhnd_compat_sprom_get_cddpo, - .powerup = bhnd_compat_powerup, - .powerdown = bhnd_compat_powerdown, - .read_2 = bhnd_compat_read_2, - .write_2 = bhnd_compat_write_2, - .read_4 = bhnd_compat_read_4, - .write_4 = bhnd_compat_write_4, - .dev_up = bhnd_compat_dev_up, - .dev_down = bhnd_compat_dev_down, - .dev_isup = bhnd_compat_dev_isup, - .pcicore_intr = bhnd_compat_pcicore_intr, - .dma_translation = bhnd_compat_dma_translation, - .read_multi_2 = bhnd_compat_read_multi_2, - .read_multi_4 = bhnd_compat_read_multi_4, - .write_multi_2 = bhnd_compat_write_multi_2, - .write_multi_4 = bhnd_compat_write_multi_4, - .barrier = bhnd_compat_barrier, - .cc_pmu_set_ldovolt = bhnd_compat_cc_pmu_set_ldovolt, - .cc_pmu_set_ldoparef = bhnd_compat_cc_pmu_set_ldoparef, - .gpio_set = bhnd_compat_gpio_set, - .gpio_get = bhnd_compat_gpio_get, - .fix_imcfglobug = bhnd_compat_fix_imcfglobug, - .sprom_get_core_power_info = bhnd_compat_sprom_get_core_power_info, - .sprom_get_mcs2gpo = bhnd_compat_sprom_get_mcs2gpo, - .sprom_get_mcs5glpo = bhnd_compat_sprom_get_mcs5glpo, - .sprom_get_mcs5gpo = bhnd_compat_sprom_get_mcs5gpo, - .sprom_get_mcs5ghpo = bhnd_compat_sprom_get_mcs5ghpo, - .pmu_spuravoid_pllupdate = bhnd_compat_pmu_spuravoid_pllupdate, - .cc_set32 = bhnd_compat_cc_set32, - .cc_mask32 = bhnd_compat_cc_mask32, - .cc_write32 = bhnd_compat_cc_write32, -}; Property changes on: head/sys/dev/bwn/if_bwn_siba_compat.c ___________________________________________________________________ Deleted: svn:eol-style ## -1 +0,0 ## -native \ No newline at end of property Deleted: svn:keywords ## -1 +0,0 ## -FreeBSD=%H \ No newline at end of property Deleted: svn:mime-type ## -1 +0,0 ## -text/plain \ No newline at end of property Index: head/sys/dev/bwn/if_bwn_siba_compat.h =================================================================== --- head/sys/dev/bwn/if_bwn_siba_compat.h (revision 328911) +++ head/sys/dev/bwn/if_bwn_siba_compat.h (nonexistent) @@ -1,102 +0,0 @@ -/*- - * SPDX-License-Identifier: BSD-2-Clause-FreeBSD - * - * Copyright (c) 2016 Landon J. Fuller . - * Copyright (c) 2017 The FreeBSD Foundation - * All rights reserved. - * - * Portions of this software were developed by Landon Fuller - * under sponsorship from the FreeBSD Foundation. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - * - * $FreeBSD$ - */ - -#ifndef _IF_BWN_SIBA_COMPAT_H_ -#define _IF_BWN_SIBA_COMPAT_H_ - -#define BWN_USE_SIBA 0 -#include "if_bwn_siba.h" - -#include "if_bwnvar.h" - -#define BWN_BHND_NUM_CORE_PWR 4 - -/** - * Compatiblity shim state. - */ -struct bwn_bhnd_ctx { - device_t chipc_dev; /**< ChipCommon device */ - device_t gpio_dev; /**< GPIO device */ - - device_t pmu_dev; /**< PMU device, or NULL if no PMU */ - uint32_t pmu_cctl_addr; /**< chipctrl_addr target of - reads/writes to/from the - chipctrl_data register */ - - uint8_t sromrev; /**< SROM format revision */ - - /* NVRAM variables for which bwn(4) expects the bus to manage storage - * for (and in some cases, allow writes). */ - uint8_t mac_80211bg[6]; /**< D11 unit 0 */ - uint8_t mac_80211a[6]; /**< D11 unit 1 */ - - uint32_t boardflags; /**< boardflags (bwn-writable) */ - uint8_t pa0maxpwr; /**< 2GHz max power (bwn-writable) */ -}; - -/** - * Return the bwn(4) device's bhnd compatiblity context. - */ -static inline struct bwn_bhnd_ctx * -bwn_bhnd_get_ctx(device_t dev) -{ - struct bwn_softc *sc = device_get_softc(dev); - return (sc->sc_bus_ctx); -} - -/** - * Fetch an NVRAM variable via bhnd_nvram_getvar_*(). - */ -#define BWN_BHND_NVRAM_FETCH_VAR(_dev, _type, _name, _result) \ -do { \ - int error; \ - \ - error = bhnd_nvram_getvar_ ## _type(_dev, _name, _result); \ - if (error) { \ - panic("NVRAM variable %s unreadable: %d", _name, \ - error); \ - } \ -} while(0) - -/** - * Fetch and return an NVRAM variable via bhnd_nvram_getvar_*(). - */ -#define BWN_BHND_NVRAM_RETURN_VAR(_dev, _type, _name) \ -do { \ - _type ## _t value; \ - BWN_BHND_NVRAM_FETCH_VAR(_dev, _type, _name, &value); \ - return (value); \ -} while(0) - -#endif /* _IF_BWN_SIBA_COMPAT_H_ */ Property changes on: head/sys/dev/bwn/if_bwn_siba_compat.h ___________________________________________________________________ Deleted: svn:eol-style ## -1 +0,0 ## -native \ No newline at end of property Deleted: svn:keywords ## -1 +0,0 ## -FreeBSD=%H \ No newline at end of property Deleted: svn:mime-type ## -1 +0,0 ## -text/plain \ No newline at end of property Index: head/sys/dev/bwn/if_bwn_chipid.h =================================================================== --- head/sys/dev/bwn/if_bwn_chipid.h (revision 328911) +++ head/sys/dev/bwn/if_bwn_chipid.h (nonexistent) @@ -1,71 +0,0 @@ -/*- - * Copyright (c) 2016 Adrian Chadd . - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer, - * without modification. - * 2. Redistributions in binary form must reproduce at minimum a disclaimer - * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any - * redistribution must be conditioned upon including a substantially - * similar Disclaimer requirement for further binary redistribution. - * - * NO WARRANTY - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY - * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL - * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, - * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER - * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF - * THE POSSIBILITY OF SUCH DAMAGES. - * - * $FreeBSD$ - */ -#ifndef __IF_BWN_CHIPID_H__ -#define __IF_BWN_CHIPID_H__ - -/* - * BCMA chip identifiers. - */ -#define BCMA_CHIP_ID_BCM4313 0x4313 -#define BCMA_CHIP_ID_BCM43142 43142 -#define BCMA_CHIP_ID_BCM43131 43131 -#define BCMA_CHIP_ID_BCM43217 43217 -#define BCMA_CHIP_ID_BCM43222 43222 -#define BCMA_CHIP_ID_BCM43224 43224 -#define BCMA_PKG_ID_BCM43224_FAB_CSM 0x8 -#define BCMA_PKG_ID_BCM43224_FAB_SMIC 0xa -#define BCMA_CHIP_ID_BCM43225 43225 -#define BCMA_CHIP_ID_BCM43227 43227 -#define BCMA_CHIP_ID_BCM43228 43228 -#define BCMA_CHIP_ID_BCM43421 43421 -#define BCMA_CHIP_ID_BCM43428 43428 -#define BCMA_CHIP_ID_BCM43431 43431 -#define BCMA_CHIP_ID_BCM43460 43460 -#define BCMA_CHIP_ID_BCM4331 0x4331 -#define BCMA_CHIP_ID_BCM6362 0x6362 -#define BCMA_CHIP_ID_BCM4360 0x4360 -#define BCMA_CHIP_ID_BCM4352 0x4352 -#define BCMA_CHIP_ID_BCM4706 0x5300 -#define BCMA_CHIP_ID_BCM4716 0x4716 -#define BCMA_CHIP_ID_BCM47162 47162 -#define BCMA_CHIP_ID_BCM4748 0x4748 -#define BCMA_CHIP_ID_BCM4749 0x4749 -#define BCMA_CHIP_ID_BCM5356 0x5356 -#define BCMA_CHIP_ID_BCM5357 0x5357 -#define BCMA_CHIP_ID_BCM53572 53572 -#define BCMA_CHIP_ID_BCM4707 53010 -#define BCMA_CHIP_ID_BCM47094 53030 -#define BCMA_CHIP_ID_BCM53018 53018 - -#define BCMA_BOARD_TYPE_BCM943224M93 0x008B -#define BCMA_BOARD_TYPE_BCM943224M93A 0x0090 - -#endif /* __IF_BWN_CHIPID_H__ */ Property changes on: head/sys/dev/bwn/if_bwn_chipid.h ___________________________________________________________________ Deleted: svn:eol-style ## -1 +0,0 ## -native \ No newline at end of property Deleted: svn:keywords ## -1 +0,0 ## -FreeBSD=%H \ No newline at end of property Deleted: svn:mime-type ## -1 +0,0 ## -text/plain \ No newline at end of property Index: head/sys/dev/bwn/if_bwn_siba.c =================================================================== --- head/sys/dev/bwn/if_bwn_siba.c (revision 328911) +++ head/sys/dev/bwn/if_bwn_siba.c (nonexistent) @@ -1,171 +0,0 @@ -/*- - * SPDX-License-Identifier: BSD-2-Clause-FreeBSD - * - * Copyright (c) 2016 Landon Fuller - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - */ - -#include -__FBSDID("$FreeBSD$"); - -#include -#include -#include - -#include -#include -#include - -#include -#include - -#define BWN_USE_SIBA 1 -#include "if_bwn_siba.h" - -/** Legacy siba(4) bus operations */ - -static int -bwn_siba_bus_ops_init(device_t dev) -{ - return (0); -} - -static void -bwn_siba_bus_ops_fini(device_t dev) -{ -} - -const struct bwn_bus_ops bwn_siba_bus_ops = { - .init = bwn_siba_bus_ops_init, - .fini = bwn_siba_bus_ops_fini, - .pci_find_cap = pci_find_cap, - .pci_alloc_msi = pci_alloc_msi, - .pci_release_msi = pci_release_msi, - .pci_msi_count = pci_msi_count, - .get_vendor = siba_get_vendor, - .get_device = siba_get_device, - .get_revid = siba_get_revid, - .get_pci_vendor = siba_get_pci_vendor, - .get_pci_device = siba_get_pci_device, - .get_pci_subvendor = siba_get_pci_subvendor, - .get_pci_subdevice = siba_get_pci_subdevice, - .get_pci_revid = siba_get_pci_revid, - .get_chipid = siba_get_chipid, - .get_chiprev = siba_get_chiprev, - .get_chippkg = siba_get_chippkg, - .get_type = siba_get_type, - .get_cc_pmufreq = siba_get_cc_pmufreq, - .get_cc_caps = siba_get_cc_caps, - .get_cc_powerdelay = siba_get_cc_powerdelay, - .get_pcicore_revid = siba_get_pcicore_revid, - .sprom_get_rev = siba_sprom_get_rev, - .sprom_get_mac_80211bg = siba_sprom_get_mac_80211bg, - .sprom_get_mac_80211a = siba_sprom_get_mac_80211a, - .sprom_get_brev = siba_sprom_get_brev, - .sprom_get_ccode = siba_sprom_get_ccode, - .sprom_get_ant_a = siba_sprom_get_ant_a, - .sprom_get_ant_bg = siba_sprom_get_ant_bg, - .sprom_get_pa0b0 = siba_sprom_get_pa0b0, - .sprom_get_pa0b1 = siba_sprom_get_pa0b1, - .sprom_get_pa0b2 = siba_sprom_get_pa0b2, - .sprom_get_gpio0 = siba_sprom_get_gpio0, - .sprom_get_gpio1 = siba_sprom_get_gpio1, - .sprom_get_gpio2 = siba_sprom_get_gpio2, - .sprom_get_gpio3 = siba_sprom_get_gpio3, - .sprom_get_maxpwr_bg = siba_sprom_get_maxpwr_bg, - .sprom_set_maxpwr_bg = siba_sprom_set_maxpwr_bg, - .sprom_get_rxpo2g = siba_sprom_get_rxpo2g, - .sprom_get_rxpo5g = siba_sprom_get_rxpo5g, - .sprom_get_tssi_bg = siba_sprom_get_tssi_bg, - .sprom_get_tri2g = siba_sprom_get_tri2g, - .sprom_get_tri5gl = siba_sprom_get_tri5gl, - .sprom_get_tri5g = siba_sprom_get_tri5g, - .sprom_get_tri5gh = siba_sprom_get_tri5gh, - .sprom_get_rssisav2g = siba_sprom_get_rssisav2g, - .sprom_get_rssismc2g = siba_sprom_get_rssismc2g, - .sprom_get_rssismf2g = siba_sprom_get_rssismf2g, - .sprom_get_bxa2g = siba_sprom_get_bxa2g, - .sprom_get_rssisav5g = siba_sprom_get_rssisav5g, - .sprom_get_rssismc5g = siba_sprom_get_rssismc5g, - .sprom_get_rssismf5g = siba_sprom_get_rssismf5g, - .sprom_get_bxa5g = siba_sprom_get_bxa5g, - .sprom_get_cck2gpo = siba_sprom_get_cck2gpo, - .sprom_get_ofdm2gpo = siba_sprom_get_ofdm2gpo, - .sprom_get_ofdm5glpo = siba_sprom_get_ofdm5glpo, - .sprom_get_ofdm5gpo = siba_sprom_get_ofdm5gpo, - .sprom_get_ofdm5ghpo = siba_sprom_get_ofdm5ghpo, - .sprom_get_bf_lo = siba_sprom_get_bf_lo, - .sprom_set_bf_lo = siba_sprom_set_bf_lo, - .sprom_get_bf_hi = siba_sprom_get_bf_hi, - .sprom_get_bf2_lo = siba_sprom_get_bf2_lo, - .sprom_get_bf2_hi = siba_sprom_get_bf2_hi, - .sprom_get_fem_2ghz_tssipos = siba_sprom_get_fem_2ghz_tssipos, - .sprom_get_fem_2ghz_extpa_gain = siba_sprom_get_fem_2ghz_extpa_gain, - .sprom_get_fem_2ghz_pdet_range = siba_sprom_get_fem_2ghz_pdet_range, - .sprom_get_fem_2ghz_tr_iso = siba_sprom_get_fem_2ghz_tr_iso, - .sprom_get_fem_2ghz_antswlut = siba_sprom_get_fem_2ghz_antswlut, - .sprom_get_fem_5ghz_extpa_gain = siba_sprom_get_fem_5ghz_extpa_gain, - .sprom_get_fem_5ghz_pdet_range = siba_sprom_get_fem_5ghz_pdet_range, - .sprom_get_fem_5ghz_antswlut = siba_sprom_get_fem_5ghz_antswlut, - .sprom_get_txpid_2g_0 = siba_sprom_get_txpid_2g_0, - .sprom_get_txpid_2g_1 = siba_sprom_get_txpid_2g_1, - .sprom_get_txpid_5gl_0 = siba_sprom_get_txpid_5gl_0, - .sprom_get_txpid_5gl_1 = siba_sprom_get_txpid_5gl_1, - .sprom_get_txpid_5g_0 = siba_sprom_get_txpid_5g_0, - .sprom_get_txpid_5g_1 = siba_sprom_get_txpid_5g_1, - .sprom_get_txpid_5gh_0 = siba_sprom_get_txpid_5gh_0, - .sprom_get_txpid_5gh_1 = siba_sprom_get_txpid_5gh_1, - .sprom_get_stbcpo = siba_sprom_get_stbcpo, - .sprom_get_cddpo = siba_sprom_get_cddpo, - .powerup = siba_powerup, - .powerdown = siba_powerdown, - .read_2 = siba_read_2, - .write_2 = siba_write_2, - .read_4 = siba_read_4, - .write_4 = siba_write_4, - .dev_up = siba_dev_up, - .dev_down = siba_dev_down, - .dev_isup = siba_dev_isup, - .pcicore_intr = siba_pcicore_intr, - .dma_translation = siba_dma_translation, - .read_multi_2 = siba_read_multi_2, - .read_multi_4 = siba_read_multi_4, - .write_multi_2 = siba_write_multi_2, - .write_multi_4 = siba_write_multi_4, - .barrier = siba_barrier, - .cc_pmu_set_ldovolt = siba_cc_pmu_set_ldovolt, - .cc_pmu_set_ldoparef = siba_cc_pmu_set_ldoparef, - .gpio_set = siba_gpio_set, - .gpio_get = siba_gpio_get, - .fix_imcfglobug = siba_fix_imcfglobug, - .sprom_get_core_power_info = siba_sprom_get_core_power_info, - .sprom_get_mcs2gpo = siba_sprom_get_mcs2gpo, - .sprom_get_mcs5glpo = siba_sprom_get_mcs5glpo, - .sprom_get_mcs5gpo = siba_sprom_get_mcs5gpo, - .sprom_get_mcs5ghpo = siba_sprom_get_mcs5ghpo, - .pmu_spuravoid_pllupdate = siba_pmu_spuravoid_pllupdate, - .cc_set32 = siba_cc_set32, - .cc_mask32 = siba_cc_mask32, - .cc_write32 = siba_cc_write32, -}; Property changes on: head/sys/dev/bwn/if_bwn_siba.c ___________________________________________________________________ Deleted: svn:eol-style ## -1 +0,0 ## -native \ No newline at end of property Deleted: svn:keywords ## -1 +0,0 ## -FreeBSD=%H \ No newline at end of property Deleted: svn:mime-type ## -1 +0,0 ## -text/plain \ No newline at end of property Index: head/sys/dev/bwn/if_bwn_bhnd.c =================================================================== --- head/sys/dev/bwn/if_bwn_bhnd.c (revision 328911) +++ head/sys/dev/bwn/if_bwn_bhnd.c (nonexistent) @@ -1,110 +0,0 @@ -/*- - * SPDX-License-Identifier: BSD-2-Clause-FreeBSD - * - * Copyright (c) 2016 Landon Fuller - * Copyright (c) 2017 The FreeBSD Foundation - * All rights reserved. - * - * Portions of this software were developed by Landon Fuller - * under sponsorship from the FreeBSD Foundation. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - */ - -#include -__FBSDID("$FreeBSD$"); - -#include "opt_bwn.h" -#include "opt_wlan.h" - -#include -#include -#include -#include -#include -#include - -#include -#include -#include - -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include -#include - -#include -#include - -#include "if_bwnvar.h" - -/* Supported device identifiers */ -#define BWN_DEV(_hwrev) {{ \ - BHND_MATCH_CORE(BHND_MFGID_BCM, BHND_COREID_D11), \ - BHND_MATCH_CORE_REV(_hwrev), \ -}} - -static const struct bhnd_device bwn_devices[] = { - BWN_DEV(HWREV_RANGE(5, 16)), - BWN_DEV(HWREV_EQ(23)), - - BHND_DEVICE_END -}; - -static int -bwn_bhnd_probe(device_t dev) -{ - const struct bhnd_device *id; - - id = bhnd_device_lookup(dev, bwn_devices, sizeof(bwn_devices[0])); - if (id == NULL) - return (ENXIO); - - bhnd_set_default_core_desc(dev); - return (BUS_PROBE_DEFAULT); -} - -static device_method_t bwn_bhnd_methods[] = { - /* Device interface */ - DEVMETHOD(device_probe, bwn_bhnd_probe), - - DEVMETHOD_END -}; - -static devclass_t bwn_devclass; - -DEFINE_CLASS_1(bwn, bwn_bhnd_driver, bwn_bhnd_methods, sizeof(struct bwn_softc), - bwn_driver); - -DRIVER_MODULE(bwn_bhnd, bhnd, bwn_bhnd_driver, bwn_devclass, 0, 0); -MODULE_DEPEND(bwn_bhnd, bhnd, 1, 1, 1); -MODULE_VERSION(bwn_bhnd, 1); Property changes on: head/sys/dev/bwn/if_bwn_bhnd.c ___________________________________________________________________ Deleted: svn:eol-style ## -1 +0,0 ## -native \ No newline at end of property Deleted: svn:keywords ## -1 +0,0 ## -FreeBSD=%H \ No newline at end of property Deleted: svn:mime-type ## -1 +0,0 ## -text/plain \ No newline at end of property Index: head/sys/dev/bwn/if_bwn_siba.h =================================================================== --- head/sys/dev/bwn/if_bwn_siba.h (revision 328911) +++ head/sys/dev/bwn/if_bwn_siba.h (nonexistent) @@ -1,491 +0,0 @@ -/*- - * SPDX-License-Identifier: BSD-2-Clause-FreeBSD - * - * Copyright (c) 2016 Landon J. Fuller . - * Copyright (c) 2007 Bruce M. Simpson. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - * - * $FreeBSD$ - */ - -#ifndef _IF_BWN_SIBA_H_ -#define _IF_BWN_SIBA_H_ - -/** If true, expose legacy siba_pci headers directly. Otherwise, - * we expose our siba/bhnd compatibility shims. */ -#ifndef BWN_USE_SIBA -#define BWN_USE_SIBA 0 -#endif - -struct bwn_softc; -struct siba_sprom_core_pwr_info; - -/* - * Legacy siba(4) bus API compatibility shims. - */ -struct bwn_bus_ops { - /* bus-specific initialization/finalization */ - int (*init)(device_t); - void (*fini)(device_t); - - /* compatibility shims */ - int (*pci_find_cap)(device_t, int, int *); - int (*pci_alloc_msi)(device_t, int *); - int (*pci_release_msi)(device_t); - int (*pci_msi_count)(device_t); - uint16_t (*get_vendor)(device_t); - uint16_t (*get_device)(device_t); - uint8_t (*get_revid)(device_t); - uint16_t (*get_pci_vendor)(device_t); - uint16_t (*get_pci_device)(device_t); - uint16_t (*get_pci_subvendor)(device_t); - uint16_t (*get_pci_subdevice)(device_t); - uint8_t (*get_pci_revid)(device_t); - uint16_t (*get_chipid)(device_t); - uint16_t (*get_chiprev)(device_t); - uint8_t (*get_chippkg)(device_t); - enum siba_type (*get_type)(device_t); - uint32_t (*get_cc_pmufreq)(device_t); - uint32_t (*get_cc_caps)(device_t); - uint16_t (*get_cc_powerdelay)(device_t); - uint8_t (*get_pcicore_revid)(device_t); - uint8_t (*sprom_get_rev)(device_t); - uint8_t *(*sprom_get_mac_80211bg)(device_t); - uint8_t *(*sprom_get_mac_80211a)(device_t); - uint8_t (*sprom_get_brev)(device_t); - uint8_t (*sprom_get_ccode)(device_t); - uint8_t (*sprom_get_ant_a)(device_t); - uint8_t (*sprom_get_ant_bg)(device_t); - uint16_t (*sprom_get_pa0b0)(device_t); - uint16_t (*sprom_get_pa0b1)(device_t); - uint16_t (*sprom_get_pa0b2)(device_t); - uint8_t (*sprom_get_gpio0)(device_t); - uint8_t (*sprom_get_gpio1)(device_t); - uint8_t (*sprom_get_gpio2)(device_t); - uint8_t (*sprom_get_gpio3)(device_t); - uint16_t (*sprom_get_maxpwr_bg)(device_t); - void (*sprom_set_maxpwr_bg)(device_t, uint16_t); - uint8_t (*sprom_get_rxpo2g)(device_t); - uint8_t (*sprom_get_rxpo5g)(device_t); - uint8_t (*sprom_get_tssi_bg)(device_t); - uint8_t (*sprom_get_tri2g)(device_t); - uint8_t (*sprom_get_tri5gl)(device_t); - uint8_t (*sprom_get_tri5g)(device_t); - uint8_t (*sprom_get_tri5gh)(device_t); - uint8_t (*sprom_get_rssisav2g)(device_t); - uint8_t (*sprom_get_rssismc2g)(device_t); - uint8_t (*sprom_get_rssismf2g)(device_t); - uint8_t (*sprom_get_bxa2g)(device_t); - uint8_t (*sprom_get_rssisav5g)(device_t); - uint8_t (*sprom_get_rssismc5g)(device_t); - uint8_t (*sprom_get_rssismf5g)(device_t); - uint8_t (*sprom_get_bxa5g)(device_t); - uint16_t (*sprom_get_cck2gpo)(device_t); - uint32_t (*sprom_get_ofdm2gpo)(device_t); - uint32_t (*sprom_get_ofdm5glpo)(device_t); - uint32_t (*sprom_get_ofdm5gpo)(device_t); - uint32_t (*sprom_get_ofdm5ghpo)(device_t); - uint16_t (*sprom_get_bf_lo)(device_t); - void (*sprom_set_bf_lo)(device_t, uint16_t); - uint16_t (*sprom_get_bf_hi)(device_t); - uint16_t (*sprom_get_bf2_lo)(device_t); - uint16_t (*sprom_get_bf2_hi)(device_t); - uint8_t (*sprom_get_fem_2ghz_tssipos)(device_t); - uint8_t (*sprom_get_fem_2ghz_extpa_gain)(device_t); - uint8_t (*sprom_get_fem_2ghz_pdet_range)(device_t); - uint8_t (*sprom_get_fem_2ghz_tr_iso)(device_t); - uint8_t (*sprom_get_fem_2ghz_antswlut)(device_t); - uint8_t (*sprom_get_fem_5ghz_extpa_gain)(device_t); - uint8_t (*sprom_get_fem_5ghz_pdet_range)(device_t); - uint8_t (*sprom_get_fem_5ghz_antswlut)(device_t); - uint8_t (*sprom_get_txpid_2g_0)(device_t); - uint8_t (*sprom_get_txpid_2g_1)(device_t); - uint8_t (*sprom_get_txpid_5gl_0)(device_t); - uint8_t (*sprom_get_txpid_5gl_1)(device_t); - uint8_t (*sprom_get_txpid_5g_0)(device_t); - uint8_t (*sprom_get_txpid_5g_1)(device_t); - uint8_t (*sprom_get_txpid_5gh_0)(device_t); - uint8_t (*sprom_get_txpid_5gh_1)(device_t); - uint16_t (*sprom_get_stbcpo)(device_t); - uint16_t (*sprom_get_cddpo)(device_t); - void (*powerup)(device_t, int); - int (*powerdown)(device_t); - uint16_t (*read_2)(device_t, uint16_t); - void (*write_2)(device_t, uint16_t, uint16_t); - uint32_t (*read_4)(device_t, uint16_t); - void (*write_4)(device_t, uint16_t, uint32_t); - void (*dev_up)(device_t, uint32_t); - void (*dev_down)(device_t, uint32_t); - int (*dev_isup)(device_t); - void (*pcicore_intr)(device_t); - uint32_t (*dma_translation)(device_t); - void (*read_multi_2)(device_t, void *, size_t, uint16_t); - void (*read_multi_4)(device_t, void *, size_t, uint16_t); - void (*write_multi_2)(device_t, const void *, size_t, uint16_t); - void (*write_multi_4)(device_t, const void *, size_t, uint16_t); - void (*barrier)(device_t, int); - void (*cc_pmu_set_ldovolt)(device_t, int, uint32_t); - void (*cc_pmu_set_ldoparef)(device_t, uint8_t); - void (*gpio_set)(device_t, uint32_t); - uint32_t (*gpio_get)(device_t); - void (*fix_imcfglobug)(device_t); - int (*sprom_get_core_power_info)(device_t, int, struct siba_sprom_core_pwr_info *); - int (*sprom_get_mcs2gpo)(device_t, uint16_t *); - int (*sprom_get_mcs5glpo)(device_t, uint16_t *); - int (*sprom_get_mcs5gpo)(device_t, uint16_t *); - int (*sprom_get_mcs5ghpo)(device_t, uint16_t *); - void (*pmu_spuravoid_pllupdate)(device_t, int); - void (*cc_set32)(device_t, uint32_t, uint32_t); - void (*cc_mask32)(device_t, uint32_t, uint32_t); - void (*cc_write32)(device_t, uint32_t, uint32_t); -}; - -#if BWN_USE_SIBA - -#include -#include -#include - -#define BWN_BUS_OPS_ATTACH(_dev) (0) -#define BWN_BUS_OPS_DETACH(_dev) - -#else /* !BWN_USE_SIBA */ - -struct bwn_bus_ops; - -extern const struct bwn_bus_ops bwn_siba_bus_ops; -extern const struct bwn_bus_ops bwn_bhnd_bus_ops; - -/* - * Declared in: - * /usr/home/landonf/Documents/Code/FreeBSD/svn/head/sys/dev/siba/siba_ids.h - */ - -struct siba_devid { - uint16_t sd_vendor; - uint16_t sd_device; - uint8_t sd_rev; - char *sd_desc; -}; - -#define SIBA_DEV(_vendor, _cid, _rev, _msg) \ - { SIBA_VID_##_vendor, SIBA_DEVID_##_cid, _rev, _msg } - -#define SIBA_DEVID_80211 0x812 -#define SIBA_VID_BROADCOM 0x4243 - -/* - * Declared in: - * /usr/home/landonf/Documents/Code/FreeBSD/svn/head/sys/dev/siba/sibareg.h - */ - -#define SIBA_CC_CAPS_PMU 0x10000000 -#define SIBA_CC_CHIPCTL 0x0028 -#define SIBA_CC_CHIPCTL_ADDR 0x0650 -#define SIBA_CC_CHIPCTL_DATA 0x0654 - -#define SIBA_DMA_TRANSLATION_MASK 0xc0000000 - -#define SIBA_TGSLOW 0x0f98 -#define SIBA_TGSLOW_FGC 0x00020000 - -#define SIBA_TGSHIGH 0x0f9c -#define SIBA_TGSHIGH_DMA64 0x10000000 - -#define SIBA_BOARDVENDOR_DELL 0x1028 -#define SIBA_BOARDVENDOR_BCM 0x14e4 - -#define SIBA_BOARD_BCM4309G 0x0421 -#define SIBA_BOARD_BU4306 0x0416 -#define SIBA_BOARD_BCM4321 0x046d - -#define SIBA_CHIPPACK_BCM4712S 1 - - -/* - * Declared in: - * /usr/home/landonf/Documents/Code/FreeBSD/svn/head/sys/dev/siba/sibavar.h - */ - -enum siba_type { - SIBA_TYPE_SSB /* unused */, - SIBA_TYPE_PCI, - SIBA_TYPE_PCMCIA -}; - -/* TODO: need a real country code table */ -enum { - SIBA_CCODE_JAPAN, - SIBA_CCODE_UNKNOWN -}; - -struct siba_sprom_core_pwr_info { - uint8_t itssi_2g; - uint8_t itssi_5g; - uint8_t maxpwr_2g; - uint8_t maxpwr_5gl; - uint8_t maxpwr_5g; - uint8_t maxpwr_5gh; - int16_t pa_2g[3]; - int16_t pa_5gl[4]; - int16_t pa_5g[4]; - int16_t pa_5gh[4]; -}; - -#define SIBA_LDO_PAREF 0 - -#define BWN_BUS_OPS_SC(_sc) \ - ((_sc)->sc_bus_ops) - -#define BWN_BUS_OPS(_dev) \ - BWN_BUS_OPS_SC((struct bwn_softc *)device_get_softc(_dev)) - -#define BWN_BUS_OPS_ATTACH(_dev) \ - BWN_BUS_OPS(_dev)->init(_dev) -#define BWN_BUS_OPS_DETACH(_dev) \ - BWN_BUS_OPS(_dev)->fini(_dev) - -#define pci_find_cap(_dev, capability, capreg) \ - BWN_BUS_OPS(_dev)->pci_find_cap(_dev, capability, capreg) -#define pci_alloc_msi(_dev, count) \ - BWN_BUS_OPS(_dev)->pci_alloc_msi(_dev, count) -#define pci_release_msi(_dev) \ - BWN_BUS_OPS(_dev)->pci_release_msi(_dev) -#define pci_msi_count(_dev) \ - BWN_BUS_OPS(_dev)->pci_msi_count(_dev) - -#define siba_get_vendor(_dev) \ - BWN_BUS_OPS(_dev)->get_vendor(_dev) -#define siba_get_device(_dev) \ - BWN_BUS_OPS(_dev)->get_device(_dev) -#define siba_get_revid(_dev) \ - BWN_BUS_OPS(_dev)->get_revid(_dev) -#define siba_get_pci_vendor(_dev) \ - BWN_BUS_OPS(_dev)->get_pci_vendor(_dev) -#define siba_get_pci_device(_dev) \ - BWN_BUS_OPS(_dev)->get_pci_device(_dev) -#define siba_get_pci_subvendor(_dev) \ - BWN_BUS_OPS(_dev)->get_pci_subvendor(_dev) -#define siba_get_pci_subdevice(_dev) \ - BWN_BUS_OPS(_dev)->get_pci_subdevice(_dev) -#define siba_get_pci_revid(_dev) \ - BWN_BUS_OPS(_dev)->get_pci_revid(_dev) -#define siba_get_chipid(_dev) \ - BWN_BUS_OPS(_dev)->get_chipid(_dev) -#define siba_get_chiprev(_dev) \ - BWN_BUS_OPS(_dev)->get_chiprev(_dev) -#define siba_get_chippkg(_dev) \ - BWN_BUS_OPS(_dev)->get_chippkg(_dev) -#define siba_get_type(_dev) \ - BWN_BUS_OPS(_dev)->get_type(_dev) -#define siba_get_cc_pmufreq(_dev) \ - BWN_BUS_OPS(_dev)->get_cc_pmufreq(_dev) -#define siba_get_cc_caps(_dev) \ - BWN_BUS_OPS(_dev)->get_cc_caps(_dev) -#define siba_get_cc_powerdelay(_dev) \ - BWN_BUS_OPS(_dev)->get_cc_powerdelay(_dev) -#define siba_get_pcicore_revid(_dev) \ - BWN_BUS_OPS(_dev)->get_pcicore_revid(_dev) -#define siba_sprom_get_rev(_dev) \ - BWN_BUS_OPS(_dev)->sprom_get_rev(_dev) -#define siba_sprom_get_mac_80211bg(_dev) \ - BWN_BUS_OPS(_dev)->sprom_get_mac_80211bg(_dev) -#define siba_sprom_get_mac_80211a(_dev) \ - BWN_BUS_OPS(_dev)->sprom_get_mac_80211a(_dev) -#define siba_sprom_get_brev(_dev) \ - BWN_BUS_OPS(_dev)->sprom_get_brev(_dev) -#define siba_sprom_get_ccode(_dev) \ - BWN_BUS_OPS(_dev)->sprom_get_ccode(_dev) -#define siba_sprom_get_ant_a(_dev) \ - BWN_BUS_OPS(_dev)->sprom_get_ant_a(_dev) -#define siba_sprom_get_ant_bg(_dev) \ - BWN_BUS_OPS(_dev)->sprom_get_ant_bg(_dev) -#define siba_sprom_get_pa0b0(_dev) \ - BWN_BUS_OPS(_dev)->sprom_get_pa0b0(_dev) -#define siba_sprom_get_pa0b1(_dev) \ - BWN_BUS_OPS(_dev)->sprom_get_pa0b1(_dev) -#define siba_sprom_get_pa0b2(_dev) \ - BWN_BUS_OPS(_dev)->sprom_get_pa0b2(_dev) -#define siba_sprom_get_gpio0(_dev) \ - BWN_BUS_OPS(_dev)->sprom_get_gpio0(_dev) -#define siba_sprom_get_gpio1(_dev) \ - BWN_BUS_OPS(_dev)->sprom_get_gpio1(_dev) -#define siba_sprom_get_gpio2(_dev) \ - BWN_BUS_OPS(_dev)->sprom_get_gpio2(_dev) -#define siba_sprom_get_gpio3(_dev) \ - BWN_BUS_OPS(_dev)->sprom_get_gpio3(_dev) -#define siba_sprom_get_maxpwr_bg(_dev) \ - BWN_BUS_OPS(_dev)->sprom_get_maxpwr_bg(_dev) -#define siba_sprom_set_maxpwr_bg(_dev, t) \ - BWN_BUS_OPS(_dev)->sprom_set_maxpwr_bg(_dev, t) -#define siba_sprom_get_rxpo2g(_dev) \ - BWN_BUS_OPS(_dev)->sprom_get_rxpo2g(_dev) -#define siba_sprom_get_rxpo5g(_dev) \ - BWN_BUS_OPS(_dev)->sprom_get_rxpo5g(_dev) -#define siba_sprom_get_tssi_bg(_dev) \ - BWN_BUS_OPS(_dev)->sprom_get_tssi_bg(_dev) -#define siba_sprom_get_tri2g(_dev) \ - BWN_BUS_OPS(_dev)->sprom_get_tri2g(_dev) -#define siba_sprom_get_tri5gl(_dev) \ - BWN_BUS_OPS(_dev)->sprom_get_tri5gl(_dev) -#define siba_sprom_get_tri5g(_dev) \ - BWN_BUS_OPS(_dev)->sprom_get_tri5g(_dev) -#define siba_sprom_get_tri5gh(_dev) \ - BWN_BUS_OPS(_dev)->sprom_get_tri5gh(_dev) -#define siba_sprom_get_rssisav2g(_dev) \ - BWN_BUS_OPS(_dev)->sprom_get_rssisav2g(_dev) -#define siba_sprom_get_rssismc2g(_dev) \ - BWN_BUS_OPS(_dev)->sprom_get_rssismc2g(_dev) -#define siba_sprom_get_rssismf2g(_dev) \ - BWN_BUS_OPS(_dev)->sprom_get_rssismf2g(_dev) -#define siba_sprom_get_bxa2g(_dev) \ - BWN_BUS_OPS(_dev)->sprom_get_bxa2g(_dev) -#define siba_sprom_get_rssisav5g(_dev) \ - BWN_BUS_OPS(_dev)->sprom_get_rssisav5g(_dev) -#define siba_sprom_get_rssismc5g(_dev) \ - BWN_BUS_OPS(_dev)->sprom_get_rssismc5g(_dev) -#define siba_sprom_get_rssismf5g(_dev) \ - BWN_BUS_OPS(_dev)->sprom_get_rssismf5g(_dev) -#define siba_sprom_get_bxa5g(_dev) \ - BWN_BUS_OPS(_dev)->sprom_get_bxa5g(_dev) -#define siba_sprom_get_cck2gpo(_dev) \ - BWN_BUS_OPS(_dev)->sprom_get_cck2gpo(_dev) -#define siba_sprom_get_ofdm2gpo(_dev) \ - BWN_BUS_OPS(_dev)->sprom_get_ofdm2gpo(_dev) -#define siba_sprom_get_ofdm5glpo(_dev) \ - BWN_BUS_OPS(_dev)->sprom_get_ofdm5glpo(_dev) -#define siba_sprom_get_ofdm5gpo(_dev) \ - BWN_BUS_OPS(_dev)->sprom_get_ofdm5gpo(_dev) -#define siba_sprom_get_ofdm5ghpo(_dev) \ - BWN_BUS_OPS(_dev)->sprom_get_ofdm5ghpo(_dev) -#define siba_sprom_get_bf_lo(_dev) \ - BWN_BUS_OPS(_dev)->sprom_get_bf_lo(_dev) -#define siba_sprom_set_bf_lo(_dev, t) \ - BWN_BUS_OPS(_dev)->sprom_set_bf_lo(_dev, t) -#define siba_sprom_get_bf_hi(_dev) \ - BWN_BUS_OPS(_dev)->sprom_get_bf_hi(_dev) -#define siba_sprom_get_bf2_lo(_dev) \ - BWN_BUS_OPS(_dev)->sprom_get_bf2_lo(_dev) -#define siba_sprom_get_bf2_hi(_dev) \ - BWN_BUS_OPS(_dev)->sprom_get_bf2_hi(_dev) -#define siba_sprom_get_fem_2ghz_tssipos(_dev) \ - BWN_BUS_OPS(_dev)->sprom_get_fem_2ghz_tssipos(_dev) -#define siba_sprom_get_fem_2ghz_extpa_gain(_dev) \ - BWN_BUS_OPS(_dev)->sprom_get_fem_2ghz_extpa_gain(_dev) -#define siba_sprom_get_fem_2ghz_pdet_range(_dev) \ - BWN_BUS_OPS(_dev)->sprom_get_fem_2ghz_pdet_range(_dev) -#define siba_sprom_get_fem_2ghz_tr_iso(_dev) \ - BWN_BUS_OPS(_dev)->sprom_get_fem_2ghz_tr_iso(_dev) -#define siba_sprom_get_fem_2ghz_antswlut(_dev) \ - BWN_BUS_OPS(_dev)->sprom_get_fem_2ghz_antswlut(_dev) -#define siba_sprom_get_fem_5ghz_extpa_gain(_dev) \ - BWN_BUS_OPS(_dev)->sprom_get_fem_5ghz_extpa_gain(_dev) -#define siba_sprom_get_fem_5ghz_pdet_range(_dev) \ - BWN_BUS_OPS(_dev)->sprom_get_fem_5ghz_pdet_range(_dev) -#define siba_sprom_get_fem_5ghz_antswlut(_dev) \ - BWN_BUS_OPS(_dev)->sprom_get_fem_5ghz_antswlut(_dev) -#define siba_sprom_get_txpid_2g_0(_dev) \ - BWN_BUS_OPS(_dev)->sprom_get_txpid_2g_0(_dev) -#define siba_sprom_get_txpid_2g_1(_dev) \ - BWN_BUS_OPS(_dev)->sprom_get_txpid_2g_1(_dev) -#define siba_sprom_get_txpid_5gl_0(_dev) \ - BWN_BUS_OPS(_dev)->sprom_get_txpid_5gl_0(_dev) -#define siba_sprom_get_txpid_5gl_1(_dev) \ - BWN_BUS_OPS(_dev)->sprom_get_txpid_5gl_1(_dev) -#define siba_sprom_get_txpid_5g_0(_dev) \ - BWN_BUS_OPS(_dev)->sprom_get_txpid_5g_0(_dev) -#define siba_sprom_get_txpid_5g_1(_dev) \ - BWN_BUS_OPS(_dev)->sprom_get_txpid_5g_1(_dev) -#define siba_sprom_get_txpid_5gh_0(_dev) \ - BWN_BUS_OPS(_dev)->sprom_get_txpid_5gh_0(_dev) -#define siba_sprom_get_txpid_5gh_1(_dev) \ - BWN_BUS_OPS(_dev)->sprom_get_txpid_5gh_1(_dev) -#define siba_sprom_get_stbcpo(_dev) \ - BWN_BUS_OPS(_dev)->sprom_get_stbcpo(_dev) -#define siba_sprom_get_cddpo(_dev) \ - BWN_BUS_OPS(_dev)->sprom_get_cddpo(_dev) -#define siba_powerup(_dev, _arg1) \ - BWN_BUS_OPS(_dev)->powerup(_dev, _arg1) -#define siba_powerdown(_dev) \ - BWN_BUS_OPS(_dev)->powerdown(_dev) -#define siba_read_2(_dev, _arg1) \ - BWN_BUS_OPS(_dev)->read_2(_dev, _arg1) -#define siba_write_2(_dev, _arg1, _arg2) \ - BWN_BUS_OPS(_dev)->write_2(_dev, _arg1, _arg2) -#define siba_read_4(_dev, _arg1) \ - BWN_BUS_OPS(_dev)->read_4(_dev, _arg1) -#define siba_write_4(_dev, _arg1, _arg2) \ - BWN_BUS_OPS(_dev)->write_4(_dev, _arg1, _arg2) -#define siba_dev_up(_dev, _arg1) \ - BWN_BUS_OPS(_dev)->dev_up(_dev, _arg1) -#define siba_dev_down(_dev, _arg1) \ - BWN_BUS_OPS(_dev)->dev_down(_dev, _arg1) -#define siba_dev_isup(_dev) \ - BWN_BUS_OPS(_dev)->dev_isup(_dev) -#define siba_pcicore_intr(_dev) \ - BWN_BUS_OPS(_dev)->pcicore_intr(_dev) -#define siba_dma_translation(_dev) \ - BWN_BUS_OPS(_dev)->dma_translation(_dev) -#define siba_read_multi_2(_dev, _arg1, _arg2, _arg3) \ - BWN_BUS_OPS(_dev)->read_multi_2(_dev, _arg1, _arg2, _arg3) -#define siba_read_multi_4(_dev, _arg1, _arg2, _arg3) \ - BWN_BUS_OPS(_dev)->read_multi_4(_dev, _arg1, _arg2, _arg3) -#define siba_write_multi_2(_dev, _arg1, _arg2, _arg3) \ - BWN_BUS_OPS(_dev)->write_multi_2(_dev, _arg1, _arg2, _arg3) -#define siba_write_multi_4(_dev, _arg1, _arg2, _arg3) \ - BWN_BUS_OPS(_dev)->write_multi_4(_dev, _arg1, _arg2, _arg3) -#define siba_barrier(_dev, _arg1) \ - BWN_BUS_OPS(_dev)->barrier(_dev, _arg1) -#define siba_cc_pmu_set_ldovolt(_dev, _arg1, _arg2) \ - BWN_BUS_OPS(_dev)->cc_pmu_set_ldovolt(_dev, _arg1, _arg2) -#define siba_cc_pmu_set_ldoparef(_dev, _arg1) \ - BWN_BUS_OPS(_dev)->cc_pmu_set_ldoparef(_dev, _arg1) -#define siba_gpio_set(_dev, _arg1) \ - BWN_BUS_OPS(_dev)->gpio_set(_dev, _arg1) -#define siba_gpio_get(_dev) \ - BWN_BUS_OPS(_dev)->gpio_get(_dev) -#define siba_fix_imcfglobug(_dev) \ - BWN_BUS_OPS(_dev)->fix_imcfglobug(_dev) -#define siba_sprom_get_core_power_info(_dev, _arg1, _arg2) \ - BWN_BUS_OPS(_dev)->sprom_get_core_power_info(_dev, _arg1, _arg2) -#define siba_sprom_get_mcs2gpo(_dev, _arg1) \ - BWN_BUS_OPS(_dev)->sprom_get_mcs2gpo(_dev, _arg1) -#define siba_sprom_get_mcs5glpo(_dev, _arg1) \ - BWN_BUS_OPS(_dev)->sprom_get_mcs5glpo(_dev, _arg1) -#define siba_sprom_get_mcs5gpo(_dev, _arg1) \ - BWN_BUS_OPS(_dev)->sprom_get_mcs5gpo(_dev, _arg1) -#define siba_sprom_get_mcs5ghpo(_dev, _arg1) \ - BWN_BUS_OPS(_dev)->sprom_get_mcs5ghpo(_dev, _arg1) -#define siba_pmu_spuravoid_pllupdate(_dev, _arg1) \ - BWN_BUS_OPS(_dev)->pmu_spuravoid_pllupdate(_dev, _arg1) -#define siba_cc_set32(_dev, _arg1, _arg2) \ - BWN_BUS_OPS(_dev)->cc_set32(_dev, _arg1, _arg2) -#define siba_cc_mask32(_dev, _arg1, _arg2) \ - BWN_BUS_OPS(_dev)->cc_mask32(_dev, _arg1, _arg2) -#define siba_cc_write32(_dev, _arg1, _arg2) \ - BWN_BUS_OPS(_dev)->cc_write32(_dev, _arg1, _arg2) - -#endif /* BWN_USE_SIBA */ - -#endif /* _IF_BWN_SIBA_H_ */ Property changes on: head/sys/dev/bwn/if_bwn_siba.h ___________________________________________________________________ Deleted: svn:eol-style ## -1 +0,0 ## -native \ No newline at end of property Deleted: svn:keywords ## -1 +0,0 ## -FreeBSD=%H \ No newline at end of property Deleted: svn:mime-type ## -1 +0,0 ## -text/plain \ No newline at end of property Index: head/sys/dev/bwn/if_bwn.c =================================================================== --- head/sys/dev/bwn/if_bwn.c (revision 328911) +++ head/sys/dev/bwn/if_bwn.c (revision 328912) @@ -1,7502 +1,7779 @@ /*- * SPDX-License-Identifier: BSD-2-Clause-FreeBSD * * Copyright (c) 2009-2010 Weongyo Jeong + * Copyright (c) 2016 Landon Fuller + * Copyright (c) 2017 The FreeBSD Foundation * All rights reserved. + * + * Portions of this software were developed by Landon Fuller + * under sponsorship from the FreeBSD Foundation. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer, * without modification. * 2. Redistributions in binary form must reproduce at minimum a disclaimer * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any * redistribution must be conditioned upon including a substantially * similar Disclaimer requirement for further binary redistribution. * * NO WARRANTY * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF * THE POSSIBILITY OF SUCH DAMAGES. */ #include __FBSDID("$FreeBSD$"); /* * The Broadcom Wireless LAN controller driver. */ #include "opt_bwn.h" #include "opt_wlan.h" #include #include #include +#include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include -#include -#include - #include #include #include #include #include -#include +#include +#include +#include +#include + #include #include #include #include #include #include #include #include #include +#include "bhnd_nvram_map.h" + +#include "gpio_if.h" + static SYSCTL_NODE(_hw, OID_AUTO, bwn, CTLFLAG_RD, 0, "Broadcom driver parameters"); /* * Tunable & sysctl variables. */ #ifdef BWN_DEBUG static int bwn_debug = 0; SYSCTL_INT(_hw_bwn, OID_AUTO, debug, CTLFLAG_RWTUN, &bwn_debug, 0, "Broadcom debugging printfs"); #endif static int bwn_bfp = 0; /* use "Bad Frames Preemption" */ SYSCTL_INT(_hw_bwn, OID_AUTO, bfp, CTLFLAG_RW, &bwn_bfp, 0, "uses Bad Frames Preemption"); static int bwn_bluetooth = 1; SYSCTL_INT(_hw_bwn, OID_AUTO, bluetooth, CTLFLAG_RW, &bwn_bluetooth, 0, "turns on Bluetooth Coexistence"); static int bwn_hwpctl = 0; SYSCTL_INT(_hw_bwn, OID_AUTO, hwpctl, CTLFLAG_RW, &bwn_hwpctl, 0, "uses H/W power control"); -static int bwn_msi_disable = 0; /* MSI disabled */ -TUNABLE_INT("hw.bwn.msi_disable", &bwn_msi_disable); static int bwn_usedma = 1; SYSCTL_INT(_hw_bwn, OID_AUTO, usedma, CTLFLAG_RD, &bwn_usedma, 0, "uses DMA"); TUNABLE_INT("hw.bwn.usedma", &bwn_usedma); static int bwn_wme = 1; SYSCTL_INT(_hw_bwn, OID_AUTO, wme, CTLFLAG_RW, &bwn_wme, 0, "uses WME support"); static void bwn_attach_pre(struct bwn_softc *); static int bwn_attach_post(struct bwn_softc *); +static int bwn_retain_bus_providers(struct bwn_softc *sc); +static void bwn_release_bus_providers(struct bwn_softc *sc); static void bwn_sprom_bugfixes(device_t); static int bwn_init(struct bwn_softc *); static void bwn_parent(struct ieee80211com *); static void bwn_start(struct bwn_softc *); static int bwn_transmit(struct ieee80211com *, struct mbuf *); static int bwn_attach_core(struct bwn_mac *); static int bwn_phy_getinfo(struct bwn_mac *, int); static int bwn_chiptest(struct bwn_mac *); static int bwn_setup_channels(struct bwn_mac *, int, int); static void bwn_shm_ctlword(struct bwn_mac *, uint16_t, uint16_t); static void bwn_addchannels(struct ieee80211_channel [], int, int *, const struct bwn_channelinfo *, const uint8_t []); static int bwn_raw_xmit(struct ieee80211_node *, struct mbuf *, const struct ieee80211_bpf_params *); static void bwn_updateslot(struct ieee80211com *); static void bwn_update_promisc(struct ieee80211com *); static void bwn_wme_init(struct bwn_mac *); static int bwn_wme_update(struct ieee80211com *); static void bwn_wme_clear(struct bwn_softc *); static void bwn_wme_load(struct bwn_mac *); static void bwn_wme_loadparams(struct bwn_mac *, const struct wmeParams *, uint16_t); static void bwn_scan_start(struct ieee80211com *); static void bwn_scan_end(struct ieee80211com *); static void bwn_set_channel(struct ieee80211com *); static struct ieee80211vap *bwn_vap_create(struct ieee80211com *, const char [IFNAMSIZ], int, enum ieee80211_opmode, int, const uint8_t [IEEE80211_ADDR_LEN], const uint8_t [IEEE80211_ADDR_LEN]); static void bwn_vap_delete(struct ieee80211vap *); static void bwn_stop(struct bwn_softc *); +static int bwn_core_forceclk(struct bwn_mac *, bool); static int bwn_core_init(struct bwn_mac *); static void bwn_core_start(struct bwn_mac *); static void bwn_core_exit(struct bwn_mac *); static void bwn_bt_disable(struct bwn_mac *); static int bwn_chip_init(struct bwn_mac *); static void bwn_set_txretry(struct bwn_mac *, int, int); static void bwn_rate_init(struct bwn_mac *); static void bwn_set_phytxctl(struct bwn_mac *); static void bwn_spu_setdelay(struct bwn_mac *, int); static void bwn_bt_enable(struct bwn_mac *); static void bwn_set_macaddr(struct bwn_mac *); static void bwn_crypt_init(struct bwn_mac *); static void bwn_chip_exit(struct bwn_mac *); static int bwn_fw_fillinfo(struct bwn_mac *); static int bwn_fw_loaducode(struct bwn_mac *); static int bwn_gpio_init(struct bwn_mac *); static int bwn_fw_loadinitvals(struct bwn_mac *); static int bwn_phy_init(struct bwn_mac *); static void bwn_set_txantenna(struct bwn_mac *, int); static void bwn_set_opmode(struct bwn_mac *); static void bwn_rate_write(struct bwn_mac *, uint16_t, int); static uint8_t bwn_plcp_getcck(const uint8_t); static uint8_t bwn_plcp_getofdm(const uint8_t); static void bwn_pio_init(struct bwn_mac *); static uint16_t bwn_pio_idx2base(struct bwn_mac *, int); static void bwn_pio_set_txqueue(struct bwn_mac *, struct bwn_pio_txqueue *, int); static void bwn_pio_setupqueue_rx(struct bwn_mac *, struct bwn_pio_rxqueue *, int); static void bwn_destroy_queue_tx(struct bwn_pio_txqueue *); static uint16_t bwn_pio_read_2(struct bwn_mac *, struct bwn_pio_txqueue *, uint16_t); static void bwn_pio_cancel_tx_packets(struct bwn_pio_txqueue *); static int bwn_pio_rx(struct bwn_pio_rxqueue *); static uint8_t bwn_pio_rxeof(struct bwn_pio_rxqueue *); static void bwn_pio_handle_txeof(struct bwn_mac *, const struct bwn_txstatus *); static uint16_t bwn_pio_rx_read_2(struct bwn_pio_rxqueue *, uint16_t); static uint32_t bwn_pio_rx_read_4(struct bwn_pio_rxqueue *, uint16_t); static void bwn_pio_rx_write_2(struct bwn_pio_rxqueue *, uint16_t, uint16_t); static void bwn_pio_rx_write_4(struct bwn_pio_rxqueue *, uint16_t, uint32_t); static int bwn_pio_tx_start(struct bwn_mac *, struct ieee80211_node *, struct mbuf *); static struct bwn_pio_txqueue *bwn_pio_select(struct bwn_mac *, uint8_t); static uint32_t bwn_pio_write_multi_4(struct bwn_mac *, struct bwn_pio_txqueue *, uint32_t, const void *, int); static void bwn_pio_write_4(struct bwn_mac *, struct bwn_pio_txqueue *, uint16_t, uint32_t); static uint16_t bwn_pio_write_multi_2(struct bwn_mac *, struct bwn_pio_txqueue *, uint16_t, const void *, int); static uint16_t bwn_pio_write_mbuf_2(struct bwn_mac *, struct bwn_pio_txqueue *, uint16_t, struct mbuf *); static struct bwn_pio_txqueue *bwn_pio_parse_cookie(struct bwn_mac *, uint16_t, struct bwn_pio_txpkt **); static void bwn_dma_init(struct bwn_mac *); static void bwn_dma_rxdirectfifo(struct bwn_mac *, int, uint8_t); -static int bwn_dma_mask2type(uint64_t); -static uint64_t bwn_dma_mask(struct bwn_mac *); static uint16_t bwn_dma_base(int, int); static void bwn_dma_ringfree(struct bwn_dma_ring **); static void bwn_dma_32_getdesc(struct bwn_dma_ring *, int, struct bwn_dmadesc_generic **, struct bwn_dmadesc_meta **); static void bwn_dma_32_setdesc(struct bwn_dma_ring *, struct bwn_dmadesc_generic *, bus_addr_t, uint16_t, int, int, int); static void bwn_dma_32_start_transfer(struct bwn_dma_ring *, int); static void bwn_dma_32_suspend(struct bwn_dma_ring *); static void bwn_dma_32_resume(struct bwn_dma_ring *); static int bwn_dma_32_get_curslot(struct bwn_dma_ring *); static void bwn_dma_32_set_curslot(struct bwn_dma_ring *, int); static void bwn_dma_64_getdesc(struct bwn_dma_ring *, int, struct bwn_dmadesc_generic **, struct bwn_dmadesc_meta **); static void bwn_dma_64_setdesc(struct bwn_dma_ring *, struct bwn_dmadesc_generic *, bus_addr_t, uint16_t, int, int, int); static void bwn_dma_64_start_transfer(struct bwn_dma_ring *, int); static void bwn_dma_64_suspend(struct bwn_dma_ring *); static void bwn_dma_64_resume(struct bwn_dma_ring *); static int bwn_dma_64_get_curslot(struct bwn_dma_ring *); static void bwn_dma_64_set_curslot(struct bwn_dma_ring *, int); static int bwn_dma_allocringmemory(struct bwn_dma_ring *); static void bwn_dma_setup(struct bwn_dma_ring *); static void bwn_dma_free_ringmemory(struct bwn_dma_ring *); static void bwn_dma_cleanup(struct bwn_dma_ring *); static void bwn_dma_free_descbufs(struct bwn_dma_ring *); static int bwn_dma_tx_reset(struct bwn_mac *, uint16_t, int); static void bwn_dma_rx(struct bwn_dma_ring *); static int bwn_dma_rx_reset(struct bwn_mac *, uint16_t, int); static void bwn_dma_free_descbuf(struct bwn_dma_ring *, struct bwn_dmadesc_meta *); static void bwn_dma_set_redzone(struct bwn_dma_ring *, struct mbuf *); -static int bwn_dma_gettype(struct bwn_mac *); static void bwn_dma_ring_addr(void *, bus_dma_segment_t *, int, int); static int bwn_dma_freeslot(struct bwn_dma_ring *); static int bwn_dma_nextslot(struct bwn_dma_ring *, int); static void bwn_dma_rxeof(struct bwn_dma_ring *, int *); static int bwn_dma_newbuf(struct bwn_dma_ring *, struct bwn_dmadesc_generic *, struct bwn_dmadesc_meta *, int); static void bwn_dma_buf_addr(void *, bus_dma_segment_t *, int, bus_size_t, int); static uint8_t bwn_dma_check_redzone(struct bwn_dma_ring *, struct mbuf *); static void bwn_ratectl_tx_complete(const struct ieee80211_node *, const struct bwn_txstatus *); static void bwn_dma_handle_txeof(struct bwn_mac *, const struct bwn_txstatus *); static int bwn_dma_tx_start(struct bwn_mac *, struct ieee80211_node *, struct mbuf *); static int bwn_dma_getslot(struct bwn_dma_ring *); static struct bwn_dma_ring *bwn_dma_select(struct bwn_mac *, uint8_t); static int bwn_dma_attach(struct bwn_mac *); static struct bwn_dma_ring *bwn_dma_ringsetup(struct bwn_mac *, - int, int, int); + int, int); static struct bwn_dma_ring *bwn_dma_parse_cookie(struct bwn_mac *, const struct bwn_txstatus *, uint16_t, int *); static void bwn_dma_free(struct bwn_mac *); static int bwn_fw_gets(struct bwn_mac *, enum bwn_fwtype); static int bwn_fw_get(struct bwn_mac *, enum bwn_fwtype, const char *, struct bwn_fwfile *); static void bwn_release_firmware(struct bwn_mac *); static void bwn_do_release_fw(struct bwn_fwfile *); static uint16_t bwn_fwcaps_read(struct bwn_mac *); static int bwn_fwinitvals_write(struct bwn_mac *, const struct bwn_fwinitvals *, size_t, size_t); static uint16_t bwn_ant2phy(int); static void bwn_mac_write_bssid(struct bwn_mac *); static void bwn_mac_setfilter(struct bwn_mac *, uint16_t, const uint8_t *); static void bwn_key_dowrite(struct bwn_mac *, uint8_t, uint8_t, const uint8_t *, size_t, const uint8_t *); static void bwn_key_macwrite(struct bwn_mac *, uint8_t, const uint8_t *); static void bwn_key_write(struct bwn_mac *, uint8_t, uint8_t, const uint8_t *); static void bwn_phy_exit(struct bwn_mac *); static void bwn_core_stop(struct bwn_mac *); static int bwn_switch_band(struct bwn_softc *, struct ieee80211_channel *); -static void bwn_phy_reset(struct bwn_mac *); +static int bwn_phy_reset(struct bwn_mac *); static int bwn_newstate(struct ieee80211vap *, enum ieee80211_state, int); static void bwn_set_pretbtt(struct bwn_mac *); static int bwn_intr(void *); static void bwn_intrtask(void *, int); static void bwn_restart(struct bwn_mac *, const char *); static void bwn_intr_ucode_debug(struct bwn_mac *); static void bwn_intr_tbtt_indication(struct bwn_mac *); static void bwn_intr_atim_end(struct bwn_mac *); static void bwn_intr_beacon(struct bwn_mac *); static void bwn_intr_pmq(struct bwn_mac *); static void bwn_intr_noise(struct bwn_mac *); static void bwn_intr_txeof(struct bwn_mac *); static void bwn_hwreset(void *, int); static void bwn_handle_fwpanic(struct bwn_mac *); static void bwn_load_beacon0(struct bwn_mac *); static void bwn_load_beacon1(struct bwn_mac *); static uint32_t bwn_jssi_read(struct bwn_mac *); static void bwn_noise_gensample(struct bwn_mac *); static void bwn_handle_txeof(struct bwn_mac *, const struct bwn_txstatus *); static void bwn_rxeof(struct bwn_mac *, struct mbuf *, const void *); static void bwn_phy_txpower_check(struct bwn_mac *, uint32_t); static int bwn_tx_start(struct bwn_softc *, struct ieee80211_node *, struct mbuf *); static int bwn_tx_isfull(struct bwn_softc *, struct mbuf *); static int bwn_set_txhdr(struct bwn_mac *, struct ieee80211_node *, struct mbuf *, struct bwn_txhdr *, uint16_t); static void bwn_plcp_genhdr(struct bwn_plcp4 *, const uint16_t, const uint8_t); static uint8_t bwn_antenna_sanitize(struct bwn_mac *, uint8_t); static uint8_t bwn_get_fbrate(uint8_t); static void bwn_txpwr(void *, int); static void bwn_tasks(void *); static void bwn_task_15s(struct bwn_mac *); static void bwn_task_30s(struct bwn_mac *); static void bwn_task_60s(struct bwn_mac *); static int bwn_plcp_get_ofdmrate(struct bwn_mac *, struct bwn_plcp6 *, uint8_t); static int bwn_plcp_get_cckrate(struct bwn_mac *, struct bwn_plcp6 *); static void bwn_rx_radiotap(struct bwn_mac *, struct mbuf *, const struct bwn_rxhdr4 *, struct bwn_plcp6 *, int, int, int); static void bwn_tsf_read(struct bwn_mac *, uint64_t *); static void bwn_set_slot_time(struct bwn_mac *, uint16_t); static void bwn_watchdog(void *); static void bwn_dma_stop(struct bwn_mac *); static void bwn_pio_stop(struct bwn_mac *); static void bwn_dma_ringstop(struct bwn_dma_ring **); -static void bwn_led_attach(struct bwn_mac *); +static int bwn_led_attach(struct bwn_mac *); static void bwn_led_newstate(struct bwn_mac *, enum ieee80211_state); static void bwn_led_event(struct bwn_mac *, int); static void bwn_led_blink_start(struct bwn_mac *, int, int); static void bwn_led_blink_next(void *); static void bwn_led_blink_end(void *); static void bwn_rfswitch(void *); static void bwn_rf_turnon(struct bwn_mac *); static void bwn_rf_turnoff(struct bwn_mac *); static void bwn_sysctl_node(struct bwn_softc *); -static struct resource_spec bwn_res_spec_legacy[] = { - { SYS_RES_IRQ, 0, RF_ACTIVE | RF_SHAREABLE }, - { -1, 0, 0 } -}; - -static struct resource_spec bwn_res_spec_msi[] = { - { SYS_RES_IRQ, 1, RF_ACTIVE }, - { -1, 0, 0 } -}; - static const struct bwn_channelinfo bwn_chantable_bg = { .channels = { { 2412, 1, 30 }, { 2417, 2, 30 }, { 2422, 3, 30 }, { 2427, 4, 30 }, { 2432, 5, 30 }, { 2437, 6, 30 }, { 2442, 7, 30 }, { 2447, 8, 30 }, { 2452, 9, 30 }, { 2457, 10, 30 }, { 2462, 11, 30 }, { 2467, 12, 30 }, { 2472, 13, 30 }, { 2484, 14, 30 } }, .nchannels = 14 }; static const struct bwn_channelinfo bwn_chantable_a = { .channels = { { 5170, 34, 30 }, { 5180, 36, 30 }, { 5190, 38, 30 }, { 5200, 40, 30 }, { 5210, 42, 30 }, { 5220, 44, 30 }, { 5230, 46, 30 }, { 5240, 48, 30 }, { 5260, 52, 30 }, { 5280, 56, 30 }, { 5300, 60, 30 }, { 5320, 64, 30 }, { 5500, 100, 30 }, { 5520, 104, 30 }, { 5540, 108, 30 }, { 5560, 112, 30 }, { 5580, 116, 30 }, { 5600, 120, 30 }, { 5620, 124, 30 }, { 5640, 128, 30 }, { 5660, 132, 30 }, { 5680, 136, 30 }, { 5700, 140, 30 }, { 5745, 149, 30 }, { 5765, 153, 30 }, { 5785, 157, 30 }, { 5805, 161, 30 }, { 5825, 165, 30 }, { 5920, 184, 30 }, { 5940, 188, 30 }, { 5960, 192, 30 }, { 5980, 196, 30 }, { 6000, 200, 30 }, { 6020, 204, 30 }, { 6040, 208, 30 }, { 6060, 212, 30 }, { 6080, 216, 30 } }, .nchannels = 37 }; #if 0 static const struct bwn_channelinfo bwn_chantable_n = { .channels = { { 5160, 32, 30 }, { 5170, 34, 30 }, { 5180, 36, 30 }, { 5190, 38, 30 }, { 5200, 40, 30 }, { 5210, 42, 30 }, { 5220, 44, 30 }, { 5230, 46, 30 }, { 5240, 48, 30 }, { 5250, 50, 30 }, { 5260, 52, 30 }, { 5270, 54, 30 }, { 5280, 56, 30 }, { 5290, 58, 30 }, { 5300, 60, 30 }, { 5310, 62, 30 }, { 5320, 64, 30 }, { 5330, 66, 30 }, { 5340, 68, 30 }, { 5350, 70, 30 }, { 5360, 72, 30 }, { 5370, 74, 30 }, { 5380, 76, 30 }, { 5390, 78, 30 }, { 5400, 80, 30 }, { 5410, 82, 30 }, { 5420, 84, 30 }, { 5430, 86, 30 }, { 5440, 88, 30 }, { 5450, 90, 30 }, { 5460, 92, 30 }, { 5470, 94, 30 }, { 5480, 96, 30 }, { 5490, 98, 30 }, { 5500, 100, 30 }, { 5510, 102, 30 }, { 5520, 104, 30 }, { 5530, 106, 30 }, { 5540, 108, 30 }, { 5550, 110, 30 }, { 5560, 112, 30 }, { 5570, 114, 30 }, { 5580, 116, 30 }, { 5590, 118, 30 }, { 5600, 120, 30 }, { 5610, 122, 30 }, { 5620, 124, 30 }, { 5630, 126, 30 }, { 5640, 128, 30 }, { 5650, 130, 30 }, { 5660, 132, 30 }, { 5670, 134, 30 }, { 5680, 136, 30 }, { 5690, 138, 30 }, { 5700, 140, 30 }, { 5710, 142, 30 }, { 5720, 144, 30 }, { 5725, 145, 30 }, { 5730, 146, 30 }, { 5735, 147, 30 }, { 5740, 148, 30 }, { 5745, 149, 30 }, { 5750, 150, 30 }, { 5755, 151, 30 }, { 5760, 152, 30 }, { 5765, 153, 30 }, { 5770, 154, 30 }, { 5775, 155, 30 }, { 5780, 156, 30 }, { 5785, 157, 30 }, { 5790, 158, 30 }, { 5795, 159, 30 }, { 5800, 160, 30 }, { 5805, 161, 30 }, { 5810, 162, 30 }, { 5815, 163, 30 }, { 5820, 164, 30 }, { 5825, 165, 30 }, { 5830, 166, 30 }, { 5840, 168, 30 }, { 5850, 170, 30 }, { 5860, 172, 30 }, { 5870, 174, 30 }, { 5880, 176, 30 }, { 5890, 178, 30 }, { 5900, 180, 30 }, { 5910, 182, 30 }, { 5920, 184, 30 }, { 5930, 186, 30 }, { 5940, 188, 30 }, { 5950, 190, 30 }, { 5960, 192, 30 }, { 5970, 194, 30 }, { 5980, 196, 30 }, { 5990, 198, 30 }, { 6000, 200, 30 }, { 6010, 202, 30 }, { 6020, 204, 30 }, { 6030, 206, 30 }, { 6040, 208, 30 }, { 6050, 210, 30 }, { 6060, 212, 30 }, { 6070, 214, 30 }, { 6080, 216, 30 }, { 6090, 218, 30 }, { 6100, 220, 30 }, { 6110, 222, 30 }, { 6120, 224, 30 }, { 6130, 226, 30 }, { 6140, 228, 30 } }, .nchannels = 110 }; #endif #define VENDOR_LED_ACT(vendor) \ { \ .vid = PCI_VENDOR_##vendor, \ .led_act = { BWN_VENDOR_LED_ACT_##vendor } \ } static const struct { uint16_t vid; uint8_t led_act[BWN_LED_MAX]; } bwn_vendor_led_act[] = { - VENDOR_LED_ACT(COMPAQ), + VENDOR_LED_ACT(HP_COMPAQ), VENDOR_LED_ACT(ASUSTEK) }; static const uint8_t bwn_default_led_act[BWN_LED_MAX] = { BWN_VENDOR_LED_ACT_DEFAULT }; #undef VENDOR_LED_ACT +static const char *bwn_led_vars[] = { + BHND_NVAR_LEDBH0, + BHND_NVAR_LEDBH1, + BHND_NVAR_LEDBH2, + BHND_NVAR_LEDBH3 +}; + static const struct { int on_dur; int off_dur; } bwn_led_duration[109] = { [0] = { 400, 100 }, [2] = { 150, 75 }, [4] = { 90, 45 }, [11] = { 66, 34 }, [12] = { 53, 26 }, [18] = { 42, 21 }, [22] = { 35, 17 }, [24] = { 32, 16 }, [36] = { 21, 10 }, [48] = { 16, 8 }, [72] = { 11, 5 }, [96] = { 9, 4 }, [108] = { 7, 3 } }; static const uint16_t bwn_wme_shm_offsets[] = { [0] = BWN_WME_BESTEFFORT, [1] = BWN_WME_BACKGROUND, [2] = BWN_WME_VOICE, [3] = BWN_WME_VIDEO, }; -static const struct siba_devid bwn_devs[] = { - SIBA_DEV(BROADCOM, 80211, 5, "Revision 5"), - SIBA_DEV(BROADCOM, 80211, 6, "Revision 6"), - SIBA_DEV(BROADCOM, 80211, 7, "Revision 7"), - SIBA_DEV(BROADCOM, 80211, 9, "Revision 9"), - SIBA_DEV(BROADCOM, 80211, 10, "Revision 10"), - SIBA_DEV(BROADCOM, 80211, 11, "Revision 11"), - SIBA_DEV(BROADCOM, 80211, 12, "Revision 12"), - SIBA_DEV(BROADCOM, 80211, 13, "Revision 13"), - SIBA_DEV(BROADCOM, 80211, 15, "Revision 15"), - SIBA_DEV(BROADCOM, 80211, 16, "Revision 16") +/* Supported D11 core revisions */ +#define BWN_DEV(_hwrev) {{ \ + BHND_MATCH_CORE(BHND_MFGID_BCM, BHND_COREID_D11), \ + BHND_MATCH_CORE_REV(_hwrev), \ +}} +static const struct bhnd_device bwn_devices[] = { + BWN_DEV(HWREV_RANGE(5, 16)), + BWN_DEV(HWREV_EQ(23)), + BHND_DEVICE_END }; -static const struct bwn_bus_ops * -bwn_get_bus_ops(device_t dev) -{ -#if BWN_USE_SIBA - return (NULL); -#else - devclass_t bus_cls; +/* D11 quirks when bridged via a PCI host bridge core */ +static const struct bhnd_device_quirk pci_bridge_quirks[] = { + BHND_CORE_QUIRK (HWREV_LTE(10), BWN_QUIRK_UCODE_SLOWCLOCK_WAR), + BHND_DEVICE_QUIRK_END +}; - bus_cls = device_get_devclass(device_get_parent(dev)); - if (bus_cls == devclass_find("bhnd")) - return (&bwn_bhnd_bus_ops); - else - return (&bwn_siba_bus_ops); -#endif -} +/* D11 quirks when bridged via a PCMCIA host bridge core */ +static const struct bhnd_device_quirk pcmcia_bridge_quirks[] = { + BHND_CORE_QUIRK (HWREV_ANY, BWN_QUIRK_NODMA), + BHND_DEVICE_QUIRK_END +}; +/* Host bridge cores for which D11 quirk flags should be applied */ +static const struct bhnd_device bridge_devices[] = { + BHND_DEVICE(BCM, PCI, NULL, pci_bridge_quirks), + BHND_DEVICE(BCM, PCMCIA, NULL, pcmcia_bridge_quirks), + BHND_DEVICE_END +}; + static int bwn_probe(device_t dev) { - struct bwn_softc *sc; - int i; + const struct bhnd_device *id; - sc = device_get_softc(dev); - sc->sc_bus_ops = bwn_get_bus_ops(dev); + id = bhnd_device_lookup(dev, bwn_devices, sizeof(bwn_devices[0])); + if (id == NULL) + return (ENXIO); - for (i = 0; i < nitems(bwn_devs); i++) { - if (siba_get_vendor(dev) == bwn_devs[i].sd_vendor && - siba_get_device(dev) == bwn_devs[i].sd_device && - siba_get_revid(dev) == bwn_devs[i].sd_rev) - return (BUS_PROBE_DEFAULT); - } - - return (ENXIO); + bhnd_set_default_core_desc(dev); + return (BUS_PROBE_DEFAULT); } -int +static int bwn_attach(device_t dev) { - struct bwn_mac *mac; - struct bwn_softc *sc = device_get_softc(dev); - int error, i, msic, reg; + struct bwn_mac *mac; + struct bwn_softc *sc; + device_t parent, hostb; + char chip_name[BHND_CHIPID_MAX_NAMELEN]; + int error; + sc = device_get_softc(dev); sc->sc_dev = dev; #ifdef BWN_DEBUG sc->sc_debug = bwn_debug; #endif - sc->sc_bus_ops = bwn_get_bus_ops(dev); - if ((error = BWN_BUS_OPS_ATTACH(dev))) { - device_printf(sc->sc_dev, - "bus-specific initialization failed (%d)\n", error); + mac = NULL; + + /* Determine the driver quirks applicable to this device, including any + * quirks specific to the bus host bridge core (if any) */ + sc->sc_quirks = bhnd_device_quirks(dev, bwn_devices, + sizeof(bwn_devices[0])); + + parent = device_get_parent(dev); + if ((hostb = bhnd_bus_find_hostb_device(parent)) != NULL) { + sc->sc_quirks |= bhnd_device_quirks(hostb, bridge_devices, + sizeof(bridge_devices[0])); + } + + /* DMA explicitly disabled? */ + if (!bwn_usedma) + sc->sc_quirks |= BWN_QUIRK_NODMA; + + /* Fetch our chip identification and board info */ + sc->sc_cid = *bhnd_get_chipid(dev); + if ((error = bhnd_read_board_info(dev, &sc->sc_board_info))) { + device_printf(sc->sc_dev, "couldn't read board info\n"); return (error); } + /* Allocate our D11 register block and PMU state */ + sc->sc_mem_rid = 0; + sc->sc_mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, + &sc->sc_mem_rid, RF_ACTIVE); + if (sc->sc_mem_res == NULL) { + device_printf(sc->sc_dev, "couldn't allocate registers\n"); + return (error); + } + + if ((error = bhnd_alloc_pmu(sc->sc_dev))) { + bus_release_resource(sc->sc_dev, SYS_RES_MEMORY, + sc->sc_mem_rid, sc->sc_mem_res); + return (error); + } + + /* Retain references to all required bus service providers */ + if ((error = bwn_retain_bus_providers(sc))) + goto fail; + + /* Fetch mask of available antennas */ + error = bhnd_nvram_getvar_uint8(sc->sc_dev, BHND_NVAR_AA2G, + &sc->sc_ant2g); + if (error) { + device_printf(sc->sc_dev, "error determining 2GHz antenna " + "availability from NVRAM: %d\n", error); + goto fail; + } + + error = bhnd_nvram_getvar_uint8(sc->sc_dev, BHND_NVAR_AA5G, + &sc->sc_ant5g); + if (error) { + device_printf(sc->sc_dev, "error determining 5GHz antenna " + "availability from NVRAM: %d\n", error); + goto fail; + } + if ((sc->sc_flags & BWN_FLAG_ATTACHED) == 0) { bwn_attach_pre(sc); bwn_sprom_bugfixes(dev); sc->sc_flags |= BWN_FLAG_ATTACHED; } - if (!TAILQ_EMPTY(&sc->sc_maclist)) { - if (siba_get_pci_device(dev) != 0x4313 && - siba_get_pci_device(dev) != 0x431a && - siba_get_pci_device(dev) != 0x4321) { - device_printf(sc->sc_dev, - "skip 802.11 cores\n"); - return (ENODEV); - } - } - mac = malloc(sizeof(*mac), M_DEVBUF, M_WAITOK | M_ZERO); mac->mac_sc = sc; mac->mac_status = BWN_MAC_STATUS_UNINIT; if (bwn_bfp != 0) mac->mac_flags |= BWN_MAC_FLAG_BADFRAME_PREEMP; TASK_INIT(&mac->mac_hwreset, 0, bwn_hwreset, mac); TASK_INIT(&mac->mac_intrtask, 0, bwn_intrtask, mac); TASK_INIT(&mac->mac_txpower, 0, bwn_txpwr, mac); error = bwn_attach_core(mac); if (error) - goto fail0; - bwn_led_attach(mac); + goto fail; + error = bwn_led_attach(mac); + if (error) + goto fail; - device_printf(sc->sc_dev, "WLAN (chipid %#x rev %u) " + bhnd_format_chip_id(chip_name, sizeof(chip_name), sc->sc_cid.chip_id); + device_printf(sc->sc_dev, "WLAN (%s rev %u) " "PHY (analog %d type %d rev %d) RADIO (manuf %#x ver %#x rev %d)\n", - siba_get_chipid(sc->sc_dev), siba_get_revid(sc->sc_dev), - mac->mac_phy.analog, mac->mac_phy.type, mac->mac_phy.rev, - mac->mac_phy.rf_manuf, mac->mac_phy.rf_ver, - mac->mac_phy.rf_rev); + chip_name, bhnd_get_hwrev(sc->sc_dev), mac->mac_phy.analog, + mac->mac_phy.type, mac->mac_phy.rev, mac->mac_phy.rf_manuf, + mac->mac_phy.rf_ver, mac->mac_phy.rf_rev); if (mac->mac_flags & BWN_MAC_FLAG_DMA) - device_printf(sc->sc_dev, "DMA (%d bits)\n", - mac->mac_method.dma.dmatype); + device_printf(sc->sc_dev, "DMA (%d bits)\n", mac->mac_dmatype); else device_printf(sc->sc_dev, "PIO\n"); #ifdef BWN_GPL_PHY device_printf(sc->sc_dev, "Note: compiled with BWN_GPL_PHY; includes GPLv2 code\n"); #endif - /* - * setup PCI resources and interrupt. - */ - if (pci_find_cap(dev, PCIY_EXPRESS, ®) == 0) { - msic = pci_msi_count(dev); - if (bootverbose) - device_printf(sc->sc_dev, "MSI count : %d\n", msic); - } else - msic = 0; + mac->mac_rid_irq = 0; + mac->mac_res_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, + &mac->mac_rid_irq, RF_ACTIVE | RF_SHAREABLE); - mac->mac_intr_spec = bwn_res_spec_legacy; - if (msic == BWN_MSI_MESSAGES && bwn_msi_disable == 0) { - if (pci_alloc_msi(dev, &msic) == 0) { - device_printf(sc->sc_dev, - "Using %d MSI messages\n", msic); - mac->mac_intr_spec = bwn_res_spec_msi; - mac->mac_msi = 1; - } + if (mac->mac_res_irq == NULL) { + device_printf(sc->sc_dev, "couldn't allocate IRQ resource\n"); + error = ENXIO; + goto fail; } - error = bus_alloc_resources(dev, mac->mac_intr_spec, - mac->mac_res_irq); - if (error) { - device_printf(sc->sc_dev, - "couldn't allocate IRQ resources (%d)\n", error); - goto fail1; + error = bus_setup_intr(dev, mac->mac_res_irq, + INTR_TYPE_NET | INTR_MPSAFE, bwn_intr, NULL, mac, + &mac->mac_intrhand); + if (error != 0) { + device_printf(sc->sc_dev, "couldn't setup interrupt (%d)\n", + error); + goto fail; } - if (mac->mac_msi == 0) - error = bus_setup_intr(dev, mac->mac_res_irq[0], - INTR_TYPE_NET | INTR_MPSAFE, bwn_intr, NULL, mac, - &mac->mac_intrhand[0]); - else { - for (i = 0; i < BWN_MSI_MESSAGES; i++) { - error = bus_setup_intr(dev, mac->mac_res_irq[i], - INTR_TYPE_NET | INTR_MPSAFE, bwn_intr, NULL, mac, - &mac->mac_intrhand[i]); - if (error != 0) { - device_printf(sc->sc_dev, - "couldn't setup interrupt (%d)\n", error); - break; - } - } - } - TAILQ_INSERT_TAIL(&sc->sc_maclist, mac, mac_list); /* * calls attach-post routine */ if ((sc->sc_flags & BWN_FLAG_ATTACHED) != 0) bwn_attach_post(sc); return (0); -fail1: - if (msic == BWN_MSI_MESSAGES && bwn_msi_disable == 0) - pci_release_msi(dev); -fail0: - BWN_BUS_OPS_DETACH(dev); +fail: + if (mac != NULL && mac->mac_res_irq != NULL) { + bus_release_resource(dev, SYS_RES_IRQ, mac->mac_rid_irq, + mac->mac_res_irq); + } + free(mac, M_DEVBUF); + bhnd_release_pmu(dev); + bwn_release_bus_providers(sc); + + if (sc->sc_mem_res != NULL) { + bus_release_resource(sc->sc_dev, SYS_RES_MEMORY, + sc->sc_mem_rid, sc->sc_mem_res); + } + return (error); } static int -bwn_is_valid_ether_addr(uint8_t *addr) +bwn_retain_bus_providers(struct bwn_softc *sc) { - char zero_addr[6] = { 0, 0, 0, 0, 0, 0 }; + struct chipc_caps *ccaps; - if ((addr[0] & 1) || (!bcmp(addr, zero_addr, ETHER_ADDR_LEN))) - return (FALSE); + sc->sc_chipc = bhnd_retain_provider(sc->sc_dev, BHND_SERVICE_CHIPC); + if (sc->sc_chipc == NULL) { + device_printf(sc->sc_dev, "ChipCommon device not found\n"); + goto failed; + } - return (TRUE); + ccaps = BHND_CHIPC_GET_CAPS(sc->sc_chipc); + + sc->sc_gpio = bhnd_retain_provider(sc->sc_dev, BHND_SERVICE_GPIO); + if (sc->sc_gpio == NULL) { + device_printf(sc->sc_dev, "GPIO device not found\n"); + goto failed; + } + + if (ccaps->pmu) { + sc->sc_pmu = bhnd_retain_provider(sc->sc_dev, BHND_SERVICE_PMU); + if (sc->sc_pmu == NULL) { + device_printf(sc->sc_dev, "PMU device not found\n"); + goto failed; + } + } + + return (0); + +failed: + bwn_release_bus_providers(sc); + return (ENXIO); } +static void +bwn_release_bus_providers(struct bwn_softc *sc) +{ +#define BWN_RELEASE_PROV(_sc, _prov, _service) do { \ + if ((_sc)-> _prov != NULL) { \ + bhnd_release_provider((_sc)->sc_dev, (_sc)-> _prov, \ + (_service)); \ + (_sc)-> _prov = NULL; \ + } \ +} while (0) + + BWN_RELEASE_PROV(sc, sc_chipc, BHND_SERVICE_CHIPC); + BWN_RELEASE_PROV(sc, sc_gpio, BHND_SERVICE_GPIO); + BWN_RELEASE_PROV(sc, sc_pmu, BHND_SERVICE_PMU); + +#undef BWN_RELEASE_PROV +} + static int bwn_attach_post(struct bwn_softc *sc) { - struct ieee80211com *ic = &sc->sc_ic; + struct ieee80211com *ic; + const char *mac_varname; + u_int core_unit; + int error; + ic = &sc->sc_ic; + ic->ic_softc = sc; ic->ic_name = device_get_nameunit(sc->sc_dev); /* XXX not right but it's not used anywhere important */ ic->ic_phytype = IEEE80211_T_OFDM; ic->ic_opmode = IEEE80211_M_STA; ic->ic_caps = IEEE80211_C_STA /* station mode supported */ | IEEE80211_C_MONITOR /* monitor mode */ | IEEE80211_C_AHDEMO /* adhoc demo mode */ | IEEE80211_C_SHPREAMBLE /* short preamble supported */ | IEEE80211_C_SHSLOT /* short slot time supported */ | IEEE80211_C_WME /* WME/WMM supported */ | IEEE80211_C_WPA /* capable of WPA1+WPA2 */ #if 0 | IEEE80211_C_BGSCAN /* capable of bg scanning */ #endif | IEEE80211_C_TXPMGT /* capable of txpow mgt */ ; ic->ic_flags_ext |= IEEE80211_FEXT_SWBMISS; /* s/w bmiss */ - IEEE80211_ADDR_COPY(ic->ic_macaddr, - bwn_is_valid_ether_addr(siba_sprom_get_mac_80211a(sc->sc_dev)) ? - siba_sprom_get_mac_80211a(sc->sc_dev) : - siba_sprom_get_mac_80211bg(sc->sc_dev)); + /* Determine the NVRAM variable containing our MAC address */ + core_unit = bhnd_get_core_unit(sc->sc_dev); + mac_varname = NULL; + if (sc->sc_board_info.board_srom_rev <= 2) { + if (core_unit == 0) { + mac_varname = BHND_NVAR_IL0MACADDR; + } else if (core_unit == 1) { + mac_varname = BHND_NVAR_ET1MACADDR; + } + } else { + if (core_unit == 0) { + mac_varname = BHND_NVAR_MACADDR; + } + } + if (mac_varname == NULL) { + device_printf(sc->sc_dev, "missing MAC address variable for " + "D11 core %u", core_unit); + return (ENXIO); + } + + /* Read the MAC address from NVRAM */ + error = bhnd_nvram_getvar_array(sc->sc_dev, mac_varname, ic->ic_macaddr, + sizeof(ic->ic_macaddr), BHND_NVRAM_TYPE_UINT8_ARRAY); + if (error) { + device_printf(sc->sc_dev, "error reading %s: %d\n", mac_varname, + error); + return (error); + } + /* call MI attach routine. */ ieee80211_ifattach(ic); ic->ic_headroom = sizeof(struct bwn_txhdr); /* override default methods */ ic->ic_raw_xmit = bwn_raw_xmit; ic->ic_updateslot = bwn_updateslot; ic->ic_update_promisc = bwn_update_promisc; ic->ic_wme.wme_update = bwn_wme_update; ic->ic_scan_start = bwn_scan_start; ic->ic_scan_end = bwn_scan_end; ic->ic_set_channel = bwn_set_channel; ic->ic_vap_create = bwn_vap_create; ic->ic_vap_delete = bwn_vap_delete; ic->ic_transmit = bwn_transmit; ic->ic_parent = bwn_parent; ieee80211_radiotap_attach(ic, &sc->sc_tx_th.wt_ihdr, sizeof(sc->sc_tx_th), BWN_TX_RADIOTAP_PRESENT, &sc->sc_rx_th.wr_ihdr, sizeof(sc->sc_rx_th), BWN_RX_RADIOTAP_PRESENT); bwn_sysctl_node(sc); if (bootverbose) ieee80211_announce(ic); return (0); } static void bwn_phy_detach(struct bwn_mac *mac) { if (mac->mac_phy.detach != NULL) mac->mac_phy.detach(mac); } -int +static int bwn_detach(device_t dev) { struct bwn_softc *sc = device_get_softc(dev); struct bwn_mac *mac = sc->sc_curmac; struct ieee80211com *ic = &sc->sc_ic; - int i; sc->sc_flags |= BWN_FLAG_INVALID; if (device_is_attached(sc->sc_dev)) { BWN_LOCK(sc); bwn_stop(sc); BWN_UNLOCK(sc); bwn_dma_free(mac); callout_drain(&sc->sc_led_blink_ch); callout_drain(&sc->sc_rfswitch_ch); callout_drain(&sc->sc_task_ch); callout_drain(&sc->sc_watchdog_ch); bwn_phy_detach(mac); ieee80211_draintask(ic, &mac->mac_hwreset); ieee80211_draintask(ic, &mac->mac_txpower); ieee80211_ifdetach(ic); } taskqueue_drain(sc->sc_tq, &mac->mac_intrtask); taskqueue_free(sc->sc_tq); - for (i = 0; i < BWN_MSI_MESSAGES; i++) { - if (mac->mac_intrhand[i] != NULL) { - bus_teardown_intr(dev, mac->mac_res_irq[i], - mac->mac_intrhand[i]); - mac->mac_intrhand[i] = NULL; - } + if (mac->mac_intrhand != NULL) { + bus_teardown_intr(dev, mac->mac_res_irq, mac->mac_intrhand); + mac->mac_intrhand = NULL; } - bus_release_resources(dev, mac->mac_intr_spec, mac->mac_res_irq); - if (mac->mac_msi != 0) - pci_release_msi(dev); + + bhnd_release_pmu(dev); + bus_release_resource(dev, SYS_RES_MEMORY, sc->sc_mem_rid, + sc->sc_mem_res); + bus_release_resource(dev, SYS_RES_IRQ, mac->mac_rid_irq, + mac->mac_res_irq); mbufq_drain(&sc->sc_snd); bwn_release_firmware(mac); BWN_LOCK_DESTROY(sc); - BWN_BUS_OPS_DETACH(dev); + + bwn_release_bus_providers(sc); + return (0); } static void bwn_attach_pre(struct bwn_softc *sc) { BWN_LOCK_INIT(sc); TAILQ_INIT(&sc->sc_maclist); callout_init_mtx(&sc->sc_rfswitch_ch, &sc->sc_mtx, 0); callout_init_mtx(&sc->sc_task_ch, &sc->sc_mtx, 0); callout_init_mtx(&sc->sc_watchdog_ch, &sc->sc_mtx, 0); mbufq_init(&sc->sc_snd, ifqmaxlen); sc->sc_tq = taskqueue_create_fast("bwn_taskq", M_NOWAIT, taskqueue_thread_enqueue, &sc->sc_tq); taskqueue_start_threads(&sc->sc_tq, 1, PI_NET, "%s taskq", device_get_nameunit(sc->sc_dev)); } static void bwn_sprom_bugfixes(device_t dev) { -#define BWN_ISDEV(_vendor, _device, _subvendor, _subdevice) \ - ((siba_get_pci_vendor(dev) == PCI_VENDOR_##_vendor) && \ - (siba_get_pci_device(dev) == _device) && \ - (siba_get_pci_subvendor(dev) == PCI_VENDOR_##_subvendor) && \ - (siba_get_pci_subdevice(dev) == _subdevice)) + struct bwn_softc *sc = device_get_softc(dev); - if (siba_get_pci_subvendor(dev) == PCI_VENDOR_APPLE && - siba_get_pci_subdevice(dev) == 0x4e && - siba_get_pci_revid(dev) > 0x40) - siba_sprom_set_bf_lo(dev, - siba_sprom_get_bf_lo(dev) | BWN_BFL_PACTRL); - if (siba_get_pci_subvendor(dev) == SIBA_BOARDVENDOR_DELL && - siba_get_chipid(dev) == 0x4301 && siba_get_pci_revid(dev) == 0x74) - siba_sprom_set_bf_lo(dev, - siba_sprom_get_bf_lo(dev) | BWN_BFL_BTCOEXIST); - if (siba_get_type(dev) == SIBA_TYPE_PCI) { - if (BWN_ISDEV(BROADCOM, 0x4318, ASUSTEK, 0x100f) || - BWN_ISDEV(BROADCOM, 0x4320, DELL, 0x0003) || - BWN_ISDEV(BROADCOM, 0x4320, HP, 0x12f8) || - BWN_ISDEV(BROADCOM, 0x4320, LINKSYS, 0x0013) || - BWN_ISDEV(BROADCOM, 0x4320, LINKSYS, 0x0014) || - BWN_ISDEV(BROADCOM, 0x4320, LINKSYS, 0x0015) || - BWN_ISDEV(BROADCOM, 0x4320, MOTOROLA, 0x7010)) - siba_sprom_set_bf_lo(dev, - siba_sprom_get_bf_lo(dev) & ~BWN_BFL_BTCOEXIST); - } +#define BWN_ISDEV(_device, _subvendor, _subdevice) \ + ((sc->sc_board_info.board_devid == PCI_DEVID_##_device) && \ + (sc->sc_board_info.board_vendor == PCI_VENDOR_##_subvendor) && \ + (sc->sc_board_info.board_type == _subdevice)) + + /* A subset of Apple Airport Extreme (BCM4306 rev 2) devices + * were programmed with a missing PACTRL boardflag */ + if (sc->sc_board_info.board_vendor == PCI_VENDOR_APPLE && + sc->sc_board_info.board_type == 0x4e && + sc->sc_board_info.board_rev > 0x40) + sc->sc_board_info.board_flags |= BHND_BFL_PACTRL; + + if (BWN_ISDEV(BCM4318_D11G, ASUSTEK, 0x100f) || + BWN_ISDEV(BCM4306_D11G, DELL, 0x0003) || + BWN_ISDEV(BCM4306_D11G, HP, 0x12f8) || + BWN_ISDEV(BCM4306_D11G, LINKSYS, 0x0013) || + BWN_ISDEV(BCM4306_D11G, LINKSYS, 0x0014) || + BWN_ISDEV(BCM4306_D11G, LINKSYS, 0x0015) || + BWN_ISDEV(BCM4306_D11G, MOTOROLA, 0x7010)) + sc->sc_board_info.board_flags &= ~BHND_BFL_BTCOEX; #undef BWN_ISDEV } static void bwn_parent(struct ieee80211com *ic) { struct bwn_softc *sc = ic->ic_softc; int startall = 0; BWN_LOCK(sc); if (ic->ic_nrunning > 0) { if ((sc->sc_flags & BWN_FLAG_RUNNING) == 0) { bwn_init(sc); startall = 1; } else bwn_update_promisc(ic); } else if (sc->sc_flags & BWN_FLAG_RUNNING) bwn_stop(sc); BWN_UNLOCK(sc); if (startall) ieee80211_start_all(ic); } static int bwn_transmit(struct ieee80211com *ic, struct mbuf *m) { struct bwn_softc *sc = ic->ic_softc; int error; BWN_LOCK(sc); if ((sc->sc_flags & BWN_FLAG_RUNNING) == 0) { BWN_UNLOCK(sc); return (ENXIO); } error = mbufq_enqueue(&sc->sc_snd, m); if (error) { BWN_UNLOCK(sc); return (error); } bwn_start(sc); BWN_UNLOCK(sc); return (0); } static void bwn_start(struct bwn_softc *sc) { struct bwn_mac *mac = sc->sc_curmac; struct ieee80211_frame *wh; struct ieee80211_node *ni; struct ieee80211_key *k; struct mbuf *m; BWN_ASSERT_LOCKED(sc); if ((sc->sc_flags & BWN_FLAG_RUNNING) == 0 || mac == NULL || mac->mac_status < BWN_MAC_STATUS_STARTED) return; while ((m = mbufq_dequeue(&sc->sc_snd)) != NULL) { if (bwn_tx_isfull(sc, m)) break; ni = (struct ieee80211_node *) m->m_pkthdr.rcvif; if (ni == NULL) { device_printf(sc->sc_dev, "unexpected NULL ni\n"); m_freem(m); counter_u64_add(sc->sc_ic.ic_oerrors, 1); continue; } wh = mtod(m, struct ieee80211_frame *); if (wh->i_fc[1] & IEEE80211_FC1_PROTECTED) { k = ieee80211_crypto_encap(ni, m); if (k == NULL) { if_inc_counter(ni->ni_vap->iv_ifp, IFCOUNTER_OERRORS, 1); ieee80211_free_node(ni); m_freem(m); continue; } } wh = NULL; /* Catch any invalid use */ if (bwn_tx_start(sc, ni, m) != 0) { if (ni != NULL) { if_inc_counter(ni->ni_vap->iv_ifp, IFCOUNTER_OERRORS, 1); ieee80211_free_node(ni); } continue; } sc->sc_watchdog_timer = 5; } } static int bwn_tx_isfull(struct bwn_softc *sc, struct mbuf *m) { struct bwn_dma_ring *dr; struct bwn_mac *mac = sc->sc_curmac; struct bwn_pio_txqueue *tq; int pktlen = roundup(m->m_pkthdr.len + BWN_HDRSIZE(mac), 4); BWN_ASSERT_LOCKED(sc); if (mac->mac_flags & BWN_MAC_FLAG_DMA) { dr = bwn_dma_select(mac, M_WME_GETAC(m)); if (dr->dr_stop == 1 || bwn_dma_freeslot(dr) < BWN_TX_SLOTS_PER_FRAME) { dr->dr_stop = 1; goto full; } } else { tq = bwn_pio_select(mac, M_WME_GETAC(m)); if (tq->tq_free == 0 || pktlen > tq->tq_size || pktlen > (tq->tq_size - tq->tq_used)) goto full; } return (0); full: mbufq_prepend(&sc->sc_snd, m); return (1); } static int bwn_tx_start(struct bwn_softc *sc, struct ieee80211_node *ni, struct mbuf *m) { struct bwn_mac *mac = sc->sc_curmac; int error; BWN_ASSERT_LOCKED(sc); if (m->m_pkthdr.len < IEEE80211_MIN_LEN || mac == NULL) { m_freem(m); return (ENXIO); } error = (mac->mac_flags & BWN_MAC_FLAG_DMA) ? bwn_dma_tx_start(mac, ni, m) : bwn_pio_tx_start(mac, ni, m); if (error) { m_freem(m); return (error); } return (0); } static int bwn_pio_tx_start(struct bwn_mac *mac, struct ieee80211_node *ni, struct mbuf *m) { struct bwn_pio_txpkt *tp; struct bwn_pio_txqueue *tq = bwn_pio_select(mac, M_WME_GETAC(m)); struct bwn_softc *sc = mac->mac_sc; struct bwn_txhdr txhdr; struct mbuf *m_new; uint32_t ctl32; int error; uint16_t ctl16; BWN_ASSERT_LOCKED(sc); /* XXX TODO send packets after DTIM */ KASSERT(!TAILQ_EMPTY(&tq->tq_pktlist), ("%s: fail", __func__)); tp = TAILQ_FIRST(&tq->tq_pktlist); tp->tp_ni = ni; tp->tp_m = m; error = bwn_set_txhdr(mac, ni, m, &txhdr, BWN_PIO_COOKIE(tq, tp)); if (error) { device_printf(sc->sc_dev, "tx fail\n"); return (error); } TAILQ_REMOVE(&tq->tq_pktlist, tp, tp_list); tq->tq_used += roundup(m->m_pkthdr.len + BWN_HDRSIZE(mac), 4); tq->tq_free--; - if (siba_get_revid(sc->sc_dev) >= 8) { + if (bhnd_get_hwrev(sc->sc_dev) >= 8) { /* * XXX please removes m_defrag(9) */ m_new = m_defrag(m, M_NOWAIT); if (m_new == NULL) { device_printf(sc->sc_dev, "%s: can't defrag TX buffer\n", __func__); return (ENOBUFS); } if (m_new->m_next != NULL) device_printf(sc->sc_dev, "TODO: fragmented packets for PIO\n"); tp->tp_m = m_new; /* send HEADER */ ctl32 = bwn_pio_write_multi_4(mac, tq, (BWN_PIO_READ_4(mac, tq, BWN_PIO8_TXCTL) | BWN_PIO8_TXCTL_FRAMEREADY) & ~BWN_PIO8_TXCTL_EOF, (const uint8_t *)&txhdr, BWN_HDRSIZE(mac)); /* send BODY */ ctl32 = bwn_pio_write_multi_4(mac, tq, ctl32, mtod(m_new, const void *), m_new->m_pkthdr.len); bwn_pio_write_4(mac, tq, BWN_PIO_TXCTL, ctl32 | BWN_PIO8_TXCTL_EOF); } else { ctl16 = bwn_pio_write_multi_2(mac, tq, (bwn_pio_read_2(mac, tq, BWN_PIO_TXCTL) | BWN_PIO_TXCTL_FRAMEREADY) & ~BWN_PIO_TXCTL_EOF, (const uint8_t *)&txhdr, BWN_HDRSIZE(mac)); ctl16 = bwn_pio_write_mbuf_2(mac, tq, ctl16, m); BWN_PIO_WRITE_2(mac, tq, BWN_PIO_TXCTL, ctl16 | BWN_PIO_TXCTL_EOF); } return (0); } static struct bwn_pio_txqueue * bwn_pio_select(struct bwn_mac *mac, uint8_t prio) { if ((mac->mac_flags & BWN_MAC_FLAG_WME) == 0) return (&mac->mac_method.pio.wme[WME_AC_BE]); switch (prio) { case 0: return (&mac->mac_method.pio.wme[WME_AC_BE]); case 1: return (&mac->mac_method.pio.wme[WME_AC_BK]); case 2: return (&mac->mac_method.pio.wme[WME_AC_VI]); case 3: return (&mac->mac_method.pio.wme[WME_AC_VO]); } KASSERT(0 == 1, ("%s:%d: fail", __func__, __LINE__)); return (NULL); } static int bwn_dma_tx_start(struct bwn_mac *mac, struct ieee80211_node *ni, struct mbuf *m) { #define BWN_GET_TXHDRCACHE(slot) \ &(txhdr_cache[(slot / BWN_TX_SLOTS_PER_FRAME) * BWN_HDRSIZE(mac)]) struct bwn_dma *dma = &mac->mac_method.dma; struct bwn_dma_ring *dr = bwn_dma_select(mac, M_WME_GETAC(m)); struct bwn_dmadesc_generic *desc; struct bwn_dmadesc_meta *mt; struct bwn_softc *sc = mac->mac_sc; uint8_t *txhdr_cache = (uint8_t *)dr->dr_txhdr_cache; int error, slot, backup[2] = { dr->dr_curslot, dr->dr_usedslot }; BWN_ASSERT_LOCKED(sc); KASSERT(!dr->dr_stop, ("%s:%d: fail", __func__, __LINE__)); /* XXX send after DTIM */ slot = bwn_dma_getslot(dr); dr->getdesc(dr, slot, &desc, &mt); KASSERT(mt->mt_txtype == BWN_DMADESC_METATYPE_HEADER, ("%s:%d: fail", __func__, __LINE__)); error = bwn_set_txhdr(dr->dr_mac, ni, m, (struct bwn_txhdr *)BWN_GET_TXHDRCACHE(slot), BWN_DMA_COOKIE(dr, slot)); if (error) goto fail; error = bus_dmamap_load(dr->dr_txring_dtag, mt->mt_dmap, BWN_GET_TXHDRCACHE(slot), BWN_HDRSIZE(mac), bwn_dma_ring_addr, &mt->mt_paddr, BUS_DMA_NOWAIT); if (error) { device_printf(sc->sc_dev, "%s: can't load TX buffer (1) %d\n", __func__, error); goto fail; } bus_dmamap_sync(dr->dr_txring_dtag, mt->mt_dmap, BUS_DMASYNC_PREWRITE); dr->setdesc(dr, desc, mt->mt_paddr, BWN_HDRSIZE(mac), 1, 0, 0); bus_dmamap_sync(dr->dr_ring_dtag, dr->dr_ring_dmap, BUS_DMASYNC_PREWRITE); slot = bwn_dma_getslot(dr); dr->getdesc(dr, slot, &desc, &mt); KASSERT(mt->mt_txtype == BWN_DMADESC_METATYPE_BODY && mt->mt_islast == 1, ("%s:%d: fail", __func__, __LINE__)); mt->mt_m = m; mt->mt_ni = ni; error = bus_dmamap_load_mbuf(dma->txbuf_dtag, mt->mt_dmap, m, bwn_dma_buf_addr, &mt->mt_paddr, BUS_DMA_NOWAIT); if (error && error != EFBIG) { device_printf(sc->sc_dev, "%s: can't load TX buffer (1) %d\n", __func__, error); goto fail; } if (error) { /* error == EFBIG */ struct mbuf *m_new; m_new = m_defrag(m, M_NOWAIT); if (m_new == NULL) { device_printf(sc->sc_dev, "%s: can't defrag TX buffer\n", __func__); error = ENOBUFS; goto fail; } else { m = m_new; } mt->mt_m = m; error = bus_dmamap_load_mbuf(dma->txbuf_dtag, mt->mt_dmap, m, bwn_dma_buf_addr, &mt->mt_paddr, BUS_DMA_NOWAIT); if (error) { device_printf(sc->sc_dev, "%s: can't load TX buffer (2) %d\n", __func__, error); goto fail; } } bus_dmamap_sync(dma->txbuf_dtag, mt->mt_dmap, BUS_DMASYNC_PREWRITE); dr->setdesc(dr, desc, mt->mt_paddr, m->m_pkthdr.len, 0, 1, 1); bus_dmamap_sync(dr->dr_ring_dtag, dr->dr_ring_dmap, BUS_DMASYNC_PREWRITE); /* XXX send after DTIM */ dr->start_transfer(dr, bwn_dma_nextslot(dr, slot)); return (0); fail: dr->dr_curslot = backup[0]; dr->dr_usedslot = backup[1]; return (error); #undef BWN_GET_TXHDRCACHE } static void bwn_watchdog(void *arg) { struct bwn_softc *sc = arg; if (sc->sc_watchdog_timer != 0 && --sc->sc_watchdog_timer == 0) { device_printf(sc->sc_dev, "device timeout\n"); counter_u64_add(sc->sc_ic.ic_oerrors, 1); } callout_schedule(&sc->sc_watchdog_ch, hz); } static int bwn_attach_core(struct bwn_mac *mac) { struct bwn_softc *sc = mac->mac_sc; int error, have_bg = 0, have_a = 0; - uint32_t high; + uint16_t iost; - KASSERT(siba_get_revid(sc->sc_dev) >= 5, - ("unsupported revision %d", siba_get_revid(sc->sc_dev))); + KASSERT(bhnd_get_hwrev(sc->sc_dev) >= 5, + ("unsupported revision %d", bhnd_get_hwrev(sc->sc_dev))); - siba_powerup(sc->sc_dev, 0); - high = siba_read_4(sc->sc_dev, SIBA_TGSHIGH); - have_a = (high & BWN_TGSHIGH_HAVE_5GHZ) ? 1 : 0; - have_bg = (high & BWN_TGSHIGH_HAVE_2GHZ) ? 1 : 0; - if (high & BWN_TGSHIGH_DUALPHY) { + if ((error = bwn_core_forceclk(mac, true))) + return (error); + + if ((error = bhnd_read_iost(sc->sc_dev, &iost))) { + device_printf(sc->sc_dev, "error reading I/O status flags: " + "%d\n", error); + return (error); + } + + have_a = (iost & BWN_IOST_HAVE_5GHZ) ? 1 : 0; + have_bg = (iost & BWN_IOST_HAVE_2GHZ) ? 1 : 0; + if (iost & BWN_IOST_DUALPHY) { have_bg = 1; have_a = 1; } + #if 0 - device_printf(sc->sc_dev, "%s: high=0x%08x, have_a=%d, have_bg=%d," + device_printf(sc->sc_dev, "%s: iost=0x%04hx, have_a=%d, have_bg=%d," " deviceid=0x%04x, siba_deviceid=0x%04x\n", __func__, - high, + iost, have_a, have_bg, - siba_get_pci_device(sc->sc_dev), - siba_get_chipid(sc->sc_dev)); + sc->sc_board_info.board_devid, + sc->sc_cid.chip_id); #endif /* * Guess at whether it has A-PHY or G-PHY. * This is just used for resetting the core to probe things; * we will re-guess once it's all up and working. */ - bwn_reset_core(mac, have_bg); + error = bwn_reset_core(mac, have_bg); + if (error) + goto fail; /* + * Determine the DMA engine type + */ + if (iost & BHND_IOST_DMA64) { + mac->mac_dmatype = BHND_DMA_ADDR_64BIT; + } else { + uint32_t tmp; + uint16_t base; + + base = bwn_dma_base(0, 0); + BWN_WRITE_4(mac, base + BWN_DMA32_TXCTL, + BWN_DMA32_TXADDREXT_MASK); + tmp = BWN_READ_4(mac, base + BWN_DMA32_TXCTL); + if (tmp & BWN_DMA32_TXADDREXT_MASK) { + mac->mac_dmatype = BHND_DMA_ADDR_32BIT; + } else { + mac->mac_dmatype = BHND_DMA_ADDR_30BIT; + } + } + + /* * Get the PHY version. */ error = bwn_phy_getinfo(mac, have_bg); if (error) goto fail; /* * This is the whitelist of devices which we "believe" * the SPROM PHY config from. The rest are "guessed". */ - if (siba_get_pci_device(sc->sc_dev) != 0x4312 && - siba_get_pci_device(sc->sc_dev) != 0x4315 && - siba_get_pci_device(sc->sc_dev) != 0x4319 && - siba_get_pci_device(sc->sc_dev) != 0x4324 && - siba_get_pci_device(sc->sc_dev) != 0x4328 && - siba_get_pci_device(sc->sc_dev) != 0x432b) { + if (sc->sc_board_info.board_devid != PCI_DEVID_BCM4311_D11DUAL && + sc->sc_board_info.board_devid != PCI_DEVID_BCM4328_D11G && + sc->sc_board_info.board_devid != PCI_DEVID_BCM4318_D11DUAL && + sc->sc_board_info.board_devid != PCI_DEVID_BCM4306_D11DUAL && + sc->sc_board_info.board_devid != PCI_DEVID_BCM4321_D11N && + sc->sc_board_info.board_devid != PCI_DEVID_BCM4322_D11N) { have_a = have_bg = 0; if (mac->mac_phy.type == BWN_PHYTYPE_A) have_a = 1; else if (mac->mac_phy.type == BWN_PHYTYPE_G || mac->mac_phy.type == BWN_PHYTYPE_N || mac->mac_phy.type == BWN_PHYTYPE_LP) have_bg = 1; else KASSERT(0 == 1, ("%s: unknown phy type (%d)", __func__, mac->mac_phy.type)); } /* * XXX The PHY-G support doesn't do 5GHz operation. */ if (mac->mac_phy.type != BWN_PHYTYPE_LP && mac->mac_phy.type != BWN_PHYTYPE_N) { device_printf(sc->sc_dev, "%s: forcing 2GHz only; no dual-band support for PHY\n", __func__); have_a = 0; have_bg = 1; } mac->mac_phy.phy_n = NULL; if (mac->mac_phy.type == BWN_PHYTYPE_G) { mac->mac_phy.attach = bwn_phy_g_attach; mac->mac_phy.detach = bwn_phy_g_detach; mac->mac_phy.prepare_hw = bwn_phy_g_prepare_hw; mac->mac_phy.init_pre = bwn_phy_g_init_pre; mac->mac_phy.init = bwn_phy_g_init; mac->mac_phy.exit = bwn_phy_g_exit; mac->mac_phy.phy_read = bwn_phy_g_read; mac->mac_phy.phy_write = bwn_phy_g_write; mac->mac_phy.rf_read = bwn_phy_g_rf_read; mac->mac_phy.rf_write = bwn_phy_g_rf_write; mac->mac_phy.use_hwpctl = bwn_phy_g_hwpctl; mac->mac_phy.rf_onoff = bwn_phy_g_rf_onoff; mac->mac_phy.switch_analog = bwn_phy_switch_analog; mac->mac_phy.switch_channel = bwn_phy_g_switch_channel; mac->mac_phy.get_default_chan = bwn_phy_g_get_default_chan; mac->mac_phy.set_antenna = bwn_phy_g_set_antenna; mac->mac_phy.set_im = bwn_phy_g_im; mac->mac_phy.recalc_txpwr = bwn_phy_g_recalc_txpwr; mac->mac_phy.set_txpwr = bwn_phy_g_set_txpwr; mac->mac_phy.task_15s = bwn_phy_g_task_15s; mac->mac_phy.task_60s = bwn_phy_g_task_60s; } else if (mac->mac_phy.type == BWN_PHYTYPE_LP) { mac->mac_phy.init_pre = bwn_phy_lp_init_pre; mac->mac_phy.init = bwn_phy_lp_init; mac->mac_phy.phy_read = bwn_phy_lp_read; mac->mac_phy.phy_write = bwn_phy_lp_write; mac->mac_phy.phy_maskset = bwn_phy_lp_maskset; mac->mac_phy.rf_read = bwn_phy_lp_rf_read; mac->mac_phy.rf_write = bwn_phy_lp_rf_write; mac->mac_phy.rf_onoff = bwn_phy_lp_rf_onoff; mac->mac_phy.switch_analog = bwn_phy_lp_switch_analog; mac->mac_phy.switch_channel = bwn_phy_lp_switch_channel; mac->mac_phy.get_default_chan = bwn_phy_lp_get_default_chan; mac->mac_phy.set_antenna = bwn_phy_lp_set_antenna; mac->mac_phy.task_60s = bwn_phy_lp_task_60s; } else if (mac->mac_phy.type == BWN_PHYTYPE_N) { mac->mac_phy.attach = bwn_phy_n_attach; mac->mac_phy.detach = bwn_phy_n_detach; mac->mac_phy.prepare_hw = bwn_phy_n_prepare_hw; mac->mac_phy.init_pre = bwn_phy_n_init_pre; mac->mac_phy.init = bwn_phy_n_init; mac->mac_phy.exit = bwn_phy_n_exit; mac->mac_phy.phy_read = bwn_phy_n_read; mac->mac_phy.phy_write = bwn_phy_n_write; mac->mac_phy.rf_read = bwn_phy_n_rf_read; mac->mac_phy.rf_write = bwn_phy_n_rf_write; mac->mac_phy.use_hwpctl = bwn_phy_n_hwpctl; mac->mac_phy.rf_onoff = bwn_phy_n_rf_onoff; mac->mac_phy.switch_analog = bwn_phy_n_switch_analog; mac->mac_phy.switch_channel = bwn_phy_n_switch_channel; mac->mac_phy.get_default_chan = bwn_phy_n_get_default_chan; mac->mac_phy.set_antenna = bwn_phy_n_set_antenna; mac->mac_phy.set_im = bwn_phy_n_im; mac->mac_phy.recalc_txpwr = bwn_phy_n_recalc_txpwr; mac->mac_phy.set_txpwr = bwn_phy_n_set_txpwr; mac->mac_phy.task_15s = bwn_phy_n_task_15s; mac->mac_phy.task_60s = bwn_phy_n_task_60s; } else { device_printf(sc->sc_dev, "unsupported PHY type (%d)\n", mac->mac_phy.type); error = ENXIO; goto fail; } mac->mac_phy.gmode = have_bg; if (mac->mac_phy.attach != NULL) { error = mac->mac_phy.attach(mac); if (error) { device_printf(sc->sc_dev, "failed\n"); goto fail; } } - bwn_reset_core(mac, have_bg); + error = bwn_reset_core(mac, have_bg); + if (error) + goto fail; error = bwn_chiptest(mac); if (error) goto fail; error = bwn_setup_channels(mac, have_bg, have_a); if (error) { device_printf(sc->sc_dev, "failed to setup channels\n"); goto fail; } if (sc->sc_curmac == NULL) sc->sc_curmac = mac; error = bwn_dma_attach(mac); if (error != 0) { device_printf(sc->sc_dev, "failed to initialize DMA\n"); goto fail; } mac->mac_phy.switch_analog(mac, 0); - siba_dev_down(sc->sc_dev, 0); fail: - siba_powerdown(sc->sc_dev); + bhnd_suspend_hw(sc->sc_dev, 0); bwn_release_firmware(mac); return (error); } /* - * Reset - SIBA. + * Reset */ -void +int bwn_reset_core(struct bwn_mac *mac, int g_mode) { - struct bwn_softc *sc = mac->mac_sc; - uint32_t low, ctl; - uint32_t flags = 0; + struct bwn_softc *sc; + uint32_t ctl; + uint16_t ioctl, ioctl_mask; + int error; + sc = mac->mac_sc; + DPRINTF(sc, BWN_DEBUG_RESET, "%s: g_mode=%d\n", __func__, g_mode); - flags |= (BWN_TGSLOW_PHYCLOCK_ENABLE | BWN_TGSLOW_PHYRESET); + /* Reset core */ + ioctl = (BWN_IOCTL_PHYCLOCK_ENABLE | BWN_IOCTL_PHYRESET); if (g_mode) - flags |= BWN_TGSLOW_SUPPORT_G; + ioctl |= BWN_IOCTL_SUPPORT_G; /* XXX N-PHY only; and hard-code to 20MHz for now */ if (mac->mac_phy.type == BWN_PHYTYPE_N) - flags |= BWN_TGSLOW_PHY_BANDWIDTH_20MHZ; + ioctl |= BWN_IOCTL_PHY_BANDWIDTH_20MHZ; - siba_dev_up(sc->sc_dev, flags); + if ((error = bhnd_reset_hw(sc->sc_dev, ioctl, ioctl))) { + device_printf(sc->sc_dev, "core reset failed: %d", error); + return (error); + } + DELAY(2000); /* Take PHY out of reset */ - low = (siba_read_4(sc->sc_dev, SIBA_TGSLOW) | SIBA_TGSLOW_FGC) & - ~(BWN_TGSLOW_PHYRESET | BWN_TGSLOW_PHYCLOCK_ENABLE); - siba_write_4(sc->sc_dev, SIBA_TGSLOW, low); - siba_read_4(sc->sc_dev, SIBA_TGSLOW); + ioctl = BHND_IOCTL_CLK_FORCE; + ioctl_mask = BHND_IOCTL_CLK_FORCE | + BWN_IOCTL_PHYRESET | + BWN_IOCTL_PHYCLOCK_ENABLE; + + if ((error = bhnd_write_ioctl(sc->sc_dev, ioctl, ioctl_mask))) { + device_printf(sc->sc_dev, "failed to set core ioctl flags: " + "%d\n", error); + return (error); + } + DELAY(2000); - low &= ~SIBA_TGSLOW_FGC; - low |= BWN_TGSLOW_PHYCLOCK_ENABLE; - siba_write_4(sc->sc_dev, SIBA_TGSLOW, low); - siba_read_4(sc->sc_dev, SIBA_TGSLOW); + + ioctl = BWN_IOCTL_PHYCLOCK_ENABLE; + if ((error = bhnd_write_ioctl(sc->sc_dev, ioctl, ioctl_mask))) { + device_printf(sc->sc_dev, "failed to set core ioctl flags: " + "%d\n", error); + return (error); + } + DELAY(2000); if (mac->mac_phy.switch_analog != NULL) mac->mac_phy.switch_analog(mac, 1); ctl = BWN_READ_4(mac, BWN_MACCTL) & ~BWN_MACCTL_GMODE; if (g_mode) ctl |= BWN_MACCTL_GMODE; BWN_WRITE_4(mac, BWN_MACCTL, ctl | BWN_MACCTL_IHR_ON); + + return (0); } static int bwn_phy_getinfo(struct bwn_mac *mac, int gmode) { struct bwn_phy *phy = &mac->mac_phy; struct bwn_softc *sc = mac->mac_sc; uint32_t tmp; /* PHY */ tmp = BWN_READ_2(mac, BWN_PHYVER); phy->gmode = gmode; phy->rf_on = 1; phy->analog = (tmp & BWN_PHYVER_ANALOG) >> 12; phy->type = (tmp & BWN_PHYVER_TYPE) >> 8; phy->rev = (tmp & BWN_PHYVER_VERSION); if ((phy->type == BWN_PHYTYPE_A && phy->rev >= 4) || (phy->type == BWN_PHYTYPE_B && phy->rev != 2 && phy->rev != 4 && phy->rev != 6 && phy->rev != 7) || (phy->type == BWN_PHYTYPE_G && phy->rev > 9) || (phy->type == BWN_PHYTYPE_N && phy->rev > 6) || (phy->type == BWN_PHYTYPE_LP && phy->rev > 2)) goto unsupphy; /* RADIO */ - if (siba_get_chipid(sc->sc_dev) == 0x4317) { - if (siba_get_chiprev(sc->sc_dev) == 0) - tmp = 0x3205017f; - else if (siba_get_chiprev(sc->sc_dev) == 1) - tmp = 0x4205017f; - else - tmp = 0x5205017f; - } else { - BWN_WRITE_2(mac, BWN_RFCTL, BWN_RFCTL_ID); - tmp = BWN_READ_2(mac, BWN_RFDATALO); - BWN_WRITE_2(mac, BWN_RFCTL, BWN_RFCTL_ID); - tmp |= (uint32_t)BWN_READ_2(mac, BWN_RFDATAHI) << 16; - } + BWN_WRITE_2(mac, BWN_RFCTL, BWN_RFCTL_ID); + tmp = BWN_READ_2(mac, BWN_RFDATALO); + BWN_WRITE_2(mac, BWN_RFCTL, BWN_RFCTL_ID); + tmp |= (uint32_t)BWN_READ_2(mac, BWN_RFDATAHI) << 16; + phy->rf_rev = (tmp & 0xf0000000) >> 28; phy->rf_ver = (tmp & 0x0ffff000) >> 12; phy->rf_manuf = (tmp & 0x00000fff); /* * For now, just always do full init (ie, what bwn has traditionally * done) */ phy->phy_do_full_init = 1; if (phy->rf_manuf != 0x17f) /* 0x17f is broadcom */ goto unsupradio; if ((phy->type == BWN_PHYTYPE_A && (phy->rf_ver != 0x2060 || phy->rf_rev != 1 || phy->rf_manuf != 0x17f)) || (phy->type == BWN_PHYTYPE_B && (phy->rf_ver & 0xfff0) != 0x2050) || (phy->type == BWN_PHYTYPE_G && phy->rf_ver != 0x2050) || (phy->type == BWN_PHYTYPE_N && phy->rf_ver != 0x2055 && phy->rf_ver != 0x2056) || (phy->type == BWN_PHYTYPE_LP && phy->rf_ver != 0x2062 && phy->rf_ver != 0x2063)) goto unsupradio; return (0); unsupphy: device_printf(sc->sc_dev, "unsupported PHY (type %#x, rev %#x, " "analog %#x)\n", phy->type, phy->rev, phy->analog); return (ENXIO); unsupradio: device_printf(sc->sc_dev, "unsupported radio (manuf %#x, ver %#x, " "rev %#x)\n", phy->rf_manuf, phy->rf_ver, phy->rf_rev); return (ENXIO); } static int bwn_chiptest(struct bwn_mac *mac) { #define TESTVAL0 0x55aaaa55 #define TESTVAL1 0xaa5555aa struct bwn_softc *sc = mac->mac_sc; uint32_t v, backup; BWN_LOCK(sc); backup = bwn_shm_read_4(mac, BWN_SHARED, 0); bwn_shm_write_4(mac, BWN_SHARED, 0, TESTVAL0); if (bwn_shm_read_4(mac, BWN_SHARED, 0) != TESTVAL0) goto error; bwn_shm_write_4(mac, BWN_SHARED, 0, TESTVAL1); if (bwn_shm_read_4(mac, BWN_SHARED, 0) != TESTVAL1) goto error; bwn_shm_write_4(mac, BWN_SHARED, 0, backup); - if ((siba_get_revid(sc->sc_dev) >= 3) && - (siba_get_revid(sc->sc_dev) <= 10)) { + if ((bhnd_get_hwrev(sc->sc_dev) >= 3) && + (bhnd_get_hwrev(sc->sc_dev) <= 10)) { BWN_WRITE_2(mac, BWN_TSF_CFP_START, 0xaaaa); BWN_WRITE_4(mac, BWN_TSF_CFP_START, 0xccccbbbb); if (BWN_READ_2(mac, BWN_TSF_CFP_START_LOW) != 0xbbbb) goto error; if (BWN_READ_2(mac, BWN_TSF_CFP_START_HIGH) != 0xcccc) goto error; } BWN_WRITE_4(mac, BWN_TSF_CFP_START, 0); v = BWN_READ_4(mac, BWN_MACCTL) | BWN_MACCTL_GMODE; if (v != (BWN_MACCTL_GMODE | BWN_MACCTL_IHR_ON)) goto error; BWN_UNLOCK(sc); return (0); error: BWN_UNLOCK(sc); device_printf(sc->sc_dev, "failed to validate the chipaccess\n"); return (ENODEV); } static int bwn_setup_channels(struct bwn_mac *mac, int have_bg, int have_a) { struct bwn_softc *sc = mac->mac_sc; struct ieee80211com *ic = &sc->sc_ic; uint8_t bands[IEEE80211_MODE_BYTES]; memset(ic->ic_channels, 0, sizeof(ic->ic_channels)); ic->ic_nchans = 0; DPRINTF(sc, BWN_DEBUG_EEPROM, "%s: called; bg=%d, a=%d\n", __func__, have_bg, have_a); if (have_bg) { memset(bands, 0, sizeof(bands)); setbit(bands, IEEE80211_MODE_11B); setbit(bands, IEEE80211_MODE_11G); bwn_addchannels(ic->ic_channels, IEEE80211_CHAN_MAX, &ic->ic_nchans, &bwn_chantable_bg, bands); } if (have_a) { memset(bands, 0, sizeof(bands)); setbit(bands, IEEE80211_MODE_11A); bwn_addchannels(ic->ic_channels, IEEE80211_CHAN_MAX, &ic->ic_nchans, &bwn_chantable_a, bands); } mac->mac_phy.supports_2ghz = have_bg; mac->mac_phy.supports_5ghz = have_a; return (ic->ic_nchans == 0 ? ENXIO : 0); } uint32_t bwn_shm_read_4(struct bwn_mac *mac, uint16_t way, uint16_t offset) { uint32_t ret; BWN_ASSERT_LOCKED(mac->mac_sc); if (way == BWN_SHARED) { KASSERT((offset & 0x0001) == 0, ("%s:%d warn", __func__, __LINE__)); if (offset & 0x0003) { bwn_shm_ctlword(mac, way, offset >> 2); ret = BWN_READ_2(mac, BWN_SHM_DATA_UNALIGNED); ret <<= 16; bwn_shm_ctlword(mac, way, (offset >> 2) + 1); ret |= BWN_READ_2(mac, BWN_SHM_DATA); goto out; } offset >>= 2; } bwn_shm_ctlword(mac, way, offset); ret = BWN_READ_4(mac, BWN_SHM_DATA); out: return (ret); } uint16_t bwn_shm_read_2(struct bwn_mac *mac, uint16_t way, uint16_t offset) { uint16_t ret; BWN_ASSERT_LOCKED(mac->mac_sc); if (way == BWN_SHARED) { KASSERT((offset & 0x0001) == 0, ("%s:%d warn", __func__, __LINE__)); if (offset & 0x0003) { bwn_shm_ctlword(mac, way, offset >> 2); ret = BWN_READ_2(mac, BWN_SHM_DATA_UNALIGNED); goto out; } offset >>= 2; } bwn_shm_ctlword(mac, way, offset); ret = BWN_READ_2(mac, BWN_SHM_DATA); out: return (ret); } static void bwn_shm_ctlword(struct bwn_mac *mac, uint16_t way, uint16_t offset) { uint32_t control; control = way; control <<= 16; control |= offset; BWN_WRITE_4(mac, BWN_SHM_CONTROL, control); } void bwn_shm_write_4(struct bwn_mac *mac, uint16_t way, uint16_t offset, uint32_t value) { BWN_ASSERT_LOCKED(mac->mac_sc); if (way == BWN_SHARED) { KASSERT((offset & 0x0001) == 0, ("%s:%d warn", __func__, __LINE__)); if (offset & 0x0003) { bwn_shm_ctlword(mac, way, offset >> 2); BWN_WRITE_2(mac, BWN_SHM_DATA_UNALIGNED, (value >> 16) & 0xffff); bwn_shm_ctlword(mac, way, (offset >> 2) + 1); BWN_WRITE_2(mac, BWN_SHM_DATA, value & 0xffff); return; } offset >>= 2; } bwn_shm_ctlword(mac, way, offset); BWN_WRITE_4(mac, BWN_SHM_DATA, value); } void bwn_shm_write_2(struct bwn_mac *mac, uint16_t way, uint16_t offset, uint16_t value) { BWN_ASSERT_LOCKED(mac->mac_sc); if (way == BWN_SHARED) { KASSERT((offset & 0x0001) == 0, ("%s:%d warn", __func__, __LINE__)); if (offset & 0x0003) { bwn_shm_ctlword(mac, way, offset >> 2); BWN_WRITE_2(mac, BWN_SHM_DATA_UNALIGNED, value); return; } offset >>= 2; } bwn_shm_ctlword(mac, way, offset); BWN_WRITE_2(mac, BWN_SHM_DATA, value); } static void bwn_addchannels(struct ieee80211_channel chans[], int maxchans, int *nchans, const struct bwn_channelinfo *ci, const uint8_t bands[]) { int i, error; for (i = 0, error = 0; i < ci->nchannels && error == 0; i++) { const struct bwn_channel *hc = &ci->channels[i]; error = ieee80211_add_channel(chans, maxchans, nchans, hc->ieee, hc->freq, hc->maxTxPow, 0, bands); } } static int bwn_raw_xmit(struct ieee80211_node *ni, struct mbuf *m, const struct ieee80211_bpf_params *params) { struct ieee80211com *ic = ni->ni_ic; struct bwn_softc *sc = ic->ic_softc; struct bwn_mac *mac = sc->sc_curmac; int error; if ((sc->sc_flags & BWN_FLAG_RUNNING) == 0 || mac->mac_status < BWN_MAC_STATUS_STARTED) { m_freem(m); return (ENETDOWN); } BWN_LOCK(sc); if (bwn_tx_isfull(sc, m)) { m_freem(m); BWN_UNLOCK(sc); return (ENOBUFS); } error = bwn_tx_start(sc, ni, m); if (error == 0) sc->sc_watchdog_timer = 5; BWN_UNLOCK(sc); return (error); } /* * Callback from the 802.11 layer to update the slot time * based on the current setting. We use it to notify the * firmware of ERP changes and the f/w takes care of things * like slot time and preamble. */ static void bwn_updateslot(struct ieee80211com *ic) { struct bwn_softc *sc = ic->ic_softc; struct bwn_mac *mac; BWN_LOCK(sc); if (sc->sc_flags & BWN_FLAG_RUNNING) { mac = (struct bwn_mac *)sc->sc_curmac; bwn_set_slot_time(mac, IEEE80211_GET_SLOTTIME(ic)); } BWN_UNLOCK(sc); } /* * Callback from the 802.11 layer after a promiscuous mode change. * Note this interface does not check the operating mode as this * is an internal callback and we are expected to honor the current * state (e.g. this is used for setting the interface in promiscuous * mode when operating in hostap mode to do ACS). */ static void bwn_update_promisc(struct ieee80211com *ic) { struct bwn_softc *sc = ic->ic_softc; struct bwn_mac *mac = sc->sc_curmac; BWN_LOCK(sc); mac = sc->sc_curmac; if (mac != NULL && mac->mac_status >= BWN_MAC_STATUS_INITED) { if (ic->ic_promisc > 0) sc->sc_filters |= BWN_MACCTL_PROMISC; else sc->sc_filters &= ~BWN_MACCTL_PROMISC; bwn_set_opmode(mac); } BWN_UNLOCK(sc); } /* * Callback from the 802.11 layer to update WME parameters. */ static int bwn_wme_update(struct ieee80211com *ic) { struct bwn_softc *sc = ic->ic_softc; struct bwn_mac *mac = sc->sc_curmac; struct chanAccParams chp; struct wmeParams *wmep; int i; ieee80211_wme_ic_getparams(ic, &chp); BWN_LOCK(sc); mac = sc->sc_curmac; if (mac != NULL && mac->mac_status >= BWN_MAC_STATUS_INITED) { bwn_mac_suspend(mac); for (i = 0; i < N(sc->sc_wmeParams); i++) { wmep = &chp.cap_wmeParams[i]; bwn_wme_loadparams(mac, wmep, bwn_wme_shm_offsets[i]); } bwn_mac_enable(mac); } BWN_UNLOCK(sc); return (0); } static void bwn_scan_start(struct ieee80211com *ic) { struct bwn_softc *sc = ic->ic_softc; struct bwn_mac *mac; BWN_LOCK(sc); mac = sc->sc_curmac; if (mac != NULL && mac->mac_status >= BWN_MAC_STATUS_INITED) { sc->sc_filters |= BWN_MACCTL_BEACON_PROMISC; bwn_set_opmode(mac); /* disable CFP update during scan */ bwn_hf_write(mac, bwn_hf_read(mac) | BWN_HF_SKIP_CFP_UPDATE); } BWN_UNLOCK(sc); } static void bwn_scan_end(struct ieee80211com *ic) { struct bwn_softc *sc = ic->ic_softc; struct bwn_mac *mac; BWN_LOCK(sc); mac = sc->sc_curmac; if (mac != NULL && mac->mac_status >= BWN_MAC_STATUS_INITED) { sc->sc_filters &= ~BWN_MACCTL_BEACON_PROMISC; bwn_set_opmode(mac); bwn_hf_write(mac, bwn_hf_read(mac) & ~BWN_HF_SKIP_CFP_UPDATE); } BWN_UNLOCK(sc); } static void bwn_set_channel(struct ieee80211com *ic) { struct bwn_softc *sc = ic->ic_softc; struct bwn_mac *mac = sc->sc_curmac; struct bwn_phy *phy = &mac->mac_phy; int chan, error; BWN_LOCK(sc); error = bwn_switch_band(sc, ic->ic_curchan); if (error) goto fail; bwn_mac_suspend(mac); bwn_set_txretry(mac, BWN_RETRY_SHORT, BWN_RETRY_LONG); chan = ieee80211_chan2ieee(ic, ic->ic_curchan); if (chan != phy->chan) bwn_switch_channel(mac, chan); /* TX power level */ if (ic->ic_curchan->ic_maxpower != 0 && ic->ic_curchan->ic_maxpower != phy->txpower) { phy->txpower = ic->ic_curchan->ic_maxpower / 2; bwn_phy_txpower_check(mac, BWN_TXPWR_IGNORE_TIME | BWN_TXPWR_IGNORE_TSSI); } bwn_set_txantenna(mac, BWN_ANT_DEFAULT); if (phy->set_antenna) phy->set_antenna(mac, BWN_ANT_DEFAULT); if (sc->sc_rf_enabled != phy->rf_on) { if (sc->sc_rf_enabled) { bwn_rf_turnon(mac); if (!(mac->mac_flags & BWN_MAC_FLAG_RADIO_ON)) device_printf(sc->sc_dev, "please turn on the RF switch\n"); } else bwn_rf_turnoff(mac); } bwn_mac_enable(mac); fail: /* * Setup radio tap channel freq and flags */ sc->sc_tx_th.wt_chan_freq = sc->sc_rx_th.wr_chan_freq = htole16(ic->ic_curchan->ic_freq); sc->sc_tx_th.wt_chan_flags = sc->sc_rx_th.wr_chan_flags = htole16(ic->ic_curchan->ic_flags & 0xffff); BWN_UNLOCK(sc); } static struct ieee80211vap * bwn_vap_create(struct ieee80211com *ic, const char name[IFNAMSIZ], int unit, enum ieee80211_opmode opmode, int flags, const uint8_t bssid[IEEE80211_ADDR_LEN], const uint8_t mac[IEEE80211_ADDR_LEN]) { struct ieee80211vap *vap; struct bwn_vap *bvp; switch (opmode) { case IEEE80211_M_HOSTAP: case IEEE80211_M_MBSS: case IEEE80211_M_STA: case IEEE80211_M_WDS: case IEEE80211_M_MONITOR: case IEEE80211_M_IBSS: case IEEE80211_M_AHDEMO: break; default: return (NULL); } bvp = malloc(sizeof(struct bwn_vap), M_80211_VAP, M_WAITOK | M_ZERO); vap = &bvp->bv_vap; ieee80211_vap_setup(ic, vap, name, unit, opmode, flags, bssid); /* override with driver methods */ bvp->bv_newstate = vap->iv_newstate; vap->iv_newstate = bwn_newstate; /* override max aid so sta's cannot assoc when we're out of sta id's */ vap->iv_max_aid = BWN_STAID_MAX; ieee80211_ratectl_init(vap); /* complete setup */ ieee80211_vap_attach(vap, ieee80211_media_change, ieee80211_media_status, mac); return (vap); } static void bwn_vap_delete(struct ieee80211vap *vap) { struct bwn_vap *bvp = BWN_VAP(vap); ieee80211_ratectl_deinit(vap); ieee80211_vap_detach(vap); free(bvp, M_80211_VAP); } static int bwn_init(struct bwn_softc *sc) { struct bwn_mac *mac; int error; BWN_ASSERT_LOCKED(sc); DPRINTF(sc, BWN_DEBUG_RESET, "%s: called\n", __func__); bzero(sc->sc_bssid, IEEE80211_ADDR_LEN); sc->sc_flags |= BWN_FLAG_NEED_BEACON_TP; sc->sc_filters = 0; bwn_wme_clear(sc); sc->sc_beacons[0] = sc->sc_beacons[1] = 0; sc->sc_rf_enabled = 1; mac = sc->sc_curmac; if (mac->mac_status == BWN_MAC_STATUS_UNINIT) { error = bwn_core_init(mac); if (error != 0) return (error); } if (mac->mac_status == BWN_MAC_STATUS_INITED) bwn_core_start(mac); bwn_set_opmode(mac); bwn_set_pretbtt(mac); bwn_spu_setdelay(mac, 0); bwn_set_macaddr(mac); sc->sc_flags |= BWN_FLAG_RUNNING; callout_reset(&sc->sc_rfswitch_ch, hz, bwn_rfswitch, sc); callout_reset(&sc->sc_watchdog_ch, hz, bwn_watchdog, sc); return (0); } static void bwn_stop(struct bwn_softc *sc) { struct bwn_mac *mac = sc->sc_curmac; BWN_ASSERT_LOCKED(sc); DPRINTF(sc, BWN_DEBUG_RESET, "%s: called\n", __func__); if (mac->mac_status >= BWN_MAC_STATUS_INITED) { /* XXX FIXME opmode not based on VAP */ bwn_set_opmode(mac); bwn_set_macaddr(mac); } if (mac->mac_status >= BWN_MAC_STATUS_STARTED) bwn_core_stop(mac); callout_stop(&sc->sc_led_blink_ch); sc->sc_led_blinking = 0; bwn_core_exit(mac); sc->sc_rf_enabled = 0; sc->sc_flags &= ~BWN_FLAG_RUNNING; } static void bwn_wme_clear(struct bwn_softc *sc) { #define MS(_v, _f) (((_v) & _f) >> _f##_S) struct wmeParams *p; unsigned int i; KASSERT(N(bwn_wme_shm_offsets) == N(sc->sc_wmeParams), ("%s:%d: fail", __func__, __LINE__)); for (i = 0; i < N(sc->sc_wmeParams); i++) { p = &(sc->sc_wmeParams[i]); switch (bwn_wme_shm_offsets[i]) { case BWN_WME_VOICE: p->wmep_txopLimit = 0; p->wmep_aifsn = 2; /* XXX FIXME: log2(cwmin) */ p->wmep_logcwmin = MS(0x0001, WME_PARAM_LOGCWMIN); p->wmep_logcwmax = MS(0x0001, WME_PARAM_LOGCWMAX); break; case BWN_WME_VIDEO: p->wmep_txopLimit = 0; p->wmep_aifsn = 2; /* XXX FIXME: log2(cwmin) */ p->wmep_logcwmin = MS(0x0001, WME_PARAM_LOGCWMIN); p->wmep_logcwmax = MS(0x0001, WME_PARAM_LOGCWMAX); break; case BWN_WME_BESTEFFORT: p->wmep_txopLimit = 0; p->wmep_aifsn = 3; /* XXX FIXME: log2(cwmin) */ p->wmep_logcwmin = MS(0x0001, WME_PARAM_LOGCWMIN); p->wmep_logcwmax = MS(0x03ff, WME_PARAM_LOGCWMAX); break; case BWN_WME_BACKGROUND: p->wmep_txopLimit = 0; p->wmep_aifsn = 7; /* XXX FIXME: log2(cwmin) */ p->wmep_logcwmin = MS(0x0001, WME_PARAM_LOGCWMIN); p->wmep_logcwmax = MS(0x03ff, WME_PARAM_LOGCWMAX); break; default: KASSERT(0 == 1, ("%s:%d: fail", __func__, __LINE__)); } } } static int +bwn_core_forceclk(struct bwn_mac *mac, bool force) +{ + struct bwn_softc *sc; + bhnd_clock clock; + int error; + + sc = mac->mac_sc; + + /* On PMU equipped devices, we do not need to force the HT clock */ + if (sc->sc_pmu != NULL) + return (0); + + /* Issue a PMU clock request */ + if (force) + clock = BHND_CLOCK_HT; + else + clock = BHND_CLOCK_DYN; + + if ((error = bhnd_request_clock(sc->sc_dev, clock))) { + device_printf(sc->sc_dev, "%d clock request failed: %d\n", + clock, error); + return (error); + } + + return (0); +} + +static int bwn_core_init(struct bwn_mac *mac) { struct bwn_softc *sc = mac->mac_sc; uint64_t hf; int error; KASSERT(mac->mac_status == BWN_MAC_STATUS_UNINIT, ("%s:%d: fail", __func__, __LINE__)); DPRINTF(mac->mac_sc, BWN_DEBUG_RESET, "%s: called\n", __func__); - siba_powerup(sc->sc_dev, 0); - if (!siba_dev_isup(sc->sc_dev)) - bwn_reset_core(mac, mac->mac_phy.gmode); + if ((error = bwn_core_forceclk(mac, true))) + return (error); + if (bhnd_is_hw_suspended(sc->sc_dev)) { + if ((error = bwn_reset_core(mac, mac->mac_phy.gmode))) + goto fail0; + } + mac->mac_flags &= ~BWN_MAC_FLAG_DFQVALID; mac->mac_flags |= BWN_MAC_FLAG_RADIO_ON; mac->mac_phy.hwpctl = (bwn_hwpctl) ? 1 : 0; BWN_GETTIME(mac->mac_phy.nexttime); mac->mac_phy.txerrors = BWN_TXERROR_MAX; bzero(&mac->mac_stats, sizeof(mac->mac_stats)); mac->mac_stats.link_noise = -95; mac->mac_reason_intr = 0; bzero(mac->mac_reason, sizeof(mac->mac_reason)); mac->mac_intr_mask = BWN_INTR_MASKTEMPLATE; #ifdef BWN_DEBUG if (sc->sc_debug & BWN_DEBUG_XMIT) mac->mac_intr_mask &= ~BWN_INTR_PHY_TXERR; #endif mac->mac_suspended = 1; mac->mac_task_state = 0; memset(&mac->mac_noise, 0, sizeof(mac->mac_noise)); mac->mac_phy.init_pre(mac); - siba_pcicore_intr(sc->sc_dev); - - siba_fix_imcfglobug(sc->sc_dev); bwn_bt_disable(mac); if (mac->mac_phy.prepare_hw) { error = mac->mac_phy.prepare_hw(mac); if (error) goto fail0; } DPRINTF(mac->mac_sc, BWN_DEBUG_RESET, "%s: chip_init\n", __func__); error = bwn_chip_init(mac); if (error) goto fail0; bwn_shm_write_2(mac, BWN_SHARED, BWN_SHARED_COREREV, - siba_get_revid(sc->sc_dev)); + bhnd_get_hwrev(sc->sc_dev)); hf = bwn_hf_read(mac); if (mac->mac_phy.type == BWN_PHYTYPE_G) { hf |= BWN_HF_GPHY_SYM_WORKAROUND; - if (siba_sprom_get_bf_lo(sc->sc_dev) & BWN_BFL_PACTRL) + if (sc->sc_board_info.board_flags & BHND_BFL_PACTRL) hf |= BWN_HF_PAGAINBOOST_OFDM_ON; if (mac->mac_phy.rev == 1) hf |= BWN_HF_GPHY_DC_CANCELFILTER; } if (mac->mac_phy.rf_ver == 0x2050) { if (mac->mac_phy.rf_rev < 6) hf |= BWN_HF_FORCE_VCO_RECALC; if (mac->mac_phy.rf_rev == 6) hf |= BWN_HF_4318_TSSI; } - if (siba_sprom_get_bf_lo(sc->sc_dev) & BWN_BFL_CRYSTAL_NOSLOW) + if (sc->sc_board_info.board_flags & BHND_BFL_NOPLLDOWN) hf |= BWN_HF_SLOWCLOCK_REQ_OFF; - if ((siba_get_type(sc->sc_dev) == SIBA_TYPE_PCI) && - (siba_get_pcicore_revid(sc->sc_dev) <= 10)) + if (sc->sc_quirks & BWN_QUIRK_UCODE_SLOWCLOCK_WAR) hf |= BWN_HF_PCI_SLOWCLOCK_WORKAROUND; hf &= ~BWN_HF_SKIP_CFP_UPDATE; bwn_hf_write(mac, hf); /* Tell the firmware about the MAC capabilities */ - if (siba_get_revid(sc->sc_dev) >= 13) { + if (bhnd_get_hwrev(sc->sc_dev) >= 13) { uint32_t cap; cap = BWN_READ_4(mac, BWN_MAC_HW_CAP); DPRINTF(sc, BWN_DEBUG_RESET, "%s: hw capabilities: 0x%08x\n", __func__, cap); bwn_shm_write_2(mac, BWN_SHARED, BWN_SHARED_MACHW_L, cap & 0xffff); bwn_shm_write_2(mac, BWN_SHARED, BWN_SHARED_MACHW_H, (cap >> 16) & 0xffff); } bwn_set_txretry(mac, BWN_RETRY_SHORT, BWN_RETRY_LONG); bwn_shm_write_2(mac, BWN_SHARED, BWN_SHARED_SHORT_RETRY_FALLBACK, 3); bwn_shm_write_2(mac, BWN_SHARED, BWN_SHARED_LONG_RETRY_FALLBACK, 2); bwn_shm_write_2(mac, BWN_SHARED, BWN_SHARED_PROBE_RESP_MAXTIME, 1); bwn_rate_init(mac); bwn_set_phytxctl(mac); bwn_shm_write_2(mac, BWN_SCRATCH, BWN_SCRATCH_CONT_MIN, (mac->mac_phy.type == BWN_PHYTYPE_B) ? 0x1f : 0xf); bwn_shm_write_2(mac, BWN_SCRATCH, BWN_SCRATCH_CONT_MAX, 0x3ff); - if (siba_get_type(sc->sc_dev) == SIBA_TYPE_PCMCIA || bwn_usedma == 0) + if (sc->sc_quirks & BWN_QUIRK_NODMA) bwn_pio_init(mac); else bwn_dma_init(mac); bwn_wme_init(mac); bwn_spu_setdelay(mac, 1); bwn_bt_enable(mac); DPRINTF(mac->mac_sc, BWN_DEBUG_RESET, "%s: powerup\n", __func__); - siba_powerup(sc->sc_dev, - !(siba_sprom_get_bf_lo(sc->sc_dev) & BWN_BFL_CRYSTAL_NOSLOW)); + if (sc->sc_board_info.board_flags & BHND_BFL_NOPLLDOWN) + bwn_core_forceclk(mac, true); + else + bwn_core_forceclk(mac, false); + bwn_set_macaddr(mac); bwn_crypt_init(mac); /* XXX LED initializatin */ mac->mac_status = BWN_MAC_STATUS_INITED; DPRINTF(mac->mac_sc, BWN_DEBUG_RESET, "%s: done\n", __func__); return (error); fail0: - siba_powerdown(sc->sc_dev); + bhnd_suspend_hw(sc->sc_dev, 0); KASSERT(mac->mac_status == BWN_MAC_STATUS_UNINIT, ("%s:%d: fail", __func__, __LINE__)); DPRINTF(mac->mac_sc, BWN_DEBUG_RESET, "%s: fail\n", __func__); return (error); } static void bwn_core_start(struct bwn_mac *mac) { struct bwn_softc *sc = mac->mac_sc; uint32_t tmp; KASSERT(mac->mac_status == BWN_MAC_STATUS_INITED, ("%s:%d: fail", __func__, __LINE__)); - if (siba_get_revid(sc->sc_dev) < 5) + if (bhnd_get_hwrev(sc->sc_dev) < 5) return; while (1) { tmp = BWN_READ_4(mac, BWN_XMITSTAT_0); if (!(tmp & 0x00000001)) break; tmp = BWN_READ_4(mac, BWN_XMITSTAT_1); } bwn_mac_enable(mac); BWN_WRITE_4(mac, BWN_INTR_MASK, mac->mac_intr_mask); callout_reset(&sc->sc_task_ch, hz * 15, bwn_tasks, mac); mac->mac_status = BWN_MAC_STATUS_STARTED; } static void bwn_core_exit(struct bwn_mac *mac) { struct bwn_softc *sc = mac->mac_sc; uint32_t macctl; BWN_ASSERT_LOCKED(mac->mac_sc); KASSERT(mac->mac_status <= BWN_MAC_STATUS_INITED, ("%s:%d: fail", __func__, __LINE__)); if (mac->mac_status != BWN_MAC_STATUS_INITED) return; mac->mac_status = BWN_MAC_STATUS_UNINIT; macctl = BWN_READ_4(mac, BWN_MACCTL); macctl &= ~BWN_MACCTL_MCODE_RUN; macctl |= BWN_MACCTL_MCODE_JMP0; BWN_WRITE_4(mac, BWN_MACCTL, macctl); bwn_dma_stop(mac); bwn_pio_stop(mac); bwn_chip_exit(mac); mac->mac_phy.switch_analog(mac, 0); - siba_dev_down(sc->sc_dev, 0); - siba_powerdown(sc->sc_dev); + bhnd_suspend_hw(sc->sc_dev, 0); } static void bwn_bt_disable(struct bwn_mac *mac) { struct bwn_softc *sc = mac->mac_sc; (void)sc; /* XXX do nothing yet */ } static int bwn_chip_init(struct bwn_mac *mac) { struct bwn_softc *sc = mac->mac_sc; struct bwn_phy *phy = &mac->mac_phy; uint32_t macctl; + u_int delay; int error; macctl = BWN_MACCTL_IHR_ON | BWN_MACCTL_SHM_ON | BWN_MACCTL_STA; if (phy->gmode) macctl |= BWN_MACCTL_GMODE; BWN_WRITE_4(mac, BWN_MACCTL, macctl); error = bwn_fw_fillinfo(mac); if (error) return (error); error = bwn_fw_loaducode(mac); if (error) return (error); error = bwn_gpio_init(mac); if (error) return (error); error = bwn_fw_loadinitvals(mac); - if (error) { - siba_gpio_set(sc->sc_dev, 0); + if (error) return (error); - } + phy->switch_analog(mac, 1); error = bwn_phy_init(mac); - if (error) { - siba_gpio_set(sc->sc_dev, 0); + if (error) return (error); - } + if (phy->set_im) phy->set_im(mac, BWN_IMMODE_NONE); if (phy->set_antenna) phy->set_antenna(mac, BWN_ANT_DEFAULT); bwn_set_txantenna(mac, BWN_ANT_DEFAULT); if (phy->type == BWN_PHYTYPE_B) BWN_WRITE_2(mac, 0x005e, BWN_READ_2(mac, 0x005e) | 0x0004); BWN_WRITE_4(mac, 0x0100, 0x01000000); - if (siba_get_revid(sc->sc_dev) < 5) + if (bhnd_get_hwrev(sc->sc_dev) < 5) BWN_WRITE_4(mac, 0x010c, 0x01000000); BWN_WRITE_4(mac, BWN_MACCTL, BWN_READ_4(mac, BWN_MACCTL) & ~BWN_MACCTL_STA); BWN_WRITE_4(mac, BWN_MACCTL, BWN_READ_4(mac, BWN_MACCTL) | BWN_MACCTL_STA); bwn_shm_write_2(mac, BWN_SHARED, 0x0074, 0x0000); bwn_set_opmode(mac); - if (siba_get_revid(sc->sc_dev) < 3) { + if (bhnd_get_hwrev(sc->sc_dev) < 3) { BWN_WRITE_2(mac, 0x060e, 0x0000); BWN_WRITE_2(mac, 0x0610, 0x8000); BWN_WRITE_2(mac, 0x0604, 0x0000); BWN_WRITE_2(mac, 0x0606, 0x0200); } else { BWN_WRITE_4(mac, 0x0188, 0x80000000); BWN_WRITE_4(mac, 0x018c, 0x02000000); } BWN_WRITE_4(mac, BWN_INTR_REASON, 0x00004000); BWN_WRITE_4(mac, BWN_DMA0_INTR_MASK, 0x0001dc00); BWN_WRITE_4(mac, BWN_DMA1_INTR_MASK, 0x0000dc00); BWN_WRITE_4(mac, BWN_DMA2_INTR_MASK, 0x0000dc00); BWN_WRITE_4(mac, BWN_DMA3_INTR_MASK, 0x0001dc00); BWN_WRITE_4(mac, BWN_DMA4_INTR_MASK, 0x0000dc00); BWN_WRITE_4(mac, BWN_DMA5_INTR_MASK, 0x0000dc00); bwn_mac_phy_clock_set(mac, true); - /* SIBA powerup */ - BWN_WRITE_2(mac, BWN_POWERUP_DELAY, siba_get_cc_powerdelay(sc->sc_dev)); - return (error); + /* Provide the HT clock transition latency to the MAC core */ + error = bhnd_get_clock_latency(sc->sc_dev, BHND_CLOCK_HT, &delay); + if (error) { + device_printf(sc->sc_dev, "failed to fetch HT clock latency: " + "%d\n", error); + return (error); + } + + if (delay > UINT16_MAX) { + device_printf(sc->sc_dev, "invalid HT clock latency: %u\n", + delay); + return (ENXIO); + } + + BWN_WRITE_2(mac, BWN_POWERUP_DELAY, delay); + return (0); } /* read hostflags */ uint64_t bwn_hf_read(struct bwn_mac *mac) { uint64_t ret; ret = bwn_shm_read_2(mac, BWN_SHARED, BWN_SHARED_HFHI); ret <<= 16; ret |= bwn_shm_read_2(mac, BWN_SHARED, BWN_SHARED_HFMI); ret <<= 16; ret |= bwn_shm_read_2(mac, BWN_SHARED, BWN_SHARED_HFLO); return (ret); } void bwn_hf_write(struct bwn_mac *mac, uint64_t value) { bwn_shm_write_2(mac, BWN_SHARED, BWN_SHARED_HFLO, (value & 0x00000000ffffull)); bwn_shm_write_2(mac, BWN_SHARED, BWN_SHARED_HFMI, (value & 0x0000ffff0000ull) >> 16); bwn_shm_write_2(mac, BWN_SHARED, BWN_SHARED_HFHI, (value & 0xffff00000000ULL) >> 32); } static void bwn_set_txretry(struct bwn_mac *mac, int s, int l) { bwn_shm_write_2(mac, BWN_SCRATCH, BWN_SCRATCH_SHORT_RETRY, MIN(s, 0xf)); bwn_shm_write_2(mac, BWN_SCRATCH, BWN_SCRATCH_LONG_RETRY, MIN(l, 0xf)); } static void bwn_rate_init(struct bwn_mac *mac) { switch (mac->mac_phy.type) { case BWN_PHYTYPE_A: case BWN_PHYTYPE_G: case BWN_PHYTYPE_LP: case BWN_PHYTYPE_N: bwn_rate_write(mac, BWN_OFDM_RATE_6MB, 1); bwn_rate_write(mac, BWN_OFDM_RATE_12MB, 1); bwn_rate_write(mac, BWN_OFDM_RATE_18MB, 1); bwn_rate_write(mac, BWN_OFDM_RATE_24MB, 1); bwn_rate_write(mac, BWN_OFDM_RATE_36MB, 1); bwn_rate_write(mac, BWN_OFDM_RATE_48MB, 1); bwn_rate_write(mac, BWN_OFDM_RATE_54MB, 1); if (mac->mac_phy.type == BWN_PHYTYPE_A) break; /* FALLTHROUGH */ case BWN_PHYTYPE_B: bwn_rate_write(mac, BWN_CCK_RATE_1MB, 0); bwn_rate_write(mac, BWN_CCK_RATE_2MB, 0); bwn_rate_write(mac, BWN_CCK_RATE_5MB, 0); bwn_rate_write(mac, BWN_CCK_RATE_11MB, 0); break; default: KASSERT(0 == 1, ("%s:%d: fail", __func__, __LINE__)); } } static void bwn_rate_write(struct bwn_mac *mac, uint16_t rate, int ofdm) { uint16_t offset; if (ofdm) { offset = 0x480; offset += (bwn_plcp_getofdm(rate) & 0x000f) * 2; } else { offset = 0x4c0; offset += (bwn_plcp_getcck(rate) & 0x000f) * 2; } bwn_shm_write_2(mac, BWN_SHARED, offset + 0x20, bwn_shm_read_2(mac, BWN_SHARED, offset)); } static uint8_t bwn_plcp_getcck(const uint8_t bitrate) { switch (bitrate) { case BWN_CCK_RATE_1MB: return (0x0a); case BWN_CCK_RATE_2MB: return (0x14); case BWN_CCK_RATE_5MB: return (0x37); case BWN_CCK_RATE_11MB: return (0x6e); } KASSERT(0 == 1, ("%s:%d: fail", __func__, __LINE__)); return (0); } static uint8_t bwn_plcp_getofdm(const uint8_t bitrate) { switch (bitrate) { case BWN_OFDM_RATE_6MB: return (0xb); case BWN_OFDM_RATE_9MB: return (0xf); case BWN_OFDM_RATE_12MB: return (0xa); case BWN_OFDM_RATE_18MB: return (0xe); case BWN_OFDM_RATE_24MB: return (0x9); case BWN_OFDM_RATE_36MB: return (0xd); case BWN_OFDM_RATE_48MB: return (0x8); case BWN_OFDM_RATE_54MB: return (0xc); } KASSERT(0 == 1, ("%s:%d: fail", __func__, __LINE__)); return (0); } static void bwn_set_phytxctl(struct bwn_mac *mac) { uint16_t ctl; ctl = (BWN_TX_PHY_ENC_CCK | BWN_TX_PHY_ANT01AUTO | BWN_TX_PHY_TXPWR); bwn_shm_write_2(mac, BWN_SHARED, BWN_SHARED_BEACON_PHYCTL, ctl); bwn_shm_write_2(mac, BWN_SHARED, BWN_SHARED_ACKCTS_PHYCTL, ctl); bwn_shm_write_2(mac, BWN_SHARED, BWN_SHARED_PROBE_RESP_PHYCTL, ctl); } static void bwn_pio_init(struct bwn_mac *mac) { struct bwn_pio *pio = &mac->mac_method.pio; BWN_WRITE_4(mac, BWN_MACCTL, BWN_READ_4(mac, BWN_MACCTL) & ~BWN_MACCTL_BIGENDIAN); bwn_shm_write_2(mac, BWN_SHARED, BWN_SHARED_RX_PADOFFSET, 0); bwn_pio_set_txqueue(mac, &pio->wme[WME_AC_BK], 0); bwn_pio_set_txqueue(mac, &pio->wme[WME_AC_BE], 1); bwn_pio_set_txqueue(mac, &pio->wme[WME_AC_VI], 2); bwn_pio_set_txqueue(mac, &pio->wme[WME_AC_VO], 3); bwn_pio_set_txqueue(mac, &pio->mcast, 4); bwn_pio_setupqueue_rx(mac, &pio->rx, 0); } static void bwn_pio_set_txqueue(struct bwn_mac *mac, struct bwn_pio_txqueue *tq, int index) { struct bwn_pio_txpkt *tp; struct bwn_softc *sc = mac->mac_sc; unsigned int i; tq->tq_base = bwn_pio_idx2base(mac, index) + BWN_PIO_TXQOFFSET(mac); tq->tq_index = index; tq->tq_free = BWN_PIO_MAX_TXPACKETS; - if (siba_get_revid(sc->sc_dev) >= 8) + if (bhnd_get_hwrev(sc->sc_dev) >= 8) tq->tq_size = 1920; else { tq->tq_size = bwn_pio_read_2(mac, tq, BWN_PIO_TXQBUFSIZE); tq->tq_size -= 80; } TAILQ_INIT(&tq->tq_pktlist); for (i = 0; i < N(tq->tq_pkts); i++) { tp = &(tq->tq_pkts[i]); tp->tp_index = i; tp->tp_queue = tq; TAILQ_INSERT_TAIL(&tq->tq_pktlist, tp, tp_list); } } static uint16_t bwn_pio_idx2base(struct bwn_mac *mac, int index) { struct bwn_softc *sc = mac->mac_sc; static const uint16_t bases[] = { BWN_PIO_BASE0, BWN_PIO_BASE1, BWN_PIO_BASE2, BWN_PIO_BASE3, BWN_PIO_BASE4, BWN_PIO_BASE5, BWN_PIO_BASE6, BWN_PIO_BASE7, }; static const uint16_t bases_rev11[] = { BWN_PIO11_BASE0, BWN_PIO11_BASE1, BWN_PIO11_BASE2, BWN_PIO11_BASE3, BWN_PIO11_BASE4, BWN_PIO11_BASE5, }; - if (siba_get_revid(sc->sc_dev) >= 11) { + if (bhnd_get_hwrev(sc->sc_dev) >= 11) { if (index >= N(bases_rev11)) device_printf(sc->sc_dev, "%s: warning\n", __func__); return (bases_rev11[index]); } if (index >= N(bases)) device_printf(sc->sc_dev, "%s: warning\n", __func__); return (bases[index]); } static void bwn_pio_setupqueue_rx(struct bwn_mac *mac, struct bwn_pio_rxqueue *prq, int index) { struct bwn_softc *sc = mac->mac_sc; prq->prq_mac = mac; - prq->prq_rev = siba_get_revid(sc->sc_dev); + prq->prq_rev = bhnd_get_hwrev(sc->sc_dev); prq->prq_base = bwn_pio_idx2base(mac, index) + BWN_PIO_RXQOFFSET(mac); bwn_dma_rxdirectfifo(mac, index, 1); } static void bwn_destroy_pioqueue_tx(struct bwn_pio_txqueue *tq) { if (tq == NULL) return; bwn_pio_cancel_tx_packets(tq); } static void bwn_destroy_queue_tx(struct bwn_pio_txqueue *pio) { bwn_destroy_pioqueue_tx(pio); } static uint16_t bwn_pio_read_2(struct bwn_mac *mac, struct bwn_pio_txqueue *tq, uint16_t offset) { return (BWN_READ_2(mac, tq->tq_base + offset)); } static void bwn_dma_rxdirectfifo(struct bwn_mac *mac, int idx, uint8_t enable) { uint32_t ctl; - int type; uint16_t base; - type = bwn_dma_mask2type(bwn_dma_mask(mac)); - base = bwn_dma_base(type, idx); - if (type == BWN_DMA_64BIT) { + base = bwn_dma_base(mac->mac_dmatype, idx); + if (mac->mac_dmatype == BHND_DMA_ADDR_64BIT) { ctl = BWN_READ_4(mac, base + BWN_DMA64_RXCTL); ctl &= ~BWN_DMA64_RXDIRECTFIFO; if (enable) ctl |= BWN_DMA64_RXDIRECTFIFO; BWN_WRITE_4(mac, base + BWN_DMA64_RXCTL, ctl); } else { ctl = BWN_READ_4(mac, base + BWN_DMA32_RXCTL); ctl &= ~BWN_DMA32_RXDIRECTFIFO; if (enable) ctl |= BWN_DMA32_RXDIRECTFIFO; BWN_WRITE_4(mac, base + BWN_DMA32_RXCTL, ctl); } } -static uint64_t -bwn_dma_mask(struct bwn_mac *mac) -{ - uint32_t tmp; - uint16_t base; - - tmp = BWN_READ_4(mac, SIBA_TGSHIGH); - if (tmp & SIBA_TGSHIGH_DMA64) - return (BWN_DMA_BIT_MASK(64)); - base = bwn_dma_base(0, 0); - BWN_WRITE_4(mac, base + BWN_DMA32_TXCTL, BWN_DMA32_TXADDREXT_MASK); - tmp = BWN_READ_4(mac, base + BWN_DMA32_TXCTL); - if (tmp & BWN_DMA32_TXADDREXT_MASK) - return (BWN_DMA_BIT_MASK(32)); - - return (BWN_DMA_BIT_MASK(30)); -} - -static int -bwn_dma_mask2type(uint64_t dmamask) -{ - - if (dmamask == BWN_DMA_BIT_MASK(30)) - return (BWN_DMA_30BIT); - if (dmamask == BWN_DMA_BIT_MASK(32)) - return (BWN_DMA_32BIT); - if (dmamask == BWN_DMA_BIT_MASK(64)) - return (BWN_DMA_64BIT); - KASSERT(0 == 1, ("%s:%d: fail", __func__, __LINE__)); - return (BWN_DMA_30BIT); -} - static void bwn_pio_cancel_tx_packets(struct bwn_pio_txqueue *tq) { struct bwn_pio_txpkt *tp; unsigned int i; for (i = 0; i < N(tq->tq_pkts); i++) { tp = &(tq->tq_pkts[i]); if (tp->tp_m) { m_freem(tp->tp_m); tp->tp_m = NULL; } } } static uint16_t bwn_dma_base(int type, int controller_idx) { static const uint16_t map64[] = { BWN_DMA64_BASE0, BWN_DMA64_BASE1, BWN_DMA64_BASE2, BWN_DMA64_BASE3, BWN_DMA64_BASE4, BWN_DMA64_BASE5, }; static const uint16_t map32[] = { BWN_DMA32_BASE0, BWN_DMA32_BASE1, BWN_DMA32_BASE2, BWN_DMA32_BASE3, BWN_DMA32_BASE4, BWN_DMA32_BASE5, }; - if (type == BWN_DMA_64BIT) { + if (type == BHND_DMA_ADDR_64BIT) { KASSERT(controller_idx >= 0 && controller_idx < N(map64), ("%s:%d: fail", __func__, __LINE__)); return (map64[controller_idx]); } KASSERT(controller_idx >= 0 && controller_idx < N(map32), ("%s:%d: fail", __func__, __LINE__)); return (map32[controller_idx]); } static void bwn_dma_init(struct bwn_mac *mac) { struct bwn_dma *dma = &mac->mac_method.dma; /* setup TX DMA channels. */ bwn_dma_setup(dma->wme[WME_AC_BK]); bwn_dma_setup(dma->wme[WME_AC_BE]); bwn_dma_setup(dma->wme[WME_AC_VI]); bwn_dma_setup(dma->wme[WME_AC_VO]); bwn_dma_setup(dma->mcast); /* setup RX DMA channel. */ bwn_dma_setup(dma->rx); } static struct bwn_dma_ring * bwn_dma_ringsetup(struct bwn_mac *mac, int controller_index, - int for_tx, int type) + int for_tx) { struct bwn_dma *dma = &mac->mac_method.dma; struct bwn_dma_ring *dr; struct bwn_dmadesc_generic *desc; struct bwn_dmadesc_meta *mt; struct bwn_softc *sc = mac->mac_sc; int error, i; dr = malloc(sizeof(*dr), M_DEVBUF, M_NOWAIT | M_ZERO); if (dr == NULL) goto out; dr->dr_numslots = BWN_RXRING_SLOTS; if (for_tx) dr->dr_numslots = BWN_TXRING_SLOTS; dr->dr_meta = malloc(dr->dr_numslots * sizeof(struct bwn_dmadesc_meta), M_DEVBUF, M_NOWAIT | M_ZERO); if (dr->dr_meta == NULL) goto fail0; - dr->dr_type = type; + dr->dr_type = mac->mac_dmatype; dr->dr_mac = mac; - dr->dr_base = bwn_dma_base(type, controller_index); + dr->dr_base = bwn_dma_base(dr->dr_type, controller_index); dr->dr_index = controller_index; - if (type == BWN_DMA_64BIT) { + if (dr->dr_type == BHND_DMA_ADDR_64BIT) { dr->getdesc = bwn_dma_64_getdesc; dr->setdesc = bwn_dma_64_setdesc; dr->start_transfer = bwn_dma_64_start_transfer; dr->suspend = bwn_dma_64_suspend; dr->resume = bwn_dma_64_resume; dr->get_curslot = bwn_dma_64_get_curslot; dr->set_curslot = bwn_dma_64_set_curslot; } else { dr->getdesc = bwn_dma_32_getdesc; dr->setdesc = bwn_dma_32_setdesc; dr->start_transfer = bwn_dma_32_start_transfer; dr->suspend = bwn_dma_32_suspend; dr->resume = bwn_dma_32_resume; dr->get_curslot = bwn_dma_32_get_curslot; dr->set_curslot = bwn_dma_32_set_curslot; } if (for_tx) { dr->dr_tx = 1; dr->dr_curslot = -1; } else { if (dr->dr_index == 0) { switch (mac->mac_fw.fw_hdr_format) { case BWN_FW_HDR_351: case BWN_FW_HDR_410: dr->dr_rx_bufsize = BWN_DMA0_RX_BUFFERSIZE_FW351; dr->dr_frameoffset = BWN_DMA0_RX_FRAMEOFFSET_FW351; break; case BWN_FW_HDR_598: dr->dr_rx_bufsize = BWN_DMA0_RX_BUFFERSIZE_FW598; dr->dr_frameoffset = BWN_DMA0_RX_FRAMEOFFSET_FW598; break; } } else KASSERT(0 == 1, ("%s:%d: fail", __func__, __LINE__)); } error = bwn_dma_allocringmemory(dr); if (error) goto fail2; if (for_tx) { /* * Assumption: BWN_TXRING_SLOTS can be divided by * BWN_TX_SLOTS_PER_FRAME */ KASSERT(BWN_TXRING_SLOTS % BWN_TX_SLOTS_PER_FRAME == 0, ("%s:%d: fail", __func__, __LINE__)); dr->dr_txhdr_cache = contigmalloc( (dr->dr_numslots / BWN_TX_SLOTS_PER_FRAME) * BWN_MAXTXHDRSIZE, M_DEVBUF, M_ZERO, 0, BUS_SPACE_MAXADDR, 8, 0); if (dr->dr_txhdr_cache == NULL) { device_printf(sc->sc_dev, "can't allocate TX header DMA memory\n"); goto fail1; } /* * Create TX ring DMA stuffs */ error = bus_dma_tag_create(dma->parent_dtag, BWN_ALIGN, 0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, BWN_HDRSIZE(mac), 1, BUS_SPACE_MAXSIZE_32BIT, 0, NULL, NULL, &dr->dr_txring_dtag); if (error) { device_printf(sc->sc_dev, "can't create TX ring DMA tag: TODO frees\n"); goto fail2; } for (i = 0; i < dr->dr_numslots; i += 2) { dr->getdesc(dr, i, &desc, &mt); mt->mt_txtype = BWN_DMADESC_METATYPE_HEADER; mt->mt_m = NULL; mt->mt_ni = NULL; mt->mt_islast = 0; error = bus_dmamap_create(dr->dr_txring_dtag, 0, &mt->mt_dmap); if (error) { device_printf(sc->sc_dev, "can't create RX buf DMA map\n"); goto fail2; } dr->getdesc(dr, i + 1, &desc, &mt); mt->mt_txtype = BWN_DMADESC_METATYPE_BODY; mt->mt_m = NULL; mt->mt_ni = NULL; mt->mt_islast = 1; error = bus_dmamap_create(dma->txbuf_dtag, 0, &mt->mt_dmap); if (error) { device_printf(sc->sc_dev, "can't create RX buf DMA map\n"); goto fail2; } } } else { error = bus_dmamap_create(dma->rxbuf_dtag, 0, &dr->dr_spare_dmap); if (error) { device_printf(sc->sc_dev, "can't create RX buf DMA map\n"); goto out; /* XXX wrong! */ } for (i = 0; i < dr->dr_numslots; i++) { dr->getdesc(dr, i, &desc, &mt); error = bus_dmamap_create(dma->rxbuf_dtag, 0, &mt->mt_dmap); if (error) { device_printf(sc->sc_dev, "can't create RX buf DMA map\n"); goto out; /* XXX wrong! */ } error = bwn_dma_newbuf(dr, desc, mt, 1); if (error) { device_printf(sc->sc_dev, "failed to allocate RX buf\n"); goto out; /* XXX wrong! */ } } bus_dmamap_sync(dr->dr_ring_dtag, dr->dr_ring_dmap, BUS_DMASYNC_PREWRITE); dr->dr_usedslot = dr->dr_numslots; } out: return (dr); fail2: if (dr->dr_txhdr_cache != NULL) { contigfree(dr->dr_txhdr_cache, (dr->dr_numslots / BWN_TX_SLOTS_PER_FRAME) * BWN_MAXTXHDRSIZE, M_DEVBUF); } fail1: free(dr->dr_meta, M_DEVBUF); fail0: free(dr, M_DEVBUF); return (NULL); } static void bwn_dma_ringfree(struct bwn_dma_ring **dr) { if (dr == NULL) return; bwn_dma_free_descbufs(*dr); bwn_dma_free_ringmemory(*dr); if ((*dr)->dr_txhdr_cache != NULL) { contigfree((*dr)->dr_txhdr_cache, ((*dr)->dr_numslots / BWN_TX_SLOTS_PER_FRAME) * BWN_MAXTXHDRSIZE, M_DEVBUF); } free((*dr)->dr_meta, M_DEVBUF); free(*dr, M_DEVBUF); *dr = NULL; } static void bwn_dma_32_getdesc(struct bwn_dma_ring *dr, int slot, struct bwn_dmadesc_generic **gdesc, struct bwn_dmadesc_meta **meta) { struct bwn_dmadesc32 *desc; *meta = &(dr->dr_meta[slot]); desc = dr->dr_ring_descbase; desc = &(desc[slot]); *gdesc = (struct bwn_dmadesc_generic *)desc; } static void bwn_dma_32_setdesc(struct bwn_dma_ring *dr, struct bwn_dmadesc_generic *desc, bus_addr_t dmaaddr, uint16_t bufsize, int start, int end, int irq) { - struct bwn_dmadesc32 *descbase = dr->dr_ring_descbase; - struct bwn_softc *sc = dr->dr_mac->mac_sc; - uint32_t addr, addrext, ctl; - int slot; + struct bwn_dmadesc32 *descbase; + struct bwn_dma *dma; + struct bhnd_dma_translation *dt; + uint32_t addr, addrext, ctl; + int slot; + + descbase = dr->dr_ring_descbase; + dma = &dr->dr_mac->mac_method.dma; + dt = &dma->translation; slot = (int)(&(desc->dma.dma32) - descbase); KASSERT(slot >= 0 && slot < dr->dr_numslots, ("%s:%d: fail", __func__, __LINE__)); - addr = (uint32_t) (dmaaddr & ~SIBA_DMA_TRANSLATION_MASK); - addrext = (uint32_t) (dmaaddr & SIBA_DMA_TRANSLATION_MASK) >> 30; - addr |= siba_dma_translation(sc->sc_dev); + addr = (dmaaddr & dt->addr_mask) | dt->base_addr; + addrext = ((dmaaddr & dt->addrext_mask) >> dma->addrext_shift); ctl = bufsize & BWN_DMA32_DCTL_BYTECNT; if (slot == dr->dr_numslots - 1) ctl |= BWN_DMA32_DCTL_DTABLEEND; if (start) ctl |= BWN_DMA32_DCTL_FRAMESTART; if (end) ctl |= BWN_DMA32_DCTL_FRAMEEND; if (irq) ctl |= BWN_DMA32_DCTL_IRQ; ctl |= (addrext << BWN_DMA32_DCTL_ADDREXT_SHIFT) & BWN_DMA32_DCTL_ADDREXT_MASK; desc->dma.dma32.control = htole32(ctl); desc->dma.dma32.address = htole32(addr); } static void bwn_dma_32_start_transfer(struct bwn_dma_ring *dr, int slot) { BWN_DMA_WRITE(dr, BWN_DMA32_TXINDEX, (uint32_t)(slot * sizeof(struct bwn_dmadesc32))); } static void bwn_dma_32_suspend(struct bwn_dma_ring *dr) { BWN_DMA_WRITE(dr, BWN_DMA32_TXCTL, BWN_DMA_READ(dr, BWN_DMA32_TXCTL) | BWN_DMA32_TXSUSPEND); } static void bwn_dma_32_resume(struct bwn_dma_ring *dr) { BWN_DMA_WRITE(dr, BWN_DMA32_TXCTL, BWN_DMA_READ(dr, BWN_DMA32_TXCTL) & ~BWN_DMA32_TXSUSPEND); } static int bwn_dma_32_get_curslot(struct bwn_dma_ring *dr) { uint32_t val; val = BWN_DMA_READ(dr, BWN_DMA32_RXSTATUS); val &= BWN_DMA32_RXDPTR; return (val / sizeof(struct bwn_dmadesc32)); } static void bwn_dma_32_set_curslot(struct bwn_dma_ring *dr, int slot) { BWN_DMA_WRITE(dr, BWN_DMA32_RXINDEX, (uint32_t) (slot * sizeof(struct bwn_dmadesc32))); } static void bwn_dma_64_getdesc(struct bwn_dma_ring *dr, int slot, struct bwn_dmadesc_generic **gdesc, struct bwn_dmadesc_meta **meta) { struct bwn_dmadesc64 *desc; *meta = &(dr->dr_meta[slot]); desc = dr->dr_ring_descbase; desc = &(desc[slot]); *gdesc = (struct bwn_dmadesc_generic *)desc; } static void bwn_dma_64_setdesc(struct bwn_dma_ring *dr, struct bwn_dmadesc_generic *desc, bus_addr_t dmaaddr, uint16_t bufsize, int start, int end, int irq) { - struct bwn_dmadesc64 *descbase = dr->dr_ring_descbase; - struct bwn_softc *sc = dr->dr_mac->mac_sc; - int slot; - uint32_t ctl0 = 0, ctl1 = 0; - uint32_t addrlo, addrhi; - uint32_t addrext; + struct bwn_dmadesc64 *descbase; + struct bwn_dma *dma; + struct bhnd_dma_translation *dt; + bhnd_addr_t addr; + uint32_t addrhi, addrlo; + uint32_t addrext; + uint32_t ctl0, ctl1; + int slot; + + + descbase = dr->dr_ring_descbase; + dma = &dr->dr_mac->mac_method.dma; + dt = &dma->translation; slot = (int)(&(desc->dma.dma64) - descbase); KASSERT(slot >= 0 && slot < dr->dr_numslots, ("%s:%d: fail", __func__, __LINE__)); - addrlo = (uint32_t) (dmaaddr & 0xffffffff); - addrhi = (((uint64_t) dmaaddr >> 32) & ~SIBA_DMA_TRANSLATION_MASK); - addrext = (((uint64_t) dmaaddr >> 32) & SIBA_DMA_TRANSLATION_MASK) >> - 30; - addrhi |= (siba_dma_translation(sc->sc_dev) << 1); + addr = (dmaaddr & dt->addr_mask) | dt->base_addr; + addrhi = (addr >> 32); + addrlo = (addr & UINT32_MAX); + addrext = ((dmaaddr & dt->addrext_mask) >> dma->addrext_shift); + + ctl0 = 0; if (slot == dr->dr_numslots - 1) ctl0 |= BWN_DMA64_DCTL0_DTABLEEND; if (start) ctl0 |= BWN_DMA64_DCTL0_FRAMESTART; if (end) ctl0 |= BWN_DMA64_DCTL0_FRAMEEND; if (irq) ctl0 |= BWN_DMA64_DCTL0_IRQ; + + ctl1 = 0; ctl1 |= bufsize & BWN_DMA64_DCTL1_BYTECNT; ctl1 |= (addrext << BWN_DMA64_DCTL1_ADDREXT_SHIFT) & BWN_DMA64_DCTL1_ADDREXT_MASK; desc->dma.dma64.control0 = htole32(ctl0); desc->dma.dma64.control1 = htole32(ctl1); desc->dma.dma64.address_low = htole32(addrlo); desc->dma.dma64.address_high = htole32(addrhi); } static void bwn_dma_64_start_transfer(struct bwn_dma_ring *dr, int slot) { BWN_DMA_WRITE(dr, BWN_DMA64_TXINDEX, (uint32_t)(slot * sizeof(struct bwn_dmadesc64))); } static void bwn_dma_64_suspend(struct bwn_dma_ring *dr) { BWN_DMA_WRITE(dr, BWN_DMA64_TXCTL, BWN_DMA_READ(dr, BWN_DMA64_TXCTL) | BWN_DMA64_TXSUSPEND); } static void bwn_dma_64_resume(struct bwn_dma_ring *dr) { BWN_DMA_WRITE(dr, BWN_DMA64_TXCTL, BWN_DMA_READ(dr, BWN_DMA64_TXCTL) & ~BWN_DMA64_TXSUSPEND); } static int bwn_dma_64_get_curslot(struct bwn_dma_ring *dr) { uint32_t val; val = BWN_DMA_READ(dr, BWN_DMA64_RXSTATUS); val &= BWN_DMA64_RXSTATDPTR; return (val / sizeof(struct bwn_dmadesc64)); } static void bwn_dma_64_set_curslot(struct bwn_dma_ring *dr, int slot) { BWN_DMA_WRITE(dr, BWN_DMA64_RXINDEX, (uint32_t)(slot * sizeof(struct bwn_dmadesc64))); } static int bwn_dma_allocringmemory(struct bwn_dma_ring *dr) { struct bwn_mac *mac = dr->dr_mac; struct bwn_dma *dma = &mac->mac_method.dma; struct bwn_softc *sc = mac->mac_sc; int error; error = bus_dma_tag_create(dma->parent_dtag, BWN_ALIGN, 0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, BWN_DMA_RINGMEMSIZE, 1, BUS_SPACE_MAXSIZE_32BIT, 0, NULL, NULL, &dr->dr_ring_dtag); if (error) { device_printf(sc->sc_dev, "can't create TX ring DMA tag: TODO frees\n"); return (-1); } error = bus_dmamem_alloc(dr->dr_ring_dtag, &dr->dr_ring_descbase, BUS_DMA_WAITOK | BUS_DMA_ZERO, &dr->dr_ring_dmap); if (error) { device_printf(sc->sc_dev, "can't allocate DMA mem: TODO frees\n"); return (-1); } error = bus_dmamap_load(dr->dr_ring_dtag, dr->dr_ring_dmap, dr->dr_ring_descbase, BWN_DMA_RINGMEMSIZE, bwn_dma_ring_addr, &dr->dr_ring_dmabase, BUS_DMA_NOWAIT); if (error) { device_printf(sc->sc_dev, "can't load DMA mem: TODO free\n"); return (-1); } return (0); } static void bwn_dma_setup(struct bwn_dma_ring *dr) { - struct bwn_softc *sc = dr->dr_mac->mac_sc; - uint64_t ring64; - uint32_t addrext, ring32, value; - uint32_t trans = siba_dma_translation(sc->sc_dev); + struct bwn_mac *mac; + struct bwn_dma *dma; + struct bhnd_dma_translation *dt; + bhnd_addr_t addr, paddr; + uint32_t addrhi, addrlo, addrext, value; + mac = dr->dr_mac; + dma = &mac->mac_method.dma; + dt = &dma->translation; + + paddr = dr->dr_ring_dmabase; + addr = (paddr & dt->addr_mask) | dt->base_addr; + addrhi = (addr >> 32); + addrlo = (addr & UINT32_MAX); + addrext = ((paddr & dt->addrext_mask) >> dma->addrext_shift); + if (dr->dr_tx) { dr->dr_curslot = -1; - if (dr->dr_type == BWN_DMA_64BIT) { - ring64 = (uint64_t)(dr->dr_ring_dmabase); - addrext = ((ring64 >> 32) & SIBA_DMA_TRANSLATION_MASK) - >> 30; + if (dr->dr_type == BHND_DMA_ADDR_64BIT) { value = BWN_DMA64_TXENABLE; value |= BWN_DMA64_TXPARITY_DISABLE; value |= (addrext << BWN_DMA64_TXADDREXT_SHIFT) & BWN_DMA64_TXADDREXT_MASK; BWN_DMA_WRITE(dr, BWN_DMA64_TXCTL, value); - BWN_DMA_WRITE(dr, BWN_DMA64_TXRINGLO, - (ring64 & 0xffffffff)); - BWN_DMA_WRITE(dr, BWN_DMA64_TXRINGHI, - ((ring64 >> 32) & - ~SIBA_DMA_TRANSLATION_MASK) | (trans << 1)); + BWN_DMA_WRITE(dr, BWN_DMA64_TXRINGLO, addrlo); + BWN_DMA_WRITE(dr, BWN_DMA64_TXRINGHI, addrhi); } else { - ring32 = (uint32_t)(dr->dr_ring_dmabase); - addrext = (ring32 & SIBA_DMA_TRANSLATION_MASK) >> 30; value = BWN_DMA32_TXENABLE; value |= BWN_DMA32_TXPARITY_DISABLE; value |= (addrext << BWN_DMA32_TXADDREXT_SHIFT) & BWN_DMA32_TXADDREXT_MASK; BWN_DMA_WRITE(dr, BWN_DMA32_TXCTL, value); - BWN_DMA_WRITE(dr, BWN_DMA32_TXRING, - (ring32 & ~SIBA_DMA_TRANSLATION_MASK) | trans); + BWN_DMA_WRITE(dr, BWN_DMA32_TXRING, addrlo); } return; } /* * set for RX */ dr->dr_usedslot = dr->dr_numslots; - if (dr->dr_type == BWN_DMA_64BIT) { - ring64 = (uint64_t)(dr->dr_ring_dmabase); - addrext = ((ring64 >> 32) & SIBA_DMA_TRANSLATION_MASK) >> 30; + if (dr->dr_type == BHND_DMA_ADDR_64BIT) { value = (dr->dr_frameoffset << BWN_DMA64_RXFROFF_SHIFT); value |= BWN_DMA64_RXENABLE; value |= BWN_DMA64_RXPARITY_DISABLE; value |= (addrext << BWN_DMA64_RXADDREXT_SHIFT) & BWN_DMA64_RXADDREXT_MASK; BWN_DMA_WRITE(dr, BWN_DMA64_RXCTL, value); - BWN_DMA_WRITE(dr, BWN_DMA64_RXRINGLO, (ring64 & 0xffffffff)); - BWN_DMA_WRITE(dr, BWN_DMA64_RXRINGHI, - ((ring64 >> 32) & ~SIBA_DMA_TRANSLATION_MASK) - | (trans << 1)); + BWN_DMA_WRITE(dr, BWN_DMA64_RXRINGLO, addrlo); + BWN_DMA_WRITE(dr, BWN_DMA64_RXRINGHI, addrhi); BWN_DMA_WRITE(dr, BWN_DMA64_RXINDEX, dr->dr_numslots * sizeof(struct bwn_dmadesc64)); } else { - ring32 = (uint32_t)(dr->dr_ring_dmabase); - addrext = (ring32 & SIBA_DMA_TRANSLATION_MASK) >> 30; value = (dr->dr_frameoffset << BWN_DMA32_RXFROFF_SHIFT); value |= BWN_DMA32_RXENABLE; value |= BWN_DMA32_RXPARITY_DISABLE; value |= (addrext << BWN_DMA32_RXADDREXT_SHIFT) & BWN_DMA32_RXADDREXT_MASK; BWN_DMA_WRITE(dr, BWN_DMA32_RXCTL, value); - BWN_DMA_WRITE(dr, BWN_DMA32_RXRING, - (ring32 & ~SIBA_DMA_TRANSLATION_MASK) | trans); + BWN_DMA_WRITE(dr, BWN_DMA32_RXRING, addrlo); BWN_DMA_WRITE(dr, BWN_DMA32_RXINDEX, dr->dr_numslots * sizeof(struct bwn_dmadesc32)); } } static void bwn_dma_free_ringmemory(struct bwn_dma_ring *dr) { bus_dmamap_unload(dr->dr_ring_dtag, dr->dr_ring_dmap); bus_dmamem_free(dr->dr_ring_dtag, dr->dr_ring_descbase, dr->dr_ring_dmap); } static void bwn_dma_cleanup(struct bwn_dma_ring *dr) { if (dr->dr_tx) { bwn_dma_tx_reset(dr->dr_mac, dr->dr_base, dr->dr_type); - if (dr->dr_type == BWN_DMA_64BIT) { + if (dr->dr_type == BHND_DMA_ADDR_64BIT) { BWN_DMA_WRITE(dr, BWN_DMA64_TXRINGLO, 0); BWN_DMA_WRITE(dr, BWN_DMA64_TXRINGHI, 0); } else BWN_DMA_WRITE(dr, BWN_DMA32_TXRING, 0); } else { bwn_dma_rx_reset(dr->dr_mac, dr->dr_base, dr->dr_type); - if (dr->dr_type == BWN_DMA_64BIT) { + if (dr->dr_type == BHND_DMA_ADDR_64BIT) { BWN_DMA_WRITE(dr, BWN_DMA64_RXRINGLO, 0); BWN_DMA_WRITE(dr, BWN_DMA64_RXRINGHI, 0); } else BWN_DMA_WRITE(dr, BWN_DMA32_RXRING, 0); } } static void bwn_dma_free_descbufs(struct bwn_dma_ring *dr) { struct bwn_dmadesc_generic *desc; struct bwn_dmadesc_meta *meta; struct bwn_mac *mac = dr->dr_mac; struct bwn_dma *dma = &mac->mac_method.dma; struct bwn_softc *sc = mac->mac_sc; int i; if (!dr->dr_usedslot) return; for (i = 0; i < dr->dr_numslots; i++) { dr->getdesc(dr, i, &desc, &meta); if (meta->mt_m == NULL) { if (!dr->dr_tx) device_printf(sc->sc_dev, "%s: not TX?\n", __func__); continue; } if (dr->dr_tx) { if (meta->mt_txtype == BWN_DMADESC_METATYPE_HEADER) bus_dmamap_unload(dr->dr_txring_dtag, meta->mt_dmap); else if (meta->mt_txtype == BWN_DMADESC_METATYPE_BODY) bus_dmamap_unload(dma->txbuf_dtag, meta->mt_dmap); } else bus_dmamap_unload(dma->rxbuf_dtag, meta->mt_dmap); bwn_dma_free_descbuf(dr, meta); } } static int bwn_dma_tx_reset(struct bwn_mac *mac, uint16_t base, int type) { struct bwn_softc *sc = mac->mac_sc; uint32_t value; int i; uint16_t offset; for (i = 0; i < 10; i++) { - offset = (type == BWN_DMA_64BIT) ? BWN_DMA64_TXSTATUS : + offset = (type == BHND_DMA_ADDR_64BIT) ? BWN_DMA64_TXSTATUS : BWN_DMA32_TXSTATUS; value = BWN_READ_4(mac, base + offset); - if (type == BWN_DMA_64BIT) { + if (type == BHND_DMA_ADDR_64BIT) { value &= BWN_DMA64_TXSTAT; if (value == BWN_DMA64_TXSTAT_DISABLED || value == BWN_DMA64_TXSTAT_IDLEWAIT || value == BWN_DMA64_TXSTAT_STOPPED) break; } else { value &= BWN_DMA32_TXSTATE; if (value == BWN_DMA32_TXSTAT_DISABLED || value == BWN_DMA32_TXSTAT_IDLEWAIT || value == BWN_DMA32_TXSTAT_STOPPED) break; } DELAY(1000); } - offset = (type == BWN_DMA_64BIT) ? BWN_DMA64_TXCTL : BWN_DMA32_TXCTL; + offset = (type == BHND_DMA_ADDR_64BIT) ? BWN_DMA64_TXCTL : + BWN_DMA32_TXCTL; BWN_WRITE_4(mac, base + offset, 0); for (i = 0; i < 10; i++) { - offset = (type == BWN_DMA_64BIT) ? BWN_DMA64_TXSTATUS : - BWN_DMA32_TXSTATUS; + offset = (type == BHND_DMA_ADDR_64BIT) ? BWN_DMA64_TXSTATUS : + BWN_DMA32_TXSTATUS; value = BWN_READ_4(mac, base + offset); - if (type == BWN_DMA_64BIT) { + if (type == BHND_DMA_ADDR_64BIT) { value &= BWN_DMA64_TXSTAT; if (value == BWN_DMA64_TXSTAT_DISABLED) { i = -1; break; } } else { value &= BWN_DMA32_TXSTATE; if (value == BWN_DMA32_TXSTAT_DISABLED) { i = -1; break; } } DELAY(1000); } if (i != -1) { device_printf(sc->sc_dev, "%s: timed out\n", __func__); return (ENODEV); } DELAY(1000); return (0); } static int bwn_dma_rx_reset(struct bwn_mac *mac, uint16_t base, int type) { struct bwn_softc *sc = mac->mac_sc; uint32_t value; int i; uint16_t offset; - offset = (type == BWN_DMA_64BIT) ? BWN_DMA64_RXCTL : BWN_DMA32_RXCTL; + offset = (type == BHND_DMA_ADDR_64BIT) ? BWN_DMA64_RXCTL : + BWN_DMA32_RXCTL; BWN_WRITE_4(mac, base + offset, 0); for (i = 0; i < 10; i++) { - offset = (type == BWN_DMA_64BIT) ? BWN_DMA64_RXSTATUS : + offset = (type == BHND_DMA_ADDR_64BIT) ? BWN_DMA64_RXSTATUS : BWN_DMA32_RXSTATUS; value = BWN_READ_4(mac, base + offset); - if (type == BWN_DMA_64BIT) { + if (type == BHND_DMA_ADDR_64BIT) { value &= BWN_DMA64_RXSTAT; if (value == BWN_DMA64_RXSTAT_DISABLED) { i = -1; break; } } else { value &= BWN_DMA32_RXSTATE; if (value == BWN_DMA32_RXSTAT_DISABLED) { i = -1; break; } } DELAY(1000); } if (i != -1) { device_printf(sc->sc_dev, "%s: timed out\n", __func__); return (ENODEV); } return (0); } static void bwn_dma_free_descbuf(struct bwn_dma_ring *dr, struct bwn_dmadesc_meta *meta) { if (meta->mt_m != NULL) { m_freem(meta->mt_m); meta->mt_m = NULL; } if (meta->mt_ni != NULL) { ieee80211_free_node(meta->mt_ni); meta->mt_ni = NULL; } } static void bwn_dma_set_redzone(struct bwn_dma_ring *dr, struct mbuf *m) { struct bwn_rxhdr4 *rxhdr; unsigned char *frame; rxhdr = mtod(m, struct bwn_rxhdr4 *); rxhdr->frame_len = 0; KASSERT(dr->dr_rx_bufsize >= dr->dr_frameoffset + sizeof(struct bwn_plcp6) + 2, ("%s:%d: fail", __func__, __LINE__)); frame = mtod(m, char *) + dr->dr_frameoffset; memset(frame, 0xff, sizeof(struct bwn_plcp6) + 2 /* padding */); } static uint8_t bwn_dma_check_redzone(struct bwn_dma_ring *dr, struct mbuf *m) { unsigned char *f = mtod(m, char *) + dr->dr_frameoffset; return ((f[0] & f[1] & f[2] & f[3] & f[4] & f[5] & f[6] & f[7]) == 0xff); } static void bwn_wme_init(struct bwn_mac *mac) { bwn_wme_load(mac); /* enable WME support. */ bwn_hf_write(mac, bwn_hf_read(mac) | BWN_HF_EDCF); BWN_WRITE_2(mac, BWN_IFSCTL, BWN_READ_2(mac, BWN_IFSCTL) | BWN_IFSCTL_USE_EDCF); } static void bwn_spu_setdelay(struct bwn_mac *mac, int idle) { struct bwn_softc *sc = mac->mac_sc; struct ieee80211com *ic = &sc->sc_ic; uint16_t delay; /* microsec */ delay = (mac->mac_phy.type == BWN_PHYTYPE_A) ? 3700 : 1050; if (ic->ic_opmode == IEEE80211_M_IBSS || idle) delay = 500; if ((mac->mac_phy.rf_ver == 0x2050) && (mac->mac_phy.rf_rev == 8)) delay = max(delay, (uint16_t)2400); bwn_shm_write_2(mac, BWN_SHARED, BWN_SHARED_SPU_WAKEUP, delay); } static void bwn_bt_enable(struct bwn_mac *mac) { struct bwn_softc *sc = mac->mac_sc; uint64_t hf; if (bwn_bluetooth == 0) return; - if ((siba_sprom_get_bf_lo(sc->sc_dev) & BWN_BFL_BTCOEXIST) == 0) + if ((sc->sc_board_info.board_flags & BHND_BFL_BTCOEX) == 0) return; if (mac->mac_phy.type != BWN_PHYTYPE_B && !mac->mac_phy.gmode) return; hf = bwn_hf_read(mac); - if (siba_sprom_get_bf_lo(sc->sc_dev) & BWN_BFL_BTCMOD) + if (sc->sc_board_info.board_flags & BHND_BFL_BTC2WIRE_ALTGPIO) hf |= BWN_HF_BT_COEXISTALT; else hf |= BWN_HF_BT_COEXIST; bwn_hf_write(mac, hf); } static void bwn_set_macaddr(struct bwn_mac *mac) { bwn_mac_write_bssid(mac); bwn_mac_setfilter(mac, BWN_MACFILTER_SELF, mac->mac_sc->sc_ic.ic_macaddr); } static void bwn_clear_keys(struct bwn_mac *mac) { int i; for (i = 0; i < mac->mac_max_nr_keys; i++) { KASSERT(i >= 0 && i < mac->mac_max_nr_keys, ("%s:%d: fail", __func__, __LINE__)); bwn_key_dowrite(mac, i, BWN_SEC_ALGO_NONE, NULL, BWN_SEC_KEYSIZE, NULL); if ((i <= 3) && !BWN_SEC_NEWAPI(mac)) { bwn_key_dowrite(mac, i + 4, BWN_SEC_ALGO_NONE, NULL, BWN_SEC_KEYSIZE, NULL); } mac->mac_key[i].keyconf = NULL; } } static void bwn_crypt_init(struct bwn_mac *mac) { struct bwn_softc *sc = mac->mac_sc; - mac->mac_max_nr_keys = (siba_get_revid(sc->sc_dev) >= 5) ? 58 : 20; + mac->mac_max_nr_keys = (bhnd_get_hwrev(sc->sc_dev) >= 5) ? 58 : 20; KASSERT(mac->mac_max_nr_keys <= N(mac->mac_key), ("%s:%d: fail", __func__, __LINE__)); mac->mac_ktp = bwn_shm_read_2(mac, BWN_SHARED, BWN_SHARED_KEY_TABLEP); mac->mac_ktp *= 2; - if (siba_get_revid(sc->sc_dev) >= 5) + if (bhnd_get_hwrev(sc->sc_dev) >= 5) BWN_WRITE_2(mac, BWN_RCMTA_COUNT, mac->mac_max_nr_keys - 8); bwn_clear_keys(mac); } static void bwn_chip_exit(struct bwn_mac *mac) { - struct bwn_softc *sc = mac->mac_sc; - bwn_phy_exit(mac); - siba_gpio_set(sc->sc_dev, 0); } static int bwn_fw_fillinfo(struct bwn_mac *mac) { int error; error = bwn_fw_gets(mac, BWN_FWTYPE_DEFAULT); if (error == 0) return (0); error = bwn_fw_gets(mac, BWN_FWTYPE_OPENSOURCE); if (error == 0) return (0); return (error); } +/** + * Request that the GPIO controller tristate all pins set in @p mask, granting + * the MAC core control over the pins. + * + * @param mac bwn MAC state. + * @param pins If the bit position for a pin number is set to one, tristate the + * pin. + */ +int +bwn_gpio_control(struct bwn_mac *mac, uint32_t pins) +{ + struct bwn_softc *sc; + uint32_t flags[32]; + int error; + + sc = mac->mac_sc; + + /* Determine desired pin flags */ + for (size_t pin = 0; pin < nitems(flags); pin++) { + uint32_t pinbit = (1 << pin); + + if (pins & pinbit) { + /* Tristate output */ + flags[pin] = GPIO_PIN_OUTPUT|GPIO_PIN_TRISTATE; + } else { + /* Leave unmodified */ + flags[pin] = 0; + } + } + + /* Configure all pins */ + error = GPIO_PIN_CONFIG_32(sc->sc_gpio, 0, nitems(flags), flags); + if (error) { + device_printf(sc->sc_dev, "error configuring %s pin flags: " + "%d\n", device_get_nameunit(sc->sc_gpio), error); + return (error); + } + + return (0); +} + + static int bwn_gpio_init(struct bwn_mac *mac) { - struct bwn_softc *sc = mac->mac_sc; - uint32_t mask = 0x1f, set = 0xf, value; + struct bwn_softc *sc; + uint32_t pins; + sc = mac->mac_sc; + + pins = 0xF; + BWN_WRITE_4(mac, BWN_MACCTL, BWN_READ_4(mac, BWN_MACCTL) & ~BWN_MACCTL_GPOUT_MASK); BWN_WRITE_2(mac, BWN_GPIO_MASK, - BWN_READ_2(mac, BWN_GPIO_MASK) | 0x000f); + BWN_READ_2(mac, BWN_GPIO_MASK) | pins); - if (siba_get_chipid(sc->sc_dev) == 0x4301) { - mask |= 0x0060; - set |= 0x0060; - } - if (siba_sprom_get_bf_lo(sc->sc_dev) & BWN_BFL_PACTRL) { + if (sc->sc_board_info.board_flags & BHND_BFL_PACTRL) { + /* MAC core is responsible for toggling PAREF via gpio9 */ BWN_WRITE_2(mac, BWN_GPIO_MASK, - BWN_READ_2(mac, BWN_GPIO_MASK) | 0x0200); - mask |= 0x0200; - set |= 0x0200; + BWN_READ_2(mac, BWN_GPIO_MASK) | BHND_GPIO_BOARD_PACTRL); + + pins |= BHND_GPIO_BOARD_PACTRL; } - if (siba_get_revid(sc->sc_dev) >= 2) - mask |= 0x0010; - value = siba_gpio_get(sc->sc_dev); - if (value == -1) - return (0); - siba_gpio_set(sc->sc_dev, (value & mask) | set); - - return (0); + return (bwn_gpio_control(mac, pins)); } static int bwn_fw_loadinitvals(struct bwn_mac *mac) { #define GETFWOFFSET(fwp, offset) \ ((const struct bwn_fwinitvals *)((const char *)fwp.fw->data + offset)) const size_t hdr_len = sizeof(struct bwn_fwhdr); const struct bwn_fwhdr *hdr; struct bwn_fw *fw = &mac->mac_fw; int error; hdr = (const struct bwn_fwhdr *)(fw->initvals.fw->data); error = bwn_fwinitvals_write(mac, GETFWOFFSET(fw->initvals, hdr_len), be32toh(hdr->size), fw->initvals.fw->datasize - hdr_len); if (error) return (error); if (fw->initvals_band.fw) { hdr = (const struct bwn_fwhdr *)(fw->initvals_band.fw->data); error = bwn_fwinitvals_write(mac, GETFWOFFSET(fw->initvals_band, hdr_len), be32toh(hdr->size), fw->initvals_band.fw->datasize - hdr_len); } return (error); #undef GETFWOFFSET } static int bwn_phy_init(struct bwn_mac *mac) { struct bwn_softc *sc = mac->mac_sc; int error; mac->mac_phy.chan = mac->mac_phy.get_default_chan(mac); mac->mac_phy.rf_onoff(mac, 1); error = mac->mac_phy.init(mac); if (error) { device_printf(sc->sc_dev, "PHY init failed\n"); goto fail0; } error = bwn_switch_channel(mac, mac->mac_phy.get_default_chan(mac)); if (error) { device_printf(sc->sc_dev, "failed to switch default channel\n"); goto fail1; } return (0); fail1: if (mac->mac_phy.exit) mac->mac_phy.exit(mac); fail0: mac->mac_phy.rf_onoff(mac, 0); return (error); } static void bwn_set_txantenna(struct bwn_mac *mac, int antenna) { uint16_t ant; uint16_t tmp; ant = bwn_ant2phy(antenna); /* For ACK/CTS */ tmp = bwn_shm_read_2(mac, BWN_SHARED, BWN_SHARED_ACKCTS_PHYCTL); tmp = (tmp & ~BWN_TX_PHY_ANT) | ant; bwn_shm_write_2(mac, BWN_SHARED, BWN_SHARED_ACKCTS_PHYCTL, tmp); /* For Probe Resposes */ tmp = bwn_shm_read_2(mac, BWN_SHARED, BWN_SHARED_PROBE_RESP_PHYCTL); tmp = (tmp & ~BWN_TX_PHY_ANT) | ant; bwn_shm_write_2(mac, BWN_SHARED, BWN_SHARED_PROBE_RESP_PHYCTL, tmp); } static void bwn_set_opmode(struct bwn_mac *mac) { struct bwn_softc *sc = mac->mac_sc; struct ieee80211com *ic = &sc->sc_ic; uint32_t ctl; uint16_t cfp_pretbtt; ctl = BWN_READ_4(mac, BWN_MACCTL); ctl &= ~(BWN_MACCTL_HOSTAP | BWN_MACCTL_PASS_CTL | BWN_MACCTL_PASS_BADPLCP | BWN_MACCTL_PASS_BADFCS | BWN_MACCTL_PROMISC | BWN_MACCTL_BEACON_PROMISC); ctl |= BWN_MACCTL_STA; if (ic->ic_opmode == IEEE80211_M_HOSTAP || ic->ic_opmode == IEEE80211_M_MBSS) ctl |= BWN_MACCTL_HOSTAP; else if (ic->ic_opmode == IEEE80211_M_IBSS) ctl &= ~BWN_MACCTL_STA; ctl |= sc->sc_filters; - if (siba_get_revid(sc->sc_dev) <= 4) + if (bhnd_get_hwrev(sc->sc_dev) <= 4) ctl |= BWN_MACCTL_PROMISC; BWN_WRITE_4(mac, BWN_MACCTL, ctl); cfp_pretbtt = 2; if ((ctl & BWN_MACCTL_STA) && !(ctl & BWN_MACCTL_HOSTAP)) { - if (siba_get_chipid(sc->sc_dev) == 0x4306 && - siba_get_chiprev(sc->sc_dev) == 3) + if (sc->sc_cid.chip_id == BHND_CHIPID_BCM4306 && + sc->sc_cid.chip_rev == 3) cfp_pretbtt = 100; else cfp_pretbtt = 50; } BWN_WRITE_2(mac, 0x612, cfp_pretbtt); } -static int -bwn_dma_gettype(struct bwn_mac *mac) -{ - uint32_t tmp; - uint16_t base; - - tmp = BWN_READ_4(mac, SIBA_TGSHIGH); - if (tmp & SIBA_TGSHIGH_DMA64) - return (BWN_DMA_64BIT); - base = bwn_dma_base(0, 0); - BWN_WRITE_4(mac, base + BWN_DMA32_TXCTL, BWN_DMA32_TXADDREXT_MASK); - tmp = BWN_READ_4(mac, base + BWN_DMA32_TXCTL); - if (tmp & BWN_DMA32_TXADDREXT_MASK) - return (BWN_DMA_32BIT); - - return (BWN_DMA_30BIT); -} - static void bwn_dma_ring_addr(void *arg, bus_dma_segment_t *seg, int nseg, int error) { if (!error) { KASSERT(nseg == 1, ("too many segments(%d)\n", nseg)); *((bus_addr_t *)arg) = seg->ds_addr; } } void bwn_dummy_transmission(struct bwn_mac *mac, int ofdm, int paon) { struct bwn_phy *phy = &mac->mac_phy; struct bwn_softc *sc = mac->mac_sc; unsigned int i, max_loop; uint16_t value; uint32_t buffer[5] = { 0x00000000, 0x00d40000, 0x00000000, 0x01000000, 0x00000000 }; if (ofdm) { max_loop = 0x1e; buffer[0] = 0x000201cc; } else { max_loop = 0xfa; buffer[0] = 0x000b846e; } BWN_ASSERT_LOCKED(mac->mac_sc); for (i = 0; i < 5; i++) bwn_ram_write(mac, i * 4, buffer[i]); BWN_WRITE_2(mac, 0x0568, 0x0000); BWN_WRITE_2(mac, 0x07c0, - (siba_get_revid(sc->sc_dev) < 11) ? 0x0000 : 0x0100); + (bhnd_get_hwrev(sc->sc_dev) < 11) ? 0x0000 : 0x0100); value = (ofdm ? 0x41 : 0x40); BWN_WRITE_2(mac, 0x050c, value); if (phy->type == BWN_PHYTYPE_N || phy->type == BWN_PHYTYPE_LP || phy->type == BWN_PHYTYPE_LCN) BWN_WRITE_2(mac, 0x0514, 0x1a02); BWN_WRITE_2(mac, 0x0508, 0x0000); BWN_WRITE_2(mac, 0x050a, 0x0000); BWN_WRITE_2(mac, 0x054c, 0x0000); BWN_WRITE_2(mac, 0x056a, 0x0014); BWN_WRITE_2(mac, 0x0568, 0x0826); BWN_WRITE_2(mac, 0x0500, 0x0000); /* XXX TODO: n phy pa override? */ switch (phy->type) { case BWN_PHYTYPE_N: case BWN_PHYTYPE_LCN: BWN_WRITE_2(mac, 0x0502, 0x00d0); break; case BWN_PHYTYPE_LP: BWN_WRITE_2(mac, 0x0502, 0x0050); break; default: BWN_WRITE_2(mac, 0x0502, 0x0030); break; } /* flush */ BWN_READ_2(mac, 0x0502); if (phy->rf_ver == 0x2050 && phy->rf_rev <= 0x5) BWN_RF_WRITE(mac, 0x0051, 0x0017); for (i = 0x00; i < max_loop; i++) { value = BWN_READ_2(mac, 0x050e); if (value & 0x0080) break; DELAY(10); } for (i = 0x00; i < 0x0a; i++) { value = BWN_READ_2(mac, 0x050e); if (value & 0x0400) break; DELAY(10); } for (i = 0x00; i < 0x19; i++) { value = BWN_READ_2(mac, 0x0690); if (!(value & 0x0100)) break; DELAY(10); } if (phy->rf_ver == 0x2050 && phy->rf_rev <= 0x5) BWN_RF_WRITE(mac, 0x0051, 0x0037); } void bwn_ram_write(struct bwn_mac *mac, uint16_t offset, uint32_t val) { uint32_t macctl; KASSERT(offset % 4 == 0, ("%s:%d: fail", __func__, __LINE__)); macctl = BWN_READ_4(mac, BWN_MACCTL); if (macctl & BWN_MACCTL_BIGENDIAN) printf("TODO: need swap\n"); BWN_WRITE_4(mac, BWN_RAM_CONTROL, offset); - BWN_BARRIER(mac, BUS_SPACE_BARRIER_WRITE); + BWN_BARRIER(mac, BWN_RAM_CONTROL, 4, BUS_SPACE_BARRIER_WRITE); BWN_WRITE_4(mac, BWN_RAM_DATA, val); } void bwn_mac_suspend(struct bwn_mac *mac) { struct bwn_softc *sc = mac->mac_sc; int i; uint32_t tmp; KASSERT(mac->mac_suspended >= 0, ("%s:%d: fail", __func__, __LINE__)); DPRINTF(mac->mac_sc, BWN_DEBUG_RESET, "%s: suspended=%d\n", __func__, mac->mac_suspended); if (mac->mac_suspended == 0) { bwn_psctl(mac, BWN_PS_AWAKE); BWN_WRITE_4(mac, BWN_MACCTL, BWN_READ_4(mac, BWN_MACCTL) & ~BWN_MACCTL_ON); BWN_READ_4(mac, BWN_MACCTL); for (i = 35; i; i--) { tmp = BWN_READ_4(mac, BWN_INTR_REASON); if (tmp & BWN_INTR_MAC_SUSPENDED) goto out; DELAY(10); } for (i = 40; i; i--) { tmp = BWN_READ_4(mac, BWN_INTR_REASON); if (tmp & BWN_INTR_MAC_SUSPENDED) goto out; DELAY(1000); } device_printf(sc->sc_dev, "MAC suspend failed\n"); } out: mac->mac_suspended++; } void bwn_mac_enable(struct bwn_mac *mac) { struct bwn_softc *sc = mac->mac_sc; uint16_t state; DPRINTF(mac->mac_sc, BWN_DEBUG_RESET, "%s: suspended=%d\n", __func__, mac->mac_suspended); state = bwn_shm_read_2(mac, BWN_SHARED, BWN_SHARED_UCODESTAT); if (state != BWN_SHARED_UCODESTAT_SUSPEND && state != BWN_SHARED_UCODESTAT_SLEEP) { DPRINTF(sc, BWN_DEBUG_FW, "%s: warn: firmware state (%d)\n", __func__, state); } mac->mac_suspended--; KASSERT(mac->mac_suspended >= 0, ("%s:%d: fail", __func__, __LINE__)); if (mac->mac_suspended == 0) { BWN_WRITE_4(mac, BWN_MACCTL, BWN_READ_4(mac, BWN_MACCTL) | BWN_MACCTL_ON); BWN_WRITE_4(mac, BWN_INTR_REASON, BWN_INTR_MAC_SUSPENDED); BWN_READ_4(mac, BWN_MACCTL); BWN_READ_4(mac, BWN_INTR_REASON); bwn_psctl(mac, 0); } } void bwn_psctl(struct bwn_mac *mac, uint32_t flags) { struct bwn_softc *sc = mac->mac_sc; int i; uint16_t ucstat; KASSERT(!((flags & BWN_PS_ON) && (flags & BWN_PS_OFF)), ("%s:%d: fail", __func__, __LINE__)); KASSERT(!((flags & BWN_PS_AWAKE) && (flags & BWN_PS_ASLEEP)), ("%s:%d: fail", __func__, __LINE__)); /* XXX forcibly awake and hwps-off */ BWN_WRITE_4(mac, BWN_MACCTL, (BWN_READ_4(mac, BWN_MACCTL) | BWN_MACCTL_AWAKE) & ~BWN_MACCTL_HWPS); BWN_READ_4(mac, BWN_MACCTL); - if (siba_get_revid(sc->sc_dev) >= 5) { + if (bhnd_get_hwrev(sc->sc_dev) >= 5) { for (i = 0; i < 100; i++) { ucstat = bwn_shm_read_2(mac, BWN_SHARED, BWN_SHARED_UCODESTAT); if (ucstat != BWN_SHARED_UCODESTAT_SLEEP) break; DELAY(10); } } DPRINTF(mac->mac_sc, BWN_DEBUG_RESET, "%s: ucstat=%d\n", __func__, ucstat); } static int bwn_fw_gets(struct bwn_mac *mac, enum bwn_fwtype type) { struct bwn_softc *sc = mac->mac_sc; struct bwn_fw *fw = &mac->mac_fw; - const uint8_t rev = siba_get_revid(sc->sc_dev); + const uint8_t rev = bhnd_get_hwrev(sc->sc_dev); const char *filename; - uint32_t high; + uint16_t iost; int error; /* microcode */ filename = NULL; switch (rev) { case 42: if (mac->mac_phy.type == BWN_PHYTYPE_AC) filename = "ucode42"; break; case 40: if (mac->mac_phy.type == BWN_PHYTYPE_AC) filename = "ucode40"; break; case 33: if (mac->mac_phy.type == BWN_PHYTYPE_LCN40) filename = "ucode33_lcn40"; break; case 30: if (mac->mac_phy.type == BWN_PHYTYPE_N) filename = "ucode30_mimo"; break; case 29: if (mac->mac_phy.type == BWN_PHYTYPE_HT) filename = "ucode29_mimo"; break; case 26: if (mac->mac_phy.type == BWN_PHYTYPE_HT) filename = "ucode26_mimo"; break; case 28: case 25: if (mac->mac_phy.type == BWN_PHYTYPE_N) filename = "ucode25_mimo"; else if (mac->mac_phy.type == BWN_PHYTYPE_LCN) filename = "ucode25_lcn"; break; case 24: if (mac->mac_phy.type == BWN_PHYTYPE_LCN) filename = "ucode24_lcn"; break; case 23: if (mac->mac_phy.type == BWN_PHYTYPE_N) filename = "ucode16_mimo"; break; case 16: case 17: case 18: case 19: if (mac->mac_phy.type == BWN_PHYTYPE_N) filename = "ucode16_mimo"; else if (mac->mac_phy.type == BWN_PHYTYPE_LP) filename = "ucode16_lp"; break; case 15: filename = "ucode15"; break; case 14: filename = "ucode14"; break; case 13: filename = "ucode13"; break; case 12: case 11: filename = "ucode11"; break; case 10: case 9: case 8: case 7: case 6: case 5: filename = "ucode5"; break; default: device_printf(sc->sc_dev, "no ucode for rev %d\n", rev); bwn_release_firmware(mac); return (EOPNOTSUPP); } device_printf(sc->sc_dev, "ucode fw: %s\n", filename); error = bwn_fw_get(mac, type, filename, &fw->ucode); if (error) { bwn_release_firmware(mac); return (error); } /* PCM */ KASSERT(fw->no_pcmfile == 0, ("%s:%d fail", __func__, __LINE__)); if (rev >= 5 && rev <= 10) { error = bwn_fw_get(mac, type, "pcm5", &fw->pcm); if (error == ENOENT) fw->no_pcmfile = 1; else if (error) { bwn_release_firmware(mac); return (error); } } else if (rev < 11) { device_printf(sc->sc_dev, "no PCM for rev %d\n", rev); bwn_release_firmware(mac); return (EOPNOTSUPP); } /* initvals */ - high = siba_read_4(sc->sc_dev, SIBA_TGSHIGH); + error = bhnd_read_iost(sc->sc_dev, &iost); + if (error) + goto fail1; + switch (mac->mac_phy.type) { case BWN_PHYTYPE_A: if (rev < 5 || rev > 10) goto fail1; - if (high & BWN_TGSHIGH_HAVE_2GHZ) + if (iost & BWN_IOST_HAVE_2GHZ) filename = "a0g1initvals5"; else filename = "a0g0initvals5"; break; case BWN_PHYTYPE_G: if (rev >= 5 && rev <= 10) filename = "b0g0initvals5"; else if (rev >= 13) filename = "b0g0initvals13"; else goto fail1; break; case BWN_PHYTYPE_LP: if (rev == 13) filename = "lp0initvals13"; else if (rev == 14) filename = "lp0initvals14"; else if (rev >= 15) filename = "lp0initvals15"; else goto fail1; break; case BWN_PHYTYPE_N: if (rev == 30) filename = "n16initvals30"; else if (rev == 28 || rev == 25) filename = "n0initvals25"; else if (rev == 24) filename = "n0initvals24"; else if (rev == 23) filename = "n0initvals16"; else if (rev >= 16 && rev <= 18) filename = "n0initvals16"; else if (rev >= 11 && rev <= 12) filename = "n0initvals11"; else goto fail1; break; default: goto fail1; } error = bwn_fw_get(mac, type, filename, &fw->initvals); if (error) { bwn_release_firmware(mac); return (error); } /* bandswitch initvals */ switch (mac->mac_phy.type) { case BWN_PHYTYPE_A: if (rev >= 5 && rev <= 10) { - if (high & BWN_TGSHIGH_HAVE_2GHZ) + if (iost & BWN_IOST_HAVE_2GHZ) filename = "a0g1bsinitvals5"; else filename = "a0g0bsinitvals5"; } else if (rev >= 11) filename = NULL; else goto fail1; break; case BWN_PHYTYPE_G: if (rev >= 5 && rev <= 10) filename = "b0g0bsinitvals5"; else if (rev >= 11) filename = NULL; else goto fail1; break; case BWN_PHYTYPE_LP: if (rev == 13) filename = "lp0bsinitvals13"; else if (rev == 14) filename = "lp0bsinitvals14"; else if (rev >= 15) filename = "lp0bsinitvals15"; else goto fail1; break; case BWN_PHYTYPE_N: if (rev == 30) filename = "n16bsinitvals30"; else if (rev == 28 || rev == 25) filename = "n0bsinitvals25"; else if (rev == 24) filename = "n0bsinitvals24"; else if (rev == 23) filename = "n0bsinitvals16"; else if (rev >= 16 && rev <= 18) filename = "n0bsinitvals16"; else if (rev >= 11 && rev <= 12) filename = "n0bsinitvals11"; else goto fail1; break; default: device_printf(sc->sc_dev, "unknown phy (%d)\n", mac->mac_phy.type); goto fail1; } error = bwn_fw_get(mac, type, filename, &fw->initvals_band); if (error) { bwn_release_firmware(mac); return (error); } return (0); fail1: device_printf(sc->sc_dev, "no INITVALS for rev %d, phy.type %d\n", rev, mac->mac_phy.type); bwn_release_firmware(mac); return (EOPNOTSUPP); } static int bwn_fw_get(struct bwn_mac *mac, enum bwn_fwtype type, const char *name, struct bwn_fwfile *bfw) { const struct bwn_fwhdr *hdr; struct bwn_softc *sc = mac->mac_sc; const struct firmware *fw; char namebuf[64]; if (name == NULL) { bwn_do_release_fw(bfw); return (0); } if (bfw->filename != NULL) { if (bfw->type == type && (strcmp(bfw->filename, name) == 0)) return (0); bwn_do_release_fw(bfw); } snprintf(namebuf, sizeof(namebuf), "bwn%s_v4_%s%s", (type == BWN_FWTYPE_OPENSOURCE) ? "-open" : "", (mac->mac_phy.type == BWN_PHYTYPE_LP) ? "lp_" : "", name); /* XXX Sleeping on "fwload" with the non-sleepable locks held */ fw = firmware_get(namebuf); if (fw == NULL) { device_printf(sc->sc_dev, "the fw file(%s) not found\n", namebuf); return (ENOENT); } if (fw->datasize < sizeof(struct bwn_fwhdr)) goto fail; hdr = (const struct bwn_fwhdr *)(fw->data); switch (hdr->type) { case BWN_FWTYPE_UCODE: case BWN_FWTYPE_PCM: if (be32toh(hdr->size) != (fw->datasize - sizeof(struct bwn_fwhdr))) goto fail; /* FALLTHROUGH */ case BWN_FWTYPE_IV: if (hdr->ver != 1) goto fail; break; default: goto fail; } bfw->filename = name; bfw->fw = fw; bfw->type = type; return (0); fail: device_printf(sc->sc_dev, "the fw file(%s) format error\n", namebuf); if (fw != NULL) firmware_put(fw, FIRMWARE_UNLOAD); return (EPROTO); } static void bwn_release_firmware(struct bwn_mac *mac) { bwn_do_release_fw(&mac->mac_fw.ucode); bwn_do_release_fw(&mac->mac_fw.pcm); bwn_do_release_fw(&mac->mac_fw.initvals); bwn_do_release_fw(&mac->mac_fw.initvals_band); } static void bwn_do_release_fw(struct bwn_fwfile *bfw) { if (bfw->fw != NULL) firmware_put(bfw->fw, FIRMWARE_UNLOAD); bfw->fw = NULL; bfw->filename = NULL; } static int bwn_fw_loaducode(struct bwn_mac *mac) { #define GETFWOFFSET(fwp, offset) \ ((const uint32_t *)((const char *)fwp.fw->data + offset)) #define GETFWSIZE(fwp, offset) \ ((fwp.fw->datasize - offset) / sizeof(uint32_t)) struct bwn_softc *sc = mac->mac_sc; const uint32_t *data; unsigned int i; uint32_t ctl; uint16_t date, fwcaps, time; int error = 0; ctl = BWN_READ_4(mac, BWN_MACCTL); ctl |= BWN_MACCTL_MCODE_JMP0; KASSERT(!(ctl & BWN_MACCTL_MCODE_RUN), ("%s:%d: fail", __func__, __LINE__)); BWN_WRITE_4(mac, BWN_MACCTL, ctl); for (i = 0; i < 64; i++) bwn_shm_write_2(mac, BWN_SCRATCH, i, 0); for (i = 0; i < 4096; i += 2) bwn_shm_write_2(mac, BWN_SHARED, i, 0); data = GETFWOFFSET(mac->mac_fw.ucode, sizeof(struct bwn_fwhdr)); bwn_shm_ctlword(mac, BWN_UCODE | BWN_SHARED_AUTOINC, 0x0000); for (i = 0; i < GETFWSIZE(mac->mac_fw.ucode, sizeof(struct bwn_fwhdr)); i++) { BWN_WRITE_4(mac, BWN_SHM_DATA, be32toh(data[i])); DELAY(10); } if (mac->mac_fw.pcm.fw) { data = GETFWOFFSET(mac->mac_fw.pcm, sizeof(struct bwn_fwhdr)); bwn_shm_ctlword(mac, BWN_HW, 0x01ea); BWN_WRITE_4(mac, BWN_SHM_DATA, 0x00004000); bwn_shm_ctlword(mac, BWN_HW, 0x01eb); for (i = 0; i < GETFWSIZE(mac->mac_fw.pcm, sizeof(struct bwn_fwhdr)); i++) { BWN_WRITE_4(mac, BWN_SHM_DATA, be32toh(data[i])); DELAY(10); } } BWN_WRITE_4(mac, BWN_INTR_REASON, BWN_INTR_ALL); BWN_WRITE_4(mac, BWN_MACCTL, (BWN_READ_4(mac, BWN_MACCTL) & ~BWN_MACCTL_MCODE_JMP0) | BWN_MACCTL_MCODE_RUN); for (i = 0; i < 21; i++) { if (BWN_READ_4(mac, BWN_INTR_REASON) == BWN_INTR_MAC_SUSPENDED) break; if (i >= 20) { device_printf(sc->sc_dev, "ucode timeout\n"); error = ENXIO; goto error; } DELAY(50000); } BWN_READ_4(mac, BWN_INTR_REASON); mac->mac_fw.rev = bwn_shm_read_2(mac, BWN_SHARED, BWN_SHARED_UCODE_REV); if (mac->mac_fw.rev <= 0x128) { device_printf(sc->sc_dev, "the firmware is too old\n"); error = EOPNOTSUPP; goto error; } /* * Determine firmware header version; needed for TX/RX packet * handling. */ if (mac->mac_fw.rev >= 598) mac->mac_fw.fw_hdr_format = BWN_FW_HDR_598; else if (mac->mac_fw.rev >= 410) mac->mac_fw.fw_hdr_format = BWN_FW_HDR_410; else mac->mac_fw.fw_hdr_format = BWN_FW_HDR_351; /* * We don't support rev 598 or later; that requires * another round of changes to the TX/RX descriptor * and status layout. * * So, complain this is the case and exit out, rather * than attaching and then failing. */ #if 0 if (mac->mac_fw.fw_hdr_format == BWN_FW_HDR_598) { device_printf(sc->sc_dev, "firmware is too new (>=598); not supported\n"); error = EOPNOTSUPP; goto error; } #endif mac->mac_fw.patch = bwn_shm_read_2(mac, BWN_SHARED, BWN_SHARED_UCODE_PATCH); date = bwn_shm_read_2(mac, BWN_SHARED, BWN_SHARED_UCODE_DATE); mac->mac_fw.opensource = (date == 0xffff); if (bwn_wme != 0) mac->mac_flags |= BWN_MAC_FLAG_WME; mac->mac_flags |= BWN_MAC_FLAG_HWCRYPTO; time = bwn_shm_read_2(mac, BWN_SHARED, BWN_SHARED_UCODE_TIME); if (mac->mac_fw.opensource == 0) { device_printf(sc->sc_dev, "firmware version (rev %u patch %u date %#x time %#x)\n", mac->mac_fw.rev, mac->mac_fw.patch, date, time); if (mac->mac_fw.no_pcmfile) device_printf(sc->sc_dev, "no HW crypto acceleration due to pcm5\n"); } else { mac->mac_fw.patch = time; fwcaps = bwn_fwcaps_read(mac); if (!(fwcaps & BWN_FWCAPS_HWCRYPTO) || mac->mac_fw.no_pcmfile) { device_printf(sc->sc_dev, "disabling HW crypto acceleration\n"); mac->mac_flags &= ~BWN_MAC_FLAG_HWCRYPTO; } if (!(fwcaps & BWN_FWCAPS_WME)) { device_printf(sc->sc_dev, "disabling WME support\n"); mac->mac_flags &= ~BWN_MAC_FLAG_WME; } } if (BWN_ISOLDFMT(mac)) device_printf(sc->sc_dev, "using old firmware image\n"); return (0); error: BWN_WRITE_4(mac, BWN_MACCTL, (BWN_READ_4(mac, BWN_MACCTL) & ~BWN_MACCTL_MCODE_RUN) | BWN_MACCTL_MCODE_JMP0); return (error); #undef GETFWSIZE #undef GETFWOFFSET } /* OpenFirmware only */ static uint16_t bwn_fwcaps_read(struct bwn_mac *mac) { KASSERT(mac->mac_fw.opensource == 1, ("%s:%d: fail", __func__, __LINE__)); return (bwn_shm_read_2(mac, BWN_SHARED, BWN_SHARED_FWCAPS)); } static int bwn_fwinitvals_write(struct bwn_mac *mac, const struct bwn_fwinitvals *ivals, size_t count, size_t array_size) { #define GET_NEXTIV16(iv) \ ((const struct bwn_fwinitvals *)((const uint8_t *)(iv) + \ sizeof(uint16_t) + sizeof(uint16_t))) #define GET_NEXTIV32(iv) \ ((const struct bwn_fwinitvals *)((const uint8_t *)(iv) + \ sizeof(uint16_t) + sizeof(uint32_t))) struct bwn_softc *sc = mac->mac_sc; const struct bwn_fwinitvals *iv; uint16_t offset; size_t i; uint8_t bit32; KASSERT(sizeof(struct bwn_fwinitvals) == 6, ("%s:%d: fail", __func__, __LINE__)); iv = ivals; for (i = 0; i < count; i++) { if (array_size < sizeof(iv->offset_size)) goto fail; array_size -= sizeof(iv->offset_size); offset = be16toh(iv->offset_size); bit32 = (offset & BWN_FWINITVALS_32BIT) ? 1 : 0; offset &= BWN_FWINITVALS_OFFSET_MASK; if (offset >= 0x1000) goto fail; if (bit32) { if (array_size < sizeof(iv->data.d32)) goto fail; array_size -= sizeof(iv->data.d32); BWN_WRITE_4(mac, offset, be32toh(iv->data.d32)); iv = GET_NEXTIV32(iv); } else { if (array_size < sizeof(iv->data.d16)) goto fail; array_size -= sizeof(iv->data.d16); BWN_WRITE_2(mac, offset, be16toh(iv->data.d16)); iv = GET_NEXTIV16(iv); } } if (array_size != 0) goto fail; return (0); fail: device_printf(sc->sc_dev, "initvals: invalid format\n"); return (EPROTO); #undef GET_NEXTIV16 #undef GET_NEXTIV32 } int bwn_switch_channel(struct bwn_mac *mac, int chan) { struct bwn_phy *phy = &(mac->mac_phy); struct bwn_softc *sc = mac->mac_sc; struct ieee80211com *ic = &sc->sc_ic; uint16_t channelcookie, savedcookie; int error; if (chan == 0xffff) chan = phy->get_default_chan(mac); channelcookie = chan; if (IEEE80211_IS_CHAN_5GHZ(ic->ic_curchan)) channelcookie |= 0x100; savedcookie = bwn_shm_read_2(mac, BWN_SHARED, BWN_SHARED_CHAN); bwn_shm_write_2(mac, BWN_SHARED, BWN_SHARED_CHAN, channelcookie); error = phy->switch_channel(mac, chan); if (error) goto fail; mac->mac_phy.chan = chan; DELAY(8000); return (0); fail: device_printf(sc->sc_dev, "failed to switch channel\n"); bwn_shm_write_2(mac, BWN_SHARED, BWN_SHARED_CHAN, savedcookie); return (error); } static uint16_t bwn_ant2phy(int antenna) { switch (antenna) { case BWN_ANT0: return (BWN_TX_PHY_ANT0); case BWN_ANT1: return (BWN_TX_PHY_ANT1); case BWN_ANT2: return (BWN_TX_PHY_ANT2); case BWN_ANT3: return (BWN_TX_PHY_ANT3); case BWN_ANTAUTO: return (BWN_TX_PHY_ANT01AUTO); } KASSERT(0 == 1, ("%s:%d: fail", __func__, __LINE__)); return (0); } static void bwn_wme_load(struct bwn_mac *mac) { struct bwn_softc *sc = mac->mac_sc; int i; KASSERT(N(bwn_wme_shm_offsets) == N(sc->sc_wmeParams), ("%s:%d: fail", __func__, __LINE__)); bwn_mac_suspend(mac); for (i = 0; i < N(sc->sc_wmeParams); i++) bwn_wme_loadparams(mac, &(sc->sc_wmeParams[i]), bwn_wme_shm_offsets[i]); bwn_mac_enable(mac); } static void bwn_wme_loadparams(struct bwn_mac *mac, const struct wmeParams *p, uint16_t shm_offset) { #define SM(_v, _f) (((_v) << _f##_S) & _f) struct bwn_softc *sc = mac->mac_sc; uint16_t params[BWN_NR_WMEPARAMS]; int slot, tmp; unsigned int i; slot = BWN_READ_2(mac, BWN_RNG) & SM(p->wmep_logcwmin, WME_PARAM_LOGCWMIN); memset(¶ms, 0, sizeof(params)); DPRINTF(sc, BWN_DEBUG_WME, "wmep_txopLimit %d wmep_logcwmin %d " "wmep_logcwmax %d wmep_aifsn %d\n", p->wmep_txopLimit, p->wmep_logcwmin, p->wmep_logcwmax, p->wmep_aifsn); params[BWN_WMEPARAM_TXOP] = p->wmep_txopLimit * 32; params[BWN_WMEPARAM_CWMIN] = SM(p->wmep_logcwmin, WME_PARAM_LOGCWMIN); params[BWN_WMEPARAM_CWMAX] = SM(p->wmep_logcwmax, WME_PARAM_LOGCWMAX); params[BWN_WMEPARAM_CWCUR] = SM(p->wmep_logcwmin, WME_PARAM_LOGCWMIN); params[BWN_WMEPARAM_AIFS] = p->wmep_aifsn; params[BWN_WMEPARAM_BSLOTS] = slot; params[BWN_WMEPARAM_REGGAP] = slot + p->wmep_aifsn; for (i = 0; i < N(params); i++) { if (i == BWN_WMEPARAM_STATUS) { tmp = bwn_shm_read_2(mac, BWN_SHARED, shm_offset + (i * 2)); tmp |= 0x100; bwn_shm_write_2(mac, BWN_SHARED, shm_offset + (i * 2), tmp); } else { bwn_shm_write_2(mac, BWN_SHARED, shm_offset + (i * 2), params[i]); } } } static void bwn_mac_write_bssid(struct bwn_mac *mac) { struct bwn_softc *sc = mac->mac_sc; uint32_t tmp; int i; uint8_t mac_bssid[IEEE80211_ADDR_LEN * 2]; bwn_mac_setfilter(mac, BWN_MACFILTER_BSSID, sc->sc_bssid); memcpy(mac_bssid, sc->sc_ic.ic_macaddr, IEEE80211_ADDR_LEN); memcpy(mac_bssid + IEEE80211_ADDR_LEN, sc->sc_bssid, IEEE80211_ADDR_LEN); for (i = 0; i < N(mac_bssid); i += sizeof(uint32_t)) { tmp = (uint32_t) (mac_bssid[i + 0]); tmp |= (uint32_t) (mac_bssid[i + 1]) << 8; tmp |= (uint32_t) (mac_bssid[i + 2]) << 16; tmp |= (uint32_t) (mac_bssid[i + 3]) << 24; bwn_ram_write(mac, 0x20 + i, tmp); } } static void bwn_mac_setfilter(struct bwn_mac *mac, uint16_t offset, const uint8_t *macaddr) { static const uint8_t zero[IEEE80211_ADDR_LEN] = { 0 }; uint16_t data; if (!mac) macaddr = zero; offset |= 0x0020; BWN_WRITE_2(mac, BWN_MACFILTER_CONTROL, offset); data = macaddr[0]; data |= macaddr[1] << 8; BWN_WRITE_2(mac, BWN_MACFILTER_DATA, data); data = macaddr[2]; data |= macaddr[3] << 8; BWN_WRITE_2(mac, BWN_MACFILTER_DATA, data); data = macaddr[4]; data |= macaddr[5] << 8; BWN_WRITE_2(mac, BWN_MACFILTER_DATA, data); } static void bwn_key_dowrite(struct bwn_mac *mac, uint8_t index, uint8_t algorithm, const uint8_t *key, size_t key_len, const uint8_t *mac_addr) { uint8_t buf[BWN_SEC_KEYSIZE] = { 0, }; uint8_t per_sta_keys_start = 8; if (BWN_SEC_NEWAPI(mac)) per_sta_keys_start = 4; KASSERT(index < mac->mac_max_nr_keys, ("%s:%d: fail", __func__, __LINE__)); KASSERT(key_len <= BWN_SEC_KEYSIZE, ("%s:%d: fail", __func__, __LINE__)); if (index >= per_sta_keys_start) bwn_key_macwrite(mac, index, NULL); if (key) memcpy(buf, key, key_len); bwn_key_write(mac, index, algorithm, buf); if (index >= per_sta_keys_start) bwn_key_macwrite(mac, index, mac_addr); mac->mac_key[index].algorithm = algorithm; } static void bwn_key_macwrite(struct bwn_mac *mac, uint8_t index, const uint8_t *addr) { struct bwn_softc *sc = mac->mac_sc; uint32_t addrtmp[2] = { 0, 0 }; uint8_t start = 8; if (BWN_SEC_NEWAPI(mac)) start = 4; KASSERT(index >= start, ("%s:%d: fail", __func__, __LINE__)); index -= start; if (addr) { addrtmp[0] = addr[0]; addrtmp[0] |= ((uint32_t) (addr[1]) << 8); addrtmp[0] |= ((uint32_t) (addr[2]) << 16); addrtmp[0] |= ((uint32_t) (addr[3]) << 24); addrtmp[1] = addr[4]; addrtmp[1] |= ((uint32_t) (addr[5]) << 8); } - if (siba_get_revid(sc->sc_dev) >= 5) { + if (bhnd_get_hwrev(sc->sc_dev) >= 5) { bwn_shm_write_4(mac, BWN_RCMTA, (index * 2) + 0, addrtmp[0]); bwn_shm_write_2(mac, BWN_RCMTA, (index * 2) + 1, addrtmp[1]); } else { if (index >= 8) { bwn_shm_write_4(mac, BWN_SHARED, BWN_SHARED_PSM + (index * 6) + 0, addrtmp[0]); bwn_shm_write_2(mac, BWN_SHARED, BWN_SHARED_PSM + (index * 6) + 4, addrtmp[1]); } } } static void bwn_key_write(struct bwn_mac *mac, uint8_t index, uint8_t algorithm, const uint8_t *key) { unsigned int i; uint32_t offset; uint16_t kidx, value; kidx = BWN_SEC_KEY2FW(mac, index); bwn_shm_write_2(mac, BWN_SHARED, BWN_SHARED_KEYIDX_BLOCK + (kidx * 2), (kidx << 4) | algorithm); offset = mac->mac_ktp + (index * BWN_SEC_KEYSIZE); for (i = 0; i < BWN_SEC_KEYSIZE; i += 2) { value = key[i]; value |= (uint16_t)(key[i + 1]) << 8; bwn_shm_write_2(mac, BWN_SHARED, offset + i, value); } } static void bwn_phy_exit(struct bwn_mac *mac) { mac->mac_phy.rf_onoff(mac, 0); if (mac->mac_phy.exit != NULL) mac->mac_phy.exit(mac); } static void bwn_dma_free(struct bwn_mac *mac) { struct bwn_dma *dma; if ((mac->mac_flags & BWN_MAC_FLAG_DMA) == 0) return; dma = &mac->mac_method.dma; bwn_dma_ringfree(&dma->rx); bwn_dma_ringfree(&dma->wme[WME_AC_BK]); bwn_dma_ringfree(&dma->wme[WME_AC_BE]); bwn_dma_ringfree(&dma->wme[WME_AC_VI]); bwn_dma_ringfree(&dma->wme[WME_AC_VO]); bwn_dma_ringfree(&dma->mcast); } static void bwn_core_stop(struct bwn_mac *mac) { struct bwn_softc *sc = mac->mac_sc; BWN_ASSERT_LOCKED(sc); if (mac->mac_status < BWN_MAC_STATUS_STARTED) return; callout_stop(&sc->sc_rfswitch_ch); callout_stop(&sc->sc_task_ch); callout_stop(&sc->sc_watchdog_ch); sc->sc_watchdog_timer = 0; BWN_WRITE_4(mac, BWN_INTR_MASK, 0); BWN_READ_4(mac, BWN_INTR_MASK); bwn_mac_suspend(mac); mac->mac_status = BWN_MAC_STATUS_INITED; } static int bwn_switch_band(struct bwn_softc *sc, struct ieee80211_channel *chan) { struct bwn_mac *up_dev = NULL; struct bwn_mac *down_dev; struct bwn_mac *mac; int err, status; uint8_t gmode; BWN_ASSERT_LOCKED(sc); TAILQ_FOREACH(mac, &sc->sc_maclist, mac_list) { if (IEEE80211_IS_CHAN_2GHZ(chan) && mac->mac_phy.supports_2ghz) { up_dev = mac; gmode = 1; } else if (IEEE80211_IS_CHAN_5GHZ(chan) && mac->mac_phy.supports_5ghz) { up_dev = mac; gmode = 0; } else { KASSERT(0 == 1, ("%s:%d: fail", __func__, __LINE__)); return (EINVAL); } if (up_dev != NULL) break; } if (up_dev == NULL) { device_printf(sc->sc_dev, "Could not find a device\n"); return (ENODEV); } if (up_dev == sc->sc_curmac && sc->sc_curmac->mac_phy.gmode == gmode) return (0); DPRINTF(sc, BWN_DEBUG_RF | BWN_DEBUG_PHY | BWN_DEBUG_RESET, "switching to %s-GHz band\n", IEEE80211_IS_CHAN_2GHZ(chan) ? "2" : "5"); down_dev = sc->sc_curmac; status = down_dev->mac_status; if (status >= BWN_MAC_STATUS_STARTED) bwn_core_stop(down_dev); if (status >= BWN_MAC_STATUS_INITED) bwn_core_exit(down_dev); - if (down_dev != up_dev) - bwn_phy_reset(down_dev); + if (down_dev != up_dev) { + err = bwn_phy_reset(down_dev); + if (err) + goto fail; + } up_dev->mac_phy.gmode = gmode; if (status >= BWN_MAC_STATUS_INITED) { err = bwn_core_init(up_dev); if (err) { device_printf(sc->sc_dev, "fatal: failed to initialize for %s-GHz\n", IEEE80211_IS_CHAN_2GHZ(chan) ? "2" : "5"); goto fail; } } if (status >= BWN_MAC_STATUS_STARTED) bwn_core_start(up_dev); KASSERT(up_dev->mac_status == status, ("%s: fail", __func__)); sc->sc_curmac = up_dev; return (0); fail: sc->sc_curmac = NULL; return (err); } static void bwn_rf_turnon(struct bwn_mac *mac) { DPRINTF(mac->mac_sc, BWN_DEBUG_RESET, "%s: called\n", __func__); bwn_mac_suspend(mac); mac->mac_phy.rf_onoff(mac, 1); mac->mac_phy.rf_on = 1; bwn_mac_enable(mac); } static void bwn_rf_turnoff(struct bwn_mac *mac) { DPRINTF(mac->mac_sc, BWN_DEBUG_RESET, "%s: called\n", __func__); bwn_mac_suspend(mac); mac->mac_phy.rf_onoff(mac, 0); mac->mac_phy.rf_on = 0; bwn_mac_enable(mac); } /* * PHY reset. */ -static void +static int bwn_phy_reset(struct bwn_mac *mac) { - struct bwn_softc *sc = mac->mac_sc; + struct bwn_softc *sc; + uint16_t iost, mask; + int error; - siba_write_4(sc->sc_dev, SIBA_TGSLOW, - ((siba_read_4(sc->sc_dev, SIBA_TGSLOW) & ~BWN_TGSLOW_SUPPORT_G) | - BWN_TGSLOW_PHYRESET) | SIBA_TGSLOW_FGC); + sc = mac->mac_sc; + + iost = BWN_IOCTL_PHYRESET | BHND_IOCTL_CLK_FORCE; + mask = iost | BWN_IOCTL_SUPPORT_G; + + if ((error = bhnd_write_ioctl(sc->sc_dev, iost, mask))) + return (error); + DELAY(1000); - siba_write_4(sc->sc_dev, SIBA_TGSLOW, - (siba_read_4(sc->sc_dev, SIBA_TGSLOW) & ~SIBA_TGSLOW_FGC)); + + iost &= ~BHND_IOCTL_CLK_FORCE; + + if ((error = bhnd_write_ioctl(sc->sc_dev, iost, mask))) + return (error); + DELAY(1000); + + return (0); } static int bwn_newstate(struct ieee80211vap *vap, enum ieee80211_state nstate, int arg) { struct bwn_vap *bvp = BWN_VAP(vap); struct ieee80211com *ic= vap->iv_ic; enum ieee80211_state ostate = vap->iv_state; struct bwn_softc *sc = ic->ic_softc; struct bwn_mac *mac = sc->sc_curmac; int error; DPRINTF(sc, BWN_DEBUG_STATE, "%s: %s -> %s\n", __func__, ieee80211_state_name[vap->iv_state], ieee80211_state_name[nstate]); error = bvp->bv_newstate(vap, nstate, arg); if (error != 0) return (error); BWN_LOCK(sc); bwn_led_newstate(mac, nstate); /* * Clear the BSSID when we stop a STA */ if (vap->iv_opmode == IEEE80211_M_STA) { if (ostate == IEEE80211_S_RUN && nstate != IEEE80211_S_RUN) { /* * Clear out the BSSID. If we reassociate to * the same AP, this will reinialize things * correctly... */ if (ic->ic_opmode == IEEE80211_M_STA && (sc->sc_flags & BWN_FLAG_INVALID) == 0) { memset(sc->sc_bssid, 0, IEEE80211_ADDR_LEN); bwn_set_macaddr(mac); } } } if (vap->iv_opmode == IEEE80211_M_MONITOR || vap->iv_opmode == IEEE80211_M_AHDEMO) { /* XXX nothing to do? */ } else if (nstate == IEEE80211_S_RUN) { memcpy(sc->sc_bssid, vap->iv_bss->ni_bssid, IEEE80211_ADDR_LEN); bwn_set_opmode(mac); bwn_set_pretbtt(mac); bwn_spu_setdelay(mac, 0); bwn_set_macaddr(mac); } BWN_UNLOCK(sc); return (error); } static void bwn_set_pretbtt(struct bwn_mac *mac) { struct bwn_softc *sc = mac->mac_sc; struct ieee80211com *ic = &sc->sc_ic; uint16_t pretbtt; if (ic->ic_opmode == IEEE80211_M_IBSS) pretbtt = 2; else pretbtt = (mac->mac_phy.type == BWN_PHYTYPE_A) ? 120 : 250; bwn_shm_write_2(mac, BWN_SHARED, BWN_SHARED_PRETBTT, pretbtt); BWN_WRITE_2(mac, BWN_TSF_CFP_PRETBTT, pretbtt); } static int bwn_intr(void *arg) { struct bwn_mac *mac = arg; struct bwn_softc *sc = mac->mac_sc; uint32_t reason; if (mac->mac_status < BWN_MAC_STATUS_STARTED || (sc->sc_flags & BWN_FLAG_INVALID)) return (FILTER_STRAY); DPRINTF(sc, BWN_DEBUG_INTR, "%s: called\n", __func__); reason = BWN_READ_4(mac, BWN_INTR_REASON); if (reason == 0xffffffff) /* shared IRQ */ return (FILTER_STRAY); reason &= mac->mac_intr_mask; if (reason == 0) return (FILTER_HANDLED); DPRINTF(sc, BWN_DEBUG_INTR, "%s: reason=0x%08x\n", __func__, reason); mac->mac_reason[0] = BWN_READ_4(mac, BWN_DMA0_REASON) & 0x0001dc00; mac->mac_reason[1] = BWN_READ_4(mac, BWN_DMA1_REASON) & 0x0000dc00; mac->mac_reason[2] = BWN_READ_4(mac, BWN_DMA2_REASON) & 0x0000dc00; mac->mac_reason[3] = BWN_READ_4(mac, BWN_DMA3_REASON) & 0x0001dc00; mac->mac_reason[4] = BWN_READ_4(mac, BWN_DMA4_REASON) & 0x0000dc00; BWN_WRITE_4(mac, BWN_INTR_REASON, reason); BWN_WRITE_4(mac, BWN_DMA0_REASON, mac->mac_reason[0]); BWN_WRITE_4(mac, BWN_DMA1_REASON, mac->mac_reason[1]); BWN_WRITE_4(mac, BWN_DMA2_REASON, mac->mac_reason[2]); BWN_WRITE_4(mac, BWN_DMA3_REASON, mac->mac_reason[3]); BWN_WRITE_4(mac, BWN_DMA4_REASON, mac->mac_reason[4]); /* Disable interrupts. */ BWN_WRITE_4(mac, BWN_INTR_MASK, 0); mac->mac_reason_intr = reason; - BWN_BARRIER(mac, BUS_SPACE_BARRIER_READ); - BWN_BARRIER(mac, BUS_SPACE_BARRIER_WRITE); + BWN_BARRIER(mac, 0, 0, BUS_SPACE_BARRIER_READ|BUS_SPACE_BARRIER_WRITE); taskqueue_enqueue(sc->sc_tq, &mac->mac_intrtask); return (FILTER_HANDLED); } static void bwn_intrtask(void *arg, int npending) { struct bwn_mac *mac = arg; struct bwn_softc *sc = mac->mac_sc; uint32_t merged = 0; int i, tx = 0, rx = 0; BWN_LOCK(sc); if (mac->mac_status < BWN_MAC_STATUS_STARTED || (sc->sc_flags & BWN_FLAG_INVALID)) { BWN_UNLOCK(sc); return; } for (i = 0; i < N(mac->mac_reason); i++) merged |= mac->mac_reason[i]; if (mac->mac_reason_intr & BWN_INTR_MAC_TXERR) device_printf(sc->sc_dev, "MAC trans error\n"); if (mac->mac_reason_intr & BWN_INTR_PHY_TXERR) { DPRINTF(sc, BWN_DEBUG_INTR, "%s: PHY trans error\n", __func__); mac->mac_phy.txerrors--; if (mac->mac_phy.txerrors == 0) { mac->mac_phy.txerrors = BWN_TXERROR_MAX; bwn_restart(mac, "PHY TX errors"); } } if (merged & (BWN_DMAINTR_FATALMASK | BWN_DMAINTR_NONFATALMASK)) { if (merged & BWN_DMAINTR_FATALMASK) { device_printf(sc->sc_dev, "Fatal DMA error: %#x %#x %#x %#x %#x %#x\n", mac->mac_reason[0], mac->mac_reason[1], mac->mac_reason[2], mac->mac_reason[3], mac->mac_reason[4], mac->mac_reason[5]); bwn_restart(mac, "DMA error"); BWN_UNLOCK(sc); return; } if (merged & BWN_DMAINTR_NONFATALMASK) { device_printf(sc->sc_dev, "DMA error: %#x %#x %#x %#x %#x %#x\n", mac->mac_reason[0], mac->mac_reason[1], mac->mac_reason[2], mac->mac_reason[3], mac->mac_reason[4], mac->mac_reason[5]); } } if (mac->mac_reason_intr & BWN_INTR_UCODE_DEBUG) bwn_intr_ucode_debug(mac); if (mac->mac_reason_intr & BWN_INTR_TBTT_INDI) bwn_intr_tbtt_indication(mac); if (mac->mac_reason_intr & BWN_INTR_ATIM_END) bwn_intr_atim_end(mac); if (mac->mac_reason_intr & BWN_INTR_BEACON) bwn_intr_beacon(mac); if (mac->mac_reason_intr & BWN_INTR_PMQ) bwn_intr_pmq(mac); if (mac->mac_reason_intr & BWN_INTR_NOISESAMPLE_OK) bwn_intr_noise(mac); if (mac->mac_flags & BWN_MAC_FLAG_DMA) { if (mac->mac_reason[0] & BWN_DMAINTR_RX_DONE) { bwn_dma_rx(mac->mac_method.dma.rx); rx = 1; } } else rx = bwn_pio_rx(&mac->mac_method.pio.rx); KASSERT(!(mac->mac_reason[1] & BWN_DMAINTR_RX_DONE), ("%s", __func__)); KASSERT(!(mac->mac_reason[2] & BWN_DMAINTR_RX_DONE), ("%s", __func__)); KASSERT(!(mac->mac_reason[3] & BWN_DMAINTR_RX_DONE), ("%s", __func__)); KASSERT(!(mac->mac_reason[4] & BWN_DMAINTR_RX_DONE), ("%s", __func__)); KASSERT(!(mac->mac_reason[5] & BWN_DMAINTR_RX_DONE), ("%s", __func__)); if (mac->mac_reason_intr & BWN_INTR_TX_OK) { bwn_intr_txeof(mac); tx = 1; } BWN_WRITE_4(mac, BWN_INTR_MASK, mac->mac_intr_mask); if (sc->sc_blink_led != NULL && sc->sc_led_blink) { int evt = BWN_LED_EVENT_NONE; if (tx && rx) { if (sc->sc_rx_rate > sc->sc_tx_rate) evt = BWN_LED_EVENT_RX; else evt = BWN_LED_EVENT_TX; } else if (tx) { evt = BWN_LED_EVENT_TX; } else if (rx) { evt = BWN_LED_EVENT_RX; } else if (rx == 0) { evt = BWN_LED_EVENT_POLL; } if (evt != BWN_LED_EVENT_NONE) bwn_led_event(mac, evt); } if (mbufq_first(&sc->sc_snd) != NULL) bwn_start(sc); - BWN_BARRIER(mac, BUS_SPACE_BARRIER_READ); - BWN_BARRIER(mac, BUS_SPACE_BARRIER_WRITE); + BWN_BARRIER(mac, 0, 0, BUS_SPACE_BARRIER_READ|BUS_SPACE_BARRIER_WRITE); BWN_UNLOCK(sc); } static void bwn_restart(struct bwn_mac *mac, const char *msg) { struct bwn_softc *sc = mac->mac_sc; struct ieee80211com *ic = &sc->sc_ic; if (mac->mac_status < BWN_MAC_STATUS_INITED) return; device_printf(sc->sc_dev, "HW reset: %s\n", msg); ieee80211_runtask(ic, &mac->mac_hwreset); } static void bwn_intr_ucode_debug(struct bwn_mac *mac) { struct bwn_softc *sc = mac->mac_sc; uint16_t reason; if (mac->mac_fw.opensource == 0) return; reason = bwn_shm_read_2(mac, BWN_SCRATCH, BWN_DEBUGINTR_REASON_REG); switch (reason) { case BWN_DEBUGINTR_PANIC: bwn_handle_fwpanic(mac); break; case BWN_DEBUGINTR_DUMP_SHM: device_printf(sc->sc_dev, "BWN_DEBUGINTR_DUMP_SHM\n"); break; case BWN_DEBUGINTR_DUMP_REGS: device_printf(sc->sc_dev, "BWN_DEBUGINTR_DUMP_REGS\n"); break; case BWN_DEBUGINTR_MARKER: device_printf(sc->sc_dev, "BWN_DEBUGINTR_MARKER\n"); break; default: device_printf(sc->sc_dev, "ucode debug unknown reason: %#x\n", reason); } bwn_shm_write_2(mac, BWN_SCRATCH, BWN_DEBUGINTR_REASON_REG, BWN_DEBUGINTR_ACK); } static void bwn_intr_tbtt_indication(struct bwn_mac *mac) { struct bwn_softc *sc = mac->mac_sc; struct ieee80211com *ic = &sc->sc_ic; if (ic->ic_opmode != IEEE80211_M_HOSTAP) bwn_psctl(mac, 0); if (ic->ic_opmode == IEEE80211_M_IBSS) mac->mac_flags |= BWN_MAC_FLAG_DFQVALID; } static void bwn_intr_atim_end(struct bwn_mac *mac) { if (mac->mac_flags & BWN_MAC_FLAG_DFQVALID) { BWN_WRITE_4(mac, BWN_MACCMD, BWN_READ_4(mac, BWN_MACCMD) | BWN_MACCMD_DFQ_VALID); mac->mac_flags &= ~BWN_MAC_FLAG_DFQVALID; } } static void bwn_intr_beacon(struct bwn_mac *mac) { struct bwn_softc *sc = mac->mac_sc; struct ieee80211com *ic = &sc->sc_ic; uint32_t cmd, beacon0, beacon1; if (ic->ic_opmode == IEEE80211_M_HOSTAP || ic->ic_opmode == IEEE80211_M_MBSS) return; mac->mac_intr_mask &= ~BWN_INTR_BEACON; cmd = BWN_READ_4(mac, BWN_MACCMD); beacon0 = (cmd & BWN_MACCMD_BEACON0_VALID); beacon1 = (cmd & BWN_MACCMD_BEACON1_VALID); if (beacon0 && beacon1) { BWN_WRITE_4(mac, BWN_INTR_REASON, BWN_INTR_BEACON); mac->mac_intr_mask |= BWN_INTR_BEACON; return; } if (sc->sc_flags & BWN_FLAG_NEED_BEACON_TP) { sc->sc_flags &= ~BWN_FLAG_NEED_BEACON_TP; bwn_load_beacon0(mac); bwn_load_beacon1(mac); cmd = BWN_READ_4(mac, BWN_MACCMD); cmd |= BWN_MACCMD_BEACON0_VALID; BWN_WRITE_4(mac, BWN_MACCMD, cmd); } else { if (!beacon0) { bwn_load_beacon0(mac); cmd = BWN_READ_4(mac, BWN_MACCMD); cmd |= BWN_MACCMD_BEACON0_VALID; BWN_WRITE_4(mac, BWN_MACCMD, cmd); } else if (!beacon1) { bwn_load_beacon1(mac); cmd = BWN_READ_4(mac, BWN_MACCMD); cmd |= BWN_MACCMD_BEACON1_VALID; BWN_WRITE_4(mac, BWN_MACCMD, cmd); } } } static void bwn_intr_pmq(struct bwn_mac *mac) { uint32_t tmp; while (1) { tmp = BWN_READ_4(mac, BWN_PS_STATUS); if (!(tmp & 0x00000008)) break; } BWN_WRITE_2(mac, BWN_PS_STATUS, 0x0002); } static void bwn_intr_noise(struct bwn_mac *mac) { struct bwn_phy_g *pg = &mac->mac_phy.phy_g; uint16_t tmp; uint8_t noise[4]; uint8_t i, j; int32_t average; if (mac->mac_phy.type != BWN_PHYTYPE_G) return; KASSERT(mac->mac_noise.noi_running, ("%s: fail", __func__)); *((uint32_t *)noise) = htole32(bwn_jssi_read(mac)); if (noise[0] == 0x7f || noise[1] == 0x7f || noise[2] == 0x7f || noise[3] == 0x7f) goto new; KASSERT(mac->mac_noise.noi_nsamples < 8, ("%s:%d: fail", __func__, __LINE__)); i = mac->mac_noise.noi_nsamples; noise[0] = MIN(MAX(noise[0], 0), N(pg->pg_nrssi_lt) - 1); noise[1] = MIN(MAX(noise[1], 0), N(pg->pg_nrssi_lt) - 1); noise[2] = MIN(MAX(noise[2], 0), N(pg->pg_nrssi_lt) - 1); noise[3] = MIN(MAX(noise[3], 0), N(pg->pg_nrssi_lt) - 1); mac->mac_noise.noi_samples[i][0] = pg->pg_nrssi_lt[noise[0]]; mac->mac_noise.noi_samples[i][1] = pg->pg_nrssi_lt[noise[1]]; mac->mac_noise.noi_samples[i][2] = pg->pg_nrssi_lt[noise[2]]; mac->mac_noise.noi_samples[i][3] = pg->pg_nrssi_lt[noise[3]]; mac->mac_noise.noi_nsamples++; if (mac->mac_noise.noi_nsamples == 8) { average = 0; for (i = 0; i < 8; i++) { for (j = 0; j < 4; j++) average += mac->mac_noise.noi_samples[i][j]; } average = (((average / 32) * 125) + 64) / 128; tmp = (bwn_shm_read_2(mac, BWN_SHARED, 0x40c) / 128) & 0x1f; if (tmp >= 8) average += 2; else average -= 25; average -= (tmp == 8) ? 72 : 48; mac->mac_stats.link_noise = average; mac->mac_noise.noi_running = 0; return; } new: bwn_noise_gensample(mac); } static int bwn_pio_rx(struct bwn_pio_rxqueue *prq) { struct bwn_mac *mac = prq->prq_mac; struct bwn_softc *sc = mac->mac_sc; unsigned int i; BWN_ASSERT_LOCKED(sc); if (mac->mac_status < BWN_MAC_STATUS_STARTED) return (0); for (i = 0; i < 5000; i++) { if (bwn_pio_rxeof(prq) == 0) break; } if (i >= 5000) device_printf(sc->sc_dev, "too many RX frames in PIO mode\n"); return ((i > 0) ? 1 : 0); } static void bwn_dma_rx(struct bwn_dma_ring *dr) { int slot, curslot; KASSERT(!dr->dr_tx, ("%s:%d: fail", __func__, __LINE__)); curslot = dr->get_curslot(dr); KASSERT(curslot >= 0 && curslot < dr->dr_numslots, ("%s:%d: fail", __func__, __LINE__)); slot = dr->dr_curslot; for (; slot != curslot; slot = bwn_dma_nextslot(dr, slot)) bwn_dma_rxeof(dr, &slot); bus_dmamap_sync(dr->dr_ring_dtag, dr->dr_ring_dmap, BUS_DMASYNC_PREWRITE); dr->set_curslot(dr, slot); dr->dr_curslot = slot; } static void bwn_intr_txeof(struct bwn_mac *mac) { struct bwn_txstatus stat; uint32_t stat0, stat1; uint16_t tmp; BWN_ASSERT_LOCKED(mac->mac_sc); while (1) { stat0 = BWN_READ_4(mac, BWN_XMITSTAT_0); if (!(stat0 & 0x00000001)) break; stat1 = BWN_READ_4(mac, BWN_XMITSTAT_1); DPRINTF(mac->mac_sc, BWN_DEBUG_XMIT, "%s: stat0=0x%08x, stat1=0x%08x\n", __func__, stat0, stat1); stat.cookie = (stat0 >> 16); stat.seq = (stat1 & 0x0000ffff); stat.phy_stat = ((stat1 & 0x00ff0000) >> 16); tmp = (stat0 & 0x0000ffff); stat.framecnt = ((tmp & 0xf000) >> 12); stat.rtscnt = ((tmp & 0x0f00) >> 8); stat.sreason = ((tmp & 0x001c) >> 2); stat.pm = (tmp & 0x0080) ? 1 : 0; stat.im = (tmp & 0x0040) ? 1 : 0; stat.ampdu = (tmp & 0x0020) ? 1 : 0; stat.ack = (tmp & 0x0002) ? 1 : 0; DPRINTF(mac->mac_sc, BWN_DEBUG_XMIT, "%s: cookie=%d, seq=%d, phystat=0x%02x, framecnt=%d, " "rtscnt=%d, sreason=%d, pm=%d, im=%d, ampdu=%d, ack=%d\n", __func__, stat.cookie, stat.seq, stat.phy_stat, stat.framecnt, stat.rtscnt, stat.sreason, stat.pm, stat.im, stat.ampdu, stat.ack); bwn_handle_txeof(mac, &stat); } } static void bwn_hwreset(void *arg, int npending) { struct bwn_mac *mac = arg; struct bwn_softc *sc = mac->mac_sc; int error = 0; int prev_status; BWN_LOCK(sc); prev_status = mac->mac_status; if (prev_status >= BWN_MAC_STATUS_STARTED) bwn_core_stop(mac); if (prev_status >= BWN_MAC_STATUS_INITED) bwn_core_exit(mac); if (prev_status >= BWN_MAC_STATUS_INITED) { error = bwn_core_init(mac); if (error) goto out; } if (prev_status >= BWN_MAC_STATUS_STARTED) bwn_core_start(mac); out: if (error) { device_printf(sc->sc_dev, "%s: failed (%d)\n", __func__, error); sc->sc_curmac = NULL; } BWN_UNLOCK(sc); } static void bwn_handle_fwpanic(struct bwn_mac *mac) { struct bwn_softc *sc = mac->mac_sc; uint16_t reason; reason = bwn_shm_read_2(mac, BWN_SCRATCH, BWN_FWPANIC_REASON_REG); device_printf(sc->sc_dev,"fw panic (%u)\n", reason); if (reason == BWN_FWPANIC_RESTART) bwn_restart(mac, "ucode panic"); } static void bwn_load_beacon0(struct bwn_mac *mac) { KASSERT(0 == 1, ("%s:%d: fail", __func__, __LINE__)); } static void bwn_load_beacon1(struct bwn_mac *mac) { KASSERT(0 == 1, ("%s:%d: fail", __func__, __LINE__)); } static uint32_t bwn_jssi_read(struct bwn_mac *mac) { uint32_t val = 0; val = bwn_shm_read_2(mac, BWN_SHARED, 0x08a); val <<= 16; val |= bwn_shm_read_2(mac, BWN_SHARED, 0x088); return (val); } static void bwn_noise_gensample(struct bwn_mac *mac) { uint32_t jssi = 0x7f7f7f7f; bwn_shm_write_2(mac, BWN_SHARED, 0x088, (jssi & 0x0000ffff)); bwn_shm_write_2(mac, BWN_SHARED, 0x08a, (jssi & 0xffff0000) >> 16); BWN_WRITE_4(mac, BWN_MACCMD, BWN_READ_4(mac, BWN_MACCMD) | BWN_MACCMD_BGNOISE); } static int bwn_dma_freeslot(struct bwn_dma_ring *dr) { BWN_ASSERT_LOCKED(dr->dr_mac->mac_sc); return (dr->dr_numslots - dr->dr_usedslot); } static int bwn_dma_nextslot(struct bwn_dma_ring *dr, int slot) { BWN_ASSERT_LOCKED(dr->dr_mac->mac_sc); KASSERT(slot >= -1 && slot <= dr->dr_numslots - 1, ("%s:%d: fail", __func__, __LINE__)); if (slot == dr->dr_numslots - 1) return (0); return (slot + 1); } static void bwn_dma_rxeof(struct bwn_dma_ring *dr, int *slot) { struct bwn_mac *mac = dr->dr_mac; struct bwn_softc *sc = mac->mac_sc; struct bwn_dma *dma = &mac->mac_method.dma; struct bwn_dmadesc_generic *desc; struct bwn_dmadesc_meta *meta; struct bwn_rxhdr4 *rxhdr; struct mbuf *m; uint32_t macstat; int32_t tmp; int cnt = 0; uint16_t len; dr->getdesc(dr, *slot, &desc, &meta); bus_dmamap_sync(dma->rxbuf_dtag, meta->mt_dmap, BUS_DMASYNC_POSTREAD); m = meta->mt_m; if (bwn_dma_newbuf(dr, desc, meta, 0)) { counter_u64_add(sc->sc_ic.ic_ierrors, 1); return; } rxhdr = mtod(m, struct bwn_rxhdr4 *); len = le16toh(rxhdr->frame_len); if (len <= 0) { counter_u64_add(sc->sc_ic.ic_ierrors, 1); return; } if (bwn_dma_check_redzone(dr, m)) { device_printf(sc->sc_dev, "redzone error.\n"); bwn_dma_set_redzone(dr, m); bus_dmamap_sync(dma->rxbuf_dtag, meta->mt_dmap, BUS_DMASYNC_PREWRITE); return; } if (len > dr->dr_rx_bufsize) { tmp = len; while (1) { dr->getdesc(dr, *slot, &desc, &meta); bwn_dma_set_redzone(dr, meta->mt_m); bus_dmamap_sync(dma->rxbuf_dtag, meta->mt_dmap, BUS_DMASYNC_PREWRITE); *slot = bwn_dma_nextslot(dr, *slot); cnt++; tmp -= dr->dr_rx_bufsize; if (tmp <= 0) break; } device_printf(sc->sc_dev, "too small buffer " "(len %u buffer %u dropped %d)\n", len, dr->dr_rx_bufsize, cnt); return; } switch (mac->mac_fw.fw_hdr_format) { case BWN_FW_HDR_351: case BWN_FW_HDR_410: macstat = le32toh(rxhdr->ps4.r351.mac_status); break; case BWN_FW_HDR_598: macstat = le32toh(rxhdr->ps4.r598.mac_status); break; } if (macstat & BWN_RX_MAC_FCSERR) { if (!(mac->mac_sc->sc_filters & BWN_MACCTL_PASS_BADFCS)) { device_printf(sc->sc_dev, "RX drop\n"); return; } } m->m_len = m->m_pkthdr.len = len + dr->dr_frameoffset; m_adj(m, dr->dr_frameoffset); bwn_rxeof(dr->dr_mac, m, rxhdr); } static void bwn_handle_txeof(struct bwn_mac *mac, const struct bwn_txstatus *status) { struct bwn_softc *sc = mac->mac_sc; struct bwn_stats *stats = &mac->mac_stats; BWN_ASSERT_LOCKED(mac->mac_sc); if (status->im) device_printf(sc->sc_dev, "TODO: STATUS IM\n"); if (status->ampdu) device_printf(sc->sc_dev, "TODO: STATUS AMPDU\n"); if (status->rtscnt) { if (status->rtscnt == 0xf) stats->rtsfail++; else stats->rts++; } if (mac->mac_flags & BWN_MAC_FLAG_DMA) { bwn_dma_handle_txeof(mac, status); } else { bwn_pio_handle_txeof(mac, status); } bwn_phy_txpower_check(mac, 0); } static uint8_t bwn_pio_rxeof(struct bwn_pio_rxqueue *prq) { struct bwn_mac *mac = prq->prq_mac; struct bwn_softc *sc = mac->mac_sc; struct bwn_rxhdr4 rxhdr; struct mbuf *m; uint32_t ctl32, macstat, v32; unsigned int i, padding; uint16_t ctl16, len, totlen, v16; unsigned char *mp; char *data; memset(&rxhdr, 0, sizeof(rxhdr)); if (prq->prq_rev >= 8) { ctl32 = bwn_pio_rx_read_4(prq, BWN_PIO8_RXCTL); if (!(ctl32 & BWN_PIO8_RXCTL_FRAMEREADY)) return (0); bwn_pio_rx_write_4(prq, BWN_PIO8_RXCTL, BWN_PIO8_RXCTL_FRAMEREADY); for (i = 0; i < 10; i++) { ctl32 = bwn_pio_rx_read_4(prq, BWN_PIO8_RXCTL); if (ctl32 & BWN_PIO8_RXCTL_DATAREADY) goto ready; DELAY(10); } } else { ctl16 = bwn_pio_rx_read_2(prq, BWN_PIO_RXCTL); if (!(ctl16 & BWN_PIO_RXCTL_FRAMEREADY)) return (0); bwn_pio_rx_write_2(prq, BWN_PIO_RXCTL, BWN_PIO_RXCTL_FRAMEREADY); for (i = 0; i < 10; i++) { ctl16 = bwn_pio_rx_read_2(prq, BWN_PIO_RXCTL); if (ctl16 & BWN_PIO_RXCTL_DATAREADY) goto ready; DELAY(10); } } device_printf(sc->sc_dev, "%s: timed out\n", __func__); return (1); ready: - if (prq->prq_rev >= 8) - siba_read_multi_4(sc->sc_dev, &rxhdr, sizeof(rxhdr), - prq->prq_base + BWN_PIO8_RXDATA); - else - siba_read_multi_2(sc->sc_dev, &rxhdr, sizeof(rxhdr), - prq->prq_base + BWN_PIO_RXDATA); + if (prq->prq_rev >= 8) { + bus_read_multi_4(sc->sc_mem_res, + prq->prq_base + BWN_PIO8_RXDATA, (void *)&rxhdr, + sizeof(rxhdr)); + } else { + bus_read_multi_2(sc->sc_mem_res, + prq->prq_base + BWN_PIO_RXDATA, (void *)&rxhdr, + sizeof(rxhdr)); + } len = le16toh(rxhdr.frame_len); if (len > 0x700) { device_printf(sc->sc_dev, "%s: len is too big\n", __func__); goto error; } if (len == 0) { device_printf(sc->sc_dev, "%s: len is 0\n", __func__); goto error; } switch (mac->mac_fw.fw_hdr_format) { case BWN_FW_HDR_351: case BWN_FW_HDR_410: macstat = le32toh(rxhdr.ps4.r351.mac_status); break; case BWN_FW_HDR_598: macstat = le32toh(rxhdr.ps4.r598.mac_status); break; } if (macstat & BWN_RX_MAC_FCSERR) { if (!(mac->mac_sc->sc_filters & BWN_MACCTL_PASS_BADFCS)) { device_printf(sc->sc_dev, "%s: FCS error", __func__); goto error; } } padding = (macstat & BWN_RX_MAC_PADDING) ? 2 : 0; totlen = len + padding; KASSERT(totlen <= MCLBYTES, ("too big..\n")); m = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR); if (m == NULL) { device_printf(sc->sc_dev, "%s: out of memory", __func__); goto error; } mp = mtod(m, unsigned char *); if (prq->prq_rev >= 8) { - siba_read_multi_4(sc->sc_dev, mp, (totlen & ~3), - prq->prq_base + BWN_PIO8_RXDATA); + bus_read_multi_4(sc->sc_mem_res, + prq->prq_base + BWN_PIO8_RXDATA, (void *)mp, (totlen & ~3)); if (totlen & 3) { v32 = bwn_pio_rx_read_4(prq, BWN_PIO8_RXDATA); data = &(mp[totlen - 1]); switch (totlen & 3) { case 3: *data = (v32 >> 16); data--; case 2: *data = (v32 >> 8); data--; case 1: *data = v32; } } } else { - siba_read_multi_2(sc->sc_dev, mp, (totlen & ~1), - prq->prq_base + BWN_PIO_RXDATA); + bus_read_multi_2(sc->sc_mem_res, + prq->prq_base + BWN_PIO_RXDATA, (void *)mp, (totlen & ~1)); if (totlen & 1) { v16 = bwn_pio_rx_read_2(prq, BWN_PIO_RXDATA); mp[totlen - 1] = v16; } } m->m_len = m->m_pkthdr.len = totlen; bwn_rxeof(prq->prq_mac, m, &rxhdr); return (1); error: if (prq->prq_rev >= 8) bwn_pio_rx_write_4(prq, BWN_PIO8_RXCTL, BWN_PIO8_RXCTL_DATAREADY); else bwn_pio_rx_write_2(prq, BWN_PIO_RXCTL, BWN_PIO_RXCTL_DATAREADY); return (1); } static int bwn_dma_newbuf(struct bwn_dma_ring *dr, struct bwn_dmadesc_generic *desc, struct bwn_dmadesc_meta *meta, int init) { struct bwn_mac *mac = dr->dr_mac; struct bwn_dma *dma = &mac->mac_method.dma; struct bwn_rxhdr4 *hdr; bus_dmamap_t map; bus_addr_t paddr; struct mbuf *m; int error; m = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR); if (m == NULL) { error = ENOBUFS; /* * If the NIC is up and running, we need to: * - Clear RX buffer's header. * - Restore RX descriptor settings. */ if (init) return (error); else goto back; } m->m_len = m->m_pkthdr.len = MCLBYTES; bwn_dma_set_redzone(dr, m); /* * Try to load RX buf into temporary DMA map */ error = bus_dmamap_load_mbuf(dma->rxbuf_dtag, dr->dr_spare_dmap, m, bwn_dma_buf_addr, &paddr, BUS_DMA_NOWAIT); if (error) { m_freem(m); /* * See the comment above */ if (init) return (error); else goto back; } if (!init) bus_dmamap_unload(dma->rxbuf_dtag, meta->mt_dmap); meta->mt_m = m; meta->mt_paddr = paddr; /* * Swap RX buf's DMA map with the loaded temporary one */ map = meta->mt_dmap; meta->mt_dmap = dr->dr_spare_dmap; dr->dr_spare_dmap = map; back: /* * Clear RX buf header */ hdr = mtod(meta->mt_m, struct bwn_rxhdr4 *); bzero(hdr, sizeof(*hdr)); bus_dmamap_sync(dma->rxbuf_dtag, meta->mt_dmap, BUS_DMASYNC_PREWRITE); /* * Setup RX buf descriptor */ dr->setdesc(dr, desc, meta->mt_paddr, meta->mt_m->m_len - sizeof(*hdr), 0, 0, 0); return (error); } static void bwn_dma_buf_addr(void *arg, bus_dma_segment_t *seg, int nseg, bus_size_t mapsz __unused, int error) { if (!error) { KASSERT(nseg == 1, ("too many segments(%d)\n", nseg)); *((bus_addr_t *)arg) = seg->ds_addr; } } static int bwn_hwrate2ieeerate(int rate) { switch (rate) { case BWN_CCK_RATE_1MB: return (2); case BWN_CCK_RATE_2MB: return (4); case BWN_CCK_RATE_5MB: return (11); case BWN_CCK_RATE_11MB: return (22); case BWN_OFDM_RATE_6MB: return (12); case BWN_OFDM_RATE_9MB: return (18); case BWN_OFDM_RATE_12MB: return (24); case BWN_OFDM_RATE_18MB: return (36); case BWN_OFDM_RATE_24MB: return (48); case BWN_OFDM_RATE_36MB: return (72); case BWN_OFDM_RATE_48MB: return (96); case BWN_OFDM_RATE_54MB: return (108); default: printf("Ooops\n"); return (0); } } /* * Post process the RX provided RSSI. * * Valid for A, B, G, LP PHYs. */ static int8_t bwn_rx_rssi_calc(struct bwn_mac *mac, uint8_t in_rssi, int ofdm, int adjust_2053, int adjust_2050) { struct bwn_phy *phy = &mac->mac_phy; struct bwn_phy_g *gphy = &phy->phy_g; int tmp; switch (phy->rf_ver) { case 0x2050: if (ofdm) { tmp = in_rssi; if (tmp > 127) tmp -= 256; tmp = tmp * 73 / 64; if (adjust_2050) tmp += 25; else tmp -= 3; } else { - if (siba_sprom_get_bf_lo(mac->mac_sc->sc_dev) - & BWN_BFL_RSSI) { + if (mac->mac_sc->sc_board_info.board_flags + & BHND_BFL_ADCDIV) { if (in_rssi > 63) in_rssi = 63; tmp = gphy->pg_nrssi_lt[in_rssi]; tmp = (31 - tmp) * -131 / 128 - 57; } else { tmp = in_rssi; tmp = (31 - tmp) * -149 / 128 - 68; } if (phy->type == BWN_PHYTYPE_G && adjust_2050) tmp += 25; } break; case 0x2060: if (in_rssi > 127) tmp = in_rssi - 256; else tmp = in_rssi; break; default: tmp = in_rssi; tmp = (tmp - 11) * 103 / 64; if (adjust_2053) tmp -= 109; else tmp -= 83; } return (tmp); } static void bwn_rxeof(struct bwn_mac *mac, struct mbuf *m, const void *_rxhdr) { const struct bwn_rxhdr4 *rxhdr = _rxhdr; struct bwn_plcp6 *plcp; struct bwn_softc *sc = mac->mac_sc; struct ieee80211_frame_min *wh; struct ieee80211_node *ni; struct ieee80211com *ic = &sc->sc_ic; uint32_t macstat; int padding, rate, rssi = 0, noise = 0, type; uint16_t phytype, phystat0, phystat3, chanstat; unsigned char *mp = mtod(m, unsigned char *); static int rx_mac_dec_rpt = 0; BWN_ASSERT_LOCKED(sc); phystat0 = le16toh(rxhdr->phy_status0); /* * XXX Note: phy_status3 doesn't exist for HT-PHY; it's only * used for LP-PHY. */ phystat3 = le16toh(rxhdr->ps3.lp.phy_status3); switch (mac->mac_fw.fw_hdr_format) { case BWN_FW_HDR_351: case BWN_FW_HDR_410: macstat = le32toh(rxhdr->ps4.r351.mac_status); chanstat = le16toh(rxhdr->ps4.r351.channel); break; case BWN_FW_HDR_598: macstat = le32toh(rxhdr->ps4.r598.mac_status); chanstat = le16toh(rxhdr->ps4.r598.channel); break; } phytype = chanstat & BWN_RX_CHAN_PHYTYPE; if (macstat & BWN_RX_MAC_FCSERR) device_printf(sc->sc_dev, "TODO RX: RX_FLAG_FAILED_FCS_CRC\n"); if (phystat0 & (BWN_RX_PHYST0_PLCPHCF | BWN_RX_PHYST0_PLCPFV)) device_printf(sc->sc_dev, "TODO RX: RX_FLAG_FAILED_PLCP_CRC\n"); if (macstat & BWN_RX_MAC_DECERR) goto drop; padding = (macstat & BWN_RX_MAC_PADDING) ? 2 : 0; if (m->m_pkthdr.len < (sizeof(struct bwn_plcp6) + padding)) { device_printf(sc->sc_dev, "frame too short (length=%d)\n", m->m_pkthdr.len); goto drop; } plcp = (struct bwn_plcp6 *)(mp + padding); m_adj(m, sizeof(struct bwn_plcp6) + padding); if (m->m_pkthdr.len < IEEE80211_MIN_LEN) { device_printf(sc->sc_dev, "frame too short (length=%d)\n", m->m_pkthdr.len); goto drop; } wh = mtod(m, struct ieee80211_frame_min *); if (macstat & BWN_RX_MAC_DEC && rx_mac_dec_rpt++ < 50) device_printf(sc->sc_dev, "RX decryption attempted (old %d keyidx %#x)\n", BWN_ISOLDFMT(mac), (macstat & BWN_RX_MAC_KEYIDX) >> BWN_RX_MAC_KEYIDX_SHIFT); if (phystat0 & BWN_RX_PHYST0_OFDM) rate = bwn_plcp_get_ofdmrate(mac, plcp, phytype == BWN_PHYTYPE_A); else rate = bwn_plcp_get_cckrate(mac, plcp); if (rate == -1) { if (!(mac->mac_sc->sc_filters & BWN_MACCTL_PASS_BADPLCP)) goto drop; } sc->sc_rx_rate = bwn_hwrate2ieeerate(rate); /* rssi/noise */ switch (phytype) { case BWN_PHYTYPE_A: case BWN_PHYTYPE_B: case BWN_PHYTYPE_G: case BWN_PHYTYPE_LP: rssi = bwn_rx_rssi_calc(mac, rxhdr->phy.abg.rssi, !! (phystat0 & BWN_RX_PHYST0_OFDM), !! (phystat0 & BWN_RX_PHYST0_GAINCTL), !! (phystat3 & BWN_RX_PHYST3_TRSTATE)); break; case BWN_PHYTYPE_N: /* Broadcom has code for min/avg, but always used max */ if (rxhdr->phy.n.power0 == 16 || rxhdr->phy.n.power0 == 32) rssi = max(rxhdr->phy.n.power1, rxhdr->ps2.n.power2); else rssi = max(rxhdr->phy.n.power0, rxhdr->phy.n.power1); #if 0 DPRINTF(mac->mac_sc, BWN_DEBUG_RECV, "%s: power0=%d, power1=%d, power2=%d\n", __func__, rxhdr->phy.n.power0, rxhdr->phy.n.power1, rxhdr->ps2.n.power2); #endif break; default: /* XXX TODO: implement rssi for other PHYs */ break; } /* * RSSI here is absolute, not relative to the noise floor. */ noise = mac->mac_stats.link_noise; rssi = rssi - noise; /* RX radio tap */ if (ieee80211_radiotap_active(ic)) bwn_rx_radiotap(mac, m, rxhdr, plcp, rate, rssi, noise); m_adj(m, -IEEE80211_CRC_LEN); BWN_UNLOCK(sc); ni = ieee80211_find_rxnode(ic, wh); if (ni != NULL) { type = ieee80211_input(ni, m, rssi, noise); ieee80211_free_node(ni); } else type = ieee80211_input_all(ic, m, rssi, noise); BWN_LOCK(sc); return; drop: device_printf(sc->sc_dev, "%s: dropped\n", __func__); } static void bwn_ratectl_tx_complete(const struct ieee80211_node *ni, const struct bwn_txstatus *status) { struct ieee80211_ratectl_tx_status txs; int retrycnt = 0; /* * If we don't get an ACK, then we should log the * full framecnt. That may be 0 if it's a PHY * failure, so ensure that gets logged as some * retry attempt. */ txs.flags = IEEE80211_RATECTL_STATUS_LONG_RETRY; if (status->ack) { txs.status = IEEE80211_RATECTL_TX_SUCCESS; retrycnt = status->framecnt - 1; } else { txs.status = IEEE80211_RATECTL_TX_FAIL_UNSPECIFIED; retrycnt = status->framecnt; if (retrycnt == 0) retrycnt = 1; } txs.long_retries = retrycnt; ieee80211_ratectl_tx_complete(ni, &txs); } static void bwn_dma_handle_txeof(struct bwn_mac *mac, const struct bwn_txstatus *status) { struct bwn_dma *dma = &mac->mac_method.dma; struct bwn_dma_ring *dr; struct bwn_dmadesc_generic *desc; struct bwn_dmadesc_meta *meta; struct bwn_softc *sc = mac->mac_sc; int slot; BWN_ASSERT_LOCKED(sc); dr = bwn_dma_parse_cookie(mac, status, status->cookie, &slot); if (dr == NULL) { device_printf(sc->sc_dev, "failed to parse cookie\n"); return; } KASSERT(dr->dr_tx, ("%s:%d: fail", __func__, __LINE__)); while (1) { KASSERT(slot >= 0 && slot < dr->dr_numslots, ("%s:%d: fail", __func__, __LINE__)); dr->getdesc(dr, slot, &desc, &meta); if (meta->mt_txtype == BWN_DMADESC_METATYPE_HEADER) bus_dmamap_unload(dr->dr_txring_dtag, meta->mt_dmap); else if (meta->mt_txtype == BWN_DMADESC_METATYPE_BODY) bus_dmamap_unload(dma->txbuf_dtag, meta->mt_dmap); if (meta->mt_islast) { KASSERT(meta->mt_m != NULL, ("%s:%d: fail", __func__, __LINE__)); bwn_ratectl_tx_complete(meta->mt_ni, status); ieee80211_tx_complete(meta->mt_ni, meta->mt_m, 0); meta->mt_ni = NULL; meta->mt_m = NULL; } else KASSERT(meta->mt_m == NULL, ("%s:%d: fail", __func__, __LINE__)); dr->dr_usedslot--; if (meta->mt_islast) break; slot = bwn_dma_nextslot(dr, slot); } sc->sc_watchdog_timer = 0; if (dr->dr_stop) { KASSERT(bwn_dma_freeslot(dr) >= BWN_TX_SLOTS_PER_FRAME, ("%s:%d: fail", __func__, __LINE__)); dr->dr_stop = 0; } } static void bwn_pio_handle_txeof(struct bwn_mac *mac, const struct bwn_txstatus *status) { struct bwn_pio_txqueue *tq; struct bwn_pio_txpkt *tp = NULL; struct bwn_softc *sc = mac->mac_sc; BWN_ASSERT_LOCKED(sc); tq = bwn_pio_parse_cookie(mac, status->cookie, &tp); if (tq == NULL) return; tq->tq_used -= roundup(tp->tp_m->m_pkthdr.len + BWN_HDRSIZE(mac), 4); tq->tq_free++; /* XXX ieee80211_tx_complete()? */ if (tp->tp_ni != NULL) { /* * Do any tx complete callback. Note this must * be done before releasing the node reference. */ bwn_ratectl_tx_complete(tp->tp_ni, status); if (tp->tp_m->m_flags & M_TXCB) ieee80211_process_callback(tp->tp_ni, tp->tp_m, 0); ieee80211_free_node(tp->tp_ni); tp->tp_ni = NULL; } m_freem(tp->tp_m); tp->tp_m = NULL; TAILQ_INSERT_TAIL(&tq->tq_pktlist, tp, tp_list); sc->sc_watchdog_timer = 0; } static void bwn_phy_txpower_check(struct bwn_mac *mac, uint32_t flags) { struct bwn_softc *sc = mac->mac_sc; struct bwn_phy *phy = &mac->mac_phy; struct ieee80211com *ic = &sc->sc_ic; unsigned long now; bwn_txpwr_result_t result; BWN_GETTIME(now); if (!(flags & BWN_TXPWR_IGNORE_TIME) && ieee80211_time_before(now, phy->nexttime)) return; phy->nexttime = now + 2 * 1000; - if (siba_get_pci_subvendor(sc->sc_dev) == SIBA_BOARDVENDOR_BCM && - siba_get_pci_subdevice(sc->sc_dev) == SIBA_BOARD_BU4306) + if (sc->sc_board_info.board_vendor == PCI_VENDOR_BROADCOM && + sc->sc_board_info.board_type == BHND_BOARD_BU4306) return; if (phy->recalc_txpwr != NULL) { result = phy->recalc_txpwr(mac, (flags & BWN_TXPWR_IGNORE_TSSI) ? 1 : 0); if (result == BWN_TXPWR_RES_DONE) return; KASSERT(result == BWN_TXPWR_RES_NEED_ADJUST, ("%s: fail", __func__)); KASSERT(phy->set_txpwr != NULL, ("%s: fail", __func__)); ieee80211_runtask(ic, &mac->mac_txpower); } } static uint16_t bwn_pio_rx_read_2(struct bwn_pio_rxqueue *prq, uint16_t offset) { return (BWN_READ_2(prq->prq_mac, prq->prq_base + offset)); } static uint32_t bwn_pio_rx_read_4(struct bwn_pio_rxqueue *prq, uint16_t offset) { return (BWN_READ_4(prq->prq_mac, prq->prq_base + offset)); } static void bwn_pio_rx_write_2(struct bwn_pio_rxqueue *prq, uint16_t offset, uint16_t value) { BWN_WRITE_2(prq->prq_mac, prq->prq_base + offset, value); } static void bwn_pio_rx_write_4(struct bwn_pio_rxqueue *prq, uint16_t offset, uint32_t value) { BWN_WRITE_4(prq->prq_mac, prq->prq_base + offset, value); } static int bwn_ieeerate2hwrate(struct bwn_softc *sc, int rate) { switch (rate) { /* OFDM rates (cf IEEE Std 802.11a-1999, pp. 14 Table 80) */ case 12: return (BWN_OFDM_RATE_6MB); case 18: return (BWN_OFDM_RATE_9MB); case 24: return (BWN_OFDM_RATE_12MB); case 36: return (BWN_OFDM_RATE_18MB); case 48: return (BWN_OFDM_RATE_24MB); case 72: return (BWN_OFDM_RATE_36MB); case 96: return (BWN_OFDM_RATE_48MB); case 108: return (BWN_OFDM_RATE_54MB); /* CCK rates (NB: not IEEE std, device-specific) */ case 2: return (BWN_CCK_RATE_1MB); case 4: return (BWN_CCK_RATE_2MB); case 11: return (BWN_CCK_RATE_5MB); case 22: return (BWN_CCK_RATE_11MB); } device_printf(sc->sc_dev, "unsupported rate %d\n", rate); return (BWN_CCK_RATE_1MB); } static uint16_t bwn_set_txhdr_phyctl1(struct bwn_mac *mac, uint8_t bitrate) { struct bwn_phy *phy = &mac->mac_phy; uint16_t control = 0; uint16_t bw; /* XXX TODO: this is for LP phy, what about N-PHY, etc? */ bw = BWN_TXH_PHY1_BW_20; if (BWN_ISCCKRATE(bitrate) && phy->type != BWN_PHYTYPE_LP) { control = bw; } else { control = bw; /* Figure out coding rate and modulation */ /* XXX TODO: table-ize, for MCS transmit */ /* Note: this is BWN_*_RATE values */ switch (bitrate) { case BWN_CCK_RATE_1MB: control |= 0; break; case BWN_CCK_RATE_2MB: control |= 1; break; case BWN_CCK_RATE_5MB: control |= 2; break; case BWN_CCK_RATE_11MB: control |= 3; break; case BWN_OFDM_RATE_6MB: control |= BWN_TXH_PHY1_CRATE_1_2; control |= BWN_TXH_PHY1_MODUL_BPSK; break; case BWN_OFDM_RATE_9MB: control |= BWN_TXH_PHY1_CRATE_3_4; control |= BWN_TXH_PHY1_MODUL_BPSK; break; case BWN_OFDM_RATE_12MB: control |= BWN_TXH_PHY1_CRATE_1_2; control |= BWN_TXH_PHY1_MODUL_QPSK; break; case BWN_OFDM_RATE_18MB: control |= BWN_TXH_PHY1_CRATE_3_4; control |= BWN_TXH_PHY1_MODUL_QPSK; break; case BWN_OFDM_RATE_24MB: control |= BWN_TXH_PHY1_CRATE_1_2; control |= BWN_TXH_PHY1_MODUL_QAM16; break; case BWN_OFDM_RATE_36MB: control |= BWN_TXH_PHY1_CRATE_3_4; control |= BWN_TXH_PHY1_MODUL_QAM16; break; case BWN_OFDM_RATE_48MB: control |= BWN_TXH_PHY1_CRATE_1_2; control |= BWN_TXH_PHY1_MODUL_QAM64; break; case BWN_OFDM_RATE_54MB: control |= BWN_TXH_PHY1_CRATE_3_4; control |= BWN_TXH_PHY1_MODUL_QAM64; break; default: break; } control |= BWN_TXH_PHY1_MODE_SISO; } return control; } static int bwn_set_txhdr(struct bwn_mac *mac, struct ieee80211_node *ni, struct mbuf *m, struct bwn_txhdr *txhdr, uint16_t cookie) { const struct bwn_phy *phy = &mac->mac_phy; struct bwn_softc *sc = mac->mac_sc; struct ieee80211_frame *wh; struct ieee80211_frame *protwh; struct ieee80211_frame_cts *cts; struct ieee80211_frame_rts *rts; const struct ieee80211_txparam *tp = ni->ni_txparms; struct ieee80211vap *vap = ni->ni_vap; struct ieee80211com *ic = &sc->sc_ic; struct mbuf *mprot; unsigned int len; uint32_t macctl = 0; int protdur, rts_rate, rts_rate_fb, ismcast, isshort, rix, type; uint16_t phyctl = 0; uint8_t rate, rate_fb; int fill_phy_ctl1 = 0; wh = mtod(m, struct ieee80211_frame *); memset(txhdr, 0, sizeof(*txhdr)); type = wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK; ismcast = IEEE80211_IS_MULTICAST(wh->i_addr1); isshort = (ic->ic_flags & IEEE80211_F_SHPREAMBLE) != 0; if ((phy->type == BWN_PHYTYPE_N) || (phy->type == BWN_PHYTYPE_LP) || (phy->type == BWN_PHYTYPE_HT)) fill_phy_ctl1 = 1; /* * Find TX rate */ if (type != IEEE80211_FC0_TYPE_DATA || (m->m_flags & M_EAPOL)) rate = rate_fb = tp->mgmtrate; else if (ismcast) rate = rate_fb = tp->mcastrate; else if (tp->ucastrate != IEEE80211_FIXED_RATE_NONE) rate = rate_fb = tp->ucastrate; else { rix = ieee80211_ratectl_rate(ni, NULL, 0); rate = ni->ni_txrate; if (rix > 0) rate_fb = ni->ni_rates.rs_rates[rix - 1] & IEEE80211_RATE_VAL; else rate_fb = rate; } sc->sc_tx_rate = rate; /* Note: this maps the select ieee80211 rate to hardware rate */ rate = bwn_ieeerate2hwrate(sc, rate); rate_fb = bwn_ieeerate2hwrate(sc, rate_fb); txhdr->phyrate = (BWN_ISOFDMRATE(rate)) ? bwn_plcp_getofdm(rate) : bwn_plcp_getcck(rate); bcopy(wh->i_fc, txhdr->macfc, sizeof(txhdr->macfc)); bcopy(wh->i_addr1, txhdr->addr1, IEEE80211_ADDR_LEN); /* XXX rate/rate_fb is the hardware rate */ if ((rate_fb == rate) || (*(u_int16_t *)wh->i_dur & htole16(0x8000)) || (*(u_int16_t *)wh->i_dur == htole16(0))) txhdr->dur_fb = *(u_int16_t *)wh->i_dur; else txhdr->dur_fb = ieee80211_compute_duration(ic->ic_rt, m->m_pkthdr.len, rate, isshort); /* XXX TX encryption */ switch (mac->mac_fw.fw_hdr_format) { case BWN_FW_HDR_351: bwn_plcp_genhdr((struct bwn_plcp4 *)(&txhdr->body.r351.plcp), m->m_pkthdr.len + IEEE80211_CRC_LEN, rate); break; case BWN_FW_HDR_410: bwn_plcp_genhdr((struct bwn_plcp4 *)(&txhdr->body.r410.plcp), m->m_pkthdr.len + IEEE80211_CRC_LEN, rate); break; case BWN_FW_HDR_598: bwn_plcp_genhdr((struct bwn_plcp4 *)(&txhdr->body.r598.plcp), m->m_pkthdr.len + IEEE80211_CRC_LEN, rate); break; } bwn_plcp_genhdr((struct bwn_plcp4 *)(&txhdr->plcp_fb), m->m_pkthdr.len + IEEE80211_CRC_LEN, rate_fb); txhdr->eftypes |= (BWN_ISOFDMRATE(rate_fb)) ? BWN_TX_EFT_FB_OFDM : BWN_TX_EFT_FB_CCK; txhdr->chan = phy->chan; phyctl |= (BWN_ISOFDMRATE(rate)) ? BWN_TX_PHY_ENC_OFDM : BWN_TX_PHY_ENC_CCK; /* XXX preamble? obey net80211 */ if (isshort && (rate == BWN_CCK_RATE_2MB || rate == BWN_CCK_RATE_5MB || rate == BWN_CCK_RATE_11MB)) phyctl |= BWN_TX_PHY_SHORTPRMBL; if (! phy->gmode) macctl |= BWN_TX_MAC_5GHZ; /* XXX TX antenna selection */ switch (bwn_antenna_sanitize(mac, 0)) { case 0: phyctl |= BWN_TX_PHY_ANT01AUTO; break; case 1: phyctl |= BWN_TX_PHY_ANT0; break; case 2: phyctl |= BWN_TX_PHY_ANT1; break; case 3: phyctl |= BWN_TX_PHY_ANT2; break; case 4: phyctl |= BWN_TX_PHY_ANT3; break; default: KASSERT(0 == 1, ("%s:%d: fail", __func__, __LINE__)); } if (!ismcast) macctl |= BWN_TX_MAC_ACK; macctl |= (BWN_TX_MAC_HWSEQ | BWN_TX_MAC_START_MSDU); if (!IEEE80211_IS_MULTICAST(wh->i_addr1) && m->m_pkthdr.len + IEEE80211_CRC_LEN > vap->iv_rtsthreshold) macctl |= BWN_TX_MAC_LONGFRAME; if (ic->ic_flags & IEEE80211_F_USEPROT) { /* Note: don't fall back to CCK rates for 5G */ if (phy->gmode) rts_rate = BWN_CCK_RATE_1MB; else rts_rate = BWN_OFDM_RATE_6MB; rts_rate_fb = bwn_get_fbrate(rts_rate); /* XXX 'rate' here is hardware rate now, not the net80211 rate */ protdur = ieee80211_compute_duration(ic->ic_rt, m->m_pkthdr.len, rate, isshort) + + ieee80211_ack_duration(ic->ic_rt, rate, isshort); if (ic->ic_protmode == IEEE80211_PROT_CTSONLY) { switch (mac->mac_fw.fw_hdr_format) { case BWN_FW_HDR_351: cts = (struct ieee80211_frame_cts *) txhdr->body.r351.rts_frame; break; case BWN_FW_HDR_410: cts = (struct ieee80211_frame_cts *) txhdr->body.r410.rts_frame; break; case BWN_FW_HDR_598: cts = (struct ieee80211_frame_cts *) txhdr->body.r598.rts_frame; break; } mprot = ieee80211_alloc_cts(ic, ni->ni_vap->iv_myaddr, protdur); KASSERT(mprot != NULL, ("failed to alloc mbuf\n")); bcopy(mtod(mprot, uint8_t *), (uint8_t *)cts, mprot->m_pkthdr.len); m_freem(mprot); macctl |= BWN_TX_MAC_SEND_CTSTOSELF; len = sizeof(struct ieee80211_frame_cts); } else { switch (mac->mac_fw.fw_hdr_format) { case BWN_FW_HDR_351: rts = (struct ieee80211_frame_rts *) txhdr->body.r351.rts_frame; break; case BWN_FW_HDR_410: rts = (struct ieee80211_frame_rts *) txhdr->body.r410.rts_frame; break; case BWN_FW_HDR_598: rts = (struct ieee80211_frame_rts *) txhdr->body.r598.rts_frame; break; } /* XXX rate/rate_fb is the hardware rate */ protdur += ieee80211_ack_duration(ic->ic_rt, rate, isshort); mprot = ieee80211_alloc_rts(ic, wh->i_addr1, wh->i_addr2, protdur); KASSERT(mprot != NULL, ("failed to alloc mbuf\n")); bcopy(mtod(mprot, uint8_t *), (uint8_t *)rts, mprot->m_pkthdr.len); m_freem(mprot); macctl |= BWN_TX_MAC_SEND_RTSCTS; len = sizeof(struct ieee80211_frame_rts); } len += IEEE80211_CRC_LEN; switch (mac->mac_fw.fw_hdr_format) { case BWN_FW_HDR_351: bwn_plcp_genhdr((struct bwn_plcp4 *) &txhdr->body.r351.rts_plcp, len, rts_rate); break; case BWN_FW_HDR_410: bwn_plcp_genhdr((struct bwn_plcp4 *) &txhdr->body.r410.rts_plcp, len, rts_rate); break; case BWN_FW_HDR_598: bwn_plcp_genhdr((struct bwn_plcp4 *) &txhdr->body.r598.rts_plcp, len, rts_rate); break; } bwn_plcp_genhdr((struct bwn_plcp4 *)&txhdr->rts_plcp_fb, len, rts_rate_fb); switch (mac->mac_fw.fw_hdr_format) { case BWN_FW_HDR_351: protwh = (struct ieee80211_frame *) &txhdr->body.r351.rts_frame; break; case BWN_FW_HDR_410: protwh = (struct ieee80211_frame *) &txhdr->body.r410.rts_frame; break; case BWN_FW_HDR_598: protwh = (struct ieee80211_frame *) &txhdr->body.r598.rts_frame; break; } txhdr->rts_dur_fb = *(u_int16_t *)protwh->i_dur; if (BWN_ISOFDMRATE(rts_rate)) { txhdr->eftypes |= BWN_TX_EFT_RTS_OFDM; txhdr->phyrate_rts = bwn_plcp_getofdm(rts_rate); } else { txhdr->eftypes |= BWN_TX_EFT_RTS_CCK; txhdr->phyrate_rts = bwn_plcp_getcck(rts_rate); } txhdr->eftypes |= (BWN_ISOFDMRATE(rts_rate_fb)) ? BWN_TX_EFT_RTS_FBOFDM : BWN_TX_EFT_RTS_FBCCK; if (fill_phy_ctl1) { txhdr->phyctl_1rts = htole16(bwn_set_txhdr_phyctl1(mac, rts_rate)); txhdr->phyctl_1rtsfb = htole16(bwn_set_txhdr_phyctl1(mac, rts_rate_fb)); } } if (fill_phy_ctl1) { txhdr->phyctl_1 = htole16(bwn_set_txhdr_phyctl1(mac, rate)); txhdr->phyctl_1fb = htole16(bwn_set_txhdr_phyctl1(mac, rate_fb)); } switch (mac->mac_fw.fw_hdr_format) { case BWN_FW_HDR_351: txhdr->body.r351.cookie = htole16(cookie); break; case BWN_FW_HDR_410: txhdr->body.r410.cookie = htole16(cookie); break; case BWN_FW_HDR_598: txhdr->body.r598.cookie = htole16(cookie); break; } txhdr->macctl = htole32(macctl); txhdr->phyctl = htole16(phyctl); /* * TX radio tap */ if (ieee80211_radiotap_active_vap(vap)) { sc->sc_tx_th.wt_flags = 0; if (wh->i_fc[1] & IEEE80211_FC1_PROTECTED) sc->sc_tx_th.wt_flags |= IEEE80211_RADIOTAP_F_WEP; if (isshort && (rate == BWN_CCK_RATE_2MB || rate == BWN_CCK_RATE_5MB || rate == BWN_CCK_RATE_11MB)) sc->sc_tx_th.wt_flags |= IEEE80211_RADIOTAP_F_SHORTPRE; sc->sc_tx_th.wt_rate = rate; ieee80211_radiotap_tx(vap, m); } return (0); } static void bwn_plcp_genhdr(struct bwn_plcp4 *plcp, const uint16_t octets, const uint8_t rate) { uint32_t d, plen; uint8_t *raw = plcp->o.raw; if (BWN_ISOFDMRATE(rate)) { d = bwn_plcp_getofdm(rate); KASSERT(!(octets & 0xf000), ("%s:%d: fail", __func__, __LINE__)); d |= (octets << 5); plcp->o.data = htole32(d); } else { plen = octets * 16 / rate; if ((octets * 16 % rate) > 0) { plen++; if ((rate == BWN_CCK_RATE_11MB) && ((octets * 8 % 11) < 4)) { raw[1] = 0x84; } else raw[1] = 0x04; } else raw[1] = 0x04; plcp->o.data |= htole32(plen << 16); raw[0] = bwn_plcp_getcck(rate); } } static uint8_t bwn_antenna_sanitize(struct bwn_mac *mac, uint8_t n) { struct bwn_softc *sc = mac->mac_sc; uint8_t mask; if (n == 0) return (0); if (mac->mac_phy.gmode) - mask = siba_sprom_get_ant_bg(sc->sc_dev); + mask = sc->sc_ant2g; else - mask = siba_sprom_get_ant_a(sc->sc_dev); + mask = sc->sc_ant5g; if (!(mask & (1 << (n - 1)))) return (0); return (n); } /* * Return a fallback rate for the given rate. * * Note: Don't fall back from OFDM to CCK. */ static uint8_t bwn_get_fbrate(uint8_t bitrate) { switch (bitrate) { /* CCK */ case BWN_CCK_RATE_1MB: return (BWN_CCK_RATE_1MB); case BWN_CCK_RATE_2MB: return (BWN_CCK_RATE_1MB); case BWN_CCK_RATE_5MB: return (BWN_CCK_RATE_2MB); case BWN_CCK_RATE_11MB: return (BWN_CCK_RATE_5MB); /* OFDM */ case BWN_OFDM_RATE_6MB: return (BWN_OFDM_RATE_6MB); case BWN_OFDM_RATE_9MB: return (BWN_OFDM_RATE_6MB); case BWN_OFDM_RATE_12MB: return (BWN_OFDM_RATE_9MB); case BWN_OFDM_RATE_18MB: return (BWN_OFDM_RATE_12MB); case BWN_OFDM_RATE_24MB: return (BWN_OFDM_RATE_18MB); case BWN_OFDM_RATE_36MB: return (BWN_OFDM_RATE_24MB); case BWN_OFDM_RATE_48MB: return (BWN_OFDM_RATE_36MB); case BWN_OFDM_RATE_54MB: return (BWN_OFDM_RATE_48MB); } KASSERT(0 == 1, ("%s:%d: fail", __func__, __LINE__)); return (0); } static uint32_t bwn_pio_write_multi_4(struct bwn_mac *mac, struct bwn_pio_txqueue *tq, uint32_t ctl, const void *_data, int len) { struct bwn_softc *sc = mac->mac_sc; uint32_t value = 0; const uint8_t *data = _data; ctl |= BWN_PIO8_TXCTL_0_7 | BWN_PIO8_TXCTL_8_15 | BWN_PIO8_TXCTL_16_23 | BWN_PIO8_TXCTL_24_31; bwn_pio_write_4(mac, tq, BWN_PIO8_TXCTL, ctl); - siba_write_multi_4(sc->sc_dev, data, (len & ~3), - tq->tq_base + BWN_PIO8_TXDATA); + bus_write_multi_4(sc->sc_mem_res, tq->tq_base + BWN_PIO8_TXDATA, + __DECONST(void *, data), (len & ~3)); if (len & 3) { ctl &= ~(BWN_PIO8_TXCTL_8_15 | BWN_PIO8_TXCTL_16_23 | BWN_PIO8_TXCTL_24_31); data = &(data[len - 1]); switch (len & 3) { case 3: ctl |= BWN_PIO8_TXCTL_16_23; value |= (uint32_t)(*data) << 16; data--; case 2: ctl |= BWN_PIO8_TXCTL_8_15; value |= (uint32_t)(*data) << 8; data--; case 1: value |= (uint32_t)(*data); } bwn_pio_write_4(mac, tq, BWN_PIO8_TXCTL, ctl); bwn_pio_write_4(mac, tq, BWN_PIO8_TXDATA, value); } return (ctl); } static void bwn_pio_write_4(struct bwn_mac *mac, struct bwn_pio_txqueue *tq, uint16_t offset, uint32_t value) { BWN_WRITE_4(mac, tq->tq_base + offset, value); } static uint16_t bwn_pio_write_multi_2(struct bwn_mac *mac, struct bwn_pio_txqueue *tq, uint16_t ctl, const void *_data, int len) { struct bwn_softc *sc = mac->mac_sc; const uint8_t *data = _data; ctl |= BWN_PIO_TXCTL_WRITELO | BWN_PIO_TXCTL_WRITEHI; BWN_PIO_WRITE_2(mac, tq, BWN_PIO_TXCTL, ctl); - siba_write_multi_2(sc->sc_dev, data, (len & ~1), - tq->tq_base + BWN_PIO_TXDATA); + bus_write_multi_2(sc->sc_mem_res, tq->tq_base + BWN_PIO_TXDATA, + __DECONST(void *, data), (len & ~1)); if (len & 1) { ctl &= ~BWN_PIO_TXCTL_WRITEHI; BWN_PIO_WRITE_2(mac, tq, BWN_PIO_TXCTL, ctl); BWN_PIO_WRITE_2(mac, tq, BWN_PIO_TXDATA, data[len - 1]); } return (ctl); } static uint16_t bwn_pio_write_mbuf_2(struct bwn_mac *mac, struct bwn_pio_txqueue *tq, uint16_t ctl, struct mbuf *m0) { int i, j = 0; uint16_t data = 0; const uint8_t *buf; struct mbuf *m = m0; ctl |= BWN_PIO_TXCTL_WRITELO | BWN_PIO_TXCTL_WRITEHI; BWN_PIO_WRITE_2(mac, tq, BWN_PIO_TXCTL, ctl); for (; m != NULL; m = m->m_next) { buf = mtod(m, const uint8_t *); for (i = 0; i < m->m_len; i++) { if (!((j++) % 2)) data |= buf[i]; else { data |= (buf[i] << 8); BWN_PIO_WRITE_2(mac, tq, BWN_PIO_TXDATA, data); data = 0; } } } if (m0->m_pkthdr.len % 2) { ctl &= ~BWN_PIO_TXCTL_WRITEHI; BWN_PIO_WRITE_2(mac, tq, BWN_PIO_TXCTL, ctl); BWN_PIO_WRITE_2(mac, tq, BWN_PIO_TXDATA, data); } return (ctl); } static void bwn_set_slot_time(struct bwn_mac *mac, uint16_t time) { /* XXX should exit if 5GHz band .. */ if (mac->mac_phy.type != BWN_PHYTYPE_G) return; BWN_WRITE_2(mac, 0x684, 510 + time); /* Disabled in Linux b43, can adversely effect performance */ #if 0 bwn_shm_write_2(mac, BWN_SHARED, 0x0010, time); #endif } static struct bwn_dma_ring * bwn_dma_select(struct bwn_mac *mac, uint8_t prio) { if ((mac->mac_flags & BWN_MAC_FLAG_WME) == 0) return (mac->mac_method.dma.wme[WME_AC_BE]); switch (prio) { case 3: return (mac->mac_method.dma.wme[WME_AC_VO]); case 2: return (mac->mac_method.dma.wme[WME_AC_VI]); case 0: return (mac->mac_method.dma.wme[WME_AC_BE]); case 1: return (mac->mac_method.dma.wme[WME_AC_BK]); } KASSERT(0 == 1, ("%s:%d: fail", __func__, __LINE__)); return (NULL); } static int bwn_dma_getslot(struct bwn_dma_ring *dr) { int slot; BWN_ASSERT_LOCKED(dr->dr_mac->mac_sc); KASSERT(dr->dr_tx, ("%s:%d: fail", __func__, __LINE__)); KASSERT(!(dr->dr_stop), ("%s:%d: fail", __func__, __LINE__)); KASSERT(bwn_dma_freeslot(dr) != 0, ("%s:%d: fail", __func__, __LINE__)); slot = bwn_dma_nextslot(dr, dr->dr_curslot); KASSERT(!(slot & ~0x0fff), ("%s:%d: fail", __func__, __LINE__)); dr->dr_curslot = slot; dr->dr_usedslot++; return (slot); } static struct bwn_pio_txqueue * bwn_pio_parse_cookie(struct bwn_mac *mac, uint16_t cookie, struct bwn_pio_txpkt **pack) { struct bwn_pio *pio = &mac->mac_method.pio; struct bwn_pio_txqueue *tq = NULL; unsigned int index; switch (cookie & 0xf000) { case 0x1000: tq = &pio->wme[WME_AC_BK]; break; case 0x2000: tq = &pio->wme[WME_AC_BE]; break; case 0x3000: tq = &pio->wme[WME_AC_VI]; break; case 0x4000: tq = &pio->wme[WME_AC_VO]; break; case 0x5000: tq = &pio->mcast; break; } KASSERT(tq != NULL, ("%s:%d: fail", __func__, __LINE__)); if (tq == NULL) return (NULL); index = (cookie & 0x0fff); KASSERT(index < N(tq->tq_pkts), ("%s:%d: fail", __func__, __LINE__)); if (index >= N(tq->tq_pkts)) return (NULL); *pack = &tq->tq_pkts[index]; KASSERT(*pack != NULL, ("%s:%d: fail", __func__, __LINE__)); return (tq); } static void bwn_txpwr(void *arg, int npending) { struct bwn_mac *mac = arg; struct bwn_softc *sc; if (mac == NULL) return; sc = mac->mac_sc; BWN_LOCK(sc); if (mac->mac_status >= BWN_MAC_STATUS_STARTED && mac->mac_phy.set_txpwr != NULL) mac->mac_phy.set_txpwr(mac); BWN_UNLOCK(sc); } static void bwn_task_15s(struct bwn_mac *mac) { uint16_t reg; if (mac->mac_fw.opensource) { reg = bwn_shm_read_2(mac, BWN_SCRATCH, BWN_WATCHDOG_REG); if (reg) { bwn_restart(mac, "fw watchdog"); return; } bwn_shm_write_2(mac, BWN_SCRATCH, BWN_WATCHDOG_REG, 1); } if (mac->mac_phy.task_15s) mac->mac_phy.task_15s(mac); mac->mac_phy.txerrors = BWN_TXERROR_MAX; } static void bwn_task_30s(struct bwn_mac *mac) { if (mac->mac_phy.type != BWN_PHYTYPE_G || mac->mac_noise.noi_running) return; mac->mac_noise.noi_running = 1; mac->mac_noise.noi_nsamples = 0; bwn_noise_gensample(mac); } static void bwn_task_60s(struct bwn_mac *mac) { if (mac->mac_phy.task_60s) mac->mac_phy.task_60s(mac); bwn_phy_txpower_check(mac, BWN_TXPWR_IGNORE_TIME); } static void bwn_tasks(void *arg) { struct bwn_mac *mac = arg; struct bwn_softc *sc = mac->mac_sc; BWN_ASSERT_LOCKED(sc); if (mac->mac_status != BWN_MAC_STATUS_STARTED) return; if (mac->mac_task_state % 4 == 0) bwn_task_60s(mac); if (mac->mac_task_state % 2 == 0) bwn_task_30s(mac); bwn_task_15s(mac); mac->mac_task_state++; callout_reset(&sc->sc_task_ch, hz * 15, bwn_tasks, mac); } static int bwn_plcp_get_ofdmrate(struct bwn_mac *mac, struct bwn_plcp6 *plcp, uint8_t a) { struct bwn_softc *sc = mac->mac_sc; KASSERT(a == 0, ("not support APHY\n")); switch (plcp->o.raw[0] & 0xf) { case 0xb: return (BWN_OFDM_RATE_6MB); case 0xf: return (BWN_OFDM_RATE_9MB); case 0xa: return (BWN_OFDM_RATE_12MB); case 0xe: return (BWN_OFDM_RATE_18MB); case 0x9: return (BWN_OFDM_RATE_24MB); case 0xd: return (BWN_OFDM_RATE_36MB); case 0x8: return (BWN_OFDM_RATE_48MB); case 0xc: return (BWN_OFDM_RATE_54MB); } device_printf(sc->sc_dev, "incorrect OFDM rate %d\n", plcp->o.raw[0] & 0xf); return (-1); } static int bwn_plcp_get_cckrate(struct bwn_mac *mac, struct bwn_plcp6 *plcp) { struct bwn_softc *sc = mac->mac_sc; switch (plcp->o.raw[0]) { case 0x0a: return (BWN_CCK_RATE_1MB); case 0x14: return (BWN_CCK_RATE_2MB); case 0x37: return (BWN_CCK_RATE_5MB); case 0x6e: return (BWN_CCK_RATE_11MB); } device_printf(sc->sc_dev, "incorrect CCK rate %d\n", plcp->o.raw[0]); return (-1); } static void bwn_rx_radiotap(struct bwn_mac *mac, struct mbuf *m, const struct bwn_rxhdr4 *rxhdr, struct bwn_plcp6 *plcp, int rate, int rssi, int noise) { struct bwn_softc *sc = mac->mac_sc; const struct ieee80211_frame_min *wh; uint64_t tsf; uint16_t low_mactime_now; uint16_t mt; if (htole16(rxhdr->phy_status0) & BWN_RX_PHYST0_SHORTPRMBL) sc->sc_rx_th.wr_flags |= IEEE80211_RADIOTAP_F_SHORTPRE; wh = mtod(m, const struct ieee80211_frame_min *); if (wh->i_fc[1] & IEEE80211_FC1_PROTECTED) sc->sc_rx_th.wr_flags |= IEEE80211_RADIOTAP_F_WEP; bwn_tsf_read(mac, &tsf); low_mactime_now = tsf; tsf = tsf & ~0xffffULL; switch (mac->mac_fw.fw_hdr_format) { case BWN_FW_HDR_351: case BWN_FW_HDR_410: mt = le16toh(rxhdr->ps4.r351.mac_time); break; case BWN_FW_HDR_598: mt = le16toh(rxhdr->ps4.r598.mac_time); break; } tsf += mt; if (low_mactime_now < mt) tsf -= 0x10000; sc->sc_rx_th.wr_tsf = tsf; sc->sc_rx_th.wr_rate = rate; sc->sc_rx_th.wr_antsignal = rssi; sc->sc_rx_th.wr_antnoise = noise; } static void bwn_tsf_read(struct bwn_mac *mac, uint64_t *tsf) { uint32_t low, high; - KASSERT(siba_get_revid(mac->mac_sc->sc_dev) >= 3, + KASSERT(bhnd_get_hwrev(mac->mac_sc->sc_dev) >= 3, ("%s:%d: fail", __func__, __LINE__)); low = BWN_READ_4(mac, BWN_REV3PLUS_TSF_LOW); high = BWN_READ_4(mac, BWN_REV3PLUS_TSF_HIGH); *tsf = high; *tsf <<= 32; *tsf |= low; } static int bwn_dma_attach(struct bwn_mac *mac) { - struct bwn_dma *dma = &mac->mac_method.dma; - struct bwn_softc *sc = mac->mac_sc; - bus_addr_t lowaddr = 0; - int error; + struct bwn_dma *dma; + struct bwn_softc *sc; + struct bhnd_dma_translation *dt, dma_translation; + bhnd_addr_t addrext_req; + bus_dma_tag_t dmat; + bus_addr_t lowaddr; + u_int addrext_shift, addr_width; + int error; - if (siba_get_type(sc->sc_dev) == SIBA_TYPE_PCMCIA || bwn_usedma == 0) + dma = &mac->mac_method.dma; + sc = mac->mac_sc; + dt = NULL; + + if (sc->sc_quirks & BWN_QUIRK_NODMA) return (0); - KASSERT(siba_get_revid(sc->sc_dev) >= 5, ("%s: fail", __func__)); + KASSERT(bhnd_get_hwrev(sc->sc_dev) >= 5, ("%s: fail", __func__)); + /* Use the DMA engine's maximum host address width to determine the + * addrext constraints, and supported device address width. */ + switch (mac->mac_dmatype) { + case BHND_DMA_ADDR_30BIT: + /* 32-bit engine without addrext support */ + addrext_req = 0x0; + addrext_shift = 0; + + /* We can address the full 32-bit device address space */ + addr_width = BHND_DMA_ADDR_32BIT; + break; + + case BHND_DMA_ADDR_32BIT: + /* 32-bit engine with addrext support */ + addrext_req = BWN_DMA32_ADDREXT_MASK; + addrext_shift = BWN_DMA32_ADDREXT_SHIFT; + addr_width = BHND_DMA_ADDR_32BIT; + break; + + case BHND_DMA_ADDR_64BIT: + /* 64-bit engine with addrext support */ + addrext_req = BWN_DMA64_ADDREXT_MASK; + addrext_shift = BWN_DMA64_ADDREXT_SHIFT; + addr_width = BHND_DMA_ADDR_64BIT; + break; + + default: + device_printf(sc->sc_dev, "unsupported DMA address width: %d\n", + mac->mac_dmatype); + return (ENXIO); + } + + + /* Fetch our device->host DMA translation and tag */ + error = bhnd_get_dma_translation(sc->sc_dev, addr_width, 0, &dmat, + &dma_translation); + if (error) { + device_printf(sc->sc_dev, "error fetching DMA translation: " + "%d\n", error); + return (error); + } + + /* Verify that our DMA engine's addrext constraints are compatible with + * our DMA translation */ + if (addrext_req != 0x0 && + (dma_translation.addrext_mask & addrext_req) != addrext_req) + { + device_printf(sc->sc_dev, "bus addrext mask %#jx incompatible " + "with device addrext mask %#jx, disabling extended address " + "support\n", (uintmax_t)dma_translation.addrext_mask, + (uintmax_t)addrext_req); + + addrext_req = 0x0; + addrext_shift = 0; + } + + /* Apply our addrext translation constraint */ + dma_translation.addrext_mask = addrext_req; + + /* Initialize our DMA engine configuration */ mac->mac_flags |= BWN_MAC_FLAG_DMA; - dma->dmatype = bwn_dma_gettype(mac); - if (dma->dmatype == BWN_DMA_30BIT) - lowaddr = BWN_BUS_SPACE_MAXADDR_30BIT; - else if (dma->dmatype == BWN_DMA_32BIT) - lowaddr = BUS_SPACE_MAXADDR_32BIT; - else - lowaddr = BUS_SPACE_MAXADDR; + dma->addrext_shift = addrext_shift; + dma->translation = dma_translation; + dt = &dma->translation; + + /* Dermine our translation's maximum supported address */ + lowaddr = MIN((dt->addr_mask | dt->addrext_mask), BUS_SPACE_MAXADDR); + /* * Create top level DMA tag */ - error = bus_dma_tag_create(bus_get_dma_tag(sc->sc_dev), /* parent */ + error = bus_dma_tag_create(dmat, /* parent */ BWN_ALIGN, 0, /* alignment, bounds */ lowaddr, /* lowaddr */ BUS_SPACE_MAXADDR, /* highaddr */ NULL, NULL, /* filter, filterarg */ BUS_SPACE_MAXSIZE, /* maxsize */ BUS_SPACE_UNRESTRICTED, /* nsegments */ BUS_SPACE_MAXSIZE, /* maxsegsize */ 0, /* flags */ NULL, NULL, /* lockfunc, lockarg */ &dma->parent_dtag); if (error) { device_printf(sc->sc_dev, "can't create parent DMA tag\n"); return (error); } /* * Create TX/RX mbuf DMA tag */ error = bus_dma_tag_create(dma->parent_dtag, 1, 0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, MCLBYTES, 1, BUS_SPACE_MAXSIZE_32BIT, 0, NULL, NULL, &dma->rxbuf_dtag); if (error) { device_printf(sc->sc_dev, "can't create mbuf DMA tag\n"); goto fail0; } error = bus_dma_tag_create(dma->parent_dtag, 1, 0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, MCLBYTES, 1, BUS_SPACE_MAXSIZE_32BIT, 0, NULL, NULL, &dma->txbuf_dtag); if (error) { device_printf(sc->sc_dev, "can't create mbuf DMA tag\n"); goto fail1; } - dma->wme[WME_AC_BK] = bwn_dma_ringsetup(mac, 0, 1, dma->dmatype); + dma->wme[WME_AC_BK] = bwn_dma_ringsetup(mac, 0, 1); if (!dma->wme[WME_AC_BK]) goto fail2; - dma->wme[WME_AC_BE] = bwn_dma_ringsetup(mac, 1, 1, dma->dmatype); + dma->wme[WME_AC_BE] = bwn_dma_ringsetup(mac, 1, 1); if (!dma->wme[WME_AC_BE]) goto fail3; - dma->wme[WME_AC_VI] = bwn_dma_ringsetup(mac, 2, 1, dma->dmatype); + dma->wme[WME_AC_VI] = bwn_dma_ringsetup(mac, 2, 1); if (!dma->wme[WME_AC_VI]) goto fail4; - dma->wme[WME_AC_VO] = bwn_dma_ringsetup(mac, 3, 1, dma->dmatype); + dma->wme[WME_AC_VO] = bwn_dma_ringsetup(mac, 3, 1); if (!dma->wme[WME_AC_VO]) goto fail5; - dma->mcast = bwn_dma_ringsetup(mac, 4, 1, dma->dmatype); + dma->mcast = bwn_dma_ringsetup(mac, 4, 1); if (!dma->mcast) goto fail6; - dma->rx = bwn_dma_ringsetup(mac, 0, 0, dma->dmatype); + dma->rx = bwn_dma_ringsetup(mac, 0, 0); if (!dma->rx) goto fail7; return (error); fail7: bwn_dma_ringfree(&dma->mcast); fail6: bwn_dma_ringfree(&dma->wme[WME_AC_VO]); fail5: bwn_dma_ringfree(&dma->wme[WME_AC_VI]); fail4: bwn_dma_ringfree(&dma->wme[WME_AC_BE]); fail3: bwn_dma_ringfree(&dma->wme[WME_AC_BK]); fail2: bus_dma_tag_destroy(dma->txbuf_dtag); fail1: bus_dma_tag_destroy(dma->rxbuf_dtag); fail0: bus_dma_tag_destroy(dma->parent_dtag); return (error); } static struct bwn_dma_ring * bwn_dma_parse_cookie(struct bwn_mac *mac, const struct bwn_txstatus *status, uint16_t cookie, int *slot) { struct bwn_dma *dma = &mac->mac_method.dma; struct bwn_dma_ring *dr; struct bwn_softc *sc = mac->mac_sc; BWN_ASSERT_LOCKED(mac->mac_sc); switch (cookie & 0xf000) { case 0x1000: dr = dma->wme[WME_AC_BK]; break; case 0x2000: dr = dma->wme[WME_AC_BE]; break; case 0x3000: dr = dma->wme[WME_AC_VI]; break; case 0x4000: dr = dma->wme[WME_AC_VO]; break; case 0x5000: dr = dma->mcast; break; default: dr = NULL; KASSERT(0 == 1, ("invalid cookie value %d", cookie & 0xf000)); } *slot = (cookie & 0x0fff); if (*slot < 0 || *slot >= dr->dr_numslots) { /* * XXX FIXME: sometimes H/W returns TX DONE events duplicately * that it occurs events which have same H/W sequence numbers. * When it's occurred just prints a WARNING msgs and ignores. */ KASSERT(status->seq == dma->lastseq, ("%s:%d: fail", __func__, __LINE__)); device_printf(sc->sc_dev, "out of slot ranges (0 < %d < %d)\n", *slot, dr->dr_numslots); return (NULL); } dma->lastseq = status->seq; return (dr); } static void bwn_dma_stop(struct bwn_mac *mac) { struct bwn_dma *dma; if ((mac->mac_flags & BWN_MAC_FLAG_DMA) == 0) return; dma = &mac->mac_method.dma; bwn_dma_ringstop(&dma->rx); bwn_dma_ringstop(&dma->wme[WME_AC_BK]); bwn_dma_ringstop(&dma->wme[WME_AC_BE]); bwn_dma_ringstop(&dma->wme[WME_AC_VI]); bwn_dma_ringstop(&dma->wme[WME_AC_VO]); bwn_dma_ringstop(&dma->mcast); } static void bwn_dma_ringstop(struct bwn_dma_ring **dr) { if (dr == NULL) return; bwn_dma_cleanup(*dr); } static void bwn_pio_stop(struct bwn_mac *mac) { struct bwn_pio *pio; if (mac->mac_flags & BWN_MAC_FLAG_DMA) return; pio = &mac->mac_method.pio; bwn_destroy_queue_tx(&pio->mcast); bwn_destroy_queue_tx(&pio->wme[WME_AC_VO]); bwn_destroy_queue_tx(&pio->wme[WME_AC_VI]); bwn_destroy_queue_tx(&pio->wme[WME_AC_BE]); bwn_destroy_queue_tx(&pio->wme[WME_AC_BK]); } -static void +static int bwn_led_attach(struct bwn_mac *mac) { struct bwn_softc *sc = mac->mac_sc; const uint8_t *led_act = NULL; - uint16_t val[BWN_LED_MAX]; + int error; int i; sc->sc_led_idle = (2350 * hz) / 1000; sc->sc_led_blink = 1; for (i = 0; i < N(bwn_vendor_led_act); ++i) { - if (siba_get_pci_subvendor(sc->sc_dev) == + if (sc->sc_board_info.board_vendor == bwn_vendor_led_act[i].vid) { led_act = bwn_vendor_led_act[i].led_act; break; } } if (led_act == NULL) led_act = bwn_default_led_act; - val[0] = siba_sprom_get_gpio0(sc->sc_dev); - val[1] = siba_sprom_get_gpio1(sc->sc_dev); - val[2] = siba_sprom_get_gpio2(sc->sc_dev); - val[3] = siba_sprom_get_gpio3(sc->sc_dev); + _Static_assert(nitems(bwn_led_vars) == BWN_LED_MAX, + "invalid NVRAM variable name array"); for (i = 0; i < BWN_LED_MAX; ++i) { - struct bwn_led *led = &sc->sc_leds[i]; + struct bwn_led *led; + uint8_t val; - if (val[i] == 0xff) { + led = &sc->sc_leds[i]; + + KASSERT(i < nitems(bwn_led_vars), ("unknown LED index")); + error = bhnd_nvram_getvar_uint8(sc->sc_dev, bwn_led_vars[i], + &val); + if (error) { + if (error != ENOENT) { + device_printf(sc->sc_dev, "NVRAM variable %s " + "unreadable: %d", bwn_led_vars[i], error); + return (error); + } + + /* Not found; use default */ led->led_act = led_act[i]; } else { - if (val[i] & BWN_LED_ACT_LOW) + if (val & BWN_LED_ACT_LOW) led->led_flags |= BWN_LED_F_ACTLOW; - led->led_act = val[i] & BWN_LED_ACT_MASK; + led->led_act = val & BWN_LED_ACT_MASK; } led->led_mask = (1 << i); if (led->led_act == BWN_LED_ACT_BLINK_SLOW || led->led_act == BWN_LED_ACT_BLINK_POLL || led->led_act == BWN_LED_ACT_BLINK) { led->led_flags |= BWN_LED_F_BLINK; if (led->led_act == BWN_LED_ACT_BLINK_POLL) led->led_flags |= BWN_LED_F_POLLABLE; else if (led->led_act == BWN_LED_ACT_BLINK_SLOW) led->led_flags |= BWN_LED_F_SLOW; if (sc->sc_blink_led == NULL) { sc->sc_blink_led = led; if (led->led_flags & BWN_LED_F_SLOW) BWN_LED_SLOWDOWN(sc->sc_led_idle); } } DPRINTF(sc, BWN_DEBUG_LED, "%dth led, act %d, lowact %d\n", i, led->led_act, led->led_flags & BWN_LED_F_ACTLOW); } callout_init_mtx(&sc->sc_led_blink_ch, &sc->sc_mtx, 0); + + return (0); } static __inline uint16_t bwn_led_onoff(const struct bwn_led *led, uint16_t val, int on) { if (led->led_flags & BWN_LED_F_ACTLOW) on = !on; if (on) val |= led->led_mask; else val &= ~led->led_mask; return val; } static void bwn_led_newstate(struct bwn_mac *mac, enum ieee80211_state nstate) { struct bwn_softc *sc = mac->mac_sc; struct ieee80211com *ic = &sc->sc_ic; uint16_t val; int i; if (nstate == IEEE80211_S_INIT) { callout_stop(&sc->sc_led_blink_ch); sc->sc_led_blinking = 0; } if ((sc->sc_flags & BWN_FLAG_RUNNING) == 0) return; val = BWN_READ_2(mac, BWN_GPIO_CONTROL); for (i = 0; i < BWN_LED_MAX; ++i) { struct bwn_led *led = &sc->sc_leds[i]; int on; if (led->led_act == BWN_LED_ACT_UNKN || led->led_act == BWN_LED_ACT_NULL) continue; if ((led->led_flags & BWN_LED_F_BLINK) && nstate != IEEE80211_S_INIT) continue; switch (led->led_act) { case BWN_LED_ACT_ON: /* Always on */ on = 1; break; case BWN_LED_ACT_OFF: /* Always off */ case BWN_LED_ACT_5GHZ: /* TODO: 11A */ on = 0; break; default: on = 1; switch (nstate) { case IEEE80211_S_INIT: on = 0; break; case IEEE80211_S_RUN: if (led->led_act == BWN_LED_ACT_11G && ic->ic_curmode != IEEE80211_MODE_11G) on = 0; break; default: if (led->led_act == BWN_LED_ACT_ASSOC) on = 0; break; } break; } val = bwn_led_onoff(led, val, on); } BWN_WRITE_2(mac, BWN_GPIO_CONTROL, val); } static void bwn_led_event(struct bwn_mac *mac, int event) { struct bwn_softc *sc = mac->mac_sc; struct bwn_led *led = sc->sc_blink_led; int rate; if (event == BWN_LED_EVENT_POLL) { if ((led->led_flags & BWN_LED_F_POLLABLE) == 0) return; if (ticks - sc->sc_led_ticks < sc->sc_led_idle) return; } sc->sc_led_ticks = ticks; if (sc->sc_led_blinking) return; switch (event) { case BWN_LED_EVENT_RX: rate = sc->sc_rx_rate; break; case BWN_LED_EVENT_TX: rate = sc->sc_tx_rate; break; case BWN_LED_EVENT_POLL: rate = 0; break; default: panic("unknown LED event %d\n", event); break; } bwn_led_blink_start(mac, bwn_led_duration[rate].on_dur, bwn_led_duration[rate].off_dur); } static void bwn_led_blink_start(struct bwn_mac *mac, int on_dur, int off_dur) { struct bwn_softc *sc = mac->mac_sc; struct bwn_led *led = sc->sc_blink_led; uint16_t val; val = BWN_READ_2(mac, BWN_GPIO_CONTROL); val = bwn_led_onoff(led, val, 1); BWN_WRITE_2(mac, BWN_GPIO_CONTROL, val); if (led->led_flags & BWN_LED_F_SLOW) { BWN_LED_SLOWDOWN(on_dur); BWN_LED_SLOWDOWN(off_dur); } sc->sc_led_blinking = 1; sc->sc_led_blink_offdur = off_dur; callout_reset(&sc->sc_led_blink_ch, on_dur, bwn_led_blink_next, mac); } static void bwn_led_blink_next(void *arg) { struct bwn_mac *mac = arg; struct bwn_softc *sc = mac->mac_sc; uint16_t val; val = BWN_READ_2(mac, BWN_GPIO_CONTROL); val = bwn_led_onoff(sc->sc_blink_led, val, 0); BWN_WRITE_2(mac, BWN_GPIO_CONTROL, val); callout_reset(&sc->sc_led_blink_ch, sc->sc_led_blink_offdur, bwn_led_blink_end, mac); } static void bwn_led_blink_end(void *arg) { struct bwn_mac *mac = arg; struct bwn_softc *sc = mac->mac_sc; sc->sc_led_blinking = 0; } static int bwn_suspend(device_t dev) { struct bwn_softc *sc = device_get_softc(dev); BWN_LOCK(sc); bwn_stop(sc); BWN_UNLOCK(sc); return (0); } static int bwn_resume(device_t dev) { struct bwn_softc *sc = device_get_softc(dev); int error = EDOOFUS; BWN_LOCK(sc); if (sc->sc_ic.ic_nrunning > 0) error = bwn_init(sc); BWN_UNLOCK(sc); if (error == 0) ieee80211_start_all(&sc->sc_ic); return (0); } static void bwn_rfswitch(void *arg) { struct bwn_softc *sc = arg; struct bwn_mac *mac = sc->sc_curmac; int cur = 0, prev = 0; KASSERT(mac->mac_status >= BWN_MAC_STATUS_STARTED, ("%s: invalid MAC status %d", __func__, mac->mac_status)); if (mac->mac_phy.rev >= 3 || mac->mac_phy.type == BWN_PHYTYPE_LP || mac->mac_phy.type == BWN_PHYTYPE_N) { if (!(BWN_READ_4(mac, BWN_RF_HWENABLED_HI) & BWN_RF_HWENABLED_HI_MASK)) cur = 1; } else { if (BWN_READ_2(mac, BWN_RF_HWENABLED_LO) & BWN_RF_HWENABLED_LO_MASK) cur = 1; } if (mac->mac_flags & BWN_MAC_FLAG_RADIO_ON) prev = 1; DPRINTF(sc, BWN_DEBUG_RESET, "%s: called; cur=%d, prev=%d\n", __func__, cur, prev); if (cur != prev) { if (cur) mac->mac_flags |= BWN_MAC_FLAG_RADIO_ON; else mac->mac_flags &= ~BWN_MAC_FLAG_RADIO_ON; device_printf(sc->sc_dev, "status of RF switch is changed to %s\n", cur ? "ON" : "OFF"); if (cur != mac->mac_phy.rf_on) { if (cur) bwn_rf_turnon(mac); else bwn_rf_turnoff(mac); } } callout_schedule(&sc->sc_rfswitch_ch, hz); } static void bwn_sysctl_node(struct bwn_softc *sc) { device_t dev = sc->sc_dev; struct bwn_mac *mac; struct bwn_stats *stats; /* XXX assume that count of MAC is only 1. */ if ((mac = sc->sc_curmac) == NULL) return; stats = &mac->mac_stats; SYSCTL_ADD_INT(device_get_sysctl_ctx(dev), SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), OID_AUTO, "linknoise", CTLFLAG_RW, &stats->rts, 0, "Noise level"); SYSCTL_ADD_INT(device_get_sysctl_ctx(dev), SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), OID_AUTO, "rts", CTLFLAG_RW, &stats->rts, 0, "RTS"); SYSCTL_ADD_INT(device_get_sysctl_ctx(dev), SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), OID_AUTO, "rtsfail", CTLFLAG_RW, &stats->rtsfail, 0, "RTS failed to send"); #ifdef BWN_DEBUG SYSCTL_ADD_UINT(device_get_sysctl_ctx(dev), SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), OID_AUTO, "debug", CTLFLAG_RW, &sc->sc_debug, 0, "Debug flags"); #endif } static device_method_t bwn_methods[] = { /* Device interface */ DEVMETHOD(device_probe, bwn_probe), DEVMETHOD(device_attach, bwn_attach), DEVMETHOD(device_detach, bwn_detach), DEVMETHOD(device_suspend, bwn_suspend), DEVMETHOD(device_resume, bwn_resume), DEVMETHOD_END }; -driver_t bwn_driver = { +static driver_t bwn_driver = { "bwn", bwn_methods, sizeof(struct bwn_softc) }; static devclass_t bwn_devclass; -DRIVER_MODULE(bwn, siba_bwn, bwn_driver, bwn_devclass, 0, 0); -MODULE_DEPEND(bwn, bwn_pci, 1, 1, 1); -MODULE_DEPEND(bwn, siba_bwn, 1, 1, 1); +DRIVER_MODULE(bwn, bhnd, bwn_driver, bwn_devclass, 0, 0); +MODULE_DEPEND(bwn, bhnd, 1, 1, 1); MODULE_DEPEND(bwn, gpiobus, 1, 1, 1); MODULE_DEPEND(bwn, wlan, 1, 1, 1); /* 802.11 media layer */ MODULE_DEPEND(bwn, firmware, 1, 1, 1); /* firmware support */ MODULE_DEPEND(bwn, wlan_amrr, 1, 1, 1); MODULE_VERSION(bwn, 1); Index: head/sys/dev/bwn/if_bwn_misc.h =================================================================== --- head/sys/dev/bwn/if_bwn_misc.h (revision 328911) +++ head/sys/dev/bwn/if_bwn_misc.h (revision 328912) @@ -1,67 +1,68 @@ /*- * Copyright (c) 2009-2010 Weongyo Jeong * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer, * without modification. * 2. Redistributions in binary form must reproduce at minimum a disclaimer * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any * redistribution must be conditioned upon including a substantially * similar Disclaimer requirement for further binary redistribution. * * NO WARRANTY * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF * THE POSSIBILITY OF SUCH DAMAGES. * * $FreeBSD$ */ #ifndef __IF_BWN_MISC_H__ #define __IF_BWN_MISC_H__ /* * These are the functions used by the PHY code. * * They currently live in the driver itself; at least until they * are broken out into smaller pieces. */ struct bwn_mac; +extern int bwn_gpio_control(struct bwn_mac *, uint32_t); + extern uint64_t bwn_hf_read(struct bwn_mac *); extern void bwn_hf_write(struct bwn_mac *, uint64_t); extern void bwn_dummy_transmission(struct bwn_mac *mac, int ofdm, int paon); extern void bwn_ram_write(struct bwn_mac *, uint16_t, uint32_t); extern void bwn_mac_suspend(struct bwn_mac *); extern void bwn_mac_enable(struct bwn_mac *); extern int bwn_switch_channel(struct bwn_mac *, int); extern uint16_t bwn_shm_read_2(struct bwn_mac *, uint16_t, uint16_t); extern void bwn_shm_write_2(struct bwn_mac *, uint16_t, uint16_t, uint16_t); extern uint32_t bwn_shm_read_4(struct bwn_mac *, uint16_t, uint16_t); extern void bwn_shm_write_4(struct bwn_mac *, uint16_t, uint16_t, uint32_t); -/* This is only for SIBA core */ -extern void bwn_reset_core(struct bwn_mac *, int g_mode); +extern int bwn_reset_core(struct bwn_mac *, int g_mode); extern void bwn_psctl(struct bwn_mac *, uint32_t); #endif Index: head/sys/dev/bwn/if_bwn_pci.c =================================================================== --- head/sys/dev/bwn/if_bwn_pci.c (revision 328911) +++ head/sys/dev/bwn/if_bwn_pci.c (revision 328912) @@ -1,317 +1,306 @@ /*- * SPDX-License-Identifier: BSD-2-Clause-FreeBSD * * Copyright (c) 2015-2016 Landon Fuller * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. */ #include __FBSDID("$FreeBSD$"); #include "opt_bwn.h" #include "opt_wlan.h" #include #include #include #include #include #include #include #include #include #include #include "bhndb_bus_if.h" #include "if_bwn_pcivar.h" /* If non-zero, enable attachment of BWN_QUIRK_UNTESTED devices */ static int attach_untested = 0; TUNABLE_INT("hw.bwn_pci.attach_untested", &attach_untested); -/* If non-zero, probe at a higher priority than the stable if_bwn driver. */ -static int prefer_new_driver = 1; -TUNABLE_INT("hw.bwn_pci.preferred", &prefer_new_driver); - /* SIBA Devices */ static const struct bwn_pci_device siba_devices[] = { BWN_BCM_DEV(BCM4306_D11A, "BCM4306 802.11a", BWN_QUIRK_WLAN_DUALCORE|BWN_QUIRK_SOFTMODEM_UNPOPULATED), BWN_BCM_DEV(BCM4306_D11G, "BCM4306 802.11b/g", BWN_QUIRK_SOFTMODEM_UNPOPULATED), BWN_BCM_DEV(BCM4306_D11G_ID2, "BCM4306 802.11b/g", BWN_QUIRK_SOFTMODEM_UNPOPULATED), BWN_BCM_DEV(BCM4306_D11DUAL, "BCM4306 802.11a/b/g", BWN_QUIRK_SOFTMODEM_UNPOPULATED), BWN_BCM_DEV(BCM4307, "BCM4307 802.11b", 0), BWN_BCM_DEV(BCM4311_D11G, "BCM4311 802.11b/g", 0), BWN_BCM_DEV(BCM4311_D11DUAL, "BCM4311 802.11a/b/g", 0), BWN_BCM_DEV(BCM4311_D11A, "BCM4311 802.11a", BWN_QUIRK_UNTESTED|BWN_QUIRK_WLAN_DUALCORE), BWN_BCM_DEV(BCM4318_D11G, "BCM4318 802.11b/g", 0), BWN_BCM_DEV(BCM4318_D11DUAL, "BCM4318 802.11a/b/g", 0), BWN_BCM_DEV(BCM4318_D11A, "BCM4318 802.11a", BWN_QUIRK_UNTESTED|BWN_QUIRK_WLAN_DUALCORE), BWN_BCM_DEV(BCM4321_D11N, "BCM4321 802.11n Dual-Band", BWN_QUIRK_USBH_UNPOPULATED), BWN_BCM_DEV(BCM4321_D11N2G, "BCM4321 802.11n 2GHz", BWN_QUIRK_USBH_UNPOPULATED), BWN_BCM_DEV(BCM4321_D11N5G, "BCM4321 802.11n 5GHz", BWN_QUIRK_UNTESTED|BWN_QUIRK_USBH_UNPOPULATED), BWN_BCM_DEV(BCM4322_D11N, "BCM4322 802.11n Dual-Band", 0), BWN_BCM_DEV(BCM4322_D11N2G, "BCM4322 802.11n 2GHz", BWN_QUIRK_UNTESTED), BWN_BCM_DEV(BCM4322_D11N5G, "BCM4322 802.11n 5GHz", BWN_QUIRK_UNTESTED), BWN_BCM_DEV(BCM4328_D11G, "BCM4328/4312 802.11g", 0), { 0, 0, NULL, 0 } }; /** BCMA Devices */ static const struct bwn_pci_device bcma_devices[] = { BWN_BCM_DEV(BCM4331_D11N, "BCM4331 802.11n Dual-Band", 0), BWN_BCM_DEV(BCM4331_D11N2G, "BCM4331 802.11n 2GHz", 0), BWN_BCM_DEV(BCM4331_D11N5G, "BCM4331 802.11n 5GHz", 0), BWN_BCM_DEV(BCM43224_D11N, "BCM43224 802.11n Dual-Band", 0), BWN_BCM_DEV(BCM43224_D11N_ID_VEN1, "BCM43224 802.11n Dual-Band",0), BWN_BCM_DEV(BCM43225_D11N2G, "BCM43225 802.11n 2GHz", 0), { 0, 0, NULL, 0} }; /** Device configuration table */ static const struct bwn_pci_devcfg bwn_pci_devcfgs[] = { /* SIBA devices */ { .bridge_hwcfg = &bhndb_pci_siba_generic_hwcfg, .bridge_hwtable = bhndb_pci_generic_hw_table, .bridge_hwprio = bhndb_siba_priority_table, .devices = siba_devices }, /* BCMA devices */ { .bridge_hwcfg = &bhndb_pci_bcma_generic_hwcfg, .bridge_hwtable = bhndb_pci_generic_hw_table, .bridge_hwprio = bhndb_bcma_priority_table, .devices = bcma_devices }, { NULL, NULL, NULL } }; /** Search the device configuration table for an entry matching @p dev. */ static int bwn_pci_find_devcfg(device_t dev, const struct bwn_pci_devcfg **cfg, const struct bwn_pci_device **device) { const struct bwn_pci_devcfg *dvc; const struct bwn_pci_device *dv; for (dvc = bwn_pci_devcfgs; dvc->devices != NULL; dvc++) { for (dv = dvc->devices; dv->device != 0; dv++) { if (pci_get_vendor(dev) == dv->vendor && pci_get_device(dev) == dv->device) { if (cfg != NULL) *cfg = dvc; if (device != NULL) *device = dv; return (0); } } } return (ENOENT); } static int bwn_pci_probe(device_t dev) { const struct bwn_pci_device *ident; if (bwn_pci_find_devcfg(dev, NULL, &ident)) return (ENXIO); /* Skip untested devices */ if (ident->quirks & BWN_QUIRK_UNTESTED && !attach_untested) return (ENXIO); device_set_desc(dev, ident->desc); - - /* Until this driver is complete, require explicit opt-in before - * superceding if_bwn/siba_bwn. */ - if (prefer_new_driver) - return (BUS_PROBE_DEFAULT+1); - else - return (BUS_PROBE_LOW_PRIORITY); - - // return (BUS_PROBE_DEFAULT); + return (BUS_PROBE_DEFAULT); } static int bwn_pci_attach(device_t dev) { struct bwn_pci_softc *sc; const struct bwn_pci_device *ident; int error; sc = device_get_softc(dev); sc->dev = dev; /* Find our hardware config */ if (bwn_pci_find_devcfg(dev, &sc->devcfg, &ident)) return (ENXIO); /* Save quirk flags */ sc->quirks = ident->quirks; /* Attach bridge device */ if ((error = bhndb_attach_bridge(dev, &sc->bhndb_dev, -1))) return (ENXIO); /* Success */ return (0); } static int bwn_pci_detach(device_t dev) { int error; if ((error = bus_generic_detach(dev))) return (error); return (device_delete_children(dev)); } static void bwn_pci_probe_nomatch(device_t dev, device_t child) { const char *name; name = device_get_name(child); if (name == NULL) name = "unknown device"; device_printf(dev, "<%s> (no driver attached)\n", name); } static const struct bhndb_hwcfg * bwn_pci_get_generic_hwcfg(device_t dev, device_t child) { struct bwn_pci_softc *sc = device_get_softc(dev); return (sc->devcfg->bridge_hwcfg); } static const struct bhndb_hw * bwn_pci_get_bhndb_hwtable(device_t dev, device_t child) { struct bwn_pci_softc *sc = device_get_softc(dev); return (sc->devcfg->bridge_hwtable); } static const struct bhndb_hw_priority * bwn_pci_get_bhndb_hwprio(device_t dev, device_t child) { struct bwn_pci_softc *sc = device_get_softc(dev); return (sc->devcfg->bridge_hwprio); } static bool bwn_pci_is_core_disabled(device_t dev, device_t child, struct bhnd_core_info *core) { struct bwn_pci_softc *sc; sc = device_get_softc(dev); switch (bhnd_core_class(core)) { case BHND_DEVCLASS_WLAN: if (core->unit > 0 && !(sc->quirks & BWN_QUIRK_WLAN_DUALCORE)) return (true); return (false); case BHND_DEVCLASS_ENET: case BHND_DEVCLASS_ENET_MAC: case BHND_DEVCLASS_ENET_PHY: return ((sc->quirks & BWN_QUIRK_ENET_HW_UNPOPULATED) != 0); case BHND_DEVCLASS_USB_HOST: return ((sc->quirks & BWN_QUIRK_USBH_UNPOPULATED) != 0); case BHND_DEVCLASS_SOFTMODEM: return ((sc->quirks & BWN_QUIRK_SOFTMODEM_UNPOPULATED) != 0); default: return (false); } } static device_method_t bwn_pci_methods[] = { /* Device interface */ DEVMETHOD(device_probe, bwn_pci_probe), DEVMETHOD(device_attach, bwn_pci_attach), DEVMETHOD(device_detach, bwn_pci_detach), DEVMETHOD(device_shutdown, bus_generic_shutdown), DEVMETHOD(device_suspend, bus_generic_suspend), DEVMETHOD(device_resume, bus_generic_resume), /* Bus interface */ DEVMETHOD(bus_probe_nomatch, bwn_pci_probe_nomatch), /* BHNDB_BUS Interface */ DEVMETHOD(bhndb_bus_get_generic_hwcfg, bwn_pci_get_generic_hwcfg), DEVMETHOD(bhndb_bus_get_hardware_table, bwn_pci_get_bhndb_hwtable), DEVMETHOD(bhndb_bus_get_hardware_prio, bwn_pci_get_bhndb_hwprio), DEVMETHOD(bhndb_bus_is_core_disabled, bwn_pci_is_core_disabled), DEVMETHOD_END }; static devclass_t bwn_pci_devclass; DEFINE_CLASS_0(bwn_pci, bwn_pci_driver, bwn_pci_methods, sizeof(struct bwn_pci_softc)); DRIVER_MODULE_ORDERED(bwn_pci, pci, bwn_pci_driver, bwn_pci_devclass, NULL, NULL, SI_ORDER_ANY); DRIVER_MODULE(bhndb, bwn_pci, bhndb_pci_driver, bhndb_devclass, NULL, NULL); +MODULE_DEPEND(bwn_pci, bwn, 1, 1, 1); MODULE_DEPEND(bwn_pci, bhnd, 1, 1, 1); MODULE_DEPEND(bwn_pci, bhndb, 1, 1, 1); MODULE_DEPEND(bwn_pci, bhndb_pci, 1, 1, 1); MODULE_DEPEND(bwn_pci, bcma_bhndb, 1, 1, 1); MODULE_DEPEND(bwn_pci, siba_bhndb, 1, 1, 1); MODULE_VERSION(bwn_pci, 1); Index: head/sys/dev/bwn/if_bwn_phy_common.c =================================================================== --- head/sys/dev/bwn/if_bwn_phy_common.c (revision 328911) +++ head/sys/dev/bwn/if_bwn_phy_common.c (revision 328912) @@ -1,199 +1,237 @@ /*- * Copyright (c) 2009-2010 Weongyo Jeong * Copyright (c) 2016 Adrian Chadd * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer, * without modification. * 2. Redistributions in binary form must reproduce at minimum a disclaimer * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any * redistribution must be conditioned upon including a substantially * similar Disclaimer requirement for further binary redistribution. * * NO WARRANTY * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF * THE POSSIBILITY OF SUCH DAMAGES. */ #include __FBSDID("$FreeBSD$"); #include "opt_bwn.h" #include "opt_wlan.h" /* * The Broadcom Wireless LAN controller driver. */ #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include -#include +#include +#include +#include +#include + #include #include -#include #include #include #include void -bwn_mac_switch_freq(struct bwn_mac *mac, int spurmode) +bwn_mac_switch_freq(struct bwn_mac *mac, bhnd_pmu_spuravoid spurmode) { struct bwn_softc *sc = mac->mac_sc; - uint16_t chip_id = siba_get_chipid(sc->sc_dev); + uint16_t chip_id = sc->sc_cid.chip_id; - if (chip_id == BCMA_CHIP_ID_BCM4331) { + if (chip_id == BHND_CHIPID_BCM4331) { switch (spurmode) { - case 2: /* 168 Mhz: 2^26/168 = 0x61862 */ + case BHND_PMU_SPURAVOID_M2: /* 168 Mhz: 2^26/168 = 0x61862 */ BWN_WRITE_2(mac, BWN_TSF_CLK_FRAC_LOW, 0x1862); BWN_WRITE_2(mac, BWN_TSF_CLK_FRAC_HIGH, 0x6); break; - case 1: /* 164 Mhz: 2^26/164 = 0x63e70 */ + case BHND_PMU_SPURAVOID_M1: /* 164 Mhz: 2^26/164 = 0x63e70 */ BWN_WRITE_2(mac, BWN_TSF_CLK_FRAC_LOW, 0x3e70); BWN_WRITE_2(mac, BWN_TSF_CLK_FRAC_HIGH, 0x6); break; - default: /* 160 Mhz: 2^26/160 = 0x66666 */ + case BHND_PMU_SPURAVOID_NONE: /* 160 Mhz: 2^26/160 = 0x66666 */ BWN_WRITE_2(mac, BWN_TSF_CLK_FRAC_LOW, 0x6666); BWN_WRITE_2(mac, BWN_TSF_CLK_FRAC_HIGH, 0x6); break; } - } else if (chip_id == BCMA_CHIP_ID_BCM43131 || - chip_id == BCMA_CHIP_ID_BCM43217 || - chip_id == BCMA_CHIP_ID_BCM43222 || - chip_id == BCMA_CHIP_ID_BCM43224 || - chip_id == BCMA_CHIP_ID_BCM43225 || - chip_id == BCMA_CHIP_ID_BCM43227 || - chip_id == BCMA_CHIP_ID_BCM43228) { + } else if (chip_id == BHND_CHIPID_BCM43131 || + chip_id == BHND_CHIPID_BCM43217 || + chip_id == BHND_CHIPID_BCM43222 || + chip_id == BHND_CHIPID_BCM43224 || + chip_id == BHND_CHIPID_BCM43225 || + chip_id == BHND_CHIPID_BCM43227 || + chip_id == BHND_CHIPID_BCM43228) { switch (spurmode) { - case 2: /* 126 Mhz */ + case BHND_PMU_SPURAVOID_M2: /* 126 Mhz */ BWN_WRITE_2(mac, BWN_TSF_CLK_FRAC_LOW, 0x2082); BWN_WRITE_2(mac, BWN_TSF_CLK_FRAC_HIGH, 0x8); break; - case 1: /* 123 Mhz */ + case BHND_PMU_SPURAVOID_M1: /* 123 Mhz */ BWN_WRITE_2(mac, BWN_TSF_CLK_FRAC_LOW, 0x5341); BWN_WRITE_2(mac, BWN_TSF_CLK_FRAC_HIGH, 0x8); break; - default: /* 120 Mhz */ + case BHND_PMU_SPURAVOID_NONE: /* 120 Mhz */ BWN_WRITE_2(mac, BWN_TSF_CLK_FRAC_LOW, 0x8889); BWN_WRITE_2(mac, BWN_TSF_CLK_FRAC_HIGH, 0x8); break; } } else if (mac->mac_phy.type == BWN_PHYTYPE_LCN) { switch (spurmode) { - case 1: /* 82 Mhz */ + case BHND_PMU_SPURAVOID_M2: + device_printf(sc->sc_dev, "invalid spuravoid mode: " + "%d\n", spurmode); + break; + case BHND_PMU_SPURAVOID_M1: /* 82 Mhz */ BWN_WRITE_2(mac, BWN_TSF_CLK_FRAC_LOW, 0x7CE0); BWN_WRITE_2(mac, BWN_TSF_CLK_FRAC_HIGH, 0xC); break; - default: /* 80 Mhz */ + case BHND_PMU_SPURAVOID_NONE: /* 80 Mhz */ BWN_WRITE_2(mac, BWN_TSF_CLK_FRAC_LOW, 0xCCCD); BWN_WRITE_2(mac, BWN_TSF_CLK_FRAC_HIGH, 0xC); break; } } } /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/BmacPhyClkFgc */ -void +int bwn_phy_force_clock(struct bwn_mac *mac, int force) { - struct bwn_softc *sc = mac->mac_sc; - uint32_t tmp; + struct bwn_softc *sc; + uint32_t val, mask; + int error; + sc = mac->mac_sc; + /* XXX Only for N, HT and AC PHYs */ + mask = BHND_IOCTL_CLK_FORCE; + if (force) { + val = BHND_IOCTL_CLK_FORCE; + } else { + val = 0; + } - tmp = siba_read_4(sc->sc_dev, SIBA_TGSLOW); - if (force) - tmp |= SIBA_TGSLOW_FGC; - else - tmp &= ~SIBA_TGSLOW_FGC; - siba_write_4(sc->sc_dev, SIBA_TGSLOW, tmp); + if ((error = bhnd_write_ioctl(sc->sc_dev, val, mask))) { + device_printf(sc->sc_dev, "failed to set CLK_FORCE ioctl flag: " + "%d\n", error); + return (error); + } + + return (0); } int bwn_radio_wait_value(struct bwn_mac *mac, uint16_t offset, uint16_t mask, uint16_t value, int delay, int timeout) { uint16_t val; int i; for (i = 0; i < timeout; i += delay) { val = BWN_RF_READ(mac, offset); if ((val & mask) == value) return (1); DELAY(delay); } return (0); } -void +int bwn_mac_phy_clock_set(struct bwn_mac *mac, int enabled) { - struct bwn_softc *sc = mac->mac_sc; - uint32_t val; + struct bwn_softc *sc; + uint32_t val, mask; + int error; - val = siba_read_4(sc->sc_dev, SIBA_TGSLOW); - if (enabled) - val |= BWN_TGSLOW_MACPHYCLKEN; - else - val &= ~BWN_TGSLOW_MACPHYCLKEN; - siba_write_4(sc->sc_dev, SIBA_TGSLOW, val); + sc = mac->mac_sc; + + mask = BWN_IOCTL_MACPHYCLKEN; + if (enabled) { + val = BWN_IOCTL_MACPHYCLKEN; + } else { + val = 0; + } + + if ((error = bhnd_write_ioctl(sc->sc_dev, val, mask))) { + device_printf(sc->sc_dev, "failed to set MACPHYCLKEN ioctl " + "flag: %d\n", error); + return (error); + } + + return (0); } /* http://bcm-v4.sipsolutions.net/802.11/PHY/BmacCorePllReset */ -void +int bwn_wireless_core_phy_pll_reset(struct bwn_mac *mac) { - struct bwn_softc *sc = mac->mac_sc; + struct bwn_softc *sc; + uint32_t pll_flag; - siba_cc_write32(sc->sc_dev, SIBA_CC_CHIPCTL_ADDR, 0); - siba_cc_mask32(sc->sc_dev, SIBA_CC_CHIPCTL_DATA, ~0x4); - siba_cc_set32(sc->sc_dev, SIBA_CC_CHIPCTL_DATA, 0x4); - siba_cc_mask32(sc->sc_dev, SIBA_CC_CHIPCTL_DATA, ~0x4); + sc = mac->mac_sc; + + if (sc->sc_pmu == NULL) { + device_printf(sc->sc_dev, "PMU device not found\n"); + return (ENXIO); + } + + pll_flag = 0x4; + bhnd_pmu_write_chipctrl(sc->sc_pmu, 0x0, 0x0, pll_flag); + bhnd_pmu_write_chipctrl(sc->sc_pmu, 0x0, pll_flag, pll_flag); + bhnd_pmu_write_chipctrl(sc->sc_pmu, 0x0, 0x0, pll_flag); + + return (0); } Index: head/sys/dev/bwn/if_bwn_phy_common.h =================================================================== --- head/sys/dev/bwn/if_bwn_phy_common.h (revision 328911) +++ head/sys/dev/bwn/if_bwn_phy_common.h (revision 328912) @@ -1,41 +1,42 @@ /*- * Copyright (c) 2016 Adrian Chadd . * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer, * without modification. * 2. Redistributions in binary form must reproduce at minimum a disclaimer * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any * redistribution must be conditioned upon including a substantially * similar Disclaimer requirement for further binary redistribution. * * NO WARRANTY * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF * THE POSSIBILITY OF SUCH DAMAGES. * * $FreeBSD$ */ #ifndef __PHY_COMMON_H__ #define __PHY_COMMON_H__ -extern void bwn_mac_switch_freq(struct bwn_mac *mac, int spurmode); -extern void bwn_phy_force_clock(struct bwn_mac *mac, int force); +extern void bwn_mac_switch_freq(struct bwn_mac *mac, + bhnd_pmu_spuravoid spurmode); +extern int bwn_phy_force_clock(struct bwn_mac *mac, int force); extern int bwn_radio_wait_value(struct bwn_mac *mac, uint16_t offset, uint16_t mask, uint16_t value, int delay, int timeout); -extern void bwn_mac_phy_clock_set(struct bwn_mac *mac, int enabled); -extern void bwn_wireless_core_phy_pll_reset(struct bwn_mac *mac); +extern int bwn_mac_phy_clock_set(struct bwn_mac *mac, int enabled); +extern int bwn_wireless_core_phy_pll_reset(struct bwn_mac *mac); #endif /* __PHY_COMMON_H__ */ Index: head/sys/dev/bwn/if_bwn_phy_g.c =================================================================== --- head/sys/dev/bwn/if_bwn_phy_g.c (revision 328911) +++ head/sys/dev/bwn/if_bwn_phy_g.c (revision 328912) @@ -1,3602 +1,3627 @@ /*- * Copyright (c) 2009-2010 Weongyo Jeong * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer, * without modification. * 2. Redistributions in binary form must reproduce at minimum a disclaimer * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any * redistribution must be conditioned upon including a substantially * similar Disclaimer requirement for further binary redistribution. * * NO WARRANTY * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF * THE POSSIBILITY OF SUCH DAMAGES. */ #include __FBSDID("$FreeBSD$"); #include "opt_bwn.h" #include "opt_wlan.h" /* * The Broadcom Wireless LAN controller driver. */ #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include -#include - #include #include #include #include #include +#include "bhnd_nvram_map.h" + static void bwn_phy_g_init_sub(struct bwn_mac *); static uint8_t bwn_has_hwpctl(struct bwn_mac *); static void bwn_phy_init_b5(struct bwn_mac *); static void bwn_phy_init_b6(struct bwn_mac *); static void bwn_phy_init_a(struct bwn_mac *); static void bwn_loopback_calcgain(struct bwn_mac *); static uint16_t bwn_rf_init_bcm2050(struct bwn_mac *); static void bwn_lo_g_init(struct bwn_mac *); static void bwn_lo_g_adjust(struct bwn_mac *); static void bwn_lo_get_powervector(struct bwn_mac *); static struct bwn_lo_calib *bwn_lo_calibset(struct bwn_mac *, const struct bwn_bbatt *, const struct bwn_rfatt *); static void bwn_lo_write(struct bwn_mac *, struct bwn_loctl *); static void bwn_phy_hwpctl_init(struct bwn_mac *); static void bwn_phy_g_switch_chan(struct bwn_mac *, int, uint8_t); static void bwn_phy_g_set_txpwr_sub(struct bwn_mac *, const struct bwn_bbatt *, const struct bwn_rfatt *, uint8_t); static void bwn_phy_g_set_bbatt(struct bwn_mac *, uint16_t); static uint16_t bwn_rf_2050_rfoverval(struct bwn_mac *, uint16_t, uint32_t); static void bwn_spu_workaround(struct bwn_mac *, uint8_t); static void bwn_wa_init(struct bwn_mac *); static void bwn_ofdmtab_write_2(struct bwn_mac *, uint16_t, uint16_t, uint16_t); static void bwn_ofdmtab_write_4(struct bwn_mac *, uint16_t, uint16_t, uint32_t); static void bwn_gtab_write(struct bwn_mac *, uint16_t, uint16_t, uint16_t); static int16_t bwn_nrssi_read(struct bwn_mac *, uint16_t); static void bwn_nrssi_offset(struct bwn_mac *); static void bwn_nrssi_threshold(struct bwn_mac *); static void bwn_nrssi_slope_11g(struct bwn_mac *); static void bwn_set_all_gains(struct bwn_mac *, int16_t, int16_t, int16_t); static void bwn_set_original_gains(struct bwn_mac *); static void bwn_hwpctl_early_init(struct bwn_mac *); static void bwn_hwpctl_init_gphy(struct bwn_mac *); static uint16_t bwn_phy_g_chan2freq(uint8_t); static void bwn_phy_g_dc_lookup_init(struct bwn_mac *, uint8_t); /* Stuff we need */ static uint16_t bwn_phy_g_txctl(struct bwn_mac *mac); static int bwn_phy_shm_tssi_read(struct bwn_mac *mac, uint16_t shm_offset); static void bwn_phy_g_setatt(struct bwn_mac *mac, int *bbattp, int *rfattp); static void bwn_phy_lock(struct bwn_mac *mac); static void bwn_phy_unlock(struct bwn_mac *mac); static void bwn_rf_lock(struct bwn_mac *mac); static void bwn_rf_unlock(struct bwn_mac *mac); static const uint16_t bwn_tab_noise_g1[] = BWN_TAB_NOISE_G1; static const uint16_t bwn_tab_noise_g2[] = BWN_TAB_NOISE_G2; static const uint16_t bwn_tab_noisescale_g1[] = BWN_TAB_NOISESCALE_G1; static const uint16_t bwn_tab_noisescale_g2[] = BWN_TAB_NOISESCALE_G2; static const uint16_t bwn_tab_noisescale_g3[] = BWN_TAB_NOISESCALE_G3; const uint8_t bwn_bitrev_table[256] = BWN_BITREV_TABLE; static uint8_t bwn_has_hwpctl(struct bwn_mac *mac) { if (mac->mac_phy.hwpctl == 0 || mac->mac_phy.use_hwpctl == NULL) return (0); return (mac->mac_phy.use_hwpctl(mac)); } int bwn_phy_g_attach(struct bwn_mac *mac) { struct bwn_softc *sc = mac->mac_sc; struct bwn_phy *phy = &mac->mac_phy; struct bwn_phy_g *pg = &phy->phy_g; unsigned int i; int16_t pab0, pab1, pab2; static int8_t bwn_phy_g_tssi2dbm_table[] = BWN_PHY_G_TSSI2DBM_TABLE; int8_t bg; + int error; - bg = (int8_t)siba_sprom_get_tssi_bg(sc->sc_dev); - pab0 = (int16_t)siba_sprom_get_pa0b0(sc->sc_dev); - pab1 = (int16_t)siba_sprom_get_pa0b1(sc->sc_dev); - pab2 = (int16_t)siba_sprom_get_pa0b2(sc->sc_dev); + /* Fetch SPROM configuration */ +#define BWN_PHY_G_READVAR(_dev, _type, _name, _result) \ +do { \ + error = bhnd_nvram_getvar_ ##_type((_dev), (_name), (_result)); \ + if (error) { \ + device_printf((_dev), "NVRAM variable %s unreadable: " \ + "%d\n", (_name), error); \ + return (error); \ + } \ +} while(0) - if ((siba_get_chipid(sc->sc_dev) == 0x4301) && (phy->rf_ver != 0x2050)) - device_printf(sc->sc_dev, "not supported anymore\n"); + BWN_PHY_G_READVAR(sc->sc_dev, int8, BHND_NVAR_PA0ITSSIT, &bg); + BWN_PHY_G_READVAR(sc->sc_dev, int16, BHND_NVAR_PA0B0, &pab0); + BWN_PHY_G_READVAR(sc->sc_dev, int16, BHND_NVAR_PA0B1, &pab1); + BWN_PHY_G_READVAR(sc->sc_dev, int16, BHND_NVAR_PA0B2, &pab2); + BWN_PHY_G_READVAR(sc->sc_dev, int16, BHND_NVAR_PA0MAXPWR, + &pg->pg_pa0maxpwr); +#undef BWN_PHY_G_READVAR + pg->pg_flags = 0; if (pab0 == 0 || pab1 == 0 || pab2 == 0 || pab0 == -1 || pab1 == -1 || pab2 == -1) { pg->pg_idletssi = 52; pg->pg_tssi2dbm = bwn_phy_g_tssi2dbm_table; return (0); } pg->pg_idletssi = (bg == 0 || bg == -1) ? 62 : bg; pg->pg_tssi2dbm = (uint8_t *)malloc(64, M_DEVBUF, M_NOWAIT | M_ZERO); if (pg->pg_tssi2dbm == NULL) { device_printf(sc->sc_dev, "failed to allocate buffer\n"); return (ENOMEM); } for (i = 0; i < 64; i++) { int32_t m1, m2, f, q, delta; int8_t j = 0; m1 = BWN_TSSI2DBM(16 * pab0 + i * pab1, 32); m2 = MAX(BWN_TSSI2DBM(32768 + i * pab2, 256), 1); f = 256; do { if (j > 15) { device_printf(sc->sc_dev, "failed to generate tssi2dBm\n"); free(pg->pg_tssi2dbm, M_DEVBUF); return (ENOMEM); } q = BWN_TSSI2DBM(f * 4096 - BWN_TSSI2DBM(m2 * f, 16) * f, 2048); delta = abs(q - f); f = q; j++; } while (delta >= 2); pg->pg_tssi2dbm[i] = MIN(MAX(BWN_TSSI2DBM(m1 * f, 8192), -127), 128); } pg->pg_flags |= BWN_PHY_G_FLAG_TSSITABLE_ALLOC; return (0); } void bwn_phy_g_detach(struct bwn_mac *mac) { struct bwn_phy_g *pg = &mac->mac_phy.phy_g; if (pg->pg_flags & BWN_PHY_G_FLAG_TSSITABLE_ALLOC) { free(pg->pg_tssi2dbm, M_DEVBUF); pg->pg_tssi2dbm = NULL; } pg->pg_flags = 0; } void bwn_phy_g_init_pre(struct bwn_mac *mac) { struct bwn_phy *phy = &mac->mac_phy; struct bwn_phy_g *pg = &phy->phy_g; void *tssi2dbm; int idletssi; unsigned int i; tssi2dbm = pg->pg_tssi2dbm; idletssi = pg->pg_idletssi; memset(pg, 0, sizeof(*pg)); pg->pg_tssi2dbm = tssi2dbm; pg->pg_idletssi = idletssi; memset(pg->pg_minlowsig, 0xff, sizeof(pg->pg_minlowsig)); for (i = 0; i < N(pg->pg_nrssi); i++) pg->pg_nrssi[i] = -1000; for (i = 0; i < N(pg->pg_nrssi_lt); i++) pg->pg_nrssi_lt[i] = i; pg->pg_lofcal = 0xffff; pg->pg_initval = 0xffff; pg->pg_immode = BWN_IMMODE_NONE; pg->pg_ofdmtab_dir = BWN_OFDMTAB_DIR_UNKNOWN; pg->pg_avgtssi = 0xff; pg->pg_loctl.tx_bias = 0xff; TAILQ_INIT(&pg->pg_loctl.calib_list); } int bwn_phy_g_prepare_hw(struct bwn_mac *mac) { struct bwn_phy *phy = &mac->mac_phy; struct bwn_phy_g *pg = &phy->phy_g; struct bwn_softc *sc = mac->mac_sc; struct bwn_txpwr_loctl *lo = &pg->pg_loctl; static const struct bwn_rfatt rfatt0[] = { { 3, 0 }, { 1, 0 }, { 5, 0 }, { 7, 0 }, { 9, 0 }, { 2, 0 }, { 0, 0 }, { 4, 0 }, { 6, 0 }, { 8, 0 }, { 1, 1 }, { 2, 1 }, { 3, 1 }, { 4, 1 } }; static const struct bwn_rfatt rfatt1[] = { { 2, 1 }, { 4, 1 }, { 6, 1 }, { 8, 1 }, { 10, 1 }, { 12, 1 }, { 14, 1 } }; static const struct bwn_rfatt rfatt2[] = { { 0, 1 }, { 2, 1 }, { 4, 1 }, { 6, 1 }, { 8, 1 }, { 9, 1 }, { 9, 1 } }; static const struct bwn_bbatt bbatt_0[] = { { 0 }, { 1 }, { 2 }, { 3 }, { 4 }, { 5 }, { 6 }, { 7 }, { 8 } }; KASSERT(phy->type == BWN_PHYTYPE_G, ("%s fail", __func__)); if (phy->rf_ver == 0x2050 && phy->rf_rev < 6) pg->pg_bbatt.att = 0; else pg->pg_bbatt.att = 2; /* prepare Radio Attenuation */ pg->pg_rfatt.padmix = 0; - if (siba_get_pci_subvendor(sc->sc_dev) == SIBA_BOARDVENDOR_BCM && - siba_get_pci_subdevice(sc->sc_dev) == SIBA_BOARD_BCM4309G) { - if (siba_get_pci_revid(sc->sc_dev) < 0x43) { + if (sc->sc_board_info.board_vendor == PCI_VENDOR_BROADCOM && + sc->sc_board_info.board_type == BHND_BOARD_BCM94309G) { + if (sc->sc_board_info.board_rev < 0x43) { pg->pg_rfatt.att = 2; goto done; - } else if (siba_get_pci_revid(sc->sc_dev) < 0x51) { + } else if (sc->sc_board_info.board_rev < 0x51) { pg->pg_rfatt.att = 3; goto done; } } if (phy->type == BWN_PHYTYPE_A) { pg->pg_rfatt.att = 0x60; goto done; } switch (phy->rf_ver) { case 0x2050: switch (phy->rf_rev) { case 0: pg->pg_rfatt.att = 5; goto done; case 1: if (phy->type == BWN_PHYTYPE_G) { - if (siba_get_pci_subvendor(sc->sc_dev) == - SIBA_BOARDVENDOR_BCM && - siba_get_pci_subdevice(sc->sc_dev) == - SIBA_BOARD_BCM4309G && - siba_get_pci_revid(sc->sc_dev) >= 30) + if (sc->sc_board_info.board_vendor == + PCI_VENDOR_BROADCOM && + sc->sc_board_info.board_type == + BHND_BOARD_BCM94309G && + sc->sc_board_info.board_rev >= 30) pg->pg_rfatt.att = 3; - else if (siba_get_pci_subvendor(sc->sc_dev) == - SIBA_BOARDVENDOR_BCM && - siba_get_pci_subdevice(sc->sc_dev) == - SIBA_BOARD_BU4306) + else if (sc->sc_board_info.board_vendor == + PCI_VENDOR_BROADCOM && + sc->sc_board_info.board_type == + BHND_BOARD_BU4306) pg->pg_rfatt.att = 3; else pg->pg_rfatt.att = 1; } else { - if (siba_get_pci_subvendor(sc->sc_dev) == - SIBA_BOARDVENDOR_BCM && - siba_get_pci_subdevice(sc->sc_dev) == - SIBA_BOARD_BCM4309G && - siba_get_pci_revid(sc->sc_dev) >= 30) + if (sc->sc_board_info.board_vendor == + PCI_VENDOR_BROADCOM && + sc->sc_board_info.board_type == + BHND_BOARD_BCM94309G && + sc->sc_board_info.board_rev >= 30) pg->pg_rfatt.att = 7; else pg->pg_rfatt.att = 6; } goto done; case 2: if (phy->type == BWN_PHYTYPE_G) { - if (siba_get_pci_subvendor(sc->sc_dev) == - SIBA_BOARDVENDOR_BCM && - siba_get_pci_subdevice(sc->sc_dev) == - SIBA_BOARD_BCM4309G && - siba_get_pci_revid(sc->sc_dev) >= 30) + if (sc->sc_board_info.board_vendor == + PCI_VENDOR_BROADCOM && + sc->sc_board_info.board_type == + BHND_BOARD_BCM94309G && + sc->sc_board_info.board_rev >= 30) pg->pg_rfatt.att = 3; - else if (siba_get_pci_subvendor(sc->sc_dev) == - SIBA_BOARDVENDOR_BCM && - siba_get_pci_subdevice(sc->sc_dev) == - SIBA_BOARD_BU4306) + else if (sc->sc_board_info.board_vendor == + PCI_VENDOR_BROADCOM && + sc->sc_board_info.board_type == + BHND_BOARD_BU4306) pg->pg_rfatt.att = 5; - else if (siba_get_chipid(sc->sc_dev) == 0x4320) + else if (sc->sc_cid.chip_id == + BHND_CHIPID_BCM4320) pg->pg_rfatt.att = 4; else pg->pg_rfatt.att = 3; } else pg->pg_rfatt.att = 6; goto done; case 3: pg->pg_rfatt.att = 5; goto done; case 4: case 5: pg->pg_rfatt.att = 1; goto done; case 6: case 7: pg->pg_rfatt.att = 5; goto done; case 8: pg->pg_rfatt.att = 0xa; pg->pg_rfatt.padmix = 1; goto done; case 9: default: pg->pg_rfatt.att = 5; goto done; } break; case 0x2053: switch (phy->rf_rev) { case 1: pg->pg_rfatt.att = 6; goto done; } break; } pg->pg_rfatt.att = 5; done: pg->pg_txctl = (bwn_phy_g_txctl(mac) << 4); if (!bwn_has_hwpctl(mac)) { lo->rfatt.array = rfatt0; lo->rfatt.len = N(rfatt0); lo->rfatt.min = 0; lo->rfatt.max = 9; goto genbbatt; } if (phy->rf_ver == 0x2050 && phy->rf_rev == 8) { lo->rfatt.array = rfatt1; lo->rfatt.len = N(rfatt1); lo->rfatt.min = 0; lo->rfatt.max = 14; goto genbbatt; } lo->rfatt.array = rfatt2; lo->rfatt.len = N(rfatt2); lo->rfatt.min = 0; lo->rfatt.max = 9; genbbatt: lo->bbatt.array = bbatt_0; lo->bbatt.len = N(bbatt_0); lo->bbatt.min = 0; lo->bbatt.max = 8; BWN_READ_4(mac, BWN_MACCTL); if (phy->rev == 1) { phy->gmode = 0; bwn_reset_core(mac, 0); bwn_phy_g_init_sub(mac); phy->gmode = 1; bwn_reset_core(mac, 1); } return (0); } static uint16_t bwn_phy_g_txctl(struct bwn_mac *mac) { struct bwn_phy *phy = &mac->mac_phy; if (phy->rf_ver != 0x2050) return (0); if (phy->rf_rev == 1) return (BWN_TXCTL_PA2DB | BWN_TXCTL_TXMIX); if (phy->rf_rev < 6) return (BWN_TXCTL_PA2DB); if (phy->rf_rev == 8) return (BWN_TXCTL_TXMIX); return (0); } int bwn_phy_g_init(struct bwn_mac *mac) { bwn_phy_g_init_sub(mac); return (0); } void bwn_phy_g_exit(struct bwn_mac *mac) { struct bwn_txpwr_loctl *lo = &mac->mac_phy.phy_g.pg_loctl; struct bwn_lo_calib *cal, *tmp; if (lo == NULL) return; TAILQ_FOREACH_SAFE(cal, &lo->calib_list, list, tmp) { TAILQ_REMOVE(&lo->calib_list, cal, list); free(cal, M_DEVBUF); } } uint16_t bwn_phy_g_read(struct bwn_mac *mac, uint16_t reg) { BWN_WRITE_2(mac, BWN_PHYCTL, reg); return (BWN_READ_2(mac, BWN_PHYDATA)); } void bwn_phy_g_write(struct bwn_mac *mac, uint16_t reg, uint16_t value) { BWN_WRITE_2(mac, BWN_PHYCTL, reg); BWN_WRITE_2(mac, BWN_PHYDATA, value); } uint16_t bwn_phy_g_rf_read(struct bwn_mac *mac, uint16_t reg) { KASSERT(reg != 1, ("%s:%d: fail", __func__, __LINE__)); BWN_WRITE_2(mac, BWN_RFCTL, reg | 0x80); return (BWN_READ_2(mac, BWN_RFDATALO)); } void bwn_phy_g_rf_write(struct bwn_mac *mac, uint16_t reg, uint16_t value) { KASSERT(reg != 1, ("%s:%d: fail", __func__, __LINE__)); BWN_WRITE_2(mac, BWN_RFCTL, reg); BWN_WRITE_2(mac, BWN_RFDATALO, value); } int bwn_phy_g_hwpctl(struct bwn_mac *mac) { return (mac->mac_phy.rev >= 6); } void bwn_phy_g_rf_onoff(struct bwn_mac *mac, int on) { struct bwn_phy *phy = &mac->mac_phy; struct bwn_phy_g *pg = &phy->phy_g; unsigned int channel; uint16_t rfover, rfoverval; if (on) { if (phy->rf_on) return; BWN_PHY_WRITE(mac, 0x15, 0x8000); BWN_PHY_WRITE(mac, 0x15, 0xcc00); BWN_PHY_WRITE(mac, 0x15, (phy->gmode ? 0xc0 : 0x0)); if (pg->pg_flags & BWN_PHY_G_FLAG_RADIOCTX_VALID) { BWN_PHY_WRITE(mac, BWN_PHY_RFOVER, pg->pg_radioctx_over); BWN_PHY_WRITE(mac, BWN_PHY_RFOVERVAL, pg->pg_radioctx_overval); pg->pg_flags &= ~BWN_PHY_G_FLAG_RADIOCTX_VALID; } channel = phy->chan; bwn_phy_g_switch_chan(mac, 6, 1); bwn_phy_g_switch_chan(mac, channel, 0); return; } rfover = BWN_PHY_READ(mac, BWN_PHY_RFOVER); rfoverval = BWN_PHY_READ(mac, BWN_PHY_RFOVERVAL); pg->pg_radioctx_over = rfover; pg->pg_radioctx_overval = rfoverval; pg->pg_flags |= BWN_PHY_G_FLAG_RADIOCTX_VALID; BWN_PHY_WRITE(mac, BWN_PHY_RFOVER, rfover | 0x008c); BWN_PHY_WRITE(mac, BWN_PHY_RFOVERVAL, rfoverval & 0xff73); } int bwn_phy_g_switch_channel(struct bwn_mac *mac, uint32_t newchan) { if ((newchan < 1) || (newchan > 14)) return (EINVAL); bwn_phy_g_switch_chan(mac, newchan, 0); return (0); } uint32_t bwn_phy_g_get_default_chan(struct bwn_mac *mac) { return (1); } void bwn_phy_g_set_antenna(struct bwn_mac *mac, int antenna) { struct bwn_phy *phy = &mac->mac_phy; uint64_t hf; int autodiv = 0; uint16_t tmp; if (antenna == BWN_ANTAUTO0 || antenna == BWN_ANTAUTO1) autodiv = 1; hf = bwn_hf_read(mac) & ~BWN_HF_UCODE_ANTDIV_HELPER; bwn_hf_write(mac, hf); BWN_PHY_WRITE(mac, BWN_PHY_BBANDCFG, (BWN_PHY_READ(mac, BWN_PHY_BBANDCFG) & ~BWN_PHY_BBANDCFG_RXANT) | ((autodiv ? BWN_ANTAUTO1 : antenna) << BWN_PHY_BBANDCFG_RXANT_SHIFT)); if (autodiv) { tmp = BWN_PHY_READ(mac, BWN_PHY_ANTDWELL); if (antenna == BWN_ANTAUTO1) tmp &= ~BWN_PHY_ANTDWELL_AUTODIV1; else tmp |= BWN_PHY_ANTDWELL_AUTODIV1; BWN_PHY_WRITE(mac, BWN_PHY_ANTDWELL, tmp); } tmp = BWN_PHY_READ(mac, BWN_PHY_ANTWRSETT); if (autodiv) tmp |= BWN_PHY_ANTWRSETT_ARXDIV; else tmp &= ~BWN_PHY_ANTWRSETT_ARXDIV; BWN_PHY_WRITE(mac, BWN_PHY_ANTWRSETT, tmp); if (phy->rev >= 2) { BWN_PHY_WRITE(mac, BWN_PHY_OFDM61, BWN_PHY_READ(mac, BWN_PHY_OFDM61) | BWN_PHY_OFDM61_10); BWN_PHY_WRITE(mac, BWN_PHY_DIVSRCHGAINBACK, (BWN_PHY_READ(mac, BWN_PHY_DIVSRCHGAINBACK) & 0xff00) | 0x15); if (phy->rev == 2) BWN_PHY_WRITE(mac, BWN_PHY_ADIVRELATED, 8); else BWN_PHY_WRITE(mac, BWN_PHY_ADIVRELATED, (BWN_PHY_READ(mac, BWN_PHY_ADIVRELATED) & 0xff00) | 8); } if (phy->rev >= 6) BWN_PHY_WRITE(mac, BWN_PHY_OFDM9B, 0xdc); hf |= BWN_HF_UCODE_ANTDIV_HELPER; bwn_hf_write(mac, hf); } int bwn_phy_g_im(struct bwn_mac *mac, int mode) { struct bwn_phy *phy = &mac->mac_phy; struct bwn_phy_g *pg = &phy->phy_g; KASSERT(phy->type == BWN_PHYTYPE_G, ("%s: fail", __func__)); KASSERT(mode == BWN_IMMODE_NONE, ("%s: fail", __func__)); if (phy->rev == 0 || !phy->gmode) return (ENODEV); pg->pg_aci_wlan_automatic = 0; return (0); } bwn_txpwr_result_t bwn_phy_g_recalc_txpwr(struct bwn_mac *mac, int ignore_tssi) { struct bwn_phy *phy = &mac->mac_phy; struct bwn_phy_g *pg = &phy->phy_g; struct bwn_softc *sc = mac->mac_sc; unsigned int tssi; int cck, ofdm; int power; int rfatt, bbatt; unsigned int max; KASSERT(phy->type == BWN_PHYTYPE_G, ("%s: fail", __func__)); cck = bwn_phy_shm_tssi_read(mac, BWN_SHARED_TSSI_CCK); ofdm = bwn_phy_shm_tssi_read(mac, BWN_SHARED_TSSI_OFDM_G); if (cck < 0 && ofdm < 0) { if (ignore_tssi == 0) return (BWN_TXPWR_RES_DONE); cck = 0; ofdm = 0; } tssi = (cck < 0) ? ofdm : ((ofdm < 0) ? cck : (cck + ofdm) / 2); if (pg->pg_avgtssi != 0xff) tssi = (tssi + pg->pg_avgtssi) / 2; pg->pg_avgtssi = tssi; KASSERT(tssi < BWN_TSSI_MAX, ("%s:%d: fail", __func__, __LINE__)); - max = siba_sprom_get_maxpwr_bg(sc->sc_dev); - if (siba_sprom_get_bf_lo(sc->sc_dev) & BWN_BFL_PACTRL) + max = pg->pg_pa0maxpwr; + if (sc->sc_board_info.board_flags & BHND_BFL_PACTRL) max -= 3; if (max >= 120) { device_printf(sc->sc_dev, "invalid max TX-power value\n"); max = 80; - siba_sprom_set_maxpwr_bg(sc->sc_dev, max); + pg->pg_pa0maxpwr = max; } power = MIN(MAX((phy->txpower < 0) ? 0 : (phy->txpower << 2), 0), max) - (pg->pg_tssi2dbm[MIN(MAX(pg->pg_idletssi - pg->pg_curtssi + tssi, 0x00), 0x3f)]); if (power == 0) return (BWN_TXPWR_RES_DONE); rfatt = -((power + 7) / 8); bbatt = (-(power / 2)) - (4 * rfatt); if ((rfatt == 0) && (bbatt == 0)) return (BWN_TXPWR_RES_DONE); pg->pg_bbatt_delta = bbatt; pg->pg_rfatt_delta = rfatt; return (BWN_TXPWR_RES_NEED_ADJUST); } void bwn_phy_g_set_txpwr(struct bwn_mac *mac) { struct bwn_phy *phy = &mac->mac_phy; struct bwn_phy_g *pg = &phy->phy_g; struct bwn_softc *sc = mac->mac_sc; int rfatt, bbatt; uint8_t txctl; bwn_mac_suspend(mac); BWN_ASSERT_LOCKED(sc); bbatt = pg->pg_bbatt.att; bbatt += pg->pg_bbatt_delta; rfatt = pg->pg_rfatt.att; rfatt += pg->pg_rfatt_delta; bwn_phy_g_setatt(mac, &bbatt, &rfatt); txctl = pg->pg_txctl; if ((phy->rf_ver == 0x2050) && (phy->rf_rev == 2)) { if (rfatt <= 1) { if (txctl == 0) { txctl = BWN_TXCTL_PA2DB | BWN_TXCTL_TXMIX; rfatt += 2; bbatt += 2; - } else if (siba_sprom_get_bf_lo(sc->sc_dev) & - BWN_BFL_PACTRL) { + } else if (sc->sc_board_info.board_flags & + BHND_BFL_PACTRL) { bbatt += 4 * (rfatt - 2); rfatt = 2; } } else if (rfatt > 4 && txctl) { txctl = 0; if (bbatt < 3) { rfatt -= 3; bbatt += 2; } else { rfatt -= 2; bbatt -= 2; } } } pg->pg_txctl = txctl; bwn_phy_g_setatt(mac, &bbatt, &rfatt); pg->pg_rfatt.att = rfatt; pg->pg_bbatt.att = bbatt; DPRINTF(sc, BWN_DEBUG_TXPOW, "%s: adjust TX power\n", __func__); bwn_phy_lock(mac); bwn_rf_lock(mac); bwn_phy_g_set_txpwr_sub(mac, &pg->pg_bbatt, &pg->pg_rfatt, pg->pg_txctl); bwn_rf_unlock(mac); bwn_phy_unlock(mac); bwn_mac_enable(mac); } void bwn_phy_g_task_15s(struct bwn_mac *mac) { struct bwn_phy *phy = &mac->mac_phy; struct bwn_phy_g *pg = &phy->phy_g; struct bwn_softc *sc = mac->mac_sc; struct bwn_txpwr_loctl *lo = &pg->pg_loctl; unsigned long expire, now; struct bwn_lo_calib *cal, *tmp; uint8_t expired = 0; bwn_mac_suspend(mac); if (lo == NULL) goto fail; BWN_GETTIME(now); if (bwn_has_hwpctl(mac)) { expire = now - BWN_LO_PWRVEC_EXPIRE; if (ieee80211_time_before(lo->pwr_vec_read_time, expire)) { bwn_lo_get_powervector(mac); bwn_phy_g_dc_lookup_init(mac, 0); } goto fail; } expire = now - BWN_LO_CALIB_EXPIRE; TAILQ_FOREACH_SAFE(cal, &lo->calib_list, list, tmp) { if (!ieee80211_time_before(cal->calib_time, expire)) continue; if (BWN_BBATTCMP(&cal->bbatt, &pg->pg_bbatt) && BWN_RFATTCMP(&cal->rfatt, &pg->pg_rfatt)) { KASSERT(!expired, ("%s:%d: fail", __func__, __LINE__)); expired = 1; } DPRINTF(sc, BWN_DEBUG_LO, "expired BB %u RF %u %u I %d Q %d\n", cal->bbatt.att, cal->rfatt.att, cal->rfatt.padmix, cal->ctl.i, cal->ctl.q); TAILQ_REMOVE(&lo->calib_list, cal, list); free(cal, M_DEVBUF); } if (expired || TAILQ_EMPTY(&lo->calib_list)) { cal = bwn_lo_calibset(mac, &pg->pg_bbatt, &pg->pg_rfatt); if (cal == NULL) { device_printf(sc->sc_dev, "failed to recalibrate LO\n"); goto fail; } TAILQ_INSERT_TAIL(&lo->calib_list, cal, list); bwn_lo_write(mac, &cal->ctl); } fail: bwn_mac_enable(mac); } void bwn_phy_g_task_60s(struct bwn_mac *mac) { struct bwn_phy *phy = &mac->mac_phy; struct bwn_softc *sc = mac->mac_sc; uint8_t old = phy->chan; - if (!(siba_sprom_get_bf_lo(sc->sc_dev) & BWN_BFL_RSSI)) + if (!(sc->sc_board_info.board_flags & BHND_BFL_ADCDIV)) return; bwn_mac_suspend(mac); bwn_nrssi_slope_11g(mac); if ((phy->rf_ver == 0x2050) && (phy->rf_rev == 8)) { bwn_switch_channel(mac, (old >= 8) ? 1 : 13); bwn_switch_channel(mac, old); } bwn_mac_enable(mac); } void bwn_phy_switch_analog(struct bwn_mac *mac, int on) { BWN_WRITE_2(mac, BWN_PHY0, on ? 0 : 0xf4); } static void bwn_phy_g_init_sub(struct bwn_mac *mac) { struct bwn_phy *phy = &mac->mac_phy; struct bwn_phy_g *pg = &phy->phy_g; struct bwn_softc *sc = mac->mac_sc; uint16_t i, tmp; if (phy->rev == 1) bwn_phy_init_b5(mac); else bwn_phy_init_b6(mac); if (phy->rev >= 2 || phy->gmode) bwn_phy_init_a(mac); if (phy->rev >= 2) { BWN_PHY_WRITE(mac, BWN_PHY_ANALOGOVER, 0); BWN_PHY_WRITE(mac, BWN_PHY_ANALOGOVERVAL, 0); } if (phy->rev == 2) { BWN_PHY_WRITE(mac, BWN_PHY_RFOVER, 0); BWN_PHY_WRITE(mac, BWN_PHY_PGACTL, 0xc0); } if (phy->rev > 5) { BWN_PHY_WRITE(mac, BWN_PHY_RFOVER, 0x400); BWN_PHY_WRITE(mac, BWN_PHY_PGACTL, 0xc0); } if (phy->gmode || phy->rev >= 2) { tmp = BWN_PHY_READ(mac, BWN_PHY_VERSION_OFDM); tmp &= BWN_PHYVER_VERSION; if (tmp == 3 || tmp == 5) { BWN_PHY_WRITE(mac, BWN_PHY_OFDM(0xc2), 0x1816); BWN_PHY_WRITE(mac, BWN_PHY_OFDM(0xc3), 0x8006); } if (tmp == 5) { BWN_PHY_SETMASK(mac, BWN_PHY_OFDM(0xcc), 0x00ff, 0x1f00); } } if ((phy->rev <= 2 && phy->gmode) || phy->rev >= 2) BWN_PHY_WRITE(mac, BWN_PHY_OFDM(0x7e), 0x78); if (phy->rf_rev == 8) { BWN_PHY_SET(mac, BWN_PHY_EXTG(0x01), 0x80); BWN_PHY_SET(mac, BWN_PHY_OFDM(0x3e), 0x4); } if (BWN_HAS_LOOPBACK(phy)) bwn_loopback_calcgain(mac); if (phy->rf_rev != 8) { if (pg->pg_initval == 0xffff) pg->pg_initval = bwn_rf_init_bcm2050(mac); else BWN_RF_WRITE(mac, 0x0078, pg->pg_initval); } bwn_lo_g_init(mac); if (BWN_HAS_TXMAG(phy)) { BWN_RF_WRITE(mac, 0x52, (BWN_RF_READ(mac, 0x52) & 0xff00) | pg->pg_loctl.tx_bias | pg->pg_loctl.tx_magn); } else { BWN_RF_SETMASK(mac, 0x52, 0xfff0, pg->pg_loctl.tx_bias); } if (phy->rev >= 6) { BWN_PHY_SETMASK(mac, BWN_PHY_CCK(0x36), 0x0fff, (pg->pg_loctl.tx_bias << 12)); } - if (siba_sprom_get_bf_lo(sc->sc_dev) & BWN_BFL_PACTRL) + if (sc->sc_board_info.board_flags & BHND_BFL_PACTRL) BWN_PHY_WRITE(mac, BWN_PHY_CCK(0x2e), 0x8075); else BWN_PHY_WRITE(mac, BWN_PHY_CCK(0x2e), 0x807f); if (phy->rev < 2) BWN_PHY_WRITE(mac, BWN_PHY_CCK(0x2f), 0x101); else BWN_PHY_WRITE(mac, BWN_PHY_CCK(0x2f), 0x202); if (phy->gmode || phy->rev >= 2) { bwn_lo_g_adjust(mac); BWN_PHY_WRITE(mac, BWN_PHY_LO_MASK, 0x8078); } - if (!(siba_sprom_get_bf_lo(sc->sc_dev) & BWN_BFL_RSSI)) { + if (!(sc->sc_board_info.board_flags & BHND_BFL_ADCDIV)) { for (i = 0; i < 64; i++) { BWN_PHY_WRITE(mac, BWN_PHY_NRSSI_CTRL, i); BWN_PHY_WRITE(mac, BWN_PHY_NRSSI_DATA, (uint16_t)MIN(MAX(bwn_nrssi_read(mac, i) - 0xffff, -32), 31)); } bwn_nrssi_threshold(mac); } else if (phy->gmode || phy->rev >= 2) { if (pg->pg_nrssi[0] == -1000) { KASSERT(pg->pg_nrssi[1] == -1000, ("%s:%d: fail", __func__, __LINE__)); bwn_nrssi_slope_11g(mac); } else bwn_nrssi_threshold(mac); } if (phy->rf_rev == 8) BWN_PHY_WRITE(mac, BWN_PHY_EXTG(0x05), 0x3230); bwn_phy_hwpctl_init(mac); - if ((siba_get_chipid(sc->sc_dev) == 0x4306 - && siba_get_chippkg(sc->sc_dev) == 2) || 0) { + if ((sc->sc_cid.chip_id == BHND_CHIPID_BCM4306 + && sc->sc_cid.chip_pkg == 2) || 0) { BWN_PHY_MASK(mac, BWN_PHY_CRS0, 0xbfff); BWN_PHY_MASK(mac, BWN_PHY_OFDM(0xc3), 0x7fff); } } static void bwn_phy_init_b5(struct bwn_mac *mac) { struct bwn_phy *phy = &mac->mac_phy; struct bwn_phy_g *pg = &phy->phy_g; struct bwn_softc *sc = mac->mac_sc; uint16_t offset, value; uint8_t old_channel; if (phy->analog == 1) BWN_RF_SET(mac, 0x007a, 0x0050); - if ((siba_get_pci_subvendor(sc->sc_dev) != SIBA_BOARDVENDOR_BCM) && - (siba_get_pci_subdevice(sc->sc_dev) != SIBA_BOARD_BU4306)) { + if ((sc->sc_board_info.board_vendor != PCI_VENDOR_BROADCOM) && + (sc->sc_board_info.board_type != BHND_BOARD_BU4306)) { value = 0x2120; for (offset = 0x00a8; offset < 0x00c7; offset++) { BWN_PHY_WRITE(mac, offset, value); value += 0x202; } } BWN_PHY_SETMASK(mac, 0x0035, 0xf0ff, 0x0700); if (phy->rf_ver == 0x2050) BWN_PHY_WRITE(mac, 0x0038, 0x0667); if (phy->gmode || phy->rev >= 2) { if (phy->rf_ver == 0x2050) { BWN_RF_SET(mac, 0x007a, 0x0020); BWN_RF_SET(mac, 0x0051, 0x0004); } BWN_WRITE_2(mac, BWN_PHY_RADIO, 0x0000); BWN_PHY_SET(mac, 0x0802, 0x0100); BWN_PHY_SET(mac, 0x042b, 0x2000); BWN_PHY_WRITE(mac, 0x001c, 0x186a); BWN_PHY_SETMASK(mac, 0x0013, 0x00ff, 0x1900); BWN_PHY_SETMASK(mac, 0x0035, 0xffc0, 0x0064); BWN_PHY_SETMASK(mac, 0x005d, 0xff80, 0x000a); } if (mac->mac_flags & BWN_MAC_FLAG_BADFRAME_PREEMP) BWN_PHY_SET(mac, BWN_PHY_RADIO_BITFIELD, (1 << 11)); if (phy->analog == 1) { BWN_PHY_WRITE(mac, 0x0026, 0xce00); BWN_PHY_WRITE(mac, 0x0021, 0x3763); BWN_PHY_WRITE(mac, 0x0022, 0x1bc3); BWN_PHY_WRITE(mac, 0x0023, 0x06f9); BWN_PHY_WRITE(mac, 0x0024, 0x037e); } else BWN_PHY_WRITE(mac, 0x0026, 0xcc00); BWN_PHY_WRITE(mac, 0x0030, 0x00c6); BWN_WRITE_2(mac, 0x03ec, 0x3f22); if (phy->analog == 1) BWN_PHY_WRITE(mac, 0x0020, 0x3e1c); else BWN_PHY_WRITE(mac, 0x0020, 0x301c); if (phy->analog == 0) BWN_WRITE_2(mac, 0x03e4, 0x3000); old_channel = phy->chan; bwn_phy_g_switch_chan(mac, 7, 0); if (phy->rf_ver != 0x2050) { BWN_RF_WRITE(mac, 0x0075, 0x0080); BWN_RF_WRITE(mac, 0x0079, 0x0081); } BWN_RF_WRITE(mac, 0x0050, 0x0020); BWN_RF_WRITE(mac, 0x0050, 0x0023); if (phy->rf_ver == 0x2050) { BWN_RF_WRITE(mac, 0x0050, 0x0020); BWN_RF_WRITE(mac, 0x005a, 0x0070); } BWN_RF_WRITE(mac, 0x005b, 0x007b); BWN_RF_WRITE(mac, 0x005c, 0x00b0); BWN_RF_SET(mac, 0x007a, 0x0007); bwn_phy_g_switch_chan(mac, old_channel, 0); BWN_PHY_WRITE(mac, 0x0014, 0x0080); BWN_PHY_WRITE(mac, 0x0032, 0x00ca); BWN_PHY_WRITE(mac, 0x002a, 0x88a3); bwn_phy_g_set_txpwr_sub(mac, &pg->pg_bbatt, &pg->pg_rfatt, pg->pg_txctl); if (phy->rf_ver == 0x2050) BWN_RF_WRITE(mac, 0x005d, 0x000d); BWN_WRITE_2(mac, 0x03e4, (BWN_READ_2(mac, 0x03e4) & 0xffc0) | 0x0004); } static void bwn_loopback_calcgain(struct bwn_mac *mac) { struct bwn_phy *phy = &mac->mac_phy; struct bwn_phy_g *pg = &phy->phy_g; struct bwn_softc *sc = mac->mac_sc; uint16_t backup_phy[16] = { 0 }; uint16_t backup_radio[3]; uint16_t backup_bband; uint16_t i, j, loop_i_max; uint16_t trsw_rx; uint16_t loop1_outer_done, loop1_inner_done; backup_phy[0] = BWN_PHY_READ(mac, BWN_PHY_CRS0); backup_phy[1] = BWN_PHY_READ(mac, BWN_PHY_CCKBBANDCFG); backup_phy[2] = BWN_PHY_READ(mac, BWN_PHY_RFOVER); backup_phy[3] = BWN_PHY_READ(mac, BWN_PHY_RFOVERVAL); if (phy->rev != 1) { backup_phy[4] = BWN_PHY_READ(mac, BWN_PHY_ANALOGOVER); backup_phy[5] = BWN_PHY_READ(mac, BWN_PHY_ANALOGOVERVAL); } backup_phy[6] = BWN_PHY_READ(mac, BWN_PHY_CCK(0x5a)); backup_phy[7] = BWN_PHY_READ(mac, BWN_PHY_CCK(0x59)); backup_phy[8] = BWN_PHY_READ(mac, BWN_PHY_CCK(0x58)); backup_phy[9] = BWN_PHY_READ(mac, BWN_PHY_CCK(0x0a)); backup_phy[10] = BWN_PHY_READ(mac, BWN_PHY_CCK(0x03)); backup_phy[11] = BWN_PHY_READ(mac, BWN_PHY_LO_MASK); backup_phy[12] = BWN_PHY_READ(mac, BWN_PHY_LO_CTL); backup_phy[13] = BWN_PHY_READ(mac, BWN_PHY_CCK(0x2b)); backup_phy[14] = BWN_PHY_READ(mac, BWN_PHY_PGACTL); backup_phy[15] = BWN_PHY_READ(mac, BWN_PHY_LO_LEAKAGE); backup_bband = pg->pg_bbatt.att; backup_radio[0] = BWN_RF_READ(mac, 0x52); backup_radio[1] = BWN_RF_READ(mac, 0x43); backup_radio[2] = BWN_RF_READ(mac, 0x7a); BWN_PHY_MASK(mac, BWN_PHY_CRS0, 0x3fff); BWN_PHY_SET(mac, BWN_PHY_CCKBBANDCFG, 0x8000); BWN_PHY_SET(mac, BWN_PHY_RFOVER, 0x0002); BWN_PHY_MASK(mac, BWN_PHY_RFOVERVAL, 0xfffd); BWN_PHY_SET(mac, BWN_PHY_RFOVER, 0x0001); BWN_PHY_MASK(mac, BWN_PHY_RFOVERVAL, 0xfffe); if (phy->rev != 1) { BWN_PHY_SET(mac, BWN_PHY_ANALOGOVER, 0x0001); BWN_PHY_MASK(mac, BWN_PHY_ANALOGOVERVAL, 0xfffe); BWN_PHY_SET(mac, BWN_PHY_ANALOGOVER, 0x0002); BWN_PHY_MASK(mac, BWN_PHY_ANALOGOVERVAL, 0xfffd); } BWN_PHY_SET(mac, BWN_PHY_RFOVER, 0x000c); BWN_PHY_SET(mac, BWN_PHY_RFOVERVAL, 0x000c); BWN_PHY_SET(mac, BWN_PHY_RFOVER, 0x0030); BWN_PHY_SETMASK(mac, BWN_PHY_RFOVERVAL, 0xffcf, 0x10); BWN_PHY_WRITE(mac, BWN_PHY_CCK(0x5a), 0x0780); BWN_PHY_WRITE(mac, BWN_PHY_CCK(0x59), 0xc810); BWN_PHY_WRITE(mac, BWN_PHY_CCK(0x58), 0x000d); BWN_PHY_SET(mac, BWN_PHY_CCK(0x0a), 0x2000); if (phy->rev != 1) { BWN_PHY_SET(mac, BWN_PHY_ANALOGOVER, 0x0004); BWN_PHY_MASK(mac, BWN_PHY_ANALOGOVERVAL, 0xfffb); } BWN_PHY_SETMASK(mac, BWN_PHY_CCK(0x03), 0xff9f, 0x40); if (phy->rf_rev == 8) BWN_RF_WRITE(mac, 0x43, 0x000f); else { BWN_RF_WRITE(mac, 0x52, 0); BWN_RF_SETMASK(mac, 0x43, 0xfff0, 0x9); } bwn_phy_g_set_bbatt(mac, 11); if (phy->rev >= 3) BWN_PHY_WRITE(mac, BWN_PHY_LO_MASK, 0xc020); else BWN_PHY_WRITE(mac, BWN_PHY_LO_MASK, 0x8020); BWN_PHY_WRITE(mac, BWN_PHY_LO_CTL, 0); BWN_PHY_SETMASK(mac, BWN_PHY_CCK(0x2b), 0xffc0, 0x01); BWN_PHY_SETMASK(mac, BWN_PHY_CCK(0x2b), 0xc0ff, 0x800); BWN_PHY_SET(mac, BWN_PHY_RFOVER, 0x0100); BWN_PHY_MASK(mac, BWN_PHY_RFOVERVAL, 0xcfff); - if (siba_sprom_get_bf_lo(sc->sc_dev) & BWN_BFL_EXTLNA) { + if (sc->sc_board_info.board_flags & BHND_BFL_EXTLNA) { if (phy->rev >= 7) { BWN_PHY_SET(mac, BWN_PHY_RFOVER, 0x0800); BWN_PHY_SET(mac, BWN_PHY_RFOVERVAL, 0x8000); } } BWN_RF_MASK(mac, 0x7a, 0x00f7); j = 0; loop_i_max = (phy->rf_rev == 8) ? 15 : 9; for (i = 0; i < loop_i_max; i++) { for (j = 0; j < 16; j++) { BWN_RF_WRITE(mac, 0x43, i); BWN_PHY_SETMASK(mac, BWN_PHY_RFOVERVAL, 0xf0ff, (j << 8)); BWN_PHY_SETMASK(mac, BWN_PHY_PGACTL, 0x0fff, 0xa000); BWN_PHY_SET(mac, BWN_PHY_PGACTL, 0xf000); DELAY(20); if (BWN_PHY_READ(mac, BWN_PHY_LO_LEAKAGE) >= 0xdfc) goto done0; } } done0: loop1_outer_done = i; loop1_inner_done = j; if (j >= 8) { BWN_PHY_SET(mac, BWN_PHY_RFOVERVAL, 0x30); trsw_rx = 0x1b; for (j = j - 8; j < 16; j++) { BWN_PHY_SETMASK(mac, BWN_PHY_RFOVERVAL, 0xf0ff, j << 8); BWN_PHY_SETMASK(mac, BWN_PHY_PGACTL, 0x0fff, 0xa000); BWN_PHY_SET(mac, BWN_PHY_PGACTL, 0xf000); DELAY(20); trsw_rx -= 3; if (BWN_PHY_READ(mac, BWN_PHY_LO_LEAKAGE) >= 0xdfc) goto done1; } } else trsw_rx = 0x18; done1: if (phy->rev != 1) { BWN_PHY_WRITE(mac, BWN_PHY_ANALOGOVER, backup_phy[4]); BWN_PHY_WRITE(mac, BWN_PHY_ANALOGOVERVAL, backup_phy[5]); } BWN_PHY_WRITE(mac, BWN_PHY_CCK(0x5a), backup_phy[6]); BWN_PHY_WRITE(mac, BWN_PHY_CCK(0x59), backup_phy[7]); BWN_PHY_WRITE(mac, BWN_PHY_CCK(0x58), backup_phy[8]); BWN_PHY_WRITE(mac, BWN_PHY_CCK(0x0a), backup_phy[9]); BWN_PHY_WRITE(mac, BWN_PHY_CCK(0x03), backup_phy[10]); BWN_PHY_WRITE(mac, BWN_PHY_LO_MASK, backup_phy[11]); BWN_PHY_WRITE(mac, BWN_PHY_LO_CTL, backup_phy[12]); BWN_PHY_WRITE(mac, BWN_PHY_CCK(0x2b), backup_phy[13]); BWN_PHY_WRITE(mac, BWN_PHY_PGACTL, backup_phy[14]); bwn_phy_g_set_bbatt(mac, backup_bband); BWN_RF_WRITE(mac, 0x52, backup_radio[0]); BWN_RF_WRITE(mac, 0x43, backup_radio[1]); BWN_RF_WRITE(mac, 0x7a, backup_radio[2]); BWN_PHY_WRITE(mac, BWN_PHY_RFOVER, backup_phy[2] | 0x0003); DELAY(10); BWN_PHY_WRITE(mac, BWN_PHY_RFOVER, backup_phy[2]); BWN_PHY_WRITE(mac, BWN_PHY_RFOVERVAL, backup_phy[3]); BWN_PHY_WRITE(mac, BWN_PHY_CRS0, backup_phy[0]); BWN_PHY_WRITE(mac, BWN_PHY_CCKBBANDCFG, backup_phy[1]); pg->pg_max_lb_gain = ((loop1_inner_done * 6) - (loop1_outer_done * 4)) - 11; pg->pg_trsw_rx_gain = trsw_rx * 2; } static uint16_t bwn_rf_init_bcm2050(struct bwn_mac *mac) { struct bwn_phy *phy = &mac->mac_phy; uint32_t tmp1 = 0, tmp2 = 0; uint16_t rcc, i, j, pgactl, cck0, cck1, cck2, cck3, rfover, rfoverval, analogover, analogoverval, crs0, classctl, lomask, loctl, syncctl, radio0, radio1, radio2, reg0, reg1, reg2, radio78, reg, index; static const uint8_t rcc_table[] = { 0x02, 0x03, 0x01, 0x0f, 0x06, 0x07, 0x05, 0x0f, 0x0a, 0x0b, 0x09, 0x0f, 0x0e, 0x0f, 0x0d, 0x0f, }; loctl = lomask = reg0 = classctl = crs0 = analogoverval = analogover = rfoverval = rfover = cck3 = 0; radio0 = BWN_RF_READ(mac, 0x43); radio1 = BWN_RF_READ(mac, 0x51); radio2 = BWN_RF_READ(mac, 0x52); pgactl = BWN_PHY_READ(mac, BWN_PHY_PGACTL); cck0 = BWN_PHY_READ(mac, BWN_PHY_CCK(0x5a)); cck1 = BWN_PHY_READ(mac, BWN_PHY_CCK(0x59)); cck2 = BWN_PHY_READ(mac, BWN_PHY_CCK(0x58)); if (phy->type == BWN_PHYTYPE_B) { cck3 = BWN_PHY_READ(mac, BWN_PHY_CCK(0x30)); reg0 = BWN_READ_2(mac, 0x3ec); BWN_PHY_WRITE(mac, BWN_PHY_CCK(0x30), 0xff); BWN_WRITE_2(mac, 0x3ec, 0x3f3f); } else if (phy->gmode || phy->rev >= 2) { rfover = BWN_PHY_READ(mac, BWN_PHY_RFOVER); rfoverval = BWN_PHY_READ(mac, BWN_PHY_RFOVERVAL); analogover = BWN_PHY_READ(mac, BWN_PHY_ANALOGOVER); analogoverval = BWN_PHY_READ(mac, BWN_PHY_ANALOGOVERVAL); crs0 = BWN_PHY_READ(mac, BWN_PHY_CRS0); classctl = BWN_PHY_READ(mac, BWN_PHY_CLASSCTL); BWN_PHY_SET(mac, BWN_PHY_ANALOGOVER, 0x0003); BWN_PHY_MASK(mac, BWN_PHY_ANALOGOVERVAL, 0xfffc); BWN_PHY_MASK(mac, BWN_PHY_CRS0, 0x7fff); BWN_PHY_MASK(mac, BWN_PHY_CLASSCTL, 0xfffc); if (BWN_HAS_LOOPBACK(phy)) { lomask = BWN_PHY_READ(mac, BWN_PHY_LO_MASK); loctl = BWN_PHY_READ(mac, BWN_PHY_LO_CTL); if (phy->rev >= 3) BWN_PHY_WRITE(mac, BWN_PHY_LO_MASK, 0xc020); else BWN_PHY_WRITE(mac, BWN_PHY_LO_MASK, 0x8020); BWN_PHY_WRITE(mac, BWN_PHY_LO_CTL, 0); } BWN_PHY_WRITE(mac, BWN_PHY_RFOVERVAL, bwn_rf_2050_rfoverval(mac, BWN_PHY_RFOVERVAL, BWN_LPD(0, 1, 1))); BWN_PHY_WRITE(mac, BWN_PHY_RFOVER, bwn_rf_2050_rfoverval(mac, BWN_PHY_RFOVER, 0)); } BWN_WRITE_2(mac, 0x3e2, BWN_READ_2(mac, 0x3e2) | 0x8000); syncctl = BWN_PHY_READ(mac, BWN_PHY_SYNCCTL); BWN_PHY_MASK(mac, BWN_PHY_SYNCCTL, 0xff7f); reg1 = BWN_READ_2(mac, 0x3e6); reg2 = BWN_READ_2(mac, 0x3f4); if (phy->analog == 0) BWN_WRITE_2(mac, 0x03e6, 0x0122); else { if (phy->analog >= 2) BWN_PHY_SETMASK(mac, BWN_PHY_CCK(0x03), 0xffbf, 0x40); BWN_WRITE_2(mac, BWN_CHANNEL_EXT, (BWN_READ_2(mac, BWN_CHANNEL_EXT) | 0x2000)); } reg = BWN_RF_READ(mac, 0x60); index = (reg & 0x001e) >> 1; rcc = (((rcc_table[index] << 1) | (reg & 0x0001)) | 0x0020); if (phy->type == BWN_PHYTYPE_B) BWN_RF_WRITE(mac, 0x78, 0x26); if (phy->gmode || phy->rev >= 2) { BWN_PHY_WRITE(mac, BWN_PHY_RFOVERVAL, bwn_rf_2050_rfoverval(mac, BWN_PHY_RFOVERVAL, BWN_LPD(0, 1, 1))); } BWN_PHY_WRITE(mac, BWN_PHY_PGACTL, 0xbfaf); BWN_PHY_WRITE(mac, BWN_PHY_CCK(0x2b), 0x1403); if (phy->gmode || phy->rev >= 2) { BWN_PHY_WRITE(mac, BWN_PHY_RFOVERVAL, bwn_rf_2050_rfoverval(mac, BWN_PHY_RFOVERVAL, BWN_LPD(0, 0, 1))); } BWN_PHY_WRITE(mac, BWN_PHY_PGACTL, 0xbfa0); BWN_RF_SET(mac, 0x51, 0x0004); if (phy->rf_rev == 8) BWN_RF_WRITE(mac, 0x43, 0x1f); else { BWN_RF_WRITE(mac, 0x52, 0); BWN_RF_SETMASK(mac, 0x43, 0xfff0, 0x0009); } BWN_PHY_WRITE(mac, BWN_PHY_CCK(0x58), 0); for (i = 0; i < 16; i++) { BWN_PHY_WRITE(mac, BWN_PHY_CCK(0x5a), 0x0480); BWN_PHY_WRITE(mac, BWN_PHY_CCK(0x59), 0xc810); BWN_PHY_WRITE(mac, BWN_PHY_CCK(0x58), 0x000d); if (phy->gmode || phy->rev >= 2) { BWN_PHY_WRITE(mac, BWN_PHY_RFOVERVAL, bwn_rf_2050_rfoverval(mac, BWN_PHY_RFOVERVAL, BWN_LPD(1, 0, 1))); } BWN_PHY_WRITE(mac, BWN_PHY_PGACTL, 0xafb0); DELAY(10); if (phy->gmode || phy->rev >= 2) { BWN_PHY_WRITE(mac, BWN_PHY_RFOVERVAL, bwn_rf_2050_rfoverval(mac, BWN_PHY_RFOVERVAL, BWN_LPD(1, 0, 1))); } BWN_PHY_WRITE(mac, BWN_PHY_PGACTL, 0xefb0); DELAY(10); if (phy->gmode || phy->rev >= 2) { BWN_PHY_WRITE(mac, BWN_PHY_RFOVERVAL, bwn_rf_2050_rfoverval(mac, BWN_PHY_RFOVERVAL, BWN_LPD(1, 0, 0))); } BWN_PHY_WRITE(mac, BWN_PHY_PGACTL, 0xfff0); DELAY(20); tmp1 += BWN_PHY_READ(mac, BWN_PHY_LO_LEAKAGE); BWN_PHY_WRITE(mac, BWN_PHY_CCK(0x58), 0); if (phy->gmode || phy->rev >= 2) { BWN_PHY_WRITE(mac, BWN_PHY_RFOVERVAL, bwn_rf_2050_rfoverval(mac, BWN_PHY_RFOVERVAL, BWN_LPD(1, 0, 1))); } BWN_PHY_WRITE(mac, BWN_PHY_PGACTL, 0xafb0); } DELAY(10); BWN_PHY_WRITE(mac, BWN_PHY_CCK(0x58), 0); tmp1++; tmp1 >>= 9; for (i = 0; i < 16; i++) { radio78 = (BWN_BITREV4(i) << 1) | 0x0020; BWN_RF_WRITE(mac, 0x78, radio78); DELAY(10); for (j = 0; j < 16; j++) { BWN_PHY_WRITE(mac, BWN_PHY_CCK(0x5a), 0x0d80); BWN_PHY_WRITE(mac, BWN_PHY_CCK(0x59), 0xc810); BWN_PHY_WRITE(mac, BWN_PHY_CCK(0x58), 0x000d); if (phy->gmode || phy->rev >= 2) { BWN_PHY_WRITE(mac, BWN_PHY_RFOVERVAL, bwn_rf_2050_rfoverval(mac, BWN_PHY_RFOVERVAL, BWN_LPD(1, 0, 1))); } BWN_PHY_WRITE(mac, BWN_PHY_PGACTL, 0xafb0); DELAY(10); if (phy->gmode || phy->rev >= 2) { BWN_PHY_WRITE(mac, BWN_PHY_RFOVERVAL, bwn_rf_2050_rfoverval(mac, BWN_PHY_RFOVERVAL, BWN_LPD(1, 0, 1))); } BWN_PHY_WRITE(mac, BWN_PHY_PGACTL, 0xefb0); DELAY(10); if (phy->gmode || phy->rev >= 2) { BWN_PHY_WRITE(mac, BWN_PHY_RFOVERVAL, bwn_rf_2050_rfoverval(mac, BWN_PHY_RFOVERVAL, BWN_LPD(1, 0, 0))); } BWN_PHY_WRITE(mac, BWN_PHY_PGACTL, 0xfff0); DELAY(10); tmp2 += BWN_PHY_READ(mac, BWN_PHY_LO_LEAKAGE); BWN_PHY_WRITE(mac, BWN_PHY_CCK(0x58), 0); if (phy->gmode || phy->rev >= 2) { BWN_PHY_WRITE(mac, BWN_PHY_RFOVERVAL, bwn_rf_2050_rfoverval(mac, BWN_PHY_RFOVERVAL, BWN_LPD(1, 0, 1))); } BWN_PHY_WRITE(mac, BWN_PHY_PGACTL, 0xafb0); } tmp2++; tmp2 >>= 8; if (tmp1 < tmp2) break; } BWN_PHY_WRITE(mac, BWN_PHY_PGACTL, pgactl); BWN_RF_WRITE(mac, 0x51, radio1); BWN_RF_WRITE(mac, 0x52, radio2); BWN_RF_WRITE(mac, 0x43, radio0); BWN_PHY_WRITE(mac, BWN_PHY_CCK(0x5a), cck0); BWN_PHY_WRITE(mac, BWN_PHY_CCK(0x59), cck1); BWN_PHY_WRITE(mac, BWN_PHY_CCK(0x58), cck2); BWN_WRITE_2(mac, 0x3e6, reg1); if (phy->analog != 0) BWN_WRITE_2(mac, 0x3f4, reg2); BWN_PHY_WRITE(mac, BWN_PHY_SYNCCTL, syncctl); bwn_spu_workaround(mac, phy->chan); if (phy->type == BWN_PHYTYPE_B) { BWN_PHY_WRITE(mac, BWN_PHY_CCK(0x30), cck3); BWN_WRITE_2(mac, 0x3ec, reg0); } else if (phy->gmode) { BWN_WRITE_2(mac, BWN_PHY_RADIO, BWN_READ_2(mac, BWN_PHY_RADIO) & 0x7fff); BWN_PHY_WRITE(mac, BWN_PHY_RFOVER, rfover); BWN_PHY_WRITE(mac, BWN_PHY_RFOVERVAL, rfoverval); BWN_PHY_WRITE(mac, BWN_PHY_ANALOGOVER, analogover); BWN_PHY_WRITE(mac, BWN_PHY_ANALOGOVERVAL, analogoverval); BWN_PHY_WRITE(mac, BWN_PHY_CRS0, crs0); BWN_PHY_WRITE(mac, BWN_PHY_CLASSCTL, classctl); if (BWN_HAS_LOOPBACK(phy)) { BWN_PHY_WRITE(mac, BWN_PHY_LO_MASK, lomask); BWN_PHY_WRITE(mac, BWN_PHY_LO_CTL, loctl); } } return ((i > 15) ? radio78 : rcc); } static void bwn_phy_init_b6(struct bwn_mac *mac) { struct bwn_phy *phy = &mac->mac_phy; struct bwn_phy_g *pg = &phy->phy_g; struct bwn_softc *sc = mac->mac_sc; uint16_t offset, val; uint8_t old_channel; KASSERT(!(phy->rf_rev == 6 || phy->rf_rev == 7), ("%s:%d: fail", __func__, __LINE__)); BWN_PHY_WRITE(mac, 0x003e, 0x817a); BWN_RF_WRITE(mac, 0x007a, BWN_RF_READ(mac, 0x007a) | 0x0058); if (phy->rf_rev == 4 || phy->rf_rev == 5) { BWN_RF_WRITE(mac, 0x51, 0x37); BWN_RF_WRITE(mac, 0x52, 0x70); BWN_RF_WRITE(mac, 0x53, 0xb3); BWN_RF_WRITE(mac, 0x54, 0x9b); BWN_RF_WRITE(mac, 0x5a, 0x88); BWN_RF_WRITE(mac, 0x5b, 0x88); BWN_RF_WRITE(mac, 0x5d, 0x88); BWN_RF_WRITE(mac, 0x5e, 0x88); BWN_RF_WRITE(mac, 0x7d, 0x88); bwn_hf_write(mac, bwn_hf_read(mac) | BWN_HF_TSSI_RESET_PSM_WORKAROUN); } if (phy->rf_rev == 8) { BWN_RF_WRITE(mac, 0x51, 0); BWN_RF_WRITE(mac, 0x52, 0x40); BWN_RF_WRITE(mac, 0x53, 0xb7); BWN_RF_WRITE(mac, 0x54, 0x98); BWN_RF_WRITE(mac, 0x5a, 0x88); BWN_RF_WRITE(mac, 0x5b, 0x6b); BWN_RF_WRITE(mac, 0x5c, 0x0f); - if (siba_sprom_get_bf_lo(sc->sc_dev) & BWN_BFL_ALTIQ) { + if (sc->sc_board_info.board_flags & BHND_BFL_ALTIQ) { BWN_RF_WRITE(mac, 0x5d, 0xfa); BWN_RF_WRITE(mac, 0x5e, 0xd8); } else { BWN_RF_WRITE(mac, 0x5d, 0xf5); BWN_RF_WRITE(mac, 0x5e, 0xb8); } BWN_RF_WRITE(mac, 0x0073, 0x0003); BWN_RF_WRITE(mac, 0x007d, 0x00a8); BWN_RF_WRITE(mac, 0x007c, 0x0001); BWN_RF_WRITE(mac, 0x007e, 0x0008); } for (val = 0x1e1f, offset = 0x0088; offset < 0x0098; offset++) { BWN_PHY_WRITE(mac, offset, val); val -= 0x0202; } for (val = 0x3e3f, offset = 0x0098; offset < 0x00a8; offset++) { BWN_PHY_WRITE(mac, offset, val); val -= 0x0202; } for (val = 0x2120, offset = 0x00a8; offset < 0x00c8; offset++) { BWN_PHY_WRITE(mac, offset, (val & 0x3f3f)); val += 0x0202; } if (phy->type == BWN_PHYTYPE_G) { BWN_RF_SET(mac, 0x007a, 0x0020); BWN_RF_SET(mac, 0x0051, 0x0004); BWN_PHY_SET(mac, 0x0802, 0x0100); BWN_PHY_SET(mac, 0x042b, 0x2000); BWN_PHY_WRITE(mac, 0x5b, 0); BWN_PHY_WRITE(mac, 0x5c, 0); } old_channel = phy->chan; bwn_phy_g_switch_chan(mac, (old_channel >= 8) ? 1 : 13, 0); BWN_RF_WRITE(mac, 0x0050, 0x0020); BWN_RF_WRITE(mac, 0x0050, 0x0023); DELAY(40); if (phy->rf_rev < 6 || phy->rf_rev == 8) { BWN_RF_WRITE(mac, 0x7c, BWN_RF_READ(mac, 0x7c) | 0x0002); BWN_RF_WRITE(mac, 0x50, 0x20); } if (phy->rf_rev <= 2) { BWN_RF_WRITE(mac, 0x7c, 0x20); BWN_RF_WRITE(mac, 0x5a, 0x70); BWN_RF_WRITE(mac, 0x5b, 0x7b); BWN_RF_WRITE(mac, 0x5c, 0xb0); } BWN_RF_SETMASK(mac, 0x007a, 0x00f8, 0x0007); bwn_phy_g_switch_chan(mac, old_channel, 0); BWN_PHY_WRITE(mac, 0x0014, 0x0200); if (phy->rf_rev >= 6) BWN_PHY_WRITE(mac, 0x2a, 0x88c2); else BWN_PHY_WRITE(mac, 0x2a, 0x8ac0); BWN_PHY_WRITE(mac, 0x0038, 0x0668); bwn_phy_g_set_txpwr_sub(mac, &pg->pg_bbatt, &pg->pg_rfatt, pg->pg_txctl); if (phy->rf_rev <= 5) BWN_PHY_SETMASK(mac, 0x5d, 0xff80, 0x0003); if (phy->rf_rev <= 2) BWN_RF_WRITE(mac, 0x005d, 0x000d); if (phy->analog == 4) { BWN_WRITE_2(mac, 0x3e4, 9); BWN_PHY_MASK(mac, 0x61, 0x0fff); } else BWN_PHY_SETMASK(mac, 0x0002, 0xffc0, 0x0004); if (phy->type == BWN_PHYTYPE_B) KASSERT(0 == 1, ("%s:%d: fail", __func__, __LINE__)); else if (phy->type == BWN_PHYTYPE_G) BWN_WRITE_2(mac, 0x03e6, 0x0); } static void bwn_phy_init_a(struct bwn_mac *mac) { struct bwn_phy *phy = &mac->mac_phy; struct bwn_softc *sc = mac->mac_sc; KASSERT(phy->type == BWN_PHYTYPE_A || phy->type == BWN_PHYTYPE_G, ("%s:%d: fail", __func__, __LINE__)); if (phy->rev >= 6) { if (phy->type == BWN_PHYTYPE_A) BWN_PHY_MASK(mac, BWN_PHY_OFDM(0x1b), ~0x1000); if (BWN_PHY_READ(mac, BWN_PHY_ENCORE) & BWN_PHY_ENCORE_EN) BWN_PHY_SET(mac, BWN_PHY_ENCORE, 0x0010); else BWN_PHY_MASK(mac, BWN_PHY_ENCORE, ~0x1010); } bwn_wa_init(mac); if (phy->type == BWN_PHYTYPE_G && - (siba_sprom_get_bf_lo(sc->sc_dev) & BWN_BFL_PACTRL)) + (sc->sc_board_info.board_flags & BHND_BFL_PACTRL)) BWN_PHY_SETMASK(mac, BWN_PHY_OFDM(0x6e), 0xe000, 0x3cf); } static void bwn_wa_write_noisescale(struct bwn_mac *mac, const uint16_t *nst) { int i; for (i = 0; i < BWN_TAB_NOISESCALE_SIZE; i++) bwn_ofdmtab_write_2(mac, BWN_OFDMTAB_NOISESCALE, i, nst[i]); } static void bwn_wa_agc(struct bwn_mac *mac) { struct bwn_phy *phy = &mac->mac_phy; if (phy->rev == 1) { bwn_ofdmtab_write_2(mac, BWN_OFDMTAB_AGC1_R1, 0, 254); bwn_ofdmtab_write_2(mac, BWN_OFDMTAB_AGC1_R1, 1, 13); bwn_ofdmtab_write_2(mac, BWN_OFDMTAB_AGC1_R1, 2, 19); bwn_ofdmtab_write_2(mac, BWN_OFDMTAB_AGC1_R1, 3, 25); bwn_ofdmtab_write_2(mac, BWN_OFDMTAB_AGC2, 0, 0x2710); bwn_ofdmtab_write_2(mac, BWN_OFDMTAB_AGC2, 1, 0x9b83); bwn_ofdmtab_write_2(mac, BWN_OFDMTAB_AGC2, 2, 0x9b83); bwn_ofdmtab_write_2(mac, BWN_OFDMTAB_AGC2, 3, 0x0f8d); BWN_PHY_WRITE(mac, BWN_PHY_LMS, 4); } else { bwn_ofdmtab_write_2(mac, BWN_OFDMTAB_AGC1, 0, 254); bwn_ofdmtab_write_2(mac, BWN_OFDMTAB_AGC1, 1, 13); bwn_ofdmtab_write_2(mac, BWN_OFDMTAB_AGC1, 2, 19); bwn_ofdmtab_write_2(mac, BWN_OFDMTAB_AGC1, 3, 25); } BWN_PHY_SETMASK(mac, BWN_PHY_CCKSHIFTBITS_WA, (uint16_t)~0xff00, 0x5700); BWN_PHY_SETMASK(mac, BWN_PHY_OFDM(0x1a), ~0x007f, 0x000f); BWN_PHY_SETMASK(mac, BWN_PHY_OFDM(0x1a), ~0x3f80, 0x2b80); BWN_PHY_SETMASK(mac, BWN_PHY_ANTWRSETT, 0xf0ff, 0x0300); BWN_RF_SET(mac, 0x7a, 0x0008); BWN_PHY_SETMASK(mac, BWN_PHY_N1P1GAIN, ~0x000f, 0x0008); BWN_PHY_SETMASK(mac, BWN_PHY_P1P2GAIN, ~0x0f00, 0x0600); BWN_PHY_SETMASK(mac, BWN_PHY_N1N2GAIN, ~0x0f00, 0x0700); BWN_PHY_SETMASK(mac, BWN_PHY_N1P1GAIN, ~0x0f00, 0x0100); if (phy->rev == 1) BWN_PHY_SETMASK(mac, BWN_PHY_N1N2GAIN, ~0x000f, 0x0007); BWN_PHY_SETMASK(mac, BWN_PHY_OFDM(0x88), ~0x00ff, 0x001c); BWN_PHY_SETMASK(mac, BWN_PHY_OFDM(0x88), ~0x3f00, 0x0200); BWN_PHY_SETMASK(mac, BWN_PHY_OFDM(0x96), ~0x00ff, 0x001c); BWN_PHY_SETMASK(mac, BWN_PHY_OFDM(0x89), ~0x00ff, 0x0020); BWN_PHY_SETMASK(mac, BWN_PHY_OFDM(0x89), ~0x3f00, 0x0200); BWN_PHY_SETMASK(mac, BWN_PHY_OFDM(0x82), ~0x00ff, 0x002e); BWN_PHY_SETMASK(mac, BWN_PHY_OFDM(0x96), (uint16_t)~0xff00, 0x1a00); BWN_PHY_SETMASK(mac, BWN_PHY_OFDM(0x81), ~0x00ff, 0x0028); BWN_PHY_SETMASK(mac, BWN_PHY_OFDM(0x81), (uint16_t)~0xff00, 0x2c00); if (phy->rev == 1) { BWN_PHY_WRITE(mac, BWN_PHY_PEAK_COUNT, 0x092b); BWN_PHY_SETMASK(mac, BWN_PHY_OFDM(0x1b), ~0x001e, 0x0002); } else { BWN_PHY_MASK(mac, BWN_PHY_OFDM(0x1b), ~0x001e); BWN_PHY_WRITE(mac, BWN_PHY_OFDM(0x1f), 0x287a); BWN_PHY_SETMASK(mac, BWN_PHY_LPFGAINCTL, ~0x000f, 0x0004); if (phy->rev >= 6) { BWN_PHY_WRITE(mac, BWN_PHY_OFDM(0x22), 0x287a); BWN_PHY_SETMASK(mac, BWN_PHY_LPFGAINCTL, (uint16_t)~0xf000, 0x3000); } } BWN_PHY_SETMASK(mac, BWN_PHY_DIVSRCHIDX, 0x8080, 0x7874); BWN_PHY_WRITE(mac, BWN_PHY_OFDM(0x8e), 0x1c00); if (phy->rev == 1) { BWN_PHY_SETMASK(mac, BWN_PHY_DIVP1P2GAIN, ~0x0f00, 0x0600); BWN_PHY_WRITE(mac, BWN_PHY_OFDM(0x8b), 0x005e); BWN_PHY_SETMASK(mac, BWN_PHY_ANTWRSETT, ~0x00ff, 0x001e); BWN_PHY_WRITE(mac, BWN_PHY_OFDM(0x8d), 0x0002); bwn_ofdmtab_write_2(mac, BWN_OFDMTAB_AGC3_R1, 0, 0); bwn_ofdmtab_write_2(mac, BWN_OFDMTAB_AGC3_R1, 1, 7); bwn_ofdmtab_write_2(mac, BWN_OFDMTAB_AGC3_R1, 2, 16); bwn_ofdmtab_write_2(mac, BWN_OFDMTAB_AGC3_R1, 3, 28); } else { bwn_ofdmtab_write_2(mac, BWN_OFDMTAB_AGC3, 0, 0); bwn_ofdmtab_write_2(mac, BWN_OFDMTAB_AGC3, 1, 7); bwn_ofdmtab_write_2(mac, BWN_OFDMTAB_AGC3, 2, 16); bwn_ofdmtab_write_2(mac, BWN_OFDMTAB_AGC3, 3, 28); } if (phy->rev >= 6) { BWN_PHY_MASK(mac, BWN_PHY_OFDM(0x26), ~0x0003); BWN_PHY_MASK(mac, BWN_PHY_OFDM(0x26), ~0x1000); } BWN_PHY_READ(mac, BWN_PHY_VERSION_OFDM); } static void bwn_wa_grev1(struct bwn_mac *mac) { struct bwn_phy *phy = &mac->mac_phy; int i; static const uint16_t bwn_tab_finefreqg[] = BWN_TAB_FINEFREQ_G; static const uint32_t bwn_tab_retard[] = BWN_TAB_RETARD; static const uint32_t bwn_tab_rotor[] = BWN_TAB_ROTOR; KASSERT(phy->type == BWN_PHYTYPE_G, ("%s fail", __func__)); /* init CRSTHRES and ANTDWELL */ if (phy->rev == 1) { BWN_PHY_WRITE(mac, BWN_PHY_CRSTHRES1_R1, 0x4f19); } else if (phy->rev == 2) { BWN_PHY_WRITE(mac, BWN_PHY_CRSTHRES1, 0x1861); BWN_PHY_WRITE(mac, BWN_PHY_CRSTHRES2, 0x0271); BWN_PHY_SET(mac, BWN_PHY_ANTDWELL, 0x0800); } else { BWN_PHY_WRITE(mac, BWN_PHY_CRSTHRES1, 0x0098); BWN_PHY_WRITE(mac, BWN_PHY_CRSTHRES2, 0x0070); BWN_PHY_WRITE(mac, BWN_PHY_OFDM(0xc9), 0x0080); BWN_PHY_SET(mac, BWN_PHY_ANTDWELL, 0x0800); } BWN_PHY_SETMASK(mac, BWN_PHY_CRS0, ~0x03c0, 0xd000); BWN_PHY_WRITE(mac, BWN_PHY_OFDM(0x2c), 0x005a); BWN_PHY_WRITE(mac, BWN_PHY_CCKSHIFTBITS, 0x0026); /* XXX support PHY-A??? */ for (i = 0; i < N(bwn_tab_finefreqg); i++) bwn_ofdmtab_write_2(mac, BWN_OFDMTAB_DACRFPABB, i, bwn_tab_finefreqg[i]); /* XXX support PHY-A??? */ if (phy->rev == 1) for (i = 0; i < N(bwn_tab_noise_g1); i++) bwn_ofdmtab_write_2(mac, BWN_OFDMTAB_AGC2, i, bwn_tab_noise_g1[i]); else for (i = 0; i < N(bwn_tab_noise_g2); i++) bwn_ofdmtab_write_2(mac, BWN_OFDMTAB_AGC2, i, bwn_tab_noise_g2[i]); for (i = 0; i < N(bwn_tab_rotor); i++) bwn_ofdmtab_write_4(mac, BWN_OFDMTAB_ROTOR, i, bwn_tab_rotor[i]); /* XXX support PHY-A??? */ if (phy->rev >= 6) { if (BWN_PHY_READ(mac, BWN_PHY_ENCORE) & BWN_PHY_ENCORE_EN) bwn_wa_write_noisescale(mac, bwn_tab_noisescale_g3); else bwn_wa_write_noisescale(mac, bwn_tab_noisescale_g2); } else bwn_wa_write_noisescale(mac, bwn_tab_noisescale_g1); for (i = 0; i < N(bwn_tab_retard); i++) bwn_ofdmtab_write_4(mac, BWN_OFDMTAB_ADVRETARD, i, bwn_tab_retard[i]); if (phy->rev == 1) { for (i = 0; i < 16; i++) bwn_ofdmtab_write_2(mac, BWN_OFDMTAB_WRSSI_R1, i, 0x0020); } else { for (i = 0; i < 32; i++) bwn_ofdmtab_write_2(mac, BWN_OFDMTAB_WRSSI, i, 0x0820); } bwn_wa_agc(mac); } static void bwn_wa_grev26789(struct bwn_mac *mac) { struct bwn_phy *phy = &mac->mac_phy; int i; static const uint16_t bwn_tab_sigmasqr2[] = BWN_TAB_SIGMASQR2; uint16_t ofdmrev; KASSERT(phy->type == BWN_PHYTYPE_G, ("%s fail", __func__)); bwn_gtab_write(mac, BWN_GTAB_ORIGTR, 0, 0xc480); /* init CRSTHRES and ANTDWELL */ if (phy->rev == 1) BWN_PHY_WRITE(mac, BWN_PHY_CRSTHRES1_R1, 0x4f19); else if (phy->rev == 2) { BWN_PHY_WRITE(mac, BWN_PHY_CRSTHRES1, 0x1861); BWN_PHY_WRITE(mac, BWN_PHY_CRSTHRES2, 0x0271); BWN_PHY_SET(mac, BWN_PHY_ANTDWELL, 0x0800); } else { BWN_PHY_WRITE(mac, BWN_PHY_CRSTHRES1, 0x0098); BWN_PHY_WRITE(mac, BWN_PHY_CRSTHRES2, 0x0070); BWN_PHY_WRITE(mac, BWN_PHY_OFDM(0xc9), 0x0080); BWN_PHY_SET(mac, BWN_PHY_ANTDWELL, 0x0800); } for (i = 0; i < 64; i++) bwn_ofdmtab_write_2(mac, BWN_OFDMTAB_RSSI, i, i); /* XXX support PHY-A??? */ if (phy->rev == 1) for (i = 0; i < N(bwn_tab_noise_g1); i++) bwn_ofdmtab_write_2(mac, BWN_OFDMTAB_AGC2, i, bwn_tab_noise_g1[i]); else for (i = 0; i < N(bwn_tab_noise_g2); i++) bwn_ofdmtab_write_2(mac, BWN_OFDMTAB_AGC2, i, bwn_tab_noise_g2[i]); /* XXX support PHY-A??? */ if (phy->rev >= 6) { if (BWN_PHY_READ(mac, BWN_PHY_ENCORE) & BWN_PHY_ENCORE_EN) bwn_wa_write_noisescale(mac, bwn_tab_noisescale_g3); else bwn_wa_write_noisescale(mac, bwn_tab_noisescale_g2); } else bwn_wa_write_noisescale(mac, bwn_tab_noisescale_g1); for (i = 0; i < N(bwn_tab_sigmasqr2); i++) bwn_ofdmtab_write_2(mac, BWN_OFDMTAB_MINSIGSQ, i, bwn_tab_sigmasqr2[i]); if (phy->rev == 1) { for (i = 0; i < 16; i++) bwn_ofdmtab_write_2(mac, BWN_OFDMTAB_WRSSI_R1, i, 0x0020); } else { for (i = 0; i < 32; i++) bwn_ofdmtab_write_2(mac, BWN_OFDMTAB_WRSSI, i, 0x0820); } bwn_wa_agc(mac); ofdmrev = BWN_PHY_READ(mac, BWN_PHY_VERSION_OFDM) & BWN_PHYVER_VERSION; if (ofdmrev > 2) { if (phy->type == BWN_PHYTYPE_A) BWN_PHY_WRITE(mac, BWN_PHY_PWRDOWN, 0x1808); else BWN_PHY_WRITE(mac, BWN_PHY_PWRDOWN, 0x1000); } else { bwn_ofdmtab_write_2(mac, BWN_OFDMTAB_DAC, 3, 0x1044); bwn_ofdmtab_write_2(mac, BWN_OFDMTAB_DAC, 4, 0x7201); bwn_ofdmtab_write_2(mac, BWN_OFDMTAB_DAC, 6, 0x0040); } bwn_ofdmtab_write_2(mac, BWN_OFDMTAB_UNKNOWN_0F, 2, 15); bwn_ofdmtab_write_2(mac, BWN_OFDMTAB_UNKNOWN_0F, 3, 20); } static void bwn_wa_init(struct bwn_mac *mac) { struct bwn_phy *phy = &mac->mac_phy; struct bwn_softc *sc = mac->mac_sc; KASSERT(phy->type == BWN_PHYTYPE_G, ("%s fail", __func__)); switch (phy->rev) { case 1: bwn_wa_grev1(mac); break; case 2: case 6: case 7: case 8: case 9: bwn_wa_grev26789(mac); break; default: KASSERT(0 == 1, ("%s:%d: fail", __func__, __LINE__)); } - if (siba_get_pci_subvendor(sc->sc_dev) != SIBA_BOARDVENDOR_BCM || - siba_get_pci_subdevice(sc->sc_dev) != SIBA_BOARD_BU4306 || - siba_get_pci_revid(sc->sc_dev) != 0x17) { + if (sc->sc_board_info.board_vendor != PCI_VENDOR_BROADCOM || + sc->sc_board_info.board_type != BHND_BOARD_BU4306 || + sc->sc_board_info.board_rev != 0x17) { if (phy->rev < 2) { bwn_ofdmtab_write_2(mac, BWN_OFDMTAB_GAINX_R1, 1, 0x0002); bwn_ofdmtab_write_2(mac, BWN_OFDMTAB_GAINX_R1, 2, 0x0001); } else { bwn_ofdmtab_write_2(mac, BWN_OFDMTAB_GAINX, 1, 0x0002); bwn_ofdmtab_write_2(mac, BWN_OFDMTAB_GAINX, 2, 0x0001); - if ((siba_sprom_get_bf_lo(sc->sc_dev) & - BWN_BFL_EXTLNA) && + if ((sc->sc_board_info.board_flags & + BHND_BFL_EXTLNA) && (phy->rev >= 7)) { BWN_PHY_MASK(mac, BWN_PHY_EXTG(0x11), 0xf7ff); bwn_ofdmtab_write_2(mac, BWN_OFDMTAB_GAINX, 0x0020, 0x0001); bwn_ofdmtab_write_2(mac, BWN_OFDMTAB_GAINX, 0x0021, 0x0001); bwn_ofdmtab_write_2(mac, BWN_OFDMTAB_GAINX, 0x0022, 0x0001); bwn_ofdmtab_write_2(mac, BWN_OFDMTAB_GAINX, 0x0023, 0x0000); bwn_ofdmtab_write_2(mac, BWN_OFDMTAB_GAINX, 0x0000, 0x0000); bwn_ofdmtab_write_2(mac, BWN_OFDMTAB_GAINX, 0x0003, 0x0002); } } } - if (siba_sprom_get_bf_lo(sc->sc_dev) & BWN_BFL_FEM) { + if (sc->sc_board_info.board_flags & BHND_BFL_FEM) { BWN_PHY_WRITE(mac, BWN_PHY_GTABCTL, 0x3120); BWN_PHY_WRITE(mac, BWN_PHY_GTABDATA, 0xc480); } bwn_ofdmtab_write_2(mac, BWN_OFDMTAB_UNKNOWN_11, 0, 0); bwn_ofdmtab_write_2(mac, BWN_OFDMTAB_UNKNOWN_11, 1, 0); } static void bwn_ofdmtab_write_2(struct bwn_mac *mac, uint16_t table, uint16_t offset, uint16_t value) { struct bwn_phy_g *pg = &mac->mac_phy.phy_g; uint16_t addr; addr = table + offset; if ((pg->pg_ofdmtab_dir != BWN_OFDMTAB_DIR_WRITE) || (addr - 1 != pg->pg_ofdmtab_addr)) { BWN_PHY_WRITE(mac, BWN_PHY_OTABLECTL, addr); pg->pg_ofdmtab_dir = BWN_OFDMTAB_DIR_WRITE; } pg->pg_ofdmtab_addr = addr; BWN_PHY_WRITE(mac, BWN_PHY_OTABLEI, value); } static void bwn_ofdmtab_write_4(struct bwn_mac *mac, uint16_t table, uint16_t offset, uint32_t value) { struct bwn_phy_g *pg = &mac->mac_phy.phy_g; uint16_t addr; addr = table + offset; if ((pg->pg_ofdmtab_dir != BWN_OFDMTAB_DIR_WRITE) || (addr - 1 != pg->pg_ofdmtab_addr)) { BWN_PHY_WRITE(mac, BWN_PHY_OTABLECTL, addr); pg->pg_ofdmtab_dir = BWN_OFDMTAB_DIR_WRITE; } pg->pg_ofdmtab_addr = addr; BWN_PHY_WRITE(mac, BWN_PHY_OTABLEI, value); BWN_PHY_WRITE(mac, BWN_PHY_OTABLEQ, (value >> 16)); } static void bwn_gtab_write(struct bwn_mac *mac, uint16_t table, uint16_t offset, uint16_t value) { BWN_PHY_WRITE(mac, BWN_PHY_GTABCTL, table + offset); BWN_PHY_WRITE(mac, BWN_PHY_GTABDATA, value); } static void bwn_lo_write(struct bwn_mac *mac, struct bwn_loctl *ctl) { uint16_t value; KASSERT(mac->mac_phy.type == BWN_PHYTYPE_G, ("%s:%d: fail", __func__, __LINE__)); value = (uint8_t) (ctl->q); value |= ((uint8_t) (ctl->i)) << 8; BWN_PHY_WRITE(mac, BWN_PHY_LO_CTL, value); } static uint16_t bwn_lo_calcfeed(struct bwn_mac *mac, uint16_t lna, uint16_t pga, uint16_t trsw_rx) { struct bwn_phy *phy = &mac->mac_phy; struct bwn_softc *sc = mac->mac_sc; uint16_t rfover; uint16_t feedthrough; if (phy->gmode) { lna <<= BWN_PHY_RFOVERVAL_LNA_SHIFT; pga <<= BWN_PHY_RFOVERVAL_PGA_SHIFT; KASSERT((lna & ~BWN_PHY_RFOVERVAL_LNA) == 0, ("%s:%d: fail", __func__, __LINE__)); KASSERT((pga & ~BWN_PHY_RFOVERVAL_PGA) == 0, ("%s:%d: fail", __func__, __LINE__)); trsw_rx &= (BWN_PHY_RFOVERVAL_TRSWRX | BWN_PHY_RFOVERVAL_BW); rfover = BWN_PHY_RFOVERVAL_UNK | pga | lna | trsw_rx; - if ((siba_sprom_get_bf_lo(sc->sc_dev) & BWN_BFL_EXTLNA) && + if ((sc->sc_board_info.board_flags & BHND_BFL_EXTLNA) && phy->rev > 6) rfover |= BWN_PHY_RFOVERVAL_EXTLNA; BWN_PHY_WRITE(mac, BWN_PHY_PGACTL, 0xe300); BWN_PHY_WRITE(mac, BWN_PHY_RFOVERVAL, rfover); DELAY(10); rfover |= BWN_PHY_RFOVERVAL_BW_LBW; BWN_PHY_WRITE(mac, BWN_PHY_RFOVERVAL, rfover); DELAY(10); rfover |= BWN_PHY_RFOVERVAL_BW_LPF; BWN_PHY_WRITE(mac, BWN_PHY_RFOVERVAL, rfover); DELAY(10); BWN_PHY_WRITE(mac, BWN_PHY_PGACTL, 0xf300); } else { pga |= BWN_PHY_PGACTL_UNKNOWN; BWN_PHY_WRITE(mac, BWN_PHY_PGACTL, pga); DELAY(10); pga |= BWN_PHY_PGACTL_LOWBANDW; BWN_PHY_WRITE(mac, BWN_PHY_PGACTL, pga); DELAY(10); pga |= BWN_PHY_PGACTL_LPF; BWN_PHY_WRITE(mac, BWN_PHY_PGACTL, pga); } DELAY(21); feedthrough = BWN_PHY_READ(mac, BWN_PHY_LO_LEAKAGE); return (feedthrough); } static uint16_t bwn_lo_txctl_regtable(struct bwn_mac *mac, uint16_t *value, uint16_t *pad_mix_gain) { struct bwn_phy *phy = &mac->mac_phy; uint16_t reg, v, padmix; if (phy->type == BWN_PHYTYPE_B) { v = 0x30; if (phy->rf_rev <= 5) { reg = 0x43; padmix = 0; } else { reg = 0x52; padmix = 5; } } else { if (phy->rev >= 2 && phy->rf_rev == 8) { reg = 0x43; v = 0x10; padmix = 2; } else { reg = 0x52; v = 0x30; padmix = 5; } } if (value) *value = v; if (pad_mix_gain) *pad_mix_gain = padmix; return (reg); } static void bwn_lo_measure_txctl_values(struct bwn_mac *mac) { struct bwn_phy *phy = &mac->mac_phy; struct bwn_phy_g *pg = &phy->phy_g; struct bwn_txpwr_loctl *lo = &pg->pg_loctl; uint16_t reg, mask; uint16_t trsw_rx, pga; uint16_t rf_pctl_reg; static const uint8_t tx_bias_values[] = { 0x09, 0x08, 0x0a, 0x01, 0x00, 0x02, 0x05, 0x04, 0x06, }; static const uint8_t tx_magn_values[] = { 0x70, 0x40, }; if (!BWN_HAS_LOOPBACK(phy)) { rf_pctl_reg = 6; trsw_rx = 2; pga = 0; } else { int lb_gain; trsw_rx = 0; lb_gain = pg->pg_max_lb_gain / 2; if (lb_gain > 10) { rf_pctl_reg = 0; pga = abs(10 - lb_gain) / 6; pga = MIN(MAX(pga, 0), 15); } else { int cmp_val; int tmp; pga = 0; cmp_val = 0x24; if ((phy->rev >= 2) && (phy->rf_ver == 0x2050) && (phy->rf_rev == 8)) cmp_val = 0x3c; tmp = lb_gain; if ((10 - lb_gain) < cmp_val) tmp = (10 - lb_gain); if (tmp < 0) tmp += 6; else tmp += 3; cmp_val /= 4; tmp /= 4; if (tmp >= cmp_val) rf_pctl_reg = cmp_val; else rf_pctl_reg = tmp; } } BWN_RF_SETMASK(mac, 0x43, 0xfff0, rf_pctl_reg); bwn_phy_g_set_bbatt(mac, 2); reg = bwn_lo_txctl_regtable(mac, &mask, NULL); mask = ~mask; BWN_RF_MASK(mac, reg, mask); if (BWN_HAS_TXMAG(phy)) { int i, j; int feedthrough; int min_feedth = 0xffff; uint8_t tx_magn, tx_bias; for (i = 0; i < N(tx_magn_values); i++) { tx_magn = tx_magn_values[i]; BWN_RF_SETMASK(mac, 0x52, 0xff0f, tx_magn); for (j = 0; j < N(tx_bias_values); j++) { tx_bias = tx_bias_values[j]; BWN_RF_SETMASK(mac, 0x52, 0xfff0, tx_bias); feedthrough = bwn_lo_calcfeed(mac, 0, pga, trsw_rx); if (feedthrough < min_feedth) { lo->tx_bias = tx_bias; lo->tx_magn = tx_magn; min_feedth = feedthrough; } if (lo->tx_bias == 0) break; } BWN_RF_WRITE(mac, 0x52, (BWN_RF_READ(mac, 0x52) & 0xff00) | lo->tx_bias | lo-> tx_magn); } } else { lo->tx_magn = 0; lo->tx_bias = 0; BWN_RF_MASK(mac, 0x52, 0xfff0); } BWN_GETTIME(lo->txctl_measured_time); } static void bwn_lo_get_powervector(struct bwn_mac *mac) { struct bwn_phy *phy = &mac->mac_phy; struct bwn_phy_g *pg = &phy->phy_g; struct bwn_txpwr_loctl *lo = &pg->pg_loctl; int i; uint64_t tmp; uint64_t power_vector = 0; for (i = 0; i < 8; i += 2) { tmp = bwn_shm_read_2(mac, BWN_SHARED, 0x310 + i); power_vector |= (tmp << (i * 8)); bwn_shm_write_2(mac, BWN_SHARED, 0x310 + i, 0); } if (power_vector) lo->power_vector = power_vector; BWN_GETTIME(lo->pwr_vec_read_time); } static void bwn_lo_measure_gain_values(struct bwn_mac *mac, int16_t max_rx_gain, int use_trsw_rx) { struct bwn_phy *phy = &mac->mac_phy; struct bwn_phy_g *pg = &phy->phy_g; uint16_t tmp; if (max_rx_gain < 0) max_rx_gain = 0; if (BWN_HAS_LOOPBACK(phy)) { int trsw_rx = 0; int trsw_rx_gain; if (use_trsw_rx) { trsw_rx_gain = pg->pg_trsw_rx_gain / 2; if (max_rx_gain >= trsw_rx_gain) { trsw_rx_gain = max_rx_gain - trsw_rx_gain; trsw_rx = 0x20; } } else trsw_rx_gain = max_rx_gain; if (trsw_rx_gain < 9) { pg->pg_lna_lod_gain = 0; } else { pg->pg_lna_lod_gain = 1; trsw_rx_gain -= 8; } trsw_rx_gain = MIN(MAX(trsw_rx_gain, 0), 0x2d); pg->pg_pga_gain = trsw_rx_gain / 3; if (pg->pg_pga_gain >= 5) { pg->pg_pga_gain -= 5; pg->pg_lna_gain = 2; } else pg->pg_lna_gain = 0; } else { pg->pg_lna_gain = 0; pg->pg_trsw_rx_gain = 0x20; if (max_rx_gain >= 0x14) { pg->pg_lna_lod_gain = 1; pg->pg_pga_gain = 2; } else if (max_rx_gain >= 0x12) { pg->pg_lna_lod_gain = 1; pg->pg_pga_gain = 1; } else if (max_rx_gain >= 0xf) { pg->pg_lna_lod_gain = 1; pg->pg_pga_gain = 0; } else { pg->pg_lna_lod_gain = 0; pg->pg_pga_gain = 0; } } tmp = BWN_RF_READ(mac, 0x7a); if (pg->pg_lna_lod_gain == 0) tmp &= ~0x0008; else tmp |= 0x0008; BWN_RF_WRITE(mac, 0x7a, tmp); } static void bwn_lo_save(struct bwn_mac *mac, struct bwn_lo_g_value *sav) { struct bwn_phy *phy = &mac->mac_phy; struct bwn_phy_g *pg = &phy->phy_g; struct bwn_softc *sc = mac->mac_sc; struct bwn_txpwr_loctl *lo = &pg->pg_loctl; struct timespec ts; uint16_t tmp; if (bwn_has_hwpctl(mac)) { sav->phy_lomask = BWN_PHY_READ(mac, BWN_PHY_LO_MASK); sav->phy_extg = BWN_PHY_READ(mac, BWN_PHY_EXTG(0x01)); sav->phy_dacctl_hwpctl = BWN_PHY_READ(mac, BWN_PHY_DACCTL); sav->phy_cck4 = BWN_PHY_READ(mac, BWN_PHY_CCK(0x14)); sav->phy_hpwr_tssictl = BWN_PHY_READ(mac, BWN_PHY_HPWR_TSSICTL); BWN_PHY_SET(mac, BWN_PHY_HPWR_TSSICTL, 0x100); BWN_PHY_SET(mac, BWN_PHY_EXTG(0x01), 0x40); BWN_PHY_SET(mac, BWN_PHY_DACCTL, 0x40); BWN_PHY_SET(mac, BWN_PHY_CCK(0x14), 0x200); } if (phy->type == BWN_PHYTYPE_B && phy->rf_ver == 0x2050 && phy->rf_rev < 6) { BWN_PHY_WRITE(mac, BWN_PHY_CCK(0x16), 0x410); BWN_PHY_WRITE(mac, BWN_PHY_CCK(0x17), 0x820); } if (phy->rev >= 2) { sav->phy_analogover = BWN_PHY_READ(mac, BWN_PHY_ANALOGOVER); sav->phy_analogoverval = BWN_PHY_READ(mac, BWN_PHY_ANALOGOVERVAL); sav->phy_rfover = BWN_PHY_READ(mac, BWN_PHY_RFOVER); sav->phy_rfoverval = BWN_PHY_READ(mac, BWN_PHY_RFOVERVAL); sav->phy_classctl = BWN_PHY_READ(mac, BWN_PHY_CLASSCTL); sav->phy_cck3 = BWN_PHY_READ(mac, BWN_PHY_CCK(0x3e)); sav->phy_crs0 = BWN_PHY_READ(mac, BWN_PHY_CRS0); BWN_PHY_MASK(mac, BWN_PHY_CLASSCTL, 0xfffc); BWN_PHY_MASK(mac, BWN_PHY_CRS0, 0x7fff); BWN_PHY_SET(mac, BWN_PHY_ANALOGOVER, 0x0003); BWN_PHY_MASK(mac, BWN_PHY_ANALOGOVERVAL, 0xfffc); if (phy->type == BWN_PHYTYPE_G) { if ((phy->rev >= 7) && - (siba_sprom_get_bf_lo(sc->sc_dev) & - BWN_BFL_EXTLNA)) { + (sc->sc_board_info.board_flags & + BHND_BFL_EXTLNA)) { BWN_PHY_WRITE(mac, BWN_PHY_RFOVER, 0x933); } else { BWN_PHY_WRITE(mac, BWN_PHY_RFOVER, 0x133); } } else { BWN_PHY_WRITE(mac, BWN_PHY_RFOVER, 0); } BWN_PHY_WRITE(mac, BWN_PHY_CCK(0x3e), 0); } sav->reg0 = BWN_READ_2(mac, 0x3f4); sav->reg1 = BWN_READ_2(mac, 0x3e2); sav->rf0 = BWN_RF_READ(mac, 0x43); sav->rf1 = BWN_RF_READ(mac, 0x7a); sav->phy_pgactl = BWN_PHY_READ(mac, BWN_PHY_PGACTL); sav->phy_cck2 = BWN_PHY_READ(mac, BWN_PHY_CCK(0x2a)); sav->phy_syncctl = BWN_PHY_READ(mac, BWN_PHY_SYNCCTL); sav->phy_dacctl = BWN_PHY_READ(mac, BWN_PHY_DACCTL); if (!BWN_HAS_TXMAG(phy)) { sav->rf2 = BWN_RF_READ(mac, 0x52); sav->rf2 &= 0x00f0; } if (phy->type == BWN_PHYTYPE_B) { sav->phy_cck0 = BWN_PHY_READ(mac, BWN_PHY_CCK(0x30)); sav->phy_cck1 = BWN_PHY_READ(mac, BWN_PHY_CCK(0x06)); BWN_PHY_WRITE(mac, BWN_PHY_CCK(0x30), 0x00ff); BWN_PHY_WRITE(mac, BWN_PHY_CCK(0x06), 0x3f3f); } else { BWN_WRITE_2(mac, 0x3e2, BWN_READ_2(mac, 0x3e2) | 0x8000); } BWN_WRITE_2(mac, 0x3f4, BWN_READ_2(mac, 0x3f4) & 0xf000); tmp = (phy->type == BWN_PHYTYPE_G) ? BWN_PHY_LO_MASK : BWN_PHY_CCK(0x2e); BWN_PHY_WRITE(mac, tmp, 0x007f); tmp = sav->phy_syncctl; BWN_PHY_WRITE(mac, BWN_PHY_SYNCCTL, tmp & 0xff7f); tmp = sav->rf1; BWN_RF_WRITE(mac, 0x007a, tmp & 0xfff0); BWN_PHY_WRITE(mac, BWN_PHY_CCK(0x2a), 0x8a3); if (phy->type == BWN_PHYTYPE_G || (phy->type == BWN_PHYTYPE_B && phy->rf_ver == 0x2050 && phy->rf_rev >= 6)) { BWN_PHY_WRITE(mac, BWN_PHY_CCK(0x2b), 0x1003); } else BWN_PHY_WRITE(mac, BWN_PHY_CCK(0x2b), 0x0802); if (phy->rev >= 2) bwn_dummy_transmission(mac, 0, 1); bwn_phy_g_switch_chan(mac, 6, 0); BWN_RF_READ(mac, 0x51); if (phy->type == BWN_PHYTYPE_G) BWN_PHY_WRITE(mac, BWN_PHY_CCK(0x2f), 0); nanouptime(&ts); if (ieee80211_time_before(lo->txctl_measured_time, (ts.tv_nsec / 1000000 + ts.tv_sec * 1000) - BWN_LO_TXCTL_EXPIRE)) bwn_lo_measure_txctl_values(mac); if (phy->type == BWN_PHYTYPE_G && phy->rev >= 3) BWN_PHY_WRITE(mac, BWN_PHY_LO_MASK, 0xc078); else { if (phy->type == BWN_PHYTYPE_B) BWN_PHY_WRITE(mac, BWN_PHY_CCK(0x2e), 0x8078); else BWN_PHY_WRITE(mac, BWN_PHY_LO_MASK, 0x8078); } } static void bwn_lo_restore(struct bwn_mac *mac, struct bwn_lo_g_value *sav) { struct bwn_phy *phy = &mac->mac_phy; struct bwn_phy_g *pg = &phy->phy_g; uint16_t tmp; if (phy->rev >= 2) { BWN_PHY_WRITE(mac, BWN_PHY_PGACTL, 0xe300); tmp = (pg->pg_pga_gain << 8); BWN_PHY_WRITE(mac, BWN_PHY_RFOVERVAL, tmp | 0xa0); DELAY(5); BWN_PHY_WRITE(mac, BWN_PHY_RFOVERVAL, tmp | 0xa2); DELAY(2); BWN_PHY_WRITE(mac, BWN_PHY_RFOVERVAL, tmp | 0xa3); } else { tmp = (pg->pg_pga_gain | 0xefa0); BWN_PHY_WRITE(mac, BWN_PHY_PGACTL, tmp); } if (phy->type == BWN_PHYTYPE_G) { if (phy->rev >= 3) BWN_PHY_WRITE(mac, BWN_PHY_CCK(0x2e), 0xc078); else BWN_PHY_WRITE(mac, BWN_PHY_CCK(0x2e), 0x8078); if (phy->rev >= 2) BWN_PHY_WRITE(mac, BWN_PHY_CCK(0x2f), 0x0202); else BWN_PHY_WRITE(mac, BWN_PHY_CCK(0x2f), 0x0101); } BWN_WRITE_2(mac, 0x3f4, sav->reg0); BWN_PHY_WRITE(mac, BWN_PHY_PGACTL, sav->phy_pgactl); BWN_PHY_WRITE(mac, BWN_PHY_CCK(0x2a), sav->phy_cck2); BWN_PHY_WRITE(mac, BWN_PHY_SYNCCTL, sav->phy_syncctl); BWN_PHY_WRITE(mac, BWN_PHY_DACCTL, sav->phy_dacctl); BWN_RF_WRITE(mac, 0x43, sav->rf0); BWN_RF_WRITE(mac, 0x7a, sav->rf1); if (!BWN_HAS_TXMAG(phy)) { tmp = sav->rf2; BWN_RF_SETMASK(mac, 0x52, 0xff0f, tmp); } BWN_WRITE_2(mac, 0x3e2, sav->reg1); if (phy->type == BWN_PHYTYPE_B && phy->rf_ver == 0x2050 && phy->rf_rev <= 5) { BWN_PHY_WRITE(mac, BWN_PHY_CCK(0x30), sav->phy_cck0); BWN_PHY_WRITE(mac, BWN_PHY_CCK(0x06), sav->phy_cck1); } if (phy->rev >= 2) { BWN_PHY_WRITE(mac, BWN_PHY_ANALOGOVER, sav->phy_analogover); BWN_PHY_WRITE(mac, BWN_PHY_ANALOGOVERVAL, sav->phy_analogoverval); BWN_PHY_WRITE(mac, BWN_PHY_CLASSCTL, sav->phy_classctl); BWN_PHY_WRITE(mac, BWN_PHY_RFOVER, sav->phy_rfover); BWN_PHY_WRITE(mac, BWN_PHY_RFOVERVAL, sav->phy_rfoverval); BWN_PHY_WRITE(mac, BWN_PHY_CCK(0x3e), sav->phy_cck3); BWN_PHY_WRITE(mac, BWN_PHY_CRS0, sav->phy_crs0); } if (bwn_has_hwpctl(mac)) { tmp = (sav->phy_lomask & 0xbfff); BWN_PHY_WRITE(mac, BWN_PHY_LO_MASK, tmp); BWN_PHY_WRITE(mac, BWN_PHY_EXTG(0x01), sav->phy_extg); BWN_PHY_WRITE(mac, BWN_PHY_DACCTL, sav->phy_dacctl_hwpctl); BWN_PHY_WRITE(mac, BWN_PHY_CCK(0x14), sav->phy_cck4); BWN_PHY_WRITE(mac, BWN_PHY_HPWR_TSSICTL, sav->phy_hpwr_tssictl); } bwn_phy_g_switch_chan(mac, sav->old_channel, 1); } static int bwn_lo_probe_loctl(struct bwn_mac *mac, struct bwn_loctl *probe, struct bwn_lo_g_sm *d) { struct bwn_phy *phy = &mac->mac_phy; struct bwn_phy_g *pg = &phy->phy_g; struct bwn_loctl orig, test; struct bwn_loctl prev = { -100, -100 }; static const struct bwn_loctl modifiers[] = { { 1, 1,}, { 1, 0,}, { 1, -1,}, { 0, -1,}, { -1, -1,}, { -1, 0,}, { -1, 1,}, { 0, 1,} }; int begin, end, lower = 0, i; uint16_t feedth; if (d->curstate == 0) { begin = 1; end = 8; } else if (d->curstate % 2 == 0) { begin = d->curstate - 1; end = d->curstate + 1; } else { begin = d->curstate - 2; end = d->curstate + 2; } if (begin < 1) begin += 8; if (end > 8) end -= 8; memcpy(&orig, probe, sizeof(struct bwn_loctl)); i = begin; d->curstate = i; while (1) { KASSERT(i >= 1 && i <= 8, ("%s:%d: fail", __func__, __LINE__)); memcpy(&test, &orig, sizeof(struct bwn_loctl)); test.i += modifiers[i - 1].i * d->multipler; test.q += modifiers[i - 1].q * d->multipler; if ((test.i != prev.i || test.q != prev.q) && (abs(test.i) <= 16 && abs(test.q) <= 16)) { bwn_lo_write(mac, &test); feedth = bwn_lo_calcfeed(mac, pg->pg_lna_gain, pg->pg_pga_gain, pg->pg_trsw_rx_gain); if (feedth < d->feedth) { memcpy(probe, &test, sizeof(struct bwn_loctl)); lower = 1; d->feedth = feedth; if (d->nmeasure < 2 && !BWN_HAS_LOOPBACK(phy)) break; } } memcpy(&prev, &test, sizeof(prev)); if (i == end) break; if (i == 8) i = 1; else i++; d->curstate = i; } return (lower); } static void bwn_lo_probe_sm(struct bwn_mac *mac, struct bwn_loctl *loctl, int *rxgain) { struct bwn_phy *phy = &mac->mac_phy; struct bwn_phy_g *pg = &phy->phy_g; struct bwn_lo_g_sm d; struct bwn_loctl probe; int lower, repeat, cnt = 0; uint16_t feedth; d.nmeasure = 0; d.multipler = 1; if (BWN_HAS_LOOPBACK(phy)) d.multipler = 3; memcpy(&d.loctl, loctl, sizeof(struct bwn_loctl)); repeat = (BWN_HAS_LOOPBACK(phy)) ? 4 : 1; do { bwn_lo_write(mac, &d.loctl); feedth = bwn_lo_calcfeed(mac, pg->pg_lna_gain, pg->pg_pga_gain, pg->pg_trsw_rx_gain); if (feedth < 0x258) { if (feedth >= 0x12c) *rxgain += 6; else *rxgain += 3; feedth = bwn_lo_calcfeed(mac, pg->pg_lna_gain, pg->pg_pga_gain, pg->pg_trsw_rx_gain); } d.feedth = feedth; d.curstate = 0; do { KASSERT(d.curstate >= 0 && d.curstate <= 8, ("%s:%d: fail", __func__, __LINE__)); memcpy(&probe, &d.loctl, sizeof(struct bwn_loctl)); lower = bwn_lo_probe_loctl(mac, &probe, &d); if (!lower) break; if ((probe.i == d.loctl.i) && (probe.q == d.loctl.q)) break; memcpy(&d.loctl, &probe, sizeof(struct bwn_loctl)); d.nmeasure++; } while (d.nmeasure < 24); memcpy(loctl, &d.loctl, sizeof(struct bwn_loctl)); if (BWN_HAS_LOOPBACK(phy)) { if (d.feedth > 0x1194) *rxgain -= 6; else if (d.feedth < 0x5dc) *rxgain += 3; if (cnt == 0) { if (d.feedth <= 0x5dc) { d.multipler = 1; cnt++; } else d.multipler = 2; } else if (cnt == 2) d.multipler = 1; } bwn_lo_measure_gain_values(mac, *rxgain, BWN_HAS_LOOPBACK(phy)); } while (++cnt < repeat); } static struct bwn_lo_calib * bwn_lo_calibset(struct bwn_mac *mac, const struct bwn_bbatt *bbatt, const struct bwn_rfatt *rfatt) { struct bwn_phy *phy = &mac->mac_phy; struct bwn_phy_g *pg = &phy->phy_g; struct bwn_loctl loctl = { 0, 0 }; struct bwn_lo_calib *cal; struct bwn_lo_g_value sval = { 0 }; int rxgain; uint16_t pad, reg, value; sval.old_channel = phy->chan; bwn_mac_suspend(mac); bwn_lo_save(mac, &sval); reg = bwn_lo_txctl_regtable(mac, &value, &pad); BWN_RF_SETMASK(mac, 0x43, 0xfff0, rfatt->att); BWN_RF_SETMASK(mac, reg, ~value, (rfatt->padmix ? value :0)); rxgain = (rfatt->att * 2) + (bbatt->att / 2); if (rfatt->padmix) rxgain -= pad; if (BWN_HAS_LOOPBACK(phy)) rxgain += pg->pg_max_lb_gain; bwn_lo_measure_gain_values(mac, rxgain, BWN_HAS_LOOPBACK(phy)); bwn_phy_g_set_bbatt(mac, bbatt->att); bwn_lo_probe_sm(mac, &loctl, &rxgain); bwn_lo_restore(mac, &sval); bwn_mac_enable(mac); cal = malloc(sizeof(*cal), M_DEVBUF, M_NOWAIT | M_ZERO); if (!cal) { device_printf(mac->mac_sc->sc_dev, "out of memory\n"); return (NULL); } memcpy(&cal->bbatt, bbatt, sizeof(*bbatt)); memcpy(&cal->rfatt, rfatt, sizeof(*rfatt)); memcpy(&cal->ctl, &loctl, sizeof(loctl)); BWN_GETTIME(cal->calib_time); return (cal); } static struct bwn_lo_calib * bwn_lo_get_calib(struct bwn_mac *mac, const struct bwn_bbatt *bbatt, const struct bwn_rfatt *rfatt) { struct bwn_txpwr_loctl *lo = &mac->mac_phy.phy_g.pg_loctl; struct bwn_lo_calib *c; TAILQ_FOREACH(c, &lo->calib_list, list) { if (!BWN_BBATTCMP(&c->bbatt, bbatt)) continue; if (!BWN_RFATTCMP(&c->rfatt, rfatt)) continue; return (c); } c = bwn_lo_calibset(mac, bbatt, rfatt); if (!c) return (NULL); TAILQ_INSERT_TAIL(&lo->calib_list, c, list); return (c); } static void bwn_phy_g_dc_lookup_init(struct bwn_mac *mac, uint8_t update) { struct bwn_phy *phy = &mac->mac_phy; struct bwn_phy_g *pg = &phy->phy_g; struct bwn_softc *sc = mac->mac_sc; struct bwn_txpwr_loctl *lo = &pg->pg_loctl; const struct bwn_rfatt *rfatt; const struct bwn_bbatt *bbatt; uint64_t pvector; int i; int rf_offset, bb_offset; uint8_t changed = 0; KASSERT(BWN_DC_LT_SIZE == 32, ("%s:%d: fail", __func__, __LINE__)); KASSERT(lo->rfatt.len * lo->bbatt.len <= 64, ("%s:%d: fail", __func__, __LINE__)); pvector = lo->power_vector; if (!update && !pvector) return; bwn_mac_suspend(mac); for (i = 0; i < BWN_DC_LT_SIZE * 2; i++) { struct bwn_lo_calib *cal; int idx; uint16_t val; if (!update && !(pvector & (((uint64_t)1ULL) << i))) continue; bb_offset = i / lo->rfatt.len; rf_offset = i % lo->rfatt.len; bbatt = &(lo->bbatt.array[bb_offset]); rfatt = &(lo->rfatt.array[rf_offset]); cal = bwn_lo_calibset(mac, bbatt, rfatt); if (!cal) { device_printf(sc->sc_dev, "LO: Could not " "calibrate DC table entry\n"); continue; } val = (uint8_t)(cal->ctl.q); val |= ((uint8_t)(cal->ctl.i)) << 4; free(cal, M_DEVBUF); idx = i / 2; if (i % 2) lo->dc_lt[idx] = (lo->dc_lt[idx] & 0x00ff) | ((val & 0x00ff) << 8); else lo->dc_lt[idx] = (lo->dc_lt[idx] & 0xff00) | (val & 0x00ff); changed = 1; } if (changed) { for (i = 0; i < BWN_DC_LT_SIZE; i++) BWN_PHY_WRITE(mac, 0x3a0 + i, lo->dc_lt[i]); } bwn_mac_enable(mac); } static void bwn_lo_fixup_rfatt(struct bwn_rfatt *rf) { if (!rf->padmix) return; if ((rf->att != 1) && (rf->att != 2) && (rf->att != 3)) rf->att = 4; } static void bwn_lo_g_adjust(struct bwn_mac *mac) { struct bwn_phy_g *pg = &mac->mac_phy.phy_g; struct bwn_lo_calib *cal; struct bwn_rfatt rf; memcpy(&rf, &pg->pg_rfatt, sizeof(rf)); bwn_lo_fixup_rfatt(&rf); cal = bwn_lo_get_calib(mac, &pg->pg_bbatt, &rf); if (!cal) return; bwn_lo_write(mac, &cal->ctl); } static void bwn_lo_g_init(struct bwn_mac *mac) { if (!bwn_has_hwpctl(mac)) return; bwn_lo_get_powervector(mac); bwn_phy_g_dc_lookup_init(mac, 1); } static int16_t bwn_nrssi_read(struct bwn_mac *mac, uint16_t offset) { BWN_PHY_WRITE(mac, BWN_PHY_NRSSI_CTRL, offset); return ((int16_t)BWN_PHY_READ(mac, BWN_PHY_NRSSI_DATA)); } static void bwn_nrssi_threshold(struct bwn_mac *mac) { struct bwn_phy *phy = &mac->mac_phy; struct bwn_phy_g *pg = &phy->phy_g; struct bwn_softc *sc = mac->mac_sc; int32_t a, b; int16_t tmp16; uint16_t tmpu16; KASSERT(phy->type == BWN_PHYTYPE_G, ("%s: fail", __func__)); - if (phy->gmode && (siba_sprom_get_bf_lo(sc->sc_dev) & BWN_BFL_RSSI)) { + if (phy->gmode && (sc->sc_board_info.board_flags & BHND_BFL_ADCDIV)) { if (!pg->pg_aci_wlan_automatic && pg->pg_aci_enable) { a = 0x13; b = 0x12; } else { a = 0xe; b = 0x11; } a = a * (pg->pg_nrssi[1] - pg->pg_nrssi[0]); a += (pg->pg_nrssi[0] << 6); a += (a < 32) ? 31 : 32; a = a >> 6; a = MIN(MAX(a, -31), 31); b = b * (pg->pg_nrssi[1] - pg->pg_nrssi[0]); b += (pg->pg_nrssi[0] << 6); if (b < 32) b += 31; else b += 32; b = b >> 6; b = MIN(MAX(b, -31), 31); tmpu16 = BWN_PHY_READ(mac, 0x048a) & 0xf000; tmpu16 |= ((uint32_t)b & 0x0000003f); tmpu16 |= (((uint32_t)a & 0x0000003f) << 6); BWN_PHY_WRITE(mac, 0x048a, tmpu16); return; } tmp16 = bwn_nrssi_read(mac, 0x20); if (tmp16 >= 0x20) tmp16 -= 0x40; BWN_PHY_SETMASK(mac, 0x048a, 0xf000, (tmp16 < 3) ? 0x09eb : 0x0aed); } static void bwn_nrssi_slope_11g(struct bwn_mac *mac) { #define SAVE_RF_MAX 3 #define SAVE_PHY_COMM_MAX 4 #define SAVE_PHY3_MAX 8 static const uint16_t save_rf_regs[SAVE_RF_MAX] = { 0x7a, 0x52, 0x43 }; static const uint16_t save_phy_comm_regs[SAVE_PHY_COMM_MAX] = { 0x15, 0x5a, 0x59, 0x58 }; static const uint16_t save_phy3_regs[SAVE_PHY3_MAX] = { 0x002e, 0x002f, 0x080f, BWN_PHY_G_LOCTL, 0x0801, 0x0060, 0x0014, 0x0478 }; struct bwn_phy *phy = &mac->mac_phy; struct bwn_phy_g *pg = &phy->phy_g; int32_t i, tmp32, phy3_idx = 0; uint16_t delta, tmp; uint16_t save_rf[SAVE_RF_MAX]; uint16_t save_phy_comm[SAVE_PHY_COMM_MAX]; uint16_t save_phy3[SAVE_PHY3_MAX]; uint16_t ant_div, phy0, chan_ex; int16_t nrssi0, nrssi1; KASSERT(phy->type == BWN_PHYTYPE_G, ("%s:%d: fail", __func__, __LINE__)); if (phy->rf_rev >= 9) return; if (phy->rf_rev == 8) bwn_nrssi_offset(mac); BWN_PHY_MASK(mac, BWN_PHY_G_CRS, 0x7fff); BWN_PHY_MASK(mac, 0x0802, 0xfffc); /* * Save RF/PHY registers for later restoration */ ant_div = BWN_READ_2(mac, 0x03e2); BWN_WRITE_2(mac, 0x03e2, BWN_READ_2(mac, 0x03e2) | 0x8000); for (i = 0; i < SAVE_RF_MAX; ++i) save_rf[i] = BWN_RF_READ(mac, save_rf_regs[i]); for (i = 0; i < SAVE_PHY_COMM_MAX; ++i) save_phy_comm[i] = BWN_PHY_READ(mac, save_phy_comm_regs[i]); phy0 = BWN_READ_2(mac, BWN_PHY0); chan_ex = BWN_READ_2(mac, BWN_CHANNEL_EXT); if (phy->rev >= 3) { for (i = 0; i < SAVE_PHY3_MAX; ++i) save_phy3[i] = BWN_PHY_READ(mac, save_phy3_regs[i]); BWN_PHY_WRITE(mac, 0x002e, 0); BWN_PHY_WRITE(mac, BWN_PHY_G_LOCTL, 0); switch (phy->rev) { case 4: case 6: case 7: BWN_PHY_SET(mac, 0x0478, 0x0100); BWN_PHY_SET(mac, 0x0801, 0x0040); break; case 3: case 5: BWN_PHY_MASK(mac, 0x0801, 0xffbf); break; } BWN_PHY_SET(mac, 0x0060, 0x0040); BWN_PHY_SET(mac, 0x0014, 0x0200); } /* * Calculate nrssi0 */ BWN_RF_SET(mac, 0x007a, 0x0070); bwn_set_all_gains(mac, 0, 8, 0); BWN_RF_MASK(mac, 0x007a, 0x00f7); if (phy->rev >= 2) { BWN_PHY_SETMASK(mac, 0x0811, 0xffcf, 0x0030); BWN_PHY_SETMASK(mac, 0x0812, 0xffcf, 0x0010); } BWN_RF_SET(mac, 0x007a, 0x0080); DELAY(20); nrssi0 = (int16_t) ((BWN_PHY_READ(mac, 0x047f) >> 8) & 0x003f); if (nrssi0 >= 0x0020) nrssi0 -= 0x0040; /* * Calculate nrssi1 */ BWN_RF_MASK(mac, 0x007a, 0x007f); if (phy->rev >= 2) BWN_PHY_SETMASK(mac, 0x0003, 0xff9f, 0x0040); BWN_WRITE_2(mac, BWN_CHANNEL_EXT, BWN_READ_2(mac, BWN_CHANNEL_EXT) | 0x2000); BWN_RF_SET(mac, 0x007a, 0x000f); BWN_PHY_WRITE(mac, 0x0015, 0xf330); if (phy->rev >= 2) { BWN_PHY_SETMASK(mac, 0x0812, 0xffcf, 0x0020); BWN_PHY_SETMASK(mac, 0x0811, 0xffcf, 0x0020); } bwn_set_all_gains(mac, 3, 0, 1); if (phy->rf_rev == 8) { BWN_RF_WRITE(mac, 0x0043, 0x001f); } else { tmp = BWN_RF_READ(mac, 0x0052) & 0xff0f; BWN_RF_WRITE(mac, 0x0052, tmp | 0x0060); tmp = BWN_RF_READ(mac, 0x0043) & 0xfff0; BWN_RF_WRITE(mac, 0x0043, tmp | 0x0009); } BWN_PHY_WRITE(mac, 0x005a, 0x0480); BWN_PHY_WRITE(mac, 0x0059, 0x0810); BWN_PHY_WRITE(mac, 0x0058, 0x000d); DELAY(20); nrssi1 = (int16_t) ((BWN_PHY_READ(mac, 0x047f) >> 8) & 0x003f); /* * Install calculated narrow RSSI values */ if (nrssi1 >= 0x0020) nrssi1 -= 0x0040; if (nrssi0 == nrssi1) pg->pg_nrssi_slope = 0x00010000; else pg->pg_nrssi_slope = 0x00400000 / (nrssi0 - nrssi1); if (nrssi0 >= -4) { pg->pg_nrssi[0] = nrssi1; pg->pg_nrssi[1] = nrssi0; } /* * Restore saved RF/PHY registers */ if (phy->rev >= 3) { for (phy3_idx = 0; phy3_idx < 4; ++phy3_idx) { BWN_PHY_WRITE(mac, save_phy3_regs[phy3_idx], save_phy3[phy3_idx]); } } if (phy->rev >= 2) { BWN_PHY_MASK(mac, 0x0812, 0xffcf); BWN_PHY_MASK(mac, 0x0811, 0xffcf); } for (i = 0; i < SAVE_RF_MAX; ++i) BWN_RF_WRITE(mac, save_rf_regs[i], save_rf[i]); BWN_WRITE_2(mac, 0x03e2, ant_div); BWN_WRITE_2(mac, 0x03e6, phy0); BWN_WRITE_2(mac, BWN_CHANNEL_EXT, chan_ex); for (i = 0; i < SAVE_PHY_COMM_MAX; ++i) BWN_PHY_WRITE(mac, save_phy_comm_regs[i], save_phy_comm[i]); bwn_spu_workaround(mac, phy->chan); BWN_PHY_SET(mac, 0x0802, (0x0001 | 0x0002)); bwn_set_original_gains(mac); BWN_PHY_SET(mac, BWN_PHY_G_CRS, 0x8000); if (phy->rev >= 3) { for (; phy3_idx < SAVE_PHY3_MAX; ++phy3_idx) { BWN_PHY_WRITE(mac, save_phy3_regs[phy3_idx], save_phy3[phy3_idx]); } } delta = 0x1f - pg->pg_nrssi[0]; for (i = 0; i < 64; i++) { tmp32 = (((i - delta) * pg->pg_nrssi_slope) / 0x10000) + 0x3a; tmp32 = MIN(MAX(tmp32, 0), 0x3f); pg->pg_nrssi_lt[i] = tmp32; } bwn_nrssi_threshold(mac); #undef SAVE_RF_MAX #undef SAVE_PHY_COMM_MAX #undef SAVE_PHY3_MAX } static void bwn_nrssi_offset(struct bwn_mac *mac) { #define SAVE_RF_MAX 2 #define SAVE_PHY_COMM_MAX 10 #define SAVE_PHY6_MAX 8 static const uint16_t save_rf_regs[SAVE_RF_MAX] = { 0x7a, 0x43 }; static const uint16_t save_phy_comm_regs[SAVE_PHY_COMM_MAX] = { 0x0001, 0x0811, 0x0812, 0x0814, 0x0815, 0x005a, 0x0059, 0x0058, 0x000a, 0x0003 }; static const uint16_t save_phy6_regs[SAVE_PHY6_MAX] = { 0x002e, 0x002f, 0x080f, 0x0810, 0x0801, 0x0060, 0x0014, 0x0478 }; struct bwn_phy *phy = &mac->mac_phy; int i, phy6_idx = 0; uint16_t save_rf[SAVE_RF_MAX]; uint16_t save_phy_comm[SAVE_PHY_COMM_MAX]; uint16_t save_phy6[SAVE_PHY6_MAX]; int16_t nrssi; uint16_t saved = 0xffff; for (i = 0; i < SAVE_PHY_COMM_MAX; ++i) save_phy_comm[i] = BWN_PHY_READ(mac, save_phy_comm_regs[i]); for (i = 0; i < SAVE_RF_MAX; ++i) save_rf[i] = BWN_RF_READ(mac, save_rf_regs[i]); BWN_PHY_MASK(mac, 0x0429, 0x7fff); BWN_PHY_SETMASK(mac, 0x0001, 0x3fff, 0x4000); BWN_PHY_SET(mac, 0x0811, 0x000c); BWN_PHY_SETMASK(mac, 0x0812, 0xfff3, 0x0004); BWN_PHY_MASK(mac, 0x0802, ~(0x1 | 0x2)); if (phy->rev >= 6) { for (i = 0; i < SAVE_PHY6_MAX; ++i) save_phy6[i] = BWN_PHY_READ(mac, save_phy6_regs[i]); BWN_PHY_WRITE(mac, 0x002e, 0); BWN_PHY_WRITE(mac, 0x002f, 0); BWN_PHY_WRITE(mac, 0x080f, 0); BWN_PHY_WRITE(mac, 0x0810, 0); BWN_PHY_SET(mac, 0x0478, 0x0100); BWN_PHY_SET(mac, 0x0801, 0x0040); BWN_PHY_SET(mac, 0x0060, 0x0040); BWN_PHY_SET(mac, 0x0014, 0x0200); } BWN_RF_SET(mac, 0x007a, 0x0070); BWN_RF_SET(mac, 0x007a, 0x0080); DELAY(30); nrssi = (int16_t) ((BWN_PHY_READ(mac, 0x047f) >> 8) & 0x003f); if (nrssi >= 0x20) nrssi -= 0x40; if (nrssi == 31) { for (i = 7; i >= 4; i--) { BWN_RF_WRITE(mac, 0x007b, i); DELAY(20); nrssi = (int16_t) ((BWN_PHY_READ(mac, 0x047f) >> 8) & 0x003f); if (nrssi >= 0x20) nrssi -= 0x40; if (nrssi < 31 && saved == 0xffff) saved = i; } if (saved == 0xffff) saved = 4; } else { BWN_RF_MASK(mac, 0x007a, 0x007f); if (phy->rev != 1) { BWN_PHY_SET(mac, 0x0814, 0x0001); BWN_PHY_MASK(mac, 0x0815, 0xfffe); } BWN_PHY_SET(mac, 0x0811, 0x000c); BWN_PHY_SET(mac, 0x0812, 0x000c); BWN_PHY_SET(mac, 0x0811, 0x0030); BWN_PHY_SET(mac, 0x0812, 0x0030); BWN_PHY_WRITE(mac, 0x005a, 0x0480); BWN_PHY_WRITE(mac, 0x0059, 0x0810); BWN_PHY_WRITE(mac, 0x0058, 0x000d); if (phy->rev == 0) BWN_PHY_WRITE(mac, 0x0003, 0x0122); else BWN_PHY_SET(mac, 0x000a, 0x2000); if (phy->rev != 1) { BWN_PHY_SET(mac, 0x0814, 0x0004); BWN_PHY_MASK(mac, 0x0815, 0xfffb); } BWN_PHY_SETMASK(mac, 0x0003, 0xff9f, 0x0040); BWN_RF_SET(mac, 0x007a, 0x000f); bwn_set_all_gains(mac, 3, 0, 1); BWN_RF_SETMASK(mac, 0x0043, 0x00f0, 0x000f); DELAY(30); nrssi = (int16_t) ((BWN_PHY_READ(mac, 0x047f) >> 8) & 0x003f); if (nrssi >= 0x20) nrssi -= 0x40; if (nrssi == -32) { for (i = 0; i < 4; i++) { BWN_RF_WRITE(mac, 0x007b, i); DELAY(20); nrssi = (int16_t)((BWN_PHY_READ(mac, 0x047f) >> 8) & 0x003f); if (nrssi >= 0x20) nrssi -= 0x40; if (nrssi > -31 && saved == 0xffff) saved = i; } if (saved == 0xffff) saved = 3; } else saved = 0; } BWN_RF_WRITE(mac, 0x007b, saved); /* * Restore saved RF/PHY registers */ if (phy->rev >= 6) { for (phy6_idx = 0; phy6_idx < 4; ++phy6_idx) { BWN_PHY_WRITE(mac, save_phy6_regs[phy6_idx], save_phy6[phy6_idx]); } } if (phy->rev != 1) { for (i = 3; i < 5; i++) BWN_PHY_WRITE(mac, save_phy_comm_regs[i], save_phy_comm[i]); } for (i = 5; i < SAVE_PHY_COMM_MAX; i++) BWN_PHY_WRITE(mac, save_phy_comm_regs[i], save_phy_comm[i]); for (i = SAVE_RF_MAX - 1; i >= 0; --i) BWN_RF_WRITE(mac, save_rf_regs[i], save_rf[i]); BWN_PHY_WRITE(mac, 0x0802, BWN_PHY_READ(mac, 0x0802) | 0x1 | 0x2); BWN_PHY_SET(mac, 0x0429, 0x8000); bwn_set_original_gains(mac); if (phy->rev >= 6) { for (; phy6_idx < SAVE_PHY6_MAX; ++phy6_idx) { BWN_PHY_WRITE(mac, save_phy6_regs[phy6_idx], save_phy6[phy6_idx]); } } BWN_PHY_WRITE(mac, save_phy_comm_regs[0], save_phy_comm[0]); BWN_PHY_WRITE(mac, save_phy_comm_regs[2], save_phy_comm[2]); BWN_PHY_WRITE(mac, save_phy_comm_regs[1], save_phy_comm[1]); } static void bwn_set_all_gains(struct bwn_mac *mac, int16_t first, int16_t second, int16_t third) { struct bwn_phy *phy = &mac->mac_phy; uint16_t i; uint16_t start = 0x08, end = 0x18; uint16_t tmp; uint16_t table; if (phy->rev <= 1) { start = 0x10; end = 0x20; } table = BWN_OFDMTAB_GAINX; if (phy->rev <= 1) table = BWN_OFDMTAB_GAINX_R1; for (i = 0; i < 4; i++) bwn_ofdmtab_write_2(mac, table, i, first); for (i = start; i < end; i++) bwn_ofdmtab_write_2(mac, table, i, second); if (third != -1) { tmp = ((uint16_t) third << 14) | ((uint16_t) third << 6); BWN_PHY_SETMASK(mac, 0x04a0, 0xbfbf, tmp); BWN_PHY_SETMASK(mac, 0x04a1, 0xbfbf, tmp); BWN_PHY_SETMASK(mac, 0x04a2, 0xbfbf, tmp); } bwn_dummy_transmission(mac, 0, 1); } static void bwn_set_original_gains(struct bwn_mac *mac) { struct bwn_phy *phy = &mac->mac_phy; uint16_t i, tmp; uint16_t table; uint16_t start = 0x0008, end = 0x0018; if (phy->rev <= 1) { start = 0x0010; end = 0x0020; } table = BWN_OFDMTAB_GAINX; if (phy->rev <= 1) table = BWN_OFDMTAB_GAINX_R1; for (i = 0; i < 4; i++) { tmp = (i & 0xfffc); tmp |= (i & 0x0001) << 1; tmp |= (i & 0x0002) >> 1; bwn_ofdmtab_write_2(mac, table, i, tmp); } for (i = start; i < end; i++) bwn_ofdmtab_write_2(mac, table, i, i - start); BWN_PHY_SETMASK(mac, 0x04a0, 0xbfbf, 0x4040); BWN_PHY_SETMASK(mac, 0x04a1, 0xbfbf, 0x4040); BWN_PHY_SETMASK(mac, 0x04a2, 0xbfbf, 0x4000); bwn_dummy_transmission(mac, 0, 1); } static void bwn_phy_hwpctl_init(struct bwn_mac *mac) { struct bwn_phy *phy = &mac->mac_phy; struct bwn_phy_g *pg = &phy->phy_g; struct bwn_rfatt old_rfatt, rfatt; struct bwn_bbatt old_bbatt, bbatt; struct bwn_softc *sc = mac->mac_sc; uint8_t old_txctl = 0; KASSERT(phy->type == BWN_PHYTYPE_G, ("%s:%d: fail", __func__, __LINE__)); - if ((siba_get_pci_subvendor(sc->sc_dev) == SIBA_BOARDVENDOR_BCM) && - (siba_get_pci_subdevice(sc->sc_dev) == SIBA_BOARD_BU4306)) + if ((sc->sc_board_info.board_vendor == PCI_VENDOR_BROADCOM) && + (sc->sc_board_info.board_type == BHND_BOARD_BU4306)) return; BWN_PHY_WRITE(mac, 0x0028, 0x8018); BWN_WRITE_2(mac, BWN_PHY0, BWN_READ_2(mac, BWN_PHY0) & 0xffdf); if (!phy->gmode) return; bwn_hwpctl_early_init(mac); if (pg->pg_curtssi == 0) { if (phy->rf_ver == 0x2050 && phy->analog == 0) { BWN_RF_SETMASK(mac, 0x0076, 0x00f7, 0x0084); } else { memcpy(&old_rfatt, &pg->pg_rfatt, sizeof(old_rfatt)); memcpy(&old_bbatt, &pg->pg_bbatt, sizeof(old_bbatt)); old_txctl = pg->pg_txctl; bbatt.att = 11; if (phy->rf_rev == 8) { rfatt.att = 15; rfatt.padmix = 1; } else { rfatt.att = 9; rfatt.padmix = 0; } bwn_phy_g_set_txpwr_sub(mac, &bbatt, &rfatt, 0); } bwn_dummy_transmission(mac, 0, 1); pg->pg_curtssi = BWN_PHY_READ(mac, BWN_PHY_TSSI); if (phy->rf_ver == 0x2050 && phy->analog == 0) BWN_RF_MASK(mac, 0x0076, 0xff7b); else bwn_phy_g_set_txpwr_sub(mac, &old_bbatt, &old_rfatt, old_txctl); } bwn_hwpctl_init_gphy(mac); /* clear TSSI */ bwn_shm_write_2(mac, BWN_SHARED, 0x0058, 0x7f7f); bwn_shm_write_2(mac, BWN_SHARED, 0x005a, 0x7f7f); bwn_shm_write_2(mac, BWN_SHARED, 0x0070, 0x7f7f); bwn_shm_write_2(mac, BWN_SHARED, 0x0072, 0x7f7f); } static void bwn_hwpctl_early_init(struct bwn_mac *mac) { struct bwn_phy *phy = &mac->mac_phy; if (!bwn_has_hwpctl(mac)) { BWN_PHY_WRITE(mac, 0x047a, 0xc111); return; } BWN_PHY_MASK(mac, 0x0036, 0xfeff); BWN_PHY_WRITE(mac, 0x002f, 0x0202); BWN_PHY_SET(mac, 0x047c, 0x0002); BWN_PHY_SET(mac, 0x047a, 0xf000); if (phy->rf_ver == 0x2050 && phy->rf_rev == 8) { BWN_PHY_SETMASK(mac, 0x047a, 0xff0f, 0x0010); BWN_PHY_SET(mac, 0x005d, 0x8000); BWN_PHY_SETMASK(mac, 0x004e, 0xffc0, 0x0010); BWN_PHY_WRITE(mac, 0x002e, 0xc07f); BWN_PHY_SET(mac, 0x0036, 0x0400); } else { BWN_PHY_SET(mac, 0x0036, 0x0200); BWN_PHY_SET(mac, 0x0036, 0x0400); BWN_PHY_MASK(mac, 0x005d, 0x7fff); BWN_PHY_MASK(mac, 0x004f, 0xfffe); BWN_PHY_SETMASK(mac, 0x004e, 0xffc0, 0x0010); BWN_PHY_WRITE(mac, 0x002e, 0xc07f); BWN_PHY_SETMASK(mac, 0x047a, 0xff0f, 0x0010); } } static void bwn_hwpctl_init_gphy(struct bwn_mac *mac) { struct bwn_phy *phy = &mac->mac_phy; struct bwn_phy_g *pg = &phy->phy_g; struct bwn_txpwr_loctl *lo = &pg->pg_loctl; int i; uint16_t nr_written = 0, tmp, value; uint8_t rf, bb; if (!bwn_has_hwpctl(mac)) { bwn_hf_write(mac, bwn_hf_read(mac) & ~BWN_HF_HW_POWERCTL); return; } BWN_PHY_SETMASK(mac, 0x0036, 0xffc0, (pg->pg_idletssi - pg->pg_curtssi)); BWN_PHY_SETMASK(mac, 0x0478, 0xff00, (pg->pg_idletssi - pg->pg_curtssi)); for (i = 0; i < 32; i++) bwn_ofdmtab_write_2(mac, 0x3c20, i, pg->pg_tssi2dbm[i]); for (i = 32; i < 64; i++) bwn_ofdmtab_write_2(mac, 0x3c00, i - 32, pg->pg_tssi2dbm[i]); for (i = 0; i < 64; i += 2) { value = (uint16_t) pg->pg_tssi2dbm[i]; value |= ((uint16_t) pg->pg_tssi2dbm[i + 1]) << 8; BWN_PHY_WRITE(mac, 0x380 + (i / 2), value); } for (rf = 0; rf < lo->rfatt.len; rf++) { for (bb = 0; bb < lo->bbatt.len; bb++) { if (nr_written >= 0x40) return; tmp = lo->bbatt.array[bb].att; tmp <<= 8; if (phy->rf_rev == 8) tmp |= 0x50; else tmp |= 0x40; tmp |= lo->rfatt.array[rf].att; BWN_PHY_WRITE(mac, 0x3c0 + nr_written, tmp); nr_written++; } } BWN_PHY_MASK(mac, 0x0060, 0xffbf); BWN_PHY_WRITE(mac, 0x0014, 0x0000); KASSERT(phy->rev >= 6, ("%s:%d: fail", __func__, __LINE__)); BWN_PHY_SET(mac, 0x0478, 0x0800); BWN_PHY_MASK(mac, 0x0478, 0xfeff); BWN_PHY_MASK(mac, 0x0801, 0xffbf); bwn_phy_g_dc_lookup_init(mac, 1); bwn_hf_write(mac, bwn_hf_read(mac) | BWN_HF_HW_POWERCTL); } static void bwn_phy_g_switch_chan(struct bwn_mac *mac, int channel, uint8_t spu) { - struct bwn_softc *sc = mac->mac_sc; + struct bwn_softc *sc = mac->mac_sc; + int error; if (spu != 0) bwn_spu_workaround(mac, channel); BWN_WRITE_2(mac, BWN_CHANNEL, bwn_phy_g_chan2freq(channel)); if (channel == 14) { - if (siba_sprom_get_ccode(sc->sc_dev) == SIBA_CCODE_JAPAN) + uint8_t cc; + + error = bhnd_nvram_getvar_uint8(sc->sc_dev, BHND_NVAR_CC, &cc); + if (error) { + device_printf(sc->sc_dev, "error reading country code " + "from NVRAM, assuming channel 14 unavailable: %d\n", + error); + cc = BWN_SPROM1_CC_WORLDWIDE; + } + + if (cc == BWN_SPROM1_CC_JP) bwn_hf_write(mac, bwn_hf_read(mac) & ~BWN_HF_JAPAN_CHAN14_OFF); else bwn_hf_write(mac, bwn_hf_read(mac) | BWN_HF_JAPAN_CHAN14_OFF); BWN_WRITE_2(mac, BWN_CHANNEL_EXT, BWN_READ_2(mac, BWN_CHANNEL_EXT) | (1 << 11)); return; } BWN_WRITE_2(mac, BWN_CHANNEL_EXT, BWN_READ_2(mac, BWN_CHANNEL_EXT) & 0xf7bf); } static uint16_t bwn_phy_g_chan2freq(uint8_t channel) { static const uint8_t bwn_phy_g_rf_channels[] = BWN_PHY_G_RF_CHANNELS; KASSERT(channel >= 1 && channel <= 14, ("%s:%d: fail", __func__, __LINE__)); return (bwn_phy_g_rf_channels[channel - 1]); } static void bwn_phy_g_set_txpwr_sub(struct bwn_mac *mac, const struct bwn_bbatt *bbatt, const struct bwn_rfatt *rfatt, uint8_t txctl) { struct bwn_phy *phy = &mac->mac_phy; struct bwn_phy_g *pg = &phy->phy_g; struct bwn_txpwr_loctl *lo = &pg->pg_loctl; uint16_t bb, rf; uint16_t tx_bias, tx_magn; bb = bbatt->att; rf = rfatt->att; tx_bias = lo->tx_bias; tx_magn = lo->tx_magn; if (tx_bias == 0xff) tx_bias = 0; pg->pg_txctl = txctl; memmove(&pg->pg_rfatt, rfatt, sizeof(*rfatt)); pg->pg_rfatt.padmix = (txctl & BWN_TXCTL_TXMIX) ? 1 : 0; memmove(&pg->pg_bbatt, bbatt, sizeof(*bbatt)); bwn_phy_g_set_bbatt(mac, bb); bwn_shm_write_2(mac, BWN_SHARED, BWN_SHARED_RADIO_ATT, rf); if (phy->rf_ver == 0x2050 && phy->rf_rev == 8) BWN_RF_WRITE(mac, 0x43, (rf & 0x000f) | (txctl & 0x0070)); else { BWN_RF_SETMASK(mac, 0x43, 0xfff0, (rf & 0x000f)); BWN_RF_SETMASK(mac, 0x52, ~0x0070, (txctl & 0x0070)); } if (BWN_HAS_TXMAG(phy)) BWN_RF_WRITE(mac, 0x52, tx_magn | tx_bias); else BWN_RF_SETMASK(mac, 0x52, 0xfff0, (tx_bias & 0x000f)); bwn_lo_g_adjust(mac); } static void bwn_phy_g_set_bbatt(struct bwn_mac *mac, uint16_t bbatt) { struct bwn_phy *phy = &mac->mac_phy; if (phy->analog == 0) { BWN_WRITE_2(mac, BWN_PHY0, (BWN_READ_2(mac, BWN_PHY0) & 0xfff0) | bbatt); return; } if (phy->analog > 1) { BWN_PHY_SETMASK(mac, BWN_PHY_DACCTL, 0xffc3, bbatt << 2); return; } BWN_PHY_SETMASK(mac, BWN_PHY_DACCTL, 0xff87, bbatt << 3); } static uint16_t bwn_rf_2050_rfoverval(struct bwn_mac *mac, uint16_t reg, uint32_t lpd) { struct bwn_phy *phy = &mac->mac_phy; struct bwn_phy_g *pg = &phy->phy_g; struct bwn_softc *sc = mac->mac_sc; int max_lb_gain; uint16_t extlna; uint16_t i; if (phy->gmode == 0) return (0); if (BWN_HAS_LOOPBACK(phy)) { max_lb_gain = pg->pg_max_lb_gain; max_lb_gain += (phy->rf_rev == 8) ? 0x3e : 0x26; if (max_lb_gain >= 0x46) { extlna = 0x3000; max_lb_gain -= 0x46; } else if (max_lb_gain >= 0x3a) { extlna = 0x1000; max_lb_gain -= 0x3a; } else if (max_lb_gain >= 0x2e) { extlna = 0x2000; max_lb_gain -= 0x2e; } else { extlna = 0; max_lb_gain -= 0x10; } for (i = 0; i < 16; i++) { max_lb_gain -= (i * 6); if (max_lb_gain < 6) break; } if ((phy->rev < 7) || - !(siba_sprom_get_bf_lo(sc->sc_dev) & BWN_BFL_EXTLNA)) { + !(sc->sc_board_info.board_flags & BHND_BFL_EXTLNA)) { if (reg == BWN_PHY_RFOVER) { return (0x1b3); } else if (reg == BWN_PHY_RFOVERVAL) { extlna |= (i << 8); switch (lpd) { case BWN_LPD(0, 1, 1): return (0x0f92); case BWN_LPD(0, 0, 1): case BWN_LPD(1, 0, 1): return (0x0092 | extlna); case BWN_LPD(1, 0, 0): return (0x0093 | extlna); } KASSERT(0 == 1, ("%s:%d: fail", __func__, __LINE__)); } KASSERT(0 == 1, ("%s:%d: fail", __func__, __LINE__)); } else { if (reg == BWN_PHY_RFOVER) return (0x9b3); if (reg == BWN_PHY_RFOVERVAL) { if (extlna) extlna |= 0x8000; extlna |= (i << 8); switch (lpd) { case BWN_LPD(0, 1, 1): return (0x8f92); case BWN_LPD(0, 0, 1): return (0x8092 | extlna); case BWN_LPD(1, 0, 1): return (0x2092 | extlna); case BWN_LPD(1, 0, 0): return (0x2093 | extlna); } KASSERT(0 == 1, ("%s:%d: fail", __func__, __LINE__)); } KASSERT(0 == 1, ("%s:%d: fail", __func__, __LINE__)); } return (0); } if ((phy->rev < 7) || - !(siba_sprom_get_bf_lo(sc->sc_dev) & BWN_BFL_EXTLNA)) { + !(sc->sc_board_info.board_flags & BHND_BFL_EXTLNA)) { if (reg == BWN_PHY_RFOVER) { return (0x1b3); } else if (reg == BWN_PHY_RFOVERVAL) { switch (lpd) { case BWN_LPD(0, 1, 1): return (0x0fb2); case BWN_LPD(0, 0, 1): return (0x00b2); case BWN_LPD(1, 0, 1): return (0x30b2); case BWN_LPD(1, 0, 0): return (0x30b3); } KASSERT(0 == 1, ("%s:%d: fail", __func__, __LINE__)); } KASSERT(0 == 1, ("%s:%d: fail", __func__, __LINE__)); } else { if (reg == BWN_PHY_RFOVER) { return (0x9b3); } else if (reg == BWN_PHY_RFOVERVAL) { switch (lpd) { case BWN_LPD(0, 1, 1): return (0x8fb2); case BWN_LPD(0, 0, 1): return (0x80b2); case BWN_LPD(1, 0, 1): return (0x20b2); case BWN_LPD(1, 0, 0): return (0x20b3); } KASSERT(0 == 1, ("%s:%d: fail", __func__, __LINE__)); } KASSERT(0 == 1, ("%s:%d: fail", __func__, __LINE__)); } return (0); } static void bwn_spu_workaround(struct bwn_mac *mac, uint8_t channel) { if (mac->mac_phy.rf_ver != 0x2050 || mac->mac_phy.rf_rev >= 6) return; BWN_WRITE_2(mac, BWN_CHANNEL, (channel <= 10) ? bwn_phy_g_chan2freq(channel + 4) : bwn_phy_g_chan2freq(1)); DELAY(1000); BWN_WRITE_2(mac, BWN_CHANNEL, bwn_phy_g_chan2freq(channel)); } static int bwn_phy_shm_tssi_read(struct bwn_mac *mac, uint16_t shm_offset) { const uint8_t ofdm = (shm_offset != BWN_SHARED_TSSI_CCK); unsigned int a, b, c, d; unsigned int avg; uint32_t tmp; tmp = bwn_shm_read_4(mac, BWN_SHARED, shm_offset); a = tmp & 0xff; b = (tmp >> 8) & 0xff; c = (tmp >> 16) & 0xff; d = (tmp >> 24) & 0xff; if (a == 0 || a == BWN_TSSI_MAX || b == 0 || b == BWN_TSSI_MAX || c == 0 || c == BWN_TSSI_MAX || d == 0 || d == BWN_TSSI_MAX) return (ENOENT); bwn_shm_write_4(mac, BWN_SHARED, shm_offset, BWN_TSSI_MAX | (BWN_TSSI_MAX << 8) | (BWN_TSSI_MAX << 16) | (BWN_TSSI_MAX << 24)); if (ofdm) { a = (a + 32) & 0x3f; b = (b + 32) & 0x3f; c = (c + 32) & 0x3f; d = (d + 32) & 0x3f; } avg = (a + b + c + d + 2) / 4; if (ofdm) { if (bwn_shm_read_2(mac, BWN_SHARED, BWN_SHARED_HFLO) & BWN_HF_4DB_CCK_POWERBOOST) avg = (avg >= 13) ? (avg - 13) : 0; } return (avg); } static void bwn_phy_g_setatt(struct bwn_mac *mac, int *bbattp, int *rfattp) { struct bwn_txpwr_loctl *lo = &mac->mac_phy.phy_g.pg_loctl; int rfatt = *rfattp; int bbatt = *bbattp; while (1) { if (rfatt > lo->rfatt.max && bbatt > lo->bbatt.max - 4) break; if (rfatt < lo->rfatt.min && bbatt < lo->bbatt.min + 4) break; if (bbatt > lo->bbatt.max && rfatt > lo->rfatt.max - 1) break; if (bbatt < lo->bbatt.min && rfatt < lo->rfatt.min + 1) break; if (bbatt > lo->bbatt.max) { bbatt -= 4; rfatt += 1; continue; } if (bbatt < lo->bbatt.min) { bbatt += 4; rfatt -= 1; continue; } if (rfatt > lo->rfatt.max) { rfatt -= 1; bbatt += 4; continue; } if (rfatt < lo->rfatt.min) { rfatt += 1; bbatt -= 4; continue; } break; } *rfattp = MIN(MAX(rfatt, lo->rfatt.min), lo->rfatt.max); *bbattp = MIN(MAX(bbatt, lo->bbatt.min), lo->bbatt.max); } static void bwn_phy_lock(struct bwn_mac *mac) { struct bwn_softc *sc = mac->mac_sc; struct ieee80211com *ic = &sc->sc_ic; - KASSERT(siba_get_revid(sc->sc_dev) >= 3, - ("%s: unsupported rev %d", __func__, siba_get_revid(sc->sc_dev))); + KASSERT(bhnd_get_hwrev(sc->sc_dev) >= 3, + ("%s: unsupported rev %d", __func__, bhnd_get_hwrev(sc->sc_dev))); if (ic->ic_opmode != IEEE80211_M_HOSTAP) bwn_psctl(mac, BWN_PS_AWAKE); } static void bwn_phy_unlock(struct bwn_mac *mac) { struct bwn_softc *sc = mac->mac_sc; struct ieee80211com *ic = &sc->sc_ic; - KASSERT(siba_get_revid(sc->sc_dev) >= 3, - ("%s: unsupported rev %d", __func__, siba_get_revid(sc->sc_dev))); + KASSERT(bhnd_get_hwrev(sc->sc_dev) >= 3, + ("%s: unsupported rev %d", __func__, bhnd_get_hwrev(sc->sc_dev))); if (ic->ic_opmode != IEEE80211_M_HOSTAP) bwn_psctl(mac, 0); } static void bwn_rf_lock(struct bwn_mac *mac) { BWN_WRITE_4(mac, BWN_MACCTL, BWN_READ_4(mac, BWN_MACCTL) | BWN_MACCTL_RADIO_LOCK); BWN_READ_4(mac, BWN_MACCTL); DELAY(10); } static void bwn_rf_unlock(struct bwn_mac *mac) { BWN_READ_2(mac, BWN_PHYVER); BWN_WRITE_4(mac, BWN_MACCTL, BWN_READ_4(mac, BWN_MACCTL) & ~BWN_MACCTL_RADIO_LOCK); } Index: head/sys/dev/bwn/if_bwn_phy_lp.c =================================================================== --- head/sys/dev/bwn/if_bwn_phy_lp.c (revision 328911) +++ head/sys/dev/bwn/if_bwn_phy_lp.c (revision 328912) @@ -1,3660 +1,3758 @@ /*- * Copyright (c) 2009-2010 Weongyo Jeong * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer, * without modification. * 2. Redistributions in binary form must reproduce at minimum a disclaimer * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any * redistribution must be conditioned upon including a substantially * similar Disclaimer requirement for further binary redistribution. * * NO WARRANTY * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF * THE POSSIBILITY OF SUCH DAMAGES. */ #include __FBSDID("$FreeBSD$"); #include "opt_bwn.h" #include "opt_wlan.h" /* * The Broadcom Wireless LAN controller driver. */ #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include -#include +#include +#include +#include + #include #include #include #include #include #include #include -static void bwn_phy_lp_readsprom(struct bwn_mac *); +#include "bhnd_nvram_map.h" + +static int bwn_phy_lp_readsprom(struct bwn_mac *); static void bwn_phy_lp_bbinit(struct bwn_mac *); static void bwn_phy_lp_txpctl_init(struct bwn_mac *); static void bwn_phy_lp_calib(struct bwn_mac *); static int bwn_phy_lp_b2062_switch_channel(struct bwn_mac *, uint8_t); static int bwn_phy_lp_b2063_switch_channel(struct bwn_mac *, uint8_t); static void bwn_phy_lp_set_anafilter(struct bwn_mac *, uint8_t); static void bwn_phy_lp_set_gaintbl(struct bwn_mac *, uint32_t); static void bwn_phy_lp_digflt_save(struct bwn_mac *); static void bwn_phy_lp_get_txpctlmode(struct bwn_mac *); static void bwn_phy_lp_set_txpctlmode(struct bwn_mac *, uint8_t); static void bwn_phy_lp_bugfix(struct bwn_mac *); static void bwn_phy_lp_digflt_restore(struct bwn_mac *); static void bwn_phy_lp_tblinit(struct bwn_mac *); static void bwn_phy_lp_bbinit_r2(struct bwn_mac *); static void bwn_phy_lp_bbinit_r01(struct bwn_mac *); -static void bwn_phy_lp_b2062_init(struct bwn_mac *); -static void bwn_phy_lp_b2063_init(struct bwn_mac *); -static void bwn_phy_lp_rxcal_r2(struct bwn_mac *); -static void bwn_phy_lp_rccal_r12(struct bwn_mac *); +static int bwn_phy_lp_b2062_init(struct bwn_mac *); +static int bwn_phy_lp_b2063_init(struct bwn_mac *); +static int bwn_phy_lp_rxcal_r2(struct bwn_mac *); +static int bwn_phy_lp_rccal_r12(struct bwn_mac *); static void bwn_phy_lp_set_rccap(struct bwn_mac *); static uint32_t bwn_phy_lp_roundup(uint32_t, uint32_t, uint8_t); static void bwn_phy_lp_b2062_reset_pllbias(struct bwn_mac *); static void bwn_phy_lp_b2062_vco_calib(struct bwn_mac *); static void bwn_tab_write_multi(struct bwn_mac *, uint32_t, int, const void *); static void bwn_tab_read_multi(struct bwn_mac *, uint32_t, int, void *); static struct bwn_txgain bwn_phy_lp_get_txgain(struct bwn_mac *); static uint8_t bwn_phy_lp_get_bbmult(struct bwn_mac *); static void bwn_phy_lp_set_txgain(struct bwn_mac *, struct bwn_txgain *); static void bwn_phy_lp_set_bbmult(struct bwn_mac *, uint8_t); static void bwn_phy_lp_set_trsw_over(struct bwn_mac *, uint8_t, uint8_t); static void bwn_phy_lp_set_rxgain(struct bwn_mac *, uint32_t); static void bwn_phy_lp_set_deaf(struct bwn_mac *, uint8_t); static int bwn_phy_lp_calc_rx_iq_comp(struct bwn_mac *, uint16_t); static void bwn_phy_lp_clear_deaf(struct bwn_mac *, uint8_t); static void bwn_phy_lp_tblinit_r01(struct bwn_mac *); static void bwn_phy_lp_tblinit_r2(struct bwn_mac *); static void bwn_phy_lp_tblinit_txgain(struct bwn_mac *); static void bwn_tab_write(struct bwn_mac *, uint32_t, uint32_t); static void bwn_phy_lp_b2062_tblinit(struct bwn_mac *); static void bwn_phy_lp_b2063_tblinit(struct bwn_mac *); static int bwn_phy_lp_loopback(struct bwn_mac *); static void bwn_phy_lp_set_rxgain_idx(struct bwn_mac *, uint16_t); static void bwn_phy_lp_ddfs_turnon(struct bwn_mac *, int, int, int, int, int); static uint8_t bwn_phy_lp_rx_iq_est(struct bwn_mac *, uint16_t, uint8_t, struct bwn_phy_lp_iq_est *); static void bwn_phy_lp_ddfs_turnoff(struct bwn_mac *); static uint32_t bwn_tab_read(struct bwn_mac *, uint32_t); static void bwn_phy_lp_set_txgain_dac(struct bwn_mac *, uint16_t); static void bwn_phy_lp_set_txgain_pa(struct bwn_mac *, uint16_t); static void bwn_phy_lp_set_txgain_override(struct bwn_mac *); static uint16_t bwn_phy_lp_get_pa_gain(struct bwn_mac *); static uint8_t bwn_nbits(int32_t); static void bwn_phy_lp_gaintbl_write_multi(struct bwn_mac *, int, int, struct bwn_txgain_entry *); static void bwn_phy_lp_gaintbl_write(struct bwn_mac *, int, struct bwn_txgain_entry); static void bwn_phy_lp_gaintbl_write_r2(struct bwn_mac *, int, struct bwn_txgain_entry); static void bwn_phy_lp_gaintbl_write_r01(struct bwn_mac *, int, struct bwn_txgain_entry); static const uint8_t bwn_b2063_chantable_data[33][12] = { { 0x6f, 0x3c, 0x3c, 0x4, 0x5, 0x5, 0x5, 0x5, 0x77, 0x80, 0x80, 0x70 }, { 0x6f, 0x2c, 0x2c, 0x4, 0x5, 0x5, 0x5, 0x5, 0x77, 0x80, 0x80, 0x70 }, { 0x6f, 0x1c, 0x1c, 0x4, 0x5, 0x5, 0x5, 0x5, 0x77, 0x80, 0x80, 0x70 }, { 0x6e, 0x1c, 0x1c, 0x4, 0x5, 0x5, 0x5, 0x5, 0x77, 0x80, 0x80, 0x70 }, { 0x6e, 0xc, 0xc, 0x4, 0x5, 0x5, 0x5, 0x5, 0x77, 0x80, 0x80, 0x70 }, { 0x6a, 0xc, 0xc, 0, 0x2, 0x5, 0xd, 0xd, 0x77, 0x80, 0x20, 0 }, { 0x6a, 0xc, 0xc, 0, 0x1, 0x5, 0xd, 0xc, 0x77, 0x80, 0x20, 0 }, { 0x6a, 0xc, 0xc, 0, 0x1, 0x4, 0xc, 0xc, 0x77, 0x80, 0x20, 0 }, { 0x69, 0xc, 0xc, 0, 0x1, 0x4, 0xc, 0xc, 0x77, 0x70, 0x20, 0 }, { 0x69, 0xc, 0xc, 0, 0x1, 0x4, 0xb, 0xc, 0x77, 0x70, 0x20, 0 }, { 0x69, 0xc, 0xc, 0, 0, 0x4, 0xb, 0xb, 0x77, 0x60, 0x20, 0 }, { 0x69, 0xc, 0xc, 0, 0, 0x3, 0xa, 0xb, 0x77, 0x60, 0x20, 0 }, { 0x69, 0xc, 0xc, 0, 0, 0x3, 0xa, 0xa, 0x77, 0x60, 0x20, 0 }, { 0x68, 0xc, 0xc, 0, 0, 0x2, 0x9, 0x9, 0x77, 0x60, 0x20, 0 }, { 0x68, 0xc, 0xc, 0, 0, 0x1, 0x8, 0x8, 0x77, 0x50, 0x10, 0 }, { 0x67, 0xc, 0xc, 0, 0, 0, 0x8, 0x8, 0x77, 0x50, 0x10, 0 }, { 0x64, 0xc, 0xc, 0, 0, 0, 0x2, 0x1, 0x77, 0x20, 0, 0 }, { 0x64, 0xc, 0xc, 0, 0, 0, 0x1, 0x1, 0x77, 0x20, 0, 0 }, { 0x63, 0xc, 0xc, 0, 0, 0, 0x1, 0, 0x77, 0x10, 0, 0 }, { 0x63, 0xc, 0xc, 0, 0, 0, 0, 0, 0x77, 0x10, 0, 0 }, { 0x62, 0xc, 0xc, 0, 0, 0, 0, 0, 0x77, 0x10, 0, 0 }, { 0x62, 0xc, 0xc, 0, 0, 0, 0, 0, 0x77, 0, 0, 0 }, { 0x61, 0xc, 0xc, 0, 0, 0, 0, 0, 0x77, 0, 0, 0 }, { 0x60, 0xc, 0xc, 0, 0, 0, 0, 0, 0x77, 0, 0, 0 }, { 0x6e, 0xc, 0xc, 0, 0x9, 0xe, 0xf, 0xf, 0x77, 0xc0, 0x50, 0 }, { 0x6e, 0xc, 0xc, 0, 0x9, 0xd, 0xf, 0xf, 0x77, 0xb0, 0x50, 0 }, { 0x6e, 0xc, 0xc, 0, 0x8, 0xc, 0xf, 0xf, 0x77, 0xb0, 0x50, 0 }, { 0x6d, 0xc, 0xc, 0, 0x8, 0xc, 0xf, 0xf, 0x77, 0xa0, 0x40, 0 }, { 0x6d, 0xc, 0xc, 0, 0x8, 0xb, 0xf, 0xf, 0x77, 0xa0, 0x40, 0 }, { 0x6d, 0xc, 0xc, 0, 0x8, 0xa, 0xf, 0xf, 0x77, 0xa0, 0x40, 0 }, { 0x6c, 0xc, 0xc, 0, 0x7, 0x9, 0xf, 0xf, 0x77, 0x90, 0x40, 0 }, { 0x6c, 0xc, 0xc, 0, 0x6, 0x8, 0xf, 0xf, 0x77, 0x90, 0x40, 0 }, { 0x6c, 0xc, 0xc, 0, 0x5, 0x8, 0xf, 0xf, 0x77, 0x90, 0x40, 0 } }; static const struct bwn_b206x_chan bwn_b2063_chantable[] = { { 1, 2412, bwn_b2063_chantable_data[0] }, { 2, 2417, bwn_b2063_chantable_data[0] }, { 3, 2422, bwn_b2063_chantable_data[0] }, { 4, 2427, bwn_b2063_chantable_data[1] }, { 5, 2432, bwn_b2063_chantable_data[1] }, { 6, 2437, bwn_b2063_chantable_data[1] }, { 7, 2442, bwn_b2063_chantable_data[1] }, { 8, 2447, bwn_b2063_chantable_data[1] }, { 9, 2452, bwn_b2063_chantable_data[2] }, { 10, 2457, bwn_b2063_chantable_data[2] }, { 11, 2462, bwn_b2063_chantable_data[3] }, { 12, 2467, bwn_b2063_chantable_data[3] }, { 13, 2472, bwn_b2063_chantable_data[3] }, { 14, 2484, bwn_b2063_chantable_data[4] }, { 34, 5170, bwn_b2063_chantable_data[5] }, { 36, 5180, bwn_b2063_chantable_data[6] }, { 38, 5190, bwn_b2063_chantable_data[7] }, { 40, 5200, bwn_b2063_chantable_data[8] }, { 42, 5210, bwn_b2063_chantable_data[9] }, { 44, 5220, bwn_b2063_chantable_data[10] }, { 46, 5230, bwn_b2063_chantable_data[11] }, { 48, 5240, bwn_b2063_chantable_data[12] }, { 52, 5260, bwn_b2063_chantable_data[13] }, { 56, 5280, bwn_b2063_chantable_data[14] }, { 60, 5300, bwn_b2063_chantable_data[14] }, { 64, 5320, bwn_b2063_chantable_data[15] }, { 100, 5500, bwn_b2063_chantable_data[16] }, { 104, 5520, bwn_b2063_chantable_data[17] }, { 108, 5540, bwn_b2063_chantable_data[18] }, { 112, 5560, bwn_b2063_chantable_data[19] }, { 116, 5580, bwn_b2063_chantable_data[20] }, { 120, 5600, bwn_b2063_chantable_data[21] }, { 124, 5620, bwn_b2063_chantable_data[21] }, { 128, 5640, bwn_b2063_chantable_data[22] }, { 132, 5660, bwn_b2063_chantable_data[22] }, { 136, 5680, bwn_b2063_chantable_data[22] }, { 140, 5700, bwn_b2063_chantable_data[23] }, { 149, 5745, bwn_b2063_chantable_data[23] }, { 153, 5765, bwn_b2063_chantable_data[23] }, { 157, 5785, bwn_b2063_chantable_data[23] }, { 161, 5805, bwn_b2063_chantable_data[23] }, { 165, 5825, bwn_b2063_chantable_data[23] }, { 184, 4920, bwn_b2063_chantable_data[24] }, { 188, 4940, bwn_b2063_chantable_data[25] }, { 192, 4960, bwn_b2063_chantable_data[26] }, { 196, 4980, bwn_b2063_chantable_data[27] }, { 200, 5000, bwn_b2063_chantable_data[28] }, { 204, 5020, bwn_b2063_chantable_data[29] }, { 208, 5040, bwn_b2063_chantable_data[30] }, { 212, 5060, bwn_b2063_chantable_data[31] }, { 216, 5080, bwn_b2063_chantable_data[32] } }; static const uint8_t bwn_b2062_chantable_data[22][12] = { { 0xff, 0xff, 0xb5, 0x1b, 0x24, 0x32, 0x32, 0x88, 0x88, 0, 0, 0 }, { 0, 0x22, 0x20, 0x84, 0x3c, 0x77, 0x35, 0xff, 0x88, 0, 0, 0 }, { 0, 0x11, 0x10, 0x83, 0x3c, 0x77, 0x35, 0xff, 0x88, 0, 0, 0 }, { 0, 0, 0, 0x83, 0x3c, 0x77, 0x35, 0xff, 0x88, 0, 0, 0 }, { 0, 0x11, 0x20, 0x83, 0x3c, 0x77, 0x35, 0xff, 0x88, 0, 0, 0 }, { 0, 0x11, 0x10, 0x84, 0x3c, 0x77, 0x35, 0xff, 0x88, 0, 0, 0 }, { 0, 0x11, 0, 0x83, 0x3c, 0x77, 0x35, 0xff, 0x88, 0, 0, 0 }, { 0, 0, 0, 0x63, 0x3c, 0x77, 0x35, 0xff, 0x88, 0, 0, 0 }, { 0, 0, 0, 0x62, 0x3c, 0x77, 0x35, 0xff, 0x88, 0, 0, 0 }, { 0, 0, 0, 0x30, 0x3c, 0x77, 0x37, 0xff, 0x88, 0, 0, 0 }, { 0, 0, 0, 0x20, 0x3c, 0x77, 0x37, 0xff, 0x88, 0, 0, 0 }, { 0, 0, 0, 0x10, 0x3c, 0x77, 0x37, 0xff, 0x88, 0, 0, 0 }, { 0, 0, 0, 0, 0x3c, 0x77, 0x37, 0xff, 0x88, 0, 0, 0 }, { 0x55, 0x77, 0x90, 0xf7, 0x3c, 0x77, 0x35, 0xff, 0xff, 0, 0, 0 }, { 0x44, 0x77, 0x80, 0xe7, 0x3c, 0x77, 0x35, 0xff, 0xff, 0, 0, 0 }, { 0x44, 0x66, 0x80, 0xe7, 0x3c, 0x77, 0x35, 0xff, 0xff, 0, 0, 0 }, { 0x33, 0x66, 0x70, 0xc7, 0x3c, 0x77, 0x35, 0xff, 0xff, 0, 0, 0 }, { 0x22, 0x55, 0x60, 0xd7, 0x3c, 0x77, 0x35, 0xff, 0xff, 0, 0, 0 }, { 0x22, 0x55, 0x60, 0xc7, 0x3c, 0x77, 0x35, 0xff, 0xff, 0, 0, 0 }, { 0x22, 0x44, 0x50, 0xc7, 0x3c, 0x77, 0x35, 0xff, 0xff, 0, 0, 0 }, { 0x11, 0x44, 0x50, 0xa5, 0x3c, 0x77, 0x35, 0xff, 0x88, 0, 0, 0 }, { 0, 0x44, 0x40, 0xb6, 0x3c, 0x77, 0x35, 0xff, 0x88, 0, 0, 0 } }; static const struct bwn_b206x_chan bwn_b2062_chantable[] = { { 1, 2412, bwn_b2062_chantable_data[0] }, { 2, 2417, bwn_b2062_chantable_data[0] }, { 3, 2422, bwn_b2062_chantable_data[0] }, { 4, 2427, bwn_b2062_chantable_data[0] }, { 5, 2432, bwn_b2062_chantable_data[0] }, { 6, 2437, bwn_b2062_chantable_data[0] }, { 7, 2442, bwn_b2062_chantable_data[0] }, { 8, 2447, bwn_b2062_chantable_data[0] }, { 9, 2452, bwn_b2062_chantable_data[0] }, { 10, 2457, bwn_b2062_chantable_data[0] }, { 11, 2462, bwn_b2062_chantable_data[0] }, { 12, 2467, bwn_b2062_chantable_data[0] }, { 13, 2472, bwn_b2062_chantable_data[0] }, { 14, 2484, bwn_b2062_chantable_data[0] }, { 34, 5170, bwn_b2062_chantable_data[1] }, { 38, 5190, bwn_b2062_chantable_data[2] }, { 42, 5210, bwn_b2062_chantable_data[2] }, { 46, 5230, bwn_b2062_chantable_data[3] }, { 36, 5180, bwn_b2062_chantable_data[4] }, { 40, 5200, bwn_b2062_chantable_data[5] }, { 44, 5220, bwn_b2062_chantable_data[6] }, { 48, 5240, bwn_b2062_chantable_data[3] }, { 52, 5260, bwn_b2062_chantable_data[3] }, { 56, 5280, bwn_b2062_chantable_data[3] }, { 60, 5300, bwn_b2062_chantable_data[7] }, { 64, 5320, bwn_b2062_chantable_data[8] }, { 100, 5500, bwn_b2062_chantable_data[9] }, { 104, 5520, bwn_b2062_chantable_data[10] }, { 108, 5540, bwn_b2062_chantable_data[10] }, { 112, 5560, bwn_b2062_chantable_data[10] }, { 116, 5580, bwn_b2062_chantable_data[11] }, { 120, 5600, bwn_b2062_chantable_data[12] }, { 124, 5620, bwn_b2062_chantable_data[12] }, { 128, 5640, bwn_b2062_chantable_data[12] }, { 132, 5660, bwn_b2062_chantable_data[12] }, { 136, 5680, bwn_b2062_chantable_data[12] }, { 140, 5700, bwn_b2062_chantable_data[12] }, { 149, 5745, bwn_b2062_chantable_data[12] }, { 153, 5765, bwn_b2062_chantable_data[12] }, { 157, 5785, bwn_b2062_chantable_data[12] }, { 161, 5805, bwn_b2062_chantable_data[12] }, { 165, 5825, bwn_b2062_chantable_data[12] }, { 184, 4920, bwn_b2062_chantable_data[13] }, { 188, 4940, bwn_b2062_chantable_data[14] }, { 192, 4960, bwn_b2062_chantable_data[15] }, { 196, 4980, bwn_b2062_chantable_data[16] }, { 200, 5000, bwn_b2062_chantable_data[17] }, { 204, 5020, bwn_b2062_chantable_data[18] }, { 208, 5040, bwn_b2062_chantable_data[19] }, { 212, 5060, bwn_b2062_chantable_data[20] }, { 216, 5080, bwn_b2062_chantable_data[21] } }; /* for LP PHY */ static const struct bwn_rxcompco bwn_rxcompco_5354[] = { { 1, -66, 15 }, { 2, -66, 15 }, { 3, -66, 15 }, { 4, -66, 15 }, { 5, -66, 15 }, { 6, -66, 15 }, { 7, -66, 14 }, { 8, -66, 14 }, { 9, -66, 14 }, { 10, -66, 14 }, { 11, -66, 14 }, { 12, -66, 13 }, { 13, -66, 13 }, { 14, -66, 13 }, }; /* for LP PHY */ static const struct bwn_rxcompco bwn_rxcompco_r12[] = { { 1, -64, 13 }, { 2, -64, 13 }, { 3, -64, 13 }, { 4, -64, 13 }, { 5, -64, 12 }, { 6, -64, 12 }, { 7, -64, 12 }, { 8, -64, 12 }, { 9, -64, 12 }, { 10, -64, 11 }, { 11, -64, 11 }, { 12, -64, 11 }, { 13, -64, 11 }, { 14, -64, 10 }, { 34, -62, 24 }, { 38, -62, 24 }, { 42, -62, 24 }, { 46, -62, 23 }, { 36, -62, 24 }, { 40, -62, 24 }, { 44, -62, 23 }, { 48, -62, 23 }, { 52, -62, 23 }, { 56, -62, 22 }, { 60, -62, 22 }, { 64, -62, 22 }, { 100, -62, 16 }, { 104, -62, 16 }, { 108, -62, 15 }, { 112, -62, 14 }, { 116, -62, 14 }, { 120, -62, 13 }, { 124, -62, 12 }, { 128, -62, 12 }, { 132, -62, 12 }, { 136, -62, 11 }, { 140, -62, 10 }, { 149, -61, 9 }, { 153, -61, 9 }, { 157, -61, 9 }, { 161, -61, 8 }, { 165, -61, 8 }, { 184, -62, 25 }, { 188, -62, 25 }, { 192, -62, 25 }, { 196, -62, 25 }, { 200, -62, 25 }, { 204, -62, 25 }, { 208, -62, 25 }, { 212, -62, 25 }, { 216, -62, 26 }, }; static const struct bwn_rxcompco bwn_rxcompco_r2 = { 0, -64, 0 }; static const uint8_t bwn_tab_sigsq_tbl[] = { 0xde, 0xdc, 0xda, 0xd8, 0xd6, 0xd4, 0xd2, 0xcf, 0xcd, 0xca, 0xc7, 0xc4, 0xc1, 0xbe, 0xbe, 0xbe, 0xbe, 0xbe, 0xbe, 0xbe, 0xbe, 0xbe, 0xbe, 0xbe, 0xbe, 0xbe, 0x00, 0xbe, 0xbe, 0xbe, 0xbe, 0xbe, 0xbe, 0xbe, 0xbe, 0xbe, 0xbe, 0xbe, 0xbe, 0xbe, 0xc1, 0xc4, 0xc7, 0xca, 0xcd, 0xcf, 0xd2, 0xd4, 0xd6, 0xd8, 0xda, 0xdc, 0xde, }; static const uint8_t bwn_tab_pllfrac_tbl[] = { 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x00, 0x00, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, }; static const uint16_t bwn_tabl_iqlocal_tbl[] = { 0x0200, 0x0300, 0x0400, 0x0600, 0x0800, 0x0b00, 0x1000, 0x1001, 0x1002, 0x1003, 0x1004, 0x1005, 0x1006, 0x1007, 0x1707, 0x2007, 0x2d07, 0x4007, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0200, 0x0300, 0x0400, 0x0600, 0x0800, 0x0b00, 0x1000, 0x1001, 0x1002, 0x1003, 0x1004, 0x1005, 0x1006, 0x1007, 0x1707, 0x2007, 0x2d07, 0x4007, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x4000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, }; void bwn_phy_lp_init_pre(struct bwn_mac *mac) { struct bwn_phy *phy = &mac->mac_phy; struct bwn_phy_lp *plp = &phy->phy_lp; plp->plp_antenna = BWN_ANT_DEFAULT; } int bwn_phy_lp_init(struct bwn_mac *mac) { static const struct bwn_stxtable tables[] = { { 2, 6, 0x3d, 3, 0x01 }, { 1, 12, 0x4c, 1, 0x01 }, { 1, 8, 0x50, 0, 0x7f }, { 0, 8, 0x44, 0, 0xff }, { 1, 0, 0x4a, 0, 0xff }, { 0, 4, 0x4d, 0, 0xff }, { 1, 4, 0x4e, 0, 0xff }, { 0, 12, 0x4f, 0, 0x0f }, { 1, 0, 0x4f, 4, 0x0f }, { 3, 0, 0x49, 0, 0x0f }, { 4, 3, 0x46, 4, 0x07 }, { 3, 15, 0x46, 0, 0x01 }, { 4, 0, 0x46, 1, 0x07 }, { 3, 8, 0x48, 4, 0x07 }, { 3, 11, 0x48, 0, 0x0f }, { 3, 4, 0x49, 4, 0x0f }, { 2, 15, 0x45, 0, 0x01 }, { 5, 13, 0x52, 4, 0x07 }, { 6, 0, 0x52, 7, 0x01 }, { 5, 3, 0x41, 5, 0x07 }, { 5, 6, 0x41, 0, 0x0f }, { 5, 10, 0x42, 5, 0x07 }, { 4, 15, 0x42, 0, 0x01 }, { 5, 0, 0x42, 1, 0x07 }, { 4, 11, 0x43, 4, 0x0f }, { 4, 7, 0x43, 0, 0x0f }, { 4, 6, 0x45, 1, 0x01 }, { 2, 7, 0x40, 4, 0x0f }, { 2, 11, 0x40, 0, 0x0f } }; struct bwn_phy_lp *plp = &mac->mac_phy.phy_lp; struct bwn_softc *sc = mac->mac_sc; const struct bwn_stxtable *st; struct ieee80211com *ic = &sc->sc_ic; int i, error; uint16_t tmp; - bwn_phy_lp_readsprom(mac); /* XXX bad place */ + /* All LP-PHY devices have a PMU */ + if (sc->sc_pmu == NULL) { + device_printf(sc->sc_dev, "no PMU; cannot configure PAREF " + "LDO\n"); + return (ENXIO); + } + + if ((error = bwn_phy_lp_readsprom(mac))) + return (error); + bwn_phy_lp_bbinit(mac); /* initialize RF */ BWN_PHY_SET(mac, BWN_PHY_4WIRECTL, 0x2); DELAY(1); BWN_PHY_MASK(mac, BWN_PHY_4WIRECTL, 0xfffd); DELAY(1); - if (mac->mac_phy.rf_ver == 0x2062) - bwn_phy_lp_b2062_init(mac); - else { - bwn_phy_lp_b2063_init(mac); + if (mac->mac_phy.rf_ver == 0x2062) { + if ((error = bwn_phy_lp_b2062_init(mac))) + return (error); + } else { + if ((error = bwn_phy_lp_b2063_init(mac))) + return (error); /* synchronize stx table. */ for (i = 0; i < N(tables); i++) { st = &tables[i]; tmp = BWN_RF_READ(mac, st->st_rfaddr); tmp >>= st->st_rfshift; tmp <<= st->st_physhift; BWN_PHY_SETMASK(mac, BWN_PHY_OFDM(0xf2 + st->st_phyoffset), ~(st->st_mask << st->st_physhift), tmp); } BWN_PHY_WRITE(mac, BWN_PHY_OFDM(0xf0), 0x5f80); BWN_PHY_WRITE(mac, BWN_PHY_OFDM(0xf1), 0); } /* calibrate RC */ - if (mac->mac_phy.rev >= 2) - bwn_phy_lp_rxcal_r2(mac); - else if (!plp->plp_rccap) { - if (IEEE80211_IS_CHAN_2GHZ(ic->ic_curchan)) - bwn_phy_lp_rccal_r12(mac); + if (mac->mac_phy.rev >= 2) { + if ((error = bwn_phy_lp_rxcal_r2(mac))) + return (error); + } else if (!plp->plp_rccap) { + if (IEEE80211_IS_CHAN_2GHZ(ic->ic_curchan)) { + if ((error = bwn_phy_lp_rccal_r12(mac))) + return (error); + } } else bwn_phy_lp_set_rccap(mac); error = bwn_phy_lp_switch_channel(mac, 7); if (error) device_printf(sc->sc_dev, "failed to change channel 7 (%d)\n", error); bwn_phy_lp_txpctl_init(mac); bwn_phy_lp_calib(mac); return (0); } uint16_t bwn_phy_lp_read(struct bwn_mac *mac, uint16_t reg) { BWN_WRITE_2(mac, BWN_PHYCTL, reg); return (BWN_READ_2(mac, BWN_PHYDATA)); } void bwn_phy_lp_write(struct bwn_mac *mac, uint16_t reg, uint16_t value) { BWN_WRITE_2(mac, BWN_PHYCTL, reg); BWN_WRITE_2(mac, BWN_PHYDATA, value); } void bwn_phy_lp_maskset(struct bwn_mac *mac, uint16_t reg, uint16_t mask, uint16_t set) { BWN_WRITE_2(mac, BWN_PHYCTL, reg); BWN_WRITE_2(mac, BWN_PHYDATA, (BWN_READ_2(mac, BWN_PHYDATA) & mask) | set); } uint16_t bwn_phy_lp_rf_read(struct bwn_mac *mac, uint16_t reg) { KASSERT(reg != 1, ("unaccessible register %d", reg)); if (mac->mac_phy.rev < 2 && reg != 0x4001) reg |= 0x100; if (mac->mac_phy.rev >= 2) reg |= 0x200; BWN_WRITE_2(mac, BWN_RFCTL, reg); return BWN_READ_2(mac, BWN_RFDATALO); } void bwn_phy_lp_rf_write(struct bwn_mac *mac, uint16_t reg, uint16_t value) { KASSERT(reg != 1, ("unaccessible register %d", reg)); BWN_WRITE_2(mac, BWN_RFCTL, reg); BWN_WRITE_2(mac, BWN_RFDATALO, value); } void bwn_phy_lp_rf_onoff(struct bwn_mac *mac, int on) { if (on) { BWN_PHY_MASK(mac, BWN_PHY_RF_OVERRIDE_0, 0xe0ff); BWN_PHY_MASK(mac, BWN_PHY_RF_OVERRIDE_2, (mac->mac_phy.rev >= 2) ? 0xf7f7 : 0xffe7); return; } if (mac->mac_phy.rev >= 2) { BWN_PHY_MASK(mac, BWN_PHY_RF_OVERRIDE_VAL_0, 0x83ff); BWN_PHY_SET(mac, BWN_PHY_RF_OVERRIDE_0, 0x1f00); BWN_PHY_MASK(mac, BWN_PHY_AFE_DDFS, 0x80ff); BWN_PHY_MASK(mac, BWN_PHY_RF_OVERRIDE_2_VAL, 0xdfff); BWN_PHY_SET(mac, BWN_PHY_RF_OVERRIDE_2, 0x0808); return; } BWN_PHY_MASK(mac, BWN_PHY_RF_OVERRIDE_VAL_0, 0xe0ff); BWN_PHY_SET(mac, BWN_PHY_RF_OVERRIDE_0, 0x1f00); BWN_PHY_MASK(mac, BWN_PHY_RF_OVERRIDE_2_VAL, 0xfcff); BWN_PHY_SET(mac, BWN_PHY_RF_OVERRIDE_2, 0x0018); } int bwn_phy_lp_switch_channel(struct bwn_mac *mac, uint32_t chan) { struct bwn_phy *phy = &mac->mac_phy; struct bwn_phy_lp *plp = &phy->phy_lp; int error; if (phy->rf_ver == 0x2063) { error = bwn_phy_lp_b2063_switch_channel(mac, chan); if (error) return (error); } else { error = bwn_phy_lp_b2062_switch_channel(mac, chan); if (error) return (error); bwn_phy_lp_set_anafilter(mac, chan); bwn_phy_lp_set_gaintbl(mac, ieee80211_ieee2mhz(chan, 0)); } plp->plp_chan = chan; BWN_WRITE_2(mac, BWN_CHANNEL, chan); return (0); } uint32_t bwn_phy_lp_get_default_chan(struct bwn_mac *mac) { struct bwn_softc *sc = mac->mac_sc; struct ieee80211com *ic = &sc->sc_ic; return (IEEE80211_IS_CHAN_2GHZ(ic->ic_curchan) ? 1 : 36); } void bwn_phy_lp_set_antenna(struct bwn_mac *mac, int antenna) { struct bwn_phy *phy = &mac->mac_phy; struct bwn_phy_lp *plp = &phy->phy_lp; if (phy->rev >= 2 || antenna > BWN_ANTAUTO1) return; bwn_hf_write(mac, bwn_hf_read(mac) & ~BWN_HF_UCODE_ANTDIV_HELPER); BWN_PHY_SETMASK(mac, BWN_PHY_CRSGAIN_CTL, 0xfffd, antenna & 0x2); BWN_PHY_SETMASK(mac, BWN_PHY_CRSGAIN_CTL, 0xfffe, antenna & 0x1); bwn_hf_write(mac, bwn_hf_read(mac) | BWN_HF_UCODE_ANTDIV_HELPER); plp->plp_antenna = antenna; } void bwn_phy_lp_task_60s(struct bwn_mac *mac) { bwn_phy_lp_calib(mac); } -static void +static int bwn_phy_lp_readsprom(struct bwn_mac *mac) { struct bwn_phy_lp *plp = &mac->mac_phy.phy_lp; struct bwn_softc *sc = mac->mac_sc; struct ieee80211com *ic = &sc->sc_ic; +#define BWN_PHY_LP_READVAR(_dev, _type, _name, _result) \ +do { \ + int error; \ + \ + error = bhnd_nvram_getvar_ ##_type((_dev), (_name), (_result)); \ + if (error) { \ + device_printf((_dev), "NVRAM variable %s unreadable: " \ + "%d\n", (_name), error); \ + return (error); \ + } \ +} while(0) + if (IEEE80211_IS_CHAN_2GHZ(ic->ic_curchan)) { - plp->plp_txisoband_m = siba_sprom_get_tri2g(sc->sc_dev); - plp->plp_bxarch = siba_sprom_get_bxa2g(sc->sc_dev); - plp->plp_rxpwroffset = siba_sprom_get_rxpo2g(sc->sc_dev); - plp->plp_rssivf = siba_sprom_get_rssismf2g(sc->sc_dev); - plp->plp_rssivc = siba_sprom_get_rssismc2g(sc->sc_dev); - plp->plp_rssigs = siba_sprom_get_rssisav2g(sc->sc_dev); - return; + BWN_PHY_LP_READVAR(sc->sc_dev, uint8, BHND_NVAR_TRI2G, + &plp->plp_txisoband_m); + BWN_PHY_LP_READVAR(sc->sc_dev, uint8, BHND_NVAR_BXA2G, + &plp->plp_bxarch); + BWN_PHY_LP_READVAR(sc->sc_dev, int8, BHND_NVAR_RXPO2G, + &plp->plp_rxpwroffset); + BWN_PHY_LP_READVAR(sc->sc_dev, uint8, BHND_NVAR_RSSISMF2G, + &plp->plp_rssivf); + BWN_PHY_LP_READVAR(sc->sc_dev, uint8, BHND_NVAR_RSSISMC2G, + &plp->plp_rssivc); + BWN_PHY_LP_READVAR(sc->sc_dev, uint8, BHND_NVAR_RSSISAV2G, + &plp->plp_rssigs); + + return (0); } - plp->plp_txisoband_l = siba_sprom_get_tri5gl(sc->sc_dev); - plp->plp_txisoband_m = siba_sprom_get_tri5g(sc->sc_dev); - plp->plp_txisoband_h = siba_sprom_get_tri5gh(sc->sc_dev); - plp->plp_bxarch = siba_sprom_get_bxa5g(sc->sc_dev); - plp->plp_rxpwroffset = siba_sprom_get_rxpo5g(sc->sc_dev); - plp->plp_rssivf = siba_sprom_get_rssismf5g(sc->sc_dev); - plp->plp_rssivc = siba_sprom_get_rssismc5g(sc->sc_dev); - plp->plp_rssigs = siba_sprom_get_rssisav5g(sc->sc_dev); + BWN_PHY_LP_READVAR(sc->sc_dev, uint8, BHND_NVAR_TRI5GL, + &plp->plp_txisoband_l); + BWN_PHY_LP_READVAR(sc->sc_dev, uint8, BHND_NVAR_TRI5G, + &plp->plp_txisoband_m); + BWN_PHY_LP_READVAR(sc->sc_dev, uint8, BHND_NVAR_TRI5GH, + &plp->plp_txisoband_h); + BWN_PHY_LP_READVAR(sc->sc_dev, uint8, BHND_NVAR_BXA5G, + &plp->plp_bxarch); + BWN_PHY_LP_READVAR(sc->sc_dev, int8, BHND_NVAR_RXPO5G, + &plp->plp_rxpwroffset); + BWN_PHY_LP_READVAR(sc->sc_dev, uint8, BHND_NVAR_RSSISMF5G, + &plp->plp_rssivf); + BWN_PHY_LP_READVAR(sc->sc_dev, uint8, BHND_NVAR_RSSISMC5G, + &plp->plp_rssivc); + BWN_PHY_LP_READVAR(sc->sc_dev, uint8, BHND_NVAR_RSSISAV5G, + &plp->plp_rssigs); + +#undef BWN_PHY_LP_READVAR + + return (0); } static void bwn_phy_lp_bbinit(struct bwn_mac *mac) { bwn_phy_lp_tblinit(mac); if (mac->mac_phy.rev >= 2) bwn_phy_lp_bbinit_r2(mac); else bwn_phy_lp_bbinit_r01(mac); } static void bwn_phy_lp_txpctl_init(struct bwn_mac *mac) { struct bwn_txgain gain_2ghz = { 4, 12, 12, 0 }; struct bwn_txgain gain_5ghz = { 7, 15, 14, 0 }; struct bwn_softc *sc = mac->mac_sc; struct ieee80211com *ic = &sc->sc_ic; bwn_phy_lp_set_txgain(mac, IEEE80211_IS_CHAN_2GHZ(ic->ic_curchan) ? &gain_2ghz : &gain_5ghz); bwn_phy_lp_set_bbmult(mac, 150); } static void bwn_phy_lp_calib(struct bwn_mac *mac) { struct bwn_phy_lp *plp = &mac->mac_phy.phy_lp; struct bwn_softc *sc = mac->mac_sc; struct ieee80211com *ic = &sc->sc_ic; const struct bwn_rxcompco *rc = NULL; struct bwn_txgain ogain; int i, omode, oafeovr, orf, obbmult; uint8_t mode, fc = 0; if (plp->plp_chanfullcal != plp->plp_chan) { plp->plp_chanfullcal = plp->plp_chan; fc = 1; } bwn_mac_suspend(mac); /* BlueTooth Coexistance Override */ BWN_WRITE_2(mac, BWN_BTCOEX_CTL, 0x3); BWN_WRITE_2(mac, BWN_BTCOEX_TXCTL, 0xff); if (mac->mac_phy.rev >= 2) bwn_phy_lp_digflt_save(mac); bwn_phy_lp_get_txpctlmode(mac); mode = plp->plp_txpctlmode; bwn_phy_lp_set_txpctlmode(mac, BWN_PHYLP_TXPCTL_OFF); if (mac->mac_phy.rev == 0 && mode != BWN_PHYLP_TXPCTL_OFF) bwn_phy_lp_bugfix(mac); if (mac->mac_phy.rev >= 2 && fc == 1) { bwn_phy_lp_get_txpctlmode(mac); omode = plp->plp_txpctlmode; oafeovr = BWN_PHY_READ(mac, BWN_PHY_AFE_CTL_OVR) & 0x40; if (oafeovr) ogain = bwn_phy_lp_get_txgain(mac); orf = BWN_PHY_READ(mac, BWN_PHY_RF_PWR_OVERRIDE) & 0xff; obbmult = bwn_phy_lp_get_bbmult(mac); bwn_phy_lp_set_txpctlmode(mac, BWN_PHYLP_TXPCTL_OFF); if (oafeovr) bwn_phy_lp_set_txgain(mac, &ogain); bwn_phy_lp_set_bbmult(mac, obbmult); bwn_phy_lp_set_txpctlmode(mac, omode); BWN_PHY_SETMASK(mac, BWN_PHY_RF_PWR_OVERRIDE, 0xff00, orf); } bwn_phy_lp_set_txpctlmode(mac, mode); if (mac->mac_phy.rev >= 2) bwn_phy_lp_digflt_restore(mac); /* do RX IQ Calculation; assumes that noise is true. */ - if (siba_get_chipid(sc->sc_dev) == 0x5354) { + if (sc->sc_cid.chip_id == BHND_CHIPID_BCM5354) { for (i = 0; i < N(bwn_rxcompco_5354); i++) { if (bwn_rxcompco_5354[i].rc_chan == plp->plp_chan) rc = &bwn_rxcompco_5354[i]; } } else if (mac->mac_phy.rev >= 2) rc = &bwn_rxcompco_r2; else { for (i = 0; i < N(bwn_rxcompco_r12); i++) { if (bwn_rxcompco_r12[i].rc_chan == plp->plp_chan) rc = &bwn_rxcompco_r12[i]; } } if (rc == NULL) goto fail; BWN_PHY_SETMASK(mac, BWN_PHY_RX_COMP_COEFF_S, 0xff00, rc->rc_c1); BWN_PHY_SETMASK(mac, BWN_PHY_RX_COMP_COEFF_S, 0x00ff, rc->rc_c0 << 8); bwn_phy_lp_set_trsw_over(mac, 1 /* TX */, 0 /* RX */); if (IEEE80211_IS_CHAN_2GHZ(ic->ic_curchan)) { BWN_PHY_SET(mac, BWN_PHY_RF_OVERRIDE_0, 0x8); BWN_PHY_SETMASK(mac, BWN_PHY_RF_OVERRIDE_VAL_0, 0xfff7, 0); } else { BWN_PHY_SET(mac, BWN_PHY_RF_OVERRIDE_0, 0x20); BWN_PHY_SETMASK(mac, BWN_PHY_RF_OVERRIDE_VAL_0, 0xffdf, 0); } bwn_phy_lp_set_rxgain(mac, 0x2d5d); BWN_PHY_MASK(mac, BWN_PHY_AFE_CTL_OVR, 0xfffe); BWN_PHY_MASK(mac, BWN_PHY_AFE_CTL_OVRVAL, 0xfffe); BWN_PHY_SET(mac, BWN_PHY_RF_OVERRIDE_0, 0x800); BWN_PHY_SET(mac, BWN_PHY_RF_OVERRIDE_VAL_0, 0x800); bwn_phy_lp_set_deaf(mac, 0); /* XXX no checking return value? */ (void)bwn_phy_lp_calc_rx_iq_comp(mac, 0xfff0); bwn_phy_lp_clear_deaf(mac, 0); BWN_PHY_MASK(mac, BWN_PHY_RF_OVERRIDE_0, 0xfffc); BWN_PHY_MASK(mac, BWN_PHY_RF_OVERRIDE_0, 0xfff7); BWN_PHY_MASK(mac, BWN_PHY_RF_OVERRIDE_0, 0xffdf); /* disable RX GAIN override. */ BWN_PHY_MASK(mac, BWN_PHY_RF_OVERRIDE_0, 0xfffe); BWN_PHY_MASK(mac, BWN_PHY_RF_OVERRIDE_0, 0xffef); BWN_PHY_MASK(mac, BWN_PHY_RF_OVERRIDE_0, 0xffbf); if (mac->mac_phy.rev >= 2) { BWN_PHY_MASK(mac, BWN_PHY_RF_OVERRIDE_2, 0xfeff); if (IEEE80211_IS_CHAN_2GHZ(ic->ic_curchan)) { BWN_PHY_MASK(mac, BWN_PHY_RF_OVERRIDE_2, 0xfbff); BWN_PHY_MASK(mac, BWN_PHY_OFDM(0xe5), 0xfff7); } } else { BWN_PHY_MASK(mac, BWN_PHY_RF_OVERRIDE_2, 0xfdff); } BWN_PHY_MASK(mac, BWN_PHY_AFE_CTL_OVR, 0xfffe); BWN_PHY_MASK(mac, BWN_PHY_AFE_CTL_OVRVAL, 0xf7ff); fail: bwn_mac_enable(mac); } void bwn_phy_lp_switch_analog(struct bwn_mac *mac, int on) { if (on) { BWN_PHY_MASK(mac, BWN_PHY_AFE_CTL_OVR, 0xfff8); return; } BWN_PHY_SET(mac, BWN_PHY_AFE_CTL_OVRVAL, 0x0007); BWN_PHY_SET(mac, BWN_PHY_AFE_CTL_OVR, 0x0007); } static int bwn_phy_lp_b2063_switch_channel(struct bwn_mac *mac, uint8_t chan) { static const struct bwn_b206x_chan *bc = NULL; struct bwn_softc *sc = mac->mac_sc; - uint32_t count, freqref, freqvco, freqxtal, val[3], timeout, timeoutref, + uint32_t count, freqref, freqvco, val[3], timeout, timeoutref, tmp[6]; uint16_t old, scale, tmp16; - int i, div; + u_int freqxtal; + int error, i, div; for (i = 0; i < N(bwn_b2063_chantable); i++) { if (bwn_b2063_chantable[i].bc_chan == chan) { bc = &bwn_b2063_chantable[i]; break; } } if (bc == NULL) return (EINVAL); + error = bhnd_get_clock_freq(sc->sc_dev, BHND_CLOCK_ALP, &freqxtal); + if (error) { + device_printf(sc->sc_dev, "failed to fetch clock frequency: %d", + error); + return (error); + } + BWN_RF_WRITE(mac, BWN_B2063_LOGEN_VCOBUF1, bc->bc_data[0]); BWN_RF_WRITE(mac, BWN_B2063_LOGEN_MIXER2, bc->bc_data[1]); BWN_RF_WRITE(mac, BWN_B2063_LOGEN_BUF2, bc->bc_data[2]); BWN_RF_WRITE(mac, BWN_B2063_LOGEN_RCCR1, bc->bc_data[3]); BWN_RF_WRITE(mac, BWN_B2063_A_RX_1ST3, bc->bc_data[4]); BWN_RF_WRITE(mac, BWN_B2063_A_RX_2ND1, bc->bc_data[5]); BWN_RF_WRITE(mac, BWN_B2063_A_RX_2ND4, bc->bc_data[6]); BWN_RF_WRITE(mac, BWN_B2063_A_RX_2ND7, bc->bc_data[7]); BWN_RF_WRITE(mac, BWN_B2063_A_RX_PS6, bc->bc_data[8]); BWN_RF_WRITE(mac, BWN_B2063_TX_RF_CTL2, bc->bc_data[9]); BWN_RF_WRITE(mac, BWN_B2063_TX_RF_CTL5, bc->bc_data[10]); BWN_RF_WRITE(mac, BWN_B2063_PA_CTL11, bc->bc_data[11]); old = BWN_RF_READ(mac, BWN_B2063_COM15); BWN_RF_SET(mac, BWN_B2063_COM15, 0x1e); - freqxtal = siba_get_cc_pmufreq(sc->sc_dev) * 1000; freqvco = bc->bc_freq << ((bc->bc_freq > 4000) ? 1 : 2); freqref = freqxtal * 3; div = (freqxtal <= 26000000 ? 1 : 2); timeout = ((((8 * freqxtal) / (div * 5000000)) + 1) >> 1) - 1; timeoutref = ((((8 * freqxtal) / (div * (timeout + 1))) + 999999) / 1000000) + 1; BWN_RF_WRITE(mac, BWN_B2063_JTAG_VCO_CALIB3, 0x2); BWN_RF_SETMASK(mac, BWN_B2063_JTAG_VCO_CALIB6, 0xfff8, timeout >> 2); BWN_RF_SETMASK(mac, BWN_B2063_JTAG_VCO_CALIB7, 0xff9f,timeout << 5); BWN_RF_WRITE(mac, BWN_B2063_JTAG_VCO_CALIB5, timeoutref); val[0] = bwn_phy_lp_roundup(freqxtal, 1000000, 16); val[1] = bwn_phy_lp_roundup(freqxtal, 1000000 * div, 16); val[2] = bwn_phy_lp_roundup(freqvco, 3, 16); count = (bwn_phy_lp_roundup(val[2], val[1] + 16, 16) * (timeout + 1) * (timeoutref + 1)) - 1; BWN_RF_SETMASK(mac, BWN_B2063_JTAG_VCO_CALIB7, 0xf0, count >> 8); BWN_RF_WRITE(mac, BWN_B2063_JTAG_VCO_CALIB8, count & 0xff); tmp[0] = ((val[2] * 62500) / freqref) << 4; tmp[1] = ((val[2] * 62500) % freqref) << 4; while (tmp[1] >= freqref) { tmp[0]++; tmp[1] -= freqref; } BWN_RF_SETMASK(mac, BWN_B2063_JTAG_SG1, 0xffe0, tmp[0] >> 4); BWN_RF_SETMASK(mac, BWN_B2063_JTAG_SG2, 0xfe0f, tmp[0] << 4); BWN_RF_SETMASK(mac, BWN_B2063_JTAG_SG2, 0xfff0, tmp[0] >> 16); BWN_RF_WRITE(mac, BWN_B2063_JTAG_SG3, (tmp[1] >> 8) & 0xff); BWN_RF_WRITE(mac, BWN_B2063_JTAG_SG4, tmp[1] & 0xff); BWN_RF_WRITE(mac, BWN_B2063_JTAG_LF1, 0xb9); BWN_RF_WRITE(mac, BWN_B2063_JTAG_LF2, 0x88); BWN_RF_WRITE(mac, BWN_B2063_JTAG_LF3, 0x28); BWN_RF_WRITE(mac, BWN_B2063_JTAG_LF4, 0x63); tmp[2] = ((41 * (val[2] - 3000)) /1200) + 27; tmp[3] = bwn_phy_lp_roundup(132000 * tmp[0], 8451, 16); if (howmany(tmp[3], tmp[2]) > 60) { scale = 1; tmp[4] = ((tmp[3] + tmp[2]) / (tmp[2] << 1)) - 8; } else { scale = 0; tmp[4] = ((tmp[3] + (tmp[2] >> 1)) / tmp[2]) - 8; } BWN_RF_SETMASK(mac, BWN_B2063_JTAG_CP2, 0xffc0, tmp[4]); BWN_RF_SETMASK(mac, BWN_B2063_JTAG_CP2, 0xffbf, scale << 6); tmp[5] = bwn_phy_lp_roundup(100 * val[0], val[2], 16) * (tmp[4] * 8) * (scale + 1); if (tmp[5] > 150) tmp[5] = 0; BWN_RF_SETMASK(mac, BWN_B2063_JTAG_CP3, 0xffe0, tmp[5]); BWN_RF_SETMASK(mac, BWN_B2063_JTAG_CP3, 0xffdf, scale << 5); BWN_RF_SETMASK(mac, BWN_B2063_JTAG_XTAL_12, 0xfffb, 0x4); if (freqxtal > 26000000) BWN_RF_SET(mac, BWN_B2063_JTAG_XTAL_12, 0x2); else BWN_RF_MASK(mac, BWN_B2063_JTAG_XTAL_12, 0xfd); if (val[0] == 45) BWN_RF_SET(mac, BWN_B2063_JTAG_VCO1, 0x2); else BWN_RF_MASK(mac, BWN_B2063_JTAG_VCO1, 0xfd); BWN_RF_SET(mac, BWN_B2063_PLL_SP2, 0x3); DELAY(1); BWN_RF_MASK(mac, BWN_B2063_PLL_SP2, 0xfffc); /* VCO Calibration */ BWN_RF_MASK(mac, BWN_B2063_PLL_SP1, ~0x40); tmp16 = BWN_RF_READ(mac, BWN_B2063_JTAG_CALNRST) & 0xf8; BWN_RF_WRITE(mac, BWN_B2063_JTAG_CALNRST, tmp16); DELAY(1); BWN_RF_WRITE(mac, BWN_B2063_JTAG_CALNRST, tmp16 | 0x4); DELAY(1); BWN_RF_WRITE(mac, BWN_B2063_JTAG_CALNRST, tmp16 | 0x6); DELAY(1); BWN_RF_WRITE(mac, BWN_B2063_JTAG_CALNRST, tmp16 | 0x7); DELAY(300); BWN_RF_SET(mac, BWN_B2063_PLL_SP1, 0x40); BWN_RF_WRITE(mac, BWN_B2063_COM15, old); return (0); } static int bwn_phy_lp_b2062_switch_channel(struct bwn_mac *mac, uint8_t chan) { struct bwn_softc *sc = mac->mac_sc; struct bwn_phy_lp *plp = &mac->mac_phy.phy_lp; const struct bwn_b206x_chan *bc = NULL; - uint32_t freqxtal = siba_get_cc_pmufreq(sc->sc_dev) * 1000; uint32_t tmp[9]; - int i; + u_int freqxtal; + int error, i; for (i = 0; i < N(bwn_b2062_chantable); i++) { if (bwn_b2062_chantable[i].bc_chan == chan) { bc = &bwn_b2062_chantable[i]; break; } } if (bc == NULL) return (EINVAL); + error = bhnd_get_clock_freq(sc->sc_dev, BHND_CLOCK_ALP, &freqxtal); + if (error) { + device_printf(sc->sc_dev, "failed to fetch clock frequency: %d", + error); + return (error); + } + BWN_RF_SET(mac, BWN_B2062_S_RFPLLCTL14, 0x04); BWN_RF_WRITE(mac, BWN_B2062_N_LGENATUNE0, bc->bc_data[0]); BWN_RF_WRITE(mac, BWN_B2062_N_LGENATUNE2, bc->bc_data[1]); BWN_RF_WRITE(mac, BWN_B2062_N_LGENATUNE3, bc->bc_data[2]); BWN_RF_WRITE(mac, BWN_B2062_N_TX_TUNE, bc->bc_data[3]); BWN_RF_WRITE(mac, BWN_B2062_S_LGENG_CTL1, bc->bc_data[4]); BWN_RF_WRITE(mac, BWN_B2062_N_LGENACTL5, bc->bc_data[5]); BWN_RF_WRITE(mac, BWN_B2062_N_LGENACTL6, bc->bc_data[6]); BWN_RF_WRITE(mac, BWN_B2062_N_TX_PGA, bc->bc_data[7]); BWN_RF_WRITE(mac, BWN_B2062_N_TX_PAD, bc->bc_data[8]); BWN_RF_WRITE(mac, BWN_B2062_S_RFPLLCTL33, 0xcc); BWN_RF_WRITE(mac, BWN_B2062_S_RFPLLCTL34, 0x07); bwn_phy_lp_b2062_reset_pllbias(mac); tmp[0] = freqxtal / 1000; tmp[1] = plp->plp_div * 1000; tmp[2] = tmp[1] * ieee80211_ieee2mhz(chan, 0); if (ieee80211_ieee2mhz(chan, 0) < 4000) tmp[2] *= 2; tmp[3] = 48 * tmp[0]; tmp[5] = tmp[2] / tmp[3]; tmp[6] = tmp[2] % tmp[3]; BWN_RF_WRITE(mac, BWN_B2062_S_RFPLLCTL26, tmp[5]); tmp[4] = tmp[6] * 0x100; tmp[5] = tmp[4] / tmp[3]; tmp[6] = tmp[4] % tmp[3]; BWN_RF_WRITE(mac, BWN_B2062_S_RFPLLCTL27, tmp[5]); tmp[4] = tmp[6] * 0x100; tmp[5] = tmp[4] / tmp[3]; tmp[6] = tmp[4] % tmp[3]; BWN_RF_WRITE(mac, BWN_B2062_S_RFPLLCTL28, tmp[5]); tmp[4] = tmp[6] * 0x100; tmp[5] = tmp[4] / tmp[3]; tmp[6] = tmp[4] % tmp[3]; BWN_RF_WRITE(mac, BWN_B2062_S_RFPLLCTL29, tmp[5] + ((2 * tmp[6]) / tmp[3])); tmp[7] = BWN_RF_READ(mac, BWN_B2062_S_RFPLLCTL19); tmp[8] = ((2 * tmp[2] * (tmp[7] + 1)) + (3 * tmp[0])) / (6 * tmp[0]); BWN_RF_WRITE(mac, BWN_B2062_S_RFPLLCTL23, (tmp[8] >> 8) + 16); BWN_RF_WRITE(mac, BWN_B2062_S_RFPLLCTL24, tmp[8] & 0xff); bwn_phy_lp_b2062_vco_calib(mac); if (BWN_RF_READ(mac, BWN_B2062_S_RFPLLCTL3) & 0x10) { BWN_RF_WRITE(mac, BWN_B2062_S_RFPLLCTL33, 0xfc); BWN_RF_WRITE(mac, BWN_B2062_S_RFPLLCTL34, 0); bwn_phy_lp_b2062_reset_pllbias(mac); bwn_phy_lp_b2062_vco_calib(mac); if (BWN_RF_READ(mac, BWN_B2062_S_RFPLLCTL3) & 0x10) { BWN_RF_MASK(mac, BWN_B2062_S_RFPLLCTL14, ~0x04); return (EIO); } } BWN_RF_MASK(mac, BWN_B2062_S_RFPLLCTL14, ~0x04); return (0); } static void bwn_phy_lp_set_anafilter(struct bwn_mac *mac, uint8_t channel) { struct bwn_phy_lp *plp = &mac->mac_phy.phy_lp; uint16_t tmp = (channel == 14); if (mac->mac_phy.rev < 2) { BWN_PHY_SETMASK(mac, BWN_PHY_LP_PHY_CTL, 0xfcff, tmp << 9); if ((mac->mac_phy.rev == 1) && (plp->plp_rccap)) bwn_phy_lp_set_rccap(mac); return; } BWN_RF_WRITE(mac, BWN_B2063_TX_BB_SP3, 0x3f); } static void bwn_phy_lp_set_gaintbl(struct bwn_mac *mac, uint32_t freq) { struct bwn_phy_lp *plp = &mac->mac_phy.phy_lp; struct bwn_softc *sc = mac->mac_sc; struct ieee80211com *ic = &sc->sc_ic; uint16_t iso, tmp[3]; KASSERT(mac->mac_phy.rev < 2, ("%s:%d: fail", __func__, __LINE__)); if (IEEE80211_IS_CHAN_2GHZ(ic->ic_curchan)) iso = plp->plp_txisoband_m; else if (freq <= 5320) iso = plp->plp_txisoband_l; else if (freq <= 5700) iso = plp->plp_txisoband_m; else iso = plp->plp_txisoband_h; tmp[0] = ((iso - 26) / 12) << 12; tmp[1] = tmp[0] + 0x1000; tmp[2] = tmp[0] + 0x2000; bwn_tab_write_multi(mac, BWN_TAB_2(13, 0), 3, tmp); bwn_tab_write_multi(mac, BWN_TAB_2(12, 0), 3, tmp); } static void bwn_phy_lp_digflt_save(struct bwn_mac *mac) { struct bwn_phy_lp *plp = &mac->mac_phy.phy_lp; int i; static const uint16_t addr[] = { BWN_PHY_OFDM(0xc1), BWN_PHY_OFDM(0xc2), BWN_PHY_OFDM(0xc3), BWN_PHY_OFDM(0xc4), BWN_PHY_OFDM(0xc5), BWN_PHY_OFDM(0xc6), BWN_PHY_OFDM(0xc7), BWN_PHY_OFDM(0xc8), BWN_PHY_OFDM(0xcf), }; static const uint16_t val[] = { 0xde5e, 0xe832, 0xe331, 0x4d26, 0x0026, 0x1420, 0x0020, 0xfe08, 0x0008, }; for (i = 0; i < N(addr); i++) { plp->plp_digfilt[i] = BWN_PHY_READ(mac, addr[i]); BWN_PHY_WRITE(mac, addr[i], val[i]); } } static void bwn_phy_lp_get_txpctlmode(struct bwn_mac *mac) { struct bwn_phy_lp *plp = &mac->mac_phy.phy_lp; struct bwn_softc *sc = mac->mac_sc; uint16_t ctl; ctl = BWN_PHY_READ(mac, BWN_PHY_TX_PWR_CTL_CMD); switch (ctl & BWN_PHY_TX_PWR_CTL_CMD_MODE) { case BWN_PHY_TX_PWR_CTL_CMD_MODE_OFF: plp->plp_txpctlmode = BWN_PHYLP_TXPCTL_OFF; break; case BWN_PHY_TX_PWR_CTL_CMD_MODE_SW: plp->plp_txpctlmode = BWN_PHYLP_TXPCTL_ON_SW; break; case BWN_PHY_TX_PWR_CTL_CMD_MODE_HW: plp->plp_txpctlmode = BWN_PHYLP_TXPCTL_ON_HW; break; default: plp->plp_txpctlmode = BWN_PHYLP_TXPCTL_UNKNOWN; device_printf(sc->sc_dev, "unknown command mode\n"); break; } } static void bwn_phy_lp_set_txpctlmode(struct bwn_mac *mac, uint8_t mode) { struct bwn_phy_lp *plp = &mac->mac_phy.phy_lp; uint16_t ctl; uint8_t old; bwn_phy_lp_get_txpctlmode(mac); old = plp->plp_txpctlmode; if (old == mode) return; plp->plp_txpctlmode = mode; if (old != BWN_PHYLP_TXPCTL_ON_HW && mode == BWN_PHYLP_TXPCTL_ON_HW) { BWN_PHY_SETMASK(mac, BWN_PHY_TX_PWR_CTL_CMD, 0xff80, plp->plp_tssiidx); BWN_PHY_SETMASK(mac, BWN_PHY_TX_PWR_CTL_NNUM, 0x8fff, ((uint16_t)plp->plp_tssinpt << 16)); /* disable TX GAIN override */ if (mac->mac_phy.rev < 2) BWN_PHY_MASK(mac, BWN_PHY_RF_OVERRIDE_2, 0xfeff); else { BWN_PHY_MASK(mac, BWN_PHY_RF_OVERRIDE_2, 0xff7f); BWN_PHY_MASK(mac, BWN_PHY_RF_OVERRIDE_2, 0xbfff); } BWN_PHY_MASK(mac, BWN_PHY_AFE_CTL_OVR, 0xffbf); plp->plp_txpwridx = -1; } if (mac->mac_phy.rev >= 2) { if (mode == BWN_PHYLP_TXPCTL_ON_HW) BWN_PHY_SET(mac, BWN_PHY_OFDM(0xd0), 0x2); else BWN_PHY_MASK(mac, BWN_PHY_OFDM(0xd0), 0xfffd); } /* writes TX Power Control mode */ switch (plp->plp_txpctlmode) { case BWN_PHYLP_TXPCTL_OFF: ctl = BWN_PHY_TX_PWR_CTL_CMD_MODE_OFF; break; case BWN_PHYLP_TXPCTL_ON_HW: ctl = BWN_PHY_TX_PWR_CTL_CMD_MODE_HW; break; case BWN_PHYLP_TXPCTL_ON_SW: ctl = BWN_PHY_TX_PWR_CTL_CMD_MODE_SW; break; default: ctl = 0; KASSERT(0 == 1, ("%s:%d: fail", __func__, __LINE__)); } BWN_PHY_SETMASK(mac, BWN_PHY_TX_PWR_CTL_CMD, (uint16_t)~BWN_PHY_TX_PWR_CTL_CMD_MODE, ctl); } static void bwn_phy_lp_bugfix(struct bwn_mac *mac) { struct bwn_phy_lp *plp = &mac->mac_phy.phy_lp; struct bwn_softc *sc = mac->mac_sc; const unsigned int size = 256; struct bwn_txgain tg; uint32_t rxcomp, txgain, coeff, rfpwr, *tabs; uint16_t tssinpt, tssiidx, value[2]; uint8_t mode; int8_t txpwridx; tabs = (uint32_t *)malloc(sizeof(uint32_t) * size, M_DEVBUF, M_NOWAIT | M_ZERO); if (tabs == NULL) { device_printf(sc->sc_dev, "failed to allocate buffer.\n"); return; } bwn_phy_lp_get_txpctlmode(mac); mode = plp->plp_txpctlmode; txpwridx = plp->plp_txpwridx; tssinpt = plp->plp_tssinpt; tssiidx = plp->plp_tssiidx; bwn_tab_read_multi(mac, (mac->mac_phy.rev < 2) ? BWN_TAB_4(10, 0x140) : BWN_TAB_4(7, 0x140), size, tabs); bwn_phy_lp_tblinit(mac); bwn_phy_lp_bbinit(mac); bwn_phy_lp_txpctl_init(mac); bwn_phy_lp_rf_onoff(mac, 1); bwn_phy_lp_set_txpctlmode(mac, BWN_PHYLP_TXPCTL_OFF); bwn_tab_write_multi(mac, (mac->mac_phy.rev < 2) ? BWN_TAB_4(10, 0x140) : BWN_TAB_4(7, 0x140), size, tabs); BWN_WRITE_2(mac, BWN_CHANNEL, plp->plp_chan); plp->plp_tssinpt = tssinpt; plp->plp_tssiidx = tssiidx; bwn_phy_lp_set_anafilter(mac, plp->plp_chan); if (txpwridx != -1) { /* set TX power by index */ plp->plp_txpwridx = txpwridx; bwn_phy_lp_get_txpctlmode(mac); if (plp->plp_txpctlmode != BWN_PHYLP_TXPCTL_OFF) bwn_phy_lp_set_txpctlmode(mac, BWN_PHYLP_TXPCTL_ON_SW); if (mac->mac_phy.rev >= 2) { rxcomp = bwn_tab_read(mac, BWN_TAB_4(7, txpwridx + 320)); txgain = bwn_tab_read(mac, BWN_TAB_4(7, txpwridx + 192)); tg.tg_pad = (txgain >> 16) & 0xff; tg.tg_gm = txgain & 0xff; tg.tg_pga = (txgain >> 8) & 0xff; tg.tg_dac = (rxcomp >> 28) & 0xff; bwn_phy_lp_set_txgain(mac, &tg); } else { rxcomp = bwn_tab_read(mac, BWN_TAB_4(10, txpwridx + 320)); txgain = bwn_tab_read(mac, BWN_TAB_4(10, txpwridx + 192)); BWN_PHY_SETMASK(mac, BWN_PHY_TX_GAIN_CTL_OVERRIDE_VAL, 0xf800, (txgain >> 4) & 0x7fff); bwn_phy_lp_set_txgain_dac(mac, txgain & 0x7); bwn_phy_lp_set_txgain_pa(mac, (txgain >> 24) & 0x7f); } bwn_phy_lp_set_bbmult(mac, (rxcomp >> 20) & 0xff); /* set TX IQCC */ value[0] = (rxcomp >> 10) & 0x3ff; value[1] = rxcomp & 0x3ff; bwn_tab_write_multi(mac, BWN_TAB_2(0, 80), 2, value); coeff = bwn_tab_read(mac, (mac->mac_phy.rev >= 2) ? BWN_TAB_4(7, txpwridx + 448) : BWN_TAB_4(10, txpwridx + 448)); bwn_tab_write(mac, BWN_TAB_2(0, 85), coeff & 0xffff); if (mac->mac_phy.rev >= 2) { rfpwr = bwn_tab_read(mac, BWN_TAB_4(7, txpwridx + 576)); BWN_PHY_SETMASK(mac, BWN_PHY_RF_PWR_OVERRIDE, 0xff00, rfpwr & 0xffff); } bwn_phy_lp_set_txgain_override(mac); } if (plp->plp_rccap) bwn_phy_lp_set_rccap(mac); bwn_phy_lp_set_antenna(mac, plp->plp_antenna); bwn_phy_lp_set_txpctlmode(mac, mode); free(tabs, M_DEVBUF); } static void bwn_phy_lp_digflt_restore(struct bwn_mac *mac) { struct bwn_phy_lp *plp = &mac->mac_phy.phy_lp; int i; static const uint16_t addr[] = { BWN_PHY_OFDM(0xc1), BWN_PHY_OFDM(0xc2), BWN_PHY_OFDM(0xc3), BWN_PHY_OFDM(0xc4), BWN_PHY_OFDM(0xc5), BWN_PHY_OFDM(0xc6), BWN_PHY_OFDM(0xc7), BWN_PHY_OFDM(0xc8), BWN_PHY_OFDM(0xcf), }; for (i = 0; i < N(addr); i++) BWN_PHY_WRITE(mac, addr[i], plp->plp_digfilt[i]); } static void bwn_phy_lp_tblinit(struct bwn_mac *mac) { uint32_t freq = ieee80211_ieee2mhz(bwn_phy_lp_get_default_chan(mac), 0); if (mac->mac_phy.rev < 2) { bwn_phy_lp_tblinit_r01(mac); bwn_phy_lp_tblinit_txgain(mac); bwn_phy_lp_set_gaintbl(mac, freq); return; } bwn_phy_lp_tblinit_r2(mac); bwn_phy_lp_tblinit_txgain(mac); } struct bwn_wpair { uint16_t reg; uint16_t value; }; struct bwn_smpair { uint16_t offset; uint16_t mask; uint16_t set; }; static void bwn_phy_lp_bbinit_r2(struct bwn_mac *mac) { struct bwn_phy_lp *plp = &mac->mac_phy.phy_lp; struct bwn_softc *sc = mac->mac_sc; struct ieee80211com *ic = &sc->sc_ic; static const struct bwn_wpair v1[] = { { BWN_PHY_AFE_DAC_CTL, 0x50 }, { BWN_PHY_AFE_CTL, 0x8800 }, { BWN_PHY_AFE_CTL_OVR, 0 }, { BWN_PHY_AFE_CTL_OVRVAL, 0 }, { BWN_PHY_RF_OVERRIDE_0, 0 }, { BWN_PHY_RF_OVERRIDE_2, 0 }, { BWN_PHY_OFDM(0xf9), 0 }, { BWN_PHY_TR_LOOKUP_1, 0 } }; static const struct bwn_smpair v2[] = { { BWN_PHY_OFDMSYNCTHRESH0, 0xff00, 0xb4 }, { BWN_PHY_DCOFFSETTRANSIENT, 0xf8ff, 0x200 }, { BWN_PHY_DCOFFSETTRANSIENT, 0xff00, 0x7f }, { BWN_PHY_GAINDIRECTMISMATCH, 0xff0f, 0x40 }, { BWN_PHY_PREAMBLECONFIRMTO, 0xff00, 0x2 } }; static const struct bwn_smpair v3[] = { { BWN_PHY_OFDM(0xfe), 0xffe0, 0x1f }, { BWN_PHY_OFDM(0xff), 0xffe0, 0xc }, { BWN_PHY_OFDM(0x100), 0xff00, 0x19 }, { BWN_PHY_OFDM(0xff), 0x03ff, 0x3c00 }, { BWN_PHY_OFDM(0xfe), 0xfc1f, 0x3e0 }, { BWN_PHY_OFDM(0xff), 0xffe0, 0xc }, { BWN_PHY_OFDM(0x100), 0x00ff, 0x1900 }, { BWN_PHY_CLIPCTRTHRESH, 0x83ff, 0x5800 }, { BWN_PHY_CLIPCTRTHRESH, 0xffe0, 0x12 }, { BWN_PHY_GAINMISMATCH, 0x0fff, 0x9000 }, }; int i; for (i = 0; i < N(v1); i++) BWN_PHY_WRITE(mac, v1[i].reg, v1[i].value); BWN_PHY_SET(mac, BWN_PHY_ADC_COMPENSATION_CTL, 0x10); for (i = 0; i < N(v2); i++) BWN_PHY_SETMASK(mac, v2[i].offset, v2[i].mask, v2[i].set); BWN_PHY_MASK(mac, BWN_PHY_CRSGAIN_CTL, ~0x4000); BWN_PHY_MASK(mac, BWN_PHY_CRSGAIN_CTL, ~0x2000); BWN_PHY_SET(mac, BWN_PHY_OFDM(0x10a), 0x1); - if (siba_get_pci_revid(sc->sc_dev) >= 0x18) { + if (sc->sc_board_info.board_rev >= 0x18) { bwn_tab_write(mac, BWN_TAB_4(17, 65), 0xec); BWN_PHY_SETMASK(mac, BWN_PHY_OFDM(0x10a), 0xff01, 0x14); } else { BWN_PHY_SETMASK(mac, BWN_PHY_OFDM(0x10a), 0xff01, 0x10); } BWN_PHY_SETMASK(mac, BWN_PHY_OFDM(0xdf), 0xff00, 0xf4); BWN_PHY_SETMASK(mac, BWN_PHY_OFDM(0xdf), 0x00ff, 0xf100); BWN_PHY_WRITE(mac, BWN_PHY_CLIPTHRESH, 0x48); BWN_PHY_SETMASK(mac, BWN_PHY_HIGAINDB, 0xff00, 0x46); BWN_PHY_SETMASK(mac, BWN_PHY_OFDM(0xe4), 0xff00, 0x10); BWN_PHY_SETMASK(mac, BWN_PHY_PWR_THRESH1, 0xfff0, 0x9); BWN_PHY_MASK(mac, BWN_PHY_GAINDIRECTMISMATCH, ~0xf); BWN_PHY_SETMASK(mac, BWN_PHY_VERYLOWGAINDB, 0x00ff, 0x5500); BWN_PHY_SETMASK(mac, BWN_PHY_CLIPCTRTHRESH, 0xfc1f, 0xa0); BWN_PHY_SETMASK(mac, BWN_PHY_GAINDIRECTMISMATCH, 0xe0ff, 0x300); BWN_PHY_SETMASK(mac, BWN_PHY_HIGAINDB, 0x00ff, 0x2a00); - if ((siba_get_chipid(sc->sc_dev) == 0x4325) && - (siba_get_chiprev(sc->sc_dev) == 0)) { + if (sc->sc_cid.chip_id == BHND_CHIPID_BCM4325 && + sc->sc_cid.chip_pkg == 0) { BWN_PHY_SETMASK(mac, BWN_PHY_LOWGAINDB, 0x00ff, 0x2100); BWN_PHY_SETMASK(mac, BWN_PHY_VERYLOWGAINDB, 0xff00, 0xa); } else { BWN_PHY_SETMASK(mac, BWN_PHY_LOWGAINDB, 0x00ff, 0x1e00); BWN_PHY_SETMASK(mac, BWN_PHY_VERYLOWGAINDB, 0xff00, 0xd); } for (i = 0; i < N(v3); i++) BWN_PHY_SETMASK(mac, v3[i].offset, v3[i].mask, v3[i].set); - if ((siba_get_chipid(sc->sc_dev) == 0x4325) && - (siba_get_chiprev(sc->sc_dev) == 0)) { + if (sc->sc_cid.chip_id == BHND_CHIPID_BCM4325 && + sc->sc_cid.chip_pkg == 0) { bwn_tab_write(mac, BWN_TAB_2(0x08, 0x14), 0); bwn_tab_write(mac, BWN_TAB_2(0x08, 0x12), 0x40); } if (IEEE80211_IS_CHAN_2GHZ(ic->ic_curchan)) { BWN_PHY_SET(mac, BWN_PHY_CRSGAIN_CTL, 0x40); BWN_PHY_SETMASK(mac, BWN_PHY_CRSGAIN_CTL, 0xf0ff, 0xb00); BWN_PHY_SETMASK(mac, BWN_PHY_SYNCPEAKCNT, 0xfff8, 0x6); BWN_PHY_SETMASK(mac, BWN_PHY_MINPWR_LEVEL, 0x00ff, 0x9d00); BWN_PHY_SETMASK(mac, BWN_PHY_MINPWR_LEVEL, 0xff00, 0xa1); BWN_PHY_MASK(mac, BWN_PHY_IDLEAFTERPKTRXTO, 0x00ff); } else BWN_PHY_MASK(mac, BWN_PHY_CRSGAIN_CTL, ~0x40); BWN_PHY_SETMASK(mac, BWN_PHY_CRS_ED_THRESH, 0xff00, 0xb3); BWN_PHY_SETMASK(mac, BWN_PHY_CRS_ED_THRESH, 0x00ff, 0xad00); BWN_PHY_SETMASK(mac, BWN_PHY_INPUT_PWRDB, 0xff00, plp->plp_rxpwroffset); BWN_PHY_SET(mac, BWN_PHY_RESET_CTL, 0x44); BWN_PHY_WRITE(mac, BWN_PHY_RESET_CTL, 0x80); BWN_PHY_WRITE(mac, BWN_PHY_AFE_RSSI_CTL_0, 0xa954); BWN_PHY_WRITE(mac, BWN_PHY_AFE_RSSI_CTL_1, 0x2000 | ((uint16_t)plp->plp_rssigs << 10) | ((uint16_t)plp->plp_rssivc << 4) | plp->plp_rssivf); - if ((siba_get_chipid(sc->sc_dev) == 0x4325) && - (siba_get_chiprev(sc->sc_dev) == 0)) { + if (sc->sc_cid.chip_id == BHND_CHIPID_BCM4325 && + sc->sc_cid.chip_pkg == 0) { BWN_PHY_SET(mac, BWN_PHY_AFE_ADC_CTL_0, 0x1c); BWN_PHY_SETMASK(mac, BWN_PHY_AFE_CTL, 0x00ff, 0x8800); BWN_PHY_SETMASK(mac, BWN_PHY_AFE_ADC_CTL_1, 0xfc3c, 0x0400); } bwn_phy_lp_digflt_save(mac); } static void bwn_phy_lp_bbinit_r01(struct bwn_mac *mac) { struct bwn_phy_lp *plp = &mac->mac_phy.phy_lp; struct bwn_softc *sc = mac->mac_sc; struct ieee80211com *ic = &sc->sc_ic; static const struct bwn_smpair v1[] = { { BWN_PHY_CLIPCTRTHRESH, 0xffe0, 0x0005 }, { BWN_PHY_CLIPCTRTHRESH, 0xfc1f, 0x0180 }, { BWN_PHY_CLIPCTRTHRESH, 0x83ff, 0x3c00 }, { BWN_PHY_GAINDIRECTMISMATCH, 0xfff0, 0x0005 }, { BWN_PHY_GAIN_MISMATCH_LIMIT, 0xffc0, 0x001a }, { BWN_PHY_CRS_ED_THRESH, 0xff00, 0x00b3 }, { BWN_PHY_CRS_ED_THRESH, 0x00ff, 0xad00 } }; static const struct bwn_smpair v2[] = { { BWN_PHY_TR_LOOKUP_1, 0xffc0, 0x000a }, { BWN_PHY_TR_LOOKUP_1, 0x3f00, 0x0900 }, { BWN_PHY_TR_LOOKUP_2, 0xffc0, 0x000a }, { BWN_PHY_TR_LOOKUP_2, 0xc0ff, 0x0b00 }, { BWN_PHY_TR_LOOKUP_3, 0xffc0, 0x000a }, { BWN_PHY_TR_LOOKUP_3, 0xc0ff, 0x0400 }, { BWN_PHY_TR_LOOKUP_4, 0xffc0, 0x000a }, { BWN_PHY_TR_LOOKUP_4, 0xc0ff, 0x0b00 }, { BWN_PHY_TR_LOOKUP_5, 0xffc0, 0x000a }, { BWN_PHY_TR_LOOKUP_5, 0xc0ff, 0x0900 }, { BWN_PHY_TR_LOOKUP_6, 0xffc0, 0x000a }, { BWN_PHY_TR_LOOKUP_6, 0xc0ff, 0x0b00 }, { BWN_PHY_TR_LOOKUP_7, 0xffc0, 0x000a }, { BWN_PHY_TR_LOOKUP_7, 0xc0ff, 0x0900 }, { BWN_PHY_TR_LOOKUP_8, 0xffc0, 0x000a }, { BWN_PHY_TR_LOOKUP_8, 0xc0ff, 0x0b00 } }; static const struct bwn_smpair v3[] = { { BWN_PHY_TR_LOOKUP_1, 0xffc0, 0x0001 }, { BWN_PHY_TR_LOOKUP_1, 0xc0ff, 0x0400 }, { BWN_PHY_TR_LOOKUP_2, 0xffc0, 0x0001 }, { BWN_PHY_TR_LOOKUP_2, 0xc0ff, 0x0500 }, { BWN_PHY_TR_LOOKUP_3, 0xffc0, 0x0002 }, { BWN_PHY_TR_LOOKUP_3, 0xc0ff, 0x0800 }, { BWN_PHY_TR_LOOKUP_4, 0xffc0, 0x0002 }, { BWN_PHY_TR_LOOKUP_4, 0xc0ff, 0x0a00 } }; static const struct bwn_smpair v4[] = { { BWN_PHY_TR_LOOKUP_1, 0xffc0, 0x0004 }, { BWN_PHY_TR_LOOKUP_1, 0xc0ff, 0x0800 }, { BWN_PHY_TR_LOOKUP_2, 0xffc0, 0x0004 }, { BWN_PHY_TR_LOOKUP_2, 0xc0ff, 0x0c00 }, { BWN_PHY_TR_LOOKUP_3, 0xffc0, 0x0002 }, { BWN_PHY_TR_LOOKUP_3, 0xc0ff, 0x0100 }, { BWN_PHY_TR_LOOKUP_4, 0xffc0, 0x0002 }, { BWN_PHY_TR_LOOKUP_4, 0xc0ff, 0x0300 } }; static const struct bwn_smpair v5[] = { { BWN_PHY_TR_LOOKUP_1, 0xffc0, 0x000a }, { BWN_PHY_TR_LOOKUP_1, 0xc0ff, 0x0900 }, { BWN_PHY_TR_LOOKUP_2, 0xffc0, 0x000a }, { BWN_PHY_TR_LOOKUP_2, 0xc0ff, 0x0b00 }, { BWN_PHY_TR_LOOKUP_3, 0xffc0, 0x0006 }, { BWN_PHY_TR_LOOKUP_3, 0xc0ff, 0x0500 }, { BWN_PHY_TR_LOOKUP_4, 0xffc0, 0x0006 }, { BWN_PHY_TR_LOOKUP_4, 0xc0ff, 0x0700 } }; - int i; + int error, i; uint16_t tmp, tmp2; BWN_PHY_MASK(mac, BWN_PHY_AFE_DAC_CTL, 0xf7ff); BWN_PHY_WRITE(mac, BWN_PHY_AFE_CTL, 0); BWN_PHY_WRITE(mac, BWN_PHY_AFE_CTL_OVR, 0); BWN_PHY_WRITE(mac, BWN_PHY_RF_OVERRIDE_0, 0); BWN_PHY_WRITE(mac, BWN_PHY_RF_OVERRIDE_2, 0); BWN_PHY_SET(mac, BWN_PHY_AFE_DAC_CTL, 0x0004); BWN_PHY_SETMASK(mac, BWN_PHY_OFDMSYNCTHRESH0, 0xff00, 0x0078); BWN_PHY_SETMASK(mac, BWN_PHY_CLIPCTRTHRESH, 0x83ff, 0x5800); BWN_PHY_WRITE(mac, BWN_PHY_ADC_COMPENSATION_CTL, 0x0016); BWN_PHY_SETMASK(mac, BWN_PHY_AFE_ADC_CTL_0, 0xfff8, 0x0004); BWN_PHY_SETMASK(mac, BWN_PHY_VERYLOWGAINDB, 0x00ff, 0x5400); BWN_PHY_SETMASK(mac, BWN_PHY_HIGAINDB, 0x00ff, 0x2400); BWN_PHY_SETMASK(mac, BWN_PHY_LOWGAINDB, 0x00ff, 0x2100); BWN_PHY_SETMASK(mac, BWN_PHY_VERYLOWGAINDB, 0xff00, 0x0006); BWN_PHY_MASK(mac, BWN_PHY_RX_RADIO_CTL, 0xfffe); for (i = 0; i < N(v1); i++) BWN_PHY_SETMASK(mac, v1[i].offset, v1[i].mask, v1[i].set); BWN_PHY_SETMASK(mac, BWN_PHY_INPUT_PWRDB, 0xff00, plp->plp_rxpwroffset); - if ((siba_sprom_get_bf_lo(sc->sc_dev) & BWN_BFL_FEM) && + if ((sc->sc_board_info.board_flags & BHND_BFL_FEM) && ((IEEE80211_IS_CHAN_5GHZ(ic->ic_curchan)) || - (siba_sprom_get_bf_hi(sc->sc_dev) & BWN_BFH_LDO_PAREF))) { - siba_cc_pmu_set_ldovolt(sc->sc_dev, SIBA_LDO_PAREF, 0x28); - siba_cc_pmu_set_ldoparef(sc->sc_dev, 1); + (sc->sc_board_info.board_flags & BHND_BFL_PAREF))) { + error = bhnd_pmu_set_voltage_raw(sc->sc_pmu, + BHND_REGULATOR_PAREF_LDO, 0x28); + if (error) + device_printf(sc->sc_dev, "failed to set PAREF LDO " + "voltage: %d\n", error); + + error = bhnd_pmu_enable_regulator(sc->sc_pmu, + BHND_REGULATOR_PAREF_LDO); + if (error) + device_printf(sc->sc_dev, "failed to enable PAREF LDO " + "regulator: %d\n", error); + if (mac->mac_phy.rev == 0) BWN_PHY_SETMASK(mac, BWN_PHY_LP_RF_SIGNAL_LUT, 0xffcf, 0x0010); bwn_tab_write(mac, BWN_TAB_2(11, 7), 60); } else { - siba_cc_pmu_set_ldoparef(sc->sc_dev, 0); + error = bhnd_pmu_disable_regulator(sc->sc_pmu, + BHND_REGULATOR_PAREF_LDO); + if (error) + device_printf(sc->sc_dev, "failed to disable PAREF LDO " + "regulator: %d\n", error); + BWN_PHY_SETMASK(mac, BWN_PHY_LP_RF_SIGNAL_LUT, 0xffcf, 0x0020); bwn_tab_write(mac, BWN_TAB_2(11, 7), 100); } tmp = plp->plp_rssivf | plp->plp_rssivc << 4 | 0xa000; BWN_PHY_WRITE(mac, BWN_PHY_AFE_RSSI_CTL_0, tmp); - if (siba_sprom_get_bf_hi(sc->sc_dev) & BWN_BFH_RSSIINV) + if (sc->sc_board_info.board_flags & BHND_BFL_RSSIINV) BWN_PHY_SETMASK(mac, BWN_PHY_AFE_RSSI_CTL_1, 0xf000, 0x0aaa); else BWN_PHY_SETMASK(mac, BWN_PHY_AFE_RSSI_CTL_1, 0xf000, 0x02aa); bwn_tab_write(mac, BWN_TAB_2(11, 1), 24); BWN_PHY_SETMASK(mac, BWN_PHY_RX_RADIO_CTL, 0xfff9, (plp->plp_bxarch << 1)); if (mac->mac_phy.rev == 1 && - (siba_sprom_get_bf_hi(sc->sc_dev) & BWN_BFH_FEM_BT)) { + (sc->sc_board_info.board_flags & BHND_BFL_FEM_BT)) { for (i = 0; i < N(v2); i++) BWN_PHY_SETMASK(mac, v2[i].offset, v2[i].mask, v2[i].set); } else if (IEEE80211_IS_CHAN_5GHZ(ic->ic_curchan) || - (siba_get_pci_subdevice(sc->sc_dev) == 0x048a) || + (sc->sc_board_info.board_type == 0x048a) || ((mac->mac_phy.rev == 0) && - (siba_sprom_get_bf_lo(sc->sc_dev) & BWN_BFL_FEM))) { + (sc->sc_board_info.board_flags & BHND_BFL_FEM))) { for (i = 0; i < N(v3); i++) BWN_PHY_SETMASK(mac, v3[i].offset, v3[i].mask, v3[i].set); } else if (mac->mac_phy.rev == 1 || - (siba_sprom_get_bf_lo(sc->sc_dev) & BWN_BFL_FEM)) { + (sc->sc_board_info.board_flags & BHND_BFL_FEM)) { for (i = 0; i < N(v4); i++) BWN_PHY_SETMASK(mac, v4[i].offset, v4[i].mask, v4[i].set); } else { for (i = 0; i < N(v5); i++) BWN_PHY_SETMASK(mac, v5[i].offset, v5[i].mask, v5[i].set); } if (mac->mac_phy.rev == 1 && - (siba_sprom_get_bf_hi(sc->sc_dev) & BWN_BFH_LDO_PAREF)) { + (sc->sc_board_info.board_flags & BHND_BFL_PAREF)) { BWN_PHY_COPY(mac, BWN_PHY_TR_LOOKUP_5, BWN_PHY_TR_LOOKUP_1); BWN_PHY_COPY(mac, BWN_PHY_TR_LOOKUP_6, BWN_PHY_TR_LOOKUP_2); BWN_PHY_COPY(mac, BWN_PHY_TR_LOOKUP_7, BWN_PHY_TR_LOOKUP_3); BWN_PHY_COPY(mac, BWN_PHY_TR_LOOKUP_8, BWN_PHY_TR_LOOKUP_4); } - if ((siba_sprom_get_bf_hi(sc->sc_dev) & BWN_BFH_FEM_BT) && - (siba_get_chipid(sc->sc_dev) == 0x5354) && - (siba_get_chippkg(sc->sc_dev) == SIBA_CHIPPACK_BCM4712S)) { + if ((sc->sc_board_info.board_flags & BHND_BFL_FEM_BT) && + (sc->sc_cid.chip_id == BHND_CHIPID_BCM5354) && + (sc->sc_cid.chip_pkg == BHND_PKGID_BCM4712SMALL)) { BWN_PHY_SET(mac, BWN_PHY_CRSGAIN_CTL, 0x0006); BWN_PHY_WRITE(mac, BWN_PHY_GPIO_SELECT, 0x0005); BWN_PHY_WRITE(mac, BWN_PHY_GPIO_OUTEN, 0xffff); bwn_hf_write(mac, bwn_hf_read(mac) | BWN_HF_PR45960W); } if (IEEE80211_IS_CHAN_2GHZ(ic->ic_curchan)) { BWN_PHY_SET(mac, BWN_PHY_LP_PHY_CTL, 0x8000); BWN_PHY_SET(mac, BWN_PHY_CRSGAIN_CTL, 0x0040); BWN_PHY_SETMASK(mac, BWN_PHY_MINPWR_LEVEL, 0x00ff, 0xa400); BWN_PHY_SETMASK(mac, BWN_PHY_CRSGAIN_CTL, 0xf0ff, 0x0b00); BWN_PHY_SETMASK(mac, BWN_PHY_SYNCPEAKCNT, 0xfff8, 0x0007); BWN_PHY_SETMASK(mac, BWN_PHY_DSSS_CONFIRM_CNT, 0xfff8, 0x0003); BWN_PHY_SETMASK(mac, BWN_PHY_DSSS_CONFIRM_CNT, 0xffc7, 0x0020); BWN_PHY_MASK(mac, BWN_PHY_IDLEAFTERPKTRXTO, 0x00ff); } else { BWN_PHY_MASK(mac, BWN_PHY_LP_PHY_CTL, 0x7fff); BWN_PHY_MASK(mac, BWN_PHY_CRSGAIN_CTL, 0xffbf); } if (mac->mac_phy.rev == 1) { tmp = BWN_PHY_READ(mac, BWN_PHY_CLIPCTRTHRESH); tmp2 = (tmp & 0x03e0) >> 5; tmp2 |= tmp2 << 5; BWN_PHY_WRITE(mac, BWN_PHY_4C3, tmp2); tmp = BWN_PHY_READ(mac, BWN_PHY_GAINDIRECTMISMATCH); tmp2 = (tmp & 0x1f00) >> 8; tmp2 |= tmp2 << 5; BWN_PHY_WRITE(mac, BWN_PHY_4C4, tmp2); tmp = BWN_PHY_READ(mac, BWN_PHY_VERYLOWGAINDB); tmp2 = tmp & 0x00ff; tmp2 |= tmp << 8; BWN_PHY_WRITE(mac, BWN_PHY_4C5, tmp2); } } struct bwn_b2062_freq { uint16_t freq; uint8_t value[6]; }; -static void +static int bwn_phy_lp_b2062_init(struct bwn_mac *mac) { #define CALC_CTL7(freq, div) \ (((800000000 * (div) + (freq)) / (2 * (freq)) - 8) & 0xff) #define CALC_CTL18(freq, div) \ ((((100 * (freq) + 16000000 * (div)) / (32000000 * (div))) - 1) & 0xff) #define CALC_CTL19(freq, div) \ ((((2 * (freq) + 1000000 * (div)) / (2000000 * (div))) - 1) & 0xff) struct bwn_phy_lp *plp = &mac->mac_phy.phy_lp; struct bwn_softc *sc = mac->mac_sc; struct ieee80211com *ic = &sc->sc_ic; static const struct bwn_b2062_freq freqdata_tab[] = { { 12000, { 6, 6, 6, 6, 10, 6 } }, { 13000, { 4, 4, 4, 4, 11, 7 } }, { 14400, { 3, 3, 3, 3, 12, 7 } }, { 16200, { 3, 3, 3, 3, 13, 8 } }, { 18000, { 2, 2, 2, 2, 14, 8 } }, { 19200, { 1, 1, 1, 1, 14, 9 } } }; static const struct bwn_wpair v1[] = { { BWN_B2062_N_TXCTL3, 0 }, { BWN_B2062_N_TXCTL4, 0 }, { BWN_B2062_N_TXCTL5, 0 }, { BWN_B2062_N_TXCTL6, 0 }, { BWN_B2062_N_PDNCTL0, 0x40 }, { BWN_B2062_N_PDNCTL0, 0 }, { BWN_B2062_N_CALIB_TS, 0x10 }, { BWN_B2062_N_CALIB_TS, 0 } }; const struct bwn_b2062_freq *f = NULL; - uint32_t xtalfreq, ref; + uint32_t ref; + u_int xtalfreq; unsigned int i; + int error; + error = bhnd_get_clock_freq(sc->sc_dev, BHND_CLOCK_ALP, &xtalfreq); + if (error) { + device_printf(sc->sc_dev, "failed to fetch clock frequency: %d", + error); + return (error); + } + bwn_phy_lp_b2062_tblinit(mac); for (i = 0; i < N(v1); i++) BWN_RF_WRITE(mac, v1[i].reg, v1[i].value); if (mac->mac_phy.rev > 0) BWN_RF_WRITE(mac, BWN_B2062_S_BG_CTL1, (BWN_RF_READ(mac, BWN_B2062_N_COM2) >> 1) | 0x80); if (IEEE80211_IS_CHAN_2GHZ(ic->ic_curchan)) BWN_RF_SET(mac, BWN_B2062_N_TSSI_CTL0, 0x1); else BWN_RF_MASK(mac, BWN_B2062_N_TSSI_CTL0, ~0x1); - KASSERT(siba_get_cc_caps(sc->sc_dev) & SIBA_CC_CAPS_PMU, - ("%s:%d: fail", __func__, __LINE__)); - xtalfreq = siba_get_cc_pmufreq(sc->sc_dev) * 1000; - KASSERT(xtalfreq != 0, ("%s:%d: fail", __func__, __LINE__)); - if (xtalfreq <= 30000000) { plp->plp_div = 1; BWN_RF_MASK(mac, BWN_B2062_S_RFPLLCTL1, 0xfffb); } else { plp->plp_div = 2; BWN_RF_SET(mac, BWN_B2062_S_RFPLLCTL1, 0x4); } BWN_RF_WRITE(mac, BWN_B2062_S_RFPLLCTL7, CALC_CTL7(xtalfreq, plp->plp_div)); BWN_RF_WRITE(mac, BWN_B2062_S_RFPLLCTL18, CALC_CTL18(xtalfreq, plp->plp_div)); BWN_RF_WRITE(mac, BWN_B2062_S_RFPLLCTL19, CALC_CTL19(xtalfreq, plp->plp_div)); ref = (1000 * plp->plp_div + 2 * xtalfreq) / (2000 * plp->plp_div); ref &= 0xffff; for (i = 0; i < N(freqdata_tab); i++) { if (ref < freqdata_tab[i].freq) { f = &freqdata_tab[i]; break; } } if (f == NULL) f = &freqdata_tab[N(freqdata_tab) - 1]; BWN_RF_WRITE(mac, BWN_B2062_S_RFPLLCTL8, ((uint16_t)(f->value[1]) << 4) | f->value[0]); BWN_RF_WRITE(mac, BWN_B2062_S_RFPLLCTL9, ((uint16_t)(f->value[3]) << 4) | f->value[2]); BWN_RF_WRITE(mac, BWN_B2062_S_RFPLLCTL10, f->value[4]); BWN_RF_WRITE(mac, BWN_B2062_S_RFPLLCTL11, f->value[5]); + + return (0); #undef CALC_CTL7 #undef CALC_CTL18 #undef CALC_CTL19 } -static void +static int bwn_phy_lp_b2063_init(struct bwn_mac *mac) { bwn_phy_lp_b2063_tblinit(mac); BWN_RF_WRITE(mac, BWN_B2063_LOGEN_SP5, 0); BWN_RF_SET(mac, BWN_B2063_COM8, 0x38); BWN_RF_WRITE(mac, BWN_B2063_REG_SP1, 0x56); BWN_RF_MASK(mac, BWN_B2063_RX_BB_CTL2, ~0x2); BWN_RF_WRITE(mac, BWN_B2063_PA_SP7, 0); BWN_RF_WRITE(mac, BWN_B2063_TX_RF_SP6, 0x20); BWN_RF_WRITE(mac, BWN_B2063_TX_RF_SP9, 0x40); if (mac->mac_phy.rev == 2) { BWN_RF_WRITE(mac, BWN_B2063_PA_SP3, 0xa0); BWN_RF_WRITE(mac, BWN_B2063_PA_SP4, 0xa0); BWN_RF_WRITE(mac, BWN_B2063_PA_SP2, 0x18); } else { BWN_RF_WRITE(mac, BWN_B2063_PA_SP3, 0x20); BWN_RF_WRITE(mac, BWN_B2063_PA_SP2, 0x20); } + + return (0); } -static void +static int bwn_phy_lp_rxcal_r2(struct bwn_mac *mac) { struct bwn_softc *sc = mac->mac_sc; static const struct bwn_wpair v1[] = { { BWN_B2063_RX_BB_SP8, 0x0 }, { BWN_B2063_RC_CALIB_CTL1, 0x7e }, { BWN_B2063_RC_CALIB_CTL1, 0x7c }, { BWN_B2063_RC_CALIB_CTL2, 0x15 }, { BWN_B2063_RC_CALIB_CTL3, 0x70 }, { BWN_B2063_RC_CALIB_CTL4, 0x52 }, { BWN_B2063_RC_CALIB_CTL5, 0x1 }, { BWN_B2063_RC_CALIB_CTL1, 0x7d } }; static const struct bwn_wpair v2[] = { { BWN_B2063_TX_BB_SP3, 0x0 }, { BWN_B2063_RC_CALIB_CTL1, 0x7e }, { BWN_B2063_RC_CALIB_CTL1, 0x7c }, { BWN_B2063_RC_CALIB_CTL2, 0x55 }, { BWN_B2063_RC_CALIB_CTL3, 0x76 } }; - uint32_t freqxtal = siba_get_cc_pmufreq(sc->sc_dev) * 1000; - int i; + u_int freqxtal; + int error, i; uint8_t tmp; + error = bhnd_get_clock_freq(sc->sc_dev, BHND_CLOCK_ALP, &freqxtal); + if (error) { + device_printf(sc->sc_dev, "failed to fetch clock frequency: %d", + error); + return (error); + } + tmp = BWN_RF_READ(mac, BWN_B2063_RX_BB_SP8) & 0xff; for (i = 0; i < 2; i++) BWN_RF_WRITE(mac, v1[i].reg, v1[i].value); BWN_RF_MASK(mac, BWN_B2063_PLL_SP1, 0xf7); for (i = 2; i < N(v1); i++) BWN_RF_WRITE(mac, v1[i].reg, v1[i].value); for (i = 0; i < 10000; i++) { if (BWN_RF_READ(mac, BWN_B2063_RC_CALIB_CTL6) & 0x2) break; DELAY(1000); } if (!(BWN_RF_READ(mac, BWN_B2063_RC_CALIB_CTL6) & 0x2)) BWN_RF_WRITE(mac, BWN_B2063_RX_BB_SP8, tmp); tmp = BWN_RF_READ(mac, BWN_B2063_TX_BB_SP3) & 0xff; for (i = 0; i < N(v2); i++) BWN_RF_WRITE(mac, v2[i].reg, v2[i].value); if (freqxtal == 24000000) { BWN_RF_WRITE(mac, BWN_B2063_RC_CALIB_CTL4, 0xfc); BWN_RF_WRITE(mac, BWN_B2063_RC_CALIB_CTL5, 0x0); } else { BWN_RF_WRITE(mac, BWN_B2063_RC_CALIB_CTL4, 0x13); BWN_RF_WRITE(mac, BWN_B2063_RC_CALIB_CTL5, 0x1); } BWN_RF_WRITE(mac, BWN_B2063_PA_SP7, 0x7d); for (i = 0; i < 10000; i++) { if (BWN_RF_READ(mac, BWN_B2063_RC_CALIB_CTL6) & 0x2) break; DELAY(1000); } if (!(BWN_RF_READ(mac, BWN_B2063_RC_CALIB_CTL6) & 0x2)) BWN_RF_WRITE(mac, BWN_B2063_TX_BB_SP3, tmp); BWN_RF_WRITE(mac, BWN_B2063_RC_CALIB_CTL1, 0x7e); + + return (0); } -static void +static int bwn_phy_lp_rccal_r12(struct bwn_mac *mac) { struct bwn_phy_lp *plp = &mac->mac_phy.phy_lp; struct bwn_softc *sc = mac->mac_sc; struct bwn_phy_lp_iq_est ie; struct bwn_txgain tx_gains; static const uint32_t pwrtbl[21] = { 0x10000, 0x10557, 0x10e2d, 0x113e0, 0x10f22, 0x0ff64, 0x0eda2, 0x0e5d4, 0x0efd1, 0x0fbe8, 0x0b7b8, 0x04b35, 0x01a5e, 0x00a0b, 0x00444, 0x001fd, 0x000ff, 0x00088, 0x0004c, 0x0002c, 0x0001a, }; uint32_t npwr, ipwr, sqpwr, tmp; int loopback, i, j, sum, error; uint16_t save[7]; uint8_t txo, bbmult, txpctlmode; error = bwn_phy_lp_switch_channel(mac, 7); if (error) device_printf(sc->sc_dev, "failed to change channel to 7 (%d)\n", error); txo = (BWN_PHY_READ(mac, BWN_PHY_AFE_CTL_OVR) & 0x40) ? 1 : 0; bbmult = bwn_phy_lp_get_bbmult(mac); if (txo) tx_gains = bwn_phy_lp_get_txgain(mac); save[0] = BWN_PHY_READ(mac, BWN_PHY_RF_OVERRIDE_0); save[1] = BWN_PHY_READ(mac, BWN_PHY_RF_OVERRIDE_VAL_0); save[2] = BWN_PHY_READ(mac, BWN_PHY_AFE_CTL_OVR); save[3] = BWN_PHY_READ(mac, BWN_PHY_AFE_CTL_OVRVAL); save[4] = BWN_PHY_READ(mac, BWN_PHY_RF_OVERRIDE_2); save[5] = BWN_PHY_READ(mac, BWN_PHY_RF_OVERRIDE_2_VAL); save[6] = BWN_PHY_READ(mac, BWN_PHY_LP_PHY_CTL); bwn_phy_lp_get_txpctlmode(mac); txpctlmode = plp->plp_txpctlmode; bwn_phy_lp_set_txpctlmode(mac, BWN_PHYLP_TXPCTL_OFF); /* disable CRS */ bwn_phy_lp_set_deaf(mac, 1); bwn_phy_lp_set_trsw_over(mac, 0, 1); BWN_PHY_MASK(mac, BWN_PHY_RF_OVERRIDE_VAL_0, 0xfffb); BWN_PHY_SET(mac, BWN_PHY_RF_OVERRIDE_0, 0x4); BWN_PHY_MASK(mac, BWN_PHY_RF_OVERRIDE_VAL_0, 0xfff7); BWN_PHY_SET(mac, BWN_PHY_RF_OVERRIDE_0, 0x8); BWN_PHY_SET(mac, BWN_PHY_RF_OVERRIDE_VAL_0, 0x10); BWN_PHY_SET(mac, BWN_PHY_RF_OVERRIDE_0, 0x10); BWN_PHY_MASK(mac, BWN_PHY_RF_OVERRIDE_VAL_0, 0xffdf); BWN_PHY_SET(mac, BWN_PHY_RF_OVERRIDE_0, 0x20); BWN_PHY_MASK(mac, BWN_PHY_RF_OVERRIDE_VAL_0, 0xffbf); BWN_PHY_SET(mac, BWN_PHY_RF_OVERRIDE_0, 0x40); BWN_PHY_SET(mac, BWN_PHY_RF_OVERRIDE_2_VAL, 0x7); BWN_PHY_SET(mac, BWN_PHY_RF_OVERRIDE_2_VAL, 0x38); BWN_PHY_MASK(mac, BWN_PHY_RF_OVERRIDE_2_VAL, 0xff3f); BWN_PHY_SET(mac, BWN_PHY_RF_OVERRIDE_2_VAL, 0x100); BWN_PHY_MASK(mac, BWN_PHY_RF_OVERRIDE_2_VAL, 0xfdff); BWN_PHY_WRITE(mac, BWN_PHY_PS_CTL_OVERRIDE_VAL0, 0); BWN_PHY_WRITE(mac, BWN_PHY_PS_CTL_OVERRIDE_VAL1, 1); BWN_PHY_WRITE(mac, BWN_PHY_PS_CTL_OVERRIDE_VAL2, 0x20); BWN_PHY_MASK(mac, BWN_PHY_RF_OVERRIDE_2_VAL, 0xfbff); BWN_PHY_MASK(mac, BWN_PHY_RF_OVERRIDE_2_VAL, 0xf7ff); BWN_PHY_WRITE(mac, BWN_PHY_TX_GAIN_CTL_OVERRIDE_VAL, 0); BWN_PHY_WRITE(mac, BWN_PHY_RX_GAIN_CTL_OVERRIDE_VAL, 0x45af); BWN_PHY_WRITE(mac, BWN_PHY_RF_OVERRIDE_2, 0x3ff); loopback = bwn_phy_lp_loopback(mac); if (loopback == -1) goto done; bwn_phy_lp_set_rxgain_idx(mac, loopback); BWN_PHY_SETMASK(mac, BWN_PHY_LP_PHY_CTL, 0xffbf, 0x40); BWN_PHY_SETMASK(mac, BWN_PHY_RF_OVERRIDE_2_VAL, 0xfff8, 0x1); BWN_PHY_SETMASK(mac, BWN_PHY_RF_OVERRIDE_2_VAL, 0xffc7, 0x8); BWN_PHY_SETMASK(mac, BWN_PHY_RF_OVERRIDE_2_VAL, 0xff3f, 0xc0); tmp = 0; memset(&ie, 0, sizeof(ie)); for (i = 128; i <= 159; i++) { BWN_RF_WRITE(mac, BWN_B2062_N_RXBB_CALIB2, i); sum = 0; for (j = 5; j <= 25; j++) { bwn_phy_lp_ddfs_turnon(mac, 1, 1, j, j, 0); if (!(bwn_phy_lp_rx_iq_est(mac, 1000, 32, &ie))) goto done; sqpwr = ie.ie_ipwr + ie.ie_qpwr; ipwr = ((pwrtbl[j - 5] >> 3) + 1) >> 1; npwr = bwn_phy_lp_roundup(sqpwr, (j == 5) ? sqpwr : 0, 12); sum += ((ipwr - npwr) * (ipwr - npwr)); if ((i == 128) || (sum < tmp)) { plp->plp_rccap = i; tmp = sum; } } } bwn_phy_lp_ddfs_turnoff(mac); done: /* restore CRS */ bwn_phy_lp_clear_deaf(mac, 1); BWN_PHY_MASK(mac, BWN_PHY_RF_OVERRIDE_0, 0xff80); BWN_PHY_MASK(mac, BWN_PHY_RF_OVERRIDE_2, 0xfc00); BWN_PHY_WRITE(mac, BWN_PHY_RF_OVERRIDE_VAL_0, save[1]); BWN_PHY_WRITE(mac, BWN_PHY_RF_OVERRIDE_0, save[0]); BWN_PHY_WRITE(mac, BWN_PHY_AFE_CTL_OVRVAL, save[3]); BWN_PHY_WRITE(mac, BWN_PHY_AFE_CTL_OVR, save[2]); BWN_PHY_WRITE(mac, BWN_PHY_RF_OVERRIDE_2_VAL, save[5]); BWN_PHY_WRITE(mac, BWN_PHY_RF_OVERRIDE_2, save[4]); BWN_PHY_WRITE(mac, BWN_PHY_LP_PHY_CTL, save[6]); bwn_phy_lp_set_bbmult(mac, bbmult); if (txo) bwn_phy_lp_set_txgain(mac, &tx_gains); bwn_phy_lp_set_txpctlmode(mac, txpctlmode); if (plp->plp_rccap) bwn_phy_lp_set_rccap(mac); + + return (0); } static void bwn_phy_lp_set_rccap(struct bwn_mac *mac) { struct bwn_phy_lp *plp = &mac->mac_phy.phy_lp; uint8_t rc_cap = (plp->plp_rccap & 0x1f) >> 1; if (mac->mac_phy.rev == 1) rc_cap = MIN(rc_cap + 5, 15); BWN_RF_WRITE(mac, BWN_B2062_N_RXBB_CALIB2, MAX(plp->plp_rccap - 4, 0x80)); BWN_RF_WRITE(mac, BWN_B2062_N_TXCTL_A, rc_cap | 0x80); BWN_RF_WRITE(mac, BWN_B2062_S_RXG_CNT16, ((plp->plp_rccap & 0x1f) >> 2) | 0x80); } static uint32_t bwn_phy_lp_roundup(uint32_t value, uint32_t div, uint8_t pre) { uint32_t i, q, r; if (div == 0) return (0); for (i = 0, q = value / div, r = value % div; i < pre; i++) { q <<= 1; if (r << 1 >= div) { q++; r = (r << 1) - div; } } if (r << 1 >= div) q++; return (q); } static void bwn_phy_lp_b2062_reset_pllbias(struct bwn_mac *mac) { struct bwn_softc *sc = mac->mac_sc; BWN_RF_WRITE(mac, BWN_B2062_S_RFPLLCTL2, 0xff); DELAY(20); - if (siba_get_chipid(sc->sc_dev) == 0x5354) { + if (sc->sc_cid.chip_id == BHND_CHIPID_BCM5354) { BWN_RF_WRITE(mac, BWN_B2062_N_COM1, 4); BWN_RF_WRITE(mac, BWN_B2062_S_RFPLLCTL2, 4); } else { BWN_RF_WRITE(mac, BWN_B2062_S_RFPLLCTL2, 0); } DELAY(5); } static void bwn_phy_lp_b2062_vco_calib(struct bwn_mac *mac) { BWN_RF_WRITE(mac, BWN_B2062_S_RFPLLCTL21, 0x42); BWN_RF_WRITE(mac, BWN_B2062_S_RFPLLCTL21, 0x62); DELAY(200); } static void bwn_phy_lp_b2062_tblinit(struct bwn_mac *mac) { #define FLAG_A 0x01 #define FLAG_G 0x02 struct bwn_softc *sc = mac->mac_sc; struct ieee80211com *ic = &sc->sc_ic; static const struct bwn_b206x_rfinit_entry bwn_b2062_init_tab[] = { { BWN_B2062_N_COM4, 0x1, 0x0, FLAG_A | FLAG_G, }, { BWN_B2062_N_PDNCTL1, 0x0, 0xca, FLAG_G, }, { BWN_B2062_N_PDNCTL3, 0x0, 0x0, FLAG_A | FLAG_G, }, { BWN_B2062_N_PDNCTL4, 0x15, 0x2a, FLAG_A | FLAG_G, }, { BWN_B2062_N_LGENC, 0xDB, 0xff, FLAG_A, }, { BWN_B2062_N_LGENATUNE0, 0xdd, 0x0, FLAG_A | FLAG_G, }, { BWN_B2062_N_LGENATUNE2, 0xdd, 0x0, FLAG_A | FLAG_G, }, { BWN_B2062_N_LGENATUNE3, 0x77, 0xB5, FLAG_A | FLAG_G, }, { BWN_B2062_N_LGENACTL3, 0x0, 0xff, FLAG_A | FLAG_G, }, { BWN_B2062_N_LGENACTL7, 0x33, 0x33, FLAG_A | FLAG_G, }, { BWN_B2062_N_RXA_CTL1, 0x0, 0x0, FLAG_G, }, { BWN_B2062_N_RXBB_CTL0, 0x82, 0x80, FLAG_A | FLAG_G, }, { BWN_B2062_N_RXBB_GAIN1, 0x4, 0x4, FLAG_A | FLAG_G, }, { BWN_B2062_N_RXBB_GAIN2, 0x0, 0x0, FLAG_A | FLAG_G, }, { BWN_B2062_N_TXCTL4, 0x3, 0x3, FLAG_A | FLAG_G, }, { BWN_B2062_N_TXCTL5, 0x2, 0x2, FLAG_A | FLAG_G, }, { BWN_B2062_N_TX_TUNE, 0x88, 0x1b, FLAG_A | FLAG_G, }, { BWN_B2062_S_COM4, 0x1, 0x0, FLAG_A | FLAG_G, }, { BWN_B2062_S_PDS_CTL0, 0xff, 0xff, FLAG_A | FLAG_G, }, { BWN_B2062_S_LGENG_CTL0, 0xf8, 0xd8, FLAG_A | FLAG_G, }, { BWN_B2062_S_LGENG_CTL1, 0x3c, 0x24, FLAG_A | FLAG_G, }, { BWN_B2062_S_LGENG_CTL8, 0x88, 0x80, FLAG_A | FLAG_G, }, { BWN_B2062_S_LGENG_CTL10, 0x88, 0x80, FLAG_A | FLAG_G, }, { BWN_B2062_S_RFPLLCTL0, 0x98, 0x98, FLAG_A | FLAG_G, }, { BWN_B2062_S_RFPLLCTL1, 0x10, 0x10, FLAG_A | FLAG_G, }, { BWN_B2062_S_RFPLLCTL5, 0x43, 0x43, FLAG_A | FLAG_G, }, { BWN_B2062_S_RFPLLCTL6, 0x47, 0x47, FLAG_A | FLAG_G, }, { BWN_B2062_S_RFPLLCTL7, 0xc, 0xc, FLAG_A | FLAG_G, }, { BWN_B2062_S_RFPLLCTL8, 0x11, 0x11, FLAG_A | FLAG_G, }, { BWN_B2062_S_RFPLLCTL9, 0x11, 0x11, FLAG_A | FLAG_G, }, { BWN_B2062_S_RFPLLCTL10, 0xe, 0xe, FLAG_A | FLAG_G, }, { BWN_B2062_S_RFPLLCTL11, 0x8, 0x8, FLAG_A | FLAG_G, }, { BWN_B2062_S_RFPLLCTL12, 0x33, 0x33, FLAG_A | FLAG_G, }, { BWN_B2062_S_RFPLLCTL13, 0xa, 0xa, FLAG_A | FLAG_G, }, { BWN_B2062_S_RFPLLCTL14, 0x6, 0x6, FLAG_A | FLAG_G, }, { BWN_B2062_S_RFPLLCTL18, 0x3e, 0x3e, FLAG_A | FLAG_G, }, { BWN_B2062_S_RFPLLCTL19, 0x13, 0x13, FLAG_A | FLAG_G, }, { BWN_B2062_S_RFPLLCTL21, 0x62, 0x62, FLAG_A | FLAG_G, }, { BWN_B2062_S_RFPLLCTL22, 0x7, 0x7, FLAG_A | FLAG_G, }, { BWN_B2062_S_RFPLLCTL23, 0x16, 0x16, FLAG_A | FLAG_G, }, { BWN_B2062_S_RFPLLCTL24, 0x5c, 0x5c, FLAG_A | FLAG_G, }, { BWN_B2062_S_RFPLLCTL25, 0x95, 0x95, FLAG_A | FLAG_G, }, { BWN_B2062_S_RFPLLCTL30, 0xa0, 0xa0, FLAG_A | FLAG_G, }, { BWN_B2062_S_RFPLLCTL31, 0x4, 0x4, FLAG_A | FLAG_G, }, { BWN_B2062_S_RFPLLCTL33, 0xcc, 0xcc, FLAG_A | FLAG_G, }, { BWN_B2062_S_RFPLLCTL34, 0x7, 0x7, FLAG_A | FLAG_G, }, { BWN_B2062_S_RXG_CNT8, 0xf, 0xf, FLAG_A, }, }; const struct bwn_b206x_rfinit_entry *br; unsigned int i; for (i = 0; i < N(bwn_b2062_init_tab); i++) { br = &bwn_b2062_init_tab[i]; if (IEEE80211_IS_CHAN_2GHZ(ic->ic_curchan)) { if (br->br_flags & FLAG_G) BWN_RF_WRITE(mac, br->br_offset, br->br_valueg); } else { if (br->br_flags & FLAG_A) BWN_RF_WRITE(mac, br->br_offset, br->br_valuea); } } #undef FLAG_A #undef FLAG_B } static void bwn_phy_lp_b2063_tblinit(struct bwn_mac *mac) { #define FLAG_A 0x01 #define FLAG_G 0x02 struct bwn_softc *sc = mac->mac_sc; struct ieee80211com *ic = &sc->sc_ic; static const struct bwn_b206x_rfinit_entry bwn_b2063_init_tab[] = { { BWN_B2063_COM1, 0x0, 0x0, FLAG_G, }, { BWN_B2063_COM10, 0x1, 0x0, FLAG_A, }, { BWN_B2063_COM16, 0x0, 0x0, FLAG_G, }, { BWN_B2063_COM17, 0x0, 0x0, FLAG_G, }, { BWN_B2063_COM18, 0x0, 0x0, FLAG_G, }, { BWN_B2063_COM19, 0x0, 0x0, FLAG_G, }, { BWN_B2063_COM20, 0x0, 0x0, FLAG_G, }, { BWN_B2063_COM21, 0x0, 0x0, FLAG_G, }, { BWN_B2063_COM22, 0x0, 0x0, FLAG_G, }, { BWN_B2063_COM23, 0x0, 0x0, FLAG_G, }, { BWN_B2063_COM24, 0x0, 0x0, FLAG_G, }, { BWN_B2063_LOGEN_SP1, 0xe8, 0xd4, FLAG_A | FLAG_G, }, { BWN_B2063_LOGEN_SP2, 0xa7, 0x53, FLAG_A | FLAG_G, }, { BWN_B2063_LOGEN_SP4, 0xf0, 0xf, FLAG_A | FLAG_G, }, { BWN_B2063_G_RX_SP1, 0x1f, 0x5e, FLAG_G, }, { BWN_B2063_G_RX_SP2, 0x7f, 0x7e, FLAG_G, }, { BWN_B2063_G_RX_SP3, 0x30, 0xf0, FLAG_G, }, { BWN_B2063_G_RX_SP7, 0x7f, 0x7f, FLAG_A | FLAG_G, }, { BWN_B2063_G_RX_SP10, 0xc, 0xc, FLAG_A | FLAG_G, }, { BWN_B2063_A_RX_SP1, 0x3c, 0x3f, FLAG_A, }, { BWN_B2063_A_RX_SP2, 0xfc, 0xfe, FLAG_A, }, { BWN_B2063_A_RX_SP7, 0x8, 0x8, FLAG_A | FLAG_G, }, { BWN_B2063_RX_BB_SP4, 0x60, 0x60, FLAG_A | FLAG_G, }, { BWN_B2063_RX_BB_SP8, 0x30, 0x30, FLAG_A | FLAG_G, }, { BWN_B2063_TX_RF_SP3, 0xc, 0xb, FLAG_A | FLAG_G, }, { BWN_B2063_TX_RF_SP4, 0x10, 0xf, FLAG_A | FLAG_G, }, { BWN_B2063_PA_SP1, 0x3d, 0xfd, FLAG_A | FLAG_G, }, { BWN_B2063_TX_BB_SP1, 0x2, 0x2, FLAG_A | FLAG_G, }, { BWN_B2063_BANDGAP_CTL1, 0x56, 0x56, FLAG_A | FLAG_G, }, { BWN_B2063_JTAG_VCO2, 0xF7, 0xF7, FLAG_A | FLAG_G, }, { BWN_B2063_G_RX_MIX3, 0x71, 0x71, FLAG_A | FLAG_G, }, { BWN_B2063_G_RX_MIX4, 0x71, 0x71, FLAG_A | FLAG_G, }, { BWN_B2063_A_RX_1ST2, 0xf0, 0x30, FLAG_A, }, { BWN_B2063_A_RX_PS6, 0x77, 0x77, FLAG_A | FLAG_G, }, { BWN_B2063_A_RX_MIX4, 0x3, 0x3, FLAG_A | FLAG_G, }, { BWN_B2063_A_RX_MIX5, 0xf, 0xf, FLAG_A | FLAG_G, }, { BWN_B2063_A_RX_MIX6, 0xf, 0xf, FLAG_A | FLAG_G, }, { BWN_B2063_RX_TIA_CTL1, 0x77, 0x77, FLAG_A | FLAG_G, }, { BWN_B2063_RX_TIA_CTL3, 0x77, 0x77, FLAG_A | FLAG_G, }, { BWN_B2063_RX_BB_CTL2, 0x4, 0x4, FLAG_A | FLAG_G, }, { BWN_B2063_PA_CTL1, 0x0, 0x4, FLAG_A, }, { BWN_B2063_VREG_CTL1, 0x3, 0x3, FLAG_A | FLAG_G, }, }; const struct bwn_b206x_rfinit_entry *br; unsigned int i; for (i = 0; i < N(bwn_b2063_init_tab); i++) { br = &bwn_b2063_init_tab[i]; if (IEEE80211_IS_CHAN_2GHZ(ic->ic_curchan)) { if (br->br_flags & FLAG_G) BWN_RF_WRITE(mac, br->br_offset, br->br_valueg); } else { if (br->br_flags & FLAG_A) BWN_RF_WRITE(mac, br->br_offset, br->br_valuea); } } #undef FLAG_A #undef FLAG_B } static void bwn_tab_read_multi(struct bwn_mac *mac, uint32_t typenoffset, int count, void *_data) { unsigned int i; uint32_t offset, type; uint8_t *data = _data; type = BWN_TAB_GETTYPE(typenoffset); offset = BWN_TAB_GETOFFSET(typenoffset); KASSERT(offset <= 0xffff, ("%s:%d: fail", __func__, __LINE__)); BWN_PHY_WRITE(mac, BWN_PHY_TABLE_ADDR, offset); for (i = 0; i < count; i++) { switch (type) { case BWN_TAB_8BIT: *data = BWN_PHY_READ(mac, BWN_PHY_TABLEDATALO) & 0xff; data++; break; case BWN_TAB_16BIT: *((uint16_t *)data) = BWN_PHY_READ(mac, BWN_PHY_TABLEDATALO); data += 2; break; case BWN_TAB_32BIT: *((uint32_t *)data) = BWN_PHY_READ(mac, BWN_PHY_TABLEDATAHI); *((uint32_t *)data) <<= 16; *((uint32_t *)data) |= BWN_PHY_READ(mac, BWN_PHY_TABLEDATALO); data += 4; break; default: KASSERT(0 == 1, ("%s:%d: fail", __func__, __LINE__)); } } } static void bwn_tab_write_multi(struct bwn_mac *mac, uint32_t typenoffset, int count, const void *_data) { uint32_t offset, type, value; const uint8_t *data = _data; unsigned int i; type = BWN_TAB_GETTYPE(typenoffset); offset = BWN_TAB_GETOFFSET(typenoffset); KASSERT(offset <= 0xffff, ("%s:%d: fail", __func__, __LINE__)); BWN_PHY_WRITE(mac, BWN_PHY_TABLE_ADDR, offset); for (i = 0; i < count; i++) { switch (type) { case BWN_TAB_8BIT: value = *data; data++; KASSERT(!(value & ~0xff), ("%s:%d: fail", __func__, __LINE__)); BWN_PHY_WRITE(mac, BWN_PHY_TABLEDATALO, value); break; case BWN_TAB_16BIT: value = *((const uint16_t *)data); data += 2; KASSERT(!(value & ~0xffff), ("%s:%d: fail", __func__, __LINE__)); BWN_PHY_WRITE(mac, BWN_PHY_TABLEDATALO, value); break; case BWN_TAB_32BIT: value = *((const uint32_t *)data); data += 4; BWN_PHY_WRITE(mac, BWN_PHY_TABLEDATAHI, value >> 16); BWN_PHY_WRITE(mac, BWN_PHY_TABLEDATALO, value); break; default: KASSERT(0 == 1, ("%s:%d: fail", __func__, __LINE__)); } } } static struct bwn_txgain bwn_phy_lp_get_txgain(struct bwn_mac *mac) { struct bwn_txgain tg; uint16_t tmp; tg.tg_dac = (BWN_PHY_READ(mac, BWN_PHY_AFE_DAC_CTL) & 0x380) >> 7; if (mac->mac_phy.rev < 2) { tmp = BWN_PHY_READ(mac, BWN_PHY_TX_GAIN_CTL_OVERRIDE_VAL) & 0x7ff; tg.tg_gm = tmp & 0x0007; tg.tg_pga = (tmp & 0x0078) >> 3; tg.tg_pad = (tmp & 0x780) >> 7; return (tg); } tmp = BWN_PHY_READ(mac, BWN_PHY_TX_GAIN_CTL_OVERRIDE_VAL); tg.tg_pad = BWN_PHY_READ(mac, BWN_PHY_OFDM(0xfb)) & 0xff; tg.tg_gm = tmp & 0xff; tg.tg_pga = (tmp >> 8) & 0xff; return (tg); } static uint8_t bwn_phy_lp_get_bbmult(struct bwn_mac *mac) { return (bwn_tab_read(mac, BWN_TAB_2(0, 87)) & 0xff00) >> 8; } static void bwn_phy_lp_set_txgain(struct bwn_mac *mac, struct bwn_txgain *tg) { uint16_t pa; if (mac->mac_phy.rev < 2) { BWN_PHY_SETMASK(mac, BWN_PHY_TX_GAIN_CTL_OVERRIDE_VAL, 0xf800, (tg->tg_pad << 7) | (tg->tg_pga << 3) | tg->tg_gm); bwn_phy_lp_set_txgain_dac(mac, tg->tg_dac); bwn_phy_lp_set_txgain_override(mac); return; } pa = bwn_phy_lp_get_pa_gain(mac); BWN_PHY_WRITE(mac, BWN_PHY_TX_GAIN_CTL_OVERRIDE_VAL, (tg->tg_pga << 8) | tg->tg_gm); BWN_PHY_SETMASK(mac, BWN_PHY_OFDM(0xfb), 0x8000, tg->tg_pad | (pa << 6)); BWN_PHY_WRITE(mac, BWN_PHY_OFDM(0xfc), (tg->tg_pga << 8) | tg->tg_gm); BWN_PHY_SETMASK(mac, BWN_PHY_OFDM(0xfd), 0x8000, tg->tg_pad | (pa << 8)); bwn_phy_lp_set_txgain_dac(mac, tg->tg_dac); bwn_phy_lp_set_txgain_override(mac); } static void bwn_phy_lp_set_bbmult(struct bwn_mac *mac, uint8_t bbmult) { bwn_tab_write(mac, BWN_TAB_2(0, 87), (uint16_t)bbmult << 8); } static void bwn_phy_lp_set_trsw_over(struct bwn_mac *mac, uint8_t tx, uint8_t rx) { uint16_t trsw = (tx << 1) | rx; BWN_PHY_SETMASK(mac, BWN_PHY_RF_OVERRIDE_VAL_0, 0xfffc, trsw); BWN_PHY_SET(mac, BWN_PHY_RF_OVERRIDE_0, 0x3); } static void bwn_phy_lp_set_rxgain(struct bwn_mac *mac, uint32_t gain) { struct bwn_softc *sc = mac->mac_sc; struct ieee80211com *ic = &sc->sc_ic; uint16_t ext_lna, high_gain, lna, low_gain, trsw, tmp; if (mac->mac_phy.rev < 2) { trsw = gain & 0x1; lna = (gain & 0xfffc) | ((gain & 0xc) >> 2); ext_lna = (gain & 2) >> 1; BWN_PHY_SETMASK(mac, BWN_PHY_RF_OVERRIDE_VAL_0, 0xfffe, trsw); BWN_PHY_SETMASK(mac, BWN_PHY_RF_OVERRIDE_2_VAL, 0xfbff, ext_lna << 10); BWN_PHY_SETMASK(mac, BWN_PHY_RF_OVERRIDE_2_VAL, 0xf7ff, ext_lna << 11); BWN_PHY_WRITE(mac, BWN_PHY_RX_GAIN_CTL_OVERRIDE_VAL, lna); } else { low_gain = gain & 0xffff; high_gain = (gain >> 16) & 0xf; ext_lna = (gain >> 21) & 0x1; trsw = ~(gain >> 20) & 0x1; BWN_PHY_SETMASK(mac, BWN_PHY_RF_OVERRIDE_VAL_0, 0xfffe, trsw); BWN_PHY_SETMASK(mac, BWN_PHY_RF_OVERRIDE_2_VAL, 0xfdff, ext_lna << 9); BWN_PHY_SETMASK(mac, BWN_PHY_RF_OVERRIDE_2_VAL, 0xfbff, ext_lna << 10); BWN_PHY_WRITE(mac, BWN_PHY_RX_GAIN_CTL_OVERRIDE_VAL, low_gain); BWN_PHY_SETMASK(mac, BWN_PHY_AFE_DDFS, 0xfff0, high_gain); if (IEEE80211_IS_CHAN_2GHZ(ic->ic_curchan)) { tmp = (gain >> 2) & 0x3; BWN_PHY_SETMASK(mac, BWN_PHY_RF_OVERRIDE_2_VAL, 0xe7ff, tmp<<11); BWN_PHY_SETMASK(mac, BWN_PHY_OFDM(0xe6), 0xffe7, tmp << 3); } } BWN_PHY_SET(mac, BWN_PHY_RF_OVERRIDE_0, 0x1); BWN_PHY_SET(mac, BWN_PHY_RF_OVERRIDE_0, 0x10); BWN_PHY_SET(mac, BWN_PHY_RF_OVERRIDE_0, 0x40); if (mac->mac_phy.rev >= 2) { BWN_PHY_SET(mac, BWN_PHY_RF_OVERRIDE_2, 0x100); if (IEEE80211_IS_CHAN_2GHZ(ic->ic_curchan)) { BWN_PHY_SET(mac, BWN_PHY_RF_OVERRIDE_2, 0x400); BWN_PHY_SET(mac, BWN_PHY_OFDM(0xe5), 0x8); } return; } BWN_PHY_SET(mac, BWN_PHY_RF_OVERRIDE_2, 0x200); } static void bwn_phy_lp_set_deaf(struct bwn_mac *mac, uint8_t user) { struct bwn_phy_lp *plp = &mac->mac_phy.phy_lp; if (user) plp->plp_crsusr_off = 1; else plp->plp_crssys_off = 1; BWN_PHY_SETMASK(mac, BWN_PHY_CRSGAIN_CTL, 0xff1f, 0x80); } static void bwn_phy_lp_clear_deaf(struct bwn_mac *mac, uint8_t user) { struct bwn_phy_lp *plp = &mac->mac_phy.phy_lp; struct bwn_softc *sc = mac->mac_sc; struct ieee80211com *ic = &sc->sc_ic; if (user) plp->plp_crsusr_off = 0; else plp->plp_crssys_off = 0; if (plp->plp_crsusr_off || plp->plp_crssys_off) return; if (IEEE80211_IS_CHAN_2GHZ(ic->ic_curchan)) BWN_PHY_SETMASK(mac, BWN_PHY_CRSGAIN_CTL, 0xff1f, 0x60); else BWN_PHY_SETMASK(mac, BWN_PHY_CRSGAIN_CTL, 0xff1f, 0x20); } static int bwn_phy_lp_calc_rx_iq_comp(struct bwn_mac *mac, uint16_t sample) { #define CALC_COEFF(_v, _x, _y, _z) do { \ int _t; \ _t = _x - 20; \ if (_t >= 0) { \ _v = ((_y << (30 - _x)) + (_z >> (1 + _t))) / (_z >> _t); \ } else { \ _v = ((_y << (30 - _x)) + (_z << (-1 - _t))) / (_z << -_t); \ } \ } while (0) #define CALC_COEFF2(_v, _x, _y, _z) do { \ int _t; \ _t = _x - 11; \ if (_t >= 0) \ _v = (_y << (31 - _x)) / (_z >> _t); \ else \ _v = (_y << (31 - _x)) / (_z << -_t); \ } while (0) struct bwn_phy_lp_iq_est ie; uint16_t v0, v1; int tmp[2], ret; v1 = BWN_PHY_READ(mac, BWN_PHY_RX_COMP_COEFF_S); v0 = v1 >> 8; v1 |= 0xff; BWN_PHY_SETMASK(mac, BWN_PHY_RX_COMP_COEFF_S, 0xff00, 0x00c0); BWN_PHY_MASK(mac, BWN_PHY_RX_COMP_COEFF_S, 0x00ff); ret = bwn_phy_lp_rx_iq_est(mac, sample, 32, &ie); if (ret == 0) goto done; if (ie.ie_ipwr + ie.ie_qpwr < 2) { ret = 0; goto done; } CALC_COEFF(tmp[0], bwn_nbits(ie.ie_iqprod), ie.ie_iqprod, ie.ie_ipwr); CALC_COEFF2(tmp[1], bwn_nbits(ie.ie_qpwr), ie.ie_qpwr, ie.ie_ipwr); tmp[1] = -bwn_sqrt(mac, tmp[1] - (tmp[0] * tmp[0])); v0 = tmp[0] >> 3; v1 = tmp[1] >> 4; done: BWN_PHY_SETMASK(mac, BWN_PHY_RX_COMP_COEFF_S, 0xff00, v1); BWN_PHY_SETMASK(mac, BWN_PHY_RX_COMP_COEFF_S, 0x00ff, v0 << 8); return ret; #undef CALC_COEFF #undef CALC_COEFF2 } static void bwn_phy_lp_tblinit_r01(struct bwn_mac *mac) { static const uint16_t noisescale[] = { 0xa4a4, 0xa4a4, 0xa4a4, 0xa4a4, 0xa4a4, 0xa4a4, 0xa4a4, 0xa4a4, 0xa4a4, 0xa4a4, 0xa4a4, 0xa4a4, 0xa4a4, 0xa400, 0xa4a4, 0xa4a4, 0xa4a4, 0xa4a4, 0xa4a4, 0xa4a4, 0xa4a4, 0xa4a4, 0xa4a4, 0xa4a4, 0xa4a4, 0xa4a4, 0x00a4, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x4c00, 0x2d36, 0x0000, 0x0000, 0x4c00, 0x2d36, }; static const uint16_t crsgainnft[] = { 0x0366, 0x036a, 0x036f, 0x0364, 0x0367, 0x036d, 0x0374, 0x037f, 0x036f, 0x037b, 0x038a, 0x0378, 0x0367, 0x036d, 0x0375, 0x0381, 0x0374, 0x0381, 0x0392, 0x03a9, 0x03c4, 0x03e1, 0x0001, 0x001f, 0x0040, 0x005e, 0x007f, 0x009e, 0x00bd, 0x00dd, 0x00fd, 0x011d, 0x013d, }; static const uint16_t filterctl[] = { 0xa0fc, 0x10fc, 0x10db, 0x20b7, 0xff93, 0x10bf, 0x109b, 0x2077, 0xff53, 0x0127, }; static const uint32_t psctl[] = { 0x00010000, 0x000000a0, 0x00040000, 0x00000048, 0x08080101, 0x00000080, 0x08080101, 0x00000040, 0x08080101, 0x000000c0, 0x08a81501, 0x000000c0, 0x0fe8fd01, 0x000000c0, 0x08300105, 0x000000c0, 0x08080201, 0x000000c0, 0x08280205, 0x000000c0, 0xe80802fe, 0x000000c7, 0x28080206, 0x000000c0, 0x08080202, 0x000000c0, 0x0ba87602, 0x000000c0, 0x1068013d, 0x000000c0, 0x10280105, 0x000000c0, 0x08880102, 0x000000c0, 0x08280106, 0x000000c0, 0xe80801fd, 0x000000c7, 0xa8080115, 0x000000c0, }; static const uint16_t ofdmcckgain_r0[] = { 0x0001, 0x0001, 0x0001, 0x0001, 0x1001, 0x2001, 0x3001, 0x4001, 0x5001, 0x6001, 0x7001, 0x7011, 0x7021, 0x2035, 0x2045, 0x2055, 0x2065, 0x2075, 0x006d, 0x007d, 0x014d, 0x015d, 0x115d, 0x035d, 0x135d, 0x055d, 0x155d, 0x0d5d, 0x1d5d, 0x2d5d, 0x555d, 0x655d, 0x755d, }; static const uint16_t ofdmcckgain_r1[] = { 0x5000, 0x6000, 0x7000, 0x0001, 0x1001, 0x2001, 0x3001, 0x4001, 0x5001, 0x6001, 0x7001, 0x7011, 0x7021, 0x2035, 0x2045, 0x2055, 0x2065, 0x2075, 0x006d, 0x007d, 0x014d, 0x015d, 0x115d, 0x035d, 0x135d, 0x055d, 0x155d, 0x0d5d, 0x1d5d, 0x2d5d, 0x555d, 0x655d, 0x755d, }; static const uint16_t gaindelta[] = { 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, }; static const uint32_t txpwrctl[] = { 0x00000050, 0x0000004f, 0x0000004e, 0x0000004d, 0x0000004c, 0x0000004b, 0x0000004a, 0x00000049, 0x00000048, 0x00000047, 0x00000046, 0x00000045, 0x00000044, 0x00000043, 0x00000042, 0x00000041, 0x00000040, 0x0000003f, 0x0000003e, 0x0000003d, 0x0000003c, 0x0000003b, 0x0000003a, 0x00000039, 0x00000038, 0x00000037, 0x00000036, 0x00000035, 0x00000034, 0x00000033, 0x00000032, 0x00000031, 0x00000030, 0x0000002f, 0x0000002e, 0x0000002d, 0x0000002c, 0x0000002b, 0x0000002a, 0x00000029, 0x00000028, 0x00000027, 0x00000026, 0x00000025, 0x00000024, 0x00000023, 0x00000022, 0x00000021, 0x00000020, 0x0000001f, 0x0000001e, 0x0000001d, 0x0000001c, 0x0000001b, 0x0000001a, 0x00000019, 0x00000018, 0x00000017, 0x00000016, 0x00000015, 0x00000014, 0x00000013, 0x00000012, 0x00000011, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x000075a0, 0x000075a0, 0x000075a1, 0x000075a1, 0x000075a2, 0x000075a2, 0x000075a3, 0x000075a3, 0x000074b0, 0x000074b0, 0x000074b1, 0x000074b1, 0x000074b2, 0x000074b2, 0x000074b3, 0x000074b3, 0x00006d20, 0x00006d20, 0x00006d21, 0x00006d21, 0x00006d22, 0x00006d22, 0x00006d23, 0x00006d23, 0x00004660, 0x00004660, 0x00004661, 0x00004661, 0x00004662, 0x00004662, 0x00004663, 0x00004663, 0x00003e60, 0x00003e60, 0x00003e61, 0x00003e61, 0x00003e62, 0x00003e62, 0x00003e63, 0x00003e63, 0x00003660, 0x00003660, 0x00003661, 0x00003661, 0x00003662, 0x00003662, 0x00003663, 0x00003663, 0x00002e60, 0x00002e60, 0x00002e61, 0x00002e61, 0x00002e62, 0x00002e62, 0x00002e63, 0x00002e63, 0x00002660, 0x00002660, 0x00002661, 0x00002661, 0x00002662, 0x00002662, 0x00002663, 0x00002663, 0x000025e0, 0x000025e0, 0x000025e1, 0x000025e1, 0x000025e2, 0x000025e2, 0x000025e3, 0x000025e3, 0x00001de0, 0x00001de0, 0x00001de1, 0x00001de1, 0x00001de2, 0x00001de2, 0x00001de3, 0x00001de3, 0x00001d60, 0x00001d60, 0x00001d61, 0x00001d61, 0x00001d62, 0x00001d62, 0x00001d63, 0x00001d63, 0x00001560, 0x00001560, 0x00001561, 0x00001561, 0x00001562, 0x00001562, 0x00001563, 0x00001563, 0x00000d60, 0x00000d60, 0x00000d61, 0x00000d61, 0x00000d62, 0x00000d62, 0x00000d63, 0x00000d63, 0x00000ce0, 0x00000ce0, 0x00000ce1, 0x00000ce1, 0x00000ce2, 0x00000ce2, 0x00000ce3, 0x00000ce3, 0x00000e10, 0x00000e10, 0x00000e11, 0x00000e11, 0x00000e12, 0x00000e12, 0x00000e13, 0x00000e13, 0x00000bf0, 0x00000bf0, 0x00000bf1, 0x00000bf1, 0x00000bf2, 0x00000bf2, 0x00000bf3, 0x00000bf3, 0x04200000, 0x04000000, 0x04200000, 0x04000000, 0x04200000, 0x04000000, 0x04200000, 0x04000000, 0x04200000, 0x04000000, 0x04200000, 0x04000000, 0x04200000, 0x04000000, 0x04200000, 0x04000000, 0x04200000, 0x04000000, 0x04200000, 0x04000000, 0x04200000, 0x04000000, 0x04200000, 0x04000000, 0x04200000, 0x04000000, 0x04200000, 0x04000000, 0x04200000, 0x04000000, 0x04200000, 0x04000000, 0x04200000, 0x04000000, 0x04200000, 0x04000000, 0x04200000, 0x04000000, 0x04200000, 0x04000000, 0x04200000, 0x04000000, 0x04200000, 0x04000000, 0x04200000, 0x04000000, 0x04200000, 0x04000000, 0x04200000, 0x04000000, 0x04200000, 0x04000000, 0x04200000, 0x04000000, 0x04200000, 0x04000000, 0x04200000, 0x04000000, 0x04200000, 0x04000000, 0x04200000, 0x04000000, 0x04200000, 0x04000000, 0x04200000, 0x04000000, 0x04200000, 0x04000000, 0x04200000, 0x04000000, 0x04200000, 0x04000000, 0x04200000, 0x04000000, 0x04200000, 0x04000000, 0x04200000, 0x04000000, 0x04200000, 0x04000000, 0x04200000, 0x04000000, 0x04200000, 0x04000000, 0x04200000, 0x04000000, 0x04200000, 0x04000000, 0x04200000, 0x04000000, 0x04200000, 0x04000000, 0x04200000, 0x04000000, 0x04200000, 0x04000000, 0x04200000, 0x04000000, 0x04200000, 0x04000000, 0x04200000, 0x04000000, 0x04200000, 0x04000000, 0x04200000, 0x04000000, 0x04200000, 0x04000000, 0x04200000, 0x04000000, 0x04200000, 0x04000000, 0x04200000, 0x04000000, 0x04200000, 0x04000000, 0x04200000, 0x04000000, 0x04200000, 0x04000000, 0x04200000, 0x04000000, 0x04200000, 0x04000000, 0x04200000, 0x04000000, 0x04200000, 0x04000000, 0x000000ff, 0x000002fc, 0x0000fa08, 0x00000305, 0x00000206, 0x00000304, 0x0000fb04, 0x0000fcff, 0x000005fb, 0x0000fd01, 0x00000401, 0x00000006, 0x0000ff03, 0x000007fc, 0x0000fc08, 0x00000203, 0x0000fffb, 0x00000600, 0x0000fa01, 0x0000fc03, 0x0000fe06, 0x0000fe00, 0x00000102, 0x000007fd, 0x000004fb, 0x000006ff, 0x000004fd, 0x0000fdfa, 0x000007fb, 0x0000fdfa, 0x0000fa06, 0x00000500, 0x0000f902, 0x000007fa, 0x0000fafa, 0x00000500, 0x000007fa, 0x00000700, 0x00000305, 0x000004ff, 0x00000801, 0x00000503, 0x000005f9, 0x00000404, 0x0000fb08, 0x000005fd, 0x00000501, 0x00000405, 0x0000fb03, 0x000007fc, 0x00000403, 0x00000303, 0x00000402, 0x0000faff, 0x0000fe05, 0x000005fd, 0x0000fe01, 0x000007fa, 0x00000202, 0x00000504, 0x00000102, 0x000008fe, 0x0000fa04, 0x0000fafc, 0x0000fe08, 0x000000f9, 0x000002fa, 0x000003fe, 0x00000304, 0x000004f9, 0x00000100, 0x0000fd06, 0x000008fc, 0x00000701, 0x00000504, 0x0000fdfe, 0x0000fdfc, 0x000003fe, 0x00000704, 0x000002fc, 0x000004f9, 0x0000fdfd, 0x0000fa07, 0x00000205, 0x000003fd, 0x000005fb, 0x000004f9, 0x00000804, 0x0000fc06, 0x0000fcf9, 0x00000100, 0x0000fe05, 0x00000408, 0x0000fb02, 0x00000304, 0x000006fe, 0x000004fa, 0x00000305, 0x000008fc, 0x00000102, 0x000001fd, 0x000004fc, 0x0000fe03, 0x00000701, 0x000001fb, 0x000001f9, 0x00000206, 0x000006fd, 0x00000508, 0x00000700, 0x00000304, 0x000005fe, 0x000005ff, 0x0000fa04, 0x00000303, 0x0000fefb, 0x000007f9, 0x0000fefc, 0x000004fd, 0x000005fc, 0x0000fffd, 0x0000fc08, 0x0000fbf9, 0x0000fd07, 0x000008fb, 0x0000fe02, 0x000006fb, 0x00000702, }; KASSERT(mac->mac_phy.rev < 2, ("%s:%d: fail", __func__, __LINE__)); bwn_tab_write_multi(mac, BWN_TAB_1(2, 0), N(bwn_tab_sigsq_tbl), bwn_tab_sigsq_tbl); bwn_tab_write_multi(mac, BWN_TAB_2(1, 0), N(noisescale), noisescale); bwn_tab_write_multi(mac, BWN_TAB_2(14, 0), N(crsgainnft), crsgainnft); bwn_tab_write_multi(mac, BWN_TAB_2(8, 0), N(filterctl), filterctl); bwn_tab_write_multi(mac, BWN_TAB_4(9, 0), N(psctl), psctl); bwn_tab_write_multi(mac, BWN_TAB_1(6, 0), N(bwn_tab_pllfrac_tbl), bwn_tab_pllfrac_tbl); bwn_tab_write_multi(mac, BWN_TAB_2(0, 0), N(bwn_tabl_iqlocal_tbl), bwn_tabl_iqlocal_tbl); if (mac->mac_phy.rev == 0) { bwn_tab_write_multi(mac, BWN_TAB_2(13, 0), N(ofdmcckgain_r0), ofdmcckgain_r0); bwn_tab_write_multi(mac, BWN_TAB_2(12, 0), N(ofdmcckgain_r0), ofdmcckgain_r0); } else { bwn_tab_write_multi(mac, BWN_TAB_2(13, 0), N(ofdmcckgain_r1), ofdmcckgain_r1); bwn_tab_write_multi(mac, BWN_TAB_2(12, 0), N(ofdmcckgain_r1), ofdmcckgain_r1); } bwn_tab_write_multi(mac, BWN_TAB_2(15, 0), N(gaindelta), gaindelta); bwn_tab_write_multi(mac, BWN_TAB_4(10, 0), N(txpwrctl), txpwrctl); } static void bwn_phy_lp_tblinit_r2(struct bwn_mac *mac) { struct bwn_softc *sc = mac->mac_sc; int i; static const uint16_t noisescale[] = { 0x00a4, 0x00a4, 0x00a4, 0x00a4, 0x00a4, 0x00a4, 0x00a4, 0x00a4, 0x00a4, 0x00a4, 0x00a4, 0x00a4, 0x00a4, 0x00a4, 0x00a4, 0x00a4, 0x00a4, 0x00a4, 0x00a4, 0x00a4, 0x00a4, 0x00a4, 0x00a4, 0x00a4, 0x00a4, 0x00a4, 0x0000, 0x00a4, 0x00a4, 0x00a4, 0x00a4, 0x00a4, 0x00a4, 0x00a4, 0x00a4, 0x00a4, 0x00a4, 0x00a4, 0x00a4, 0x00a4, 0x00a4, 0x00a4, 0x00a4, 0x00a4, 0x00a4, 0x00a4, 0x00a4, 0x00a4, 0x00a4, 0x00a4, 0x00a4, 0x00a4, 0x00a4 }; static const uint32_t filterctl[] = { 0x000141fc, 0x000021fc, 0x000021b7, 0x0000416f, 0x0001ff27, 0x0000217f, 0x00002137, 0x000040ef, 0x0001fea7, 0x0000024f }; static const uint32_t psctl[] = { 0x00e38e08, 0x00e08e38, 0x00000000, 0x00000000, 0x00000000, 0x00002080, 0x00006180, 0x00003002, 0x00000040, 0x00002042, 0x00180047, 0x00080043, 0x00000041, 0x000020c1, 0x00046006, 0x00042002, 0x00040000, 0x00002003, 0x00180006, 0x00080002 }; static const uint32_t gainidx[] = { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x10000001, 0x00000000, 0x20000082, 0x00000000, 0x40000104, 0x00000000, 0x60004207, 0x00000001, 0x7000838a, 0x00000001, 0xd021050d, 0x00000001, 0xe041c683, 0x00000001, 0x50828805, 0x00000000, 0x80e34288, 0x00000000, 0xb144040b, 0x00000000, 0xe1a6058e, 0x00000000, 0x12064711, 0x00000001, 0xb0a18612, 0x00000010, 0xe1024794, 0x00000010, 0x11630915, 0x00000011, 0x31c3ca1b, 0x00000011, 0xc1848a9c, 0x00000018, 0xf1e50da0, 0x00000018, 0x22468e21, 0x00000019, 0x4286d023, 0x00000019, 0xa347d0a4, 0x00000019, 0xb36811a6, 0x00000019, 0xf3e89227, 0x00000019, 0x0408d329, 0x0000001a, 0x244953aa, 0x0000001a, 0x346994ab, 0x0000001a, 0x54aa152c, 0x0000001a, 0x64ca55ad, 0x0000001a, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x10000001, 0x00000000, 0x20000082, 0x00000000, 0x40000104, 0x00000000, 0x60004207, 0x00000001, 0x7000838a, 0x00000001, 0xd021050d, 0x00000001, 0xe041c683, 0x00000001, 0x50828805, 0x00000000, 0x80e34288, 0x00000000, 0xb144040b, 0x00000000, 0xe1a6058e, 0x00000000, 0x12064711, 0x00000001, 0xb0a18612, 0x00000010, 0xe1024794, 0x00000010, 0x11630915, 0x00000011, 0x31c3ca1b, 0x00000011, 0xc1848a9c, 0x00000018, 0xf1e50da0, 0x00000018, 0x22468e21, 0x00000019, 0x4286d023, 0x00000019, 0xa347d0a4, 0x00000019, 0xb36811a6, 0x00000019, 0xf3e89227, 0x00000019, 0x0408d329, 0x0000001a, 0x244953aa, 0x0000001a, 0x346994ab, 0x0000001a, 0x54aa152c, 0x0000001a, 0x64ca55ad, 0x0000001a }; static const uint16_t auxgainidx[] = { 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0001, 0x0002, 0x0004, 0x0016, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0001, 0x0002, 0x0004, 0x0016 }; static const uint16_t swctl[] = { 0x0128, 0x0128, 0x0009, 0x0009, 0x0028, 0x0028, 0x0028, 0x0028, 0x0128, 0x0128, 0x0009, 0x0009, 0x0028, 0x0028, 0x0028, 0x0028, 0x0009, 0x0009, 0x0009, 0x0009, 0x0009, 0x0009, 0x0009, 0x0009, 0x0018, 0x0018, 0x0018, 0x0018, 0x0018, 0x0018, 0x0018, 0x0018, 0x0128, 0x0128, 0x0009, 0x0009, 0x0028, 0x0028, 0x0028, 0x0028, 0x0128, 0x0128, 0x0009, 0x0009, 0x0028, 0x0028, 0x0028, 0x0028, 0x0009, 0x0009, 0x0009, 0x0009, 0x0009, 0x0009, 0x0009, 0x0009, 0x0018, 0x0018, 0x0018, 0x0018, 0x0018, 0x0018, 0x0018, 0x0018 }; static const uint8_t hf[] = { 0x4b, 0x36, 0x24, 0x18, 0x49, 0x34, 0x23, 0x17, 0x48, 0x33, 0x23, 0x17, 0x48, 0x33, 0x23, 0x17 }; static const uint32_t gainval[] = { 0x00000008, 0x0000000e, 0x00000014, 0x0000001a, 0x000000fb, 0x00000004, 0x00000008, 0x0000000d, 0x00000001, 0x00000004, 0x00000007, 0x0000000a, 0x0000000d, 0x00000010, 0x00000012, 0x00000015, 0x00000000, 0x00000006, 0x0000000c, 0x00000000, 0x00000000, 0x00000000, 0x00000012, 0x00000000, 0x00000000, 0x00000000, 0x00000018, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x0000001e, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000003, 0x00000006, 0x00000009, 0x0000000c, 0x0000000f, 0x00000012, 0x00000015, 0x00000018, 0x0000001b, 0x0000001e, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000009, 0x000000f1, 0x00000000, 0x00000000 }; static const uint16_t gain[] = { 0x0000, 0x0400, 0x0800, 0x0802, 0x0804, 0x0806, 0x0807, 0x0808, 0x080a, 0x080b, 0x080c, 0x080e, 0x080f, 0x0810, 0x0812, 0x0813, 0x0814, 0x0816, 0x0817, 0x081a, 0x081b, 0x081f, 0x0820, 0x0824, 0x0830, 0x0834, 0x0837, 0x083b, 0x083f, 0x0840, 0x0844, 0x0857, 0x085b, 0x085f, 0x08d7, 0x08db, 0x08df, 0x0957, 0x095b, 0x095f, 0x0b57, 0x0b5b, 0x0b5f, 0x0f5f, 0x135f, 0x175f, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000 }; static const uint32_t papdeps[] = { 0x00000000, 0x00013ffc, 0x0001dff3, 0x0001bff0, 0x00023fe9, 0x00021fdf, 0x00028fdf, 0x00033fd2, 0x00039fcb, 0x00043fc7, 0x0004efc2, 0x00055fb5, 0x0005cfb0, 0x00063fa8, 0x00068fa3, 0x00071f98, 0x0007ef92, 0x00084f8b, 0x0008df82, 0x00097f77, 0x0009df69, 0x000a3f62, 0x000adf57, 0x000b6f4c, 0x000bff41, 0x000c9f39, 0x000cff30, 0x000dbf27, 0x000e4f1e, 0x000edf16, 0x000f7f13, 0x00102f11, 0x00110f10, 0x0011df11, 0x0012ef15, 0x00143f1c, 0x00158f27, 0x00172f35, 0x00193f47, 0x001baf5f, 0x001e6f7e, 0x0021cfa4, 0x0025bfd2, 0x002a2008, 0x002fb047, 0x00360090, 0x003d40e0, 0x0045c135, 0x004fb189, 0x005ae1d7, 0x0067221d, 0x0075025a, 0x007ff291, 0x007ff2bf, 0x007ff2e3, 0x007ff2ff, 0x007ff315, 0x007ff329, 0x007ff33f, 0x007ff356, 0x007ff36e, 0x007ff39c, 0x007ff441, 0x007ff506 }; static const uint32_t papdmult[] = { 0x001111e0, 0x00652051, 0x00606055, 0x005b005a, 0x00555060, 0x00511065, 0x004c806b, 0x0047d072, 0x00444078, 0x00400080, 0x003ca087, 0x0039408f, 0x0035e098, 0x0032e0a1, 0x003030aa, 0x002d80b4, 0x002ae0bf, 0x002880ca, 0x002640d6, 0x002410e3, 0x002220f0, 0x002020ff, 0x001e510e, 0x001ca11e, 0x001b012f, 0x00199140, 0x00182153, 0x0016c168, 0x0015817d, 0x00145193, 0x001321ab, 0x001211c5, 0x001111e0, 0x001021fc, 0x000f321a, 0x000e523a, 0x000d925c, 0x000cd27f, 0x000c12a5, 0x000b62cd, 0x000ac2f8, 0x000a2325, 0x00099355, 0x00091387, 0x000883bd, 0x000813f5, 0x0007a432, 0x00073471, 0x0006c4b5, 0x000664fc, 0x00061547, 0x0005b598, 0x000565ec, 0x00051646, 0x0004d6a5, 0x0004870a, 0x00044775, 0x000407e6, 0x0003d85e, 0x000398dd, 0x00036963, 0x000339f2, 0x00030a89, 0x0002db28 }; static const uint32_t gainidx_a0[] = { 0x001111e0, 0x00652051, 0x00606055, 0x005b005a, 0x00555060, 0x00511065, 0x004c806b, 0x0047d072, 0x00444078, 0x00400080, 0x003ca087, 0x0039408f, 0x0035e098, 0x0032e0a1, 0x003030aa, 0x002d80b4, 0x002ae0bf, 0x002880ca, 0x002640d6, 0x002410e3, 0x002220f0, 0x002020ff, 0x001e510e, 0x001ca11e, 0x001b012f, 0x00199140, 0x00182153, 0x0016c168, 0x0015817d, 0x00145193, 0x001321ab, 0x001211c5, 0x001111e0, 0x001021fc, 0x000f321a, 0x000e523a, 0x000d925c, 0x000cd27f, 0x000c12a5, 0x000b62cd, 0x000ac2f8, 0x000a2325, 0x00099355, 0x00091387, 0x000883bd, 0x000813f5, 0x0007a432, 0x00073471, 0x0006c4b5, 0x000664fc, 0x00061547, 0x0005b598, 0x000565ec, 0x00051646, 0x0004d6a5, 0x0004870a, 0x00044775, 0x000407e6, 0x0003d85e, 0x000398dd, 0x00036963, 0x000339f2, 0x00030a89, 0x0002db28 }; static const uint16_t auxgainidx_a0[] = { 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0002, 0x0014, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0002, 0x0014 }; static const uint32_t gainval_a0[] = { 0x00000008, 0x0000000e, 0x00000014, 0x0000001a, 0x000000fb, 0x00000004, 0x00000008, 0x0000000d, 0x00000001, 0x00000004, 0x00000007, 0x0000000a, 0x0000000d, 0x00000010, 0x00000012, 0x00000015, 0x00000000, 0x00000006, 0x0000000c, 0x00000000, 0x00000000, 0x00000000, 0x00000012, 0x00000000, 0x00000000, 0x00000000, 0x00000018, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x0000001e, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000003, 0x00000006, 0x00000009, 0x0000000c, 0x0000000f, 0x00000012, 0x00000015, 0x00000018, 0x0000001b, 0x0000001e, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x0000000f, 0x000000f7, 0x00000000, 0x00000000 }; static const uint16_t gain_a0[] = { 0x0000, 0x0002, 0x0004, 0x0006, 0x0007, 0x0008, 0x000a, 0x000b, 0x000c, 0x000e, 0x000f, 0x0010, 0x0012, 0x0013, 0x0014, 0x0016, 0x0017, 0x001a, 0x001b, 0x001f, 0x0020, 0x0024, 0x0030, 0x0034, 0x0037, 0x003b, 0x003f, 0x0040, 0x0044, 0x0057, 0x005b, 0x005f, 0x00d7, 0x00db, 0x00df, 0x0157, 0x015b, 0x015f, 0x0357, 0x035b, 0x035f, 0x075f, 0x0b5f, 0x0f5f, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000 }; KASSERT(mac->mac_phy.rev < 2, ("%s:%d: fail", __func__, __LINE__)); for (i = 0; i < 704; i++) bwn_tab_write(mac, BWN_TAB_4(7, i), 0); bwn_tab_write_multi(mac, BWN_TAB_1(2, 0), N(bwn_tab_sigsq_tbl), bwn_tab_sigsq_tbl); bwn_tab_write_multi(mac, BWN_TAB_2(1, 0), N(noisescale), noisescale); bwn_tab_write_multi(mac, BWN_TAB_4(11, 0), N(filterctl), filterctl); bwn_tab_write_multi(mac, BWN_TAB_4(12, 0), N(psctl), psctl); bwn_tab_write_multi(mac, BWN_TAB_4(13, 0), N(gainidx), gainidx); bwn_tab_write_multi(mac, BWN_TAB_2(14, 0), N(auxgainidx), auxgainidx); bwn_tab_write_multi(mac, BWN_TAB_2(15, 0), N(swctl), swctl); bwn_tab_write_multi(mac, BWN_TAB_1(16, 0), N(hf), hf); bwn_tab_write_multi(mac, BWN_TAB_4(17, 0), N(gainval), gainval); bwn_tab_write_multi(mac, BWN_TAB_2(18, 0), N(gain), gain); bwn_tab_write_multi(mac, BWN_TAB_1(6, 0), N(bwn_tab_pllfrac_tbl), bwn_tab_pllfrac_tbl); bwn_tab_write_multi(mac, BWN_TAB_2(0, 0), N(bwn_tabl_iqlocal_tbl), bwn_tabl_iqlocal_tbl); bwn_tab_write_multi(mac, BWN_TAB_4(9, 0), N(papdeps), papdeps); bwn_tab_write_multi(mac, BWN_TAB_4(10, 0), N(papdmult), papdmult); - if ((siba_get_chipid(sc->sc_dev) == 0x4325) && - (siba_get_chiprev(sc->sc_dev) == 0)) { + if (sc->sc_cid.chip_id == BHND_CHIPID_BCM4325 && + sc->sc_cid.chip_pkg == 0) { bwn_tab_write_multi(mac, BWN_TAB_4(13, 0), N(gainidx_a0), gainidx_a0); bwn_tab_write_multi(mac, BWN_TAB_2(14, 0), N(auxgainidx_a0), auxgainidx_a0); bwn_tab_write_multi(mac, BWN_TAB_4(17, 0), N(gainval_a0), gainval_a0); bwn_tab_write_multi(mac, BWN_TAB_2(18, 0), N(gain_a0), gain_a0); } } static void bwn_phy_lp_tblinit_txgain(struct bwn_mac *mac) { struct bwn_softc *sc = mac->mac_sc; struct ieee80211com *ic = &sc->sc_ic; static struct bwn_txgain_entry txgain_r2[] = { { 255, 255, 203, 0, 152 }, { 255, 255, 203, 0, 147 }, { 255, 255, 203, 0, 143 }, { 255, 255, 203, 0, 139 }, { 255, 255, 203, 0, 135 }, { 255, 255, 203, 0, 131 }, { 255, 255, 203, 0, 128 }, { 255, 255, 203, 0, 124 }, { 255, 255, 203, 0, 121 }, { 255, 255, 203, 0, 117 }, { 255, 255, 203, 0, 114 }, { 255, 255, 203, 0, 111 }, { 255, 255, 203, 0, 107 }, { 255, 255, 203, 0, 104 }, { 255, 255, 203, 0, 101 }, { 255, 255, 203, 0, 99 }, { 255, 255, 203, 0, 96 }, { 255, 255, 203, 0, 93 }, { 255, 255, 203, 0, 90 }, { 255, 255, 203, 0, 88 }, { 255, 255, 203, 0, 85 }, { 255, 255, 203, 0, 83 }, { 255, 255, 203, 0, 81 }, { 255, 255, 203, 0, 78 }, { 255, 255, 203, 0, 76 }, { 255, 255, 203, 0, 74 }, { 255, 255, 203, 0, 72 }, { 255, 255, 203, 0, 70 }, { 255, 255, 203, 0, 68 }, { 255, 255, 203, 0, 66 }, { 255, 255, 203, 0, 64 }, { 255, 255, 197, 0, 64 }, { 255, 255, 192, 0, 64 }, { 255, 255, 186, 0, 64 }, { 255, 255, 181, 0, 64 }, { 255, 255, 176, 0, 64 }, { 255, 255, 171, 0, 64 }, { 255, 255, 166, 0, 64 }, { 255, 255, 161, 0, 64 }, { 255, 255, 157, 0, 64 }, { 255, 255, 152, 0, 64 }, { 255, 255, 148, 0, 64 }, { 255, 255, 144, 0, 64 }, { 255, 255, 140, 0, 64 }, { 255, 255, 136, 0, 64 }, { 255, 255, 132, 0, 64 }, { 255, 255, 128, 0, 64 }, { 255, 255, 124, 0, 64 }, { 255, 255, 121, 0, 64 }, { 255, 255, 117, 0, 64 }, { 255, 255, 114, 0, 64 }, { 255, 255, 111, 0, 64 }, { 255, 255, 108, 0, 64 }, { 255, 255, 105, 0, 64 }, { 255, 255, 102, 0, 64 }, { 255, 255, 99, 0, 64 }, { 255, 255, 96, 0, 64 }, { 255, 255, 93, 0, 64 }, { 255, 255, 91, 0, 64 }, { 255, 255, 88, 0, 64 }, { 255, 255, 86, 0, 64 }, { 255, 255, 83, 0, 64 }, { 255, 255, 81, 0, 64 }, { 255, 255, 79, 0, 64 }, { 255, 255, 76, 0, 64 }, { 255, 255, 74, 0, 64 }, { 255, 255, 72, 0, 64 }, { 255, 255, 70, 0, 64 }, { 255, 255, 68, 0, 64 }, { 255, 255, 66, 0, 64 }, { 255, 255, 64, 0, 64 }, { 255, 248, 64, 0, 64 }, { 255, 248, 62, 0, 64 }, { 255, 241, 62, 0, 64 }, { 255, 241, 60, 0, 64 }, { 255, 234, 60, 0, 64 }, { 255, 234, 59, 0, 64 }, { 255, 227, 59, 0, 64 }, { 255, 227, 57, 0, 64 }, { 255, 221, 57, 0, 64 }, { 255, 221, 55, 0, 64 }, { 255, 215, 55, 0, 64 }, { 255, 215, 54, 0, 64 }, { 255, 208, 54, 0, 64 }, { 255, 208, 52, 0, 64 }, { 255, 203, 52, 0, 64 }, { 255, 203, 51, 0, 64 }, { 255, 197, 51, 0, 64 }, { 255, 197, 49, 0, 64 }, { 255, 191, 49, 0, 64 }, { 255, 191, 48, 0, 64 }, { 255, 186, 48, 0, 64 }, { 255, 186, 47, 0, 64 }, { 255, 181, 47, 0, 64 }, { 255, 181, 45, 0, 64 }, { 255, 175, 45, 0, 64 }, { 255, 175, 44, 0, 64 }, { 255, 170, 44, 0, 64 }, { 255, 170, 43, 0, 64 }, { 255, 166, 43, 0, 64 }, { 255, 166, 42, 0, 64 }, { 255, 161, 42, 0, 64 }, { 255, 161, 40, 0, 64 }, { 255, 156, 40, 0, 64 }, { 255, 156, 39, 0, 64 }, { 255, 152, 39, 0, 64 }, { 255, 152, 38, 0, 64 }, { 255, 148, 38, 0, 64 }, { 255, 148, 37, 0, 64 }, { 255, 143, 37, 0, 64 }, { 255, 143, 36, 0, 64 }, { 255, 139, 36, 0, 64 }, { 255, 139, 35, 0, 64 }, { 255, 135, 35, 0, 64 }, { 255, 135, 34, 0, 64 }, { 255, 132, 34, 0, 64 }, { 255, 132, 33, 0, 64 }, { 255, 128, 33, 0, 64 }, { 255, 128, 32, 0, 64 }, { 255, 124, 32, 0, 64 }, { 255, 124, 31, 0, 64 }, { 255, 121, 31, 0, 64 }, { 255, 121, 30, 0, 64 }, { 255, 117, 30, 0, 64 }, { 255, 117, 29, 0, 64 }, { 255, 114, 29, 0, 64 }, { 255, 114, 29, 0, 64 }, { 255, 111, 29, 0, 64 }, }; static struct bwn_txgain_entry txgain_2ghz_r2[] = { { 7, 99, 255, 0, 64 }, { 7, 96, 255, 0, 64 }, { 7, 93, 255, 0, 64 }, { 7, 90, 255, 0, 64 }, { 7, 88, 255, 0, 64 }, { 7, 85, 255, 0, 64 }, { 7, 83, 255, 0, 64 }, { 7, 81, 255, 0, 64 }, { 7, 78, 255, 0, 64 }, { 7, 76, 255, 0, 64 }, { 7, 74, 255, 0, 64 }, { 7, 72, 255, 0, 64 }, { 7, 70, 255, 0, 64 }, { 7, 68, 255, 0, 64 }, { 7, 66, 255, 0, 64 }, { 7, 64, 255, 0, 64 }, { 7, 64, 255, 0, 64 }, { 7, 62, 255, 0, 64 }, { 7, 62, 248, 0, 64 }, { 7, 60, 248, 0, 64 }, { 7, 60, 241, 0, 64 }, { 7, 59, 241, 0, 64 }, { 7, 59, 234, 0, 64 }, { 7, 57, 234, 0, 64 }, { 7, 57, 227, 0, 64 }, { 7, 55, 227, 0, 64 }, { 7, 55, 221, 0, 64 }, { 7, 54, 221, 0, 64 }, { 7, 54, 215, 0, 64 }, { 7, 52, 215, 0, 64 }, { 7, 52, 208, 0, 64 }, { 7, 51, 208, 0, 64 }, { 7, 51, 203, 0, 64 }, { 7, 49, 203, 0, 64 }, { 7, 49, 197, 0, 64 }, { 7, 48, 197, 0, 64 }, { 7, 48, 191, 0, 64 }, { 7, 47, 191, 0, 64 }, { 7, 47, 186, 0, 64 }, { 7, 45, 186, 0, 64 }, { 7, 45, 181, 0, 64 }, { 7, 44, 181, 0, 64 }, { 7, 44, 175, 0, 64 }, { 7, 43, 175, 0, 64 }, { 7, 43, 170, 0, 64 }, { 7, 42, 170, 0, 64 }, { 7, 42, 166, 0, 64 }, { 7, 40, 166, 0, 64 }, { 7, 40, 161, 0, 64 }, { 7, 39, 161, 0, 64 }, { 7, 39, 156, 0, 64 }, { 7, 38, 156, 0, 64 }, { 7, 38, 152, 0, 64 }, { 7, 37, 152, 0, 64 }, { 7, 37, 148, 0, 64 }, { 7, 36, 148, 0, 64 }, { 7, 36, 143, 0, 64 }, { 7, 35, 143, 0, 64 }, { 7, 35, 139, 0, 64 }, { 7, 34, 139, 0, 64 }, { 7, 34, 135, 0, 64 }, { 7, 33, 135, 0, 64 }, { 7, 33, 132, 0, 64 }, { 7, 32, 132, 0, 64 }, { 7, 32, 128, 0, 64 }, { 7, 31, 128, 0, 64 }, { 7, 31, 124, 0, 64 }, { 7, 30, 124, 0, 64 }, { 7, 30, 121, 0, 64 }, { 7, 29, 121, 0, 64 }, { 7, 29, 117, 0, 64 }, { 7, 29, 117, 0, 64 }, { 7, 29, 114, 0, 64 }, { 7, 28, 114, 0, 64 }, { 7, 28, 111, 0, 64 }, { 7, 27, 111, 0, 64 }, { 7, 27, 108, 0, 64 }, { 7, 26, 108, 0, 64 }, { 7, 26, 104, 0, 64 }, { 7, 25, 104, 0, 64 }, { 7, 25, 102, 0, 64 }, { 7, 25, 102, 0, 64 }, { 7, 25, 99, 0, 64 }, { 7, 24, 99, 0, 64 }, { 7, 24, 96, 0, 64 }, { 7, 23, 96, 0, 64 }, { 7, 23, 93, 0, 64 }, { 7, 23, 93, 0, 64 }, { 7, 23, 90, 0, 64 }, { 7, 22, 90, 0, 64 }, { 7, 22, 88, 0, 64 }, { 7, 21, 88, 0, 64 }, { 7, 21, 85, 0, 64 }, { 7, 21, 85, 0, 64 }, { 7, 21, 83, 0, 64 }, { 7, 20, 83, 0, 64 }, { 7, 20, 81, 0, 64 }, { 7, 20, 81, 0, 64 }, { 7, 20, 78, 0, 64 }, { 7, 19, 78, 0, 64 }, { 7, 19, 76, 0, 64 }, { 7, 19, 76, 0, 64 }, { 7, 19, 74, 0, 64 }, { 7, 18, 74, 0, 64 }, { 7, 18, 72, 0, 64 }, { 7, 18, 72, 0, 64 }, { 7, 18, 70, 0, 64 }, { 7, 17, 70, 0, 64 }, { 7, 17, 68, 0, 64 }, { 7, 17, 68, 0, 64 }, { 7, 17, 66, 0, 64 }, { 7, 16, 66, 0, 64 }, { 7, 16, 64, 0, 64 }, { 7, 16, 64, 0, 64 }, { 7, 16, 62, 0, 64 }, { 7, 15, 62, 0, 64 }, { 7, 15, 60, 0, 64 }, { 7, 15, 60, 0, 64 }, { 7, 15, 59, 0, 64 }, { 7, 14, 59, 0, 64 }, { 7, 14, 57, 0, 64 }, { 7, 14, 57, 0, 64 }, { 7, 14, 55, 0, 64 }, { 7, 14, 55, 0, 64 }, { 7, 14, 54, 0, 64 }, { 7, 13, 54, 0, 64 }, { 7, 13, 52, 0, 64 }, { 7, 13, 52, 0, 64 }, }; static struct bwn_txgain_entry txgain_5ghz_r2[] = { { 255, 255, 255, 0, 152 }, { 255, 255, 255, 0, 147 }, { 255, 255, 255, 0, 143 }, { 255, 255, 255, 0, 139 }, { 255, 255, 255, 0, 135 }, { 255, 255, 255, 0, 131 }, { 255, 255, 255, 0, 128 }, { 255, 255, 255, 0, 124 }, { 255, 255, 255, 0, 121 }, { 255, 255, 255, 0, 117 }, { 255, 255, 255, 0, 114 }, { 255, 255, 255, 0, 111 }, { 255, 255, 255, 0, 107 }, { 255, 255, 255, 0, 104 }, { 255, 255, 255, 0, 101 }, { 255, 255, 255, 0, 99 }, { 255, 255, 255, 0, 96 }, { 255, 255, 255, 0, 93 }, { 255, 255, 255, 0, 90 }, { 255, 255, 255, 0, 88 }, { 255, 255, 255, 0, 85 }, { 255, 255, 255, 0, 83 }, { 255, 255, 255, 0, 81 }, { 255, 255, 255, 0, 78 }, { 255, 255, 255, 0, 76 }, { 255, 255, 255, 0, 74 }, { 255, 255, 255, 0, 72 }, { 255, 255, 255, 0, 70 }, { 255, 255, 255, 0, 68 }, { 255, 255, 255, 0, 66 }, { 255, 255, 255, 0, 64 }, { 255, 255, 248, 0, 64 }, { 255, 255, 241, 0, 64 }, { 255, 255, 234, 0, 64 }, { 255, 255, 227, 0, 64 }, { 255, 255, 221, 0, 64 }, { 255, 255, 215, 0, 64 }, { 255, 255, 208, 0, 64 }, { 255, 255, 203, 0, 64 }, { 255, 255, 197, 0, 64 }, { 255, 255, 191, 0, 64 }, { 255, 255, 186, 0, 64 }, { 255, 255, 181, 0, 64 }, { 255, 255, 175, 0, 64 }, { 255, 255, 170, 0, 64 }, { 255, 255, 166, 0, 64 }, { 255, 255, 161, 0, 64 }, { 255, 255, 156, 0, 64 }, { 255, 255, 152, 0, 64 }, { 255, 255, 148, 0, 64 }, { 255, 255, 143, 0, 64 }, { 255, 255, 139, 0, 64 }, { 255, 255, 135, 0, 64 }, { 255, 255, 132, 0, 64 }, { 255, 255, 128, 0, 64 }, { 255, 255, 124, 0, 64 }, { 255, 255, 121, 0, 64 }, { 255, 255, 117, 0, 64 }, { 255, 255, 114, 0, 64 }, { 255, 255, 111, 0, 64 }, { 255, 255, 108, 0, 64 }, { 255, 255, 104, 0, 64 }, { 255, 255, 102, 0, 64 }, { 255, 255, 99, 0, 64 }, { 255, 255, 96, 0, 64 }, { 255, 255, 93, 0, 64 }, { 255, 255, 90, 0, 64 }, { 255, 255, 88, 0, 64 }, { 255, 255, 85, 0, 64 }, { 255, 255, 83, 0, 64 }, { 255, 255, 81, 0, 64 }, { 255, 255, 78, 0, 64 }, { 255, 255, 76, 0, 64 }, { 255, 255, 74, 0, 64 }, { 255, 255, 72, 0, 64 }, { 255, 255, 70, 0, 64 }, { 255, 255, 68, 0, 64 }, { 255, 255, 66, 0, 64 }, { 255, 255, 64, 0, 64 }, { 255, 255, 64, 0, 64 }, { 255, 255, 62, 0, 64 }, { 255, 248, 62, 0, 64 }, { 255, 248, 60, 0, 64 }, { 255, 241, 60, 0, 64 }, { 255, 241, 59, 0, 64 }, { 255, 234, 59, 0, 64 }, { 255, 234, 57, 0, 64 }, { 255, 227, 57, 0, 64 }, { 255, 227, 55, 0, 64 }, { 255, 221, 55, 0, 64 }, { 255, 221, 54, 0, 64 }, { 255, 215, 54, 0, 64 }, { 255, 215, 52, 0, 64 }, { 255, 208, 52, 0, 64 }, { 255, 208, 51, 0, 64 }, { 255, 203, 51, 0, 64 }, { 255, 203, 49, 0, 64 }, { 255, 197, 49, 0, 64 }, { 255, 197, 48, 0, 64 }, { 255, 191, 48, 0, 64 }, { 255, 191, 47, 0, 64 }, { 255, 186, 47, 0, 64 }, { 255, 186, 45, 0, 64 }, { 255, 181, 45, 0, 64 }, { 255, 181, 44, 0, 64 }, { 255, 175, 44, 0, 64 }, { 255, 175, 43, 0, 64 }, { 255, 170, 43, 0, 64 }, { 255, 170, 42, 0, 64 }, { 255, 166, 42, 0, 64 }, { 255, 166, 40, 0, 64 }, { 255, 161, 40, 0, 64 }, { 255, 161, 39, 0, 64 }, { 255, 156, 39, 0, 64 }, { 255, 156, 38, 0, 64 }, { 255, 152, 38, 0, 64 }, { 255, 152, 37, 0, 64 }, { 255, 148, 37, 0, 64 }, { 255, 148, 36, 0, 64 }, { 255, 143, 36, 0, 64 }, { 255, 143, 35, 0, 64 }, { 255, 139, 35, 0, 64 }, { 255, 139, 34, 0, 64 }, { 255, 135, 34, 0, 64 }, { 255, 135, 33, 0, 64 }, { 255, 132, 33, 0, 64 }, { 255, 132, 32, 0, 64 }, { 255, 128, 32, 0, 64 } }; static struct bwn_txgain_entry txgain_r0[] = { { 7, 15, 14, 0, 152 }, { 7, 15, 14, 0, 147 }, { 7, 15, 14, 0, 143 }, { 7, 15, 14, 0, 139 }, { 7, 15, 14, 0, 135 }, { 7, 15, 14, 0, 131 }, { 7, 15, 14, 0, 128 }, { 7, 15, 14, 0, 124 }, { 7, 15, 14, 0, 121 }, { 7, 15, 14, 0, 117 }, { 7, 15, 14, 0, 114 }, { 7, 15, 14, 0, 111 }, { 7, 15, 14, 0, 107 }, { 7, 15, 14, 0, 104 }, { 7, 15, 14, 0, 101 }, { 7, 15, 14, 0, 99 }, { 7, 15, 14, 0, 96 }, { 7, 15, 14, 0, 93 }, { 7, 15, 14, 0, 90 }, { 7, 15, 14, 0, 88 }, { 7, 15, 14, 0, 85 }, { 7, 15, 14, 0, 83 }, { 7, 15, 14, 0, 81 }, { 7, 15, 14, 0, 78 }, { 7, 15, 14, 0, 76 }, { 7, 15, 14, 0, 74 }, { 7, 15, 14, 0, 72 }, { 7, 15, 14, 0, 70 }, { 7, 15, 14, 0, 68 }, { 7, 15, 14, 0, 66 }, { 7, 15, 14, 0, 64 }, { 7, 15, 14, 0, 62 }, { 7, 15, 14, 0, 60 }, { 7, 15, 14, 0, 59 }, { 7, 15, 14, 0, 57 }, { 7, 15, 13, 0, 72 }, { 7, 15, 13, 0, 70 }, { 7, 15, 13, 0, 68 }, { 7, 15, 13, 0, 66 }, { 7, 15, 13, 0, 64 }, { 7, 15, 13, 0, 62 }, { 7, 15, 13, 0, 60 }, { 7, 15, 13, 0, 59 }, { 7, 15, 13, 0, 57 }, { 7, 15, 12, 0, 71 }, { 7, 15, 12, 0, 69 }, { 7, 15, 12, 0, 67 }, { 7, 15, 12, 0, 65 }, { 7, 15, 12, 0, 63 }, { 7, 15, 12, 0, 62 }, { 7, 15, 12, 0, 60 }, { 7, 15, 12, 0, 58 }, { 7, 15, 12, 0, 57 }, { 7, 15, 11, 0, 70 }, { 7, 15, 11, 0, 68 }, { 7, 15, 11, 0, 66 }, { 7, 15, 11, 0, 65 }, { 7, 15, 11, 0, 63 }, { 7, 15, 11, 0, 61 }, { 7, 15, 11, 0, 59 }, { 7, 15, 11, 0, 58 }, { 7, 15, 10, 0, 71 }, { 7, 15, 10, 0, 69 }, { 7, 15, 10, 0, 67 }, { 7, 15, 10, 0, 65 }, { 7, 15, 10, 0, 63 }, { 7, 15, 10, 0, 61 }, { 7, 15, 10, 0, 60 }, { 7, 15, 10, 0, 58 }, { 7, 15, 10, 0, 56 }, { 7, 15, 9, 0, 70 }, { 7, 15, 9, 0, 68 }, { 7, 15, 9, 0, 66 }, { 7, 15, 9, 0, 64 }, { 7, 15, 9, 0, 62 }, { 7, 15, 9, 0, 60 }, { 7, 15, 9, 0, 59 }, { 7, 14, 9, 0, 72 }, { 7, 14, 9, 0, 70 }, { 7, 14, 9, 0, 68 }, { 7, 14, 9, 0, 66 }, { 7, 14, 9, 0, 64 }, { 7, 14, 9, 0, 62 }, { 7, 14, 9, 0, 60 }, { 7, 14, 9, 0, 59 }, { 7, 13, 9, 0, 72 }, { 7, 13, 9, 0, 70 }, { 7, 13, 9, 0, 68 }, { 7, 13, 9, 0, 66 }, { 7, 13, 9, 0, 64 }, { 7, 13, 9, 0, 63 }, { 7, 13, 9, 0, 61 }, { 7, 13, 9, 0, 59 }, { 7, 13, 9, 0, 57 }, { 7, 13, 8, 0, 72 }, { 7, 13, 8, 0, 70 }, { 7, 13, 8, 0, 68 }, { 7, 13, 8, 0, 66 }, { 7, 13, 8, 0, 64 }, { 7, 13, 8, 0, 62 }, { 7, 13, 8, 0, 60 }, { 7, 13, 8, 0, 59 }, { 7, 12, 8, 0, 72 }, { 7, 12, 8, 0, 70 }, { 7, 12, 8, 0, 68 }, { 7, 12, 8, 0, 66 }, { 7, 12, 8, 0, 64 }, { 7, 12, 8, 0, 62 }, { 7, 12, 8, 0, 61 }, { 7, 12, 8, 0, 59 }, { 7, 12, 7, 0, 73 }, { 7, 12, 7, 0, 71 }, { 7, 12, 7, 0, 69 }, { 7, 12, 7, 0, 67 }, { 7, 12, 7, 0, 65 }, { 7, 12, 7, 0, 63 }, { 7, 12, 7, 0, 61 }, { 7, 12, 7, 0, 59 }, { 7, 11, 7, 0, 72 }, { 7, 11, 7, 0, 70 }, { 7, 11, 7, 0, 68 }, { 7, 11, 7, 0, 66 }, { 7, 11, 7, 0, 65 }, { 7, 11, 7, 0, 63 }, { 7, 11, 7, 0, 61 }, { 7, 11, 7, 0, 59 }, { 7, 11, 6, 0, 73 }, { 7, 11, 6, 0, 71 } }; static struct bwn_txgain_entry txgain_2ghz_r0[] = { { 4, 15, 9, 0, 64 }, { 4, 15, 9, 0, 62 }, { 4, 15, 9, 0, 60 }, { 4, 15, 9, 0, 59 }, { 4, 14, 9, 0, 72 }, { 4, 14, 9, 0, 70 }, { 4, 14, 9, 0, 68 }, { 4, 14, 9, 0, 66 }, { 4, 14, 9, 0, 64 }, { 4, 14, 9, 0, 62 }, { 4, 14, 9, 0, 60 }, { 4, 14, 9, 0, 59 }, { 4, 13, 9, 0, 72 }, { 4, 13, 9, 0, 70 }, { 4, 13, 9, 0, 68 }, { 4, 13, 9, 0, 66 }, { 4, 13, 9, 0, 64 }, { 4, 13, 9, 0, 63 }, { 4, 13, 9, 0, 61 }, { 4, 13, 9, 0, 59 }, { 4, 13, 9, 0, 57 }, { 4, 13, 8, 0, 72 }, { 4, 13, 8, 0, 70 }, { 4, 13, 8, 0, 68 }, { 4, 13, 8, 0, 66 }, { 4, 13, 8, 0, 64 }, { 4, 13, 8, 0, 62 }, { 4, 13, 8, 0, 60 }, { 4, 13, 8, 0, 59 }, { 4, 12, 8, 0, 72 }, { 4, 12, 8, 0, 70 }, { 4, 12, 8, 0, 68 }, { 4, 12, 8, 0, 66 }, { 4, 12, 8, 0, 64 }, { 4, 12, 8, 0, 62 }, { 4, 12, 8, 0, 61 }, { 4, 12, 8, 0, 59 }, { 4, 12, 7, 0, 73 }, { 4, 12, 7, 0, 71 }, { 4, 12, 7, 0, 69 }, { 4, 12, 7, 0, 67 }, { 4, 12, 7, 0, 65 }, { 4, 12, 7, 0, 63 }, { 4, 12, 7, 0, 61 }, { 4, 12, 7, 0, 59 }, { 4, 11, 7, 0, 72 }, { 4, 11, 7, 0, 70 }, { 4, 11, 7, 0, 68 }, { 4, 11, 7, 0, 66 }, { 4, 11, 7, 0, 65 }, { 4, 11, 7, 0, 63 }, { 4, 11, 7, 0, 61 }, { 4, 11, 7, 0, 59 }, { 4, 11, 6, 0, 73 }, { 4, 11, 6, 0, 71 }, { 4, 11, 6, 0, 69 }, { 4, 11, 6, 0, 67 }, { 4, 11, 6, 0, 65 }, { 4, 11, 6, 0, 63 }, { 4, 11, 6, 0, 61 }, { 4, 11, 6, 0, 60 }, { 4, 10, 6, 0, 72 }, { 4, 10, 6, 0, 70 }, { 4, 10, 6, 0, 68 }, { 4, 10, 6, 0, 66 }, { 4, 10, 6, 0, 64 }, { 4, 10, 6, 0, 62 }, { 4, 10, 6, 0, 60 }, { 4, 10, 6, 0, 59 }, { 4, 10, 5, 0, 72 }, { 4, 10, 5, 0, 70 }, { 4, 10, 5, 0, 68 }, { 4, 10, 5, 0, 66 }, { 4, 10, 5, 0, 64 }, { 4, 10, 5, 0, 62 }, { 4, 10, 5, 0, 60 }, { 4, 10, 5, 0, 59 }, { 4, 9, 5, 0, 70 }, { 4, 9, 5, 0, 68 }, { 4, 9, 5, 0, 66 }, { 4, 9, 5, 0, 64 }, { 4, 9, 5, 0, 63 }, { 4, 9, 5, 0, 61 }, { 4, 9, 5, 0, 59 }, { 4, 9, 4, 0, 71 }, { 4, 9, 4, 0, 69 }, { 4, 9, 4, 0, 67 }, { 4, 9, 4, 0, 65 }, { 4, 9, 4, 0, 63 }, { 4, 9, 4, 0, 62 }, { 4, 9, 4, 0, 60 }, { 4, 9, 4, 0, 58 }, { 4, 8, 4, 0, 70 }, { 4, 8, 4, 0, 68 }, { 4, 8, 4, 0, 66 }, { 4, 8, 4, 0, 65 }, { 4, 8, 4, 0, 63 }, { 4, 8, 4, 0, 61 }, { 4, 8, 4, 0, 59 }, { 4, 7, 4, 0, 68 }, { 4, 7, 4, 0, 66 }, { 4, 7, 4, 0, 64 }, { 4, 7, 4, 0, 62 }, { 4, 7, 4, 0, 61 }, { 4, 7, 4, 0, 59 }, { 4, 7, 3, 0, 67 }, { 4, 7, 3, 0, 65 }, { 4, 7, 3, 0, 63 }, { 4, 7, 3, 0, 62 }, { 4, 7, 3, 0, 60 }, { 4, 6, 3, 0, 65 }, { 4, 6, 3, 0, 63 }, { 4, 6, 3, 0, 61 }, { 4, 6, 3, 0, 60 }, { 4, 6, 3, 0, 58 }, { 4, 5, 3, 0, 68 }, { 4, 5, 3, 0, 66 }, { 4, 5, 3, 0, 64 }, { 4, 5, 3, 0, 62 }, { 4, 5, 3, 0, 60 }, { 4, 5, 3, 0, 59 }, { 4, 5, 3, 0, 57 }, { 4, 4, 2, 0, 83 }, { 4, 4, 2, 0, 81 }, { 4, 4, 2, 0, 78 }, { 4, 4, 2, 0, 76 }, { 4, 4, 2, 0, 74 }, { 4, 4, 2, 0, 72 } }; static struct bwn_txgain_entry txgain_5ghz_r0[] = { { 7, 15, 15, 0, 99 }, { 7, 15, 15, 0, 96 }, { 7, 15, 15, 0, 93 }, { 7, 15, 15, 0, 90 }, { 7, 15, 15, 0, 88 }, { 7, 15, 15, 0, 85 }, { 7, 15, 15, 0, 83 }, { 7, 15, 15, 0, 81 }, { 7, 15, 15, 0, 78 }, { 7, 15, 15, 0, 76 }, { 7, 15, 15, 0, 74 }, { 7, 15, 15, 0, 72 }, { 7, 15, 15, 0, 70 }, { 7, 15, 15, 0, 68 }, { 7, 15, 15, 0, 66 }, { 7, 15, 15, 0, 64 }, { 7, 15, 15, 0, 62 }, { 7, 15, 15, 0, 60 }, { 7, 15, 15, 0, 59 }, { 7, 15, 15, 0, 57 }, { 7, 15, 15, 0, 55 }, { 7, 15, 14, 0, 72 }, { 7, 15, 14, 0, 70 }, { 7, 15, 14, 0, 68 }, { 7, 15, 14, 0, 66 }, { 7, 15, 14, 0, 64 }, { 7, 15, 14, 0, 62 }, { 7, 15, 14, 0, 60 }, { 7, 15, 14, 0, 58 }, { 7, 15, 14, 0, 56 }, { 7, 15, 14, 0, 55 }, { 7, 15, 13, 0, 71 }, { 7, 15, 13, 0, 69 }, { 7, 15, 13, 0, 67 }, { 7, 15, 13, 0, 65 }, { 7, 15, 13, 0, 63 }, { 7, 15, 13, 0, 62 }, { 7, 15, 13, 0, 60 }, { 7, 15, 13, 0, 58 }, { 7, 15, 13, 0, 56 }, { 7, 15, 12, 0, 72 }, { 7, 15, 12, 0, 70 }, { 7, 15, 12, 0, 68 }, { 7, 15, 12, 0, 66 }, { 7, 15, 12, 0, 64 }, { 7, 15, 12, 0, 62 }, { 7, 15, 12, 0, 60 }, { 7, 15, 12, 0, 59 }, { 7, 15, 12, 0, 57 }, { 7, 15, 11, 0, 73 }, { 7, 15, 11, 0, 71 }, { 7, 15, 11, 0, 69 }, { 7, 15, 11, 0, 67 }, { 7, 15, 11, 0, 65 }, { 7, 15, 11, 0, 63 }, { 7, 15, 11, 0, 61 }, { 7, 15, 11, 0, 60 }, { 7, 15, 11, 0, 58 }, { 7, 15, 10, 0, 71 }, { 7, 15, 10, 0, 69 }, { 7, 15, 10, 0, 67 }, { 7, 15, 10, 0, 65 }, { 7, 15, 10, 0, 63 }, { 7, 15, 10, 0, 61 }, { 7, 15, 10, 0, 60 }, { 7, 15, 10, 0, 58 }, { 7, 15, 9, 0, 70 }, { 7, 15, 9, 0, 68 }, { 7, 15, 9, 0, 66 }, { 7, 15, 9, 0, 64 }, { 7, 15, 9, 0, 62 }, { 7, 15, 9, 0, 61 }, { 7, 15, 9, 0, 59 }, { 7, 15, 9, 0, 57 }, { 7, 15, 9, 0, 56 }, { 7, 14, 9, 0, 68 }, { 7, 14, 9, 0, 66 }, { 7, 14, 9, 0, 65 }, { 7, 14, 9, 0, 63 }, { 7, 14, 9, 0, 61 }, { 7, 14, 9, 0, 59 }, { 7, 14, 9, 0, 58 }, { 7, 13, 9, 0, 70 }, { 7, 13, 9, 0, 68 }, { 7, 13, 9, 0, 66 }, { 7, 13, 9, 0, 64 }, { 7, 13, 9, 0, 63 }, { 7, 13, 9, 0, 61 }, { 7, 13, 9, 0, 59 }, { 7, 13, 9, 0, 57 }, { 7, 13, 8, 0, 70 }, { 7, 13, 8, 0, 68 }, { 7, 13, 8, 0, 66 }, { 7, 13, 8, 0, 64 }, { 7, 13, 8, 0, 62 }, { 7, 13, 8, 0, 60 }, { 7, 13, 8, 0, 59 }, { 7, 13, 8, 0, 57 }, { 7, 12, 8, 0, 70 }, { 7, 12, 8, 0, 68 }, { 7, 12, 8, 0, 66 }, { 7, 12, 8, 0, 64 }, { 7, 12, 8, 0, 62 }, { 7, 12, 8, 0, 61 }, { 7, 12, 8, 0, 59 }, { 7, 12, 8, 0, 57 }, { 7, 12, 7, 0, 70 }, { 7, 12, 7, 0, 68 }, { 7, 12, 7, 0, 66 }, { 7, 12, 7, 0, 64 }, { 7, 12, 7, 0, 62 }, { 7, 12, 7, 0, 61 }, { 7, 12, 7, 0, 59 }, { 7, 12, 7, 0, 57 }, { 7, 11, 7, 0, 70 }, { 7, 11, 7, 0, 68 }, { 7, 11, 7, 0, 66 }, { 7, 11, 7, 0, 64 }, { 7, 11, 7, 0, 62 }, { 7, 11, 7, 0, 61 }, { 7, 11, 7, 0, 59 }, { 7, 11, 7, 0, 57 }, { 7, 11, 6, 0, 69 }, { 7, 11, 6, 0, 67 }, { 7, 11, 6, 0, 65 }, { 7, 11, 6, 0, 63 }, { 7, 11, 6, 0, 62 }, { 7, 11, 6, 0, 60 } }; static struct bwn_txgain_entry txgain_r1[] = { { 7, 15, 14, 0, 152 }, { 7, 15, 14, 0, 147 }, { 7, 15, 14, 0, 143 }, { 7, 15, 14, 0, 139 }, { 7, 15, 14, 0, 135 }, { 7, 15, 14, 0, 131 }, { 7, 15, 14, 0, 128 }, { 7, 15, 14, 0, 124 }, { 7, 15, 14, 0, 121 }, { 7, 15, 14, 0, 117 }, { 7, 15, 14, 0, 114 }, { 7, 15, 14, 0, 111 }, { 7, 15, 14, 0, 107 }, { 7, 15, 14, 0, 104 }, { 7, 15, 14, 0, 101 }, { 7, 15, 14, 0, 99 }, { 7, 15, 14, 0, 96 }, { 7, 15, 14, 0, 93 }, { 7, 15, 14, 0, 90 }, { 7, 15, 14, 0, 88 }, { 7, 15, 14, 0, 85 }, { 7, 15, 14, 0, 83 }, { 7, 15, 14, 0, 81 }, { 7, 15, 14, 0, 78 }, { 7, 15, 14, 0, 76 }, { 7, 15, 14, 0, 74 }, { 7, 15, 14, 0, 72 }, { 7, 15, 14, 0, 70 }, { 7, 15, 14, 0, 68 }, { 7, 15, 14, 0, 66 }, { 7, 15, 14, 0, 64 }, { 7, 15, 14, 0, 62 }, { 7, 15, 14, 0, 60 }, { 7, 15, 14, 0, 59 }, { 7, 15, 14, 0, 57 }, { 7, 15, 13, 0, 72 }, { 7, 15, 13, 0, 70 }, { 7, 15, 14, 0, 68 }, { 7, 15, 14, 0, 66 }, { 7, 15, 14, 0, 64 }, { 7, 15, 14, 0, 62 }, { 7, 15, 14, 0, 60 }, { 7, 15, 14, 0, 59 }, { 7, 15, 14, 0, 57 }, { 7, 15, 13, 0, 72 }, { 7, 15, 13, 0, 70 }, { 7, 15, 13, 0, 68 }, { 7, 15, 13, 0, 66 }, { 7, 15, 13, 0, 64 }, { 7, 15, 13, 0, 62 }, { 7, 15, 13, 0, 60 }, { 7, 15, 13, 0, 59 }, { 7, 15, 13, 0, 57 }, { 7, 15, 12, 0, 71 }, { 7, 15, 12, 0, 69 }, { 7, 15, 12, 0, 67 }, { 7, 15, 12, 0, 65 }, { 7, 15, 12, 0, 63 }, { 7, 15, 12, 0, 62 }, { 7, 15, 12, 0, 60 }, { 7, 15, 12, 0, 58 }, { 7, 15, 12, 0, 57 }, { 7, 15, 11, 0, 70 }, { 7, 15, 11, 0, 68 }, { 7, 15, 11, 0, 66 }, { 7, 15, 11, 0, 65 }, { 7, 15, 11, 0, 63 }, { 7, 15, 11, 0, 61 }, { 7, 15, 11, 0, 59 }, { 7, 15, 11, 0, 58 }, { 7, 15, 10, 0, 71 }, { 7, 15, 10, 0, 69 }, { 7, 15, 10, 0, 67 }, { 7, 15, 10, 0, 65 }, { 7, 15, 10, 0, 63 }, { 7, 15, 10, 0, 61 }, { 7, 15, 10, 0, 60 }, { 7, 15, 10, 0, 58 }, { 7, 15, 10, 0, 56 }, { 7, 15, 9, 0, 70 }, { 7, 15, 9, 0, 68 }, { 7, 15, 9, 0, 66 }, { 7, 15, 9, 0, 64 }, { 7, 15, 9, 0, 62 }, { 7, 15, 9, 0, 60 }, { 7, 15, 9, 0, 59 }, { 7, 14, 9, 0, 72 }, { 7, 14, 9, 0, 70 }, { 7, 14, 9, 0, 68 }, { 7, 14, 9, 0, 66 }, { 7, 14, 9, 0, 64 }, { 7, 14, 9, 0, 62 }, { 7, 14, 9, 0, 60 }, { 7, 14, 9, 0, 59 }, { 7, 13, 9, 0, 72 }, { 7, 13, 9, 0, 70 }, { 7, 13, 9, 0, 68 }, { 7, 13, 9, 0, 66 }, { 7, 13, 9, 0, 64 }, { 7, 13, 9, 0, 63 }, { 7, 13, 9, 0, 61 }, { 7, 13, 9, 0, 59 }, { 7, 13, 9, 0, 57 }, { 7, 13, 8, 0, 72 }, { 7, 13, 8, 0, 70 }, { 7, 13, 8, 0, 68 }, { 7, 13, 8, 0, 66 }, { 7, 13, 8, 0, 64 }, { 7, 13, 8, 0, 62 }, { 7, 13, 8, 0, 60 }, { 7, 13, 8, 0, 59 }, { 7, 12, 8, 0, 72 }, { 7, 12, 8, 0, 70 }, { 7, 12, 8, 0, 68 }, { 7, 12, 8, 0, 66 }, { 7, 12, 8, 0, 64 }, { 7, 12, 8, 0, 62 }, { 7, 12, 8, 0, 61 }, { 7, 12, 8, 0, 59 }, { 7, 12, 7, 0, 73 }, { 7, 12, 7, 0, 71 }, { 7, 12, 7, 0, 69 }, { 7, 12, 7, 0, 67 }, { 7, 12, 7, 0, 65 }, { 7, 12, 7, 0, 63 }, { 7, 12, 7, 0, 61 }, { 7, 12, 7, 0, 59 }, { 7, 11, 7, 0, 72 }, { 7, 11, 7, 0, 70 }, { 7, 11, 7, 0, 68 }, { 7, 11, 7, 0, 66 }, { 7, 11, 7, 0, 65 }, { 7, 11, 7, 0, 63 }, { 7, 11, 7, 0, 61 }, { 7, 11, 7, 0, 59 }, { 7, 11, 6, 0, 73 }, { 7, 11, 6, 0, 71 } }; static struct bwn_txgain_entry txgain_2ghz_r1[] = { { 4, 15, 15, 0, 90 }, { 4, 15, 15, 0, 88 }, { 4, 15, 15, 0, 85 }, { 4, 15, 15, 0, 83 }, { 4, 15, 15, 0, 81 }, { 4, 15, 15, 0, 78 }, { 4, 15, 15, 0, 76 }, { 4, 15, 15, 0, 74 }, { 4, 15, 15, 0, 72 }, { 4, 15, 15, 0, 70 }, { 4, 15, 15, 0, 68 }, { 4, 15, 15, 0, 66 }, { 4, 15, 15, 0, 64 }, { 4, 15, 15, 0, 62 }, { 4, 15, 15, 0, 60 }, { 4, 15, 15, 0, 59 }, { 4, 15, 14, 0, 72 }, { 4, 15, 14, 0, 70 }, { 4, 15, 14, 0, 68 }, { 4, 15, 14, 0, 66 }, { 4, 15, 14, 0, 64 }, { 4, 15, 14, 0, 62 }, { 4, 15, 14, 0, 60 }, { 4, 15, 14, 0, 59 }, { 4, 15, 13, 0, 72 }, { 4, 15, 13, 0, 70 }, { 4, 15, 13, 0, 68 }, { 4, 15, 13, 0, 66 }, { 4, 15, 13, 0, 64 }, { 4, 15, 13, 0, 62 }, { 4, 15, 13, 0, 60 }, { 4, 15, 13, 0, 59 }, { 4, 15, 12, 0, 72 }, { 4, 15, 12, 0, 70 }, { 4, 15, 12, 0, 68 }, { 4, 15, 12, 0, 66 }, { 4, 15, 12, 0, 64 }, { 4, 15, 12, 0, 62 }, { 4, 15, 12, 0, 60 }, { 4, 15, 12, 0, 59 }, { 4, 15, 11, 0, 72 }, { 4, 15, 11, 0, 70 }, { 4, 15, 11, 0, 68 }, { 4, 15, 11, 0, 66 }, { 4, 15, 11, 0, 64 }, { 4, 15, 11, 0, 62 }, { 4, 15, 11, 0, 60 }, { 4, 15, 11, 0, 59 }, { 4, 15, 10, 0, 72 }, { 4, 15, 10, 0, 70 }, { 4, 15, 10, 0, 68 }, { 4, 15, 10, 0, 66 }, { 4, 15, 10, 0, 64 }, { 4, 15, 10, 0, 62 }, { 4, 15, 10, 0, 60 }, { 4, 15, 10, 0, 59 }, { 4, 15, 9, 0, 72 }, { 4, 15, 9, 0, 70 }, { 4, 15, 9, 0, 68 }, { 4, 15, 9, 0, 66 }, { 4, 15, 9, 0, 64 }, { 4, 15, 9, 0, 62 }, { 4, 15, 9, 0, 60 }, { 4, 15, 9, 0, 59 }, { 4, 14, 9, 0, 72 }, { 4, 14, 9, 0, 70 }, { 4, 14, 9, 0, 68 }, { 4, 14, 9, 0, 66 }, { 4, 14, 9, 0, 64 }, { 4, 14, 9, 0, 62 }, { 4, 14, 9, 0, 60 }, { 4, 14, 9, 0, 59 }, { 4, 13, 9, 0, 72 }, { 4, 13, 9, 0, 70 }, { 4, 13, 9, 0, 68 }, { 4, 13, 9, 0, 66 }, { 4, 13, 9, 0, 64 }, { 4, 13, 9, 0, 63 }, { 4, 13, 9, 0, 61 }, { 4, 13, 9, 0, 59 }, { 4, 13, 9, 0, 57 }, { 4, 13, 8, 0, 72 }, { 4, 13, 8, 0, 70 }, { 4, 13, 8, 0, 68 }, { 4, 13, 8, 0, 66 }, { 4, 13, 8, 0, 64 }, { 4, 13, 8, 0, 62 }, { 4, 13, 8, 0, 60 }, { 4, 13, 8, 0, 59 }, { 4, 12, 8, 0, 72 }, { 4, 12, 8, 0, 70 }, { 4, 12, 8, 0, 68 }, { 4, 12, 8, 0, 66 }, { 4, 12, 8, 0, 64 }, { 4, 12, 8, 0, 62 }, { 4, 12, 8, 0, 61 }, { 4, 12, 8, 0, 59 }, { 4, 12, 7, 0, 73 }, { 4, 12, 7, 0, 71 }, { 4, 12, 7, 0, 69 }, { 4, 12, 7, 0, 67 }, { 4, 12, 7, 0, 65 }, { 4, 12, 7, 0, 63 }, { 4, 12, 7, 0, 61 }, { 4, 12, 7, 0, 59 }, { 4, 11, 7, 0, 72 }, { 4, 11, 7, 0, 70 }, { 4, 11, 7, 0, 68 }, { 4, 11, 7, 0, 66 }, { 4, 11, 7, 0, 65 }, { 4, 11, 7, 0, 63 }, { 4, 11, 7, 0, 61 }, { 4, 11, 7, 0, 59 }, { 4, 11, 6, 0, 73 }, { 4, 11, 6, 0, 71 }, { 4, 11, 6, 0, 69 }, { 4, 11, 6, 0, 67 }, { 4, 11, 6, 0, 65 }, { 4, 11, 6, 0, 63 }, { 4, 11, 6, 0, 61 }, { 4, 11, 6, 0, 60 }, { 4, 10, 6, 0, 72 }, { 4, 10, 6, 0, 70 }, { 4, 10, 6, 0, 68 }, { 4, 10, 6, 0, 66 }, { 4, 10, 6, 0, 64 }, { 4, 10, 6, 0, 62 }, { 4, 10, 6, 0, 60 } }; static struct bwn_txgain_entry txgain_5ghz_r1[] = { { 7, 15, 15, 0, 99 }, { 7, 15, 15, 0, 96 }, { 7, 15, 15, 0, 93 }, { 7, 15, 15, 0, 90 }, { 7, 15, 15, 0, 88 }, { 7, 15, 15, 0, 85 }, { 7, 15, 15, 0, 83 }, { 7, 15, 15, 0, 81 }, { 7, 15, 15, 0, 78 }, { 7, 15, 15, 0, 76 }, { 7, 15, 15, 0, 74 }, { 7, 15, 15, 0, 72 }, { 7, 15, 15, 0, 70 }, { 7, 15, 15, 0, 68 }, { 7, 15, 15, 0, 66 }, { 7, 15, 15, 0, 64 }, { 7, 15, 15, 0, 62 }, { 7, 15, 15, 0, 60 }, { 7, 15, 15, 0, 59 }, { 7, 15, 15, 0, 57 }, { 7, 15, 15, 0, 55 }, { 7, 15, 14, 0, 72 }, { 7, 15, 14, 0, 70 }, { 7, 15, 14, 0, 68 }, { 7, 15, 14, 0, 66 }, { 7, 15, 14, 0, 64 }, { 7, 15, 14, 0, 62 }, { 7, 15, 14, 0, 60 }, { 7, 15, 14, 0, 58 }, { 7, 15, 14, 0, 56 }, { 7, 15, 14, 0, 55 }, { 7, 15, 13, 0, 71 }, { 7, 15, 13, 0, 69 }, { 7, 15, 13, 0, 67 }, { 7, 15, 13, 0, 65 }, { 7, 15, 13, 0, 63 }, { 7, 15, 13, 0, 62 }, { 7, 15, 13, 0, 60 }, { 7, 15, 13, 0, 58 }, { 7, 15, 13, 0, 56 }, { 7, 15, 12, 0, 72 }, { 7, 15, 12, 0, 70 }, { 7, 15, 12, 0, 68 }, { 7, 15, 12, 0, 66 }, { 7, 15, 12, 0, 64 }, { 7, 15, 12, 0, 62 }, { 7, 15, 12, 0, 60 }, { 7, 15, 12, 0, 59 }, { 7, 15, 12, 0, 57 }, { 7, 15, 11, 0, 73 }, { 7, 15, 11, 0, 71 }, { 7, 15, 11, 0, 69 }, { 7, 15, 11, 0, 67 }, { 7, 15, 11, 0, 65 }, { 7, 15, 11, 0, 63 }, { 7, 15, 11, 0, 61 }, { 7, 15, 11, 0, 60 }, { 7, 15, 11, 0, 58 }, { 7, 15, 10, 0, 71 }, { 7, 15, 10, 0, 69 }, { 7, 15, 10, 0, 67 }, { 7, 15, 10, 0, 65 }, { 7, 15, 10, 0, 63 }, { 7, 15, 10, 0, 61 }, { 7, 15, 10, 0, 60 }, { 7, 15, 10, 0, 58 }, { 7, 15, 9, 0, 70 }, { 7, 15, 9, 0, 68 }, { 7, 15, 9, 0, 66 }, { 7, 15, 9, 0, 64 }, { 7, 15, 9, 0, 62 }, { 7, 15, 9, 0, 61 }, { 7, 15, 9, 0, 59 }, { 7, 15, 9, 0, 57 }, { 7, 15, 9, 0, 56 }, { 7, 14, 9, 0, 68 }, { 7, 14, 9, 0, 66 }, { 7, 14, 9, 0, 65 }, { 7, 14, 9, 0, 63 }, { 7, 14, 9, 0, 61 }, { 7, 14, 9, 0, 59 }, { 7, 14, 9, 0, 58 }, { 7, 13, 9, 0, 70 }, { 7, 13, 9, 0, 68 }, { 7, 13, 9, 0, 66 }, { 7, 13, 9, 0, 64 }, { 7, 13, 9, 0, 63 }, { 7, 13, 9, 0, 61 }, { 7, 13, 9, 0, 59 }, { 7, 13, 9, 0, 57 }, { 7, 13, 8, 0, 70 }, { 7, 13, 8, 0, 68 }, { 7, 13, 8, 0, 66 }, { 7, 13, 8, 0, 64 }, { 7, 13, 8, 0, 62 }, { 7, 13, 8, 0, 60 }, { 7, 13, 8, 0, 59 }, { 7, 13, 8, 0, 57 }, { 7, 12, 8, 0, 70 }, { 7, 12, 8, 0, 68 }, { 7, 12, 8, 0, 66 }, { 7, 12, 8, 0, 64 }, { 7, 12, 8, 0, 62 }, { 7, 12, 8, 0, 61 }, { 7, 12, 8, 0, 59 }, { 7, 12, 8, 0, 57 }, { 7, 12, 7, 0, 70 }, { 7, 12, 7, 0, 68 }, { 7, 12, 7, 0, 66 }, { 7, 12, 7, 0, 64 }, { 7, 12, 7, 0, 62 }, { 7, 12, 7, 0, 61 }, { 7, 12, 7, 0, 59 }, { 7, 12, 7, 0, 57 }, { 7, 11, 7, 0, 70 }, { 7, 11, 7, 0, 68 }, { 7, 11, 7, 0, 66 }, { 7, 11, 7, 0, 64 }, { 7, 11, 7, 0, 62 }, { 7, 11, 7, 0, 61 }, { 7, 11, 7, 0, 59 }, { 7, 11, 7, 0, 57 }, { 7, 11, 6, 0, 69 }, { 7, 11, 6, 0, 67 }, { 7, 11, 6, 0, 65 }, { 7, 11, 6, 0, 63 }, { 7, 11, 6, 0, 62 }, { 7, 11, 6, 0, 60 } }; if (mac->mac_phy.rev != 0 && mac->mac_phy.rev != 1) { - if (siba_sprom_get_bf_hi(sc->sc_dev) & BWN_BFH_NOPA) + if (sc->sc_board_info.board_flags & BHND_BFL_NOPA) bwn_phy_lp_gaintbl_write_multi(mac, 0, 128, txgain_r2); else if (IEEE80211_IS_CHAN_2GHZ(ic->ic_curchan)) bwn_phy_lp_gaintbl_write_multi(mac, 0, 128, txgain_2ghz_r2); else bwn_phy_lp_gaintbl_write_multi(mac, 0, 128, txgain_5ghz_r2); return; } if (mac->mac_phy.rev == 0) { - if ((siba_sprom_get_bf_hi(sc->sc_dev) & BWN_BFH_NOPA) || - (siba_sprom_get_bf_lo(sc->sc_dev) & BWN_BFL_HGPA)) + if ((sc->sc_board_info.board_flags & BHND_BFL_NOPA) || + (sc->sc_board_info.board_flags & BHND_BFL_HGPA)) bwn_phy_lp_gaintbl_write_multi(mac, 0, 128, txgain_r0); else if (IEEE80211_IS_CHAN_2GHZ(ic->ic_curchan)) bwn_phy_lp_gaintbl_write_multi(mac, 0, 128, txgain_2ghz_r0); else bwn_phy_lp_gaintbl_write_multi(mac, 0, 128, txgain_5ghz_r0); return; } - if ((siba_sprom_get_bf_hi(sc->sc_dev) & BWN_BFH_NOPA) || - (siba_sprom_get_bf_lo(sc->sc_dev) & BWN_BFL_HGPA)) + if ((sc->sc_board_info.board_flags & BHND_BFL_NOPA) || + (sc->sc_board_info.board_flags & BHND_BFL_HGPA)) bwn_phy_lp_gaintbl_write_multi(mac, 0, 128, txgain_r1); else if (IEEE80211_IS_CHAN_2GHZ(ic->ic_curchan)) bwn_phy_lp_gaintbl_write_multi(mac, 0, 128, txgain_2ghz_r1); else bwn_phy_lp_gaintbl_write_multi(mac, 0, 128, txgain_5ghz_r1); } static void bwn_tab_write(struct bwn_mac *mac, uint32_t typeoffset, uint32_t value) { uint32_t offset, type; type = BWN_TAB_GETTYPE(typeoffset); offset = BWN_TAB_GETOFFSET(typeoffset); KASSERT(offset <= 0xffff, ("%s:%d: fail", __func__, __LINE__)); switch (type) { case BWN_TAB_8BIT: KASSERT(!(value & ~0xff), ("%s:%d: fail", __func__, __LINE__)); BWN_PHY_WRITE(mac, BWN_PHY_TABLE_ADDR, offset); BWN_PHY_WRITE(mac, BWN_PHY_TABLEDATALO, value); break; case BWN_TAB_16BIT: KASSERT(!(value & ~0xffff), ("%s:%d: fail", __func__, __LINE__)); BWN_PHY_WRITE(mac, BWN_PHY_TABLE_ADDR, offset); BWN_PHY_WRITE(mac, BWN_PHY_TABLEDATALO, value); break; case BWN_TAB_32BIT: BWN_PHY_WRITE(mac, BWN_PHY_TABLE_ADDR, offset); BWN_PHY_WRITE(mac, BWN_PHY_TABLEDATAHI, value >> 16); BWN_PHY_WRITE(mac, BWN_PHY_TABLEDATALO, value); break; default: KASSERT(0 == 1, ("%s:%d: fail", __func__, __LINE__)); } } static int bwn_phy_lp_loopback(struct bwn_mac *mac) { struct bwn_phy_lp_iq_est ie; int i, index = -1; uint32_t tmp; memset(&ie, 0, sizeof(ie)); bwn_phy_lp_set_trsw_over(mac, 1, 1); BWN_PHY_SET(mac, BWN_PHY_AFE_CTL_OVR, 1); BWN_PHY_MASK(mac, BWN_PHY_AFE_CTL_OVRVAL, 0xfffe); BWN_PHY_SET(mac, BWN_PHY_RF_OVERRIDE_0, 0x800); BWN_PHY_SET(mac, BWN_PHY_RF_OVERRIDE_VAL_0, 0x800); BWN_PHY_SET(mac, BWN_PHY_RF_OVERRIDE_0, 0x8); BWN_PHY_SET(mac, BWN_PHY_RF_OVERRIDE_VAL_0, 0x8); BWN_RF_WRITE(mac, BWN_B2062_N_TXCTL_A, 0x80); BWN_PHY_SET(mac, BWN_PHY_RF_OVERRIDE_0, 0x80); BWN_PHY_SET(mac, BWN_PHY_RF_OVERRIDE_VAL_0, 0x80); for (i = 0; i < 32; i++) { bwn_phy_lp_set_rxgain_idx(mac, i); bwn_phy_lp_ddfs_turnon(mac, 1, 1, 5, 5, 0); if (!(bwn_phy_lp_rx_iq_est(mac, 1000, 32, &ie))) continue; tmp = (ie.ie_ipwr + ie.ie_qpwr) / 1000; if ((tmp > 4000) && (tmp < 10000)) { index = i; break; } } bwn_phy_lp_ddfs_turnoff(mac); return (index); } static void bwn_phy_lp_set_rxgain_idx(struct bwn_mac *mac, uint16_t idx) { bwn_phy_lp_set_rxgain(mac, bwn_tab_read(mac, BWN_TAB_2(12, idx))); } static void bwn_phy_lp_ddfs_turnon(struct bwn_mac *mac, int i_on, int q_on, int incr1, int incr2, int scale_idx) { bwn_phy_lp_ddfs_turnoff(mac); BWN_PHY_MASK(mac, BWN_PHY_AFE_DDFS_POINTER_INIT, 0xff80); BWN_PHY_MASK(mac, BWN_PHY_AFE_DDFS_POINTER_INIT, 0x80ff); BWN_PHY_SETMASK(mac, BWN_PHY_AFE_DDFS_INCR_INIT, 0xff80, incr1); BWN_PHY_SETMASK(mac, BWN_PHY_AFE_DDFS_INCR_INIT, 0x80ff, incr2 << 8); BWN_PHY_SETMASK(mac, BWN_PHY_AFE_DDFS, 0xfff7, i_on << 3); BWN_PHY_SETMASK(mac, BWN_PHY_AFE_DDFS, 0xffef, q_on << 4); BWN_PHY_SETMASK(mac, BWN_PHY_AFE_DDFS, 0xff9f, scale_idx << 5); BWN_PHY_MASK(mac, BWN_PHY_AFE_DDFS, 0xfffb); BWN_PHY_SET(mac, BWN_PHY_AFE_DDFS, 0x2); BWN_PHY_SET(mac, BWN_PHY_LP_PHY_CTL, 0x20); } static uint8_t bwn_phy_lp_rx_iq_est(struct bwn_mac *mac, uint16_t sample, uint8_t time, struct bwn_phy_lp_iq_est *ie) { int i; BWN_PHY_MASK(mac, BWN_PHY_CRSGAIN_CTL, 0xfff7); BWN_PHY_WRITE(mac, BWN_PHY_IQ_NUM_SMPLS_ADDR, sample); BWN_PHY_SETMASK(mac, BWN_PHY_IQ_ENABLE_WAIT_TIME_ADDR, 0xff00, time); BWN_PHY_MASK(mac, BWN_PHY_IQ_ENABLE_WAIT_TIME_ADDR, 0xfeff); BWN_PHY_SET(mac, BWN_PHY_IQ_ENABLE_WAIT_TIME_ADDR, 0x200); for (i = 0; i < 500; i++) { if (!(BWN_PHY_READ(mac, BWN_PHY_IQ_ENABLE_WAIT_TIME_ADDR) & 0x200)) break; DELAY(1000); } if ((BWN_PHY_READ(mac, BWN_PHY_IQ_ENABLE_WAIT_TIME_ADDR) & 0x200)) { BWN_PHY_SET(mac, BWN_PHY_CRSGAIN_CTL, 0x8); return 0; } ie->ie_iqprod = BWN_PHY_READ(mac, BWN_PHY_IQ_ACC_HI_ADDR); ie->ie_iqprod <<= 16; ie->ie_iqprod |= BWN_PHY_READ(mac, BWN_PHY_IQ_ACC_LO_ADDR); ie->ie_ipwr = BWN_PHY_READ(mac, BWN_PHY_IQ_I_PWR_ACC_HI_ADDR); ie->ie_ipwr <<= 16; ie->ie_ipwr |= BWN_PHY_READ(mac, BWN_PHY_IQ_I_PWR_ACC_LO_ADDR); ie->ie_qpwr = BWN_PHY_READ(mac, BWN_PHY_IQ_Q_PWR_ACC_HI_ADDR); ie->ie_qpwr <<= 16; ie->ie_qpwr |= BWN_PHY_READ(mac, BWN_PHY_IQ_Q_PWR_ACC_LO_ADDR); BWN_PHY_SET(mac, BWN_PHY_CRSGAIN_CTL, 0x8); return 1; } static uint32_t bwn_tab_read(struct bwn_mac *mac, uint32_t typeoffset) { uint32_t offset, type, value; type = BWN_TAB_GETTYPE(typeoffset); offset = BWN_TAB_GETOFFSET(typeoffset); KASSERT(offset <= 0xffff, ("%s:%d: fail", __func__, __LINE__)); switch (type) { case BWN_TAB_8BIT: BWN_PHY_WRITE(mac, BWN_PHY_TABLE_ADDR, offset); value = BWN_PHY_READ(mac, BWN_PHY_TABLEDATALO) & 0xff; break; case BWN_TAB_16BIT: BWN_PHY_WRITE(mac, BWN_PHY_TABLE_ADDR, offset); value = BWN_PHY_READ(mac, BWN_PHY_TABLEDATALO); break; case BWN_TAB_32BIT: BWN_PHY_WRITE(mac, BWN_PHY_TABLE_ADDR, offset); value = BWN_PHY_READ(mac, BWN_PHY_TABLEDATAHI); value <<= 16; value |= BWN_PHY_READ(mac, BWN_PHY_TABLEDATALO); break; default: KASSERT(0 == 1, ("%s:%d: fail", __func__, __LINE__)); value = 0; } return (value); } static void bwn_phy_lp_ddfs_turnoff(struct bwn_mac *mac) { BWN_PHY_MASK(mac, BWN_PHY_AFE_DDFS, 0xfffd); BWN_PHY_MASK(mac, BWN_PHY_LP_PHY_CTL, 0xffdf); } static void bwn_phy_lp_set_txgain_dac(struct bwn_mac *mac, uint16_t dac) { uint16_t ctl; ctl = BWN_PHY_READ(mac, BWN_PHY_AFE_DAC_CTL) & 0xc7f; ctl |= dac << 7; BWN_PHY_SETMASK(mac, BWN_PHY_AFE_DAC_CTL, 0xf000, ctl); } static void bwn_phy_lp_set_txgain_pa(struct bwn_mac *mac, uint16_t gain) { BWN_PHY_SETMASK(mac, BWN_PHY_OFDM(0xfb), 0xe03f, gain << 6); BWN_PHY_SETMASK(mac, BWN_PHY_OFDM(0xfd), 0x80ff, gain << 8); } static void bwn_phy_lp_set_txgain_override(struct bwn_mac *mac) { if (mac->mac_phy.rev < 2) BWN_PHY_SET(mac, BWN_PHY_RF_OVERRIDE_2, 0x100); else { BWN_PHY_SET(mac, BWN_PHY_RF_OVERRIDE_2, 0x80); BWN_PHY_SET(mac, BWN_PHY_RF_OVERRIDE_2, 0x4000); } BWN_PHY_SET(mac, BWN_PHY_AFE_CTL_OVR, 0x40); } static uint16_t bwn_phy_lp_get_pa_gain(struct bwn_mac *mac) { return BWN_PHY_READ(mac, BWN_PHY_OFDM(0xfb)) & 0x7f; } static uint8_t bwn_nbits(int32_t val) { uint32_t tmp; uint8_t nbits = 0; for (tmp = abs(val); tmp != 0; tmp >>= 1) nbits++; return (nbits); } static void bwn_phy_lp_gaintbl_write_multi(struct bwn_mac *mac, int offset, int count, struct bwn_txgain_entry *table) { int i; for (i = offset; i < count; i++) bwn_phy_lp_gaintbl_write(mac, i, table[i]); } static void bwn_phy_lp_gaintbl_write(struct bwn_mac *mac, int offset, struct bwn_txgain_entry data) { if (mac->mac_phy.rev >= 2) bwn_phy_lp_gaintbl_write_r2(mac, offset, data); else bwn_phy_lp_gaintbl_write_r01(mac, offset, data); } static void bwn_phy_lp_gaintbl_write_r2(struct bwn_mac *mac, int offset, struct bwn_txgain_entry te) { struct bwn_softc *sc = mac->mac_sc; struct ieee80211com *ic = &sc->sc_ic; uint32_t tmp; KASSERT(mac->mac_phy.rev >= 2, ("%s:%d: fail", __func__, __LINE__)); tmp = (te.te_pad << 16) | (te.te_pga << 8) | te.te_gm; if (mac->mac_phy.rev >= 3) { tmp |= ((IEEE80211_IS_CHAN_5GHZ(ic->ic_curchan)) ? (0x10 << 24) : (0x70 << 24)); } else { tmp |= ((IEEE80211_IS_CHAN_5GHZ(ic->ic_curchan)) ? (0x14 << 24) : (0x7f << 24)); } bwn_tab_write(mac, BWN_TAB_4(7, 0xc0 + offset), tmp); bwn_tab_write(mac, BWN_TAB_4(7, 0x140 + offset), te.te_bbmult << 20 | te.te_dac << 28); } static void bwn_phy_lp_gaintbl_write_r01(struct bwn_mac *mac, int offset, struct bwn_txgain_entry te) { KASSERT(mac->mac_phy.rev < 2, ("%s:%d: fail", __func__, __LINE__)); bwn_tab_write(mac, BWN_TAB_4(10, 0xc0 + offset), (te.te_pad << 11) | (te.te_pga << 7) | (te.te_gm << 4) | te.te_dac); bwn_tab_write(mac, BWN_TAB_4(10, 0x140 + offset), te.te_bbmult << 20); } Index: head/sys/dev/bwn/if_bwn_phy_n.c =================================================================== --- head/sys/dev/bwn/if_bwn_phy_n.c (revision 328911) +++ head/sys/dev/bwn/if_bwn_phy_n.c (revision 328912) @@ -1,283 +1,280 @@ /*- * Copyright (c) 2016 Adrian Chadd * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer, * without modification. * 2. Redistributions in binary form must reproduce at minimum a disclaimer * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any * redistribution must be conditioned upon including a substantially * similar Disclaimer requirement for further binary redistribution. * * NO WARRANTY * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF * THE POSSIBILITY OF SUCH DAMAGES. */ #include __FBSDID("$FreeBSD$"); /* * This is the top-level N-PHY support for the Broadcom softmac driver. */ #include "opt_bwn.h" #include "opt_wlan.h" #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include -#include - #include #include #include #include #include #ifdef BWN_GPL_PHY #include #include #include #endif /* * This module is always compiled into the kernel, regardless of * whether the GPL PHY is enabled. If the GPL PHY isn't enabled * then it'll just be stubs that will fail to attach. */ int bwn_phy_n_attach(struct bwn_mac *mac) { #ifdef BWN_GPL_PHY return bwn_nphy_op_allocate(mac); #else device_printf(mac->mac_sc->sc_dev, "%s: BWN_GPL_PHY not in kernel config; " "no PHY-N support\n", __func__); return (ENXIO); #endif } void bwn_phy_n_detach(struct bwn_mac *mac) { #ifdef BWN_GPL_PHY return bwn_nphy_op_free(mac); #endif } int bwn_phy_n_prepare_hw(struct bwn_mac *mac) { #ifdef BWN_GPL_PHY - bwn_nphy_op_prepare_structs(mac); - return (0); + return (bwn_nphy_op_prepare_structs(mac)); #else return (ENXIO); #endif } void bwn_phy_n_init_pre(struct bwn_mac *mac) { /* XXX TODO */ } int bwn_phy_n_init(struct bwn_mac *mac) { #ifdef BWN_GPL_PHY return bwn_nphy_op_init(mac); #else return (ENXIO); #endif } void bwn_phy_n_exit(struct bwn_mac *mac) { /* XXX TODO */ } uint16_t bwn_phy_n_read(struct bwn_mac *mac, uint16_t reg) { BWN_WRITE_2(mac, BWN_PHYCTL, reg); return BWN_READ_2(mac, BWN_PHYDATA); } void bwn_phy_n_write(struct bwn_mac *mac, uint16_t reg, uint16_t value) { BWN_WRITE_2(mac, BWN_PHYCTL, reg); BWN_WRITE_2(mac, BWN_PHYDATA, value); } uint16_t bwn_phy_n_rf_read(struct bwn_mac *mac, uint16_t reg) { /* Register 1 is a 32-bit register. */ if (mac->mac_phy.rev < 7 && reg == 1) { BWN_ERRPRINTF(mac->mac_sc, "%s: bad reg access\n", __func__); } if (mac->mac_phy.rev >= 7) reg |= 0x200; /* radio 0x2057 */ else reg |= 0x100; BWN_WRITE_2(mac, BWN_RFCTL, reg); return BWN_READ_2(mac, BWN_RFDATALO); } void bwn_phy_n_rf_write(struct bwn_mac *mac, uint16_t reg, uint16_t value) { /* Register 1 is a 32-bit register. */ if (mac->mac_phy.rev < 7 && reg == 1) { BWN_ERRPRINTF(mac->mac_sc, "%s: bad reg access\n", __func__); } BWN_WRITE_2(mac, BWN_RFCTL, reg); BWN_WRITE_2(mac, BWN_RFDATALO, value); } int bwn_phy_n_hwpctl(struct bwn_mac *mac) { return (0); } void bwn_phy_n_rf_onoff(struct bwn_mac *mac, int on) { #ifdef BWN_GPL_PHY bwn_nphy_op_software_rfkill(mac, on); #endif } void bwn_phy_n_switch_analog(struct bwn_mac *mac, int on) { #ifdef BWN_GPL_PHY bwn_nphy_op_switch_analog(mac, on); #endif } int bwn_phy_n_switch_channel(struct bwn_mac *mac, uint32_t newchan) { #ifdef BWN_GPL_PHY return bwn_nphy_op_switch_channel(mac, newchan); #else return (ENXIO); #endif } uint32_t bwn_phy_n_get_default_chan(struct bwn_mac *mac) { if (bwn_current_band(mac) == BWN_BAND_2G) return (1); return (36); } void bwn_phy_n_set_antenna(struct bwn_mac *mac, int antenna) { /* XXX TODO */ } int bwn_phy_n_im(struct bwn_mac *mac, int mode) { /* XXX TODO */ return (0); } bwn_txpwr_result_t bwn_phy_n_recalc_txpwr(struct bwn_mac *mac, int ignore_tssi) { #ifdef BWN_GPL_PHY return bwn_nphy_op_recalc_txpower(mac, ignore_tssi); #else return (BWN_TXPWR_RES_DONE); #endif } void bwn_phy_n_set_txpwr(struct bwn_mac *mac) { } void bwn_phy_n_task_15s(struct bwn_mac *mac) { } void bwn_phy_n_task_60s(struct bwn_mac *mac) { } Index: head/sys/dev/bwn/if_bwn_util.c =================================================================== --- head/sys/dev/bwn/if_bwn_util.c (revision 328911) +++ head/sys/dev/bwn/if_bwn_util.c (revision 328912) @@ -1,134 +1,131 @@ /*- * Copyright (c) 2009-2010 Weongyo Jeong * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer, * without modification. * 2. Redistributions in binary form must reproduce at minimum a disclaimer * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any * redistribution must be conditioned upon including a substantially * similar Disclaimer requirement for further binary redistribution. * * NO WARRANTY * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF * THE POSSIBILITY OF SUCH DAMAGES. */ #include __FBSDID("$FreeBSD$"); /* * The Broadcom Wireless LAN controller driver. */ #include "opt_bwn.h" #include "opt_wlan.h" #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include -#include - #include #include -#include #include #include #include unsigned int bwn_sqrt(struct bwn_mac *mac, unsigned int x) { /* Table holding (10 * sqrt(x)) for x between 1 and 256. */ static uint8_t sqrt_table[256] = { 10, 14, 17, 20, 22, 24, 26, 28, 30, 31, 33, 34, 36, 37, 38, 40, 41, 42, 43, 44, 45, 46, 47, 48, 50, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 60, 61, 62, 63, 64, 64, 65, 66, 67, 67, 68, 69, 70, 70, 71, 72, 72, 73, 74, 74, 75, 76, 76, 77, 78, 78, 79, 80, 80, 81, 81, 82, 83, 83, 84, 84, 85, 86, 86, 87, 87, 88, 88, 89, 90, 90, 91, 91, 92, 92, 93, 93, 94, 94, 95, 95, 96, 96, 97, 97, 98, 98, 99, 100, 100, 100, 101, 101, 102, 102, 103, 103, 104, 104, 105, 105, 106, 106, 107, 107, 108, 108, 109, 109, 110, 110, 110, 111, 111, 112, 112, 113, 113, 114, 114, 114, 115, 115, 116, 116, 117, 117, 117, 118, 118, 119, 119, 120, 120, 120, 121, 121, 122, 122, 122, 123, 123, 124, 124, 124, 125, 125, 126, 126, 126, 127, 127, 128, 128, 128, 129, 129, 130, 130, 130, 131, 131, 131, 132, 132, 133, 133, 133, 134, 134, 134, 135, 135, 136, 136, 136, 137, 137, 137, 138, 138, 138, 139, 139, 140, 140, 140, 141, 141, 141, 142, 142, 142, 143, 143, 143, 144, 144, 144, 145, 145, 145, 146, 146, 146, 147, 147, 147, 148, 148, 148, 149, 149, 150, 150, 150, 150, 151, 151, 151, 152, 152, 152, 153, 153, 153, 154, 154, 154, 155, 155, 155, 156, 156, 156, 157, 157, 157, 158, 158, 158, 159, 159, 159, 160 }; if (x == 0) return (0); if (x >= 256) { unsigned int tmp; for (tmp = 0; x >= (2 * tmp) + 1; x -= (2 * tmp++) + 1) /* do nothing */ ; return (tmp); } return (sqrt_table[x - 1] / 10); } Index: head/sys/dev/bwn/if_bwnreg.h =================================================================== --- head/sys/dev/bwn/if_bwnreg.h (revision 328911) +++ head/sys/dev/bwn/if_bwnreg.h (revision 328912) @@ -1,1126 +1,1086 @@ /*- * SPDX-License-Identifier: BSD-2-Clause-FreeBSD * * Copyright (c) 2009-2010 Weongyo Jeong * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer, * without modification. * 2. Redistributions in binary form must reproduce at minimum a disclaimer * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any * redistribution must be conditioned upon including a substantially * similar Disclaimer requirement for further binary redistribution. * * NO WARRANTY * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF * THE POSSIBILITY OF SUCH DAMAGES. * * $FreeBSD$ */ #ifndef _IF_BWNREG_H #define _IF_BWNREG_H -#define PCI_VENDOR_COMPAQ 0x0e11 -#define PCI_VENDOR_DELL 0x1028 -#define PCI_VENDOR_HP 0x103c -#define PCI_VENDOR_ASUSTEK 0x1043 -#define PCI_VENDOR_MOTOROLA 0x1057 -#define PCI_VENDOR_APPLE 0x106b -#define PCI_VENDOR_BROADCOM 0x14e4 -#define PCI_VENDOR_LINKSYS 0x1737 - -/* SPROM flags */ -#define BWN_BFL_BTCOEXIST 0x0001 /* implements Bluetooth coexistance */ -#define BWN_BFL_PACTRL 0x0002 /* GPIO 9 controlling the PA */ -#define BWN_BFL_AIRLINEMODE 0x0004 /* implements GPIO 13 radio disable indication */ -#define BWN_BFL_RSSI 0x0008 /* software calculates nrssi slope. */ -#define BWN_BFL_ENETSPI 0x0010 /* has ephy roboswitch spi */ -#define BWN_BFL_CRYSTAL_NOSLOW 0x0020 /* no slow clock available */ -#define BWN_BFL_CCKHIPWR 0x0040 /* can do high power CCK transmission */ -#define BWN_BFL_ENETADM 0x0080 /* has ADMtek switch */ -#define BWN_BFL_ENETVLAN 0x0100 /* can do vlan */ -#define BWN_BFL_AFTERBURNER 0x0200 /* supports Afterburner mode */ -#define BWN_BFL_NOPCI 0x0400 /* leaves PCI floating */ -#define BWN_BFL_FEM 0x0800 /* supports the Front End Module */ -#define BWN_BFL_EXTLNA 0x1000 /* has an external LNA */ -#define BWN_BFL_HGPA 0x2000 /* had high gain PA */ -#define BWN_BFL_BTCMOD 0x4000 /* BFL_BTCOEXIST is given in alternate GPIOs */ -#define BWN_BFL_ALTIQ 0x8000 /* alternate I/Q settings */ - -/* SPROM boardflags_hi values */ -#define BWN_BFH_NOPA 0x0001 /* has no PA */ -#define BWN_BFH_RSSIINV 0x0002 /* RSSI uses positive slope (not TSSI) */ -#define BWN_BFH_LDO_PAREF 0x0004 /* uses the PARef LDO */ -#define BWN_BFH_3TSWITCH 0x0008 /* uses a triple throw switch shared - * with bluetooth */ -#define BWN_BFH_PHASESHIFT 0x0010 /* can support phase shifter */ -#define BWN_BFH_BUCKBOOST 0x0020 /* has buck/booster */ -#define BWN_BFH_FEM_BT 0x0040 /* has FEM and switch to share antenna - * with bluetooth */ -#define BWN_BFH_NOCBUCK 0x0080 -#define BWN_BFH_PALDO 0x0200 -#define BWN_BFH_EXTLNA_5GHZ 0x1000 /* has an external LNA (5GHz mode) */ - -/* SPROM boardflags2_lo values */ -#define BWN_BFL2_RXBB_INT_REG_DIS 0x0001 /* external RX BB regulator present */ -#define BWN_BFL2_APLL_WAR 0x0002 /* alternative A-band PLL settings implemented */ -#define BWN_BFL2_TXPWRCTRL_EN 0x0004 /* permits enabling TX Power Control */ -#define BWN_BFL2_2X4_DIV 0x0008 /* 2x4 diversity switch */ -#define BWN_BFL2_5G_PWRGAIN 0x0010 /* supports 5G band power gain */ -#define BWN_BFL2_PCIEWAR_OVR 0x0020 /* overrides ASPM and Clkreq settings */ -#define BWN_BFL2_CAESERS_BRD 0x0040 /* is Caesers board (unused) */ -#define BWN_BFL2_BTC3WIRE 0x0080 /* used 3-wire bluetooth coexist */ -#define BWN_BFL2_SKWRKFEM_BRD 0x0100 /* 4321mcm93 uses Skyworks FEM */ -#define BWN_BFL2_SPUR_WAR 0x0200 /* has a workaround for clock-harmonic spurs */ -#define BWN_BFL2_GPLL_WAR 0x0400 /* altenative G-band PLL settings implemented */ -#define BWN_BFL2_SINGLEANT_CCK 0x1000 -#define BWN_BFL2_2G_SPUR_WAR 0x2000 - -/* SPROM boardflags2_hi values */ -#define BWN_BFH2_GPLL_WAR2 0x0001 -#define BWN_BFH2_IPALVLSHIFT_3P3 0x0002 -#define BWN_BFH2_INTERNDET_TXIQCAL 0x0004 -#define BWN_BFH2_XTALBUFOUTEN 0x0008 - -/* SIBA control registers */ -#define BWN_TGSLOW_PHYCLOCK_ENABLE 0x00040000 -#define BWN_TGSLOW_PHYRESET 0x00080000 -#define BWN_TGSLOW_MACPHYCLKEN 0x00100000 /* MAC PHY Clock Control Enable (rev >= 5) */ -#define BWN_TGSLOW_PLLREFSEL 0x00200000 /* PLL Frequency Reference Select (rev >= 5) */ +/* D11-specific I/O control flags */ +#define BWN_IOCTL_PHYCLOCK_ENABLE 0x0004 +#define BWN_IOCTL_PHYRESET 0x0008 +#define BWN_IOCTL_MACPHYCLKEN 0x0010 /* MAC PHY Clock Control Enable (rev >= 5) */ +#define BWN_IOCTL_PLLREFSEL 0x0020 /* PLL Frequency Reference Select (rev >= 5) */ /* PHY_BANDWIDTH: N-PHY only */ -#define BWN_TGSLOW_PHY_BANDWIDTH 0x00C00000 -#define BWN_TGSLOW_PHY_BANDWIDTH_10MHZ 0x00000000 -#define BWN_TGSLOW_PHY_BANDWIDTH_20MHZ 0x00400000 -#define BWN_TGSLOW_PHY_BANDWIDTH_40MHZ 0x00800000 -#define BWN_TGSLOW_SUPPORT_G 0x20000000 +#define BWN_IOCTL_PHY_BANDWIDTH 0x00C0 +#define BWN_IOCTL_PHY_BANDWIDTH_10MHZ 0x0000 +#define BWN_IOCTL_PHY_BANDWIDTH_20MHZ 0x0040 +#define BWN_IOCTL_PHY_BANDWIDTH_40MHZ 0x0080 +#define BWN_IOCTL_SUPPORT_G 0x2000 -#define BWN_TGSHIGH_HAVE_2GHZ 0x00010000 -#define BWN_TGSHIGH_HAVE_5GHZ 0x00020000 -#define BWN_TGSHIGH_DUALPHY 0x00080000 +/* D11-specific I/O status flags */ +#define BWN_IOST_HAVE_2GHZ 0x0001 +#define BWN_IOST_HAVE_5GHZ 0x0002 +#define BWN_IOST_DUALPHY 0x0008 #define BWN_PHYTYPE_A 0x00 #define BWN_PHYTYPE_B 0x01 #define BWN_PHYTYPE_G 0x02 #define BWN_PHYTYPE_N 0x04 #define BWN_PHYTYPE_LP 0x05 #define BWN_PHYTYPE_SSLPN 0x06 #define BWN_PHYTYPE_HT 0x07 #define BWN_PHYTYPE_LCN 0x08 #define BWN_PHYTYPE_LCNXN 0x09 #define BWN_PHYTYPE_LCN40 0x0a #define BWN_PHYTYPE_AC 0x0b #define BWN_DMA0_REASON 0x20 #define BWN_DMA0_INTR_MASK 0x24 #define BWN_DMA1_REASON 0x28 #define BWN_DMA1_INTR_MASK 0x2c #define BWN_DMA2_REASON 0x30 #define BWN_DMA2_INTR_MASK 0x34 #define BWN_DMA3_REASON 0x38 #define BWN_DMA3_INTR_MASK 0x3c #define BWN_DMA4_REASON 0x40 #define BWN_DMA4_INTR_MASK 0x44 #define BWN_DMA5_INTR_MASK 0x4c #define BWN_MACCTL 0x120 #define BWN_MACCTL_ON 0x00000001 #define BWN_MACCTL_MCODE_RUN 0x00000002 #define BWN_MACCTL_MCODE_JMP0 0x00000004 #define BWN_MACCTL_SHM_ON 0x00000100 #define BWN_MACCTL_IHR_ON 0x00000400 #define BWN_MACCTL_GPOUT_MASK 0x0000c000 #define BWN_MACCTL_BIGENDIAN 0x00010000 #define BWN_MACCTL_STA 0x00020000 #define BWN_MACCTL_HOSTAP 0x00040000 #define BWN_MACCTL_RADIO_LOCK 0x00080000 #define BWN_MACCTL_BEACON_PROMISC 0x00100000 #define BWN_MACCTL_PASS_BADPLCP 0x00200000 #define BWN_MACCTL_PHY_LOCK 0x00200000 /* PHY-N? */ #define BWN_MACCTL_PASS_CTL 0x00400000 #define BWN_MACCTL_PASS_BADFCS 0x00800000 #define BWN_MACCTL_PROMISC 0x01000000 #define BWN_MACCTL_HWPS 0x02000000 #define BWN_MACCTL_AWAKE 0x04000000 #define BWN_MACCTL_CLOSEDNET 0x08000000 #define BWN_MACCTL_TBTT_HOLD 0x10000000 #define BWN_MACCTL_DISC_TXSTAT 0x20000000 #define BWN_MACCTL_DISC_PMQ 0x40000000 #define BWN_MACCTL_GMODE 0x80000000 #define BWN_MACCMD 0x124 /* MAC command */ #define BWN_MACCMD_BEACON0_VALID 0x00000001 #define BWN_MACCMD_BEACON1_VALID 0x00000002 #define BWN_MACCMD_DFQ_VALID 0x00000004 #define BWN_MACCMD_BGNOISE 0x00000010 #define BWN_INTR_REASON 0x128 #define BWN_INTR_MASK 0x12c #define BWN_RAM_CONTROL 0x130 #define BWN_RAM_DATA 0x134 #define BWN_PS_STATUS 0x140 #define BWN_MAC_HW_CAP 0x15c /* core rev >= 13 */ #define BWN_RF_HWENABLED_HI 0x158 #define BWN_RF_HWENABLED_HI_MASK (1 << 16) #define BWN_SHM_CONTROL 0x160 #define BWN_SHM_DATA 0x164 #define BWN_SHM_DATA_UNALIGNED 0x166 #define BWN_XMITSTAT_0 0x170 #define BWN_XMITSTAT_1 0x174 #define BWN_REV3PLUS_TSF_LOW 0x180 /* core rev >= 3 only */ #define BWN_REV3PLUS_TSF_HIGH 0x184 /* core rev >= 3 only */ #define BWN_TSF_CFP_START 0x18c /* 32-bit DMA */ #define BWN_DMA32_BASE0 0x200 #define BWN_DMA32_BASE1 0x220 #define BWN_DMA32_BASE2 0x240 #define BWN_DMA32_BASE3 0x260 #define BWN_DMA32_BASE4 0x280 #define BWN_DMA32_BASE5 0x2a0 /* 64-bit DMA */ #define BWN_DMA64_BASE0 0x200 #define BWN_DMA64_BASE1 0x240 #define BWN_DMA64_BASE2 0x280 #define BWN_DMA64_BASE3 0x2c0 #define BWN_DMA64_BASE4 0x300 #define BWN_DMA64_BASE5 0x340 /* PIO on core rev < 11 */ #define BWN_PIO_BASE0 0x300 #define BWN_PIO_BASE1 0x310 #define BWN_PIO_BASE2 0x320 #define BWN_PIO_BASE3 0x330 #define BWN_PIO_BASE4 0x340 #define BWN_PIO_BASE5 0x350 #define BWN_PIO_BASE6 0x360 #define BWN_PIO_BASE7 0x370 /* PIO on core rev >= 11 */ #define BWN_PIO11_BASE0 0x200 #define BWN_PIO11_BASE1 0x240 #define BWN_PIO11_BASE2 0x280 #define BWN_PIO11_BASE3 0x2c0 #define BWN_PIO11_BASE4 0x300 #define BWN_PIO11_BASE5 0x340 #define BWN_GPIOCTL 0x06c #define BWN_PHYVER 0x3e0 #define BWN_PHYVER_ANALOG 0xf000 #define BWN_PHYVER_TYPE 0x0f00 #define BWN_PHYVER_VERSION 0x00ff #define BWN_PHY_RADIO 0x3e2 #define BWN_PHY0 0x3e6 #define BWN_CHANNEL 0x3f0 #define BWN_CHANNEL_EXT 0x3f4 #define BWN_RFCTL 0x3f6 #define BWN_RFCTL_ID 0x01 #define BWN_RFDATAHI 0x3f8 #define BWN_RFDATALO 0x3fa #define BWN_PHYCTL 0x3fc #define BWN_PHYDATA 0x3fe #define BWN_MACFILTER_CONTROL 0x420 #define BWN_MACFILTER_DATA 0x422 #define BWN_RCMTA_COUNT 0x43c #define BWN_PSM_PHY_HDR 0x492 /* BWN_PSM_PHY_HDR bits */ #define BWN_PSM_HDR_MAC_PHY_RESET 0x00000001 #define BWN_PSM_HDR_MAC_PHY_CLOCK_EN 0x00000002 #define BWN_PSM_HDR_MAC_PHY_FORCE_CLK 0x00000004 #define BWN_RF_HWENABLED_LO 0x49a #define BWN_RF_HWENABLED_LO_MASK (1 << 4) #define BWN_GPIO_CONTROL 0x49c #define BWN_GPIO_MASK 0x49e #define BWN_TSF_CFP_START_LOW 0x604 #define BWN_TSF_CFP_START_HIGH 0x606 #define BWN_TSF_CFP_PRETBTT 0x612 #define BWN_TSF_CLK_FRAC_LOW 0x62e #define BWN_TSF_CLK_FRAC_HIGH 0x630 #define BWN_RNG 0x65a #define BWN_IFSCTL 0x688 /* Interframe space control */ #define BWN_IFSCTL_USE_EDCF 0x0004 #define BWN_POWERUP_DELAY 0x6a8 #define BWN_BTCOEX_CTL 0x6b4 #define BWN_BTCOEX_TXCTL 0x6b8 #define BWN_UCODE 0x0 #define BWN_HW 0x3 #define BWN_RCMTA 0x4 #define BWN_TSSI_MAX 0x7f #define BWN_SHARED 0x1 #define BWN_SHARED_UCODE_REV 0x0000 #define BWN_SHARED_UCODE_PATCH 0x0002 #define BWN_SHARED_UCODE_DATE 0x0004 #define BWN_SHARED_UCODE_TIME 0x0006 #define BWN_SHARED_COREREV 0x0016 #define BWN_SHARED_ACKCTS_PHYCTL 0x0022 #define BWN_SHARED_RX_PADOFFSET 0x0034 #define BWN_SHARED_UCODESTAT 0x0040 #define BWN_SHARED_UCODESTAT_SUSPEND 3 #define BWN_SHARED_UCODESTAT_SLEEP 4 #define BWN_SHARED_FWCAPS 0x0042 #define BWN_SHARED_SHORT_RETRY_FALLBACK 0x0044 #define BWN_SHARED_LONG_RETRY_FALLBACK 0x0046 #define BWN_SHARED_BEACON_PHYCTL 0x0054 #define BWN_SHARED_KEY_TABLEP 0x0056 #define BWN_SHARED_TSSI_CCK 0x0058 #define BWN_SHARED_HFLO 0x005e /* low hostflag */ #define BWN_SHARED_HFMI 0x0060 /* middle hostflag */ #define BWN_SHARED_HFHI 0x0062 /* high hostflag */ #define BWN_SHARED_RADIO_ATT 0x0064 #define BWN_SHARED_TSSI_OFDM_G 0x0070 #define BWN_SHARED_PROBE_RESP_MAXTIME 0x0074 #define BWN_SHARED_SPU_WAKEUP 0x0094 #define BWN_SHARED_PRETBTT 0x0096 #define BWN_SHARED_CHAN 0x00a0 #define BWN_SHARED_MACHW_L 0x00c0 #define BWN_SHARED_MACHW_H 0x00c2 #define BWN_SHARED_AUTOINC 0x0100 #define BWN_SHARED_PROBE_RESP_PHYCTL 0x0188 #define BWN_SHARED_EDCFQ 0x0240 #define BWN_SHARED_KEYIDX_BLOCK 0x05d4 #define BWN_SHARED_PSM 0x05f4 /* SHM_SHARED tx iq workarounds */ #define BWN_SHM_SH_NPHY_TXIQW0 0x0700 #define BWN_SHM_SH_NPHY_TXIQW1 0x0702 #define BWN_SHM_SH_NPHY_TXIQW2 0x0704 #define BWN_SHM_SH_NPHY_TXIQW3 0x0706 /* SHM_SHARED tx pwr ctrl */ #define BWN_SHM_SH_NPHY_TXPWR_INDX0 0x0708 #define BWN_SHM_SH_NPHY_TXPWR_INDX1 0x070E /* SHM_SCRATCH offsets */ #define BWN_SCRATCH 0x2 #define BWN_SCRATCH_CONT_MIN 0x0003 #define BWN_SCRATCH_CONT_MAX 0x0004 #define BWN_SCRATCH_SHORT_RETRY 0x0006 #define BWN_SCRATCH_LONG_RETRY 0x0007 /* Generic-Interrupt reasons. */ #define BWN_INTR_MAC_SUSPENDED 0x00000001 #define BWN_INTR_BEACON 0x00000002 #define BWN_INTR_TBTT_INDI 0x00000004 #define BWN_INTR_ATIM_END 0x00000020 #define BWN_INTR_PMQ 0x00000040 #define BWN_INTR_MAC_TXERR 0x00000200 #define BWN_INTR_PHY_TXERR 0x00000800 #define BWN_INTR_DMA 0x00008000 #define BWN_INTR_TXFIFO_FLUSH_OK 0x00010000 #define BWN_INTR_NOISESAMPLE_OK 0x00040000 #define BWN_INTR_UCODE_DEBUG 0x08000000 #define BWN_INTR_RFKILL 0x10000000 #define BWN_INTR_TX_OK 0x20000000 #define BWN_INTR_ALL 0xffffffff #define BWN_INTR_MASKTEMPLATE \ (BWN_INTR_TBTT_INDI | BWN_INTR_ATIM_END | BWN_INTR_PMQ | \ BWN_INTR_MAC_TXERR | BWN_INTR_PHY_TXERR | BWN_INTR_DMA | \ BWN_INTR_TXFIFO_FLUSH_OK | BWN_INTR_NOISESAMPLE_OK | \ BWN_INTR_UCODE_DEBUG | BWN_INTR_RFKILL | BWN_INTR_TX_OK) #define BWN_HF_UCODE_ANTDIV_HELPER 0x000000000001ull #define BWN_HF_GPHY_SYM_WORKAROUND 0x000000000002ull #define BWN_HF_4DB_CCK_POWERBOOST 0x000000000008ull #define BWN_HF_BT_COEXIST 0x000000000010ull #define BWN_HF_GPHY_DC_CANCELFILTER 0x000000000020ull #define BWN_HF_PAGAINBOOST_OFDM_ON 0x000000000040ull #define BWN_HF_JAPAN_CHAN14_OFF 0x000000000080ull #define BWN_HF_EDCF 0x000000000100ull #define BWN_HF_TSSI_RESET_PSM_WORKAROUN 0x000000000200ull #define BWN_HF_SLOWCLOCK_REQ_OFF 0x000000000400ull #define BWN_HF_ACI_WORKAROUND 0x000000000800ull #define BWN_HF_2060_RADIO_WORKAROUND 0x000000001000ull #define BWN_HF_FORCE_VCO_RECALC 0x000000040000ull #define BWN_HF_PCI_SLOWCLOCK_WORKAROUND 0x000000080000ull #define BWN_HF_4318_TSSI 0x000000200000ull #define BWN_HF_HW_POWERCTL 0x000000800000ull #define BWN_HF_BT_COEXISTALT 0x000001000000ull #define BWN_HF_SKIP_CFP_UPDATE 0x000004000000ull #define BWN_HF_N40W 0x000008000000ULL /* N PHY 40 MHz workaround (rev >= 13 only) */ #define BWN_HF_ANTSEL 0x000020000000ULL /* Antenna selection (for testing antenna div.) */ #define BWN_HF_BT3COEXT 0x000020000000ULL /* Bluetooth 3-wire coexistence (rev >= 13 only) */ #define BWN_HF_BTCANT 0x000040000000ULL /* Bluetooth coexistence (antenna mode) (rev >= 13 only) */ #define BWN_HF_ANTSELEN 0x000100000000ULL /* Antenna selection enabled (rev >= 13 only) */ #define BWN_HF_ANTSELMODE 0x000200000000ULL /* Antenna selection mode (rev >= 13 only) */ #define BWN_HF_MLADVW 0x001000000000ULL /* N PHY ML ADV workaround (rev >= 13 only) */ #define BWN_HF_PR45960W 0x080000000000ULL #define BWN_TX_PHY_ENC_CCK 0x0000 #define BWN_TX_PHY_ENC_OFDM 0x0001 #define BWN_TX_PHY_SHORTPRMBL 0x0010 #define BWN_TX_PHY_ANT 0x03c0 #define BWN_TX_PHY_ANT0 0x0000 #define BWN_TX_PHY_ANT1 0x0040 #define BWN_TX_PHY_ANT01AUTO 0x00c0 #define BWN_TX_PHY_ANT2 0x0100 #define BWN_TX_PHY_ANT3 0x0200 #define BWN_TX_PHY_TXPWR 0xfc00 #define BWN_TX_MAC_ACK 0x00000001 /* immediate ACK */ #define BWN_TX_MAC_LONGFRAME 0x00000002 #define BWN_TX_MAC_SEND_RTSCTS 0x00000004 #define BWN_TX_MAC_START_MSDU 0x00000008 #define BWN_TX_MAC_HWSEQ 0x00000010 #define BWN_TX_MAC_5GHZ 0x00000080 #define BWN_TX_MAC_SEND_CTSTOSELF 0x00000800 #define BWN_TX_EFT_FB_CCK 0x00 #define BWN_TX_EFT_FB_OFDM 0x01 #define BWN_TX_EFT_RTS_CCK 0x00 #define BWN_TX_EFT_RTS_OFDM 0x04 #define BWN_TX_EFT_RTS_FBCCK 0x00 #define BWN_TX_EFT_RTS_FBOFDM 0x10 #define BWN_PIO_TXCTL 0x00 #define BWN_PIO_TXCTL_WRITELO 0x0001 #define BWN_PIO_TXCTL_WRITEHI 0x0002 #define BWN_PIO_TXCTL_EOF 0x0004 #define BWN_PIO_TXCTL_FRAMEREADY 0x0008 #define BWN_PIO_TXDATA 0x02 #define BWN_PIO_TXQBUFSIZE 0x04 #define BWN_PIO_RXCTL 0x00 #define BWN_PIO_RXCTL_FRAMEREADY 0x0001 #define BWN_PIO_RXCTL_DATAREADY 0x0002 #define BWN_PIO_RXDATA 0x02 #define BWN_PIO8_TXCTL 0x00 #define BWN_PIO8_TXCTL_0_7 0x00000001 #define BWN_PIO8_TXCTL_8_15 0x00000002 #define BWN_PIO8_TXCTL_16_23 0x00000004 #define BWN_PIO8_TXCTL_24_31 0x00000008 #define BWN_PIO8_TXCTL_EOF 0x00000010 #define BWN_PIO8_TXCTL_FRAMEREADY 0x00000080 #define BWN_PIO8_TXDATA 0x04 #define BWN_PIO8_RXCTL 0x00 #define BWN_PIO8_RXCTL_FRAMEREADY 0x00000001 #define BWN_PIO8_RXCTL_DATAREADY 0x00000002 #define BWN_PIO8_RXDATA 0x04 #define BWN_DMA32_TXCTL 0x00 #define BWN_DMA32_TXENABLE 0x00000001 #define BWN_DMA32_TXSUSPEND 0x00000002 #define BWN_DMA32_TXPARITY_DISABLE 0x00000800 #define BWN_DMA32_TXADDREXT_MASK 0x00030000 #define BWN_DMA32_TXADDREXT_SHIFT 16 #define BWN_DMA32_TXRING 0x04 #define BWN_DMA32_TXINDEX 0x08 #define BWN_DMA32_TXSTATUS 0x0c #define BWN_DMA32_TXSTATE 0x0000f000 #define BWN_DMA32_TXSTAT_DISABLED 0x00000000 #define BWN_DMA32_TXSTAT_IDLEWAIT 0x00002000 #define BWN_DMA32_TXSTAT_STOPPED 0x00003000 #define BWN_DMA32_RXCTL 0x10 #define BWN_DMA32_RXENABLE 0x00000001 #define BWN_DMA32_RXFROFF_SHIFT 1 #define BWN_DMA32_RXDIRECTFIFO 0x00000100 #define BWN_DMA32_RXPARITY_DISABLE 0x00000800 #define BWN_DMA32_RXADDREXT_MASK 0x00030000 #define BWN_DMA32_RXADDREXT_SHIFT 16 #define BWN_DMA32_RXRING 0x14 #define BWN_DMA32_RXINDEX 0x18 #define BWN_DMA32_RXSTATUS 0x1c #define BWN_DMA32_RXDPTR 0x00000fff #define BWN_DMA32_RXSTATE 0x0000f000 #define BWN_DMA32_RXSTAT_DISABLED 0x00000000 +#define BWN_DMA32_ADDREXT_MASK 0xC0000000 +#define BWN_DMA32_ADDREXT_SHIFT 30 #define BWN_DMA64_TXCTL 0x00 #define BWN_DMA64_TXENABLE 0x00000001 #define BWN_DMA64_TXSUSPEND 0x00000002 #define BWN_DMA64_TXPARITY_DISABLE 0x00000800 #define BWN_DMA64_TXADDREXT_MASK 0x00030000 #define BWN_DMA64_TXADDREXT_SHIFT 16 #define BWN_DMA64_TXINDEX 0x04 #define BWN_DMA64_TXRINGLO 0x08 #define BWN_DMA64_TXRINGHI 0x0c #define BWN_DMA64_TXSTATUS 0x10 #define BWN_DMA64_TXSTAT 0xf0000000 #define BWN_DMA64_TXSTAT_DISABLED 0x00000000 #define BWN_DMA64_TXSTAT_IDLEWAIT 0x20000000 #define BWN_DMA64_TXSTAT_STOPPED 0x30000000 #define BWN_DMA64_RXCTL 0x20 #define BWN_DMA64_RXENABLE 0x00000001 #define BWN_DMA64_RXFROFF_SHIFT 1 #define BWN_DMA64_RXDIRECTFIFO 0x00000100 #define BWN_DMA64_RXPARITY_DISABLE 0x00000800 #define BWN_DMA64_RXADDREXT_MASK 0x00030000 #define BWN_DMA64_RXADDREXT_SHIFT 16 #define BWN_DMA64_RXINDEX 0x24 #define BWN_DMA64_RXRINGLO 0x28 #define BWN_DMA64_RXRINGHI 0x2c #define BWN_DMA64_RXSTATUS 0x30 #define BWN_DMA64_RXSTATDPTR 0x00001fff #define BWN_DMA64_RXSTAT 0xf0000000 #define BWN_DMA64_RXSTAT_DISABLED 0x00000000 +#define BWN_DMA64_ADDREXT_MASK 0xC000000000000000ULL +#define BWN_DMA64_ADDREXT_SHIFT 62 #define BWN_DMA_RINGMEMSIZE PAGE_SIZE #define BWN_DMA0_RX_FRAMEOFFSET_FW351 30 #define BWN_DMA0_RX_FRAMEOFFSET_FW598 38 #define BWN_TXRING_SLOTS 64 #define BWN_RXRING_SLOTS 64 #define BWN_DMA0_RX_BUFFERSIZE_FW351 (IEEE80211_MAX_LEN + BWN_DMA0_RX_FRAMEOFFSET_FW351) #define BWN_DMA0_RX_BUFFERSIZE_FW598 (IEEE80211_MAX_LEN + BWN_DMA0_RX_FRAMEOFFSET_FW598) #define BWN_PHYROUTE_BASE 0x0000 #define BWN_PHYROUTE_MASK 0x0c00 #define BWN_PHYROUTE_OFDM_GPHY 0x0400 #define BWN_PHYROUTE_EXT_GPHY 0x0800 #define BWN_PHYROUTE_N_BMODE 0x0C00 #define BWN_PHY_CCK(reg) ((reg) | BWN_PHYROUTE_BASE) #define BWN_PHY_N(reg) ((reg) | BWN_PHYROUTE_BASE) /* PHY-N */ #define BWN_PHY_N_BMODE(reg) ((reg) | BWN_PHYROUTE_N_BMODE) #define BWN_PHY_OFDM(reg) ((reg) | BWN_PHYROUTE_OFDM_GPHY) #define BWN_PHY_EXTG(reg) ((reg) | BWN_PHYROUTE_EXT_GPHY) #define BWN_PHY_VERSION_OFDM BWN_PHY_OFDM(0x00) #define BWN_PHY_BBANDCFG BWN_PHY_OFDM(0x01) #define BWN_PHY_BBANDCFG_RXANT 0x180 #define BWN_PHY_BBANDCFG_RXANT_SHIFT 7 #define BWN_PHY_PWRDOWN BWN_PHY_OFDM(0x03) #define BWN_PHY_CRSTHRES1_R1 BWN_PHY_OFDM(0x06) #define BWN_PHY_CRSGAIN_CTL BWN_PHY_OFDM(0x10) #define BWN_PHY_MINPWR_LEVEL BWN_PHY_OFDM(0x16) #define BWN_PHY_OFDMSYNCTHRESH0 BWN_PHY_OFDM(0x17) #define BWN_PHY_IDLEAFTERPKTRXTO BWN_PHY_OFDM(0x1a) #define BWN_PHY_LNAHPFCTL BWN_PHY_OFDM(0x1c) #define BWN_PHY_DCOFFSETTRANSIENT BWN_PHY_OFDM(0x1c) /* for LP */ #define BWN_PHY_PREAMBLECONFIRMTO BWN_PHY_OFDM(0x1e) #define BWN_PHY_CLIPTHRESH BWN_PHY_OFDM(0x1f) #define BWN_PHY_LPFGAINCTL BWN_PHY_OFDM(0x20) #define BWN_PHY_CLIPCTRTHRESH BWN_PHY_OFDM(0x20) /* for LP */ #define BWN_PHY_HIGAINDB BWN_PHY_OFDM(0x23) #define BWN_PHY_LOWGAINDB BWN_PHY_OFDM(0x24) #define BWN_PHY_VERYLOWGAINDB BWN_PHY_OFDM(0x25) #define BWN_PHY_GAINMISMATCH BWN_PHY_OFDM(0x26) #define BWN_PHY_ADIVRELATED BWN_PHY_OFDM(0x27) #define BWN_PHY_GAINDIRECTMISMATCH BWN_PHY_OFDM(0x27) /* for LP */ #define BWN_PHY_CRS0 BWN_PHY_OFDM(0x29) #define BWN_PHY_CRS0_EN 0x4000 #define BWN_PHY_PWR_THRESH1 BWN_PHY_OFDM(0x29) /* for LP */ #define BWN_PHY_ANTDWELL BWN_PHY_OFDM(0x2b) #define BWN_PHY_ANTDWELL_AUTODIV1 0x0100 #define BWN_PHY_DSSS_CONFIRM_CNT BWN_PHY_OFDM(0x2f) /* DSSS Confirm Cnt */ #define BWN_PHY_PEAK_COUNT BWN_PHY_OFDM(0x30) #define BWN_PHY_GAIN_MISMATCH_LIMIT BWN_PHY_OFDM(0x31) #define BWN_PHY_CRS_ED_THRESH BWN_PHY_OFDM(0x32) #define BWN_PHY_INPUT_PWRDB BWN_PHY_OFDM(0x34) #define BWN_PHY_AFE_ADC_CTL_0 BWN_PHY_OFDM(0x36) #define BWN_PHY_AFE_ADC_CTL_1 BWN_PHY_OFDM(0x37) #define BWN_PHY_AFE_DAC_CTL BWN_PHY_OFDM(0x39) #define BWN_PHY_AFE_CTL BWN_PHY_OFDM(0x3a) #define BWN_PHY_AFE_CTL_OVR BWN_PHY_OFDM(0x3b) #define BWN_PHY_AFE_CTL_OVRVAL BWN_PHY_OFDM(0x3c) #define BWN_PHY_AFE_RSSI_CTL_0 BWN_PHY_OFDM(0x3d) #define BWN_PHY_AFE_RSSI_CTL_1 BWN_PHY_OFDM(0x3e) #define BWN_PHY_LP_PHY_CTL BWN_PHY_OFDM(0x48) #define BWN_PHY_ENCORE BWN_PHY_OFDM(0x49) #define BWN_PHY_ENCORE_EN 0x0200 #define BWN_PHY_RESET_CTL BWN_PHY_OFDM(0x4a) #define BWN_PHY_RF_OVERRIDE_0 BWN_PHY_OFDM(0x4c) #define BWN_PHY_RF_OVERRIDE_VAL_0 BWN_PHY_OFDM(0x4d) #define BWN_PHY_TR_LOOKUP_1 BWN_PHY_OFDM(0x4e) #define BWN_PHY_TR_LOOKUP_2 BWN_PHY_OFDM(0x4F) #define BWN_PHY_LMS BWN_PHY_OFDM(0x55) #define BWN_PHY_TABLE_ADDR BWN_PHY_OFDM(0x55) /* for LP */ #define BWN_PHY_TABLEDATALO BWN_PHY_OFDM(0x56) #define BWN_PHY_TABLEDATAHI BWN_PHY_OFDM(0x57) #define BWN_PHY_OFDM61 BWN_PHY_OFDM(0x61) #define BWN_PHY_OFDM61_10 0x0010 #define BWN_PHY_ADC_COMPENSATION_CTL BWN_PHY_OFDM(0x70) #define BWN_PHY_OTABLECTL BWN_PHY_OFDM(0x72) #define BWN_PHY_OTABLENR_SHIFT 10 #define BWN_PHY_OTABLEI BWN_PHY_OFDM(0x73) #define BWN_PHY_OTABLEQ BWN_PHY_OFDM(0x74) #define BWN_PHY_HPWR_TSSICTL BWN_PHY_OFDM(0x78) #define BWN_PHY_IQ_ENABLE_WAIT_TIME_ADDR BWN_PHY_OFDM(0x81) #define BWN_PHY_IQ_NUM_SMPLS_ADDR BWN_PHY_OFDM(0x82) #define BWN_PHY_IQ_ACC_HI_ADDR BWN_PHY_OFDM(0x83) #define BWN_PHY_IQ_ACC_LO_ADDR BWN_PHY_OFDM(0x84) #define BWN_PHY_IQ_I_PWR_ACC_HI_ADDR BWN_PHY_OFDM(0x85) #define BWN_PHY_IQ_I_PWR_ACC_LO_ADDR BWN_PHY_OFDM(0x86) #define BWN_PHY_IQ_Q_PWR_ACC_HI_ADDR BWN_PHY_OFDM(0x87) #define BWN_PHY_IQ_Q_PWR_ACC_LO_ADDR BWN_PHY_OFDM(0x88) #define BWN_PHY_ANTWRSETT BWN_PHY_OFDM(0x8c) #define BWN_PHY_ANTWRSETT_ARXDIV 0x2000 #define BWN_PHY_OFDM9B BWN_PHY_OFDM(0x9b) #define BWN_PHY_A_PHY_CTL_ADDR BWN_PHY_OFDM(0x9c) #define BWN_PHY_RX_COMP_COEFF_S BWN_PHY_OFDM(0x9e) #define BWN_PHY_N1P1GAIN BWN_PHY_OFDM(0xa0) #define BWN_PHY_SMPL_PLAY_COUNT BWN_PHY_OFDM(0xa0) /* for LP */ #define BWN_PHY_P1P2GAIN BWN_PHY_OFDM(0xa1) #define BWN_PHY_SMPL_PLAY_BUFFER_CTL BWN_PHY_OFDM(0xA1) /* for LP */ #define BWN_PHY_N1N2GAIN BWN_PHY_OFDM(0xa2) #define BWN_PHY_4WIRECTL BWN_PHY_OFDM(0xa2) /* for LP */ #define BWN_PHY_TX_PWR_CTL_CMD BWN_PHY_OFDM(0xa4) #define BWN_PHY_TX_PWR_CTL_CMD_MODE 0xe000 #define BWN_PHY_TX_PWR_CTL_CMD_MODE_OFF 0x0000 #define BWN_PHY_TX_PWR_CTL_CMD_MODE_SW 0x8000 #define BWN_PHY_TX_PWR_CTL_CMD_MODE_HW 0xe000 #define BWN_PHY_CCKSHIFTBITS_WA BWN_PHY_OFDM(0xa5) #define BWN_PHY_TX_PWR_CTL_NNUM BWN_PHY_OFDM(0xa5) /* for LP */ #define BWN_PHY_CCKSHIFTBITS BWN_PHY_OFDM(0xa7) #define BWN_PHY_DIVSRCHIDX BWN_PHY_OFDM(0xa8) #define BWN_PHY_DIVP1P2GAIN BWN_PHY_OFDM(0xab) #define BWN_PHY_LP_RF_SIGNAL_LUT BWN_PHY_OFDM(0xac) #define BWN_PHY_DIVSRCHGAINBACK BWN_PHY_OFDM(0xad) #define BWN_PHY_RX_RADIO_CTL BWN_PHY_OFDM(0xae) #define BWN_PHY_RF_OVERRIDE_2 BWN_PHY_OFDM(0xb0) #define BWN_PHY_RF_OVERRIDE_2_VAL BWN_PHY_OFDM(0xb1) #define BWN_PHY_PS_CTL_OVERRIDE_VAL0 BWN_PHY_OFDM(0xB2) #define BWN_PHY_PS_CTL_OVERRIDE_VAL1 BWN_PHY_OFDM(0xB3) #define BWN_PHY_PS_CTL_OVERRIDE_VAL2 BWN_PHY_OFDM(0xB4) #define BWN_PHY_TX_GAIN_CTL_OVERRIDE_VAL BWN_PHY_OFDM(0xB5) #define BWN_PHY_RX_GAIN_CTL_OVERRIDE_VAL BWN_PHY_OFDM(0xB6) #define BWN_PHY_AFE_DDFS BWN_PHY_OFDM(0xb7) #define BWN_PHY_AFE_DDFS_POINTER_INIT BWN_PHY_OFDM(0xB8) #define BWN_PHY_AFE_DDFS_INCR_INIT BWN_PHY_OFDM(0xB9) #define BWN_PHY_TR_LOOKUP_3 BWN_PHY_OFDM(0xbb) #define BWN_PHY_TR_LOOKUP_4 BWN_PHY_OFDM(0xbc) #define BWN_PHY_GPIO_OUTEN BWN_PHY_OFDM(0xbe) #define BWN_PHY_GPIO_SELECT BWN_PHY_OFDM(0xbf) #define BWN_PHY_CRSTHRES1 BWN_PHY_OFDM(0xc0) #define BWN_PHY_CRSTHRES2 BWN_PHY_OFDM(0xc1) #define BWN_PHY_4C3 BWN_PHY_OFDM(0xC3) #define BWN_PHY_4C4 BWN_PHY_OFDM(0xC4) #define BWN_PHY_4C5 BWN_PHY_OFDM(0xC5) #define BWN_PHY_TR_LOOKUP_5 BWN_PHY_OFDM(0xC7) #define BWN_PHY_TR_LOOKUP_6 BWN_PHY_OFDM(0xC8) #define BWN_PHY_TR_LOOKUP_7 BWN_PHY_OFDM(0xC9) #define BWN_PHY_TR_LOOKUP_8 BWN_PHY_OFDM(0xCA) #define BWN_PHY_RF_PWR_OVERRIDE BWN_PHY_OFDM(0xd3) #define BWN_OFDMTAB(number, offset) \ (((number) << BWN_PHY_OTABLENR_SHIFT) | (offset)) #define BWN_OFDMTAB_AGC1 BWN_OFDMTAB(0x00, 0) #define BWN_OFDMTAB_GAIN0 BWN_OFDMTAB(0x00, 0) #define BWN_OFDMTAB_GAINX BWN_OFDMTAB(0x01, 0) #define BWN_OFDMTAB_GAIN1 BWN_OFDMTAB(0x01, 4) #define BWN_OFDMTAB_AGC3 BWN_OFDMTAB(0x02, 0) #define BWN_OFDMTAB_GAIN2 BWN_OFDMTAB(0x02, 3) #define BWN_OFDMTAB_LNAHPFGAIN1 BWN_OFDMTAB(0x03, 0) #define BWN_OFDMTAB_WRSSI BWN_OFDMTAB(0x04, 0) #define BWN_OFDMTAB_NOISESCALE BWN_OFDMTAB(0x05, 0) #define BWN_OFDMTAB_AGC2 BWN_OFDMTAB(0x06, 0) #define BWN_OFDMTAB_ROTOR BWN_OFDMTAB(0x08, 0) #define BWN_OFDMTAB_ADVRETARD BWN_OFDMTAB(0x09, 0) #define BWN_OFDMTAB_DAC BWN_OFDMTAB(0x0c, 0) #define BWN_OFDMTAB_DC BWN_OFDMTAB(0x0e, 7) #define BWN_OFDMTAB_PWRDYN2 BWN_OFDMTAB(0x0e, 12) #define BWN_OFDMTAB_UNKNOWN_0F BWN_OFDMTAB(0x0f, 0) #define BWN_OFDMTAB_UNKNOWN_APHY BWN_OFDMTAB(0x0f, 7) #define BWN_OFDMTAB_LPFGAIN BWN_OFDMTAB(0x0f, 12) #define BWN_OFDMTAB_RSSI BWN_OFDMTAB(0x10, 0) #define BWN_OFDMTAB_UNKNOWN_11 BWN_OFDMTAB(0x11, 4) #define BWN_OFDMTAB_AGC1_R1 BWN_OFDMTAB(0x13, 0) #define BWN_OFDMTAB_GAINX_R1 BWN_OFDMTAB(0x14, 0) #define BWN_OFDMTAB_MINSIGSQ BWN_OFDMTAB(0x14, 0) #define BWN_OFDMTAB_AGC3_R1 BWN_OFDMTAB(0x15, 0) #define BWN_OFDMTAB_WRSSI_R1 BWN_OFDMTAB(0x15, 4) #define BWN_OFDMTAB_DACRFPABB BWN_OFDMTAB(0x16, 0) #define BWN_PHY_CCKBBANDCFG BWN_PHY_CCK(0x01) #define BWN_PHY_PGACTL BWN_PHY_CCK(0x15) #define BWN_PHY_PGACTL_LPF 0x1000 #define BWN_PHY_PGACTL_LOWBANDW 0x0040 #define BWN_PHY_PGACTL_UNKNOWN 0xefa0 #define BWN_PHY_TSSI BWN_PHY_CCK(0x29) #define BWN_PHY_LO_LEAKAGE BWN_PHY_CCK(0x2d) #define BWN_PHY_SYNCPEAKCNT BWN_PHY_CCK(0x30) #define BWN_PHY_SYNCCTL BWN_PHY_CCK(0x35) #define BWN_PHY_DACCTL BWN_PHY_CCK(0x60) #define BWN_PHY_CLASSCTL BWN_PHY_EXTG(0x02) #define BWN_PHY_GTABCTL BWN_PHY_EXTG(0x03) #define BWN_PHY_GTABNR_SHIFT 10 #define BWN_PHY_GTABDATA BWN_PHY_EXTG(0x04) #define BWN_PHY_LO_MASK BWN_PHY_EXTG(0x0f) #define BWN_PHY_LO_CTL BWN_PHY_EXTG(0x10) #define BWN_PHY_RFOVER BWN_PHY_EXTG(0x11) #define BWN_PHY_RFOVERVAL BWN_PHY_EXTG(0x12) #define BWN_PHY_RFOVERVAL_EXTLNA 0x8000 #define BWN_PHY_RFOVERVAL_LNA 0x7000 #define BWN_PHY_RFOVERVAL_LNA_SHIFT 12 #define BWN_PHY_RFOVERVAL_PGA 0x0f00 #define BWN_PHY_RFOVERVAL_PGA_SHIFT 8 #define BWN_PHY_RFOVERVAL_UNK 0x0010 #define BWN_PHY_RFOVERVAL_TRSWRX 0x00e0 #define BWN_PHY_RFOVERVAL_BW 0x0003 #define BWN_PHY_RFOVERVAL_BW_LPF 0x0001 #define BWN_PHY_RFOVERVAL_BW_LBW 0x0002 #define BWN_PHY_ANALOGOVER BWN_PHY_EXTG(0x14) #define BWN_PHY_ANALOGOVERVAL BWN_PHY_EXTG(0x15) #define BWN_GTAB(number, offset) \ (((number) << BWN_PHY_GTABNR_SHIFT) | (offset)) #define BWN_GTAB_ORIGTR BWN_GTAB(0x2e, 0x298) #define BWN_PHY_G_LOCTL 0x0810 #define BWN_PHY_RADIO_BITFIELD 0x0401 #define BWN_PHY_G_CRS 0x0429 #define BWN_PHY_NRSSI_CTRL 0x0803 #define BWN_PHY_NRSSI_DATA 0x0804 #define BWN_FWCAPS_HWCRYPTO 0x0001 #define BWN_FWCAPS_WME 0x0002 #define BWN_MACFILTER_SELF 0x0000 #define BWN_MACFILTER_BSSID 0x0003 #define BWN_SEC_KEYSIZE 16 #define BWN_SEC_ALGO_NONE 0 #define BWN_LED_BEHAVIOUR 0x7f #define BWN_LED_ACTIVELOW 0x80 #define BWN_DEBUGINTR_REASON_REG 63 #define BWN_DEBUGINTR_PANIC 0 #define BWN_DEBUGINTR_DUMP_SHM 1 #define BWN_DEBUGINTR_DUMP_REGS 2 #define BWN_DEBUGINTR_MARKER 3 #define BWN_DEBUGINTR_ACK 0xffff #define BWN_FWPANIC_REASON_REG 3 #define BWN_FWPANIC_DIE 0 #define BWN_FWPANIC_RESTART 1 #define BWN_WATCHDOG_REG 1 #define BWN_CCK_RATE_1MB 0x02 #define BWN_CCK_RATE_2MB 0x04 #define BWN_CCK_RATE_5MB 0x0b #define BWN_CCK_RATE_11MB 0x16 #define BWN_OFDM_RATE_6MB 0x0c #define BWN_OFDM_RATE_9MB 0x12 #define BWN_OFDM_RATE_12MB 0x18 #define BWN_OFDM_RATE_18MB 0x24 #define BWN_OFDM_RATE_24MB 0x30 #define BWN_OFDM_RATE_36MB 0x48 #define BWN_OFDM_RATE_48MB 0x60 #define BWN_OFDM_RATE_54MB 0x6c #define BWN_RX_CHAN_PHYTYPE 0x0007 #define BWN_RX_PHYST0_GAINCTL 0x4000 #define BWN_RX_PHYST0_PLCPHCF 0x0200 #define BWN_RX_PHYST0_PLCPFV 0x0100 #define BWN_RX_PHYST0_SHORTPRMBL 0x0080 #define BWN_RX_PHYST0_OFDM 0x0001 #define BWN_RX_PHYST3_TRSTATE 0x0400 #define BWN_RX_MAC_KEYIDX 0x000007e0 #define BWN_RX_MAC_KEYIDX_SHIFT 5 #define BWN_RX_MAC_DECERR 0x00000010 #define BWN_RX_MAC_DEC 0x00000008 #define BWN_RX_MAC_PADDING 0x00000004 #define BWN_RX_MAC_FCSERR 0x00000001 #define BWN_PS_ON (1 << 0) #define BWN_PS_OFF (1 << 1) #define BWN_PS_AWAKE (1 << 2) #define BWN_PS_ASLEEP (1 << 3) #define BWN_TAB_NOISESCALE_SIZE 27 /* + * SPROM rev 1 locale codes. Later SPROM revisions use a two-character + * country code. + */ +enum { + BWN_SPROM1_CC_WORLDWIDE = 0, + BWN_SPROM1_CC_THAILAND = 1, + BWN_SPROM1_CC_ISRAEL = 2, + BWN_SPROM1_CC_JORDAN = 3, + BWN_SPROM1_CC_CHINA = 4, + BWN_SPROM1_CC_JP = 5, + BWN_SPROM1_CC_USA = 6, + BWN_SPROM1_CC_EUROPE = 7, + BWN_SPROM1_CC_US_LOW = 8, + BWN_SPROM1_CC_JP_HIGH = 9, +}; + +/* * SPROM GPIO */ #define BWN_LED_ACT_LOW 0x80 #define BWN_LED_ACT_MASK 0x7f #define BWN_LED_ACT_OFF 0 #define BWN_LED_ACT_ON 1 #define BWN_LED_ACT_BLINK 2 #define BWN_LED_ACT_RF_ENABLED 3 #define BWN_LED_ACT_5GHZ 4 #define BWN_LED_ACT_2GHZ 5 #define BWN_LED_ACT_11G 6 #define BWN_LED_ACT_BLINK_SLOW 7 #define BWN_LED_ACT_BLINK_POLL 8 #define BWN_LED_ACT_UNKN 9 #define BWN_LED_ACT_ASSOC 10 #define BWN_LED_ACT_NULL 11 -#define BWN_VENDOR_LED_ACT_COMPAQ \ +#define BWN_VENDOR_LED_ACT_HP_COMPAQ \ BWN_LED_ACT_RF_ENABLED, \ BWN_LED_ACT_2GHZ, \ BWN_LED_ACT_5GHZ, \ BWN_LED_ACT_OFF #define BWN_VENDOR_LED_ACT_ASUSTEK \ BWN_LED_ACT_ASSOC, \ BWN_LED_ACT_2GHZ, \ BWN_LED_ACT_5GHZ, \ BWN_LED_ACT_OFF #define BWN_VENDOR_LED_ACT_DEFAULT \ BWN_LED_ACT_BLINK, \ BWN_LED_ACT_2GHZ, \ BWN_LED_ACT_5GHZ, \ BWN_LED_ACT_OFF #define BWN_TAB_ROTOR \ { \ 0xfeb93ffd, 0xfec63ffd, 0xfed23ffd, 0xfedf3ffd, 0xfeec3ffe, \ 0xfef83ffe, 0xff053ffe, 0xff113ffe, 0xff1e3ffe, 0xff2a3fff, \ 0xff373fff, 0xff443fff, 0xff503fff, 0xff5d3fff, 0xff693fff, \ 0xff763fff, 0xff824000, 0xff8f4000, 0xff9b4000, 0xffa84000, \ 0xffb54000, 0xffc14000, 0xffce4000, 0xffda4000, 0xffe74000, \ 0xfff34000, 0x00004000, 0x000d4000, 0x00194000, 0x00264000, \ 0x00324000, 0x003f4000, 0x004b4000, 0x00584000, 0x00654000, \ 0x00714000, 0x007e4000, 0x008a3fff, 0x00973fff, 0x00a33fff, \ 0x00b03fff, 0x00bc3fff, 0x00c93fff, 0x00d63fff, 0x00e23ffe, \ 0x00ef3ffe, 0x00fb3ffe, 0x01083ffe, 0x01143ffe, 0x01213ffd, \ 0x012e3ffd, 0x013a3ffd, 0x01473ffd \ } #define BWN_TAB_RETARD \ { \ 0xdb93cb87, 0xd666cf64, 0xd1fdd358, 0xcda6d826, 0xca38dd9f, \ 0xc729e2b4, 0xc469e88e, 0xc26aee2b, 0xc0def46c, 0xc073fa62, \ 0xc01d00d5, 0xc0760743, 0xc1560d1e, 0xc2e51369, 0xc4ed18ff, \ 0xc7ac1ed7, 0xcb2823b2, 0xcefa28d9, 0xd2f62d3f, 0xd7bb3197, \ 0xdce53568, 0xe1fe3875, 0xe7d13b35, 0xed663d35, 0xf39b3ec4, \ 0xf98e3fa7, 0x00004000, 0x06723fa7, 0x0c653ec4, 0x129a3d35, \ 0x182f3b35, 0x1e023875, 0x231b3568, 0x28453197, 0x2d0a2d3f, \ 0x310628d9, 0x34d823b2, 0x38541ed7, 0x3b1318ff, 0x3d1b1369, \ 0x3eaa0d1e, 0x3f8a0743, 0x3fe300d5, 0x3f8dfa62, 0x3f22f46c, \ 0x3d96ee2b, 0x3b97e88e, 0x38d7e2b4, 0x35c8dd9f, 0x325ad826, \ 0x2e03d358, 0x299acf64, 0x246dcb87, \ } #define BWN_TAB_FINEFREQ_G \ { \ 0x0089, 0x02e9, 0x0409, 0x04e9, 0x05a9, 0x0669, 0x0709, 0x0789, \ 0x0829, 0x08a9, 0x0929, 0x0989, 0x0a09, 0x0a69, 0x0ac9, 0x0b29, \ 0x0ba9, 0x0be9, 0x0c49, 0x0ca9, 0x0d09, 0x0d69, 0x0da9, 0x0e09, \ 0x0e69, 0x0ea9, 0x0f09, 0x0f49, 0x0fa9, 0x0fe9, 0x1029, 0x1089, \ 0x10c9, 0x1109, 0x1169, 0x11a9, 0x11e9, 0x1229, 0x1289, 0x12c9, \ 0x1309, 0x1349, 0x1389, 0x13c9, 0x1409, 0x1449, 0x14a9, 0x14e9, \ 0x1529, 0x1569, 0x15a9, 0x15e9, 0x1629, 0x1669, 0x16a9, 0x16e8, \ 0x1728, 0x1768, 0x17a8, 0x17e8, 0x1828, 0x1868, 0x18a8, 0x18e8, \ 0x1928, 0x1968, 0x19a8, 0x19e8, 0x1a28, 0x1a68, 0x1aa8, 0x1ae8, \ 0x1b28, 0x1b68, 0x1ba8, 0x1be8, 0x1c28, 0x1c68, 0x1ca8, 0x1ce8, \ 0x1d28, 0x1d68, 0x1dc8, 0x1e08, 0x1e48, 0x1e88, 0x1ec8, 0x1f08, \ 0x1f48, 0x1f88, 0x1fe8, 0x2028, 0x2068, 0x20a8, 0x2108, 0x2148, \ 0x2188, 0x21c8, 0x2228, 0x2268, 0x22c8, 0x2308, 0x2348, 0x23a8, \ 0x23e8, 0x2448, 0x24a8, 0x24e8, 0x2548, 0x25a8, 0x2608, 0x2668, \ 0x26c8, 0x2728, 0x2787, 0x27e7, 0x2847, 0x28c7, 0x2947, 0x29a7, \ 0x2a27, 0x2ac7, 0x2b47, 0x2be7, 0x2ca7, 0x2d67, 0x2e47, 0x2f67, \ 0x3247, 0x3526, 0x3646, 0x3726, 0x3806, 0x38a6, 0x3946, 0x39e6, \ 0x3a66, 0x3ae6, 0x3b66, 0x3bc6, 0x3c45, 0x3ca5, 0x3d05, 0x3d85, \ 0x3de5, 0x3e45, 0x3ea5, 0x3ee5, 0x3f45, 0x3fa5, 0x4005, 0x4045, \ 0x40a5, 0x40e5, 0x4145, 0x4185, 0x41e5, 0x4225, 0x4265, 0x42c5, \ 0x4305, 0x4345, 0x43a5, 0x43e5, 0x4424, 0x4464, 0x44c4, 0x4504, \ 0x4544, 0x4584, 0x45c4, 0x4604, 0x4644, 0x46a4, 0x46e4, 0x4724, \ 0x4764, 0x47a4, 0x47e4, 0x4824, 0x4864, 0x48a4, 0x48e4, 0x4924, \ 0x4964, 0x49a4, 0x49e4, 0x4a24, 0x4a64, 0x4aa4, 0x4ae4, 0x4b23, \ 0x4b63, 0x4ba3, 0x4be3, 0x4c23, 0x4c63, 0x4ca3, 0x4ce3, 0x4d23, \ 0x4d63, 0x4da3, 0x4de3, 0x4e23, 0x4e63, 0x4ea3, 0x4ee3, 0x4f23, \ 0x4f63, 0x4fc3, 0x5003, 0x5043, 0x5083, 0x50c3, 0x5103, 0x5143, \ 0x5183, 0x51e2, 0x5222, 0x5262, 0x52a2, 0x52e2, 0x5342, 0x5382, \ 0x53c2, 0x5402, 0x5462, 0x54a2, 0x5502, 0x5542, 0x55a2, 0x55e2, \ 0x5642, 0x5682, 0x56e2, 0x5722, 0x5782, 0x57e1, 0x5841, 0x58a1, \ 0x5901, 0x5961, 0x59c1, 0x5a21, 0x5aa1, 0x5b01, 0x5b81, 0x5be1, \ 0x5c61, 0x5d01, 0x5d80, 0x5e20, 0x5ee0, 0x5fa0, 0x6080, 0x61c0, \ } #define BWN_TAB_NOISE_G1 \ { \ 0x013c, 0x01f5, 0x031a, 0x0631, 0x0001, 0x0001, 0x0001, 0x0001, \ } #define BWN_TAB_NOISE_G2 \ { \ 0x5484, 0x3c40, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, \ } #define BWN_TAB_NOISESCALE_G1 \ { \ 0x6c77, 0x5162, 0x3b40, 0x3335, 0x2f2d, 0x2a2a, 0x2527, 0x1f21, \ 0x1a1d, 0x1719, 0x1616, 0x1414, 0x1414, 0x1400, 0x1414, 0x1614, \ 0x1716, 0x1a19, 0x1f1d, 0x2521, 0x2a27, 0x2f2a, 0x332d, 0x3b35, \ 0x5140, 0x6c62, 0x0077, \ } #define BWN_TAB_NOISESCALE_G2 \ { \ 0xd8dd, 0xcbd4, 0xbcc0, 0xb6b7, 0xb2b0, 0xadad, 0xa7a9, 0x9fa1, \ 0x969b, 0x9195, 0x8f8f, 0x8a8a, 0x8a8a, 0x8a00, 0x8a8a, 0x8f8a, \ 0x918f, 0x9695, 0x9f9b, 0xa7a1, 0xada9, 0xb2ad, 0xb6b0, 0xbcb7, \ 0xcbc0, 0xd8d4, 0x00dd, \ } #define BWN_TAB_NOISESCALE_G3 \ { \ 0xa4a4, 0xa4a4, 0xa4a4, 0xa4a4, 0xa4a4, 0xa4a4, 0xa4a4, 0xa4a4, \ 0xa4a4, 0xa4a4, 0xa4a4, 0xa4a4, 0xa4a4, 0xa400, 0xa4a4, 0xa4a4, \ 0xa4a4, 0xa4a4, 0xa4a4, 0xa4a4, 0xa4a4, 0xa4a4, 0xa4a4, 0xa4a4, \ 0xa4a4, 0xa4a4, 0x00a4, \ } #define BWN_TAB_SIGMASQR2 \ { \ 0x00de, 0x00dc, 0x00da, 0x00d8, 0x00d6, 0x00d4, 0x00d2, 0x00cf, \ 0x00cd, 0x00ca, 0x00c7, 0x00c4, 0x00c1, 0x00be, 0x00be, 0x00be, \ 0x00be, 0x00be, 0x00be, 0x00be, 0x00be, 0x00be, 0x00be, 0x00be, \ 0x00be, 0x00be, 0x0000, 0x00be, 0x00be, 0x00be, 0x00be, 0x00be, \ 0x00be, 0x00be, 0x00be, 0x00be, 0x00be, 0x00be, 0x00be, 0x00be, \ 0x00c1, 0x00c4, 0x00c7, 0x00ca, 0x00cd, 0x00cf, 0x00d2, 0x00d4, \ 0x00d6, 0x00d8, 0x00da, 0x00dc, 0x00de, \ } #define BWN_PHY_G_TSSI2DBM_TABLE \ { \ 77, 77, 77, 76, 76, 76, 75, 75, 74, 74, 73, 73, 73, 72, 72, 71, \ 71, 70, 70, 69, 68, 68, 67, 67, 66, 65, 65, 64, 63, 63, 62, 61, \ 60, 59, 58, 57, 56, 55, 54, 53, 52, 50, 49, 47, 45, 43, 40, 37, \ 33, 28, 22, 14, 5, -7, -20, -20, -20, -20, -20, -20, -20, -20, \ -20, -20 \ } #define BWN_PHY_G_RF_CHANNELS \ { \ 12, 17, 22, 27, 32, 37, 42, 47, 52, 57, 62, 67, 72, 84, \ } #define BWN_BITREV_TABLE \ { \ 0x00, 0x80, 0x40, 0xc0, 0x20, 0xa0, 0x60, 0xe0, 0x10, 0x90, \ 0x50, 0xd0, 0x30, 0xb0, 0x70, 0xf0, 0x08, 0x88, 0x48, 0xc8, \ 0x28, 0xa8, 0x68, 0xe8, 0x18, 0x98, 0x58, 0xd8, 0x38, 0xb8, \ 0x78, 0xf8, 0x04, 0x84, 0x44, 0xc4, 0x24, 0xa4, 0x64, 0xe4, \ 0x14, 0x94, 0x54, 0xd4, 0x34, 0xb4, 0x74, 0xf4, 0x0c, 0x8c, \ 0x4c, 0xcc, 0x2c, 0xac, 0x6c, 0xec, 0x1c, 0x9c, 0x5c, 0xdc, \ 0x3c, 0xbc, 0x7c, 0xfc, 0x02, 0x82, 0x42, 0xc2, 0x22, 0xa2, \ 0x62, 0xe2, 0x12, 0x92, 0x52, 0xd2, 0x32, 0xb2, 0x72, 0xf2, \ 0x0a, 0x8a, 0x4a, 0xca, 0x2a, 0xaa, 0x6a, 0xea, 0x1a, 0x9a, \ 0x5a, 0xda, 0x3a, 0xba, 0x7a, 0xfa, 0x06, 0x86, 0x46, 0xc6, \ 0x26, 0xa6, 0x66, 0xe6, 0x16, 0x96, 0x56, 0xd6, 0x36, 0xb6, \ 0x76, 0xf6, 0x0e, 0x8e, 0x4e, 0xce, 0x2e, 0xae, 0x6e, 0xee, \ 0x1e, 0x9e, 0x5e, 0xde, 0x3e, 0xbe, 0x7e, 0xfe, 0x01, 0x81, \ 0x41, 0xc1, 0x21, 0xa1, 0x61, 0xe1, 0x11, 0x91, 0x51, 0xd1, \ 0x31, 0xb1, 0x71, 0xf1, 0x09, 0x89, 0x49, 0xc9, 0x29, 0xa9, \ 0x69, 0xe9, 0x19, 0x99, 0x59, 0xd9, 0x39, 0xb9, 0x79, 0xf9, \ 0x05, 0x85, 0x45, 0xc5, 0x25, 0xa5, 0x65, 0xe5, 0x15, 0x95, \ 0x55, 0xd5, 0x35, 0xb5, 0x75, 0xf5, 0x0d, 0x8d, 0x4d, 0xcd, \ 0x2d, 0xad, 0x6d, 0xed, 0x1d, 0x9d, 0x5d, 0xdd, 0x3d, 0xbd, \ 0x7d, 0xfd, 0x03, 0x83, 0x43, 0xc3, 0x23, 0xa3, 0x63, 0xe3, \ 0x13, 0x93, 0x53, 0xd3, 0x33, 0xb3, 0x73, 0xf3, 0x0b, 0x8b, \ 0x4b, 0xcb, 0x2b, 0xab, 0x6b, 0xeb, 0x1b, 0x9b, 0x5b, 0xdb, \ 0x3b, 0xbb, 0x7b, 0xfb, 0x07, 0x87, 0x47, 0xc7, 0x27, 0xa7, \ 0x67, 0xe7, 0x17, 0x97, 0x57, 0xd7, 0x37, 0xb7, 0x77, 0xf7, \ 0x0f, 0x8f, 0x4f, 0xcf, 0x2f, 0xaf, 0x6f, 0xef, 0x1f, 0x9f, \ 0x5f, 0xdf, 0x3f, 0xbf, 0x7f, 0xff \ } /* * LP PHY */ #define BWN_TAB_TYPEMASK 0xf0000000 #define BWN_TAB_GETTYPE(v) ((v) & BWN_TAB_TYPEMASK) #define BWN_TAB_GETOFFSET(v) ((v) & ~BWN_TAB_TYPEMASK) #define BWN_TAB_8BIT 0x10000000 #define BWN_TAB_16BIT 0x20000000 #define BWN_TAB_32BIT 0x30000000 #define BWN_TAB_1(table, offset) \ (((table) << 10) | (offset) | BWN_TAB_8BIT) #define BWN_TAB_2(table, offset) \ (((table) << 10) | (offset) | BWN_TAB_16BIT) #define BWN_TAB_4(table, offset) \ (((table) << 10) | (offset) | BWN_TAB_32BIT) #define BWN_LP_RADIO(radio_reg) (radio_reg) #define BWN_LP_NORTH(radio_reg) BWN_LP_RADIO(radio_reg) #define BWN_LP_SOUTH(radio_reg) BWN_LP_RADIO((radio_reg) | 0x4000) #define BWN_B2062_N_COM1 BWN_LP_NORTH(0x000) #define BWN_B2062_N_COM2 BWN_LP_NORTH(0x002) #define BWN_B2062_N_COM4 BWN_LP_NORTH(0x004) #define BWN_B2062_N_PDNCTL0 BWN_LP_NORTH(0x010) #define BWN_B2062_N_PDNCTL1 BWN_LP_NORTH(0x011) #define BWN_B2062_N_PDNCTL3 BWN_LP_NORTH(0x013) #define BWN_B2062_N_PDNCTL4 BWN_LP_NORTH(0x014) #define BWN_B2062_N_LGENC BWN_LP_NORTH(0x017) #define BWN_B2062_N_LGENATUNE0 BWN_LP_NORTH(0x01E) #define BWN_B2062_N_LGENATUNE2 BWN_LP_NORTH(0x020) #define BWN_B2062_N_LGENATUNE3 BWN_LP_NORTH(0x021) #define BWN_B2062_N_LGENACTL3 BWN_LP_NORTH(0x022) #define BWN_B2062_N_LGENACTL5 BWN_LP_NORTH(0x024) #define BWN_B2062_N_LGENACTL6 BWN_LP_NORTH(0x025) #define BWN_B2062_N_LGENACTL7 BWN_LP_NORTH(0x026) #define BWN_B2062_N_RXA_CTL1 BWN_LP_NORTH(0x028) #define BWN_B2062_N_RXBB_CTL0 BWN_LP_NORTH(0x02F) #define BWN_B2062_N_RXBB_GAIN1 BWN_LP_NORTH(0x033) #define BWN_B2062_N_RXBB_GAIN2 BWN_LP_NORTH(0x034) #define BWN_B2062_N_RXBB_CALIB2 BWN_LP_NORTH(0x03A) #define BWN_B2062_N_TXCTL3 BWN_LP_NORTH(0x048) #define BWN_B2062_N_TXCTL4 BWN_LP_NORTH(0x049) #define BWN_B2062_N_TXCTL5 BWN_LP_NORTH(0x04A) #define BWN_B2062_N_TXCTL6 BWN_LP_NORTH(0x04B) #define BWN_B2062_N_TXCTL_A BWN_LP_NORTH(0x04F) #define BWN_B2062_N_TX_TUNE BWN_LP_NORTH(0x052) #define BWN_B2062_N_TX_PAD BWN_LP_NORTH(0x053) #define BWN_B2062_N_TX_PGA BWN_LP_NORTH(0x054) #define BWN_B2062_N_TSSI_CTL0 BWN_LP_NORTH(0x057) #define BWN_B2062_N_CALIB_TS BWN_LP_NORTH(0x05D) #define BWN_B2062_S_COM4 BWN_LP_SOUTH(0x004) #define BWN_B2062_S_PDS_CTL0 BWN_LP_SOUTH(0x010) #define BWN_B2062_S_BG_CTL1 BWN_LP_SOUTH(0x015) #define BWN_B2062_S_LGENG_CTL0 BWN_LP_SOUTH(0x017) #define BWN_B2062_S_LGENG_CTL1 BWN_LP_SOUTH(0x018) #define BWN_B2062_S_LGENG_CTL8 BWN_LP_SOUTH(0x01F) #define BWN_B2062_S_LGENG_CTL10 BWN_LP_SOUTH(0x021) #define BWN_B2062_S_RFPLLCTL0 BWN_LP_SOUTH(0x034) #define BWN_B2062_S_RFPLLCTL1 BWN_LP_SOUTH(0x035) #define BWN_B2062_S_RFPLLCTL2 BWN_LP_SOUTH(0x036) #define BWN_B2062_S_RFPLLCTL3 BWN_LP_SOUTH(0x037) #define BWN_B2062_S_RFPLLCTL5 BWN_LP_SOUTH(0x039) #define BWN_B2062_S_RFPLLCTL6 BWN_LP_SOUTH(0x03A) #define BWN_B2062_S_RFPLLCTL7 BWN_LP_SOUTH(0x03B) #define BWN_B2062_S_RFPLLCTL8 BWN_LP_SOUTH(0x03C) #define BWN_B2062_S_RFPLLCTL9 BWN_LP_SOUTH(0x03D) #define BWN_B2062_S_RFPLLCTL10 BWN_LP_SOUTH(0x03E) #define BWN_B2062_S_RFPLLCTL11 BWN_LP_SOUTH(0x03F) #define BWN_B2062_S_RFPLLCTL12 BWN_LP_SOUTH(0x040) #define BWN_B2062_S_RFPLLCTL13 BWN_LP_SOUTH(0x041) #define BWN_B2062_S_RFPLLCTL14 BWN_LP_SOUTH(0x042) #define BWN_B2062_S_RFPLLCTL18 BWN_LP_SOUTH(0x046) #define BWN_B2062_S_RFPLLCTL19 BWN_LP_SOUTH(0x047) #define BWN_B2062_S_RFPLLCTL21 BWN_LP_SOUTH(0x049) #define BWN_B2062_S_RFPLLCTL22 BWN_LP_SOUTH(0x04A) #define BWN_B2062_S_RFPLLCTL23 BWN_LP_SOUTH(0x04B) #define BWN_B2062_S_RFPLLCTL24 BWN_LP_SOUTH(0x04C) #define BWN_B2062_S_RFPLLCTL25 BWN_LP_SOUTH(0x04D) #define BWN_B2062_S_RFPLLCTL26 BWN_LP_SOUTH(0x04E) #define BWN_B2062_S_RFPLLCTL27 BWN_LP_SOUTH(0x04F) #define BWN_B2062_S_RFPLLCTL28 BWN_LP_SOUTH(0x050) #define BWN_B2062_S_RFPLLCTL29 BWN_LP_SOUTH(0x051) #define BWN_B2062_S_RFPLLCTL30 BWN_LP_SOUTH(0x052) #define BWN_B2062_S_RFPLLCTL31 BWN_LP_SOUTH(0x053) #define BWN_B2062_S_RFPLLCTL33 BWN_LP_SOUTH(0x055) #define BWN_B2062_S_RFPLLCTL34 BWN_LP_SOUTH(0x056) #define BWN_B2062_S_RXG_CNT8 BWN_LP_SOUTH(0x05F) #define BWN_B2062_S_RXG_CNT16 BWN_LP_SOUTH(0x067) #define BWN_B2063_COM1 BWN_LP_RADIO(0x000) #define BWN_B2063_COM8 BWN_LP_RADIO(0x008) #define BWN_B2063_COM10 BWN_LP_RADIO(0x00A) #define BWN_B2063_COM15 BWN_LP_RADIO(0x00F) #define BWN_B2063_COM16 BWN_LP_RADIO(0x010) #define BWN_B2063_COM17 BWN_LP_RADIO(0x011) #define BWN_B2063_COM18 BWN_LP_RADIO(0x012) #define BWN_B2063_COM19 BWN_LP_RADIO(0x013) #define BWN_B2063_COM20 BWN_LP_RADIO(0x014) #define BWN_B2063_COM21 BWN_LP_RADIO(0x015) #define BWN_B2063_COM22 BWN_LP_RADIO(0x016) #define BWN_B2063_COM23 BWN_LP_RADIO(0x017) #define BWN_B2063_COM24 BWN_LP_RADIO(0x018) #define BWN_B2063_PLL_SP1 BWN_LP_RADIO(0x01A) #define BWN_B2063_PLL_SP2 BWN_LP_RADIO(0x01B) #define BWN_B2063_LOGEN_SP1 BWN_LP_RADIO(0x01C) #define BWN_B2063_LOGEN_SP2 BWN_LP_RADIO(0x01D) #define BWN_B2063_LOGEN_SP4 BWN_LP_RADIO(0x01F) #define BWN_B2063_LOGEN_SP5 BWN_LP_RADIO(0x020) #define BWN_B2063_G_RX_SP1 BWN_LP_RADIO(0x021) #define BWN_B2063_G_RX_SP2 BWN_LP_RADIO(0x022) #define BWN_B2063_G_RX_SP3 BWN_LP_RADIO(0x023) #define BWN_B2063_G_RX_SP7 BWN_LP_RADIO(0x027) #define BWN_B2063_G_RX_SP10 BWN_LP_RADIO(0x02A) #define BWN_B2063_A_RX_SP1 BWN_LP_RADIO(0x02C) #define BWN_B2063_A_RX_SP2 BWN_LP_RADIO(0x02D) #define BWN_B2063_A_RX_SP7 BWN_LP_RADIO(0x032) #define BWN_B2063_RX_BB_SP3 BWN_LP_RADIO(0x035) #define BWN_B2063_RX_BB_SP4 BWN_LP_RADIO(0x036) #define BWN_B2063_RX_BB_SP8 BWN_LP_RADIO(0x03A) #define BWN_B2063_TX_RF_SP3 BWN_LP_RADIO(0x03D) #define BWN_B2063_TX_RF_SP4 BWN_LP_RADIO(0x03E) #define BWN_B2063_TX_RF_SP6 BWN_LP_RADIO(0x040) #define BWN_B2063_TX_RF_SP9 BWN_LP_RADIO(0x043) #define BWN_B2063_PA_SP1 BWN_LP_RADIO(0x04C) #define BWN_B2063_PA_SP2 BWN_LP_RADIO(0x04D) #define BWN_B2063_PA_SP3 BWN_LP_RADIO(0x04E) #define BWN_B2063_PA_SP4 BWN_LP_RADIO(0x04F) #define BWN_B2063_PA_SP7 BWN_LP_RADIO(0x052) #define BWN_B2063_TX_BB_SP1 BWN_LP_RADIO(0x053) #define BWN_B2063_TX_BB_SP3 BWN_LP_RADIO(0x055) #define BWN_B2063_REG_SP1 BWN_LP_RADIO(0x056) #define BWN_B2063_BANDGAP_CTL1 BWN_LP_RADIO(0x057) #define BWN_B2063_RC_CALIB_CTL1 BWN_LP_RADIO(0x05A) #define BWN_B2063_RC_CALIB_CTL2 BWN_LP_RADIO(0x05B) #define BWN_B2063_RC_CALIB_CTL3 BWN_LP_RADIO(0x05C) #define BWN_B2063_RC_CALIB_CTL4 BWN_LP_RADIO(0x05D) #define BWN_B2063_RC_CALIB_CTL5 BWN_LP_RADIO(0x05E) #define BWN_B2063_RC_CALIB_CTL6 BWN_LP_RADIO(0x05F) #define BWN_B2063_JTAG_CALNRST BWN_LP_RADIO(0x064) #define BWN_B2063_JTAG_CP2 BWN_LP_RADIO(0x068) #define BWN_B2063_JTAG_CP3 BWN_LP_RADIO(0x069) #define BWN_B2063_JTAG_LF1 BWN_LP_RADIO(0x06C) #define BWN_B2063_JTAG_LF2 BWN_LP_RADIO(0x06D) #define BWN_B2063_JTAG_LF3 BWN_LP_RADIO(0x06E) #define BWN_B2063_JTAG_LF4 BWN_LP_RADIO(0x06F) #define BWN_B2063_JTAG_SG1 BWN_LP_RADIO(0x070) #define BWN_B2063_JTAG_SG2 BWN_LP_RADIO(0x071) #define BWN_B2063_JTAG_SG3 BWN_LP_RADIO(0x072) #define BWN_B2063_JTAG_SG4 BWN_LP_RADIO(0x073) #define BWN_B2063_JTAG_VCO1 BWN_LP_RADIO(0x075) #define BWN_B2063_JTAG_VCO2 BWN_LP_RADIO(0x076) #define BWN_B2063_JTAG_VCO_CALIB3 BWN_LP_RADIO(0x079) #define BWN_B2063_JTAG_VCO_CALIB5 BWN_LP_RADIO(0x07B) #define BWN_B2063_JTAG_VCO_CALIB6 BWN_LP_RADIO(0x07C) #define BWN_B2063_JTAG_VCO_CALIB7 BWN_LP_RADIO(0x07D) #define BWN_B2063_JTAG_VCO_CALIB8 BWN_LP_RADIO(0x07E) #define BWN_B2063_JTAG_XTAL_12 BWN_LP_RADIO(0x081) #define BWN_B2063_LOGEN_RCCR1 BWN_LP_RADIO(0x0A1) #define BWN_B2063_LOGEN_VCOBUF1 BWN_LP_RADIO(0x0A2) #define BWN_B2063_LOGEN_MIXER2 BWN_LP_RADIO(0x0A4) #define BWN_B2063_LOGEN_BUF2 BWN_LP_RADIO(0x0A6) #define BWN_B2063_G_RX_MIX3 BWN_LP_RADIO(0x0C4) #define BWN_B2063_G_RX_MIX4 BWN_LP_RADIO(0x0C5) #define BWN_B2063_A_RX_1ST2 BWN_LP_RADIO(0x0CF) #define BWN_B2063_A_RX_1ST3 BWN_LP_RADIO(0x0D0) #define BWN_B2063_A_RX_2ND1 BWN_LP_RADIO(0x0D3) #define BWN_B2063_A_RX_2ND4 BWN_LP_RADIO(0x0D6) #define BWN_B2063_A_RX_2ND7 BWN_LP_RADIO(0x0D9) #define BWN_B2063_A_RX_PS6 BWN_LP_RADIO(0x0DF) #define BWN_B2063_A_RX_MIX4 BWN_LP_RADIO(0x0E3) #define BWN_B2063_A_RX_MIX5 BWN_LP_RADIO(0x0E4) #define BWN_B2063_A_RX_MIX6 BWN_LP_RADIO(0x0E5) #define BWN_B2063_RX_TIA_CTL1 BWN_LP_RADIO(0x0EC) #define BWN_B2063_RX_TIA_CTL3 BWN_LP_RADIO(0x0EE) #define BWN_B2063_RX_BB_CTL2 BWN_LP_RADIO(0x0F3) #define BWN_B2063_TX_RF_CTL2 BWN_LP_RADIO(0x100) #define BWN_B2063_TX_RF_CTL5 BWN_LP_RADIO(0x103) #define BWN_B2063_PA_CTL1 BWN_LP_RADIO(0x10B) #define BWN_B2063_PA_CTL11 BWN_LP_RADIO(0x115) #define BWN_B2063_VREG_CTL1 BWN_LP_RADIO(0x11D) /* N-PHY, etc TX configuration */ #define BWN_TXH_PHY1_BW 0x0007 /* Bandwidth */ #define BWN_TXH_PHY1_BW_10 0x0000 /* 10 MHz */ #define BWN_TXH_PHY1_BW_10U 0x0001 /* 10 MHz upper */ #define BWN_TXH_PHY1_BW_20 0x0002 /* 20 MHz */ #define BWN_TXH_PHY1_BW_20U 0x0003 /* 20 MHz upper */ #define BWN_TXH_PHY1_BW_40 0x0004 /* 40 MHz */ #define BWN_TXH_PHY1_BW_40DUP 0x0005 /* 40 MHz duplicate */ #define BWN_TXH_PHY1_MODE 0x0038 /* Mode */ #define BWN_TXH_PHY1_MODE_SISO 0x0000 /* SISO */ #define BWN_TXH_PHY1_MODE_CDD 0x0008 /* CDD */ #define BWN_TXH_PHY1_MODE_STBC 0x0010 /* STBC */ #define BWN_TXH_PHY1_MODE_SDM 0x0018 /* SDM */ #define BWN_TXH_PHY1_CRATE 0x0700 /* Coding rate */ #define BWN_TXH_PHY1_CRATE_1_2 0x0000 /* 1/2 */ #define BWN_TXH_PHY1_CRATE_2_3 0x0100 /* 2/3 */ #define BWN_TXH_PHY1_CRATE_3_4 0x0200 /* 3/4 */ #define BWN_TXH_PHY1_CRATE_4_5 0x0300 /* 4/5 */ #define BWN_TXH_PHY1_CRATE_5_6 0x0400 /* 5/6 */ #define BWN_TXH_PHY1_CRATE_7_8 0x0600 /* 7/8 */ #define BWN_TXH_PHY1_MODUL 0x3800 /* Modulation scheme */ #define BWN_TXH_PHY1_MODUL_BPSK 0x0000 /* BPSK */ #define BWN_TXH_PHY1_MODUL_QPSK 0x0800 /* QPSK */ #define BWN_TXH_PHY1_MODUL_QAM16 0x1000 /* QAM16 */ #define BWN_TXH_PHY1_MODUL_QAM64 0x1800 /* QAM64 */ #define BWN_TXH_PHY1_MODUL_QAM256 0x2000 /* QAM256 */ #endif /* !_IF_BWNREG_H */ Index: head/sys/dev/bwn/if_bwnvar.h =================================================================== --- head/sys/dev/bwn/if_bwnvar.h (revision 328911) +++ head/sys/dev/bwn/if_bwnvar.h (revision 328912) @@ -1,1167 +1,1180 @@ /*- * SPDX-License-Identifier: BSD-2-Clause-FreeBSD * * Copyright (c) 2009-2010 Weongyo Jeong * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer, * without modification. * 2. Redistributions in binary form must reproduce at minimum a disclaimer * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any * redistribution must be conditioned upon including a substantially * similar Disclaimer requirement for further binary redistribution. * * NO WARRANTY * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF * THE POSSIBILITY OF SUCH DAMAGES. * * $FreeBSD$ */ #ifndef _IF_BWNVAR_H #define _IF_BWNVAR_H -#include "if_bwn_siba.h" +#include struct bwn_softc; struct bwn_mac; -extern driver_t bwn_driver; - -int bwn_attach(device_t dev); -int bwn_detach(device_t dev); - #define N(a) (sizeof(a) / sizeof(a[0])) #define BWN_ALIGN 0x1000 -#define BWN_BUS_SPACE_MAXADDR_30BIT 0x3fffffff #define BWN_RETRY_SHORT 7 #define BWN_RETRY_LONG 4 #define BWN_STAID_MAX 64 #define BWN_TXPWR_IGNORE_TIME (1 << 0) #define BWN_TXPWR_IGNORE_TSSI (1 << 1) #define BWN_HAS_TXMAG(phy) \ (((phy)->rev >= 2) && ((phy)->rf_ver == 0x2050) && \ ((phy)->rf_rev == 8)) #define BWN_HAS_LOOPBACK(phy) \ (((phy)->rev > 1) || ((phy)->gmode)) #define BWN_TXERROR_MAX 1000 #define BWN_GETTIME(v) do { \ struct timespec ts; \ nanouptime(&ts); \ (v) = ts.tv_nsec / 1000000 + ts.tv_sec * 1000; \ } while (0) #define BWN_ISOLDFMT(mac) ((mac)->mac_fw.rev <= 351) #define BWN_TSSI2DBM(num, den) \ ((int32_t)((num < 0) ? num / den : (num + den / 2) / den)) #define BWN_HDRSIZE(mac) bwn_tx_hdrsize(mac) #define BWN_MAXTXHDRSIZE (112 + (sizeof(struct bwn_plcp6))) #define BWN_PIO_COOKIE(tq, tp) \ ((uint16_t)((((uint16_t)tq->tq_index + 1) << 12) | tp->tp_index)) #define BWN_DMA_COOKIE(dr, slot) \ ((uint16_t)(((uint16_t)dr->dr_index + 1) << 12) | (uint16_t)slot) -#define BWN_READ_2(mac, o) (siba_read_2(mac->mac_sc->sc_dev, o)) -#define BWN_READ_4(mac, o) (siba_read_4(mac->mac_sc->sc_dev, o)) +#define BWN_READ_2(mac, o) \ + (bus_read_2((mac)->mac_sc->sc_mem_res, (o))) +#define BWN_READ_4(mac, o) \ + (bus_read_4((mac)->mac_sc->sc_mem_res, (o))) #define BWN_WRITE_2(mac, o, v) \ - (siba_write_2(mac->mac_sc->sc_dev, o, v)) + (bus_write_2((mac)->mac_sc->sc_mem_res, (o), (v))) #define BWN_WRITE_2_F(mac, o, v) do { \ (BWN_WRITE_2(mac, o, v)); \ BWN_READ_2(mac, o); \ } while(0) #define BWN_WRITE_SETMASK2(mac, offset, mask, set) \ BWN_WRITE_2(mac, offset, (BWN_READ_2(mac, offset) & mask) | set) #define BWN_WRITE_4(mac, o, v) \ - (siba_write_4(mac->mac_sc->sc_dev, o, v)) + (bus_write_4((mac)->mac_sc->sc_mem_res, (o), (v))) #define BWN_WRITE_SETMASK4(mac, offset, mask, set) \ BWN_WRITE_4(mac, offset, (BWN_READ_4(mac, offset) & mask) | set) #define BWN_PIO_TXQOFFSET(mac) \ - ((siba_get_revid(mac->mac_sc->sc_dev) >= 11) ? 0x18 : 0) + ((bhnd_get_hwrev(mac->mac_sc->sc_dev) >= 11) ? 0x18 : 0) #define BWN_PIO_RXQOFFSET(mac) \ - ((siba_get_revid(mac->mac_sc->sc_dev) >= 11) ? 0x38 : 8) + ((bhnd_get_hwrev(mac->mac_sc->sc_dev) >= 11) ? 0x38 : 8) #define BWN_SEC_NEWAPI(mac) (mac->mac_fw.rev >= 351) #define BWN_SEC_KEY2FW(mac, idx) \ (BWN_SEC_NEWAPI(mac) ? idx : ((idx >= 4) ? idx - 4 : idx)) #define BWN_RF_READ(mac, r) (mac->mac_phy.rf_read(mac, r)) #define BWN_RF_WRITE(mac, r, v) (mac->mac_phy.rf_write(mac, r, v)) #define BWN_RF_MASK(mac, o, m) \ BWN_RF_WRITE(mac, o, BWN_RF_READ(mac, o) & m) #define BWN_RF_SETMASK(mac, offset, mask, set) \ BWN_RF_WRITE(mac, offset, (BWN_RF_READ(mac, offset) & mask) | set) #define BWN_RF_SET(mac, offset, set) \ BWN_RF_WRITE(mac, offset, BWN_RF_READ(mac, offset) | set) #define BWN_PHY_READ(mac, r) (mac->mac_phy.phy_read(mac, r)) #define BWN_PHY_WRITE(mac, r, v) \ (mac->mac_phy.phy_write(mac, r, v)) #define BWN_PHY_SET(mac, offset, set) do { \ if (mac->mac_phy.phy_maskset != NULL) { \ KASSERT(mac->mac_status < BWN_MAC_STATUS_INITED || \ mac->mac_suspended > 0, \ ("dont access PHY or RF registers after turning on MAC")); \ mac->mac_phy.phy_maskset(mac, offset, 0xffff, set); \ } else \ BWN_PHY_WRITE(mac, offset, \ BWN_PHY_READ(mac, offset) | (set)); \ } while (0) #define BWN_PHY_SETMASK(mac, offset, mask, set) do { \ if (mac->mac_phy.phy_maskset != NULL) { \ KASSERT(mac->mac_status < BWN_MAC_STATUS_INITED || \ mac->mac_suspended > 0, \ ("dont access PHY or RF registers after turning on MAC")); \ mac->mac_phy.phy_maskset(mac, offset, mask, set); \ } else \ BWN_PHY_WRITE(mac, offset, \ (BWN_PHY_READ(mac, offset) & (mask)) | (set)); \ } while (0) #define BWN_PHY_MASK(mac, offset, mask) do { \ if (mac->mac_phy.phy_maskset != NULL) { \ KASSERT(mac->mac_status < BWN_MAC_STATUS_INITED || \ mac->mac_suspended > 0, \ ("dont access PHY or RF registers after turning on MAC")); \ mac->mac_phy.phy_maskset(mac, offset, mask, 0); \ } else \ BWN_PHY_WRITE(mac, offset, \ BWN_PHY_READ(mac, offset) & mask); \ } while (0) #define BWN_PHY_COPY(mac, dst, src) do { \ KASSERT(mac->mac_status < BWN_MAC_STATUS_INITED || \ mac->mac_suspended > 0, \ ("dont access PHY or RF registers after turning on MAC")); \ BWN_PHY_WRITE(mac, dst, BWN_PHY_READ(mac, src)); \ } while (0) #define BWN_LO_CALIB_EXPIRE (1000 * (30 - 2)) #define BWN_LO_PWRVEC_EXPIRE (1000 * (30 - 2)) #define BWN_LO_TXCTL_EXPIRE (1000 * (180 - 4)) -#define BWN_DMA_BIT_MASK(n) (((n) == 64) ? ~0ULL : ((1ULL<<(n))-1)) #define BWN_LPD(L, P, D) (((L) << 2) | ((P) << 1) | ((D) << 0)) #define BWN_BITREV4(tmp) (BWN_BITREV8(tmp) >> 4) #define BWN_BITREV8(byte) (bwn_bitrev_table[byte]) #define BWN_BBATTCMP(a, b) ((a)->att == (b)->att) #define BWN_RFATTCMP(a, b) \ (((a)->att == (b)->att) && ((a)->padmix == (b)->padmix)) #define BWN_PIO_WRITE_2(mac, tq, offset, value) \ BWN_WRITE_2(mac, (tq)->tq_base + offset, value) #define BWN_PIO_READ_4(mac, tq, offset) \ BWN_READ_4(mac, tq->tq_base + offset) #define BWN_ISCCKRATE(rate) \ (rate == BWN_CCK_RATE_1MB || rate == BWN_CCK_RATE_2MB || \ rate == BWN_CCK_RATE_5MB || rate == BWN_CCK_RATE_11MB) #define BWN_ISOFDMRATE(rate) (!BWN_ISCCKRATE(rate)) -#define BWN_BARRIER(mac, flags) siba_barrier(mac->mac_sc->sc_dev, flags) +#define BWN_BARRIER(mac, offset, length, flags) \ + bus_barrier((mac)->mac_sc->sc_mem_res, (offset), (length), (flags)) #define BWN_DMA_READ(dr, offset) \ (BWN_READ_4(dr->dr_mac, dr->dr_base + offset)) #define BWN_DMA_WRITE(dr, offset, value) \ (BWN_WRITE_4(dr->dr_mac, dr->dr_base + offset, value)) typedef enum { BWN_PHY_BAND_2G = 0, BWN_PHY_BAND_5G_LO = 1, BWN_PHY_BAND_5G_MI = 2, BWN_PHY_BAND_5G_HI = 3 } bwn_phy_band_t; typedef enum { BWN_BAND_2G, BWN_BAND_5G, } bwn_band_t; typedef enum { BWN_CHAN_TYPE_20, BWN_CHAN_TYPE_20_HT, BWN_CHAN_TYPE_40_HT_U, BWN_CHAN_TYPE_40_HT_D, } bwn_chan_type_t; struct bwn_rate { uint16_t rateid; uint32_t flags; }; #define BWN_ANT0 0 #define BWN_ANT1 1 #define BWN_ANTAUTO0 2 #define BWN_ANTAUTO1 3 #define BWN_ANT2 4 #define BWN_ANT3 8 #define BWN_ANTAUTO BWN_ANTAUTO0 #define BWN_ANT_DEFAULT BWN_ANTAUTO #define BWN_TX_SLOTS_PER_FRAME 2 struct bwn_channel { unsigned freq; unsigned ieee; unsigned maxTxPow; }; struct bwn_channelinfo { struct bwn_channel channels[IEEE80211_CHAN_MAX]; unsigned nchannels; }; struct bwn_bbatt { uint8_t att; }; struct bwn_bbatt_list { const struct bwn_bbatt *array; uint8_t len; uint8_t min; uint8_t max; }; struct bwn_rfatt { uint8_t att; int padmix; }; struct bwn_rfatt_list { const struct bwn_rfatt *array; uint8_t len; uint8_t min; uint8_t max; }; #define BWN_DC_LT_SIZE 32 struct bwn_loctl { int8_t i; int8_t q; }; typedef enum { BWN_TXPWR_RES_NEED_ADJUST, BWN_TXPWR_RES_DONE, } bwn_txpwr_result_t; struct bwn_lo_calib { struct bwn_bbatt bbatt; struct bwn_rfatt rfatt; struct bwn_loctl ctl; unsigned long calib_time; TAILQ_ENTRY(bwn_lo_calib) list; }; struct bwn_rxhdr4 { uint16_t frame_len; uint8_t pad1[2]; uint16_t phy_status0; union { struct { uint8_t rssi; uint8_t sig_qual; } __packed abg; struct { int8_t power0; int8_t power1; } __packed n; } __packed phy; union { struct { int8_t power2; uint8_t pad; } __packed n; struct { uint8_t pad; int8_t ht_power0; } __packed ht; uint16_t phy_status2; } __packed ps2; union { struct { uint16_t phy_status3; } __packed lp; struct { int8_t phy_ht_power1; int8_t phy_ht_power2; } __packed ht; } __packed ps3; union { struct { uint32_t mac_status; uint16_t mac_time; uint16_t channel; } __packed r351; struct { uint16_t phy_status4; uint16_t phy_status5; uint32_t mac_status; uint16_t mac_time; uint16_t channel; } __packed r598; } __packed ps4; } __packed; struct bwn_txstatus { uint16_t cookie; uint16_t seq; uint8_t phy_stat; uint8_t framecnt; uint8_t rtscnt; uint8_t sreason; uint8_t pm; uint8_t im; uint8_t ampdu; uint8_t ack; }; #define BWN_TXCTL_PA3DB 0x40 #define BWN_TXCTL_PA2DB 0x20 #define BWN_TXCTL_TXMIX 0x10 struct bwn_txpwr_loctl { struct bwn_rfatt_list rfatt; struct bwn_bbatt_list bbatt; uint16_t dc_lt[BWN_DC_LT_SIZE]; TAILQ_HEAD(, bwn_lo_calib) calib_list; unsigned long pwr_vec_read_time; unsigned long txctl_measured_time; uint8_t tx_bias; uint8_t tx_magn; uint64_t power_vector; }; #define BWN_OFDMTAB_DIR_UNKNOWN 0 #define BWN_OFDMTAB_DIR_READ 1 #define BWN_OFDMTAB_DIR_WRITE 2 struct bwn_phy_g { unsigned pg_flags; #define BWN_PHY_G_FLAG_TSSITABLE_ALLOC (1 << 0) #define BWN_PHY_G_FLAG_RADIOCTX_VALID (1 << 1) int pg_aci_enable; int pg_aci_wlan_automatic; int pg_aci_hw_rssi; int pg_rf_on; uint16_t pg_radioctx_over; uint16_t pg_radioctx_overval; uint16_t pg_minlowsig[2]; uint16_t pg_minlowsigpos[2]; + uint16_t pg_pa0maxpwr; int8_t *pg_tssi2dbm; int pg_idletssi; int pg_curtssi; uint8_t pg_avgtssi; struct bwn_bbatt pg_bbatt; struct bwn_rfatt pg_rfatt; uint8_t pg_txctl; int pg_bbatt_delta; int pg_rfatt_delta; struct bwn_txpwr_loctl pg_loctl; int16_t pg_max_lb_gain; int16_t pg_trsw_rx_gain; int16_t pg_lna_lod_gain; int16_t pg_lna_gain; int16_t pg_pga_gain; int pg_immode; #define BWN_INTERFSTACK_SIZE 26 uint32_t pg_interfstack[BWN_INTERFSTACK_SIZE]; int16_t pg_nrssi[2]; int32_t pg_nrssi_slope; int8_t pg_nrssi_lt[64]; uint16_t pg_lofcal; uint16_t pg_initval; uint16_t pg_ofdmtab_addr; unsigned pg_ofdmtab_dir; }; #define BWN_IMMODE_NONE 0 #define BWN_IMMODE_NONWLAN 1 #define BWN_IMMODE_MANUAL 2 #define BWN_IMMODE_AUTO 3 #define BWN_PHYLP_TXPCTL_UNKNOWN 0 #define BWN_PHYLP_TXPCTL_OFF 1 #define BWN_PHYLP_TXPCTL_ON_SW 2 #define BWN_PHYLP_TXPCTL_ON_HW 3 struct bwn_phy_lp { uint8_t plp_chan; uint8_t plp_chanfullcal; int32_t plp_antenna; uint8_t plp_txpctlmode; uint8_t plp_txisoband_h; uint8_t plp_txisoband_m; uint8_t plp_txisoband_l; uint8_t plp_rxpwroffset; int8_t plp_txpwridx; uint16_t plp_tssiidx; uint16_t plp_tssinpt; uint8_t plp_rssivf; uint8_t plp_rssivc; uint8_t plp_rssigs; uint8_t plp_rccap; uint8_t plp_bxarch; uint8_t plp_crsusr_off; uint8_t plp_crssys_off; uint32_t plp_div; int32_t plp_tonefreq; uint16_t plp_digfilt[9]; }; /* for LP */ struct bwn_txgain { uint16_t tg_gm; uint16_t tg_pga; uint16_t tg_pad; uint16_t tg_dac; }; struct bwn_rxcompco { uint8_t rc_chan; int8_t rc_c1; int8_t rc_c0; }; struct bwn_phy_lp_iq_est { uint32_t ie_iqprod; uint32_t ie_ipwr; uint32_t ie_qpwr; }; struct bwn_txgain_entry { uint8_t te_gm; uint8_t te_pga; uint8_t te_pad; uint8_t te_dac; uint8_t te_bbmult; }; /* only for LP PHY */ struct bwn_stxtable { uint16_t st_phyoffset; uint16_t st_physhift; uint16_t st_rfaddr; uint16_t st_rfshift; uint16_t st_mask; }; struct bwn_b206x_chan { uint8_t bc_chan; uint16_t bc_freq; const uint8_t *bc_data; }; struct bwn_b206x_rfinit_entry { uint16_t br_offset; uint16_t br_valuea; uint16_t br_valueg; uint8_t br_flags; }; struct bwn_phy_n; struct bwn_phy { uint8_t type; uint8_t rev; uint8_t analog; int supports_2ghz; int supports_5ghz; int gmode; struct bwn_phy_g phy_g; struct bwn_phy_lp phy_lp; /* * I'd like the newer PHY code to not hide in the top-level * structs.. */ struct bwn_phy_n *phy_n; uint16_t rf_manuf; uint16_t rf_ver; uint8_t rf_rev; int rf_on; int phy_do_full_init; int txpower; int hwpctl; unsigned long nexttime; unsigned int chan; int txerrors; int (*attach)(struct bwn_mac *); void (*detach)(struct bwn_mac *); int (*prepare_hw)(struct bwn_mac *); void (*init_pre)(struct bwn_mac *); int (*init)(struct bwn_mac *); void (*exit)(struct bwn_mac *); uint16_t (*phy_read)(struct bwn_mac *, uint16_t); void (*phy_write)(struct bwn_mac *, uint16_t, uint16_t); void (*phy_maskset)(struct bwn_mac *, uint16_t, uint16_t, uint16_t); uint16_t (*rf_read)(struct bwn_mac *, uint16_t); void (*rf_write)(struct bwn_mac *, uint16_t, uint16_t); int (*use_hwpctl)(struct bwn_mac *); void (*rf_onoff)(struct bwn_mac *, int); void (*switch_analog)(struct bwn_mac *, int); int (*switch_channel)(struct bwn_mac *, unsigned int); uint32_t (*get_default_chan)(struct bwn_mac *); void (*set_antenna)(struct bwn_mac *, int); int (*set_im)(struct bwn_mac *, int); bwn_txpwr_result_t (*recalc_txpwr)(struct bwn_mac *, int); void (*set_txpwr)(struct bwn_mac *); void (*task_15s)(struct bwn_mac *); void (*task_60s)(struct bwn_mac *); }; struct bwn_chan_band { uint32_t flags; uint8_t nchan; #define BWN_MAX_CHAN_PER_BAND 14 uint8_t chan[BWN_MAX_CHAN_PER_BAND]; }; #define BWN_NR_WMEPARAMS 16 enum { BWN_WMEPARAM_TXOP = 0, BWN_WMEPARAM_CWMIN, BWN_WMEPARAM_CWMAX, BWN_WMEPARAM_CWCUR, BWN_WMEPARAM_AIFS, BWN_WMEPARAM_BSLOTS, BWN_WMEPARAM_REGGAP, BWN_WMEPARAM_STATUS, }; #define BWN_WME_PARAMS(queue) \ (BWN_SHARED_EDCFQ + (BWN_NR_WMEPARAMS * sizeof(uint16_t) * (queue))) #define BWN_WME_BACKGROUND BWN_WME_PARAMS(0) #define BWN_WME_BESTEFFORT BWN_WME_PARAMS(1) #define BWN_WME_VIDEO BWN_WME_PARAMS(2) #define BWN_WME_VOICE BWN_WME_PARAMS(3) /* * Radio capture format. */ #define BWN_RX_RADIOTAP_PRESENT ( \ (1 << IEEE80211_RADIOTAP_TSFT) | \ (1 << IEEE80211_RADIOTAP_FLAGS) | \ (1 << IEEE80211_RADIOTAP_RATE) | \ (1 << IEEE80211_RADIOTAP_CHANNEL) | \ (1 << IEEE80211_RADIOTAP_ANTENNA) | \ (1 << IEEE80211_RADIOTAP_DBM_ANTSIGNAL) | \ (1 << IEEE80211_RADIOTAP_DBM_ANTNOISE) | \ 0) struct bwn_rx_radiotap_header { struct ieee80211_radiotap_header wr_ihdr; uint64_t wr_tsf; u_int8_t wr_flags; u_int8_t wr_rate; u_int16_t wr_chan_freq; u_int16_t wr_chan_flags; int8_t wr_antsignal; int8_t wr_antnoise; u_int8_t wr_antenna; }; #define BWN_TX_RADIOTAP_PRESENT ( \ (1 << IEEE80211_RADIOTAP_FLAGS) | \ (1 << IEEE80211_RADIOTAP_RATE) | \ (1 << IEEE80211_RADIOTAP_CHANNEL) | \ (1 << IEEE80211_RADIOTAP_DBM_TX_POWER) | \ (1 << IEEE80211_RADIOTAP_ANTENNA) | \ 0) struct bwn_tx_radiotap_header { struct ieee80211_radiotap_header wt_ihdr; u_int8_t wt_flags; u_int8_t wt_rate; u_int16_t wt_chan_freq; u_int16_t wt_chan_flags; u_int8_t wt_txpower; u_int8_t wt_antenna; }; struct bwn_stats { int32_t rtsfail; int32_t rts; int32_t link_noise; }; /* Noise Calculation (Link Quality) */ struct bwn_noise { uint8_t noi_running; uint8_t noi_nsamples; int8_t noi_samples[8][4]; }; -#define BWN_DMA_30BIT 30 -#define BWN_DMA_32BIT 32 -#define BWN_DMA_64BIT 64 - struct bwn_dmadesc_meta { bus_dmamap_t mt_dmap; bus_addr_t mt_paddr; struct mbuf *mt_m; struct ieee80211_node *mt_ni; uint8_t mt_txtype; #define BWN_DMADESC_METATYPE_HEADER 0 #define BWN_DMADESC_METATYPE_BODY 1 uint8_t mt_islast; }; #define BWN_DMAINTR_FATALMASK \ ((1 << 10) | (1 << 11) | (1 << 12) | (1 << 14) | (1 << 15)) #define BWN_DMAINTR_NONFATALMASK (1 << 13) #define BWN_DMAINTR_RX_DONE (1 << 16) #define BWN_DMA32_DCTL_BYTECNT 0x00001fff #define BWN_DMA32_DCTL_ADDREXT_MASK 0x00030000 #define BWN_DMA32_DCTL_ADDREXT_SHIFT 16 #define BWN_DMA32_DCTL_DTABLEEND 0x10000000 #define BWN_DMA32_DCTL_IRQ 0x20000000 #define BWN_DMA32_DCTL_FRAMEEND 0x40000000 #define BWN_DMA32_DCTL_FRAMESTART 0x80000000 struct bwn_dmadesc32 { uint32_t control; uint32_t address; } __packed; #define BWN_DMA64_DCTL0_DTABLEEND 0x10000000 #define BWN_DMA64_DCTL0_IRQ 0x20000000 #define BWN_DMA64_DCTL0_FRAMEEND 0x40000000 #define BWN_DMA64_DCTL0_FRAMESTART 0x80000000 #define BWN_DMA64_DCTL1_BYTECNT 0x00001fff #define BWN_DMA64_DCTL1_ADDREXT_MASK 0x00030000 #define BWN_DMA64_DCTL1_ADDREXT_SHIFT 16 struct bwn_dmadesc64 { uint32_t control0; uint32_t control1; uint32_t address_low; uint32_t address_high; } __packed; struct bwn_dmadesc_generic { union { struct bwn_dmadesc32 dma32; struct bwn_dmadesc64 dma64; } __packed dma; } __packed; struct bwn_dma_ring; struct bwn_dma_ring { struct bwn_mac *dr_mac; const struct bwn_dma_ops *dr_ops; struct bwn_dmadesc_meta *dr_meta; void *dr_txhdr_cache; bus_dma_tag_t dr_ring_dtag; bus_dma_tag_t dr_txring_dtag; bus_dmamap_t dr_spare_dmap; /* only for RX */ bus_dmamap_t dr_ring_dmap; bus_addr_t dr_txring_paddr; void *dr_ring_descbase; bus_addr_t dr_ring_dmabase; int dr_numslots; int dr_usedslot; int dr_curslot; uint32_t dr_frameoffset; uint16_t dr_rx_bufsize; uint16_t dr_base; int dr_index; uint8_t dr_tx; uint8_t dr_stop; int dr_type; void (*getdesc)(struct bwn_dma_ring *, int, struct bwn_dmadesc_generic **, struct bwn_dmadesc_meta **); void (*setdesc)(struct bwn_dma_ring *, struct bwn_dmadesc_generic *, bus_addr_t, uint16_t, int, int, int); void (*start_transfer)(struct bwn_dma_ring *, int); void (*suspend)(struct bwn_dma_ring *); void (*resume)(struct bwn_dma_ring *); int (*get_curslot)(struct bwn_dma_ring *); void (*set_curslot)(struct bwn_dma_ring *, int); }; struct bwn_dma { - int dmatype; bus_dma_tag_t parent_dtag; bus_dma_tag_t rxbuf_dtag; bus_dma_tag_t txbuf_dtag; + struct bhnd_dma_translation translation; + u_int addrext_shift; struct bwn_dma_ring *wme[5]; struct bwn_dma_ring *mcast; struct bwn_dma_ring *rx; uint64_t lastseq; /* XXX FIXME */ }; struct bwn_pio_rxqueue { struct bwn_mac *prq_mac; uint16_t prq_base; uint8_t prq_rev; }; struct bwn_pio_txqueue; struct bwn_pio_txpkt { struct bwn_pio_txqueue *tp_queue; struct ieee80211_node *tp_ni; struct mbuf *tp_m; uint8_t tp_index; TAILQ_ENTRY(bwn_pio_txpkt) tp_list; }; #define BWN_PIO_MAX_TXPACKETS 32 struct bwn_pio_txqueue { uint16_t tq_base; uint16_t tq_size; uint16_t tq_used; uint16_t tq_free; uint8_t tq_index; struct bwn_pio_txpkt tq_pkts[BWN_PIO_MAX_TXPACKETS]; TAILQ_HEAD(, bwn_pio_txpkt) tq_pktlist; }; struct bwn_pio { struct bwn_pio_txqueue wme[5]; struct bwn_pio_txqueue mcast; struct bwn_pio_rxqueue rx; }; struct bwn_plcp4 { union { uint32_t data; uint8_t raw[4]; } __packed o; } __packed; struct bwn_plcp6 { union { uint32_t data; uint8_t raw[6]; } __packed o; } __packed; struct bwn_txhdr { uint32_t macctl; uint8_t macfc[2]; uint16_t tx_festime; uint16_t phyctl; uint16_t phyctl_1; uint16_t phyctl_1fb; uint16_t phyctl_1rts; uint16_t phyctl_1rtsfb; uint8_t phyrate; uint8_t phyrate_rts; uint8_t eftypes; /* extra frame types */ uint8_t chan; uint8_t iv[16]; uint8_t addr1[IEEE80211_ADDR_LEN]; uint16_t tx_festime_fb; struct bwn_plcp6 rts_plcp_fb; uint16_t rts_dur_fb; struct bwn_plcp6 plcp_fb; uint16_t dur_fb; uint16_t mimo_modelen; uint16_t mimo_ratelen_fb; uint32_t timeout; union { /* format <= r351 */ struct { uint8_t pad0[2]; uint16_t cookie; uint16_t tx_status; struct bwn_plcp6 rts_plcp; uint8_t rts_frame[16]; uint8_t pad1[2]; struct bwn_plcp6 plcp; } __packed r351; /* format > r410 < r598 */ struct { uint16_t mimo_antenna; uint16_t preload_size; uint8_t pad0[2]; uint16_t cookie; uint16_t tx_status; struct bwn_plcp6 rts_plcp; uint8_t rts_frame[16]; uint8_t pad1[2]; struct bwn_plcp6 plcp; } __packed r410; struct { uint16_t mimo_antenna; uint16_t preload_size; uint8_t pad0[2]; uint16_t cookie; uint16_t tx_status; uint16_t max_n_mpdus; uint16_t max_a_bytes_mrt; uint16_t max_a_bytes_fbr; uint16_t min_m_bytes; struct bwn_plcp6 rts_plcp; uint8_t rts_frame[16]; uint8_t pad1[2]; struct bwn_plcp6 plcp; } __packed r598; } __packed body; } __packed; #define BWN_FWTYPE_UCODE 'u' #define BWN_FWTYPE_PCM 'p' #define BWN_FWTYPE_IV 'i' struct bwn_fwhdr { uint8_t type; uint8_t ver; uint8_t pad[2]; uint32_t size; } __packed; #define BWN_FWINITVALS_OFFSET_MASK 0x7fff #define BWN_FWINITVALS_32BIT 0x8000 struct bwn_fwinitvals { uint16_t offset_size; union { uint16_t d16; uint32_t d32; } __packed data; } __packed; enum bwn_fw_hdr_format { BWN_FW_HDR_598, BWN_FW_HDR_410, BWN_FW_HDR_351, }; enum bwn_fwtype { BWN_FWTYPE_DEFAULT, BWN_FWTYPE_OPENSOURCE, BWN_NR_FWTYPES, }; struct bwn_fwfile { const char *filename; const struct firmware *fw; enum bwn_fwtype type; }; struct bwn_key { void *keyconf; uint8_t algorithm; }; struct bwn_fw { struct bwn_fwfile ucode; struct bwn_fwfile pcm; struct bwn_fwfile initvals; struct bwn_fwfile initvals_band; enum bwn_fw_hdr_format fw_hdr_format; uint16_t rev; uint16_t patch; uint8_t opensource; uint8_t no_pcmfile; }; struct bwn_lo_g_sm { int curstate; int nmeasure; int multipler; uint16_t feedth; struct bwn_loctl loctl; }; struct bwn_lo_g_value { uint8_t old_channel; uint16_t phy_lomask; uint16_t phy_extg; uint16_t phy_dacctl_hwpctl; uint16_t phy_dacctl; uint16_t phy_hpwr_tssictl; uint16_t phy_analogover; uint16_t phy_analogoverval; uint16_t phy_rfover; uint16_t phy_rfoverval; uint16_t phy_classctl; uint16_t phy_crs0; uint16_t phy_pgactl; uint16_t phy_syncctl; uint16_t phy_cck0; uint16_t phy_cck1; uint16_t phy_cck2; uint16_t phy_cck3; uint16_t phy_cck4; uint16_t reg0; uint16_t reg1; uint16_t rf0; uint16_t rf1; uint16_t rf2; }; #define BWN_LED_MAX 4 #define BWN_LED_EVENT_NONE -1 #define BWN_LED_EVENT_POLL 0 #define BWN_LED_EVENT_TX 1 #define BWN_LED_EVENT_RX 2 #define BWN_LED_SLOWDOWN(dur) (dur) = (((dur) * 3) / 2) struct bwn_led { uint8_t led_flags; /* BWN_LED_F_ */ uint8_t led_act; /* BWN_LED_ACT_ */ uint8_t led_mask; }; #define BWN_LED_F_ACTLOW 0x1 #define BWN_LED_F_BLINK 0x2 #define BWN_LED_F_POLLABLE 0x4 #define BWN_LED_F_SLOW 0x8 struct bwn_mac { struct bwn_softc *mac_sc; unsigned mac_status; #define BWN_MAC_STATUS_UNINIT 0 #define BWN_MAC_STATUS_INITED 1 #define BWN_MAC_STATUS_STARTED 2 unsigned mac_flags; /* use "Bad Frames Preemption" */ #define BWN_MAC_FLAG_BADFRAME_PREEMP (1 << 0) #define BWN_MAC_FLAG_DFQVALID (1 << 1) #define BWN_MAC_FLAG_RADIO_ON (1 << 2) #define BWN_MAC_FLAG_DMA (1 << 3) #define BWN_MAC_FLAG_WME (1 << 4) #define BWN_MAC_FLAG_HWCRYPTO (1 << 5) - struct resource_spec *mac_intr_spec; -#define BWN_MSI_MESSAGES 1 - struct resource *mac_res_irq[BWN_MSI_MESSAGES]; - void *mac_intrhand[BWN_MSI_MESSAGES]; - int mac_msi; + struct resource *mac_res_irq; + int mac_rid_irq; + void *mac_intrhand; struct bwn_noise mac_noise; struct bwn_phy mac_phy; struct bwn_stats mac_stats; uint32_t mac_reason_intr; uint32_t mac_reason[6]; uint32_t mac_intr_mask; int mac_suspended; struct bwn_fw mac_fw; + int mac_dmatype; union { struct bwn_dma dma; struct bwn_pio pio; } mac_method; uint16_t mac_ktp; /* Key table pointer */ uint8_t mac_max_nr_keys; struct bwn_key mac_key[58]; unsigned int mac_task_state; struct task mac_intrtask; struct task mac_hwreset; struct task mac_txpower; TAILQ_ENTRY(bwn_mac) mac_list; }; static inline int bwn_tx_hdrsize(struct bwn_mac *mac) { switch (mac->mac_fw.fw_hdr_format) { case BWN_FW_HDR_598: return (112 + (sizeof(struct bwn_plcp6))); case BWN_FW_HDR_410: return (104 + (sizeof(struct bwn_plcp6))); case BWN_FW_HDR_351: return (100 + (sizeof(struct bwn_plcp6))); default: printf("%s: unknown header format (%d)\n", __func__, mac->mac_fw.fw_hdr_format); return (112 + (sizeof(struct bwn_plcp6))); } } /* * Driver-specific vap state. */ struct bwn_vap { struct ieee80211vap bv_vap; /* base class */ int (*bv_newstate)(struct ieee80211vap *, enum ieee80211_state, int); }; #define BWN_VAP(vap) ((struct bwn_vap *)(vap)) #define BWN_VAP_CONST(vap) ((const struct mwl_vap *)(vap)) +enum bwn_quirk { + /** + * The ucode PCI slowclock workaround is required on this device. + * @see BWN_HF_PCI_SLOWCLOCK_WORKAROUND. + */ + BWN_QUIRK_UCODE_SLOWCLOCK_WAR = (1<<0), + + /** + * DMA is unsupported on this device; PIO should be used instead. + */ + BWN_QUIRK_NODMA = (1<<1), +}; + struct bwn_softc { device_t sc_dev; - const struct bwn_bus_ops *sc_bus_ops; -#if !BWN_USE_SIBA - void *sc_bus_ctx; - struct bhnd_resource *sc_mem_res; - int sc_mem_rid; -#endif /* !BWN_USE_SIBA */ + struct bhnd_board_info sc_board_info; + struct bhnd_chipid sc_cid; + uint32_t sc_quirks; /**< @see bwn_quirk */ + struct resource *sc_mem_res; + int sc_mem_rid; + + device_t sc_chipc; /**< ChipCommon device */ + device_t sc_gpio; /**< GPIO device */ + device_t sc_pmu; /**< PMU device, or NULL if unsupported */ + struct mtx sc_mtx; struct ieee80211com sc_ic; struct mbufq sc_snd; unsigned sc_flags; #define BWN_FLAG_ATTACHED (1 << 0) #define BWN_FLAG_INVALID (1 << 1) #define BWN_FLAG_NEED_BEACON_TP (1 << 2) #define BWN_FLAG_RUNNING (1 << 3) unsigned sc_debug; struct bwn_mac *sc_curmac; TAILQ_HEAD(, bwn_mac) sc_maclist; uint8_t sc_bssid[IEEE80211_ADDR_LEN]; unsigned int sc_filters; uint8_t sc_beacons[2]; uint8_t sc_rf_enabled; struct wmeParams sc_wmeParams[4]; struct callout sc_rfswitch_ch; /* for laptop */ struct callout sc_task_ch; struct callout sc_watchdog_ch; int sc_watchdog_timer; struct taskqueue *sc_tq; /* private task queue */ int (*sc_newstate)(struct ieee80211com *, enum ieee80211_state, int); void (*sc_node_cleanup)( struct ieee80211_node *); int sc_rx_rate; int sc_tx_rate; int sc_led_blinking; int sc_led_ticks; struct bwn_led *sc_blink_led; struct callout sc_led_blink_ch; int sc_led_blink_offdur; struct bwn_led sc_leds[BWN_LED_MAX]; int sc_led_idle; int sc_led_blink; + + uint8_t sc_ant2g; /**< available 2GHz antennas */ + uint8_t sc_ant5g; /**< available 5GHz antennas */ struct bwn_tx_radiotap_header sc_tx_th; struct bwn_rx_radiotap_header sc_rx_th; }; #define BWN_LOCK_INIT(sc) \ mtx_init(&(sc)->sc_mtx, device_get_nameunit((sc)->sc_dev), \ MTX_NETWORK_LOCK, MTX_DEF) #define BWN_LOCK_DESTROY(sc) mtx_destroy(&(sc)->sc_mtx) #define BWN_LOCK(sc) mtx_lock(&(sc)->sc_mtx) #define BWN_UNLOCK(sc) mtx_unlock(&(sc)->sc_mtx) #define BWN_ASSERT_LOCKED(sc) mtx_assert(&(sc)->sc_mtx, MA_OWNED) static inline bwn_band_t bwn_channel_band(struct bwn_mac *mac, struct ieee80211_channel *c) { if (IEEE80211_IS_CHAN_5GHZ(c)) return BWN_BAND_5G; /* XXX check 2g, log error if not 2g or 5g? */ return BWN_BAND_2G; } static inline bwn_band_t bwn_current_band(struct bwn_mac *mac) { struct ieee80211com *ic = &mac->mac_sc->sc_ic; if (IEEE80211_IS_CHAN_5GHZ(ic->ic_curchan)) return BWN_BAND_5G; /* XXX check 2g, log error if not 2g or 5g? */ return BWN_BAND_2G; } static inline bool bwn_is_40mhz(struct bwn_mac *mac) { struct ieee80211com *ic = &mac->mac_sc->sc_ic; return !! (IEEE80211_IS_CHAN_HT40(ic->ic_curchan)); } static inline int bwn_get_centre_freq(struct bwn_mac *mac) { struct ieee80211com *ic = &mac->mac_sc->sc_ic; /* XXX TODO: calculate correctly for HT40 mode */ return ic->ic_curchan->ic_freq; } static inline int bwn_get_chan_centre_freq(struct bwn_mac *mac, struct ieee80211_channel *chan) { /* XXX TODO: calculate correctly for HT40 mode */ return chan->ic_freq; } static inline int bwn_get_chan(struct bwn_mac *mac) { struct ieee80211com *ic = &mac->mac_sc->sc_ic; /* XXX TODO: calculate correctly for HT40 mode */ return ic->ic_curchan->ic_ieee; } static inline struct ieee80211_channel * bwn_get_channel(struct bwn_mac *mac) { struct ieee80211com *ic = &mac->mac_sc->sc_ic; return ic->ic_curchan; } static inline bool bwn_is_chan_passive(struct bwn_mac *mac) { struct ieee80211com *ic = &mac->mac_sc->sc_ic; return !! IEEE80211_IS_CHAN_PASSIVE(ic->ic_curchan); } static inline bwn_chan_type_t bwn_get_chan_type(struct bwn_mac *mac, struct ieee80211_channel *c) { struct ieee80211com *ic = &mac->mac_sc->sc_ic; if (c == NULL) c = ic->ic_curchan; if (IEEE80211_IS_CHAN_HT40U(c)) return BWN_CHAN_TYPE_40_HT_U; else if (IEEE80211_IS_CHAN_HT40D(c)) return BWN_CHAN_TYPE_40_HT_D; else if (IEEE80211_IS_CHAN_HT20(c)) return BWN_CHAN_TYPE_20_HT; else return BWN_CHAN_TYPE_20; } static inline int bwn_get_chan_power(struct bwn_mac *mac, struct ieee80211_channel *c) { /* return in dbm */ return c->ic_maxpower / 2; } #endif /* !_IF_BWNVAR_H */ Index: head/sys/gnu/dev/bwn/phy_n/if_bwn_phy_n_core.c =================================================================== --- head/sys/gnu/dev/bwn/phy_n/if_bwn_phy_n_core.c (revision 328911) +++ head/sys/gnu/dev/bwn/phy_n/if_bwn_phy_n_core.c (revision 328912) @@ -1,6833 +1,6943 @@ /* Broadcom B43 wireless driver IEEE 802.11n PHY data tables Copyright (c) 2008 Michael Buesch Copyright (c) 2010 RafaÅ‚ MiÅ‚ecki This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 2 of the License, or (at your option) any later version. This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with this program; see the file COPYING. If not, write to the Free Software Foundation, Inc., 51 Franklin Steet, Fifth Floor, Boston, MA 02110-1301, USA. */ #include __FBSDID("$FreeBSD$"); /* * The Broadcom Wireless LAN controller driver. */ #include "opt_wlan.h" #include "opt_bwn.h" #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include +#include +#include + +#include +#include + #include #include #include #include #include #include -#include #include #include #include +#include #include #include #include #include #include +#include "bhnd_nvram_map.h" + struct bwn_nphy_txgains { uint16_t tx_lpf[2]; uint16_t txgm[2]; uint16_t pga[2]; uint16_t pad[2]; uint16_t ipa[2]; }; struct bwn_nphy_iqcal_params { uint16_t tx_lpf; uint16_t txgm; uint16_t pga; uint16_t pad; uint16_t ipa; uint16_t cal_gain; uint16_t ncorr[5]; }; struct bwn_nphy_iq_est { int32_t iq0_prod; uint32_t i0_pwr; uint32_t q0_pwr; int32_t iq1_prod; uint32_t i1_pwr; uint32_t q1_pwr; }; enum bwn_nphy_rf_sequence { BWN_RFSEQ_RX2TX, BWN_RFSEQ_TX2RX, BWN_RFSEQ_RESET2RX, BWN_RFSEQ_UPDATE_GAINH, BWN_RFSEQ_UPDATE_GAINL, BWN_RFSEQ_UPDATE_GAINU, }; enum n_rf_ctl_over_cmd { N_RF_CTL_OVER_CMD_RXRF_PU = 0, N_RF_CTL_OVER_CMD_RX_PU = 1, N_RF_CTL_OVER_CMD_TX_PU = 2, N_RF_CTL_OVER_CMD_RX_GAIN = 3, N_RF_CTL_OVER_CMD_TX_GAIN = 4, }; enum n_intc_override { N_INTC_OVERRIDE_OFF = 0, N_INTC_OVERRIDE_TRSW = 1, N_INTC_OVERRIDE_PA = 2, N_INTC_OVERRIDE_EXT_LNA_PU = 3, N_INTC_OVERRIDE_EXT_LNA_GAIN = 4, }; enum n_rssi_type { N_RSSI_W1 = 0, N_RSSI_W2, N_RSSI_NB, N_RSSI_IQ, N_RSSI_TSSI_2G, N_RSSI_TSSI_5G, N_RSSI_TBD, }; enum n_rail_type { N_RAIL_I = 0, N_RAIL_Q = 1, }; static inline bool bwn_nphy_ipa(struct bwn_mac *mac) { bwn_band_t band = bwn_current_band(mac); return ((mac->mac_phy.phy_n->ipa2g_on && band == BWN_BAND_2G) || (mac->mac_phy.phy_n->ipa5g_on && band == BWN_BAND_5G)); } /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RxCoreGetState */ static uint8_t bwn_nphy_get_rx_core_state(struct bwn_mac *mac) { return (BWN_PHY_READ(mac, BWN_NPHY_RFSEQCA) & BWN_NPHY_RFSEQCA_RXEN) >> BWN_NPHY_RFSEQCA_RXEN_SHIFT; } /************************************************** * RF (just without bwn_nphy_rf_ctl_intc_override) **************************************************/ /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/ForceRFSeq */ static void bwn_nphy_force_rf_sequence(struct bwn_mac *mac, enum bwn_nphy_rf_sequence seq) { static const uint16_t trigger[] = { [BWN_RFSEQ_RX2TX] = BWN_NPHY_RFSEQTR_RX2TX, [BWN_RFSEQ_TX2RX] = BWN_NPHY_RFSEQTR_TX2RX, [BWN_RFSEQ_RESET2RX] = BWN_NPHY_RFSEQTR_RST2RX, [BWN_RFSEQ_UPDATE_GAINH] = BWN_NPHY_RFSEQTR_UPGH, [BWN_RFSEQ_UPDATE_GAINL] = BWN_NPHY_RFSEQTR_UPGL, [BWN_RFSEQ_UPDATE_GAINU] = BWN_NPHY_RFSEQTR_UPGU, }; int i; uint16_t seq_mode = BWN_PHY_READ(mac, BWN_NPHY_RFSEQMODE); if (seq >= nitems(trigger)) { BWN_WARNPRINTF(mac->mac_sc, "%s: seq %d > max", __func__, seq); } BWN_PHY_SET(mac, BWN_NPHY_RFSEQMODE, BWN_NPHY_RFSEQMODE_CAOVER | BWN_NPHY_RFSEQMODE_TROVER); BWN_PHY_SET(mac, BWN_NPHY_RFSEQTR, trigger[seq]); for (i = 0; i < 200; i++) { if (!(BWN_PHY_READ(mac, BWN_NPHY_RFSEQST) & trigger[seq])) goto ok; DELAY(1000); } BWN_ERRPRINTF(mac->mac_sc, "RF sequence status timeout\n"); ok: BWN_PHY_WRITE(mac, BWN_NPHY_RFSEQMODE, seq_mode); } static void bwn_nphy_rf_ctl_override_rev19(struct bwn_mac *mac, uint16_t field, uint16_t value, uint8_t core, bool off, uint8_t override_id) { /* TODO */ } /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RFCtrlOverrideRev7 */ static void bwn_nphy_rf_ctl_override_rev7(struct bwn_mac *mac, uint16_t field, uint16_t value, uint8_t core, bool off, uint8_t override) { struct bwn_phy *phy = &mac->mac_phy; const struct bwn_nphy_rf_control_override_rev7 *e; uint16_t en_addrs[3][2] = { { 0x0E7, 0x0EC }, { 0x342, 0x343 }, { 0x346, 0x347 } }; uint16_t en_addr; uint16_t en_mask = field; uint16_t val_addr; uint8_t i; if (phy->rev >= 19 || phy->rev < 3) { BWN_WARNPRINTF(mac->mac_sc, "%s: phy rev %d out of range\n", __func__, phy->rev); return; } /* Remember: we can get NULL! */ e = bwn_nphy_get_rf_ctl_over_rev7(mac, field, override); for (i = 0; i < 2; i++) { if (override >= nitems(en_addrs)) { BWN_ERRPRINTF(mac->mac_sc, "Invalid override value %d\n", override); return; } en_addr = en_addrs[override][i]; if (e) val_addr = (i == 0) ? e->val_addr_core0 : e->val_addr_core1; if (off) { BWN_PHY_MASK(mac, en_addr, ~en_mask); if (e) /* Do it safer, better than wl */ BWN_PHY_MASK(mac, val_addr, ~e->val_mask); } else { if (!core || (core & (1 << i))) { BWN_PHY_SET(mac, en_addr, en_mask); if (e) BWN_PHY_SETMASK(mac, val_addr, ~e->val_mask, (value << e->val_shift)); } } } } /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RFCtrlOverideOneToMany */ static void bwn_nphy_rf_ctl_override_one_to_many(struct bwn_mac *mac, enum n_rf_ctl_over_cmd cmd, uint16_t value, uint8_t core, bool off) { struct bwn_phy *phy = &mac->mac_phy; uint16_t tmp; if (phy->rev < 7) { BWN_ERRPRINTF(mac->mac_sc, "%s: phy rev %d out of range\n", __func__, phy->rev); } switch (cmd) { case N_RF_CTL_OVER_CMD_RXRF_PU: bwn_nphy_rf_ctl_override_rev7(mac, 0x20, value, core, off, 1); bwn_nphy_rf_ctl_override_rev7(mac, 0x10, value, core, off, 1); bwn_nphy_rf_ctl_override_rev7(mac, 0x08, value, core, off, 1); break; case N_RF_CTL_OVER_CMD_RX_PU: bwn_nphy_rf_ctl_override_rev7(mac, 0x4, value, core, off, 1); bwn_nphy_rf_ctl_override_rev7(mac, 0x2, value, core, off, 1); bwn_nphy_rf_ctl_override_rev7(mac, 0x1, value, core, off, 1); bwn_nphy_rf_ctl_override_rev7(mac, 0x2, value, core, off, 2); bwn_nphy_rf_ctl_override_rev7(mac, 0x0800, 0, core, off, 1); break; case N_RF_CTL_OVER_CMD_TX_PU: bwn_nphy_rf_ctl_override_rev7(mac, 0x4, value, core, off, 0); bwn_nphy_rf_ctl_override_rev7(mac, 0x2, value, core, off, 1); bwn_nphy_rf_ctl_override_rev7(mac, 0x1, value, core, off, 2); bwn_nphy_rf_ctl_override_rev7(mac, 0x0800, 1, core, off, 1); break; case N_RF_CTL_OVER_CMD_RX_GAIN: tmp = value & 0xFF; bwn_nphy_rf_ctl_override_rev7(mac, 0x0800, tmp, core, off, 0); tmp = value >> 8; bwn_nphy_rf_ctl_override_rev7(mac, 0x6000, tmp, core, off, 0); break; case N_RF_CTL_OVER_CMD_TX_GAIN: tmp = value & 0x7FFF; bwn_nphy_rf_ctl_override_rev7(mac, 0x1000, tmp, core, off, 0); tmp = value >> 14; bwn_nphy_rf_ctl_override_rev7(mac, 0x4000, tmp, core, off, 0); break; } } /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RFCtrlOverride */ static void bwn_nphy_rf_ctl_override(struct bwn_mac *mac, uint16_t field, uint16_t value, uint8_t core, bool off) { int i; uint8_t index = fls(field); uint8_t addr, en_addr, val_addr; /* we expect only one bit set */ if (field & (~(1 << (index - 1)))) { BWN_ERRPRINTF(mac->mac_sc, "%s: field 0x%04x has >1 bit set\n", __func__, field); } if (mac->mac_phy.rev >= 3) { const struct bwn_nphy_rf_control_override_rev3 *rf_ctrl; for (i = 0; i < 2; i++) { if (index == 0 || index == 16) { BWN_ERRPRINTF(mac->mac_sc, "Unsupported RF Ctrl Override call\n"); return; } rf_ctrl = &tbl_rf_control_override_rev3[index - 1]; en_addr = BWN_PHY_N((i == 0) ? rf_ctrl->en_addr0 : rf_ctrl->en_addr1); val_addr = BWN_PHY_N((i == 0) ? rf_ctrl->val_addr0 : rf_ctrl->val_addr1); if (off) { BWN_PHY_MASK(mac, en_addr, ~(field)); BWN_PHY_MASK(mac, val_addr, ~(rf_ctrl->val_mask)); } else { if (core == 0 || ((1 << i) & core)) { BWN_PHY_SET(mac, en_addr, field); BWN_PHY_SETMASK(mac, val_addr, ~(rf_ctrl->val_mask), (value << rf_ctrl->val_shift)); } } } } else { const struct bwn_nphy_rf_control_override_rev2 *rf_ctrl; if (off) { BWN_PHY_MASK(mac, BWN_NPHY_RFCTL_OVER, ~(field)); value = 0; } else { BWN_PHY_SET(mac, BWN_NPHY_RFCTL_OVER, field); } for (i = 0; i < 2; i++) { if (index <= 1 || index == 16) { BWN_ERRPRINTF(mac->mac_sc, "Unsupported RF Ctrl Override call\n"); return; } if (index == 2 || index == 10 || (index >= 13 && index <= 15)) { core = 1; } rf_ctrl = &tbl_rf_control_override_rev2[index - 2]; addr = BWN_PHY_N((i == 0) ? rf_ctrl->addr0 : rf_ctrl->addr1); if ((1 << i) & core) BWN_PHY_SETMASK(mac, addr, ~(rf_ctrl->bmask), (value << rf_ctrl->shift)); BWN_PHY_SET(mac, BWN_NPHY_RFCTL_OVER, 0x1); BWN_PHY_SET(mac, BWN_NPHY_RFCTL_CMD, BWN_NPHY_RFCTL_CMD_START); DELAY(1); BWN_PHY_MASK(mac, BWN_NPHY_RFCTL_OVER, 0xFFFE); } } } static void bwn_nphy_rf_ctl_intc_override_rev7(struct bwn_mac *mac, enum n_intc_override intc_override, uint16_t value, uint8_t core_sel) { uint16_t reg, tmp, tmp2, val; int core; /* TODO: What about rev19+? Revs 3+ and 7+ are a bit similar */ for (core = 0; core < 2; core++) { if ((core_sel == 1 && core != 0) || (core_sel == 2 && core != 1)) continue; reg = (core == 0) ? BWN_NPHY_RFCTL_INTC1 : BWN_NPHY_RFCTL_INTC2; switch (intc_override) { case N_INTC_OVERRIDE_OFF: BWN_PHY_WRITE(mac, reg, 0); BWN_PHY_MASK(mac, 0x2ff, ~0x2000); bwn_nphy_force_rf_sequence(mac, BWN_RFSEQ_RESET2RX); break; case N_INTC_OVERRIDE_TRSW: BWN_PHY_SETMASK(mac, reg, ~0xC0, value << 6); BWN_PHY_SET(mac, reg, 0x400); BWN_PHY_MASK(mac, 0x2ff, ~0xC000 & 0xFFFF); BWN_PHY_SET(mac, 0x2ff, 0x2000); BWN_PHY_SET(mac, 0x2ff, 0x0001); break; case N_INTC_OVERRIDE_PA: tmp = 0x0030; if (bwn_current_band(mac) == BWN_BAND_5G) val = value << 5; else val = value << 4; BWN_PHY_SETMASK(mac, reg, ~tmp, val); BWN_PHY_SET(mac, reg, 0x1000); break; case N_INTC_OVERRIDE_EXT_LNA_PU: if (bwn_current_band(mac) == BWN_BAND_5G) { tmp = 0x0001; tmp2 = 0x0004; val = value; } else { tmp = 0x0004; tmp2 = 0x0001; val = value << 2; } BWN_PHY_SETMASK(mac, reg, ~tmp, val); BWN_PHY_MASK(mac, reg, ~tmp2); break; case N_INTC_OVERRIDE_EXT_LNA_GAIN: if (bwn_current_band(mac) == BWN_BAND_5G) { tmp = 0x0002; tmp2 = 0x0008; val = value << 1; } else { tmp = 0x0008; tmp2 = 0x0002; val = value << 3; } BWN_PHY_SETMASK(mac, reg, ~tmp, val); BWN_PHY_MASK(mac, reg, ~tmp2); break; } } } /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RFCtrlIntcOverride */ static void bwn_nphy_rf_ctl_intc_override(struct bwn_mac *mac, enum n_intc_override intc_override, uint16_t value, uint8_t core) { uint8_t i, j; uint16_t reg, tmp, val; if (mac->mac_phy.rev >= 7) { bwn_nphy_rf_ctl_intc_override_rev7(mac, intc_override, value, core); return; } if (mac->mac_phy.rev < 3) { BWN_ERRPRINTF(mac->mac_sc, "%s: phy rev %d out of range\n", __func__, mac->mac_phy.rev); } for (i = 0; i < 2; i++) { if ((core == 1 && i == 1) || (core == 2 && !i)) continue; reg = (i == 0) ? BWN_NPHY_RFCTL_INTC1 : BWN_NPHY_RFCTL_INTC2; BWN_PHY_SET(mac, reg, 0x400); switch (intc_override) { case N_INTC_OVERRIDE_OFF: BWN_PHY_WRITE(mac, reg, 0); bwn_nphy_force_rf_sequence(mac, BWN_RFSEQ_RESET2RX); break; case N_INTC_OVERRIDE_TRSW: if (!i) { BWN_PHY_SETMASK(mac, BWN_NPHY_RFCTL_INTC1, 0xFC3F, (value << 6)); BWN_PHY_SETMASK(mac, BWN_NPHY_TXF_40CO_B1S1, 0xFFFE, 1); BWN_PHY_SET(mac, BWN_NPHY_RFCTL_CMD, BWN_NPHY_RFCTL_CMD_START); for (j = 0; j < 100; j++) { if (!(BWN_PHY_READ(mac, BWN_NPHY_RFCTL_CMD) & BWN_NPHY_RFCTL_CMD_START)) { j = 0; break; } DELAY(10); } if (j) BWN_ERRPRINTF(mac->mac_sc, "intc override timeout\n"); BWN_PHY_MASK(mac, BWN_NPHY_TXF_40CO_B1S1, 0xFFFE); } else { BWN_PHY_SETMASK(mac, BWN_NPHY_RFCTL_INTC2, 0xFC3F, (value << 6)); BWN_PHY_SETMASK(mac, BWN_NPHY_RFCTL_OVER, 0xFFFE, 1); BWN_PHY_SET(mac, BWN_NPHY_RFCTL_CMD, BWN_NPHY_RFCTL_CMD_RXTX); for (j = 0; j < 100; j++) { if (!(BWN_PHY_READ(mac, BWN_NPHY_RFCTL_CMD) & BWN_NPHY_RFCTL_CMD_RXTX)) { j = 0; break; } DELAY(10); } if (j) BWN_ERRPRINTF(mac->mac_sc, "intc override timeout\n"); BWN_PHY_MASK(mac, BWN_NPHY_RFCTL_OVER, 0xFFFE); } break; case N_INTC_OVERRIDE_PA: if (bwn_current_band(mac) == BWN_BAND_5G) { tmp = 0x0020; val = value << 5; } else { tmp = 0x0010; val = value << 4; } BWN_PHY_SETMASK(mac, reg, ~tmp, val); break; case N_INTC_OVERRIDE_EXT_LNA_PU: if (bwn_current_band(mac) == BWN_BAND_5G) { tmp = 0x0001; val = value; } else { tmp = 0x0004; val = value << 2; } BWN_PHY_SETMASK(mac, reg, ~tmp, val); break; case N_INTC_OVERRIDE_EXT_LNA_GAIN: if (bwn_current_band(mac) == BWN_BAND_5G) { tmp = 0x0002; val = value << 1; } else { tmp = 0x0008; val = value << 3; } BWN_PHY_SETMASK(mac, reg, ~tmp, val); break; } } } /************************************************** * Various PHY ops **************************************************/ /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/clip-detection */ static void bwn_nphy_write_clip_detection(struct bwn_mac *mac, const uint16_t *clip_st) { BWN_PHY_WRITE(mac, BWN_NPHY_C1_CLIP1THRES, clip_st[0]); BWN_PHY_WRITE(mac, BWN_NPHY_C2_CLIP1THRES, clip_st[1]); } /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/clip-detection */ static void bwn_nphy_read_clip_detection(struct bwn_mac *mac, uint16_t *clip_st) { clip_st[0] = BWN_PHY_READ(mac, BWN_NPHY_C1_CLIP1THRES); clip_st[1] = BWN_PHY_READ(mac, BWN_NPHY_C2_CLIP1THRES); } /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/classifier */ static uint16_t bwn_nphy_classifier(struct bwn_mac *mac, uint16_t mask, uint16_t val) { struct bwn_softc *sc = mac->mac_sc; uint16_t tmp; - if (siba_get_revid(sc->sc_dev) == 16) + if (bhnd_get_hwrev(sc->sc_dev) == 16) bwn_mac_suspend(mac); tmp = BWN_PHY_READ(mac, BWN_NPHY_CLASSCTL); tmp &= (BWN_NPHY_CLASSCTL_CCKEN | BWN_NPHY_CLASSCTL_OFDMEN | BWN_NPHY_CLASSCTL_WAITEDEN); tmp &= ~mask; tmp |= (val & mask); BWN_PHY_SETMASK(mac, BWN_NPHY_CLASSCTL, 0xFFF8, tmp); - if (siba_get_revid(sc->sc_dev) == 16) + if (bhnd_get_hwrev(sc->sc_dev) == 16) bwn_mac_enable(mac); return tmp; } /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/CCA */ static void bwn_nphy_reset_cca(struct bwn_mac *mac) { uint16_t bbcfg; bwn_phy_force_clock(mac, 1); bbcfg = BWN_PHY_READ(mac, BWN_NPHY_BBCFG); BWN_PHY_WRITE(mac, BWN_NPHY_BBCFG, bbcfg | BWN_NPHY_BBCFG_RSTCCA); DELAY(1); BWN_PHY_WRITE(mac, BWN_NPHY_BBCFG, bbcfg & ~BWN_NPHY_BBCFG_RSTCCA); bwn_phy_force_clock(mac, 0); bwn_nphy_force_rf_sequence(mac, BWN_RFSEQ_RESET2RX); } /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/carriersearch */ static void bwn_nphy_stay_in_carrier_search(struct bwn_mac *mac, bool enable) { struct bwn_phy *phy = &mac->mac_phy; struct bwn_phy_n *nphy = phy->phy_n; if (enable) { static const uint16_t clip[] = { 0xFFFF, 0xFFFF }; if (nphy->deaf_count++ == 0) { nphy->classifier_state = bwn_nphy_classifier(mac, 0, 0); bwn_nphy_classifier(mac, 0x7, BWN_NPHY_CLASSCTL_WAITEDEN); bwn_nphy_read_clip_detection(mac, nphy->clip_state); bwn_nphy_write_clip_detection(mac, clip); } bwn_nphy_reset_cca(mac); } else { if (--nphy->deaf_count == 0) { bwn_nphy_classifier(mac, 0x7, nphy->classifier_state); bwn_nphy_write_clip_detection(mac, nphy->clip_state); } } } /* http://bcm-v4.sipsolutions.net/PHY/N/Read_Lpf_Bw_Ctl */ static uint16_t bwn_nphy_read_lpf_ctl(struct bwn_mac *mac, uint16_t offset) { if (!offset) offset = bwn_is_40mhz(mac) ? 0x159 : 0x154; return bwn_ntab_read(mac, BWN_NTAB16(7, offset)) & 0x7; } /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/AdjustLnaGainTbl */ static void bwn_nphy_adjust_lna_gain_table(struct bwn_mac *mac) { struct bwn_phy_n *nphy = mac->mac_phy.phy_n; uint8_t i; int16_t tmp; uint16_t data[4]; int16_t gain[2]; uint16_t minmax[2]; static const uint16_t lna_gain[4] = { -2, 10, 19, 25 }; if (nphy->hang_avoid) bwn_nphy_stay_in_carrier_search(mac, 1); if (nphy->gain_boost) { if (bwn_current_band(mac) == BWN_BAND_2G) { gain[0] = 6; gain[1] = 6; } else { tmp = 40370 - 315 * bwn_get_chan(mac); gain[0] = ((tmp >> 13) + ((tmp >> 12) & 1)); tmp = 23242 - 224 * bwn_get_chan(mac); gain[1] = ((tmp >> 13) + ((tmp >> 12) & 1)); } } else { gain[0] = 0; gain[1] = 0; } for (i = 0; i < 2; i++) { if (nphy->elna_gain_config) { data[0] = 19 + gain[i]; data[1] = 25 + gain[i]; data[2] = 25 + gain[i]; data[3] = 25 + gain[i]; } else { data[0] = lna_gain[0] + gain[i]; data[1] = lna_gain[1] + gain[i]; data[2] = lna_gain[2] + gain[i]; data[3] = lna_gain[3] + gain[i]; } bwn_ntab_write_bulk(mac, BWN_NTAB16(i, 8), 4, data); minmax[i] = 23 + gain[i]; } BWN_PHY_SETMASK(mac, BWN_NPHY_C1_MINMAX_GAIN, ~BWN_NPHY_C1_MINGAIN, minmax[0] << BWN_NPHY_C1_MINGAIN_SHIFT); BWN_PHY_SETMASK(mac, BWN_NPHY_C2_MINMAX_GAIN, ~BWN_NPHY_C2_MINGAIN, minmax[1] << BWN_NPHY_C2_MINGAIN_SHIFT); if (nphy->hang_avoid) bwn_nphy_stay_in_carrier_search(mac, 0); } /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/SetRfSeq */ static void bwn_nphy_set_rf_sequence(struct bwn_mac *mac, uint8_t cmd, uint8_t *events, uint8_t *delays, uint8_t length) { struct bwn_phy_n *nphy = mac->mac_phy.phy_n; uint8_t i; uint8_t end = (mac->mac_phy.rev >= 3) ? 0x1F : 0x0F; uint16_t offset1 = cmd << 4; uint16_t offset2 = offset1 + 0x80; if (nphy->hang_avoid) bwn_nphy_stay_in_carrier_search(mac, true); bwn_ntab_write_bulk(mac, BWN_NTAB8(7, offset1), length, events); bwn_ntab_write_bulk(mac, BWN_NTAB8(7, offset2), length, delays); for (i = length; i < 16; i++) { bwn_ntab_write(mac, BWN_NTAB8(7, offset1 + i), end); bwn_ntab_write(mac, BWN_NTAB8(7, offset2 + i), 1); } if (nphy->hang_avoid) bwn_nphy_stay_in_carrier_search(mac, false); } /************************************************** * Radio 0x2057 **************************************************/ static void bwn_radio_2057_chantab_upload(struct bwn_mac *mac, const struct bwn_nphy_chantabent_rev7 *e_r7, const struct bwn_nphy_chantabent_rev7_2g *e_r7_2g) { if (e_r7_2g) { BWN_RF_WRITE(mac, R2057_VCOCAL_COUNTVAL0, e_r7_2g->radio_vcocal_countval0); BWN_RF_WRITE(mac, R2057_VCOCAL_COUNTVAL1, e_r7_2g->radio_vcocal_countval1); BWN_RF_WRITE(mac, R2057_RFPLL_REFMASTER_SPAREXTALSIZE, e_r7_2g->radio_rfpll_refmaster_sparextalsize); BWN_RF_WRITE(mac, R2057_RFPLL_LOOPFILTER_R1, e_r7_2g->radio_rfpll_loopfilter_r1); BWN_RF_WRITE(mac, R2057_RFPLL_LOOPFILTER_C2, e_r7_2g->radio_rfpll_loopfilter_c2); BWN_RF_WRITE(mac, R2057_RFPLL_LOOPFILTER_C1, e_r7_2g->radio_rfpll_loopfilter_c1); BWN_RF_WRITE(mac, R2057_CP_KPD_IDAC, e_r7_2g->radio_cp_kpd_idac); BWN_RF_WRITE(mac, R2057_RFPLL_MMD0, e_r7_2g->radio_rfpll_mmd0); BWN_RF_WRITE(mac, R2057_RFPLL_MMD1, e_r7_2g->radio_rfpll_mmd1); BWN_RF_WRITE(mac, R2057_VCOBUF_TUNE, e_r7_2g->radio_vcobuf_tune); BWN_RF_WRITE(mac, R2057_LOGEN_MX2G_TUNE, e_r7_2g->radio_logen_mx2g_tune); BWN_RF_WRITE(mac, R2057_LOGEN_INDBUF2G_TUNE, e_r7_2g->radio_logen_indbuf2g_tune); BWN_RF_WRITE(mac, R2057_TXMIX2G_TUNE_BOOST_PU_CORE0, e_r7_2g->radio_txmix2g_tune_boost_pu_core0); BWN_RF_WRITE(mac, R2057_PAD2G_TUNE_PUS_CORE0, e_r7_2g->radio_pad2g_tune_pus_core0); BWN_RF_WRITE(mac, R2057_LNA2G_TUNE_CORE0, e_r7_2g->radio_lna2g_tune_core0); BWN_RF_WRITE(mac, R2057_TXMIX2G_TUNE_BOOST_PU_CORE1, e_r7_2g->radio_txmix2g_tune_boost_pu_core1); BWN_RF_WRITE(mac, R2057_PAD2G_TUNE_PUS_CORE1, e_r7_2g->radio_pad2g_tune_pus_core1); BWN_RF_WRITE(mac, R2057_LNA2G_TUNE_CORE1, e_r7_2g->radio_lna2g_tune_core1); } else { BWN_RF_WRITE(mac, R2057_VCOCAL_COUNTVAL0, e_r7->radio_vcocal_countval0); BWN_RF_WRITE(mac, R2057_VCOCAL_COUNTVAL1, e_r7->radio_vcocal_countval1); BWN_RF_WRITE(mac, R2057_RFPLL_REFMASTER_SPAREXTALSIZE, e_r7->radio_rfpll_refmaster_sparextalsize); BWN_RF_WRITE(mac, R2057_RFPLL_LOOPFILTER_R1, e_r7->radio_rfpll_loopfilter_r1); BWN_RF_WRITE(mac, R2057_RFPLL_LOOPFILTER_C2, e_r7->radio_rfpll_loopfilter_c2); BWN_RF_WRITE(mac, R2057_RFPLL_LOOPFILTER_C1, e_r7->radio_rfpll_loopfilter_c1); BWN_RF_WRITE(mac, R2057_CP_KPD_IDAC, e_r7->radio_cp_kpd_idac); BWN_RF_WRITE(mac, R2057_RFPLL_MMD0, e_r7->radio_rfpll_mmd0); BWN_RF_WRITE(mac, R2057_RFPLL_MMD1, e_r7->radio_rfpll_mmd1); BWN_RF_WRITE(mac, R2057_VCOBUF_TUNE, e_r7->radio_vcobuf_tune); BWN_RF_WRITE(mac, R2057_LOGEN_MX2G_TUNE, e_r7->radio_logen_mx2g_tune); BWN_RF_WRITE(mac, R2057_LOGEN_MX5G_TUNE, e_r7->radio_logen_mx5g_tune); BWN_RF_WRITE(mac, R2057_LOGEN_INDBUF2G_TUNE, e_r7->radio_logen_indbuf2g_tune); BWN_RF_WRITE(mac, R2057_LOGEN_INDBUF5G_TUNE, e_r7->radio_logen_indbuf5g_tune); BWN_RF_WRITE(mac, R2057_TXMIX2G_TUNE_BOOST_PU_CORE0, e_r7->radio_txmix2g_tune_boost_pu_core0); BWN_RF_WRITE(mac, R2057_PAD2G_TUNE_PUS_CORE0, e_r7->radio_pad2g_tune_pus_core0); BWN_RF_WRITE(mac, R2057_PGA_BOOST_TUNE_CORE0, e_r7->radio_pga_boost_tune_core0); BWN_RF_WRITE(mac, R2057_TXMIX5G_BOOST_TUNE_CORE0, e_r7->radio_txmix5g_boost_tune_core0); BWN_RF_WRITE(mac, R2057_PAD5G_TUNE_MISC_PUS_CORE0, e_r7->radio_pad5g_tune_misc_pus_core0); BWN_RF_WRITE(mac, R2057_LNA2G_TUNE_CORE0, e_r7->radio_lna2g_tune_core0); BWN_RF_WRITE(mac, R2057_LNA5G_TUNE_CORE0, e_r7->radio_lna5g_tune_core0); BWN_RF_WRITE(mac, R2057_TXMIX2G_TUNE_BOOST_PU_CORE1, e_r7->radio_txmix2g_tune_boost_pu_core1); BWN_RF_WRITE(mac, R2057_PAD2G_TUNE_PUS_CORE1, e_r7->radio_pad2g_tune_pus_core1); BWN_RF_WRITE(mac, R2057_PGA_BOOST_TUNE_CORE1, e_r7->radio_pga_boost_tune_core1); BWN_RF_WRITE(mac, R2057_TXMIX5G_BOOST_TUNE_CORE1, e_r7->radio_txmix5g_boost_tune_core1); BWN_RF_WRITE(mac, R2057_PAD5G_TUNE_MISC_PUS_CORE1, e_r7->radio_pad5g_tune_misc_pus_core1); BWN_RF_WRITE(mac, R2057_LNA2G_TUNE_CORE1, e_r7->radio_lna2g_tune_core1); BWN_RF_WRITE(mac, R2057_LNA5G_TUNE_CORE1, e_r7->radio_lna5g_tune_core1); } } static void bwn_radio_2057_setup(struct bwn_mac *mac, const struct bwn_nphy_chantabent_rev7 *tabent_r7, const struct bwn_nphy_chantabent_rev7_2g *tabent_r7_2g) { struct bwn_phy *phy = &mac->mac_phy; bwn_radio_2057_chantab_upload(mac, tabent_r7, tabent_r7_2g); switch (phy->rf_rev) { case 0 ... 4: case 6: if (bwn_current_band(mac) == BWN_BAND_2G) { BWN_RF_WRITE(mac, R2057_RFPLL_LOOPFILTER_R1, 0x3f); BWN_RF_WRITE(mac, R2057_CP_KPD_IDAC, 0x3f); BWN_RF_WRITE(mac, R2057_RFPLL_LOOPFILTER_C1, 0x8); BWN_RF_WRITE(mac, R2057_RFPLL_LOOPFILTER_C2, 0x8); } else { BWN_RF_WRITE(mac, R2057_RFPLL_LOOPFILTER_R1, 0x1f); BWN_RF_WRITE(mac, R2057_CP_KPD_IDAC, 0x3f); BWN_RF_WRITE(mac, R2057_RFPLL_LOOPFILTER_C1, 0x8); BWN_RF_WRITE(mac, R2057_RFPLL_LOOPFILTER_C2, 0x8); } break; case 9: /* e.g. PHY rev 16 */ BWN_RF_WRITE(mac, R2057_LOGEN_PTAT_RESETS, 0x20); BWN_RF_WRITE(mac, R2057_VCOBUF_IDACS, 0x18); if (bwn_current_band(mac) == BWN_BAND_5G) { BWN_RF_WRITE(mac, R2057_LOGEN_PTAT_RESETS, 0x38); BWN_RF_WRITE(mac, R2057_VCOBUF_IDACS, 0x0f); if (bwn_is_40mhz(mac)) { /* TODO */ } else { BWN_RF_WRITE(mac, R2057_PAD_BIAS_FILTER_BWS_CORE0, 0x3c); BWN_RF_WRITE(mac, R2057_PAD_BIAS_FILTER_BWS_CORE1, 0x3c); } } break; case 14: /* 2 GHz only */ BWN_RF_WRITE(mac, R2057_RFPLL_LOOPFILTER_R1, 0x1b); BWN_RF_WRITE(mac, R2057_CP_KPD_IDAC, 0x3f); BWN_RF_WRITE(mac, R2057_RFPLL_LOOPFILTER_C1, 0x1f); BWN_RF_WRITE(mac, R2057_RFPLL_LOOPFILTER_C2, 0x1f); break; } if (bwn_current_band(mac) == BWN_BAND_2G) { uint16_t txmix2g_tune_boost_pu = 0; uint16_t pad2g_tune_pus = 0; if (bwn_nphy_ipa(mac)) { switch (phy->rf_rev) { case 9: txmix2g_tune_boost_pu = 0x0041; /* TODO */ break; case 14: txmix2g_tune_boost_pu = 0x21; pad2g_tune_pus = 0x23; break; } } if (txmix2g_tune_boost_pu) BWN_RF_WRITE(mac, R2057_TXMIX2G_TUNE_BOOST_PU_CORE0, txmix2g_tune_boost_pu); if (pad2g_tune_pus) BWN_RF_WRITE(mac, R2057_PAD2G_TUNE_PUS_CORE0, pad2g_tune_pus); if (txmix2g_tune_boost_pu) BWN_RF_WRITE(mac, R2057_TXMIX2G_TUNE_BOOST_PU_CORE1, txmix2g_tune_boost_pu); if (pad2g_tune_pus) BWN_RF_WRITE(mac, R2057_PAD2G_TUNE_PUS_CORE1, pad2g_tune_pus); } /* 50..100 */ DELAY(100); /* VCO calibration */ BWN_RF_MASK(mac, R2057_RFPLL_MISC_EN, ~0x01); BWN_RF_MASK(mac, R2057_RFPLL_MISC_CAL_RESETN, ~0x04); BWN_RF_SET(mac, R2057_RFPLL_MISC_CAL_RESETN, 0x4); BWN_RF_SET(mac, R2057_RFPLL_MISC_EN, 0x01); /* 300..600 */ DELAY(600); } /* Calibrate resistors in LPF of PLL? * http://bcm-v4.sipsolutions.net/PHY/radio205x_rcal */ static uint8_t bwn_radio_2057_rcal(struct bwn_mac *mac) { struct bwn_phy *phy = &mac->mac_phy; uint16_t saved_regs_phy[12]; uint16_t saved_regs_phy_rf[6]; uint16_t saved_regs_radio[2] = { }; static const uint16_t phy_to_store[] = { BWN_NPHY_RFCTL_RSSIO1, BWN_NPHY_RFCTL_RSSIO2, BWN_NPHY_RFCTL_LUT_TRSW_LO1, BWN_NPHY_RFCTL_LUT_TRSW_LO2, BWN_NPHY_RFCTL_RXG1, BWN_NPHY_RFCTL_RXG2, BWN_NPHY_RFCTL_TXG1, BWN_NPHY_RFCTL_TXG2, BWN_NPHY_REV7_RF_CTL_MISC_REG3, BWN_NPHY_REV7_RF_CTL_MISC_REG4, BWN_NPHY_REV7_RF_CTL_MISC_REG5, BWN_NPHY_REV7_RF_CTL_MISC_REG6, }; static const uint16_t phy_to_store_rf[] = { BWN_NPHY_REV3_RFCTL_OVER0, BWN_NPHY_REV3_RFCTL_OVER1, BWN_NPHY_REV7_RF_CTL_OVER3, BWN_NPHY_REV7_RF_CTL_OVER4, BWN_NPHY_REV7_RF_CTL_OVER5, BWN_NPHY_REV7_RF_CTL_OVER6, }; uint16_t tmp; int i; /* Save */ for (i = 0; i < nitems(phy_to_store); i++) saved_regs_phy[i] = BWN_PHY_READ(mac, phy_to_store[i]); for (i = 0; i < nitems(phy_to_store_rf); i++) saved_regs_phy_rf[i] = BWN_PHY_READ(mac, phy_to_store_rf[i]); /* Set */ for (i = 0; i < nitems(phy_to_store); i++) BWN_PHY_WRITE(mac, phy_to_store[i], 0); BWN_PHY_WRITE(mac, BWN_NPHY_REV3_RFCTL_OVER0, 0x07ff); BWN_PHY_WRITE(mac, BWN_NPHY_REV3_RFCTL_OVER1, 0x07ff); BWN_PHY_WRITE(mac, BWN_NPHY_REV7_RF_CTL_OVER3, 0x07ff); BWN_PHY_WRITE(mac, BWN_NPHY_REV7_RF_CTL_OVER4, 0x07ff); BWN_PHY_WRITE(mac, BWN_NPHY_REV7_RF_CTL_OVER5, 0x007f); BWN_PHY_WRITE(mac, BWN_NPHY_REV7_RF_CTL_OVER6, 0x007f); switch (phy->rf_rev) { case 5: BWN_PHY_MASK(mac, BWN_NPHY_REV7_RF_CTL_OVER3, ~0x2); DELAY(10); BWN_RF_SET(mac, R2057_IQTEST_SEL_PU, 0x1); BWN_RF_SETMASK(mac, R2057v7_IQTEST_SEL_PU2, ~0x2, 0x1); break; case 9: BWN_PHY_SET(mac, BWN_NPHY_REV7_RF_CTL_OVER3, 0x2); BWN_PHY_SET(mac, BWN_NPHY_REV7_RF_CTL_MISC_REG3, 0x2); saved_regs_radio[0] = BWN_RF_READ(mac, R2057_IQTEST_SEL_PU); BWN_RF_WRITE(mac, R2057_IQTEST_SEL_PU, 0x11); break; case 14: saved_regs_radio[0] = BWN_RF_READ(mac, R2057_IQTEST_SEL_PU); saved_regs_radio[1] = BWN_RF_READ(mac, R2057v7_IQTEST_SEL_PU2); BWN_PHY_SET(mac, BWN_NPHY_REV7_RF_CTL_MISC_REG3, 0x2); BWN_PHY_SET(mac, BWN_NPHY_REV7_RF_CTL_OVER3, 0x2); BWN_RF_WRITE(mac, R2057v7_IQTEST_SEL_PU2, 0x2); BWN_RF_WRITE(mac, R2057_IQTEST_SEL_PU, 0x1); break; } /* Enable */ BWN_RF_SET(mac, R2057_RCAL_CONFIG, 0x1); DELAY(10); /* Start */ BWN_RF_SET(mac, R2057_RCAL_CONFIG, 0x2); /* 100..200 */ DELAY(200); /* Stop */ BWN_RF_MASK(mac, R2057_RCAL_CONFIG, ~0x2); /* Wait and check for result */ if (!bwn_radio_wait_value(mac, R2057_RCAL_STATUS, 1, 1, 100, 1000000)) { BWN_ERRPRINTF(mac->mac_sc, "Radio 0x2057 rcal timeout\n"); return 0; } tmp = BWN_RF_READ(mac, R2057_RCAL_STATUS) & 0x3E; /* Disable */ BWN_RF_MASK(mac, R2057_RCAL_CONFIG, ~0x1); /* Restore */ for (i = 0; i < nitems(phy_to_store_rf); i++) BWN_PHY_WRITE(mac, phy_to_store_rf[i], saved_regs_phy_rf[i]); for (i = 0; i < nitems(phy_to_store); i++) BWN_PHY_WRITE(mac, phy_to_store[i], saved_regs_phy[i]); switch (phy->rf_rev) { case 0 ... 4: case 6: BWN_RF_SETMASK(mac, R2057_TEMPSENSE_CONFIG, ~0x3C, tmp); BWN_RF_SETMASK(mac, R2057_BANDGAP_RCAL_TRIM, ~0xF0, tmp << 2); break; case 5: BWN_RF_MASK(mac, R2057_IPA2G_CASCONV_CORE0, ~0x1); BWN_RF_MASK(mac, R2057v7_IQTEST_SEL_PU2, ~0x2); break; case 9: BWN_RF_WRITE(mac, R2057_IQTEST_SEL_PU, saved_regs_radio[0]); break; case 14: BWN_RF_WRITE(mac, R2057_IQTEST_SEL_PU, saved_regs_radio[0]); BWN_RF_WRITE(mac, R2057v7_IQTEST_SEL_PU2, saved_regs_radio[1]); break; } return tmp & 0x3e; } /* Calibrate the internal RC oscillator? * http://bcm-v4.sipsolutions.net/PHY/radio2057_rccal */ static uint16_t bwn_radio_2057_rccal(struct bwn_mac *mac) { struct bwn_phy *phy = &mac->mac_phy; bool special = (phy->rf_rev == 3 || phy->rf_rev == 4 || phy->rf_rev == 6); uint16_t tmp; /* Setup cal */ if (special) { BWN_RF_WRITE(mac, R2057_RCCAL_MASTER, 0x61); BWN_RF_WRITE(mac, R2057_RCCAL_TRC0, 0xC0); } else { BWN_RF_WRITE(mac, R2057v7_RCCAL_MASTER, 0x61); BWN_RF_WRITE(mac, R2057_RCCAL_TRC0, 0xE9); } BWN_RF_WRITE(mac, R2057_RCCAL_X1, 0x6E); /* Start, wait, stop */ BWN_RF_WRITE(mac, R2057_RCCAL_START_R1_Q1_P1, 0x55); if (!bwn_radio_wait_value(mac, R2057_RCCAL_DONE_OSCCAP, 2, 2, 500, 5000000)) BWN_DBGPRINTF(mac, "Radio 0x2057 rccal timeout\n"); /* 35..70 */ DELAY(70); BWN_RF_WRITE(mac, R2057_RCCAL_START_R1_Q1_P1, 0x15); /* 70..140 */ DELAY(140); /* Setup cal */ if (special) { BWN_RF_WRITE(mac, R2057_RCCAL_MASTER, 0x69); BWN_RF_WRITE(mac, R2057_RCCAL_TRC0, 0xB0); } else { BWN_RF_WRITE(mac, R2057v7_RCCAL_MASTER, 0x69); BWN_RF_WRITE(mac, R2057_RCCAL_TRC0, 0xD5); } BWN_RF_WRITE(mac, R2057_RCCAL_X1, 0x6E); /* Start, wait, stop */ /* 35..70 */ DELAY(70); BWN_RF_WRITE(mac, R2057_RCCAL_START_R1_Q1_P1, 0x55); /* 70..140 */ DELAY(140); if (!bwn_radio_wait_value(mac, R2057_RCCAL_DONE_OSCCAP, 2, 2, 500, 5000000)) BWN_DBGPRINTF(mac, "Radio 0x2057 rccal timeout\n"); /* 35..70 */ DELAY(70); BWN_RF_WRITE(mac, R2057_RCCAL_START_R1_Q1_P1, 0x15); /* 70..140 */ DELAY(140); /* Setup cal */ if (special) { BWN_RF_WRITE(mac, R2057_RCCAL_MASTER, 0x73); BWN_RF_WRITE(mac, R2057_RCCAL_X1, 0x28); BWN_RF_WRITE(mac, R2057_RCCAL_TRC0, 0xB0); } else { BWN_RF_WRITE(mac, R2057v7_RCCAL_MASTER, 0x73); BWN_RF_WRITE(mac, R2057_RCCAL_X1, 0x6E); BWN_RF_WRITE(mac, R2057_RCCAL_TRC0, 0x99); } /* Start, wait, stop */ /* 35..70 */ DELAY(70); BWN_RF_WRITE(mac, R2057_RCCAL_START_R1_Q1_P1, 0x55); /* 70..140 */ DELAY(140); if (!bwn_radio_wait_value(mac, R2057_RCCAL_DONE_OSCCAP, 2, 2, 500, 5000000)) { BWN_ERRPRINTF(mac->mac_sc, "Radio 0x2057 rcal timeout\n"); return 0; } tmp = BWN_RF_READ(mac, R2057_RCCAL_DONE_OSCCAP); /* 35..70 */ DELAY(70); BWN_RF_WRITE(mac, R2057_RCCAL_START_R1_Q1_P1, 0x15); /* 70..140 */ DELAY(140); if (special) BWN_RF_MASK(mac, R2057_RCCAL_MASTER, ~0x1); else BWN_RF_MASK(mac, R2057v7_RCCAL_MASTER, ~0x1); return tmp; } static void bwn_radio_2057_init_pre(struct bwn_mac *mac) { BWN_PHY_MASK(mac, BWN_NPHY_RFCTL_CMD, ~BWN_NPHY_RFCTL_CMD_CHIP0PU); /* Maybe wl meant to reset and set (order?) RFCTL_CMD_OEPORFORCE? */ BWN_PHY_MASK(mac, BWN_NPHY_RFCTL_CMD, BWN_NPHY_RFCTL_CMD_OEPORFORCE); BWN_PHY_SET(mac, BWN_NPHY_RFCTL_CMD, ~BWN_NPHY_RFCTL_CMD_OEPORFORCE); BWN_PHY_SET(mac, BWN_NPHY_RFCTL_CMD, BWN_NPHY_RFCTL_CMD_CHIP0PU); } static void bwn_radio_2057_init_post(struct bwn_mac *mac) { BWN_RF_SET(mac, R2057_XTALPUOVR_PINCTRL, 0x1); if (0) /* FIXME: Is this BCM43217 specific? */ BWN_RF_SET(mac, R2057_XTALPUOVR_PINCTRL, 0x2); BWN_RF_SET(mac, R2057_RFPLL_MISC_CAL_RESETN, 0x78); BWN_RF_SET(mac, R2057_XTAL_CONFIG2, 0x80); DELAY(2000); BWN_RF_MASK(mac, R2057_RFPLL_MISC_CAL_RESETN, ~0x78); BWN_RF_MASK(mac, R2057_XTAL_CONFIG2, ~0x80); if (mac->mac_phy.phy_do_full_init) { bwn_radio_2057_rcal(mac); bwn_radio_2057_rccal(mac); } BWN_RF_MASK(mac, R2057_RFPLL_MASTER, ~0x8); } /* http://bcm-v4.sipsolutions.net/802.11/Radio/2057/Init */ static void bwn_radio_2057_init(struct bwn_mac *mac) { bwn_radio_2057_init_pre(mac); r2057_upload_inittabs(mac); bwn_radio_2057_init_post(mac); } /************************************************** * Radio 0x2056 **************************************************/ static void bwn_chantab_radio_2056_upload(struct bwn_mac *mac, const struct bwn_nphy_channeltab_entry_rev3 *e) { BWN_RF_WRITE(mac, B2056_SYN_PLL_VCOCAL1, e->radio_syn_pll_vcocal1); BWN_RF_WRITE(mac, B2056_SYN_PLL_VCOCAL2, e->radio_syn_pll_vcocal2); BWN_RF_WRITE(mac, B2056_SYN_PLL_REFDIV, e->radio_syn_pll_refdiv); BWN_RF_WRITE(mac, B2056_SYN_PLL_MMD2, e->radio_syn_pll_mmd2); BWN_RF_WRITE(mac, B2056_SYN_PLL_MMD1, e->radio_syn_pll_mmd1); BWN_RF_WRITE(mac, B2056_SYN_PLL_LOOPFILTER1, e->radio_syn_pll_loopfilter1); BWN_RF_WRITE(mac, B2056_SYN_PLL_LOOPFILTER2, e->radio_syn_pll_loopfilter2); BWN_RF_WRITE(mac, B2056_SYN_PLL_LOOPFILTER3, e->radio_syn_pll_loopfilter3); BWN_RF_WRITE(mac, B2056_SYN_PLL_LOOPFILTER4, e->radio_syn_pll_loopfilter4); BWN_RF_WRITE(mac, B2056_SYN_PLL_LOOPFILTER5, e->radio_syn_pll_loopfilter5); BWN_RF_WRITE(mac, B2056_SYN_RESERVED_ADDR27, e->radio_syn_reserved_addr27); BWN_RF_WRITE(mac, B2056_SYN_RESERVED_ADDR28, e->radio_syn_reserved_addr28); BWN_RF_WRITE(mac, B2056_SYN_RESERVED_ADDR29, e->radio_syn_reserved_addr29); BWN_RF_WRITE(mac, B2056_SYN_LOGEN_VCOBUF1, e->radio_syn_logen_vcobuf1); BWN_RF_WRITE(mac, B2056_SYN_LOGEN_MIXER2, e->radio_syn_logen_mixer2); BWN_RF_WRITE(mac, B2056_SYN_LOGEN_BUF3, e->radio_syn_logen_buf3); BWN_RF_WRITE(mac, B2056_SYN_LOGEN_BUF4, e->radio_syn_logen_buf4); BWN_RF_WRITE(mac, B2056_RX0 | B2056_RX_LNAA_TUNE, e->radio_rx0_lnaa_tune); BWN_RF_WRITE(mac, B2056_RX0 | B2056_RX_LNAG_TUNE, e->radio_rx0_lnag_tune); BWN_RF_WRITE(mac, B2056_TX0 | B2056_TX_INTPAA_BOOST_TUNE, e->radio_tx0_intpaa_boost_tune); BWN_RF_WRITE(mac, B2056_TX0 | B2056_TX_INTPAG_BOOST_TUNE, e->radio_tx0_intpag_boost_tune); BWN_RF_WRITE(mac, B2056_TX0 | B2056_TX_PADA_BOOST_TUNE, e->radio_tx0_pada_boost_tune); BWN_RF_WRITE(mac, B2056_TX0 | B2056_TX_PADG_BOOST_TUNE, e->radio_tx0_padg_boost_tune); BWN_RF_WRITE(mac, B2056_TX0 | B2056_TX_PGAA_BOOST_TUNE, e->radio_tx0_pgaa_boost_tune); BWN_RF_WRITE(mac, B2056_TX0 | B2056_TX_PGAG_BOOST_TUNE, e->radio_tx0_pgag_boost_tune); BWN_RF_WRITE(mac, B2056_TX0 | B2056_TX_MIXA_BOOST_TUNE, e->radio_tx0_mixa_boost_tune); BWN_RF_WRITE(mac, B2056_TX0 | B2056_TX_MIXG_BOOST_TUNE, e->radio_tx0_mixg_boost_tune); BWN_RF_WRITE(mac, B2056_RX1 | B2056_RX_LNAA_TUNE, e->radio_rx1_lnaa_tune); BWN_RF_WRITE(mac, B2056_RX1 | B2056_RX_LNAG_TUNE, e->radio_rx1_lnag_tune); BWN_RF_WRITE(mac, B2056_TX1 | B2056_TX_INTPAA_BOOST_TUNE, e->radio_tx1_intpaa_boost_tune); BWN_RF_WRITE(mac, B2056_TX1 | B2056_TX_INTPAG_BOOST_TUNE, e->radio_tx1_intpag_boost_tune); BWN_RF_WRITE(mac, B2056_TX1 | B2056_TX_PADA_BOOST_TUNE, e->radio_tx1_pada_boost_tune); BWN_RF_WRITE(mac, B2056_TX1 | B2056_TX_PADG_BOOST_TUNE, e->radio_tx1_padg_boost_tune); BWN_RF_WRITE(mac, B2056_TX1 | B2056_TX_PGAA_BOOST_TUNE, e->radio_tx1_pgaa_boost_tune); BWN_RF_WRITE(mac, B2056_TX1 | B2056_TX_PGAG_BOOST_TUNE, e->radio_tx1_pgag_boost_tune); BWN_RF_WRITE(mac, B2056_TX1 | B2056_TX_MIXA_BOOST_TUNE, e->radio_tx1_mixa_boost_tune); BWN_RF_WRITE(mac, B2056_TX1 | B2056_TX_MIXG_BOOST_TUNE, e->radio_tx1_mixg_boost_tune); } /* http://bcm-v4.sipsolutions.net/802.11/PHY/Radio/2056Setup */ static void bwn_radio_2056_setup(struct bwn_mac *mac, const struct bwn_nphy_channeltab_entry_rev3 *e) { struct bwn_softc *sc = mac->mac_sc; bwn_band_t band = bwn_current_band(mac); uint16_t offset; uint8_t i; uint16_t bias, cbias; uint16_t pag_boost, padg_boost, pgag_boost, mixg_boost; uint16_t paa_boost, pada_boost, pgaa_boost, mixa_boost; bool is_pkg_fab_smic; DPRINTF(mac->mac_sc, BWN_DEBUG_RF, "%s: called\n", __func__); if (mac->mac_phy.rev < 3) { BWN_ERRPRINTF(mac->mac_sc, "%s: phy rev %d out of range\n", __func__, mac->mac_phy.rev); } is_pkg_fab_smic = - ((siba_get_chipid(sc->sc_dev) == BCMA_CHIP_ID_BCM43224 || - siba_get_chipid(sc->sc_dev) == BCMA_CHIP_ID_BCM43225 || - siba_get_chipid(sc->sc_dev) == BCMA_CHIP_ID_BCM43421) && - siba_get_chippkg(sc->sc_dev) == BCMA_PKG_ID_BCM43224_FAB_SMIC); + ((sc->sc_cid.chip_id == BHND_CHIPID_BCM43224 || + sc->sc_cid.chip_id == BHND_CHIPID_BCM43225 || + sc->sc_cid.chip_id == BHND_CHIPID_BCM43421) && + sc->sc_cid.chip_pkg == BHND_PKGID_BCM43224_FAB_SMIC); bwn_chantab_radio_2056_upload(mac, e); b2056_upload_syn_pll_cp2(mac, band == BWN_BAND_5G); - if (siba_sprom_get_bf2_lo(sc->sc_dev) & BWN_BFL2_GPLL_WAR && + if (sc->sc_board_info.board_flags2 & BHND_BFL2_GPLL_WAR && bwn_current_band(mac) == BWN_BAND_2G) { BWN_RF_WRITE(mac, B2056_SYN_PLL_LOOPFILTER1, 0x1F); BWN_RF_WRITE(mac, B2056_SYN_PLL_LOOPFILTER2, 0x1F); - if (siba_get_chipid(sc->sc_dev) == BCMA_CHIP_ID_BCM4716 || - siba_get_chipid(sc->sc_dev) == BCMA_CHIP_ID_BCM47162) { + if (sc->sc_cid.chip_id == BHND_CHIPID_BCM4716 || + sc->sc_cid.chip_id == BHND_CHIPID_BCM47162) { BWN_RF_WRITE(mac, B2056_SYN_PLL_LOOPFILTER4, 0x14); BWN_RF_WRITE(mac, B2056_SYN_PLL_CP2, 0); } else { BWN_RF_WRITE(mac, B2056_SYN_PLL_LOOPFILTER4, 0x0B); BWN_RF_WRITE(mac, B2056_SYN_PLL_CP2, 0x14); } } - if (siba_sprom_get_bf2_hi(sc->sc_dev) & BWN_BFH2_GPLL_WAR2 && + if (sc->sc_board_info.board_flags2 & BHND_BFL2_GPLL_WAR && bwn_current_band(mac) == BWN_BAND_2G) { BWN_RF_WRITE(mac, B2056_SYN_PLL_LOOPFILTER1, 0x1f); BWN_RF_WRITE(mac, B2056_SYN_PLL_LOOPFILTER2, 0x1f); BWN_RF_WRITE(mac, B2056_SYN_PLL_LOOPFILTER4, 0x0b); BWN_RF_WRITE(mac, B2056_SYN_PLL_CP2, 0x20); } - if (siba_sprom_get_bf2_lo(sc->sc_dev) & BWN_BFL2_APLL_WAR && + if (sc->sc_board_info.board_flags2 & BHND_BFL2_APLL_WAR && bwn_current_band(mac) == BWN_BAND_5G) { BWN_RF_WRITE(mac, B2056_SYN_PLL_LOOPFILTER1, 0x1F); BWN_RF_WRITE(mac, B2056_SYN_PLL_LOOPFILTER2, 0x1F); BWN_RF_WRITE(mac, B2056_SYN_PLL_LOOPFILTER4, 0x05); BWN_RF_WRITE(mac, B2056_SYN_PLL_CP2, 0x0C); } if (mac->mac_phy.phy_n->ipa2g_on && band == BWN_BAND_2G) { for (i = 0; i < 2; i++) { offset = i ? B2056_TX1 : B2056_TX0; if (mac->mac_phy.rev >= 5) { BWN_RF_WRITE(mac, offset | B2056_TX_PADG_IDAC, 0xcc); - if (siba_get_chipid(sc->sc_dev) == BCMA_CHIP_ID_BCM4716 || - siba_get_chipid(sc->sc_dev) == BCMA_CHIP_ID_BCM47162) { + if (sc->sc_cid.chip_id == BHND_CHIPID_BCM4716 || + sc->sc_cid.chip_id == BHND_CHIPID_BCM47162) { bias = 0x40; cbias = 0x45; pag_boost = 0x5; pgag_boost = 0x33; mixg_boost = 0x55; } else { bias = 0x25; cbias = 0x20; if (is_pkg_fab_smic) { bias = 0x2a; cbias = 0x38; } pag_boost = 0x4; pgag_boost = 0x03; mixg_boost = 0x65; } padg_boost = 0x77; BWN_RF_WRITE(mac, offset | B2056_TX_INTPAG_IMAIN_STAT, bias); BWN_RF_WRITE(mac, offset | B2056_TX_INTPAG_IAUX_STAT, bias); BWN_RF_WRITE(mac, offset | B2056_TX_INTPAG_CASCBIAS, cbias); BWN_RF_WRITE(mac, offset | B2056_TX_INTPAG_BOOST_TUNE, pag_boost); BWN_RF_WRITE(mac, offset | B2056_TX_PGAG_BOOST_TUNE, pgag_boost); BWN_RF_WRITE(mac, offset | B2056_TX_PADG_BOOST_TUNE, padg_boost); BWN_RF_WRITE(mac, offset | B2056_TX_MIXG_BOOST_TUNE, mixg_boost); } else { bias = bwn_is_40mhz(mac) ? 0x40 : 0x20; BWN_RF_WRITE(mac, offset | B2056_TX_INTPAG_IMAIN_STAT, bias); BWN_RF_WRITE(mac, offset | B2056_TX_INTPAG_IAUX_STAT, bias); BWN_RF_WRITE(mac, offset | B2056_TX_INTPAG_CASCBIAS, 0x30); } BWN_RF_WRITE(mac, offset | B2056_TX_PA_SPARE1, 0xee); } } else if (mac->mac_phy.phy_n->ipa5g_on && band == BWN_BAND_5G) { uint16_t freq = bwn_get_centre_freq(mac); /* XXX 5g low/med/high? */ if (freq < 5100) { paa_boost = 0xA; pada_boost = 0x77; pgaa_boost = 0xF; mixa_boost = 0xF; } else if (freq < 5340) { paa_boost = 0x8; pada_boost = 0x77; pgaa_boost = 0xFB; mixa_boost = 0xF; } else if (freq < 5650) { paa_boost = 0x0; pada_boost = 0x77; pgaa_boost = 0xB; mixa_boost = 0xF; } else { paa_boost = 0x0; pada_boost = 0x77; if (freq != 5825) pgaa_boost = -(freq - 18) / 36 + 168; else pgaa_boost = 6; mixa_boost = 0xF; } cbias = is_pkg_fab_smic ? 0x35 : 0x30; for (i = 0; i < 2; i++) { offset = i ? B2056_TX1 : B2056_TX0; BWN_RF_WRITE(mac, offset | B2056_TX_INTPAA_BOOST_TUNE, paa_boost); BWN_RF_WRITE(mac, offset | B2056_TX_PADA_BOOST_TUNE, pada_boost); BWN_RF_WRITE(mac, offset | B2056_TX_PGAA_BOOST_TUNE, pgaa_boost); BWN_RF_WRITE(mac, offset | B2056_TX_MIXA_BOOST_TUNE, mixa_boost); BWN_RF_WRITE(mac, offset | B2056_TX_TXSPARE1, 0x30); BWN_RF_WRITE(mac, offset | B2056_TX_PA_SPARE2, 0xee); BWN_RF_WRITE(mac, offset | B2056_TX_PADA_CASCBIAS, 0x03); BWN_RF_WRITE(mac, offset | B2056_TX_INTPAA_IAUX_STAT, 0x30); BWN_RF_WRITE(mac, offset | B2056_TX_INTPAA_IMAIN_STAT, 0x30); BWN_RF_WRITE(mac, offset | B2056_TX_INTPAA_CASCBIAS, cbias); } } DELAY(50); /* VCO calibration */ BWN_RF_WRITE(mac, B2056_SYN_PLL_VCOCAL12, 0x00); BWN_RF_WRITE(mac, B2056_TX_INTPAA_PA_MISC, 0x38); BWN_RF_WRITE(mac, B2056_TX_INTPAA_PA_MISC, 0x18); BWN_RF_WRITE(mac, B2056_TX_INTPAA_PA_MISC, 0x38); BWN_RF_WRITE(mac, B2056_TX_INTPAA_PA_MISC, 0x39); DELAY(300); } static uint8_t bwn_radio_2056_rcal(struct bwn_mac *mac) { struct bwn_phy *phy = &mac->mac_phy; uint16_t mast2, tmp; if (phy->rev != 3) return 0; DPRINTF(mac->mac_sc, BWN_DEBUG_RF, "%s: called\n", __func__); mast2 = BWN_RF_READ(mac, B2056_SYN_PLL_MAST2); BWN_RF_WRITE(mac, B2056_SYN_PLL_MAST2, mast2 | 0x7); DELAY(10); BWN_RF_WRITE(mac, B2056_SYN_RCAL_MASTER, 0x01); DELAY(10); BWN_RF_WRITE(mac, B2056_SYN_RCAL_MASTER, 0x09); if (!bwn_radio_wait_value(mac, B2056_SYN_RCAL_CODE_OUT, 0x80, 0x80, 100, 1000000)) { BWN_ERRPRINTF(mac->mac_sc, "Radio recalibration timeout\n"); return 0; } BWN_RF_WRITE(mac, B2056_SYN_RCAL_MASTER, 0x01); tmp = BWN_RF_READ(mac, B2056_SYN_RCAL_CODE_OUT); BWN_RF_WRITE(mac, B2056_SYN_RCAL_MASTER, 0x00); BWN_RF_WRITE(mac, B2056_SYN_PLL_MAST2, mast2); return tmp & 0x1f; } static void bwn_radio_init2056_pre(struct bwn_mac *mac) { DPRINTF(mac->mac_sc, BWN_DEBUG_RF, "%s: called\n", __func__); BWN_PHY_MASK(mac, BWN_NPHY_RFCTL_CMD, ~BWN_NPHY_RFCTL_CMD_CHIP0PU); /* Maybe wl meant to reset and set (order?) RFCTL_CMD_OEPORFORCE? */ BWN_PHY_MASK(mac, BWN_NPHY_RFCTL_CMD, BWN_NPHY_RFCTL_CMD_OEPORFORCE); BWN_PHY_SET(mac, BWN_NPHY_RFCTL_CMD, ~BWN_NPHY_RFCTL_CMD_OEPORFORCE); BWN_PHY_SET(mac, BWN_NPHY_RFCTL_CMD, BWN_NPHY_RFCTL_CMD_CHIP0PU); } static void bwn_radio_init2056_post(struct bwn_mac *mac) { DPRINTF(mac->mac_sc, BWN_DEBUG_RF, "%s: called\n", __func__); BWN_RF_SET(mac, B2056_SYN_COM_CTRL, 0xB); BWN_RF_SET(mac, B2056_SYN_COM_PU, 0x2); BWN_RF_SET(mac, B2056_SYN_COM_RESET, 0x2); DELAY(1000); BWN_RF_MASK(mac, B2056_SYN_COM_RESET, ~0x2); BWN_RF_MASK(mac, B2056_SYN_PLL_MAST2, ~0xFC); BWN_RF_MASK(mac, B2056_SYN_RCCAL_CTRL0, ~0x1); if (mac->mac_phy.phy_do_full_init) bwn_radio_2056_rcal(mac); } /* * Initialize a Broadcom 2056 N-radio * http://bcm-v4.sipsolutions.net/802.11/Radio/2056/Init */ static void bwn_radio_init2056(struct bwn_mac *mac) { DPRINTF(mac->mac_sc, BWN_DEBUG_RF, "%s: called\n", __func__); bwn_radio_init2056_pre(mac); b2056_upload_inittabs(mac, 0, 0); bwn_radio_init2056_post(mac); } /************************************************** * Radio 0x2055 **************************************************/ static void bwn_chantab_radio_upload(struct bwn_mac *mac, const struct bwn_nphy_channeltab_entry_rev2 *e) { BWN_RF_WRITE(mac, B2055_PLL_REF, e->radio_pll_ref); BWN_RF_WRITE(mac, B2055_RF_PLLMOD0, e->radio_rf_pllmod0); BWN_RF_WRITE(mac, B2055_RF_PLLMOD1, e->radio_rf_pllmod1); BWN_RF_WRITE(mac, B2055_VCO_CAPTAIL, e->radio_vco_captail); BWN_READ_4(mac, BWN_MACCTL); /* flush writes */ BWN_RF_WRITE(mac, B2055_VCO_CAL1, e->radio_vco_cal1); BWN_RF_WRITE(mac, B2055_VCO_CAL2, e->radio_vco_cal2); BWN_RF_WRITE(mac, B2055_PLL_LFC1, e->radio_pll_lfc1); BWN_RF_WRITE(mac, B2055_PLL_LFR1, e->radio_pll_lfr1); BWN_READ_4(mac, BWN_MACCTL); /* flush writes */ BWN_RF_WRITE(mac, B2055_PLL_LFC2, e->radio_pll_lfc2); BWN_RF_WRITE(mac, B2055_LGBUF_CENBUF, e->radio_lgbuf_cenbuf); BWN_RF_WRITE(mac, B2055_LGEN_TUNE1, e->radio_lgen_tune1); BWN_RF_WRITE(mac, B2055_LGEN_TUNE2, e->radio_lgen_tune2); BWN_READ_4(mac, BWN_MACCTL); /* flush writes */ BWN_RF_WRITE(mac, B2055_C1_LGBUF_ATUNE, e->radio_c1_lgbuf_atune); BWN_RF_WRITE(mac, B2055_C1_LGBUF_GTUNE, e->radio_c1_lgbuf_gtune); BWN_RF_WRITE(mac, B2055_C1_RX_RFR1, e->radio_c1_rx_rfr1); BWN_RF_WRITE(mac, B2055_C1_TX_PGAPADTN, e->radio_c1_tx_pgapadtn); BWN_READ_4(mac, BWN_MACCTL); /* flush writes */ BWN_RF_WRITE(mac, B2055_C1_TX_MXBGTRIM, e->radio_c1_tx_mxbgtrim); BWN_RF_WRITE(mac, B2055_C2_LGBUF_ATUNE, e->radio_c2_lgbuf_atune); BWN_RF_WRITE(mac, B2055_C2_LGBUF_GTUNE, e->radio_c2_lgbuf_gtune); BWN_RF_WRITE(mac, B2055_C2_RX_RFR1, e->radio_c2_rx_rfr1); BWN_READ_4(mac, BWN_MACCTL); /* flush writes */ BWN_RF_WRITE(mac, B2055_C2_TX_PGAPADTN, e->radio_c2_tx_pgapadtn); BWN_RF_WRITE(mac, B2055_C2_TX_MXBGTRIM, e->radio_c2_tx_mxbgtrim); } /* http://bcm-v4.sipsolutions.net/802.11/PHY/Radio/2055Setup */ static void bwn_radio_2055_setup(struct bwn_mac *mac, const struct bwn_nphy_channeltab_entry_rev2 *e) { if (mac->mac_phy.rev >= 3) { BWN_ERRPRINTF(mac->mac_sc, "%s: phy rev %d out of range\n", __func__, mac->mac_phy.rev); } DPRINTF(mac->mac_sc, BWN_DEBUG_RF, "%s: called\n", __func__); bwn_chantab_radio_upload(mac, e); DELAY(50); BWN_RF_WRITE(mac, B2055_VCO_CAL10, 0x05); BWN_RF_WRITE(mac, B2055_VCO_CAL10, 0x45); BWN_READ_4(mac, BWN_MACCTL); /* flush writes */ BWN_RF_WRITE(mac, B2055_VCO_CAL10, 0x65); DELAY(300); } static void bwn_radio_init2055_pre(struct bwn_mac *mac) { BWN_PHY_MASK(mac, BWN_NPHY_RFCTL_CMD, ~BWN_NPHY_RFCTL_CMD_PORFORCE); BWN_PHY_SET(mac, BWN_NPHY_RFCTL_CMD, BWN_NPHY_RFCTL_CMD_CHIP0PU | BWN_NPHY_RFCTL_CMD_OEPORFORCE); BWN_PHY_SET(mac, BWN_NPHY_RFCTL_CMD, BWN_NPHY_RFCTL_CMD_PORFORCE); } static void bwn_radio_init2055_post(struct bwn_mac *mac) { struct bwn_softc *sc = mac->mac_sc; struct bwn_phy_n *nphy = mac->mac_phy.phy_n; bool workaround = false; - if (siba_get_revid(sc->sc_dev) < 4) + if (bhnd_get_hwrev(sc->sc_dev) < 4) workaround = - (siba_get_pci_subvendor(sc->sc_dev) != SIBA_BOARDVENDOR_BCM) - && (siba_get_pci_subdevice(sc->sc_dev) == SIBA_BOARD_BCM4321) - && (siba_sprom_get_brev(sc->sc_dev) >= 0x41); + (sc->sc_board_info.board_vendor != PCI_VENDOR_BROADCOM) + && (sc->sc_board_info.board_type == BHND_BOARD_BCM4321CB2) + && (sc->sc_board_info.board_rev >= 0x41); else workaround = - !(siba_sprom_get_bf2_lo(sc->sc_dev) & BWN_BFL2_RXBB_INT_REG_DIS); + !(sc->sc_board_info.board_flags2 & BHND_BFL2_RXBB_INT_REG_DIS); BWN_RF_MASK(mac, B2055_MASTER1, 0xFFF3); if (workaround) { BWN_RF_MASK(mac, B2055_C1_RX_BB_REG, 0x7F); BWN_RF_MASK(mac, B2055_C2_RX_BB_REG, 0x7F); } BWN_RF_SETMASK(mac, B2055_RRCCAL_NOPTSEL, 0xFFC0, 0x2C); BWN_RF_WRITE(mac, B2055_CAL_MISC, 0x3C); BWN_RF_MASK(mac, B2055_CAL_MISC, 0xFFBE); BWN_RF_SET(mac, B2055_CAL_LPOCTL, 0x80); BWN_RF_SET(mac, B2055_CAL_MISC, 0x1); DELAY(1000); BWN_RF_SET(mac, B2055_CAL_MISC, 0x40); if (!bwn_radio_wait_value(mac, B2055_CAL_COUT2, 0x80, 0x80, 10, 2000)) BWN_ERRPRINTF(mac->mac_sc, "radio post init timeout\n"); BWN_RF_MASK(mac, B2055_CAL_LPOCTL, 0xFF7F); bwn_switch_channel(mac, bwn_get_chan(mac)); BWN_RF_WRITE(mac, B2055_C1_RX_BB_LPF, 0x9); BWN_RF_WRITE(mac, B2055_C2_RX_BB_LPF, 0x9); BWN_RF_WRITE(mac, B2055_C1_RX_BB_MIDACHP, 0x83); BWN_RF_WRITE(mac, B2055_C2_RX_BB_MIDACHP, 0x83); BWN_RF_SETMASK(mac, B2055_C1_LNA_GAINBST, 0xFFF8, 0x6); BWN_RF_SETMASK(mac, B2055_C2_LNA_GAINBST, 0xFFF8, 0x6); if (!nphy->gain_boost) { BWN_RF_SET(mac, B2055_C1_RX_RFSPC1, 0x2); BWN_RF_SET(mac, B2055_C2_RX_RFSPC1, 0x2); } else { BWN_RF_MASK(mac, B2055_C1_RX_RFSPC1, 0xFFFD); BWN_RF_MASK(mac, B2055_C2_RX_RFSPC1, 0xFFFD); } DELAY(2); } /* * Initialize a Broadcom 2055 N-radio * http://bcm-v4.sipsolutions.net/802.11/Radio/2055/Init */ static void bwn_radio_init2055(struct bwn_mac *mac) { bwn_radio_init2055_pre(mac); if (mac->mac_status < BWN_MAC_STATUS_INITED) { /* Follow wl, not specs. Do not force uploading all regs */ b2055_upload_inittab(mac, 0, 0); } else { bool ghz5 = bwn_current_band(mac) == BWN_BAND_5G; b2055_upload_inittab(mac, ghz5, 0); } bwn_radio_init2055_post(mac); } /************************************************** * Samples **************************************************/ /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/LoadSampleTable */ static int bwn_nphy_load_samples(struct bwn_mac *mac, struct bwn_c32 *samples, uint16_t len) { struct bwn_phy_n *nphy = mac->mac_phy.phy_n; uint16_t i; uint32_t *data; data = malloc(len * sizeof(uint32_t), M_DEVBUF, M_NOWAIT | M_ZERO); if (!data) { BWN_ERRPRINTF(mac->mac_sc, "allocation for samples loading failed\n"); return -ENOMEM; } if (nphy->hang_avoid) bwn_nphy_stay_in_carrier_search(mac, 1); for (i = 0; i < len; i++) { data[i] = (samples[i].i & 0x3FF << 10); data[i] |= samples[i].q & 0x3FF; } bwn_ntab_write_bulk(mac, BWN_NTAB32(17, 0), len, data); free(data, M_DEVBUF); if (nphy->hang_avoid) bwn_nphy_stay_in_carrier_search(mac, 0); return 0; } /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/GenLoadSamples */ static uint16_t bwn_nphy_gen_load_samples(struct bwn_mac *mac, uint32_t freq, uint16_t max, bool test) { int i; uint16_t bw, len, rot, angle; struct bwn_c32 *samples; bw = bwn_is_40mhz(mac) ? 40 : 20; len = bw << 3; if (test) { if (BWN_PHY_READ(mac, BWN_NPHY_BBCFG) & BWN_NPHY_BBCFG_RSTRX) bw = 82; else bw = 80; if (bwn_is_40mhz(mac)) bw <<= 1; len = bw << 1; } samples = malloc(len * sizeof(struct bwn_c32), M_DEVBUF, M_NOWAIT | M_ZERO); if (!samples) { BWN_ERRPRINTF(mac->mac_sc, "allocation for samples generation failed\n"); return 0; } rot = (((freq * 36) / bw) << 16) / 100; angle = 0; for (i = 0; i < len; i++) { samples[i] = bwn_cordic(angle); angle += rot; samples[i].q = CORDIC_CONVERT(samples[i].q * max); samples[i].i = CORDIC_CONVERT(samples[i].i * max); } i = bwn_nphy_load_samples(mac, samples, len); free(samples, M_DEVBUF); return (i < 0) ? 0 : len; } /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RunSamples */ static void bwn_nphy_run_samples(struct bwn_mac *mac, uint16_t samps, uint16_t loops, uint16_t wait, bool iqmode, bool dac_test, bool modify_bbmult) { struct bwn_phy *phy = &mac->mac_phy; struct bwn_phy_n *nphy = mac->mac_phy.phy_n; int i; uint16_t seq_mode; uint32_t tmp; bwn_nphy_stay_in_carrier_search(mac, true); if (phy->rev >= 7) { bool lpf_bw3, lpf_bw4; lpf_bw3 = BWN_PHY_READ(mac, BWN_NPHY_REV7_RF_CTL_OVER3) & 0x80; lpf_bw4 = BWN_PHY_READ(mac, BWN_NPHY_REV7_RF_CTL_OVER4) & 0x80; if (lpf_bw3 || lpf_bw4) { /* TODO */ } else { uint16_t value = bwn_nphy_read_lpf_ctl(mac, 0); if (phy->rev >= 19) bwn_nphy_rf_ctl_override_rev19(mac, 0x80, value, 0, false, 1); else bwn_nphy_rf_ctl_override_rev7(mac, 0x80, value, 0, false, 1); nphy->lpf_bw_overrode_for_sample_play = true; } } if ((nphy->bb_mult_save & 0x80000000) == 0) { tmp = bwn_ntab_read(mac, BWN_NTAB16(15, 87)); nphy->bb_mult_save = (tmp & 0xFFFF) | 0x80000000; } if (modify_bbmult) { tmp = !bwn_is_40mhz(mac) ? 0x6464 : 0x4747; bwn_ntab_write(mac, BWN_NTAB16(15, 87), tmp); } BWN_PHY_WRITE(mac, BWN_NPHY_SAMP_DEPCNT, (samps - 1)); if (loops != 0xFFFF) BWN_PHY_WRITE(mac, BWN_NPHY_SAMP_LOOPCNT, (loops - 1)); else BWN_PHY_WRITE(mac, BWN_NPHY_SAMP_LOOPCNT, loops); BWN_PHY_WRITE(mac, BWN_NPHY_SAMP_WAITCNT, wait); seq_mode = BWN_PHY_READ(mac, BWN_NPHY_RFSEQMODE); BWN_PHY_SET(mac, BWN_NPHY_RFSEQMODE, BWN_NPHY_RFSEQMODE_CAOVER); if (iqmode) { BWN_PHY_MASK(mac, BWN_NPHY_IQLOCAL_CMDGCTL, 0x7FFF); BWN_PHY_SET(mac, BWN_NPHY_IQLOCAL_CMDGCTL, 0x8000); } else { tmp = dac_test ? 5 : 1; BWN_PHY_WRITE(mac, BWN_NPHY_SAMP_CMD, tmp); } for (i = 0; i < 100; i++) { if (!(BWN_PHY_READ(mac, BWN_NPHY_RFSEQST) & 1)) { i = 0; break; } DELAY(10); } if (i) BWN_ERRPRINTF(mac->mac_sc, "run samples timeout\n"); BWN_PHY_WRITE(mac, BWN_NPHY_RFSEQMODE, seq_mode); bwn_nphy_stay_in_carrier_search(mac, false); } /************************************************** * RSSI **************************************************/ /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/ScaleOffsetRssi */ static void bwn_nphy_scale_offset_rssi(struct bwn_mac *mac, uint16_t scale, int8_t offset, uint8_t core, enum n_rail_type rail, enum n_rssi_type rssi_type) { uint16_t tmp; bool core1or5 = (core == 1) || (core == 5); bool core2or5 = (core == 2) || (core == 5); offset = bwn_clamp_val(offset, -32, 31); tmp = ((scale & 0x3F) << 8) | (offset & 0x3F); switch (rssi_type) { case N_RSSI_NB: if (core1or5 && rail == N_RAIL_I) BWN_PHY_WRITE(mac, BWN_NPHY_RSSIMC_0I_RSSI_Z, tmp); if (core1or5 && rail == N_RAIL_Q) BWN_PHY_WRITE(mac, BWN_NPHY_RSSIMC_0Q_RSSI_Z, tmp); if (core2or5 && rail == N_RAIL_I) BWN_PHY_WRITE(mac, BWN_NPHY_RSSIMC_1I_RSSI_Z, tmp); if (core2or5 && rail == N_RAIL_Q) BWN_PHY_WRITE(mac, BWN_NPHY_RSSIMC_1Q_RSSI_Z, tmp); break; case N_RSSI_W1: if (core1or5 && rail == N_RAIL_I) BWN_PHY_WRITE(mac, BWN_NPHY_RSSIMC_0I_RSSI_X, tmp); if (core1or5 && rail == N_RAIL_Q) BWN_PHY_WRITE(mac, BWN_NPHY_RSSIMC_0Q_RSSI_X, tmp); if (core2or5 && rail == N_RAIL_I) BWN_PHY_WRITE(mac, BWN_NPHY_RSSIMC_1I_RSSI_X, tmp); if (core2or5 && rail == N_RAIL_Q) BWN_PHY_WRITE(mac, BWN_NPHY_RSSIMC_1Q_RSSI_X, tmp); break; case N_RSSI_W2: if (core1or5 && rail == N_RAIL_I) BWN_PHY_WRITE(mac, BWN_NPHY_RSSIMC_0I_RSSI_Y, tmp); if (core1or5 && rail == N_RAIL_Q) BWN_PHY_WRITE(mac, BWN_NPHY_RSSIMC_0Q_RSSI_Y, tmp); if (core2or5 && rail == N_RAIL_I) BWN_PHY_WRITE(mac, BWN_NPHY_RSSIMC_1I_RSSI_Y, tmp); if (core2or5 && rail == N_RAIL_Q) BWN_PHY_WRITE(mac, BWN_NPHY_RSSIMC_1Q_RSSI_Y, tmp); break; case N_RSSI_TBD: if (core1or5 && rail == N_RAIL_I) BWN_PHY_WRITE(mac, BWN_NPHY_RSSIMC_0I_TBD, tmp); if (core1or5 && rail == N_RAIL_Q) BWN_PHY_WRITE(mac, BWN_NPHY_RSSIMC_0Q_TBD, tmp); if (core2or5 && rail == N_RAIL_I) BWN_PHY_WRITE(mac, BWN_NPHY_RSSIMC_1I_TBD, tmp); if (core2or5 && rail == N_RAIL_Q) BWN_PHY_WRITE(mac, BWN_NPHY_RSSIMC_1Q_TBD, tmp); break; case N_RSSI_IQ: if (core1or5 && rail == N_RAIL_I) BWN_PHY_WRITE(mac, BWN_NPHY_RSSIMC_0I_PWRDET, tmp); if (core1or5 && rail == N_RAIL_Q) BWN_PHY_WRITE(mac, BWN_NPHY_RSSIMC_0Q_PWRDET, tmp); if (core2or5 && rail == N_RAIL_I) BWN_PHY_WRITE(mac, BWN_NPHY_RSSIMC_1I_PWRDET, tmp); if (core2or5 && rail == N_RAIL_Q) BWN_PHY_WRITE(mac, BWN_NPHY_RSSIMC_1Q_PWRDET, tmp); break; case N_RSSI_TSSI_2G: if (core1or5) BWN_PHY_WRITE(mac, BWN_NPHY_RSSIMC_0I_TSSI, tmp); if (core2or5) BWN_PHY_WRITE(mac, BWN_NPHY_RSSIMC_1I_TSSI, tmp); break; case N_RSSI_TSSI_5G: if (core1or5) BWN_PHY_WRITE(mac, BWN_NPHY_RSSIMC_0Q_TSSI, tmp); if (core2or5) BWN_PHY_WRITE(mac, BWN_NPHY_RSSIMC_1Q_TSSI, tmp); break; } } static void bwn_nphy_rssi_select_rev19(struct bwn_mac *mac, uint8_t code, enum n_rssi_type rssi_type) { /* TODO */ } static void bwn_nphy_rev3_rssi_select(struct bwn_mac *mac, uint8_t code, enum n_rssi_type rssi_type) { uint8_t i; uint16_t reg, val; if (code == 0) { BWN_PHY_MASK(mac, BWN_NPHY_AFECTL_OVER1, 0xFDFF); BWN_PHY_MASK(mac, BWN_NPHY_AFECTL_OVER, 0xFDFF); BWN_PHY_MASK(mac, BWN_NPHY_AFECTL_C1, 0xFCFF); BWN_PHY_MASK(mac, BWN_NPHY_AFECTL_C2, 0xFCFF); BWN_PHY_MASK(mac, BWN_NPHY_TXF_40CO_B1S0, 0xFFDF); BWN_PHY_MASK(mac, BWN_NPHY_TXF_40CO_B32S1, 0xFFDF); BWN_PHY_MASK(mac, BWN_NPHY_RFCTL_LUT_TRSW_UP1, 0xFFC3); BWN_PHY_MASK(mac, BWN_NPHY_RFCTL_LUT_TRSW_UP2, 0xFFC3); } else { for (i = 0; i < 2; i++) { if ((code == 1 && i == 1) || (code == 2 && !i)) continue; reg = (i == 0) ? BWN_NPHY_AFECTL_OVER1 : BWN_NPHY_AFECTL_OVER; BWN_PHY_SETMASK(mac, reg, 0xFDFF, 0x0200); if (rssi_type == N_RSSI_W1 || rssi_type == N_RSSI_W2 || rssi_type == N_RSSI_NB) { reg = (i == 0) ? BWN_NPHY_AFECTL_C1 : BWN_NPHY_AFECTL_C2; BWN_PHY_SETMASK(mac, reg, 0xFCFF, 0); reg = (i == 0) ? BWN_NPHY_RFCTL_LUT_TRSW_UP1 : BWN_NPHY_RFCTL_LUT_TRSW_UP2; BWN_PHY_SETMASK(mac, reg, 0xFFC3, 0); if (rssi_type == N_RSSI_W1) val = (bwn_current_band(mac) == BWN_BAND_5G) ? 4 : 8; else if (rssi_type == N_RSSI_W2) val = 16; else val = 32; BWN_PHY_SET(mac, reg, val); reg = (i == 0) ? BWN_NPHY_TXF_40CO_B1S0 : BWN_NPHY_TXF_40CO_B32S1; BWN_PHY_SET(mac, reg, 0x0020); } else { if (rssi_type == N_RSSI_TBD) val = 0x0100; else if (rssi_type == N_RSSI_IQ) val = 0x0200; else val = 0x0300; reg = (i == 0) ? BWN_NPHY_AFECTL_C1 : BWN_NPHY_AFECTL_C2; BWN_PHY_SETMASK(mac, reg, 0xFCFF, val); BWN_PHY_SETMASK(mac, reg, 0xF3FF, val << 2); if (rssi_type != N_RSSI_IQ && rssi_type != N_RSSI_TBD) { bwn_band_t band = bwn_current_band(mac); if (mac->mac_phy.rev < 7) { if (bwn_nphy_ipa(mac)) val = (band == BWN_BAND_5G) ? 0xC : 0xE; else val = 0x11; reg = (i == 0) ? B2056_TX0 : B2056_TX1; reg |= B2056_TX_TX_SSI_MUX; BWN_RF_WRITE(mac, reg, val); } reg = (i == 0) ? BWN_NPHY_AFECTL_OVER1 : BWN_NPHY_AFECTL_OVER; BWN_PHY_SET(mac, reg, 0x0200); } } } } } static void bwn_nphy_rev2_rssi_select(struct bwn_mac *mac, uint8_t code, enum n_rssi_type rssi_type) { uint16_t val; bool rssi_w1_w2_nb = false; switch (rssi_type) { case N_RSSI_W1: case N_RSSI_W2: case N_RSSI_NB: val = 0; rssi_w1_w2_nb = true; break; case N_RSSI_TBD: val = 1; break; case N_RSSI_IQ: val = 2; break; default: val = 3; } val = (val << 12) | (val << 14); BWN_PHY_SETMASK(mac, BWN_NPHY_AFECTL_C1, 0x0FFF, val); BWN_PHY_SETMASK(mac, BWN_NPHY_AFECTL_C2, 0x0FFF, val); if (rssi_w1_w2_nb) { BWN_PHY_SETMASK(mac, BWN_NPHY_RFCTL_RSSIO1, 0xFFCF, (rssi_type + 1) << 4); BWN_PHY_SETMASK(mac, BWN_NPHY_RFCTL_RSSIO2, 0xFFCF, (rssi_type + 1) << 4); } if (code == 0) { BWN_PHY_MASK(mac, BWN_NPHY_AFECTL_OVER, ~0x3000); if (rssi_w1_w2_nb) { BWN_PHY_MASK(mac, BWN_NPHY_RFCTL_CMD, ~(BWN_NPHY_RFCTL_CMD_RXEN | BWN_NPHY_RFCTL_CMD_CORESEL)); BWN_PHY_MASK(mac, BWN_NPHY_RFCTL_OVER, ~(0x1 << 12 | 0x1 << 5 | 0x1 << 1 | 0x1)); BWN_PHY_MASK(mac, BWN_NPHY_RFCTL_CMD, ~BWN_NPHY_RFCTL_CMD_START); DELAY(20); BWN_PHY_MASK(mac, BWN_NPHY_RFCTL_OVER, ~0x1); } } else { BWN_PHY_SET(mac, BWN_NPHY_AFECTL_OVER, 0x3000); if (rssi_w1_w2_nb) { BWN_PHY_SETMASK(mac, BWN_NPHY_RFCTL_CMD, ~(BWN_NPHY_RFCTL_CMD_RXEN | BWN_NPHY_RFCTL_CMD_CORESEL), (BWN_NPHY_RFCTL_CMD_RXEN | code << BWN_NPHY_RFCTL_CMD_CORESEL_SHIFT)); BWN_PHY_SET(mac, BWN_NPHY_RFCTL_OVER, (0x1 << 12 | 0x1 << 5 | 0x1 << 1 | 0x1)); BWN_PHY_SET(mac, BWN_NPHY_RFCTL_CMD, BWN_NPHY_RFCTL_CMD_START); DELAY(20); BWN_PHY_MASK(mac, BWN_NPHY_RFCTL_OVER, ~0x1); } } } /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RSSISel */ static void bwn_nphy_rssi_select(struct bwn_mac *mac, uint8_t code, enum n_rssi_type type) { if (mac->mac_phy.rev >= 19) bwn_nphy_rssi_select_rev19(mac, code, type); else if (mac->mac_phy.rev >= 3) bwn_nphy_rev3_rssi_select(mac, code, type); else bwn_nphy_rev2_rssi_select(mac, code, type); } /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/SetRssi2055Vcm */ static void bwn_nphy_set_rssi_2055_vcm(struct bwn_mac *mac, enum n_rssi_type rssi_type, uint8_t *buf) { int i; for (i = 0; i < 2; i++) { if (rssi_type == N_RSSI_NB) { if (i == 0) { BWN_RF_SETMASK(mac, B2055_C1_B0NB_RSSIVCM, 0xFC, buf[0]); BWN_RF_SETMASK(mac, B2055_C1_RX_BB_RSSICTL5, 0xFC, buf[1]); } else { BWN_RF_SETMASK(mac, B2055_C2_B0NB_RSSIVCM, 0xFC, buf[2 * i]); BWN_RF_SETMASK(mac, B2055_C2_RX_BB_RSSICTL5, 0xFC, buf[2 * i + 1]); } } else { if (i == 0) BWN_RF_SETMASK(mac, B2055_C1_RX_BB_RSSICTL5, 0xF3, buf[0] << 2); else BWN_RF_SETMASK(mac, B2055_C2_RX_BB_RSSICTL5, 0xF3, buf[2 * i + 1] << 2); } } } /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/PollRssi */ static int bwn_nphy_poll_rssi(struct bwn_mac *mac, enum n_rssi_type rssi_type, int32_t *buf, uint8_t nsamp) { int i; int out; uint16_t save_regs_phy[9]; uint16_t s[2]; /* TODO: rev7+ is treated like rev3+, what about rev19+? */ if (mac->mac_phy.rev >= 3) { save_regs_phy[0] = BWN_PHY_READ(mac, BWN_NPHY_AFECTL_C1); save_regs_phy[1] = BWN_PHY_READ(mac, BWN_NPHY_AFECTL_C2); save_regs_phy[2] = BWN_PHY_READ(mac, BWN_NPHY_RFCTL_LUT_TRSW_UP1); save_regs_phy[3] = BWN_PHY_READ(mac, BWN_NPHY_RFCTL_LUT_TRSW_UP2); save_regs_phy[4] = BWN_PHY_READ(mac, BWN_NPHY_AFECTL_OVER1); save_regs_phy[5] = BWN_PHY_READ(mac, BWN_NPHY_AFECTL_OVER); save_regs_phy[6] = BWN_PHY_READ(mac, BWN_NPHY_TXF_40CO_B1S0); save_regs_phy[7] = BWN_PHY_READ(mac, BWN_NPHY_TXF_40CO_B32S1); save_regs_phy[8] = 0; } else { save_regs_phy[0] = BWN_PHY_READ(mac, BWN_NPHY_AFECTL_C1); save_regs_phy[1] = BWN_PHY_READ(mac, BWN_NPHY_AFECTL_C2); save_regs_phy[2] = BWN_PHY_READ(mac, BWN_NPHY_AFECTL_OVER); save_regs_phy[3] = BWN_PHY_READ(mac, BWN_NPHY_RFCTL_CMD); save_regs_phy[4] = BWN_PHY_READ(mac, BWN_NPHY_RFCTL_OVER); save_regs_phy[5] = BWN_PHY_READ(mac, BWN_NPHY_RFCTL_RSSIO1); save_regs_phy[6] = BWN_PHY_READ(mac, BWN_NPHY_RFCTL_RSSIO2); save_regs_phy[7] = 0; save_regs_phy[8] = 0; } bwn_nphy_rssi_select(mac, 5, rssi_type); if (mac->mac_phy.rev < 2) { save_regs_phy[8] = BWN_PHY_READ(mac, BWN_NPHY_GPIO_SEL); BWN_PHY_WRITE(mac, BWN_NPHY_GPIO_SEL, 5); } for (i = 0; i < 4; i++) buf[i] = 0; for (i = 0; i < nsamp; i++) { if (mac->mac_phy.rev < 2) { s[0] = BWN_PHY_READ(mac, BWN_NPHY_GPIO_LOOUT); s[1] = BWN_PHY_READ(mac, BWN_NPHY_GPIO_HIOUT); } else { s[0] = BWN_PHY_READ(mac, BWN_NPHY_RSSI1); s[1] = BWN_PHY_READ(mac, BWN_NPHY_RSSI2); } buf[0] += ((int8_t)((s[0] & 0x3F) << 2)) >> 2; buf[1] += ((int8_t)(((s[0] >> 8) & 0x3F) << 2)) >> 2; buf[2] += ((int8_t)((s[1] & 0x3F) << 2)) >> 2; buf[3] += ((int8_t)(((s[1] >> 8) & 0x3F) << 2)) >> 2; } out = (buf[0] & 0xFF) << 24 | (buf[1] & 0xFF) << 16 | (buf[2] & 0xFF) << 8 | (buf[3] & 0xFF); if (mac->mac_phy.rev < 2) BWN_PHY_WRITE(mac, BWN_NPHY_GPIO_SEL, save_regs_phy[8]); if (mac->mac_phy.rev >= 3) { BWN_PHY_WRITE(mac, BWN_NPHY_AFECTL_C1, save_regs_phy[0]); BWN_PHY_WRITE(mac, BWN_NPHY_AFECTL_C2, save_regs_phy[1]); BWN_PHY_WRITE(mac, BWN_NPHY_RFCTL_LUT_TRSW_UP1, save_regs_phy[2]); BWN_PHY_WRITE(mac, BWN_NPHY_RFCTL_LUT_TRSW_UP2, save_regs_phy[3]); BWN_PHY_WRITE(mac, BWN_NPHY_AFECTL_OVER1, save_regs_phy[4]); BWN_PHY_WRITE(mac, BWN_NPHY_AFECTL_OVER, save_regs_phy[5]); BWN_PHY_WRITE(mac, BWN_NPHY_TXF_40CO_B1S0, save_regs_phy[6]); BWN_PHY_WRITE(mac, BWN_NPHY_TXF_40CO_B32S1, save_regs_phy[7]); } else { BWN_PHY_WRITE(mac, BWN_NPHY_AFECTL_C1, save_regs_phy[0]); BWN_PHY_WRITE(mac, BWN_NPHY_AFECTL_C2, save_regs_phy[1]); BWN_PHY_WRITE(mac, BWN_NPHY_AFECTL_OVER, save_regs_phy[2]); BWN_PHY_WRITE(mac, BWN_NPHY_RFCTL_CMD, save_regs_phy[3]); BWN_PHY_WRITE(mac, BWN_NPHY_RFCTL_OVER, save_regs_phy[4]); BWN_PHY_WRITE(mac, BWN_NPHY_RFCTL_RSSIO1, save_regs_phy[5]); BWN_PHY_WRITE(mac, BWN_NPHY_RFCTL_RSSIO2, save_regs_phy[6]); } return out; } /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RSSICalRev3 */ static void bwn_nphy_rev3_rssi_cal(struct bwn_mac *mac) { //struct bwn_phy *phy = &mac->mac_phy; struct bwn_phy_n *nphy = mac->mac_phy.phy_n; uint16_t saved_regs_phy_rfctl[2]; uint16_t saved_regs_phy[22]; uint16_t regs_to_store_rev3[] = { BWN_NPHY_AFECTL_OVER1, BWN_NPHY_AFECTL_OVER, BWN_NPHY_AFECTL_C1, BWN_NPHY_AFECTL_C2, BWN_NPHY_TXF_40CO_B1S1, BWN_NPHY_RFCTL_OVER, BWN_NPHY_TXF_40CO_B1S0, BWN_NPHY_TXF_40CO_B32S1, BWN_NPHY_RFCTL_CMD, BWN_NPHY_RFCTL_LUT_TRSW_UP1, BWN_NPHY_RFCTL_LUT_TRSW_UP2, BWN_NPHY_RFCTL_RSSIO1, BWN_NPHY_RFCTL_RSSIO2 }; uint16_t regs_to_store_rev7[] = { BWN_NPHY_AFECTL_OVER1, BWN_NPHY_AFECTL_OVER, BWN_NPHY_AFECTL_C1, BWN_NPHY_AFECTL_C2, BWN_NPHY_TXF_40CO_B1S1, BWN_NPHY_RFCTL_OVER, BWN_NPHY_REV7_RF_CTL_OVER3, BWN_NPHY_REV7_RF_CTL_OVER4, BWN_NPHY_REV7_RF_CTL_OVER5, BWN_NPHY_REV7_RF_CTL_OVER6, 0x2ff, BWN_NPHY_TXF_40CO_B1S0, BWN_NPHY_TXF_40CO_B32S1, BWN_NPHY_RFCTL_CMD, BWN_NPHY_RFCTL_LUT_TRSW_UP1, BWN_NPHY_RFCTL_LUT_TRSW_UP2, BWN_NPHY_REV7_RF_CTL_MISC_REG3, BWN_NPHY_REV7_RF_CTL_MISC_REG4, BWN_NPHY_REV7_RF_CTL_MISC_REG5, BWN_NPHY_REV7_RF_CTL_MISC_REG6, BWN_NPHY_RFCTL_RSSIO1, BWN_NPHY_RFCTL_RSSIO2 }; uint16_t *regs_to_store; int regs_amount; uint16_t class; uint16_t clip_state[2]; uint16_t clip_off[2] = { 0xFFFF, 0xFFFF }; uint8_t vcm_final = 0; int32_t offset[4]; int32_t results[8][4] = { }; int32_t results_min[4] = { }; int32_t poll_results[4] = { }; uint16_t *rssical_radio_regs = NULL; uint16_t *rssical_phy_regs = NULL; uint16_t r; /* routing */ uint8_t rx_core_state; int core, i, j, vcm; if (mac->mac_phy.rev >= 7) { regs_to_store = regs_to_store_rev7; regs_amount = nitems(regs_to_store_rev7); } else { regs_to_store = regs_to_store_rev3; regs_amount = nitems(regs_to_store_rev3); } KASSERT((regs_amount <= nitems(saved_regs_phy)), ("%s: reg_amount (%d) too large\n", __func__, regs_amount)); class = bwn_nphy_classifier(mac, 0, 0); bwn_nphy_classifier(mac, 7, 4); bwn_nphy_read_clip_detection(mac, clip_state); bwn_nphy_write_clip_detection(mac, clip_off); saved_regs_phy_rfctl[0] = BWN_PHY_READ(mac, BWN_NPHY_RFCTL_INTC1); saved_regs_phy_rfctl[1] = BWN_PHY_READ(mac, BWN_NPHY_RFCTL_INTC2); for (i = 0; i < regs_amount; i++) saved_regs_phy[i] = BWN_PHY_READ(mac, regs_to_store[i]); bwn_nphy_rf_ctl_intc_override(mac, N_INTC_OVERRIDE_OFF, 0, 7); bwn_nphy_rf_ctl_intc_override(mac, N_INTC_OVERRIDE_TRSW, 1, 7); if (mac->mac_phy.rev >= 7) { bwn_nphy_rf_ctl_override_one_to_many(mac, N_RF_CTL_OVER_CMD_RXRF_PU, 0, 0, false); bwn_nphy_rf_ctl_override_one_to_many(mac, N_RF_CTL_OVER_CMD_RX_PU, 1, 0, false); bwn_nphy_rf_ctl_override_rev7(mac, 0x80, 1, 0, false, 0); bwn_nphy_rf_ctl_override_rev7(mac, 0x40, 1, 0, false, 0); if (bwn_current_band(mac) == BWN_BAND_5G) { bwn_nphy_rf_ctl_override_rev7(mac, 0x20, 0, 0, false, 0); bwn_nphy_rf_ctl_override_rev7(mac, 0x10, 1, 0, false, 0); } else { bwn_nphy_rf_ctl_override_rev7(mac, 0x10, 0, 0, false, 0); bwn_nphy_rf_ctl_override_rev7(mac, 0x20, 1, 0, false, 0); } } else { bwn_nphy_rf_ctl_override(mac, 0x1, 0, 0, false); bwn_nphy_rf_ctl_override(mac, 0x2, 1, 0, false); bwn_nphy_rf_ctl_override(mac, 0x80, 1, 0, false); bwn_nphy_rf_ctl_override(mac, 0x40, 1, 0, false); if (bwn_current_band(mac) == BWN_BAND_5G) { bwn_nphy_rf_ctl_override(mac, 0x20, 0, 0, false); bwn_nphy_rf_ctl_override(mac, 0x10, 1, 0, false); } else { bwn_nphy_rf_ctl_override(mac, 0x10, 0, 0, false); bwn_nphy_rf_ctl_override(mac, 0x20, 1, 0, false); } } rx_core_state = bwn_nphy_get_rx_core_state(mac); for (core = 0; core < 2; core++) { if (!(rx_core_state & (1 << core))) continue; r = core ? B2056_RX1 : B2056_RX0; bwn_nphy_scale_offset_rssi(mac, 0, 0, core + 1, N_RAIL_I, N_RSSI_NB); bwn_nphy_scale_offset_rssi(mac, 0, 0, core + 1, N_RAIL_Q, N_RSSI_NB); /* Grab RSSI results for every possible VCM */ for (vcm = 0; vcm < 8; vcm++) { if (mac->mac_phy.rev >= 7) BWN_RF_SETMASK(mac, core ? R2057_NB_MASTER_CORE1 : R2057_NB_MASTER_CORE0, ~R2057_VCM_MASK, vcm); else BWN_RF_SETMASK(mac, r | B2056_RX_RSSI_MISC, 0xE3, vcm << 2); bwn_nphy_poll_rssi(mac, N_RSSI_NB, results[vcm], 8); } /* Find out which VCM got the best results */ for (i = 0; i < 4; i += 2) { int32_t currd; int32_t mind = 0x100000; int32_t minpoll = 249; uint8_t minvcm = 0; if (2 * core != i) continue; for (vcm = 0; vcm < 8; vcm++) { currd = results[vcm][i] * results[vcm][i] + results[vcm][i + 1] * results[vcm][i]; if (currd < mind) { mind = currd; minvcm = vcm; } if (results[vcm][i] < minpoll) minpoll = results[vcm][i]; } vcm_final = minvcm; results_min[i] = minpoll; } /* Select the best VCM */ if (mac->mac_phy.rev >= 7) BWN_RF_SETMASK(mac, core ? R2057_NB_MASTER_CORE1 : R2057_NB_MASTER_CORE0, ~R2057_VCM_MASK, vcm); else BWN_RF_SETMASK(mac, r | B2056_RX_RSSI_MISC, 0xE3, vcm_final << 2); for (i = 0; i < 4; i++) { if (core != i / 2) continue; offset[i] = -results[vcm_final][i]; if (offset[i] < 0) offset[i] = -((abs(offset[i]) + 4) / 8); else offset[i] = (offset[i] + 4) / 8; if (results_min[i] == 248) offset[i] = -32; bwn_nphy_scale_offset_rssi(mac, 0, offset[i], (i / 2 == 0) ? 1 : 2, (i % 2 == 0) ? N_RAIL_I : N_RAIL_Q, N_RSSI_NB); } } for (core = 0; core < 2; core++) { if (!(rx_core_state & (1 << core))) continue; for (i = 0; i < 2; i++) { bwn_nphy_scale_offset_rssi(mac, 0, 0, core + 1, N_RAIL_I, i); bwn_nphy_scale_offset_rssi(mac, 0, 0, core + 1, N_RAIL_Q, i); bwn_nphy_poll_rssi(mac, i, poll_results, 8); for (j = 0; j < 4; j++) { if (j / 2 == core) { offset[j] = 232 - poll_results[j]; if (offset[j] < 0) offset[j] = -(abs(offset[j] + 4) / 8); else offset[j] = (offset[j] + 4) / 8; bwn_nphy_scale_offset_rssi(mac, 0, offset[2 * core], core + 1, j % 2, i); } } } } BWN_PHY_WRITE(mac, BWN_NPHY_RFCTL_INTC1, saved_regs_phy_rfctl[0]); BWN_PHY_WRITE(mac, BWN_NPHY_RFCTL_INTC2, saved_regs_phy_rfctl[1]); bwn_nphy_force_rf_sequence(mac, BWN_RFSEQ_RESET2RX); BWN_PHY_SET(mac, BWN_NPHY_TXF_40CO_B1S1, 0x1); BWN_PHY_SET(mac, BWN_NPHY_RFCTL_CMD, BWN_NPHY_RFCTL_CMD_START); BWN_PHY_MASK(mac, BWN_NPHY_TXF_40CO_B1S1, ~0x1); BWN_PHY_SET(mac, BWN_NPHY_RFCTL_OVER, 0x1); BWN_PHY_SET(mac, BWN_NPHY_RFCTL_CMD, BWN_NPHY_RFCTL_CMD_RXTX); BWN_PHY_MASK(mac, BWN_NPHY_RFCTL_OVER, ~0x1); for (i = 0; i < regs_amount; i++) BWN_PHY_WRITE(mac, regs_to_store[i], saved_regs_phy[i]); /* Store for future configuration */ if (bwn_current_band(mac) == BWN_BAND_2G) { rssical_radio_regs = nphy->rssical_cache.rssical_radio_regs_2G; rssical_phy_regs = nphy->rssical_cache.rssical_phy_regs_2G; } else { rssical_radio_regs = nphy->rssical_cache.rssical_radio_regs_5G; rssical_phy_regs = nphy->rssical_cache.rssical_phy_regs_5G; } if (mac->mac_phy.rev >= 7) { rssical_radio_regs[0] = BWN_RF_READ(mac, R2057_NB_MASTER_CORE0); rssical_radio_regs[1] = BWN_RF_READ(mac, R2057_NB_MASTER_CORE1); } else { rssical_radio_regs[0] = BWN_RF_READ(mac, B2056_RX0 | B2056_RX_RSSI_MISC); rssical_radio_regs[1] = BWN_RF_READ(mac, B2056_RX1 | B2056_RX_RSSI_MISC); } rssical_phy_regs[0] = BWN_PHY_READ(mac, BWN_NPHY_RSSIMC_0I_RSSI_Z); rssical_phy_regs[1] = BWN_PHY_READ(mac, BWN_NPHY_RSSIMC_0Q_RSSI_Z); rssical_phy_regs[2] = BWN_PHY_READ(mac, BWN_NPHY_RSSIMC_1I_RSSI_Z); rssical_phy_regs[3] = BWN_PHY_READ(mac, BWN_NPHY_RSSIMC_1Q_RSSI_Z); rssical_phy_regs[4] = BWN_PHY_READ(mac, BWN_NPHY_RSSIMC_0I_RSSI_X); rssical_phy_regs[5] = BWN_PHY_READ(mac, BWN_NPHY_RSSIMC_0Q_RSSI_X); rssical_phy_regs[6] = BWN_PHY_READ(mac, BWN_NPHY_RSSIMC_1I_RSSI_X); rssical_phy_regs[7] = BWN_PHY_READ(mac, BWN_NPHY_RSSIMC_1Q_RSSI_X); rssical_phy_regs[8] = BWN_PHY_READ(mac, BWN_NPHY_RSSIMC_0I_RSSI_Y); rssical_phy_regs[9] = BWN_PHY_READ(mac, BWN_NPHY_RSSIMC_0Q_RSSI_Y); rssical_phy_regs[10] = BWN_PHY_READ(mac, BWN_NPHY_RSSIMC_1I_RSSI_Y); rssical_phy_regs[11] = BWN_PHY_READ(mac, BWN_NPHY_RSSIMC_1Q_RSSI_Y); /* Remember for which channel we store configuration */ if (bwn_current_band(mac) == BWN_BAND_2G) nphy->rssical_chanspec_2G.center_freq = bwn_get_centre_freq(mac); else nphy->rssical_chanspec_5G.center_freq = bwn_get_centre_freq(mac); /* End of calibration, restore configuration */ bwn_nphy_classifier(mac, 7, class); bwn_nphy_write_clip_detection(mac, clip_state); } /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RSSICal */ static void bwn_nphy_rev2_rssi_cal(struct bwn_mac *mac, enum n_rssi_type type) { int i, j, vcm; uint8_t state[4]; uint8_t code, val; uint16_t class, override; uint8_t regs_save_radio[2]; uint16_t regs_save_phy[2]; int32_t offset[4]; uint8_t core; uint8_t rail; uint16_t clip_state[2]; uint16_t clip_off[2] = { 0xFFFF, 0xFFFF }; int32_t results_min[4] = { }; uint8_t vcm_final[4] = { }; int32_t results[4][4] = { }; int32_t miniq[4][2] = { }; if (type == N_RSSI_NB) { code = 0; val = 6; } else if (type == N_RSSI_W1 || type == N_RSSI_W2) { code = 25; val = 4; } else { BWN_ERRPRINTF(mac->mac_sc, "%s: RSSI type %d invalid\n", __func__, type); return; } class = bwn_nphy_classifier(mac, 0, 0); bwn_nphy_classifier(mac, 7, 4); bwn_nphy_read_clip_detection(mac, clip_state); bwn_nphy_write_clip_detection(mac, clip_off); if (bwn_current_band(mac) == BWN_BAND_5G) override = 0x140; else override = 0x110; regs_save_phy[0] = BWN_PHY_READ(mac, BWN_NPHY_RFCTL_INTC1); regs_save_radio[0] = BWN_RF_READ(mac, B2055_C1_PD_RXTX); BWN_PHY_WRITE(mac, BWN_NPHY_RFCTL_INTC1, override); BWN_RF_WRITE(mac, B2055_C1_PD_RXTX, val); regs_save_phy[1] = BWN_PHY_READ(mac, BWN_NPHY_RFCTL_INTC2); regs_save_radio[1] = BWN_RF_READ(mac, B2055_C2_PD_RXTX); BWN_PHY_WRITE(mac, BWN_NPHY_RFCTL_INTC2, override); BWN_RF_WRITE(mac, B2055_C2_PD_RXTX, val); state[0] = BWN_RF_READ(mac, B2055_C1_PD_RSSIMISC) & 0x07; state[1] = BWN_RF_READ(mac, B2055_C2_PD_RSSIMISC) & 0x07; BWN_RF_MASK(mac, B2055_C1_PD_RSSIMISC, 0xF8); BWN_RF_MASK(mac, B2055_C2_PD_RSSIMISC, 0xF8); state[2] = BWN_RF_READ(mac, B2055_C1_SP_RSSI) & 0x07; state[3] = BWN_RF_READ(mac, B2055_C2_SP_RSSI) & 0x07; bwn_nphy_rssi_select(mac, 5, type); bwn_nphy_scale_offset_rssi(mac, 0, 0, 5, N_RAIL_I, type); bwn_nphy_scale_offset_rssi(mac, 0, 0, 5, N_RAIL_Q, type); for (vcm = 0; vcm < 4; vcm++) { uint8_t tmp[4]; for (j = 0; j < 4; j++) tmp[j] = vcm; if (type != N_RSSI_W2) bwn_nphy_set_rssi_2055_vcm(mac, type, tmp); bwn_nphy_poll_rssi(mac, type, results[vcm], 8); if (type == N_RSSI_W1 || type == N_RSSI_W2) for (j = 0; j < 2; j++) miniq[vcm][j] = min(results[vcm][2 * j], results[vcm][2 * j + 1]); } for (i = 0; i < 4; i++) { int32_t mind = 0x100000; uint8_t minvcm = 0; int32_t minpoll = 249; int32_t currd; for (vcm = 0; vcm < 4; vcm++) { if (type == N_RSSI_NB) currd = abs(results[vcm][i] - code * 8); else currd = abs(miniq[vcm][i / 2] - code * 8); if (currd < mind) { mind = currd; minvcm = vcm; } if (results[vcm][i] < minpoll) minpoll = results[vcm][i]; } results_min[i] = minpoll; vcm_final[i] = minvcm; } if (type != N_RSSI_W2) bwn_nphy_set_rssi_2055_vcm(mac, type, vcm_final); for (i = 0; i < 4; i++) { offset[i] = (code * 8) - results[vcm_final[i]][i]; if (offset[i] < 0) offset[i] = -((abs(offset[i]) + 4) / 8); else offset[i] = (offset[i] + 4) / 8; if (results_min[i] == 248) offset[i] = code - 32; core = (i / 2) ? 2 : 1; rail = (i % 2) ? N_RAIL_Q : N_RAIL_I; bwn_nphy_scale_offset_rssi(mac, 0, offset[i], core, rail, type); } BWN_RF_SETMASK(mac, B2055_C1_PD_RSSIMISC, 0xF8, state[0]); BWN_RF_SETMASK(mac, B2055_C2_PD_RSSIMISC, 0xF8, state[1]); switch (state[2]) { case 1: bwn_nphy_rssi_select(mac, 1, N_RSSI_NB); break; case 4: bwn_nphy_rssi_select(mac, 1, N_RSSI_W1); break; case 2: bwn_nphy_rssi_select(mac, 1, N_RSSI_W2); break; default: bwn_nphy_rssi_select(mac, 1, N_RSSI_W2); break; } switch (state[3]) { case 1: bwn_nphy_rssi_select(mac, 2, N_RSSI_NB); break; case 4: bwn_nphy_rssi_select(mac, 2, N_RSSI_W1); break; default: bwn_nphy_rssi_select(mac, 2, N_RSSI_W2); break; } bwn_nphy_rssi_select(mac, 0, type); BWN_PHY_WRITE(mac, BWN_NPHY_RFCTL_INTC1, regs_save_phy[0]); BWN_RF_WRITE(mac, B2055_C1_PD_RXTX, regs_save_radio[0]); BWN_PHY_WRITE(mac, BWN_NPHY_RFCTL_INTC2, regs_save_phy[1]); BWN_RF_WRITE(mac, B2055_C2_PD_RXTX, regs_save_radio[1]); bwn_nphy_classifier(mac, 7, class); bwn_nphy_write_clip_detection(mac, clip_state); /* Specs don't say about reset here, but it makes wl and b43 dumps identical, it really seems wl performs this */ bwn_nphy_reset_cca(mac); } /* * RSSI Calibration * http://bcm-v4.sipsolutions.net/802.11/PHY/N/RSSICal */ static void bwn_nphy_rssi_cal(struct bwn_mac *mac) { if (mac->mac_phy.rev >= 19) { /* TODO */ } else if (mac->mac_phy.rev >= 3) { bwn_nphy_rev3_rssi_cal(mac); } else { bwn_nphy_rev2_rssi_cal(mac, N_RSSI_NB); bwn_nphy_rev2_rssi_cal(mac, N_RSSI_W1); bwn_nphy_rev2_rssi_cal(mac, N_RSSI_W2); } } /************************************************** * Workarounds **************************************************/ static void bwn_nphy_gain_ctl_workarounds_rev19(struct bwn_mac *mac) { /* TODO */ } static void bwn_nphy_gain_ctl_workarounds_rev7(struct bwn_mac *mac) { struct bwn_phy *phy = &mac->mac_phy; switch (phy->rev) { /* TODO */ } } static void bwn_nphy_gain_ctl_workarounds_rev3(struct bwn_mac *mac) { struct bwn_softc *sc = mac->mac_sc; bool ghz5; bool ext_lna; uint16_t rssi_gain; struct bwn_nphy_gain_ctl_workaround_entry *e; uint8_t lpf_gain[6] = { 0x00, 0x06, 0x0C, 0x12, 0x12, 0x12 }; uint8_t lpf_bits[6] = { 0, 1, 2, 3, 3, 3 }; /* Prepare values */ ghz5 = BWN_PHY_READ(mac, BWN_NPHY_BANDCTL) & BWN_NPHY_BANDCTL_5GHZ; - ext_lna = ghz5 ? siba_sprom_get_bf_hi(sc->sc_dev) & BWN_BFH_EXTLNA_5GHZ : - siba_sprom_get_bf_lo(sc->sc_dev) & BWN_BFL_EXTLNA; + ext_lna = ghz5 ? sc->sc_board_info.board_flags & BHND_BFL_EXTLNA_5GHZ : + sc->sc_board_info.board_flags & BHND_BFL_EXTLNA; e = bwn_nphy_get_gain_ctl_workaround_ent(mac, ghz5, ext_lna); if (ghz5 && mac->mac_phy.rev >= 5) rssi_gain = 0x90; else rssi_gain = 0x50; BWN_PHY_SET(mac, BWN_NPHY_RXCTL, 0x0040); /* Set Clip 2 detect */ BWN_PHY_SET(mac, BWN_NPHY_C1_CGAINI, BWN_NPHY_C1_CGAINI_CL2DETECT); BWN_PHY_SET(mac, BWN_NPHY_C2_CGAINI, BWN_NPHY_C2_CGAINI_CL2DETECT); BWN_RF_WRITE(mac, B2056_RX0 | B2056_RX_BIASPOLE_LNAG1_IDAC, 0x17); BWN_RF_WRITE(mac, B2056_RX1 | B2056_RX_BIASPOLE_LNAG1_IDAC, 0x17); BWN_RF_WRITE(mac, B2056_RX0 | B2056_RX_LNAG2_IDAC, 0xF0); BWN_RF_WRITE(mac, B2056_RX1 | B2056_RX_LNAG2_IDAC, 0xF0); BWN_RF_WRITE(mac, B2056_RX0 | B2056_RX_RSSI_POLE, 0x00); BWN_RF_WRITE(mac, B2056_RX1 | B2056_RX_RSSI_POLE, 0x00); BWN_RF_WRITE(mac, B2056_RX0 | B2056_RX_RSSI_GAIN, rssi_gain); BWN_RF_WRITE(mac, B2056_RX1 | B2056_RX_RSSI_GAIN, rssi_gain); BWN_RF_WRITE(mac, B2056_RX0 | B2056_RX_BIASPOLE_LNAA1_IDAC, 0x17); BWN_RF_WRITE(mac, B2056_RX1 | B2056_RX_BIASPOLE_LNAA1_IDAC, 0x17); BWN_RF_WRITE(mac, B2056_RX0 | B2056_RX_LNAA2_IDAC, 0xFF); BWN_RF_WRITE(mac, B2056_RX1 | B2056_RX_LNAA2_IDAC, 0xFF); bwn_ntab_write_bulk(mac, BWN_NTAB8(0, 8), 4, e->lna1_gain); bwn_ntab_write_bulk(mac, BWN_NTAB8(1, 8), 4, e->lna1_gain); bwn_ntab_write_bulk(mac, BWN_NTAB8(0, 16), 4, e->lna2_gain); bwn_ntab_write_bulk(mac, BWN_NTAB8(1, 16), 4, e->lna2_gain); bwn_ntab_write_bulk(mac, BWN_NTAB8(0, 32), 10, e->gain_db); bwn_ntab_write_bulk(mac, BWN_NTAB8(1, 32), 10, e->gain_db); bwn_ntab_write_bulk(mac, BWN_NTAB8(2, 32), 10, e->gain_bits); bwn_ntab_write_bulk(mac, BWN_NTAB8(3, 32), 10, e->gain_bits); bwn_ntab_write_bulk(mac, BWN_NTAB8(0, 0x40), 6, lpf_gain); bwn_ntab_write_bulk(mac, BWN_NTAB8(1, 0x40), 6, lpf_gain); bwn_ntab_write_bulk(mac, BWN_NTAB8(2, 0x40), 6, lpf_bits); bwn_ntab_write_bulk(mac, BWN_NTAB8(3, 0x40), 6, lpf_bits); BWN_PHY_WRITE(mac, BWN_NPHY_REV3_C1_INITGAIN_A, e->init_gain); BWN_PHY_WRITE(mac, BWN_NPHY_REV3_C2_INITGAIN_A, e->init_gain); bwn_ntab_write_bulk(mac, BWN_NTAB16(7, 0x106), 2, e->rfseq_init); BWN_PHY_WRITE(mac, BWN_NPHY_REV3_C1_CLIP_HIGAIN_A, e->cliphi_gain); BWN_PHY_WRITE(mac, BWN_NPHY_REV3_C2_CLIP_HIGAIN_A, e->cliphi_gain); BWN_PHY_WRITE(mac, BWN_NPHY_REV3_C1_CLIP_MEDGAIN_A, e->clipmd_gain); BWN_PHY_WRITE(mac, BWN_NPHY_REV3_C2_CLIP_MEDGAIN_A, e->clipmd_gain); BWN_PHY_WRITE(mac, BWN_NPHY_REV3_C1_CLIP_LOGAIN_A, e->cliplo_gain); BWN_PHY_WRITE(mac, BWN_NPHY_REV3_C2_CLIP_LOGAIN_A, e->cliplo_gain); BWN_PHY_SETMASK(mac, BWN_NPHY_CRSMINPOWER0, 0xFF00, e->crsmin); BWN_PHY_SETMASK(mac, BWN_NPHY_CRSMINPOWERL0, 0xFF00, e->crsminl); BWN_PHY_SETMASK(mac, BWN_NPHY_CRSMINPOWERU0, 0xFF00, e->crsminu); BWN_PHY_WRITE(mac, BWN_NPHY_C1_NBCLIPTHRES, e->nbclip); BWN_PHY_WRITE(mac, BWN_NPHY_C2_NBCLIPTHRES, e->nbclip); BWN_PHY_SETMASK(mac, BWN_NPHY_C1_CLIPWBTHRES, ~BWN_NPHY_C1_CLIPWBTHRES_CLIP2, e->wlclip); BWN_PHY_SETMASK(mac, BWN_NPHY_C2_CLIPWBTHRES, ~BWN_NPHY_C2_CLIPWBTHRES_CLIP2, e->wlclip); BWN_PHY_WRITE(mac, BWN_NPHY_CCK_SHIFTB_REF, 0x809C); } static void bwn_nphy_gain_ctl_workarounds_rev1_2(struct bwn_mac *mac) { struct bwn_phy_n *nphy = mac->mac_phy.phy_n; uint8_t i, j; uint8_t code; uint16_t tmp; uint8_t rfseq_events[3] = { 6, 8, 7 }; uint8_t rfseq_delays[3] = { 10, 30, 1 }; /* Set Clip 2 detect */ BWN_PHY_SET(mac, BWN_NPHY_C1_CGAINI, BWN_NPHY_C1_CGAINI_CL2DETECT); BWN_PHY_SET(mac, BWN_NPHY_C2_CGAINI, BWN_NPHY_C2_CGAINI_CL2DETECT); /* Set narrowband clip threshold */ BWN_PHY_WRITE(mac, BWN_NPHY_C1_NBCLIPTHRES, 0x84); BWN_PHY_WRITE(mac, BWN_NPHY_C2_NBCLIPTHRES, 0x84); if (!bwn_is_40mhz(mac)) { /* Set dwell lengths */ BWN_PHY_WRITE(mac, BWN_NPHY_CLIP1_NBDWELL_LEN, 0x002B); BWN_PHY_WRITE(mac, BWN_NPHY_CLIP2_NBDWELL_LEN, 0x002B); BWN_PHY_WRITE(mac, BWN_NPHY_W1CLIP1_DWELL_LEN, 0x0009); BWN_PHY_WRITE(mac, BWN_NPHY_W1CLIP2_DWELL_LEN, 0x0009); } /* Set wideband clip 2 threshold */ BWN_PHY_SETMASK(mac, BWN_NPHY_C1_CLIPWBTHRES, ~BWN_NPHY_C1_CLIPWBTHRES_CLIP2, 21); BWN_PHY_SETMASK(mac, BWN_NPHY_C2_CLIPWBTHRES, ~BWN_NPHY_C2_CLIPWBTHRES_CLIP2, 21); if (!bwn_is_40mhz(mac)) { BWN_PHY_SETMASK(mac, BWN_NPHY_C1_CGAINI, ~BWN_NPHY_C1_CGAINI_GAINBKOFF, 0x1); BWN_PHY_SETMASK(mac, BWN_NPHY_C2_CGAINI, ~BWN_NPHY_C2_CGAINI_GAINBKOFF, 0x1); BWN_PHY_SETMASK(mac, BWN_NPHY_C1_CCK_CGAINI, ~BWN_NPHY_C1_CCK_CGAINI_GAINBKOFF, 0x1); BWN_PHY_SETMASK(mac, BWN_NPHY_C2_CCK_CGAINI, ~BWN_NPHY_C2_CCK_CGAINI_GAINBKOFF, 0x1); } BWN_PHY_WRITE(mac, BWN_NPHY_CCK_SHIFTB_REF, 0x809C); if (nphy->gain_boost) { if (bwn_current_band(mac) == BWN_BAND_2G && bwn_is_40mhz(mac)) code = 4; else code = 5; } else { code = bwn_is_40mhz(mac) ? 6 : 7; } /* Set HPVGA2 index */ BWN_PHY_SETMASK(mac, BWN_NPHY_C1_INITGAIN, ~BWN_NPHY_C1_INITGAIN_HPVGA2, code << BWN_NPHY_C1_INITGAIN_HPVGA2_SHIFT); BWN_PHY_SETMASK(mac, BWN_NPHY_C2_INITGAIN, ~BWN_NPHY_C2_INITGAIN_HPVGA2, code << BWN_NPHY_C2_INITGAIN_HPVGA2_SHIFT); BWN_PHY_WRITE(mac, BWN_NPHY_TABLE_ADDR, 0x1D06); /* specs say about 2 loops, but wl does 4 */ for (i = 0; i < 4; i++) BWN_PHY_WRITE(mac, BWN_NPHY_TABLE_DATALO, (code << 8 | 0x7C)); bwn_nphy_adjust_lna_gain_table(mac); if (nphy->elna_gain_config) { BWN_PHY_WRITE(mac, BWN_NPHY_TABLE_ADDR, 0x0808); BWN_PHY_WRITE(mac, BWN_NPHY_TABLE_DATALO, 0x0); BWN_PHY_WRITE(mac, BWN_NPHY_TABLE_DATALO, 0x1); BWN_PHY_WRITE(mac, BWN_NPHY_TABLE_DATALO, 0x1); BWN_PHY_WRITE(mac, BWN_NPHY_TABLE_DATALO, 0x1); BWN_PHY_WRITE(mac, BWN_NPHY_TABLE_ADDR, 0x0C08); BWN_PHY_WRITE(mac, BWN_NPHY_TABLE_DATALO, 0x0); BWN_PHY_WRITE(mac, BWN_NPHY_TABLE_DATALO, 0x1); BWN_PHY_WRITE(mac, BWN_NPHY_TABLE_DATALO, 0x1); BWN_PHY_WRITE(mac, BWN_NPHY_TABLE_DATALO, 0x1); BWN_PHY_WRITE(mac, BWN_NPHY_TABLE_ADDR, 0x1D06); /* specs say about 2 loops, but wl does 4 */ for (i = 0; i < 4; i++) BWN_PHY_WRITE(mac, BWN_NPHY_TABLE_DATALO, (code << 8 | 0x74)); } if (mac->mac_phy.rev == 2) { for (i = 0; i < 4; i++) { BWN_PHY_WRITE(mac, BWN_NPHY_TABLE_ADDR, (0x0400 * i) + 0x0020); for (j = 0; j < 21; j++) { tmp = j * (i < 2 ? 3 : 1); BWN_PHY_WRITE(mac, BWN_NPHY_TABLE_DATALO, tmp); } } } bwn_nphy_set_rf_sequence(mac, 5, rfseq_events, rfseq_delays, 3); BWN_PHY_SETMASK(mac, BWN_NPHY_OVER_DGAIN1, ~BWN_NPHY_OVER_DGAIN_CCKDGECV & 0xFFFF, 0x5A << BWN_NPHY_OVER_DGAIN_CCKDGECV_SHIFT); if (bwn_current_band(mac) == BWN_BAND_2G) BWN_PHY_SETMASK(mac, BWN_PHY_N(0xC5D), 0xFF80, 4); } /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/WorkaroundsGainCtrl */ static void bwn_nphy_gain_ctl_workarounds(struct bwn_mac *mac) { if (mac->mac_phy.rev >= 19) bwn_nphy_gain_ctl_workarounds_rev19(mac); else if (mac->mac_phy.rev >= 7) bwn_nphy_gain_ctl_workarounds_rev7(mac); else if (mac->mac_phy.rev >= 3) bwn_nphy_gain_ctl_workarounds_rev3(mac); else bwn_nphy_gain_ctl_workarounds_rev1_2(mac); } -static void bwn_nphy_workarounds_rev7plus(struct bwn_mac *mac) +static int bwn_nphy_workarounds_rev7plus(struct bwn_mac *mac) { struct bwn_softc *sc = mac->mac_sc; struct bwn_phy *phy = &mac->mac_phy; /* TX to RX */ uint8_t tx2rx_events[7] = { 4, 3, 5, 2, 1, 8, 31, }; uint8_t tx2rx_delays[7] = { 8, 4, 4, 4, 4, 6, 1, }; /* RX to TX */ uint8_t rx2tx_events_ipa[9] = { 0x0, 0x1, 0x2, 0x8, 0x5, 0x6, 0xF, 0x3, 0x1F }; uint8_t rx2tx_delays_ipa[9] = { 8, 6, 6, 4, 4, 16, 43, 1, 1 }; static const uint16_t ntab7_15e_16e[] = { 0, 0x10f, 0x10f }; uint8_t ntab7_138_146[] = { 0x11, 0x11 }; uint8_t ntab7_133[] = { 0x77, 0x11, 0x11 }; uint16_t lpf_ofdm_20mhz[2], lpf_ofdm_40mhz[2], lpf_11b[2]; uint16_t bcap_val; int16_t bcap_val_11b[2], bcap_val_11n_20[2], bcap_val_11n_40[2]; uint16_t scap_val; int16_t scap_val_11b[2], scap_val_11n_20[2], scap_val_11n_40[2]; bool rccal_ovrd = false; uint16_t bias, conv, filt; uint32_t noise_tbl[2]; uint32_t tmp32; uint8_t core; BWN_PHY_WRITE(mac, BWN_NPHY_PHASETR_A0, 0x0125); BWN_PHY_WRITE(mac, BWN_NPHY_PHASETR_A1, 0x01b3); BWN_PHY_WRITE(mac, BWN_NPHY_PHASETR_A2, 0x0105); BWN_PHY_WRITE(mac, BWN_NPHY_PHASETR_B0, 0x016e); BWN_PHY_WRITE(mac, BWN_NPHY_PHASETR_B1, 0x00cd); BWN_PHY_WRITE(mac, BWN_NPHY_PHASETR_B2, 0x0020); if (phy->rev == 7) { BWN_PHY_SET(mac, BWN_NPHY_FINERX2_CGC, 0x10); BWN_PHY_SETMASK(mac, BWN_NPHY_FREQGAIN0, 0xFF80, 0x0020); BWN_PHY_SETMASK(mac, BWN_NPHY_FREQGAIN0, 0x80FF, 0x2700); BWN_PHY_SETMASK(mac, BWN_NPHY_FREQGAIN1, 0xFF80, 0x002E); BWN_PHY_SETMASK(mac, BWN_NPHY_FREQGAIN1, 0x80FF, 0x3300); BWN_PHY_SETMASK(mac, BWN_NPHY_FREQGAIN2, 0xFF80, 0x0037); BWN_PHY_SETMASK(mac, BWN_NPHY_FREQGAIN2, 0x80FF, 0x3A00); BWN_PHY_SETMASK(mac, BWN_NPHY_FREQGAIN3, 0xFF80, 0x003C); BWN_PHY_SETMASK(mac, BWN_NPHY_FREQGAIN3, 0x80FF, 0x3E00); BWN_PHY_SETMASK(mac, BWN_NPHY_FREQGAIN4, 0xFF80, 0x003E); BWN_PHY_SETMASK(mac, BWN_NPHY_FREQGAIN4, 0x80FF, 0x3F00); BWN_PHY_SETMASK(mac, BWN_NPHY_FREQGAIN5, 0xFF80, 0x0040); BWN_PHY_SETMASK(mac, BWN_NPHY_FREQGAIN5, 0x80FF, 0x4000); BWN_PHY_SETMASK(mac, BWN_NPHY_FREQGAIN6, 0xFF80, 0x0040); BWN_PHY_SETMASK(mac, BWN_NPHY_FREQGAIN6, 0x80FF, 0x4000); BWN_PHY_SETMASK(mac, BWN_NPHY_FREQGAIN7, 0xFF80, 0x0040); BWN_PHY_SETMASK(mac, BWN_NPHY_FREQGAIN7, 0x80FF, 0x4000); } if (phy->rev >= 16) { BWN_PHY_WRITE(mac, BWN_NPHY_FORCEFRONT0, 0x7ff); BWN_PHY_WRITE(mac, BWN_NPHY_FORCEFRONT1, 0x7ff); } else if (phy->rev <= 8) { BWN_PHY_WRITE(mac, BWN_NPHY_FORCEFRONT0, 0x1B0); BWN_PHY_WRITE(mac, BWN_NPHY_FORCEFRONT1, 0x1B0); } if (phy->rev >= 16) BWN_PHY_SETMASK(mac, BWN_NPHY_TXTAILCNT, ~0xFF, 0xa0); else if (phy->rev >= 8) BWN_PHY_SETMASK(mac, BWN_NPHY_TXTAILCNT, ~0xFF, 0x72); bwn_ntab_write(mac, BWN_NTAB16(8, 0x00), 2); bwn_ntab_write(mac, BWN_NTAB16(8, 0x10), 2); tmp32 = bwn_ntab_read(mac, BWN_NTAB32(30, 0)); tmp32 &= 0xffffff; bwn_ntab_write(mac, BWN_NTAB32(30, 0), tmp32); bwn_ntab_write_bulk(mac, BWN_NTAB16(7, 0x15d), 3, ntab7_15e_16e); bwn_ntab_write_bulk(mac, BWN_NTAB16(7, 0x16d), 3, ntab7_15e_16e); bwn_nphy_set_rf_sequence(mac, 1, tx2rx_events, tx2rx_delays, nitems(tx2rx_events)); if (bwn_nphy_ipa(mac)) bwn_nphy_set_rf_sequence(mac, 0, rx2tx_events_ipa, rx2tx_delays_ipa, nitems(rx2tx_events_ipa)); BWN_PHY_SETMASK(mac, BWN_NPHY_EPS_OVERRIDEI_0, 0x3FFF, 0x4000); BWN_PHY_SETMASK(mac, BWN_NPHY_EPS_OVERRIDEI_1, 0x3FFF, 0x4000); for (core = 0; core < 2; core++) { lpf_ofdm_20mhz[core] = bwn_nphy_read_lpf_ctl(mac, 0x154 + core * 0x10); lpf_ofdm_40mhz[core] = bwn_nphy_read_lpf_ctl(mac, 0x159 + core * 0x10); lpf_11b[core] = bwn_nphy_read_lpf_ctl(mac, 0x152 + core * 0x10); } bcap_val = BWN_RF_READ(mac, R2057_RCCAL_BCAP_VAL); scap_val = BWN_RF_READ(mac, R2057_RCCAL_SCAP_VAL); if (bwn_nphy_ipa(mac)) { bool ghz2 = bwn_current_band(mac) == BWN_BAND_2G; switch (phy->rf_rev) { case 5: /* Check radio version (to be 0) by PHY rev for now */ if (phy->rev == 8 && bwn_is_40mhz(mac)) { for (core = 0; core < 2; core++) { scap_val_11b[core] = scap_val; bcap_val_11b[core] = bcap_val; scap_val_11n_20[core] = scap_val; bcap_val_11n_20[core] = bcap_val; scap_val_11n_40[core] = 0xc; bcap_val_11n_40[core] = 0xc; } rccal_ovrd = true; } if (phy->rev == 9) { /* TODO: Radio version 1 (e.g. BCM5357B0) */ } break; case 7: case 8: for (core = 0; core < 2; core++) { scap_val_11b[core] = scap_val; bcap_val_11b[core] = bcap_val; lpf_ofdm_20mhz[core] = 4; lpf_11b[core] = 1; if (bwn_current_band(mac) == BWN_BAND_2G) { scap_val_11n_20[core] = 0xc; bcap_val_11n_20[core] = 0xc; scap_val_11n_40[core] = 0xa; bcap_val_11n_40[core] = 0xa; } else { scap_val_11n_20[core] = 0x14; bcap_val_11n_20[core] = 0x14; scap_val_11n_40[core] = 0xf; bcap_val_11n_40[core] = 0xf; } } rccal_ovrd = true; break; case 9: for (core = 0; core < 2; core++) { bcap_val_11b[core] = bcap_val; scap_val_11b[core] = scap_val; lpf_11b[core] = 1; if (ghz2) { bcap_val_11n_20[core] = bcap_val + 13; scap_val_11n_20[core] = scap_val + 15; } else { bcap_val_11n_20[core] = bcap_val + 14; scap_val_11n_20[core] = scap_val + 15; } lpf_ofdm_20mhz[core] = 4; if (ghz2) { bcap_val_11n_40[core] = bcap_val - 7; scap_val_11n_40[core] = scap_val - 5; } else { bcap_val_11n_40[core] = bcap_val + 2; scap_val_11n_40[core] = scap_val + 4; } lpf_ofdm_40mhz[core] = 4; } rccal_ovrd = true; break; case 14: for (core = 0; core < 2; core++) { bcap_val_11b[core] = bcap_val; scap_val_11b[core] = scap_val; lpf_11b[core] = 1; } bcap_val_11n_20[0] = bcap_val + 20; scap_val_11n_20[0] = scap_val + 20; lpf_ofdm_20mhz[0] = 3; bcap_val_11n_20[1] = bcap_val + 16; scap_val_11n_20[1] = scap_val + 16; lpf_ofdm_20mhz[1] = 3; bcap_val_11n_40[0] = bcap_val + 20; scap_val_11n_40[0] = scap_val + 20; lpf_ofdm_40mhz[0] = 4; bcap_val_11n_40[1] = bcap_val + 10; scap_val_11n_40[1] = scap_val + 10; lpf_ofdm_40mhz[1] = 4; rccal_ovrd = true; break; } } else { if (phy->rf_rev == 5) { for (core = 0; core < 2; core++) { lpf_ofdm_20mhz[core] = 1; lpf_ofdm_40mhz[core] = 3; scap_val_11b[core] = scap_val; bcap_val_11b[core] = bcap_val; scap_val_11n_20[core] = 0x11; scap_val_11n_40[core] = 0x11; bcap_val_11n_20[core] = 0x13; bcap_val_11n_40[core] = 0x13; } rccal_ovrd = true; } } if (rccal_ovrd) { uint16_t rx2tx_lut_20_11b[2], rx2tx_lut_20_11n[2], rx2tx_lut_40_11n[2]; uint8_t rx2tx_lut_extra = 1; for (core = 0; core < 2; core++) { bcap_val_11b[core] = bwn_clamp_val(bcap_val_11b[core], 0, 0x1f); scap_val_11b[core] = bwn_clamp_val(scap_val_11b[core], 0, 0x1f); bcap_val_11n_20[core] = bwn_clamp_val(bcap_val_11n_20[core], 0, 0x1f); scap_val_11n_20[core] = bwn_clamp_val(scap_val_11n_20[core], 0, 0x1f); bcap_val_11n_40[core] = bwn_clamp_val(bcap_val_11n_40[core], 0, 0x1f); scap_val_11n_40[core] = bwn_clamp_val(scap_val_11n_40[core], 0, 0x1f); rx2tx_lut_20_11b[core] = (rx2tx_lut_extra << 13) | (bcap_val_11b[core] << 8) | (scap_val_11b[core] << 3) | lpf_11b[core]; rx2tx_lut_20_11n[core] = (rx2tx_lut_extra << 13) | (bcap_val_11n_20[core] << 8) | (scap_val_11n_20[core] << 3) | lpf_ofdm_20mhz[core]; rx2tx_lut_40_11n[core] = (rx2tx_lut_extra << 13) | (bcap_val_11n_40[core] << 8) | (scap_val_11n_40[core] << 3) | lpf_ofdm_40mhz[core]; } for (core = 0; core < 2; core++) { bwn_ntab_write(mac, BWN_NTAB16(7, 0x152 + core * 16), rx2tx_lut_20_11b[core]); bwn_ntab_write(mac, BWN_NTAB16(7, 0x153 + core * 16), rx2tx_lut_20_11n[core]); bwn_ntab_write(mac, BWN_NTAB16(7, 0x154 + core * 16), rx2tx_lut_20_11n[core]); bwn_ntab_write(mac, BWN_NTAB16(7, 0x155 + core * 16), rx2tx_lut_40_11n[core]); bwn_ntab_write(mac, BWN_NTAB16(7, 0x156 + core * 16), rx2tx_lut_40_11n[core]); bwn_ntab_write(mac, BWN_NTAB16(7, 0x157 + core * 16), rx2tx_lut_40_11n[core]); bwn_ntab_write(mac, BWN_NTAB16(7, 0x158 + core * 16), rx2tx_lut_40_11n[core]); bwn_ntab_write(mac, BWN_NTAB16(7, 0x159 + core * 16), rx2tx_lut_40_11n[core]); } } BWN_PHY_WRITE(mac, 0x32F, 0x3); if (phy->rf_rev == 4 || phy->rf_rev == 6) bwn_nphy_rf_ctl_override_rev7(mac, 4, 1, 3, false, 0); if (phy->rf_rev == 3 || phy->rf_rev == 4 || phy->rf_rev == 6) { - if (siba_sprom_get_rev(sc->sc_dev) && - siba_sprom_get_bf2_hi(sc->sc_dev) & BWN_BFH2_IPALVLSHIFT_3P3) { + if (sc->sc_board_info.board_srom_rev && + sc->sc_board_info.board_flags2 & BHND_BFL2_IPALVLSHIFT_3P3) { BWN_RF_WRITE(mac, 0x5, 0x05); BWN_RF_WRITE(mac, 0x6, 0x30); BWN_RF_WRITE(mac, 0x7, 0x00); BWN_RF_SET(mac, 0x4f, 0x1); BWN_RF_SET(mac, 0xd4, 0x1); bias = 0x1f; conv = 0x6f; filt = 0xaa; } else { bias = 0x2b; conv = 0x7f; filt = 0xee; } if (bwn_current_band(mac) == BWN_BAND_2G) { for (core = 0; core < 2; core++) { if (core == 0) { BWN_RF_WRITE(mac, 0x5F, bias); BWN_RF_WRITE(mac, 0x64, conv); BWN_RF_WRITE(mac, 0x66, filt); } else { BWN_RF_WRITE(mac, 0xE8, bias); BWN_RF_WRITE(mac, 0xE9, conv); BWN_RF_WRITE(mac, 0xEB, filt); } } } } if (bwn_nphy_ipa(mac)) { if (bwn_current_band(mac) == BWN_BAND_2G) { if (phy->rf_rev == 3 || phy->rf_rev == 4 || phy->rf_rev == 6) { for (core = 0; core < 2; core++) { if (core == 0) BWN_RF_WRITE(mac, 0x51, 0x7f); else BWN_RF_WRITE(mac, 0xd6, 0x7f); } } switch (phy->rf_rev) { case 3: for (core = 0; core < 2; core++) { if (core == 0) { BWN_RF_WRITE(mac, 0x64, 0x13); BWN_RF_WRITE(mac, 0x5F, 0x1F); BWN_RF_WRITE(mac, 0x66, 0xEE); BWN_RF_WRITE(mac, 0x59, 0x8A); BWN_RF_WRITE(mac, 0x80, 0x3E); } else { BWN_RF_WRITE(mac, 0x69, 0x13); BWN_RF_WRITE(mac, 0xE8, 0x1F); BWN_RF_WRITE(mac, 0xEB, 0xEE); BWN_RF_WRITE(mac, 0xDE, 0x8A); BWN_RF_WRITE(mac, 0x105, 0x3E); } } break; case 7: case 8: if (!bwn_is_40mhz(mac)) { BWN_RF_WRITE(mac, 0x5F, 0x14); BWN_RF_WRITE(mac, 0xE8, 0x12); } else { BWN_RF_WRITE(mac, 0x5F, 0x16); BWN_RF_WRITE(mac, 0xE8, 0x16); } break; case 14: for (core = 0; core < 2; core++) { int o = core ? 0x85 : 0; BWN_RF_WRITE(mac, o + R2057_IPA2G_CASCONV_CORE0, 0x13); BWN_RF_WRITE(mac, o + R2057_TXMIX2G_TUNE_BOOST_PU_CORE0, 0x21); BWN_RF_WRITE(mac, o + R2057_IPA2G_BIAS_FILTER_CORE0, 0xff); BWN_RF_WRITE(mac, o + R2057_PAD2G_IDACS_CORE0, 0x88); BWN_RF_WRITE(mac, o + R2057_PAD2G_TUNE_PUS_CORE0, 0x23); BWN_RF_WRITE(mac, o + R2057_IPA2G_IMAIN_CORE0, 0x16); BWN_RF_WRITE(mac, o + R2057_PAD_BIAS_FILTER_BWS_CORE0, 0x3e); BWN_RF_WRITE(mac, o + R2057_BACKUP1_CORE0, 0x10); } break; } } else { uint16_t freq = bwn_get_centre_freq(mac); if ((freq >= 5180 && freq <= 5230) || (freq >= 5745 && freq <= 5805)) { BWN_RF_WRITE(mac, 0x7D, 0xFF); BWN_RF_WRITE(mac, 0xFE, 0xFF); } } } else { if (phy->rf_rev != 5) { for (core = 0; core < 2; core++) { if (core == 0) { BWN_RF_WRITE(mac, 0x5c, 0x61); BWN_RF_WRITE(mac, 0x51, 0x70); } else { BWN_RF_WRITE(mac, 0xe1, 0x61); BWN_RF_WRITE(mac, 0xd6, 0x70); } } } } if (phy->rf_rev == 4) { bwn_ntab_write(mac, BWN_NTAB16(8, 0x05), 0x20); bwn_ntab_write(mac, BWN_NTAB16(8, 0x15), 0x20); for (core = 0; core < 2; core++) { if (core == 0) { BWN_RF_WRITE(mac, 0x1a1, 0x00); BWN_RF_WRITE(mac, 0x1a2, 0x3f); BWN_RF_WRITE(mac, 0x1a6, 0x3f); } else { BWN_RF_WRITE(mac, 0x1a7, 0x00); BWN_RF_WRITE(mac, 0x1ab, 0x3f); BWN_RF_WRITE(mac, 0x1ac, 0x3f); } } } else { BWN_PHY_SET(mac, BWN_NPHY_AFECTL_C1, 0x4); BWN_PHY_SET(mac, BWN_NPHY_AFECTL_OVER1, 0x4); BWN_PHY_SET(mac, BWN_NPHY_AFECTL_C2, 0x4); BWN_PHY_SET(mac, BWN_NPHY_AFECTL_OVER, 0x4); BWN_PHY_MASK(mac, BWN_NPHY_AFECTL_C1, ~0x1); BWN_PHY_SET(mac, BWN_NPHY_AFECTL_OVER1, 0x1); BWN_PHY_MASK(mac, BWN_NPHY_AFECTL_C2, ~0x1); BWN_PHY_SET(mac, BWN_NPHY_AFECTL_OVER, 0x1); bwn_ntab_write(mac, BWN_NTAB16(8, 0x05), 0); bwn_ntab_write(mac, BWN_NTAB16(8, 0x15), 0); BWN_PHY_MASK(mac, BWN_NPHY_AFECTL_C1, ~0x4); BWN_PHY_MASK(mac, BWN_NPHY_AFECTL_OVER1, ~0x4); BWN_PHY_MASK(mac, BWN_NPHY_AFECTL_C2, ~0x4); BWN_PHY_MASK(mac, BWN_NPHY_AFECTL_OVER, ~0x4); } BWN_PHY_WRITE(mac, BWN_NPHY_ENDROP_TLEN, 0x2); bwn_ntab_write(mac, BWN_NTAB32(16, 0x100), 20); bwn_ntab_write_bulk(mac, BWN_NTAB8(7, 0x138), 2, ntab7_138_146); bwn_ntab_write(mac, BWN_NTAB16(7, 0x141), 0x77); bwn_ntab_write_bulk(mac, BWN_NTAB8(7, 0x133), 3, ntab7_133); bwn_ntab_write_bulk(mac, BWN_NTAB8(7, 0x146), 2, ntab7_138_146); bwn_ntab_write(mac, BWN_NTAB16(7, 0x123), 0x77); bwn_ntab_write(mac, BWN_NTAB16(7, 0x12A), 0x77); bwn_ntab_read_bulk(mac, BWN_NTAB32(16, 0x02), 1, noise_tbl); noise_tbl[1] = bwn_is_40mhz(mac) ? 0x14D : 0x18D; bwn_ntab_write_bulk(mac, BWN_NTAB32(16, 0x02), 2, noise_tbl); bwn_ntab_read_bulk(mac, BWN_NTAB32(16, 0x7E), 1, noise_tbl); noise_tbl[1] = bwn_is_40mhz(mac) ? 0x14D : 0x18D; bwn_ntab_write_bulk(mac, BWN_NTAB32(16, 0x7E), 2, noise_tbl); bwn_nphy_gain_ctl_workarounds(mac); /* TODO bwn_ntab_write_bulk(mac, BWN_NTAB16(8, 0x08), 4, aux_adc_vmid_rev7_core0); bwn_ntab_write_bulk(mac, BWN_NTAB16(8, 0x18), 4, aux_adc_vmid_rev7_core1); bwn_ntab_write_bulk(mac, BWN_NTAB16(8, 0x0C), 4, aux_adc_gain_rev7); bwn_ntab_write_bulk(mac, BWN_NTAB16(8, 0x1C), 4, aux_adc_gain_rev7); */ + + return (0); } -static void bwn_nphy_workarounds_rev3plus(struct bwn_mac *mac) +static int bwn_nphy_workarounds_rev3plus(struct bwn_mac *mac) { struct bwn_softc *sc = mac->mac_sc; struct bwn_phy_n *nphy = mac->mac_phy.phy_n; /* TX to RX */ uint8_t tx2rx_events[7] = { 0x4, 0x3, 0x5, 0x2, 0x1, 0x8, 0x1F }; uint8_t tx2rx_delays[7] = { 8, 4, 4, 4, 4, 6, 1 }; /* RX to TX */ uint8_t rx2tx_events_ipa[9] = { 0x0, 0x1, 0x2, 0x8, 0x5, 0x6, 0xF, 0x3, 0x1F }; uint8_t rx2tx_delays_ipa[9] = { 8, 6, 6, 4, 4, 16, 43, 1, 1 }; uint8_t rx2tx_events[9] = { 0x0, 0x1, 0x2, 0x8, 0x5, 0x6, 0x3, 0x4, 0x1F }; uint8_t rx2tx_delays[9] = { 8, 6, 6, 4, 4, 18, 42, 1, 1 }; uint16_t vmids[5][4] = { { 0xa2, 0xb4, 0xb4, 0x89, }, /* 0 */ { 0xb4, 0xb4, 0xb4, 0x24, }, /* 1 */ { 0xa2, 0xb4, 0xb4, 0x74, }, /* 2 */ { 0xa2, 0xb4, 0xb4, 0x270, }, /* 3 */ { 0xa2, 0xb4, 0xb4, 0x00, }, /* 4 and 5 */ }; uint16_t gains[5][4] = { { 0x02, 0x02, 0x02, 0x00, }, /* 0 */ { 0x02, 0x02, 0x02, 0x02, }, /* 1 */ { 0x02, 0x02, 0x02, 0x04, }, /* 2 */ { 0x02, 0x02, 0x02, 0x00, }, /* 3 */ { 0x02, 0x02, 0x02, 0x00, }, /* 4 and 5 */ }; uint16_t *vmid, *gain; + const char *pdet_range_var; uint8_t pdet_range; uint16_t tmp16; uint32_t tmp32; + int error; BWN_PHY_WRITE(mac, BWN_NPHY_FORCEFRONT0, 0x1f8); BWN_PHY_WRITE(mac, BWN_NPHY_FORCEFRONT1, 0x1f8); tmp32 = bwn_ntab_read(mac, BWN_NTAB32(30, 0)); tmp32 &= 0xffffff; bwn_ntab_write(mac, BWN_NTAB32(30, 0), tmp32); BWN_PHY_WRITE(mac, BWN_NPHY_PHASETR_A0, 0x0125); BWN_PHY_WRITE(mac, BWN_NPHY_PHASETR_A1, 0x01B3); BWN_PHY_WRITE(mac, BWN_NPHY_PHASETR_A2, 0x0105); BWN_PHY_WRITE(mac, BWN_NPHY_PHASETR_B0, 0x016E); BWN_PHY_WRITE(mac, BWN_NPHY_PHASETR_B1, 0x00CD); BWN_PHY_WRITE(mac, BWN_NPHY_PHASETR_B2, 0x0020); BWN_PHY_WRITE(mac, BWN_NPHY_REV3_C1_CLIP_LOGAIN_B, 0x000C); BWN_PHY_WRITE(mac, BWN_NPHY_REV3_C2_CLIP_LOGAIN_B, 0x000C); /* TX to RX */ bwn_nphy_set_rf_sequence(mac, 1, tx2rx_events, tx2rx_delays, nitems(tx2rx_events)); /* RX to TX */ if (bwn_nphy_ipa(mac)) bwn_nphy_set_rf_sequence(mac, 0, rx2tx_events_ipa, rx2tx_delays_ipa, nitems(rx2tx_events_ipa)); if (nphy->hw_phyrxchain != 3 && nphy->hw_phyrxchain != nphy->hw_phytxchain) { if (bwn_nphy_ipa(mac)) { rx2tx_delays[5] = 59; rx2tx_delays[6] = 1; rx2tx_events[7] = 0x1F; } bwn_nphy_set_rf_sequence(mac, 0, rx2tx_events, rx2tx_delays, nitems(rx2tx_events)); } tmp16 = (bwn_current_band(mac) == BWN_BAND_2G) ? 0x2 : 0x9C40; BWN_PHY_WRITE(mac, BWN_NPHY_ENDROP_TLEN, tmp16); BWN_PHY_SETMASK(mac, BWN_NPHY_SGILTRNOFFSET, 0xF0FF, 0x0700); if (!bwn_is_40mhz(mac)) { bwn_ntab_write(mac, BWN_NTAB32(16, 3), 0x18D); bwn_ntab_write(mac, BWN_NTAB32(16, 127), 0x18D); } else { bwn_ntab_write(mac, BWN_NTAB32(16, 3), 0x14D); bwn_ntab_write(mac, BWN_NTAB32(16, 127), 0x14D); } bwn_nphy_gain_ctl_workarounds(mac); bwn_ntab_write(mac, BWN_NTAB16(8, 0), 2); bwn_ntab_write(mac, BWN_NTAB16(8, 16), 2); if (bwn_current_band(mac) == BWN_BAND_2G) - pdet_range = siba_sprom_get_fem_2ghz_pdet_range(sc->sc_dev); + pdet_range_var = BHND_NVAR_PDETRANGE2G; else - pdet_range = siba_sprom_get_fem_5ghz_pdet_range(sc->sc_dev); + pdet_range_var = BHND_NVAR_PDETRANGE5G; + + error = bhnd_nvram_getvar_uint8(sc->sc_dev, pdet_range_var, + &pdet_range); + if (error) { + BWN_ERRPRINTF(mac->mac_sc, "Error reading PDet range %s from " + "NVRAM: %d\n", pdet_range_var, error); + return (error); + } + /* uint16_t min() */ vmid = vmids[min(pdet_range, 4)]; gain = gains[min(pdet_range, 4)]; switch (pdet_range) { case 3: if (!(mac->mac_phy.rev >= 4 && bwn_current_band(mac) == BWN_BAND_2G)) break; /* FALL THROUGH */ case 0: case 1: bwn_ntab_write_bulk(mac, BWN_NTAB16(8, 0x08), 4, vmid); bwn_ntab_write_bulk(mac, BWN_NTAB16(8, 0x18), 4, vmid); bwn_ntab_write_bulk(mac, BWN_NTAB16(8, 0x0c), 4, gain); bwn_ntab_write_bulk(mac, BWN_NTAB16(8, 0x1c), 4, gain); break; case 2: if (mac->mac_phy.rev >= 6) { if (bwn_current_band(mac) == BWN_BAND_2G) vmid[3] = 0x94; else vmid[3] = 0x8e; gain[3] = 3; } else if (mac->mac_phy.rev == 5) { vmid[3] = 0x84; gain[3] = 2; } bwn_ntab_write_bulk(mac, BWN_NTAB16(8, 0x08), 4, vmid); bwn_ntab_write_bulk(mac, BWN_NTAB16(8, 0x18), 4, vmid); bwn_ntab_write_bulk(mac, BWN_NTAB16(8, 0x0c), 4, gain); bwn_ntab_write_bulk(mac, BWN_NTAB16(8, 0x1c), 4, gain); break; case 4: case 5: if (bwn_current_band(mac) != BWN_BAND_2G) { if (pdet_range == 4) { vmid[3] = 0x8e; tmp16 = 0x96; gain[3] = 0x2; } else { vmid[3] = 0x89; tmp16 = 0x89; gain[3] = 0; } } else { if (pdet_range == 4) { vmid[3] = 0x89; tmp16 = 0x8b; gain[3] = 0x2; } else { vmid[3] = 0x74; tmp16 = 0x70; gain[3] = 0; } } bwn_ntab_write_bulk(mac, BWN_NTAB16(8, 0x08), 4, vmid); bwn_ntab_write_bulk(mac, BWN_NTAB16(8, 0x0c), 4, gain); vmid[3] = tmp16; bwn_ntab_write_bulk(mac, BWN_NTAB16(8, 0x18), 4, vmid); bwn_ntab_write_bulk(mac, BWN_NTAB16(8, 0x1c), 4, gain); break; } BWN_RF_WRITE(mac, B2056_RX0 | B2056_RX_MIXA_MAST_BIAS, 0x00); BWN_RF_WRITE(mac, B2056_RX1 | B2056_RX_MIXA_MAST_BIAS, 0x00); BWN_RF_WRITE(mac, B2056_RX0 | B2056_RX_MIXA_BIAS_MAIN, 0x06); BWN_RF_WRITE(mac, B2056_RX1 | B2056_RX_MIXA_BIAS_MAIN, 0x06); BWN_RF_WRITE(mac, B2056_RX0 | B2056_RX_MIXA_BIAS_AUX, 0x07); BWN_RF_WRITE(mac, B2056_RX1 | B2056_RX_MIXA_BIAS_AUX, 0x07); BWN_RF_WRITE(mac, B2056_RX0 | B2056_RX_MIXA_LOB_BIAS, 0x88); BWN_RF_WRITE(mac, B2056_RX1 | B2056_RX_MIXA_LOB_BIAS, 0x88); BWN_RF_WRITE(mac, B2056_RX0 | B2056_RX_MIXA_CMFB_IDAC, 0x00); BWN_RF_WRITE(mac, B2056_RX1 | B2056_RX_MIXA_CMFB_IDAC, 0x00); BWN_RF_WRITE(mac, B2056_RX0 | B2056_RX_MIXG_CMFB_IDAC, 0x00); BWN_RF_WRITE(mac, B2056_RX1 | B2056_RX_MIXG_CMFB_IDAC, 0x00); /* N PHY WAR TX Chain Update with hw_phytxchain as argument */ - if ((siba_sprom_get_bf2_lo(sc->sc_dev) & BWN_BFL2_APLL_WAR && + if ((sc->sc_board_info.board_flags2 & BHND_BFL2_APLL_WAR && bwn_current_band(mac) == BWN_BAND_5G) || - (siba_sprom_get_bf2_lo(sc->sc_dev) & BWN_BFL2_GPLL_WAR && + (sc->sc_board_info.board_flags2 & BHND_BFL2_GPLL_WAR2 && bwn_current_band(mac) == BWN_BAND_2G)) tmp32 = 0x00088888; else tmp32 = 0x88888888; bwn_ntab_write(mac, BWN_NTAB32(30, 1), tmp32); bwn_ntab_write(mac, BWN_NTAB32(30, 2), tmp32); bwn_ntab_write(mac, BWN_NTAB32(30, 3), tmp32); if (mac->mac_phy.rev == 4 && bwn_current_band(mac) == BWN_BAND_5G) { BWN_RF_WRITE(mac, B2056_TX0 | B2056_TX_GMBB_IDAC, 0x70); BWN_RF_WRITE(mac, B2056_TX1 | B2056_TX_GMBB_IDAC, 0x70); } /* Dropped probably-always-true condition */ BWN_PHY_WRITE(mac, BWN_NPHY_ED_CRS40ASSERTTHRESH0, 0x03eb); BWN_PHY_WRITE(mac, BWN_NPHY_ED_CRS40ASSERTTHRESH1, 0x03eb); BWN_PHY_WRITE(mac, BWN_NPHY_ED_CRS40DEASSERTTHRESH0, 0x0341); BWN_PHY_WRITE(mac, BWN_NPHY_ED_CRS40DEASSERTTHRESH1, 0x0341); BWN_PHY_WRITE(mac, BWN_NPHY_ED_CRS20LASSERTTHRESH0, 0x042b); BWN_PHY_WRITE(mac, BWN_NPHY_ED_CRS20LASSERTTHRESH1, 0x042b); BWN_PHY_WRITE(mac, BWN_NPHY_ED_CRS20LDEASSERTTHRESH0, 0x0381); BWN_PHY_WRITE(mac, BWN_NPHY_ED_CRS20LDEASSERTTHRESH1, 0x0381); BWN_PHY_WRITE(mac, BWN_NPHY_ED_CRS20UASSERTTHRESH0, 0x042b); BWN_PHY_WRITE(mac, BWN_NPHY_ED_CRS20UASSERTTHRESH1, 0x042b); BWN_PHY_WRITE(mac, BWN_NPHY_ED_CRS20UDEASSERTTHRESH0, 0x0381); BWN_PHY_WRITE(mac, BWN_NPHY_ED_CRS20UDEASSERTTHRESH1, 0x0381); - if (mac->mac_phy.rev >= 6 && siba_sprom_get_bf2_lo(sc->sc_dev) & BWN_BFL2_SINGLEANT_CCK) + if (mac->mac_phy.rev >= 6 && sc->sc_board_info.board_flags2 & BHND_BFL2_SINGLEANT_CCK) ; /* TODO: 0x0080000000000000 HF */ + + return (0); } -static void bwn_nphy_workarounds_rev1_2(struct bwn_mac *mac) +static int bwn_nphy_workarounds_rev1_2(struct bwn_mac *mac) { struct bwn_softc *sc = mac->mac_sc; struct bwn_phy *phy = &mac->mac_phy; struct bwn_phy_n *nphy = phy->phy_n; uint8_t events1[7] = { 0x0, 0x1, 0x2, 0x8, 0x4, 0x5, 0x3 }; uint8_t delays1[7] = { 0x8, 0x6, 0x6, 0x2, 0x4, 0x3C, 0x1 }; uint8_t events2[7] = { 0x0, 0x3, 0x5, 0x4, 0x2, 0x1, 0x8 }; uint8_t delays2[7] = { 0x8, 0x6, 0x2, 0x4, 0x4, 0x6, 0x1 }; - if (siba_sprom_get_bf2_lo(sc->sc_dev) & BWN_BFL2_SKWRKFEM_BRD || - siba_get_pci_subdevice(sc->sc_dev)== BCMA_BOARD_TYPE_BCM943224M93) { + if (sc->sc_board_info.board_flags2 & BHND_BFL2_SKWRKFEM_BRD || + sc->sc_board_info.board_type == BHND_BOARD_BCM943224M93) { delays1[0] = 0x1; delays1[5] = 0x14; } if (bwn_current_band(mac) == BWN_BAND_5G && nphy->band5g_pwrgain) { BWN_RF_MASK(mac, B2055_C1_TX_RF_SPARE, ~0x8); BWN_RF_MASK(mac, B2055_C2_TX_RF_SPARE, ~0x8); } else { BWN_RF_SET(mac, B2055_C1_TX_RF_SPARE, 0x8); BWN_RF_SET(mac, B2055_C2_TX_RF_SPARE, 0x8); } bwn_ntab_write(mac, BWN_NTAB16(8, 0x00), 0x000A); bwn_ntab_write(mac, BWN_NTAB16(8, 0x10), 0x000A); if (mac->mac_phy.rev < 3) { bwn_ntab_write(mac, BWN_NTAB16(8, 0x02), 0xCDAA); bwn_ntab_write(mac, BWN_NTAB16(8, 0x12), 0xCDAA); } if (mac->mac_phy.rev < 2) { bwn_ntab_write(mac, BWN_NTAB16(8, 0x08), 0x0000); bwn_ntab_write(mac, BWN_NTAB16(8, 0x18), 0x0000); bwn_ntab_write(mac, BWN_NTAB16(8, 0x07), 0x7AAB); bwn_ntab_write(mac, BWN_NTAB16(8, 0x17), 0x7AAB); bwn_ntab_write(mac, BWN_NTAB16(8, 0x06), 0x0800); bwn_ntab_write(mac, BWN_NTAB16(8, 0x16), 0x0800); } BWN_PHY_WRITE(mac, BWN_NPHY_RFCTL_LUT_TRSW_LO1, 0x2D8); BWN_PHY_WRITE(mac, BWN_NPHY_RFCTL_LUT_TRSW_UP1, 0x301); BWN_PHY_WRITE(mac, BWN_NPHY_RFCTL_LUT_TRSW_LO2, 0x2D8); BWN_PHY_WRITE(mac, BWN_NPHY_RFCTL_LUT_TRSW_UP2, 0x301); bwn_nphy_set_rf_sequence(mac, 0, events1, delays1, 7); bwn_nphy_set_rf_sequence(mac, 1, events2, delays2, 7); bwn_nphy_gain_ctl_workarounds(mac); if (mac->mac_phy.rev < 2) { if (BWN_PHY_READ(mac, BWN_NPHY_RXCTL) & 0x2) bwn_hf_write(mac, bwn_hf_read(mac) | BWN_HF_MLADVW); } else if (mac->mac_phy.rev == 2) { BWN_PHY_WRITE(mac, BWN_NPHY_CRSCHECK2, 0); BWN_PHY_WRITE(mac, BWN_NPHY_CRSCHECK3, 0); } if (mac->mac_phy.rev < 2) BWN_PHY_MASK(mac, BWN_NPHY_SCRAM_SIGCTL, ~BWN_NPHY_SCRAM_SIGCTL_SCM); /* Set phase track alpha and beta */ BWN_PHY_WRITE(mac, BWN_NPHY_PHASETR_A0, 0x125); BWN_PHY_WRITE(mac, BWN_NPHY_PHASETR_A1, 0x1B3); BWN_PHY_WRITE(mac, BWN_NPHY_PHASETR_A2, 0x105); BWN_PHY_WRITE(mac, BWN_NPHY_PHASETR_B0, 0x16E); BWN_PHY_WRITE(mac, BWN_NPHY_PHASETR_B1, 0xCD); BWN_PHY_WRITE(mac, BWN_NPHY_PHASETR_B2, 0x20); if (mac->mac_phy.rev < 3) { BWN_PHY_MASK(mac, BWN_NPHY_PIL_DW1, ~BWN_NPHY_PIL_DW_64QAM & 0xFFFF); BWN_PHY_WRITE(mac, BWN_NPHY_TXF_20CO_S2B1, 0xB5); BWN_PHY_WRITE(mac, BWN_NPHY_TXF_20CO_S2B2, 0xA4); BWN_PHY_WRITE(mac, BWN_NPHY_TXF_20CO_S2B3, 0x00); } if (mac->mac_phy.rev == 2) BWN_PHY_SET(mac, BWN_NPHY_FINERX2_CGC, BWN_NPHY_FINERX2_CGC_DECGC); + + return (0); } /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/Workarounds */ -static void bwn_nphy_workarounds(struct bwn_mac *mac) +static int bwn_nphy_workarounds(struct bwn_mac *mac) { struct bwn_phy *phy = &mac->mac_phy; struct bwn_phy_n *nphy = phy->phy_n; + int error; if (bwn_current_band(mac) == BWN_BAND_5G) bwn_nphy_classifier(mac, 1, 0); else bwn_nphy_classifier(mac, 1, 1); if (nphy->hang_avoid) bwn_nphy_stay_in_carrier_search(mac, 1); BWN_PHY_SET(mac, BWN_NPHY_IQFLIP, BWN_NPHY_IQFLIP_ADC1 | BWN_NPHY_IQFLIP_ADC2); /* TODO: rev19+ */ if (mac->mac_phy.rev >= 7) - bwn_nphy_workarounds_rev7plus(mac); + error = bwn_nphy_workarounds_rev7plus(mac); else if (mac->mac_phy.rev >= 3) - bwn_nphy_workarounds_rev3plus(mac); + error = bwn_nphy_workarounds_rev3plus(mac); else - bwn_nphy_workarounds_rev1_2(mac); + error = bwn_nphy_workarounds_rev1_2(mac); + if (error) + return (error); + if (nphy->hang_avoid) bwn_nphy_stay_in_carrier_search(mac, 0); + + return (0); } /************************************************** * Tx/Rx common **************************************************/ /* * Transmits a known value for LO calibration * http://bcm-v4.sipsolutions.net/802.11/PHY/N/TXTone */ static int bwn_nphy_tx_tone(struct bwn_mac *mac, uint32_t freq, uint16_t max_val, bool iqmode, bool dac_test, bool modify_bbmult) { uint16_t samp = bwn_nphy_gen_load_samples(mac, freq, max_val, dac_test); if (samp == 0) return -1; bwn_nphy_run_samples(mac, samp, 0xFFFF, 0, iqmode, dac_test, modify_bbmult); return 0; } /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/Chains */ static void bwn_nphy_update_txrx_chain(struct bwn_mac *mac) { struct bwn_phy_n *nphy = mac->mac_phy.phy_n; bool override = false; uint16_t chain = 0x33; if (nphy->txrx_chain == 0) { chain = 0x11; override = true; } else if (nphy->txrx_chain == 1) { chain = 0x22; override = true; } BWN_PHY_SETMASK(mac, BWN_NPHY_RFSEQCA, ~(BWN_NPHY_RFSEQCA_TXEN | BWN_NPHY_RFSEQCA_RXEN), chain); if (override) BWN_PHY_SET(mac, BWN_NPHY_RFSEQMODE, BWN_NPHY_RFSEQMODE_CAOVER); else BWN_PHY_MASK(mac, BWN_NPHY_RFSEQMODE, ~BWN_NPHY_RFSEQMODE_CAOVER); } /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/stop-playback */ static void bwn_nphy_stop_playback(struct bwn_mac *mac) { struct bwn_phy *phy = &mac->mac_phy; struct bwn_phy_n *nphy = mac->mac_phy.phy_n; uint16_t tmp; if (nphy->hang_avoid) bwn_nphy_stay_in_carrier_search(mac, 1); tmp = BWN_PHY_READ(mac, BWN_NPHY_SAMP_STAT); if (tmp & 0x1) BWN_PHY_SET(mac, BWN_NPHY_SAMP_CMD, BWN_NPHY_SAMP_CMD_STOP); else if (tmp & 0x2) BWN_PHY_MASK(mac, BWN_NPHY_IQLOCAL_CMDGCTL, 0x7FFF); BWN_PHY_MASK(mac, BWN_NPHY_SAMP_CMD, ~0x0004); if (nphy->bb_mult_save & 0x80000000) { tmp = nphy->bb_mult_save & 0xFFFF; bwn_ntab_write(mac, BWN_NTAB16(15, 87), tmp); nphy->bb_mult_save = 0; } if (phy->rev >= 7 && nphy->lpf_bw_overrode_for_sample_play) { if (phy->rev >= 19) bwn_nphy_rf_ctl_override_rev19(mac, 0x80, 0, 0, true, 1); else bwn_nphy_rf_ctl_override_rev7(mac, 0x80, 0, 0, true, 1); nphy->lpf_bw_overrode_for_sample_play = false; } if (nphy->hang_avoid) bwn_nphy_stay_in_carrier_search(mac, 0); } /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/IqCalGainParams */ static void bwn_nphy_iq_cal_gain_params(struct bwn_mac *mac, uint16_t core, struct bwn_nphy_txgains target, struct bwn_nphy_iqcal_params *params) { struct bwn_phy *phy = &mac->mac_phy; int i, j, indx; uint16_t gain; if (mac->mac_phy.rev >= 3) { params->tx_lpf = target.tx_lpf[core]; /* Rev 7+ */ params->txgm = target.txgm[core]; params->pga = target.pga[core]; params->pad = target.pad[core]; params->ipa = target.ipa[core]; if (phy->rev >= 19) { /* TODO */ } else if (phy->rev >= 7) { params->cal_gain = (params->txgm << 12) | (params->pga << 8) | (params->pad << 3) | (params->ipa) | (params->tx_lpf << 15); } else { params->cal_gain = (params->txgm << 12) | (params->pga << 8) | (params->pad << 4) | (params->ipa); } for (j = 0; j < 5; j++) params->ncorr[j] = 0x79; } else { gain = (target.pad[core]) | (target.pga[core] << 4) | (target.txgm[core] << 8); indx = (bwn_current_band(mac) == BWN_BAND_5G) ? 1 : 0; for (i = 0; i < 9; i++) if (tbl_iqcal_gainparams[indx][i][0] == gain) break; i = min(i, 8); params->txgm = tbl_iqcal_gainparams[indx][i][1]; params->pga = tbl_iqcal_gainparams[indx][i][2]; params->pad = tbl_iqcal_gainparams[indx][i][3]; params->cal_gain = (params->txgm << 7) | (params->pga << 4) | (params->pad << 2); for (j = 0; j < 4; j++) params->ncorr[j] = tbl_iqcal_gainparams[indx][i][4 + j]; } } /************************************************** * Tx and Rx **************************************************/ /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxPwrCtrlEnable */ static void bwn_nphy_tx_power_ctrl(struct bwn_mac *mac, bool enable) { struct bwn_phy *phy = &mac->mac_phy; struct bwn_phy_n *nphy = mac->mac_phy.phy_n; uint8_t i; uint16_t bmask, val, tmp; bwn_band_t band = bwn_current_band(mac); if (nphy->hang_avoid) bwn_nphy_stay_in_carrier_search(mac, 1); nphy->txpwrctrl = enable; if (!enable) { if (mac->mac_phy.rev >= 3 && (BWN_PHY_READ(mac, BWN_NPHY_TXPCTL_CMD) & (BWN_NPHY_TXPCTL_CMD_COEFF | BWN_NPHY_TXPCTL_CMD_HWPCTLEN | BWN_NPHY_TXPCTL_CMD_PCTLEN))) { /* We disable enabled TX pwr ctl, save it's state */ nphy->tx_pwr_idx[0] = BWN_PHY_READ(mac, BWN_NPHY_C1_TXPCTL_STAT) & 0x7f; nphy->tx_pwr_idx[1] = BWN_PHY_READ(mac, BWN_NPHY_C2_TXPCTL_STAT) & 0x7f; } BWN_PHY_WRITE(mac, BWN_NPHY_TABLE_ADDR, 0x6840); for (i = 0; i < 84; i++) BWN_PHY_WRITE(mac, BWN_NPHY_TABLE_DATALO, 0); BWN_PHY_WRITE(mac, BWN_NPHY_TABLE_ADDR, 0x6C40); for (i = 0; i < 84; i++) BWN_PHY_WRITE(mac, BWN_NPHY_TABLE_DATALO, 0); tmp = BWN_NPHY_TXPCTL_CMD_COEFF | BWN_NPHY_TXPCTL_CMD_HWPCTLEN; if (mac->mac_phy.rev >= 3) tmp |= BWN_NPHY_TXPCTL_CMD_PCTLEN; BWN_PHY_MASK(mac, BWN_NPHY_TXPCTL_CMD, ~tmp); if (mac->mac_phy.rev >= 3) { BWN_PHY_SET(mac, BWN_NPHY_AFECTL_OVER1, 0x0100); BWN_PHY_SET(mac, BWN_NPHY_AFECTL_OVER, 0x0100); } else { BWN_PHY_SET(mac, BWN_NPHY_AFECTL_OVER, 0x4000); } if (mac->mac_phy.rev == 2) BWN_PHY_SETMASK(mac, BWN_NPHY_BPHY_CTL3, ~BWN_NPHY_BPHY_CTL3_SCALE, 0x53); else if (mac->mac_phy.rev < 2) BWN_PHY_SETMASK(mac, BWN_NPHY_BPHY_CTL3, ~BWN_NPHY_BPHY_CTL3_SCALE, 0x5A); if (mac->mac_phy.rev < 2 && bwn_is_40mhz(mac)) bwn_hf_write(mac, bwn_hf_read(mac) | BWN_HF_TSSI_RESET_PSM_WORKAROUN); } else { bwn_ntab_write_bulk(mac, BWN_NTAB16(26, 64), 84, nphy->adj_pwr_tbl); bwn_ntab_write_bulk(mac, BWN_NTAB16(27, 64), 84, nphy->adj_pwr_tbl); bmask = BWN_NPHY_TXPCTL_CMD_COEFF | BWN_NPHY_TXPCTL_CMD_HWPCTLEN; /* wl does useless check for "enable" param here */ val = BWN_NPHY_TXPCTL_CMD_COEFF | BWN_NPHY_TXPCTL_CMD_HWPCTLEN; if (mac->mac_phy.rev >= 3) { bmask |= BWN_NPHY_TXPCTL_CMD_PCTLEN; if (val) val |= BWN_NPHY_TXPCTL_CMD_PCTLEN; } BWN_PHY_SETMASK(mac, BWN_NPHY_TXPCTL_CMD, ~(bmask), val); if (band == BWN_BAND_5G) { if (phy->rev >= 19) { /* TODO */ } else if (phy->rev >= 7) { BWN_PHY_SETMASK(mac, BWN_NPHY_TXPCTL_CMD, ~BWN_NPHY_TXPCTL_CMD_INIT, 0x32); BWN_PHY_SETMASK(mac, BWN_NPHY_TXPCTL_INIT, ~BWN_NPHY_TXPCTL_INIT_PIDXI1, 0x32); } else { BWN_PHY_SETMASK(mac, BWN_NPHY_TXPCTL_CMD, ~BWN_NPHY_TXPCTL_CMD_INIT, 0x64); if (phy->rev > 1) BWN_PHY_SETMASK(mac, BWN_NPHY_TXPCTL_INIT, ~BWN_NPHY_TXPCTL_INIT_PIDXI1, 0x64); } } if (mac->mac_phy.rev >= 3) { if (nphy->tx_pwr_idx[0] != 128 && nphy->tx_pwr_idx[1] != 128) { /* Recover TX pwr ctl state */ BWN_PHY_SETMASK(mac, BWN_NPHY_TXPCTL_CMD, ~BWN_NPHY_TXPCTL_CMD_INIT, nphy->tx_pwr_idx[0]); if (mac->mac_phy.rev > 1) BWN_PHY_SETMASK(mac, BWN_NPHY_TXPCTL_INIT, ~0xff, nphy->tx_pwr_idx[1]); } } if (phy->rev >= 7) { /* TODO */ } if (mac->mac_phy.rev >= 3) { BWN_PHY_MASK(mac, BWN_NPHY_AFECTL_OVER1, ~0x100); BWN_PHY_MASK(mac, BWN_NPHY_AFECTL_OVER, ~0x100); } else { BWN_PHY_MASK(mac, BWN_NPHY_AFECTL_OVER, ~0x4000); } if (mac->mac_phy.rev == 2) BWN_PHY_SETMASK(mac, BWN_NPHY_BPHY_CTL3, ~0xFF, 0x3b); else if (mac->mac_phy.rev < 2) BWN_PHY_SETMASK(mac, BWN_NPHY_BPHY_CTL3, ~0xFF, 0x40); if (mac->mac_phy.rev < 2 && bwn_is_40mhz(mac)) bwn_hf_write(mac, bwn_hf_read(mac) & ~BWN_HF_TSSI_RESET_PSM_WORKAROUN); if (bwn_nphy_ipa(mac)) { BWN_PHY_MASK(mac, BWN_NPHY_PAPD_EN0, ~0x4); BWN_PHY_MASK(mac, BWN_NPHY_PAPD_EN1, ~0x4); } } if (nphy->hang_avoid) bwn_nphy_stay_in_carrier_search(mac, 0); } /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxPwrFix */ -static void bwn_nphy_tx_power_fix(struct bwn_mac *mac) +static int bwn_nphy_tx_power_fix(struct bwn_mac *mac) { struct bwn_softc *sc = mac->mac_sc; struct bwn_phy_n *nphy = mac->mac_phy.phy_n; uint8_t txpi[2], bbmult, i; uint16_t tmp, radio_gain, dac_gain; uint16_t freq = bwn_get_centre_freq(mac); uint32_t txgain; /* uint32_t gaintbl; rev3+ */ if (nphy->hang_avoid) bwn_nphy_stay_in_carrier_search(mac, 1); /* TODO: rev19+ */ if (mac->mac_phy.rev >= 7) { txpi[0] = txpi[1] = 30; } else if (mac->mac_phy.rev >= 3) { txpi[0] = 40; txpi[1] = 40; - } else if (siba_sprom_get_rev(sc->sc_dev) < 4) { + } else if (sc->sc_board_info.board_srom_rev < 4) { txpi[0] = 72; txpi[1] = 72; } else { +#define BWN_NPHY_GET_TXPI(_name, _result) \ +do { \ + int error; \ + error = bhnd_nvram_getvar_uint8(sc->sc_dev, (_name), \ + (_result)); \ + if (error) { \ + device_printf(sc->sc_dev, "NVRAM variable %s " \ + "unreadable: %d\n", (_name), error); \ + return (error); \ + } \ +} while(0) + if (bwn_current_band(mac) == BWN_BAND_2G) { - txpi[0] = siba_sprom_get_txpid_2g_0(sc->sc_dev); - txpi[1] = siba_sprom_get_txpid_2g_1(sc->sc_dev); + BWN_NPHY_GET_TXPI(BHND_NVAR_TXPID2GA0, &txpi[0]); + BWN_NPHY_GET_TXPI(BHND_NVAR_TXPID2GA1, &txpi[1]); } else if (freq >= 4900 && freq < 5100) { - txpi[0] = siba_sprom_get_txpid_5gl_0(sc->sc_dev); - txpi[1] = siba_sprom_get_txpid_5gl_1(sc->sc_dev); + BWN_NPHY_GET_TXPI(BHND_NVAR_TXPID5GLA0, &txpi[0]); + BWN_NPHY_GET_TXPI(BHND_NVAR_TXPID5GLA1, &txpi[1]); } else if (freq >= 5100 && freq < 5500) { - txpi[0] = siba_sprom_get_txpid_5g_0(sc->sc_dev); - txpi[1] = siba_sprom_get_txpid_5g_1(sc->sc_dev); + BWN_NPHY_GET_TXPI(BHND_NVAR_TXPID5GA0, &txpi[0]); + BWN_NPHY_GET_TXPI(BHND_NVAR_TXPID5GA1, &txpi[1]); } else if (freq >= 5500) { - txpi[0] = siba_sprom_get_txpid_5gh_0(sc->sc_dev); - txpi[1] = siba_sprom_get_txpid_5gh_1(sc->sc_dev); + BWN_NPHY_GET_TXPI(BHND_NVAR_TXPID5GHA0, &txpi[0]); + BWN_NPHY_GET_TXPI(BHND_NVAR_TXPID5GHA1, &txpi[1]); } else { txpi[0] = 91; txpi[1] = 91; } + +#undef BWN_NPHY_GET_TXPI } if (mac->mac_phy.rev < 7 && (txpi[0] < 40 || txpi[0] > 100 || txpi[1] < 40 || txpi[1] > 100)) txpi[0] = txpi[1] = 91; /* for (i = 0; i < 2; i++) { nphy->txpwrindex[i].index_internal = txpi[i]; nphy->txpwrindex[i].index_internal_save = txpi[i]; } */ for (i = 0; i < 2; i++) { const uint32_t *table = bwn_nphy_get_tx_gain_table(mac); if (!table) break; txgain = *(table + txpi[i]); if (mac->mac_phy.rev >= 3) radio_gain = (txgain >> 16) & 0x1FFFF; else radio_gain = (txgain >> 16) & 0x1FFF; if (mac->mac_phy.rev >= 7) dac_gain = (txgain >> 8) & 0x7; else dac_gain = (txgain >> 8) & 0x3F; bbmult = txgain & 0xFF; if (mac->mac_phy.rev >= 3) { if (i == 0) BWN_PHY_SET(mac, BWN_NPHY_AFECTL_OVER1, 0x0100); else BWN_PHY_SET(mac, BWN_NPHY_AFECTL_OVER, 0x0100); } else { BWN_PHY_SET(mac, BWN_NPHY_AFECTL_OVER, 0x4000); } if (i == 0) BWN_PHY_WRITE(mac, BWN_NPHY_AFECTL_DACGAIN1, dac_gain); else BWN_PHY_WRITE(mac, BWN_NPHY_AFECTL_DACGAIN2, dac_gain); bwn_ntab_write(mac, BWN_NTAB16(0x7, 0x110 + i), radio_gain); tmp = bwn_ntab_read(mac, BWN_NTAB16(0xF, 0x57)); if (i == 0) tmp = (tmp & 0x00FF) | (bbmult << 8); else tmp = (tmp & 0xFF00) | bbmult; bwn_ntab_write(mac, BWN_NTAB16(0xF, 0x57), tmp); if (bwn_nphy_ipa(mac)) { uint32_t tmp32; uint16_t reg = (i == 0) ? BWN_NPHY_PAPD_EN0 : BWN_NPHY_PAPD_EN1; tmp32 = bwn_ntab_read(mac, BWN_NTAB32(26 + i, 576 + txpi[i])); BWN_PHY_SETMASK(mac, reg, 0xE00F, (uint32_t) tmp32 << 4); BWN_PHY_SET(mac, reg, 0x4); } } BWN_PHY_MASK(mac, BWN_NPHY_BPHY_CTL2, ~BWN_NPHY_BPHY_CTL2_LUT); if (nphy->hang_avoid) bwn_nphy_stay_in_carrier_search(mac, 0); + + return (0); } static void bwn_nphy_ipa_internal_tssi_setup(struct bwn_mac *mac) { struct bwn_phy *phy = &mac->mac_phy; uint8_t core; uint16_t r; /* routing */ if (phy->rev >= 19) { /* TODO */ } else if (phy->rev >= 7) { for (core = 0; core < 2; core++) { r = core ? 0x190 : 0x170; if (bwn_current_band(mac) == BWN_BAND_2G) { BWN_RF_WRITE(mac, r + 0x5, 0x5); BWN_RF_WRITE(mac, r + 0x9, 0xE); if (phy->rev != 5) BWN_RF_WRITE(mac, r + 0xA, 0); if (phy->rev != 7) BWN_RF_WRITE(mac, r + 0xB, 1); else BWN_RF_WRITE(mac, r + 0xB, 0x31); } else { BWN_RF_WRITE(mac, r + 0x5, 0x9); BWN_RF_WRITE(mac, r + 0x9, 0xC); BWN_RF_WRITE(mac, r + 0xB, 0x0); if (phy->rev != 5) BWN_RF_WRITE(mac, r + 0xA, 1); else BWN_RF_WRITE(mac, r + 0xA, 0x31); } BWN_RF_WRITE(mac, r + 0x6, 0); BWN_RF_WRITE(mac, r + 0x7, 0); BWN_RF_WRITE(mac, r + 0x8, 3); BWN_RF_WRITE(mac, r + 0xC, 0); } } else { if (bwn_current_band(mac) == BWN_BAND_2G) BWN_RF_WRITE(mac, B2056_SYN_RESERVED_ADDR31, 0x128); else BWN_RF_WRITE(mac, B2056_SYN_RESERVED_ADDR31, 0x80); BWN_RF_WRITE(mac, B2056_SYN_RESERVED_ADDR30, 0); BWN_RF_WRITE(mac, B2056_SYN_GPIO_MASTER1, 0x29); for (core = 0; core < 2; core++) { r = core ? B2056_TX1 : B2056_TX0; BWN_RF_WRITE(mac, r | B2056_TX_IQCAL_VCM_HG, 0); BWN_RF_WRITE(mac, r | B2056_TX_IQCAL_IDAC, 0); BWN_RF_WRITE(mac, r | B2056_TX_TSSI_VCM, 3); BWN_RF_WRITE(mac, r | B2056_TX_TX_AMP_DET, 0); BWN_RF_WRITE(mac, r | B2056_TX_TSSI_MISC1, 8); BWN_RF_WRITE(mac, r | B2056_TX_TSSI_MISC2, 0); BWN_RF_WRITE(mac, r | B2056_TX_TSSI_MISC3, 0); if (bwn_current_band(mac) == BWN_BAND_2G) { BWN_RF_WRITE(mac, r | B2056_TX_TX_SSI_MASTER, 0x5); if (phy->rev != 5) BWN_RF_WRITE(mac, r | B2056_TX_TSSIA, 0x00); if (phy->rev >= 5) BWN_RF_WRITE(mac, r | B2056_TX_TSSIG, 0x31); else BWN_RF_WRITE(mac, r | B2056_TX_TSSIG, 0x11); BWN_RF_WRITE(mac, r | B2056_TX_TX_SSI_MUX, 0xE); } else { BWN_RF_WRITE(mac, r | B2056_TX_TX_SSI_MASTER, 0x9); BWN_RF_WRITE(mac, r | B2056_TX_TSSIA, 0x31); BWN_RF_WRITE(mac, r | B2056_TX_TSSIG, 0x0); BWN_RF_WRITE(mac, r | B2056_TX_TX_SSI_MUX, 0xC); } } } } /* * Stop radio and transmit known signal. Then check received signal strength to * get TSSI (Transmit Signal Strength Indicator). * http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxPwrCtrlIdleTssi */ static void bwn_nphy_tx_power_ctl_idle_tssi(struct bwn_mac *mac) { struct bwn_phy *phy = &mac->mac_phy; struct bwn_phy_n *nphy = mac->mac_phy.phy_n; uint32_t tmp; int32_t rssi[4] = { }; if (bwn_is_chan_passive(mac)) return; if (bwn_nphy_ipa(mac)) bwn_nphy_ipa_internal_tssi_setup(mac); if (phy->rev >= 19) bwn_nphy_rf_ctl_override_rev19(mac, 0x1000, 0, 3, false, 0); else if (phy->rev >= 7) bwn_nphy_rf_ctl_override_rev7(mac, 0x1000, 0, 3, false, 0); else if (phy->rev >= 3) bwn_nphy_rf_ctl_override(mac, 0x2000, 0, 3, false); bwn_nphy_stop_playback(mac); bwn_nphy_tx_tone(mac, 4000, 0, false, false, false); DELAY(20); tmp = bwn_nphy_poll_rssi(mac, N_RSSI_TSSI_2G, rssi, 1); bwn_nphy_stop_playback(mac); bwn_nphy_rssi_select(mac, 0, N_RSSI_W1); if (phy->rev >= 19) bwn_nphy_rf_ctl_override_rev19(mac, 0x1000, 0, 3, true, 0); else if (phy->rev >= 7) bwn_nphy_rf_ctl_override_rev7(mac, 0x1000, 0, 3, true, 0); else if (phy->rev >= 3) bwn_nphy_rf_ctl_override(mac, 0x2000, 0, 3, true); if (phy->rev >= 19) { /* TODO */ return; } else if (phy->rev >= 3) { nphy->pwr_ctl_info[0].idle_tssi_5g = (tmp >> 24) & 0xFF; nphy->pwr_ctl_info[1].idle_tssi_5g = (tmp >> 8) & 0xFF; } else { nphy->pwr_ctl_info[0].idle_tssi_5g = (tmp >> 16) & 0xFF; nphy->pwr_ctl_info[1].idle_tssi_5g = tmp & 0xFF; } nphy->pwr_ctl_info[0].idle_tssi_2g = (tmp >> 24) & 0xFF; nphy->pwr_ctl_info[1].idle_tssi_2g = (tmp >> 8) & 0xFF; } /* http://bcm-v4.sipsolutions.net/PHY/N/TxPwrLimitToTbl */ static void bwn_nphy_tx_prepare_adjusted_power_table(struct bwn_mac *mac) { struct bwn_phy_n *nphy = mac->mac_phy.phy_n; uint8_t idx, delta; uint8_t i, stf_mode; /* Array adj_pwr_tbl corresponds to the hardware table. It consists of * 21 groups, each containing 4 entries. * * First group has entries for CCK modulation. * The rest of groups has 1 entry per modulation (SISO, CDD, STBC, SDM). * * Group 0 is for CCK * Groups 1..4 use BPSK (group per coding rate) * Groups 5..8 use QPSK (group per coding rate) * Groups 9..12 use 16-QAM (group per coding rate) * Groups 13..16 use 64-QAM (group per coding rate) * Groups 17..20 are unknown */ for (i = 0; i < 4; i++) nphy->adj_pwr_tbl[i] = nphy->tx_power_offset[i]; for (stf_mode = 0; stf_mode < 4; stf_mode++) { delta = 0; switch (stf_mode) { case 0: if (bwn_is_40mhz(mac) && mac->mac_phy.rev >= 5) { idx = 68; } else { delta = 1; idx = bwn_is_40mhz(mac) ? 52 : 4; } break; case 1: idx = bwn_is_40mhz(mac) ? 76 : 28; break; case 2: idx = bwn_is_40mhz(mac) ? 84 : 36; break; case 3: idx = bwn_is_40mhz(mac) ? 92 : 44; break; } for (i = 0; i < 20; i++) { nphy->adj_pwr_tbl[4 + 4 * i + stf_mode] = nphy->tx_power_offset[idx]; if (i == 0) idx += delta; if (i == 14) idx += 1 - delta; if (i == 3 || i == 4 || i == 7 || i == 8 || i == 11 || i == 13) idx += 1; } } } /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxPwrCtrlSetup */ static void bwn_nphy_tx_power_ctl_setup(struct bwn_mac *mac) { struct bwn_softc *sc = mac->mac_sc; struct bwn_phy *phy = &mac->mac_phy; struct bwn_phy_n *nphy = mac->mac_phy.phy_n; - struct siba_sprom_core_pwr_info core_pwr_info[4]; + struct bwn_phy_n_core_pwr_info core_pwr_info[4]; int n; int16_t a1[2], b0[2], b1[2]; uint8_t idle[2]; uint8_t ppr_max; int8_t target[2]; int32_t num, den, pwr; uint32_t regval[64]; uint16_t freq = bwn_get_centre_freq(mac); uint16_t tmp; uint16_t r; /* routing */ uint8_t i, c; for (n = 0; n < 4; n++) { bzero(&core_pwr_info[n], sizeof(core_pwr_info[n])); - if (siba_sprom_get_core_power_info(sc->sc_dev, n, + if (bwn_nphy_get_core_power_info(mac, n, &core_pwr_info[n]) != 0) { BWN_ERRPRINTF(mac->mac_sc, "%s: failed to get core_pwr_info for core %d\n", __func__, n); } } - if (siba_get_revid(sc->sc_dev) == 11 || siba_get_revid(sc->sc_dev) == 12) { + if (bhnd_get_hwrev(sc->sc_dev) == 11 || bhnd_get_hwrev(sc->sc_dev) == 12) { BWN_WRITE_SETMASK4(mac, BWN_MACCTL, ~0, 0x200000); BWN_READ_4(mac, BWN_MACCTL); DELAY(1); } if (nphy->hang_avoid) bwn_nphy_stay_in_carrier_search(mac, true); BWN_PHY_SET(mac, BWN_NPHY_TSSIMODE, BWN_NPHY_TSSIMODE_EN); if (mac->mac_phy.rev >= 3) BWN_PHY_MASK(mac, BWN_NPHY_TXPCTL_CMD, ~BWN_NPHY_TXPCTL_CMD_PCTLEN & 0xFFFF); else BWN_PHY_SET(mac, BWN_NPHY_TXPCTL_CMD, BWN_NPHY_TXPCTL_CMD_PCTLEN); - if (siba_get_revid(sc->sc_dev) == 11 || siba_get_revid(sc->sc_dev) == 12) + if (bhnd_get_hwrev(sc->sc_dev) == 11 || bhnd_get_hwrev(sc->sc_dev) == 12) BWN_WRITE_SETMASK4(mac, BWN_MACCTL, ~0x200000, 0); /* * XXX TODO: see if those bandsbelow map to 5g-lo, 5g-mid, 5g-hi in * any way. */ - if (siba_sprom_get_rev(sc->sc_dev) < 4) { + if (sc->sc_board_info.board_srom_rev < 4) { idle[0] = nphy->pwr_ctl_info[0].idle_tssi_2g; idle[1] = nphy->pwr_ctl_info[1].idle_tssi_2g; target[0] = target[1] = 52; a1[0] = a1[1] = -424; b0[0] = b0[1] = 5612; b1[0] = b1[1] = -1393; } else { if (bwn_current_band(mac) == BWN_BAND_2G) { for (c = 0; c < 2; c++) { idle[c] = nphy->pwr_ctl_info[c].idle_tssi_2g; target[c] = core_pwr_info[c].maxpwr_2g; a1[c] = core_pwr_info[c].pa_2g[0]; b0[c] = core_pwr_info[c].pa_2g[1]; b1[c] = core_pwr_info[c].pa_2g[2]; } } else if (freq >= 4900 && freq < 5100) { for (c = 0; c < 2; c++) { idle[c] = nphy->pwr_ctl_info[c].idle_tssi_5g; target[c] = core_pwr_info[c].maxpwr_5gl; a1[c] = core_pwr_info[c].pa_5gl[0]; b0[c] = core_pwr_info[c].pa_5gl[1]; b1[c] = core_pwr_info[c].pa_5gl[2]; } } else if (freq >= 5100 && freq < 5500) { for (c = 0; c < 2; c++) { idle[c] = nphy->pwr_ctl_info[c].idle_tssi_5g; target[c] = core_pwr_info[c].maxpwr_5g; a1[c] = core_pwr_info[c].pa_5g[0]; b0[c] = core_pwr_info[c].pa_5g[1]; b1[c] = core_pwr_info[c].pa_5g[2]; } } else if (freq >= 5500) { for (c = 0; c < 2; c++) { idle[c] = nphy->pwr_ctl_info[c].idle_tssi_5g; target[c] = core_pwr_info[c].maxpwr_5gh; a1[c] = core_pwr_info[c].pa_5gh[0]; b0[c] = core_pwr_info[c].pa_5gh[1]; b1[c] = core_pwr_info[c].pa_5gh[2]; } } else { idle[0] = nphy->pwr_ctl_info[0].idle_tssi_5g; idle[1] = nphy->pwr_ctl_info[1].idle_tssi_5g; target[0] = target[1] = 52; a1[0] = a1[1] = -424; b0[0] = b0[1] = 5612; b1[0] = b1[1] = -1393; } } ppr_max = bwn_ppr_get_max(mac, &nphy->tx_pwr_max_ppr); if (ppr_max) { target[0] = ppr_max; target[1] = ppr_max; } if (mac->mac_phy.rev >= 3) { - if (siba_sprom_get_fem_2ghz_tssipos(sc->sc_dev)) + if (nphy->tsspos_2g) BWN_PHY_SET(mac, BWN_NPHY_TXPCTL_ITSSI, 0x4000); if (mac->mac_phy.rev >= 7) { for (c = 0; c < 2; c++) { r = c ? 0x190 : 0x170; if (bwn_nphy_ipa(mac)) BWN_RF_WRITE(mac, r + 0x9, (bwn_current_band(mac) == BWN_BAND_2G) ? 0xE : 0xC); } } else { if (bwn_nphy_ipa(mac)) { tmp = (bwn_current_band(mac) == BWN_BAND_5G) ? 0xC : 0xE; BWN_RF_WRITE(mac, B2056_TX0 | B2056_TX_TX_SSI_MUX, tmp); BWN_RF_WRITE(mac, B2056_TX1 | B2056_TX_TX_SSI_MUX, tmp); } else { BWN_RF_WRITE(mac, B2056_TX0 | B2056_TX_TX_SSI_MUX, 0x11); BWN_RF_WRITE(mac, B2056_TX1 | B2056_TX_TX_SSI_MUX, 0x11); } } } - if (siba_get_revid(sc->sc_dev) == 11 || siba_get_revid(sc->sc_dev) == 12) { + if (bhnd_get_hwrev(sc->sc_dev) == 11 || bhnd_get_hwrev(sc->sc_dev) == 12) { BWN_WRITE_SETMASK4(mac, BWN_MACCTL, ~0, 0x200000); BWN_READ_4(mac, BWN_MACCTL); DELAY(1); } if (phy->rev >= 19) { /* TODO */ } else if (phy->rev >= 7) { BWN_PHY_SETMASK(mac, BWN_NPHY_TXPCTL_CMD, ~BWN_NPHY_TXPCTL_CMD_INIT, 0x19); BWN_PHY_SETMASK(mac, BWN_NPHY_TXPCTL_INIT, ~BWN_NPHY_TXPCTL_INIT_PIDXI1, 0x19); } else { BWN_PHY_SETMASK(mac, BWN_NPHY_TXPCTL_CMD, ~BWN_NPHY_TXPCTL_CMD_INIT, 0x40); if (mac->mac_phy.rev > 1) BWN_PHY_SETMASK(mac, BWN_NPHY_TXPCTL_INIT, ~BWN_NPHY_TXPCTL_INIT_PIDXI1, 0x40); } - if (siba_get_revid(sc->sc_dev) == 11 || siba_get_revid(sc->sc_dev) == 12) + if (bhnd_get_hwrev(sc->sc_dev) == 11 || bhnd_get_hwrev(sc->sc_dev) == 12) BWN_WRITE_SETMASK4(mac, BWN_MACCTL, ~0x200000, 0); BWN_PHY_WRITE(mac, BWN_NPHY_TXPCTL_N, 0xF0 << BWN_NPHY_TXPCTL_N_TSSID_SHIFT | 3 << BWN_NPHY_TXPCTL_N_NPTIL2_SHIFT); BWN_PHY_WRITE(mac, BWN_NPHY_TXPCTL_ITSSI, idle[0] << BWN_NPHY_TXPCTL_ITSSI_0_SHIFT | idle[1] << BWN_NPHY_TXPCTL_ITSSI_1_SHIFT | BWN_NPHY_TXPCTL_ITSSI_BINF); BWN_PHY_WRITE(mac, BWN_NPHY_TXPCTL_TPWR, target[0] << BWN_NPHY_TXPCTL_TPWR_0_SHIFT | target[1] << BWN_NPHY_TXPCTL_TPWR_1_SHIFT); for (c = 0; c < 2; c++) { for (i = 0; i < 64; i++) { num = 8 * (16 * b0[c] + b1[c] * i); den = 32768 + a1[c] * i; pwr = max((4 * num + den / 2) / den, -8); if (mac->mac_phy.rev < 3 && (i <= (31 - idle[c] + 1))) pwr = max(pwr, target[c] + 1); regval[i] = pwr; } bwn_ntab_write_bulk(mac, BWN_NTAB32(26 + c, 0), 64, regval); } bwn_nphy_tx_prepare_adjusted_power_table(mac); bwn_ntab_write_bulk(mac, BWN_NTAB16(26, 64), 84, nphy->adj_pwr_tbl); bwn_ntab_write_bulk(mac, BWN_NTAB16(27, 64), 84, nphy->adj_pwr_tbl); if (nphy->hang_avoid) bwn_nphy_stay_in_carrier_search(mac, false); } static void bwn_nphy_tx_gain_table_upload(struct bwn_mac *mac) { struct bwn_phy *phy = &mac->mac_phy; const uint32_t *table = NULL; uint32_t rfpwr_offset; uint8_t pga_gain, pad_gain; int i; const int16_t *rf_pwr_offset_table = NULL; table = bwn_nphy_get_tx_gain_table(mac); if (!table) return; bwn_ntab_write_bulk(mac, BWN_NTAB32(26, 192), 128, table); bwn_ntab_write_bulk(mac, BWN_NTAB32(27, 192), 128, table); if (phy->rev < 3) return; #if 0 nphy->gmval = (table[0] >> 16) & 0x7000; #endif if (phy->rev >= 19) { return; } else if (phy->rev >= 7) { rf_pwr_offset_table = bwn_ntab_get_rf_pwr_offset_table(mac); if (!rf_pwr_offset_table) return; /* TODO: Enable this once we have gains configured */ return; } for (i = 0; i < 128; i++) { if (phy->rev >= 19) { /* TODO */ return; } else if (phy->rev >= 7) { pga_gain = (table[i] >> 24) & 0xf; pad_gain = (table[i] >> 19) & 0x1f; if (bwn_current_band(mac) == BWN_BAND_2G) rfpwr_offset = rf_pwr_offset_table[pad_gain]; else rfpwr_offset = rf_pwr_offset_table[pga_gain]; } else { pga_gain = (table[i] >> 24) & 0xF; if (bwn_current_band(mac) == BWN_BAND_2G) rfpwr_offset = bwn_ntab_papd_pga_gain_delta_ipa_2g[pga_gain]; else rfpwr_offset = 0; /* FIXME */ } bwn_ntab_write(mac, BWN_NTAB32(26, 576 + i), rfpwr_offset); bwn_ntab_write(mac, BWN_NTAB32(27, 576 + i), rfpwr_offset); } } /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/PA%20override */ static void bwn_nphy_pa_override(struct bwn_mac *mac, bool enable) { struct bwn_phy_n *nphy = mac->mac_phy.phy_n; bwn_band_t band; uint16_t tmp; if (!enable) { nphy->rfctrl_intc1_save = BWN_PHY_READ(mac, BWN_NPHY_RFCTL_INTC1); nphy->rfctrl_intc2_save = BWN_PHY_READ(mac, BWN_NPHY_RFCTL_INTC2); band = bwn_current_band(mac); if (mac->mac_phy.rev >= 7) { tmp = 0x1480; } else if (mac->mac_phy.rev >= 3) { if (band == BWN_BAND_5G) tmp = 0x600; else tmp = 0x480; } else { if (band == BWN_BAND_5G) tmp = 0x180; else tmp = 0x120; } BWN_PHY_WRITE(mac, BWN_NPHY_RFCTL_INTC1, tmp); BWN_PHY_WRITE(mac, BWN_NPHY_RFCTL_INTC2, tmp); } else { BWN_PHY_WRITE(mac, BWN_NPHY_RFCTL_INTC1, nphy->rfctrl_intc1_save); BWN_PHY_WRITE(mac, BWN_NPHY_RFCTL_INTC2, nphy->rfctrl_intc2_save); } } /* * TX low-pass filter bandwidth setup * http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxLpFbw */ static void bwn_nphy_tx_lpf_bw(struct bwn_mac *mac) { uint16_t tmp; if (mac->mac_phy.rev < 3 || mac->mac_phy.rev >= 7) return; if (bwn_nphy_ipa(mac)) tmp = bwn_is_40mhz(mac) ? 5 : 4; else tmp = bwn_is_40mhz(mac) ? 3 : 1; BWN_PHY_WRITE(mac, BWN_NPHY_TXF_40CO_B32S2, (tmp << 9) | (tmp << 6) | (tmp << 3) | tmp); if (bwn_nphy_ipa(mac)) { tmp = bwn_is_40mhz(mac) ? 4 : 1; BWN_PHY_WRITE(mac, BWN_NPHY_TXF_40CO_B1S2, (tmp << 9) | (tmp << 6) | (tmp << 3) | tmp); } } /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RxIqEst */ static void bwn_nphy_rx_iq_est(struct bwn_mac *mac, struct bwn_nphy_iq_est *est, uint16_t samps, uint8_t time, bool wait) { int i; uint16_t tmp; BWN_PHY_WRITE(mac, BWN_NPHY_IQEST_SAMCNT, samps); BWN_PHY_SETMASK(mac, BWN_NPHY_IQEST_WT, ~BWN_NPHY_IQEST_WT_VAL, time); if (wait) BWN_PHY_SET(mac, BWN_NPHY_IQEST_CMD, BWN_NPHY_IQEST_CMD_MODE); else BWN_PHY_MASK(mac, BWN_NPHY_IQEST_CMD, ~BWN_NPHY_IQEST_CMD_MODE); BWN_PHY_SET(mac, BWN_NPHY_IQEST_CMD, BWN_NPHY_IQEST_CMD_START); for (i = 1000; i; i--) { tmp = BWN_PHY_READ(mac, BWN_NPHY_IQEST_CMD); if (!(tmp & BWN_NPHY_IQEST_CMD_START)) { est->i0_pwr = (BWN_PHY_READ(mac, BWN_NPHY_IQEST_IPACC_HI0) << 16) | BWN_PHY_READ(mac, BWN_NPHY_IQEST_IPACC_LO0); est->q0_pwr = (BWN_PHY_READ(mac, BWN_NPHY_IQEST_QPACC_HI0) << 16) | BWN_PHY_READ(mac, BWN_NPHY_IQEST_QPACC_LO0); est->iq0_prod = (BWN_PHY_READ(mac, BWN_NPHY_IQEST_IQACC_HI0) << 16) | BWN_PHY_READ(mac, BWN_NPHY_IQEST_IQACC_LO0); est->i1_pwr = (BWN_PHY_READ(mac, BWN_NPHY_IQEST_IPACC_HI1) << 16) | BWN_PHY_READ(mac, BWN_NPHY_IQEST_IPACC_LO1); est->q1_pwr = (BWN_PHY_READ(mac, BWN_NPHY_IQEST_QPACC_HI1) << 16) | BWN_PHY_READ(mac, BWN_NPHY_IQEST_QPACC_LO1); est->iq1_prod = (BWN_PHY_READ(mac, BWN_NPHY_IQEST_IQACC_HI1) << 16) | BWN_PHY_READ(mac, BWN_NPHY_IQEST_IQACC_LO1); return; } DELAY(10); } memset(est, 0, sizeof(*est)); } /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RxIqCoeffs */ static void bwn_nphy_rx_iq_coeffs(struct bwn_mac *mac, bool write, struct bwn_phy_n_iq_comp *pcomp) { if (write) { BWN_PHY_WRITE(mac, BWN_NPHY_C1_RXIQ_COMPA0, pcomp->a0); BWN_PHY_WRITE(mac, BWN_NPHY_C1_RXIQ_COMPB0, pcomp->b0); BWN_PHY_WRITE(mac, BWN_NPHY_C2_RXIQ_COMPA1, pcomp->a1); BWN_PHY_WRITE(mac, BWN_NPHY_C2_RXIQ_COMPB1, pcomp->b1); } else { pcomp->a0 = BWN_PHY_READ(mac, BWN_NPHY_C1_RXIQ_COMPA0); pcomp->b0 = BWN_PHY_READ(mac, BWN_NPHY_C1_RXIQ_COMPB0); pcomp->a1 = BWN_PHY_READ(mac, BWN_NPHY_C2_RXIQ_COMPA1); pcomp->b1 = BWN_PHY_READ(mac, BWN_NPHY_C2_RXIQ_COMPB1); } } #if 0 /* Ready but not used anywhere */ /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RxCalPhyCleanup */ static void bwn_nphy_rx_cal_phy_cleanup(struct bwn_mac *mac, uint8_t core) { uint16_t *regs = mac->mac_phy.phy_n->tx_rx_cal_phy_saveregs; BWN_PHY_WRITE(mac, BWN_NPHY_RFSEQCA, regs[0]); if (core == 0) { BWN_PHY_WRITE(mac, BWN_NPHY_AFECTL_C1, regs[1]); BWN_PHY_WRITE(mac, BWN_NPHY_AFECTL_OVER1, regs[2]); } else { BWN_PHY_WRITE(mac, BWN_NPHY_AFECTL_C2, regs[1]); BWN_PHY_WRITE(mac, BWN_NPHY_AFECTL_OVER, regs[2]); } BWN_PHY_WRITE(mac, BWN_NPHY_RFCTL_INTC1, regs[3]); BWN_PHY_WRITE(mac, BWN_NPHY_RFCTL_INTC2, regs[4]); BWN_PHY_WRITE(mac, BWN_NPHY_RFCTL_RSSIO1, regs[5]); BWN_PHY_WRITE(mac, BWN_NPHY_RFCTL_RSSIO2, regs[6]); BWN_PHY_WRITE(mac, BWN_NPHY_TXF_40CO_B1S1, regs[7]); BWN_PHY_WRITE(mac, BWN_NPHY_RFCTL_OVER, regs[8]); BWN_PHY_WRITE(mac, BWN_NPHY_PAPD_EN0, regs[9]); BWN_PHY_WRITE(mac, BWN_NPHY_PAPD_EN1, regs[10]); } /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RxCalPhySetup */ static void bwn_nphy_rx_cal_phy_setup(struct bwn_mac *mac, uint8_t core) { uint8_t rxval, txval; uint16_t *regs = mac->mac_phy.phy_n->tx_rx_cal_phy_saveregs; regs[0] = BWN_PHY_READ(mac, BWN_NPHY_RFSEQCA); if (core == 0) { regs[1] = BWN_PHY_READ(mac, BWN_NPHY_AFECTL_C1); regs[2] = BWN_PHY_READ(mac, BWN_NPHY_AFECTL_OVER1); } else { regs[1] = BWN_PHY_READ(mac, BWN_NPHY_AFECTL_C2); regs[2] = BWN_PHY_READ(mac, BWN_NPHY_AFECTL_OVER); } regs[3] = BWN_PHY_READ(mac, BWN_NPHY_RFCTL_INTC1); regs[4] = BWN_PHY_READ(mac, BWN_NPHY_RFCTL_INTC2); regs[5] = BWN_PHY_READ(mac, BWN_NPHY_RFCTL_RSSIO1); regs[6] = BWN_PHY_READ(mac, BWN_NPHY_RFCTL_RSSIO2); regs[7] = BWN_PHY_READ(mac, BWN_NPHY_TXF_40CO_B1S1); regs[8] = BWN_PHY_READ(mac, BWN_NPHY_RFCTL_OVER); regs[9] = BWN_PHY_READ(mac, BWN_NPHY_PAPD_EN0); regs[10] = BWN_PHY_READ(mac, BWN_NPHY_PAPD_EN1); BWN_PHY_MASK(mac, BWN_NPHY_PAPD_EN0, ~0x0001); BWN_PHY_MASK(mac, BWN_NPHY_PAPD_EN1, ~0x0001); BWN_PHY_SETMASK(mac, BWN_NPHY_RFSEQCA, ~BWN_NPHY_RFSEQCA_RXDIS & 0xFFFF, ((1 - core) << BWN_NPHY_RFSEQCA_RXDIS_SHIFT)); BWN_PHY_SETMASK(mac, BWN_NPHY_RFSEQCA, ~BWN_NPHY_RFSEQCA_TXEN, ((1 - core) << BWN_NPHY_RFSEQCA_TXEN_SHIFT)); BWN_PHY_SETMASK(mac, BWN_NPHY_RFSEQCA, ~BWN_NPHY_RFSEQCA_RXEN, (core << BWN_NPHY_RFSEQCA_RXEN_SHIFT)); BWN_PHY_SETMASK(mac, BWN_NPHY_RFSEQCA, ~BWN_NPHY_RFSEQCA_TXDIS, (core << BWN_NPHY_RFSEQCA_TXDIS_SHIFT)); if (core == 0) { BWN_PHY_MASK(mac, BWN_NPHY_AFECTL_C1, ~0x0007); BWN_PHY_SET(mac, BWN_NPHY_AFECTL_OVER1, 0x0007); } else { BWN_PHY_MASK(mac, BWN_NPHY_AFECTL_C2, ~0x0007); BWN_PHY_SET(mac, BWN_NPHY_AFECTL_OVER, 0x0007); } bwn_nphy_rf_ctl_intc_override(mac, N_INTC_OVERRIDE_PA, 0, 3); bwn_nphy_rf_ctl_override(mac, 8, 0, 3, false); bwn_nphy_force_rf_sequence(mac, BWN_RFSEQ_RX2TX); if (core == 0) { rxval = 1; txval = 8; } else { rxval = 4; txval = 2; } bwn_nphy_rf_ctl_intc_override(mac, N_INTC_OVERRIDE_TRSW, rxval, core + 1); bwn_nphy_rf_ctl_intc_override(mac, N_INTC_OVERRIDE_TRSW, txval, 2 - core); } #endif /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/CalcRxIqComp */ static void bwn_nphy_calc_rx_iq_comp(struct bwn_mac *mac, uint8_t mask) { int i; int32_t iq; uint32_t ii; uint32_t qq; int iq_nbits, qq_nbits; int arsh, brsh; uint16_t tmp, a, b; struct bwn_nphy_iq_est est; struct bwn_phy_n_iq_comp old; struct bwn_phy_n_iq_comp new = { }; bool error = false; if (mask == 0) return; bwn_nphy_rx_iq_coeffs(mac, false, &old); bwn_nphy_rx_iq_coeffs(mac, true, &new); bwn_nphy_rx_iq_est(mac, &est, 0x4000, 32, false); new = old; for (i = 0; i < 2; i++) { if (i == 0 && (mask & 1)) { iq = est.iq0_prod; ii = est.i0_pwr; qq = est.q0_pwr; } else if (i == 1 && (mask & 2)) { iq = est.iq1_prod; ii = est.i1_pwr; qq = est.q1_pwr; } else { continue; } if (ii + qq < 2) { error = true; break; } iq_nbits = fls(abs(iq)); qq_nbits = fls(qq); arsh = iq_nbits - 20; if (arsh >= 0) { a = -((iq << (30 - iq_nbits)) + (ii >> (1 + arsh))); tmp = ii >> arsh; } else { a = -((iq << (30 - iq_nbits)) + (ii << (-1 - arsh))); tmp = ii << -arsh; } if (tmp == 0) { error = true; break; } a /= tmp; brsh = qq_nbits - 11; if (brsh >= 0) { b = (qq << (31 - qq_nbits)); tmp = ii >> brsh; } else { b = (qq << (31 - qq_nbits)); tmp = ii << -brsh; } if (tmp == 0) { error = true; break; } b = bwn_sqrt(mac, b / tmp - a * a) - (1 << 10); if (i == 0 && (mask & 0x1)) { if (mac->mac_phy.rev >= 3) { new.a0 = a & 0x3FF; new.b0 = b & 0x3FF; } else { new.a0 = b & 0x3FF; new.b0 = a & 0x3FF; } } else if (i == 1 && (mask & 0x2)) { if (mac->mac_phy.rev >= 3) { new.a1 = a & 0x3FF; new.b1 = b & 0x3FF; } else { new.a1 = b & 0x3FF; new.b1 = a & 0x3FF; } } } if (error) new = old; bwn_nphy_rx_iq_coeffs(mac, true, &new); } /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxIqWar */ static void bwn_nphy_tx_iq_workaround(struct bwn_mac *mac) { uint16_t array[4]; bwn_ntab_read_bulk(mac, BWN_NTAB16(0xF, 0x50), 4, array); bwn_shm_write_2(mac, BWN_SHARED, BWN_SHM_SH_NPHY_TXIQW0, array[0]); bwn_shm_write_2(mac, BWN_SHARED, BWN_SHM_SH_NPHY_TXIQW1, array[1]); bwn_shm_write_2(mac, BWN_SHARED, BWN_SHM_SH_NPHY_TXIQW2, array[2]); bwn_shm_write_2(mac, BWN_SHARED, BWN_SHM_SH_NPHY_TXIQW3, array[3]); } /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/SpurWar */ static void bwn_nphy_spur_workaround(struct bwn_mac *mac) { struct bwn_phy_n *nphy = mac->mac_phy.phy_n; uint8_t channel = bwn_get_chan(mac); int tone[2] = { 57, 58 }; uint32_t noise[2] = { 0x3FF, 0x3FF }; if (mac->mac_phy.rev < 3) { BWN_ERRPRINTF(mac->mac_sc, "%s: phy rev %d out of range\n", __func__, mac->mac_phy.rev); } if (nphy->hang_avoid) bwn_nphy_stay_in_carrier_search(mac, 1); if (nphy->gband_spurwar_en) { /* TODO: N PHY Adjust Analog Pfbw (7) */ if (channel == 11 && bwn_is_40mhz(mac)) ; /* TODO: N PHY Adjust Min Noise Var(2, tone, noise)*/ else ; /* TODO: N PHY Adjust Min Noise Var(0, NULL, NULL)*/ /* TODO: N PHY Adjust CRS Min Power (0x1E) */ } if (nphy->aband_spurwar_en) { if (channel == 54) { tone[0] = 0x20; noise[0] = 0x25F; } else if (channel == 38 || channel == 102 || channel == 118) { if (0 /* FIXME */) { tone[0] = 0x20; noise[0] = 0x21F; } else { tone[0] = 0; noise[0] = 0; } } else if (channel == 134) { tone[0] = 0x20; noise[0] = 0x21F; } else if (channel == 151) { tone[0] = 0x10; noise[0] = 0x23F; } else if (channel == 153 || channel == 161) { tone[0] = 0x30; noise[0] = 0x23F; } else { tone[0] = 0; noise[0] = 0; } if (!tone[0] && !noise[0]) ; /* TODO: N PHY Adjust Min Noise Var(1, tone, noise)*/ else ; /* TODO: N PHY Adjust Min Noise Var(0, NULL, NULL)*/ } if (nphy->hang_avoid) bwn_nphy_stay_in_carrier_search(mac, 0); } /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxPwrCtrlCoefSetup */ static void bwn_nphy_tx_pwr_ctrl_coef_setup(struct bwn_mac *mac) { struct bwn_phy_n *nphy = mac->mac_phy.phy_n; int i, j; uint32_t tmp; uint32_t cur_real, cur_imag, real_part, imag_part; uint16_t buffer[7]; if (nphy->hang_avoid) bwn_nphy_stay_in_carrier_search(mac, true); bwn_ntab_read_bulk(mac, BWN_NTAB16(15, 80), 7, buffer); for (i = 0; i < 2; i++) { tmp = ((buffer[i * 2] & 0x3FF) << 10) | (buffer[i * 2 + 1] & 0x3FF); BWN_PHY_WRITE(mac, BWN_NPHY_TABLE_ADDR, (((i + 26) << 10) | 320)); for (j = 0; j < 128; j++) { BWN_PHY_WRITE(mac, BWN_NPHY_TABLE_DATAHI, ((tmp >> 16) & 0xFFFF)); BWN_PHY_WRITE(mac, BWN_NPHY_TABLE_DATALO, (tmp & 0xFFFF)); } } for (i = 0; i < 2; i++) { tmp = buffer[5 + i]; real_part = (tmp >> 8) & 0xFF; imag_part = (tmp & 0xFF); BWN_PHY_WRITE(mac, BWN_NPHY_TABLE_ADDR, (((i + 26) << 10) | 448)); if (mac->mac_phy.rev >= 3) { cur_real = real_part; cur_imag = imag_part; tmp = ((cur_real & 0xFF) << 8) | (cur_imag & 0xFF); } for (j = 0; j < 128; j++) { if (mac->mac_phy.rev < 3) { cur_real = (real_part * loscale[j] + 128) >> 8; cur_imag = (imag_part * loscale[j] + 128) >> 8; tmp = ((cur_real & 0xFF) << 8) | (cur_imag & 0xFF); } BWN_PHY_WRITE(mac, BWN_NPHY_TABLE_DATAHI, ((tmp >> 16) & 0xFFFF)); BWN_PHY_WRITE(mac, BWN_NPHY_TABLE_DATALO, (tmp & 0xFFFF)); } } if (mac->mac_phy.rev >= 3) { bwn_shm_write_2(mac, BWN_SHARED, BWN_SHM_SH_NPHY_TXPWR_INDX0, 0xFFFF); bwn_shm_write_2(mac, BWN_SHARED, BWN_SHM_SH_NPHY_TXPWR_INDX1, 0xFFFF); } if (nphy->hang_avoid) bwn_nphy_stay_in_carrier_search(mac, false); } /* * Restore RSSI Calibration * http://bcm-v4.sipsolutions.net/802.11/PHY/N/RestoreRssiCal */ static void bwn_nphy_restore_rssi_cal(struct bwn_mac *mac) { struct bwn_phy_n *nphy = mac->mac_phy.phy_n; uint16_t *rssical_radio_regs = NULL; uint16_t *rssical_phy_regs = NULL; if (bwn_current_band(mac) == BWN_BAND_2G) { if (!nphy->rssical_chanspec_2G.center_freq) return; rssical_radio_regs = nphy->rssical_cache.rssical_radio_regs_2G; rssical_phy_regs = nphy->rssical_cache.rssical_phy_regs_2G; } else { if (!nphy->rssical_chanspec_5G.center_freq) return; rssical_radio_regs = nphy->rssical_cache.rssical_radio_regs_5G; rssical_phy_regs = nphy->rssical_cache.rssical_phy_regs_5G; } if (mac->mac_phy.rev >= 19) { /* TODO */ } else if (mac->mac_phy.rev >= 7) { BWN_RF_SETMASK(mac, R2057_NB_MASTER_CORE0, ~R2057_VCM_MASK, rssical_radio_regs[0]); BWN_RF_SETMASK(mac, R2057_NB_MASTER_CORE1, ~R2057_VCM_MASK, rssical_radio_regs[1]); } else { BWN_RF_SETMASK(mac, B2056_RX0 | B2056_RX_RSSI_MISC, 0xE3, rssical_radio_regs[0]); BWN_RF_SETMASK(mac, B2056_RX1 | B2056_RX_RSSI_MISC, 0xE3, rssical_radio_regs[1]); } BWN_PHY_WRITE(mac, BWN_NPHY_RSSIMC_0I_RSSI_Z, rssical_phy_regs[0]); BWN_PHY_WRITE(mac, BWN_NPHY_RSSIMC_0Q_RSSI_Z, rssical_phy_regs[1]); BWN_PHY_WRITE(mac, BWN_NPHY_RSSIMC_1I_RSSI_Z, rssical_phy_regs[2]); BWN_PHY_WRITE(mac, BWN_NPHY_RSSIMC_1Q_RSSI_Z, rssical_phy_regs[3]); BWN_PHY_WRITE(mac, BWN_NPHY_RSSIMC_0I_RSSI_X, rssical_phy_regs[4]); BWN_PHY_WRITE(mac, BWN_NPHY_RSSIMC_0Q_RSSI_X, rssical_phy_regs[5]); BWN_PHY_WRITE(mac, BWN_NPHY_RSSIMC_1I_RSSI_X, rssical_phy_regs[6]); BWN_PHY_WRITE(mac, BWN_NPHY_RSSIMC_1Q_RSSI_X, rssical_phy_regs[7]); BWN_PHY_WRITE(mac, BWN_NPHY_RSSIMC_0I_RSSI_Y, rssical_phy_regs[8]); BWN_PHY_WRITE(mac, BWN_NPHY_RSSIMC_0Q_RSSI_Y, rssical_phy_regs[9]); BWN_PHY_WRITE(mac, BWN_NPHY_RSSIMC_1I_RSSI_Y, rssical_phy_regs[10]); BWN_PHY_WRITE(mac, BWN_NPHY_RSSIMC_1Q_RSSI_Y, rssical_phy_regs[11]); } static void bwn_nphy_tx_cal_radio_setup_rev19(struct bwn_mac *mac) { /* TODO */ } static void bwn_nphy_tx_cal_radio_setup_rev7(struct bwn_mac *mac) { struct bwn_phy *phy = &mac->mac_phy; struct bwn_phy_n *nphy = mac->mac_phy.phy_n; uint16_t *save = nphy->tx_rx_cal_radio_saveregs; int core, off; uint16_t r, tmp; for (core = 0; core < 2; core++) { r = core ? 0x20 : 0; off = core * 11; save[off + 0] = BWN_RF_READ(mac, r + R2057_TX0_TX_SSI_MASTER); save[off + 1] = BWN_RF_READ(mac, r + R2057_TX0_IQCAL_VCM_HG); save[off + 2] = BWN_RF_READ(mac, r + R2057_TX0_IQCAL_IDAC); save[off + 3] = BWN_RF_READ(mac, r + R2057_TX0_TSSI_VCM); save[off + 4] = 0; save[off + 5] = BWN_RF_READ(mac, r + R2057_TX0_TX_SSI_MUX); if (phy->rf_rev != 5) save[off + 6] = BWN_RF_READ(mac, r + R2057_TX0_TSSIA); save[off + 7] = BWN_RF_READ(mac, r + R2057_TX0_TSSIG); save[off + 8] = BWN_RF_READ(mac, r + R2057_TX0_TSSI_MISC1); if (bwn_current_band(mac) == BWN_BAND_5G) { BWN_RF_WRITE(mac, r + R2057_TX0_TX_SSI_MASTER, 0xA); BWN_RF_WRITE(mac, r + R2057_TX0_IQCAL_VCM_HG, 0x43); BWN_RF_WRITE(mac, r + R2057_TX0_IQCAL_IDAC, 0x55); BWN_RF_WRITE(mac, r + R2057_TX0_TSSI_VCM, 0); BWN_RF_WRITE(mac, r + R2057_TX0_TSSIG, 0); if (nphy->use_int_tx_iq_lo_cal) { BWN_RF_WRITE(mac, r + R2057_TX0_TX_SSI_MUX, 0x4); tmp = true ? 0x31 : 0x21; /* TODO */ BWN_RF_WRITE(mac, r + R2057_TX0_TSSIA, tmp); } BWN_RF_WRITE(mac, r + R2057_TX0_TSSI_MISC1, 0x00); } else { BWN_RF_WRITE(mac, r + R2057_TX0_TX_SSI_MASTER, 0x6); BWN_RF_WRITE(mac, r + R2057_TX0_IQCAL_VCM_HG, 0x43); BWN_RF_WRITE(mac, r + R2057_TX0_IQCAL_IDAC, 0x55); BWN_RF_WRITE(mac, r + R2057_TX0_TSSI_VCM, 0); if (phy->rf_rev != 5) BWN_RF_WRITE(mac, r + R2057_TX0_TSSIA, 0); if (nphy->use_int_tx_iq_lo_cal) { BWN_RF_WRITE(mac, r + R2057_TX0_TX_SSI_MUX, 0x6); tmp = true ? 0x31 : 0x21; /* TODO */ BWN_RF_WRITE(mac, r + R2057_TX0_TSSIG, tmp); } BWN_RF_WRITE(mac, r + R2057_TX0_TSSI_MISC1, 0); } } } /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxCalRadioSetup */ static void bwn_nphy_tx_cal_radio_setup(struct bwn_mac *mac) { struct bwn_phy *phy = &mac->mac_phy; struct bwn_phy_n *nphy = mac->mac_phy.phy_n; uint16_t *save = nphy->tx_rx_cal_radio_saveregs; uint16_t tmp; uint8_t offset, i; if (phy->rev >= 19) { bwn_nphy_tx_cal_radio_setup_rev19(mac); } else if (phy->rev >= 7) { bwn_nphy_tx_cal_radio_setup_rev7(mac); } else if (phy->rev >= 3) { for (i = 0; i < 2; i++) { tmp = (i == 0) ? 0x2000 : 0x3000; offset = i * 11; save[offset + 0] = BWN_RF_READ(mac, B2055_CAL_RVARCTL); save[offset + 1] = BWN_RF_READ(mac, B2055_CAL_LPOCTL); save[offset + 2] = BWN_RF_READ(mac, B2055_CAL_TS); save[offset + 3] = BWN_RF_READ(mac, B2055_CAL_RCCALRTS); save[offset + 4] = BWN_RF_READ(mac, B2055_CAL_RCALRTS); save[offset + 5] = BWN_RF_READ(mac, B2055_PADDRV); save[offset + 6] = BWN_RF_READ(mac, B2055_XOCTL1); save[offset + 7] = BWN_RF_READ(mac, B2055_XOCTL2); save[offset + 8] = BWN_RF_READ(mac, B2055_XOREGUL); save[offset + 9] = BWN_RF_READ(mac, B2055_XOMISC); save[offset + 10] = BWN_RF_READ(mac, B2055_PLL_LFC1); if (bwn_current_band(mac) == BWN_BAND_5G) { BWN_RF_WRITE(mac, tmp | B2055_CAL_RVARCTL, 0x0A); BWN_RF_WRITE(mac, tmp | B2055_CAL_LPOCTL, 0x40); BWN_RF_WRITE(mac, tmp | B2055_CAL_TS, 0x55); BWN_RF_WRITE(mac, tmp | B2055_CAL_RCCALRTS, 0); BWN_RF_WRITE(mac, tmp | B2055_CAL_RCALRTS, 0); if (nphy->ipa5g_on) { BWN_RF_WRITE(mac, tmp | B2055_PADDRV, 4); BWN_RF_WRITE(mac, tmp | B2055_XOCTL1, 1); } else { BWN_RF_WRITE(mac, tmp | B2055_PADDRV, 0); BWN_RF_WRITE(mac, tmp | B2055_XOCTL1, 0x2F); } BWN_RF_WRITE(mac, tmp | B2055_XOCTL2, 0); } else { BWN_RF_WRITE(mac, tmp | B2055_CAL_RVARCTL, 0x06); BWN_RF_WRITE(mac, tmp | B2055_CAL_LPOCTL, 0x40); BWN_RF_WRITE(mac, tmp | B2055_CAL_TS, 0x55); BWN_RF_WRITE(mac, tmp | B2055_CAL_RCCALRTS, 0); BWN_RF_WRITE(mac, tmp | B2055_CAL_RCALRTS, 0); BWN_RF_WRITE(mac, tmp | B2055_XOCTL1, 0); if (nphy->ipa2g_on) { BWN_RF_WRITE(mac, tmp | B2055_PADDRV, 6); BWN_RF_WRITE(mac, tmp | B2055_XOCTL2, (mac->mac_phy.rev < 5) ? 0x11 : 0x01); } else { BWN_RF_WRITE(mac, tmp | B2055_PADDRV, 0); BWN_RF_WRITE(mac, tmp | B2055_XOCTL2, 0); } } BWN_RF_WRITE(mac, tmp | B2055_XOREGUL, 0); BWN_RF_WRITE(mac, tmp | B2055_XOMISC, 0); BWN_RF_WRITE(mac, tmp | B2055_PLL_LFC1, 0); } } else { save[0] = BWN_RF_READ(mac, B2055_C1_TX_RF_IQCAL1); BWN_RF_WRITE(mac, B2055_C1_TX_RF_IQCAL1, 0x29); save[1] = BWN_RF_READ(mac, B2055_C1_TX_RF_IQCAL2); BWN_RF_WRITE(mac, B2055_C1_TX_RF_IQCAL2, 0x54); save[2] = BWN_RF_READ(mac, B2055_C2_TX_RF_IQCAL1); BWN_RF_WRITE(mac, B2055_C2_TX_RF_IQCAL1, 0x29); save[3] = BWN_RF_READ(mac, B2055_C2_TX_RF_IQCAL2); BWN_RF_WRITE(mac, B2055_C2_TX_RF_IQCAL2, 0x54); save[3] = BWN_RF_READ(mac, B2055_C1_PWRDET_RXTX); save[4] = BWN_RF_READ(mac, B2055_C2_PWRDET_RXTX); if (!(BWN_PHY_READ(mac, BWN_NPHY_BANDCTL) & BWN_NPHY_BANDCTL_5GHZ)) { BWN_RF_WRITE(mac, B2055_C1_PWRDET_RXTX, 0x04); BWN_RF_WRITE(mac, B2055_C2_PWRDET_RXTX, 0x04); } else { BWN_RF_WRITE(mac, B2055_C1_PWRDET_RXTX, 0x20); BWN_RF_WRITE(mac, B2055_C2_PWRDET_RXTX, 0x20); } if (mac->mac_phy.rev < 2) { BWN_RF_SET(mac, B2055_C1_TX_BB_MXGM, 0x20); BWN_RF_SET(mac, B2055_C2_TX_BB_MXGM, 0x20); } else { BWN_RF_MASK(mac, B2055_C1_TX_BB_MXGM, ~0x20); BWN_RF_MASK(mac, B2055_C2_TX_BB_MXGM, ~0x20); } } } /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/UpdateTxCalLadder */ static void bwn_nphy_update_tx_cal_ladder(struct bwn_mac *mac, uint16_t core) { struct bwn_phy_n *nphy = mac->mac_phy.phy_n; int i; uint16_t scale, entry; uint16_t tmp = nphy->txcal_bbmult; if (core == 0) tmp >>= 8; tmp &= 0xff; for (i = 0; i < 18; i++) { scale = (ladder_lo[i].percent * tmp) / 100; entry = ((scale & 0xFF) << 8) | ladder_lo[i].g_env; bwn_ntab_write(mac, BWN_NTAB16(15, i), entry); scale = (ladder_iq[i].percent * tmp) / 100; entry = ((scale & 0xFF) << 8) | ladder_iq[i].g_env; bwn_ntab_write(mac, BWN_NTAB16(15, i + 32), entry); } } static void bwn_nphy_pa_set_tx_dig_filter(struct bwn_mac *mac, uint16_t offset, const int16_t *filter) { int i; offset = BWN_PHY_N(offset); for (i = 0; i < 15; i++, offset++) BWN_PHY_WRITE(mac, offset, filter[i]); } /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/ExtPaSetTxDigiFilts */ static void bwn_nphy_ext_pa_set_tx_dig_filters(struct bwn_mac *mac) { bwn_nphy_pa_set_tx_dig_filter(mac, 0x2C5, tbl_tx_filter_coef_rev4[2]); } /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/IpaSetTxDigiFilts */ static void bwn_nphy_int_pa_set_tx_dig_filters(struct bwn_mac *mac) { /* BWN_NPHY_TXF_20CO_S0A1, BWN_NPHY_TXF_40CO_S0A1, unknown */ static const uint16_t offset[] = { 0x186, 0x195, 0x2C5 }; static const int16_t dig_filter_phy_rev16[] = { -375, 136, -407, 208, -1527, 956, 93, 186, 93, 230, -44, 230, 201, -191, 201, }; int i; for (i = 0; i < 3; i++) bwn_nphy_pa_set_tx_dig_filter(mac, offset[i], tbl_tx_filter_coef_rev4[i]); /* Verified with BCM43227 and BCM43228 */ if (mac->mac_phy.rev == 16) bwn_nphy_pa_set_tx_dig_filter(mac, 0x186, dig_filter_phy_rev16); /* Verified with BCM43131 and BCM43217 */ if (mac->mac_phy.rev == 17) { bwn_nphy_pa_set_tx_dig_filter(mac, 0x186, dig_filter_phy_rev16); bwn_nphy_pa_set_tx_dig_filter(mac, 0x195, tbl_tx_filter_coef_rev4[1]); } if (bwn_is_40mhz(mac)) { bwn_nphy_pa_set_tx_dig_filter(mac, 0x186, tbl_tx_filter_coef_rev4[3]); } else { if (bwn_current_band(mac) == BWN_BAND_5G) bwn_nphy_pa_set_tx_dig_filter(mac, 0x186, tbl_tx_filter_coef_rev4[5]); if (bwn_get_chan(mac) == 14) bwn_nphy_pa_set_tx_dig_filter(mac, 0x186, tbl_tx_filter_coef_rev4[6]); } } /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/GetTxGain */ static struct bwn_nphy_txgains bwn_nphy_get_tx_gains(struct bwn_mac *mac) { struct bwn_phy_n *nphy = mac->mac_phy.phy_n; uint16_t curr_gain[2]; struct bwn_nphy_txgains target; const uint32_t *table = NULL; if (!nphy->txpwrctrl) { int i; if (nphy->hang_avoid) bwn_nphy_stay_in_carrier_search(mac, true); bwn_ntab_read_bulk(mac, BWN_NTAB16(7, 0x110), 2, curr_gain); if (nphy->hang_avoid) bwn_nphy_stay_in_carrier_search(mac, false); for (i = 0; i < 2; ++i) { if (mac->mac_phy.rev >= 7) { target.ipa[i] = curr_gain[i] & 0x0007; target.pad[i] = (curr_gain[i] & 0x00F8) >> 3; target.pga[i] = (curr_gain[i] & 0x0F00) >> 8; target.txgm[i] = (curr_gain[i] & 0x7000) >> 12; target.tx_lpf[i] = (curr_gain[i] & 0x8000) >> 15; } else if (mac->mac_phy.rev >= 3) { target.ipa[i] = curr_gain[i] & 0x000F; target.pad[i] = (curr_gain[i] & 0x00F0) >> 4; target.pga[i] = (curr_gain[i] & 0x0F00) >> 8; target.txgm[i] = (curr_gain[i] & 0x7000) >> 12; } else { target.ipa[i] = curr_gain[i] & 0x0003; target.pad[i] = (curr_gain[i] & 0x000C) >> 2; target.pga[i] = (curr_gain[i] & 0x0070) >> 4; target.txgm[i] = (curr_gain[i] & 0x0380) >> 7; } } } else { int i; uint16_t index[2]; index[0] = (BWN_PHY_READ(mac, BWN_NPHY_C1_TXPCTL_STAT) & BWN_NPHY_TXPCTL_STAT_BIDX) >> BWN_NPHY_TXPCTL_STAT_BIDX_SHIFT; index[1] = (BWN_PHY_READ(mac, BWN_NPHY_C2_TXPCTL_STAT) & BWN_NPHY_TXPCTL_STAT_BIDX) >> BWN_NPHY_TXPCTL_STAT_BIDX_SHIFT; for (i = 0; i < 2; ++i) { table = bwn_nphy_get_tx_gain_table(mac); if (!table) break; if (mac->mac_phy.rev >= 7) { target.ipa[i] = (table[index[i]] >> 16) & 0x7; target.pad[i] = (table[index[i]] >> 19) & 0x1F; target.pga[i] = (table[index[i]] >> 24) & 0xF; target.txgm[i] = (table[index[i]] >> 28) & 0x7; target.tx_lpf[i] = (table[index[i]] >> 31) & 0x1; } else if (mac->mac_phy.rev >= 3) { target.ipa[i] = (table[index[i]] >> 16) & 0xF; target.pad[i] = (table[index[i]] >> 20) & 0xF; target.pga[i] = (table[index[i]] >> 24) & 0xF; target.txgm[i] = (table[index[i]] >> 28) & 0xF; } else { target.ipa[i] = (table[index[i]] >> 16) & 0x3; target.pad[i] = (table[index[i]] >> 18) & 0x3; target.pga[i] = (table[index[i]] >> 20) & 0x7; target.txgm[i] = (table[index[i]] >> 23) & 0x7; } } } return target; } /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxCalPhyCleanup */ static void bwn_nphy_tx_cal_phy_cleanup(struct bwn_mac *mac) { uint16_t *regs = mac->mac_phy.phy_n->tx_rx_cal_phy_saveregs; if (mac->mac_phy.rev >= 3) { BWN_PHY_WRITE(mac, BWN_NPHY_AFECTL_C1, regs[0]); BWN_PHY_WRITE(mac, BWN_NPHY_AFECTL_C2, regs[1]); BWN_PHY_WRITE(mac, BWN_NPHY_AFECTL_OVER1, regs[2]); BWN_PHY_WRITE(mac, BWN_NPHY_AFECTL_OVER, regs[3]); BWN_PHY_WRITE(mac, BWN_NPHY_BBCFG, regs[4]); bwn_ntab_write(mac, BWN_NTAB16(8, 3), regs[5]); bwn_ntab_write(mac, BWN_NTAB16(8, 19), regs[6]); BWN_PHY_WRITE(mac, BWN_NPHY_RFCTL_INTC1, regs[7]); BWN_PHY_WRITE(mac, BWN_NPHY_RFCTL_INTC2, regs[8]); BWN_PHY_WRITE(mac, BWN_NPHY_PAPD_EN0, regs[9]); BWN_PHY_WRITE(mac, BWN_NPHY_PAPD_EN1, regs[10]); bwn_nphy_reset_cca(mac); } else { BWN_PHY_SETMASK(mac, BWN_NPHY_AFECTL_C1, 0x0FFF, regs[0]); BWN_PHY_SETMASK(mac, BWN_NPHY_AFECTL_C2, 0x0FFF, regs[1]); BWN_PHY_WRITE(mac, BWN_NPHY_AFECTL_OVER, regs[2]); bwn_ntab_write(mac, BWN_NTAB16(8, 2), regs[3]); bwn_ntab_write(mac, BWN_NTAB16(8, 18), regs[4]); BWN_PHY_WRITE(mac, BWN_NPHY_RFCTL_INTC1, regs[5]); BWN_PHY_WRITE(mac, BWN_NPHY_RFCTL_INTC2, regs[6]); } } /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxCalPhySetup */ static void bwn_nphy_tx_cal_phy_setup(struct bwn_mac *mac) { struct bwn_phy *phy = &mac->mac_phy; struct bwn_phy_n *nphy = mac->mac_phy.phy_n; uint16_t *regs = mac->mac_phy.phy_n->tx_rx_cal_phy_saveregs; uint16_t tmp; regs[0] = BWN_PHY_READ(mac, BWN_NPHY_AFECTL_C1); regs[1] = BWN_PHY_READ(mac, BWN_NPHY_AFECTL_C2); if (mac->mac_phy.rev >= 3) { BWN_PHY_SETMASK(mac, BWN_NPHY_AFECTL_C1, 0xF0FF, 0x0A00); BWN_PHY_SETMASK(mac, BWN_NPHY_AFECTL_C2, 0xF0FF, 0x0A00); tmp = BWN_PHY_READ(mac, BWN_NPHY_AFECTL_OVER1); regs[2] = tmp; BWN_PHY_WRITE(mac, BWN_NPHY_AFECTL_OVER1, tmp | 0x0600); tmp = BWN_PHY_READ(mac, BWN_NPHY_AFECTL_OVER); regs[3] = tmp; BWN_PHY_WRITE(mac, BWN_NPHY_AFECTL_OVER, tmp | 0x0600); regs[4] = BWN_PHY_READ(mac, BWN_NPHY_BBCFG); BWN_PHY_MASK(mac, BWN_NPHY_BBCFG, ~BWN_NPHY_BBCFG_RSTRX & 0xFFFF); tmp = bwn_ntab_read(mac, BWN_NTAB16(8, 3)); regs[5] = tmp; bwn_ntab_write(mac, BWN_NTAB16(8, 3), 0); tmp = bwn_ntab_read(mac, BWN_NTAB16(8, 19)); regs[6] = tmp; bwn_ntab_write(mac, BWN_NTAB16(8, 19), 0); regs[7] = BWN_PHY_READ(mac, BWN_NPHY_RFCTL_INTC1); regs[8] = BWN_PHY_READ(mac, BWN_NPHY_RFCTL_INTC2); if (!nphy->use_int_tx_iq_lo_cal) bwn_nphy_rf_ctl_intc_override(mac, N_INTC_OVERRIDE_PA, 1, 3); else bwn_nphy_rf_ctl_intc_override(mac, N_INTC_OVERRIDE_PA, 0, 3); bwn_nphy_rf_ctl_intc_override(mac, N_INTC_OVERRIDE_TRSW, 2, 1); bwn_nphy_rf_ctl_intc_override(mac, N_INTC_OVERRIDE_TRSW, 8, 2); regs[9] = BWN_PHY_READ(mac, BWN_NPHY_PAPD_EN0); regs[10] = BWN_PHY_READ(mac, BWN_NPHY_PAPD_EN1); BWN_PHY_MASK(mac, BWN_NPHY_PAPD_EN0, ~0x0001); BWN_PHY_MASK(mac, BWN_NPHY_PAPD_EN1, ~0x0001); tmp = bwn_nphy_read_lpf_ctl(mac, 0); if (phy->rev >= 19) bwn_nphy_rf_ctl_override_rev19(mac, 0x80, tmp, 0, false, 1); else if (phy->rev >= 7) bwn_nphy_rf_ctl_override_rev7(mac, 0x80, tmp, 0, false, 1); if (nphy->use_int_tx_iq_lo_cal && true /* FIXME */) { if (phy->rev >= 19) { bwn_nphy_rf_ctl_override_rev19(mac, 0x8, 0, 0x3, false, 0); } else if (phy->rev >= 8) { bwn_nphy_rf_ctl_override_rev7(mac, 0x8, 0, 0x3, false, 0); } else if (phy->rev == 7) { BWN_RF_SETMASK(mac, R2057_OVR_REG0, 1 << 4, 1 << 4); if (bwn_current_band(mac) == BWN_BAND_2G) { BWN_RF_SETMASK(mac, R2057_PAD2G_TUNE_PUS_CORE0, ~1, 0); BWN_RF_SETMASK(mac, R2057_PAD2G_TUNE_PUS_CORE1, ~1, 0); } else { BWN_RF_SETMASK(mac, R2057_IPA5G_CASCOFFV_PU_CORE0, ~1, 0); BWN_RF_SETMASK(mac, R2057_IPA5G_CASCOFFV_PU_CORE1, ~1, 0); } } } } else { BWN_PHY_SETMASK(mac, BWN_NPHY_AFECTL_C1, 0x0FFF, 0xA000); BWN_PHY_SETMASK(mac, BWN_NPHY_AFECTL_C2, 0x0FFF, 0xA000); tmp = BWN_PHY_READ(mac, BWN_NPHY_AFECTL_OVER); regs[2] = tmp; BWN_PHY_WRITE(mac, BWN_NPHY_AFECTL_OVER, tmp | 0x3000); tmp = bwn_ntab_read(mac, BWN_NTAB16(8, 2)); regs[3] = tmp; tmp |= 0x2000; bwn_ntab_write(mac, BWN_NTAB16(8, 2), tmp); tmp = bwn_ntab_read(mac, BWN_NTAB16(8, 18)); regs[4] = tmp; tmp |= 0x2000; bwn_ntab_write(mac, BWN_NTAB16(8, 18), tmp); regs[5] = BWN_PHY_READ(mac, BWN_NPHY_RFCTL_INTC1); regs[6] = BWN_PHY_READ(mac, BWN_NPHY_RFCTL_INTC2); if (bwn_current_band(mac) == BWN_BAND_5G) tmp = 0x0180; else tmp = 0x0120; BWN_PHY_WRITE(mac, BWN_NPHY_RFCTL_INTC1, tmp); BWN_PHY_WRITE(mac, BWN_NPHY_RFCTL_INTC2, tmp); } } /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/SaveCal */ static void bwn_nphy_save_cal(struct bwn_mac *mac) { struct bwn_phy *phy = &mac->mac_phy; struct bwn_phy_n *nphy = mac->mac_phy.phy_n; struct bwn_phy_n_iq_comp *rxcal_coeffs = NULL; uint16_t *txcal_radio_regs = NULL; struct bwn_chanspec *iqcal_chanspec; uint16_t *table = NULL; if (nphy->hang_avoid) bwn_nphy_stay_in_carrier_search(mac, 1); if (bwn_current_band(mac) == BWN_BAND_2G) { rxcal_coeffs = &nphy->cal_cache.rxcal_coeffs_2G; txcal_radio_regs = nphy->cal_cache.txcal_radio_regs_2G; iqcal_chanspec = &nphy->iqcal_chanspec_2G; table = nphy->cal_cache.txcal_coeffs_2G; } else { rxcal_coeffs = &nphy->cal_cache.rxcal_coeffs_5G; txcal_radio_regs = nphy->cal_cache.txcal_radio_regs_5G; iqcal_chanspec = &nphy->iqcal_chanspec_5G; table = nphy->cal_cache.txcal_coeffs_5G; } bwn_nphy_rx_iq_coeffs(mac, false, rxcal_coeffs); /* TODO use some definitions */ if (phy->rev >= 19) { /* TODO */ } else if (phy->rev >= 7) { txcal_radio_regs[0] = BWN_RF_READ(mac, R2057_TX0_LOFT_FINE_I); txcal_radio_regs[1] = BWN_RF_READ(mac, R2057_TX0_LOFT_FINE_Q); txcal_radio_regs[4] = BWN_RF_READ(mac, R2057_TX0_LOFT_COARSE_I); txcal_radio_regs[5] = BWN_RF_READ(mac, R2057_TX0_LOFT_COARSE_Q); txcal_radio_regs[2] = BWN_RF_READ(mac, R2057_TX1_LOFT_FINE_I); txcal_radio_regs[3] = BWN_RF_READ(mac, R2057_TX1_LOFT_FINE_Q); txcal_radio_regs[6] = BWN_RF_READ(mac, R2057_TX1_LOFT_COARSE_I); txcal_radio_regs[7] = BWN_RF_READ(mac, R2057_TX1_LOFT_COARSE_Q); } else if (phy->rev >= 3) { txcal_radio_regs[0] = BWN_RF_READ(mac, 0x2021); txcal_radio_regs[1] = BWN_RF_READ(mac, 0x2022); txcal_radio_regs[2] = BWN_RF_READ(mac, 0x3021); txcal_radio_regs[3] = BWN_RF_READ(mac, 0x3022); txcal_radio_regs[4] = BWN_RF_READ(mac, 0x2023); txcal_radio_regs[5] = BWN_RF_READ(mac, 0x2024); txcal_radio_regs[6] = BWN_RF_READ(mac, 0x3023); txcal_radio_regs[7] = BWN_RF_READ(mac, 0x3024); } else { txcal_radio_regs[0] = BWN_RF_READ(mac, 0x8B); txcal_radio_regs[1] = BWN_RF_READ(mac, 0xBA); txcal_radio_regs[2] = BWN_RF_READ(mac, 0x8D); txcal_radio_regs[3] = BWN_RF_READ(mac, 0xBC); } iqcal_chanspec->center_freq = bwn_get_centre_freq(mac); iqcal_chanspec->channel_type = bwn_get_chan_type(mac, NULL); bwn_ntab_read_bulk(mac, BWN_NTAB16(15, 80), 8, table); if (nphy->hang_avoid) bwn_nphy_stay_in_carrier_search(mac, 0); } /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RestoreCal */ static void bwn_nphy_restore_cal(struct bwn_mac *mac) { struct bwn_phy *phy = &mac->mac_phy; struct bwn_phy_n *nphy = mac->mac_phy.phy_n; uint16_t coef[4]; uint16_t *loft = NULL; uint16_t *table = NULL; int i; uint16_t *txcal_radio_regs = NULL; struct bwn_phy_n_iq_comp *rxcal_coeffs = NULL; if (bwn_current_band(mac) == BWN_BAND_2G) { if (!nphy->iqcal_chanspec_2G.center_freq) return; table = nphy->cal_cache.txcal_coeffs_2G; loft = &nphy->cal_cache.txcal_coeffs_2G[5]; } else { if (!nphy->iqcal_chanspec_5G.center_freq) return; table = nphy->cal_cache.txcal_coeffs_5G; loft = &nphy->cal_cache.txcal_coeffs_5G[5]; } bwn_ntab_write_bulk(mac, BWN_NTAB16(15, 80), 4, table); for (i = 0; i < 4; i++) { if (mac->mac_phy.rev >= 3) table[i] = coef[i]; else coef[i] = 0; } bwn_ntab_write_bulk(mac, BWN_NTAB16(15, 88), 4, coef); bwn_ntab_write_bulk(mac, BWN_NTAB16(15, 85), 2, loft); bwn_ntab_write_bulk(mac, BWN_NTAB16(15, 93), 2, loft); if (mac->mac_phy.rev < 2) bwn_nphy_tx_iq_workaround(mac); if (bwn_current_band(mac) == BWN_BAND_2G) { txcal_radio_regs = nphy->cal_cache.txcal_radio_regs_2G; rxcal_coeffs = &nphy->cal_cache.rxcal_coeffs_2G; } else { txcal_radio_regs = nphy->cal_cache.txcal_radio_regs_5G; rxcal_coeffs = &nphy->cal_cache.rxcal_coeffs_5G; } /* TODO use some definitions */ if (phy->rev >= 19) { /* TODO */ } else if (phy->rev >= 7) { BWN_RF_WRITE(mac, R2057_TX0_LOFT_FINE_I, txcal_radio_regs[0]); BWN_RF_WRITE(mac, R2057_TX0_LOFT_FINE_Q, txcal_radio_regs[1]); BWN_RF_WRITE(mac, R2057_TX0_LOFT_COARSE_I, txcal_radio_regs[4]); BWN_RF_WRITE(mac, R2057_TX0_LOFT_COARSE_Q, txcal_radio_regs[5]); BWN_RF_WRITE(mac, R2057_TX1_LOFT_FINE_I, txcal_radio_regs[2]); BWN_RF_WRITE(mac, R2057_TX1_LOFT_FINE_Q, txcal_radio_regs[3]); BWN_RF_WRITE(mac, R2057_TX1_LOFT_COARSE_I, txcal_radio_regs[6]); BWN_RF_WRITE(mac, R2057_TX1_LOFT_COARSE_Q, txcal_radio_regs[7]); } else if (phy->rev >= 3) { BWN_RF_WRITE(mac, 0x2021, txcal_radio_regs[0]); BWN_RF_WRITE(mac, 0x2022, txcal_radio_regs[1]); BWN_RF_WRITE(mac, 0x3021, txcal_radio_regs[2]); BWN_RF_WRITE(mac, 0x3022, txcal_radio_regs[3]); BWN_RF_WRITE(mac, 0x2023, txcal_radio_regs[4]); BWN_RF_WRITE(mac, 0x2024, txcal_radio_regs[5]); BWN_RF_WRITE(mac, 0x3023, txcal_radio_regs[6]); BWN_RF_WRITE(mac, 0x3024, txcal_radio_regs[7]); } else { BWN_RF_WRITE(mac, 0x8B, txcal_radio_regs[0]); BWN_RF_WRITE(mac, 0xBA, txcal_radio_regs[1]); BWN_RF_WRITE(mac, 0x8D, txcal_radio_regs[2]); BWN_RF_WRITE(mac, 0xBC, txcal_radio_regs[3]); } bwn_nphy_rx_iq_coeffs(mac, true, rxcal_coeffs); } /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/CalTxIqlo */ static int bwn_nphy_cal_tx_iq_lo(struct bwn_mac *mac, struct bwn_nphy_txgains target, bool full, bool mphase) { struct bwn_phy *phy = &mac->mac_phy; struct bwn_phy_n *nphy = mac->mac_phy.phy_n; int i; int error = 0; int freq; bool avoid = false; uint8_t length; uint16_t tmp, core, type, count, max, numb, last = 0, cmd; const uint16_t *table; bool phy6or5x; uint16_t buffer[11]; uint16_t diq_start = 0; uint16_t save[2]; uint16_t gain[2]; struct bwn_nphy_iqcal_params params[2]; bool updated[2] = { }; bwn_nphy_stay_in_carrier_search(mac, true); if (mac->mac_phy.rev >= 4) { avoid = nphy->hang_avoid; nphy->hang_avoid = false; } bwn_ntab_read_bulk(mac, BWN_NTAB16(7, 0x110), 2, save); for (i = 0; i < 2; i++) { bwn_nphy_iq_cal_gain_params(mac, i, target, ¶ms[i]); gain[i] = params[i].cal_gain; } bwn_ntab_write_bulk(mac, BWN_NTAB16(7, 0x110), 2, gain); bwn_nphy_tx_cal_radio_setup(mac); bwn_nphy_tx_cal_phy_setup(mac); phy6or5x = mac->mac_phy.rev >= 6 || (mac->mac_phy.rev == 5 && nphy->ipa2g_on && bwn_current_band(mac) == BWN_BAND_2G); if (phy6or5x) { if (bwn_is_40mhz(mac)) { bwn_ntab_write_bulk(mac, BWN_NTAB16(15, 0), 18, tbl_tx_iqlo_cal_loft_ladder_40); bwn_ntab_write_bulk(mac, BWN_NTAB16(15, 32), 18, tbl_tx_iqlo_cal_iqimb_ladder_40); } else { bwn_ntab_write_bulk(mac, BWN_NTAB16(15, 0), 18, tbl_tx_iqlo_cal_loft_ladder_20); bwn_ntab_write_bulk(mac, BWN_NTAB16(15, 32), 18, tbl_tx_iqlo_cal_iqimb_ladder_20); } } if (phy->rev >= 19) { /* TODO */ } else if (phy->rev >= 7) { BWN_PHY_WRITE(mac, BWN_NPHY_IQLOCAL_CMDGCTL, 0x8AD9); } else { BWN_PHY_WRITE(mac, BWN_NPHY_IQLOCAL_CMDGCTL, 0x8AA9); } if (!bwn_is_40mhz(mac)) freq = 2500; else freq = 5000; if (nphy->mphase_cal_phase_id > 2) bwn_nphy_run_samples(mac, (bwn_is_40mhz(mac) ? 40 : 20) * 8, 0xFFFF, 0, true, false, false); else error = bwn_nphy_tx_tone(mac, freq, 250, true, false, false); if (error == 0) { if (nphy->mphase_cal_phase_id > 2) { table = nphy->mphase_txcal_bestcoeffs; length = 11; if (mac->mac_phy.rev < 3) length -= 2; } else { if (!full && nphy->txiqlocal_coeffsvalid) { table = nphy->txiqlocal_bestc; length = 11; if (mac->mac_phy.rev < 3) length -= 2; } else { full = true; if (mac->mac_phy.rev >= 3) { table = tbl_tx_iqlo_cal_startcoefs_nphyrev3; length = BWN_NTAB_TX_IQLO_CAL_STARTCOEFS_REV3; } else { table = tbl_tx_iqlo_cal_startcoefs; length = BWN_NTAB_TX_IQLO_CAL_STARTCOEFS; } } } bwn_ntab_write_bulk(mac, BWN_NTAB16(15, 64), length, table); if (full) { if (mac->mac_phy.rev >= 3) max = BWN_NTAB_TX_IQLO_CAL_CMDS_FULLCAL_REV3; else max = BWN_NTAB_TX_IQLO_CAL_CMDS_FULLCAL; } else { if (mac->mac_phy.rev >= 3) max = BWN_NTAB_TX_IQLO_CAL_CMDS_RECAL_REV3; else max = BWN_NTAB_TX_IQLO_CAL_CMDS_RECAL; } if (mphase) { count = nphy->mphase_txcal_cmdidx; numb = min(max, (uint16_t)(count + nphy->mphase_txcal_numcmds)); } else { count = 0; numb = max; } for (; count < numb; count++) { if (full) { if (mac->mac_phy.rev >= 3) cmd = tbl_tx_iqlo_cal_cmds_fullcal_nphyrev3[count]; else cmd = tbl_tx_iqlo_cal_cmds_fullcal[count]; } else { if (mac->mac_phy.rev >= 3) cmd = tbl_tx_iqlo_cal_cmds_recal_nphyrev3[count]; else cmd = tbl_tx_iqlo_cal_cmds_recal[count]; } core = (cmd & 0x3000) >> 12; type = (cmd & 0x0F00) >> 8; if (phy6or5x && updated[core] == 0) { bwn_nphy_update_tx_cal_ladder(mac, core); updated[core] = true; } tmp = (params[core].ncorr[type] << 8) | 0x66; BWN_PHY_WRITE(mac, BWN_NPHY_IQLOCAL_CMDNNUM, tmp); if (type == 1 || type == 3 || type == 4) { buffer[0] = bwn_ntab_read(mac, BWN_NTAB16(15, 69 + core)); diq_start = buffer[0]; buffer[0] = 0; bwn_ntab_write(mac, BWN_NTAB16(15, 69 + core), 0); } BWN_PHY_WRITE(mac, BWN_NPHY_IQLOCAL_CMD, cmd); for (i = 0; i < 2000; i++) { tmp = BWN_PHY_READ(mac, BWN_NPHY_IQLOCAL_CMD); if (tmp & 0xC000) break; DELAY(10); } bwn_ntab_read_bulk(mac, BWN_NTAB16(15, 96), length, buffer); bwn_ntab_write_bulk(mac, BWN_NTAB16(15, 64), length, buffer); if (type == 1 || type == 3 || type == 4) buffer[0] = diq_start; } if (mphase) nphy->mphase_txcal_cmdidx = (numb >= max) ? 0 : numb; last = (mac->mac_phy.rev < 3) ? 6 : 7; if (!mphase || nphy->mphase_cal_phase_id == last) { bwn_ntab_write_bulk(mac, BWN_NTAB16(15, 96), 4, buffer); bwn_ntab_read_bulk(mac, BWN_NTAB16(15, 80), 4, buffer); if (mac->mac_phy.rev < 3) { buffer[0] = 0; buffer[1] = 0; buffer[2] = 0; buffer[3] = 0; } bwn_ntab_write_bulk(mac, BWN_NTAB16(15, 88), 4, buffer); bwn_ntab_read_bulk(mac, BWN_NTAB16(15, 101), 2, buffer); bwn_ntab_write_bulk(mac, BWN_NTAB16(15, 85), 2, buffer); bwn_ntab_write_bulk(mac, BWN_NTAB16(15, 93), 2, buffer); length = 11; if (mac->mac_phy.rev < 3) length -= 2; bwn_ntab_read_bulk(mac, BWN_NTAB16(15, 96), length, nphy->txiqlocal_bestc); nphy->txiqlocal_coeffsvalid = true; nphy->txiqlocal_chanspec.center_freq = bwn_get_centre_freq(mac); nphy->txiqlocal_chanspec.channel_type = bwn_get_chan_type(mac, NULL); } else { length = 11; if (mac->mac_phy.rev < 3) length -= 2; bwn_ntab_read_bulk(mac, BWN_NTAB16(15, 96), length, nphy->mphase_txcal_bestcoeffs); } bwn_nphy_stop_playback(mac); BWN_PHY_WRITE(mac, BWN_NPHY_IQLOCAL_CMDGCTL, 0); } bwn_nphy_tx_cal_phy_cleanup(mac); bwn_ntab_write_bulk(mac, BWN_NTAB16(7, 0x110), 2, save); if (mac->mac_phy.rev < 2 && (!mphase || nphy->mphase_cal_phase_id == last)) bwn_nphy_tx_iq_workaround(mac); if (mac->mac_phy.rev >= 4) nphy->hang_avoid = avoid; bwn_nphy_stay_in_carrier_search(mac, false); return error; } /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/ReapplyTxCalCoeffs */ static void bwn_nphy_reapply_tx_cal_coeffs(struct bwn_mac *mac) { struct bwn_phy_n *nphy = mac->mac_phy.phy_n; uint8_t i; uint16_t buffer[7]; bool equal = true; if (!nphy->txiqlocal_coeffsvalid || nphy->txiqlocal_chanspec.center_freq != bwn_get_centre_freq(mac) || nphy->txiqlocal_chanspec.channel_type != bwn_get_chan_type(mac, NULL)) return; bwn_ntab_read_bulk(mac, BWN_NTAB16(15, 80), 7, buffer); for (i = 0; i < 4; i++) { if (buffer[i] != nphy->txiqlocal_bestc[i]) { equal = false; break; } } if (!equal) { bwn_ntab_write_bulk(mac, BWN_NTAB16(15, 80), 4, nphy->txiqlocal_bestc); for (i = 0; i < 4; i++) buffer[i] = 0; bwn_ntab_write_bulk(mac, BWN_NTAB16(15, 88), 4, buffer); bwn_ntab_write_bulk(mac, BWN_NTAB16(15, 85), 2, &nphy->txiqlocal_bestc[5]); bwn_ntab_write_bulk(mac, BWN_NTAB16(15, 93), 2, &nphy->txiqlocal_bestc[5]); } } /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/CalRxIqRev2 */ static int bwn_nphy_rev2_cal_rx_iq(struct bwn_mac *mac, struct bwn_nphy_txgains target, uint8_t type, bool debug) { struct bwn_phy_n *nphy = mac->mac_phy.phy_n; int i, j, index; uint8_t rfctl[2]; uint8_t afectl_core; uint16_t tmp[6]; uint16_t cur_hpf1, cur_hpf2, cur_lna; uint32_t real, imag; bwn_band_t band; uint8_t use; uint16_t cur_hpf; uint16_t lna[3] = { 3, 3, 1 }; uint16_t hpf1[3] = { 7, 2, 0 }; uint16_t hpf2[3] = { 2, 0, 0 }; uint32_t power[3] = { }; uint16_t gain_save[2]; uint16_t cal_gain[2]; struct bwn_nphy_iqcal_params cal_params[2]; struct bwn_nphy_iq_est est; int ret = 0; bool playtone = true; int desired = 13; bwn_nphy_stay_in_carrier_search(mac, 1); if (mac->mac_phy.rev < 2) bwn_nphy_reapply_tx_cal_coeffs(mac); bwn_ntab_read_bulk(mac, BWN_NTAB16(7, 0x110), 2, gain_save); for (i = 0; i < 2; i++) { bwn_nphy_iq_cal_gain_params(mac, i, target, &cal_params[i]); cal_gain[i] = cal_params[i].cal_gain; } bwn_ntab_write_bulk(mac, BWN_NTAB16(7, 0x110), 2, cal_gain); for (i = 0; i < 2; i++) { if (i == 0) { rfctl[0] = BWN_NPHY_RFCTL_INTC1; rfctl[1] = BWN_NPHY_RFCTL_INTC2; afectl_core = BWN_NPHY_AFECTL_C1; } else { rfctl[0] = BWN_NPHY_RFCTL_INTC2; rfctl[1] = BWN_NPHY_RFCTL_INTC1; afectl_core = BWN_NPHY_AFECTL_C2; } tmp[1] = BWN_PHY_READ(mac, BWN_NPHY_RFSEQCA); tmp[2] = BWN_PHY_READ(mac, afectl_core); tmp[3] = BWN_PHY_READ(mac, BWN_NPHY_AFECTL_OVER); tmp[4] = BWN_PHY_READ(mac, rfctl[0]); tmp[5] = BWN_PHY_READ(mac, rfctl[1]); BWN_PHY_SETMASK(mac, BWN_NPHY_RFSEQCA, ~BWN_NPHY_RFSEQCA_RXDIS & 0xFFFF, ((1 - i) << BWN_NPHY_RFSEQCA_RXDIS_SHIFT)); BWN_PHY_SETMASK(mac, BWN_NPHY_RFSEQCA, ~BWN_NPHY_RFSEQCA_TXEN, (1 - i)); BWN_PHY_SET(mac, afectl_core, 0x0006); BWN_PHY_SET(mac, BWN_NPHY_AFECTL_OVER, 0x0006); band = bwn_current_band(mac); if (nphy->rxcalparams & 0xFF000000) { if (band == BWN_BAND_5G) BWN_PHY_WRITE(mac, rfctl[0], 0x140); else BWN_PHY_WRITE(mac, rfctl[0], 0x110); } else { if (band == BWN_BAND_5G) BWN_PHY_WRITE(mac, rfctl[0], 0x180); else BWN_PHY_WRITE(mac, rfctl[0], 0x120); } if (band == BWN_BAND_5G) BWN_PHY_WRITE(mac, rfctl[1], 0x148); else BWN_PHY_WRITE(mac, rfctl[1], 0x114); if (nphy->rxcalparams & 0x10000) { BWN_RF_SETMASK(mac, B2055_C1_GENSPARE2, 0xFC, (i + 1)); BWN_RF_SETMASK(mac, B2055_C2_GENSPARE2, 0xFC, (2 - i)); } for (j = 0; j < 4; j++) { if (j < 3) { cur_lna = lna[j]; cur_hpf1 = hpf1[j]; cur_hpf2 = hpf2[j]; } else { if (power[1] > 10000) { use = 1; cur_hpf = cur_hpf1; index = 2; } else { if (power[0] > 10000) { use = 1; cur_hpf = cur_hpf1; index = 1; } else { index = 0; use = 2; cur_hpf = cur_hpf2; } } cur_lna = lna[index]; cur_hpf1 = hpf1[index]; cur_hpf2 = hpf2[index]; cur_hpf += desired - bwn_hweight32(power[index]); cur_hpf = bwn_clamp_val(cur_hpf, 0, 10); if (use == 1) cur_hpf1 = cur_hpf; else cur_hpf2 = cur_hpf; } tmp[0] = ((cur_hpf2 << 8) | (cur_hpf1 << 4) | (cur_lna << 2)); bwn_nphy_rf_ctl_override(mac, 0x400, tmp[0], 3, false); bwn_nphy_force_rf_sequence(mac, BWN_RFSEQ_RESET2RX); bwn_nphy_stop_playback(mac); if (playtone) { ret = bwn_nphy_tx_tone(mac, 4000, (nphy->rxcalparams & 0xFFFF), false, false, true); playtone = false; } else { bwn_nphy_run_samples(mac, 160, 0xFFFF, 0, false, false, true); } if (ret == 0) { if (j < 3) { bwn_nphy_rx_iq_est(mac, &est, 1024, 32, false); if (i == 0) { real = est.i0_pwr; imag = est.q0_pwr; } else { real = est.i1_pwr; imag = est.q1_pwr; } power[i] = ((real + imag) / 1024) + 1; } else { bwn_nphy_calc_rx_iq_comp(mac, 1 << i); } bwn_nphy_stop_playback(mac); } if (ret != 0) break; } BWN_RF_MASK(mac, B2055_C1_GENSPARE2, 0xFC); BWN_RF_MASK(mac, B2055_C2_GENSPARE2, 0xFC); BWN_PHY_WRITE(mac, rfctl[1], tmp[5]); BWN_PHY_WRITE(mac, rfctl[0], tmp[4]); BWN_PHY_WRITE(mac, BWN_NPHY_AFECTL_OVER, tmp[3]); BWN_PHY_WRITE(mac, afectl_core, tmp[2]); BWN_PHY_WRITE(mac, BWN_NPHY_RFSEQCA, tmp[1]); if (ret != 0) break; } bwn_nphy_rf_ctl_override(mac, 0x400, 0, 3, true); bwn_nphy_force_rf_sequence(mac, BWN_RFSEQ_RESET2RX); bwn_ntab_write_bulk(mac, BWN_NTAB16(7, 0x110), 2, gain_save); bwn_nphy_stay_in_carrier_search(mac, 0); return ret; } static int bwn_nphy_rev3_cal_rx_iq(struct bwn_mac *mac, struct bwn_nphy_txgains target, uint8_t type, bool debug) { return -1; } /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/CalRxIq */ static int bwn_nphy_cal_rx_iq(struct bwn_mac *mac, struct bwn_nphy_txgains target, uint8_t type, bool debug) { if (mac->mac_phy.rev >= 7) type = 0; if (mac->mac_phy.rev >= 3) return bwn_nphy_rev3_cal_rx_iq(mac, target, type, debug); else return bwn_nphy_rev2_cal_rx_iq(mac, target, type, debug); } /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RxCoreSetState */ static void bwn_nphy_set_rx_core_state(struct bwn_mac *mac, uint8_t mask) { struct bwn_phy *phy = &mac->mac_phy; struct bwn_phy_n *nphy = phy->phy_n; /* uint16_t buf[16]; it's rev3+ */ nphy->phyrxchain = mask; if (0 /* FIXME clk */) return; bwn_mac_suspend(mac); if (nphy->hang_avoid) bwn_nphy_stay_in_carrier_search(mac, true); BWN_PHY_SETMASK(mac, BWN_NPHY_RFSEQCA, ~BWN_NPHY_RFSEQCA_RXEN, (mask & 0x3) << BWN_NPHY_RFSEQCA_RXEN_SHIFT); if ((mask & 0x3) != 0x3) { BWN_PHY_WRITE(mac, BWN_NPHY_HPANT_SWTHRES, 1); if (mac->mac_phy.rev >= 3) { /* TODO */ } } else { BWN_PHY_WRITE(mac, BWN_NPHY_HPANT_SWTHRES, 0x1E); if (mac->mac_phy.rev >= 3) { /* TODO */ } } bwn_nphy_force_rf_sequence(mac, BWN_RFSEQ_RESET2RX); if (nphy->hang_avoid) bwn_nphy_stay_in_carrier_search(mac, false); bwn_mac_enable(mac); } bwn_txpwr_result_t bwn_nphy_op_recalc_txpower(struct bwn_mac *mac, bool ignore_tssi) { struct bwn_phy *phy = &mac->mac_phy; struct bwn_phy_n *nphy = mac->mac_phy.phy_n; struct ieee80211_channel *channel = bwn_get_channel(mac); struct bwn_softc *sc = mac->mac_sc; struct bwn_ppr *ppr = &nphy->tx_pwr_max_ppr; uint8_t max; /* qdBm */ bool tx_pwr_state; if (nphy->tx_pwr_last_recalc_freq == bwn_get_centre_freq(mac) && nphy->tx_pwr_last_recalc_limit == phy->txpower) return BWN_TXPWR_RES_DONE; /* Make sure we have a clean PPR */ bwn_ppr_clear(mac, ppr); /* HW limitations */ bwn_ppr_load_max_from_sprom(mac, ppr, BWN_PHY_BAND_2G); /* XXX TODO: other bands? */ /* Regulatory & user settings */ max = INT_TO_Q52(bwn_get_chan_power(mac, channel)); /* uint8_t */ if (phy->txpower) max = min(max, INT_TO_Q52(phy->txpower)); bwn_ppr_apply_max(mac, ppr, max); DPRINTF(mac->mac_sc, BWN_DEBUG_XMIT_POWER, "Calculated TX power: " Q52_FMT "\n", Q52_ARG(bwn_ppr_get_max(mac, ppr))); /* TODO: Enable this once we get gains working */ #if 0 /* Some extra gains */ hw_gain = 6; /* N-PHY specific */ if (bwn_current_band(mac) == BWN_BAND_2G) hw_gain += sprom->antenna_gain.a0; else hw_gain += sprom->antenna_gain.a1; bwn_ppr_add(mac, ppr, -hw_gain); #endif /* Make sure we didn't go too low */ bwn_ppr_apply_min(mac, ppr, INT_TO_Q52(8)); /* Apply */ tx_pwr_state = nphy->txpwrctrl; bwn_mac_suspend(mac); bwn_nphy_tx_power_ctl_setup(mac); - if (siba_get_revid(sc->sc_dev) == 11 || siba_get_revid(sc->sc_dev) == 12) { + if (bhnd_get_hwrev(sc->sc_dev) == 11 || bhnd_get_hwrev(sc->sc_dev) == 12) { BWN_WRITE_SETMASK4(mac, BWN_MACCTL, ~0, BWN_MACCTL_PHY_LOCK); BWN_READ_4(mac, BWN_MACCTL); DELAY(1); } bwn_nphy_tx_power_ctrl(mac, nphy->txpwrctrl); - if (siba_get_revid(sc->sc_dev) == 11 || siba_get_revid(sc->sc_dev) == 12) + if (bhnd_get_hwrev(sc->sc_dev) == 11 || bhnd_get_hwrev(sc->sc_dev) == 12) BWN_WRITE_SETMASK4(mac, BWN_MACCTL, ~BWN_MACCTL_PHY_LOCK, 0); bwn_mac_enable(mac); nphy->tx_pwr_last_recalc_freq = bwn_get_centre_freq(mac); nphy->tx_pwr_last_recalc_limit = phy->txpower; return BWN_TXPWR_RES_DONE; } /************************************************** * N-PHY init **************************************************/ /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/MIMOConfig */ static void bwn_nphy_update_mimo_config(struct bwn_mac *mac, int32_t preamble) { uint16_t mimocfg = BWN_PHY_READ(mac, BWN_NPHY_MIMOCFG); mimocfg |= BWN_NPHY_MIMOCFG_AUTO; if (preamble == 1) mimocfg |= BWN_NPHY_MIMOCFG_GFMIX; else mimocfg &= ~BWN_NPHY_MIMOCFG_GFMIX; BWN_PHY_WRITE(mac, BWN_NPHY_MIMOCFG, mimocfg); } /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/BPHYInit */ static void bwn_nphy_bphy_init(struct bwn_mac *mac) { unsigned int i; uint16_t val; val = 0x1E1F; for (i = 0; i < 16; i++) { BWN_PHY_WRITE(mac, BWN_PHY_N_BMODE(0x88 + i), val); val -= 0x202; } val = 0x3E3F; for (i = 0; i < 16; i++) { BWN_PHY_WRITE(mac, BWN_PHY_N_BMODE(0x98 + i), val); val -= 0x202; } BWN_PHY_WRITE(mac, BWN_PHY_N_BMODE(0x38), 0x668); } /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/SuperSwitchInit */ -static void bwn_nphy_superswitch_init(struct bwn_mac *mac, bool init) +static int bwn_nphy_superswitch_init(struct bwn_mac *mac, bool init) { - struct bwn_softc *sc = mac->mac_sc; + int error; if (mac->mac_phy.rev >= 7) - return; + return (0); if (mac->mac_phy.rev >= 3) { if (!init) - return; + return (0); if (0 /* FIXME */) { bwn_ntab_write(mac, BWN_NTAB16(9, 2), 0x211); bwn_ntab_write(mac, BWN_NTAB16(9, 3), 0x222); bwn_ntab_write(mac, BWN_NTAB16(9, 8), 0x144); bwn_ntab_write(mac, BWN_NTAB16(9, 12), 0x188); } } else { BWN_PHY_WRITE(mac, BWN_NPHY_GPIO_LOOEN, 0); BWN_PHY_WRITE(mac, BWN_NPHY_GPIO_HIOEN, 0); - siba_gpio_set(sc->sc_dev, 0xfc00); + if ((error = bwn_gpio_control(mac, 0xfc00))) + return (error); BWN_WRITE_SETMASK4(mac, BWN_MACCTL, ~BWN_MACCTL_GPOUT_MASK, 0); BWN_WRITE_SETMASK2(mac, BWN_GPIO_MASK, ~0, 0xFC00); BWN_WRITE_SETMASK2(mac, BWN_GPIO_CONTROL, (~0xFC00 & 0xFFFF), 0); if (init) { BWN_PHY_WRITE(mac, BWN_NPHY_RFCTL_LUT_TRSW_LO1, 0x2D8); BWN_PHY_WRITE(mac, BWN_NPHY_RFCTL_LUT_TRSW_UP1, 0x301); BWN_PHY_WRITE(mac, BWN_NPHY_RFCTL_LUT_TRSW_LO2, 0x2D8); BWN_PHY_WRITE(mac, BWN_NPHY_RFCTL_LUT_TRSW_UP2, 0x301); } } + + return (0); } /* http://bcm-v4.sipsolutions.net/802.11/PHY/Init/N */ static int bwn_phy_initn(struct bwn_mac *mac) { struct bwn_softc *sc = mac->mac_sc; struct bwn_phy *phy = &mac->mac_phy; struct bwn_phy_n *nphy = phy->phy_n; uint8_t tx_pwr_state; struct bwn_nphy_txgains target; + int error; uint16_t tmp; bwn_band_t tmp2; bool do_rssi_cal; uint16_t clip[2]; bool do_cal = false; + if (mac->mac_phy.rev >= 3) { + error = bhnd_nvram_getvar_uint8(sc->sc_dev, BHND_NVAR_TSSIPOS2G, + &nphy->tsspos_2g); + if (error) { + BWN_ERRPRINTF(mac->mac_sc, "Error reading %s from " + "NVRAM: %d\n", BHND_NVAR_TSSIPOS2G, error); + return (error); + } + } else { + nphy->tsspos_2g = 0; + } + if ((mac->mac_phy.rev >= 3) && - (siba_sprom_get_bf_lo(sc->sc_dev) & BWN_BFL_EXTLNA) && - (bwn_current_band(mac) == BWN_BAND_2G)) { - siba_cc_set32(sc->sc_dev, SIBA_CC_CHIPCTL, 0x40); + (sc->sc_board_info.board_flags & BHND_BFL_EXTLNA) && + (bwn_current_band(mac) == BWN_BAND_2G)) + { + BHND_CHIPC_WRITE_CHIPCTRL(sc->sc_chipc, 0x40, 0x40); } nphy->use_int_tx_iq_lo_cal = bwn_nphy_ipa(mac) || phy->rev >= 7 || (phy->rev >= 5 && - siba_sprom_get_bf2_hi(sc->sc_dev) & BWN_BFH2_INTERNDET_TXIQCAL); + sc->sc_board_info.board_flags2 & BHND_BFL2_INTERNDET_TXIQCAL); nphy->deaf_count = 0; bwn_nphy_tables_init(mac); nphy->crsminpwr_adjusted = false; nphy->noisevars_adjusted = false; /* Clear all overrides */ if (mac->mac_phy.rev >= 3) { BWN_PHY_WRITE(mac, BWN_NPHY_TXF_40CO_B1S1, 0); BWN_PHY_WRITE(mac, BWN_NPHY_RFCTL_OVER, 0); if (phy->rev >= 7) { BWN_PHY_WRITE(mac, BWN_NPHY_REV7_RF_CTL_OVER3, 0); BWN_PHY_WRITE(mac, BWN_NPHY_REV7_RF_CTL_OVER4, 0); BWN_PHY_WRITE(mac, BWN_NPHY_REV7_RF_CTL_OVER5, 0); BWN_PHY_WRITE(mac, BWN_NPHY_REV7_RF_CTL_OVER6, 0); } if (phy->rev >= 19) { /* TODO */ } BWN_PHY_WRITE(mac, BWN_NPHY_TXF_40CO_B1S0, 0); BWN_PHY_WRITE(mac, BWN_NPHY_TXF_40CO_B32S1, 0); } else { BWN_PHY_WRITE(mac, BWN_NPHY_RFCTL_OVER, 0); } BWN_PHY_WRITE(mac, BWN_NPHY_RFCTL_INTC1, 0); BWN_PHY_WRITE(mac, BWN_NPHY_RFCTL_INTC2, 0); if (mac->mac_phy.rev < 6) { BWN_PHY_WRITE(mac, BWN_NPHY_RFCTL_INTC3, 0); BWN_PHY_WRITE(mac, BWN_NPHY_RFCTL_INTC4, 0); } BWN_PHY_MASK(mac, BWN_NPHY_RFSEQMODE, ~(BWN_NPHY_RFSEQMODE_CAOVER | BWN_NPHY_RFSEQMODE_TROVER)); if (mac->mac_phy.rev >= 3) BWN_PHY_WRITE(mac, BWN_NPHY_AFECTL_OVER1, 0); BWN_PHY_WRITE(mac, BWN_NPHY_AFECTL_OVER, 0); if (mac->mac_phy.rev <= 2) { tmp = (mac->mac_phy.rev == 2) ? 0x3B : 0x40; BWN_PHY_SETMASK(mac, BWN_NPHY_BPHY_CTL3, ~BWN_NPHY_BPHY_CTL3_SCALE, tmp << BWN_NPHY_BPHY_CTL3_SCALE_SHIFT); } BWN_PHY_WRITE(mac, BWN_NPHY_AFESEQ_TX2RX_PUD_20M, 0x20); BWN_PHY_WRITE(mac, BWN_NPHY_AFESEQ_TX2RX_PUD_40M, 0x20); - if (siba_sprom_get_bf2_lo(sc->sc_dev) & BWN_BFL2_SKWRKFEM_BRD || - (siba_get_pci_subvendor(sc->sc_dev) == PCI_VENDOR_APPLE && - siba_get_pci_subdevice(sc->sc_dev) == BCMA_BOARD_TYPE_BCM943224M93)) + if (sc->sc_board_info.board_flags2 & BHND_BFL2_SKWRKFEM_BRD || + (sc->sc_board_info.board_vendor == PCI_VENDOR_APPLE && + sc->sc_board_info.board_type == BHND_BOARD_BCM943224M93)) BWN_PHY_WRITE(mac, BWN_NPHY_TXREALFD, 0xA0); else BWN_PHY_WRITE(mac, BWN_NPHY_TXREALFD, 0xB8); BWN_PHY_WRITE(mac, BWN_NPHY_MIMO_CRSTXEXT, 0xC8); BWN_PHY_WRITE(mac, BWN_NPHY_PLOAD_CSENSE_EXTLEN, 0x50); BWN_PHY_WRITE(mac, BWN_NPHY_TXRIFS_FRDEL, 0x30); if (phy->rev < 8) bwn_nphy_update_mimo_config(mac, nphy->preamble_override); bwn_nphy_update_txrx_chain(mac); if (phy->rev < 2) { BWN_PHY_WRITE(mac, BWN_NPHY_DUP40_GFBL, 0xAA8); BWN_PHY_WRITE(mac, BWN_NPHY_DUP40_BL, 0x9A4); } tmp2 = bwn_current_band(mac); if (bwn_nphy_ipa(mac)) { BWN_PHY_SET(mac, BWN_NPHY_PAPD_EN0, 0x1); BWN_PHY_SETMASK(mac, BWN_NPHY_EPS_TABLE_ADJ0, 0x007F, nphy->papd_epsilon_offset[0] << 7); BWN_PHY_SET(mac, BWN_NPHY_PAPD_EN1, 0x1); BWN_PHY_SETMASK(mac, BWN_NPHY_EPS_TABLE_ADJ1, 0x007F, nphy->papd_epsilon_offset[1] << 7); bwn_nphy_int_pa_set_tx_dig_filters(mac); } else if (phy->rev >= 5) { bwn_nphy_ext_pa_set_tx_dig_filters(mac); } - bwn_nphy_workarounds(mac); + if ((error = bwn_nphy_workarounds(mac))) + return (error); /* Reset CCA, in init code it differs a little from standard way */ bwn_phy_force_clock(mac, 1); tmp = BWN_PHY_READ(mac, BWN_NPHY_BBCFG); BWN_PHY_WRITE(mac, BWN_NPHY_BBCFG, tmp | BWN_NPHY_BBCFG_RSTCCA); BWN_PHY_WRITE(mac, BWN_NPHY_BBCFG, tmp & ~BWN_NPHY_BBCFG_RSTCCA); bwn_phy_force_clock(mac, 0); bwn_mac_phy_clock_set(mac, true); if (phy->rev < 7) { bwn_nphy_pa_override(mac, false); bwn_nphy_force_rf_sequence(mac, BWN_RFSEQ_RX2TX); bwn_nphy_force_rf_sequence(mac, BWN_RFSEQ_RESET2RX); bwn_nphy_pa_override(mac, true); } bwn_nphy_classifier(mac, 0, 0); bwn_nphy_read_clip_detection(mac, clip); if (bwn_current_band(mac) == BWN_BAND_2G) bwn_nphy_bphy_init(mac); tx_pwr_state = nphy->txpwrctrl; bwn_nphy_tx_power_ctrl(mac, false); - bwn_nphy_tx_power_fix(mac); + if ((error = bwn_nphy_tx_power_fix(mac))) + return (error); bwn_nphy_tx_power_ctl_idle_tssi(mac); bwn_nphy_tx_power_ctl_setup(mac); bwn_nphy_tx_gain_table_upload(mac); if (nphy->phyrxchain != 3) bwn_nphy_set_rx_core_state(mac, nphy->phyrxchain); if (nphy->mphase_cal_phase_id > 0) ;/* TODO PHY Periodic Calibration Multi-Phase Restart */ do_rssi_cal = false; if (phy->rev >= 3) { if (bwn_current_band(mac) == BWN_BAND_2G) do_rssi_cal = !nphy->rssical_chanspec_2G.center_freq; else do_rssi_cal = !nphy->rssical_chanspec_5G.center_freq; if (do_rssi_cal) bwn_nphy_rssi_cal(mac); else bwn_nphy_restore_rssi_cal(mac); } else { bwn_nphy_rssi_cal(mac); } if (!((nphy->measure_hold & 0x6) != 0)) { if (bwn_current_band(mac) == BWN_BAND_2G) do_cal = !nphy->iqcal_chanspec_2G.center_freq; else do_cal = !nphy->iqcal_chanspec_5G.center_freq; if (nphy->mute) do_cal = false; if (do_cal) { target = bwn_nphy_get_tx_gains(mac); - if (nphy->antsel_type == 2) - bwn_nphy_superswitch_init(mac, true); + if (nphy->antsel_type == 2) { + error = bwn_nphy_superswitch_init(mac, true); + if (error) + return (error); + } if (nphy->perical != 2) { bwn_nphy_rssi_cal(mac); if (phy->rev >= 3) { nphy->cal_orig_pwr_idx[0] = nphy->txpwrindex[0].index_internal; nphy->cal_orig_pwr_idx[1] = nphy->txpwrindex[1].index_internal; /* TODO N PHY Pre Calibrate TX Gain */ target = bwn_nphy_get_tx_gains(mac); } if (!bwn_nphy_cal_tx_iq_lo(mac, target, true, false)) if (bwn_nphy_cal_rx_iq(mac, target, 2, 0) == 0) bwn_nphy_save_cal(mac); } else if (nphy->mphase_cal_phase_id == 0) ;/* N PHY Periodic Calibration with arg 3 */ } else { bwn_nphy_restore_cal(mac); } } bwn_nphy_tx_pwr_ctrl_coef_setup(mac); bwn_nphy_tx_power_ctrl(mac, tx_pwr_state); BWN_PHY_WRITE(mac, BWN_NPHY_TXMACIF_HOLDOFF, 0x0015); BWN_PHY_WRITE(mac, BWN_NPHY_TXMACDELAY, 0x0320); if (phy->rev >= 3 && phy->rev <= 6) BWN_PHY_WRITE(mac, BWN_NPHY_PLOAD_CSENSE_EXTLEN, 0x0032); bwn_nphy_tx_lpf_bw(mac); if (phy->rev >= 3) bwn_nphy_spur_workaround(mac); return 0; } /************************************************** * Channel switching ops. **************************************************/ static void bwn_chantab_phy_upload(struct bwn_mac *mac, const struct bwn_phy_n_sfo_cfg *e) { BWN_PHY_WRITE(mac, BWN_NPHY_BW1A, e->phy_bw1a); BWN_PHY_WRITE(mac, BWN_NPHY_BW2, e->phy_bw2); BWN_PHY_WRITE(mac, BWN_NPHY_BW3, e->phy_bw3); BWN_PHY_WRITE(mac, BWN_NPHY_BW4, e->phy_bw4); BWN_PHY_WRITE(mac, BWN_NPHY_BW5, e->phy_bw5); BWN_PHY_WRITE(mac, BWN_NPHY_BW6, e->phy_bw6); } /* http://bcm-v4.sipsolutions.net/802.11/PmuSpurAvoid */ -static void bwn_nphy_pmu_spur_avoid(struct bwn_mac *mac, bool avoid) +static void bwn_nphy_pmu_spur_avoid(struct bwn_mac *mac, + bhnd_pmu_spuravoid mode) { struct bwn_softc *sc = mac->mac_sc; + int error; - DPRINTF(sc, BWN_DEBUG_RESET, "%s: spuravoid %d\n", __func__, avoid); - siba_pmu_spuravoid_pllupdate(sc->sc_dev, avoid); + DPRINTF(sc, BWN_DEBUG_RESET, "%s: spuravoid %d\n", __func__, mode); + + if (sc->sc_pmu == NULL) { + BWN_ERRPRINTF(mac->mac_sc, "no PMU; cannot configure spurious " + "signal avoidance\n"); + return; + } + + if ((error = bhnd_pmu_request_spuravoid(sc->sc_pmu, mode))) { + device_printf(sc->sc_dev, "spuravoid request failed: %d", + error); + } } /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/ChanspecSetup */ -static void bwn_nphy_channel_setup(struct bwn_mac *mac, +static int bwn_nphy_channel_setup(struct bwn_mac *mac, const struct bwn_phy_n_sfo_cfg *e, struct ieee80211_channel *new_channel) { struct bwn_softc *sc = mac->mac_sc; struct bwn_phy *phy = &mac->mac_phy; struct bwn_phy_n *nphy = mac->mac_phy.phy_n; int ch = new_channel->ic_ieee; + int error; uint16_t tmp16; if (bwn_channel_band(mac, new_channel) == BWN_BAND_5G) { DPRINTF(sc, BWN_DEBUG_RESET, "%s: BAND_5G; chan=%d\n", __func__, ch); /* Switch to 2 GHz for a moment to access BWN_PHY_B_BBCFG */ BWN_PHY_MASK(mac, BWN_NPHY_BANDCTL, ~BWN_NPHY_BANDCTL_5GHZ); tmp16 = BWN_READ_2(mac, BWN_PSM_PHY_HDR); BWN_WRITE_2(mac, BWN_PSM_PHY_HDR, tmp16 | 4); /* Put BPHY in the reset */ BWN_PHY_SET(mac, BWN_PHY_B_BBCFG, BWN_PHY_B_BBCFG_RSTCCA | BWN_PHY_B_BBCFG_RSTRX); BWN_WRITE_2(mac, BWN_PSM_PHY_HDR, tmp16); BWN_PHY_SET(mac, BWN_NPHY_BANDCTL, BWN_NPHY_BANDCTL_5GHZ); } else if (bwn_channel_band(mac, new_channel) == BWN_BAND_2G) { DPRINTF(sc, BWN_DEBUG_RESET, "%s: BAND_2G; chan=%d\n", __func__, ch); BWN_PHY_MASK(mac, BWN_NPHY_BANDCTL, ~BWN_NPHY_BANDCTL_5GHZ); tmp16 = BWN_READ_2(mac, BWN_PSM_PHY_HDR); BWN_WRITE_2(mac, BWN_PSM_PHY_HDR, tmp16 | 4); /* Take BPHY out of the reset */ BWN_PHY_MASK(mac, BWN_PHY_B_BBCFG, (uint16_t)~(BWN_PHY_B_BBCFG_RSTCCA | BWN_PHY_B_BBCFG_RSTRX)); BWN_WRITE_2(mac, BWN_PSM_PHY_HDR, tmp16); } else { BWN_ERRPRINTF(mac->mac_sc, "%s: unknown band?\n", __func__); } bwn_chantab_phy_upload(mac, e); if (new_channel->ic_ieee == 14) { bwn_nphy_classifier(mac, 2, 0); BWN_PHY_SET(mac, BWN_PHY_B_TEST, 0x0800); } else { bwn_nphy_classifier(mac, 2, 2); if (bwn_channel_band(mac, new_channel) == BWN_BAND_2G) BWN_PHY_MASK(mac, BWN_PHY_B_TEST, ~0x840); } - if (!nphy->txpwrctrl) - bwn_nphy_tx_power_fix(mac); + if (!nphy->txpwrctrl) { + if ((error = bwn_nphy_tx_power_fix(mac))) + return (error); + } if (mac->mac_phy.rev < 3) bwn_nphy_adjust_lna_gain_table(mac); bwn_nphy_tx_lpf_bw(mac); if (mac->mac_phy.rev >= 3 && mac->mac_phy.phy_n->spur_avoid != BWN_SPUR_AVOID_DISABLE) { - uint8_t spuravoid = 0; + bhnd_pmu_spuravoid spuravoid = BHND_PMU_SPURAVOID_NONE; if (mac->mac_phy.phy_n->spur_avoid == BWN_SPUR_AVOID_FORCE) { - spuravoid = 1; + spuravoid = BHND_PMU_SPURAVOID_M1; } else if (phy->rev >= 19) { /* TODO */ } else if (phy->rev >= 18) { /* TODO */ } else if (phy->rev >= 17) { /* TODO: Off for channels 1-11, but check 12-14! */ } else if (phy->rev >= 16) { /* TODO: Off for 2 GHz, but check 5 GHz! */ } else if (phy->rev >= 7) { if (!bwn_is_40mhz(mac)) { /* 20MHz */ if (ch == 13 || ch == 14 || ch == 153) - spuravoid = 1; + spuravoid = BHND_PMU_SPURAVOID_M1; } else { /* 40 MHz */ if (ch == 54) - spuravoid = 1; + spuravoid = BHND_PMU_SPURAVOID_M1; } } else { if (!bwn_is_40mhz(mac)) { /* 20MHz */ if ((ch >= 5 && ch <= 8) || ch == 13 || ch == 14) - spuravoid = 1; + spuravoid = BHND_PMU_SPURAVOID_M1; } else { /* 40MHz */ if (nphy->aband_spurwar_en && - (ch == 38 || ch == 102 || ch == 118)) - spuravoid = siba_get_chipid(sc->sc_dev) == 0x4716; + (ch == 38 || ch == 102 || ch == 118) && + sc->sc_cid.chip_id == BHND_CHIPID_BCM4716) + spuravoid = BHND_PMU_SPURAVOID_M1; } } bwn_nphy_pmu_spur_avoid(mac, spuravoid); bwn_mac_switch_freq(mac, spuravoid); if (mac->mac_phy.rev == 3 || mac->mac_phy.rev == 4) bwn_wireless_core_phy_pll_reset(mac); - if (spuravoid) + if (spuravoid != BHND_PMU_SPURAVOID_NONE) BWN_PHY_SET(mac, BWN_NPHY_BBCFG, BWN_NPHY_BBCFG_RSTRX); else BWN_PHY_MASK(mac, BWN_NPHY_BBCFG, ~BWN_NPHY_BBCFG_RSTRX & 0xFFFF); bwn_nphy_reset_cca(mac); /* wl sets useless phy_isspuravoid here */ } BWN_PHY_WRITE(mac, BWN_NPHY_NDATAT_DUP40, 0x3830); if (phy->rev >= 3) bwn_nphy_spur_workaround(mac); + + return (0); } /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/SetChanspec */ static int bwn_nphy_set_channel(struct bwn_mac *mac, struct ieee80211_channel *channel, bwn_chan_type_t channel_type) { struct bwn_phy *phy = &mac->mac_phy; const struct bwn_nphy_channeltab_entry_rev2 *tabent_r2 = NULL; const struct bwn_nphy_channeltab_entry_rev3 *tabent_r3 = NULL; const struct bwn_nphy_chantabent_rev7 *tabent_r7 = NULL; const struct bwn_nphy_chantabent_rev7_2g *tabent_r7_2g = NULL; + int error; uint8_t tmp; if (phy->rev >= 19) { return -ESRCH; /* TODO */ } else if (phy->rev >= 7) { r2057_get_chantabent_rev7(mac, bwn_get_chan_centre_freq(mac, channel), &tabent_r7, &tabent_r7_2g); if (!tabent_r7 && !tabent_r7_2g) return -ESRCH; } else if (phy->rev >= 3) { tabent_r3 = bwn_nphy_get_chantabent_rev3(mac, bwn_get_chan_centre_freq(mac, channel)); if (!tabent_r3) return -ESRCH; } else { tabent_r2 = bwn_nphy_get_chantabent_rev2(mac, channel->ic_ieee); if (!tabent_r2) return -ESRCH; } /* Channel is set later in common code, but we need to set it on our own to let this function's subcalls work properly. */ #if 0 phy->channel = channel->ic_ieee; #endif #if 0 if (bwn_channel_type_is_40mhz(phy->channel_type) != bwn_channel_type_is_40mhz(channel_type)) ; /* TODO: BMAC BW Set (channel_type) */ #endif if (channel_type == BWN_CHAN_TYPE_40_HT_U) { BWN_PHY_SET(mac, BWN_NPHY_RXCTL, BWN_NPHY_RXCTL_BSELU20); if (phy->rev >= 7) BWN_PHY_SET(mac, 0x310, 0x8000); } else if (channel_type == BWN_CHAN_TYPE_40_HT_D) { BWN_PHY_MASK(mac, BWN_NPHY_RXCTL, ~BWN_NPHY_RXCTL_BSELU20); if (phy->rev >= 7) BWN_PHY_MASK(mac, 0x310, (uint16_t)~0x8000); } if (phy->rev >= 19) { /* TODO */ + error = ENODEV; } else if (phy->rev >= 7) { const struct bwn_phy_n_sfo_cfg *phy_regs = tabent_r7 ? &(tabent_r7->phy_regs) : &(tabent_r7_2g->phy_regs); if (phy->rf_rev <= 4 || phy->rf_rev == 6) { tmp = (bwn_channel_band(mac, channel) == BWN_BAND_5G) ? 2 : 0; BWN_RF_SETMASK(mac, R2057_TIA_CONFIG_CORE0, ~2, tmp); BWN_RF_SETMASK(mac, R2057_TIA_CONFIG_CORE1, ~2, tmp); } bwn_radio_2057_setup(mac, tabent_r7, tabent_r7_2g); - bwn_nphy_channel_setup(mac, phy_regs, channel); + error = bwn_nphy_channel_setup(mac, phy_regs, channel); } else if (phy->rev >= 3) { tmp = (bwn_channel_band(mac, channel) == BWN_BAND_5G) ? 4 : 0; BWN_RF_SETMASK(mac, 0x08, 0xFFFB, tmp); bwn_radio_2056_setup(mac, tabent_r3); - bwn_nphy_channel_setup(mac, &(tabent_r3->phy_regs), channel); + error = bwn_nphy_channel_setup(mac, &(tabent_r3->phy_regs), + channel); } else { tmp = (bwn_channel_band(mac, channel) == BWN_BAND_5G) ? 0x0020 : 0x0050; BWN_RF_SETMASK(mac, B2055_MASTER1, 0xFF8F, tmp); bwn_radio_2055_setup(mac, tabent_r2); - bwn_nphy_channel_setup(mac, &(tabent_r2->phy_regs), channel); + error = bwn_nphy_channel_setup(mac, &(tabent_r2->phy_regs), + channel); } - return 0; + return (error); } /************************************************** * Basic PHY ops. **************************************************/ int bwn_nphy_op_allocate(struct bwn_mac *mac) { struct bwn_phy_n *nphy; nphy = malloc(sizeof(*nphy), M_DEVBUF, M_ZERO | M_NOWAIT); if (!nphy) return -ENOMEM; mac->mac_phy.phy_n = nphy; return 0; } -void +int bwn_nphy_op_prepare_structs(struct bwn_mac *mac) { struct bwn_softc *sc = mac->mac_sc; struct bwn_phy *phy = &mac->mac_phy; struct bwn_phy_n *nphy = phy->phy_n; + int error; memset(nphy, 0, sizeof(*nphy)); nphy->hang_avoid = (phy->rev == 3 || phy->rev == 4); nphy->spur_avoid = (phy->rev >= 3) ? BWN_SPUR_AVOID_AUTO : BWN_SPUR_AVOID_DISABLE; nphy->gain_boost = true; /* this way we follow wl, assume it is true */ nphy->txrx_chain = 2; /* sth different than 0 and 1 for now */ nphy->phyrxchain = 3; /* to avoid bwn_nphy_set_rx_core_state like wl */ nphy->perical = 2; /* avoid additional rssi cal on init (like wl) */ /* 128 can mean disabled-by-default state of TX pwr ctl. Max value is * 0x7f == 127 and we check for 128 when restoring TX pwr ctl. */ nphy->tx_pwr_idx[0] = 128; nphy->tx_pwr_idx[1] = 128; /* Hardware TX power control and 5GHz power gain */ nphy->txpwrctrl = false; nphy->pwg_gain_5ghz = false; if (mac->mac_phy.rev >= 3 || - (siba_get_pci_subvendor(sc->sc_dev) == PCI_VENDOR_APPLE && - (siba_get_revid(sc->sc_dev) == 11 || siba_get_revid(sc->sc_dev) == 12))) { + (sc->sc_board_info.board_vendor == PCI_VENDOR_APPLE && + (bhnd_get_hwrev(sc->sc_dev) == 11 || bhnd_get_hwrev(sc->sc_dev) == 12))) { nphy->txpwrctrl = true; nphy->pwg_gain_5ghz = true; - } else if (siba_sprom_get_rev(sc->sc_dev) >= 4) { + } else if (sc->sc_board_info.board_srom_rev >= 4) { if (mac->mac_phy.rev >= 2 && - (siba_sprom_get_bf2_lo(sc->sc_dev) & BWN_BFL2_TXPWRCTRL_EN)) { + (sc->sc_board_info.board_flags2 & BHND_BFL2_TXPWRCTRL_EN)) { nphy->txpwrctrl = true; - if (siba_get_type(sc->sc_dev) == SIBA_TYPE_PCI) { - if ((siba_get_pci_device(sc->sc_dev) == 0x4328) || - (siba_get_pci_device(sc->sc_dev) == 0x432a)) - nphy->pwg_gain_5ghz = true; - } - } else if (siba_sprom_get_bf2_lo(sc->sc_dev) & BWN_BFL2_5G_PWRGAIN) { + if ((sc->sc_board_info.board_devid == PCI_DEVID_BCM4321_D11N) || + (sc->sc_board_info.board_devid == PCI_DEVID_BCM4321_D11N5G)) + nphy->pwg_gain_5ghz = true; + } else if (sc->sc_board_info.board_flags2 & BHND_BFL2_5G_PWRGAIN) { nphy->pwg_gain_5ghz = true; } } if (mac->mac_phy.rev >= 3) { - nphy->ipa2g_on = siba_sprom_get_fem_2ghz_extpa_gain(sc->sc_dev) == 2; - nphy->ipa5g_on = siba_sprom_get_fem_5ghz_extpa_gain(sc->sc_dev) == 2; + uint8_t extpa_gain2g, extpa_gain5g; + + error = bhnd_nvram_getvar_uint8(sc->sc_dev, + BHND_NVAR_EXTPAGAIN2G, &extpa_gain2g); + if (error) { + BWN_ERRPRINTF(mac->mac_sc, "Error reading 2GHz EPA " + "gain configuration from NVRAM: %d\n", error); + return (error); + } + + error = bhnd_nvram_getvar_uint8(sc->sc_dev, + BHND_NVAR_EXTPAGAIN5G, &extpa_gain5g); + if (error) { + BWN_ERRPRINTF(mac->mac_sc, "Error reading 5GHz EPA " + "gain configuration from NVRAM: %d\n", error); + return (error); + } + + nphy->ipa2g_on = (extpa_gain2g == 2); + nphy->ipa5g_on = (extpa_gain5g == 2); } + + return (0); } void bwn_nphy_op_free(struct bwn_mac *mac) { struct bwn_phy *phy = &mac->mac_phy; struct bwn_phy_n *nphy = phy->phy_n; free(nphy, M_DEVBUF); phy->phy_n = NULL; } int bwn_nphy_op_init(struct bwn_mac *mac) { return bwn_phy_initn(mac); } static inline void check_phyreg(struct bwn_mac *mac, uint16_t offset) { #ifdef BWN_DEBUG if ((offset & BWN_PHYROUTE_MASK) == BWN_PHYROUTE_OFDM_GPHY) { /* OFDM registers are onnly available on A/G-PHYs */ BWN_ERRPRINTF(mac->mac_sc, "Invalid OFDM PHY access at " "0x%04X on N-PHY\n", offset); } if ((offset & BWN_PHYROUTE_MASK) == BWN_PHYROUTE_EXT_GPHY) { /* Ext-G registers are only available on G-PHYs */ BWN_ERRPRINTF(mac->mac_sc, "Invalid EXT-G PHY access at " "0x%04X on N-PHY\n", offset); } #endif /* BWN_DEBUG */ } void bwn_nphy_op_maskset(struct bwn_mac *mac, uint16_t reg, uint16_t mask, uint16_t set) { check_phyreg(mac, reg); BWN_WRITE_2_F(mac, BWN_PHYCTL, reg); BWN_WRITE_SETMASK2(mac, BWN_PHYDATA, mask, set); } #if 0 uint16_t bwn_nphy_op_radio_read(struct bwn_mac *mac, uint16_t reg) { /* Register 1 is a 32-bit register. */ if (mac->mac_phy.rev < 7 && reg == 1) { BWN_ERRPRINTF(mac->mac_sc, "%s: bad reg access\n", __func__); } if (mac->mac_phy.rev >= 7) reg |= 0x200; /* Radio 0x2057 */ else reg |= 0x100; BWN_WRITE_2_F(mac, BWN_RFCTL, reg); return BWN_READ_2(mac, BWN_RFDATALO); } #endif #if 0 void bwn_nphy_op_radio_write(struct bwn_mac *mac, uint16_t reg, uint16_t value) { /* Register 1 is a 32-bit register. */ if (mac->mac_phy.rev < 7 && reg == 1) { BWN_ERRPRINTF(mac->mac_sc, "%s: bad reg access\n", __func__); } BWN_WRITE_2_F(mac, BWN_RFCTL, reg); BWN_WRITE_2(mac, BWN_RFDATALO, value); } #endif /* http://bcm-v4.sipsolutions.net/802.11/Radio/Switch%20Radio */ void bwn_nphy_op_software_rfkill(struct bwn_mac *mac, bool active) { struct bwn_phy *phy = &mac->mac_phy; if (BWN_READ_4(mac, BWN_MACCTL) & BWN_MACCTL_ON) BWN_ERRPRINTF(mac->mac_sc, "MAC not suspended\n"); DPRINTF(mac->mac_sc, BWN_DEBUG_RESET | BWN_DEBUG_PHY, "%s: called; rev=%d, rf_on=%d, active=%d\n", __func__, phy->rev, mac->mac_phy.rf_on, active); /* * XXX TODO: don't bother doing RF programming if it's * already done. But, bwn(4) currently sets rf_on in the * PHY setup and leaves it on after startup, which causes * the below to not init the 2056/2057 radios. */ if (active) { if (phy->rev >= 19) { /* TODO */ } else if (phy->rev >= 7) { // if (!mac->mac_phy.rf_on) bwn_radio_2057_init(mac); bwn_switch_channel(mac, bwn_get_chan(mac)); } else if (phy->rev >= 3) { // if (!mac->mac_phy.rf_on) bwn_radio_init2056(mac); bwn_switch_channel(mac, bwn_get_chan(mac)); } else { bwn_radio_init2055(mac); } } else { if (phy->rev >= 19) { /* TODO */ } else if (phy->rev >= 8) { BWN_PHY_MASK(mac, BWN_NPHY_RFCTL_CMD, ~BWN_NPHY_RFCTL_CMD_CHIP0PU); } else if (phy->rev >= 7) { /* Nothing needed */ } else if (phy->rev >= 3) { BWN_PHY_MASK(mac, BWN_NPHY_RFCTL_CMD, ~BWN_NPHY_RFCTL_CMD_CHIP0PU); BWN_RF_MASK(mac, 0x09, ~0x2); BWN_RF_WRITE(mac, 0x204D, 0); BWN_RF_WRITE(mac, 0x2053, 0); BWN_RF_WRITE(mac, 0x2058, 0); BWN_RF_WRITE(mac, 0x205E, 0); BWN_RF_MASK(mac, 0x2062, ~0xF0); BWN_RF_WRITE(mac, 0x2064, 0); BWN_RF_WRITE(mac, 0x304D, 0); BWN_RF_WRITE(mac, 0x3053, 0); BWN_RF_WRITE(mac, 0x3058, 0); BWN_RF_WRITE(mac, 0x305E, 0); BWN_RF_MASK(mac, 0x3062, ~0xF0); BWN_RF_WRITE(mac, 0x3064, 0); } } } /* http://bcm-v4.sipsolutions.net/802.11/PHY/Anacore */ void bwn_nphy_op_switch_analog(struct bwn_mac *mac, bool on) { struct bwn_phy *phy = &mac->mac_phy; uint16_t override = on ? 0x0 : 0x7FFF; uint16_t core = on ? 0xD : 0x00FD; if (phy->rev >= 19) { /* TODO */ device_printf(mac->mac_sc->sc_dev, "%s: TODO\n", __func__); } else if (phy->rev >= 3) { if (on) { BWN_PHY_WRITE(mac, BWN_NPHY_AFECTL_C1, core); BWN_PHY_WRITE(mac, BWN_NPHY_AFECTL_OVER1, override); BWN_PHY_WRITE(mac, BWN_NPHY_AFECTL_C2, core); BWN_PHY_WRITE(mac, BWN_NPHY_AFECTL_OVER, override); } else { BWN_PHY_WRITE(mac, BWN_NPHY_AFECTL_OVER1, override); BWN_PHY_WRITE(mac, BWN_NPHY_AFECTL_C1, core); BWN_PHY_WRITE(mac, BWN_NPHY_AFECTL_OVER, override); BWN_PHY_WRITE(mac, BWN_NPHY_AFECTL_C2, core); } } else { BWN_PHY_WRITE(mac, BWN_NPHY_AFECTL_OVER, override); } } int bwn_nphy_op_switch_channel(struct bwn_mac *mac, unsigned int new_channel) { struct ieee80211_channel *channel = bwn_get_channel(mac); bwn_chan_type_t channel_type = bwn_get_chan_type(mac, NULL); if (bwn_current_band(mac) == BWN_BAND_2G) { if ((new_channel < 1) || (new_channel > 14)) return -EINVAL; } else { if (new_channel > 200) return -EINVAL; } return bwn_nphy_set_channel(mac, channel, channel_type); } #if 0 unsigned int bwn_nphy_op_get_default_chan(struct bwn_mac *mac) { if (bwn_current_band(mac) == BWN_BAND_2G) return 1; return 36; } #endif Index: head/sys/gnu/dev/bwn/phy_n/if_bwn_phy_n_core.h =================================================================== --- head/sys/gnu/dev/bwn/phy_n/if_bwn_phy_n_core.h (revision 328911) +++ head/sys/gnu/dev/bwn/phy_n/if_bwn_phy_n_core.h (revision 328912) @@ -1,181 +1,182 @@ /* Broadcom B43 wireless driver N-PHY core code. Copyright (c) 2008 Michael Buesch Copyright (c) 2010 RafaÅ‚ MiÅ‚ecki Copyright (c) 2016 Adrian Chadd This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 2 of the License, or (at your option) any later version. This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with this program; see the file COPYING. If not, write to the Free Software Foundation, Inc., 51 Franklin Steet, Fifth Floor, Boston, MA 02110-1301, USA. */ /* * $FreeBSD$ */ #ifndef __IF_BWN_PHY_N_CORE_H__ #define __IF_BWN_PHY_N_CORE_H__ struct bwn_mac; enum b43_nphy_spur_avoid { BWN_SPUR_AVOID_DISABLE, BWN_SPUR_AVOID_AUTO, BWN_SPUR_AVOID_FORCE, }; /* * TODO: determine whether center_freq is the primary * channel centre frequency or the actual centre centre * frequency (eg radio tuning.) It /looks/ like it's * actual channel centre. */ struct bwn_chanspec { uint16_t center_freq; /* This is HT40U, HT40D, HT20, no-HT 20, etc */ bwn_chan_type_t channel_type; }; struct bwn_phy_n_iq_comp { int16_t a0; int16_t b0; int16_t a1; int16_t b1; }; struct bwn_phy_n_rssical_cache { uint16_t rssical_radio_regs_2G[2]; uint16_t rssical_phy_regs_2G[12]; uint16_t rssical_radio_regs_5G[2]; uint16_t rssical_phy_regs_5G[12]; }; struct bwn_phy_n_cal_cache { uint16_t txcal_radio_regs_2G[8]; uint16_t txcal_coeffs_2G[8]; struct bwn_phy_n_iq_comp rxcal_coeffs_2G; uint16_t txcal_radio_regs_5G[8]; uint16_t txcal_coeffs_5G[8]; struct bwn_phy_n_iq_comp rxcal_coeffs_5G; }; struct bwn_phy_n_txpwrindex { int8_t index; int8_t index_internal; int8_t index_internal_save; uint16_t AfectrlOverride; uint16_t AfeCtrlDacGain; uint16_t rad_gain; uint8_t bbmult; uint16_t iqcomp_a; uint16_t iqcomp_b; uint16_t locomp; }; struct bwn_phy_n_pwr_ctl_info { uint8_t idle_tssi_2g; uint8_t idle_tssi_5g; }; struct bwn_phy_n { uint8_t antsel_type; uint8_t cal_orig_pwr_idx[2]; uint8_t measure_hold; uint8_t phyrxchain; uint8_t hw_phyrxchain; uint8_t hw_phytxchain; uint8_t perical; uint32_t deaf_count; uint32_t rxcalparams; bool hang_avoid; bool mute; uint16_t papd_epsilon_offset[2]; int32_t preamble_override; uint32_t bb_mult_save; bool gain_boost; bool elna_gain_config; bool band5g_pwrgain; bool use_int_tx_iq_lo_cal; bool lpf_bw_overrode_for_sample_play; uint8_t mphase_cal_phase_id; uint16_t mphase_txcal_cmdidx; uint16_t mphase_txcal_numcmds; uint16_t mphase_txcal_bestcoeffs[11]; bool txpwrctrl; bool pwg_gain_5ghz; uint8_t tx_pwr_idx[2]; int8_t tx_power_offset[101]; uint16_t adj_pwr_tbl[84]; uint16_t txcal_bbmult; uint16_t txiqlocal_bestc[11]; bool txiqlocal_coeffsvalid; struct bwn_phy_n_txpwrindex txpwrindex[2]; struct bwn_phy_n_pwr_ctl_info pwr_ctl_info[2]; struct bwn_chanspec txiqlocal_chanspec; struct bwn_ppr tx_pwr_max_ppr; uint16_t tx_pwr_last_recalc_freq; int tx_pwr_last_recalc_limit; + uint8_t tsspos_2g; uint8_t txrx_chain; uint16_t tx_rx_cal_phy_saveregs[11]; uint16_t tx_rx_cal_radio_saveregs[22]; uint16_t rfctrl_intc1_save; uint16_t rfctrl_intc2_save; uint16_t classifier_state; uint16_t clip_state[2]; enum b43_nphy_spur_avoid spur_avoid; bool aband_spurwar_en; bool gband_spurwar_en; bool ipa2g_on; struct bwn_chanspec iqcal_chanspec_2G; struct bwn_chanspec rssical_chanspec_2G; bool ipa5g_on; struct bwn_chanspec iqcal_chanspec_5G; struct bwn_chanspec rssical_chanspec_5G; struct bwn_phy_n_rssical_cache rssical_cache; struct bwn_phy_n_cal_cache cal_cache; bool crsminpwr_adjusted; bool noisevars_adjusted; }; extern bwn_txpwr_result_t bwn_nphy_op_recalc_txpower(struct bwn_mac *mac, bool ignore_tssi); extern int bwn_nphy_op_allocate(struct bwn_mac *mac); -extern void bwn_nphy_op_prepare_structs(struct bwn_mac *mac); +extern int bwn_nphy_op_prepare_structs(struct bwn_mac *mac); extern void bwn_nphy_op_free(struct bwn_mac *mac); extern int bwn_nphy_op_init(struct bwn_mac *mac); extern void bwn_nphy_op_maskset(struct bwn_mac *mac, uint16_t reg, uint16_t mask, uint16_t set); extern uint16_t bwn_nphy_op_radio_read(struct bwn_mac *mac, uint16_t reg); extern void bwn_nphy_op_radio_write(struct bwn_mac *mac, uint16_t reg, uint16_t value); extern void bwn_nphy_op_software_rfkill(struct bwn_mac *mac, bool blocked); extern void bwn_nphy_op_switch_analog(struct bwn_mac *mac, bool on); extern int bwn_nphy_op_switch_channel(struct bwn_mac *mac, unsigned int new_channel); extern unsigned int bwn_nphy_op_get_default_chan(struct bwn_mac *mac); #endif /* __IF_BWN_PHY_N_CORE_H__ */ Index: head/sys/gnu/dev/bwn/phy_n/if_bwn_phy_n_ppr.c =================================================================== --- head/sys/gnu/dev/bwn/phy_n/if_bwn_phy_n_ppr.c (revision 328911) +++ head/sys/gnu/dev/bwn/phy_n/if_bwn_phy_n_ppr.c (revision 328912) @@ -1,271 +1,334 @@ /* Broadcom B43 wireless driver IEEE 802.11n PHY data tables Copyright (c) 2008 Michael Buesch Copyright (c) 2010 RafaÅ‚ MiÅ‚ecki This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 2 of the License, or (at your option) any later version. This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with this program; see the file COPYING. If not, write to the Free Software Foundation, Inc., 51 Franklin Steet, Fifth Floor, Boston, MA 02110-1301, USA. */ #include __FBSDID("$FreeBSD$"); /* * The Broadcom Wireless LAN controller driver. */ #include "opt_wlan.h" #include "opt_bwn.h" #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include +#include +#include + #include #include #include #include #include #include +#include #include +#include "bhnd_nvram_map.h" + #define ppr_for_each_entry(ppr, i, entry) \ for (i = 0, entry = &(ppr)->__all_rates[i]; \ i < BWN_PPR_RATES_NUM; \ i++, entry++) void bwn_ppr_clear(struct bwn_mac *mac, struct bwn_ppr *ppr) { memset(ppr, 0, sizeof(*ppr)); /* Compile-time PPR check */ CTASSERT(sizeof(struct bwn_ppr) == BWN_PPR_RATES_NUM * sizeof(uint8_t)); } void bwn_ppr_add(struct bwn_mac *mac, struct bwn_ppr *ppr, int diff) { int i; uint8_t *rate; ppr_for_each_entry(ppr, i, rate) { *rate = bwn_clamp_val(*rate + diff, 0, 127); } } void bwn_ppr_apply_max(struct bwn_mac *mac, struct bwn_ppr *ppr, uint8_t max) { int i; uint8_t *rate; ppr_for_each_entry(ppr, i, rate) { *rate = min(*rate, max); } } void bwn_ppr_apply_min(struct bwn_mac *mac, struct bwn_ppr *ppr, uint8_t min) { int i; uint8_t *rate; ppr_for_each_entry(ppr, i, rate) { *rate = max(*rate, min); } } uint8_t bwn_ppr_get_max(struct bwn_mac *mac, struct bwn_ppr *ppr) { uint8_t res = 0; int i; uint8_t *rate; ppr_for_each_entry(ppr, i, rate) { res = max(*rate, res); } return res; } bool bwn_ppr_load_max_from_sprom(struct bwn_mac *mac, struct bwn_ppr *ppr, bwn_phy_band_t band) { struct bwn_softc *sc = mac->mac_sc; - struct siba_sprom_core_pwr_info core_pwr_info[4]; + struct bwn_phy_n_core_pwr_info core_pwr_info[4]; struct bwn_ppr_rates *rates = &ppr->rates; struct bwn_phy *phy = &mac->mac_phy; + const char *var_ofdmgpo, *var_mcsgpo_prefix; uint8_t maxpwr, off; uint32_t sprom_ofdm_po; uint16_t sprom_mcs_po[8]; + uint16_t cddpo, stbcpo; uint8_t extra_cdd_po, extra_stbc_po; + int error; int i; for (i = 0; i < 4; i++) { bzero(&core_pwr_info[i], sizeof(core_pwr_info[i])); - if (siba_sprom_get_core_power_info(sc->sc_dev, i, + if (bwn_nphy_get_core_power_info(mac, i, &core_pwr_info[i]) != 0) { BWN_ERRPRINTF(mac->mac_sc, "%s: failed to get core_pwr_info for core %d\n", __func__, i); } } + error = bhnd_nvram_getvar_uint16(sc->sc_dev, BHND_NVAR_CDDPO, &cddpo); + if (error) { + BWN_ERRPRINTF(mac->mac_sc, "NVRAM variable %s unreadable: %d\n", + BHND_NVAR_CDDPO, error); + return (false); + } + + error = bhnd_nvram_getvar_uint16(sc->sc_dev, BHND_NVAR_STBCPO, &stbcpo); + if (error) { + BWN_ERRPRINTF(mac->mac_sc, "NVRAM variable %s unreadable: %d\n", + BHND_NVAR_STBCPO, error); + return (false); + } + switch (band) { case BWN_PHY_BAND_2G: maxpwr = min(core_pwr_info[0].maxpwr_2g, core_pwr_info[1].maxpwr_2g); - sprom_ofdm_po = siba_sprom_get_ofdm2gpo(sc->sc_dev); - siba_sprom_get_mcs2gpo(sc->sc_dev, sprom_mcs_po); - extra_cdd_po = (siba_sprom_get_cddpo(sc->sc_dev) >> 0) & 0xf; - extra_stbc_po = (siba_sprom_get_stbcpo(sc->sc_dev) >> 0) & 0xf; + + var_ofdmgpo = BHND_NVAR_OFDM2GPO; + var_mcsgpo_prefix = "mcs2gpo"; + extra_cdd_po = (cddpo >> 0) & 0xf; + extra_stbc_po = (stbcpo >> 0) & 0xf; break; case BWN_PHY_BAND_5G_LO: maxpwr = min(core_pwr_info[0].maxpwr_5gl, core_pwr_info[1].maxpwr_5gl); - sprom_ofdm_po = siba_sprom_get_ofdm5glpo(sc->sc_dev); - siba_sprom_get_mcs5glpo(sc->sc_dev, sprom_mcs_po); - extra_cdd_po = (siba_sprom_get_cddpo(sc->sc_dev) >> 8) & 0xf; - extra_stbc_po = (siba_sprom_get_stbcpo(sc->sc_dev) >> 8) & 0xf; + var_ofdmgpo = BHND_NVAR_OFDM5GLPO; + var_mcsgpo_prefix = "mcs5glpo"; + extra_cdd_po = (cddpo >> 8) & 0xf; + extra_stbc_po = (stbcpo >> 8) & 0xf; break; case BWN_PHY_BAND_5G_MI: maxpwr = min(core_pwr_info[0].maxpwr_5g, core_pwr_info[1].maxpwr_5g); - sprom_ofdm_po = siba_sprom_get_ofdm5gpo(sc->sc_dev); - siba_sprom_get_mcs5gpo(sc->sc_dev, sprom_mcs_po); - extra_cdd_po = (siba_sprom_get_cddpo(sc->sc_dev) >> 4) & 0xf; - extra_stbc_po = (siba_sprom_get_stbcpo(sc->sc_dev) >> 4) & 0xf; + var_ofdmgpo = BHND_NVAR_OFDM5GPO; + var_mcsgpo_prefix = "mcs5gpo"; + extra_cdd_po = (cddpo >> 4) & 0xf; + extra_stbc_po = (stbcpo >> 4) & 0xf; break; case BWN_PHY_BAND_5G_HI: maxpwr = min(core_pwr_info[0].maxpwr_5gh, core_pwr_info[1].maxpwr_5gh); - sprom_ofdm_po = siba_sprom_get_ofdm5ghpo(sc->sc_dev); - siba_sprom_get_mcs5ghpo(sc->sc_dev, sprom_mcs_po); - extra_cdd_po = (siba_sprom_get_cddpo(sc->sc_dev) >> 12) & 0xf; - extra_stbc_po = (siba_sprom_get_stbcpo(sc->sc_dev) >> 12) & 0xf; + var_ofdmgpo = BHND_NVAR_OFDM5GHPO; + var_mcsgpo_prefix = "mcs5ghpo"; + extra_cdd_po = (cddpo >> 12) & 0xf; + extra_stbc_po = (stbcpo >> 12) & 0xf; break; default: device_printf(mac->mac_sc->sc_dev, "%s: invalid band (%d)\n", __func__, band); return false; } + error = bhnd_nvram_getvar_uint32(sc->sc_dev, var_ofdmgpo, + &sprom_ofdm_po); + if (error) { + device_printf(sc->sc_dev, "NVRAM variable %s unreadable: %d\n", + var_ofdmgpo, error); + return (false); + } + + for (size_t i = 0; i < nitems(sprom_mcs_po); i++) { + char var[strlen(var_mcsgpo_prefix) + sizeof("XX")]; + int ret; + + /* mcs[25]g[lh]?po[0-9] */ + ret = snprintf(var, sizeof(var), "%s%zu", var_mcsgpo_prefix, i); + if (ret >= sizeof(var)) { + device_printf(sc->sc_dev, "buffer too small for " + "%s%zu\n", var_mcsgpo_prefix, i); + return (false); + } + + error = bhnd_nvram_getvar_uint16(sc->sc_dev, var, + &sprom_mcs_po[i]); + if (error) { + device_printf(sc->sc_dev, "NVRAM variable %s " + "unreadable: %d\n", var, error); + return (false); + } + } + if (band == BWN_BAND_2G) { + uint16_t ck2gpo; + + error = bhnd_nvram_getvar_uint16(sc->sc_dev, BHND_NVAR_CCK2GPO, + &ck2gpo); + if (error) { + device_printf(sc->sc_dev, "NVRAM variable %s " + "unreadable: %d\n", BHND_NVAR_CCK2GPO, error); + return (false); + } + for (i = 0; i < 4; i++) { - off = ((siba_sprom_get_cck2gpo(sc->sc_dev) >> (i * 4)) & 0xf) * 2; + off = ((ck2gpo >> (i * 4)) & 0xf) * 2; rates->cck[i] = maxpwr - off; } } /* OFDM */ for (i = 0; i < 8; i++) { off = ((sprom_ofdm_po >> (i * 4)) & 0xf) * 2; rates->ofdm[i] = maxpwr - off; } /* MCS 20 SISO */ rates->mcs_20[0] = rates->ofdm[0]; rates->mcs_20[1] = rates->ofdm[2]; rates->mcs_20[2] = rates->ofdm[3]; rates->mcs_20[3] = rates->ofdm[4]; rates->mcs_20[4] = rates->ofdm[5]; rates->mcs_20[5] = rates->ofdm[6]; rates->mcs_20[6] = rates->ofdm[7]; rates->mcs_20[7] = rates->ofdm[7]; /* MCS 20 CDD */ for (i = 0; i < 4; i++) { off = ((sprom_mcs_po[0] >> (i * 4)) & 0xf) * 2; rates->mcs_20_cdd[i] = maxpwr - off; if (phy->type == BWN_PHYTYPE_N && phy->rev >= 3) rates->mcs_20_cdd[i] -= extra_cdd_po; } for (i = 0; i < 4; i++) { off = ((sprom_mcs_po[1] >> (i * 4)) & 0xf) * 2; rates->mcs_20_cdd[4 + i] = maxpwr - off; if (phy->type == BWN_PHYTYPE_N && phy->rev >= 3) rates->mcs_20_cdd[4 + i] -= extra_cdd_po; } /* OFDM 20 CDD */ rates->ofdm_20_cdd[0] = rates->mcs_20_cdd[0]; rates->ofdm_20_cdd[1] = rates->mcs_20_cdd[0]; rates->ofdm_20_cdd[2] = rates->mcs_20_cdd[1]; rates->ofdm_20_cdd[3] = rates->mcs_20_cdd[2]; rates->ofdm_20_cdd[4] = rates->mcs_20_cdd[3]; rates->ofdm_20_cdd[5] = rates->mcs_20_cdd[4]; rates->ofdm_20_cdd[6] = rates->mcs_20_cdd[5]; rates->ofdm_20_cdd[7] = rates->mcs_20_cdd[6]; /* MCS 20 STBC */ for (i = 0; i < 4; i++) { off = ((sprom_mcs_po[0] >> (i * 4)) & 0xf) * 2; rates->mcs_20_stbc[i] = maxpwr - off; if (phy->type == BWN_PHYTYPE_N && phy->rev >= 3) rates->mcs_20_stbc[i] -= extra_stbc_po; } for (i = 0; i < 4; i++) { off = ((sprom_mcs_po[1] >> (i * 4)) & 0xf) * 2; rates->mcs_20_stbc[4 + i] = maxpwr - off; if (phy->type == BWN_PHYTYPE_N && phy->rev >= 3) rates->mcs_20_stbc[4 + i] -= extra_stbc_po; } /* MCS 20 SDM */ for (i = 0; i < 4; i++) { off = ((sprom_mcs_po[2] >> (i * 4)) & 0xf) * 2; rates->mcs_20_sdm[i] = maxpwr - off; } for (i = 0; i < 4; i++) { off = ((sprom_mcs_po[3] >> (i * 4)) & 0xf) * 2; rates->mcs_20_sdm[4 + i] = maxpwr - off; } return true; } Index: head/sys/gnu/dev/bwn/phy_n/if_bwn_phy_n_sprom.c =================================================================== --- head/sys/gnu/dev/bwn/phy_n/if_bwn_phy_n_sprom.c (nonexistent) +++ head/sys/gnu/dev/bwn/phy_n/if_bwn_phy_n_sprom.c (revision 328912) @@ -0,0 +1,181 @@ +/*- + * SPDX-License-Identifier: BSD-2-Clause + * + * Copyright (c) 2016 Landon Fuller + * Copyright (c) 2017 The FreeBSD Foundation + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer, + * without modification. + * 2. Redistributions in binary form must reproduce at minimum a disclaimer + * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any + * redistribution must be conditioned upon including a substantially + * similar Disclaimer requirement for further binary redistribution. + * + * NO WARRANTY + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY + * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL + * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, + * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER + * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF + * THE POSSIBILITY OF SUCH DAMAGES. + * + * $FreeBSD$ + */ + +#include +__FBSDID("$FreeBSD$"); + +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include + +#include + +#include + +#include "if_bwn_phy_n_sprom.h" + +#include "bhnd_nvram_map.h" + + +/* Core power NVRAM variables, indexed by D11 core unit number */ +static const struct bwn_nphy_power_vars { + const char *itt2ga; + const char *itt5ga; + const char *maxp2ga; + const char *pa2ga; + const char *pa5ga; +} bwn_nphy_power_vars[BWN_NPHY_NUM_CORE_PWR] = { +#define BHND_POWER_NVAR(_idx) \ + { BHND_NVAR_ITT2GA ## _idx, BHND_NVAR_ITT5GA ## _idx, \ + BHND_NVAR_MAXP2GA ## _idx, BHND_NVAR_PA2GA ## _idx, \ + BHND_NVAR_PA5GA ## _idx } + BHND_POWER_NVAR(0), + BHND_POWER_NVAR(1), + BHND_POWER_NVAR(2), + BHND_POWER_NVAR(3) +#undef BHND_POWER_NVAR +}; + +static int +bwn_nphy_get_core_power_info_r11(struct bwn_softc *sc, + const struct bwn_nphy_power_vars *v, struct bwn_phy_n_core_pwr_info *c) +{ + int16_t pa5ga[12]; + int error; + + /* BHND_NVAR_PA2GA[core] */ + error = bhnd_nvram_getvar_array(sc->sc_dev, v->pa2ga, c->pa_2g, + sizeof(c->pa_2g), BHND_NVRAM_TYPE_INT16); + if (error) + return (error); + + /* + * BHND_NVAR_PA5GA + * + * The NVRAM variable is defined as a single pa5ga[12] array; we have + * to split this into pa_5gl[4], pa_5g[4], and pa_5gh[4] for use + * by bwn(4); + */ + _Static_assert(nitems(pa5ga) == nitems(c->pa_5g) + nitems(c->pa_5gh) + + nitems(c->pa_5gl), "cannot split pa5ga into pa_5gl/pa_5g/pa_5gh"); + + error = bhnd_nvram_getvar_array(sc->sc_dev, v->pa5ga, pa5ga, + sizeof(pa5ga), BHND_NVRAM_TYPE_INT16); + if (error) + return (error); + + memcpy(c->pa_5gl, &pa5ga[0], sizeof(c->pa_5gl)); + memcpy(c->pa_5g, &pa5ga[4], sizeof(c->pa_5g)); + memcpy(c->pa_5gh, &pa5ga[8], sizeof(c->pa_5gh)); + return (0); +} + +static int +bwn_nphy_get_core_power_info_r4_r10(struct bwn_softc *sc, + const struct bwn_nphy_power_vars *v, struct bwn_phy_n_core_pwr_info *c) +{ + int error; + + /* BHND_NVAR_ITT2GA[core] */ + error = bhnd_nvram_getvar_uint8(sc->sc_dev, v->itt2ga, &c->itssi_2g); + if (error) + return (error); + + /* BHND_NVAR_ITT5GA[core] */ + error = bhnd_nvram_getvar_uint8(sc->sc_dev, v->itt5ga, &c->itssi_5g); + if (error) + return (error); + + return (0); +} + +/* + * siba_sprom_get_core_power_info() + * + * Referenced by: + * bwn_nphy_tx_power_ctl_setup() + * bwn_ppr_load_max_from_sprom() + */ +int +bwn_nphy_get_core_power_info(struct bwn_mac *mac, int core, + struct bwn_phy_n_core_pwr_info *c) +{ + struct bwn_softc *sc; + const struct bwn_nphy_power_vars *v; + uint8_t sromrev; + int error; + + sc = mac->mac_sc; + + if (core < 0 || core >= nitems(bwn_nphy_power_vars)) + return (EINVAL); + + sromrev = sc->sc_board_info.board_srom_rev; + if (sromrev < 4) + return (ENXIO); + + v = &bwn_nphy_power_vars[core]; + + /* Any power variables not found in NVRAM (or returning a + * shorter array for a particular NVRAM revision) should be zero + * initialized */ + memset(c, 0x0, sizeof(*c)); + + /* Populate SPROM revision-independent values */ + error = bhnd_nvram_getvar_uint8(sc->sc_dev, v->maxp2ga, &c->maxpwr_2g); + if (error) + return (error); + + /* Populate SPROM revision-specific values */ + if (sromrev >= 4 && sromrev <= 10) + return (bwn_nphy_get_core_power_info_r4_r10(sc, v, c)); + else + return (bwn_nphy_get_core_power_info_r11(sc, v, c)); +} Property changes on: head/sys/gnu/dev/bwn/phy_n/if_bwn_phy_n_sprom.c ___________________________________________________________________ Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:keywords ## -0,0 +1 ## +FreeBSD=%H \ No newline at end of property Added: svn:mime-type ## -0,0 +1 ## +text/plain \ No newline at end of property Index: head/sys/gnu/dev/bwn/phy_n/if_bwn_phy_n_sprom.h =================================================================== --- head/sys/gnu/dev/bwn/phy_n/if_bwn_phy_n_sprom.h (nonexistent) +++ head/sys/gnu/dev/bwn/phy_n/if_bwn_phy_n_sprom.h (revision 328912) @@ -0,0 +1,56 @@ +/*- + * SPDX-License-Identifier: BSD-2-Clause + * + * Copyright (c) 2017 The FreeBSD Foundation + * Copyright (c) 2016 Landon J. Fuller + * Copyright (c) 2007 Bruce M. Simpson. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * $FreeBSD$ + */ + +#ifndef _IF_BWN_PHY_N_SPROM_H_ +#define _IF_BWN_PHY_N_SPROM_H_ + +struct bwn_mac; + +#define BWN_NPHY_NUM_CORE_PWR 4 + +struct bwn_phy_n_core_pwr_info { + uint8_t itssi_2g; + uint8_t itssi_5g; + uint8_t maxpwr_2g; + uint8_t maxpwr_5gl; + uint8_t maxpwr_5g; + uint8_t maxpwr_5gh; + int16_t pa_2g[3]; + int16_t pa_5gl[4]; + int16_t pa_5g[4]; + int16_t pa_5gh[4]; +}; + +int bwn_nphy_get_core_power_info(struct bwn_mac *mac, int core, + struct bwn_phy_n_core_pwr_info *c); + +#endif /* _IF_BWN_PHY_N_SPROM_H_ */ Property changes on: head/sys/gnu/dev/bwn/phy_n/if_bwn_phy_n_sprom.h ___________________________________________________________________ Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:keywords ## -0,0 +1 ## +FreeBSD=%H \ No newline at end of property Added: svn:mime-type ## -0,0 +1 ## +text/plain \ No newline at end of property Index: head/sys/gnu/dev/bwn/phy_n/if_bwn_phy_n_tables.c =================================================================== --- head/sys/gnu/dev/bwn/phy_n/if_bwn_phy_n_tables.c (revision 328911) +++ head/sys/gnu/dev/bwn/phy_n/if_bwn_phy_n_tables.c (revision 328912) @@ -1,3962 +1,4005 @@ /* Broadcom B43 wireless driver IEEE 802.11n PHY data tables Copyright (c) 2008 Michael Buesch Copyright (c) 2010 RafaÅ‚ MiÅ‚ecki This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 2 of the License, or (at your option) any later version. This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with this program; see the file COPYING. If not, write to the Free Software Foundation, Inc., 51 Franklin Steet, Fifth Floor, Boston, MA 02110-1301, USA. */ #include __FBSDID("$FreeBSD$"); /* * The Broadcom Wireless LAN controller driver. */ #include "opt_wlan.h" #include "opt_bwn.h" #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include +#include +#include + #include #include #include #include #include #include #include +#include "bhnd_nvram_map.h" + static const uint8_t bwn_ntab_adjustpower0[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, }; static const uint8_t bwn_ntab_adjustpower1[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, }; static const uint16_t bwn_ntab_bdi[] = { 0x0070, 0x0126, 0x012C, 0x0246, 0x048D, 0x04D2, }; static const uint32_t bwn_ntab_channelest[] = { 0x44444444, 0x44444444, 0x44444444, 0x44444444, 0x44444444, 0x44444444, 0x44444444, 0x44444444, 0x10101010, 0x10101010, 0x10101010, 0x10101010, 0x10101010, 0x10101010, 0x10101010, 0x10101010, 0x44444444, 0x44444444, 0x44444444, 0x44444444, 0x44444444, 0x44444444, 0x44444444, 0x44444444, 0x10101010, 0x10101010, 0x10101010, 0x10101010, 0x10101010, 0x10101010, 0x10101010, 0x10101010, 0x44444444, 0x44444444, 0x44444444, 0x44444444, 0x44444444, 0x44444444, 0x44444444, 0x44444444, 0x44444444, 0x44444444, 0x44444444, 0x44444444, 0x44444444, 0x44444444, 0x44444444, 0x44444444, 0x10101010, 0x10101010, 0x10101010, 0x10101010, 0x10101010, 0x10101010, 0x10101010, 0x10101010, 0x10101010, 0x10101010, 0x10101010, 0x10101010, 0x10101010, 0x10101010, 0x10101010, 0x10101010, 0x44444444, 0x44444444, 0x44444444, 0x44444444, 0x44444444, 0x44444444, 0x44444444, 0x44444444, 0x44444444, 0x44444444, 0x44444444, 0x44444444, 0x44444444, 0x44444444, 0x44444444, 0x44444444, 0x10101010, 0x10101010, 0x10101010, 0x10101010, 0x10101010, 0x10101010, 0x10101010, 0x10101010, 0x10101010, 0x10101010, 0x10101010, 0x10101010, 0x10101010, 0x10101010, 0x10101010, 0x10101010, }; static const uint8_t bwn_ntab_estimatepowerlt0[] = { 0x50, 0x4F, 0x4E, 0x4D, 0x4C, 0x4B, 0x4A, 0x49, 0x48, 0x47, 0x46, 0x45, 0x44, 0x43, 0x42, 0x41, 0x40, 0x3F, 0x3E, 0x3D, 0x3C, 0x3B, 0x3A, 0x39, 0x38, 0x37, 0x36, 0x35, 0x34, 0x33, 0x32, 0x31, 0x30, 0x2F, 0x2E, 0x2D, 0x2C, 0x2B, 0x2A, 0x29, 0x28, 0x27, 0x26, 0x25, 0x24, 0x23, 0x22, 0x21, 0x20, 0x1F, 0x1E, 0x1D, 0x1C, 0x1B, 0x1A, 0x19, 0x18, 0x17, 0x16, 0x15, 0x14, 0x13, 0x12, 0x11, }; static const uint8_t bwn_ntab_estimatepowerlt1[] = { 0x50, 0x4F, 0x4E, 0x4D, 0x4C, 0x4B, 0x4A, 0x49, 0x48, 0x47, 0x46, 0x45, 0x44, 0x43, 0x42, 0x41, 0x40, 0x3F, 0x3E, 0x3D, 0x3C, 0x3B, 0x3A, 0x39, 0x38, 0x37, 0x36, 0x35, 0x34, 0x33, 0x32, 0x31, 0x30, 0x2F, 0x2E, 0x2D, 0x2C, 0x2B, 0x2A, 0x29, 0x28, 0x27, 0x26, 0x25, 0x24, 0x23, 0x22, 0x21, 0x20, 0x1F, 0x1E, 0x1D, 0x1C, 0x1B, 0x1A, 0x19, 0x18, 0x17, 0x16, 0x15, 0x14, 0x13, 0x12, 0x11, }; static const uint8_t bwn_ntab_framelookup[] = { 0x02, 0x04, 0x14, 0x14, 0x03, 0x05, 0x16, 0x16, 0x0A, 0x0C, 0x1C, 0x1C, 0x0B, 0x0D, 0x1E, 0x1E, 0x06, 0x08, 0x18, 0x18, 0x07, 0x09, 0x1A, 0x1A, 0x0E, 0x10, 0x20, 0x28, 0x0F, 0x11, 0x22, 0x2A, }; static const uint32_t bwn_ntab_framestruct[] = { 0x08004A04, 0x00100000, 0x01000A05, 0x00100020, 0x09804506, 0x00100030, 0x09804507, 0x00100030, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x08004A0C, 0x00100004, 0x01000A0D, 0x00100024, 0x0980450E, 0x00100034, 0x0980450F, 0x00100034, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000A04, 0x00100000, 0x11008A05, 0x00100020, 0x1980C506, 0x00100030, 0x21810506, 0x00100030, 0x21810506, 0x00100030, 0x01800504, 0x00100030, 0x11808505, 0x00100030, 0x29814507, 0x01100030, 0x00000A04, 0x00100000, 0x11008A05, 0x00100020, 0x21810506, 0x00100030, 0x21810506, 0x00100030, 0x29814507, 0x01100030, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000A0C, 0x00100008, 0x11008A0D, 0x00100028, 0x1980C50E, 0x00100038, 0x2181050E, 0x00100038, 0x2181050E, 0x00100038, 0x0180050C, 0x00100038, 0x1180850D, 0x00100038, 0x2981450F, 0x01100038, 0x00000A0C, 0x00100008, 0x11008A0D, 0x00100028, 0x2181050E, 0x00100038, 0x2181050E, 0x00100038, 0x2981450F, 0x01100038, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x08004A04, 0x00100000, 0x01000A05, 0x00100020, 0x1980C506, 0x00100030, 0x1980C506, 0x00100030, 0x11808504, 0x00100030, 0x3981CA05, 0x00100030, 0x29814507, 0x01100030, 0x00000000, 0x00000000, 0x10008A04, 0x00100000, 0x3981CA05, 0x00100030, 0x1980C506, 0x00100030, 0x29814507, 0x01100030, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x08004A0C, 0x00100008, 0x01000A0D, 0x00100028, 0x1980C50E, 0x00100038, 0x1980C50E, 0x00100038, 0x1180850C, 0x00100038, 0x3981CA0D, 0x00100038, 0x2981450F, 0x01100038, 0x00000000, 0x00000000, 0x10008A0C, 0x00100008, 0x3981CA0D, 0x00100038, 0x1980C50E, 0x00100038, 0x2981450F, 0x01100038, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x40021404, 0x00100000, 0x02001405, 0x00100040, 0x0B004A06, 0x01900060, 0x13008A06, 0x01900060, 0x13008A06, 0x01900060, 0x43020A04, 0x00100060, 0x1B00CA05, 0x00100060, 0x23010A07, 0x01500060, 0x40021404, 0x00100000, 0x1A00D405, 0x00100040, 0x13008A06, 0x01900060, 0x13008A06, 0x01900060, 0x23010A07, 0x01500060, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x4002140C, 0x00100010, 0x0200140D, 0x00100050, 0x0B004A0E, 0x01900070, 0x13008A0E, 0x01900070, 0x13008A0E, 0x01900070, 0x43020A0C, 0x00100070, 0x1B00CA0D, 0x00100070, 0x23010A0F, 0x01500070, 0x4002140C, 0x00100010, 0x1A00D40D, 0x00100050, 0x13008A0E, 0x01900070, 0x13008A0E, 0x01900070, 0x23010A0F, 0x01500070, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x50029404, 0x00100000, 0x32019405, 0x00100040, 0x0B004A06, 0x01900060, 0x0B004A06, 0x01900060, 0x5B02CA04, 0x00100060, 0x3B01D405, 0x00100060, 0x23010A07, 0x01500060, 0x00000000, 0x00000000, 0x5802D404, 0x00100000, 0x3B01D405, 0x00100060, 0x0B004A06, 0x01900060, 0x23010A07, 0x01500060, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x5002940C, 0x00100010, 0x3201940D, 0x00100050, 0x0B004A0E, 0x01900070, 0x0B004A0E, 0x01900070, 0x5B02CA0C, 0x00100070, 0x3B01D40D, 0x00100070, 0x23010A0F, 0x01500070, 0x00000000, 0x00000000, 0x5802D40C, 0x00100010, 0x3B01D40D, 0x00100070, 0x0B004A0E, 0x01900070, 0x23010A0F, 0x01500070, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x40021404, 0x000F4800, 0x62031405, 0x00100040, 0x53028A06, 0x01900060, 0x53028A07, 0x01900060, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x4002140C, 0x000F4808, 0x6203140D, 0x00100048, 0x53028A0E, 0x01900068, 0x53028A0F, 0x01900068, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000A0C, 0x00100004, 0x11008A0D, 0x00100024, 0x1980C50E, 0x00100034, 0x2181050E, 0x00100034, 0x2181050E, 0x00100034, 0x0180050C, 0x00100038, 0x1180850D, 0x00100038, 0x1181850D, 0x00100038, 0x2981450F, 0x01100038, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000A0C, 0x00100008, 0x11008A0D, 0x00100028, 0x2181050E, 0x00100038, 0x2181050E, 0x00100038, 0x1181850D, 0x00100038, 0x2981450F, 0x01100038, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x08004A04, 0x00100000, 0x01000A05, 0x00100020, 0x0180C506, 0x00100030, 0x0180C506, 0x00100030, 0x2180C50C, 0x00100030, 0x49820A0D, 0x0016A130, 0x41824A0D, 0x0016A130, 0x2981450F, 0x01100030, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x2000CA0C, 0x00100000, 0x49820A0D, 0x0016A130, 0x1980C50E, 0x00100030, 0x41824A0D, 0x0016A130, 0x2981450F, 0x01100030, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x4002140C, 0x00100008, 0x0200140D, 0x00100048, 0x0B004A0E, 0x01900068, 0x13008A0E, 0x01900068, 0x13008A0E, 0x01900068, 0x43020A0C, 0x00100070, 0x1B00CA0D, 0x00100070, 0x1B014A0D, 0x00100070, 0x23010A0F, 0x01500070, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x4002140C, 0x00100010, 0x1A00D40D, 0x00100050, 0x13008A0E, 0x01900070, 0x13008A0E, 0x01900070, 0x1B014A0D, 0x00100070, 0x23010A0F, 0x01500070, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x50029404, 0x00100000, 0x32019405, 0x00100040, 0x03004A06, 0x01900060, 0x03004A06, 0x01900060, 0x6B030A0C, 0x00100060, 0x4B02140D, 0x0016A160, 0x4302540D, 0x0016A160, 0x23010A0F, 0x01500060, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x6B03140C, 0x00100060, 0x4B02140D, 0x0016A160, 0x0B004A0E, 0x01900060, 0x4302540D, 0x0016A160, 0x23010A0F, 0x01500060, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x40021404, 0x00100000, 0x1A00D405, 0x00100040, 0x53028A06, 0x01900060, 0x5B02CA06, 0x01900060, 0x5B02CA06, 0x01900060, 0x43020A04, 0x00100060, 0x1B00CA05, 0x00100060, 0x53028A07, 0x0190C060, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x4002140C, 0x00100010, 0x1A00D40D, 0x00100050, 0x53028A0E, 0x01900070, 0x5B02CA0E, 0x01900070, 0x5B02CA0E, 0x01900070, 0x43020A0C, 0x00100070, 0x1B00CA0D, 0x00100070, 0x53028A0F, 0x0190C070, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x40021404, 0x00100000, 0x1A00D405, 0x00100040, 0x5B02CA06, 0x01900060, 0x5B02CA06, 0x01900060, 0x53028A07, 0x0190C060, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x4002140C, 0x00100010, 0x1A00D40D, 0x00100050, 0x5B02CA0E, 0x01900070, 0x5B02CA0E, 0x01900070, 0x53028A0F, 0x0190C070, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, }; static const uint32_t bwn_ntab_gainctl0[] = { 0x03CC2B44, 0x03CC2B42, 0x03CC2B40, 0x03CC2B3E, 0x03CC2B3D, 0x03CC2B3B, 0x03C82B44, 0x03C82B42, 0x03C82B40, 0x03C82B3E, 0x03C82B3D, 0x03C82B3B, 0x03C82B39, 0x03C82B38, 0x03C82B36, 0x03C82B34, 0x03C42B44, 0x03C42B42, 0x03C42B40, 0x03C42B3E, 0x03C42B3D, 0x03C42B3B, 0x03C42B39, 0x03C42B38, 0x03C42B36, 0x03C42B34, 0x03C42B33, 0x03C42B32, 0x03C42B30, 0x03C42B2F, 0x03C42B2D, 0x03C02B44, 0x03C02B42, 0x03C02B40, 0x03C02B3E, 0x03C02B3D, 0x03C02B3B, 0x03C02B39, 0x03C02B38, 0x03C02B36, 0x03C02B34, 0x03B02B44, 0x03B02B42, 0x03B02B40, 0x03B02B3E, 0x03B02B3D, 0x03B02B3B, 0x03B02B39, 0x03B02B38, 0x03B02B36, 0x03B02B34, 0x03B02B33, 0x03B02B32, 0x03B02B30, 0x03B02B2F, 0x03B02B2D, 0x03A02B44, 0x03A02B42, 0x03A02B40, 0x03A02B3E, 0x03A02B3D, 0x03A02B3B, 0x03A02B39, 0x03A02B38, 0x03A02B36, 0x03A02B34, 0x03902B44, 0x03902B42, 0x03902B40, 0x03902B3E, 0x03902B3D, 0x03902B3B, 0x03902B39, 0x03902B38, 0x03902B36, 0x03902B34, 0x03902B33, 0x03902B32, 0x03902B30, 0x03802B44, 0x03802B42, 0x03802B40, 0x03802B3E, 0x03802B3D, 0x03802B3B, 0x03802B39, 0x03802B38, 0x03802B36, 0x03802B34, 0x03802B33, 0x03802B32, 0x03802B30, 0x03802B2F, 0x03802B2D, 0x03802B2C, 0x03802B2B, 0x03802B2A, 0x03802B29, 0x03802B27, 0x03802B26, 0x03802B25, 0x03802B24, 0x03802B23, 0x03802B22, 0x03802B21, 0x03802B20, 0x03802B1F, 0x03802B1E, 0x03802B1E, 0x03802B1D, 0x03802B1C, 0x03802B1B, 0x03802B1A, 0x03802B1A, 0x03802B19, 0x03802B18, 0x03802B18, 0x03802B18, 0x03802B18, 0x03802B18, 0x03802B18, 0x03802B18, 0x03802B18, 0x03802B18, 0x03802B18, 0x03802B18, 0x03802B18, 0x00002B00, }; static const uint32_t bwn_ntab_gainctl1[] = { 0x03CC2B44, 0x03CC2B42, 0x03CC2B40, 0x03CC2B3E, 0x03CC2B3D, 0x03CC2B3B, 0x03C82B44, 0x03C82B42, 0x03C82B40, 0x03C82B3E, 0x03C82B3D, 0x03C82B3B, 0x03C82B39, 0x03C82B38, 0x03C82B36, 0x03C82B34, 0x03C42B44, 0x03C42B42, 0x03C42B40, 0x03C42B3E, 0x03C42B3D, 0x03C42B3B, 0x03C42B39, 0x03C42B38, 0x03C42B36, 0x03C42B34, 0x03C42B33, 0x03C42B32, 0x03C42B30, 0x03C42B2F, 0x03C42B2D, 0x03C02B44, 0x03C02B42, 0x03C02B40, 0x03C02B3E, 0x03C02B3D, 0x03C02B3B, 0x03C02B39, 0x03C02B38, 0x03C02B36, 0x03C02B34, 0x03B02B44, 0x03B02B42, 0x03B02B40, 0x03B02B3E, 0x03B02B3D, 0x03B02B3B, 0x03B02B39, 0x03B02B38, 0x03B02B36, 0x03B02B34, 0x03B02B33, 0x03B02B32, 0x03B02B30, 0x03B02B2F, 0x03B02B2D, 0x03A02B44, 0x03A02B42, 0x03A02B40, 0x03A02B3E, 0x03A02B3D, 0x03A02B3B, 0x03A02B39, 0x03A02B38, 0x03A02B36, 0x03A02B34, 0x03902B44, 0x03902B42, 0x03902B40, 0x03902B3E, 0x03902B3D, 0x03902B3B, 0x03902B39, 0x03902B38, 0x03902B36, 0x03902B34, 0x03902B33, 0x03902B32, 0x03902B30, 0x03802B44, 0x03802B42, 0x03802B40, 0x03802B3E, 0x03802B3D, 0x03802B3B, 0x03802B39, 0x03802B38, 0x03802B36, 0x03802B34, 0x03802B33, 0x03802B32, 0x03802B30, 0x03802B2F, 0x03802B2D, 0x03802B2C, 0x03802B2B, 0x03802B2A, 0x03802B29, 0x03802B27, 0x03802B26, 0x03802B25, 0x03802B24, 0x03802B23, 0x03802B22, 0x03802B21, 0x03802B20, 0x03802B1F, 0x03802B1E, 0x03802B1E, 0x03802B1D, 0x03802B1C, 0x03802B1B, 0x03802B1A, 0x03802B1A, 0x03802B19, 0x03802B18, 0x03802B18, 0x03802B18, 0x03802B18, 0x03802B18, 0x03802B18, 0x03802B18, 0x03802B18, 0x03802B18, 0x03802B18, 0x03802B18, 0x03802B18, 0x00002B00, }; static const uint32_t bwn_ntab_intlevel[] = { 0x00802070, 0x0671188D, 0x0A60192C, 0x0A300E46, 0x00C1188D, 0x080024D2, 0x00000070, }; static const uint32_t bwn_ntab_iqlt0[] = { 0x0000007F, 0x0000007F, 0x0000007F, 0x0000007F, 0x0000007F, 0x0000007F, 0x0000007F, 0x0000007F, 0x0000007F, 0x0000007F, 0x0000007F, 0x0000007F, 0x0000007F, 0x0000007F, 0x0000007F, 0x0000007F, 0x0000007F, 0x0000007F, 0x0000007F, 0x0000007F, 0x0000007F, 0x0000007F, 0x0000007F, 0x0000007F, 0x0000007F, 0x0000007F, 0x0000007F, 0x0000007F, 0x0000007F, 0x0000007F, 0x0000007F, 0x0000007F, 0x0000007F, 0x0000007F, 0x0000007F, 0x0000007F, 0x0000007F, 0x0000007F, 0x0000007F, 0x0000007F, 0x0000007F, 0x0000007F, 0x0000007F, 0x0000007F, 0x0000007F, 0x0000007F, 0x0000007F, 0x0000007F, 0x0000007F, 0x0000007F, 0x0000007F, 0x0000007F, 0x0000007F, 0x0000007F, 0x0000007F, 0x0000007F, 0x0000007F, 0x0000007F, 0x0000007F, 0x0000007F, 0x0000007F, 0x0000007F, 0x0000007F, 0x0000007F, 0x0000007F, 0x0000007F, 0x0000007F, 0x0000007F, 0x0000007F, 0x0000007F, 0x0000007F, 0x0000007F, 0x0000007F, 0x0000007F, 0x0000007F, 0x0000007F, 0x0000007F, 0x0000007F, 0x0000007F, 0x0000007F, 0x0000007F, 0x0000007F, 0x0000007F, 0x0000007F, 0x0000007F, 0x0000007F, 0x0000007F, 0x0000007F, 0x0000007F, 0x0000007F, 0x0000007F, 0x0000007F, 0x0000007F, 0x0000007F, 0x0000007F, 0x0000007F, 0x0000007F, 0x0000007F, 0x0000007F, 0x0000007F, 0x0000007F, 0x0000007F, 0x0000007F, 0x0000007F, 0x0000007F, 0x0000007F, 0x0000007F, 0x0000007F, 0x0000007F, 0x0000007F, 0x0000007F, 0x0000007F, 0x0000007F, 0x0000007F, 0x0000007F, 0x0000007F, 0x0000007F, 0x0000007F, 0x0000007F, 0x0000007F, 0x0000007F, 0x0000007F, 0x0000007F, 0x0000007F, 0x0000007F, 0x0000007F, 0x0000007F, 0x0000007F, }; static const uint32_t bwn_ntab_iqlt1[] = { 0x0000007F, 0x0000007F, 0x0000007F, 0x0000007F, 0x0000007F, 0x0000007F, 0x0000007F, 0x0000007F, 0x0000007F, 0x0000007F, 0x0000007F, 0x0000007F, 0x0000007F, 0x0000007F, 0x0000007F, 0x0000007F, 0x0000007F, 0x0000007F, 0x0000007F, 0x0000007F, 0x0000007F, 0x0000007F, 0x0000007F, 0x0000007F, 0x0000007F, 0x0000007F, 0x0000007F, 0x0000007F, 0x0000007F, 0x0000007F, 0x0000007F, 0x0000007F, 0x0000007F, 0x0000007F, 0x0000007F, 0x0000007F, 0x0000007F, 0x0000007F, 0x0000007F, 0x0000007F, 0x0000007F, 0x0000007F, 0x0000007F, 0x0000007F, 0x0000007F, 0x0000007F, 0x0000007F, 0x0000007F, 0x0000007F, 0x0000007F, 0x0000007F, 0x0000007F, 0x0000007F, 0x0000007F, 0x0000007F, 0x0000007F, 0x0000007F, 0x0000007F, 0x0000007F, 0x0000007F, 0x0000007F, 0x0000007F, 0x0000007F, 0x0000007F, 0x0000007F, 0x0000007F, 0x0000007F, 0x0000007F, 0x0000007F, 0x0000007F, 0x0000007F, 0x0000007F, 0x0000007F, 0x0000007F, 0x0000007F, 0x0000007F, 0x0000007F, 0x0000007F, 0x0000007F, 0x0000007F, 0x0000007F, 0x0000007F, 0x0000007F, 0x0000007F, 0x0000007F, 0x0000007F, 0x0000007F, 0x0000007F, 0x0000007F, 0x0000007F, 0x0000007F, 0x0000007F, 0x0000007F, 0x0000007F, 0x0000007F, 0x0000007F, 0x0000007F, 0x0000007F, 0x0000007F, 0x0000007F, 0x0000007F, 0x0000007F, 0x0000007F, 0x0000007F, 0x0000007F, 0x0000007F, 0x0000007F, 0x0000007F, 0x0000007F, 0x0000007F, 0x0000007F, 0x0000007F, 0x0000007F, 0x0000007F, 0x0000007F, 0x0000007F, 0x0000007F, 0x0000007F, 0x0000007F, 0x0000007F, 0x0000007F, 0x0000007F, 0x0000007F, 0x0000007F, 0x0000007F, 0x0000007F, 0x0000007F, 0x0000007F, }; static const uint16_t bwn_ntab_loftlt0[] = { 0x0000, 0x0101, 0x0002, 0x0103, 0x0000, 0x0101, 0x0002, 0x0103, 0x0000, 0x0101, 0x0002, 0x0103, 0x0000, 0x0101, 0x0002, 0x0103, 0x0000, 0x0101, 0x0002, 0x0103, 0x0000, 0x0101, 0x0002, 0x0103, 0x0000, 0x0101, 0x0002, 0x0103, 0x0000, 0x0101, 0x0002, 0x0103, 0x0000, 0x0101, 0x0002, 0x0103, 0x0000, 0x0101, 0x0002, 0x0103, 0x0000, 0x0101, 0x0002, 0x0103, 0x0000, 0x0101, 0x0002, 0x0103, 0x0000, 0x0101, 0x0002, 0x0103, 0x0000, 0x0101, 0x0002, 0x0103, 0x0000, 0x0101, 0x0002, 0x0103, 0x0000, 0x0101, 0x0002, 0x0103, 0x0000, 0x0101, 0x0002, 0x0103, 0x0000, 0x0101, 0x0002, 0x0103, 0x0000, 0x0101, 0x0002, 0x0103, 0x0000, 0x0101, 0x0002, 0x0103, 0x0000, 0x0101, 0x0002, 0x0103, 0x0000, 0x0101, 0x0002, 0x0103, 0x0000, 0x0101, 0x0002, 0x0103, 0x0000, 0x0101, 0x0002, 0x0103, 0x0000, 0x0101, 0x0002, 0x0103, 0x0000, 0x0101, 0x0002, 0x0103, 0x0000, 0x0101, 0x0002, 0x0103, 0x0000, 0x0101, 0x0002, 0x0103, 0x0000, 0x0101, 0x0002, 0x0103, 0x0000, 0x0101, 0x0002, 0x0103, 0x0000, 0x0101, 0x0002, 0x0103, 0x0000, 0x0101, 0x0002, 0x0103, }; static const uint16_t bwn_ntab_loftlt1[] = { 0x0000, 0x0101, 0x0002, 0x0103, 0x0000, 0x0101, 0x0002, 0x0103, 0x0000, 0x0101, 0x0002, 0x0103, 0x0000, 0x0101, 0x0002, 0x0103, 0x0000, 0x0101, 0x0002, 0x0103, 0x0000, 0x0101, 0x0002, 0x0103, 0x0000, 0x0101, 0x0002, 0x0103, 0x0000, 0x0101, 0x0002, 0x0103, 0x0000, 0x0101, 0x0002, 0x0103, 0x0000, 0x0101, 0x0002, 0x0103, 0x0000, 0x0101, 0x0002, 0x0103, 0x0000, 0x0101, 0x0002, 0x0103, 0x0000, 0x0101, 0x0002, 0x0103, 0x0000, 0x0101, 0x0002, 0x0103, 0x0000, 0x0101, 0x0002, 0x0103, 0x0000, 0x0101, 0x0002, 0x0103, 0x0000, 0x0101, 0x0002, 0x0103, 0x0000, 0x0101, 0x0002, 0x0103, 0x0000, 0x0101, 0x0002, 0x0103, 0x0000, 0x0101, 0x0002, 0x0103, 0x0000, 0x0101, 0x0002, 0x0103, 0x0000, 0x0101, 0x0002, 0x0103, 0x0000, 0x0101, 0x0002, 0x0103, 0x0000, 0x0101, 0x0002, 0x0103, 0x0000, 0x0101, 0x0002, 0x0103, 0x0000, 0x0101, 0x0002, 0x0103, 0x0000, 0x0101, 0x0002, 0x0103, 0x0000, 0x0101, 0x0002, 0x0103, 0x0000, 0x0101, 0x0002, 0x0103, 0x0000, 0x0101, 0x0002, 0x0103, 0x0000, 0x0101, 0x0002, 0x0103, 0x0000, 0x0101, 0x0002, 0x0103, }; static const uint8_t bwn_ntab_mcs[] = { 0x00, 0x08, 0x0A, 0x10, 0x12, 0x19, 0x1A, 0x1C, 0x40, 0x48, 0x4A, 0x50, 0x52, 0x59, 0x5A, 0x5C, 0x80, 0x88, 0x8A, 0x90, 0x92, 0x99, 0x9A, 0x9C, 0xC0, 0xC8, 0xCA, 0xD0, 0xD2, 0xD9, 0xDA, 0xDC, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x02, 0x04, 0x08, 0x09, 0x0A, 0x0C, 0x10, 0x11, 0x12, 0x14, 0x18, 0x19, 0x1A, 0x1C, 0x20, 0x21, 0x22, 0x24, 0x40, 0x41, 0x42, 0x44, 0x48, 0x49, 0x4A, 0x4C, 0x50, 0x51, 0x52, 0x54, 0x58, 0x59, 0x5A, 0x5C, 0x60, 0x61, 0x62, 0x64, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, }; static const uint32_t bwn_ntab_noisevar10[] = { 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D, }; static const uint32_t bwn_ntab_noisevar11[] = { 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D, 0x020C020C, 0x0000014D, }; static const uint16_t bwn_ntab_pilot[] = { 0xFF08, 0xFF08, 0xFF08, 0xFF08, 0xFF08, 0xFF08, 0xFF08, 0xFF08, 0x80D5, 0x80D5, 0x80D5, 0x80D5, 0x80D5, 0x80D5, 0x80D5, 0x80D5, 0xFF0A, 0xFF82, 0xFFA0, 0xFF28, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFF82, 0xFFA0, 0xFF28, 0xFF0A, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xF83F, 0xFA1F, 0xFA97, 0xFAB5, 0xF2BD, 0xF0BF, 0xFFFF, 0xFFFF, 0xF017, 0xF815, 0xF215, 0xF095, 0xF035, 0xF01D, 0xFFFF, 0xFFFF, 0xFF08, 0xFF02, 0xFF80, 0xFF20, 0xFF08, 0xFF02, 0xFF80, 0xFF20, 0xF01F, 0xF817, 0xFA15, 0xF295, 0xF0B5, 0xF03D, 0xFFFF, 0xFFFF, 0xF82A, 0xFA0A, 0xFA82, 0xFAA0, 0xF2A8, 0xF0AA, 0xFFFF, 0xFFFF, 0xF002, 0xF800, 0xF200, 0xF080, 0xF020, 0xF008, 0xFFFF, 0xFFFF, 0xF00A, 0xF802, 0xFA00, 0xF280, 0xF0A0, 0xF028, 0xFFFF, 0xFFFF, }; static const uint32_t bwn_ntab_pilotlt[] = { 0x76540123, 0x62407351, 0x76543201, 0x76540213, 0x76540123, 0x76430521, }; static const uint32_t bwn_ntab_tdi20a0[] = { 0x00091226, 0x000A1429, 0x000B56AD, 0x000C58B0, 0x000D5AB3, 0x000E9CB6, 0x000F9EBA, 0x0000C13D, 0x00020301, 0x00030504, 0x00040708, 0x0005090B, 0x00064B8E, 0x00095291, 0x000A5494, 0x000B9718, 0x000C9927, 0x000D9B2A, 0x000EDD2E, 0x000FDF31, 0x000101B4, 0x000243B7, 0x000345BB, 0x000447BE, 0x00058982, 0x00068C05, 0x00099309, 0x000A950C, 0x000BD78F, 0x000CD992, 0x000DDB96, 0x000F1D99, 0x00005FA8, 0x0001422C, 0x0002842F, 0x00038632, 0x00048835, 0x0005CA38, 0x0006CCBC, 0x0009D3BF, 0x000B1603, 0x000C1806, 0x000D1A0A, 0x000E1C0D, 0x000F5E10, 0x00008093, 0x00018297, 0x0002C49A, 0x0003C680, 0x0004C880, 0x00060B00, 0x00070D00, 0x00000000, 0x00000000, 0x00000000, }; static const uint32_t bwn_ntab_tdi20a1[] = { 0x00014B26, 0x00028D29, 0x000393AD, 0x00049630, 0x0005D833, 0x0006DA36, 0x00099C3A, 0x000A9E3D, 0x000BC081, 0x000CC284, 0x000DC488, 0x000F068B, 0x0000488E, 0x00018B91, 0x0002D214, 0x0003D418, 0x0004D6A7, 0x000618AA, 0x00071AAE, 0x0009DCB1, 0x000B1EB4, 0x000C0137, 0x000D033B, 0x000E053E, 0x000F4702, 0x00008905, 0x00020C09, 0x0003128C, 0x0004148F, 0x00051712, 0x00065916, 0x00091B19, 0x000A1D28, 0x000B5F2C, 0x000C41AF, 0x000D43B2, 0x000E85B5, 0x000F87B8, 0x0000C9BC, 0x00024CBF, 0x00035303, 0x00045506, 0x0005978A, 0x0006998D, 0x00095B90, 0x000A5D93, 0x000B9F97, 0x000C821A, 0x000D8400, 0x000EC600, 0x000FC800, 0x00010A00, 0x00000000, 0x00000000, 0x00000000, }; static const uint32_t bwn_ntab_tdi40a0[] = { 0x0011A346, 0x00136CCF, 0x0014F5D9, 0x001641E2, 0x0017CB6B, 0x00195475, 0x001B2383, 0x001CAD0C, 0x001E7616, 0x0000821F, 0x00020BA8, 0x0003D4B2, 0x00056447, 0x00072DD0, 0x0008B6DA, 0x000A02E3, 0x000B8C6C, 0x000D15F6, 0x0011E484, 0x0013AE0D, 0x00153717, 0x00168320, 0x00180CA9, 0x00199633, 0x001B6548, 0x001CEED1, 0x001EB7DB, 0x0000C3E4, 0x00024D6D, 0x000416F7, 0x0005A585, 0x00076F0F, 0x0008F818, 0x000A4421, 0x000BCDAB, 0x000D9734, 0x00122649, 0x0013EFD2, 0x001578DC, 0x0016C4E5, 0x00184E6E, 0x001A17F8, 0x001BA686, 0x001D3010, 0x001EF999, 0x00010522, 0x00028EAC, 0x00045835, 0x0005E74A, 0x0007B0D3, 0x00093A5D, 0x000A85E6, 0x000C0F6F, 0x000DD8F9, 0x00126787, 0x00143111, 0x0015BA9A, 0x00170623, 0x00188FAD, 0x001A5936, 0x001BE84B, 0x001DB1D4, 0x001F3B5E, 0x000146E7, 0x00031070, 0x000499FA, 0x00062888, 0x0007F212, 0x00097B9B, 0x000AC7A4, 0x000C50AE, 0x000E1A37, 0x0012A94C, 0x001472D5, 0x0015FC5F, 0x00174868, 0x0018D171, 0x001A9AFB, 0x001C2989, 0x001DF313, 0x001F7C9C, 0x000188A5, 0x000351AF, 0x0004DB38, 0x0006AA4D, 0x000833D7, 0x0009BD60, 0x000B0969, 0x000C9273, 0x000E5BFC, 0x00132A8A, 0x0014B414, 0x00163D9D, 0x001789A6, 0x001912B0, 0x001ADC39, 0x001C6BCE, 0x001E34D8, 0x001FBE61, 0x0001CA6A, 0x00039374, 0x00051CFD, 0x0006EC0B, 0x00087515, 0x0009FE9E, 0x000B4AA7, 0x000CD3B1, 0x000E9D3A, 0x00000000, 0x00000000, }; static const uint32_t bwn_ntab_tdi40a1[] = { 0x001EDB36, 0x000129CA, 0x0002B353, 0x00047CDD, 0x0005C8E6, 0x000791EF, 0x00091BF9, 0x000AAA07, 0x000C3391, 0x000DFD1A, 0x00120923, 0x0013D22D, 0x00155C37, 0x0016EACB, 0x00187454, 0x001A3DDE, 0x001B89E7, 0x001D12F0, 0x001F1CFA, 0x00016B88, 0x00033492, 0x0004BE1B, 0x00060A24, 0x0007D32E, 0x00095D38, 0x000AEC4C, 0x000C7555, 0x000E3EDF, 0x00124AE8, 0x001413F1, 0x0015A37B, 0x00172C89, 0x0018B593, 0x001A419C, 0x001BCB25, 0x001D942F, 0x001F63B9, 0x0001AD4D, 0x00037657, 0x0004C260, 0x00068BE9, 0x000814F3, 0x0009A47C, 0x000B2D8A, 0x000CB694, 0x000E429D, 0x00128C26, 0x001455B0, 0x0015E4BA, 0x00176E4E, 0x0018F758, 0x001A8361, 0x001C0CEA, 0x001DD674, 0x001FA57D, 0x0001EE8B, 0x0003B795, 0x0005039E, 0x0006CD27, 0x000856B1, 0x0009E5C6, 0x000B6F4F, 0x000CF859, 0x000E8462, 0x00130DEB, 0x00149775, 0x00162603, 0x0017AF8C, 0x00193896, 0x001AC49F, 0x001C4E28, 0x001E17B2, 0x0000A6C7, 0x00023050, 0x0003F9DA, 0x00054563, 0x00070EEC, 0x00089876, 0x000A2704, 0x000BB08D, 0x000D3A17, 0x001185A0, 0x00134F29, 0x0014D8B3, 0x001667C8, 0x0017F151, 0x00197ADB, 0x001B0664, 0x001C8FED, 0x001E5977, 0x0000E805, 0x0002718F, 0x00043B18, 0x000586A1, 0x0007502B, 0x0008D9B4, 0x000A68C9, 0x000BF252, 0x000DBBDC, 0x0011C7E5, 0x001390EE, 0x00151A78, 0x0016A906, 0x00183290, 0x0019BC19, 0x001B4822, 0x001CD12C, 0x001E9AB5, 0x00000000, 0x00000000, }; static const uint32_t bwn_ntab_tdtrn[] = { 0x061C061C, 0x0050EE68, 0xF592FE36, 0xFE5212F6, 0x00000C38, 0xFE5212F6, 0xF592FE36, 0x0050EE68, 0x061C061C, 0xEE680050, 0xFE36F592, 0x12F6FE52, 0x0C380000, 0x12F6FE52, 0xFE36F592, 0xEE680050, 0x061C061C, 0x0050EE68, 0xF592FE36, 0xFE5212F6, 0x00000C38, 0xFE5212F6, 0xF592FE36, 0x0050EE68, 0x061C061C, 0xEE680050, 0xFE36F592, 0x12F6FE52, 0x0C380000, 0x12F6FE52, 0xFE36F592, 0xEE680050, 0x05E305E3, 0x004DEF0C, 0xF5F3FE47, 0xFE611246, 0x00000BC7, 0xFE611246, 0xF5F3FE47, 0x004DEF0C, 0x05E305E3, 0xEF0C004D, 0xFE47F5F3, 0x1246FE61, 0x0BC70000, 0x1246FE61, 0xFE47F5F3, 0xEF0C004D, 0x05E305E3, 0x004DEF0C, 0xF5F3FE47, 0xFE611246, 0x00000BC7, 0xFE611246, 0xF5F3FE47, 0x004DEF0C, 0x05E305E3, 0xEF0C004D, 0xFE47F5F3, 0x1246FE61, 0x0BC70000, 0x1246FE61, 0xFE47F5F3, 0xEF0C004D, 0xFA58FA58, 0xF895043B, 0xFF4C09C0, 0xFBC6FFA8, 0xFB84F384, 0x0798F6F9, 0x05760122, 0x058409F6, 0x0B500000, 0x05B7F542, 0x08860432, 0x06DDFEE7, 0xFB84F384, 0xF9D90664, 0xF7E8025C, 0x00FFF7BD, 0x05A805A8, 0xF7BD00FF, 0x025CF7E8, 0x0664F9D9, 0xF384FB84, 0xFEE706DD, 0x04320886, 0xF54205B7, 0x00000B50, 0x09F60584, 0x01220576, 0xF6F90798, 0xF384FB84, 0xFFA8FBC6, 0x09C0FF4C, 0x043BF895, 0x02D402D4, 0x07DE0270, 0xFC96079C, 0xF90AFE94, 0xFE00FF2C, 0x02D4065D, 0x092A0096, 0x0014FBB8, 0xFD2CFD2C, 0x076AFB3C, 0x0096F752, 0xF991FD87, 0xFB2C0200, 0xFEB8F960, 0x08E0FC96, 0x049802A8, 0xFD2CFD2C, 0x02A80498, 0xFC9608E0, 0xF960FEB8, 0x0200FB2C, 0xFD87F991, 0xF7520096, 0xFB3C076A, 0xFD2CFD2C, 0xFBB80014, 0x0096092A, 0x065D02D4, 0xFF2CFE00, 0xFE94F90A, 0x079CFC96, 0x027007DE, 0x02D402D4, 0x027007DE, 0x079CFC96, 0xFE94F90A, 0xFF2CFE00, 0x065D02D4, 0x0096092A, 0xFBB80014, 0xFD2CFD2C, 0xFB3C076A, 0xF7520096, 0xFD87F991, 0x0200FB2C, 0xF960FEB8, 0xFC9608E0, 0x02A80498, 0xFD2CFD2C, 0x049802A8, 0x08E0FC96, 0xFEB8F960, 0xFB2C0200, 0xF991FD87, 0x0096F752, 0x076AFB3C, 0xFD2CFD2C, 0x0014FBB8, 0x092A0096, 0x02D4065D, 0xFE00FF2C, 0xF90AFE94, 0xFC96079C, 0x07DE0270, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x062A0000, 0xFEFA0759, 0x08B80908, 0xF396FC2D, 0xF9D6045C, 0xFC4EF608, 0xF748F596, 0x07B207BF, 0x062A062A, 0xF84EF841, 0xF748F596, 0x03B209F8, 0xF9D6045C, 0x0C6A03D3, 0x08B80908, 0x0106F8A7, 0x062A0000, 0xFEFAF8A7, 0x08B8F6F8, 0xF39603D3, 0xF9D6FBA4, 0xFC4E09F8, 0xF7480A6A, 0x07B2F841, 0x062AF9D6, 0xF84E07BF, 0xF7480A6A, 0x03B2F608, 0xF9D6FBA4, 0x0C6AFC2D, 0x08B8F6F8, 0x01060759, 0x062A0000, 0xFEFA0759, 0x08B80908, 0xF396FC2D, 0xF9D6045C, 0xFC4EF608, 0xF748F596, 0x07B207BF, 0x062A062A, 0xF84EF841, 0xF748F596, 0x03B209F8, 0xF9D6045C, 0x0C6A03D3, 0x08B80908, 0x0106F8A7, 0x062A0000, 0xFEFAF8A7, 0x08B8F6F8, 0xF39603D3, 0xF9D6FBA4, 0xFC4E09F8, 0xF7480A6A, 0x07B2F841, 0x062AF9D6, 0xF84E07BF, 0xF7480A6A, 0x03B2F608, 0xF9D6FBA4, 0x0C6AFC2D, 0x08B8F6F8, 0x01060759, 0x061C061C, 0xFF30009D, 0xFFB21141, 0xFD87FB54, 0xF65DFE59, 0x02EEF99E, 0x0166F03C, 0xFFF809B6, 0x000008A4, 0x000AF42B, 0x00EFF577, 0xFA840BF2, 0xFC02FF51, 0x08260F67, 0xFFF0036F, 0x0842F9C3, 0x00000000, 0x063DF7BE, 0xFC910010, 0xF099F7DA, 0x00AF03FE, 0xF40E057C, 0x0A89FF11, 0x0BD5FFF6, 0xF75C0000, 0xF64A0008, 0x0FC4FE9A, 0x0662FD12, 0x01A709A3, 0x04AC0279, 0xEEBF004E, 0xFF6300D0, 0xF9E4F9E4, 0x00D0FF63, 0x004EEEBF, 0x027904AC, 0x09A301A7, 0xFD120662, 0xFE9A0FC4, 0x0008F64A, 0x0000F75C, 0xFFF60BD5, 0xFF110A89, 0x057CF40E, 0x03FE00AF, 0xF7DAF099, 0x0010FC91, 0xF7BE063D, 0x00000000, 0xF9C30842, 0x036FFFF0, 0x0F670826, 0xFF51FC02, 0x0BF2FA84, 0xF57700EF, 0xF42B000A, 0x08A40000, 0x09B6FFF8, 0xF03C0166, 0xF99E02EE, 0xFE59F65D, 0xFB54FD87, 0x1141FFB2, 0x009DFF30, 0x05E30000, 0xFF060705, 0x085408A0, 0xF425FC59, 0xFA1D042A, 0xFC78F67A, 0xF7ACF60E, 0x075A0766, 0x05E305E3, 0xF8A6F89A, 0xF7ACF60E, 0x03880986, 0xFA1D042A, 0x0BDB03A7, 0x085408A0, 0x00FAF8FB, 0x05E30000, 0xFF06F8FB, 0x0854F760, 0xF42503A7, 0xFA1DFBD6, 0xFC780986, 0xF7AC09F2, 0x075AF89A, 0x05E3FA1D, 0xF8A60766, 0xF7AC09F2, 0x0388F67A, 0xFA1DFBD6, 0x0BDBFC59, 0x0854F760, 0x00FA0705, 0x05E30000, 0xFF060705, 0x085408A0, 0xF425FC59, 0xFA1D042A, 0xFC78F67A, 0xF7ACF60E, 0x075A0766, 0x05E305E3, 0xF8A6F89A, 0xF7ACF60E, 0x03880986, 0xFA1D042A, 0x0BDB03A7, 0x085408A0, 0x00FAF8FB, 0x05E30000, 0xFF06F8FB, 0x0854F760, 0xF42503A7, 0xFA1DFBD6, 0xFC780986, 0xF7AC09F2, 0x075AF89A, 0x05E3FA1D, 0xF8A60766, 0xF7AC09F2, 0x0388F67A, 0xFA1DFBD6, 0x0BDBFC59, 0x0854F760, 0x00FA0705, 0xFA58FA58, 0xF8F0FE00, 0x0448073D, 0xFDC9FE46, 0xF9910258, 0x089D0407, 0xFD5CF71A, 0x02AFFDE0, 0x083E0496, 0xFF5A0740, 0xFF7AFD97, 0x00FE01F1, 0x0009082E, 0xFA94FF75, 0xFECDF8EA, 0xFFB0F693, 0xFD2CFA58, 0x0433FF16, 0xFBA405DD, 0xFA610341, 0x06A606CB, 0x0039FD2D, 0x0677FA97, 0x01FA05E0, 0xF896003E, 0x075A068B, 0x012CFC3E, 0xFA23F98D, 0xFC7CFD43, 0xFF90FC0D, 0x01C10982, 0x00C601D6, 0xFD2CFD2C, 0x01D600C6, 0x098201C1, 0xFC0DFF90, 0xFD43FC7C, 0xF98DFA23, 0xFC3E012C, 0x068B075A, 0x003EF896, 0x05E001FA, 0xFA970677, 0xFD2D0039, 0x06CB06A6, 0x0341FA61, 0x05DDFBA4, 0xFF160433, 0xFA58FD2C, 0xF693FFB0, 0xF8EAFECD, 0xFF75FA94, 0x082E0009, 0x01F100FE, 0xFD97FF7A, 0x0740FF5A, 0x0496083E, 0xFDE002AF, 0xF71AFD5C, 0x0407089D, 0x0258F991, 0xFE46FDC9, 0x073D0448, 0xFE00F8F0, 0xFD2CFD2C, 0xFCE00500, 0xFC09FDDC, 0xFE680157, 0x04C70571, 0xFC3AFF21, 0xFCD70228, 0x056D0277, 0x0200FE00, 0x0022F927, 0xFE3C032B, 0xFC44FF3C, 0x03E9FBDB, 0x04570313, 0x04C9FF5C, 0x000D03B8, 0xFA580000, 0xFBE900D2, 0xF9D0FE0B, 0x0125FDF9, 0x042501BF, 0x0328FA2B, 0xFFA902F0, 0xFA250157, 0x0200FE00, 0x03740438, 0xFF0405FD, 0x030CFE52, 0x0037FB39, 0xFF6904C5, 0x04F8FD23, 0xFD31FC1B, 0xFD2CFD2C, 0xFC1BFD31, 0xFD2304F8, 0x04C5FF69, 0xFB390037, 0xFE52030C, 0x05FDFF04, 0x04380374, 0xFE000200, 0x0157FA25, 0x02F0FFA9, 0xFA2B0328, 0x01BF0425, 0xFDF90125, 0xFE0BF9D0, 0x00D2FBE9, 0x0000FA58, 0x03B8000D, 0xFF5C04C9, 0x03130457, 0xFBDB03E9, 0xFF3CFC44, 0x032BFE3C, 0xF9270022, 0xFE000200, 0x0277056D, 0x0228FCD7, 0xFF21FC3A, 0x057104C7, 0x0157FE68, 0xFDDCFC09, 0x0500FCE0, 0xFD2CFD2C, 0x0500FCE0, 0xFDDCFC09, 0x0157FE68, 0x057104C7, 0xFF21FC3A, 0x0228FCD7, 0x0277056D, 0xFE000200, 0xF9270022, 0x032BFE3C, 0xFF3CFC44, 0xFBDB03E9, 0x03130457, 0xFF5C04C9, 0x03B8000D, 0x0000FA58, 0x00D2FBE9, 0xFE0BF9D0, 0xFDF90125, 0x01BF0425, 0xFA2B0328, 0x02F0FFA9, 0x0157FA25, 0xFE000200, 0x04380374, 0x05FDFF04, 0xFE52030C, 0xFB390037, 0x04C5FF69, 0xFD2304F8, 0xFC1BFD31, 0xFD2CFD2C, 0xFD31FC1B, 0x04F8FD23, 0xFF6904C5, 0x0037FB39, 0x030CFE52, 0xFF0405FD, 0x03740438, 0x0200FE00, 0xFA250157, 0xFFA902F0, 0x0328FA2B, 0x042501BF, 0x0125FDF9, 0xF9D0FE0B, 0xFBE900D2, 0xFA580000, 0x000D03B8, 0x04C9FF5C, 0x04570313, 0x03E9FBDB, 0xFC44FF3C, 0xFE3C032B, 0x0022F927, 0x0200FE00, 0x056D0277, 0xFCD70228, 0xFC3AFF21, 0x04C70571, 0xFE680157, 0xFC09FDDC, 0xFCE00500, 0x05A80000, 0xFF1006BE, 0x0800084A, 0xF49CFC7E, 0xFA580400, 0xFC9CF6DA, 0xF800F672, 0x0710071C, 0x05A805A8, 0xF8F0F8E4, 0xF800F672, 0x03640926, 0xFA580400, 0x0B640382, 0x0800084A, 0x00F0F942, 0x05A80000, 0xFF10F942, 0x0800F7B6, 0xF49C0382, 0xFA58FC00, 0xFC9C0926, 0xF800098E, 0x0710F8E4, 0x05A8FA58, 0xF8F0071C, 0xF800098E, 0x0364F6DA, 0xFA58FC00, 0x0B64FC7E, 0x0800F7B6, 0x00F006BE, 0x05A80000, 0xFF1006BE, 0x0800084A, 0xF49CFC7E, 0xFA580400, 0xFC9CF6DA, 0xF800F672, 0x0710071C, 0x05A805A8, 0xF8F0F8E4, 0xF800F672, 0x03640926, 0xFA580400, 0x0B640382, 0x0800084A, 0x00F0F942, 0x05A80000, 0xFF10F942, 0x0800F7B6, 0xF49C0382, 0xFA58FC00, 0xFC9C0926, 0xF800098E, 0x0710F8E4, 0x05A8FA58, 0xF8F0071C, 0xF800098E, 0x0364F6DA, 0xFA58FC00, 0x0B64FC7E, 0x0800F7B6, 0x00F006BE, }; static const uint32_t bwn_ntab_tmap[] = { 0x8A88AA80, 0x8AAAAA8A, 0x8A8A8AA8, 0x00000888, 0x88000000, 0x8A8A88AA, 0x8AA88888, 0x8888A8A8, 0xF1111110, 0x11111111, 0x11F11111, 0x00000111, 0x11000000, 0x1111F111, 0x11111111, 0x111111F1, 0x8A88AA80, 0x8AAAAA8A, 0x8A8A8AA8, 0x000AA888, 0x88880000, 0x8A8A88AA, 0x8AA88888, 0x8888A8A8, 0xA1111110, 0x11111111, 0x11C11111, 0x00000111, 0x11000000, 0x1111A111, 0x11111111, 0x111111A1, 0xA2222220, 0x22222222, 0x22C22222, 0x00000222, 0x22000000, 0x2222A222, 0x22222222, 0x222222A2, 0xF1111110, 0x11111111, 0x11F11111, 0x00011111, 0x11110000, 0x1111F111, 0x11111111, 0x111111F1, 0xA8AA88A0, 0xA88888A8, 0xA8A8A88A, 0x00088AAA, 0xAAAA0000, 0xA8A8AA88, 0xA88AAAAA, 0xAAAA8A8A, 0xAAA8AAA0, 0x8AAA8AAA, 0xAA8A8A8A, 0x000AAA88, 0x8AAA0000, 0xAAA8A888, 0x8AA88A8A, 0x8A88A888, 0x08080A00, 0x0A08080A, 0x080A0A08, 0x00080808, 0x080A0000, 0x080A0808, 0x080A0808, 0x0A0A0A08, 0xA0A0A0A0, 0x80A0A080, 0x8080A0A0, 0x00008080, 0x80A00000, 0x80A080A0, 0xA080A0A0, 0x8080A0A0, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x99999000, 0x9B9B99BB, 0x9BB99999, 0x9999B9B9, 0x9B99BB90, 0x9BBBBB9B, 0x9B9B9BB9, 0x00000999, 0x88000000, 0x8A8A88AA, 0x8AA88888, 0x8888A8A8, 0x8A88AA80, 0x8AAAAA8A, 0x8A8A8AA8, 0x00AAA888, 0x22000000, 0x2222B222, 0x22222222, 0x222222B2, 0xB2222220, 0x22222222, 0x22D22222, 0x00000222, 0x11000000, 0x1111A111, 0x11111111, 0x111111A1, 0xA1111110, 0x11111111, 0x11C11111, 0x00000111, 0x33000000, 0x3333B333, 0x33333333, 0x333333B3, 0xB3333330, 0x33333333, 0x33D33333, 0x00000333, 0x22000000, 0x2222A222, 0x22222222, 0x222222A2, 0xA2222220, 0x22222222, 0x22C22222, 0x00000222, 0x99B99B00, 0x9B9B99BB, 0x9BB99999, 0x9999B9B9, 0x9B99BB99, 0x9BBBBB9B, 0x9B9B9BB9, 0x00000999, 0x88000000, 0x8A8A88AA, 0x8AA88888, 0x8888A8A8, 0x8A88AA88, 0x8AAAAA8A, 0x8A8A8AA8, 0x08AAA888, 0x22222200, 0x2222F222, 0x22222222, 0x222222F2, 0x22222222, 0x22222222, 0x22F22222, 0x00000222, 0x11000000, 0x1111F111, 0x11111111, 0x11111111, 0xF1111111, 0x11111111, 0x11F11111, 0x01111111, 0xBB9BB900, 0xB9B9BB99, 0xB99BBBBB, 0xBBBB9B9B, 0xB9BB99BB, 0xB99999B9, 0xB9B9B99B, 0x00000BBB, 0xAA000000, 0xA8A8AA88, 0xA88AAAAA, 0xAAAA8A8A, 0xA8AA88AA, 0xA88888A8, 0xA8A8A88A, 0x0A888AAA, 0xAA000000, 0xA8A8AA88, 0xA88AAAAA, 0xAAAA8A8A, 0xA8AA88A0, 0xA88888A8, 0xA8A8A88A, 0x00000AAA, 0x88000000, 0x8A8A88AA, 0x8AA88888, 0x8888A8A8, 0x8A88AA80, 0x8AAAAA8A, 0x8A8A8AA8, 0x00000888, 0xBBBBBB00, 0x999BBBBB, 0x9BB99B9B, 0xB9B9B9BB, 0xB9B99BBB, 0xB9B9B9BB, 0xB9BB9B99, 0x00000999, 0x8A000000, 0xAA88A888, 0xA88888AA, 0xA88A8A88, 0xA88AA88A, 0x88A8AAAA, 0xA8AA8AAA, 0x0888A88A, 0x0B0B0B00, 0x090B0B0B, 0x0B090B0B, 0x0909090B, 0x09090B0B, 0x09090B0B, 0x09090B09, 0x00000909, 0x0A000000, 0x0A080808, 0x080A080A, 0x080A0A08, 0x080A080A, 0x0808080A, 0x0A0A0A08, 0x0808080A, 0xB0B0B000, 0x9090B0B0, 0x90B09090, 0xB0B0B090, 0xB0B090B0, 0x90B0B0B0, 0xB0B09090, 0x00000090, 0x80000000, 0xA080A080, 0xA08080A0, 0xA0808080, 0xA080A080, 0x80A0A0A0, 0xA0A080A0, 0x00A0A0A0, 0x22000000, 0x2222F222, 0x22222222, 0x222222F2, 0xF2222220, 0x22222222, 0x22F22222, 0x00000222, 0x11000000, 0x1111F111, 0x11111111, 0x111111F1, 0xF1111110, 0x11111111, 0x11F11111, 0x00000111, 0x33000000, 0x3333F333, 0x33333333, 0x333333F3, 0xF3333330, 0x33333333, 0x33F33333, 0x00000333, 0x22000000, 0x2222F222, 0x22222222, 0x222222F2, 0xF2222220, 0x22222222, 0x22F22222, 0x00000222, 0x99000000, 0x9B9B99BB, 0x9BB99999, 0x9999B9B9, 0x9B99BB90, 0x9BBBBB9B, 0x9B9B9BB9, 0x00000999, 0x88000000, 0x8A8A88AA, 0x8AA88888, 0x8888A8A8, 0x8A88AA80, 0x8AAAAA8A, 0x8A8A8AA8, 0x00000888, 0x88888000, 0x8A8A88AA, 0x8AA88888, 0x8888A8A8, 0x8A88AA80, 0x8AAAAA8A, 0x8A8A8AA8, 0x00000888, 0x88000000, 0x8A8A88AA, 0x8AA88888, 0x8888A8A8, 0x8A88AA80, 0x8AAAAA8A, 0x8A8A8AA8, 0x00AAA888, 0x88A88A00, 0x8A8A88AA, 0x8AA88888, 0x8888A8A8, 0x8A88AA88, 0x8AAAAA8A, 0x8A8A8AA8, 0x00000888, 0x88000000, 0x8A8A88AA, 0x8AA88888, 0x8888A8A8, 0x8A88AA88, 0x8AAAAA8A, 0x8A8A8AA8, 0x08AAA888, 0x11000000, 0x1111A111, 0x11111111, 0x111111A1, 0xA1111110, 0x11111111, 0x11C11111, 0x00000111, 0x11000000, 0x1111A111, 0x11111111, 0x111111A1, 0xA1111110, 0x11111111, 0x11C11111, 0x00000111, 0x88000000, 0x8A8A88AA, 0x8AA88888, 0x8888A8A8, 0x8A88AA80, 0x8AAAAA8A, 0x8A8A8AA8, 0x00000888, 0x88000000, 0x8A8A88AA, 0x8AA88888, 0x8888A8A8, 0x8A88AA80, 0x8AAAAA8A, 0x8A8A8AA8, 0x00000888, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, }; /* static tables, PHY revision >= 3 */ static const uint32_t bwn_ntab_framestruct_r3[] = { 0x08004a04, 0x00100000, 0x01000a05, 0x00100020, 0x09804506, 0x00100030, 0x09804507, 0x00100030, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x08004a0c, 0x00100004, 0x01000a0d, 0x00100024, 0x0980450e, 0x00100034, 0x0980450f, 0x00100034, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000a04, 0x00100000, 0x11008a05, 0x00100020, 0x1980c506, 0x00100030, 0x21810506, 0x00100030, 0x21810506, 0x00100030, 0x01800504, 0x00100030, 0x11808505, 0x00100030, 0x29814507, 0x01100030, 0x00000a04, 0x00100000, 0x11008a05, 0x00100020, 0x21810506, 0x00100030, 0x21810506, 0x00100030, 0x29814507, 0x01100030, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000a0c, 0x00100008, 0x11008a0d, 0x00100028, 0x1980c50e, 0x00100038, 0x2181050e, 0x00100038, 0x2181050e, 0x00100038, 0x0180050c, 0x00100038, 0x1180850d, 0x00100038, 0x2981450f, 0x01100038, 0x00000a0c, 0x00100008, 0x11008a0d, 0x00100028, 0x2181050e, 0x00100038, 0x2181050e, 0x00100038, 0x2981450f, 0x01100038, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x08004a04, 0x00100000, 0x01000a05, 0x00100020, 0x1980c506, 0x00100030, 0x1980c506, 0x00100030, 0x11808504, 0x00100030, 0x3981ca05, 0x00100030, 0x29814507, 0x01100030, 0x00000000, 0x00000000, 0x10008a04, 0x00100000, 0x3981ca05, 0x00100030, 0x1980c506, 0x00100030, 0x29814507, 0x01100030, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x08004a0c, 0x00100008, 0x01000a0d, 0x00100028, 0x1980c50e, 0x00100038, 0x1980c50e, 0x00100038, 0x1180850c, 0x00100038, 0x3981ca0d, 0x00100038, 0x2981450f, 0x01100038, 0x00000000, 0x00000000, 0x10008a0c, 0x00100008, 0x3981ca0d, 0x00100038, 0x1980c50e, 0x00100038, 0x2981450f, 0x01100038, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x40021404, 0x00100000, 0x02001405, 0x00100040, 0x0b004a06, 0x01900060, 0x13008a06, 0x01900060, 0x13008a06, 0x01900060, 0x43020a04, 0x00100060, 0x1b00ca05, 0x00100060, 0x23010a07, 0x01500060, 0x40021404, 0x00100000, 0x1a00d405, 0x00100040, 0x13008a06, 0x01900060, 0x13008a06, 0x01900060, 0x23010a07, 0x01500060, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x4002140c, 0x00100010, 0x0200140d, 0x00100050, 0x0b004a0e, 0x01900070, 0x13008a0e, 0x01900070, 0x13008a0e, 0x01900070, 0x43020a0c, 0x00100070, 0x1b00ca0d, 0x00100070, 0x23010a0f, 0x01500070, 0x4002140c, 0x00100010, 0x1a00d40d, 0x00100050, 0x13008a0e, 0x01900070, 0x13008a0e, 0x01900070, 0x23010a0f, 0x01500070, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x50029404, 0x00100000, 0x32019405, 0x00100040, 0x0b004a06, 0x01900060, 0x0b004a06, 0x01900060, 0x5b02ca04, 0x00100060, 0x3b01d405, 0x00100060, 0x23010a07, 0x01500060, 0x00000000, 0x00000000, 0x5802d404, 0x00100000, 0x3b01d405, 0x00100060, 0x0b004a06, 0x01900060, 0x23010a07, 0x01500060, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x5002940c, 0x00100010, 0x3201940d, 0x00100050, 0x0b004a0e, 0x01900070, 0x0b004a0e, 0x01900070, 0x5b02ca0c, 0x00100070, 0x3b01d40d, 0x00100070, 0x23010a0f, 0x01500070, 0x00000000, 0x00000000, 0x5802d40c, 0x00100010, 0x3b01d40d, 0x00100070, 0x0b004a0e, 0x01900070, 0x23010a0f, 0x01500070, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x40021404, 0x000f4800, 0x62031405, 0x00100040, 0x53028a06, 0x01900060, 0x53028a07, 0x01900060, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x4002140c, 0x000f4808, 0x6203140d, 0x00100048, 0x53028a0e, 0x01900068, 0x53028a0f, 0x01900068, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000a0c, 0x00100004, 0x11008a0d, 0x00100024, 0x1980c50e, 0x00100034, 0x2181050e, 0x00100034, 0x2181050e, 0x00100034, 0x0180050c, 0x00100038, 0x1180850d, 0x00100038, 0x1181850d, 0x00100038, 0x2981450f, 0x01100038, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000a0c, 0x00100008, 0x11008a0d, 0x00100028, 0x2181050e, 0x00100038, 0x2181050e, 0x00100038, 0x1181850d, 0x00100038, 0x2981450f, 0x01100038, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x08004a04, 0x00100000, 0x01000a05, 0x00100020, 0x0180c506, 0x00100030, 0x0180c506, 0x00100030, 0x2180c50c, 0x00100030, 0x49820a0d, 0x0016a130, 0x41824a0d, 0x0016a130, 0x2981450f, 0x01100030, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x2000ca0c, 0x00100000, 0x49820a0d, 0x0016a130, 0x1980c50e, 0x00100030, 0x41824a0d, 0x0016a130, 0x2981450f, 0x01100030, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x4002140c, 0x00100008, 0x0200140d, 0x00100048, 0x0b004a0e, 0x01900068, 0x13008a0e, 0x01900068, 0x13008a0e, 0x01900068, 0x43020a0c, 0x00100070, 0x1b00ca0d, 0x00100070, 0x1b014a0d, 0x00100070, 0x23010a0f, 0x01500070, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x4002140c, 0x00100010, 0x1a00d40d, 0x00100050, 0x13008a0e, 0x01900070, 0x13008a0e, 0x01900070, 0x1b014a0d, 0x00100070, 0x23010a0f, 0x01500070, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x50029404, 0x00100000, 0x32019405, 0x00100040, 0x03004a06, 0x01900060, 0x03004a06, 0x01900060, 0x6b030a0c, 0x00100060, 0x4b02140d, 0x0016a160, 0x4302540d, 0x0016a160, 0x23010a0f, 0x01500060, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x6b03140c, 0x00100060, 0x4b02140d, 0x0016a160, 0x0b004a0e, 0x01900060, 0x4302540d, 0x0016a160, 0x23010a0f, 0x01500060, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x40021404, 0x00100000, 0x1a00d405, 0x00100040, 0x53028a06, 0x01900060, 0x5b02ca06, 0x01900060, 0x5b02ca06, 0x01900060, 0x43020a04, 0x00100060, 0x1b00ca05, 0x00100060, 0x53028a07, 0x0190c060, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x4002140c, 0x00100010, 0x1a00d40d, 0x00100050, 0x53028a0e, 0x01900070, 0x5b02ca0e, 0x01900070, 0x5b02ca0e, 0x01900070, 0x43020a0c, 0x00100070, 0x1b00ca0d, 0x00100070, 0x53028a0f, 0x0190c070, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x40021404, 0x00100000, 0x1a00d405, 0x00100040, 0x5b02ca06, 0x01900060, 0x5b02ca06, 0x01900060, 0x53028a07, 0x0190c060, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x4002140c, 0x00100010, 0x1a00d40d, 0x00100050, 0x5b02ca0e, 0x01900070, 0x5b02ca0e, 0x01900070, 0x53028a0f, 0x0190c070, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, }; static const uint16_t bwn_ntab_pilot_r3[] = { 0xff08, 0xff08, 0xff08, 0xff08, 0xff08, 0xff08, 0xff08, 0xff08, 0x80d5, 0x80d5, 0x80d5, 0x80d5, 0x80d5, 0x80d5, 0x80d5, 0x80d5, 0xff0a, 0xff82, 0xffa0, 0xff28, 0xffff, 0xffff, 0xffff, 0xffff, 0xff82, 0xffa0, 0xff28, 0xff0a, 0xffff, 0xffff, 0xffff, 0xffff, 0xf83f, 0xfa1f, 0xfa97, 0xfab5, 0xf2bd, 0xf0bf, 0xffff, 0xffff, 0xf017, 0xf815, 0xf215, 0xf095, 0xf035, 0xf01d, 0xffff, 0xffff, 0xff08, 0xff02, 0xff80, 0xff20, 0xff08, 0xff02, 0xff80, 0xff20, 0xf01f, 0xf817, 0xfa15, 0xf295, 0xf0b5, 0xf03d, 0xffff, 0xffff, 0xf82a, 0xfa0a, 0xfa82, 0xfaa0, 0xf2a8, 0xf0aa, 0xffff, 0xffff, 0xf002, 0xf800, 0xf200, 0xf080, 0xf020, 0xf008, 0xffff, 0xffff, 0xf00a, 0xf802, 0xfa00, 0xf280, 0xf0a0, 0xf028, 0xffff, 0xffff, }; static const uint32_t bwn_ntab_tmap_r3[] = { 0x8a88aa80, 0x8aaaaa8a, 0x8a8a8aa8, 0x00000888, 0x88000000, 0x8a8a88aa, 0x8aa88888, 0x8888a8a8, 0xf1111110, 0x11111111, 0x11f11111, 0x00000111, 0x11000000, 0x1111f111, 0x11111111, 0x111111f1, 0x8a88aa80, 0x8aaaaa8a, 0x8a8a8aa8, 0x000aa888, 0x88880000, 0x8a8a88aa, 0x8aa88888, 0x8888a8a8, 0xa1111110, 0x11111111, 0x11c11111, 0x00000111, 0x11000000, 0x1111a111, 0x11111111, 0x111111a1, 0xa2222220, 0x22222222, 0x22c22222, 0x00000222, 0x22000000, 0x2222a222, 0x22222222, 0x222222a2, 0xf1111110, 0x11111111, 0x11f11111, 0x00011111, 0x11110000, 0x1111f111, 0x11111111, 0x111111f1, 0xa8aa88a0, 0xa88888a8, 0xa8a8a88a, 0x00088aaa, 0xaaaa0000, 0xa8a8aa88, 0xa88aaaaa, 0xaaaa8a8a, 0xaaa8aaa0, 0x8aaa8aaa, 0xaa8a8a8a, 0x000aaa88, 0x8aaa0000, 0xaaa8a888, 0x8aa88a8a, 0x8a88a888, 0x08080a00, 0x0a08080a, 0x080a0a08, 0x00080808, 0x080a0000, 0x080a0808, 0x080a0808, 0x0a0a0a08, 0xa0a0a0a0, 0x80a0a080, 0x8080a0a0, 0x00008080, 0x80a00000, 0x80a080a0, 0xa080a0a0, 0x8080a0a0, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x99999000, 0x9b9b99bb, 0x9bb99999, 0x9999b9b9, 0x9b99bb90, 0x9bbbbb9b, 0x9b9b9bb9, 0x00000999, 0x88000000, 0x8a8a88aa, 0x8aa88888, 0x8888a8a8, 0x8a88aa80, 0x8aaaaa8a, 0x8a8a8aa8, 0x00aaa888, 0x22000000, 0x2222b222, 0x22222222, 0x222222b2, 0xb2222220, 0x22222222, 0x22d22222, 0x00000222, 0x11000000, 0x1111a111, 0x11111111, 0x111111a1, 0xa1111110, 0x11111111, 0x11c11111, 0x00000111, 0x33000000, 0x3333b333, 0x33333333, 0x333333b3, 0xb3333330, 0x33333333, 0x33d33333, 0x00000333, 0x22000000, 0x2222a222, 0x22222222, 0x222222a2, 0xa2222220, 0x22222222, 0x22c22222, 0x00000222, 0x99b99b00, 0x9b9b99bb, 0x9bb99999, 0x9999b9b9, 0x9b99bb99, 0x9bbbbb9b, 0x9b9b9bb9, 0x00000999, 0x88000000, 0x8a8a88aa, 0x8aa88888, 0x8888a8a8, 0x8a88aa88, 0x8aaaaa8a, 0x8a8a8aa8, 0x08aaa888, 0x22222200, 0x2222f222, 0x22222222, 0x222222f2, 0x22222222, 0x22222222, 0x22f22222, 0x00000222, 0x11000000, 0x1111f111, 0x11111111, 0x11111111, 0xf1111111, 0x11111111, 0x11f11111, 0x01111111, 0xbb9bb900, 0xb9b9bb99, 0xb99bbbbb, 0xbbbb9b9b, 0xb9bb99bb, 0xb99999b9, 0xb9b9b99b, 0x00000bbb, 0xaa000000, 0xa8a8aa88, 0xa88aaaaa, 0xaaaa8a8a, 0xa8aa88aa, 0xa88888a8, 0xa8a8a88a, 0x0a888aaa, 0xaa000000, 0xa8a8aa88, 0xa88aaaaa, 0xaaaa8a8a, 0xa8aa88a0, 0xa88888a8, 0xa8a8a88a, 0x00000aaa, 0x88000000, 0x8a8a88aa, 0x8aa88888, 0x8888a8a8, 0x8a88aa80, 0x8aaaaa8a, 0x8a8a8aa8, 0x00000888, 0xbbbbbb00, 0x999bbbbb, 0x9bb99b9b, 0xb9b9b9bb, 0xb9b99bbb, 0xb9b9b9bb, 0xb9bb9b99, 0x00000999, 0x8a000000, 0xaa88a888, 0xa88888aa, 0xa88a8a88, 0xa88aa88a, 0x88a8aaaa, 0xa8aa8aaa, 0x0888a88a, 0x0b0b0b00, 0x090b0b0b, 0x0b090b0b, 0x0909090b, 0x09090b0b, 0x09090b0b, 0x09090b09, 0x00000909, 0x0a000000, 0x0a080808, 0x080a080a, 0x080a0a08, 0x080a080a, 0x0808080a, 0x0a0a0a08, 0x0808080a, 0xb0b0b000, 0x9090b0b0, 0x90b09090, 0xb0b0b090, 0xb0b090b0, 0x90b0b0b0, 0xb0b09090, 0x00000090, 0x80000000, 0xa080a080, 0xa08080a0, 0xa0808080, 0xa080a080, 0x80a0a0a0, 0xa0a080a0, 0x00a0a0a0, 0x22000000, 0x2222f222, 0x22222222, 0x222222f2, 0xf2222220, 0x22222222, 0x22f22222, 0x00000222, 0x11000000, 0x1111f111, 0x11111111, 0x111111f1, 0xf1111110, 0x11111111, 0x11f11111, 0x00000111, 0x33000000, 0x3333f333, 0x33333333, 0x333333f3, 0xf3333330, 0x33333333, 0x33f33333, 0x00000333, 0x22000000, 0x2222f222, 0x22222222, 0x222222f2, 0xf2222220, 0x22222222, 0x22f22222, 0x00000222, 0x99000000, 0x9b9b99bb, 0x9bb99999, 0x9999b9b9, 0x9b99bb90, 0x9bbbbb9b, 0x9b9b9bb9, 0x00000999, 0x88000000, 0x8a8a88aa, 0x8aa88888, 0x8888a8a8, 0x8a88aa80, 0x8aaaaa8a, 0x8a8a8aa8, 0x00000888, 0x88888000, 0x8a8a88aa, 0x8aa88888, 0x8888a8a8, 0x8a88aa80, 0x8aaaaa8a, 0x8a8a8aa8, 0x00000888, 0x88000000, 0x8a8a88aa, 0x8aa88888, 0x8888a8a8, 0x8a88aa80, 0x8aaaaa8a, 0x8a8a8aa8, 0x00aaa888, 0x88a88a00, 0x8a8a88aa, 0x8aa88888, 0x8888a8a8, 0x8a88aa88, 0x8aaaaa8a, 0x8a8a8aa8, 0x00000888, 0x88000000, 0x8a8a88aa, 0x8aa88888, 0x8888a8a8, 0x8a88aa88, 0x8aaaaa8a, 0x8a8a8aa8, 0x08aaa888, 0x11000000, 0x1111a111, 0x11111111, 0x111111a1, 0xa1111110, 0x11111111, 0x11c11111, 0x00000111, 0x11000000, 0x1111a111, 0x11111111, 0x111111a1, 0xa1111110, 0x11111111, 0x11c11111, 0x00000111, 0x88000000, 0x8a8a88aa, 0x8aa88888, 0x8888a8a8, 0x8a88aa80, 0x8aaaaa8a, 0x8a8a8aa8, 0x00000888, 0x88000000, 0x8a8a88aa, 0x8aa88888, 0x8888a8a8, 0x8a88aa80, 0x8aaaaa8a, 0x8a8a8aa8, 0x00000888, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, }; static const uint32_t bwn_ntab_intlevel_r3[] = { 0x00802070, 0x0671188d, 0x0a60192c, 0x0a300e46, 0x00c1188d, 0x080024d2, 0x00000070, }; static const uint32_t bwn_ntab_tdtrn_r3[] = { 0x061c061c, 0x0050ee68, 0xf592fe36, 0xfe5212f6, 0x00000c38, 0xfe5212f6, 0xf592fe36, 0x0050ee68, 0x061c061c, 0xee680050, 0xfe36f592, 0x12f6fe52, 0x0c380000, 0x12f6fe52, 0xfe36f592, 0xee680050, 0x061c061c, 0x0050ee68, 0xf592fe36, 0xfe5212f6, 0x00000c38, 0xfe5212f6, 0xf592fe36, 0x0050ee68, 0x061c061c, 0xee680050, 0xfe36f592, 0x12f6fe52, 0x0c380000, 0x12f6fe52, 0xfe36f592, 0xee680050, 0x05e305e3, 0x004def0c, 0xf5f3fe47, 0xfe611246, 0x00000bc7, 0xfe611246, 0xf5f3fe47, 0x004def0c, 0x05e305e3, 0xef0c004d, 0xfe47f5f3, 0x1246fe61, 0x0bc70000, 0x1246fe61, 0xfe47f5f3, 0xef0c004d, 0x05e305e3, 0x004def0c, 0xf5f3fe47, 0xfe611246, 0x00000bc7, 0xfe611246, 0xf5f3fe47, 0x004def0c, 0x05e305e3, 0xef0c004d, 0xfe47f5f3, 0x1246fe61, 0x0bc70000, 0x1246fe61, 0xfe47f5f3, 0xef0c004d, 0xfa58fa58, 0xf895043b, 0xff4c09c0, 0xfbc6ffa8, 0xfb84f384, 0x0798f6f9, 0x05760122, 0x058409f6, 0x0b500000, 0x05b7f542, 0x08860432, 0x06ddfee7, 0xfb84f384, 0xf9d90664, 0xf7e8025c, 0x00fff7bd, 0x05a805a8, 0xf7bd00ff, 0x025cf7e8, 0x0664f9d9, 0xf384fb84, 0xfee706dd, 0x04320886, 0xf54205b7, 0x00000b50, 0x09f60584, 0x01220576, 0xf6f90798, 0xf384fb84, 0xffa8fbc6, 0x09c0ff4c, 0x043bf895, 0x02d402d4, 0x07de0270, 0xfc96079c, 0xf90afe94, 0xfe00ff2c, 0x02d4065d, 0x092a0096, 0x0014fbb8, 0xfd2cfd2c, 0x076afb3c, 0x0096f752, 0xf991fd87, 0xfb2c0200, 0xfeb8f960, 0x08e0fc96, 0x049802a8, 0xfd2cfd2c, 0x02a80498, 0xfc9608e0, 0xf960feb8, 0x0200fb2c, 0xfd87f991, 0xf7520096, 0xfb3c076a, 0xfd2cfd2c, 0xfbb80014, 0x0096092a, 0x065d02d4, 0xff2cfe00, 0xfe94f90a, 0x079cfc96, 0x027007de, 0x02d402d4, 0x027007de, 0x079cfc96, 0xfe94f90a, 0xff2cfe00, 0x065d02d4, 0x0096092a, 0xfbb80014, 0xfd2cfd2c, 0xfb3c076a, 0xf7520096, 0xfd87f991, 0x0200fb2c, 0xf960feb8, 0xfc9608e0, 0x02a80498, 0xfd2cfd2c, 0x049802a8, 0x08e0fc96, 0xfeb8f960, 0xfb2c0200, 0xf991fd87, 0x0096f752, 0x076afb3c, 0xfd2cfd2c, 0x0014fbb8, 0x092a0096, 0x02d4065d, 0xfe00ff2c, 0xf90afe94, 0xfc96079c, 0x07de0270, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x062a0000, 0xfefa0759, 0x08b80908, 0xf396fc2d, 0xf9d6045c, 0xfc4ef608, 0xf748f596, 0x07b207bf, 0x062a062a, 0xf84ef841, 0xf748f596, 0x03b209f8, 0xf9d6045c, 0x0c6a03d3, 0x08b80908, 0x0106f8a7, 0x062a0000, 0xfefaf8a7, 0x08b8f6f8, 0xf39603d3, 0xf9d6fba4, 0xfc4e09f8, 0xf7480a6a, 0x07b2f841, 0x062af9d6, 0xf84e07bf, 0xf7480a6a, 0x03b2f608, 0xf9d6fba4, 0x0c6afc2d, 0x08b8f6f8, 0x01060759, 0x062a0000, 0xfefa0759, 0x08b80908, 0xf396fc2d, 0xf9d6045c, 0xfc4ef608, 0xf748f596, 0x07b207bf, 0x062a062a, 0xf84ef841, 0xf748f596, 0x03b209f8, 0xf9d6045c, 0x0c6a03d3, 0x08b80908, 0x0106f8a7, 0x062a0000, 0xfefaf8a7, 0x08b8f6f8, 0xf39603d3, 0xf9d6fba4, 0xfc4e09f8, 0xf7480a6a, 0x07b2f841, 0x062af9d6, 0xf84e07bf, 0xf7480a6a, 0x03b2f608, 0xf9d6fba4, 0x0c6afc2d, 0x08b8f6f8, 0x01060759, 0x061c061c, 0xff30009d, 0xffb21141, 0xfd87fb54, 0xf65dfe59, 0x02eef99e, 0x0166f03c, 0xfff809b6, 0x000008a4, 0x000af42b, 0x00eff577, 0xfa840bf2, 0xfc02ff51, 0x08260f67, 0xfff0036f, 0x0842f9c3, 0x00000000, 0x063df7be, 0xfc910010, 0xf099f7da, 0x00af03fe, 0xf40e057c, 0x0a89ff11, 0x0bd5fff6, 0xf75c0000, 0xf64a0008, 0x0fc4fe9a, 0x0662fd12, 0x01a709a3, 0x04ac0279, 0xeebf004e, 0xff6300d0, 0xf9e4f9e4, 0x00d0ff63, 0x004eeebf, 0x027904ac, 0x09a301a7, 0xfd120662, 0xfe9a0fc4, 0x0008f64a, 0x0000f75c, 0xfff60bd5, 0xff110a89, 0x057cf40e, 0x03fe00af, 0xf7daf099, 0x0010fc91, 0xf7be063d, 0x00000000, 0xf9c30842, 0x036ffff0, 0x0f670826, 0xff51fc02, 0x0bf2fa84, 0xf57700ef, 0xf42b000a, 0x08a40000, 0x09b6fff8, 0xf03c0166, 0xf99e02ee, 0xfe59f65d, 0xfb54fd87, 0x1141ffb2, 0x009dff30, 0x05e30000, 0xff060705, 0x085408a0, 0xf425fc59, 0xfa1d042a, 0xfc78f67a, 0xf7acf60e, 0x075a0766, 0x05e305e3, 0xf8a6f89a, 0xf7acf60e, 0x03880986, 0xfa1d042a, 0x0bdb03a7, 0x085408a0, 0x00faf8fb, 0x05e30000, 0xff06f8fb, 0x0854f760, 0xf42503a7, 0xfa1dfbd6, 0xfc780986, 0xf7ac09f2, 0x075af89a, 0x05e3fa1d, 0xf8a60766, 0xf7ac09f2, 0x0388f67a, 0xfa1dfbd6, 0x0bdbfc59, 0x0854f760, 0x00fa0705, 0x05e30000, 0xff060705, 0x085408a0, 0xf425fc59, 0xfa1d042a, 0xfc78f67a, 0xf7acf60e, 0x075a0766, 0x05e305e3, 0xf8a6f89a, 0xf7acf60e, 0x03880986, 0xfa1d042a, 0x0bdb03a7, 0x085408a0, 0x00faf8fb, 0x05e30000, 0xff06f8fb, 0x0854f760, 0xf42503a7, 0xfa1dfbd6, 0xfc780986, 0xf7ac09f2, 0x075af89a, 0x05e3fa1d, 0xf8a60766, 0xf7ac09f2, 0x0388f67a, 0xfa1dfbd6, 0x0bdbfc59, 0x0854f760, 0x00fa0705, 0xfa58fa58, 0xf8f0fe00, 0x0448073d, 0xfdc9fe46, 0xf9910258, 0x089d0407, 0xfd5cf71a, 0x02affde0, 0x083e0496, 0xff5a0740, 0xff7afd97, 0x00fe01f1, 0x0009082e, 0xfa94ff75, 0xfecdf8ea, 0xffb0f693, 0xfd2cfa58, 0x0433ff16, 0xfba405dd, 0xfa610341, 0x06a606cb, 0x0039fd2d, 0x0677fa97, 0x01fa05e0, 0xf896003e, 0x075a068b, 0x012cfc3e, 0xfa23f98d, 0xfc7cfd43, 0xff90fc0d, 0x01c10982, 0x00c601d6, 0xfd2cfd2c, 0x01d600c6, 0x098201c1, 0xfc0dff90, 0xfd43fc7c, 0xf98dfa23, 0xfc3e012c, 0x068b075a, 0x003ef896, 0x05e001fa, 0xfa970677, 0xfd2d0039, 0x06cb06a6, 0x0341fa61, 0x05ddfba4, 0xff160433, 0xfa58fd2c, 0xf693ffb0, 0xf8eafecd, 0xff75fa94, 0x082e0009, 0x01f100fe, 0xfd97ff7a, 0x0740ff5a, 0x0496083e, 0xfde002af, 0xf71afd5c, 0x0407089d, 0x0258f991, 0xfe46fdc9, 0x073d0448, 0xfe00f8f0, 0xfd2cfd2c, 0xfce00500, 0xfc09fddc, 0xfe680157, 0x04c70571, 0xfc3aff21, 0xfcd70228, 0x056d0277, 0x0200fe00, 0x0022f927, 0xfe3c032b, 0xfc44ff3c, 0x03e9fbdb, 0x04570313, 0x04c9ff5c, 0x000d03b8, 0xfa580000, 0xfbe900d2, 0xf9d0fe0b, 0x0125fdf9, 0x042501bf, 0x0328fa2b, 0xffa902f0, 0xfa250157, 0x0200fe00, 0x03740438, 0xff0405fd, 0x030cfe52, 0x0037fb39, 0xff6904c5, 0x04f8fd23, 0xfd31fc1b, 0xfd2cfd2c, 0xfc1bfd31, 0xfd2304f8, 0x04c5ff69, 0xfb390037, 0xfe52030c, 0x05fdff04, 0x04380374, 0xfe000200, 0x0157fa25, 0x02f0ffa9, 0xfa2b0328, 0x01bf0425, 0xfdf90125, 0xfe0bf9d0, 0x00d2fbe9, 0x0000fa58, 0x03b8000d, 0xff5c04c9, 0x03130457, 0xfbdb03e9, 0xff3cfc44, 0x032bfe3c, 0xf9270022, 0xfe000200, 0x0277056d, 0x0228fcd7, 0xff21fc3a, 0x057104c7, 0x0157fe68, 0xfddcfc09, 0x0500fce0, 0xfd2cfd2c, 0x0500fce0, 0xfddcfc09, 0x0157fe68, 0x057104c7, 0xff21fc3a, 0x0228fcd7, 0x0277056d, 0xfe000200, 0xf9270022, 0x032bfe3c, 0xff3cfc44, 0xfbdb03e9, 0x03130457, 0xff5c04c9, 0x03b8000d, 0x0000fa58, 0x00d2fbe9, 0xfe0bf9d0, 0xfdf90125, 0x01bf0425, 0xfa2b0328, 0x02f0ffa9, 0x0157fa25, 0xfe000200, 0x04380374, 0x05fdff04, 0xfe52030c, 0xfb390037, 0x04c5ff69, 0xfd2304f8, 0xfc1bfd31, 0xfd2cfd2c, 0xfd31fc1b, 0x04f8fd23, 0xff6904c5, 0x0037fb39, 0x030cfe52, 0xff0405fd, 0x03740438, 0x0200fe00, 0xfa250157, 0xffa902f0, 0x0328fa2b, 0x042501bf, 0x0125fdf9, 0xf9d0fe0b, 0xfbe900d2, 0xfa580000, 0x000d03b8, 0x04c9ff5c, 0x04570313, 0x03e9fbdb, 0xfc44ff3c, 0xfe3c032b, 0x0022f927, 0x0200fe00, 0x056d0277, 0xfcd70228, 0xfc3aff21, 0x04c70571, 0xfe680157, 0xfc09fddc, 0xfce00500, 0x05a80000, 0xff1006be, 0x0800084a, 0xf49cfc7e, 0xfa580400, 0xfc9cf6da, 0xf800f672, 0x0710071c, 0x05a805a8, 0xf8f0f8e4, 0xf800f672, 0x03640926, 0xfa580400, 0x0b640382, 0x0800084a, 0x00f0f942, 0x05a80000, 0xff10f942, 0x0800f7b6, 0xf49c0382, 0xfa58fc00, 0xfc9c0926, 0xf800098e, 0x0710f8e4, 0x05a8fa58, 0xf8f0071c, 0xf800098e, 0x0364f6da, 0xfa58fc00, 0x0b64fc7e, 0x0800f7b6, 0x00f006be, 0x05a80000, 0xff1006be, 0x0800084a, 0xf49cfc7e, 0xfa580400, 0xfc9cf6da, 0xf800f672, 0x0710071c, 0x05a805a8, 0xf8f0f8e4, 0xf800f672, 0x03640926, 0xfa580400, 0x0b640382, 0x0800084a, 0x00f0f942, 0x05a80000, 0xff10f942, 0x0800f7b6, 0xf49c0382, 0xfa58fc00, 0xfc9c0926, 0xf800098e, 0x0710f8e4, 0x05a8fa58, 0xf8f0071c, 0xf800098e, 0x0364f6da, 0xfa58fc00, 0x0b64fc7e, 0x0800f7b6, 0x00f006be, }; static const uint32_t bwn_ntab_noisevar_r3[] = { 0x02110211, 0x0000014d, 0x02110211, 0x0000014d, 0x02110211, 0x0000014d, 0x02110211, 0x0000014d, 0x02110211, 0x0000014d, 0x02110211, 0x0000014d, 0x02110211, 0x0000014d, 0x02110211, 0x0000014d, 0x02110211, 0x0000014d, 0x02110211, 0x0000014d, 0x02110211, 0x0000014d, 0x02110211, 0x0000014d, 0x02110211, 0x0000014d, 0x02110211, 0x0000014d, 0x02110211, 0x0000014d, 0x02110211, 0x0000014d, 0x02110211, 0x0000014d, 0x02110211, 0x0000014d, 0x02110211, 0x0000014d, 0x02110211, 0x0000014d, 0x02110211, 0x0000014d, 0x02110211, 0x0000014d, 0x02110211, 0x0000014d, 0x02110211, 0x0000014d, 0x02110211, 0x0000014d, 0x02110211, 0x0000014d, 0x02110211, 0x0000014d, 0x02110211, 0x0000014d, 0x02110211, 0x0000014d, 0x02110211, 0x0000014d, 0x02110211, 0x0000014d, 0x02110211, 0x0000014d, 0x02110211, 0x0000014d, 0x02110211, 0x0000014d, 0x02110211, 0x0000014d, 0x02110211, 0x0000014d, 0x02110211, 0x0000014d, 0x02110211, 0x0000014d, 0x02110211, 0x0000014d, 0x02110211, 0x0000014d, 0x02110211, 0x0000014d, 0x02110211, 0x0000014d, 0x02110211, 0x0000014d, 0x02110211, 0x0000014d, 0x02110211, 0x0000014d, 0x02110211, 0x0000014d, 0x02110211, 0x0000014d, 0x02110211, 0x0000014d, 0x02110211, 0x0000014d, 0x02110211, 0x0000014d, 0x02110211, 0x0000014d, 0x02110211, 0x0000014d, 0x02110211, 0x0000014d, 0x02110211, 0x0000014d, 0x02110211, 0x0000014d, 0x02110211, 0x0000014d, 0x02110211, 0x0000014d, 0x02110211, 0x0000014d, 0x02110211, 0x0000014d, 0x02110211, 0x0000014d, 0x02110211, 0x0000014d, 0x02110211, 0x0000014d, 0x02110211, 0x0000014d, 0x02110211, 0x0000014d, 0x02110211, 0x0000014d, 0x02110211, 0x0000014d, 0x02110211, 0x0000014d, 0x02110211, 0x0000014d, 0x02110211, 0x0000014d, 0x02110211, 0x0000014d, 0x02110211, 0x0000014d, 0x02110211, 0x0000014d, 0x02110211, 0x0000014d, 0x02110211, 0x0000014d, 0x02110211, 0x0000014d, 0x02110211, 0x0000014d, 0x02110211, 0x0000014d, 0x02110211, 0x0000014d, 0x02110211, 0x0000014d, 0x02110211, 0x0000014d, 0x02110211, 0x0000014d, 0x02110211, 0x0000014d, 0x02110211, 0x0000014d, 0x02110211, 0x0000014d, 0x02110211, 0x0000014d, 0x02110211, 0x0000014d, 0x02110211, 0x0000014d, 0x02110211, 0x0000014d, 0x02110211, 0x0000014d, 0x02110211, 0x0000014d, 0x02110211, 0x0000014d, 0x02110211, 0x0000014d, 0x02110211, 0x0000014d, 0x02110211, 0x0000014d, 0x02110211, 0x0000014d, 0x02110211, 0x0000014d, 0x02110211, 0x0000014d, 0x02110211, 0x0000014d, 0x02110211, 0x0000014d, 0x02110211, 0x0000014d, 0x02110211, 0x0000014d, 0x02110211, 0x0000014d, 0x02110211, 0x0000014d, 0x02110211, 0x0000014d, 0x02110211, 0x0000014d, 0x02110211, 0x0000014d, 0x02110211, 0x0000014d, 0x02110211, 0x0000014d, 0x02110211, 0x0000014d, 0x02110211, 0x0000014d, 0x02110211, 0x0000014d, 0x02110211, 0x0000014d, 0x02110211, 0x0000014d, 0x02110211, 0x0000014d, 0x02110211, 0x0000014d, 0x02110211, 0x0000014d, 0x02110211, 0x0000014d, 0x02110211, 0x0000014d, 0x02110211, 0x0000014d, 0x02110211, 0x0000014d, 0x02110211, 0x0000014d, 0x02110211, 0x0000014d, 0x02110211, 0x0000014d, 0x02110211, 0x0000014d, 0x02110211, 0x0000014d, 0x02110211, 0x0000014d, 0x02110211, 0x0000014d, 0x02110211, 0x0000014d, }; static const uint16_t bwn_ntab_mcs_r3[] = { 0x0000, 0x0008, 0x000a, 0x0010, 0x0012, 0x0019, 0x001a, 0x001c, 0x0080, 0x0088, 0x008a, 0x0090, 0x0092, 0x0099, 0x009a, 0x009c, 0x0100, 0x0108, 0x010a, 0x0110, 0x0112, 0x0119, 0x011a, 0x011c, 0x0180, 0x0188, 0x018a, 0x0190, 0x0192, 0x0199, 0x019a, 0x019c, 0x0000, 0x0098, 0x00a0, 0x00a8, 0x009a, 0x00a2, 0x00aa, 0x0120, 0x0128, 0x0128, 0x0130, 0x0138, 0x0138, 0x0140, 0x0122, 0x012a, 0x012a, 0x0132, 0x013a, 0x013a, 0x0142, 0x01a8, 0x01b0, 0x01b8, 0x01b0, 0x01b8, 0x01c0, 0x01c8, 0x01c0, 0x01c8, 0x01d0, 0x01d0, 0x01d8, 0x01aa, 0x01b2, 0x01ba, 0x01b2, 0x01ba, 0x01c2, 0x01ca, 0x01c2, 0x01ca, 0x01d2, 0x01d2, 0x01da, 0x0001, 0x0002, 0x0004, 0x0009, 0x000c, 0x0011, 0x0014, 0x0018, 0x0020, 0x0021, 0x0022, 0x0024, 0x0081, 0x0082, 0x0084, 0x0089, 0x008c, 0x0091, 0x0094, 0x0098, 0x00a0, 0x00a1, 0x00a2, 0x00a4, 0x0007, 0x0007, 0x0007, 0x0007, 0x0007, 0x0007, 0x0007, 0x0007, 0x0007, 0x0007, 0x0007, 0x0007, 0x0007, 0x0007, 0x0007, 0x0007, 0x0007, 0x0007, 0x0007, 0x0007, 0x0007, 0x0007, 0x0007, 0x0007, 0x0007, 0x0007, 0x0007, }; static const uint32_t bwn_ntab_tdi20a0_r3[] = { 0x00091226, 0x000a1429, 0x000b56ad, 0x000c58b0, 0x000d5ab3, 0x000e9cb6, 0x000f9eba, 0x0000c13d, 0x00020301, 0x00030504, 0x00040708, 0x0005090b, 0x00064b8e, 0x00095291, 0x000a5494, 0x000b9718, 0x000c9927, 0x000d9b2a, 0x000edd2e, 0x000fdf31, 0x000101b4, 0x000243b7, 0x000345bb, 0x000447be, 0x00058982, 0x00068c05, 0x00099309, 0x000a950c, 0x000bd78f, 0x000cd992, 0x000ddb96, 0x000f1d99, 0x00005fa8, 0x0001422c, 0x0002842f, 0x00038632, 0x00048835, 0x0005ca38, 0x0006ccbc, 0x0009d3bf, 0x000b1603, 0x000c1806, 0x000d1a0a, 0x000e1c0d, 0x000f5e10, 0x00008093, 0x00018297, 0x0002c49a, 0x0003c680, 0x0004c880, 0x00060b00, 0x00070d00, 0x00000000, 0x00000000, 0x00000000, }; static const uint32_t bwn_ntab_tdi20a1_r3[] = { 0x00014b26, 0x00028d29, 0x000393ad, 0x00049630, 0x0005d833, 0x0006da36, 0x00099c3a, 0x000a9e3d, 0x000bc081, 0x000cc284, 0x000dc488, 0x000f068b, 0x0000488e, 0x00018b91, 0x0002d214, 0x0003d418, 0x0004d6a7, 0x000618aa, 0x00071aae, 0x0009dcb1, 0x000b1eb4, 0x000c0137, 0x000d033b, 0x000e053e, 0x000f4702, 0x00008905, 0x00020c09, 0x0003128c, 0x0004148f, 0x00051712, 0x00065916, 0x00091b19, 0x000a1d28, 0x000b5f2c, 0x000c41af, 0x000d43b2, 0x000e85b5, 0x000f87b8, 0x0000c9bc, 0x00024cbf, 0x00035303, 0x00045506, 0x0005978a, 0x0006998d, 0x00095b90, 0x000a5d93, 0x000b9f97, 0x000c821a, 0x000d8400, 0x000ec600, 0x000fc800, 0x00010a00, 0x00000000, 0x00000000, 0x00000000, }; static const uint32_t bwn_ntab_tdi40a0_r3[] = { 0x0011a346, 0x00136ccf, 0x0014f5d9, 0x001641e2, 0x0017cb6b, 0x00195475, 0x001b2383, 0x001cad0c, 0x001e7616, 0x0000821f, 0x00020ba8, 0x0003d4b2, 0x00056447, 0x00072dd0, 0x0008b6da, 0x000a02e3, 0x000b8c6c, 0x000d15f6, 0x0011e484, 0x0013ae0d, 0x00153717, 0x00168320, 0x00180ca9, 0x00199633, 0x001b6548, 0x001ceed1, 0x001eb7db, 0x0000c3e4, 0x00024d6d, 0x000416f7, 0x0005a585, 0x00076f0f, 0x0008f818, 0x000a4421, 0x000bcdab, 0x000d9734, 0x00122649, 0x0013efd2, 0x001578dc, 0x0016c4e5, 0x00184e6e, 0x001a17f8, 0x001ba686, 0x001d3010, 0x001ef999, 0x00010522, 0x00028eac, 0x00045835, 0x0005e74a, 0x0007b0d3, 0x00093a5d, 0x000a85e6, 0x000c0f6f, 0x000dd8f9, 0x00126787, 0x00143111, 0x0015ba9a, 0x00170623, 0x00188fad, 0x001a5936, 0x001be84b, 0x001db1d4, 0x001f3b5e, 0x000146e7, 0x00031070, 0x000499fa, 0x00062888, 0x0007f212, 0x00097b9b, 0x000ac7a4, 0x000c50ae, 0x000e1a37, 0x0012a94c, 0x001472d5, 0x0015fc5f, 0x00174868, 0x0018d171, 0x001a9afb, 0x001c2989, 0x001df313, 0x001f7c9c, 0x000188a5, 0x000351af, 0x0004db38, 0x0006aa4d, 0x000833d7, 0x0009bd60, 0x000b0969, 0x000c9273, 0x000e5bfc, 0x00132a8a, 0x0014b414, 0x00163d9d, 0x001789a6, 0x001912b0, 0x001adc39, 0x001c6bce, 0x001e34d8, 0x001fbe61, 0x0001ca6a, 0x00039374, 0x00051cfd, 0x0006ec0b, 0x00087515, 0x0009fe9e, 0x000b4aa7, 0x000cd3b1, 0x000e9d3a, 0x00000000, 0x00000000, }; static const uint32_t bwn_ntab_tdi40a1_r3[] = { 0x001edb36, 0x000129ca, 0x0002b353, 0x00047cdd, 0x0005c8e6, 0x000791ef, 0x00091bf9, 0x000aaa07, 0x000c3391, 0x000dfd1a, 0x00120923, 0x0013d22d, 0x00155c37, 0x0016eacb, 0x00187454, 0x001a3dde, 0x001b89e7, 0x001d12f0, 0x001f1cfa, 0x00016b88, 0x00033492, 0x0004be1b, 0x00060a24, 0x0007d32e, 0x00095d38, 0x000aec4c, 0x000c7555, 0x000e3edf, 0x00124ae8, 0x001413f1, 0x0015a37b, 0x00172c89, 0x0018b593, 0x001a419c, 0x001bcb25, 0x001d942f, 0x001f63b9, 0x0001ad4d, 0x00037657, 0x0004c260, 0x00068be9, 0x000814f3, 0x0009a47c, 0x000b2d8a, 0x000cb694, 0x000e429d, 0x00128c26, 0x001455b0, 0x0015e4ba, 0x00176e4e, 0x0018f758, 0x001a8361, 0x001c0cea, 0x001dd674, 0x001fa57d, 0x0001ee8b, 0x0003b795, 0x0005039e, 0x0006cd27, 0x000856b1, 0x0009e5c6, 0x000b6f4f, 0x000cf859, 0x000e8462, 0x00130deb, 0x00149775, 0x00162603, 0x0017af8c, 0x00193896, 0x001ac49f, 0x001c4e28, 0x001e17b2, 0x0000a6c7, 0x00023050, 0x0003f9da, 0x00054563, 0x00070eec, 0x00089876, 0x000a2704, 0x000bb08d, 0x000d3a17, 0x001185a0, 0x00134f29, 0x0014d8b3, 0x001667c8, 0x0017f151, 0x00197adb, 0x001b0664, 0x001c8fed, 0x001e5977, 0x0000e805, 0x0002718f, 0x00043b18, 0x000586a1, 0x0007502b, 0x0008d9b4, 0x000a68c9, 0x000bf252, 0x000dbbdc, 0x0011c7e5, 0x001390ee, 0x00151a78, 0x0016a906, 0x00183290, 0x0019bc19, 0x001b4822, 0x001cd12c, 0x001e9ab5, 0x00000000, 0x00000000, }; static const uint32_t bwn_ntab_pilotlt_r3[] = { 0x76540213, 0x62407351, 0x76543210, 0x76540213, 0x76540213, 0x76430521, }; static const uint32_t bwn_ntab_channelest_r3[] = { 0x44444444, 0x44444444, 0x44444444, 0x44444444, 0x44444444, 0x44444444, 0x44444444, 0x44444444, 0x10101010, 0x10101010, 0x10101010, 0x10101010, 0x10101010, 0x10101010, 0x10101010, 0x10101010, 0x44444444, 0x44444444, 0x44444444, 0x44444444, 0x44444444, 0x44444444, 0x44444444, 0x44444444, 0x10101010, 0x10101010, 0x10101010, 0x10101010, 0x10101010, 0x10101010, 0x10101010, 0x10101010, 0x44444444, 0x44444444, 0x44444444, 0x44444444, 0x44444444, 0x44444444, 0x44444444, 0x44444444, 0x44444444, 0x44444444, 0x44444444, 0x44444444, 0x44444444, 0x44444444, 0x44444444, 0x44444444, 0x10101010, 0x10101010, 0x10101010, 0x10101010, 0x10101010, 0x10101010, 0x10101010, 0x10101010, 0x10101010, 0x10101010, 0x10101010, 0x10101010, 0x10101010, 0x10101010, 0x10101010, 0x10101010, 0x44444444, 0x44444444, 0x44444444, 0x44444444, 0x44444444, 0x44444444, 0x44444444, 0x44444444, 0x44444444, 0x44444444, 0x44444444, 0x44444444, 0x44444444, 0x44444444, 0x44444444, 0x44444444, 0x10101010, 0x10101010, 0x10101010, 0x10101010, 0x10101010, 0x10101010, 0x10101010, 0x10101010, 0x10101010, 0x10101010, 0x10101010, 0x10101010, 0x10101010, 0x10101010, 0x10101010, 0x10101010, }; static const uint8_t bwn_ntab_framelookup_r3[] = { 0x02, 0x04, 0x14, 0x14, 0x03, 0x05, 0x16, 0x16, 0x0a, 0x0c, 0x1c, 0x1c, 0x0b, 0x0d, 0x1e, 0x1e, 0x06, 0x08, 0x18, 0x18, 0x07, 0x09, 0x1a, 0x1a, 0x0e, 0x10, 0x20, 0x28, 0x0f, 0x11, 0x22, 0x2a, }; static const uint8_t bwn_ntab_estimatepowerlt0_r3[] = { 0x55, 0x54, 0x54, 0x53, 0x52, 0x52, 0x51, 0x51, 0x50, 0x4f, 0x4f, 0x4e, 0x4e, 0x4d, 0x4c, 0x4c, 0x4b, 0x4a, 0x49, 0x49, 0x48, 0x47, 0x46, 0x46, 0x45, 0x44, 0x43, 0x42, 0x41, 0x40, 0x40, 0x3f, 0x3e, 0x3d, 0x3c, 0x3a, 0x39, 0x38, 0x37, 0x36, 0x35, 0x33, 0x32, 0x31, 0x2f, 0x2e, 0x2c, 0x2b, 0x29, 0x27, 0x25, 0x23, 0x21, 0x1f, 0x1d, 0x1a, 0x18, 0x15, 0x12, 0x0e, 0x0b, 0x07, 0x02, 0xfd, }; static const uint8_t bwn_ntab_estimatepowerlt1_r3[] = { 0x55, 0x54, 0x54, 0x53, 0x52, 0x52, 0x51, 0x51, 0x50, 0x4f, 0x4f, 0x4e, 0x4e, 0x4d, 0x4c, 0x4c, 0x4b, 0x4a, 0x49, 0x49, 0x48, 0x47, 0x46, 0x46, 0x45, 0x44, 0x43, 0x42, 0x41, 0x40, 0x40, 0x3f, 0x3e, 0x3d, 0x3c, 0x3a, 0x39, 0x38, 0x37, 0x36, 0x35, 0x33, 0x32, 0x31, 0x2f, 0x2e, 0x2c, 0x2b, 0x29, 0x27, 0x25, 0x23, 0x21, 0x1f, 0x1d, 0x1a, 0x18, 0x15, 0x12, 0x0e, 0x0b, 0x07, 0x02, 0xfd, }; static const uint8_t bwn_ntab_adjustpower0_r3[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, }; static const uint8_t bwn_ntab_adjustpower1_r3[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, }; static const uint32_t bwn_ntab_gainctl0_r3[] = { 0x5bf70044, 0x5bf70042, 0x5bf70040, 0x5bf7003e, 0x5bf7003c, 0x5bf7003b, 0x5bf70039, 0x5bf70037, 0x5bf70036, 0x5bf70034, 0x5bf70033, 0x5bf70031, 0x5bf70030, 0x5ba70044, 0x5ba70042, 0x5ba70040, 0x5ba7003e, 0x5ba7003c, 0x5ba7003b, 0x5ba70039, 0x5ba70037, 0x5ba70036, 0x5ba70034, 0x5ba70033, 0x5b770044, 0x5b770042, 0x5b770040, 0x5b77003e, 0x5b77003c, 0x5b77003b, 0x5b770039, 0x5b770037, 0x5b770036, 0x5b770034, 0x5b770033, 0x5b770031, 0x5b770030, 0x5b77002f, 0x5b77002d, 0x5b77002c, 0x5b470044, 0x5b470042, 0x5b470040, 0x5b47003e, 0x5b47003c, 0x5b47003b, 0x5b470039, 0x5b470037, 0x5b470036, 0x5b470034, 0x5b470033, 0x5b470031, 0x5b470030, 0x5b47002f, 0x5b47002d, 0x5b47002c, 0x5b47002b, 0x5b47002a, 0x5b270044, 0x5b270042, 0x5b270040, 0x5b27003e, 0x5b27003c, 0x5b27003b, 0x5b270039, 0x5b270037, 0x5b270036, 0x5b270034, 0x5b270033, 0x5b270031, 0x5b270030, 0x5b27002f, 0x5b170044, 0x5b170042, 0x5b170040, 0x5b17003e, 0x5b17003c, 0x5b17003b, 0x5b170039, 0x5b170037, 0x5b170036, 0x5b170034, 0x5b170033, 0x5b170031, 0x5b170030, 0x5b17002f, 0x5b17002d, 0x5b17002c, 0x5b17002b, 0x5b17002a, 0x5b170028, 0x5b170027, 0x5b170026, 0x5b170025, 0x5b170024, 0x5b170023, 0x5b070044, 0x5b070042, 0x5b070040, 0x5b07003e, 0x5b07003c, 0x5b07003b, 0x5b070039, 0x5b070037, 0x5b070036, 0x5b070034, 0x5b070033, 0x5b070031, 0x5b070030, 0x5b07002f, 0x5b07002d, 0x5b07002c, 0x5b07002b, 0x5b07002a, 0x5b070028, 0x5b070027, 0x5b070026, 0x5b070025, 0x5b070024, 0x5b070023, 0x5b070022, 0x5b070021, 0x5b070020, 0x5b07001f, 0x5b07001e, 0x5b07001d, 0x5b07001d, 0x5b07001c, }; static const uint32_t bwn_ntab_gainctl1_r3[] = { 0x5bf70044, 0x5bf70042, 0x5bf70040, 0x5bf7003e, 0x5bf7003c, 0x5bf7003b, 0x5bf70039, 0x5bf70037, 0x5bf70036, 0x5bf70034, 0x5bf70033, 0x5bf70031, 0x5bf70030, 0x5ba70044, 0x5ba70042, 0x5ba70040, 0x5ba7003e, 0x5ba7003c, 0x5ba7003b, 0x5ba70039, 0x5ba70037, 0x5ba70036, 0x5ba70034, 0x5ba70033, 0x5b770044, 0x5b770042, 0x5b770040, 0x5b77003e, 0x5b77003c, 0x5b77003b, 0x5b770039, 0x5b770037, 0x5b770036, 0x5b770034, 0x5b770033, 0x5b770031, 0x5b770030, 0x5b77002f, 0x5b77002d, 0x5b77002c, 0x5b470044, 0x5b470042, 0x5b470040, 0x5b47003e, 0x5b47003c, 0x5b47003b, 0x5b470039, 0x5b470037, 0x5b470036, 0x5b470034, 0x5b470033, 0x5b470031, 0x5b470030, 0x5b47002f, 0x5b47002d, 0x5b47002c, 0x5b47002b, 0x5b47002a, 0x5b270044, 0x5b270042, 0x5b270040, 0x5b27003e, 0x5b27003c, 0x5b27003b, 0x5b270039, 0x5b270037, 0x5b270036, 0x5b270034, 0x5b270033, 0x5b270031, 0x5b270030, 0x5b27002f, 0x5b170044, 0x5b170042, 0x5b170040, 0x5b17003e, 0x5b17003c, 0x5b17003b, 0x5b170039, 0x5b170037, 0x5b170036, 0x5b170034, 0x5b170033, 0x5b170031, 0x5b170030, 0x5b17002f, 0x5b17002d, 0x5b17002c, 0x5b17002b, 0x5b17002a, 0x5b170028, 0x5b170027, 0x5b170026, 0x5b170025, 0x5b170024, 0x5b170023, 0x5b070044, 0x5b070042, 0x5b070040, 0x5b07003e, 0x5b07003c, 0x5b07003b, 0x5b070039, 0x5b070037, 0x5b070036, 0x5b070034, 0x5b070033, 0x5b070031, 0x5b070030, 0x5b07002f, 0x5b07002d, 0x5b07002c, 0x5b07002b, 0x5b07002a, 0x5b070028, 0x5b070027, 0x5b070026, 0x5b070025, 0x5b070024, 0x5b070023, 0x5b070022, 0x5b070021, 0x5b070020, 0x5b07001f, 0x5b07001e, 0x5b07001d, 0x5b07001d, 0x5b07001c, }; static const uint32_t bwn_ntab_iqlt0_r3[] = { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, }; static const uint32_t bwn_ntab_iqlt1_r3[] = { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, }; static const uint16_t bwn_ntab_loftlt0_r3[] = { 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, }; static const uint16_t bwn_ntab_loftlt1_r3[] = { 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, }; /* volatile tables, PHY revision >= 3 */ /* indexed by antswctl2g */ static const uint16_t bwn_ntab_antswctl_r3[4][32] = { { 0x0082, 0x0082, 0x0211, 0x0222, 0x0328, 0x0000, 0x0000, 0x0000, 0x0144, 0x0000, 0x0000, 0x0000, 0x0188, 0x0000, 0x0000, 0x0000, 0x0082, 0x0082, 0x0211, 0x0222, 0x0328, 0x0000, 0x0000, 0x0000, 0x0144, 0x0000, 0x0000, 0x0000, 0x0188, 0x0000, 0x0000, 0x0000, }, { 0x0022, 0x0022, 0x0011, 0x0022, 0x0022, 0x0000, 0x0000, 0x0000, 0x0011, 0x0000, 0x0000, 0x0000, 0x0022, 0x0000, 0x0000, 0x0000, 0x0022, 0x0022, 0x0011, 0x0022, 0x0022, 0x0000, 0x0000, 0x0000, 0x0011, 0x0000, 0x0000, 0x0000, 0x0022, 0x0000, 0x0000, 0x0000, }, { 0x0088, 0x0088, 0x0044, 0x0088, 0x0088, 0x0000, 0x0000, 0x0000, 0x0044, 0x0000, 0x0000, 0x0000, 0x0088, 0x0000, 0x0000, 0x0000, 0x0088, 0x0088, 0x0044, 0x0088, 0x0088, 0x0000, 0x0000, 0x0000, 0x0044, 0x0000, 0x0000, 0x0000, 0x0088, 0x0000, 0x0000, 0x0000, }, { 0x0022, 0x0022, 0x0011, 0x0022, 0x0000, 0x0000, 0x0000, 0x0000, 0x0011, 0x0000, 0x0000, 0x0000, 0x0022, 0x0000, 0x0000, 0x03cc, 0x0022, 0x0022, 0x0011, 0x0022, 0x0000, 0x0000, 0x0000, 0x0000, 0x0011, 0x0000, 0x0000, 0x0000, 0x0022, 0x0000, 0x0000, 0x03cc, } }; /* static tables, PHY revision >= 7 */ /* Copied from brcmsmac (5.75.11) */ static const uint32_t bwn_ntab_tmap_r7[] = { 0x8a88aa80, 0x8aaaaa8a, 0x8a8a8aa8, 0x00000888, 0x88000000, 0x8a8a88aa, 0x8aa88888, 0x8888a8a8, 0xf1111110, 0x11111111, 0x11f11111, 0x00000111, 0x11000000, 0x1111f111, 0x11111111, 0x111111f1, 0x8a88aa80, 0x8aaaaa8a, 0x8a8a8aa8, 0x000aa888, 0x88880000, 0x8a8a88aa, 0x8aa88888, 0x8888a8a8, 0xa1111110, 0x11111111, 0x11c11111, 0x00000111, 0x11000000, 0x1111a111, 0x11111111, 0x111111a1, 0xa2222220, 0x22222222, 0x22c22222, 0x00000222, 0x22000000, 0x2222a222, 0x22222222, 0x222222a2, 0xf1111110, 0x11111111, 0x11f11111, 0x00011111, 0x11110000, 0x1111f111, 0x11111111, 0x111111f1, 0xa8aa88a0, 0xa88888a8, 0xa8a8a88a, 0x00088aaa, 0xaaaa0000, 0xa8a8aa88, 0xa88aaaaa, 0xaaaa8a8a, 0xaaa8aaa0, 0x8aaa8aaa, 0xaa8a8a8a, 0x000aaa88, 0x8aaa0000, 0xaaa8a888, 0x8aa88a8a, 0x8a88a888, 0x08080a00, 0x0a08080a, 0x080a0a08, 0x00080808, 0x080a0000, 0x080a0808, 0x080a0808, 0x0a0a0a08, 0xa0a0a0a0, 0x80a0a080, 0x8080a0a0, 0x00008080, 0x80a00000, 0x80a080a0, 0xa080a0a0, 0x8080a0a0, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x99999000, 0x9b9b99bb, 0x9bb99999, 0x9999b9b9, 0x9b99bb90, 0x9bbbbb9b, 0x9b9b9bb9, 0x00000999, 0x88000000, 0x8a8a88aa, 0x8aa88888, 0x8888a8a8, 0x8a88aa80, 0x8aaaaa8a, 0x8a8a8aa8, 0x00aaa888, 0x22000000, 0x2222b222, 0x22222222, 0x222222b2, 0xb2222220, 0x22222222, 0x22d22222, 0x00000222, 0x11000000, 0x1111a111, 0x11111111, 0x111111a1, 0xa1111110, 0x11111111, 0x11c11111, 0x00000111, 0x33000000, 0x3333b333, 0x33333333, 0x333333b3, 0xb3333330, 0x33333333, 0x33d33333, 0x00000333, 0x22000000, 0x2222a222, 0x22222222, 0x222222a2, 0xa2222220, 0x22222222, 0x22c22222, 0x00000222, 0x99b99b00, 0x9b9b99bb, 0x9bb99999, 0x9999b9b9, 0x9b99bb99, 0x9bbbbb9b, 0x9b9b9bb9, 0x00000999, 0x88000000, 0x8a8a88aa, 0x8aa88888, 0x8888a8a8, 0x8a88aa88, 0x8aaaaa8a, 0x8a8a8aa8, 0x08aaa888, 0x22222200, 0x2222f222, 0x22222222, 0x222222f2, 0x22222222, 0x22222222, 0x22f22222, 0x00000222, 0x11000000, 0x1111f111, 0x11111111, 0x11111111, 0xf1111111, 0x11111111, 0x11f11111, 0x01111111, 0xbb9bb900, 0xb9b9bb99, 0xb99bbbbb, 0xbbbb9b9b, 0xb9bb99bb, 0xb99999b9, 0xb9b9b99b, 0x00000bbb, 0xaa000000, 0xa8a8aa88, 0xa88aaaaa, 0xaaaa8a8a, 0xa8aa88aa, 0xa88888a8, 0xa8a8a88a, 0x0a888aaa, 0xaa000000, 0xa8a8aa88, 0xa88aaaaa, 0xaaaa8a8a, 0xa8aa88a0, 0xa88888a8, 0xa8a8a88a, 0x00000aaa, 0x88000000, 0x8a8a88aa, 0x8aa88888, 0x8888a8a8, 0x8a88aa80, 0x8aaaaa8a, 0x8a8a8aa8, 0x00000888, 0xbbbbbb00, 0x999bbbbb, 0x9bb99b9b, 0xb9b9b9bb, 0xb9b99bbb, 0xb9b9b9bb, 0xb9bb9b99, 0x00000999, 0x8a000000, 0xaa88a888, 0xa88888aa, 0xa88a8a88, 0xa88aa88a, 0x88a8aaaa, 0xa8aa8aaa, 0x0888a88a, 0x0b0b0b00, 0x090b0b0b, 0x0b090b0b, 0x0909090b, 0x09090b0b, 0x09090b0b, 0x09090b09, 0x00000909, 0x0a000000, 0x0a080808, 0x080a080a, 0x080a0a08, 0x080a080a, 0x0808080a, 0x0a0a0a08, 0x0808080a, 0xb0b0b000, 0x9090b0b0, 0x90b09090, 0xb0b0b090, 0xb0b090b0, 0x90b0b0b0, 0xb0b09090, 0x00000090, 0x80000000, 0xa080a080, 0xa08080a0, 0xa0808080, 0xa080a080, 0x80a0a0a0, 0xa0a080a0, 0x00a0a0a0, 0x22000000, 0x2222f222, 0x22222222, 0x222222f2, 0xf2222220, 0x22222222, 0x22f22222, 0x00000222, 0x11000000, 0x1111f111, 0x11111111, 0x111111f1, 0xf1111110, 0x11111111, 0x11f11111, 0x00000111, 0x33000000, 0x3333f333, 0x33333333, 0x333333f3, 0xf3333330, 0x33333333, 0x33f33333, 0x00000333, 0x22000000, 0x2222f222, 0x22222222, 0x222222f2, 0xf2222220, 0x22222222, 0x22f22222, 0x00000222, 0x99000000, 0x9b9b99bb, 0x9bb99999, 0x9999b9b9, 0x9b99bb90, 0x9bbbbb9b, 0x9b9b9bb9, 0x00000999, 0x88000000, 0x8a8a88aa, 0x8aa88888, 0x8888a8a8, 0x8a88aa80, 0x8aaaaa8a, 0x8a8a8aa8, 0x00000888, 0x88888000, 0x8a8a88aa, 0x8aa88888, 0x8888a8a8, 0x8a88aa80, 0x8aaaaa8a, 0x8a8a8aa8, 0x00000888, 0x88000000, 0x8a8a88aa, 0x8aa88888, 0x8888a8a8, 0x8a88aa80, 0x8aaaaa8a, 0x8a8a8aa8, 0x00aaa888, 0x88a88a00, 0x8a8a88aa, 0x8aa88888, 0x8888a8a8, 0x8a88aa88, 0x8aaaaa8a, 0x8a8a8aa8, 0x000aa888, 0x88880000, 0x8a8a88aa, 0x8aa88888, 0x8888a8a8, 0x8a88aa88, 0x8aaaaa8a, 0x8a8a8aa8, 0x08aaa888, 0x11000000, 0x1111a111, 0x11111111, 0x111111a1, 0xa1111110, 0x11111111, 0x11c11111, 0x00000111, 0x11000000, 0x1111a111, 0x11111111, 0x111111a1, 0xa1111110, 0x11111111, 0x11c11111, 0x00000111, 0x88000000, 0x8a8a88aa, 0x8aa88888, 0x8888a8a8, 0x8a88aa80, 0x8aaaaa8a, 0x8a8a8aa8, 0x00000888, 0x88000000, 0x8a8a88aa, 0x8aa88888, 0x8888a8a8, 0x8a88aa80, 0x8aaaaa8a, 0x8a8a8aa8, 0x00000888, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, }; /* Extracted from MMIO dump of 6.30.223.141 */ static const uint32_t bwn_ntab_noisevar_r7[] = { 0x020c020c, 0x0000014d, 0x020c020c, 0x0000014d, 0x020c020c, 0x0000014d, 0x020c020c, 0x0000014d, 0x020c020c, 0x0000014d, 0x020c020c, 0x0000014d, 0x020c020c, 0x0000014d, 0x020c020c, 0x0000014d, 0x020c020c, 0x0000014d, 0x020c020c, 0x0000014d, 0x020c020c, 0x0000014d, 0x020c020c, 0x0000014d, 0x020c020c, 0x0000014d, 0x020c020c, 0x0000014d, 0x020c020c, 0x0000014d, 0x020c020c, 0x0000014d, 0x020c020c, 0x0000014d, 0x020c020c, 0x0000014d, 0x020c020c, 0x0000014d, 0x020c020c, 0x0000014d, 0x020c020c, 0x0000014d, 0x020c020c, 0x0000014d, 0x020c020c, 0x0000014d, 0x020c020c, 0x0000014d, 0x020c020c, 0x0000014d, 0x020c020c, 0x0000014d, 0x020c020c, 0x0000014d, 0x020c020c, 0x0000014d, 0x020c020c, 0x0000014d, 0x020c020c, 0x0000014d, 0x020c020c, 0x0000014d, 0x020c020c, 0x0000014d, 0x020c020c, 0x0000014d, 0x020c020c, 0x0000014d, 0x020c020c, 0x0000014d, 0x020c020c, 0x0000014d, 0x020c020c, 0x0000014d, 0x020c020c, 0x0000014d, 0x020c020c, 0x0000014d, 0x020c020c, 0x0000014d, 0x020c020c, 0x0000014d, 0x020c020c, 0x0000014d, 0x020c020c, 0x0000014d, 0x020c020c, 0x0000014d, 0x020c020c, 0x0000014d, 0x020c020c, 0x0000014d, 0x020c020c, 0x0000014d, 0x020c020c, 0x0000014d, 0x020c020c, 0x0000014d, 0x020c020c, 0x0000014d, 0x020c020c, 0x0000014d, 0x020c020c, 0x0000014d, 0x020c020c, 0x0000014d, 0x020c020c, 0x0000014d, 0x020c020c, 0x0000014d, 0x020c020c, 0x0000014d, 0x020c020c, 0x0000014d, 0x020c020c, 0x0000014d, 0x020c020c, 0x0000014d, 0x020c020c, 0x0000014d, 0x020c020c, 0x0000014d, 0x020c020c, 0x0000014d, 0x020c020c, 0x0000014d, 0x020c020c, 0x0000014d, 0x020c020c, 0x0000014d, 0x020c020c, 0x0000014d, 0x020c020c, 0x0000014d, 0x020c020c, 0x0000014d, 0x020c020c, 0x0000014d, 0x020c020c, 0x0000014d, 0x020c020c, 0x0000014d, 0x020c020c, 0x0000014d, 0x020c020c, 0x0000014d, 0x020c020c, 0x0000014d, 0x020c020c, 0x0000014d, 0x020c020c, 0x0000014d, 0x020c020c, 0x0000014d, 0x020c020c, 0x0000014d, 0x020c020c, 0x0000014d, 0x020c020c, 0x0000014d, 0x020c020c, 0x0000014d, 0x020c020c, 0x0000014d, 0x020c020c, 0x0000014d, 0x020c020c, 0x0000014d, 0x020c020c, 0x0000014d, 0x020c020c, 0x0000014d, 0x020c020c, 0x0000014d, 0x020c020c, 0x0000014d, 0x020c020c, 0x0000014d, 0x020c020c, 0x0000014d, 0x020c020c, 0x0000014d, 0x020c020c, 0x0000014d, 0x020c020c, 0x0000014d, 0x020c020c, 0x0000014d, 0x020c020c, 0x0000014d, 0x020c020c, 0x0000014d, 0x020c020c, 0x0000014d, 0x020c020c, 0x0000014d, 0x020c020c, 0x0000014d, 0x020c020c, 0x0000014d, 0x020c020c, 0x0000014d, 0x020c020c, 0x0000014d, 0x020c020c, 0x0000014d, 0x020c020c, 0x0000014d, 0x020c020c, 0x0000014d, 0x020c020c, 0x0000014d, 0x020c020c, 0x0000014d, 0x020c020c, 0x0000014d, 0x020c020c, 0x0000014d, 0x020c020c, 0x0000014d, 0x020c020c, 0x0000014d, 0x020c020c, 0x0000014d, 0x020c020c, 0x0000014d, 0x020c020c, 0x0000014d, 0x020c020c, 0x0000014d, 0x020c020c, 0x0000014d, 0x020c020c, 0x0000014d, 0x020c020c, 0x0000014d, 0x020c020c, 0x0000014d, 0x020c020c, 0x0000014d, 0x020c020c, 0x0000014d, 0x020c020c, 0x0000014d, 0x020c020c, 0x0000014d, 0x020c020c, 0x0000014d, 0x020c020c, 0x0000014d, 0x020c020c, 0x0000014d, 0x020c020c, 0x0000014d, 0x020c020c, 0x0000014d, }; /************************************************** * TX gain tables **************************************************/ static const uint32_t bwn_ntab_tx_gain_rev0_1_2[] = { 0x03cc2b44, 0x03cc2b42, 0x03cc2a44, 0x03cc2a42, 0x03cc2944, 0x03c82b44, 0x03c82b42, 0x03c82a44, 0x03c82a42, 0x03c82944, 0x03c82942, 0x03c82844, 0x03c82842, 0x03c42b44, 0x03c42b42, 0x03c42a44, 0x03c42a42, 0x03c42944, 0x03c42942, 0x03c42844, 0x03c42842, 0x03c42744, 0x03c42742, 0x03c42644, 0x03c42642, 0x03c42544, 0x03c42542, 0x03c42444, 0x03c42442, 0x03c02b44, 0x03c02b42, 0x03c02a44, 0x03c02a42, 0x03c02944, 0x03c02942, 0x03c02844, 0x03c02842, 0x03c02744, 0x03c02742, 0x03b02b44, 0x03b02b42, 0x03b02a44, 0x03b02a42, 0x03b02944, 0x03b02942, 0x03b02844, 0x03b02842, 0x03b02744, 0x03b02742, 0x03b02644, 0x03b02642, 0x03b02544, 0x03b02542, 0x03a02b44, 0x03a02b42, 0x03a02a44, 0x03a02a42, 0x03a02944, 0x03a02942, 0x03a02844, 0x03a02842, 0x03a02744, 0x03a02742, 0x03902b44, 0x03902b42, 0x03902a44, 0x03902a42, 0x03902944, 0x03902942, 0x03902844, 0x03902842, 0x03902744, 0x03902742, 0x03902644, 0x03902642, 0x03902544, 0x03902542, 0x03802b44, 0x03802b42, 0x03802a44, 0x03802a42, 0x03802944, 0x03802942, 0x03802844, 0x03802842, 0x03802744, 0x03802742, 0x03802644, 0x03802642, 0x03802544, 0x03802542, 0x03802444, 0x03802442, 0x03802344, 0x03802342, 0x03802244, 0x03802242, 0x03802144, 0x03802142, 0x03802044, 0x03802042, 0x03801f44, 0x03801f42, 0x03801e44, 0x03801e42, 0x03801d44, 0x03801d42, 0x03801c44, 0x03801c42, 0x03801b44, 0x03801b42, 0x03801a44, 0x03801a42, 0x03801944, 0x03801942, 0x03801844, 0x03801842, 0x03801744, 0x03801742, 0x03801644, 0x03801642, 0x03801544, 0x03801542, 0x03801444, 0x03801442, 0x03801344, 0x03801342, 0x00002b00, }; /* EPA 2 GHz */ static const uint32_t bwn_ntab_tx_gain_epa_rev3_2g[] = { 0x1f410044, 0x1f410042, 0x1f410040, 0x1f41003e, 0x1f41003c, 0x1f41003b, 0x1f410039, 0x1f410037, 0x1e410044, 0x1e410042, 0x1e410040, 0x1e41003e, 0x1e41003c, 0x1e41003b, 0x1e410039, 0x1e410037, 0x1d410044, 0x1d410042, 0x1d410040, 0x1d41003e, 0x1d41003c, 0x1d41003b, 0x1d410039, 0x1d410037, 0x1c410044, 0x1c410042, 0x1c410040, 0x1c41003e, 0x1c41003c, 0x1c41003b, 0x1c410039, 0x1c410037, 0x1b410044, 0x1b410042, 0x1b410040, 0x1b41003e, 0x1b41003c, 0x1b41003b, 0x1b410039, 0x1b410037, 0x1a410044, 0x1a410042, 0x1a410040, 0x1a41003e, 0x1a41003c, 0x1a41003b, 0x1a410039, 0x1a410037, 0x19410044, 0x19410042, 0x19410040, 0x1941003e, 0x1941003c, 0x1941003b, 0x19410039, 0x19410037, 0x18410044, 0x18410042, 0x18410040, 0x1841003e, 0x1841003c, 0x1841003b, 0x18410039, 0x18410037, 0x17410044, 0x17410042, 0x17410040, 0x1741003e, 0x1741003c, 0x1741003b, 0x17410039, 0x17410037, 0x16410044, 0x16410042, 0x16410040, 0x1641003e, 0x1641003c, 0x1641003b, 0x16410039, 0x16410037, 0x15410044, 0x15410042, 0x15410040, 0x1541003e, 0x1541003c, 0x1541003b, 0x15410039, 0x15410037, 0x14410044, 0x14410042, 0x14410040, 0x1441003e, 0x1441003c, 0x1441003b, 0x14410039, 0x14410037, 0x13410044, 0x13410042, 0x13410040, 0x1341003e, 0x1341003c, 0x1341003b, 0x13410039, 0x13410037, 0x12410044, 0x12410042, 0x12410040, 0x1241003e, 0x1241003c, 0x1241003b, 0x12410039, 0x12410037, 0x11410044, 0x11410042, 0x11410040, 0x1141003e, 0x1141003c, 0x1141003b, 0x11410039, 0x11410037, 0x10410044, 0x10410042, 0x10410040, 0x1041003e, 0x1041003c, 0x1041003b, 0x10410039, 0x10410037, }; static const uint32_t bwn_ntab_tx_gain_epa_rev3_hi_pwr_2g[] = { 0x0f410044, 0x0f410042, 0x0f410040, 0x0f41003e, 0x0f41003c, 0x0f41003b, 0x0f410039, 0x0f410037, 0x0e410044, 0x0e410042, 0x0e410040, 0x0e41003e, 0x0e41003c, 0x0e41003b, 0x0e410039, 0x0e410037, 0x0d410044, 0x0d410042, 0x0d410040, 0x0d41003e, 0x0d41003c, 0x0d41003b, 0x0d410039, 0x0d410037, 0x0c410044, 0x0c410042, 0x0c410040, 0x0c41003e, 0x0c41003c, 0x0c41003b, 0x0c410039, 0x0c410037, 0x0b410044, 0x0b410042, 0x0b410040, 0x0b41003e, 0x0b41003c, 0x0b41003b, 0x0b410039, 0x0b410037, 0x0a410044, 0x0a410042, 0x0a410040, 0x0a41003e, 0x0a41003c, 0x0a41003b, 0x0a410039, 0x0a410037, 0x09410044, 0x09410042, 0x09410040, 0x0941003e, 0x0941003c, 0x0941003b, 0x09410039, 0x09410037, 0x08410044, 0x08410042, 0x08410040, 0x0841003e, 0x0841003c, 0x0841003b, 0x08410039, 0x08410037, 0x07410044, 0x07410042, 0x07410040, 0x0741003e, 0x0741003c, 0x0741003b, 0x07410039, 0x07410037, 0x06410044, 0x06410042, 0x06410040, 0x0641003e, 0x0641003c, 0x0641003b, 0x06410039, 0x06410037, 0x05410044, 0x05410042, 0x05410040, 0x0541003e, 0x0541003c, 0x0541003b, 0x05410039, 0x05410037, 0x04410044, 0x04410042, 0x04410040, 0x0441003e, 0x0441003c, 0x0441003b, 0x04410039, 0x04410037, 0x03410044, 0x03410042, 0x03410040, 0x0341003e, 0x0341003c, 0x0341003b, 0x03410039, 0x03410037, 0x02410044, 0x02410042, 0x02410040, 0x0241003e, 0x0241003c, 0x0241003b, 0x02410039, 0x02410037, 0x01410044, 0x01410042, 0x01410040, 0x0141003e, 0x0141003c, 0x0141003b, 0x01410039, 0x01410037, 0x00410044, 0x00410042, 0x00410040, 0x0041003e, 0x0041003c, 0x0041003b, 0x00410039, 0x00410037 }; /* EPA 5 GHz */ static const uint32_t bwn_ntab_tx_gain_epa_rev3_5g[] = { 0xcff70044, 0xcff70042, 0xcff70040, 0xcff7003e, 0xcff7003c, 0xcff7003b, 0xcff70039, 0xcff70037, 0xcef70044, 0xcef70042, 0xcef70040, 0xcef7003e, 0xcef7003c, 0xcef7003b, 0xcef70039, 0xcef70037, 0xcdf70044, 0xcdf70042, 0xcdf70040, 0xcdf7003e, 0xcdf7003c, 0xcdf7003b, 0xcdf70039, 0xcdf70037, 0xccf70044, 0xccf70042, 0xccf70040, 0xccf7003e, 0xccf7003c, 0xccf7003b, 0xccf70039, 0xccf70037, 0xcbf70044, 0xcbf70042, 0xcbf70040, 0xcbf7003e, 0xcbf7003c, 0xcbf7003b, 0xcbf70039, 0xcbf70037, 0xcaf70044, 0xcaf70042, 0xcaf70040, 0xcaf7003e, 0xcaf7003c, 0xcaf7003b, 0xcaf70039, 0xcaf70037, 0xc9f70044, 0xc9f70042, 0xc9f70040, 0xc9f7003e, 0xc9f7003c, 0xc9f7003b, 0xc9f70039, 0xc9f70037, 0xc8f70044, 0xc8f70042, 0xc8f70040, 0xc8f7003e, 0xc8f7003c, 0xc8f7003b, 0xc8f70039, 0xc8f70037, 0xc7f70044, 0xc7f70042, 0xc7f70040, 0xc7f7003e, 0xc7f7003c, 0xc7f7003b, 0xc7f70039, 0xc7f70037, 0xc6f70044, 0xc6f70042, 0xc6f70040, 0xc6f7003e, 0xc6f7003c, 0xc6f7003b, 0xc6f70039, 0xc6f70037, 0xc5f70044, 0xc5f70042, 0xc5f70040, 0xc5f7003e, 0xc5f7003c, 0xc5f7003b, 0xc5f70039, 0xc5f70037, 0xc4f70044, 0xc4f70042, 0xc4f70040, 0xc4f7003e, 0xc4f7003c, 0xc4f7003b, 0xc4f70039, 0xc4f70037, 0xc3f70044, 0xc3f70042, 0xc3f70040, 0xc3f7003e, 0xc3f7003c, 0xc3f7003b, 0xc3f70039, 0xc3f70037, 0xc2f70044, 0xc2f70042, 0xc2f70040, 0xc2f7003e, 0xc2f7003c, 0xc2f7003b, 0xc2f70039, 0xc2f70037, 0xc1f70044, 0xc1f70042, 0xc1f70040, 0xc1f7003e, 0xc1f7003c, 0xc1f7003b, 0xc1f70039, 0xc1f70037, 0xc0f70044, 0xc0f70042, 0xc0f70040, 0xc0f7003e, 0xc0f7003c, 0xc0f7003b, 0xc0f70039, 0xc0f70037, }; static const uint32_t bwn_ntab_tx_gain_epa_rev4_5g[] = { 0x2ff20044, 0x2ff20042, 0x2ff20040, 0x2ff2003e, 0x2ff2003c, 0x2ff2003b, 0x2ff20039, 0x2ff20037, 0x2ef20044, 0x2ef20042, 0x2ef20040, 0x2ef2003e, 0x2ef2003c, 0x2ef2003b, 0x2ef20039, 0x2ef20037, 0x2df20044, 0x2df20042, 0x2df20040, 0x2df2003e, 0x2df2003c, 0x2df2003b, 0x2df20039, 0x2df20037, 0x2cf20044, 0x2cf20042, 0x2cf20040, 0x2cf2003e, 0x2cf2003c, 0x2cf2003b, 0x2cf20039, 0x2cf20037, 0x2bf20044, 0x2bf20042, 0x2bf20040, 0x2bf2003e, 0x2bf2003c, 0x2bf2003b, 0x2bf20039, 0x2bf20037, 0x2af20044, 0x2af20042, 0x2af20040, 0x2af2003e, 0x2af2003c, 0x2af2003b, 0x2af20039, 0x2af20037, 0x29f20044, 0x29f20042, 0x29f20040, 0x29f2003e, 0x29f2003c, 0x29f2003b, 0x29f20039, 0x29f20037, 0x28f20044, 0x28f20042, 0x28f20040, 0x28f2003e, 0x28f2003c, 0x28f2003b, 0x28f20039, 0x28f20037, 0x27f20044, 0x27f20042, 0x27f20040, 0x27f2003e, 0x27f2003c, 0x27f2003b, 0x27f20039, 0x27f20037, 0x26f20044, 0x26f20042, 0x26f20040, 0x26f2003e, 0x26f2003c, 0x26f2003b, 0x26f20039, 0x26f20037, 0x25f20044, 0x25f20042, 0x25f20040, 0x25f2003e, 0x25f2003c, 0x25f2003b, 0x25f20039, 0x25f20037, 0x24f20044, 0x24f20042, 0x24f20040, 0x24f2003e, 0x24f2003c, 0x24f2003b, 0x24f20039, 0x24f20038, 0x23f20041, 0x23f20040, 0x23f2003f, 0x23f2003e, 0x23f2003c, 0x23f2003b, 0x23f20039, 0x23f20037, 0x22f20044, 0x22f20042, 0x22f20040, 0x22f2003e, 0x22f2003c, 0x22f2003b, 0x22f20039, 0x22f20037, 0x21f20044, 0x21f20042, 0x21f20040, 0x21f2003e, 0x21f2003c, 0x21f2003b, 0x21f20039, 0x21f20037, 0x20d20043, 0x20d20041, 0x20d2003e, 0x20d2003c, 0x20d2003a, 0x20d20038, 0x20d20036, 0x20d20034, }; static const uint32_t bwn_ntab_tx_gain_epa_rev4_hi_pwr_5g[] = { 0x2ff10044, 0x2ff10042, 0x2ff10040, 0x2ff1003e, 0x2ff1003c, 0x2ff1003b, 0x2ff10039, 0x2ff10037, 0x2ef10044, 0x2ef10042, 0x2ef10040, 0x2ef1003e, 0x2ef1003c, 0x2ef1003b, 0x2ef10039, 0x2ef10037, 0x2df10044, 0x2df10042, 0x2df10040, 0x2df1003e, 0x2df1003c, 0x2df1003b, 0x2df10039, 0x2df10037, 0x2cf10044, 0x2cf10042, 0x2cf10040, 0x2cf1003e, 0x2cf1003c, 0x2cf1003b, 0x2cf10039, 0x2cf10037, 0x2bf10044, 0x2bf10042, 0x2bf10040, 0x2bf1003e, 0x2bf1003c, 0x2bf1003b, 0x2bf10039, 0x2bf10037, 0x2af10044, 0x2af10042, 0x2af10040, 0x2af1003e, 0x2af1003c, 0x2af1003b, 0x2af10039, 0x2af10037, 0x29f10044, 0x29f10042, 0x29f10040, 0x29f1003e, 0x29f1003c, 0x29f1003b, 0x29f10039, 0x29f10037, 0x28f10044, 0x28f10042, 0x28f10040, 0x28f1003e, 0x28f1003c, 0x28f1003b, 0x28f10039, 0x28f10037, 0x27f10044, 0x27f10042, 0x27f10040, 0x27f1003e, 0x27f1003c, 0x27f1003b, 0x27f10039, 0x27f10037, 0x26f10044, 0x26f10042, 0x26f10040, 0x26f1003e, 0x26f1003c, 0x26f1003b, 0x26f10039, 0x26f10037, 0x25f10044, 0x25f10042, 0x25f10040, 0x25f1003e, 0x25f1003c, 0x25f1003b, 0x25f10039, 0x25f10037, 0x24f10044, 0x24f10042, 0x24f10040, 0x24f1003e, 0x24f1003c, 0x24f1003b, 0x24f10039, 0x24f10038, 0x23f10041, 0x23f10040, 0x23f1003f, 0x23f1003e, 0x23f1003c, 0x23f1003b, 0x23f10039, 0x23f10037, 0x22f10044, 0x22f10042, 0x22f10040, 0x22f1003e, 0x22f1003c, 0x22f1003b, 0x22f10039, 0x22f10037, 0x21f10044, 0x21f10042, 0x21f10040, 0x21f1003e, 0x21f1003c, 0x21f1003b, 0x21f10039, 0x21f10037, 0x20d10043, 0x20d10041, 0x20d1003e, 0x20d1003c, 0x20d1003a, 0x20d10038, 0x20d10036, 0x20d10034 }; static const uint32_t bwn_ntab_tx_gain_epa_rev5_5g[] = { 0x0f62004a, 0x0f620048, 0x0f620046, 0x0f620044, 0x0f620042, 0x0f620040, 0x0f62003e, 0x0f62003c, 0x0e620044, 0x0e620042, 0x0e620040, 0x0e62003e, 0x0e62003c, 0x0e62003d, 0x0e62003b, 0x0e62003a, 0x0d620043, 0x0d620041, 0x0d620040, 0x0d62003e, 0x0d62003d, 0x0d62003c, 0x0d62003b, 0x0d62003a, 0x0c620041, 0x0c620040, 0x0c62003f, 0x0c62003e, 0x0c62003c, 0x0c62003b, 0x0c620039, 0x0c620037, 0x0b620046, 0x0b620044, 0x0b620042, 0x0b620040, 0x0b62003e, 0x0b62003c, 0x0b62003b, 0x0b62003a, 0x0a620041, 0x0a620040, 0x0a62003e, 0x0a62003c, 0x0a62003b, 0x0a62003a, 0x0a620039, 0x0a620038, 0x0962003e, 0x0962003d, 0x0962003c, 0x0962003b, 0x09620039, 0x09620037, 0x09620035, 0x09620033, 0x08620044, 0x08620042, 0x08620040, 0x0862003e, 0x0862003c, 0x0862003b, 0x0862003a, 0x08620039, 0x07620043, 0x07620042, 0x07620040, 0x0762003f, 0x0762003d, 0x0762003b, 0x0762003a, 0x07620039, 0x0662003e, 0x0662003d, 0x0662003c, 0x0662003b, 0x06620039, 0x06620037, 0x06620035, 0x06620033, 0x05620046, 0x05620044, 0x05620042, 0x05620040, 0x0562003e, 0x0562003c, 0x0562003b, 0x05620039, 0x04620044, 0x04620042, 0x04620040, 0x0462003e, 0x0462003c, 0x0462003b, 0x04620039, 0x04620038, 0x0362003c, 0x0362003b, 0x0362003a, 0x03620039, 0x03620038, 0x03620037, 0x03620035, 0x03620033, 0x0262004c, 0x0262004a, 0x02620048, 0x02620047, 0x02620046, 0x02620044, 0x02620043, 0x02620042, 0x0162004a, 0x01620048, 0x01620046, 0x01620044, 0x01620043, 0x01620042, 0x01620041, 0x01620040, 0x00620042, 0x00620040, 0x0062003e, 0x0062003c, 0x0062003b, 0x00620039, 0x00620037, 0x00620035, }; /* IPA 2 GHz */ static const uint32_t bwn_ntab_tx_gain_ipa_rev3_2g[] = { 0x5ff7002d, 0x5ff7002b, 0x5ff7002a, 0x5ff70029, 0x5ff70028, 0x5ff70027, 0x5ff70026, 0x5ff70025, 0x5ef7002d, 0x5ef7002b, 0x5ef7002a, 0x5ef70029, 0x5ef70028, 0x5ef70027, 0x5ef70026, 0x5ef70025, 0x5df7002d, 0x5df7002b, 0x5df7002a, 0x5df70029, 0x5df70028, 0x5df70027, 0x5df70026, 0x5df70025, 0x5cf7002d, 0x5cf7002b, 0x5cf7002a, 0x5cf70029, 0x5cf70028, 0x5cf70027, 0x5cf70026, 0x5cf70025, 0x5bf7002d, 0x5bf7002b, 0x5bf7002a, 0x5bf70029, 0x5bf70028, 0x5bf70027, 0x5bf70026, 0x5bf70025, 0x5af7002d, 0x5af7002b, 0x5af7002a, 0x5af70029, 0x5af70028, 0x5af70027, 0x5af70026, 0x5af70025, 0x59f7002d, 0x59f7002b, 0x59f7002a, 0x59f70029, 0x59f70028, 0x59f70027, 0x59f70026, 0x59f70025, 0x58f7002d, 0x58f7002b, 0x58f7002a, 0x58f70029, 0x58f70028, 0x58f70027, 0x58f70026, 0x58f70025, 0x57f7002d, 0x57f7002b, 0x57f7002a, 0x57f70029, 0x57f70028, 0x57f70027, 0x57f70026, 0x57f70025, 0x56f7002d, 0x56f7002b, 0x56f7002a, 0x56f70029, 0x56f70028, 0x56f70027, 0x56f70026, 0x56f70025, 0x55f7002d, 0x55f7002b, 0x55f7002a, 0x55f70029, 0x55f70028, 0x55f70027, 0x55f70026, 0x55f70025, 0x54f7002d, 0x54f7002b, 0x54f7002a, 0x54f70029, 0x54f70028, 0x54f70027, 0x54f70026, 0x54f70025, 0x53f7002d, 0x53f7002b, 0x53f7002a, 0x53f70029, 0x53f70028, 0x53f70027, 0x53f70026, 0x53f70025, 0x52f7002d, 0x52f7002b, 0x52f7002a, 0x52f70029, 0x52f70028, 0x52f70027, 0x52f70026, 0x52f70025, 0x51f7002d, 0x51f7002b, 0x51f7002a, 0x51f70029, 0x51f70028, 0x51f70027, 0x51f70026, 0x51f70025, 0x50f7002d, 0x50f7002b, 0x50f7002a, 0x50f70029, 0x50f70028, 0x50f70027, 0x50f70026, 0x50f70025, }; static const uint32_t bwn_ntab_tx_gain_ipa_rev5_2g[] = { 0x1ff7002d, 0x1ff7002b, 0x1ff7002a, 0x1ff70029, 0x1ff70028, 0x1ff70027, 0x1ff70026, 0x1ff70025, 0x1ef7002d, 0x1ef7002b, 0x1ef7002a, 0x1ef70029, 0x1ef70028, 0x1ef70027, 0x1ef70026, 0x1ef70025, 0x1df7002d, 0x1df7002b, 0x1df7002a, 0x1df70029, 0x1df70028, 0x1df70027, 0x1df70026, 0x1df70025, 0x1cf7002d, 0x1cf7002b, 0x1cf7002a, 0x1cf70029, 0x1cf70028, 0x1cf70027, 0x1cf70026, 0x1cf70025, 0x1bf7002d, 0x1bf7002b, 0x1bf7002a, 0x1bf70029, 0x1bf70028, 0x1bf70027, 0x1bf70026, 0x1bf70025, 0x1af7002d, 0x1af7002b, 0x1af7002a, 0x1af70029, 0x1af70028, 0x1af70027, 0x1af70026, 0x1af70025, 0x19f7002d, 0x19f7002b, 0x19f7002a, 0x19f70029, 0x19f70028, 0x19f70027, 0x19f70026, 0x19f70025, 0x18f7002d, 0x18f7002b, 0x18f7002a, 0x18f70029, 0x18f70028, 0x18f70027, 0x18f70026, 0x18f70025, 0x17f7002d, 0x17f7002b, 0x17f7002a, 0x17f70029, 0x17f70028, 0x17f70027, 0x17f70026, 0x17f70025, 0x16f7002d, 0x16f7002b, 0x16f7002a, 0x16f70029, 0x16f70028, 0x16f70027, 0x16f70026, 0x16f70025, 0x15f7002d, 0x15f7002b, 0x15f7002a, 0x15f70029, 0x15f70028, 0x15f70027, 0x15f70026, 0x15f70025, 0x14f7002d, 0x14f7002b, 0x14f7002a, 0x14f70029, 0x14f70028, 0x14f70027, 0x14f70026, 0x14f70025, 0x13f7002d, 0x13f7002b, 0x13f7002a, 0x13f70029, 0x13f70028, 0x13f70027, 0x13f70026, 0x13f70025, 0x12f7002d, 0x12f7002b, 0x12f7002a, 0x12f70029, 0x12f70028, 0x12f70027, 0x12f70026, 0x12f70025, 0x11f7002d, 0x11f7002b, 0x11f7002a, 0x11f70029, 0x11f70028, 0x11f70027, 0x11f70026, 0x11f70025, 0x10f7002d, 0x10f7002b, 0x10f7002a, 0x10f70029, 0x10f70028, 0x10f70027, 0x10f70026, 0x10f70025, }; static const uint32_t bwn_ntab_tx_gain_ipa_rev6_2g[] = { 0x0ff7002d, 0x0ff7002b, 0x0ff7002a, 0x0ff70029, 0x0ff70028, 0x0ff70027, 0x0ff70026, 0x0ff70025, 0x0ef7002d, 0x0ef7002b, 0x0ef7002a, 0x0ef70029, 0x0ef70028, 0x0ef70027, 0x0ef70026, 0x0ef70025, 0x0df7002d, 0x0df7002b, 0x0df7002a, 0x0df70029, 0x0df70028, 0x0df70027, 0x0df70026, 0x0df70025, 0x0cf7002d, 0x0cf7002b, 0x0cf7002a, 0x0cf70029, 0x0cf70028, 0x0cf70027, 0x0cf70026, 0x0cf70025, 0x0bf7002d, 0x0bf7002b, 0x0bf7002a, 0x0bf70029, 0x0bf70028, 0x0bf70027, 0x0bf70026, 0x0bf70025, 0x0af7002d, 0x0af7002b, 0x0af7002a, 0x0af70029, 0x0af70028, 0x0af70027, 0x0af70026, 0x0af70025, 0x09f7002d, 0x09f7002b, 0x09f7002a, 0x09f70029, 0x09f70028, 0x09f70027, 0x09f70026, 0x09f70025, 0x08f7002d, 0x08f7002b, 0x08f7002a, 0x08f70029, 0x08f70028, 0x08f70027, 0x08f70026, 0x08f70025, 0x07f7002d, 0x07f7002b, 0x07f7002a, 0x07f70029, 0x07f70028, 0x07f70027, 0x07f70026, 0x07f70025, 0x06f7002d, 0x06f7002b, 0x06f7002a, 0x06f70029, 0x06f70028, 0x06f70027, 0x06f70026, 0x06f70025, 0x05f7002d, 0x05f7002b, 0x05f7002a, 0x05f70029, 0x05f70028, 0x05f70027, 0x05f70026, 0x05f70025, 0x04f7002d, 0x04f7002b, 0x04f7002a, 0x04f70029, 0x04f70028, 0x04f70027, 0x04f70026, 0x04f70025, 0x03f7002d, 0x03f7002b, 0x03f7002a, 0x03f70029, 0x03f70028, 0x03f70027, 0x03f70026, 0x03f70025, 0x02f7002d, 0x02f7002b, 0x02f7002a, 0x02f70029, 0x02f70028, 0x02f70027, 0x02f70026, 0x02f70025, 0x01f7002d, 0x01f7002b, 0x01f7002a, 0x01f70029, 0x01f70028, 0x01f70027, 0x01f70026, 0x01f70025, 0x00f7002d, 0x00f7002b, 0x00f7002a, 0x00f70029, 0x00f70028, 0x00f70027, 0x00f70026, 0x00f70025, }; /* Copied from brcmsmac (5.75.11): nphy_tpc_txgain_ipa_2g_2057rev5 */ static const uint32_t bwn_ntab_tx_gain_ipa_2057_rev5_2g[] = { 0x30ff0031, 0x30e70031, 0x30e7002e, 0x30cf002e, 0x30bf002e, 0x30af002e, 0x309f002f, 0x307f0033, 0x307f0031, 0x307f002e, 0x3077002e, 0x306f002e, 0x3067002e, 0x305f002f, 0x30570030, 0x3057002d, 0x304f002e, 0x30470031, 0x3047002e, 0x3047002c, 0x30470029, 0x303f002c, 0x303f0029, 0x3037002d, 0x3037002a, 0x30370028, 0x302f002c, 0x302f002a, 0x302f0028, 0x302f0026, 0x3027002c, 0x30270029, 0x30270027, 0x30270025, 0x30270023, 0x301f002c, 0x301f002a, 0x301f0028, 0x301f0025, 0x301f0024, 0x301f0022, 0x301f001f, 0x3017002d, 0x3017002b, 0x30170028, 0x30170026, 0x30170024, 0x30170022, 0x30170020, 0x3017001e, 0x3017001d, 0x3017001b, 0x3017001a, 0x30170018, 0x30170017, 0x30170015, 0x300f002c, 0x300f0029, 0x300f0027, 0x300f0024, 0x300f0022, 0x300f0021, 0x300f001f, 0x300f001d, 0x300f001b, 0x300f001a, 0x300f0018, 0x300f0017, 0x300f0016, 0x300f0015, 0x300f0115, 0x300f0215, 0x300f0315, 0x300f0415, 0x300f0515, 0x300f0615, 0x300f0715, 0x300f0715, 0x300f0715, 0x300f0715, 0x300f0715, 0x300f0715, 0x300f0715, 0x300f0715, 0x300f0715, 0x300f0715, 0x300f0715, 0x300f0715, 0x300f0715, 0x300f0715, 0x300f0715, 0x300f0715, 0x300f0715, 0x300f0715, 0x300f0715, 0x300f0715, 0x300f0715, 0x300f0715, 0x300f0715, 0x300f0715, 0x300f0715, 0x300f0715, 0x300f0715, 0x300f0715, 0x300f0715, 0x300f0715, 0x300f0715, 0x300f0715, 0x300f0715, 0x300f0715, 0x300f0715, 0x300f0715, 0x300f0715, 0x300f0715, 0x300f0715, 0x300f0715, 0x300f0715, 0x300f0715, 0x300f0715, 0x300f0715, 0x300f0715, 0x300f0715, 0x300f0715, 0x300f0715, 0x300f0715, 0x300f0715, 0x300f0715, 0x300f0715, }; /* Extracted from MMIO dump of 6.30.223.141 */ static const uint32_t bwn_ntab_tx_gain_ipa_2057_rev9_2g[] = { 0x60ff0031, 0x60e7002c, 0x60cf002a, 0x60c70029, 0x60b70029, 0x60a70029, 0x609f002a, 0x6097002b, 0x6087002e, 0x60770031, 0x606f0032, 0x60670034, 0x60670031, 0x605f0033, 0x605f0031, 0x60570033, 0x60570030, 0x6057002d, 0x6057002b, 0x604f002d, 0x604f002b, 0x604f0029, 0x604f0026, 0x60470029, 0x60470027, 0x603f0029, 0x603f0027, 0x603f0025, 0x60370029, 0x60370027, 0x60370024, 0x602f002a, 0x602f0028, 0x602f0026, 0x602f0024, 0x6027002a, 0x60270028, 0x60270026, 0x60270024, 0x60270022, 0x601f002b, 0x601f0029, 0x601f0027, 0x601f0024, 0x601f0022, 0x601f0020, 0x601f001f, 0x601f001d, 0x60170029, 0x60170027, 0x60170025, 0x60170023, 0x60170021, 0x6017001f, 0x6017001d, 0x6017001c, 0x6017001a, 0x60170018, 0x60170018, 0x60170016, 0x60170015, 0x600f0029, 0x600f0027, 0x600f0025, 0x600f0023, 0x600f0021, 0x600f001f, 0x600f001d, 0x600f001c, 0x600f001a, 0x600f0019, 0x600f0018, 0x600f0016, 0x600f0015, 0x600f0115, 0x600f0215, 0x600f0315, 0x600f0415, 0x600f0515, 0x600f0615, 0x600f0715, 0x600f0715, 0x600f0715, 0x600f0715, 0x600f0715, 0x600f0715, 0x600f0715, 0x600f0715, 0x600f0715, 0x600f0715, 0x600f0715, 0x600f0715, 0x600f0715, 0x600f0715, 0x600f0715, 0x600f0715, 0x600f0715, 0x600f0715, 0x600f0715, 0x600f0715, 0x600f0715, 0x600f0715, 0x600f0715, 0x600f0715, 0x600f0715, 0x600f0715, 0x600f0715, 0x600f0715, 0x600f0715, 0x600f0715, 0x600f0715, 0x600f0715, 0x600f0715, 0x600f0715, 0x600f0715, 0x600f0715, 0x600f0715, 0x600f0715, 0x600f0715, 0x600f0715, 0x600f0715, 0x600f0715, 0x600f0715, 0x600f0715, 0x600f0715, 0x600f0715, 0x600f0715, 0x600f0715, }; /* Extracted from MMIO dump of 6.30.223.248 */ static const uint32_t bwn_ntab_tx_gain_ipa_2057_rev14_2g[] = { 0x50df002e, 0x50cf002d, 0x50bf002c, 0x50b7002b, 0x50af002a, 0x50a70029, 0x509f0029, 0x50970028, 0x508f0027, 0x50870027, 0x507f0027, 0x50770027, 0x506f0027, 0x50670027, 0x505f0028, 0x50570029, 0x504f002b, 0x5047002e, 0x5047002b, 0x50470029, 0x503f002c, 0x503f0029, 0x5037002c, 0x5037002a, 0x50370028, 0x502f002d, 0x502f002b, 0x502f0028, 0x502f0026, 0x5027002d, 0x5027002a, 0x50270028, 0x50270026, 0x50270024, 0x501f002e, 0x501f002b, 0x501f0029, 0x501f0027, 0x501f0024, 0x501f0022, 0x501f0020, 0x501f001f, 0x5017002c, 0x50170029, 0x50170027, 0x50170024, 0x50170022, 0x50170021, 0x5017001f, 0x5017001d, 0x5017001b, 0x5017001a, 0x50170018, 0x50170017, 0x50170015, 0x500f002c, 0x500f002a, 0x500f0027, 0x500f0025, 0x500f0023, 0x500f0022, 0x500f001f, 0x500f001e, 0x500f001c, 0x500f001a, 0x500f0019, 0x500f0018, 0x500f0016, 0x500f0015, 0x500f0015, 0x500f0015, 0x500f0015, 0x500f0015, 0x500f0015, 0x500f0015, 0x500f0015, 0x500f0015, 0x500f0015, 0x500f0015, 0x500f0015, 0x500f0015, 0x500f0015, 0x500f0015, 0x500f0015, 0x500f0015, 0x500f0015, 0x500f0015, 0x500f0015, 0x500f0015, 0x500f0015, 0x500f0015, 0x500f0015, 0x500f0015, 0x500f0015, 0x500f0015, 0x500f0015, 0x500f0015, 0x500f0015, 0x500f0015, 0x500f0015, 0x500f0015, 0x500f0015, 0x500f0015, 0x500f0015, 0x500f0015, 0x500f0015, 0x500f0015, 0x500f0015, 0x500f0015, 0x500f0015, 0x500f0015, 0x500f0015, 0x500f0015, 0x500f0015, 0x500f0015, 0x500f0015, 0x500f0015, 0x500f0015, 0x500f0015, 0x500f0015, 0x500f0015, 0x500f0015, 0x500f0015, 0x500f0015, 0x500f0015, 0x500f0015, 0x500f0015, 0x500f0015, }; /* IPA 2 5Hz */ static const uint32_t bwn_ntab_tx_gain_ipa_rev3_5g[] = { 0x7ff70035, 0x7ff70033, 0x7ff70032, 0x7ff70031, 0x7ff7002f, 0x7ff7002e, 0x7ff7002d, 0x7ff7002b, 0x7ff7002a, 0x7ff70029, 0x7ff70028, 0x7ff70027, 0x7ff70026, 0x7ff70024, 0x7ff70023, 0x7ff70022, 0x7ef70028, 0x7ef70027, 0x7ef70026, 0x7ef70025, 0x7ef70024, 0x7ef70023, 0x7df70028, 0x7df70027, 0x7df70026, 0x7df70025, 0x7df70024, 0x7df70023, 0x7df70022, 0x7cf70029, 0x7cf70028, 0x7cf70027, 0x7cf70026, 0x7cf70025, 0x7cf70023, 0x7cf70022, 0x7bf70029, 0x7bf70028, 0x7bf70026, 0x7bf70025, 0x7bf70024, 0x7bf70023, 0x7bf70022, 0x7bf70021, 0x7af70029, 0x7af70028, 0x7af70027, 0x7af70026, 0x7af70025, 0x7af70024, 0x7af70023, 0x7af70022, 0x79f70029, 0x79f70028, 0x79f70027, 0x79f70026, 0x79f70025, 0x79f70024, 0x79f70023, 0x79f70022, 0x78f70029, 0x78f70028, 0x78f70027, 0x78f70026, 0x78f70025, 0x78f70024, 0x78f70023, 0x78f70022, 0x77f70029, 0x77f70028, 0x77f70027, 0x77f70026, 0x77f70025, 0x77f70024, 0x77f70023, 0x77f70022, 0x76f70029, 0x76f70028, 0x76f70027, 0x76f70026, 0x76f70024, 0x76f70023, 0x76f70022, 0x76f70021, 0x75f70029, 0x75f70028, 0x75f70027, 0x75f70026, 0x75f70025, 0x75f70024, 0x75f70023, 0x74f70029, 0x74f70028, 0x74f70026, 0x74f70025, 0x74f70024, 0x74f70023, 0x74f70022, 0x73f70029, 0x73f70027, 0x73f70026, 0x73f70025, 0x73f70024, 0x73f70023, 0x73f70022, 0x72f70028, 0x72f70027, 0x72f70026, 0x72f70025, 0x72f70024, 0x72f70023, 0x72f70022, 0x71f70028, 0x71f70027, 0x71f70026, 0x71f70025, 0x71f70024, 0x71f70023, 0x70f70028, 0x70f70027, 0x70f70026, 0x70f70024, 0x70f70023, 0x70f70022, 0x70f70021, 0x70f70020, 0x70f70020, 0x70f7001f, }; /* Extracted from MMIO dump of 6.30.223.141 */ static const uint32_t bwn_ntab_tx_gain_ipa_2057_rev9_5g[] = { 0x7f7f0053, 0x7f7f004b, 0x7f7f0044, 0x7f7f003f, 0x7f7f0039, 0x7f7f0035, 0x7f7f0032, 0x7f7f0030, 0x7f7f002d, 0x7e7f0030, 0x7e7f002d, 0x7d7f0032, 0x7d7f002f, 0x7d7f002c, 0x7c7f0032, 0x7c7f0030, 0x7c7f002d, 0x7b7f0030, 0x7b7f002e, 0x7b7f002b, 0x7a7f0032, 0x7a7f0030, 0x7a7f002d, 0x7a7f002b, 0x797f0030, 0x797f002e, 0x797f002b, 0x797f0029, 0x787f0030, 0x787f002d, 0x787f002b, 0x777f0032, 0x777f0030, 0x777f002d, 0x777f002b, 0x767f0031, 0x767f002f, 0x767f002c, 0x767f002a, 0x757f0031, 0x757f002f, 0x757f002c, 0x757f002a, 0x747f0030, 0x747f002d, 0x747f002b, 0x737f0032, 0x737f002f, 0x737f002c, 0x737f002a, 0x727f0030, 0x727f002d, 0x727f002b, 0x727f0029, 0x717f0030, 0x717f002d, 0x717f002b, 0x707f0031, 0x707f002f, 0x707f002c, 0x707f002a, 0x707f0027, 0x707f0025, 0x707f0023, 0x707f0021, 0x707f001f, 0x707f001d, 0x707f001c, 0x707f001a, 0x707f0019, 0x707f0017, 0x707f0016, 0x707f0015, 0x707f0014, 0x707f0012, 0x707f0012, 0x707f0011, 0x707f0010, 0x707f000f, 0x707f000e, 0x707f000d, 0x707f000d, 0x707f000c, 0x707f000b, 0x707f000a, 0x707f000a, 0x707f0009, 0x707f0008, 0x707f0008, 0x707f0008, 0x707f0008, 0x707f0007, 0x707f0007, 0x707f0006, 0x707f0006, 0x707f0006, 0x707f0005, 0x707f0005, 0x707f0005, 0x707f0004, 0x707f0004, 0x707f0004, 0x707f0003, 0x707f0003, 0x707f0003, 0x707f0003, 0x707f0003, 0x707f0003, 0x707f0003, 0x707f0003, 0x707f0003, 0x707f0003, 0x707f0002, 0x707f0002, 0x707f0002, 0x707f0002, 0x707f0002, 0x707f0002, 0x707f0002, 0x707f0002, 0x707f0002, 0x707f0001, 0x707f0001, 0x707f0001, 0x707f0001, 0x707f0001, 0x707f0001, 0x707f0001, }; const int8_t bwn_ntab_papd_pga_gain_delta_ipa_2g[] = { -114, -108, -98, -91, -84, -78, -70, -62, -54, -46, -39, -31, -23, -15, -8, 0 }; /* Extracted from MMIO dump of 6.30.223.248 * Entries: 0, 15, 17, 21, 24, 26, 27, 29, 30 were guessed */ static const int16_t bwn_ntab_rf_pwr_offset_2057_rev9_2g[] = { -133, -133, -107, -92, -81, -73, -66, -61, -56, -52, -48, -44, -41, -37, -34, -31, -28, -25, -22, -19, -17, -14, -12, -10, -9, -7, -5, -4, -3, -2, -1, 0, }; /* Extracted from MMIO dump of 6.30.223.248 */ static const int16_t bwn_ntab_rf_pwr_offset_2057_rev9_5g[] = { -101, -94, -86, -79, -72, -65, -57, -50, -42, -35, -28, -21, -16, -9, -4, 0, }; /* Extracted from MMIO dump of 6.30.223.248 * Entries: 0, 26, 28, 29, 30, 31 were guessed */ static const int16_t bwn_ntab_rf_pwr_offset_2057_rev14_2g[] = { -111, -111, -111, -84, -70, -59, -52, -45, -40, -36, -32, -29, -26, -23, -21, -18, -16, -15, -13, -11, -10, -8, -7, -6, -5, -4, -4, -3, -3, -2, -2, -1, }; const uint16_t tbl_iqcal_gainparams[2][9][8] = { { { 0x000, 0, 0, 2, 0x69, 0x69, 0x69, 0x69 }, { 0x700, 7, 0, 0, 0x69, 0x69, 0x69, 0x69 }, { 0x710, 7, 1, 0, 0x68, 0x68, 0x68, 0x68 }, { 0x720, 7, 2, 0, 0x67, 0x67, 0x67, 0x67 }, { 0x730, 7, 3, 0, 0x66, 0x66, 0x66, 0x66 }, { 0x740, 7, 4, 0, 0x65, 0x65, 0x65, 0x65 }, { 0x741, 7, 4, 1, 0x65, 0x65, 0x65, 0x65 }, { 0x742, 7, 4, 2, 0x65, 0x65, 0x65, 0x65 }, { 0x743, 7, 4, 3, 0x65, 0x65, 0x65, 0x65 } }, { { 0x000, 7, 0, 0, 0x79, 0x79, 0x79, 0x79 }, { 0x700, 7, 0, 0, 0x79, 0x79, 0x79, 0x79 }, { 0x710, 7, 1, 0, 0x79, 0x79, 0x79, 0x79 }, { 0x720, 7, 2, 0, 0x78, 0x78, 0x78, 0x78 }, { 0x730, 7, 3, 0, 0x78, 0x78, 0x78, 0x78 }, { 0x740, 7, 4, 0, 0x78, 0x78, 0x78, 0x78 }, { 0x741, 7, 4, 1, 0x78, 0x78, 0x78, 0x78 }, { 0x742, 7, 4, 2, 0x78, 0x78, 0x78, 0x78 }, { 0x743, 7, 4, 3, 0x78, 0x78, 0x78, 0x78 } } }; const struct bwn_nphy_txiqcal_ladder ladder_lo[] = { { 3, 0 }, { 4, 0 }, { 6, 0 }, { 9, 0 }, { 13, 0 }, { 18, 0 }, { 25, 0 }, { 25, 1 }, { 25, 2 }, { 25, 3 }, { 25, 4 }, { 25, 5 }, { 25, 6 }, { 25, 7 }, { 35, 7 }, { 50, 7 }, { 71, 7 }, { 100, 7 } }; const struct bwn_nphy_txiqcal_ladder ladder_iq[] = { { 3, 0 }, { 4, 0 }, { 6, 0 }, { 9, 0 }, { 13, 0 }, { 18, 0 }, { 25, 0 }, { 35, 0 }, { 50, 0 }, { 71, 0 }, { 100, 0 }, { 100, 1 }, { 100, 2 }, { 100, 3 }, { 100, 4 }, { 100, 5 }, { 100, 6 }, { 100, 7 } }; const uint16_t loscale[] = { 256, 256, 271, 271, 287, 256, 256, 271, 271, 287, 287, 304, 304, 256, 256, 271, 271, 287, 287, 304, 304, 322, 322, 341, 341, 362, 362, 383, 383, 256, 256, 271, 271, 287, 287, 304, 304, 322, 322, 256, 256, 271, 271, 287, 287, 304, 304, 322, 322, 341, 341, 362, 362, 256, 256, 271, 271, 287, 287, 304, 304, 322, 322, 256, 256, 271, 271, 287, 287, 304, 304, 322, 322, 341, 341, 362, 362, 256, 256, 271, 271, 287, 287, 304, 304, 322, 322, 341, 341, 362, 362, 383, 383, 406, 406, 430, 430, 455, 455, 482, 482, 511, 511, 541, 541, 573, 573, 607, 607, 643, 643, 681, 681, 722, 722, 764, 764, 810, 810, 858, 858, 908, 908, 962, 962, 1019, 1019, 256 }; const uint16_t tbl_tx_iqlo_cal_loft_ladder_40[] = { 0x0200, 0x0300, 0x0400, 0x0700, 0x0900, 0x0c00, 0x1200, 0x1201, 0x1202, 0x1203, 0x1204, 0x1205, 0x1206, 0x1207, 0x1907, 0x2307, 0x3207, 0x4707 }; const uint16_t tbl_tx_iqlo_cal_loft_ladder_20[] = { 0x0300, 0x0500, 0x0700, 0x0900, 0x0d00, 0x1100, 0x1900, 0x1901, 0x1902, 0x1903, 0x1904, 0x1905, 0x1906, 0x1907, 0x2407, 0x3207, 0x4607, 0x6407 }; const uint16_t tbl_tx_iqlo_cal_iqimb_ladder_40[] = { 0x0100, 0x0200, 0x0400, 0x0700, 0x0900, 0x0c00, 0x1200, 0x1900, 0x2300, 0x3200, 0x4700, 0x4701, 0x4702, 0x4703, 0x4704, 0x4705, 0x4706, 0x4707 }; const uint16_t tbl_tx_iqlo_cal_iqimb_ladder_20[] = { 0x0200, 0x0300, 0x0600, 0x0900, 0x0d00, 0x1100, 0x1900, 0x2400, 0x3200, 0x4600, 0x6400, 0x6401, 0x6402, 0x6403, 0x6404, 0x6405, 0x6406, 0x6407 }; const uint16_t tbl_tx_iqlo_cal_startcoefs_nphyrev3[BWN_NTAB_TX_IQLO_CAL_STARTCOEFS_REV3] = { }; const uint16_t tbl_tx_iqlo_cal_startcoefs[BWN_NTAB_TX_IQLO_CAL_STARTCOEFS] = { }; const uint16_t tbl_tx_iqlo_cal_cmds_recal_nphyrev3[] = { 0x8423, 0x8323, 0x8073, 0x8256, 0x8045, 0x8223, 0x9423, 0x9323, 0x9073, 0x9256, 0x9045, 0x9223 }; const uint16_t tbl_tx_iqlo_cal_cmds_recal[] = { 0x8101, 0x8253, 0x8053, 0x8234, 0x8034, 0x9101, 0x9253, 0x9053, 0x9234, 0x9034 }; const uint16_t tbl_tx_iqlo_cal_cmds_fullcal[] = { 0x8123, 0x8264, 0x8086, 0x8245, 0x8056, 0x9123, 0x9264, 0x9086, 0x9245, 0x9056 }; const uint16_t tbl_tx_iqlo_cal_cmds_fullcal_nphyrev3[] = { 0x8434, 0x8334, 0x8084, 0x8267, 0x8056, 0x8234, 0x9434, 0x9334, 0x9084, 0x9267, 0x9056, 0x9234 }; const int16_t tbl_tx_filter_coef_rev4[7][15] = { { -377, 137, -407, 208, -1527, 956, 93, 186, 93, 230, -44, 230, 201, -191, 201 }, { -77, 20, -98, 49, -93, 60, 56, 111, 56, 26, -5, 26, 34, -32, 34 }, { -360, 164, -376, 164, -1533, 576, 308, -314, 308, 121, -73, 121, 91, 124, 91 }, { -295, 200, -363, 142, -1391, 826, 151, 301, 151, 151, 301, 151, 602, -752, 602 }, { -92, 58, -96, 49, -104, 44, 17, 35, 17, 12, 25, 12, 13, 27, 13 }, { -375, 136, -399, 209, -1479, 949, 130, 260, 130, 230, -44, 230, 201, -191, 201 }, { 0xed9, 0xc8, 0xe95, 0x8e, 0xa91, 0x33a, 0x97, 0x12d, 0x97, 0x97, 0x12d, 0x97, 0x25a, 0xd10, 0x25a } }; /* addr0, addr1, bmask, shift */ const struct bwn_nphy_rf_control_override_rev2 tbl_rf_control_override_rev2[] = { { 0x78, 0x78, 0x0038, 3 }, /* for field == 0x0002 (fls == 2) */ { 0x7A, 0x7D, 0x0001, 0 }, /* for field == 0x0004 (fls == 3) */ { 0x7A, 0x7D, 0x0002, 1 }, /* for field == 0x0008 (fls == 4) */ { 0x7A, 0x7D, 0x0004, 2 }, /* for field == 0x0010 (fls == 5) */ { 0x7A, 0x7D, 0x0030, 4 }, /* for field == 0x0020 (fls == 6) */ { 0x7A, 0x7D, 0x00C0, 6 }, /* for field == 0x0040 (fls == 7) */ { 0x7A, 0x7D, 0x0100, 8 }, /* for field == 0x0080 (fls == 8) */ { 0x7A, 0x7D, 0x0200, 9 }, /* for field == 0x0100 (fls == 9) */ { 0x78, 0x78, 0x0004, 2 }, /* for field == 0x0200 (fls == 10) */ { 0x7B, 0x7E, 0x01FF, 0 }, /* for field == 0x0400 (fls == 11) */ { 0x7C, 0x7F, 0x01FF, 0 }, /* for field == 0x0800 (fls == 12) */ { 0x78, 0x78, 0x0100, 8 }, /* for field == 0x1000 (fls == 13) */ { 0x78, 0x78, 0x0200, 9 }, /* for field == 0x2000 (fls == 14) */ { 0x78, 0x78, 0xF000, 12 } /* for field == 0x4000 (fls == 15) */ }; /* val_mask, val_shift, en_addr0, val_addr0, en_addr1, val_addr1 */ const struct bwn_nphy_rf_control_override_rev3 tbl_rf_control_override_rev3[] = { { 0x8000, 15, 0xE5, 0xF9, 0xE6, 0xFB }, /* field == 0x0001 (fls 1) */ { 0x0001, 0, 0xE7, 0x7A, 0xEC, 0x7D }, /* field == 0x0002 (fls 2) */ { 0x0002, 1, 0xE7, 0x7A, 0xEC, 0x7D }, /* field == 0x0004 (fls 3) */ { 0x0004, 2, 0xE7, 0x7A, 0xEC, 0x7D }, /* field == 0x0008 (fls 4) */ { 0x0010, 4, 0xE7, 0x7A, 0xEC, 0x7D }, /* field == 0x0010 (fls 5) */ { 0x0020, 5, 0xE7, 0x7A, 0xEC, 0x7D }, /* field == 0x0020 (fls 6) */ { 0x0040, 6, 0xE7, 0x7A, 0xEC, 0x7D }, /* field == 0x0040 (fls 7) */ { 0x0080, 7, 0xE7, 0x7A, 0xEC, 0x7D }, /* field == 0x0080 (fls 8) */ { 0x0100, 8, 0xE7, 0x7A, 0xEC, 0x7D }, /* field == 0x0100 (fls 9) */ { 0x0007, 0, 0xE7, 0xF8, 0xEC, 0xFA }, /* field == 0x0200 (fls 10) */ { 0x0070, 4, 0xE7, 0xF8, 0xEC, 0xFA }, /* field == 0x0400 (fls 11) */ { 0xE000, 13, 0xE7, 0x7A, 0xEC, 0x7D }, /* field == 0x0800 (fls 12) */ { 0xFFFF, 0, 0xE7, 0x7B, 0xEC, 0x7E }, /* field == 0x1000 (fls 13) */ { 0xFFFF, 0, 0xE7, 0x7C, 0xEC, 0x7F }, /* field == 0x2000 (fls 14) */ { 0x00C0, 6, 0xE7, 0xF9, 0xEC, 0xFB } /* field == 0x4000 (fls 15) */ }; /* field, val_addr_core0, val_addr_core1, val_mask, val_shift */ static const struct bwn_nphy_rf_control_override_rev7 tbl_rf_control_override_rev7_over0[] = { { 0x0004, 0x07A, 0x07D, 0x0002, 1 }, { 0x0008, 0x07A, 0x07D, 0x0004, 2 }, { 0x0010, 0x07A, 0x07D, 0x0010, 4 }, { 0x0020, 0x07A, 0x07D, 0x0020, 5 }, { 0x0040, 0x07A, 0x07D, 0x0040, 6 }, { 0x0080, 0x07A, 0x07D, 0x0080, 7 }, { 0x0400, 0x0F8, 0x0FA, 0x0070, 4 }, { 0x0800, 0x07B, 0x07E, 0xFFFF, 0 }, { 0x1000, 0x07C, 0x07F, 0xFFFF, 0 }, { 0x6000, 0x348, 0x349, 0x00FF, 0 }, { 0x2000, 0x348, 0x349, 0x000F, 0 }, }; /* field, val_addr_core0, val_addr_core1, val_mask, val_shift */ static const struct bwn_nphy_rf_control_override_rev7 tbl_rf_control_override_rev7_over1[] = { { 0x0002, 0x340, 0x341, 0x0002, 1 }, { 0x0008, 0x340, 0x341, 0x0008, 3 }, { 0x0020, 0x340, 0x341, 0x0020, 5 }, { 0x0010, 0x340, 0x341, 0x0010, 4 }, { 0x0004, 0x340, 0x341, 0x0004, 2 }, { 0x0080, 0x340, 0x341, 0x0700, 8 }, { 0x0800, 0x340, 0x341, 0x4000, 14 }, { 0x0400, 0x340, 0x341, 0x2000, 13 }, { 0x0200, 0x340, 0x341, 0x0800, 12 }, { 0x0100, 0x340, 0x341, 0x0100, 11 }, { 0x0040, 0x340, 0x341, 0x0040, 6 }, { 0x0001, 0x340, 0x341, 0x0001, 0 }, }; /* field, val_addr_core0, val_addr_core1, val_mask, val_shift */ static const struct bwn_nphy_rf_control_override_rev7 tbl_rf_control_override_rev7_over2[] = { { 0x0008, 0x344, 0x345, 0x0008, 3 }, { 0x0002, 0x344, 0x345, 0x0002, 1 }, { 0x0001, 0x344, 0x345, 0x0001, 0 }, { 0x0004, 0x344, 0x345, 0x0004, 2 }, { 0x0010, 0x344, 0x345, 0x0010, 4 }, }; static struct bwn_nphy_gain_ctl_workaround_entry nphy_gain_ctl_wa_phy6_radio11_ghz2 = { { 10, 14, 19, 27 }, { -5, 6, 10, 15 }, { 0xA, 0xA, 0xA, 0xA, 0xA, 0xA, 0xA, 0xA, 0xA, 0xA }, { 3, 3, 3, 3, 3, 3, 3, 3, 3, 3 }, 0x427E, { 0x413F, 0x413F, 0x413F, 0x413F }, 0x007E, 0x0066, 0x1074, 0x18, 0x18, 0x18, 0x01D0, 0x5, }; static struct bwn_nphy_gain_ctl_workaround_entry nphy_gain_ctl_workaround[2][4] = { { /* 2GHz */ { /* PHY rev 3 */ { 7, 11, 16, 23 }, { -5, 6, 10, 14 }, { 0xA, 0xA, 0xA, 0xA, 0xA, 0xA, 0xA, 0xA, 0xA, 0xA }, { 3, 3, 3, 3, 3, 3, 3, 3, 3, 3 }, 0x627E, { 0x613F, 0x613F, 0x613F, 0x613F }, 0x107E, 0x0066, 0x0074, 0x18, 0x18, 0x18, 0x020D, 0x5, }, { /* PHY rev 4 */ { 8, 12, 17, 25 }, { -5, 6, 10, 14 }, { 0xA, 0xA, 0xA, 0xA, 0xA, 0xA, 0xA, 0xA, 0xA, 0xA }, { 3, 3, 3, 3, 3, 3, 3, 3, 3, 3 }, 0x527E, { 0x513F, 0x513F, 0x513F, 0x513F }, 0x007E, 0x0066, 0x0074, 0x18, 0x18, 0x18, 0x01A1, 0x5, }, { /* PHY rev 5 */ { 9, 13, 18, 26 }, { -3, 7, 11, 16 }, { 0xA, 0xA, 0xA, 0xA, 0xA, 0xA, 0xA, 0xA, 0xA, 0xA }, { 3, 3, 3, 3, 3, 3, 3, 3, 3, 3 }, 0x427E, /* invalid for external LNA! */ { 0x413F, 0x413F, 0x413F, 0x413F }, /* invalid for external LNA! */ 0x1076, 0x0066, 0x0000, /* low is invalid (the last one) */ 0x18, 0x18, 0x18, 0x01D0, 0x9, }, { /* PHY rev 6+ */ { 8, 13, 18, 25 }, { -5, 6, 10, 14 }, { 0xA, 0xA, 0xA, 0xA, 0xA, 0xA, 0xA, 0xA, 0xA, 0xA }, { 3, 3, 3, 3, 3, 3, 3, 3, 3, 3 }, 0x527E, /* invalid for external LNA! */ { 0x513F, 0x513F, 0x513F, 0x513F }, /* invalid for external LNA! */ 0x007E, 0x0066, 0x0000, /* low is invalid (the last one) */ 0x18, 0x18, 0x18, 0x01D0, 0x5, }, }, { /* 5GHz */ { /* PHY rev 3 */ { 7, 11, 17, 23 }, { -6, 2, 6, 10 }, { 0x13, 0x13, 0x13, 0x13, 0x13, 0x13, 0x13, 0x13, 0x13, 0x13 }, { 6, 6, 6, 6, 6, 6, 6, 6, 6, 6 }, 0x52DE, { 0x516F, 0x516F, 0x516F, 0x516F }, 0x00DE, 0x00CA, 0x00CC, 0x1E, 0x1E, 0x1E, 0x01A1, 25, }, { /* PHY rev 4 */ { 8, 12, 18, 23 }, { -5, 2, 6, 10 }, { 0xD, 0xD, 0xD, 0xD, 0xD, 0xD, 0xD, 0xD, 0xD, 0xD }, { 4, 4, 4, 4, 4, 4, 4, 4, 4, 4 }, 0x629E, { 0x614F, 0x614F, 0x614F, 0x614F }, 0x029E, 0x1084, 0x0086, 0x24, 0x24, 0x24, 0x0107, 25, }, { /* PHY rev 5 */ { 6, 10, 16, 21 }, { -7, 0, 4, 8 }, { 0xD, 0xD, 0xD, 0xD, 0xD, 0xD, 0xD, 0xD, 0xD, 0xD }, { 4, 4, 4, 4, 4, 4, 4, 4, 4, 4 }, 0x729E, { 0x714F, 0x714F, 0x714F, 0x714F }, 0x029E, 0x2084, 0x2086, 0x24, 0x24, 0x24, 0x00A9, 25, }, { /* PHY rev 6+ */ { 6, 10, 16, 21 }, { -7, 0, 4, 8 }, { 0xD, 0xD, 0xD, 0xD, 0xD, 0xD, 0xD, 0xD, 0xD, 0xD }, { 4, 4, 4, 4, 4, 4, 4, 4, 4, 4 }, 0x729E, { 0x714F, 0x714F, 0x714F, 0x714F }, 0x029E, 0x2084, 0x2086, 0x24, 0x24, 0x24, /* low is invalid for radio rev 11! */ 0x00F0, 25, }, }, }; static inline void assert_ntab_array_sizes(void) { #undef check #define check(table, size) \ CTASSERT(nitems(bwn_ntab_##table) == BWN_NTAB_##size##_SIZE) check(adjustpower0, C0_ADJPLT); check(adjustpower1, C1_ADJPLT); check(bdi, BDI); check(channelest, CHANEST); check(estimatepowerlt0, C0_ESTPLT); check(estimatepowerlt1, C1_ESTPLT); check(framelookup, FRAMELT); check(framestruct, FRAMESTRUCT); check(gainctl0, C0_GAINCTL); check(gainctl1, C1_GAINCTL); check(intlevel, INTLEVEL); check(iqlt0, C0_IQLT); check(iqlt1, C1_IQLT); check(loftlt0, C0_LOFEEDTH); check(loftlt1, C1_LOFEEDTH); check(mcs, MCS); check(noisevar10, NOISEVAR10); check(noisevar11, NOISEVAR11); check(pilot, PILOT); check(pilotlt, PILOTLT); check(tdi20a0, TDI20A0); check(tdi20a1, TDI20A1); check(tdi40a0, TDI40A0); check(tdi40a1, TDI40A1); check(tdtrn, TDTRN); check(tmap, TMAP); #undef check } uint32_t bwn_ntab_read(struct bwn_mac *mac, uint32_t offset) { uint32_t type, value; type = offset & BWN_NTAB_TYPEMASK; offset &= ~BWN_NTAB_TYPEMASK; KASSERT(offset <= 0xFFFF, ("%s: invalid offset (%d)\n", __func__, offset)); switch (type) { case BWN_NTAB_8BIT: BWN_PHY_WRITE(mac, BWN_NPHY_TABLE_ADDR, offset); value = BWN_PHY_READ(mac, BWN_NPHY_TABLE_DATALO) & 0xFF; break; case BWN_NTAB_16BIT: BWN_PHY_WRITE(mac, BWN_NPHY_TABLE_ADDR, offset); value = BWN_PHY_READ(mac, BWN_NPHY_TABLE_DATALO); break; case BWN_NTAB_32BIT: BWN_PHY_WRITE(mac, BWN_NPHY_TABLE_ADDR, offset); value = BWN_PHY_READ(mac, BWN_NPHY_TABLE_DATALO); value |= BWN_PHY_READ(mac, BWN_NPHY_TABLE_DATAHI) << 16; break; default: KASSERT(0, ("%s: invalid type", __func__)); value = 0; } return value; } void bwn_ntab_read_bulk(struct bwn_mac *mac, uint32_t offset, unsigned int nr_elements, void *_data) { struct bwn_softc *sc = mac->mac_sc; uint32_t type; uint8_t *data = _data; unsigned int i; type = offset & BWN_NTAB_TYPEMASK; offset &= ~BWN_NTAB_TYPEMASK; KASSERT(offset <= 0xFFFF, ("%s: invalid offset (%d)\n", __func__, offset)); BWN_PHY_WRITE(mac, BWN_NPHY_TABLE_ADDR, offset); for (i = 0; i < nr_elements; i++) { /* Auto increment broken + caching issue on BCM43224? */ - if (siba_get_chipid(sc->sc_dev) == 43224 && - siba_get_revid(sc->sc_dev) == 1) { + if (sc->sc_cid.chip_id == BHND_CHIPID_BCM43224 && + bhnd_get_hwrev(sc->sc_dev) == 1) { BWN_PHY_READ(mac, BWN_NPHY_TABLE_DATALO); BWN_PHY_WRITE(mac, BWN_NPHY_TABLE_ADDR, offset + i); } switch (type) { case BWN_NTAB_8BIT: *data = BWN_PHY_READ(mac, BWN_NPHY_TABLE_DATALO) & 0xFF; data++; break; case BWN_NTAB_16BIT: *((uint16_t *)data) = BWN_PHY_READ(mac, BWN_NPHY_TABLE_DATALO); data += 2; break; case BWN_NTAB_32BIT: *((uint32_t *)data) = BWN_PHY_READ(mac, BWN_NPHY_TABLE_DATALO); *((uint32_t *)data) |= BWN_PHY_READ(mac, BWN_NPHY_TABLE_DATAHI) << 16; data += 4; break; default: KASSERT(0, ("%s: called; invalid type (%d)\n", __func__, type)); } } } void bwn_ntab_write(struct bwn_mac *mac, uint32_t offset, uint32_t value) { uint32_t type, orig; type = offset & BWN_NTAB_TYPEMASK; orig = offset; offset &= 0xFFFF; switch (type) { case BWN_NTAB_8BIT: KASSERT(value <= 0xFF, ("%s: 8bit: invalid value (%d) (0x%08x)\n", __func__, value, orig)); BWN_PHY_WRITE(mac, BWN_NPHY_TABLE_ADDR, offset); BWN_PHY_WRITE(mac, BWN_NPHY_TABLE_DATALO, value); break; case BWN_NTAB_16BIT: KASSERT(value <= 0xFFFF, ("%s: 8bit: invalid value (%d) (0x%08x)\n", __func__, value, orig)); BWN_PHY_WRITE(mac, BWN_NPHY_TABLE_ADDR, offset); BWN_PHY_WRITE(mac, BWN_NPHY_TABLE_DATALO, value); break; case BWN_NTAB_32BIT: BWN_PHY_WRITE(mac, BWN_NPHY_TABLE_ADDR, offset); BWN_PHY_WRITE(mac, BWN_NPHY_TABLE_DATAHI, value >> 16); BWN_PHY_WRITE(mac, BWN_NPHY_TABLE_DATALO, value & 0xFFFF); break; default: KASSERT(0, ("%s: called; invalid type (%d)\n", __func__, type)); } return; /* Some compiletime assertions... */ assert_ntab_array_sizes(); } void bwn_ntab_write_bulk(struct bwn_mac *mac, uint32_t offset, unsigned int nr_elements, const void *_data) { struct bwn_softc *sc = mac->mac_sc; uint32_t type, value; uint32_t orig; const uint8_t *data = _data; unsigned int i; type = offset & BWN_NTAB_TYPEMASK; orig = offset; offset &= ~BWN_NTAB_TYPEMASK; KASSERT(offset <= 0xFFFF, ("%s: invalid offset (%d)\n", __func__, offset)); BWN_PHY_WRITE(mac, BWN_NPHY_TABLE_ADDR, offset); for (i = 0; i < nr_elements; i++) { /* Auto increment broken + caching issue on BCM43224? */ if ((offset >> 10) == 9 && - siba_get_chipid(sc->sc_dev) == 43224 && - siba_get_revid(sc->sc_dev) == 1) { + sc->sc_cid.chip_id == BHND_CHIPID_BCM43224 && + bhnd_get_hwrev(sc->sc_dev) == 1) { BWN_PHY_READ(mac, BWN_NPHY_TABLE_DATALO); BWN_PHY_WRITE(mac, BWN_NPHY_TABLE_ADDR, offset + i); } switch (type) { case BWN_NTAB_8BIT: value = *data; data++; KASSERT(value <= 0xFF, ("%s: 8bit: invalid value (%d) (0x%08x)\n", __func__, value, orig)); BWN_PHY_WRITE(mac, BWN_NPHY_TABLE_DATALO, value); break; case BWN_NTAB_16BIT: value = *((const uint16_t *)data); data += 2; KASSERT(value <= 0xFFFF, ("%s: 16bit: invalid value (%d) (0x%08x)\n", __func__, value, orig)); BWN_PHY_WRITE(mac, BWN_NPHY_TABLE_DATALO, value); break; case BWN_NTAB_32BIT: value = *((const uint32_t *)data); data += 4; BWN_PHY_WRITE(mac, BWN_NPHY_TABLE_DATAHI, value >> 16); BWN_PHY_WRITE(mac, BWN_NPHY_TABLE_DATALO, value & 0xFFFF); break; default: KASSERT(0, ("%s: invalid type (%d)\n", __func__, type)); } } } #define ntab_upload(mac, offset, data) do { \ bwn_ntab_write_bulk(mac, offset, nitems(data), data); \ } while (0) static void bwn_nphy_tables_init_shared_lut(struct bwn_mac *mac) { ntab_upload(mac, BWN_NTAB_C0_ESTPLT_R3, bwn_ntab_estimatepowerlt0_r3); ntab_upload(mac, BWN_NTAB_C1_ESTPLT_R3, bwn_ntab_estimatepowerlt1_r3); ntab_upload(mac, BWN_NTAB_C0_ADJPLT_R3, bwn_ntab_adjustpower0_r3); ntab_upload(mac, BWN_NTAB_C1_ADJPLT_R3, bwn_ntab_adjustpower1_r3); ntab_upload(mac, BWN_NTAB_C0_GAINCTL_R3, bwn_ntab_gainctl0_r3); ntab_upload(mac, BWN_NTAB_C1_GAINCTL_R3, bwn_ntab_gainctl1_r3); ntab_upload(mac, BWN_NTAB_C0_IQLT_R3, bwn_ntab_iqlt0_r3); ntab_upload(mac, BWN_NTAB_C1_IQLT_R3, bwn_ntab_iqlt1_r3); ntab_upload(mac, BWN_NTAB_C0_LOFEEDTH_R3, bwn_ntab_loftlt0_r3); ntab_upload(mac, BWN_NTAB_C1_LOFEEDTH_R3, bwn_ntab_loftlt1_r3); } +static int bwn_nphy_tables_get_antswlut(struct bwn_mac *mac, uint8_t *antswlut) +{ + struct ieee80211com *ic = &mac->mac_sc->sc_ic; + struct bwn_softc *sc = mac->mac_sc; + const char *antswlut_var; + int error; + + if (IEEE80211_IS_CHAN_5GHZ(ic->ic_curchan)) + antswlut_var = BHND_NVAR_ANTSWCTL5G; + else + antswlut_var = BHND_NVAR_ANTSWCTL2G; + + error = bhnd_nvram_getvar_uint8(sc->sc_dev, antswlut_var, antswlut); + if (error) + BWN_ERRPRINTF(mac->mac_sc, "NVRAM variable %s unreadable: %d", + antswlut_var, error); + + return (error); +} + static void bwn_nphy_tables_init_rev7_volatile(struct bwn_mac *mac) { - struct ieee80211com *ic = &mac->mac_sc->sc_ic; - struct bwn_softc *sc = mac->mac_sc; - uint8_t antswlut; - int core, offset, i; + int core, error, offset, i; + uint8_t antswlut; const int antswlut0_offsets[] = { 0, 4, 8, }; /* Offsets for values */ const uint8_t antswlut0_values[][3] = { { 0x2, 0x12, 0x8 }, /* Core 0 */ { 0x2, 0x18, 0x2 }, /* Core 1 */ }; - if (IEEE80211_IS_CHAN_5GHZ(ic->ic_curchan)) - antswlut = siba_sprom_get_fem_5ghz_antswlut(sc->sc_dev); - else - antswlut = siba_sprom_get_fem_2ghz_antswlut(sc->sc_dev); + if ((error = bwn_nphy_tables_get_antswlut(mac, &antswlut))) + return; switch (antswlut) { case 0: for (core = 0; core < 2; core++) { for (i = 0; i < nitems(antswlut0_values[0]); i++) { offset = core ? 0x20 : 0x00; offset += antswlut0_offsets[i]; bwn_ntab_write(mac, BWN_NTAB8(9, offset), antswlut0_values[core][i]); } } break; default: BWN_ERRPRINTF(mac->mac_sc, "Unsupported antswlut: %d\n", antswlut); break; } } static void bwn_nphy_tables_init_rev16(struct bwn_mac *mac) { /* Static tables */ if (mac->mac_phy.phy_do_full_init) { ntab_upload(mac, BWN_NTAB_NOISEVAR_R7, bwn_ntab_noisevar_r7); bwn_nphy_tables_init_shared_lut(mac); } /* Volatile tables */ bwn_nphy_tables_init_rev7_volatile(mac); } static void bwn_nphy_tables_init_rev7(struct bwn_mac *mac) { /* Static tables */ if (mac->mac_phy.phy_do_full_init) { ntab_upload(mac, BWN_NTAB_FRAMESTRUCT_R3, bwn_ntab_framestruct_r3); ntab_upload(mac, BWN_NTAB_PILOT_R3, bwn_ntab_pilot_r3); ntab_upload(mac, BWN_NTAB_TMAP_R7, bwn_ntab_tmap_r7); ntab_upload(mac, BWN_NTAB_INTLEVEL_R3, bwn_ntab_intlevel_r3); ntab_upload(mac, BWN_NTAB_TDTRN_R3, bwn_ntab_tdtrn_r3); ntab_upload(mac, BWN_NTAB_NOISEVAR_R7, bwn_ntab_noisevar_r7); ntab_upload(mac, BWN_NTAB_MCS_R3, bwn_ntab_mcs_r3); ntab_upload(mac, BWN_NTAB_TDI20A0_R3, bwn_ntab_tdi20a0_r3); ntab_upload(mac, BWN_NTAB_TDI20A1_R3, bwn_ntab_tdi20a1_r3); ntab_upload(mac, BWN_NTAB_TDI40A0_R3, bwn_ntab_tdi40a0_r3); ntab_upload(mac, BWN_NTAB_TDI40A1_R3, bwn_ntab_tdi40a1_r3); ntab_upload(mac, BWN_NTAB_PILOTLT_R3, bwn_ntab_pilotlt_r3); ntab_upload(mac, BWN_NTAB_CHANEST_R3, bwn_ntab_channelest_r3); ntab_upload(mac, BWN_NTAB_FRAMELT_R3, bwn_ntab_framelookup_r3); bwn_nphy_tables_init_shared_lut(mac); } /* Volatile tables */ bwn_nphy_tables_init_rev7_volatile(mac); } static void bwn_nphy_tables_init_rev3(struct bwn_mac *mac) { - struct ieee80211com *ic = &mac->mac_sc->sc_ic; - struct bwn_softc *sc = mac->mac_sc; - uint8_t antswlut; + int error; + uint8_t antswlut; - if (IEEE80211_IS_CHAN_5GHZ(ic->ic_curchan)) - antswlut = siba_sprom_get_fem_5ghz_antswlut(sc->sc_dev); - else - antswlut = siba_sprom_get_fem_2ghz_antswlut(sc->sc_dev); + if ((error = bwn_nphy_tables_get_antswlut(mac, &antswlut))) + return; /* Static tables */ if (mac->mac_phy.phy_do_full_init) { ntab_upload(mac, BWN_NTAB_FRAMESTRUCT_R3, bwn_ntab_framestruct_r3); ntab_upload(mac, BWN_NTAB_PILOT_R3, bwn_ntab_pilot_r3); ntab_upload(mac, BWN_NTAB_TMAP_R3, bwn_ntab_tmap_r3); ntab_upload(mac, BWN_NTAB_INTLEVEL_R3, bwn_ntab_intlevel_r3); ntab_upload(mac, BWN_NTAB_TDTRN_R3, bwn_ntab_tdtrn_r3); ntab_upload(mac, BWN_NTAB_NOISEVAR_R3, bwn_ntab_noisevar_r3); ntab_upload(mac, BWN_NTAB_MCS_R3, bwn_ntab_mcs_r3); ntab_upload(mac, BWN_NTAB_TDI20A0_R3, bwn_ntab_tdi20a0_r3); ntab_upload(mac, BWN_NTAB_TDI20A1_R3, bwn_ntab_tdi20a1_r3); ntab_upload(mac, BWN_NTAB_TDI40A0_R3, bwn_ntab_tdi40a0_r3); ntab_upload(mac, BWN_NTAB_TDI40A1_R3, bwn_ntab_tdi40a1_r3); ntab_upload(mac, BWN_NTAB_PILOTLT_R3, bwn_ntab_pilotlt_r3); ntab_upload(mac, BWN_NTAB_CHANEST_R3, bwn_ntab_channelest_r3); ntab_upload(mac, BWN_NTAB_FRAMELT_R3, bwn_ntab_framelookup_r3); bwn_nphy_tables_init_shared_lut(mac); } /* Volatile tables */ if (antswlut < nitems(bwn_ntab_antswctl_r3)) ntab_upload(mac, BWN_NTAB_ANT_SW_CTL_R3, bwn_ntab_antswctl_r3[antswlut]); else KASSERT(0, ("%s: antswlut out of bounds (%d)\n", __func__, antswlut)); } static void bwn_nphy_tables_init_rev0(struct bwn_mac *mac) { /* Static tables */ if (mac->mac_phy.phy_do_full_init) { ntab_upload(mac, BWN_NTAB_FRAMESTRUCT, bwn_ntab_framestruct); ntab_upload(mac, BWN_NTAB_FRAMELT, bwn_ntab_framelookup); ntab_upload(mac, BWN_NTAB_TMAP, bwn_ntab_tmap); ntab_upload(mac, BWN_NTAB_TDTRN, bwn_ntab_tdtrn); ntab_upload(mac, BWN_NTAB_INTLEVEL, bwn_ntab_intlevel); ntab_upload(mac, BWN_NTAB_PILOT, bwn_ntab_pilot); ntab_upload(mac, BWN_NTAB_TDI20A0, bwn_ntab_tdi20a0); ntab_upload(mac, BWN_NTAB_TDI20A1, bwn_ntab_tdi20a1); ntab_upload(mac, BWN_NTAB_TDI40A0, bwn_ntab_tdi40a0); ntab_upload(mac, BWN_NTAB_TDI40A1, bwn_ntab_tdi40a1); ntab_upload(mac, BWN_NTAB_CHANEST, bwn_ntab_channelest); ntab_upload(mac, BWN_NTAB_MCS, bwn_ntab_mcs); ntab_upload(mac, BWN_NTAB_NOISEVAR10, bwn_ntab_noisevar10); ntab_upload(mac, BWN_NTAB_NOISEVAR11, bwn_ntab_noisevar11); } /* Volatile tables */ ntab_upload(mac, BWN_NTAB_BDI, bwn_ntab_bdi); ntab_upload(mac, BWN_NTAB_PILOTLT, bwn_ntab_pilotlt); ntab_upload(mac, BWN_NTAB_C0_GAINCTL, bwn_ntab_gainctl0); ntab_upload(mac, BWN_NTAB_C1_GAINCTL, bwn_ntab_gainctl1); ntab_upload(mac, BWN_NTAB_C0_ESTPLT, bwn_ntab_estimatepowerlt0); ntab_upload(mac, BWN_NTAB_C1_ESTPLT, bwn_ntab_estimatepowerlt1); ntab_upload(mac, BWN_NTAB_C0_ADJPLT, bwn_ntab_adjustpower0); ntab_upload(mac, BWN_NTAB_C1_ADJPLT, bwn_ntab_adjustpower1); ntab_upload(mac, BWN_NTAB_C0_IQLT, bwn_ntab_iqlt0); ntab_upload(mac, BWN_NTAB_C1_IQLT, bwn_ntab_iqlt1); ntab_upload(mac, BWN_NTAB_C0_LOFEEDTH, bwn_ntab_loftlt0); ntab_upload(mac, BWN_NTAB_C1_LOFEEDTH, bwn_ntab_loftlt1); } /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/InitTables */ void bwn_nphy_tables_init(struct bwn_mac *mac) { if (mac->mac_phy.rev >= 16) bwn_nphy_tables_init_rev16(mac); else if (mac->mac_phy.rev >= 7) bwn_nphy_tables_init_rev7(mac); else if (mac->mac_phy.rev >= 3) bwn_nphy_tables_init_rev3(mac); else bwn_nphy_tables_init_rev0(mac); } /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/GetIpaGainTbl */ static const uint32_t *bwn_nphy_get_ipa_gain_table(struct bwn_mac *mac) { struct bwn_softc *sc = mac->mac_sc; struct ieee80211com *ic = &mac->mac_sc->sc_ic; struct bwn_phy *phy = &mac->mac_phy; if (IEEE80211_IS_CHAN_2GHZ(ic->ic_curchan)) { switch (phy->rev) { case 17: if (phy->rf_rev == 14) return bwn_ntab_tx_gain_ipa_2057_rev14_2g; break; case 16: if (phy->rf_rev == 9) return bwn_ntab_tx_gain_ipa_2057_rev9_2g; break; case 8: if (phy->rf_rev == 5) return bwn_ntab_tx_gain_ipa_2057_rev5_2g; break; case 6: - if (siba_get_chipid(sc->sc_dev) == 47162) /* BCM47612 */ + if (sc->sc_cid.chip_id == BHND_CHIPID_BCM47162) return bwn_ntab_tx_gain_ipa_rev5_2g; return bwn_ntab_tx_gain_ipa_rev6_2g; case 5: return bwn_ntab_tx_gain_ipa_rev5_2g; case 4: case 3: return bwn_ntab_tx_gain_ipa_rev3_2g; } BWN_ERRPRINTF(mac->mac_sc, "No 2GHz IPA gain table available for this device\n"); return NULL; } else { switch (phy->rev) { case 16: if (phy->rf_rev == 9) return bwn_ntab_tx_gain_ipa_2057_rev9_5g; break; case 3 ... 6: return bwn_ntab_tx_gain_ipa_rev3_5g; } BWN_ERRPRINTF(mac->mac_sc, "No 5GHz IPA gain table available for this device\n"); return NULL; } } const uint32_t *bwn_nphy_get_tx_gain_table(struct bwn_mac *mac) { struct ieee80211com *ic = &mac->mac_sc->sc_ic; struct bwn_softc *sc = mac->mac_sc; struct bwn_phy *phy = &mac->mac_phy; - int is_5ghz; + int error, is_5ghz; + uint8_t extpa_gain; /* XXX ideally we'd have is2, is5, etc */ is_5ghz = !! IEEE80211_IS_CHAN_5GHZ(ic->ic_curchan); if (mac->mac_phy.rev < 3) return bwn_ntab_tx_gain_rev0_1_2; /* rev 3+ */ if ((mac->mac_phy.phy_n->ipa2g_on && is_5ghz == 0) || (mac->mac_phy.phy_n->ipa5g_on && is_5ghz == 1)) { return bwn_nphy_get_ipa_gain_table(mac); } else if (is_5ghz == 1) { switch (phy->rev) { case 6: case 5: return bwn_ntab_tx_gain_epa_rev5_5g; case 4: - return siba_sprom_get_fem_5ghz_extpa_gain(sc->sc_dev) == 3 ? + error = bhnd_nvram_getvar_uint8(sc->sc_dev, + BHND_NVAR_EXTPAGAIN5G, &extpa_gain); + if (error) { + BWN_ERRPRINTF(mac->mac_sc, "Error reading EPA " + "gain configuration (%s) from NVRAM: %d\n", + BHND_NVAR_EXTPAGAIN5G, error); + return (NULL); + } + + return (extpa_gain == 3) ? bwn_ntab_tx_gain_epa_rev4_5g : bwn_ntab_tx_gain_epa_rev4_hi_pwr_5g; case 3: return bwn_ntab_tx_gain_epa_rev3_5g; default: BWN_ERRPRINTF(mac->mac_sc, "No 5GHz EPA gain table available for this device\n"); return NULL; } } else { switch (phy->rev) { case 6: case 5: - if (siba_sprom_get_fem_5ghz_extpa_gain(sc->sc_dev) == 3) + error = bhnd_nvram_getvar_uint8(sc->sc_dev, + BHND_NVAR_EXTPAGAIN2G, &extpa_gain); + if (error) { + BWN_ERRPRINTF(mac->mac_sc, "Error reading EPA " + "gain configuration (%s) from NVRAM: %d\n", + BHND_NVAR_EXTPAGAIN2G, error); + return (NULL); + } + + if (extpa_gain == 3) return bwn_ntab_tx_gain_epa_rev3_hi_pwr_2g; /* fall through */ case 4: case 3: return bwn_ntab_tx_gain_epa_rev3_2g; default: BWN_ERRPRINTF(mac->mac_sc, "No 2GHz EPA gain table available for this device\n"); return NULL; } } } const int16_t *bwn_ntab_get_rf_pwr_offset_table(struct bwn_mac *mac) { struct ieee80211com *ic = &mac->mac_sc->sc_ic; struct bwn_phy *phy = &mac->mac_phy; if (IEEE80211_IS_CHAN_2GHZ(ic->ic_curchan)) { switch (phy->rev) { case 17: if (phy->rf_rev == 14) return bwn_ntab_rf_pwr_offset_2057_rev14_2g; break; case 16: if (phy->rf_rev == 9) return bwn_ntab_rf_pwr_offset_2057_rev9_2g; break; } BWN_ERRPRINTF(mac->mac_sc, "No 2GHz RF power table available for this device\n"); return NULL; } else { switch (phy->rev) { case 16: if (phy->rf_rev == 9) return bwn_ntab_rf_pwr_offset_2057_rev9_5g; break; } BWN_ERRPRINTF(mac->mac_sc, "No 5GHz RF power table available for this device\n"); return NULL; } } struct bwn_nphy_gain_ctl_workaround_entry *bwn_nphy_get_gain_ctl_workaround_ent( struct bwn_mac *mac, bool ghz5, bool ext_lna) { struct ieee80211com *ic = &mac->mac_sc->sc_ic; struct bwn_softc *sc = mac->mac_sc; struct bwn_phy *phy = &mac->mac_phy; struct bwn_nphy_gain_ctl_workaround_entry *e; uint8_t phy_idx; if (!ghz5 && mac->mac_phy.rev >= 6 && mac->mac_phy.rf_rev == 11) return &nphy_gain_ctl_wa_phy6_radio11_ghz2; KASSERT(mac->mac_phy.rev >= 3, ("%s: called; too early phy rev (%d)\n", __func__, mac->mac_phy.rev)); if (mac->mac_phy.rev >= 6) phy_idx = 3; else if (mac->mac_phy.rev == 5) phy_idx = 2; else if (mac->mac_phy.rev == 4) phy_idx = 1; else phy_idx = 0; e = &nphy_gain_ctl_workaround[ghz5][phy_idx]; /* Some workarounds to the workarounds... */ if (!ghz5) { - uint8_t tr_iso = siba_sprom_get_fem_2ghz_tr_iso(sc->sc_dev); + uint8_t tr_iso; + int error; + + error = bhnd_nvram_getvar_uint8(sc->sc_dev, BHND_NVAR_TRISO2G, + &tr_iso); + BWN_ERRPRINTF(mac->mac_sc, "Error reading %s from NVRAM: %d\n", + BHND_NVAR_TRISO2G, error); if (tr_iso > 7) tr_iso = 3; if (phy->rev >= 6) { static const int gain_data[] = { 0x106a, 0x106c, 0x1074, 0x107c, 0x007e, 0x107e, 0x207e, 0x307e, }; e->cliplo_gain = gain_data[tr_iso]; } else if (phy->rev == 5) { static const int gain_data[] = { 0x0062, 0x0064, 0x006a, 0x106a, 0x106c, 0x1074, 0x107c, 0x207c, }; e->cliplo_gain = gain_data[tr_iso]; } if (phy->rev >= 5 && ext_lna) { e->rfseq_init[0] &= ~0x4000; e->rfseq_init[1] &= ~0x4000; e->rfseq_init[2] &= ~0x4000; e->rfseq_init[3] &= ~0x4000; e->init_gain &= ~0x4000; } } else { if (phy->rev >= 6) { /* XXX 40MHz HT only? No static-40MHz? */ if (phy->rf_rev == 11 && IEEE80211_IS_CHAN_HT40(ic->ic_curchan)) e->crsminu = 0x2d; } else if (phy->rev == 4 && ext_lna) { e->rfseq_init[0] &= ~0x4000; e->rfseq_init[1] &= ~0x4000; e->rfseq_init[2] &= ~0x4000; e->rfseq_init[3] &= ~0x4000; e->init_gain &= ~0x4000; e->rfseq_init[0] |= 0x1000; e->rfseq_init[1] |= 0x1000; e->rfseq_init[2] |= 0x1000; e->rfseq_init[3] |= 0x1000; e->init_gain |= 0x1000; } } return e; } const struct bwn_nphy_rf_control_override_rev7 * bwn_nphy_get_rf_ctl_over_rev7(struct bwn_mac *mac, uint16_t field, uint8_t override) { const struct bwn_nphy_rf_control_override_rev7 *e; uint8_t size, i; switch (override) { case 0: e = tbl_rf_control_override_rev7_over0; size = nitems(tbl_rf_control_override_rev7_over0); break; case 1: e = tbl_rf_control_override_rev7_over1; size = nitems(tbl_rf_control_override_rev7_over1); break; case 2: e = tbl_rf_control_override_rev7_over2; size = nitems(tbl_rf_control_override_rev7_over2); break; default: BWN_ERRPRINTF(mac->mac_sc, "Invalid override value %d\n", override); return NULL; } for (i = 0; i < size; i++) { if (e[i].field == field) return &e[i]; } return NULL; } Index: head/sys/modules/bwn_pci/Makefile =================================================================== --- head/sys/modules/bwn_pci/Makefile (revision 328911) +++ head/sys/modules/bwn_pci/Makefile (nonexistent) @@ -1,13 +0,0 @@ -# $FreeBSD$ - -.PATH: ${SRCTOP}/sys/dev/bwn - -KMOD= if_bwn_pci -SRCS= if_bwn_pci.c - -SRCS+= bhnd_bus_if.h bhndb_bus_if.h \ - bhndb_if.h -SRCS+= device_if.h bus_if.h pci_if.h \ - opt_bwn.h opt_wlan.h opt_global.h - -.include Property changes on: head/sys/modules/bwn_pci/Makefile ___________________________________________________________________ Deleted: svn:eol-style ## -1 +0,0 ## -native \ No newline at end of property Deleted: svn:keywords ## -1 +0,0 ## -FreeBSD=%H \ No newline at end of property Deleted: svn:mime-type ## -1 +0,0 ## -text/plain \ No newline at end of property Index: head/sys/modules/siba_bwn/Makefile =================================================================== --- head/sys/modules/siba_bwn/Makefile (revision 328911) +++ head/sys/modules/siba_bwn/Makefile (nonexistent) @@ -1,9 +0,0 @@ -# $FreeBSD$ - -.PATH: ${SRCTOP}/sys/dev/siba - -KMOD= siba_bwn -SRCS= siba_core.c siba_bwn.c sibareg.h sibavar.h -SRCS+= device_if.h bus_if.h pci_if.h opt_siba.h - -.include Property changes on: head/sys/modules/siba_bwn/Makefile ___________________________________________________________________ Deleted: svn:keywords ## -1 +0,0 ## -FreeBSD=%H \ No newline at end of property Index: head/sys/modules/Makefile =================================================================== --- head/sys/modules/Makefile (revision 328911) +++ head/sys/modules/Makefile (revision 328912) @@ -1,840 +1,838 @@ # $FreeBSD$ SYSDIR?=${SRCTOP}/sys .include "${SYSDIR}/conf/kern.opts.mk" SUBDIR_PARALLEL= # Modules that include binary-only blobs of microcode should be selectable by # MK_SOURCELESS_UCODE option (see below). .if defined(MODULES_OVERRIDE) && !defined(ALL_MODULES) SUBDIR=${MODULES_OVERRIDE} .else SUBDIR= \ ${_3dfx} \ ${_3dfx_linux} \ ${_aac} \ ${_aacraid} \ accf_data \ accf_dns \ accf_http \ acl_nfs4 \ acl_posix1e \ ${_acpi} \ ae \ ${_aesni} \ age \ ${_agp} \ aha \ ahci \ ${_aic} \ aic7xxx \ alc \ ale \ alq \ ${_amd_ecc_inject} \ ${_amdsbwd} \ ${_amdsmn} \ ${_amdtemp} \ amr \ ${_an} \ ${_aout} \ ${_apm} \ ${_arcmsr} \ ${_arcnet} \ ${_armv8crypto} \ ${_asmc} \ ata \ ath \ ath_dfs \ ath_hal \ ath_hal_ar5210 \ ath_hal_ar5211 \ ath_hal_ar5212 \ ath_hal_ar5416 \ ath_hal_ar9300 \ ath_main \ ath_rate \ ath_pci \ ${_autofs} \ ${_auxio} \ ${_bce} \ ${_bcm283x_clkman} \ ${_bcm283x_pwm} \ bfe \ bge \ bhnd \ ${_bxe} \ ${_bios} \ ${_bktr} \ ${_bm} \ bnxt \ bridgestp \ bwi \ bwn \ - bwn_pci \ ${_bytgpio} \ cam \ ${_cardbus} \ ${_carp} \ cas \ ${_cbb} \ cc \ ${_ccp} \ cd9660 \ cd9660_iconv \ ${_ce} \ ${_cfi} \ chacha20 \ ${_chromebook_platform} \ ${_ciss} \ cloudabi \ ${_cloudabi32} \ ${_cloudabi64} \ ${_cm} \ ${_cmx} \ ${_coff} \ ${_coretemp} \ ${_cp} \ ${_cpsw} \ ${_cpuctl} \ ${_cpufreq} \ ${_crypto} \ ${_cryptodev} \ ${_cs} \ ${_ctau} \ ctl \ ${_cxgb} \ ${_cxgbe} \ dc \ dcons \ dcons_crom \ de \ ${_dpms} \ ${_dpt} \ ${_drm} \ ${_drm2} \ dummynet \ ${_ed} \ ${_efirt} \ ${_em} \ ${_ena} \ ${_ep} \ ${_epic} \ esp \ ${_et} \ evdev \ ${_ex} \ ${_exca} \ ext2fs \ fdc \ fdescfs \ ${_fe} \ ${_ffec} \ filemon \ firewire \ firmware \ fuse \ ${_fxp} \ gem \ geom \ ${_glxiic} \ ${_glxsb} \ gpio \ hifn \ hme \ ${_hpt27xx} \ ${_hptiop} \ ${_hptmv} \ ${_hptnr} \ ${_hptrr} \ hwpmc \ ${_hwpmc_mips24k} \ ${_hwpmc_mips74k} \ ${_hyperv} \ i2c \ ${_ibcore} \ ${_ibcs2} \ ${_ichwd} \ ${_ida} \ if_bridge \ if_disc \ if_edsc \ ${_if_enc} \ if_epair \ ${_if_gif} \ ${_if_gre} \ ${_if_me} \ if_lagg \ ${_if_ndis} \ ${_if_stf} \ if_tap \ if_tun \ if_vlan \ if_vxlan \ ${_iir} \ imgact_binmisc \ ${_intelspi} \ ${_io} \ ${_ioat} \ ${_ipoib} \ ${_ipdivert} \ ${_ipfilter} \ ${_ipfw} \ ipfw_nat \ ${_ipfw_nat64} \ ${_ipfw_nptv6} \ ${_ipfw_pmod} \ ${_ipmi} \ ip6_mroute_mod \ ip_mroute_mod \ ${_ips} \ ${_ipsec} \ ${_ipw} \ ${_ipwfw} \ ${_isci} \ ${_iser} \ isp \ ${_ispfw} \ ${_iwi} \ ${_iwifw} \ ${_iwm} \ ${_iwmfw} \ ${_iwn} \ ${_iwnfw} \ ${_ix} \ ${_ixv} \ ${_ixgb} \ ${_ixl} \ ${_ixlv} \ jme \ joy \ kbdmux \ kgssapi \ kgssapi_krb5 \ khelp \ krpc \ ksyms \ le \ lge \ libalias \ libiconv \ libmchain \ ${_linprocfs} \ ${_linsysfs} \ ${_linux} \ ${_linux_common} \ ${_linux64} \ linuxkpi \ ${_lio} \ lmc \ lpt \ mac_biba \ mac_bsdextended \ mac_ifoff \ mac_lomac \ mac_mls \ mac_none \ mac_partition \ mac_portacl \ mac_seeotheruids \ mac_stub \ mac_test \ malo \ md \ mdio \ mem \ mfi \ mii \ mlx \ ${_mlx4} \ ${_mlx4ib} \ ${_mlx4en} \ ${_mlx5} \ ${_mlx5en} \ ${_mlx5ib} \ ${_mly} \ mmc \ mmcsd \ mpr \ mps \ mpt \ mqueue \ mrsas \ msdosfs \ msdosfs_iconv \ ${_mse} \ msk \ mvs \ mwl \ ${_mwlfw} \ mxge \ my \ ${_nandfs} \ ${_nandsim} \ ${_ncr} \ ${_nctgpio} \ ${_ncv} \ ${_ndis} \ ${_netgraph} \ ${_nfe} \ nfscl \ nfscommon \ nfsd \ nfslock \ nfslockd \ nfssvc \ nge \ nmdm \ ${_nsp} \ nullfs \ ${_ntb} \ ${_nvd} \ ${_nvme} \ ${_nvram} \ ${_nxge} \ oce \ otus \ ${_otusfw} \ ow \ ${_padlock} \ ${_padlock_rng} \ ${_pccard} \ ${_pcfclock} \ pcn \ ${_pf} \ ${_pflog} \ ${_pfsync} \ plip \ ${_pms} \ ppbus \ ppc \ ppi \ pps \ procfs \ proto \ pseudofs \ ${_pst} \ pty \ puc \ ${_qlxge} \ ${_qlxgb} \ ${_qlxgbe} \ ${_qlnx} \ ral \ ${_ralfw} \ ${_random_fortuna} \ ${_random_yarrow} \ ${_random_other} \ rc4 \ ${_rdma} \ ${_rdrand_rng} \ re \ rl \ rtwn \ rtwn_pci \ rtwn_usb \ ${_rtwnfw} \ ${_s3} \ ${_safe} \ ${_sbni} \ scc \ ${_scsi_low} \ sdhci \ ${_sdhci_acpi} \ sdhci_pci \ sem \ send \ ${_sf} \ ${_sfxge} \ sge \ ${_sgx} \ ${_sgx_linux} \ - siba_bwn \ siftr \ siis \ sis \ sk \ smbfs \ sn \ snp \ sound \ ${_speaker} \ spigen \ ${_splash} \ ${_sppp} \ ste \ ${_stg} \ stge \ ${_sym} \ ${_syscons} \ sysvipc \ tcp \ ${_ti} \ tl \ tmpfs \ ${_toecore} \ ${_tpm} \ trm \ ${_twa} \ twe \ tws \ tx \ ${_txp} \ uart \ ubsec \ udf \ udf_iconv \ ufs \ uinput \ unionfs \ usb \ ${_vesa} \ ${_virtio} \ vge \ ${_viawd} \ videomode \ vkbd \ ${_vmm} \ ${_vmware} \ ${_vpo} \ vr \ vte \ vx \ ${_vxge} \ wb \ ${_wbwd} \ ${_wi} \ wlan \ wlan_acl \ wlan_amrr \ wlan_ccmp \ wlan_rssadapt \ wlan_tkip \ wlan_wep \ wlan_xauth \ ${_wpi} \ ${_wpifw} \ ${_x86bios} \ ${_xe} \ xl \ zlib .if ${MK_AUTOFS} != "no" || defined(ALL_MODULES) _autofs= autofs .endif .if ${MK_CDDL} != "no" || defined(ALL_MODULES) .if (${MACHINE_CPUARCH} != "arm" || ${MACHINE_ARCH:Marmv[67]*} != "") && \ ${MACHINE_CPUARCH} != "mips" && \ ${MACHINE_CPUARCH} != "sparc64" SUBDIR+= dtrace .endif SUBDIR+= opensolaris .endif .if ${MK_CRYPT} != "no" || defined(ALL_MODULES) .if exists(${SRCTOP}/sys/opencrypto) _crypto= crypto _cryptodev= cryptodev _random_fortuna=random_fortuna _random_yarrow= random_yarrow _random_other= random_other .endif .endif .if ${MK_CUSE} != "no" || defined(ALL_MODULES) SUBDIR+= cuse .endif .if (${MK_INET_SUPPORT} != "no" || ${MK_INET6_SUPPORT} != "no") || \ defined(ALL_MODULES) _carp= carp _toecore= toecore _if_enc= if_enc _if_gif= if_gif _if_gre= if_gre _ipfw_pmod= ipfw_pmod .if ${MK_IPSEC_SUPPORT} != "no" _ipsec= ipsec .endif .endif .if (${MK_INET_SUPPORT} != "no" && ${MK_INET6_SUPPORT} != "no") || \ defined(ALL_MODULES) _if_stf= if_stf .endif .if ${MK_INET_SUPPORT} != "no" || defined(ALL_MODULES) _if_me= if_me _ipdivert= ipdivert _ipfw= ipfw .if ${MK_INET6_SUPPORT} != "no" || defined(ALL_MODULES) _ipfw_nat64= ipfw_nat64 .endif .endif .if ${MK_INET6_SUPPORT} != "no" || defined(ALL_MODULES) _ipfw_nptv6= ipfw_nptv6 .endif .if ${MK_IPFILTER} != "no" || defined(ALL_MODULES) _ipfilter= ipfilter .endif .if ${MK_ISCSI} != "no" || defined(ALL_MODULES) SUBDIR+= cfiscsi SUBDIR+= iscsi SUBDIR+= iscsi_initiator .endif .if ${MK_NAND} != "no" || defined(ALL_MODULES) _nandfs= nandfs _nandsim= nandsim .endif .if ${MK_NETGRAPH} != "no" || defined(ALL_MODULES) _netgraph= netgraph .endif .if (${MK_PF} != "no" && (${MK_INET_SUPPORT} != "no" || \ ${MK_INET6_SUPPORT} != "no")) || defined(ALL_MODULES) _pf= pf _pflog= pflog .if ${MK_INET_SUPPORT} != "no" _pfsync= pfsync .endif .endif .if ${MK_SOURCELESS_UCODE} != "no" _bce= bce _fxp= fxp _ispfw= ispfw _sf= sf _ti= ti _txp= txp .if ${MACHINE_CPUARCH} != "mips" _mwlfw= mwlfw _otusfw= otusfw _ralfw= ralfw _rtwnfw= rtwnfw .endif .endif .if ${MK_SOURCELESS_UCODE} != "no" && ${MACHINE_CPUARCH} != "arm" && \ ${MACHINE_CPUARCH} != "mips" && \ ${MACHINE_ARCH} != "powerpc" && ${MACHINE_ARCH} != "powerpcspe" && \ ${MACHINE_CPUARCH} != "riscv" _cxgbe= cxgbe .endif .if ${MK_TESTS} != "no" || defined(ALL_MODULES) SUBDIR+= tests .endif .if ${MK_ZFS} != "no" || defined(ALL_MODULES) SUBDIR+= zfs .endif .if (${MACHINE_CPUARCH} == "mips" && ${MACHINE_ARCH:Mmips64} == "") _hwpmc_mips24k= hwpmc_mips24k _hwpmc_mips74k= hwpmc_mips74k .endif .if ${MACHINE_CPUARCH} != "aarch64" && ${MACHINE_CPUARCH} != "arm" && \ ${MACHINE_CPUARCH} != "mips" && ${MACHINE_CPUARCH} != "powerpc" && \ ${MACHINE_CPUARCH} != "riscv" _syscons= syscons _vpo= vpo .endif .if ${MACHINE_CPUARCH} != "mips" # no BUS_SPACE_UNSPECIFIED # No barrier instruction support (specific to this driver) _sym= sym # intr_disable() is a macro, causes problems .if ${MK_SOURCELESS_UCODE} != "no" _cxgb= cxgb .endif .endif .if ${MACHINE_CPUARCH} == "aarch64" _armv8crypto= armv8crypto _efirt= efirt _em= em .endif .if ${MACHINE_CPUARCH} == "i386" || ${MACHINE_CPUARCH} == "amd64" _agp= agp _an= an _aout= aout _bios= bios _bktr= bktr .if ${MK_SOURCELESS_UCODE} != "no" _bxe= bxe .endif _cardbus= cardbus _cbb= cbb _cpuctl= cpuctl _cpufreq= cpufreq _cs= cs _dpms= dpms _drm= drm _drm2= drm2 _ed= ed _em= em _ena= ena _ep= ep _et= et _exca= exca _fe= fe .if ${MK_OFED} != "no" || defined(ALL_MODULES) _ibcore= ibcore .endif _if_ndis= if_ndis _io= io .if ${MK_OFED} != "no" || defined(ALL_MODULES) _ipoib= ipoib _iser= iser .endif _ix= ix _ixv= ixv _linprocfs= linprocfs _linsysfs= linsysfs _linux= linux .if ${MK_SOURCELESS_UCODE} != "no" _lio= lio .endif _nctgpio= nctgpio _ndis= ndis _pccard= pccard .if ${MK_OFED} != "no" || defined(ALL_MODULES) _rdma= rdma .endif _safe= safe _scsi_low= scsi_low _speaker= speaker _splash= splash _sppp= sppp _vmware= vmware _vxge= vxge _wbwd= wbwd _wi= wi _xe= xe _aac= aac _aacraid= aacraid _acpi= acpi .if ${MK_CRYPT} != "no" || defined(ALL_MODULES) _aesni= aesni .endif _amd_ecc_inject=amd_ecc_inject _amdsbwd= amdsbwd _amdsmn= amdsmn _amdtemp= amdtemp _arcmsr= arcmsr _asmc= asmc _bytgpio= bytgpio _ciss= ciss _chromebook_platform= chromebook_platform _cmx= cmx _coretemp= coretemp .if ${MK_SOURCELESS_HOST} != "no" _hpt27xx= hpt27xx .endif _hptiop= hptiop .if ${MK_SOURCELESS_HOST} != "no" _hptmv= hptmv _hptnr= hptnr _hptrr= hptrr .endif _hyperv= hyperv _ichwd= ichwd _ida= ida _iir= iir _intelspi= intelspi _ipmi= ipmi _ips= ips _isci= isci _ipw= ipw _iwi= iwi _iwm= iwm _iwn= iwn _ixgb= ixgb .if ${MK_SOURCELESS_UCODE} != "no" _ipwfw= ipwfw _iwifw= iwifw _iwmfw= iwmfw _iwnfw= iwnfw .endif _mlx4= mlx4 _mlx5= mlx5 .if (${MK_INET_SUPPORT} != "no" && ${MK_INET6_SUPPORT} != "no") || \ defined(ALL_MODULES) _mlx4en= mlx4en _mlx5en= mlx5en .endif .if ${MK_OFED} != "no" || defined(ALL_MODULES) _mlx4ib= mlx4ib _mlx5ib= mlx5ib .endif _mly= mly _nfe= nfe _nvd= nvd _nvme= nvme _nvram= nvram _nxge= nxge .if ${MK_CRYPT} != "no" || defined(ALL_MODULES) _padlock= padlock _padlock_rng= padlock_rng _rdrand_rng= rdrand_rng .endif _s3= s3 _sdhci_acpi= sdhci_acpi _tpm= tpm _twa= twa _vesa= vesa _viawd= viawd _virtio= virtio _wpi= wpi .if ${MK_SOURCELESS_UCODE} != "no" _wpifw= wpifw .endif _x86bios= x86bios .endif .if ${MACHINE_CPUARCH} == "amd64" _ccp= ccp _efirt= efirt _ioat= ioat _ixl= ixl _ixlv= ixlv _linux64= linux64 _linux_common= linux_common _ntb= ntb _pms= pms _qlxge= qlxge _qlxgb= qlxgb .if ${MK_SOURCELESS_UCODE} != "no" _qlxgbe= qlxgbe _qlnx= qlnx .endif _sfxge= sfxge _sgx= sgx _sgx_linux= sgx_linux .if ${MK_BHYVE} != "no" || defined(ALL_MODULES) _vmm= vmm .endif .endif .if ${MACHINE_CPUARCH} == "i386" # XXX some of these can move to the general case when de-i386'ed # XXX some of these can move now, but are untested on other architectures. _3dfx= 3dfx _3dfx_linux= 3dfx_linux _aic= aic _apm= apm _arcnet= arcnet .if ${MK_SOURCELESS_UCODE} != "no" _ce= ce .endif _coff= coff .if ${MK_SOURCELESS_UCODE} != "no" _cp= cp .endif _glxiic= glxiic _glxsb= glxsb #_ibcs2= ibcs2 _mse= mse _ncr= ncr _ncv= ncv _nsp= nsp _pcfclock= pcfclock _pst= pst _sbni= sbni _stg= stg _cm= cm .if ${MK_SOURCELESS_UCODE} != "no" _ctau= ctau .endif _dpt= dpt _ex= ex .endif .if ${MACHINE_CPUARCH} == "arm" _cfi= cfi _cpsw= cpsw .endif .if ${MACHINE_CPUARCH} == "powerpc" _agp= agp _an= an _bm= bm _cardbus= cardbus _cbb= cbb _cfi= cfi _cpufreq= cpufreq _drm= drm _exca= exca _ffec= ffec _pccard= pccard _wi= wi .endif .if ${MACHINE_ARCH} == "powerpc64" _drm2= drm2 .endif .if ${MACHINE_ARCH} == "powerpc64" || ${MACHINE_ARCH} == "powerpc" # Don't build powermac_nvram for powerpcspe, it's never supported. _nvram= powermac_nvram .endif .if ${MACHINE_CPUARCH} == "sparc64" _auxio= auxio _em= em _epic= epic .endif .if (${MACHINE_CPUARCH} == "aarch64" || ${MACHINE_CPUARCH} == "amd64" || \ ${MACHINE_ARCH:Marmv[67]*} != "" || ${MACHINE_CPUARCH} == "i386") _cloudabi32= cloudabi32 .endif .if ${MACHINE_CPUARCH} == "aarch64" || ${MACHINE_CPUARCH} == "amd64" _cloudabi64= cloudabi64 .endif .endif .if ${MACHINE_ARCH:Marmv[67]*} != "" || ${MACHINE_CPUARCH} == "aarch64" _bcm283x_clkman= bcm283x_clkman _bcm283x_pwm= bcm283x_pwm .endif .if ${MACHINE_ARCH:Marmv[67]*} != "" _ffec= ffec .endif SUBDIR+=${MODULES_EXTRA} .for reject in ${WITHOUT_MODULES} SUBDIR:= ${SUBDIR:N${reject}} .endfor # Calling kldxref(8) for each module is expensive. .if !defined(NO_XREF) .MAKEFLAGS+= -DNO_XREF afterinstall: .PHONY @if type kldxref >/dev/null 2>&1; then \ ${ECHO} kldxref ${DESTDIR}${KMODDIR}; \ kldxref ${DESTDIR}${KMODDIR}; \ fi .endif .include "${SYSDIR}/conf/config.mk" SUBDIR:= ${SUBDIR:u:O} .include Index: head/sys/modules/bwn/Makefile =================================================================== --- head/sys/modules/bwn/Makefile (revision 328911) +++ head/sys/modules/bwn/Makefile (revision 328912) @@ -1,40 +1,45 @@ # $FreeBSD$ .PATH: ${SRCTOP}/sys/dev/bwn KMOD= if_bwn SRCS= if_bwn.c if_bwnreg.h if_bwnvar.h -SRCS+= if_bwn_siba.c if_bwn_bhnd.c if_bwn_siba_compat.c +SRCS+= if_bwn_pci.c SRCS+= if_bwn_util.c # PHY SRCS+= if_bwn_phy_common.c SRCS+= if_bwn_phy_g.c if_bwn_phy_lp.c SRCS+= if_bwn_phy_n.c # BHND SRCS+= bhnd_bus_if.h \ bhnd_chipc_if.h \ bhnd_pmu_if.h \ bhnd_pwrctl_if.h SRCS+= bhnd_nvram_map.h +# BHNDB +SRCS+= bhndb_bus_if.h \ + bhndb_if.h + # Other SRCS+= device_if.h bus_if.h gpio_if.h pci_if.h opt_bwn.h opt_wlan.h # The following need the BWN_GPL_PHY kenrel option to opt-in # to the GPL'd 802.11n PHY support for this driver. .PATH: ${SRCTOP}/sys/gnu/dev/bwn/phy_n SRCS.BWN_GPL_PHY+= if_bwn_radio_2055.c SRCS.BWN_GPL_PHY+= if_bwn_radio_2056.c SRCS.BWN_GPL_PHY+= if_bwn_radio_2057.c +SRCS.BWN_GPL_PHY+= if_bwn_phy_n_sprom.c SRCS.BWN_GPL_PHY+= if_bwn_phy_n_tables.c SRCS.BWN_GPL_PHY+= if_bwn_phy_n_ppr.c SRCS.BWN_GPL_PHY+= if_bwn_phy_n_core.c .include # XXX Work around clang warnings, until maintainer approves fix. CWARNFLAGS.if_bwn.c= ${NO_WSOMETIMES_UNINITIALIZED} CWARNFLAGS.if_bwn_phy_g.c= ${NO_WSOMETIMES_UNINITIALIZED} ${NO_WCONSTANT_CONVERSION} CWARNFLAGS.if_bwn_phy_lp.c= ${NO_WSOMETIMES_UNINITIALIZED}