Index: head/sys/mips/conf/AP135.hints
===================================================================
--- head/sys/mips/conf/AP135.hints	(revision 328755)
+++ head/sys/mips/conf/AP135.hints	(revision 328756)
@@ -1,189 +1,179 @@
 # This is a placeholder until the hardware support is complete.
 
 # I'm assuming this is an AP135-020. The AP136-010 in openwrt has
 # the ethernet ports wired up to the switch in the reverse way.
 
 # $FreeBSD$
 
 # QCA955X_ETH_CFG_RGMII_EN (1 << 0)
 hint.qca955x_gmac.0.gmac_cfg=0x1
 
 # mdiobus0 on arge0
 hint.argemdio.0.at="nexus0"
 hint.argemdio.0.maddr=0x19000000
 hint.argemdio.0.msize=0x1000
 hint.argemdio.0.order=0
 
 # mdiobus1 on arge1 - required to bring up arge1?
 hint.argemdio.1.at="nexus0"
 hint.argemdio.1.maddr=0x1a000000
 hint.argemdio.1.msize=0x1000
 hint.argemdio.1.order=0
 
 # AR8327 - connected via mdiobus0 on arge0
 hint.arswitch.0.at="mdio0"
 hint.arswitch.0.is_7240=0	# definitely not the internal switch!
 hint.arswitch.0.is_9340=0	# not the internal switch!
 hint.arswitch.0.numphys=5	# all ports are PHYs
 hint.arswitch.0.phy4cpu=0
 hint.arswitch.0.is_rgmii=0	# not needed
 hint.arswitch.0.is_gmii=0	# not needed
 
 # This is where it gets a bit odd. port 0 and port 6 are CPU ports.
 # The current code only supports one CPU port.  So hm, what should
 # we do to hook PAD6 up to be RGMII but a PHY, not a MAC?
 
 # The other trick - how do we get arge1 (hooked up to GMAC0) to work?
 # That's currently supposed to be hooked up to CPU port 0.
 
 # Other AR8327 configuration parameters
 
 # AP136-020 parameters
 
 # GMAC0 AR8327 -> GMAC1 (arge1) SoC, SGMII
 
 # AR8327_PAD_MAC_SGMII
 hint.arswitch.0.pad.0.mode=3
 #hint.arswitch.0.pad.0.rxclk_delay_sel=0
 hint.arswitch.0.pad.0.sgmii_delay_en=1
 
 # GMAC6 AR8327 -> GMAC0 (arge0) SoC, RGMII
 
 # AR8327_PAD_MAC_RGMII
 # XXX I think this hooks it up to the internal MAC6
 hint.arswitch.0.pad.6.mode=6
 hint.arswitch.0.pad.6.txclk_delay_en=1
 hint.arswitch.0.pad.6.rxclk_delay_en=1
 # AR8327_CLK_DELAY_SEL1
 hint.arswitch.0.pad.6.txclk_delay_sel=1
 # AR8327_CLK_DELAY_SEL2
 hint.arswitch.0.pad.6.rxclk_delay_sel=2
 
 # XXX there's no LED management just yet!
 hint.arswitch.0.led.ctrl0=0x00000000
 hint.arswitch.0.led.ctrl1=0xc737c737
 hint.arswitch.0.led.ctrl2=0x00000000
 hint.arswitch.0.led.ctrl3=0x00c30c00
 hint.arswitch.0.led.open_drain=1
 
 # force_link=1 is required for the rest of the parameters
 # to be configured.
 hint.arswitch.0.port.0.force_link=1
 hint.arswitch.0.port.0.speed=1000
 hint.arswitch.0.port.0.duplex=1
 hint.arswitch.0.port.0.txpause=1
 hint.arswitch.0.port.0.rxpause=1
 
 # force_link=1 is required for the rest of the parameters
 # to be configured.
 hint.arswitch.0.port.6.force_link=1
 hint.arswitch.0.port.6.speed=1000
 hint.arswitch.0.port.6.duplex=1
 hint.arswitch.0.port.6.txpause=1
 hint.arswitch.0.port.6.rxpause=1
 
 # arge0 - hooked up to AR8327 GMAC6, RGMII
 # set at 1000/full to the switch.
 # so, lock both sides of this connect up to 1000/full;
 # if_arge thus wont change the PLL configuration
 # upon a link status change.
 hint.arge.0.phymask=0x0
 hint.arge.0.miimode=3           # RGMII
 hint.arge.0.media=1000
 hint.arge.0.fduplex=1
 hint.arge.0.pll_1000=0x56000000
 
 # MAC for arge0 is the first 6 bytes of the ART
 hint.arge.0.eeprommac=0x1fff0000
 
 # arge1 - lock up to 1000/full
 hint.arge.1.phymask=0x0
 hint.arge.1.media=1000
 hint.arge.1.fduplex=1
 hint.arge.1.miimode=5		# SGMII
 hint.arge.1.pll_1000=0x03000101
 
 # MAC for arge1 is the second 6 bytes of the ART
 hint.arge.1.eeprommac=0x1fff0006
 
-# ath0: Where the ART is - last 64k in the flash
-hint.ath.0.eepromaddr=0x1fff0000
-hint.ath.0.eepromsize=16384
+# Where the ART is - last 64k in the first 8MB of flash
+hint.ar71xx_caldata.0.map.0.ath_fixup_addr=0x1fff0000
+hint.ar71xx_caldata.0.map.0.ath_fixup_size=16384
 
-# ath1: it's different; it's a PCIe attached device, so
-# we instead need to teach the PCIe bridge code about it
-# (ie, the 'early pci fixup' stuff that programs the PCIe
-# host registers on the NIC) and then we teach ath where
-# to find it.
-
-# ath1 hint - pcie slot 0
-# hint.pcib.0.bus.0.0.0.ath_fixup_addr=0x1fff4000
-# hint.pcib.0.bus.0.0.0.ath_fixup_size=16384
-
-# ath0 - eeprom comes from here
-# hint.ath.1.eeprom_firmware="pcib.0.bus.0.0.0.eeprom_firmware"
+# And now tell the ath(4) driver where to look!
+hint.ath.0.eeprom_firmware="ar71xx_caldata.0.map.0.eeprom_firmware"
 
 # flash layout:
 #
 # bootargs=console=ttyS0,115200 root=31:02 rootfstype=jffs2 init=/sbin/init mtdparts=ath-nor0:256k(u-boot),64k(u-boot-env),6336k(rootfs),1408k(uImage),8256k(mib0),64k(ART)
 
 # The default flash layout isn't enough to fit a freebsd kernel
 # now, so the layout has been shuffled around.
 #
 # By default it's set to:
 # 256KB uboot, 64KB uboot-env, 6336KB rootfs, 1344KB kernel, 64KB cfg, 8256MB mib0, 64KB ART
 # With 'bootcmd=bootm 0x9f680000' in the environment.
 #
 # Instead, now let's make it:
 # 256KB uboot, 64KB uboot-env, 2048MB kernel, 6144MB rootfs, 7644KB mib0, 64KB cfg, 64KB ART
 # .. and then you change the boot env to be:
 # 'bootcmd=bootm 0x9f050000'
 
 # 256KiB u-boot
 hint.map.0.at="flash/spi0"
 hint.map.0.start=0x00000000
 hint.map.0.end=0x00040000	# 256k u-boot
 hint.map.0.name="u-boot"
 hint.map.0.readonly=1
 
 # 64KiB u-boot-env
 hint.map.1.at="flash/spi0"
 hint.map.1.start=0x00040000
 hint.map.1.end=0x00050000	# 64k u-boot-env
 hint.map.1.name="u-boot-env"
 hint.map.1.readonly=1
 
 # 2048KiB kernel
 hint.map.2.at="flash/spi0"
 hint.map.2.start=0x00050000
 hint.map.2.end=0x00250000	# 2048k rootfs
 hint.map.2.name="kernel"
 hint.map.2.readonly=1
 
 # 6144KiB rootfs
 hint.map.3.at="flash/spi0"
 hint.map.3.start=0x00250000
 hint.map.3.end=0x00850000
 hint.map.3.name="rootfs"
 hint.map.3.readonly=1
 
 # 7644KiB mib0
 hint.map.4.at="flash/spi0"
 hint.map.4.start=0x00850000
 hint.map.4.end=0x00fe0000
 hint.map.4.name="mib0"
 hint.map.4.readonly=0
 
 # 64KiB cfg
 hint.map.5.at="flash/spi0"
 hint.map.5.start=0x00fe0000
 hint.map.5.end=0x00ff0000
 hint.map.5.name="cfg"
 hint.map.5.readonly=0
 
 # 64KiB ART
 hint.map.6.at="flash/spi0"
 hint.map.6.start=0x00ff0000
 hint.map.6.end=0x01000000	# 64k ART
 hint.map.6.name="ART"
 hint.map.6.readonly=1
Index: head/sys/mips/conf/AP143.hints
===================================================================
--- head/sys/mips/conf/AP143.hints	(revision 328755)
+++ head/sys/mips/conf/AP143.hints	(revision 328756)
@@ -1,109 +1,112 @@
 #
 # This file adds to the values in QCA953X_BASE.hints.
 #
 # $FreeBSD$
 
 # Embedded Atheros Switch
 hint.arswitch.0.at="mdio1"
 hint.arswitch.0.is_7240=0
 hint.arswitch.0.is_9340=1
 hint.arswitch.0.numphys=4
 hint.arswitch.0.phy4cpu=1	# phy 4 is a "CPU" separate PHY
 hint.arswitch.0.is_rgmii=0
 hint.arswitch.0.is_gmii=1	# arge1 <-> switch PHY is GMII
 
 # arge0 - MII, autoneg, phy(4)
 # MAC for arge0 is the first 6 bytes of the ART
 hint.arge.0.eeprommac=0x1fff0000
 hint.arge.0.phymask=0x10	# PHY4
 hint.arge.0.mdio=mdioproxy2	# .. off of the switch mdiobus
 
 # arge1 - GMII, 1000/full
 hint.arge.1.eeprommac=0x1fff0006
 hint.arge.1.phymask=0x0		# No directly mapped PHYs
 hint.arge.1.media=1000
 hint.arge.1.fduplex=1
 
-# ath0: Where the ART is - last 64k in the flash
-hint.ath.0.eepromaddr=0x1fff0000
-hint.ath.0.eepromsize=16384
+# Where the ART is - last 64k in the first 8MB of flash
+hint.ar71xx_caldata.0.map.0.ath_fixup_addr=0x1fff0000
+hint.ar71xx_caldata.0.map.0.ath_fixup_size=16384
+
+# And now tell the ath(4) driver where to look!
+hint.ath.0.eeprom_firmware="ar71xx_caldata.0.map.0.eeprom_firmware"
 
 # The AP121 4MB flash layout:
 #
 # bootargs=console=ttyS0,115200 root=31:02 rootfstype=squashfs
 #    init=/sbin/init mtdparts=ar7240-nor0:256k(u-boot),64k(u-boot-env),
 #    2752k(rootfs),896k(uImage),64k(NVRAM),64k(ART)
 #
 # So:
 # 256k: uboot
 # 64: uboot-env
 # 2752k: rootfs
 # 896k: kernel
 # 64k: config
 # 64k: ART
 
 hint.map.0.at="flash/spi0"
 hint.map.0.start=0x00000000
 hint.map.0.end=0x000040000
 hint.map.0.name="uboot"
 hint.map.0.readonly=1
 
 hint.map.1.at="flash/spi0"
 hint.map.1.start=0x00040000
 hint.map.1.end=0x00050000
 hint.map.1.name="uboot-env"
 hint.map.1.readonly=0
 
 hint.map.2.at="flash/spi0"
 hint.map.2.start=0x00050000
 hint.map.2.end=0x00300000
 hint.map.2.name="rootfs"
 hint.map.2.readonly=0
 
 hint.map.3.at="flash/spi0"
 hint.map.3.start=0x00300000
 hint.map.3.end=0x003e0000
 hint.map.3.name="kernel"
 hint.map.3.readonly=0
 
 hint.map.4.at="flash/spi0"
 hint.map.4.start=0x003e0000
 hint.map.4.end=0x003f0000
 hint.map.4.name="cfg"
 hint.map.4.readonly=0
 
 # This is radio calibration section.  It is (or should be!) unique
 # for each board, to take into account thermal and electrical differences
 # as well as the regulatory compliance data.
 #
 hint.map.5.at="flash/spi0"
 hint.map.5.start=0x003f0000
 hint.map.5.end=0x00400000
 hint.map.5.name="art"
 hint.map.5.readonly=1
 
 # GPIO specific configuration block
 
 # Don't flip on anything that isn't already enabled.
 # This includes leaving the SPI CS1/CS2 pins as GPIO pins as they're
 # not used here.
 hint.gpio.0.function_set=0x00000000
 hint.gpio.0.function_clear=0x00000000
 
 # These are the GPIO LEDs and buttons which can be software controlled.
 #hint.gpio.0.pinmask=0x001c02ae
 # hint.gpio.0.pinmask=0x00001803
 
 # gpio0 - WLAN LED
 # gpio1 - USB LED
 # gpio11 - Jumpstart button
 # gpio12 - Reset button
 
 # LEDs are configured separately and driven by the LED device
 #hint.gpioled.0.at="gpiobus0"
 #hint.gpioled.0.name="wlan"
 #hint.gpioled.0.pins=0x0001
 
 #hint.gpioled.1.at="gpiobus0"
 #hint.gpioled.1.name="usb"
 #hint.gpioled.1.pins=0x0002