Index: head/sys/powerpc/powermac/uninorthpci.c =================================================================== --- head/sys/powerpc/powermac/uninorthpci.c (revision 327797) +++ head/sys/powerpc/powermac/uninorthpci.c (revision 327798) @@ -1,265 +1,280 @@ /*- * SPDX-License-Identifier: BSD-2-Clause-FreeBSD * * Copyright (C) 2002 Benno Rice. * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY Benno Rice ``AS IS'' AND ANY EXPRESS OR * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. * IN NO EVENT SHALL TOOLS GMBH BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ #include __FBSDID("$FreeBSD$"); #include #include #include #include #include #include +#include +#include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include "pcib_if.h" #define UNINORTH_DEBUG 0 /* * Device interface. */ static int uninorth_probe(device_t); static int uninorth_attach(device_t); /* * pcib interface. */ static u_int32_t uninorth_read_config(device_t, u_int, u_int, u_int, u_int, int); static void uninorth_write_config(device_t, u_int, u_int, u_int, u_int, u_int32_t, int); /* * Local routines. */ static int uninorth_enable_config(struct uninorth_softc *, u_int, u_int, u_int, u_int); /* * Driver methods. */ static device_method_t uninorth_methods[] = { /* Device interface */ DEVMETHOD(device_probe, uninorth_probe), DEVMETHOD(device_attach, uninorth_attach), /* pcib interface */ DEVMETHOD(pcib_read_config, uninorth_read_config), DEVMETHOD(pcib_write_config, uninorth_write_config), DEVMETHOD_END }; static devclass_t uninorth_devclass; DEFINE_CLASS_1(pcib, uninorth_driver, uninorth_methods, sizeof(struct uninorth_softc), ofw_pci_driver); DRIVER_MODULE(uninorth, ofwbus, uninorth_driver, uninorth_devclass, 0, 0); static int uninorth_probe(device_t dev) { const char *type, *compatible; type = ofw_bus_get_type(dev); compatible = ofw_bus_get_compat(dev); if (type == NULL || compatible == NULL) return (ENXIO); if (strcmp(type, "pci") != 0) return (ENXIO); if (strcmp(compatible, "uni-north") == 0) { device_set_desc(dev, "Apple UniNorth Host-PCI bridge"); return (0); } else if (strcmp(compatible, "u3-agp") == 0) { device_set_desc(dev, "Apple U3 Host-AGP bridge"); return (0); } else if (strcmp(compatible, "u4-pcie") == 0) { device_set_desc(dev, "IBM CPC945 PCI Express Root"); return (0); } return (ENXIO); } static int uninorth_attach(device_t dev) { struct uninorth_softc *sc; const char *compatible; + const char *name; phandle_t node; uint32_t reg[3]; uint64_t regbase; cell_t acells; + int unit; node = ofw_bus_get_node(dev); sc = device_get_softc(dev); + name = device_get_name(dev); + unit = device_get_unit(dev); if (OF_getprop(node, "reg", reg, sizeof(reg)) < 8) return (ENXIO); sc->sc_ver = 0; compatible = ofw_bus_get_compat(dev); if (strcmp(compatible, "u3-agp") == 0) sc->sc_ver = 3; if (strcmp(compatible, "u4-pcie") == 0) sc->sc_ver = 4; acells = 1; OF_getprop(OF_parent(node), "#address-cells", &acells, sizeof(acells)); regbase = reg[0]; if (acells == 2) { regbase <<= 32; regbase |= reg[1]; } sc->sc_addr = (vm_offset_t)pmap_mapdev(regbase + 0x800000, PAGE_SIZE); sc->sc_data = (vm_offset_t)pmap_mapdev(regbase + 0xc00000, PAGE_SIZE); + if (resource_int_value(name, unit, "skipslot", &sc->sc_skipslot) != 0) + sc->sc_skipslot = -1; + + mtx_init(&sc->sc_cfg_mtx, "uninorth pcicfg", NULL, MTX_SPIN); + return (ofw_pci_attach(dev)); } static u_int32_t uninorth_read_config(device_t dev, u_int bus, u_int slot, u_int func, u_int reg, int width) { struct uninorth_softc *sc; vm_offset_t caoff; + u_int32_t val; sc = device_get_softc(dev); caoff = sc->sc_data + (reg & 0x07); + val = 0xffffffff; + mtx_lock_spin(&sc->sc_cfg_mtx); if (uninorth_enable_config(sc, bus, slot, func, reg) != 0) { switch (width) { case 1: - return (in8rb(caoff)); + val = in8rb(caoff); break; case 2: - return (in16rb(caoff)); + val = in16rb(caoff); break; case 4: - return (in32rb(caoff)); + val = in32rb(caoff); break; } } + mtx_unlock_spin(&sc->sc_cfg_mtx); - return (0xffffffff); + return (val); } static void uninorth_write_config(device_t dev, u_int bus, u_int slot, u_int func, u_int reg, u_int32_t val, int width) { struct uninorth_softc *sc; vm_offset_t caoff; sc = device_get_softc(dev); caoff = sc->sc_data + (reg & 0x07); + mtx_lock_spin(&sc->sc_cfg_mtx); if (uninorth_enable_config(sc, bus, slot, func, reg)) { switch (width) { case 1: out8rb(caoff, val); break; case 2: out16rb(caoff, val); break; case 4: out32rb(caoff, val); break; } } + mtx_unlock_spin(&sc->sc_cfg_mtx); } static int uninorth_enable_config(struct uninorth_softc *sc, u_int bus, u_int slot, u_int func, u_int reg) { uint32_t cfgval; - uint32_t pass; - if (resource_int_value(device_get_name(sc->pci_sc.sc_dev), - device_get_unit(sc->pci_sc.sc_dev), "skipslot", &pass) == 0) { - if (pass == slot) - return (0); - } + mtx_assert(&sc->sc_cfg_mtx, MA_OWNED); + + if (sc->sc_skipslot == slot) + return (0); /* * Issue type 0 configuration space accesses for the root bus. * * NOTE: On U4, issue only type 1 accesses. There is a secret * PCI Express <-> PCI Express bridge not present in the device tree, * and we need to route all of our configuration space through it. */ if (sc->pci_sc.sc_bus == bus && sc->sc_ver < 4) { /* * No slots less than 11 on the primary bus on U3 and lower */ if (slot < 11) return (0); cfgval = (1 << slot) | (func << 8) | (reg & 0xfc); } else { cfgval = (bus << 16) | (slot << 11) | (func << 8) | (reg & 0xfc) | 1; } /* Set extended register bits on U4 */ if (sc->sc_ver == 4) cfgval |= (reg >> 8) << 28; do { out32rb(sc->sc_addr, cfgval); } while (in32rb(sc->sc_addr) != cfgval); return (1); } Index: head/sys/powerpc/powermac/uninorthvar.h =================================================================== --- head/sys/powerpc/powermac/uninorthvar.h (revision 327797) +++ head/sys/powerpc/powermac/uninorthvar.h (revision 327798) @@ -1,109 +1,111 @@ /*- * SPDX-License-Identifier: BSD-2-Clause-FreeBSD * * Copyright (C) 2002 Benno Rice. * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY Benno Rice ``AS IS'' AND ANY EXPRESS OR * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. * IN NO EVENT SHALL TOOLS GMBH BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * * $FreeBSD$ */ #ifndef _POWERPC_POWERMAC_UNINORTHVAR_H_ #define _POWERPC_POWERMAC_UNINORTHVAR_H_ #include #include #include struct uninorth_softc { struct ofw_pci_softc pci_sc; vm_offset_t sc_addr; vm_offset_t sc_data; int sc_ver; + int sc_skipslot; + struct mtx sc_cfg_mtx; }; struct unin_chip_softc { uint64_t sc_physaddr; uint64_t sc_size; vm_offset_t sc_addr; struct rman sc_mem_rman; int sc_version; }; /* * Format of a unin reg property entry. */ struct unin_chip_reg { u_int32_t mr_base; u_int32_t mr_size; }; /* * Per unin device structure. */ struct unin_chip_devinfo { int udi_interrupts[6]; int udi_ninterrupts; int udi_base; struct ofw_bus_devinfo udi_obdinfo; struct resource_list udi_resources; }; /* * Version register */ #define UNIN_VERS 0x0 /* * Clock-control register */ #define UNIN_CLOCKCNTL 0x20 #define UNIN_CLOCKCNTL_GMAC 0x2 /* * Power management register */ #define UNIN_PWR_MGMT 0x30 #define UNIN_PWR_NORMAL 0x00 #define UNIN_PWR_IDLE2 0x01 #define UNIN_PWR_SLEEP 0x02 #define UNIN_PWR_SAVE 0x03 #define UNIN_PWR_MASK 0x03 /* * Hardware initialization state register */ #define UNIN_HWINIT_STATE 0x70 #define UNIN_SLEEPING 0x01 #define UNIN_RUNNING 0x02 /* * Toggle registers */ #define UNIN_TOGGLE_REG 0xe0 #define UNIN_MPIC_RESET 0x2 #define UNIN_MPIC_OUTPUT_ENABLE 0x4 extern int unin_chip_sleep(device_t dev, int idle); extern int unin_chip_wake(device_t dev); #endif /* _POWERPC_POWERMAC_UNINORTHVAR_H_ */