Index: head/sys/mips/rmi/xlr_csum_nocopy.S =================================================================== --- head/sys/mips/rmi/xlr_csum_nocopy.S (revision 327460) +++ head/sys/mips/rmi/xlr_csum_nocopy.S (nonexistent) @@ -1,217 +0,0 @@ -#include - - -/* - * a0: source address - * a1: length of the area to checksum - * a2: partial checksum - * a3: dst - */ - -#define src a0 -#define dst a3 -#define sum v0 - - .text - .set noreorder - - .macro CSUM_BIGCHUNK_AND_COPY offset - pref 0, (\offset+0x0)(a0) - ld t0, (\offset+0x00)(a0) - ld t1, (\offset+0x08)(a0) - .word 0x70481038 /*daddwc v0, v0, t0 */ - .word 0x70491038 /*daddwc v0, v0, t1 */ - ld t0, (\offset + 0x10)(a0) - ld t1, (\offset + 0x18)(a0) - .word 0x70481038 /* daddwc v0, v0, t0 */ - .word 0x70491038 /*daddwc v0, v0, t1 */ - .endm - -small_csumcpy: /* unknown src alignment and < 8 bytes to go */ - move a1, t2 - - andi t0, a1, 4 - beqz t0, 1f - andi t0, a1, 2 - - ulw t1, (src) /* Still a full word to go */ - daddiu src, 4 - .word 0x70491038 /*daddwc v0, v0, t1 */ - -1: move t1, zero - beqz t0, 1f - andi t0, a1, 1 - - ulhu t1, (src) /* Still a halfword to go */ - daddiu src, 2 - -1: beqz t0, 1f - sll t1, t1, 16 - - lbu t2, (src) - nop - -#ifdef __MIPSEB__ - sll t2, t2, 8 -#endif - or t1, t2 - -1: .word 0x70491038 /*daddwc v0, v0, t1 */ - - .word 0x70461038 /*daddwc v0, v0, a2 */ - .word 0x70401038 /*daddwc v0, v0, $0 */ - - /* Ideally at this point of time the status flag must be cleared */ - - dsll32 v1, sum, 0 - .word 0x70431038 /*daddwc v0, v0, v1 */ - dsrl32 sum, sum, 0 - .word 0x70401038 /*daddwc v0, v0, zero */ - - /* fold the checksum */ - sll v1, sum, 16 - addu sum, v1 - sltu v1, sum, v1 - srl sum, sum, 16 - addu sum, v1 -1: - .set reorder - jr ra - .set noreorder - -/* ------------------------------------------------------------------ */ - - .align 5 -LEAF(xlr_csum_partial_nocopy) - move sum, zero - move t7, zero - - sltiu t8, a1, 0x8 - bnez t8, small_csumcpy /* < 8 bytes to copy */ - move t2, a1 - - beqz a1, out - andi t7, src, 0x1 /* odd buffer? */ - -hword_align: - beqz t7, word_align - andi t8, src, 0x2 - - lbu t0, (src) - dsubu a1, a1, 0x1 - .word 0x70481038 /*daddwc v0, v0, t0 */ - daddu src, src, 0x1 - andi t8, src, 0x2 - -word_align: - beqz t8, dword_align - sltiu t8, a1, 56 - - lhu t0, (src) - dsubu a1, a1, 0x2 - .word 0x70481038 /*daddwc v0, v0, t0 */ - sltiu t8, a1, 56 - daddu src, src, 0x2 - -dword_align: - bnez t8, do_end_words - move t8, a1 - - andi t8, src, 0x4 - beqz t8, qword_align - andi t8, src, 0x8 - - lw t0, 0x00(src) - dsubu a1, a1, 0x4 - .word 0x70481038 /*daddwc v0, v0, t0 */ - daddu src, src, 0x4 - andi t8, src, 0x8 - -qword_align: - beqz t8, oword_align - andi t8, src, 0x10 - - ld t0, 0x00(src) - dsubu a1, a1, 0x8 - .word 0x70481038 /*daddwc v0, v0, t0 */ - daddu src, src, 0x8 - andi t8, src, 0x10 - -oword_align: - beqz t8, begin_movement - dsrl t8, a1, 0x7 - - ld t3, 0x08(src) - ld t0, 0x00(src) - .word 0x704b1038 /*daddwc v0, v0, t3 */ - .word 0x70481038 /*daddwc v0, v0, t0 */ - dsubu a1, a1, 0x10 - daddu src, src, 0x10 - dsrl t8, a1, 0x7 - -begin_movement: - beqz t8, 1f - andi t2, a1, 0x40 - -move_128bytes: - pref 0, 0x20(a0) - pref 0, 0x40(a0) - pref 0, 0x60(a0) - CSUM_BIGCHUNK_AND_COPY(0x00) - CSUM_BIGCHUNK_AND_COPY(0x20) - CSUM_BIGCHUNK_AND_COPY(0x40) - CSUM_BIGCHUNK_AND_COPY(0x60) - dsubu t8, t8, 0x01 - bnez t8, move_128bytes /* flag */ - daddu src, src, 0x80 - -1: - beqz t2, 1f - andi t2, a1, 0x20 - -move_64bytes: - pref 0, 0x20(a0) - pref 0, 0x40(a0) - CSUM_BIGCHUNK_AND_COPY(0x00) - CSUM_BIGCHUNK_AND_COPY(0x20) - daddu src, src, 0x40 - -1: - beqz t2, do_end_words - andi t8, a1, 0x1c - -move_32bytes: - pref 0, 0x20(a0) - CSUM_BIGCHUNK_AND_COPY(0x00) - andi t8, a1, 0x1c - daddu src, src, 0x20 - -do_end_words: - beqz t8, maybe_end_cruft - dsrl t8, t8, 0x2 - -end_words: - lw t0, (src) - dsubu t8, t8, 0x1 - .word 0x70481038 /*daddwc v0, v0, t0 */ - bnez t8, end_words - daddu src, src, 0x4 - -maybe_end_cruft: - andi t2, a1, 0x3 - -small_memcpy: - j small_csumcpy; move a1, t2 - beqz t2, out - move a1, t2 - -end_bytes: - lb t0, (src) - dsubu a1, a1, 0x1 - bnez a2, end_bytes - daddu src, src, 0x1 - -out: - jr ra - move v0, sum - END(xlr_csum_partial_nocopy) Property changes on: head/sys/mips/rmi/xlr_csum_nocopy.S ___________________________________________________________________ Deleted: svn:eol-style ## -1 +0,0 ## -native \ No newline at end of property Deleted: svn:keywords ## -1 +0,0 ## -FreeBSD=%H \ No newline at end of property Deleted: svn:mime-type ## -1 +0,0 ## -text/plain \ No newline at end of property Index: head/sys/mips/rmi/iomap.h =================================================================== --- head/sys/mips/rmi/iomap.h (revision 327460) +++ head/sys/mips/rmi/iomap.h (nonexistent) @@ -1,117 +0,0 @@ -/*- - * SPDX-License-Identifier: BSD-3-Clause - * - * Copyright (c) 2003-2009 RMI Corporation - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. Neither the name of RMI Corporation, nor the names of its contributors, - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - * - * RMI_BSD - * $FreeBSD$ - */ -#ifndef _RMI_IOMAP_H_ -#define _RMI_IOMAP_H_ - -#include -#define XLR_DEVICE_REGISTER_BASE 0x1EF00000 -#define DEFAULT_XLR_IO_BASE 0xffffffffbef00000ULL -#define XLR_IO_SIZE 0x1000 - -#define XLR_IO_BRIDGE_OFFSET 0x00000 - -#define XLR_IO_DDR2_CHN0_OFFSET 0x01000 -#define XLR_IO_DDR2_CHN1_OFFSET 0x02000 -#define XLR_IO_DDR2_CHN2_OFFSET 0x03000 -#define XLR_IO_DDR2_CHN3_OFFSET 0x04000 - -#define XLR_IO_RLD2_CHN0_OFFSET 0x05000 -#define XLR_IO_RLD2_CHN1_OFFSET 0x06000 - -#define XLR_IO_SRAM_OFFSET 0x07000 - -#define XLR_IO_PIC_OFFSET 0x08000 -#define XLR_IO_PCIX_OFFSET 0x09000 -#define XLR_IO_HT_OFFSET 0x0A000 - -#define XLR_IO_SECURITY_OFFSET 0x0B000 - -#define XLR_IO_GMAC_0_OFFSET 0x0C000 -#define XLR_IO_GMAC_1_OFFSET 0x0D000 -#define XLR_IO_GMAC_2_OFFSET 0x0E000 -#define XLR_IO_GMAC_3_OFFSET 0x0F000 - -#define XLR_IO_SPI4_0_OFFSET 0x10000 -#define XLR_IO_XGMAC_0_OFFSET 0x11000 -#define XLR_IO_SPI4_1_OFFSET 0x12000 -#define XLR_IO_XGMAC_1_OFFSET 0x13000 - -#define XLR_IO_UART_0_OFFSET 0x14000 -#define XLR_IO_UART_1_OFFSET 0x15000 -#define XLR_UART0ADDR (XLR_IO_UART_0_OFFSET+XLR_DEVICE_REGISTER_BASE) - - - -#define XLR_IO_I2C_0_OFFSET 0x16000 -#define XLR_IO_I2C_1_OFFSET 0x17000 - -#define XLR_IO_GPIO_OFFSET 0x18000 - -#define XLR_IO_FLASH_OFFSET 0x19000 - -#define XLR_IO_TB_OFFSET 0x1C000 - -#define XLR_IO_GMAC_4_OFFSET 0x20000 -#define XLR_IO_GMAC_5_OFFSET 0x21000 -#define XLR_IO_GMAC_6_OFFSET 0x22000 -#define XLR_IO_GMAC_7_OFFSET 0x23000 - -#define XLR_IO_PCIE_0_OFFSET 0x1E000 -#define XLR_IO_PCIE_1_OFFSET 0x1F000 - -#define XLR_IO_USB_0_OFFSET 0x24000 -#define XLR_IO_USB_1_OFFSET 0x25000 - -#define XLR_IO_COMP_OFFSET 0x1d000 - -/* Base Address (Virtual) of the PCI Config address space - * For now, choose 256M phys in kseg1 = 0xA0000000 + (1<<28) - * Config space spans 256 (num of buses) * 256 (num functions) * 256 bytes - * ie 1<<24 = 16M - */ -#define DEFAULT_PCI_CONFIG_BASE 0x18000000 -#define DEFAULT_HT_TYPE0_CFG_BASE 0x16000000 -#define DEFAULT_HT_TYPE1_CFG_BASE 0x17000000 - -typedef volatile __uint32_t xlr_reg_t; -extern unsigned long xlr_io_base; - -#define xlr_io_mmio(offset) ((xlr_reg_t *)(xlr_io_base+(offset))) - -#define xlr_read_reg(base, offset) (__ntohl((base)[(offset)])) -#define xlr_write_reg(base, offset, value) ((base)[(offset)] = __htonl((value))) - -extern void on_chip_init(void); - -#endif /* _RMI_IOMAP_H_ */ Property changes on: head/sys/mips/rmi/iomap.h ___________________________________________________________________ Deleted: svn:eol-style ## -1 +0,0 ## -native \ No newline at end of property Deleted: svn:keywords ## -1 +0,0 ## -FreeBSD=%H \ No newline at end of property Deleted: svn:mime-type ## -1 +0,0 ## -text/plain \ No newline at end of property Index: head/sys/mips/rmi/board.c =================================================================== --- head/sys/mips/rmi/board.c (revision 327460) +++ head/sys/mips/rmi/board.c (nonexistent) @@ -1,595 +0,0 @@ -/********************************************************************* - * SPDX-License-Identifier: BSD-2-Clause-FreeBSD - * - * - * Copyright 2003-2006 Raza Microelectronics, Inc. (RMI). All rights - * reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * - * THIS SOFTWARE IS PROVIDED BY Raza Microelectronics, Inc. ``AS IS'' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR - * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL RMI OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES, LOSS OF USE, DATA, OR PROFITS, OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF - * THE POSSIBILITY OF SUCH DAMAGE. - * - * *****************************RMI_2**********************************/ -#include /* RCS ID & Copyright macro defns */ -__FBSDID("$FreeBSD$"); -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include -#include - -#define XLR_I2C_RTC_ADDR 0xd0 -#define XLR_I2C_EEPROM_ADDR 0xa0 -#define XLR_I2C_TEMPSENSOR_ADDR 0x98 -#define XLR_I2C_ATX8_TEMPSENSOR_ADDR 0x9a - -struct stn_cc *xlr_core_cc_configs[] = { &cc_table_cpu_0, &cc_table_cpu_1, - &cc_table_cpu_2, &cc_table_cpu_3, &cc_table_cpu_4, &cc_table_cpu_5, - &cc_table_cpu_6, &cc_table_cpu_7}; - -struct stn_cc *xls_core_cc_configs[] = { &xls_cc_table_cpu_0, &xls_cc_table_cpu_1, - &xls_cc_table_cpu_2, &xls_cc_table_cpu_3 }; - -struct xlr_board_info xlr_board_info; - -static int -xlr_pcmcia_present(void) -{ - xlr_reg_t *mmio = xlr_io_mmio(XLR_IO_GPIO_OFFSET); - uint32_t resetconf; - - resetconf = xlr_read_reg(mmio, 21); - return ((resetconf & 0x4000) != 0); -} - -static void -xlr_chip_specific_overrides(struct xlr_board_info* board) -{ - struct xlr_gmac_block_t *blk0, *blk1, *blk2; - uint32_t chipid; - uint32_t revision; - - blk0 = &board->gmac_block[0]; - blk1 = &board->gmac_block[1]; - blk2 = &board->gmac_block[2]; - - chipid = xlr_processor_id(); - revision = xlr_revision(); - - if (revision == 0x04) { /* B2 */ - switch (chipid) { - case 0x07: /* XLR 508 */ - case 0x08: /* XLR 516 */ - case 0x09: /* XLR 532 */ - /* NA[12] not available */ - memset(blk1, 0, sizeof(*blk1)); - memset(blk2, 0, sizeof(*blk2)); - break; - case 0x06: /* XLR 308 */ - /* NA0 has 3 ports */ - blk0->gmac_port[3].valid = 0; - blk0->num_ports--; - /* NA[12] not available */ - memset(blk1, 0, sizeof(*blk1)); - memset(blk2, 0, sizeof(*blk2)); - break; - default: - break; - } - } else if (revision == 0x91) { /* C4 */ - switch (chipid) { - case 0x0B: /* XLR 508 */ - case 0x0A: /* XLR 516 */ - case 0x08: /* XLR 532 */ - /* NA[12] not available */ - memset(blk1, 0, sizeof(*blk1)); - memset(blk2, 0, sizeof(*blk2)); - break; - case 0x0F: /* XLR 308 */ - /* NA0 has 3 ports */ - blk0->gmac_port[3].valid = 0; - blk0->num_ports--; - /* NA[12] not available */ - memset(blk1, 0, sizeof(*blk1)); - memset(blk2, 0, sizeof(*blk2)); - break; - default: - break; - } - } else { /* other pre-production silicon */ - switch (chipid) { - /* XLR 5xx */ - case 0x0B: - case 0x0A: - case 0x07: - case 0x08: - case 0x09: - /* NA[12] not available */ - memset(blk1, 0, sizeof(*blk1)); - memset(blk2, 0, sizeof(*blk2)); - break; - /* XLR 3xx */ - case 0x0F: - case 0x06: - /* NA0 has 3 ports */ - blk0->gmac_port[3].valid = 0; - blk0->num_ports--; - /* NA[12] not available */ - memset(blk1, 0, sizeof(*blk1)); - memset(blk2, 0, sizeof(*blk2)); - break; - default: - break; - } - } -} - -static void -xlr_board_specific_overrides(struct xlr_board_info* board) -{ - struct xlr_gmac_block_t *blk1, *blk2; - - blk1 = &board->gmac_block[1]; - blk2 = &board->gmac_block[2]; - - switch (xlr_boot1_info.board_major_version) { - case RMI_XLR_BOARD_ARIZONA_I: - /* ATX-I has SPI-4, not XGMAC */ - blk1->type = XLR_SPI4; - blk1->enabled = 0; /* nlge does not - support SPI-4 */ - blk2->type = XLR_SPI4; - blk2->enabled = 0; - break; - - case RMI_XLR_BOARD_ARIZONA_II: - /* XGMII_A --> VSC7281, XGMII_B --> VSC7281 */ - blk1->enabled = 1; - blk1->num_ports = 1; - blk1->gmac_port[0].valid = 1; - - blk2->enabled = 1; - blk2->num_ports = 1; - blk2->gmac_port[0].valid = 1; - default: - break; - } -} - -static int -quad0_xaui(void) -{ - xlr_reg_t *gpio_mmio = - (unsigned int *)(DEFAULT_XLR_IO_BASE + XLR_IO_GPIO_OFFSET); - uint32_t bit24; - - bit24 = (xlr_read_reg(gpio_mmio, 0x15) >> 24) & 0x1; - return (bit24); -} - -static int -quad1_xaui(void) -{ - xlr_reg_t *gpio_mmio = - (unsigned int *)(DEFAULT_XLR_IO_BASE + XLR_IO_GPIO_OFFSET); - uint32_t bit25; - - bit25 = (xlr_read_reg(gpio_mmio, 0x15) >> 25) & 0x1; - return (bit25); -} - -static void -xls_chip_specific_overrides(struct xlr_board_info* board) -{ - struct xlr_gmac_block_t *blk0, *blk1; - uint32_t chipid; - - blk0 = &board->gmac_block[0]; - blk1 = &board->gmac_block[1]; - chipid = xlr_processor_id(); - - switch (chipid) { - case 0x8E: /* XLS208 */ - case 0x8F: /* XLS204 */ - /* NA1 is not available */ - memset(blk1, 0, sizeof(*blk1)); - break; - case 0xCE: /* XLS108 */ - case 0xCF: /* XLS104 */ - /* NA0 has 3 ports */ - blk0->gmac_port[3].valid = 0; - blk0->num_ports--; - /* NA1 is not available */ - memset(blk1, 0, sizeof(*blk1)); - break; - default: - break; - } -} - -static void -xls_board_specific_overrides(struct xlr_board_info* board) -{ - struct xlr_gmac_block_t *blk0, *blk1; - int i; - struct xlr_i2c_dev_t* iic_blk; - - blk0 = &board->gmac_block[0]; - blk1 = &board->gmac_block[1]; - - switch (xlr_boot1_info.board_major_version) { - case RMI_XLR_BOARD_ARIZONA_VI: - blk0->mode = XLR_PORT0_RGMII; - blk0->gmac_port[0].type = XLR_RGMII; - blk0->gmac_port[0].phy_addr = 0; - blk0->gmac_port[0].mii_addr = XLR_IO_GMAC_4_OFFSET; - /* Because of the Octal PHY, SGMII Quad1 is MII is also bound - * to the PHY attached to SGMII0_MDC/MDIO/MDINT. */ - for (i = 0; i < 4; i++) { - blk1->gmac_port[i].mii_addr = XLR_IO_GMAC_0_OFFSET; - blk1->gmac_port[i].serdes_addr = XLR_IO_GMAC_0_OFFSET; - } - blk1->gmac_port[1].mii_addr = XLR_IO_GMAC_0_OFFSET; - blk1->gmac_port[2].mii_addr = XLR_IO_GMAC_0_OFFSET; - blk1->gmac_port[3].mii_addr = XLR_IO_GMAC_0_OFFSET; - - blk1->gmac_port[1].serdes_addr = XLR_IO_GMAC_0_OFFSET; - blk1->gmac_port[2].serdes_addr = XLR_IO_GMAC_0_OFFSET; - blk1->gmac_port[3].serdes_addr = XLR_IO_GMAC_0_OFFSET; - - /* RGMII MDIO interrupt is thru NA1 and SGMII MDIO - * interrupts for ports in blk1 are from NA0 */ - blk0->gmac_port[0].mdint_id = 1; - - blk1->gmac_port[0].mdint_id = 0; - blk1->gmac_port[1].mdint_id = 0; - blk1->gmac_port[2].mdint_id = 0; - blk1->gmac_port[3].mdint_id = 0; - - /* If we have a 4xx lite chip, don't enable the - * GMACs which are disabled in hardware */ - if (xlr_is_xls4xx_lite()) { - xlr_reg_t *mmio = xlr_io_mmio(XLR_IO_GPIO_OFFSET); - uint32_t tmp; - - /* Port 6 & 7 are not enabled on the condor 4xx, figure - * this out from the GPIO fuse bank */ - tmp = xlr_read_reg(mmio, 35); - if ((tmp & (3 << 28)) != 0) { - blk1->enabled = 0x3; - blk1->gmac_port[2].valid = 0; - blk1->gmac_port[3].valid = 0; - blk1->num_ports = 2; - } - } - break; - - case RMI_XLR_BOARD_ARIZONA_VIII: - iic_blk = &xlr_board_info.xlr_i2c_device[I2C_THERMAL]; - if (iic_blk->enabled) { - iic_blk->addr = XLR_I2C_ATX8_TEMPSENSOR_ADDR; - } - if (blk1->enabled) { - /* There is just one Octal PHY on the board and it is - * connected to the MII interface for NA Quad 0. */ - for (i = 0; i < 4; i++) { - blk1->gmac_port[i].mii_addr = - XLR_IO_GMAC_0_OFFSET; - blk1->gmac_port[i].mdint_id = 0; - } - } - break; - - case RMI_XLR_BOARD_ARIZONA_XI: - case RMI_XLR_BOARD_ARIZONA_XII: - if (quad0_xaui()) { /* GMAC ports 0-3 are set to XAUI */ - /* only GMAC0 is active i.e, the 0-th port on this quad. - * Disable all the other 7 possible ports. */ - for (i = 1; i < MAX_NA_PORTS; i++) { - memset(&blk0->gmac_port[i], 0, - sizeof(blk0->gmac_port[i])); - } - /* Setup for XAUI on N/w Acc0: gmac0 */ - blk0->type = XLR_XGMAC; - blk0->mode = XLR_XAUI; - blk0->num_ports = 1; - blk0->gmac_port[0].type = XLR_XAUI; - blk1->gmac_port[0].phy_addr = 16; - blk0->gmac_port[0].tx_bucket_id = blk0->station_txbase; - /* Other addresses etc need not be modified as XAUI_0 - * shares its addresses with SGMII GMAC_0, which was - * set in the caller. */ - } - else { - blk0->num_ports = 1; /* only 1 RGMII port */ - blk0->mode = XLR_PORT0_RGMII; - blk0->gmac_port[0].type = XLR_RGMII; - blk0->gmac_port[0].phy_addr = 0; - blk0->gmac_port[0].mii_addr = XLR_IO_GMAC_0_OFFSET; - } - - if (quad1_xaui()) { /* GMAC ports 4-7 are used for XAUI */ - /* only GMAC4 is active i.e, the 0-th port on this quad. - * Disable all the other 7 possible ports. */ - for (i = 1; i < MAX_NA_PORTS; i++) { - memset(&blk1->gmac_port[i], 0, - sizeof(blk1->gmac_port[i])); - } - /* Setup for XAUI on N/w Acc1: gmac4 */ - blk1->type = XLR_XGMAC; - blk1->mode = XLR_XAUI; - blk1->num_ports = 1; - /* XAUI and SGMII ports share FMN buckets on N/w Acc 1; - so, station_txbase, station_rfr need not be - patched up. */ - blk1->gmac_port[0].type = XLR_XAUI; - blk1->gmac_port[0].phy_addr = 16; - blk1->gmac_port[0].tx_bucket_id = blk1->station_txbase; - /* Other addresses etc need not be modified as XAUI_1 - * shares its addresses with SGMII GMAC_4, which was - * set in the caller. */ - } - break; - - default: - break; - } -} - -/* - * All our knowledge of chip and board that cannot be detected by probing - * at run-time goes here - */ -int -xlr_board_info_setup() -{ - struct xlr_gmac_block_t *blk0, *blk1, *blk2; - struct xlr_i2c_dev_t* iic_blk; - int i; - - /* This setup code is long'ish because the same base driver - * (if_nlge.c) is used for different: - * - CPUs (XLR/XLS) - * - boards (for each CPU, multiple board configs are possible - * and available). - * - * At the time of writing, there are atleast 12 boards, 4 with XLR - * and 8 with XLS. This means that the base driver needs to work with - * 12 different configurations, with varying levels of differences. - * To accomodate the different configs, the xlr_board_info struct - * has various attributes for paramters that could be different. - * These attributes are setup here and can be used directly in the - * base driver. - * It was seen that the setup code is not entirely trivial and - * it is possible to organize it in different ways. In the following, - * we choose an approach that sacrifices code-compactness/speed for - * readability. This is because configuration code executes once - * per reboot and hence has a minimal performance impact. - * On the other hand, driver debugging/enhancements require - * that different engineers can quickly comprehend the setup - * sequence. Hence, readability is seen as the key requirement for - * this code. It is for the reader to decide how much of this - * requirement is met with the current code organization !! - * - * The initialization is organized thus: - * - * if (CPU is XLS) { - * // initialize per XLS architecture - * // default inits (per chip spec) - * // chip-specific overrides - * // board-specific overrides - * } else if (CPU is XLR) { - * // initialize per XLR architecture - * // default inits (per chip spec) - * // chip-specific overrides - * // board-specific overrides - * } - * - * For each CPU family, all the default initializations - * are done for a fully-loaded device of that family. - * This configuration is then adjusted for the actual - * chip id. This is followed up with board specific - * overrides. - */ - - /* start with a clean slate */ - memset(&xlr_board_info, 0, sizeof(xlr_board_info)); - xlr_board_info.ata = xlr_pcmcia_present(); - - blk0 = &xlr_board_info.gmac_block[0]; - blk1 = &xlr_board_info.gmac_block[1]; - blk2 = &xlr_board_info.gmac_block[2]; - - iic_blk = xlr_board_info.xlr_i2c_device; - iic_blk[I2C_RTC].enabled = 1; - iic_blk[I2C_RTC].addr = XLR_I2C_RTC_ADDR; - iic_blk[I2C_THERMAL].enabled = 1; - iic_blk[I2C_THERMAL].addr = XLR_I2C_TEMPSENSOR_ADDR; - iic_blk[I2C_EEPROM].enabled = 1; - iic_blk[I2C_EEPROM].addr = XLR_I2C_EEPROM_ADDR; - - if (xlr_is_xls()) { - xlr_board_info.is_xls = 1; - xlr_board_info.nr_cpus = 8; - xlr_board_info.usb = 1; - /* Board version 8 has NAND flash */ - xlr_board_info.cfi = - (xlr_boot1_info.board_major_version != RMI_XLR_BOARD_ARIZONA_VIII); - xlr_board_info.pci_irq = 0; - xlr_board_info.credit_configs = xls_core_cc_configs; - xlr_board_info.bucket_sizes = &xls_bucket_sizes; - xlr_board_info.gmacports = MAX_NA_PORTS; - - /* ---------------- Network Acc 0 ---------------- */ - - blk0->type = XLR_GMAC; - blk0->enabled = 0xf; - blk0->credit_config = &xls_cc_table_gmac0; - blk0->station_id = MSGRNG_STNID_GMAC; - blk0->station_txbase = MSGRNG_STNID_GMACTX0; - blk0->station_rfr = MSGRNG_STNID_GMACRFR_0; - blk0->mode = XLR_SGMII; - blk0->baseaddr = XLR_IO_GMAC_0_OFFSET; - blk0->baseirq = PIC_GMAC_0_IRQ; - blk0->baseinst = 0; - - /* By default, assume SGMII is setup. But this can change based - on board-specific or setting-specific info. */ - for (i = 0; i < 4; i++) { - blk0->gmac_port[i].valid = 1; - blk0->gmac_port[i].instance = i + blk0->baseinst; - blk0->gmac_port[i].type = XLR_SGMII; - blk0->gmac_port[i].phy_addr = i + 16; - blk0->gmac_port[i].tx_bucket_id = - blk0->station_txbase + i; - blk0->gmac_port[i].mdint_id = 0; - blk0->num_ports++; - blk0->gmac_port[i].base_addr = XLR_IO_GMAC_0_OFFSET + i * 0x1000; - blk0->gmac_port[i].mii_addr = XLR_IO_GMAC_0_OFFSET; - blk0->gmac_port[i].pcs_addr = XLR_IO_GMAC_0_OFFSET; - blk0->gmac_port[i].serdes_addr = XLR_IO_GMAC_0_OFFSET; - } - - /* ---------------- Network Acc 1 ---------------- */ - blk1->type = XLR_GMAC; - blk1->enabled = 0xf; - blk1->credit_config = &xls_cc_table_gmac1; - blk1->station_id = MSGRNG_STNID_GMAC1; - blk1->station_txbase = MSGRNG_STNID_GMAC1_TX0; - blk1->station_rfr = MSGRNG_STNID_GMAC1_FR_0; - blk1->mode = XLR_SGMII; - blk1->baseaddr = XLR_IO_GMAC_4_OFFSET; - blk1->baseirq = PIC_XGS_0_IRQ; - blk1->baseinst = 4; - - for (i = 0; i < 4; i++) { - blk1->gmac_port[i].valid = 1; - blk1->gmac_port[i].instance = i + blk1->baseinst; - blk1->gmac_port[i].type = XLR_SGMII; - blk1->gmac_port[i].phy_addr = i + 20; - blk1->gmac_port[i].tx_bucket_id = - blk1->station_txbase + i; - blk1->gmac_port[i].mdint_id = 1; - blk1->num_ports++; - blk1->gmac_port[i].base_addr = XLR_IO_GMAC_4_OFFSET + i * 0x1000; - blk1->gmac_port[i].mii_addr = XLR_IO_GMAC_4_OFFSET; - blk1->gmac_port[i].pcs_addr = XLR_IO_GMAC_4_OFFSET; - blk1->gmac_port[i].serdes_addr = XLR_IO_GMAC_0_OFFSET; - } - - /* ---------------- Network Acc 2 ---------------- */ - xlr_board_info.gmac_block[2].enabled = 0; /* disabled on XLS */ - - xls_chip_specific_overrides(&xlr_board_info); - xls_board_specific_overrides(&xlr_board_info); - - } else { /* XLR */ - xlr_board_info.is_xls = 0; - xlr_board_info.nr_cpus = 32; - xlr_board_info.usb = 0; - xlr_board_info.cfi = 1; - xlr_board_info.pci_irq = 0; - xlr_board_info.credit_configs = xlr_core_cc_configs; - xlr_board_info.bucket_sizes = &bucket_sizes; - xlr_board_info.gmacports = 4; - - /* ---------------- GMAC0 ---------------- */ - blk0->type = XLR_GMAC; - blk0->enabled = 0xf; - blk0->credit_config = &cc_table_gmac; - blk0->station_id = MSGRNG_STNID_GMAC; - blk0->station_txbase = MSGRNG_STNID_GMACTX0; - blk0->station_rfr = MSGRNG_STNID_GMACRFR_0; - blk0->mode = XLR_RGMII; - blk0->baseaddr = XLR_IO_GMAC_0_OFFSET; - blk0->baseirq = PIC_GMAC_0_IRQ; - blk0->baseinst = 0; - - /* first, do the common/easy stuff for all the ports */ - for (i = 0; i < 4; i++) { - blk0->gmac_port[i].valid = 1; - blk0->gmac_port[i].instance = i + blk0->baseinst; - blk0->gmac_port[i].type = XLR_RGMII; - blk0->gmac_port[i].phy_addr = i; - blk0->gmac_port[i].tx_bucket_id = - blk0->station_txbase + i; - blk0->gmac_port[i].mdint_id = 0; - blk0->gmac_port[i].base_addr = XLR_IO_GMAC_0_OFFSET + i * 0x1000; - blk0->gmac_port[i].mii_addr = XLR_IO_GMAC_0_OFFSET; - /* RGMII ports, no PCS/SERDES */ - blk0->num_ports++; - } - - /* ---------------- XGMAC0 ---------------- */ - blk1->type = XLR_XGMAC; - blk1->mode = XLR_XGMII; - blk1->enabled = 0; - blk1->credit_config = &cc_table_xgs_0; - blk1->station_txbase = MSGRNG_STNID_XGS0_TX; - blk1->station_rfr = MSGRNG_STNID_XMAC0RFR; - blk1->station_id = MSGRNG_STNID_XGS0FR; - blk1->baseaddr = XLR_IO_XGMAC_0_OFFSET; - blk1->baseirq = PIC_XGS_0_IRQ; - blk1->baseinst = 4; - - blk1->gmac_port[0].type = XLR_XGMII; - blk1->gmac_port[0].instance = 0; - blk1->gmac_port[0].phy_addr = 0; - blk1->gmac_port[0].base_addr = XLR_IO_XGMAC_0_OFFSET; - blk1->gmac_port[0].mii_addr = XLR_IO_XGMAC_0_OFFSET; - blk1->gmac_port[0].tx_bucket_id = blk1->station_txbase; - blk1->gmac_port[0].mdint_id = 1; - - /* ---------------- XGMAC1 ---------------- */ - blk2->type = XLR_XGMAC; - blk2->mode = XLR_XGMII; - blk2->enabled = 0; - blk2->credit_config = &cc_table_xgs_1; - blk2->station_txbase = MSGRNG_STNID_XGS1_TX; - blk2->station_rfr = MSGRNG_STNID_XMAC1RFR; - blk2->station_id = MSGRNG_STNID_XGS1FR; - blk2->baseaddr = XLR_IO_XGMAC_1_OFFSET; - blk2->baseirq = PIC_XGS_1_IRQ; - blk2->baseinst = 5; - - blk2->gmac_port[0].type = XLR_XGMII; - blk2->gmac_port[0].instance = 0; - blk2->gmac_port[0].phy_addr = 0; - blk2->gmac_port[0].base_addr = XLR_IO_XGMAC_1_OFFSET; - blk2->gmac_port[0].mii_addr = XLR_IO_XGMAC_1_OFFSET; - blk2->gmac_port[0].tx_bucket_id = blk2->station_txbase; - blk2->gmac_port[0].mdint_id = 2; - - /* Done with default setup. Now handle chip and board-specific - variations. */ - xlr_chip_specific_overrides(&xlr_board_info); - xlr_board_specific_overrides(&xlr_board_info); - } - return 0; -} Property changes on: head/sys/mips/rmi/board.c ___________________________________________________________________ Deleted: svn:eol-style ## -1 +0,0 ## -native \ No newline at end of property Deleted: svn:keywords ## -1 +0,0 ## -FreeBSD=%H \ No newline at end of property Deleted: svn:mime-type ## -1 +0,0 ## -text/plain \ No newline at end of property Index: head/sys/mips/rmi/board.h =================================================================== --- head/sys/mips/rmi/board.h (revision 327460) +++ head/sys/mips/rmi/board.h (nonexistent) @@ -1,252 +0,0 @@ -/*- - * SPDX-License-Identifier: BSD-3-Clause - * - * Copyright (c) 2003-2009 RMI Corporation - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. Neither the name of RMI Corporation, nor the names of its contributors, - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - * - * RMI_BSD - * $FreeBSD$ - */ -#ifndef _RMI_BOARD_H_ -#define _RMI_BOARD_H_ - -/* - * Engineering boards have a major/minor number in their EEPROM to - * identify their configuration - */ -#define RMI_XLR_BOARD_ARIZONA_I 1 -#define RMI_XLR_BOARD_ARIZONA_II 2 -#define RMI_XLR_BOARD_ARIZONA_III 3 -#define RMI_XLR_BOARD_ARIZONA_IV 4 -#define RMI_XLR_BOARD_ARIZONA_V 5 -#define RMI_XLR_BOARD_ARIZONA_VI 6 -#define RMI_XLR_BOARD_ARIZONA_VII 7 -#define RMI_XLR_BOARD_ARIZONA_VIII 8 -#define RMI_XLR_BOARD_ARIZONA_XI 11 -#define RMI_XLR_BOARD_ARIZONA_XII 12 - -/* - * RMI Chips - Values in Processor ID field - */ -#define RMI_CHIP_XLR732 0x00 -#define RMI_CHIP_XLR716 0x02 -#define RMI_CHIP_XLR308 0x06 -#define RMI_CHIP_XLR532 0x09 - -/* - * XLR C revisions - */ -#define RMI_CHIP_XLR308_C 0x0F -#define RMI_CHIP_XLR508_C 0x0b -#define RMI_CHIP_XLR516_C 0x0a -#define RMI_CHIP_XLR532_C 0x08 - -/* - * XLS processors - */ -#define RMI_CHIP_XLS408 0x88 /* Lite "Condor" */ -#define RMI_CHIP_XLS608 0x80 /* Internal */ -#define RMI_CHIP_XLS404 0x8c /* Lite "Condor" */ -#define RMI_CHIP_XLS208 0x8e -#define RMI_CHIP_XLS204 0x8f -#define RMI_CHIP_XLS108 0xce -#define RMI_CHIP_XLS104 0xcf - -/* - * XLS B revision chips - */ -#define RMI_CHIP_XLS616_B0 0x40 -#define RMI_CHIP_XLS608_B0 0x4a -#define RMI_CHIP_XLS416_B0 0x44 -#define RMI_CHIP_XLS412_B0 0x4c -#define RMI_CHIP_XLS408_B0 0x4e -#define RMI_CHIP_XLS404_B0 0x4f - -/* - * The XLS product line has chip versions 0x4x and 0x8x - */ -static __inline unsigned int -xlr_is_xls(void) -{ - uint32_t prid = mips_rd_prid(); - - return ((prid & 0xf000) == 0x8000 || (prid & 0xf000) == 0x4000 || - (prid & 0xf000) == 0xc000); -} - -/* - * The last byte of the processor id field is revision - */ -static __inline unsigned int -xlr_revision(void) -{ - - return (mips_rd_prid() & 0xff); -} - -/* - * The 15:8 byte of the PR Id register is the Processor ID - */ -static __inline unsigned int -xlr_processor_id(void) -{ - - return ((mips_rd_prid() & 0xff00) >> 8); -} - -/* - * The processor is XLR and C-Series - */ -static __inline unsigned int -xlr_is_c_revision(void) -{ - int processor_id = xlr_processor_id(); - int revision_id = xlr_revision(); - - switch (processor_id) { - /* - * These are the relevant PIDs for XLR - * steppings (hawk and above). For these, - * PIDs, Rev-Ids of [5-9] indicate 'C'. - */ - case RMI_CHIP_XLR308_C: - case RMI_CHIP_XLR508_C: - case RMI_CHIP_XLR516_C: - case RMI_CHIP_XLR532_C: - case RMI_CHIP_XLR716: - case RMI_CHIP_XLR732: - if (revision_id >= 5 && revision_id <= 9) - return (1); - default: - return (0); - } - return (0); -} - -/* - * RMI Engineering boards which are PCI cards - * These should come up in PCI device mode (not yet) - */ -static __inline int -xlr_board_pci(int board_major) -{ - - return ((board_major == RMI_XLR_BOARD_ARIZONA_III) || - (board_major == RMI_XLR_BOARD_ARIZONA_V)); -} - -static __inline int -xlr_is_xls1xx(void) -{ - uint32_t chipid = xlr_processor_id(); - - return (chipid == 0xce || chipid == 0xcf); -} - -static __inline int -xlr_is_xls2xx(void) -{ - uint32_t chipid = xlr_processor_id(); - - return (chipid == 0x8e || chipid == 0x8f); -} - -static __inline int -xlr_is_xls4xx_lite(void) -{ - uint32_t chipid = xlr_processor_id(); - - return (chipid == 0x88 || chipid == 0x8c); -} - -static __inline unsigned int -xlr_is_xls_b0(void) -{ - uint32_t chipid = xlr_processor_id(); - - return (chipid >= 0x40 && chipid <= 0x4f); -} - -/* SPI-4 --> 8 ports, 1G MAC --> 4 ports and 10G MAC --> 1 port */ -#define MAX_NA_PORTS 8 - -/* all our knowledge of chip and board that cannot be detected run-time goes here */ -enum gmac_block_types { XLR_GMAC, XLR_XGMAC, XLR_SPI4}; -enum gmac_port_types { XLR_RGMII, XLR_SGMII, XLR_PORT0_RGMII, XLR_XGMII, XLR_XAUI }; -enum i2c_dev_types { I2C_RTC, I2C_THERMAL, I2C_EEPROM }; - -struct xlr_board_info { - int is_xls; - int nr_cpus; - int usb; /* usb enabled ? */ - int cfi; /* compact flash driver for NOR? */ - int ata; /* ata driver */ - int pci_irq; - struct stn_cc **credit_configs; /* pointer to Core station credits */ - struct bucket_size *bucket_sizes; /* pointer to Core station bucket */ - int *msgmap; /* mapping of message station to devices */ - int gmacports; /* number of gmac ports on the board */ - struct xlr_i2c_dev_t { - uint32_t addr; - unsigned int enabled; /* mask of devs enabled */ - int type; - int unit; - char *dev_name; - } xlr_i2c_device[3]; - struct xlr_gmac_block_t { /* refers to the set of GMACs controlled by a - network accelarator */ - int type; /* see enum gmac_block_types */ - unsigned int enabled; /* mask of ports enabled */ - struct stn_cc *credit_config; /* credit configuration */ - int station_id; /* station id for sending msgs */ - int station_txbase; /* station id for tx */ - int station_rfr; /* free desc bucket */ - int mode; /* see gmac_block_modes */ - uint32_t baseaddr; /* IO base */ - int baseirq; /* first irq for this block, the rest are in sequence */ - int baseinst; /* the first rge unit for this block */ - int num_ports; - struct xlr_gmac_port { - int valid; - int type; /* see enum gmac_port_types */ - uint32_t instance; /* identifies the GMAC to which - this port is bound to. */ - uint32_t phy_addr; - uint32_t base_addr; - uint32_t mii_addr; - uint32_t pcs_addr; - uint32_t serdes_addr; - uint32_t tx_bucket_id; - uint32_t mdint_id; - } gmac_port[MAX_NA_PORTS]; - } gmac_block [3]; -}; - -extern struct xlr_board_info xlr_board_info; -int xlr_board_info_setup(void); - -#endif Property changes on: head/sys/mips/rmi/board.h ___________________________________________________________________ Deleted: svn:eol-style ## -1 +0,0 ## -native \ No newline at end of property Deleted: svn:keywords ## -1 +0,0 ## -FreeBSD=%H \ No newline at end of property Deleted: svn:mime-type ## -1 +0,0 ## -text/plain \ No newline at end of property Index: head/sys/mips/rmi/xlr_i2c.c =================================================================== --- head/sys/mips/rmi/xlr_i2c.c (revision 327460) +++ head/sys/mips/rmi/xlr_i2c.c (nonexistent) @@ -1,418 +0,0 @@ -/*- - * SPDX-License-Identifier: BSD-3-Clause - * - * Copyright (c) 2003-2009 RMI Corporation - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. Neither the name of RMI Corporation, nor the names of its contributors, - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - * - * RMI_BSD */ - -#include -__FBSDID("$FreeBSD$"); - -/* - * I2C driver for the Palm-BK3220 I2C Host adapter on the RMI XLR. - */ - -#include -#include -#include -#include -#include -#include -#include -#include - - -#include -#include - -#include -#include -#include - -#include "iicbus_if.h" - -/* XLR I2C REGISTERS */ -#define XLR_I2C_CFG 0x00 -#define XLR_I2C_CLKDIV 0x01 -#define XLR_I2C_DEVADDR 0x02 -#define XLR_I2C_ADDR 0x03 -#define XLR_I2C_DATAOUT 0x04 -#define XLR_I2C_DATAIN 0x05 -#define XLR_I2C_STATUS 0x06 -#define XLR_I2C_STARTXFR 0x07 -#define XLR_I2C_BYTECNT 0x08 -#define XLR_I2C_HDSTATIM 0x09 - -/* XLR I2C REGISTERS FLAGS */ -#define XLR_I2C_BUS_BUSY 0x01 -#define XLR_I2C_SDOEMPTY 0x02 -#define XLR_I2C_RXRDY 0x04 -#define XLR_I2C_ACK_ERR 0x08 -#define XLR_I2C_ARB_STARTERR 0x30 - -/* Register Programming Values!! Change as required */ -#define XLR_I2C_CFG_ADDR 0xF8 /* 8-Bit dev Addr + POR Values */ -#define XLR_I2C_CFG_NOADDR 0xFA /* 8-Bit reg Addr + POR Values : No dev addr */ -#define XLR_I2C_STARTXFR_ND 0x02 /* No data , only addr */ -#define XLR_I2C_STARTXFR_RD 0x01 /* Read */ -#define XLR_I2C_STARTXFR_WR 0x00 /* Write */ -#define XLR_I2C_CLKDIV_DEF 0x14A /* 0x00000052 */ -#define XLR_I2C_HDSTATIM_DEF 0x107 /* 0x00000000 */ - -#define MAXTIME 0x10000 -#define ARIZONA_I2C_BUS 1 - -static devclass_t xlr_i2c_devclass; - -/* - * Device methods - */ -static int xlr_i2c_probe(device_t); -static int xlr_i2c_attach(device_t); -static int xlr_i2c_detach(device_t); - -static int xlr_i2c_start(device_t dev, u_char slave, int timeout); -static int xlr_i2c_stop(device_t dev); -static int xlr_i2c_read(device_t dev, char *buf, int len, int *read, int last, int delay); -static int xlr_i2c_write(device_t dev, const char *buf, int len, int *sent, int timeout); -static int xlr_i2c_callback(device_t dev, int index, caddr_t data); -static int xlr_i2c_repeated_start(device_t dev, u_char slave, int timeout); -static int xlr_i2c_transfer(device_t bus, struct iic_msg *msgs, uint32_t nmsgs); - -struct xlr_i2c_softc { - device_t dev; /* Self */ - struct resource *mem_res; /* Memory resource */ - volatile int flags; - int sc_started; - uint8_t i2cdev_addr; - xlr_reg_t *iobase_i2c_regs; - device_t iicbus; - struct mtx sc_mtx; -}; - -static void -set_i2c_base(device_t dev) -{ - struct xlr_i2c_softc *sc; - - sc = device_get_softc(dev); - if (device_get_unit(dev) == 0) - sc->iobase_i2c_regs = xlr_io_mmio(XLR_IO_I2C_0_OFFSET); - else - sc->iobase_i2c_regs = xlr_io_mmio(XLR_IO_I2C_1_OFFSET); -} - -static void -xlr_i2c_dev_write(device_t dev, int reg, int value) -{ - struct xlr_i2c_softc *sc; - - sc = device_get_softc(dev); - xlr_write_reg(sc->iobase_i2c_regs, reg, value); - return; -} - - -static int -xlr_i2c_dev_read(device_t dev, int reg) -{ - uint32_t val; - struct xlr_i2c_softc *sc; - - sc = device_get_softc(dev); - val = xlr_read_reg(sc->iobase_i2c_regs, reg); - return ((int)val); -} - - -static int -xlr_i2c_probe(device_t dev) -{ - device_set_desc(dev, "XLR/XLS I2C bus controller"); - - return (0); -} - - -/* - * We add all the devices which we know about. - * The generic attach routine will attach them if they are alive. - */ -static int -xlr_i2c_attach(device_t dev) -{ - int rid; - struct xlr_i2c_softc *sc; - device_t tmpd; - - if(device_get_unit(dev)!=ARIZONA_I2C_BUS) { - device_printf(dev, "unused iicbus instance\n"); - return 0; - } - - sc = device_get_softc(dev); - set_i2c_base(dev); - - mtx_init(&sc->sc_mtx, "xlr_i2c", "xlr_i2c", MTX_DEF); - - sc->mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, RF_ACTIVE); - if (sc->mem_res == NULL) { - printf("not able to allocate the bus resource\n"); - } - if ((sc->iicbus = device_add_child(dev, "iicbus", -1)) == NULL) { - printf("could not allocate iicbus instance\n"); - return -1; - } - if(xlr_board_info.xlr_i2c_device[I2C_RTC].enabled == 1) { - tmpd = device_add_child(sc->iicbus, "ds13rtc", 0); - device_set_ivars(tmpd, &xlr_board_info.xlr_i2c_device[I2C_RTC]); - } - if(xlr_board_info.xlr_i2c_device[I2C_THERMAL].enabled == 1) { - tmpd = device_add_child(sc->iicbus, "max6657", 0); - device_set_ivars(tmpd, &xlr_board_info.xlr_i2c_device[I2C_THERMAL]); - } - if(xlr_board_info.xlr_i2c_device[I2C_EEPROM].enabled == 1) { - tmpd = device_add_child(sc->iicbus, "at24co2n", 0); - device_set_ivars(tmpd, &xlr_board_info.xlr_i2c_device[I2C_EEPROM]); - } - - /* - * The old ds1374 rtc driver only handled one chip type. The new - * ds13rtc driver handles all ds13xx chips, but must be told the chip - * type via hints. XLR historically hasn't had a standard hints file, - * so set up the hint now if it isn't already there. - */ -#define HINTNAME "hint.ds13rtc.0.compatible" - if (!testenv(HINTNAME)) - kern_setenv(HINTNAME, "dallas,ds1374"); - - bus_generic_attach(dev); - - return (0); -} - -static int -xlr_i2c_detach(device_t dev) -{ - bus_generic_detach(dev); - - return (0); -} - -static int -xlr_i2c_start(device_t dev, u_char slave, int timeout) -{ - int error = 0; - struct xlr_i2c_softc *sc; - - sc = device_get_softc(dev); - mtx_lock(&sc->sc_mtx); - sc->sc_started = 1; - sc->i2cdev_addr = (slave >> 1); - return error; - -} - -static int -xlr_i2c_stop(device_t dev) -{ - int error = 0; - struct xlr_i2c_softc *sc; - - sc = device_get_softc(dev); - mtx_unlock(&sc->sc_mtx); - return error; - -} - -static int -xlr_i2c_read(device_t dev, char *buf, int len, int *read, int last, - int delay) -{ - volatile uint32_t i2c_status = 0; - int pos=0; - int timeout = 0; - - xlr_i2c_dev_write(dev, XLR_I2C_CFG, XLR_I2C_CFG_NOADDR); - xlr_i2c_dev_write(dev, XLR_I2C_BYTECNT, len); - -retry: - xlr_i2c_dev_write(dev, XLR_I2C_STARTXFR, XLR_I2C_STARTXFR_RD); - - timeout = 0; - while(1) { - if(timeout++ > MAXTIME) - return -1; - - i2c_status = xlr_i2c_dev_read(dev, XLR_I2C_STATUS); - if (i2c_status & XLR_I2C_RXRDY) - buf[pos++] = (uint8_t) xlr_i2c_dev_read(dev, XLR_I2C_DATAIN); - - /* ACKERR -- bail */ - if (i2c_status & XLR_I2C_ACK_ERR) - return -1; /* ACK_ERROR */ - - /* LOST ARB or STARTERR -- repeat */ - if (i2c_status & XLR_I2C_ARB_STARTERR) - goto retry; - - /* Wait for busy bit to go away */ - if (i2c_status & XLR_I2C_BUS_BUSY) - continue; - - if (pos == len) - break; - } - *read = pos; - return 0; - -} - -static int -xlr_i2c_write(device_t dev, const char *buf, int len, int *sent, int timeout /* us */ ) -{ - volatile uint32_t i2c_status = 0x00; - uint8_t devaddr, addr; - struct xlr_i2c_softc *sc; - int pos; - - sc = device_get_softc(dev); - - /* the first byte of write is addr (of register in device) */ - addr = buf[0]; - devaddr = sc->i2cdev_addr; - xlr_i2c_dev_write(dev, XLR_I2C_ADDR, addr); - xlr_i2c_dev_write(dev, XLR_I2C_DEVADDR, devaddr); - xlr_i2c_dev_write(dev, XLR_I2C_CFG, XLR_I2C_CFG_ADDR); - xlr_i2c_dev_write(dev, XLR_I2C_BYTECNT, len - 1); - -retry: - pos = 1; - if (len == 1) /* there is no data only address */ - xlr_i2c_dev_write(dev, XLR_I2C_STARTXFR, XLR_I2C_STARTXFR_ND); - else { - xlr_i2c_dev_write(dev, XLR_I2C_STARTXFR, XLR_I2C_STARTXFR_WR); - xlr_i2c_dev_write(dev, XLR_I2C_DATAOUT, buf[pos]); - } - - while (1) { - i2c_status = xlr_i2c_dev_read(dev, XLR_I2C_STATUS); - - /* sdo empty send next byte */ - if (i2c_status & XLR_I2C_SDOEMPTY) { - pos++; - xlr_i2c_dev_write(dev, XLR_I2C_DATAOUT, buf[pos]); - } - - /* LOST ARB or STARTERR -- repeat */ - if (i2c_status & XLR_I2C_ARB_STARTERR) - goto retry; - - /* ACKERR -- bail */ - if (i2c_status & XLR_I2C_ACK_ERR) { - printf("ACK ERR : exiting\n "); - return -1; - } - - /* busy try again */ - if (i2c_status & XLR_I2C_BUS_BUSY) - continue; - - if (pos >= len) - break; - } - *sent = len - 1; - return 0; -} - - - -static int -xlr_i2c_callback(device_t dev, int index, caddr_t data) -{ - return 0; -} - -static int -xlr_i2c_repeated_start(device_t dev, u_char slave, int timeout) -{ - return 0; -} - -/* - * I2C bus transfer for RMI boards and devices. - * Generic version of iicbus_transfer that calls the appropriate - * routines to accomplish this. See note above about acceptable - * buffer addresses. - */ -int -xlr_i2c_transfer(device_t bus, struct iic_msg *msgs, uint32_t nmsgs) -{ - int i, error, lenread, lenwrote; - u_char addr; - - addr = msgs[0].slave | LSB; - error = xlr_i2c_start(bus, addr, 0); - for (i = 0, error = 0; i < nmsgs && error == 0; i++) { - if (msgs[i].flags & IIC_M_RD) { - error = xlr_i2c_read((bus), msgs[i].buf, msgs[i].len, &lenread, IIC_LAST_READ, 0); - } - else { - error = xlr_i2c_write((bus), msgs[i].buf, msgs[i].len, &lenwrote, 0); - } - } - error = xlr_i2c_stop(bus); - return (error); -} - - -static device_method_t xlr_i2c_methods[] = { - /* device interface */ - DEVMETHOD(device_probe, xlr_i2c_probe), - DEVMETHOD(device_attach, xlr_i2c_attach), - DEVMETHOD(device_detach, xlr_i2c_detach), - - /* iicbus interface */ - DEVMETHOD(iicbus_callback, xlr_i2c_callback), - DEVMETHOD(iicbus_repeated_start, xlr_i2c_repeated_start), - DEVMETHOD(iicbus_start, xlr_i2c_start), - DEVMETHOD(iicbus_stop, xlr_i2c_stop), - DEVMETHOD(iicbus_write, xlr_i2c_write), - DEVMETHOD(iicbus_read, xlr_i2c_read), - DEVMETHOD(iicbus_transfer, xlr_i2c_transfer), - {0, 0} -}; - -static driver_t xlr_i2c_driver = { - "xlr_i2c", - xlr_i2c_methods, - sizeof(struct xlr_i2c_softc), -}; - -DRIVER_MODULE(xlr_i2c, iodi, xlr_i2c_driver, xlr_i2c_devclass, 0, 0); -DRIVER_MODULE(iicbus, xlr_i2c, iicbus_driver, iicbus_devclass, 0, 0); Property changes on: head/sys/mips/rmi/xlr_i2c.c ___________________________________________________________________ Deleted: svn:eol-style ## -1 +0,0 ## -native \ No newline at end of property Deleted: svn:keywords ## -1 +0,0 ## -FreeBSD=%H \ No newline at end of property Deleted: svn:mime-type ## -1 +0,0 ## -text/plain \ No newline at end of property Index: head/sys/mips/rmi/bus_space_rmi.c =================================================================== --- head/sys/mips/rmi/bus_space_rmi.c (revision 327460) +++ head/sys/mips/rmi/bus_space_rmi.c (nonexistent) @@ -1,688 +0,0 @@ -/*- - * SPDX-License-Identifier: BSD-2-Clause-FreeBSD - * - * Copyright (c) 2009 RMI Corporation - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - * - * $FreeBSD$ - */ -#include -__FBSDID("$FreeBSD$"); - -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include - -#include -#include - -static int -rmi_bus_space_map(void *t, bus_addr_t addr, - bus_size_t size, int flags, - bus_space_handle_t * bshp); - -static void -rmi_bus_space_unmap(void *t, bus_space_handle_t bsh, - bus_size_t size); - -static int -rmi_bus_space_subregion(void *t, - bus_space_handle_t bsh, - bus_size_t offset, bus_size_t size, - bus_space_handle_t * nbshp); - -static u_int8_t -rmi_bus_space_read_1(void *t, - bus_space_handle_t handle, - bus_size_t offset); - -static u_int16_t -rmi_bus_space_read_2(void *t, - bus_space_handle_t handle, - bus_size_t offset); - -static u_int32_t -rmi_bus_space_read_4(void *t, - bus_space_handle_t handle, - bus_size_t offset); - -static void -rmi_bus_space_read_multi_1(void *t, - bus_space_handle_t handle, - bus_size_t offset, u_int8_t * addr, - size_t count); - -static void -rmi_bus_space_read_multi_2(void *t, - bus_space_handle_t handle, - bus_size_t offset, u_int16_t * addr, - size_t count); - -static void -rmi_bus_space_read_multi_4(void *t, - bus_space_handle_t handle, - bus_size_t offset, u_int32_t * addr, - size_t count); - -static void -rmi_bus_space_read_region_1(void *t, - bus_space_handle_t bsh, - bus_size_t offset, u_int8_t * addr, - size_t count); - -static void -rmi_bus_space_read_region_2(void *t, - bus_space_handle_t bsh, - bus_size_t offset, u_int16_t * addr, - size_t count); - -static void -rmi_bus_space_read_region_4(void *t, - bus_space_handle_t bsh, - bus_size_t offset, u_int32_t * addr, - size_t count); - -static void -rmi_bus_space_write_1(void *t, - bus_space_handle_t handle, - bus_size_t offset, u_int8_t value); - -static void -rmi_bus_space_write_2(void *t, - bus_space_handle_t handle, - bus_size_t offset, u_int16_t value); - -static void -rmi_bus_space_write_4(void *t, - bus_space_handle_t handle, - bus_size_t offset, u_int32_t value); - -static void -rmi_bus_space_write_multi_1(void *t, - bus_space_handle_t handle, - bus_size_t offset, - const u_int8_t * addr, - size_t count); - -static void -rmi_bus_space_write_multi_2(void *t, - bus_space_handle_t handle, - bus_size_t offset, - const u_int16_t * addr, - size_t count); - -static void -rmi_bus_space_write_multi_4(void *t, - bus_space_handle_t handle, - bus_size_t offset, - const u_int32_t * addr, - size_t count); - -static void -rmi_bus_space_write_region_2(void *t, - bus_space_handle_t bsh, - bus_size_t offset, - const u_int16_t * addr, - size_t count); - -static void -rmi_bus_space_write_region_4(void *t, - bus_space_handle_t bsh, - bus_size_t offset, - const u_int32_t * addr, - size_t count); - - -static void -rmi_bus_space_set_region_2(void *t, - bus_space_handle_t bsh, - bus_size_t offset, u_int16_t value, - size_t count); -static void -rmi_bus_space_set_region_4(void *t, - bus_space_handle_t bsh, - bus_size_t offset, u_int32_t value, - size_t count); - -static void -rmi_bus_space_barrier(void *tag __unused, bus_space_handle_t bsh __unused, - bus_size_t offset __unused, bus_size_t len __unused, int flags); - -static void -rmi_bus_space_copy_region_2(void *t, - bus_space_handle_t bsh1, - bus_size_t off1, - bus_space_handle_t bsh2, - bus_size_t off2, size_t count); - -u_int8_t -rmi_bus_space_read_stream_1(void *t, bus_space_handle_t handle, - bus_size_t offset); - -static u_int16_t -rmi_bus_space_read_stream_2(void *t, bus_space_handle_t handle, - bus_size_t offset); - -static u_int32_t -rmi_bus_space_read_stream_4(void *t, bus_space_handle_t handle, - bus_size_t offset); -static void -rmi_bus_space_read_multi_stream_1(void *t, - bus_space_handle_t handle, - bus_size_t offset, u_int8_t * addr, - size_t count); - -static void -rmi_bus_space_read_multi_stream_2(void *t, - bus_space_handle_t handle, - bus_size_t offset, u_int16_t * addr, - size_t count); - -static void -rmi_bus_space_read_multi_stream_4(void *t, - bus_space_handle_t handle, - bus_size_t offset, u_int32_t * addr, - size_t count); - -void -rmi_bus_space_write_stream_1(void *t, bus_space_handle_t bsh, - bus_size_t offset, u_int8_t value); -static void -rmi_bus_space_write_stream_2(void *t, bus_space_handle_t handle, - bus_size_t offset, u_int16_t value); - -static void -rmi_bus_space_write_stream_4(void *t, bus_space_handle_t handle, - bus_size_t offset, u_int32_t value); - -static void -rmi_bus_space_write_multi_stream_1(void *t, - bus_space_handle_t handle, - bus_size_t offset, - const u_int8_t * addr, - size_t count); -static void -rmi_bus_space_write_multi_stream_2(void *t, - bus_space_handle_t handle, - bus_size_t offset, - const u_int16_t * addr, - size_t count); - -static void -rmi_bus_space_write_multi_stream_4(void *t, - bus_space_handle_t handle, - bus_size_t offset, - const u_int32_t * addr, - size_t count); - -#define TODO() printf("XLR memory bus space function '%s' unimplemented\n", __func__) - -static struct bus_space local_rmi_bus_space = { - /* cookie */ - (void *)0, - - /* mapping/unmapping */ - rmi_bus_space_map, - rmi_bus_space_unmap, - rmi_bus_space_subregion, - - /* allocation/deallocation */ - NULL, - NULL, - - /* barrier */ - rmi_bus_space_barrier, - - /* read (single) */ - rmi_bus_space_read_1, - rmi_bus_space_read_2, - rmi_bus_space_read_4, - NULL, - - /* read multiple */ - rmi_bus_space_read_multi_1, - rmi_bus_space_read_multi_2, - rmi_bus_space_read_multi_4, - NULL, - - /* read region */ - rmi_bus_space_read_region_1, - rmi_bus_space_read_region_2, - rmi_bus_space_read_region_4, - NULL, - - /* write (single) */ - rmi_bus_space_write_1, - rmi_bus_space_write_2, - rmi_bus_space_write_4, - NULL, - - /* write multiple */ - rmi_bus_space_write_multi_1, - rmi_bus_space_write_multi_2, - rmi_bus_space_write_multi_4, - NULL, - - /* write region */ - NULL, - rmi_bus_space_write_region_2, - rmi_bus_space_write_region_4, - NULL, - - /* set multiple */ - NULL, - NULL, - NULL, - NULL, - - /* set region */ - NULL, - rmi_bus_space_set_region_2, - rmi_bus_space_set_region_4, - NULL, - - /* copy */ - NULL, - rmi_bus_space_copy_region_2, - NULL, - NULL, - - /* read (single) stream */ - rmi_bus_space_read_stream_1, - rmi_bus_space_read_stream_2, - rmi_bus_space_read_stream_4, - NULL, - - /* read multiple stream */ - rmi_bus_space_read_multi_stream_1, - rmi_bus_space_read_multi_stream_2, - rmi_bus_space_read_multi_stream_4, - NULL, - - /* read region stream */ - rmi_bus_space_read_region_1, - rmi_bus_space_read_region_2, - rmi_bus_space_read_region_4, - NULL, - - /* write (single) stream */ - rmi_bus_space_write_stream_1, - rmi_bus_space_write_stream_2, - rmi_bus_space_write_stream_4, - NULL, - - /* write multiple stream */ - rmi_bus_space_write_multi_stream_1, - rmi_bus_space_write_multi_stream_2, - rmi_bus_space_write_multi_stream_4, - NULL, - - /* write region stream */ - NULL, - rmi_bus_space_write_region_2, - rmi_bus_space_write_region_4, - NULL, -}; - -/* generic bus_space tag */ -bus_space_tag_t rmi_bus_space = &local_rmi_bus_space; - -/* - * Map a region of device bus space into CPU virtual address space. - */ -static int -rmi_bus_space_map(void *t __unused, bus_addr_t addr, - bus_size_t size __unused, int flags __unused, - bus_space_handle_t * bshp) -{ - - *bshp = addr; - return (0); -} - -/* - * Unmap a region of device bus space. - */ -static void -rmi_bus_space_unmap(void *t __unused, bus_space_handle_t bsh __unused, - bus_size_t size __unused) -{ -} - -/* - * Get a new handle for a subregion of an already-mapped area of bus space. - */ - -static int -rmi_bus_space_subregion(void *t __unused, bus_space_handle_t bsh, - bus_size_t offset, bus_size_t size __unused, - bus_space_handle_t * nbshp) -{ - *nbshp = bsh + offset; - return (0); -} - -/* - * Read a 1, 2, 4, or 8 byte quantity from bus space - * described by tag/handle/offset. - */ - -static u_int8_t -rmi_bus_space_read_1(void *tag, bus_space_handle_t handle, - bus_size_t offset) -{ - return (u_int8_t) (*(volatile u_int32_t *)(handle + offset)); -} - -static u_int16_t -rmi_bus_space_read_2(void *tag, bus_space_handle_t handle, - bus_size_t offset) -{ - return (u_int16_t)(*(volatile u_int32_t *)(handle + offset)); -} - -static u_int32_t -rmi_bus_space_read_4(void *tag, bus_space_handle_t handle, - bus_size_t offset) -{ - return (*(volatile u_int32_t *)(handle + offset)); -} - - -/* - * Read `count' 1, 2, 4, or 8 byte quantities from bus space - * described by tag/handle/offset and copy into buffer provided. - */ -static void -rmi_bus_space_read_multi_1(void *tag, bus_space_handle_t handle, - bus_size_t offset, u_int8_t * addr, size_t count) -{ - TODO(); -} - -static void -rmi_bus_space_read_multi_2(void *tag, bus_space_handle_t handle, - bus_size_t offset, u_int16_t * addr, size_t count) -{ - TODO(); -} - -static void -rmi_bus_space_read_multi_4(void *tag, bus_space_handle_t handle, - bus_size_t offset, u_int32_t * addr, size_t count) -{ - TODO(); -} - -/* - * Write the 1, 2, 4, or 8 byte value `value' to bus space - * described by tag/handle/offset. - */ - -static void -rmi_bus_space_write_1(void *tag, bus_space_handle_t handle, - bus_size_t offset, u_int8_t value) -{ - *(volatile u_int32_t *)(handle + offset) = (u_int32_t)value; -} - -static void -rmi_bus_space_write_2(void *tag, bus_space_handle_t handle, - bus_size_t offset, u_int16_t value) -{ - *(volatile u_int32_t *)(handle + offset) = (u_int32_t)value; -} - -static void -rmi_bus_space_write_4(void *tag, bus_space_handle_t handle, - bus_size_t offset, u_int32_t value) -{ - *(volatile u_int32_t *)(handle + offset) = value; -} - - -/* - * Write `count' 1, 2, 4, or 8 byte quantities from the buffer - * provided to bus space described by tag/handle/offset. - */ - - -static void -rmi_bus_space_write_multi_1(void *tag, bus_space_handle_t handle, - bus_size_t offset, const u_int8_t * addr, size_t count) -{ - TODO(); -} - -static void -rmi_bus_space_write_multi_2(void *tag, bus_space_handle_t handle, - bus_size_t offset, const u_int16_t * addr, size_t count) -{ - TODO(); -} - -static void -rmi_bus_space_write_multi_4(void *tag, bus_space_handle_t handle, - bus_size_t offset, const u_int32_t * addr, size_t count) -{ - TODO(); -} - -/* - * Write `count' 1, 2, 4, or 8 byte value `val' to bus space described - * by tag/handle starting at `offset'. - */ - -static void -rmi_bus_space_set_region_2(void *t, bus_space_handle_t bsh, - bus_size_t offset, u_int16_t value, size_t count) -{ - bus_addr_t addr = bsh + offset; - - for (; count != 0; count--, addr += 2) - (*(volatile u_int32_t *)(addr)) = value; -} - -static void -rmi_bus_space_set_region_4(void *t, bus_space_handle_t bsh, - bus_size_t offset, u_int32_t value, size_t count) -{ - bus_addr_t addr = bsh + offset; - - for (; count != 0; count--, addr += 4) - (*(volatile u_int32_t *)(addr)) = value; -} - - -/* - * Copy `count' 1, 2, 4, or 8 byte values from bus space starting - * at tag/bsh1/off1 to bus space starting at tag/bsh2/off2. - */ -static void -rmi_bus_space_copy_region_2(void *t, bus_space_handle_t bsh1, - bus_size_t off1, bus_space_handle_t bsh2, - bus_size_t off2, size_t count) -{ - printf("bus_space_copy_region_2 - unimplemented\n"); -} - -/* - * Read `count' 1, 2, 4, or 8 byte quantities from bus space - * described by tag/handle/offset and copy into buffer provided. - */ - -u_int8_t -rmi_bus_space_read_stream_1(void *t, bus_space_handle_t handle, - bus_size_t offset) -{ - - return *((volatile u_int8_t *)(handle + offset)); -} - - -static u_int16_t -rmi_bus_space_read_stream_2(void *t, bus_space_handle_t handle, - bus_size_t offset) -{ - return *(volatile u_int16_t *)(handle + offset); -} - - -static u_int32_t -rmi_bus_space_read_stream_4(void *t, bus_space_handle_t handle, - bus_size_t offset) -{ - return (*(volatile u_int32_t *)(handle + offset)); -} - - -static void -rmi_bus_space_read_multi_stream_1(void *tag, bus_space_handle_t handle, - bus_size_t offset, u_int8_t * addr, size_t count) -{ - TODO(); -} - -static void -rmi_bus_space_read_multi_stream_2(void *tag, bus_space_handle_t handle, - bus_size_t offset, u_int16_t * addr, size_t count) -{ - TODO(); -} - -static void -rmi_bus_space_read_multi_stream_4(void *tag, bus_space_handle_t handle, - bus_size_t offset, u_int32_t * addr, size_t count) -{ - TODO(); -} - - -/* - * Read `count' 1, 2, 4, or 8 byte quantities from bus space - * described by tag/handle and starting at `offset' and copy into - * buffer provided. - */ -void -rmi_bus_space_read_region_1(void *t, bus_space_handle_t bsh, - bus_size_t offset, u_int8_t * addr, size_t count) -{ - TODO(); -} - -void -rmi_bus_space_read_region_2(void *t, bus_space_handle_t bsh, - bus_size_t offset, u_int16_t * addr, size_t count) -{ - TODO(); -} - -void -rmi_bus_space_read_region_4(void *t, bus_space_handle_t bsh, - bus_size_t offset, u_int32_t * addr, size_t count) -{ - bus_addr_t baddr = bsh + offset; - - while (count--) { - *addr++ = (*(volatile u_int32_t *)(baddr)); - baddr += 4; - } -} - -void -rmi_bus_space_write_stream_1(void *t, bus_space_handle_t handle, - bus_size_t offset, u_int8_t value) -{ - TODO(); -} - - -static void -rmi_bus_space_write_stream_2(void *t, bus_space_handle_t handle, - bus_size_t offset, u_int16_t value) -{ - TODO(); -} - - -static void -rmi_bus_space_write_stream_4(void *t, bus_space_handle_t handle, - bus_size_t offset, u_int32_t value) -{ - TODO(); -} - - -static void -rmi_bus_space_write_multi_stream_1(void *tag, bus_space_handle_t handle, - bus_size_t offset, const u_int8_t * addr, size_t count) -{ - TODO(); -} - -static void -rmi_bus_space_write_multi_stream_2(void *tag, bus_space_handle_t handle, - bus_size_t offset, const u_int16_t * addr, size_t count) -{ - TODO(); -} - -static void -rmi_bus_space_write_multi_stream_4(void *tag, bus_space_handle_t handle, - bus_size_t offset, const u_int32_t * addr, size_t count) -{ - TODO(); -} - -void -rmi_bus_space_write_region_2(void *t, - bus_space_handle_t bsh, - bus_size_t offset, - const u_int16_t * addr, - size_t count) -{ - TODO(); -} - -void -rmi_bus_space_write_region_4(void *t, bus_space_handle_t bsh, - bus_size_t offset, const u_int32_t * addr, size_t count) -{ - TODO(); -} - -static void -rmi_bus_space_barrier(void *tag __unused, bus_space_handle_t bsh __unused, - bus_size_t offset __unused, bus_size_t len __unused, int flags) -{ -} Property changes on: head/sys/mips/rmi/bus_space_rmi.c ___________________________________________________________________ Deleted: svn:eol-style ## -1 +0,0 ## -native \ No newline at end of property Deleted: svn:keywords ## -1 +0,0 ## -FreeBSD=%H \ No newline at end of property Deleted: svn:mime-type ## -1 +0,0 ## -text/plain \ No newline at end of property Index: head/sys/mips/rmi/xlr_pcmcia.c =================================================================== --- head/sys/mips/rmi/xlr_pcmcia.c (revision 327460) +++ head/sys/mips/rmi/xlr_pcmcia.c (nonexistent) @@ -1,151 +0,0 @@ -/*- - * SPDX-License-Identifier: BSD-3-Clause - * - * Copyright (c) 2003-2009 RMI Corporation - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. Neither the name of RMI Corporation, nor the names of its contributors, - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - * - * RMI_BSD */ -/* - * ATA driver for the XLR_PCMCIA Host adapter on the RMI XLR/XLS/. - */ -#include -__FBSDID("$FreeBSD$"); - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include -#include - -#define XLR_PCMCIA_DATA_REG 0x1f0 -#define XLR_PCMCIA_ERROR_REG 0x1f1 -#define XLR_PCMCIA_SECT_CNT_REG 0x1f2 -#define XLR_PCMCIA_SECT_NUM_REG 0x1f3 -#define XLR_PCMCIA_CYLINDER_LOW_REG 0x1f4 -#define XLR_PCMCIA_CYLINDER_HIGH_REG 0x1f5 -#define XLR_PCMCIA_SECT_DRIVE_HEAD_REG 0x1f6 -#define XLR_PCMCIA_CMD_STATUS_REG 0x1f7 -#define XLR_PCMCIA_ALT_STATUS_REG 0x3f6 -#define XLR_PCMCIA_CONTROL_REG 0x3f6 - -/* - * Device methods - */ -static int xlr_pcmcia_probe(device_t); -static int xlr_pcmcia_attach(device_t); -static int xlr_pcmcia_detach(device_t); - -static int -xlr_pcmcia_probe(device_t dev) -{ - struct ata_channel *ch = device_get_softc(dev); - - ch->unit = 0; - ch->flags |= ATA_USE_16BIT | ATA_NO_SLAVE ; - device_set_desc(dev, "PCMCIA ATA controller"); - - return (ata_probe(dev)); -} - -/* - * We add all the devices which we know about. - * The generic attach routine will attach them if they are alive. - */ -static int -xlr_pcmcia_attach(device_t dev) -{ - struct ata_channel *ch = device_get_softc(dev); - int i; - int rid =0; - struct resource *mem_res; - - - mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, RF_ACTIVE); - for (i = 0; i < ATA_MAX_RES; i++) - ch->r_io[i].res = mem_res; - - /* - * CF+ Specification. - */ - ch->r_io[ATA_DATA].offset = XLR_PCMCIA_DATA_REG; - ch->r_io[ATA_FEATURE].offset = XLR_PCMCIA_ERROR_REG; - ch->r_io[ATA_COUNT].offset = XLR_PCMCIA_SECT_CNT_REG; - ch->r_io[ATA_SECTOR].offset = XLR_PCMCIA_SECT_NUM_REG; - ch->r_io[ATA_CYL_LSB].offset = XLR_PCMCIA_CYLINDER_LOW_REG; - ch->r_io[ATA_CYL_MSB].offset = XLR_PCMCIA_CYLINDER_HIGH_REG; - ch->r_io[ATA_DRIVE].offset = XLR_PCMCIA_SECT_DRIVE_HEAD_REG; - ch->r_io[ATA_COMMAND].offset = XLR_PCMCIA_CMD_STATUS_REG; - ch->r_io[ATA_ERROR].offset = XLR_PCMCIA_ERROR_REG; - ch->r_io[ATA_IREASON].offset = XLR_PCMCIA_SECT_CNT_REG; - ch->r_io[ATA_STATUS].offset = XLR_PCMCIA_CMD_STATUS_REG; - ch->r_io[ATA_ALTSTAT].offset = XLR_PCMCIA_ALT_STATUS_REG; - ch->r_io[ATA_CONTROL].offset = XLR_PCMCIA_CONTROL_REG; - - /* Should point at the base of registers. */ - ch->r_io[ATA_IDX_ADDR].offset = XLR_PCMCIA_DATA_REG; - - ata_generic_hw(dev); - - return (ata_attach(dev)); -} - -static int -xlr_pcmcia_detach(device_t dev) -{ - bus_generic_detach(dev); - - return (0); -} - -static device_method_t xlr_pcmcia_methods[] = { - /* device interface */ - DEVMETHOD(device_probe, xlr_pcmcia_probe), - DEVMETHOD(device_attach, xlr_pcmcia_attach), - DEVMETHOD(device_detach, xlr_pcmcia_detach), - - { 0, 0 } -}; - -static driver_t xlr_pcmcia_driver = { - "ata", - xlr_pcmcia_methods, - sizeof(struct ata_channel), -}; - -DRIVER_MODULE(ata, iodi, xlr_pcmcia_driver, ata_devclass, 0, 0); Property changes on: head/sys/mips/rmi/xlr_pcmcia.c ___________________________________________________________________ Deleted: svn:eol-style ## -1 +0,0 ## -native \ No newline at end of property Deleted: svn:keywords ## -1 +0,0 ## -FreeBSD=%H \ No newline at end of property Deleted: svn:mime-type ## -1 +0,0 ## -text/plain \ No newline at end of property Index: head/sys/mips/rmi/bus_space_rmi_pci.c =================================================================== --- head/sys/mips/rmi/bus_space_rmi_pci.c (revision 327460) +++ head/sys/mips/rmi/bus_space_rmi_pci.c (nonexistent) @@ -1,763 +0,0 @@ -/*- - * SPDX-License-Identifier: BSD-2-Clause-FreeBSD - * - * Copyright (c) 2009 RMI Corporation - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - * - * $FreeBSD$ - */ -#include -__FBSDID("$FreeBSD$"); - -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include - -#include -#include - -static int -rmi_pci_bus_space_map(void *t, bus_addr_t addr, - bus_size_t size, int flags, - bus_space_handle_t * bshp); - -static void -rmi_pci_bus_space_unmap(void *t, bus_space_handle_t bsh, - bus_size_t size); - -static int -rmi_pci_bus_space_subregion(void *t, - bus_space_handle_t bsh, - bus_size_t offset, bus_size_t size, - bus_space_handle_t * nbshp); - -static u_int8_t -rmi_pci_bus_space_read_1(void *t, - bus_space_handle_t handle, - bus_size_t offset); - -static u_int16_t -rmi_pci_bus_space_read_2(void *t, - bus_space_handle_t handle, - bus_size_t offset); - -static u_int32_t -rmi_pci_bus_space_read_4(void *t, - bus_space_handle_t handle, - bus_size_t offset); - -static void -rmi_pci_bus_space_read_multi_1(void *t, - bus_space_handle_t handle, - bus_size_t offset, u_int8_t * addr, - size_t count); - -static void -rmi_pci_bus_space_read_multi_2(void *t, - bus_space_handle_t handle, - bus_size_t offset, u_int16_t * addr, - size_t count); - -static void -rmi_pci_bus_space_read_multi_4(void *t, - bus_space_handle_t handle, - bus_size_t offset, u_int32_t * addr, - size_t count); - -static void -rmi_pci_bus_space_read_region_1(void *t, - bus_space_handle_t bsh, - bus_size_t offset, u_int8_t * addr, - size_t count); - -static void -rmi_pci_bus_space_read_region_2(void *t, - bus_space_handle_t bsh, - bus_size_t offset, u_int16_t * addr, - size_t count); - -static void -rmi_pci_bus_space_read_region_4(void *t, - bus_space_handle_t bsh, - bus_size_t offset, u_int32_t * addr, - size_t count); - -static void -rmi_pci_bus_space_write_1(void *t, - bus_space_handle_t handle, - bus_size_t offset, u_int8_t value); - -static void -rmi_pci_bus_space_write_2(void *t, - bus_space_handle_t handle, - bus_size_t offset, u_int16_t value); - -static void -rmi_pci_bus_space_write_4(void *t, - bus_space_handle_t handle, - bus_size_t offset, u_int32_t value); - -static void -rmi_pci_bus_space_write_multi_1(void *t, - bus_space_handle_t handle, - bus_size_t offset, - const u_int8_t * addr, - size_t count); - -static void -rmi_pci_bus_space_write_multi_2(void *t, - bus_space_handle_t handle, - bus_size_t offset, - const u_int16_t * addr, - size_t count); - -static void -rmi_pci_bus_space_write_multi_4(void *t, - bus_space_handle_t handle, - bus_size_t offset, - const u_int32_t * addr, - size_t count); - -static void -rmi_pci_bus_space_write_region_2(void *t, - bus_space_handle_t bsh, - bus_size_t offset, - const u_int16_t * addr, - size_t count); - -static void -rmi_pci_bus_space_write_region_4(void *t, - bus_space_handle_t bsh, - bus_size_t offset, - const u_int32_t * addr, - size_t count); - - -static void -rmi_pci_bus_space_set_region_2(void *t, - bus_space_handle_t bsh, - bus_size_t offset, u_int16_t value, - size_t count); -static void -rmi_pci_bus_space_set_region_4(void *t, - bus_space_handle_t bsh, - bus_size_t offset, u_int32_t value, - size_t count); - -static void -rmi_pci_bus_space_barrier(void *tag __unused, bus_space_handle_t bsh __unused, - bus_size_t offset __unused, bus_size_t len __unused, int flags); - -static void -rmi_pci_bus_space_copy_region_2(void *t, - bus_space_handle_t bsh1, - bus_size_t off1, - bus_space_handle_t bsh2, - bus_size_t off2, size_t count); - -u_int8_t -rmi_pci_bus_space_read_stream_1(void *t, bus_space_handle_t handle, - bus_size_t offset); - -static u_int16_t -rmi_pci_bus_space_read_stream_2(void *t, bus_space_handle_t handle, - bus_size_t offset); - -static u_int32_t -rmi_pci_bus_space_read_stream_4(void *t, bus_space_handle_t handle, - bus_size_t offset); -static void -rmi_pci_bus_space_read_multi_stream_1(void *t, - bus_space_handle_t handle, - bus_size_t offset, u_int8_t * addr, - size_t count); - -static void -rmi_pci_bus_space_read_multi_stream_2(void *t, - bus_space_handle_t handle, - bus_size_t offset, u_int16_t * addr, - size_t count); - -static void -rmi_pci_bus_space_read_multi_stream_4(void *t, - bus_space_handle_t handle, - bus_size_t offset, u_int32_t * addr, - size_t count); - -void -rmi_pci_bus_space_write_stream_1(void *t, bus_space_handle_t bsh, - bus_size_t offset, u_int8_t value); -static void -rmi_pci_bus_space_write_stream_2(void *t, bus_space_handle_t handle, - bus_size_t offset, u_int16_t value); - -static void -rmi_pci_bus_space_write_stream_4(void *t, bus_space_handle_t handle, - bus_size_t offset, u_int32_t value); - -static void -rmi_pci_bus_space_write_multi_stream_1(void *t, - bus_space_handle_t handle, - bus_size_t offset, - const u_int8_t * addr, - size_t count); -static void -rmi_pci_bus_space_write_multi_stream_2(void *t, - bus_space_handle_t handle, - bus_size_t offset, - const u_int16_t * addr, - size_t count); - -static void -rmi_pci_bus_space_write_multi_stream_4(void *t, - bus_space_handle_t handle, - bus_size_t offset, - const u_int32_t * addr, - size_t count); - -#define TODO() printf("XLR memory bus space function '%s' unimplemented\n", __func__) - -static struct bus_space local_rmi_pci_bus_space = { - /* cookie */ - (void *)0, - - /* mapping/unmapping */ - rmi_pci_bus_space_map, - rmi_pci_bus_space_unmap, - rmi_pci_bus_space_subregion, - - /* allocation/deallocation */ - NULL, - NULL, - - /* barrier */ - rmi_pci_bus_space_barrier, - - /* read (single) */ - rmi_pci_bus_space_read_1, - rmi_pci_bus_space_read_2, - rmi_pci_bus_space_read_4, - NULL, - - /* read multiple */ - rmi_pci_bus_space_read_multi_1, - rmi_pci_bus_space_read_multi_2, - rmi_pci_bus_space_read_multi_4, - NULL, - - /* read region */ - rmi_pci_bus_space_read_region_1, - rmi_pci_bus_space_read_region_2, - rmi_pci_bus_space_read_region_4, - NULL, - - /* write (single) */ - rmi_pci_bus_space_write_1, - rmi_pci_bus_space_write_2, - rmi_pci_bus_space_write_4, - NULL, - - /* write multiple */ - rmi_pci_bus_space_write_multi_1, - rmi_pci_bus_space_write_multi_2, - rmi_pci_bus_space_write_multi_4, - NULL, - - /* write region */ - NULL, - rmi_pci_bus_space_write_region_2, - rmi_pci_bus_space_write_region_4, - NULL, - - /* set multiple */ - NULL, - NULL, - NULL, - NULL, - - /* set region */ - NULL, - rmi_pci_bus_space_set_region_2, - rmi_pci_bus_space_set_region_4, - NULL, - - /* copy */ - NULL, - rmi_pci_bus_space_copy_region_2, - NULL, - NULL, - - /* read (single) stream */ - rmi_pci_bus_space_read_stream_1, - rmi_pci_bus_space_read_stream_2, - rmi_pci_bus_space_read_stream_4, - NULL, - - /* read multiple stream */ - rmi_pci_bus_space_read_multi_stream_1, - rmi_pci_bus_space_read_multi_stream_2, - rmi_pci_bus_space_read_multi_stream_4, - NULL, - - /* read region stream */ - rmi_pci_bus_space_read_region_1, - rmi_pci_bus_space_read_region_2, - rmi_pci_bus_space_read_region_4, - NULL, - - /* write (single) stream */ - rmi_pci_bus_space_write_stream_1, - rmi_pci_bus_space_write_stream_2, - rmi_pci_bus_space_write_stream_4, - NULL, - - /* write multiple stream */ - rmi_pci_bus_space_write_multi_stream_1, - rmi_pci_bus_space_write_multi_stream_2, - rmi_pci_bus_space_write_multi_stream_4, - NULL, - - /* write region stream */ - NULL, - rmi_pci_bus_space_write_region_2, - rmi_pci_bus_space_write_region_4, - NULL, -}; - -/* generic bus_space tag */ -bus_space_tag_t rmi_pci_bus_space = &local_rmi_pci_bus_space; - -/* - * Map a region of device bus space into CPU virtual address space. - */ -static int -rmi_pci_bus_space_map(void *t __unused, bus_addr_t addr, - bus_size_t size __unused, int flags __unused, - bus_space_handle_t * bshp) -{ - *bshp = addr; - return (0); -} - -/* - * Unmap a region of device bus space. - */ -static void -rmi_pci_bus_space_unmap(void *t __unused, bus_space_handle_t bsh __unused, - bus_size_t size __unused) -{ -} - -/* - * Get a new handle for a subregion of an already-mapped area of bus space. - */ - -static int -rmi_pci_bus_space_subregion(void *t __unused, bus_space_handle_t bsh, - bus_size_t offset, bus_size_t size __unused, - bus_space_handle_t * nbshp) -{ - *nbshp = bsh + offset; - return (0); -} - -/* - * Read a 1, 2, 4, or 8 byte quantity from bus space - * described by tag/handle/offset. - */ - -static u_int8_t -rmi_pci_bus_space_read_1(void *tag, bus_space_handle_t handle, - bus_size_t offset) -{ - return (u_int8_t) (*(volatile u_int8_t *)(handle + offset)); -} - -static u_int16_t -rmi_pci_bus_space_read_2(void *tag, bus_space_handle_t handle, - bus_size_t offset) -{ - return bswap16((u_int16_t) (*(volatile u_int16_t *)(handle + offset))); -} - -static u_int32_t -rmi_pci_bus_space_read_4(void *tag, bus_space_handle_t handle, - bus_size_t offset) -{ - return bswap32((*(volatile u_int32_t *)(handle + offset))); -} - - -/* - * Read `count' 1, 2, 4, or 8 byte quantities from bus space - * described by tag/handle/offset and copy into buffer provided. - */ -static void -rmi_pci_bus_space_read_multi_1(void *tag, bus_space_handle_t handle, - bus_size_t offset, u_int8_t * addr, size_t count) -{ - while (count--) { - *addr = (*(volatile u_int8_t *)(handle + offset)); - addr++; - } -} - -static void -rmi_pci_bus_space_read_multi_2(void *tag, bus_space_handle_t handle, - bus_size_t offset, u_int16_t * addr, size_t count) -{ - - while (count--) { - *addr = *(volatile u_int16_t *)(handle + offset); - *addr = bswap16(*addr); - addr++; - } -} - -static void -rmi_pci_bus_space_read_multi_4(void *tag, bus_space_handle_t handle, - bus_size_t offset, u_int32_t * addr, size_t count) -{ - - while (count--) { - *addr = *(volatile u_int32_t *)(handle + offset); - *addr = bswap32(*addr); - addr++; - } -} - -/* - * Write the 1, 2, 4, or 8 byte value `value' to bus space - * described by tag/handle/offset. - */ - -static void -rmi_pci_bus_space_write_1(void *tag, bus_space_handle_t handle, - bus_size_t offset, u_int8_t value) -{ - mips_sync(); - *(volatile u_int8_t *)(handle + offset) = value; -} - -static void -rmi_pci_bus_space_write_2(void *tag, bus_space_handle_t handle, - bus_size_t offset, u_int16_t value) -{ - mips_sync(); - *(volatile u_int16_t *)(handle + offset) = bswap16(value); -} - - -static void -rmi_pci_bus_space_write_4(void *tag, bus_space_handle_t handle, - bus_size_t offset, u_int32_t value) -{ - mips_sync(); - *(volatile u_int32_t *)(handle + offset) = bswap32(value); -} - -/* - * Write `count' 1, 2, 4, or 8 byte quantities from the buffer - * provided to bus space described by tag/handle/offset. - */ - - -static void -rmi_pci_bus_space_write_multi_1(void *tag, bus_space_handle_t handle, - bus_size_t offset, const u_int8_t * addr, size_t count) -{ - mips_sync(); - while (count--) { - (*(volatile u_int8_t *)(handle + offset)) = *addr; - addr++; - } -} - -static void -rmi_pci_bus_space_write_multi_2(void *tag, bus_space_handle_t handle, - bus_size_t offset, const u_int16_t * addr, size_t count) -{ - mips_sync(); - while (count--) { - (*(volatile u_int16_t *)(handle + offset)) = bswap16(*addr); - addr++; - } -} - -static void -rmi_pci_bus_space_write_multi_4(void *tag, bus_space_handle_t handle, - bus_size_t offset, const u_int32_t * addr, size_t count) -{ - mips_sync(); - while (count--) { - (*(volatile u_int32_t *)(handle + offset)) = bswap32(*addr); - addr++; - } -} - -/* - * Write `count' 1, 2, 4, or 8 byte value `val' to bus space described - * by tag/handle starting at `offset'. - */ - -static void -rmi_pci_bus_space_set_region_2(void *t, bus_space_handle_t bsh, - bus_size_t offset, u_int16_t value, size_t count) -{ - bus_addr_t addr = bsh + offset; - - for (; count != 0; count--, addr += 2) - (*(volatile u_int16_t *)(addr)) = value; -} - -static void -rmi_pci_bus_space_set_region_4(void *t, bus_space_handle_t bsh, - bus_size_t offset, u_int32_t value, size_t count) -{ - bus_addr_t addr = bsh + offset; - - for (; count != 0; count--, addr += 4) - (*(volatile u_int32_t *)(addr)) = value; -} - - -/* - * Copy `count' 1, 2, 4, or 8 byte values from bus space starting - * at tag/bsh1/off1 to bus space starting at tag/bsh2/off2. - */ -static void -rmi_pci_bus_space_copy_region_2(void *t, bus_space_handle_t bsh1, - bus_size_t off1, bus_space_handle_t bsh2, - bus_size_t off2, size_t count) -{ - TODO(); -} - -/* - * Read `count' 1, 2, 4, or 8 byte quantities from bus space - * described by tag/handle/offset and copy into buffer provided. - */ - -u_int8_t -rmi_pci_bus_space_read_stream_1(void *t, bus_space_handle_t handle, - bus_size_t offset) -{ - - return *((volatile u_int8_t *)(handle + offset)); -} - - -static u_int16_t -rmi_pci_bus_space_read_stream_2(void *t, bus_space_handle_t handle, - bus_size_t offset) -{ - return *(volatile u_int16_t *)(handle + offset); -} - - -static u_int32_t -rmi_pci_bus_space_read_stream_4(void *t, bus_space_handle_t handle, - bus_size_t offset) -{ - return (*(volatile u_int32_t *)(handle + offset)); -} - - -static void -rmi_pci_bus_space_read_multi_stream_1(void *tag, bus_space_handle_t handle, - bus_size_t offset, u_int8_t * addr, size_t count) -{ - while (count--) { - *addr = (*(volatile u_int8_t *)(handle + offset)); - addr++; - } -} - -static void -rmi_pci_bus_space_read_multi_stream_2(void *tag, bus_space_handle_t handle, - bus_size_t offset, u_int16_t * addr, size_t count) -{ - while (count--) { - *addr = (*(volatile u_int16_t *)(handle + offset)); - addr++; - } -} - -static void -rmi_pci_bus_space_read_multi_stream_4(void *tag, bus_space_handle_t handle, - bus_size_t offset, u_int32_t * addr, size_t count) -{ - while (count--) { - *addr = (*(volatile u_int32_t *)(handle + offset)); - addr++; - } -} - - - -/* - * Read `count' 1, 2, 4, or 8 byte quantities from bus space - * described by tag/handle and starting at `offset' and copy into - * buffer provided. - */ -void -rmi_pci_bus_space_read_region_1(void *t, bus_space_handle_t bsh, - bus_size_t offset, u_int8_t * addr, size_t count) -{ - bus_addr_t baddr = bsh + offset; - - while (count--) { - *addr++ = (*(volatile u_int8_t *)(baddr)); - baddr += 1; - } -} - -void -rmi_pci_bus_space_read_region_2(void *t, bus_space_handle_t bsh, - bus_size_t offset, u_int16_t * addr, size_t count) -{ - bus_addr_t baddr = bsh + offset; - - while (count--) { - *addr++ = (*(volatile u_int16_t *)(baddr)); - baddr += 2; - } -} - -void -rmi_pci_bus_space_read_region_4(void *t, bus_space_handle_t bsh, - bus_size_t offset, u_int32_t * addr, size_t count) -{ - bus_addr_t baddr = bsh + offset; - - while (count--) { - *addr++ = (*(volatile u_int32_t *)(baddr)); - baddr += 4; - } -} - - -void -rmi_pci_bus_space_write_stream_1(void *t, bus_space_handle_t handle, - bus_size_t offset, u_int8_t value) -{ - mips_sync(); - *(volatile u_int8_t *)(handle + offset) = value; -} - -static void -rmi_pci_bus_space_write_stream_2(void *t, bus_space_handle_t handle, - bus_size_t offset, u_int16_t value) -{ - mips_sync(); - *(volatile u_int16_t *)(handle + offset) = value; -} - - -static void -rmi_pci_bus_space_write_stream_4(void *t, bus_space_handle_t handle, - bus_size_t offset, u_int32_t value) -{ - mips_sync(); - *(volatile u_int32_t *)(handle + offset) = value; -} - - -static void -rmi_pci_bus_space_write_multi_stream_1(void *tag, bus_space_handle_t handle, - bus_size_t offset, const u_int8_t * addr, size_t count) -{ - mips_sync(); - while (count--) { - (*(volatile u_int8_t *)(handle + offset)) = *addr; - addr++; - } -} - -static void -rmi_pci_bus_space_write_multi_stream_2(void *tag, bus_space_handle_t handle, - bus_size_t offset, const u_int16_t * addr, size_t count) -{ - mips_sync(); - while (count--) { - (*(volatile u_int16_t *)(handle + offset)) = *addr; - addr++; - } -} - -static void -rmi_pci_bus_space_write_multi_stream_4(void *tag, bus_space_handle_t handle, - bus_size_t offset, const u_int32_t * addr, size_t count) -{ - mips_sync(); - while (count--) { - (*(volatile u_int32_t *)(handle + offset)) = *addr; - addr++; - } -} - -void -rmi_pci_bus_space_write_region_2(void *t, - bus_space_handle_t bsh, - bus_size_t offset, - const u_int16_t * addr, - size_t count) -{ - bus_addr_t baddr = (bus_addr_t) bsh + offset; - - while (count--) { - (*(volatile u_int16_t *)(baddr)) = *addr; - addr++; - baddr += 2; - } -} - -void -rmi_pci_bus_space_write_region_4(void *t, bus_space_handle_t bsh, - bus_size_t offset, const u_int32_t * addr, size_t count) -{ - bus_addr_t baddr = bsh + offset; - - while (count--) { - (*(volatile u_int32_t *)(baddr)) = *addr; - addr++; - baddr += 4; - } -} - -static void -rmi_pci_bus_space_barrier(void *tag __unused, bus_space_handle_t bsh __unused, - bus_size_t offset __unused, bus_size_t len __unused, int flags) -{ - -} Property changes on: head/sys/mips/rmi/bus_space_rmi_pci.c ___________________________________________________________________ Deleted: svn:keywords ## -1 +0,0 ## -FreeBSD=%H \ No newline at end of property Index: head/sys/mips/rmi/xlr_pci.c =================================================================== --- head/sys/mips/rmi/xlr_pci.c (revision 327460) +++ head/sys/mips/rmi/xlr_pci.c (nonexistent) @@ -1,659 +0,0 @@ -/*- - * SPDX-License-Identifier: BSD-3-Clause - * - * Copyright (c) 2003-2009 RMI Corporation - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. Neither the name of RMI Corporation, nor the names of its contributors, - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - * - * RMI_BSD */ -#include -__FBSDID("$FreeBSD$"); - -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include - -#include -#include - -#include -#include -#include -#include - -#include -#include -#include -#include -#include -#include - -#include "pcib_if.h" -#include - -#define pci_cfg_offset(bus,slot,devfn,where) (((bus)<<16) + ((slot) << 11)+((devfn)<<8)+(where)) -#define PCIE_LINK_STATE 0x4000 - -#define LSU_CFG0_REGID 0 -#define LSU_CERRLOG_REGID 9 -#define LSU_CERROVF_REGID 10 -#define LSU_CERRINT_REGID 11 - -/* MSI support */ -#define MSI_MIPS_ADDR_DEST 0x000ff000 -#define MSI_MIPS_ADDR_RH 0x00000008 -#define MSI_MIPS_ADDR_RH_OFF 0x00000000 -#define MSI_MIPS_ADDR_RH_ON 0x00000008 -#define MSI_MIPS_ADDR_DM 0x00000004 -#define MSI_MIPS_ADDR_DM_PHYSICAL 0x00000000 -#define MSI_MIPS_ADDR_DM_LOGICAL 0x00000004 - -/* Fields in data for Intel MSI messages. */ -#define MSI_MIPS_DATA_TRGRMOD 0x00008000 /* Trigger mode */ -#define MSI_MIPS_DATA_TRGREDG 0x00000000 /* edge */ -#define MSI_MIPS_DATA_TRGRLVL 0x00008000 /* level */ - -#define MSI_MIPS_DATA_LEVEL 0x00004000 /* Polarity. */ -#define MSI_MIPS_DATA_DEASSERT 0x00000000 -#define MSI_MIPS_DATA_ASSERT 0x00004000 - -#define MSI_MIPS_DATA_DELMOD 0x00000700 /* Delivery Mode */ -#define MSI_MIPS_DATA_DELFIXED 0x00000000 /* fixed */ -#define MSI_MIPS_DATA_DELLOPRI 0x00000100 /* lowest priority */ - -#define MSI_MIPS_DATA_INTVEC 0x000000ff - -/* - * Build Intel MSI message and data values from a source. AMD64 systems - * seem to be compatible, so we use the same function for both. - */ -#define MIPS_MSI_ADDR(cpu) \ - (MSI_MIPS_ADDR_BASE | (cpu) << 12 | \ - MSI_MIPS_ADDR_RH_OFF | MSI_MIPS_ADDR_DM_PHYSICAL) - -#define MIPS_MSI_DATA(irq) \ - (MSI_MIPS_DATA_TRGRLVL | MSI_MIPS_DATA_DELFIXED | \ - MSI_MIPS_DATA_ASSERT | (irq)) - -struct xlr_pcib_softc { - bus_dma_tag_t sc_pci_dmat; /* PCI DMA tag pointer */ -}; - -static devclass_t pcib_devclass; -static void *xlr_pci_config_base; -static struct rman irq_rman, port_rman, mem_rman; - -static void -xlr_pci_init_resources(void) -{ - - irq_rman.rm_start = 0; - irq_rman.rm_end = 255; - irq_rman.rm_type = RMAN_ARRAY; - irq_rman.rm_descr = "PCI Mapped Interrupts"; - if (rman_init(&irq_rman) - || rman_manage_region(&irq_rman, 0, 255)) - panic("pci_init_resources irq_rman"); - - port_rman.rm_type = RMAN_ARRAY; - port_rman.rm_descr = "I/O ports"; - if (rman_init(&port_rman) - || rman_manage_region(&port_rman, 0x10000000, 0x1fffffff)) - panic("pci_init_resources port_rman"); - - mem_rman.rm_type = RMAN_ARRAY; - mem_rman.rm_descr = "I/O memory"; - if (rman_init(&mem_rman) - || rman_manage_region(&mem_rman, 0xd0000000, 0xdfffffff)) - panic("pci_init_resources mem_rman"); -} - -static int -xlr_pcib_probe(device_t dev) -{ - - if (xlr_board_info.is_xls) - device_set_desc(dev, "XLS PCIe bus"); - else - device_set_desc(dev, "XLR PCI bus"); - - xlr_pci_init_resources(); - xlr_pci_config_base = (void *)MIPS_PHYS_TO_KSEG1(DEFAULT_PCI_CONFIG_BASE); - - return (0); -} - -static int -xlr_pcib_read_ivar(device_t dev, device_t child, int which, uintptr_t *result) -{ - - switch (which) { - case PCIB_IVAR_DOMAIN: - *result = 0; - return (0); - case PCIB_IVAR_BUS: - *result = 0; - return (0); - } - return (ENOENT); -} - -static int -xlr_pcib_write_ivar(device_t dev, device_t child, int which, uintptr_t result) -{ - switch (which) { - case PCIB_IVAR_DOMAIN: - return (EINVAL); - case PCIB_IVAR_BUS: - return (EINVAL); - } - return (ENOENT); -} - -static int -xlr_pcib_maxslots(device_t dev) -{ - - return (PCI_SLOTMAX); -} - -static __inline__ void -disable_and_clear_cache_error(void) -{ - uint64_t lsu_cfg0; - - lsu_cfg0 = read_xlr_ctrl_register(CPU_BLOCKID_LSU, LSU_CFG0_REGID); - lsu_cfg0 = lsu_cfg0 & ~0x2e; - write_xlr_ctrl_register(CPU_BLOCKID_LSU, LSU_CFG0_REGID, lsu_cfg0); - /* Clear cache error log */ - write_xlr_ctrl_register(CPU_BLOCKID_LSU, LSU_CERRLOG_REGID, 0); -} - -static __inline__ void -clear_and_enable_cache_error(void) -{ - uint64_t lsu_cfg0 = 0; - - /* first clear the cache error logging register */ - write_xlr_ctrl_register(CPU_BLOCKID_LSU, LSU_CERRLOG_REGID, 0); - write_xlr_ctrl_register(CPU_BLOCKID_LSU, LSU_CERROVF_REGID, 0); - write_xlr_ctrl_register(CPU_BLOCKID_LSU, LSU_CERRINT_REGID, 0); - - lsu_cfg0 = read_xlr_ctrl_register(CPU_BLOCKID_LSU, LSU_CFG0_REGID); - lsu_cfg0 = lsu_cfg0 | 0x2e; - write_xlr_ctrl_register(CPU_BLOCKID_LSU, LSU_CFG0_REGID, lsu_cfg0); -} - -static uint32_t -pci_cfg_read_32bit(uint32_t addr) -{ - uint32_t temp = 0; - uint32_t *p = (uint32_t *)xlr_pci_config_base + addr / sizeof(uint32_t); - uint64_t cerr_cpu_log = 0; - - disable_and_clear_cache_error(); - temp = bswap32(*p); - - /* Read cache err log */ - cerr_cpu_log = read_xlr_ctrl_register(CPU_BLOCKID_LSU, - LSU_CERRLOG_REGID); - if (cerr_cpu_log) { - /* Device don't exist. */ - temp = ~0x0; - } - clear_and_enable_cache_error(); - return (temp); -} - -static u_int32_t -xlr_pcib_read_config(device_t dev, u_int b, u_int s, u_int f, - u_int reg, int width) -{ - uint32_t data = 0; - - if ((width == 2) && (reg & 1)) - return 0xFFFFFFFF; - else if ((width == 4) && (reg & 3)) - return 0xFFFFFFFF; - - data = pci_cfg_read_32bit(pci_cfg_offset(b, s, f, reg)); - - if (width == 1) - return ((data >> ((reg & 3) << 3)) & 0xff); - else if (width == 2) - return ((data >> ((reg & 3) << 3)) & 0xffff); - else - return (data); -} - -static void -xlr_pcib_write_config(device_t dev, u_int b, u_int s, u_int f, - u_int reg, u_int32_t val, int width) -{ - uint32_t cfgaddr = pci_cfg_offset(b, s, f, reg); - uint32_t data = 0, *p; - - if ((width == 2) && (reg & 1)) - return; - else if ((width == 4) && (reg & 3)) - return; - - if (width == 1) { - data = pci_cfg_read_32bit(cfgaddr); - data = (data & ~(0xff << ((reg & 3) << 3))) | - (val << ((reg & 3) << 3)); - } else if (width == 2) { - data = pci_cfg_read_32bit(cfgaddr); - data = (data & ~(0xffff << ((reg & 3) << 3))) | - (val << ((reg & 3) << 3)); - } else { - data = val; - } - - p = (uint32_t *)xlr_pci_config_base + cfgaddr / sizeof(uint32_t); - *p = bswap32(data); - - return; -} - -static int -xlr_pcib_attach(device_t dev) -{ - struct xlr_pcib_softc *sc; - sc = device_get_softc(dev); - - /* - * XLR C revision chips cannot do DMA above 2G physical address - * create a parent tag with this lowaddr - */ - if (xlr_is_c_revision()) { - if (bus_dma_tag_create(bus_get_dma_tag(dev), 1, 0, - 0x7fffffff, ~0, NULL, NULL, 0x7fffffff, - 0xff, 0x7fffffff, 0, NULL, NULL, &sc->sc_pci_dmat) != 0) - panic("%s: bus_dma_tag_create failed", __func__); - } - device_add_child(dev, "pci", -1); - bus_generic_attach(dev); - return (0); -} - -static void -xlr_pcib_identify(driver_t * driver, device_t parent) -{ - - BUS_ADD_CHILD(parent, 0, "pcib", 0); -} - -/* - * XLS PCIe can have upto 4 links, and each link has its on IRQ - * Find the link on which the device is on - */ -static int -xls_pcie_link(device_t pcib, device_t dev) -{ - device_t parent, tmp; - - /* find the lane on which the slot is connected to */ - printf("xls_pcie_link : bus %s dev %s\n", device_get_nameunit(pcib), - device_get_nameunit(dev)); - tmp = dev; - while (1) { - parent = device_get_parent(tmp); - if (parent == NULL || parent == pcib) { - device_printf(dev, "Cannot find parent bus\n"); - return (-1); - } - if (strcmp(device_get_nameunit(parent), "pci0") == 0) - break; - tmp = parent; - } - return (pci_get_slot(tmp)); -} - -/* - * Find the IRQ for the link, each link has a different interrupt - * at the XLS pic - */ -static int -xls_pcie_link_irq(int link) -{ - - switch (link) { - case 0: - return (PIC_PCIE_LINK0_IRQ); - case 1: - return (PIC_PCIE_LINK1_IRQ); - case 2: - if (xlr_is_xls_b0()) - return (PIC_PCIE_B0_LINK2_IRQ); - else - return (PIC_PCIE_LINK2_IRQ); - case 3: - if (xlr_is_xls_b0()) - return (PIC_PCIE_B0_LINK3_IRQ); - else - return (PIC_PCIE_LINK3_IRQ); - } - return (-1); -} - -static int -xlr_alloc_msi(device_t pcib, device_t dev, int count, int maxcount, int *irqs) -{ - int i, link; - - /* - * Each link has 32 MSIs that can be allocated, but for now - * we only support one device per link. - * msi_alloc() equivalent is needed when we start supporting - * bridges on the PCIe link. - */ - link = xls_pcie_link(pcib, dev); - if (link == -1) - return (ENXIO); - - /* - * encode the irq so that we know it is a MSI interrupt when we - * setup interrupts - */ - for (i = 0; i < count; i++) - irqs[i] = 64 + link * 32 + i; - - return (0); -} - -static int -xlr_release_msi(device_t pcib, device_t dev, int count, int *irqs) -{ - device_printf(dev, "%s: msi release %d\n", device_get_nameunit(pcib), - count); - return (0); -} - -static int -xlr_map_msi(device_t pcib, device_t dev, int irq, uint64_t *addr, - uint32_t *data) -{ - int msi; - - if (irq >= 64) { - msi = irq - 64; - *addr = MIPS_MSI_ADDR(0); - *data = MIPS_MSI_DATA(msi); - return (0); - } else { - device_printf(dev, "%s: map_msi for irq %d - ignored", - device_get_nameunit(pcib), irq); - return (ENXIO); - } -} - -static void -bridge_pcix_ack(int irq) -{ - - (void)xlr_read_reg(xlr_io_mmio(XLR_IO_PCIX_OFFSET), 0x140 >> 2); -} - -static void -bridge_pcie_ack(int irq) -{ - uint32_t reg; - xlr_reg_t *pcie_mmio_le = xlr_io_mmio(XLR_IO_PCIE_1_OFFSET); - - switch (irq) { - case PIC_PCIE_LINK0_IRQ: - reg = PCIE_LINK0_MSI_STATUS; - break; - case PIC_PCIE_LINK1_IRQ: - reg = PCIE_LINK1_MSI_STATUS; - break; - case PIC_PCIE_LINK2_IRQ: - case PIC_PCIE_B0_LINK2_IRQ: - reg = PCIE_LINK2_MSI_STATUS; - break; - case PIC_PCIE_LINK3_IRQ: - case PIC_PCIE_B0_LINK3_IRQ: - reg = PCIE_LINK3_MSI_STATUS; - break; - default: - return; - } - xlr_write_reg(pcie_mmio_le, reg>>2, 0xffffffff); -} - -static int -mips_platform_pci_setup_intr(device_t dev, device_t child, - struct resource *irq, int flags, driver_filter_t *filt, - driver_intr_t *intr, void *arg, void **cookiep) -{ - int error = 0; - int xlrirq; - - error = rman_activate_resource(irq); - if (error) - return error; - if (rman_get_start(irq) != rman_get_end(irq)) { - device_printf(dev, "Interrupt allocation %ju != %ju\n", - rman_get_start(irq), rman_get_end(irq)); - return (EINVAL); - } - xlrirq = rman_get_start(irq); - - if (strcmp(device_get_name(dev), "pcib") != 0) - return (0); - - if (xlr_board_info.is_xls == 0) { - xlr_establish_intr(device_get_name(child), filt, - intr, arg, PIC_PCIX_IRQ, flags, cookiep, bridge_pcix_ack); - pic_setup_intr(PIC_IRT_PCIX_INDEX, PIC_PCIX_IRQ, 0x1, 1); - } else { - /* - * temporary hack for MSI, we support just one device per - * link, and assign the link interrupt to the device interrupt - */ - if (xlrirq >= 64) { - xlrirq -= 64; - if (xlrirq % 32 != 0) - return (0); - xlrirq = xls_pcie_link_irq(xlrirq / 32); - if (xlrirq == -1) - return (EINVAL); - } - xlr_establish_intr(device_get_name(child), filt, - intr, arg, xlrirq, flags, cookiep, bridge_pcie_ack); - pic_setup_intr(xlrirq - PIC_IRQ_BASE, xlrirq, 0x1, 1); - } - - return (bus_generic_setup_intr(dev, child, irq, flags, filt, intr, - arg, cookiep)); -} - -static int -mips_platform_pci_teardown_intr(device_t dev, device_t child, - struct resource *irq, void *cookie) -{ - if (strcmp(device_get_name(child), "pci") == 0) { - /* if needed reprogram the pic to clear pcix related entry */ - device_printf(dev, "teardown intr\n"); - } - return (bus_generic_teardown_intr(dev, child, irq, cookie)); -} - -static struct resource * -xlr_pci_alloc_resource(device_t bus, device_t child, int type, int *rid, - rman_res_t start, rman_res_t end, rman_res_t count, u_int flags) -{ - struct rman *rm; - struct resource *rv; - vm_offset_t va; - int needactivate = flags & RF_ACTIVE; - - switch (type) { - case SYS_RES_IRQ: - rm = &irq_rman; - break; - - case SYS_RES_IOPORT: - rm = &port_rman; - break; - - case SYS_RES_MEMORY: - rm = &mem_rman; - break; - - default: - return (0); - } - - rv = rman_reserve_resource(rm, start, end, count, flags, child); - if (rv == NULL) - return (0); - - rman_set_rid(rv, *rid); - - if (type == SYS_RES_MEMORY || type == SYS_RES_IOPORT) { - va = (vm_offset_t)pmap_mapdev(start, count); - rman_set_bushandle(rv, va); - /* bushandle is same as virtual addr */ - rman_set_virtual(rv, (void *)va); - rman_set_bustag(rv, rmi_pci_bus_space); - } - - if (needactivate) { - if (bus_activate_resource(child, type, *rid, rv)) { - rman_release_resource(rv); - return (NULL); - } - } - return (rv); -} - -static int -xlr_pci_release_resource(device_t bus, device_t child, int type, int rid, - struct resource *r) -{ - - return (rman_release_resource(r)); -} - -static bus_dma_tag_t -xlr_pci_get_dma_tag(device_t bus, device_t child) -{ - struct xlr_pcib_softc *sc; - - sc = device_get_softc(bus); - return (sc->sc_pci_dmat); -} - -static int -xlr_pci_activate_resource(device_t bus, device_t child, int type, int rid, - struct resource *r) -{ - - return (rman_activate_resource(r)); -} - -static int -xlr_pci_deactivate_resource(device_t bus, device_t child, int type, int rid, - struct resource *r) -{ - - return (rman_deactivate_resource(r)); -} - -static int -mips_pci_route_interrupt(device_t bus, device_t dev, int pin) -{ - int irq, link; - - /* - * Validate requested pin number. - */ - if ((pin < 1) || (pin > 4)) - return (255); - - if (xlr_board_info.is_xls) { - link = xls_pcie_link(bus, dev); - irq = xls_pcie_link_irq(link); - if (irq != -1) - return (irq); - } else { - if (pin == 1) - return (PIC_PCIX_IRQ); - } - - return (255); -} - -static device_method_t xlr_pcib_methods[] = { - /* Device interface */ - DEVMETHOD(device_identify, xlr_pcib_identify), - DEVMETHOD(device_probe, xlr_pcib_probe), - DEVMETHOD(device_attach, xlr_pcib_attach), - - /* Bus interface */ - DEVMETHOD(bus_read_ivar, xlr_pcib_read_ivar), - DEVMETHOD(bus_write_ivar, xlr_pcib_write_ivar), - DEVMETHOD(bus_alloc_resource, xlr_pci_alloc_resource), - DEVMETHOD(bus_release_resource, xlr_pci_release_resource), - DEVMETHOD(bus_get_dma_tag, xlr_pci_get_dma_tag), - DEVMETHOD(bus_activate_resource, xlr_pci_activate_resource), - DEVMETHOD(bus_deactivate_resource, xlr_pci_deactivate_resource), - DEVMETHOD(bus_setup_intr, mips_platform_pci_setup_intr), - DEVMETHOD(bus_teardown_intr, mips_platform_pci_teardown_intr), - - /* pcib interface */ - DEVMETHOD(pcib_maxslots, xlr_pcib_maxslots), - DEVMETHOD(pcib_read_config, xlr_pcib_read_config), - DEVMETHOD(pcib_write_config, xlr_pcib_write_config), - DEVMETHOD(pcib_route_interrupt, mips_pci_route_interrupt), - DEVMETHOD(pcib_request_feature, pcib_request_feature_allow), - - DEVMETHOD(pcib_alloc_msi, xlr_alloc_msi), - DEVMETHOD(pcib_release_msi, xlr_release_msi), - DEVMETHOD(pcib_map_msi, xlr_map_msi), - - DEVMETHOD_END -}; - -static driver_t xlr_pcib_driver = { - "pcib", - xlr_pcib_methods, - sizeof(struct xlr_pcib_softc), -}; - -DRIVER_MODULE(pcib, iodi, xlr_pcib_driver, pcib_devclass, 0, 0); Property changes on: head/sys/mips/rmi/xlr_pci.c ___________________________________________________________________ Deleted: svn:eol-style ## -1 +0,0 ## -native \ No newline at end of property Deleted: svn:keywords ## -1 +0,0 ## -FreeBSD=%H \ No newline at end of property Deleted: svn:mime-type ## -1 +0,0 ## -text/plain \ No newline at end of property Index: head/sys/mips/rmi/xls_ehci.c =================================================================== --- head/sys/mips/rmi/xls_ehci.c (revision 327460) +++ head/sys/mips/rmi/xls_ehci.c (nonexistent) @@ -1,222 +0,0 @@ -/*- - * SPDX-License-Identifier: BSD-2-Clause-NetBSD - * - * Copyright (c) 1998 The NetBSD Foundation, Inc. - * All rights reserved. - * - * This code is derived from software contributed to The NetBSD Foundation - * by Lennart Augustsson (augustss@carlstedt.se) at - * Carlstedt Research & Technology. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS - * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED - * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR - * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS - * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - */ - -#include -__FBSDID("$FreeBSD$"); - -#include "opt_bus.h" - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include - -#include -#include - -#include -#include -#include -#include - -#include -#include -#include -#include -#include - -static device_attach_t ehci_xls_attach; -static device_detach_t ehci_xls_detach; - -static const char *xlr_usb_dev_desc = "RMI XLR USB 2.0 controller"; -static const char *xlr_vendor_desc = "RMI Corp"; - -static int -ehci_xls_probe(device_t self) -{ - /* TODO see if usb is enabled on the board */ - device_set_desc(self, xlr_usb_dev_desc); - return BUS_PROBE_DEFAULT; -} - -static int -ehci_xls_attach(device_t self) -{ - ehci_softc_t *sc = device_get_softc(self); - int err; - int rid; - - sc->sc_bus.parent = self; - sc->sc_bus.devices = sc->sc_devices; - sc->sc_bus.devices_max = EHCI_MAX_DEVICES; - sc->sc_bus.dma_bits = 32; - - /* get all DMA memory */ - if (usb_bus_mem_alloc_all(&sc->sc_bus, - USB_GET_DMA_TAG(self), &ehci_iterate_hw_softc)) { - return (ENOMEM); - } - - rid = 0; - sc->sc_io_res = bus_alloc_resource_any(self, SYS_RES_MEMORY, &rid, - RF_ACTIVE); - if (!sc->sc_io_res) { - device_printf(self, "Could not map memory\n"); - goto error; - } - sc->sc_io_tag = rman_get_bustag(sc->sc_io_res); - sc->sc_io_hdl = rman_get_bushandle(sc->sc_io_res); - printf("IO Resource tag %lx, hdl %lx, size %lx\n", - (u_long)sc->sc_io_tag, (u_long)sc->sc_io_hdl, - (u_long)sc->sc_io_size); - - rid = 0; - sc->sc_irq_res = bus_alloc_resource(self, SYS_RES_IRQ, &rid, - PIC_USB_IRQ, PIC_USB_IRQ, 1, RF_SHAREABLE | RF_ACTIVE); - if (sc->sc_irq_res == NULL) { - device_printf(self, "Could not allocate irq\n"); - goto error; - } - - sc->sc_bus.bdev = device_add_child(self, "usbus", -1); - if (!sc->sc_bus.bdev) { - device_printf(self, "Could not add USB device\n"); - goto error; - } - device_set_ivars(sc->sc_bus.bdev, &sc->sc_bus); - device_set_desc(sc->sc_bus.bdev, xlr_usb_dev_desc); - - strlcpy(sc->sc_vendor, xlr_vendor_desc, sizeof(sc->sc_vendor)); - - err = bus_setup_intr(self, sc->sc_irq_res, - INTR_TYPE_BIO | INTR_MPSAFE, NULL, - (driver_intr_t *) ehci_interrupt, sc, &sc->sc_intr_hdl); - if (err) { - device_printf(self, "Could not setup irq, %d\n", err); - sc->sc_intr_hdl = NULL; - goto error; - } - - err = ehci_init(sc); - if (err) { - device_printf(self, "USB init failed err=%d\n", err); - goto error; - } - - err = device_probe_and_attach(sc->sc_bus.bdev); - if (err) { - device_printf(self, "USB probe and attach failed err=%d\n", err); - goto error; - } - - return (0); - -error: - ehci_xls_detach(self); - return (ENXIO); -} - -static int -ehci_xls_detach(device_t self) -{ - ehci_softc_t *sc = device_get_softc(self); - int err; - - /* during module unload there are lots of children leftover */ - device_delete_children(self); - - if (sc->sc_irq_res && sc->sc_intr_hdl) { - ehci_detach(sc); - - err = bus_teardown_intr(self, sc->sc_irq_res, sc->sc_intr_hdl); - if (err) - device_printf(self, "Could not tear down irq, %d\n", - err); - sc->sc_intr_hdl = 0; - } - - if (sc->sc_irq_res) { - bus_release_resource(self, SYS_RES_IRQ, 0, sc->sc_irq_res); - sc->sc_irq_res = NULL; - } - if (sc->sc_io_res) { - bus_release_resource(self, SYS_RES_MEMORY, 0, - sc->sc_io_res); - sc->sc_io_res = NULL; - sc->sc_io_tag = 0; - sc->sc_io_hdl = 0; - } - - usb_bus_mem_free_all(&sc->sc_bus, &ehci_iterate_hw_softc); - - return (0); -} - -static device_method_t ehci_methods[] = { - /* Device interface */ - DEVMETHOD(device_probe, ehci_xls_probe), - DEVMETHOD(device_attach, ehci_xls_attach), - DEVMETHOD(device_detach, ehci_xls_detach), - DEVMETHOD(device_suspend, bus_generic_suspend), - DEVMETHOD(device_resume, bus_generic_resume), - DEVMETHOD(device_shutdown, bus_generic_shutdown), - - DEVMETHOD_END -}; - -static driver_t ehci_driver = { - .name = "ehci", - .methods = ehci_methods, - .size = sizeof(struct ehci_softc), -}; - -static devclass_t ehci_devclass; - -DRIVER_MODULE(ehci, iodi, ehci_driver, ehci_devclass, 0, 0); -MODULE_DEPEND(ehci, usb, 1, 1, 1); Property changes on: head/sys/mips/rmi/xls_ehci.c ___________________________________________________________________ Deleted: svn:eol-style ## -1 +0,0 ## -native \ No newline at end of property Deleted: svn:keywords ## -1 +0,0 ## -FreeBSD=%H \ No newline at end of property Deleted: svn:mime-type ## -1 +0,0 ## -text/plain \ No newline at end of property Index: head/sys/mips/rmi/std.xlr =================================================================== --- head/sys/mips/rmi/std.xlr (revision 327460) +++ head/sys/mips/rmi/std.xlr (nonexistent) @@ -1,5 +0,0 @@ -# $FreeBSD$ -files "../rmi/files.xlr" - -cpu CPU_RMI -option NOFPU Property changes on: head/sys/mips/rmi/std.xlr ___________________________________________________________________ Deleted: svn:eol-style ## -1 +0,0 ## -native \ No newline at end of property Deleted: svn:keywords ## -1 +0,0 ## -FreeBSD=%H \ No newline at end of property Deleted: svn:mime-type ## -1 +0,0 ## -text/plain \ No newline at end of property Index: head/sys/mips/rmi/files.xlr =================================================================== --- head/sys/mips/rmi/files.xlr (revision 327460) +++ head/sys/mips/rmi/files.xlr (nonexistent) @@ -1,25 +0,0 @@ -# $FreeBSD$ -#mips/rmi/xlr_boot1_console.c standard -mips/rmi/xlr_machdep.c standard -#mips/rmi/clock.c standard -mips/rmi/tick.c standard -mips/rmi/iodi.c standard -mips/rmi/msgring.c standard -mips/rmi/msgring_xls.c standard -mips/rmi/board.c standard -mips/rmi/fmn.c standard -mips/rmi/intr_machdep.c standard -mips/rmi/mpwait.S optional smp -mips/rmi/xlr_i2c.c optional iic -mips/rmi/uart_bus_xlr_iodi.c optional uart -mips/rmi/uart_cpu_mips_xlr.c optional uart -mips/rmi/xlr_pci.c optional pci -mips/rmi/xlr_pcmcia.c optional ata -mips/rmi/xls_ehci.c optional usb ehci -mips/rmi/bus_space_rmi.c standard -mips/rmi/bus_space_rmi_pci.c standard -mips/rmi/dev/sec/rmisec.c optional rmisec -mips/rmi/dev/sec/rmilib.c optional rmisec -mips/rmi/dev/nlge/if_nlge.c optional nlge -mips/rmi/dev/iic/max6657.c optional max6657 -mips/rmi/dev/iic/at24co2n.c optional at24co2n Property changes on: head/sys/mips/rmi/files.xlr ___________________________________________________________________ Deleted: svn:eol-style ## -1 +0,0 ## -native \ No newline at end of property Deleted: svn:keywords ## -1 +0,0 ## -FreeBSD=%H \ No newline at end of property Deleted: svn:mime-type ## -1 +0,0 ## -text/plain \ No newline at end of property Index: head/sys/mips/rmi/intr_machdep.c =================================================================== --- head/sys/mips/rmi/intr_machdep.c (revision 327460) +++ head/sys/mips/rmi/intr_machdep.c (nonexistent) @@ -1,251 +0,0 @@ -/*- - * SPDX-License-Identifier: BSD-2-Clause-FreeBSD - * - * Copyright (c) 2006-2009 RMI Corporation - * Copyright (c) 2002-2004 Juli Mallett - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions, and the following disclaimer, - * without modification, immediately at the beginning of the file. - * 2. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - * - */ - -#include -__FBSDID("$FreeBSD$"); - -#include -#include -#include -#include -#include - -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include - -struct xlr_intrsrc { - void (*busack)(int); /* Additional ack */ - struct intr_event *ie; /* event corresponding to intr */ - int irq; -}; - -static struct xlr_intrsrc xlr_interrupts[XLR_MAX_INTR]; -static mips_intrcnt_t mips_intr_counters[XLR_MAX_INTR]; -static int intrcnt_index; - -void -xlr_enable_irq(int irq) -{ - uint64_t eimr; - - eimr = read_c0_eimr64(); - write_c0_eimr64(eimr | (1ULL << irq)); -} - -void -cpu_establish_softintr(const char *name, driver_filter_t * filt, - void (*handler) (void *), void *arg, int irq, int flags, - void **cookiep) -{ - - panic("Soft interrupts unsupported!\n"); -} - -void -cpu_establish_hardintr(const char *name, driver_filter_t * filt, - void (*handler) (void *), void *arg, int irq, int flags, - void **cookiep) -{ - - xlr_establish_intr(name, filt, handler, arg, irq, flags, - cookiep, NULL); -} - -static void -xlr_post_filter(void *source) -{ - struct xlr_intrsrc *src = source; - - if (src->busack) - src->busack(src->irq); - pic_ack(PIC_IRQ_TO_INTR(src->irq)); -} - -static void -xlr_pre_ithread(void *source) -{ - struct xlr_intrsrc *src = source; - - if (src->busack) - src->busack(src->irq); -} - -static void -xlr_post_ithread(void *source) -{ - struct xlr_intrsrc *src = source; - - pic_ack(PIC_IRQ_TO_INTR(src->irq)); -} - -void -xlr_establish_intr(const char *name, driver_filter_t filt, - driver_intr_t handler, void *arg, int irq, int flags, - void **cookiep, void (*busack)(int)) -{ - struct intr_event *ie; /* descriptor for the IRQ */ - struct xlr_intrsrc *src = NULL; - int errcode; - - if (irq < 0 || irq > XLR_MAX_INTR) - panic("%s called for unknown hard intr %d", __func__, irq); - - /* - * FIXME locking - not needed now, because we do this only on - * startup from CPU0 - */ - src = &xlr_interrupts[irq]; - ie = src->ie; - if (ie == NULL) { - /* - * PIC based interrupts need ack in PIC, and some SoC - * components need additional acks (e.g. PCI) - */ - if (PIC_IRQ_IS_PICINTR(irq)) - errcode = intr_event_create(&ie, src, 0, irq, - xlr_pre_ithread, xlr_post_ithread, xlr_post_filter, - NULL, "hard intr%d:", irq); - else { - if (filt == NULL) - panic("Not supported - non filter percpu intr"); - errcode = intr_event_create(&ie, src, 0, irq, - NULL, NULL, NULL, NULL, "hard intr%d:", irq); - } - if (errcode) { - printf("Could not create event for intr %d\n", irq); - return; - } - src->irq = irq; - src->busack = busack; - src->ie = ie; - } - intr_event_add_handler(ie, name, filt, handler, arg, - intr_priority(flags), flags, cookiep); - xlr_enable_irq(irq); -} - -void -cpu_intr(struct trapframe *tf) -{ - struct intr_event *ie; - uint64_t eirr, eimr; - int i; - - critical_enter(); - - /* find a list of enabled interrupts */ - eirr = read_c0_eirr64(); - eimr = read_c0_eimr64(); - eirr &= eimr; - - if (eirr == 0) { - critical_exit(); - return; - } - /* - * No need to clear the EIRR here as the handler writes to - * compare which ACKs the interrupt. - */ - if (eirr & (1 << IRQ_TIMER)) { - intr_event_handle(xlr_interrupts[IRQ_TIMER].ie, tf); - critical_exit(); - return; - } - - /* FIXME sched pin >? LOCK>? */ - for (i = sizeof(eirr) * 8 - 1; i >= 0; i--) { - if ((eirr & (1ULL << i)) == 0) - continue; - - ie = xlr_interrupts[i].ie; - /* Don't account special IRQs */ - switch (i) { - case IRQ_IPI: - case IRQ_MSGRING: - break; - default: - mips_intrcnt_inc(mips_intr_counters[i]); - } - - /* Ack the IRQ on the CPU */ - write_c0_eirr64(1ULL << i); - if (intr_event_handle(ie, tf) != 0) { - printf("stray interrupt %d\n", i); - } - } - critical_exit(); -} - -void -mips_intrcnt_setname(mips_intrcnt_t counter, const char *name) -{ - int idx = counter - intrcnt; - - KASSERT(counter != NULL, ("mips_intrcnt_setname: NULL counter")); - - snprintf(intrnames + (MAXCOMLEN + 1) * idx, - MAXCOMLEN + 1, "%-*s", MAXCOMLEN, name); -} - -mips_intrcnt_t -mips_intrcnt_create(const char* name) -{ - mips_intrcnt_t counter = &intrcnt[intrcnt_index++]; - - mips_intrcnt_setname(counter, name); - return counter; -} - -void -cpu_init_interrupts() -{ - int i; - char name[MAXCOMLEN + 1]; - - /* - * Initialize all available vectors so spare IRQ - * would show up in systat output - */ - for (i = 0; i < XLR_MAX_INTR; i++) { - snprintf(name, MAXCOMLEN + 1, "int%d:", i); - mips_intr_counters[i] = mips_intrcnt_create(name); - } -} Property changes on: head/sys/mips/rmi/intr_machdep.c ___________________________________________________________________ Deleted: svn:eol-style ## -1 +0,0 ## -native \ No newline at end of property Deleted: svn:keywords ## -1 +0,0 ## -FreeBSD=%H \ No newline at end of property Deleted: svn:mime-type ## -1 +0,0 ## -text/plain \ No newline at end of property Index: head/sys/mips/rmi/dev/nlge/if_nlge.c =================================================================== --- head/sys/mips/rmi/dev/nlge/if_nlge.c (revision 327460) +++ head/sys/mips/rmi/dev/nlge/if_nlge.c (nonexistent) @@ -1,2565 +0,0 @@ -/*- - * SPDX-License-Identifier: BSD-3-Clause - * - * Copyright (c) 2003-2009 RMI Corporation - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. Neither the name of RMI Corporation, nor the names of its contributors, - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - * - * RMI_BSD */ - -/* - * The XLR device supports upto four 10/100/1000 Ethernet MACs and upto - * two 10G Ethernet MACs (of XGMII). Alternatively, each 10G port can used - * as a SPI-4 interface, with 8 ports per such interface. The MACs are - * encapsulated in another hardware block referred to as network accelerator, - * such that there are three instances of these in a XLR. One of them controls - * the four 1G RGMII ports while one each of the others controls an XGMII port. - * Enabling MACs requires configuring the corresponding network accelerator - * and the individual port. - * The XLS device supports upto 8 10/100/1000 Ethernet MACs or max 2 10G - * Ethernet MACs. The 1G MACs are of SGMII and 10G MACs are of XAUI - * interface. These ports are part of two network accelerators. - * The nlge driver configures and initializes non-SPI4 Ethernet ports in the - * XLR/XLS devices and enables data transfer on them. - */ - -#include -__FBSDID("$FreeBSD$"); - -#ifdef HAVE_KERNEL_OPTION_HEADERS -#include "opt_device_polling.h" -#endif - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#define __RMAN_RESOURCE_VISIBLE -#include -#include -#include -#include - -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include - -#include -#include -#include - -#include -#include -#include -#include -#include -#include -#include /* for DELAY */ -#include -#include - -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include "miidevs.h" -#include -#include "miibus_if.h" - -#include - -MODULE_DEPEND(nlna, nlge, 1, 1, 1); -MODULE_DEPEND(nlge, ether, 1, 1, 1); -MODULE_DEPEND(nlge, miibus, 1, 1, 1); - -/* Network accelarator entry points */ -static int nlna_probe(device_t); -static int nlna_attach(device_t); -static int nlna_detach(device_t); -static int nlna_suspend(device_t); -static int nlna_resume(device_t); -static int nlna_shutdown(device_t); - -/* GMAC port entry points */ -static int nlge_probe(device_t); -static int nlge_attach(device_t); -static int nlge_detach(device_t); -static int nlge_suspend(device_t); -static int nlge_resume(device_t); -static void nlge_init(void *); -static int nlge_ioctl(struct ifnet *, u_long, caddr_t); -static int nlge_tx(struct ifnet *ifp, struct mbuf *m); -static void nlge_rx(struct nlge_softc *sc, vm_paddr_t paddr, int len); - -static int nlge_mii_write(device_t, int, int, int); -static int nlge_mii_read(device_t, int, int); -static void nlge_mac_mii_statchg(device_t); -static int nlge_mediachange(struct ifnet *ifp); -static void nlge_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr); - -/* Other internal/helper functions */ -static void *get_buf(void); - -static void nlna_add_to_port_set(struct nlge_port_set *pset, - struct nlge_softc *sc); -static void nlna_config_pde(struct nlna_softc *); -static void nlna_config_parser(struct nlna_softc *); -static void nlna_config_classifier(struct nlna_softc *); -static void nlna_config_fifo_spill_area(struct nlna_softc *sc); -static void nlna_config_translate_table(struct nlna_softc *sc); -static void nlna_config_common(struct nlna_softc *); -static void nlna_disable_ports(struct nlna_softc *sc); -static void nlna_enable_intr(struct nlna_softc *sc); -static void nlna_disable_intr(struct nlna_softc *sc); -static void nlna_enable_ports(struct nlna_softc *sc); -static void nlna_get_all_softc(device_t iodi_dev, - struct nlna_softc **sc_vec, uint32_t vec_sz); -static void nlna_hw_init(struct nlna_softc *sc); -static int nlna_is_last_active_na(struct nlna_softc *sc); -static void nlna_media_specific_config(struct nlna_softc *sc); -static void nlna_reset_ports(struct nlna_softc *sc, - struct xlr_gmac_block_t *blk); -static struct nlna_softc *nlna_sc_init(device_t dev, - struct xlr_gmac_block_t *blk); -static void nlna_setup_intr(struct nlna_softc *sc); -static void nlna_smp_update_pde(void *dummy __unused); -static void nlna_submit_rx_free_desc(struct nlna_softc *sc, - uint32_t n_desc); - -static int nlge_gmac_config_speed(struct nlge_softc *, int quick); -static void nlge_hw_init(struct nlge_softc *sc); -static int nlge_if_init(struct nlge_softc *sc); -static void nlge_intr(void *arg); -static int nlge_irq_init(struct nlge_softc *sc); -static void nlge_irq_fini(struct nlge_softc *sc); -static void nlge_media_specific_init(struct nlge_softc *sc); -static void nlge_mii_init(device_t dev, struct nlge_softc *sc); -static int nlge_mii_read_internal(xlr_reg_t *mii_base, int phyaddr, - int regidx); -static void nlge_mii_write_internal(xlr_reg_t *mii_base, int phyaddr, - int regidx, int regval); -void nlge_msgring_handler(int bucket, int size, int code, - int stid, struct msgrng_msg *msg, void *data); -static void nlge_port_disable(struct nlge_softc *sc); -static void nlge_port_enable(struct nlge_softc *sc); -static void nlge_read_mac_addr(struct nlge_softc *sc); -static void nlge_sc_init(struct nlge_softc *sc, device_t dev, - struct xlr_gmac_port *port_info); -static void nlge_set_mac_addr(struct nlge_softc *sc); -static void nlge_set_port_attribs(struct nlge_softc *, - struct xlr_gmac_port *); -static void nlge_mac_set_rx_mode(struct nlge_softc *sc); -static void nlge_sgmii_init(struct nlge_softc *sc); -static int nlge_start_locked(struct ifnet *ifp, struct nlge_softc *sc, - struct mbuf *m); - -static int prepare_fmn_message(struct nlge_softc *sc, - struct msgrng_msg *msg, uint32_t *n_entries, struct mbuf *m_head, - uint64_t fr_stid, struct nlge_tx_desc **tx_desc); - -static void release_tx_desc(vm_paddr_t phy_addr); -static int send_fmn_msg_tx(struct nlge_softc *, struct msgrng_msg *, - uint32_t n_entries); - -//#define DEBUG -#ifdef DEBUG -static int mac_debug = 1; -#undef PDEBUG -#define PDEBUG(fmt, args...) \ - do {\ - if (mac_debug) {\ - printf("[%s@%d|%s]: cpu_%d: " fmt, \ - __FILE__, __LINE__, __FUNCTION__, PCPU_GET(cpuid), ##args);\ - }\ - } while(0); - -/* Debug/dump functions */ -static void dump_reg(xlr_reg_t *addr, uint32_t offset, char *name); -static void dump_gmac_registers(struct nlge_softc *); -static void dump_na_registers(xlr_reg_t *base, int port_id); -static void dump_mac_stats(struct nlge_softc *sc); -static void dump_mii_regs(struct nlge_softc *sc) __attribute__((used)); -static void dump_mii_data(struct mii_data *mii) __attribute__((used)); -static void dump_board_info(struct xlr_board_info *); -static void dump_pcs_regs(struct nlge_softc *sc, int phy); - -#else -#undef PDEBUG -#define PDEBUG(fmt, args...) -#define dump_reg(a, o, n) /* nop */ -#define dump_gmac_registers(a) /* nop */ -#define dump_na_registers(a, p) /* nop */ -#define dump_board_info(b) /* nop */ -#define dump_mac_stats(sc) /* nop */ -#define dump_mii_regs(sc) /* nop */ -#define dump_mii_data(mii) /* nop */ -#define dump_pcs_regs(sc, phy) /* nop */ -#endif - -/* Wrappers etc. to export the driver entry points. */ -static device_method_t nlna_methods[] = { - /* Device interface */ - DEVMETHOD(device_probe, nlna_probe), - DEVMETHOD(device_attach, nlna_attach), - DEVMETHOD(device_detach, nlna_detach), - DEVMETHOD(device_shutdown, nlna_shutdown), - DEVMETHOD(device_suspend, nlna_suspend), - DEVMETHOD(device_resume, nlna_resume), - - /* bus interface : TBD : what are these for ? */ - DEVMETHOD(bus_setup_intr, bus_generic_setup_intr), - - DEVMETHOD_END -}; - -static driver_t nlna_driver = { - "nlna", - nlna_methods, - sizeof(struct nlna_softc) -}; - -static devclass_t nlna_devclass; - -static device_method_t nlge_methods[] = { - /* Device interface */ - DEVMETHOD(device_probe, nlge_probe), - DEVMETHOD(device_attach, nlge_attach), - DEVMETHOD(device_detach, nlge_detach), - DEVMETHOD(device_shutdown, bus_generic_shutdown), - DEVMETHOD(device_suspend, nlge_suspend), - DEVMETHOD(device_resume, nlge_resume), - - /* MII interface */ - DEVMETHOD(miibus_readreg, nlge_mii_read), - DEVMETHOD(miibus_writereg, nlge_mii_write), - DEVMETHOD(miibus_statchg, nlge_mac_mii_statchg), - - {0, 0} -}; - -static driver_t nlge_driver = { - "nlge", - nlge_methods, - sizeof(struct nlge_softc) -}; - -static devclass_t nlge_devclass; - -DRIVER_MODULE(nlna, iodi, nlna_driver, nlna_devclass, 0, 0); -DRIVER_MODULE(nlge, nlna, nlge_driver, nlge_devclass, 0, 0); -DRIVER_MODULE(miibus, nlge, miibus_driver, miibus_devclass, 0, 0); - -static uma_zone_t nl_tx_desc_zone; - -/* Tunables. */ -static int flow_classification = 0; -TUNABLE_INT("hw.nlge.flow_classification", &flow_classification); - -#define NLGE_HW_CHKSUM 1 - -static __inline void -atomic_incr_long(unsigned long *addr) -{ - /* XXX: fix for 64 bit */ - unsigned int *iaddr = (unsigned int *)addr; - - xlr_ldaddwu(1, iaddr); -} - -static int -nlna_probe(device_t dev) -{ - return (BUS_PROBE_DEFAULT); -} - -/* - * Add all attached GMAC/XGMAC ports to the device tree. Port - * configuration is spread in two regions - common configuration - * for all ports in the NA and per-port configuration in MAC-specific - * region. This function does the following: - * - adds the ports to the device tree - * - reset the ports - * - do all the common initialization - * - invoke bus_generic_attach for per-port configuration - * - supply initial free rx descriptors to ports - * - initialize s/w data structures - * - finally, enable interrupts (only in the last NA). - * - * For reference, sample address space for common and per-port - * registers is given below. - * - * The address map for RNA0 is: (typical value) - * - * XLR_IO_BASE +--------------------------------------+ 0xbef0_0000 - * | | - * | | - * | | - * | | - * | | - * | | - * GMAC0 ---> +--------------------------------------+ 0xbef0_c000 - * | | - * | | - * (common) -> |......................................| 0xbef0_c400 - * | | - * | (RGMII/SGMII: common registers) | - * | | - * GMAC1 ---> |--------------------------------------| 0xbef0_d000 - * | | - * | | - * (common) -> |......................................| 0xbef0_d400 - * | | - * | (RGMII/SGMII: common registers) | - * | | - * |......................................| - * and so on .... - * - * Ref: Figure 14-3 and Table 14-1 of XLR PRM - */ -static int -nlna_attach(device_t dev) -{ - struct xlr_gmac_block_t *block_info; - device_t gmac_dev; - struct nlna_softc *sc; - int error; - int i; - int id; - - id = device_get_unit(dev); - block_info = device_get_ivars(dev); - if (!block_info->enabled) { - return 0; - } - -#ifdef DEBUG - dump_board_info(&xlr_board_info); -#endif - /* Initialize nlna state in softc structure */ - sc = nlna_sc_init(dev, block_info); - - /* Add device's for the ports controlled by this NA. */ - if (block_info->type == XLR_GMAC) { - KASSERT(id < 2, ("No GMACs supported with this network" - "accelerator: %d", id)); - for (i = 0; i < sc->num_ports; i++) { - gmac_dev = device_add_child(dev, "nlge", -1); - device_set_ivars(gmac_dev, &block_info->gmac_port[i]); - } - } else if (block_info->type == XLR_XGMAC) { - KASSERT(id > 0 && id <= 2, ("No XGMACs supported with this" - "network accelerator: %d", id)); - gmac_dev = device_add_child(dev, "nlge", -1); - device_set_ivars(gmac_dev, &block_info->gmac_port[0]); - } else if (block_info->type == XLR_SPI4) { - /* SPI4 is not supported here */ - device_printf(dev, "Unsupported: NA with SPI4 type"); - return (ENOTSUP); - } - - nlna_reset_ports(sc, block_info); - - /* Initialize Network Accelarator registers. */ - nlna_hw_init(sc); - - error = bus_generic_attach(dev); - if (error) { - device_printf(dev, "failed to attach port(s)\n"); - goto fail; - } - - /* Send out the initial pool of free-descriptors for the rx path */ - nlna_submit_rx_free_desc(sc, MAX_FRIN_SPILL); - - /* S/w data structure initializations shared by all NA's. */ - if (nl_tx_desc_zone == NULL) { - /* Create a zone for allocating tx descriptors */ - nl_tx_desc_zone = uma_zcreate("NL Tx Desc", - sizeof(struct nlge_tx_desc), NULL, NULL, NULL, NULL, - XLR_CACHELINE_SIZE, 0); - } - - /* Enable NA interrupts */ - nlna_setup_intr(sc); - - return (0); - -fail: - return (error); -} - -static int -nlna_detach(device_t dev) -{ - struct nlna_softc *sc; - - sc = device_get_softc(dev); - if (device_is_alive(dev)) { - nlna_disable_intr(sc); - /* This will make sure that per-port detach is complete - * and all traffic on the ports has been stopped. */ - bus_generic_detach(dev); - uma_zdestroy(nl_tx_desc_zone); - } - - return (0); -} - -static int -nlna_suspend(device_t dev) -{ - - return (0); -} - -static int -nlna_resume(device_t dev) -{ - - return (0); -} - -static int -nlna_shutdown(device_t dev) -{ - return (0); -} - - -/* GMAC port entry points */ -static int -nlge_probe(device_t dev) -{ - struct nlge_softc *sc; - struct xlr_gmac_port *port_info; - int index; - char *desc[] = { "RGMII", "SGMII", "RGMII/SGMII", "XGMAC", "XAUI", - "Unknown"}; - - port_info = device_get_ivars(dev); - index = (port_info->type < XLR_RGMII || port_info->type > XLR_XAUI) ? - 5 : port_info->type; - device_set_desc_copy(dev, desc[index]); - - sc = device_get_softc(dev); - nlge_sc_init(sc, dev, port_info); - - nlge_port_disable(sc); - - return (0); -} - -static int -nlge_attach(device_t dev) -{ - struct nlge_softc *sc; - struct nlna_softc *nsc; - int error; - - sc = device_get_softc(dev); - - nlge_if_init(sc); - nlge_mii_init(dev, sc); - error = nlge_irq_init(sc); - if (error) - return error; - nlge_hw_init(sc); - - nsc = (struct nlna_softc *)device_get_softc(device_get_parent(dev)); - nsc->child_sc[sc->instance] = sc; - - return (0); -} - -static int -nlge_detach(device_t dev) -{ - struct nlge_softc *sc; - struct ifnet *ifp; - - sc = device_get_softc(dev); - ifp = sc->nlge_if; - - if (device_is_attached(dev)) { - nlge_port_disable(sc); - nlge_irq_fini(sc); - ether_ifdetach(ifp); - bus_generic_detach(dev); - } - if (ifp) - if_free(ifp); - - return (0); -} - -static int -nlge_suspend(device_t dev) -{ - return (0); -} - -static int -nlge_resume(device_t dev) -{ - return (0); -} - -static void -nlge_init(void *addr) -{ - struct nlge_softc *sc; - struct ifnet *ifp; - - sc = (struct nlge_softc *)addr; - ifp = sc->nlge_if; - - if (ifp->if_drv_flags & IFF_DRV_RUNNING) - return; - - nlge_gmac_config_speed(sc, 1); - ifp->if_drv_flags |= IFF_DRV_RUNNING; - ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; - nlge_port_enable(sc); - - if (sc->port_type == XLR_SGMII) { - dump_pcs_regs(sc, 27); - } - dump_gmac_registers(sc); - dump_mac_stats(sc); -} - -static int -nlge_ioctl(struct ifnet *ifp, u_long command, caddr_t data) -{ - struct mii_data *mii; - struct nlge_softc *sc; - struct ifreq *ifr; - int error; - - sc = ifp->if_softc; - error = 0; - ifr = (struct ifreq *)data; - - switch(command) { - case SIOCSIFFLAGS: - NLGE_LOCK(sc); - if (ifp->if_flags & IFF_UP) { - if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) { - nlge_init(sc); - } - if (ifp->if_flags & IFF_PROMISC && - !(sc->if_flags & IFF_PROMISC)) { - sc->if_flags |= IFF_PROMISC; - nlge_mac_set_rx_mode(sc); - } else if (!(ifp->if_flags & IFF_PROMISC) && - sc->if_flags & IFF_PROMISC) { - sc->if_flags &= IFF_PROMISC; - nlge_mac_set_rx_mode(sc); - } - } else { - if (ifp->if_drv_flags & IFF_DRV_RUNNING) { - nlge_port_disable(sc); - } - } - sc->if_flags = ifp->if_flags; - NLGE_UNLOCK(sc); - error = 0; - break; - - case SIOCSIFMEDIA: - case SIOCGIFMEDIA: - if (sc->mii_bus != NULL) { - mii = (struct mii_data *)device_get_softc(sc->mii_bus); - error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, - command); - } - break; - - default: - error = ether_ioctl(ifp, command, data); - break; - } - - return (error); -} - -/* This function is called from an interrupt handler */ -void -nlge_msgring_handler(int bucket, int size, int code, int stid, - struct msgrng_msg *msg, void *data) -{ - struct nlna_softc *na_sc; - struct nlge_softc *sc; - struct ifnet *ifp; - struct mbuf *m; - vm_paddr_t phys_addr; - uint32_t length; - int ctrl; - int tx_error; - int port; - int is_p2p; - - is_p2p = 0; - tx_error = 0; - length = (msg->msg0 >> 40) & 0x3fff; - na_sc = (struct nlna_softc *)data; - if (length == 0) { - ctrl = CTRL_REG_FREE; - phys_addr = msg->msg0 & 0xffffffffffULL; - port = (msg->msg0 >> 54) & 0x0f; - is_p2p = (msg->msg0 >> 62) & 0x1; - tx_error = (msg->msg0 >> 58) & 0xf; - } else { - ctrl = CTRL_SNGL; - phys_addr = msg->msg0 & 0xffffffffe0ULL; - length = length - BYTE_OFFSET - MAC_CRC_LEN; - port = msg->msg0 & 0x0f; - } - - sc = na_sc->child_sc[port]; - if (sc == NULL) { - printf("Message (of %d len) with softc=NULL on %d port (type=%s)\n", - length, port, (ctrl == CTRL_SNGL ? "Pkt rx" : - "Freeback for tx packet")); - return; - } - - if (ctrl == CTRL_REG_FREE || ctrl == CTRL_JUMBO_FREE) { - ifp = sc->nlge_if; - if (!tx_error) { - if (is_p2p) { - release_tx_desc(phys_addr); - } else { -#ifdef __mips_n64 - m = (struct mbuf *)(uintptr_t)xlr_paddr_ld(phys_addr); - m->m_nextpkt = NULL; -#else - m = (struct mbuf *)(uintptr_t)phys_addr; -#endif - m_freem(m); - } - NLGE_LOCK(sc); - if (ifp->if_drv_flags & IFF_DRV_OACTIVE){ - ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; - } - NLGE_UNLOCK(sc); - } else { - printf("ERROR: Tx fb error (%d) on port %d\n", tx_error, - port); - } - tx_error ? - if_inc_counter(ifp, IFCOUNTER_OERRORS, 1) : - if_inc_counter(ifp, IFCOUNTER_OPACKETS, 1); - } else if (ctrl == CTRL_SNGL || ctrl == CTRL_START) { - /* Rx Packet */ - - nlge_rx(sc, phys_addr, length); - nlna_submit_rx_free_desc(na_sc, 1); /* return free descr to NA */ - } else { - printf("[%s]: unrecognized ctrl=%d!\n", __func__, ctrl); - } - -} - -static int -nlge_tx(struct ifnet *ifp, struct mbuf *m) -{ - return (nlge_start_locked(ifp, ifp->if_softc, m)); -} - -static int -nlge_start_locked(struct ifnet *ifp, struct nlge_softc *sc, struct mbuf *m) -{ - struct msgrng_msg msg; - struct nlge_tx_desc *tx_desc; - uint64_t fr_stid; - uint32_t cpu; - uint32_t n_entries; - uint32_t tid; - int error, ret; - - if (m == NULL) - return (0); - - tx_desc = NULL; - error = 0; - if (!(ifp->if_drv_flags & IFF_DRV_RUNNING) || - ifp->if_drv_flags & IFF_DRV_OACTIVE) { - error = ENXIO; - goto fail; // note: mbuf will get free'd - } - - cpu = xlr_core_id(); - tid = xlr_thr_id(); - /* H/w threads [0, 2] --> bucket 6 and [1, 3] --> bucket 7 */ - fr_stid = cpu * 8 + 6 + (tid % 2); - - /* - * First, remove some freeback messages before transmitting - * any new packets. However, cap the number of messages - * drained to permit this thread to continue with its - * transmission. - * - * Mask for buckets {6, 7} is 0xc0 - */ - xlr_msgring_handler(0xc0, 4); - - ret = prepare_fmn_message(sc, &msg, &n_entries, m, fr_stid, &tx_desc); - if (ret) { - error = (ret == 2) ? ENOBUFS : ENOTSUP; - goto fail; - } - ret = send_fmn_msg_tx(sc, &msg, n_entries); - if (ret != 0) { - error = EBUSY; - goto fail; - } - - return (0); - -fail: - if (tx_desc != NULL) { - uma_zfree(nl_tx_desc_zone, tx_desc); - } - if (m != NULL) { - if (ifp->if_drv_flags & IFF_DRV_RUNNING) { - NLGE_LOCK(sc); - ifp->if_drv_flags |= IFF_DRV_OACTIVE; - NLGE_UNLOCK(sc); - } - m_freem(m); - if_inc_counter(ifp, IFCOUNTER_IQDROPS, 1); - } - return (error); -} - -static void -nlge_rx(struct nlge_softc *sc, vm_paddr_t paddr, int len) -{ - struct ifnet *ifp; - struct mbuf *m; - uint64_t tm, mag; - uint32_t sr; - - sr = xlr_enable_kx(); - tm = xlr_paddr_ld(paddr - XLR_CACHELINE_SIZE); - mag = xlr_paddr_ld(paddr - XLR_CACHELINE_SIZE + sizeof(uint64_t)); - xlr_restore_kx(sr); - - m = (struct mbuf *)(intptr_t)tm; - if (mag != 0xf00bad) { - /* somebody else's packet. Error - FIXME in intialization */ - printf("cpu %d: *ERROR* Not my packet paddr %jx\n", - xlr_core_id(), (uintmax_t)paddr); - return; - } - - ifp = sc->nlge_if; - -#ifdef NLGE_HW_CHKSUM - m->m_pkthdr.csum_flags = CSUM_IP_CHECKED; - if (m->m_data[10] & 0x2) { - m->m_pkthdr.csum_flags |= CSUM_IP_VALID; - if (m->m_data[10] & 0x1) { - m->m_pkthdr.csum_flags |= (CSUM_DATA_VALID | - CSUM_PSEUDO_HDR); - m->m_pkthdr.csum_data = htons(0xffff); - } - } - m->m_data += NLGE_PREPAD_LEN; - len -= NLGE_PREPAD_LEN; -#else - m->m_pkthdr.csum_flags = 0; -#endif - - /* align the data */ - m->m_data += BYTE_OFFSET ; - m->m_pkthdr.len = m->m_len = len; - m->m_pkthdr.rcvif = ifp; - - if_inc_counter(ifp, IFCOUNTER_IPACKETS, 1); - (*ifp->if_input)(ifp, m); -} - -static int -nlge_mii_write(device_t dev, int phyaddr, int regidx, int regval) -{ - struct nlge_softc *sc; - - sc = device_get_softc(dev); - if (sc->port_type != XLR_XGMII) - nlge_mii_write_internal(sc->mii_base, phyaddr, regidx, regval); - - return (0); -} - -static int -nlge_mii_read(device_t dev, int phyaddr, int regidx) -{ - struct nlge_softc *sc; - int val; - - sc = device_get_softc(dev); - val = (sc->port_type == XLR_XGMII) ? (0xffff) : - nlge_mii_read_internal(sc->mii_base, phyaddr, regidx); - - return (val); -} - -static void -nlge_mac_mii_statchg(device_t dev) -{ -} - -static int -nlge_mediachange(struct ifnet *ifp) -{ - return 0; -} - -static void -nlge_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr) -{ - struct nlge_softc *sc; - struct mii_data *md; - - md = NULL; - sc = ifp->if_softc; - if (sc->mii_bus) - md = device_get_softc(sc->mii_bus); - - ifmr->ifm_status = IFM_AVALID; - ifmr->ifm_active = IFM_ETHER; - - if (sc->link == xlr_mac_link_down) - return; - - if (md != NULL) - ifmr->ifm_active = md->mii_media.ifm_cur->ifm_media; - ifmr->ifm_status |= IFM_ACTIVE; -} - -static struct nlna_softc * -nlna_sc_init(device_t dev, struct xlr_gmac_block_t *blk) -{ - struct nlna_softc *sc; - - sc = device_get_softc(dev); - memset(sc, 0, sizeof(*sc)); - sc->nlna_dev = dev; - sc->base = xlr_io_mmio(blk->baseaddr); - sc->rfrbucket = blk->station_rfr; - sc->station_id = blk->station_id; - sc->na_type = blk->type; - sc->mac_type = blk->mode; - sc->num_ports = blk->num_ports; - - sc->mdio_set.port_vec = sc->mdio_sc; - sc->mdio_set.vec_sz = XLR_MAX_MACS; - - return (sc); -} - -/* - * Do: - * - Initialize common GMAC registers (index range 0x100-0x3ff). - */ -static void -nlna_hw_init(struct nlna_softc *sc) -{ - - /* - * Register message ring handler for the NA block, messages from - * the GMAC will have source station id to the first bucket of the - * NA FMN station, so register just that station id. - */ - if (register_msgring_handler(sc->station_id, sc->station_id + 1, - nlge_msgring_handler, sc)) { - panic("Couldn't register msgring handler\n"); - } - nlna_config_fifo_spill_area(sc); - nlna_config_pde(sc); - nlna_config_common(sc); - nlna_config_parser(sc); - nlna_config_classifier(sc); -} - -/* - * Enable interrupts on all the ports controlled by this NA. For now, we - * only care about the MII interrupt and this has to be enabled only - * on the port id0. - * - * This function is not in-sync with the regular way of doing things - it - * executes only in the context of the last active network accelerator (and - * thereby has some ugly accesses in the device tree). Though inelegant, it - * is necessary to do it this way as the per-port interrupts can be - * setup/enabled only after all the network accelerators have been - * initialized. - */ -static void -nlna_setup_intr(struct nlna_softc *sc) -{ - struct nlna_softc *na_sc[XLR_MAX_NLNA]; - struct nlge_port_set *pset; - struct xlr_gmac_port *port_info; - device_t iodi_dev; - int i, j; - - if (!nlna_is_last_active_na(sc)) - return ; - - /* Collect all nlna softc pointers */ - memset(na_sc, 0, sizeof(*na_sc) * XLR_MAX_NLNA); - iodi_dev = device_get_parent(sc->nlna_dev); - nlna_get_all_softc(iodi_dev, na_sc, XLR_MAX_NLNA); - - /* Setup the MDIO interrupt lists. */ - /* - * MDIO interrupts are coarse - a single interrupt line provides - * information about one of many possible ports. To figure out the - * exact port on which action is to be taken, all of the ports - * linked to an MDIO interrupt should be read. To enable this, - * ports need to add themselves to port sets. - */ - for (i = 0; i < XLR_MAX_NLNA; i++) { - if (na_sc[i] == NULL) - continue; - for (j = 0; j < na_sc[i]->num_ports; j++) { - /* processing j-th port on i-th NA */ - port_info = device_get_ivars( - na_sc[i]->child_sc[j]->nlge_dev); - pset = &na_sc[port_info->mdint_id]->mdio_set; - nlna_add_to_port_set(pset, na_sc[i]->child_sc[j]); - } - } - - /* Enable interrupts */ - for (i = 0; i < XLR_MAX_NLNA; i++) { - if (na_sc[i] != NULL && na_sc[i]->na_type != XLR_XGMAC) { - nlna_enable_intr(na_sc[i]); - } - } -} - -static void -nlna_add_to_port_set(struct nlge_port_set *pset, struct nlge_softc *sc) -{ - int i; - - /* step past the non-NULL elements */ - for (i = 0; i < pset->vec_sz && pset->port_vec[i] != NULL; i++) ; - if (i < pset->vec_sz) - pset->port_vec[i] = sc; - else - printf("warning: internal error: out-of-bounds for MDIO array"); -} - -static void -nlna_enable_intr(struct nlna_softc *sc) -{ - int i; - - for (i = 0; i < sc->num_ports; i++) { - if (sc->child_sc[i]->instance == 0) - NLGE_WRITE(sc->child_sc[i]->base, R_INTMASK, - (1 << O_INTMASK__MDInt)); - } -} - -static void -nlna_disable_intr(struct nlna_softc *sc) -{ - int i; - - for (i = 0; i < sc->num_ports; i++) { - if (sc->child_sc[i]->instance == 0) - NLGE_WRITE(sc->child_sc[i]->base, R_INTMASK, 0); - } -} - -static int -nlna_is_last_active_na(struct nlna_softc *sc) -{ - int id; - - id = device_get_unit(sc->nlna_dev); - return (id == 2 || xlr_board_info.gmac_block[id + 1].enabled == 0); -} - -static void -nlna_submit_rx_free_desc(struct nlna_softc *sc, uint32_t n_desc) -{ - struct msgrng_msg msg; - void *ptr; - uint32_t msgrng_flags; - int i, n, stid, ret, code; - - if (n_desc > 1) { - PDEBUG("Sending %d free-in descriptors to station=%d\n", n_desc, - sc->rfrbucket); - } - - stid = sc->rfrbucket; - code = (sc->na_type == XLR_XGMAC) ? MSGRNG_CODE_XGMAC : MSGRNG_CODE_MAC; - memset(&msg, 0, sizeof(msg)); - - for (i = 0; i < n_desc; i++) { - ptr = get_buf(); - if (!ptr) { - ret = -ENOMEM; - device_printf(sc->nlna_dev, "Cannot allocate mbuf\n"); - break; - } - - /* Send the free Rx desc to the MAC */ - msg.msg0 = vtophys(ptr) & 0xffffffffe0ULL; - n = 0; - do { - msgrng_flags = msgrng_access_enable(); - ret = message_send(1, code, stid, &msg); - msgrng_restore(msgrng_flags); - KASSERT(n++ < 100000, ("Too many credit fails in rx path\n")); - } while (ret != 0); - } -} - -static __inline__ void * -nlna_config_spill(xlr_reg_t *base, int reg_start_0, int reg_start_1, - int reg_size, int size) -{ - void *spill; - uint64_t phys_addr; - uint32_t spill_size; - - spill_size = size; - spill = contigmalloc((spill_size + XLR_CACHELINE_SIZE), M_DEVBUF, - M_NOWAIT | M_ZERO, 0, 0xffffffff, XLR_CACHELINE_SIZE, 0); - if (spill == NULL || ((vm_offset_t) spill & (XLR_CACHELINE_SIZE - 1))) { - panic("Unable to allocate memory for spill area!\n"); - } - phys_addr = vtophys(spill); - PDEBUG("Allocated spill %d bytes at %llx\n", size, phys_addr); - NLGE_WRITE(base, reg_start_0, (phys_addr >> 5) & 0xffffffff); - NLGE_WRITE(base, reg_start_1, (phys_addr >> 37) & 0x07); - NLGE_WRITE(base, reg_size, spill_size); - - return (spill); -} - -/* - * Configure the 6 FIFO's that are used by the network accelarator to - * communicate with the rest of the XLx device. 4 of the FIFO's are for - * packets from NA --> cpu (called Class FIFO's) and 2 are for feeding - * the NA with free descriptors. - */ -static void -nlna_config_fifo_spill_area(struct nlna_softc *sc) -{ - sc->frin_spill = nlna_config_spill(sc->base, - R_REG_FRIN_SPILL_MEM_START_0, - R_REG_FRIN_SPILL_MEM_START_1, - R_REG_FRIN_SPILL_MEM_SIZE, - MAX_FRIN_SPILL * - sizeof(struct fr_desc)); - sc->frout_spill = nlna_config_spill(sc->base, - R_FROUT_SPILL_MEM_START_0, - R_FROUT_SPILL_MEM_START_1, - R_FROUT_SPILL_MEM_SIZE, - MAX_FROUT_SPILL * - sizeof(struct fr_desc)); - sc->class_0_spill = nlna_config_spill(sc->base, - R_CLASS0_SPILL_MEM_START_0, - R_CLASS0_SPILL_MEM_START_1, - R_CLASS0_SPILL_MEM_SIZE, - MAX_CLASS_0_SPILL * - sizeof(union rx_tx_desc)); - sc->class_1_spill = nlna_config_spill(sc->base, - R_CLASS1_SPILL_MEM_START_0, - R_CLASS1_SPILL_MEM_START_1, - R_CLASS1_SPILL_MEM_SIZE, - MAX_CLASS_1_SPILL * - sizeof(union rx_tx_desc)); - sc->class_2_spill = nlna_config_spill(sc->base, - R_CLASS2_SPILL_MEM_START_0, - R_CLASS2_SPILL_MEM_START_1, - R_CLASS2_SPILL_MEM_SIZE, - MAX_CLASS_2_SPILL * - sizeof(union rx_tx_desc)); - sc->class_3_spill = nlna_config_spill(sc->base, - R_CLASS3_SPILL_MEM_START_0, - R_CLASS3_SPILL_MEM_START_1, - R_CLASS3_SPILL_MEM_SIZE, - MAX_CLASS_3_SPILL * - sizeof(union rx_tx_desc)); -} - -/* Set the CPU buckets that receive packets from the NA class FIFOs. */ -static void -nlna_config_pde(struct nlna_softc *sc) -{ - uint64_t bucket_map; - uint32_t cpumask; - int i, cpu, bucket; - - cpumask = 0x1; -#ifdef SMP - /* - * nlna may be called before SMP start in a BOOTP/NFSROOT - * setup. we will distribute packets to other cpus only when - * the SMP is started. - */ - if (smp_started) - cpumask = xlr_hw_thread_mask; -#endif - bucket_map = 0; - for (i = 0; i < 32; i++) { - if (cpumask & (1 << i)) { - cpu = i; - /* use bucket 0 and 1 on every core for NA msgs */ - bucket = cpu/4 * 8; - bucket_map |= (3ULL << bucket); - } - } - - NLGE_WRITE(sc->base, R_PDE_CLASS_0, (bucket_map & 0xffffffff)); - NLGE_WRITE(sc->base, R_PDE_CLASS_0 + 1, ((bucket_map >> 32) & 0xffffffff)); - - NLGE_WRITE(sc->base, R_PDE_CLASS_1, (bucket_map & 0xffffffff)); - NLGE_WRITE(sc->base, R_PDE_CLASS_1 + 1, ((bucket_map >> 32) & 0xffffffff)); - - NLGE_WRITE(sc->base, R_PDE_CLASS_2, (bucket_map & 0xffffffff)); - NLGE_WRITE(sc->base, R_PDE_CLASS_2 + 1, ((bucket_map >> 32) & 0xffffffff)); - - NLGE_WRITE(sc->base, R_PDE_CLASS_3, (bucket_map & 0xffffffff)); - NLGE_WRITE(sc->base, R_PDE_CLASS_3 + 1, ((bucket_map >> 32) & 0xffffffff)); -} - -/* - * Update the network accelerator packet distribution engine for SMP. - * On bootup, we have just the boot hw thread handling all packets, on SMP - * start, we can start distributing packets across all the cores which are up. - */ -static void -nlna_smp_update_pde(void *dummy __unused) -{ - device_t iodi_dev; - struct nlna_softc *na_sc[XLR_MAX_NLNA]; - int i; - - printf("Updating packet distribution for SMP\n"); - - iodi_dev = devclass_get_device(devclass_find("iodi"), 0); - nlna_get_all_softc(iodi_dev, na_sc, XLR_MAX_NLNA); - - for (i = 0; i < XLR_MAX_NLNA; i++) { - if (na_sc[i] == NULL) - continue; - nlna_disable_ports(na_sc[i]); - nlna_config_pde(na_sc[i]); - nlna_config_translate_table(na_sc[i]); - nlna_enable_ports(na_sc[i]); - } -} - -SYSINIT(nlna_smp_update_pde, SI_SUB_SMP, SI_ORDER_ANY, nlna_smp_update_pde, - NULL); - -static void -nlna_config_translate_table(struct nlna_softc *sc) -{ - uint32_t cpu_mask; - uint32_t val; - int bkts[32]; /* one bucket is assumed for each cpu */ - int b1, b2, c1, c2, i, j, k; - int use_bkt; - - if (!flow_classification) - return; - - use_bkt = 1; - if (smp_started) - cpu_mask = xlr_hw_thread_mask; - else - return; - - printf("Using %s-based distribution\n", (use_bkt) ? "bucket" : "class"); - - j = 0; - for(i = 0; i < 32; i++) { - if ((1 << i) & cpu_mask){ - /* for each cpu, mark the 4+threadid bucket */ - bkts[j] = ((i / 4) * 8) + (i % 4); - j++; - } - } - - /*configure the 128 * 9 Translation table to send to available buckets*/ - k = 0; - c1 = 3; - c2 = 0; - for(i = 0; i < 64; i++) { - /* Get the next 2 pairs of (class, bucket): - (c1, b1), (c2, b2). - - c1, c2 limited to {0, 1, 2, 3} - i.e, the 4 classes defined by h/w - b1, b2 limited to { bkts[i], where 0 <= i < j} - i.e, the set of buckets computed in the - above loop. - */ - - c1 = (c1 + 1) & 3; - c2 = (c1 + 1) & 3; - b1 = bkts[k]; - k = (k + 1) % j; - b2 = bkts[k]; - k = (k + 1) % j; - PDEBUG("Translation table[%d] b1=%d b2=%d c1=%d c2=%d\n", - i, b1, b2, c1, c2); - val = ((c1 << 23) | (b1 << 17) | (use_bkt << 16) | - (c2 << 7) | (b2 << 1) | (use_bkt << 0)); - NLGE_WRITE(sc->base, R_TRANSLATETABLE + i, val); - c1 = c2; - } -} - -static void -nlna_config_parser(struct nlna_softc *sc) -{ - uint32_t val; - - /* - * Mark it as ETHERNET type. - */ - NLGE_WRITE(sc->base, R_L2TYPE_0, 0x01); - -#ifndef NLGE_HW_CHKSUM - if (!flow_classification) - return; -#endif - - /* Use 7bit CRChash for flow classification with 127 as CRC polynomial*/ - NLGE_WRITE(sc->base, R_PARSERCONFIGREG, ((0x7f << 8) | (1 << 1))); - - /* configure the parser : L2 Type is configured in the bootloader */ - /* extract IP: src, dest protocol */ - NLGE_WRITE(sc->base, R_L3CTABLE, - (9 << 20) | (1 << 19) | (1 << 18) | (0x01 << 16) | - (0x0800 << 0)); - NLGE_WRITE(sc->base, R_L3CTABLE + 1, - (9 << 25) | (1 << 21) | (12 << 14) | (4 << 10) | (16 << 4) | 4); -#ifdef NLGE_HW_CHKSUM - device_printf(sc->nlna_dev, "Enabled h/w support to compute TCP/IP" - " checksum\n"); -#endif - - /* Configure to extract SRC port and Dest port for TCP and UDP pkts */ - NLGE_WRITE(sc->base, R_L4CTABLE, 6); - NLGE_WRITE(sc->base, R_L4CTABLE + 2, 17); - val = ((0 << 21) | (2 << 17) | (2 << 11) | (2 << 7)); - NLGE_WRITE(sc->base, R_L4CTABLE + 1, val); - NLGE_WRITE(sc->base, R_L4CTABLE + 3, val); -} - -static void -nlna_config_classifier(struct nlna_softc *sc) -{ - int i; - - if (sc->mac_type == XLR_XGMII) { /* TBD: XGMII init sequence */ - /* xgmac translation table doesn't have sane values on reset */ - for (i = 0; i < 64; i++) - NLGE_WRITE(sc->base, R_TRANSLATETABLE + i, 0x0); - - /* - * use upper 7 bits of the parser extract to index the - * translate table - */ - NLGE_WRITE(sc->base, R_PARSERCONFIGREG, 0x0); - } -} - -/* - * Complete a bunch of h/w register initializations that are common for all the - * ports controlled by a NA. - */ -static void -nlna_config_common(struct nlna_softc *sc) -{ - struct xlr_gmac_block_t *block_info; - struct stn_cc *gmac_cc_config; - int i; - - block_info = device_get_ivars(sc->nlna_dev); - gmac_cc_config = block_info->credit_config; - for (i = 0; i < MAX_NUM_MSGRNG_STN_CC; i++) { - NLGE_WRITE(sc->base, R_CC_CPU0_0 + i, - gmac_cc_config->counters[i >> 3][i & 0x07]); - } - - NLGE_WRITE(sc->base, R_MSG_TX_THRESHOLD, 3); - - NLGE_WRITE(sc->base, R_DMACR0, 0xffffffff); - NLGE_WRITE(sc->base, R_DMACR1, 0xffffffff); - NLGE_WRITE(sc->base, R_DMACR2, 0xffffffff); - NLGE_WRITE(sc->base, R_DMACR3, 0xffffffff); - NLGE_WRITE(sc->base, R_FREEQCARVE, 0); - - nlna_media_specific_config(sc); -} - -static void -nlna_media_specific_config(struct nlna_softc *sc) -{ - struct bucket_size *bucket_sizes; - - bucket_sizes = xlr_board_info.bucket_sizes; - switch (sc->mac_type) { - case XLR_RGMII: - case XLR_SGMII: - case XLR_XAUI: - NLGE_WRITE(sc->base, R_GMAC_JFR0_BUCKET_SIZE, - bucket_sizes->bucket[MSGRNG_STNID_GMACJFR_0]); - NLGE_WRITE(sc->base, R_GMAC_RFR0_BUCKET_SIZE, - bucket_sizes->bucket[MSGRNG_STNID_GMACRFR_0]); - NLGE_WRITE(sc->base, R_GMAC_JFR1_BUCKET_SIZE, - bucket_sizes->bucket[MSGRNG_STNID_GMACJFR_1]); - NLGE_WRITE(sc->base, R_GMAC_RFR1_BUCKET_SIZE, - bucket_sizes->bucket[MSGRNG_STNID_GMACRFR_1]); - - if (sc->mac_type == XLR_XAUI) { - NLGE_WRITE(sc->base, R_TXDATAFIFO0, (224 << 16)); - } - break; - - case XLR_XGMII: - NLGE_WRITE(sc->base, R_XGS_RFR_BUCKET_SIZE, - bucket_sizes->bucket[sc->rfrbucket]); - - default: - break; - } -} - -static void -nlna_reset_ports(struct nlna_softc *sc, struct xlr_gmac_block_t *blk) -{ - xlr_reg_t *addr; - int i; - uint32_t rx_ctrl; - - /* Refer Section 13.9.3 in the PRM for the reset sequence */ - - for (i = 0; i < sc->num_ports; i++) { - addr = xlr_io_mmio(blk->gmac_port[i].base_addr); - - /* 1. Reset RxEnable in MAC_CONFIG */ - switch (sc->mac_type) { - case XLR_RGMII: - case XLR_SGMII: - NLGE_UPDATE(addr, R_MAC_CONFIG_1, 0, - (1 << O_MAC_CONFIG_1__rxen)); - break; - case XLR_XAUI: - case XLR_XGMII: - NLGE_UPDATE(addr, R_RX_CONTROL, 0, - (1 << O_RX_CONTROL__RxEnable)); - break; - default: - printf("Error: Unsupported port_type=%d\n", - sc->mac_type); - } - - /* 1.1 Wait for RxControl.RxHalt to be set */ - do { - rx_ctrl = NLGE_READ(addr, R_RX_CONTROL); - } while (!(rx_ctrl & 0x2)); - - /* 2. Set the soft reset bit in RxControl */ - NLGE_UPDATE(addr, R_RX_CONTROL, (1 << O_RX_CONTROL__SoftReset), - (1 << O_RX_CONTROL__SoftReset)); - - /* 2.1 Wait for RxControl.SoftResetDone to be set */ - do { - rx_ctrl = NLGE_READ(addr, R_RX_CONTROL); - } while (!(rx_ctrl & 0x8)); - - /* 3. Clear the soft reset bit in RxControl */ - NLGE_UPDATE(addr, R_RX_CONTROL, 0, - (1 << O_RX_CONTROL__SoftReset)); - - /* Turn off tx/rx on the port. */ - NLGE_UPDATE(addr, R_RX_CONTROL, 0, - (1 << O_RX_CONTROL__RxEnable)); - NLGE_UPDATE(addr, R_TX_CONTROL, 0, - (1 << O_TX_CONTROL__TxEnable)); - } -} - -static void -nlna_disable_ports(struct nlna_softc *sc) -{ - int i; - - for (i = 0; i < sc->num_ports; i++) { - if (sc->child_sc[i] != NULL) - nlge_port_disable(sc->child_sc[i]); - } -} - -static void -nlna_enable_ports(struct nlna_softc *sc) -{ - device_t nlge_dev, *devlist; - struct nlge_softc *port_sc; - int i, numdevs; - - device_get_children(sc->nlna_dev, &devlist, &numdevs); - for (i = 0; i < numdevs; i++) { - nlge_dev = devlist[i]; - if (nlge_dev == NULL) - continue; - port_sc = device_get_softc(nlge_dev); - if (port_sc->nlge_if->if_drv_flags & IFF_DRV_RUNNING) - nlge_port_enable(port_sc); - } - free(devlist, M_TEMP); -} - -static void -nlna_get_all_softc(device_t iodi_dev, struct nlna_softc **sc_vec, - uint32_t vec_sz) -{ - device_t na_dev; - int i; - - for (i = 0; i < vec_sz; i++) { - sc_vec[i] = NULL; - na_dev = device_find_child(iodi_dev, "nlna", i); - if (na_dev != NULL) - sc_vec[i] = device_get_softc(na_dev); - } -} - -static void -nlge_port_disable(struct nlge_softc *sc) -{ - struct ifnet *ifp; - xlr_reg_t *base; - uint32_t rd; - int id, port_type; - - id = sc->id; - port_type = sc->port_type; - base = sc->base; - ifp = sc->nlge_if; - - NLGE_UPDATE(base, R_RX_CONTROL, 0x0, 1 << O_RX_CONTROL__RxEnable); - do { - rd = NLGE_READ(base, R_RX_CONTROL); - } while (!(rd & (1 << O_RX_CONTROL__RxHalt))); - - NLGE_UPDATE(base, R_TX_CONTROL, 0, 1 << O_TX_CONTROL__TxEnable); - do { - rd = NLGE_READ(base, R_TX_CONTROL); - } while (!(rd & (1 << O_TX_CONTROL__TxIdle))); - - switch (port_type) { - case XLR_RGMII: - case XLR_SGMII: - NLGE_UPDATE(base, R_MAC_CONFIG_1, 0, - ((1 << O_MAC_CONFIG_1__rxen) | - (1 << O_MAC_CONFIG_1__txen))); - break; - case XLR_XGMII: - case XLR_XAUI: - NLGE_UPDATE(base, R_XGMAC_CONFIG_1, 0, - ((1 << O_XGMAC_CONFIG_1__hsttfen) | - (1 << O_XGMAC_CONFIG_1__hstrfen))); - break; - default: - panic("Unknown MAC type on port %d\n", id); - } - - if (ifp) { - ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); - } -} - -static void -nlge_port_enable(struct nlge_softc *sc) -{ - struct xlr_gmac_port *self; - xlr_reg_t *base; - - base = sc->base; - self = device_get_ivars(sc->nlge_dev); - if (xlr_board_info.is_xls && sc->port_type == XLR_RGMII) - NLGE_UPDATE(base, R_RX_CONTROL, (1 << O_RX_CONTROL__RGMII), - (1 << O_RX_CONTROL__RGMII)); - - NLGE_UPDATE(base, R_RX_CONTROL, (1 << O_RX_CONTROL__RxEnable), - (1 << O_RX_CONTROL__RxEnable)); - NLGE_UPDATE(base, R_TX_CONTROL, - (1 << O_TX_CONTROL__TxEnable | RGE_TX_THRESHOLD_BYTES), - (1 << O_TX_CONTROL__TxEnable | 0x3fff)); - switch (sc->port_type) { - case XLR_RGMII: - case XLR_SGMII: - NLGE_UPDATE(base, R_MAC_CONFIG_1, - ((1 << O_MAC_CONFIG_1__rxen) | (1 << O_MAC_CONFIG_1__txen)), - ((1 << O_MAC_CONFIG_1__rxen) | (1 << O_MAC_CONFIG_1__txen))); - break; - case XLR_XGMII: - case XLR_XAUI: - NLGE_UPDATE(base, R_XGMAC_CONFIG_1, - ((1 << O_XGMAC_CONFIG_1__hsttfen) | (1 << O_XGMAC_CONFIG_1__hstrfen)), - ((1 << O_XGMAC_CONFIG_1__hsttfen) | (1 << O_XGMAC_CONFIG_1__hstrfen))); - break; - default: - panic("Unknown MAC type on port %d\n", sc->id); - } -} - -static void -nlge_mac_set_rx_mode(struct nlge_softc *sc) -{ - uint32_t regval; - - regval = NLGE_READ(sc->base, R_MAC_FILTER_CONFIG); - - if (sc->if_flags & IFF_PROMISC) { - regval |= (1 << O_MAC_FILTER_CONFIG__BROADCAST_EN) | - (1 << O_MAC_FILTER_CONFIG__PAUSE_FRAME_EN) | - (1 << O_MAC_FILTER_CONFIG__ALL_MCAST_EN) | - (1 << O_MAC_FILTER_CONFIG__ALL_UCAST_EN); - } else { - regval &= ~((1 << O_MAC_FILTER_CONFIG__PAUSE_FRAME_EN) | - (1 << O_MAC_FILTER_CONFIG__ALL_UCAST_EN)); - } - - NLGE_WRITE(sc->base, R_MAC_FILTER_CONFIG, regval); -} - -static void -nlge_sgmii_init(struct nlge_softc *sc) -{ - xlr_reg_t *mmio_gpio; - int phy; - - if (sc->port_type != XLR_SGMII) - return; - - nlge_mii_write_internal(sc->serdes_addr, 26, 0, 0x6DB0); - nlge_mii_write_internal(sc->serdes_addr, 26, 1, 0xFFFF); - nlge_mii_write_internal(sc->serdes_addr, 26, 2, 0xB6D0); - nlge_mii_write_internal(sc->serdes_addr, 26, 3, 0x00FF); - nlge_mii_write_internal(sc->serdes_addr, 26, 4, 0x0000); - nlge_mii_write_internal(sc->serdes_addr, 26, 5, 0x0000); - nlge_mii_write_internal(sc->serdes_addr, 26, 6, 0x0005); - nlge_mii_write_internal(sc->serdes_addr, 26, 7, 0x0001); - nlge_mii_write_internal(sc->serdes_addr, 26, 8, 0x0000); - nlge_mii_write_internal(sc->serdes_addr, 26, 9, 0x0000); - nlge_mii_write_internal(sc->serdes_addr, 26,10, 0x0000); - - /* program GPIO values for serdes init parameters */ - DELAY(100); - mmio_gpio = xlr_io_mmio(XLR_IO_GPIO_OFFSET); - xlr_write_reg(mmio_gpio, 0x20, 0x7e6802); - xlr_write_reg(mmio_gpio, 0x10, 0x7104); - DELAY(100); - - /* - * This kludge is needed to setup serdes (?) clock correctly on some - * XLS boards - */ - if ((xlr_boot1_info.board_major_version == RMI_XLR_BOARD_ARIZONA_XI || - xlr_boot1_info.board_major_version == RMI_XLR_BOARD_ARIZONA_XII) && - xlr_boot1_info.board_minor_version == 4) { - /* use 125 Mhz instead of 156.25Mhz ref clock */ - DELAY(100); - xlr_write_reg(mmio_gpio, 0x10, 0x7103); - xlr_write_reg(mmio_gpio, 0x21, 0x7103); - DELAY(100); - } - - /* enable autoneg - more magic */ - phy = sc->phy_addr % 4 + 27; - nlge_mii_write_internal(sc->pcs_addr, phy, 0, 0x1000); - DELAY(100000); - nlge_mii_write_internal(sc->pcs_addr, phy, 0, 0x0200); - DELAY(100000); -} - -static void -nlge_intr(void *arg) -{ - struct nlge_port_set *pset; - struct nlge_softc *sc; - struct nlge_softc *port_sc; - xlr_reg_t *base; - uint32_t intreg; - uint32_t intr_status; - int i; - - sc = arg; - if (sc == NULL) { - printf("warning: No port registered for interrupt\n"); - return; - } - base = sc->base; - - intreg = NLGE_READ(base, R_INTREG); - if (intreg & (1 << O_INTREG__MDInt)) { - pset = sc->mdio_pset; - if (pset == NULL) { - printf("warning: No ports for MDIO interrupt\n"); - return; - } - for (i = 0; i < pset->vec_sz; i++) { - port_sc = pset->port_vec[i]; - - if (port_sc == NULL) - continue; - - /* Ack phy interrupt - clear on read*/ - intr_status = nlge_mii_read_internal(port_sc->mii_base, - port_sc->phy_addr, 26); - PDEBUG("Phy_%d: int_status=0x%08x\n", port_sc->phy_addr, - intr_status); - - if (!(intr_status & 0x8000)) { - /* no interrupt for this port */ - continue; - } - - if (intr_status & 0x2410) { - /* update link status for port */ - nlge_gmac_config_speed(port_sc, 1); - } else { - printf("%s: Unsupported phy interrupt" - " (0x%08x)\n", - device_get_nameunit(port_sc->nlge_dev), - intr_status); - } - } - } - - /* Clear the NA interrupt */ - xlr_write_reg(base, R_INTREG, 0xffffffff); - - return; -} - -static int -nlge_irq_init(struct nlge_softc *sc) -{ - struct resource irq_res; - struct nlna_softc *na_sc; - struct xlr_gmac_block_t *block_info; - device_t na_dev; - int ret; - int irq_num; - - na_dev = device_get_parent(sc->nlge_dev); - block_info = device_get_ivars(na_dev); - - irq_num = block_info->baseirq + sc->instance; - irq_res.__r_i = (struct resource_i *)(intptr_t) (irq_num); - ret = bus_setup_intr(sc->nlge_dev, &irq_res, - INTR_TYPE_NET | INTR_MPSAFE, NULL, nlge_intr, sc, NULL); - if (ret) { - nlge_detach(sc->nlge_dev); - device_printf(sc->nlge_dev, "couldn't set up irq: error=%d\n", - ret); - return (ENXIO); - } - PDEBUG("Setup intr for dev=%s, irq=%d\n", - device_get_nameunit(sc->nlge_dev), irq_num); - - if (sc->instance == 0) { - na_sc = device_get_softc(na_dev); - sc->mdio_pset = &na_sc->mdio_set; - } - return (0); -} - -static void -nlge_irq_fini(struct nlge_softc *sc) -{ -} - -static void -nlge_hw_init(struct nlge_softc *sc) -{ - struct xlr_gmac_port *port_info; - xlr_reg_t *base; - - base = sc->base; - port_info = device_get_ivars(sc->nlge_dev); - sc->tx_bucket_id = port_info->tx_bucket_id; - - /* each packet buffer is 1536 bytes */ - NLGE_WRITE(base, R_DESC_PACK_CTRL, - (1 << O_DESC_PACK_CTRL__MaxEntry) | -#ifdef NLGE_HW_CHKSUM - (1 << O_DESC_PACK_CTRL__PrePadEnable) | -#endif - (MAX_FRAME_SIZE << O_DESC_PACK_CTRL__RegularSize)); - NLGE_WRITE(base, R_STATCTRL, ((1 << O_STATCTRL__Sten) | - (1 << O_STATCTRL__ClrCnt))); - NLGE_WRITE(base, R_L2ALLOCCTRL, 0xffffffff); - NLGE_WRITE(base, R_INTMASK, 0); - nlge_set_mac_addr(sc); - nlge_media_specific_init(sc); -} - -static void -nlge_sc_init(struct nlge_softc *sc, device_t dev, - struct xlr_gmac_port *port_info) -{ - memset(sc, 0, sizeof(*sc)); - sc->nlge_dev = dev; - sc->id = device_get_unit(dev); - nlge_set_port_attribs(sc, port_info); -} - -static void -nlge_media_specific_init(struct nlge_softc *sc) -{ - struct mii_data *media; - struct bucket_size *bucket_sizes; - - bucket_sizes = xlr_board_info.bucket_sizes; - switch (sc->port_type) { - case XLR_RGMII: - case XLR_SGMII: - case XLR_XAUI: - NLGE_UPDATE(sc->base, R_DESC_PACK_CTRL, - (BYTE_OFFSET << O_DESC_PACK_CTRL__ByteOffset), - (W_DESC_PACK_CTRL__ByteOffset << - O_DESC_PACK_CTRL__ByteOffset)); - NLGE_WRITE(sc->base, R_GMAC_TX0_BUCKET_SIZE + sc->instance, - bucket_sizes->bucket[sc->tx_bucket_id]); - if (sc->port_type != XLR_XAUI) { - nlge_gmac_config_speed(sc, 1); - if (sc->mii_bus) { - media = (struct mii_data *)device_get_softc( - sc->mii_bus); - } - } - break; - - case XLR_XGMII: - NLGE_WRITE(sc->base, R_BYTEOFFSET0, 0x2); - NLGE_WRITE(sc->base, R_XGMACPADCALIBRATION, 0x30); - NLGE_WRITE(sc->base, R_XGS_TX0_BUCKET_SIZE, - bucket_sizes->bucket[sc->tx_bucket_id]); - break; - default: - break; - } -} - -/* - * Read the MAC address from the XLR boot registers. All port addresses - * are identical except for the lowest octet. - */ -static void -nlge_read_mac_addr(struct nlge_softc *sc) -{ - int i, j; - - for (i = 0, j = 40; i < ETHER_ADDR_LEN && j >= 0; i++, j-= 8) - sc->dev_addr[i] = (xlr_boot1_info.mac_addr >> j) & 0xff; - - sc->dev_addr[i - 1] += sc->id; /* last octet is port-specific */ -} - -/* - * Write the MAC address to the XLR MAC port. Also, set the address - * masks and MAC filter configuration. - */ -static void -nlge_set_mac_addr(struct nlge_softc *sc) -{ - NLGE_WRITE(sc->base, R_MAC_ADDR0, - ((sc->dev_addr[5] << 24) | (sc->dev_addr[4] << 16) | - (sc->dev_addr[3] << 8) | (sc->dev_addr[2]))); - NLGE_WRITE(sc->base, R_MAC_ADDR0 + 1, - ((sc->dev_addr[1] << 24) | (sc-> dev_addr[0] << 16))); - - NLGE_WRITE(sc->base, R_MAC_ADDR_MASK2, 0xffffffff); - NLGE_WRITE(sc->base, R_MAC_ADDR_MASK2 + 1, 0xffffffff); - NLGE_WRITE(sc->base, R_MAC_ADDR_MASK3, 0xffffffff); - NLGE_WRITE(sc->base, R_MAC_ADDR_MASK3 + 1, 0xffffffff); - - NLGE_WRITE(sc->base, R_MAC_FILTER_CONFIG, - (1 << O_MAC_FILTER_CONFIG__BROADCAST_EN) | - (1 << O_MAC_FILTER_CONFIG__ALL_MCAST_EN) | - (1 << O_MAC_FILTER_CONFIG__MAC_ADDR0_VALID)); - - if (sc->port_type == XLR_RGMII || sc->port_type == XLR_SGMII) { - NLGE_UPDATE(sc->base, R_IPG_IFG, MAC_B2B_IPG, 0x7f); - } -} - -static int -nlge_if_init(struct nlge_softc *sc) -{ - struct ifnet *ifp; - device_t dev; - int error; - - error = 0; - dev = sc->nlge_dev; - NLGE_LOCK_INIT(sc, device_get_nameunit(dev)); - - ifp = sc->nlge_if = if_alloc(IFT_ETHER); - if (ifp == NULL) { - device_printf(dev, "can not if_alloc()\n"); - error = ENOSPC; - goto fail; - } - ifp->if_softc = sc; - if_initname(ifp, device_get_name(dev), device_get_unit(dev)); - ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; - ifp->if_capabilities = 0; - ifp->if_capenable = ifp->if_capabilities; - ifp->if_ioctl = nlge_ioctl; - ifp->if_init = nlge_init; - ifp->if_hwassist = 0; - ifp->if_snd.ifq_drv_maxlen = RGE_TX_Q_SIZE; - IFQ_SET_MAXLEN(&ifp->if_snd, ifp->if_snd.ifq_drv_maxlen); - IFQ_SET_READY(&ifp->if_snd); - - ifmedia_init(&sc->nlge_mii.mii_media, 0, nlge_mediachange, - nlge_mediastatus); - ifmedia_add(&sc->nlge_mii.mii_media, IFM_ETHER | IFM_AUTO, 0, NULL); - ifmedia_set(&sc->nlge_mii.mii_media, IFM_ETHER | IFM_AUTO); - sc->nlge_mii.mii_media.ifm_media = sc->nlge_mii.mii_media.ifm_cur->ifm_media; - nlge_read_mac_addr(sc); - - ether_ifattach(ifp, sc->dev_addr); - - /* override if_transmit : per ifnet(9), do it after if_attach */ - ifp->if_transmit = nlge_tx; - -fail: - return (error); -} - -static void -nlge_mii_init(device_t dev, struct nlge_softc *sc) -{ - int error; - - if (sc->port_type != XLR_XAUI && sc->port_type != XLR_XGMII) { - NLGE_WRITE(sc->mii_base, R_MII_MGMT_CONFIG, 0x07); - } - error = mii_attach(dev, &sc->mii_bus, sc->nlge_if, nlge_mediachange, - nlge_mediastatus, BMSR_DEFCAPMASK, sc->phy_addr, MII_OFFSET_ANY, - 0); - if (error) { - device_printf(dev, "attaching PHYs failed\n"); - sc->mii_bus = NULL; - } - if (sc->mii_bus != NULL) { - /* - * Enable all MDIO interrupts in the phy. RX_ER bit seems to get - * set about every 1 sec in GigE mode, ignore it for now... - */ - nlge_mii_write_internal(sc->mii_base, sc->phy_addr, 25, - 0xfffffffe); - } -} - -/* - * Read a PHY register. - * - * Input parameters: - * mii_base - Base address of MII - * phyaddr - PHY's address - * regidx = index of register to read - * - * Return value: - * value read, or 0 if an error occurred. - */ - -static int -nlge_mii_read_internal(xlr_reg_t *mii_base, int phyaddr, int regidx) -{ - int i, val; - - /* setup the phy reg to be used */ - NLGE_WRITE(mii_base, R_MII_MGMT_ADDRESS, - (phyaddr << 8) | (regidx << 0)); - /* Issue the read command */ - NLGE_WRITE(mii_base, R_MII_MGMT_COMMAND, - (1 << O_MII_MGMT_COMMAND__rstat)); - - /* poll for the read cycle to complete */ - for (i = 0; i < PHY_STATUS_RETRIES; i++) { - if (NLGE_READ(mii_base, R_MII_MGMT_INDICATORS) == 0) - break; - } - - /* clear the read cycle */ - NLGE_WRITE(mii_base, R_MII_MGMT_COMMAND, 0); - - if (i == PHY_STATUS_RETRIES) { - return (0xffffffff); - } - - val = NLGE_READ(mii_base, R_MII_MGMT_STATUS); - - return (val); -} - -/* - * Write a value to a PHY register. - * - * Input parameters: - * mii_base - Base address of MII - * phyaddr - PHY to use - * regidx - register within the PHY - * regval - data to write to register - * - * Return value: - * nothing - */ -static void -nlge_mii_write_internal(xlr_reg_t *mii_base, int phyaddr, int regidx, - int regval) -{ - int i; - - NLGE_WRITE(mii_base, R_MII_MGMT_ADDRESS, - (phyaddr << 8) | (regidx << 0)); - - /* Write the data which starts the write cycle */ - NLGE_WRITE(mii_base, R_MII_MGMT_WRITE_DATA, regval); - - /* poll for the write cycle to complete */ - for (i = 0; i < PHY_STATUS_RETRIES; i++) { - if (NLGE_READ(mii_base, R_MII_MGMT_INDICATORS) == 0) - break; - } -} - -/* - * Function to optimize the use of p2d descriptors for the given PDU. - * As it is on the fast-path (called during packet transmission), it - * described in more detail than the initialization functions. - * - * Input: mbuf chain (MC), pointer to fmn message - * Input constraints: None - * Output: FMN message to transmit the data in MC - * Return values: 0 - success - * 1 - MC cannot be handled (see Limitations below) - * 2 - MC cannot be handled presently (maybe worth re-trying) - * Other output: Number of entries filled in the FMN message - * - * Output structure/constraints: - * 1. Max 3 p2d's + 1 zero-len (ZL) p2d with virtual address of MC. - * 2. 3 p2d's + 1 p2p with max 14 p2d's (ZL p2d not required in this case). - * 3. Each p2d points to physically contiguous chunk of data (subject to - * entire MC requiring max 17 p2d's). - * Limitations: - * 1. MC's that require more than 17 p2d's are not handled. - * Benefits: MC's that require <= 3 p2d's avoid the overhead of allocating - * the p2p structure. Small packets (which typically give low - * performance) are expected to have a small MC that takes - * advantage of this. - */ -static int -prepare_fmn_message(struct nlge_softc *sc, struct msgrng_msg *fmn_msg, - uint32_t *n_entries, struct mbuf *mbuf_chain, uint64_t fb_stn_id, - struct nlge_tx_desc **tx_desc) -{ - struct mbuf *m; - struct nlge_tx_desc *p2p; - uint64_t *cur_p2d; - uint64_t fbpaddr; - vm_offset_t buf; - vm_paddr_t paddr; - int msg_sz, p2p_sz, len, frag_sz; - /* Num entries per FMN msg is 4 for XLR/XLS */ - const int FMN_SZ = sizeof(*fmn_msg) / sizeof(uint64_t); - - msg_sz = p2p_sz = 0; - p2p = NULL; - cur_p2d = &fmn_msg->msg0; - - for (m = mbuf_chain; m != NULL; m = m->m_next) { - buf = (vm_offset_t) m->m_data; - len = m->m_len; - - while (len) { - if (msg_sz == (FMN_SZ - 1)) { - p2p = uma_zalloc(nl_tx_desc_zone, M_NOWAIT); - if (p2p == NULL) { - return (2); - } - /* - * Save the virtual address in the descriptor, - * it makes freeing easy. - */ - p2p->frag[XLR_MAX_TX_FRAGS] = - (uint64_t)(vm_offset_t)p2p; - cur_p2d = &p2p->frag[0]; - } else if (msg_sz == (FMN_SZ - 2 + XLR_MAX_TX_FRAGS)) { - uma_zfree(nl_tx_desc_zone, p2p); - return (1); - } - paddr = vtophys(buf); - frag_sz = PAGE_SIZE - (buf & PAGE_MASK); - if (len < frag_sz) - frag_sz = len; - *cur_p2d++ = (127ULL << 54) | ((uint64_t)frag_sz << 40) - | paddr; - msg_sz++; - if (p2p != NULL) - p2p_sz++; - len -= frag_sz; - buf += frag_sz; - } - } - - if (msg_sz == 0) { - printf("Zero-length mbuf chain ??\n"); - *n_entries = msg_sz ; - return (0); - } - - /* set eop in most-recent p2d */ - cur_p2d[-1] |= (1ULL << 63); - -#ifdef __mips_n64 - /* - * On n64, we cannot store our mbuf pointer(64 bit) in the freeback - * message (40bit available), so we put the mbuf in m_nextpkt and - * use the physical addr of that in freeback message. - */ - mbuf_chain->m_nextpkt = mbuf_chain; - fbpaddr = vtophys(&mbuf_chain->m_nextpkt); -#else - /* Careful, don't sign extend when going to 64bit */ - fbpaddr = (uint64_t)(uintptr_t)mbuf_chain; -#endif - *cur_p2d = (1ULL << 63) | ((uint64_t)fb_stn_id << 54) | fbpaddr; - *tx_desc = p2p; - - if (p2p != NULL) { - paddr = vtophys(p2p); - p2p_sz++; - fmn_msg->msg3 = (1ULL << 62) | ((uint64_t)fb_stn_id << 54) | - ((uint64_t)(p2p_sz * 8) << 40) | paddr; - *n_entries = FMN_SZ; - } else { - *n_entries = msg_sz + 1; - } - - return (0); -} - -static int -send_fmn_msg_tx(struct nlge_softc *sc, struct msgrng_msg *msg, - uint32_t n_entries) -{ - uint32_t msgrng_flags; - int ret; - int i = 0; - - do { - msgrng_flags = msgrng_access_enable(); - ret = message_send(n_entries, MSGRNG_CODE_MAC, - sc->tx_bucket_id, msg); - msgrng_restore(msgrng_flags); - if (ret == 0) - return (0); - i++; - } while (i < 100000); - - device_printf(sc->nlge_dev, "Too many credit fails in tx path\n"); - - return (1); -} - -static void -release_tx_desc(vm_paddr_t paddr) -{ - struct nlge_tx_desc *tx_desc; - uint32_t sr; - uint64_t vaddr; - - paddr += (XLR_MAX_TX_FRAGS * sizeof(uint64_t)); - sr = xlr_enable_kx(); - vaddr = xlr_paddr_ld(paddr); - xlr_restore_kx(sr); - - tx_desc = (struct nlge_tx_desc*)(intptr_t)vaddr; - uma_zfree(nl_tx_desc_zone, tx_desc); -} - -static void * -get_buf(void) -{ - struct mbuf *m_new; - uint64_t *md; -#ifdef INVARIANTS - vm_paddr_t temp1, temp2; -#endif - - if ((m_new = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR)) == NULL) - return (NULL); - m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; - m_adj(m_new, XLR_CACHELINE_SIZE - ((uintptr_t)m_new->m_data & 0x1f)); - md = (uint64_t *)m_new->m_data; - md[0] = (intptr_t)m_new; /* Back Ptr */ - md[1] = 0xf00bad; - m_adj(m_new, XLR_CACHELINE_SIZE); - -#ifdef INVARIANTS - temp1 = vtophys((vm_offset_t) m_new->m_data); - temp2 = vtophys((vm_offset_t) m_new->m_data + 1536); - if ((temp1 + 1536) != temp2) - panic("ALLOCED BUFFER IS NOT CONTIGUOUS\n"); -#endif - - return ((void *)m_new->m_data); -} - -static int -nlge_gmac_config_speed(struct nlge_softc *sc, int quick) -{ - struct mii_data *md; - xlr_reg_t *mmio; - int bmsr, n_tries, max_tries; - int core_ctl[] = { 0x2, 0x1, 0x0, 0x1 }; - int sgmii_speed[] = { SGMII_SPEED_10, - SGMII_SPEED_100, - SGMII_SPEED_1000, - SGMII_SPEED_100 }; /* default to 100Mbps */ - char *speed_str[] = { "10", - "100", - "1000", - "unknown, defaulting to 100" }; - int link_state = LINK_STATE_DOWN; - - if (sc->port_type == XLR_XAUI || sc->port_type == XLR_XGMII) - return 0; - - md = NULL; - mmio = sc->base; - if (sc->mii_base != NULL) { - max_tries = (quick == 1) ? 100 : 4000; - bmsr = 0; - for (n_tries = 0; n_tries < max_tries; n_tries++) { - bmsr = nlge_mii_read_internal(sc->mii_base, - sc->phy_addr, MII_BMSR); - if ((bmsr & BMSR_ACOMP) && (bmsr & BMSR_LINK)) - break; /* Auto-negotiation is complete - and link is up */ - DELAY(1000); - } - bmsr &= BMSR_LINK; - sc->link = (bmsr == 0) ? xlr_mac_link_down : xlr_mac_link_up; - sc->speed = nlge_mii_read_internal(sc->mii_base, sc->phy_addr, 28); - sc->speed = (sc->speed >> 3) & 0x03; - if (sc->link == xlr_mac_link_up) { - link_state = LINK_STATE_UP; - nlge_sgmii_init(sc); - } - if (sc->mii_bus) - md = (struct mii_data *)device_get_softc(sc->mii_bus); - } - - if (sc->port_type != XLR_RGMII) - NLGE_WRITE(mmio, R_INTERFACE_CONTROL, sgmii_speed[sc->speed]); - if (sc->speed == xlr_mac_speed_10 || sc->speed == xlr_mac_speed_100 || - sc->speed == xlr_mac_speed_rsvd) { - NLGE_WRITE(mmio, R_MAC_CONFIG_2, 0x7117); - } else if (sc->speed == xlr_mac_speed_1000) { - NLGE_WRITE(mmio, R_MAC_CONFIG_2, 0x7217); - if (md != NULL) { - ifmedia_set(&md->mii_media, IFM_MAKEWORD(IFM_ETHER, - IFM_1000_T, IFM_FDX, md->mii_instance)); - } - } - NLGE_WRITE(mmio, R_CORECONTROL, core_ctl[sc->speed]); - if_link_state_change(sc->nlge_if, link_state); - printf("%s: [%sMbps]\n", device_get_nameunit(sc->nlge_dev), - speed_str[sc->speed]); - - return (0); -} - -/* - * This function is called for each port that was added to the device tree - * and it initializes the following port attributes: - * - type - * - base (base address to access port-specific registers) - * - mii_base - * - phy_addr - */ -static void -nlge_set_port_attribs(struct nlge_softc *sc, - struct xlr_gmac_port *port_info) -{ - sc->instance = port_info->instance % 4; /* TBD: will not work for SPI-4 */ - sc->port_type = port_info->type; - sc->base = xlr_io_mmio(port_info->base_addr); - sc->mii_base = xlr_io_mmio(port_info->mii_addr); - if (port_info->pcs_addr != 0) - sc->pcs_addr = xlr_io_mmio(port_info->pcs_addr); - if (port_info->serdes_addr != 0) - sc->serdes_addr = xlr_io_mmio(port_info->serdes_addr); - sc->phy_addr = port_info->phy_addr; - - PDEBUG("Port%d: base=%p, mii_base=%p, phy_addr=%d\n", sc->id, sc->base, - sc->mii_base, sc->phy_addr); -} - -/* ------------------------------------------------------------------------ */ - -/* Debug dump functions */ - -#ifdef DEBUG - -static void -dump_reg(xlr_reg_t *base, uint32_t offset, char *name) -{ - int val; - - val = NLGE_READ(base, offset); - printf("%-30s: 0x%8x 0x%8x\n", name, offset, val); -} - -#define STRINGIFY(x) #x - -static void -dump_na_registers(xlr_reg_t *base_addr, int port_id) -{ - PDEBUG("Register dump for NA (of port=%d)\n", port_id); - dump_reg(base_addr, R_PARSERCONFIGREG, STRINGIFY(R_PARSERCONFIGREG)); - PDEBUG("Tx bucket sizes\n"); - dump_reg(base_addr, R_GMAC_JFR0_BUCKET_SIZE, - STRINGIFY(R_GMAC_JFR0_BUCKET_SIZE)); - dump_reg(base_addr, R_GMAC_RFR0_BUCKET_SIZE, - STRINGIFY(R_GMAC_RFR0_BUCKET_SIZE)); - dump_reg(base_addr, R_GMAC_TX0_BUCKET_SIZE, - STRINGIFY(R_GMAC_TX0_BUCKET_SIZE)); - dump_reg(base_addr, R_GMAC_TX1_BUCKET_SIZE, - STRINGIFY(R_GMAC_TX1_BUCKET_SIZE)); - dump_reg(base_addr, R_GMAC_TX2_BUCKET_SIZE, - STRINGIFY(R_GMAC_TX2_BUCKET_SIZE)); - dump_reg(base_addr, R_GMAC_TX3_BUCKET_SIZE, - STRINGIFY(R_GMAC_TX3_BUCKET_SIZE)); - dump_reg(base_addr, R_GMAC_JFR1_BUCKET_SIZE, - STRINGIFY(R_GMAC_JFR1_BUCKET_SIZE)); - dump_reg(base_addr, R_GMAC_RFR1_BUCKET_SIZE, - STRINGIFY(R_GMAC_RFR1_BUCKET_SIZE)); - dump_reg(base_addr, R_TXDATAFIFO0, STRINGIFY(R_TXDATAFIFO0)); - dump_reg(base_addr, R_TXDATAFIFO1, STRINGIFY(R_TXDATAFIFO1)); -} - -static void -dump_gmac_registers(struct nlge_softc *sc) -{ - xlr_reg_t *base_addr = sc->base; - int port_id = sc->instance; - - PDEBUG("Register dump for port=%d\n", port_id); - if (sc->port_type == XLR_RGMII || sc->port_type == XLR_SGMII) { - dump_reg(base_addr, R_MAC_CONFIG_1, STRINGIFY(R_MAC_CONFIG_1)); - dump_reg(base_addr, R_MAC_CONFIG_2, STRINGIFY(R_MAC_CONFIG_2)); - dump_reg(base_addr, R_IPG_IFG, STRINGIFY(R_IPG_IFG)); - dump_reg(base_addr, R_HALF_DUPLEX, STRINGIFY(R_HALF_DUPLEX)); - dump_reg(base_addr, R_MAXIMUM_FRAME_LENGTH, - STRINGIFY(R_MAXIMUM_FRAME_LENGTH)); - dump_reg(base_addr, R_TEST, STRINGIFY(R_TEST)); - dump_reg(base_addr, R_MII_MGMT_CONFIG, - STRINGIFY(R_MII_MGMT_CONFIG)); - dump_reg(base_addr, R_MII_MGMT_COMMAND, - STRINGIFY(R_MII_MGMT_COMMAND)); - dump_reg(base_addr, R_MII_MGMT_ADDRESS, - STRINGIFY(R_MII_MGMT_ADDRESS)); - dump_reg(base_addr, R_MII_MGMT_WRITE_DATA, - STRINGIFY(R_MII_MGMT_WRITE_DATA)); - dump_reg(base_addr, R_MII_MGMT_STATUS, - STRINGIFY(R_MII_MGMT_STATUS)); - dump_reg(base_addr, R_MII_MGMT_INDICATORS, - STRINGIFY(R_MII_MGMT_INDICATORS)); - dump_reg(base_addr, R_INTERFACE_CONTROL, - STRINGIFY(R_INTERFACE_CONTROL)); - dump_reg(base_addr, R_INTERFACE_STATUS, - STRINGIFY(R_INTERFACE_STATUS)); - } else if (sc->port_type == XLR_XAUI || sc->port_type == XLR_XGMII) { - dump_reg(base_addr, R_XGMAC_CONFIG_0, - STRINGIFY(R_XGMAC_CONFIG_0)); - dump_reg(base_addr, R_XGMAC_CONFIG_1, - STRINGIFY(R_XGMAC_CONFIG_1)); - dump_reg(base_addr, R_XGMAC_CONFIG_2, - STRINGIFY(R_XGMAC_CONFIG_2)); - dump_reg(base_addr, R_XGMAC_CONFIG_3, - STRINGIFY(R_XGMAC_CONFIG_3)); - dump_reg(base_addr, R_XGMAC_STATION_ADDRESS_LS, - STRINGIFY(R_XGMAC_STATION_ADDRESS_LS)); - dump_reg(base_addr, R_XGMAC_STATION_ADDRESS_MS, - STRINGIFY(R_XGMAC_STATION_ADDRESS_MS)); - dump_reg(base_addr, R_XGMAC_MAX_FRAME_LEN, - STRINGIFY(R_XGMAC_MAX_FRAME_LEN)); - dump_reg(base_addr, R_XGMAC_REV_LEVEL, - STRINGIFY(R_XGMAC_REV_LEVEL)); - dump_reg(base_addr, R_XGMAC_MIIM_COMMAND, - STRINGIFY(R_XGMAC_MIIM_COMMAND)); - dump_reg(base_addr, R_XGMAC_MIIM_FILED, - STRINGIFY(R_XGMAC_MIIM_FILED)); - dump_reg(base_addr, R_XGMAC_MIIM_CONFIG, - STRINGIFY(R_XGMAC_MIIM_CONFIG)); - dump_reg(base_addr, R_XGMAC_MIIM_LINK_FAIL_VECTOR, - STRINGIFY(R_XGMAC_MIIM_LINK_FAIL_VECTOR)); - dump_reg(base_addr, R_XGMAC_MIIM_INDICATOR, - STRINGIFY(R_XGMAC_MIIM_INDICATOR)); - } - - dump_reg(base_addr, R_MAC_ADDR0, STRINGIFY(R_MAC_ADDR0)); - dump_reg(base_addr, R_MAC_ADDR0 + 1, STRINGIFY(R_MAC_ADDR0+1)); - dump_reg(base_addr, R_MAC_ADDR1, STRINGIFY(R_MAC_ADDR1)); - dump_reg(base_addr, R_MAC_ADDR2, STRINGIFY(R_MAC_ADDR2)); - dump_reg(base_addr, R_MAC_ADDR3, STRINGIFY(R_MAC_ADDR3)); - dump_reg(base_addr, R_MAC_ADDR_MASK2, STRINGIFY(R_MAC_ADDR_MASK2)); - dump_reg(base_addr, R_MAC_ADDR_MASK3, STRINGIFY(R_MAC_ADDR_MASK3)); - dump_reg(base_addr, R_MAC_FILTER_CONFIG, STRINGIFY(R_MAC_FILTER_CONFIG)); - dump_reg(base_addr, R_TX_CONTROL, STRINGIFY(R_TX_CONTROL)); - dump_reg(base_addr, R_RX_CONTROL, STRINGIFY(R_RX_CONTROL)); - dump_reg(base_addr, R_DESC_PACK_CTRL, STRINGIFY(R_DESC_PACK_CTRL)); - dump_reg(base_addr, R_STATCTRL, STRINGIFY(R_STATCTRL)); - dump_reg(base_addr, R_L2ALLOCCTRL, STRINGIFY(R_L2ALLOCCTRL)); - dump_reg(base_addr, R_INTMASK, STRINGIFY(R_INTMASK)); - dump_reg(base_addr, R_INTREG, STRINGIFY(R_INTREG)); - dump_reg(base_addr, R_TXRETRY, STRINGIFY(R_TXRETRY)); - dump_reg(base_addr, R_CORECONTROL, STRINGIFY(R_CORECONTROL)); - dump_reg(base_addr, R_BYTEOFFSET0, STRINGIFY(R_BYTEOFFSET0)); - dump_reg(base_addr, R_BYTEOFFSET1, STRINGIFY(R_BYTEOFFSET1)); - dump_reg(base_addr, R_L2TYPE_0, STRINGIFY(R_L2TYPE_0)); - dump_na_registers(base_addr, port_id); -} - -static void -dump_fmn_cpu_credits_for_gmac(struct xlr_board_info *board, int gmac_id) -{ - struct stn_cc *cc; - int gmac_bucket_ids[] = { 97, 98, 99, 100, 101, 103 }; - int j, k, r, c; - int n_gmac_buckets; - - n_gmac_buckets = nitems(gmac_bucket_ids); - for (j = 0; j < 8; j++) { // for each cpu - cc = board->credit_configs[j]; - printf("Credits for Station CPU_%d ---> GMAC buckets (tx path)\n", j); - for (k = 0; k < n_gmac_buckets; k++) { - r = gmac_bucket_ids[k] / 8; - c = gmac_bucket_ids[k] % 8; - printf (" --> gmac%d_bucket_%-3d: credits=%d\n", gmac_id, - gmac_bucket_ids[k], cc->counters[r][c]); - } - } -} - -static void -dump_fmn_gmac_credits(struct xlr_board_info *board, int gmac_id) -{ - struct stn_cc *cc; - int j, k; - - cc = board->gmac_block[gmac_id].credit_config; - printf("Credits for Station: GMAC_%d ---> CPU buckets (rx path)\n", gmac_id); - for (j = 0; j < 8; j++) { // for each cpu - printf(" ---> cpu_%d\n", j); - for (k = 0; k < 8; k++) { // for each bucket in cpu - printf(" ---> bucket_%d: credits=%d\n", j * 8 + k, - cc->counters[j][k]); - } - } -} - -static void -dump_board_info(struct xlr_board_info *board) -{ - struct xlr_gmac_block_t *gm; - int i, k; - - printf("cpu=%x ", xlr_revision()); - printf("board_version: major=%llx, minor=%llx\n", - xlr_boot1_info.board_major_version, - xlr_boot1_info.board_minor_version); - printf("is_xls=%d, nr_cpus=%d, usb=%s, cfi=%s, ata=%s\npci_irq=%d," - "gmac_ports=%d\n", board->is_xls, board->nr_cpus, - board->usb ? "Yes" : "No", board->cfi ? "Yes": "No", - board->ata ? "Yes" : "No", board->pci_irq, board->gmacports); - printf("FMN: Core-station bucket sizes\n"); - for (i = 0; i < 128; i++) { - if (i && ((i % 16) == 0)) - printf("\n"); - printf ("b[%d] = %d ", i, board->bucket_sizes->bucket[i]); - } - printf("\n"); - for (i = 0; i < 3; i++) { - gm = &board->gmac_block[i]; - printf("RNA_%d: type=%d, enabled=%s, mode=%d, station_id=%d," - "station_txbase=%d, station_rfr=%d ", i, gm->type, - gm->enabled ? "Yes" : "No", gm->mode, gm->station_id, - gm->station_txbase, gm->station_rfr); - printf("n_ports=%d, baseaddr=%p, baseirq=%d, baseinst=%d\n", - gm->num_ports, (xlr_reg_t *)gm->baseaddr, gm->baseirq, - gm->baseinst); - } - for (k = 0; k < 3; k++) { // for each NA - dump_fmn_cpu_credits_for_gmac(board, k); - dump_fmn_gmac_credits(board, k); - } -} - -static void -dump_mac_stats(struct nlge_softc *sc) -{ - xlr_reg_t *addr; - uint32_t pkts_tx, pkts_rx; - - addr = sc->base; - pkts_rx = NLGE_READ(sc->base, R_RPKT); - pkts_tx = NLGE_READ(sc->base, R_TPKT); - - printf("[nlge_%d mac stats]: pkts_tx=%u, pkts_rx=%u\n", sc->id, pkts_tx, - pkts_rx); - if (pkts_rx > 0) { - uint32_t r; - - /* dump all rx counters. we need this because pkts_rx includes - bad packets. */ - for (r = R_RFCS; r <= R_ROVR; r++) - printf("[nlge_%d mac stats]: [0x%x]=%u\n", sc->id, r, - NLGE_READ(sc->base, r)); - } - if (pkts_tx > 0) { - uint32_t r; - - /* dump all tx counters. might be useful for debugging. */ - for (r = R_TMCA; r <= R_TFRG; r++) { - if ((r == (R_TNCL + 1)) || (r == (R_TNCL + 2))) - continue; - printf("[nlge_%d mac stats]: [0x%x]=%u\n", sc->id, r, - NLGE_READ(sc->base, r)); - } - } - -} - -static void -dump_mii_regs(struct nlge_softc *sc) -{ - uint32_t mii_regs[] = { 0x0, 0x1, 0x2, 0x3, 0x4, 0x5, 0x6, 0x7, - 0x8, 0x9, 0xa, 0xf, 0x10, 0x11, 0x12, 0x13, - 0x14, 0x15, 0x16, 0x17, 0x18, 0x19, 0x1a, 0x1b, - 0x1c, 0x1d, 0x1e}; - int i, n_regs; - - if (sc->mii_base == NULL || sc->mii_bus == NULL) - return; - - n_regs = nitems(mii_regs); - for (i = 0; i < n_regs; i++) { - printf("[mii_0x%x] = %x\n", mii_regs[i], - nlge_mii_read_internal(sc->mii_base, sc->phy_addr, - mii_regs[i])); - } -} - -static void -dump_ifmedia(struct ifmedia *ifm) -{ - printf("ifm_mask=%08x, ifm_media=%08x, cur=%p\n", ifm->ifm_mask, - ifm->ifm_media, ifm->ifm_cur); - if (ifm->ifm_cur != NULL) { - printf("Cur attribs: ifmedia_entry.ifm_media=%08x," - " ifmedia_entry.ifm_data=%08x\n", ifm->ifm_cur->ifm_media, - ifm->ifm_cur->ifm_data); - } -} - -static void -dump_mii_data(struct mii_data *mii) -{ - dump_ifmedia(&mii->mii_media); - printf("ifp=%p, mii_instance=%d, mii_media_status=%08x," - " mii_media_active=%08x\n", mii->mii_ifp, mii->mii_instance, - mii->mii_media_status, mii->mii_media_active); -} - -static void -dump_pcs_regs(struct nlge_softc *sc, int phy) -{ - int i, val; - - printf("PCS regs from %p for phy=%d\n", sc->pcs_addr, phy); - for (i = 0; i < 18; i++) { - if (i == 2 || i == 3 || (i >= 9 && i <= 14)) - continue; - val = nlge_mii_read_internal(sc->pcs_addr, phy, i); - printf("PHY:%d pcs[0x%x] is 0x%x\n", phy, i, val); - } -} -#endif Property changes on: head/sys/mips/rmi/dev/nlge/if_nlge.c ___________________________________________________________________ Deleted: svn:eol-style ## -1 +0,0 ## -native \ No newline at end of property Deleted: svn:keywords ## -1 +0,0 ## -FreeBSD=%H \ No newline at end of property Deleted: svn:mime-type ## -1 +0,0 ## -text/plain \ No newline at end of property Index: head/sys/mips/rmi/dev/nlge/if_nlge.h =================================================================== --- head/sys/mips/rmi/dev/nlge/if_nlge.h (revision 327460) +++ head/sys/mips/rmi/dev/nlge/if_nlge.h (nonexistent) @@ -1,1184 +0,0 @@ -/*- - * SPDX-License-Identifier: BSD-3-Clause - * - * Copyright (c) 2003-2009 RMI Corporation - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. Neither the name of RMI Corporation, nor the names of its contributors, - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - * $FreeBSD$ - * - * RMI_BSD - */ - -/* #define MAC_SPLIT_MODE */ - -#define MAC_SPACING 0x400 -#define XGMAC_SPACING 0x400 - -/* PE-MCXMAC register and bit field definitions */ -#define R_MAC_CONFIG_1 0x00 -#define O_MAC_CONFIG_1__srst 31 -#define O_MAC_CONFIG_1__simr 30 -#define O_MAC_CONFIG_1__hrrmc 18 -#define W_MAC_CONFIG_1__hrtmc 2 -#define O_MAC_CONFIG_1__hrrfn 16 -#define W_MAC_CONFIG_1__hrtfn 2 -#define O_MAC_CONFIG_1__intlb 8 -#define O_MAC_CONFIG_1__rxfc 5 -#define O_MAC_CONFIG_1__txfc 4 -#define O_MAC_CONFIG_1__srxen 3 -#define O_MAC_CONFIG_1__rxen 2 -#define O_MAC_CONFIG_1__stxen 1 -#define O_MAC_CONFIG_1__txen 0 -#define R_MAC_CONFIG_2 0x01 -#define O_MAC_CONFIG_2__prlen 12 -#define W_MAC_CONFIG_2__prlen 4 -#define O_MAC_CONFIG_2__speed 8 -#define W_MAC_CONFIG_2__speed 2 -#define O_MAC_CONFIG_2__hugen 5 -#define O_MAC_CONFIG_2__flchk 4 -#define O_MAC_CONFIG_2__crce 1 -#define O_MAC_CONFIG_2__fulld 0 -#define R_IPG_IFG 0x02 -#define O_IPG_IFG__ipgr1 24 -#define W_IPG_IFG__ipgr1 7 -#define O_IPG_IFG__ipgr2 16 -#define W_IPG_IFG__ipgr2 7 -#define O_IPG_IFG__mifg 8 -#define W_IPG_IFG__mifg 8 -#define O_IPG_IFG__ipgt 0 -#define W_IPG_IFG__ipgt 7 -#define R_HALF_DUPLEX 0x03 -#define O_HALF_DUPLEX__abebt 24 -#define W_HALF_DUPLEX__abebt 4 -#define O_HALF_DUPLEX__abebe 19 -#define O_HALF_DUPLEX__bpnb 18 -#define O_HALF_DUPLEX__nobo 17 -#define O_HALF_DUPLEX__edxsdfr 16 -#define O_HALF_DUPLEX__retry 12 -#define W_HALF_DUPLEX__retry 4 -#define O_HALF_DUPLEX__lcol 0 -#define W_HALF_DUPLEX__lcol 10 -#define R_MAXIMUM_FRAME_LENGTH 0x04 -#define O_MAXIMUM_FRAME_LENGTH__maxf 0 -#define W_MAXIMUM_FRAME_LENGTH__maxf 16 -#define R_TEST 0x07 -#define O_TEST__mbof 3 -#define O_TEST__rthdf 2 -#define O_TEST__tpause 1 -#define O_TEST__sstct 0 -#define R_MII_MGMT_CONFIG 0x08 -#define O_MII_MGMT_CONFIG__scinc 5 -#define O_MII_MGMT_CONFIG__spre 4 -#define O_MII_MGMT_CONFIG__clks 3 -#define W_MII_MGMT_CONFIG__clks 3 -#define R_MII_MGMT_COMMAND 0x09 -#define O_MII_MGMT_COMMAND__scan 1 -#define O_MII_MGMT_COMMAND__rstat 0 -#define R_MII_MGMT_ADDRESS 0x0A -#define O_MII_MGMT_ADDRESS__fiad 8 -#define W_MII_MGMT_ADDRESS__fiad 5 -#define O_MII_MGMT_ADDRESS__fgad 5 -#define W_MII_MGMT_ADDRESS__fgad 0 -#define R_MII_MGMT_WRITE_DATA 0x0B -#define O_MII_MGMT_WRITE_DATA__ctld 0 -#define W_MII_MGMT_WRITE_DATA__ctld 16 -#define R_MII_MGMT_STATUS 0x0C -#define R_MII_MGMT_INDICATORS 0x0D -#define O_MII_MGMT_INDICATORS__nvalid 2 -#define O_MII_MGMT_INDICATORS__scan 1 -#define O_MII_MGMT_INDICATORS__busy 0 -#define R_INTERFACE_CONTROL 0x0E -#define O_INTERFACE_CONTROL__hrstint 31 -#define O_INTERFACE_CONTROL__tbimode 27 -#define O_INTERFACE_CONTROL__ghdmode 26 -#define O_INTERFACE_CONTROL__lhdmode 25 -#define O_INTERFACE_CONTROL__phymod 24 -#define O_INTERFACE_CONTROL__hrrmi 23 -#define O_INTERFACE_CONTROL__rspd 16 -#define O_INTERFACE_CONTROL__hr100 15 -#define O_INTERFACE_CONTROL__frcq 10 -#define O_INTERFACE_CONTROL__nocfr 9 -#define O_INTERFACE_CONTROL__dlfct 8 -#define O_INTERFACE_CONTROL__enjab 0 -#define R_INTERFACE_STATUS 0x0F -#define O_INTERFACE_STATUS__xsdfr 9 -#define O_INTERFACE_STATUS__ssrr 8 -#define W_INTERFACE_STATUS__ssrr 5 -#define O_INTERFACE_STATUS__miilf 3 -#define O_INTERFACE_STATUS__locar 2 -#define O_INTERFACE_STATUS__sqerr 1 -#define O_INTERFACE_STATUS__jabber 0 -#define R_STATION_ADDRESS_LS 0x10 -#define R_STATION_ADDRESS_MS 0x11 - -/* A-XGMAC register and bit field definitions */ -#define R_XGMAC_CONFIG_0 0x00 -#define O_XGMAC_CONFIG_0__hstmacrst 31 -#define O_XGMAC_CONFIG_0__hstrstrctl 23 -#define O_XGMAC_CONFIG_0__hstrstrfn 22 -#define O_XGMAC_CONFIG_0__hstrsttctl 18 -#define O_XGMAC_CONFIG_0__hstrsttfn 17 -#define O_XGMAC_CONFIG_0__hstrstmiim 16 -#define O_XGMAC_CONFIG_0__hstloopback 8 -#define R_XGMAC_CONFIG_1 0x01 -#define O_XGMAC_CONFIG_1__hsttctlen 31 -#define O_XGMAC_CONFIG_1__hsttfen 30 -#define O_XGMAC_CONFIG_1__hstrctlen 29 -#define O_XGMAC_CONFIG_1__hstrfen 28 -#define O_XGMAC_CONFIG_1__tfen 26 -#define O_XGMAC_CONFIG_1__rfen 24 -#define O_XGMAC_CONFIG_1__hstrctlshrtp 12 -#define O_XGMAC_CONFIG_1__hstdlyfcstx 10 -#define W_XGMAC_CONFIG_1__hstdlyfcstx 2 -#define O_XGMAC_CONFIG_1__hstdlyfcsrx 8 -#define W_XGMAC_CONFIG_1__hstdlyfcsrx 2 -#define O_XGMAC_CONFIG_1__hstppen 7 -#define O_XGMAC_CONFIG_1__hstbytswp 6 -#define O_XGMAC_CONFIG_1__hstdrplt64 5 -#define O_XGMAC_CONFIG_1__hstprmscrx 4 -#define O_XGMAC_CONFIG_1__hstlenchk 3 -#define O_XGMAC_CONFIG_1__hstgenfcs 2 -#define O_XGMAC_CONFIG_1__hstpadmode 0 -#define W_XGMAC_CONFIG_1__hstpadmode 2 -#define R_XGMAC_CONFIG_2 0x02 -#define O_XGMAC_CONFIG_2__hsttctlfrcp 31 -#define O_XGMAC_CONFIG_2__hstmlnkflth 27 -#define O_XGMAC_CONFIG_2__hstalnkflth 26 -#define O_XGMAC_CONFIG_2__rflnkflt 24 -#define W_XGMAC_CONFIG_2__rflnkflt 2 -#define O_XGMAC_CONFIG_2__hstipgextmod 16 -#define W_XGMAC_CONFIG_2__hstipgextmod 5 -#define O_XGMAC_CONFIG_2__hstrctlfrcp 15 -#define O_XGMAC_CONFIG_2__hstipgexten 5 -#define O_XGMAC_CONFIG_2__hstmipgext 0 -#define W_XGMAC_CONFIG_2__hstmipgext 5 -#define R_XGMAC_CONFIG_3 0x03 -#define O_XGMAC_CONFIG_3__hstfltrfrm 31 -#define W_XGMAC_CONFIG_3__hstfltrfrm 16 -#define O_XGMAC_CONFIG_3__hstfltrfrmdc 15 -#define W_XGMAC_CONFIG_3__hstfltrfrmdc 16 -#define R_XGMAC_STATION_ADDRESS_LS 0x04 -#define O_XGMAC_STATION_ADDRESS_LS__hstmacadr0 0 -#define W_XGMAC_STATION_ADDRESS_LS__hstmacadr0 32 -#define R_XGMAC_STATION_ADDRESS_MS 0x05 -#define R_XGMAC_MAX_FRAME_LEN 0x08 -#define O_XGMAC_MAX_FRAME_LEN__hstmxfrmwctx 16 -#define W_XGMAC_MAX_FRAME_LEN__hstmxfrmwctx 14 -#define O_XGMAC_MAX_FRAME_LEN__hstmxfrmbcrx 0 -#define W_XGMAC_MAX_FRAME_LEN__hstmxfrmbcrx 16 -#define R_XGMAC_REV_LEVEL 0x0B -#define O_XGMAC_REV_LEVEL__revlvl 0 -#define W_XGMAC_REV_LEVEL__revlvl 15 -#define R_XGMAC_MIIM_COMMAND 0x10 -#define O_XGMAC_MIIM_COMMAND__hstldcmd 3 -#define O_XGMAC_MIIM_COMMAND__hstmiimcmd 0 -#define W_XGMAC_MIIM_COMMAND__hstmiimcmd 3 -#define R_XGMAC_MIIM_FILED 0x11 -#define O_XGMAC_MIIM_FILED__hststfield 30 -#define W_XGMAC_MIIM_FILED__hststfield 2 -#define O_XGMAC_MIIM_FILED__hstopfield 28 -#define W_XGMAC_MIIM_FILED__hstopfield 2 -#define O_XGMAC_MIIM_FILED__hstphyadx 23 -#define W_XGMAC_MIIM_FILED__hstphyadx 5 -#define O_XGMAC_MIIM_FILED__hstregadx 18 -#define W_XGMAC_MIIM_FILED__hstregadx 5 -#define O_XGMAC_MIIM_FILED__hsttafield 16 -#define W_XGMAC_MIIM_FILED__hsttafield 2 -#define O_XGMAC_MIIM_FILED__miimrddat 0 -#define W_XGMAC_MIIM_FILED__miimrddat 16 -#define R_XGMAC_MIIM_CONFIG 0x12 -#define O_XGMAC_MIIM_CONFIG__hstnopram 7 -#define O_XGMAC_MIIM_CONFIG__hstclkdiv 0 -#define W_XGMAC_MIIM_CONFIG__hstclkdiv 7 -#define R_XGMAC_MIIM_LINK_FAIL_VECTOR 0x13 -#define O_XGMAC_MIIM_LINK_FAIL_VECTOR__miimlfvec 0 -#define W_XGMAC_MIIM_LINK_FAIL_VECTOR__miimlfvec 32 -#define R_XGMAC_MIIM_INDICATOR 0x14 -#define O_XGMAC_MIIM_INDICATOR__miimphylf 4 -#define O_XGMAC_MIIM_INDICATOR__miimmoncplt 3 -#define O_XGMAC_MIIM_INDICATOR__miimmonvld 2 -#define O_XGMAC_MIIM_INDICATOR__miimmon 1 -#define O_XGMAC_MIIM_INDICATOR__miimbusy 0 - -/* GMAC stats registers */ -#define R_RBYT 0x27 -#define R_RPKT 0x28 -#define R_RFCS 0x29 -#define R_RMCA 0x2A -#define R_RBCA 0x2B -#define R_RXCF 0x2C -#define R_RXPF 0x2D -#define R_RXUO 0x2E -#define R_RALN 0x2F -#define R_RFLR 0x30 -#define R_RCDE 0x31 -#define R_RCSE 0x32 -#define R_RUND 0x33 -#define R_ROVR 0x34 -#define R_TBYT 0x38 -#define R_TPKT 0x39 -#define R_TMCA 0x3A -#define R_TBCA 0x3B -#define R_TXPF 0x3C -#define R_TDFR 0x3D -#define R_TEDF 0x3E -#define R_TSCL 0x3F -#define R_TMCL 0x40 -#define R_TLCL 0x41 -#define R_TXCL 0x42 -#define R_TNCL 0x43 -#define R_TJBR 0x46 -#define R_TFCS 0x47 -#define R_TXCF 0x48 -#define R_TOVR 0x49 -#define R_TUND 0x4A -#define R_TFRG 0x4B - -/* Glue logic register and bit field definitions */ -#define R_MAC_ADDR0 0x50 -#define R_MAC_ADDR1 0x52 -#define R_MAC_ADDR2 0x54 -#define R_MAC_ADDR3 0x56 -#define R_MAC_ADDR_MASK2 0x58 -#define R_MAC_ADDR_MASK3 0x5A -#define R_MAC_FILTER_CONFIG 0x5C -#define O_MAC_FILTER_CONFIG__BROADCAST_EN 10 -#define O_MAC_FILTER_CONFIG__PAUSE_FRAME_EN 9 -#define O_MAC_FILTER_CONFIG__ALL_MCAST_EN 8 -#define O_MAC_FILTER_CONFIG__ALL_UCAST_EN 7 -#define O_MAC_FILTER_CONFIG__HASH_MCAST_EN 6 -#define O_MAC_FILTER_CONFIG__HASH_UCAST_EN 5 -#define O_MAC_FILTER_CONFIG__ADDR_MATCH_DISC 4 -#define O_MAC_FILTER_CONFIG__MAC_ADDR3_VALID 3 -#define O_MAC_FILTER_CONFIG__MAC_ADDR2_VALID 2 -#define O_MAC_FILTER_CONFIG__MAC_ADDR1_VALID 1 -#define O_MAC_FILTER_CONFIG__MAC_ADDR0_VALID 0 -#define R_HASH_TABLE_VECTOR 0x30 -#define R_TX_CONTROL 0x0A0 -#define O_TX_CONTROL__Tx15Halt 31 -#define O_TX_CONTROL__Tx14Halt 30 -#define O_TX_CONTROL__Tx13Halt 29 -#define O_TX_CONTROL__Tx12Halt 28 -#define O_TX_CONTROL__Tx11Halt 27 -#define O_TX_CONTROL__Tx10Halt 26 -#define O_TX_CONTROL__Tx9Halt 25 -#define O_TX_CONTROL__Tx8Halt 24 -#define O_TX_CONTROL__Tx7Halt 23 -#define O_TX_CONTROL__Tx6Halt 22 -#define O_TX_CONTROL__Tx5Halt 21 -#define O_TX_CONTROL__Tx4Halt 20 -#define O_TX_CONTROL__Tx3Halt 19 -#define O_TX_CONTROL__Tx2Halt 18 -#define O_TX_CONTROL__Tx1Halt 17 -#define O_TX_CONTROL__Tx0Halt 16 -#define O_TX_CONTROL__TxIdle 15 -#define O_TX_CONTROL__TxEnable 14 -#define O_TX_CONTROL__TxThreshold 0 -#define W_TX_CONTROL__TxThreshold 14 -#define R_RX_CONTROL 0x0A1 -#define O_RX_CONTROL__RGMII 10 -#define O_RX_CONTROL__SoftReset 2 -#define O_RX_CONTROL__RxHalt 1 -#define O_RX_CONTROL__RxEnable 0 -#define R_DESC_PACK_CTRL 0x0A2 -#define O_DESC_PACK_CTRL__ByteOffset 17 -#define W_DESC_PACK_CTRL__ByteOffset 3 -#define O_DESC_PACK_CTRL__PrePadEnable 16 -#define O_DESC_PACK_CTRL__MaxEntry 14 -#define W_DESC_PACK_CTRL__MaxEntry 2 -#define O_DESC_PACK_CTRL__RegularSize 0 -#define W_DESC_PACK_CTRL__RegularSize 14 -#define R_STATCTRL 0x0A3 -#define O_STATCTRL__OverFlowEn 4 -#define O_STATCTRL__GIG 3 -#define O_STATCTRL__Sten 2 -#define O_STATCTRL__ClrCnt 1 -#define O_STATCTRL__AutoZ 0 -#define R_L2ALLOCCTRL 0x0A4 -#define O_L2ALLOCCTRL__TxL2Allocate 9 -#define W_L2ALLOCCTRL__TxL2Allocate 9 -#define O_L2ALLOCCTRL__RxL2Allocate 0 -#define W_L2ALLOCCTRL__RxL2Allocate 9 -#define R_INTMASK 0x0A5 -#define O_INTMASK__Spi4TxError 28 -#define O_INTMASK__Spi4RxError 27 -#define O_INTMASK__RGMIIHalfDupCollision 27 -#define O_INTMASK__Abort 26 -#define O_INTMASK__Underrun 25 -#define O_INTMASK__DiscardPacket 24 -#define O_INTMASK__AsyncFifoFull 23 -#define O_INTMASK__TagFull 22 -#define O_INTMASK__Class3Full 21 -#define O_INTMASK__C3EarlyFull 20 -#define O_INTMASK__Class2Full 19 -#define O_INTMASK__C2EarlyFull 18 -#define O_INTMASK__Class1Full 17 -#define O_INTMASK__C1EarlyFull 16 -#define O_INTMASK__Class0Full 15 -#define O_INTMASK__C0EarlyFull 14 -#define O_INTMASK__RxDataFull 13 -#define O_INTMASK__RxEarlyFull 12 -#define O_INTMASK__RFreeEmpty 9 -#define O_INTMASK__RFEarlyEmpty 8 -#define O_INTMASK__P2PSpillEcc 7 -#define O_INTMASK__FreeDescFull 5 -#define O_INTMASK__FreeEarlyFull 4 -#define O_INTMASK__TxFetchError 3 -#define O_INTMASK__StatCarry 2 -#define O_INTMASK__MDInt 1 -#define O_INTMASK__TxIllegal 0 -#define R_INTREG 0x0A6 -#define O_INTREG__Spi4TxError 28 -#define O_INTREG__Spi4RxError 27 -#define O_INTREG__RGMIIHalfDupCollision 27 -#define O_INTREG__Abort 26 -#define O_INTREG__Underrun 25 -#define O_INTREG__DiscardPacket 24 -#define O_INTREG__AsyncFifoFull 23 -#define O_INTREG__TagFull 22 -#define O_INTREG__Class3Full 21 -#define O_INTREG__C3EarlyFull 20 -#define O_INTREG__Class2Full 19 -#define O_INTREG__C2EarlyFull 18 -#define O_INTREG__Class1Full 17 -#define O_INTREG__C1EarlyFull 16 -#define O_INTREG__Class0Full 15 -#define O_INTREG__C0EarlyFull 14 -#define O_INTREG__RxDataFull 13 -#define O_INTREG__RxEarlyFull 12 -#define O_INTREG__RFreeEmpty 9 -#define O_INTREG__RFEarlyEmpty 8 -#define O_INTREG__P2PSpillEcc 7 -#define O_INTREG__FreeDescFull 5 -#define O_INTREG__FreeEarlyFull 4 -#define O_INTREG__TxFetchError 3 -#define O_INTREG__StatCarry 2 -#define O_INTREG__MDInt 1 -#define O_INTREG__TxIllegal 0 -#define R_TXRETRY 0x0A7 -#define O_TXRETRY__CollisionRetry 6 -#define O_TXRETRY__BusErrorRetry 5 -#define O_TXRETRY__UnderRunRetry 4 -#define O_TXRETRY__Retries 0 -#define W_TXRETRY__Retries 4 -#define R_CORECONTROL 0x0A8 -#define O_CORECONTROL__ErrorThread 4 -#define W_CORECONTROL__ErrorThread 7 -#define O_CORECONTROL__Shutdown 2 -#define O_CORECONTROL__Speed 0 -#define W_CORECONTROL__Speed 2 -#define R_BYTEOFFSET0 0x0A9 -#define R_BYTEOFFSET1 0x0AA -#define R_L2TYPE_0 0x0F0 -#define O_L2TYPE__ExtraHdrProtoSize 26 -#define W_L2TYPE__ExtraHdrProtoSize 5 -#define O_L2TYPE__ExtraHdrProtoOffset 20 -#define W_L2TYPE__ExtraHdrProtoOffset 6 -#define O_L2TYPE__ExtraHeaderSize 14 -#define W_L2TYPE__ExtraHeaderSize 6 -#define O_L2TYPE__ProtoOffset 8 -#define W_L2TYPE__ProtoOffset 6 -#define O_L2TYPE__L2HdrOffset 2 -#define W_L2TYPE__L2HdrOffset 6 -#define O_L2TYPE__L2Proto 0 -#define W_L2TYPE__L2Proto 2 -#define R_L2TYPE_1 0xF0 -#define R_L2TYPE_2 0xF0 -#define R_L2TYPE_3 0xF0 -#define R_PARSERCONFIGREG 0x100 -#define O_PARSERCONFIGREG__CRCHashPoly 8 -#define W_PARSERCONFIGREG__CRCHashPoly 7 -#define O_PARSERCONFIGREG__PrePadOffset 4 -#define W_PARSERCONFIGREG__PrePadOffset 4 -#define O_PARSERCONFIGREG__UseCAM 2 -#define O_PARSERCONFIGREG__UseHASH 1 -#define O_PARSERCONFIGREG__UseProto 0 -#define R_L3CTABLE 0x140 -#define O_L3CTABLE__Offset0 25 -#define W_L3CTABLE__Offset0 7 -#define O_L3CTABLE__Len0 21 -#define W_L3CTABLE__Len0 4 -#define O_L3CTABLE__Offset1 14 -#define W_L3CTABLE__Offset1 7 -#define O_L3CTABLE__Len1 10 -#define W_L3CTABLE__Len1 4 -#define O_L3CTABLE__Offset2 4 -#define W_L3CTABLE__Offset2 6 -#define O_L3CTABLE__Len2 0 -#define W_L3CTABLE__Len2 4 -#define O_L3CTABLE__L3HdrOffset 26 -#define W_L3CTABLE__L3HdrOffset 6 -#define O_L3CTABLE__L4ProtoOffset 20 -#define W_L3CTABLE__L4ProtoOffset 6 -#define O_L3CTABLE__IPChksumCompute 19 -#define O_L3CTABLE__L4Classify 18 -#define O_L3CTABLE__L2Proto 16 -#define W_L3CTABLE__L2Proto 2 -#define O_L3CTABLE__L3ProtoKey 0 -#define W_L3CTABLE__L3ProtoKey 16 -#define R_L4CTABLE 0x160 -#define O_L4CTABLE__Offset0 21 -#define W_L4CTABLE__Offset0 6 -#define O_L4CTABLE__Len0 17 -#define W_L4CTABLE__Len0 4 -#define O_L4CTABLE__Offset1 11 -#define W_L4CTABLE__Offset1 6 -#define O_L4CTABLE__Len1 7 -#define W_L4CTABLE__Len1 4 -#define O_L4CTABLE__TCPChksumEnable 0 -#define R_CAM4X128TABLE 0x172 -#define O_CAM4X128TABLE__ClassId 7 -#define W_CAM4X128TABLE__ClassId 2 -#define O_CAM4X128TABLE__BucketId 1 -#define W_CAM4X128TABLE__BucketId 6 -#define O_CAM4X128TABLE__UseBucket 0 -#define R_CAM4X128KEY 0x180 -#define R_TRANSLATETABLE 0x1A0 -#define R_DMACR0 0x200 -#define O_DMACR0__Data0WrMaxCr 27 -#define W_DMACR0__Data0WrMaxCr 3 -#define O_DMACR0__Data0RdMaxCr 24 -#define W_DMACR0__Data0RdMaxCr 3 -#define O_DMACR0__Data1WrMaxCr 21 -#define W_DMACR0__Data1WrMaxCr 3 -#define O_DMACR0__Data1RdMaxCr 18 -#define W_DMACR0__Data1RdMaxCr 3 -#define O_DMACR0__Data2WrMaxCr 15 -#define W_DMACR0__Data2WrMaxCr 3 -#define O_DMACR0__Data2RdMaxCr 12 -#define W_DMACR0__Data2RdMaxCr 3 -#define O_DMACR0__Data3WrMaxCr 9 -#define W_DMACR0__Data3WrMaxCr 3 -#define O_DMACR0__Data3RdMaxCr 6 -#define W_DMACR0__Data3RdMaxCr 3 -#define O_DMACR0__Data4WrMaxCr 3 -#define W_DMACR0__Data4WrMaxCr 3 -#define O_DMACR0__Data4RdMaxCr 0 -#define W_DMACR0__Data4RdMaxCr 3 -#define R_DMACR1 0x201 -#define O_DMACR1__Data5WrMaxCr 27 -#define W_DMACR1__Data5WrMaxCr 3 -#define O_DMACR1__Data5RdMaxCr 24 -#define W_DMACR1__Data5RdMaxCr 3 -#define O_DMACR1__Data6WrMaxCr 21 -#define W_DMACR1__Data6WrMaxCr 3 -#define O_DMACR1__Data6RdMaxCr 18 -#define W_DMACR1__Data6RdMaxCr 3 -#define O_DMACR1__Data7WrMaxCr 15 -#define W_DMACR1__Data7WrMaxCr 3 -#define O_DMACR1__Data7RdMaxCr 12 -#define W_DMACR1__Data7RdMaxCr 3 -#define O_DMACR1__Data8WrMaxCr 9 -#define W_DMACR1__Data8WrMaxCr 3 -#define O_DMACR1__Data8RdMaxCr 6 -#define W_DMACR1__Data8RdMaxCr 3 -#define O_DMACR1__Data9WrMaxCr 3 -#define W_DMACR1__Data9WrMaxCr 3 -#define O_DMACR1__Data9RdMaxCr 0 -#define W_DMACR1__Data9RdMaxCr 3 -#define R_DMACR2 0x202 -#define O_DMACR2__Data10WrMaxCr 27 -#define W_DMACR2__Data10WrMaxCr 3 -#define O_DMACR2__Data10RdMaxCr 24 -#define W_DMACR2__Data10RdMaxCr 3 -#define O_DMACR2__Data11WrMaxCr 21 -#define W_DMACR2__Data11WrMaxCr 3 -#define O_DMACR2__Data11RdMaxCr 18 -#define W_DMACR2__Data11RdMaxCr 3 -#define O_DMACR2__Data12WrMaxCr 15 -#define W_DMACR2__Data12WrMaxCr 3 -#define O_DMACR2__Data12RdMaxCr 12 -#define W_DMACR2__Data12RdMaxCr 3 -#define O_DMACR2__Data13WrMaxCr 9 -#define W_DMACR2__Data13WrMaxCr 3 -#define O_DMACR2__Data13RdMaxCr 6 -#define W_DMACR2__Data13RdMaxCr 3 -#define O_DMACR2__Data14WrMaxCr 3 -#define W_DMACR2__Data14WrMaxCr 3 -#define O_DMACR2__Data14RdMaxCr 0 -#define W_DMACR2__Data14RdMaxCr 3 -#define R_DMACR3 0x203 -#define O_DMACR3__Data15WrMaxCr 27 -#define W_DMACR3__Data15WrMaxCr 3 -#define O_DMACR3__Data15RdMaxCr 24 -#define W_DMACR3__Data15RdMaxCr 3 -#define O_DMACR3__SpClassWrMaxCr 21 -#define W_DMACR3__SpClassWrMaxCr 3 -#define O_DMACR3__SpClassRdMaxCr 18 -#define W_DMACR3__SpClassRdMaxCr 3 -#define O_DMACR3__JumFrInWrMaxCr 15 -#define W_DMACR3__JumFrInWrMaxCr 3 -#define O_DMACR3__JumFrInRdMaxCr 12 -#define W_DMACR3__JumFrInRdMaxCr 3 -#define O_DMACR3__RegFrInWrMaxCr 9 -#define W_DMACR3__RegFrInWrMaxCr 3 -#define O_DMACR3__RegFrInRdMaxCr 6 -#define W_DMACR3__RegFrInRdMaxCr 3 -#define O_DMACR3__FrOutWrMaxCr 3 -#define W_DMACR3__FrOutWrMaxCr 3 -#define O_DMACR3__FrOutRdMaxCr 0 -#define W_DMACR3__FrOutRdMaxCr 3 -#define R_REG_FRIN_SPILL_MEM_START_0 0x204 -#define O_REG_FRIN_SPILL_MEM_START_0__RegFrInSpillMemStart0 0 -#define W_REG_FRIN_SPILL_MEM_START_0__RegFrInSpillMemStart0 32 -#define R_REG_FRIN_SPILL_MEM_START_1 0x205 -#define O_REG_FRIN_SPILL_MEM_START_1__RegFrInSpillMemStart1 0 -#define W_REG_FRIN_SPILL_MEM_START_1__RegFrInSpillMemStart1 3 -#define R_REG_FRIN_SPILL_MEM_SIZE 0x206 -#define O_REG_FRIN_SPILL_MEM_SIZE__RegFrInSpillMemSize 0 -#define W_REG_FRIN_SPILL_MEM_SIZE__RegFrInSpillMemSize 32 -#define R_FROUT_SPILL_MEM_START_0 0x207 -#define O_FROUT_SPILL_MEM_START_0__FrOutSpillMemStart0 0 -#define W_FROUT_SPILL_MEM_START_0__FrOutSpillMemStart0 32 -#define R_FROUT_SPILL_MEM_START_1 0x208 -#define O_FROUT_SPILL_MEM_START_1__FrOutSpillMemStart1 0 -#define W_FROUT_SPILL_MEM_START_1__FrOutSpillMemStart1 3 -#define R_FROUT_SPILL_MEM_SIZE 0x209 -#define O_FROUT_SPILL_MEM_SIZE__FrOutSpillMemSize 0 -#define W_FROUT_SPILL_MEM_SIZE__FrOutSpillMemSize 32 -#define R_CLASS0_SPILL_MEM_START_0 0x20A -#define O_CLASS0_SPILL_MEM_START_0__Class0SpillMemStart0 0 -#define W_CLASS0_SPILL_MEM_START_0__Class0SpillMemStart0 32 -#define R_CLASS0_SPILL_MEM_START_1 0x20B -#define O_CLASS0_SPILL_MEM_START_1__Class0SpillMemStart1 0 -#define W_CLASS0_SPILL_MEM_START_1__Class0SpillMemStart1 3 -#define R_CLASS0_SPILL_MEM_SIZE 0x20C -#define O_CLASS0_SPILL_MEM_SIZE__Class0SpillMemSize 0 -#define W_CLASS0_SPILL_MEM_SIZE__Class0SpillMemSize 32 -#define R_JUMFRIN_SPILL_MEM_START_0 0x20D -#define O_JUMFRIN_SPILL_MEM_START_0__JumFrInSpillMemStar0 0 -#define W_JUMFRIN_SPILL_MEM_START_0__JumFrInSpillMemStar0 32 -#define R_JUMFRIN_SPILL_MEM_START_1 0x20E -#define O_JUMFRIN_SPILL_MEM_START_1__JumFrInSpillMemStart1 0 -#define W_JUMFRIN_SPILL_MEM_START_1__JumFrInSpillMemStart1 3 -#define R_JUMFRIN_SPILL_MEM_SIZE 0x20F -#define O_JUMFRIN_SPILL_MEM_SIZE__JumFrInSpillMemSize 0 -#define W_JUMFRIN_SPILL_MEM_SIZE__JumFrInSpillMemSize 32 -#define R_CLASS1_SPILL_MEM_START_0 0x210 -#define O_CLASS1_SPILL_MEM_START_0__Class1SpillMemStart0 0 -#define W_CLASS1_SPILL_MEM_START_0__Class1SpillMemStart0 32 -#define R_CLASS1_SPILL_MEM_START_1 0x211 -#define O_CLASS1_SPILL_MEM_START_1__Class1SpillMemStart1 0 -#define W_CLASS1_SPILL_MEM_START_1__Class1SpillMemStart1 3 -#define R_CLASS1_SPILL_MEM_SIZE 0x212 -#define O_CLASS1_SPILL_MEM_SIZE__Class1SpillMemSize 0 -#define W_CLASS1_SPILL_MEM_SIZE__Class1SpillMemSize 32 -#define R_CLASS2_SPILL_MEM_START_0 0x213 -#define O_CLASS2_SPILL_MEM_START_0__Class2SpillMemStart0 0 -#define W_CLASS2_SPILL_MEM_START_0__Class2SpillMemStart0 32 -#define R_CLASS2_SPILL_MEM_START_1 0x214 -#define O_CLASS2_SPILL_MEM_START_1__Class2SpillMemStart1 0 -#define W_CLASS2_SPILL_MEM_START_1__Class2SpillMemStart1 3 -#define R_CLASS2_SPILL_MEM_SIZE 0x215 -#define O_CLASS2_SPILL_MEM_SIZE__Class2SpillMemSize 0 -#define W_CLASS2_SPILL_MEM_SIZE__Class2SpillMemSize 32 -#define R_CLASS3_SPILL_MEM_START_0 0x216 -#define O_CLASS3_SPILL_MEM_START_0__Class3SpillMemStart0 0 -#define W_CLASS3_SPILL_MEM_START_0__Class3SpillMemStart0 32 -#define R_CLASS3_SPILL_MEM_START_1 0x217 -#define O_CLASS3_SPILL_MEM_START_1__Class3SpillMemStart1 0 -#define W_CLASS3_SPILL_MEM_START_1__Class3SpillMemStart1 3 -#define R_CLASS3_SPILL_MEM_SIZE 0x218 -#define O_CLASS3_SPILL_MEM_SIZE__Class3SpillMemSize 0 -#define W_CLASS3_SPILL_MEM_SIZE__Class3SpillMemSize 32 -#define R_REG_FRIN1_SPILL_MEM_START_0 0x219 -#define R_REG_FRIN1_SPILL_MEM_START_1 0x21a -#define R_REG_FRIN1_SPILL_MEM_SIZE 0x21b -#define R_SPIHNGY0 0x219 -#define O_SPIHNGY0__EG_HNGY_THRESH_0 24 -#define W_SPIHNGY0__EG_HNGY_THRESH_0 7 -#define O_SPIHNGY0__EG_HNGY_THRESH_1 16 -#define W_SPIHNGY0__EG_HNGY_THRESH_1 7 -#define O_SPIHNGY0__EG_HNGY_THRESH_2 8 -#define W_SPIHNGY0__EG_HNGY_THRESH_2 7 -#define O_SPIHNGY0__EG_HNGY_THRESH_3 0 -#define W_SPIHNGY0__EG_HNGY_THRESH_3 7 -#define R_SPIHNGY1 0x21A -#define O_SPIHNGY1__EG_HNGY_THRESH_4 24 -#define W_SPIHNGY1__EG_HNGY_THRESH_4 7 -#define O_SPIHNGY1__EG_HNGY_THRESH_5 16 -#define W_SPIHNGY1__EG_HNGY_THRESH_5 7 -#define O_SPIHNGY1__EG_HNGY_THRESH_6 8 -#define W_SPIHNGY1__EG_HNGY_THRESH_6 7 -#define O_SPIHNGY1__EG_HNGY_THRESH_7 0 -#define W_SPIHNGY1__EG_HNGY_THRESH_7 7 -#define R_SPIHNGY2 0x21B -#define O_SPIHNGY2__EG_HNGY_THRESH_8 24 -#define W_SPIHNGY2__EG_HNGY_THRESH_8 7 -#define O_SPIHNGY2__EG_HNGY_THRESH_9 16 -#define W_SPIHNGY2__EG_HNGY_THRESH_9 7 -#define O_SPIHNGY2__EG_HNGY_THRESH_10 8 -#define W_SPIHNGY2__EG_HNGY_THRESH_10 7 -#define O_SPIHNGY2__EG_HNGY_THRESH_11 0 -#define W_SPIHNGY2__EG_HNGY_THRESH_11 7 -#define R_SPIHNGY3 0x21C -#define O_SPIHNGY3__EG_HNGY_THRESH_12 24 -#define W_SPIHNGY3__EG_HNGY_THRESH_12 7 -#define O_SPIHNGY3__EG_HNGY_THRESH_13 16 -#define W_SPIHNGY3__EG_HNGY_THRESH_13 7 -#define O_SPIHNGY3__EG_HNGY_THRESH_14 8 -#define W_SPIHNGY3__EG_HNGY_THRESH_14 7 -#define O_SPIHNGY3__EG_HNGY_THRESH_15 0 -#define W_SPIHNGY3__EG_HNGY_THRESH_15 7 -#define R_SPISTRV0 0x21D -#define O_SPISTRV0__EG_STRV_THRESH_0 24 -#define W_SPISTRV0__EG_STRV_THRESH_0 7 -#define O_SPISTRV0__EG_STRV_THRESH_1 16 -#define W_SPISTRV0__EG_STRV_THRESH_1 7 -#define O_SPISTRV0__EG_STRV_THRESH_2 8 -#define W_SPISTRV0__EG_STRV_THRESH_2 7 -#define O_SPISTRV0__EG_STRV_THRESH_3 0 -#define W_SPISTRV0__EG_STRV_THRESH_3 7 -#define R_SPISTRV1 0x21E -#define O_SPISTRV1__EG_STRV_THRESH_4 24 -#define W_SPISTRV1__EG_STRV_THRESH_4 7 -#define O_SPISTRV1__EG_STRV_THRESH_5 16 -#define W_SPISTRV1__EG_STRV_THRESH_5 7 -#define O_SPISTRV1__EG_STRV_THRESH_6 8 -#define W_SPISTRV1__EG_STRV_THRESH_6 7 -#define O_SPISTRV1__EG_STRV_THRESH_7 0 -#define W_SPISTRV1__EG_STRV_THRESH_7 7 -#define R_SPISTRV2 0x21F -#define O_SPISTRV2__EG_STRV_THRESH_8 24 -#define W_SPISTRV2__EG_STRV_THRESH_8 7 -#define O_SPISTRV2__EG_STRV_THRESH_9 16 -#define W_SPISTRV2__EG_STRV_THRESH_9 7 -#define O_SPISTRV2__EG_STRV_THRESH_10 8 -#define W_SPISTRV2__EG_STRV_THRESH_10 7 -#define O_SPISTRV2__EG_STRV_THRESH_11 0 -#define W_SPISTRV2__EG_STRV_THRESH_11 7 -#define R_SPISTRV3 0x220 -#define O_SPISTRV3__EG_STRV_THRESH_12 24 -#define W_SPISTRV3__EG_STRV_THRESH_12 7 -#define O_SPISTRV3__EG_STRV_THRESH_13 16 -#define W_SPISTRV3__EG_STRV_THRESH_13 7 -#define O_SPISTRV3__EG_STRV_THRESH_14 8 -#define W_SPISTRV3__EG_STRV_THRESH_14 7 -#define O_SPISTRV3__EG_STRV_THRESH_15 0 -#define W_SPISTRV3__EG_STRV_THRESH_15 7 -#define R_TXDATAFIFO0 0x221 -#define O_TXDATAFIFO0__Tx0DataFifoStart 24 -#define W_TXDATAFIFO0__Tx0DataFifoStart 7 -#define O_TXDATAFIFO0__Tx0DataFifoSize 16 -#define W_TXDATAFIFO0__Tx0DataFifoSize 7 -#define O_TXDATAFIFO0__Tx1DataFifoStart 8 -#define W_TXDATAFIFO0__Tx1DataFifoStart 7 -#define O_TXDATAFIFO0__Tx1DataFifoSize 0 -#define W_TXDATAFIFO0__Tx1DataFifoSize 7 -#define R_TXDATAFIFO1 0x222 -#define O_TXDATAFIFO1__Tx2DataFifoStart 24 -#define W_TXDATAFIFO1__Tx2DataFifoStart 7 -#define O_TXDATAFIFO1__Tx2DataFifoSize 16 -#define W_TXDATAFIFO1__Tx2DataFifoSize 7 -#define O_TXDATAFIFO1__Tx3DataFifoStart 8 -#define W_TXDATAFIFO1__Tx3DataFifoStart 7 -#define O_TXDATAFIFO1__Tx3DataFifoSize 0 -#define W_TXDATAFIFO1__Tx3DataFifoSize 7 -#define R_TXDATAFIFO2 0x223 -#define O_TXDATAFIFO2__Tx4DataFifoStart 24 -#define W_TXDATAFIFO2__Tx4DataFifoStart 7 -#define O_TXDATAFIFO2__Tx4DataFifoSize 16 -#define W_TXDATAFIFO2__Tx4DataFifoSize 7 -#define O_TXDATAFIFO2__Tx5DataFifoStart 8 -#define W_TXDATAFIFO2__Tx5DataFifoStart 7 -#define O_TXDATAFIFO2__Tx5DataFifoSize 0 -#define W_TXDATAFIFO2__Tx5DataFifoSize 7 -#define R_TXDATAFIFO3 0x224 -#define O_TXDATAFIFO3__Tx6DataFifoStart 24 -#define W_TXDATAFIFO3__Tx6DataFifoStart 7 -#define O_TXDATAFIFO3__Tx6DataFifoSize 16 -#define W_TXDATAFIFO3__Tx6DataFifoSize 7 -#define O_TXDATAFIFO3__Tx7DataFifoStart 8 -#define W_TXDATAFIFO3__Tx7DataFifoStart 7 -#define O_TXDATAFIFO3__Tx7DataFifoSize 0 -#define W_TXDATAFIFO3__Tx7DataFifoSize 7 -#define R_TXDATAFIFO4 0x225 -#define O_TXDATAFIFO4__Tx8DataFifoStart 24 -#define W_TXDATAFIFO4__Tx8DataFifoStart 7 -#define O_TXDATAFIFO4__Tx8DataFifoSize 16 -#define W_TXDATAFIFO4__Tx8DataFifoSize 7 -#define O_TXDATAFIFO4__Tx9DataFifoStart 8 -#define W_TXDATAFIFO4__Tx9DataFifoStart 7 -#define O_TXDATAFIFO4__Tx9DataFifoSize 0 -#define W_TXDATAFIFO4__Tx9DataFifoSize 7 -#define R_TXDATAFIFO5 0x226 -#define O_TXDATAFIFO5__Tx10DataFifoStart 24 -#define W_TXDATAFIFO5__Tx10DataFifoStart 7 -#define O_TXDATAFIFO5__Tx10DataFifoSize 16 -#define W_TXDATAFIFO5__Tx10DataFifoSize 7 -#define O_TXDATAFIFO5__Tx11DataFifoStart 8 -#define W_TXDATAFIFO5__Tx11DataFifoStart 7 -#define O_TXDATAFIFO5__Tx11DataFifoSize 0 -#define W_TXDATAFIFO5__Tx11DataFifoSize 7 -#define R_TXDATAFIFO6 0x227 -#define O_TXDATAFIFO6__Tx12DataFifoStart 24 -#define W_TXDATAFIFO6__Tx12DataFifoStart 7 -#define O_TXDATAFIFO6__Tx12DataFifoSize 16 -#define W_TXDATAFIFO6__Tx12DataFifoSize 7 -#define O_TXDATAFIFO6__Tx13DataFifoStart 8 -#define W_TXDATAFIFO6__Tx13DataFifoStart 7 -#define O_TXDATAFIFO6__Tx13DataFifoSize 0 -#define W_TXDATAFIFO6__Tx13DataFifoSize 7 -#define R_TXDATAFIFO7 0x228 -#define O_TXDATAFIFO7__Tx14DataFifoStart 24 -#define W_TXDATAFIFO7__Tx14DataFifoStart 7 -#define O_TXDATAFIFO7__Tx14DataFifoSize 16 -#define W_TXDATAFIFO7__Tx14DataFifoSize 7 -#define O_TXDATAFIFO7__Tx15DataFifoStart 8 -#define W_TXDATAFIFO7__Tx15DataFifoStart 7 -#define O_TXDATAFIFO7__Tx15DataFifoSize 0 -#define W_TXDATAFIFO7__Tx15DataFifoSize 7 -#define R_RXDATAFIFO0 0x229 -#define O_RXDATAFIFO0__Rx0DataFifoStart 24 -#define W_RXDATAFIFO0__Rx0DataFifoStart 7 -#define O_RXDATAFIFO0__Rx0DataFifoSize 16 -#define W_RXDATAFIFO0__Rx0DataFifoSize 7 -#define O_RXDATAFIFO0__Rx1DataFifoStart 8 -#define W_RXDATAFIFO0__Rx1DataFifoStart 7 -#define O_RXDATAFIFO0__Rx1DataFifoSize 0 -#define W_RXDATAFIFO0__Rx1DataFifoSize 7 -#define R_RXDATAFIFO1 0x22A -#define O_RXDATAFIFO1__Rx2DataFifoStart 24 -#define W_RXDATAFIFO1__Rx2DataFifoStart 7 -#define O_RXDATAFIFO1__Rx2DataFifoSize 16 -#define W_RXDATAFIFO1__Rx2DataFifoSize 7 -#define O_RXDATAFIFO1__Rx3DataFifoStart 8 -#define W_RXDATAFIFO1__Rx3DataFifoStart 7 -#define O_RXDATAFIFO1__Rx3DataFifoSize 0 -#define W_RXDATAFIFO1__Rx3DataFifoSize 7 -#define R_RXDATAFIFO2 0x22B -#define O_RXDATAFIFO2__Rx4DataFifoStart 24 -#define W_RXDATAFIFO2__Rx4DataFifoStart 7 -#define O_RXDATAFIFO2__Rx4DataFifoSize 16 -#define W_RXDATAFIFO2__Rx4DataFifoSize 7 -#define O_RXDATAFIFO2__Rx5DataFifoStart 8 -#define W_RXDATAFIFO2__Rx5DataFifoStart 7 -#define O_RXDATAFIFO2__Rx5DataFifoSize 0 -#define W_RXDATAFIFO2__Rx5DataFifoSize 7 -#define R_RXDATAFIFO3 0x22C -#define O_RXDATAFIFO3__Rx6DataFifoStart 24 -#define W_RXDATAFIFO3__Rx6DataFifoStart 7 -#define O_RXDATAFIFO3__Rx6DataFifoSize 16 -#define W_RXDATAFIFO3__Rx6DataFifoSize 7 -#define O_RXDATAFIFO3__Rx7DataFifoStart 8 -#define W_RXDATAFIFO3__Rx7DataFifoStart 7 -#define O_RXDATAFIFO3__Rx7DataFifoSize 0 -#define W_RXDATAFIFO3__Rx7DataFifoSize 7 -#define R_RXDATAFIFO4 0x22D -#define O_RXDATAFIFO4__Rx8DataFifoStart 24 -#define W_RXDATAFIFO4__Rx8DataFifoStart 7 -#define O_RXDATAFIFO4__Rx8DataFifoSize 16 -#define W_RXDATAFIFO4__Rx8DataFifoSize 7 -#define O_RXDATAFIFO4__Rx9DataFifoStart 8 -#define W_RXDATAFIFO4__Rx9DataFifoStart 7 -#define O_RXDATAFIFO4__Rx9DataFifoSize 0 -#define W_RXDATAFIFO4__Rx9DataFifoSize 7 -#define R_RXDATAFIFO5 0x22E -#define O_RXDATAFIFO5__Rx10DataFifoStart 24 -#define W_RXDATAFIFO5__Rx10DataFifoStart 7 -#define O_RXDATAFIFO5__Rx10DataFifoSize 16 -#define W_RXDATAFIFO5__Rx10DataFifoSize 7 -#define O_RXDATAFIFO5__Rx11DataFifoStart 8 -#define W_RXDATAFIFO5__Rx11DataFifoStart 7 -#define O_RXDATAFIFO5__Rx11DataFifoSize 0 -#define W_RXDATAFIFO5__Rx11DataFifoSize 7 -#define R_RXDATAFIFO6 0x22F -#define O_RXDATAFIFO6__Rx12DataFifoStart 24 -#define W_RXDATAFIFO6__Rx12DataFifoStart 7 -#define O_RXDATAFIFO6__Rx12DataFifoSize 16 -#define W_RXDATAFIFO6__Rx12DataFifoSize 7 -#define O_RXDATAFIFO6__Rx13DataFifoStart 8 -#define W_RXDATAFIFO6__Rx13DataFifoStart 7 -#define O_RXDATAFIFO6__Rx13DataFifoSize 0 -#define W_RXDATAFIFO6__Rx13DataFifoSize 7 -#define R_RXDATAFIFO7 0x230 -#define O_RXDATAFIFO7__Rx14DataFifoStart 24 -#define W_RXDATAFIFO7__Rx14DataFifoStart 7 -#define O_RXDATAFIFO7__Rx14DataFifoSize 16 -#define W_RXDATAFIFO7__Rx14DataFifoSize 7 -#define O_RXDATAFIFO7__Rx15DataFifoStart 8 -#define W_RXDATAFIFO7__Rx15DataFifoStart 7 -#define O_RXDATAFIFO7__Rx15DataFifoSize 0 -#define W_RXDATAFIFO7__Rx15DataFifoSize 7 -#define R_XGMACPADCALIBRATION 0x231 -#define R_FREEQCARVE 0x233 -#define R_SPI4STATICDELAY0 0x240 -#define O_SPI4STATICDELAY0__DataLine7 28 -#define W_SPI4STATICDELAY0__DataLine7 4 -#define O_SPI4STATICDELAY0__DataLine6 24 -#define W_SPI4STATICDELAY0__DataLine6 4 -#define O_SPI4STATICDELAY0__DataLine5 20 -#define W_SPI4STATICDELAY0__DataLine5 4 -#define O_SPI4STATICDELAY0__DataLine4 16 -#define W_SPI4STATICDELAY0__DataLine4 4 -#define O_SPI4STATICDELAY0__DataLine3 12 -#define W_SPI4STATICDELAY0__DataLine3 4 -#define O_SPI4STATICDELAY0__DataLine2 8 -#define W_SPI4STATICDELAY0__DataLine2 4 -#define O_SPI4STATICDELAY0__DataLine1 4 -#define W_SPI4STATICDELAY0__DataLine1 4 -#define O_SPI4STATICDELAY0__DataLine0 0 -#define W_SPI4STATICDELAY0__DataLine0 4 -#define R_SPI4STATICDELAY1 0x241 -#define O_SPI4STATICDELAY1__DataLine15 28 -#define W_SPI4STATICDELAY1__DataLine15 4 -#define O_SPI4STATICDELAY1__DataLine14 24 -#define W_SPI4STATICDELAY1__DataLine14 4 -#define O_SPI4STATICDELAY1__DataLine13 20 -#define W_SPI4STATICDELAY1__DataLine13 4 -#define O_SPI4STATICDELAY1__DataLine12 16 -#define W_SPI4STATICDELAY1__DataLine12 4 -#define O_SPI4STATICDELAY1__DataLine11 12 -#define W_SPI4STATICDELAY1__DataLine11 4 -#define O_SPI4STATICDELAY1__DataLine10 8 -#define W_SPI4STATICDELAY1__DataLine10 4 -#define O_SPI4STATICDELAY1__DataLine9 4 -#define W_SPI4STATICDELAY1__DataLine9 4 -#define O_SPI4STATICDELAY1__DataLine8 0 -#define W_SPI4STATICDELAY1__DataLine8 4 -#define R_SPI4STATICDELAY2 0x242 -#define O_SPI4STATICDELAY0__TxStat1 8 -#define W_SPI4STATICDELAY0__TxStat1 4 -#define O_SPI4STATICDELAY0__TxStat0 4 -#define W_SPI4STATICDELAY0__TxStat0 4 -#define O_SPI4STATICDELAY0__RxControl 0 -#define W_SPI4STATICDELAY0__RxControl 4 -#define R_SPI4CONTROL 0x243 -#define O_SPI4CONTROL__StaticDelay 2 -#define O_SPI4CONTROL__LVDS_LVTTL 1 -#define O_SPI4CONTROL__SPI4Enable 0 -#define R_CLASSWATERMARKS 0x244 -#define O_CLASSWATERMARKS__Class0Watermark 24 -#define W_CLASSWATERMARKS__Class0Watermark 5 -#define O_CLASSWATERMARKS__Class1Watermark 16 -#define W_CLASSWATERMARKS__Class1Watermark 5 -#define O_CLASSWATERMARKS__Class3Watermark 0 -#define W_CLASSWATERMARKS__Class3Watermark 5 -#define R_RXWATERMARKS1 0x245 -#define O_RXWATERMARKS__Rx0DataWatermark 24 -#define W_RXWATERMARKS__Rx0DataWatermark 7 -#define O_RXWATERMARKS__Rx1DataWatermark 16 -#define W_RXWATERMARKS__Rx1DataWatermark 7 -#define O_RXWATERMARKS__Rx3DataWatermark 0 -#define W_RXWATERMARKS__Rx3DataWatermark 7 -#define R_RXWATERMARKS2 0x246 -#define O_RXWATERMARKS__Rx4DataWatermark 24 -#define W_RXWATERMARKS__Rx4DataWatermark 7 -#define O_RXWATERMARKS__Rx5DataWatermark 16 -#define W_RXWATERMARKS__Rx5DataWatermark 7 -#define O_RXWATERMARKS__Rx6DataWatermark 8 -#define W_RXWATERMARKS__Rx6DataWatermark 7 -#define O_RXWATERMARKS__Rx7DataWatermark 0 -#define W_RXWATERMARKS__Rx7DataWatermark 7 -#define R_RXWATERMARKS3 0x247 -#define O_RXWATERMARKS__Rx8DataWatermark 24 -#define W_RXWATERMARKS__Rx8DataWatermark 7 -#define O_RXWATERMARKS__Rx9DataWatermark 16 -#define W_RXWATERMARKS__Rx9DataWatermark 7 -#define O_RXWATERMARKS__Rx10DataWatermark 8 -#define W_RXWATERMARKS__Rx10DataWatermark 7 -#define O_RXWATERMARKS__Rx11DataWatermark 0 -#define W_RXWATERMARKS__Rx11DataWatermark 7 -#define R_RXWATERMARKS4 0x248 -#define O_RXWATERMARKS__Rx12DataWatermark 24 -#define W_RXWATERMARKS__Rx12DataWatermark 7 -#define O_RXWATERMARKS__Rx13DataWatermark 16 -#define W_RXWATERMARKS__Rx13DataWatermark 7 -#define O_RXWATERMARKS__Rx14DataWatermark 8 -#define W_RXWATERMARKS__Rx14DataWatermark 7 -#define O_RXWATERMARKS__Rx15DataWatermark 0 -#define W_RXWATERMARKS__Rx15DataWatermark 7 -#define R_FREEWATERMARKS 0x249 -#define O_FREEWATERMARKS__FreeOutWatermark 16 -#define W_FREEWATERMARKS__FreeOutWatermark 16 -#define O_FREEWATERMARKS__JumFrWatermark 8 -#define W_FREEWATERMARKS__JumFrWatermark 7 -#define O_FREEWATERMARKS__RegFrWatermark 0 -#define W_FREEWATERMARKS__RegFrWatermark 7 -#define R_EGRESSFIFOCARVINGSLOTS 0x24a - -#define CTRL_RES0 0 -#define CTRL_RES1 1 -#define CTRL_REG_FREE 2 -#define CTRL_JUMBO_FREE 3 -#define CTRL_CONT 4 -#define CTRL_EOP 5 -#define CTRL_START 6 -#define CTRL_SNGL 7 - -#define CTRL_B0_NOT_EOP 0 -#define CTRL_B0_EOP 1 - -#define R_ROUND_ROBIN_TABLE 0 -#define R_PDE_CLASS_0 0x300 -#define R_PDE_CLASS_1 0x302 -#define R_PDE_CLASS_2 0x304 -#define R_PDE_CLASS_3 0x306 - -#define R_MSG_TX_THRESHOLD 0x308 - -#define R_GMAC_JFR0_BUCKET_SIZE 0x320 -#define R_GMAC_RFR0_BUCKET_SIZE 0x321 -#define R_GMAC_TX0_BUCKET_SIZE 0x322 -#define R_GMAC_TX1_BUCKET_SIZE 0x323 -#define R_GMAC_TX2_BUCKET_SIZE 0x324 -#define R_GMAC_TX3_BUCKET_SIZE 0x325 -#define R_GMAC_JFR1_BUCKET_SIZE 0x326 -#define R_GMAC_RFR1_BUCKET_SIZE 0x327 - -#define R_XGS_TX0_BUCKET_SIZE 0x320 -#define R_XGS_TX1_BUCKET_SIZE 0x321 -#define R_XGS_TX2_BUCKET_SIZE 0x322 -#define R_XGS_TX3_BUCKET_SIZE 0x323 -#define R_XGS_TX4_BUCKET_SIZE 0x324 -#define R_XGS_TX5_BUCKET_SIZE 0x325 -#define R_XGS_TX6_BUCKET_SIZE 0x326 -#define R_XGS_TX7_BUCKET_SIZE 0x327 -#define R_XGS_TX8_BUCKET_SIZE 0x328 -#define R_XGS_TX9_BUCKET_SIZE 0x329 -#define R_XGS_TX10_BUCKET_SIZE 0x32A -#define R_XGS_TX11_BUCKET_SIZE 0x32B -#define R_XGS_TX12_BUCKET_SIZE 0x32C -#define R_XGS_TX13_BUCKET_SIZE 0x32D -#define R_XGS_TX14_BUCKET_SIZE 0x32E -#define R_XGS_TX15_BUCKET_SIZE 0x32F -#define R_XGS_JFR_BUCKET_SIZE 0x330 -#define R_XGS_RFR_BUCKET_SIZE 0x331 - -#define R_CC_CPU0_0 0x380 -#define R_CC_CPU1_0 0x388 -#define R_CC_CPU2_0 0x390 -#define R_CC_CPU3_0 0x398 -#define R_CC_CPU4_0 0x3a0 -#define R_CC_CPU5_0 0x3a8 -#define R_CC_CPU6_0 0x3b0 -#define R_CC_CPU7_0 0x3b8 - -#define XLR_GMAC_BLK_SZ (XLR_IO_GMAC_1_OFFSET - \ - XLR_IO_GMAC_0_OFFSET) - -/* Constants used for configuring the devices */ - -#define RGE_TX_THRESHOLD 1024 -#define RGE_TX_Q_SIZE 1024 - -#define MAC_B2B_IPG 88 - -#define NLGE_PREPAD_LEN 32 - -/* frame sizes need to be cacheline aligned */ -#define MAX_FRAME_SIZE (1536 + NLGE_PREPAD_LEN) -#define MAX_FRAME_SIZE_JUMBO 9216 -#define RGE_TX_THRESHOLD_BYTES ETHER_MAX_LEN - -#define MAC_SKB_BACK_PTR_SIZE SMP_CACHE_BYTES -#define MAC_PREPAD 0 -#define BYTE_OFFSET 2 -#define XLR_RX_BUF_SIZE (MAX_FRAME_SIZE + BYTE_OFFSET + \ - MAC_PREPAD + MAC_SKB_BACK_PTR_SIZE + SMP_CACHE_BYTES) -#define MAC_CRC_LEN 4 -#define MAX_NUM_MSGRNG_STN_CC 128 -#define MAX_MSG_SND_ATTEMPTS 100 /* 13 stns x 4 entry msg/stn + - headroom */ - -#define MAC_FRIN_TO_BE_SENT_THRESHOLD 16 - -#define MAX_NUM_DESC_SPILL 1024 -#define MAX_FRIN_SPILL (MAX_NUM_DESC_SPILL << 2) -#define MAX_FROUT_SPILL (MAX_NUM_DESC_SPILL << 2) -#define MAX_CLASS_0_SPILL (MAX_NUM_DESC_SPILL << 2) -#define MAX_CLASS_1_SPILL (MAX_NUM_DESC_SPILL << 2) -#define MAX_CLASS_2_SPILL (MAX_NUM_DESC_SPILL << 2) -#define MAX_CLASS_3_SPILL (MAX_NUM_DESC_SPILL << 2) - -#define XLR_MAX_CORE 8 - -#define XLR_MAX_NLNA 3 -#define XLR_MAX_MACS 8 -#define XLR_MAX_TX_FRAGS 14 -#define MAX_P2D_DESC_PER_PORT 512 - -#define PHY_STATUS_RETRIES 25000 - -/* Structs representing hardware data structures */ -struct size_1_desc { - uint64_t entry0; -}; - -struct size_2_desc { - uint64_t entry0; - uint64_t entry1; -}; - -struct size_3_desc { - uint64_t entry0; - uint64_t entry1; - uint64_t entry2; -}; - -struct size_4_desc { - uint64_t entry0; - uint64_t entry1; - uint64_t entry2; - uint64_t entry3; -}; - -struct fr_desc { - struct size_1_desc d1; -}; - -union rx_tx_desc { - struct size_2_desc d2; - /* struct size_3_desc d3; */ - /* struct size_4_desc d4; */ -}; - - -extern unsigned char xlr_base_mac_addr[]; - -/* Driver data structures and enums */ - -typedef enum { - xlr_mac_speed_10, xlr_mac_speed_100, - xlr_mac_speed_1000, xlr_mac_speed_rsvd -} xlr_mac_speed_t; - -typedef enum { - xlr_mac_duplex_auto, xlr_mac_duplex_half, - xlr_mac_duplex_full -} xlr_mac_duplex_t; - -typedef enum { - xlr_mac_link_down, - xlr_mac_link_up, -} xlr_mac_link_t; - -typedef enum { - xlr_mac_fc_auto, xlr_mac_fc_disabled, xlr_mac_fc_frame, - xlr_mac_fc_collision, xlr_mac_fc_carrier -} xlr_mac_fc_t; - -enum { - SGMII_SPEED_10 = 0x00000000, - SGMII_SPEED_100 = 0x02000000, - SGMII_SPEED_1000 = 0x04000000, -}; - -struct nlge_softc; - -/* - * A data-structure to hold a set of related ports. The "sense" in which they - * are related is defined by the user of this data-structure. - * - * One example: a set of ports that are controlled thru a single MDIO line. - */ -struct nlge_port_set { - struct nlge_softc **port_vec; - uint32_t vec_sz; -}; - -/* - * nlna_softc has Network Accelerator (NA) attributes that are necessary to - * configure the h/w registers of this block. All the commmon configuration - * for a set of GMAC ports controlled by an NA is done from here. - */ -struct nlna_softc { - device_t nlna_dev; - - uint32_t num_ports; - int na_type; - int mac_type; - xlr_reg_t *base; - - struct fr_desc *frin_spill; - struct fr_desc *frout_spill; - union rx_tx_desc *class_0_spill; - union rx_tx_desc *class_1_spill; - union rx_tx_desc *class_2_spill; - union rx_tx_desc *class_3_spill; - uint32_t rfrbucket; - uint32_t station_id; - - struct nlge_softc *child_sc[XLR_MAX_MACS]; - - /* - * Set of ports controlled/configured by the MII line - * of this network accelerator. - */ - struct nlge_port_set mdio_set; - struct nlge_softc *mdio_sc[XLR_MAX_MACS]; -}; - -struct nlge_softc { - struct ifnet *nlge_if; /* should be first member - cf. - mii.c:miibus_attach() */ - struct mii_data nlge_mii; - struct nlge_port_set *mdio_pset; - device_t nlge_dev; - device_t mii_bus; - xlr_reg_t *base; - xlr_reg_t *mii_base; - xlr_reg_t *pcs_addr; - xlr_reg_t *serdes_addr; - int port_type; - int if_flags; - xlr_mac_speed_t speed; - xlr_mac_duplex_t duplex; - xlr_mac_link_t link; - xlr_mac_fc_t flow_ctrl; - uint32_t id; - uint32_t instance; - uint32_t phy_addr; - uint32_t tx_bucket_id; - uint8_t dev_addr[ETHER_ADDR_LEN]; - struct mtx sc_lock; -}; - - -struct nlge_tx_desc { - uint64_t frag[XLR_MAX_TX_FRAGS + 2]; -}; - -#define MAX_TX_RING_SIZE (XLR_MAX_MACS * MAX_P2D_DESC_PER_PORT *\ - sizeof(struct p2d_tx_desc)) - -#define NLGE_WRITE(base, off, val) xlr_write_reg(base, off, val) -#define NLGE_READ(base, off) xlr_read_reg(base, off) -#define NLGE_UPDATE(base, off, val, mask) \ - do { \ - uint32_t rd_val, wrt_val; \ - rd_val = NLGE_READ(base, off); \ - wrt_val = (rd_val & ~mask) | (val & mask); \ - NLGE_WRITE(base, off, wrt_val); \ - } while (0) - -#define NLGE_LOCK_INIT(_sc, _name) \ - mtx_init(&(_sc)->sc_lock, _name, MTX_NETWORK_LOCK, MTX_DEF) -#define NLGE_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->sc_lock) -#define NLGE_LOCK(_sc) mtx_lock(&(_sc)->sc_lock) -#define NLGE_UNLOCK(_sc) mtx_unlock(&(_sc)->sc_lock) -#define NLGE_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->sc_lock, MA_OWNED) - Property changes on: head/sys/mips/rmi/dev/nlge/if_nlge.h ___________________________________________________________________ Deleted: svn:eol-style ## -1 +0,0 ## -native \ No newline at end of property Deleted: svn:keywords ## -1 +0,0 ## -FreeBSD=%H \ No newline at end of property Deleted: svn:mime-type ## -1 +0,0 ## -text/plain \ No newline at end of property Index: head/sys/mips/rmi/dev/iic/at24co2n.c =================================================================== --- head/sys/mips/rmi/dev/iic/at24co2n.c (revision 327460) +++ head/sys/mips/rmi/dev/iic/at24co2n.c (nonexistent) @@ -1,142 +0,0 @@ -/*- - * SPDX-License-Identifier: BSD-3-Clause - * - * Copyright (c) 2003-2009 RMI Corporation - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. Neither the name of RMI Corporation, nor the names of its contributors, - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - * - * RMI_BSD */ - -#include -__FBSDID("$FreeBSD$"); -/* - * reading eeprom for the mac address . - */ -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include -#include - -#include -#include - -#include "iicbus_if.h" - -#define AT24CO_EEPROM_ETH_MACADDR 0x20 - -struct at24co2n_softc { - uint32_t sc_addr; - device_t sc_dev; - uint8_t sc_mac_addr[6]; -}; - -static void at24co2n_read_mac(struct at24co2n_softc *); - -static int -at24co2n_probe(device_t dev) -{ - device_set_desc(dev, "AT24Co2N-10SE-2.7 EEPROM for mac address"); - return (0); -} - -static int -at24co2n_mac_sysctl(SYSCTL_HANDLER_ARGS) -{ - struct at24co2n_softc *sc = arg1; - char buf[24]; - int len; - uint8_t *p; - - at24co2n_read_mac(sc); - p = sc->sc_mac_addr; - len = snprintf(buf, sizeof(buf), "%02x:%02x:%02x:%02x:%02x:%02x", - p[0], p[1], p[2], p[3], p[4], p[5]); - return SYSCTL_OUT_STR(req, buf); -} - - -static int -at24co2n_attach(device_t dev) -{ - struct at24co2n_softc *sc = device_get_softc(dev); - struct sysctl_ctx_list *ctx = device_get_sysctl_ctx(dev); - struct sysctl_oid *tree = device_get_sysctl_tree(dev); - - if(sc == NULL) { - printf("at24co2n_attach device_get_softc failed\n"); - return (0); - } - sc->sc_dev = dev; - sc->sc_addr = iicbus_get_addr(dev); - - SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, - "eeprom-mac", CTLTYPE_STRING | CTLFLAG_RD, sc, 0, - at24co2n_mac_sysctl, "A", "mac address"); - - return (0); -} - -static void -at24co2n_read_mac(struct at24co2n_softc *sc) -{ - uint8_t addr = AT24CO_EEPROM_ETH_MACADDR; - struct iic_msg msgs[2] = { - { sc->sc_addr, IIC_M_WR, 1, &addr }, - { sc->sc_addr, IIC_M_RD, 6, sc->sc_mac_addr}, - }; - - iicbus_transfer(sc->sc_dev, msgs, 2); -} - -static device_method_t at24co2n_methods[] = { - DEVMETHOD(device_probe, at24co2n_probe), - DEVMETHOD(device_attach, at24co2n_attach), - - {0, 0}, -}; - -static driver_t at24co2n_driver = { - "at24co2n", - at24co2n_methods, - sizeof(struct at24co2n_softc), -}; -static devclass_t at24co2n_devclass; - -DRIVER_MODULE(at24co2n, iicbus, at24co2n_driver, at24co2n_devclass, 0, 0); -MODULE_VERSION(at24co2n, 1); -MODULE_DEPEND(at24co2n, iicbus, 1, 1, 1); Property changes on: head/sys/mips/rmi/dev/iic/at24co2n.c ___________________________________________________________________ Deleted: svn:eol-style ## -1 +0,0 ## -native \ No newline at end of property Deleted: svn:keywords ## -1 +0,0 ## -FreeBSD=%H \ No newline at end of property Deleted: svn:mime-type ## -1 +0,0 ## -text/plain \ No newline at end of property Index: head/sys/mips/rmi/dev/iic/max6657.c =================================================================== --- head/sys/mips/rmi/dev/iic/max6657.c (revision 327460) +++ head/sys/mips/rmi/dev/iic/max6657.c (nonexistent) @@ -1,160 +0,0 @@ -/*- - * SPDX-License-Identifier: BSD-3-Clause - * - * Copyright (c) 2003-2009 RMI Corporation - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. Neither the name of RMI Corporation, nor the names of its contributors, - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - * - * RMI_BSD */ - -#include -__FBSDID("$FreeBSD$"); -/* - * temperature sensor chip sitting on the I2C bus. - */ -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include -#include - -#include -#include - -#include -#include -#include "iicbus_if.h" - -#define MAX6657_EXT_TEMP 1 - -struct max6657_softc { - uint32_t sc_addr; - device_t sc_dev; - int sc_curtemp; - int sc_lastupdate; /* in ticks */ -}; - -static void max6657_update(struct max6657_softc *); -static int max6657_read(device_t dev, uint32_t addr, int reg) ; - -static int -max6657_probe(device_t dev) -{ - device_set_desc(dev, "MAX6657MSA Temperature Sensor"); - return (0); -} - -static int -max6657_sysctl_temp(SYSCTL_HANDLER_ARGS) -{ - struct max6657_softc *sc = arg1; - int temp; - - max6657_update(sc); - temp = sc->sc_curtemp ; - return sysctl_handle_int(oidp, &temp, 0, req); -} - -static int -max6657_attach(device_t dev) -{ - struct max6657_softc *sc = device_get_softc(dev); - struct sysctl_ctx_list *ctx = device_get_sysctl_ctx(dev); - struct sysctl_oid *tree = device_get_sysctl_tree(dev); - - if(sc==NULL) { - printf("max6657_attach device_get_softc failed\n"); - return (0); - } - sc->sc_dev = dev; - sc->sc_addr = iicbus_get_addr(dev); - - SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, - "temp", CTLTYPE_INT | CTLFLAG_RD, sc, 0, - max6657_sysctl_temp, "I", "operating temperature"); - - device_printf(dev, "Chip temperature {%d} Degree Celsius\n", - max6657_read(sc->sc_dev, sc->sc_addr, MAX6657_EXT_TEMP)); - - return (0); -} - -static int -max6657_read(device_t dev, uint32_t slave_addr, int reg) -{ - uint8_t addr = reg; - uint8_t data[1]; - struct iic_msg msgs[2] = { - { slave_addr, IIC_M_WR, 1, &addr }, - { slave_addr, IIC_M_RD, 1, data }, - }; - - return iicbus_transfer(dev, msgs, 2) != 0 ? -1 : data[0]; -} - - -static void -max6657_update(struct max6657_softc *sc) -{ - int v; - - /* NB: no point in updating any faster than the chip */ - if (ticks - sc->sc_lastupdate > hz) { - v = max6657_read(sc->sc_dev, sc->sc_addr, MAX6657_EXT_TEMP); - if (v >= 0) - sc->sc_curtemp = v; - sc->sc_lastupdate = ticks; - } -} - -static device_method_t max6657_methods[] = { - DEVMETHOD(device_probe, max6657_probe), - DEVMETHOD(device_attach, max6657_attach), - - {0, 0}, -}; - -static driver_t max6657_driver = { - "max6657", - max6657_methods, - sizeof(struct max6657_softc), -}; -static devclass_t max6657_devclass; - -DRIVER_MODULE(max6657, iicbus, max6657_driver, max6657_devclass, 0, 0); -MODULE_VERSION(max6657, 1); -MODULE_DEPEND(max6657, iicbus, 1, 1, 1); Property changes on: head/sys/mips/rmi/dev/iic/max6657.c ___________________________________________________________________ Deleted: svn:eol-style ## -1 +0,0 ## -native \ No newline at end of property Deleted: svn:keywords ## -1 +0,0 ## -FreeBSD=%H \ No newline at end of property Deleted: svn:mime-type ## -1 +0,0 ## -text/plain \ No newline at end of property Index: head/sys/mips/rmi/dev/xlr/debug.h =================================================================== --- head/sys/mips/rmi/dev/xlr/debug.h (revision 327460) +++ head/sys/mips/rmi/dev/xlr/debug.h (nonexistent) @@ -1,107 +0,0 @@ -/*- - * SPDX-License-Identifier: BSD-3-Clause - * - * Copyright (c) 2003-2009 RMI Corporation - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. Neither the name of RMI Corporation, nor the names of its contributors, - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - * - * RMI_BSD - * $FreeBSD$ - */ -#ifndef _RMI_DEBUG_H_ -#define _RMI_DEBUG_H_ - -#include - -enum { - //cacheline 0 - MSGRNG_INT, - MSGRNG_PIC_INT, - MSGRNG_MSG, - MSGRNG_EXIT_STATUS, - MSGRNG_MSG_CYCLES, - //cacheline 1 - NETIF_TX = 8, - NETIF_RX, - NETIF_TX_COMPLETE, - NETIF_TX_COMPLETE_TX, - NETIF_RX_CYCLES, - NETIF_TX_COMPLETE_CYCLES, - NETIF_TX_CYCLES, - NETIF_TIMER_START_Q, - //NETIF_REG_FRIN, - //NETIF_INT_REG, - //cacheline 2 - REPLENISH_ENTER = 16, - REPLENISH_ENTER_COUNT, - REPLENISH_CPU, - REPLENISH_FRIN, - REPLENISH_CYCLES, - NETIF_STACK_TX, - NETIF_START_Q, - NETIF_STOP_Q, - //cacheline 3 - USER_MAC_START = 24, - USER_MAC_INT = 24, - USER_MAC_TX_COMPLETE, - USER_MAC_RX, - USER_MAC_POLL, - USER_MAC_TX, - USER_MAC_TX_FAIL, - USER_MAC_TX_COUNT, - USER_MAC_FRIN, - //cacheline 4 - USER_MAC_TX_FAIL_GMAC_CREDITS = 32, - USER_MAC_DO_PAGE_FAULT, - USER_MAC_UPDATE_TLB, - USER_MAC_UPDATE_BIGTLB, - USER_MAC_UPDATE_TLB_PFN0, - USER_MAC_UPDATE_TLB_PFN1, - - XLR_MAX_COUNTERS = 40 -}; -extern int xlr_counters[MAXCPU][XLR_MAX_COUNTERS]; -extern __uint32_t msgrng_msg_cycles; - -#ifdef ENABLE_DEBUG -#define xlr_inc_counter(x) atomic_add_int(&xlr_counters[PCPU_GET(cpuid)][(x)], 1) -#define xlr_dec_counter(x) atomic_subtract_int(&xlr_counters[PCPU_GET(cpuid)][(x)], 1) -#define xlr_set_counter(x, value) atomic_set_int(&xlr_counters[PCPU_GET(cpuid)][(x)], (value)) -#define xlr_get_counter(x) (&xlr_counters[0][(x)]) - -#else /* default mode */ - -#define xlr_inc_counter(x) -#define xlr_dec_counter(x) -#define xlr_set_counter(x, value) -#define xlr_get_counter(x) - -#endif - -#define dbg_msg(fmt, args...) printf(fmt, ##args) -#define dbg_panic(fmt, args...) panic(fmt, ##args) - -#endif Property changes on: head/sys/mips/rmi/dev/xlr/debug.h ___________________________________________________________________ Deleted: svn:eol-style ## -1 +0,0 ## -native \ No newline at end of property Deleted: svn:keywords ## -1 +0,0 ## -FreeBSD=%H \ No newline at end of property Deleted: svn:mime-type ## -1 +0,0 ## -text/plain \ No newline at end of property Index: head/sys/mips/rmi/dev/xlr/xgmac_mdio.h =================================================================== --- head/sys/mips/rmi/dev/xlr/xgmac_mdio.h (revision 327460) +++ head/sys/mips/rmi/dev/xlr/xgmac_mdio.h (nonexistent) @@ -1,130 +0,0 @@ -/*- - * SPDX-License-Identifier: BSD-3-Clause - * - * Copyright (c) 2003-2009 RMI Corporation - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. Neither the name of RMI Corporation, nor the names of its contributors, - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - * - * $FreeBSD$ - * RMI_BSD */ -/* MDIO Low level Access routines */ -/* All Phy's accessed from GMAC0 base */ - -#ifndef _XGMAC_MDIO_H_ -#define _XGMAC_MDIO_H_ - -static inline int -xmdio_read(volatile unsigned int *_mmio, - uint32_t phy_addr, uint32_t address); -static inline void -xmdio_write(volatile unsigned int *_mmio, - uint32_t phy_addr, uint32_t address, uint32_t data); -static inline void -xmdio_address(volatile unsigned int *_mmio, - uint32_t phy_addr, uint32_t dev_ad, uint32_t address); - -static inline void -xmdio_address(volatile unsigned int *_mmio, - uint32_t phy_addr, uint32_t dev_ad, uint32_t address) -{ - uint32_t st_field = 0x0; - uint32_t op_type = 0x0; /* address operation */ - uint32_t ta_field = 0x2;/* ta field */ - - _mmio[0x11] = ((st_field & 0x3) << 30) | - ((op_type & 0x3) << 28) | - ((phy_addr & 0x1F) << 23) | - ((dev_ad & 0x1F) << 18) | - ((ta_field & 0x3) << 16) | - ((address & 0xffff) << 0); - - _mmio[0x10] = (0x0 << 3) | 0x5; - _mmio[0x10] = (0x1 << 3) | 0x5; - _mmio[0x10] = (0x0 << 3) | 0x5; - - /* wait for dev_ad cycle to complete */ - while (_mmio[0x14] & 0x1) { - }; - -} - -/* function prototypes */ -static inline int -xmdio_read(volatile unsigned int *_mmio, - uint32_t phy_addr, uint32_t address) -{ - uint32_t st_field = 0x0; - uint32_t op_type = 0x3; /* read operation */ - uint32_t ta_field = 0x2;/* ta field */ - uint32_t data = 0; - - xmdio_address(_mmio, phy_addr, 5, address); - _mmio[0x11] = ((st_field & 0x3) << 30) | - ((op_type & 0x3) << 28) | - ((phy_addr & 0x1F) << 23) | - ((5 & 0x1F) << 18) | - ((ta_field & 0x3) << 16) | - ((data & 0xffff) << 0); - - _mmio[0x10] = (0x0 << 3) | 0x5; - _mmio[0x10] = (0x1 << 3) | 0x5; - _mmio[0x10] = (0x0 << 3) | 0x5; - - /* wait for write cycle to complete */ - while (_mmio[0x14] & 0x1) { - }; - - data = _mmio[0x11] & 0xffff; - return (data); -} - -static inline void -xmdio_write(volatile unsigned int *_mmio, - uint32_t phy_addr, uint32_t address, uint32_t data) -{ - uint32_t st_field = 0x0; - uint32_t op_type = 0x1; /* write operation */ - uint32_t ta_field = 0x2;/* ta field */ - - xmdio_address(_mmio, phy_addr, 5, address); - _mmio[0x11] = ((st_field & 0x3) << 30) | - ((op_type & 0x3) << 28) | - ((phy_addr & 0x1F) << 23) | - ((5 & 0x1F) << 18) | - ((ta_field & 0x3) << 16) | - ((data & 0xffff) << 0); - - _mmio[0x10] = (0x0 << 3) | 0x5; - _mmio[0x10] = (0x1 << 3) | 0x5; - _mmio[0x10] = (0x0 << 3) | 0x5; - - /* wait for write cycle to complete */ - while (_mmio[0x14] & 0x1) { - }; - -} - -#endif Property changes on: head/sys/mips/rmi/dev/xlr/xgmac_mdio.h ___________________________________________________________________ Deleted: svn:eol-style ## -1 +0,0 ## -native \ No newline at end of property Deleted: svn:keywords ## -1 +0,0 ## -FreeBSD=%H \ No newline at end of property Deleted: svn:mime-type ## -1 +0,0 ## -text/plain \ No newline at end of property Index: head/sys/mips/rmi/dev/xlr/atx_cpld.h =================================================================== --- head/sys/mips/rmi/dev/xlr/atx_cpld.h (revision 327460) +++ head/sys/mips/rmi/dev/xlr/atx_cpld.h (nonexistent) @@ -1,56 +0,0 @@ -/*- - * SPDX-License-Identifier: BSD-3-Clause - * - * Copyright (c) 2003-2009 RMI Corporation - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. Neither the name of RMI Corporation, nor the names of its contributors, - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - * - * $FreeBSD$ - * RMI_BSD */ -#ifndef _RMI_ATX_CPLD_H_ -#define _RMI_ATX_CPLD_H_ - -/* - * bit_0 : xgs0 phy reset, bit_1 : xgs1 phy reset, bit_2 : HT reset, bit_3 : - * RTC reset, bit_4 : gmac phy soft reset, bit_5 : gmac phy hard reset, bit_6 - * : board reset, bit_7 : reserved - */ -#define ATX_CPLD_RESET_1 2 - -/* - * bit_0_2 : reserved, bit_3 : turn off xpak_0 tx, bit_4 : turn off xpak_1 - * tx, bit_5 : HT stop (active low), bit_6 : flash program enable, bit_7 : - * compact flash io mode - */ -#define ATX_CPLD_MISC_CTRL 8 - -/* - * bit_0 : reset tcam, bit_1 : reset xpak_0 module, bit_2 : reset xpak_1 - * module, bit_3_7 : reserved - */ -#define ATX_CPLD_RESET_2 9 - -#endif /* _RMI_ATX_CPLD_H_ */ Property changes on: head/sys/mips/rmi/dev/xlr/atx_cpld.h ___________________________________________________________________ Deleted: svn:eol-style ## -1 +0,0 ## -native \ No newline at end of property Deleted: svn:keywords ## -1 +0,0 ## -FreeBSD=%H \ No newline at end of property Deleted: svn:mime-type ## -1 +0,0 ## -text/plain \ No newline at end of property Index: head/sys/mips/rmi/dev/sec/rmisec.c =================================================================== --- head/sys/mips/rmi/dev/sec/rmisec.c (revision 327460) +++ head/sys/mips/rmi/dev/sec/rmisec.c (nonexistent) @@ -1,573 +0,0 @@ -/*- - * SPDX-License-Identifier: BSD-3-Clause - * - * Copyright (c) 2003-2009 RMI Corporation - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. Neither the name of RMI Corporation, nor the names of its contributors, - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - * - * RMI_BSD - */ - -#include -__FBSDID("$FreeBSD$"); - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include "cryptodev_if.h" - -#include -#include - -#include - -/* #define RMI_SEC_DEBUG */ - -void xlr_sec_print_data(struct cryptop *crp); - -static int xlr_sec_newsession(device_t dev, uint32_t * sidp, struct cryptoini *cri); -static int xlr_sec_freesession(device_t dev, uint64_t tid); -static int xlr_sec_process(device_t dev, struct cryptop *crp, int hint); - -static int xlr_sec_probe(device_t); -static int xlr_sec_attach(device_t); -static int xlr_sec_detach(device_t); - - -static device_method_t xlr_sec_methods[] = { - /* device interface */ - DEVMETHOD(device_probe, xlr_sec_probe), - DEVMETHOD(device_attach, xlr_sec_attach), - DEVMETHOD(device_detach, xlr_sec_detach), - - /* crypto device methods */ - DEVMETHOD(cryptodev_newsession, xlr_sec_newsession), - DEVMETHOD(cryptodev_freesession,xlr_sec_freesession), - DEVMETHOD(cryptodev_process, xlr_sec_process), - - DEVMETHOD_END -}; - -static driver_t xlr_sec_driver = { - "rmisec", - xlr_sec_methods, - sizeof(struct xlr_sec_softc) -}; -static devclass_t xlr_sec_devclass; - -DRIVER_MODULE(rmisec, iodi, xlr_sec_driver, xlr_sec_devclass, 0, 0); -MODULE_DEPEND(rmisec, crypto, 1, 1, 1); - -static int -xlr_sec_probe(device_t dev) -{ - - device_set_desc(dev, "XLR Security Accelerator"); - return (BUS_PROBE_DEFAULT); -} - -/* - * Attach an interface that successfully probed. - */ -static int -xlr_sec_attach(device_t dev) -{ - struct xlr_sec_softc *sc = device_get_softc(dev); - - sc->sc_dev = dev; - mtx_init(&sc->sc_mtx, device_get_nameunit(dev), "rmi crypto driver", - MTX_DEF); - sc->sc_cid = crypto_get_driverid(dev, CRYPTOCAP_F_HARDWARE); - if (sc->sc_cid < 0) { - printf("xlr_sec - error : could not get the driver id\n"); - goto error_exit; - } - if (crypto_register(sc->sc_cid, CRYPTO_DES_CBC, 0, 0) != 0) - printf("register failed for CRYPTO_DES_CBC\n"); - - if (crypto_register(sc->sc_cid, CRYPTO_3DES_CBC, 0, 0) != 0) - printf("register failed for CRYPTO_3DES_CBC\n"); - - if (crypto_register(sc->sc_cid, CRYPTO_AES_CBC, 0, 0) != 0) - printf("register failed for CRYPTO_AES_CBC\n"); - - if (crypto_register(sc->sc_cid, CRYPTO_ARC4, 0, 0) != 0) - printf("register failed for CRYPTO_ARC4\n"); - - if (crypto_register(sc->sc_cid, CRYPTO_MD5, 0, 0) != 0) - printf("register failed for CRYPTO_MD5\n"); - - if (crypto_register(sc->sc_cid, CRYPTO_SHA1, 0, 0) != 0) - printf("register failed for CRYPTO_SHA1\n"); - - if (crypto_register(sc->sc_cid, CRYPTO_MD5_HMAC, 0, 0) != 0) - printf("register failed for CRYPTO_MD5_HMAC\n"); - - if (crypto_register(sc->sc_cid, CRYPTO_SHA1_HMAC, 0, 0) != 0) - printf("register failed for CRYPTO_SHA1_HMAC\n"); - - xlr_sec_init(sc); - device_printf(dev, "Initialization complete!\n"); - return (0); - -error_exit: - return (ENXIO); - -} - -/* - * Detach an interface that successfully probed. - */ -static int -xlr_sec_detach(device_t dev) -{ - int sesn; - struct xlr_sec_softc *sc = device_get_softc(dev); - struct xlr_sec_session *ses = NULL; - symkey_desc_pt desc; - - for (sesn = 0; sesn < sc->sc_nsessions; sesn++) { - ses = &sc->sc_sessions[sesn]; - desc = (symkey_desc_pt) ses->desc_ptr; - free(desc->user.kern_src, M_DEVBUF); - free(desc->user.kern_dest, M_DEVBUF); - free(desc->next_src_buf, M_DEVBUF); - free(desc->next_dest_buf, M_DEVBUF); - free(ses->desc_ptr, M_DEVBUF); - } - - return (0); -} - -/* - * Allocate a new 'session' and return an encoded session id. 'sidp' - * contains our registration id, and should contain an encoded session - * id on successful allocation. - */ -static int -xlr_sec_newsession(device_t dev, u_int32_t *sidp, struct cryptoini *cri) -{ - struct cryptoini *c; - struct xlr_sec_softc *sc = device_get_softc(dev); - int mac = 0, cry = 0, sesn; - struct xlr_sec_session *ses = NULL; - - if (sidp == NULL || cri == NULL || sc == NULL) - return (EINVAL); - - if (sc->sc_sessions == NULL) { - ses = sc->sc_sessions = (struct xlr_sec_session *)malloc( - sizeof(struct xlr_sec_session), M_DEVBUF, M_NOWAIT); - if (ses == NULL) - return (ENOMEM); - sesn = 0; - sc->sc_nsessions = 1; - } else { - for (sesn = 0; sesn < sc->sc_nsessions; sesn++) { - if (!sc->sc_sessions[sesn].hs_used) { - ses = &sc->sc_sessions[sesn]; - break; - } - } - - if (ses == NULL) { - sesn = sc->sc_nsessions; - ses = (struct xlr_sec_session *)malloc((sesn + 1) * - sizeof(struct xlr_sec_session), M_DEVBUF, M_NOWAIT); - if (ses == NULL) - return (ENOMEM); - bcopy(sc->sc_sessions, ses, sesn * sizeof(*ses)); - bzero(sc->sc_sessions, sesn * sizeof(*ses)); - free(sc->sc_sessions, M_DEVBUF); - sc->sc_sessions = ses; - ses = &sc->sc_sessions[sesn]; - sc->sc_nsessions++; - } - } - bzero(ses, sizeof(*ses)); - ses->sessionid = sesn; - ses->desc_ptr = xlr_sec_allocate_desc(ses); - if (ses->desc_ptr == NULL) - return (ENOMEM); - ses->hs_used = 1; - - for (c = cri; c != NULL; c = c->cri_next) { - switch (c->cri_alg) { - case CRYPTO_MD5: - case CRYPTO_SHA1: - case CRYPTO_MD5_HMAC: - case CRYPTO_SHA1_HMAC: - if (mac) - return (EINVAL); - mac = 1; - ses->hs_mlen = c->cri_mlen; - if (ses->hs_mlen == 0) { - switch (c->cri_alg) { - case CRYPTO_MD5: - case CRYPTO_MD5_HMAC: - ses->hs_mlen = 16; - break; - case CRYPTO_SHA1: - case CRYPTO_SHA1_HMAC: - ses->hs_mlen = 20; - break; - } - } - break; - case CRYPTO_DES_CBC: - case CRYPTO_3DES_CBC: - case CRYPTO_AES_CBC: - /* XXX this may read fewer, does it matter? */ - /* - * read_random(ses->hs_iv, c->cri_alg == - * CRYPTO_AES_CBC ? XLR_SEC_AES_IV_LENGTH : - * XLR_SEC_IV_LENGTH); - */ - /* FALLTHROUGH */ - case CRYPTO_ARC4: - if (cry) - return (EINVAL); - cry = 1; - break; - default: - return (EINVAL); - } - } - if (mac == 0 && cry == 0) - return (EINVAL); - - *sidp = XLR_SEC_SID(device_get_unit(sc->sc_dev), sesn); - return (0); -} - -/* - * Deallocate a session. - * XXX this routine should run a zero'd mac/encrypt key into context ram. - * XXX to blow away any keys already stored there. - */ -static int -xlr_sec_freesession(device_t dev, u_int64_t tid) -{ - struct xlr_sec_softc *sc = device_get_softc(dev); - int session; - u_int32_t sid = CRYPTO_SESID2LID(tid); - - if (sc == NULL) - return (EINVAL); - - session = XLR_SEC_SESSION(sid); - if (session >= sc->sc_nsessions) - return (EINVAL); - - sc->sc_sessions[session].hs_used = 0; - return (0); -} - -#ifdef RMI_SEC_DEBUG - -void -xlr_sec_print_data(struct cryptop *crp) -{ - int i, key_len; - struct cryptodesc *crp_desc; - - printf("session id = 0x%llx, crp_ilen = %d, crp_olen=%d \n", - crp->crp_sid, crp->crp_ilen, crp->crp_olen); - - printf("crp_flags = 0x%x\n", crp->crp_flags); - - - printf("crp buf:\n"); - for (i = 0; i < crp->crp_ilen; i++) { - printf("%c ", crp->crp_buf[i]); - if (i % 10 == 0) - printf("\n"); - } - - printf("\n"); - printf("****************** desc ****************\n"); - crp_desc = crp->crp_desc; - printf("crd_skip=%d, crd_len=%d, crd_flags=0x%x, crd_alg=%d\n", - crp_desc->crd_skip, crp_desc->crd_len, crp_desc->crd_flags, crp_desc->crd_alg); - - key_len = crp_desc->crd_klen / 8; - printf("key(%d) :\n", key_len); - for (i = 0; i < key_len; i++) - printf("%d", crp_desc->crd_key[i]); - printf("\n"); - - printf(" IV : \n"); - for (i = 0; i < EALG_MAX_BLOCK_LEN; i++) - printf("%d", crp_desc->crd_iv[i]); - printf("\n"); - - printf("crd_next=%p\n", crp_desc->crd_next); - return; -} - -#endif - -static int -xlr_sec_process(device_t dev, struct cryptop *crp, int hint) -{ - struct xlr_sec_softc *sc = device_get_softc(dev); - struct xlr_sec_command *cmd = NULL; - int session, err; - struct cryptodesc *crd1, *crd2, *maccrd, *enccrd; - struct xlr_sec_session *ses; - - if (crp == NULL || crp->crp_callback == NULL) { - return (EINVAL); - } - session = XLR_SEC_SESSION(crp->crp_sid); - if (sc == NULL || session >= sc->sc_nsessions) { - err = EINVAL; - goto errout; - } - ses = &sc->sc_sessions[session]; - - cmd = &ses->cmd; - if (cmd == NULL) { - err = ENOMEM; - goto errout; - } - crd1 = crp->crp_desc; - if (crd1 == NULL) { - err = EINVAL; - goto errout; - } - crd2 = crd1->crd_next; - - if (crd2 == NULL) { - if (crd1->crd_alg == CRYPTO_MD5_HMAC || - crd1->crd_alg == CRYPTO_SHA1_HMAC || - crd1->crd_alg == CRYPTO_SHA1 || - crd1->crd_alg == CRYPTO_MD5) { - maccrd = crd1; - enccrd = NULL; - } else if (crd1->crd_alg == CRYPTO_DES_CBC || - crd1->crd_alg == CRYPTO_3DES_CBC || - crd1->crd_alg == CRYPTO_AES_CBC || - crd1->crd_alg == CRYPTO_ARC4) { - maccrd = NULL; - enccrd = crd1; - } else { - err = EINVAL; - goto errout; - } - } else { - if ((crd1->crd_alg == CRYPTO_MD5_HMAC || - crd1->crd_alg == CRYPTO_SHA1_HMAC || - crd1->crd_alg == CRYPTO_MD5 || - crd1->crd_alg == CRYPTO_SHA1) && - (crd2->crd_alg == CRYPTO_DES_CBC || - crd2->crd_alg == CRYPTO_3DES_CBC || - crd2->crd_alg == CRYPTO_AES_CBC || - crd2->crd_alg == CRYPTO_ARC4)) { - maccrd = crd1; - enccrd = crd2; - } else if ((crd1->crd_alg == CRYPTO_DES_CBC || - crd1->crd_alg == CRYPTO_ARC4 || - crd1->crd_alg == CRYPTO_3DES_CBC || - crd1->crd_alg == CRYPTO_AES_CBC) && - (crd2->crd_alg == CRYPTO_MD5_HMAC || - crd2->crd_alg == CRYPTO_SHA1_HMAC || - crd2->crd_alg == CRYPTO_MD5 || - crd2->crd_alg == CRYPTO_SHA1) && - (crd1->crd_flags & CRD_F_ENCRYPT)) { - enccrd = crd1; - maccrd = crd2; - } else { - err = EINVAL; - goto errout; - } - } - - bzero(&cmd->op, sizeof(xlr_sec_io_t)); - - cmd->op.source_buf = (uint64_t) (unsigned long)crp->crp_buf; - cmd->op.source_buf_size = crp->crp_ilen; - cmd->op.dest_buf = (uint64_t) (unsigned long)crp->crp_buf; - cmd->op.dest_buf_size = crp->crp_ilen; - cmd->op.num_packets = 1; - cmd->op.num_fragments = 1; - - if (cmd->op.source_buf_size > SEC_MAX_FRAG_LEN) { - ses->multi_frag_flag = 1; - } else { - ses->multi_frag_flag = 0; - } - - if (maccrd) { - cmd->maccrd = maccrd; - cmd->op.cipher_op = XLR_SEC_CIPHER_MODE_PASS; - cmd->op.cipher_mode = XLR_SEC_CIPHER_MODE_NONE; - cmd->op.cipher_type = XLR_SEC_CIPHER_TYPE_NONE; - cmd->op.cipher_init = 0; - cmd->op.cipher_offset = 0; - - switch (maccrd->crd_alg) { - case CRYPTO_MD5: - cmd->op.digest_type = XLR_SEC_DIGEST_TYPE_MD5; - cmd->op.digest_init = XLR_SEC_DIGEST_INIT_NEWKEY; - cmd->op.digest_src = XLR_SEC_DIGEST_SRC_DMA; - cmd->op.digest_offset = 0; - - cmd->op.cksum_type = XLR_SEC_CKSUM_TYPE_NOP; - cmd->op.cksum_src = XLR_SEC_CKSUM_SRC_CIPHER; - cmd->op.cksum_offset = 0; - - cmd->op.pkt_hmac = XLR_SEC_LOADHMACKEY_MODE_OLD; - cmd->op.pkt_hash = XLR_SEC_PADHASH_PAD; - cmd->op.pkt_hashbytes = XLR_SEC_HASHBYTES_ALL8; - cmd->op.pkt_next = XLR_SEC_NEXT_FINISH; - cmd->op.pkt_iv = XLR_SEC_PKT_IV_OLD; - cmd->op.pkt_lastword = XLR_SEC_LASTWORD_128; - - default: - printf("currently not handled\n"); - } - } - if (enccrd) { - cmd->enccrd = enccrd; - -#ifdef RMI_SEC_DEBUG - xlr_sec_print_data(crp); -#endif - - if (enccrd->crd_flags & CRD_F_ENCRYPT) { - cmd->op.cipher_op = XLR_SEC_CIPHER_OP_ENCRYPT; - } else - cmd->op.cipher_op = XLR_SEC_CIPHER_OP_DECRYPT; - - switch (enccrd->crd_alg) { - case CRYPTO_DES_CBC: - case CRYPTO_3DES_CBC: - if (enccrd->crd_alg == CRYPTO_DES_CBC) { - cmd->op.cipher_type = XLR_SEC_CIPHER_TYPE_DES; - memcpy(&cmd->op.crypt_key[0], enccrd->crd_key, XLR_SEC_DES_KEY_LENGTH); - } else { - cmd->op.cipher_type = XLR_SEC_CIPHER_TYPE_3DES; - //if (enccrd->crd_flags & CRD_F_KEY_EXPLICIT) - { - memcpy(&cmd->op.crypt_key[0], enccrd->crd_key, - XLR_SEC_3DES_KEY_LENGTH); - } - } - - cmd->op.cipher_mode = XLR_SEC_CIPHER_MODE_CBC; - cmd->op.cipher_init = XLR_SEC_CIPHER_INIT_NK; - cmd->op.cipher_offset = XLR_SEC_DES_IV_LENGTH; - - cmd->op.digest_type = XLR_SEC_DIGEST_TYPE_NONE; - cmd->op.digest_init = XLR_SEC_DIGEST_INIT_OLDKEY; - cmd->op.digest_src = XLR_SEC_DIGEST_SRC_DMA; - cmd->op.digest_offset = 0; - - cmd->op.cksum_type = XLR_SEC_CKSUM_TYPE_NOP; - cmd->op.cksum_src = XLR_SEC_CKSUM_SRC_CIPHER; - cmd->op.cksum_offset = 0; - - cmd->op.pkt_hmac = XLR_SEC_LOADHMACKEY_MODE_OLD; - cmd->op.pkt_hash = XLR_SEC_PADHASH_PAD; - cmd->op.pkt_hashbytes = XLR_SEC_HASHBYTES_ALL8; - cmd->op.pkt_next = XLR_SEC_NEXT_FINISH; - cmd->op.pkt_iv = XLR_SEC_PKT_IV_NEW; - cmd->op.pkt_lastword = XLR_SEC_LASTWORD_128; - - //if ((!(enccrd->crd_flags & CRD_F_IV_PRESENT)) && - if ((enccrd->crd_flags & CRD_F_IV_EXPLICIT)) { - memcpy(&cmd->op.initial_vector[0], enccrd->crd_iv, - XLR_SEC_DES_IV_LENGTH); - } - break; - - case CRYPTO_AES_CBC: - if (enccrd->crd_alg == CRYPTO_AES_CBC) { - cmd->op.cipher_type = XLR_SEC_CIPHER_TYPE_AES128; - //if (enccrd->crd_flags & CRD_F_KEY_EXPLICIT) - { - memcpy(&cmd->op.crypt_key[0], enccrd->crd_key, - XLR_SEC_AES128_KEY_LENGTH); - } - } - cmd->op.cipher_mode = XLR_SEC_CIPHER_MODE_CBC; - cmd->op.cipher_init = XLR_SEC_CIPHER_INIT_NK; - cmd->op.cipher_offset = XLR_SEC_AES_BLOCK_SIZE; - - cmd->op.digest_type = XLR_SEC_DIGEST_TYPE_NONE; - cmd->op.digest_init = XLR_SEC_DIGEST_INIT_OLDKEY; - cmd->op.digest_src = XLR_SEC_DIGEST_SRC_DMA; - cmd->op.digest_offset = 0; - - cmd->op.cksum_type = XLR_SEC_CKSUM_TYPE_NOP; - cmd->op.cksum_src = XLR_SEC_CKSUM_SRC_CIPHER; - cmd->op.cksum_offset = 0; - - cmd->op.pkt_hmac = XLR_SEC_LOADHMACKEY_MODE_OLD; - cmd->op.pkt_hash = XLR_SEC_PADHASH_PAD; - cmd->op.pkt_hashbytes = XLR_SEC_HASHBYTES_ALL8; - cmd->op.pkt_next = XLR_SEC_NEXT_FINISH; - cmd->op.pkt_iv = XLR_SEC_PKT_IV_NEW; - cmd->op.pkt_lastword = XLR_SEC_LASTWORD_128; - - //if (!(enccrd->crd_flags & CRD_F_IV_PRESENT)) { - if ((enccrd->crd_flags & CRD_F_IV_EXPLICIT)) { - memcpy(&cmd->op.initial_vector[0], enccrd->crd_iv, - XLR_SEC_AES_BLOCK_SIZE); - } - //} - break; - } - } - cmd->crp = crp; - cmd->session_num = session; - xlr_sec_setup(ses, cmd, (symkey_desc_pt) ses->desc_ptr); - - return (0); - -errout: - if (cmd != NULL) - free(cmd, M_DEVBUF); - crp->crp_etype = err; - crypto_done(crp); - return (err); -} Property changes on: head/sys/mips/rmi/dev/sec/rmisec.c ___________________________________________________________________ Deleted: svn:eol-style ## -1 +0,0 ## -native \ No newline at end of property Deleted: svn:keywords ## -1 +0,0 ## -FreeBSD=%H \ No newline at end of property Deleted: svn:mime-type ## -1 +0,0 ## -text/plain \ No newline at end of property Index: head/sys/mips/rmi/dev/sec/desc.h =================================================================== --- head/sys/mips/rmi/dev/sec/desc.h (revision 327460) +++ head/sys/mips/rmi/dev/sec/desc.h (nonexistent) @@ -1,3070 +0,0 @@ -/*- - * SPDX-License-Identifier: BSD-3-Clause - * - * Copyright (c) 2003-2009 RMI Corporation - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. Neither the name of RMI Corporation, nor the names of its contributors, - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - * - * $FreeBSD$ - * RMI_BSD */ -#ifndef _DESC_H_ -#define _DESC_H_ - - -#define ONE_BIT 0x0000000000000001ULL -#define TWO_BITS 0x0000000000000003ULL -#define THREE_BITS 0x0000000000000007ULL -#define FOUR_BITS 0x000000000000000fULL -#define FIVE_BITS 0x000000000000001fULL -#define SIX_BITS 0x000000000000003fULL -#define SEVEN_BITS 0x000000000000007fULL -#define EIGHT_BITS 0x00000000000000ffULL -#define NINE_BITS 0x00000000000001ffULL -#define ELEVEN_BITS 0x00000000000007ffULL -#define TWELVE_BITS 0x0000000000000fffULL -#define FOURTEEN_BITS 0x0000000000003fffULL -#define TWENTYFOUR_BITS 0x0000000000ffffffULL -#define THIRTY_TWO_BITS 0x00000000ffffffffULL -#define THIRTY_FIVE_BITS 0x00000007ffffffffULL -#define FOURTY_BITS 0x000000ffffffffffULL - -#define MSG_IN_CTL_LEN_BASE 40 -#define MSG_IN_CTL_ADDR_BASE 0 - -#define GET_FIELD(word,field) \ - ((word) & (field ## _MASK)) >> (field ## _LSB) - -#define FIELD_VALUE(field,value) (((value) & (field ## _BITS)) << (field ## _LSB)) - -/* - * NOTE: this macro expects 'word' to be uninitialized (i.e. zeroed) - */ -#define SET_FIELD(word,field,value) \ - { (word) |= (((value) & (field ## _BITS)) << (field ## _LSB)); } - -/* - * This macro clears 'word', then sets the value - */ -#define CLEAR_SET_FIELD(word,field,value) \ - { (word) &= ~((field ## _BITS) << (field ## _LSB)); \ - (word) |= (((value) & (field ## _BITS)) << (field ## _LSB)); } - -/* - * NOTE: May be used to build value specific mask - * (e.g. GEN_MASK(CTL_DSC_CPHR_3DES,CTL_DSC_CPHR_LSB) - */ -#define GEN_MASK(bits,lsb) ((bits) << (lsb)) - - - - -/* - * Security block data and control exchange - * - * A 2-word message ring descriptor is used to pass a pointer to the control descriptor data structure - * and a pointer to the packet descriptor data structure: - * - * 63 61 60 54 53 52 49 48 45 44 40 - * 39 5 4 0 - * --------------------------------------------------------------------------------------------------------------------------------------------------------- - * | Ctrl | Resp Dest Id Entry0 | IF_L2ALLOC | UNUSED | Control Length | UNUSED - * | 35 MSB of address of control descriptor data structure | Software Scratch0 - * | - * --------------------------------------------------------------------------------------------------------------------------------------------------------- - * 3 7 1 4 4 5 - * 35 5 - * - * 63 61 60 54 53 52 51 50 46 45 44 40 39 5 4 0 - * --------------------------------------------------------------------------------------------------------------------------------------------------------- - * | Ctrl | UNUSED | WRB_COH | WRB_L2ALLOC | DF_PTR_L2ALLOC | UNUSED | Data Length | UNUSED | 35 MSB of address of packet descriptor data structure | UNUSED | - * --------------------------------------------------------------------------------------------------------------------------------------------------------- - * 3 7 1 1 1 5 1 5 35 5 - * - * Addresses assumed to be cache-line aligned, i.e., Address[4:0] ignored (using 5'h00 instead) - * - * Control length is the number of control cachelines to be read so user needs - * to round up - * the control length to closest integer multiple of 32 bytes. Note that at - * present (08/12/04) - * the longest (sensical) ctrl structure is <= 416 bytes, i.e., 13 cachelines. - * - * The packet descriptor data structure size is fixed at 1 cacheline (32 bytes). - * This effectively makes "Data Length" a Load/NoLoad bit. NoLoad causes an abort. - * - * - * Upon completion of operation, the security block returns a 2-word free descriptor - * in the following format: - * - * 63 61 60 54 53 52 51 49 48 47 40 39 0 - * ---------------------------------------------------------------------------------------------------------------------------- - * | Ctrl | Destination Id | 2'b00 | Desc Ctrl | 1'b0 | Instruction Error | Address of control descriptor data structure | - * ---------------------------------------------------------------------------------------------------------------------------- - * | Ctrl | Destination Id | 2'b00 | Desc Ctrl | 1'b0 | Data Error | Address of packet descriptor data structure | - * ---------------------------------------------------------------------------------------------------------------------------- - * - * The Instruction and Data Error codes are enumerated in the - * ControlDescriptor and PacketDescriptor sections below - * - */ - - -/* - * Operating assumptions - * ===================== - * - * - * -> For all IpSec ops, I assume that all the IP/IPSec/TCP headers - * and the data are present at the specified source addresses. - * I also assume that all necessary header data already exists - * at the destination. Additionally, in AH I assume that all - * mutable fields (IP.{TOS, Flags, Offset, TTL, Header_Checksum}) - * and the AH.Authentication_Data have been zeroed by the client. - * - * - * -> In principle, the HW can calculate TCP checksums on both - * incoming and outgoing data; however, since the TCP header - * contains the TCP checksum of the plain payload and the header - * is encrypted, two passes would be necessary to do checksum + encryption - * for outgoing messages; - * therefore the checksum engine will likely only be used during decryption - * (incoming). - * - * - * -> For all operations involving TCP checksum, I assume the client has filled - * the TCP checksum field with the appropriate value: - * - * - 0 for generation phase - * - actual value for verification phase (expecting 0 result) - * - * - * -> For ESP tunnel, the original IP header exists between the end of the - * ESP header and the beginning of the TCP header; it is assumed that the - * maximum length of this header is 16 k(32bit)words (used in CkSum_Offset). - * - * - * -> The authentication data is merely written to the destination address; - * the client is left with the task of comparing to the data in packet - * in decrypt. - * - * -> PacketDescriptor_t.dstLLWMask relevant to AES CTR mode only but it will - * affect all AES-related operations. It will not affect DES/3DES/bypass ops. - * The mask is applied to data as it emerges from the AES engine for the sole - * purpose of providing the authenticator and cksum engines with correct data. - * CAVEAT: the HW does not mask the incoming data. It is the user's responsibility - * to set to 0 the corresponding data in memory. If the surplus data is not masked - * in memory, cksum/auth results will be incorrect if those engines receive data - * straight from memory (i.e., not from cipher, as it happens while decoding) - */ - -/* - * Fragmentation and offset related notes - * ====================================== - * - * - * A) Rebuilding packets from fragments on dword boundaries. The discussion - * below is exemplified by tests memcpy_all_off_frags and memcpy_same_off_frags - * - * 1) The Offset before data/iv on first fragment is ALWAYS written back - * Non-zero dst dword or global offsets may cause more data to be - * written than the user-specified length. - * - * - * Example: - * -------- - * - * Below is a source (first fragment) packet (@ ADD0 cache-aligned address). - * Assume we just copy it and relevant data starts on - * dword 3 so Cipher_Offset = IV_Offset = 3 (dwords). - * D0X denotes relevant data and G denotes dont care data. - * Offset data is also copied so Packet_Legth = 9 (dwords) * 8 = 72 (bytes) - * Segment_src_address = ADD0 - * - * If we want to, e.g., copy so that the relevant (i.e., D0X) data - * starts at (cache-aligned address) ADD1, we need to specify - * Dst_dword_offset = 1 so D00 is moved from dword position 3 to 0 on next cache-line - * Cipher_dst_address = ADD1 - 0x20 so D00 is written to ADD1 - * - * Note that the security engine always writes full cachelines - * therefore, data written to dword0 0 of ADD1 (denoted w/ ?) is what the sec pipe - * write back buffer contained from previous op. - * - * - * SOURCE: DESTINATION: - * ------- ------------ - * - * Segment_src_address = ADD0 Cipher_dst_address = ADD1 - 0x20 - * Packet_Legth = 72 Dst_dword_offset = 1 - * Cipher_Offset = 3 - * IV_Offset = 3 - * Use_IV = ANY - * - * - * - * 3 2 1 0 3 2 1 0 - * ----------------------- ----------------------- - * | D00 | G | G | G | <- ADD0 | G | G | G | ? | <- ADD1 - 0x20 - * ----------------------- ----------------------- - * | D04 | D03 | D02 | D01 | | D03 | D02 | D01 | D00 | <- ADD1 - * ----------------------- ----------------------- - * | | | | D05 | | | | D05 | D04 | - * ----------------------- ----------------------- - * - * 2) On fragments following the first, IV_Offset is overloaded to mean data offset - * (number of dwords to skip from beginning of cacheline before starting processing) - * and Use_IV is overloaded to mean do writeback the offset (in the clear). - * These fields in combination with Dst_dword_offset allow packet fragments with - * arbitrary boundaries/lengthd to be reasembled. - * - * - * Example: - * -------- - * - * Assume data above was first fragment of a packet we'd like to merge to - * (second) fragment below located at ADD2. The written data should follow - * the previous data without gaps or overwrites. To achieve this, one should - * assert the "Next" field on the previous fragment and use self-explanatory - * set of parameters below - * - * - * SOURCE: DESTINATION: - * ------- ------------ - * - * Segment_src_address = ADD2 Cipher_dst_address = ADD1 + 0x20 - * Packet_Legth = 104 Dst_dword_offset = 1 - * IV_Offset = 1 - * Use_IV = 0 - * - * - * - * 3 2 1 0 3 2 1 0 - * ----------------------- ----------------------- - * | D12 | D11 | D10 | G | <- ADD2 | G | G | G | ? | <- ADD1 - 0x20 - * ----------------------- ----------------------- - * | D16 | D15 | D14 | D13 | | D03 | D02 | D01 | D00 | <- ADD1 - * ----------------------- ----------------------- - * | D1a | D19 | D18 | D17 | | D11 | D10 | D05 | D04 | <- ADD1 + 0x20 - * ----------------------- ----------------------- - * | | | | D1b | | D15 | D14 | D13 | D12 | - * ----------------------- ----------------------- - * | D19 | D18 | D17 | D16 | - * ----------------------- - * | | | D1b | D1a | - * ----------------------- - * - * It is note-worthy that the merging can only be achieved if Use_IV is 0. Indeed, the security - * engine always writes full lines, therefore ADD1 + 0x20 will be re-written. Setting Use_IV to 0 - * will allow the sec pipe write back buffer to preserve D04, D05 from previous frag and only - * receive D10, D11 thereby preserving the integrity of the previous data. - * - * 3) On fragments following the first, !UseIV in combination w/ Dst_dword_offset >= (4 - IV_Offset) - * will cause a wraparound of the write thus achieving all 16 possible (Initial_Location, Final_Location) - * combinations for the data. - * - * - * Example: - * -------- - * - * Contiguously merging 2 data sets above with a third located at ADD3. If this is the last fragment, - * reset its Next bit. - * - * - * SOURCE: DESTINATION: - * ------- ------------ - * - * Segment_src_address = ADD3 Cipher_dst_address = ADD1 + 0x80 - * Packet_Legth = 152 Dst_dword_offset = 3 - * IV_Offset = 3 - * Use_IV = 0 - * - * - * - * 3 2 1 0 3 2 1 0 - * ----------------------- ----------------------- - * | D20 | G | G | G | <- ADD2 | G | G | G | ? | <- ADD1 - 0x20 - * ----------------------- ----------------------- - * | D24 | D23 | D22 | D21 | | D03 | D02 | D01 | D00 | <- ADD1 - * ----------------------- ----------------------- - * | D28 | D27 | D26 | D25 | | D11 | D10 | D05 | D04 | <- ADD1 + 0x20 - * ----------------------- ----------------------- - * | D2c | D2b | D2a | D29 | | D15 | D14 | D13 | D12 | - * ----------------------- ----------------------- - * | | D2f | D2e | D2d | | D19 | D18 | D17 | D16 | - * ----------------------- ----------------------- - * | D21 | D20 | D1b | D1a | <- ADD1 + 0x80 - * ----------------------- - * | D25 | D24 | D23 | D22 | - * ----------------------- - * | D29 | D28 | D27 | D26 | - * ----------------------- - * | D2d | D2c | D2b | D2a | - * ----------------------- - * |(D2d)|(D2c)| D2f | D2e | - * ----------------------- - * - * It is worth noticing that always writing full-lines causes the last 2 dwords in the reconstituted - * packet to be unnecessarily written: (D2d) and (D2c) - * - * - * - * B) Implications of fragmentation on AES - * - * 1) AES is a 128 bit block cipher; therefore it requires an even dword total data length - * Data fragments (provided there are more than 1) are allowed to have odd dword - * data lengths provided the total length (cumulated over fragments) is an even dword - * count; an error will be generated otherwise, upon receiving the last fragment descriptor - * (see error conditions below). - * - * 2) While using fragments with AES, a fragment (other than first) starting with a != 0 (IV) offset - * while the subsequent total dword count given to AES is odd may not be required to write - * its offset (UseIV). Doing so will cause an error (see error conditions below). - * - * - * Example: - * -------- - * - * Suppose the first fragment has an odd DATA dword count and USES AES (as seen below) - * - * SOURCE: DESTINATION: - * ------- ------------ - * - * Segment_src_address = ADD0 Cipher_dst_address = ADD1 - * Packet_Legth = 64 Dst_dword_offset = 1 - * Cipher_Offset = 3 - * IV_Offset = 1 - * Use_IV = 1 - * Cipher = Any AES - * Next = 1 - * - * - * - * - * 3 2 1 0 3 2 1 0 - * ----------------------- ----------------------- - * | D00 | IV1 | IV0 | G | <- ADD0 | E00 | IV1 | IV0 | G | <- ADD1 - * ----------------------- ----------------------- - * | D04 | D03 | D02 | D01 | | X | E03 | E02 | E01 | - * ----------------------- ----------------------- - * - * At the end of processing of the previous fragment, the AES engine input buffer has D04 - * and waits for next dword, therefore the writeback buffer cannot finish writing the fragment - * to destination (X instead of E04). - * - * If a second fragment now arrives with a non-0 offset and requires the offset data to be - * written to destination, the previous write (still needing the arrival of the last dword - * required by the AES to complete the previous operation) cannot complete before the present - * should start causing a deadlock. - */ - -/* - * Command Control Word for Message Ring Descriptor - */ - -/* #define MSG_CMD_CTL_CTL */ -#define MSG_CMD_CTL_CTL_LSB 61 -#define MSG_CMD_CTL_CTL_BITS THREE_BITS -#define MSG_CMD_CTL_CTL_MASK (MSG_CMD_CTL_CTL_BITS << MSG_CMD_CTL_CTL_LSB) - -/* #define MSG_CMD_CTL_ID */ -#define MSG_CMD_CTL_ID_LSB 54 -#define MSG_CMD_CTL_ID_BITS SEVEN_BITS -#define MSG_CMD_CTL_ID_MASK (MSG_CMD_CTL_ID_BITS << MSG_CMD_CTL_ID_LSB) - -/* #define MSG_CMD_CTL_LEN */ -#define MSG_CMD_CTL_LEN_LSB 45 -#define MSG_CMD_CTL_LEN_BITS FOUR_BITS -#define MSG_CMD_CTL_LEN_MASK (MSG_CMD_CTL_LEN_BITS << MSG_CMD_CTL_LEN_LSB) - - -/* #define MSG_CMD_CTL_ADDR */ -#define MSG_CMD_CTL_ADDR_LSB 0 -#define MSG_CMD_CTL_ADDR_BITS FOURTY_BITS -#define MSG_CMD_CTL_ADDR_MASK (MSG_CMD_CTL_ADDR_BITS << MSG_CMD_CTL_ADDR_LSB) - -#define MSG_CMD_CTL_MASK (MSG_CMD_CTL_CTL_MASK | \ - MSG_CMD_CTL_LEN_MASK | MSG_CMD_CTL_ADDR_MASK) - -/* - * Command Data Word for Message Ring Descriptor - */ - -/* #define MSG_IN_DATA_CTL */ -#define MSG_CMD_DATA_CTL_LSB 61 -#define MSG_CMD_DATA_CTL_BITS THREE_BITS -#define MSG_CMD_DATA_CTL_MASK (MSG_CMD_DATA_CTL_BITS << MSG_CMD_DATA_CTL_LSB) - -/* #define MSG_CMD_DATA_LEN */ -#define MSG_CMD_DATA_LEN_LOAD 1 -#define MSG_CMD_DATA_LEN_LSB 45 -#define MSG_CMD_DATA_LEN_BITS ONE_BIT -#define MSG_CMD_DATA_LEN_MASK (MSG_CMD_DATA_LEN_BITS << MSG_CMD_DATA_LEN_LSB) - -/* #define MSG_CMD_DATA_ADDR */ -#define MSG_CMD_DATA_ADDR_LSB 0 -#define MSG_CMD_DATA_ADDR_BITS FOURTY_BITS -#define MSG_CMD_DATA_ADDR_MASK (MSG_CMD_DATA_ADDR_BITS << MSG_CMD_DATA_ADDR_LSB) - -#define MSG_CMD_DATA_MASK (MSG_CMD_DATA_CTL_MASK | \ - MSG_CMD_DATA_LEN_MASK | MSG_CMD_DATA_ADDR_MASK) - - -/* - * Upon completion of operation, the Sec block returns a 2-word free descriptor - * in the following format: - * - * 63 61 60 54 53 52 51 49 48 40 39 0 - * ---------------------------------------------------------------------------- - * | Ctrl | Destination Id | 2'b00 | Desc Ctrl | Control Error | Source Address | - * ---------------------------------------------------------------------------- - * | Ctrl | Destination Id | 2'b00 | Desc Ctrl | Data Error | Dest Address | - * ---------------------------------------------------------------------------- - * - * The Control and Data Error codes are enumerated below - * - * Error conditions - * ================ - * - * Control Error Code Control Error Condition - * ------------------ --------------------------- - * 9'h000 No Error - * 9'h001 Unknown Cipher Op ( Cipher == 3'h{6,7}) - * 9'h002 Unknown or Illegal Mode ((Mode == 3'h{2,3,4} & !AES) | (Mode == 3'h{5,6,7})) - * 9'h004 Unsupported CkSum Src (CkSum_Src == 2'h{2,3} & CKSUM) - * 9'h008 Forbidden CFB Mask (AES & CFBMode & UseNewKeysCFBMask & CFBMask[7] & (| CFBMask[6:0])) - * 9'h010 Unknown Ctrl Op ((| Ctrl[63:37]) | (| Ctrl[15:14])) - * 9'h020 UNUSED - * 9'h040 UNUSED - * 9'h080 Data Read Error - * 9'h100 Descriptor Ctrl Field Error (D0.Ctrl != SOP || D1.Ctrl != EOP) - * - * Data Error Code Data Error Condition - * --------------- -------------------- - * 9'h000 No Error - * 9'h001 Insufficient Data To Cipher (Packet_Length <= (Cipher_Offset or IV_Offset)) - * 9'h002 Illegal IV Location ((Cipher_Offset < IV_Offset) | (Cipher_Offset <= IV_Offset & AES & ~CTR)) - * 9'h004 Illegal Wordcount To AES (Packet_Length[3] != Cipher_Offset[0] & AES) - * 9'h008 Illegal Pad And ByteCount Spec (Hash_Byte_Count != 0 & !Pad_Hash) - * 9'h010 Insufficient Data To CkSum ({Packet_Length, 1'b0} <= CkSum_Offset) - * 9'h020 Unknown Data Op ((| dstLLWMask[63:60]) | (| dstLLWMask[57:40]) | (| authDst[63:40]) | (| ckSumDst[63:40])) - * 9'h040 Insufficient Data To Auth ({Packet_Length} <= Auth_Offset) - * 9'h080 Data Read Error - * 9'h100 UNUSED - */ - -/* - * Result Control Word for Message Ring Descriptor - */ - -/* #define MSG_RSLT_CTL_CTL */ -#define MSG_RSLT_CTL_CTL_LSB 61 -#define MSG_RSLT_CTL_CTL_BITS THREE_BITS -#define MSG_RSLT_CTL_CTL_MASK \ - (MSG_RSLT_CTL_CTL_BITS << MSG_RSLT_CTL_CTL_LSB) - -/* #define MSG_RSLT_CTL_DST_ID */ -#define MSG_RSLT_CTL_DST_ID_LSB 54 -#define MSG_RSLT_CTL_DST_ID_BITS SEVEN_BITS -#define MSG_RSLT_CTL_DST_ID_MASK \ - (MSG_RSLT_CTL_DST_ID_BITS << MSG_RSLT_CTL_DST_ID_LSB) - -/* #define MSG_RSLT_CTL_DSC_CTL */ -#define MSG_RSLT_CTL_DSC_CTL_LSB 49 -#define MSG_RSLT_CTL_DSC_CTL_BITS THREE_BITS -#define MSG_RSLT_CTL_DSC_CTL_MASK \ - (MSG_RSLT_CTL_DSC_CTL_BITS << MSG_RSLT_CTL_DSC_CTL_LSB) - -/* #define MSG_RSLT_CTL_INST_ERR */ -#define MSG_RSLT_CTL_INST_ERR_LSB 40 -#define MSG_RSLT_CTL_INST_ERR_BITS NINE_BITS -#define MSG_RSLT_CTL_INST_ERR_MASK \ - (MSG_RSLT_CTL_INST_ERR_BITS << MSG_RSLT_CTL_INST_ERR_LSB) - -/* #define MSG_RSLT_CTL_DSC_ADDR */ -#define MSG_RSLT_CTL_DSC_ADDR_LSB 0 -#define MSG_RSLT_CTL_DSC_ADDR_BITS FOURTY_BITS -#define MSG_RSLT_CTL_DSC_ADDR_MASK \ - (MSG_RSLT_CTL_DSC_ADDR_BITS << MSG_RSLT_CTL_DSC_ADDR_LSB) - -/* #define MSG_RSLT_CTL_MASK */ -#define MSG_RSLT_CTL_MASK \ - (MSG_RSLT_CTL_CTRL_MASK | MSG_RSLT_CTL_DST_ID_MASK | \ - MSG_RSLT_CTL_DSC_CTL_MASK | MSG_RSLT_CTL_INST_ERR_MASK | \ - MSG_RSLT_CTL_DSC_ADDR_MASK) - -/* - * Result Data Word for Message Ring Descriptor - */ -/* #define MSG_RSLT_DATA_CTL */ -#define MSG_RSLT_DATA_CTL_LSB 61 -#define MSG_RSLT_DATA_CTL_BITS THREE_BITS -#define MSG_RSLT_DATA_CTL_MASK \ - (MSG_RSLT_DATA_CTL_BITS << MSG_RSLT_DATA_CTL_LSB) - -/* #define MSG_RSLT_DATA_DST_ID */ -#define MSG_RSLT_DATA_DST_ID_LSB 54 -#define MSG_RSLT_DATA_DST_ID_BITS SEVEN_BITS -#define MSG_RSLT_DATA_DST_ID_MASK \ - (MSG_RSLT_DATA_DST_ID_BITS << MSG_RSLT_DATA_DST_ID_LSB) - -/* #define MSG_RSLT_DATA_DSC_CTL */ -#define MSG_RSLT_DATA_DSC_CTL_LSB 49 -#define MSG_RSLT_DATA_DSC_CTL_BITS THREE_BITS -#define MSG_RSLT_DATA_DSC_CTL_MASK \ - (MSG_RSLT_DATA_DSC_CTL_BITS << MSG_RSLT_DATA_DSC_CTL_LSB) - -/* #define MSG_RSLT_DATA_INST_ERR */ -#define MSG_RSLT_DATA_INST_ERR_LSB 40 -#define MSG_RSLT_DATA_INST_ERR_BITS NINE_BITS -#define MSG_RSLT_DATA_INST_ERR_MASK \ - (MSG_RSLT_DATA_INST_ERR_BITS << MSG_RSLT_DATA_INST_ERR_LSB) - -/* #define MSG_RSLT_DATA_DSC_ADDR */ -#define MSG_RSLT_DATA_DSC_ADDR_LSB 0 -#define MSG_RSLT_DATA_DSC_ADDR_BITS FOURTY_BITS -#define MSG_RSLT_DATA_DSC_ADDR_MASK \ - (MSG_RSLT_DATA_DSC_ADDR_BITS << MSG_RSLT_DATA_DSC_ADDR_LSB) - -#define MSG_RSLT_DATA_MASK \ - (MSG_RSLT_DATA_CTRL_MASK | MSG_RSLT_DATA_DST_ID_MASK | \ - MSG_RSLT_DATA_DSC_CTL_MASK | MSG_RSLT_DATA_INST_ERR_MASK | \ - MSG_RSLT_DATA_DSC_ADDR_MASK) - - -/* - * Common Message Definitions - * - */ - -/* #define MSG_CTL_OP_ADDR */ -#define MSG_CTL_OP_ADDR_LSB 0 -#define MSG_CTL_OP_ADDR_BITS FOURTY_BITS -#define MSG_CTL_OP_ADDR_MASK (MSG_CTL_OP_ADDR_BITS << MSG_CTL_OP_ADDR_LSB) - -#define MSG_CTL_OP_TYPE -#define MSG_CTL_OP_TYPE_LSB 3 -#define MSG_CTL_OP_TYPE_BITS TWO_BITS -#define MSG_CTL_OP_TYPE_MASK \ - (MSG_CTL_OP_TYPE_BITS << MSG_CTL_OP_TYPE_LSB) - -#define MSG0_CTL_OP_ENGINE_SYMKEY 0x01 -#define MSG0_CTL_OP_ENGINE_PUBKEY 0x02 - -#define MSG1_CTL_OP_SYMKEY_PIPE0 0x00 -#define MSG1_CTL_OP_SYMKEY_PIPE1 0x01 -#define MSG1_CTL_OP_SYMKEY_PIPE2 0x02 -#define MSG1_CTL_OP_SYMKEY_PIPE3 0x03 - -#define MSG1_CTL_OP_PUBKEY_PIPE0 0x00 -#define MSG1_CTL_OP_PUBKEY_PIPE1 0x01 -#define MSG1_CTL_OP_PUBKEY_PIPE2 0x02 -#define MSG1_CTL_OP_PUBKEY_PIPE3 0x03 - - -/* /----------------------------------------\ - * | | - * | ControlDescriptor_s datastructure | - * | | - * \----------------------------------------/ - * - * - * ControlDescriptor_t.Instruction - * ------------------------------- - * - * 63 44 43 42 41 40 39 35 34 32 31 29 28 - * -------------------------------------------------------------------------------------------------------------------- - * || UNUSED || OverrideCipher | Arc4Wait4Save | SaveArc4State | LoadArc4State | Arc4KeyLen | Cipher | Mode | InCp_Key || ... CONT ... - * -------------------------------------------------------------------------------------------------------------------- - * 20 1 1 1 1 5 3 3 1 - * <-----------------------------------------------CIPHER---------------------------------------------------> - * - * 27 25 24 23 22 21 20 19 17 16 15 0 - * ----------------------------------------------------------------------------- - * || UNUSED | Hash_Hi | HMAC | Hash_Lo | InHs_Key || UNUSED || CkSum || UNUSED || - * ----------------------------------------------------------------------------- - * 3 1 1 2 1 3 1 16 - * <---------------------HASH---------------------><-----------CKSUM-----------> - * - * X0 CIPHER.Arc4Wait4Save = If op is Arc4 and it requires state saving, then - * setting this bit will cause the current op to - * delay subsequent op loading until saved state data - * becomes visible. - * CIPHER.OverrideCipher = Override encryption if PacketDescriptor_t.dstDataSettings.CipherPrefix - * is set; data will be copied out (and optionally auth/cksum) - * in the clear. This is used in GCM mode if auth only as we - * still need E(K, 0) calculated by cipher. Engine behavior is - * undefined if this bit is set and CipherPrefix is not. - * X0 SaveArc4State = Save Arc4 state at the end of Arc4 operation - * X0 LoadArc4State = Load Arc4 state at the beginning of an Arc4 operation - * This overriden by the InCp_Key setting for Arc4 - * Arc4KeyLen = Length in bytes of Arc4 key (0 is interpreted as 32) - * Ignored for other ciphers - * For ARC4, IFetch/IDecode will always read exactly 4 - * consecutive dwords into its CipherKey{0,3} regardless - * of this quantity; it will however only use the specified - * number of bytes. - * Cipher = 3'b000 Bypass - * 3'b001 DES - * 3'b010 3DES - * 3'b011 AES 128-bit key - * 3'b100 AES 192-bit key - * 3'b101 AES 256-bit key - * 3'b110 ARC4 - * 3'b111 Kasumi f8 - * Remainder UNDEFINED - * Mode = 3'b000 ECB - * 3'b001 CBC - * 3'b010 CFB (AES only, otherwise undefined) - * 3'b011 OFB (AES only, otherwise undefined) - * 3'b100 CTR (AES only, otherwise undefined) - * 3'b101 F8 (AES only, otherwise undefined) - * Remainder UNDEFINED - * InCp_Key = 1'b0 Preserve old Cipher Keys - * 1'b1 Load new Cipher Keys from memory to local registers - * and recalculate the Arc4 Sbox if Arc4 Cipher chosen; - * This overrides LoadArc4State setting. - * HASH.HMAC = 1'b0 Hash without HMAC - * 1'b1 Hash with HMAC - * Needs to be set to 0 for GCM and Kasumi F9 authenticators - * otherwise unpredictable results will be generated - * Hash = 2'b00 Hash NOP - * 2'b01 MD5 - * 2'b10 SHA-1 - * 2'b11 SHA-256 - * 3'b100 SHA-384 - * 3'b101 SHA-512 - * 3'b110 GCM - * 3'b111 Kasumi f9 - * InHs_Key = 1'b0 Preserve old HMAC Keys - * If GCM is selected as authenticator, leaving this bit - * at 0 will cause the engine to use the old H value. - * It will use the old SCI inside the decoder if - * CFBMask[1:0] == 2'b11. - * If Kasumi F9 authenticator, using 0 preserves - * old keys (IK) in decoder. - * 1'b1 Load new HMAC Keys from memory to local registers - * Setting this bit while Cipher=Arc4 and LoadArc4State=1 - * causes the decoder to load the Arc4 state from the - * cacheline following the HMAC keys (Whether HASH.HMAC - * is set or not). - * If GCM is selected as authenticator, setting this bit - * causes both H (16 bytes) and SCI (8 bytes) to be loaded - * from memory to the decoder. H will be loaded to the engine - * but SCI is only loaded to the engine if CFBMask[1:0] == 2'b11. - * If Kasumi F9 authenticator, using 1 loads new keys (IK) - * from memory to decoder. - * CHECKSUM.CkSum = 1'b0 CkSum NOP - * 1'b1 INTERNET_CHECKSUM - * - * - * - */ - - /* #define CTRL_DSC_OVERRIDECIPHER */ -#define CTL_DSC_OVERRIDECIPHER_OFF 0 -#define CTL_DSC_OVERRIDECIPHER_ON 1 -#define CTL_DSC_OVERRIDECIPHER_LSB 43 -#define CTL_DSC_OVERRIDECIPHER_BITS ONE_BIT -#define CTL_DSC_OVERRIDECIPHER_MASK (CTL_DSC_OVERRIDECIPHER_BITS << CTL_DSC_OVERRIDECIPHER_LSB) - -/* #define CTRL_DSC_ARC4_WAIT4SAVE */ -#define CTL_DSC_ARC4_WAIT4SAVE_OFF 0 -#define CTL_DSC_ARC4_WAIT4SAVE_ON 1 -#define CTL_DSC_ARC4_WAIT4SAVE_LSB 42 -#define CTL_DSC_ARC4_WAIT4SAVE_BITS ONE_BIT -#define CTL_DSC_ARC4_WAIT4SAVE_MASK (CTL_DSC_ARC4_WAIT4SAVE_BITS << CTL_DSC_ARC4_WAIT4SAVE_LSB) - -/* #define CTRL_DSC_ARC4_SAVESTATE */ -#define CTL_DSC_ARC4_SAVESTATE_OFF 0 -#define CTL_DSC_ARC4_SAVESTATE_ON 1 -#define CTL_DSC_ARC4_SAVESTATE_LSB 41 -#define CTL_DSC_ARC4_SAVESTATE_BITS ONE_BIT -#define CTL_DSC_ARC4_SAVESTATE_MASK (CTL_DSC_ARC4_SAVESTATE_BITS << CTL_DSC_ARC4_SAVESTATE_LSB) - -/* #define CTRL_DSC_ARC4_LOADSTATE */ -#define CTL_DSC_ARC4_LOADSTATE_OFF 0 -#define CTL_DSC_ARC4_LOADSTATE_ON 1 -#define CTL_DSC_ARC4_LOADSTATE_LSB 40 -#define CTL_DSC_ARC4_LOADSTATE_BITS ONE_BIT -#define CTL_DSC_ARC4_LOADSTATE_MASK (CTL_DSC_ARC4_LOADSTATE_BITS << CTL_DSC_ARC4_LOADSTATE_LSB) - -/* #define CTRL_DSC_ARC4_KEYLEN */ -#define CTL_DSC_ARC4_KEYLEN_LSB 35 -#define CTL_DSC_ARC4_KEYLEN_BITS FIVE_BITS -#define CTL_DSC_ARC4_KEYLEN_MASK (CTL_DSC_ARC4_KEYLEN_BITS << CTL_DSC_ARC4_KEYLEN_LSB) - -/* #define CTL_DSC_CPHR (cipher) */ -#define CTL_DSC_CPHR_BYPASS 0 /* undefined */ -#define CTL_DSC_CPHR_DES 1 -#define CTL_DSC_CPHR_3DES 2 -#define CTL_DSC_CPHR_AES128 3 -#define CTL_DSC_CPHR_AES192 4 -#define CTL_DSC_CPHR_AES256 5 -#define CTL_DSC_CPHR_ARC4 6 -#define CTL_DSC_CPHR_KASUMI_F8 7 -#define CTL_DSC_CPHR_LSB 32 -#define CTL_DSC_CPHR_BITS THREE_BITS -#define CTL_DSC_CPHR_MASK (CTL_DSC_CPHR_BITS << CTL_DSC_CPHR_LSB) - -/* #define CTL_DSC_MODE */ -#define CTL_DSC_MODE_ECB 0 -#define CTL_DSC_MODE_CBC 1 -#define CTL_DSC_MODE_CFB 2 -#define CTL_DSC_MODE_OFB 3 -#define CTL_DSC_MODE_CTR 4 -#define CTL_DSC_MODE_F8 5 -#define CTL_DSC_MODE_LSB 29 -#define CTL_DSC_MODE_BITS THREE_BITS -#define CTL_DSC_MODE_MASK (CTL_DSC_MODE_BITS << CTL_DSC_MODE_LSB) - -/* #define CTL_DSC_ICPHR */ -#define CTL_DSC_ICPHR_OKY 0 /* Old Keys */ -#define CTL_DSC_ICPHR_NKY 1 /* New Keys */ -#define CTL_DSC_ICPHR_LSB 28 -#define CTL_DSC_ICPHR_BITS ONE_BIT -#define CTL_DSC_ICPHR_MASK (CTL_DSC_ICPHR_BITS << CTL_DSC_ICPHR_LSB) - -/* #define CTL_DSC_HASHHI */ -#define CTL_DSC_HASHHI_LSB 24 -#define CTL_DSC_HASHHI_BITS ONE_BIT -#define CTL_DSC_HASHHI_MASK (CTL_DSC_HASHHI_BITS << CTL_DSC_HASHHI_LSB) - -/* #define CTL_DSC_HMAC */ -#define CTL_DSC_HMAC_OFF 0 -#define CTL_DSC_HMAC_ON 1 -#define CTL_DSC_HMAC_LSB 23 -#define CTL_DSC_HMAC_BITS ONE_BIT -#define CTL_DSC_HMAC_MASK (CTL_DSC_HMAC_BITS << CTL_DSC_HMAC_LSB) - -/* #define CTL_DSC_HASH */ -#define CTL_DSC_HASH_NOP 0 -#define CTL_DSC_HASH_MD5 1 -#define CTL_DSC_HASH_SHA1 2 -#define CTL_DSC_HASH_SHA256 3 -#define CTL_DSC_HASH_SHA384 4 -#define CTL_DSC_HASH_SHA512 5 -#define CTL_DSC_HASH_GCM 6 -#define CTL_DSC_HASH_KASUMI_F9 7 -#define CTL_DSC_HASH_LSB 21 -#define CTL_DSC_HASH_BITS TWO_BITS -#define CTL_DSC_HASH_MASK (CTL_DSC_HASH_BITS << CTL_DSC_HASH_LSB) - -/* #define CTL_DSC_IHASH */ -#define CTL_DSC_IHASH_OLD 0 -#define CTL_DSC_IHASH_NEW 1 -#define CTL_DSC_IHASH_LSB 20 -#define CTL_DSC_IHASH_BITS ONE_BIT -#define CTL_DSC_IHASH_MASK (CTL_DSC_IHASH_BITS << CTL_DSC_IHASH_LSB) - -/* #define CTL_DSC_CKSUM */ -#define CTL_DSC_CKSUM_NOP 0 -#define CTL_DSC_CKSUM_IP 1 -#define CTL_DSC_CKSUM_LSB 16 -#define CTL_DSC_CKSUM_BITS ONE_BIT -#define CTL_DSC_CKSUM_MASK (CTL_DSC_CKSUM_BITS << CTL_DSC_CKSUM_LSB) - - -/* - * Component strcts and unions defining CipherHashInfo_u - */ - -/* AES256, (ECB, CBC, OFB, CTR, CFB), HMAC (MD5, SHA-1, SHA-256) - 96 bytes */ -typedef struct AES256HMAC_s { - uint64_t cipherKey0; - uint64_t cipherKey1; - uint64_t cipherKey2; - uint64_t cipherKey3; - uint64_t hmacKey0; - uint64_t hmacKey1; - uint64_t hmacKey2; - uint64_t hmacKey3; - uint64_t hmacKey4; - uint64_t hmacKey5; - uint64_t hmacKey6; - uint64_t hmacKey7; -} AES256HMAC_t, *AES256HMAC_pt; - -/* AES256, (ECB, CBC, OFB, CTR, CFB), HMAC (SHA-384, SHA-512) - 160 bytes */ -typedef struct AES256HMAC2_s { - uint64_t cipherKey0; - uint64_t cipherKey1; - uint64_t cipherKey2; - uint64_t cipherKey3; - uint64_t hmacKey0; - uint64_t hmacKey1; - uint64_t hmacKey2; - uint64_t hmacKey3; - uint64_t hmacKey4; - uint64_t hmacKey5; - uint64_t hmacKey6; - uint64_t hmacKey7; - uint64_t hmacKey8; - uint64_t hmacKey9; - uint64_t hmacKey10; - uint64_t hmacKey11; - uint64_t hmacKey12; - uint64_t hmacKey13; - uint64_t hmacKey14; - uint64_t hmacKey15; -} AES256HMAC2_t, *AES256HMAC2_pt; - -/* AES256, (ECB, CBC, OFB, CTR, CFB), GCM - 56 bytes */ -typedef struct AES256GCM_s { - uint64_t cipherKey0; - uint64_t cipherKey1; - uint64_t cipherKey2; - uint64_t cipherKey3; - uint64_t GCMH0; - uint64_t GCMH1; - uint64_t GCMSCI; -} AES256GCM_t, *AES256GCM_pt; - -/* AES256, (ECB, CBC, OFB, CTR, CFB), F9 - 56 bytes */ -typedef struct AES256F9_s { - uint64_t cipherKey0; - uint64_t cipherKey1; - uint64_t cipherKey2; - uint64_t cipherKey3; - uint64_t authKey0; - uint64_t authKey1; -} AES256F9_t, *AES256F9_pt; - -/* AES256, (ECB, CBC, OFB, CTR, CFB), Non-HMAC (MD5, SHA-1, SHA-256) - 32 bytes */ -typedef struct AES256_s { - uint64_t cipherKey0; - uint64_t cipherKey1; - uint64_t cipherKey2; - uint64_t cipherKey3; -} AES256_t, *AES256_pt; - - -/* All AES192 possibilities */ - -/* AES192, (ECB, CBC, OFB, CTR, CFB), HMAC (MD5, SHA-1, SHA-192) - 88 bytes */ -typedef struct AES192HMAC_s { - uint64_t cipherKey0; - uint64_t cipherKey1; - uint64_t cipherKey2; - uint64_t hmacKey0; - uint64_t hmacKey1; - uint64_t hmacKey2; - uint64_t hmacKey3; - uint64_t hmacKey4; - uint64_t hmacKey5; - uint64_t hmacKey6; - uint64_t hmacKey7; -} AES192HMAC_t, *AES192HMAC_pt; - -/* AES192, (ECB, CBC, OFB, CTR, CFB), HMAC (SHA-384, SHA-512) - 152 bytes */ -typedef struct AES192HMAC2_s { - uint64_t cipherKey0; - uint64_t cipherKey1; - uint64_t cipherKey2; - uint64_t hmacKey0; - uint64_t hmacKey1; - uint64_t hmacKey2; - uint64_t hmacKey3; - uint64_t hmacKey4; - uint64_t hmacKey5; - uint64_t hmacKey6; - uint64_t hmacKey7; - uint64_t hmacKey8; - uint64_t hmacKey9; - uint64_t hmacKey10; - uint64_t hmacKey11; - uint64_t hmacKey12; - uint64_t hmacKey13; - uint64_t hmacKey14; - uint64_t hmacKey15; -} AES192HMAC2_t, *AES192HMAC2_pt; - -/* AES192, (ECB, CBC, OFB, CTR, CFB), GCM - 48 bytes */ -typedef struct AES192GCM_s { - uint64_t cipherKey0; - uint64_t cipherKey1; - uint64_t cipherKey2; - uint64_t GCMH0; - uint64_t GCMH1; - uint64_t GCMSCI; -} AES192GCM_t, *AES192GCM_pt; - -/* AES192, (ECB, CBC, OFB, CTR, CFB), F9 - 48 bytes */ -typedef struct AES192F9_s { - uint64_t cipherKey0; - uint64_t cipherKey1; - uint64_t cipherKey2; - uint64_t authKey0; - uint64_t authKey1; -} AES192F9_t, *AES192F9_pt; - -/* AES192, (ECB, CBC, OFB, CTR, CFB), Non-HMAC (MD5, SHA-1, SHA-192) - 24 bytes */ -typedef struct AES192_s { - uint64_t cipherKey0; - uint64_t cipherKey1; - uint64_t cipherKey2; -} AES192_t, *AES192_pt; - - -/* All AES128 possibilities */ - -/* AES128, (ECB, CBC, OFB, CTR, CFB), HMAC (MD5, SHA-1, SHA-128) - 80 bytes */ -typedef struct AES128HMAC_s { - uint64_t cipherKey0; - uint64_t cipherKey1; - uint64_t hmacKey0; - uint64_t hmacKey1; - uint64_t hmacKey2; - uint64_t hmacKey3; - uint64_t hmacKey4; - uint64_t hmacKey5; - uint64_t hmacKey6; - uint64_t hmacKey7; -} AES128HMAC_t, *AES128HMAC_pt; - -/* AES128, (ECB, CBC, OFB, CTR, CFB), HMAC (SHA-384, SHA-612) - 144 bytes */ -typedef struct AES128HMAC2_s { - uint64_t cipherKey0; - uint64_t cipherKey1; - uint64_t hmacKey0; - uint64_t hmacKey1; - uint64_t hmacKey2; - uint64_t hmacKey3; - uint64_t hmacKey4; - uint64_t hmacKey5; - uint64_t hmacKey6; - uint64_t hmacKey7; - uint64_t hmacKey8; - uint64_t hmacKey9; - uint64_t hmacKey10; - uint64_t hmacKey11; - uint64_t hmacKey12; - uint64_t hmacKey13; - uint64_t hmacKey14; - uint64_t hmacKey15; -} AES128HMAC2_t, *AES128HMAC2_pt; - -/* AES128, (ECB, CBC, OFB, CTR, CFB), GCM - 40 bytes */ -typedef struct AES128GCM_s { - uint64_t cipherKey0; - uint64_t cipherKey1; - uint64_t GCMH0; - uint64_t GCMH1; - uint64_t GCMSCI; -} AES128GCM_t, *AES128GCM_pt; - -/* AES128, (ECB, CBC, OFB, CTR, CFB), F9 - 48 bytes */ -typedef struct AES128F9_s { - uint64_t cipherKey0; - uint64_t cipherKey1; - uint64_t authKey0; - uint64_t authKey1; -} AES128F9_t, *AES128F9_pt; - -/* AES128, (ECB, CBC, OFB, CTR, CFB), Non-HMAC (MD5, SHA-1, SHA-128) - 16 bytes */ -typedef struct AES128_s { - uint64_t cipherKey0; - uint64_t cipherKey1; -} AES128_t, *AES128_pt; - -/* AES128, (OFB F8), Non-HMAC (MD5, SHA-1, SHA-256) - 32 bytes */ -typedef struct AES128F8_s { - uint64_t cipherKey0; - uint64_t cipherKey1; - uint64_t cipherKeyMask0; - uint64_t cipherKeyMask1; -} AES128F8_t, *AES128F8_pt; - -/* AES128, (OFB F8), HMAC (MD5, SHA-1, SHA-256) - 96 bytes */ -typedef struct AES128F8HMAC_s { - uint64_t cipherKey0; - uint64_t cipherKey1; - uint64_t cipherKeyMask0; - uint64_t cipherKeyMask1; - uint64_t hmacKey0; - uint64_t hmacKey1; - uint64_t hmacKey2; - uint64_t hmacKey3; - uint64_t hmacKey4; - uint64_t hmacKey5; - uint64_t hmacKey6; - uint64_t hmacKey7; -} AES128F8HMAC_t, *AES128F8HMAC_pt; - -/* AES128, (OFB F8), HMAC (SHA-384, SHA-512) - 160 bytes */ -typedef struct AES128F8HMAC2_s { - uint64_t cipherKey0; - uint64_t cipherKey1; - uint64_t cipherKeyMask0; - uint64_t cipherKeyMask1; - uint64_t hmacKey0; - uint64_t hmacKey1; - uint64_t hmacKey2; - uint64_t hmacKey3; - uint64_t hmacKey4; - uint64_t hmacKey5; - uint64_t hmacKey6; - uint64_t hmacKey7; - uint64_t hmacKey8; - uint64_t hmacKey9; - uint64_t hmacKey10; - uint64_t hmacKey11; - uint64_t hmacKey12; - uint64_t hmacKey13; - uint64_t hmacKey14; - uint64_t hmacKey15; -} AES128F8HMAC2_t, *AES128F8HMAC2_pt; - -/* AES192, (OFB F8), Non-HMAC (MD5, SHA-1, SHA-256) - 48 bytes */ -typedef struct AES192F8_s { - uint64_t cipherKey0; - uint64_t cipherKey1; - uint64_t cipherKey2; - uint64_t cipherKeyMask0; - uint64_t cipherKeyMask1; - uint64_t cipherKeyMask2; -} AES192F8_t, *AES192F8_pt; - -/* AES192, (OFB F8), HMAC (MD5, SHA-1, SHA-256) - 112 bytes */ -typedef struct AES192F8HMAC_s { - uint64_t cipherKey0; - uint64_t cipherKey1; - uint64_t cipherKey2; - uint64_t cipherKeyMask0; - uint64_t cipherKeyMask1; - uint64_t cipherKeyMask2; - uint64_t hmacKey0; - uint64_t hmacKey1; - uint64_t hmacKey2; - uint64_t hmacKey3; - uint64_t hmacKey4; - uint64_t hmacKey5; - uint64_t hmacKey6; - uint64_t hmacKey7; -} AES192F8HMAC_t, *AES192F8HMAC_pt; - -/* AES192, (OFB F8), HMAC (SHA-384, SHA-512) - 176 bytes */ -typedef struct AES192F8HMAC2_s { - uint64_t cipherKey0; - uint64_t cipherKey1; - uint64_t cipherKey2; - uint64_t cipherKeyMask0; - uint64_t cipherKeyMask1; - uint64_t cipherKeyMask2; - uint64_t hmacKey0; - uint64_t hmacKey1; - uint64_t hmacKey2; - uint64_t hmacKey3; - uint64_t hmacKey4; - uint64_t hmacKey5; - uint64_t hmacKey6; - uint64_t hmacKey7; - uint64_t hmacKey8; - uint64_t hmacKey9; - uint64_t hmacKey10; - uint64_t hmacKey11; - uint64_t hmacKey12; - uint64_t hmacKey13; - uint64_t hmacKey14; - uint64_t hmacKey15; -} AES192F8HMAC2_t, *AES192F8HMAC2_pt; - -/* AES256, (OFB F8), Non-HMAC (MD5, SHA-1, SHA-256) - 64 bytes */ -typedef struct AES256F8_s { - uint64_t cipherKey0; - uint64_t cipherKey1; - uint64_t cipherKey2; - uint64_t cipherKey3; - uint64_t cipherKeyMask0; - uint64_t cipherKeyMask1; - uint64_t cipherKeyMask2; - uint64_t cipherKeyMask3; -} AES256F8_t, *AES256F8_pt; - -/* AES256, (OFB F8), HMAC (MD5, SHA-1, SHA-256) - 128 bytes */ -typedef struct AES256F8HMAC_s { - uint64_t cipherKey0; - uint64_t cipherKey1; - uint64_t cipherKey2; - uint64_t cipherKey3; - uint64_t cipherKeyMask0; - uint64_t cipherKeyMask1; - uint64_t cipherKeyMask2; - uint64_t cipherKeyMask3; - uint64_t hmacKey0; - uint64_t hmacKey1; - uint64_t hmacKey2; - uint64_t hmacKey3; - uint64_t hmacKey4; - uint64_t hmacKey5; - uint64_t hmacKey6; - uint64_t hmacKey7; -} AES256F8HMAC_t, *AES256F8HMAC_pt; - -/* AES256, (OFB F8), HMAC (SHA-384, SHA-512) - 192 bytes */ -typedef struct AES256F8HMAC2_s { - uint64_t cipherKey0; - uint64_t cipherKey1; - uint64_t cipherKey2; - uint64_t cipherKey3; - uint64_t cipherKeyMask0; - uint64_t cipherKeyMask1; - uint64_t cipherKeyMask2; - uint64_t cipherKeyMask3; - uint64_t hmacKey0; - uint64_t hmacKey1; - uint64_t hmacKey2; - uint64_t hmacKey3; - uint64_t hmacKey4; - uint64_t hmacKey5; - uint64_t hmacKey6; - uint64_t hmacKey7; - uint64_t hmacKey8; - uint64_t hmacKey9; - uint64_t hmacKey10; - uint64_t hmacKey11; - uint64_t hmacKey12; - uint64_t hmacKey13; - uint64_t hmacKey14; - uint64_t hmacKey15; -} AES256F8HMAC2_t, *AES256F8HMAC2_pt; - -/* AES256, (F8), GCM - 40 bytes */ -typedef struct AES128F8GCM_s { - uint64_t cipherKey0; - uint64_t cipherKey2; - uint64_t GCMH0; - uint64_t GCMH1; - uint64_t GCMSCI; -} AES128F8GCM_t, *AES128F8GCM_pt; - -/* AES256, (F8), GCM - 48 bytes */ -typedef struct AES192F8GCM_s { - uint64_t cipherKey0; - uint64_t cipherKey1; - uint64_t cipherKey2; - uint64_t GCMH0; - uint64_t GCMH1; - uint64_t GCMSCI; -} AES192F8GCM_t, *AES192F8GCM_pt; - -/* AES256, (F8), GCM - 56 bytes */ -typedef struct AES256F8GCM_s { - uint64_t cipherKey0; - uint64_t cipherKey1; - uint64_t cipherKey2; - uint64_t cipherKey3; - uint64_t GCMH0; - uint64_t GCMH1; - uint64_t GCMSCI; -} AES256F8GCM_t, *AES256F8GCM_pt; - -/* AES256, (F8), F9 - 40 bytes */ -typedef struct AES128F8F9_s { - uint64_t cipherKey0; - uint64_t cipherKey2; - uint64_t authKey0; - uint64_t authKey1; -} AES128F8F9_t, *AES128F8F9_pt; - -/* AES256, (F8), F9 - 48 bytes */ -typedef struct AES192F8F9_s { - uint64_t cipherKey0; - uint64_t cipherKey1; - uint64_t cipherKey2; - uint64_t authKey0; - uint64_t authKey1; -} AES192F8F9_t, *AES192F8F9_pt; - -/* AES256F8, (F8), F9 - 56 bytes */ -typedef struct AES256F8F9_s { - uint64_t cipherKey0; - uint64_t cipherKey1; - uint64_t cipherKey2; - uint64_t cipherKey3; - uint64_t authKey0; - uint64_t authKey1; -} AES256F8F9_t, *AES256F8F9_pt; - -/* All DES possibilities */ - -/* DES, (ECB, CBC), HMAC (MD5, SHA-1, SHA-128) - 72 bytes */ -typedef struct DESHMAC_s { - uint64_t cipherKey0; - uint64_t hmacKey0; - uint64_t hmacKey1; - uint64_t hmacKey2; - uint64_t hmacKey3; - uint64_t hmacKey4; - uint64_t hmacKey5; - uint64_t hmacKey6; - uint64_t hmacKey7; -} DESHMAC_t, *DESHMAC_pt; - -/* DES, (ECB, CBC), HMAC (SHA-384, SHA-512) - 136 bytes */ -typedef struct DESHMAC2_s { - uint64_t cipherKey0; - uint64_t hmacKey0; - uint64_t hmacKey1; - uint64_t hmacKey2; - uint64_t hmacKey3; - uint64_t hmacKey4; - uint64_t hmacKey5; - uint64_t hmacKey6; - uint64_t hmacKey7; - uint64_t hmacKey8; - uint64_t hmacKey9; - uint64_t hmacKey10; - uint64_t hmacKey11; - uint64_t hmacKey12; - uint64_t hmacKey13; - uint64_t hmacKey14; - uint64_t hmacKey15; -} DESHMAC2_t, *DESHMAC2_pt; - -/* DES, (ECB, CBC), GCM - 32 bytes */ -typedef struct DESGCM_s { - uint64_t cipherKey0; - uint64_t GCMH0; - uint64_t GCMH1; - uint64_t GCMSCI; -} DESGCM_t, *DESGCM_pt; - -/* DES, (ECB, CBC), F9 - 32 bytes */ -typedef struct DESF9_s { - uint64_t cipherKey0; - uint64_t authKey0; - uint64_t authKey1; -} DESF9_t, *DESF9_pt; - -/* DES, (ECB, CBC), Non-HMAC (MD5, SHA-1, SHA-128) - 9 bytes */ -typedef struct DES_s { - uint64_t cipherKey0; -} DES_t, *DES_pt; - - -/* All 3DES possibilities */ - -/* 3DES, (ECB, CBC), HMAC (MD5, SHA-1, SHA-128) - 88 bytes */ -typedef struct DES3HMAC_s { - uint64_t cipherKey0; - uint64_t cipherKey1; - uint64_t cipherKey2; - uint64_t hmacKey0; - uint64_t hmacKey1; - uint64_t hmacKey2; - uint64_t hmacKey3; - uint64_t hmacKey4; - uint64_t hmacKey5; - uint64_t hmacKey6; - uint64_t hmacKey7; -} DES3HMAC_t, *DES3HMAC_pt; - -/* 3DES, (ECB, CBC), HMAC (SHA-384, SHA-512) - 152 bytes */ -typedef struct DES3HMAC2_s { - uint64_t cipherKey0; - uint64_t cipherKey1; - uint64_t cipherKey2; - uint64_t hmacKey0; - uint64_t hmacKey1; - uint64_t hmacKey2; - uint64_t hmacKey3; - uint64_t hmacKey4; - uint64_t hmacKey5; - uint64_t hmacKey6; - uint64_t hmacKey7; - uint64_t hmacKey8; - uint64_t hmacKey9; - uint64_t hmacKey10; - uint64_t hmacKey11; - uint64_t hmacKey12; - uint64_t hmacKey13; - uint64_t hmacKey14; - uint64_t hmacKey15; -} DES3HMAC2_t, *DES3HMAC2_pt; - -/* 3DES, (ECB, CBC), GCM - 48 bytes */ -typedef struct DES3GCM_s { - uint64_t cipherKey0; - uint64_t cipherKey1; - uint64_t cipherKey2; - uint64_t GCMH0; - uint64_t GCMH1; - uint64_t GCMSCI; -} DES3GCM_t, *DES3GCM_pt; - -/* 3DES, (ECB, CBC), GCM - 48 bytes */ -typedef struct DES3F9_s { - uint64_t cipherKey0; - uint64_t cipherKey1; - uint64_t cipherKey2; - uint64_t authKey0; - uint64_t authKey1; -} DES3F9_t, *DES3F9_pt; - -/* 3DES, (ECB, CBC), Non-HMAC (MD5, SHA-1, SHA-128) - 24 bytes */ -typedef struct DES3_s { - uint64_t cipherKey0; - uint64_t cipherKey1; - uint64_t cipherKey2; -} DES3_t, *DES3_pt; - - -/* HMAC only - no cipher */ - -/* HMAC (MD5, SHA-1, SHA-128) - 64 bytes */ -typedef struct HMAC_s { - uint64_t hmacKey0; - uint64_t hmacKey1; - uint64_t hmacKey2; - uint64_t hmacKey3; - uint64_t hmacKey4; - uint64_t hmacKey5; - uint64_t hmacKey6; - uint64_t hmacKey7; -} HMAC_t, *HMAC_pt; - -/* HMAC (SHA-384, SHA-512) - 128 bytes */ -typedef struct HMAC2_s { - uint64_t hmacKey0; - uint64_t hmacKey1; - uint64_t hmacKey2; - uint64_t hmacKey3; - uint64_t hmacKey4; - uint64_t hmacKey5; - uint64_t hmacKey6; - uint64_t hmacKey7; - uint64_t hmacKey8; - uint64_t hmacKey9; - uint64_t hmacKey10; - uint64_t hmacKey11; - uint64_t hmacKey12; - uint64_t hmacKey13; - uint64_t hmacKey14; - uint64_t hmacKey15; -} HMAC2_t, *HMAC2_pt; - -/* GCM - 24 bytes */ -typedef struct GCM_s { - uint64_t GCMH0; - uint64_t GCMH1; - uint64_t GCMSCI; -} GCM_t, *GCM_pt; - -/* F9 - 24 bytes */ -typedef struct F9_s { - uint64_t authKey0; - uint64_t authKey1; -} F9_t, *F9_pt; - -/* All ARC4 possibilities */ -/* ARC4, HMAC (MD5, SHA-1, SHA-256) - 96 bytes */ -typedef struct ARC4HMAC_s { - uint64_t cipherKey0; - uint64_t cipherKey1; - uint64_t cipherKey2; - uint64_t cipherKey3; - uint64_t hmacKey0; - uint64_t hmacKey1; - uint64_t hmacKey2; - uint64_t hmacKey3; - uint64_t hmacKey4; - uint64_t hmacKey5; - uint64_t hmacKey6; - uint64_t hmacKey7; -} ARC4HMAC_t, *ARC4HMAC_pt; - -/* ARC4, HMAC (SHA-384, SHA-512) - 160 bytes */ -typedef struct ARC4HMAC2_s { - uint64_t cipherKey0; - uint64_t cipherKey1; - uint64_t cipherKey2; - uint64_t cipherKey3; - uint64_t hmacKey0; - uint64_t hmacKey1; - uint64_t hmacKey2; - uint64_t hmacKey3; - uint64_t hmacKey4; - uint64_t hmacKey5; - uint64_t hmacKey6; - uint64_t hmacKey7; - uint64_t hmacKey8; - uint64_t hmacKey9; - uint64_t hmacKey10; - uint64_t hmacKey11; - uint64_t hmacKey12; - uint64_t hmacKey13; - uint64_t hmacKey14; - uint64_t hmacKey15; -} ARC4HMAC2_t, *ARC4HMAC2_pt; - -/* ARC4, GCM - 56 bytes */ -typedef struct ARC4GCM_s { - uint64_t cipherKey0; - uint64_t cipherKey1; - uint64_t cipherKey2; - uint64_t cipherKey3; - uint64_t GCMH0; - uint64_t GCMH1; - uint64_t GCMSCI; -} ARC4GCM_t, *ARC4GCM_pt; - -/* ARC4, F9 - 56 bytes */ -typedef struct ARC4F9_s { - uint64_t cipherKey0; - uint64_t cipherKey1; - uint64_t cipherKey2; - uint64_t cipherKey3; - uint64_t authKey0; - uint64_t authKey1; -} ARC4F9_t, *ARC4F9_pt; - -/* ARC4, HMAC (MD5, SHA-1, SHA-256) - 408 bytes (not including 8 bytes from instruction) */ -typedef struct ARC4StateHMAC_s { - uint64_t cipherKey0; - uint64_t cipherKey1; - uint64_t cipherKey2; - uint64_t cipherKey3; - uint64_t hmacKey0; - uint64_t hmacKey1; - uint64_t hmacKey2; - uint64_t hmacKey3; - uint64_t hmacKey4; - uint64_t hmacKey5; - uint64_t hmacKey6; - uint64_t hmacKey7; - uint64_t PAD0; - uint64_t PAD1; - uint64_t PAD2; - uint64_t Arc4SboxData0; - uint64_t Arc4SboxData1; - uint64_t Arc4SboxData2; - uint64_t Arc4SboxData3; - uint64_t Arc4SboxData4; - uint64_t Arc4SboxData5; - uint64_t Arc4SboxData6; - uint64_t Arc4SboxData7; - uint64_t Arc4SboxData8; - uint64_t Arc4SboxData9; - uint64_t Arc4SboxData10; - uint64_t Arc4SboxData11; - uint64_t Arc4SboxData12; - uint64_t Arc4SboxData13; - uint64_t Arc4SboxData14; - uint64_t Arc4SboxData15; - uint64_t Arc4SboxData16; - uint64_t Arc4SboxData17; - uint64_t Arc4SboxData18; - uint64_t Arc4SboxData19; - uint64_t Arc4SboxData20; - uint64_t Arc4SboxData21; - uint64_t Arc4SboxData22; - uint64_t Arc4SboxData23; - uint64_t Arc4SboxData24; - uint64_t Arc4SboxData25; - uint64_t Arc4SboxData26; - uint64_t Arc4SboxData27; - uint64_t Arc4SboxData28; - uint64_t Arc4SboxData29; - uint64_t Arc4SboxData30; - uint64_t Arc4SboxData31; - uint64_t Arc4IJData; - uint64_t PAD3; - uint64_t PAD4; - uint64_t PAD5; -} ARC4StateHMAC_t, *ARC4StateHMAC_pt; - -/* ARC4, HMAC (SHA-384, SHA-512) - 480 bytes (not including 8 bytes from instruction) */ -typedef struct ARC4StateHMAC2_s { - uint64_t cipherKey0; - uint64_t cipherKey1; - uint64_t cipherKey2; - uint64_t cipherKey3; - uint64_t hmacKey0; - uint64_t hmacKey1; - uint64_t hmacKey2; - uint64_t hmacKey3; - uint64_t hmacKey4; - uint64_t hmacKey5; - uint64_t hmacKey6; - uint64_t hmacKey7; - uint64_t hmacKey8; - uint64_t hmacKey9; - uint64_t hmacKey10; - uint64_t hmacKey11; - uint64_t hmacKey12; - uint64_t hmacKey13; - uint64_t hmacKey14; - uint64_t hmacKey15; - uint64_t PAD0; - uint64_t PAD1; - uint64_t PAD2; - uint64_t Arc4SboxData0; - uint64_t Arc4SboxData1; - uint64_t Arc4SboxData2; - uint64_t Arc4SboxData3; - uint64_t Arc4SboxData4; - uint64_t Arc4SboxData5; - uint64_t Arc4SboxData6; - uint64_t Arc4SboxData7; - uint64_t Arc4SboxData8; - uint64_t Arc4SboxData9; - uint64_t Arc4SboxData10; - uint64_t Arc4SboxData11; - uint64_t Arc4SboxData12; - uint64_t Arc4SboxData13; - uint64_t Arc4SboxData14; - uint64_t Arc4SboxData15; - uint64_t Arc4SboxData16; - uint64_t Arc4SboxData17; - uint64_t Arc4SboxData18; - uint64_t Arc4SboxData19; - uint64_t Arc4SboxData20; - uint64_t Arc4SboxData21; - uint64_t Arc4SboxData22; - uint64_t Arc4SboxData23; - uint64_t Arc4SboxData24; - uint64_t Arc4SboxData25; - uint64_t Arc4SboxData26; - uint64_t Arc4SboxData27; - uint64_t Arc4SboxData28; - uint64_t Arc4SboxData29; - uint64_t Arc4SboxData30; - uint64_t Arc4SboxData31; - uint64_t Arc4IJData; - uint64_t PAD3; - uint64_t PAD4; - uint64_t PAD5; -} ARC4StateHMAC2_t, *ARC4StateHMAC2_pt; - -/* ARC4, GCM - 408 bytes (not including 8 bytes from instruction) */ -typedef struct ARC4StateGCM_s { - uint64_t cipherKey0; - uint64_t cipherKey1; - uint64_t cipherKey2; - uint64_t cipherKey3; - uint64_t GCMH0; - uint64_t GCMH1; - uint64_t GCMSCI; - uint64_t PAD0; - uint64_t PAD1; - uint64_t PAD2; - uint64_t PAD3; - uint64_t PAD4; - uint64_t PAD5; - uint64_t PAD6; - uint64_t PAD7; - uint64_t Arc4SboxData0; - uint64_t Arc4SboxData1; - uint64_t Arc4SboxData2; - uint64_t Arc4SboxData3; - uint64_t Arc4SboxData4; - uint64_t Arc4SboxData5; - uint64_t Arc4SboxData6; - uint64_t Arc4SboxData7; - uint64_t Arc4SboxData8; - uint64_t Arc4SboxData9; - uint64_t Arc4SboxData10; - uint64_t Arc4SboxData11; - uint64_t Arc4SboxData12; - uint64_t Arc4SboxData13; - uint64_t Arc4SboxData14; - uint64_t Arc4SboxData15; - uint64_t Arc4SboxData16; - uint64_t Arc4SboxData17; - uint64_t Arc4SboxData18; - uint64_t Arc4SboxData19; - uint64_t Arc4SboxData20; - uint64_t Arc4SboxData21; - uint64_t Arc4SboxData22; - uint64_t Arc4SboxData23; - uint64_t Arc4SboxData24; - uint64_t Arc4SboxData25; - uint64_t Arc4SboxData26; - uint64_t Arc4SboxData27; - uint64_t Arc4SboxData28; - uint64_t Arc4SboxData29; - uint64_t Arc4SboxData30; - uint64_t Arc4SboxData31; - uint64_t Arc4IJData; - uint64_t PAD8; - uint64_t PAD9; - uint64_t PAD10; -} ARC4StateGCM_t, *ARC4StateGCM_pt; - -/* ARC4, F9 - 408 bytes (not including 8 bytes from instruction) */ -typedef struct ARC4StateF9_s { - uint64_t cipherKey0; - uint64_t cipherKey1; - uint64_t cipherKey2; - uint64_t cipherKey3; - uint64_t authKey0; - uint64_t authKey1; - uint64_t PAD0; - uint64_t PAD1; - uint64_t PAD2; - uint64_t PAD3; - uint64_t PAD4; - uint64_t PAD5; - uint64_t PAD6; - uint64_t PAD7; - uint64_t PAD8; - uint64_t Arc4SboxData0; - uint64_t Arc4SboxData1; - uint64_t Arc4SboxData2; - uint64_t Arc4SboxData3; - uint64_t Arc4SboxData4; - uint64_t Arc4SboxData5; - uint64_t Arc4SboxData6; - uint64_t Arc4SboxData7; - uint64_t Arc4SboxData8; - uint64_t Arc4SboxData9; - uint64_t Arc4SboxData10; - uint64_t Arc4SboxData11; - uint64_t Arc4SboxData12; - uint64_t Arc4SboxData13; - uint64_t Arc4SboxData14; - uint64_t Arc4SboxData15; - uint64_t Arc4SboxData16; - uint64_t Arc4SboxData17; - uint64_t Arc4SboxData18; - uint64_t Arc4SboxData19; - uint64_t Arc4SboxData20; - uint64_t Arc4SboxData21; - uint64_t Arc4SboxData22; - uint64_t Arc4SboxData23; - uint64_t Arc4SboxData24; - uint64_t Arc4SboxData25; - uint64_t Arc4SboxData26; - uint64_t Arc4SboxData27; - uint64_t Arc4SboxData28; - uint64_t Arc4SboxData29; - uint64_t Arc4SboxData30; - uint64_t Arc4SboxData31; - uint64_t Arc4IJData; - uint64_t PAD9; - uint64_t PAD10; - uint64_t PAD11; -} ARC4StateF9_t, *ARC4StateF9_pt; - -/* ARC4, Non-HMAC (MD5, SHA-1, SHA-256) - 32 bytes */ -typedef struct ARC4_s { - uint64_t cipherKey0; - uint64_t cipherKey1; - uint64_t cipherKey2; - uint64_t cipherKey3; -} ARC4_t, *ARC4_pt; - -/* ARC4, Non-HMAC (MD5, SHA-1, SHA-256) - 344 bytes (not including 8 bytes from instruction) */ -typedef struct ARC4State_s { - uint64_t cipherKey0; - uint64_t cipherKey1; - uint64_t cipherKey2; - uint64_t cipherKey3; - uint64_t PAD0; - uint64_t PAD1; - uint64_t PAD2; - uint64_t Arc4SboxData0; - uint64_t Arc4SboxData1; - uint64_t Arc4SboxData2; - uint64_t Arc4SboxData3; - uint64_t Arc4SboxData4; - uint64_t Arc4SboxData5; - uint64_t Arc4SboxData6; - uint64_t Arc4SboxData7; - uint64_t Arc4SboxData8; - uint64_t Arc4SboxData9; - uint64_t Arc4SboxData10; - uint64_t Arc4SboxData11; - uint64_t Arc4SboxData12; - uint64_t Arc4SboxData13; - uint64_t Arc4SboxData14; - uint64_t Arc4SboxData15; - uint64_t Arc4SboxData16; - uint64_t Arc4SboxData17; - uint64_t Arc4SboxData18; - uint64_t Arc4SboxData19; - uint64_t Arc4SboxData20; - uint64_t Arc4SboxData21; - uint64_t Arc4SboxData22; - uint64_t Arc4SboxData23; - uint64_t Arc4SboxData24; - uint64_t Arc4SboxData25; - uint64_t Arc4SboxData26; - uint64_t Arc4SboxData27; - uint64_t Arc4SboxData28; - uint64_t Arc4SboxData29; - uint64_t Arc4SboxData30; - uint64_t Arc4SboxData31; - uint64_t Arc4IJData; - uint64_t PAD3; - uint64_t PAD4; - uint64_t PAD5; -} ARC4State_t, *ARC4State_pt; - -/* Kasumi f8 - 32 bytes */ -typedef struct KASUMIF8_s { - uint64_t cipherKey0; - uint64_t cipherKey1; -} KASUMIF8_t, *KASUMIF8_pt; - -/* Kasumi f8 + HMAC (MD5, SHA-1, SHA-256) - 80 bytes */ -typedef struct KASUMIF8HMAC_s { - uint64_t cipherKey0; - uint64_t cipherKey1; - uint64_t hmacKey0; - uint64_t hmacKey1; - uint64_t hmacKey2; - uint64_t hmacKey3; - uint64_t hmacKey4; - uint64_t hmacKey5; - uint64_t hmacKey6; - uint64_t hmacKey7; -} KASUMIF8HMAC_t, *KASUMIF8HMAC_pt; - -/* Kasumi f8 + HMAC (SHA-384, SHA-512) - 144 bytes */ -typedef struct KASUMIF8HMAC2_s { - uint64_t cipherKey0; - uint64_t cipherKey1; - uint64_t hmacKey0; - uint64_t hmacKey1; - uint64_t hmacKey2; - uint64_t hmacKey3; - uint64_t hmacKey4; - uint64_t hmacKey5; - uint64_t hmacKey6; - uint64_t hmacKey7; - uint64_t hmacKey8; - uint64_t hmacKey9; - uint64_t hmacKey10; - uint64_t hmacKey11; - uint64_t hmacKey12; - uint64_t hmacKey13; - uint64_t hmacKey14; - uint64_t hmacKey15; -} KASUMIF8HMAC2_t, *KASUMIF8HMAC2_pt; - -/* Kasumi f8 + GCM - 144 bytes */ -typedef struct KASUMIF8GCM_s { - uint64_t cipherKey0; - uint64_t cipherKey1; - uint64_t GCMH0; - uint64_t GCMH1; - uint64_t GCMSCI; -} KASUMIF8GCM_t, *KASUMIF8GCM_pt; - -/* Kasumi f8 + f9 - 32 bytes */ -typedef struct KASUMIF8F9_s { - uint64_t cipherKey0; - uint64_t cipherKey1; - uint64_t authKey0; - uint64_t authKey1; -} KASUMIF8F9_t, *KASUMIF8F9_pt; - -typedef union CipherHashInfo_u { - AES256HMAC_t infoAES256HMAC; - AES256_t infoAES256; - AES192HMAC_t infoAES192HMAC; - AES192_t infoAES192; - AES128HMAC_t infoAES128HMAC; - AES128_t infoAES128; - DESHMAC_t infoDESHMAC; - DES_t infoDES; - DES3HMAC_t info3DESHMAC; - DES3_t info3DES; - HMAC_t infoHMAC; - /* ARC4 */ - ARC4HMAC_t infoARC4HMAC; - ARC4StateHMAC_t infoARC4StateHMAC; - ARC4_t infoARC4; - ARC4State_t infoARC4State; - /* AES mode F8 */ - AES256F8HMAC_t infoAES256F8HMAC; - AES256F8_t infoAES256F8; - AES192F8HMAC_t infoAES192F8HMAC; - AES192F8_t infoAES192F8; - AES128F8HMAC_t infoAES128F8HMAC; - AES128F8_t infoAES128F8; - /* KASUMI F8 */ - KASUMIF8HMAC_t infoKASUMIF8HMAC; - KASUMIF8_t infoKASUMIF8; - /* GCM */ - GCM_t infoGCM; - AES256F8GCM_t infoAES256F8GCM; - AES192F8GCM_t infoAES192F8GCM; - AES128F8GCM_t infoAES128F8GCM; - AES256GCM_t infoAES256GCM; - AES192GCM_t infoAES192GCM; - AES128GCM_t infoAES128GCM; - DESGCM_t infoDESGCM; - DES3GCM_t info3DESGCM; - ARC4GCM_t infoARC4GCM; - ARC4StateGCM_t infoARC4StateGCM; - KASUMIF8GCM_t infoKASUMIF8GCM; - /* HMAC2 */ - HMAC2_t infoHMAC2; - AES256F8HMAC2_t infoAES256F8HMAC2; - AES192F8HMAC2_t infoAES192F8HMAC2; - AES128F8HMAC2_t infoAES128F8HMAC2; - AES256HMAC2_t infoAES256HMAC2; - AES192HMAC2_t infoAES192HMAC2; - AES128HMAC2_t infoAES128HMAC2; - DESHMAC2_t infoDESHMAC2; - DES3HMAC2_t info3DESHMAC2; - ARC4HMAC2_t infoARC4HMAC2; - ARC4StateHMAC2_t infoARC4StateHMAC2; - KASUMIF8HMAC2_t infoKASUMIF8HMAC2; - /* F9 */ - F9_t infoF9; - AES256F8F9_t infoAES256F8F9; - AES192F8F9_t infoAES192F8F9; - AES128F8F9_t infoAES128F8F9; - AES256F9_t infoAES256F9; - AES192F9_t infoAES192F9; - AES128F9_t infoAES128F9; - DESF9_t infoDESF9; - DES3F9_t info3DESF9; - ARC4F9_t infoARC4F9; - ARC4StateF9_t infoARC4StateF9; - KASUMIF8F9_t infoKASUMIF8F9; -} CipherHashInfo_t, *CipherHashInfo_pt; - - -/* - * - * ControlDescriptor_s datastructure - * - */ - -typedef struct ControlDescriptor_s { - uint64_t instruction; - CipherHashInfo_t cipherHashInfo; -} ControlDescriptor_t, *ControlDescriptor_pt; - - - - -/* ********************************************************************** - * PacketDescriptor_t - * ********************************************************************** - */ - -/* /--------------------------------------------\ - * | | - * | New PacketDescriptor_s datastructure | - * | | - * \--------------------------------------------/ - * - * - * - * PacketDescriptor_t.srcLengthIVOffUseIVNext - * ------------------------------------------ - * - * 63 62 61 59 58 57 56 54 53 43 - * ------------------------------------------------------------------------------------------------ - * || Load HMAC key || Pad Hash || Hash Byte Count || Next || Use IV || IV Offset || Packet length || ... CONT ... - * ------------------------------------------------------------------------------------------------ - * 1 1 3 1 1 3 11 - * - * - * 42 41 40 39 5 4 3 2 - * 0 - * ---------------------------------------------------------------------------------------------------- - * || NLHMAC || Break || Wait || Segment src address || SRTCP || Reserved || Global src data offset || - * ---------------------------------------------------------------------------------------------------- - * 1 1 1 35 1 1 3 - * - * - * - * Load HMAC key = 1'b0 Preserve old HMAC key stored in Auth engine (moot if HASH.HMAC == 0) - * 1'b1 Load HMAC key from ID registers at beginning of op - * If GCM is selected as authenticator, setting this bit - * will cause the H value from ID to be loaded to the engine - * If Kasumi F9 is selected as authenticator, setting this bit - * will cause the IK value from ID to be loaded to the engine. - * Pad Hash = 1'b0 HASH will assume the data was padded to be a multiple - * of 512 bits in length and that the last 64 bit word - * expresses the total datalength in bits seen by HASH engine - * 1'b1 The data was not padded to be a multiple of 512 bits in length; - * The Hash engine will do its own padding to generate the correct digest. - * Ignored by GCM (always does its own padding) - * Hash Byte Count Number of BYTES on last 64-bit data word to use in digest calculation RELEVANT ONLY IF Pad Hash IS SET - * 3'b000 Use all 8 - * 3'b001 Use first (MS) byte only (0-out rest), i.e., 0xddXXXXXXXXXXXXXX - * 3'b010 Use first 2 bytes only (0-out rest), i.e., 0xddddXXXXXXXXXXXX ... etc - * Next = 1'b0 Finish (return msg descriptor) at end of operation - * 1'b1 Grab the next PacketDescriptor (i.e. next cache-line) when the current is complete. - * This allows for fragmentation/defragmentation and processing of large (>16kB) packets. - * The sequence of adjacent PacketDescriptor acts as a contiguous linked list of - * pointers to the actual packets with Next==0 on the last PacketDescriptor to end processing. - * Use IV = 1'b0 On first frag: Use old IV - * On subsequent frags: Do not write out to DST the (dword) offset data - * 1'b1 On first frag: Use data @ Segment_address + IV_Offset as IV - * On subsequent frags: Do write out to DST the (dword) offset data - * IV Offset = On first frag: Offset IN NB OF 8 BYTE WORDS (dwords) from beginning of packet - * (i.e. (Potentially byte-shifted) Segment address) to cipher IV - * On subsequent frags: Offset to beginning of data to process; data to offset won't - * be given to engines and will be written out to dst in the clear. - * ON SUBSEQUENT FRAGS, IV_Offset MAY NOT EXCEED 3; LARGER VALUES WILL CAUSE AN ERROR - * SEE ERROR CONDITIONS BELOW - * Packet length = Nb double words to stream in (Including Segment address->CP/IV/Auth/CkSum offsets) - * This is the total amount of data (x8 in bytes) read (+1 dword if "Global src data offset" != 0) - * This is the total amount of data (x8 in bytes) written (+1 dword if "Global dst data offset" != 0, if Dst dword offset == 0) - * If Packet length == 11'h7ff and (Global src data offset != 0 or Global dst data offset != 0) - * the operation is aborted (no mem writes occur) - * and the "Insufficient Data To Cipher" error flag is raised - * NLHMAC = No last to hmac. Setting this to 1 will prevent the transmission of the last DWORD - * to the authenticator, i.e., the DWORD before last will be designated as last for the purposes of authentication. - * Break = Break a wait (see below) state - causes the operation to be flushed and free descriptor to be returned. - * Activated if DFetch blocked by Wait and Wait still active. - * AS OF 02/10/2005 THIS FEATURE IS EXPERIMENTAL - * Wait = Setting that bit causes the operation to block in DFetch stage. - * DFetch will keep polling the memory location until the bit is reset at which time - * the pipe resumes normal operation. This feature is convenient for software dealing with fragmented packets. - * AS OF 02/10/2005 THIS FEATURE IS EXPERIMENTAL - * Segment src address = 35 MSB of pointer to src data (i.e., cache-line aligned) - * SRTCP = Bypass the cipher for the last 4 bytes of data, i.e. the last 4 bytes will be sent to memory - * and the authenticator in the clear. Applicable to last packet descriptor andlast frag only. - * This accommodates a requirement of SRTCP. - * Global src data offset = Nb BYTES to right-shift data by before presenting it to engines - * (0-7); allows realignment of byte-aligned, non-double-word aligned data - * - * PacketDescriptor_t.dstDataSettings - * ---------------------------------- - * - * - * 63 62 60 59 58 56 55 54 53 52 41 40 - * ------------------------------------------------------------------------------------------------------------ - * || CipherPrefix | Arc4ByteCount | E/D | Cipher_Offset || Hash_Offset | Hash_Src || CkSum_Offset | CkSum_Src || ... CONT ... - * ------------------------------------------------------------------------------------------------------------ - * 1 3 1 3 2 1 12 1 - * <-----------------------CIPHER-----------------------><---------HASH-----------><-------CHECKSUM-----------> - * - * - * CipherPrefix = 128'b0 will be sent to the selected cipher - * KEEP VALUE ON ALL FRAGS after the IV is loaded, before the actual data goes in. - * The result of that encryption (aka E(K, 0))will be stored - * locally and XOR-ed with the auth digest to create the final - * digest at the end of the auth OP: - * This is covered by the GCM spec - * AesPrefix = 1'b1 -> Force E=Cipher(K,0) before start of data encr. - * -> Digest ^= E - * AesPrefix = 1'b0 -> Regular digest - * This flag is ignored if no cipher is chosen (Bypass condition) - * X0 Arc4ByteCount = Number of BYTES on last 64-bit data word to encrypt - * 3'b000 Encrypt all 8 - * 3'b001 Encrypt first (MS) byte only i.e., 0xddXXXXXXXXXXXXXX - * 3'b010 Encrypt first 2 bytes only i.e., 0xddddXXXXXXXXXXXX ... etc - * In reality, all are encrypted, however, the SBOX - * is not written past the last byte to encrypt - * E/D = 1'b0 Decrypt - * 1'b1 Encrypt - * Overloaded to also mean IV byte offset for first frag - * Cipher_Offset = Nb of words between the first data segment - * and word on which to start cipher operation - * (64 BIT WORDS !!!) - * Hash_Offset = Nb of words between the first data segment - * and word on which to start hashing - * (64 bit words) - * Hash_Src = 1'b0 DMA channel - * 1'b1 Cipher if word count exceeded Cipher_Offset; - * DMA channel otherwise - * CkSum_Offset = Nb of words between the first data segment - * and word on which to start - * checksum calculation (32 BIT WORDS !!!) - * CkSum_Src = 1'b0 DMA channel - * 1'b1 Cipher if word count exceeded Cipher_Offset - * DMA channel otherwise - * Cipher dst address = 35 MSB of pointer to dst location (i.e., cache-line aligned) - * Dst dword offset = Nb of double-words to left-shift data from spec'ed Cipher dst address before writing it to memory - * Global dst data offset = Nb BYTES to left-shift (double-word boundary aligned) data by before writing it to memory - * - * - * PacketDescriptor_t.authDstNonceLow - * ---------------------------------- - * - * 63 40 39 5 4 0 - * ----------------------------------------------------- - * || Nonce_Low || Auth_dst_address || Cipher_Offset_Hi || - * ----------------------------------------------------- - * 24 35 5 - * - * - * - * Nonce_Low = Nonce[23:0] 24 least significant bits of 32-bit long nonce - * Used by AES in counter mode - * Auth_dst_address = 35 MSB of pointer to authentication dst location (i.e., cache-line aligned) - * X0 Cipher_Offset_Hi = On first frag: 5 MSB of 8-bit Cipher_offset; will be concatenated to - * the top of PacketDescriptor_t.dstDataSettings.Cipher_Offset - * On subsequent frags: Ignored - * - * - * PacketDescriptor_t.ckSumDstNonceHiCFBMaskLLWMask - * ------------------------------------------------ - * - * - * 63 61 60 58 57 56 55 48 47 40 39 5 4 0 - * ------------------------------------------------------------------------------------------------------------------- - * || Hash_Byte_Offset || Packet length bytes || LLWMask || CFB_Mask || Nonce_Hi || CkSum_dst_address || IV_Offset_Hi || - * ------------------------------------------------------------------------------------------------------------------- - * 3 3 2 8 8 35 5 - * - * - * Hash_Byte_Offset = On first frag: Additional offset in bytes to be added to Hash_Offset - * to obtain the full offset applied to the data before - * submitting it to authenticator - * On subsequent frags: Same - * Packet length bytes = On one fragment payloads: Ignored (i.e. assumed to be 0, last dword used in its entirety) - * On fragments before last: Number of bytes on last fragment dword - * On last fragment: Ignored (i.e. assumed to be 0, last dword used in its entirety) - * LLWMask, aka, Last_long_word_mask = 2'b00 Give last 128 bit word from AES engine to auth/cksum/wrbbufer as is - applicable in AES CTR only - * 2'b11 Mask (zero-out) 32 least significant bits - * 2'b10 Mask 64 LSBs - * 2'b01 Mask 96 LSBs - * If the GCM authenticator is used, setting LLWMask to 2'b10 or 2'b01 - * will also prevent the transmission of the last DWORD - * to the authenticator, i.e., the DWORD before last will - * be designated as last for the purposes of authentication. - * CFB_Mask = 8 bit mask used by AES in CFB mode - * In CTR mode: - * CFB_Mask[1:0] = 2'b00 -> Counter[127:0] = {Nonce[31:0], IV0[63:0], 4'h00000001} (only 1 IV exp -ected) regular CTR - * 2'b01 -> Counter[127:0] = {Nonce[31:0], IV0[63:0], IV1[31:0]} (2 IV expected -) CCMP - * 2'b10 -> Counter[127:0] = {IV1[63:0], IV0[31:0], Nonce[31:0]} (2 IV expected -) GCM with SCI - * 2'b11 -> Counter[127:0] = {IDecode.SCI[63:0], IV0[31:0], Nonce[31:0]} (1 IV expected -) GCM w/o SCI - * Nonce_Hi = Nonce[31:24] 8 most significant bits of 32-bit long nonce - * Used by AES in counter mode - * CkSum_dst_address = 35 MSB of pointer to cksum dst location (i.e., cache-line aligned) - * X0 IV_Offset_Hi = On first frag: 5 MSB of 8-bit IV offset; will be concatenated to - * the top of PacketDescriptor_t.srcLengthIVOffUseIVNext.IV_Offset - * On subsequent frags: Ignored - */ - -/* #define PKT_DSC_LOADHMACKEY */ -#define PKT_DSC_LOADHMACKEY_OLD 0 -#define PKT_DSC_LOADHMACKEY_LOAD 1 -#define PKT_DSC_LOADHMACKEY_LSB 63 -#define PKT_DSC_LOADHMACKEY_BITS ONE_BIT -#define PKT_DSC_LOADHMACKEY_MASK \ - (PKT_DSC_LOADHMACKEY_BITS << PKT_DSC_LOADHMACKEY_LSB) - -/* #define PKT_DSC_PADHASH */ -#define PKT_DSC_PADHASH_PADDED 0 -#define PKT_DSC_PADHASH_PAD 1 /* requires padding */ -#define PKT_DSC_PADHASH_LSB 62 -#define PKT_DSC_PADHASH_BITS ONE_BIT -#define PKT_DSC_PADHASH_MASK (PKT_DSC_PADHASH_BITS << PKT_DSC_PADHASH_LSB) - -/* #define PKT_DSC_HASHBYTES */ -#define PKT_DSC_HASHBYTES_ALL8 0 -#define PKT_DSC_HASHBYTES_MSB 1 -#define PKT_DSC_HASHBYTES_MSW 2 -#define PKT_DSC_HASHBYTES_LSB 59 -#define PKT_DSC_HASHBYTES_BITS THREE_BITS -#define PKT_DSC_HASHBYTES_MASK \ - (PKT_DSC_HASHBYTES_BITS << PKT_DSC_HASHBYTES_LSB) - -/* #define PKT_DSC_NEXT */ -#define PKT_DSC_NEXT_FINISH 0 -#define PKT_DSC_NEXT_DO 1 -#define PKT_DSC_NEXT_LSB 58 -#define PKT_DSC_NEXT_BITS ONE_BIT -#define PKT_DSC_NEXT_MASK (PKT_DSC_NEXT_BITS << PKT_DSC_NEXT_LSB) - -/* #define PKT_DSC_IV */ -#define PKT_DSC_IV_OLD 0 -#define PKT_DSC_IV_NEW 1 -#define PKT_DSC_IV_LSB 57 -#define PKT_DSC_IV_BITS ONE_BIT -#define PKT_DSC_IV_MASK (PKT_DSC_IV_BITS << PKT_DSC_IV_LSB) - -/* #define PKT_DSC_IVOFF */ -#define PKT_DSC_IVOFF_LSB 54 -#define PKT_DSC_IVOFF_BITS THREE_BITS -#define PKT_DSC_IVOFF_MASK (PKT_DSC_IVOFF_BITS << PKT_DSC_IVOFF_LSB) - -/* #define PKT_DSC_PKTLEN */ -#define PKT_DSC_PKTLEN_LSB 43 -#define PKT_DSC_PKTLEN_BITS ELEVEN_BITS -#define PKT_DSC_PKTLEN_MASK (PKT_DSC_PKTLEN_BITS << PKT_DSC_PKTLEN_LSB) - -/* #define PKT_DSC_NLHMAC */ -#define PKT_DSC_NLHMAC_LSB 42 -#define PKT_DSC_NLHMAC_BITS ONE_BIT -#define PKT_DSC_NLHMAC_MASK (PKT_DSC_NLHMAC_BITS << PKT_DSC_NLHMAC_LSB) - -/* #define PKT_DSC_BREAK */ -#define PKT_DSC_BREAK_OLD 0 -#define PKT_DSC_BREAK_NEW 1 -#define PKT_DSC_BREAK_LSB 41 -#define PKT_DSC_BREAK_BITS ONE_BIT -#define PKT_DSC_BREAK_MASK (PKT_DSC_BREAK_BITS << PKT_DSC_BREAK_LSB) - -/* #define PKT_DSC_WAIT */ -#define PKT_DSC_WAIT_OLD 0 -#define PKT_DSC_WAIT_NEW 1 -#define PKT_DSC_WAIT_LSB 40 -#define PKT_DSC_WAIT_BITS ONE_BIT -#define PKT_DSC_WAIT_MASK (PKT_DSC_WAIT_BITS << PKT_DSC_WAIT_LSB) - -/* #define PKT_DSC_SEGADDR */ -#define PKT_DSC_SEGADDR_LSB 5 -#define PKT_DSC_SEGADDR_BITS FOURTY_BITS -#define PKT_DSC_SEGADDR_MASK \ - (PKT_DSC_SEGADDR_BITS << PKT_DSC_SEGADDR_LSB) - -/* #define PKT_DSC_SRTCP */ -#define PKT_DSC_SRTCP_OFF 0 -#define PKT_DSC_SRTCP_ON 1 -#define PKT_DSC_SRTCP_LSB 4 -#define PKT_DSC_SRTCP_BITS ONE_BIT -#define PKT_DSC_SRTCP_MASK (PKT_DSC_SRTCP_BITS << PKT_DSC_SRTCP_LSB) - -#define PKT_DSC_SEGOFFSET_LSB 0 -#define PKT_DSC_SEGOFFSET_BITS THREE_BITS -#define PKT_DSC_SEGOFFSET_MASK \ - (PKT_DSC_SEGOFFSET_BITS << PKT_DSC_SEGOFFSET_LSB) - -/* ********************************************************************** - * PacketDescriptor_t.dstDataSettings - * ********************************************************************** - */ -/* #define PKT_DSC_ARC4BYTECOUNT */ -#define PKT_DSC_ARC4BYTECOUNT_ALL8 0 -#define PKT_DSC_ARC4BYTECOUNT_MSB 1 -#define PKT_DSC_ARC4BYTECOUNT_MSW 2 -#define PKT_DSC_ARC4BYTECOUNT_LSB 60 -#define PKT_DSC_ARC4BYTECOUNT_BITS THREE_BITS -#define PKT_DSC_ARC4BYTECOUNT_MASK (PKT_DSC_ARC4BYTECOUNT_BITS << PKT_DSC_ARC4BYTECOUNT_LSB) - -/* #define PKT_DSC_SYM_OP (symmetric key operation) */ -#define PKT_DSC_SYM_OP_DECRYPT 0 -#define PKT_DSC_SYM_OP_ENCRYPT 1 -#define PKT_DSC_SYM_OP_LSB 59 -#define PKT_DSC_SYM_OP_BITS ONE_BIT -#define PKT_DSC_SYM_OP_MASK (PKT_DSC_SYM_OP_BITS << PKT_DSC_SYM_OP_LSB) - -/* #define PKT_DSC_CPHROFF */ -#define PKT_DSC_CPHROFF_LSB 56 -#define PKT_DSC_CPHROFF_BITS THREE_BITS -#define PKT_DSC_CPHROFF_MASK (PKT_DSC_CPHROFF_BITS << PKT_DSC_CPHROFF_LSB) - -/* #define PKT_DSC_HASHOFF */ -#define PKT_DSC_HASHOFF_LSB 54 -#define PKT_DSC_HASHOFF_BITS TWO_BITS -#define PKT_DSC_HASHOFF_MASK (PKT_DSC_HASHOFF_BITS << PKT_DSC_HASHOFF_LSB) - -/* #define PKT_DSC_HASHSRC */ -#define PKT_DSC_HASHSRC_DMA 0 -#define PKT_DSC_HASHSRC_CIPHER 1 -#define PKT_DSC_HASHSRC_LSB 53 -#define PKT_DSC_HASHSRC_BITS ONE_BIT -#define PKT_DSC_HASHSRC_MASK (PKT_DSC_HASHSRC_BITS << PKT_DSC_HASHSRC_LSB) - -/* #define PKT_DSC_CKSUMOFF */ -#define PKT_DSC_CKSUMOFF_LSB 41 -#define PKT_DSC_CKSUMOFF_BITS TWELVE_BITS -#define PKT_DSC_CKSUMOFF_MASK (PKT_DSC_CKSUMOFF_BITS << PKT_DSC_CKSUMOFF_LSB) - -/* #define PKT_DSC_CKSUMSRC */ -#define PKT_DSC_CKSUMSRC_DMA 0 -#define PKT_DSC_CKSUMSRC_CIPHER 1 -#define PKT_DSC_CKSUMSRC_LSB 40 -#define PKT_DSC_CKSUMSRC_BITS ONE_BIT -#define PKT_DSC_CKSUMSRC_MASK (PKT_DSC_CKSUMSRC_BITS << PKT_DSC_CKSUMSRC_LSB) - -/* #define PKT_DSC_CPHR_DST_ADDR */ -#define PKT_DSC_CPHR_DST_ADDR_LSB 0 -#define PKT_DSC_CPHR_DST_ADDR_BITS FOURTY_BITS -#define PKT_DSC_CPHR_DST_ADDR_MASK \ - (PKT_DSC_CPHR_DST_ADDR_BITS << PKT_DSC_CPHR_DST_ADDR_LSB) - -/* #define PKT_DSC_CPHR_DST_DWOFFSET */ -#define PKT_DSC_CPHR_DST_DWOFFSET_LSB 3 -#define PKT_DSC_CPHR_DST_DWOFFSET_BITS TWO_BITS -#define PKT_DSC_CPHR_DST_DWOFFSET_MASK \ - (PKT_DSC_CPHR_DST_DWOFFSET_BITS << PKT_DSC_CPHR_DST_DWOFFSET_LSB) - - /* #define PKT_DSC_CPHR_DST_OFFSET */ -#define PKT_DSC_CPHR_DST_OFFSET_LSB 0 -#define PKT_DSC_CPHR_DST_OFFSET_BITS THREE_BITS -#define PKT_DSC_CPHR_DST_OFFSET_MASK \ - (PKT_DSC_CPHR_DST_OFFSET_BITS << PKT_DSC_CPHR_DST_OFFSET_LSB) - -/* ********************************************************************** - * PacketDescriptor_t.authDstNonceLow - * ********************************************************************** - */ -/* #define PKT_DSC_NONCE_LOW */ -#define PKT_DSC_NONCE_LOW_LSB 40 -#define PKT_DSC_NONCE_LOW_BITS TWENTYFOUR_BITS -#define PKT_DSC_NONCE_LOW_MASK \ - (PKT_DSC_NONCE_LOW_BITS << PKT_DSC_NONCE_LOW_LSB) - -/* #define PKT_DSC_AUTH_DST_ADDR */ -#define PKT_DSC_AUTH_DST_ADDR_LSB 0 -#define PKT_DSC_AUTH_DST_ADDR_BITS FOURTY_BITS -#define PKT_DSC_AUTH_DST_ADDR_MASK \ - (PKT_DSC_AUTH_DST_ADDR_BITS << PKT_DSC_AUTH_DST_ADDR_LSB) - -/* #define PKT_DSC_CIPH_OFF_HI */ -#define PKT_DSC_CIPH_OFF_HI_LSB 0 -#define PKT_DSC_CIPH_OFF_HI_BITS FIVE_BITS -#define PKT_DSC_CIPH_OFF_HI_MASK (PKT_DSC_CIPH_OFF_HI_BITS << PKT_DSC_CIPH_OFF_HI_LSB) - -/* ********************************************************************** - * PacketDescriptor_t.ckSumDstNonceHiCFBMaskLLWMask - * ********************************************************************** - */ -/* #define PKT_DSC_HASH_BYTE_OFF */ -#define PKT_DSC_HASH_BYTE_OFF_LSB 61 -#define PKT_DSC_HASH_BYTE_OFF_BITS THREE_BITS -#define PKT_DSC_HASH_BYTE_OFF_MASK (PKT_DSC_HASH_BYTE_OFF_BITS << PKT_DSC_HASH_BYTE_OFF_LSB) - -/* #define PKT_DSC_PKTLEN_BYTES */ -#define PKT_DSC_PKTLEN_BYTES_LSB 58 -#define PKT_DSC_PKTLEN_BYTES_BITS THREE_BITS -#define PKT_DSC_PKTLEN_BYTES_MASK (PKT_DSC_PKTLEN_BYTES_BITS << PKT_DSC_PKTLEN_BYTES_LSB) - -/* #define PKT_DSC_LASTWORD */ -#define PKT_DSC_LASTWORD_128 0 -#define PKT_DSC_LASTWORD_96MASK 1 -#define PKT_DSC_LASTWORD_64MASK 2 -#define PKT_DSC_LASTWORD_32MASK 3 -#define PKT_DSC_LASTWORD_LSB 56 -#define PKT_DSC_LASTWORD_BITS TWO_BITS -#define PKT_DSC_LASTWORD_MASK (PKT_DSC_LASTWORD_BITS << PKT_DSC_LASTWORD_LSB) - -/* #define PKT_DSC_CFB_MASK */ -#define PKT_DSC_CFB_MASK_LSB 48 -#define PKT_DSC_CFB_MASK_BITS EIGHT_BITS -#define PKT_DSC_CFB_MASK_MASK (PKT_DSC_CFB_MASK_BITS << PKT_DSC_CFB_MASK_LSB) - -/* #define PKT_DSC_NONCE_HI */ -#define PKT_DSC_NONCE_HI_LSB 40 -#define PKT_DSC_NONCE_HI_BITS EIGHT_BITS -#define PKT_DSC_NONCE_HI_MASK (PKT_DSC_NONCE_HI_BITS << PKT_DSC_NONCE_HI_LSB) - -/* #define PKT_DSC_CKSUM_DST_ADDR */ -#define PKT_DSC_CKSUM_DST_ADDR_LSB 5 -#define PKT_DSC_CKSUM_DST_ADDR_BITS THIRTY_FIVE_BITS -#define PKT_DSC_CKSUM_DST_ADDR_MASK (PKT_DSC_CKSUM_DST_ADDR_BITS << PKT_DSC_CKSUM_DST_ADDR_LSB) - -/* #define PKT_DSC_IV_OFF_HI */ -#define PKT_DSC_IV_OFF_HI_LSB 0 -#define PKT_DSC_IV_OFF_HI_BITS FIVE_BITS -#define PKT_DSC_IV_OFF_HI_MASK (PKT_DSC_IV_OFF_HI_BITS << PKT_DSC_IV_OFF_HI_LSB) - - -/* ****************************************************************** - * Control Error Code and Conditions - * ****************************************************************** - */ -#define CTL_ERR_NONE 0x0000 /* No Error */ -#define CTL_ERR_CIPHER_OP 0x0001 /* Unknown Cipher Op */ -#define CTL_ERR_MODE 0x0002 /* Unknown or Not Allowed Mode */ -#define CTL_ERR_CHKSUM_SRC 0x0004 /* Unknown CkSum Src - UNUSED */ -#define CTL_ERR_CFB_MASK 0x0008 /* Forbidden CFB Mask - UNUSED */ -#define CTL_ERR_OP 0x0010 /* Unknown Ctrl Op - UNUSED */ -#define CTL_ERR_UNDEF1 0x0020 /* UNUSED */ -#define CTL_ERR_UNDEF2 0x0040 /* UNUSED */ -#define CTL_ERR_DATA_READ 0x0080 /* Data Read Error */ -#define CTL_ERR_DESC_CTRL 0x0100 /* Descriptor Ctrl Field Error */ - -#define CTL_ERR_TIMEOUT 0x1000 /* Message Response Timeout */ - -/* ****************************************************************** - * Data Error Code and Conditions - * ****************************************************************** - */ -#define DATA_ERR_NONE 0x0000 /* No Error */ -#define DATA_ERR_LEN_CIPHER 0x0001 /* Not Enough Data To Cipher */ -#define DATA_ERR_IV_ADDR 0x0002 /* Illegal IV Loacation */ -#define DATA_ERR_WD_LEN_AES 0x0004 /* Illegal Nb Words To AES */ -#define DATA_ERR_BYTE_COUNT 0x0008 /* Illegal Pad And ByteCount Spec */ -#define DATA_ERR_LEN_CKSUM 0x0010 /* Not Enough Data To CkSum */ -#define DATA_ERR_OP 0x0020 /* Unknown Data Op */ -#define DATA_ERR_UNDEF1 0x0040 /* UNUSED */ -#define DATA_ERR_READ 0x0080 /* Data Read Error */ -#define DATA_ERR_WRITE 0x0100 /* Data Write Error */ - - -/* - * Common Descriptor - * NOTE: Size of struct is size of cacheline. - */ - -typedef struct OperationDescriptor_s { - uint64_t phys_self; - uint32_t stn_id; - uint32_t flags; - uint32_t cpu; - uint32_t seq_num; - uint64_t vaddr; -} OperationDescriptor_t, *OperationDescriptor_pt; - - -/* - * This defines the security data descriptor format - */ -typedef struct PacketDescriptor_s { - uint64_t srcLengthIVOffUseIVNext; - uint64_t dstDataSettings; - uint64_t authDstNonceLow; - uint64_t ckSumDstNonceHiCFBMaskLLWMask; -} PacketDescriptor_t, *PacketDescriptor_pt; - -typedef struct { - uint8_t *user_auth; - uint8_t *user_src; - uint8_t *user_dest; - uint8_t *user_state; - uint8_t *kern_auth; - uint8_t *kern_src; - uint8_t *kern_dest; - uint8_t *kern_state; - uint8_t *aligned_auth; - uint8_t *aligned_src; - uint8_t *aligned_dest; - uint8_t *aligned_state; -} xlr_sec_drv_user_t, *xlr_sec_drv_user_pt; - -typedef struct symkey_desc { - OperationDescriptor_t op_ctl; /* size is cacheline */ - PacketDescriptor_t pkt_desc[2]; /* size is cacheline */ - ControlDescriptor_t ctl_desc; /* makes this aligned */ - uint64_t control; /* message word0 */ - uint64_t data; /* message word1 */ - uint64_t ctl_result; - uint64_t data_result; - struct symkey_desc *alloc; /* real allocated addr */ - xlr_sec_drv_user_t user; - //volatile atomic_t flag_complete; - //struct semaphore sem_complete; - //wait_queue_t submit_wait; - - uint8_t *next_src_buf; - uint32_t next_src_len; - - uint8_t *next_dest_buf; - uint32_t next_dest_len; - - uint8_t *next_auth_dest; - uint8_t *next_cksum_dest; - - void *ses; -} symkey_desc_t, *symkey_desc_pt; - - -/* - * ************************************************************************** - * RSA Block - * ************************************************************************** - */ - -/* - * RSA and ECC Block - * ================= - * - * A 2-word message ring descriptor is used to pass all information - * pertaining to the RSA or ECC operation: - * - * 63 61 60 54 53 52 40 39 5 4 3 2 0 - * ----------------------------------------------------------------------------------------------------- - * | Ctrl | Op Class | Valid Op | Op Ctrl0 | Source Addr | Software Scratch0 | Global src data offset | - * ----------------------------------------------------------------------------------------------------- - * 3 7 1 13 35 2 3 - * - * - * 63 61 60 54 53 52 51 50 40 39 5 4 3 2 0 - * -------------------------------------------------------------------------------------------------------------------------------- - * | Ctrl | Destination Id | WRB_COH | WRB_L2ALLOC | DF_L2ALLOC | Op Ctrl1 | Dest Addr | Software Scratch1 | Global dst data offset | - * -------------------------------------------------------------------------------------------------------------------------------- - * 3 7 1 1 1 11 35 2 3 - * - * - * Op Class = 7'h0_0 Modular exponentiation - * 7'h0_1 ECC (including prime modular ops and binary GF ops) - * REMAINDER UNDEF - * - * Valid Op = 1'b1 Will cause operation to start; descriptors sent back at end of operation - * 1'b0 No operation performed; descriptors sent back right away - * - * RSA ECC - * === === - * Op Ctrl0 = BlockWidth[1] {TYPE[6:0], FUNCTION[5:0]} - * LoadConstant[1] - * ExponentWidth[10:0] - * RSA Only - * ======== - * Block Width = 1'b1 1024 bit op - * = 1'b0 512 bit op - * Load Constant = 1'b1 Load constant from data structure - * 1'b0 Preserve old constant (this assumes - * Source Addr points to RSAData_pt->Exponent - * or that the length of Constant is 0) - * Exponent Width = 11-bit expression of exponent width EXPRESSED IN NUMBER OF BITS - * - * ECC Only - * ======== - * - * TYPE = 7'h0_0 ECC prime 160 - * 7'h0_1 ECC prime 192 - * 7'h0_2 ECC prime 224 - * 7'h0_3 ECC prime 256 - * 7'h0_4 ECC prime 384 - * 7'h0_5 ECC prime 512 - * - * 7'h0_6 through 7'h1_f UNDEF - * - * 7'h2_0 ECC bin 163 - * 7'h2_1 ECC bin 191 - * 7'h2_2 ECC bin 233 - * - * 7'h2_3 through 7'h6_f UNDEF - * - * 7'h7_0 ECC UC load - * - * 7'b7_1 through 7'b7_f UNDEF - * - * Prime field Binary field - * =========== ============ - * FUNCTION = 6'h0_0 Point multiplication R = k.P Point multiplication R = k.P - * 6'h0_1 Point addition R = P + Q Binary GF inversion C(x) = 1 / A(x) mod F(x) - * 6'h0_2 Point double R = 2 x P Binary GF multiplication C(x) = B(x) * A(x) mod F(x) - * 6'h0_3 Point verification R ? Binary GF addition C(x) = B(x) + A(x) mod F(x) - * 6'h0_4 Modular addition c = x + y mod m UNDEF - * 6'h0_5 Modular substraction c = x - y mod m UNDEF - * 6'h0_6 Modular multiplication c = x * y mod m UNDEF - * 6'h0_7 Modular division c = x / y mod m UNDEF - * 6'h0_8 Modular inversion c = 1 / y mod m UNDEF - * 6'h0_9 Modular reduction c = x mod m UNDEF - * - * 6'h0_a - * through UNDEF UNDEF - * 6'h3_f - * - * Source Addr = 35 MSB of pointer to source address (i.e., cache-line aligned) - * - * Software Scratch0 = Two bit field ignored by engine and returned as is in free descriptor - * - * Global src data offset = Nb BYTES to right-shift data by before presenting it to engines - * (0-7); allows realignment of byte-aligned, non-double-word aligned data - * - * RSA ECC - * === === - * OpCtrl1 = ModulusWidth[10:0] Not used - * RSA Only - * ======== - * Modulus Width = 11-bit expression of modulus width EXPRESSED IN NUMBER OF BITS - * - * Dest Addr = 35 MSB of pointer to destination address (i.e., cache-line aligned) - * - * Software Scratch1 = Two bit field ignored by engine and returned as is in free descriptor - * - * Global dst data offset = Nb BYTES to left-shift (double-word boundary aligned) data by before writing it to memory - * - * - */ - -/* - * ECC data formats - */ - -/********************************************************** - * * - * ECC prime data formats * - * * - ********************************************************** - * - * - * The size of all quantities below is that of the precision - * of the chosen op (160, 192, ...) ROUNDED UP to a multiple - * of 8 bytes, i.e., 3 dwords (160, 192), 4 dwords (224, 256) - * 6 dwords (384) and 8 dwords (512) and padded with zeroes - * when necessary. - * - * The only exception to this is the key quantity (k) which - * needs to be rounded up to 32 bytes in all cases and padded - * with zeroes; therefore the key needs to be 4 dwords (160, 192, - * 224, 256) or 8 dwords (384, 512) - * - * The total lengths in dwords that are read and in - * bytes that are written, for each operation and - * length group, are specified at the bottom of each - * datastructure. - * - * In all that follows, m is the modulus and cst is the constant, - * cst = 2 ^ (2*length + 4) mod m . a and b are the curve - * parameters. - * - * 0) UC load - * - * DATA IN DATA OUT - * ======= ======== - * src+glb_off-> Dword_0 N/A - * . - * . - * . - * Dword_331 - * 332 dw - * - * 1) Point multiplication R(x_r, y_r) = k . P(x_p, y_p) - * - * DATA IN DATA OUT - * ======= ======== - * src+glb_off-> x_p dst+glb_off-> x_r - * x_p y_r - * y_p 2x(3/4/6/8)= - * y_p 6/8/12/16 dw - * a - * k - * m - * cst - * 7x(3/4/6/8)+(4/4/8/8)= - * 25/32/50/64 dw - * - * 2) Point addition R(x_r, y_r) = P(x_p, y_p) + Q(x_q, y_q) - * - * DATA IN DATA OUT - * ======= ======== - * src+glb_off-> x_p dst+glb_off-> x_r - * y_p y_r - * x_q 2x(3/4/6/8)= - * y_q 6/8/12/16 dw - * a - * m - * cst - * 7x(3/4/6/8)= - * 21/28/42/56 dw - * - * 3) Point double R(x_r, y_r) = 2 . P(x_p, y_p) - * - * DATA IN DATA OUT - * ======= ======== - * src+glb_off-> x_p dst+glb_off-> x_r - * y_p y_r - * a 2x(3/4/6/8)= - * m 6/8/12/16 dw - * cst - * 5x(3/4/6/8)= - * 15/20/30/40 dw - * - * 4) Point verification Is_On_Curve = P(x_p, y_p) on curve ? 1 : 0 - * - * DATA IN DATA OUT - * ======= ======== - * src+glb_off-> x_p dst+glb_off-> Is_On_Curve - * y_p 1 dw - * a - * b - * m - * cst - * 6x(3/4/6/8)= - * 18/24/36/48 dw - * - * 5) Modular addition c = x + y mod m - * - * DATA IN DATA OUT - * ======= ======== - * src+glb_off-> x dst+glb_off-> c - * y 3/4/6/8 dw - * m - * 3x(3/4/6/8)= - * 9/12/18/24 dw - * - * 6) Modular substraction c = x - y mod m - * - * DATA IN DATA OUT - * ======= ======== - * src+glb_off-> x dst+glb_off-> c - * y 3/4/6/8 dw - * m - * 3x(3/4/6/8)= - * 9/12/18/24 dw - * - * 7) Modular multiplication c = x * y mod m - * - * DATA IN DATA OUT - * ======= ======== - * src+glb_off-> x dst+glb_off-> c - * y 3/4/6/8 dw - * m - * cst - * 4x(3/4/6/8)= - * 12/16/24/32 dw - * - * 8) Modular division c = x / y mod m - * - * DATA IN DATA OUT - * ======= ======== - * src+glb_off-> y dst+glb_off-> c - * x 3/4/6/8 dw - * m - * 3x(3/4/6/8)= - * 9/12/18/24 dw - * - * 9) Modular inversion c = 1 / y mod m - * - * DATA IN DATA OUT - * ======= ======== - * src+glb_off-> y dst+glb_off-> c - * m 3/4/6/8 dw - * 2x(3/4/6/8)= - * 6/8/12/16 dw - * - * 10) Modular reduction c = x mod m - * - * DATA IN DATA OUT - * ======= ======== - * src+glb_off-> x dst+glb_off-> c - * m 3/4/6/8 dw - * 2x(3/4/6/8)= - * 6/8/12/16 dw - * - */ - -/********************************************************** - * * - * ECC binary data formats * - * * - ********************************************************** - * - * - * The size of all quantities below is that of the precision - * of the chosen op (163, 191, 233) ROUNDED UP to a multiple - * of 8 bytes, i.e. 3 dwords for (163, 191) and 4 dwords for - * (233), padded with zeroes as necessary. - * - * The total lengths in dwords that are read and written, - * for each operation and length group, are specified - * at the bottom of each datastructure. - * In all that follows, b is the curve parameter. - * - * 1) Point multiplication R(x_r, y_r) = k . P(x_p, y_p) - * - * DATA IN DATA OUT - * ======= ======== - * src+glb_off-> b dst+glb_off-> x_r - * k y_r - * x_p 2x(3/4) - * y_p 6/8 dw - * 4x(3/4)= - * 12/16 dw - * - * 2) Binary GF inversion C(x) = 1 / A(x) mod F(x) - * - * DATA IN DATA OUT - * ======= ======== - * src+glb_off-> A dst+glb_off-> C - * 1x(3/4)= 1x(3/4) - * 3/4 dw 3/4 dw - * - * 3) Binary GF multiplication C(x) = B(x) * A(x) mod F(x) - * - * DATA IN DATA OUT - * ======= ======== - * src+glb_off-> A dst+glb_off-> C - * B 1x(3/4) - * 2x(3/4)= 3/4 dw - * 6/8 dw - * - * 4) Binary GF addition C(x) = B(x) + A(x) mod F(x) - * - * DATA IN DATA OUT - * ======= ======== - * src+glb_off-> A dst+glb_off-> C - * B 1x(3/4) - * 2x(3/4)= 3/4 dw - * 6/8dw - * - */ - -/* - * RSA data format - */ - -/* - * IMPORTANT NOTE: - * - * As specified in the datastructures below, - * the engine assumes all data (including - * exponent and modulus) to be adjacent on - * dword boundaries, e.g., - * - * Operation length = 512 bits - * Exponent length = 16 bits - * Modulus length = 512 bits - * - * The engine expects to read: - * - * 63 0 - * ----------------------- - * | | Constant0 - * ----------------------- - * | | Constant1 - * ----------------------- - * | | Constant2 - * ----------------------- - * | | Constant3 - * ----------------------- - * | | Constant4 - * ----------------------- - * | | Constant5 - * ----------------------- - * | | Constant6 - * ----------------------- - * | | Constant7 - * ----------------------- - * | IGNORED |B1|B0| Exponent0 (Exponent length = 16 bits = 2 bytes, so only 2 least significant bytes of exponent used) - * ----------------------- - * | | Modulus0 - * ----------------------- - * | | Modulus1 - * ----------------------- - * | | Modulus2 - * ----------------------- - * | | Modulus3 - * ----------------------- - * | | Modulus4 - * ----------------------- - * | | Modulus5 - * ----------------------- - * | | Modulus6 - * ----------------------- - * | | Modulus7 - * ----------------------- - * | | Message0 - * ----------------------- - * | | Message1 - * ----------------------- - * | | Message2 - * ----------------------- - * | | Message3 - * ----------------------- - * | | Message4 - * ----------------------- - * | | Message5 - * ----------------------- - * | | Message6 - * ----------------------- - * | | Message7 - * ----------------------- - * - */ - -/* #define PUBKEY_CTL_CTL */ -#define PUBKEY_CTL_CTL_LSB 61 -#define PUBKEY_CTL_CTL_BITS THREE_BITS -#define PUBKEY_CTL_CTL_MASK (PUBKEY_CTL_CTL_BITS << PUBKEY_CTL_CTL_LSB) - -/* #define PUBKEY_CTL_OP_CLASS */ -#define PUBKEY_CTL_OP_CLASS_RSA 0 -#define PUBKEY_CTL_OP_CLASS_ECC 1 -#define PUBKEY_CTL_OP_CLASS_LSB 54 -#define PUBKEY_CTL_OP_CLASS_BITS SEVEN_BITS -#define PUBKEY_CTL_OP_CLASS_MASK (PUBKEY_CTL_OP_CLASS_BITS << PUBKEY_CTL_OP_CLASS_LSB) - -/* #define PUBKEY_CTL_VALID */ -#define PUBKEY_CTL_VALID_FALSE 0 -#define PUBKEY_CTL_VALID_TRUE 1 -#define PUBKEY_CTL_VALID_LSB 53 -#define PUBKEY_CTL_VALID_BITS ONE_BIT -#define PUBKEY_CTL_VALID_MASK \ - (PUBKEY_CTL_VALID_BITS << PUBKEY_CTL_VALID_LSB) - -/* #define PUBKEY_CTL_ECC_TYPE */ -#define PUBKEY_CTL_ECC_TYPE_PRIME_160 0 -#define PUBKEY_CTL_ECC_TYPE_PRIME_192 1 -#define PUBKEY_CTL_ECC_TYPE_PRIME_224 2 -#define PUBKEY_CTL_ECC_TYPE_PRIME_256 3 -#define PUBKEY_CTL_ECC_TYPE_PRIME_384 4 -#define PUBKEY_CTL_ECC_TYPE_PRIME_512 5 -#define PUBKEY_CTL_ECC_TYPE_BIN_163 0x20 -#define PUBKEY_CTL_ECC_TYPE_BIN_191 0x21 -#define PUBKEY_CTL_ECC_TYPE_BIN_233 0x22 -#define PUBKEY_CTL_ECC_TYPE_UC_LOAD 0x70 -#define PUBKEY_CTL_ECC_TYPE_LSB 46 -#define PUBKEY_CTL_ECC_TYPE_BITS SEVEN_BITS -#define PUBKEY_CTL_ECC_TYPE_MASK (PUBKEY_CTL_ECC_TYPE_BITS << PUBKEY_CTL_ECC_TYPE_LSB) - -/* #define PUBKEY_CTL_ECC_FUNCTION */ -#define PUBKEY_CTL_ECC_FUNCTION_NOP 0 -#define PUBKEY_CTL_ECC_FUNCTION_POINT_MUL 0 -#define PUBKEY_CTL_ECC_FUNCTION_POINT_ADD 1 -#define PUBKEY_CTL_ECC_FUNCTION_POINT_DBL 2 -#define PUBKEY_CTL_ECC_FUNCTION_POINT_VFY 3 -#define PUBKEY_CTL_ECC_FUNCTION_MODULAR_ADD 4 -#define PUBKEY_CTL_ECC_FUNCTION_MODULAR_SUB 5 -#define PUBKEY_CTL_ECC_FUNCTION_MODULAR_MUL 6 -#define PUBKEY_CTL_ECC_FUNCTION_MODULAR_DIV 7 -#define PUBKEY_CTL_ECC_FUNCTION_MODULAR_INV 8 -#define PUBKEY_CTL_ECC_FUNCTION_MODULAR_RED 9 -#define PUBKEY_CTL_ECC_FUNCTION_LSB 40 -#define PUBKEY_CTL_ECC_FUNCTION_BITS SIX_BITS -#define PUBKEY_CTL_ECC_FUNCTION_MASK (PUBKEY_CTL_ECC_FUNCTION_BITS << PUBKEY_CTL_ECC_FUNCTION_LSB) - -/* #define PUBKEY_CTL_BLKWIDTH */ -#define PUBKEY_CTL_BLKWIDTH_512 0 -#define PUBKEY_CTL_BLKWIDTH_1024 1 -#define PUBKEY_CTL_BLKWIDTH_LSB 52 -#define PUBKEY_CTL_BLKWIDTH_BITS ONE_BIT -#define PUBKEY_CTL_BLKWIDTH_MASK \ - (PUBKEY_CTL_BLKWIDTH_BITS << PUBKEY_CTL_BLKWIDTH_LSB) - -/* #define PUBKEY_CTL_LD_CONST */ -#define PUBKEY_CTL_LD_CONST_OLD 0 -#define PUBKEY_CTL_LD_CONST_NEW 1 -#define PUBKEY_CTL_LD_CONST_LSB 51 -#define PUBKEY_CTL_LD_CONST_BITS ONE_BIT -#define PUBKEY_CTL_LD_CONST_MASK \ - (PUBKEY_CTL_LD_CONST_BITS << PUBKEY_CTL_LD_CONST_LSB) - -/* #define PUBKEY_CTL_EXPWIDTH */ -#define PUBKEY_CTL_EXPWIDTH_LSB 40 -#define PUBKEY_CTL_EXPWIDTH_BITS ELEVEN_BITS -#define PUBKEY_CTL_EXPWIDTH_MASK \ - (PUBKEY_CTL_EXPWIDTH_BITS << PUBKEY_CTL_EXPWIDTH_LSB) - -/* #define PUBKEY_CTL_SRCADDR */ -#define PUBKEY_CTL_SRCADDR_LSB 0 -#define PUBKEY_CTL_SRCADDR_BITS FOURTY_BITS -#define PUBKEY_CTL_SRCADDR_MASK \ - (PUBKEY_CTL_SRCADDR_BITS << PUBKEY_CTL_SRCADDR_LSB) - -/* #define PUBKEY_CTL_SRC_OFFSET */ -#define PUBKEY_CTL_SRC_OFFSET_LSB 0 -#define PUBKEY_CTL_SRC_OFFSET_BITS THREE_BITS -#define PUBKEY_CTL_SRC_OFFSET_MASK \ - (PUBKEY_CTL_SRC_OFFSET_BITS << PUBKEY_CTL_SRC_OFFSET_LSB) - - -/* #define PUBKEY_CTL1_CTL */ -#define PUBKEY_CTL1_CTL_LSB 61 -#define PUBKEY_CTL1_CTL_BITS THREE_BITS -#define PUBKEY_CTL1_CTL_MASK (PUBKEY_CTL_CTL_BITS << PUBKEY_CTL_CTL_LSB) - -/* #define PUBKEY_CTL1_MODWIDTH */ -#define PUBKEY_CTL1_MODWIDTH_LSB 40 -#define PUBKEY_CTL1_MODWIDTH_BITS ELEVEN_BITS -#define PUBKEY_CTL1_MODWIDTH_MASK \ - (PUBKEY_CTL1_MODWIDTH_BITS << PUBKEY_CTL1_MODWIDTH_LSB) - -/* #define PUBKEY_CTL1_DSTADDR */ -#define PUBKEY_CTL1_DSTADDR_LSB 0 -#define PUBKEY_CTL1_DSTADDR_BITS FOURTY_BITS -#define PUBKEY_CTL1_DSTADDR_MASK \ - (PUBKEY_CTL1_DSTADDR_BITS << PUBKEY_CTL1_DSTADDR_LSB) - -/* #define PUBKEY_CTL1_DST_OFFSET */ -#define PUBKEY_CTL1_DST_OFFSET_LSB 0 -#define PUBKEY_CTL1_DST_OFFSET_BITS THREE_BITS -#define PUBKEY_CTL1_DST_OFFSET_MASK \ - (PUBKEY_CTL1_DST_OFFSET_BITS << PUBKEY_CTL1_DST_OFFSET_LSB) - -/* - * Upon completion of operation, the RSA block returns a 2-word free descriptor - * in the following format: - * - * 63 61 60 54 53 52 51 49 48 40 39 5 4 3 2 0 - * ------------------------------------------------------------------------------------------------------------------------- - * | Ctrl | Destination Id | 2'b00 | Desc Ctrl | Control Error | Source Address | Software Scratch0 | Global src data offset | - * ------------------------------------------------------------------------------------------------------------------------- - * | Ctrl | Destination Id | 2'b00 | Desc Ctrl | Data Error | Dest Address | Software Scratch1 | Global dst data offset | - * ------------------------------------------------------------------------------------------------------------------------- - * - * The Control and Data Error codes are enumerated below - * - * Error conditions - * ================ - * - * Control Error Code Control Error Condition - * ------------------ ----------------------- - * 9'h000 No Error - * 9'h001 Undefined Op Class - * 9'h002 Undefined ECC TYPE (ECC only) - * 9'h004 Undefined ECC FUNCTION (ECC only) - * 9'h008 ECC timeout (ECC only) - * 9'h010 UNUSED - * 9'h020 UNUSED - * 9'h040 UNUSED - * 9'h080 Data Read Error - * 9'h100 Descriptor Ctrl Field Error (D0.Ctrl != SOP || D1.Ctrl != EOP) - * - * Data Error Code Data Error Condition - * --------------- -------------------- - * 9'h000 No Error - * 9'h001 Exponent Width > Block Width (RSA Only) - * 9'h002 Modulus Width > Block Width (RSA Only) - * 9'h004 UNUSED - * 9'h008 UNUSED - * 9'h010 UNUSED - * 9'h020 UNUSED - * 9'h040 UNUSED - * 9'h080 Data Read Error - * 9'h100 UNUSED - */ - -/* - * Result Data Word for Message Ring Descriptor - */ - -/* #define PUBKEY_RSLT_CTL_CTL */ -#define PUBKEY_RSLT_CTL_CTL_LSB 61 -#define PUBKEY_RSLT_CTL_CTL_BITS THREE_BITS -#define PUBKEY_RSLT_CTL_CTL_MASK \ - (PUBKEY_RSLT_CTL_CTL_BITS << PUBKEY_RSLT_CTL_CTL_LSB) - -/* #define PUBKEY_RSLT_CTL_DST_ID */ -#define PUBKEY_RSLT_CTL_DST_ID_LSB 54 -#define PUBKEY_RSLT_CTL_DST_ID_BITS SEVEN_BITS -#define PUBKEY_RSLT_CTL_DST_ID_MASK \ - (PUBKEY_RSLT_CTL_DST_ID_BITS << PUBKEY_RSLT_CTL_DST_ID_LSB) - -/* #define PUBKEY_RSLT_CTL_DESC_CTL */ -#define PUBKEY_RSLT_CTL_DESC_CTL_LSB 49 -#define PUBKEY_RSLT_CTL_DESC_CTL_BITS THREE_BITS -#define PUBKEY_RSLT_CTL_DESC_CTL_MASK \ - (PUBKEY_RSLT_CTL_DESC_CTL_BITS << PUBKEY_RSLT_CTL_DESC_CTL_LSB) - - -/* #define PUBKEY_RSLT_CTL_ERROR */ -#define PUBKEY_RSLT_CTL_ERROR_LSB 40 -#define PUBKEY_RSLT_CTL_ERROR_BITS NINE_BITS -#define PUBKEY_RSLT_CTL_ERROR_MASK \ - (PUBKEY_RSLT_CTL_ERROR_BITS << PUBKEY_RSLT_CTL_ERROR_LSB) - -/* #define PUBKEY_RSLT_CTL_SRCADDR */ -#define PUBKEY_RSLT_CTL_SRCADDR_LSB 0 -#define PUBKEY_RSLT_CTL_SRCADDR_BITS FOURTY_BITS -#define PUBKEY_RSLT_CTL_SRCADDR_MASK \ - (PUBKEY_RSLT_CTL_SRCADDR_BITS << PUBKEY_RSLT_CTL_SRCADDR_LSB) - - -/* #define PUBKEY_RSLT_DATA_CTL */ -#define PUBKEY_RSLT_DATA_CTL_LSB 61 -#define PUBKEY_RSLT_DATA_CTL_BITS THREE_BITS -#define PUBKEY_RSLT_DATA_CTL_MASK \ - (PUBKEY_RSLT_DATA_CTL_BITS << PUBKEY_RSLT_DATA_CTL_LSB) - -/* #define PUBKEY_RSLT_DATA_DST_ID */ -#define PUBKEY_RSLT_DATA_DST_ID_LSB 54 -#define PUBKEY_RSLT_DATA_DST_ID_BITS SEVEN_BITS -#define PUBKEY_RSLT_DATA_DST_ID_MASK \ - (PUBKEY_RSLT_DATA_DST_ID_BITS << PUBKEY_RSLT_DATA_DST_ID_LSB) - -/* #define PUBKEY_RSLT_DATA_DESC_CTL */ -#define PUBKEY_RSLT_DATA_DESC_CTL_LSB 49 -#define PUBKEY_RSLT_DATA_DESC_CTL_BITS THREE_BITS -#define PUBKEY_RSLT_DATA_DESC_CTL_MASK \ - (PUBKEY_RSLT_DATA_DESC_CTL_BITS << PUBKEY_RSLT_DATA_DESC_CTL_LSB) - -/* #define PUBKEY_RSLT_DATA_ERROR */ -#define PUBKEY_RSLT_DATA_ERROR_LSB 40 -#define PUBKEY_RSLT_DATA_ERROR_BITS NINE_BITS -#define PUBKEY_RSLT_DATA_ERROR_MASK \ - (PUBKEY_RSLT_DATA_ERROR_BITS << PUBKEY_RSLT_DATA_ERROR_LSB) - -/* #define PUBKEY_RSLT_DATA_DSTADDR */ -#define PUBKEY_RSLT_DATA_DSTADDR_LSB 40 -#define PUBKEY_RSLT_DATA_DSTADDR_BITS FOURTY_BITS -#define PUBKEY_RSLT_DATA_DSTADDR_MASK \ - (PUBKEY_RSLT_DATA_DSTADDR_BITS << PUBKEY_RSLT_DATA_DSTADDR_LSB) - -/* - * ****************************************************************** - * RSA Block - Data Error Code and Conditions - * ****************************************************************** - */ - -#define PK_CTL_ERR_NONE 0x0000 /* No Error */ -#define PK_CTL_ERR_OP_CLASS 0x0001 /* Undefined Op Class */ -#define PK_CTL_ERR_ECC_TYPE 0x0002 /* Undefined ECC TYPE (ECC only) */ -#define PK_CTL_ERR_ECC_FUNCT 0x0004 /* Undefined ECC FUNCTION (ECC only) */ -#define PK_CTL_ERR_ECC_TIMEOUT 0x0008 /* ECC timeout (ECC only) */ -#define PK_CTL_ERR_READ 0x0080 /* Data Read Error */ -#define PK_CTL_ERR_DESC 0x0100 /* Descriptor Ctrl Field Error - * (D0.Ctrl != SOP || D1.Ctrl != EOP) */ -#define PK_CTL_ERR_TIMEOUT 0x1000 /* Message Responce Timeout */ - -#define PK_DATA_ERR_NONE 0x0000 /* No Error */ -#define PK_DATA_ERR_EXP_WIDTH 0x0001 /* Exponent Width > Block Width */ -#define PK_DATA_ERR_MOD_WIDTH 0x0002 /* Modulus Width > Block Width */ -#define PK_DATA_ERR_READ 0x0080 /* Data Read Error */ - - -/* - * This defines the RSA data format - */ -/* - * typedef struct RSAData_s { - * uint64_t Constant; - * uint64_t Exponent; - * uint64_t Modulus; - * uint64_t Message; - *} RSAData_t, *RSAData_pt; - * - * typedef RSAData_t DHData_t; - * typedef RSAData_pt DHData_pt; - */ - -typedef struct UserPubData_s { - uint8_t *source; - uint8_t *user_result; - uint32_t result_length; -} UserPubData_t, *UserPubData_pt; - -typedef struct pubkey_desc { - OperationDescriptor_t op_ctl; /* size is cacheline */ - uint8_t source[1024]; - uint8_t dest[256]; /* 1024 makes cacheline-aligned */ - uint64_t control0; - uint64_t control1; - uint64_t ctl_result; - uint64_t data_result; - struct pubkey_desc *alloc; - UserPubData_t kern; /* ptrs for temp buffers */ - //volatile atomic_t flag_complete; - //struct semaphore sem_complete; - //wait_queue_t submit_wait; -} pubkey_desc_t, *pubkey_desc_pt; - -/* - * KASUMI F8 and F9 use the IV0/IV1 fields : - * - * 63 41 40 39 37 36 32 31 0 - * ---------------------------------------------------------------------------- - * | |FX/DIRECTION| | F8/BEARER | F8/COUNT | IV0 - * ---------------------------------------------------------------------------- - * 1 5 32 - * - * 63 32 31 0 - * ---------------------------------------------------------------------------- - * | F9/FRESH | F9/COUNT | IV1 - * ---------------------------------------------------------------------------- - * 32 32 - */ -#endif /* _XLR_SEC_DESC_H_ */ Property changes on: head/sys/mips/rmi/dev/sec/desc.h ___________________________________________________________________ Deleted: svn:eol-style ## -1 +0,0 ## -native \ No newline at end of property Deleted: svn:keywords ## -1 +0,0 ## -FreeBSD=%H \ No newline at end of property Deleted: svn:mime-type ## -1 +0,0 ## -text/plain \ No newline at end of property Index: head/sys/mips/rmi/dev/sec/rmilib.c =================================================================== --- head/sys/mips/rmi/dev/sec/rmilib.c (revision 327460) +++ head/sys/mips/rmi/dev/sec/rmilib.c (nonexistent) @@ -1,3076 +0,0 @@ -/*- - * SPDX-License-Identifier: BSD-3-Clause - * - * Copyright (c) 2003-2009 RMI Corporation - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. Neither the name of RMI Corporation, nor the names of its contributors, - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - * - * RMI_BSD - */ - -#include -__FBSDID("$FreeBSD$"); - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include - -#include - -#include -#include -#include -#include -#include -#include -#include -#include - - -/* static int msgrng_stnid_pk0 = MSGRNG_STNID_PK0; */ - -/* #define RMI_SEC_DEBUG */ - -#define SMP_CACHE_BYTES XLR_CACHELINE_SIZE -#define NUM_CHUNKS(size, bits) ( ((size)>>(bits)) + (((size)&((1<<(bits))-1))?1:0) ) - -static const char nib2hex[] = "0123456789ABCDEF"; -symkey_desc_pt g_desc; -struct xlr_sec_command *g_cmd; - -#ifdef XLR_SEC_CMD_DEBUG -static void decode_symkey_desc(symkey_desc_pt desc, uint32_t cfg_vector); -#endif - -static int xlr_sec_cipher_hash_command(xlr_sec_io_pt op, symkey_desc_pt desc, - uint8_t); -static xlr_sec_error_t xlr_sec_setup_descriptor(xlr_sec_io_pt op, - unsigned int flags, symkey_desc_pt desc, uint32_t * cfg_vector); - -static xlr_sec_error_t xlr_sec_setup_packet(xlr_sec_io_pt op, - symkey_desc_pt desc, unsigned int flags, uint64_t * data, - PacketDescriptor_pt pkt_desc, ControlDescriptor_pt ctl_desc, - uint32_t vector, PacketDescriptor_pt next_pkt_desc, - uint8_t multi_frag_flag); -static int xlr_sec_submit_message(symkey_desc_pt desc, uint32_t cfg_vector); -static xlr_sec_error_t xlr_sec_setup_cipher(xlr_sec_io_pt op, - ControlDescriptor_pt ctl_desc, uint32_t * vector); -static xlr_sec_error_t xlr_sec_setup_digest(xlr_sec_io_pt op, - ControlDescriptor_pt ctl_desc, uint32_t * vector); -static xlr_sec_error_t xlr_sec_setup_cksum(xlr_sec_io_pt op, - ControlDescriptor_pt ctl_desc); -static xlr_sec_error_t xlr_sec_control_setup(xlr_sec_io_pt op, - unsigned int flags, uint64_t * control, ControlDescriptor_pt ctl_desc, - xlr_sec_drv_user_t * user, uint32_t vector); -static void xlr_sec_free_desc(symkey_desc_pt desc); - -void print_buf(char *desc, void *data, int len); -xlr_sec_error_t xlr_sec_submit_op(symkey_desc_pt desc); -void xlr_sec_msgring_handler(int bucket, int size, int code, int stid, - struct msgrng_msg *msg, void *data); - -void -xlr_sec_init(struct xlr_sec_softc *sc) -{ - unsigned int i; - xlr_reg_t *mmio; - - mmio = sc->mmio = xlr_io_mmio(XLR_IO_SECURITY_OFFSET); - xlr_write_reg(mmio, SEC_DMA_CREDIT, SEC_DMA_CREDIT_CONFIG); - xlr_write_reg(mmio, SEC_CONFIG2, SEC_CFG2_ROUND_ROBIN_ON); - - for (i = 0; i < 8; i++) - xlr_write_reg(mmio, - SEC_MSG_BUCKET0_SIZE + i, - xlr_is_xls() ? - xls_bucket_sizes.bucket[MSGRNG_STNID_SEC + i] : - bucket_sizes.bucket[MSGRNG_STNID_SEC + i]); - - for (i = 0; i < 128; i++) - xlr_write_reg(mmio, - SEC_CC_CPU0_0 + i, - xlr_is_xls() ? - xls_cc_table_sec.counters[i >> 3][i & 0x07] : - cc_table_sec.counters[i >> 3][i & 0x07]); - - /* - * Register a bucket handler with the phoenix messaging subsystem - * For now, register handler for bucket 0->5 in msg stn 0 - */ - if (register_msgring_handler(TX_STN_SAE, xlr_sec_msgring_handler, NULL)) { - panic("Couldn't register msgring handler 0\n"); - } - return; -} - -int -xlr_sec_setup(struct xlr_sec_session *ses, - struct xlr_sec_command *cmd, - symkey_desc_pt desc) -{ - xlr_sec_io_pt op; - int size, ret_val; - int iv_len; - - desc->ses = ses; - op = &cmd->op; - if (op == NULL) - return (-ENOMEM); - - desc->ctl_desc.instruction = 0; - memset(&desc->ctl_desc.cipherHashInfo, 0, sizeof(CipherHashInfo_t)); - desc->control = 0; - desc->pkt_desc[0].srcLengthIVOffUseIVNext = 0; - desc->pkt_desc[0].dstDataSettings = 0; - desc->pkt_desc[0].authDstNonceLow = 0; - desc->pkt_desc[0].ckSumDstNonceHiCFBMaskLLWMask = 0; - desc->pkt_desc[1].srcLengthIVOffUseIVNext = 0; - desc->pkt_desc[1].dstDataSettings = 0; - desc->pkt_desc[1].authDstNonceLow = 0; - desc->pkt_desc[1].ckSumDstNonceHiCFBMaskLLWMask = 0; - desc->data = 0; - desc->ctl_result = 0; - desc->data_result = 0; - - if (op->flags & XLR_SEC_FLAGS_HIGH_PRIORITY) - if (!xlr_is_xls()) - desc->op_ctl.stn_id++; - - desc->user.user_src = (uint8_t *) (unsigned long)op->source_buf; - desc->user.user_dest = (uint8_t *) (unsigned long)op->dest_buf; - desc->user.user_auth = (uint8_t *) (unsigned long)op->auth_dest; - - if ((op->cipher_type == XLR_SEC_CIPHER_TYPE_ARC4) && - (!op->rc4_state && (op->rc4_loadstate || op->rc4_savestate))) { - printf(" ** Load/Save State and no State **"); - xlr_sec_free_desc(desc); - return (-EINVAL); - } - desc->user.user_state = (uint8_t *) (unsigned long)op->rc4_state; - - switch (op->cipher_type) { - case XLR_SEC_CIPHER_TYPE_NONE: - iv_len = 0; - break; - case XLR_SEC_CIPHER_TYPE_DES: - case XLR_SEC_CIPHER_TYPE_3DES: - iv_len = XLR_SEC_DES_IV_LENGTH; - break; - case XLR_SEC_CIPHER_TYPE_AES128: - case XLR_SEC_CIPHER_TYPE_AES192: - case XLR_SEC_CIPHER_TYPE_AES256: - iv_len = XLR_SEC_AES_IV_LENGTH; - break; - case XLR_SEC_CIPHER_TYPE_ARC4: - iv_len = XLR_SEC_ARC4_IV_LENGTH; - break; - case XLR_SEC_CIPHER_TYPE_KASUMI_F8: - iv_len = XLR_SEC_KASUMI_F8_IV_LENGTH; - break; - - default: - printf(" ** Undefined Cipher Type **"); - xlr_sec_free_desc(desc); - return (-EINVAL); - } - size = op->source_buf_size + iv_len; - - /* - * make sure that there are enough bytes for aes based stream - * ciphers - */ - if (op->cipher_mode == XLR_SEC_CIPHER_MODE_F8 || - op->cipher_mode == XLR_SEC_CIPHER_MODE_CTR) - size += XLR_SEC_AES_BLOCK_SIZE - 1; - - if (op->cipher_type == XLR_SEC_CIPHER_TYPE_NONE) { - if (op->source_buf_size != 0) { - memcpy(desc->user.aligned_src, - (uint8_t *)(uintptr_t)op->source_buf, - op->source_buf_size); - } - } else { - if (ses->multi_frag_flag) { - /* copy IV into temporary kernel source buffer */ - memcpy(desc->user.aligned_src, &op->initial_vector[0], iv_len); - - /* copy input data to temporary kernel source buffer */ - memcpy((uint8_t *) (desc->user.aligned_src + iv_len), - (uint8_t *) (unsigned long)op->source_buf, SEC_MAX_FRAG_LEN); - - desc->next_src_len = op->source_buf_size - SEC_MAX_FRAG_LEN; - memcpy((uint8_t *) (desc->next_src_buf), - (uint8_t *) (unsigned long)(op->source_buf + SEC_MAX_FRAG_LEN), - desc->next_src_len); - - op->source_buf_size = SEC_MAX_FRAG_LEN; - op->source_buf_size += iv_len; - } else { - /* copy IV into temporary kernel source buffer */ - memcpy(desc->user.aligned_src, &op->initial_vector[0], iv_len); - - /* copy input data to temporary kernel source buffer */ - memcpy((uint8_t *) (desc->user.aligned_src + iv_len), - (uint8_t *) (unsigned long)op->source_buf, op->source_buf_size); - op->source_buf_size += iv_len; - } - } - - /* Set source to new kernel space */ - op->source_buf = (uint64_t) (unsigned long)desc->user.aligned_src; - - /* - * Build new dest buffer, for Cipher output only - */ - if (op->cipher_type == XLR_SEC_CIPHER_TYPE_NONE) { - /* - * Digest Engine *NEEDS* this, otherwise it will write at - * 0[x] - */ - op->dest_buf = (uint64_t) (unsigned long)desc->user.aligned_src; - } else { - /* DEBUG -dpk */ - XLR_SEC_CMD_DIAG("dest_buf_size = %d \n", op->dest_buf_size); - size = op->dest_buf_size + iv_len; - - /* - * make sure that there are enough bytes for aes based - * stream ciphers - */ - if (op->cipher_mode == XLR_SEC_CIPHER_MODE_F8 || - op->cipher_mode == XLR_SEC_CIPHER_MODE_CTR) - size += XLR_SEC_AES_BLOCK_SIZE - 1; - op->dest_buf = (uint64_t) (unsigned long)desc->user.aligned_dest; - } - - ret_val = xlr_sec_cipher_hash_command(op, desc, ses->multi_frag_flag); - return (ret_val); - -} - -static int -xlr_sec_cipher_hash_command(xlr_sec_io_pt op, symkey_desc_pt desc, - uint8_t multi_frag_flag) -{ - xlr_sec_error_t err; - uint32_t cfg_vector; - unsigned int setup_flags = 0; - - err = XLR_SEC_ERR_NONE; - cfg_vector = 0; - - if ((op->digest_type == XLR_SEC_DIGEST_TYPE_NONE) && - (op->cipher_type != XLR_SEC_CIPHER_TYPE_ARC4) && - (op->cipher_mode != XLR_SEC_CIPHER_MODE_F8) && - (op->cipher_type != XLR_SEC_CIPHER_TYPE_KASUMI_F8) && - (op->source_buf_size & 0x7)) { - printf("Invalid Cipher Block Size, data len=%d\n", - op->source_buf_size); - return (-EINVAL); - } - do { - - if ((op->cipher_type == XLR_SEC_CIPHER_TYPE_3DES) && - (op->cipher_op == XLR_SEC_CIPHER_OP_DECRYPT)) - setup_flags = XLR_SEC_SETUP_OP_FLIP_3DES_KEY; - - err = xlr_sec_setup_descriptor(op, - setup_flags, - desc, &cfg_vector); - if (err != XLR_SEC_ERR_NONE) - break; - - err = xlr_sec_setup_packet(op, - desc, - op->digest_type != XLR_SEC_DIGEST_TYPE_NONE ? - XLR_SEC_SETUP_OP_CIPHER_HMAC : 0, - &desc->data, - &desc->pkt_desc[0], - &desc->ctl_desc, - cfg_vector, - &desc->pkt_desc[1], - multi_frag_flag); - if (err != XLR_SEC_ERR_NONE) - break; - } while (0); - if (err != XLR_SEC_ERR_NONE) { - return (EINVAL); - } - err = xlr_sec_submit_message(desc, cfg_vector); - return err; -} - -static xlr_sec_error_t -xlr_sec_setup_descriptor(xlr_sec_io_pt op, - unsigned int flags, - symkey_desc_pt desc, - uint32_t * cfg_vector) -{ - xlr_sec_error_t err; - - XLR_SEC_CMD_DIAG("xlr_sec_setup_descriptor: ENTER\n"); - - if ((err = xlr_sec_setup_cipher(op, &desc->ctl_desc, cfg_vector)) != XLR_SEC_ERR_NONE) { - XLR_SEC_CMD_DIAG("xlr_sec_setup_descriptor: xlr_sec_setup_cipher done err %d\n", - (int)err); - return err; - } - if (op->digest_type != XLR_SEC_DIGEST_TYPE_NONE) { - if ((err = xlr_sec_setup_digest(op, &desc->ctl_desc, cfg_vector)) != XLR_SEC_ERR_NONE) { - XLR_SEC_CMD_DIAG("xlr_sec_setup_descriptor: xlr_sec_setup_digest done err %d\n", - (int)err); - return err; - } - } - if ((err = xlr_sec_setup_cksum(op, &desc->ctl_desc)) != XLR_SEC_ERR_NONE) { - XLR_SEC_CMD_DIAG("xlr_sec_setup_descriptor: xlr_sec_setup_cksum done err %d\n", - (int)err); - return err; - } - if ((err = xlr_sec_control_setup(op, - flags, - &desc->control, - &desc->ctl_desc, - &desc->user, - *cfg_vector)) != XLR_SEC_ERR_NONE) { - XLR_SEC_CMD_DIAG("xlr_sec_setup_descriptor: xlr_sec_control_setup done err %d\n", - (int)err); - return err; - } - XLR_SEC_CMD_DIAG("xlr_sec_setup_descriptor: DONE\n"); - return err; -} - - - -static -xlr_sec_error_t -xlr_sec_setup_packet(xlr_sec_io_pt op, - symkey_desc_pt desc, - unsigned int flags, - uint64_t * data, - PacketDescriptor_pt pkt_desc, - ControlDescriptor_pt ctl_desc, - uint32_t vector, - PacketDescriptor_pt next_pkt_desc, - uint8_t multi_frag_flag) -{ - uint32_t len, next_len = 0, len_dwords, last_u64_bytes; - uint64_t addr; - uint64_t seg_addr, next_seg_addr = 0; - uint64_t byte_offset, global_offset; - uint32_t cipher_offset_dwords; - - XLR_SEC_CMD_DIAG("xlr_sec_setup_packet: ENTER vector = %04x\n", vector); - - /* physical address of the source buffer */ - addr = (uint64_t) vtophys((void *)(unsigned long)op->source_buf); - /* cache-aligned base of the source buffer */ - seg_addr = rounddown2(addr, SMP_CACHE_BYTES); - /* offset in bytes to the source buffer start from the segment base */ - byte_offset = addr - seg_addr; - /* global offset: 0-7 bytes */ - global_offset = byte_offset & 0x7; - - - /* - * op->source_buf_size is expected to be the Nb double words to - * stream in (Including Segment address->CP/IV/Auth/CkSum offsets) - */ - - /* - * adjusted length of the whole thing, accounting for the added - * head, sans global_offset (per Paul S.) - */ - - len = op->source_buf_size + byte_offset - global_offset; - if (multi_frag_flag) { - next_seg_addr = (uint64_t)vtophys((void *)(uintptr_t)desc->next_src_buf); - next_seg_addr = rounddown2(next_seg_addr, SMP_CACHE_BYTES); - next_len = desc->next_src_len; - } - /* length of the whole thing in dwords */ - len_dwords = NUM_CHUNKS(len, 3); - /* number of bytes in the last chunk (len % 8) */ - last_u64_bytes = len & 0x07; - - if (op->cipher_offset & 0x7) { - printf("** cipher_offset(%d) fails 64-bit word alignment **", - op->cipher_offset); - - return XLR_SEC_ERR_CIPHER_MODE; /* ! fix ! */ - } - /* - * global_offset is only three bits, so work the number of the whole - * 8-byte words into the global offset. both offset and - * cipher_offset are byte counts - */ - cipher_offset_dwords = (op->iv_offset + byte_offset) >> 3; - - if (op->cipher_mode == XLR_SEC_CIPHER_MODE_F8 || - op->cipher_mode == XLR_SEC_CIPHER_MODE_CTR) { - if (multi_frag_flag) { - int nlhmac = ((op->source_buf_size + global_offset + 7 - op->cipher_offset) >> 3) & 1; - - pkt_desc->srcLengthIVOffUseIVNext = - FIELD_VALUE(PKT_DSC_HASHBYTES, len & 7) | - FIELD_VALUE(PKT_DSC_IVOFF, cipher_offset_dwords) | - FIELD_VALUE(PKT_DSC_PKTLEN, nlhmac + ((len + 7) >> 3)) | - FIELD_VALUE(PKT_DSC_NLHMAC, nlhmac) | - FIELD_VALUE(PKT_DSC_BREAK, 0) | - FIELD_VALUE(PKT_DSC_WAIT, 1) | - FIELD_VALUE(PKT_DSC_NEXT, 1) | - FIELD_VALUE(PKT_DSC_SEGADDR, seg_addr >> (PKT_DSC_SEGADDR_LSB)) | - FIELD_VALUE(PKT_DSC_SEGOFFSET, global_offset); - } else { - int nlhmac = ((op->source_buf_size + global_offset + 7 - op->cipher_offset) >> 3) & 1; - - pkt_desc->srcLengthIVOffUseIVNext = - FIELD_VALUE(PKT_DSC_HASHBYTES, len & 7) | - FIELD_VALUE(PKT_DSC_IVOFF, cipher_offset_dwords) | - FIELD_VALUE(PKT_DSC_PKTLEN, nlhmac + ((len + 7) >> 3)) | - FIELD_VALUE(PKT_DSC_NLHMAC, nlhmac) | - FIELD_VALUE(PKT_DSC_BREAK, 0) | - FIELD_VALUE(PKT_DSC_WAIT, 0) | - FIELD_VALUE(PKT_DSC_SEGADDR, seg_addr >> (PKT_DSC_SEGADDR_LSB)) | - FIELD_VALUE(PKT_DSC_SEGOFFSET, global_offset); - - } - } else { - if (multi_frag_flag) { - pkt_desc->srcLengthIVOffUseIVNext = - FIELD_VALUE(PKT_DSC_HASHBYTES, len & 7) | - FIELD_VALUE(PKT_DSC_IVOFF, cipher_offset_dwords) | - FIELD_VALUE(PKT_DSC_PKTLEN, (len + 7) >> 3) | - FIELD_VALUE(PKT_DSC_BREAK, 0) | - FIELD_VALUE(PKT_DSC_WAIT, 0) | - FIELD_VALUE(PKT_DSC_NEXT, 1) | - FIELD_VALUE(PKT_DSC_SEGADDR, seg_addr >> (PKT_DSC_SEGADDR_LSB)) | - FIELD_VALUE(PKT_DSC_SEGOFFSET, global_offset); - - - next_pkt_desc->srcLengthIVOffUseIVNext = - FIELD_VALUE(PKT_DSC_HASHBYTES, (next_len & 7)) | - FIELD_VALUE(PKT_DSC_IVOFF, 0) | - FIELD_VALUE(PKT_DSC_PKTLEN, (next_len + 7) >> 3) | - FIELD_VALUE(PKT_DSC_BREAK, 0) | - FIELD_VALUE(PKT_DSC_WAIT, 0) | - FIELD_VALUE(PKT_DSC_NEXT, 0) | - FIELD_VALUE(PKT_DSC_SEGADDR, next_seg_addr >> (PKT_DSC_SEGADDR_LSB)) | - FIELD_VALUE(PKT_DSC_SEGOFFSET, 0); - - - } else { - pkt_desc->srcLengthIVOffUseIVNext = - FIELD_VALUE(PKT_DSC_HASHBYTES, len & 7) | - FIELD_VALUE(PKT_DSC_IVOFF, cipher_offset_dwords) | - FIELD_VALUE(PKT_DSC_PKTLEN, (len + 7) >> 3) | - FIELD_VALUE(PKT_DSC_BREAK, 0) | - FIELD_VALUE(PKT_DSC_WAIT, 0) | - FIELD_VALUE(PKT_DSC_SEGADDR, seg_addr >> (PKT_DSC_SEGADDR_LSB)) | - FIELD_VALUE(PKT_DSC_SEGOFFSET, global_offset); - - - } - } - - switch (op->pkt_hmac) { - case XLR_SEC_LOADHMACKEY_MODE_OLD: - CLEAR_SET_FIELD(pkt_desc->srcLengthIVOffUseIVNext, - PKT_DSC_LOADHMACKEY, PKT_DSC_LOADHMACKEY_OLD); - if (multi_frag_flag) { - CLEAR_SET_FIELD(next_pkt_desc->srcLengthIVOffUseIVNext, - PKT_DSC_LOADHMACKEY, PKT_DSC_LOADHMACKEY_OLD); - - } - break; - case XLR_SEC_LOADHMACKEY_MODE_LOAD: - CLEAR_SET_FIELD(pkt_desc->srcLengthIVOffUseIVNext, - PKT_DSC_LOADHMACKEY, PKT_DSC_LOADHMACKEY_LOAD); - if (multi_frag_flag) { - CLEAR_SET_FIELD(next_pkt_desc->srcLengthIVOffUseIVNext, - PKT_DSC_LOADHMACKEY, PKT_DSC_LOADHMACKEY_LOAD); - - } - break; - default: - if (vector & (XLR_SEC_VECTOR_HMAC | XLR_SEC_VECTOR_HMAC2 | XLR_SEC_VECTOR_GCM | XLR_SEC_VECTOR_F9)) { - XLR_SEC_CMD_DIAG("xlr_sec_setup_packet: ERR_LOADHMACKEY_MODE EXIT\n"); - return XLR_SEC_ERR_LOADHMACKEY_MODE; - } - break; - } - - switch (op->pkt_hash) { - case XLR_SEC_PADHASH_PADDED: - CLEAR_SET_FIELD(pkt_desc->srcLengthIVOffUseIVNext, - PKT_DSC_PADHASH, PKT_DSC_PADHASH_PADDED); - if (multi_frag_flag) { - CLEAR_SET_FIELD(next_pkt_desc->srcLengthIVOffUseIVNext, - PKT_DSC_PADHASH, PKT_DSC_PADHASH_PADDED); - } - break; - case XLR_SEC_PADHASH_PAD: - CLEAR_SET_FIELD(pkt_desc->srcLengthIVOffUseIVNext, - PKT_DSC_PADHASH, PKT_DSC_PADHASH_PAD); - if (multi_frag_flag) { - CLEAR_SET_FIELD(next_pkt_desc->srcLengthIVOffUseIVNext, - PKT_DSC_PADHASH, PKT_DSC_PADHASH_PAD); - } - break; - default: - if (vector & (XLR_SEC_VECTOR_MAC | XLR_SEC_VECTOR_HMAC | XLR_SEC_VECTOR_HMAC2)) { - XLR_SEC_CMD_DIAG("xlr_sec_setup_packet: ERR_PADHASH_MODE EXIT\n"); - return XLR_SEC_ERR_PADHASH_MODE; - } - break; - } - - switch (op->pkt_iv) { - case XLR_SEC_PKT_IV_OLD: - CLEAR_SET_FIELD(pkt_desc->srcLengthIVOffUseIVNext, - PKT_DSC_IV, PKT_DSC_IV_OLD); - if (multi_frag_flag) { - CLEAR_SET_FIELD(next_pkt_desc->srcLengthIVOffUseIVNext, - PKT_DSC_IV, PKT_DSC_IV_OLD); - - } - break; - case XLR_SEC_PKT_IV_NEW: - CLEAR_SET_FIELD(pkt_desc->srcLengthIVOffUseIVNext, - PKT_DSC_IV, PKT_DSC_IV_NEW); - if (multi_frag_flag) { - CLEAR_SET_FIELD(next_pkt_desc->srcLengthIVOffUseIVNext, - PKT_DSC_IV, PKT_DSC_IV_NEW); - - } - break; - default: - if (vector & XLR_SEC_VECTOR_CIPHER) { - XLR_SEC_CMD_DIAG("xlr_sec_setup_packet: ERR_PKT_IV_MODE EXIT\n"); - return XLR_SEC_ERR_PKT_IV_MODE; - } - break; - } - - XLR_SEC_CMD_DIAG("xlr_sec_setup_packet: src_buf=%llx phys_src_buf=%llx \n", - (unsigned long long)op->source_buf, (unsigned long long)addr); - - XLR_SEC_CMD_DIAG("xlr_sec_setup_packet: seg_addr=%llx offset=%lld\n", - (unsigned long long)seg_addr, (unsigned long long)byte_offset); - - XLR_SEC_CMD_DIAG("xlr_sec_setup_packet: global src offset: %d, iv_offset=%d\n", - cipher_offset_dwords, op->iv_offset); - - XLR_SEC_CMD_DIAG("xlr_sec_setup_packet: src_buf_sz=%d PKT_LEN=%d\n", - op->source_buf_size, len_dwords); - - /* - * same operation with the destination. cipher offset affects this, - * as well - */ - if (multi_frag_flag) { - next_seg_addr = (uint64_t) vtophys((void *)(unsigned long)(desc->next_dest_buf)); - next_seg_addr = rounddown2(next_seg_addr, SMP_CACHE_BYTES); - } - addr = (uint64_t) vtophys((void *)(unsigned long)op->dest_buf); - seg_addr = rounddown2(addr, SMP_CACHE_BYTES); - byte_offset = addr - seg_addr; - global_offset = byte_offset & 0x7; - - XLR_SEC_CMD_DIAG("xlr_sec_setup_packet: dest_buf=%llx phys_dest_buf=%llx \n", - (unsigned long long)op->dest_buf, (unsigned long long)addr); - - XLR_SEC_CMD_DIAG("xlr_sec_setup_packet: seg_addr=%llx offset=%lld\n", - (unsigned long long)seg_addr, (unsigned long long)byte_offset); - - /* - * Dest Address = (Cipher Dest Address) + (Cipher Offset) + (Global - * Dest Data Offset) - * - * Cipher Dest Address - Cache-line (0xffffffffe0) Cipher Offset - - * Which (64-bit) Word in Cacheline (0-3) Global Dest Data Offset - - * Number of Bytes in (64-bit) Word before data - * - * It must be set for Digest-only Ops, since the Digest engine will - * write data to this address. - */ - cipher_offset_dwords = (op->cipher_offset + byte_offset) >> 3; - - - pkt_desc->dstDataSettings = - /* SYM_OP, HASHSRC */ - FIELD_VALUE(PKT_DSC_CPHROFF, cipher_offset_dwords) | - FIELD_VALUE(PKT_DSC_HASHOFF, (op->digest_offset + byte_offset) >> 3) | - FIELD_VALUE(PKT_DSC_CPHR_DST_ADDR, seg_addr) | - FIELD_VALUE(PKT_DSC_CPHR_DST_DWOFFSET, 0) | - FIELD_VALUE(PKT_DSC_CPHR_DST_OFFSET, global_offset); - - if (multi_frag_flag) { - next_pkt_desc->dstDataSettings = - /* SYM_OP, HASHSRC */ - FIELD_VALUE(PKT_DSC_CPHROFF, cipher_offset_dwords) | - FIELD_VALUE(PKT_DSC_HASHOFF, (op->digest_offset + byte_offset) >> 3) | - FIELD_VALUE(PKT_DSC_CPHR_DST_ADDR, next_seg_addr) | - FIELD_VALUE(PKT_DSC_CPHR_DST_DWOFFSET, 0) | - FIELD_VALUE(PKT_DSC_CPHR_DST_OFFSET, global_offset); - - } - if (op->cipher_type == XLR_SEC_CIPHER_TYPE_ARC4) - pkt_desc->dstDataSettings |= FIELD_VALUE(PKT_DSC_ARC4BYTECOUNT, last_u64_bytes); - - if (op->cipher_type != XLR_SEC_CIPHER_TYPE_NONE) { - switch (op->cipher_op) { - case XLR_SEC_CIPHER_OP_ENCRYPT: - CLEAR_SET_FIELD(pkt_desc->dstDataSettings, - PKT_DSC_SYM_OP, PKT_DSC_SYM_OP_ENCRYPT); - if (multi_frag_flag) { - CLEAR_SET_FIELD(next_pkt_desc->dstDataSettings, - PKT_DSC_SYM_OP, PKT_DSC_SYM_OP_ENCRYPT); - - } - break; - case XLR_SEC_CIPHER_OP_DECRYPT: - CLEAR_SET_FIELD(pkt_desc->dstDataSettings, - PKT_DSC_SYM_OP, PKT_DSC_SYM_OP_DECRYPT); - if (multi_frag_flag) { - CLEAR_SET_FIELD(next_pkt_desc->dstDataSettings, - PKT_DSC_SYM_OP, PKT_DSC_SYM_OP_DECRYPT); - - } - break; - default: - XLR_SEC_CMD_DIAG("xlr_sec_setup_packet: ERR_CIPHER_OP EXIT\n"); - return XLR_SEC_ERR_CIPHER_OP; - } - } - if (flags & XLR_SEC_SETUP_OP_HMAC) { - switch (op->digest_src) { - case XLR_SEC_DIGEST_SRC_DMA: - CLEAR_SET_FIELD(pkt_desc->dstDataSettings, - PKT_DSC_HASHSRC, PKT_DSC_HASHSRC_DMA); - if (multi_frag_flag) { - CLEAR_SET_FIELD(next_pkt_desc->dstDataSettings, - PKT_DSC_HASHSRC, PKT_DSC_HASHSRC_DMA); - - } - break; - case XLR_SEC_DIGEST_SRC_CPHR: - CLEAR_SET_FIELD(pkt_desc->dstDataSettings, - PKT_DSC_HASHSRC, PKT_DSC_HASHSRC_CIPHER); - if (multi_frag_flag) { - CLEAR_SET_FIELD(next_pkt_desc->dstDataSettings, - PKT_DSC_HASHSRC, PKT_DSC_HASHSRC_CIPHER); - } - break; - default: - XLR_SEC_CMD_DIAG("xlr_sec_setup_packet: ERR_DIGEST_SRC EXIT\n"); - return XLR_SEC_ERR_DIGEST_SRC; - } - } - if (op->cksum_type != XLR_SEC_CKSUM_TYPE_NOP) { - switch (op->cksum_src) { - case XLR_SEC_CKSUM_SRC_DMA: - CLEAR_SET_FIELD(pkt_desc->dstDataSettings, - PKT_DSC_CKSUMSRC, PKT_DSC_CKSUMSRC_DMA); - if (multi_frag_flag) { - CLEAR_SET_FIELD(next_pkt_desc->dstDataSettings, - PKT_DSC_CKSUMSRC, PKT_DSC_CKSUMSRC_DMA); - } - break; - case XLR_SEC_CKSUM_SRC_CIPHER: - CLEAR_SET_FIELD(next_pkt_desc->dstDataSettings, - PKT_DSC_CKSUMSRC, PKT_DSC_CKSUMSRC_CIPHER); - if (multi_frag_flag) { - CLEAR_SET_FIELD(next_pkt_desc->dstDataSettings, - PKT_DSC_CKSUMSRC, PKT_DSC_CKSUMSRC_CIPHER); - } - break; - default: - XLR_SEC_CMD_DIAG("xlr_sec_setup_packet: ERR_CKSUM_SRC EXIT\n"); - return XLR_SEC_ERR_CKSUM_SRC; - } - } - pkt_desc->ckSumDstNonceHiCFBMaskLLWMask = - FIELD_VALUE(PKT_DSC_HASH_BYTE_OFF, (op->digest_offset & 0x7)) | - FIELD_VALUE(PKT_DSC_PKTLEN_BYTES, 0) | - /* NONCE_HI, PKT_DSC_LASTWORD, CFB_MASK, CKSUM_DST_ADDR */ - FIELD_VALUE(PKT_DSC_IV_OFF_HI, 0); - - if (multi_frag_flag) { - next_pkt_desc->ckSumDstNonceHiCFBMaskLLWMask = - FIELD_VALUE(PKT_DSC_HASH_BYTE_OFF, (op->digest_offset & 0x7)) | - FIELD_VALUE(PKT_DSC_PKTLEN_BYTES, 0) | - /* NONCE_HI, PKT_DSC_LASTWORD, CFB_MASK, CKSUM_DST_ADDR */ - FIELD_VALUE(PKT_DSC_IV_OFF_HI, 0); - - } - switch (op->pkt_lastword) { - case XLR_SEC_LASTWORD_128: - CLEAR_SET_FIELD(pkt_desc->ckSumDstNonceHiCFBMaskLLWMask, - PKT_DSC_LASTWORD, PKT_DSC_LASTWORD_128); - if (multi_frag_flag) { - CLEAR_SET_FIELD(next_pkt_desc->ckSumDstNonceHiCFBMaskLLWMask, - PKT_DSC_LASTWORD, PKT_DSC_LASTWORD_128); - - } - break; - case XLR_SEC_LASTWORD_96MASK: - CLEAR_SET_FIELD(pkt_desc->ckSumDstNonceHiCFBMaskLLWMask, - PKT_DSC_LASTWORD, PKT_DSC_LASTWORD_96MASK); - if (multi_frag_flag) { - CLEAR_SET_FIELD(next_pkt_desc->ckSumDstNonceHiCFBMaskLLWMask, - PKT_DSC_LASTWORD, PKT_DSC_LASTWORD_96MASK); - } - break; - case XLR_SEC_LASTWORD_64MASK: - CLEAR_SET_FIELD(pkt_desc->ckSumDstNonceHiCFBMaskLLWMask, - PKT_DSC_LASTWORD, PKT_DSC_LASTWORD_64MASK); - if (multi_frag_flag) { - CLEAR_SET_FIELD(next_pkt_desc->ckSumDstNonceHiCFBMaskLLWMask, - PKT_DSC_LASTWORD, PKT_DSC_LASTWORD_64MASK); - } - break; - case XLR_SEC_LASTWORD_32MASK: - CLEAR_SET_FIELD(pkt_desc->ckSumDstNonceHiCFBMaskLLWMask, - PKT_DSC_LASTWORD, PKT_DSC_LASTWORD_32MASK); - if (multi_frag_flag) { - CLEAR_SET_FIELD(next_pkt_desc->ckSumDstNonceHiCFBMaskLLWMask, - PKT_DSC_LASTWORD, PKT_DSC_LASTWORD_32MASK); - } - break; - default: - XLR_SEC_CMD_DIAG("xlr_sec_setup_packet: ERR_LASTWORD_MODE EXIT\n"); - return XLR_SEC_ERR_LASTWORD_MODE; - } - CLEAR_SET_FIELD(pkt_desc->ckSumDstNonceHiCFBMaskLLWMask, - PKT_DSC_CFB_MASK, op->cfb_mask); - CLEAR_SET_FIELD(pkt_desc->ckSumDstNonceHiCFBMaskLLWMask, - PKT_DSC_NONCE_HI, htonl(op->nonce) >> 24); - CLEAR_SET_FIELD(pkt_desc->authDstNonceLow, - PKT_DSC_NONCE_LOW, htonl(op->nonce) & 0xffffff); - - if (multi_frag_flag) { - CLEAR_SET_FIELD(next_pkt_desc->ckSumDstNonceHiCFBMaskLLWMask, - PKT_DSC_CFB_MASK, op->cfb_mask); - CLEAR_SET_FIELD(next_pkt_desc->ckSumDstNonceHiCFBMaskLLWMask, - PKT_DSC_NONCE_HI, htonl(op->nonce) >> 24); - CLEAR_SET_FIELD(next_pkt_desc->authDstNonceLow, - PKT_DSC_NONCE_LOW, htonl(op->nonce) & 0xffffff); - - - } - /* Auth Dest Address must be Cacheline aligned on input */ - if (vector & (XLR_SEC_VECTOR_MAC | XLR_SEC_VECTOR_HMAC | XLR_SEC_VECTOR_HMAC2 | XLR_SEC_VECTOR_GCM | XLR_SEC_VECTOR_F9)) { - pkt_desc->authDstNonceLow |= - /* NONCE_LOW */ - FIELD_VALUE(PKT_DSC_AUTH_DST_ADDR, - (uint64_t) vtophys((void *)(unsigned long)op->auth_dest)) | - FIELD_VALUE(PKT_DSC_CIPH_OFF_HI, 0); - - - if (multi_frag_flag) { - next_pkt_desc->authDstNonceLow |= - /* NONCE_LOW */ - FIELD_VALUE(PKT_DSC_AUTH_DST_ADDR, - (uint64_t) vtophys((void *)(unsigned long)desc->next_auth_dest)) | - FIELD_VALUE(PKT_DSC_CIPH_OFF_HI, 0); - - - } - } - /* CkSum Dest Address must be Cacheline aligned on input */ - if (op->cksum_type == XLR_SEC_CKSUM_TYPE_IP) { - CLEAR_SET_FIELD(pkt_desc->ckSumDstNonceHiCFBMaskLLWMask, - PKT_DSC_CKSUM_DST_ADDR, - (uint64_t) vtophys((void *)(unsigned long)op->cksum_dest)); - - if (multi_frag_flag) { - CLEAR_SET_FIELD(next_pkt_desc->ckSumDstNonceHiCFBMaskLLWMask, - PKT_DSC_CKSUM_DST_ADDR, - (uint64_t) vtophys((void *)(unsigned long)desc->next_cksum_dest)); - } - } - /* - * XLR_SEC_CMD_DIAG (" xlr_sec_setup_packet(): pkt_desc=%llx - * phys_pkt_desc=%llx \n", (unsigned long long)pkt_desc, (unsigned - * long long)virt_to_phys(pkt_desc)); (unsigned long long)pkt_desc, - * (unsigned long long)vtophys(pkt_desc)); - */ - XLR_SEC_CMD_DIAG(" xlr_sec_setup_packet(): pkt_desc=%p phys_pkt_desc=%llx \n", - pkt_desc, (unsigned long long)vtophys(pkt_desc)); - - CLEAR_SET_FIELD(*data, MSG_CMD_DATA_ADDR, ((uint64_t) vtophys(pkt_desc))); - CLEAR_SET_FIELD(*data, MSG_CMD_DATA_CTL, SEC_EOP); - CLEAR_SET_FIELD(*data, MSG_CMD_DATA_LEN, MSG_CMD_DATA_LEN_LOAD); - - XLR_SEC_CMD_DIAG("xlr_sec_setup_packet: DONE\n"); - -#ifdef RMI_SEC_DEBUG - { - printf("data desc\n"); - printf("srcLengthIVOffUseIVNext = 0x%llx\n", pkt_desc->srcLengthIVOffUseIVNext); - printf("dstDataSettings = 0x%llx\n", pkt_desc->dstDataSettings); - printf("authDstNonceLow = 0x%llx\n", pkt_desc->authDstNonceLow); - printf("ckSumDstNonceHiCFBMaskLLWMask = 0x%llx\n", pkt_desc->ckSumDstNonceHiCFBMaskLLWMask); - } - - if (multi_frag_flag) { - - printf("next data desc\n"); - printf("srcLengthIVOffUseIVNext = 0x%llx\n", next_pkt_desc->srcLengthIVOffUseIVNext); - printf("dstDataSettings = 0x%llx\n", next_pkt_desc->dstDataSettings); - printf("authDstNonceLow = 0x%llx\n", next_pkt_desc->authDstNonceLow); - printf("ckSumDstNonceHiCFBMaskLLWMask = 0x%llx\n", next_pkt_desc->ckSumDstNonceHiCFBMaskLLWMask); - } -#endif - -#ifdef SYMBOL - if (op->cipher_type == XLR_SEC_CIPHER_TYPE_ARC4) { - op->source_buf -= 0; - op->source_buf_size += 0; - op->dest_buf -= 0; - } -#endif - return XLR_SEC_ERR_NONE; -} - - -static int -identify_symkey_ctl_error(uint32_t code, xlr_sec_error_t err) -{ - int ret_val = EINVAL; - - switch (code) { - case CTL_ERR_NONE: - XLR_SEC_CMD_DIAG("XLR_SEC_SEC: CTL Error: No Error\n"); - ret_val = 0; - break; - case CTL_ERR_CIPHER_OP: - XLR_SEC_CMD_DIAG("XLR_SEC_SEC: CTL Error(CTL_ERR_CIPHER_OP) - Unknown Cipher Op \n"); - break; - case CTL_ERR_MODE: - XLR_SEC_CMD_DIAG("XLR_SEC_SEC: CTL Error(CTL_ERR_MODE) - " - "Unknown or Not Allowed Mode \n"); - break; - case CTL_ERR_CHKSUM_SRC: - XLR_SEC_CMD_DIAG("XLR_SEC_SEC: CTL Error(CTL_ERR_CHKSUM_SRC) - Unknown CkSum Src\n"); - break; - case CTL_ERR_CFB_MASK: - XLR_SEC_CMD_DIAG("XLR_SEC_SEC: CTL Error(CTL_ERR_CFB_MASK) - Forbidden CFB Mask \n"); - break; - case CTL_ERR_OP: - XLR_SEC_CMD_DIAG("XLR_SEC_SEC: CTL Error(CTL_ERR_OP) - Unknown Ctrl Op \n"); - break; - case CTL_ERR_DATA_READ: - XLR_SEC_CMD_DIAG("XLR_SEC_SEC: CTL Error(CTL_ERR_DATA_READ) - Data Read Error\n"); - break; - case CTL_ERR_DESC_CTRL: - XLR_SEC_CMD_DIAG("XLR_SEC_SEC: CTL Error(CTL_ERR_DESC_CTRL) - " - "Descriptor Ctrl Field Error \n"); - break; - case CTL_ERR_UNDEF1: - case CTL_ERR_UNDEF2: - default: - XLR_SEC_CMD_DIAG("XLR_SEC_SEC: CTL Error: UNKNOWN CODE=%d \n", code); - break; - } - return ret_val; -} - -static -int -identify_symkey_data_error(uint32_t code, xlr_sec_error_t err) -{ - int ret_val = -EINVAL; - - switch (code) { - case DATA_ERR_NONE: - XLR_SEC_CMD_DIAG("XLR_SEC_SEC: DATA Error No Error\n"); - ret_val = 0; - break; - case DATA_ERR_LEN_CIPHER: - XLR_SEC_CMD_DIAG("XLR_SEC_SEC: DATA Error() - Not Enough Data To Cipher\n"); - break; - case DATA_ERR_IV_ADDR: - XLR_SEC_CMD_DIAG("XLR_SEC_SEC: DATA Error() - Illegal IV Loacation\n"); - break; - case DATA_ERR_WD_LEN_AES: - XLR_SEC_CMD_DIAG("XLR_SEC_SEC: DATA Error() - Illegal Nb Words To AES\n"); - break; - case DATA_ERR_BYTE_COUNT: - XLR_SEC_CMD_DIAG("XLR_SEC_SEC: DATA Error() - Illegal Pad And ByteCount Spec\n"); - break; - case DATA_ERR_LEN_CKSUM: - XLR_SEC_CMD_DIAG("XLR_SEC_SEC: DATA Error() - Not Enough Data To CkSum\n"); - break; - case DATA_ERR_OP: - XLR_SEC_CMD_DIAG("XLR_SEC_SEC: DATA Error() - Unknown Data Op \n"); - break; - case DATA_ERR_READ: - XLR_SEC_CMD_DIAG("XLR_SEC_SEC: DATA Error() - Data Read Error \n"); - break; - case DATA_ERR_WRITE: - XLR_SEC_CMD_DIAG("XLR_SEC_SEC: DATA Error() - Data Write Error \n"); - break; - case DATA_ERR_UNDEF1: - default: - XLR_SEC_CMD_DIAG("XLR_SEC_SEC: DATA Error - UNKNOWN CODE=%d \n", code); - break; - } - return ret_val; -} - - -static int -xlr_sec_submit_message(symkey_desc_pt desc, uint32_t cfg_vector) -{ - xlr_sec_error_t err; - uint32_t ctl_error, data_error; - int ret_val = 0; - - XLR_SEC_CMD_DIAG("xlr_sec_submit_message: ENTER\n"); - err = XLR_SEC_ERR_NONE; - XLR_SEC_CMD_DIAG_SYM_DESC(desc, cfg_vector); - - do { - /* For now, send message and wait for response */ - err = xlr_sec_submit_op(desc); - - XLR_SEC_CMD_DIAG("xlr_sec_submit_message: err = %d \n", (uint32_t) err); - - if (err != XLR_SEC_ERR_NONE) { - ret_val = (EINVAL); - break; - } - ctl_error = desc->ctl_result; - data_error = desc->data_result; - - XLR_SEC_CMD_DIAG("xlr_sec_submit_message: ctl_error = %x data_error = %x\n", - ctl_error, data_error); - - if ((ret_val = identify_symkey_ctl_error(ctl_error, err)) == 0) - ret_val = identify_symkey_data_error(data_error, err); - - XLR_SEC_CMD_DIAG("xlr_sec_submit_message: identify error = %d \n", ret_val); - - } while (0); - - XLR_SEC_CMD_DIAG("xlr_sec_submit_message: DONE\n"); - return (ret_val); -} - - -static -xlr_sec_error_t -xlr_sec_setup_cipher(xlr_sec_io_pt op, - ControlDescriptor_pt ctl_desc, - uint32_t * vector) -{ - uint32_t aes_flag = 0; - uint32_t cipher_vector = 0; - - XLR_SEC_CMD_DIAG("xlr_sec_setup_cipher: ENTER vector = %04x\n", *vector); - - switch (op->cipher_type) { - case XLR_SEC_CIPHER_TYPE_NONE: - SET_FIELD(ctl_desc->instruction, CTL_DSC_CPHR, CTL_DSC_CPHR_BYPASS); - XLR_SEC_CMD_DIAG("xlr_sec_setup_cipher: CIPHER_TYPE_NONE EXIT\n"); - return XLR_SEC_ERR_NONE; - case XLR_SEC_CIPHER_TYPE_DES: - cipher_vector |= XLR_SEC_VECTOR_CIPHER_DES; - SET_FIELD(ctl_desc->instruction, CTL_DSC_CPHR, CTL_DSC_CPHR_DES); - break; - case XLR_SEC_CIPHER_TYPE_3DES: - cipher_vector |= XLR_SEC_VECTOR_CIPHER_3DES; - SET_FIELD(ctl_desc->instruction, CTL_DSC_CPHR, CTL_DSC_CPHR_3DES); - break; - case XLR_SEC_CIPHER_TYPE_AES128: - aes_flag = 1; - cipher_vector |= XLR_SEC_VECTOR_CIPHER_AES128; - SET_FIELD(ctl_desc->instruction, CTL_DSC_CPHR, CTL_DSC_CPHR_AES128); - break; - case XLR_SEC_CIPHER_TYPE_AES192: - aes_flag = 1; - cipher_vector |= XLR_SEC_VECTOR_CIPHER_AES192; - SET_FIELD(ctl_desc->instruction, CTL_DSC_CPHR, CTL_DSC_CPHR_AES192); - break; - case XLR_SEC_CIPHER_TYPE_AES256: - aes_flag = 1; - cipher_vector |= XLR_SEC_VECTOR_CIPHER_AES256; - SET_FIELD(ctl_desc->instruction, CTL_DSC_CPHR, CTL_DSC_CPHR_AES256); - break; - case XLR_SEC_CIPHER_TYPE_ARC4: - cipher_vector |= XLR_SEC_VECTOR_CIPHER_ARC4; - SET_FIELD(ctl_desc->instruction, CTL_DSC_CPHR, CTL_DSC_CPHR_ARC4); - SET_FIELD(ctl_desc->instruction, CTL_DSC_ARC4_KEYLEN, - op->rc4_key_len); - SET_FIELD(ctl_desc->instruction, CTL_DSC_ARC4_LOADSTATE, - op->rc4_loadstate); - SET_FIELD(ctl_desc->instruction, CTL_DSC_ARC4_SAVESTATE, - op->rc4_savestate); - if (op->rc4_loadstate || op->rc4_savestate) - cipher_vector |= XLR_SEC_VECTOR_STATE; - break; - case XLR_SEC_CIPHER_TYPE_KASUMI_F8: - aes_flag = 1; - cipher_vector |= XLR_SEC_VECTOR_CIPHER_KASUMI_F8; - SET_FIELD(ctl_desc->instruction, CTL_DSC_CPHR, CTL_DSC_CPHR_KASUMI_F8); - break; - default: - XLR_SEC_CMD_DIAG("xlr_sec_setup_cipher: ERR_CIPHER_TYPE EXIT\n"); - return XLR_SEC_ERR_CIPHER_TYPE; - } - - switch (op->cipher_mode) { - case XLR_SEC_CIPHER_MODE_ECB: - if (aes_flag == 1) - cipher_vector |= XLR_SEC_VECTOR_MODE_ECB_CBC_OFB; - else - cipher_vector |= XLR_SEC_VECTOR_MODE_ECB_CBC; - SET_FIELD(ctl_desc->instruction, CTL_DSC_MODE, CTL_DSC_MODE_ECB); - break; - case XLR_SEC_CIPHER_MODE_CBC: - if (aes_flag == 1) - cipher_vector |= XLR_SEC_VECTOR_MODE_ECB_CBC_OFB; - else - cipher_vector |= XLR_SEC_VECTOR_MODE_ECB_CBC; - SET_FIELD(ctl_desc->instruction, CTL_DSC_MODE, CTL_DSC_MODE_CBC); - break; - case XLR_SEC_CIPHER_MODE_OFB: - if (aes_flag == 0) { - XLR_SEC_CMD_DIAG("xlr_sec_setup_cipher: ERR_CIPHER_MODE EXIT\n"); - return XLR_SEC_ERR_CIPHER_MODE; - } - cipher_vector |= XLR_SEC_VECTOR_MODE_ECB_CBC_OFB; - SET_FIELD(ctl_desc->instruction, CTL_DSC_MODE, CTL_DSC_MODE_OFB); - break; - case XLR_SEC_CIPHER_MODE_CTR: - if (aes_flag == 0) { - XLR_SEC_CMD_DIAG("xlr_sec_setup_cipher: ERR_CIPHER_MODE EXIT\n"); - return XLR_SEC_ERR_CIPHER_MODE; - } - cipher_vector |= XLR_SEC_VECTOR_MODE_CTR_CFB; - SET_FIELD(ctl_desc->instruction, CTL_DSC_MODE, CTL_DSC_MODE_CTR); - break; - case XLR_SEC_CIPHER_MODE_CFB: - if (aes_flag == 0) { - XLR_SEC_CMD_DIAG("xlr_sec_setup_cipher: ERR_CIPHER_MODE EXIT\n"); - return XLR_SEC_ERR_CIPHER_MODE; - } - cipher_vector |= XLR_SEC_VECTOR_MODE_CTR_CFB; - SET_FIELD(ctl_desc->instruction, CTL_DSC_MODE, CTL_DSC_MODE_CFB); - break; - case XLR_SEC_CIPHER_MODE_F8: - if (aes_flag == 0) { - XLR_SEC_CMD_DIAG("xlr_sec_setup_cipher: ERR_CIPHER_MODE EXIT\n"); - return XLR_SEC_ERR_CIPHER_MODE; - } - cipher_vector |= XLR_SEC_VECTOR_MODE_F8; - SET_FIELD(ctl_desc->instruction, CTL_DSC_MODE, CTL_DSC_MODE_F8); - break; - default: - if (!(cipher_vector & (XLR_SEC_VECTOR_CIPHER_ARC4 | XLR_SEC_VECTOR_CIPHER_KASUMI_F8))) { - XLR_SEC_CMD_DIAG("xlr_sec_setup_cipher: ERR_CIPHER_MODE EXIT\n"); - return XLR_SEC_ERR_CIPHER_MODE; - } - } - - switch (op->cipher_init) { - case XLR_SEC_CIPHER_INIT_OK: - SET_FIELD(ctl_desc->instruction, - CTL_DSC_ICPHR, CTL_DSC_ICPHR_OKY); - break; - - case XLR_SEC_CIPHER_INIT_NK: - SET_FIELD(ctl_desc->instruction, - CTL_DSC_ICPHR, CTL_DSC_ICPHR_NKY); - break; - default: - XLR_SEC_CMD_DIAG("xlr_sec_setup_cipher: ERR_CIPHER_INIT EXIT\n"); - return XLR_SEC_ERR_CIPHER_INIT; - } - - *vector |= cipher_vector; - - XLR_SEC_CMD_DIAG("xlr_sec_setup_cipher: EXIT vector = %04x\n", *vector); - - return XLR_SEC_ERR_NONE; -} - -static -xlr_sec_error_t -xlr_sec_setup_digest(xlr_sec_io_pt op, - ControlDescriptor_pt ctl_desc, - uint32_t * vector) -{ - uint32_t hash_flag = 0; - uint32_t hmac_flag = 0; - uint32_t digest_vector = 0; - - XLR_SEC_CMD_DIAG("xlr_sec_setup_digest: ENTER vector = %04x\n", *vector); - - switch (op->digest_type) { - case XLR_SEC_DIGEST_TYPE_MD5: - digest_vector |= XLR_SEC_VECTOR_MAC; - SET_FIELD(ctl_desc->instruction, CTL_DSC_HASH, CTL_DSC_HASH_MD5); - break; - case XLR_SEC_DIGEST_TYPE_SHA1: - digest_vector |= XLR_SEC_VECTOR_MAC; - SET_FIELD(ctl_desc->instruction, CTL_DSC_HASH, CTL_DSC_HASH_SHA1); - break; - case XLR_SEC_DIGEST_TYPE_SHA256: - digest_vector |= XLR_SEC_VECTOR_MAC; - SET_FIELD(ctl_desc->instruction, CTL_DSC_HASH, CTL_DSC_HASH_SHA256); - break; - case XLR_SEC_DIGEST_TYPE_SHA384: - digest_vector |= XLR_SEC_VECTOR_MAC; - SET_FIELD(ctl_desc->instruction, CTL_DSC_HASHHI, CTL_DSC_HASH_SHA384 >> 2); - SET_FIELD(ctl_desc->instruction, CTL_DSC_HASH, CTL_DSC_HASH_SHA384); - break; - case XLR_SEC_DIGEST_TYPE_SHA512: - digest_vector |= XLR_SEC_VECTOR_MAC; - SET_FIELD(ctl_desc->instruction, CTL_DSC_HASHHI, CTL_DSC_HASH_SHA512 >> 2); - SET_FIELD(ctl_desc->instruction, CTL_DSC_HASH, CTL_DSC_HASH_SHA512); - break; - case XLR_SEC_DIGEST_TYPE_GCM: - hash_flag = 1; - digest_vector |= XLR_SEC_VECTOR_GCM; - SET_FIELD(ctl_desc->instruction, CTL_DSC_HASHHI, CTL_DSC_HASH_GCM >> 2); - SET_FIELD(ctl_desc->instruction, CTL_DSC_HASH, CTL_DSC_HASH_GCM); - break; - case XLR_SEC_DIGEST_TYPE_KASUMI_F9: - hash_flag = 1; - digest_vector |= XLR_SEC_VECTOR_F9; - SET_FIELD(ctl_desc->instruction, CTL_DSC_HASHHI, CTL_DSC_HASH_KASUMI_F9 >> 2); - SET_FIELD(ctl_desc->instruction, CTL_DSC_HASH, CTL_DSC_HASH_KASUMI_F9); - break; - case XLR_SEC_DIGEST_TYPE_HMAC_MD5: - hmac_flag = 1; - digest_vector |= XLR_SEC_VECTOR_HMAC; - SET_FIELD(ctl_desc->instruction, CTL_DSC_HASH, CTL_DSC_HASH_MD5); - break; - case XLR_SEC_DIGEST_TYPE_HMAC_SHA1: - hmac_flag = 1; - digest_vector |= XLR_SEC_VECTOR_HMAC; - SET_FIELD(ctl_desc->instruction, CTL_DSC_HASH, CTL_DSC_HASH_SHA1); - break; - case XLR_SEC_DIGEST_TYPE_HMAC_SHA256: - hmac_flag = 1; - digest_vector |= XLR_SEC_VECTOR_HMAC; - SET_FIELD(ctl_desc->instruction, CTL_DSC_HASH, CTL_DSC_HASH_SHA256); - break; - case XLR_SEC_DIGEST_TYPE_HMAC_SHA384: - hmac_flag = 1; - digest_vector |= XLR_SEC_VECTOR_HMAC2; - SET_FIELD(ctl_desc->instruction, CTL_DSC_HASHHI, CTL_DSC_HASH_SHA384 >> 2); - SET_FIELD(ctl_desc->instruction, CTL_DSC_HASH, CTL_DSC_HASH_SHA384); - break; - case XLR_SEC_DIGEST_TYPE_HMAC_SHA512: - hmac_flag = 1; - digest_vector |= XLR_SEC_VECTOR_HMAC2; - SET_FIELD(ctl_desc->instruction, CTL_DSC_HASHHI, CTL_DSC_HASH_SHA512 >> 2); - SET_FIELD(ctl_desc->instruction, CTL_DSC_HASH, CTL_DSC_HASH_SHA512); - break; - default: - return XLR_SEC_ERR_DIGEST_TYPE; - } - - if (hmac_flag == 1) { - SET_FIELD(ctl_desc->instruction, CTL_DSC_HMAC, CTL_DSC_HMAC_ON); - - } - if (hmac_flag || hash_flag) { - switch (op->digest_init) { - case XLR_SEC_DIGEST_INIT_OLDKEY: - SET_FIELD(ctl_desc->instruction, CTL_DSC_IHASH, CTL_DSC_IHASH_OLD); - break; - case XLR_SEC_DIGEST_INIT_NEWKEY: - SET_FIELD(ctl_desc->instruction, CTL_DSC_IHASH, CTL_DSC_IHASH_NEW); - break; - default: - return XLR_SEC_ERR_DIGEST_INIT; - } - } /* hmac_flag */ - *vector |= digest_vector; - - XLR_SEC_CMD_DIAG("xlr_sec_setup_digest: EXIT vector = %04x\n", *vector); - return XLR_SEC_ERR_NONE; -} - -static -xlr_sec_error_t -xlr_sec_setup_cksum(xlr_sec_io_pt op, - ControlDescriptor_pt ctl_desc) -{ - switch (op->cksum_type) { - case XLR_SEC_CKSUM_TYPE_NOP: - SET_FIELD(ctl_desc->instruction, CTL_DSC_CKSUM, CTL_DSC_CKSUM_NOP); - return XLR_SEC_ERR_NONE; - case XLR_SEC_CKSUM_TYPE_IP: - SET_FIELD(ctl_desc->instruction, CTL_DSC_CKSUM, CTL_DSC_CKSUM_IP); - break; - default: - return XLR_SEC_ERR_CKSUM_TYPE; - } - - return XLR_SEC_ERR_NONE; -} - - -static -xlr_sec_error_t -xlr_sec_control_setup(xlr_sec_io_pt op, - unsigned int flags, - uint64_t * control, - ControlDescriptor_pt ctl_desc, - xlr_sec_drv_user_t * user, - uint32_t vector) -{ - uint64_t *hmac_key = NULL; - uint64_t *cipher_key = NULL; - uint64_t *cipher_state = NULL; - uint32_t ctl_size = 0; - uint64_t ctl_addr = 0; - uint32_t cipher_keylen = 0; - uint32_t hmac_keylen = 0; - uint32_t ctl_len; - -#ifdef SYM_DEBUG - XLR_SEC_CMD_DIAG(" ENTER vector = %04x\n", vector); -#endif - - switch (vector) { - case XLR_SEC_VECTOR_MAC: - XLR_SEC_CMD_DIAG(" XLR_SEC_VECTOR_MAC \n"); - ctl_size = sizeof(HMAC_t); - break; - case XLR_SEC_VECTOR_HMAC: - XLR_SEC_CMD_DIAG("XLR_SEC_VECTOR_HMAC \n"); - hmac_key = &ctl_desc->cipherHashInfo.infoHMAC.hmacKey0; - hmac_keylen = sizeof(HMAC_t); - ctl_size = sizeof(HMAC_t); - break; - case XLR_SEC_VECTOR_CIPHER_ARC4: - XLR_SEC_CMD_DIAG("XLR_SEC_VECTOR_CIPHER_ARC4\n"); - cipher_key = &ctl_desc->cipherHashInfo.infoARC4.cipherKey0; - cipher_keylen = op->rc4_key_len; - ctl_size = sizeof(ARC4_t); - break; - case XLR_SEC_VECTOR_CIPHER_ARC4__HMAC: - XLR_SEC_CMD_DIAG("XLR_SEC_VECTOR_CIPHER_ARC4__HMAC\n"); - cipher_key = &ctl_desc->cipherHashInfo.infoARC4HMAC.cipherKey0; - hmac_key = &ctl_desc->cipherHashInfo.infoARC4HMAC.hmacKey0; - cipher_keylen = op->rc4_key_len; - hmac_keylen = sizeof(HMAC_t); - ctl_size = sizeof(ARC4HMAC_t); - break; - case XLR_SEC_VECTOR_CIPHER_ARC4__STATE: - XLR_SEC_CMD_DIAG("XLR_SEC_VECTOR_CIPHER_ARC4__STATE\n"); - cipher_key = &ctl_desc->cipherHashInfo.infoARC4State.cipherKey0; - cipher_state = - &ctl_desc->cipherHashInfo.infoARC4State.Arc4SboxData0; - cipher_keylen = op->rc4_key_len; - ctl_size = sizeof(ARC4State_t); - break; - case XLR_SEC_VECTOR_CIPHER_ARC4__HMAC__STATE: - XLR_SEC_CMD_DIAG("XLR_SEC_VECTOR_CIPHER_ARC4__HMAC__STATE\n"); - cipher_key = &ctl_desc->cipherHashInfo.infoARC4StateHMAC.cipherKey0; - cipher_state = - &ctl_desc->cipherHashInfo.infoARC4StateHMAC.Arc4SboxData0; - hmac_key = &ctl_desc->cipherHashInfo.infoARC4StateHMAC.hmacKey0; - cipher_keylen = op->rc4_key_len; - hmac_keylen = sizeof(HMAC_t); - ctl_size = sizeof(ARC4StateHMAC_t); - break; - case XLR_SEC_VECTOR_CIPHER_KASUMI_F8: - XLR_SEC_CMD_DIAG("XLR_SEC_VECTOR_CIPHER_KASUMI_F8\n"); - cipher_key = &ctl_desc->cipherHashInfo.infoKASUMIF8.cipherKey0; - cipher_keylen = XLR_SEC_KASUMI_F8_KEY_LENGTH; - ctl_size = sizeof(KASUMIF8_t); - break; - case XLR_SEC_VECTOR_CIPHER_KASUMI_F8__HMAC: - XLR_SEC_CMD_DIAG("XLR_SEC_VECTOR_CIPHER_KASUMI_F8__HMAC\n"); - cipher_key = &ctl_desc->cipherHashInfo.infoKASUMIF8HMAC.cipherKey0; - cipher_keylen = XLR_SEC_KASUMI_F8_KEY_LENGTH; - hmac_key = &ctl_desc->cipherHashInfo.infoKASUMIF8HMAC.hmacKey0; - hmac_keylen = sizeof(HMAC_t); - ctl_size = sizeof(KASUMIF8HMAC_t); - break; - case XLR_SEC_VECTOR_CIPHER_KASUMI_F8__HMAC2: - XLR_SEC_CMD_DIAG("XLR_SEC_VECTOR_CIPHER_KASUMI_F8__HMAC2\n"); - cipher_key = &ctl_desc->cipherHashInfo.infoKASUMIF8HMAC2.cipherKey0; - cipher_keylen = XLR_SEC_KASUMI_F8_KEY_LENGTH; - hmac_key = &ctl_desc->cipherHashInfo.infoKASUMIF8HMAC2.hmacKey0; - hmac_keylen = sizeof(HMAC2_t); - ctl_size = sizeof(KASUMIF8HMAC2_t); - break; - case XLR_SEC_VECTOR_CIPHER_KASUMI_F8__GCM: - XLR_SEC_CMD_DIAG("XLR_SEC_VECTOR_CIPHER_KASUMI_F8__GCM\n"); - cipher_key = &ctl_desc->cipherHashInfo.infoKASUMIF8GCM.cipherKey0; - cipher_keylen = XLR_SEC_KASUMI_F8_KEY_LENGTH; - hmac_key = &ctl_desc->cipherHashInfo.infoKASUMIF8GCM.GCMH0; - hmac_keylen = sizeof(GCM_t); - ctl_size = sizeof(KASUMIF8GCM_t); - break; - case XLR_SEC_VECTOR_CIPHER_KASUMI_F8__F9: - XLR_SEC_CMD_DIAG("XLR_SEC_VECTOR_CIPHER_KASUMI_F8__F9\n"); - cipher_key = &ctl_desc->cipherHashInfo.infoKASUMIF8F9.cipherKey0; - cipher_keylen = XLR_SEC_KASUMI_F8_KEY_LENGTH; - hmac_key = &ctl_desc->cipherHashInfo.infoKASUMIF8F9.authKey0; - hmac_keylen = sizeof(F9_t); - ctl_size = sizeof(KASUMIF8F9_t); - break; - case XLR_SEC_VECTOR__CIPHER_DES__HMAC__MODE_ECB_CBC: - XLR_SEC_CMD_DIAG(" XLR_SEC_VECTOR__CIPHER_DES__HMAC__MODE_ECB_CBC \n"); - cipher_key = &ctl_desc->cipherHashInfo.infoDESHMAC.cipherKey0; - hmac_key = &ctl_desc->cipherHashInfo.infoDESHMAC.hmacKey0; - hmac_keylen = sizeof(HMAC_t); - cipher_keylen = XLR_SEC_DES_KEY_LENGTH; - ctl_size = sizeof(DESHMAC_t); - break; - case XLR_SEC_VECTOR__CIPHER_DES__MODE_ECB_CBC: - XLR_SEC_CMD_DIAG("XLR_SEC_VECTOR__CIPHER_DES__MODE_ECB_CBC \n"); - cipher_key = &ctl_desc->cipherHashInfo.infoDES.cipherKey0; - cipher_keylen = XLR_SEC_DES_KEY_LENGTH; - ctl_size = sizeof(DES_t); - break; - case XLR_SEC_VECTOR__CIPHER_3DES__HMAC__MODE_ECB_CBC: - XLR_SEC_CMD_DIAG("XLR_SEC_VECTOR__CIPHER_3DES__HMAC__MODE_ECB_CBC \n"); - cipher_key = &ctl_desc->cipherHashInfo.info3DESHMAC.cipherKey0; - hmac_key = &ctl_desc->cipherHashInfo.info3DESHMAC.hmacKey0; - cipher_keylen = XLR_SEC_3DES_KEY_LENGTH; - hmac_keylen = sizeof(HMAC_t); - ctl_size = sizeof(DES3HMAC_t); - break; - case XLR_SEC_VECTOR__CIPHER_3DES__MODE_ECB_CBC: - XLR_SEC_CMD_DIAG("XLR_SEC_VECTOR__CIPHER_3DES__MODE_ECB_CBC \n"); - cipher_key = &ctl_desc->cipherHashInfo.info3DES.cipherKey0; - cipher_keylen = XLR_SEC_3DES_KEY_LENGTH; - ctl_size = sizeof(DES3_t); - break; - case XLR_SEC_VECTOR__CIPHER_AES128__HMAC__MODE_CTR_CFB: - XLR_SEC_CMD_DIAG("XLR_SEC_VECTOR__CIPHER_AES128__HMAC__MODE_CTR_CFB \n"); - cipher_key = &ctl_desc->cipherHashInfo.infoAES128HMAC.cipherKey0; - hmac_key = &ctl_desc->cipherHashInfo.infoAES128HMAC.hmacKey0; - cipher_keylen = XLR_SEC_AES128_KEY_LENGTH; - hmac_keylen = sizeof(HMAC_t); - ctl_size = sizeof(AES128HMAC_t); - break; - case XLR_SEC_VECTOR__CIPHER_AES128__MODE_CTR_CFB: - XLR_SEC_CMD_DIAG("XLR_SEC_VECTOR__CIPHER_AES128__MODE_CTR_CFB \n"); - cipher_key = &ctl_desc->cipherHashInfo.infoAES128.cipherKey0; - cipher_keylen = XLR_SEC_AES128_KEY_LENGTH; - ctl_size = sizeof(AES128_t); - break; - case XLR_SEC_VECTOR__CIPHER_AES128__HMAC__MODE_ECB_CBC_OFB: - XLR_SEC_CMD_DIAG(" XLR_SEC_VECTOR__CIPHER_AES128__HMAC__MODE_ECB_CBC_OFB \n"); - cipher_key = &ctl_desc->cipherHashInfo.infoAES128HMAC.cipherKey0; - hmac_key = &ctl_desc->cipherHashInfo.infoAES128HMAC.hmacKey0; - cipher_keylen = XLR_SEC_AES128_KEY_LENGTH; - hmac_keylen = sizeof(HMAC_t); - ctl_size = sizeof(AES128HMAC_t); - break; - case XLR_SEC_VECTOR__CIPHER_AES128__MODE_ECB_CBC_OFB: - XLR_SEC_CMD_DIAG("XLR_SEC_VECTOR__CIPHER_AES128__MODE_ECB_CBC_OFB \n"); - cipher_key = &ctl_desc->cipherHashInfo.infoAES128.cipherKey0; - cipher_keylen = XLR_SEC_AES128_KEY_LENGTH; - ctl_size = sizeof(AES128_t); - break; - case XLR_SEC_VECTOR__CIPHER_AES128__HMAC__MODE_F8: - XLR_SEC_CMD_DIAG("XLR_SEC_VECTOR__CIPHER_AES128__HMAC__MODE_F8 \n"); - cipher_key = &ctl_desc->cipherHashInfo.infoAES128F8HMAC.cipherKey0; - hmac_key = &ctl_desc->cipherHashInfo.infoAES128F8HMAC.hmacKey0; - cipher_keylen = XLR_SEC_AES128F8_KEY_LENGTH; - hmac_keylen = sizeof(HMAC_t); - ctl_size = sizeof(AES128F8HMAC_t); - break; - case XLR_SEC_VECTOR__CIPHER_AES128__MODE_F8: - XLR_SEC_CMD_DIAG("XLR_SEC_VECTOR__CIPHER_AES128__MODE_F8 \n"); - cipher_key = &ctl_desc->cipherHashInfo.infoAES128F8.cipherKey0; - cipher_keylen = XLR_SEC_AES128F8_KEY_LENGTH; - ctl_size = sizeof(AES128F8_t); - break; - case XLR_SEC_VECTOR__CIPHER_AES192__HMAC__MODE_CTR_CFB: - XLR_SEC_CMD_DIAG("XLR_SEC_VECTOR__CIPHER_AES192__HMAC__MODE_CTR_CFB \n"); - cipher_key = &ctl_desc->cipherHashInfo.infoAES192HMAC.cipherKey0; - hmac_key = &ctl_desc->cipherHashInfo.infoAES192HMAC.hmacKey0; - cipher_keylen = XLR_SEC_AES192_KEY_LENGTH; - hmac_keylen = sizeof(HMAC_t); - ctl_size = sizeof(AES192HMAC_t); - break; - case XLR_SEC_VECTOR__CIPHER_AES192__MODE_CTR_CFB: - XLR_SEC_CMD_DIAG("XLR_SEC_VECTOR__CIPHER_AES192__MODE_CTR_CFB \n"); - cipher_key = &ctl_desc->cipherHashInfo.infoAES192.cipherKey0; - cipher_keylen = XLR_SEC_AES192_KEY_LENGTH; - ctl_size = sizeof(AES192_t); - break; - case XLR_SEC_VECTOR__CIPHER_AES192__HMAC__MODE_ECB_CBC_OFB: - XLR_SEC_CMD_DIAG("XLR_SEC_VECTOR__CIPHER_AES192__HMAC__MODE_ECB_CBC_OFB \n"); - cipher_key = &ctl_desc->cipherHashInfo.infoAES192HMAC.cipherKey0; - hmac_key = &ctl_desc->cipherHashInfo.infoAES192HMAC.hmacKey0; - cipher_keylen = XLR_SEC_AES192_KEY_LENGTH; - hmac_keylen = sizeof(HMAC_t); - ctl_size = sizeof(AES192HMAC_t); - break; - case XLR_SEC_VECTOR__CIPHER_AES192__MODE_ECB_CBC_OFB: - XLR_SEC_CMD_DIAG("XLR_SEC_VECTOR__CIPHER_AES192__MODE_ECB_CBC_OFB \n"); - cipher_key = &ctl_desc->cipherHashInfo.infoAES192.cipherKey0; - cipher_keylen = XLR_SEC_AES192_KEY_LENGTH; - ctl_size = sizeof(AES192_t); - break; - case XLR_SEC_VECTOR__CIPHER_AES192__HMAC__MODE_F8: - XLR_SEC_CMD_DIAG("XLR_SEC_VECTOR__CIPHER_AES192__HMAC__MODE_F8 \n"); - cipher_key = &ctl_desc->cipherHashInfo.infoAES192F8HMAC.cipherKey0; - hmac_key = &ctl_desc->cipherHashInfo.infoAES192F8HMAC.hmacKey0; - cipher_keylen = XLR_SEC_AES192F8_KEY_LENGTH; - hmac_keylen = sizeof(HMAC_t); - ctl_size = sizeof(AES192F8HMAC_t); - break; - case XLR_SEC_VECTOR__CIPHER_AES192__MODE_F8: - XLR_SEC_CMD_DIAG("XLR_SEC_VECTOR__CIPHER_AES192__MODE_F8 \n"); - cipher_key = &ctl_desc->cipherHashInfo.infoAES192F8.cipherKey0; - cipher_keylen = XLR_SEC_AES192F8_KEY_LENGTH; - ctl_size = sizeof(AES192F8_t); - break; - - case XLR_SEC_VECTOR__CIPHER_AES256__HMAC__MODE_CTR_CFB: - XLR_SEC_CMD_DIAG("XLR_SEC_VECTOR__CIPHER_AES256__HMAC__MODE_CTR_CFB \n"); - cipher_key = &ctl_desc->cipherHashInfo.infoAES256HMAC.cipherKey0; - hmac_key = &ctl_desc->cipherHashInfo.infoAES256HMAC.hmacKey0; - cipher_keylen = XLR_SEC_AES256_KEY_LENGTH; - hmac_keylen = sizeof(HMAC_t); - ctl_size = sizeof(AES256HMAC_t); - break; - case XLR_SEC_VECTOR__CIPHER_AES256__MODE_CTR_CFB: - XLR_SEC_CMD_DIAG("XLR_SEC_VECTOR__CIPHER_AES256__MODE_CTR_CFB \n"); - cipher_key = &ctl_desc->cipherHashInfo.infoAES256.cipherKey0; - cipher_keylen = XLR_SEC_AES256_KEY_LENGTH; - ctl_size = sizeof(AES256_t); - break; - case XLR_SEC_VECTOR__CIPHER_AES256__HMAC__MODE_ECB_CBC_OFB: - XLR_SEC_CMD_DIAG("XLR_SEC_VECTOR__CIPHER_AES256__HMAC__MODE_ECB_CBC_OFB \n"); - cipher_key = &ctl_desc->cipherHashInfo.infoAES256HMAC.cipherKey0; - hmac_key = &ctl_desc->cipherHashInfo.infoAES256HMAC.hmacKey0; - cipher_keylen = XLR_SEC_AES256_KEY_LENGTH; - hmac_keylen = sizeof(HMAC_t); - ctl_size = sizeof(AES256HMAC_t); - break; - case XLR_SEC_VECTOR__CIPHER_AES256__MODE_ECB_CBC_OFB: - XLR_SEC_CMD_DIAG("XLR_SEC_VECTOR__CIPHER_AES256__MODE_ECB_CBC_OFB \n"); - cipher_key = &ctl_desc->cipherHashInfo.infoAES256.cipherKey0; - cipher_keylen = XLR_SEC_AES256_KEY_LENGTH; - ctl_size = sizeof(AES256_t); - break; - case XLR_SEC_VECTOR__CIPHER_AES256__HMAC__MODE_F8: - XLR_SEC_CMD_DIAG("XLR_SEC_VECTOR__CIPHER_AES256__HMAC__MODE_F8 \n"); - cipher_key = &ctl_desc->cipherHashInfo.infoAES256F8HMAC.cipherKey0; - hmac_key = &ctl_desc->cipherHashInfo.infoAES256F8HMAC.hmacKey0; - cipher_keylen = XLR_SEC_AES256F8_KEY_LENGTH; - hmac_keylen = sizeof(HMAC_t); - ctl_size = sizeof(AES256F8HMAC_t); - break; - case XLR_SEC_VECTOR__CIPHER_AES256__MODE_F8: - XLR_SEC_CMD_DIAG("XLR_SEC_VECTOR__CIPHER_AES256__MODE_F8 \n"); - cipher_key = &ctl_desc->cipherHashInfo.infoAES256F8.cipherKey0; - cipher_keylen = XLR_SEC_AES256F8_KEY_LENGTH; - ctl_size = sizeof(AES256F8_t); - break; - case XLR_SEC_VECTOR_HMAC2: - XLR_SEC_CMD_DIAG("XLR_SEC_VECTOR_HMAC2 \n"); - hmac_key = &ctl_desc->cipherHashInfo.infoHMAC2.hmacKey0; - hmac_keylen = sizeof(HMAC2_t); - ctl_size = sizeof(HMAC2_t); - break; - case XLR_SEC_VECTOR_CIPHER_ARC4__HMAC2: - XLR_SEC_CMD_DIAG("XLR_SEC_VECTOR_CIPHER_ARC4__HMAC2\n"); - cipher_key = &ctl_desc->cipherHashInfo.infoARC4HMAC2.cipherKey0; - hmac_key = &ctl_desc->cipherHashInfo.infoARC4HMAC2.hmacKey0; - cipher_keylen = op->rc4_key_len; - hmac_keylen = sizeof(HMAC2_t); - ctl_size = sizeof(ARC4HMAC2_t); - break; - case XLR_SEC_VECTOR_CIPHER_ARC4__HMAC2__STATE: - XLR_SEC_CMD_DIAG("XLR_SEC_VECTOR_CIPHER_ARC4__HMAC2__STATE\n"); - cipher_key = &ctl_desc->cipherHashInfo.infoARC4StateHMAC2.cipherKey0; - cipher_state = - &ctl_desc->cipherHashInfo.infoARC4StateHMAC2.Arc4SboxData0; - hmac_key = &ctl_desc->cipherHashInfo.infoARC4StateHMAC2.hmacKey0; - cipher_keylen = op->rc4_key_len; - hmac_keylen = sizeof(HMAC2_t); - ctl_size = sizeof(ARC4StateHMAC2_t); - break; - case XLR_SEC_VECTOR__CIPHER_DES__HMAC2__MODE_ECB_CBC: - XLR_SEC_CMD_DIAG(" XLR_SEC_VECTOR__CIPHER_DES__HMAC2__MODE_ECB_CBC \n"); - cipher_key = &ctl_desc->cipherHashInfo.infoDESHMAC2.cipherKey0; - hmac_key = &ctl_desc->cipherHashInfo.infoDESHMAC2.hmacKey0; - hmac_keylen = sizeof(HMAC2_t); - cipher_keylen = XLR_SEC_DES_KEY_LENGTH; - ctl_size = sizeof(DESHMAC2_t); - break; - case XLR_SEC_VECTOR__CIPHER_3DES__HMAC2__MODE_ECB_CBC: - XLR_SEC_CMD_DIAG("XLR_SEC_VECTOR__CIPHER_3DES__HMAC2__MODE_ECB_CBC \n"); - cipher_key = &ctl_desc->cipherHashInfo.info3DESHMAC2.cipherKey0; - hmac_key = &ctl_desc->cipherHashInfo.info3DESHMAC2.hmacKey0; - cipher_keylen = XLR_SEC_3DES_KEY_LENGTH; - hmac_keylen = sizeof(HMAC2_t); - ctl_size = sizeof(DES3HMAC2_t); - break; - case XLR_SEC_VECTOR__CIPHER_AES128__HMAC2__MODE_CTR_CFB: - XLR_SEC_CMD_DIAG("XLR_SEC_VECTOR__CIPHER_AES128__HMAC2__MODE_CTR_CFB \n"); - cipher_key = &ctl_desc->cipherHashInfo.infoAES128HMAC2.cipherKey0; - hmac_key = &ctl_desc->cipherHashInfo.infoAES128HMAC2.hmacKey0; - cipher_keylen = XLR_SEC_AES128_KEY_LENGTH; - hmac_keylen = sizeof(HMAC2_t); - ctl_size = sizeof(AES128HMAC2_t); - break; - case XLR_SEC_VECTOR__CIPHER_AES128__HMAC2__MODE_ECB_CBC_OFB: - XLR_SEC_CMD_DIAG(" XLR_SEC_VECTOR__CIPHER_AES128__HMAC2__MODE_ECB_CBC_OFB \n"); - cipher_key = &ctl_desc->cipherHashInfo.infoAES128HMAC2.cipherKey0; - hmac_key = &ctl_desc->cipherHashInfo.infoAES128HMAC2.hmacKey0; - cipher_keylen = XLR_SEC_AES128_KEY_LENGTH; - hmac_keylen = sizeof(HMAC2_t); - ctl_size = sizeof(AES128HMAC2_t); - break; - case XLR_SEC_VECTOR__CIPHER_AES128__HMAC2__MODE_F8: - XLR_SEC_CMD_DIAG("XLR_SEC_VECTOR__CIPHER_AES128__HMAC2__MODE_F8 \n"); - cipher_key = &ctl_desc->cipherHashInfo.infoAES128F8HMAC2.cipherKey0; - hmac_key = &ctl_desc->cipherHashInfo.infoAES128F8HMAC2.hmacKey0; - cipher_keylen = XLR_SEC_AES128F8_KEY_LENGTH; - hmac_keylen = sizeof(HMAC2_t); - ctl_size = sizeof(AES128F8HMAC2_t); - break; - case XLR_SEC_VECTOR__CIPHER_AES192__HMAC2__MODE_CTR_CFB: - XLR_SEC_CMD_DIAG("XLR_SEC_VECTOR__CIPHER_AES192__HMAC2__MODE_CTR_CFB \n"); - cipher_key = &ctl_desc->cipherHashInfo.infoAES192HMAC2.cipherKey0; - hmac_key = &ctl_desc->cipherHashInfo.infoAES192HMAC2.hmacKey0; - cipher_keylen = XLR_SEC_AES192_KEY_LENGTH; - hmac_keylen = sizeof(HMAC2_t); - ctl_size = sizeof(AES192HMAC2_t); - break; - case XLR_SEC_VECTOR__CIPHER_AES192__HMAC2__MODE_ECB_CBC_OFB: - XLR_SEC_CMD_DIAG("XLR_SEC_VECTOR__CIPHER_AES192__HMAC2__MODE_ECB_CBC_OFB \n"); - cipher_key = &ctl_desc->cipherHashInfo.infoAES192HMAC2.cipherKey0; - hmac_key = &ctl_desc->cipherHashInfo.infoAES192HMAC2.hmacKey0; - cipher_keylen = XLR_SEC_AES192_KEY_LENGTH; - hmac_keylen = sizeof(HMAC2_t); - ctl_size = sizeof(AES192HMAC2_t); - break; - case XLR_SEC_VECTOR__CIPHER_AES192__HMAC2__MODE_F8: - XLR_SEC_CMD_DIAG("XLR_SEC_VECTOR__CIPHER_AES192__HMAC2__MODE_F8 \n"); - cipher_key = &ctl_desc->cipherHashInfo.infoAES192F8HMAC2.cipherKey0; - hmac_key = &ctl_desc->cipherHashInfo.infoAES192F8HMAC2.hmacKey0; - cipher_keylen = XLR_SEC_AES192F8_KEY_LENGTH; - hmac_keylen = sizeof(HMAC2_t); - ctl_size = sizeof(AES192F8HMAC2_t); - break; - case XLR_SEC_VECTOR__CIPHER_AES256__HMAC2__MODE_CTR_CFB: - XLR_SEC_CMD_DIAG("XLR_SEC_VECTOR__CIPHER_AES256__HMAC2__MODE_CTR_CFB \n"); - cipher_key = &ctl_desc->cipherHashInfo.infoAES256HMAC2.cipherKey0; - hmac_key = &ctl_desc->cipherHashInfo.infoAES256HMAC2.hmacKey0; - cipher_keylen = XLR_SEC_AES256_KEY_LENGTH; - hmac_keylen = sizeof(HMAC2_t); - ctl_size = sizeof(AES256HMAC2_t); - break; - case XLR_SEC_VECTOR__CIPHER_AES256__HMAC2__MODE_ECB_CBC_OFB: - XLR_SEC_CMD_DIAG("XLR_SEC_VECTOR__CIPHER_AES256__HMAC2__MODE_ECB_CBC_OFB \n"); - cipher_key = &ctl_desc->cipherHashInfo.infoAES256HMAC2.cipherKey0; - hmac_key = &ctl_desc->cipherHashInfo.infoAES256HMAC2.hmacKey0; - cipher_keylen = XLR_SEC_AES256_KEY_LENGTH; - hmac_keylen = sizeof(HMAC2_t); - ctl_size = sizeof(AES256HMAC2_t); - break; - case XLR_SEC_VECTOR__CIPHER_AES256__HMAC2__MODE_F8: - XLR_SEC_CMD_DIAG("XLR_SEC_VECTOR__CIPHER_AES256__HMAC2__MODE_F8 \n"); - cipher_key = &ctl_desc->cipherHashInfo.infoAES256F8HMAC2.cipherKey0; - hmac_key = &ctl_desc->cipherHashInfo.infoAES256F8HMAC2.hmacKey0; - cipher_keylen = XLR_SEC_AES256F8_KEY_LENGTH; - hmac_keylen = sizeof(HMAC2_t); - ctl_size = sizeof(AES256F8HMAC2_t); - break; - case XLR_SEC_VECTOR_GCM: - XLR_SEC_CMD_DIAG("XLR_SEC_VECTOR_GCM \n"); - hmac_key = &ctl_desc->cipherHashInfo.infoGCM.GCMH0; - hmac_keylen = sizeof(GCM_t); - ctl_size = sizeof(GCM_t); - break; - case XLR_SEC_VECTOR_CIPHER_ARC4__GCM: - XLR_SEC_CMD_DIAG("XLR_SEC_VECTOR_CIPHER_ARC4__GCM\n"); - cipher_key = &ctl_desc->cipherHashInfo.infoARC4GCM.cipherKey0; - hmac_key = &ctl_desc->cipherHashInfo.infoARC4GCM.GCMH0; - cipher_keylen = op->rc4_key_len; - hmac_keylen = sizeof(GCM_t); - ctl_size = sizeof(ARC4GCM_t); - break; - case XLR_SEC_VECTOR_CIPHER_ARC4__GCM__STATE: - XLR_SEC_CMD_DIAG("XLR_SEC_VECTOR_CIPHER_ARC4__GCM__STATE\n"); - cipher_key = &ctl_desc->cipherHashInfo.infoARC4StateGCM.cipherKey0; - cipher_state = - &ctl_desc->cipherHashInfo.infoARC4StateGCM.Arc4SboxData0; - hmac_key = &ctl_desc->cipherHashInfo.infoARC4StateGCM.GCMH0; - cipher_keylen = op->rc4_key_len; - hmac_keylen = sizeof(GCM_t); - ctl_size = sizeof(ARC4StateGCM_t); - break; - case XLR_SEC_VECTOR__CIPHER_DES__GCM__MODE_ECB_CBC: - XLR_SEC_CMD_DIAG(" XLR_SEC_VECTOR__CIPHER_DES__GCM__MODE_ECB_CBC \n"); - cipher_key = &ctl_desc->cipherHashInfo.infoDESGCM.cipherKey0; - hmac_key = &ctl_desc->cipherHashInfo.infoDESGCM.GCMH0; - hmac_keylen = sizeof(GCM_t); - cipher_keylen = XLR_SEC_DES_KEY_LENGTH; - ctl_size = sizeof(DESGCM_t); - break; - case XLR_SEC_VECTOR__CIPHER_3DES__GCM__MODE_ECB_CBC: - XLR_SEC_CMD_DIAG("XLR_SEC_VECTOR__CIPHER_3DES__GCM__MODE_ECB_CBC \n"); - cipher_key = &ctl_desc->cipherHashInfo.info3DESGCM.cipherKey0; - hmac_key = &ctl_desc->cipherHashInfo.info3DESGCM.GCMH0; - cipher_keylen = XLR_SEC_3DES_KEY_LENGTH; - hmac_keylen = sizeof(GCM_t); - ctl_size = sizeof(DES3GCM_t); - break; - case XLR_SEC_VECTOR__CIPHER_AES128__GCM__MODE_CTR_CFB: - XLR_SEC_CMD_DIAG("XLR_SEC_VECTOR__CIPHER_AES128__GCM__MODE_CTR_CFB \n"); - cipher_key = &ctl_desc->cipherHashInfo.infoAES128GCM.cipherKey0; - hmac_key = &ctl_desc->cipherHashInfo.infoAES128GCM.GCMH0; - cipher_keylen = XLR_SEC_AES128_KEY_LENGTH; - hmac_keylen = sizeof(GCM_t); - ctl_size = sizeof(AES128GCM_t); - break; - case XLR_SEC_VECTOR__CIPHER_AES128__GCM__MODE_ECB_CBC_OFB: - XLR_SEC_CMD_DIAG(" XLR_SEC_VECTOR__CIPHER_AES128__GCM__MODE_ECB_CBC_OFB \n"); - cipher_key = &ctl_desc->cipherHashInfo.infoAES128GCM.cipherKey0; - hmac_key = &ctl_desc->cipherHashInfo.infoAES128GCM.GCMH0; - cipher_keylen = XLR_SEC_AES128_KEY_LENGTH; - hmac_keylen = sizeof(GCM_t); - ctl_size = sizeof(AES128GCM_t); - break; - case XLR_SEC_VECTOR__CIPHER_AES128__GCM__MODE_F8: - XLR_SEC_CMD_DIAG("XLR_SEC_VECTOR__CIPHER_AES128__GCM__MODE_F8 \n"); - cipher_key = &ctl_desc->cipherHashInfo.infoAES128F8GCM.cipherKey0; - hmac_key = &ctl_desc->cipherHashInfo.infoAES128F8GCM.GCMH0; - cipher_keylen = XLR_SEC_AES128F8_KEY_LENGTH; - hmac_keylen = sizeof(GCM_t); - ctl_size = sizeof(AES128F8GCM_t); - break; - case XLR_SEC_VECTOR__CIPHER_AES192__GCM__MODE_CTR_CFB: - XLR_SEC_CMD_DIAG("XLR_SEC_VECTOR__CIPHER_AES192__GCM__MODE_CTR_CFB \n"); - cipher_key = &ctl_desc->cipherHashInfo.infoAES192GCM.cipherKey0; - hmac_key = &ctl_desc->cipherHashInfo.infoAES192GCM.GCMH0; - cipher_keylen = XLR_SEC_AES192_KEY_LENGTH; - hmac_keylen = sizeof(GCM_t); - ctl_size = sizeof(AES192GCM_t); - break; - case XLR_SEC_VECTOR__CIPHER_AES192__GCM__MODE_ECB_CBC_OFB: - XLR_SEC_CMD_DIAG("XLR_SEC_VECTOR__CIPHER_AES192__GCM__MODE_ECB_CBC_OFB \n"); - cipher_key = &ctl_desc->cipherHashInfo.infoAES192GCM.cipherKey0; - hmac_key = &ctl_desc->cipherHashInfo.infoAES192GCM.GCMH0; - cipher_keylen = XLR_SEC_AES192_KEY_LENGTH; - hmac_keylen = sizeof(GCM_t); - ctl_size = sizeof(AES192GCM_t); - break; - case XLR_SEC_VECTOR__CIPHER_AES192__GCM__MODE_F8: - XLR_SEC_CMD_DIAG("XLR_SEC_VECTOR__CIPHER_AES192__GCM__MODE_F8 \n"); - cipher_key = &ctl_desc->cipherHashInfo.infoAES192F8GCM.cipherKey0; - hmac_key = &ctl_desc->cipherHashInfo.infoAES192F8GCM.GCMH0; - cipher_keylen = XLR_SEC_AES192F8_KEY_LENGTH; - hmac_keylen = sizeof(GCM_t); - ctl_size = sizeof(AES192F8GCM_t); - break; - case XLR_SEC_VECTOR__CIPHER_AES256__GCM__MODE_CTR_CFB: - XLR_SEC_CMD_DIAG("XLR_SEC_VECTOR__CIPHER_AES256__GCM__MODE_CTR_CFB \n"); - cipher_key = &ctl_desc->cipherHashInfo.infoAES256GCM.cipherKey0; - hmac_key = &ctl_desc->cipherHashInfo.infoAES256GCM.GCMH0; - cipher_keylen = XLR_SEC_AES256_KEY_LENGTH; - hmac_keylen = sizeof(GCM_t); - ctl_size = sizeof(AES256GCM_t); - break; - case XLR_SEC_VECTOR__CIPHER_AES256__GCM__MODE_ECB_CBC_OFB: - XLR_SEC_CMD_DIAG("XLR_SEC_VECTOR__CIPHER_AES256__GCM__MODE_ECB_CBC_OFB \n"); - cipher_key = &ctl_desc->cipherHashInfo.infoAES256GCM.cipherKey0; - hmac_key = &ctl_desc->cipherHashInfo.infoAES256GCM.GCMH0; - cipher_keylen = XLR_SEC_AES256_KEY_LENGTH; - hmac_keylen = sizeof(GCM_t); - ctl_size = sizeof(AES256GCM_t); - break; - case XLR_SEC_VECTOR__CIPHER_AES256__GCM__MODE_F8: - XLR_SEC_CMD_DIAG("XLR_SEC_VECTOR__CIPHER_AES256__GCM__MODE_F8 \n"); - cipher_key = &ctl_desc->cipherHashInfo.infoAES256F8GCM.cipherKey0; - hmac_key = &ctl_desc->cipherHashInfo.infoAES256F8GCM.GCMH0; - cipher_keylen = XLR_SEC_AES256F8_KEY_LENGTH; - hmac_keylen = sizeof(GCM_t); - ctl_size = sizeof(AES256F8GCM_t); - break; - case XLR_SEC_VECTOR_F9: - XLR_SEC_CMD_DIAG("XLR_SEC_VECTOR_F9 \n"); - hmac_key = &ctl_desc->cipherHashInfo.infoF9.authKey0; - hmac_keylen = sizeof(F9_t); - ctl_size = sizeof(F9_t); - break; - case XLR_SEC_VECTOR_CIPHER_ARC4__F9: - XLR_SEC_CMD_DIAG("XLR_SEC_VECTOR_CIPHER_ARC4__F9\n"); - cipher_key = &ctl_desc->cipherHashInfo.infoARC4F9.cipherKey0; - hmac_key = &ctl_desc->cipherHashInfo.infoARC4F9.authKey0; - cipher_keylen = op->rc4_key_len; - hmac_keylen = sizeof(F9_t); - ctl_size = sizeof(ARC4F9_t); - break; - case XLR_SEC_VECTOR_CIPHER_ARC4__F9__STATE: - XLR_SEC_CMD_DIAG("XLR_SEC_VECTOR_CIPHER_ARC4__F9__STATE\n"); - cipher_key = &ctl_desc->cipherHashInfo.infoARC4StateF9.cipherKey0; - cipher_state = - &ctl_desc->cipherHashInfo.infoARC4StateF9.Arc4SboxData0; - hmac_key = &ctl_desc->cipherHashInfo.infoARC4StateF9.authKey0; - cipher_keylen = op->rc4_key_len; - hmac_keylen = sizeof(F9_t); - ctl_size = sizeof(ARC4StateF9_t); - break; - case XLR_SEC_VECTOR__CIPHER_DES__F9__MODE_ECB_CBC: - XLR_SEC_CMD_DIAG(" XLR_SEC_VECTOR__CIPHER_DES__F9__MODE_ECB_CBC \n"); - cipher_key = &ctl_desc->cipherHashInfo.infoDESF9.cipherKey0; - hmac_key = &ctl_desc->cipherHashInfo.infoDESF9.authKey0; - hmac_keylen = sizeof(F9_t); - cipher_keylen = XLR_SEC_DES_KEY_LENGTH; - ctl_size = sizeof(DESF9_t); - break; - case XLR_SEC_VECTOR__CIPHER_3DES__F9__MODE_ECB_CBC: - XLR_SEC_CMD_DIAG("XLR_SEC_VECTOR__CIPHER_3DES__F9__MODE_ECB_CBC \n"); - cipher_key = &ctl_desc->cipherHashInfo.info3DESF9.cipherKey0; - hmac_key = &ctl_desc->cipherHashInfo.info3DESF9.authKey0; - cipher_keylen = XLR_SEC_3DES_KEY_LENGTH; - hmac_keylen = sizeof(F9_t); - ctl_size = sizeof(DES3F9_t); - break; - case XLR_SEC_VECTOR__CIPHER_AES128__F9__MODE_CTR_CFB: - XLR_SEC_CMD_DIAG("XLR_SEC_VECTOR__CIPHER_AES128__F9__MODE_CTR_CFB \n"); - cipher_key = &ctl_desc->cipherHashInfo.infoAES128F9.cipherKey0; - hmac_key = &ctl_desc->cipherHashInfo.infoAES128F9.authKey0; - cipher_keylen = XLR_SEC_AES128_KEY_LENGTH; - hmac_keylen = sizeof(F9_t); - ctl_size = sizeof(AES128F9_t); - break; - case XLR_SEC_VECTOR__CIPHER_AES128__F9__MODE_ECB_CBC_OFB: - XLR_SEC_CMD_DIAG(" XLR_SEC_VECTOR__CIPHER_AES128__F9__MODE_ECB_CBC_OFB \n"); - cipher_key = &ctl_desc->cipherHashInfo.infoAES128F9.cipherKey0; - hmac_key = &ctl_desc->cipherHashInfo.infoAES128F9.authKey0; - cipher_keylen = XLR_SEC_AES128_KEY_LENGTH; - hmac_keylen = sizeof(F9_t); - ctl_size = sizeof(AES128F9_t); - break; - case XLR_SEC_VECTOR__CIPHER_AES128__F9__MODE_F8: - XLR_SEC_CMD_DIAG("XLR_SEC_VECTOR__CIPHER_AES128__F9__MODE_F8 \n"); - cipher_key = &ctl_desc->cipherHashInfo.infoAES128F8F9.cipherKey0; - hmac_key = &ctl_desc->cipherHashInfo.infoAES128F8F9.authKey0; - cipher_keylen = XLR_SEC_AES128F8_KEY_LENGTH; - hmac_keylen = sizeof(F9_t); - ctl_size = sizeof(AES128F8F9_t); - break; - case XLR_SEC_VECTOR__CIPHER_AES192__F9__MODE_CTR_CFB: - XLR_SEC_CMD_DIAG("XLR_SEC_VECTOR__CIPHER_AES192__F9__MODE_CTR_CFB \n"); - cipher_key = &ctl_desc->cipherHashInfo.infoAES192F9.cipherKey0; - hmac_key = &ctl_desc->cipherHashInfo.infoAES192F9.authKey0; - cipher_keylen = XLR_SEC_AES192_KEY_LENGTH; - hmac_keylen = sizeof(F9_t); - ctl_size = sizeof(AES192F9_t); - break; - case XLR_SEC_VECTOR__CIPHER_AES192__F9__MODE_ECB_CBC_OFB: - XLR_SEC_CMD_DIAG("XLR_SEC_VECTOR__CIPHER_AES192__F9__MODE_ECB_CBC_OFB \n"); - cipher_key = &ctl_desc->cipherHashInfo.infoAES192F9.cipherKey0; - hmac_key = &ctl_desc->cipherHashInfo.infoAES192F9.authKey0; - cipher_keylen = XLR_SEC_AES192_KEY_LENGTH; - hmac_keylen = sizeof(F9_t); - ctl_size = sizeof(AES192F9_t); - break; - case XLR_SEC_VECTOR__CIPHER_AES192__F9__MODE_F8: - XLR_SEC_CMD_DIAG("XLR_SEC_VECTOR__CIPHER_AES192__F9__MODE_F8 \n"); - cipher_key = &ctl_desc->cipherHashInfo.infoAES192F8F9.cipherKey0; - hmac_key = &ctl_desc->cipherHashInfo.infoAES192F8F9.authKey0; - cipher_keylen = XLR_SEC_AES192F8_KEY_LENGTH; - hmac_keylen = sizeof(F9_t); - ctl_size = sizeof(AES192F8F9_t); - break; - case XLR_SEC_VECTOR__CIPHER_AES256__F9__MODE_CTR_CFB: - XLR_SEC_CMD_DIAG("XLR_SEC_VECTOR__CIPHER_AES256__F9__MODE_CTR_CFB \n"); - cipher_key = &ctl_desc->cipherHashInfo.infoAES256F9.cipherKey0; - hmac_key = &ctl_desc->cipherHashInfo.infoAES256F9.authKey0; - cipher_keylen = XLR_SEC_AES256_KEY_LENGTH; - hmac_keylen = sizeof(F9_t); - ctl_size = sizeof(AES256F9_t); - break; - case XLR_SEC_VECTOR__CIPHER_AES256__F9__MODE_ECB_CBC_OFB: - XLR_SEC_CMD_DIAG("XLR_SEC_VECTOR__CIPHER_AES256__F9__MODE_ECB_CBC_OFB \n"); - cipher_key = &ctl_desc->cipherHashInfo.infoAES256F9.cipherKey0; - hmac_key = &ctl_desc->cipherHashInfo.infoAES256F9.authKey0; - cipher_keylen = XLR_SEC_AES256_KEY_LENGTH; - hmac_keylen = sizeof(F9_t); - ctl_size = sizeof(AES256F9_t); - break; - case XLR_SEC_VECTOR__CIPHER_AES256__F9__MODE_F8: - XLR_SEC_CMD_DIAG("XLR_SEC_VECTOR__CIPHER_AES256__F9__MODE_F8 \n"); - cipher_key = &ctl_desc->cipherHashInfo.infoAES256F8F9.cipherKey0; - hmac_key = &ctl_desc->cipherHashInfo.infoAES256F8F9.authKey0; - cipher_keylen = XLR_SEC_AES256F8_KEY_LENGTH; - hmac_keylen = sizeof(F9_t); - ctl_size = sizeof(AES256F8F9_t); - break; - - default: - XLR_SEC_CMD_DIAG("default \n"); - return XLR_SEC_ERR_CONTROL_VECTOR; - } - - if ((cipher_key != NULL) && !(flags & XLR_SEC_SETUP_OP_PRESERVE_CIPHER_KEY)) - memcpy(cipher_key, &op->crypt_key[0], cipher_keylen); - - if ((hmac_key != NULL) && !(flags & XLR_SEC_SETUP_OP_PRESERVE_HMAC_KEY)) - memcpy(hmac_key, &op->mac_key[0], hmac_keylen); - if (cipher_state) { - if (op->rc4_loadstate) - memcpy(cipher_state, (void *)(unsigned long)op->rc4_state, - XLR_SEC_MAX_RC4_STATE_SIZE); - if (op->rc4_savestate) - user->aligned_state = (char *)cipher_state; - } - if (flags & XLR_SEC_SETUP_OP_FLIP_3DES_KEY) { - uint64_t temp; - - temp = ctl_desc->cipherHashInfo.info3DES.cipherKey0; - ctl_desc->cipherHashInfo.info3DES.cipherKey0 = - ctl_desc->cipherHashInfo.info3DES.cipherKey2; - ctl_desc->cipherHashInfo.info3DES.cipherKey2 = temp; - } - /* - * Control length is the number of control cachelines to be read so - * user needs to round up the control length to closest integer - * multiple of 32 bytes. - */ - ctl_size += sizeof(ctl_desc->instruction); - ctl_len = NUM_CHUNKS(ctl_size, 5); - XLR_SEC_CMD_DIAG("ctl_size in bytes: %u, in cachelines: %u\n", ctl_size, ctl_len); - CLEAR_SET_FIELD(*control, MSG_CMD_CTL_LEN, ctl_len); - - ctl_addr = (uint64_t) vtophys(ctl_desc); - CLEAR_SET_FIELD(*control, MSG_CMD_CTL_ADDR, ctl_addr); - - XLR_SEC_CMD_DIAG(" xlr_sec_control_setup(): ctl_desc=%p ctl_addr=%llx \n", - ctl_desc, (unsigned long long)ctl_addr); - - CLEAR_SET_FIELD(*control, MSG_CMD_CTL_CTL, SEC_SOP); - - return XLR_SEC_ERR_NONE; -} - -xlr_sec_error_t -xlr_sec_submit_op(symkey_desc_pt desc) -{ - struct msgrng_msg send_msg; - - int rsp_dest_id, cpu, hard_cpu, hard_thread; - int code, retries; - unsigned long msgrng_flags = 0; - - /* threads (0-3) are orthogonal to buckets 0-3 */ - cpu = xlr_cpu_id(); - - hard_cpu = cpu >> 2; - hard_thread = cpu & 0x3;/* thread id */ - rsp_dest_id = (hard_cpu << 3) + hard_thread; - - desc->op_ctl.cpu = hard_cpu; - desc->op_ctl.flags = 0; /* called from kernel thread */ - - XLR_SEC_CMD_DIAG("[%s]:%d: cpu=0x%x hard_cpu=0x%x hard_thrd=0x%x id=0x%x \n", - __FUNCTION__, __LINE__, cpu, hard_cpu, hard_thread, rsp_dest_id); - - /* - * Set DestId in Message Control Word. This tells the Security - * Engine which bucket to send the reply to for this CPU - */ - CLEAR_SET_FIELD(desc->control, MSG_CMD_CTL_ID, rsp_dest_id); - CLEAR_SET_FIELD(desc->data, MSG_CMD_CTL_ID, rsp_dest_id); - - CLEAR_SET_FIELD(desc->control, MSG_CTL_OP_TYPE, MSG0_CTL_OP_ENGINE_SYMKEY); - CLEAR_SET_FIELD(desc->data, MSG_CTL_OP_TYPE, MSG1_CTL_OP_SYMKEY_PIPE0); - - send_msg.msg0 = desc->control | (1ULL << 53); - send_msg.msg1 = desc->data | (1ULL << 53) | (1ULL << 52); - send_msg.msg2 = send_msg.msg3 = 0; - - desc->op_ctl.flags = 1; - //in_interrupt(); /* ipsec softirq ? */ - - XLR_SEC_CMD_DIAG("[%s]: IN_IRQ=%d msg0=0x%llx msg1=0x%llx \n", - __FUNCTION__, desc->op_ctl.flags, send_msg.msg0, send_msg.msg1); - - retries = 100; - while (retries--) { - msgrng_flags = msgrng_access_enable(); - code = message_send(SEC_MSGRING_WORDSIZE, MSGRNG_CODE_SEC, - desc->op_ctl.stn_id, &send_msg); - msgrng_restore(msgrng_flags); - if (code == 0) - break; - } - return (XLR_SEC_ERR_NONE); -} - -symkey_desc_pt -xlr_sec_allocate_desc(void *session_ptr) -{ - uint64_t addr; - symkey_desc_pt aligned, new; - - new = (symkey_desc_pt) malloc(sizeof(symkey_desc_t), - M_DEVBUF, M_NOWAIT | M_ZERO); - - if (new == NULL) - return (NULL); - - new->ses = session_ptr; - - new->user.kern_src = new->user.aligned_src = - (uint8_t *) contigmalloc(256 * 1024 + 1024, - M_DEVBUF, M_NOWAIT | M_ZERO, - 0, 0xffffffff, XLR_CACHELINE_SIZE, 0); - - if (new->user.kern_src == NULL) { - printf("ERROR - malloc failed for user.kern_src\n"); - return NULL; - } - new->user.aligned_dest = new->user.kern_dest = - (uint8_t *) contigmalloc(257 * 1024, - M_DEVBUF, M_NOWAIT | M_ZERO, - 0, 0xffffffff, XLR_CACHELINE_SIZE, 0); - - if (new->user.aligned_dest == NULL) { - printf("ERROR - malloc failed for user.aligned_dest\n"); - return NULL; - } - new->next_src_buf = (uint8_t *) contigmalloc(256 * 1024 + 1024, - M_DEVBUF, M_NOWAIT | M_ZERO, - 0, 0xffffffff, XLR_CACHELINE_SIZE, 0); - - if (new->next_src_buf == NULL) { - printf("ERROR - malloc failed for next_src_buf\n"); - return NULL; - } - new->next_dest_buf = - (uint8_t *) contigmalloc(257 * 1024, - M_DEVBUF, M_NOWAIT | M_ZERO, - 0, 0xffffffff, XLR_CACHELINE_SIZE, 0); - - if (new->next_dest_buf == NULL) { - printf("ERROR - malloc failed for next_dest_buf\n"); - return NULL; - } - new->user.kern_auth = new->user.user_auth = NULL; - new->user.aligned_auth = new->user.user_auth = NULL; - - /* find cacheline alignment */ - aligned = new; - addr = (uint64_t) vtophys(new); - - /* save for free */ - aligned->alloc = new; - - /* setup common control info */ - aligned->op_ctl.phys_self = addr; - aligned->op_ctl.stn_id = MSGRNG_STNID_SEC0; - aligned->op_ctl.vaddr = (uintptr_t)aligned; - - return (aligned); -} - - -static void -xlr_sec_free_desc(symkey_desc_pt desc) -{ - if ((desc == NULL) || (desc->alloc == NULL)) { - printf("%s: NULL descriptor \n", __FUNCTION__); - return; - } - contigfree(desc, sizeof(symkey_desc_t), M_DEVBUF); - return; -} - -void -print_buf(char *desc, void *data, int len) -{ - uint8_t *dp; - int i; - - DPRINT("%s: ", desc); /* newline done in for-loop */ - dp = data; - for (i = 0; i < len; i++, dp++) { - if ((i % 16) == 0) - DPRINT("\n"); - DPRINT(" %c%c", - nib2hex[(((*dp) & 0xf0) >> 4)], - nib2hex[((*dp) & 0x0f)]); - } - DPRINT("\n"); -} - - -#ifdef XLR_SEC_CMD_DEBUG -static void -decode_symkey_desc(symkey_desc_pt desc, uint32_t cfg_vector) -{ - - unsigned long long word; - - /* uint8_t *info; */ - /* int i; */ - - DPRINT("MSG - CTL: \n"); - DPRINT("\t CTRL = %lld \n", - GET_FIELD(desc->control, MSG_CMD_CTL_CTL)); - DPRINT("\t CTRL LEN = %lld \n", - GET_FIELD(desc->control, MSG_CMD_CTL_LEN)); - DPRINT("\t CTRL ADDR = %llx \n\n", - GET_FIELD(desc->control, MSG_CMD_CTL_ADDR)); - - DPRINT("MSG - DATA: \n"); - DPRINT("\t CTRL = %lld \n", - GET_FIELD(desc->data, MSG_CMD_DATA_CTL)); - DPRINT("\t DATA LEN = %lld \n", - GET_FIELD(desc->data, MSG_CMD_DATA_LEN)); - DPRINT("\t DATA ADDR = %llx \n\n", - GET_FIELD(desc->data, MSG_CMD_DATA_ADDR)); - - DPRINT("CONTROL DESCRIPTOR: \n"); - word = desc->ctl_desc.instruction; - DPRINT("\tINSTRUCTION: %llx\n", word); - DPRINT("\t\tOVERRIDE CIPH = %lld \n", GET_FIELD(word, CTL_DSC_OVERRIDECIPHER)); - DPRINT("\t\tARC4 WAIT = %lld \n", GET_FIELD(word, CTL_DSC_ARC4_WAIT4SAVE)); - DPRINT("\t\tARC4 SAVE = %lld \n", GET_FIELD(word, CTL_DSC_ARC4_SAVESTATE)); - DPRINT("\t\tARC4 LOAD = %lld \n", GET_FIELD(word, CTL_DSC_ARC4_LOADSTATE)); - DPRINT("\t\tARC4 KEYLEN = %lld \n", GET_FIELD(word, CTL_DSC_ARC4_KEYLEN)); - DPRINT("\t\tCIPHER = %lld \n", GET_FIELD(word, CTL_DSC_CPHR)); - DPRINT("\t\tCIPHER MODE = %lld \n", GET_FIELD(word, CTL_DSC_MODE)); - DPRINT("\t\tINIT CIPHER = %lld \n", GET_FIELD(word, CTL_DSC_ICPHR)); - DPRINT("\t\tHMAC = %lld \n", GET_FIELD(word, CTL_DSC_HMAC)); - DPRINT("\t\tHASH ALG = %lld \n", GET_FIELD(word, CTL_DSC_HASH) | (GET_FIELD(word, CTL_DSC_HASHHI) << 2)); - DPRINT("\t\tINIT HASH = %lld \n", GET_FIELD(word, CTL_DSC_IHASH)); - DPRINT("\t\tCHKSUM = %lld \n", GET_FIELD(word, CTL_DSC_CKSUM)); - DPRINT("\tCIPHER HASH INFO: \n"); -#if 0 - info = (uint8_t *) & desc->ctl_desc->cipherHashInfo; - for (i = 0; i < sizeof(CipherHashInfo_t); i++, info++) { - DPRINT(" %02x", *info); - if (i && (i % 16) == 0) - DPRINT("\n"); - } - DPRINT("\n\n"); -#endif - - switch (cfg_vector) { - case XLR_SEC_VECTOR_CIPHER_ARC4: - DPRINT("VECTOR: XLR_SEC_VECTOR_CIPHER_ARC4 \n"); - print_buf("ARC4 Key", - &desc->ctl_desc.cipherHashInfo.infoARC4.cipherKey0, - GET_FIELD(word, CTL_DSC_ARC4_KEYLEN)); - break; - case XLR_SEC_VECTOR_CIPHER_ARC4__HMAC: - DPRINT("VECTOR: XLR_SEC_VECTOR_CIPHER_ARC4__HMAC \n"); - print_buf("ARC4 Key", - &desc->ctl_desc.cipherHashInfo.infoARC4HMAC.cipherKey0, - GET_FIELD(word, CTL_DSC_ARC4_KEYLEN)); - print_buf("HMAC Key", - &desc->ctl_desc.cipherHashInfo.infoARC4HMAC.hmacKey0, - sizeof(HMAC_t)); - break; - case XLR_SEC_VECTOR_CIPHER_ARC4__STATE: - DPRINT("VECTOR: XLR_SEC_VECTOR_CIPHER_ARC4__STATE \n"); - print_buf("ARC4 Key", - &desc->ctl_desc.cipherHashInfo.infoARC4State.cipherKey0, - GET_FIELD(word, CTL_DSC_ARC4_KEYLEN)); - break; - case XLR_SEC_VECTOR_CIPHER_ARC4__HMAC__STATE: - DPRINT("VECTOR: XLR_SEC_VECTOR_CIPHER_ARC4__HMAC__STATE \n"); - print_buf("ARC4 Key", - &desc->ctl_desc.cipherHashInfo.infoARC4StateHMAC.cipherKey0, - GET_FIELD(word, CTL_DSC_ARC4_KEYLEN)); - print_buf("HMAC Key", - &desc->ctl_desc.cipherHashInfo.infoARC4StateHMAC.hmacKey0, - sizeof(HMAC_t)); - break; - case XLR_SEC_VECTOR_CIPHER_KASUMI_F8: - DPRINT("VECTOR: XLR_SEC_VECTOR_CIPHER_KASUMI_F8 \n"); - print_buf("KASUMI_F8 Key", - &desc->ctl_desc.cipherHashInfo.infoKASUMIF8.cipherKey0, - XLR_SEC_KASUMI_F8_KEY_LENGTH); - break; - case XLR_SEC_VECTOR_CIPHER_KASUMI_F8__HMAC: - DPRINT("XLR_SEC_VECTOR_CIPHER_KASUMI_F8__HMAC\n"); - print_buf("KASUMI_F8 Key", - &desc->ctl_desc.cipherHashInfo.infoKASUMIF8HMAC.cipherKey0, - XLR_SEC_KASUMI_F8_KEY_LENGTH); - print_buf("HMAC Key", - &desc->ctl_desc.cipherHashInfo.infoKASUMIF8HMAC.hmacKey0, - sizeof(HMAC_t)); - break; - case XLR_SEC_VECTOR_CIPHER_KASUMI_F8__HMAC2: - DPRINT("XLR_SEC_VECTOR_CIPHER_KASUMI_F8__HMAC2\n"); - print_buf("KASUMI_F8 Key", - &desc->ctl_desc.cipherHashInfo.infoKASUMIF8HMAC2.cipherKey0, - XLR_SEC_KASUMI_F8_KEY_LENGTH); - print_buf("HMAC2 Key", - &desc->ctl_desc.cipherHashInfo.infoKASUMIF8HMAC2.hmacKey0, - sizeof(HMAC2_t)); - break; - case XLR_SEC_VECTOR_CIPHER_KASUMI_F8__GCM: - DPRINT("XLR_SEC_VECTOR_CIPHER_KASUMI_F8__GCM\n"); - print_buf("KASUMI_F8 Key", - &desc->ctl_desc.cipherHashInfo.infoKASUMIF8GCM.cipherKey0, - XLR_SEC_KASUMI_F8_KEY_LENGTH); - print_buf("GCM Key", - &desc->ctl_desc.cipherHashInfo.infoKASUMIF8GCM.GCMH0, - sizeof(GCM_t)); - break; - case XLR_SEC_VECTOR_CIPHER_KASUMI_F8__F9: - DPRINT("XLR_SEC_VECTOR_CIPHER_KASUMI_F8__F9\n"); - print_buf("KASUMI_F8 Key", - &desc->ctl_desc.cipherHashInfo.infoKASUMIF8F9.cipherKey0, - XLR_SEC_KASUMI_F8_KEY_LENGTH); - print_buf("F9 Key", - &desc->ctl_desc.cipherHashInfo.infoKASUMIF8F9.authKey0, - sizeof(F9_t)); - break; - case XLR_SEC_VECTOR_MAC: - DPRINT("VECTOR: XLR_SEC_VECTOR_MAC \n"); - DPRINT("MAC-ONLY - No Info\n"); - break; - case XLR_SEC_VECTOR_HMAC: - DPRINT("VECTOR: XLR_SEC_VECTOR_HMAC \n"); - print_buf("HMAC Key", - &desc->ctl_desc.cipherHashInfo.infoHMAC.hmacKey0, - sizeof(HMAC_t)); - break; - case XLR_SEC_VECTOR__CIPHER_DES__HMAC__MODE_ECB_CBC: - DPRINT("VECTOR: XLR_SEC_VECTOR__CIPHER_DES__HMAC__MODE_ECB_CBC \n"); - print_buf("CIPHER Key", - &desc->ctl_desc.cipherHashInfo.infoDESHMAC.cipherKey0, - XLR_SEC_DES_KEY_LENGTH); - print_buf("HMAC Key", - &desc->ctl_desc.cipherHashInfo.infoDESHMAC.hmacKey0, - sizeof(HMAC_t)); - break; - case XLR_SEC_VECTOR__CIPHER_DES__MODE_ECB_CBC: - DPRINT("VECTOR: XLR_SEC_VECTOR__CIPHER_DES__MODE_ECB_CBC \n"); - print_buf("CIPHER Key", - &desc->ctl_desc.cipherHashInfo.infoDES.cipherKey0, - XLR_SEC_DES_KEY_LENGTH); - break; - case XLR_SEC_VECTOR__CIPHER_3DES__HMAC__MODE_ECB_CBC: - DPRINT("VECTOR: XLR_SEC_VECTOR__CIPHER_3DES__HMAC__MODE_ECB_CBC \n"); - print_buf("CIPHER Key", - &desc->ctl_desc.cipherHashInfo.info3DESHMAC.cipherKey0, - XLR_SEC_3DES_KEY_LENGTH); - print_buf("HMAC Key", - &desc->ctl_desc.cipherHashInfo.info3DESHMAC.hmacKey0, - sizeof(HMAC_t)); - break; - case XLR_SEC_VECTOR__CIPHER_3DES__MODE_ECB_CBC: - DPRINT("VECTOR: XLR_SEC_VECTOR__CIPHER_3DES__MODE_ECB_CBC \n"); - print_buf("CIPHER Key", - &desc->ctl_desc.cipherHashInfo.info3DES.cipherKey0, - XLR_SEC_3DES_KEY_LENGTH); - break; - case XLR_SEC_VECTOR__CIPHER_AES128__HMAC__MODE_CTR_CFB: - DPRINT("VECTOR: XLR_SEC_VECTOR__CIPHER_AES128__HMAC__MODE_CTR_CFB \n"); - print_buf("CIPHER Key", - &desc->ctl_desc.cipherHashInfo.infoAES128HMAC.cipherKey0, - XLR_SEC_AES128_KEY_LENGTH); - print_buf("HMAC Key", - &desc->ctl_desc.cipherHashInfo.infoAES128HMAC.hmacKey0, - sizeof(HMAC_t)); - break; - case XLR_SEC_VECTOR__CIPHER_AES128__MODE_CTR_CFB: - DPRINT("VECTOR: XLR_SEC_VECTOR__CIPHER_AES128__MODE_CTR_CFB \n"); - print_buf("CIPHER Key", - &desc->ctl_desc.cipherHashInfo.infoAES128.cipherKey0, - XLR_SEC_AES128_KEY_LENGTH); - break; - case XLR_SEC_VECTOR__CIPHER_AES128__HMAC__MODE_ECB_CBC_OFB: - DPRINT("VECTOR: XLR_SEC_VECTOR__CIPHER_AES128__HMAC__MODE_ECB_CBC_OFB\n"); - print_buf("CIPHER Key", - &desc->ctl_desc.cipherHashInfo.infoAES128HMAC.cipherKey0, - XLR_SEC_AES128_KEY_LENGTH); - print_buf("HMAC Key", - &desc->ctl_desc.cipherHashInfo.infoAES128HMAC.hmacKey0, - sizeof(HMAC_t)); - break; - case XLR_SEC_VECTOR__CIPHER_AES128__MODE_ECB_CBC_OFB: - DPRINT("VECTOR: XLR_SEC_VECTOR__CIPHER_AES128__MODE_ECB_CBC_OFB \n"); - print_buf("CIPHER Key", - &desc->ctl_desc.cipherHashInfo.infoAES128.cipherKey0, - XLR_SEC_AES128_KEY_LENGTH); - break; - case XLR_SEC_VECTOR__CIPHER_AES192__HMAC__MODE_CTR_CFB: - DPRINT("VECTOR: XLR_SEC_VECTOR__CIPHER_AES192__HMAC__MODE_CTR_CFB \n"); - print_buf("CIPHER Key", - &desc->ctl_desc.cipherHashInfo.infoAES192HMAC.cipherKey0, - XLR_SEC_AES192_KEY_LENGTH); - print_buf("HMAC Key", - &desc->ctl_desc.cipherHashInfo.infoAES192HMAC.hmacKey0, - sizeof(HMAC_t)); - break; - case XLR_SEC_VECTOR__CIPHER_AES192__MODE_CTR_CFB: - DPRINT("VECTOR: XLR_SEC_VECTOR__CIPHER_AES192__MODE_CTR_CFB \n"); - print_buf("CIPHER Key", - &desc->ctl_desc.cipherHashInfo.infoAES192.cipherKey0, - XLR_SEC_AES192_KEY_LENGTH); - break; - case XLR_SEC_VECTOR__CIPHER_AES192__HMAC__MODE_ECB_CBC_OFB: - DPRINT("VECTOR: XLR_SEC_VECTOR__CIPHER_AES192__HMAC__MODE_ECB_CBC_OFB\n"); - print_buf("CIPHER Key", - &desc->ctl_desc.cipherHashInfo.infoAES192HMAC.cipherKey0, - XLR_SEC_AES192_KEY_LENGTH); - print_buf("HMAC Key", - &desc->ctl_desc.cipherHashInfo.infoAES192HMAC.hmacKey0, - sizeof(HMAC_t)); - break; - case XLR_SEC_VECTOR__CIPHER_AES192__MODE_ECB_CBC_OFB: - DPRINT("VECTOR: XLR_SEC_VECTOR__CIPHER_AES192__MODE_ECB_CBC_OFB \n"); - print_buf("CIPHER Key", - &desc->ctl_desc.cipherHashInfo.infoAES192.cipherKey0, - XLR_SEC_AES192_KEY_LENGTH); - break; - - case XLR_SEC_VECTOR__CIPHER_AES256__HMAC__MODE_CTR_CFB: - DPRINT("VECTOR: XLR_SEC_VECTOR__CIPHER_AES256__HMAC__MODE_CTR_CFB \n"); - print_buf("CIPHER Key", - &desc->ctl_desc.cipherHashInfo.infoAES256HMAC.cipherKey0, - XLR_SEC_AES256_KEY_LENGTH); - print_buf("HMAC Key", - &desc->ctl_desc.cipherHashInfo.infoAES256HMAC.hmacKey0, - sizeof(HMAC_t)); - break; - case XLR_SEC_VECTOR__CIPHER_AES256__MODE_CTR_CFB: - DPRINT("VECTOR: XLR_SEC_VECTOR__CIPHER_AES256__MODE_CTR_CFB \n"); - print_buf("CIPHER Key", - &desc->ctl_desc.cipherHashInfo.infoAES256.cipherKey0, - XLR_SEC_AES256_KEY_LENGTH); - break; - case XLR_SEC_VECTOR__CIPHER_AES256__HMAC__MODE_ECB_CBC_OFB: - DPRINT("VECTOR: XLR_SEC_VECTOR__CIPHER_AES256__HMAC__MODE_ECB_CBC_OFB \n"); - print_buf("CIPHER Key", - &desc->ctl_desc.cipherHashInfo.infoAES256HMAC.cipherKey0, - XLR_SEC_AES256_KEY_LENGTH); - print_buf("HMAC Key", - &desc->ctl_desc.cipherHashInfo.infoAES256HMAC.hmacKey0, - sizeof(HMAC_t)); - break; - case XLR_SEC_VECTOR__CIPHER_AES256__MODE_ECB_CBC_OFB: - DPRINT("VECTOR: XLR_SEC_VECTOR__CIPHER_AES256__MODE_ECB_CBC_OFB \n"); - print_buf("CIPHER Key", - &desc->ctl_desc.cipherHashInfo.infoAES256.cipherKey0, - XLR_SEC_AES256_KEY_LENGTH); - break; - case XLR_SEC_VECTOR_CIPHER_ARC4__HMAC2: - DPRINT("VECTOR: XLR_SEC_VECTOR_CIPHER_ARC4__HMAC2 \n"); - print_buf("ARC4 Key", - &desc->ctl_desc.cipherHashInfo.infoARC4HMAC2.cipherKey0, - GET_FIELD(word, CTL_DSC_ARC4_KEYLEN)); - print_buf("HMAC2 Key", - &desc->ctl_desc.cipherHashInfo.infoARC4HMAC2.hmacKey0, - sizeof(HMAC2_t)); - break; - case XLR_SEC_VECTOR_CIPHER_ARC4__HMAC2__STATE: - DPRINT("VECTOR: XLR_SEC_VECTOR_CIPHER_ARC4__HMAC2__STATE \n"); - print_buf("ARC4 Key", - &desc->ctl_desc.cipherHashInfo.infoARC4StateHMAC2.cipherKey0, - GET_FIELD(word, CTL_DSC_ARC4_KEYLEN)); - print_buf("HMAC2 Key", - &desc->ctl_desc.cipherHashInfo.infoARC4StateHMAC2.hmacKey0, - sizeof(HMAC2_t)); - break; - case XLR_SEC_VECTOR_HMAC2: - DPRINT("VECTOR: XLR_SEC_VECTOR_HMAC2 \n"); - print_buf("HMAC2 Key", - &desc->ctl_desc.cipherHashInfo.infoHMAC2.hmacKey0, - sizeof(HMAC2_t)); - break; - case XLR_SEC_VECTOR__CIPHER_DES__HMAC2__MODE_ECB_CBC: - DPRINT("VECTOR: XLR_SEC_VECTOR__CIPHER_DES__HMAC2__MODE_ECB_CBC \n"); - print_buf("CIPHER Key", - &desc->ctl_desc.cipherHashInfo.infoDESHMAC2.cipherKey0, - XLR_SEC_DES_KEY_LENGTH); - print_buf("HMAC2 Key", - &desc->ctl_desc.cipherHashInfo.infoDESHMAC2.hmacKey0, - sizeof(HMAC2_t)); - break; - case XLR_SEC_VECTOR__CIPHER_3DES__HMAC2__MODE_ECB_CBC: - DPRINT("VECTOR: XLR_SEC_VECTOR__CIPHER_3DES__HMAC2__MODE_ECB_CBC \n"); - print_buf("CIPHER Key", - &desc->ctl_desc.cipherHashInfo.info3DESHMAC2.cipherKey0, - XLR_SEC_3DES_KEY_LENGTH); - print_buf("HMAC2 Key", - &desc->ctl_desc.cipherHashInfo.info3DESHMAC2.hmacKey0, - sizeof(HMAC2_t)); - break; - case XLR_SEC_VECTOR__CIPHER_AES128__HMAC2__MODE_CTR_CFB: - DPRINT("VECTOR: XLR_SEC_VECTOR__CIPHER_AES128__HMAC2__MODE_CTR_CFB \n"); - print_buf("CIPHER Key", - &desc->ctl_desc.cipherHashInfo.infoAES128HMAC2.cipherKey0, - XLR_SEC_AES128_KEY_LENGTH); - print_buf("HMAC2 Key", - &desc->ctl_desc.cipherHashInfo.infoAES128HMAC2.hmacKey0, - sizeof(HMAC2_t)); - break; - case XLR_SEC_VECTOR__CIPHER_AES128__HMAC2__MODE_ECB_CBC_OFB: - DPRINT("VECTOR: XLR_SEC_VECTOR__CIPHER_AES128__HMAC2__MODE_ECB_CBC_OFB\n"); - print_buf("CIPHER Key", - &desc->ctl_desc.cipherHashInfo.infoAES128HMAC2.cipherKey0, - XLR_SEC_AES128_KEY_LENGTH); - print_buf("HMAC2 Key", - &desc->ctl_desc.cipherHashInfo.infoAES128HMAC2.hmacKey0, - sizeof(HMAC2_t)); - break; - case XLR_SEC_VECTOR__CIPHER_AES192__HMAC2__MODE_CTR_CFB: - DPRINT("VECTOR: XLR_SEC_VECTOR__CIPHER_AES192__HMAC2__MODE_CTR_CFB \n"); - print_buf("CIPHER Key", - &desc->ctl_desc.cipherHashInfo.infoAES192HMAC2.cipherKey0, - XLR_SEC_AES192_KEY_LENGTH); - print_buf("HMAC2 Key", - &desc->ctl_desc.cipherHashInfo.infoAES192HMAC2.hmacKey0, - sizeof(HMAC2_t)); - break; - case XLR_SEC_VECTOR__CIPHER_AES192__HMAC2__MODE_ECB_CBC_OFB: - DPRINT("VECTOR: XLR_SEC_VECTOR__CIPHER_AES192__HMAC2__MODE_ECB_CBC_OFB\n"); - print_buf("CIPHER Key", - &desc->ctl_desc.cipherHashInfo.infoAES192HMAC2.cipherKey0, - XLR_SEC_AES192_KEY_LENGTH); - print_buf("HMAC2 Key", - &desc->ctl_desc.cipherHashInfo.infoAES192HMAC2.hmacKey0, - sizeof(HMAC2_t)); - break; - case XLR_SEC_VECTOR__CIPHER_AES256__HMAC2__MODE_CTR_CFB: - DPRINT("VECTOR: XLR_SEC_VECTOR__CIPHER_AES256__HMAC2__MODE_CTR_CFB \n"); - print_buf("CIPHER Key", - &desc->ctl_desc.cipherHashInfo.infoAES256HMAC2.cipherKey0, - XLR_SEC_AES256_KEY_LENGTH); - print_buf("HMAC2 Key", - &desc->ctl_desc.cipherHashInfo.infoAES256HMAC2.hmacKey0, - sizeof(HMAC2_t)); - break; - - case XLR_SEC_VECTOR__CIPHER_AES256__HMAC2__MODE_ECB_CBC_OFB: - DPRINT("VECTOR: XLR_SEC_VECTOR__CIPHER_AES256__HMAC2__MODE_ECB_CBC_OFB \n"); - print_buf("CIPHER Key", - &desc->ctl_desc.cipherHashInfo.infoAES256HMAC2.cipherKey0, - XLR_SEC_AES256_KEY_LENGTH); - print_buf("HMAC2 Key", - &desc->ctl_desc.cipherHashInfo.infoAES256HMAC2.hmacKey0, - sizeof(HMAC2_t)); - break; - case XLR_SEC_VECTOR_CIPHER_ARC4__GCM: - DPRINT("VECTOR: XLR_SEC_VECTOR_CIPHER_ARC4__GCM \n"); - print_buf("ARC4 Key", - &desc->ctl_desc.cipherHashInfo.infoARC4GCM.cipherKey0, - GET_FIELD(word, CTL_DSC_ARC4_KEYLEN)); - print_buf("GCM Key", - &desc->ctl_desc.cipherHashInfo.infoARC4GCM.GCMH0, - sizeof(GCM_t)); - break; - case XLR_SEC_VECTOR_CIPHER_ARC4__GCM__STATE: - DPRINT("VECTOR: XLR_SEC_VECTOR_CIPHER_ARC4__GCM__STATE \n"); - print_buf("ARC4 Key", - &desc->ctl_desc.cipherHashInfo.infoARC4StateGCM.cipherKey0, - GET_FIELD(word, CTL_DSC_ARC4_KEYLEN)); - print_buf("GCM Key", - &desc->ctl_desc.cipherHashInfo.infoARC4StateGCM.GCMH0, - sizeof(GCM_t)); - break; - case XLR_SEC_VECTOR_GCM: - DPRINT("VECTOR: XLR_SEC_VECTOR_GCM \n"); - print_buf("GCM Key", - &desc->ctl_desc.cipherHashInfo.infoGCM.GCMH0, - sizeof(GCM_t)); - break; - case XLR_SEC_VECTOR__CIPHER_DES__GCM__MODE_ECB_CBC: - DPRINT("VECTOR: XLR_SEC_VECTOR__CIPHER_DES__GCM__MODE_ECB_CBC \n"); - print_buf("CIPHER Key", - &desc->ctl_desc.cipherHashInfo.infoDESGCM.cipherKey0, - XLR_SEC_DES_KEY_LENGTH); - print_buf("GCM Key", - &desc->ctl_desc.cipherHashInfo.infoDESGCM.GCMH0, - sizeof(GCM_t)); - break; - case XLR_SEC_VECTOR__CIPHER_3DES__GCM__MODE_ECB_CBC: - DPRINT("VECTOR: XLR_SEC_VECTOR__CIPHER_3DES__GCM__MODE_ECB_CBC \n"); - print_buf("CIPHER Key", - &desc->ctl_desc.cipherHashInfo.info3DESGCM.cipherKey0, - XLR_SEC_3DES_KEY_LENGTH); - print_buf("GCM Key", - &desc->ctl_desc.cipherHashInfo.info3DESGCM.GCMH0, - sizeof(GCM_t)); - break; - case XLR_SEC_VECTOR__CIPHER_AES128__GCM__MODE_CTR_CFB: - DPRINT("VECTOR: XLR_SEC_VECTOR__CIPHER_AES128__GCM__MODE_CTR_CFB \n"); - print_buf("CIPHER Key", - &desc->ctl_desc.cipherHashInfo.infoAES128GCM.cipherKey0, - XLR_SEC_AES128_KEY_LENGTH); - print_buf("GCM Key", - &desc->ctl_desc.cipherHashInfo.infoAES128GCM.GCMH0, - XLR_SEC_AES128_KEY_LENGTH); - break; - case XLR_SEC_VECTOR__CIPHER_AES128__GCM__MODE_ECB_CBC_OFB: - DPRINT("VECTOR: XLR_SEC_VECTOR__CIPHER_AES128__GCM__MODE_ECB_CBC_OFB\n"); - print_buf("CIPHER Key", - &desc->ctl_desc.cipherHashInfo.infoAES128GCM.cipherKey0, - XLR_SEC_AES128_KEY_LENGTH); - print_buf("GCM Key", - &desc->ctl_desc.cipherHashInfo.infoAES128GCM.GCMH0, - XLR_SEC_AES128_KEY_LENGTH); - break; - case XLR_SEC_VECTOR__CIPHER_AES192__GCM__MODE_CTR_CFB: - DPRINT("VECTOR: XLR_SEC_VECTOR__CIPHER_AES192__GCM__MODE_CTR_CFB \n"); - print_buf("CIPHER Key", - &desc->ctl_desc.cipherHashInfo.infoAES192GCM.cipherKey0, - XLR_SEC_AES192_KEY_LENGTH); - print_buf("GCM Key", - &desc->ctl_desc.cipherHashInfo.infoAES192GCM.GCMH0, - XLR_SEC_AES192_KEY_LENGTH); - break; - case XLR_SEC_VECTOR__CIPHER_AES192__GCM__MODE_ECB_CBC_OFB: - DPRINT("VECTOR: XLR_SEC_VECTOR__CIPHER_AES192__GCM__MODE_ECB_CBC_OFB\n"); - print_buf("CIPHER Key", - &desc->ctl_desc.cipherHashInfo.infoAES192GCM.cipherKey0, - XLR_SEC_AES192_KEY_LENGTH); - print_buf("GCM Key", - &desc->ctl_desc.cipherHashInfo.infoAES192GCM.GCMH0, - XLR_SEC_AES192_KEY_LENGTH); - break; - case XLR_SEC_VECTOR__CIPHER_AES256__GCM__MODE_CTR_CFB: - DPRINT("VECTOR: XLR_SEC_VECTOR__CIPHER_AES256__GCM__MODE_CTR_CFB \n"); - print_buf("CIPHER Key", - &desc->ctl_desc.cipherHashInfo.infoAES256GCM.cipherKey0, - XLR_SEC_AES256_KEY_LENGTH); - print_buf("GCM Key", - &desc->ctl_desc.cipherHashInfo.infoAES256GCM.GCMH0, - XLR_SEC_AES256_KEY_LENGTH); - break; - case XLR_SEC_VECTOR__CIPHER_AES256__GCM__MODE_ECB_CBC_OFB: - DPRINT("VECTOR: XLR_SEC_VECTOR__CIPHER_AES256__GCM__MODE_ECB_CBC_OFB \n"); - print_buf("CIPHER Key", - &desc->ctl_desc.cipherHashInfo.infoAES256GCM.cipherKey0, - XLR_SEC_AES256_KEY_LENGTH); - print_buf("GCM Key", - &desc->ctl_desc.cipherHashInfo.infoAES256GCM.GCMH0, - XLR_SEC_AES256_KEY_LENGTH); - break; - case XLR_SEC_VECTOR_CIPHER_ARC4__F9: - DPRINT("VECTOR: XLR_SEC_VECTOR_CIPHER_ARC4__F9 \n"); - print_buf("ARC4 Key", - &desc->ctl_desc.cipherHashInfo.infoARC4F9.cipherKey0, - GET_FIELD(word, CTL_DSC_ARC4_KEYLEN)); - print_buf("F9 Key", - &desc->ctl_desc.cipherHashInfo.infoARC4F9.authKey0, - sizeof(F9_t)); - break; - case XLR_SEC_VECTOR_CIPHER_ARC4__F9__STATE: - DPRINT("VECTOR: XLR_SEC_VECTOR_CIPHER_ARC4__F9__STATE \n"); - print_buf("ARC4 Key", - &desc->ctl_desc.cipherHashInfo.infoARC4StateF9.cipherKey0, - GET_FIELD(word, CTL_DSC_ARC4_KEYLEN)); - print_buf("F9 Key", - &desc->ctl_desc.cipherHashInfo.infoARC4StateF9.authKey0, - sizeof(F9_t)); - break; - case XLR_SEC_VECTOR_F9: - DPRINT("VECTOR: XLR_SEC_VECTOR_F9 \n"); - print_buf("F9 Key", - &desc->ctl_desc.cipherHashInfo.infoF9.authKey0, - sizeof(F9_t)); - break; - case XLR_SEC_VECTOR__CIPHER_DES__F9__MODE_ECB_CBC: - DPRINT("VECTOR: XLR_SEC_VECTOR__CIPHER_DES__F9__MODE_ECB_CBC \n"); - print_buf("CIPHER Key", - &desc->ctl_desc.cipherHashInfo.infoDESF9.cipherKey0, - XLR_SEC_DES_KEY_LENGTH); - print_buf("F9 Key", - &desc->ctl_desc.cipherHashInfo.infoDESF9.authKey0, - sizeof(F9_t)); - break; - case XLR_SEC_VECTOR__CIPHER_3DES__F9__MODE_ECB_CBC: - DPRINT("VECTOR: XLR_SEC_VECTOR__CIPHER_3DES__F9__MODE_ECB_CBC \n"); - print_buf("CIPHER Key", - &desc->ctl_desc.cipherHashInfo.info3DESF9.cipherKey0, - XLR_SEC_3DES_KEY_LENGTH); - print_buf("F9 Key", - &desc->ctl_desc.cipherHashInfo.info3DESF9.authKey0, - sizeof(F9_t)); - break; - case XLR_SEC_VECTOR__CIPHER_AES128__F9__MODE_CTR_CFB: - DPRINT("VECTOR: XLR_SEC_VECTOR__CIPHER_AES128__F9__MODE_CTR_CFB \n"); - print_buf("CIPHER Key", - &desc->ctl_desc.cipherHashInfo.infoAES128F9.cipherKey0, - XLR_SEC_AES128_KEY_LENGTH); - print_buf("F9 Key", - &desc->ctl_desc.cipherHashInfo.infoAES128F9.authKey0, - sizeof(F9_t)); - break; - case XLR_SEC_VECTOR__CIPHER_AES128__F9__MODE_ECB_CBC_OFB: - DPRINT("VECTOR: XLR_SEC_VECTOR__CIPHER_AES128__F9__MODE_ECB_CBC_OFB\n"); - print_buf("CIPHER Key", - &desc->ctl_desc.cipherHashInfo.infoAES128F9.cipherKey0, - XLR_SEC_AES128_KEY_LENGTH); - print_buf("F9 Key", - &desc->ctl_desc.cipherHashInfo.infoAES128F9.authKey0, - sizeof(F9_t)); - break; - case XLR_SEC_VECTOR__CIPHER_AES192__F9__MODE_CTR_CFB: - DPRINT("VECTOR: XLR_SEC_VECTOR__CIPHER_AES192__F9__MODE_CTR_CFB \n"); - print_buf("CIPHER Key", - &desc->ctl_desc.cipherHashInfo.infoAES192F9.cipherKey0, - XLR_SEC_AES192_KEY_LENGTH); - print_buf("F9 Key", - &desc->ctl_desc.cipherHashInfo.infoAES192F9.authKey0, - sizeof(F9_t)); - break; - case XLR_SEC_VECTOR__CIPHER_AES192__F9__MODE_ECB_CBC_OFB: - DPRINT("VECTOR: XLR_SEC_VECTOR__CIPHER_AES192__F9__MODE_ECB_CBC_OFB\n"); - print_buf("CIPHER Key", - &desc->ctl_desc.cipherHashInfo.infoAES192F9.cipherKey0, - XLR_SEC_AES192_KEY_LENGTH); - print_buf("F9 Key", - &desc->ctl_desc.cipherHashInfo.infoAES192F9.authKey0, - sizeof(F9_t)); - break; - case XLR_SEC_VECTOR__CIPHER_AES256__F9__MODE_CTR_CFB: - DPRINT("VECTOR: XLR_SEC_VECTOR__CIPHER_AES256__F9__MODE_CTR_CFB \n"); - print_buf("CIPHER Key", - &desc->ctl_desc.cipherHashInfo.infoAES256F9.cipherKey0, - XLR_SEC_AES256_KEY_LENGTH); - print_buf("F9 Key", - &desc->ctl_desc.cipherHashInfo.infoAES256F9.authKey0, - sizeof(F9_t)); - break; - case XLR_SEC_VECTOR__CIPHER_AES256__F9__MODE_ECB_CBC_OFB: - DPRINT("VECTOR: XLR_SEC_VECTOR__CIPHER_AES256__F9__MODE_ECB_CBC_OFB \n"); - print_buf("CIPHER Key", - &desc->ctl_desc.cipherHashInfo.infoAES256F9.cipherKey0, - XLR_SEC_AES256_KEY_LENGTH); - print_buf("F9 Key", - &desc->ctl_desc.cipherHashInfo.infoAES256F9.authKey0, - sizeof(F9_t)); - break; - case XLR_SEC_VECTOR__CIPHER_AES128__HMAC__MODE_F8: - DPRINT("VECTOR: XLR_SEC_VECTOR__CIPHER_AES128__HMAC__MODE_F8 \n"); - print_buf("CIPHER Key", - &desc->ctl_desc.cipherHashInfo.infoAES128F8HMAC.cipherKey0, - XLR_SEC_AES128F8_KEY_LENGTH); - print_buf("HMAC Key", - &desc->ctl_desc.cipherHashInfo.infoAES128F8HMAC.hmacKey0, - sizeof(HMAC_t)); - break; - case XLR_SEC_VECTOR__CIPHER_AES128__MODE_F8: - DPRINT("VECTOR: XLR_SEC_VECTOR__CIPHER_AES128__MODE_F8 \n"); - print_buf("CIPHER Key", - &desc->ctl_desc.cipherHashInfo.infoAES128F8.cipherKey0, - XLR_SEC_AES128F8_KEY_LENGTH); - break; - case XLR_SEC_VECTOR__CIPHER_AES192__HMAC__MODE_F8: - DPRINT("VECTOR: XLR_SEC_VECTOR__CIPHER_AES192__HMAC__MODE_F8 \n"); - print_buf("CIPHER Key", - &desc->ctl_desc.cipherHashInfo.infoAES192F8HMAC.cipherKey0, - XLR_SEC_AES192F8_KEY_LENGTH); - print_buf("HMAC Key", - &desc->ctl_desc.cipherHashInfo.infoAES192F8HMAC.hmacKey0, - sizeof(HMAC_t)); - break; - case XLR_SEC_VECTOR__CIPHER_AES192__MODE_F8: - DPRINT("VECTOR: XLR_SEC_VECTOR__CIPHER_AES192__MODE_F8 \n"); - print_buf("CIPHER Key", - &desc->ctl_desc.cipherHashInfo.infoAES192F8.cipherKey0, - XLR_SEC_AES192F8_KEY_LENGTH); - break; - case XLR_SEC_VECTOR__CIPHER_AES256__HMAC__MODE_F8: - DPRINT("VECTOR: XLR_SEC_VECTOR__CIPHER_AES256__HMAC__MODE_F8 \n"); - print_buf("CIPHER Key", - &desc->ctl_desc.cipherHashInfo.infoAES256F8HMAC.cipherKey0, - XLR_SEC_AES256F8_KEY_LENGTH); - print_buf("HMAC Key", - &desc->ctl_desc.cipherHashInfo.infoAES256HMAC.hmacKey0, - sizeof(HMAC_t)); - break; - case XLR_SEC_VECTOR__CIPHER_AES256__MODE_F8: - DPRINT("VECTOR: XLR_SEC_VECTOR__CIPHER_AES256__MODE_F8 \n"); - print_buf("CIPHER Key", - &desc->ctl_desc.cipherHashInfo.infoAES256F8.cipherKey0, - XLR_SEC_AES256F8_KEY_LENGTH); - break; - case XLR_SEC_VECTOR__CIPHER_AES128__HMAC2__MODE_F8: - DPRINT("VECTOR: XLR_SEC_VECTOR__CIPHER_AES128__HMAC2__MODE_F8 \n"); - print_buf("CIPHER Key", - &desc->ctl_desc.cipherHashInfo.infoAES128F8HMAC2.cipherKey0, - XLR_SEC_AES128F8_KEY_LENGTH); - print_buf("HMAC2 Key", - &desc->ctl_desc.cipherHashInfo.infoAES128F8HMAC2.hmacKey0, - sizeof(HMAC2_t)); - break; - case XLR_SEC_VECTOR__CIPHER_AES192__HMAC2__MODE_F8: - DPRINT("VECTOR: XLR_SEC_VECTOR__CIPHER_AES192__HMAC2__MODE_F8 \n"); - print_buf("CIPHER Key", - &desc->ctl_desc.cipherHashInfo.infoAES192F8HMAC2.cipherKey0, - XLR_SEC_AES192F8_KEY_LENGTH); - print_buf("HMAC2 Key", - &desc->ctl_desc.cipherHashInfo.infoAES192F8HMAC2.hmacKey0, - sizeof(HMAC2_t)); - break; - case XLR_SEC_VECTOR__CIPHER_AES256__HMAC2__MODE_F8: - DPRINT("VECTOR: XLR_SEC_VECTOR__CIPHER_AES256__HMAC2__MODE_F8 \n"); - print_buf("CIPHER Key", - &desc->ctl_desc.cipherHashInfo.infoAES256F8HMAC2.cipherKey0, - XLR_SEC_AES256F8_KEY_LENGTH); - print_buf("HMAC2 Key", - &desc->ctl_desc.cipherHashInfo.infoAES256F8HMAC2.hmacKey0, - sizeof(HMAC2_t)); - break; - case XLR_SEC_VECTOR__CIPHER_AES128__GCM__MODE_F8: - DPRINT("VECTOR: XLR_SEC_VECTOR__CIPHER_AES128__GCM__MODE_F8 \n"); - print_buf("CIPHER Key", - &desc->ctl_desc.cipherHashInfo.infoAES128F8GCM.cipherKey0, - XLR_SEC_AES128F8_KEY_LENGTH); - print_buf("GCM Key", - &desc->ctl_desc.cipherHashInfo.infoAES128GCM.GCMH0, - XLR_SEC_AES128_KEY_LENGTH); - break; - case XLR_SEC_VECTOR__CIPHER_AES192__GCM__MODE_F8: - DPRINT("VECTOR: XLR_SEC_VECTOR__CIPHER_AES192__GCM__MODE_F8 \n"); - print_buf("CIPHER Key", - &desc->ctl_desc.cipherHashInfo.infoAES192F8GCM.cipherKey0, - XLR_SEC_AES192_KEY_LENGTH); - print_buf("GCM Key", - &desc->ctl_desc.cipherHashInfo.infoAES192F8GCM.GCMH0, - XLR_SEC_AES192_KEY_LENGTH); - break; - case XLR_SEC_VECTOR__CIPHER_AES256__GCM__MODE_F8: - DPRINT("VECTOR: XLR_SEC_VECTOR__CIPHER_AES256__GCM__MODE_F8 \n"); - print_buf("CIPHER Key", - &desc->ctl_desc.cipherHashInfo.infoAES256F8GCM.cipherKey0, - XLR_SEC_AES256F8_KEY_LENGTH); - print_buf("GCM Key", - &desc->ctl_desc.cipherHashInfo.infoAES256F8GCM.GCMH0, - XLR_SEC_AES256_KEY_LENGTH); - break; - case XLR_SEC_VECTOR__CIPHER_AES128__F9__MODE_F8: - DPRINT("VECTOR: XLR_SEC_VECTOR__CIPHER_AES128__F9__MODE_F8 \n"); - print_buf("CIPHER Key", - &desc->ctl_desc.cipherHashInfo.infoAES128F8F9.cipherKey0, - XLR_SEC_AES128F8_KEY_LENGTH); - print_buf("F9 Key", - &desc->ctl_desc.cipherHashInfo.infoAES128F8F9.authKey0, - sizeof(F9_t)); - break; - case XLR_SEC_VECTOR__CIPHER_AES192__F9__MODE_F8: - DPRINT("VECTOR: XLR_SEC_VECTOR__CIPHER_AES192__F9__MODE_F8 \n"); - print_buf("CIPHER Key", - &desc->ctl_desc.cipherHashInfo.infoAES192F8F9.cipherKey0, - XLR_SEC_AES192F8_KEY_LENGTH); - print_buf("F9 Key", - &desc->ctl_desc.cipherHashInfo.infoAES192F8F9.authKey0, - sizeof(F9_t)); - break; - case XLR_SEC_VECTOR__CIPHER_AES256__F9__MODE_F8: - DPRINT("VECTOR: XLR_SEC_VECTOR__CIPHER_AES256__F9__MODE_F8 \n"); - print_buf("CIPHER Key", - &desc->ctl_desc.cipherHashInfo.infoAES256F8F9.cipherKey0, - XLR_SEC_AES256F8_KEY_LENGTH); - print_buf("F9 Key", - &desc->ctl_desc.cipherHashInfo.infoAES256F8F9.authKey0, - sizeof(F9_t)); - break; - - default: - DPRINT("VECTOR: ???? \n"); - DPRINT(">>> WHAT THE HECK !!! <<< \n"); - break; - } - DPRINT("PACKET DESCRIPTOR: \n"); - word = 0; //desc->pkt_desc.srcLengthIVOffUseIVNext; - DPRINT("\tSrcLengthIVOffsetIVNext: %llx\n", word); - DPRINT("\t\tLoad HMAC = %lld \n", - GET_FIELD(word, PKT_DSC_LOADHMACKEY)); - DPRINT("\t\tPad Hash = %lld \n", - GET_FIELD(word, PKT_DSC_PADHASH)); - DPRINT("\t\tHash Byte Count = %lld \n", - GET_FIELD(word, PKT_DSC_HASHBYTES)); - DPRINT("\t\tNext = %lld \n", - GET_FIELD(word, PKT_DSC_NEXT)); - DPRINT("\t\tUse IV = %lld \n", - GET_FIELD(word, PKT_DSC_IV)); - DPRINT("\t\tIV Offset = %lld \n", - GET_FIELD(word, PKT_DSC_IVOFF)); - DPRINT("\t\tPacket Length = %lld \n", - GET_FIELD(word, PKT_DSC_PKTLEN)); - DPRINT("\t\tNLHMAC = %lld \n", GET_FIELD(word, PKT_DSC_NLHMAC)); - DPRINT("\t\tBreak = %lld \n", GET_FIELD(word, PKT_DSC_BREAK)); - DPRINT("\t\tWait = %lld \n", GET_FIELD(word, PKT_DSC_WAIT)); - DPRINT("\t\tSegment Src Addr = %llx \n", - (GET_FIELD(word, PKT_DSC_SEGADDR) << 5) & 0xffffffffffULL); - DPRINT("\t\tSRTCP = %lld \n", GET_FIELD(word, PKT_DSC_SRTCP)); - DPRINT("\t\tGlobal Src Offset = %lld \n", - GET_FIELD(word, PKT_DSC_SEGOFFSET)); - - word = 0; //desc->pkt_desc.dstDataSettings; - DPRINT("\tdstDataSettings: %llx \n", word); - DPRINT("\t\tArc4 Byte Count = %lld \n", GET_FIELD(word, - PKT_DSC_ARC4BYTECOUNT)); - DPRINT("\t\tSym Operation = %lld \n", GET_FIELD(word, PKT_DSC_SYM_OP)); - DPRINT("\t\tCipher Offset = %lld \n", GET_FIELD(word, PKT_DSC_CPHROFF)); - DPRINT("\t\tHash Offset = %lld \n", GET_FIELD(word, PKT_DSC_HASHOFF)); - DPRINT("\t\tHash Source = %lld \n", GET_FIELD(word, PKT_DSC_HASHSRC)); - DPRINT("\t\tChecksum Offset = %lld \n", GET_FIELD(word, - PKT_DSC_CKSUMOFF)); - DPRINT("\t\tChecksum Source = %lld \n", GET_FIELD(word, - PKT_DSC_CKSUMSRC)); - DPRINT("\t\tCipher Dest Addr = %llx \n", GET_FIELD(word, - PKT_DSC_CPHR_DST_ADDR)); - DPRINT("\t\tCipher Dest Dword = %lld \n", GET_FIELD(word, - PKT_DSC_CPHR_DST_DWOFFSET)); - DPRINT("\t\tCipher Dest Offset= %lld \n", GET_FIELD(word, - PKT_DSC_CPHR_DST_OFFSET)); - word = 0; //desc->pkt_desc.authDstNonceLow; - DPRINT("\tauthDstNonceLow: %llx \n", word); - DPRINT("\t\tNonce Low 24 = %lld \n", GET_FIELD(word, - PKT_DSC_NONCE_LOW)); - DPRINT("\t\tauthDst = %llx \n", GET_FIELD(word, - PKT_DSC_AUTH_DST_ADDR)); - DPRINT("\t\tCipher Offset High= %lld \n", GET_FIELD(word, - PKT_DSC_CIPH_OFF_HI)); - word = 0; //desc->pkt_desc.ckSumDstNonceHiCFBMaskLLWMask; - DPRINT("\tckSumDstNonceHiCFBMaskLLWMask: %llx \n", word); - DPRINT("\t\tHash Byte off = %lld \n", GET_FIELD(word, PKT_DSC_HASH_BYTE_OFF)); - DPRINT("\t\tPacket Len bytes = %lld \n", GET_FIELD(word, PKT_DSC_PKTLEN_BYTES)); - DPRINT("\t\tLast Long Word Mask = %lld \n", GET_FIELD(word, - PKT_DSC_LASTWORD)); - DPRINT("\t\tCipher Dst Address = %llx \n", GET_FIELD(word, - PKT_DSC_CPHR_DST_ADDR)); - DPRINT("\t\tGlobal Dst Offset = %lld \n", GET_FIELD(word, - PKT_DSC_CPHR_DST_OFFSET)); - - DPRINT("CFG_VECTOR = %04x\n", cfg_vector); - DPRINT("\n\n"); -} - -#endif - - - -/* This function is called from an interrupt handler */ -void -xlr_sec_msgring_handler(int bucket, int size, int code, int stid, - struct msgrng_msg *msg, void *data) -{ - uint64_t error; - uint64_t addr, sec_eng, sec_pipe; - xlr_sec_io_pt op = NULL; - symkey_desc_pt desc = NULL; - struct xlr_sec_session *ses = NULL; - struct xlr_sec_command *cmd = NULL; - uint32_t flags; - - if (code != MSGRNG_CODE_SEC) { - panic("xlr_sec_msgring_handler: bad code = %d," - " expected code = %d\n", - code, MSGRNG_CODE_SEC); - } - if ((stid < MSGRNG_STNID_SEC0) || (stid > MSGRNG_STNID_PK0)) { - panic("xlr_sec_msgring_handler: bad stn id = %d, expect %d - %d\n", - stid, MSGRNG_STNID_SEC0, MSGRNG_STNID_PK0); - } - /* - * The Submit() operation encodes the engine and pipe in these two - * separate fields. This allows use to verify the result type with - * the submitted operation type. - */ - sec_eng = GET_FIELD(msg->msg0, MSG_CTL_OP_TYPE); - sec_pipe = GET_FIELD(msg->msg1, MSG_CTL_OP_TYPE); - - error = msg->msg0 >> 40 & 0x1ff; - if (error) - printf("ctrl error = 0x%llx\n", error); - error = msg->msg1 >> 40 & 0x1ff; - if (error) - printf("data error = 0x%llx\n", error); - - - XLR_SEC_CMD_DIAG("[%s]: eng=%lld pipe=%lld\n", - __FUNCTION__, sec_eng, sec_pipe); - - /* Symmetric Key Operation ? */ - if (sec_eng == MSG0_CTL_OP_ENGINE_SYMKEY) { - - /* - * The data descriptor address allows us to associate the - * response with the submitted operation. Address is 40-bit - * cacheline aligned address. We need to zero bit 0-4 since - * they are used for the engine and pipe Id. - */ - addr = GET_FIELD(msg->msg1, MSG_RSLT_DATA_DSC_ADDR); - addr = addr & ~((1 << 5) - 1); - if (!addr) { - panic("[%s:STNID_SEC]: NULL symkey addr!\n", __FUNCTION__); - } - - /* - * The adddress points to the data descriptor. The operation - * descriptor is defined with the 32-byte cacheline size in - * mind. It allows the code to use this address to - * reference the symkey descriptor. (ref: xlr_sec_desc.h) - */ - addr = addr - sizeof(OperationDescriptor_t); - flags = xlr_enable_kx(); - desc = (symkey_desc_pt)(uintptr_t)xlr_paddr_ld(addr + - offsetof(OperationDescriptor_t, vaddr)); - xlr_restore_kx(flags); - - if (!desc) { - printf("\nerror : not getting desc back correctly \n"); - panic("[%s:STNID_SEC]: NULL symkey data descriptor!\n", __FUNCTION__); - } - ses = (struct xlr_sec_session *)desc->ses; - if (!ses) { - printf("\n error : not getting ses back correctly \n"); - panic("[%s:STNID_SEC]: NULL symkey data descriptor!\n", __FUNCTION__); - } - cmd = &ses->cmd; - if (!cmd) { - printf("\n error : not getting cmd back correctly \n"); - panic("[%s:STNID_SEC]: NULL symkey data descriptor!\n", __FUNCTION__); - } - op = &cmd->op; - if (!op) { - printf("\n error : not getting op back correctly \n"); - panic("[%s:STNID_SEC]: NULL symkey data descriptor!\n", __FUNCTION__); - } - XLR_SEC_CMD_DIAG("[%s:STNID_SEC]: addr=0x%llx desc=%p alloc=%p \n", - __FUNCTION__, addr, desc, desc->alloc); - - XLR_SEC_CMD_DIAG("[%s:STNID_SEC]: op_ctl=%p phys_self=%llx stn_id=%d \n", - __FUNCTION__, &desc->op_ctl, desc->op_ctl.phys_self, - desc->op_ctl.stn_id); - - if (addr != desc->op_ctl.phys_self) { - XLR_SEC_CMD_DIAG("[%s:STNID_SEC]: Control Descriptor fails Self-Verify !\n", - __FUNCTION__); - printf("[%s:STNID_SEC]: Control Descriptor fails Self-Verify !\n", - __FUNCTION__); - printf("[%s:STNID_SEC]: addr=0x%llx desc=%p alloc=%p \n", - __FUNCTION__, (unsigned long long)addr, desc, desc->alloc); - printf("[%s:STNID_SEC]: op_ctl=%p phys_self=%llx stn_id=%d \n", - __FUNCTION__, &desc->op_ctl, (unsigned long long)desc->op_ctl.phys_self, - desc->op_ctl.stn_id); - - } - if (desc->op_ctl.stn_id != MSGRNG_STNID_SEC0 && - desc->op_ctl.stn_id != MSGRNG_STNID_SEC1) { - XLR_SEC_CMD_DIAG("[%s:STNID_SEC]: Operation Type Mismatch !\n", - __FUNCTION__); - printf("[%s:STNID_SEC]: Operation Type Mismatch !\n", - __FUNCTION__); - printf("[%s:STNID_SEC]: addr=0x%llx desc=%p alloc=%p \n", - __FUNCTION__, (unsigned long long)addr, desc, desc->alloc); - printf("[%s:STNID_SEC]: op_ctl=%p phys_self=%llx stn_id=%d \n", - __FUNCTION__, &desc->op_ctl, (unsigned long long)desc->op_ctl.phys_self, - desc->op_ctl.stn_id); - } - desc->ctl_result = GET_FIELD(msg->msg0, MSG_RSLT_CTL_INST_ERR); - desc->data_result = GET_FIELD(msg->msg1, MSG_RSLT_DATA_INST_ERR); - - XLR_SEC_CMD_DIAG("[%s:STNID_SEC]: cpu=%d ctl_result=0x%llx data_result=%llx\n", - __FUNCTION__, desc->op_ctl.cpu, - desc->ctl_result, desc->data_result); - - } -#if 0 - else if (sec_eng == MSG0_CTL_OP_ENGINE_PUBKEY) { - pubkey_desc_pt desc; - - if (sec_pipe != MSG1_CTL_OP_PUBKEY_PIPE0) { - /* response to uc load */ - /* - * XLR_SEC_CMD_DIAG("[%s:STNID_SEC]: ecc cpu=%d - * ctl_result=0x%llx data_result=%llx\n", - * __FUNCTION__, desc->op_ctl.cpu, desc->ctl_result, - * desc->data_result); - */ - return; - } - /* - * The data descriptor address allows us to associate the - * response with the submitted operation. Address is 40-bit - * cacheline aligned address. We need to zero bit 0-4 since - * they are used for the engine and pipe Id. - */ - addr = GET_FIELD(msg->msg0, PUBKEY_RSLT_CTL_SRCADDR); - addr = addr & ~((1 << 5) - 1); - if (!addr) { - panic("[%s:STNID_SEC]: NULL pubkey ctrl desc!\n", __FUNCTION__); - } - /* - * The adddress points to the data descriptor. The operation - * descriptor is defined with the 32-byte cacheline size in - * mind. It allows the code to use this address to - * reference the symkey descriptor. (ref: xlr_sec_desc.h) - */ - addr = addr - sizeof(OperationDescriptor_t); - - /* Get pointer to pubkey Descriptor */ - desc = (pubkey_desc_pt) (unsigned long)addr; - if (!desc) { - panic("[%s:STNID_SEC]: NULL pubkey data descriptor!\n", __FUNCTION__); - } - XLR_SEC_CMD_DIAG("[%s:STNID_PK0]: addr=0x%llx desc=%p alloc=%p \n", - __FUNCTION__, addr, desc, desc->alloc); - - XLR_SEC_CMD_DIAG("[%s:STNID_PK0]: op_ctl=%p phys_self=%llx stn_id=%d \n", - __FUNCTION__, &desc->op_ctl, desc->op_ctl.phys_self, - desc->op_ctl.stn_id); - - if (addr != desc->op_ctl.phys_self) { - XLR_SEC_CMD_DIAG("[%s:STNID_PK0]: Control Descriptor fails Self-Verify !\n", - __FUNCTION__); - } - if (desc->op_ctl.stn_id != msgrng_stnid_pk0) { - XLR_SEC_CMD_DIAG("[%s:STNID_PK0]: Operation Type Mismatch ! \n", - __FUNCTION__); - } - desc->ctl_result = GET_FIELD(msg->msg0, PUBKEY_RSLT_CTL_ERROR); - desc->data_result = GET_FIELD(msg->msg1, PUBKEY_RSLT_DATA_ERROR); - - XLR_SEC_CMD_DIAG("[%s:STNID_PK0]: ctl_result=0x%llx data_result=%llx\n", - __FUNCTION__, desc->ctl_result, desc->data_result); - - } -#endif - else { - printf("[%s]: HANDLER bad id = %d\n", __FUNCTION__, stid); - } -#ifdef RMI_SEC_DEBUG - if (ses->multi_frag_flag) { - int i; - char *ptr; - - printf("\n RETURNED DATA: \n"); - - ptr = (char *)(unsigned long)(desc->user.aligned_dest + cmd->op.cipher_offset); - for (i = 0; i < SEC_MAX_FRAG_LEN; i++) { - printf("%c ", (char)*ptr++); - if ((i % 10) == 0) - printf("\n"); - } - - printf("second desc\n"); - ptr = (char *)(unsigned long)(desc->next_dest_buf); - for (i = 0; i < desc->next_src_len; i++) { - printf("%c ", (char)*ptr++); - if ((i % 10) == 0) - printf("\n"); - } - } -#endif - - /* Copy cipher-data to User-space */ - if (op->cipher_type != XLR_SEC_CIPHER_TYPE_NONE) { - size = op->dest_buf_size; - - /* DEBUG -dpk */ - XLR_SEC_CMD_DIAG("cipher: to_addr=%p from_addr=%p size=%d \n", - desc->user.user_dest, desc->user.aligned_dest, size); - - if (ses->multi_frag_flag) { - crypto_copyback(cmd->crp->crp_flags, cmd->crp->crp_buf, 0, - SEC_MAX_FRAG_LEN, (caddr_t)(long)desc->user.aligned_dest + op->cipher_offset); - crypto_copyback(cmd->crp->crp_flags, cmd->crp->crp_buf + SEC_MAX_FRAG_LEN, 0, - desc->next_src_len, (caddr_t)(long)desc->next_dest_buf); - crypto_done(cmd->crp); - } else { - crypto_copyback(cmd->crp->crp_flags, cmd->crp->crp_buf, 0, - cmd->op.dest_buf_size, (caddr_t)(long)desc->user.aligned_dest + op->cipher_offset); - crypto_done(cmd->crp); - } - - } - - /* Copy digest to User-space */ - if (op->digest_type != XLR_SEC_DIGEST_TYPE_NONE) { - int offset = 0; - - switch (op->digest_type) { - case XLR_SEC_DIGEST_TYPE_MD5: - size = XLR_SEC_MD5_LENGTH; - break; - case XLR_SEC_DIGEST_TYPE_SHA1: - size = XLR_SEC_SHA1_LENGTH; - break; - case XLR_SEC_DIGEST_TYPE_SHA256: - size = XLR_SEC_SHA256_LENGTH; - break; - case XLR_SEC_DIGEST_TYPE_SHA384: - size = XLR_SEC_SHA384_LENGTH; - break; - case XLR_SEC_DIGEST_TYPE_SHA512: - size = XLR_SEC_SHA512_LENGTH; - break; - case XLR_SEC_DIGEST_TYPE_GCM: - size = XLR_SEC_GCM_LENGTH; - break; - case XLR_SEC_DIGEST_TYPE_KASUMI_F9: - offset = 4; - size = XLR_SEC_KASUMI_F9_RESULT_LENGTH; - break; - default: - size = 0; - } - - XLR_SEC_CMD_DIAG("digest: to_addr=%p from_addr=%p size=%d \n", - desc->user.user_auth, desc->user.aligned_auth, size); - memcpy(desc->user.user_auth, desc->user.aligned_auth + offset, size); - op->auth_dest = (uint64_t) (unsigned long)desc->user.user_auth; - } - if (op->cipher_type == XLR_SEC_CIPHER_TYPE_ARC4 && - op->rc4_savestate) { - size = XLR_SEC_MAX_RC4_STATE_SIZE; - - XLR_SEC_CMD_DIAG("state: to_addr=%p from_addr=%p size=%d \n", - desc->user.user_state, desc->user.aligned_state, size); - op->rc4_state = (uint64_t) (unsigned long)desc->user.user_state; - } - return; -} Property changes on: head/sys/mips/rmi/dev/sec/rmilib.c ___________________________________________________________________ Deleted: svn:eol-style ## -1 +0,0 ## -native \ No newline at end of property Deleted: svn:keywords ## -1 +0,0 ## -FreeBSD=%H \ No newline at end of property Deleted: svn:mime-type ## -1 +0,0 ## -text/plain \ No newline at end of property Index: head/sys/mips/rmi/dev/sec/rmilib.h =================================================================== --- head/sys/mips/rmi/dev/sec/rmilib.h (revision 327460) +++ head/sys/mips/rmi/dev/sec/rmilib.h (nonexistent) @@ -1,1002 +0,0 @@ -/*- - * SPDX-License-Identifier: BSD-3-Clause - * - * Copyright (c) 2003-2009 RMI Corporation - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. Neither the name of RMI Corporation, nor the names of its contributors, - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - * - * $FreeBSD$ - * RMI_BSD - */ - -#ifndef _RMILIB_H_ -#define _RMILIB_H_ - -#include -#include -#include - -/* #define XLR_SEC_CMD_DEBUG */ - -#ifdef XLR_SEC_CMD_DEBUG -#define DPRINT printf -#define XLR_SEC_CMD_DIAG(fmt, args...) { \ - DPRINT(fmt, ##args); \ - } -#define XLR_SEC_CMD_DIAG_SYM_DESC(desc, vec) { \ - decode_symkey_desc ((desc), (vec)); \ - } -#else -#define DPRINT(fmt, args...) -#define XLR_SEC_CMD_DIAG(fmt, args...) -#define XLR_SEC_CMD_DIAG_SYM_DESC(desc, vec) -#endif - - - - - - -/* -#include - -#define OS_ALLOC_KERNEL(size) kmalloc((size), GFP_KERNEL) -#define virt_to_phys(x) vtophys((vm_offset_t)(x)) -*/ -/* - * Cryptographic parameter definitions - */ -#define XLR_SEC_DES_KEY_LENGTH 8 /* Bytes */ -#define XLR_SEC_3DES_KEY_LENGTH 24 /* Bytes */ -#define XLR_SEC_AES128_KEY_LENGTH 16 /* Bytes */ -#define XLR_SEC_AES192_KEY_LENGTH 24 /* Bytes */ -#define XLR_SEC_AES256_KEY_LENGTH 32 /* Bytes */ -#define XLR_SEC_AES128F8_KEY_LENGTH 32 /* Bytes */ -#define XLR_SEC_AES192F8_KEY_LENGTH 48 /* Bytes */ -#define XLR_SEC_AES256F8_KEY_LENGTH 64 /* Bytes */ -#define XLR_SEC_KASUMI_F8_KEY_LENGTH 16 /* Bytes */ -#define XLR_SEC_MAX_CRYPT_KEY_LENGTH XLR_SEC_AES256F8_KEY_LENGTH - - -#define XLR_SEC_DES_IV_LENGTH 8 /* Bytes */ -#define XLR_SEC_AES_IV_LENGTH 16 /* Bytes */ -#define XLR_SEC_ARC4_IV_LENGTH 0 /* Bytes */ -#define XLR_SEC_KASUMI_F8_IV_LENGTH 16 /* Bytes */ -#define XLR_SEC_MAX_IV_LENGTH 16 /* Bytes */ -#define XLR_SEC_IV_LENGTH_BYTES 8 /* Bytes */ - -#define XLR_SEC_AES_BLOCK_SIZE 16 /* Bytes */ -#define XLR_SEC_DES_BLOCK_SIZE 8 /* Bytes */ -#define XLR_SEC_3DES_BLOCK_SIZE 8 /* Bytes */ - -#define XLR_SEC_MD5_BLOCK_SIZE 64 /* Bytes */ -#define XLR_SEC_SHA1_BLOCK_SIZE 64 /* Bytes */ -#define XLR_SEC_SHA256_BLOCK_SIZE 64 /* Bytes */ -#define XLR_SEC_SHA384_BLOCK_SIZE 128 /* Bytes */ -#define XLR_SEC_SHA512_BLOCK_SIZE 128 /* Bytes */ -#define XLR_SEC_GCM_BLOCK_SIZE 16 /* XXX: Bytes */ -#define XLR_SEC_KASUMI_F9_BLOCK_SIZE 16 /* XXX: Bytes */ -#define XLR_SEC_MAX_BLOCK_SIZE 64 /* Max of MD5/SHA */ -#define XLR_SEC_MD5_LENGTH 16 /* Bytes */ -#define XLR_SEC_SHA1_LENGTH 20 /* Bytes */ -#define XLR_SEC_SHA256_LENGTH 32 /* Bytes */ -#define XLR_SEC_SHA384_LENGTH 64 /* Bytes */ -#define XLR_SEC_SHA512_LENGTH 64 /* Bytes */ -#define XLR_SEC_GCM_LENGTH 16 /* Bytes */ -#define XLR_SEC_KASUMI_F9_LENGTH 16 /* Bytes */ -#define XLR_SEC_KASUMI_F9_RESULT_LENGTH 4 /* Bytes */ -#define XLR_SEC_HMAC_LENGTH 64 /* Max of MD5/SHA/SHA256 */ -#define XLR_SEC_MAX_AUTH_KEY_LENGTH XLR_SEC_SHA512_BLOCK_SIZE -#define XLR_SEC_MAX_RC4_STATE_SIZE 264 /* char s[256], int i, int j */ - -/* Status code is used by the SRL to indicate status */ -typedef unsigned int xlr_sec_status_t; - -/* - * Status codes - */ -#define XLR_SEC_STATUS_SUCCESS 0 -#define XLR_SEC_STATUS_NO_DEVICE -1 -#define XLR_SEC_STATUS_TIMEOUT -2 -#define XLR_SEC_STATUS_INVALID_PARAMETER -3 -#define XLR_SEC_STATUS_DEVICE_FAILED -4 -#define XLR_SEC_STATUS_DEVICE_BUSY -5 -#define XLR_SEC_STATUS_NO_RESOURCE -6 -#define XLR_SEC_STATUS_CANCELLED -7 - -/* - * Flags - */ -#define XLR_SEC_FLAGS_HIGH_PRIORITY 1 - -/* Error code is used to indicate any errors */ -typedef int xlr_sec_error_t; - -/* - */ -#define XLR_SEC_ERR_NONE 0 -#define XLR_SEC_ERR_CIPHER_OP -1 -#define XLR_SEC_ERR_CIPHER_TYPE -2 -#define XLR_SEC_ERR_CIPHER_MODE -3 -#define XLR_SEC_ERR_CIPHER_INIT -4 -#define XLR_SEC_ERR_DIGEST_TYPE -5 -#define XLR_SEC_ERR_DIGEST_INIT -6 -#define XLR_SEC_ERR_DIGEST_SRC -7 -#define XLR_SEC_ERR_CKSUM_TYPE -8 -#define XLR_SEC_ERR_CKSUM_SRC -9 -#define XLR_SEC_ERR_ALLOC -10 -#define XLR_SEC_ERR_CONTROL_VECTOR -11 -#define XLR_SEC_ERR_LOADHMACKEY_MODE -12 -#define XLR_SEC_ERR_PADHASH_MODE -13 -#define XLR_SEC_ERR_HASHBYTES_MODE -14 -#define XLR_SEC_ERR_NEXT_MODE -15 -#define XLR_SEC_ERR_PKT_IV_MODE -16 -#define XLR_SEC_ERR_LASTWORD_MODE -17 -#define XLR_SEC_ERR_PUBKEY_OP -18 -#define XLR_SEC_ERR_SYMKEY_MSGSND -19 -#define XLR_SEC_ERR_PUBKEY_MSGSND -20 -#define XLR_SEC_ERR_SYMKEY_GETSEM -21 -#define XLR_SEC_ERR_PUBKEY_GETSEM -22 - -/* - * Descriptor Vector quantities - * (helps to identify descriptor type per operation) - */ -#define XLR_SEC_VECTOR_CIPHER_DES 0x0001 -#define XLR_SEC_VECTOR_CIPHER_3DES 0x0002 -#define XLR_SEC_VECTOR_CIPHER_AES128 0x0004 -#define XLR_SEC_VECTOR_CIPHER_AES192 0x0008 -#define XLR_SEC_VECTOR_CIPHER_AES256 0x0010 -#define XLR_SEC_VECTOR_CIPHER_ARC4 0x0020 -#define XLR_SEC_VECTOR_CIPHER_AES (XLR_SEC_VECTOR_CIPHER_AES128 | \ - XLR_SEC_VECTOR_CIPHER_AES192 | \ - XLR_SEC_VECTOR_CIPHER_AES256) -#define XLR_SEC_VECTOR_CIPHER (XLR_SEC_VECTOR_CIPHER_DES | \ - XLR_SEC_VECTOR_CIPHER_3DES | \ - XLR_SEC_VECTOR_CIPHER_AES128 | \ - XLR_SEC_VECTOR_CIPHER_AES192 | \ - XLR_SEC_VECTOR_CIPHER_AES256 | \ - XLR_SEC_VECTOR_CIPHER_ARC4) - -#define XLR_SEC_VECTOR_HMAC 0x0040 -#define XLR_SEC_VECTOR_MAC 0x0080 -#define XLR_SEC_VECTOR_MODE_CTR_CFB 0x0100 -#define XLR_SEC_VECTOR_MODE_ECB_CBC_OFB 0x0200 -#define XLR_SEC_VECTOR_MODE_ECB_CBC 0x0400 -#define XLR_SEC_VECTOR_STATE 0x0800 -#define XLR_SEC_VECTOR_CIPHER_KASUMI_F8 0x01000 -#define XLR_SEC_VECTOR_HMAC2 0x02000 -#define XLR_SEC_VECTOR_GCM 0x04000 -#define XLR_SEC_VECTOR_F9 0x08000 -#define XLR_SEC_VECTOR_MODE_F8 0x10000 - -#define XLR_SEC_VECTOR_CIPHER_ARC4__HMAC \ -(XLR_SEC_VECTOR_CIPHER_ARC4 | XLR_SEC_VECTOR_HMAC) -#define XLR_SEC_VECTOR_CIPHER_ARC4__STATE \ -(XLR_SEC_VECTOR_CIPHER_ARC4 | XLR_SEC_VECTOR_STATE) -#define XLR_SEC_VECTOR_CIPHER_ARC4__HMAC__STATE \ -(XLR_SEC_VECTOR_CIPHER_ARC4 | XLR_SEC_VECTOR_HMAC | XLR_SEC_VECTOR_STATE) - -#define XLR_SEC_VECTOR__CIPHER_DES__HMAC__MODE_ECB_CBC \ -(XLR_SEC_VECTOR_CIPHER_DES | XLR_SEC_VECTOR_HMAC | XLR_SEC_VECTOR_MODE_ECB_CBC) - -#define XLR_SEC_VECTOR__CIPHER_DES__MODE_ECB_CBC \ -(XLR_SEC_VECTOR_CIPHER_DES | XLR_SEC_VECTOR_MODE_ECB_CBC) - -#define XLR_SEC_VECTOR__CIPHER_3DES__HMAC__MODE_ECB_CBC \ -(XLR_SEC_VECTOR_CIPHER_3DES | XLR_SEC_VECTOR_HMAC | XLR_SEC_VECTOR_MODE_ECB_CBC) - -#define XLR_SEC_VECTOR__CIPHER_3DES__MODE_ECB_CBC \ -(XLR_SEC_VECTOR_CIPHER_3DES | XLR_SEC_VECTOR_MODE_ECB_CBC) - -#define XLR_SEC_VECTOR__CIPHER_AES128__HMAC__MODE_CTR_CFB \ -(XLR_SEC_VECTOR_CIPHER_AES128 | XLR_SEC_VECTOR_HMAC | XLR_SEC_VECTOR_MODE_CTR_CFB) - -#define XLR_SEC_VECTOR__CIPHER_AES128__MODE_CTR_CFB \ -(XLR_SEC_VECTOR_CIPHER_AES128 | XLR_SEC_VECTOR_MODE_CTR_CFB) - -#define XLR_SEC_VECTOR__CIPHER_AES128__HMAC__MODE_ECB_CBC_OFB \ -(XLR_SEC_VECTOR_CIPHER_AES128 | XLR_SEC_VECTOR_HMAC | XLR_SEC_VECTOR_MODE_ECB_CBC_OFB) - -#define XLR_SEC_VECTOR__CIPHER_AES128__MODE_ECB_CBC_OFB \ -(XLR_SEC_VECTOR_CIPHER_AES128 | XLR_SEC_VECTOR_MODE_ECB_CBC_OFB) - -#define XLR_SEC_VECTOR__CIPHER_AES192__HMAC__MODE_CTR_CFB \ -(XLR_SEC_VECTOR_CIPHER_AES192 | XLR_SEC_VECTOR_HMAC | XLR_SEC_VECTOR_MODE_CTR_CFB) - -#define XLR_SEC_VECTOR__CIPHER_AES192__MODE_CTR_CFB \ -(XLR_SEC_VECTOR_CIPHER_AES192 | XLR_SEC_VECTOR_MODE_CTR_CFB) - -#define XLR_SEC_VECTOR__CIPHER_AES192__HMAC__MODE_ECB_CBC_OFB \ -(XLR_SEC_VECTOR_CIPHER_AES192 | XLR_SEC_VECTOR_HMAC | XLR_SEC_VECTOR_MODE_ECB_CBC_OFB) - -#define XLR_SEC_VECTOR__CIPHER_AES192__MODE_ECB_CBC_OFB \ -(XLR_SEC_VECTOR_CIPHER_AES192 | XLR_SEC_VECTOR_MODE_ECB_CBC_OFB) - -#define XLR_SEC_VECTOR__CIPHER_AES256__HMAC__MODE_CTR_CFB \ -(XLR_SEC_VECTOR_CIPHER_AES256 | XLR_SEC_VECTOR_HMAC | XLR_SEC_VECTOR_MODE_CTR_CFB) - -#define XLR_SEC_VECTOR__CIPHER_AES256__MODE_CTR_CFB \ -(XLR_SEC_VECTOR_CIPHER_AES256 | XLR_SEC_VECTOR_MODE_CTR_CFB) - -#define XLR_SEC_VECTOR__CIPHER_AES256__HMAC__MODE_ECB_CBC_OFB \ -(XLR_SEC_VECTOR_CIPHER_AES256 | XLR_SEC_VECTOR_HMAC | XLR_SEC_VECTOR_MODE_ECB_CBC_OFB) - -#define XLR_SEC_VECTOR__CIPHER_AES256__MODE_ECB_CBC_OFB \ -(XLR_SEC_VECTOR_CIPHER_AES256 | XLR_SEC_VECTOR_MODE_ECB_CBC_OFB) - -#define XLR_SEC_VECTOR__CIPHER_AES128__HMAC__MODE_F8 \ -(XLR_SEC_VECTOR_CIPHER_AES128 | XLR_SEC_VECTOR_HMAC | XLR_SEC_VECTOR_MODE_F8) - -#define XLR_SEC_VECTOR__CIPHER_AES128__MODE_F8 \ -(XLR_SEC_VECTOR_CIPHER_AES128 | XLR_SEC_VECTOR_MODE_F8) - -#define XLR_SEC_VECTOR__CIPHER_AES192__HMAC__MODE_F8 \ -(XLR_SEC_VECTOR_CIPHER_AES192 | XLR_SEC_VECTOR_HMAC | XLR_SEC_VECTOR_MODE_F8) - -#define XLR_SEC_VECTOR__CIPHER_AES192__MODE_F8 \ -(XLR_SEC_VECTOR_CIPHER_AES192 | XLR_SEC_VECTOR_MODE_F8) - -#define XLR_SEC_VECTOR__CIPHER_AES256__HMAC__MODE_F8 \ -(XLR_SEC_VECTOR_CIPHER_AES256 | XLR_SEC_VECTOR_HMAC | XLR_SEC_VECTOR_MODE_F8) - -#define XLR_SEC_VECTOR__CIPHER_AES256__MODE_F8 \ -(XLR_SEC_VECTOR_CIPHER_AES256 | XLR_SEC_VECTOR_MODE_F8) - -#define XLR_SEC_VECTOR_CIPHER_KASUMI_F8__F9 \ -(XLR_SEC_VECTOR_CIPHER_KASUMI_F8 | XLR_SEC_VECTOR_F9) - -#define XLR_SEC_VECTOR_CIPHER_KASUMI_F8__HMAC \ -(XLR_SEC_VECTOR_CIPHER_KASUMI_F8 | XLR_SEC_VECTOR_HMAC) - -#define XLR_SEC_VECTOR_CIPHER_KASUMI_F8__HMAC2 \ -(XLR_SEC_VECTOR_CIPHER_KASUMI_F8 | XLR_SEC_VECTOR_HMAC2) - -#define XLR_SEC_VECTOR_CIPHER_KASUMI_F8__GCM \ -(XLR_SEC_VECTOR_CIPHER_KASUMI_F8 | XLR_SEC_VECTOR_GCM) - -#define XLR_SEC_VECTOR_CIPHER_ARC4__HMAC2 \ -(XLR_SEC_VECTOR_CIPHER_ARC4 | XLR_SEC_VECTOR_HMAC2) - -#define XLR_SEC_VECTOR_CIPHER_ARC4__HMAC2__STATE \ -(XLR_SEC_VECTOR_CIPHER_ARC4 | XLR_SEC_VECTOR_HMAC2 | XLR_SEC_VECTOR_STATE) - -#define XLR_SEC_VECTOR__CIPHER_DES__HMAC2__MODE_ECB_CBC \ -(XLR_SEC_VECTOR_CIPHER_DES | XLR_SEC_VECTOR_HMAC2 | XLR_SEC_VECTOR_MODE_ECB_CBC) - -#define XLR_SEC_VECTOR__CIPHER_3DES__HMAC2__MODE_ECB_CBC \ -(XLR_SEC_VECTOR_CIPHER_3DES | XLR_SEC_VECTOR_HMAC2 | XLR_SEC_VECTOR_MODE_ECB_CBC) - -#define XLR_SEC_VECTOR__CIPHER_AES128__HMAC2__MODE_CTR_CFB \ -(XLR_SEC_VECTOR_CIPHER_AES128 | XLR_SEC_VECTOR_HMAC2 | XLR_SEC_VECTOR_MODE_CTR_CFB) - -#define XLR_SEC_VECTOR__CIPHER_AES128__HMAC2__MODE_ECB_CBC_OFB \ -(XLR_SEC_VECTOR_CIPHER_AES128 | XLR_SEC_VECTOR_HMAC2 | XLR_SEC_VECTOR_MODE_ECB_CBC_OFB) - -#define XLR_SEC_VECTOR__CIPHER_AES192__HMAC2__MODE_CTR_CFB \ -(XLR_SEC_VECTOR_CIPHER_AES192 | XLR_SEC_VECTOR_HMAC2 | XLR_SEC_VECTOR_MODE_CTR_CFB) - -#define XLR_SEC_VECTOR__CIPHER_AES192__HMAC2__MODE_ECB_CBC_OFB \ -(XLR_SEC_VECTOR_CIPHER_AES192 | XLR_SEC_VECTOR_HMAC2 | XLR_SEC_VECTOR_MODE_ECB_CBC_OFB) - -#define XLR_SEC_VECTOR__CIPHER_AES256__HMAC2__MODE_CTR_CFB \ -(XLR_SEC_VECTOR_CIPHER_AES256 | XLR_SEC_VECTOR_HMAC2 | XLR_SEC_VECTOR_MODE_CTR_CFB) - -#define XLR_SEC_VECTOR__CIPHER_AES256__HMAC2__MODE_ECB_CBC_OFB \ -(XLR_SEC_VECTOR_CIPHER_AES256 | XLR_SEC_VECTOR_HMAC2 | XLR_SEC_VECTOR_MODE_ECB_CBC_OFB) - -#define XLR_SEC_VECTOR__CIPHER_AES128__HMAC2__MODE_F8 \ -(XLR_SEC_VECTOR_CIPHER_AES128 | XLR_SEC_VECTOR_HMAC2 | XLR_SEC_VECTOR_MODE_F8) - -#define XLR_SEC_VECTOR__CIPHER_AES192__HMAC2__MODE_F8 \ -(XLR_SEC_VECTOR_CIPHER_AES192 | XLR_SEC_VECTOR_HMAC2 | XLR_SEC_VECTOR_MODE_F8) - -#define XLR_SEC_VECTOR__CIPHER_AES256__HMAC2__MODE_F8 \ -(XLR_SEC_VECTOR_CIPHER_AES256 | XLR_SEC_VECTOR_HMAC2 | XLR_SEC_VECTOR_MODE_F8) - -#define XLR_SEC_VECTOR_CIPHER_ARC4__GCM \ -(XLR_SEC_VECTOR_CIPHER_ARC4 | XLR_SEC_VECTOR_GCM) - -#define XLR_SEC_VECTOR_CIPHER_ARC4__GCM__STATE \ -(XLR_SEC_VECTOR_CIPHER_ARC4 | XLR_SEC_VECTOR_GCM | XLR_SEC_VECTOR_STATE) - -#define XLR_SEC_VECTOR__CIPHER_DES__GCM__MODE_ECB_CBC \ -(XLR_SEC_VECTOR_CIPHER_DES | XLR_SEC_VECTOR_GCM | XLR_SEC_VECTOR_MODE_ECB_CBC) - -#define XLR_SEC_VECTOR__CIPHER_3DES__GCM__MODE_ECB_CBC \ -(XLR_SEC_VECTOR_CIPHER_3DES | XLR_SEC_VECTOR_GCM | XLR_SEC_VECTOR_MODE_ECB_CBC) - -#define XLR_SEC_VECTOR__CIPHER_AES128__GCM__MODE_CTR_CFB \ -(XLR_SEC_VECTOR_CIPHER_AES128 | XLR_SEC_VECTOR_GCM | XLR_SEC_VECTOR_MODE_CTR_CFB) - -#define XLR_SEC_VECTOR__CIPHER_AES128__GCM__MODE_ECB_CBC_OFB \ -(XLR_SEC_VECTOR_CIPHER_AES128 | XLR_SEC_VECTOR_GCM | XLR_SEC_VECTOR_MODE_ECB_CBC_OFB) - -#define XLR_SEC_VECTOR__CIPHER_AES192__GCM__MODE_CTR_CFB \ -(XLR_SEC_VECTOR_CIPHER_AES192 | XLR_SEC_VECTOR_GCM | XLR_SEC_VECTOR_MODE_CTR_CFB) - -#define XLR_SEC_VECTOR__CIPHER_AES192__GCM__MODE_ECB_CBC_OFB \ -(XLR_SEC_VECTOR_CIPHER_AES192 | XLR_SEC_VECTOR_GCM | XLR_SEC_VECTOR_MODE_ECB_CBC_OFB) - -#define XLR_SEC_VECTOR__CIPHER_AES256__GCM__MODE_CTR_CFB \ -(XLR_SEC_VECTOR_CIPHER_AES256 | XLR_SEC_VECTOR_GCM | XLR_SEC_VECTOR_MODE_CTR_CFB) - -#define XLR_SEC_VECTOR__CIPHER_AES256__GCM__MODE_ECB_CBC_OFB \ -(XLR_SEC_VECTOR_CIPHER_AES256 | XLR_SEC_VECTOR_GCM | XLR_SEC_VECTOR_MODE_ECB_CBC_OFB) - -#define XLR_SEC_VECTOR__CIPHER_AES128__GCM__MODE_F8 \ -(XLR_SEC_VECTOR_CIPHER_AES128 | XLR_SEC_VECTOR_GCM | XLR_SEC_VECTOR_MODE_F8) - -#define XLR_SEC_VECTOR__CIPHER_AES192__GCM__MODE_F8 \ -(XLR_SEC_VECTOR_CIPHER_AES192 | XLR_SEC_VECTOR_GCM | XLR_SEC_VECTOR_MODE_F8) - -#define XLR_SEC_VECTOR__CIPHER_AES256__GCM__MODE_F8 \ -(XLR_SEC_VECTOR_CIPHER_AES256 | XLR_SEC_VECTOR_GCM | XLR_SEC_VECTOR_MODE_F8) - -#define XLR_SEC_VECTOR_CIPHER_ARC4__F9 \ -(XLR_SEC_VECTOR_CIPHER_ARC4 | XLR_SEC_VECTOR_F9) - -#define XLR_SEC_VECTOR_CIPHER_ARC4__F9__STATE \ -(XLR_SEC_VECTOR_CIPHER_ARC4 | XLR_SEC_VECTOR_F9 | XLR_SEC_VECTOR_STATE) - -#define XLR_SEC_VECTOR__CIPHER_DES__F9__MODE_ECB_CBC \ -(XLR_SEC_VECTOR_CIPHER_DES | XLR_SEC_VECTOR_F9 | XLR_SEC_VECTOR_MODE_ECB_CBC) - -#define XLR_SEC_VECTOR__CIPHER_3DES__F9__MODE_ECB_CBC \ -(XLR_SEC_VECTOR_CIPHER_3DES | XLR_SEC_VECTOR_F9 | XLR_SEC_VECTOR_MODE_ECB_CBC) - -#define XLR_SEC_VECTOR__CIPHER_AES128__F9__MODE_CTR_CFB \ -(XLR_SEC_VECTOR_CIPHER_AES128 | XLR_SEC_VECTOR_F9 | XLR_SEC_VECTOR_MODE_CTR_CFB) - -#define XLR_SEC_VECTOR__CIPHER_AES128__F9__MODE_ECB_CBC_OFB \ -(XLR_SEC_VECTOR_CIPHER_AES128 | XLR_SEC_VECTOR_F9 | XLR_SEC_VECTOR_MODE_ECB_CBC_OFB) - -#define XLR_SEC_VECTOR__CIPHER_AES192__F9__MODE_CTR_CFB \ -(XLR_SEC_VECTOR_CIPHER_AES192 | XLR_SEC_VECTOR_F9 | XLR_SEC_VECTOR_MODE_CTR_CFB) - -#define XLR_SEC_VECTOR__CIPHER_AES192__F9__MODE_ECB_CBC_OFB \ -(XLR_SEC_VECTOR_CIPHER_AES192 | XLR_SEC_VECTOR_F9 | XLR_SEC_VECTOR_MODE_ECB_CBC_OFB) - -#define XLR_SEC_VECTOR__CIPHER_AES256__F9__MODE_CTR_CFB \ -(XLR_SEC_VECTOR_CIPHER_AES256 | XLR_SEC_VECTOR_F9 | XLR_SEC_VECTOR_MODE_CTR_CFB) - -#define XLR_SEC_VECTOR__CIPHER_AES256__F9__MODE_ECB_CBC_OFB \ -(XLR_SEC_VECTOR_CIPHER_AES256 | XLR_SEC_VECTOR_F9 | XLR_SEC_VECTOR_MODE_ECB_CBC_OFB) - -#define XLR_SEC_VECTOR__CIPHER_AES128__F9__MODE_F8 \ -(XLR_SEC_VECTOR_CIPHER_AES128 | XLR_SEC_VECTOR_F9 | XLR_SEC_VECTOR_MODE_F8) - -#define XLR_SEC_VECTOR__CIPHER_AES192__F9__MODE_F8 \ -(XLR_SEC_VECTOR_CIPHER_AES192 | XLR_SEC_VECTOR_F9 | XLR_SEC_VECTOR_MODE_F8) - -#define XLR_SEC_VECTOR__CIPHER_AES256__F9__MODE_F8 \ -(XLR_SEC_VECTOR_CIPHER_AES256 | XLR_SEC_VECTOR_F9 | XLR_SEC_VECTOR_MODE_F8) - -/* - * Cipher Modes - */ -typedef enum { - XLR_SEC_CIPHER_MODE_NONE = 0, - XLR_SEC_CIPHER_MODE_PASS = 1, - XLR_SEC_CIPHER_MODE_ECB, - XLR_SEC_CIPHER_MODE_CBC, - XLR_SEC_CIPHER_MODE_OFB, - XLR_SEC_CIPHER_MODE_CTR, - XLR_SEC_CIPHER_MODE_CFB, - XLR_SEC_CIPHER_MODE_F8 -} XLR_SEC_CIPHER_MODE; - -typedef enum { - XLR_SEC_CIPHER_OP_NONE = 0, - XLR_SEC_CIPHER_OP_ENCRYPT = 1, - XLR_SEC_CIPHER_OP_DECRYPT -} XLR_SEC_CIPHER_OP; - -typedef enum { - XLR_SEC_CIPHER_TYPE_UNSUPPORTED = -1, - XLR_SEC_CIPHER_TYPE_NONE = 0, - XLR_SEC_CIPHER_TYPE_DES, - XLR_SEC_CIPHER_TYPE_3DES, - XLR_SEC_CIPHER_TYPE_AES128, - XLR_SEC_CIPHER_TYPE_AES192, - XLR_SEC_CIPHER_TYPE_AES256, - XLR_SEC_CIPHER_TYPE_ARC4, - XLR_SEC_CIPHER_TYPE_KASUMI_F8 -} XLR_SEC_CIPHER_TYPE; - -typedef enum { - XLR_SEC_CIPHER_INIT_OK = 1, /* Preserve old Keys */ - XLR_SEC_CIPHER_INIT_NK /* Load new Keys */ -} XLR_SEC_CIPHER_INIT; - - -/* - * Hash Modes - */ -typedef enum { - XLR_SEC_DIGEST_TYPE_UNSUPPORTED = -1, - XLR_SEC_DIGEST_TYPE_NONE = 0, - XLR_SEC_DIGEST_TYPE_MD5, - XLR_SEC_DIGEST_TYPE_SHA1, - XLR_SEC_DIGEST_TYPE_SHA256, - XLR_SEC_DIGEST_TYPE_SHA384, - XLR_SEC_DIGEST_TYPE_SHA512, - XLR_SEC_DIGEST_TYPE_GCM, - XLR_SEC_DIGEST_TYPE_KASUMI_F9, - XLR_SEC_DIGEST_TYPE_HMAC_MD5, - XLR_SEC_DIGEST_TYPE_HMAC_SHA1, - XLR_SEC_DIGEST_TYPE_HMAC_SHA256, - XLR_SEC_DIGEST_TYPE_HMAC_SHA384, - XLR_SEC_DIGEST_TYPE_HMAC_SHA512, - XLR_SEC_DIGEST_TYPE_HMAC_AES_CBC, - XLR_SEC_DIGEST_TYPE_HMAC_AES_XCBC -} XLR_SEC_DIGEST_TYPE; - -typedef enum { - XLR_SEC_DIGEST_INIT_OLDKEY = 1, /* Preserve old key HMAC key stored in - * ID registers (moot if HASH.HMAC == - * 0) */ - XLR_SEC_DIGEST_INIT_NEWKEY /* Load new HMAC key from memory ctrl - * section to ID registers */ -} XLR_SEC_DIGEST_INIT; - -typedef enum { - XLR_SEC_DIGEST_SRC_DMA = 1, /* DMA channel */ - XLR_SEC_DIGEST_SRC_CPHR /* Cipher if word count exceeded - * Cipher_Offset; else DMA */ -} XLR_SEC_DIGEST_SRC; - -/* - * Checksum Modes - */ -typedef enum { - XLR_SEC_CKSUM_TYPE_NOP = 1, - XLR_SEC_CKSUM_TYPE_IP -} XLR_SEC_CKSUM_TYPE; - -typedef enum { - XLR_SEC_CKSUM_SRC_DMA = 1, - XLR_SEC_CKSUM_SRC_CIPHER -} XLR_SEC_CKSUM_SRC; - -/* - * Packet Modes - */ -typedef enum { - XLR_SEC_LOADHMACKEY_MODE_OLD = 1, - XLR_SEC_LOADHMACKEY_MODE_LOAD -} XLR_SEC_LOADHMACKEY_MODE; - -typedef enum { - XLR_SEC_PADHASH_PADDED = 1, - XLR_SEC_PADHASH_PAD -} XLR_SEC_PADHASH_MODE; - -typedef enum { - XLR_SEC_HASHBYTES_ALL8 = 1, - XLR_SEC_HASHBYTES_MSB, - XLR_SEC_HASHBYTES_MSW -} XLR_SEC_HASHBYTES_MODE; - -typedef enum { - XLR_SEC_NEXT_FINISH = 1, - XLR_SEC_NEXT_DO -} XLR_SEC_NEXT_MODE; - -typedef enum { - XLR_SEC_PKT_IV_OLD = 1, - XLR_SEC_PKT_IV_NEW -} XLR_SEC_PKT_IV_MODE; - -typedef enum { - XLR_SEC_LASTWORD_128 = 1, - XLR_SEC_LASTWORD_96MASK, - XLR_SEC_LASTWORD_64MASK, - XLR_SEC_LASTWORD_32MASK -} XLR_SEC_LASTWORD_MODE; - -typedef enum { - XLR_SEC_CFB_MASK_REGULAR_CTR = 0, - XLR_SEC_CFB_MASK_CCMP, - XLR_SEC_CFB_MASK_GCM_WITH_SCI, - XLR_SEC_CFB_MASK_GCM_WITHOUT_SCI -} XLR_SEC_CFB_MASK_MODE; - -/* - * Public Key - */ -typedef enum { - RMIPK_BLKWIDTH_512 = 1, - RMIPK_BLKWIDTH_1024 -} RMIPK_BLKWIDTH_MODE; - -typedef enum { - RMIPK_LDCONST_OLD = 1, - RMIPK_LDCONST_NEW -} RMIPK_LDCONST_MODE; - - -typedef struct xlr_sec_io_s { - unsigned int command; - unsigned int result_status; - unsigned int flags; - unsigned int session_num; - unsigned int use_callback; - unsigned int time_us; - unsigned int user_context[2]; /* usable for anything by caller */ - unsigned int command_context; /* Context (ID) of this command). */ - unsigned char initial_vector[XLR_SEC_MAX_IV_LENGTH]; - unsigned char crypt_key[XLR_SEC_MAX_CRYPT_KEY_LENGTH]; - unsigned char mac_key[XLR_SEC_MAX_AUTH_KEY_LENGTH]; - - XLR_SEC_CIPHER_OP cipher_op; - XLR_SEC_CIPHER_MODE cipher_mode; - XLR_SEC_CIPHER_TYPE cipher_type; - XLR_SEC_CIPHER_INIT cipher_init; - unsigned int cipher_offset; - - XLR_SEC_DIGEST_TYPE digest_type; - XLR_SEC_DIGEST_INIT digest_init; - XLR_SEC_DIGEST_SRC digest_src; - unsigned int digest_offset; - - XLR_SEC_CKSUM_TYPE cksum_type; - XLR_SEC_CKSUM_SRC cksum_src; - unsigned int cksum_offset; - - XLR_SEC_LOADHMACKEY_MODE pkt_hmac; - XLR_SEC_PADHASH_MODE pkt_hash; - XLR_SEC_HASHBYTES_MODE pkt_hashbytes; - XLR_SEC_NEXT_MODE pkt_next; - XLR_SEC_PKT_IV_MODE pkt_iv; - XLR_SEC_LASTWORD_MODE pkt_lastword; - - unsigned int nonce; - unsigned int cfb_mask; - - unsigned int iv_offset; - unsigned short pad_type; - unsigned short rc4_key_len; - - unsigned int num_packets; - unsigned int num_fragments; - - uint64_t source_buf; - unsigned int source_buf_size; - uint64_t dest_buf; - unsigned int dest_buf_size; - - uint64_t auth_dest; - uint64_t cksum_dest; - - unsigned short rc4_loadstate; - unsigned short rc4_savestate; - uint64_t rc4_state; - -} xlr_sec_io_t, *xlr_sec_io_pt; - - -#define XLR_SEC_SESSION(sid) ((sid) & 0x000007ff) -#define XLR_SEC_SID(crd,ses) (((crd) << 28) | ((ses) & 0x7ff)) - -/* - * Length values for cryptography - */ -/* -#define XLR_SEC_DES_KEY_LENGTH 8 -#define XLR_SEC_3DES_KEY_LENGTH 24 -#define XLR_SEC_MAX_CRYPT_KEY_LENGTH XLR_SEC_3DES_KEY_LENGTH -#define XLR_SEC_IV_LENGTH 8 -#define XLR_SEC_AES_IV_LENGTH 16 -#define XLR_SEC_MAX_IV_LENGTH XLR_SEC_AES_IV_LENGTH -*/ - -#define SEC_MAX_FRAG_LEN 16000 - -struct xlr_sec_command { - uint16_t session_num; - struct cryptop *crp; - struct cryptodesc *enccrd, *maccrd; - - xlr_sec_io_t op; -}; -struct xlr_sec_session { - uint32_t sessionid; - int hs_used; - int hs_mlen; - struct xlr_sec_command cmd; - void *desc_ptr; - uint8_t multi_frag_flag; -}; - -/* - * Holds data specific to rmi security accelerators - */ -struct xlr_sec_softc { - device_t sc_dev; /* device backpointer */ - struct mtx sc_mtx; /* per-instance lock */ - - int32_t sc_cid; - struct xlr_sec_session *sc_sessions; - int sc_nsessions; - xlr_reg_t *mmio; -}; - - -/* - -union xlr_sec_operand_t { - struct mbuf *m; - struct uio *io; - void *buf; -}xlr_sec_operand; -*/ - - - - - -/* this is passed to packet setup to optimize */ -#define XLR_SEC_SETUP_OP_CIPHER 0x00000001 -#define XLR_SEC_SETUP_OP_HMAC 0x00000002 -#define XLR_SEC_SETUP_OP_CIPHER_HMAC (XLR_SEC_SETUP_OP_CIPHER | XLR_SEC_SETUP_OP_HMAC) -/* this is passed to control_setup to update w/preserving existing keys */ -#define XLR_SEC_SETUP_OP_PRESERVE_HMAC_KEY 0x80000000 -#define XLR_SEC_SETUP_OP_PRESERVE_CIPHER_KEY 0x40000000 -#define XLR_SEC_SETUP_OP_UPDATE_KEYS 0x00000010 -#define XLR_SEC_SETUP_OP_FLIP_3DES_KEY 0x00000020 - - - - - -/* - * Message Ring Specifics - */ - -#define SEC_MSGRING_WORDSIZE 2 - - -/* - * - * - * rwR 31 30 29 27 26 24 23 21 20 18 - * | NA | RSA0Out | Rsa0In | Pipe3Out | Pipe3In | ... - * - * 17 15 14 12 11 9 8 6 5 3 2 0 - * | Pipe2Out | Pipe2In | Pipe1In | Pipe1In | Pipe0Out | Pipe0In | - * - * DMA CREDIT REG - - * NUMBER OF CREDITS PER PIPE - */ - -#define SEC_DMA_CREDIT_RSA0_OUT_FOUR 0x20000000 -#define SEC_DMA_CREDIT_RSA0_OUT_TWO 0x10000000 -#define SEC_DMA_CREDIT_RSA0_OUT_ONE 0x08000000 - -#define SEC_DMA_CREDIT_RSA0_IN_FOUR 0x04000000 -#define SEC_DMA_CREDIT_RSA0_IN_TWO 0x02000000 -#define SEC_DMA_CREDIT_RSA0_IN_ONE 0x01000000 - -#define SEC_DMA_CREDIT_PIPE3_OUT_FOUR 0x00800000 -#define SEC_DMA_CREDIT_PIPE3_OUT_TWO 0x00400000 -#define SEC_DMA_CREDIT_PIPE3_OUT_ONE 0x00200000 - -#define SEC_DMA_CREDIT_PIPE3_IN_FOUR 0x00100000 -#define SEC_DMA_CREDIT_PIPE3_IN_TWO 0x00080000 -#define SEC_DMA_CREDIT_PIPE3_IN_ONE 0x00040000 - -#define SEC_DMA_CREDIT_PIPE2_OUT_FOUR 0x00020000 -#define SEC_DMA_CREDIT_PIPE2_OUT_TWO 0x00010000 -#define SEC_DMA_CREDIT_PIPE2_OUT_ONE 0x00008000 - -#define SEC_DMA_CREDIT_PIPE2_IN_FOUR 0x00004000 -#define SEC_DMA_CREDIT_PIPE2_IN_TWO 0x00002000 -#define SEC_DMA_CREDIT_PIPE2_IN_ONE 0x00001000 - -#define SEC_DMA_CREDIT_PIPE1_OUT_FOUR 0x00000800 -#define SEC_DMA_CREDIT_PIPE1_OUT_TWO 0x00000400 -#define SEC_DMA_CREDIT_PIPE1_OUT_ONE 0x00000200 - -#define SEC_DMA_CREDIT_PIPE1_IN_FOUR 0x00000100 -#define SEC_DMA_CREDIT_PIPE1_IN_TWO 0x00000080 -#define SEC_DMA_CREDIT_PIPE1_IN_ONE 0x00000040 - -#define SEC_DMA_CREDIT_PIPE0_OUT_FOUR 0x00000020 -#define SEC_DMA_CREDIT_PIPE0_OUT_TWO 0x00000010 -#define SEC_DMA_CREDIT_PIPE0_OUT_ONE 0x00000008 - -#define SEC_DMA_CREDIT_PIPE0_IN_FOUR 0x00000004 -#define SEC_DMA_CREDIT_PIPE0_IN_TWO 0x00000002 -#define SEC_DMA_CREDIT_PIPE0_IN_ONE 0x00000001 - - -/* - * Currently, FOUR credits per PIPE - * 0x24924924 - */ -#define SEC_DMA_CREDIT_CONFIG SEC_DMA_CREDIT_RSA0_OUT_FOUR | \ - SEC_DMA_CREDIT_RSA0_IN_FOUR | \ - SEC_DMA_CREDIT_PIPE3_OUT_FOUR | \ - SEC_DMA_CREDIT_PIPE3_IN_FOUR | \ - SEC_DMA_CREDIT_PIPE2_OUT_FOUR | \ - SEC_DMA_CREDIT_PIPE2_IN_FOUR | \ - SEC_DMA_CREDIT_PIPE1_OUT_FOUR | \ - SEC_DMA_CREDIT_PIPE1_IN_FOUR | \ - SEC_DMA_CREDIT_PIPE0_OUT_FOUR | \ - SEC_DMA_CREDIT_PIPE0_IN_FOUR - - - - -/* - * CONFIG2 - * 31 5 4 3 - * | NA | PIPE3_DEF_DBL_ISS | PIPE2_DEF_DBL_ISS | ... - * - * 2 1 0 - * ... | PIPE1_DEF_DBL_ISS | PIPE0_DEF_DBL_ISS | ROUND_ROBIN_MODE | - * - * DBL_ISS - mode for SECENG and DMA controller which slows down transfers - * (to be conservativei; 0=Disable,1=Enable). - * ROUND_ROBIN - mode where SECENG dispatches operations to PIPE0-PIPE3 - * and all messages are sent to PIPE0. - * - */ - -#define SEC_CFG2_PIPE3_DBL_ISS_ON 0x00000010 -#define SEC_CFG2_PIPE3_DBL_ISS_OFF 0x00000000 -#define SEC_CFG2_PIPE2_DBL_ISS_ON 0x00000008 -#define SEC_CFG2_PIPE2_DBL_ISS_OFF 0x00000000 -#define SEC_CFG2_PIPE1_DBL_ISS_ON 0x00000004 -#define SEC_CFG2_PIPE1_DBL_ISS_OFF 0x00000000 -#define SEC_CFG2_PIPE0_DBL_ISS_ON 0x00000002 -#define SEC_CFG2_PIPE0_DBL_ISS_OFF 0x00000000 -#define SEC_CFG2_ROUND_ROBIN_ON 0x00000001 -#define SEC_CFG2_ROUND_ROBIN_OFF 0x00000000 - - -enum sec_pipe_config { - - SEC_PIPE_CIPHER_KEY0_L0 = 0x00, - SEC_PIPE_CIPHER_KEY0_HI, - SEC_PIPE_CIPHER_KEY1_LO, - SEC_PIPE_CIPHER_KEY1_HI, - SEC_PIPE_CIPHER_KEY2_LO, - SEC_PIPE_CIPHER_KEY2_HI, - SEC_PIPE_CIPHER_KEY3_LO, - SEC_PIPE_CIPHER_KEY3_HI, - SEC_PIPE_HMAC_KEY0_LO, - SEC_PIPE_HMAC_KEY0_HI, - SEC_PIPE_HMAC_KEY1_LO, - SEC_PIPE_HMAC_KEY1_HI, - SEC_PIPE_HMAC_KEY2_LO, - SEC_PIPE_HMAC_KEY2_HI, - SEC_PIPE_HMAC_KEY3_LO, - SEC_PIPE_HMAC_KEY3_HI, - SEC_PIPE_HMAC_KEY4_LO, - SEC_PIPE_HMAC_KEY4_HI, - SEC_PIPE_HMAC_KEY5_LO, - SEC_PIPE_HMAC_KEY5_HI, - SEC_PIPE_HMAC_KEY6_LO, - SEC_PIPE_HMAC_KEY6_HI, - SEC_PIPE_HMAC_KEY7_LO, - SEC_PIPE_HMAC_KEY7_HI, - SEC_PIPE_NCFBM_LO, - SEC_PIPE_NCFBM_HI, - SEC_PIPE_INSTR_LO, - SEC_PIPE_INSTR_HI, - SEC_PIPE_RSVD0, - SEC_PIPE_RSVD1, - SEC_PIPE_RSVD2, - SEC_PIPE_RSVD3, - - SEC_PIPE_DF_PTRS0, - SEC_PIPE_DF_PTRS1, - SEC_PIPE_DF_PTRS2, - SEC_PIPE_DF_PTRS3, - SEC_PIPE_DF_PTRS4, - SEC_PIPE_DF_PTRS5, - SEC_PIPE_DF_PTRS6, - SEC_PIPE_DF_PTRS7, - - SEC_PIPE_DU_DATA_IN_LO, - SEC_PIPE_DU_DATA_IN_HI, - SEC_PIPE_DU_DATA_IN_CTRL, - SEC_PIPE_DU_DATA_OUT_LO, - SEC_PIPE_DU_DATA_OUT_HI, - SEC_PIPE_DU_DATA_OUT_CTRL, - - SEC_PIPE_STATE0, - SEC_PIPE_STATE1, - SEC_PIPE_STATE2, - SEC_PIPE_STATE3, - SEC_PIPE_STATE4, - SEC_PIPE_INCLUDE_MASK0, - SEC_PIPE_INCLUDE_MASK1, - SEC_PIPE_INCLUDE_MASK2, - SEC_PIPE_INCLUDE_MASK3, - SEC_PIPE_INCLUDE_MASK4, - SEC_PIPE_EXCLUDE_MASK0, - SEC_PIPE_EXCLUDE_MASK1, - SEC_PIPE_EXCLUDE_MASK2, - SEC_PIPE_EXCLUDE_MASK3, - SEC_PIPE_EXCLUDE_MASK4, -}; - - -enum sec_pipe_base_config { - - SEC_PIPE0_BASE = 0x00, - SEC_PIPE1_BASE = 0x40, - SEC_PIPE2_BASE = 0x80, - SEC_PIPE3_BASE = 0xc0 - -}; - -enum sec_rsa_config { - - SEC_RSA_PIPE0_DU_DATA_IN_LO = 0x100, - SEC_RSA_PIPE0_DU_DATA_IN_HI, - SEC_RSA_PIPE0_DU_DATA_IN_CTRL, - SEC_RSA_PIPE0_DU_DATA_OUT_LO, - SEC_RSA_PIPE0_DU_DATA_OUT_HI, - SEC_RSA_PIPE0_DU_DATA_OUT_CTRL, - SEC_RSA_RSVD0, - SEC_RSA_RSVD1, - - SEC_RSA_PIPE0_STATE0, - SEC_RSA_PIPE0_STATE1, - SEC_RSA_PIPE0_STATE2, - SEC_RSA_PIPE0_INCLUDE_MASK0, - SEC_RSA_PIPE0_INCLUDE_MASK1, - SEC_RSA_PIPE0_INCLUDE_MASK2, - SEC_RSA_PIPE0_EXCLUDE_MASK0, - SEC_RSA_PIPE0_EXCLUDE_MASK1, - SEC_RSA_PIPE0_EXCLUDE_MASK2, - SEC_RSA_PIPE0_EVENT_CTR - -}; - - - - -enum sec_config { - - SEC_DMA_CREDIT = 0x140, - SEC_CONFIG1, - SEC_CONFIG2, - SEC_CONFIG3, - -}; - - - -enum sec_debug_config { - - SEC_DW0_DESCRIPTOR0_LO = 0x180, - SEC_DW0_DESCRIPTOR0_HI, - SEC_DW0_DESCRIPTOR1_LO, - SEC_DW0_DESCRIPTOR1_HI, - SEC_DW1_DESCRIPTOR0_LO, - SEC_DW1_DESCRIPTOR0_HI, - SEC_DW1_DESCRIPTOR1_LO, - SEC_DW1_DESCRIPTOR1_HI, - SEC_DW2_DESCRIPTOR0_LO, - SEC_DW2_DESCRIPTOR0_HI, - SEC_DW2_DESCRIPTOR1_LO, - SEC_DW2_DESCRIPTOR1_HI, - SEC_DW3_DESCRIPTOR0_LO, - SEC_DW3_DESCRIPTOR0_HI, - SEC_DW3_DESCRIPTOR1_LO, - SEC_DW3_DESCRIPTOR1_HI, - - SEC_STATE0, - SEC_STATE1, - SEC_STATE2, - SEC_INCLUDE_MASK0, - SEC_INCLUDE_MASK1, - SEC_INCLUDE_MASK2, - SEC_EXCLUDE_MASK0, - SEC_EXCLUDE_MASK1, - SEC_EXCLUDE_MASK2, - SEC_EVENT_CTR - -}; - - -enum sec_msgring_bucket_config { - - SEC_BIU_CREDITS = 0x308, - - SEC_MSG_BUCKET0_SIZE = 0x320, - SEC_MSG_BUCKET1_SIZE, - SEC_MSG_BUCKET2_SIZE, - SEC_MSG_BUCKET3_SIZE, - SEC_MSG_BUCKET4_SIZE, - SEC_MSG_BUCKET5_SIZE, - SEC_MSG_BUCKET6_SIZE, - SEC_MSG_BUCKET7_SIZE, -}; - -enum sec_msgring_credit_config { - - SEC_CC_CPU0_0 = 0x380, - SEC_CC_CPU1_0 = 0x388, - SEC_CC_CPU2_0 = 0x390, - SEC_CC_CPU3_0 = 0x398, - SEC_CC_CPU4_0 = 0x3a0, - SEC_CC_CPU5_0 = 0x3a8, - SEC_CC_CPU6_0 = 0x3b0, - SEC_CC_CPU7_0 = 0x3b8 - -}; - -enum sec_engine_id { - SEC_PIPE0, - SEC_PIPE1, - SEC_PIPE2, - SEC_PIPE3, - SEC_RSA -}; - -enum sec_cipher { - SEC_AES256_MODE_HMAC, - SEC_AES256_MODE, - SEC_AES256_HMAC, - SEC_AES256, - SEC_AES192_MODE_HMAC, - SEC_AES192_MODE, - SEC_AES192_HMAC, - SEC_AES192, - SEC_AES128_MODE_HMAC, - SEC_AES128_MODE, - SEC_AES128_HMAC, - SEC_AES128, - SEC_DES_HMAC, - SEC_DES, - SEC_3DES, - SEC_3DES_HMAC, - SEC_HMAC -}; - -enum sec_msgrng_msg_ctrl_config { - SEC_EOP = 5, - SEC_SOP = 6, -}; - - - -void -xlr_sec_init(struct xlr_sec_softc *sc); - -int -xlr_sec_setup(struct xlr_sec_session *ses, - struct xlr_sec_command *cmd, symkey_desc_pt desc); - -symkey_desc_pt xlr_sec_allocate_desc(void *); - -#endif Property changes on: head/sys/mips/rmi/dev/sec/rmilib.h ___________________________________________________________________ Deleted: svn:eol-style ## -1 +0,0 ## -native \ No newline at end of property Deleted: svn:keywords ## -1 +0,0 ## -FreeBSD=%H \ No newline at end of property Deleted: svn:mime-type ## -1 +0,0 ## -text/plain \ No newline at end of property Index: head/sys/mips/rmi/msgring.c =================================================================== --- head/sys/mips/rmi/msgring.c (revision 327460) +++ head/sys/mips/rmi/msgring.c (nonexistent) @@ -1,320 +0,0 @@ -/*- - * SPDX-License-Identifier: BSD-3-Clause - * - * Copyright (c) 2003-2009 RMI Corporation - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. Neither the name of RMI Corporation, nor the names of its contributors, - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - * - * $FreeBSD$ - * RMI_BSD */ -/********************************************************** - * -----------------DO NOT EDIT THIS FILE------------------ - * This file has been autogenerated by the build process - * from "msgring.cfg" - **********************************************************/ - -#include - -struct bucket_size bucket_sizes = { - { - 32, 32, 32, 32, 32, 32, 32, 32, - 32, 32, 32, 32, 32, 32, 32, 32, - 32, 32, 32, 32, 32, 32, 32, 32, - 32, 32, 32, 32, 32, 32, 32, 32, - 32, 32, 32, 32, 32, 32, 32, 32, - 32, 32, 32, 32, 32, 32, 32, 32, - 32, 32, 32, 32, 32, 32, 32, 32, - 32, 32, 32, 32, 32, 32, 32, 32, - 32, 16, 16, 16, 16, 16, 16, 16, - 16, 16, 16, 16, 16, 16, 16, 0, - 32, 16, 16, 16, 16, 16, 16, 16, - 16, 16, 16, 16, 16, 16, 16, 0, - 0, 32, 32, 32, 32, 32, 0, 32, - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 32, 0, 32, 0, 0, 0, 0, - 128, 0, 0, 0, 128, 0, 0, 0, - } -}; - -struct stn_cc cc_table_cpu_0 = {{ - - {0, 0, 0, 0, 0, 0, 0, 0}, - {0, 0, 0, 4, 0, 0, 0, 0}, - {0, 0, 0, 0, 0, 0, 0, 0}, - {0, 0, 0, 0, 0, 0, 0, 0}, - {0, 0, 0, 0, 0, 0, 0, 0}, - {0, 0, 0, 0, 0, 0, 0, 0}, - {0, 0, 0, 0, 0, 0, 0, 0}, - {0, 0, 0, 0, 0, 0, 0, 0}, - {4, 2, 2, 2, 2, 2, 2, 2}, - {2, 2, 2, 2, 2, 2, 2, 0}, - {4, 2, 2, 2, 2, 2, 2, 2}, - {2, 2, 2, 2, 2, 2, 2, 0}, - {0, 2, 4, 4, 4, 4, 0, 2}, - {0, 0, 0, 0, 0, 0, 0, 0}, - {0, 2, 0, 2, 0, 0, 0, 0}, - {16, 0, 0, 0, 16, 0, 0, 0}, -}}; - -struct stn_cc cc_table_cpu_1 = {{ - - {0, 0, 0, 0, 0, 0, 0, 0}, - {0, 0, 0, 0, 0, 0, 0, 0}, - {0, 0, 0, 0, 0, 0, 0, 0}, - {0, 0, 0, 0, 0, 0, 0, 0}, - {0, 0, 0, 0, 0, 0, 0, 0}, - {0, 0, 0, 0, 0, 0, 0, 0}, - {0, 0, 0, 0, 0, 0, 0, 0}, - {0, 0, 0, 0, 0, 0, 0, 0}, - {4, 2, 2, 2, 2, 2, 2, 2}, - {2, 2, 2, 2, 2, 2, 2, 0}, - {4, 2, 2, 2, 2, 2, 2, 2}, - {2, 2, 2, 2, 2, 2, 2, 0}, - {0, 2, 4, 4, 4, 4, 0, 2}, - {0, 0, 0, 0, 0, 0, 0, 0}, - {0, 2, 0, 2, 0, 0, 0, 0}, - {16, 0, 0, 0, 16, 0, 0, 0}, -}}; - -struct stn_cc cc_table_cpu_2 = {{ - - {0, 0, 0, 0, 0, 0, 0, 0}, - {0, 0, 0, 0, 0, 0, 0, 0}, - {0, 0, 0, 0, 0, 0, 0, 0}, - {0, 0, 0, 0, 0, 0, 0, 0}, - {0, 0, 0, 0, 0, 0, 0, 0}, - {0, 0, 0, 0, 0, 0, 0, 0}, - {0, 0, 0, 0, 0, 0, 0, 0}, - {0, 0, 0, 0, 0, 0, 0, 0}, - {4, 2, 2, 2, 2, 2, 2, 2}, - {2, 2, 2, 2, 2, 2, 2, 0}, - {4, 2, 2, 2, 2, 2, 2, 2}, - {2, 2, 2, 2, 2, 2, 2, 0}, - {0, 4, 4, 4, 4, 4, 0, 4}, - {0, 0, 0, 0, 0, 0, 0, 0}, - {0, 4, 0, 4, 0, 0, 0, 0}, - {16, 0, 0, 0, 16, 0, 0, 0}, -}}; - -struct stn_cc cc_table_cpu_3 = {{ - - {0, 0, 0, 0, 0, 0, 0, 0}, - {0, 0, 0, 0, 0, 0, 0, 0}, - {0, 0, 0, 0, 0, 0, 0, 0}, - {0, 0, 0, 0, 0, 0, 0, 0}, - {0, 0, 0, 0, 0, 0, 0, 0}, - {0, 0, 0, 0, 0, 0, 0, 0}, - {0, 0, 0, 0, 0, 0, 0, 0}, - {0, 0, 0, 0, 0, 0, 0, 0}, - {4, 2, 2, 2, 2, 2, 2, 2}, - {2, 2, 2, 2, 2, 2, 2, 0}, - {4, 2, 2, 2, 2, 2, 2, 2}, - {2, 2, 2, 2, 2, 2, 2, 0}, - {0, 4, 4, 4, 4, 4, 0, 4}, - {0, 0, 0, 0, 0, 0, 0, 0}, - {0, 4, 0, 4, 0, 0, 0, 0}, - {16, 0, 0, 0, 16, 0, 0, 0}, -}}; - -struct stn_cc cc_table_cpu_4 = {{ - - {0, 0, 0, 0, 0, 0, 0, 0}, - {0, 0, 0, 0, 0, 0, 0, 0}, - {0, 0, 0, 0, 0, 0, 0, 0}, - {0, 0, 0, 0, 0, 0, 0, 0}, - {0, 0, 0, 0, 0, 0, 0, 0}, - {0, 0, 0, 0, 0, 0, 0, 0}, - {0, 0, 0, 0, 0, 0, 0, 0}, - {0, 0, 0, 0, 0, 0, 0, 0}, - {4, 2, 2, 2, 2, 2, 2, 2}, - {2, 2, 2, 2, 2, 2, 2, 0}, - {4, 2, 2, 2, 2, 2, 2, 2}, - {2, 2, 2, 2, 2, 2, 2, 0}, - {0, 4, 4, 4, 4, 4, 0, 4}, - {0, 0, 0, 0, 0, 0, 0, 0}, - {0, 4, 0, 4, 0, 0, 0, 0}, - {16, 0, 0, 0, 16, 0, 0, 0}, -}}; - -struct stn_cc cc_table_cpu_5 = {{ - - {0, 0, 0, 0, 0, 0, 0, 0}, - {0, 0, 0, 0, 0, 0, 0, 0}, - {0, 0, 0, 0, 0, 0, 0, 0}, - {0, 0, 0, 0, 0, 0, 0, 0}, - {0, 0, 0, 0, 0, 0, 0, 0}, - {0, 0, 0, 0, 0, 0, 0, 0}, - {0, 0, 0, 0, 0, 0, 0, 0}, - {0, 0, 0, 0, 0, 0, 0, 0}, - {4, 2, 2, 2, 2, 2, 2, 2}, - {2, 2, 2, 2, 2, 2, 2, 0}, - {4, 2, 2, 2, 2, 2, 2, 2}, - {2, 2, 2, 2, 2, 2, 2, 0}, - {0, 4, 4, 4, 4, 4, 0, 4}, - {0, 0, 0, 0, 0, 0, 0, 0}, - {0, 4, 0, 4, 0, 0, 0, 0}, - {16, 0, 0, 0, 16, 0, 0, 0}, -}}; - -struct stn_cc cc_table_cpu_6 = {{ - - {0, 0, 0, 0, 0, 0, 0, 0}, - {0, 0, 0, 0, 0, 0, 0, 0}, - {0, 0, 0, 0, 0, 0, 0, 0}, - {0, 0, 0, 0, 0, 0, 0, 0}, - {0, 0, 0, 0, 0, 0, 0, 0}, - {0, 0, 0, 0, 0, 0, 0, 0}, - {0, 0, 0, 0, 0, 0, 0, 0}, - {0, 0, 0, 0, 0, 0, 0, 0}, - {4, 2, 2, 2, 2, 2, 2, 2}, - {2, 2, 2, 2, 2, 2, 2, 0}, - {4, 2, 2, 2, 2, 2, 2, 2}, - {2, 2, 2, 2, 2, 2, 2, 0}, - {0, 4, 4, 4, 4, 4, 0, 4}, - {0, 0, 0, 0, 0, 0, 0, 0}, - {0, 4, 0, 4, 0, 0, 0, 0}, - {16, 0, 0, 0, 16, 0, 0, 0}, -}}; - -struct stn_cc cc_table_cpu_7 = {{ - - {0, 0, 0, 0, 0, 0, 0, 0}, - {0, 0, 0, 0, 0, 0, 0, 0}, - {0, 0, 0, 0, 0, 0, 0, 0}, - {0, 0, 0, 0, 0, 0, 0, 0}, - {0, 0, 0, 0, 0, 0, 0, 0}, - {0, 0, 0, 0, 0, 0, 0, 0}, - {0, 0, 0, 0, 0, 0, 0, 0}, - {0, 0, 0, 0, 0, 0, 0, 0}, - {4, 2, 2, 2, 2, 2, 2, 2}, - {2, 2, 2, 2, 2, 2, 2, 0}, - {4, 2, 2, 2, 2, 2, 2, 2}, - {2, 2, 2, 2, 2, 2, 2, 0}, - {0, 4, 4, 4, 4, 4, 0, 4}, - {0, 0, 0, 0, 0, 0, 0, 0}, - {0, 4, 0, 4, 0, 0, 0, 0}, - {16, 0, 0, 0, 16, 0, 0, 0}, -}}; - -struct stn_cc cc_table_xgs_0 = {{ - - {8, 8, 8, 8, 8, 8, 8, 8}, - {8, 8, 8, 8, 8, 8, 8, 8}, - {8, 8, 8, 8, 8, 8, 8, 8}, - {8, 8, 8, 8, 8, 8, 8, 8}, - {8, 8, 8, 8, 8, 8, 8, 8}, - {8, 8, 8, 8, 8, 8, 8, 8}, - {8, 8, 8, 8, 8, 8, 8, 8}, - {8, 8, 8, 8, 8, 8, 8, 8}, - {0, 0, 0, 0, 0, 0, 0, 0}, - {0, 0, 0, 0, 0, 0, 0, 0}, - {0, 0, 0, 0, 0, 0, 0, 0}, - {0, 0, 0, 0, 0, 0, 0, 0}, - {0, 0, 0, 0, 0, 0, 0, 0}, - {0, 0, 0, 0, 0, 0, 0, 0}, - {0, 4, 0, 0, 0, 0, 0, 0}, - {0, 0, 0, 0, 0, 0, 0, 0}, -}}; - -struct stn_cc cc_table_xgs_1 = {{ - - {8, 8, 8, 8, 8, 8, 8, 8}, - {8, 8, 8, 8, 8, 8, 8, 8}, - {8, 8, 8, 8, 8, 8, 8, 8}, - {8, 8, 8, 8, 8, 8, 8, 8}, - {8, 8, 8, 8, 8, 8, 8, 8}, - {8, 8, 8, 8, 8, 8, 8, 8}, - {8, 8, 8, 8, 8, 8, 8, 8}, - {8, 8, 8, 8, 8, 8, 8, 8}, - {0, 0, 0, 0, 0, 0, 0, 0}, - {0, 0, 0, 0, 0, 0, 0, 0}, - {0, 0, 0, 0, 0, 0, 0, 0}, - {0, 0, 0, 0, 0, 0, 0, 0}, - {0, 0, 0, 0, 0, 0, 0, 0}, - {0, 0, 0, 0, 0, 0, 0, 0}, - {0, 0, 0, 4, 0, 0, 0, 0}, - {0, 0, 0, 0, 0, 0, 0, 0}, -}}; - -struct stn_cc cc_table_gmac = {{ - - {8, 8, 8, 8, 16, 16, 16, 16}, - {8, 8, 8, 8, 16, 16, 16, 16}, - {8, 8, 8, 8, 16, 16, 16, 16}, - {8, 8, 8, 8, 16, 16, 16, 16}, - {8, 8, 8, 8, 16, 16, 16, 16}, - {8, 8, 8, 8, 16, 16, 16, 16}, - {8, 8, 8, 8, 16, 16, 16, 16}, - {8, 8, 8, 8, 16, 16, 16, 16}, - {0, 0, 0, 0, 0, 0, 0, 0}, - {0, 0, 0, 0, 0, 0, 0, 0}, - {0, 0, 0, 0, 0, 0, 0, 0}, - {0, 0, 0, 0, 0, 0, 0, 0}, - {0, 4, 0, 0, 0, 0, 0, 4}, - {0, 0, 0, 0, 0, 0, 0, 0}, - {0, 0, 0, 0, 0, 0, 0, 0}, - {0, 0, 0, 0, 0, 0, 0, 0}, -}}; - -struct stn_cc cc_table_dma = {{ - - {0, 0, 0, 0, 0, 0, 0, 0}, - {0, 0, 0, 0, 0, 0, 0, 0}, - {0, 0, 0, 0, 0, 0, 0, 0}, - {0, 0, 0, 0, 0, 0, 0, 0}, - {0, 0, 0, 0, 0, 0, 0, 0}, - {0, 0, 0, 0, 0, 0, 0, 0}, - {0, 0, 0, 0, 0, 0, 0, 0}, - {0, 0, 0, 0, 0, 0, 0, 0}, - {0, 0, 0, 0, 0, 0, 0, 0}, - {0, 0, 0, 0, 0, 0, 0, 0}, - {0, 0, 0, 0, 0, 0, 0, 0}, - {0, 0, 0, 0, 0, 0, 0, 0}, - {0, 0, 0, 0, 0, 0, 0, 0}, - {0, 0, 0, 0, 0, 0, 0, 0}, - {0, 0, 0, 0, 0, 0, 0, 0}, - {0, 0, 0, 0, 0, 0, 0, 0}, -}}; - -struct stn_cc cc_table_sec = {{ - - {8, 8, 8, 8, 0, 0, 0, 0}, - {8, 8, 8, 4, 0, 0, 0, 0}, - {8, 8, 8, 8, 0, 0, 0, 0}, - {8, 8, 8, 8, 0, 0, 0, 0}, - {8, 8, 8, 8, 0, 0, 0, 0}, - {8, 8, 8, 8, 0, 0, 0, 0}, - {8, 8, 8, 8, 0, 0, 0, 0}, - {8, 8, 8, 8, 0, 0, 0, 0}, - {0, 0, 0, 0, 0, 0, 0, 0}, - {0, 0, 0, 0, 0, 0, 0, 0}, - {0, 0, 0, 0, 0, 0, 0, 0}, - {0, 0, 0, 0, 0, 0, 0, 0}, - {0, 0, 0, 0, 0, 0, 0, 0}, - {0, 0, 0, 0, 0, 0, 0, 0}, - {0, 0, 0, 0, 0, 0, 0, 0}, - {0, 0, 0, 0, 0, 0, 0, 0}, -}}; Property changes on: head/sys/mips/rmi/msgring.c ___________________________________________________________________ Deleted: svn:eol-style ## -1 +0,0 ## -native \ No newline at end of property Deleted: svn:keywords ## -1 +0,0 ## -FreeBSD=%H \ No newline at end of property Deleted: svn:mime-type ## -1 +0,0 ## -text/plain \ No newline at end of property Index: head/sys/mips/rmi/fmn.c =================================================================== --- head/sys/mips/rmi/fmn.c (revision 327460) +++ head/sys/mips/rmi/fmn.c (nonexistent) @@ -1,493 +0,0 @@ -/*- - * SPDX-License-Identifier: BSD-3-Clause - * - * Copyright (c) 2003-2009 RMI Corporation - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. Neither the name of RMI Corporation, nor the names of its contributors, - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - * - * RMI_BSD */ -#include -__FBSDID("$FreeBSD$"); -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include - -#include -#include -#include -#include -#include - -#define MSGRNG_CC_INIT_CPU_DEST(dest, counter) \ -do { \ - msgrng_write_cc(MSGRNG_CC_##dest##_REG, counter[dest][0], 0 ); \ - msgrng_write_cc(MSGRNG_CC_##dest##_REG, counter[dest][1], 1 ); \ - msgrng_write_cc(MSGRNG_CC_##dest##_REG, counter[dest][2], 2 ); \ - msgrng_write_cc(MSGRNG_CC_##dest##_REG, counter[dest][3], 3 ); \ - msgrng_write_cc(MSGRNG_CC_##dest##_REG, counter[dest][4], 4 ); \ - msgrng_write_cc(MSGRNG_CC_##dest##_REG, counter[dest][5], 5 ); \ - msgrng_write_cc(MSGRNG_CC_##dest##_REG, counter[dest][6], 6 ); \ - msgrng_write_cc(MSGRNG_CC_##dest##_REG, counter[dest][7], 7 ); \ -} while(0) - - -/* - * Keep track of our message ring handler threads, each core has a - * different message station. Ideally we will need to start a few - * message handling threads every core, and wake them up depending on - * load - */ -struct msgring_thread { - struct { - struct thread *thread; /* msgring handler threads */ - int needed; /* thread needs to wake up */ - } threads[XLR_NTHREADS]; - int running; /* number of threads running */ - int nthreads; /* number of threads started */ - struct mtx lock; /* for changing running/active */ -}; -static struct msgring_thread msgring_threads[XLR_MAX_CORES]; -static struct proc *msgring_proc; /* all threads are under a proc */ - -/* - * The maximum number of software message handler threads to be started - * per core. Default is 3 per core - */ -static int msgring_maxthreads = 3; -TUNABLE_INT("hw.fmn.maxthreads", &msgring_maxthreads); - -/* - * The device drivers can register a handler for the messages sent - * from a station (corresponding to the device). - */ -struct tx_stn_handler { - msgring_handler action; - void *arg; -}; -static struct tx_stn_handler msgmap[MSGRNG_NSTATIONS]; -static struct mtx msgmap_lock; - -/* - * Initialize the messaging subsystem. - * - * Message Stations are shared among all threads in a cpu core, this - * has to be called once from every core which is online. - */ -void -xlr_msgring_cpu_init(void) -{ - struct stn_cc *cc_config; - struct bucket_size *bucket_sizes; - uint32_t flags; - int id; - - KASSERT(xlr_thr_id() == 0, - ("xlr_msgring_cpu_init from non-zero thread")); - id = xlr_core_id(); - bucket_sizes = xlr_board_info.bucket_sizes; - cc_config = xlr_board_info.credit_configs[id]; - - flags = msgrng_access_enable(); - - /* - * FMN messages are received in 8 buckets per core, set up - * the bucket sizes for each bucket - */ - msgrng_write_bucksize(0, bucket_sizes->bucket[id * 8 + 0]); - msgrng_write_bucksize(1, bucket_sizes->bucket[id * 8 + 1]); - msgrng_write_bucksize(2, bucket_sizes->bucket[id * 8 + 2]); - msgrng_write_bucksize(3, bucket_sizes->bucket[id * 8 + 3]); - msgrng_write_bucksize(4, bucket_sizes->bucket[id * 8 + 4]); - msgrng_write_bucksize(5, bucket_sizes->bucket[id * 8 + 5]); - msgrng_write_bucksize(6, bucket_sizes->bucket[id * 8 + 6]); - msgrng_write_bucksize(7, bucket_sizes->bucket[id * 8 + 7]); - - /* - * For sending FMN messages, we need credits on the destination - * bucket. Program the credits this core has on the 128 possible - * destination buckets. - * We cannot use a loop here, because the first argument has - * to be a constant integer value. - */ - MSGRNG_CC_INIT_CPU_DEST(0, cc_config->counters); - MSGRNG_CC_INIT_CPU_DEST(1, cc_config->counters); - MSGRNG_CC_INIT_CPU_DEST(2, cc_config->counters); - MSGRNG_CC_INIT_CPU_DEST(3, cc_config->counters); - MSGRNG_CC_INIT_CPU_DEST(4, cc_config->counters); - MSGRNG_CC_INIT_CPU_DEST(5, cc_config->counters); - MSGRNG_CC_INIT_CPU_DEST(6, cc_config->counters); - MSGRNG_CC_INIT_CPU_DEST(7, cc_config->counters); - MSGRNG_CC_INIT_CPU_DEST(8, cc_config->counters); - MSGRNG_CC_INIT_CPU_DEST(9, cc_config->counters); - MSGRNG_CC_INIT_CPU_DEST(10, cc_config->counters); - MSGRNG_CC_INIT_CPU_DEST(11, cc_config->counters); - MSGRNG_CC_INIT_CPU_DEST(12, cc_config->counters); - MSGRNG_CC_INIT_CPU_DEST(13, cc_config->counters); - MSGRNG_CC_INIT_CPU_DEST(14, cc_config->counters); - MSGRNG_CC_INIT_CPU_DEST(15, cc_config->counters); - msgrng_restore(flags); -} - -/* - * Boot time init, called only once - */ -void -xlr_msgring_config(void) -{ - mtx_init(&msgmap_lock, "msgring", NULL, MTX_SPIN); - - /* check value */ - if (msgring_maxthreads < 0 || msgring_maxthreads > XLR_NTHREADS) - msgring_maxthreads = XLR_NTHREADS; -} - -/* - * Drain out max_messages for the buckets set in the bucket mask. - * Use max_messages = 0 to drain out all messages. - */ -uint32_t -xlr_msgring_handler(uint8_t bucket_mask, uint32_t max_messages) -{ - int bucket = 0; - int size = 0, code = 0, rx_stid = 0; - struct msgrng_msg msg; - struct tx_stn_handler *he; - unsigned int status = 0; - unsigned long mflags; - uint32_t n_msgs; - uint32_t msgbuckets; - - n_msgs = 0; - mflags = msgrng_access_enable(); - for (;;) { - msgbuckets = (~msgrng_read_status() >> 24) & bucket_mask; - - /* all buckets empty, break */ - if (msgbuckets == 0) - break; - - for (bucket = 0; bucket < 8; bucket++) { - if ((msgbuckets & (1 << bucket)) == 0) /* empty */ - continue; - - status = message_receive(bucket, &size, &code, - &rx_stid, &msg); - if (status != 0) - continue; - n_msgs++; - he = &msgmap[rx_stid]; - if (he->action == NULL) { - printf("[%s]: No Handler for message from " - "stn_id=%d, bucket=%d, size=%d, msg0=%jx\n", - __func__, rx_stid, bucket, size, - (uintmax_t)msg.msg0); - } else { - msgrng_restore(mflags); - (*he->action)(bucket, size, code, rx_stid, - &msg, he->arg); - mflags = msgrng_access_enable(); - } - if (max_messages > 0 && n_msgs >= max_messages) - goto done; - } - } - -done: - msgrng_restore(mflags); - return (n_msgs); -} - -/* - * XLR COP2 supports watermark interrupts based on the number of - * messages pending in all the buckets in the core. We increase - * the watermark until all the possible handler threads in the core - * are woken up. - */ -static void -msgrng_setconfig(int running, int nthr) -{ - uint32_t config, mflags; - int watermark = 1; /* non zero needed */ - int wm_intr_value; - - KASSERT(nthr >= 0 && nthr <= msgring_maxthreads, - ("Bad value of nthr %d", nthr)); - KASSERT(running <= nthr, ("Bad value of running %d", running)); - - if (running == nthr) { - wm_intr_value = 0; - } else { - switch (running) { - case 0: break; /* keep default */ - case 1: - watermark = 32; break; - case 2: - watermark = 48; break; - case 3: - watermark = 56; break; - } - wm_intr_value = 0x2; /* set watermark enable interrupt */ - } - mflags = msgrng_access_enable(); - config = (watermark << 24) | (IRQ_MSGRING << 16) | (1 << 8) | - wm_intr_value; - /* clear pending interrupts, they will get re-raised if still valid */ - write_c0_eirr64(1ULL << IRQ_MSGRING); - msgrng_write_config(config); - msgrng_restore(mflags); -} - -/* Debug counters */ -static int msgring_nintr[XLR_MAX_CORES]; -static int msgring_badintr[XLR_MAX_CORES]; -static int msgring_wakeup_sleep[XLR_MAX_CORES * XLR_NTHREADS]; -static int msgring_wakeup_nosleep[XLR_MAX_CORES * XLR_NTHREADS]; -static int msgring_nmsgs[XLR_MAX_CORES * XLR_NTHREADS]; - -static int -msgring_process_fast_intr(void *arg) -{ - struct msgring_thread *mthd; - struct thread *td; - uint32_t mflags; - int core, nt; - - core = xlr_core_id(); - mthd = &msgring_threads[core]; - msgring_nintr[core]++; - mtx_lock_spin(&mthd->lock); - nt = mthd->running; - if(nt >= mthd->nthreads) { - msgring_badintr[core]++; - mtx_unlock_spin(&mthd->lock); - return (FILTER_HANDLED); - } - - td = mthd->threads[nt].thread; - mflags = msgrng_access_enable(); - - /* default value with interrupts disabled */ - msgrng_write_config((1 << 24) | (IRQ_MSGRING << 16) | (1 << 8)); - /* clear pending interrupts */ - write_c0_eirr64(1ULL << IRQ_MSGRING); - msgrng_restore(mflags); - mtx_unlock_spin(&mthd->lock); - - /* wake up the target thread */ - mthd->threads[nt].needed = 1; - thread_lock(td); - if (TD_AWAITING_INTR(td)) { - msgring_wakeup_sleep[core*4+nt]++; - TD_CLR_IWAIT(td); - sched_add(td, SRQ_INTR); - } else - msgring_wakeup_nosleep[core*4+nt]++; - thread_unlock(td); - return (FILTER_HANDLED); -} - -static void -msgring_process(void *arg) -{ - struct msgring_thread *mthd; - struct thread *td; - int hwtid, tid, core; - int nmsgs; - - hwtid = (intptr_t)arg; - core = hwtid / 4; - tid = hwtid % 4; - mthd = &msgring_threads[core]; - td = mthd->threads[tid].thread; - KASSERT(curthread == td, - ("Incorrect thread core %d, thread %d", core, hwtid)); - - /* First bind this thread to the right CPU */ - thread_lock(td); - sched_bind(td, xlr_hwtid_to_cpuid[hwtid]); - thread_unlock(td); - - mtx_lock_spin(&mthd->lock); - ++mthd->nthreads; /* Active thread count */ - mtx_unlock_spin(&mthd->lock); - - /* start processing messages */ - for(;;) { - mtx_lock_spin(&mthd->lock); - ++mthd->running; - msgrng_setconfig(mthd->running, mthd->nthreads); - mtx_unlock_spin(&mthd->lock); - - atomic_store_rel_int(&mthd->threads[tid].needed, 0); - nmsgs = xlr_msgring_handler(0xff, 0); - msgring_nmsgs[hwtid] += nmsgs; - - mtx_lock_spin(&mthd->lock); - --mthd->running; - msgrng_setconfig(mthd->running, mthd->nthreads); - mtx_unlock_spin(&mthd->lock); - - /* sleep */ - thread_lock(td); - if (mthd->threads[tid].needed) { - thread_unlock(td); - continue; - } - sched_class(td, PRI_ITHD); - TD_SET_IWAIT(td); - mi_switch(SW_VOL, NULL); - thread_unlock(td); - } -} - -static void -create_msgring_thread(int hwtid) -{ - struct msgring_thread *mthd; - struct thread *td; - int tid, core; - int error; - - core = hwtid / 4; - tid = hwtid % 4; - mthd = &msgring_threads[core]; - if (tid == 0) { - mtx_init(&mthd->lock, "msgrngcore", NULL, MTX_SPIN); - mthd->running = mthd->nthreads = 0; - } - error = kproc_kthread_add(msgring_process, (void *)(uintptr_t)hwtid, - &msgring_proc, &td, RFSTOPPED, 2, "msgrngproc", - "msgthr%d", hwtid); - if (error) - panic("kproc_kthread_add() failed with %d", error); - mthd->threads[tid].thread = td; - - thread_lock(td); - sched_class(td, PRI_ITHD); - sched_add(td, SRQ_INTR); - thread_unlock(td); - CTR2(KTR_INTR, "%s: created %s", __func__, td->td_name); -} - -int -register_msgring_handler(int startb, int endb, msgring_handler action, - void *arg) -{ - void *cookie; - int i; - static int msgring_int_enabled = 0; - - KASSERT(startb >= 0 && startb <= endb && endb < MSGRNG_NSTATIONS, - ("Invalid value for for bucket range %d,%d", startb, endb)); - - mtx_lock_spin(&msgmap_lock); - for (i = startb; i <= endb; i++) { - KASSERT(msgmap[i].action == NULL, - ("Bucket %d already used [action %p]", i, msgmap[i].action)); - msgmap[i].action = action; - msgmap[i].arg = arg; - } - mtx_unlock_spin(&msgmap_lock); - - if (xlr_test_and_set(&msgring_int_enabled)) { - create_msgring_thread(0); - if (msgring_maxthreads > xlr_threads_per_core) - msgring_maxthreads = xlr_threads_per_core; - cpu_establish_hardintr("msgring", msgring_process_fast_intr, - NULL, NULL, IRQ_MSGRING, - INTR_TYPE_NET, &cookie); - } - return (0); -} - -/* - * Start message ring processing threads on other CPUs, after SMP start - */ -static void -start_msgring_threads(void *arg) -{ - int hwt, tid; - - for (hwt = 1; hwt < XLR_MAX_CORES * XLR_NTHREADS; hwt++) { - if ((xlr_hw_thread_mask & (1 << hwt)) == 0) - continue; - tid = hwt % XLR_NTHREADS; - if (tid >= msgring_maxthreads) - continue; - create_msgring_thread(hwt); - } -} - -SYSINIT(start_msgring_threads, SI_SUB_SMP, SI_ORDER_MIDDLE, - start_msgring_threads, NULL); - -/* - * DEBUG support, XXX: static buffer, not locked - */ -static int -sys_print_debug(SYSCTL_HANDLER_ARGS) -{ - struct sbuf sb; - int error, i; - - sbuf_new_for_sysctl(&sb, NULL, 64, req); - sbuf_printf(&sb, - "\nID INTR ER WU-SLP WU-ERR MSGS\n"); - for (i = 0; i < 32; i++) { - if ((xlr_hw_thread_mask & (1 << i)) == 0) - continue; - sbuf_printf(&sb, "%2d: %8d %4d %8d %8d %8d\n", i, - msgring_nintr[i/4], msgring_badintr[i/4], - msgring_wakeup_sleep[i], msgring_wakeup_nosleep[i], - msgring_nmsgs[i]); - } - error = sbuf_finish(&sb); - sbuf_delete(&sb); - return (error); -} - -SYSCTL_PROC(_debug, OID_AUTO, msgring, CTLTYPE_STRING | CTLFLAG_RD, 0, 0, - sys_print_debug, "A", "msgring debug info"); Property changes on: head/sys/mips/rmi/fmn.c ___________________________________________________________________ Deleted: svn:eol-style ## -1 +0,0 ## -native \ No newline at end of property Deleted: svn:keywords ## -1 +0,0 ## -FreeBSD=%H \ No newline at end of property Deleted: svn:mime-type ## -1 +0,0 ## -text/plain \ No newline at end of property Index: head/sys/mips/rmi/rootfs_list.txt =================================================================== --- head/sys/mips/rmi/rootfs_list.txt (revision 327460) +++ head/sys/mips/rmi/rootfs_list.txt (nonexistent) @@ -1,669 +0,0 @@ -# $FreeBSD$ -# -# This is the list of files that -# should be in your rootfs (copy it from -# the build world nfsmount dir. When the rge0 -# driver gets fixed we should be able to start -# using nfs mount... for now we need to use MD_ROOT -./.cshrc -./.profile -./COPYRIGHT -./bin -./bin/cat -./bin/chflags -./bin/chio -./bin/chmod -./bin/cp -./bin/csh -./bin/tcsh -./bin/date -./bin/dd -./bin/df -./bin/domainname -./bin/echo -./bin/ed -./bin/red -./bin/expr -./bin/getfacl -./bin/hostname -./bin/kenv -./bin/kill -./bin/ln -./bin/link -./bin/ls -./bin/mkdir -./bin/mv -./bin/pax -./bin/pkill -./bin/pgrep -./bin/ps -./bin/pwd -./bin/rcp -./bin/realpath -./bin/rm -./bin/unlink -./bin/rmail -./bin/rmdir -./bin/setfacl -./bin/sh -./bin/sleep -./bin/stty -./bin/sync -./bin/test -./bin/[ -./bin/uuidgen -./etc -./etc/bluetooth -./etc/bluetooth/hcsecd.conf -./etc/bluetooth/hosts -./etc/bluetooth/protocols -./etc/defaults -./etc/defaults/bluetooth.device.conf -./etc/defaults/devfs.rules -./etc/defaults/periodic.conf -./etc/defaults/rc.conf -./etc/devd -./etc/devd/asus.conf -./etc/gss -./etc/gss/mech -./etc/gss/qop -./etc/mail -./etc/mail/mailer.conf -./etc/mail/freebsd.mc -./etc/mail/freebsd.cf -./etc/mail/freebsd.submit.mc -./etc/mail/freebsd.submit.cf -./etc/mail/helpfile -./etc/mail/sendmail.cf -./etc/mail/submit.cf -./etc/mail/Makefile -./etc/mail/README -./etc/mail/access.sample -./etc/mail/virtusertable.sample -./etc/mail/mailertable.sample -./etc/mail/aliases -./etc/mtree -./etc/mtree/BSD.include.dist -./etc/mtree/BSD.root.dist -./etc/mtree/BSD.usr.dist -./etc/mtree/BSD.var.dist -./etc/mtree/BSD.sendmail.dist -./etc/mtree/BIND.chroot.dist -./etc/pam.d -./etc/pam.d/README -./etc/pam.d/atrun -./etc/pam.d/cron -./etc/pam.d/ftpd -./etc/pam.d/imap -./etc/pam.d/kde -./etc/pam.d/login -./etc/pam.d/other -./etc/pam.d/passwd -./etc/pam.d/pop3 -./etc/pam.d/rsh -./etc/pam.d/sshd -./etc/pam.d/su -./etc/pam.d/system -./etc/pam.d/telnetd -./etc/pam.d/xdm -./etc/pam.d/ftp -./etc/periodic -./etc/periodic/daily -./etc/periodic/daily/100.clean-disks -./etc/periodic/daily/110.clean-tmps -./etc/periodic/daily/120.clean-preserve -./etc/periodic/daily/200.backup-passwd -./etc/periodic/daily/330.news -./etc/periodic/daily/400.status-disks -./etc/periodic/daily/404.status-zfs -./etc/periodic/daily/405.status-ata-raid -./etc/periodic/daily/406.status-gmirror -./etc/periodic/daily/407.status-graid3 -./etc/periodic/daily/408.status-gstripe -./etc/periodic/daily/409.status-gconcat -./etc/periodic/daily/420.status-network -./etc/periodic/daily/450.status-security -./etc/periodic/daily/999.local -./etc/periodic/daily/310.accounting -./etc/periodic/daily/470.status-named -./etc/periodic/daily/300.calendar -./etc/periodic/daily/130.clean-msgs -./etc/periodic/daily/480.status-ntpd -./etc/periodic/daily/140.clean-rwho -./etc/periodic/daily/430.status-rwho -./etc/periodic/daily/150.clean-hoststat -./etc/periodic/daily/210.backup-aliases -./etc/periodic/daily/440.status-mailq -./etc/periodic/daily/460.status-mail-rejects -./etc/periodic/daily/500.queuerun -./etc/periodic/monthly -./etc/periodic/monthly/999.local -./etc/periodic/monthly/200.accounting -./etc/periodic/security -./etc/periodic/security/100.chksetuid -./etc/periodic/security/200.chkmounts -./etc/periodic/security/300.chkuid0 -./etc/periodic/security/400.passwdless -./etc/periodic/security/410.logincheck -./etc/periodic/security/700.kernelmsg -./etc/periodic/security/800.loginfail -./etc/periodic/security/900.tcpwrap -./etc/periodic/security/security.functions -./etc/periodic/security/510.ipfdenied -./etc/periodic/security/500.ipfwdenied -./etc/periodic/security/550.ipfwlimit -./etc/periodic/security/520.pfdenied -./etc/periodic/weekly -./etc/periodic/weekly/340.noid -./etc/periodic/weekly/999.local -./etc/periodic/weekly/310.locate -./etc/periodic/weekly/320.whatis -./etc/periodic/weekly/400.status-pkg -./etc/ppp -./etc/ppp/ppp.conf -./etc/rc.d -./etc/rc.d/DAEMON -./etc/rc.d/FILESYSTEMS -./etc/rc.d/LOGIN -./etc/rc.d/NETWORKING -./etc/rc.d/SERVERS -./etc/rc.d/abi -./etc/rc.d/accounting -./etc/rc.d/addswap -./etc/rc.d/adjkerntz -./etc/rc.d/amd -./etc/rc.d/apm -./etc/rc.d/apmd -./etc/rc.d/archdep -./etc/rc.d/atm1 -./etc/rc.d/atm2 -./etc/rc.d/atm3 -./etc/rc.d/auditd -./etc/rc.d/bgfsck -./etc/rc.d/bluetooth -./etc/rc.d/bootparams -./etc/rc.d/bridge -./etc/rc.d/bthidd -./etc/rc.d/ccd -./etc/rc.d/cleanvar -./etc/rc.d/cleartmp -./etc/rc.d/cron -./etc/rc.d/ddb -./etc/rc.d/defaultroute -./etc/rc.d/devd -./etc/rc.d/devfs -./etc/rc.d/dhclient -./etc/rc.d/dmesg -./etc/rc.d/dumpon -./etc/rc.d/encswap -./etc/rc.d/fsck -./etc/rc.d/ftp-proxy -./etc/rc.d/ftpd -./etc/rc.d/gbde -./etc/rc.d/geli -./etc/rc.d/geli2 -./etc/rc.d/gssd -./etc/rc.d/hcsecd -./etc/rc.d/hostapd -./etc/rc.d/hostid -./etc/rc.d/hostid_save -./etc/rc.d/hostname -./etc/rc.d/inetd -./etc/rc.d/initrandom -./etc/rc.d/ip6addrctl -./etc/rc.d/ip6fw -./etc/rc.d/ipfilter -./etc/rc.d/ipfs -./etc/rc.d/ipfw -./etc/rc.d/ipmon -./etc/rc.d/ipnat -./etc/rc.d/ipsec -./etc/rc.d/jail -./etc/rc.d/kadmind -./etc/rc.d/kerberos -./etc/rc.d/keyserv -./etc/rc.d/kldxref -./etc/rc.d/kpasswdd -./etc/rc.d/ldconfig -./etc/rc.d/local -./etc/rc.d/localpkg -./etc/rc.d/lockd -./etc/rc.d/lpd -./etc/rc.d/mixer -./etc/rc.d/motd -./etc/rc.d/mountcritlocal -./etc/rc.d/mountcritremote -./etc/rc.d/mountlate -./etc/rc.d/mdconfig -./etc/rc.d/mdconfig2 -./etc/rc.d/mountd -./etc/rc.d/moused -./etc/rc.d/mroute6d -./etc/rc.d/mrouted -./etc/rc.d/msgs -./etc/rc.d/named -./etc/rc.d/natd -./etc/rc.d/netif -./etc/rc.d/netoptions -./etc/rc.d/newsyslog -./etc/rc.d/pf -./etc/rc.d/nfscbd -./etc/rc.d/nfsclient -./etc/rc.d/nfsd -./etc/rc.d/nfsserver -./etc/rc.d/nfsuserd -./etc/rc.d/nisdomain -./etc/rc.d/nsswitch -./etc/rc.d/ntpd -./etc/rc.d/ntpdate -./etc/rc.d/othermta -./etc/rc.d/pflog -./etc/rc.d/pfsync -./etc/rc.d/powerd -./etc/rc.d/power_profile -./etc/rc.d/ppp -./etc/rc.d/pppoed -./etc/rc.d/pwcheck -./etc/rc.d/quota -./etc/rc.d/random -./etc/rc.d/rarpd -./etc/rc.d/resolv -./etc/rc.d/rfcomm_pppd_server -./etc/rc.d/root -./etc/rc.d/route6d -./etc/rc.d/routed -./etc/rc.d/routing -./etc/rc.d/rpcbind -./etc/rc.d/rtadvd -./etc/rc.d/rwho -./etc/rc.d/savecore -./etc/rc.d/sdpd -./etc/rc.d/securelevel -./etc/rc.d/sendmail -./etc/rc.d/serial -./etc/rc.d/sppp -./etc/rc.d/statd -./etc/rc.d/static_arp -./etc/rc.d/stf -./etc/rc.d/swap1 -./etc/rc.d/syscons -./etc/rc.d/sysctl -./etc/rc.d/syslogd -./etc/rc.d/timed -./etc/rc.d/tmp -./etc/rc.d/ugidfw -./etc/rc.d/var -./etc/rc.d/virecover -./etc/rc.d/watchdogd -./etc/rc.d/wpa_supplicant -./etc/rc.d/ypbind -./etc/rc.d/yppasswdd -./etc/rc.d/ypserv -./etc/rc.d/ypset -./etc/rc.d/ypupdated -./etc/rc.d/ypxfrd -./etc/rc.d/zfs -./etc/rc.d/zvol -./etc/rc.d/sshd -./etc/rc.d/nscd -./etc/security -./etc/security/audit_class -./etc/security/audit_event -./etc/security/audit_control -./etc/security/audit_user -./etc/security/audit_warn -./etc/ssh -./etc/ssh/ssh_config -./etc/ssh/sshd_config -./etc/ssh/moduli -./etc/ssl -./etc/ssl/openssl.cnf -./etc/crontab -./etc/devd.conf -./etc/devfs.conf -./etc/ddb.conf -./etc/dhclient.conf -./etc/disktab -./etc/fbtab -./etc/ftpusers -./etc/gettytab -./etc/group -./etc/hosts -./etc/hosts.allow -./etc/hosts.equiv -./etc/inetd.conf -./etc/libalias.conf -./etc/login.access -./etc/login.conf -./etc/mac.conf -./etc/motd -./etc/netconfig -./etc/network.subr -./etc/networks -./etc/newsyslog.conf -./etc/nsswitch.conf -./etc/phones -./etc/profile -./etc/protocols -./etc/rc -./etc/rc.bsdextended -./etc/rc.firewall -./etc/rc.firewall6 -./etc/rc.initdiskless -./etc/rc.sendmail -./etc/rc.shutdown -./etc/rc.subr -./etc/remote -./etc/rpc -./etc/services -./etc/shells -./etc/sysctl.conf -./etc/syslog.conf -./etc/ttys -./etc/amd.map -./etc/apmd.conf -./etc/freebsd-update.conf -./etc/locate.rc -./etc/hosts.lpd -./etc/printcap -./etc/mail.rc -./etc/manpath.config -./etc/ntp.conf -./etc/nscd.conf -./etc/portsnap.conf -./etc/pf.os -./etc/csh.cshrc -./etc/csh.login -./etc/csh.logout -./etc/regdomain.xml -./etc/login.conf.db -./etc/pwd.db -./etc/netstart -./etc/pccard_ether -./etc/rc.suspend -./etc/rc.resume -./etc/master.passwd -./etc/nsmb.conf -./etc/opieaccess -./etc/spwd.db -./etc/passwd -./etc/dumpdates -./etc/fstab -./etc/rc.conf -./etc/resolv.conf -./etc/termcap -./lib -./lib/geom -./lib/geom/geom_cache.so -./lib/geom/geom_concat.so -./lib/geom/geom_eli.so -./lib/geom/geom_journal.so -./lib/geom/geom_label.so -./lib/geom/geom_mirror.so -./lib/geom/geom_multipath.so -./lib/geom/geom_nop.so -./lib/geom/geom_part.so -./lib/geom/geom_raid3.so -./lib/geom/geom_shsec.so -./lib/geom/geom_stripe.so -./lib/geom/geom_virstor.so -./lib/libc.so.7 -./lib/libcrypt.so.5 -./lib/libkvm.so.5 -./lib/libm.so.5 -./lib/libmd.so.5 -./lib/libncurses.so.8 -./lib/libncursesw.so.8 -./lib/libsbuf.so.5 -./lib/libutil.so.8 -./lib/libalias.so.7 -./lib/libalias_cuseeme.so -./lib/libalias_dummy.so -./lib/libalias_ftp.so -./lib/libalias_irc.so -./lib/libalias_nbt.so -./lib/libalias_pptp.so -./lib/libalias_skinny.so -./lib/libalias_smedia.so -./lib/libbegemot.so.4 -./lib/libcam.so.5 -./lib/libdevstat.so.7 -./lib/libedit.so.7 -./lib/libbsdxml.so.4 -./lib/libgeom.so.5 -./lib/libipsec.so.4 -./lib/libjail.so.1 -./lib/libkiconv.so.4 -./lib/libpcap.so.7 -./lib/libthr.so.3 -./lib/libufs.so.5 -./lib/libz.so.5 -./lib/libgcc_s.so.1 -./lib/libreadline.so.8 -./lib/libssp.so.0 -./lib/libcrypto.so.6 -./libexec -./libexec/ld-elf.so.1 -./libexec/ld-elf.so.1.old -./sbin -./sbin/adjkerntz -./sbin/atacontrol -./sbin/bsdlabel -./sbin/camcontrol -./sbin/ccdconfig -./sbin/clri -./sbin/comcontrol -./sbin/conscontrol -./sbin/devd -./sbin/devfs -./sbin/dhclient -./sbin/dhclient-script -./sbin/dmesg -./sbin/dump -./sbin/rdump -./sbin/dumpfs -./sbin/dumpon -./sbin/fdisk -./sbin/ffsinfo -./sbin/fsck -./sbin/fsck_ffs -./sbin/fsck_ufs -./sbin/fsck_4.2bsd -./sbin/fsdb -./sbin/fsirand -./sbin/gbde -./sbin/fsck_msdosfs -./sbin/geom -./sbin/gcache -./sbin/gconcat -./sbin/geli -./sbin/gjournal -./sbin/glabel -./sbin/gmirror -./sbin/gmultipath -./sbin/gnop -./sbin/gpart -./sbin/graid3 -./sbin/gshsec -./sbin/gstripe -./sbin/gvirstor -./sbin/ggatec -./sbin/ggated -./sbin/ggatel -./sbin/growfs -./sbin/gvinum -./sbin/ifconfig -./sbin/init -./sbin/ipf -./sbin/ipfs -./sbin/ipfstat -./sbin/ipftest -./sbin/ipmon -./sbin/ipnat -./sbin/ippool -./sbin/md5 -./sbin/ipfw -./sbin/ipresend -./sbin/iscontrol -./sbin/kldconfig -./sbin/kldload -./sbin/kldstat -./sbin/kldunload -./sbin/ldconfig -./sbin/rmd160 -./sbin/sha1 -./sbin/sha256 -./sbin/mdconfig -./sbin/mdmfs -./sbin/mount_mfs -./sbin/mknod -./sbin/mksnap_ffs -./sbin/mount -./sbin/mount_cd9660 -./sbin/mount_msdosfs -./sbin/mount_nfs -./sbin/mount_newnfs -./sbin/mount_nullfs -./sbin/mount_udf -./sbin/mount_unionfs -./sbin/natd -./sbin/ddb -./sbin/newfs -./sbin/newfs_msdos -./sbin/nfsiod -./sbin/nos-tun -./sbin/pfctl -./sbin/pflogd -./sbin/ping -./sbin/ping6 -./sbin/quotacheck -./sbin/rcorder -./sbin/reboot -./sbin/nextboot -./sbin/halt -./sbin/fastboot -./sbin/fasthalt -./sbin/recoverdisk -./sbin/restore -./sbin/rrestore -./sbin/route -./sbin/routed -./sbin/rtquery -./sbin/rtsol -./sbin/savecore -./sbin/setkey -./sbin/shutdown -./sbin/spppcontrol -./sbin/swapon -./sbin/swapoff -./sbin/swapctl -./sbin/sysctl -./sbin/tunefs -./sbin/umount -./sbin/init.bak -./var -./var/crash -./var/crash/minfree -./var/db -./var/db/locate.database -./var/log -./var/log/sendmail.st -./var/named -./var/named/etc -./var/named/etc/namedb -./var/named/etc/namedb/master -./var/named/etc/namedb/master/empty.db -./var/named/etc/namedb/master/localhost-forward.db -./var/named/etc/namedb/master/localhost-reverse.db -./var/named/etc/namedb/named.conf -./var/named/etc/namedb/named.root -./var/yp -./var/yp/Makefile.dist -./var/run -./var/cron -./var/cron/tabs -./root -./root/.k5login -./root/.profile -./root/.cshrc -./root/.login -./list -./dev -./usr -./usr/sbin -./usr/sbin/newsyslog -./usr/sbin/syslogd -./usr/sbin/ip6addrctl -./usr/sbin/sendmail -./usr/sbin/cron -./usr/lib -./usr/lib/libpam.so.5 -./usr/lib/libpam.so -./usr/lib/pam_opie.so.5 -./usr/lib/libbsm.so.3 -./usr/lib/libbsm.so -./usr/lib/pam_chroot.so.5 -./usr/lib/pam_tacplus.so.5 -./usr/lib/pam_ssh.so.5 -./usr/lib/pam_self.so.5 -./usr/lib/pam_securetty.so.5 -./usr/lib/pam_rootok.so.5 -./usr/lib/pam_rhosts.so.5 -./usr/lib/pam_radius.so.5 -./usr/lib/pam_permit.so.5 -./usr/lib/pam_passwdqc.so.5 -./usr/lib/libcom_err.so.5 -./usr/lib/libcom_err.so -./usr/lib/pam_opieaccess.so.5 -./usr/lib/pam_nologin.so.5 -./usr/lib/libc.so.7 -./usr/lib/pam_login_access.so.5 -./usr/lib/pam_lastlog.so.5 -./usr/lib/pam_ksu.so.5 -./usr/lib/pam_krb5.so.5 -./usr/lib/pam_guest.so.5 -./usr/lib/pam_group.so.5 -./usr/lib/pam_ftpusers.so.5 -./usr/lib/pam_exec.so.5 -./usr/lib/pam_echo.so.5 -./usr/lib/pam_deny.so.5 -./usr/lib/pam_unix.so.5 -./usr/lib/pam_chroot.so -./usr/lib/libopie.so -./usr/lib/pam_deny.so -./usr/lib/pam_echo.so -./usr/lib/pam_exec.so -./usr/lib/pam_ftpusers.so -./usr/lib/pam_group.so -./usr/lib/pam_guest.so -./usr/lib/pam_krb5.so -./usr/lib/pam_ksu.so -./usr/lib/pam_lastlog.so -./usr/lib/pam_login_access.so -./usr/lib/pam_nologin.so -./usr/lib/pam_opie.so -./usr/lib/pam_opieaccess.so -./usr/lib/pam_passwdqc.so -./usr/lib/pam_permit.so -./usr/lib/pam_radius.so -./usr/lib/pam_rhosts.so -./usr/lib/pam_rootok.so -./usr/lib/pam_securetty.so -./usr/lib/pam_self.so -./usr/lib/pam_ssh.so -./usr/lib/pam_tacplus.so -./usr/lib/pam_unix.so -./usr/lib/libmd.so.5 -./usr/lib/libbz2.so.4 -./usr/lib/libgnuregex.so.5 -./usr/lib/libypclnt.so.4 -./usr/bin -./usr/bin/mktemp -./usr/bin/login -./usr/bin/uname -./usr/bin/awk -./usr/bin/logger -./usr/bin/grep -./usr/bin/ftp -./usr/libexec -./usr/libexec/getty Property changes on: head/sys/mips/rmi/rootfs_list.txt ___________________________________________________________________ Deleted: svn:eol-style ## -1 +0,0 ## -native \ No newline at end of property Deleted: svn:keywords ## -1 +0,0 ## -FreeBSD=%H \ No newline at end of property Deleted: svn:mime-type ## -1 +0,0 ## -text/plain \ No newline at end of property Index: head/sys/mips/rmi/msgring.h =================================================================== --- head/sys/mips/rmi/msgring.h (revision 327460) +++ head/sys/mips/rmi/msgring.h (nonexistent) @@ -1,372 +0,0 @@ -/*- - * SPDX-License-Identifier: BSD-3-Clause - * - * Copyright (c) 2003-2009 RMI Corporation - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. Neither the name of RMI Corporation, nor the names of its contributors, - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - * - * RMI_BSD - * $FreeBSD$ - */ -#ifndef _RMI_MSGRING_H_ -#define _RMI_MSGRING_H_ - -#include -#include -#include - -#include -#include -#include - -#define MSGRNG_TX_BUF_REG 0 -#define MSGRNG_RX_BUF_REG 1 -#define MSGRNG_MSG_STATUS_REG 2 -#define MSGRNG_MSG_CONFIG_REG 3 -#define MSGRNG_MSG_BUCKSIZE_REG 4 - -#define MSGRNG_CC_0_REG 16 -#define MSGRNG_CC_1_REG 17 -#define MSGRNG_CC_2_REG 18 -#define MSGRNG_CC_3_REG 19 -#define MSGRNG_CC_4_REG 20 -#define MSGRNG_CC_5_REG 21 -#define MSGRNG_CC_6_REG 22 -#define MSGRNG_CC_7_REG 23 -#define MSGRNG_CC_8_REG 24 -#define MSGRNG_CC_9_REG 25 -#define MSGRNG_CC_10_REG 26 -#define MSGRNG_CC_11_REG 27 -#define MSGRNG_CC_12_REG 28 -#define MSGRNG_CC_13_REG 29 -#define MSGRNG_CC_14_REG 30 -#define MSGRNG_CC_15_REG 31 - -/* Station IDs */ -#define MSGRNG_STNID_CPU0 0x00 -#define MSGRNG_STNID_CPU1 0x08 -#define MSGRNG_STNID_CPU2 0x10 -#define MSGRNG_STNID_CPU3 0x18 -#define MSGRNG_STNID_CPU4 0x20 -#define MSGRNG_STNID_CPU5 0x28 -#define MSGRNG_STNID_CPU6 0x30 -#define MSGRNG_STNID_CPU7 0x38 -#define MSGRNG_STNID_XGS0_TX 64 -#define MSGRNG_STNID_XMAC0_00_TX 64 -#define MSGRNG_STNID_XMAC0_01_TX 65 -#define MSGRNG_STNID_XMAC0_02_TX 66 -#define MSGRNG_STNID_XMAC0_03_TX 67 -#define MSGRNG_STNID_XMAC0_04_TX 68 -#define MSGRNG_STNID_XMAC0_05_TX 69 -#define MSGRNG_STNID_XMAC0_06_TX 70 -#define MSGRNG_STNID_XMAC0_07_TX 71 -#define MSGRNG_STNID_XMAC0_08_TX 72 -#define MSGRNG_STNID_XMAC0_09_TX 73 -#define MSGRNG_STNID_XMAC0_10_TX 74 -#define MSGRNG_STNID_XMAC0_11_TX 75 -#define MSGRNG_STNID_XMAC0_12_TX 76 -#define MSGRNG_STNID_XMAC0_13_TX 77 -#define MSGRNG_STNID_XMAC0_14_TX 78 -#define MSGRNG_STNID_XMAC0_15_TX 79 - -#define MSGRNG_STNID_XGS1_TX 80 -#define MSGRNG_STNID_XMAC1_00_TX 80 -#define MSGRNG_STNID_XMAC1_01_TX 81 -#define MSGRNG_STNID_XMAC1_02_TX 82 -#define MSGRNG_STNID_XMAC1_03_TX 83 -#define MSGRNG_STNID_XMAC1_04_TX 84 -#define MSGRNG_STNID_XMAC1_05_TX 85 -#define MSGRNG_STNID_XMAC1_06_TX 86 -#define MSGRNG_STNID_XMAC1_07_TX 87 -#define MSGRNG_STNID_XMAC1_08_TX 88 -#define MSGRNG_STNID_XMAC1_09_TX 89 -#define MSGRNG_STNID_XMAC1_10_TX 90 -#define MSGRNG_STNID_XMAC1_11_TX 91 -#define MSGRNG_STNID_XMAC1_12_TX 92 -#define MSGRNG_STNID_XMAC1_13_TX 93 -#define MSGRNG_STNID_XMAC1_14_TX 94 -#define MSGRNG_STNID_XMAC1_15_TX 95 - -#define MSGRNG_STNID_GMAC 96 -#define MSGRNG_STNID_GMACJFR_0 96 -#define MSGRNG_STNID_GMACRFR_0 97 -#define MSGRNG_STNID_GMACTX0 98 -#define MSGRNG_STNID_GMACTX1 99 -#define MSGRNG_STNID_GMACTX2 100 -#define MSGRNG_STNID_GMACTX3 101 -#define MSGRNG_STNID_GMACJFR_1 102 -#define MSGRNG_STNID_GMACRFR_1 103 - -#define MSGRNG_STNID_DMA 104 -#define MSGRNG_STNID_DMA_0 104 -#define MSGRNG_STNID_DMA_1 105 -#define MSGRNG_STNID_DMA_2 106 -#define MSGRNG_STNID_DMA_3 107 - -#define MSGRNG_STNID_XGS0FR 112 -#define MSGRNG_STNID_XMAC0JFR 112 -#define MSGRNG_STNID_XMAC0RFR 113 - -#define MSGRNG_STNID_XGS1FR 114 -#define MSGRNG_STNID_XMAC1JFR 114 -#define MSGRNG_STNID_XMAC1RFR 115 -#define MSGRNG_STNID_SEC 120 -#define MSGRNG_STNID_SEC0 120 -#define MSGRNG_STNID_SEC1 121 -#define MSGRNG_STNID_SEC2 122 -#define MSGRNG_STNID_SEC3 123 -#define MSGRNG_STNID_PK0 124 -#define MSGRNG_STNID_SEC_RSA 124 -#define MSGRNG_STNID_SEC_RSVD0 125 -#define MSGRNG_STNID_SEC_RSVD1 126 -#define MSGRNG_STNID_SEC_RSVD2 127 - -#define MSGRNG_STNID_GMAC1 80 -#define MSGRNG_STNID_GMAC1_FR_0 81 -#define MSGRNG_STNID_GMAC1_TX0 82 -#define MSGRNG_STNID_GMAC1_TX1 83 -#define MSGRNG_STNID_GMAC1_TX2 84 -#define MSGRNG_STNID_GMAC1_TX3 85 -#define MSGRNG_STNID_GMAC1_FR_1 87 -#define MSGRNG_STNID_GMAC0 96 -#define MSGRNG_STNID_GMAC0_FR_0 97 -#define MSGRNG_STNID_GMAC0_TX0 98 -#define MSGRNG_STNID_GMAC0_TX1 99 -#define MSGRNG_STNID_GMAC0_TX2 100 -#define MSGRNG_STNID_GMAC0_TX3 101 -#define MSGRNG_STNID_GMAC0_FR_1 103 -#define MSGRNG_STNID_CMP_0 108 -#define MSGRNG_STNID_CMP_1 109 -#define MSGRNG_STNID_CMP_2 110 -#define MSGRNG_STNID_CMP_3 111 -#define MSGRNG_STNID_PCIE_0 116 -#define MSGRNG_STNID_PCIE_1 117 -#define MSGRNG_STNID_PCIE_2 118 -#define MSGRNG_STNID_PCIE_3 119 -#define MSGRNG_STNID_XLS_PK0 121 - -#define MSGRNG_CODE_MAC 0 -#define MSGRNG_CODE_XGMAC 2 -#define MSGRNG_CODE_SEC 0 -#define MSGRNG_CODE_BOOT_WAKEUP 200 -#define MSGRNG_CODE_SPI4 3 - -#define msgrng_read_status() read_c2_register32(MSGRNG_MSG_STATUS_REG, 0) -#define msgrng_read_config() read_c2_register32(MSGRNG_MSG_CONFIG_REG, 0) -#define msgrng_write_config(v) write_c2_register32(MSGRNG_MSG_CONFIG_REG, 0, v) -#define msgrng_read_bucksize(b) read_c2_register32(MSGRNG_MSG_BUCKSIZE_REG, b) -#define msgrng_write_bucksize(b, v) write_c2_register32(MSGRNG_MSG_BUCKSIZE_REG, b, v) -#define msgrng_read_cc(r, s) read_c2_register32(r, s) -#define msgrng_write_cc(r, v, s) write_c2_register32(r, s, v) - -#define msgrng_load_rx_msg0() read_c2_register64(MSGRNG_RX_BUF_REG, 0) -#define msgrng_load_rx_msg1() read_c2_register64(MSGRNG_RX_BUF_REG, 1) -#define msgrng_load_rx_msg2() read_c2_register64(MSGRNG_RX_BUF_REG, 2) -#define msgrng_load_rx_msg3() read_c2_register64(MSGRNG_RX_BUF_REG, 3) - -#define msgrng_load_tx_msg0(v) write_c2_register64(MSGRNG_TX_BUF_REG, 0, v) -#define msgrng_load_tx_msg1(v) write_c2_register64(MSGRNG_TX_BUF_REG, 1, v) -#define msgrng_load_tx_msg2(v) write_c2_register64(MSGRNG_TX_BUF_REG, 2, v) -#define msgrng_load_tx_msg3(v) write_c2_register64(MSGRNG_TX_BUF_REG, 3, v) - -static __inline void -msgrng_send(unsigned int stid) -{ - __asm__ volatile ( - ".set push\n" - ".set noreorder\n" - "move $8, %0\n" - "c2 0x80001\n" /* msgsnd $8 */ - ".set pop\n" - :: "r" (stid): "$8" - ); -} - -static __inline void -msgrng_receive(unsigned int pri) -{ - __asm__ volatile ( - ".set push\n" - ".set noreorder\n" - "move $8, %0\n" - "c2 0x80002\n" /* msgld $8 */ - ".set pop\n" - :: "r" (pri): "$8" - ); -} - -static __inline void -msgrng_wait(unsigned int mask) -{ - __asm__ volatile ( - ".set push\n" - ".set noreorder\n" - "move $8, %0\n" - "c2 0x80003\n" /* msgwait $8 */ - ".set pop\n" - :: "r" (mask): "$8" - ); -} - -static __inline uint32_t -msgrng_access_enable(void) -{ - uint32_t sr = mips_rd_status(); - - mips_wr_status((sr & ~MIPS_SR_INT_IE) | MIPS_SR_COP_2_BIT); - return (sr); -} - -static __inline void -msgrng_restore(uint32_t sr) -{ - - mips_wr_status(sr); -} - -struct msgrng_msg { - uint64_t msg0; - uint64_t msg1; - uint64_t msg2; - uint64_t msg3; -}; - -static __inline int -message_send(unsigned int size, unsigned int code, - unsigned int stid, struct msgrng_msg *msg) -{ - unsigned int dest = 0; - unsigned long long status = 0; - int i = 0; - - /* - * Make sure that all the writes pending at the cpu are flushed. - * Any writes pending on CPU will not be see by devices. L1/L2 - * caches are coherent with IO, so no cache flush needed. - */ - __asm __volatile ("sync"); - - /* Load TX message buffers */ - msgrng_load_tx_msg0(msg->msg0); - msgrng_load_tx_msg1(msg->msg1); - msgrng_load_tx_msg2(msg->msg2); - msgrng_load_tx_msg3(msg->msg3); - dest = ((size - 1) << 16) | (code << 8) | stid; - - /* - * Retry a few times on credit fail, this should be a - * transient condition, unless there is a configuration - * failure, or the receiver is stuck. - */ - for (i = 0; i < 8; i++) { - msgrng_send(dest); - status = msgrng_read_status(); - KASSERT((status & 0x2) == 0, ("Send pending fail!")); - if ((status & 0x4) == 0) - return (0); - } - - /* If there is a credit failure, return error */ - return (status & 0x06); -} - -static __inline int -message_receive(int bucket, int *size, int *code, int *stid, - struct msgrng_msg *msg) -{ - uint32_t status = 0, tmp = 0; - - msgrng_receive(bucket); - - /* wait for load pending to clear */ - do { - status = msgrng_read_status(); - } while ((status & 0x08) != 0); - - /* receive error bits */ - tmp = status & 0x30; - if (tmp != 0) - return (tmp); - - *size = ((status & 0xc0) >> 6) + 1; - *code = (status & 0xff00) >> 8; - *stid = (status & 0x7f0000) >> 16; - msg->msg0 = msgrng_load_rx_msg0(); - msg->msg1 = msgrng_load_rx_msg1(); - msg->msg2 = msgrng_load_rx_msg2(); - msg->msg3 = msgrng_load_rx_msg3(); - return (0); -} - -#define MSGRNG_STN_RX_QSIZE 256 -#define MSGRNG_NSTATIONS 128 -#define MSGRNG_CORE_NBUCKETS 8 - -struct stn_cc { - unsigned short counters[16][8]; -}; - -struct bucket_size { - unsigned short bucket[MSGRNG_NSTATIONS]; -}; - -extern struct bucket_size bucket_sizes; - -extern struct stn_cc cc_table_cpu_0; -extern struct stn_cc cc_table_cpu_1; -extern struct stn_cc cc_table_cpu_2; -extern struct stn_cc cc_table_cpu_3; -extern struct stn_cc cc_table_cpu_4; -extern struct stn_cc cc_table_cpu_5; -extern struct stn_cc cc_table_cpu_6; -extern struct stn_cc cc_table_cpu_7; -extern struct stn_cc cc_table_xgs_0; -extern struct stn_cc cc_table_xgs_1; -extern struct stn_cc cc_table_gmac; -extern struct stn_cc cc_table_dma; -extern struct stn_cc cc_table_sec; - -extern struct bucket_size xls_bucket_sizes; - -extern struct stn_cc xls_cc_table_cpu_0; -extern struct stn_cc xls_cc_table_cpu_1; -extern struct stn_cc xls_cc_table_cpu_2; -extern struct stn_cc xls_cc_table_cpu_3; -extern struct stn_cc xls_cc_table_gmac0; -extern struct stn_cc xls_cc_table_gmac1; -extern struct stn_cc xls_cc_table_cmp; -extern struct stn_cc xls_cc_table_pcie; -extern struct stn_cc xls_cc_table_dma; -extern struct stn_cc xls_cc_table_sec; - -typedef void (*msgring_handler)(int, int, int, int, struct msgrng_msg *, void *); -int register_msgring_handler(int startb, int endb, msgring_handler action, - void *arg); -uint32_t xlr_msgring_handler(uint8_t bucket_mask, uint32_t max_messages); -void xlr_msgring_cpu_init(void); -void xlr_msgring_config(void); - -#endif Property changes on: head/sys/mips/rmi/msgring.h ___________________________________________________________________ Deleted: svn:eol-style ## -1 +0,0 ## -native \ No newline at end of property Deleted: svn:keywords ## -1 +0,0 ## -FreeBSD=%H \ No newline at end of property Deleted: svn:mime-type ## -1 +0,0 ## -text/plain \ No newline at end of property Index: head/sys/mips/rmi/mpwait.S =================================================================== --- head/sys/mips/rmi/mpwait.S (revision 327460) +++ head/sys/mips/rmi/mpwait.S (nonexistent) @@ -1,68 +0,0 @@ -/*- - * Copyright (c) 2010 RMI Technologies Ltd. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - * - * $FreeBSD$ - */ - -#include -#include -#include - -#include "assym.s" - - .text - .set noat - .set noreorder - -/* - * On XLR the slave processors and threads will be executing boot - * loader code on startup. We need to make them run our code before - * blowing away boot loader memory. - */ -LEAF(mpwait) - PTR_LA gp, _C_LABEL(_gp) - PTR_LA t1, _C_LABEL(xlr_ap_release) - mfc0 t2, $15, 1 - andi t2, 0x1f - sll t2, t2, 2 - add t1, t2 - -1: lw t0, 0(t1) - bnez t0, 2f - nop /* We should not busy wait in core0 threads */ - nop /* on bootup, this will slow the cpu0 thread */ - nop /* down - TODO - wait with IPI based wakeup */ - nop - nop - nop - nop - nop - j 1b - nop -2: - PTR_LA t1, _C_LABEL(mpentry) - jr t1 - nop -END(mpwait) Property changes on: head/sys/mips/rmi/mpwait.S ___________________________________________________________________ Deleted: svn:eol-style ## -1 +0,0 ## -native \ No newline at end of property Deleted: svn:keywords ## -1 +0,0 ## -FreeBSD=%H \ No newline at end of property Deleted: svn:mime-type ## -1 +0,0 ## -text/plain \ No newline at end of property Index: head/sys/mips/rmi/pic.h =================================================================== --- head/sys/mips/rmi/pic.h (revision 327460) +++ head/sys/mips/rmi/pic.h (nonexistent) @@ -1,274 +0,0 @@ -/*- - * SPDX-License-Identifier: BSD-3-Clause - * - * Copyright (c) 2003-2009 RMI Corporation - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. Neither the name of RMI Corporation, nor the names of its contributors, - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - * - * RMI_BSD - * $FreeBSD$ - */ -#ifndef _RMI_PIC_H_ -#define _RMI_PIC_H_ - -#include -#include -#include -#include - -#define PIC_IRT_WD_INDEX 0 -#define PIC_IRT_TIMER_INDEX(i) (1 + (i)) -#define PIC_IRT_UART_0_INDEX 9 -#define PIC_IRT_UART_1_INDEX 10 -#define PIC_IRT_I2C_0_INDEX 11 -#define PIC_IRT_I2C_1_INDEX 12 -#define PIC_IRT_PCMCIA_INDEX 13 -#define PIC_IRT_GPIO_INDEX 14 -#define PIC_IRT_HYPER_INDEX 15 -#define PIC_IRT_PCIX_INDEX 16 -#define PIC_IRT_GMAC0_INDEX 17 -#define PIC_IRT_GMAC1_INDEX 18 -#define PIC_IRT_GMAC2_INDEX 19 -#define PIC_IRT_GMAC3_INDEX 20 -#define PIC_IRT_XGS0_INDEX 21 -#define PIC_IRT_XGS1_INDEX 22 -#define PIC_IRT_HYPER_FATAL_INDEX 23 -#define PIC_IRT_PCIX_FATAL_INDEX 24 -#define PIC_IRT_BRIDGE_AERR_INDEX 25 -#define PIC_IRT_BRIDGE_BERR_INDEX 26 -#define PIC_IRT_BRIDGE_TB_INDEX 27 -#define PIC_IRT_BRIDGE_AERR_NMI_INDEX 28 - -/* numbering for XLS */ -#define PIC_IRT_BRIDGE_ERR_INDEX 25 -#define PIC_IRT_PCIE_LINK0_INDEX 26 -#define PIC_IRT_PCIE_LINK1_INDEX 27 -#define PIC_IRT_PCIE_LINK2_INDEX 23 -#define PIC_IRT_PCIE_LINK3_INDEX 24 -#define PIC_IRT_PCIE_B0_LINK2_INDEX 28 -#define PIC_IRT_PCIE_B0_LINK3_INDEX 29 -#define PIC_IRT_PCIE_INT_INDEX 28 -#define PIC_IRT_PCIE_FATAL_INDEX 29 -#define PIC_IRT_GPIO_B_INDEX 30 -#define PIC_IRT_USB_INDEX 31 -#define PIC_NUM_IRTS 32 - -#define PIC_CLOCK_TIMER 7 - -#define PIC_CTRL 0x00 -#define PIC_IPI 0x04 -#define PIC_INT_ACK 0x06 - -#define WD_MAX_VAL_0 0x08 -#define WD_MAX_VAL_1 0x09 -#define WD_MASK_0 0x0a -#define WD_MASK_1 0x0b -#define WD_HEARBEAT_0 0x0c -#define WD_HEARBEAT_1 0x0d - -#define PIC_IRT_0_BASE 0x40 -#define PIC_IRT_1_BASE 0x80 -#define PIC_TIMER_MAXVAL_0_BASE 0x100 -#define PIC_TIMER_MAXVAL_1_BASE 0x110 -#define PIC_TIMER_COUNT_0_BASE 0x120 -#define PIC_TIMER_COUNT_1_BASE 0x130 - -#define PIC_IRT_0(picintr) (PIC_IRT_0_BASE + (picintr)) -#define PIC_IRT_1(picintr) (PIC_IRT_1_BASE + (picintr)) - -#define PIC_TIMER_MAXVAL_0(i) (PIC_TIMER_MAXVAL_0_BASE + (i)) -#define PIC_TIMER_MAXVAL_1(i) (PIC_TIMER_MAXVAL_1_BASE + (i)) -#define PIC_TIMER_COUNT_0(i) (PIC_TIMER_COUNT_0_BASE + (i)) -#define PIC_TIMER_COUNT_1(i) (PIC_TIMER_COUNT_0_BASE + (i)) -#define PIC_TIMER_HZ 66000000U - -/* - * We use a simple mapping form PIC interrupts to CPU IRQs. - * The PIC interrupts 0-31 are mapped to CPU irq's 8-39. - * this leaves the lower 0-7 for the cpu interrupts (like - * count/compare, msgrng) and 40-63 for IPIs - */ -#define PIC_IRQ_BASE 8 -#define PIC_INTR_TO_IRQ(i) (PIC_IRQ_BASE + (i)) -#define PIC_IRQ_TO_INTR(i) ((i) - PIC_IRQ_BASE) - -#define PIC_WD_IRQ (PIC_IRQ_BASE + PIC_IRT_WD_INDEX) -#define PIC_TIMER_IRQ(i) (PIC_IRQ_BASE + PIC_IRT_TIMER_INDEX(i)) -#define PIC_CLOCK_IRQ PIC_TIMER_IRQ(PIC_CLOCK_TIMER) - -#define PIC_UART_0_IRQ (PIC_IRQ_BASE + PIC_IRT_UART_0_INDEX) -#define PIC_UART_1_IRQ (PIC_IRQ_BASE + PIC_IRT_UART_1_INDEX) -#define PIC_I2C_0_IRQ (PIC_IRQ_BASE + PIC_IRT_I2C_0_INDEX) -#define PIC_I2C_1_IRQ (PIC_IRQ_BASE + PIC_IRT_I2C_1_INDEX) -#define PIC_PCMCIA_IRQ (PIC_IRQ_BASE + PIC_IRT_PCMCIA_INDEX) -#define PIC_GPIO_IRQ (PIC_IRQ_BASE + PIC_IRT_GPIO_INDEX) -#define PIC_HYPER_IRQ (PIC_IRQ_BASE + PIC_IRT_HYPER_INDEX) -#define PIC_PCIX_IRQ (PIC_IRQ_BASE + PIC_IRT_PCIX_INDEX) -#define PIC_GMAC_0_IRQ (PIC_IRQ_BASE + PIC_IRT_GMAC0_INDEX) -#define PIC_GMAC_1_IRQ (PIC_IRQ_BASE + PIC_IRT_GMAC1_INDEX) -#define PIC_GMAC_2_IRQ (PIC_IRQ_BASE + PIC_IRT_GMAC2_INDEX) -#define PIC_GMAC_3_IRQ (PIC_IRQ_BASE + PIC_IRT_GMAC3_INDEX) -#define PIC_XGS_0_IRQ (PIC_IRQ_BASE + PIC_IRT_XGS0_INDEX) -#define PIC_XGS_1_IRQ (PIC_IRQ_BASE + PIC_IRT_XGS1_INDEX) -#define PIC_HYPER_FATAL_IRQ (PIC_IRQ_BASE + PIC_IRT_HYPER_FATAL_INDEX) -#define PIC_PCIX_FATAL_IRQ (PIC_IRQ_BASE + PIC_IRT_PCIX_FATAL_INDEX) -#define PIC_BRIDGE_AERR_IRQ (PIC_IRQ_BASE + PIC_IRT_BRIDGE_AERR_INDEX) -#define PIC_BRIDGE_BERR_IRQ (PIC_IRQ_BASE + PIC_IRT_BRIDGE_BERR_INDEX) -#define PIC_BRIDGE_TB_IRQ (PIC_IRQ_BASE + PIC_IRT_BRIDGE_TB_INDEX) -#define PIC_BRIDGE_AERR_NMI_IRQ (PIC_IRQ_BASE + PIC_IRT_BRIDGE_AERR_NMI_INDEX) -#define PIC_BRIDGE_ERR_IRQ (PIC_IRQ_BASE + PIC_IRT_BRIDGE_ERR_INDEX) -#define PIC_PCIE_LINK0_IRQ (PIC_IRQ_BASE + PIC_IRT_PCIE_LINK0_INDEX) -#define PIC_PCIE_LINK1_IRQ (PIC_IRQ_BASE + PIC_IRT_PCIE_LINK1_INDEX) -#define PIC_PCIE_LINK2_IRQ (PIC_IRQ_BASE + PIC_IRT_PCIE_LINK2_INDEX) -#define PIC_PCIE_LINK3_IRQ (PIC_IRQ_BASE + PIC_IRT_PCIE_LINK3_INDEX) -#define PIC_PCIE_B0_LINK2_IRQ (PIC_IRQ_BASE + PIC_IRT_PCIE_B0_LINK2_INDEX) -#define PIC_PCIE_B0_LINK3_IRQ (PIC_IRQ_BASE + PIC_IRT_PCIE_B0_LINK3_INDEX) -#define PIC_PCIE_INT_IRQ (PIC_IRQ_BASE + PIC_IRT_PCIE_INT_INDEX) -#define PIC_PCIE_FATAL_IRQ (PIC_IRQ_BASE + PIC_IRT_PCIE_FATAL_INDEX) -#define PIC_GPIO_B_IRQ (PIC_IRQ_BASE + PIC_IRT_GPIO_B_INDEX) -#define PIC_USB_IRQ (PIC_IRQ_BASE + PIC_IRT_USB_INDEX) - -#define PIC_IRQ_IS_PICINTR(irq) ((irq) >= PIC_IRQ_BASE && \ - (irq) < PIC_IRQ_BASE + PIC_NUM_IRTS) -#define PIC_IS_EDGE_TRIGGERED(i) ((i) >= PIC_IRT_TIMER_INDEX(0) && \ - (i) <= PIC_IRT_TIMER_INDEX(7)) - -extern struct mtx xlr_pic_lock; - -static __inline uint32_t -pic_read_control(void) -{ - xlr_reg_t *mmio = xlr_io_mmio(XLR_IO_PIC_OFFSET); - uint32_t reg; - - mtx_lock_spin(&xlr_pic_lock); - reg = xlr_read_reg(mmio, PIC_CTRL); - mtx_unlock_spin(&xlr_pic_lock); - return (reg); -} - -static __inline void -pic_write_control(uint32_t control) -{ - xlr_reg_t *mmio = xlr_io_mmio(XLR_IO_PIC_OFFSET); - - mtx_lock_spin(&xlr_pic_lock); - xlr_write_reg(mmio, PIC_CTRL, control); - mtx_unlock_spin(&xlr_pic_lock); -} - -static __inline void -pic_update_control(uint32_t control) -{ - xlr_reg_t *mmio = xlr_io_mmio(XLR_IO_PIC_OFFSET); - - mtx_lock_spin(&xlr_pic_lock); - xlr_write_reg(mmio, PIC_CTRL, (control | xlr_read_reg(mmio, PIC_CTRL))); - mtx_unlock_spin(&xlr_pic_lock); -} - -static __inline void -pic_ack(int picintr) -{ - xlr_reg_t *mmio = xlr_io_mmio(XLR_IO_PIC_OFFSET); - - xlr_write_reg(mmio, PIC_INT_ACK, 1U << picintr); -} - -static __inline -void pic_send_ipi(int cpu, int ipi) -{ - xlr_reg_t *mmio = xlr_io_mmio(XLR_IO_PIC_OFFSET); - int tid, pid; - - tid = cpu & 0x3; - pid = (cpu >> 2) & 0x7; - xlr_write_reg(mmio, PIC_IPI, (pid << 20) | (tid << 16) | ipi); -} - -static __inline -void pic_setup_intr(int picintr, int irq, uint32_t cpumask, int level) -{ - xlr_reg_t *mmio = xlr_io_mmio(XLR_IO_PIC_OFFSET); - - mtx_lock_spin(&xlr_pic_lock); - xlr_write_reg(mmio, PIC_IRT_0(picintr), cpumask); - xlr_write_reg(mmio, PIC_IRT_1(picintr), ((1U << 31) | (level << 30) | - (1 << 6) | irq)); - mtx_unlock_spin(&xlr_pic_lock); -} - -static __inline void -pic_init_timer(int timer) -{ - xlr_reg_t *mmio = xlr_io_mmio(XLR_IO_PIC_OFFSET); - uint32_t val; - - mtx_lock_spin(&xlr_pic_lock); - val = xlr_read_reg(mmio, PIC_CTRL); - val |= (1 << (8 + timer)); - xlr_write_reg(mmio, PIC_CTRL, val); - mtx_unlock_spin(&xlr_pic_lock); -} - -static __inline void -pic_set_timer(int timer, uint64_t maxval) -{ - xlr_reg_t *mmio = xlr_io_mmio(XLR_IO_PIC_OFFSET); - - xlr_write_reg(mmio, PIC_TIMER_MAXVAL_0(timer), - (maxval & 0xffffffff)); - xlr_write_reg(mmio, PIC_TIMER_MAXVAL_1(timer), - (maxval >> 32) & 0xffffffff); -} - -static __inline uint32_t -pic_timer_count32(int timer) - { - xlr_reg_t *mmio = xlr_io_mmio(XLR_IO_PIC_OFFSET); - - return (xlr_read_reg(mmio, PIC_TIMER_COUNT_0(timer))); -} - -/* - * The timer can wrap 32 bits between the two reads, so we - * need additional logic to detect that. - */ -static __inline uint64_t -pic_timer_count(int timer) -{ - xlr_reg_t *mmio = xlr_io_mmio(XLR_IO_PIC_OFFSET); - uint32_t tu1, tu2, tl; - - tu1 = xlr_read_reg(mmio, PIC_TIMER_COUNT_1(timer)); - tl = xlr_read_reg(mmio, PIC_TIMER_COUNT_0(timer)); - tu2 = xlr_read_reg(mmio, PIC_TIMER_COUNT_1(timer)); - if (tu2 != tu1) - tl = xlr_read_reg(mmio, PIC_TIMER_COUNT_0(timer)); - return (((uint64_t)tu2 << 32) | tl); -} - -#endif /* _RMI_PIC_H_ */ Property changes on: head/sys/mips/rmi/pic.h ___________________________________________________________________ Deleted: svn:eol-style ## -1 +0,0 ## -native \ No newline at end of property Deleted: svn:keywords ## -1 +0,0 ## -FreeBSD=%H \ No newline at end of property Deleted: svn:mime-type ## -1 +0,0 ## -text/plain \ No newline at end of property Index: head/sys/mips/rmi/uart_cpu_mips_xlr.c =================================================================== --- head/sys/mips/rmi/uart_cpu_mips_xlr.c (revision 327460) +++ head/sys/mips/rmi/uart_cpu_mips_xlr.c (nonexistent) @@ -1,86 +0,0 @@ -/*- - * SPDX-License-Identifier: BSD-2-Clause-FreeBSD - * - * Copyright (c) 2006 Wojciech A. Koszek - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - * - * $Id: uart_cpu_mips_xlr.c,v 1.5 2008-07-16 20:22:39 jayachandranc Exp $ - */ -/* - * Skeleton of this file was based on respective code for ARM - * code written by Olivier Houchard. - */ -/* - * XLRMIPS: This file is hacked from arm/... - */ -#include "opt_uart.h" - -#include -__FBSDID("$FreeBSD$"); - -#include -#include -#include -#include - -#include - -#include -#include -#include -#include -#include -#include -#include - -bus_space_tag_t uart_bus_space_io; -bus_space_tag_t uart_bus_space_mem; - -int -uart_cpu_eqres(struct uart_bas *b1, struct uart_bas *b2) -{ - return ((b1->bsh == b2->bsh && b1->bst == b2->bst) ? 1 : 0); -} - - -int -uart_cpu_getdev(int devtype, struct uart_devinfo *di) -{ - di->ops = uart_getops(&uart_ns8250_class); - di->bas.chan = 0; - di->bas.bst = rmi_bus_space; - di->bas.bsh = MIPS_PHYS_TO_KSEG1(XLR_UART0ADDR); - - di->bas.regshft = 2; - /* divisor = rclk / (baudrate * 16); */ - di->bas.rclk = 66000000; - di->baudrate = 0; - di->databits = 8; - di->stopbits = 1; - di->parity = UART_PARITY_NONE; - - uart_bus_space_io = NULL; - uart_bus_space_mem = rmi_bus_space; - return (0); -} Property changes on: head/sys/mips/rmi/uart_cpu_mips_xlr.c ___________________________________________________________________ Deleted: svn:eol-style ## -1 +0,0 ## -native \ No newline at end of property Deleted: svn:keywords ## -1 +0,0 ## -FreeBSD=%H \ No newline at end of property Deleted: svn:mime-type ## -1 +0,0 ## -text/plain \ No newline at end of property Index: head/sys/mips/rmi/msgring.cfg =================================================================== --- head/sys/mips/rmi/msgring.cfg (revision 327460) +++ head/sys/mips/rmi/msgring.cfg (nonexistent) @@ -1,1185 +0,0 @@ -/*- - * SPDX-License-Identifier: BSD-3-Clause - * - * Copyright (c) 2003-2009 RMI Corporation - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. Neither the name of RMI Corporation, nor the names of its contributors, - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - * - * $FreeBSD$ - * RMI_BSD */ -/* - * This file defines the message ring configuration for phoenix-8. It tries to allow - * many different point-point communications between the message stations on the message ring - * and as result is _not_ the best configuration for performance - * - * The message ring on phoenix family of processors connects the cpus, gmacs, xgmac/spi4, - * security engine and the general purpose DMA engines. It provides a high bandwidth, - * low latency communication links. On traditional processors, this communication goes through - * which inherently does not scale very well with increasing number of cpus. - * - * Message ring has an in-built flow control mechanism. Every agent/station on the ring has to - * have software configured credits to send messages to any agent. Every receiving agent on the - * ring has a 256 entry FIFO that can divided into "buckets". All addressing on the ring is - * in terms of buckets. There are a total 128 buckets on the ring. The total number of credits - * across all sending agents should not exceed the bucket size. - * - * Below are the receiving agents and the max number of buckets they can have - * CPU 0 : 8 buckets - * CPU 1 : 8 buckets - * CPU 2 : 8 buckets - * CPU 3 : 8 buckets - * CPU 4 : 8 buckets - * CPU 5 : 8 buckets - * CPU 6 : 8 buckets - * CPU 7 : 8 buckets - * - * XGMAC 0 / SPI4 0 - * TX : 16 buckets - * FREE : 2 buckets - * XGMAC 1 / SPI4 1 - * TX : 16 buckets - * FREE : 2 buckets - * - * GMAC : 8 buckets - * - * SEC : 8 buckets - * - * DMA : 8 buckets - * - * The bucket size of a bucket should be aligned to the bucket's starting index in that - * receiving station's FIFO. For example, if sizes of bucket0 and bucket1 of a station - * are 32 and 32, bucket2's size has to be 64. bucket size 0 is valid. - * - * The format of the file is pretty straight forward. Each bucket definition has the size - * and the list of sending agents to that bucket with the number of credits to send. - * - * Undefined buckets have a size of 0 and Tx stations have 0 credits to send to that bucket. - * - * Following are the currently supported bucket names - * cpu_0_0 - * cpu_0_1 - * cpu_0_2 - * cpu_0_3 - * cpu_0_4 - * cpu_0_5 - * cpu_0_6 - * cpu_0_7 - * - * cpu_1_0 - * cpu_1_1 - * cpu_1_2 - * cpu_1_3 - * cpu_1_4 - * cpu_1_5 - * cpu_1_6 - * cpu_1_7 - * - * cpu_2_0 - * cpu_2_1 - * cpu_2_2 - * cpu_2_3 - * cpu_2_4 - * cpu_2_5 - * cpu_2_6 - * cpu_2_7 - * - * cpu_3_0 - * cpu_3_1 - * cpu_3_2 - * cpu_3_3 - * cpu_3_4 - * cpu_3_5 - * cpu_3_6 - * cpu_3_7 - * - * cpu_4_0 - * cpu_4_1 - * cpu_4_2 - * cpu_4_3 - * cpu_4_4 - * cpu_4_5 - * cpu_4_6 - * cpu_4_7 - * - * cpu_5_0 - * cpu_5_1 - * cpu_5_2 - * cpu_5_3 - * cpu_5_4 - * cpu_5_5 - * cpu_5_6 - * cpu_5_7 - * - * cpu_6_0 - * cpu_6_1 - * cpu_6_2 - * cpu_6_3 - * cpu_6_4 - * cpu_6_5 - * cpu_6_6 - * cpu_6_7 - * - * cpu_7_0 - * cpu_7_1 - * cpu_7_2 - * cpu_7_3 - * cpu_7_4 - * cpu_7_5 - * cpu_7_6 - * cpu_7_7 - * - * xgs_0_tx_0 - * xgs_0_tx_1 - * xgs_0_tx_2 - * xgs_0_tx_3 - * xgs_0_tx_4 - * xgs_0_tx_5 - * xgs_0_tx_6 - * xgs_0_tx_7 - * xgs_0_tx_8 - * xgs_0_tx_9 - * xgs_0_tx_10 - * xgs_0_tx_11 - * xgs_0_tx_12 - * xgs_0_tx_13 - * xgs_0_tx_14 - * xgs_0_tx_15 - * - * xgs_1_tx_0 - * xgs_1_tx_1 - * xgs_1_tx_2 - * xgs_1_tx_3 - * xgs_1_tx_4 - * xgs_1_tx_5 - * xgs_1_tx_6 - * xgs_1_tx_7 - * xgs_1_tx_8 - * xgs_1_tx_9 - * xgs_1_tx_10 - * xgs_1_tx_11 - * xgs_1_tx_12 - * xgs_1_tx_13 - * xgs_1_tx_14 - * xgs_1_tx_15 - * - * gmac_rsvd_0 - * gmac_rfr_0 - * gmac_tx_0 - * gmac_tx_1 - * gmac_tx_2 - * gmac_tx_3 - * gmac_rsvd_1 - * gmac_rfr_1 - * - * xgs_0_rsvd - * xgs_0_rfr - * - * xgs_1_rsvd - * xgs_1_rfr - * - * sec_pipe_0 - * sec_pipe_1 - * sec_pipe_2 - * sec_pipe_3 - * sec_rsa - * - * Following are the currently supported Tx Agent/Station names - * - * tx_stn_cpu_0 - * tx_stn_cpu_1 - * tx_stn_cpu_2 - * tx_stn_cpu_3 - * tx_stn_cpu_4 - * tx_stn_cpu_5 - * tx_stn_cpu_6 - * tx_stn_cpu_7 - * - * tx_stn_xgs_0 - * tx_stn_xgs_1 - * - * tx_stn_gmac - * - * tx_stn_dma - * - * tx_stn_sec - * - * - * - */ - -/*************************************************************/ -// CPU_0 Message Station - -bucket "cpu_0_0" { - size 32; - "tx_stn_xgs_0" 8; - "tx_stn_xgs_1" 8; - "tx_stn_gmac" 8; - "tx_stn_sec" 8; -} -bucket "cpu_0_1" { - size 32; - "tx_stn_xgs_0" 8; - "tx_stn_xgs_1" 8; - "tx_stn_gmac" 8; - "tx_stn_sec" 8; -} -bucket "cpu_0_2" { - size 32; - "tx_stn_xgs_0" 8; - "tx_stn_xgs_1" 8; - "tx_stn_gmac" 8; - "tx_stn_sec" 8; -} -bucket "cpu_0_3" { - size 32; - "tx_stn_xgs_0" 8; - "tx_stn_xgs_1" 8; - "tx_stn_gmac" 8; - "tx_stn_sec" 8; -} -bucket "cpu_0_4" { - size 32; - "tx_stn_gmac" 16; - "tx_stn_xgs_0" 8; - "tx_stn_xgs_1" 8; -} -bucket "cpu_0_5" { - size 32; - "tx_stn_gmac" 16; - "tx_stn_xgs_0" 8; - "tx_stn_xgs_1" 8; -} -bucket "cpu_0_6" { - size 32; - "tx_stn_gmac" 16; - "tx_stn_xgs_0" 8; - "tx_stn_xgs_1" 8; -} -bucket "cpu_0_7" { - size 32; - "tx_stn_gmac" 16; - "tx_stn_xgs_0" 8; - "tx_stn_xgs_1" 8; -} - -/*************************************************************/ -// CPU_1 Message Station - -bucket "cpu_1_0" { - size 32; - "tx_stn_xgs_0" 8; - "tx_stn_xgs_1" 8; - "tx_stn_gmac" 8; - "tx_stn_sec" 8; -} -bucket "cpu_1_1" { - size 32; - "tx_stn_xgs_0" 8; - "tx_stn_xgs_1" 8; - "tx_stn_gmac" 8; - "tx_stn_sec" 8; -} -bucket "cpu_1_2" { - size 32; - "tx_stn_xgs_0" 8; - "tx_stn_xgs_1" 8; - "tx_stn_gmac" 8; - "tx_stn_sec" 8; -} -bucket "cpu_1_3" { - size 32; - "tx_stn_xgs_0" 8; - "tx_stn_xgs_1" 8; - "tx_stn_gmac" 8; - "tx_stn_sec" 4; - "tx_stn_cpu_0" 4; /* NEEDED BY RMIOS IPSEC */ -} -bucket "cpu_1_4" { - size 32; - "tx_stn_gmac" 16; - "tx_stn_xgs_0" 8; - "tx_stn_xgs_1" 8; -} -bucket "cpu_1_5" { - size 32; - "tx_stn_gmac" 16; - "tx_stn_xgs_0" 8; - "tx_stn_xgs_1" 8; -} -bucket "cpu_1_6" { - size 32; - "tx_stn_gmac" 16; - "tx_stn_xgs_0" 8; - "tx_stn_xgs_1" 8; -} -bucket "cpu_1_7" { - size 32; - "tx_stn_gmac" 16; - "tx_stn_xgs_0" 8; - "tx_stn_xgs_1" 8; -} - -/*************************************************************/ -// CPU_2 Message Station - -bucket "cpu_2_0" { - size 32; - "tx_stn_xgs_0" 8; - "tx_stn_xgs_1" 8; - "tx_stn_gmac" 8; - "tx_stn_sec" 8; -} -bucket "cpu_2_1" { - size 32; - "tx_stn_xgs_0" 8; - "tx_stn_xgs_1" 8; - "tx_stn_gmac" 8; - "tx_stn_sec" 8; -} -bucket "cpu_2_2" { - size 32; - "tx_stn_xgs_0" 8; - "tx_stn_xgs_1" 8; - "tx_stn_gmac" 8; - "tx_stn_sec" 8; -} -bucket "cpu_2_3" { - size 32; - "tx_stn_xgs_0" 8; - "tx_stn_xgs_1" 8; - "tx_stn_gmac" 8; - "tx_stn_sec" 8; -} -bucket "cpu_2_4" { - size 32; - "tx_stn_gmac" 16; - "tx_stn_xgs_0" 8; - "tx_stn_xgs_1" 8; -} -bucket "cpu_2_5" { - size 32; - "tx_stn_gmac" 16; - "tx_stn_xgs_0" 8; - "tx_stn_xgs_1" 8; -} -bucket "cpu_2_6" { - size 32; - "tx_stn_gmac" 16; - "tx_stn_xgs_0" 8; - "tx_stn_xgs_1" 8; -} -bucket "cpu_2_7" { - size 32; - "tx_stn_gmac" 16; - "tx_stn_xgs_0" 8; - "tx_stn_xgs_1" 8; -} - -/*************************************************************/ -// CPU_3 Message Station - -bucket "cpu_3_0" { - size 32; - "tx_stn_xgs_0" 8; - "tx_stn_xgs_1" 8; - "tx_stn_gmac" 8; - "tx_stn_sec" 8; -} -bucket "cpu_3_1" { - size 32; - "tx_stn_xgs_0" 8; - "tx_stn_xgs_1" 8; - "tx_stn_gmac" 8; - "tx_stn_sec" 8; -} -bucket "cpu_3_2" { - size 32; - "tx_stn_xgs_0" 8; - "tx_stn_xgs_1" 8; - "tx_stn_gmac" 8; - "tx_stn_sec" 8; -} -bucket "cpu_3_3" { - size 32; - "tx_stn_xgs_0" 8; - "tx_stn_xgs_1" 8; - "tx_stn_gmac" 8; - "tx_stn_sec" 8; -} -bucket "cpu_3_4" { - size 32; - "tx_stn_gmac" 16; - "tx_stn_xgs_0" 8; - "tx_stn_xgs_1" 8; -} -bucket "cpu_3_5" { - size 32; - "tx_stn_gmac" 16; - "tx_stn_xgs_0" 8; - "tx_stn_xgs_1" 8; -} -bucket "cpu_3_6" { - size 32; - "tx_stn_gmac" 16; - "tx_stn_xgs_0" 8; - "tx_stn_xgs_1" 8; -} -bucket "cpu_3_7" { - size 32; - "tx_stn_gmac" 16; - "tx_stn_xgs_0" 8; - "tx_stn_xgs_1" 8; -} - -/*************************************************************/ -// CPU_4 Message Station - -bucket "cpu_4_0" { - size 32; - "tx_stn_xgs_0" 8; - "tx_stn_xgs_1" 8; - "tx_stn_gmac" 8; - "tx_stn_sec" 8; -} -bucket "cpu_4_1" { - size 32; - "tx_stn_xgs_0" 8; - "tx_stn_xgs_1" 8; - "tx_stn_gmac" 8; - "tx_stn_sec" 8; -} -bucket "cpu_4_2" { - size 32; - "tx_stn_xgs_0" 8; - "tx_stn_xgs_1" 8; - "tx_stn_gmac" 8; - "tx_stn_sec" 8; -} -bucket "cpu_4_3" { - size 32; - "tx_stn_xgs_0" 8; - "tx_stn_xgs_1" 8; - "tx_stn_gmac" 8; - "tx_stn_sec" 8; -} -bucket "cpu_4_4" { - size 32; - "tx_stn_gmac" 16; - "tx_stn_xgs_0" 8; - "tx_stn_xgs_1" 8; -} -bucket "cpu_4_5" { - size 32; - "tx_stn_gmac" 16; - "tx_stn_xgs_0" 8; - "tx_stn_xgs_1" 8; -} -bucket "cpu_4_6" { - size 32; - "tx_stn_gmac" 16; - "tx_stn_xgs_0" 8; - "tx_stn_xgs_1" 8; -} -bucket "cpu_4_7" { - size 32; - "tx_stn_gmac" 16; - "tx_stn_xgs_0" 8; - "tx_stn_xgs_1" 8; -} - -/*************************************************************/ -// CPU_5 Message Station - -bucket "cpu_5_0" { - size 32; - "tx_stn_xgs_0" 8; - "tx_stn_xgs_1" 8; - "tx_stn_gmac" 8; - "tx_stn_sec" 8; -} -bucket "cpu_5_1" { - size 32; - "tx_stn_xgs_0" 8; - "tx_stn_xgs_1" 8; - "tx_stn_gmac" 8; - "tx_stn_sec" 8; -} -bucket "cpu_5_2" { - size 32; - "tx_stn_xgs_0" 8; - "tx_stn_xgs_1" 8; - "tx_stn_gmac" 8; - "tx_stn_sec" 8; -} -bucket "cpu_5_3" { - size 32; - "tx_stn_xgs_0" 8; - "tx_stn_xgs_1" 8; - "tx_stn_gmac" 8; - "tx_stn_sec" 8; -} -bucket "cpu_5_4" { - size 32; - "tx_stn_gmac" 16; - "tx_stn_xgs_0" 8; - "tx_stn_xgs_1" 8; -} -bucket "cpu_5_5" { - size 32; - "tx_stn_gmac" 16; - "tx_stn_xgs_0" 8; - "tx_stn_xgs_1" 8; -} -bucket "cpu_5_6" { - size 32; - "tx_stn_gmac" 16; - "tx_stn_xgs_0" 8; - "tx_stn_xgs_1" 8; -} -bucket "cpu_5_7" { - size 32; - "tx_stn_gmac" 16; - "tx_stn_xgs_0" 8; - "tx_stn_xgs_1" 8; -} - - -/*************************************************************/ -// CPU_6 Message Station - -bucket "cpu_6_0" { - size 32; - "tx_stn_xgs_0" 8; - "tx_stn_xgs_1" 8; - "tx_stn_gmac" 8; - "tx_stn_sec" 8; -} -bucket "cpu_6_1" { - size 32; - "tx_stn_xgs_0" 8; - "tx_stn_xgs_1" 8; - "tx_stn_gmac" 8; - "tx_stn_sec" 8; -} -bucket "cpu_6_2" { - size 32; - "tx_stn_xgs_0" 8; - "tx_stn_xgs_1" 8; - "tx_stn_gmac" 8; - "tx_stn_sec" 8; -} -bucket "cpu_6_3" { - size 32; - "tx_stn_xgs_0" 8; - "tx_stn_xgs_1" 8; - "tx_stn_gmac" 8; - "tx_stn_sec" 8; -} -bucket "cpu_6_4" { - size 32; - "tx_stn_gmac" 16; - "tx_stn_xgs_0" 8; - "tx_stn_xgs_1" 8; -} -bucket "cpu_6_5" { - size 32; - "tx_stn_gmac" 16; - "tx_stn_xgs_0" 8; - "tx_stn_xgs_1" 8; -} -bucket "cpu_6_6" { - size 32; - "tx_stn_gmac" 16; - "tx_stn_xgs_0" 8; - "tx_stn_xgs_1" 8; -} -bucket "cpu_6_7" { - size 32; - "tx_stn_gmac" 16; - "tx_stn_xgs_0" 8; - "tx_stn_xgs_1" 8; -} - - -/*************************************************************/ -// CPU_7 Message Station - -bucket "cpu_7_0" { - size 32; - "tx_stn_xgs_0" 8; - "tx_stn_xgs_1" 8; - "tx_stn_gmac" 8; - "tx_stn_sec" 8; -} -bucket "cpu_7_1" { - size 32; - "tx_stn_xgs_0" 8; - "tx_stn_xgs_1" 8; - "tx_stn_gmac" 8; - "tx_stn_sec" 8; -} -bucket "cpu_7_2" { - size 32; - "tx_stn_xgs_0" 8; - "tx_stn_xgs_1" 8; - "tx_stn_gmac" 8; - "tx_stn_sec" 8; -} -bucket "cpu_7_3" { - size 32; - "tx_stn_xgs_0" 8; - "tx_stn_xgs_1" 8; - "tx_stn_gmac" 8; - "tx_stn_sec" 8; -} -bucket "cpu_7_4" { - size 32; - "tx_stn_gmac" 16; - "tx_stn_xgs_0" 8; - "tx_stn_xgs_1" 8; -} -bucket "cpu_7_5" { - size 32; - "tx_stn_gmac" 16; - "tx_stn_xgs_0" 8; - "tx_stn_xgs_1" 8; -} -bucket "cpu_7_6" { - size 32; - "tx_stn_gmac" 16; - "tx_stn_xgs_0" 8; - "tx_stn_xgs_1" 8; -} -bucket "cpu_7_7" { - size 32; - "tx_stn_gmac" 16; - "tx_stn_xgs_0" 8; - "tx_stn_xgs_1" 8; -} - - -/*************************************************************/ -// GMAC Message Station - -bucket "gmac_rfr_0" { - size 32; - "tx_stn_cpu_0" 2; - "tx_stn_cpu_1" 2; - "tx_stn_cpu_2" 4; - "tx_stn_cpu_3" 4; - "tx_stn_cpu_4" 4; - "tx_stn_cpu_5" 4; - "tx_stn_cpu_6" 4; - "tx_stn_cpu_7" 4; - "tx_stn_gmac" 4; -} - -bucket "gmac_tx_0" { - size 32; - "tx_stn_cpu_0" 4; - "tx_stn_cpu_1" 4; - "tx_stn_cpu_2" 4; - "tx_stn_cpu_3" 4; - "tx_stn_cpu_4" 4; - "tx_stn_cpu_5" 4; - "tx_stn_cpu_6" 4; - "tx_stn_cpu_7" 4; -} - -bucket "gmac_tx_1" { - size 32; - "tx_stn_cpu_0" 4; - "tx_stn_cpu_1" 4; - "tx_stn_cpu_2" 4; - "tx_stn_cpu_3" 4; - "tx_stn_cpu_4" 4; - "tx_stn_cpu_5" 4; - "tx_stn_cpu_6" 4; - "tx_stn_cpu_7" 4; -} - -bucket "gmac_tx_2" { - size 32; - "tx_stn_cpu_0" 4; - "tx_stn_cpu_1" 4; - "tx_stn_cpu_2" 4; - "tx_stn_cpu_3" 4; - "tx_stn_cpu_4" 4; - "tx_stn_cpu_5" 4; - "tx_stn_cpu_6" 4; - "tx_stn_cpu_7" 4; -} - -bucket "gmac_tx_3" { - size 32; - "tx_stn_cpu_0" 4; - "tx_stn_cpu_1" 4; - "tx_stn_cpu_2" 4; - "tx_stn_cpu_3" 4; - "tx_stn_cpu_4" 4; - "tx_stn_cpu_5" 4; - "tx_stn_cpu_6" 4; - "tx_stn_cpu_7" 4; -} - -bucket "gmac_rfr_1" { - size 32; - "tx_stn_cpu_0" 2; - "tx_stn_cpu_1" 2; - "tx_stn_cpu_2" 4; - "tx_stn_cpu_3" 4; - "tx_stn_cpu_4" 4; - "tx_stn_cpu_5" 4; - "tx_stn_cpu_6" 4; - "tx_stn_cpu_7" 4; - "tx_stn_gmac" 4; -} -/*********************************************/ -// xgmac -bucket "xgs_0_rfr" { - size 32; - "tx_stn_cpu_0" 2; - "tx_stn_cpu_1" 2; - "tx_stn_cpu_2" 4; - "tx_stn_cpu_3" 4; - "tx_stn_cpu_4" 4; - "tx_stn_cpu_5" 4; - "tx_stn_cpu_6" 4; - "tx_stn_cpu_7" 4; - "tx_stn_xgs_0" 4; -} - -bucket "xgs_0_tx_0" { - size 32; - "tx_stn_cpu_0" 4; - "tx_stn_cpu_1" 4; - "tx_stn_cpu_2" 4; - "tx_stn_cpu_3" 4; - "tx_stn_cpu_4" 4; - "tx_stn_cpu_5" 4; - "tx_stn_cpu_6" 4; - "tx_stn_cpu_7" 4; -} - -bucket "xgs_0_tx_1" { - size 16; - "tx_stn_cpu_0" 2; - "tx_stn_cpu_1" 2; - "tx_stn_cpu_2" 2; - "tx_stn_cpu_3" 2; - "tx_stn_cpu_4" 2; - "tx_stn_cpu_5" 2; - "tx_stn_cpu_6" 2; - "tx_stn_cpu_7" 2; -} - -bucket "xgs_0_tx_2" { - size 16; - "tx_stn_cpu_0" 2; - "tx_stn_cpu_1" 2; - "tx_stn_cpu_2" 2; - "tx_stn_cpu_3" 2; - "tx_stn_cpu_4" 2; - "tx_stn_cpu_5" 2; - "tx_stn_cpu_6" 2; - "tx_stn_cpu_7" 2; -} - -bucket "xgs_0_tx_3" { - size 16; - "tx_stn_cpu_0" 2; - "tx_stn_cpu_1" 2; - "tx_stn_cpu_2" 2; - "tx_stn_cpu_3" 2; - "tx_stn_cpu_4" 2; - "tx_stn_cpu_5" 2; - "tx_stn_cpu_6" 2; - "tx_stn_cpu_7" 2; -} - -bucket "xgs_0_tx_4" { - size 16; - "tx_stn_cpu_0" 2; - "tx_stn_cpu_1" 2; - "tx_stn_cpu_2" 2; - "tx_stn_cpu_3" 2; - "tx_stn_cpu_4" 2; - "tx_stn_cpu_5" 2; - "tx_stn_cpu_6" 2; - "tx_stn_cpu_7" 2; -} -bucket "xgs_0_tx_5" { - size 16; - "tx_stn_cpu_0" 2; - "tx_stn_cpu_1" 2; - "tx_stn_cpu_2" 2; - "tx_stn_cpu_3" 2; - "tx_stn_cpu_4" 2; - "tx_stn_cpu_5" 2; - "tx_stn_cpu_6" 2; - "tx_stn_cpu_7" 2; -} - -bucket "xgs_0_tx_6" { - size 16; - "tx_stn_cpu_0" 2; - "tx_stn_cpu_1" 2; - "tx_stn_cpu_2" 2; - "tx_stn_cpu_3" 2; - "tx_stn_cpu_4" 2; - "tx_stn_cpu_5" 2; - "tx_stn_cpu_6" 2; - "tx_stn_cpu_7" 2; -} - -bucket "xgs_0_tx_7" { - size 16; - "tx_stn_cpu_0" 2; - "tx_stn_cpu_1" 2; - "tx_stn_cpu_2" 2; - "tx_stn_cpu_3" 2; - "tx_stn_cpu_4" 2; - "tx_stn_cpu_5" 2; - "tx_stn_cpu_6" 2; - "tx_stn_cpu_7" 2; -} - -bucket "xgs_0_tx_8" { - size 16; - "tx_stn_cpu_0" 2; - "tx_stn_cpu_1" 2; - "tx_stn_cpu_2" 2; - "tx_stn_cpu_3" 2; - "tx_stn_cpu_4" 2; - "tx_stn_cpu_5" 2; - "tx_stn_cpu_6" 2; - "tx_stn_cpu_7" 2; -} - -bucket "xgs_0_tx_9" { - size 16; - "tx_stn_cpu_0" 2; - "tx_stn_cpu_1" 2; - "tx_stn_cpu_2" 2; - "tx_stn_cpu_3" 2; - "tx_stn_cpu_4" 2; - "tx_stn_cpu_5" 2; - "tx_stn_cpu_6" 2; - "tx_stn_cpu_7" 2; -} - -bucket "xgs_0_tx_10" { - size 16; - "tx_stn_cpu_0" 2; - "tx_stn_cpu_1" 2; - "tx_stn_cpu_2" 2; - "tx_stn_cpu_3" 2; - "tx_stn_cpu_4" 2; - "tx_stn_cpu_5" 2; - "tx_stn_cpu_6" 2; - "tx_stn_cpu_7" 2; -} - - -bucket "xgs_0_tx_11" { - size 16; - "tx_stn_cpu_0" 2; - "tx_stn_cpu_1" 2; - "tx_stn_cpu_2" 2; - "tx_stn_cpu_3" 2; - "tx_stn_cpu_4" 2; - "tx_stn_cpu_5" 2; - "tx_stn_cpu_6" 2; - "tx_stn_cpu_7" 2; -} - -bucket "xgs_0_tx_12" { - size 16; - "tx_stn_cpu_0" 2; - "tx_stn_cpu_1" 2; - "tx_stn_cpu_2" 2; - "tx_stn_cpu_3" 2; - "tx_stn_cpu_4" 2; - "tx_stn_cpu_5" 2; - "tx_stn_cpu_6" 2; - "tx_stn_cpu_7" 2; -} - -bucket "xgs_0_tx_13" { - size 16; - "tx_stn_cpu_0" 2; - "tx_stn_cpu_1" 2; - "tx_stn_cpu_2" 2; - "tx_stn_cpu_3" 2; - "tx_stn_cpu_4" 2; - "tx_stn_cpu_5" 2; - "tx_stn_cpu_6" 2; - "tx_stn_cpu_7" 2; -} - -bucket "xgs_0_tx_14" { - size 16; - "tx_stn_cpu_0" 2; - "tx_stn_cpu_1" 2; - "tx_stn_cpu_2" 2; - "tx_stn_cpu_3" 2; - "tx_stn_cpu_4" 2; - "tx_stn_cpu_5" 2; - "tx_stn_cpu_6" 2; - "tx_stn_cpu_7" 2; -} - - -bucket "xgs_1_rfr" { - size 32; - "tx_stn_cpu_0" 2; - "tx_stn_cpu_1" 2; - "tx_stn_cpu_2" 4; - "tx_stn_cpu_3" 4; - "tx_stn_cpu_4" 4; - "tx_stn_cpu_5" 4; - "tx_stn_cpu_6" 4; - "tx_stn_cpu_7" 4; - "tx_stn_xgs_1" 4; -} - -bucket "xgs_1_tx_0" { - size 32; - "tx_stn_cpu_0" 4; - "tx_stn_cpu_1" 4; - "tx_stn_cpu_2" 4; - "tx_stn_cpu_3" 4; - "tx_stn_cpu_4" 4; - "tx_stn_cpu_5" 4; - "tx_stn_cpu_6" 4; - "tx_stn_cpu_7" 4; -} - - -bucket "xgs_1_tx_1" { - size 16; - "tx_stn_cpu_0" 2; - "tx_stn_cpu_1" 2; - "tx_stn_cpu_2" 2; - "tx_stn_cpu_3" 2; - "tx_stn_cpu_4" 2; - "tx_stn_cpu_5" 2; - "tx_stn_cpu_6" 2; - "tx_stn_cpu_7" 2; -} - -bucket "xgs_1_tx_2" { - size 16; - "tx_stn_cpu_0" 2; - "tx_stn_cpu_1" 2; - "tx_stn_cpu_2" 2; - "tx_stn_cpu_3" 2; - "tx_stn_cpu_4" 2; - "tx_stn_cpu_5" 2; - "tx_stn_cpu_6" 2; - "tx_stn_cpu_7" 2; -} - -bucket "xgs_1_tx_3" { - size 16; - "tx_stn_cpu_0" 2; - "tx_stn_cpu_1" 2; - "tx_stn_cpu_2" 2; - "tx_stn_cpu_3" 2; - "tx_stn_cpu_4" 2; - "tx_stn_cpu_5" 2; - "tx_stn_cpu_6" 2; - "tx_stn_cpu_7" 2; -} - -bucket "xgs_1_tx_4" { - size 16; - "tx_stn_cpu_0" 2; - "tx_stn_cpu_1" 2; - "tx_stn_cpu_2" 2; - "tx_stn_cpu_3" 2; - "tx_stn_cpu_4" 2; - "tx_stn_cpu_5" 2; - "tx_stn_cpu_6" 2; - "tx_stn_cpu_7" 2; -} - -bucket "xgs_1_tx_5" { - size 16; - "tx_stn_cpu_0" 2; - "tx_stn_cpu_1" 2; - "tx_stn_cpu_2" 2; - "tx_stn_cpu_3" 2; - "tx_stn_cpu_4" 2; - "tx_stn_cpu_5" 2; - "tx_stn_cpu_6" 2; - "tx_stn_cpu_7" 2; -} - -bucket "xgs_1_tx_6" { - size 16; - "tx_stn_cpu_0" 2; - "tx_stn_cpu_1" 2; - "tx_stn_cpu_2" 2; - "tx_stn_cpu_3" 2; - "tx_stn_cpu_4" 2; - "tx_stn_cpu_5" 2; - "tx_stn_cpu_6" 2; - "tx_stn_cpu_7" 2; -} - -bucket "xgs_1_tx_7" { - size 16; - "tx_stn_cpu_0" 2; - "tx_stn_cpu_1" 2; - "tx_stn_cpu_2" 2; - "tx_stn_cpu_3" 2; - "tx_stn_cpu_4" 2; - "tx_stn_cpu_5" 2; - "tx_stn_cpu_6" 2; - "tx_stn_cpu_7" 2; -} - - -bucket "xgs_1_tx_8" { - size 16; - "tx_stn_cpu_0" 2; - "tx_stn_cpu_1" 2; - "tx_stn_cpu_2" 2; - "tx_stn_cpu_3" 2; - "tx_stn_cpu_4" 2; - "tx_stn_cpu_5" 2; - "tx_stn_cpu_6" 2; - "tx_stn_cpu_7" 2; -} - - -bucket "xgs_1_tx_9" { - size 16; - "tx_stn_cpu_0" 2; - "tx_stn_cpu_1" 2; - "tx_stn_cpu_2" 2; - "tx_stn_cpu_3" 2; - "tx_stn_cpu_4" 2; - "tx_stn_cpu_5" 2; - "tx_stn_cpu_6" 2; - "tx_stn_cpu_7" 2; -} - - -bucket "xgs_1_tx_10" { - size 16; - "tx_stn_cpu_0" 2; - "tx_stn_cpu_1" 2; - "tx_stn_cpu_2" 2; - "tx_stn_cpu_3" 2; - "tx_stn_cpu_4" 2; - "tx_stn_cpu_5" 2; - "tx_stn_cpu_6" 2; - "tx_stn_cpu_7" 2; -} - -bucket "xgs_1_tx_11" { - size 16; - "tx_stn_cpu_0" 2; - "tx_stn_cpu_1" 2; - "tx_stn_cpu_2" 2; - "tx_stn_cpu_3" 2; - "tx_stn_cpu_4" 2; - "tx_stn_cpu_5" 2; - "tx_stn_cpu_6" 2; - "tx_stn_cpu_7" 2; -} - -bucket "xgs_1_tx_12" { - size 16; - "tx_stn_cpu_0" 2; - "tx_stn_cpu_1" 2; - "tx_stn_cpu_2" 2; - "tx_stn_cpu_3" 2; - "tx_stn_cpu_4" 2; - "tx_stn_cpu_5" 2; - "tx_stn_cpu_6" 2; - "tx_stn_cpu_7" 2; -} - -bucket "xgs_1_tx_13" { - size 16; - "tx_stn_cpu_0" 2; - "tx_stn_cpu_1" 2; - "tx_stn_cpu_2" 2; - "tx_stn_cpu_3" 2; - "tx_stn_cpu_4" 2; - "tx_stn_cpu_5" 2; - "tx_stn_cpu_6" 2; - "tx_stn_cpu_7" 2; -} - -bucket "xgs_1_tx_14" { - size 16; - "tx_stn_cpu_0" 2; - "tx_stn_cpu_1" 2; - "tx_stn_cpu_2" 2; - "tx_stn_cpu_3" 2; - "tx_stn_cpu_4" 2; - "tx_stn_cpu_5" 2; - "tx_stn_cpu_6" 2; - "tx_stn_cpu_7" 2; -} - - - - - - -/*************************************************************/ -// Security Message Station - -bucket "sec_pipe_0" { - size 128; - "tx_stn_cpu_0" 16; - "tx_stn_cpu_1" 16; - "tx_stn_cpu_2" 16; - "tx_stn_cpu_3" 16; - "tx_stn_cpu_4" 16; - "tx_stn_cpu_5" 16; - "tx_stn_cpu_6" 16; - "tx_stn_cpu_7" 16; -} - -bucket "sec_rsa" { - size 128; - "tx_stn_cpu_0" 16; - "tx_stn_cpu_1" 16; - "tx_stn_cpu_2" 16; - "tx_stn_cpu_3" 16; - "tx_stn_cpu_4" 16; - "tx_stn_cpu_5" 16; - "tx_stn_cpu_6" 16; - "tx_stn_cpu_7" 16; -} - Property changes on: head/sys/mips/rmi/msgring.cfg ___________________________________________________________________ Deleted: svn:eol-style ## -1 +0,0 ## -native \ No newline at end of property Deleted: svn:keywords ## -1 +0,0 ## -FreeBSD=%H \ No newline at end of property Deleted: svn:mime-type ## -1 +0,0 ## -text/plain \ No newline at end of property Index: head/sys/mips/rmi/iodi.c =================================================================== --- head/sys/mips/rmi/iodi.c (revision 327460) +++ head/sys/mips/rmi/iodi.c (nonexistent) @@ -1,277 +0,0 @@ -/*- - * SPDX-License-Identifier: BSD-3-Clause - * - * Copyright (c) 2003-2009 RMI Corporation - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. Neither the name of RMI Corporation, nor the names of its contributors, - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - * - * RMI_BSD - */ - -#include -__FBSDID("$FreeBSD$"); - -#define __RMAN_RESOURCE_VISIBLE -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include /* for DELAY */ -#include - -#include -#include -#include -#include -#include -#include - -#include -#include - -extern bus_space_tag_t uart_bus_space_mem; - -static struct resource * -iodi_alloc_resource(device_t, device_t, int, int *, - rman_res_t, rman_res_t, rman_res_t, u_int); - -static int -iodi_activate_resource(device_t, device_t, int, int, - struct resource *); -static int -iodi_setup_intr(device_t, device_t, struct resource *, int, - driver_filter_t *, driver_intr_t *, void *, void **); - -struct iodi_softc *iodi_softc; /* There can be only one. */ - -/* - * We will manage the Flash/PCMCIA devices in IODI for now. - * The NOR flash, Compact flash etc. which can be connected on - * various chip selects on the peripheral IO, should have a - * separate bus later. - */ -static void -bridge_pcmcia_ack(int irq) -{ - xlr_reg_t *mmio = xlr_io_mmio(XLR_IO_FLASH_OFFSET); - - xlr_write_reg(mmio, 0x60, 0xffffffff); -} - -static int -iodi_setup_intr(device_t dev, device_t child, - struct resource *ires, int flags, driver_filter_t *filt, - driver_intr_t *intr, void *arg, void **cookiep) -{ - const char *name = device_get_name(child); - - if (strcmp(name, "uart") == 0) { - /* FIXME uart 1? */ - cpu_establish_hardintr("uart", filt, intr, arg, - PIC_UART_0_IRQ, flags, cookiep); - pic_setup_intr(PIC_IRT_UART_0_INDEX, PIC_UART_0_IRQ, 0x1, 1); - } else if (strcmp(name, "nlge") == 0) { - int irq; - - /* This is a hack to pass in the irq */ - irq = (intptr_t)ires->__r_i; - cpu_establish_hardintr("nlge", filt, intr, arg, irq, flags, - cookiep); - pic_setup_intr(irq - PIC_IRQ_BASE, irq, 0x1, 1); - } else if (strcmp(name, "ehci") == 0) { - cpu_establish_hardintr("ehci", filt, intr, arg, PIC_USB_IRQ, flags, - cookiep); - pic_setup_intr(PIC_USB_IRQ - PIC_IRQ_BASE, PIC_USB_IRQ, 0x1, 1); - } else if (strcmp(name, "ata") == 0) { - xlr_establish_intr("ata", filt, intr, arg, PIC_PCMCIA_IRQ, flags, - cookiep, bridge_pcmcia_ack); - pic_setup_intr(PIC_PCMCIA_IRQ - PIC_IRQ_BASE, PIC_PCMCIA_IRQ, 0x1, 1); - } - return (0); -} - -static struct resource * -iodi_alloc_resource(device_t bus, device_t child, int type, int *rid, - rman_res_t start, rman_res_t end, rman_res_t count, u_int flags) -{ - struct resource *res = malloc(sizeof(*res), M_DEVBUF, M_WAITOK); - const char *name = device_get_name(child); - int unit; - -#ifdef DEBUG - switch (type) { - case SYS_RES_IRQ: - device_printf(bus, "IRQ resource - for %s %jx-%jx\n", - device_get_nameunit(child), start, end); - break; - - case SYS_RES_IOPORT: - device_printf(bus, "IOPORT resource - for %s %jx-%jx\n", - device_get_nameunit(child), start, end); - break; - - case SYS_RES_MEMORY: - device_printf(bus, "MEMORY resource - for %s %jx-%jx\n", - device_get_nameunit(child), start, end); - break; - } -#endif - - if (strcmp(name, "uart") == 0) { - if ((unit = device_get_unit(child)) == 0) { /* uart 0 */ - res->r_bushandle = (xlr_io_base + XLR_IO_UART_0_OFFSET); - } else if (unit == 1) { - res->r_bushandle = (xlr_io_base + XLR_IO_UART_1_OFFSET); - } else - printf("%s: Unknown uart unit\n", __FUNCTION__); - - res->r_bustag = uart_bus_space_mem; - } else if (strcmp(name, "ehci") == 0) { - res->r_bushandle = MIPS_PHYS_TO_KSEG1(0x1ef24000); - res->r_bustag = rmi_pci_bus_space; - } else if (strcmp(name, "cfi") == 0) { - res->r_bushandle = MIPS_PHYS_TO_KSEG1(0x1c000000); - res->r_bustag = 0; - } else if (strcmp(name, "ata") == 0) { - res->r_bushandle = MIPS_PHYS_TO_KSEG1(0x1d000000); - res->r_bustag = rmi_pci_bus_space; /* byte swapping (not really PCI) */ - } - /* res->r_start = *rid; */ - return (res); -} - -static int -iodi_activate_resource(device_t bus, device_t child, int type, int rid, - struct resource *r) -{ - return (0); -} - -/* prototypes */ -static int iodi_probe(device_t); -static int iodi_attach(device_t); -static int iodi_detach(device_t); -static void iodi_identify(driver_t *, device_t); - -int -iodi_probe(device_t dev) -{ - return (BUS_PROBE_NOWILDCARD); -} - -void -iodi_identify(driver_t * driver, device_t parent) -{ - - BUS_ADD_CHILD(parent, 0, "iodi", 0); -} - -int -iodi_attach(device_t dev) -{ - device_t tmpd; - int i; - - /* - * Attach each devices - */ - device_add_child(dev, "uart", 0); - device_add_child(dev, "xlr_i2c", 0); - device_add_child(dev, "xlr_i2c", 1); - device_add_child(dev, "pcib", 0); - device_add_child(dev, "rmisec", -1); - - if (xlr_board_info.usb) - device_add_child(dev, "ehci", 0); - - if (xlr_board_info.cfi) - device_add_child(dev, "cfi", 0); - - if (xlr_board_info.ata) - device_add_child(dev, "ata", 0); - - for (i = 0; i < 3; i++) { - if (xlr_board_info.gmac_block[i].enabled == 0) - continue; - tmpd = device_add_child(dev, "nlna", i); - device_set_ivars(tmpd, &xlr_board_info.gmac_block[i]); - } - - bus_generic_probe(dev); - bus_generic_attach(dev); - return 0; -} - -int -iodi_detach(device_t dev) -{ - device_t nlna_dev; - int error, i, ret; - - error = 0; - ret = 0; - for (i = 0; i < 3; i++) { - nlna_dev = device_find_child(dev, "nlna", i); - if (nlna_dev != NULL) - error = bus_generic_detach(nlna_dev); - if (error) - ret = error; - } - return ret; -} - -static device_method_t iodi_methods[] = { - DEVMETHOD(device_probe, iodi_probe), - DEVMETHOD(device_attach, iodi_attach), - DEVMETHOD(device_detach, iodi_detach), - DEVMETHOD(device_identify, iodi_identify), - DEVMETHOD(bus_alloc_resource, iodi_alloc_resource), - DEVMETHOD(bus_activate_resource, iodi_activate_resource), - DEVMETHOD(bus_add_child, bus_generic_add_child), - DEVMETHOD(bus_setup_intr, iodi_setup_intr), - {0, 0}, -}; - -static driver_t iodi_driver = { - "iodi", - iodi_methods, - 1 /* no softc */ -}; -static devclass_t iodi_devclass; - -DRIVER_MODULE(iodi, nexus, iodi_driver, iodi_devclass, 0, 0); Property changes on: head/sys/mips/rmi/iodi.c ___________________________________________________________________ Deleted: svn:eol-style ## -1 +0,0 ## -native \ No newline at end of property Deleted: svn:keywords ## -1 +0,0 ## -FreeBSD=%H \ No newline at end of property Deleted: svn:mime-type ## -1 +0,0 ## -text/plain \ No newline at end of property Index: head/sys/mips/rmi/uart_bus_xlr_iodi.c =================================================================== --- head/sys/mips/rmi/uart_bus_xlr_iodi.c (revision 327460) +++ head/sys/mips/rmi/uart_bus_xlr_iodi.c (nonexistent) @@ -1,82 +0,0 @@ -/*- - * SPDX-License-Identifier: BSD-2-Clause-FreeBSD - * - * Copyright (c) 2006 Raza Microelectronics - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES - * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. - * IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, - * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - */ - -#include -__FBSDID("$FreeBSD$"); - -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include -#include -#include -#include - -static int uart_iodi_probe(device_t dev); - -static device_method_t uart_iodi_methods[] = { - /* Device interface */ - DEVMETHOD(device_probe, uart_iodi_probe), - DEVMETHOD(device_attach, uart_bus_attach), - DEVMETHOD(device_detach, uart_bus_detach), - {0, 0} -}; - -static driver_t uart_iodi_driver = { - uart_driver_name, - uart_iodi_methods, - sizeof(struct uart_softc), -}; - - -extern SLIST_HEAD(uart_devinfo_list, uart_devinfo) uart_sysdevs; -static int -uart_iodi_probe(device_t dev) -{ - struct uart_softc *sc; - sc = device_get_softc(dev); - sc->sc_sysdev = SLIST_FIRST(&uart_sysdevs); - sc->sc_class = &uart_ns8250_class; - bcopy(&sc->sc_sysdev->bas, &sc->sc_bas, sizeof(sc->sc_bas)); - sc->sc_sysdev->bas.bst = rmi_bus_space; - sc->sc_sysdev->bas.bsh = MIPS_PHYS_TO_KSEG1(XLR_UART0ADDR); - sc->sc_bas.bst = rmi_bus_space; - sc->sc_bas.bsh = MIPS_PHYS_TO_KSEG1(XLR_UART0ADDR); - /* regshft = 2, rclk = 66000000, rid = 0, chan = 0 */ - return (uart_bus_probe(dev, 2, 0, 66000000, 0, 0)); -} - -DRIVER_MODULE(uart, iodi, uart_iodi_driver, uart_devclass, 0, 0); Property changes on: head/sys/mips/rmi/uart_bus_xlr_iodi.c ___________________________________________________________________ Deleted: svn:eol-style ## -1 +0,0 ## -native \ No newline at end of property Deleted: svn:keywords ## -1 +0,0 ## -FreeBSD=%H \ No newline at end of property Deleted: svn:mime-type ## -1 +0,0 ## -text/plain \ No newline at end of property Index: head/sys/mips/rmi/Makefile.msgring =================================================================== --- head/sys/mips/rmi/Makefile.msgring (revision 327460) +++ head/sys/mips/rmi/Makefile.msgring (nonexistent) @@ -1,14 +0,0 @@ -RM = rm -MSGRNG_CFG = msgring.cfg - -MSGRNG_CFG_C = $(patsubst %.cfg,%.c,$(MSGRNG_CFG)) - -#all: msgring.l msgring.y msgring.cfg -all: $(MSGRNG_CFG) - flex -omsgring.lex.c msgring.l - bison -d -omsgring.yacc.c msgring.y - gcc -g3 msgring.lex.c msgring.yacc.c -o msgring - ./msgring -i $(MSGRNG_CFG) -o $(MSGRNG_CFG_C) - -clean: - $(RM) -f msgring.lex.c msgring.yacc.c msgring.yacc.h msgring msgring.o* Property changes on: head/sys/mips/rmi/Makefile.msgring ___________________________________________________________________ Deleted: svn:eol-style ## -1 +0,0 ## -native \ No newline at end of property Deleted: svn:keywords ## -1 +0,0 ## -FreeBSD=%H \ No newline at end of property Deleted: svn:mime-type ## -1 +0,0 ## -text/plain \ No newline at end of property Index: head/sys/mips/rmi/xlr_machdep.c =================================================================== --- head/sys/mips/rmi/xlr_machdep.c (revision 327460) +++ head/sys/mips/rmi/xlr_machdep.c (nonexistent) @@ -1,626 +0,0 @@ -/*- - * SPDX-License-Identifier: BSD-2-Clause-FreeBSD - * - * Copyright (c) 2006-2009 RMI Corporation - * Copyright (c) 2002-2004 Juli Mallett - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - * - */ -#include -__FBSDID("$FreeBSD$"); - -#include "opt_ddb.h" - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include /* cinit() */ -#include -#include -#include -#include -#include - -#include -#include - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include -#include -#include -#include - -void mpwait(void); -unsigned long xlr_io_base = (unsigned long)(DEFAULT_XLR_IO_BASE); - -/* 4KB static data aread to keep a copy of the bootload env until - the dynamic kenv is setup */ -char boot1_env[4096]; -int rmi_spin_mutex_safe=0; -struct mtx xlr_pic_lock; - -/* - * Parameters from boot loader - */ -struct boot1_info xlr_boot1_info; -int xlr_run_mode; -int xlr_argc; -int32_t *xlr_argv, *xlr_envp; -uint64_t cpu_mask_info; -uint32_t xlr_online_cpumask; -uint32_t xlr_core_cpu_mask = 0x1; /* Core 0 thread 0 is always there */ - -int xlr_shtlb_enabled; -int xlr_ncores; -int xlr_threads_per_core; -uint32_t xlr_hw_thread_mask; -int xlr_cpuid_to_hwtid[MAXCPU]; -int xlr_hwtid_to_cpuid[MAXCPU]; - -static void -xlr_setup_mmu_split(void) -{ - uint64_t mmu_setup; - int val = 0; - - if (xlr_threads_per_core == 4 && xlr_shtlb_enabled == 0) - return; /* no change from boot setup */ - - switch (xlr_threads_per_core) { - case 1: - val = 0; break; - case 2: - val = 2; break; - case 4: - val = 3; break; - } - - mmu_setup = read_xlr_ctrl_register(4, 0); - mmu_setup = mmu_setup & ~0x06; - mmu_setup |= (val << 1); - - /* turn on global mode */ - if (xlr_shtlb_enabled) - mmu_setup |= 0x01; - - write_xlr_ctrl_register(4, 0, mmu_setup); -} - -static void -xlr_parse_mmu_options(void) -{ -#ifdef notyet - char *hw_env, *start, *end; -#endif - uint32_t cpu_map; - uint8_t core0_thr_mask, core_thr_mask; - int i, j, k; - - /* First check for the shared TLB setup */ - xlr_shtlb_enabled = 0; -#ifdef notyet - /* - * We don't support sharing TLB per core - TODO - */ - xlr_shtlb_enabled = 0; - if ((hw_env = kern_getenv("xlr.shtlb")) != NULL) { - start = hw_env; - tmp = strtoul(start, &end, 0); - if (start != end) - xlr_shtlb_enabled = (tmp != 0); - else - printf("Bad value for xlr.shtlb [%s]\n", hw_env); - freeenv(hw_env); - } -#endif - /* - * XLR supports splitting the 64 TLB entries across one, two or four - * threads (split mode). XLR also allows the 64 TLB entries to be shared - * across all threads in the core using a global flag (shared TLB mode). - * We will support 1/2/4 threads in split mode or shared mode. - * - */ - xlr_ncores = 1; - cpu_map = xlr_boot1_info.cpu_online_map; - -#ifndef SMP /* Uniprocessor! */ - if (cpu_map != 0x1) { - printf("WARNING: Starting uniprocessor kernel on cpumask [0x%lx]!\n" - "WARNING: Other CPUs will be unused.\n", (u_long)cpu_map); - cpu_map = 0x1; - } -#endif - core0_thr_mask = cpu_map & 0xf; - switch (core0_thr_mask) { - case 1: - xlr_threads_per_core = 1; break; - case 3: - xlr_threads_per_core = 2; break; - case 0xf: - xlr_threads_per_core = 4; break; - default: - goto unsupp; - } - - /* Verify other cores CPU masks */ - for (i = 1; i < XLR_MAX_CORES; i++) { - core_thr_mask = (cpu_map >> (i*4)) & 0xf; - if (core_thr_mask) { - if (core_thr_mask != core0_thr_mask) - goto unsupp; - xlr_ncores++; - } - } - xlr_hw_thread_mask = cpu_map; - - /* setup hardware processor id to cpu id mapping */ - for (i = 0; i< MAXCPU; i++) - xlr_cpuid_to_hwtid[i] = - xlr_hwtid_to_cpuid [i] = -1; - for (i = 0, k = 0; i < XLR_MAX_CORES; i++) { - if (((cpu_map >> (i*4)) & 0xf) == 0) - continue; - for (j = 0; j < xlr_threads_per_core; j++) { - xlr_cpuid_to_hwtid[k] = i*4 + j; - xlr_hwtid_to_cpuid[i*4 + j] = k; - k++; - } - } - - /* setup for the startup core */ - xlr_setup_mmu_split(); - return; - -unsupp: - printf("ERROR : Unsupported CPU mask [use 1,2 or 4 threads per core].\n" - "\tcore0 thread mask [%lx], boot cpu mask [%lx]\n" - "\tUsing default, 16 TLB entries per CPU, split mode\n", - (u_long)core0_thr_mask, (u_long)cpu_map); - panic("Invalid CPU mask - halting.\n"); - return; -} - -static void -xlr_set_boot_flags(void) -{ - char *p; - - p = kern_getenv("bootflags"); - if (p == NULL) - p = kern_getenv("boot_flags"); /* old style */ - if (p == NULL) - return; - - for (; p && *p != '\0'; p++) { - switch (*p) { - case 'd': - case 'D': - boothowto |= RB_KDB; - break; - case 'g': - case 'G': - boothowto |= RB_GDB; - break; - case 'v': - case 'V': - boothowto |= RB_VERBOSE; - break; - - case 's': /* single-user (default, supported for sanity) */ - case 'S': - boothowto |= RB_SINGLE; - break; - - default: - printf("Unrecognized boot flag '%c'.\n", *p); - break; - } - } - - freeenv(p); - return; -} -extern uint32_t _end; - -static void -mips_init(void) -{ - init_param1(); - init_param2(physmem); - - mips_cpu_init(); - cpuinfo.cache_coherent_dma = TRUE; - pmap_bootstrap(); -#ifdef DDB - kdb_init(); - if (boothowto & RB_KDB) { - kdb_enter("Boot flags requested debugger", NULL); - } -#endif - mips_proc0_init(); - mutex_init(); -} - -u_int -platform_get_timecount(struct timecounter *tc __unused) -{ - - return (0xffffffffU - pic_timer_count32(PIC_CLOCK_TIMER)); -} - -static void -xlr_pic_init(void) -{ - struct timecounter pic_timecounter = { - platform_get_timecount, /* get_timecount */ - 0, /* no poll_pps */ - ~0U, /* counter_mask */ - PIC_TIMER_HZ, /* frequency */ - "XLRPIC", /* name */ - 2000, /* quality (adjusted in code) */ - }; - xlr_reg_t *mmio = xlr_io_mmio(XLR_IO_PIC_OFFSET); - int i, irq; - - write_c0_eimr64(0ULL); - mtx_init(&xlr_pic_lock, "pic", NULL, MTX_SPIN); - xlr_write_reg(mmio, PIC_CTRL, 0); - - /* Initialize all IRT entries */ - for (i = 0; i < PIC_NUM_IRTS; i++) { - irq = PIC_INTR_TO_IRQ(i); - - /* - * Disable all IRTs. Set defaults (local scheduling, high - * polarity, level * triggered, and CPU irq) - */ - xlr_write_reg(mmio, PIC_IRT_1(i), (1 << 30) | (1 << 6) | irq); - /* Bind all PIC irqs to cpu 0 */ - xlr_write_reg(mmio, PIC_IRT_0(i), 0x01); - } - - /* Setup timer 7 of PIC as a timestamp, no interrupts */ - pic_init_timer(PIC_CLOCK_TIMER); - pic_set_timer(PIC_CLOCK_TIMER, ~UINT64_C(0)); - platform_timecounter = &pic_timecounter; -} - -static void -xlr_mem_init(void) -{ - struct xlr_boot1_mem_map *boot_map; - vm_size_t physsz = 0; - int i, j; - - /* get physical memory info from boot loader */ - boot_map = (struct xlr_boot1_mem_map *) - (unsigned long)xlr_boot1_info.psb_mem_map; - for (i = 0, j = 0; i < boot_map->num_entries; i++, j += 2) { - if (boot_map->physmem_map[i].type != BOOT1_MEM_RAM) - continue; - if (j == 14) { - printf("*** ERROR *** memory map too large ***\n"); - break; - } - if (j == 0) { - /* start after kernel end */ - phys_avail[0] = (vm_paddr_t) - MIPS_KSEG0_TO_PHYS(&_end) + 0x20000; - /* boot loader start */ - /* HACK to Use bootloaders memory region */ - if (boot_map->physmem_map[0].size == 0x0c000000) { - boot_map->physmem_map[0].size = 0x0ff00000; - } - phys_avail[1] = boot_map->physmem_map[0].addr + - boot_map->physmem_map[0].size; - printf("First segment: addr:%#jx -> %#jx \n", - (uintmax_t)phys_avail[0], - (uintmax_t)phys_avail[1]); - - dump_avail[0] = phys_avail[0]; - dump_avail[1] = phys_avail[1]; - } else { -#if !defined(__mips_n64) && !defined(__mips_n32) /* !PHYSADDR_64_BIT */ - /* - * In 32 bit physical address mode we cannot use - * mem > 0xffffffff - */ - if (boot_map->physmem_map[i].addr > 0xfffff000U) { - printf("Memory: start %#jx size %#jx ignored" - "(>4GB)\n", - (intmax_t)boot_map->physmem_map[i].addr, - (intmax_t)boot_map->physmem_map[i].size); - continue; - } - if (boot_map->physmem_map[i].addr + - boot_map->physmem_map[i].size > 0xfffff000U) { - boot_map->physmem_map[i].size = 0xfffff000U - - boot_map->physmem_map[i].addr; - printf("Memory: start %#jx limited to 4GB\n", - (intmax_t)boot_map->physmem_map[i].addr); - } -#endif /* !PHYSADDR_64_BIT */ - phys_avail[j] = (vm_paddr_t) - boot_map->physmem_map[i].addr; - phys_avail[j + 1] = phys_avail[j] + - boot_map->physmem_map[i].size; - printf("Next segment : addr:%#jx -> %#jx\n", - (uintmax_t)phys_avail[j], - (uintmax_t)phys_avail[j+1]); - } - - dump_avail[j] = phys_avail[j]; - dump_avail[j+1] = phys_avail[j+1]; - - physsz += boot_map->physmem_map[i].size; - } - - phys_avail[j] = phys_avail[j + 1] = 0; - realmem = physmem = btoc(physsz); -} - -void -platform_start(__register_t a0 __unused, - __register_t a1 __unused, - __register_t a2 __unused, - __register_t a3 __unused) -{ - int i; -#ifdef SMP - uint32_t tmp; - void (*wakeup) (void *, void *, unsigned int); -#endif - - /* Save boot loader and other stuff from scratch regs */ - xlr_boot1_info = *(struct boot1_info *)(intptr_t)(int)read_c0_register32(MIPS_COP_0_OSSCRATCH, 0); - cpu_mask_info = read_c0_register64(MIPS_COP_0_OSSCRATCH, 1); - xlr_online_cpumask = read_c0_register32(MIPS_COP_0_OSSCRATCH, 2); - xlr_run_mode = read_c0_register32(MIPS_COP_0_OSSCRATCH, 3); - xlr_argc = read_c0_register32(MIPS_COP_0_OSSCRATCH, 4); - /* - * argv and envp are passed in array of 32bit pointers - */ - xlr_argv = (int32_t *)(intptr_t)(int)read_c0_register32(MIPS_COP_0_OSSCRATCH, 5); - xlr_envp = (int32_t *)(intptr_t)(int)read_c0_register32(MIPS_COP_0_OSSCRATCH, 6); - - /* Initialize pcpu stuff */ - mips_pcpu0_init(); - - /* initialize console so that we have printf */ - boothowto |= (RB_SERIAL | RB_MULTIPLE); /* Use multiple consoles */ - - /* clockrate used by delay, so initialize it here */ - cpu_clock = xlr_boot1_info.cpu_frequency / 1000000; - - /* - * Note the time counter on CPU0 runs not at system clock speed, but - * at PIC time counter speed (which is returned by - * platform_get_frequency(). Thus we do not use - * xlr_boot1_info.cpu_frequency here. - */ - mips_timer_early_init(xlr_boot1_info.cpu_frequency); - - /* Init console please */ - cninit(); - init_static_kenv(boot1_env, sizeof(boot1_env)); - printf("Environment (from %d args):\n", xlr_argc - 1); - if (xlr_argc == 1) - printf("\tNone\n"); - for (i = 1; i < xlr_argc; i++) { - char *n, *arg; - - arg = (char *)(intptr_t)xlr_argv[i]; - printf("\t%s\n", arg); - n = strsep(&arg, "="); - if (arg == NULL) - kern_setenv(n, "1"); - else - kern_setenv(n, arg); - } - - xlr_set_boot_flags(); - xlr_parse_mmu_options(); - - xlr_mem_init(); - /* Set up hz, among others. */ - mips_init(); - -#ifdef SMP - /* - * If thread 0 of any core is not available then mark whole core as - * not available - */ - tmp = xlr_boot1_info.cpu_online_map; - for (i = 4; i < MAXCPU; i += 4) { - if ((tmp & (0xf << i)) && !(tmp & (0x1 << i))) { - /* - * Oops.. thread 0 is not available. Disable whole - * core - */ - tmp = tmp & ~(0xf << i); - printf("WARNING: Core %d is disabled because thread 0" - " of this core is not enabled.\n", i / 4); - } - } - xlr_boot1_info.cpu_online_map = tmp; - - /* Wakeup Other cpus, and put them in bsd park code. */ - wakeup = ((void (*) (void *, void *, unsigned int)) - (unsigned long)(xlr_boot1_info.wakeup)); - printf("Waking up CPUs 0x%jx.\n", - (intmax_t)xlr_boot1_info.cpu_online_map & ~(0x1U)); - if (xlr_boot1_info.cpu_online_map & ~(0x1U)) - wakeup(mpwait, 0, - (unsigned int)xlr_boot1_info.cpu_online_map); -#endif - - /* xlr specific post initialization */ - /* initialize other on chip stuff */ - xlr_board_info_setup(); - xlr_msgring_config(); - xlr_pic_init(); - xlr_msgring_cpu_init(); - - mips_timer_init_params(xlr_boot1_info.cpu_frequency, 0); - - printf("Platform specific startup now completes\n"); -} - -void -platform_cpu_init() -{ -} - -void -platform_reset(void) -{ - xlr_reg_t *mmio = xlr_io_mmio(XLR_IO_GPIO_OFFSET); - - /* write 1 to GPIO software reset register */ - xlr_write_reg(mmio, 8, 1); -} - -#ifdef SMP -int xlr_ap_release[MAXCPU]; - -int -platform_start_ap(int cpuid) -{ - int hwid = xlr_cpuid_to_hwtid[cpuid]; - - if (xlr_boot1_info.cpu_online_map & (1<> 32; - low = value & 0xffffffff; - - __asm__ __volatile__( - ".set push\n\t" - ".set noreorder\n\t" - ".set mips64\n\t" - "dsll32 $9, %0, 0\n\t" - "dsll32 $8, %1, 0\n\t" - "dsrl32 $8, $8, 0\n\t" - "or $8, $9, $8\n\t" - "move $9, %2\n\t" - ".word 0x71280019\n\t" /* mtcr $8, $9 */ - ".set pop\n" - : /* No outputs */ - : "r" (high), "r" (low), "r"((block << 8) | reg) - : "$8", "$9"); -} -#endif /* defined(__mips_n64) || defined(__mips_n32) */ - -/* - * 32 bit read write for c0 - */ -#define read_c0_register32(reg, sel) \ -({ \ - uint32_t __rv; \ - __asm__ __volatile__( \ - ".set push\n\t" \ - ".set mips32\n\t" \ - "mfc0 %0, $%1, %2\n\t" \ - ".set pop\n" \ - : "=r" (__rv) : "i" (reg), "i" (sel) ); \ - __rv; \ - }) - -#define write_c0_register32(reg, sel, value) \ - __asm__ __volatile__( \ - ".set push\n\t" \ - ".set mips32\n\t" \ - "mtc0 %0, $%1, %2\n\t" \ - ".set pop\n" \ - : : "r" (value), "i" (reg), "i" (sel) ); - -#define read_c2_register32(reg, sel) \ -({ \ - uint32_t __rv; \ - __asm__ __volatile__( \ - ".set push\n\t" \ - ".set mips32\n\t" \ - "mfc2 %0, $%1, %2\n\t" \ - ".set pop\n" \ - : "=r" (__rv) : "i" (reg), "i" (sel) ); \ - __rv; \ - }) - -#define write_c2_register32(reg, sel, value) \ - __asm__ __volatile__( \ - ".set push\n\t" \ - ".set mips32\n\t" \ - "mtc2 %0, $%1, %2\n\t" \ - ".set pop\n" \ - : : "r" (value), "i" (reg), "i" (sel) ); - -#if defined(__mips_n64) || defined(__mips_n32) -/* - * On 64 bit compilation, the operations are simple - */ -#define read_c0_register64(reg, sel) \ -({ \ - uint64_t __rv; \ - __asm__ __volatile__( \ - ".set push\n\t" \ - ".set mips64\n\t" \ - "dmfc0 %0, $%1, %2\n\t" \ - ".set pop\n" \ - : "=r" (__rv) : "i" (reg), "i" (sel) ); \ - __rv; \ - }) - -#define write_c0_register64(reg, sel, value) \ - __asm__ __volatile__( \ - ".set push\n\t" \ - ".set mips64\n\t" \ - "dmtc0 %0, $%1, %2\n\t" \ - ".set pop\n" \ - : : "r" (value), "i" (reg), "i" (sel) ); - -#define read_c2_register64(reg, sel) \ -({ \ - uint64_t __rv; \ - __asm__ __volatile__( \ - ".set push\n\t" \ - ".set mips64\n\t" \ - "dmfc2 %0, $%1, %2\n\t" \ - ".set pop\n" \ - : "=r" (__rv) : "i" (reg), "i" (sel) ); \ - __rv; \ - }) - -#define write_c2_register64(reg, sel, value) \ - __asm__ __volatile__( \ - ".set push\n\t" \ - ".set mips64\n\t" \ - "dmtc2 %0, $%1, %2\n\t" \ - ".set pop\n" \ - : : "r" (value), "i" (reg), "i" (sel) ); - -#else /* ! (defined(__mips_n64) || defined(__mips_n32)) */ - -/* - * 32 bit compilation, 64 bit values has to split - */ -#define read_c0_register64(reg, sel) \ -({ \ - uint32_t __high, __low; \ - __asm__ __volatile__( \ - ".set push\n\t" \ - ".set noreorder\n\t" \ - ".set mips64\n\t" \ - "dmfc0 $8, $%2, %3\n\t" \ - "dsra32 %0, $8, 0\n\t" \ - "sll %1, $8, 0\n\t" \ - ".set pop\n" \ - : "=r"(__high), "=r"(__low): "i"(reg), "i"(sel) \ - : "$8"); \ - ((uint64_t)__high << 32) | __low; \ -}) - -#define write_c0_register64(reg, sel, value) \ -do { \ - uint32_t __high = value >> 32; \ - uint32_t __low = value & 0xffffffff; \ - __asm__ __volatile__( \ - ".set push\n\t" \ - ".set noreorder\n\t" \ - ".set mips64\n\t" \ - "dsll32 $8, %1, 0\n\t" \ - "dsll32 $9, %0, 0\n\t" \ - "dsrl32 $8, $8, 0\n\t" \ - "or $8, $8, $9\n\t" \ - "dmtc0 $8, $%2, %3\n\t" \ - ".set pop" \ - :: "r"(__high), "r"(__low), "i"(reg), "i"(sel) \ - :"$8", "$9"); \ -} while(0) - -#define read_c2_register64(reg, sel) \ -({ \ - uint32_t __high, __low; \ - __asm__ __volatile__( \ - ".set push\n\t" \ - ".set noreorder\n\t" \ - ".set mips64\n\t" \ - "dmfc2 $8, $%2, %3\n\t" \ - "dsra32 %0, $8, 0\n\t" \ - "sll %1, $8, 0\n\t" \ - ".set pop\n" \ - : "=r"(__high), "=r"(__low): "i"(reg), "i"(sel) \ - : "$8"); \ - ((uint64_t)__high << 32) | __low; \ -}) - -#define write_c2_register64(reg, sel, value) \ -do { \ - uint32_t __high = value >> 32; \ - uint32_t __low = value & 0xffffffff; \ - __asm__ __volatile__( \ - ".set push\n\t" \ - ".set noreorder\n\t" \ - ".set mips64\n\t" \ - "dsll32 $8, %1, 0\n\t" \ - "dsll32 $9, %0, 0\n\t" \ - "dsrl32 $8, $8, 0\n\t" \ - "or $8, $8, $9\n\t" \ - "dmtc2 $8, $%2, %3\n\t" \ - ".set pop" \ - :: "r"(__high), "r"(__low), "i"(reg), "i"(sel) \ - :"$8", "$9"); \ -} while(0) - -#endif /* defined(__mips_n64) || defined(__mips_n32) */ - -static __inline int -xlr_cpu_id(void) -{ - - return (read_c0_register32(15, 1) & 0x1f); -} - -static __inline int -xlr_core_id(void) -{ - - return (xlr_cpu_id() / 4); -} - -static __inline int -xlr_thr_id(void) -{ - - return (read_c0_register32(15, 1) & 0x3); -} - -/* Additional registers on the XLR */ -#define MIPS_COP_0_OSSCRATCH 22 -#define XLR_CACHELINE_SIZE 32 - -/* functions to write to and read from the extended - * cp0 registers. - * EIRR : Extended Interrupt Request Register - * cp0 register 9 sel 6 - * bits 0...7 are same as cause register 8...15 - * EIMR : Extended Interrupt Mask Register - * cp0 register 9 sel 7 - * bits 0...7 are same as status register 8...15 - */ -static __inline uint64_t -read_c0_eirr64(void) -{ - - return (read_c0_register64(9, 6)); -} - -static __inline void -write_c0_eirr64(uint64_t val) -{ - - write_c0_register64(9, 6, val); -} - -static __inline uint64_t -read_c0_eimr64(void) -{ - - return (read_c0_register64(9, 7)); -} - -static __inline void -write_c0_eimr64(uint64_t val) -{ - - write_c0_register64(9, 7, val); -} - -static __inline int -xlr_test_and_set(int *lock) -{ - int oldval = 0; - - __asm__ __volatile__( - ".set push\n" - ".set noreorder\n" - "move $9, %2\n" - "li $8, 1\n" - // "swapw $8, $9\n" - ".word 0x71280014\n" - "move %1, $8\n" - ".set pop\n" - : "+m"(*lock), "=r"(oldval) - : "r"((unsigned long)lock) - : "$8", "$9" - ); - - return (oldval == 0 ? 1 /* success */ : 0 /* failure */); -} - -static __inline uint32_t -xlr_mfcr(uint32_t reg) -{ - uint32_t val; - - __asm__ __volatile__( - "move $8, %1\n" - ".word 0x71090018\n" - "move %0, $9\n" - : "=r"(val) - : "r"(reg):"$8", "$9"); - - return val; -} - -static __inline void -xlr_mtcr(uint32_t reg, uint32_t val) -{ - __asm__ __volatile__( - "move $8, %1\n" - "move $9, %0\n" - ".word 0x71090019\n" - :: "r"(val), "r"(reg) - : "$8", "$9"); -} - -/* - * Atomic increment a unsigned int - */ -static __inline unsigned int -xlr_ldaddwu(unsigned int value, unsigned int *addr) -{ - __asm__ __volatile__( - ".set push\n" - ".set noreorder\n" - "move $8, %2\n" - "move $9, %3\n" - ".word 0x71280011\n" /* ldaddwu $8, $9 */ - "move %0, $8\n" - ".set pop\n" - : "=&r"(value), "+m"(*addr) - : "0"(value), "r" ((unsigned long)addr) - : "$8", "$9"); - - return (value); -} - -#if defined(__mips_n64) -static __inline uint32_t -xlr_paddr_lw(uint64_t paddr) -{ - - paddr |= 0x9800000000000000ULL; - return (*(uint32_t *)(uintptr_t)paddr); -} - -static __inline uint64_t -xlr_paddr_ld(uint64_t paddr) -{ - - paddr |= 0x9800000000000000ULL; - return (*(uint64_t *)(uintptr_t)paddr); -} - -#elif defined(__mips_n32) -static __inline uint32_t -xlr_paddr_lw(uint64_t paddr) -{ - uint32_t val; - - paddr |= 0x9800000000000000ULL; - __asm__ __volatile__( - ".set push \n\t" - ".set mips64 \n\t" - "lw %0, 0(%1) \n\t" - ".set pop \n" - : "=r"(val) - : "r"(paddr)); - - return (val); -} - -static __inline uint64_t -xlr_paddr_ld(uint64_t paddr) -{ - uint64_t val; - - paddr |= 0x9800000000000000ULL; - __asm__ __volatile__( - ".set push \n\t" - ".set mips64 \n\t" - "ld %0, 0(%1) \n\t" - ".set pop \n" - : "=r"(val) - : "r"(paddr)); - - return (val); -} - -#else /* o32 compilation */ -static __inline uint32_t -xlr_paddr_lw(uint64_t paddr) -{ - uint32_t addrh, addrl; - uint32_t val; - - addrh = 0x98000000 | (paddr >> 32); - addrl = paddr & 0xffffffff; - - __asm__ __volatile__( - ".set push \n\t" - ".set mips64 \n\t" - "dsll32 $8, %1, 0 \n\t" - "dsll32 $9, %2, 0 \n\t" /* get rid of the */ - "dsrl32 $9, $9, 0 \n\t" /* sign extend */ - "or $9, $8, $8 \n\t" - "lw %0, 0($9) \n\t" - ".set pop \n" - : "=r"(val) - : "r"(addrh), "r"(addrl) - : "$8", "$9"); - - return (val); -} - -static __inline uint64_t -xlr_paddr_ld(uint64_t paddr) -{ - uint32_t addrh, addrl; - uint32_t valh, vall; - - addrh = 0x98000000 | (paddr >> 32); - addrl = paddr & 0xffffffff; - - __asm__ __volatile__( - ".set push \n\t" - ".set mips64 \n\t" - "dsll32 %0, %2, 0 \n\t" - "dsll32 %1, %3, 0 \n\t" /* get rid of the */ - "dsrl32 %1, %1, 0 \n\t" /* sign extend */ - "or %0, %0, %1 \n\t" - "lw %1, 4(%0) \n\t" - "lw %0, 0(%0) \n\t" - ".set pop \n" - : "=&r"(valh), "=&r"(vall) - : "r"(addrh), "r"(addrl)); - - return (((uint64_t)valh << 32) | vall); -} -#endif - -/* - * XXX: Not really needed in n32 or n64, retain for now - */ -#if defined(__mips_n64) || defined(__mips_n32) -static __inline uint32_t -xlr_enable_kx(void) -{ - - return (0); -} - -static __inline void -xlr_restore_kx(uint32_t sr) -{ -} - -#else /* !defined(__mips_n64) && !defined(__mips_n32) */ -/* - * o32 compilation, we will disable interrupts and enable - * the KX bit so that we can use XKPHYS to access any 40bit - * physical address - */ -static __inline uint32_t -xlr_enable_kx(void) -{ - uint32_t sr = mips_rd_status(); - - mips_wr_status((sr & ~MIPS_SR_INT_IE) | MIPS_SR_KX); - return (sr); -} - -static __inline void -xlr_restore_kx(uint32_t sr) -{ - - mips_wr_status(sr); -} -#endif /* defined(__mips_n64) || defined(__mips_n32) */ - -/* - * XLR/XLS processors have maximum 8 cores, and maximum 4 threads - * per core - */ -#define XLR_MAX_CORES 8 -#define XLR_NTHREADS 4 - -/* - * FreeBSD can be started with few threads and cores turned off, - * so have a hardware thread id to FreeBSD cpuid mapping. - */ -extern int xlr_ncores; -extern int xlr_threads_per_core; -extern uint32_t xlr_hw_thread_mask; -extern int xlr_cpuid_to_hwtid[]; -extern int xlr_hwtid_to_cpuid[]; - -#endif Property changes on: head/sys/mips/rmi/rmi_mips_exts.h ___________________________________________________________________ Deleted: svn:eol-style ## -1 +0,0 ## -native \ No newline at end of property Deleted: svn:keywords ## -1 +0,0 ## -FreeBSD=%H \ No newline at end of property Deleted: svn:mime-type ## -1 +0,0 ## -text/plain \ No newline at end of property Index: head/sys/mips/rmi/msgring_xls.c =================================================================== --- head/sys/mips/rmi/msgring_xls.c (revision 327460) +++ head/sys/mips/rmi/msgring_xls.c (nonexistent) @@ -1,217 +0,0 @@ -/********************************************************** - * -----------------DO NOT EDIT THIS FILE------------------ - * This file has been autogenerated by the build process - * from "msgring_xls.cfg" - **********************************************************/ - -#include - -struct bucket_size xls_bucket_sizes = { - {32, 32, 32, 32, 32, 32, 32, 32, - 32, 32, 32, 32, 32, 32, 32, 32, - 32, 32, 32, 32, 32, 32, 32, 32, - 32, 32, 32, 32, 32, 32, 32, 32, - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 32, 32, 32, 32, 32, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 32, 32, 32, 32, 32, 0, 0, - 64, 64, 64, 64, 32, 32, 32, 32, - 0, 0, 0, 0, 0, 0, 0, 0, - 128, 128, 0, 0, 0, 0, 0, 0, - } -}; - -struct stn_cc xls_cc_table_cpu_0 = {{ - {1, 0, 0, 0, 0, 0, 0, 0}, - {0, 0, 0, 8, 0, 0, 0, 0}, - {0, 0, 0, 8, 0, 0, 0, 0}, - {0, 0, 0, 8, 0, 0, 0, 0}, - {0, 0, 0, 0, 0, 0, 0, 0}, - {0, 0, 0, 0, 0, 0, 0, 0}, - {0, 0, 0, 0, 0, 0, 0, 0}, - {0, 0, 0, 0, 0, 0, 0, 0}, - {0, 0, 0, 0, 0, 0, 0, 0}, - {0, 0, 0, 0, 0, 0, 0, 0}, - {0, 4, 8, 8, 8, 8, 0, 0}, - {0, 0, 0, 0, 0, 0, 0, 0}, - {0, 4, 8, 8, 8, 8, 0, 0}, - {16, 16, 16, 16, 16, 16, 16, 16}, - {0, 0, 0, 0, 0, 0, 0, 0}, - {32, 32, 0, 0, 0, 0, 0, 0}, -}}; - -struct stn_cc xls_cc_table_cpu_1 = {{ - {1, 0, 0, 0, 0, 0, 0, 0}, - {0, 0, 0, 0, 0, 0, 0, 0}, - {0, 0, 0, 0, 0, 0, 0, 0}, - {0, 0, 0, 0, 0, 0, 0, 0}, - {0, 0, 0, 0, 0, 0, 0, 0}, - {0, 0, 0, 0, 0, 0, 0, 0}, - {0, 0, 0, 0, 0, 0, 0, 0}, - {0, 0, 0, 0, 0, 0, 0, 0}, - {0, 0, 0, 0, 0, 0, 0, 0}, - {0, 0, 0, 0, 0, 0, 0, 0}, - {0, 4, 8, 8, 8, 8, 0, 0}, - {0, 0, 0, 0, 0, 0, 0, 0}, - {0, 4, 8, 8, 8, 8, 0, 0}, - {16, 16, 16, 16, 16, 16, 16, 16}, - {0, 0, 0, 0, 0, 0, 0, 0}, - {32, 32, 0, 0, 0, 0, 0, 0}, -}}; - -struct stn_cc xls_cc_table_cpu_2 = {{ - {0, 0, 0, 0, 0, 0, 0, 0}, - {0, 0, 0, 0, 0, 0, 0, 0}, - {0, 0, 0, 0, 0, 0, 0, 0}, - {0, 0, 0, 0, 0, 0, 0, 0}, - {0, 0, 0, 0, 0, 0, 0, 0}, - {0, 0, 0, 0, 0, 0, 0, 0}, - {0, 0, 0, 0, 0, 0, 0, 0}, - {0, 0, 0, 0, 0, 0, 0, 0}, - {0, 0, 0, 0, 0, 0, 0, 0}, - {0, 0, 0, 0, 0, 0, 0, 0}, - {0, 4, 8, 8, 8, 8, 0, 0}, - {0, 0, 0, 0, 0, 0, 0, 0}, - {0, 4, 8, 8, 8, 8, 0, 0}, - {16, 16, 16, 16, 0, 0, 0, 0}, - {0, 0, 0, 0, 0, 0, 0, 0}, - {32, 32, 0, 0, 0, 0, 0, 0}, -}}; - -struct stn_cc xls_cc_table_cpu_3 = {{ - {0, 0, 0, 0, 0, 0, 0, 0}, - {0, 0, 0, 0, 0, 0, 0, 0}, - {0, 0, 0, 0, 0, 0, 0, 0}, - {0, 0, 0, 0, 0, 0, 0, 0}, - {0, 0, 0, 0, 0, 0, 0, 0}, - {0, 0, 0, 0, 0, 0, 0, 0}, - {0, 0, 0, 0, 0, 0, 0, 0}, - {0, 0, 0, 0, 0, 0, 0, 0}, - {0, 0, 0, 0, 0, 0, 0, 0}, - {0, 0, 0, 0, 0, 0, 0, 0}, - {0, 4, 8, 8, 8, 8, 0, 0}, - {0, 0, 0, 0, 0, 0, 0, 0}, - {0, 4, 8, 8, 8, 8, 0, 0}, - {16, 16, 16, 16, 0, 0, 0, 0}, - {0, 0, 0, 0, 0, 0, 0, 0}, - {32, 32, 0, 0, 0, 0, 0, 0}, -}}; - -struct stn_cc xls_cc_table_gmac0 = {{ - {8, 8, 8, 8, 8, 8, 8, 8}, - {8, 8, 8, 8, 8, 8, 8, 8}, - {8, 8, 8, 8, 8, 8, 8, 8}, - {8, 8, 8, 8, 8, 8, 8, 8}, - {0, 0, 0, 0, 0, 0, 0, 0}, - {0, 0, 0, 0, 0, 0, 0, 0}, - {0, 0, 0, 0, 0, 0, 0, 0}, - {0, 0, 0, 0, 0, 0, 0, 0}, - {0, 0, 0, 0, 0, 0, 0, 0}, - {0, 0, 0, 0, 0, 0, 0, 0}, - {0, 8, 0, 0, 0, 0, 0, 0}, - {0, 0, 0, 0, 0, 0, 0, 0}, - {0, 8, 0, 0, 0, 0, 0, 0}, - {0, 0, 0, 0, 0, 0, 0, 0}, - {0, 0, 0, 0, 0, 0, 0, 0}, - {0, 0, 0, 0, 0, 0, 0, 0}, -}}; - -struct stn_cc xls_cc_table_gmac1 = {{ - {8, 8, 8, 8, 8, 8, 8, 8}, - {8, 8, 8, 8, 8, 8, 8, 8}, - {8, 8, 8, 8, 8, 8, 8, 8}, - {8, 8, 8, 8, 8, 8, 8, 8}, - {0, 0, 0, 0, 0, 0, 0, 0}, - {0, 0, 0, 0, 0, 0, 0, 0}, - {0, 0, 0, 0, 0, 0, 0, 0}, - {0, 0, 0, 0, 0, 0, 0, 0}, - {0, 0, 0, 0, 0, 0, 0, 0}, - {0, 0, 0, 0, 0, 0, 0, 0}, - {0, 8, 0, 0, 0, 0, 0, 0}, - {0, 0, 0, 0, 0, 0, 0, 0}, - {0, 8, 0, 0, 0, 0, 0, 0}, - {0, 0, 0, 0, 0, 0, 0, 0}, - {0, 0, 0, 0, 0, 0, 0, 0}, - {0, 0, 0, 0, 0, 0, 0, 0}, -}}; - -struct stn_cc xls_cc_table_dma = {{ - {4, 4, 4, 4, 4, 4, 4, 4}, - {4, 4, 4, 2, 4, 4, 4, 4}, - {4, 4, 4, 2, 4, 4, 4, 4}, - {4, 4, 4, 2, 4, 4, 4, 4}, - {0, 0, 0, 0, 0, 0, 0, 0}, - {0, 0, 0, 0, 0, 0, 0, 0}, - {0, 0, 0, 0, 0, 0, 0, 0}, - {0, 0, 0, 0, 0, 0, 0, 0}, - {0, 0, 0, 0, 0, 0, 0, 0}, - {0, 0, 0, 0, 0, 0, 0, 0}, - {0, 0, 0, 0, 0, 0, 0, 0}, - {0, 0, 0, 0, 0, 0, 0, 0}, - {0, 0, 0, 0, 0, 0, 0, 0}, - {0, 0, 0, 0, 0, 0, 0, 0}, - {0, 0, 0, 0, 0, 0, 0, 0}, - {0, 0, 0, 0, 0, 0, 0, 0}, -}}; - -struct stn_cc xls_cc_table_cmp = {{ - {4, 4, 4, 4, 4, 4, 4, 4}, - {4, 4, 4, 2, 4, 4, 4, 4}, - {4, 4, 4, 2, 4, 4, 4, 4}, - {4, 4, 4, 2, 4, 4, 4, 4}, - {0, 0, 0, 0, 0, 0, 0, 0}, - {0, 0, 0, 0, 0, 0, 0, 0}, - {0, 0, 0, 0, 0, 0, 0, 0}, - {0, 0, 0, 0, 0, 0, 0, 0}, - {0, 0, 0, 0, 0, 0, 0, 0}, - {0, 0, 0, 0, 0, 0, 0, 0}, - {0, 0, 0, 0, 0, 0, 0, 0}, - {0, 0, 0, 0, 0, 0, 0, 0}, - {0, 0, 0, 0, 0, 0, 0, 0}, - {0, 0, 0, 0, 0, 0, 0, 0}, - {0, 0, 0, 0, 0, 0, 0, 0}, - {0, 0, 0, 0, 0, 0, 0, 0}, -}}; - -struct stn_cc xls_cc_table_pcie = {{ - {0, 0, 0, 0, 0, 0, 0, 0}, - {0, 0, 0, 0, 0, 0, 0, 0}, - {0, 0, 0, 0, 0, 0, 0, 0}, - {0, 0, 0, 0, 0, 0, 0, 0}, - {0, 0, 0, 0, 0, 0, 0, 0}, - {0, 0, 0, 0, 0, 0, 0, 0}, - {0, 0, 0, 0, 0, 0, 0, 0}, - {0, 0, 0, 0, 0, 0, 0, 0}, - {0, 0, 0, 0, 0, 0, 0, 0}, - {0, 0, 0, 0, 0, 0, 0, 0}, - {0, 0, 0, 0, 0, 0, 0, 0}, - {0, 0, 0, 0, 0, 0, 0, 0}, - {0, 0, 0, 0, 0, 0, 0, 0}, - {0, 0, 0, 0, 0, 0, 0, 0}, - {0, 0, 0, 0, 0, 0, 0, 0}, - {0, 0, 0, 0, 0, 0, 0, 0}, -}}; - -struct stn_cc xls_cc_table_sec = {{ - {6, 8, 8, 8, 0, 0, 0, 0}, - {8, 8, 8, 4, 0, 0, 0, 0}, - {8, 8, 8, 4, 0, 0, 0, 0}, - {8, 8, 8, 4, 0, 0, 0, 0}, - {0, 0, 0, 0, 0, 0, 0, 0}, - {0, 0, 0, 0, 0, 0, 0, 0}, - {0, 0, 0, 0, 0, 0, 0, 0}, - {0, 0, 0, 0, 0, 0, 0, 0}, - {0, 0, 0, 0, 0, 0, 0, 0}, - {0, 0, 0, 0, 0, 0, 0, 0}, - {0, 0, 0, 0, 0, 0, 0, 0}, - {0, 0, 0, 0, 0, 0, 0, 0}, - {0, 0, 0, 0, 0, 0, 0, 0}, - {0, 0, 0, 0, 0, 0, 0, 0}, - {0, 0, 0, 0, 0, 0, 0, 0}, - {0, 0, 0, 0, 0, 0, 0, 0}, -}}; Property changes on: head/sys/mips/rmi/msgring_xls.c ___________________________________________________________________ Deleted: svn:eol-style ## -1 +0,0 ## -native \ No newline at end of property Deleted: svn:keywords ## -1 +0,0 ## -FreeBSD=%H \ No newline at end of property Deleted: svn:mime-type ## -1 +0,0 ## -text/plain \ No newline at end of property Index: head/sys/mips/rmi/pcibus.h =================================================================== --- head/sys/mips/rmi/pcibus.h (revision 327460) +++ head/sys/mips/rmi/pcibus.h (nonexistent) @@ -1,37 +0,0 @@ -/*- - * SPDX-License-Identifier: BSD-2-Clause-FreeBSD - * - * Copyright (c) 1998 Doug Rabson - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - * - * $FreeBSD$ - */ -#define DEFAULT_PCI_CONFIG_BASE 0x18000000 -#define MSI_MIPS_ADDR_BASE 0xfee00000 - -#define PCIE_LINK0_MSI_STATUS 0x90 -#define PCIE_LINK1_MSI_STATUS 0x94 -#define PCIE_LINK2_MSI_STATUS 0x190 -#define PCIE_LINK3_MSI_STATUS 0x194 - Property changes on: head/sys/mips/rmi/pcibus.h ___________________________________________________________________ Deleted: svn:eol-style ## -1 +0,0 ## -native \ No newline at end of property Deleted: svn:keywords ## -1 +0,0 ## -FreeBSD=%H \ No newline at end of property Deleted: svn:mime-type ## -1 +0,0 ## -text/plain \ No newline at end of property Index: head/sys/mips/rmi/tick.c =================================================================== --- head/sys/mips/rmi/tick.c (revision 327460) +++ head/sys/mips/rmi/tick.c (nonexistent) @@ -1,381 +0,0 @@ -/*- - * SPDX-License-Identifier: BSD-2-Clause-FreeBSD - * - * Copyright (c) 2006-2007 Bruce M. Simpson. - * Copyright (c) 2003-2004 Juli Mallett. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - */ - -/* - * Simple driver for the 32-bit interval counter built in to all - * MIPS32 CPUs. - */ - -#include -__FBSDID("$FreeBSD$"); - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include -#include -#include - -uint64_t counter_freq; - -struct timecounter *platform_timecounter; - -static DPCPU_DEFINE(uint32_t, cycles_per_tick); -static uint32_t cycles_per_usec; - -static DPCPU_DEFINE(volatile uint32_t, counter_upper); -static DPCPU_DEFINE(volatile uint32_t, counter_lower_last); -static DPCPU_DEFINE(uint32_t, compare_ticks); -static DPCPU_DEFINE(uint32_t, lost_ticks); - -struct clock_softc { - int intr_rid; - struct resource *intr_res; - void *intr_handler; - struct timecounter tc; - struct eventtimer et; -}; -static struct clock_softc *softc; - -/* - * Device methods - */ -static int clock_probe(device_t); -static void clock_identify(driver_t *, device_t); -static int clock_attach(device_t); -static unsigned counter_get_timecount(struct timecounter *tc); - -void -mips_timer_early_init(uint64_t clock_hz) -{ - /* Initialize clock early so that we can use DELAY sooner */ - counter_freq = clock_hz; - cycles_per_usec = (clock_hz / (1000 * 1000)); -} - -void -platform_initclocks(void) -{ - - if (platform_timecounter != NULL) - tc_init(platform_timecounter); -} - -static uint64_t -tick_ticker(void) -{ - uint64_t ret; - uint32_t ticktock; - uint32_t t_lower_last, t_upper; - - /* - * Disable preemption because we are working with cpu specific data. - */ - critical_enter(); - - /* - * Note that even though preemption is disabled, interrupts are - * still enabled. In particular there is a race with clock_intr() - * reading the values of 'counter_upper' and 'counter_lower_last'. - * - * XXX this depends on clock_intr() being executed periodically - * so that 'counter_upper' and 'counter_lower_last' are not stale. - */ - do { - t_upper = DPCPU_GET(counter_upper); - t_lower_last = DPCPU_GET(counter_lower_last); - } while (t_upper != DPCPU_GET(counter_upper)); - - ticktock = mips_rd_count(); - - critical_exit(); - - /* COUNT register wrapped around */ - if (ticktock < t_lower_last) - t_upper++; - - ret = ((uint64_t)t_upper << 32) | ticktock; - return (ret); -} - -void -mips_timer_init_params(uint64_t platform_counter_freq, int double_count) -{ - - /* - * XXX: Do not use printf here: uart code 8250 may use DELAY so this - * function should be called before cninit. - */ - counter_freq = platform_counter_freq; - /* - * XXX: Some MIPS32 cores update the Count register only every two - * pipeline cycles. - * We know this because of status registers in CP0, make it automatic. - */ - if (double_count != 0) - counter_freq /= 2; - - cycles_per_usec = counter_freq / (1 * 1000 * 1000); - set_cputicker(tick_ticker, counter_freq, 1); -} - -static int -sysctl_machdep_counter_freq(SYSCTL_HANDLER_ARGS) -{ - int error; - uint64_t freq; - - if (softc == NULL) - return (EOPNOTSUPP); - freq = counter_freq; - error = sysctl_handle_64(oidp, &freq, sizeof(freq), req); - if (error == 0 && req->newptr != NULL) { - counter_freq = freq; - softc->et.et_frequency = counter_freq; - softc->tc.tc_frequency = counter_freq; - } - return (error); -} - -SYSCTL_PROC(_machdep, OID_AUTO, counter_freq, CTLTYPE_U64 | CTLFLAG_RW, - NULL, 0, sysctl_machdep_counter_freq, "QU", - "Timecounter frequency in Hz"); - -static unsigned -counter_get_timecount(struct timecounter *tc) -{ - - return (mips_rd_count()); -} - -/* - * Wait for about n microseconds (at least!). - */ -void -DELAY(int n) -{ - uint32_t cur, last, delta, usecs; - - TSENTER(); - /* - * This works by polling the timer and counting the number of - * microseconds that go by. - */ - last = mips_rd_count(); - delta = usecs = 0; - - while (n > usecs) { - cur = mips_rd_count(); - - /* Check to see if the timer has wrapped around. */ - if (cur < last) - delta += cur + (0xffffffff - last) + 1; - else - delta += cur - last; - - last = cur; - - if (delta >= cycles_per_usec) { - usecs += delta / cycles_per_usec; - delta %= cycles_per_usec; - } - } - TSEXIT(); -} - -static int -clock_start(struct eventtimer *et, sbintime_t first, sbintime_t period) -{ - uint32_t fdiv, div, next; - - if (period != 0) - div = (et->et_frequency * period) >> 32; - else - div = 0; - if (first != 0) - fdiv = (et->et_frequency * first) >> 32; - else - fdiv = div; - DPCPU_SET(cycles_per_tick, div); - next = mips_rd_count() + fdiv; - DPCPU_SET(compare_ticks, next); - mips_wr_compare(next); - return (0); -} - -static int -clock_stop(struct eventtimer *et) -{ - - DPCPU_SET(cycles_per_tick, 0); - mips_wr_compare(0xffffffff); - return (0); -} - -/* - * Device section of file below - */ -static int -clock_intr(void *arg) -{ - struct clock_softc *sc = (struct clock_softc *)arg; - uint32_t cycles_per_tick; - uint32_t count, compare_last, compare_next, lost_ticks; - - cycles_per_tick = DPCPU_GET(cycles_per_tick); - /* - * Set next clock edge. - */ - count = mips_rd_count(); - compare_last = DPCPU_GET(compare_ticks); - if (cycles_per_tick > 0) { - compare_next = count + cycles_per_tick; - DPCPU_SET(compare_ticks, compare_next); - mips_wr_compare(compare_next); - } else /* In one-shot mode timer should be stopped after the event. */ - mips_wr_compare(0xffffffff); - - /* COUNT register wrapped around */ - if (count < DPCPU_GET(counter_lower_last)) { - DPCPU_SET(counter_upper, DPCPU_GET(counter_upper) + 1); - } - DPCPU_SET(counter_lower_last, count); - - if (cycles_per_tick > 0) { - - /* - * Account for the "lost time" between when the timer interrupt - * fired and when 'clock_intr' actually started executing. - */ - lost_ticks = DPCPU_GET(lost_ticks); - lost_ticks += count - compare_last; - - /* - * If the COUNT and COMPARE registers are no longer in sync - * then make up some reasonable value for the 'lost_ticks'. - * - * This could happen, for e.g., after we resume normal - * operations after exiting the debugger. - */ - if (lost_ticks > 2 * cycles_per_tick) - lost_ticks = cycles_per_tick; - - while (lost_ticks >= cycles_per_tick) { - if (sc->et.et_active) - sc->et.et_event_cb(&sc->et, sc->et.et_arg); - lost_ticks -= cycles_per_tick; - } - DPCPU_SET(lost_ticks, lost_ticks); - } - if (sc->et.et_active) - sc->et.et_event_cb(&sc->et, sc->et.et_arg); - return (FILTER_HANDLED); -} - -static int -clock_probe(device_t dev) -{ - - device_set_desc(dev, "Generic MIPS32 ticker"); - return (BUS_PROBE_NOWILDCARD); -} - -static void -clock_identify(driver_t * drv, device_t parent) -{ - - BUS_ADD_CHILD(parent, 0, "clock", 0); -} - -static int -clock_attach(device_t dev) -{ - struct clock_softc *sc; - - if (device_get_unit(dev) != 0) - panic("can't attach more clocks"); - - softc = sc = device_get_softc(dev); - cpu_establish_hardintr("compare", clock_intr, NULL, - sc, IRQ_TIMER, INTR_TYPE_CLK, &sc->intr_handler); - - sc->tc.tc_get_timecount = counter_get_timecount; - sc->tc.tc_counter_mask = 0xffffffff; - sc->tc.tc_frequency = counter_freq; - sc->tc.tc_name = "MIPS32"; - sc->tc.tc_quality = 800; - sc->tc.tc_priv = sc; - tc_init(&sc->tc); - sc->et.et_name = "MIPS32"; - sc->et.et_flags = ET_FLAGS_PERIODIC | ET_FLAGS_ONESHOT | - ET_FLAGS_PERCPU; - sc->et.et_quality = 800; - sc->et.et_frequency = counter_freq; - sc->et.et_min_period = 0x00004000LLU; /* To be safe. */ - sc->et.et_max_period = (0xfffffffeLLU << 32) / sc->et.et_frequency; - sc->et.et_start = clock_start; - sc->et.et_stop = clock_stop; - sc->et.et_priv = sc; - et_register(&sc->et); - return (0); -} - -static device_method_t clock_methods[] = { - /* Device interface */ - DEVMETHOD(device_probe, clock_probe), - DEVMETHOD(device_identify, clock_identify), - DEVMETHOD(device_attach, clock_attach), - DEVMETHOD(device_detach, bus_generic_detach), - DEVMETHOD(device_shutdown, bus_generic_shutdown), - - {0, 0} -}; - -static driver_t clock_driver = { - "clock", - clock_methods, - sizeof(struct clock_softc), -}; - -static devclass_t clock_devclass; - -DRIVER_MODULE(clock, nexus, clock_driver, clock_devclass, 0, 0); Property changes on: head/sys/mips/rmi/tick.c ___________________________________________________________________ Deleted: svn:eol-style ## -1 +0,0 ## -native \ No newline at end of property Deleted: svn:keywords ## -1 +0,0 ## -FreeBSD=%H \ No newline at end of property Deleted: svn:mime-type ## -1 +0,0 ## -text/plain \ No newline at end of property Index: head/sys/mips/rmi/interrupt.h =================================================================== --- head/sys/mips/rmi/interrupt.h (revision 327460) +++ head/sys/mips/rmi/interrupt.h (nonexistent) @@ -1,52 +0,0 @@ -/*- - * SPDX-License-Identifier: BSD-3-Clause - * - * Copyright (c) 2003-2009 RMI Corporation - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. Neither the name of RMI Corporation, nor the names of its contributors, - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - * - * RMI_BSD - * $FreeBSD$ - */ -#ifndef _RMI_INTERRUPT_H_ -#define _RMI_INTERRUPT_H_ - -/* Defines for the IRQ numbers */ - -#define IRQ_IPI 41 /* 8-39 are mapped by PIC intr 0-31 */ -#define IRQ_MSGRING 6 -#define IRQ_TIMER 7 - -/* - * XLR needs custom pre and post handlers for PCI/PCI-e interrupts - * XXX: maybe follow i386 intsrc model - */ -void xlr_establish_intr(const char *name, driver_filter_t filt, - driver_intr_t handler, void *arg, int irq, int flags, - void **cookiep, void (*busack)(int)); -void xlr_enable_irq(int irq); - -#endif /* _RMI_INTERRUPT_H_ */ Property changes on: head/sys/mips/rmi/interrupt.h ___________________________________________________________________ Deleted: svn:eol-style ## -1 +0,0 ## -native \ No newline at end of property Deleted: svn:keywords ## -1 +0,0 ## -FreeBSD=%H \ No newline at end of property Deleted: svn:mime-type ## -1 +0,0 ## -text/plain \ No newline at end of property Index: head/sys/mips/rmi/rmi_boot_info.h =================================================================== --- head/sys/mips/rmi/rmi_boot_info.h (revision 327460) +++ head/sys/mips/rmi/rmi_boot_info.h (nonexistent) @@ -1,111 +0,0 @@ -/*- - * SPDX-License-Identifier: BSD-3-Clause - * - * Copyright (c) 2003-2009 RMI Corporation - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. Neither the name of RMI Corporation, nor the names of its contributors, - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - * - * RMI_BSD - * $FreeBSD$ - */ -#ifndef _SHARED_STRUCTS_H -#define _SHARED_STRUCTS_H - -#define BOOT1_INFO_VERSION 0x0001 - -struct boot1_info { - uint64_t boot_level; - uint64_t io_base; - uint64_t output_device; - uint64_t uart_print; - uint64_t led_output; - uint64_t init; - uint64_t exit; - uint64_t warm_reset; - uint64_t wakeup; - uint64_t cpu_online_map; - uint64_t master_reentry_sp; - uint64_t master_reentry_gp; - uint64_t master_reentry_fn; - uint64_t slave_reentry_fn; - uint64_t magic_dword; - uint64_t uart_putchar; - uint64_t size; - uint64_t uart_getchar; - uint64_t nmi_handler; - uint64_t psb_version; - uint64_t mac_addr; - uint64_t cpu_frequency; - uint64_t board_version; - uint64_t malloc; - uint64_t free; - uint64_t alloc_pbuf; - uint64_t free_pbuf; - uint64_t psb_os_cpu_map; - uint64_t userapp_cpu_map; - uint64_t wakeup_os; - uint64_t psb_mem_map; - uint64_t board_major_version; - uint64_t board_minor_version; - uint64_t board_manf_revision; - uint64_t board_serial_number; - uint64_t psb_physaddr_map; -}; - -extern struct boot1_info xlr_boot1_info; - - -/* This structure is passed to all applications launched from the linux - loader through K0 register - */ -#define XLR_LOADER_INFO_MAGIC 0x600ddeed -struct xlr_loader_info { - uint32_t magic; - /* xlr_loader_shared_struct_t for CPU 0 will start here */ - unsigned long sh_mem_start; - /* Size of the shared memory b/w linux apps and rmios apps */ - uint32_t app_sh_mem_size; -}; - -/* Boot loader uses the linux mips convention */ -#define BOOT1_MEMMAP_MAX 32 - -enum xlr_phys_memmap_t { - BOOT1_MEM_RAM = 1, BOOT1_MEM_ROM_DATA, BOOT1_MEM_RESERVED -}; - -struct xlr_boot1_mem_map { - uint32_t num_entries; - struct { - uint64_t addr; - uint64_t size; - uint32_t type; - uint32_t pad; - } physmem_map[BOOT1_MEMMAP_MAX]; -}; - - -#endif Property changes on: head/sys/mips/rmi/rmi_boot_info.h ___________________________________________________________________ Deleted: svn:eol-style ## -1 +0,0 ## -native \ No newline at end of property Deleted: svn:keywords ## -1 +0,0 ## -FreeBSD=%H \ No newline at end of property Deleted: svn:mime-type ## -1 +0,0 ## -text/plain \ No newline at end of property Index: head/sys/mips/rmi/msgring_xls.cfg =================================================================== --- head/sys/mips/rmi/msgring_xls.cfg (revision 327460) +++ head/sys/mips/rmi/msgring_xls.cfg (nonexistent) @@ -1,563 +0,0 @@ -/********************************************************************* - * - * Copyright 2003-2006 Raza Microelectronics, Inc. (RMI). All rights - * reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * - * THIS SOFTWARE IS PROVIDED BY Raza Microelectronics, Inc. ``AS IS'' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR - * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL RMI OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES, LOSS OF USE, DATA, OR PROFITS, OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF - * THE POSSIBILITY OF SUCH DAMAGE. - * - * *****************************RMI_2**********************************/ - - -/* - * This file defines the message ring configuration for XLS two core. It tries to allow - * many different point-point communications between the message stations on the message ring - * and as result is _not_ the best configuration for performance - * - * The message ring on phoenix family of processors connects the cpus, gmacs, xgmac/spi4, - * security engine and the general purpose DMA engines. It provides a high bandwidth, - * low latency communication links. On traditional processors, this communication goes through - * which inherently does not scale very well with increasing number of cpus. - * - * Message ring has an in-built flow control mechanism. Every agent/station on the ring has to - * have software configured credits to send messages to any agent. Every receiving agent on the - * ring has a 256 entry FIFO that can divided into "buckets". All addressing on the ring is - * in terms of buckets. There are a total 128 buckets on the ring. The total number of credits - * across all sending agents should not exceed the bucket size. - * - * Below are the receiving agents and the max number of buckets they can have - * CPU 0 : 8 buckets - * CPU 1 : 8 buckets - * - * GMAC : 8 buckets - * - * SEC : 8 buckets - * - * DMA : 8 buckets - * - * CMP : Currently disabled. - * - * The bucket size of a bucket should be aligned to the bucket's starting index in that - * receiving station's FIFO. For example, if sizes of bucket0 and bucket1 of a station - * are 32 and 32, bucket2's size has to be 64. bucket size 0 is valid. - * - * The format of the file is pretty straight forward. Each bucket definition has the size - * and the list of sending agents to that bucket with the number of credits to send. - * - * Undefined buckets have a size of 0 and Tx stations have 0 credits to send to that bucket. - * - * Following are the currently supported bucket names - * cpu_0_0 - * cpu_0_1 - * cpu_0_2 - * cpu_0_3 - * cpu_0_4 - * cpu_0_5 - * cpu_0_6 - * cpu_0_7 - * - * cpu_1_0 - * cpu_1_1 - * cpu_1_2 - * cpu_1_3 - * cpu_1_4 - * cpu_1_5 - * cpu_1_6 - * cpu_1_7 - * - * enabled only for xls-b0 - * cpu_2_0 - * cpu_2_1 - * cpu_2_2 - * cpu_2_3 - * cpu_2_4 - * cpu_2_5 - * cpu_2_6 - * cpu_2_7 - * - * enabled only for xls-b0 - * cpu_3_0 - * cpu_3_1 - * cpu_3_2 - * cpu_3_3 - * cpu_3_4 - * cpu_3_5 - * cpu_3_6 - * cpu_3_7 - * - * gmac0_rfr - * gmac0_tx_0 - * gmac0_tx_1 - * gmac0_tx_2 - * gmac0_tx_3 - * - * gmac1_rfr - * gmac1_tx_0 - * gmac1_tx_1 - * gmac1_tx_2 - * gmac1_tx_3 - * - * sec_pipe_0 - * sec_rsa - * - * Following are the currently supported Tx Agent/Station names - * - * tx_stn_cpu_0 - * tx_stn_cpu_1 - * - * tx_stn_gmac0 - * tx_stn_gmac1 - * - * tx_stn_dma - * - * tx_stn_sec - * - * - */ - -/*************************************************************/ -// CPU_0 Message Station - -bucket "cpu_0_0" { - size 32; - "tx_stn_gmac0" 8; - "tx_stn_gmac1" 8; - "tx_stn_sec" 6; - "tx_stn_dma" 4; - "tx_stn_cmp" 4; - "tx_stn_cpu_0" 1; - "tx_stn_cpu_1" 1; /* NEEDED BY RMIOS IPSEC */ -} -bucket "cpu_0_1" { - size 32; - "tx_stn_gmac0" 8; - "tx_stn_gmac1" 8; - "tx_stn_sec" 8; - "tx_stn_dma" 4; - "tx_stn_cmp" 4; -} -bucket "cpu_0_2" { - size 32; - "tx_stn_gmac0" 8; - "tx_stn_gmac1" 8; - "tx_stn_sec" 8; - "tx_stn_dma" 4; - "tx_stn_cmp" 4; -} -bucket "cpu_0_3" { - size 32; - "tx_stn_gmac0" 8; - "tx_stn_gmac1" 8; - "tx_stn_sec" 8; - "tx_stn_dma" 4; - "tx_stn_cmp" 4; -} -bucket "cpu_0_4" { - size 32; - "tx_stn_gmac0" 8; - "tx_stn_gmac1" 8; - "tx_stn_dma" 4; - "tx_stn_cmp" 4; -} -bucket "cpu_0_5" { - size 32; - "tx_stn_gmac0" 8; - "tx_stn_gmac1" 8; - "tx_stn_dma" 4; - "tx_stn_cmp" 4; -} -bucket "cpu_0_6" { - size 32; - "tx_stn_gmac0" 8; - "tx_stn_gmac1" 8; - "tx_stn_dma" 4; - "tx_stn_cmp" 4; -} -bucket "cpu_0_7" { - size 32; - "tx_stn_gmac0" 8; - "tx_stn_gmac1" 8; - "tx_stn_dma" 4; - "tx_stn_cmp" 4; -} - -/*************************************************************/ -// CPU_1 Message Station - -bucket "cpu_1_0" { - size 32; - "tx_stn_gmac0" 8; - "tx_stn_gmac1" 8; - "tx_stn_sec" 8; - "tx_stn_dma" 4; - "tx_stn_cmp" 4; -} -bucket "cpu_1_1" { - size 32; - "tx_stn_gmac0" 8; - "tx_stn_gmac1" 8; - "tx_stn_sec" 8; - "tx_stn_dma" 4; - "tx_stn_cmp" 4; -} -bucket "cpu_1_2" { - size 32; - "tx_stn_gmac0" 8; - "tx_stn_gmac1" 8; - "tx_stn_sec" 8; - "tx_stn_dma" 4; - "tx_stn_cmp" 4; -} -bucket "cpu_1_3" { - size 32; - "tx_stn_gmac0" 8; - "tx_stn_gmac1" 8; - "tx_stn_sec" 4; - "tx_stn_cpu_0" 8; /* NEEDED BY RMIOS IPSEC */ - "tx_stn_dma" 2; - "tx_stn_cmp" 2; -} -bucket "cpu_1_4" { - size 32; - "tx_stn_gmac0" 8; - "tx_stn_gmac1" 8; - "tx_stn_dma" 4; - "tx_stn_cmp" 4; -} -bucket "cpu_1_5" { - size 32; - "tx_stn_gmac0" 8; - "tx_stn_gmac1" 8; - "tx_stn_dma" 4; - "tx_stn_cmp" 4; -} -bucket "cpu_1_6" { - size 32; - "tx_stn_gmac0" 8; - "tx_stn_gmac1" 8; - "tx_stn_dma" 4; - "tx_stn_cmp" 4; -} -bucket "cpu_1_7" { - size 32; - "tx_stn_gmac0" 8; - "tx_stn_gmac1" 8; - "tx_stn_dma" 4; - "tx_stn_cmp" 4; -} - -/*************************************************************/ -// CPU_2 Message Station - -bucket "cpu_2_0" { - size 32; - "tx_stn_gmac0" 8; - "tx_stn_gmac1" 8; - "tx_stn_sec" 8; - "tx_stn_dma" 4; - "tx_stn_cmp" 4; -} -bucket "cpu_2_1" { - size 32; - "tx_stn_gmac0" 8; - "tx_stn_gmac1" 8; - "tx_stn_sec" 8; - "tx_stn_dma" 4; - "tx_stn_cmp" 4; -} -bucket "cpu_2_2" { - size 32; - "tx_stn_gmac0" 8; - "tx_stn_gmac1" 8; - "tx_stn_sec" 8; - "tx_stn_dma" 4; - "tx_stn_cmp" 4; -} -bucket "cpu_2_3" { - size 32; - "tx_stn_gmac0" 8; - "tx_stn_gmac1" 8; - "tx_stn_sec" 4; - "tx_stn_cpu_0" 8; /* NEEDED BY RMIOS IPSEC */ - "tx_stn_dma" 2; - "tx_stn_cmp" 2; -} -bucket "cpu_2_4" { - size 32; - "tx_stn_gmac0" 8; - "tx_stn_gmac1" 8; - "tx_stn_dma" 4; - "tx_stn_cmp" 4; -} -bucket "cpu_2_5" { - size 32; - "tx_stn_gmac0" 8; - "tx_stn_gmac1" 8; - "tx_stn_dma" 4; - "tx_stn_cmp" 4; -} -bucket "cpu_2_6" { - size 32; - "tx_stn_gmac0" 8; - "tx_stn_gmac1" 8; - "tx_stn_dma" 4; - "tx_stn_cmp" 4; -} -bucket "cpu_2_7" { - size 32; - "tx_stn_gmac0" 8; - "tx_stn_gmac1" 8; - "tx_stn_dma" 4; - "tx_stn_cmp" 4; -} - - -/*************************************************************/ -// CPU_3 Message Station -bucket "cpu_3_0" { - size 32; - "tx_stn_gmac0" 8; - "tx_stn_gmac1" 8; - "tx_stn_sec" 8; - "tx_stn_dma" 4; - "tx_stn_cmp" 4; -} -bucket "cpu_3_1" { - size 32; - "tx_stn_gmac0" 8; - "tx_stn_gmac1" 8; - "tx_stn_sec" 8; - "tx_stn_dma" 4; - "tx_stn_cmp" 4; -} -bucket "cpu_3_2" { - size 32; - "tx_stn_gmac0" 8; - "tx_stn_gmac1" 8; - "tx_stn_sec" 8; - "tx_stn_dma" 4; - "tx_stn_cmp" 4; -} -bucket "cpu_3_3" { - size 32; - "tx_stn_gmac0" 8; - "tx_stn_gmac1" 8; - "tx_stn_sec" 4; - "tx_stn_cpu_0" 8; /* NEEDED BY RMIOS IPSEC */ - "tx_stn_dma" 2; - "tx_stn_cmp" 2; -} -bucket "cpu_3_4" { - size 32; - "tx_stn_gmac0" 8; - "tx_stn_gmac1" 8; - "tx_stn_dma" 4; - "tx_stn_cmp" 4; -} -bucket "cpu_3_5" { - size 32; - "tx_stn_gmac0" 8; - "tx_stn_gmac1" 8; - "tx_stn_dma" 4; - "tx_stn_cmp" 4; -} -bucket "cpu_3_6" { - size 32; - "tx_stn_gmac0" 8; - "tx_stn_gmac1" 8; - "tx_stn_dma" 4; - "tx_stn_cmp" 4; -} -bucket "cpu_3_7" { - size 32; - "tx_stn_gmac0" 8; - "tx_stn_gmac1" 8; - "tx_stn_dma" 4; - "tx_stn_cmp" 4; -} - -/*************************************************************/ - -// GMAC Message Station - -bucket "gmac0_rfr" { - size 32; - "tx_stn_cpu_0" 4; - "tx_stn_cpu_1" 4; - "tx_stn_cpu_2" 4; - "tx_stn_cpu_3" 4; - "tx_stn_gmac0" 8; - "tx_stn_gmac1" 8; -} - -bucket "gmac0_tx_0" { - size 32; - "tx_stn_cpu_0" 8; - "tx_stn_cpu_1" 8; - "tx_stn_cpu_2" 8; - "tx_stn_cpu_3" 8; -} - -bucket "gmac0_tx_1" { - size 32; - "tx_stn_cpu_0" 8; - "tx_stn_cpu_1" 8; - "tx_stn_cpu_2" 8; - "tx_stn_cpu_3" 8; -} - -bucket "gmac0_tx_2" { - size 32; - "tx_stn_cpu_0" 8; - "tx_stn_cpu_1" 8; - "tx_stn_cpu_2" 8; - "tx_stn_cpu_3" 8; -} - -bucket "gmac0_tx_3" { - size 32; - "tx_stn_cpu_0" 8; - "tx_stn_cpu_1" 8; - "tx_stn_cpu_2" 8; - "tx_stn_cpu_3" 8; -} - -bucket "gmac1_rfr" { - size 32; - "tx_stn_cpu_0" 4; - "tx_stn_cpu_1" 4; - "tx_stn_cpu_2" 4; - "tx_stn_cpu_3" 4; - "tx_stn_gmac0" 8; - "tx_stn_gmac1" 8; -} - -bucket "gmac1_tx_0" { - size 32; - "tx_stn_cpu_0" 8; - "tx_stn_cpu_1" 8; - "tx_stn_cpu_2" 8; - "tx_stn_cpu_3" 8; -} - -bucket "gmac1_tx_1" { - size 32; - "tx_stn_cpu_0" 8; - "tx_stn_cpu_1" 8; - "tx_stn_cpu_2" 8; - "tx_stn_cpu_3" 8; -} - -bucket "gmac1_tx_2" { - size 32; - "tx_stn_cpu_0" 8; - "tx_stn_cpu_1" 8; - "tx_stn_cpu_2" 8; - "tx_stn_cpu_3" 8; -} - -bucket "gmac1_tx_3" { - size 32; - "tx_stn_cpu_0" 8; - "tx_stn_cpu_1" 8; - "tx_stn_cpu_2" 8; - "tx_stn_cpu_3" 8; -} - -/*************************************************************/ -// Security Message Station - -bucket "sec_pipe_0" { - size 128; - "tx_stn_cpu_0" 32; - "tx_stn_cpu_1" 32; - "tx_stn_cpu_2" 32; - "tx_stn_cpu_3" 32; -} - -bucket "sec_rsa_ecc" { - size 128; - "tx_stn_cpu_0" 32; - "tx_stn_cpu_1" 32; - "tx_stn_cpu_2" 32; - "tx_stn_cpu_3" 32; -} - -bucket "dma_rsvd_0" { - size 64; - "tx_stn_cpu_0" 16; - "tx_stn_cpu_1" 16; - "tx_stn_cpu_2" 16; - "tx_stn_cpu_3" 16; -} -bucket "dma_rsvd_1" { - size 64; - "tx_stn_cpu_0" 16; - "tx_stn_cpu_1" 16; - "tx_stn_cpu_2" 16; - "tx_stn_cpu_3" 16; -} - -bucket "dma_rsvd_2" { - size 64; - "tx_stn_cpu_0" 16; - "tx_stn_cpu_1" 16; - "tx_stn_cpu_2" 16; - "tx_stn_cpu_3" 16; -} - -bucket "dma_rsvd_3" { - size 64; - "tx_stn_cpu_0" 16; - "tx_stn_cpu_1" 16; - "tx_stn_cpu_2" 16; - "tx_stn_cpu_3" 16; -} - -/*************************************************************/ -// Compression Message Station - -bucket "cmp_0" { - size 32; - "tx_stn_cpu_0" 16; - "tx_stn_cpu_1" 16; -} - -bucket "cmp_1" { - size 32; - "tx_stn_cpu_0" 16; - "tx_stn_cpu_1" 16; -} - -bucket "cmp_2" { - size 32; - "tx_stn_cpu_0" 16; - "tx_stn_cpu_1" 16; -} - -bucket "cmp_3" { - size 32; - "tx_stn_cpu_0" 16; - "tx_stn_cpu_1" 16; -} - Property changes on: head/sys/mips/rmi/msgring_xls.cfg ___________________________________________________________________ Deleted: svn:eol-style ## -1 +0,0 ## -native \ No newline at end of property Deleted: svn:keywords ## -1 +0,0 ## -FreeBSD=%H \ No newline at end of property Deleted: svn:mime-type ## -1 +0,0 ## -text/plain \ No newline at end of property Index: head/sys/mips/conf/XLR =================================================================== --- head/sys/mips/conf/XLR (revision 327460) +++ head/sys/mips/conf/XLR (nonexistent) @@ -1,147 +0,0 @@ -#################################RMI_BSD##################################### -# Copyright (c) 2003-2009 RMI Corporation -# All rights reserved. -# -# Redistribution and use in source and binary forms, with or without -# modification, are permitted provided that the following conditions -# are met: -# 1. Redistributions of source code must retain the above copyright -# notice, this list of conditions and the following disclaimer. -# 2. Redistributions in binary form must reproduce the above copyright -# notice, this list of conditions and the following disclaimer in the -# documentation and/or other materials provided with the distribution. -# 3. Neither the name of RMI Corporation, nor the names of its contributors, -# may be used to endorse or promote products derived from this software -# without specific prior written permission. -# -# THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND -# ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -# ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE -# FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL -# DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS -# OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) -# HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT -# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY -# OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF -# SUCH DAMAGE. -#################################RMI_BSD##################################### -# XLR -- Generic kernel configuration file for FreeBSD/mips -# -# For more information on this file, please read the handbook section on -# Kernel Configuration Files: -# -# https://www.FreeBSD.org/doc/en_US.ISO8859-1/books/handbook/kernelconfig-config.html -# -# The handbook is also available locally in /usr/share/doc/handbook -# if you've installed the doc distribution, otherwise always see the -# FreeBSD World Wide Web server (https://www.FreeBSD.org/) for the -# latest information. -# -# An exhaustive list of options and more detailed explanations of the -# device lines is also present in the ../../conf/NOTES and NOTES files. -# If you are in doubt as to the purpose or necessity of a line, check first -# in NOTES. -# -# $FreeBSD$ - -machine mips mips -ident XLR -include "../rmi/std.xlr" - -makeoptions MODULES_OVERRIDE="" -makeoptions DEBUG=-g # Build kernel with gdb(1) debug symbols -makeoptions KERNLOADADDR=0x80100000 -#profile 2 - -options SCHED_ULE # ULE scheduler -#options VERBOSE_SYSINIT -#options SCHED_4BSD # 4BSD scheduler -options SMP -options PREEMPTION # Enable kernel thread preemption -#options FULL_PREEMPTION # Enable kernel thread preemption -options INET # InterNETworking -options INET6 # IPv6 communications protocols -options TCP_HHOOK # hhook(9) framework for TCP -options FFS # Berkeley Fast Filesystem -#options SOFTUPDATES # Enable FFS soft updates support -options UFS_ACL # Support for access control lists -options UFS_DIRHASH # Improve performance on big directories -options NFSCL -options NFS_ROOT -# -options BOOTP -options BOOTP_NFSROOT -options BOOTP_NFSV3 -options BOOTP_WIRED_TO=nlge0 -options BOOTP_COMPAT -options ROOTDEVNAME=\"nfs:10.1.1.8:/usr/extra/nfsroot\" -# -#options MD_ROOT # MD is a potential root device -#options MD_ROOT_SIZE=27000 -#options MD_ROOT_SIZE=5120 -#options ROOTDEVNAME=\"ufs:md0\" -options _KPOSIX_PRIORITY_SCHEDULING # POSIX P1003_1B real-time extensions -options HZ=1000 -options NO_SWAPPING - -#Debugging options -options KTRACE # ktrace(1) support -options DDB -options KDB -options GDB -options ALT_BREAK_TO_DEBUGGER -options BREAK_TO_DEBUGGER -#options DEADLKRES #Enable the deadlock resolver -options INVARIANTS #Enable calls of extra sanity checking -options INVARIANT_SUPPORT #Extra sanity checks of internal structures, required by INVARIANTS -#options WITNESS #Enable checks to detect deadlocks and cycles -#options WITNESS_SKIPSPIN #Don't run witness on spinlocks for speed -#options KTR # ktr(4) and ktrdump(8) support -#options KTR_COMPILE=(KTR_LOCK|KTR_PROC|KTR_INTR|KTR_CALLOUT|KTR_UMA|KTR_SYSC) -#options KTR_ENTRIES=131072 - -#options LOCK_PROFILING -#options SLEEPQUEUE_PROFILING -#options TURNSTILE_PROFILING - -device pci -#device ata -device uart -# Pseudo -device loop -device random -device md -device bpf - -# Network -device miibus -device nlge -device ether -device re -device msk - -device da -device scbus -device ehci # EHCI PCI->USB interface (USB 2.0) -device usb # USB Bus (required) -#options USB_DEBUG # enable debug msgs -#device uhid # "Human Interface Devices" -device umass # Disks/Mass storage - Requires scbus and da - -#device cfi - -#i2c -device ic -device iic -device iicbb -device iicbus -device ds13rtc # RTC on XLR boards -device max6657 # Temparature sensor on XLR boards -device at24co2n # EEPROM on XLR boards - -#crypto -# Not yet -#device cryptodev -#device crypto -#device rmisec Property changes on: head/sys/mips/conf/XLR ___________________________________________________________________ Deleted: svn:eol-style ## -1 +0,0 ## -native \ No newline at end of property Deleted: svn:keywords ## -1 +0,0 ## -FreeBSD=%H \ No newline at end of property Deleted: svn:mime-type ## -1 +0,0 ## -text/plain \ No newline at end of property Index: head/sys/mips/conf/XLRN32 =================================================================== --- head/sys/mips/conf/XLRN32 (revision 327460) +++ head/sys/mips/conf/XLRN32 (nonexistent) @@ -1,125 +0,0 @@ -# XLRN32 -- Kernel configuration file for N32 kernel on XLR/XLS -# -# For more information on this file, please read the handbook section on -# Kernel Configuration Files: -# -# https://www.FreeBSD.org/doc/en_US.ISO8859-1/books/handbook/kernelconfig-config.html -# -# The handbook is also available locally in /usr/share/doc/handbook -# if you've installed the doc distribution, otherwise always see the -# FreeBSD World Wide Web server (https://www.FreeBSD.org/) for the -# latest information. -# -# An exhaustive list of options and more detailed explanations of the -# device lines is also present in the ../../conf/NOTES and NOTES files. -# If you are in doubt as to the purpose or necessity of a line, check first -# in NOTES. -# -# $FreeBSD$ - -machine mips mipsn32 -ident XLRN32 -include "../rmi/std.xlr" - -makeoptions MODULES_OVERRIDE="" -makeoptions DEBUG=-g # Build kernel with gdb(1) debug symbols -makeoptions ARCH_FLAGS="-march=mips64 -mabi=n32" -makeoptions KERNLOADADDR=0x80100000 - -#profile 2 - -options SCHED_ULE # ULE scheduler -#options VERBOSE_SYSINIT -#options SCHED_4BSD # 4BSD scheduler -options SMP -options PREEMPTION # Enable kernel thread preemption -#options FULL_PREEMPTION # Enable kernel thread preemption -options INET # InterNETworking -options INET6 # IPv6 communications protocols -options TCP_HHOOK # hhook(9) framework for TCP -options FFS # Berkeley Fast Filesystem -#options SOFTUPDATES # Enable FFS soft updates support -options UFS_ACL # Support for access control lists -options UFS_DIRHASH # Improve performance on big directories -options NFSCL -options NFS_ROOT -# -options BOOTP -options BOOTP_NFSROOT -options BOOTP_NFSV3 -options BOOTP_WIRED_TO=nlge0 -options BOOTP_COMPAT -options ROOTDEVNAME=\"nfs:10.1.1.8:/usr/extra/nfsroot\" -# -#options MD_ROOT # MD is a potential root device -#options MD_ROOT_SIZE=27000 -#options MD_ROOT_SIZE=5120 -#options ROOTDEVNAME=\"ufs:md0\" -options _KPOSIX_PRIORITY_SCHEDULING # POSIX P1003_1B real-time extensions -options HZ=1000 -options NO_SWAPPING - -#Debugging options -options KTRACE # ktrace(1) support -#options DDB -#options KDB -#options GDB -#options ALT_BREAK_TO_DEBUGGER -#options DEADLKRES #Enable the deadlock resolver -options INVARIANTS #Enable calls of extra sanity checking -options INVARIANT_SUPPORT #Extra sanity checks of internal structures, required by INVARIANTS -#options WITNESS #Enable checks to detect deadlocks and cycles -#options WITNESS_SKIPSPIN #Don't run witness on spinlocks for speed -#options KTR # ktr(4) and ktrdump(8) support -#options KTR_COMPILE=(KTR_LOCK|KTR_PROC|KTR_INTR|KTR_CALLOUT|KTR_UMA|KTR_SYSC) -#options KTR_ENTRIES=131072 - -#options LOCK_PROFILING -#options SLEEPQUEUE_PROFILING -#options TURNSTILE_PROFILING - -device pci -#device ata -#options XLR_PERFMON # Enable XLR processor activity monitoring -options BREAK_TO_DEBUGGER -device uart -# Pseudo -device loop -device random -device md -device bpf - -# Network -device miibus -device nlge -device ether -device re -device msk - -device da -device scbus -#device ohci # OHCI PCI->USB interface -device ehci # EHCI PCI->USB interface (USB 2.0) -device usb # USB Bus (required) -options USB_DEBUG # enable debug msgs -#device udbp # USB Double Bulk Pipe devices -#device ugen # Generic -#device uhid # "Human Interface Devices" -device umass # Disks/Mass storage - Requires scbus and da - -#device cfi - -#i2c -device ic -device iic -device iicbb -device iicbus -device ds13rtc # RTC on XLR boards -device max6657 # Temparature sensor on XLR boards -device at24co2n # EEPROM on XLR boards - -#crypto -# Not yet -#device cryptodev -#device crypto -#device rmisec Property changes on: head/sys/mips/conf/XLRN32 ___________________________________________________________________ Deleted: svn:eol-style ## -1 +0,0 ## -native \ No newline at end of property Deleted: svn:keywords ## -1 +0,0 ## -FreeBSD=%H \ No newline at end of property Deleted: svn:mime-type ## -1 +0,0 ## -text/plain \ No newline at end of property Index: head/sys/mips/conf/XLR64 =================================================================== --- head/sys/mips/conf/XLR64 (revision 327460) +++ head/sys/mips/conf/XLR64 (nonexistent) @@ -1,121 +0,0 @@ -# XLR64 -- Kernel configuration file for N64 kernel on XLR/XLS -# -# For more information on this file, please read the handbook section on -# Kernel Configuration Files: -# -# https://www.FreeBSD.org/doc/en_US.ISO8859-1/books/handbook/kernelconfig-config.html -# -# The handbook is also available locally in /usr/share/doc/handbook -# if you've installed the doc distribution, otherwise always see the -# FreeBSD World Wide Web server (https://www.FreeBSD.org/) for the -# latest information. -# -# An exhaustive list of options and more detailed explanations of the -# device lines is also present in the ../../conf/NOTES and NOTES files. -# If you are in doubt as to the purpose or necessity of a line, check first -# in NOTES. -# -# $FreeBSD$ - -machine mips mips64 -ident XLR64 -include "../rmi/std.xlr" - -makeoptions MODULES_OVERRIDE="" -makeoptions DEBUG=-g # Build kernel with gdb(1) debug symbols -makeoptions ARCH_FLAGS="-march=mips64 -mabi=64" -makeoptions KERNLOADADDR=0xffffffff80100000 - -#profile 2 - -options SCHED_ULE # ULE scheduler -#options VERBOSE_SYSINIT -#options SCHED_4BSD # 4BSD scheduler -options SMP -#options PREEMPTION # Enable kernel thread preemption -#options FULL_PREEMPTION # Enable kernel thread preemption -options INET # InterNETworking -options INET6 # IPv6 communications protocols -options TCP_HHOOK # hhook(9) framework for TCP -options FFS # Berkeley Fast Filesystem -#options SOFTUPDATES # Enable FFS soft updates support -options UFS_ACL # Support for access control lists -options UFS_DIRHASH # Improve performance on big directories -options NFSCL -options NFS_ROOT -# -options BOOTP -options BOOTP_NFSROOT -options BOOTP_NFSV3 -options BOOTP_WIRED_TO=nlge0 -options BOOTP_COMPAT -options ROOTDEVNAME=\"nfs:10.1.1.8:/usr/extra/nfsroot\" -# -#options MD_ROOT # MD is a potential root device -#options MD_ROOT_SIZE=27000 -#options MD_ROOT_SIZE=5120 -#options ROOTDEVNAME=\"ufs:md0\" -options _KPOSIX_PRIORITY_SCHEDULING # POSIX P1003_1B real-time extensions -options HZ=1000 -options NO_SWAPPING - -#Debugging options -options KTRACE # ktrace(1) support -options DDB -options KDB -options GDB -options ALT_BREAK_TO_DEBUGGER -options BREAK_TO_DEBUGGER -#options DEADLKRES #Enable the deadlock resolver -options INVARIANTS #Enable calls of extra sanity checking -options INVARIANT_SUPPORT #Extra sanity checks of internal structures, required by INVARIANTS -#options WITNESS #Enable checks to detect deadlocks and cycles -#options WITNESS_SKIPSPIN #Don't run witness on spinlocks for speed -#options KTR # ktr(4) and ktrdump(8) support -#options KTR_COMPILE=(KTR_LOCK|KTR_PROC|KTR_INTR|KTR_CALLOUT|KTR_UMA|KTR_SYSC) -#options KTR_ENTRIES=131072 - -#options LOCK_PROFILING -#options SLEEPQUEUE_PROFILING -#options TURNSTILE_PROFILING - -device pci -#device ata -device uart -# Pseudo -device loop -device random -device md -device bpf - -# Network -device miibus -device nlge -device ether -device re -device msk - -device da -device scbus -device ehci # EHCI PCI->USB interface (USB 2.0) -device usb # USB Bus (required) -options USB_DEBUG # enable debug msgs -#device uhid # "Human Interface Devices" -device umass # Disks/Mass storage - Requires scbus and da - -#device cfi - -#i2c -device ic -device iic -device iicbb -device iicbus -device ds13rtc # RTC on XLR boards -device max6657 # Temparature sensor on XLR boards -device at24co2n # EEPROM on XLR boards - -#crypto -# Not yet -#device cryptodev -#device crypto -#device rmisec Property changes on: head/sys/mips/conf/XLR64 ___________________________________________________________________ Deleted: svn:eol-style ## -1 +0,0 ## -native \ No newline at end of property Deleted: svn:keywords ## -1 +0,0 ## -FreeBSD=%H \ No newline at end of property Deleted: svn:mime-type ## -1 +0,0 ## -text/plain \ No newline at end of property