Index: head/sys/arm/allwinner/a10_gpio.c =================================================================== --- head/sys/arm/allwinner/a10_gpio.c (revision 326578) +++ head/sys/arm/allwinner/a10_gpio.c (revision 326579) @@ -1,1025 +1,1026 @@ /*- * SPDX-License-Identifier: BSD-2-Clause-FreeBSD * * Copyright (c) 2013 Ganbold Tsagaankhuu * Copyright (c) 2012 Oleksandr Tymoshenko * Copyright (c) 2012 Luiz Otavio O Souza. * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. * */ #include __FBSDID("$FreeBSD$"); #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #if defined(__aarch64__) #include "opt_soc.h" #endif #include "gpio_if.h" #define A10_GPIO_DEFAULT_CAPS (GPIO_PIN_INPUT | GPIO_PIN_OUTPUT | \ GPIO_PIN_PULLUP | GPIO_PIN_PULLDOWN) #define A10_GPIO_NONE 0 #define A10_GPIO_PULLUP 1 #define A10_GPIO_PULLDOWN 2 #define A10_GPIO_INPUT 0 #define A10_GPIO_OUTPUT 1 #define AW_GPIO_DRV_MASK 0x3 #define AW_GPIO_PUD_MASK 0x3 #define AW_PINCTRL 1 #define AW_R_PINCTRL 2 /* Defined in a10_padconf.c */ #ifdef SOC_ALLWINNER_A10 extern const struct allwinner_padconf a10_padconf; #endif /* Defined in a13_padconf.c */ #ifdef SOC_ALLWINNER_A13 extern const struct allwinner_padconf a13_padconf; #endif /* Defined in a20_padconf.c */ #ifdef SOC_ALLWINNER_A20 extern const struct allwinner_padconf a20_padconf; #endif /* Defined in a31_padconf.c */ #ifdef SOC_ALLWINNER_A31 extern const struct allwinner_padconf a31_padconf; #endif /* Defined in a31s_padconf.c */ #ifdef SOC_ALLWINNER_A31S extern const struct allwinner_padconf a31s_padconf; #endif #if defined(SOC_ALLWINNER_A31) || defined(SOC_ALLWINNER_A31S) extern const struct allwinner_padconf a31_r_padconf; #endif /* Defined in a33_padconf.c */ #ifdef SOC_ALLWINNER_A33 extern const struct allwinner_padconf a33_padconf; #endif /* Defined in h3_padconf.c */ -#ifdef SOC_ALLWINNER_H3 +#if defined(SOC_ALLWINNER_H3) || defined(SOC_ALLWINNER_H5) extern const struct allwinner_padconf h3_padconf; extern const struct allwinner_padconf h3_r_padconf; #endif /* Defined in a83t_padconf.c */ #ifdef SOC_ALLWINNER_A83T extern const struct allwinner_padconf a83t_padconf; extern const struct allwinner_padconf a83t_r_padconf; #endif /* Defined in a64_padconf.c */ #ifdef SOC_ALLWINNER_A64 extern const struct allwinner_padconf a64_padconf; extern const struct allwinner_padconf a64_r_padconf; #endif static struct ofw_compat_data compat_data[] = { #ifdef SOC_ALLWINNER_A10 {"allwinner,sun4i-a10-pinctrl", (uintptr_t)&a10_padconf}, #endif #ifdef SOC_ALLWINNER_A13 {"allwinner,sun5i-a13-pinctrl", (uintptr_t)&a13_padconf}, #endif #ifdef SOC_ALLWINNER_A20 {"allwinner,sun7i-a20-pinctrl", (uintptr_t)&a20_padconf}, #endif #ifdef SOC_ALLWINNER_A31 {"allwinner,sun6i-a31-pinctrl", (uintptr_t)&a31_padconf}, #endif #ifdef SOC_ALLWINNER_A31S {"allwinner,sun6i-a31s-pinctrl", (uintptr_t)&a31s_padconf}, #endif #if defined(SOC_ALLWINNER_A31) || defined(SOC_ALLWINNER_A31S) {"allwinner,sun6i-a31-r-pinctrl", (uintptr_t)&a31_r_padconf}, #endif #ifdef SOC_ALLWINNER_A33 {"allwinner,sun6i-a33-pinctrl", (uintptr_t)&a33_padconf}, #endif #ifdef SOC_ALLWINNER_A83T {"allwinner,sun8i-a83t-pinctrl", (uintptr_t)&a83t_padconf}, {"allwinner,sun8i-a83t-r-pinctrl", (uintptr_t)&a83t_r_padconf}, #endif -#ifdef SOC_ALLWINNER_H3 +#if defined(SOC_ALLWINNER_H3) || defined(SOC_ALLWINNER_H5) {"allwinner,sun8i-h3-pinctrl", (uintptr_t)&h3_padconf}, + {"allwinner,sun50i-h5-pinctrl", (uintptr_t)&h3_padconf}, {"allwinner,sun8i-h3-r-pinctrl", (uintptr_t)&h3_r_padconf}, #endif #ifdef SOC_ALLWINNER_A64 {"allwinner,sun50i-a64-pinctrl", (uintptr_t)&a64_padconf}, {"allwinner,sun50i-a64-r-pinctrl", (uintptr_t)&a64_r_padconf}, #endif {NULL, 0} }; struct clk_list { TAILQ_ENTRY(clk_list) next; clk_t clk; }; struct a10_gpio_softc { device_t sc_dev; device_t sc_busdev; struct mtx sc_mtx; struct resource * sc_mem_res; struct resource * sc_irq_res; bus_space_tag_t sc_bst; bus_space_handle_t sc_bsh; void * sc_intrhand; const struct allwinner_padconf * padconf; TAILQ_HEAD(, clk_list) clk_list; }; #define A10_GPIO_LOCK(_sc) mtx_lock_spin(&(_sc)->sc_mtx) #define A10_GPIO_UNLOCK(_sc) mtx_unlock_spin(&(_sc)->sc_mtx) #define A10_GPIO_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->sc_mtx, MA_OWNED) #define A10_GPIO_GP_CFG(_bank, _idx) 0x00 + ((_bank) * 0x24) + ((_idx) << 2) #define A10_GPIO_GP_DAT(_bank) 0x10 + ((_bank) * 0x24) #define A10_GPIO_GP_DRV(_bank, _idx) 0x14 + ((_bank) * 0x24) + ((_idx) << 2) #define A10_GPIO_GP_PUL(_bank, _idx) 0x1c + ((_bank) * 0x24) + ((_idx) << 2) #define A10_GPIO_GP_INT_CFG0 0x200 #define A10_GPIO_GP_INT_CFG1 0x204 #define A10_GPIO_GP_INT_CFG2 0x208 #define A10_GPIO_GP_INT_CFG3 0x20c #define A10_GPIO_GP_INT_CTL 0x210 #define A10_GPIO_GP_INT_STA 0x214 #define A10_GPIO_GP_INT_DEB 0x218 static char *a10_gpio_parse_function(phandle_t node); static const char **a10_gpio_parse_pins(phandle_t node, int *pins_nb); static uint32_t a10_gpio_parse_bias(phandle_t node); static int a10_gpio_parse_drive_strength(phandle_t node, uint32_t *drive); static int a10_gpio_pin_get(device_t dev, uint32_t pin, unsigned int *value); static int a10_gpio_pin_set(device_t dev, uint32_t pin, unsigned int value); static int a10_gpio_pin_get_locked(struct a10_gpio_softc *sc, uint32_t pin, unsigned int *value); static int a10_gpio_pin_set_locked(struct a10_gpio_softc *sc, uint32_t pin, unsigned int value); #define A10_GPIO_WRITE(_sc, _off, _val) \ bus_space_write_4(_sc->sc_bst, _sc->sc_bsh, _off, _val) #define A10_GPIO_READ(_sc, _off) \ bus_space_read_4(_sc->sc_bst, _sc->sc_bsh, _off) static uint32_t a10_gpio_get_function(struct a10_gpio_softc *sc, uint32_t pin) { uint32_t bank, func, offset; /* Must be called with lock held. */ A10_GPIO_LOCK_ASSERT(sc); if (pin > sc->padconf->npins) return (0); bank = sc->padconf->pins[pin].port; pin = sc->padconf->pins[pin].pin; offset = ((pin & 0x07) << 2); func = A10_GPIO_READ(sc, A10_GPIO_GP_CFG(bank, pin >> 3)); return ((func >> offset) & 0x7); } static int a10_gpio_set_function(struct a10_gpio_softc *sc, uint32_t pin, uint32_t f) { uint32_t bank, data, offset; /* Check if the function exists in the padconf data */ if (sc->padconf->pins[pin].functions[f] == NULL) return (EINVAL); /* Must be called with lock held. */ A10_GPIO_LOCK_ASSERT(sc); bank = sc->padconf->pins[pin].port; pin = sc->padconf->pins[pin].pin; offset = ((pin & 0x07) << 2); data = A10_GPIO_READ(sc, A10_GPIO_GP_CFG(bank, pin >> 3)); data &= ~(7 << offset); data |= (f << offset); A10_GPIO_WRITE(sc, A10_GPIO_GP_CFG(bank, pin >> 3), data); return (0); } static uint32_t a10_gpio_get_pud(struct a10_gpio_softc *sc, uint32_t pin) { uint32_t bank, offset, val; /* Must be called with lock held. */ A10_GPIO_LOCK_ASSERT(sc); bank = sc->padconf->pins[pin].port; pin = sc->padconf->pins[pin].pin; offset = ((pin & 0x0f) << 1); val = A10_GPIO_READ(sc, A10_GPIO_GP_PUL(bank, pin >> 4)); return ((val >> offset) & AW_GPIO_PUD_MASK); } static void a10_gpio_set_pud(struct a10_gpio_softc *sc, uint32_t pin, uint32_t state) { uint32_t bank, offset, val; if (a10_gpio_get_pud(sc, pin) == state) return; /* Must be called with lock held. */ A10_GPIO_LOCK_ASSERT(sc); bank = sc->padconf->pins[pin].port; pin = sc->padconf->pins[pin].pin; offset = ((pin & 0x0f) << 1); val = A10_GPIO_READ(sc, A10_GPIO_GP_PUL(bank, pin >> 4)); val &= ~(AW_GPIO_PUD_MASK << offset); val |= (state << offset); A10_GPIO_WRITE(sc, A10_GPIO_GP_PUL(bank, pin >> 4), val); } static uint32_t a10_gpio_get_drv(struct a10_gpio_softc *sc, uint32_t pin) { uint32_t bank, offset, val; /* Must be called with lock held. */ A10_GPIO_LOCK_ASSERT(sc); bank = sc->padconf->pins[pin].port; pin = sc->padconf->pins[pin].pin; offset = ((pin & 0x0f) << 1); val = A10_GPIO_READ(sc, A10_GPIO_GP_DRV(bank, pin >> 4)); return ((val >> offset) & AW_GPIO_DRV_MASK); } static void a10_gpio_set_drv(struct a10_gpio_softc *sc, uint32_t pin, uint32_t drive) { uint32_t bank, offset, val; if (a10_gpio_get_drv(sc, pin) == drive) return; /* Must be called with lock held. */ A10_GPIO_LOCK_ASSERT(sc); bank = sc->padconf->pins[pin].port; pin = sc->padconf->pins[pin].pin; offset = ((pin & 0x0f) << 1); val = A10_GPIO_READ(sc, A10_GPIO_GP_DRV(bank, pin >> 4)); val &= ~(AW_GPIO_DRV_MASK << offset); val |= (drive << offset); A10_GPIO_WRITE(sc, A10_GPIO_GP_DRV(bank, pin >> 4), val); } static int a10_gpio_pin_configure(struct a10_gpio_softc *sc, uint32_t pin, uint32_t flags) { u_int val; int err = 0; /* Must be called with lock held. */ A10_GPIO_LOCK_ASSERT(sc); if (pin > sc->padconf->npins) return (EINVAL); /* Manage input/output. */ if (flags & GPIO_PIN_INPUT) { err = a10_gpio_set_function(sc, pin, A10_GPIO_INPUT); } else if (flags & GPIO_PIN_OUTPUT) { if (flags & GPIO_PIN_PRESET_LOW) { a10_gpio_pin_set_locked(sc, pin, 0); } else if (flags & GPIO_PIN_PRESET_HIGH) { a10_gpio_pin_set_locked(sc, pin, 1); } else { /* Read the pin and preset output to current state. */ err = a10_gpio_set_function(sc, pin, A10_GPIO_INPUT); if (err == 0) { a10_gpio_pin_get_locked(sc, pin, &val); a10_gpio_pin_set_locked(sc, pin, val); } } if (err == 0) err = a10_gpio_set_function(sc, pin, A10_GPIO_OUTPUT); } if (err) return (err); /* Manage Pull-up/pull-down. */ if (flags & GPIO_PIN_PULLUP) a10_gpio_set_pud(sc, pin, A10_GPIO_PULLUP); else if (flags & GPIO_PIN_PULLDOWN) a10_gpio_set_pud(sc, pin, A10_GPIO_PULLDOWN); else a10_gpio_set_pud(sc, pin, A10_GPIO_NONE); return (0); } static device_t a10_gpio_get_bus(device_t dev) { struct a10_gpio_softc *sc; sc = device_get_softc(dev); return (sc->sc_busdev); } static int a10_gpio_pin_max(device_t dev, int *maxpin) { struct a10_gpio_softc *sc; sc = device_get_softc(dev); *maxpin = sc->padconf->npins - 1; return (0); } static int a10_gpio_pin_getcaps(device_t dev, uint32_t pin, uint32_t *caps) { struct a10_gpio_softc *sc; sc = device_get_softc(dev); if (pin >= sc->padconf->npins) return (EINVAL); *caps = A10_GPIO_DEFAULT_CAPS; return (0); } static int a10_gpio_pin_getflags(device_t dev, uint32_t pin, uint32_t *flags) { struct a10_gpio_softc *sc; uint32_t func; uint32_t pud; sc = device_get_softc(dev); if (pin >= sc->padconf->npins) return (EINVAL); A10_GPIO_LOCK(sc); func = a10_gpio_get_function(sc, pin); switch (func) { case A10_GPIO_INPUT: *flags = GPIO_PIN_INPUT; break; case A10_GPIO_OUTPUT: *flags = GPIO_PIN_OUTPUT; break; default: *flags = 0; break; } pud = a10_gpio_get_pud(sc, pin); switch (pud) { case A10_GPIO_PULLDOWN: *flags |= GPIO_PIN_PULLDOWN; break; case A10_GPIO_PULLUP: *flags |= GPIO_PIN_PULLUP; break; default: break; } A10_GPIO_UNLOCK(sc); return (0); } static int a10_gpio_pin_getname(device_t dev, uint32_t pin, char *name) { struct a10_gpio_softc *sc; sc = device_get_softc(dev); if (pin >= sc->padconf->npins) return (EINVAL); snprintf(name, GPIOMAXNAME - 1, "%s", sc->padconf->pins[pin].name); name[GPIOMAXNAME - 1] = '\0'; return (0); } static int a10_gpio_pin_setflags(device_t dev, uint32_t pin, uint32_t flags) { struct a10_gpio_softc *sc; int err; sc = device_get_softc(dev); if (pin > sc->padconf->npins) return (EINVAL); A10_GPIO_LOCK(sc); err = a10_gpio_pin_configure(sc, pin, flags); A10_GPIO_UNLOCK(sc); return (err); } static int a10_gpio_pin_set_locked(struct a10_gpio_softc *sc, uint32_t pin, unsigned int value) { uint32_t bank, data; A10_GPIO_LOCK_ASSERT(sc); if (pin > sc->padconf->npins) return (EINVAL); bank = sc->padconf->pins[pin].port; pin = sc->padconf->pins[pin].pin; data = A10_GPIO_READ(sc, A10_GPIO_GP_DAT(bank)); if (value) data |= (1 << pin); else data &= ~(1 << pin); A10_GPIO_WRITE(sc, A10_GPIO_GP_DAT(bank), data); return (0); } static int a10_gpio_pin_set(device_t dev, uint32_t pin, unsigned int value) { struct a10_gpio_softc *sc; int ret; sc = device_get_softc(dev); A10_GPIO_LOCK(sc); ret = a10_gpio_pin_set_locked(sc, pin, value); A10_GPIO_UNLOCK(sc); return (ret); } static int a10_gpio_pin_get_locked(struct a10_gpio_softc *sc,uint32_t pin, unsigned int *val) { uint32_t bank, reg_data; A10_GPIO_LOCK_ASSERT(sc); if (pin > sc->padconf->npins) return (EINVAL); bank = sc->padconf->pins[pin].port; pin = sc->padconf->pins[pin].pin; reg_data = A10_GPIO_READ(sc, A10_GPIO_GP_DAT(bank)); *val = (reg_data & (1 << pin)) ? 1 : 0; return (0); } static char * a10_gpio_parse_function(phandle_t node) { char *function; if (OF_getprop_alloc(node, "function", sizeof(*function), (void **)&function) != -1) return (function); if (OF_getprop_alloc(node, "allwinner,function", sizeof(*function), (void **)&function) != -1) return (function); return (NULL); } static const char ** a10_gpio_parse_pins(phandle_t node, int *pins_nb) { const char **pinlist; *pins_nb = ofw_bus_string_list_to_array(node, "pins", &pinlist); if (*pins_nb > 0) return (pinlist); *pins_nb = ofw_bus_string_list_to_array(node, "allwinner,pins", &pinlist); if (*pins_nb > 0) return (pinlist); return (NULL); } static uint32_t a10_gpio_parse_bias(phandle_t node) { uint32_t bias; if (OF_getencprop(node, "pull", &bias, sizeof(bias)) != -1) return (bias); if (OF_getencprop(node, "allwinner,pull", &bias, sizeof(bias)) != -1) return (bias); if (OF_hasprop(node, "bias-disable")) return (A10_GPIO_NONE); if (OF_hasprop(node, "bias-pull-up")) return (A10_GPIO_PULLUP); if (OF_hasprop(node, "bias-pull-down")) return (A10_GPIO_PULLDOWN); return (A10_GPIO_NONE); } static int a10_gpio_parse_drive_strength(phandle_t node, uint32_t *drive) { uint32_t drive_str; if (OF_getencprop(node, "drive", drive, sizeof(*drive)) != -1) return (0); if (OF_getencprop(node, "allwinner,drive", drive, sizeof(*drive)) != -1) return (0); if (OF_getencprop(node, "drive-strength", &drive_str, sizeof(drive_str)) != -1) { *drive = (drive_str / 10) - 1; return (0); } return (1); } static int a10_gpio_pin_get(device_t dev, uint32_t pin, unsigned int *val) { struct a10_gpio_softc *sc; int ret; sc = device_get_softc(dev); A10_GPIO_LOCK(sc); ret = a10_gpio_pin_get_locked(sc, pin, val); A10_GPIO_UNLOCK(sc); return (ret); } static int a10_gpio_pin_toggle(device_t dev, uint32_t pin) { struct a10_gpio_softc *sc; uint32_t bank, data; sc = device_get_softc(dev); if (pin > sc->padconf->npins) return (EINVAL); bank = sc->padconf->pins[pin].port; pin = sc->padconf->pins[pin].pin; A10_GPIO_LOCK(sc); data = A10_GPIO_READ(sc, A10_GPIO_GP_DAT(bank)); if (data & (1 << pin)) data &= ~(1 << pin); else data |= (1 << pin); A10_GPIO_WRITE(sc, A10_GPIO_GP_DAT(bank), data); A10_GPIO_UNLOCK(sc); return (0); } static int a10_gpio_pin_access_32(device_t dev, uint32_t first_pin, uint32_t clear_pins, uint32_t change_pins, uint32_t *orig_pins) { struct a10_gpio_softc *sc; uint32_t bank, data, pin; sc = device_get_softc(dev); if (first_pin > sc->padconf->npins) return (EINVAL); /* * We require that first_pin refers to the first pin in a bank, because * this API is not about convenience, it's for making a set of pins * change simultaneously (required) with reasonably high performance * (desired); we need to do a read-modify-write on a single register. */ bank = sc->padconf->pins[first_pin].port; pin = sc->padconf->pins[first_pin].pin; if (pin != 0) return (EINVAL); A10_GPIO_LOCK(sc); data = A10_GPIO_READ(sc, A10_GPIO_GP_DAT(bank)); if ((clear_pins | change_pins) != 0) A10_GPIO_WRITE(sc, A10_GPIO_GP_DAT(bank), (data & ~clear_pins) ^ change_pins); A10_GPIO_UNLOCK(sc); if (orig_pins != NULL) *orig_pins = data; return (0); } static int a10_gpio_pin_config_32(device_t dev, uint32_t first_pin, uint32_t num_pins, uint32_t *pin_flags) { struct a10_gpio_softc *sc; uint32_t bank, pin; int err; sc = device_get_softc(dev); if (first_pin > sc->padconf->npins) return (EINVAL); bank = sc->padconf->pins[first_pin].port; if (sc->padconf->pins[first_pin].pin != 0) return (EINVAL); /* * The configuration for a bank of pins is scattered among several * registers; we cannot g'tee to simultaneously change the state of all * the pins in the flags array. So just loop through the array * configuring each pin for now. If there was a strong need, it might * be possible to support some limited simultaneous config, such as * adjacent groups of 8 pins that line up the same as the config regs. */ for (err = 0, pin = first_pin; err == 0 && pin < num_pins; ++pin) { if (pin_flags[pin] & (GPIO_PIN_INPUT | GPIO_PIN_OUTPUT)) err = a10_gpio_pin_configure(sc, pin, pin_flags[pin]); } return (err); } static int aw_find_pinnum_by_name(struct a10_gpio_softc *sc, const char *pinname) { int i; for (i = 0; i < sc->padconf->npins; i++) if (!strcmp(pinname, sc->padconf->pins[i].name)) return i; return (-1); } static int aw_find_pin_func(struct a10_gpio_softc *sc, int pin, const char *func) { int i; for (i = 0; i < AW_MAX_FUNC_BY_PIN; i++) if (sc->padconf->pins[pin].functions[i] && !strcmp(func, sc->padconf->pins[pin].functions[i])) return (i); return (-1); } static int aw_fdt_configure_pins(device_t dev, phandle_t cfgxref) { struct a10_gpio_softc *sc; phandle_t node; const char **pinlist = NULL; char *pin_function = NULL; uint32_t pin_drive, pin_pull; int pins_nb, pin_num, pin_func, i, ret; bool set_drive; sc = device_get_softc(dev); node = OF_node_from_xref(cfgxref); ret = 0; set_drive = false; /* Getting all prop for configuring pins */ pinlist = a10_gpio_parse_pins(node, &pins_nb); if (pinlist == NULL) return (ENOENT); pin_function = a10_gpio_parse_function(node); if (pin_function == NULL) { ret = ENOENT; goto out; } if (a10_gpio_parse_drive_strength(node, &pin_drive) == 0) set_drive = true; pin_pull = a10_gpio_parse_bias(node); /* Configure each pin to the correct function, drive and pull */ for (i = 0; i < pins_nb; i++) { pin_num = aw_find_pinnum_by_name(sc, pinlist[i]); if (pin_num == -1) { ret = ENOENT; goto out; } pin_func = aw_find_pin_func(sc, pin_num, pin_function); if (pin_func == -1) { ret = ENOENT; goto out; } A10_GPIO_LOCK(sc); if (a10_gpio_get_function(sc, pin_num) != pin_func) a10_gpio_set_function(sc, pin_num, pin_func); if (set_drive) a10_gpio_set_drv(sc, pin_num, pin_drive); if (pin_pull != A10_GPIO_NONE) a10_gpio_set_pud(sc, pin_num, pin_pull); A10_GPIO_UNLOCK(sc); } out: OF_prop_free(pinlist); OF_prop_free(pin_function); return (ret); } static int a10_gpio_probe(device_t dev) { if (!ofw_bus_status_okay(dev)) return (ENXIO); if (ofw_bus_search_compatible(dev, compat_data)->ocd_data == 0) return (ENXIO); device_set_desc(dev, "Allwinner GPIO/Pinmux controller"); return (BUS_PROBE_DEFAULT); } static int a10_gpio_attach(device_t dev) { int rid, error; phandle_t gpio; struct a10_gpio_softc *sc; struct clk_list *clkp, *clkp_tmp; clk_t clk; hwreset_t rst = NULL; int off, err, clkret; sc = device_get_softc(dev); sc->sc_dev = dev; mtx_init(&sc->sc_mtx, "a10 gpio", "gpio", MTX_SPIN); rid = 0; sc->sc_mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, RF_ACTIVE); if (!sc->sc_mem_res) { device_printf(dev, "cannot allocate memory window\n"); goto fail; } sc->sc_bst = rman_get_bustag(sc->sc_mem_res); sc->sc_bsh = rman_get_bushandle(sc->sc_mem_res); rid = 0; sc->sc_irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, RF_ACTIVE); if (!sc->sc_irq_res) { device_printf(dev, "cannot allocate interrupt\n"); goto fail; } /* Find our node. */ gpio = ofw_bus_get_node(sc->sc_dev); if (!OF_hasprop(gpio, "gpio-controller")) /* Node is not a GPIO controller. */ goto fail; /* Use the right pin data for the current SoC */ sc->padconf = (struct allwinner_padconf *)ofw_bus_search_compatible(dev, compat_data)->ocd_data; if (hwreset_get_by_ofw_idx(dev, 0, 0, &rst) == 0) { error = hwreset_deassert(rst); if (error != 0) { device_printf(dev, "cannot de-assert reset\n"); goto fail; } } TAILQ_INIT(&sc->clk_list); for (off = 0, clkret = 0; clkret == 0; off++) { clkret = clk_get_by_ofw_index(dev, 0, off, &clk); if (clkret != 0) break; err = clk_enable(clk); if (err != 0) { device_printf(dev, "Could not enable clock %s\n", clk_get_name(clk)); goto fail; } clkp = malloc(sizeof(*clkp), M_DEVBUF, M_WAITOK | M_ZERO); clkp->clk = clk; TAILQ_INSERT_TAIL(&sc->clk_list, clkp, next); } if (clkret != 0 && clkret != ENOENT) { device_printf(dev, "Could not find clock at offset %d (%d)\n", off, clkret); goto fail; } sc->sc_busdev = gpiobus_attach_bus(dev); if (sc->sc_busdev == NULL) goto fail; /* * Register as a pinctrl device */ fdt_pinctrl_register(dev, "pins"); fdt_pinctrl_configure_tree(dev); fdt_pinctrl_register(dev, "allwinner,pins"); fdt_pinctrl_configure_tree(dev); return (0); fail: if (sc->sc_irq_res) bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sc_irq_res); if (sc->sc_mem_res) bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->sc_mem_res); mtx_destroy(&sc->sc_mtx); /* Disable clock */ TAILQ_FOREACH_SAFE(clkp, &sc->clk_list, next, clkp_tmp) { err = clk_disable(clkp->clk); if (err != 0) device_printf(dev, "Could not disable clock %s\n", clk_get_name(clkp->clk)); err = clk_release(clkp->clk); if (err != 0) device_printf(dev, "Could not release clock %s\n", clk_get_name(clkp->clk)); TAILQ_REMOVE(&sc->clk_list, clkp, next); free(clkp, M_DEVBUF); } /* Assert resets */ if (rst) { hwreset_assert(rst); hwreset_release(rst); } return (ENXIO); } static int a10_gpio_detach(device_t dev) { return (EBUSY); } static phandle_t a10_gpio_get_node(device_t dev, device_t bus) { /* We only have one child, the GPIO bus, which needs our own node. */ return (ofw_bus_get_node(dev)); } static int a10_gpio_map_gpios(device_t bus, phandle_t dev, phandle_t gparent, int gcells, pcell_t *gpios, uint32_t *pin, uint32_t *flags) { struct a10_gpio_softc *sc; int i; sc = device_get_softc(bus); /* The GPIO pins are mapped as: . */ for (i = 0; i < sc->padconf->npins; i++) if (sc->padconf->pins[i].port == gpios[0] && sc->padconf->pins[i].pin == gpios[1]) { *pin = i; break; } *flags = gpios[gcells - 1]; return (0); } static device_method_t a10_gpio_methods[] = { /* Device interface */ DEVMETHOD(device_probe, a10_gpio_probe), DEVMETHOD(device_attach, a10_gpio_attach), DEVMETHOD(device_detach, a10_gpio_detach), /* GPIO protocol */ DEVMETHOD(gpio_get_bus, a10_gpio_get_bus), DEVMETHOD(gpio_pin_max, a10_gpio_pin_max), DEVMETHOD(gpio_pin_getname, a10_gpio_pin_getname), DEVMETHOD(gpio_pin_getflags, a10_gpio_pin_getflags), DEVMETHOD(gpio_pin_getcaps, a10_gpio_pin_getcaps), DEVMETHOD(gpio_pin_setflags, a10_gpio_pin_setflags), DEVMETHOD(gpio_pin_get, a10_gpio_pin_get), DEVMETHOD(gpio_pin_set, a10_gpio_pin_set), DEVMETHOD(gpio_pin_toggle, a10_gpio_pin_toggle), DEVMETHOD(gpio_pin_access_32, a10_gpio_pin_access_32), DEVMETHOD(gpio_pin_config_32, a10_gpio_pin_config_32), DEVMETHOD(gpio_map_gpios, a10_gpio_map_gpios), /* ofw_bus interface */ DEVMETHOD(ofw_bus_get_node, a10_gpio_get_node), /* fdt_pinctrl interface */ DEVMETHOD(fdt_pinctrl_configure,aw_fdt_configure_pins), DEVMETHOD_END }; static devclass_t a10_gpio_devclass; static driver_t a10_gpio_driver = { "gpio", a10_gpio_methods, sizeof(struct a10_gpio_softc), }; EARLY_DRIVER_MODULE(a10_gpio, simplebus, a10_gpio_driver, a10_gpio_devclass, 0, 0, BUS_PASS_INTERRUPT + BUS_PASS_ORDER_LATE); Index: head/sys/arm/allwinner/clkng/ccu_h3.c =================================================================== --- head/sys/arm/allwinner/clkng/ccu_h3.c (revision 326578) +++ head/sys/arm/allwinner/clkng/ccu_h3.c (revision 326579) @@ -1,761 +1,765 @@ /*- * Copyright (c) 2017 Emmanuel Vadot * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. * * $FreeBSD$ */ #include __FBSDID("$FreeBSD$"); #include #include #include #include #include #include +#if defined(__aarch64__) +#include "opt_soc.h" +#endif + #include #include #include #include #include #include #include #include "ccu_h3.h" /* Non-exported resets */ #define RST_BUS_SCR 53 /* Non-exported clocks */ #define CLK_PLL_CPUX 0 #define CLK_PLL_AUDIO_BASE 1 #define CLK_PLL_AUDIO 2 #define CLK_PLL_AUDIO_2X 3 #define CLK_PLL_AUDIO_4X 4 #define CLK_PLL_AUDIO_8X 5 #define CLK_PLL_VIDEO 6 #define CLK_PLL_VE 7 #define CLK_PLL_DDR 8 #define CLK_PLL_PERIPH0_2X 10 #define CLK_PLL_GPU 11 #define CLK_PLL_PERIPH1 12 #define CLK_PLL_DE 13 #define CLK_AXI 15 #define CLK_AHB1 16 #define CLK_APB1 17 #define CLK_APB2 18 #define CLK_AHB2 19 #define CLK_BUS_SCR 66 #define CLK_USBPHY0 88 #define CLK_USBPHY1 89 #define CLK_USBPHY2 90 #define CLK_USBPHY3 91 #define CLK_USBOHCI0 92 #define CLK_USBOHCI1 93 #define CLK_USBOHCI2 94 #define CLK_USBOHCI3 95 #define CLK_DRAM 96 #define CLK_MBUS 113 static struct aw_ccung_reset h3_ccu_resets[] = { CCU_RESET(RST_USB_PHY0, 0xcc, 0) CCU_RESET(RST_USB_PHY1, 0xcc, 1) CCU_RESET(RST_USB_PHY2, 0xcc, 2) CCU_RESET(RST_USB_PHY3, 0xcc, 3) CCU_RESET(RST_MBUS, 0xfc, 31) CCU_RESET(RST_BUS_CE, 0x2c0, 5) CCU_RESET(RST_BUS_DMA, 0x2c0, 6) CCU_RESET(RST_BUS_MMC0, 0x2c0, 8) CCU_RESET(RST_BUS_MMC1, 0x2c0, 9) CCU_RESET(RST_BUS_MMC2, 0x2c0, 10) CCU_RESET(RST_BUS_NAND, 0x2c0, 13) CCU_RESET(RST_BUS_DRAM, 0x2c0, 14) CCU_RESET(RST_BUS_EMAC, 0x2c0, 17) CCU_RESET(RST_BUS_TS, 0x2c0, 18) CCU_RESET(RST_BUS_HSTIMER, 0x2c0, 19) CCU_RESET(RST_BUS_SPI0, 0x2c0, 20) CCU_RESET(RST_BUS_SPI1, 0x2c0, 21) CCU_RESET(RST_BUS_OTG, 0x2c0, 23) CCU_RESET(RST_BUS_EHCI0, 0x2c0, 24) CCU_RESET(RST_BUS_EHCI1, 0x2c0, 25) CCU_RESET(RST_BUS_EHCI2, 0x2c0, 26) CCU_RESET(RST_BUS_EHCI3, 0x2c0, 27) CCU_RESET(RST_BUS_OHCI0, 0x2c0, 28) CCU_RESET(RST_BUS_OHCI1, 0x2c0, 29) CCU_RESET(RST_BUS_OHCI2, 0x2c0, 30) CCU_RESET(RST_BUS_OHCI3, 0x2c0, 31) CCU_RESET(RST_BUS_VE, 0x2c4, 0) CCU_RESET(RST_BUS_TCON0, 0x2c4, 3) CCU_RESET(RST_BUS_TCON1, 0x2c4, 4) CCU_RESET(RST_BUS_DEINTERLACE, 0x2c4, 5) CCU_RESET(RST_BUS_CSI, 0x2c4, 8) CCU_RESET(RST_BUS_TVE, 0x2c4, 9) CCU_RESET(RST_BUS_HDMI0, 0x2c4, 10) CCU_RESET(RST_BUS_HDMI1, 0x2c4, 11) CCU_RESET(RST_BUS_DE, 0x2c4, 12) CCU_RESET(RST_BUS_GPU, 0x2c4, 20) CCU_RESET(RST_BUS_MSGBOX, 0x2c4, 21) CCU_RESET(RST_BUS_SPINLOCK, 0x2c4, 22) CCU_RESET(RST_BUS_DBG, 0x2c4, 31) CCU_RESET(RST_BUS_EPHY, 0x2c8, 2) CCU_RESET(RST_BUS_CODEC, 0x2d0, 0) CCU_RESET(RST_BUS_SPDIF, 0x2d0, 1) CCU_RESET(RST_BUS_THS, 0x2d0, 8) CCU_RESET(RST_BUS_I2S0, 0x2d0, 12) CCU_RESET(RST_BUS_I2S1, 0x2d0, 13) CCU_RESET(RST_BUS_I2S2, 0x2d0, 14) CCU_RESET(RST_BUS_I2C0, 0x2d8, 0) CCU_RESET(RST_BUS_I2C1, 0x2d8, 1) CCU_RESET(RST_BUS_I2C2, 0x2d8, 2) CCU_RESET(RST_BUS_UART0, 0x2d8, 16) CCU_RESET(RST_BUS_UART1, 0x2d8, 17) CCU_RESET(RST_BUS_UART2, 0x2d8, 18) CCU_RESET(RST_BUS_UART3, 0x2d8, 19) CCU_RESET(RST_BUS_SCR, 0x2d8, 20) }; static struct aw_ccung_gate h3_ccu_gates[] = { CCU_GATE(CLK_BUS_CE, "bus-ce", "ahb1", 0x60, 5) CCU_GATE(CLK_BUS_DMA, "bus-dma", "ahb1", 0x60, 6) CCU_GATE(CLK_BUS_MMC0, "bus-mmc0", "ahb1", 0x60, 8) CCU_GATE(CLK_BUS_MMC1, "bus-mmc1", "ahb1", 0x60, 9) CCU_GATE(CLK_BUS_MMC2, "bus-mmc2", "ahb1", 0x60, 10) CCU_GATE(CLK_BUS_NAND, "bus-nand", "ahb1", 0x60, 13) CCU_GATE(CLK_BUS_DRAM, "bus-dram", "ahb1", 0x60, 14) CCU_GATE(CLK_BUS_EMAC, "bus-emac", "ahb2", 0x60, 17) CCU_GATE(CLK_BUS_TS, "bus-ts", "ahb1", 0x60, 18) CCU_GATE(CLK_BUS_HSTIMER, "bus-hstimer", "ahb1", 0x60, 19) CCU_GATE(CLK_BUS_SPI0, "bus-spi0", "ahb1", 0x60, 20) CCU_GATE(CLK_BUS_SPI1, "bus-spi1", "ahb1", 0x60, 21) CCU_GATE(CLK_BUS_OTG, "bus-otg", "ahb1", 0x60, 23) CCU_GATE(CLK_BUS_EHCI0, "bus-ehci0", "ahb1", 0x60, 24) CCU_GATE(CLK_BUS_EHCI1, "bus-ehci1", "ahb2", 0x60, 25) CCU_GATE(CLK_BUS_EHCI2, "bus-ehci2", "ahb2", 0x60, 26) CCU_GATE(CLK_BUS_EHCI3, "bus-ehci3", "ahb2", 0x60, 27) CCU_GATE(CLK_BUS_OHCI0, "bus-ohci0", "ahb1", 0x60, 28) CCU_GATE(CLK_BUS_OHCI1, "bus-ohci1", "ahb2", 0x60, 29) CCU_GATE(CLK_BUS_OHCI2, "bus-ohci2", "ahb2", 0x60, 30) CCU_GATE(CLK_BUS_OHCI3, "bus-ohci3", "ahb2", 0x60, 31) CCU_GATE(CLK_BUS_VE, "bus-ve", "ahb1", 0x64, 0) CCU_GATE(CLK_BUS_TCON0, "bus-tcon0", "ahb1", 0x64, 3) CCU_GATE(CLK_BUS_TCON1, "bus-tcon1", "ahb1", 0x64, 4) CCU_GATE(CLK_BUS_DEINTERLACE, "bus-deinterlace", "ahb1", 0x64, 5) CCU_GATE(CLK_BUS_CSI, "bus-csi", "ahb1", 0x64, 8) CCU_GATE(CLK_BUS_TVE, "bus-tve", "ahb1", 0x64, 9) CCU_GATE(CLK_BUS_HDMI, "bus-hdmi", "ahb1", 0x64, 11) CCU_GATE(CLK_BUS_DE, "bus-de", "ahb1", 0x64, 12) CCU_GATE(CLK_BUS_GPU, "bus-gpu", "ahb1", 0x64, 20) CCU_GATE(CLK_BUS_MSGBOX, "bus-msgbox", "ahb1", 0x64, 21) CCU_GATE(CLK_BUS_SPINLOCK, "bus-spinlock", "ahb1", 0x64, 22) CCU_GATE(CLK_BUS_CODEC, "bus-codec", "apb1", 0x68, 0) CCU_GATE(CLK_BUS_SPDIF, "bus-spdif", "apb1", 0x68, 1) CCU_GATE(CLK_BUS_PIO, "bus-pio", "apb1", 0x68, 5) CCU_GATE(CLK_BUS_THS, "bus-ths", "apb1", 0x68, 8) CCU_GATE(CLK_BUS_I2S0, "bus-i2s0", "apb1", 0x68, 12) CCU_GATE(CLK_BUS_I2S1, "bus-i2s1", "apb1", 0x68, 13) CCU_GATE(CLK_BUS_I2S2, "bus-i2s2", "apb1", 0x68, 14) CCU_GATE(CLK_BUS_I2C0, "bus-i2c0", "apb2", 0x6c, 0) CCU_GATE(CLK_BUS_I2C1, "bus-i2c1", "apb2", 0x6c, 1) CCU_GATE(CLK_BUS_I2C2, "bus-i2c2", "apb2", 0x6c, 2) CCU_GATE(CLK_BUS_UART0, "bus-uart0", "apb2", 0x6c, 16) CCU_GATE(CLK_BUS_UART1, "bus-uart1", "apb2", 0x6c, 17) CCU_GATE(CLK_BUS_UART2, "bus-uart2", "apb2", 0x6c, 18) CCU_GATE(CLK_BUS_UART3, "bus-uart3", "apb2", 0x6c, 19) CCU_GATE(CLK_BUS_SCR, "bus-scr", "apb2", 0x6c, 20) CCU_GATE(CLK_BUS_EPHY, "bus-ephy", "ahb1", 0x70, 0) CCU_GATE(CLK_BUS_DBG, "bus-dbg", "ahb1", 0x70, 7) CCU_GATE(CLK_USBPHY0, "usb-phy0", "osc24M", 0xcc, 8) CCU_GATE(CLK_USBPHY1, "usb-phy1", "osc24M", 0xcc, 9) CCU_GATE(CLK_USBPHY2, "usb-phy2", "osc24M", 0xcc, 10) CCU_GATE(CLK_USBPHY3, "usb-phy3", "osc24M", 0xcc, 11) CCU_GATE(CLK_USBOHCI0, "usb-ohci0", "osc24M", 0xcc, 16) CCU_GATE(CLK_USBOHCI1, "usb-ohci1", "osc24M", 0xcc, 17) CCU_GATE(CLK_USBOHCI2, "usb-ohci2", "osc24M", 0xcc, 18) CCU_GATE(CLK_USBOHCI3, "usb-ohci3", "osc24M", 0xcc, 19) CCU_GATE(CLK_THS, "ths", "thsdiv", 0x74, 31) CCU_GATE(CLK_I2S0, "i2s0", "i2s0mux", 0xB0, 31) CCU_GATE(CLK_I2S1, "i2s1", "i2s1mux", 0xB4, 31) CCU_GATE(CLK_I2S2, "i2s2", "i2s2mux", 0xB8, 31) CCU_GATE(CLK_DRAM_VE, "dram-ve", "dram", 0x100, 0) CCU_GATE(CLK_DRAM_CSI, "dram-csi", "dram", 0x100, 1) CCU_GATE(CLK_DRAM_DEINTERLACE, "dram-deinterlace", "dram", 0x100, 2) CCU_GATE(CLK_DRAM_TS, "dram-ts", "dram", 0x100, 3) CCU_GATE(CLK_AC_DIG, "ac-dig", "pll_audio", 0x140, 31) CCU_GATE(CLK_AVS, "avs", "osc24M", 0x144, 31) CCU_GATE(CLK_CSI_MISC, "csi-misc", "osc24M", 0x130, 31) CCU_GATE(CLK_HDMI_DDC, "hdmi-ddc", "osc24M", 0x154, 31) }; static const char *pll_cpux_parents[] = {"osc24M"}; NKMP_CLK(pll_cpux_clk, CLK_PLL_CPUX, /* id */ "pll_cpux", pll_cpux_parents, /* name, parents */ 0x00, /* offset */ 8, 5, 0, 0, /* n factor */ 4, 2, 0, 0, /* k factor */ 0, 2, 0, 0, /* m factor */ 16, 2, 0, AW_CLK_FACTOR_POWER_OF_TWO, /* p factor */ 31, /* gate */ 28, 1000, /* lock */ AW_CLK_HAS_GATE | AW_CLK_HAS_LOCK | AW_CLK_SCALE_CHANGE); /* flags */ static const char *pll_audio_parents[] = {"osc24M"}; NKMP_CLK(pll_audio_clk, CLK_PLL_AUDIO, /* id */ "pll_audio", pll_audio_parents, /* name, parents */ 0x08, /* offset */ 8, 7, 0, 0, /* n factor */ 0, 0, 1, AW_CLK_FACTOR_FIXED, /* k factor (fake) */ 0, 5, 0, 0, /* m factor */ 16, 4, 0, 0, /* p factor */ 31, /* gate */ 28, 1000, /* lock */ AW_CLK_HAS_GATE | AW_CLK_HAS_LOCK); /* flags */ static const char *pll_audio_mult_parents[] = {"pll_audio"}; FIXED_CLK(pll_audio_2x_clk, CLK_PLL_AUDIO_2X, /* id */ "pll_audio-2x", /* name */ pll_audio_mult_parents, /* parent */ 0, /* freq */ 2, /* mult */ 1, /* div */ 0); /* flags */ FIXED_CLK(pll_audio_4x_clk, CLK_PLL_AUDIO_4X, /* id */ "pll_audio-4x", /* name */ pll_audio_mult_parents, /* parent */ 0, /* freq */ 4, /* mult */ 1, /* div */ 0); /* flags */ FIXED_CLK(pll_audio_8x_clk, CLK_PLL_AUDIO_8X, /* id */ "pll_audio-8x", /* name */ pll_audio_mult_parents, /* parent */ 0, /* freq */ 8, /* mult */ 1, /* div */ 0); /* flags */ static const char *pll_video_parents[] = {"osc24M"}; NM_CLK_WITH_FRAC(pll_video_clk, CLK_PLL_VIDEO, /* id */ "pll_video", pll_video_parents, /* name, parents */ 0x10, /* offset */ 8, 7, 0, 0, /* n factor */ 0, 4, 0, 0, /* m factor */ 31, 28, 1000, /* gate, lock, lock retries */ AW_CLK_HAS_LOCK, /* flags */ 270000000, 297000000, /* freq0, freq1 */ 24, 25); /* mode sel, freq sel */ static const char *pll_ve_parents[] = {"osc24M"}; NM_CLK_WITH_FRAC(pll_ve_clk, CLK_PLL_VE, /* id */ "pll_ve", pll_ve_parents, /* name, parents */ 0x18, /* offset */ 8, 7, 0, 0, /* n factor */ 0, 4, 0, 0, /* m factor */ 31, 28, 1000, /* gate, lock, lock retries */ AW_CLK_HAS_LOCK, /* flags */ 270000000, 297000000, /* freq0, freq1 */ 24, 25); /* mode sel, freq sel */ static const char *pll_ddr_parents[] = {"osc24M"}; NKMP_CLK_WITH_UPDATE(pll_ddr_clk, CLK_PLL_DDR, /* id */ "pll_ddr", pll_ddr_parents, /* name, parents */ 0x20, /* offset */ 8, 5, 0, 0, /* n factor */ 4, 2, 0, 0, /* k factor */ 0, 2, 0, 0, /* m factor */ 0, 0, 1, AW_CLK_FACTOR_FIXED, /* p factor (fake) */ 31, /* gate */ 28, 1000, /* lock */ 20, /* update */ AW_CLK_HAS_GATE | AW_CLK_HAS_LOCK); /* flags */ static const char *pll_periph0_parents[] = {"osc24M"}; static const char *pll_periph0_2x_parents[] = {"pll_periph0"}; NKMP_CLK(pll_periph0_clk, CLK_PLL_PERIPH0, /* id */ "pll_periph0", pll_periph0_parents, /* name, parents */ 0x28, /* offset */ 8, 5, 0, 0, /* n factor */ 4, 2, 0, 0, /* k factor */ 0, 0, 2, AW_CLK_FACTOR_FIXED, /* m factor (fake) */ 0, 0, 1, AW_CLK_FACTOR_FIXED, /* p factor (fake) */ 31, /* gate */ 28, 1000, /* lock */ AW_CLK_HAS_GATE | AW_CLK_HAS_LOCK); /* flags */ FIXED_CLK(pll_periph0_2x_clk, CLK_PLL_PERIPH0_2X, /* id */ "pll_periph0-2x", /* name */ pll_periph0_2x_parents, /* parent */ 0, /* freq */ 2, /* mult */ 1, /* div */ 0); /* flags */ static const char *pll_gpu_parents[] = {"osc24M"}; NM_CLK_WITH_FRAC(pll_gpu_clk, CLK_PLL_GPU, /* id */ "pll_gpu", pll_gpu_parents, /* name, parents */ 0x38, /* offset */ 8, 7, 0, 0, /* n factor */ 0, 4, 0, 0, /* m factor */ 31, 28, 1000, /* gate, lock, lock retries */ AW_CLK_HAS_LOCK, /* flags */ 270000000, 297000000, /* freq0, freq1 */ 24, 25); /* mode sel, freq sel */ static const char *pll_periph1_parents[] = {"osc24M"}; NKMP_CLK(pll_periph1_clk, CLK_PLL_PERIPH1, /* id */ "pll_periph1", pll_periph1_parents, /* name, parents */ 0x44, /* offset */ 8, 5, 0, 0, /* n factor */ 4, 2, 0, 0, /* k factor */ 0, 0, 2, AW_CLK_FACTOR_FIXED, /* m factor (fake) */ 0, 0, 1, AW_CLK_FACTOR_FIXED, /* p factor (fake) */ 31, /* gate */ 28, 1000, /* lock */ AW_CLK_HAS_GATE | AW_CLK_HAS_LOCK); /* flags */ static const char *pll_de_parents[] = {"osc24M"}; NM_CLK_WITH_FRAC(pll_de_clk, CLK_PLL_DE, /* id */ "pll_de", pll_de_parents, /* name, parents */ 0x48, /* offset */ 8, 7, 0, 0, /* n factor */ 0, 4, 0, 0, /* m factor */ 31, 28, 1000, /* gate, lock, lock retries */ AW_CLK_HAS_LOCK, /* flags */ 270000000, 297000000, /* freq0, freq1 */ 24, 25); /* mode sel, freq sel */ static const char *cpux_parents[] = {"osc32k", "osc24M", "pll_cpux", "pll_cpux"}; MUX_CLK(cpux_clk, CLK_CPUX, /* id */ "cpux", cpux_parents, /* name, parents */ 0x50, 16, 2); /* offset, shift, width */ static const char *axi_parents[] = {"cpux"}; DIV_CLK(axi_clk, CLK_AXI, /* id */ "axi", axi_parents, /* name, parents */ 0x50, /* offset */ 0, 2, /* shift, width */ 0, NULL); /* flags, div table */ static const char *ahb1_parents[] = {"osc32k", "osc24M", "axi", "pll_periph0"}; PREDIV_CLK(ahb1_clk, CLK_AHB1, /* id */ "ahb1", ahb1_parents, /* name, parents */ 0x54, /* offset */ 12, 2, /* mux */ 4, 2, 0, AW_CLK_FACTOR_POWER_OF_TWO, /* div */ 6, 2, 0, AW_CLK_FACTOR_HAS_COND, /* prediv */ 12, 2, 3); /* prediv condition */ static const char *apb1_parents[] = {"ahb1"}; static struct clk_div_table apb1_div_table[] = { { .value = 0, .divider = 2, }, { .value = 1, .divider = 2, }, { .value = 2, .divider = 4, }, { .value = 3, .divider = 8, }, { }, }; DIV_CLK(apb1_clk, CLK_APB1, /* id */ "apb1", apb1_parents, /* name, parents */ 0x54, /* offset */ 8, 2, /* shift, width */ CLK_DIV_WITH_TABLE, /* flags */ apb1_div_table); /* div table */ static const char *apb2_parents[] = {"osc32k", "osc24M", "pll_periph0", "pll_periph0"}; NM_CLK(apb2_clk, CLK_APB2, /* id */ "apb2", apb2_parents, /* name, parents */ 0x58, /* offset */ 16, 2, 0, AW_CLK_FACTOR_POWER_OF_TWO, /* n factor */ 0, 5, 0, 0, /* m factor */ 24, 2, /* mux */ 0, /* gate */ AW_CLK_HAS_MUX); static const char *ahb2_parents[] = {"ahb1", "pll_periph0"}; PREDIV_CLK(ahb2_clk, CLK_AHB2, /* id */ "ahb2", ahb2_parents, /* name, parents */ 0x5c, /* offset */ 0, 2, /* mux */ 0, 0, 1, AW_CLK_FACTOR_FIXED, /* div */ 0, 0, 2, AW_CLK_FACTOR_HAS_COND | AW_CLK_FACTOR_FIXED, /* prediv */ 0, 2, 1); /* prediv condition */ static const char *ths_parents[] = {"osc24M"}; static struct clk_div_table ths_div_table[] = { { .value = 0, .divider = 1, }, { .value = 1, .divider = 2, }, { .value = 2, .divider = 4, }, { .value = 3, .divider = 6, }, { }, }; DIV_CLK(thsdiv_clk, 0, /* id */ "thsdiv", ths_parents, /* name, parents */ 0x74, /* offset */ 0, 2, /* shift, width */ CLK_DIV_WITH_TABLE, /* flags */ ths_div_table); /* div table */ static const char *mod_parents[] = {"osc24M", "pll_periph0", "pll_periph1"}; NM_CLK(nand_clk, CLK_NAND, "nand", mod_parents, /* id, name, parents */ 0x80, /* offset */ 16, 2, 0, AW_CLK_FACTOR_POWER_OF_TWO, /* n factor */ 0, 4, 0, 0, /* m factor */ 24, 2, /* mux */ 31, /* gate */ AW_CLK_HAS_GATE | AW_CLK_HAS_MUX); /* flags */ NM_CLK(mmc0_clk, CLK_MMC0, "mmc0", mod_parents, /* id, name, parents */ 0x88, /* offset */ 16, 2, 0, AW_CLK_FACTOR_POWER_OF_TWO, /* n factor */ 0, 4, 0, 0, /* m factor */ 24, 2, /* mux */ 31, /* gate */ AW_CLK_HAS_GATE | AW_CLK_HAS_MUX | AW_CLK_REPARENT); /* flags */ NM_CLK(mmc1_clk, CLK_MMC1, "mmc1", mod_parents, /* id, name, parents */ 0x8c, /* offset */ 16, 2, 0, AW_CLK_FACTOR_POWER_OF_TWO, /* n factor */ 0, 4, 0, 0, /* m factor */ 24, 2, /* mux */ 31, /* gate */ AW_CLK_HAS_GATE | AW_CLK_HAS_MUX | AW_CLK_REPARENT); /* flags */ NM_CLK(mmc2_clk, CLK_MMC2, "mmc2", mod_parents, /* id, name, parents */ 0x90, /* offset */ 16, 2, 0, AW_CLK_FACTOR_POWER_OF_TWO, /* n factor */ 0, 4, 0, 0, /* m factor */ 24, 2, /* mux */ 31, /* gate */ AW_CLK_HAS_GATE | AW_CLK_HAS_MUX | AW_CLK_REPARENT); /* flags */ static const char *ts_parents[] = {"osc24M", "pll_periph0"}; NM_CLK(ts_clk, CLK_TS, "ts", ts_parents, /* id, name, parents */ 0x98, /* offset */ 16, 2, 0, AW_CLK_FACTOR_POWER_OF_TWO, /* n factor */ 0, 4, 0, 0, /* m factor */ 24, 2, /* mux */ 31, /* gate */ AW_CLK_HAS_GATE | AW_CLK_HAS_MUX); /* flags */ NM_CLK(ce_clk, CLK_CE, "ce", mod_parents, /* id, name, parents */ 0x9C, /* offset */ 16, 2, 0, AW_CLK_FACTOR_POWER_OF_TWO, /* n factor */ 0, 4, 0, 0, /* m factor */ 24, 2, /* mux */ 31, /* gate */ AW_CLK_HAS_GATE | AW_CLK_HAS_MUX); /* flags */ NM_CLK(spi0_clk, CLK_SPI0, "spi0", mod_parents, /* id, name, parents */ 0xA0, /* offset */ 16, 2, 0, AW_CLK_FACTOR_POWER_OF_TWO, /* n factor */ 0, 4, 0, 0, /* m factor */ 24, 2, /* mux */ 31, /* gate */ AW_CLK_HAS_GATE | AW_CLK_HAS_MUX | AW_CLK_REPARENT); /* flags */ NM_CLK(spi1_clk, CLK_SPI1, "spi1", mod_parents, /* id, name, parents */ 0xA4, /* offset */ 16, 2, 0, AW_CLK_FACTOR_POWER_OF_TWO, /* n factor */ 0, 4, 0, 0, /* m factor */ 24, 2, /* mux */ 31, /* gate */ AW_CLK_HAS_GATE | AW_CLK_HAS_MUX | AW_CLK_REPARENT); /* flags */ static const char *i2s_parents[] = {"pll_audio-8x", "pll_audio-4x", "pll_audio-2x", "pll_audio"}; MUX_CLK(i2s0mux_clk, 0, "i2s0mux", i2s_parents, /* id, name, parents */ 0xb0, 16, 2); /* offset, mux shift, mux width */ MUX_CLK(i2s1mux_clk, 0, "i2s1mux", i2s_parents, /* id, name, parents */ 0xb4, 16, 2); /* offset, mux shift, mux width */ MUX_CLK(i2s2mux_clk, 0, "i2s2mux", i2s_parents, /* id, name, parents */ 0xb8, 16, 2); /* offset, mux shift, mux width */ static const char *spdif_parents[] = {"pll_audio"}; NM_CLK(spdif_clk, CLK_SPDIF, "spdif", spdif_parents, /* id, name, parents */ 0xC0, /* offset */ 0, 0, 1, AW_CLK_FACTOR_FIXED, /* n factor (fake); */ 0, 4, 0, 0, /* m factor */ 0, 0, /* mux */ 31, /* gate */ AW_CLK_HAS_GATE); /* flags */ static const char *dram_parents[] = {"pll_ddr", "pll_periph0-2x"}; NM_CLK(dram_clk, CLK_DRAM, "dram", dram_parents, /* id, name, parents */ 0xF4, /* offset */ 0, 0, 1, AW_CLK_FACTOR_FIXED, /* n factor (fake) */ 0, 4, 0, 0, /* m factor */ 20, 2, /* mux */ 0, /* gate */ AW_CLK_HAS_MUX); /* flags */ static const char *de_parents[] = {"pll_periph0-2x", "pll_de"}; NM_CLK(de_clk, CLK_DE, "de", de_parents, /* id, name, parents */ 0x104, /* offset */ 0, 0, 1, AW_CLK_FACTOR_FIXED, /* n factor (fake) */ 0, 4, 0, 0, /* m factor */ 24, 2, /* mux */ 31, /* gate */ AW_CLK_HAS_MUX | AW_CLK_HAS_GATE); /* flags */ static const char *tcon0_parents[] = {"pll_video"}; NM_CLK(tcon0_clk, CLK_TCON0, "tcon0", tcon0_parents, /* id, name, parents */ 0x118, /* offset */ 0, 0, 1, AW_CLK_FACTOR_FIXED, /* n factor (fake) */ 0, 4, 0, 0, /* m factor */ 24, 2, /* mux */ 31, /* gate */ AW_CLK_HAS_MUX | AW_CLK_HAS_GATE); /* flags */ static const char *tve_parents[] = {"pll_de", "pll_periph1"}; NM_CLK(tve_clk, CLK_TVE, "tve", tve_parents, /* id, name, parents */ 0x120, /* offset */ 0, 0, 1, AW_CLK_FACTOR_FIXED, /* n factor (fake) */ 0, 4, 0, 0, /* m factor */ 24, 2, /* mux */ 31, /* gate */ AW_CLK_HAS_MUX | AW_CLK_HAS_GATE); /* flags */ static const char *deinterlace_parents[] = {"pll_periph0", "pll_periph1"}; NM_CLK(deinterlace_clk, CLK_DEINTERLACE, "deinterlace", deinterlace_parents, /* id, name, parents */ 0x124, /* offset */ 0, 0, 1, AW_CLK_FACTOR_FIXED, /* n factor (fake) */ 0, 4, 0, 0, /* m factor */ 24, 2, /* mux */ 31, /* gate */ AW_CLK_HAS_MUX | AW_CLK_HAS_GATE); /* flags */ static const char *csi_sclk_parents[] = {"pll_periph0", "pll_periph1"}; NM_CLK(csi_sclk_clk, CLK_CSI_SCLK, "csi-sclk", csi_sclk_parents, /* id, name, parents */ 0x134, /* offset */ 0, 0, 1, AW_CLK_FACTOR_FIXED, /* n factor (fake) */ 16, 4, 0, 0, /* m factor */ 24, 2, /* mux */ 31, /* gate */ AW_CLK_HAS_MUX | AW_CLK_HAS_GATE); /* flags */ static const char *csi_mclk_parents[] = {"osc24M", "pll_video", "pll_periph1"}; NM_CLK(csi_mclk_clk, CLK_CSI_MCLK, "csi-mclk", csi_mclk_parents, /* id, name, parents */ 0x134, /* offset */ 0, 0, 1, AW_CLK_FACTOR_FIXED, /* n factor (fake) */ 0, 4, 0, 0, /* m factor */ 8, 2, /* mux */ 15, /* gate */ AW_CLK_HAS_MUX | AW_CLK_HAS_GATE); /* flags */ static const char *ve_parents[] = {"pll_ve"}; NM_CLK(ve_clk, CLK_VE, "ve", ve_parents, /* id, name, parents */ 0x13C, /* offset */ 16, 3, 0, 0, /* n factor */ 0, 0, 1, AW_CLK_FACTOR_FIXED, /* m factor (fake) */ 0, 0, /* mux */ 31, /* gate */ AW_CLK_HAS_GATE); /* flags */ static const char *hdmi_parents[] = {"pll_video"}; NM_CLK(hdmi_clk, CLK_HDMI, "hdmi", hdmi_parents, /* id, name, parents */ 0x150, /* offset */ 0, 0, 1, AW_CLK_FACTOR_FIXED, /* n factor (fake) */ 0, 4, 0, 0, /* m factor */ 24, 2, /* mux */ 31, /* gate */ AW_CLK_HAS_MUX | AW_CLK_HAS_GATE); /* flags */ static const char *mbus_parents[] = {"osc24M", "pll_periph0-2x", "pll_ddr"}; NM_CLK(mbus_clk, CLK_MBUS, "mbus", mbus_parents, /* id, name, parents */ 0x15C, /* offset */ 0, 0, 1, AW_CLK_FACTOR_FIXED, /* n factor (fake) */ 0, 3, 0, 0, /* m factor */ 24, 2, /* mux */ 31, /* gate */ AW_CLK_HAS_MUX | AW_CLK_HAS_GATE); /* flags */ static const char *gpu_parents[] = {"pll_gpu"}; NM_CLK(gpu_clk, CLK_GPU, "gpu", gpu_parents, /* id, name, parents */ 0x1A0, /* offset */ 0, 2, 0, 0, /* n factor */ 0, 0, 1, AW_CLK_FACTOR_FIXED, /* m factor (fake) */ 0, 0, /* mux */ 31, /* gate */ AW_CLK_HAS_GATE); /* flags */ static struct aw_clk_nkmp_def *nkmp_clks[] = { &pll_cpux_clk, &pll_audio_clk, &pll_periph0_clk, &pll_periph1_clk, &pll_ddr_clk, }; static struct aw_clk_nm_def *nm_clks[] = { &pll_video_clk, &pll_ve_clk, &pll_gpu_clk, &pll_de_clk, &apb2_clk, &nand_clk, &mmc0_clk, &mmc1_clk, &mmc2_clk, &ts_clk, &ce_clk, &spi0_clk, &spi1_clk, &spdif_clk, &dram_clk, &de_clk, &tcon0_clk, &tve_clk, &deinterlace_clk, &csi_sclk_clk, &csi_mclk_clk, &ve_clk, &hdmi_clk, &mbus_clk, &gpu_clk, }; static struct aw_clk_prediv_mux_def *prediv_mux_clks[] = { &ahb1_clk, &ahb2_clk, }; static struct clk_mux_def *mux_clks[] = { &cpux_clk, &i2s0mux_clk, &i2s1mux_clk, &i2s2mux_clk, }; static struct clk_div_def *div_clks[] = { &axi_clk, &apb1_clk, &thsdiv_clk, }; static struct clk_fixed_def *fixed_factor_clks[] = { &pll_periph0_2x_clk, &pll_audio_2x_clk, &pll_audio_4x_clk, &pll_audio_8x_clk, }; static struct aw_clk_init init_clks[] = { {"ahb1", "pll_periph0", 0, false}, {"ahb2", "pll_periph0", 0, false}, {"dram", "pll_ddr", 0, false}, }; void ccu_h3_register_clocks(struct aw_ccung_softc *sc) { int i; sc->resets = h3_ccu_resets; sc->nresets = nitems(h3_ccu_resets); sc->gates = h3_ccu_gates; sc->ngates = nitems(h3_ccu_gates); sc->clk_init = init_clks; sc->n_clk_init = nitems(init_clks); for (i = 0; i < nitems(nkmp_clks); i++) aw_clk_nkmp_register(sc->clkdom, nkmp_clks[i]); for (i = 0; i < nitems(nm_clks); i++) aw_clk_nm_register(sc->clkdom, nm_clks[i]); for (i = 0; i < nitems(prediv_mux_clks); i++) aw_clk_prediv_mux_register(sc->clkdom, prediv_mux_clks[i]); for (i = 0; i < nitems(mux_clks); i++) clknode_mux_register(sc->clkdom, mux_clks[i]); for (i = 0; i < nitems(div_clks); i++) clknode_div_register(sc->clkdom, div_clks[i]); for (i = 0; i < nitems(fixed_factor_clks); i++) clknode_fixed_register(sc->clkdom, fixed_factor_clks[i]); } Index: head/sys/arm/allwinner/clkng/ccu_sun8i_r.c =================================================================== --- head/sys/arm/allwinner/clkng/ccu_sun8i_r.c (revision 326578) +++ head/sys/arm/allwinner/clkng/ccu_sun8i_r.c (revision 326579) @@ -1,146 +1,150 @@ /*- * Copyright (c) 2017 Emmanuel Vadot * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. * * $FreeBSD$ */ #include __FBSDID("$FreeBSD$"); #include #include #include +#if defined(__aarch64__) +#include "opt_soc.h" +#endif + #include #include #include #include #include #include #include #include #include #include #include /* Non-exported clocks */ #define CLK_AHB0 1 #define CLK_APB0 2 static struct aw_ccung_reset ccu_sun8i_r_resets[] = { CCU_RESET(RST_APB0_IR, 0xb0, 1) CCU_RESET(RST_APB0_TIMER, 0xb0, 2) CCU_RESET(RST_APB0_RSB, 0xb0, 4) CCU_RESET(RST_APB0_UART, 0xb0, 6) }; static struct aw_ccung_gate ccu_sun8i_r_gates[] = { CCU_GATE(CLK_APB0_PIO, "apb0-pio", "apb0", 0x28, 0) CCU_GATE(CLK_APB0_IR, "apb0-ir", "apb0", 0x28, 1) CCU_GATE(CLK_APB0_TIMER, "apb0-timer", "apb0", 0x28, 2) CCU_GATE(CLK_APB0_RSB, "apb0-rsb", "apb0", 0x28, 3) CCU_GATE(CLK_APB0_UART, "apb0-uart", "apb0", 0x28, 4) CCU_GATE(CLK_APB0_I2C, "apb0-i2c", "apb0", 0x28, 6) CCU_GATE(CLK_APB0_TWD, "apb0-twd", "apb0", 0x28, 7) }; static const char *ar100_parents[] = {"osc32k", "osc24M", "pll_periph0", "iosc"}; static const char *a83t_ar100_parents[] = {"osc16M-d512", "osc24M", "pll_periph", "osc16M"}; PREDIV_CLK(ar100_clk, CLK_AR100, /* id */ "ar100", ar100_parents, /* name, parents */ 0x00, /* offset */ 16, 2, /* mux */ 4, 2, 0, AW_CLK_FACTOR_POWER_OF_TWO, /* div */ 8, 5, 0, AW_CLK_FACTOR_HAS_COND, /* prediv */ 16, 2, 2); /* prediv condition */ PREDIV_CLK(a83t_ar100_clk, CLK_AR100, /* id */ "ar100", a83t_ar100_parents, /* name, parents */ 0x00, /* offset */ 16, 2, /* mux */ 4, 2, 0, AW_CLK_FACTOR_POWER_OF_TWO, /* div */ 8, 5, 0, AW_CLK_FACTOR_HAS_COND, /* prediv */ 16, 2, 2); /* prediv condition */ static const char *ahb0_parents[] = {"ar100"}; FIXED_CLK(ahb0_clk, CLK_AHB0, /* id */ "ahb0", /* name */ ahb0_parents, /* parent */ 0, /* freq */ 1, /* mult */ 1, /* div */ 0); /* flags */ static const char *apb0_parents[] = {"ahb0"}; DIV_CLK(apb0_clk, CLK_APB0, /* id */ "apb0", apb0_parents, /* name, parents */ 0x0c, /* offset */ 0, 2, /* shift, width */ 0, NULL); /* flags, div table */ static struct aw_clk_prediv_mux_def *r_ccu_prediv_mux_clks[] = { &ar100_clk, }; static struct aw_clk_prediv_mux_def *a83t_r_ccu_prediv_mux_clks[] = { &a83t_ar100_clk, }; static struct clk_div_def *div_clks[] = { &apb0_clk, }; static struct clk_fixed_def *fixed_factor_clks[] = { &ahb0_clk, }; void ccu_sun8i_r_register_clocks(struct aw_ccung_softc *sc) { int i; struct aw_clk_prediv_mux_def **prediv_mux_clks; sc->resets = ccu_sun8i_r_resets; sc->nresets = nitems(ccu_sun8i_r_resets); sc->gates = ccu_sun8i_r_gates; sc->ngates = nitems(ccu_sun8i_r_gates); /* a83t names the parents differently than the others */ if (sc->type == A83T_R_CCU) prediv_mux_clks = a83t_r_ccu_prediv_mux_clks; else prediv_mux_clks = r_ccu_prediv_mux_clks; for (i = 0; i < nitems(prediv_mux_clks); i++) aw_clk_prediv_mux_register(sc->clkdom, prediv_mux_clks[i]); for (i = 0; i < nitems(div_clks); i++) clknode_div_register(sc->clkdom, div_clks[i]); for (i = 0; i < nitems(fixed_factor_clks); i++) clknode_fixed_register(sc->clkdom, fixed_factor_clks[i]); } Index: head/sys/arm/allwinner/h3/h3_padconf.c =================================================================== --- head/sys/arm/allwinner/h3/h3_padconf.c (revision 326578) +++ head/sys/arm/allwinner/h3/h3_padconf.c (revision 326579) @@ -1,147 +1,151 @@ /*- - * Copyright (c) 2016 Emmanuel Vadot + * Copyright (c) 2016-2017 Emmanuel Vadot * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. * */ #include __FBSDID("$FreeBSD$"); #include #include #include #include +#if defined(__aarch64__) +#include "opt_soc.h" +#endif + #include -#ifdef SOC_ALLWINNER_H3 +#if defined(SOC_ALLWINNER_H3) || defined(SOC_ALLWINNER_H5) const static struct allwinner_pins h3_pins[] = { {"PA0", 0, 0, {"gpio_in", "gpio_out", "uart2", "jtag", NULL, NULL, "pa_eint0", NULL}, 6, 0}, {"PA1", 0, 1, {"gpio_in", "gpio_out", "uart2", "jtag", NULL, NULL, "pa_eint1", NULL}, 6, 1}, {"PA2", 0, 2, {"gpio_in", "gpio_out", "uart2", "jtag", NULL, NULL, "pa_eint2", NULL}, 6, 2}, {"PA3", 0, 3, {"gpio_in", "gpio_out", "uart2", "jtag", NULL, NULL, "pa_eint3", NULL}, 6, 3}, {"PA4", 0, 4, {"gpio_in", "gpio_out", "uart0", NULL, NULL, NULL, "pa_eint4", NULL}, 6, 4}, {"PA5", 0, 5, {"gpio_in", "gpio_out", "uart0", "pwm0", NULL, NULL, "pa_eint5", NULL}, 6, 5}, {"PA6", 0, 6, {"gpio_in", "gpio_out", "sim", NULL, NULL, NULL, "pa_eint6", NULL}, 6, 6}, {"PA7", 0, 7, {"gpio_in", "gpio_out", "sim", NULL, NULL, NULL, "pa_eint7", NULL}, 6, 7}, {"PA8", 0, 8, {"gpio_in", "gpio_out", "sim", NULL, NULL, NULL, "pa_eint8", NULL}, 6, 8}, {"PA9", 0, 9, {"gpio_in", "gpio_out", "sim", NULL, NULL, NULL, "pa_eint9", NULL}, 6, 9}, {"PA10", 0, 10, {"gpio_in", "gpio_out", "sim", NULL, NULL, NULL, "pa_eint10", NULL}, 6, 10}, {"PA11", 0, 11, {"gpio_in", "gpio_out", "i2c0", "di", NULL, NULL, "pa_eint11", NULL}, 6, 11}, {"PA12", 0, 12, {"gpio_in", "gpio_out", "i2c0", "di", NULL, NULL, "pa_eint12", NULL}, 6, 12}, {"PA13", 0, 13, {"gpio_in", "gpio_out", "spi1", "uart3", NULL, NULL, "pa_eint13", NULL}, 6, 13}, {"PA14", 0, 14, {"gpio_in", "gpio_out", "spi1", "uart3", NULL, NULL, "pa_eint14", NULL}, 6, 14}, {"PA15", 0, 15, {"gpio_in", "gpio_out", "spi1", "uart3", NULL, NULL, "pa_eint15", NULL}, 6, 15}, {"PA16", 0, 16, {"gpio_in", "gpio_out", "spi1", "uart3", NULL, NULL, "pa_eint16", NULL}, 6, 16}, {"PA17", 0, 17, {"gpio_in", "gpio_out", "spdif", NULL, NULL, NULL, "pa_eint17", NULL}, 6, 17}, {"PA18", 0, 18, {"gpio_in", "gpio_out", "i2s0", "i2c1", NULL, NULL, "pa_eint18", NULL}, 6, 18}, {"PA19", 0, 19, {"gpio_in", "gpio_out", "i2s0", "i2c1", NULL, NULL, "pa_eint19", NULL}, 6, 19}, {"PA20", 0, 20, {"gpio_in", "gpio_out", "i2s0", "sim", NULL, NULL, "pa_eint20", NULL}, 6, 20}, {"PA21", 0, 21, {"gpio_in", "gpio_out", "i2s0", "sim", NULL, NULL, "pa_eint21", NULL}, 6, 21}, {"PC0", 2, 0, {"gpio_in", "gpio_out", "nand", "spi0", NULL, NULL, NULL, NULL}}, {"PC1", 2, 1, {"gpio_in", "gpio_out", "nand", "spi0", NULL, NULL, NULL, NULL}}, {"PC2", 2, 2, {"gpio_in", "gpio_out", "nand", "spi0", NULL, NULL, NULL, NULL}}, {"PC3", 2, 3, {"gpio_in", "gpio_out", "nand", "spi0", NULL, NULL, NULL, NULL}}, {"PC4", 2, 4, {"gpio_in", "gpio_out", "nand", NULL, NULL, NULL, NULL, NULL}}, {"PC5", 2, 5, {"gpio_in", "gpio_out", "nand", "mmc2", NULL, NULL, NULL, NULL}}, {"PC6", 2, 6, {"gpio_in", "gpio_out", "nand", "mmc2", NULL, NULL, NULL, NULL}}, {"PC7", 2, 7, {"gpio_in", "gpio_out", "nand", NULL, NULL, NULL, NULL, NULL}}, {"PC8", 2, 8, {"gpio_in", "gpio_out", "nand", "mmc2", NULL, NULL, NULL, NULL}}, {"PC9", 2, 9, {"gpio_in", "gpio_out", "nand", "mmc2", NULL, NULL, NULL, NULL}}, {"PC10", 2, 10, {"gpio_in", "gpio_out", "nand", "mmc2", NULL, NULL, NULL, NULL}}, {"PC11", 2, 11, {"gpio_in", "gpio_out", "nand", "mmc2", NULL, NULL, NULL, NULL}}, {"PC12", 2, 12, {"gpio_in", "gpio_out", "nand", "mmc2", NULL, NULL, NULL, NULL}}, {"PC13", 2, 13, {"gpio_in", "gpio_out", "nand", "mmc2", NULL, NULL, NULL, NULL}}, {"PC14", 2, 14, {"gpio_in", "gpio_out", "nand", "mmc2", NULL, NULL, NULL, NULL}}, {"PC15", 2, 15, {"gpio_in", "gpio_out", "nand", "mmc2", NULL, NULL, NULL, NULL}}, {"PC16", 2, 16, {"gpio_in", "gpio_out", "nand", "mmc2", NULL, NULL, NULL, NULL}}, {"PD0", 3, 0, {"gpio_in", "gpio_out", "emac", NULL, NULL, NULL, NULL, NULL}}, {"PD1", 3, 1, {"gpio_in", "gpio_out", "emac", NULL, NULL, NULL, NULL, NULL}}, {"PD2", 3, 2, {"gpio_in", "gpio_out", "emac", NULL, NULL, NULL, NULL, NULL}}, {"PD3", 3, 3, {"gpio_in", "gpio_out", "emac", NULL, NULL, NULL, NULL, NULL}}, {"PD4", 3, 4, {"gpio_in", "gpio_out", "emac", NULL, NULL, NULL, NULL, NULL}}, {"PD5", 3, 5, {"gpio_in", "gpio_out", "emac", NULL, NULL, NULL, NULL, NULL}}, {"PD6", 3, 6, {"gpio_in", "gpio_out", "emac", NULL, NULL, NULL, NULL, NULL}}, {"PD7", 3, 7, {"gpio_in", "gpio_out", "emac", NULL, NULL, NULL, NULL, NULL}}, {"PD8", 3, 8, {"gpio_in", "gpio_out", "emac", NULL, NULL, NULL, NULL, NULL}}, {"PD9", 3, 9, {"gpio_in", "gpio_out", "emac", NULL, NULL, NULL, NULL, NULL}}, {"PD10", 3, 10, {"gpio_in", "gpio_out", "emac", NULL, NULL, NULL, NULL, NULL}}, {"PD11", 3, 11, {"gpio_in", "gpio_out", "emac", NULL, NULL, NULL, NULL, NULL}}, {"PD12", 3, 12, {"gpio_in", "gpio_out", "emac", NULL, NULL, NULL, NULL, NULL}}, {"PD13", 3, 13, {"gpio_in", "gpio_out", "emac", NULL, NULL, NULL, NULL, NULL}}, {"PD14", 3, 14, {"gpio_in", "gpio_out", "emac", NULL, NULL, NULL, NULL, NULL}}, {"PD15", 3, 15, {"gpio_in", "gpio_out", "emac", NULL, NULL, NULL, NULL, NULL}}, {"PD16", 3, 16, {"gpio_in", "gpio_out", "emac", NULL, NULL, NULL, NULL, NULL}}, {"PD17", 3, 17, {"gpio_in", "gpio_out", "emac", NULL, NULL, NULL, NULL, NULL}}, {"PE0", 4, 0, {"gpio_in", "gpio_out", "csi", "ts", NULL, NULL, NULL, NULL}}, {"PE1", 4, 1, {"gpio_in", "gpio_out", "csi", "ts", NULL, NULL, NULL, NULL}}, {"PE2", 4, 2, {"gpio_in", "gpio_out", "csi", "ts", NULL, NULL, NULL, NULL}}, {"PE3", 4, 3, {"gpio_in", "gpio_out", "csi", "ts", NULL, NULL, NULL, NULL}}, {"PE4", 4, 4, {"gpio_in", "gpio_out", "csi", "ts", NULL, NULL, NULL, NULL}}, {"PE5", 4, 5, {"gpio_in", "gpio_out", "csi", "ts", NULL, NULL, NULL, NULL}}, {"PE6", 4, 6, {"gpio_in", "gpio_out", "csi", "ts", NULL, NULL, NULL, NULL}}, {"PE7", 4, 7, {"gpio_in", "gpio_out", "csi", "ts", NULL, NULL, NULL, NULL}}, {"PE8", 4, 8, {"gpio_in", "gpio_out", "csi", "ts", NULL, NULL, NULL, NULL}}, {"PE9", 4, 9, {"gpio_in", "gpio_out", "csi", "ts", NULL, NULL, NULL, NULL}}, {"PE10", 4, 10, {"gpio_in", "gpio_out", "csi", "ts", NULL, NULL, NULL, NULL}}, {"PE11", 4, 11, {"gpio_in", "gpio_out", "csi", "ts", NULL, NULL, NULL, NULL}}, {"PE12", 4, 12, {"gpio_in", "gpio_out", "csi", "i2c2", NULL, NULL, NULL, NULL}}, {"PE13", 4, 13, {"gpio_in", "gpio_out", "csi", "i2c2", NULL, NULL, NULL, NULL}}, {"PE14", 4, 14, {"gpio_in", "gpio_out", NULL, NULL, NULL, NULL, NULL, NULL}}, {"PE15", 4, 15, {"gpio_in", "gpio_out", NULL, NULL, NULL, NULL, NULL, NULL}}, {"PF0", 5, 0, {"gpio_in", "gpio_out", "mmc0", "jtag", NULL, NULL, NULL, NULL}}, {"PF1", 5, 1, {"gpio_in", "gpio_out", "mmc0", "jtag", NULL, NULL, NULL, NULL}}, {"PF2", 5, 2, {"gpio_in", "gpio_out", "mmc0", "uart0", NULL, NULL, NULL, NULL}}, {"PF3", 5, 3, {"gpio_in", "gpio_out", "mmc0", "jtag", NULL, NULL, NULL, NULL}}, {"PF4", 5, 4, {"gpio_in", "gpio_out", "mmc0", "uart0", NULL, NULL, NULL, NULL}}, {"PF5", 5, 5, {"gpio_in", "gpio_out", "mmc0", "jtag", NULL, NULL, NULL, NULL}}, {"PF6", 5, 6, {"gpio_in", "gpio_out", NULL, NULL, NULL, NULL, NULL, NULL}}, {"PG0", 6, 0, {"gpio_in", "gpio_out", "mmc1", NULL, NULL, NULL, "pg_eint0", NULL}, 6, 0}, {"PG1", 6, 1, {"gpio_in", "gpio_out", "mmc1", NULL, NULL, NULL, "pg_eint1", NULL}, 6, 1}, {"PG2", 6, 2, {"gpio_in", "gpio_out", "mmc1", NULL, NULL, NULL, "pg_eint2", NULL}, 6, 2}, {"PG3", 6, 3, {"gpio_in", "gpio_out", "mmc1", NULL, NULL, NULL, "pg_eint3", NULL}, 6, 3}, {"PG4", 6, 4, {"gpio_in", "gpio_out", "mmc1", NULL, NULL, NULL, "pg_eint4", NULL}, 6, 4}, {"PG5", 6, 5, {"gpio_in", "gpio_out", "mmc1", NULL, NULL, NULL, "pg_eint5", NULL}, 6, 5}, {"PG6", 6, 6, {"gpio_in", "gpio_out", "uart1", NULL, NULL, NULL, "pg_eint6", NULL}, 6, 6}, {"PG7", 6, 7, {"gpio_in", "gpio_out", "uart1", NULL, NULL, NULL, "pg_eint7", NULL}, 6, 7}, {"PG8", 6, 8, {"gpio_in", "gpio_out", "uart1", NULL, NULL, NULL, "pg_eint8", NULL}, 6, 8}, {"PG9", 6, 9, {"gpio_in", "gpio_out", "uart1", NULL, NULL, NULL, "pg_eint9", NULL}, 6, 9}, {"PG10", 6, 10, {"gpio_in", "gpio_out", "i2s1", NULL, NULL, NULL, "pg_eint10", NULL}, 6, 10}, {"PG11", 6, 11, {"gpio_in", "gpio_out", "i2s1", NULL, NULL, NULL, "pg_eint11", NULL}, 6, 11}, {"PG12", 6, 12, {"gpio_in", "gpio_out", "i2s1", NULL, NULL, NULL, "pg_eint12", NULL}, 6, 12}, {"PG13", 6, 13, {"gpio_in", "gpio_out", "i2s1", NULL, NULL, NULL, "pg_eint13", NULL}, 6, 13}, }; const struct allwinner_padconf h3_padconf = { .npins = nitems(h3_pins), .pins = h3_pins, }; #endif /* SOC_ALLWINNER_H3 */ Index: head/sys/arm/allwinner/h3/h3_r_padconf.c =================================================================== --- head/sys/arm/allwinner/h3/h3_r_padconf.c (revision 326578) +++ head/sys/arm/allwinner/h3/h3_r_padconf.c (revision 326579) @@ -1,60 +1,64 @@ /*- - * Copyright (c) 2016 Emmanuel Vadot + * Copyright (c) 2016-2017 Emmanuel Vadot * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. * */ #include __FBSDID("$FreeBSD$"); #include #include #include #include +#if defined(__aarch64__) +#include "opt_soc.h" +#endif + #include -#ifdef SOC_ALLWINNER_H3 +#if defined(SOC_ALLWINNER_H3) || defined(SOC_ALLWINNER_H5) const static struct allwinner_pins h3_r_pins[] = { {"PL0", 0, 0, {"gpio_in", "gpio_out", "s_twi", NULL, NULL, NULL, "pl_eint0", NULL}, 6, 0}, {"PL1", 0, 1, {"gpio_in", "gpio_out", "s_twi", NULL, NULL, NULL, "pl_eint1", NULL}, 6, 1}, {"PL2", 0, 2, {"gpio_in", "gpio_out", "s_uart", NULL, NULL, NULL, "pl_eint2", NULL}, 6, 2}, {"PL3", 0, 3, {"gpio_in", "gpio_out", "s_uart", NULL, NULL, NULL, "pl_eint3", NULL}, 6, 3}, {"PL4", 0, 4, {"gpio_in", "gpio_out", "s_jtag", NULL, NULL, NULL, "pl_eint4", NULL}, 6, 4}, {"PL5", 0, 5, {"gpio_in", "gpio_out", "s_jtag", NULL, NULL, NULL, "pl_eint5", NULL}, 6, 5}, {"PL6", 0, 6, {"gpio_in", "gpio_out", "s_jtag", NULL, NULL, NULL, "pl_eint6", NULL}, 6, 6}, {"PL7", 0, 7, {"gpio_in", "gpio_out", "s_jtag", NULL, NULL, NULL, "pl_eint7", NULL}, 6, 7}, {"PL8", 0, 8, {"gpio_in", "gpio_out", NULL, NULL, NULL, NULL, "pl_eint8", NULL}, 6, 8}, {"PL9", 0, 9, {"gpio_in", "gpio_out", NULL, NULL, NULL, NULL, "pl_eint9", NULL}, 6, 9}, {"PL10", 0, 10, {"gpio_in", "gpio_out", "s_pwm", NULL, NULL, NULL, "pl_eint10", NULL}, 6, 10}, {"PL11", 0, 11, {"gpio_in", "gpio_out", "s_cir_rx", NULL, NULL, NULL, "pl_eint11", NULL}, 6, 11}, }; const struct allwinner_padconf h3_r_padconf = { .npins = nitems(h3_r_pins), .pins = h3_r_pins, }; #endif /* SOC_ALLWINNER_H3 */ Index: head/sys/conf/files.arm64 =================================================================== --- head/sys/conf/files.arm64 (revision 326578) +++ head/sys/conf/files.arm64 (revision 326579) @@ -1,230 +1,232 @@ # $FreeBSD$ cloudabi32_vdso.o optional compat_cloudabi32 \ dependency "$S/contrib/cloudabi/cloudabi_vdso_armv6_on_64bit.S" \ compile-with "${CC} -x assembler-with-cpp -m32 -shared -nostdinc -nostdlib -Wl,-T$S/compat/cloudabi/cloudabi_vdso.lds $S/contrib/cloudabi/cloudabi_vdso_armv6_on_64bit.S -o ${.TARGET}" \ no-obj no-implicit-rule \ clean "cloudabi32_vdso.o" # cloudabi32_vdso_blob.o optional compat_cloudabi32 \ dependency "cloudabi32_vdso.o" \ compile-with "${OBJCOPY} --input-target binary --output-target elf64-littleaarch64 --binary-architecture aarch64 cloudabi32_vdso.o ${.TARGET}" \ no-implicit-rule \ clean "cloudabi32_vdso_blob.o" # cloudabi64_vdso.o optional compat_cloudabi64 \ dependency "$S/contrib/cloudabi/cloudabi_vdso_aarch64.S" \ compile-with "${CC} -x assembler-with-cpp -shared -nostdinc -nostdlib -Wl,-T$S/compat/cloudabi/cloudabi_vdso.lds $S/contrib/cloudabi/cloudabi_vdso_aarch64.S -o ${.TARGET}" \ no-obj no-implicit-rule \ clean "cloudabi64_vdso.o" # cloudabi64_vdso_blob.o optional compat_cloudabi64 \ dependency "cloudabi64_vdso.o" \ compile-with "${OBJCOPY} --input-target binary --output-target elf64-littleaarch64 --binary-architecture aarch64 cloudabi64_vdso.o ${.TARGET}" \ no-implicit-rule \ clean "cloudabi64_vdso_blob.o" # arm/allwinner/a10_ehci.c optional ehci aw_ehci fdt arm/allwinner/a10_gpio.c optional gpio aw_gpio fdt arm/allwinner/a10_mmc.c optional mmc aw_mmc fdt arm/allwinner/a64/a64_padconf.c optional soc_allwinner_a64 fdt arm/allwinner/a64/a64_r_padconf.c optional soc_allwinner_a64 fdt +arm/allwinner/h3/h3_padconf.c optional soc_allwinner_h5 fdt +arm/allwinner/h3/h3_r_padconf.c optional soc_allwinner_h5 fdt arm/allwinner/aw_ccu.c optional aw_ccu fdt arm/allwinner/aw_nmi.c optional aw_nmi fdt \ compile-with "${NORMAL_C} -I$S/gnu/dts/include" arm/allwinner/aw_reset.c optional aw_ccu fdt arm/allwinner/aw_rsb.c optional aw_rsb fdt arm/allwinner/aw_rtc.c optional aw_rtc fdt arm/allwinner/aw_sid.c optional aw_sid fdt arm/allwinner/aw_thermal.c optional aw_thermal fdt arm/allwinner/aw_usbphy.c optional ehci aw_usbphy fdt arm/allwinner/aw_wdog.c optional aw_wdog fdt arm/allwinner/axp81x.c optional axp81x fdt arm/allwinner/clk/aw_ahbclk.c optional aw_ccu fdt arm/allwinner/clk/aw_apbclk.c optional aw_ccu fdt arm/allwinner/clk/aw_axiclk.c optional aw_ccu fdt arm/allwinner/clk/aw_cpuclk.c optional aw_ccu fdt arm/allwinner/clk/aw_gate.c optional aw_ccu fdt arm/allwinner/clk/aw_modclk.c optional aw_ccu fdt arm/allwinner/clk/aw_pll.c optional aw_ccu fdt \ compile-with "${NORMAL_C} -I$S/gnu/dts/include" arm/allwinner/clk/aw_thsclk.c optional aw_ccu fdt arm/allwinner/clk/aw_usbclk.c optional aw_ccu fdt arm/allwinner/clkng/aw_ccung.c optional aw_ccu fdt arm/allwinner/clkng/aw_clk_nkmp.c optional aw_ccu fdt arm/allwinner/clkng/aw_clk_nm.c optional aw_ccu fdt arm/allwinner/clkng/aw_clk_prediv_mux.c optional aw_ccu fdt arm/allwinner/clkng/ccu_a64.c optional aw_ccu fdt arm/allwinner/clkng/ccu_h3.c optional aw_ccu fdt arm/allwinner/clkng/ccu_sun8i_r.c optional aw_ccu fdt arm/allwinner/if_awg.c optional awg fdt arm/annapurna/alpine/alpine_ccu.c optional al_ccu fdt arm/annapurna/alpine/alpine_nb_service.c optional al_nb_service fdt arm/annapurna/alpine/alpine_pci.c optional al_pci fdt arm/annapurna/alpine/alpine_pci_msix.c optional al_pci fdt arm/annapurna/alpine/alpine_serdes.c optional al_serdes fdt \ no-depend \ compile-with "${CC} -c -o ${.TARGET} ${CFLAGS} -I$S/contrib/alpine-hal -I$S/contrib/alpine-hal/eth ${PROF} ${.IMPSRC}" arm/arm/generic_timer.c standard arm/arm/gic.c standard arm/arm/gic_fdt.c optional fdt arm/arm/pmu.c standard arm/broadcom/bcm2835/bcm2835_audio.c optional sound vchiq fdt \ compile-with "${NORMAL_C} -DUSE_VCHIQ_ARM -D__VCCOREVER__=0x04000000 -I$S/contrib/vchiq" arm/broadcom/bcm2835/bcm2835_bsc.c optional bcm2835_bsc soc_brcm_bcm2837 fdt arm/broadcom/bcm2835/bcm2835_cpufreq.c optional soc_brcm_bcm2837 fdt arm/broadcom/bcm2835/bcm2835_dma.c optional soc_brcm_bcm2837 fdt arm/broadcom/bcm2835/bcm2835_fbd.c optional vt soc_brcm_bcm2837 fdt arm/broadcom/bcm2835/bcm2835_ft5406.c optional evdev bcm2835_ft5406 soc_brcm_bcm2837 fdt arm/broadcom/bcm2835/bcm2835_gpio.c optional gpio soc_brcm_bcm2837 fdt arm/broadcom/bcm2835/bcm2835_intr.c optional soc_brcm_bcm2837 fdt arm/broadcom/bcm2835/bcm2835_mbox.c optional soc_brcm_bcm2837 fdt arm/broadcom/bcm2835/bcm2835_rng.c optional random soc_brcm_bcm2837 fdt arm/broadcom/bcm2835/bcm2835_sdhci.c optional sdhci soc_brcm_bcm2837 fdt arm/broadcom/bcm2835/bcm2835_spi.c optional bcm2835_spi soc_brcm_bcm2837 fdt arm/broadcom/bcm2835/bcm2835_vcio.c optional soc_brcm_bcm2837 fdt arm/broadcom/bcm2835/bcm2835_wdog.c optional soc_brcm_bcm2837 fdt arm/broadcom/bcm2835/bcm2836.c optional soc_brcm_bcm2837 fdt arm/broadcom/bcm2835/bcm283x_dwc_fdt.c optional dwcotg fdt soc_brcm_bcm2837 arm/mv/armada38x/armada38x_rtc.c optional mv_rtc fdt arm64/acpica/acpi_machdep.c optional acpi arm64/acpica/OsdEnvironment.c optional acpi arm64/acpica/acpi_wakeup.c optional acpi arm64/acpica/pci_cfgreg.c optional acpi pci arm64/arm64/autoconf.c standard arm64/arm64/bus_machdep.c standard arm64/arm64/bus_space_asm.S standard arm64/arm64/busdma_bounce.c standard arm64/arm64/busdma_machdep.c standard arm64/arm64/bzero.S standard arm64/arm64/clock.c standard arm64/arm64/copyinout.S standard arm64/arm64/copystr.c standard arm64/arm64/cpufunc_asm.S standard arm64/arm64/db_disasm.c optional ddb arm64/arm64/db_interface.c optional ddb arm64/arm64/db_trace.c optional ddb arm64/arm64/debug_monitor.c optional ddb arm64/arm64/disassem.c optional ddb arm64/arm64/dump_machdep.c standard arm64/arm64/efirt_machdep.c optional efirt arm64/arm64/elf32_machdep.c optional compat_freebsd32 arm64/arm64/elf_machdep.c standard arm64/arm64/exception.S standard arm64/arm64/freebsd32_machdep.c optional compat_freebsd32 arm64/arm64/gicv3_its.c optional intrng fdt arm64/arm64/gic_v3.c standard arm64/arm64/gic_v3_fdt.c optional fdt arm64/arm64/identcpu.c standard arm64/arm64/in_cksum.c optional inet | inet6 arm64/arm64/locore.S standard no-obj arm64/arm64/machdep.c standard arm64/arm64/mem.c standard arm64/arm64/memcpy.S standard arm64/arm64/memmove.S standard arm64/arm64/minidump_machdep.c standard arm64/arm64/mp_machdep.c optional smp arm64/arm64/nexus.c standard arm64/arm64/ofw_machdep.c optional fdt arm64/arm64/pmap.c standard arm64/arm64/stack_machdep.c optional ddb | stack arm64/arm64/support.S standard arm64/arm64/swtch.S standard arm64/arm64/sys_machdep.c standard arm64/arm64/trap.c standard arm64/arm64/uio_machdep.c standard arm64/arm64/uma_machdep.c standard arm64/arm64/undefined.c standard arm64/arm64/unwind.c optional ddb | kdtrace_hooks | stack arm64/arm64/vfp.c standard arm64/arm64/vm_machdep.c standard arm64/cavium/thunder_pcie_fdt.c optional soc_cavm_thunderx pci fdt arm64/cavium/thunder_pcie_pem.c optional soc_cavm_thunderx pci arm64/cavium/thunder_pcie_pem_fdt.c optional soc_cavm_thunderx pci fdt arm64/cavium/thunder_pcie_common.c optional soc_cavm_thunderx pci arm64/cloudabi32/cloudabi32_sysvec.c optional compat_cloudabi32 arm64/cloudabi64/cloudabi64_sysvec.c optional compat_cloudabi64 contrib/vchiq/interface/compat/vchi_bsd.c optional vchiq soc_brcm_bcm2837 \ compile-with "${NORMAL_C} -DUSE_VCHIQ_ARM -D__VCCOREVER__=0x04000000 -I$S/contrib/vchiq" contrib/vchiq/interface/vchiq_arm/vchiq_2835_arm.c optional vchiq soc_brcm_bcm2837 \ compile-with "${NORMAL_C} -Wno-unused -DUSE_VCHIQ_ARM -D__VCCOREVER__=0x04000000 -I$S/contrib/vchiq" contrib/vchiq/interface/vchiq_arm/vchiq_arm.c optional vchiq soc_brcm_bcm2837 \ compile-with "${NORMAL_C} -Wno-unused -DUSE_VCHIQ_ARM -D__VCCOREVER__=0x04000000 -I$S/contrib/vchiq" contrib/vchiq/interface/vchiq_arm/vchiq_connected.c optional vchiq soc_brcm_bcm2837 \ compile-with "${NORMAL_C} -DUSE_VCHIQ_ARM -D__VCCOREVER__=0x04000000 -I$S/contrib/vchiq" contrib/vchiq/interface/vchiq_arm/vchiq_core.c optional vchiq soc_brcm_bcm2837 \ compile-with "${NORMAL_C} -DUSE_VCHIQ_ARM -D__VCCOREVER__=0x04000000 -I$S/contrib/vchiq" contrib/vchiq/interface/vchiq_arm/vchiq_kern_lib.c optional vchiq soc_brcm_bcm2837 \ compile-with "${NORMAL_C} -DUSE_VCHIQ_ARM -D__VCCOREVER__=0x04000000 -I$S/contrib/vchiq" contrib/vchiq/interface/vchiq_arm/vchiq_kmod.c optional vchiq soc_brcm_bcm2837 \ compile-with "${NORMAL_C} -DUSE_VCHIQ_ARM -D__VCCOREVER__=0x04000000 -I$S/contrib/vchiq" contrib/vchiq/interface/vchiq_arm/vchiq_shim.c optional vchiq soc_brcm_bcm2837 \ compile-with "${NORMAL_C} -DUSE_VCHIQ_ARM -D__VCCOREVER__=0x04000000 -I$S/contrib/vchiq" contrib/vchiq/interface/vchiq_arm/vchiq_util.c optional vchiq soc_brcm_bcm2837 \ compile-with "${NORMAL_C} -DUSE_VCHIQ_ARM -D__VCCOREVER__=0x04000000 -I$S/contrib/vchiq" crypto/armv8/armv8_crypto.c optional armv8crypto armv8_crypto_wrap.o optional armv8crypto \ dependency "$S/crypto/armv8/armv8_crypto_wrap.c" \ compile-with "${CC} -c ${CFLAGS:C/^-O2$/-O3/:N-nostdinc:N-mgeneral-regs-only} ${WERROR} ${NO_WCAST_QUAL} ${PROF} -march=armv8-a+crypto ${.IMPSRC}" \ no-implicit-rule \ clean "armv8_crypto_wrap.o" crypto/blowfish/bf_enc.c optional crypto | ipsec | ipsec_support crypto/des/des_enc.c optional crypto | ipsec | ipsec_support | netsmb dev/acpica/acpi_if.m optional acpi dev/ahci/ahci_generic.c optional ahci dev/axgbe/if_axgbe.c optional axgbe dev/axgbe/xgbe-desc.c optional axgbe dev/axgbe/xgbe-dev.c optional axgbe dev/axgbe/xgbe-drv.c optional axgbe dev/axgbe/xgbe-mdio.c optional axgbe dev/cpufreq/cpufreq_dt.c optional cpufreq fdt dev/iicbus/twsi/a10_twsi.c optional twsi fdt dev/iicbus/twsi/twsi.c optional twsi fdt dev/hwpmc/hwpmc_arm64.c optional hwpmc dev/hwpmc/hwpmc_arm64_md.c optional hwpmc dev/mbox/mbox_if.m optional soc_brcm_bcm2837 dev/mmc/host/dwmmc.c optional dwmmc fdt dev/mmc/host/dwmmc_hisi.c optional dwmmc fdt soc_hisi_hi6220 dev/neta/if_mvneta_fdt.c optional neta fdt dev/neta/if_mvneta.c optional neta mdio mii dev/ofw/ofw_cpu.c optional fdt dev/ofw/ofwpci.c optional fdt pci dev/pci/pci_host_generic.c optional pci dev/pci/pci_host_generic_fdt.c optional pci fdt dev/psci/psci.c optional psci dev/psci/psci_arm64.S optional psci dev/uart/uart_cpu_arm64.c optional uart dev/uart/uart_dev_pl011.c optional uart pl011 dev/usb/controller/dwc_otg_hisi.c optional dwcotg fdt soc_hisi_hi6220 dev/usb/controller/ehci_mv.c optional ehci_mv fdt dev/usb/controller/generic_ehci.c optional ehci acpi dev/usb/controller/generic_ohci.c optional ohci fdt dev/usb/controller/generic_usb_if.m optional ohci fdt dev/usb/controller/xhci_mv.c optional xhci_mv fdt dev/vnic/mrml_bridge.c optional vnic fdt dev/vnic/nic_main.c optional vnic pci dev/vnic/nicvf_main.c optional vnic pci pci_iov dev/vnic/nicvf_queues.c optional vnic pci pci_iov dev/vnic/thunder_bgx_fdt.c optional vnic fdt dev/vnic/thunder_bgx.c optional vnic pci dev/vnic/thunder_mdio_fdt.c optional vnic fdt dev/vnic/thunder_mdio.c optional vnic dev/vnic/lmac_if.m optional inet | inet6 | vnic kern/kern_clocksource.c standard kern/msi_if.m optional intrng kern/pic_if.m optional intrng kern/subr_devmap.c standard kern/subr_intr.c optional intrng libkern/bcmp.c standard libkern/ffs.c standard libkern/ffsl.c standard libkern/ffsll.c standard libkern/fls.c standard libkern/flsl.c standard libkern/flsll.c standard libkern/memset.c standard libkern/arm64/crc32c_armv8.S standard cddl/contrib/opensolaris/common/atomic/aarch64/opensolaris_atomic.S optional zfs | dtrace compile-with "${CDDL_C}" cddl/dev/dtrace/aarch64/dtrace_asm.S optional dtrace compile-with "${DTRACE_S}" cddl/dev/dtrace/aarch64/dtrace_subr.c optional dtrace compile-with "${DTRACE_C}" cddl/dev/fbt/aarch64/fbt_isa.c optional dtrace_fbt | dtraceall compile-with "${FBT_C}"