Index: stable/11/sys/dev/qlxgbe/ql_def.h =================================================================== --- stable/11/sys/dev/qlxgbe/ql_def.h (revision 324761) +++ stable/11/sys/dev/qlxgbe/ql_def.h (revision 324762) @@ -1,277 +1,276 @@ /* * Copyright (c) 2013-2016 Qlogic Corporation * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE * POSSIBILITY OF SUCH DAMAGE. * * $FreeBSD$ */ /* * File: ql_def.h * Author : David C Somayajulu, Qlogic Corporation, Aliso Viejo, CA 92656. */ #ifndef _QL_DEF_H_ #define _QL_DEF_H_ #define BIT_0 (0x1 << 0) #define BIT_1 (0x1 << 1) #define BIT_2 (0x1 << 2) #define BIT_3 (0x1 << 3) #define BIT_4 (0x1 << 4) #define BIT_5 (0x1 << 5) #define BIT_6 (0x1 << 6) #define BIT_7 (0x1 << 7) #define BIT_8 (0x1 << 8) #define BIT_9 (0x1 << 9) #define BIT_10 (0x1 << 10) #define BIT_11 (0x1 << 11) #define BIT_12 (0x1 << 12) #define BIT_13 (0x1 << 13) #define BIT_14 (0x1 << 14) #define BIT_15 (0x1 << 15) #define BIT_16 (0x1 << 16) #define BIT_17 (0x1 << 17) #define BIT_18 (0x1 << 18) #define BIT_19 (0x1 << 19) #define BIT_20 (0x1 << 20) #define BIT_21 (0x1 << 21) #define BIT_22 (0x1 << 22) #define BIT_23 (0x1 << 23) #define BIT_24 (0x1 << 24) #define BIT_25 (0x1 << 25) #define BIT_26 (0x1 << 26) #define BIT_27 (0x1 << 27) #define BIT_28 (0x1 << 28) #define BIT_29 (0x1 << 29) #define BIT_30 (0x1 << 30) #define BIT_31 (0x1 << 31) struct qla_rx_buf { struct mbuf *m_head; bus_dmamap_t map; bus_addr_t paddr; uint32_t handle; void *next; }; typedef struct qla_rx_buf qla_rx_buf_t; struct qla_rx_ring { qla_rx_buf_t rx_buf[NUM_RX_DESCRIPTORS]; }; typedef struct qla_rx_ring qla_rx_ring_t; struct qla_tx_buf { struct mbuf *m_head; bus_dmamap_t map; }; typedef struct qla_tx_buf qla_tx_buf_t; #define QLA_MAX_SEGMENTS 62 /* maximum # of segs in a sg list */ #define QLA_MAX_MTU 9000 #define QLA_STD_FRAME_SIZE 1514 #define QLA_MAX_TSO_FRAME_SIZE ((64 * 1024 - 1) + 22) /* Number of MSIX/MSI Vectors required */ struct qla_ivec { uint32_t sds_idx; void *ha; struct resource *irq; void *handle; int irq_rid; }; typedef struct qla_ivec qla_ivec_t; #define QLA_WATCHDOG_CALLOUT_TICKS 2 typedef struct _qla_tx_ring { qla_tx_buf_t tx_buf[NUM_TX_DESCRIPTORS]; uint64_t count; uint64_t iscsi_pkt_count; } qla_tx_ring_t; typedef struct _qla_tx_fp { struct mtx tx_mtx; char tx_mtx_name[32]; struct buf_ring *tx_br; struct task fp_task; struct taskqueue *fp_taskqueue; void *ha; uint32_t txr_idx; } qla_tx_fp_t; /* * Adapter structure contains the hardware independant information of the * pci function. */ struct qla_host { volatile struct { volatile uint32_t qla_callout_init :1, qla_watchdog_active :1, parent_tag :1, lock_init :1; } flags; volatile uint32_t qla_interface_up; volatile uint32_t stop_rcv; volatile uint32_t qla_watchdog_exit; volatile uint32_t qla_watchdog_exited; volatile uint32_t qla_watchdog_pause; volatile uint32_t qla_watchdog_paused; volatile uint32_t qla_initiate_recovery; volatile uint32_t qla_detach_active; device_t pci_dev; uint16_t watchdog_ticks; uint8_t pci_func; uint8_t resvd; /* ioctl related */ struct cdev *ioctl_dev; /* register mapping */ struct resource *pci_reg; int reg_rid; struct resource *pci_reg1; int reg_rid1; /* interrupts */ struct resource *mbx_irq; void *mbx_handle; int mbx_irq_rid; int msix_count; qla_ivec_t irq_vec[MAX_SDS_RINGS]; /* parent dma tag */ bus_dma_tag_t parent_tag; /* interface to o.s */ struct ifnet *ifp; struct ifmedia media; uint16_t max_frame_size; uint16_t rsrvd0; int if_flags; /* hardware access lock */ struct mtx hw_lock; volatile uint32_t hw_lock_held; uint64_t hw_lock_failed; /* transmit and receive buffers */ uint32_t txr_idx; /* index of the current tx ring */ qla_tx_ring_t tx_ring[NUM_TX_RINGS]; bus_dma_tag_t tx_tag; struct callout tx_callout; qla_tx_fp_t tx_fp[MAX_SDS_RINGS]; qla_rx_ring_t rx_ring[MAX_RDS_RINGS]; bus_dma_tag_t rx_tag; uint32_t std_replenish; qla_rx_buf_t *rxb_free; uint32_t rxb_free_count; - volatile uint32_t posting; /* stats */ uint32_t err_m_getcl; uint32_t err_m_getjcl; uint32_t err_tx_dmamap_create; uint32_t err_tx_dmamap_load; uint32_t err_tx_defrag; uint64_t rx_frames; uint64_t rx_bytes; uint64_t lro_pkt_count; uint64_t lro_bytes; uint64_t ipv4_lro; uint64_t ipv6_lro; uint64_t tx_frames; uint64_t tx_bytes; uint64_t tx_tso_frames; uint64_t hw_vlan_tx_frames; struct task stats_task; struct taskqueue *stats_tq; uint32_t fw_ver_major; uint32_t fw_ver_minor; uint32_t fw_ver_sub; uint32_t fw_ver_build; /* hardware specific */ qla_hw_t hw; /* debug stuff */ volatile const char *qla_lock; volatile const char *qla_unlock; uint32_t dbg_level; uint32_t enable_minidump; uint8_t fw_ver_str[32]; /* Error Injection Related */ uint32_t err_inject; struct task err_task; struct taskqueue *err_tq; /* Async Event Related */ uint32_t async_event; struct task async_event_task; struct taskqueue *async_event_tq; /* Peer Device */ device_t peer_dev; volatile uint32_t msg_from_peer; #define QL_PEER_MSG_RESET 0x01 #define QL_PEER_MSG_ACK 0x02 }; typedef struct qla_host qla_host_t; /* note that align has to be a power of 2 */ #define QL_ALIGN(size, align) (size + (align - 1)) & ~(align - 1); #define QL_MIN(x, y) ((x < y) ? x : y) #define QL_RUNNING(ifp) (ifp->if_drv_flags & IFF_DRV_RUNNING) /* Return 0, if identical, else 1 */ #define QL_MAC_CMP(mac1, mac2) \ ((((*(uint32_t *) mac1) == (*(uint32_t *) mac2) && \ (*(uint16_t *)(mac1 + 4)) == (*(uint16_t *)(mac2 + 4)))) ? 0 : 1) #endif /* #ifndef _QL_DEF_H_ */ Index: stable/11/sys/dev/qlxgbe/ql_glbl.h =================================================================== --- stable/11/sys/dev/qlxgbe/ql_glbl.h (revision 324761) +++ stable/11/sys/dev/qlxgbe/ql_glbl.h (revision 324762) @@ -1,115 +1,119 @@ /* * Copyright (c) 2013-2016 Qlogic Corporation * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE * POSSIBILITY OF SUCH DAMAGE. * * $FreeBSD$ */ /* * File: ql_glbl.h * Author : David C Somayajulu, Qlogic Corporation, Aliso Viejo, CA 92656. * Content: Contains prototypes of the exported functions from each file. */ #ifndef _QL_GLBL_H_ #define _QL_GLBL_H_ /* * from ql_isr.c */ extern void ql_mbx_isr(void *arg); extern void ql_isr(void *arg); extern uint32_t ql_rcv_isr(qla_host_t *ha, uint32_t sds_idx, uint32_t count); /* * from ql_os.c */ extern int ql_alloc_dmabuf(qla_host_t *ha, qla_dma_t *dma_buf); extern void ql_free_dmabuf(qla_host_t *ha, qla_dma_t *dma_buf); extern int ql_get_mbuf(qla_host_t *ha, qla_rx_buf_t *rxb, struct mbuf *nmp); /* * from ql_hw.c */ extern int ql_alloc_dma(qla_host_t *ha); extern void ql_free_dma(qla_host_t *ha); extern void ql_hw_add_sysctls(qla_host_t *ha); extern int ql_hw_send(qla_host_t *ha, bus_dma_segment_t *segs, int nsegs, uint32_t tx_idx, struct mbuf *mp, uint32_t txr_idx, uint32_t iscsi_pdu); extern void qla_confirm_9kb_enable(qla_host_t *ha); extern int ql_init_hw_if(qla_host_t *ha); extern int ql_hw_set_multi(qla_host_t *ha, uint8_t *mta, uint32_t mcnt, uint32_t add_multi); extern void ql_del_hw_if(qla_host_t *ha); extern int ql_set_promisc(qla_host_t *ha); extern void qla_reset_promisc(qla_host_t *ha); extern int ql_set_allmulti(qla_host_t *ha); extern void qla_reset_allmulti(qla_host_t *ha); extern void ql_update_link_state(qla_host_t *ha); extern void ql_hw_tx_done_locked(qla_host_t *ha, uint32_t txr_idx); extern int ql_set_max_mtu(qla_host_t *ha, uint32_t mtu, uint16_t cntxt_id); extern void ql_get_stats(qla_host_t *ha); extern void ql_hw_link_status(qla_host_t *ha); extern int ql_hw_check_health(qla_host_t *ha); extern void qla_hw_async_event(qla_host_t *ha); extern int qla_get_nic_partition(qla_host_t *ha, uint32_t *supports_9kb, uint32_t *num_rcvq); extern int qla_hw_del_all_mcast(qla_host_t *ha); extern int ql_iscsi_pdu(qla_host_t *ha, struct mbuf *mp); extern void ql_minidump(qla_host_t *ha); extern int ql_minidump_init(qla_host_t *ha); /* * from ql_misc.c */ extern int ql_init_hw(qla_host_t *ha); extern int ql_rdwr_indreg32(qla_host_t *ha, uint32_t addr, uint32_t *val, uint32_t rd); extern int ql_rd_flash32(qla_host_t *ha, uint32_t addr, uint32_t *data); extern int ql_rdwr_offchip_mem(qla_host_t *ha, uint64_t addr, q80_offchip_mem_val_t *val, uint32_t rd); extern void ql_read_mac_addr(qla_host_t *ha); extern int ql_erase_flash(qla_host_t *ha, uint32_t off, uint32_t size); extern int ql_wr_flash_buffer(qla_host_t *ha, uint32_t off, uint32_t size, void *buf); extern int ql_stop_sequence(qla_host_t *ha); extern int ql_start_sequence(qla_host_t *ha, uint16_t index); /* * from ql_ioctl.c */ extern int ql_make_cdev(qla_host_t *ha); extern void ql_del_cdev(qla_host_t *ha); extern unsigned char ql83xx_firmware[]; extern unsigned int ql83xx_firmware_len; extern unsigned char ql83xx_bootloader[]; extern unsigned int ql83xx_bootloader_len; extern unsigned char ql83xx_resetseq[]; extern unsigned int ql83xx_resetseq_len; extern unsigned char ql83xx_minidump[]; extern unsigned int ql83xx_minidump_len; +extern void ql_alloc_drvr_state_buffer(qla_host_t *ha); +extern void ql_free_drvr_state_buffer(qla_host_t *ha); +extern void ql_capture_drvr_state(qla_host_t *ha); + #endif /* #ifndef_QL_GLBL_H_ */ Index: stable/11/sys/dev/qlxgbe/ql_hw.h =================================================================== --- stable/11/sys/dev/qlxgbe/ql_hw.h (revision 324761) +++ stable/11/sys/dev/qlxgbe/ql_hw.h (revision 324762) @@ -1,1761 +1,1764 @@ /* * Copyright (c) 2013-2016 Qlogic Corporation * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE * POSSIBILITY OF SUCH DAMAGE. * * $FreeBSD$ */ /* * File: ql_hw.h * Author : David C Somayajulu, Qlogic Corporation, Aliso Viejo, CA 92656. */ #ifndef _QL_HW_H_ #define _QL_HW_H_ /* * PCIe Registers; Direct Mapped; Offsets from BAR0 */ /* * Register offsets for QLE8030 */ /* * Firmware Mailbox Registers * 0 thru 511; offsets 0x800 thru 0xFFC; 32bits each */ #define Q8_FW_MBOX0 0x00000800 #define Q8_FW_MBOX511 0x00000FFC /* * Host Mailbox Registers * 0 thru 511; offsets 0x000 thru 0x7FC; 32bits each */ #define Q8_HOST_MBOX0 0x00000000 #define Q8_HOST_MBOX511 0x000007FC #define Q8_MBOX_INT_ENABLE 0x00001000 #define Q8_MBOX_INT_MASK_MSIX 0x00001200 #define Q8_MBOX_INT_LEGACY 0x00003010 #define Q8_HOST_MBOX_CNTRL 0x00003038 #define Q8_FW_MBOX_CNTRL 0x0000303C #define Q8_PEG_HALT_STATUS1 0x000034A8 #define Q8_PEG_HALT_STATUS2 0x000034AC #define Q8_FIRMWARE_HEARTBEAT 0x000034B0 #define Q8_FLASH_LOCK_ID 0x00003500 #define Q8_DRIVER_LOCK_ID 0x00003504 #define Q8_FW_CAPABILITIES 0x00003528 #define Q8_FW_VER_MAJOR 0x00003550 #define Q8_FW_VER_MINOR 0x00003554 #define Q8_FW_VER_SUB 0x00003558 #define Q8_BOOTLD_ADDR 0x0000355C #define Q8_BOOTLD_SIZE 0x00003560 #define Q8_FW_IMAGE_ADDR 0x00003564 #define Q8_FW_BUILD_NUMBER 0x00003568 #define Q8_FW_IMAGE_VALID 0x000035FC #define Q8_CMDPEG_STATE 0x00003650 #define Q8_LINK_STATE 0x00003698 #define Q8_LINK_STATE_2 0x0000369C #define Q8_LINK_SPEED_0 0x000036E0 #define Q8_LINK_SPEED_1 0x000036E4 #define Q8_LINK_SPEED_2 0x000036E8 #define Q8_LINK_SPEED_3 0x000036EC #define Q8_MAX_LINK_SPEED_0 0x000036F0 #define Q8_MAX_LINK_SPEED_1 0x000036F4 #define Q8_MAX_LINK_SPEED_2 0x000036F8 #define Q8_MAX_LINK_SPEED_3 0x000036FC #define Q8_ASIC_TEMPERATURE 0x000037B4 /* * CRB Window Registers * 0 thru 15; offsets 0x3800 thru 0x383C; 32bits each */ #define Q8_CRB_WINDOW_PF0 0x00003800 #define Q8_CRB_WINDOW_PF15 0x0000383C #define Q8_FLASH_LOCK 0x00003850 #define Q8_FLASH_UNLOCK 0x00003854 #define Q8_DRIVER_LOCK 0x00003868 #define Q8_DRIVER_UNLOCK 0x0000386C #define Q8_LEGACY_INT_PTR 0x000038C0 #define Q8_LEGACY_INT_TRIG 0x000038C4 #define Q8_LEGACY_INT_MASK 0x000038C8 #define Q8_WILD_CARD 0x000038F0 #define Q8_INFORMANT 0x000038FC /* * Ethernet Interface Specific Registers */ #define Q8_DRIVER_OP_MODE 0x00003570 #define Q8_API_VERSION 0x0000356C #define Q8_NPAR_STATE 0x0000359C /* * End of PCIe Registers; Direct Mapped; Offsets from BAR0 */ /* * Indirect Registers */ #define Q8_LED_DUAL_0 0x28084C80 #define Q8_LED_SINGLE_0 0x28084C90 #define Q8_LED_DUAL_1 0x28084CA0 #define Q8_LED_SINGLE_1 0x28084CB0 #define Q8_LED_DUAL_2 0x28084CC0 #define Q8_LED_SINGLE_2 0x28084CD0 #define Q8_LED_DUAL_3 0x28084CE0 #define Q8_LED_SINGLE_3 0x28084CF0 #define Q8_GPIO_1 0x28084D00 #define Q8_GPIO_2 0x28084D10 #define Q8_GPIO_3 0x28084D20 #define Q8_GPIO_4 0x28084D40 #define Q8_GPIO_5 0x28084D50 #define Q8_GPIO_6 0x28084D60 #define Q8_GPIO_7 0x42100060 #define Q8_GPIO_8 0x42100064 #define Q8_FLASH_SPI_STATUS 0x2808E010 #define Q8_FLASH_SPI_CONTROL 0x2808E014 #define Q8_FLASH_STATUS 0x42100004 #define Q8_FLASH_CONTROL 0x42110004 #define Q8_FLASH_ADDRESS 0x42110008 #define Q8_FLASH_WR_DATA 0x4211000C #define Q8_FLASH_RD_DATA 0x42110018 #define Q8_FLASH_DIRECT_WINDOW 0x42110030 #define Q8_FLASH_DIRECT_DATA 0x42150000 #define Q8_MS_CNTRL 0x41000090 #define Q8_MS_ADDR_LO 0x41000094 #define Q8_MS_ADDR_HI 0x41000098 #define Q8_MS_WR_DATA_0_31 0x410000A0 #define Q8_MS_WR_DATA_32_63 0x410000A4 #define Q8_MS_WR_DATA_64_95 0x410000B0 #define Q8_MS_WR_DATA_96_127 0x410000B4 #define Q8_MS_RD_DATA_0_31 0x410000A8 #define Q8_MS_RD_DATA_32_63 0x410000AC #define Q8_MS_RD_DATA_64_95 0x410000B8 #define Q8_MS_RD_DATA_96_127 0x410000BC #define Q8_CRB_PEG_0 0x3400003c #define Q8_CRB_PEG_1 0x3410003c #define Q8_CRB_PEG_2 0x3420003c #define Q8_CRB_PEG_3 0x3430003c #define Q8_CRB_PEG_4 0x34B0003c /* * Macros for reading and writing registers */ #if defined(__i386__) || defined(__amd64__) #define Q8_MB() __asm volatile("mfence" ::: "memory") #define Q8_WMB() __asm volatile("sfence" ::: "memory") #define Q8_RMB() __asm volatile("lfence" ::: "memory") #else #define Q8_MB() #define Q8_WMB() #define Q8_RMB() #endif #define READ_REG32(ha, reg) bus_read_4((ha->pci_reg), reg) #define WRITE_REG32(ha, reg, val) \ {\ bus_write_4((ha->pci_reg), reg, val);\ bus_read_4((ha->pci_reg), reg);\ } #define Q8_NUM_MBOX 512 #define Q8_MAX_NUM_MULTICAST_ADDRS 1022 #define Q8_MAC_ADDR_LEN 6 /* * Firmware Interface */ /* * Command Response Interface - Commands */ #define Q8_MBX_CONFIG_IP_ADDRESS 0x0001 #define Q8_MBX_CONFIG_INTR 0x0002 #define Q8_MBX_MAP_INTR_SRC 0x0003 #define Q8_MBX_MAP_SDS_TO_RDS 0x0006 #define Q8_MBX_CREATE_RX_CNTXT 0x0007 #define Q8_MBX_DESTROY_RX_CNTXT 0x0008 #define Q8_MBX_CREATE_TX_CNTXT 0x0009 #define Q8_MBX_DESTROY_TX_CNTXT 0x000A #define Q8_MBX_ADD_RX_RINGS 0x000B #define Q8_MBX_CONFIG_LRO_FLOW 0x000C #define Q8_MBX_CONFIG_MAC_LEARNING 0x000D #define Q8_MBX_GET_STATS 0x000F #define Q8_MBX_GENERATE_INTR 0x0011 #define Q8_MBX_SET_MAX_MTU 0x0012 #define Q8_MBX_MAC_ADDR_CNTRL 0x001F #define Q8_MBX_GET_PCI_CONFIG 0x0020 #define Q8_MBX_GET_NIC_PARTITION 0x0021 #define Q8_MBX_SET_NIC_PARTITION 0x0022 #define Q8_MBX_QUERY_WOL_CAP 0x002C #define Q8_MBX_SET_WOL_CONFIG 0x002D #define Q8_MBX_GET_MINIDUMP_TMPLT_SIZE 0x002F #define Q8_MBX_GET_MINIDUMP_TMPLT 0x0030 #define Q8_MBX_GET_FW_DCBX_CAPS 0x0034 #define Q8_MBX_QUERY_DCBX_SETTINGS 0x0035 #define Q8_MBX_CONFIG_RSS 0x0041 #define Q8_MBX_CONFIG_RSS_TABLE 0x0042 #define Q8_MBX_CONFIG_INTR_COALESCE 0x0043 #define Q8_MBX_CONFIG_LED 0x0044 #define Q8_MBX_CONFIG_MAC_ADDR 0x0045 #define Q8_MBX_CONFIG_STATISTICS 0x0046 #define Q8_MBX_CONFIG_LOOPBACK 0x0047 #define Q8_MBX_LINK_EVENT_REQ 0x0048 #define Q8_MBX_CONFIG_MAC_RX_MODE 0x0049 #define Q8_MBX_CONFIG_FW_LRO 0x004A #define Q8_MBX_HW_CONFIG 0x004C #define Q8_MBX_INIT_NIC_FUNC 0x0060 #define Q8_MBX_STOP_NIC_FUNC 0x0061 #define Q8_MBX_IDC_REQ 0x0062 #define Q8_MBX_IDC_ACK 0x0063 #define Q8_MBX_SET_PORT_CONFIG 0x0066 #define Q8_MBX_GET_PORT_CONFIG 0x0067 #define Q8_MBX_GET_LINK_STATUS 0x0068 /* * Mailbox Command Response */ #define Q8_MBX_RSP_SUCCESS 0x0001 #define Q8_MBX_RSP_RESPONSE_FAILURE 0x0002 #define Q8_MBX_RSP_NO_CARD_CRB 0x0003 #define Q8_MBX_RSP_NO_CARD_MEM 0x0004 #define Q8_MBX_RSP_NO_CARD_RSRC 0x0005 #define Q8_MBX_RSP_INVALID_ARGS 0x0006 #define Q8_MBX_RSP_INVALID_ACTION 0x0007 #define Q8_MBX_RSP_INVALID_STATE 0x0008 #define Q8_MBX_RSP_NOT_SUPPORTED 0x0009 #define Q8_MBX_RSP_NOT_PERMITTED 0x000A #define Q8_MBX_RSP_NOT_READY 0x000B #define Q8_MBX_RSP_DOES_NOT_EXIST 0x000C #define Q8_MBX_RSP_ALREADY_EXISTS 0x000D #define Q8_MBX_RSP_BAD_SIGNATURE 0x000E #define Q8_MBX_RSP_CMD_NOT_IMPLEMENTED 0x000F #define Q8_MBX_RSP_CMD_INVALID 0x0010 #define Q8_MBX_RSP_TIMEOUT 0x0011 #define Q8_MBX_RSP_CMD_FAILED 0x0012 #define Q8_MBX_RSP_FATAL_TEMP 0x0013 #define Q8_MBX_RSP_MAX_EXCEEDED 0x0014 #define Q8_MBX_RSP_UNSPECIFIED 0x0015 #define Q8_MBX_RSP_INTR_CREATE_FAILED 0x0017 #define Q8_MBX_RSP_INTR_DELETE_FAILED 0x0018 #define Q8_MBX_RSP_INTR_INVALID_OP 0x0019 #define Q8_MBX_RSP_IDC_INTRMD_RSP 0x001A #define Q8_MBX_CMD_VERSION (0x2 << 13) #define Q8_MBX_RSP_STATUS(x) (((!(x >> 9)) || ((x >> 9) == 1)) ? 0: (x >> 9)) /* * Configure IP Address */ typedef struct _q80_config_ip_addr { uint16_t opcode; uint16_t count_version; uint8_t cmd; #define Q8_MBX_CONFIG_IP_ADD_IP 0x1 #define Q8_MBX_CONFIG_IP_DEL_IP 0x2 uint8_t ip_type; #define Q8_MBX_CONFIG_IP_V4 0x0 #define Q8_MBX_CONFIG_IP_V6 0x1 uint16_t rsrvd; union { struct { uint32_t addr; uint32_t rsrvd[3]; } ipv4; uint8_t ipv6_addr[16]; } u; } __packed q80_config_ip_addr_t; typedef struct _q80_config_ip_addr_rsp { uint16_t opcode; uint16_t regcnt_status; } __packed q80_config_ip_addr_rsp_t; /* * Configure Interrupt Command */ typedef struct _q80_intr { uint8_t cmd_type; #define Q8_MBX_CONFIG_INTR_CREATE 0x1 #define Q8_MBX_CONFIG_INTR_DELETE 0x2 #define Q8_MBX_CONFIG_INTR_TYPE_LINE (0x1 << 4) #define Q8_MBX_CONFIG_INTR_TYPE_MSI_X (0x3 << 4) uint8_t rsrvd; uint16_t msix_index; } __packed q80_intr_t; #define Q8_MAX_INTR_VECTORS 16 typedef struct _q80_config_intr { uint16_t opcode; uint16_t count_version; uint8_t nentries; uint8_t rsrvd[3]; q80_intr_t intr[Q8_MAX_INTR_VECTORS]; } __packed q80_config_intr_t; typedef struct _q80_intr_rsp { uint8_t status; uint8_t cmd; uint16_t intr_id; uint32_t intr_src; } q80_intr_rsp_t; typedef struct _q80_config_intr_rsp { uint16_t opcode; uint16_t regcnt_status; uint8_t nentries; uint8_t rsrvd[3]; q80_intr_rsp_t intr[Q8_MAX_INTR_VECTORS]; } __packed q80_config_intr_rsp_t; /* * Configure LRO Flow Command */ typedef struct _q80_config_lro_flow { uint16_t opcode; uint16_t count_version; uint8_t cmd; #define Q8_MBX_CONFIG_LRO_FLOW_ADD 0x01 #define Q8_MBX_CONFIG_LRO_FLOW_DELETE 0x02 uint8_t type_ts; #define Q8_MBX_CONFIG_LRO_FLOW_IPV4 0x00 #define Q8_MBX_CONFIG_LRO_FLOW_IPV6 0x01 #define Q8_MBX_CONFIG_LRO_FLOW_TS_ABSENT 0x00 #define Q8_MBX_CONFIG_LRO_FLOW_TS_PRESENT 0x02 uint16_t rsrvd; union { struct { uint32_t addr; uint32_t rsrvd[3]; } ipv4; uint8_t ipv6_addr[16]; } dst; union { struct { uint32_t addr; uint32_t rsrvd[3]; } ipv4; uint8_t ipv6_addr[16]; } src; uint16_t dst_port; uint16_t src_port; } __packed q80_config_lro_flow_t; typedef struct _q80_config_lro_flow_rsp { uint16_t opcode; uint16_t regcnt_status; } __packed q80_config_lro_flow_rsp_t; typedef struct _q80_set_max_mtu { uint16_t opcode; uint16_t count_version; uint32_t cntxt_id; uint32_t mtu; } __packed q80_set_max_mtu_t; typedef struct _q80_set_max_mtu_rsp { uint16_t opcode; uint16_t regcnt_status; } __packed q80_set_max_mtu_rsp_t; /* * Configure RSS */ typedef struct _q80_config_rss { uint16_t opcode; uint16_t count_version; uint16_t cntxt_id; uint16_t rsrvd; uint8_t hash_type; #define Q8_MBX_RSS_HASH_TYPE_IPV4_IP (0x1 << 4) #define Q8_MBX_RSS_HASH_TYPE_IPV4_TCP (0x2 << 4) #define Q8_MBX_RSS_HASH_TYPE_IPV4_TCP_IP (0x3 << 4) #define Q8_MBX_RSS_HASH_TYPE_IPV6_IP (0x1 << 6) #define Q8_MBX_RSS_HASH_TYPE_IPV6_TCP (0x2 << 6) #define Q8_MBX_RSS_HASH_TYPE_IPV6_TCP_IP (0x3 << 6) uint8_t flags; #define Q8_MBX_RSS_FLAGS_ENABLE_RSS (0x1) #define Q8_MBX_RSS_FLAGS_USE_IND_TABLE (0x2) #define Q8_MBX_RSS_FLAGS_TYPE_CRSS (0x4) uint16_t indtbl_mask; #define Q8_MBX_RSS_INDTBL_MASK 0x7F #define Q8_MBX_RSS_FLAGS_MULTI_RSS_VALID 0x8000 uint32_t multi_rss; #define Q8_MBX_RSS_MULTI_RSS_ENGINE_ASSIGN BIT_30 #define Q8_MBX_RSS_USE_MULTI_RSS_ENGINES BIT_31 uint64_t rss_key[5]; } __packed q80_config_rss_t; typedef struct _q80_config_rss_rsp { uint16_t opcode; uint16_t regcnt_status; } __packed q80_config_rss_rsp_t; /* * Configure RSS Indirection Table */ #define Q8_RSS_IND_TBL_SIZE 40 #define Q8_RSS_IND_TBL_MIN_IDX 0 #define Q8_RSS_IND_TBL_MAX_IDX 127 typedef struct _q80_config_rss_ind_table { uint16_t opcode; uint16_t count_version; uint8_t start_idx; uint8_t end_idx; uint16_t cntxt_id; uint8_t ind_table[Q8_RSS_IND_TBL_SIZE]; } __packed q80_config_rss_ind_table_t; typedef struct _q80_config_rss_ind_table_rsp { uint16_t opcode; uint16_t regcnt_status; } __packed q80_config_rss_ind_table_rsp_t; /* * Configure Interrupt Coalescing and Generation */ typedef struct _q80_config_intr_coalesc { uint16_t opcode; uint16_t count_version; uint16_t flags; #define Q8_MBX_INTRC_FLAGS_RCV 1 #define Q8_MBX_INTRC_FLAGS_XMT 2 #define Q8_MBX_INTRC_FLAGS_PERIODIC (1 << 3) uint16_t cntxt_id; uint16_t max_pkts; uint16_t max_mswait; uint8_t timer_type; #define Q8_MBX_INTRC_TIMER_NONE 0 #define Q8_MBX_INTRC_TIMER_SINGLE 1 #define Q8_MBX_INTRC_TIMER_PERIODIC 2 uint16_t sds_ring_mask; uint8_t rsrvd; uint32_t ms_timeout; } __packed q80_config_intr_coalesc_t; typedef struct _q80_config_intr_coalesc_rsp { uint16_t opcode; uint16_t regcnt_status; } __packed q80_config_intr_coalesc_rsp_t; /* * Configure MAC Address */ #define Q8_ETHER_ADDR_LEN 6 typedef struct _q80_mac_addr { uint8_t addr[Q8_ETHER_ADDR_LEN]; uint16_t vlan_tci; } __packed q80_mac_addr_t; #define Q8_MAX_MAC_ADDRS 64 typedef struct _q80_config_mac_addr { uint16_t opcode; uint16_t count_version; uint8_t cmd; #define Q8_MBX_CMAC_CMD_ADD_MAC_ADDR 1 #define Q8_MBX_CMAC_CMD_DEL_MAC_ADDR 2 #define Q8_MBX_CMAC_CMD_CAM_BOTH (0x0 << 6) #define Q8_MBX_CMAC_CMD_CAM_INGRESS (0x1 << 6) #define Q8_MBX_CMAC_CMD_CAM_EGRESS (0x2 << 6) uint8_t nmac_entries; uint16_t cntxt_id; q80_mac_addr_t mac_addr[Q8_MAX_MAC_ADDRS]; } __packed q80_config_mac_addr_t; typedef struct _q80_config_mac_addr_rsp { uint16_t opcode; uint16_t regcnt_status; uint8_t cmd; uint8_t nmac_entries; uint16_t cntxt_id; uint32_t status[Q8_MAX_MAC_ADDRS]; } __packed q80_config_mac_addr_rsp_t; /* * Configure MAC Receive Mode */ typedef struct _q80_config_mac_rcv_mode { uint16_t opcode; uint16_t count_version; uint8_t mode; #define Q8_MBX_MAC_RCV_PROMISC_ENABLE 0x1 #define Q8_MBX_MAC_ALL_MULTI_ENABLE 0x2 uint8_t rsrvd; uint16_t cntxt_id; } __packed q80_config_mac_rcv_mode_t; typedef struct _q80_config_mac_rcv_mode_rsp { uint16_t opcode; uint16_t regcnt_status; } __packed q80_config_mac_rcv_mode_rsp_t; /* * Configure Firmware Controlled LRO */ typedef struct _q80_config_fw_lro { uint16_t opcode; uint16_t count_version; uint8_t flags; #define Q8_MBX_FW_LRO_IPV4 0x1 #define Q8_MBX_FW_LRO_IPV6 0x2 #define Q8_MBX_FW_LRO_IPV4_WO_DST_IP_CHK 0x4 #define Q8_MBX_FW_LRO_IPV6_WO_DST_IP_CHK 0x8 #define Q8_MBX_FW_LRO_LOW_THRESHOLD 0x10 uint8_t rsrvd; uint16_t cntxt_id; uint16_t low_threshold; uint16_t rsrvd0; } __packed q80_config_fw_lro_t; typedef struct _q80_config_fw_lro_rsp { uint16_t opcode; uint16_t regcnt_status; } __packed q80_config_fw_lro_rsp_t; /* * Minidump mailbox commands */ typedef struct _q80_config_md_templ_size { uint16_t opcode; uint16_t count_version; } __packed q80_config_md_templ_size_t; typedef struct _q80_config_md_templ_size_rsp { uint16_t opcode; uint16_t regcnt_status; uint32_t rsrvd; uint32_t templ_size; uint32_t templ_version; } __packed q80_config_md_templ_size_rsp_t; typedef struct _q80_config_md_templ_cmd { uint16_t opcode; uint16_t count_version; uint64_t buf_addr; /* physical address of buffer */ uint32_t buff_size; uint32_t offset; } __packed q80_config_md_templ_cmd_t; typedef struct _q80_config_md_templ_cmd_rsp { uint16_t opcode; uint16_t regcnt_status; uint32_t rsrvd; uint32_t templ_size; uint32_t buff_size; uint32_t offset; } __packed q80_config_md_templ_cmd_rsp_t; /* * Hardware Configuration Commands */ typedef struct _q80_hw_config { uint16_t opcode; uint16_t count_version; #define Q8_HW_CONFIG_SET_MDIO_REG_COUNT 0x06 #define Q8_HW_CONFIG_GET_MDIO_REG_COUNT 0x05 #define Q8_HW_CONFIG_SET_CAM_SEARCH_MODE_COUNT 0x03 #define Q8_HW_CONFIG_GET_CAM_SEARCH_MODE_COUNT 0x02 #define Q8_HW_CONFIG_SET_TEMP_THRESHOLD_COUNT 0x03 #define Q8_HW_CONFIG_GET_TEMP_THRESHOLD_COUNT 0x02 #define Q8_HW_CONFIG_GET_ECC_COUNTS_COUNT 0x02 uint32_t cmd; #define Q8_HW_CONFIG_SET_MDIO_REG 0x01 #define Q8_HW_CONFIG_GET_MDIO_REG 0x02 #define Q8_HW_CONFIG_SET_CAM_SEARCH_MODE 0x03 #define Q8_HW_CONFIG_GET_CAM_SEARCH_MODE 0x04 #define Q8_HW_CONFIG_SET_TEMP_THRESHOLD 0x07 #define Q8_HW_CONFIG_GET_TEMP_THRESHOLD 0x08 #define Q8_HW_CONFIG_GET_ECC_COUNTS 0x0A union { struct { uint32_t phys_port_number; uint32_t phy_dev_addr; uint32_t reg_addr; uint32_t data; } set_mdio; struct { uint32_t phys_port_number; uint32_t phy_dev_addr; uint32_t reg_addr; } get_mdio; struct { uint32_t mode; #define Q8_HW_CONFIG_CAM_SEARCH_MODE_INTERNAL 0x1 #define Q8_HW_CONFIG_CAM_SEARCH_MODE_AUTO 0x2 } set_cam_search_mode; struct { uint32_t value; } set_temp_threshold; } u; } __packed q80_hw_config_t; typedef struct _q80_hw_config_rsp { uint16_t opcode; uint16_t regcnt_status; union { struct { uint32_t value; } get_mdio; struct { uint32_t mode; } get_cam_search_mode; struct { uint32_t temp_warn; uint32_t curr_temp; uint32_t osc_ring_rate; uint32_t core_voltage; } get_temp_threshold; struct { uint32_t ddr_ecc_error_count; uint32_t ocm_ecc_error_count; uint32_t l2_dcache_ecc_error_count; uint32_t l2_icache_ecc_error_count; uint32_t eport_ecc_error_count; } get_ecc_counts; } u; } __packed q80_hw_config_rsp_t; /* * Link Event Request Command */ typedef struct _q80_link_event { uint16_t opcode; uint16_t count_version; uint8_t cmd; #define Q8_LINK_EVENT_CMD_STOP_PERIODIC 0 #define Q8_LINK_EVENT_CMD_ENABLE_ASYNC 1 uint8_t flags; #define Q8_LINK_EVENT_FLAGS_SEND_RSP 1 uint16_t cntxt_id; } __packed q80_link_event_t; typedef struct _q80_link_event_rsp { uint16_t opcode; uint16_t regcnt_status; } __packed q80_link_event_rsp_t; /* * Get Statistics Command */ typedef struct _q80_rcv_stats { uint64_t total_bytes; uint64_t total_pkts; uint64_t lro_pkt_count; uint64_t sw_pkt_count; uint64_t ip_chksum_err; uint64_t pkts_wo_acntxts; uint64_t pkts_dropped_no_sds_card; uint64_t pkts_dropped_no_sds_host; uint64_t oversized_pkts; uint64_t pkts_dropped_no_rds; uint64_t unxpctd_mcast_pkts; uint64_t re1_fbq_error; uint64_t invalid_mac_addr; uint64_t rds_prime_trys; uint64_t rds_prime_success; uint64_t lro_flows_added; uint64_t lro_flows_deleted; uint64_t lro_flows_active; uint64_t pkts_droped_unknown; uint64_t pkts_cnt_oversized; } __packed q80_rcv_stats_t; typedef struct _q80_xmt_stats { uint64_t total_bytes; uint64_t total_pkts; uint64_t errors; uint64_t pkts_dropped; uint64_t switch_pkts; uint64_t num_buffers; } __packed q80_xmt_stats_t; typedef struct _q80_mac_stats { uint64_t xmt_frames; uint64_t xmt_bytes; uint64_t xmt_mcast_pkts; uint64_t xmt_bcast_pkts; uint64_t xmt_pause_frames; uint64_t xmt_cntrl_pkts; uint64_t xmt_pkt_lt_64bytes; uint64_t xmt_pkt_lt_127bytes; uint64_t xmt_pkt_lt_255bytes; uint64_t xmt_pkt_lt_511bytes; uint64_t xmt_pkt_lt_1023bytes; uint64_t xmt_pkt_lt_1518bytes; uint64_t xmt_pkt_gt_1518bytes; uint64_t rsrvd0[3]; uint64_t rcv_frames; uint64_t rcv_bytes; uint64_t rcv_mcast_pkts; uint64_t rcv_bcast_pkts; uint64_t rcv_pause_frames; uint64_t rcv_cntrl_pkts; uint64_t rcv_pkt_lt_64bytes; uint64_t rcv_pkt_lt_127bytes; uint64_t rcv_pkt_lt_255bytes; uint64_t rcv_pkt_lt_511bytes; uint64_t rcv_pkt_lt_1023bytes; uint64_t rcv_pkt_lt_1518bytes; uint64_t rcv_pkt_gt_1518bytes; uint64_t rsrvd1[3]; uint64_t rcv_len_error; uint64_t rcv_len_small; uint64_t rcv_len_large; uint64_t rcv_jabber; uint64_t rcv_dropped; uint64_t fcs_error; uint64_t align_error; uint64_t eswitched_frames; uint64_t eswitched_bytes; uint64_t eswitched_mcast_frames; uint64_t eswitched_bcast_frames; uint64_t eswitched_ucast_frames; uint64_t eswitched_err_free_frames; uint64_t eswitched_err_free_bytes; } __packed q80_mac_stats_t; typedef struct _q80_get_stats { uint16_t opcode; uint16_t count_version; uint32_t cmd; #define Q8_GET_STATS_CMD_CLEAR 0x01 #define Q8_GET_STATS_CMD_RCV 0x00 #define Q8_GET_STATS_CMD_XMT 0x02 #define Q8_GET_STATS_CMD_TYPE_CNTXT 0x00 #define Q8_GET_STATS_CMD_TYPE_MAC 0x04 #define Q8_GET_STATS_CMD_TYPE_FUNC 0x08 #define Q8_GET_STATS_CMD_TYPE_VPORT 0x0C #define Q8_GET_STATS_CMD_TYPE_ALL (0x7 << 2) } __packed q80_get_stats_t; typedef struct _q80_get_stats_rsp { uint16_t opcode; uint16_t regcnt_status; uint32_t cmd; union { q80_rcv_stats_t rcv; q80_xmt_stats_t xmt; q80_mac_stats_t mac; } u; } __packed q80_get_stats_rsp_t; typedef struct _q80_get_mac_rcv_xmt_stats_rsp { uint16_t opcode; uint16_t regcnt_status; uint32_t cmd; q80_mac_stats_t mac; q80_rcv_stats_t rcv; q80_xmt_stats_t xmt; } __packed q80_get_mac_rcv_xmt_stats_rsp_t; /* * Init NIC Function * Used to Register DCBX Configuration Change AEN */ typedef struct _q80_init_nic_func { uint16_t opcode; uint16_t count_version; uint32_t options; #define Q8_INIT_NIC_REG_IDC_AEN 0x01 #define Q8_INIT_NIC_REG_DCBX_CHNG_AEN 0x02 #define Q8_INIT_NIC_REG_SFP_CHNG_AEN 0x04 } __packed q80_init_nic_func_t; typedef struct _q80_init_nic_func_rsp { uint16_t opcode; uint16_t regcnt_status; } __packed q80_init_nic_func_rsp_t; /* * Stop NIC Function * Used to DeRegister DCBX Configuration Change AEN */ typedef struct _q80_stop_nic_func { uint16_t opcode; uint16_t count_version; uint32_t options; #define Q8_STOP_NIC_DEREG_DCBX_CHNG_AEN 0x02 #define Q8_STOP_NIC_DEREG_SFP_CHNG_AEN 0x04 } __packed q80_stop_nic_func_t; typedef struct _q80_stop_nic_func_rsp { uint16_t opcode; uint16_t regcnt_status; } __packed q80_stop_nic_func_rsp_t; /* * Query Firmware DCBX Capabilities */ typedef struct _q80_query_fw_dcbx_caps { uint16_t opcode; uint16_t count_version; } __packed q80_query_fw_dcbx_caps_t; typedef struct _q80_query_fw_dcbx_caps_rsp { uint16_t opcode; uint16_t regcnt_status; uint32_t dcbx_caps; #define Q8_QUERY_FW_DCBX_CAPS_TSA 0x00000001 #define Q8_QUERY_FW_DCBX_CAPS_ETS 0x00000002 #define Q8_QUERY_FW_DCBX_CAPS_DCBX_CEE_1_01 0x00000004 #define Q8_QUERY_FW_DCBX_CAPS_DCBX_IEEE_1_0 0x00000008 #define Q8_QUERY_FW_DCBX_MAX_TC_MASK 0x00F00000 #define Q8_QUERY_FW_DCBX_MAX_ETS_TC_MASK 0x0F000000 #define Q8_QUERY_FW_DCBX_MAX_PFC_TC_MASK 0xF0000000 } __packed q80_query_fw_dcbx_caps_rsp_t; /* * IDC Ack Cmd */ typedef struct _q80_idc_ack { uint16_t opcode; uint16_t count_version; uint32_t aen_mb1; uint32_t aen_mb2; uint32_t aen_mb3; uint32_t aen_mb4; } __packed q80_idc_ack_t; typedef struct _q80_idc_ack_rsp { uint16_t opcode; uint16_t regcnt_status; } __packed q80_idc_ack_rsp_t; /* * Set Port Configuration command * Used to set Ethernet Standard Pause values */ typedef struct _q80_set_port_cfg { uint16_t opcode; uint16_t count_version; uint32_t cfg_bits; #define Q8_PORT_CFG_BITS_LOOPBACK_MODE_MASK (0x7 << 1) #define Q8_PORT_CFG_BITS_LOOPBACK_MODE_NONE (0x0 << 1) #define Q8_PORT_CFG_BITS_LOOPBACK_MODE_HSS (0x2 << 1) #define Q8_PORT_CFG_BITS_LOOPBACK_MODE_PHY (0x3 << 1) #define Q8_PORT_CFG_BITS_LOOPBACK_MODE_EXT (0x4 << 1) #define Q8_VALID_LOOPBACK_MODE(mode) \ (((mode) == Q8_PORT_CFG_BITS_LOOPBACK_MODE_NONE) || \ (((mode) >= Q8_PORT_CFG_BITS_LOOPBACK_MODE_HSS) && \ ((mode) <= Q8_PORT_CFG_BITS_LOOPBACK_MODE_EXT))) #define Q8_PORT_CFG_BITS_DCBX_ENABLE BIT_4 #define Q8_PORT_CFG_BITS_PAUSE_CFG_MASK (0x3 << 5) #define Q8_PORT_CFG_BITS_PAUSE_DISABLED (0x0 << 5) #define Q8_PORT_CFG_BITS_PAUSE_STD (0x1 << 5) #define Q8_PORT_CFG_BITS_PAUSE_PPM (0x2 << 5) #define Q8_PORT_CFG_BITS_LNKCAP_10MB BIT_8 #define Q8_PORT_CFG_BITS_LNKCAP_100MB BIT_9 #define Q8_PORT_CFG_BITS_LNKCAP_1GB BIT_10 #define Q8_PORT_CFG_BITS_LNKCAP_10GB BIT_11 #define Q8_PORT_CFG_BITS_AUTONEG BIT_15 #define Q8_PORT_CFG_BITS_XMT_DISABLE BIT_17 #define Q8_PORT_CFG_BITS_FEC_RQSTD BIT_18 #define Q8_PORT_CFG_BITS_EEE_RQSTD BIT_19 #define Q8_PORT_CFG_BITS_STDPAUSE_DIR_MASK (0x3 << 20) #define Q8_PORT_CFG_BITS_STDPAUSE_XMT_RCV (0x0 << 20) #define Q8_PORT_CFG_BITS_STDPAUSE_XMT (0x1 << 20) #define Q8_PORT_CFG_BITS_STDPAUSE_RCV (0x2 << 20) } __packed q80_set_port_cfg_t; typedef struct _q80_set_port_cfg_rsp { uint16_t opcode; uint16_t regcnt_status; } __packed q80_set_port_cfg_rsp_t; /* * Get Port Configuration Command */ typedef struct _q80_get_port_cfg { uint16_t opcode; uint16_t count_version; } __packed q80_get_port_cfg_t; typedef struct _q80_get_port_cfg_rsp { uint16_t opcode; uint16_t regcnt_status; uint32_t cfg_bits; /* same as in q80_set_port_cfg_t */ uint8_t phys_port_type; uint8_t rsvd[3]; } __packed q80_get_port_cfg_rsp_t; /* * Get Link Status Command * Used to get current PAUSE values for the port */ typedef struct _q80_get_link_status { uint16_t opcode; uint16_t count_version; } __packed q80_get_link_status_t; typedef struct _q80_get_link_status_rsp { uint16_t opcode; uint16_t regcnt_status; uint32_t cfg_bits; #define Q8_GET_LINK_STAT_CFG_BITS_LINK_UP BIT_0 #define Q8_GET_LINK_STAT_CFG_BITS_LINK_SPEED_MASK (0x7 << 3) #define Q8_GET_LINK_STAT_CFG_BITS_LINK_SPEED_UNKNOWN (0x0 << 3) #define Q8_GET_LINK_STAT_CFG_BITS_LINK_SPEED_10MB (0x1 << 3) #define Q8_GET_LINK_STAT_CFG_BITS_LINK_SPEED_100MB (0x2 << 3) #define Q8_GET_LINK_STAT_CFG_BITS_LINK_SPEED_1GB (0x3 << 3) #define Q8_GET_LINK_STAT_CFG_BITS_LINK_SPEED_10GB (0x4 << 3) #define Q8_GET_LINK_STAT_CFG_BITS_PAUSE_CFG_MASK (0x3 << 6) #define Q8_GET_LINK_STAT_CFG_BITS_PAUSE_CFG_DISABLE (0x0 << 6) #define Q8_GET_LINK_STAT_CFG_BITS_PAUSE_CFG_STD (0x1 << 6) #define Q8_GET_LINK_STAT_CFG_BITS_PAUSE_CFG_PPM (0x2 << 6) #define Q8_GET_LINK_STAT_CFG_BITS_LOOPBACK_MASK (0x7 << 8) #define Q8_GET_LINK_STAT_CFG_BITS_LOOPBACK_NONE (0x0 << 6) #define Q8_GET_LINK_STAT_CFG_BITS_LOOPBACK_HSS (0x2 << 6) #define Q8_GET_LINK_STAT_CFG_BITS_LOOPBACK_PHY (0x3 << 6) #define Q8_GET_LINK_STAT_CFG_BITS_FEC_ENABLED BIT_12 #define Q8_GET_LINK_STAT_CFG_BITS_EEE_ENABLED BIT_13 #define Q8_GET_LINK_STAT_CFG_BITS_STDPAUSE_DIR_MASK (0x3 << 20) #define Q8_GET_LINK_STAT_CFG_BITS_STDPAUSE_NONE (0x0 << 20) #define Q8_GET_LINK_STAT_CFG_BITS_STDPAUSE_XMT (0x1 << 20) #define Q8_GET_LINK_STAT_CFG_BITS_STDPAUSE_RCV (0x2 << 20) #define Q8_GET_LINK_STAT_CFG_BITS_STDPAUSE_XMT_RCV (0x3 << 20) uint32_t link_state; #define Q8_GET_LINK_STAT_LOSS_OF_SIGNAL BIT_0 #define Q8_GET_LINK_STAT_PORT_RST_DONE BIT_3 #define Q8_GET_LINK_STAT_PHY_LINK_DOWN BIT_4 #define Q8_GET_LINK_STAT_PCS_LINK_DOWN BIT_5 #define Q8_GET_LINK_STAT_MAC_LOCAL_FAULT BIT_6 #define Q8_GET_LINK_STAT_MAC_REMOTE_FAULT BIT_7 #define Q8_GET_LINK_STAT_XMT_DISABLED BIT_9 #define Q8_GET_LINK_STAT_SFP_XMT_FAULT BIT_10 uint32_t sfp_info; #define Q8_GET_LINK_STAT_SFP_TRNCVR_MASK 0x3 #define Q8_GET_LINK_STAT_SFP_TRNCVR_NOT_EXPECTED 0x0 #define Q8_GET_LINK_STAT_SFP_TRNCVR_NONE 0x1 #define Q8_GET_LINK_STAT_SFP_TRNCVR_INVALID 0x2 #define Q8_GET_LINK_STAT_SFP_TRNCVR_VALID 0x3 #define Q8_GET_LINK_STAT_SFP_ADDTL_INFO_MASK (0x3 << 2) #define Q8_GET_LINK_STAT_SFP_ADDTL_INFO_UNREC_TRSVR (0x0 << 2) #define Q8_GET_LINK_STAT_SFP_ADDTL_INFO_NOT_QLOGIC (0x1 << 2) #define Q8_GET_LINK_STAT_SFP_ADDTL_INFO_SPEED_FAILED (0x2 << 2) #define Q8_GET_LINK_STAT_SFP_ADDTL_INFO_ACCESS_ERROR (0x3 << 2) #define Q8_GET_LINK_STAT_SFP_MOD_TYPE_MASK (0x1F << 4) #define Q8_GET_LINK_STAT_SFP_MOD_NONE (0x00 << 4) #define Q8_GET_LINK_STAT_SFP_MOD_10GBLRM (0x01 << 4) #define Q8_GET_LINK_STAT_SFP_MOD_10GBLR (0x02 << 4) #define Q8_GET_LINK_STAT_SFP_MOD_10GBSR (0x03 << 4) #define Q8_GET_LINK_STAT_SFP_MOD_10GBC_P (0x04 << 4) #define Q8_GET_LINK_STAT_SFP_MOD_10GBC_AL (0x05 << 4) #define Q8_GET_LINK_STAT_SFP_MOD_10GBC_PL (0x06 << 4) #define Q8_GET_LINK_STAT_SFP_MOD_1GBSX (0x07 << 4) #define Q8_GET_LINK_STAT_SFP_MOD_1GBLX (0x08 << 4) #define Q8_GET_LINK_STAT_SFP_MOD_1GBCX (0x09 << 4) #define Q8_GET_LINK_STAT_SFP_MOD_1GBT (0x0A << 4) #define Q8_GET_LINK_STAT_SFP_MOD_1GBC_PL (0x0B << 4) #define Q8_GET_LINK_STAT_SFP_MOD_UNKNOWN (0x0F << 4) #define Q8_GET_LINK_STAT_SFP_MULTI_RATE_MOD BIT_9 #define Q8_GET_LINK_STAT_SFP_XMT_FAULT BIT_10 #define Q8_GET_LINK_STAT_SFP_COPPER_CBL_LENGTH_MASK (0xFF << 16) } __packed q80_get_link_status_rsp_t; /* * Transmit Related Definitions */ /* Max# of TX Rings per Tx Create Cntxt Mbx Cmd*/ #define MAX_TCNTXT_RINGS 8 /* * Transmit Context - Q8_CMD_CREATE_TX_CNTXT Command Configuration Data */ typedef struct _q80_rq_tx_ring { uint64_t paddr; uint64_t tx_consumer; uint16_t nentries; uint16_t intr_id; uint8_t intr_src_bit; uint8_t rsrvd[3]; } __packed q80_rq_tx_ring_t; typedef struct _q80_rq_tx_cntxt { uint16_t opcode; uint16_t count_version; uint32_t cap0; #define Q8_TX_CNTXT_CAP0_BASEFW (1 << 0) #define Q8_TX_CNTXT_CAP0_LSO (1 << 6) #define Q8_TX_CNTXT_CAP0_TC (1 << 25) uint32_t cap1; uint32_t cap2; uint32_t cap3; uint8_t ntx_rings; uint8_t traffic_class; /* bits 8-10; others reserved */ uint16_t tx_vpid; q80_rq_tx_ring_t tx_ring[MAX_TCNTXT_RINGS]; } __packed q80_rq_tx_cntxt_t; typedef struct _q80_rsp_tx_ring { uint32_t prod_index; uint16_t cntxt_id; uint8_t state; uint8_t rsrvd; } q80_rsp_tx_ring_t; typedef struct _q80_rsp_tx_cntxt { uint16_t opcode; uint16_t regcnt_status; uint8_t ntx_rings; uint8_t phy_port; uint8_t virt_port; uint8_t rsrvd; q80_rsp_tx_ring_t tx_ring[MAX_TCNTXT_RINGS]; } __packed q80_rsp_tx_cntxt_t; typedef struct _q80_tx_cntxt_destroy { uint16_t opcode; uint16_t count_version; uint32_t cntxt_id; } __packed q80_tx_cntxt_destroy_t; typedef struct _q80_tx_cntxt_destroy_rsp { uint16_t opcode; uint16_t regcnt_status; } __packed q80_tx_cntxt_destroy_rsp_t; /* * Transmit Command Descriptor * These commands are issued on the Transmit Ring associated with a Transmit * context */ typedef struct _q80_tx_cmd { uint8_t tcp_hdr_off; /* TCP Header Offset */ uint8_t ip_hdr_off; /* IP Header Offset */ uint16_t flags_opcode; /* Bits 0-6: flags; 7-12: opcode */ /* flags field */ #define Q8_TX_CMD_FLAGS_MULTICAST 0x01 #define Q8_TX_CMD_FLAGS_LSO_TSO 0x02 #define Q8_TX_CMD_FLAGS_VLAN_TAGGED 0x10 #define Q8_TX_CMD_FLAGS_HW_VLAN_ID 0x40 /* opcode field */ #define Q8_TX_CMD_OP_XMT_UDP_CHKSUM_IPV6 (0xC << 7) #define Q8_TX_CMD_OP_XMT_TCP_CHKSUM_IPV6 (0xB << 7) #define Q8_TX_CMD_OP_XMT_TCP_LSO_IPV6 (0x6 << 7) #define Q8_TX_CMD_OP_XMT_TCP_LSO (0x5 << 7) #define Q8_TX_CMD_OP_XMT_UDP_CHKSUM (0x3 << 7) #define Q8_TX_CMD_OP_XMT_TCP_CHKSUM (0x2 << 7) #define Q8_TX_CMD_OP_XMT_ETHER (0x1 << 7) uint8_t n_bufs; /* # of data segs in data buffer */ uint8_t data_len_lo; /* data length lower 8 bits */ uint16_t data_len_hi; /* data length upper 16 bits */ uint64_t buf2_addr; /* buffer 2 address */ uint16_t rsrvd0; uint16_t mss; /* MSS for this packet */ uint8_t cntxtid; /* Bits 7-4: ContextId; 3-0: reserved */ #define Q8_TX_CMD_PORT_CNXTID(c_id) ((c_id & 0xF) << 4) uint8_t total_hdr_len; /* MAC+IP+TCP Header Length for LSO */ uint16_t rsrvd1; uint64_t buf3_addr; /* buffer 3 address */ uint64_t buf1_addr; /* buffer 1 address */ uint16_t buf1_len; /* length of buffer 1 */ uint16_t buf2_len; /* length of buffer 2 */ uint16_t buf3_len; /* length of buffer 3 */ uint16_t buf4_len; /* length of buffer 4 */ uint64_t buf4_addr; /* buffer 4 address */ uint32_t rsrvd2; uint16_t rsrvd3; uint16_t vlan_tci; /* VLAN TCI when hw tagging is enabled*/ } __packed q80_tx_cmd_t; /* 64 bytes */ #define Q8_TX_CMD_MAX_SEGMENTS 4 #define Q8_TX_CMD_TSO_ALIGN 2 #define Q8_TX_MAX_NON_TSO_SEGS 62 /* * Receive Related Definitions */ #define MAX_RDS_RING_SETS 8 /* Max# of Receive Descriptor Rings */ #ifdef QL_ENABLE_ISCSI_TLV #define MAX_SDS_RINGS 32 /* Max# of Status Descriptor Rings */ #define NUM_TX_RINGS (MAX_SDS_RINGS * 2) #else #define MAX_SDS_RINGS 32 /* Max# of Status Descriptor Rings */ #define NUM_TX_RINGS MAX_SDS_RINGS #endif /* #ifdef QL_ENABLE_ISCSI_TLV */ #define MAX_RDS_RINGS MAX_SDS_RINGS /* Max# of Rcv Descriptor Rings */ typedef struct _q80_rq_sds_ring { uint64_t paddr; /* physical addr of status ring in system memory */ uint64_t hdr_split1; uint64_t hdr_split2; uint16_t size; /* number of entries in status ring */ uint16_t hdr_split1_size; uint16_t hdr_split2_size; uint16_t hdr_split_count; uint16_t intr_id; uint8_t intr_src_bit; uint8_t rsrvd[5]; } __packed q80_rq_sds_ring_t; /* 10 32bit words */ typedef struct _q80_rq_rds_ring { uint64_t paddr_std; /* physical addr of rcv ring in system memory */ uint64_t paddr_jumbo; /* physical addr of rcv ring in system memory */ uint16_t std_bsize; uint16_t std_nentries; uint16_t jumbo_bsize; uint16_t jumbo_nentries; } __packed q80_rq_rds_ring_t; /* 6 32bit words */ #define MAX_RCNTXT_SDS_RINGS 8 typedef struct _q80_rq_rcv_cntxt { uint16_t opcode; uint16_t count_version; uint32_t cap0; #define Q8_RCV_CNTXT_CAP0_BASEFW (1 << 0) #define Q8_RCV_CNTXT_CAP0_MULTI_RDS (1 << 1) #define Q8_RCV_CNTXT_CAP0_LRO (1 << 5) #define Q8_RCV_CNTXT_CAP0_HW_LRO (1 << 10) #define Q8_RCV_CNTXT_CAP0_VLAN_ALIGN (1 << 14) #define Q8_RCV_CNTXT_CAP0_RSS (1 << 15) #define Q8_RCV_CNTXT_CAP0_MSFT_RSS (1 << 16) #define Q8_RCV_CNTXT_CAP0_SGL_JUMBO (1 << 18) #define Q8_RCV_CNTXT_CAP0_SGL_LRO (1 << 19) #define Q8_RCV_CNTXT_CAP0_SINGLE_JUMBO (1 << 26) uint32_t cap1; uint32_t cap2; uint32_t cap3; uint8_t nrds_sets_rings; uint8_t nsds_rings; uint16_t rds_producer_mode; #define Q8_RCV_CNTXT_RDS_PROD_MODE_UNIQUE 0 #define Q8_RCV_CNTXT_RDS_PROD_MODE_SHARED 1 uint16_t rcv_vpid; uint16_t rsrvd0; uint32_t rsrvd1; q80_rq_sds_ring_t sds[MAX_RCNTXT_SDS_RINGS]; q80_rq_rds_ring_t rds[MAX_RDS_RING_SETS]; } __packed q80_rq_rcv_cntxt_t; typedef struct _q80_rsp_rds_ring { uint32_t prod_std; uint32_t prod_jumbo; } __packed q80_rsp_rds_ring_t; /* 8 bytes */ typedef struct _q80_rsp_rcv_cntxt { uint16_t opcode; uint16_t regcnt_status; uint8_t nrds_sets_rings; uint8_t nsds_rings; uint16_t cntxt_id; uint8_t state; uint8_t num_funcs; uint8_t phy_port; uint8_t virt_port; uint32_t sds_cons[MAX_RCNTXT_SDS_RINGS]; q80_rsp_rds_ring_t rds[MAX_RDS_RING_SETS]; } __packed q80_rsp_rcv_cntxt_t; typedef struct _q80_rcv_cntxt_destroy { uint16_t opcode; uint16_t count_version; uint32_t cntxt_id; } __packed q80_rcv_cntxt_destroy_t; typedef struct _q80_rcv_cntxt_destroy_rsp { uint16_t opcode; uint16_t regcnt_status; } __packed q80_rcv_cntxt_destroy_rsp_t; /* * Add Receive Rings */ typedef struct _q80_rq_add_rcv_rings { uint16_t opcode; uint16_t count_version; uint8_t nrds_sets_rings; uint8_t nsds_rings; uint16_t cntxt_id; q80_rq_sds_ring_t sds[MAX_RCNTXT_SDS_RINGS]; q80_rq_rds_ring_t rds[MAX_RDS_RING_SETS]; } __packed q80_rq_add_rcv_rings_t; typedef struct _q80_rsp_add_rcv_rings { uint16_t opcode; uint16_t regcnt_status; uint8_t nrds_sets_rings; uint8_t nsds_rings; uint16_t cntxt_id; uint32_t sds_cons[MAX_RCNTXT_SDS_RINGS]; q80_rsp_rds_ring_t rds[MAX_RDS_RING_SETS]; } __packed q80_rsp_add_rcv_rings_t; /* * Map Status Ring to Receive Descriptor Set */ #define MAX_SDS_TO_RDS_MAP 16 typedef struct _q80_sds_rds_map_e { uint8_t sds_ring; uint8_t rsrvd0; uint8_t rds_ring; uint8_t rsrvd1; } __packed q80_sds_rds_map_e_t; typedef struct _q80_rq_map_sds_to_rds { uint16_t opcode; uint16_t count_version; uint16_t cntxt_id; uint16_t num_rings; q80_sds_rds_map_e_t sds_rds[MAX_SDS_TO_RDS_MAP]; } __packed q80_rq_map_sds_to_rds_t; typedef struct _q80_rsp_map_sds_to_rds { uint16_t opcode; uint16_t regcnt_status; uint16_t cntxt_id; uint16_t num_rings; q80_sds_rds_map_e_t sds_rds[MAX_SDS_TO_RDS_MAP]; } __packed q80_rsp_map_sds_to_rds_t; /* * Receive Descriptor corresponding to each entry in the receive ring */ typedef struct _q80_rcv_desc { uint16_t handle; uint16_t rsrvd; uint32_t buf_size; /* buffer size in bytes */ uint64_t buf_addr; /* physical address of buffer */ } __packed q80_recv_desc_t; /* * Status Descriptor corresponding to each entry in the Status ring */ typedef struct _q80_stat_desc { uint64_t data[2]; } __packed q80_stat_desc_t; /* * definitions for data[0] field of Status Descriptor */ #define Q8_STAT_DESC_RSS_HASH(data) (data & 0xFFFFFFFF) #define Q8_STAT_DESC_TOTAL_LENGTH(data) ((data >> 32) & 0x3FFF) #define Q8_STAT_DESC_TOTAL_LENGTH_SGL_RCV(data) ((data >> 32) & 0xFFFF) #define Q8_STAT_DESC_HANDLE(data) ((data >> 48) & 0xFFFF) /* * definitions for data[1] field of Status Descriptor */ #define Q8_STAT_DESC_OPCODE(data) ((data >> 42) & 0xF) #define Q8_STAT_DESC_OPCODE_RCV_PKT 0x01 #define Q8_STAT_DESC_OPCODE_LRO_PKT 0x02 #define Q8_STAT_DESC_OPCODE_SGL_LRO 0x04 #define Q8_STAT_DESC_OPCODE_SGL_RCV 0x05 #define Q8_STAT_DESC_OPCODE_CONT 0x06 /* * definitions for data[1] field of Status Descriptor for standard frames * status descriptor opcode equals 0x04 */ #define Q8_STAT_DESC_STATUS(data) ((data >> 39) & 0x0007) #define Q8_STAT_DESC_STATUS_CHKSUM_NOT_DONE 0x00 #define Q8_STAT_DESC_STATUS_NO_CHKSUM 0x01 #define Q8_STAT_DESC_STATUS_CHKSUM_OK 0x02 #define Q8_STAT_DESC_STATUS_CHKSUM_ERR 0x03 #define Q8_STAT_DESC_VLAN(data) ((data >> 47) & 1) #define Q8_STAT_DESC_VLAN_ID(data) ((data >> 48) & 0xFFFF) #define Q8_STAT_DESC_PROTOCOL(data) ((data >> 44) & 0x000F) #define Q8_STAT_DESC_L2_OFFSET(data) ((data >> 48) & 0x001F) #define Q8_STAT_DESC_COUNT(data) ((data >> 37) & 0x0007) /* * definitions for data[0-1] fields of Status Descriptor for LRO * status descriptor opcode equals 0x04 */ /* definitions for data[1] field */ #define Q8_LRO_STAT_DESC_SEQ_NUM(data) (uint32_t)(data) /* * definitions specific to opcode 0x04 data[1] */ #define Q8_STAT_DESC_COUNT_SGL_LRO(data) ((data >> 13) & 0x0007) #define Q8_SGL_LRO_STAT_L2_OFFSET(data) ((data >> 16) & 0xFF) #define Q8_SGL_LRO_STAT_L4_OFFSET(data) ((data >> 24) & 0xFF) #define Q8_SGL_LRO_STAT_TS(data) ((data >> 40) & 0x1) #define Q8_SGL_LRO_STAT_PUSH_BIT(data) ((data >> 41) & 0x1) /* * definitions specific to opcode 0x05 data[1] */ #define Q8_STAT_DESC_COUNT_SGL_RCV(data) ((data >> 37) & 0x0003) /* * definitions for opcode 0x06 */ /* definitions for data[0] field */ #define Q8_SGL_STAT_DESC_HANDLE1(data) (data & 0xFFFF) #define Q8_SGL_STAT_DESC_HANDLE2(data) ((data >> 16) & 0xFFFF) #define Q8_SGL_STAT_DESC_HANDLE3(data) ((data >> 32) & 0xFFFF) #define Q8_SGL_STAT_DESC_HANDLE4(data) ((data >> 48) & 0xFFFF) /* definitions for data[1] field */ #define Q8_SGL_STAT_DESC_HANDLE5(data) (data & 0xFFFF) #define Q8_SGL_STAT_DESC_HANDLE6(data) ((data >> 16) & 0xFFFF) #define Q8_SGL_STAT_DESC_NUM_HANDLES(data) ((data >> 32) & 0x7) #define Q8_SGL_STAT_DESC_HANDLE7(data) ((data >> 48) & 0xFFFF) /** Driver Related Definitions Begin **/ #define TX_SMALL_PKT_SIZE 128 /* size in bytes of small packets */ /* The number of descriptors should be a power of 2 */ #define NUM_TX_DESCRIPTORS 1024 #define NUM_STATUS_DESCRIPTORS 1024 #define NUM_RX_DESCRIPTORS 2048 /* * structure describing various dma buffers */ typedef struct qla_dmabuf { volatile struct { uint32_t tx_ring :1, rds_ring :1, sds_ring :1, minidump :1; } flags; qla_dma_t tx_ring; qla_dma_t rds_ring[MAX_RDS_RINGS]; qla_dma_t sds_ring[MAX_SDS_RINGS]; qla_dma_t minidump; } qla_dmabuf_t; typedef struct _qla_sds { q80_stat_desc_t *sds_ring_base; /* start of sds ring */ uint32_t sdsr_next; /* next entry in SDS ring to process */ struct lro_ctrl lro; void *rxb_free; uint32_t rx_free; volatile uint32_t rcv_active; uint32_t sds_consumer; uint64_t intr_count; uint64_t spurious_intr_count; } qla_sds_t; #define Q8_MAX_LRO_CONT_DESC 7 #define Q8_MAX_HANDLES_LRO (1 + (Q8_MAX_LRO_CONT_DESC * 7)) #define Q8_MAX_HANDLES_NON_LRO 8 typedef struct _qla_sgl_rcv { uint16_t pkt_length; uint16_t num_handles; uint16_t chksum_status; uint32_t rss_hash; uint16_t rss_hash_flags; uint16_t vlan_tag; uint16_t handle[Q8_MAX_HANDLES_NON_LRO]; } qla_sgl_rcv_t; typedef struct _qla_sgl_lro { uint16_t flags; #define Q8_LRO_COMP_TS 0x1 #define Q8_LRO_COMP_PUSH_BIT 0x2 uint16_t l2_offset; uint16_t l4_offset; uint16_t payload_length; uint16_t num_handles; uint32_t rss_hash; uint16_t rss_hash_flags; uint16_t vlan_tag; uint16_t handle[Q8_MAX_HANDLES_LRO]; } qla_sgl_lro_t; typedef union { qla_sgl_rcv_t rcv; qla_sgl_lro_t lro; } qla_sgl_comp_t; #define QL_FRAME_HDR_SIZE (ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN +\ sizeof (struct ip6_hdr) + sizeof (struct tcphdr) + 16) typedef struct _qla_hw_tx_cntxt { q80_tx_cmd_t *tx_ring_base; bus_addr_t tx_ring_paddr; volatile uint32_t *tx_cons; /* tx consumer shadow reg */ bus_addr_t tx_cons_paddr; volatile uint32_t txr_free; /* # of free entries in tx ring */ volatile uint32_t txr_next; /* # next available tx ring entry */ volatile uint32_t txr_comp; /* index of last tx entry completed */ uint32_t tx_prod_reg; uint16_t tx_cntxt_id; } qla_hw_tx_cntxt_t; typedef struct _qla_mcast { uint16_t rsrvd; uint8_t addr[ETHER_ADDR_LEN]; } __packed qla_mcast_t; typedef struct _qla_rdesc { volatile uint32_t prod_std; volatile uint32_t prod_jumbo; volatile uint32_t rx_next; /* next standard rcv ring to arm fw */ volatile int32_t rx_in; /* next standard rcv ring to add mbufs */ uint64_t count; uint64_t lro_pkt_count; uint64_t lro_bytes; } qla_rdesc_t; typedef struct _qla_flash_desc_table { uint32_t flash_valid; uint16_t flash_ver; uint16_t flash_len; uint16_t flash_cksum; uint16_t flash_unused; uint8_t flash_model[16]; uint16_t flash_manuf; uint16_t flash_id; uint8_t flash_flag; uint8_t erase_cmd; uint8_t alt_erase_cmd; uint8_t write_enable_cmd; uint8_t write_enable_bits; uint8_t write_statusreg_cmd; uint8_t unprotected_sec_cmd; uint8_t read_manuf_cmd; uint32_t block_size; uint32_t alt_block_size; uint32_t flash_size; uint32_t write_enable_data; uint8_t readid_addr_len; uint8_t write_disable_bits; uint8_t read_dev_id_len; uint8_t chip_erase_cmd; uint16_t read_timeo; uint8_t protected_sec_cmd; uint8_t resvd[65]; } __packed qla_flash_desc_table_t; /* * struct for storing hardware specific information for a given interface */ typedef struct _qla_hw { struct { uint32_t unicast_mac :1, bcast_mac :1, loopback_mode :2, init_tx_cnxt :1, init_rx_cnxt :1, init_intr_cnxt :1, fduplex :1, autoneg :1, fdt_valid :1; } flags; uint16_t link_speed; uint16_t cable_length; uint32_t cable_oui; uint8_t link_up; uint8_t module_type; uint8_t link_faults; uint8_t mac_rcv_mode; uint32_t max_mtu; uint8_t mac_addr[ETHER_ADDR_LEN]; uint32_t num_sds_rings; uint32_t num_rds_rings; uint32_t num_tx_rings; qla_dmabuf_t dma_buf; /* Transmit Side */ qla_hw_tx_cntxt_t tx_cntxt[NUM_TX_RINGS]; /* Receive Side */ uint16_t rcv_cntxt_id; uint32_t mbx_intr_mask_offset; uint16_t intr_id[MAX_SDS_RINGS]; uint32_t intr_src[MAX_SDS_RINGS]; qla_sds_t sds[MAX_SDS_RINGS]; uint32_t mbox[Q8_NUM_MBOX]; qla_rdesc_t rds[MAX_RDS_RINGS]; uint32_t rds_pidx_thres; uint32_t sds_cidx_thres; uint32_t rcv_intr_coalesce; uint32_t xmt_intr_coalesce; /* Immediate Completion */ volatile uint32_t imd_compl; volatile uint32_t aen_mb0; volatile uint32_t aen_mb1; volatile uint32_t aen_mb2; volatile uint32_t aen_mb3; volatile uint32_t aen_mb4; /* multicast address list */ uint32_t nmcast; qla_mcast_t mcast[Q8_MAX_NUM_MULTICAST_ADDRS]; uint8_t mac_addr_arr[(Q8_MAX_MAC_ADDRS * ETHER_ADDR_LEN)]; /* reset sequence */ #define Q8_MAX_RESET_SEQ_IDX 16 uint32_t rst_seq[Q8_MAX_RESET_SEQ_IDX]; uint32_t rst_seq_idx; /* heart beat register value */ uint32_t hbeat_value; uint32_t health_count; uint32_t hbeat_failure; uint32_t max_tx_segs; uint32_t min_lro_pkt_size; uint32_t enable_hw_lro; uint32_t enable_soft_lro; uint32_t enable_9kb; uint32_t user_pri_nic; uint32_t user_pri_iscsi; /* Flash Descriptor Table */ qla_flash_desc_table_t fdt; /* stats */ q80_mac_stats_t mac; q80_rcv_stats_t rcv; q80_xmt_stats_t xmt[NUM_TX_RINGS]; /* Minidump Related */ uint32_t mdump_init; uint32_t mdump_done; uint32_t mdump_active; uint32_t mdump_capture_mask; uint32_t mdump_start_seq_index; void *mdump_buffer; uint32_t mdump_buffer_size; void *mdump_template; uint32_t mdump_template_size; + + /* driver state related */ + void *drvr_state; } qla_hw_t; #define QL_UPDATE_RDS_PRODUCER_INDEX(ha, prod_reg, val) \ bus_write_4((ha->pci_reg), prod_reg, val); #define QL_UPDATE_TX_PRODUCER_INDEX(ha, val, i) \ WRITE_REG32(ha, ha->hw.tx_cntxt[i].tx_prod_reg, val) #define QL_UPDATE_SDS_CONSUMER_INDEX(ha, i, val) \ bus_write_4((ha->pci_reg), (ha->hw.sds[i].sds_consumer), val); #define QL_ENABLE_INTERRUPTS(ha, i) \ bus_write_4((ha->pci_reg), (ha->hw.intr_src[i]), 0); #define QL_BUFFER_ALIGN 16 /* * Flash Configuration */ #define Q8_BOARD_CONFIG_OFFSET 0x370000 #define Q8_BOARD_CONFIG_LENGTH 0x2000 #define Q8_BOARD_CONFIG_MAC0_LO 0x400 #define Q8_FDT_LOCK_MAGIC_ID 0x00FD00FD #define Q8_FDT_FLASH_ADDR_VAL 0xFD009F #define Q8_FDT_FLASH_CTRL_VAL 0x3F #define Q8_FDT_MASK_VAL 0xFF #define Q8_WR_ENABLE_FL_ADDR 0xFD0100 #define Q8_WR_ENABLE_FL_CTRL 0x5 #define Q8_ERASE_LOCK_MAGIC_ID 0x00EF00EF #define Q8_ERASE_FL_ADDR_MASK 0xFD0300 #define Q8_ERASE_FL_CTRL_MASK 0x3D #define Q8_WR_FL_LOCK_MAGIC_ID 0xABCDABCD #define Q8_WR_FL_ADDR_MASK 0x800000 #define Q8_WR_FL_CTRL_MASK 0x3D #define QL_FDT_OFFSET 0x3F0000 #define Q8_FLASH_SECTOR_SIZE 0x10000 /* * Off Chip Memory Access */ typedef struct _q80_offchip_mem_val { uint32_t data_lo; uint32_t data_hi; uint32_t data_ulo; uint32_t data_uhi; } q80_offchip_mem_val_t; #endif /* #ifndef _QL_HW_H_ */ Index: stable/11/sys/dev/qlxgbe/ql_ioctl.c =================================================================== --- stable/11/sys/dev/qlxgbe/ql_ioctl.c (revision 324761) +++ stable/11/sys/dev/qlxgbe/ql_ioctl.c (revision 324762) @@ -1,297 +1,525 @@ /* * Copyright (c) 2013-2016 Qlogic Corporation * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE * POSSIBILITY OF SUCH DAMAGE. */ /* * File: ql_ioctl.c * Author : David C Somayajulu, Qlogic Corporation, Aliso Viejo, CA 92656. */ #include __FBSDID("$FreeBSD$"); #include "ql_os.h" #include "ql_hw.h" #include "ql_def.h" #include "ql_inline.h" #include "ql_glbl.h" #include "ql_ioctl.h" +#include "ql_ver.h" +#include "ql_dbg.h" +static int ql_drvr_state(qla_host_t *ha, qla_driver_state_t *drvr_state); +static uint32_t ql_drvr_state_size(qla_host_t *ha); static int ql_eioctl(struct cdev *dev, u_long cmd, caddr_t data, int fflag, struct thread *td); static struct cdevsw qla_cdevsw = { .d_version = D_VERSION, .d_ioctl = ql_eioctl, .d_name = "qlcnic", }; int ql_make_cdev(qla_host_t *ha) { ha->ioctl_dev = make_dev(&qla_cdevsw, ha->ifp->if_dunit, UID_ROOT, GID_WHEEL, 0600, "%s", if_name(ha->ifp)); if (ha->ioctl_dev == NULL) return (-1); ha->ioctl_dev->si_drv1 = ha; return (0); } void ql_del_cdev(qla_host_t *ha) { if (ha->ioctl_dev != NULL) destroy_dev(ha->ioctl_dev); return; } static int ql_eioctl(struct cdev *dev, u_long cmd, caddr_t data, int fflag, struct thread *td) { qla_host_t *ha; int rval = 0; device_t pci_dev; struct ifnet *ifp; int count; q80_offchip_mem_val_t val; qla_rd_pci_ids_t *pci_ids; qla_rd_fw_dump_t *fw_dump; union { qla_reg_val_t *rv; qla_rd_flash_t *rdf; qla_wr_flash_t *wrf; qla_erase_flash_t *erf; qla_offchip_mem_val_t *mem; } u; if ((ha = (qla_host_t *)dev->si_drv1) == NULL) return ENXIO; pci_dev= ha->pci_dev; switch(cmd) { case QLA_RDWR_REG: u.rv = (qla_reg_val_t *)data; if (u.rv->direct) { if (u.rv->rd) { u.rv->val = READ_REG32(ha, u.rv->reg); } else { WRITE_REG32(ha, u.rv->reg, u.rv->val); } } else { if ((rval = ql_rdwr_indreg32(ha, u.rv->reg, &u.rv->val, u.rv->rd))) rval = ENXIO; } break; case QLA_RD_FLASH: if (!ha->hw.flags.fdt_valid) { rval = EIO; break; } u.rdf = (qla_rd_flash_t *)data; if ((rval = ql_rd_flash32(ha, u.rdf->off, &u.rdf->data))) rval = ENXIO; break; case QLA_WR_FLASH: ifp = ha->ifp; if (ifp == NULL) { rval = ENXIO; break; } if (ifp->if_drv_flags & IFF_DRV_RUNNING) { rval = ENXIO; break; } if (!ha->hw.flags.fdt_valid) { rval = EIO; break; } u.wrf = (qla_wr_flash_t *)data; if ((rval = ql_wr_flash_buffer(ha, u.wrf->off, u.wrf->size, u.wrf->buffer))) { printf("flash write failed[%d]\n", rval); rval = ENXIO; } break; case QLA_ERASE_FLASH: ifp = ha->ifp; if (ifp == NULL) { rval = ENXIO; break; } if (ifp->if_drv_flags & IFF_DRV_RUNNING) { rval = ENXIO; break; } if (!ha->hw.flags.fdt_valid) { rval = EIO; break; } u.erf = (qla_erase_flash_t *)data; if ((rval = ql_erase_flash(ha, u.erf->off, u.erf->size))) { printf("flash erase failed[%d]\n", rval); rval = ENXIO; } break; case QLA_RDWR_MS_MEM: u.mem = (qla_offchip_mem_val_t *)data; if ((rval = ql_rdwr_offchip_mem(ha, u.mem->off, &val, u.mem->rd))) rval = ENXIO; else { u.mem->data_lo = val.data_lo; u.mem->data_hi = val.data_hi; u.mem->data_ulo = val.data_ulo; u.mem->data_uhi = val.data_uhi; } break; case QLA_RD_FW_DUMP_SIZE: if (ha->hw.mdump_init == 0) { rval = EINVAL; break; } fw_dump = (qla_rd_fw_dump_t *)data; fw_dump->minidump_size = ha->hw.mdump_buffer_size + ha->hw.mdump_template_size; fw_dump->pci_func = ha->pci_func; break; case QLA_RD_FW_DUMP: if (ha->hw.mdump_init == 0) { rval = EINVAL; break; } fw_dump = (qla_rd_fw_dump_t *)data; if ((fw_dump->minidump == NULL) || (fw_dump->minidump_size != (ha->hw.mdump_buffer_size + ha->hw.mdump_template_size))) { rval = EINVAL; break; } if (QLA_LOCK(ha, __func__, QLA_LOCK_DEFAULT_MS_TIMEOUT, 0) == 0) { if (!ha->hw.mdump_done) ha->qla_initiate_recovery = 1; QLA_UNLOCK(ha, __func__); } else { rval = ENXIO; break; } #define QLNX_DUMP_WAIT_SECS 30 count = QLNX_DUMP_WAIT_SECS * 1000; while (count) { if (ha->hw.mdump_done) break; qla_mdelay(__func__, 100); count -= 100; } if (!ha->hw.mdump_done) { rval = ENXIO; break; } if (QLA_LOCK(ha, __func__, QLA_LOCK_DEFAULT_MS_TIMEOUT, 0) == 0) { ha->hw.mdump_done = 0; QLA_UNLOCK(ha, __func__); } else { rval = ENXIO; break; } if ((rval = copyout(ha->hw.mdump_template, fw_dump->minidump, ha->hw.mdump_template_size))) { rval = ENXIO; break; } if ((rval = copyout(ha->hw.mdump_buffer, ((uint8_t *)fw_dump->minidump + ha->hw.mdump_template_size), ha->hw.mdump_buffer_size))) rval = ENXIO; break; + case QLA_RD_DRVR_STATE: + rval = ql_drvr_state(ha, (qla_driver_state_t *)data); + break; + case QLA_RD_PCI_IDS: pci_ids = (qla_rd_pci_ids_t *)data; pci_ids->ven_id = pci_get_vendor(pci_dev); pci_ids->dev_id = pci_get_device(pci_dev); pci_ids->subsys_ven_id = pci_get_subvendor(pci_dev); pci_ids->subsys_dev_id = pci_get_subdevice(pci_dev); pci_ids->rev_id = pci_read_config(pci_dev, PCIR_REVID, 1); break; default: break; } return rval; +} + + +static int +ql_drvr_state(qla_host_t *ha, qla_driver_state_t *state) +{ + int rval = 0; + uint32_t drvr_state_size; + qla_drvr_state_hdr_t *hdr; + + drvr_state_size = ql_drvr_state_size(ha); + + if (state->buffer == NULL) { + state->size = drvr_state_size; + return (0); + } + + if (state->size < drvr_state_size) + return (ENXIO); + + if (ha->hw.drvr_state == NULL) + return (ENOMEM); + + hdr = ha->hw.drvr_state; + + if (!hdr->drvr_version_major) + ql_capture_drvr_state(ha); + + rval = copyout(ha->hw.drvr_state, state->buffer, drvr_state_size); + + bzero(ha->hw.drvr_state, drvr_state_size); + + return (rval); +} + +static uint32_t +ql_drvr_state_size(qla_host_t *ha) +{ + uint32_t drvr_state_size; + uint32_t size; + + size = sizeof (qla_drvr_state_hdr_t); + drvr_state_size = QL_ALIGN(size, 64); + + size = ha->hw.num_tx_rings * (sizeof (qla_drvr_state_tx_t)); + drvr_state_size += QL_ALIGN(size, 64); + + size = ha->hw.num_rds_rings * (sizeof (qla_drvr_state_rx_t)); + drvr_state_size += QL_ALIGN(size, 64); + + size = ha->hw.num_sds_rings * (sizeof (qla_drvr_state_sds_t)); + drvr_state_size += QL_ALIGN(size, 64); + + size = sizeof(q80_tx_cmd_t) * NUM_TX_DESCRIPTORS * ha->hw.num_tx_rings; + drvr_state_size += QL_ALIGN(size, 64); + + size = sizeof(q80_recv_desc_t) * NUM_RX_DESCRIPTORS * ha->hw.num_rds_rings; + drvr_state_size += QL_ALIGN(size, 64); + + size = sizeof(q80_stat_desc_t) * NUM_STATUS_DESCRIPTORS * + ha->hw.num_sds_rings; + drvr_state_size += QL_ALIGN(size, 64); + + return (drvr_state_size); +} + +static void +ql_get_tx_state(qla_host_t *ha, qla_drvr_state_tx_t *tx_state) +{ + int i; + + for (i = 0; i < ha->hw.num_tx_rings; i++) { + tx_state->base_p_addr = ha->hw.tx_cntxt[i].tx_ring_paddr; + tx_state->cons_p_addr = ha->hw.tx_cntxt[i].tx_cons_paddr; + tx_state->tx_prod_reg = ha->hw.tx_cntxt[i].tx_prod_reg; + tx_state->tx_cntxt_id = ha->hw.tx_cntxt[i].tx_cntxt_id; + tx_state->txr_free = ha->hw.tx_cntxt[i].txr_free; + tx_state->txr_next = ha->hw.tx_cntxt[i].txr_next; + tx_state->txr_comp = ha->hw.tx_cntxt[i].txr_comp; + tx_state++; + } + return; +} + +static void +ql_get_rx_state(qla_host_t *ha, qla_drvr_state_rx_t *rx_state) +{ + int i; + + for (i = 0; i < ha->hw.num_rds_rings; i++) { + rx_state->prod_std = ha->hw.rds[i].prod_std; + rx_state->rx_next = ha->hw.rds[i].rx_next; + rx_state++; + } + return; +} + +static void +ql_get_sds_state(qla_host_t *ha, qla_drvr_state_sds_t *sds_state) +{ + int i; + + for (i = 0; i < ha->hw.num_sds_rings; i++) { + sds_state->sdsr_next = ha->hw.sds[i].sdsr_next; + sds_state->sds_consumer = ha->hw.sds[i].sds_consumer; + sds_state++; + } + return; +} + +void +ql_capture_drvr_state(qla_host_t *ha) +{ + uint8_t *state_buffer; + uint8_t *ptr; + uint32_t drvr_state_size; + qla_drvr_state_hdr_t *hdr; + uint32_t size; + int i; + + drvr_state_size = ql_drvr_state_size(ha); + + state_buffer = ha->hw.drvr_state; + + if (state_buffer == NULL) + return; + + bzero(state_buffer, drvr_state_size); + + hdr = (qla_drvr_state_hdr_t *)state_buffer; + + hdr->drvr_version_major = QLA_VERSION_MAJOR; + hdr->drvr_version_minor = QLA_VERSION_MINOR; + hdr->drvr_version_build = QLA_VERSION_BUILD; + + bcopy(ha->hw.mac_addr, hdr->mac_addr, ETHER_ADDR_LEN); + + hdr->link_speed = ha->hw.link_speed; + hdr->cable_length = ha->hw.cable_length; + hdr->cable_oui = ha->hw.cable_oui; + hdr->link_up = ha->hw.link_up; + hdr->module_type = ha->hw.module_type; + hdr->link_faults = ha->hw.link_faults; + hdr->rcv_intr_coalesce = ha->hw.rcv_intr_coalesce; + hdr->xmt_intr_coalesce = ha->hw.xmt_intr_coalesce; + + size = sizeof (qla_drvr_state_hdr_t); + hdr->tx_state_offset = QL_ALIGN(size, 64); + + ptr = state_buffer + hdr->tx_state_offset; + + ql_get_tx_state(ha, (qla_drvr_state_tx_t *)ptr); + + size = ha->hw.num_tx_rings * (sizeof (qla_drvr_state_tx_t)); + hdr->rx_state_offset = hdr->tx_state_offset + QL_ALIGN(size, 64); + ptr = state_buffer + hdr->rx_state_offset; + + ql_get_rx_state(ha, (qla_drvr_state_rx_t *)ptr); + + size = ha->hw.num_rds_rings * (sizeof (qla_drvr_state_rx_t)); + hdr->sds_state_offset = hdr->rx_state_offset + QL_ALIGN(size, 64); + ptr = state_buffer + hdr->sds_state_offset; + + ql_get_sds_state(ha, (qla_drvr_state_sds_t *)ptr); + + size = ha->hw.num_sds_rings * (sizeof (qla_drvr_state_sds_t)); + hdr->txr_offset = hdr->sds_state_offset + QL_ALIGN(size, 64); + ptr = state_buffer + hdr->txr_offset; + + hdr->num_tx_rings = ha->hw.num_tx_rings; + hdr->txr_size = sizeof(q80_tx_cmd_t) * NUM_TX_DESCRIPTORS; + hdr->txr_entries = NUM_TX_DESCRIPTORS; + + size = hdr->num_tx_rings * hdr->txr_size; + bcopy(ha->hw.dma_buf.tx_ring.dma_b, ptr, size); + + hdr->rxr_offset = hdr->txr_offset + QL_ALIGN(size, 64); + ptr = state_buffer + hdr->rxr_offset; + + hdr->rxr_size = sizeof(q80_recv_desc_t) * NUM_RX_DESCRIPTORS; + hdr->rxr_entries = NUM_RX_DESCRIPTORS; + hdr->num_rx_rings = ha->hw.num_rds_rings; + + for (i = 0; i < ha->hw.num_rds_rings; i++) { + bcopy(ha->hw.dma_buf.rds_ring[i].dma_b, ptr, hdr->rxr_size); + ptr += hdr->rxr_size; + } + + size = hdr->rxr_size * hdr->num_rx_rings; + hdr->sds_offset = hdr->rxr_offset + QL_ALIGN(size, 64); + hdr->sds_ring_size = sizeof(q80_stat_desc_t) * NUM_STATUS_DESCRIPTORS; + hdr->sds_entries = NUM_STATUS_DESCRIPTORS; + hdr->num_sds_rings = ha->hw.num_sds_rings; + + ptr = state_buffer + hdr->sds_offset; + for (i = 0; i < ha->hw.num_sds_rings; i++) { + bcopy(ha->hw.dma_buf.sds_ring[i].dma_b, ptr, hdr->sds_ring_size); + ptr += hdr->sds_ring_size; + } + return; +} + +void +ql_alloc_drvr_state_buffer(qla_host_t *ha) +{ + uint32_t drvr_state_size; + + drvr_state_size = ql_drvr_state_size(ha); + + ha->hw.drvr_state = malloc(drvr_state_size, M_QLA83XXBUF, M_NOWAIT); + + return; +} + +void +ql_free_drvr_state_buffer(qla_host_t *ha) +{ + if (ha->hw.drvr_state != NULL) + free(ha->hw.drvr_state, M_QLA83XXBUF); + return; } Index: stable/11/sys/dev/qlxgbe/ql_ioctl.h =================================================================== --- stable/11/sys/dev/qlxgbe/ql_ioctl.h (revision 324761) +++ stable/11/sys/dev/qlxgbe/ql_ioctl.h (revision 324762) @@ -1,136 +1,208 @@ /* * Copyright (c) 2013-2016 Qlogic Corporation * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE * POSSIBILITY OF SUCH DAMAGE. * * $FreeBSD$ */ /* * File: ql_ioctl.h * Author : David C Somayajulu, Qlogic Corporation, Aliso Viejo, CA 92656. */ #ifndef _QL_IOCTL_H_ #define _QL_IOCTL_H_ #include struct qla_reg_val { uint16_t rd; uint16_t direct; uint32_t reg; uint32_t val; }; typedef struct qla_reg_val qla_reg_val_t; struct qla_rd_flash { uint32_t off; uint32_t data; }; typedef struct qla_rd_flash qla_rd_flash_t; struct qla_wr_flash { uint32_t off; uint32_t size; void *buffer; uint32_t pattern; }; typedef struct qla_wr_flash qla_wr_flash_t; struct qla_erase_flash { uint32_t off; uint32_t size; }; typedef struct qla_erase_flash qla_erase_flash_t; struct qla_rd_pci_ids { uint16_t ven_id; uint16_t dev_id; uint16_t subsys_ven_id; uint16_t subsys_dev_id; uint8_t rev_id; }; typedef struct qla_rd_pci_ids qla_rd_pci_ids_t; /* * structure encapsulating the value to read/write from/to offchip (MS) memory */ struct qla_offchip_mem_val { uint16_t rd; uint64_t off; uint32_t data_lo; uint32_t data_hi; uint32_t data_ulo; uint32_t data_uhi; }; typedef struct qla_offchip_mem_val qla_offchip_mem_val_t; struct qla_rd_fw_dump { uint16_t pci_func; uint32_t minidump_size; void *minidump; }; typedef struct qla_rd_fw_dump qla_rd_fw_dump_t; +struct qla_drvr_state_tx { + uint64_t base_p_addr; + uint64_t cons_p_addr; + uint32_t tx_prod_reg; + uint32_t tx_cntxt_id; + uint32_t txr_free; + uint32_t txr_next; + uint32_t txr_comp; +}; +typedef struct qla_drvr_state_tx qla_drvr_state_tx_t; + +struct qla_drvr_state_sds { + uint32_t sdsr_next; /* next entry in SDS ring to process */ + uint32_t sds_consumer; +}; +typedef struct qla_drvr_state_sds qla_drvr_state_sds_t; + +struct qla_drvr_state_rx { + uint32_t prod_std; + uint32_t rx_next; /* next standard rcv ring to arm fw */; +}; +typedef struct qla_drvr_state_rx qla_drvr_state_rx_t; + +struct qla_drvr_state_hdr { + uint32_t drvr_version_major; + uint32_t drvr_version_minor; + uint32_t drvr_version_build; + + uint8_t mac_addr[ETHER_ADDR_LEN]; + uint16_t link_speed; + uint16_t cable_length; + uint32_t cable_oui; + uint8_t link_up; + uint8_t module_type; + uint8_t link_faults; + uint32_t rcv_intr_coalesce; + uint32_t xmt_intr_coalesce; + + uint32_t tx_state_offset;/* size = sizeof (qla_drvr_state_tx_t) * num_tx_rings */ + uint32_t rx_state_offset;/* size = sizeof (qla_drvr_state_rx_t) * num_rx_rings */ + uint32_t sds_state_offset;/* size = sizeof (qla_drvr_state_sds_t) * num_sds_rings */ + + uint32_t num_tx_rings; /* number of tx rings */ + uint32_t txr_size; /* size of each tx ring in bytes */ + uint32_t txr_entries; /* number of descriptors in each tx ring */ + uint32_t txr_offset; /* start of tx ring [0 - #rings] content */ + + uint32_t num_rx_rings; /* number of rx rings */ + uint32_t rxr_size; /* size of each rx ring in bytes */ + uint32_t rxr_entries; /* number of descriptors in each rx ring */ + uint32_t rxr_offset; /* start of rx ring [0 - #rings] content */ + + uint32_t num_sds_rings; /* number of sds rings */ + uint32_t sds_ring_size; /* size of each sds ring in bytes */ + uint32_t sds_entries; /* number of descriptors in each sds ring */ + uint32_t sds_offset; /* start of sds ring [0 - #rings] content */ +}; + +typedef struct qla_drvr_state_hdr qla_drvr_state_hdr_t; + +struct qla_driver_state { + uint32_t size; + void *buffer; +}; +typedef struct qla_driver_state qla_driver_state_t; + /* * Read/Write Register */ #define QLA_RDWR_REG _IOWR('q', 1, qla_reg_val_t) /* * Read Flash */ #define QLA_RD_FLASH _IOWR('q', 2, qla_rd_flash_t) /* * Write Flash */ #define QLA_WR_FLASH _IOWR('q', 3, qla_wr_flash_t) /* * Read Offchip (MS) Memory */ #define QLA_RDWR_MS_MEM _IOWR('q', 4, qla_offchip_mem_val_t) /* * Erase Flash */ #define QLA_ERASE_FLASH _IOWR('q', 5, qla_erase_flash_t) /* * Read PCI IDs */ #define QLA_RD_PCI_IDS _IOWR('q', 6, qla_rd_pci_ids_t) /* * Read Minidump Template Size */ #define QLA_RD_FW_DUMP_SIZE _IOWR('q', 7, qla_rd_fw_dump_t) /* * Read Minidump Template */ #define QLA_RD_FW_DUMP _IOWR('q', 8, qla_rd_fw_dump_t) + +/* + * Read Driver State + */ +#define QLA_RD_DRVR_STATE _IOWR('q', 9, qla_driver_state_t) + #endif /* #ifndef _QL_IOCTL_H_ */ Index: stable/11/sys/dev/qlxgbe/ql_os.c =================================================================== --- stable/11/sys/dev/qlxgbe/ql_os.c (revision 324761) +++ stable/11/sys/dev/qlxgbe/ql_os.c (revision 324762) @@ -1,2169 +1,2171 @@ /* * Copyright (c) 2013-2016 Qlogic Corporation * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" * and ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE * POSSIBILITY OF SUCH DAMAGE. */ /* * File: ql_os.c * Author : David C Somayajulu, Qlogic Corporation, Aliso Viejo, CA 92656. */ #include __FBSDID("$FreeBSD$"); #include "ql_os.h" #include "ql_hw.h" #include "ql_def.h" #include "ql_inline.h" #include "ql_ver.h" #include "ql_glbl.h" #include "ql_dbg.h" #include /* * Some PCI Configuration Space Related Defines */ #ifndef PCI_VENDOR_QLOGIC #define PCI_VENDOR_QLOGIC 0x1077 #endif #ifndef PCI_PRODUCT_QLOGIC_ISP8030 #define PCI_PRODUCT_QLOGIC_ISP8030 0x8030 #endif #define PCI_QLOGIC_ISP8030 \ ((PCI_PRODUCT_QLOGIC_ISP8030 << 16) | PCI_VENDOR_QLOGIC) /* * static functions */ static int qla_alloc_parent_dma_tag(qla_host_t *ha); static void qla_free_parent_dma_tag(qla_host_t *ha); static int qla_alloc_xmt_bufs(qla_host_t *ha); static void qla_free_xmt_bufs(qla_host_t *ha); static int qla_alloc_rcv_bufs(qla_host_t *ha); static void qla_free_rcv_bufs(qla_host_t *ha); static void qla_clear_tx_buf(qla_host_t *ha, qla_tx_buf_t *txb); static void qla_init_ifnet(device_t dev, qla_host_t *ha); static int qla_sysctl_get_link_status(SYSCTL_HANDLER_ARGS); static void qla_release(qla_host_t *ha); static void qla_dmamap_callback(void *arg, bus_dma_segment_t *segs, int nsegs, int error); static void qla_stop(qla_host_t *ha); static void qla_get_peer(qla_host_t *ha); static void qla_error_recovery(void *context, int pending); static void qla_async_event(void *context, int pending); static void qla_stats(void *context, int pending); static int qla_send(qla_host_t *ha, struct mbuf **m_headp, uint32_t txr_idx, uint32_t iscsi_pdu); /* * Hooks to the Operating Systems */ static int qla_pci_probe (device_t); static int qla_pci_attach (device_t); static int qla_pci_detach (device_t); static void qla_init(void *arg); static int qla_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data); static int qla_media_change(struct ifnet *ifp); static void qla_media_status(struct ifnet *ifp, struct ifmediareq *ifmr); static int qla_transmit(struct ifnet *ifp, struct mbuf *mp); static void qla_qflush(struct ifnet *ifp); static int qla_alloc_tx_br(qla_host_t *ha, qla_tx_fp_t *tx_fp); static void qla_free_tx_br(qla_host_t *ha, qla_tx_fp_t *tx_fp); static int qla_create_fp_taskqueues(qla_host_t *ha); static void qla_destroy_fp_taskqueues(qla_host_t *ha); static void qla_drain_fp_taskqueues(qla_host_t *ha); static device_method_t qla_pci_methods[] = { /* Device interface */ DEVMETHOD(device_probe, qla_pci_probe), DEVMETHOD(device_attach, qla_pci_attach), DEVMETHOD(device_detach, qla_pci_detach), { 0, 0 } }; static driver_t qla_pci_driver = { "ql", qla_pci_methods, sizeof (qla_host_t), }; static devclass_t qla83xx_devclass; DRIVER_MODULE(qla83xx, pci, qla_pci_driver, qla83xx_devclass, 0, 0); MODULE_DEPEND(qla83xx, pci, 1, 1, 1); MODULE_DEPEND(qla83xx, ether, 1, 1, 1); MALLOC_DEFINE(M_QLA83XXBUF, "qla83xxbuf", "Buffers for qla83xx driver"); #define QL_STD_REPLENISH_THRES 0 #define QL_JUMBO_REPLENISH_THRES 32 static char dev_str[64]; static char ver_str[64]; /* * Name: qla_pci_probe * Function: Validate the PCI device to be a QLA80XX device */ static int qla_pci_probe(device_t dev) { switch ((pci_get_device(dev) << 16) | (pci_get_vendor(dev))) { case PCI_QLOGIC_ISP8030: snprintf(dev_str, sizeof(dev_str), "%s v%d.%d.%d", "Qlogic ISP 83xx PCI CNA Adapter-Ethernet Function", QLA_VERSION_MAJOR, QLA_VERSION_MINOR, QLA_VERSION_BUILD); snprintf(ver_str, sizeof(ver_str), "v%d.%d.%d", QLA_VERSION_MAJOR, QLA_VERSION_MINOR, QLA_VERSION_BUILD); device_set_desc(dev, dev_str); break; default: return (ENXIO); } if (bootverbose) printf("%s: %s\n ", __func__, dev_str); return (BUS_PROBE_DEFAULT); } static void qla_add_sysctls(qla_host_t *ha) { device_t dev = ha->pci_dev; SYSCTL_ADD_STRING(device_get_sysctl_ctx(dev), SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), OID_AUTO, "version", CTLFLAG_RD, ver_str, 0, "Driver Version"); SYSCTL_ADD_STRING(device_get_sysctl_ctx(dev), SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), OID_AUTO, "fw_version", CTLFLAG_RD, ha->fw_ver_str, 0, "firmware version"); SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev), SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), OID_AUTO, "link_status", CTLTYPE_INT | CTLFLAG_RW, (void *)ha, 0, qla_sysctl_get_link_status, "I", "Link Status"); ha->dbg_level = 0; SYSCTL_ADD_UINT(device_get_sysctl_ctx(dev), SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), OID_AUTO, "debug", CTLFLAG_RW, &ha->dbg_level, ha->dbg_level, "Debug Level"); ha->enable_minidump = 1; SYSCTL_ADD_UINT(device_get_sysctl_ctx(dev), SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), OID_AUTO, "enable_minidump", CTLFLAG_RW, &ha->enable_minidump, ha->enable_minidump, "Minidump retrival is enabled only when this is set"); ha->std_replenish = QL_STD_REPLENISH_THRES; SYSCTL_ADD_UINT(device_get_sysctl_ctx(dev), SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), OID_AUTO, "std_replenish", CTLFLAG_RW, &ha->std_replenish, ha->std_replenish, "Threshold for Replenishing Standard Frames"); SYSCTL_ADD_QUAD(device_get_sysctl_ctx(dev), SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), OID_AUTO, "ipv4_lro", CTLFLAG_RD, &ha->ipv4_lro, "number of ipv4 lro completions"); SYSCTL_ADD_QUAD(device_get_sysctl_ctx(dev), SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), OID_AUTO, "ipv6_lro", CTLFLAG_RD, &ha->ipv6_lro, "number of ipv6 lro completions"); SYSCTL_ADD_QUAD(device_get_sysctl_ctx(dev), SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), OID_AUTO, "tx_tso_frames", CTLFLAG_RD, &ha->tx_tso_frames, "number of Tx TSO Frames"); SYSCTL_ADD_QUAD(device_get_sysctl_ctx(dev), SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), OID_AUTO, "hw_vlan_tx_frames", CTLFLAG_RD, &ha->hw_vlan_tx_frames, "number of Tx VLAN Frames"); SYSCTL_ADD_QUAD(device_get_sysctl_ctx(dev), SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), OID_AUTO, "hw_lock_failed", CTLFLAG_RD, &ha->hw_lock_failed, "number of hw_lock failures"); return; } static void qla_watchdog(void *arg) { qla_host_t *ha = arg; qla_hw_t *hw; struct ifnet *ifp; hw = &ha->hw; ifp = ha->ifp; if (ha->qla_watchdog_exit) { ha->qla_watchdog_exited = 1; return; } ha->qla_watchdog_exited = 0; if (!ha->qla_watchdog_pause) { if (ql_hw_check_health(ha) || ha->qla_initiate_recovery || (ha->msg_from_peer == QL_PEER_MSG_RESET)) { if (!(ha->dbg_level & 0x8000)) { ha->qla_watchdog_paused = 1; ha->qla_watchdog_pause = 1; ha->qla_initiate_recovery = 0; ha->err_inject = 0; device_printf(ha->pci_dev, "%s: taskqueue_enqueue(err_task) \n", __func__); taskqueue_enqueue(ha->err_tq, &ha->err_task); return; } } else if (ha->qla_interface_up) { ha->watchdog_ticks++; if (ha->watchdog_ticks > 1000) ha->watchdog_ticks = 0; if (!ha->watchdog_ticks && QL_RUNNING(ifp)) { taskqueue_enqueue(ha->stats_tq, &ha->stats_task); } if (ha->async_event) { taskqueue_enqueue(ha->async_event_tq, &ha->async_event_task); } #if 0 for (i = 0; ((i < ha->hw.num_sds_rings) && !ha->watchdog_ticks); i++) { qla_tx_fp_t *fp = &ha->tx_fp[i]; if (fp->fp_taskqueue != NULL) taskqueue_enqueue(fp->fp_taskqueue, &fp->fp_task); } #endif ha->qla_watchdog_paused = 0; } else { ha->qla_watchdog_paused = 0; } } else { ha->qla_watchdog_paused = 1; } callout_reset(&ha->tx_callout, QLA_WATCHDOG_CALLOUT_TICKS, qla_watchdog, ha); } /* * Name: qla_pci_attach * Function: attaches the device to the operating system */ static int qla_pci_attach(device_t dev) { qla_host_t *ha = NULL; uint32_t rsrc_len; int i; uint32_t num_rcvq = 0; if ((ha = device_get_softc(dev)) == NULL) { device_printf(dev, "cannot get softc\n"); return (ENOMEM); } memset(ha, 0, sizeof (qla_host_t)); if (pci_get_device(dev) != PCI_PRODUCT_QLOGIC_ISP8030) { device_printf(dev, "device is not ISP8030\n"); return (ENXIO); } ha->pci_func = pci_get_function(dev) & 0x1; ha->pci_dev = dev; pci_enable_busmaster(dev); ha->reg_rid = PCIR_BAR(0); ha->pci_reg = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &ha->reg_rid, RF_ACTIVE); if (ha->pci_reg == NULL) { device_printf(dev, "unable to map any ports\n"); goto qla_pci_attach_err; } rsrc_len = (uint32_t) bus_get_resource_count(dev, SYS_RES_MEMORY, ha->reg_rid); mtx_init(&ha->hw_lock, "qla83xx_hw_lock", MTX_NETWORK_LOCK, MTX_DEF); ha->flags.lock_init = 1; qla_add_sysctls(ha); ha->hw.num_sds_rings = MAX_SDS_RINGS; ha->hw.num_rds_rings = MAX_RDS_RINGS; ha->hw.num_tx_rings = NUM_TX_RINGS; ha->reg_rid1 = PCIR_BAR(2); ha->pci_reg1 = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &ha->reg_rid1, RF_ACTIVE); ha->msix_count = pci_msix_count(dev); if (ha->msix_count < 1 ) { device_printf(dev, "%s: msix_count[%d] not enough\n", __func__, ha->msix_count); goto qla_pci_attach_err; } if (ha->msix_count < (ha->hw.num_sds_rings + 1)) { ha->hw.num_sds_rings = ha->msix_count - 1; } QL_DPRINT2(ha, (dev, "%s: ha %p pci_func 0x%x rsrc_count 0x%08x" " msix_count 0x%x pci_reg %p pci_reg1 %p\n", __func__, ha, ha->pci_func, rsrc_len, ha->msix_count, ha->pci_reg, ha->pci_reg1)); /* initialize hardware */ if (ql_init_hw(ha)) { device_printf(dev, "%s: ql_init_hw failed\n", __func__); goto qla_pci_attach_err; } device_printf(dev, "%s: firmware[%d.%d.%d.%d]\n", __func__, ha->fw_ver_major, ha->fw_ver_minor, ha->fw_ver_sub, ha->fw_ver_build); snprintf(ha->fw_ver_str, sizeof(ha->fw_ver_str), "%d.%d.%d.%d", ha->fw_ver_major, ha->fw_ver_minor, ha->fw_ver_sub, ha->fw_ver_build); if (qla_get_nic_partition(ha, NULL, &num_rcvq)) { device_printf(dev, "%s: qla_get_nic_partition failed\n", __func__); goto qla_pci_attach_err; } device_printf(dev, "%s: ha %p pci_func 0x%x rsrc_count 0x%08x" " msix_count 0x%x pci_reg %p pci_reg1 %p num_rcvq = %d\n", __func__, ha, ha->pci_func, rsrc_len, ha->msix_count, ha->pci_reg, ha->pci_reg1, num_rcvq); if ((ha->msix_count < 64) || (num_rcvq != 32)) { if (ha->hw.num_sds_rings > 15) { ha->hw.num_sds_rings = 15; } } ha->hw.num_rds_rings = ha->hw.num_sds_rings; ha->hw.num_tx_rings = ha->hw.num_sds_rings; #ifdef QL_ENABLE_ISCSI_TLV ha->hw.num_tx_rings = ha->hw.num_sds_rings * 2; #endif /* #ifdef QL_ENABLE_ISCSI_TLV */ ql_hw_add_sysctls(ha); ha->msix_count = ha->hw.num_sds_rings + 1; if (pci_alloc_msix(dev, &ha->msix_count)) { device_printf(dev, "%s: pci_alloc_msi[%d] failed\n", __func__, ha->msix_count); ha->msix_count = 0; goto qla_pci_attach_err; } ha->mbx_irq_rid = 1; ha->mbx_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &ha->mbx_irq_rid, (RF_ACTIVE | RF_SHAREABLE)); if (ha->mbx_irq == NULL) { device_printf(dev, "could not allocate mbx interrupt\n"); goto qla_pci_attach_err; } if (bus_setup_intr(dev, ha->mbx_irq, (INTR_TYPE_NET | INTR_MPSAFE), NULL, ql_mbx_isr, ha, &ha->mbx_handle)) { device_printf(dev, "could not setup mbx interrupt\n"); goto qla_pci_attach_err; } for (i = 0; i < ha->hw.num_sds_rings; i++) { ha->irq_vec[i].sds_idx = i; ha->irq_vec[i].ha = ha; ha->irq_vec[i].irq_rid = 2 + i; ha->irq_vec[i].irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &ha->irq_vec[i].irq_rid, (RF_ACTIVE | RF_SHAREABLE)); if (ha->irq_vec[i].irq == NULL) { device_printf(dev, "could not allocate interrupt\n"); goto qla_pci_attach_err; } if (bus_setup_intr(dev, ha->irq_vec[i].irq, (INTR_TYPE_NET | INTR_MPSAFE), NULL, ql_isr, &ha->irq_vec[i], &ha->irq_vec[i].handle)) { device_printf(dev, "could not setup interrupt\n"); goto qla_pci_attach_err; } ha->tx_fp[i].ha = ha; ha->tx_fp[i].txr_idx = i; if (qla_alloc_tx_br(ha, &ha->tx_fp[i])) { device_printf(dev, "%s: could not allocate tx_br[%d]\n", __func__, i); goto qla_pci_attach_err; } } if (qla_create_fp_taskqueues(ha) != 0) goto qla_pci_attach_err; printf("%s: mp__ncpus %d sds %d rds %d msi-x %d\n", __func__, mp_ncpus, ha->hw.num_sds_rings, ha->hw.num_rds_rings, ha->msix_count); ql_read_mac_addr(ha); /* allocate parent dma tag */ if (qla_alloc_parent_dma_tag(ha)) { device_printf(dev, "%s: qla_alloc_parent_dma_tag failed\n", __func__); goto qla_pci_attach_err; } /* alloc all dma buffers */ if (ql_alloc_dma(ha)) { device_printf(dev, "%s: ql_alloc_dma failed\n", __func__); goto qla_pci_attach_err; } qla_get_peer(ha); if (ql_minidump_init(ha) != 0) { device_printf(dev, "%s: ql_minidump_init failed\n", __func__); goto qla_pci_attach_err; } + ql_alloc_drvr_state_buffer(ha); /* create the o.s ethernet interface */ qla_init_ifnet(dev, ha); ha->flags.qla_watchdog_active = 1; ha->qla_watchdog_pause = 0; callout_init(&ha->tx_callout, TRUE); ha->flags.qla_callout_init = 1; /* create ioctl device interface */ if (ql_make_cdev(ha)) { device_printf(dev, "%s: ql_make_cdev failed\n", __func__); goto qla_pci_attach_err; } callout_reset(&ha->tx_callout, QLA_WATCHDOG_CALLOUT_TICKS, qla_watchdog, ha); TASK_INIT(&ha->err_task, 0, qla_error_recovery, ha); ha->err_tq = taskqueue_create("qla_errq", M_NOWAIT, taskqueue_thread_enqueue, &ha->err_tq); taskqueue_start_threads(&ha->err_tq, 1, PI_NET, "%s errq", device_get_nameunit(ha->pci_dev)); TASK_INIT(&ha->async_event_task, 0, qla_async_event, ha); ha->async_event_tq = taskqueue_create("qla_asyncq", M_NOWAIT, taskqueue_thread_enqueue, &ha->async_event_tq); taskqueue_start_threads(&ha->async_event_tq, 1, PI_NET, "%s asyncq", device_get_nameunit(ha->pci_dev)); TASK_INIT(&ha->stats_task, 0, qla_stats, ha); ha->stats_tq = taskqueue_create("qla_statsq", M_NOWAIT, taskqueue_thread_enqueue, &ha->stats_tq); taskqueue_start_threads(&ha->stats_tq, 1, PI_NET, "%s taskq", device_get_nameunit(ha->pci_dev)); QL_DPRINT2(ha, (dev, "%s: exit 0\n", __func__)); return (0); qla_pci_attach_err: qla_release(ha); if (ha->flags.lock_init) { mtx_destroy(&ha->hw_lock); } QL_DPRINT2(ha, (dev, "%s: exit ENXIO\n", __func__)); return (ENXIO); } /* * Name: qla_pci_detach * Function: Unhooks the device from the operating system */ static int qla_pci_detach(device_t dev) { qla_host_t *ha = NULL; struct ifnet *ifp; if ((ha = device_get_softc(dev)) == NULL) { device_printf(dev, "cannot get softc\n"); return (ENOMEM); } QL_DPRINT2(ha, (dev, "%s: enter\n", __func__)); ifp = ha->ifp; ifp->if_drv_flags &= ~IFF_DRV_RUNNING; QLA_LOCK(ha, __func__, -1, 0); ha->qla_detach_active = 1; qla_stop(ha); qla_release(ha); QLA_UNLOCK(ha, __func__); if (ha->flags.lock_init) { mtx_destroy(&ha->hw_lock); } QL_DPRINT2(ha, (dev, "%s: exit\n", __func__)); return (0); } /* * SYSCTL Related Callbacks */ static int qla_sysctl_get_link_status(SYSCTL_HANDLER_ARGS) { int err, ret = 0; qla_host_t *ha; err = sysctl_handle_int(oidp, &ret, 0, req); if (err || !req->newptr) return (err); if (ret == 1) { ha = (qla_host_t *)arg1; ql_hw_link_status(ha); } return (err); } /* * Name: qla_release * Function: Releases the resources allocated for the device */ static void qla_release(qla_host_t *ha) { device_t dev; int i; dev = ha->pci_dev; if (ha->async_event_tq) { taskqueue_drain(ha->async_event_tq, &ha->async_event_task); taskqueue_free(ha->async_event_tq); } if (ha->err_tq) { taskqueue_drain(ha->err_tq, &ha->err_task); taskqueue_free(ha->err_tq); } if (ha->stats_tq) { taskqueue_drain(ha->stats_tq, &ha->stats_task); taskqueue_free(ha->stats_tq); } ql_del_cdev(ha); if (ha->flags.qla_watchdog_active) { ha->qla_watchdog_exit = 1; while (ha->qla_watchdog_exited == 0) qla_mdelay(__func__, 1); } if (ha->flags.qla_callout_init) callout_stop(&ha->tx_callout); if (ha->ifp != NULL) ether_ifdetach(ha->ifp); + ql_free_drvr_state_buffer(ha); ql_free_dma(ha); qla_free_parent_dma_tag(ha); if (ha->mbx_handle) (void)bus_teardown_intr(dev, ha->mbx_irq, ha->mbx_handle); if (ha->mbx_irq) (void) bus_release_resource(dev, SYS_RES_IRQ, ha->mbx_irq_rid, ha->mbx_irq); for (i = 0; i < ha->hw.num_sds_rings; i++) { if (ha->irq_vec[i].handle) { (void)bus_teardown_intr(dev, ha->irq_vec[i].irq, ha->irq_vec[i].handle); } if (ha->irq_vec[i].irq) { (void)bus_release_resource(dev, SYS_RES_IRQ, ha->irq_vec[i].irq_rid, ha->irq_vec[i].irq); } qla_free_tx_br(ha, &ha->tx_fp[i]); } qla_destroy_fp_taskqueues(ha); if (ha->msix_count) pci_release_msi(dev); // if (ha->flags.lock_init) { // mtx_destroy(&ha->hw_lock); // } if (ha->pci_reg) (void) bus_release_resource(dev, SYS_RES_MEMORY, ha->reg_rid, ha->pci_reg); if (ha->pci_reg1) (void) bus_release_resource(dev, SYS_RES_MEMORY, ha->reg_rid1, ha->pci_reg1); return; } /* * DMA Related Functions */ static void qla_dmamap_callback(void *arg, bus_dma_segment_t *segs, int nsegs, int error) { *((bus_addr_t *)arg) = 0; if (error) { printf("%s: bus_dmamap_load failed (%d)\n", __func__, error); return; } *((bus_addr_t *)arg) = segs[0].ds_addr; return; } int ql_alloc_dmabuf(qla_host_t *ha, qla_dma_t *dma_buf) { int ret = 0; device_t dev; bus_addr_t b_addr; dev = ha->pci_dev; QL_DPRINT2(ha, (dev, "%s: enter\n", __func__)); ret = bus_dma_tag_create( ha->parent_tag,/* parent */ dma_buf->alignment, ((bus_size_t)(1ULL << 32)),/* boundary */ BUS_SPACE_MAXADDR, /* lowaddr */ BUS_SPACE_MAXADDR, /* highaddr */ NULL, NULL, /* filter, filterarg */ dma_buf->size, /* maxsize */ 1, /* nsegments */ dma_buf->size, /* maxsegsize */ 0, /* flags */ NULL, NULL, /* lockfunc, lockarg */ &dma_buf->dma_tag); if (ret) { device_printf(dev, "%s: could not create dma tag\n", __func__); goto ql_alloc_dmabuf_exit; } ret = bus_dmamem_alloc(dma_buf->dma_tag, (void **)&dma_buf->dma_b, (BUS_DMA_ZERO | BUS_DMA_COHERENT | BUS_DMA_NOWAIT), &dma_buf->dma_map); if (ret) { bus_dma_tag_destroy(dma_buf->dma_tag); device_printf(dev, "%s: bus_dmamem_alloc failed\n", __func__); goto ql_alloc_dmabuf_exit; } ret = bus_dmamap_load(dma_buf->dma_tag, dma_buf->dma_map, dma_buf->dma_b, dma_buf->size, qla_dmamap_callback, &b_addr, BUS_DMA_NOWAIT); if (ret || !b_addr) { bus_dma_tag_destroy(dma_buf->dma_tag); bus_dmamem_free(dma_buf->dma_tag, dma_buf->dma_b, dma_buf->dma_map); ret = -1; goto ql_alloc_dmabuf_exit; } dma_buf->dma_addr = b_addr; ql_alloc_dmabuf_exit: QL_DPRINT2(ha, (dev, "%s: exit ret 0x%08x tag %p map %p b %p sz 0x%x\n", __func__, ret, (void *)dma_buf->dma_tag, (void *)dma_buf->dma_map, (void *)dma_buf->dma_b, dma_buf->size)); return ret; } void ql_free_dmabuf(qla_host_t *ha, qla_dma_t *dma_buf) { bus_dmamap_unload(dma_buf->dma_tag, dma_buf->dma_map); bus_dmamem_free(dma_buf->dma_tag, dma_buf->dma_b, dma_buf->dma_map); bus_dma_tag_destroy(dma_buf->dma_tag); } static int qla_alloc_parent_dma_tag(qla_host_t *ha) { int ret; device_t dev; dev = ha->pci_dev; /* * Allocate parent DMA Tag */ ret = bus_dma_tag_create( bus_get_dma_tag(dev), /* parent */ 1,((bus_size_t)(1ULL << 32)),/* alignment, boundary */ BUS_SPACE_MAXADDR, /* lowaddr */ BUS_SPACE_MAXADDR, /* highaddr */ NULL, NULL, /* filter, filterarg */ BUS_SPACE_MAXSIZE_32BIT,/* maxsize */ 0, /* nsegments */ BUS_SPACE_MAXSIZE_32BIT,/* maxsegsize */ 0, /* flags */ NULL, NULL, /* lockfunc, lockarg */ &ha->parent_tag); if (ret) { device_printf(dev, "%s: could not create parent dma tag\n", __func__); return (-1); } ha->flags.parent_tag = 1; return (0); } static void qla_free_parent_dma_tag(qla_host_t *ha) { if (ha->flags.parent_tag) { bus_dma_tag_destroy(ha->parent_tag); ha->flags.parent_tag = 0; } } /* * Name: qla_init_ifnet * Function: Creates the Network Device Interface and Registers it with the O.S */ static void qla_init_ifnet(device_t dev, qla_host_t *ha) { struct ifnet *ifp; QL_DPRINT2(ha, (dev, "%s: enter\n", __func__)); ifp = ha->ifp = if_alloc(IFT_ETHER); if (ifp == NULL) panic("%s: cannot if_alloc()\n", device_get_nameunit(dev)); if_initname(ifp, device_get_name(dev), device_get_unit(dev)); ifp->if_baudrate = IF_Gbps(10); ifp->if_capabilities = IFCAP_LINKSTATE; ifp->if_mtu = ETHERMTU; ifp->if_init = qla_init; ifp->if_softc = ha; ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; ifp->if_ioctl = qla_ioctl; ifp->if_transmit = qla_transmit; ifp->if_qflush = qla_qflush; IFQ_SET_MAXLEN(&ifp->if_snd, qla_get_ifq_snd_maxlen(ha)); ifp->if_snd.ifq_drv_maxlen = qla_get_ifq_snd_maxlen(ha); IFQ_SET_READY(&ifp->if_snd); ha->max_frame_size = ifp->if_mtu + ETHER_HDR_LEN + ETHER_CRC_LEN; ether_ifattach(ifp, qla_get_mac_addr(ha)); ifp->if_capabilities |= IFCAP_HWCSUM | IFCAP_TSO4 | IFCAP_JUMBO_MTU | IFCAP_VLAN_HWTAGGING | IFCAP_VLAN_MTU | IFCAP_VLAN_HWTSO | IFCAP_LRO; ifp->if_capenable = ifp->if_capabilities; ifp->if_hdrlen = sizeof(struct ether_vlan_header); ifmedia_init(&ha->media, IFM_IMASK, qla_media_change, qla_media_status); ifmedia_add(&ha->media, (IFM_ETHER | qla_get_optics(ha) | IFM_FDX), 0, NULL); ifmedia_add(&ha->media, (IFM_ETHER | IFM_AUTO), 0, NULL); ifmedia_set(&ha->media, (IFM_ETHER | IFM_AUTO)); QL_DPRINT2(ha, (dev, "%s: exit\n", __func__)); return; } static void qla_init_locked(qla_host_t *ha) { struct ifnet *ifp = ha->ifp; qla_stop(ha); if (qla_alloc_xmt_bufs(ha) != 0) return; qla_confirm_9kb_enable(ha); if (qla_alloc_rcv_bufs(ha) != 0) return; bcopy(IF_LLADDR(ha->ifp), ha->hw.mac_addr, ETHER_ADDR_LEN); ifp->if_hwassist = CSUM_TCP | CSUM_UDP | CSUM_TSO; ifp->if_hwassist |= CSUM_TCP_IPV6 | CSUM_UDP_IPV6; ha->stop_rcv = 0; if (ql_init_hw_if(ha) == 0) { ifp = ha->ifp; ifp->if_drv_flags |= IFF_DRV_RUNNING; ha->qla_watchdog_pause = 0; ha->hw_vlan_tx_frames = 0; ha->tx_tso_frames = 0; ha->qla_interface_up = 1; ql_update_link_state(ha); } return; } static void qla_init(void *arg) { qla_host_t *ha; ha = (qla_host_t *)arg; QL_DPRINT2(ha, (ha->pci_dev, "%s: enter\n", __func__)); if (QLA_LOCK(ha, __func__, -1, 0) != 0) return; qla_init_locked(ha); QLA_UNLOCK(ha, __func__); QL_DPRINT2(ha, (ha->pci_dev, "%s: exit\n", __func__)); } static int qla_set_multi(qla_host_t *ha, uint32_t add_multi) { uint8_t mta[Q8_MAX_NUM_MULTICAST_ADDRS * Q8_MAC_ADDR_LEN]; struct ifmultiaddr *ifma; int mcnt = 0; struct ifnet *ifp = ha->ifp; int ret = 0; if_maddr_rlock(ifp); TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { if (ifma->ifma_addr->sa_family != AF_LINK) continue; if (mcnt == Q8_MAX_NUM_MULTICAST_ADDRS) break; bcopy(LLADDR((struct sockaddr_dl *) ifma->ifma_addr), &mta[mcnt * Q8_MAC_ADDR_LEN], Q8_MAC_ADDR_LEN); mcnt++; } if_maddr_runlock(ifp); if (QLA_LOCK(ha, __func__, QLA_LOCK_DEFAULT_MS_TIMEOUT, QLA_LOCK_NO_SLEEP) != 0) return (-1); if (ifp->if_drv_flags & IFF_DRV_RUNNING) { if (!add_multi) { ret = qla_hw_del_all_mcast(ha); if (ret) device_printf(ha->pci_dev, "%s: qla_hw_del_all_mcast() failed\n", __func__); } if (!ret) ret = ql_hw_set_multi(ha, mta, mcnt, 1); } QLA_UNLOCK(ha, __func__); return (ret); } static int qla_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data) { int ret = 0; struct ifreq *ifr = (struct ifreq *)data; struct ifaddr *ifa = (struct ifaddr *)data; qla_host_t *ha; ha = (qla_host_t *)ifp->if_softc; switch (cmd) { case SIOCSIFADDR: QL_DPRINT4(ha, (ha->pci_dev, "%s: SIOCSIFADDR (0x%lx)\n", __func__, cmd)); if (ifa->ifa_addr->sa_family == AF_INET) { ret = QLA_LOCK(ha, __func__, QLA_LOCK_DEFAULT_MS_TIMEOUT, QLA_LOCK_NO_SLEEP); if (ret) break; ifp->if_flags |= IFF_UP; if (!(ifp->if_drv_flags & IFF_DRV_RUNNING)) { qla_init_locked(ha); } QLA_UNLOCK(ha, __func__); QL_DPRINT4(ha, (ha->pci_dev, "%s: SIOCSIFADDR (0x%lx) ipv4 [0x%08x]\n", __func__, cmd, ntohl(IA_SIN(ifa)->sin_addr.s_addr))); arp_ifinit(ifp, ifa); } else { ether_ioctl(ifp, cmd, data); } break; case SIOCSIFMTU: QL_DPRINT4(ha, (ha->pci_dev, "%s: SIOCSIFMTU (0x%lx)\n", __func__, cmd)); if (ifr->ifr_mtu > QLA_MAX_MTU) { ret = EINVAL; } else { ret = QLA_LOCK(ha, __func__, QLA_LOCK_DEFAULT_MS_TIMEOUT, QLA_LOCK_NO_SLEEP); if (ret) break; ifp->if_mtu = ifr->ifr_mtu; ha->max_frame_size = ifp->if_mtu + ETHER_HDR_LEN + ETHER_CRC_LEN; if (ifp->if_drv_flags & IFF_DRV_RUNNING) { qla_init_locked(ha); } if (ifp->if_mtu > ETHERMTU) ha->std_replenish = QL_JUMBO_REPLENISH_THRES; else ha->std_replenish = QL_STD_REPLENISH_THRES; QLA_UNLOCK(ha, __func__); } break; case SIOCSIFFLAGS: QL_DPRINT4(ha, (ha->pci_dev, "%s: SIOCSIFFLAGS (0x%lx)\n", __func__, cmd)); ret = QLA_LOCK(ha, __func__, QLA_LOCK_DEFAULT_MS_TIMEOUT, QLA_LOCK_NO_SLEEP); if (ret) break; if (ifp->if_flags & IFF_UP) { ha->max_frame_size = ifp->if_mtu + ETHER_HDR_LEN + ETHER_CRC_LEN; qla_init_locked(ha); if (ifp->if_drv_flags & IFF_DRV_RUNNING) { if ((ifp->if_flags ^ ha->if_flags) & IFF_PROMISC) { ret = ql_set_promisc(ha); } else if ((ifp->if_flags ^ ha->if_flags) & IFF_ALLMULTI) { ret = ql_set_allmulti(ha); } } } else { if (ifp->if_drv_flags & IFF_DRV_RUNNING) qla_stop(ha); ha->if_flags = ifp->if_flags; } QLA_UNLOCK(ha, __func__); break; case SIOCADDMULTI: QL_DPRINT4(ha, (ha->pci_dev, "%s: %s (0x%lx)\n", __func__, "SIOCADDMULTI", cmd)); if (qla_set_multi(ha, 1)) ret = EINVAL; break; case SIOCDELMULTI: QL_DPRINT4(ha, (ha->pci_dev, "%s: %s (0x%lx)\n", __func__, "SIOCDELMULTI", cmd)); if (qla_set_multi(ha, 0)) ret = EINVAL; break; case SIOCSIFMEDIA: case SIOCGIFMEDIA: QL_DPRINT4(ha, (ha->pci_dev, "%s: SIOCSIFMEDIA/SIOCGIFMEDIA (0x%lx)\n", __func__, cmd)); ret = ifmedia_ioctl(ifp, ifr, &ha->media, cmd); break; case SIOCSIFCAP: { int mask = ifr->ifr_reqcap ^ ifp->if_capenable; QL_DPRINT4(ha, (ha->pci_dev, "%s: SIOCSIFCAP (0x%lx)\n", __func__, cmd)); if (mask & IFCAP_HWCSUM) ifp->if_capenable ^= IFCAP_HWCSUM; if (mask & IFCAP_TSO4) ifp->if_capenable ^= IFCAP_TSO4; if (mask & IFCAP_TSO6) ifp->if_capenable ^= IFCAP_TSO6; if (mask & IFCAP_VLAN_HWTAGGING) ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING; if (mask & IFCAP_VLAN_HWTSO) ifp->if_capenable ^= IFCAP_VLAN_HWTSO; if (mask & IFCAP_LRO) ifp->if_capenable ^= IFCAP_LRO; if (ifp->if_drv_flags & IFF_DRV_RUNNING) { ret = QLA_LOCK(ha, __func__, QLA_LOCK_DEFAULT_MS_TIMEOUT, QLA_LOCK_NO_SLEEP); if (ret) break; qla_init_locked(ha); QLA_UNLOCK(ha, __func__); } VLAN_CAPABILITIES(ifp); break; } default: QL_DPRINT4(ha, (ha->pci_dev, "%s: default (0x%lx)\n", __func__, cmd)); ret = ether_ioctl(ifp, cmd, data); break; } return (ret); } static int qla_media_change(struct ifnet *ifp) { qla_host_t *ha; struct ifmedia *ifm; int ret = 0; ha = (qla_host_t *)ifp->if_softc; QL_DPRINT2(ha, (ha->pci_dev, "%s: enter\n", __func__)); ifm = &ha->media; if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER) ret = EINVAL; QL_DPRINT2(ha, (ha->pci_dev, "%s: exit\n", __func__)); return (ret); } static void qla_media_status(struct ifnet *ifp, struct ifmediareq *ifmr) { qla_host_t *ha; ha = (qla_host_t *)ifp->if_softc; QL_DPRINT2(ha, (ha->pci_dev, "%s: enter\n", __func__)); ifmr->ifm_status = IFM_AVALID; ifmr->ifm_active = IFM_ETHER; ql_update_link_state(ha); if (ha->hw.link_up) { ifmr->ifm_status |= IFM_ACTIVE; ifmr->ifm_active |= (IFM_FDX | qla_get_optics(ha)); } QL_DPRINT2(ha, (ha->pci_dev, "%s: exit (%s)\n", __func__,\ (ha->hw.link_up ? "link_up" : "link_down"))); return; } static int qla_send(qla_host_t *ha, struct mbuf **m_headp, uint32_t txr_idx, uint32_t iscsi_pdu) { bus_dma_segment_t segs[QLA_MAX_SEGMENTS]; bus_dmamap_t map; int nsegs; int ret = -1; uint32_t tx_idx; struct mbuf *m_head = *m_headp; QL_DPRINT8(ha, (ha->pci_dev, "%s: enter\n", __func__)); tx_idx = ha->hw.tx_cntxt[txr_idx].txr_next; if (NULL != ha->tx_ring[txr_idx].tx_buf[tx_idx].m_head) { QL_ASSERT(ha, 0, ("%s [%d]: txr_idx = %d tx_idx = %d "\ "mbuf = %p\n", __func__, __LINE__, txr_idx, tx_idx,\ ha->tx_ring[txr_idx].tx_buf[tx_idx].m_head)); if (m_head) m_freem(m_head); *m_headp = NULL; return (ret); } map = ha->tx_ring[txr_idx].tx_buf[tx_idx].map; ret = bus_dmamap_load_mbuf_sg(ha->tx_tag, map, m_head, segs, &nsegs, BUS_DMA_NOWAIT); if (ret == EFBIG) { struct mbuf *m; QL_DPRINT8(ha, (ha->pci_dev, "%s: EFBIG [%d]\n", __func__, m_head->m_pkthdr.len)); m = m_defrag(m_head, M_NOWAIT); if (m == NULL) { ha->err_tx_defrag++; m_freem(m_head); *m_headp = NULL; device_printf(ha->pci_dev, "%s: m_defrag() = NULL [%d]\n", __func__, ret); return (ENOBUFS); } m_head = m; *m_headp = m_head; if ((ret = bus_dmamap_load_mbuf_sg(ha->tx_tag, map, m_head, segs, &nsegs, BUS_DMA_NOWAIT))) { ha->err_tx_dmamap_load++; device_printf(ha->pci_dev, "%s: bus_dmamap_load_mbuf_sg failed0[%d, %d]\n", __func__, ret, m_head->m_pkthdr.len); if (ret != ENOMEM) { m_freem(m_head); *m_headp = NULL; } return (ret); } } else if (ret) { ha->err_tx_dmamap_load++; device_printf(ha->pci_dev, "%s: bus_dmamap_load_mbuf_sg failed1[%d, %d]\n", __func__, ret, m_head->m_pkthdr.len); if (ret != ENOMEM) { m_freem(m_head); *m_headp = NULL; } return (ret); } QL_ASSERT(ha, (nsegs != 0), ("qla_send: empty packet")); bus_dmamap_sync(ha->tx_tag, map, BUS_DMASYNC_PREWRITE); if (!(ret = ql_hw_send(ha, segs, nsegs, tx_idx, m_head, txr_idx, iscsi_pdu))) { ha->tx_ring[txr_idx].count++; if (iscsi_pdu) ha->tx_ring[txr_idx].iscsi_pkt_count++; ha->tx_ring[txr_idx].tx_buf[tx_idx].m_head = m_head; } else { bus_dmamap_unload(ha->tx_tag, map); if (ret == EINVAL) { if (m_head) m_freem(m_head); *m_headp = NULL; } } QL_DPRINT8(ha, (ha->pci_dev, "%s: exit\n", __func__)); return (ret); } static int qla_alloc_tx_br(qla_host_t *ha, qla_tx_fp_t *fp) { snprintf(fp->tx_mtx_name, sizeof(fp->tx_mtx_name), "qla%d_fp%d_tx_mq_lock", ha->pci_func, fp->txr_idx); mtx_init(&fp->tx_mtx, fp->tx_mtx_name, NULL, MTX_DEF); fp->tx_br = buf_ring_alloc(NUM_TX_DESCRIPTORS, M_DEVBUF, M_NOWAIT, &fp->tx_mtx); if (fp->tx_br == NULL) { QL_DPRINT1(ha, (ha->pci_dev, "buf_ring_alloc failed for " " fp[%d, %d]\n", ha->pci_func, fp->txr_idx)); return (-ENOMEM); } return 0; } static void qla_free_tx_br(qla_host_t *ha, qla_tx_fp_t *fp) { struct mbuf *mp; struct ifnet *ifp = ha->ifp; if (mtx_initialized(&fp->tx_mtx)) { if (fp->tx_br != NULL) { mtx_lock(&fp->tx_mtx); while ((mp = drbr_dequeue(ifp, fp->tx_br)) != NULL) { m_freem(mp); } mtx_unlock(&fp->tx_mtx); buf_ring_free(fp->tx_br, M_DEVBUF); fp->tx_br = NULL; } mtx_destroy(&fp->tx_mtx); } return; } static void qla_fp_taskqueue(void *context, int pending) { qla_tx_fp_t *fp; qla_host_t *ha; struct ifnet *ifp; struct mbuf *mp; int ret; uint32_t txr_idx; uint32_t iscsi_pdu = 0; uint32_t rx_pkts_left = -1; fp = context; if (fp == NULL) return; ha = (qla_host_t *)fp->ha; ifp = ha->ifp; txr_idx = fp->txr_idx; mtx_lock(&fp->tx_mtx); if (!(ifp->if_drv_flags & IFF_DRV_RUNNING) || (!ha->hw.link_up)) { mtx_unlock(&fp->tx_mtx); goto qla_fp_taskqueue_exit; } while (rx_pkts_left && !ha->stop_rcv && (ifp->if_drv_flags & IFF_DRV_RUNNING)) { rx_pkts_left = ql_rcv_isr(ha, fp->txr_idx, 64); #ifdef QL_ENABLE_ISCSI_TLV ql_hw_tx_done_locked(ha, fp->txr_idx); ql_hw_tx_done_locked(ha, (fp->txr_idx + (ha->hw.num_tx_rings >> 1))); #else ql_hw_tx_done_locked(ha, fp->txr_idx); #endif /* #ifdef QL_ENABLE_ISCSI_TLV */ mp = drbr_peek(ifp, fp->tx_br); while (mp != NULL) { if (M_HASHTYPE_GET(mp) != M_HASHTYPE_NONE) { #ifdef QL_ENABLE_ISCSI_TLV if (ql_iscsi_pdu(ha, mp) == 0) { txr_idx = txr_idx + (ha->hw.num_tx_rings >> 1); iscsi_pdu = 1; } else { iscsi_pdu = 0; txr_idx = fp->txr_idx; } #endif /* #ifdef QL_ENABLE_ISCSI_TLV */ } ret = qla_send(ha, &mp, txr_idx, iscsi_pdu); if (ret) { if (mp != NULL) drbr_putback(ifp, fp->tx_br, mp); else { drbr_advance(ifp, fp->tx_br); } mtx_unlock(&fp->tx_mtx); goto qla_fp_taskqueue_exit0; } else { drbr_advance(ifp, fp->tx_br); } /* Send a copy of the frame to the BPF listener */ ETHER_BPF_MTAP(ifp, mp); if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) break; mp = drbr_peek(ifp, fp->tx_br); } } mtx_unlock(&fp->tx_mtx); qla_fp_taskqueue_exit0: if (rx_pkts_left || ((mp != NULL) && ret)) { taskqueue_enqueue(fp->fp_taskqueue, &fp->fp_task); } else { if (!ha->stop_rcv) { QL_ENABLE_INTERRUPTS(ha, fp->txr_idx); } } qla_fp_taskqueue_exit: QL_DPRINT2(ha, (ha->pci_dev, "%s: exit ret = %d\n", __func__, ret)); return; } static int qla_create_fp_taskqueues(qla_host_t *ha) { int i; uint8_t tq_name[32]; for (i = 0; i < ha->hw.num_sds_rings; i++) { qla_tx_fp_t *fp = &ha->tx_fp[i]; bzero(tq_name, sizeof (tq_name)); snprintf(tq_name, sizeof (tq_name), "ql_fp_tq_%d", i); TASK_INIT(&fp->fp_task, 0, qla_fp_taskqueue, fp); fp->fp_taskqueue = taskqueue_create_fast(tq_name, M_NOWAIT, taskqueue_thread_enqueue, &fp->fp_taskqueue); if (fp->fp_taskqueue == NULL) return (-1); taskqueue_start_threads(&fp->fp_taskqueue, 1, PI_NET, "%s", tq_name); QL_DPRINT1(ha, (ha->pci_dev, "%s: %p\n", __func__, fp->fp_taskqueue)); } return (0); } static void qla_destroy_fp_taskqueues(qla_host_t *ha) { int i; for (i = 0; i < ha->hw.num_sds_rings; i++) { qla_tx_fp_t *fp = &ha->tx_fp[i]; if (fp->fp_taskqueue != NULL) { taskqueue_drain(fp->fp_taskqueue, &fp->fp_task); taskqueue_free(fp->fp_taskqueue); fp->fp_taskqueue = NULL; } } return; } static void qla_drain_fp_taskqueues(qla_host_t *ha) { int i; for (i = 0; i < ha->hw.num_sds_rings; i++) { qla_tx_fp_t *fp = &ha->tx_fp[i]; if (fp->fp_taskqueue != NULL) { taskqueue_drain(fp->fp_taskqueue, &fp->fp_task); } } return; } static int qla_transmit(struct ifnet *ifp, struct mbuf *mp) { qla_host_t *ha = (qla_host_t *)ifp->if_softc; qla_tx_fp_t *fp; int rss_id = 0; int ret = 0; QL_DPRINT2(ha, (ha->pci_dev, "%s: enter\n", __func__)); #if __FreeBSD_version >= 1100000 if (M_HASHTYPE_GET(mp) != M_HASHTYPE_NONE) #else if (mp->m_flags & M_FLOWID) #endif rss_id = (mp->m_pkthdr.flowid & Q8_RSS_IND_TBL_MAX_IDX) % ha->hw.num_sds_rings; fp = &ha->tx_fp[rss_id]; if (fp->tx_br == NULL) { ret = EINVAL; goto qla_transmit_exit; } if (mp != NULL) { ret = drbr_enqueue(ifp, fp->tx_br, mp); } if (fp->fp_taskqueue != NULL) taskqueue_enqueue(fp->fp_taskqueue, &fp->fp_task); ret = 0; qla_transmit_exit: QL_DPRINT2(ha, (ha->pci_dev, "%s: exit ret = %d\n", __func__, ret)); return ret; } static void qla_qflush(struct ifnet *ifp) { int i; qla_tx_fp_t *fp; struct mbuf *mp; qla_host_t *ha; ha = (qla_host_t *)ifp->if_softc; QL_DPRINT2(ha, (ha->pci_dev, "%s: enter\n", __func__)); for (i = 0; i < ha->hw.num_sds_rings; i++) { fp = &ha->tx_fp[i]; if (fp == NULL) continue; if (fp->tx_br) { mtx_lock(&fp->tx_mtx); while ((mp = drbr_dequeue(ifp, fp->tx_br)) != NULL) { m_freem(mp); } mtx_unlock(&fp->tx_mtx); } } QL_DPRINT2(ha, (ha->pci_dev, "%s: exit\n", __func__)); return; } static void qla_stop(qla_host_t *ha) { struct ifnet *ifp = ha->ifp; device_t dev; int i = 0; dev = ha->pci_dev; ifp->if_drv_flags &= ~IFF_DRV_RUNNING; ha->qla_watchdog_pause = 1; for (i = 0; i < ha->hw.num_sds_rings; i++) { qla_tx_fp_t *fp; fp = &ha->tx_fp[i]; if (fp == NULL) continue; if (fp->tx_br != NULL) { mtx_lock(&fp->tx_mtx); mtx_unlock(&fp->tx_mtx); } } while (!ha->qla_watchdog_paused) qla_mdelay(__func__, 1); ha->qla_interface_up = 0; qla_drain_fp_taskqueues(ha); ql_del_hw_if(ha); qla_free_xmt_bufs(ha); qla_free_rcv_bufs(ha); return; } /* * Buffer Management Functions for Transmit and Receive Rings */ static int qla_alloc_xmt_bufs(qla_host_t *ha) { int ret = 0; uint32_t i, j; qla_tx_buf_t *txb; if (bus_dma_tag_create(NULL, /* parent */ 1, 0, /* alignment, bounds */ BUS_SPACE_MAXADDR, /* lowaddr */ BUS_SPACE_MAXADDR, /* highaddr */ NULL, NULL, /* filter, filterarg */ QLA_MAX_TSO_FRAME_SIZE, /* maxsize */ QLA_MAX_SEGMENTS, /* nsegments */ PAGE_SIZE, /* maxsegsize */ BUS_DMA_ALLOCNOW, /* flags */ NULL, /* lockfunc */ NULL, /* lockfuncarg */ &ha->tx_tag)) { device_printf(ha->pci_dev, "%s: tx_tag alloc failed\n", __func__); return (ENOMEM); } for (i = 0; i < ha->hw.num_tx_rings; i++) { bzero((void *)ha->tx_ring[i].tx_buf, (sizeof(qla_tx_buf_t) * NUM_TX_DESCRIPTORS)); } for (j = 0; j < ha->hw.num_tx_rings; j++) { for (i = 0; i < NUM_TX_DESCRIPTORS; i++) { txb = &ha->tx_ring[j].tx_buf[i]; if ((ret = bus_dmamap_create(ha->tx_tag, BUS_DMA_NOWAIT, &txb->map))) { ha->err_tx_dmamap_create++; device_printf(ha->pci_dev, "%s: bus_dmamap_create failed[%d]\n", __func__, ret); qla_free_xmt_bufs(ha); return (ret); } } } return 0; } /* * Release mbuf after it sent on the wire */ static void qla_clear_tx_buf(qla_host_t *ha, qla_tx_buf_t *txb) { QL_DPRINT2(ha, (ha->pci_dev, "%s: enter\n", __func__)); if (txb->m_head) { bus_dmamap_sync(ha->tx_tag, txb->map, BUS_DMASYNC_POSTWRITE); bus_dmamap_unload(ha->tx_tag, txb->map); m_freem(txb->m_head); txb->m_head = NULL; bus_dmamap_destroy(ha->tx_tag, txb->map); txb->map = NULL; } if (txb->map) { bus_dmamap_unload(ha->tx_tag, txb->map); bus_dmamap_destroy(ha->tx_tag, txb->map); txb->map = NULL; } QL_DPRINT2(ha, (ha->pci_dev, "%s: exit\n", __func__)); } static void qla_free_xmt_bufs(qla_host_t *ha) { int i, j; for (j = 0; j < ha->hw.num_tx_rings; j++) { for (i = 0; i < NUM_TX_DESCRIPTORS; i++) qla_clear_tx_buf(ha, &ha->tx_ring[j].tx_buf[i]); } if (ha->tx_tag != NULL) { bus_dma_tag_destroy(ha->tx_tag); ha->tx_tag = NULL; } for (i = 0; i < ha->hw.num_tx_rings; i++) { bzero((void *)ha->tx_ring[i].tx_buf, (sizeof(qla_tx_buf_t) * NUM_TX_DESCRIPTORS)); } return; } static int qla_alloc_rcv_std(qla_host_t *ha) { int i, j, k, r, ret = 0; qla_rx_buf_t *rxb; qla_rx_ring_t *rx_ring; for (r = 0; r < ha->hw.num_rds_rings; r++) { rx_ring = &ha->rx_ring[r]; for (i = 0; i < NUM_RX_DESCRIPTORS; i++) { rxb = &rx_ring->rx_buf[i]; ret = bus_dmamap_create(ha->rx_tag, BUS_DMA_NOWAIT, &rxb->map); if (ret) { device_printf(ha->pci_dev, "%s: dmamap[%d, %d] failed\n", __func__, r, i); for (k = 0; k < r; k++) { for (j = 0; j < NUM_RX_DESCRIPTORS; j++) { rxb = &ha->rx_ring[k].rx_buf[j]; bus_dmamap_destroy(ha->rx_tag, rxb->map); } } for (j = 0; j < i; j++) { bus_dmamap_destroy(ha->rx_tag, rx_ring->rx_buf[j].map); } goto qla_alloc_rcv_std_err; } } } qla_init_hw_rcv_descriptors(ha); for (r = 0; r < ha->hw.num_rds_rings; r++) { rx_ring = &ha->rx_ring[r]; for (i = 0; i < NUM_RX_DESCRIPTORS; i++) { rxb = &rx_ring->rx_buf[i]; rxb->handle = i; if (!(ret = ql_get_mbuf(ha, rxb, NULL))) { /* * set the physical address in the * corresponding descriptor entry in the * receive ring/queue for the hba */ qla_set_hw_rcv_desc(ha, r, i, rxb->handle, rxb->paddr, (rxb->m_head)->m_pkthdr.len); } else { device_printf(ha->pci_dev, "%s: ql_get_mbuf [%d, %d] failed\n", __func__, r, i); bus_dmamap_destroy(ha->rx_tag, rxb->map); goto qla_alloc_rcv_std_err; } } } return 0; qla_alloc_rcv_std_err: return (-1); } static void qla_free_rcv_std(qla_host_t *ha) { int i, r; qla_rx_buf_t *rxb; for (r = 0; r < ha->hw.num_rds_rings; r++) { for (i = 0; i < NUM_RX_DESCRIPTORS; i++) { rxb = &ha->rx_ring[r].rx_buf[i]; if (rxb->m_head != NULL) { bus_dmamap_unload(ha->rx_tag, rxb->map); bus_dmamap_destroy(ha->rx_tag, rxb->map); m_freem(rxb->m_head); rxb->m_head = NULL; } } } return; } static int qla_alloc_rcv_bufs(qla_host_t *ha) { int i, ret = 0; if (bus_dma_tag_create(NULL, /* parent */ 1, 0, /* alignment, bounds */ BUS_SPACE_MAXADDR, /* lowaddr */ BUS_SPACE_MAXADDR, /* highaddr */ NULL, NULL, /* filter, filterarg */ MJUM9BYTES, /* maxsize */ 1, /* nsegments */ MJUM9BYTES, /* maxsegsize */ BUS_DMA_ALLOCNOW, /* flags */ NULL, /* lockfunc */ NULL, /* lockfuncarg */ &ha->rx_tag)) { device_printf(ha->pci_dev, "%s: rx_tag alloc failed\n", __func__); return (ENOMEM); } bzero((void *)ha->rx_ring, (sizeof(qla_rx_ring_t) * MAX_RDS_RINGS)); for (i = 0; i < ha->hw.num_sds_rings; i++) { ha->hw.sds[i].sdsr_next = 0; ha->hw.sds[i].rxb_free = NULL; ha->hw.sds[i].rx_free = 0; } ret = qla_alloc_rcv_std(ha); return (ret); } static void qla_free_rcv_bufs(qla_host_t *ha) { int i; qla_free_rcv_std(ha); if (ha->rx_tag != NULL) { bus_dma_tag_destroy(ha->rx_tag); ha->rx_tag = NULL; } bzero((void *)ha->rx_ring, (sizeof(qla_rx_ring_t) * MAX_RDS_RINGS)); for (i = 0; i < ha->hw.num_sds_rings; i++) { ha->hw.sds[i].sdsr_next = 0; ha->hw.sds[i].rxb_free = NULL; ha->hw.sds[i].rx_free = 0; } return; } int ql_get_mbuf(qla_host_t *ha, qla_rx_buf_t *rxb, struct mbuf *nmp) { register struct mbuf *mp = nmp; struct ifnet *ifp; int ret = 0; uint32_t offset; bus_dma_segment_t segs[1]; int nsegs, mbuf_size; QL_DPRINT2(ha, (ha->pci_dev, "%s: enter\n", __func__)); ifp = ha->ifp; if (ha->hw.enable_9kb) mbuf_size = MJUM9BYTES; else mbuf_size = MCLBYTES; if (mp == NULL) { if (QL_ERR_INJECT(ha, INJCT_M_GETCL_M_GETJCL_FAILURE)) return(-1); if (ha->hw.enable_9kb) mp = m_getjcl(M_NOWAIT, MT_DATA, M_PKTHDR, mbuf_size); else mp = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR); if (mp == NULL) { ha->err_m_getcl++; ret = ENOBUFS; device_printf(ha->pci_dev, "%s: m_getcl failed\n", __func__); goto exit_ql_get_mbuf; } mp->m_len = mp->m_pkthdr.len = mbuf_size; } else { mp->m_len = mp->m_pkthdr.len = mbuf_size; mp->m_data = mp->m_ext.ext_buf; mp->m_next = NULL; } offset = (uint32_t)((unsigned long long)mp->m_data & 0x7ULL); if (offset) { offset = 8 - offset; m_adj(mp, offset); } /* * Using memory from the mbuf cluster pool, invoke the bus_dma * machinery to arrange the memory mapping. */ ret = bus_dmamap_load_mbuf_sg(ha->rx_tag, rxb->map, mp, segs, &nsegs, BUS_DMA_NOWAIT); rxb->paddr = segs[0].ds_addr; if (ret || !rxb->paddr || (nsegs != 1)) { m_free(mp); rxb->m_head = NULL; device_printf(ha->pci_dev, "%s: bus_dmamap_load failed[%d, 0x%016llx, %d]\n", __func__, ret, (long long unsigned int)rxb->paddr, nsegs); ret = -1; goto exit_ql_get_mbuf; } rxb->m_head = mp; bus_dmamap_sync(ha->rx_tag, rxb->map, BUS_DMASYNC_PREREAD); exit_ql_get_mbuf: QL_DPRINT2(ha, (ha->pci_dev, "%s: exit ret = 0x%08x\n", __func__, ret)); return (ret); } static void qla_get_peer(qla_host_t *ha) { device_t *peers; int count, i, slot; int my_slot = pci_get_slot(ha->pci_dev); if (device_get_children(device_get_parent(ha->pci_dev), &peers, &count)) return; for (i = 0; i < count; i++) { slot = pci_get_slot(peers[i]); if ((slot >= 0) && (slot == my_slot) && (pci_get_device(peers[i]) == pci_get_device(ha->pci_dev))) { if (ha->pci_dev != peers[i]) ha->peer_dev = peers[i]; } } } static void qla_send_msg_to_peer(qla_host_t *ha, uint32_t msg_to_peer) { qla_host_t *ha_peer; if (ha->peer_dev) { if ((ha_peer = device_get_softc(ha->peer_dev)) != NULL) { ha_peer->msg_from_peer = msg_to_peer; } } } static void qla_error_recovery(void *context, int pending) { qla_host_t *ha = context; uint32_t msecs_100 = 100; struct ifnet *ifp = ha->ifp; int i = 0; device_printf(ha->pci_dev, "%s: \n", __func__); ha->hw.imd_compl = 1; if (QLA_LOCK(ha, __func__, -1, 0) != 0) return; device_printf(ha->pci_dev, "%s: enter\n", __func__); if (ha->qla_interface_up) { qla_mdelay(__func__, 300); ifp->if_drv_flags &= ~IFF_DRV_RUNNING; for (i = 0; i < ha->hw.num_sds_rings; i++) { qla_tx_fp_t *fp; fp = &ha->tx_fp[i]; if (fp == NULL) continue; if (fp->tx_br != NULL) { mtx_lock(&fp->tx_mtx); mtx_unlock(&fp->tx_mtx); } } } qla_drain_fp_taskqueues(ha); if ((ha->pci_func & 0x1) == 0) { if (!ha->msg_from_peer) { qla_send_msg_to_peer(ha, QL_PEER_MSG_RESET); while ((ha->msg_from_peer != QL_PEER_MSG_ACK) && msecs_100--) qla_mdelay(__func__, 100); } ha->msg_from_peer = 0; if (ha->enable_minidump) ql_minidump(ha); (void) ql_init_hw(ha); if (ha->qla_interface_up) { qla_free_xmt_bufs(ha); qla_free_rcv_bufs(ha); } qla_send_msg_to_peer(ha, QL_PEER_MSG_ACK); } else { if (ha->msg_from_peer == QL_PEER_MSG_RESET) { ha->msg_from_peer = 0; qla_send_msg_to_peer(ha, QL_PEER_MSG_ACK); } else { qla_send_msg_to_peer(ha, QL_PEER_MSG_RESET); } while ((ha->msg_from_peer != QL_PEER_MSG_ACK) && msecs_100--) qla_mdelay(__func__, 100); ha->msg_from_peer = 0; (void) ql_init_hw(ha); qla_mdelay(__func__, 1000); if (ha->qla_interface_up) { qla_free_xmt_bufs(ha); qla_free_rcv_bufs(ha); } } if (ha->qla_interface_up) { if (qla_alloc_xmt_bufs(ha) != 0) { goto qla_error_recovery_exit; } qla_confirm_9kb_enable(ha); if (qla_alloc_rcv_bufs(ha) != 0) { goto qla_error_recovery_exit; } ha->stop_rcv = 0; if (ql_init_hw_if(ha) == 0) { ifp = ha->ifp; ifp->if_drv_flags |= IFF_DRV_RUNNING; ha->qla_watchdog_pause = 0; } } else ha->qla_watchdog_pause = 0; qla_error_recovery_exit: device_printf(ha->pci_dev, "%s: exit\n", __func__); QLA_UNLOCK(ha, __func__); callout_reset(&ha->tx_callout, QLA_WATCHDOG_CALLOUT_TICKS, qla_watchdog, ha); return; } static void qla_async_event(void *context, int pending) { qla_host_t *ha = context; if (QLA_LOCK(ha, __func__, -1, 0) != 0) return; if (ha->async_event) { ha->async_event = 0; qla_hw_async_event(ha); } QLA_UNLOCK(ha, __func__); return; } static void qla_stats(void *context, int pending) { qla_host_t *ha; ha = context; ql_get_stats(ha); return; } Index: stable/11/sys/dev/qlxgbe/ql_ver.h =================================================================== --- stable/11/sys/dev/qlxgbe/ql_ver.h (revision 324761) +++ stable/11/sys/dev/qlxgbe/ql_ver.h (revision 324762) @@ -1,41 +1,41 @@ /* * Copyright (c) 2013-2016 Qlogic Corporation * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE * POSSIBILITY OF SUCH DAMAGE. * * $FreeBSD$ */ /* * File: ql_ver.h * Author : David C Somayajulu, Qlogic Corporation, Aliso Viejo, CA 92656. */ #ifndef _QL_VER_H_ #define _QL_VER_H_ #define QLA_VERSION_MAJOR 3 #define QLA_VERSION_MINOR 10 -#define QLA_VERSION_BUILD 34 +#define QLA_VERSION_BUILD 35 #endif /* #ifndef _QL_VER_H_ */ Index: stable/11 =================================================================== --- stable/11 (revision 324761) +++ stable/11 (revision 324762) Property changes on: stable/11 ___________________________________________________________________ Modified: svn:mergeinfo ## -0,0 +0,1 ## Merged /head:r324538