Index: head/sys/arm/broadcom/bcm2835/bcm2835_sdhci.c =================================================================== --- head/sys/arm/broadcom/bcm2835/bcm2835_sdhci.c (revision 323965) +++ head/sys/arm/broadcom/bcm2835/bcm2835_sdhci.c (revision 323966) @@ -1,690 +1,686 @@ /*- * Copyright (c) 2012 Oleksandr Tymoshenko * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. * */ #include __FBSDID("$FreeBSD$"); #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include "mmcbr_if.h" #include "sdhci_if.h" #include "opt_mmccam.h" #include "bcm2835_dma.h" #include #include "bcm2835_vcbus.h" #define BCM2835_DEFAULT_SDHCI_FREQ 50 #define BCM_SDHCI_BUFFER_SIZE 512 #define NUM_DMA_SEGS 2 #ifdef DEBUG #define dprintf(fmt, args...) do { printf("%s(): ", __func__); \ printf(fmt,##args); } while (0) #else #define dprintf(fmt, args...) #endif static int bcm2835_sdhci_hs = 1; static int bcm2835_sdhci_pio_mode = 0; static struct ofw_compat_data compat_data[] = { {"broadcom,bcm2835-sdhci", 1}, {"brcm,bcm2835-mmc", 1}, {NULL, 0} }; TUNABLE_INT("hw.bcm2835.sdhci.hs", &bcm2835_sdhci_hs); TUNABLE_INT("hw.bcm2835.sdhci.pio_mode", &bcm2835_sdhci_pio_mode); struct bcm_sdhci_softc { device_t sc_dev; struct resource * sc_mem_res; struct resource * sc_irq_res; bus_space_tag_t sc_bst; bus_space_handle_t sc_bsh; void * sc_intrhand; struct mmc_request * sc_req; struct sdhci_slot sc_slot; int sc_dma_ch; bus_dma_tag_t sc_dma_tag; bus_dmamap_t sc_dma_map; vm_paddr_t sc_sdhci_buffer_phys; uint32_t cmd_and_mode; bus_addr_t dmamap_seg_addrs[NUM_DMA_SEGS]; bus_size_t dmamap_seg_sizes[NUM_DMA_SEGS]; int dmamap_seg_count; int dmamap_seg_index; int dmamap_status; }; static int bcm_sdhci_probe(device_t); static int bcm_sdhci_attach(device_t); static int bcm_sdhci_detach(device_t); static void bcm_sdhci_intr(void *); static int bcm_sdhci_get_ro(device_t, device_t); static void bcm_sdhci_dma_intr(int ch, void *arg); static void bcm_sdhci_dmacb(void *arg, bus_dma_segment_t *segs, int nseg, int err) { struct bcm_sdhci_softc *sc = arg; int i; sc->dmamap_status = err; sc->dmamap_seg_count = nseg; /* Note nseg is guaranteed to be zero if err is non-zero. */ for (i = 0; i < nseg; i++) { sc->dmamap_seg_addrs[i] = segs[i].ds_addr; sc->dmamap_seg_sizes[i] = segs[i].ds_len; } } static int bcm_sdhci_probe(device_t dev) { if (!ofw_bus_status_okay(dev)) return (ENXIO); if (ofw_bus_search_compatible(dev, compat_data)->ocd_data == 0) return (ENXIO); device_set_desc(dev, "Broadcom 2708 SDHCI controller"); return (BUS_PROBE_DEFAULT); } static int bcm_sdhci_attach(device_t dev) { struct bcm_sdhci_softc *sc = device_get_softc(dev); int rid, err; phandle_t node; pcell_t cell; u_int default_freq; sc->sc_dev = dev; sc->sc_req = NULL; err = bcm2835_mbox_set_power_state(BCM2835_MBOX_POWER_ID_EMMC, TRUE); if (err != 0) { if (bootverbose) device_printf(dev, "Unable to enable the power\n"); return (err); } default_freq = 0; err = bcm2835_mbox_get_clock_rate(BCM2835_MBOX_CLOCK_ID_EMMC, &default_freq); if (err == 0) { /* Convert to MHz */ default_freq /= 1000000; } if (default_freq == 0) { node = ofw_bus_get_node(sc->sc_dev); if ((OF_getencprop(node, "clock-frequency", &cell, sizeof(cell))) > 0) default_freq = cell / 1000000; } if (default_freq == 0) default_freq = BCM2835_DEFAULT_SDHCI_FREQ; if (bootverbose) device_printf(dev, "SDHCI frequency: %dMHz\n", default_freq); rid = 0; sc->sc_mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, RF_ACTIVE); if (!sc->sc_mem_res) { device_printf(dev, "cannot allocate memory window\n"); err = ENXIO; goto fail; } sc->sc_bst = rman_get_bustag(sc->sc_mem_res); sc->sc_bsh = rman_get_bushandle(sc->sc_mem_res); rid = 0; sc->sc_irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, RF_ACTIVE); if (!sc->sc_irq_res) { device_printf(dev, "cannot allocate interrupt\n"); err = ENXIO; goto fail; } if (bus_setup_intr(dev, sc->sc_irq_res, INTR_TYPE_BIO | INTR_MPSAFE, NULL, bcm_sdhci_intr, sc, &sc->sc_intrhand)) { device_printf(dev, "cannot setup interrupt handler\n"); err = ENXIO; goto fail; } if (!bcm2835_sdhci_pio_mode) sc->sc_slot.opt = SDHCI_PLATFORM_TRANSFER; sc->sc_slot.caps = SDHCI_CAN_VDD_330 | SDHCI_CAN_VDD_180; if (bcm2835_sdhci_hs) sc->sc_slot.caps |= SDHCI_CAN_DO_HISPD; sc->sc_slot.caps |= (default_freq << SDHCI_CLOCK_BASE_SHIFT); sc->sc_slot.quirks = SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK | SDHCI_QUIRK_BROKEN_TIMEOUT_VAL | SDHCI_QUIRK_DONT_SET_HISPD_BIT | SDHCI_QUIRK_MISSING_CAPS; sdhci_init_slot(dev, &sc->sc_slot, 0); sc->sc_dma_ch = bcm_dma_allocate(BCM_DMA_CH_ANY); if (sc->sc_dma_ch == BCM_DMA_CH_INVALID) goto fail; bcm_dma_setup_intr(sc->sc_dma_ch, bcm_sdhci_dma_intr, sc); /* Allocate bus_dma resources. */ err = bus_dma_tag_create(bus_get_dma_tag(dev), 1, 0, BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, BCM_SDHCI_BUFFER_SIZE, NUM_DMA_SEGS, BCM_SDHCI_BUFFER_SIZE, BUS_DMA_ALLOCNOW, NULL, NULL, &sc->sc_dma_tag); if (err) { device_printf(dev, "failed allocate DMA tag"); goto fail; } err = bus_dmamap_create(sc->sc_dma_tag, 0, &sc->sc_dma_map); if (err) { device_printf(dev, "bus_dmamap_create failed\n"); goto fail; } /* FIXME: Fix along with other BUS_SPACE_PHYSADDR instances */ sc->sc_sdhci_buffer_phys = rman_get_start(sc->sc_mem_res) + SDHCI_BUFFER; bus_generic_probe(dev); bus_generic_attach(dev); -#ifdef MMCCAM - sdhci_cam_start_slot(&sc->sc_slot); -#else sdhci_start_slot(&sc->sc_slot); -#endif return (0); fail: if (sc->sc_intrhand) bus_teardown_intr(dev, sc->sc_irq_res, sc->sc_intrhand); if (sc->sc_irq_res) bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sc_irq_res); if (sc->sc_mem_res) bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->sc_mem_res); return (err); } static int bcm_sdhci_detach(device_t dev) { return (EBUSY); } static void bcm_sdhci_intr(void *arg) { struct bcm_sdhci_softc *sc = arg; sdhci_generic_intr(&sc->sc_slot); } static int bcm_sdhci_get_ro(device_t bus, device_t child) { return (0); } static inline uint32_t RD4(struct bcm_sdhci_softc *sc, bus_size_t off) { uint32_t val = bus_space_read_4(sc->sc_bst, sc->sc_bsh, off); return val; } static inline void WR4(struct bcm_sdhci_softc *sc, bus_size_t off, uint32_t val) { bus_space_write_4(sc->sc_bst, sc->sc_bsh, off, val); /* * The Arasan HC has a bug where it may lose the content of * consecutive writes to registers that are within two SD-card * clock cycles of each other (a clock domain crossing problem). */ if (sc->sc_slot.clock > 0) DELAY(((2 * 1000000) / sc->sc_slot.clock) + 1); } static uint8_t bcm_sdhci_read_1(device_t dev, struct sdhci_slot *slot, bus_size_t off) { struct bcm_sdhci_softc *sc = device_get_softc(dev); uint32_t val = RD4(sc, off & ~3); return ((val >> (off & 3)*8) & 0xff); } static uint16_t bcm_sdhci_read_2(device_t dev, struct sdhci_slot *slot, bus_size_t off) { struct bcm_sdhci_softc *sc = device_get_softc(dev); uint32_t val = RD4(sc, off & ~3); /* * Standard 32-bit handling of command and transfer mode. */ if (off == SDHCI_TRANSFER_MODE) { return (sc->cmd_and_mode >> 16); } else if (off == SDHCI_COMMAND_FLAGS) { return (sc->cmd_and_mode & 0x0000ffff); } return ((val >> (off & 3)*8) & 0xffff); } static uint32_t bcm_sdhci_read_4(device_t dev, struct sdhci_slot *slot, bus_size_t off) { struct bcm_sdhci_softc *sc = device_get_softc(dev); return RD4(sc, off); } static void bcm_sdhci_read_multi_4(device_t dev, struct sdhci_slot *slot, bus_size_t off, uint32_t *data, bus_size_t count) { struct bcm_sdhci_softc *sc = device_get_softc(dev); bus_space_read_multi_4(sc->sc_bst, sc->sc_bsh, off, data, count); } static void bcm_sdhci_write_1(device_t dev, struct sdhci_slot *slot, bus_size_t off, uint8_t val) { struct bcm_sdhci_softc *sc = device_get_softc(dev); uint32_t val32 = RD4(sc, off & ~3); val32 &= ~(0xff << (off & 3)*8); val32 |= (val << (off & 3)*8); WR4(sc, off & ~3, val32); } static void bcm_sdhci_write_2(device_t dev, struct sdhci_slot *slot, bus_size_t off, uint16_t val) { struct bcm_sdhci_softc *sc = device_get_softc(dev); uint32_t val32; if (off == SDHCI_COMMAND_FLAGS) val32 = sc->cmd_and_mode; else val32 = RD4(sc, off & ~3); val32 &= ~(0xffff << (off & 3)*8); val32 |= (val << (off & 3)*8); if (off == SDHCI_TRANSFER_MODE) sc->cmd_and_mode = val32; else { WR4(sc, off & ~3, val32); if (off == SDHCI_COMMAND_FLAGS) sc->cmd_and_mode = val32; } } static void bcm_sdhci_write_4(device_t dev, struct sdhci_slot *slot, bus_size_t off, uint32_t val) { struct bcm_sdhci_softc *sc = device_get_softc(dev); WR4(sc, off, val); } static void bcm_sdhci_write_multi_4(device_t dev, struct sdhci_slot *slot, bus_size_t off, uint32_t *data, bus_size_t count) { struct bcm_sdhci_softc *sc = device_get_softc(dev); bus_space_write_multi_4(sc->sc_bst, sc->sc_bsh, off, data, count); } static void bcm_sdhci_start_dma_seg(struct bcm_sdhci_softc *sc) { struct sdhci_slot *slot; vm_paddr_t pdst, psrc; int err, idx, len, sync_op; slot = &sc->sc_slot; idx = sc->dmamap_seg_index++; len = sc->dmamap_seg_sizes[idx]; slot->offset += len; if (slot->curcmd->data->flags & MMC_DATA_READ) { bcm_dma_setup_src(sc->sc_dma_ch, BCM_DMA_DREQ_EMMC, BCM_DMA_SAME_ADDR, BCM_DMA_32BIT); bcm_dma_setup_dst(sc->sc_dma_ch, BCM_DMA_DREQ_NONE, BCM_DMA_INC_ADDR, (len & 0xf) ? BCM_DMA_32BIT : BCM_DMA_128BIT); psrc = sc->sc_sdhci_buffer_phys; pdst = sc->dmamap_seg_addrs[idx]; sync_op = BUS_DMASYNC_PREREAD; } else { bcm_dma_setup_src(sc->sc_dma_ch, BCM_DMA_DREQ_NONE, BCM_DMA_INC_ADDR, (len & 0xf) ? BCM_DMA_32BIT : BCM_DMA_128BIT); bcm_dma_setup_dst(sc->sc_dma_ch, BCM_DMA_DREQ_EMMC, BCM_DMA_SAME_ADDR, BCM_DMA_32BIT); psrc = sc->dmamap_seg_addrs[idx]; pdst = sc->sc_sdhci_buffer_phys; sync_op = BUS_DMASYNC_PREWRITE; } /* * When starting a new DMA operation do the busdma sync operation, and * disable SDCHI data interrrupts because we'll be driven by DMA * interrupts (or SDHCI error interrupts) until the IO is done. */ if (idx == 0) { bus_dmamap_sync(sc->sc_dma_tag, sc->sc_dma_map, sync_op); slot->intmask &= ~(SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL | SDHCI_INT_DATA_END); bcm_sdhci_write_4(sc->sc_dev, &sc->sc_slot, SDHCI_SIGNAL_ENABLE, slot->intmask); } /* * Start the DMA transfer. Only programming errors (like failing to * allocate a channel) cause a non-zero return from bcm_dma_start(). */ err = bcm_dma_start(sc->sc_dma_ch, psrc, pdst, len); KASSERT((err == 0), ("bcm2835_sdhci: failed DMA start")); } static void bcm_sdhci_dma_intr(int ch, void *arg) { struct bcm_sdhci_softc *sc = (struct bcm_sdhci_softc *)arg; struct sdhci_slot *slot = &sc->sc_slot; uint32_t reg, mask; int left, sync_op; mtx_lock(&slot->mtx); /* * If there are more segments for the current dma, start the next one. * Otherwise unload the dma map and decide what to do next based on the * status of the sdhci controller and whether there's more data left. */ if (sc->dmamap_seg_index < sc->dmamap_seg_count) { bcm_sdhci_start_dma_seg(sc); mtx_unlock(&slot->mtx); return; } if (slot->curcmd->data->flags & MMC_DATA_READ) { sync_op = BUS_DMASYNC_POSTREAD; mask = SDHCI_INT_DATA_AVAIL; } else { sync_op = BUS_DMASYNC_POSTWRITE; mask = SDHCI_INT_SPACE_AVAIL; } bus_dmamap_sync(sc->sc_dma_tag, sc->sc_dma_map, sync_op); bus_dmamap_unload(sc->sc_dma_tag, sc->sc_dma_map); sc->dmamap_seg_count = 0; sc->dmamap_seg_index = 0; left = min(BCM_SDHCI_BUFFER_SIZE, slot->curcmd->data->len - slot->offset); /* DATA END? */ reg = bcm_sdhci_read_4(slot->bus, slot, SDHCI_INT_STATUS); if (reg & SDHCI_INT_DATA_END) { /* ACK for all outstanding interrupts */ bcm_sdhci_write_4(slot->bus, slot, SDHCI_INT_STATUS, reg); /* enable INT */ slot->intmask |= SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL | SDHCI_INT_DATA_END; bcm_sdhci_write_4(slot->bus, slot, SDHCI_SIGNAL_ENABLE, slot->intmask); /* finish this data */ sdhci_finish_data(slot); } else { /* already available? */ if (reg & mask) { /* ACK for DATA_AVAIL or SPACE_AVAIL */ bcm_sdhci_write_4(slot->bus, slot, SDHCI_INT_STATUS, mask); /* continue next DMA transfer */ if (bus_dmamap_load(sc->sc_dma_tag, sc->sc_dma_map, (uint8_t *)slot->curcmd->data->data + slot->offset, left, bcm_sdhci_dmacb, sc, BUS_DMA_NOWAIT) != 0 || sc->dmamap_status != 0) { slot->curcmd->error = MMC_ERR_NO_MEMORY; sdhci_finish_data(slot); } else { bcm_sdhci_start_dma_seg(sc); } } else { /* wait for next data by INT */ /* enable INT */ slot->intmask |= SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL | SDHCI_INT_DATA_END; bcm_sdhci_write_4(slot->bus, slot, SDHCI_SIGNAL_ENABLE, slot->intmask); } } mtx_unlock(&slot->mtx); } static void bcm_sdhci_read_dma(device_t dev, struct sdhci_slot *slot) { struct bcm_sdhci_softc *sc = device_get_softc(slot->bus); size_t left; if (sc->dmamap_seg_count != 0) { device_printf(sc->sc_dev, "DMA in use\n"); return; } left = min(BCM_SDHCI_BUFFER_SIZE, slot->curcmd->data->len - slot->offset); KASSERT((left & 3) == 0, ("%s: len = %zu, not word-aligned", __func__, left)); if (bus_dmamap_load(sc->sc_dma_tag, sc->sc_dma_map, (uint8_t *)slot->curcmd->data->data + slot->offset, left, bcm_sdhci_dmacb, sc, BUS_DMA_NOWAIT) != 0 || sc->dmamap_status != 0) { slot->curcmd->error = MMC_ERR_NO_MEMORY; return; } /* DMA start */ bcm_sdhci_start_dma_seg(sc); } static void bcm_sdhci_write_dma(device_t dev, struct sdhci_slot *slot) { struct bcm_sdhci_softc *sc = device_get_softc(slot->bus); size_t left; if (sc->dmamap_seg_count != 0) { device_printf(sc->sc_dev, "DMA in use\n"); return; } left = min(BCM_SDHCI_BUFFER_SIZE, slot->curcmd->data->len - slot->offset); KASSERT((left & 3) == 0, ("%s: len = %zu, not word-aligned", __func__, left)); if (bus_dmamap_load(sc->sc_dma_tag, sc->sc_dma_map, (uint8_t *)slot->curcmd->data->data + slot->offset, left, bcm_sdhci_dmacb, sc, BUS_DMA_NOWAIT) != 0 || sc->dmamap_status != 0) { slot->curcmd->error = MMC_ERR_NO_MEMORY; return; } /* DMA start */ bcm_sdhci_start_dma_seg(sc); } static int bcm_sdhci_will_handle_transfer(device_t dev, struct sdhci_slot *slot) { size_t left; /* * Do not use DMA for transfers less than block size or with a length * that is not a multiple of four. */ left = min(BCM_DMA_BLOCK_SIZE, slot->curcmd->data->len - slot->offset); if (left < BCM_DMA_BLOCK_SIZE) return (0); if (left & 0x03) return (0); return (1); } static void bcm_sdhci_start_transfer(device_t dev, struct sdhci_slot *slot, uint32_t *intmask) { /* DMA transfer FIFO 1KB */ if (slot->curcmd->data->flags & MMC_DATA_READ) bcm_sdhci_read_dma(dev, slot); else bcm_sdhci_write_dma(dev, slot); } static void bcm_sdhci_finish_transfer(device_t dev, struct sdhci_slot *slot) { sdhci_finish_data(slot); } static device_method_t bcm_sdhci_methods[] = { /* Device interface */ DEVMETHOD(device_probe, bcm_sdhci_probe), DEVMETHOD(device_attach, bcm_sdhci_attach), DEVMETHOD(device_detach, bcm_sdhci_detach), /* Bus interface */ DEVMETHOD(bus_read_ivar, sdhci_generic_read_ivar), DEVMETHOD(bus_write_ivar, sdhci_generic_write_ivar), /* MMC bridge interface */ DEVMETHOD(mmcbr_update_ios, sdhci_generic_update_ios), DEVMETHOD(mmcbr_request, sdhci_generic_request), DEVMETHOD(mmcbr_get_ro, bcm_sdhci_get_ro), DEVMETHOD(mmcbr_acquire_host, sdhci_generic_acquire_host), DEVMETHOD(mmcbr_release_host, sdhci_generic_release_host), /* Platform transfer methods */ DEVMETHOD(sdhci_platform_will_handle, bcm_sdhci_will_handle_transfer), DEVMETHOD(sdhci_platform_start_transfer, bcm_sdhci_start_transfer), DEVMETHOD(sdhci_platform_finish_transfer, bcm_sdhci_finish_transfer), /* SDHCI registers accessors */ DEVMETHOD(sdhci_read_1, bcm_sdhci_read_1), DEVMETHOD(sdhci_read_2, bcm_sdhci_read_2), DEVMETHOD(sdhci_read_4, bcm_sdhci_read_4), DEVMETHOD(sdhci_read_multi_4, bcm_sdhci_read_multi_4), DEVMETHOD(sdhci_write_1, bcm_sdhci_write_1), DEVMETHOD(sdhci_write_2, bcm_sdhci_write_2), DEVMETHOD(sdhci_write_4, bcm_sdhci_write_4), DEVMETHOD(sdhci_write_multi_4, bcm_sdhci_write_multi_4), DEVMETHOD_END }; static devclass_t bcm_sdhci_devclass; static driver_t bcm_sdhci_driver = { "sdhci_bcm", bcm_sdhci_methods, sizeof(struct bcm_sdhci_softc), }; DRIVER_MODULE(sdhci_bcm, simplebus, bcm_sdhci_driver, bcm_sdhci_devclass, NULL, NULL); MODULE_DEPEND(sdhci_bcm, sdhci, 1, 1, 1); #ifndef MMCCAM MMC_DECLARE_BRIDGE(sdhci_bcm); #endif Index: head/sys/arm/ti/ti_sdhci.c =================================================================== --- head/sys/arm/ti/ti_sdhci.c (revision 323965) +++ head/sys/arm/ti/ti_sdhci.c (revision 323966) @@ -1,764 +1,760 @@ /*- * Copyright (c) 2013 Ian Lepore * Copyright (c) 2011 Ben Gray . * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. * */ #include __FBSDID("$FreeBSD$"); #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include "sdhci_if.h" #include #include #include #include "gpio_if.h" #include "opt_mmccam.h" struct ti_sdhci_softc { device_t dev; struct sdhci_fdt_gpio * gpio; struct resource * mem_res; struct resource * irq_res; void * intr_cookie; struct sdhci_slot slot; clk_ident_t mmchs_clk_id; uint32_t mmchs_reg_off; uint32_t sdhci_reg_off; uint32_t baseclk_hz; uint32_t cmd_and_mode; uint32_t sdhci_clkdiv; boolean_t disable_highspeed; boolean_t force_card_present; boolean_t disable_readonly; }; /* * Table of supported FDT compat strings. * * Note that "ti,mmchs" is our own invention, and should be phased out in favor * of the documented names. * * Note that vendor Beaglebone dtsi files use "ti,omap3-hsmmc" for the am335x. */ static struct ofw_compat_data compat_data[] = { {"ti,omap3-hsmmc", 1}, {"ti,omap4-hsmmc", 1}, {"ti,mmchs", 1}, {NULL, 0}, }; /* * The MMCHS hardware has a few control and status registers at the beginning of * the device's memory map, followed by the standard sdhci register block. * Different SoCs have the register blocks at different offsets from the * beginning of the device. Define some constants to map out the registers we * access, and the various per-SoC offsets. The SDHCI_REG_OFFSET is how far * beyond the MMCHS block the SDHCI block is found; it's the same on all SoCs. */ #define OMAP3_MMCHS_REG_OFFSET 0x000 #define OMAP4_MMCHS_REG_OFFSET 0x100 #define AM335X_MMCHS_REG_OFFSET 0x100 #define SDHCI_REG_OFFSET 0x100 #define MMCHS_SYSCONFIG 0x010 #define MMCHS_SYSCONFIG_RESET (1 << 1) #define MMCHS_SYSSTATUS 0x014 #define MMCHS_SYSSTATUS_RESETDONE (1 << 0) #define MMCHS_CON 0x02C #define MMCHS_CON_DW8 (1 << 5) #define MMCHS_CON_DVAL_8_4MS (3 << 9) #define MMCHS_CON_OD (1 << 0) #define MMCHS_SYSCTL 0x12C #define MMCHS_SYSCTL_CLKD_MASK 0x3FF #define MMCHS_SYSCTL_CLKD_SHIFT 6 #define MMCHS_SD_CAPA 0x140 #define MMCHS_SD_CAPA_VS18 (1 << 26) #define MMCHS_SD_CAPA_VS30 (1 << 25) #define MMCHS_SD_CAPA_VS33 (1 << 24) /* Forward declarations, CAM-relataed */ // static void ti_sdhci_cam_poll(struct cam_sim *); // static void ti_sdhci_cam_action(struct cam_sim *, union ccb *); // static int ti_sdhci_cam_settran_settings(struct ti_sdhci_softc *sc, union ccb *); static inline uint32_t ti_mmchs_read_4(struct ti_sdhci_softc *sc, bus_size_t off) { return (bus_read_4(sc->mem_res, off + sc->mmchs_reg_off)); } static inline void ti_mmchs_write_4(struct ti_sdhci_softc *sc, bus_size_t off, uint32_t val) { bus_write_4(sc->mem_res, off + sc->mmchs_reg_off, val); } static inline uint32_t RD4(struct ti_sdhci_softc *sc, bus_size_t off) { return (bus_read_4(sc->mem_res, off + sc->sdhci_reg_off)); } static inline void WR4(struct ti_sdhci_softc *sc, bus_size_t off, uint32_t val) { bus_write_4(sc->mem_res, off + sc->sdhci_reg_off, val); } static uint8_t ti_sdhci_read_1(device_t dev, struct sdhci_slot *slot, bus_size_t off) { struct ti_sdhci_softc *sc = device_get_softc(dev); return ((RD4(sc, off & ~3) >> (off & 3) * 8) & 0xff); } static uint16_t ti_sdhci_read_2(device_t dev, struct sdhci_slot *slot, bus_size_t off) { struct ti_sdhci_softc *sc = device_get_softc(dev); uint32_t clkdiv, val32; /* * The MMCHS hardware has a non-standard interpretation of the sdclock * divisor bits. It uses the same bit positions as SDHCI 3.0 (15..6) * but doesn't split them into low:high fields. Instead they're a * single number in the range 0..1023 and the number is exactly the * clock divisor (with 0 and 1 both meaning divide by 1). The SDHCI * driver code expects a v2.0 or v3.0 divisor. The shifting and masking * here extracts the MMCHS representation from the hardware word, cleans * those bits out, applies the 2N adjustment, and plugs the result into * the bit positions for the 2.0 or 3.0 divisor in the returned register * value. The ti_sdhci_write_2() routine performs the opposite * transformation when the SDHCI driver writes to the register. */ if (off == SDHCI_CLOCK_CONTROL) { val32 = RD4(sc, SDHCI_CLOCK_CONTROL); clkdiv = ((val32 >> MMCHS_SYSCTL_CLKD_SHIFT) & MMCHS_SYSCTL_CLKD_MASK) / 2; val32 &= ~(MMCHS_SYSCTL_CLKD_MASK << MMCHS_SYSCTL_CLKD_SHIFT); val32 |= (clkdiv & SDHCI_DIVIDER_MASK) << SDHCI_DIVIDER_SHIFT; if (slot->version >= SDHCI_SPEC_300) val32 |= ((clkdiv >> SDHCI_DIVIDER_MASK_LEN) & SDHCI_DIVIDER_HI_MASK) << SDHCI_DIVIDER_HI_SHIFT; return (val32 & 0xffff); } /* * Standard 32-bit handling of command and transfer mode. */ if (off == SDHCI_TRANSFER_MODE) { return (sc->cmd_and_mode >> 16); } else if (off == SDHCI_COMMAND_FLAGS) { return (sc->cmd_and_mode & 0x0000ffff); } return ((RD4(sc, off & ~3) >> (off & 3) * 8) & 0xffff); } static uint32_t ti_sdhci_read_4(device_t dev, struct sdhci_slot *slot, bus_size_t off) { struct ti_sdhci_softc *sc = device_get_softc(dev); uint32_t val32; val32 = RD4(sc, off); /* * If we need to disallow highspeed mode due to the OMAP4 erratum, strip * that flag from the returned capabilities. */ if (off == SDHCI_CAPABILITIES && sc->disable_highspeed) val32 &= ~SDHCI_CAN_DO_HISPD; /* * Force the card-present state if necessary. */ if (off == SDHCI_PRESENT_STATE && sc->force_card_present) val32 |= SDHCI_CARD_PRESENT; return (val32); } static void ti_sdhci_read_multi_4(device_t dev, struct sdhci_slot *slot, bus_size_t off, uint32_t *data, bus_size_t count) { struct ti_sdhci_softc *sc = device_get_softc(dev); bus_read_multi_4(sc->mem_res, off + sc->sdhci_reg_off, data, count); } static void ti_sdhci_write_1(device_t dev, struct sdhci_slot *slot, bus_size_t off, uint8_t val) { struct ti_sdhci_softc *sc = device_get_softc(dev); uint32_t val32; #ifdef MMCCAM uint32_t newval32; if (off == SDHCI_HOST_CONTROL) { val32 = ti_mmchs_read_4(sc, MMCHS_CON); newval32 = val32; if (val & SDHCI_CTRL_8BITBUS) { device_printf(dev, "Custom-enabling 8-bit bus\n"); newval32 |= MMCHS_CON_DW8; } else { device_printf(dev, "Custom-disabling 8-bit bus\n"); newval32 &= ~MMCHS_CON_DW8; } if (newval32 != val32) ti_mmchs_write_4(sc, MMCHS_CON, newval32); } #endif val32 = RD4(sc, off & ~3); val32 &= ~(0xff << (off & 3) * 8); val32 |= (val << (off & 3) * 8); WR4(sc, off & ~3, val32); } static void ti_sdhci_write_2(device_t dev, struct sdhci_slot *slot, bus_size_t off, uint16_t val) { struct ti_sdhci_softc *sc = device_get_softc(dev); uint32_t clkdiv, val32; /* * Translate between the hardware and SDHCI 2.0 or 3.0 representations * of the clock divisor. See the comments in ti_sdhci_read_2() for * details. */ if (off == SDHCI_CLOCK_CONTROL) { clkdiv = (val >> SDHCI_DIVIDER_SHIFT) & SDHCI_DIVIDER_MASK; if (slot->version >= SDHCI_SPEC_300) clkdiv |= ((val >> SDHCI_DIVIDER_HI_SHIFT) & SDHCI_DIVIDER_HI_MASK) << SDHCI_DIVIDER_MASK_LEN; clkdiv *= 2; if (clkdiv > MMCHS_SYSCTL_CLKD_MASK) clkdiv = MMCHS_SYSCTL_CLKD_MASK; val32 = RD4(sc, SDHCI_CLOCK_CONTROL); val32 &= 0xffff0000; val32 |= val & ~(MMCHS_SYSCTL_CLKD_MASK << MMCHS_SYSCTL_CLKD_SHIFT); val32 |= clkdiv << MMCHS_SYSCTL_CLKD_SHIFT; WR4(sc, SDHCI_CLOCK_CONTROL, val32); return; } /* * Standard 32-bit handling of command and transfer mode. */ if (off == SDHCI_TRANSFER_MODE) { sc->cmd_and_mode = (sc->cmd_and_mode & 0xffff0000) | ((uint32_t)val & 0x0000ffff); return; } else if (off == SDHCI_COMMAND_FLAGS) { sc->cmd_and_mode = (sc->cmd_and_mode & 0x0000ffff) | ((uint32_t)val << 16); WR4(sc, SDHCI_TRANSFER_MODE, sc->cmd_and_mode); return; } val32 = RD4(sc, off & ~3); val32 &= ~(0xffff << (off & 3) * 8); val32 |= ((val & 0xffff) << (off & 3) * 8); WR4(sc, off & ~3, val32); } static void ti_sdhci_write_4(device_t dev, struct sdhci_slot *slot, bus_size_t off, uint32_t val) { struct ti_sdhci_softc *sc = device_get_softc(dev); WR4(sc, off, val); } static void ti_sdhci_write_multi_4(device_t dev, struct sdhci_slot *slot, bus_size_t off, uint32_t *data, bus_size_t count) { struct ti_sdhci_softc *sc = device_get_softc(dev); bus_write_multi_4(sc->mem_res, off + sc->sdhci_reg_off, data, count); } static void ti_sdhci_intr(void *arg) { struct ti_sdhci_softc *sc = arg; sdhci_generic_intr(&sc->slot); } static int ti_sdhci_update_ios(device_t brdev, device_t reqdev) { struct ti_sdhci_softc *sc = device_get_softc(brdev); struct sdhci_slot *slot; struct mmc_ios *ios; uint32_t val32, newval32; slot = device_get_ivars(reqdev); ios = &slot->host.ios; /* * There is an 8-bit-bus bit in the MMCHS control register which, when * set, overrides the 1 vs 4 bit setting in the standard SDHCI * registers. Set that bit first according to whether an 8-bit bus is * requested, then let the standard driver handle everything else. */ val32 = ti_mmchs_read_4(sc, MMCHS_CON); newval32 = val32; if (ios->bus_width == bus_width_8) newval32 |= MMCHS_CON_DW8; else newval32 &= ~MMCHS_CON_DW8; if (ios->bus_mode == opendrain) newval32 |= MMCHS_CON_OD; else /* if (ios->bus_mode == pushpull) */ newval32 &= ~MMCHS_CON_OD; if (newval32 != val32) ti_mmchs_write_4(sc, MMCHS_CON, newval32); return (sdhci_generic_update_ios(brdev, reqdev)); } static int ti_sdhci_get_ro(device_t brdev, device_t reqdev) { struct ti_sdhci_softc *sc = device_get_softc(brdev); if (sc->disable_readonly) return (0); return (sdhci_fdt_gpio_get_readonly(sc->gpio)); } static bool ti_sdhci_get_card_present(device_t dev, struct sdhci_slot *slot) { struct ti_sdhci_softc *sc = device_get_softc(dev); return (sdhci_fdt_gpio_get_present(sc->gpio)); } static int ti_sdhci_detach(device_t dev) { /* sdhci_fdt_gpio_teardown(sc->gpio); */ return (EBUSY); } static void ti_sdhci_hw_init(device_t dev) { struct ti_sdhci_softc *sc = device_get_softc(dev); uint32_t regval; unsigned long timeout; /* Enable the controller and interface/functional clocks */ if (ti_prcm_clk_enable(sc->mmchs_clk_id) != 0) { device_printf(dev, "Error: failed to enable MMC clock\n"); return; } /* Get the frequency of the source clock */ if (ti_prcm_clk_get_source_freq(sc->mmchs_clk_id, &sc->baseclk_hz) != 0) { device_printf(dev, "Error: failed to get source clock freq\n"); return; } /* Issue a softreset to the controller */ ti_mmchs_write_4(sc, MMCHS_SYSCONFIG, MMCHS_SYSCONFIG_RESET); timeout = 1000; while (!(ti_mmchs_read_4(sc, MMCHS_SYSSTATUS) & MMCHS_SYSSTATUS_RESETDONE)) { if (--timeout == 0) { device_printf(dev, "Error: Controller reset operation timed out\n"); break; } DELAY(100); } /* * Reset the command and data state machines and also other aspects of * the controller such as bus clock and power. * * If we read the software reset register too fast after writing it we * can get back a zero that means the reset hasn't started yet rather * than that the reset is complete. Per TI recommendations, work around * it by reading until we see the reset bit asserted, then read until * it's clear. We also set the SDHCI_QUIRK_WAITFOR_RESET_ASSERTED quirk * so that the main sdhci driver uses this same logic in its resets. */ ti_sdhci_write_1(dev, NULL, SDHCI_SOFTWARE_RESET, SDHCI_RESET_ALL); timeout = 10000; while ((ti_sdhci_read_1(dev, NULL, SDHCI_SOFTWARE_RESET) & SDHCI_RESET_ALL) != SDHCI_RESET_ALL) { if (--timeout == 0) { break; } DELAY(1); } timeout = 10000; while ((ti_sdhci_read_1(dev, NULL, SDHCI_SOFTWARE_RESET) & SDHCI_RESET_ALL)) { if (--timeout == 0) { device_printf(dev, "Error: Software reset operation timed out\n"); break; } DELAY(100); } /* * The attach() routine has examined fdt data and set flags in * slot.host.caps to reflect what voltages we can handle. Set those * values in the CAPA register. The manual says that these values can * only be set once, "before initialization" whatever that means, and * that they survive a reset. So maybe doing this will be a no-op if * u-boot has already initialized the hardware. */ regval = ti_mmchs_read_4(sc, MMCHS_SD_CAPA); if (sc->slot.host.caps & MMC_OCR_LOW_VOLTAGE) regval |= MMCHS_SD_CAPA_VS18; if (sc->slot.host.caps & (MMC_OCR_290_300 | MMC_OCR_300_310)) regval |= MMCHS_SD_CAPA_VS30; ti_mmchs_write_4(sc, MMCHS_SD_CAPA, regval); /* Set initial host configuration (1-bit, std speed, pwr off). */ ti_sdhci_write_1(dev, NULL, SDHCI_HOST_CONTROL, 0); ti_sdhci_write_1(dev, NULL, SDHCI_POWER_CONTROL, 0); /* Set the initial controller configuration. */ ti_mmchs_write_4(sc, MMCHS_CON, MMCHS_CON_DVAL_8_4MS); } static int ti_sdhci_attach(device_t dev) { struct ti_sdhci_softc *sc = device_get_softc(dev); int rid, err; pcell_t prop; phandle_t node; sc->dev = dev; /* * Get the MMCHS device id from FDT. If it's not there use the newbus * unit number (which will work as long as the devices are in order and * none are skipped in the fdt). Note that this is a property we made * up and added in freebsd, it doesn't exist in the published bindings. */ node = ofw_bus_get_node(dev); sc->mmchs_clk_id = ti_hwmods_get_clock(dev); if (sc->mmchs_clk_id == INVALID_CLK_IDENT) { device_printf(dev, "failed to get clock based on hwmods property\n"); } /* * The hardware can inherently do dual-voltage (1p8v, 3p0v) on the first * device, and only 1p8v on other devices unless an external transceiver * is used. The only way we could know about a transceiver is fdt data. * Note that we have to do this before calling ti_sdhci_hw_init() so * that it can set the right values in the CAPA register, which can only * be done once and never reset. */ sc->slot.host.caps |= MMC_OCR_LOW_VOLTAGE; if (sc->mmchs_clk_id == MMC1_CLK || OF_hasprop(node, "ti,dual-volt")) { sc->slot.host.caps |= MMC_OCR_290_300 | MMC_OCR_300_310; } /* * Set the offset from the device's memory start to the MMCHS registers. * Also for OMAP4 disable high speed mode due to erratum ID i626. */ switch (ti_chip()) { #ifdef SOC_OMAP4 case CHIP_OMAP_4: sc->mmchs_reg_off = OMAP4_MMCHS_REG_OFFSET; sc->disable_highspeed = true; break; #endif #ifdef SOC_TI_AM335X case CHIP_AM335X: sc->mmchs_reg_off = AM335X_MMCHS_REG_OFFSET; break; #endif default: panic("Unknown OMAP device\n"); } /* * The standard SDHCI registers are at a fixed offset (the same on all * SoCs) beyond the MMCHS registers. */ sc->sdhci_reg_off = sc->mmchs_reg_off + SDHCI_REG_OFFSET; /* Resource setup. */ rid = 0; sc->mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, RF_ACTIVE); if (!sc->mem_res) { device_printf(dev, "cannot allocate memory window\n"); err = ENXIO; goto fail; } rid = 0; sc->irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, RF_ACTIVE); if (!sc->irq_res) { device_printf(dev, "cannot allocate interrupt\n"); err = ENXIO; goto fail; } if (bus_setup_intr(dev, sc->irq_res, INTR_TYPE_BIO | INTR_MPSAFE, NULL, ti_sdhci_intr, sc, &sc->intr_cookie)) { device_printf(dev, "cannot setup interrupt handler\n"); err = ENXIO; goto fail; } /* * Set up handling of card-detect and write-protect gpio lines. * * If there is no write protect info in the fdt data, fall back to the * historical practice of assuming that the card is writable. This * works around bad fdt data from the upstream source. The alternative * would be to trust the sdhci controller's PRESENT_STATE register WP * bit, but it may say write protect is in effect when it's not if the * pinmux setup doesn't route the WP signal into the sdchi block. */ sc->gpio = sdhci_fdt_gpio_setup(sc->dev, &sc->slot); if (!OF_hasprop(node, "wp-gpios") && !OF_hasprop(node, "wp-disable")) sc->disable_readonly = true; /* Initialise the MMCHS hardware. */ ti_sdhci_hw_init(dev); /* * The capabilities register can only express base clock frequencies in * the range of 0-63MHz for a v2.0 controller. Since our clock runs * faster than that, the hardware sets the frequency to zero in the * register. When the register contains zero, the sdhci driver expects * slot.max_clk to already have the right value in it. */ sc->slot.max_clk = sc->baseclk_hz; /* * The MMCHS timeout counter is based on the output sdclock. Tell the * sdhci driver to recalculate the timeout clock whenever the output * sdclock frequency changes. */ sc->slot.quirks |= SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK; /* * The MMCHS hardware shifts the 136-bit response data (in violation of * the spec), so tell the sdhci driver not to do the same in software. */ sc->slot.quirks |= SDHCI_QUIRK_DONT_SHIFT_RESPONSE; /* * Reset bits are broken, have to wait to see the bits asserted * before waiting to see them de-asserted. */ sc->slot.quirks |= SDHCI_QUIRK_WAITFOR_RESET_ASSERTED; /* * The controller waits for busy responses. */ sc->slot.quirks |= SDHCI_QUIRK_WAIT_WHILE_BUSY; /* * DMA is not really broken, I just haven't implemented it yet. */ sc->slot.quirks |= SDHCI_QUIRK_BROKEN_DMA; /* * Set up the hardware and go. Note that this sets many of the * slot.host.* fields, so we have to do this before overriding any of * those values based on fdt data, below. */ sdhci_init_slot(dev, &sc->slot, 0); /* * The SDHCI controller doesn't realize it, but we can support 8-bit * even though we're not a v3.0 controller. If there's an fdt bus-width * property, honor it. */ if (OF_getencprop(node, "bus-width", &prop, sizeof(prop)) > 0) { sc->slot.host.caps &= ~(MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA); switch (prop) { case 8: sc->slot.host.caps |= MMC_CAP_8_BIT_DATA; /* FALLTHROUGH */ case 4: sc->slot.host.caps |= MMC_CAP_4_BIT_DATA; break; case 1: break; default: device_printf(dev, "Bad bus-width value %u\n", prop); break; } } /* * If the slot is flagged with the non-removable property, set our flag * to always force the SDHCI_CARD_PRESENT bit on. */ node = ofw_bus_get_node(dev); if (OF_hasprop(node, "non-removable")) sc->force_card_present = true; bus_generic_probe(dev); bus_generic_attach(dev); -#ifdef MMCCAM - sdhci_cam_start_slot(&sc->slot); -#else sdhci_start_slot(&sc->slot); -#endif return (0); fail: if (sc->intr_cookie) bus_teardown_intr(dev, sc->irq_res, sc->intr_cookie); if (sc->irq_res) bus_release_resource(dev, SYS_RES_IRQ, 0, sc->irq_res); if (sc->mem_res) bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->mem_res); return (err); } static int ti_sdhci_probe(device_t dev) { if (!ofw_bus_status_okay(dev)) return (ENXIO); if (ofw_bus_search_compatible(dev, compat_data)->ocd_data != 0) { device_set_desc(dev, "TI MMCHS (SDHCI 2.0)"); return (BUS_PROBE_DEFAULT); } return (ENXIO); } static device_method_t ti_sdhci_methods[] = { /* Device interface */ DEVMETHOD(device_probe, ti_sdhci_probe), DEVMETHOD(device_attach, ti_sdhci_attach), DEVMETHOD(device_detach, ti_sdhci_detach), /* Bus interface */ DEVMETHOD(bus_read_ivar, sdhci_generic_read_ivar), DEVMETHOD(bus_write_ivar, sdhci_generic_write_ivar), /* MMC bridge interface */ DEVMETHOD(mmcbr_update_ios, ti_sdhci_update_ios), DEVMETHOD(mmcbr_request, sdhci_generic_request), DEVMETHOD(mmcbr_get_ro, ti_sdhci_get_ro), DEVMETHOD(mmcbr_acquire_host, sdhci_generic_acquire_host), DEVMETHOD(mmcbr_release_host, sdhci_generic_release_host), /* SDHCI registers accessors */ DEVMETHOD(sdhci_read_1, ti_sdhci_read_1), DEVMETHOD(sdhci_read_2, ti_sdhci_read_2), DEVMETHOD(sdhci_read_4, ti_sdhci_read_4), DEVMETHOD(sdhci_read_multi_4, ti_sdhci_read_multi_4), DEVMETHOD(sdhci_write_1, ti_sdhci_write_1), DEVMETHOD(sdhci_write_2, ti_sdhci_write_2), DEVMETHOD(sdhci_write_4, ti_sdhci_write_4), DEVMETHOD(sdhci_write_multi_4, ti_sdhci_write_multi_4), DEVMETHOD(sdhci_get_card_present, ti_sdhci_get_card_present), DEVMETHOD_END }; static devclass_t ti_sdhci_devclass; static driver_t ti_sdhci_driver = { "sdhci_ti", ti_sdhci_methods, sizeof(struct ti_sdhci_softc), }; DRIVER_MODULE(sdhci_ti, simplebus, ti_sdhci_driver, ti_sdhci_devclass, NULL, NULL); MODULE_DEPEND(sdhci_ti, sdhci, 1, 1, 1); #ifndef MMCCAM MMC_DECLARE_BRIDGE(sdhci_ti); #endif Index: head/sys/dev/sdhci/fsl_sdhci.c =================================================================== --- head/sys/dev/sdhci/fsl_sdhci.c (revision 323965) +++ head/sys/dev/sdhci/fsl_sdhci.c (revision 323966) @@ -1,1000 +1,996 @@ /*- * Copyright (c) 2013 Ian Lepore * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. * */ #include __FBSDID("$FreeBSD$"); /* * SDHCI driver glue for Freescale i.MX SoC and QorIQ families. * * This supports both eSDHC (earlier SoCs) and uSDHC (more recent SoCs). */ #include "opt_mmccam.h" #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #ifdef __arm__ #include #include #endif #ifdef __powerpc__ #include #endif #include #include #include #include #include #include #include "mmcbr_if.h" #include "sdhci_if.h" struct fsl_sdhci_softc { device_t dev; struct resource * mem_res; struct resource * irq_res; void * intr_cookie; struct sdhci_slot slot; struct callout r1bfix_callout; sbintime_t r1bfix_timeout_at; struct sdhci_fdt_gpio * gpio; uint32_t baseclk_hz; uint32_t cmd_and_mode; uint32_t r1bfix_intmask; uint16_t sdclockreg_freq_bits; uint8_t r1bfix_type; uint8_t hwtype; }; #define R1BFIX_NONE 0 /* No fix needed at next interrupt. */ #define R1BFIX_NODATA 1 /* Synthesize DATA_END for R1B w/o data. */ #define R1BFIX_AC12 2 /* Wait for busy after auto command 12. */ #define HWTYPE_NONE 0 /* Hardware not recognized/supported. */ #define HWTYPE_ESDHC 1 /* fsl5x and earlier. */ #define HWTYPE_USDHC 2 /* fsl6. */ /* * Freescale-specific registers, or in some cases the layout of bits within the * sdhci-defined register is different on Freescale. These names all begin with * SDHC_ (not SDHCI_). */ #define SDHC_WTMK_LVL 0x44 /* Watermark Level register. */ #define USDHC_MIX_CONTROL 0x48 /* Mix(ed) Control register. */ #define SDHC_VEND_SPEC 0xC0 /* Vendor-specific register. */ #define SDHC_VEND_FRC_SDCLK_ON (1 << 8) #define SDHC_VEND_IPGEN (1 << 11) #define SDHC_VEND_HCKEN (1 << 12) #define SDHC_VEND_PEREN (1 << 13) #define SDHC_PRES_STATE 0x24 #define SDHC_PRES_CIHB (1 << 0) #define SDHC_PRES_CDIHB (1 << 1) #define SDHC_PRES_DLA (1 << 2) #define SDHC_PRES_SDSTB (1 << 3) #define SDHC_PRES_IPGOFF (1 << 4) #define SDHC_PRES_HCKOFF (1 << 5) #define SDHC_PRES_PEROFF (1 << 6) #define SDHC_PRES_SDOFF (1 << 7) #define SDHC_PRES_WTA (1 << 8) #define SDHC_PRES_RTA (1 << 9) #define SDHC_PRES_BWEN (1 << 10) #define SDHC_PRES_BREN (1 << 11) #define SDHC_PRES_RTR (1 << 12) #define SDHC_PRES_CINST (1 << 16) #define SDHC_PRES_CDPL (1 << 18) #define SDHC_PRES_WPSPL (1 << 19) #define SDHC_PRES_CLSL (1 << 23) #define SDHC_PRES_DLSL_SHIFT 24 #define SDHC_PRES_DLSL_MASK (0xffU << SDHC_PRES_DLSL_SHIFT) #define SDHC_PROT_CTRL 0x28 #define SDHC_PROT_LED (1 << 0) #define SDHC_PROT_WIDTH_1BIT (0 << 1) #define SDHC_PROT_WIDTH_4BIT (1 << 1) #define SDHC_PROT_WIDTH_8BIT (2 << 1) #define SDHC_PROT_WIDTH_MASK (3 << 1) #define SDHC_PROT_D3CD (1 << 3) #define SDHC_PROT_EMODE_BIG (0 << 4) #define SDHC_PROT_EMODE_HALF (1 << 4) #define SDHC_PROT_EMODE_LITTLE (2 << 4) #define SDHC_PROT_EMODE_MASK (3 << 4) #define SDHC_PROT_SDMA (0 << 8) #define SDHC_PROT_ADMA1 (1 << 8) #define SDHC_PROT_ADMA2 (2 << 8) #define SDHC_PROT_ADMA264 (3 << 8) #define SDHC_PROT_DMA_MASK (3 << 8) #define SDHC_PROT_CDTL (1 << 6) #define SDHC_PROT_CDSS (1 << 7) #define SDHC_SYS_CTRL 0x2c /* * The clock enable bits exist in different registers for ESDHC vs USDHC, but * they are the same bits in both cases. The divisor values go into the * standard sdhci clock register, but in different bit positions and meanings than the sdhci spec values. */ #define SDHC_CLK_IPGEN (1 << 0) #define SDHC_CLK_HCKEN (1 << 1) #define SDHC_CLK_PEREN (1 << 2) #define SDHC_CLK_SDCLKEN (1 << 3) #define SDHC_CLK_ENABLE_MASK 0x0000000f #define SDHC_CLK_DIVISOR_MASK 0x000000f0 #define SDHC_CLK_DIVISOR_SHIFT 4 #define SDHC_CLK_PRESCALE_MASK 0x0000ff00 #define SDHC_CLK_PRESCALE_SHIFT 8 static struct ofw_compat_data compat_data[] = { {"fsl,imx6q-usdhc", HWTYPE_USDHC}, {"fsl,imx6sl-usdhc", HWTYPE_USDHC}, {"fsl,imx53-esdhc", HWTYPE_ESDHC}, {"fsl,imx51-esdhc", HWTYPE_ESDHC}, {"fsl,esdhc", HWTYPE_ESDHC}, {NULL, HWTYPE_NONE}, }; static uint16_t fsl_sdhc_get_clock(struct fsl_sdhci_softc *sc); static void fsl_sdhc_set_clock(struct fsl_sdhci_softc *sc, uint16_t val); static void fsl_sdhci_r1bfix_func(void *arg); static inline uint32_t RD4(struct fsl_sdhci_softc *sc, bus_size_t off) { return (bus_read_4(sc->mem_res, off)); } static inline void WR4(struct fsl_sdhci_softc *sc, bus_size_t off, uint32_t val) { bus_write_4(sc->mem_res, off, val); } static uint8_t fsl_sdhci_read_1(device_t dev, struct sdhci_slot *slot, bus_size_t off) { struct fsl_sdhci_softc *sc = device_get_softc(dev); uint32_t val32, wrk32; /* * Most of the things in the standard host control register are in the * hardware's wider protocol control register, but some of the bits are * moved around. */ if (off == SDHCI_HOST_CONTROL) { wrk32 = RD4(sc, SDHC_PROT_CTRL); val32 = wrk32 & (SDHCI_CTRL_LED | SDHCI_CTRL_CARD_DET | SDHCI_CTRL_FORCE_CARD); switch (wrk32 & SDHC_PROT_WIDTH_MASK) { case SDHC_PROT_WIDTH_1BIT: /* Value is already 0. */ break; case SDHC_PROT_WIDTH_4BIT: val32 |= SDHCI_CTRL_4BITBUS; break; case SDHC_PROT_WIDTH_8BIT: val32 |= SDHCI_CTRL_8BITBUS; break; } switch (wrk32 & SDHC_PROT_DMA_MASK) { case SDHC_PROT_SDMA: /* Value is already 0. */ break; case SDHC_PROT_ADMA1: /* This value is deprecated, should never appear. */ break; case SDHC_PROT_ADMA2: val32 |= SDHCI_CTRL_ADMA2; break; case SDHC_PROT_ADMA264: val32 |= SDHCI_CTRL_ADMA264; break; } return val32; } /* * XXX can't find the bus power on/off knob. For now we have to say the * power is always on and always set to the same voltage. */ if (off == SDHCI_POWER_CONTROL) { return (SDHCI_POWER_ON | SDHCI_POWER_300); } return ((RD4(sc, off & ~3) >> (off & 3) * 8) & 0xff); } static uint16_t fsl_sdhci_read_2(device_t dev, struct sdhci_slot *slot, bus_size_t off) { struct fsl_sdhci_softc *sc = device_get_softc(dev); uint32_t val32; if (sc->hwtype == HWTYPE_USDHC) { /* * The USDHC hardware has nothing in the version register, but * it's v3 compatible with all our translation code. */ if (off == SDHCI_HOST_VERSION) { return (SDHCI_SPEC_300 << SDHCI_SPEC_VER_SHIFT); } /* * The USDHC hardware moved the transfer mode bits to the mixed * control register, fetch them from there. */ if (off == SDHCI_TRANSFER_MODE) return (RD4(sc, USDHC_MIX_CONTROL) & 0x37); } else if (sc->hwtype == HWTYPE_ESDHC) { /* * The ESDHC hardware has the typical 32-bit combined "command * and mode" register that we have to cache so that command * isn't written until after mode. On a read, just retrieve the * cached values last written. */ if (off == SDHCI_TRANSFER_MODE) { return (sc->cmd_and_mode & 0x0000ffff); } else if (off == SDHCI_COMMAND_FLAGS) { return (sc->cmd_and_mode >> 16); } } /* * This hardware only manages one slot. Synthesize a slot interrupt * status register... if there are any enabled interrupts active they * must be coming from our one and only slot. */ if (off == SDHCI_SLOT_INT_STATUS) { val32 = RD4(sc, SDHCI_INT_STATUS); val32 &= RD4(sc, SDHCI_SIGNAL_ENABLE); return (val32 ? 1 : 0); } /* * Clock bits are scattered into various registers which differ by * hardware type, complex enough to have their own function. */ if (off == SDHCI_CLOCK_CONTROL) { return (fsl_sdhc_get_clock(sc)); } return ((RD4(sc, off & ~3) >> (off & 3) * 8) & 0xffff); } static uint32_t fsl_sdhci_read_4(device_t dev, struct sdhci_slot *slot, bus_size_t off) { struct fsl_sdhci_softc *sc = device_get_softc(dev); uint32_t val32, wrk32; val32 = RD4(sc, off); /* * The hardware leaves the base clock frequency out of the capabilities * register, but we filled it in by setting slot->max_clk at attach time * rather than here, because we can't represent frequencies above 63MHz * in an sdhci 2.0 capabliities register. The timeout clock is the same * as the active output sdclock; we indicate that with a quirk setting * so don't populate the timeout frequency bits. * * XXX Turn off (for now) features the hardware can do but this driver * doesn't yet handle (1.8v, suspend/resume, etc). */ if (off == SDHCI_CAPABILITIES) { val32 &= ~SDHCI_CAN_VDD_180; val32 &= ~SDHCI_CAN_DO_SUSPEND; val32 |= SDHCI_CAN_DO_8BITBUS; return (val32); } /* * The hardware moves bits around in the present state register to make * room for all 8 data line state bits. To translate, mask out all the * bits which are not in the same position in both registers (this also * masks out some Freescale-specific bits in locations defined as * reserved by sdhci), then shift the data line and retune request bits * down to their standard locations. */ if (off == SDHCI_PRESENT_STATE) { wrk32 = val32; val32 &= 0x000F0F07; val32 |= (wrk32 >> 4) & SDHCI_STATE_DAT_MASK; val32 |= (wrk32 >> 9) & SDHCI_RETUNE_REQUEST; return (val32); } /* * fsl_sdhci_intr() can synthesize a DATA_END interrupt following a * command with an R1B response, mix it into the hardware status. */ if (off == SDHCI_INT_STATUS) { return (val32 | sc->r1bfix_intmask); } return val32; } static void fsl_sdhci_read_multi_4(device_t dev, struct sdhci_slot *slot, bus_size_t off, uint32_t *data, bus_size_t count) { struct fsl_sdhci_softc *sc = device_get_softc(dev); bus_read_multi_4(sc->mem_res, off, data, count); } static void fsl_sdhci_write_1(device_t dev, struct sdhci_slot *slot, bus_size_t off, uint8_t val) { struct fsl_sdhci_softc *sc = device_get_softc(dev); uint32_t val32; /* * Most of the things in the standard host control register are in the * hardware's wider protocol control register, but some of the bits are * moved around. */ if (off == SDHCI_HOST_CONTROL) { val32 = RD4(sc, SDHC_PROT_CTRL); val32 &= ~(SDHC_PROT_LED | SDHC_PROT_DMA_MASK | SDHC_PROT_WIDTH_MASK | SDHC_PROT_CDTL | SDHC_PROT_CDSS); val32 |= (val & SDHCI_CTRL_LED); if (val & SDHCI_CTRL_8BITBUS) val32 |= SDHC_PROT_WIDTH_8BIT; else val32 |= (val & SDHCI_CTRL_4BITBUS); val32 |= (val & (SDHCI_CTRL_SDMA | SDHCI_CTRL_ADMA2)) << 4; val32 |= (val & (SDHCI_CTRL_CARD_DET | SDHCI_CTRL_FORCE_CARD)); WR4(sc, SDHC_PROT_CTRL, val32); return; } /* XXX I can't find the bus power on/off knob; do nothing. */ if (off == SDHCI_POWER_CONTROL) { return; } #ifdef __powerpc__ /* XXX Reset doesn't seem to work as expected. Do nothing for now. */ if (off == SDHCI_SOFTWARE_RESET) return; #endif val32 = RD4(sc, off & ~3); val32 &= ~(0xff << (off & 3) * 8); val32 |= (val << (off & 3) * 8); WR4(sc, off & ~3, val32); } static void fsl_sdhci_write_2(device_t dev, struct sdhci_slot *slot, bus_size_t off, uint16_t val) { struct fsl_sdhci_softc *sc = device_get_softc(dev); uint32_t val32; /* * The clock control stuff is complex enough to have its own function * that can handle the ESDHC versus USDHC differences. */ if (off == SDHCI_CLOCK_CONTROL) { fsl_sdhc_set_clock(sc, val); return; } /* * Figure out whether we need to check the DAT0 line for busy status at * interrupt time. The controller should be doing this, but for some * reason it doesn't. There are two cases: * - R1B response with no data transfer should generate a DATA_END (aka * TRANSFER_COMPLETE) interrupt after waiting for busy, but if * there's no data transfer there's no DATA_END interrupt. This is * documented; they seem to think it's a feature. * - R1B response after Auto-CMD12 appears to not work, even though * there's a control bit for it (bit 3) in the vendor register. * When we're starting a command that needs a manual DAT0 line check at * interrupt time, we leave ourselves a note in r1bfix_type so that we * can do the extra work in fsl_sdhci_intr(). */ if (off == SDHCI_COMMAND_FLAGS) { if (val & SDHCI_CMD_DATA) { const uint32_t MBAUTOCMD = SDHCI_TRNS_ACMD12 | SDHCI_TRNS_MULTI; val32 = RD4(sc, USDHC_MIX_CONTROL); if ((val32 & MBAUTOCMD) == MBAUTOCMD) sc->r1bfix_type = R1BFIX_AC12; } else { if ((val & SDHCI_CMD_RESP_MASK) == SDHCI_CMD_RESP_SHORT_BUSY) { WR4(sc, SDHCI_INT_ENABLE, slot->intmask | SDHCI_INT_RESPONSE); WR4(sc, SDHCI_SIGNAL_ENABLE, slot->intmask | SDHCI_INT_RESPONSE); sc->r1bfix_type = R1BFIX_NODATA; } } } /* * The USDHC hardware moved the transfer mode bits to mixed control; we * just write them there and we're done. The ESDHC hardware has the * typical combined cmd-and-mode register that allows only 32-bit * access, so when writing the mode bits just save them, then later when * writing the command bits, add in the saved mode bits. */ if (sc->hwtype == HWTYPE_USDHC) { if (off == SDHCI_TRANSFER_MODE) { val32 = RD4(sc, USDHC_MIX_CONTROL); val32 &= ~0x3f; val32 |= val & 0x37; // XXX acmd23 not supported here (or by sdhci driver) WR4(sc, USDHC_MIX_CONTROL, val32); return; } } else if (sc->hwtype == HWTYPE_ESDHC) { if (off == SDHCI_TRANSFER_MODE) { sc->cmd_and_mode = (sc->cmd_and_mode & 0xffff0000) | val; return; } else if (off == SDHCI_COMMAND_FLAGS) { sc->cmd_and_mode = (sc->cmd_and_mode & 0xffff) | (val << 16); WR4(sc, SDHCI_TRANSFER_MODE, sc->cmd_and_mode); return; } } val32 = RD4(sc, off & ~3); val32 &= ~(0xffff << (off & 3) * 8); val32 |= ((val & 0xffff) << (off & 3) * 8); WR4(sc, off & ~3, val32); } static void fsl_sdhci_write_4(device_t dev, struct sdhci_slot *slot, bus_size_t off, uint32_t val) { struct fsl_sdhci_softc *sc = device_get_softc(dev); /* Clear synthesized interrupts, then pass the value to the hardware. */ if (off == SDHCI_INT_STATUS) { sc->r1bfix_intmask &= ~val; } WR4(sc, off, val); } static void fsl_sdhci_write_multi_4(device_t dev, struct sdhci_slot *slot, bus_size_t off, uint32_t *data, bus_size_t count) { struct fsl_sdhci_softc *sc = device_get_softc(dev); bus_write_multi_4(sc->mem_res, off, data, count); } static uint16_t fsl_sdhc_get_clock(struct fsl_sdhci_softc *sc) { uint16_t val; /* * Whenever the sdhci driver writes the clock register we save a * snapshot of just the frequency bits, so that we can play them back * here on a register read without recalculating the frequency from the * prescalar and divisor bits in the real register. We'll start with * those bits, and mix in the clock status and enable bits that come * from different places depending on which hardware we've got. */ val = sc->sdclockreg_freq_bits; /* * The internal clock is always enabled (actually, the hardware manages * it). Whether the internal clock is stable yet after a frequency * change comes from the present-state register on both hardware types. */ val |= SDHCI_CLOCK_INT_EN; if (RD4(sc, SDHC_PRES_STATE) & SDHC_PRES_SDSTB) val |= SDHCI_CLOCK_INT_STABLE; /* * On i.MX ESDHC hardware the card bus clock enable is in the usual * sdhci register but it's a different bit, so transcribe it (note the * difference between standard SDHCI_ and Freescale SDHC_ prefixes * here). On USDHC and QorIQ ESDHC hardware there is a force-on bit, but * no force-off for the card bus clock (the hardware runs the clock when * transfers are active no matter what), so we always say the clock is * on. * XXX Maybe we should say it's in whatever state the sdhci driver last * set it to. */ if (sc->hwtype == HWTYPE_ESDHC) { #ifdef __arm__ if (RD4(sc, SDHC_SYS_CTRL) & SDHC_CLK_SDCLKEN) #endif val |= SDHCI_CLOCK_CARD_EN; } else { val |= SDHCI_CLOCK_CARD_EN; } return (val); } static void fsl_sdhc_set_clock(struct fsl_sdhci_softc *sc, uint16_t val) { uint32_t divisor, freq, prescale, val32; val32 = RD4(sc, SDHCI_CLOCK_CONTROL); /* * Save the frequency-setting bits in SDHCI format so that we can play * them back in get_clock without complex decoding of hardware regs, * then deal with the freqency part of the value based on hardware type. */ sc->sdclockreg_freq_bits = val & SDHCI_DIVIDERS_MASK; if (sc->hwtype == HWTYPE_ESDHC) { /* * The i.MX5 ESDHC hardware requires the driver to manually * start and stop the sd bus clock. If the enable bit is not * set, turn off the clock in hardware and we're done, otherwise * decode the requested frequency. ESDHC hardware is sdhci 2.0; * the sdhci driver will use the original 8-bit divisor field * and the "base / 2^N" divisor scheme. */ if ((val & SDHCI_CLOCK_CARD_EN) == 0) { #ifdef __arm__ /* On QorIQ, this is a reserved bit. */ WR4(sc, SDHCI_CLOCK_CONTROL, val32 & ~SDHC_CLK_SDCLKEN); #endif return; } divisor = (val >> SDHCI_DIVIDER_SHIFT) & SDHCI_DIVIDER_MASK; freq = sc->baseclk_hz >> ffs(divisor); } else { /* * The USDHC hardware provides only "force always on" control * over the sd bus clock, but no way to turn it off. (If a cmd * or data transfer is in progress the clock is on, otherwise it * is off.) If the clock is being disabled, we can just return * now, otherwise we decode the requested frequency. USDHC * hardware is sdhci 3.0; the sdhci driver will use a 10-bit * divisor using the "base / 2*N" divisor scheme. */ if ((val & SDHCI_CLOCK_CARD_EN) == 0) return; divisor = ((val >> SDHCI_DIVIDER_SHIFT) & SDHCI_DIVIDER_MASK) | ((val >> SDHCI_DIVIDER_HI_SHIFT) & SDHCI_DIVIDER_HI_MASK) << SDHCI_DIVIDER_MASK_LEN; if (divisor == 0) freq = sc->baseclk_hz; else freq = sc->baseclk_hz / (2 * divisor); } /* * Get a prescaler and final divisor to achieve the desired frequency. */ for (prescale = 2; freq < sc->baseclk_hz / (prescale * 16);) prescale <<= 1; for (divisor = 1; freq < sc->baseclk_hz / (prescale * divisor);) ++divisor; #ifdef DEBUG device_printf(sc->dev, "desired SD freq: %d, actual: %d; base %d prescale %d divisor %d\n", freq, sc->baseclk_hz / (prescale * divisor), sc->baseclk_hz, prescale, divisor); #endif /* * Adjust to zero-based values, and store them to the hardware. */ prescale >>= 1; divisor -= 1; val32 &= ~(SDHC_CLK_DIVISOR_MASK | SDHC_CLK_PRESCALE_MASK); val32 |= divisor << SDHC_CLK_DIVISOR_SHIFT; val32 |= prescale << SDHC_CLK_PRESCALE_SHIFT; val32 |= SDHC_CLK_IPGEN; WR4(sc, SDHCI_CLOCK_CONTROL, val32); } static boolean_t fsl_sdhci_r1bfix_is_wait_done(struct fsl_sdhci_softc *sc) { uint32_t inhibit; mtx_assert(&sc->slot.mtx, MA_OWNED); /* * Check the DAT0 line status using both the DLA (data line active) and * CDIHB (data inhibit) bits in the present state register. In theory * just DLA should do the trick, but in practice it takes both. If the * DAT0 line is still being held and we're not yet beyond the timeout * point, just schedule another callout to check again later. */ inhibit = RD4(sc, SDHC_PRES_STATE) & (SDHC_PRES_DLA | SDHC_PRES_CDIHB); if (inhibit && getsbinuptime() < sc->r1bfix_timeout_at) { callout_reset_sbt(&sc->r1bfix_callout, SBT_1MS, 0, fsl_sdhci_r1bfix_func, sc, 0); return (false); } /* * If we reach this point with the inhibit bits still set, we've got a * timeout, synthesize a DATA_TIMEOUT interrupt. Otherwise the DAT0 * line has been released, and we synthesize a DATA_END, and if the type * of fix needed was on a command-without-data we also now add in the * original INT_RESPONSE that we suppressed earlier. */ if (inhibit) sc->r1bfix_intmask |= SDHCI_INT_DATA_TIMEOUT; else { sc->r1bfix_intmask |= SDHCI_INT_DATA_END; if (sc->r1bfix_type == R1BFIX_NODATA) sc->r1bfix_intmask |= SDHCI_INT_RESPONSE; } sc->r1bfix_type = R1BFIX_NONE; return (true); } static void fsl_sdhci_r1bfix_func(void * arg) { struct fsl_sdhci_softc *sc = arg; boolean_t r1bwait_done; mtx_lock(&sc->slot.mtx); r1bwait_done = fsl_sdhci_r1bfix_is_wait_done(sc); mtx_unlock(&sc->slot.mtx); if (r1bwait_done) sdhci_generic_intr(&sc->slot); } static void fsl_sdhci_intr(void *arg) { struct fsl_sdhci_softc *sc = arg; uint32_t intmask; mtx_lock(&sc->slot.mtx); /* * Manually check the DAT0 line for R1B response types that the * controller fails to handle properly. The controller asserts the done * interrupt while the card is still asserting busy with the DAT0 line. * * We check DAT0 immediately because most of the time, especially on a * read, the card will actually be done by time we get here. If it's * not, then the wait_done routine will schedule a callout to re-check * periodically until it is done. In that case we clear the interrupt * out of the hardware now so that we can present it later when the DAT0 * line is released. * * If we need to wait for the DAT0 line to be released, we set up a * timeout point 250ms in the future. This number comes from the SD * spec, which allows a command to take that long. In the real world, * cards tend to take 10-20ms for a long-running command such as a write * or erase that spans two pages. */ switch (sc->r1bfix_type) { case R1BFIX_NODATA: intmask = RD4(sc, SDHCI_INT_STATUS) & SDHCI_INT_RESPONSE; break; case R1BFIX_AC12: intmask = RD4(sc, SDHCI_INT_STATUS) & SDHCI_INT_DATA_END; break; default: intmask = 0; break; } if (intmask) { sc->r1bfix_timeout_at = getsbinuptime() + 250 * SBT_1MS; if (!fsl_sdhci_r1bfix_is_wait_done(sc)) { WR4(sc, SDHCI_INT_STATUS, intmask); bus_barrier(sc->mem_res, SDHCI_INT_STATUS, 4, BUS_SPACE_BARRIER_WRITE); } } mtx_unlock(&sc->slot.mtx); sdhci_generic_intr(&sc->slot); } static int fsl_sdhci_get_ro(device_t bus, device_t child) { struct fsl_sdhci_softc *sc = device_get_softc(bus); return (sdhci_fdt_gpio_get_readonly(sc->gpio)); } static bool fsl_sdhci_get_card_present(device_t dev, struct sdhci_slot *slot) { struct fsl_sdhci_softc *sc = device_get_softc(dev); return (sdhci_fdt_gpio_get_present(sc->gpio)); } #ifdef __powerpc__ static uint32_t fsl_sdhci_get_platform_clock(device_t dev) { phandle_t node; uint32_t clock; node = ofw_bus_get_node(dev); /* Get sdhci node properties */ if((OF_getprop(node, "clock-frequency", (void *)&clock, sizeof(clock)) <= 0) || (clock == 0)) { clock = mpc85xx_get_system_clock(); if (clock == 0) { device_printf(dev,"Cannot acquire correct sdhci " "frequency from DTS.\n"); return (0); } } if (bootverbose) device_printf(dev, "Acquired clock: %d from DTS\n", clock); return (clock); } #endif static int fsl_sdhci_detach(device_t dev) { /* sdhci_fdt_gpio_teardown(sc->gpio); */ return (EBUSY); } static int fsl_sdhci_attach(device_t dev) { struct fsl_sdhci_softc *sc = device_get_softc(dev); int rid, err; #ifdef __powerpc__ phandle_t node; uint32_t protctl; #endif sc->dev = dev; sc->hwtype = ofw_bus_search_compatible(dev, compat_data)->ocd_data; if (sc->hwtype == HWTYPE_NONE) panic("Impossible: not compatible in fsl_sdhci_attach()"); rid = 0; sc->mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, RF_ACTIVE); if (!sc->mem_res) { device_printf(dev, "cannot allocate memory window\n"); err = ENXIO; goto fail; } rid = 0; sc->irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, RF_ACTIVE); if (!sc->irq_res) { device_printf(dev, "cannot allocate interrupt\n"); err = ENXIO; goto fail; } if (bus_setup_intr(dev, sc->irq_res, INTR_TYPE_BIO | INTR_MPSAFE, NULL, fsl_sdhci_intr, sc, &sc->intr_cookie)) { device_printf(dev, "cannot setup interrupt handler\n"); err = ENXIO; goto fail; } sc->slot.quirks |= SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK; /* * DMA is not really broken, I just haven't implemented it yet. */ sc->slot.quirks |= SDHCI_QUIRK_BROKEN_DMA; /* * Set the buffer watermark level to 128 words (512 bytes) for both read * and write. The hardware has a restriction that when the read or * write ready status is asserted, that means you can read exactly the * number of words set in the watermark register before you have to * re-check the status and potentially wait for more data. The main * sdhci driver provides no hook for doing status checking on less than * a full block boundary, so we set the watermark level to be a full * block. Reads and writes where the block size is less than the * watermark size will work correctly too, no need to change the * watermark for different size blocks. However, 128 is the maximum * allowed for the watermark, so PIO is limitted to 512 byte blocks * (which works fine for SD cards, may be a problem for SDIO some day). * * XXX need named constants for this stuff. */ /* P1022 has the '*_BRST_LEN' fields as reserved, always reading 0x10 */ if (ofw_bus_is_compatible(dev, "fsl,p1022-esdhc")) WR4(sc, SDHC_WTMK_LVL, 0x10801080); else WR4(sc, SDHC_WTMK_LVL, 0x08800880); /* * We read in native byte order in the main driver, but the register * defaults to little endian. */ #ifdef __powerpc__ sc->baseclk_hz = fsl_sdhci_get_platform_clock(dev); #else sc->baseclk_hz = imx_ccm_sdhci_hz(); #endif sc->slot.max_clk = sc->baseclk_hz; /* * Set up any gpio pin handling described in the FDT data. This cannot * fail; see comments in sdhci_fdt_gpio.h for details. */ sc->gpio = sdhci_fdt_gpio_setup(dev, &sc->slot); #ifdef __powerpc__ node = ofw_bus_get_node(dev); /* Default to big-endian on powerpc */ protctl = RD4(sc, SDHC_PROT_CTRL); protctl &= ~SDHC_PROT_EMODE_MASK; if (OF_hasprop(node, "little-endian")) protctl |= SDHC_PROT_EMODE_LITTLE; else protctl |= SDHC_PROT_EMODE_BIG; WR4(sc, SDHC_PROT_CTRL, protctl); #endif callout_init(&sc->r1bfix_callout, 1); sdhci_init_slot(dev, &sc->slot, 0); bus_generic_probe(dev); bus_generic_attach(dev); -#ifdef MMCCAM - sdhci_cam_start_slot(&sc->slot); -#else sdhci_start_slot(&sc->slot); -#endif return (0); fail: if (sc->intr_cookie) bus_teardown_intr(dev, sc->irq_res, sc->intr_cookie); if (sc->irq_res) bus_release_resource(dev, SYS_RES_IRQ, 0, sc->irq_res); if (sc->mem_res) bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->mem_res); return (err); } static int fsl_sdhci_probe(device_t dev) { if (!ofw_bus_status_okay(dev)) return (ENXIO); switch (ofw_bus_search_compatible(dev, compat_data)->ocd_data) { case HWTYPE_ESDHC: device_set_desc(dev, "Freescale eSDHC controller"); return (BUS_PROBE_DEFAULT); case HWTYPE_USDHC: device_set_desc(dev, "Freescale uSDHC controller"); return (BUS_PROBE_DEFAULT); default: break; } return (ENXIO); } static device_method_t fsl_sdhci_methods[] = { /* Device interface */ DEVMETHOD(device_probe, fsl_sdhci_probe), DEVMETHOD(device_attach, fsl_sdhci_attach), DEVMETHOD(device_detach, fsl_sdhci_detach), /* Bus interface */ DEVMETHOD(bus_read_ivar, sdhci_generic_read_ivar), DEVMETHOD(bus_write_ivar, sdhci_generic_write_ivar), /* MMC bridge interface */ DEVMETHOD(mmcbr_update_ios, sdhci_generic_update_ios), DEVMETHOD(mmcbr_request, sdhci_generic_request), DEVMETHOD(mmcbr_get_ro, fsl_sdhci_get_ro), DEVMETHOD(mmcbr_acquire_host, sdhci_generic_acquire_host), DEVMETHOD(mmcbr_release_host, sdhci_generic_release_host), /* SDHCI accessors */ DEVMETHOD(sdhci_read_1, fsl_sdhci_read_1), DEVMETHOD(sdhci_read_2, fsl_sdhci_read_2), DEVMETHOD(sdhci_read_4, fsl_sdhci_read_4), DEVMETHOD(sdhci_read_multi_4, fsl_sdhci_read_multi_4), DEVMETHOD(sdhci_write_1, fsl_sdhci_write_1), DEVMETHOD(sdhci_write_2, fsl_sdhci_write_2), DEVMETHOD(sdhci_write_4, fsl_sdhci_write_4), DEVMETHOD(sdhci_write_multi_4, fsl_sdhci_write_multi_4), DEVMETHOD(sdhci_get_card_present,fsl_sdhci_get_card_present), DEVMETHOD_END }; static devclass_t fsl_sdhci_devclass; static driver_t fsl_sdhci_driver = { "sdhci_fsl", fsl_sdhci_methods, sizeof(struct fsl_sdhci_softc), }; DRIVER_MODULE(sdhci_fsl, simplebus, fsl_sdhci_driver, fsl_sdhci_devclass, NULL, NULL); MODULE_DEPEND(sdhci_fsl, sdhci, 1, 1, 1); #ifndef MMCCAM MMC_DECLARE_BRIDGE(sdhci_fsl); #endif Index: head/sys/dev/sdhci/sdhci.c =================================================================== --- head/sys/dev/sdhci/sdhci.c (revision 323965) +++ head/sys/dev/sdhci/sdhci.c (revision 323966) @@ -1,2698 +1,2700 @@ /*- * Copyright (c) 2008 Alexander Motin * Copyright (c) 2017 Marius Strobl * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ #include __FBSDID("$FreeBSD$"); #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include "mmcbr_if.h" #include "sdhci_if.h" #include "opt_mmccam.h" SYSCTL_NODE(_hw, OID_AUTO, sdhci, CTLFLAG_RD, 0, "sdhci driver"); static int sdhci_debug = 0; SYSCTL_INT(_hw_sdhci, OID_AUTO, debug, CTLFLAG_RWTUN, &sdhci_debug, 0, "Debug level"); u_int sdhci_quirk_clear = 0; SYSCTL_INT(_hw_sdhci, OID_AUTO, quirk_clear, CTLFLAG_RWTUN, &sdhci_quirk_clear, 0, "Mask of quirks to clear"); u_int sdhci_quirk_set = 0; SYSCTL_INT(_hw_sdhci, OID_AUTO, quirk_set, CTLFLAG_RWTUN, &sdhci_quirk_set, 0, "Mask of quirks to set"); #define RD1(slot, off) SDHCI_READ_1((slot)->bus, (slot), (off)) #define RD2(slot, off) SDHCI_READ_2((slot)->bus, (slot), (off)) #define RD4(slot, off) SDHCI_READ_4((slot)->bus, (slot), (off)) #define RD_MULTI_4(slot, off, ptr, count) \ SDHCI_READ_MULTI_4((slot)->bus, (slot), (off), (ptr), (count)) #define WR1(slot, off, val) SDHCI_WRITE_1((slot)->bus, (slot), (off), (val)) #define WR2(slot, off, val) SDHCI_WRITE_2((slot)->bus, (slot), (off), (val)) #define WR4(slot, off, val) SDHCI_WRITE_4((slot)->bus, (slot), (off), (val)) #define WR_MULTI_4(slot, off, ptr, count) \ SDHCI_WRITE_MULTI_4((slot)->bus, (slot), (off), (ptr), (count)) static void sdhci_card_poll(void *arg); static void sdhci_card_task(void *arg, int pending); static int sdhci_exec_tuning(struct sdhci_slot *slot, bool reset); static void sdhci_req_wakeup(struct mmc_request *req); static void sdhci_retune(void *arg); static void sdhci_set_clock(struct sdhci_slot *slot, uint32_t clock); static void sdhci_start(struct sdhci_slot *slot); static void sdhci_start_data(struct sdhci_slot *slot, struct mmc_data *data); #ifdef MMCCAM /* CAM-related */ int sdhci_cam_get_possible_host_clock(struct sdhci_slot *slot, int proposed_clock); static int sdhci_cam_update_ios(struct sdhci_slot *slot); static int sdhci_cam_request(struct sdhci_slot *slot, union ccb *ccb); static void sdhci_cam_action(struct cam_sim *sim, union ccb *ccb); static void sdhci_cam_poll(struct cam_sim *sim); static int sdhci_cam_settran_settings(struct sdhci_slot *slot, union ccb *ccb); #endif /* helper routines */ static void sdhci_dumpregs(struct sdhci_slot *slot); static int slot_printf(struct sdhci_slot *slot, const char * fmt, ...) __printflike(2, 3); static uint32_t sdhci_tuning_intmask(struct sdhci_slot *slot); #define SDHCI_LOCK(_slot) mtx_lock(&(_slot)->mtx) #define SDHCI_UNLOCK(_slot) mtx_unlock(&(_slot)->mtx) #define SDHCI_LOCK_INIT(_slot) \ mtx_init(&_slot->mtx, "SD slot mtx", "sdhci", MTX_DEF) #define SDHCI_LOCK_DESTROY(_slot) mtx_destroy(&_slot->mtx); #define SDHCI_ASSERT_LOCKED(_slot) mtx_assert(&_slot->mtx, MA_OWNED); #define SDHCI_ASSERT_UNLOCKED(_slot) mtx_assert(&_slot->mtx, MA_NOTOWNED); #define SDHCI_DEFAULT_MAX_FREQ 50 #define SDHCI_200_MAX_DIVIDER 256 #define SDHCI_300_MAX_DIVIDER 2046 #define SDHCI_CARD_PRESENT_TICKS (hz / 5) #define SDHCI_INSERT_DELAY_TICKS (hz / 2) /* * Broadcom BCM577xx Controller Constants */ /* Maximum divider supported by the default clock source. */ #define BCM577XX_DEFAULT_MAX_DIVIDER 256 /* Alternative clock's base frequency. */ #define BCM577XX_ALT_CLOCK_BASE 63000000 #define BCM577XX_HOST_CONTROL 0x198 #define BCM577XX_CTRL_CLKSEL_MASK 0xFFFFCFFF #define BCM577XX_CTRL_CLKSEL_SHIFT 12 #define BCM577XX_CTRL_CLKSEL_DEFAULT 0x0 #define BCM577XX_CTRL_CLKSEL_64MHZ 0x3 static void sdhci_getaddr(void *arg, bus_dma_segment_t *segs, int nsegs, int error) { if (error != 0) { printf("getaddr: error %d\n", error); return; } *(bus_addr_t *)arg = segs[0].ds_addr; } static int slot_printf(struct sdhci_slot *slot, const char * fmt, ...) { va_list ap; int retval; retval = printf("%s-slot%d: ", device_get_nameunit(slot->bus), slot->num); va_start(ap, fmt); retval += vprintf(fmt, ap); va_end(ap); return (retval); } static void sdhci_dumpregs(struct sdhci_slot *slot) { slot_printf(slot, "============== REGISTER DUMP ==============\n"); slot_printf(slot, "Sys addr: 0x%08x | Version: 0x%08x\n", RD4(slot, SDHCI_DMA_ADDRESS), RD2(slot, SDHCI_HOST_VERSION)); slot_printf(slot, "Blk size: 0x%08x | Blk cnt: 0x%08x\n", RD2(slot, SDHCI_BLOCK_SIZE), RD2(slot, SDHCI_BLOCK_COUNT)); slot_printf(slot, "Argument: 0x%08x | Trn mode: 0x%08x\n", RD4(slot, SDHCI_ARGUMENT), RD2(slot, SDHCI_TRANSFER_MODE)); slot_printf(slot, "Present: 0x%08x | Host ctl: 0x%08x\n", RD4(slot, SDHCI_PRESENT_STATE), RD1(slot, SDHCI_HOST_CONTROL)); slot_printf(slot, "Power: 0x%08x | Blk gap: 0x%08x\n", RD1(slot, SDHCI_POWER_CONTROL), RD1(slot, SDHCI_BLOCK_GAP_CONTROL)); slot_printf(slot, "Wake-up: 0x%08x | Clock: 0x%08x\n", RD1(slot, SDHCI_WAKE_UP_CONTROL), RD2(slot, SDHCI_CLOCK_CONTROL)); slot_printf(slot, "Timeout: 0x%08x | Int stat: 0x%08x\n", RD1(slot, SDHCI_TIMEOUT_CONTROL), RD4(slot, SDHCI_INT_STATUS)); slot_printf(slot, "Int enab: 0x%08x | Sig enab: 0x%08x\n", RD4(slot, SDHCI_INT_ENABLE), RD4(slot, SDHCI_SIGNAL_ENABLE)); slot_printf(slot, "AC12 err: 0x%08x | Host ctl2:0x%08x\n", RD2(slot, SDHCI_ACMD12_ERR), RD2(slot, SDHCI_HOST_CONTROL2)); slot_printf(slot, "Caps: 0x%08x | Caps2: 0x%08x\n", RD4(slot, SDHCI_CAPABILITIES), RD4(slot, SDHCI_CAPABILITIES2)); slot_printf(slot, "Max curr: 0x%08x | ADMA err: 0x%08x\n", RD4(slot, SDHCI_MAX_CURRENT), RD1(slot, SDHCI_ADMA_ERR)); slot_printf(slot, "ADMA addr:0x%08x | Slot int: 0x%08x\n", RD4(slot, SDHCI_ADMA_ADDRESS_LO), RD2(slot, SDHCI_SLOT_INT_STATUS)); slot_printf(slot, "===========================================\n"); } static void sdhci_reset(struct sdhci_slot *slot, uint8_t mask) { int timeout; uint32_t clock; if (slot->quirks & SDHCI_QUIRK_NO_CARD_NO_RESET) { if (!SDHCI_GET_CARD_PRESENT(slot->bus, slot)) return; } /* Some controllers need this kick or reset won't work. */ if ((mask & SDHCI_RESET_ALL) == 0 && (slot->quirks & SDHCI_QUIRK_CLOCK_BEFORE_RESET)) { /* This is to force an update */ clock = slot->clock; slot->clock = 0; sdhci_set_clock(slot, clock); } if (mask & SDHCI_RESET_ALL) { slot->clock = 0; slot->power = 0; } WR1(slot, SDHCI_SOFTWARE_RESET, mask); if (slot->quirks & SDHCI_QUIRK_WAITFOR_RESET_ASSERTED) { /* * Resets on TI OMAPs and AM335x are incompatible with SDHCI * specification. The reset bit has internal propagation delay, * so a fast read after write returns 0 even if reset process is * in progress. The workaround is to poll for 1 before polling * for 0. In the worst case, if we miss seeing it asserted the * time we spent waiting is enough to ensure the reset finishes. */ timeout = 10000; while ((RD1(slot, SDHCI_SOFTWARE_RESET) & mask) != mask) { if (timeout <= 0) break; timeout--; DELAY(1); } } /* Wait max 100 ms */ timeout = 10000; /* Controller clears the bits when it's done */ while (RD1(slot, SDHCI_SOFTWARE_RESET) & mask) { if (timeout <= 0) { slot_printf(slot, "Reset 0x%x never completed.\n", mask); sdhci_dumpregs(slot); return; } timeout--; DELAY(10); } } static uint32_t sdhci_tuning_intmask(struct sdhci_slot *slot) { uint32_t intmask; intmask = 0; if (slot->opt & SDHCI_TUNING_SUPPORTED) { intmask |= SDHCI_INT_TUNEERR; if (slot->retune_mode == SDHCI_RETUNE_MODE_2 || slot->retune_mode == SDHCI_RETUNE_MODE_3) intmask |= SDHCI_INT_RETUNE; } return (intmask); } static void sdhci_init(struct sdhci_slot *slot) { sdhci_reset(slot, SDHCI_RESET_ALL); /* Enable interrupts. */ slot->intmask = SDHCI_INT_BUS_POWER | SDHCI_INT_DATA_END_BIT | SDHCI_INT_DATA_CRC | SDHCI_INT_DATA_TIMEOUT | SDHCI_INT_INDEX | SDHCI_INT_END_BIT | SDHCI_INT_CRC | SDHCI_INT_TIMEOUT | SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL | SDHCI_INT_DMA_END | SDHCI_INT_DATA_END | SDHCI_INT_RESPONSE | SDHCI_INT_ACMD12ERR; if (!(slot->quirks & SDHCI_QUIRK_POLL_CARD_PRESENT) && !(slot->opt & SDHCI_NON_REMOVABLE)) { slot->intmask |= SDHCI_INT_CARD_REMOVE | SDHCI_INT_CARD_INSERT; } WR4(slot, SDHCI_INT_ENABLE, slot->intmask | sdhci_tuning_intmask(slot)); WR4(slot, SDHCI_SIGNAL_ENABLE, slot->intmask); } static void sdhci_set_clock(struct sdhci_slot *slot, uint32_t clock) { uint32_t clk_base; uint32_t clk_sel; uint32_t res; uint16_t clk; uint16_t div; int timeout; if (clock == slot->clock) return; slot->clock = clock; /* Turn off the clock. */ clk = RD2(slot, SDHCI_CLOCK_CONTROL); WR2(slot, SDHCI_CLOCK_CONTROL, clk & ~SDHCI_CLOCK_CARD_EN); /* If no clock requested - leave it so. */ if (clock == 0) return; /* Determine the clock base frequency */ clk_base = slot->max_clk; if (slot->quirks & SDHCI_QUIRK_BCM577XX_400KHZ_CLKSRC) { clk_sel = RD2(slot, BCM577XX_HOST_CONTROL) & BCM577XX_CTRL_CLKSEL_MASK; /* * Select clock source appropriate for the requested frequency. */ if ((clk_base / BCM577XX_DEFAULT_MAX_DIVIDER) > clock) { clk_base = BCM577XX_ALT_CLOCK_BASE; clk_sel |= (BCM577XX_CTRL_CLKSEL_64MHZ << BCM577XX_CTRL_CLKSEL_SHIFT); } else { clk_sel |= (BCM577XX_CTRL_CLKSEL_DEFAULT << BCM577XX_CTRL_CLKSEL_SHIFT); } WR2(slot, BCM577XX_HOST_CONTROL, clk_sel); } /* Recalculate timeout clock frequency based on the new sd clock. */ if (slot->quirks & SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK) slot->timeout_clk = slot->clock / 1000; if (slot->version < SDHCI_SPEC_300) { /* Looking for highest freq <= clock. */ res = clk_base; for (div = 1; div < SDHCI_200_MAX_DIVIDER; div <<= 1) { if (res <= clock) break; res >>= 1; } /* Divider 1:1 is 0x00, 2:1 is 0x01, 256:1 is 0x80 ... */ div >>= 1; } else { /* Version 3.0 divisors are multiples of two up to 1023 * 2 */ if (clock >= clk_base) div = 0; else { for (div = 2; div < SDHCI_300_MAX_DIVIDER; div += 2) { if ((clk_base / div) <= clock) break; } } div >>= 1; } if (bootverbose || sdhci_debug) slot_printf(slot, "Divider %d for freq %d (base %d)\n", div, clock, clk_base); /* Now we have got divider, set it. */ clk = (div & SDHCI_DIVIDER_MASK) << SDHCI_DIVIDER_SHIFT; clk |= ((div >> SDHCI_DIVIDER_MASK_LEN) & SDHCI_DIVIDER_HI_MASK) << SDHCI_DIVIDER_HI_SHIFT; WR2(slot, SDHCI_CLOCK_CONTROL, clk); /* Enable clock. */ clk |= SDHCI_CLOCK_INT_EN; WR2(slot, SDHCI_CLOCK_CONTROL, clk); /* Wait up to 10 ms until it stabilize. */ timeout = 10; while (!((clk = RD2(slot, SDHCI_CLOCK_CONTROL)) & SDHCI_CLOCK_INT_STABLE)) { if (timeout == 0) { slot_printf(slot, "Internal clock never stabilised.\n"); sdhci_dumpregs(slot); return; } timeout--; DELAY(1000); } /* Pass clock signal to the bus. */ clk |= SDHCI_CLOCK_CARD_EN; WR2(slot, SDHCI_CLOCK_CONTROL, clk); } static void sdhci_set_power(struct sdhci_slot *slot, u_char power) { int i; uint8_t pwr; if (slot->power == power) return; slot->power = power; /* Turn off the power. */ pwr = 0; WR1(slot, SDHCI_POWER_CONTROL, pwr); /* If power down requested - leave it so. */ if (power == 0) return; /* Set voltage. */ switch (1 << power) { case MMC_OCR_LOW_VOLTAGE: pwr |= SDHCI_POWER_180; break; case MMC_OCR_290_300: case MMC_OCR_300_310: pwr |= SDHCI_POWER_300; break; case MMC_OCR_320_330: case MMC_OCR_330_340: pwr |= SDHCI_POWER_330; break; } WR1(slot, SDHCI_POWER_CONTROL, pwr); /* * Turn on VDD1 power. Note that at least some Intel controllers can * fail to enable bus power on the first try after transiting from D3 * to D0, so we give them up to 2 ms. */ pwr |= SDHCI_POWER_ON; for (i = 0; i < 20; i++) { WR1(slot, SDHCI_POWER_CONTROL, pwr); if (RD1(slot, SDHCI_POWER_CONTROL) & SDHCI_POWER_ON) break; DELAY(100); } if (!(RD1(slot, SDHCI_POWER_CONTROL) & SDHCI_POWER_ON)) slot_printf(slot, "Bus power failed to enable"); if (slot->quirks & SDHCI_QUIRK_INTEL_POWER_UP_RESET) { WR1(slot, SDHCI_POWER_CONTROL, pwr | 0x10); DELAY(10); WR1(slot, SDHCI_POWER_CONTROL, pwr); DELAY(300); } } static void sdhci_read_block_pio(struct sdhci_slot *slot) { uint32_t data; char *buffer; size_t left; buffer = slot->curcmd->data->data; buffer += slot->offset; /* Transfer one block at a time. */ left = min(512, slot->curcmd->data->len - slot->offset); slot->offset += left; /* If we are too fast, broken controllers return zeroes. */ if (slot->quirks & SDHCI_QUIRK_BROKEN_TIMINGS) DELAY(10); /* Handle unaligned and aligned buffer cases. */ if ((intptr_t)buffer & 3) { while (left > 3) { data = RD4(slot, SDHCI_BUFFER); buffer[0] = data; buffer[1] = (data >> 8); buffer[2] = (data >> 16); buffer[3] = (data >> 24); buffer += 4; left -= 4; } } else { RD_MULTI_4(slot, SDHCI_BUFFER, (uint32_t *)buffer, left >> 2); left &= 3; } /* Handle uneven size case. */ if (left > 0) { data = RD4(slot, SDHCI_BUFFER); while (left > 0) { *(buffer++) = data; data >>= 8; left--; } } } static void sdhci_write_block_pio(struct sdhci_slot *slot) { uint32_t data = 0; char *buffer; size_t left; buffer = slot->curcmd->data->data; buffer += slot->offset; /* Transfer one block at a time. */ left = min(512, slot->curcmd->data->len - slot->offset); slot->offset += left; /* Handle unaligned and aligned buffer cases. */ if ((intptr_t)buffer & 3) { while (left > 3) { data = buffer[0] + (buffer[1] << 8) + (buffer[2] << 16) + (buffer[3] << 24); left -= 4; buffer += 4; WR4(slot, SDHCI_BUFFER, data); } } else { WR_MULTI_4(slot, SDHCI_BUFFER, (uint32_t *)buffer, left >> 2); left &= 3; } /* Handle uneven size case. */ if (left > 0) { while (left > 0) { data <<= 8; data += *(buffer++); left--; } WR4(slot, SDHCI_BUFFER, data); } } static void sdhci_transfer_pio(struct sdhci_slot *slot) { /* Read as many blocks as possible. */ if (slot->curcmd->data->flags & MMC_DATA_READ) { while (RD4(slot, SDHCI_PRESENT_STATE) & SDHCI_DATA_AVAILABLE) { sdhci_read_block_pio(slot); if (slot->offset >= slot->curcmd->data->len) break; } } else { while (RD4(slot, SDHCI_PRESENT_STATE) & SDHCI_SPACE_AVAILABLE) { sdhci_write_block_pio(slot); if (slot->offset >= slot->curcmd->data->len) break; } } } static void sdhci_card_task(void *arg, int pending __unused) { struct sdhci_slot *slot = arg; device_t d; SDHCI_LOCK(slot); if (SDHCI_GET_CARD_PRESENT(slot->bus, slot)) { #ifdef MMCCAM if (slot->card_present == 0) { #else if (slot->dev == NULL) { #endif /* If card is present - attach mmc bus. */ if (bootverbose || sdhci_debug) slot_printf(slot, "Card inserted\n"); #ifdef MMCCAM slot->card_present = 1; union ccb *ccb; uint32_t pathid; pathid = cam_sim_path(slot->sim); ccb = xpt_alloc_ccb_nowait(); if (ccb == NULL) { slot_printf(slot, "Unable to alloc CCB for rescan\n"); SDHCI_UNLOCK(slot); return; } /* * We create a rescan request for BUS:0:0, since the card * will be at lun 0. */ if (xpt_create_path(&ccb->ccb_h.path, NULL, pathid, /* target */ 0, /* lun */ 0) != CAM_REQ_CMP) { slot_printf(slot, "Unable to create path for rescan\n"); SDHCI_UNLOCK(slot); xpt_free_ccb(ccb); return; } SDHCI_UNLOCK(slot); xpt_rescan(ccb); #else d = slot->dev = device_add_child(slot->bus, "mmc", -1); SDHCI_UNLOCK(slot); if (d) { device_set_ivars(d, slot); (void)device_probe_and_attach(d); } #endif } else SDHCI_UNLOCK(slot); } else { #ifdef MMCCAM if (slot->card_present == 1) { #else if (slot->dev != NULL) { #endif /* If no card present - detach mmc bus. */ if (bootverbose || sdhci_debug) slot_printf(slot, "Card removed\n"); d = slot->dev; slot->dev = NULL; #ifdef MMCCAM slot->card_present = 0; union ccb *ccb; uint32_t pathid; pathid = cam_sim_path(slot->sim); ccb = xpt_alloc_ccb_nowait(); if (ccb == NULL) { slot_printf(slot, "Unable to alloc CCB for rescan\n"); SDHCI_UNLOCK(slot); return; } /* * We create a rescan request for BUS:0:0, since the card * will be at lun 0. */ if (xpt_create_path(&ccb->ccb_h.path, NULL, pathid, /* target */ 0, /* lun */ 0) != CAM_REQ_CMP) { slot_printf(slot, "Unable to create path for rescan\n"); SDHCI_UNLOCK(slot); xpt_free_ccb(ccb); return; } SDHCI_UNLOCK(slot); xpt_rescan(ccb); #else slot->intmask &= ~sdhci_tuning_intmask(slot); WR4(slot, SDHCI_SIGNAL_ENABLE, slot->intmask); slot->opt &= ~SDHCI_TUNING_ENABLED; SDHCI_UNLOCK(slot); callout_drain(&slot->retune_callout); device_delete_child(slot->bus, d); #endif } else SDHCI_UNLOCK(slot); } } static void sdhci_handle_card_present_locked(struct sdhci_slot *slot, bool is_present) { bool was_present; /* * If there was no card and now there is one, schedule the task to * create the child device after a short delay. The delay is to * debounce the card insert (sometimes the card detect pin stabilizes * before the other pins have made good contact). * * If there was a card present and now it's gone, immediately schedule * the task to delete the child device. No debouncing -- gone is gone, * because once power is removed, a full card re-init is needed, and * that happens by deleting and recreating the child device. */ #ifdef MMCCAM was_present = slot->card_present; #else was_present = slot->dev != NULL; #endif if (!was_present && is_present) { taskqueue_enqueue_timeout(taskqueue_swi_giant, &slot->card_delayed_task, -SDHCI_INSERT_DELAY_TICKS); } else if (was_present && !is_present) { taskqueue_enqueue(taskqueue_swi_giant, &slot->card_task); } } void sdhci_handle_card_present(struct sdhci_slot *slot, bool is_present) { SDHCI_LOCK(slot); sdhci_handle_card_present_locked(slot, is_present); SDHCI_UNLOCK(slot); } static void sdhci_card_poll(void *arg) { struct sdhci_slot *slot = arg; sdhci_handle_card_present(slot, SDHCI_GET_CARD_PRESENT(slot->bus, slot)); callout_reset(&slot->card_poll_callout, SDHCI_CARD_PRESENT_TICKS, sdhci_card_poll, slot); } int sdhci_init_slot(device_t dev, struct sdhci_slot *slot, int num) { kobjop_desc_t kobj_desc; kobj_method_t *kobj_method; uint32_t caps, caps2, freq, host_caps; int err; SDHCI_LOCK_INIT(slot); slot->num = num; slot->bus = dev; /* Allocate DMA tag. */ err = bus_dma_tag_create(bus_get_dma_tag(dev), DMA_BLOCK_SIZE, 0, BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, DMA_BLOCK_SIZE, 1, DMA_BLOCK_SIZE, BUS_DMA_ALLOCNOW, NULL, NULL, &slot->dmatag); if (err != 0) { device_printf(dev, "Can't create DMA tag\n"); SDHCI_LOCK_DESTROY(slot); return (err); } /* Allocate DMA memory. */ err = bus_dmamem_alloc(slot->dmatag, (void **)&slot->dmamem, BUS_DMA_NOWAIT, &slot->dmamap); if (err != 0) { device_printf(dev, "Can't alloc DMA memory\n"); bus_dma_tag_destroy(slot->dmatag); SDHCI_LOCK_DESTROY(slot); return (err); } /* Map the memory. */ err = bus_dmamap_load(slot->dmatag, slot->dmamap, (void *)slot->dmamem, DMA_BLOCK_SIZE, sdhci_getaddr, &slot->paddr, 0); if (err != 0 || slot->paddr == 0) { device_printf(dev, "Can't load DMA memory\n"); bus_dmamem_free(slot->dmatag, slot->dmamem, slot->dmamap); bus_dma_tag_destroy(slot->dmatag); SDHCI_LOCK_DESTROY(slot); if (err) return (err); else return (EFAULT); } slot->version = (RD2(slot, SDHCI_HOST_VERSION) >> SDHCI_SPEC_VER_SHIFT) & SDHCI_SPEC_VER_MASK; if (slot->quirks & SDHCI_QUIRK_MISSING_CAPS) { caps = slot->caps; caps2 = slot->caps2; } else { caps = RD4(slot, SDHCI_CAPABILITIES); if (slot->version >= SDHCI_SPEC_300) caps2 = RD4(slot, SDHCI_CAPABILITIES2); else caps2 = 0; } if (slot->version >= SDHCI_SPEC_300) { if ((caps & SDHCI_SLOTTYPE_MASK) != SDHCI_SLOTTYPE_REMOVABLE && (caps & SDHCI_SLOTTYPE_MASK) != SDHCI_SLOTTYPE_EMBEDDED) { device_printf(dev, "Driver doesn't support shared bus slots\n"); bus_dmamap_unload(slot->dmatag, slot->dmamap); bus_dmamem_free(slot->dmatag, slot->dmamem, slot->dmamap); bus_dma_tag_destroy(slot->dmatag); SDHCI_LOCK_DESTROY(slot); return (ENXIO); } else if ((caps & SDHCI_SLOTTYPE_MASK) == SDHCI_SLOTTYPE_EMBEDDED) { slot->opt |= SDHCI_SLOT_EMBEDDED | SDHCI_NON_REMOVABLE; } } /* Calculate base clock frequency. */ if (slot->version >= SDHCI_SPEC_300) freq = (caps & SDHCI_CLOCK_V3_BASE_MASK) >> SDHCI_CLOCK_BASE_SHIFT; else freq = (caps & SDHCI_CLOCK_BASE_MASK) >> SDHCI_CLOCK_BASE_SHIFT; if (freq != 0) slot->max_clk = freq * 1000000; /* * If the frequency wasn't in the capabilities and the hardware driver * hasn't already set max_clk we're probably not going to work right * with an assumption, so complain about it. */ if (slot->max_clk == 0) { slot->max_clk = SDHCI_DEFAULT_MAX_FREQ * 1000000; device_printf(dev, "Hardware doesn't specify base clock " "frequency, using %dMHz as default.\n", SDHCI_DEFAULT_MAX_FREQ); } /* Calculate/set timeout clock frequency. */ if (slot->quirks & SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK) { slot->timeout_clk = slot->max_clk / 1000; } else if (slot->quirks & SDHCI_QUIRK_DATA_TIMEOUT_1MHZ) { slot->timeout_clk = 1000; } else { slot->timeout_clk = (caps & SDHCI_TIMEOUT_CLK_MASK) >> SDHCI_TIMEOUT_CLK_SHIFT; if (caps & SDHCI_TIMEOUT_CLK_UNIT) slot->timeout_clk *= 1000; } /* * If the frequency wasn't in the capabilities and the hardware driver * hasn't already set timeout_clk we'll probably work okay using the * max timeout, but still mention it. */ if (slot->timeout_clk == 0) { device_printf(dev, "Hardware doesn't specify timeout clock " "frequency, setting BROKEN_TIMEOUT quirk.\n"); slot->quirks |= SDHCI_QUIRK_BROKEN_TIMEOUT_VAL; } slot->host.f_min = SDHCI_MIN_FREQ(slot->bus, slot); slot->host.f_max = slot->max_clk; slot->host.host_ocr = 0; if (caps & SDHCI_CAN_VDD_330) slot->host.host_ocr |= MMC_OCR_320_330 | MMC_OCR_330_340; if (caps & SDHCI_CAN_VDD_300) slot->host.host_ocr |= MMC_OCR_290_300 | MMC_OCR_300_310; /* 1.8V VDD is not supposed to be used for removable cards. */ if ((caps & SDHCI_CAN_VDD_180) && (slot->opt & SDHCI_SLOT_EMBEDDED)) slot->host.host_ocr |= MMC_OCR_LOW_VOLTAGE; if (slot->host.host_ocr == 0) { device_printf(dev, "Hardware doesn't report any " "support voltages.\n"); } host_caps = MMC_CAP_4_BIT_DATA; if (caps & SDHCI_CAN_DO_8BITBUS) host_caps |= MMC_CAP_8_BIT_DATA; if (caps & SDHCI_CAN_DO_HISPD) host_caps |= MMC_CAP_HSPEED; if (slot->quirks & SDHCI_QUIRK_BOOT_NOACC) host_caps |= MMC_CAP_BOOT_NOACC; if (slot->quirks & SDHCI_QUIRK_WAIT_WHILE_BUSY) host_caps |= MMC_CAP_WAIT_WHILE_BUSY; /* Determine supported UHS-I and eMMC modes. */ if (caps2 & (SDHCI_CAN_SDR50 | SDHCI_CAN_SDR104 | SDHCI_CAN_DDR50)) host_caps |= MMC_CAP_UHS_SDR12 | MMC_CAP_UHS_SDR25; if (caps2 & SDHCI_CAN_SDR104) { host_caps |= MMC_CAP_UHS_SDR104 | MMC_CAP_UHS_SDR50; if (!(slot->quirks & SDHCI_QUIRK_BROKEN_MMC_HS200)) host_caps |= MMC_CAP_MMC_HS200; } else if (caps2 & SDHCI_CAN_SDR50) host_caps |= MMC_CAP_UHS_SDR50; if (caps2 & SDHCI_CAN_DDR50 && !(slot->quirks & SDHCI_QUIRK_BROKEN_UHS_DDR50)) host_caps |= MMC_CAP_UHS_DDR50; if (slot->quirks & SDHCI_QUIRK_MMC_DDR52) host_caps |= MMC_CAP_MMC_DDR52; if (slot->quirks & SDHCI_QUIRK_CAPS_BIT63_FOR_MMC_HS400 && caps2 & SDHCI_CAN_MMC_HS400) host_caps |= MMC_CAP_MMC_HS400; /* * Disable UHS-I and eMMC modes if the set_uhs_timing method is the * default NULL implementation. */ kobj_desc = &sdhci_set_uhs_timing_desc; kobj_method = kobj_lookup_method(((kobj_t)dev)->ops->cls, NULL, kobj_desc); if (kobj_method == &kobj_desc->deflt) host_caps &= ~(MMC_CAP_UHS_SDR12 | MMC_CAP_UHS_SDR25 | MMC_CAP_UHS_SDR50 | MMC_CAP_UHS_DDR50 | MMC_CAP_UHS_SDR104 | MMC_CAP_MMC_DDR52 | MMC_CAP_MMC_HS200 | MMC_CAP_MMC_HS400); #define SDHCI_CAP_MODES_TUNING(caps2) \ (((caps2) & SDHCI_TUNE_SDR50 ? MMC_CAP_UHS_SDR50 : 0) | \ MMC_CAP_UHS_DDR50 | MMC_CAP_UHS_SDR104 | MMC_CAP_MMC_HS200 | \ MMC_CAP_MMC_HS400) /* * Disable UHS-I and eMMC modes that require (re-)tuning if either * the tune or re-tune method is the default NULL implementation. */ kobj_desc = &mmcbr_tune_desc; kobj_method = kobj_lookup_method(((kobj_t)dev)->ops->cls, NULL, kobj_desc); if (kobj_method == &kobj_desc->deflt) goto no_tuning; kobj_desc = &mmcbr_retune_desc; kobj_method = kobj_lookup_method(((kobj_t)dev)->ops->cls, NULL, kobj_desc); if (kobj_method == &kobj_desc->deflt) { no_tuning: host_caps &= ~(SDHCI_CAP_MODES_TUNING(caps2)); } /* Allocate tuning structures and determine tuning parameters. */ if (host_caps & SDHCI_CAP_MODES_TUNING(caps2)) { slot->opt |= SDHCI_TUNING_SUPPORTED; slot->tune_req = malloc(sizeof(*slot->tune_req), M_DEVBUF, M_WAITOK); slot->tune_cmd = malloc(sizeof(*slot->tune_cmd), M_DEVBUF, M_WAITOK); slot->tune_data = malloc(sizeof(*slot->tune_data), M_DEVBUF, M_WAITOK); if (caps2 & SDHCI_TUNE_SDR50) slot->opt |= SDHCI_SDR50_NEEDS_TUNING; slot->retune_mode = (caps2 & SDHCI_RETUNE_MODES_MASK) >> SDHCI_RETUNE_MODES_SHIFT; if (slot->retune_mode == SDHCI_RETUNE_MODE_1) { slot->retune_count = (caps2 & SDHCI_RETUNE_CNT_MASK) >> SDHCI_RETUNE_CNT_SHIFT; if (slot->retune_count > 0xb) { device_printf(dev, "Unknown re-tuning count " "%x, using 1 sec\n", slot->retune_count); slot->retune_count = 1; } else if (slot->retune_count != 0) slot->retune_count = 1 << (slot->retune_count - 1); } } #undef SDHCI_CAP_MODES_TUNING /* Determine supported VCCQ signaling levels. */ host_caps |= MMC_CAP_SIGNALING_330; if (host_caps & (MMC_CAP_UHS_SDR12 | MMC_CAP_UHS_SDR25 | MMC_CAP_UHS_SDR50 | MMC_CAP_UHS_DDR50 | MMC_CAP_UHS_SDR104 | MMC_CAP_MMC_DDR52_180 | MMC_CAP_MMC_HS200_180 | MMC_CAP_MMC_HS400_180)) host_caps |= MMC_CAP_SIGNALING_120 | MMC_CAP_SIGNALING_180; /* * Disable 1.2 V and 1.8 V signaling if the switch_vccq method is the * default NULL implementation. Disable 1.2 V support if it's the * generic SDHCI implementation. */ kobj_desc = &mmcbr_switch_vccq_desc; kobj_method = kobj_lookup_method(((kobj_t)dev)->ops->cls, NULL, kobj_desc); if (kobj_method == &kobj_desc->deflt) host_caps &= ~(MMC_CAP_SIGNALING_120 | MMC_CAP_SIGNALING_180); else if (kobj_method->func == (kobjop_t)sdhci_generic_switch_vccq) host_caps &= ~MMC_CAP_SIGNALING_120; /* Determine supported driver types (type B is always mandatory). */ if (caps2 & SDHCI_CAN_DRIVE_TYPE_A) host_caps |= MMC_CAP_DRIVER_TYPE_A; if (caps2 & SDHCI_CAN_DRIVE_TYPE_C) host_caps |= MMC_CAP_DRIVER_TYPE_C; if (caps2 & SDHCI_CAN_DRIVE_TYPE_D) host_caps |= MMC_CAP_DRIVER_TYPE_D; slot->host.caps = host_caps; /* Decide if we have usable DMA. */ if (caps & SDHCI_CAN_DO_DMA) slot->opt |= SDHCI_HAVE_DMA; if (slot->quirks & SDHCI_QUIRK_BROKEN_DMA) slot->opt &= ~SDHCI_HAVE_DMA; if (slot->quirks & SDHCI_QUIRK_FORCE_DMA) slot->opt |= SDHCI_HAVE_DMA; if (slot->quirks & SDHCI_QUIRK_ALL_SLOTS_NON_REMOVABLE) slot->opt |= SDHCI_NON_REMOVABLE; /* * Use platform-provided transfer backend * with PIO as a fallback mechanism */ if (slot->opt & SDHCI_PLATFORM_TRANSFER) slot->opt &= ~SDHCI_HAVE_DMA; if (bootverbose || sdhci_debug) { slot_printf(slot, "%uMHz%s %s VDD:%s%s%s VCCQ: 3.3V%s%s DRV: B%s%s%s %s %s\n", slot->max_clk / 1000000, (caps & SDHCI_CAN_DO_HISPD) ? " HS" : "", (host_caps & MMC_CAP_8_BIT_DATA) ? "8bits" : ((host_caps & MMC_CAP_4_BIT_DATA) ? "4bits" : "1bit"), (caps & SDHCI_CAN_VDD_330) ? " 3.3V" : "", (caps & SDHCI_CAN_VDD_300) ? " 3.0V" : "", ((caps & SDHCI_CAN_VDD_180) && (slot->opt & SDHCI_SLOT_EMBEDDED)) ? " 1.8V" : "", (host_caps & MMC_CAP_SIGNALING_180) ? " 1.8V" : "", (host_caps & MMC_CAP_SIGNALING_120) ? " 1.2V" : "", (host_caps & MMC_CAP_DRIVER_TYPE_A) ? "A" : "", (host_caps & MMC_CAP_DRIVER_TYPE_C) ? "C" : "", (host_caps & MMC_CAP_DRIVER_TYPE_D) ? "D" : "", (slot->opt & SDHCI_HAVE_DMA) ? "DMA" : "PIO", (slot->opt & SDHCI_SLOT_EMBEDDED) ? "embedded" : (slot->opt & SDHCI_NON_REMOVABLE) ? "non-removable" : "removable"); if (host_caps & (MMC_CAP_MMC_DDR52 | MMC_CAP_MMC_HS200 | MMC_CAP_MMC_HS400 | MMC_CAP_MMC_ENH_STROBE)) slot_printf(slot, "eMMC:%s%s%s%s\n", (host_caps & MMC_CAP_MMC_DDR52) ? " DDR52" : "", (host_caps & MMC_CAP_MMC_HS200) ? " HS200" : "", (host_caps & MMC_CAP_MMC_HS400) ? " HS400" : "", ((host_caps & (MMC_CAP_MMC_HS400 | MMC_CAP_MMC_ENH_STROBE)) == (MMC_CAP_MMC_HS400 | MMC_CAP_MMC_ENH_STROBE)) ? " HS400ES" : ""); if (host_caps & (MMC_CAP_UHS_SDR12 | MMC_CAP_UHS_SDR25 | MMC_CAP_UHS_SDR50 | MMC_CAP_UHS_SDR104)) slot_printf(slot, "UHS-I:%s%s%s%s%s\n", (host_caps & MMC_CAP_UHS_SDR12) ? " SDR12" : "", (host_caps & MMC_CAP_UHS_SDR25) ? " SDR25" : "", (host_caps & MMC_CAP_UHS_SDR50) ? " SDR50" : "", (host_caps & MMC_CAP_UHS_SDR104) ? " SDR104" : "", (host_caps & MMC_CAP_UHS_DDR50) ? " DDR50" : ""); if (slot->opt & SDHCI_TUNING_SUPPORTED) slot_printf(slot, "Re-tuning count %d secs, mode %d\n", slot->retune_count, slot->retune_mode + 1); sdhci_dumpregs(slot); } slot->timeout = 10; SYSCTL_ADD_INT(device_get_sysctl_ctx(slot->bus), SYSCTL_CHILDREN(device_get_sysctl_tree(slot->bus)), OID_AUTO, "timeout", CTLFLAG_RW, &slot->timeout, 0, "Maximum timeout for SDHCI transfers (in secs)"); TASK_INIT(&slot->card_task, 0, sdhci_card_task, slot); TIMEOUT_TASK_INIT(taskqueue_swi_giant, &slot->card_delayed_task, 0, sdhci_card_task, slot); callout_init(&slot->card_poll_callout, 1); callout_init_mtx(&slot->timeout_callout, &slot->mtx, 0); callout_init_mtx(&slot->retune_callout, &slot->mtx, 0); if ((slot->quirks & SDHCI_QUIRK_POLL_CARD_PRESENT) && !(slot->opt & SDHCI_NON_REMOVABLE)) { callout_reset(&slot->card_poll_callout, SDHCI_CARD_PRESENT_TICKS, sdhci_card_poll, slot); } sdhci_init(slot); return (0); } +#ifndef MMCCAM void sdhci_start_slot(struct sdhci_slot *slot) { sdhci_card_task(slot, 0); } +#endif int sdhci_cleanup_slot(struct sdhci_slot *slot) { device_t d; callout_drain(&slot->timeout_callout); callout_drain(&slot->card_poll_callout); callout_drain(&slot->retune_callout); taskqueue_drain(taskqueue_swi_giant, &slot->card_task); taskqueue_drain_timeout(taskqueue_swi_giant, &slot->card_delayed_task); SDHCI_LOCK(slot); d = slot->dev; slot->dev = NULL; SDHCI_UNLOCK(slot); if (d != NULL) device_delete_child(slot->bus, d); SDHCI_LOCK(slot); sdhci_reset(slot, SDHCI_RESET_ALL); SDHCI_UNLOCK(slot); bus_dmamap_unload(slot->dmatag, slot->dmamap); bus_dmamem_free(slot->dmatag, slot->dmamem, slot->dmamap); bus_dma_tag_destroy(slot->dmatag); if (slot->opt & SDHCI_TUNING_SUPPORTED) { free(slot->tune_req, M_DEVBUF); free(slot->tune_cmd, M_DEVBUF); free(slot->tune_data, M_DEVBUF); } SDHCI_LOCK_DESTROY(slot); return (0); } int sdhci_generic_suspend(struct sdhci_slot *slot) { /* * We expect the MMC layer to issue initial tuning after resume. * Otherwise, we'd need to indicate re-tuning including circuit reset * being required at least for re-tuning modes 1 and 2 ourselves. */ callout_drain(&slot->retune_callout); SDHCI_LOCK(slot); slot->opt &= ~SDHCI_TUNING_ENABLED; sdhci_reset(slot, SDHCI_RESET_ALL); SDHCI_UNLOCK(slot); return (0); } int sdhci_generic_resume(struct sdhci_slot *slot) { SDHCI_LOCK(slot); sdhci_init(slot); SDHCI_UNLOCK(slot); return (0); } uint32_t sdhci_generic_min_freq(device_t brdev __unused, struct sdhci_slot *slot) { if (slot->version >= SDHCI_SPEC_300) return (slot->max_clk / SDHCI_300_MAX_DIVIDER); else return (slot->max_clk / SDHCI_200_MAX_DIVIDER); } bool sdhci_generic_get_card_present(device_t brdev __unused, struct sdhci_slot *slot) { if (slot->opt & SDHCI_NON_REMOVABLE) return true; return (RD4(slot, SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT); } void sdhci_generic_set_uhs_timing(device_t brdev __unused, struct sdhci_slot *slot) { struct mmc_ios *ios; uint16_t hostctrl2; if (slot->version < SDHCI_SPEC_300) return; SDHCI_ASSERT_LOCKED(slot); ios = &slot->host.ios; sdhci_set_clock(slot, 0); hostctrl2 = RD2(slot, SDHCI_HOST_CONTROL2); hostctrl2 &= ~SDHCI_CTRL2_UHS_MASK; if (ios->clock > SD_SDR50_MAX) { if (ios->timing == bus_timing_mmc_hs400 || ios->timing == bus_timing_mmc_hs400es) hostctrl2 |= SDHCI_CTRL2_MMC_HS400; else hostctrl2 |= SDHCI_CTRL2_UHS_SDR104; } else if (ios->clock > SD_SDR25_MAX) hostctrl2 |= SDHCI_CTRL2_UHS_SDR50; else if (ios->clock > SD_SDR12_MAX) { if (ios->timing == bus_timing_uhs_ddr50 || ios->timing == bus_timing_mmc_ddr52) hostctrl2 |= SDHCI_CTRL2_UHS_DDR50; else hostctrl2 |= SDHCI_CTRL2_UHS_SDR25; } else if (ios->clock > SD_MMC_CARD_ID_FREQUENCY) hostctrl2 |= SDHCI_CTRL2_UHS_SDR12; WR2(slot, SDHCI_HOST_CONTROL2, hostctrl2); sdhci_set_clock(slot, ios->clock); } int sdhci_generic_update_ios(device_t brdev, device_t reqdev) { struct sdhci_slot *slot = device_get_ivars(reqdev); struct mmc_ios *ios = &slot->host.ios; SDHCI_LOCK(slot); /* Do full reset on bus power down to clear from any state. */ if (ios->power_mode == power_off) { WR4(slot, SDHCI_SIGNAL_ENABLE, 0); sdhci_init(slot); } /* Configure the bus. */ sdhci_set_clock(slot, ios->clock); sdhci_set_power(slot, (ios->power_mode == power_off) ? 0 : ios->vdd); if (ios->bus_width == bus_width_8) { slot->hostctrl |= SDHCI_CTRL_8BITBUS; slot->hostctrl &= ~SDHCI_CTRL_4BITBUS; } else if (ios->bus_width == bus_width_4) { slot->hostctrl &= ~SDHCI_CTRL_8BITBUS; slot->hostctrl |= SDHCI_CTRL_4BITBUS; } else if (ios->bus_width == bus_width_1) { slot->hostctrl &= ~SDHCI_CTRL_8BITBUS; slot->hostctrl &= ~SDHCI_CTRL_4BITBUS; } else { panic("Invalid bus width: %d", ios->bus_width); } if (ios->clock > SD_SDR12_MAX && !(slot->quirks & SDHCI_QUIRK_DONT_SET_HISPD_BIT)) slot->hostctrl |= SDHCI_CTRL_HISPD; else slot->hostctrl &= ~SDHCI_CTRL_HISPD; WR1(slot, SDHCI_HOST_CONTROL, slot->hostctrl); SDHCI_SET_UHS_TIMING(brdev, slot); /* Some controllers like reset after bus changes. */ if (slot->quirks & SDHCI_QUIRK_RESET_ON_IOS) sdhci_reset(slot, SDHCI_RESET_CMD | SDHCI_RESET_DATA); SDHCI_UNLOCK(slot); return (0); } int sdhci_generic_switch_vccq(device_t brdev __unused, device_t reqdev) { struct sdhci_slot *slot = device_get_ivars(reqdev); enum mmc_vccq vccq; int err; uint16_t hostctrl2; if (slot->version < SDHCI_SPEC_300) return (0); err = 0; vccq = slot->host.ios.vccq; SDHCI_LOCK(slot); sdhci_set_clock(slot, 0); hostctrl2 = RD2(slot, SDHCI_HOST_CONTROL2); switch (vccq) { case vccq_330: if (!(hostctrl2 & SDHCI_CTRL2_S18_ENABLE)) goto done; hostctrl2 &= ~SDHCI_CTRL2_S18_ENABLE; WR2(slot, SDHCI_HOST_CONTROL2, hostctrl2); DELAY(5000); hostctrl2 = RD2(slot, SDHCI_HOST_CONTROL2); if (!(hostctrl2 & SDHCI_CTRL2_S18_ENABLE)) goto done; err = EAGAIN; break; case vccq_180: if (!(slot->host.caps & MMC_CAP_SIGNALING_180)) { err = EINVAL; goto done; } if (hostctrl2 & SDHCI_CTRL2_S18_ENABLE) goto done; hostctrl2 |= SDHCI_CTRL2_S18_ENABLE; WR2(slot, SDHCI_HOST_CONTROL2, hostctrl2); DELAY(5000); hostctrl2 = RD2(slot, SDHCI_HOST_CONTROL2); if (hostctrl2 & SDHCI_CTRL2_S18_ENABLE) goto done; err = EAGAIN; break; default: slot_printf(slot, "Attempt to set unsupported signaling voltage\n"); err = EINVAL; break; } done: sdhci_set_clock(slot, slot->host.ios.clock); SDHCI_UNLOCK(slot); return (err); } int sdhci_generic_tune(device_t brdev __unused, device_t reqdev, bool hs400) { struct sdhci_slot *slot = device_get_ivars(reqdev); struct mmc_ios *ios = &slot->host.ios; struct mmc_command *tune_cmd; struct mmc_data *tune_data; uint32_t opcode; int err; if (!(slot->opt & SDHCI_TUNING_SUPPORTED)) return (0); slot->retune_ticks = slot->retune_count * hz; opcode = MMC_SEND_TUNING_BLOCK; SDHCI_LOCK(slot); switch (ios->timing) { case bus_timing_mmc_hs400: slot_printf(slot, "HS400 must be tuned in HS200 mode\n"); SDHCI_UNLOCK(slot); return (EINVAL); case bus_timing_mmc_hs200: /* * In HS400 mode, controllers use the data strobe line to * latch data from the devices so periodic re-tuning isn't * expected to be required. */ if (hs400) slot->retune_ticks = 0; opcode = MMC_SEND_TUNING_BLOCK_HS200; break; case bus_timing_uhs_ddr50: case bus_timing_uhs_sdr104: break; case bus_timing_uhs_sdr50: if (slot->opt & SDHCI_SDR50_NEEDS_TUNING) break; /* FALLTHROUGH */ default: SDHCI_UNLOCK(slot); return (0); } tune_cmd = slot->tune_cmd; memset(tune_cmd, 0, sizeof(*tune_cmd)); tune_cmd->opcode = opcode; tune_cmd->flags = MMC_RSP_R1 | MMC_CMD_ADTC; tune_data = tune_cmd->data = slot->tune_data; memset(tune_data, 0, sizeof(*tune_data)); tune_data->len = (opcode == MMC_SEND_TUNING_BLOCK_HS200 && ios->bus_width == bus_width_8) ? MMC_TUNING_LEN_HS200 : MMC_TUNING_LEN; tune_data->flags = MMC_DATA_READ; tune_data->mrq = tune_cmd->mrq = slot->tune_req; slot->opt &= ~SDHCI_TUNING_ENABLED; err = sdhci_exec_tuning(slot, true); if (err == 0) { slot->opt |= SDHCI_TUNING_ENABLED; slot->intmask |= sdhci_tuning_intmask(slot); WR4(slot, SDHCI_SIGNAL_ENABLE, slot->intmask); if (slot->retune_ticks) { callout_reset(&slot->retune_callout, slot->retune_ticks, sdhci_retune, slot); } } SDHCI_UNLOCK(slot); return (err); } int sdhci_generic_retune(device_t brdev __unused, device_t reqdev, bool reset) { struct sdhci_slot *slot = device_get_ivars(reqdev); int err; if (!(slot->opt & SDHCI_TUNING_ENABLED)) return (0); /* HS400 must be tuned in HS200 mode. */ if (slot->host.ios.timing == bus_timing_mmc_hs400) return (EINVAL); SDHCI_LOCK(slot); err = sdhci_exec_tuning(slot, reset); /* * There are two ways sdhci_exec_tuning() can fail: * EBUSY should not actually happen when requests are only issued * with the host properly acquired, and * EIO re-tuning failed (but it did work initially). * * In both cases, we should retry at later point if periodic re-tuning * is enabled. Note that due to slot->retune_req not being cleared in * these failure cases, the MMC layer should trigger another attempt at * re-tuning with the next request anyway, though. */ if (slot->retune_ticks) { callout_reset(&slot->retune_callout, slot->retune_ticks, sdhci_retune, slot); } SDHCI_UNLOCK(slot); return (err); } static int sdhci_exec_tuning(struct sdhci_slot *slot, bool reset) { struct mmc_request *tune_req; struct mmc_command *tune_cmd; int i; uint32_t intmask; uint16_t hostctrl2; u_char opt; SDHCI_ASSERT_LOCKED(slot); if (slot->req != NULL) return (EBUSY); /* Tuning doesn't work with DMA enabled. */ opt = slot->opt; slot->opt = opt & ~SDHCI_HAVE_DMA; /* * Ensure that as documented, SDHCI_INT_DATA_AVAIL is the only * kind of interrupt we receive in response to a tuning request. */ intmask = slot->intmask; slot->intmask = SDHCI_INT_DATA_AVAIL; WR4(slot, SDHCI_SIGNAL_ENABLE, SDHCI_INT_DATA_AVAIL); hostctrl2 = RD2(slot, SDHCI_HOST_CONTROL2); if (reset) hostctrl2 &= ~SDHCI_CTRL2_SAMPLING_CLOCK; else hostctrl2 |= SDHCI_CTRL2_SAMPLING_CLOCK; WR2(slot, SDHCI_HOST_CONTROL2, hostctrl2 | SDHCI_CTRL2_EXEC_TUNING); tune_req = slot->tune_req; tune_cmd = slot->tune_cmd; for (i = 0; i < MMC_TUNING_MAX; i++) { memset(tune_req, 0, sizeof(*tune_req)); tune_req->cmd = tune_cmd; tune_req->done = sdhci_req_wakeup; tune_req->done_data = slot; slot->req = tune_req; slot->flags = 0; sdhci_start(slot); while (!(tune_req->flags & MMC_REQ_DONE)) msleep(tune_req, &slot->mtx, 0, "sdhciet", 0); if (!(tune_req->flags & MMC_TUNE_DONE)) break; hostctrl2 = RD2(slot, SDHCI_HOST_CONTROL2); if (!(hostctrl2 & SDHCI_CTRL2_EXEC_TUNING)) break; if (tune_cmd->opcode == MMC_SEND_TUNING_BLOCK) DELAY(1000); } slot->opt = opt; slot->intmask = intmask; WR4(slot, SDHCI_SIGNAL_ENABLE, intmask); if ((hostctrl2 & (SDHCI_CTRL2_EXEC_TUNING | SDHCI_CTRL2_SAMPLING_CLOCK)) == SDHCI_CTRL2_SAMPLING_CLOCK) { slot->retune_req = 0; return (0); } slot_printf(slot, "Tuning failed, using fixed sampling clock\n"); WR2(slot, SDHCI_HOST_CONTROL2, hostctrl2 & ~(SDHCI_CTRL2_EXEC_TUNING | SDHCI_CTRL2_SAMPLING_CLOCK)); sdhci_reset(slot, SDHCI_RESET_CMD | SDHCI_RESET_DATA); return (EIO); } static void sdhci_retune(void *arg) { struct sdhci_slot *slot = arg; slot->retune_req |= SDHCI_RETUNE_REQ_NEEDED; } #ifdef MMCCAM static void sdhci_req_done(struct sdhci_slot *slot) { union ccb *ccb; if (__predict_false(sdhci_debug > 1)) slot_printf(slot, "%s\n", __func__); if (slot->ccb != NULL && slot->curcmd != NULL) { callout_stop(&slot->timeout_callout); ccb = slot->ccb; slot->ccb = NULL; slot->curcmd = NULL; /* Tell CAM the request is finished */ struct ccb_mmcio *mmcio; mmcio = &ccb->mmcio; ccb->ccb_h.status = (mmcio->cmd.error == 0 ? CAM_REQ_CMP : CAM_REQ_CMP_ERR); xpt_done(ccb); } } #else static void sdhci_req_done(struct sdhci_slot *slot) { struct mmc_request *req; if (slot->req != NULL && slot->curcmd != NULL) { callout_stop(&slot->timeout_callout); req = slot->req; slot->req = NULL; slot->curcmd = NULL; req->done(req); } } #endif static void sdhci_req_wakeup(struct mmc_request *req) { struct sdhci_slot *slot; slot = req->done_data; req->flags |= MMC_REQ_DONE; wakeup(req); } static void sdhci_timeout(void *arg) { struct sdhci_slot *slot = arg; if (slot->curcmd != NULL) { slot_printf(slot, "Controller timeout\n"); sdhci_dumpregs(slot); sdhci_reset(slot, SDHCI_RESET_CMD | SDHCI_RESET_DATA); slot->curcmd->error = MMC_ERR_TIMEOUT; sdhci_req_done(slot); } else { slot_printf(slot, "Spurious timeout - no active command\n"); } } static void sdhci_set_transfer_mode(struct sdhci_slot *slot, struct mmc_data *data) { uint16_t mode; if (data == NULL) return; mode = SDHCI_TRNS_BLK_CNT_EN; if (data->len > 512) mode |= SDHCI_TRNS_MULTI; if (data->flags & MMC_DATA_READ) mode |= SDHCI_TRNS_READ; #ifdef MMCCAM struct ccb_mmcio *mmcio; mmcio = &slot->ccb->mmcio; if (mmcio->stop.opcode == MMC_STOP_TRANSMISSION && !(slot->quirks & SDHCI_QUIRK_BROKEN_AUTO_STOP)) mode |= SDHCI_TRNS_ACMD12; #else if (slot->req->stop && !(slot->quirks & SDHCI_QUIRK_BROKEN_AUTO_STOP)) mode |= SDHCI_TRNS_ACMD12; #endif if (slot->flags & SDHCI_USE_DMA) mode |= SDHCI_TRNS_DMA; WR2(slot, SDHCI_TRANSFER_MODE, mode); } static void sdhci_start_command(struct sdhci_slot *slot, struct mmc_command *cmd) { int flags, timeout; uint32_t mask; slot->curcmd = cmd; slot->cmd_done = 0; cmd->error = MMC_ERR_NONE; /* This flags combination is not supported by controller. */ if ((cmd->flags & MMC_RSP_136) && (cmd->flags & MMC_RSP_BUSY)) { slot_printf(slot, "Unsupported response type!\n"); cmd->error = MMC_ERR_FAILED; sdhci_req_done(slot); return; } /* * Do not issue command if there is no card, clock or power. * Controller will not detect timeout without clock active. */ if (!SDHCI_GET_CARD_PRESENT(slot->bus, slot) || slot->power == 0 || slot->clock == 0) { slot_printf(slot, "Cannot issue a command (power=%d clock=%d)", slot->power, slot->clock); cmd->error = MMC_ERR_FAILED; sdhci_req_done(slot); return; } /* Always wait for free CMD bus. */ mask = SDHCI_CMD_INHIBIT; /* Wait for free DAT if we have data or busy signal. */ if (cmd->data != NULL || (cmd->flags & MMC_RSP_BUSY)) mask |= SDHCI_DAT_INHIBIT; /* * We shouldn't wait for DAT for stop commands or CMD19/CMD21. Note * that these latter are also special in that SDHCI_CMD_DATA should * be set below but no actual data is ever read from the controller. */ #ifdef MMCCAM if (cmd == &slot->ccb->mmcio.stop || #else if (cmd == slot->req->stop || #endif __predict_false(cmd->opcode == MMC_SEND_TUNING_BLOCK || cmd->opcode == MMC_SEND_TUNING_BLOCK_HS200)) mask &= ~SDHCI_DAT_INHIBIT; /* * Wait for bus no more then 250 ms. Typically there will be no wait * here at all, but when writing a crash dump we may be bypassing the * host platform's interrupt handler, and in some cases that handler * may be working around hardware quirks such as not respecting r1b * busy indications. In those cases, this wait-loop serves the purpose * of waiting for the prior command and data transfers to be done, and * SD cards are allowed to take up to 250ms for write and erase ops. * (It's usually more like 20-30ms in the real world.) */ timeout = 250; while (mask & RD4(slot, SDHCI_PRESENT_STATE)) { if (timeout == 0) { slot_printf(slot, "Controller never released " "inhibit bit(s).\n"); sdhci_dumpregs(slot); cmd->error = MMC_ERR_FAILED; sdhci_req_done(slot); return; } timeout--; DELAY(1000); } /* Prepare command flags. */ if (!(cmd->flags & MMC_RSP_PRESENT)) flags = SDHCI_CMD_RESP_NONE; else if (cmd->flags & MMC_RSP_136) flags = SDHCI_CMD_RESP_LONG; else if (cmd->flags & MMC_RSP_BUSY) flags = SDHCI_CMD_RESP_SHORT_BUSY; else flags = SDHCI_CMD_RESP_SHORT; if (cmd->flags & MMC_RSP_CRC) flags |= SDHCI_CMD_CRC; if (cmd->flags & MMC_RSP_OPCODE) flags |= SDHCI_CMD_INDEX; if (cmd->data != NULL) flags |= SDHCI_CMD_DATA; if (cmd->opcode == MMC_STOP_TRANSMISSION) flags |= SDHCI_CMD_TYPE_ABORT; /* Prepare data. */ sdhci_start_data(slot, cmd->data); /* * Interrupt aggregation: To reduce total number of interrupts * group response interrupt with data interrupt when possible. * If there going to be data interrupt, mask response one. */ if (slot->data_done == 0) { WR4(slot, SDHCI_SIGNAL_ENABLE, slot->intmask &= ~SDHCI_INT_RESPONSE); } /* Set command argument. */ WR4(slot, SDHCI_ARGUMENT, cmd->arg); /* Set data transfer mode. */ sdhci_set_transfer_mode(slot, cmd->data); if (__predict_false(sdhci_debug > 1)) slot_printf(slot, "Starting command!\n"); /* Start command. */ WR2(slot, SDHCI_COMMAND_FLAGS, (cmd->opcode << 8) | (flags & 0xff)); /* Start timeout callout. */ callout_reset(&slot->timeout_callout, slot->timeout * hz, sdhci_timeout, slot); } static void sdhci_finish_command(struct sdhci_slot *slot) { int i; uint32_t val; uint8_t extra; if (__predict_false(sdhci_debug > 1)) slot_printf(slot, "%s: called, err %d flags %d\n", __func__, slot->curcmd->error, slot->curcmd->flags); slot->cmd_done = 1; /* * Interrupt aggregation: Restore command interrupt. * Main restore point for the case when command interrupt * happened first. */ if (__predict_true(slot->curcmd->opcode != MMC_SEND_TUNING_BLOCK && slot->curcmd->opcode != MMC_SEND_TUNING_BLOCK_HS200)) WR4(slot, SDHCI_SIGNAL_ENABLE, slot->intmask |= SDHCI_INT_RESPONSE); /* In case of error - reset host and return. */ if (slot->curcmd->error) { if (slot->curcmd->error == MMC_ERR_BADCRC) slot->retune_req |= SDHCI_RETUNE_REQ_RESET; sdhci_reset(slot, SDHCI_RESET_CMD); sdhci_reset(slot, SDHCI_RESET_DATA); sdhci_start(slot); return; } /* If command has response - fetch it. */ if (slot->curcmd->flags & MMC_RSP_PRESENT) { if (slot->curcmd->flags & MMC_RSP_136) { /* CRC is stripped so we need one byte shift. */ extra = 0; for (i = 0; i < 4; i++) { val = RD4(slot, SDHCI_RESPONSE + i * 4); if (slot->quirks & SDHCI_QUIRK_DONT_SHIFT_RESPONSE) slot->curcmd->resp[3 - i] = val; else { slot->curcmd->resp[3 - i] = (val << 8) | extra; extra = val >> 24; } } } else slot->curcmd->resp[0] = RD4(slot, SDHCI_RESPONSE); } if (__predict_false(sdhci_debug > 1)) printf("Resp: %02x %02x %02x %02x\n", slot->curcmd->resp[0], slot->curcmd->resp[1], slot->curcmd->resp[2], slot->curcmd->resp[3]); /* If data ready - finish. */ if (slot->data_done) sdhci_start(slot); } static void sdhci_start_data(struct sdhci_slot *slot, struct mmc_data *data) { uint32_t target_timeout, current_timeout; uint8_t div; if (data == NULL && (slot->curcmd->flags & MMC_RSP_BUSY) == 0) { slot->data_done = 1; return; } slot->data_done = 0; /* Calculate and set data timeout.*/ /* XXX: We should have this from mmc layer, now assume 1 sec. */ if (slot->quirks & SDHCI_QUIRK_BROKEN_TIMEOUT_VAL) { div = 0xE; } else { target_timeout = 1000000; div = 0; current_timeout = (1 << 13) * 1000 / slot->timeout_clk; while (current_timeout < target_timeout && div < 0xE) { ++div; current_timeout <<= 1; } /* Compensate for an off-by-one error in the CaFe chip.*/ if (div < 0xE && (slot->quirks & SDHCI_QUIRK_INCR_TIMEOUT_CONTROL)) { ++div; } } WR1(slot, SDHCI_TIMEOUT_CONTROL, div); if (data == NULL) return; /* Use DMA if possible. */ if ((slot->opt & SDHCI_HAVE_DMA)) slot->flags |= SDHCI_USE_DMA; /* If data is small, broken DMA may return zeroes instead of data, */ if ((slot->quirks & SDHCI_QUIRK_BROKEN_TIMINGS) && (data->len <= 512)) slot->flags &= ~SDHCI_USE_DMA; /* Some controllers require even block sizes. */ if ((slot->quirks & SDHCI_QUIRK_32BIT_DMA_SIZE) && ((data->len) & 0x3)) slot->flags &= ~SDHCI_USE_DMA; /* Load DMA buffer. */ if (slot->flags & SDHCI_USE_DMA) { if (data->flags & MMC_DATA_READ) bus_dmamap_sync(slot->dmatag, slot->dmamap, BUS_DMASYNC_PREREAD); else { memcpy(slot->dmamem, data->data, (data->len < DMA_BLOCK_SIZE) ? data->len : DMA_BLOCK_SIZE); bus_dmamap_sync(slot->dmatag, slot->dmamap, BUS_DMASYNC_PREWRITE); } WR4(slot, SDHCI_DMA_ADDRESS, slot->paddr); /* Interrupt aggregation: Mask border interrupt * for the last page and unmask else. */ if (data->len == DMA_BLOCK_SIZE) slot->intmask &= ~SDHCI_INT_DMA_END; else slot->intmask |= SDHCI_INT_DMA_END; WR4(slot, SDHCI_SIGNAL_ENABLE, slot->intmask); } /* Current data offset for both PIO and DMA. */ slot->offset = 0; /* Set block size and request IRQ on 4K border. */ WR2(slot, SDHCI_BLOCK_SIZE, SDHCI_MAKE_BLKSZ(DMA_BOUNDARY, (data->len < 512) ? data->len : 512)); /* Set block count. */ WR2(slot, SDHCI_BLOCK_COUNT, (data->len + 511) / 512); if (__predict_false(sdhci_debug > 1)) slot_printf(slot, "Block size: %02x, count %lu\n", (unsigned int)SDHCI_MAKE_BLKSZ(DMA_BOUNDARY, (data->len < 512) ? data->len : 512), (unsigned long)(data->len + 511) / 512); } void sdhci_finish_data(struct sdhci_slot *slot) { struct mmc_data *data = slot->curcmd->data; size_t left; /* Interrupt aggregation: Restore command interrupt. * Auxiliary restore point for the case when data interrupt * happened first. */ if (!slot->cmd_done) { WR4(slot, SDHCI_SIGNAL_ENABLE, slot->intmask |= SDHCI_INT_RESPONSE); } /* Unload rest of data from DMA buffer. */ if (!slot->data_done && (slot->flags & SDHCI_USE_DMA) && slot->curcmd->data != NULL) { if (data->flags & MMC_DATA_READ) { left = data->len - slot->offset; bus_dmamap_sync(slot->dmatag, slot->dmamap, BUS_DMASYNC_POSTREAD); memcpy((u_char*)data->data + slot->offset, slot->dmamem, (left < DMA_BLOCK_SIZE) ? left : DMA_BLOCK_SIZE); } else bus_dmamap_sync(slot->dmatag, slot->dmamap, BUS_DMASYNC_POSTWRITE); } slot->data_done = 1; /* If there was error - reset the host. */ if (slot->curcmd->error) { if (slot->curcmd->error == MMC_ERR_BADCRC) slot->retune_req |= SDHCI_RETUNE_REQ_RESET; sdhci_reset(slot, SDHCI_RESET_CMD); sdhci_reset(slot, SDHCI_RESET_DATA); sdhci_start(slot); return; } /* If we already have command response - finish. */ if (slot->cmd_done) sdhci_start(slot); } #ifdef MMCCAM static void sdhci_start(struct sdhci_slot *slot) { union ccb *ccb; ccb = slot->ccb; if (ccb == NULL) return; struct ccb_mmcio *mmcio; mmcio = &ccb->mmcio; if (!(slot->flags & CMD_STARTED)) { slot->flags |= CMD_STARTED; sdhci_start_command(slot, &mmcio->cmd); return; } /* * Old stack doesn't use this! * Enabling this code causes significant performance degradation * and IRQ storms on BBB, Wandboard behaves fine. * Not using this code does no harm... if (!(slot->flags & STOP_STARTED) && mmcio->stop.opcode != 0) { slot->flags |= STOP_STARTED; sdhci_start_command(slot, &mmcio->stop); return; } */ if (__predict_false(sdhci_debug > 1)) slot_printf(slot, "result: %d\n", mmcio->cmd.error); if (mmcio->cmd.error == 0 && (slot->quirks & SDHCI_QUIRK_RESET_AFTER_REQUEST)) { sdhci_reset(slot, SDHCI_RESET_CMD); sdhci_reset(slot, SDHCI_RESET_DATA); } sdhci_req_done(slot); } #else static void sdhci_start(struct sdhci_slot *slot) { struct mmc_request *req; req = slot->req; if (req == NULL) return; if (!(slot->flags & CMD_STARTED)) { slot->flags |= CMD_STARTED; sdhci_start_command(slot, req->cmd); return; } if ((slot->quirks & SDHCI_QUIRK_BROKEN_AUTO_STOP) && !(slot->flags & STOP_STARTED) && req->stop) { slot->flags |= STOP_STARTED; sdhci_start_command(slot, req->stop); return; } if (__predict_false(sdhci_debug > 1)) slot_printf(slot, "result: %d\n", req->cmd->error); if (!req->cmd->error && ((slot->curcmd == req->stop && (slot->quirks & SDHCI_QUIRK_BROKEN_AUTO_STOP)) || (slot->quirks & SDHCI_QUIRK_RESET_AFTER_REQUEST))) { sdhci_reset(slot, SDHCI_RESET_CMD); sdhci_reset(slot, SDHCI_RESET_DATA); } sdhci_req_done(slot); } #endif int sdhci_generic_request(device_t brdev __unused, device_t reqdev, struct mmc_request *req) { struct sdhci_slot *slot = device_get_ivars(reqdev); SDHCI_LOCK(slot); if (slot->req != NULL) { SDHCI_UNLOCK(slot); return (EBUSY); } if (__predict_false(sdhci_debug > 1)) { slot_printf(slot, "CMD%u arg %#x flags %#x dlen %u dflags %#x\n", req->cmd->opcode, req->cmd->arg, req->cmd->flags, (req->cmd->data)?(u_int)req->cmd->data->len:0, (req->cmd->data)?req->cmd->data->flags:0); } slot->req = req; slot->flags = 0; sdhci_start(slot); SDHCI_UNLOCK(slot); if (dumping) { while (slot->req != NULL) { sdhci_generic_intr(slot); DELAY(10); } } return (0); } int sdhci_generic_get_ro(device_t brdev __unused, device_t reqdev) { struct sdhci_slot *slot = device_get_ivars(reqdev); uint32_t val; SDHCI_LOCK(slot); val = RD4(slot, SDHCI_PRESENT_STATE); SDHCI_UNLOCK(slot); return (!(val & SDHCI_WRITE_PROTECT)); } int sdhci_generic_acquire_host(device_t brdev __unused, device_t reqdev) { struct sdhci_slot *slot = device_get_ivars(reqdev); int err = 0; SDHCI_LOCK(slot); while (slot->bus_busy) msleep(slot, &slot->mtx, 0, "sdhciah", 0); slot->bus_busy++; /* Activate led. */ WR1(slot, SDHCI_HOST_CONTROL, slot->hostctrl |= SDHCI_CTRL_LED); SDHCI_UNLOCK(slot); return (err); } int sdhci_generic_release_host(device_t brdev __unused, device_t reqdev) { struct sdhci_slot *slot = device_get_ivars(reqdev); SDHCI_LOCK(slot); /* Deactivate led. */ WR1(slot, SDHCI_HOST_CONTROL, slot->hostctrl &= ~SDHCI_CTRL_LED); slot->bus_busy--; SDHCI_UNLOCK(slot); wakeup(slot); return (0); } static void sdhci_cmd_irq(struct sdhci_slot *slot, uint32_t intmask) { if (!slot->curcmd) { slot_printf(slot, "Got command interrupt 0x%08x, but " "there is no active command.\n", intmask); sdhci_dumpregs(slot); return; } if (intmask & SDHCI_INT_TIMEOUT) slot->curcmd->error = MMC_ERR_TIMEOUT; else if (intmask & SDHCI_INT_CRC) slot->curcmd->error = MMC_ERR_BADCRC; else if (intmask & (SDHCI_INT_END_BIT | SDHCI_INT_INDEX)) slot->curcmd->error = MMC_ERR_FIFO; sdhci_finish_command(slot); } static void sdhci_data_irq(struct sdhci_slot *slot, uint32_t intmask) { struct mmc_data *data; size_t left; if (!slot->curcmd) { slot_printf(slot, "Got data interrupt 0x%08x, but " "there is no active command.\n", intmask); sdhci_dumpregs(slot); return; } if (slot->curcmd->data == NULL && (slot->curcmd->flags & MMC_RSP_BUSY) == 0) { slot_printf(slot, "Got data interrupt 0x%08x, but " "there is no active data operation.\n", intmask); sdhci_dumpregs(slot); return; } if (intmask & SDHCI_INT_DATA_TIMEOUT) slot->curcmd->error = MMC_ERR_TIMEOUT; else if (intmask & (SDHCI_INT_DATA_CRC | SDHCI_INT_DATA_END_BIT)) slot->curcmd->error = MMC_ERR_BADCRC; if (slot->curcmd->data == NULL && (intmask & (SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL | SDHCI_INT_DMA_END))) { slot_printf(slot, "Got data interrupt 0x%08x, but " "there is busy-only command.\n", intmask); sdhci_dumpregs(slot); slot->curcmd->error = MMC_ERR_INVALID; } if (slot->curcmd->error) { /* No need to continue after any error. */ goto done; } /* Handle tuning completion interrupt. */ if (__predict_false((intmask & SDHCI_INT_DATA_AVAIL) && (slot->curcmd->opcode == MMC_SEND_TUNING_BLOCK || slot->curcmd->opcode == MMC_SEND_TUNING_BLOCK_HS200))) { slot->req->flags |= MMC_TUNE_DONE; sdhci_finish_command(slot); sdhci_finish_data(slot); return; } /* Handle PIO interrupt. */ if (intmask & (SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL)) { if ((slot->opt & SDHCI_PLATFORM_TRANSFER) && SDHCI_PLATFORM_WILL_HANDLE(slot->bus, slot)) { SDHCI_PLATFORM_START_TRANSFER(slot->bus, slot, &intmask); slot->flags |= PLATFORM_DATA_STARTED; } else sdhci_transfer_pio(slot); } /* Handle DMA border. */ if (intmask & SDHCI_INT_DMA_END) { data = slot->curcmd->data; /* Unload DMA buffer ... */ left = data->len - slot->offset; if (data->flags & MMC_DATA_READ) { bus_dmamap_sync(slot->dmatag, slot->dmamap, BUS_DMASYNC_POSTREAD); memcpy((u_char*)data->data + slot->offset, slot->dmamem, (left < DMA_BLOCK_SIZE) ? left : DMA_BLOCK_SIZE); } else { bus_dmamap_sync(slot->dmatag, slot->dmamap, BUS_DMASYNC_POSTWRITE); } /* ... and reload it again. */ slot->offset += DMA_BLOCK_SIZE; left = data->len - slot->offset; if (data->flags & MMC_DATA_READ) { bus_dmamap_sync(slot->dmatag, slot->dmamap, BUS_DMASYNC_PREREAD); } else { memcpy(slot->dmamem, (u_char*)data->data + slot->offset, (left < DMA_BLOCK_SIZE)? left : DMA_BLOCK_SIZE); bus_dmamap_sync(slot->dmatag, slot->dmamap, BUS_DMASYNC_PREWRITE); } /* Interrupt aggregation: Mask border interrupt * for the last page. */ if (left == DMA_BLOCK_SIZE) { slot->intmask &= ~SDHCI_INT_DMA_END; WR4(slot, SDHCI_SIGNAL_ENABLE, slot->intmask); } /* Restart DMA. */ WR4(slot, SDHCI_DMA_ADDRESS, slot->paddr); } /* We have got all data. */ if (intmask & SDHCI_INT_DATA_END) { if (slot->flags & PLATFORM_DATA_STARTED) { slot->flags &= ~PLATFORM_DATA_STARTED; SDHCI_PLATFORM_FINISH_TRANSFER(slot->bus, slot); } else sdhci_finish_data(slot); } done: if (slot->curcmd != NULL && slot->curcmd->error != 0) { if (slot->flags & PLATFORM_DATA_STARTED) { slot->flags &= ~PLATFORM_DATA_STARTED; SDHCI_PLATFORM_FINISH_TRANSFER(slot->bus, slot); } else sdhci_finish_data(slot); } } static void sdhci_acmd_irq(struct sdhci_slot *slot) { uint16_t err; err = RD4(slot, SDHCI_ACMD12_ERR); if (!slot->curcmd) { slot_printf(slot, "Got AutoCMD12 error 0x%04x, but " "there is no active command.\n", err); sdhci_dumpregs(slot); return; } slot_printf(slot, "Got AutoCMD12 error 0x%04x\n", err); sdhci_reset(slot, SDHCI_RESET_CMD); } void sdhci_generic_intr(struct sdhci_slot *slot) { uint32_t intmask, present; SDHCI_LOCK(slot); /* Read slot interrupt status. */ intmask = RD4(slot, SDHCI_INT_STATUS); if (intmask == 0 || intmask == 0xffffffff) { SDHCI_UNLOCK(slot); return; } if (__predict_false(sdhci_debug > 2)) slot_printf(slot, "Interrupt %#x\n", intmask); /* Handle tuning error interrupt. */ if (__predict_false(intmask & SDHCI_INT_TUNEERR)) { slot_printf(slot, "Tuning error indicated\n"); slot->retune_req |= SDHCI_RETUNE_REQ_RESET; if (slot->curcmd) { slot->curcmd->error = MMC_ERR_BADCRC; sdhci_finish_command(slot); } } /* Handle re-tuning interrupt. */ if (__predict_false(intmask & SDHCI_INT_RETUNE)) slot->retune_req |= SDHCI_RETUNE_REQ_NEEDED; /* Handle card presence interrupts. */ if (intmask & (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE)) { present = (intmask & SDHCI_INT_CARD_INSERT) != 0; slot->intmask &= ~(SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE); slot->intmask |= present ? SDHCI_INT_CARD_REMOVE : SDHCI_INT_CARD_INSERT; WR4(slot, SDHCI_INT_ENABLE, slot->intmask); WR4(slot, SDHCI_SIGNAL_ENABLE, slot->intmask); WR4(slot, SDHCI_INT_STATUS, intmask & (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE)); sdhci_handle_card_present_locked(slot, present); } /* Handle command interrupts. */ if (intmask & SDHCI_INT_CMD_MASK) { WR4(slot, SDHCI_INT_STATUS, intmask & SDHCI_INT_CMD_MASK); sdhci_cmd_irq(slot, intmask & SDHCI_INT_CMD_MASK); } /* Handle data interrupts. */ if (intmask & SDHCI_INT_DATA_MASK) { WR4(slot, SDHCI_INT_STATUS, intmask & SDHCI_INT_DATA_MASK); /* Don't call data_irq in case of errored command. */ if ((intmask & SDHCI_INT_CMD_ERROR_MASK) == 0) sdhci_data_irq(slot, intmask & SDHCI_INT_DATA_MASK); } /* Handle AutoCMD12 error interrupt. */ if (intmask & SDHCI_INT_ACMD12ERR) { WR4(slot, SDHCI_INT_STATUS, SDHCI_INT_ACMD12ERR); sdhci_acmd_irq(slot); } /* Handle bus power interrupt. */ if (intmask & SDHCI_INT_BUS_POWER) { WR4(slot, SDHCI_INT_STATUS, SDHCI_INT_BUS_POWER); slot_printf(slot, "Card is consuming too much power!\n"); } intmask &= ~(SDHCI_INT_ERROR | SDHCI_INT_TUNEERR | SDHCI_INT_RETUNE | SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE | SDHCI_INT_CMD_MASK | SDHCI_INT_DATA_MASK | SDHCI_INT_ACMD12ERR | SDHCI_INT_BUS_POWER); /* The rest is unknown. */ if (intmask) { WR4(slot, SDHCI_INT_STATUS, intmask); slot_printf(slot, "Unexpected interrupt 0x%08x.\n", intmask); sdhci_dumpregs(slot); } SDHCI_UNLOCK(slot); } int sdhci_generic_read_ivar(device_t bus, device_t child, int which, uintptr_t *result) { struct sdhci_slot *slot = device_get_ivars(child); switch (which) { default: return (EINVAL); case MMCBR_IVAR_BUS_MODE: *result = slot->host.ios.bus_mode; break; case MMCBR_IVAR_BUS_WIDTH: *result = slot->host.ios.bus_width; break; case MMCBR_IVAR_CHIP_SELECT: *result = slot->host.ios.chip_select; break; case MMCBR_IVAR_CLOCK: *result = slot->host.ios.clock; break; case MMCBR_IVAR_F_MIN: *result = slot->host.f_min; break; case MMCBR_IVAR_F_MAX: *result = slot->host.f_max; break; case MMCBR_IVAR_HOST_OCR: *result = slot->host.host_ocr; break; case MMCBR_IVAR_MODE: *result = slot->host.mode; break; case MMCBR_IVAR_OCR: *result = slot->host.ocr; break; case MMCBR_IVAR_POWER_MODE: *result = slot->host.ios.power_mode; break; case MMCBR_IVAR_VDD: *result = slot->host.ios.vdd; break; case MMCBR_IVAR_RETUNE_REQ: if (slot->opt & SDHCI_TUNING_ENABLED) { if (slot->retune_req & SDHCI_RETUNE_REQ_RESET) { *result = retune_req_reset; break; } if (slot->retune_req & SDHCI_RETUNE_REQ_NEEDED) { *result = retune_req_normal; break; } } *result = retune_req_none; break; case MMCBR_IVAR_VCCQ: *result = slot->host.ios.vccq; break; case MMCBR_IVAR_CAPS: *result = slot->host.caps; break; case MMCBR_IVAR_TIMING: *result = slot->host.ios.timing; break; case MMCBR_IVAR_MAX_DATA: /* * Re-tuning modes 1 and 2 restrict the maximum data length * per read/write command to 4 MiB. */ if (slot->opt & SDHCI_TUNING_ENABLED && (slot->retune_mode == SDHCI_RETUNE_MODE_1 || slot->retune_mode == SDHCI_RETUNE_MODE_2)) { *result = 4 * 1024 * 1024 / MMC_SECTOR_SIZE; break; } *result = 65535; break; case MMCBR_IVAR_MAX_BUSY_TIMEOUT: /* * Currently, sdhci_start_data() hardcodes 1 s for all CMDs. */ *result = 1000000; break; } return (0); } int sdhci_generic_write_ivar(device_t bus, device_t child, int which, uintptr_t value) { struct sdhci_slot *slot = device_get_ivars(child); uint32_t clock, max_clock; int i; if (sdhci_debug > 1) slot_printf(slot, "%s: var=%d\n", __func__, which); switch (which) { default: return (EINVAL); case MMCBR_IVAR_BUS_MODE: slot->host.ios.bus_mode = value; break; case MMCBR_IVAR_BUS_WIDTH: slot->host.ios.bus_width = value; break; case MMCBR_IVAR_CHIP_SELECT: slot->host.ios.chip_select = value; break; case MMCBR_IVAR_CLOCK: if (value > 0) { max_clock = slot->max_clk; clock = max_clock; if (slot->version < SDHCI_SPEC_300) { for (i = 0; i < SDHCI_200_MAX_DIVIDER; i <<= 1) { if (clock <= value) break; clock >>= 1; } } else { for (i = 0; i < SDHCI_300_MAX_DIVIDER; i += 2) { if (clock <= value) break; clock = max_clock / (i + 2); } } slot->host.ios.clock = clock; } else slot->host.ios.clock = 0; break; case MMCBR_IVAR_MODE: slot->host.mode = value; break; case MMCBR_IVAR_OCR: slot->host.ocr = value; break; case MMCBR_IVAR_POWER_MODE: slot->host.ios.power_mode = value; break; case MMCBR_IVAR_VDD: slot->host.ios.vdd = value; break; case MMCBR_IVAR_VCCQ: slot->host.ios.vccq = value; break; case MMCBR_IVAR_TIMING: slot->host.ios.timing = value; break; case MMCBR_IVAR_CAPS: case MMCBR_IVAR_HOST_OCR: case MMCBR_IVAR_F_MIN: case MMCBR_IVAR_F_MAX: case MMCBR_IVAR_MAX_DATA: case MMCBR_IVAR_RETUNE_REQ: return (EINVAL); } return (0); } #ifdef MMCCAM void -sdhci_cam_start_slot(struct sdhci_slot *slot) +sdhci_start_slot(struct sdhci_slot *slot) { if ((slot->devq = cam_simq_alloc(1)) == NULL) { goto fail; } mtx_init(&slot->sim_mtx, "sdhcisim", NULL, MTX_DEF); slot->sim = cam_sim_alloc(sdhci_cam_action, sdhci_cam_poll, "sdhci_slot", slot, device_get_unit(slot->bus), &slot->sim_mtx, 1, 1, slot->devq); if (slot->sim == NULL) { cam_simq_free(slot->devq); slot_printf(slot, "cannot allocate CAM SIM\n"); goto fail; } mtx_lock(&slot->sim_mtx); if (xpt_bus_register(slot->sim, slot->bus, 0) != 0) { slot_printf(slot, "cannot register SCSI pass-through bus\n"); cam_sim_free(slot->sim, FALSE); cam_simq_free(slot->devq); mtx_unlock(&slot->sim_mtx); goto fail; } mtx_unlock(&slot->sim_mtx); /* End CAM-specific init */ slot->card_present = 0; sdhci_card_task(slot, 0); return; fail: if (slot->sim != NULL) { mtx_lock(&slot->sim_mtx); xpt_bus_deregister(cam_sim_path(slot->sim)); cam_sim_free(slot->sim, FALSE); mtx_unlock(&slot->sim_mtx); } if (slot->devq != NULL) cam_simq_free(slot->devq); } static void sdhci_cam_handle_mmcio(struct cam_sim *sim, union ccb *ccb) { struct sdhci_slot *slot; slot = cam_sim_softc(sim); sdhci_cam_request(slot, ccb); } void sdhci_cam_action(struct cam_sim *sim, union ccb *ccb) { struct sdhci_slot *slot; slot = cam_sim_softc(sim); if (slot == NULL) { ccb->ccb_h.status = CAM_SEL_TIMEOUT; xpt_done(ccb); return; } mtx_assert(&slot->sim_mtx, MA_OWNED); switch (ccb->ccb_h.func_code) { case XPT_PATH_INQ: { struct ccb_pathinq *cpi; cpi = &ccb->cpi; cpi->version_num = 1; cpi->hba_inquiry = 0; cpi->target_sprt = 0; cpi->hba_misc = PIM_NOBUSRESET | PIM_SEQSCAN; cpi->hba_eng_cnt = 0; cpi->max_target = 0; cpi->max_lun = 0; cpi->initiator_id = 1; cpi->maxio = MAXPHYS; strncpy(cpi->sim_vid, "FreeBSD", SIM_IDLEN); strncpy(cpi->hba_vid, "Deglitch Networks", HBA_IDLEN); strncpy(cpi->dev_name, cam_sim_name(sim), DEV_IDLEN); cpi->unit_number = cam_sim_unit(sim); cpi->bus_id = cam_sim_bus(sim); cpi->base_transfer_speed = 100; /* XXX WTF? */ cpi->protocol = PROTO_MMCSD; cpi->protocol_version = SCSI_REV_0; cpi->transport = XPORT_MMCSD; cpi->transport_version = 0; cpi->ccb_h.status = CAM_REQ_CMP; break; } case XPT_GET_TRAN_SETTINGS: { struct ccb_trans_settings *cts = &ccb->cts; if (sdhci_debug > 1) slot_printf(slot, "Got XPT_GET_TRAN_SETTINGS\n"); cts->protocol = PROTO_MMCSD; cts->protocol_version = 1; cts->transport = XPORT_MMCSD; cts->transport_version = 1; cts->xport_specific.valid = 0; cts->proto_specific.mmc.host_ocr = slot->host.host_ocr; cts->proto_specific.mmc.host_f_min = slot->host.f_min; cts->proto_specific.mmc.host_f_max = slot->host.f_max; cts->proto_specific.mmc.host_caps = slot->host.caps; memcpy(&cts->proto_specific.mmc.ios, &slot->host.ios, sizeof(struct mmc_ios)); ccb->ccb_h.status = CAM_REQ_CMP; break; } case XPT_SET_TRAN_SETTINGS: { if (sdhci_debug > 1) slot_printf(slot, "Got XPT_SET_TRAN_SETTINGS\n"); sdhci_cam_settran_settings(slot, ccb); ccb->ccb_h.status = CAM_REQ_CMP; break; } case XPT_RESET_BUS: if (sdhci_debug > 1) slot_printf(slot, "Got XPT_RESET_BUS, ACK it...\n"); ccb->ccb_h.status = CAM_REQ_CMP; break; case XPT_MMC_IO: /* * Here is the HW-dependent part of * sending the command to the underlying h/w * At some point in the future an interrupt comes. * Then the request will be marked as completed. */ if (__predict_false(sdhci_debug > 1)) slot_printf(slot, "Got XPT_MMC_IO\n"); ccb->ccb_h.status = CAM_REQ_INPROG; sdhci_cam_handle_mmcio(sim, ccb); return; /* NOTREACHED */ break; default: ccb->ccb_h.status = CAM_REQ_INVALID; break; } xpt_done(ccb); return; } void sdhci_cam_poll(struct cam_sim *sim) { return; } int sdhci_cam_get_possible_host_clock(struct sdhci_slot *slot, int proposed_clock) { int max_clock, clock, i; if (proposed_clock == 0) return 0; max_clock = slot->max_clk; clock = max_clock; if (slot->version < SDHCI_SPEC_300) { for (i = 0; i < SDHCI_200_MAX_DIVIDER; i <<= 1) { if (clock <= proposed_clock) break; clock >>= 1; } } else { for (i = 0; i < SDHCI_300_MAX_DIVIDER; i += 2) { if (clock <= proposed_clock) break; clock = max_clock / (i + 2); } } return clock; } int sdhci_cam_settran_settings(struct sdhci_slot *slot, union ccb *ccb) { struct mmc_ios *ios; struct mmc_ios *new_ios; struct ccb_trans_settings_mmc *cts; ios = &slot->host.ios; cts = &ccb->cts.proto_specific.mmc; new_ios = &cts->ios; /* Update only requested fields */ if (cts->ios_valid & MMC_CLK) { ios->clock = sdhci_cam_get_possible_host_clock(slot, new_ios->clock); slot_printf(slot, "Clock => %d\n", ios->clock); } if (cts->ios_valid & MMC_VDD) { ios->vdd = new_ios->vdd; slot_printf(slot, "VDD => %d\n", ios->vdd); } if (cts->ios_valid & MMC_CS) { ios->chip_select = new_ios->chip_select; slot_printf(slot, "CS => %d\n", ios->chip_select); } if (cts->ios_valid & MMC_BW) { ios->bus_width = new_ios->bus_width; slot_printf(slot, "Bus width => %d\n", ios->bus_width); } if (cts->ios_valid & MMC_PM) { ios->power_mode = new_ios->power_mode; slot_printf(slot, "Power mode => %d\n", ios->power_mode); } if (cts->ios_valid & MMC_BT) { ios->timing = new_ios->timing; slot_printf(slot, "Timing => %d\n", ios->timing); } if (cts->ios_valid & MMC_BM) { ios->bus_mode = new_ios->bus_mode; slot_printf(slot, "Bus mode => %d\n", ios->bus_mode); } /* XXX Provide a way to call a chip-specific IOS update, required for TI */ return (sdhci_cam_update_ios(slot)); } int sdhci_cam_update_ios(struct sdhci_slot *slot) { struct mmc_ios *ios = &slot->host.ios; slot_printf(slot, "%s: power_mode=%d, clk=%d, bus_width=%d, timing=%d\n", __func__, ios->power_mode, ios->clock, ios->bus_width, ios->timing); SDHCI_LOCK(slot); /* Do full reset on bus power down to clear from any state. */ if (ios->power_mode == power_off) { WR4(slot, SDHCI_SIGNAL_ENABLE, 0); sdhci_init(slot); } /* Configure the bus. */ sdhci_set_clock(slot, ios->clock); sdhci_set_power(slot, (ios->power_mode == power_off) ? 0 : ios->vdd); if (ios->bus_width == bus_width_8) { slot->hostctrl |= SDHCI_CTRL_8BITBUS; slot->hostctrl &= ~SDHCI_CTRL_4BITBUS; } else if (ios->bus_width == bus_width_4) { slot->hostctrl &= ~SDHCI_CTRL_8BITBUS; slot->hostctrl |= SDHCI_CTRL_4BITBUS; } else if (ios->bus_width == bus_width_1) { slot->hostctrl &= ~SDHCI_CTRL_8BITBUS; slot->hostctrl &= ~SDHCI_CTRL_4BITBUS; } else { panic("Invalid bus width: %d", ios->bus_width); } if (ios->timing == bus_timing_hs && !(slot->quirks & SDHCI_QUIRK_DONT_SET_HISPD_BIT)) slot->hostctrl |= SDHCI_CTRL_HISPD; else slot->hostctrl &= ~SDHCI_CTRL_HISPD; WR1(slot, SDHCI_HOST_CONTROL, slot->hostctrl); /* Some controllers like reset after bus changes. */ if(slot->quirks & SDHCI_QUIRK_RESET_ON_IOS) sdhci_reset(slot, SDHCI_RESET_CMD | SDHCI_RESET_DATA); SDHCI_UNLOCK(slot); return (0); } int sdhci_cam_request(struct sdhci_slot *slot, union ccb *ccb) { struct ccb_mmcio *mmcio; mmcio = &ccb->mmcio; SDHCI_LOCK(slot); /* if (slot->req != NULL) { SDHCI_UNLOCK(slot); return (EBUSY); } */ if (__predict_false(sdhci_debug > 1)) { slot_printf(slot, "CMD%u arg %#x flags %#x dlen %u dflags %#x\n", mmcio->cmd.opcode, mmcio->cmd.arg, mmcio->cmd.flags, mmcio->cmd.data != NULL ? (unsigned int) mmcio->cmd.data->len : 0, mmcio->cmd.data != NULL ? mmcio->cmd.data->flags: 0); } if (mmcio->cmd.data != NULL) { if (mmcio->cmd.data->len == 0 || mmcio->cmd.data->flags == 0) panic("data->len = %d, data->flags = %d -- something is b0rked", (int)mmcio->cmd.data->len, mmcio->cmd.data->flags); } slot->ccb = ccb; slot->flags = 0; sdhci_start(slot); SDHCI_UNLOCK(slot); if (dumping) { while (slot->ccb != NULL) { sdhci_generic_intr(slot); DELAY(10); } } return (0); } #endif /* MMCCAM */ MODULE_VERSION(sdhci, 1); Index: head/sys/dev/sdhci/sdhci.h =================================================================== --- head/sys/dev/sdhci/sdhci.h (revision 323965) +++ head/sys/dev/sdhci/sdhci.h (revision 323966) @@ -1,438 +1,433 @@ /*- * Copyright (c) 2008 Alexander Motin * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * * $FreeBSD$ */ #ifndef __SDHCI_H__ #define __SDHCI_H__ #include "opt_mmccam.h" #define DMA_BLOCK_SIZE 4096 #define DMA_BOUNDARY 0 /* DMA reload every 4K */ /* Controller doesn't honor resets unless we touch the clock register */ #define SDHCI_QUIRK_CLOCK_BEFORE_RESET (1 << 0) /* Controller really supports DMA */ #define SDHCI_QUIRK_FORCE_DMA (1 << 1) /* Controller has unusable DMA engine */ #define SDHCI_QUIRK_BROKEN_DMA (1 << 2) /* Controller doesn't like to be reset when there is no card inserted. */ #define SDHCI_QUIRK_NO_CARD_NO_RESET (1 << 3) /* Controller has flaky internal state so reset it on each ios change */ #define SDHCI_QUIRK_RESET_ON_IOS (1 << 4) /* Controller can only DMA chunk sizes that are a multiple of 32 bits */ #define SDHCI_QUIRK_32BIT_DMA_SIZE (1 << 5) /* Controller needs to be reset after each request to stay stable */ #define SDHCI_QUIRK_RESET_AFTER_REQUEST (1 << 6) /* Controller has an off-by-one issue with timeout value */ #define SDHCI_QUIRK_INCR_TIMEOUT_CONTROL (1 << 7) /* Controller has broken read timings */ #define SDHCI_QUIRK_BROKEN_TIMINGS (1 << 8) /* Controller needs lowered frequency */ #define SDHCI_QUIRK_LOWER_FREQUENCY (1 << 9) /* Data timeout is invalid, should use SD clock */ #define SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK (1 << 10) /* Timeout value is invalid, should be overriden */ #define SDHCI_QUIRK_BROKEN_TIMEOUT_VAL (1 << 11) /* SDHCI_CAPABILITIES is invalid */ #define SDHCI_QUIRK_MISSING_CAPS (1 << 12) /* Hardware shifts the 136-bit response, don't do it in software. */ #define SDHCI_QUIRK_DONT_SHIFT_RESPONSE (1 << 13) /* Wait to see reset bit asserted before waiting for de-asserted */ #define SDHCI_QUIRK_WAITFOR_RESET_ASSERTED (1 << 14) /* Leave controller in standard mode when putting card in HS mode. */ #define SDHCI_QUIRK_DONT_SET_HISPD_BIT (1 << 15) /* Alternate clock source is required when supplying a 400 KHz clock. */ #define SDHCI_QUIRK_BCM577XX_400KHZ_CLKSRC (1 << 16) /* Card insert/remove interrupts don't work, polling required. */ #define SDHCI_QUIRK_POLL_CARD_PRESENT (1 << 17) /* All controller slots are non-removable. */ #define SDHCI_QUIRK_ALL_SLOTS_NON_REMOVABLE (1 << 18) /* Issue custom Intel controller reset sequence after power-up. */ #define SDHCI_QUIRK_INTEL_POWER_UP_RESET (1 << 19) /* Data timeout is invalid, use 1 MHz clock instead. */ #define SDHCI_QUIRK_DATA_TIMEOUT_1MHZ (1 << 20) /* Controller doesn't allow access boot partitions. */ #define SDHCI_QUIRK_BOOT_NOACC (1 << 21) /* Controller waits for busy responses. */ #define SDHCI_QUIRK_WAIT_WHILE_BUSY (1 << 22) /* Controller supports eMMC DDR52 mode. */ #define SDHCI_QUIRK_MMC_DDR52 (1 << 23) /* Controller support for UHS DDR50 mode is broken. */ #define SDHCI_QUIRK_BROKEN_UHS_DDR50 (1 << 24) /* Controller support for eMMC HS200 mode is broken. */ #define SDHCI_QUIRK_BROKEN_MMC_HS200 (1 << 25) /* Controller reports support for eMMC HS400 mode as SDHCI_CAN_MMC_HS400. */ #define SDHCI_QUIRK_CAPS_BIT63_FOR_MMC_HS400 (1 << 26) /* Controller support for SDHCI_CTRL2_PRESET_VALUE is broken. */ #define SDHCI_QUIRK_PRESET_VALUE_BROKEN (1 << 27) /* Controller does not support or the support for ACMD12 is broken. */ #define SDHCI_QUIRK_BROKEN_AUTO_STOP (1 << 28) /* * Controller registers */ #define SDHCI_DMA_ADDRESS 0x00 #define SDHCI_BLOCK_SIZE 0x04 #define SDHCI_MAKE_BLKSZ(dma, blksz) (((dma & 0x7) << 12) | (blksz & 0xFFF)) #define SDHCI_BLOCK_COUNT 0x06 #define SDHCI_ARGUMENT 0x08 #define SDHCI_TRANSFER_MODE 0x0C #define SDHCI_TRNS_DMA 0x01 #define SDHCI_TRNS_BLK_CNT_EN 0x02 #define SDHCI_TRNS_ACMD12 0x04 #define SDHCI_TRNS_READ 0x10 #define SDHCI_TRNS_MULTI 0x20 #define SDHCI_COMMAND_FLAGS 0x0E #define SDHCI_CMD_RESP_NONE 0x00 #define SDHCI_CMD_RESP_LONG 0x01 #define SDHCI_CMD_RESP_SHORT 0x02 #define SDHCI_CMD_RESP_SHORT_BUSY 0x03 #define SDHCI_CMD_RESP_MASK 0x03 #define SDHCI_CMD_CRC 0x08 #define SDHCI_CMD_INDEX 0x10 #define SDHCI_CMD_DATA 0x20 #define SDHCI_CMD_TYPE_NORMAL 0x00 #define SDHCI_CMD_TYPE_SUSPEND 0x40 #define SDHCI_CMD_TYPE_RESUME 0x80 #define SDHCI_CMD_TYPE_ABORT 0xc0 #define SDHCI_CMD_TYPE_MASK 0xc0 #define SDHCI_COMMAND 0x0F #define SDHCI_RESPONSE 0x10 #define SDHCI_BUFFER 0x20 #define SDHCI_PRESENT_STATE 0x24 #define SDHCI_CMD_INHIBIT 0x00000001 #define SDHCI_DAT_INHIBIT 0x00000002 #define SDHCI_DAT_ACTIVE 0x00000004 #define SDHCI_RETUNE_REQUEST 0x00000008 #define SDHCI_DOING_WRITE 0x00000100 #define SDHCI_DOING_READ 0x00000200 #define SDHCI_SPACE_AVAILABLE 0x00000400 #define SDHCI_DATA_AVAILABLE 0x00000800 #define SDHCI_CARD_PRESENT 0x00010000 #define SDHCI_CARD_STABLE 0x00020000 #define SDHCI_CARD_PIN 0x00040000 #define SDHCI_WRITE_PROTECT 0x00080000 #define SDHCI_STATE_DAT_MASK 0x00f00000 #define SDHCI_STATE_CMD 0x01000000 #define SDHCI_HOST_CONTROL 0x28 #define SDHCI_CTRL_LED 0x01 #define SDHCI_CTRL_4BITBUS 0x02 #define SDHCI_CTRL_HISPD 0x04 #define SDHCI_CTRL_SDMA 0x08 #define SDHCI_CTRL_ADMA2 0x10 #define SDHCI_CTRL_ADMA264 0x18 #define SDHCI_CTRL_DMA_MASK 0x18 #define SDHCI_CTRL_8BITBUS 0x20 #define SDHCI_CTRL_CARD_DET 0x40 #define SDHCI_CTRL_FORCE_CARD 0x80 #define SDHCI_POWER_CONTROL 0x29 #define SDHCI_POWER_ON 0x01 #define SDHCI_POWER_180 0x0A #define SDHCI_POWER_300 0x0C #define SDHCI_POWER_330 0x0E #define SDHCI_BLOCK_GAP_CONTROL 0x2A #define SDHCI_WAKE_UP_CONTROL 0x2B #define SDHCI_CLOCK_CONTROL 0x2C #define SDHCI_DIVIDER_MASK 0xff #define SDHCI_DIVIDER_MASK_LEN 8 #define SDHCI_DIVIDER_SHIFT 8 #define SDHCI_DIVIDER_HI_MASK 3 #define SDHCI_DIVIDER_HI_SHIFT 6 #define SDHCI_CLOCK_CARD_EN 0x0004 #define SDHCI_CLOCK_INT_STABLE 0x0002 #define SDHCI_CLOCK_INT_EN 0x0001 #define SDHCI_DIVIDERS_MASK \ ((SDHCI_DIVIDER_MASK << SDHCI_DIVIDER_SHIFT) | \ (SDHCI_DIVIDER_HI_MASK << SDHCI_DIVIDER_HI_SHIFT)) #define SDHCI_TIMEOUT_CONTROL 0x2E #define SDHCI_SOFTWARE_RESET 0x2F #define SDHCI_RESET_ALL 0x01 #define SDHCI_RESET_CMD 0x02 #define SDHCI_RESET_DATA 0x04 #define SDHCI_INT_STATUS 0x30 #define SDHCI_INT_ENABLE 0x34 #define SDHCI_SIGNAL_ENABLE 0x38 #define SDHCI_INT_RESPONSE 0x00000001 #define SDHCI_INT_DATA_END 0x00000002 #define SDHCI_INT_BLOCK_GAP 0x00000004 #define SDHCI_INT_DMA_END 0x00000008 #define SDHCI_INT_SPACE_AVAIL 0x00000010 #define SDHCI_INT_DATA_AVAIL 0x00000020 #define SDHCI_INT_CARD_INSERT 0x00000040 #define SDHCI_INT_CARD_REMOVE 0x00000080 #define SDHCI_INT_CARD_INT 0x00000100 #define SDHCI_INT_INT_A 0x00000200 #define SDHCI_INT_INT_B 0x00000400 #define SDHCI_INT_INT_C 0x00000800 #define SDHCI_INT_RETUNE 0x00001000 #define SDHCI_INT_ERROR 0x00008000 #define SDHCI_INT_TIMEOUT 0x00010000 #define SDHCI_INT_CRC 0x00020000 #define SDHCI_INT_END_BIT 0x00040000 #define SDHCI_INT_INDEX 0x00080000 #define SDHCI_INT_DATA_TIMEOUT 0x00100000 #define SDHCI_INT_DATA_CRC 0x00200000 #define SDHCI_INT_DATA_END_BIT 0x00400000 #define SDHCI_INT_BUS_POWER 0x00800000 #define SDHCI_INT_ACMD12ERR 0x01000000 #define SDHCI_INT_ADMAERR 0x02000000 #define SDHCI_INT_TUNEERR 0x04000000 #define SDHCI_INT_NORMAL_MASK 0x00007FFF #define SDHCI_INT_ERROR_MASK 0xFFFF8000 #define SDHCI_INT_CMD_ERROR_MASK (SDHCI_INT_TIMEOUT | \ SDHCI_INT_CRC | SDHCI_INT_END_BIT | SDHCI_INT_INDEX) #define SDHCI_INT_CMD_MASK (SDHCI_INT_RESPONSE | SDHCI_INT_CMD_ERROR_MASK) #define SDHCI_INT_DATA_MASK (SDHCI_INT_DATA_END | SDHCI_INT_DMA_END | \ SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL | \ SDHCI_INT_DATA_TIMEOUT | SDHCI_INT_DATA_CRC | \ SDHCI_INT_DATA_END_BIT) #define SDHCI_ACMD12_ERR 0x3C #define SDHCI_HOST_CONTROL2 0x3E #define SDHCI_CTRL2_PRESET_VALUE 0x8000 #define SDHCI_CTRL2_ASYNC_INTR 0x4000 #define SDHCI_CTRL2_64BIT_ENABLE 0x2000 #define SDHCI_CTRL2_HOST_V4_ENABLE 0x1000 #define SDHCI_CTRL2_CMD23_ENABLE 0x0800 #define SDHCI_CTRL2_ADMA2_LENGTH_MODE 0x0400 #define SDHCI_CTRL2_UHS2_IFACE_ENABLE 0x0100 #define SDHCI_CTRL2_SAMPLING_CLOCK 0x0080 #define SDHCI_CTRL2_EXEC_TUNING 0x0040 #define SDHCI_CTRL2_DRIVER_TYPE_MASK 0x0030 #define SDHCI_CTRL2_DRIVER_TYPE_B 0x0000 #define SDHCI_CTRL2_DRIVER_TYPE_A 0x0010 #define SDHCI_CTRL2_DRIVER_TYPE_C 0x0020 #define SDHCI_CTRL2_DRIVER_TYPE_D 0x0030 #define SDHCI_CTRL2_S18_ENABLE 0x0008 #define SDHCI_CTRL2_UHS_MASK 0x0007 #define SDHCI_CTRL2_UHS_SDR12 0x0000 #define SDHCI_CTRL2_UHS_SDR25 0x0001 #define SDHCI_CTRL2_UHS_SDR50 0x0002 #define SDHCI_CTRL2_UHS_SDR104 0x0003 #define SDHCI_CTRL2_UHS_DDR50 0x0004 #define SDHCI_CTRL2_MMC_HS400 0x0005 /* non-standard */ #define SDHCI_CAPABILITIES 0x40 #define SDHCI_TIMEOUT_CLK_MASK 0x0000003F #define SDHCI_TIMEOUT_CLK_SHIFT 0 #define SDHCI_TIMEOUT_CLK_UNIT 0x00000080 #define SDHCI_CLOCK_BASE_MASK 0x00003F00 #define SDHCI_CLOCK_V3_BASE_MASK 0x0000FF00 #define SDHCI_CLOCK_BASE_SHIFT 8 #define SDHCI_MAX_BLOCK_MASK 0x00030000 #define SDHCI_MAX_BLOCK_SHIFT 16 #define SDHCI_CAN_DO_8BITBUS 0x00040000 #define SDHCI_CAN_DO_ADMA2 0x00080000 #define SDHCI_CAN_DO_HISPD 0x00200000 #define SDHCI_CAN_DO_DMA 0x00400000 #define SDHCI_CAN_DO_SUSPEND 0x00800000 #define SDHCI_CAN_VDD_330 0x01000000 #define SDHCI_CAN_VDD_300 0x02000000 #define SDHCI_CAN_VDD_180 0x04000000 #define SDHCI_CAN_DO_64BIT 0x10000000 #define SDHCI_CAN_ASYNC_INTR 0x20000000 #define SDHCI_SLOTTYPE_MASK 0xC0000000 #define SDHCI_SLOTTYPE_REMOVABLE 0x00000000 #define SDHCI_SLOTTYPE_EMBEDDED 0x40000000 #define SDHCI_SLOTTYPE_SHARED 0x80000000 #define SDHCI_CAPABILITIES2 0x44 #define SDHCI_CAN_SDR50 0x00000001 #define SDHCI_CAN_SDR104 0x00000002 #define SDHCI_CAN_DDR50 0x00000004 #define SDHCI_CAN_DRIVE_TYPE_A 0x00000010 #define SDHCI_CAN_DRIVE_TYPE_C 0x00000020 #define SDHCI_CAN_DRIVE_TYPE_D 0x00000040 #define SDHCI_RETUNE_CNT_MASK 0x00000F00 #define SDHCI_RETUNE_CNT_SHIFT 8 #define SDHCI_TUNE_SDR50 0x00002000 #define SDHCI_RETUNE_MODES_MASK 0x0000C000 #define SDHCI_RETUNE_MODES_SHIFT 14 #define SDHCI_CLOCK_MULT_MASK 0x00FF0000 #define SDHCI_CLOCK_MULT_SHIFT 16 #define SDHCI_CAN_MMC_HS400 0x80000000 /* non-standard */ #define SDHCI_MAX_CURRENT 0x48 #define SDHCI_FORCE_AUTO_EVENT 0x50 #define SDHCI_FORCE_INTR_EVENT 0x52 #define SDHCI_ADMA_ERR 0x54 #define SDHCI_ADMA_ERR_LENGTH 0x04 #define SDHCI_ADMA_ERR_STATE_MASK 0x03 #define SDHCI_ADMA_ERR_STATE_STOP 0x00 #define SDHCI_ADMA_ERR_STATE_FDS 0x01 #define SDHCI_ADMA_ERR_STATE_TFR 0x03 #define SDHCI_ADMA_ADDRESS_LO 0x58 #define SDHCI_ADMA_ADDRESS_HI 0x5C #define SDHCI_PRESET_VALUE 0x60 #define SDHCI_SHARED_BUS_CTRL 0xE0 #define SDHCI_SLOT_INT_STATUS 0xFC #define SDHCI_HOST_VERSION 0xFE #define SDHCI_VENDOR_VER_MASK 0xFF00 #define SDHCI_VENDOR_VER_SHIFT 8 #define SDHCI_SPEC_VER_MASK 0x00FF #define SDHCI_SPEC_VER_SHIFT 0 #define SDHCI_SPEC_100 0 #define SDHCI_SPEC_200 1 #define SDHCI_SPEC_300 2 #define SDHCI_SPEC_400 3 #define SDHCI_SPEC_410 4 #define SDHCI_SPEC_420 5 SYSCTL_DECL(_hw_sdhci); extern u_int sdhci_quirk_clear; extern u_int sdhci_quirk_set; struct sdhci_slot { struct mtx mtx; /* Slot mutex */ u_int quirks; /* Chip specific quirks */ u_int caps; /* Override SDHCI_CAPABILITIES */ u_int caps2; /* Override SDHCI_CAPABILITIES2 */ device_t bus; /* Bus device */ device_t dev; /* Slot device */ u_char num; /* Slot number */ u_char opt; /* Slot options */ #define SDHCI_HAVE_DMA 0x01 #define SDHCI_PLATFORM_TRANSFER 0x02 #define SDHCI_NON_REMOVABLE 0x04 #define SDHCI_TUNING_SUPPORTED 0x08 #define SDHCI_TUNING_ENABLED 0x10 #define SDHCI_SDR50_NEEDS_TUNING 0x20 #define SDHCI_SLOT_EMBEDDED 0x40 u_char version; int timeout; /* Transfer timeout */ uint32_t max_clk; /* Max possible freq */ uint32_t timeout_clk; /* Timeout freq */ bus_dma_tag_t dmatag; bus_dmamap_t dmamap; u_char *dmamem; bus_addr_t paddr; /* DMA buffer address */ struct task card_task; /* Card presence check task */ struct timeout_task card_delayed_task;/* Card insert delayed task */ struct callout card_poll_callout;/* Card present polling callout */ struct callout timeout_callout;/* Card command/data response timeout */ struct callout retune_callout; /* Re-tuning mode 1 callout */ struct mmc_host host; /* Host parameters */ struct mmc_request *req; /* Current request */ struct mmc_command *curcmd; /* Current command of current request */ struct mmc_request *tune_req; /* Tuning request */ struct mmc_command *tune_cmd; /* Tuning command of tuning request */ struct mmc_data *tune_data; /* Tuning data of tuning command */ uint32_t retune_ticks; /* Re-tuning callout ticks [hz] */ uint32_t intmask; /* Current interrupt mask */ uint32_t clock; /* Current clock freq. */ size_t offset; /* Data buffer offset */ uint8_t hostctrl; /* Current host control register */ uint8_t retune_count; /* Controller re-tuning count [s] */ uint8_t retune_mode; /* Controller re-tuning mode */ #define SDHCI_RETUNE_MODE_1 0x00 #define SDHCI_RETUNE_MODE_2 0x01 #define SDHCI_RETUNE_MODE_3 0x02 uint8_t retune_req; /* Re-tuning request status */ #define SDHCI_RETUNE_REQ_NEEDED 0x01 /* Re-tuning w/o circuit reset needed */ #define SDHCI_RETUNE_REQ_RESET 0x02 /* Re-tuning w/ circuit reset needed */ u_char power; /* Current power */ u_char bus_busy; /* Bus busy status */ u_char cmd_done; /* CMD command part done flag */ u_char data_done; /* DAT command part done flag */ u_char flags; /* Request execution flags */ #define CMD_STARTED 1 #define STOP_STARTED 2 #define SDHCI_USE_DMA 4 /* Use DMA for this req. */ #define PLATFORM_DATA_STARTED 8 /* Data xfer is handled by platform */ #ifdef MMCCAM /* CAM stuff */ union ccb *ccb; struct cam_devq *devq; struct cam_sim *sim; struct mtx sim_mtx; u_char card_present; /* XXX Maybe derive this from elsewhere? */ #endif }; int sdhci_generic_read_ivar(device_t bus, device_t child, int which, uintptr_t *result); int sdhci_generic_write_ivar(device_t bus, device_t child, int which, uintptr_t value); int sdhci_init_slot(device_t dev, struct sdhci_slot *slot, int num); void sdhci_start_slot(struct sdhci_slot *slot); /* performs generic clean-up for platform transfers */ void sdhci_finish_data(struct sdhci_slot *slot); int sdhci_cleanup_slot(struct sdhci_slot *slot); int sdhci_generic_suspend(struct sdhci_slot *slot); int sdhci_generic_resume(struct sdhci_slot *slot); int sdhci_generic_update_ios(device_t brdev, device_t reqdev); int sdhci_generic_tune(device_t brdev, device_t reqdev, bool hs400); int sdhci_generic_switch_vccq(device_t brdev, device_t reqdev); int sdhci_generic_retune(device_t brdev, device_t reqdev, bool reset); int sdhci_generic_request(device_t brdev, device_t reqdev, struct mmc_request *req); int sdhci_generic_get_ro(device_t brdev, device_t reqdev); int sdhci_generic_acquire_host(device_t brdev, device_t reqdev); int sdhci_generic_release_host(device_t brdev, device_t reqdev); void sdhci_generic_intr(struct sdhci_slot *slot); uint32_t sdhci_generic_min_freq(device_t brdev, struct sdhci_slot *slot); bool sdhci_generic_get_card_present(device_t brdev, struct sdhci_slot *slot); void sdhci_generic_set_uhs_timing(device_t brdev, struct sdhci_slot *slot); void sdhci_handle_card_present(struct sdhci_slot *slot, bool is_present); -#ifdef MMCCAM -/* CAM-related */ -void sdhci_cam_start_slot(struct sdhci_slot *slot); -#endif - #endif /* __SDHCI_H__ */ Index: head/sys/dev/sdhci/sdhci_pci.c =================================================================== --- head/sys/dev/sdhci/sdhci_pci.c (revision 323965) +++ head/sys/dev/sdhci/sdhci_pci.c (revision 323966) @@ -1,529 +1,525 @@ /*- * Copyright (c) 2008 Alexander Motin * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ #include __FBSDID("$FreeBSD$"); #include "opt_mmccam.h" #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include "mmcbr_if.h" #include "sdhci_if.h" /* * PCI registers */ #define PCI_SDHCI_IFPIO 0x00 #define PCI_SDHCI_IFDMA 0x01 #define PCI_SDHCI_IFVENDOR 0x02 #define PCI_SLOT_INFO 0x40 /* 8 bits */ #define PCI_SLOT_INFO_SLOTS(x) (((x >> 4) & 7) + 1) #define PCI_SLOT_INFO_FIRST_BAR(x) ((x) & 7) /* * RICOH specific PCI registers */ #define SDHC_PCI_MODE_KEY 0xf9 #define SDHC_PCI_MODE 0x150 #define SDHC_PCI_MODE_SD20 0x10 #define SDHC_PCI_BASE_FREQ_KEY 0xfc #define SDHC_PCI_BASE_FREQ 0xe1 static const struct sdhci_device { uint32_t model; uint16_t subvendor; const char *desc; u_int quirks; } sdhci_devices[] = { { 0x08221180, 0xffff, "RICOH R5C822 SD", SDHCI_QUIRK_FORCE_DMA }, { 0xe8221180, 0xffff, "RICOH R5CE822 SD", SDHCI_QUIRK_FORCE_DMA | SDHCI_QUIRK_LOWER_FREQUENCY }, { 0xe8231180, 0xffff, "RICOH R5CE823 SD", SDHCI_QUIRK_LOWER_FREQUENCY }, { 0x8034104c, 0xffff, "TI XX21/XX11 SD", SDHCI_QUIRK_FORCE_DMA }, { 0x05501524, 0xffff, "ENE CB712 SD", SDHCI_QUIRK_BROKEN_TIMINGS }, { 0x05511524, 0xffff, "ENE CB712 SD 2", SDHCI_QUIRK_BROKEN_TIMINGS }, { 0x07501524, 0xffff, "ENE CB714 SD", SDHCI_QUIRK_RESET_ON_IOS | SDHCI_QUIRK_BROKEN_TIMINGS }, { 0x07511524, 0xffff, "ENE CB714 SD 2", SDHCI_QUIRK_RESET_ON_IOS | SDHCI_QUIRK_BROKEN_TIMINGS }, { 0x410111ab, 0xffff, "Marvell CaFe SD", SDHCI_QUIRK_INCR_TIMEOUT_CONTROL }, { 0x2381197B, 0xffff, "JMicron JMB38X SD", SDHCI_QUIRK_32BIT_DMA_SIZE | SDHCI_QUIRK_RESET_AFTER_REQUEST }, { 0x16bc14e4, 0xffff, "Broadcom BCM577xx SDXC/MMC Card Reader", SDHCI_QUIRK_BCM577XX_400KHZ_CLKSRC }, { 0x0f148086, 0xffff, "Intel Bay Trail eMMC 4.5 Controller", SDHCI_QUIRK_INTEL_POWER_UP_RESET | SDHCI_QUIRK_WAIT_WHILE_BUSY | SDHCI_QUIRK_MMC_DDR52 | SDHCI_QUIRK_CAPS_BIT63_FOR_MMC_HS400 | SDHCI_QUIRK_PRESET_VALUE_BROKEN}, { 0x0f158086, 0xffff, "Intel Bay Trail SDXC Controller", SDHCI_QUIRK_WAIT_WHILE_BUSY | SDHCI_QUIRK_PRESET_VALUE_BROKEN }, { 0x0f508086, 0xffff, "Intel Bay Trail eMMC 4.5 Controller", SDHCI_QUIRK_INTEL_POWER_UP_RESET | SDHCI_QUIRK_WAIT_WHILE_BUSY | SDHCI_QUIRK_MMC_DDR52 | SDHCI_QUIRK_CAPS_BIT63_FOR_MMC_HS400 | SDHCI_QUIRK_PRESET_VALUE_BROKEN }, { 0x22948086, 0xffff, "Intel Braswell eMMC 4.5.1 Controller", SDHCI_QUIRK_DATA_TIMEOUT_1MHZ | SDHCI_QUIRK_INTEL_POWER_UP_RESET | SDHCI_QUIRK_WAIT_WHILE_BUSY | SDHCI_QUIRK_MMC_DDR52 | SDHCI_QUIRK_CAPS_BIT63_FOR_MMC_HS400 | SDHCI_QUIRK_PRESET_VALUE_BROKEN }, { 0x22968086, 0xffff, "Intel Braswell SDXC Controller", SDHCI_QUIRK_WAIT_WHILE_BUSY | SDHCI_QUIRK_PRESET_VALUE_BROKEN }, { 0x5aca8086, 0xffff, "Intel Apollo Lake SDXC Controller", SDHCI_QUIRK_BROKEN_DMA | /* APL18 erratum */ SDHCI_QUIRK_WAIT_WHILE_BUSY | SDHCI_QUIRK_PRESET_VALUE_BROKEN }, { 0x5acc8086, 0xffff, "Intel Apollo Lake eMMC 5.0 Controller", SDHCI_QUIRK_BROKEN_DMA | /* APL18 erratum */ SDHCI_QUIRK_INTEL_POWER_UP_RESET | SDHCI_QUIRK_WAIT_WHILE_BUSY | SDHCI_QUIRK_MMC_DDR52 | SDHCI_QUIRK_CAPS_BIT63_FOR_MMC_HS400 | SDHCI_QUIRK_PRESET_VALUE_BROKEN }, { 0, 0xffff, NULL, 0 } }; struct sdhci_pci_softc { u_int quirks; /* Chip specific quirks */ struct resource *irq_res; /* IRQ resource */ void *intrhand; /* Interrupt handle */ int num_slots; /* Number of slots on this controller */ struct sdhci_slot slots[6]; struct resource *mem_res[6]; /* Memory resource */ uint8_t cfg_freq; /* Saved frequency */ uint8_t cfg_mode; /* Saved mode */ }; static int sdhci_enable_msi = 1; SYSCTL_INT(_hw_sdhci, OID_AUTO, enable_msi, CTLFLAG_RDTUN, &sdhci_enable_msi, 0, "Enable MSI interrupts"); static uint8_t sdhci_pci_read_1(device_t dev, struct sdhci_slot *slot __unused, bus_size_t off) { struct sdhci_pci_softc *sc = device_get_softc(dev); bus_barrier(sc->mem_res[slot->num], 0, 0xFF, BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); return bus_read_1(sc->mem_res[slot->num], off); } static void sdhci_pci_write_1(device_t dev, struct sdhci_slot *slot __unused, bus_size_t off, uint8_t val) { struct sdhci_pci_softc *sc = device_get_softc(dev); bus_barrier(sc->mem_res[slot->num], 0, 0xFF, BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); bus_write_1(sc->mem_res[slot->num], off, val); } static uint16_t sdhci_pci_read_2(device_t dev, struct sdhci_slot *slot __unused, bus_size_t off) { struct sdhci_pci_softc *sc = device_get_softc(dev); bus_barrier(sc->mem_res[slot->num], 0, 0xFF, BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); return bus_read_2(sc->mem_res[slot->num], off); } static void sdhci_pci_write_2(device_t dev, struct sdhci_slot *slot __unused, bus_size_t off, uint16_t val) { struct sdhci_pci_softc *sc = device_get_softc(dev); bus_barrier(sc->mem_res[slot->num], 0, 0xFF, BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); bus_write_2(sc->mem_res[slot->num], off, val); } static uint32_t sdhci_pci_read_4(device_t dev, struct sdhci_slot *slot __unused, bus_size_t off) { struct sdhci_pci_softc *sc = device_get_softc(dev); bus_barrier(sc->mem_res[slot->num], 0, 0xFF, BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); return bus_read_4(sc->mem_res[slot->num], off); } static void sdhci_pci_write_4(device_t dev, struct sdhci_slot *slot __unused, bus_size_t off, uint32_t val) { struct sdhci_pci_softc *sc = device_get_softc(dev); bus_barrier(sc->mem_res[slot->num], 0, 0xFF, BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); bus_write_4(sc->mem_res[slot->num], off, val); } static void sdhci_pci_read_multi_4(device_t dev, struct sdhci_slot *slot __unused, bus_size_t off, uint32_t *data, bus_size_t count) { struct sdhci_pci_softc *sc = device_get_softc(dev); bus_read_multi_stream_4(sc->mem_res[slot->num], off, data, count); } static void sdhci_pci_write_multi_4(device_t dev, struct sdhci_slot *slot __unused, bus_size_t off, uint32_t *data, bus_size_t count) { struct sdhci_pci_softc *sc = device_get_softc(dev); bus_write_multi_stream_4(sc->mem_res[slot->num], off, data, count); } static void sdhci_pci_intr(void *arg); static void sdhci_lower_frequency(device_t dev) { struct sdhci_pci_softc *sc = device_get_softc(dev); /* * Enable SD2.0 mode. * NB: for RICOH R5CE823, this changes the PCI device ID to 0xe822. */ pci_write_config(dev, SDHC_PCI_MODE_KEY, 0xfc, 1); sc->cfg_mode = pci_read_config(dev, SDHC_PCI_MODE, 1); pci_write_config(dev, SDHC_PCI_MODE, SDHC_PCI_MODE_SD20, 1); pci_write_config(dev, SDHC_PCI_MODE_KEY, 0x00, 1); /* * Some SD/MMC cards don't work with the default base * clock frequency of 200 MHz. Lower it to 50 MHz. */ pci_write_config(dev, SDHC_PCI_BASE_FREQ_KEY, 0x01, 1); sc->cfg_freq = pci_read_config(dev, SDHC_PCI_BASE_FREQ, 1); pci_write_config(dev, SDHC_PCI_BASE_FREQ, 50, 1); pci_write_config(dev, SDHC_PCI_BASE_FREQ_KEY, 0x00, 1); } static void sdhci_restore_frequency(device_t dev) { struct sdhci_pci_softc *sc = device_get_softc(dev); /* Restore mode. */ pci_write_config(dev, SDHC_PCI_MODE_KEY, 0xfc, 1); pci_write_config(dev, SDHC_PCI_MODE, sc->cfg_mode, 1); pci_write_config(dev, SDHC_PCI_MODE_KEY, 0x00, 1); /* Restore frequency. */ pci_write_config(dev, SDHC_PCI_BASE_FREQ_KEY, 0x01, 1); pci_write_config(dev, SDHC_PCI_BASE_FREQ, sc->cfg_freq, 1); pci_write_config(dev, SDHC_PCI_BASE_FREQ_KEY, 0x00, 1); } static int sdhci_pci_probe(device_t dev) { uint32_t model; uint16_t subvendor; uint8_t class, subclass; int i, result; model = (uint32_t)pci_get_device(dev) << 16; model |= (uint32_t)pci_get_vendor(dev) & 0x0000ffff; subvendor = pci_get_subvendor(dev); class = pci_get_class(dev); subclass = pci_get_subclass(dev); result = ENXIO; for (i = 0; sdhci_devices[i].model != 0; i++) { if (sdhci_devices[i].model == model && (sdhci_devices[i].subvendor == 0xffff || sdhci_devices[i].subvendor == subvendor)) { device_set_desc(dev, sdhci_devices[i].desc); result = BUS_PROBE_DEFAULT; break; } } if (result == ENXIO && class == PCIC_BASEPERIPH && subclass == PCIS_BASEPERIPH_SDHC) { device_set_desc(dev, "Generic SD HCI"); result = BUS_PROBE_GENERIC; } return (result); } static int sdhci_pci_attach(device_t dev) { struct sdhci_pci_softc *sc = device_get_softc(dev); struct sdhci_slot *slot; uint32_t model; uint16_t subvendor; int bar, err, rid, slots, i; model = (uint32_t)pci_get_device(dev) << 16; model |= (uint32_t)pci_get_vendor(dev) & 0x0000ffff; subvendor = pci_get_subvendor(dev); /* Apply chip specific quirks. */ for (i = 0; sdhci_devices[i].model != 0; i++) { if (sdhci_devices[i].model == model && (sdhci_devices[i].subvendor == 0xffff || sdhci_devices[i].subvendor == subvendor)) { sc->quirks = sdhci_devices[i].quirks; break; } } sc->quirks &= ~sdhci_quirk_clear; sc->quirks |= sdhci_quirk_set; /* Some controllers need to be bumped into the right mode. */ if (sc->quirks & SDHCI_QUIRK_LOWER_FREQUENCY) sdhci_lower_frequency(dev); /* Read slots info from PCI registers. */ slots = pci_read_config(dev, PCI_SLOT_INFO, 1); bar = PCI_SLOT_INFO_FIRST_BAR(slots); slots = PCI_SLOT_INFO_SLOTS(slots); if (slots > 6 || bar > 5) { device_printf(dev, "Incorrect slots information (%d, %d).\n", slots, bar); return (EINVAL); } /* Allocate IRQ. */ i = 1; rid = 0; if (sdhci_enable_msi != 0 && pci_alloc_msi(dev, &i) == 0) rid = 1; sc->irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, RF_ACTIVE | (rid != 0 ? 0 : RF_SHAREABLE)); if (sc->irq_res == NULL) { device_printf(dev, "Can't allocate IRQ\n"); pci_release_msi(dev); return (ENOMEM); } /* Scan all slots. */ for (i = 0; i < slots; i++) { slot = &sc->slots[sc->num_slots]; /* Allocate memory. */ rid = PCIR_BAR(bar + i); sc->mem_res[i] = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, RF_ACTIVE); if (sc->mem_res[i] == NULL) { device_printf(dev, "Can't allocate memory for slot %d\n", i); continue; } slot->quirks = sc->quirks; if (sdhci_init_slot(dev, slot, i) != 0) continue; sc->num_slots++; } device_printf(dev, "%d slot(s) allocated\n", sc->num_slots); /* Activate the interrupt */ err = bus_setup_intr(dev, sc->irq_res, INTR_TYPE_MISC | INTR_MPSAFE, NULL, sdhci_pci_intr, sc, &sc->intrhand); if (err) device_printf(dev, "Can't setup IRQ\n"); pci_enable_busmaster(dev); /* Process cards detection. */ for (i = 0; i < sc->num_slots; i++) { -#ifdef MMCCAM - sdhci_cam_start_slot(&sc->slots[i]); -#else sdhci_start_slot(&sc->slots[i]); -#endif } return (0); } static int sdhci_pci_detach(device_t dev) { struct sdhci_pci_softc *sc = device_get_softc(dev); int i; bus_teardown_intr(dev, sc->irq_res, sc->intrhand); bus_release_resource(dev, SYS_RES_IRQ, rman_get_rid(sc->irq_res), sc->irq_res); pci_release_msi(dev); for (i = 0; i < sc->num_slots; i++) { sdhci_cleanup_slot(&sc->slots[i]); bus_release_resource(dev, SYS_RES_MEMORY, rman_get_rid(sc->mem_res[i]), sc->mem_res[i]); } if (sc->quirks & SDHCI_QUIRK_LOWER_FREQUENCY) sdhci_restore_frequency(dev); return (0); } static int sdhci_pci_shutdown(device_t dev) { struct sdhci_pci_softc *sc = device_get_softc(dev); if (sc->quirks & SDHCI_QUIRK_LOWER_FREQUENCY) sdhci_restore_frequency(dev); return (0); } static int sdhci_pci_suspend(device_t dev) { struct sdhci_pci_softc *sc = device_get_softc(dev); int i, err; err = bus_generic_suspend(dev); if (err) return (err); for (i = 0; i < sc->num_slots; i++) sdhci_generic_suspend(&sc->slots[i]); return (0); } static int sdhci_pci_resume(device_t dev) { struct sdhci_pci_softc *sc = device_get_softc(dev); int i, err; for (i = 0; i < sc->num_slots; i++) sdhci_generic_resume(&sc->slots[i]); err = bus_generic_resume(dev); if (err) return (err); if (sc->quirks & SDHCI_QUIRK_LOWER_FREQUENCY) sdhci_lower_frequency(dev); return (0); } static void sdhci_pci_intr(void *arg) { struct sdhci_pci_softc *sc = (struct sdhci_pci_softc *)arg; int i; for (i = 0; i < sc->num_slots; i++) sdhci_generic_intr(&sc->slots[i]); } static device_method_t sdhci_methods[] = { /* device_if */ DEVMETHOD(device_probe, sdhci_pci_probe), DEVMETHOD(device_attach, sdhci_pci_attach), DEVMETHOD(device_detach, sdhci_pci_detach), DEVMETHOD(device_shutdown, sdhci_pci_shutdown), DEVMETHOD(device_suspend, sdhci_pci_suspend), DEVMETHOD(device_resume, sdhci_pci_resume), /* Bus interface */ DEVMETHOD(bus_read_ivar, sdhci_generic_read_ivar), DEVMETHOD(bus_write_ivar, sdhci_generic_write_ivar), /* mmcbr_if */ DEVMETHOD(mmcbr_update_ios, sdhci_generic_update_ios), DEVMETHOD(mmcbr_switch_vccq, sdhci_generic_switch_vccq), DEVMETHOD(mmcbr_tune, sdhci_generic_tune), DEVMETHOD(mmcbr_retune, sdhci_generic_retune), DEVMETHOD(mmcbr_request, sdhci_generic_request), DEVMETHOD(mmcbr_get_ro, sdhci_generic_get_ro), DEVMETHOD(mmcbr_acquire_host, sdhci_generic_acquire_host), DEVMETHOD(mmcbr_release_host, sdhci_generic_release_host), /* SDHCI accessors */ DEVMETHOD(sdhci_read_1, sdhci_pci_read_1), DEVMETHOD(sdhci_read_2, sdhci_pci_read_2), DEVMETHOD(sdhci_read_4, sdhci_pci_read_4), DEVMETHOD(sdhci_read_multi_4, sdhci_pci_read_multi_4), DEVMETHOD(sdhci_write_1, sdhci_pci_write_1), DEVMETHOD(sdhci_write_2, sdhci_pci_write_2), DEVMETHOD(sdhci_write_4, sdhci_pci_write_4), DEVMETHOD(sdhci_write_multi_4, sdhci_pci_write_multi_4), DEVMETHOD(sdhci_set_uhs_timing, sdhci_generic_set_uhs_timing), DEVMETHOD_END }; static driver_t sdhci_pci_driver = { "sdhci_pci", sdhci_methods, sizeof(struct sdhci_pci_softc), }; static devclass_t sdhci_pci_devclass; DRIVER_MODULE(sdhci_pci, pci, sdhci_pci_driver, sdhci_pci_devclass, NULL, NULL); MODULE_DEPEND(sdhci_pci, sdhci, 1, 1, 1); #ifndef MMCCAM MMC_DECLARE_BRIDGE(sdhci_pci); #endif