Index: head/sys/arm64/arm64/identcpu.c
===================================================================
--- head/sys/arm64/arm64/identcpu.c	(revision 323592)
+++ head/sys/arm64/arm64/identcpu.c	(revision 323593)
@@ -1,971 +1,967 @@
 /*-
  * Copyright (c) 2014 Andrew Turner
  * Copyright (c) 2014 The FreeBSD Foundation
  * All rights reserved.
  *
  * Portions of this software were developed by Semihalf
  * under sponsorship of the FreeBSD Foundation.
  *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions
  * are met:
  * 1. Redistributions of source code must retain the above copyright
  *    notice, this list of conditions and the following disclaimer.
  * 2. Redistributions in binary form must reproduce the above copyright
  *    notice, this list of conditions and the following disclaimer in the
  *    documentation and/or other materials provided with the distribution.
  *
  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  * SUCH DAMAGE.
  *
  */
 
 #include <sys/cdefs.h>
 __FBSDID("$FreeBSD$");
 
 #include <sys/param.h>
 #include <sys/kernel.h>
 #include <sys/pcpu.h>
 #include <sys/smp.h>
 #include <sys/sysctl.h>
 #include <sys/systm.h>
 
 #include <machine/atomic.h>
 #include <machine/cpu.h>
 #include <machine/cpufunc.h>
 
 static int ident_lock;
 
 char machine[] = "arm64";
 
 SYSCTL_STRING(_hw, HW_MACHINE, machine, CTLFLAG_RD, machine, 0,
     "Machine class");
 
 /*
  * Per-CPU affinity as provided in MPIDR_EL1
  * Indexed by CPU number in logical order selected by the system.
  * Relevant fields can be extracted using CPU_AFFn macros,
  * Aff3.Aff2.Aff1.Aff0 construct a unique CPU address in the system.
  *
  * Fields used by us:
  * Aff1 - Cluster number
  * Aff0 - CPU number in Aff1 cluster
  */
 uint64_t __cpu_affinity[MAXCPU];
 static u_int cpu_aff_levels;
 
 struct cpu_desc {
 	u_int		cpu_impl;
 	u_int		cpu_part_num;
 	u_int		cpu_variant;
 	u_int		cpu_revision;
 	const char	*cpu_impl_name;
 	const char	*cpu_part_name;
 
 	uint64_t	mpidr;
 	uint64_t	id_aa64afr0;
 	uint64_t	id_aa64afr1;
 	uint64_t	id_aa64dfr0;
 	uint64_t	id_aa64dfr1;
 	uint64_t	id_aa64isar0;
 	uint64_t	id_aa64isar1;
 	uint64_t	id_aa64mmfr0;
 	uint64_t	id_aa64mmfr1;
 	uint64_t	id_aa64mmfr2;
 	uint64_t	id_aa64pfr0;
 	uint64_t	id_aa64pfr1;
 };
 
 struct cpu_desc cpu_desc[MAXCPU];
 static u_int cpu_print_regs;
 #define	PRINT_ID_AA64_AFR0	0x00000001
 #define	PRINT_ID_AA64_AFR1	0x00000002
 #define	PRINT_ID_AA64_DFR0	0x00000010
 #define	PRINT_ID_AA64_DFR1	0x00000020
 #define	PRINT_ID_AA64_ISAR0	0x00000100
 #define	PRINT_ID_AA64_ISAR1	0x00000200
 #define	PRINT_ID_AA64_MMFR0	0x00001000
 #define	PRINT_ID_AA64_MMFR1	0x00002000
 #define	PRINT_ID_AA64_MMFR2	0x00004000
 #define	PRINT_ID_AA64_PFR0	0x00010000
 #define	PRINT_ID_AA64_PFR1	0x00020000
 
 struct cpu_parts {
 	u_int		part_id;
 	const char	*part_name;
 };
 #define	CPU_PART_NONE	{ 0, "Unknown Processor" }
 
 struct cpu_implementers {
 	u_int			impl_id;
 	const char		*impl_name;
 	/*
 	 * Part number is implementation defined
 	 * so each vendor will have its own set of values and names.
 	 */
 	const struct cpu_parts	*cpu_parts;
 };
 #define	CPU_IMPLEMENTER_NONE	{ 0, "Unknown Implementer", cpu_parts_none }
 
 /*
  * Per-implementer table of (PartNum, CPU Name) pairs.
  */
 /* ARM Ltd. */
 static const struct cpu_parts cpu_parts_arm[] = {
 	{ CPU_PART_FOUNDATION, "Foundation-Model" },
 	{ CPU_PART_CORTEX_A35, "Cortex-A35" },
 	{ CPU_PART_CORTEX_A53, "Cortex-A53" },
 	{ CPU_PART_CORTEX_A55, "Cortex-A55" },
 	{ CPU_PART_CORTEX_A57, "Cortex-A57" },
 	{ CPU_PART_CORTEX_A72, "Cortex-A72" },
 	{ CPU_PART_CORTEX_A73, "Cortex-A73" },
 	{ CPU_PART_CORTEX_A75, "Cortex-A75" },
 	CPU_PART_NONE,
 };
 /* Cavium */
 static const struct cpu_parts cpu_parts_cavium[] = {
 	{ CPU_PART_THUNDER, "Thunder" },
 	CPU_PART_NONE,
 };
 
 /* Unknown */
 static const struct cpu_parts cpu_parts_none[] = {
 	CPU_PART_NONE,
 };
 
 /*
  * Implementers table.
  */
 const struct cpu_implementers cpu_implementers[] = {
 	{ CPU_IMPL_ARM,		"ARM",		cpu_parts_arm },
 	{ CPU_IMPL_BROADCOM,	"Broadcom",	cpu_parts_none },
 	{ CPU_IMPL_CAVIUM,	"Cavium",	cpu_parts_cavium },
 	{ CPU_IMPL_DEC,		"DEC",		cpu_parts_none },
 	{ CPU_IMPL_INFINEON,	"IFX",		cpu_parts_none },
 	{ CPU_IMPL_FREESCALE,	"Freescale",	cpu_parts_none },
 	{ CPU_IMPL_NVIDIA,	"NVIDIA",	cpu_parts_none },
 	{ CPU_IMPL_APM,		"APM",		cpu_parts_none },
 	{ CPU_IMPL_QUALCOMM,	"Qualcomm",	cpu_parts_none },
 	{ CPU_IMPL_MARVELL,	"Marvell",	cpu_parts_none },
 	{ CPU_IMPL_INTEL,	"Intel",	cpu_parts_none },
 	CPU_IMPLEMENTER_NONE,
 };
 
 static void
 identify_cpu_sysinit(void *dummy __unused)
 {
 	int cpu;
 
 	CPU_FOREACH(cpu) {
 		print_cpu_features(cpu);
 	}
 }
 SYSINIT(idenrity_cpu, SI_SUB_SMP, SI_ORDER_ANY, identify_cpu_sysinit, NULL);
 
 void
 print_cpu_features(u_int cpu)
 {
 	int printed;
 
 	printf("CPU%3d: %s %s r%dp%d", cpu, cpu_desc[cpu].cpu_impl_name,
 	    cpu_desc[cpu].cpu_part_name, cpu_desc[cpu].cpu_variant,
 	    cpu_desc[cpu].cpu_revision);
 
 	printf(" affinity:");
 	switch(cpu_aff_levels) {
 	default:
 	case 4:
 		printf(" %2d", CPU_AFF3(cpu_desc[cpu].mpidr));
 		/* FALLTHROUGH */
 	case 3:
 		printf(" %2d", CPU_AFF2(cpu_desc[cpu].mpidr));
 		/* FALLTHROUGH */
 	case 2:
 		printf(" %2d", CPU_AFF1(cpu_desc[cpu].mpidr));
 		/* FALLTHROUGH */
 	case 1:
 	case 0: /* On UP this will be zero */
 		printf(" %2d", CPU_AFF0(cpu_desc[cpu].mpidr));
 		break;
 	}
 	printf("\n");
 
 	/*
 	 * There is a hardware errata where, if one CPU is performing a TLB
 	 * invalidation while another is performing a store-exclusive the
 	 * store-exclusive may return the wrong status. A workaround seems
 	 * to be to use an IPI to invalidate on each CPU, however given the
 	 * limited number of affected units (pass 1.1 is the evaluation
 	 * hardware revision), and the lack of information from Cavium
 	 * this has not been implemented.
 	 *
 	 * At the time of writing this the only information is from:
 	 * https://lkml.org/lkml/2016/8/4/722
 	 */
 	/*
 	 * XXX: CPU_MATCH_ERRATA_CAVIUM_THUNDER_1_1 on its own also
 	 * triggers on pass 2.0+.
 	 */
 	if (cpu == 0 && CPU_VAR(PCPU_GET(midr)) == 0 &&
 	    CPU_MATCH_ERRATA_CAVIUM_THUNDER_1_1)
 		printf("WARNING: ThunderX Pass 1.1 detected.\nThis has known "
 		    "hardware bugs that may cause the incorrect operation of "
 		    "atomic operations.\n");
 
 	if (cpu != 0 && cpu_print_regs == 0)
 		return;
 
 #define SEP_STR	((printed++) == 0) ? "" : ","
 
 	/* AArch64 Instruction Set Attribute Register 0 */
 	if (cpu == 0 || (cpu_print_regs & PRINT_ID_AA64_ISAR0) != 0) {
 		printed = 0;
 		printf(" Instruction Set Attributes 0 = <");
 
 		switch (ID_AA64ISAR0_RDM(cpu_desc[cpu].id_aa64isar0)) {
 		case ID_AA64ISAR0_RDM_NONE:
 			break;
 		case ID_AA64ISAR0_RDM_IMPL:
 			printf("%sRDM", SEP_STR);
 			break;
 		default:
 			printf("%sUnknown RDM", SEP_STR);
 		}
 
 		switch (ID_AA64ISAR0_ATOMIC(cpu_desc[cpu].id_aa64isar0)) {
 		case ID_AA64ISAR0_ATOMIC_NONE:
 			break;
 		case ID_AA64ISAR0_ATOMIC_IMPL:
 			printf("%sAtomic", SEP_STR);
 			break;
 		default:
 			printf("%sUnknown Atomic", SEP_STR);
 		}
 
 		switch (ID_AA64ISAR0_AES(cpu_desc[cpu].id_aa64isar0)) {
 		case ID_AA64ISAR0_AES_NONE:
 			break;
 		case ID_AA64ISAR0_AES_BASE:
 			printf("%sAES", SEP_STR);
 			break;
 		case ID_AA64ISAR0_AES_PMULL:
 			printf("%sAES+PMULL", SEP_STR);
 			break;
 		default:
 			printf("%sUnknown AES", SEP_STR);
 			break;
 		}
 
 		switch (ID_AA64ISAR0_SHA1(cpu_desc[cpu].id_aa64isar0)) {
 		case ID_AA64ISAR0_SHA1_NONE:
 			break;
 		case ID_AA64ISAR0_SHA1_BASE:
 			printf("%sSHA1", SEP_STR);
 			break;
 		default:
 			printf("%sUnknown SHA1", SEP_STR);
 			break;
 		}
 
 		switch (ID_AA64ISAR0_SHA2(cpu_desc[cpu].id_aa64isar0)) {
 		case ID_AA64ISAR0_SHA2_NONE:
 			break;
 		case ID_AA64ISAR0_SHA2_BASE:
 			printf("%sSHA2", SEP_STR);
 			break;
 		default:
 			printf("%sUnknown SHA2", SEP_STR);
 			break;
 		}
 
 		switch (ID_AA64ISAR0_CRC32(cpu_desc[cpu].id_aa64isar0)) {
 		case ID_AA64ISAR0_CRC32_NONE:
 			break;
 		case ID_AA64ISAR0_CRC32_BASE:
 			printf("%sCRC32", SEP_STR);
 			break;
 		default:
 			printf("%sUnknown CRC32", SEP_STR);
 			break;
 		}
 
 		if ((cpu_desc[cpu].id_aa64isar0 & ~ID_AA64ISAR0_MASK) != 0)
 			printf("%s%#lx", SEP_STR,
 			    cpu_desc[cpu].id_aa64isar0 & ~ID_AA64ISAR0_MASK);
 
 		printf(">\n");
 	}
 
 	/* AArch64 Instruction Set Attribute Register 1 */
 	if (cpu == 0 || (cpu_print_regs & PRINT_ID_AA64_ISAR1) != 0) {
 		printed = 0;
 		printf(" Instruction Set Attributes 1 = <");
 
 		switch (ID_AA64ISAR1_DPB(cpu_desc[cpu].id_aa64isar1)) {
 		case ID_AA64ISAR1_DPB_NONE:
 			break;
 		case ID_AA64ISAR1_DPB_IMPL:
 			printf("%sDC CVAP", SEP_STR);
 			break;
 		default:
 			printf("%sUnknown DC CVAP", SEP_STR);
 			break;
 		}
 
 		if ((cpu_desc[cpu].id_aa64isar1 & ~ID_AA64ISAR1_MASK) != 0)
 			printf("%s%#lx", SEP_STR,
 			    cpu_desc[cpu].id_aa64isar1 & ~ID_AA64ISAR1_MASK);
 		printf(">\n");
 	}
 
 	/* AArch64 Processor Feature Register 0 */
 	if (cpu == 0 || (cpu_print_regs & PRINT_ID_AA64_PFR0) != 0) {
 		printed = 0;
 		printf("         Processor Features 0 = <");
 
 		switch (ID_AA64PFR0_SVE(cpu_desc[cpu].id_aa64pfr0)) {
 		case ID_AA64PFR0_SVE_NONE:
 			break;
 		case ID_AA64PFR0_SVE_IMPL:
 			printf("%sSVE", SEP_STR);
 			break;
 		default:
 			printf("%sUnknown SVE", SEP_STR);
 			break;
 		}
 
 		switch (ID_AA64PFR0_RAS(cpu_desc[cpu].id_aa64pfr0)) {
 		case ID_AA64PFR0_RAS_NONE:
 			break;
 		case ID_AA64PFR0_RAS_V1:
 			printf("%sRASv1", SEP_STR);
 			break;
 		default:
 			printf("%sUnknown RAS", SEP_STR);
 			break;
 		}
 
 		switch (ID_AA64PFR0_GIC(cpu_desc[cpu].id_aa64pfr0)) {
 		case ID_AA64PFR0_GIC_CPUIF_NONE:
 			break;
 		case ID_AA64PFR0_GIC_CPUIF_EN:
 			printf("%sGIC", SEP_STR);
 			break;
 		default:
 			printf("%sUnknown GIC interface", SEP_STR);
 			break;
 		}
 
 		switch (ID_AA64PFR0_ADV_SIMD(cpu_desc[cpu].id_aa64pfr0)) {
 		case ID_AA64PFR0_ADV_SIMD_NONE:
 			break;
 		case ID_AA64PFR0_ADV_SIMD_IMPL:
 			printf("%sAdvSIMD", SEP_STR);
 			break;
 		case ID_AA64PFR0_ADV_SIMD_HP:
 			printf("%sAdvSIMD+HP", SEP_STR);
 			break;
 		default:
 			printf("%sUnknown AdvSIMD", SEP_STR);
 			break;
 		}
 
 		switch (ID_AA64PFR0_FP(cpu_desc[cpu].id_aa64pfr0)) {
 		case ID_AA64PFR0_FP_NONE:
 			break;
 		case ID_AA64PFR0_FP_IMPL:
 			printf("%sFloat", SEP_STR);
 			break;
 		case ID_AA64PFR0_FP_HP:
 			printf("%sFloat+HP", SEP_STR);
 			break;
 		default:
 			printf("%sUnknown Float", SEP_STR);
 			break;
 		}
 
 		switch (ID_AA64PFR0_EL3(cpu_desc[cpu].id_aa64pfr0)) {
 		case ID_AA64PFR0_EL3_NONE:
 			printf("%sNo EL3", SEP_STR);
 			break;
 		case ID_AA64PFR0_EL3_64:
 			printf("%sEL3", SEP_STR);
 			break;
 		case ID_AA64PFR0_EL3_64_32:
 			printf("%sEL3 32", SEP_STR);
 			break;
 		default:
 			printf("%sUnknown EL3", SEP_STR);
 			break;
 		}
 
 		switch (ID_AA64PFR0_EL2(cpu_desc[cpu].id_aa64pfr0)) {
 		case ID_AA64PFR0_EL2_NONE:
 			printf("%sNo EL2", SEP_STR);
 			break;
 		case ID_AA64PFR0_EL2_64:
 			printf("%sEL2", SEP_STR);
 			break;
 		case ID_AA64PFR0_EL2_64_32:
 			printf("%sEL2 32", SEP_STR);
 			break;
 		default:
 			printf("%sUnknown EL2", SEP_STR);
 			break;
 		}
 
 		switch (ID_AA64PFR0_EL1(cpu_desc[cpu].id_aa64pfr0)) {
 		case ID_AA64PFR0_EL1_64:
 			printf("%sEL1", SEP_STR);
 			break;
 		case ID_AA64PFR0_EL1_64_32:
 			printf("%sEL1 32", SEP_STR);
 			break;
 		default:
 			printf("%sUnknown EL1", SEP_STR);
 			break;
 		}
 
 		switch (ID_AA64PFR0_EL0(cpu_desc[cpu].id_aa64pfr0)) {
 		case ID_AA64PFR0_EL0_64:
 			printf("%sEL0", SEP_STR);
 			break;
 		case ID_AA64PFR0_EL0_64_32:
 			printf("%sEL0 32", SEP_STR);
 			break;
 		default:
 			printf("%sUnknown EL0", SEP_STR);
 			break;
 		}
 
 		if ((cpu_desc[cpu].id_aa64pfr0 & ~ID_AA64PFR0_MASK) != 0)
 			printf("%s%#lx", SEP_STR,
 			    cpu_desc[cpu].id_aa64pfr0 & ~ID_AA64PFR0_MASK);
 
 		printf(">\n");
 	}
 
 	/* AArch64 Processor Feature Register 1 */
 	if (cpu == 0 || (cpu_print_regs & PRINT_ID_AA64_PFR1) != 0) {
 		printf("         Processor Features 1 = <%#lx>\n",
 		    cpu_desc[cpu].id_aa64pfr1);
 	}
 
 	/* AArch64 Memory Model Feature Register 0 */
 	if (cpu == 0 || (cpu_print_regs & PRINT_ID_AA64_MMFR0) != 0) {
 		printed = 0;
 		printf("      Memory Model Features 0 = <");
 		switch (ID_AA64MMFR0_TGRAN4(cpu_desc[cpu].id_aa64mmfr0)) {
 		case ID_AA64MMFR0_TGRAN4_NONE:
 			break;
 		case ID_AA64MMFR0_TGRAN4_IMPL:
 			printf("%s4k Granule", SEP_STR);
 			break;
 		default:
 			printf("%sUnknown 4k Granule", SEP_STR);
 			break;
 		}
 
 		switch (ID_AA64MMFR0_TGRAN16(cpu_desc[cpu].id_aa64mmfr0)) {
 		case ID_AA64MMFR0_TGRAN16_NONE:
 			break;
 		case ID_AA64MMFR0_TGRAN16_IMPL:
 			printf("%s16k Granule", SEP_STR);
 			break;
 		default:
 			printf("%sUnknown 16k Granule", SEP_STR);
 			break;
 		}
 
 		switch (ID_AA64MMFR0_TGRAN64(cpu_desc[cpu].id_aa64mmfr0)) {
 		case ID_AA64MMFR0_TGRAN64_NONE:
 			break;
 		case ID_AA64MMFR0_TGRAN64_IMPL:
 			printf("%s64k Granule", SEP_STR);
 			break;
 		default:
 			printf("%sUnknown 64k Granule", SEP_STR);
 			break;
 		}
 
 		switch (ID_AA64MMFR0_BIGEND(cpu_desc[cpu].id_aa64mmfr0)) {
 		case ID_AA64MMFR0_BIGEND_FIXED:
 			break;
 		case ID_AA64MMFR0_BIGEND_MIXED:
 			printf("%sMixedEndian", SEP_STR);
 			break;
 		default:
 			printf("%sUnknown Endian switching", SEP_STR);
 			break;
 		}
 
 		switch (ID_AA64MMFR0_BIGEND_EL0(cpu_desc[cpu].id_aa64mmfr0)) {
 		case ID_AA64MMFR0_BIGEND_EL0_FIXED:
 			break;
 		case ID_AA64MMFR0_BIGEND_EL0_MIXED:
 			printf("%sEL0 MixEndian", SEP_STR);
 			break;
 		default:
 			printf("%sUnknown EL0 Endian switching", SEP_STR);
 			break;
 		}
 
 		switch (ID_AA64MMFR0_S_NS_MEM(cpu_desc[cpu].id_aa64mmfr0)) {
 		case ID_AA64MMFR0_S_NS_MEM_NONE:
 			break;
 		case ID_AA64MMFR0_S_NS_MEM_DISTINCT:
 			printf("%sS/NS Mem", SEP_STR);
 			break;
 		default:
 			printf("%sUnknown S/NS Mem", SEP_STR);
 			break;
 		}
 
 		switch (ID_AA64MMFR0_ASID_BITS(cpu_desc[cpu].id_aa64mmfr0)) {
 		case ID_AA64MMFR0_ASID_BITS_8:
 			printf("%s8bit ASID", SEP_STR);
 			break;
 		case ID_AA64MMFR0_ASID_BITS_16:
 			printf("%s16bit ASID", SEP_STR);
 			break;
 		default:
 			printf("%sUnknown ASID", SEP_STR);
 			break;
 		}
 
 		switch (ID_AA64MMFR0_PA_RANGE(cpu_desc[cpu].id_aa64mmfr0)) {
 		case ID_AA64MMFR0_PA_RANGE_4G:
 			printf("%s4GB PA", SEP_STR);
 			break;
 		case ID_AA64MMFR0_PA_RANGE_64G:
 			printf("%s64GB PA", SEP_STR);
 			break;
 		case ID_AA64MMFR0_PA_RANGE_1T:
 			printf("%s1TB PA", SEP_STR);
 			break;
 		case ID_AA64MMFR0_PA_RANGE_4T:
 			printf("%s4TB PA", SEP_STR);
 			break;
 		case ID_AA64MMFR0_PA_RANGE_16T:
 			printf("%s16TB PA", SEP_STR);
 			break;
 		case ID_AA64MMFR0_PA_RANGE_256T:
 			printf("%s256TB PA", SEP_STR);
 			break;
 		case ID_AA64MMFR0_PA_RANGE_4P:
 			printf("%s4PB PA", SEP_STR);
 			break;
 		default:
 			printf("%sUnknown PA Range", SEP_STR);
 			break;
 		}
 
 		if ((cpu_desc[cpu].id_aa64mmfr0 & ~ID_AA64MMFR0_MASK) != 0)
 			printf("%s%#lx", SEP_STR,
 			    cpu_desc[cpu].id_aa64mmfr0 & ~ID_AA64MMFR0_MASK);
 		printf(">\n");
 	}
 
 	/* AArch64 Memory Model Feature Register 1 */
 	if (cpu == 0 || (cpu_print_regs & PRINT_ID_AA64_MMFR1) != 0) {
 		printed = 0;
 		printf("      Memory Model Features 1 = <");
 
 		switch (ID_AA64MMFR1_XNX(cpu_desc[cpu].id_aa64mmfr1)) {
 		case ID_AA64MMFR1_XNX_NONE:
 			break;
 		case ID_AA64MMFR1_XNX_IMPL:
 			printf("%sEL2 XN", SEP_STR);
 			break;
 		default:
 			printf("%sUnknown XNX", SEP_STR);
 			break;
 		}
 
 		switch (ID_AA64MMFR1_SPEC_SEI(cpu_desc[cpu].id_aa64mmfr1)) {
 		case ID_AA64MMFR1_SPEC_SEI_NONE:
 			break;
 		case ID_AA64MMFR1_SPEC_SEI_IMPL:
 			printf("%sSpecSEI", SEP_STR);
 			break;
 		default:
 			printf("%sUnknown SpecSEI", SEP_STR);
 			break;
 		}
 
 		switch (ID_AA64MMFR1_PAN(cpu_desc[cpu].id_aa64mmfr1)) {
 		case ID_AA64MMFR1_PAN_NONE:
 			break;
 		case ID_AA64MMFR1_PAN_IMPL:
 			printf("%sPAN", SEP_STR);
 			break;
 		case ID_AA64MMFR1_PAN_ATS1E1:
 			printf("%sPAN+AT", SEP_STR);
 			break;
 		default:
 			printf("%sUnknown PAN", SEP_STR);
 			break;
 		}
 
 		switch (ID_AA64MMFR1_LO(cpu_desc[cpu].id_aa64mmfr1)) {
 		case ID_AA64MMFR1_LO_NONE:
 			break;
 		case ID_AA64MMFR1_LO_IMPL:
 			printf("%sLO", SEP_STR);
 			break;
 		default:
 			printf("%sUnknown LO", SEP_STR);
 			break;
 		}
 
 		switch (ID_AA64MMFR1_HPDS(cpu_desc[cpu].id_aa64mmfr1)) {
 		case ID_AA64MMFR1_HPDS_NONE:
 			break;
 		case ID_AA64MMFR1_HPDS_HPD:
 			printf("%sHPDS", SEP_STR);
 			break;
 		case ID_AA64MMFR1_HPDS_TTPBHA:
 			printf("%sTTPBHA", SEP_STR);
 			break;
 		default:
 			printf("%sUnknown HPDS", SEP_STR);
 			break;
 		}
 
 		switch (ID_AA64MMFR1_VH(cpu_desc[cpu].id_aa64mmfr1)) {
 		case ID_AA64MMFR1_VH_NONE:
 			break;
 		case ID_AA64MMFR1_VH_IMPL:
 			printf("%sVHE", SEP_STR);
 			break;
 		default:
 			printf("%sUnknown VHE", SEP_STR);
 			break;
 		}
 
 		switch (ID_AA64MMFR1_VMIDBITS(cpu_desc[cpu].id_aa64mmfr1)) {
 		case ID_AA64MMFR1_VMIDBITS_8:
 			break;
 		case ID_AA64MMFR1_VMIDBITS_16:
 			printf("%s16 VMID bits", SEP_STR);
 			break;
 		default:
 			printf("%sUnknown VMID bits", SEP_STR);
 			break;
 		}
 
 		switch (ID_AA64MMFR1_HAFDBS(cpu_desc[cpu].id_aa64mmfr1)) {
 		case ID_AA64MMFR1_HAFDBS_NONE:
 			break;
 		case ID_AA64MMFR1_HAFDBS_AF:
 			printf("%sAF", SEP_STR);
 			break;
 		case ID_AA64MMFR1_HAFDBS_AF_DBS:
 			printf("%sAF+DBS", SEP_STR);
 			break;
 		default:
 			printf("%sUnknown Hardware update AF/DBS", SEP_STR);
 			break;
 		}
 
 		if ((cpu_desc[cpu].id_aa64mmfr1 & ~ID_AA64MMFR1_MASK) != 0)
 			printf("%s%#lx", SEP_STR,
 			    cpu_desc[cpu].id_aa64mmfr1 & ~ID_AA64MMFR1_MASK);
 		printf(">\n");
 	}
 
 	/* AArch64 Memory Model Feature Register 2 */
 	if (cpu == 0 || (cpu_print_regs & PRINT_ID_AA64_MMFR2) != 0) {
 		printed = 0;
 		printf("      Memory Model Features 2 = <");
 
 		switch (ID_AA64MMFR2_VA_RANGE(cpu_desc[cpu].id_aa64mmfr2)) {
 		case ID_AA64MMFR2_VA_RANGE_48:
 			printf("%s48b VA", SEP_STR);
 			break;
 		case ID_AA64MMFR2_VA_RANGE_52:
 			printf("%s52b VA", SEP_STR);
 			break;
 		default:
 			printf("%sUnknown VA Range", SEP_STR);
 			break;
 		}
 
 		switch (ID_AA64MMFR2_IESB(cpu_desc[cpu].id_aa64mmfr2)) {
 		case ID_AA64MMFR2_IESB_NONE:
 			break;
 		case ID_AA64MMFR2_IESB_IMPL:
 			printf("%sIESB", SEP_STR);
 			break;
 		default:
 			printf("%sUnknown IESB", SEP_STR);
 			break;
 		}
 
 		switch (ID_AA64MMFR2_LSM(cpu_desc[cpu].id_aa64mmfr2)) {
 		case ID_AA64MMFR2_LSM_NONE:
 			break;
 		case ID_AA64MMFR2_LSM_IMPL:
 			printf("%sLSM", SEP_STR);
 			break;
 		default:
 			printf("%sUnknown LSM", SEP_STR);
 			break;
 		}
 
 		switch (ID_AA64MMFR2_UAO(cpu_desc[cpu].id_aa64mmfr2)) {
 		case ID_AA64MMFR2_UAO_NONE:
 			break;
 		case ID_AA64MMFR2_UAO_IMPL:
 			printf("%sUAO", SEP_STR);
 			break;
 		default:
 			printf("%sUnknown UAO", SEP_STR);
 			break;
 		}
 
 		switch (ID_AA64MMFR2_CNP(cpu_desc[cpu].id_aa64mmfr2)) {
 		case ID_AA64MMFR2_CNP_NONE:
 			break;
 		case ID_AA64MMFR2_CNP_IMPL:
 			printf("%sCnP", SEP_STR);
 			break;
 		default:
 			printf("%sUnknown CnP", SEP_STR);
 			break;
 		}
 
 		if ((cpu_desc[cpu].id_aa64mmfr2 & ~ID_AA64MMFR2_MASK) != 0)
 			printf("%s%#lx", SEP_STR,
 			    cpu_desc[cpu].id_aa64mmfr2 & ~ID_AA64MMFR2_MASK);
 		printf(">\n");
 	}
 
 	/* AArch64 Debug Feature Register 0 */
 	if (cpu == 0 || (cpu_print_regs & PRINT_ID_AA64_DFR0) != 0) {
 		printed = 0;
 		printf("             Debug Features 0 = <");
 		switch(ID_AA64DFR0_PMS_VER(cpu_desc[cpu].id_aa64dfr0)) {
 		case ID_AA64DFR0_PMS_VER_NONE:
 			break;
 		case ID_AA64DFR0_PMS_VER_V1:
 			printf("%sSPE v1", SEP_STR);
 			break;
 		default:
 			printf("%sUnknown SPE", SEP_STR);
 			break;
 		}
 
 		printf("%s%lu CTX Breakpoints", SEP_STR,
 		    ID_AA64DFR0_CTX_CMPS(cpu_desc[cpu].id_aa64dfr0));
 
 		printf("%s%lu Watchpoints", SEP_STR,
 		    ID_AA64DFR0_WRPS(cpu_desc[cpu].id_aa64dfr0));
 
 		printf("%s%lu Breakpoints", SEP_STR,
 		    ID_AA64DFR0_BRPS(cpu_desc[cpu].id_aa64dfr0));
 
 		switch (ID_AA64DFR0_PMU_VER(cpu_desc[cpu].id_aa64dfr0)) {
 		case ID_AA64DFR0_PMU_VER_NONE:
 			break;
 		case ID_AA64DFR0_PMU_VER_3:
 			printf("%sPMUv3", SEP_STR);
 			break;
 		case ID_AA64DFR0_PMU_VER_3_1:
 			printf("%sPMUv3+16 bit evtCount", SEP_STR);
 			break;
 		case ID_AA64DFR0_PMU_VER_IMPL:
 			printf("%sImplementation defined PMU", SEP_STR);
 			break;
 		default:
 			printf("%sUnknown PMU", SEP_STR);
 			break;
 		}
 
 		switch (ID_AA64DFR0_TRACE_VER(cpu_desc[cpu].id_aa64dfr0)) {
 		case ID_AA64DFR0_TRACE_VER_NONE:
 			break;
 		case ID_AA64DFR0_TRACE_VER_IMPL:
 			printf("%sTrace", SEP_STR);
 			break;
 		default:
 			printf("%sUnknown Trace", SEP_STR);
 			break;
 		}
 
 		switch (ID_AA64DFR0_DEBUG_VER(cpu_desc[cpu].id_aa64dfr0)) {
 		case ID_AA64DFR0_DEBUG_VER_8:
 			printf("%sDebug v8", SEP_STR);
 			break;
 		case ID_AA64DFR0_DEBUG_VER_8_VHE:
 			printf("%sDebug v8+VHE", SEP_STR);
 			break;
 		case ID_AA64DFR0_DEBUG_VER_8_2:
 			printf("%sDebug v8.2", SEP_STR);
 			break;
 		default:
 			printf("%sUnknown Debug", SEP_STR);
 			break;
 		}
 
 		if (cpu_desc[cpu].id_aa64dfr0 & ~ID_AA64DFR0_MASK)
 			printf("%s%#lx", SEP_STR,
 			    cpu_desc[cpu].id_aa64dfr0 & ~ID_AA64DFR0_MASK);
 		printf(">\n");
 	}
 
 	/* AArch64 Memory Model Feature Register 1 */
 	if (cpu == 0 || (cpu_print_regs & PRINT_ID_AA64_DFR1) != 0) {
 		printf("             Debug Features 1 = <%#lx>\n",
 		    cpu_desc[cpu].id_aa64dfr1);
 	}
 
 	/* AArch64 Auxiliary Feature Register 0 */
 	if (cpu == 0 || (cpu_print_regs & PRINT_ID_AA64_AFR0) != 0) {
 		printf("         Auxiliary Features 0 = <%#lx>\n",
 		    cpu_desc[cpu].id_aa64afr0);
 	}
 
 	/* AArch64 Auxiliary Feature Register 1 */
 	if (cpu == 0 || (cpu_print_regs & PRINT_ID_AA64_AFR1) != 0) {
 		printf("         Auxiliary Features 1 = <%#lx>\n",
 		    cpu_desc[cpu].id_aa64afr1);
 	}
 
 #undef SEP_STR
 }
 
 void
 identify_cpu(void)
 {
 	u_int midr;
 	u_int impl_id;
 	u_int part_id;
 	u_int cpu;
 	size_t i;
 	const struct cpu_parts *cpu_partsp = NULL;
 
 	cpu = PCPU_GET(cpuid);
 	midr = get_midr();
 
 	/*
 	 * Store midr to pcpu to allow fast reading
 	 * from EL0, EL1 and assembly code.
 	 */
 	PCPU_SET(midr, midr);
 
 	impl_id = CPU_IMPL(midr);
 	for (i = 0; i < nitems(cpu_implementers); i++) {
 		if (impl_id == cpu_implementers[i].impl_id ||
 		    cpu_implementers[i].impl_id == 0) {
 			cpu_desc[cpu].cpu_impl = impl_id;
 			cpu_desc[cpu].cpu_impl_name = cpu_implementers[i].impl_name;
 			cpu_partsp = cpu_implementers[i].cpu_parts;
 			break;
 		}
 	}
 
 	part_id = CPU_PART(midr);
 	for (i = 0; &cpu_partsp[i] != NULL; i++) {
 		if (part_id == cpu_partsp[i].part_id ||
 		    cpu_partsp[i].part_id == 0) {
 			cpu_desc[cpu].cpu_part_num = part_id;
 			cpu_desc[cpu].cpu_part_name = cpu_partsp[i].part_name;
 			break;
 		}
 	}
 
 	cpu_desc[cpu].cpu_revision = CPU_REV(midr);
 	cpu_desc[cpu].cpu_variant = CPU_VAR(midr);
 
 	/* Save affinity for current CPU */
 	cpu_desc[cpu].mpidr = get_mpidr();
 	CPU_AFFINITY(cpu) = cpu_desc[cpu].mpidr & CPU_AFF_MASK;
 
 	cpu_desc[cpu].id_aa64dfr0 = READ_SPECIALREG(ID_AA64DFR0_EL1);
 	cpu_desc[cpu].id_aa64dfr1 = READ_SPECIALREG(ID_AA64DFR1_EL1);
 	cpu_desc[cpu].id_aa64isar0 = READ_SPECIALREG(ID_AA64ISAR0_EL1);
 	cpu_desc[cpu].id_aa64isar1 = READ_SPECIALREG(ID_AA64ISAR1_EL1);
 	cpu_desc[cpu].id_aa64mmfr0 = READ_SPECIALREG(ID_AA64MMFR0_EL1);
 	cpu_desc[cpu].id_aa64mmfr1 = READ_SPECIALREG(ID_AA64MMFR1_EL1);
-#ifdef NOTYET
 	cpu_desc[cpu].id_aa64mmfr2 = READ_SPECIALREG(ID_AA64MMFR2_EL1);
-#else
-	cpu_desc[cpu].id_aa64mmfr2 = 0;
-#endif
 	cpu_desc[cpu].id_aa64pfr0 = READ_SPECIALREG(ID_AA64PFR0_EL1);
 	cpu_desc[cpu].id_aa64pfr1 = READ_SPECIALREG(ID_AA64PFR1_EL1);
 
 	if (cpu != 0) {
 		/*
 		 * This code must run on one cpu at a time, but we are
 		 * not scheduling on the current core so implement a
 		 * simple spinlock.
 		 */
 		while (atomic_cmpset_acq_int(&ident_lock, 0, 1) == 0)
 			__asm __volatile("wfe" ::: "memory");
 
 		switch (cpu_aff_levels) {
 		case 0:
 			if (CPU_AFF0(cpu_desc[cpu].mpidr) !=
 			    CPU_AFF0(cpu_desc[0].mpidr))
 				cpu_aff_levels = 1;
 			/* FALLTHROUGH */
 		case 1:
 			if (CPU_AFF1(cpu_desc[cpu].mpidr) !=
 			    CPU_AFF1(cpu_desc[0].mpidr))
 				cpu_aff_levels = 2;
 			/* FALLTHROUGH */
 		case 2:
 			if (CPU_AFF2(cpu_desc[cpu].mpidr) !=
 			    CPU_AFF2(cpu_desc[0].mpidr))
 				cpu_aff_levels = 3;
 			/* FALLTHROUGH */
 		case 3:
 			if (CPU_AFF3(cpu_desc[cpu].mpidr) !=
 			    CPU_AFF3(cpu_desc[0].mpidr))
 				cpu_aff_levels = 4;
 			break;
 		}
 
 		if (cpu_desc[cpu].id_aa64afr0 != cpu_desc[0].id_aa64afr0)
 			cpu_print_regs |= PRINT_ID_AA64_AFR0;
 		if (cpu_desc[cpu].id_aa64afr1 != cpu_desc[0].id_aa64afr1)
 			cpu_print_regs |= PRINT_ID_AA64_AFR1;
 
 		if (cpu_desc[cpu].id_aa64dfr0 != cpu_desc[0].id_aa64dfr0)
 			cpu_print_regs |= PRINT_ID_AA64_DFR0;
 		if (cpu_desc[cpu].id_aa64dfr1 != cpu_desc[0].id_aa64dfr1)
 			cpu_print_regs |= PRINT_ID_AA64_DFR1;
 
 		if (cpu_desc[cpu].id_aa64isar0 != cpu_desc[0].id_aa64isar0)
 			cpu_print_regs |= PRINT_ID_AA64_ISAR0;
 		if (cpu_desc[cpu].id_aa64isar1 != cpu_desc[0].id_aa64isar1)
 			cpu_print_regs |= PRINT_ID_AA64_ISAR1;
 
 		if (cpu_desc[cpu].id_aa64mmfr0 != cpu_desc[0].id_aa64mmfr0)
 			cpu_print_regs |= PRINT_ID_AA64_MMFR0;
 		if (cpu_desc[cpu].id_aa64mmfr1 != cpu_desc[0].id_aa64mmfr1)
 			cpu_print_regs |= PRINT_ID_AA64_MMFR1;
 		if (cpu_desc[cpu].id_aa64mmfr2 != cpu_desc[0].id_aa64mmfr2)
 			cpu_print_regs |= PRINT_ID_AA64_MMFR2;
 
 		if (cpu_desc[cpu].id_aa64pfr0 != cpu_desc[0].id_aa64pfr0)
 			cpu_print_regs |= PRINT_ID_AA64_PFR0;
 		if (cpu_desc[cpu].id_aa64pfr1 != cpu_desc[0].id_aa64pfr1)
 			cpu_print_regs |= PRINT_ID_AA64_PFR1;
 
 		/* Wake up the other CPUs */
 		atomic_store_rel_int(&ident_lock, 0);
 		__asm __volatile("sev" ::: "memory");
 	}
 }
Index: head/sys/arm64/arm64/machdep.c
===================================================================
--- head/sys/arm64/arm64/machdep.c	(revision 323592)
+++ head/sys/arm64/arm64/machdep.c	(revision 323593)
@@ -1,1170 +1,1172 @@
 /*-
  * Copyright (c) 2014 Andrew Turner
  * All rights reserved.
  *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions
  * are met:
  * 1. Redistributions of source code must retain the above copyright
  *    notice, this list of conditions and the following disclaimer.
  * 2. Redistributions in binary form must reproduce the above copyright
  *    notice, this list of conditions and the following disclaimer in the
  *    documentation and/or other materials provided with the distribution.
  *
  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  * SUCH DAMAGE.
  *
  */
 
 #include "opt_acpi.h"
 #include "opt_platform.h"
 #include "opt_ddb.h"
 
 #include <sys/cdefs.h>
 __FBSDID("$FreeBSD$");
 
 #include <sys/param.h>
 #include <sys/systm.h>
 #include <sys/buf.h>
 #include <sys/bus.h>
 #include <sys/cons.h>
 #include <sys/cpu.h>
 #include <sys/devmap.h>
 #include <sys/efi.h>
 #include <sys/exec.h>
 #include <sys/imgact.h>
 #include <sys/kdb.h> 
 #include <sys/kernel.h>
 #include <sys/limits.h>
 #include <sys/linker.h>
 #include <sys/msgbuf.h>
 #include <sys/pcpu.h>
 #include <sys/proc.h>
 #include <sys/ptrace.h>
 #include <sys/reboot.h>
 #include <sys/rwlock.h>
 #include <sys/sched.h>
 #include <sys/signalvar.h>
 #include <sys/syscallsubr.h>
 #include <sys/sysent.h>
 #include <sys/sysproto.h>
 #include <sys/ucontext.h>
 #include <sys/vdso.h>
 
 #include <vm/vm.h>
 #include <vm/vm_kern.h>
 #include <vm/vm_object.h>
 #include <vm/vm_page.h>
 #include <vm/pmap.h>
 #include <vm/vm_map.h>
 #include <vm/vm_pager.h>
 
 #include <machine/armreg.h>
 #include <machine/cpu.h>
 #include <machine/debug_monitor.h>
 #include <machine/kdb.h>
 #include <machine/machdep.h>
 #include <machine/metadata.h>
 #include <machine/md_var.h>
 #include <machine/pcb.h>
 #include <machine/reg.h>
+#include <machine/undefined.h>
 #include <machine/vmparam.h>
 
 #ifdef VFP
 #include <machine/vfp.h>
 #endif
 
 #ifdef DEV_ACPI
 #include <contrib/dev/acpica/include/acpi.h>
 #include <machine/acpica_machdep.h>
 #endif
 
 #ifdef FDT
 #include <dev/fdt/fdt_common.h>
 #include <dev/ofw/openfirm.h>
 #endif
 
 
 enum arm64_bus arm64_bus_method = ARM64_BUS_NONE;
 
 struct pcpu __pcpu[MAXCPU];
 
 static struct trapframe proc0_tf;
 
 vm_paddr_t phys_avail[PHYS_AVAIL_SIZE + 2];
 vm_paddr_t dump_avail[PHYS_AVAIL_SIZE + 2];
 
 int early_boot = 1;
 int cold = 1;
 long realmem = 0;
 long Maxmem = 0;
 
 #define	PHYSMAP_SIZE	(2 * (VM_PHYSSEG_MAX - 1))
 vm_paddr_t physmap[PHYSMAP_SIZE];
 u_int physmap_idx;
 
 struct kva_md_info kmi;
 
 int64_t dcache_line_size;	/* The minimum D cache line size */
 int64_t icache_line_size;	/* The minimum I cache line size */
 int64_t idcache_line_size;	/* The minimum cache line size */
 int64_t dczva_line_size;	/* The size of cache line the dc zva zeroes */
 int has_pan;
 
 /* pagezero_* implementations are provided in support.S */
 void pagezero_simple(void *);
 void pagezero_cache(void *);
 
 /* pagezero_simple is default pagezero */
 void (*pagezero)(void *p) = pagezero_simple;
 
 static void
 pan_setup(void)
 {
 	uint64_t id_aa64mfr1;
 
 	id_aa64mfr1 = READ_SPECIALREG(id_aa64mmfr1_el1);
 	if (ID_AA64MMFR1_PAN(id_aa64mfr1) != ID_AA64MMFR1_PAN_NONE)
 		has_pan = 1;
 }
 
 void
 pan_enable(void)
 {
 
 	/*
 	 * The LLVM integrated assembler doesn't understand the PAN
 	 * PSTATE field. Because of this we need to manually create
 	 * the instruction in an asm block. This is equivalent to:
 	 * msr pan, #1
 	 *
 	 * This sets the PAN bit, stopping the kernel from accessing
 	 * memory when userspace can also access it unless the kernel
 	 * uses the userspace load/store instructions.
 	 */
 	if (has_pan) {
 		WRITE_SPECIALREG(sctlr_el1,
 		    READ_SPECIALREG(sctlr_el1) & ~SCTLR_SPAN);
 		__asm __volatile(".inst 0xd500409f | (0x1 << 8)");
 	}
 }
 
 static void
 cpu_startup(void *dummy)
 {
 
+	undef_init();
 	identify_cpu();
 
 	vm_ksubmap_init(&kmi);
 	bufinit();
 	vm_pager_bufferinit();
 }
 
 SYSINIT(cpu, SI_SUB_CPU, SI_ORDER_FIRST, cpu_startup, NULL);
 
 int
 cpu_idle_wakeup(int cpu)
 {
 
 	return (0);
 }
 
 int
 fill_regs(struct thread *td, struct reg *regs)
 {
 	struct trapframe *frame;
 
 	frame = td->td_frame;
 	regs->sp = frame->tf_sp;
 	regs->lr = frame->tf_lr;
 	regs->elr = frame->tf_elr;
 	regs->spsr = frame->tf_spsr;
 
 	memcpy(regs->x, frame->tf_x, sizeof(regs->x));
 
 	return (0);
 }
 
 int
 set_regs(struct thread *td, struct reg *regs)
 {
 	struct trapframe *frame;
 
 	frame = td->td_frame;
 	frame->tf_sp = regs->sp;
 	frame->tf_lr = regs->lr;
 	frame->tf_elr = regs->elr;
 	frame->tf_spsr = regs->spsr;
 
 	memcpy(frame->tf_x, regs->x, sizeof(frame->tf_x));
 
 	return (0);
 }
 
 int
 fill_fpregs(struct thread *td, struct fpreg *regs)
 {
 #ifdef VFP
 	struct pcb *pcb;
 
 	pcb = td->td_pcb;
 	if ((pcb->pcb_fpflags & PCB_FP_STARTED) != 0) {
 		/*
 		 * If we have just been running VFP instructions we will
 		 * need to save the state to memcpy it below.
 		 */
 		if (td == curthread)
 			vfp_save_state(td, pcb);
 
 		KASSERT(pcb->pcb_fpusaved == &pcb->pcb_fpustate,
 		    ("Called fill_fpregs while the kernel is using the VFP"));
 		memcpy(regs->fp_q, pcb->pcb_fpustate.vfp_regs,
 		    sizeof(regs->fp_q));
 		regs->fp_cr = pcb->pcb_fpustate.vfp_fpcr;
 		regs->fp_sr = pcb->pcb_fpustate.vfp_fpsr;
 	} else
 #endif
 		memset(regs->fp_q, 0, sizeof(regs->fp_q));
 	return (0);
 }
 
 int
 set_fpregs(struct thread *td, struct fpreg *regs)
 {
 #ifdef VFP
 	struct pcb *pcb;
 
 	pcb = td->td_pcb;
 	KASSERT(pcb->pcb_fpusaved == &pcb->pcb_fpustate,
 	    ("Called set_fpregs while the kernel is using the VFP"));
 	memcpy(pcb->pcb_fpustate.vfp_regs, regs->fp_q, sizeof(regs->fp_q));
 	pcb->pcb_fpustate.vfp_fpcr = regs->fp_cr;
 	pcb->pcb_fpustate.vfp_fpsr = regs->fp_sr;
 #endif
 	return (0);
 }
 
 int
 fill_dbregs(struct thread *td, struct dbreg *regs)
 {
 
 	printf("ARM64TODO: fill_dbregs");
 	return (EDOOFUS);
 }
 
 int
 set_dbregs(struct thread *td, struct dbreg *regs)
 {
 
 	printf("ARM64TODO: set_dbregs");
 	return (EDOOFUS);
 }
 
 int
 ptrace_set_pc(struct thread *td, u_long addr)
 {
 
 	printf("ARM64TODO: ptrace_set_pc");
 	return (EDOOFUS);
 }
 
 int
 ptrace_single_step(struct thread *td)
 {
 
 	td->td_frame->tf_spsr |= PSR_SS;
 	td->td_pcb->pcb_flags |= PCB_SINGLE_STEP;
 	return (0);
 }
 
 int
 ptrace_clear_single_step(struct thread *td)
 {
 
 	td->td_frame->tf_spsr &= ~PSR_SS;
 	td->td_pcb->pcb_flags &= ~PCB_SINGLE_STEP;
 	return (0);
 }
 
 void
 exec_setregs(struct thread *td, struct image_params *imgp, u_long stack)
 {
 	struct trapframe *tf = td->td_frame;
 
 	memset(tf, 0, sizeof(struct trapframe));
 
 	/*
 	 * We need to set x0 for init as it doesn't call
 	 * cpu_set_syscall_retval to copy the value. We also
 	 * need to set td_retval for the cases where we do.
 	 */
 	tf->tf_x[0] = td->td_retval[0] = stack;
 	tf->tf_sp = STACKALIGN(stack);
 	tf->tf_lr = imgp->entry_addr;
 	tf->tf_elr = imgp->entry_addr;
 }
 
 /* Sanity check these are the same size, they will be memcpy'd to and fro */
 CTASSERT(sizeof(((struct trapframe *)0)->tf_x) ==
     sizeof((struct gpregs *)0)->gp_x);
 CTASSERT(sizeof(((struct trapframe *)0)->tf_x) ==
     sizeof((struct reg *)0)->x);
 
 int
 get_mcontext(struct thread *td, mcontext_t *mcp, int clear_ret)
 {
 	struct trapframe *tf = td->td_frame;
 
 	if (clear_ret & GET_MC_CLEAR_RET) {
 		mcp->mc_gpregs.gp_x[0] = 0;
 		mcp->mc_gpregs.gp_spsr = tf->tf_spsr & ~PSR_C;
 	} else {
 		mcp->mc_gpregs.gp_x[0] = tf->tf_x[0];
 		mcp->mc_gpregs.gp_spsr = tf->tf_spsr;
 	}
 
 	memcpy(&mcp->mc_gpregs.gp_x[1], &tf->tf_x[1],
 	    sizeof(mcp->mc_gpregs.gp_x[1]) * (nitems(mcp->mc_gpregs.gp_x) - 1));
 
 	mcp->mc_gpregs.gp_sp = tf->tf_sp;
 	mcp->mc_gpregs.gp_lr = tf->tf_lr;
 	mcp->mc_gpregs.gp_elr = tf->tf_elr;
 
 	return (0);
 }
 
 int
 set_mcontext(struct thread *td, mcontext_t *mcp)
 {
 	struct trapframe *tf = td->td_frame;
 
 	memcpy(tf->tf_x, mcp->mc_gpregs.gp_x, sizeof(tf->tf_x));
 
 	tf->tf_sp = mcp->mc_gpregs.gp_sp;
 	tf->tf_lr = mcp->mc_gpregs.gp_lr;
 	tf->tf_elr = mcp->mc_gpregs.gp_elr;
 	tf->tf_spsr = mcp->mc_gpregs.gp_spsr;
 
 	return (0);
 }
 
 static void
 get_fpcontext(struct thread *td, mcontext_t *mcp)
 {
 #ifdef VFP
 	struct pcb *curpcb;
 
 	critical_enter();
 
 	curpcb = curthread->td_pcb;
 
 	if ((curpcb->pcb_fpflags & PCB_FP_STARTED) != 0) {
 		/*
 		 * If we have just been running VFP instructions we will
 		 * need to save the state to memcpy it below.
 		 */
 		vfp_save_state(td, curpcb);
 
 		KASSERT(curpcb->pcb_fpusaved == &curpcb->pcb_fpustate,
 		    ("Called get_fpcontext while the kernel is using the VFP"));
 		KASSERT((curpcb->pcb_fpflags & ~PCB_FP_USERMASK) == 0,
 		    ("Non-userspace FPU flags set in get_fpcontext"));
 		memcpy(mcp->mc_fpregs.fp_q, curpcb->pcb_fpustate.vfp_regs,
 		    sizeof(mcp->mc_fpregs));
 		mcp->mc_fpregs.fp_cr = curpcb->pcb_fpustate.vfp_fpcr;
 		mcp->mc_fpregs.fp_sr = curpcb->pcb_fpustate.vfp_fpsr;
 		mcp->mc_fpregs.fp_flags = curpcb->pcb_fpflags;
 		mcp->mc_flags |= _MC_FP_VALID;
 	}
 
 	critical_exit();
 #endif
 }
 
 static void
 set_fpcontext(struct thread *td, mcontext_t *mcp)
 {
 #ifdef VFP
 	struct pcb *curpcb;
 
 	critical_enter();
 
 	if ((mcp->mc_flags & _MC_FP_VALID) != 0) {
 		curpcb = curthread->td_pcb;
 
 		/*
 		 * Discard any vfp state for the current thread, we
 		 * are about to override it.
 		 */
 		vfp_discard(td);
 
 		KASSERT(curpcb->pcb_fpusaved == &curpcb->pcb_fpustate,
 		    ("Called set_fpcontext while the kernel is using the VFP"));
 		memcpy(curpcb->pcb_fpustate.vfp_regs, mcp->mc_fpregs.fp_q,
 		    sizeof(mcp->mc_fpregs));
 		curpcb->pcb_fpustate.vfp_fpcr = mcp->mc_fpregs.fp_cr;
 		curpcb->pcb_fpustate.vfp_fpsr = mcp->mc_fpregs.fp_sr;
 		curpcb->pcb_fpflags = mcp->mc_fpregs.fp_flags & PCB_FP_USERMASK;
 	}
 
 	critical_exit();
 #endif
 }
 
 void
 cpu_idle(int busy)
 {
 
 	spinlock_enter();
 	if (!busy)
 		cpu_idleclock();
 	if (!sched_runnable())
 		__asm __volatile(
 		    "dsb sy \n"
 		    "wfi    \n");
 	if (!busy)
 		cpu_activeclock();
 	spinlock_exit();
 }
 
 void
 cpu_halt(void)
 {
 
 	/* We should have shutdown by now, if not enter a low power sleep */
 	intr_disable();
 	while (1) {
 		__asm __volatile("wfi");
 	}
 }
 
 /*
  * Flush the D-cache for non-DMA I/O so that the I-cache can
  * be made coherent later.
  */
 void
 cpu_flush_dcache(void *ptr, size_t len)
 {
 
 	/* ARM64TODO TBD */
 }
 
 /* Get current clock frequency for the given CPU ID. */
 int
 cpu_est_clockrate(int cpu_id, uint64_t *rate)
 {
 	struct pcpu *pc;
 
 	pc = pcpu_find(cpu_id);
 	if (pc == NULL || rate == NULL)
 		return (EINVAL);
 
 	if (pc->pc_clock == 0)
 		return (EOPNOTSUPP);
 
 	*rate = pc->pc_clock;
 	return (0);
 }
 
 void
 cpu_pcpu_init(struct pcpu *pcpu, int cpuid, size_t size)
 {
 
 	pcpu->pc_acpi_id = 0xffffffff;
 }
 
 void
 spinlock_enter(void)
 {
 	struct thread *td;
 	register_t daif;
 
 	td = curthread;
 	if (td->td_md.md_spinlock_count == 0) {
 		daif = intr_disable();
 		td->td_md.md_spinlock_count = 1;
 		td->td_md.md_saved_daif = daif;
 	} else
 		td->td_md.md_spinlock_count++;
 	critical_enter();
 }
 
 void
 spinlock_exit(void)
 {
 	struct thread *td;
 	register_t daif;
 
 	td = curthread;
 	critical_exit();
 	daif = td->td_md.md_saved_daif;
 	td->td_md.md_spinlock_count--;
 	if (td->td_md.md_spinlock_count == 0)
 		intr_restore(daif);
 }
 
 #ifndef	_SYS_SYSPROTO_H_
 struct sigreturn_args {
 	ucontext_t *ucp;
 };
 #endif
 
 int
 sys_sigreturn(struct thread *td, struct sigreturn_args *uap)
 {
 	ucontext_t uc;
 	uint32_t spsr;
 
 	if (uap == NULL)
 		return (EFAULT);
 	if (copyin(uap->sigcntxp, &uc, sizeof(uc)))
 		return (EFAULT);
 
 	spsr = uc.uc_mcontext.mc_gpregs.gp_spsr;
 	if ((spsr & PSR_M_MASK) != PSR_M_EL0t ||
 	    (spsr & (PSR_F | PSR_I | PSR_A | PSR_D)) != 0)
 		return (EINVAL); 
 
 	set_mcontext(td, &uc.uc_mcontext);
 	set_fpcontext(td, &uc.uc_mcontext);
 
 	/* Restore signal mask. */
 	kern_sigprocmask(td, SIG_SETMASK, &uc.uc_sigmask, NULL, 0);
 
 	return (EJUSTRETURN);
 }
 
 /*
  * Construct a PCB from a trapframe. This is called from kdb_trap() where
  * we want to start a backtrace from the function that caused us to enter
  * the debugger. We have the context in the trapframe, but base the trace
  * on the PCB. The PCB doesn't have to be perfect, as long as it contains
  * enough for a backtrace.
  */
 void
 makectx(struct trapframe *tf, struct pcb *pcb)
 {
 	int i;
 
 	for (i = 0; i < PCB_LR; i++)
 		pcb->pcb_x[i] = tf->tf_x[i];
 
 	pcb->pcb_x[PCB_LR] = tf->tf_lr;
 	pcb->pcb_pc = tf->tf_elr;
 	pcb->pcb_sp = tf->tf_sp;
 }
 
 void
 sendsig(sig_t catcher, ksiginfo_t *ksi, sigset_t *mask)
 {
 	struct thread *td;
 	struct proc *p;
 	struct trapframe *tf;
 	struct sigframe *fp, frame;
 	struct sigacts *psp;
 	struct sysentvec *sysent;
 	int code, onstack, sig;
 
 	td = curthread;
 	p = td->td_proc;
 	PROC_LOCK_ASSERT(p, MA_OWNED);
 
 	sig = ksi->ksi_signo;
 	code = ksi->ksi_code;
 	psp = p->p_sigacts;
 	mtx_assert(&psp->ps_mtx, MA_OWNED);
 
 	tf = td->td_frame;
 	onstack = sigonstack(tf->tf_sp);
 
 	CTR4(KTR_SIG, "sendsig: td=%p (%s) catcher=%p sig=%d", td, p->p_comm,
 	    catcher, sig);
 
 	/* Allocate and validate space for the signal handler context. */
 	if ((td->td_pflags & TDP_ALTSTACK) != 0 && !onstack &&
 	    SIGISMEMBER(psp->ps_sigonstack, sig)) {
 		fp = (struct sigframe *)((uintptr_t)td->td_sigstk.ss_sp +
 		    td->td_sigstk.ss_size);
 #if defined(COMPAT_43)
 		td->td_sigstk.ss_flags |= SS_ONSTACK;
 #endif
 	} else {
 		fp = (struct sigframe *)td->td_frame->tf_sp;
 	}
 
 	/* Make room, keeping the stack aligned */
 	fp--;
 	fp = (struct sigframe *)STACKALIGN(fp);
 
 	/* Fill in the frame to copy out */
 	get_mcontext(td, &frame.sf_uc.uc_mcontext, 0);
 	get_fpcontext(td, &frame.sf_uc.uc_mcontext);
 	frame.sf_si = ksi->ksi_info;
 	frame.sf_uc.uc_sigmask = *mask;
 	frame.sf_uc.uc_stack.ss_flags = (td->td_pflags & TDP_ALTSTACK) ?
 	    ((onstack) ? SS_ONSTACK : 0) : SS_DISABLE;
 	frame.sf_uc.uc_stack = td->td_sigstk;
 	mtx_unlock(&psp->ps_mtx);
 	PROC_UNLOCK(td->td_proc);
 
 	/* Copy the sigframe out to the user's stack. */
 	if (copyout(&frame, fp, sizeof(*fp)) != 0) {
 		/* Process has trashed its stack. Kill it. */
 		CTR2(KTR_SIG, "sendsig: sigexit td=%p fp=%p", td, fp);
 		PROC_LOCK(p);
 		sigexit(td, SIGILL);
 	}
 
 	tf->tf_x[0]= sig;
 	tf->tf_x[1] = (register_t)&fp->sf_si;
 	tf->tf_x[2] = (register_t)&fp->sf_uc;
 
 	tf->tf_elr = (register_t)catcher;
 	tf->tf_sp = (register_t)fp;
 	sysent = p->p_sysent;
 	if (sysent->sv_sigcode_base != 0)
 		tf->tf_lr = (register_t)sysent->sv_sigcode_base;
 	else
 		tf->tf_lr = (register_t)(sysent->sv_psstrings -
 		    *(sysent->sv_szsigcode));
 
 	CTR3(KTR_SIG, "sendsig: return td=%p pc=%#x sp=%#x", td, tf->tf_elr,
 	    tf->tf_sp);
 
 	PROC_LOCK(p);
 	mtx_lock(&psp->ps_mtx);
 }
 
 static void
 init_proc0(vm_offset_t kstack)
 {
 	struct pcpu *pcpup = &__pcpu[0];
 
 	proc_linkup0(&proc0, &thread0);
 	thread0.td_kstack = kstack;
 	thread0.td_pcb = (struct pcb *)(thread0.td_kstack) - 1;
 	thread0.td_pcb->pcb_fpflags = 0;
 	thread0.td_pcb->pcb_fpusaved = &thread0.td_pcb->pcb_fpustate;
 	thread0.td_pcb->pcb_vfpcpu = UINT_MAX;
 	thread0.td_frame = &proc0_tf;
 	pcpup->pc_curpcb = thread0.td_pcb;
 }
 
 typedef struct {
 	uint32_t type;
 	uint64_t phys_start;
 	uint64_t virt_start;
 	uint64_t num_pages;
 	uint64_t attr;
 } EFI_MEMORY_DESCRIPTOR;
 
 static int
 add_physmap_entry(uint64_t base, uint64_t length, vm_paddr_t *physmap,
     u_int *physmap_idxp)
 {
 	u_int i, insert_idx, _physmap_idx;
 
 	_physmap_idx = *physmap_idxp;
 
 	if (length == 0)
 		return (1);
 
 	/*
 	 * Find insertion point while checking for overlap.  Start off by
 	 * assuming the new entry will be added to the end.
 	 */
 	insert_idx = _physmap_idx;
 	for (i = 0; i <= _physmap_idx; i += 2) {
 		if (base < physmap[i + 1]) {
 			if (base + length <= physmap[i]) {
 				insert_idx = i;
 				break;
 			}
 			if (boothowto & RB_VERBOSE)
 				printf(
 		    "Overlapping memory regions, ignoring second region\n");
 			return (1);
 		}
 	}
 
 	/* See if we can prepend to the next entry. */
 	if (insert_idx <= _physmap_idx &&
 	    base + length == physmap[insert_idx]) {
 		physmap[insert_idx] = base;
 		return (1);
 	}
 
 	/* See if we can append to the previous entry. */
 	if (insert_idx > 0 && base == physmap[insert_idx - 1]) {
 		physmap[insert_idx - 1] += length;
 		return (1);
 	}
 
 	_physmap_idx += 2;
 	*physmap_idxp = _physmap_idx;
 	if (_physmap_idx == PHYSMAP_SIZE) {
 		printf(
 		"Too many segments in the physical address map, giving up\n");
 		return (0);
 	}
 
 	/*
 	 * Move the last 'N' entries down to make room for the new
 	 * entry if needed.
 	 */
 	for (i = _physmap_idx; i > insert_idx; i -= 2) {
 		physmap[i] = physmap[i - 2];
 		physmap[i + 1] = physmap[i - 1];
 	}
 
 	/* Insert the new entry. */
 	physmap[insert_idx] = base;
 	physmap[insert_idx + 1] = base + length;
 	return (1);
 }
 
 #ifdef FDT
 static void
 add_fdt_mem_regions(struct mem_region *mr, int mrcnt, vm_paddr_t *physmap,
     u_int *physmap_idxp)
 {
 
 	for (int i = 0; i < mrcnt; i++) {
 		if (!add_physmap_entry(mr[i].mr_start, mr[i].mr_size, physmap,
 		    physmap_idxp))
 			break;
 	}
 }
 #endif
 
 static void
 add_efi_map_entries(struct efi_map_header *efihdr, vm_paddr_t *physmap,
     u_int *physmap_idxp)
 {
 	struct efi_md *map, *p;
 	const char *type;
 	size_t efisz;
 	int ndesc, i;
 
 	static const char *types[] = {
 		"Reserved",
 		"LoaderCode",
 		"LoaderData",
 		"BootServicesCode",
 		"BootServicesData",
 		"RuntimeServicesCode",
 		"RuntimeServicesData",
 		"ConventionalMemory",
 		"UnusableMemory",
 		"ACPIReclaimMemory",
 		"ACPIMemoryNVS",
 		"MemoryMappedIO",
 		"MemoryMappedIOPortSpace",
 		"PalCode",
 		"PersistentMemory"
 	};
 
 	/*
 	 * Memory map data provided by UEFI via the GetMemoryMap
 	 * Boot Services API.
 	 */
 	efisz = (sizeof(struct efi_map_header) + 0xf) & ~0xf;
 	map = (struct efi_md *)((uint8_t *)efihdr + efisz); 
 
 	if (efihdr->descriptor_size == 0)
 		return;
 	ndesc = efihdr->memory_size / efihdr->descriptor_size;
 
 	if (boothowto & RB_VERBOSE)
 		printf("%23s %12s %12s %8s %4s\n",
 		    "Type", "Physical", "Virtual", "#Pages", "Attr");
 
 	for (i = 0, p = map; i < ndesc; i++,
 	    p = efi_next_descriptor(p, efihdr->descriptor_size)) {
 		if (boothowto & RB_VERBOSE) {
 			if (p->md_type < nitems(types))
 				type = types[p->md_type];
 			else
 				type = "<INVALID>";
 			printf("%23s %012lx %12p %08lx ", type, p->md_phys,
 			    p->md_virt, p->md_pages);
 			if (p->md_attr & EFI_MD_ATTR_UC)
 				printf("UC ");
 			if (p->md_attr & EFI_MD_ATTR_WC)
 				printf("WC ");
 			if (p->md_attr & EFI_MD_ATTR_WT)
 				printf("WT ");
 			if (p->md_attr & EFI_MD_ATTR_WB)
 				printf("WB ");
 			if (p->md_attr & EFI_MD_ATTR_UCE)
 				printf("UCE ");
 			if (p->md_attr & EFI_MD_ATTR_WP)
 				printf("WP ");
 			if (p->md_attr & EFI_MD_ATTR_RP)
 				printf("RP ");
 			if (p->md_attr & EFI_MD_ATTR_XP)
 				printf("XP ");
 			if (p->md_attr & EFI_MD_ATTR_NV)
 				printf("NV ");
 			if (p->md_attr & EFI_MD_ATTR_MORE_RELIABLE)
 				printf("MORE_RELIABLE ");
 			if (p->md_attr & EFI_MD_ATTR_RO)
 				printf("RO ");
 			if (p->md_attr & EFI_MD_ATTR_RT)
 				printf("RUNTIME");
 			printf("\n");
 		}
 
 		switch (p->md_type) {
 		case EFI_MD_TYPE_CODE:
 		case EFI_MD_TYPE_DATA:
 		case EFI_MD_TYPE_BS_CODE:
 		case EFI_MD_TYPE_BS_DATA:
 		case EFI_MD_TYPE_FREE:
 			/*
 			 * We're allowed to use any entry with these types.
 			 */
 			break;
 		default:
 			continue;
 		}
 
 		if (!add_physmap_entry(p->md_phys, (p->md_pages * PAGE_SIZE),
 		    physmap, physmap_idxp))
 			break;
 	}
 }
 
 #ifdef FDT
 static void
 try_load_dtb(caddr_t kmdp)
 {
 	vm_offset_t dtbp;
 
 	dtbp = MD_FETCH(kmdp, MODINFOMD_DTBP, vm_offset_t);
 	if (dtbp == (vm_offset_t)NULL) {
 		printf("ERROR loading DTB\n");
 		return;
 	}
 
 	if (OF_install(OFW_FDT, 0) == FALSE)
 		panic("Cannot install FDT");
 
 	if (OF_init((void *)dtbp) != 0)
 		panic("OF_init failed with the found device tree");
 }
 #endif
 
 static bool
 bus_probe(void)
 {
 	bool has_acpi, has_fdt;
 	char *order, *env;
 
 	has_acpi = has_fdt = false;
 
 #ifdef FDT
 	has_fdt = (OF_peer(0) != 0);
 #endif
 #ifdef DEV_ACPI
 	has_acpi = (acpi_find_table(ACPI_SIG_SPCR) != 0);
 #endif
 
 	env = kern_getenv("kern.cfg.order");
 	if (env != NULL) {
 		order = env;
 		while (order != NULL) {
 			if (has_acpi &&
 			    strncmp(order, "acpi", 4) == 0 &&
 			    (order[4] == ',' || order[4] == '\0')) {
 				arm64_bus_method = ARM64_BUS_ACPI;
 				break;
 			}
 			if (has_fdt &&
 			    strncmp(order, "fdt", 3) == 0 &&
 			    (order[3] == ',' || order[3] == '\0')) {
 				arm64_bus_method = ARM64_BUS_FDT;
 				break;
 			}
 			order = strchr(order, ',');
 		}
 		freeenv(env);
 
 		/* If we set the bus method it is valid */
 		if (arm64_bus_method != ARM64_BUS_NONE)
 			return (true);
 	}
 	/* If no order or an invalid order was set use the default */
 	if (arm64_bus_method == ARM64_BUS_NONE) {
 		if (has_fdt)
 			arm64_bus_method = ARM64_BUS_FDT;
 		else if (has_acpi)
 			arm64_bus_method = ARM64_BUS_ACPI;
 	}
 
 	/*
 	 * If no option was set the default is valid, otherwise we are
 	 * setting one to get cninit() working, then calling panic to tell
 	 * the user about the invalid bus setup.
 	 */
 	return (env == NULL);
 }
 
 static void
 cache_setup(void)
 {
 	int dcache_line_shift, icache_line_shift, dczva_line_shift;
 	uint32_t ctr_el0;
 	uint32_t dczid_el0;
 
 	ctr_el0 = READ_SPECIALREG(ctr_el0);
 
 	/* Read the log2 words in each D cache line */
 	dcache_line_shift = CTR_DLINE_SIZE(ctr_el0);
 	/* Get the D cache line size */
 	dcache_line_size = sizeof(int) << dcache_line_shift;
 
 	/* And the same for the I cache */
 	icache_line_shift = CTR_ILINE_SIZE(ctr_el0);
 	icache_line_size = sizeof(int) << icache_line_shift;
 
 	idcache_line_size = MIN(dcache_line_size, icache_line_size);
 
 	dczid_el0 = READ_SPECIALREG(dczid_el0);
 
 	/* Check if dc zva is not prohibited */
 	if (dczid_el0 & DCZID_DZP)
 		dczva_line_size = 0;
 	else {
 		/* Same as with above calculations */
 		dczva_line_shift = DCZID_BS_SIZE(dczid_el0);
 		dczva_line_size = sizeof(int) << dczva_line_shift;
 
 		/* Change pagezero function */
 		pagezero = pagezero_cache;
 	}
 }
 
 void
 initarm(struct arm64_bootparams *abp)
 {
 	struct efi_map_header *efihdr;
 	struct pcpu *pcpup;
 #ifdef FDT
 	struct mem_region mem_regions[FDT_MEM_REGIONS];
 	int mem_regions_sz;
 #endif
 	vm_offset_t lastaddr;
 	caddr_t kmdp;
 	vm_paddr_t mem_len;
 	bool valid;
 	int i;
 
 	/* Set the module data location */
 	preload_metadata = (caddr_t)(uintptr_t)(abp->modulep);
 
 	/* Find the kernel address */
 	kmdp = preload_search_by_type("elf kernel");
 	if (kmdp == NULL)
 		kmdp = preload_search_by_type("elf64 kernel");
 
 	boothowto = MD_FETCH(kmdp, MODINFOMD_HOWTO, int);
 	init_static_kenv(MD_FETCH(kmdp, MODINFOMD_ENVP, char *), 0);
 
 #ifdef FDT
 	try_load_dtb(kmdp);
 #endif
 
 	/* Find the address to start allocating from */
 	lastaddr = MD_FETCH(kmdp, MODINFOMD_KERNEND, vm_offset_t);
 
 	/* Load the physical memory ranges */
 	physmap_idx = 0;
 	efihdr = (struct efi_map_header *)preload_search_info(kmdp,
 	    MODINFO_METADATA | MODINFOMD_EFI_MAP);
 	if (efihdr != NULL)
 		add_efi_map_entries(efihdr, physmap, &physmap_idx);
 #ifdef FDT
 	else {
 		/* Grab physical memory regions information from device tree. */
 		if (fdt_get_mem_regions(mem_regions, &mem_regions_sz,
 		    NULL) != 0)
 			panic("Cannot get physical memory regions");
 		add_fdt_mem_regions(mem_regions, mem_regions_sz, physmap,
 		    &physmap_idx);
 	}
 #endif
 
 	/* Print the memory map */
 	mem_len = 0;
 	for (i = 0; i < physmap_idx; i += 2) {
 		dump_avail[i] = physmap[i];
 		dump_avail[i + 1] = physmap[i + 1];
 		mem_len += physmap[i + 1] - physmap[i];
 	}
 	dump_avail[i] = 0;
 	dump_avail[i + 1] = 0;
 
 	/* Set the pcpu data, this is needed by pmap_bootstrap */
 	pcpup = &__pcpu[0];
 	pcpu_init(pcpup, 0, sizeof(struct pcpu));
 
 	/*
 	 * Set the pcpu pointer with a backup in tpidr_el1 to be
 	 * loaded when entering the kernel from userland.
 	 */
 	__asm __volatile(
 	    "mov x18, %0 \n"
 	    "msr tpidr_el1, %0" :: "r"(pcpup));
 
 	PCPU_SET(curthread, &thread0);
 
 	/* Do basic tuning, hz etc */
 	init_param1();
 
 	cache_setup();
 	pan_setup();
 
 	/* Bootstrap enough of pmap  to enter the kernel proper */
 	pmap_bootstrap(abp->kern_l0pt, abp->kern_l1pt,
 	    KERNBASE - abp->kern_delta, lastaddr - KERNBASE);
 
 	devmap_bootstrap(0, NULL);
 
 	valid = bus_probe();
 
 	cninit();
 
 	if (!valid)
 		panic("Invalid bus configuration: %s",
 		    kern_getenv("kern.cfg.order"));
 
 	init_proc0(abp->kern_stack);
 	msgbufinit(msgbufp, msgbufsize);
 	mutex_init();
 	init_param2(physmem);
 
 	dbg_init();
 	kdb_init();
 	pan_enable();
 
 	early_boot = 0;
 }
 
 void
 dbg_init(void)
 {
 
 	/* Clear OS lock */
 	WRITE_SPECIALREG(OSLAR_EL1, 0);
 
 	/* This permits DDB to use debug registers for watchpoints. */
 	dbg_monitor_init();
 
 	/* TODO: Eventually will need to initialize debug registers here. */
 }
 
 #ifdef DDB
 #include <ddb/ddb.h>
 
 DB_SHOW_COMMAND(specialregs, db_show_spregs)
 {
 #define	PRINT_REG(reg)	\
     db_printf(__STRING(reg) " = %#016lx\n", READ_SPECIALREG(reg))
 
 	PRINT_REG(actlr_el1);
 	PRINT_REG(afsr0_el1);
 	PRINT_REG(afsr1_el1);
 	PRINT_REG(aidr_el1);
 	PRINT_REG(amair_el1);
 	PRINT_REG(ccsidr_el1);
 	PRINT_REG(clidr_el1);
 	PRINT_REG(contextidr_el1);
 	PRINT_REG(cpacr_el1);
 	PRINT_REG(csselr_el1);
 	PRINT_REG(ctr_el0);
 	PRINT_REG(currentel);
 	PRINT_REG(daif);
 	PRINT_REG(dczid_el0);
 	PRINT_REG(elr_el1);
 	PRINT_REG(esr_el1);
 	PRINT_REG(far_el1);
 #if 0
 	/* ARM64TODO: Enable VFP before reading floating-point registers */
 	PRINT_REG(fpcr);
 	PRINT_REG(fpsr);
 #endif
 	PRINT_REG(id_aa64afr0_el1);
 	PRINT_REG(id_aa64afr1_el1);
 	PRINT_REG(id_aa64dfr0_el1);
 	PRINT_REG(id_aa64dfr1_el1);
 	PRINT_REG(id_aa64isar0_el1);
 	PRINT_REG(id_aa64isar1_el1);
 	PRINT_REG(id_aa64pfr0_el1);
 	PRINT_REG(id_aa64pfr1_el1);
 	PRINT_REG(id_afr0_el1);
 	PRINT_REG(id_dfr0_el1);
 	PRINT_REG(id_isar0_el1);
 	PRINT_REG(id_isar1_el1);
 	PRINT_REG(id_isar2_el1);
 	PRINT_REG(id_isar3_el1);
 	PRINT_REG(id_isar4_el1);
 	PRINT_REG(id_isar5_el1);
 	PRINT_REG(id_mmfr0_el1);
 	PRINT_REG(id_mmfr1_el1);
 	PRINT_REG(id_mmfr2_el1);
 	PRINT_REG(id_mmfr3_el1);
 #if 0
 	/* Missing from llvm */
 	PRINT_REG(id_mmfr4_el1);
 #endif
 	PRINT_REG(id_pfr0_el1);
 	PRINT_REG(id_pfr1_el1);
 	PRINT_REG(isr_el1);
 	PRINT_REG(mair_el1);
 	PRINT_REG(midr_el1);
 	PRINT_REG(mpidr_el1);
 	PRINT_REG(mvfr0_el1);
 	PRINT_REG(mvfr1_el1);
 	PRINT_REG(mvfr2_el1);
 	PRINT_REG(revidr_el1);
 	PRINT_REG(sctlr_el1);
 	PRINT_REG(sp_el0);
 	PRINT_REG(spsel);
 	PRINT_REG(spsr_el1);
 	PRINT_REG(tcr_el1);
 	PRINT_REG(tpidr_el0);
 	PRINT_REG(tpidr_el1);
 	PRINT_REG(tpidrro_el0);
 	PRINT_REG(ttbr0_el1);
 	PRINT_REG(ttbr1_el1);
 	PRINT_REG(vbar_el1);
 #undef PRINT_REG
 }
 
 DB_SHOW_COMMAND(vtop, db_show_vtop)
 {
 	uint64_t phys;
 
 	if (have_addr) {
 		phys = arm64_address_translate_s1e1r(addr);
 		db_printf("EL1 physical address reg (read):  0x%016lx\n", phys);
 		phys = arm64_address_translate_s1e1w(addr);
 		db_printf("EL1 physical address reg (write): 0x%016lx\n", phys);
 		phys = arm64_address_translate_s1e0r(addr);
 		db_printf("EL0 physical address reg (read):  0x%016lx\n", phys);
 		phys = arm64_address_translate_s1e0w(addr);
 		db_printf("EL0 physical address reg (write): 0x%016lx\n", phys);
 	} else
 		db_printf("show vtop <virt_addr>\n");
 }
 #endif
Index: head/sys/arm64/arm64/trap.c
===================================================================
--- head/sys/arm64/arm64/trap.c	(revision 323592)
+++ head/sys/arm64/arm64/trap.c	(revision 323593)
@@ -1,448 +1,441 @@
 /*-
  * Copyright (c) 2014 Andrew Turner
  * All rights reserved.
  *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions
  * are met:
  * 1. Redistributions of source code must retain the above copyright
  *    notice, this list of conditions and the following disclaimer.
  * 2. Redistributions in binary form must reproduce the above copyright
  *    notice, this list of conditions and the following disclaimer in the
  *    documentation and/or other materials provided with the distribution.
  *
  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  * SUCH DAMAGE.
  *
  */
 
 #include <sys/cdefs.h>
 __FBSDID("$FreeBSD$");
 
 #include <sys/param.h>
 #include <sys/systm.h>
 #include <sys/kernel.h>
 #include <sys/lock.h>
 #include <sys/mutex.h>
 #include <sys/pioctl.h>
 #include <sys/proc.h>
 #include <sys/ptrace.h>
 #include <sys/syscall.h>
 #include <sys/sysent.h>
 #ifdef KDB
 #include <sys/kdb.h>
 #endif
 
 #include <vm/vm.h>
 #include <vm/pmap.h>
 #include <vm/vm_kern.h>
 #include <vm/vm_map.h>
 #include <vm/vm_param.h>
 #include <vm/vm_extern.h>
 
 #include <machine/frame.h>
 #include <machine/pcb.h>
 #include <machine/pcpu.h>
+#include <machine/undefined.h>
 
 #ifdef KDTRACE_HOOKS
 #include <sys/dtrace_bsd.h>
 #endif
 
 #ifdef VFP
 #include <machine/vfp.h>
 #endif
 
 #ifdef KDB
 #include <machine/db_machdep.h>
 #endif
 
 #ifdef DDB
 #include <ddb/db_output.h>
 #endif
 
 extern register_t fsu_intr_fault;
 
 /* Called from exception.S */
 void do_el1h_sync(struct thread *, struct trapframe *);
 void do_el0_sync(struct thread *, struct trapframe *);
 void do_el0_error(struct trapframe *);
 static void print_registers(struct trapframe *frame);
 
 int (*dtrace_invop_jump_addr)(struct trapframe *);
 
 static __inline void
 call_trapsignal(struct thread *td, int sig, int code, void *addr)
 {
 	ksiginfo_t ksi;
 
 	ksiginfo_init_trap(&ksi);
 	ksi.ksi_signo = sig;
 	ksi.ksi_code = code;
 	ksi.ksi_addr = addr;
 	trapsignal(td, &ksi);
 }
 
 int
 cpu_fetch_syscall_args(struct thread *td)
 {
 	struct proc *p;
 	register_t *ap;
 	struct syscall_args *sa;
 	int nap;
 
 	nap = 8;
 	p = td->td_proc;
 	ap = td->td_frame->tf_x;
 	sa = &td->td_sa;
 
 	sa->code = td->td_frame->tf_x[8];
 
 	if (sa->code == SYS_syscall || sa->code == SYS___syscall) {
 		sa->code = *ap++;
 		nap--;
 	}
 
 	if (p->p_sysent->sv_mask)
 		sa->code &= p->p_sysent->sv_mask;
 	if (sa->code >= p->p_sysent->sv_size)
 		sa->callp = &p->p_sysent->sv_table[0];
 	else
 		sa->callp = &p->p_sysent->sv_table[sa->code];
 
 	sa->narg = sa->callp->sy_narg;
 	memcpy(sa->args, ap, nap * sizeof(register_t));
 	if (sa->narg > nap)
 		panic("ARM64TODO: Could we have more than 8 args?");
 
 	td->td_retval[0] = 0;
 	td->td_retval[1] = 0;
 
 	return (0);
 }
 
 #include "../../kern/subr_syscall.c"
 
 static void
 svc_handler(struct thread *td, struct trapframe *frame)
 {
 	int error;
 
 	if ((frame->tf_esr & ESR_ELx_ISS_MASK) == 0) {
 		error = syscallenter(td);
 		syscallret(td, error);
 	} else {
 		call_trapsignal(td, SIGILL, ILL_ILLOPN, (void *)frame->tf_elr);
 		userret(td, frame);
 	}
 }
 
 static void
 data_abort(struct thread *td, struct trapframe *frame, uint64_t esr,
     uint64_t far, int lower)
 {
 	struct vm_map *map;
 	struct proc *p;
 	struct pcb *pcb;
 	vm_prot_t ftype;
 	vm_offset_t va;
 	int error, sig, ucode;
 
 	/*
 	 * According to the ARMv8-A rev. A.g, B2.10.5 "Load-Exclusive
 	 * and Store-Exclusive instruction usage restrictions", state
 	 * of the exclusive monitors after data abort exception is unknown.
 	 */
 	clrex();
 
 #ifdef KDB
 	if (kdb_active) {
 		kdb_reenter();
 		return;
 	}
 #endif
 
 	pcb = td->td_pcb;
 
 	/*
 	 * Special case for fuswintr and suswintr. These can't sleep so
 	 * handle them early on in the trap handler.
 	 */
 	if (__predict_false(pcb->pcb_onfault == (vm_offset_t)&fsu_intr_fault)) {
 		frame->tf_elr = pcb->pcb_onfault;
 		return;
 	}
 
 	p = td->td_proc;
 	if (lower)
 		map = &p->p_vmspace->vm_map;
 	else {
 		/* The top bit tells us which range to use */
 		if (far >= VM_MAXUSER_ADDRESS) {
 			map = kernel_map;
 		} else {
 			map = &p->p_vmspace->vm_map;
 			if (map == NULL)
 				map = kernel_map;
 		}
 	}
 
 	if (pmap_fault(map->pmap, esr, far) == KERN_SUCCESS)
 		return;
 
 	KASSERT(td->td_md.md_spinlock_count == 0,
 	    ("data abort with spinlock held"));
 	if (td->td_critnest != 0 || WITNESS_CHECK(WARN_SLEEPOK |
 	    WARN_GIANTOK, NULL, "Kernel page fault") != 0) {
 		print_registers(frame);
 		printf(" far: %16lx\n", far);
 		printf(" esr:         %.8lx\n", esr);
 		panic("data abort in critical section or under mutex");
 	}
 
 	va = trunc_page(far);
 	ftype = ((esr >> 6) & 1) ? VM_PROT_READ | VM_PROT_WRITE : VM_PROT_READ;
 
 	/* Fault in the page. */
 	error = vm_fault(map, va, ftype, VM_FAULT_NORMAL);
 	if (error != KERN_SUCCESS) {
 		if (lower) {
 			sig = SIGSEGV;
 			if (error == KERN_PROTECTION_FAILURE)
 				ucode = SEGV_ACCERR;
 			else
 				ucode = SEGV_MAPERR;
 			call_trapsignal(td, sig, ucode, (void *)far);
 		} else {
 			if (td->td_intr_nesting_level == 0 &&
 			    pcb->pcb_onfault != 0) {
 				frame->tf_x[0] = error;
 				frame->tf_elr = pcb->pcb_onfault;
 				return;
 			}
 
 			printf("Fatal data abort:\n");
 			print_registers(frame);
 			printf(" far: %16lx\n", far);
 			printf(" esr:         %.8lx\n", esr);
 
 #ifdef KDB
 			if (debugger_on_panic || kdb_active)
 				if (kdb_trap(ESR_ELx_EXCEPTION(esr), 0, frame))
 					return;
 #endif
 			panic("vm_fault failed: %lx", frame->tf_elr);
 		}
 	}
 
 	if (lower)
 		userret(td, frame);
 }
 
 static void
 print_registers(struct trapframe *frame)
 {
 	u_int reg;
 
 	for (reg = 0; reg < nitems(frame->tf_x); reg++) {
 		printf(" %sx%d: %16lx\n", (reg < 10) ? " " : "", reg,
 		    frame->tf_x[reg]);
 	}
 	printf("  sp: %16lx\n", frame->tf_sp);
 	printf("  lr: %16lx\n", frame->tf_lr);
 	printf(" elr: %16lx\n", frame->tf_elr);
 	printf("spsr:         %8x\n", frame->tf_spsr);
 }
 
 void
 do_el1h_sync(struct thread *td, struct trapframe *frame)
 {
 	struct trapframe *oframe;
 	uint32_t exception;
 	uint64_t esr, far;
 
 	/* Read the esr register to get the exception details */
 	esr = frame->tf_esr;
 	exception = ESR_ELx_EXCEPTION(esr);
 
 #ifdef KDTRACE_HOOKS
 	if (dtrace_trap_func != NULL && (*dtrace_trap_func)(frame, exception))
 		return;
 #endif
 
 	CTR4(KTR_TRAP,
 	    "do_el1_sync: curthread: %p, esr %lx, elr: %lx, frame: %p", td,
 	    esr, frame->tf_elr, frame);
 
 	oframe = td->td_frame;
 
 	switch (exception) {
 	case EXCP_BRK:
 	case EXCP_WATCHPT_EL1:
 	case EXCP_SOFTSTP_EL1:
 		break;
 	default:
 		td->td_frame = frame;
 		break;
 	}
 
 	switch(exception) {
 	case EXCP_FP_SIMD:
 	case EXCP_TRAP_FP:
 #ifdef VFP
 		if ((td->td_pcb->pcb_fpflags & PCB_FP_KERN) != 0) {
 			vfp_restore_state();
 		} else
 #endif
 		{
 			print_registers(frame);
 			printf(" esr:         %.8lx\n", esr);
 			panic("VFP exception in the kernel");
 		}
 		break;
 	case EXCP_INSN_ABORT:
 	case EXCP_DATA_ABORT:
 		far = READ_SPECIALREG(far_el1);
 		intr_enable();
 		data_abort(td, frame, esr, far, 0);
 		break;
 	case EXCP_BRK:
 #ifdef KDTRACE_HOOKS
 		if ((esr & ESR_ELx_ISS_MASK) == 0x40d && \
 		    dtrace_invop_jump_addr != 0) {
 			dtrace_invop_jump_addr(frame);
 			break;
 		}
 #endif
 		/* FALLTHROUGH */
 	case EXCP_WATCHPT_EL1:
 	case EXCP_SOFTSTP_EL1:
 #ifdef KDB
 		kdb_trap(exception, 0,
 		    (td->td_frame != NULL) ? td->td_frame : frame);
 #else
 		panic("No debugger in kernel.\n");
 #endif
 		break;
+	case EXCP_UNKNOWN:
+		if (undef_insn(1, frame))
+			break;
+		/* FALLTHROUGH */
 	default:
 		print_registers(frame);
 		panic("Unknown kernel exception %x esr_el1 %lx\n", exception,
 		    esr);
 	}
 
 	td->td_frame = oframe;
 }
 
-/*
- * The attempted execution of an instruction bit pattern that has no allocated
- * instruction results in an exception with an unknown reason.
- */
-static void
-el0_excp_unknown(struct trapframe *frame, uint64_t far)
-{
-	struct thread *td;
-
-	td = curthread;
-	call_trapsignal(td, SIGILL, ILL_ILLTRP, (void *)far);
-	userret(td, frame);
-}
-
 void
 do_el0_sync(struct thread *td, struct trapframe *frame)
 {
 	uint32_t exception;
 	uint64_t esr, far;
 
 	/* Check we have a sane environment when entering from userland */
 	KASSERT((uintptr_t)get_pcpu() >= VM_MIN_KERNEL_ADDRESS,
 	    ("Invalid pcpu address from userland: %p (tpidr %lx)",
 	     get_pcpu(), READ_SPECIALREG(tpidr_el1)));
 
 	esr = frame->tf_esr;
 	exception = ESR_ELx_EXCEPTION(esr);
 	switch (exception) {
 	case EXCP_UNKNOWN:
 	case EXCP_INSN_ABORT_L:
 	case EXCP_DATA_ABORT_L:
 	case EXCP_DATA_ABORT:
 		far = READ_SPECIALREG(far_el1);
 	}
 	intr_enable();
 
 	CTR4(KTR_TRAP,
 	    "do_el0_sync: curthread: %p, esr %lx, elr: %lx, frame: %p", td, esr,
 	    frame->tf_elr, frame);
 
 	switch(exception) {
 	case EXCP_FP_SIMD:
 	case EXCP_TRAP_FP:
 #ifdef VFP
 		vfp_restore_state();
 #else
 		panic("VFP exception in userland");
 #endif
 		break;
 	case EXCP_SVC:
 		svc_handler(td, frame);
 		break;
 	case EXCP_INSN_ABORT_L:
 	case EXCP_DATA_ABORT_L:
 	case EXCP_DATA_ABORT:
 		data_abort(td, frame, esr, far, 1);
 		break;
 	case EXCP_UNKNOWN:
-		el0_excp_unknown(frame, far);
+		if (!undef_insn(0, frame))
+			call_trapsignal(td, SIGILL, ILL_ILLTRP, (void *)far);
+		userret(td, frame);
 		break;
 	case EXCP_SP_ALIGN:
 		call_trapsignal(td, SIGBUS, BUS_ADRALN, (void *)frame->tf_sp);
 		userret(td, frame);
 		break;
 	case EXCP_PC_ALIGN:
 		call_trapsignal(td, SIGBUS, BUS_ADRALN, (void *)frame->tf_elr);
 		userret(td, frame);
 		break;
 	case EXCP_BRK:
 		call_trapsignal(td, SIGTRAP, TRAP_BRKPT, (void *)frame->tf_elr);
 		userret(td, frame);
 		break;
 	case EXCP_MSR:
 		call_trapsignal(td, SIGILL, ILL_PRVOPC, (void *)frame->tf_elr); 
 		userret(td, frame);
 		break;
 	case EXCP_SOFTSTP_EL0:
 		td->td_frame->tf_spsr &= ~PSR_SS;
 		td->td_pcb->pcb_flags &= ~PCB_SINGLE_STEP;
 		WRITE_SPECIALREG(MDSCR_EL1,
 		    READ_SPECIALREG(MDSCR_EL1) & ~DBG_MDSCR_SS);
 		call_trapsignal(td, SIGTRAP, TRAP_TRACE,
 		    (void *)frame->tf_elr);
 		userret(td, frame);
 		break;
 	default:
 		call_trapsignal(td, SIGBUS, BUS_OBJERR, (void *)frame->tf_elr);
 		userret(td, frame);
 		break;
 	}
 
 	KASSERT((td->td_pcb->pcb_fpflags & ~PCB_FP_USERMASK) == 0,
 	    ("Kernel VFP flags set while entering userspace"));
 	KASSERT(
 	    td->td_pcb->pcb_fpusaved == &td->td_pcb->pcb_fpustate,
 	    ("Kernel VFP state in use when entering userspace"));
 }
 
 void
 do_el0_error(struct trapframe *frame)
 {
 
 	panic("ARM64TODO: do_el0_error");
 }
 
Index: head/sys/arm64/arm64/undefined.c
===================================================================
--- head/sys/arm64/arm64/undefined.c	(nonexistent)
+++ head/sys/arm64/arm64/undefined.c	(revision 323593)
@@ -0,0 +1,145 @@
+/*-
+ * Copyright (c) 2017 Andrew Turner
+ * All rights reserved.
+ *
+ * This software was developed by SRI International and the University of
+ * Cambridge Computer Laboratory under DARPA/AFRL contract FA8750-10-C-0237
+ * ("CTSRD"), as part of the DARPA CRASH research programme.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+#include <sys/cdefs.h>
+__FBSDID("$FreeBSD$");
+
+#include <sys/param.h>
+#include <sys/systm.h>
+#include <sys/kernel.h>
+#include <sys/malloc.h>
+#include <sys/queue.h>
+
+#include <machine/frame.h>
+#include <machine/undefined.h>
+
+MALLOC_DEFINE(M_UNDEF, "undefhandler", "Undefined instruction handler data");
+
+struct undef_handler {
+	LIST_ENTRY(undef_handler) uh_link;
+	undef_handler_t		uh_handler;
+};
+
+/*
+ * Create two undefined instruction handler lists, one for userspace, one for
+ * the kernel. This allows us to handle instructions that will trap
+ */
+LIST_HEAD(, undef_handler) undef_handlers[2];
+
+/*
+ * Work around a bug in QEMU prior to 2.5.1 where reading unknown ID
+ * registers would raise an exception when they should return 0.
+ */
+static int
+id_aa64mmfr2_handler(vm_offset_t va, uint32_t insn, struct trapframe *frame,
+    uint32_t esr)
+{
+	int reg;
+
+#define	MRS_MASK			0xfff00000
+#define	MRS_VALUE			0xd5300000
+#define	MRS_REGISTER(insn)		((insn) & 0x1f)
+#define	 MRS_ID_AA64MMFR2_EL0_MASK	(MRS_MASK | 0x000fffe0)
+#define	 MRS_ID_AA64MMFR2_EL0_VALUE	(MRS_VALUE | 0x00080740)
+
+	/* mrs xn, id_aa64mfr2_el1 */
+	if ((insn & MRS_ID_AA64MMFR2_EL0_MASK) == MRS_ID_AA64MMFR2_EL0_VALUE) {
+		reg = MRS_REGISTER(insn);
+
+		frame->tf_elr += INSN_SIZE;
+		if (reg < nitems(frame->tf_x)) {
+			frame->tf_x[reg] = 0;
+		} else if (reg == 30) {
+			frame->tf_lr = 0;
+		}
+		/* If reg is 32 then write to xzr, i.e. do nothing */
+
+		return (1);
+	}
+	return (0);
+}
+
+void
+undef_init(void)
+{
+
+	LIST_INIT(&undef_handlers[0]);
+	LIST_INIT(&undef_handlers[1]);
+
+	install_undef_handler(false, id_aa64mmfr2_handler);
+}
+
+void *
+install_undef_handler(bool user, undef_handler_t func)
+{
+	struct undef_handler *uh;
+
+	uh = malloc(sizeof(*uh), M_UNDEF, M_WAITOK);
+	uh->uh_handler = func;
+	LIST_INSERT_HEAD(&undef_handlers[user ? 0 : 1], uh, uh_link);
+
+	return (uh);
+}
+
+void
+remove_undef_handler(void *handle)
+{
+	struct undef_handler *uh;
+
+	uh = handle;
+	LIST_REMOVE(uh, uh_link);
+	free(handle, M_UNDEF);
+}
+
+int
+undef_insn(u_int el, struct trapframe *frame)
+{
+	struct undef_handler *uh;
+	uint32_t insn;
+	int ret;
+
+	KASSERT(el < 2, ("Invalid exception level %u", el));
+
+	if (el == 0) {
+		ret = fueword32((uint32_t *)frame->tf_elr, &insn);
+		if (ret != 0)
+			panic("Unable to read userspace faulting instruction");
+	} else {
+		insn = *(uint32_t *)frame->tf_elr;
+	}
+
+	LIST_FOREACH(uh, &undef_handlers[el], uh_link) {
+		ret = uh->uh_handler(frame->tf_elr, insn, frame, frame->tf_esr);
+		if (ret)
+			return (1);
+	}
+
+	return (0);
+}

Property changes on: head/sys/arm64/arm64/undefined.c
___________________________________________________________________
Added: svn:eol-style
## -0,0 +1 ##
+native
\ No newline at end of property
Added: svn:keywords
## -0,0 +1 ##
+FreeBSD=%H
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+text/plain
\ No newline at end of property
Index: head/sys/arm64/include/undefined.h
===================================================================
--- head/sys/arm64/include/undefined.h	(nonexistent)
+++ head/sys/arm64/include/undefined.h	(revision 323593)
@@ -0,0 +1,44 @@
+/*-
+ * Copyright (c) 2017 Andrew Turner
+ * All rights reserved.
+ *
+ * This software was developed by SRI International and the University of
+ * Cambridge Computer Laboratory under DARPA/AFRL contract FA8750-10-C-0237
+ * ("CTSRD"), as part of the DARPA CRASH research programme.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * $FreeBSD$
+ */
+
+#ifndef _MACHINE__UNDEFINED_H_
+#define	_MACHINE__UNDEFINED_H_
+
+typedef int (*undef_handler_t)(vm_offset_t, uint32_t, struct trapframe *,
+    uint32_t);
+
+void undef_init(void);
+void *install_undef_handler(bool, undef_handler_t);
+void remove_undef_handler(void *);
+int undef_insn(u_int, struct trapframe *);
+
+#endif

Property changes on: head/sys/arm64/include/undefined.h
___________________________________________________________________
Added: svn:eol-style
## -0,0 +1 ##
+native
\ No newline at end of property
Added: svn:keywords
## -0,0 +1 ##
+FreeBSD=%H
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+text/plain
\ No newline at end of property
Index: head/sys/conf/files.arm64
===================================================================
--- head/sys/conf/files.arm64	(revision 323592)
+++ head/sys/conf/files.arm64	(revision 323593)
@@ -1,212 +1,213 @@
 # $FreeBSD$
 cloudabi64_vdso.o		optional	compat_cloudabi64	\
 	dependency	"$S/contrib/cloudabi/cloudabi_vdso_aarch64.S"	\
 	compile-with	"${CC} -x assembler-with-cpp -shared -nostdinc -nostdlib -Wl,-T$S/compat/cloudabi/cloudabi_vdso.lds $S/contrib/cloudabi/cloudabi_vdso_aarch64.S -o ${.TARGET}" \
 	no-obj no-implicit-rule						\
 	clean		"cloudabi64_vdso.o"
 #
 cloudabi64_vdso_blob.o		optional	compat_cloudabi64	\
 	dependency 	"cloudabi64_vdso.o"			\
 	compile-with	"${OBJCOPY} --input-target binary --output-target elf64-littleaarch64 --binary-architecture aarch64 cloudabi64_vdso.o ${.TARGET}" \
 	no-implicit-rule						\
 	clean		"cloudabi64_vdso_blob.o"
 #
 arm/allwinner/a10_ehci.c	optional	ehci aw_ehci fdt
 arm/allwinner/a10_gpio.c	optional	gpio aw_gpio fdt
 arm/allwinner/a10_mmc.c		optional	mmc aw_mmc fdt
 arm/allwinner/a64/a64_padconf.c	optional	soc_allwinner_a64 fdt
 arm/allwinner/a64/a64_r_padconf.c optional	soc_allwinner_a64 fdt
 arm/allwinner/aw_ccu.c		optional	aw_ccu fdt
 arm/allwinner/aw_nmi.c		optional	aw_nmi fdt \
 	compile-with "${NORMAL_C} -I$S/gnu/dts/include"
 arm/allwinner/aw_reset.c	optional	aw_ccu fdt
 arm/allwinner/aw_rsb.c		optional	aw_rsb fdt
 arm/allwinner/aw_rtc.c		optional	aw_rtc fdt
 arm/allwinner/aw_sid.c		optional	aw_sid fdt
 arm/allwinner/aw_thermal.c	optional	aw_thermal fdt
 arm/allwinner/aw_usbphy.c	optional	ehci aw_usbphy fdt
 arm/allwinner/aw_wdog.c		optional	aw_wdog fdt
 arm/allwinner/axp81x.c		optional	axp81x fdt
 arm/allwinner/clk/aw_ahbclk.c	optional	aw_ccu fdt
 arm/allwinner/clk/aw_apbclk.c	optional	aw_ccu fdt
 arm/allwinner/clk/aw_axiclk.c	optional	aw_ccu fdt
 arm/allwinner/clk/aw_cpuclk.c	optional	aw_ccu fdt
 arm/allwinner/clk/aw_gate.c	optional	aw_ccu fdt
 arm/allwinner/clk/aw_modclk.c	optional	aw_ccu fdt
 arm/allwinner/clk/aw_pll.c	optional	aw_ccu fdt \
 	compile-with "${NORMAL_C} -I$S/gnu/dts/include"
 arm/allwinner/clk/aw_thsclk.c	optional	aw_ccu fdt
 arm/allwinner/clk/aw_usbclk.c	optional	aw_ccu fdt
 arm/allwinner/clkng/aw_ccung.c	optional	aw_ccu fdt
 arm/allwinner/clkng/aw_clk_nkmp.c	optional	aw_ccu fdt
 arm/allwinner/clkng/aw_clk_nm.c	optional	aw_ccu fdt
 arm/allwinner/clkng/aw_clk_prediv_mux.c	optional	aw_ccu fdt
 arm/allwinner/clkng/ccu_a64.c	optional	aw_ccu fdt
 arm/allwinner/clkng/ccu_h3.c	optional	aw_ccu fdt
 
 arm/allwinner/if_awg.c		optional	awg fdt
 arm/annapurna/alpine/alpine_ccu.c		optional	al_ccu fdt
 arm/annapurna/alpine/alpine_nb_service.c	optional	al_nb_service fdt
 arm/annapurna/alpine/alpine_pci.c		optional	al_pci fdt
 arm/annapurna/alpine/alpine_pci_msix.c		optional	al_pci fdt
 arm/annapurna/alpine/alpine_serdes.c		optional al_serdes fdt		\
 	no-depend	\
 	compile-with "${CC} -c -o ${.TARGET} ${CFLAGS} -I$S/contrib/alpine-hal -I$S/contrib/alpine-hal/eth ${PROF} ${.IMPSRC}"
 arm/arm/generic_timer.c		standard
 arm/arm/gic.c			standard
 arm/arm/gic_fdt.c		optional	fdt
 arm/arm/pmu.c			standard
 arm/broadcom/bcm2835/bcm2835_audio.c		optional sound vchiq fdt \
 	compile-with "${NORMAL_C} -DUSE_VCHIQ_ARM -D__VCCOREVER__=0x04000000 -I$S/contrib/vchiq"
 arm/broadcom/bcm2835/bcm2835_bsc.c		optional bcm2835_bsc soc_brcm_bcm2837 fdt
 arm/broadcom/bcm2835/bcm2835_cpufreq.c		optional soc_brcm_bcm2837 fdt
 arm/broadcom/bcm2835/bcm2835_dma.c		optional soc_brcm_bcm2837 fdt
 arm/broadcom/bcm2835/bcm2835_fbd.c		optional vt soc_brcm_bcm2837 fdt
 arm/broadcom/bcm2835/bcm2835_ft5406.c		optional evdev bcm2835_ft5406 soc_brcm_bcm2837 fdt
 arm/broadcom/bcm2835/bcm2835_gpio.c		optional gpio soc_brcm_bcm2837 fdt
 arm/broadcom/bcm2835/bcm2835_intr.c		optional soc_brcm_bcm2837 fdt
 arm/broadcom/bcm2835/bcm2835_mbox.c		optional soc_brcm_bcm2837 fdt
 arm/broadcom/bcm2835/bcm2835_rng.c		optional random soc_brcm_bcm2837 fdt
 arm/broadcom/bcm2835/bcm2835_sdhci.c		optional sdhci soc_brcm_bcm2837 fdt
 arm/broadcom/bcm2835/bcm2835_spi.c		optional bcm2835_spi soc_brcm_bcm2837 fdt
 arm/broadcom/bcm2835/bcm2835_vcio.c		optional soc_brcm_bcm2837 fdt
 arm/broadcom/bcm2835/bcm2835_wdog.c		optional soc_brcm_bcm2837 fdt
 arm/broadcom/bcm2835/bcm2836.c			optional soc_brcm_bcm2837 fdt
 arm/broadcom/bcm2835/bcm283x_dwc_fdt.c		optional dwcotg fdt soc_brcm_bcm2837
 arm/mv/armada38x/armada38x_rtc.c		optional mv_rtc fdt
 arm64/acpica/acpi_machdep.c	optional	acpi
 arm64/acpica/OsdEnvironment.c	optional	acpi
 arm64/acpica/acpi_wakeup.c	optional	acpi
 arm64/acpica/pci_cfgreg.c	optional	acpi	pci
 arm64/arm64/autoconf.c		standard
 arm64/arm64/bus_machdep.c	standard
 arm64/arm64/bus_space_asm.S	standard
 arm64/arm64/busdma_bounce.c	standard
 arm64/arm64/busdma_machdep.c	standard
 arm64/arm64/bzero.S		standard
 arm64/arm64/clock.c		standard
 arm64/arm64/copyinout.S		standard
 arm64/arm64/copystr.c		standard
 arm64/arm64/cpufunc_asm.S	standard
 arm64/arm64/db_disasm.c		optional	ddb
 arm64/arm64/db_interface.c	optional	ddb
 arm64/arm64/db_trace.c		optional	ddb
 arm64/arm64/debug_monitor.c	optional	ddb
 arm64/arm64/disassem.c		optional	ddb
 arm64/arm64/dump_machdep.c	standard
 arm64/arm64/elf_machdep.c	standard
 arm64/arm64/exception.S		standard
 arm64/arm64/gicv3_its.c		optional	intrng fdt
 arm64/arm64/gic_v3.c		standard
 arm64/arm64/gic_v3_fdt.c	optional	fdt
 arm64/arm64/identcpu.c		standard
 arm64/arm64/in_cksum.c		optional	inet | inet6
 arm64/arm64/locore.S		standard	no-obj
 arm64/arm64/machdep.c		standard
 arm64/arm64/mem.c		standard
 arm64/arm64/memcpy.S		standard
 arm64/arm64/memmove.S		standard
 arm64/arm64/minidump_machdep.c	standard
 arm64/arm64/mp_machdep.c	optional	smp
 arm64/arm64/nexus.c		standard
 arm64/arm64/ofw_machdep.c	optional	fdt
 arm64/arm64/pmap.c		standard
 arm64/arm64/stack_machdep.c	optional	ddb | stack
 arm64/arm64/support.S		standard
 arm64/arm64/swtch.S		standard
 arm64/arm64/sys_machdep.c	standard
 arm64/arm64/trap.c		standard
 arm64/arm64/uio_machdep.c	standard
 arm64/arm64/uma_machdep.c	standard
+arm64/arm64/undefined.c		standard
 arm64/arm64/unwind.c		optional	ddb | kdtrace_hooks | stack
 arm64/arm64/vfp.c		standard
 arm64/arm64/vm_machdep.c	standard
 arm64/cavium/thunder_pcie_fdt.c		optional	soc_cavm_thunderx pci fdt
 arm64/cavium/thunder_pcie_pem.c		optional	soc_cavm_thunderx pci
 arm64/cavium/thunder_pcie_pem_fdt.c	optional	soc_cavm_thunderx pci fdt
 arm64/cavium/thunder_pcie_common.c	optional	soc_cavm_thunderx pci
 arm64/cloudabi64/cloudabi64_sysvec.c	optional compat_cloudabi64
 contrib/vchiq/interface/compat/vchi_bsd.c	optional vchiq soc_brcm_bcm2837 \
 	compile-with "${NORMAL_C} -DUSE_VCHIQ_ARM -D__VCCOREVER__=0x04000000 -I$S/contrib/vchiq"
 contrib/vchiq/interface/vchiq_arm/vchiq_2835_arm.c	optional vchiq soc_brcm_bcm2837 \
 	compile-with "${NORMAL_C} -Wno-unused -DUSE_VCHIQ_ARM -D__VCCOREVER__=0x04000000 -I$S/contrib/vchiq"
 contrib/vchiq/interface/vchiq_arm/vchiq_arm.c	optional vchiq soc_brcm_bcm2837 \
 	compile-with "${NORMAL_C} -Wno-unused -DUSE_VCHIQ_ARM -D__VCCOREVER__=0x04000000 -I$S/contrib/vchiq"
 contrib/vchiq/interface/vchiq_arm/vchiq_connected.c	optional vchiq soc_brcm_bcm2837 \
 	compile-with "${NORMAL_C} -DUSE_VCHIQ_ARM -D__VCCOREVER__=0x04000000 -I$S/contrib/vchiq"
 contrib/vchiq/interface/vchiq_arm/vchiq_core.c	optional vchiq soc_brcm_bcm2837 \
 	compile-with "${NORMAL_C} -DUSE_VCHIQ_ARM -D__VCCOREVER__=0x04000000 -I$S/contrib/vchiq"
 contrib/vchiq/interface/vchiq_arm/vchiq_kern_lib.c	optional vchiq soc_brcm_bcm2837 \
 	compile-with "${NORMAL_C} -DUSE_VCHIQ_ARM -D__VCCOREVER__=0x04000000 -I$S/contrib/vchiq"
 contrib/vchiq/interface/vchiq_arm/vchiq_kmod.c	optional vchiq soc_brcm_bcm2837 \
 	compile-with "${NORMAL_C} -DUSE_VCHIQ_ARM -D__VCCOREVER__=0x04000000 -I$S/contrib/vchiq"
 contrib/vchiq/interface/vchiq_arm/vchiq_shim.c	optional vchiq soc_brcm_bcm2837 \
 	compile-with "${NORMAL_C} -DUSE_VCHIQ_ARM -D__VCCOREVER__=0x04000000 -I$S/contrib/vchiq"
 contrib/vchiq/interface/vchiq_arm/vchiq_util.c	optional vchiq soc_brcm_bcm2837 \
 	compile-with "${NORMAL_C} -DUSE_VCHIQ_ARM -D__VCCOREVER__=0x04000000 -I$S/contrib/vchiq"
 crypto/armv8/armv8_crypto.c	optional	armv8crypto
 armv8_crypto_wrap.o		optional	armv8crypto		\
 	dependency	"$S/crypto/armv8/armv8_crypto_wrap.c"		\
 	compile-with	"${CC} -c ${CFLAGS:C/^-O2$/-O3/:N-nostdinc:N-mgeneral-regs-only} ${WERROR} ${NO_WCAST_QUAL} ${PROF} -march=armv8-a+crypto ${.IMPSRC}" \
 	no-implicit-rule						\
 	clean		"armv8_crypto_wrap.o"
 crypto/blowfish/bf_enc.c	optional	crypto | ipsec | ipsec_support
 crypto/des/des_enc.c		optional	crypto | ipsec | ipsec_support | netsmb
 dev/acpica/acpi_if.m		optional	acpi
 dev/ahci/ahci_generic.c		optional	ahci
 dev/axgbe/if_axgbe.c		optional	axgbe
 dev/axgbe/xgbe-desc.c		optional	axgbe
 dev/axgbe/xgbe-dev.c		optional	axgbe
 dev/axgbe/xgbe-drv.c		optional	axgbe
 dev/axgbe/xgbe-mdio.c		optional	axgbe
 dev/cpufreq/cpufreq_dt.c	optional	cpufreq fdt
 dev/iicbus/twsi/a10_twsi.c	optional	twsi fdt
 dev/iicbus/twsi/twsi.c		optional	twsi fdt
 dev/hwpmc/hwpmc_arm64.c		optional	hwpmc
 dev/hwpmc/hwpmc_arm64_md.c	optional	hwpmc
 dev/mbox/mbox_if.m		optional	soc_brcm_bcm2837
 dev/mmc/host/dwmmc.c		optional	dwmmc fdt
 dev/mmc/host/dwmmc_hisi.c	optional	dwmmc fdt soc_hisi_hi6220
 dev/neta/if_mvneta_fdt.c	optional	neta fdt
 dev/neta/if_mvneta.c		optional	neta mdio mii
 dev/ofw/ofw_cpu.c		optional	fdt
 dev/ofw/ofwpci.c		optional 	fdt pci
 dev/pci/pci_host_generic.c	optional	pci
 dev/pci/pci_host_generic_fdt.c	optional	pci fdt
 dev/psci/psci.c			optional	psci
 dev/psci/psci_arm64.S		optional	psci
 dev/uart/uart_cpu_arm64.c	optional	uart
 dev/uart/uart_dev_pl011.c	optional	uart pl011
 dev/usb/controller/dwc_otg_hisi.c optional	dwcotg fdt soc_hisi_hi6220
 dev/usb/controller/ehci_mv.c	optional	ehci_mv fdt
 dev/usb/controller/generic_ehci.c optional	ehci acpi
 dev/usb/controller/generic_ohci.c optional	ohci fdt
 dev/usb/controller/generic_usb_if.m optional	ohci fdt
 dev/usb/controller/xhci_mv.c	optional	xhci_mv fdt
 dev/vnic/mrml_bridge.c		optional	vnic fdt
 dev/vnic/nic_main.c		optional	vnic pci
 dev/vnic/nicvf_main.c		optional	vnic pci pci_iov
 dev/vnic/nicvf_queues.c		optional	vnic pci pci_iov
 dev/vnic/thunder_bgx_fdt.c	optional	vnic fdt
 dev/vnic/thunder_bgx.c		optional	vnic pci
 dev/vnic/thunder_mdio_fdt.c	optional	vnic fdt
 dev/vnic/thunder_mdio.c		optional	vnic
 dev/vnic/lmac_if.m		optional	inet | inet6 | vnic
 kern/kern_clocksource.c		standard
 kern/msi_if.m			optional	intrng
 kern/pic_if.m			optional	intrng
 kern/subr_devmap.c		standard
 kern/subr_intr.c		optional	intrng
 libkern/bcmp.c			standard
 libkern/ffs.c			standard
 libkern/ffsl.c			standard
 libkern/ffsll.c			standard
 libkern/fls.c			standard
 libkern/flsl.c			standard
 libkern/flsll.c			standard
 libkern/memset.c		standard
 libkern/arm64/crc32c_armv8.S	standard
 cddl/contrib/opensolaris/common/atomic/aarch64/opensolaris_atomic.S	optional zfs | dtrace compile-with "${CDDL_C}"
 cddl/dev/dtrace/aarch64/dtrace_asm.S			optional dtrace compile-with "${DTRACE_S}"
 cddl/dev/dtrace/aarch64/dtrace_subr.c			optional dtrace compile-with "${DTRACE_C}"
 cddl/dev/fbt/aarch64/fbt_isa.c				optional dtrace_fbt | dtraceall compile-with "${FBT_C}"