Index: head/sys/arm/at91/at91_twi.c =================================================================== --- head/sys/arm/at91/at91_twi.c (revision 323552) +++ head/sys/arm/at91/at91_twi.c (revision 323553) @@ -1,428 +1,428 @@ /*- * Copyright (c) 2006 M. Warner Losh. All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. */ #include "opt_platform.h" #include __FBSDID("$FreeBSD$"); #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include "iicbus_if.h" #ifdef FDT #include #include #endif #define TWI_SLOW_CLOCK 1500 #define TWI_FAST_CLOCK 45000 #define TWI_FASTEST_CLOCK 90000 struct at91_twi_softc { device_t dev; /* Myself */ void *intrhand; /* Interrupt handle */ struct resource *irq_res; /* IRQ resource */ struct resource *mem_res; /* Memory resource */ struct mtx sc_mtx; /* basically a perimeter lock */ volatile uint32_t flags; uint32_t cwgr; int sc_started; int twi_addr; device_t iicbus; }; static inline uint32_t RD4(struct at91_twi_softc *sc, bus_size_t off) { return bus_read_4(sc->mem_res, off); } static inline void WR4(struct at91_twi_softc *sc, bus_size_t off, uint32_t val) { bus_write_4(sc->mem_res, off, val); } #define AT91_TWI_LOCK(_sc) mtx_lock(&(_sc)->sc_mtx) #define AT91_TWI_UNLOCK(_sc) mtx_unlock(&(_sc)->sc_mtx) #define AT91_TWI_LOCK_INIT(_sc) \ mtx_init(&_sc->sc_mtx, device_get_nameunit(_sc->dev), \ "twi", MTX_DEF) #define AT91_TWI_LOCK_DESTROY(_sc) mtx_destroy(&_sc->sc_mtx); #define AT91_TWI_ASSERT_LOCKED(_sc) mtx_assert(&_sc->sc_mtx, MA_OWNED); #define AT91_TWI_ASSERT_UNLOCKED(_sc) mtx_assert(&_sc->sc_mtx, MA_NOTOWNED); #define TWI_DEF_CLK 100000 static devclass_t at91_twi_devclass; /* bus entry points */ static int at91_twi_probe(device_t dev); static int at91_twi_attach(device_t dev); static int at91_twi_detach(device_t dev); static void at91_twi_intr(void *); /* helper routines */ static int at91_twi_activate(device_t dev); static void at91_twi_deactivate(device_t dev); static int at91_twi_probe(device_t dev) { #ifdef FDT /* XXXX need a whole list, since there's at least 4 different ones */ if (!ofw_bus_is_compatible(dev, "atmel,at91sam9g20-i2c")) return (ENXIO); #endif device_set_desc(dev, "TWI"); return (0); } static int at91_twi_attach(device_t dev) { struct at91_twi_softc *sc = device_get_softc(dev); int err; sc->dev = dev; err = at91_twi_activate(dev); if (err) goto out; AT91_TWI_LOCK_INIT(sc); #ifdef FDT /* * Disable devices need to hold their resources, so return now and not attach * the iicbus, setup interrupt handlers, etc. */ if (!ofw_bus_status_okay(dev)) return 0; #endif /* * Activate the interrupt */ err = bus_setup_intr(dev, sc->irq_res, INTR_TYPE_MISC | INTR_MPSAFE, NULL, at91_twi_intr, sc, &sc->intrhand); if (err) { AT91_TWI_LOCK_DESTROY(sc); goto out; } sc->cwgr = TWI_CWGR_CKDIV(8 * at91_master_clock / TWI_FASTEST_CLOCK) | TWI_CWGR_CHDIV(TWI_CWGR_DIV(TWI_DEF_CLK)) | TWI_CWGR_CLDIV(TWI_CWGR_DIV(TWI_DEF_CLK)); WR4(sc, TWI_CR, TWI_CR_SWRST); WR4(sc, TWI_CR, TWI_CR_MSEN | TWI_CR_SVDIS); WR4(sc, TWI_CWGR, sc->cwgr); if ((sc->iicbus = device_add_child(dev, "iicbus", -1)) == NULL) device_printf(dev, "could not allocate iicbus instance\n"); - /* probe and attach the iicbus */ - bus_generic_attach(dev); + /* Probe and attach the iicbus when interrupts are available. */ + config_intrhook_oneshot((ich_func_t)bus_generic_attach, dev); out: if (err) at91_twi_deactivate(dev); return (err); } static int at91_twi_detach(device_t dev) { struct at91_twi_softc *sc; int rv; sc = device_get_softc(dev); at91_twi_deactivate(dev); if (sc->iicbus && (rv = device_delete_child(dev, sc->iicbus)) != 0) return (rv); AT91_TWI_LOCK_DESTROY(sc); return (0); } static int at91_twi_activate(device_t dev) { struct at91_twi_softc *sc; int rid; sc = device_get_softc(dev); rid = 0; sc->mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, RF_ACTIVE); if (sc->mem_res == NULL) goto errout; rid = 0; sc->irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, RF_ACTIVE); if (sc->irq_res == NULL) goto errout; return (0); errout: at91_twi_deactivate(dev); return (ENOMEM); } static void at91_twi_deactivate(device_t dev) { struct at91_twi_softc *sc; sc = device_get_softc(dev); if (sc->intrhand) bus_teardown_intr(dev, sc->irq_res, sc->intrhand); sc->intrhand = NULL; bus_generic_detach(sc->dev); if (sc->mem_res) bus_release_resource(dev, SYS_RES_MEMORY, rman_get_rid(sc->mem_res), sc->mem_res); sc->mem_res = NULL; if (sc->irq_res) bus_release_resource(dev, SYS_RES_IRQ, rman_get_rid(sc->irq_res), sc->irq_res); sc->irq_res = NULL; return; } static void at91_twi_intr(void *xsc) { struct at91_twi_softc *sc = xsc; uint32_t status; status = RD4(sc, TWI_SR); if (status == 0) return; AT91_TWI_LOCK(sc); sc->flags |= status & (TWI_SR_OVRE | TWI_SR_UNRE | TWI_SR_NACK); if (status & TWI_SR_RXRDY) sc->flags |= TWI_SR_RXRDY; if (status & TWI_SR_TXRDY) sc->flags |= TWI_SR_TXRDY; if (status & TWI_SR_TXCOMP) sc->flags |= TWI_SR_TXCOMP; WR4(sc, TWI_IDR, status); wakeup(sc); AT91_TWI_UNLOCK(sc); return; } static int at91_twi_wait(struct at91_twi_softc *sc, uint32_t bit) { int err = 0; int counter = 100000; uint32_t sr; AT91_TWI_ASSERT_LOCKED(sc); while (!((sr = RD4(sc, TWI_SR)) & bit) && counter-- > 0 && !(sr & TWI_SR_NACK)) continue; if (counter <= 0) err = EBUSY; else if (sr & TWI_SR_NACK) err = ENXIO; // iic nack convention return (err); } static int at91_twi_rst_card(device_t dev, u_char speed, u_char addr, u_char *oldaddr) { struct at91_twi_softc *sc; int clk; sc = device_get_softc(dev); AT91_TWI_LOCK(sc); if (oldaddr) *oldaddr = sc->twi_addr; sc->twi_addr = addr; /* * speeds are for 1.5kb/s, 45kb/s and 90kb/s. */ switch (speed) { case IIC_SLOW: clk = TWI_SLOW_CLOCK; break; case IIC_FAST: clk = TWI_FAST_CLOCK; break; case IIC_UNKNOWN: case IIC_FASTEST: default: clk = TWI_FASTEST_CLOCK; break; } sc->cwgr = TWI_CWGR_CKDIV(1) | TWI_CWGR_CHDIV(TWI_CWGR_DIV(clk)) | TWI_CWGR_CLDIV(TWI_CWGR_DIV(clk)); WR4(sc, TWI_CR, TWI_CR_SWRST); WR4(sc, TWI_CR, TWI_CR_MSEN | TWI_CR_SVDIS); WR4(sc, TWI_CWGR, sc->cwgr); AT91_TWI_UNLOCK(sc); return 0; } static int at91_twi_callback(device_t dev, int index, caddr_t data) { int error = 0; switch (index) { case IIC_REQUEST_BUS: break; case IIC_RELEASE_BUS: break; default: error = EINVAL; } return (error); } static int at91_twi_transfer(device_t dev, struct iic_msg *msgs, uint32_t nmsgs) { struct at91_twi_softc *sc; int i, len, err; uint32_t rdwr; uint8_t *buf; uint32_t sr; sc = device_get_softc(dev); err = 0; AT91_TWI_LOCK(sc); for (i = 0; i < nmsgs; i++) { /* * The linux atmel driver doesn't use the internal device * address feature of twi. A separate i2c message needs to * be written to use this. * See http://lists.arm.linux.org.uk/pipermail/linux-arm-kernel/2004-September/024411.html * for details. Upon reflection, we could use this as an * optimization, but it is unclear the code bloat will * result in faster/better operations. */ rdwr = (msgs[i].flags & IIC_M_RD) ? TWI_MMR_MREAD : 0; WR4(sc, TWI_MMR, TWI_MMR_DADR(msgs[i].slave) | rdwr); len = msgs[i].len; buf = msgs[i].buf; /* zero byte transfers aren't allowed */ if (len == 0 || buf == NULL) { err = EINVAL; goto out; } if (len == 1 && msgs[i].flags & IIC_M_RD) WR4(sc, TWI_CR, TWI_CR_START | TWI_CR_STOP); else WR4(sc, TWI_CR, TWI_CR_START); if (msgs[i].flags & IIC_M_RD) { sr = RD4(sc, TWI_SR); while (!(sr & TWI_SR_TXCOMP)) { if ((sr = RD4(sc, TWI_SR)) & TWI_SR_RXRDY) { len--; *buf++ = RD4(sc, TWI_RHR) & 0xff; if (len == 1) WR4(sc, TWI_CR, TWI_CR_STOP); } } if (len > 0 || (sr & TWI_SR_NACK)) { err = ENXIO; // iic nack convention goto out; } } else { while (len--) { if ((err = at91_twi_wait(sc, TWI_SR_TXRDY))) goto out; WR4(sc, TWI_THR, *buf++); } WR4(sc, TWI_CR, TWI_CR_STOP); } if ((err = at91_twi_wait(sc, TWI_SR_TXCOMP))) break; } out: if (err) { WR4(sc, TWI_CR, TWI_CR_SWRST); WR4(sc, TWI_CR, TWI_CR_MSEN | TWI_CR_SVDIS); WR4(sc, TWI_CWGR, sc->cwgr); } AT91_TWI_UNLOCK(sc); return (err); } static device_method_t at91_twi_methods[] = { /* Device interface */ DEVMETHOD(device_probe, at91_twi_probe), DEVMETHOD(device_attach, at91_twi_attach), DEVMETHOD(device_detach, at91_twi_detach), /* iicbus interface */ DEVMETHOD(iicbus_callback, at91_twi_callback), DEVMETHOD(iicbus_reset, at91_twi_rst_card), DEVMETHOD(iicbus_transfer, at91_twi_transfer), DEVMETHOD_END }; static driver_t at91_twi_driver = { "at91_twi", at91_twi_methods, sizeof(struct at91_twi_softc), }; #ifdef FDT DRIVER_MODULE(at91_twi, simplebus, at91_twi_driver, at91_twi_devclass, NULL, NULL); #else DRIVER_MODULE(at91_twi, atmelarm, at91_twi_driver, at91_twi_devclass, NULL, NULL); #endif DRIVER_MODULE(iicbus, at91_twi, iicbus_driver, iicbus_devclass, NULL, NULL); MODULE_DEPEND(at91_twi, iicbus, 1, 1, 1); Index: head/sys/arm/broadcom/bcm2835/bcm2835_bsc.c =================================================================== --- head/sys/arm/broadcom/bcm2835/bcm2835_bsc.c (revision 323552) +++ head/sys/arm/broadcom/bcm2835/bcm2835_bsc.c (revision 323553) @@ -1,514 +1,517 @@ /*- * Copyright (c) 2001 Tsubai Masanari. * Copyright (c) 2012 Oleksandr Tymoshenko * Copyright (c) 2013 Luiz Otavio O Souza * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. * */ #include __FBSDID("$FreeBSD$"); #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include "iicbus_if.h" static struct ofw_compat_data compat_data[] = { {"broadcom,bcm2835-bsc", 1}, {"brcm,bcm2708-i2c", 1}, {"brcm,bcm2835-i2c", 1}, {NULL, 0} }; static void bcm_bsc_intr(void *); static int bcm_bsc_detach(device_t); static void bcm_bsc_modifyreg(struct bcm_bsc_softc *sc, uint32_t off, uint32_t mask, uint32_t value) { uint32_t reg; mtx_assert(&sc->sc_mtx, MA_OWNED); reg = BCM_BSC_READ(sc, off); reg &= ~mask; reg |= value; BCM_BSC_WRITE(sc, off, reg); } static int bcm_bsc_clock_proc(SYSCTL_HANDLER_ARGS) { struct bcm_bsc_softc *sc; uint32_t clk; sc = (struct bcm_bsc_softc *)arg1; BCM_BSC_LOCK(sc); clk = BCM_BSC_READ(sc, BCM_BSC_CLOCK); BCM_BSC_UNLOCK(sc); clk &= 0xffff; if (clk == 0) clk = 32768; clk = BCM_BSC_CORE_CLK / clk; return (sysctl_handle_int(oidp, &clk, 0, req)); } static int bcm_bsc_clkt_proc(SYSCTL_HANDLER_ARGS) { struct bcm_bsc_softc *sc; uint32_t clkt; int error; sc = (struct bcm_bsc_softc *)arg1; BCM_BSC_LOCK(sc); clkt = BCM_BSC_READ(sc, BCM_BSC_CLKT); BCM_BSC_UNLOCK(sc); clkt &= 0xffff; error = sysctl_handle_int(oidp, &clkt, sizeof(clkt), req); if (error != 0 || req->newptr == NULL) return (error); BCM_BSC_LOCK(sc); BCM_BSC_WRITE(sc, BCM_BSC_CLKT, clkt & 0xffff); BCM_BSC_UNLOCK(sc); return (0); } static int bcm_bsc_fall_proc(SYSCTL_HANDLER_ARGS) { struct bcm_bsc_softc *sc; uint32_t clk, reg; int error; sc = (struct bcm_bsc_softc *)arg1; BCM_BSC_LOCK(sc); reg = BCM_BSC_READ(sc, BCM_BSC_DELAY); BCM_BSC_UNLOCK(sc); reg >>= 16; error = sysctl_handle_int(oidp, ®, sizeof(reg), req); if (error != 0 || req->newptr == NULL) return (error); BCM_BSC_LOCK(sc); clk = BCM_BSC_READ(sc, BCM_BSC_CLOCK); clk = BCM_BSC_CORE_CLK / clk; if (reg > clk / 2) reg = clk / 2 - 1; bcm_bsc_modifyreg(sc, BCM_BSC_DELAY, 0xffff0000, reg << 16); BCM_BSC_UNLOCK(sc); return (0); } static int bcm_bsc_rise_proc(SYSCTL_HANDLER_ARGS) { struct bcm_bsc_softc *sc; uint32_t clk, reg; int error; sc = (struct bcm_bsc_softc *)arg1; BCM_BSC_LOCK(sc); reg = BCM_BSC_READ(sc, BCM_BSC_DELAY); BCM_BSC_UNLOCK(sc); reg &= 0xffff; error = sysctl_handle_int(oidp, ®, sizeof(reg), req); if (error != 0 || req->newptr == NULL) return (error); BCM_BSC_LOCK(sc); clk = BCM_BSC_READ(sc, BCM_BSC_CLOCK); clk = BCM_BSC_CORE_CLK / clk; if (reg > clk / 2) reg = clk / 2 - 1; bcm_bsc_modifyreg(sc, BCM_BSC_DELAY, 0xffff, reg); BCM_BSC_UNLOCK(sc); return (0); } static void bcm_bsc_sysctl_init(struct bcm_bsc_softc *sc) { struct sysctl_ctx_list *ctx; struct sysctl_oid *tree_node; struct sysctl_oid_list *tree; /* * Add system sysctl tree/handlers. */ ctx = device_get_sysctl_ctx(sc->sc_dev); tree_node = device_get_sysctl_tree(sc->sc_dev); tree = SYSCTL_CHILDREN(tree_node); SYSCTL_ADD_PROC(ctx, tree, OID_AUTO, "frequency", CTLFLAG_RW | CTLTYPE_UINT, sc, sizeof(*sc), bcm_bsc_clock_proc, "IU", "I2C BUS clock frequency"); SYSCTL_ADD_PROC(ctx, tree, OID_AUTO, "clock_stretch", CTLFLAG_RW | CTLTYPE_UINT, sc, sizeof(*sc), bcm_bsc_clkt_proc, "IU", "I2C BUS clock stretch timeout"); SYSCTL_ADD_PROC(ctx, tree, OID_AUTO, "fall_edge_delay", CTLFLAG_RW | CTLTYPE_UINT, sc, sizeof(*sc), bcm_bsc_fall_proc, "IU", "I2C BUS falling edge delay"); SYSCTL_ADD_PROC(ctx, tree, OID_AUTO, "rise_edge_delay", CTLFLAG_RW | CTLTYPE_UINT, sc, sizeof(*sc), bcm_bsc_rise_proc, "IU", "I2C BUS rising edge delay"); } static void bcm_bsc_reset(struct bcm_bsc_softc *sc) { /* Enable the BSC Controller, disable interrupts. */ BCM_BSC_WRITE(sc, BCM_BSC_CTRL, BCM_BSC_CTRL_I2CEN); /* Clear pending interrupts. */ BCM_BSC_WRITE(sc, BCM_BSC_STATUS, BCM_BSC_STATUS_CLKT | BCM_BSC_STATUS_ERR | BCM_BSC_STATUS_DONE); /* Clear the FIFO. */ bcm_bsc_modifyreg(sc, BCM_BSC_CTRL, BCM_BSC_CTRL_CLEAR0, BCM_BSC_CTRL_CLEAR0); } static int bcm_bsc_probe(device_t dev) { if (!ofw_bus_status_okay(dev)) return (ENXIO); if (ofw_bus_search_compatible(dev, compat_data)->ocd_data == 0) return (ENXIO); device_set_desc(dev, "BCM2708/2835 BSC controller"); return (BUS_PROBE_DEFAULT); } static int bcm_bsc_attach(device_t dev) { struct bcm_bsc_softc *sc; unsigned long start; device_t gpio; int i, rid; sc = device_get_softc(dev); sc->sc_dev = dev; rid = 0; sc->sc_mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, RF_ACTIVE); if (!sc->sc_mem_res) { device_printf(dev, "cannot allocate memory window\n"); return (ENXIO); } sc->sc_bst = rman_get_bustag(sc->sc_mem_res); sc->sc_bsh = rman_get_bushandle(sc->sc_mem_res); /* Check the unit we are attaching by its base address. */ start = rman_get_start(sc->sc_mem_res); for (i = 0; i < nitems(bcm_bsc_pins); i++) { if (bcm_bsc_pins[i].start == (start & BCM_BSC_BASE_MASK)) break; } if (i == nitems(bcm_bsc_pins)) { device_printf(dev, "only bsc0 and bsc1 are supported\n"); bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->sc_mem_res); return (ENXIO); } /* * Configure the GPIO pins to ALT0 function to enable BSC control * over the pins. */ gpio = devclass_get_device(devclass_find("gpio"), 0); if (!gpio) { device_printf(dev, "cannot find gpio0\n"); bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->sc_mem_res); return (ENXIO); } bcm_gpio_set_alternate(gpio, bcm_bsc_pins[i].sda, BCM_GPIO_ALT0); bcm_gpio_set_alternate(gpio, bcm_bsc_pins[i].scl, BCM_GPIO_ALT0); rid = 0; sc->sc_irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, RF_ACTIVE | RF_SHAREABLE); if (!sc->sc_irq_res) { bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->sc_mem_res); device_printf(dev, "cannot allocate interrupt\n"); return (ENXIO); } /* Hook up our interrupt handler. */ if (bus_setup_intr(dev, sc->sc_irq_res, INTR_TYPE_MISC | INTR_MPSAFE, NULL, bcm_bsc_intr, sc, &sc->sc_intrhand)) { bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sc_irq_res); bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->sc_mem_res); device_printf(dev, "cannot setup the interrupt handler\n"); return (ENXIO); } mtx_init(&sc->sc_mtx, "bcm_bsc", NULL, MTX_DEF); bcm_bsc_sysctl_init(sc); /* Enable the BSC controller. Flush the FIFO. */ BCM_BSC_LOCK(sc); bcm_bsc_reset(sc); BCM_BSC_UNLOCK(sc); sc->sc_iicbus = device_add_child(dev, "iicbus", -1); if (sc->sc_iicbus == NULL) { bcm_bsc_detach(dev); return (ENXIO); } - return (bus_generic_attach(dev)); + /* Probe and attach the iicbus when interrupts are available. */ + config_intrhook_oneshot((ich_func_t)bus_generic_attach, dev); + + return (0); } static int bcm_bsc_detach(device_t dev) { struct bcm_bsc_softc *sc; bus_generic_detach(dev); sc = device_get_softc(dev); mtx_destroy(&sc->sc_mtx); if (sc->sc_intrhand) bus_teardown_intr(dev, sc->sc_irq_res, sc->sc_intrhand); if (sc->sc_irq_res) bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sc_irq_res); if (sc->sc_mem_res) bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->sc_mem_res); return (0); } static void bcm_bsc_intr(void *arg) { struct bcm_bsc_softc *sc; uint32_t status; sc = (struct bcm_bsc_softc *)arg; BCM_BSC_LOCK(sc); /* The I2C interrupt is shared among all the BSC controllers. */ if ((sc->sc_flags & BCM_I2C_BUSY) == 0) { BCM_BSC_UNLOCK(sc); return; } status = BCM_BSC_READ(sc, BCM_BSC_STATUS); /* Check for errors. */ if (status & (BCM_BSC_STATUS_CLKT | BCM_BSC_STATUS_ERR)) { /* Disable interrupts. */ bcm_bsc_reset(sc); sc->sc_flags |= BCM_I2C_ERROR; wakeup(sc->sc_dev); BCM_BSC_UNLOCK(sc); return; } if (sc->sc_flags & BCM_I2C_READ) { while (sc->sc_resid > 0 && (status & BCM_BSC_STATUS_RXD)) { *sc->sc_data++ = BCM_BSC_READ(sc, BCM_BSC_DATA); sc->sc_resid--; status = BCM_BSC_READ(sc, BCM_BSC_STATUS); } } else { while (sc->sc_resid > 0 && (status & BCM_BSC_STATUS_TXD)) { BCM_BSC_WRITE(sc, BCM_BSC_DATA, *sc->sc_data++); sc->sc_resid--; status = BCM_BSC_READ(sc, BCM_BSC_STATUS); } } if (status & BCM_BSC_STATUS_DONE) { /* Disable interrupts. */ bcm_bsc_reset(sc); wakeup(sc->sc_dev); } BCM_BSC_UNLOCK(sc); } static int bcm_bsc_transfer(device_t dev, struct iic_msg *msgs, uint32_t nmsgs) { struct bcm_bsc_softc *sc; uint32_t intr, read, status; int i, err; sc = device_get_softc(dev); BCM_BSC_LOCK(sc); /* If the controller is busy wait until it is available. */ while (sc->sc_flags & BCM_I2C_BUSY) mtx_sleep(dev, &sc->sc_mtx, 0, "bscbusw", 0); /* Now we have control over the BSC controller. */ sc->sc_flags = BCM_I2C_BUSY; /* Clear the FIFO and the pending interrupts. */ bcm_bsc_reset(sc); err = 0; for (i = 0; i < nmsgs; i++) { /* Write the slave address. */ BCM_BSC_WRITE(sc, BCM_BSC_SLAVE, msgs[i].slave >> 1); /* Write the data length. */ BCM_BSC_WRITE(sc, BCM_BSC_DLEN, msgs[i].len); sc->sc_data = msgs[i].buf; sc->sc_resid = msgs[i].len; if ((msgs[i].flags & IIC_M_RD) == 0) { /* Fill up the TX FIFO. */ status = BCM_BSC_READ(sc, BCM_BSC_STATUS); while (sc->sc_resid > 0 && (status & BCM_BSC_STATUS_TXD)) { BCM_BSC_WRITE(sc, BCM_BSC_DATA, *sc->sc_data); sc->sc_data++; sc->sc_resid--; status = BCM_BSC_READ(sc, BCM_BSC_STATUS); } read = 0; intr = BCM_BSC_CTRL_INTT; sc->sc_flags &= ~BCM_I2C_READ; } else { sc->sc_flags |= BCM_I2C_READ; read = BCM_BSC_CTRL_READ; intr = BCM_BSC_CTRL_INTR; } intr |= BCM_BSC_CTRL_INTD; /* Start the transfer. */ BCM_BSC_WRITE(sc, BCM_BSC_CTRL, BCM_BSC_CTRL_I2CEN | BCM_BSC_CTRL_ST | read | intr); /* Wait for the transaction to complete. */ err = mtx_sleep(dev, &sc->sc_mtx, 0, "bsciow", hz); /* Check for errors. */ if (err == 0 && (sc->sc_flags & BCM_I2C_ERROR)) err = EIO; if (err != 0) break; } /* Clean the controller flags. */ sc->sc_flags = 0; /* Wake up the threads waiting for bus. */ wakeup(dev); BCM_BSC_UNLOCK(sc); return (err); } static int bcm_bsc_iicbus_reset(device_t dev, u_char speed, u_char addr, u_char *oldaddr) { struct bcm_bsc_softc *sc; uint32_t busfreq; sc = device_get_softc(dev); BCM_BSC_LOCK(sc); bcm_bsc_reset(sc); if (sc->sc_iicbus == NULL) busfreq = 100000; else busfreq = IICBUS_GET_FREQUENCY(sc->sc_iicbus, speed); BCM_BSC_WRITE(sc, BCM_BSC_CLOCK, BCM_BSC_CORE_CLK / busfreq); BCM_BSC_UNLOCK(sc); return (IIC_ENOADDR); } static phandle_t bcm_bsc_get_node(device_t bus, device_t dev) { /* We only have one child, the I2C bus, which needs our own node. */ return (ofw_bus_get_node(bus)); } static device_method_t bcm_bsc_methods[] = { /* Device interface */ DEVMETHOD(device_probe, bcm_bsc_probe), DEVMETHOD(device_attach, bcm_bsc_attach), DEVMETHOD(device_detach, bcm_bsc_detach), /* iicbus interface */ DEVMETHOD(iicbus_reset, bcm_bsc_iicbus_reset), DEVMETHOD(iicbus_callback, iicbus_null_callback), DEVMETHOD(iicbus_transfer, bcm_bsc_transfer), /* ofw_bus interface */ DEVMETHOD(ofw_bus_get_node, bcm_bsc_get_node), DEVMETHOD_END }; static devclass_t bcm_bsc_devclass; static driver_t bcm_bsc_driver = { "iichb", bcm_bsc_methods, sizeof(struct bcm_bsc_softc), }; DRIVER_MODULE(iicbus, bcm2835_bsc, iicbus_driver, iicbus_devclass, 0, 0); DRIVER_MODULE(bcm2835_bsc, simplebus, bcm_bsc_driver, bcm_bsc_devclass, 0, 0); Index: head/sys/arm/freescale/imx/imx_i2c.c =================================================================== --- head/sys/arm/freescale/imx/imx_i2c.c (revision 323552) +++ head/sys/arm/freescale/imx/imx_i2c.c (revision 323553) @@ -1,656 +1,657 @@ /*- * Copyright (C) 2008-2009 Semihalf, Michal Hajduk * Copyright (c) 2012, 2013 The FreeBSD Foundation * Copyright (c) 2015 Ian Lepore * All rights reserved. * * Portions of this software were developed by Oleksandr Rybalko * under sponsorship from the FreeBSD Foundation. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. */ /* * I2C driver for Freescale i.MX hardware. * * Note that the hardware is capable of running as both a master and a slave. * This driver currently implements only master-mode operations. * * This driver supports multi-master i2c buses, by detecting bus arbitration * loss and returning IIC_EBUSBSY status. Notably, it does not do any kind of * retries if some other master jumps onto the bus and interrupts one of our * transfer cycles resulting in arbitration loss in mid-transfer. The caller * must handle retries in a way that makes sense for the slave being addressed. */ #include __FBSDID("$FreeBSD$"); #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include "iicbus_if.h" #include #include #include #include #include #define I2C_ADDR_REG 0x00 /* I2C slave address register */ #define I2C_FDR_REG 0x04 /* I2C frequency divider register */ #define I2C_CONTROL_REG 0x08 /* I2C control register */ #define I2C_STATUS_REG 0x0C /* I2C status register */ #define I2C_DATA_REG 0x10 /* I2C data register */ #define I2C_DFSRR_REG 0x14 /* I2C Digital Filter Sampling rate */ #define I2CCR_MEN (1 << 7) /* Module enable */ #define I2CCR_MSTA (1 << 5) /* Master/slave mode */ #define I2CCR_MTX (1 << 4) /* Transmit/receive mode */ #define I2CCR_TXAK (1 << 3) /* Transfer acknowledge */ #define I2CCR_RSTA (1 << 2) /* Repeated START */ #define I2CSR_MCF (1 << 7) /* Data transfer */ #define I2CSR_MASS (1 << 6) /* Addressed as a slave */ #define I2CSR_MBB (1 << 5) /* Bus busy */ #define I2CSR_MAL (1 << 4) /* Arbitration lost */ #define I2CSR_SRW (1 << 2) /* Slave read/write */ #define I2CSR_MIF (1 << 1) /* Module interrupt */ #define I2CSR_RXAK (1 << 0) /* Received acknowledge */ #define I2C_BAUD_RATE_FAST 0x31 #define I2C_BAUD_RATE_DEF 0x3F #define I2C_DFSSR_DIV 0x10 /* * A table of available divisors and the associated coded values to put in the * FDR register to achieve that divisor.. There is no algorithmic relationship I * can see between divisors and the codes that go into the register. The table * begins and ends with entries that handle insane configuration values. */ struct clkdiv { u_int divisor; u_int regcode; }; static struct clkdiv clkdiv_table[] = { { 0, 0x20 }, { 22, 0x20 }, { 24, 0x21 }, { 26, 0x22 }, { 28, 0x23 }, { 30, 0x00 }, { 32, 0x24 }, { 36, 0x25 }, { 40, 0x26 }, { 42, 0x03 }, { 44, 0x27 }, { 48, 0x28 }, { 52, 0x05 }, { 56, 0x29 }, { 60, 0x06 }, { 64, 0x2a }, { 72, 0x2b }, { 80, 0x2c }, { 88, 0x09 }, { 96, 0x2d }, { 104, 0x0a }, { 112, 0x2e }, { 128, 0x2f }, { 144, 0x0c }, { 160, 0x30 }, { 192, 0x31 }, { 224, 0x32 }, { 240, 0x0f }, { 256, 0x33 }, { 288, 0x10 }, { 320, 0x34 }, { 384, 0x35 }, { 448, 0x36 }, { 480, 0x13 }, { 512, 0x37 }, { 576, 0x14 }, { 640, 0x38 }, { 768, 0x39 }, { 896, 0x3a }, { 960, 0x17 }, { 1024, 0x3b }, { 1152, 0x18 }, { 1280, 0x3c }, { 1536, 0x3d }, { 1792, 0x3e }, { 1920, 0x1b }, { 2048, 0x3f }, { 2304, 0x1c }, { 2560, 0x1d }, { 3072, 0x1e }, { 3840, 0x1f }, {UINT_MAX, 0x1f} }; static struct ofw_compat_data compat_data[] = { {"fsl,imx6q-i2c", 1}, {"fsl,imx-i2c", 1}, {NULL, 0} }; struct i2c_softc { device_t dev; device_t iicbus; struct resource *res; int rid; sbintime_t byte_time_sbt; int rb_pinctl_idx; gpio_pin_t rb_sclpin; gpio_pin_t rb_sdapin; u_int debug; u_int slave; }; #define DEVICE_DEBUGF(sc, lvl, fmt, args...) \ if ((lvl) <= (sc)->debug) \ device_printf((sc)->dev, fmt, ##args) #define DEBUGF(sc, lvl, fmt, args...) \ if ((lvl) <= (sc)->debug) \ printf(fmt, ##args) static phandle_t i2c_get_node(device_t, device_t); static int i2c_probe(device_t); static int i2c_attach(device_t); static int i2c_repeated_start(device_t, u_char, int); static int i2c_start(device_t, u_char, int); static int i2c_stop(device_t); static int i2c_reset(device_t, u_char, u_char, u_char *); static int i2c_read(device_t, char *, int, int *, int, int); static int i2c_write(device_t, const char *, int, int *, int); static device_method_t i2c_methods[] = { DEVMETHOD(device_probe, i2c_probe), DEVMETHOD(device_attach, i2c_attach), /* OFW methods */ DEVMETHOD(ofw_bus_get_node, i2c_get_node), DEVMETHOD(iicbus_callback, iicbus_null_callback), DEVMETHOD(iicbus_repeated_start, i2c_repeated_start), DEVMETHOD(iicbus_start, i2c_start), DEVMETHOD(iicbus_stop, i2c_stop), DEVMETHOD(iicbus_reset, i2c_reset), DEVMETHOD(iicbus_read, i2c_read), DEVMETHOD(iicbus_write, i2c_write), DEVMETHOD(iicbus_transfer, iicbus_transfer_gen), DEVMETHOD_END }; static driver_t i2c_driver = { "iichb", i2c_methods, sizeof(struct i2c_softc), }; static devclass_t i2c_devclass; DRIVER_MODULE(i2c, simplebus, i2c_driver, i2c_devclass, 0, 0); DRIVER_MODULE(iicbus, i2c, iicbus_driver, iicbus_devclass, 0, 0); static phandle_t i2c_get_node(device_t bus, device_t dev) { /* * Share controller node with iicbus device */ return ofw_bus_get_node(bus); } static __inline void i2c_write_reg(struct i2c_softc *sc, bus_size_t off, uint8_t val) { bus_write_1(sc->res, off, val); } static __inline uint8_t i2c_read_reg(struct i2c_softc *sc, bus_size_t off) { return (bus_read_1(sc->res, off)); } static __inline void i2c_flag_set(struct i2c_softc *sc, bus_size_t off, uint8_t mask) { uint8_t status; status = i2c_read_reg(sc, off); status |= mask; i2c_write_reg(sc, off, status); } /* Wait for bus to become busy or not-busy. */ static int wait_for_busbusy(struct i2c_softc *sc, int wantbusy) { int retry, srb; retry = 1000; while (retry --) { srb = i2c_read_reg(sc, I2C_STATUS_REG) & I2CSR_MBB; if ((srb && wantbusy) || (!srb && !wantbusy)) return (IIC_NOERR); DELAY(1); } return (IIC_ETIMEOUT); } /* Wait for transfer to complete, optionally check RXAK. */ static int wait_for_xfer(struct i2c_softc *sc, int checkack) { int retry, sr; /* * Sleep for about the time it takes to transfer a byte (with precision * set to tolerate 5% oversleep). We calculate the approximate byte * transfer time when we set the bus speed divisor. Slaves are allowed * to do clock-stretching so the actual transfer time can be larger, but * this gets the bulk of the waiting out of the way without tying up the * processor the whole time. */ pause_sbt("imxi2c", sc->byte_time_sbt, sc->byte_time_sbt / 20, 0); retry = 10000; while (retry --) { sr = i2c_read_reg(sc, I2C_STATUS_REG); if (sr & I2CSR_MIF) { if (sr & I2CSR_MAL) return (IIC_EBUSERR); else if (checkack && (sr & I2CSR_RXAK)) return (IIC_ENOACK); else return (IIC_NOERR); } DELAY(1); } return (IIC_ETIMEOUT); } /* * Implement the error handling shown in the state diagram of the imx6 reference * manual. If there was an error, then: * - Clear master mode (MSTA and MTX). * - Wait for the bus to become free or for a timeout to happen. * - Disable the controller. */ static int i2c_error_handler(struct i2c_softc *sc, int error) { if (error != 0) { i2c_write_reg(sc, I2C_STATUS_REG, 0); i2c_write_reg(sc, I2C_CONTROL_REG, I2CCR_MEN); wait_for_busbusy(sc, false); i2c_write_reg(sc, I2C_CONTROL_REG, 0); } return (error); } static int i2c_recover_getsda(void *ctx) { bool active; gpio_pin_is_active(((struct i2c_softc *)ctx)->rb_sdapin, &active); return (active); } static void i2c_recover_setsda(void *ctx, int value) { gpio_pin_set_active(((struct i2c_softc *)ctx)->rb_sdapin, value); } static int i2c_recover_getscl(void *ctx) { bool active; gpio_pin_is_active(((struct i2c_softc *)ctx)->rb_sclpin, &active); return (active); } static void i2c_recover_setscl(void *ctx, int value) { gpio_pin_set_active(((struct i2c_softc *)ctx)->rb_sclpin, value); } static int i2c_recover_bus(struct i2c_softc *sc) { struct iicrb_pin_access pins; int err; /* * If we have gpio pinmux config, reconfigure the pins to gpio mode, * invoke iic_recover_bus which checks for a hung bus and bitbangs a * recovery sequence if necessary, then configure the pins back to i2c * mode (idx 0). */ if (sc->rb_pinctl_idx == 0) return (0); fdt_pinctrl_configure(sc->dev, sc->rb_pinctl_idx); pins.ctx = sc; pins.getsda = i2c_recover_getsda; pins.setsda = i2c_recover_setsda; pins.getscl = i2c_recover_getscl; pins.setscl = i2c_recover_setscl; err = iic_recover_bus(&pins); fdt_pinctrl_configure(sc->dev, 0); return (err); } static int i2c_probe(device_t dev) { if (!ofw_bus_status_okay(dev)) return (ENXIO); if (ofw_bus_search_compatible(dev, compat_data)->ocd_data == 0) return (ENXIO); device_set_desc(dev, "Freescale i.MX I2C"); return (BUS_PROBE_DEFAULT); } static int i2c_attach(device_t dev) { char wrkstr[16]; struct i2c_softc *sc; phandle_t node; int err, cfgidx; sc = device_get_softc(dev); sc->dev = dev; sc->rid = 0; sc->res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &sc->rid, RF_ACTIVE); if (sc->res == NULL) { device_printf(dev, "could not allocate resources"); return (ENXIO); } sc->iicbus = device_add_child(dev, "iicbus", -1); if (sc->iicbus == NULL) { device_printf(dev, "could not add iicbus child"); return (ENXIO); } /* Set up debug-enable sysctl. */ SYSCTL_ADD_INT(device_get_sysctl_ctx(sc->dev), SYSCTL_CHILDREN(device_get_sysctl_tree(sc->dev)), OID_AUTO, "debug", CTLFLAG_RWTUN, &sc->debug, 0, "Enable debug; 1=reads/writes, 2=add starts/stops"); /* * Set up for bus recovery using gpio pins, if the pinctrl and gpio * properties are present. This is optional. If all the config data is * not in place, we just don't do gpio bitbang bus recovery. */ node = ofw_bus_get_node(sc->dev); err = gpio_pin_get_by_ofw_property(dev, node, "scl-gpios", &sc->rb_sclpin); if (err != 0) goto no_recovery; err = gpio_pin_get_by_ofw_property(dev, node, "sda-gpios", &sc->rb_sdapin); if (err != 0) goto no_recovery; /* * Preset the gpio pins to output high (idle bus state). The signal * won't actually appear on the pins until the bus recovery code changes * the pinmux config from i2c to gpio. */ gpio_pin_setflags(sc->rb_sclpin, GPIO_PIN_OUTPUT); gpio_pin_setflags(sc->rb_sdapin, GPIO_PIN_OUTPUT); gpio_pin_set_active(sc->rb_sclpin, true); gpio_pin_set_active(sc->rb_sdapin, true); /* * Obtain the index of pinctrl node for bus recovery using gpio pins, * then confirm that pinctrl properties exist for that index and for the * default pinctrl-0. If sc->rb_pinctl_idx is non-zero, the reset code * will also do a bus recovery, so setting this value must be last. */ err = ofw_bus_find_string_index(node, "pinctrl-names", "gpio", &cfgidx); if (err == 0) { snprintf(wrkstr, sizeof(wrkstr), "pinctrl-%d", cfgidx); if (OF_hasprop(node, "pinctrl-0") && OF_hasprop(node, wrkstr)) sc->rb_pinctl_idx = cfgidx; } no_recovery: /* We don't do a hardware reset here because iicbus_attach() does it. */ - bus_generic_attach(dev); + /* Probe and attach the iicbus when interrupts are available. */ + config_intrhook_oneshot((ich_func_t)bus_generic_attach, dev); return (0); } static int i2c_repeated_start(device_t dev, u_char slave, int timeout) { struct i2c_softc *sc; int error; sc = device_get_softc(dev); if ((i2c_read_reg(sc, I2C_STATUS_REG) & I2CSR_MBB) == 0) { return (IIC_EBUSERR); } /* * Set repeated start condition, delay (per reference manual, min 156nS) * before writing slave address, wait for ack after write. */ i2c_flag_set(sc, I2C_CONTROL_REG, I2CCR_RSTA); DELAY(1); i2c_write_reg(sc, I2C_STATUS_REG, 0x0); i2c_write_reg(sc, I2C_DATA_REG, slave); sc->slave = slave; DEVICE_DEBUGF(sc, 2, "rstart 0x%02x\n", sc->slave); error = wait_for_xfer(sc, true); return (i2c_error_handler(sc, error)); } static int i2c_start_ll(device_t dev, u_char slave, int timeout) { struct i2c_softc *sc; int error; sc = device_get_softc(dev); i2c_write_reg(sc, I2C_CONTROL_REG, I2CCR_MEN); DELAY(10); /* Delay for controller to sample bus state. */ if (i2c_read_reg(sc, I2C_STATUS_REG) & I2CSR_MBB) { return (i2c_error_handler(sc, IIC_EBUSERR)); } i2c_write_reg(sc, I2C_CONTROL_REG, I2CCR_MEN | I2CCR_MSTA | I2CCR_MTX); if ((error = wait_for_busbusy(sc, true)) != IIC_NOERR) return (i2c_error_handler(sc, error)); i2c_write_reg(sc, I2C_STATUS_REG, 0); i2c_write_reg(sc, I2C_DATA_REG, slave); sc->slave = slave; DEVICE_DEBUGF(sc, 2, "start 0x%02x\n", sc->slave); error = wait_for_xfer(sc, true); return (i2c_error_handler(sc, error)); } static int i2c_start(device_t dev, u_char slave, int timeout) { struct i2c_softc *sc; int error; sc = device_get_softc(dev); /* * Invoke the low-level code to put the bus into master mode and address * the given slave. If that fails, idle the controller and attempt a * bus recovery, and then try again one time. Signaling a start and * addressing the slave is the only operation that a low-level driver * can safely retry without any help from the upper layers that know * more about the slave device. */ if ((error = i2c_start_ll(dev, slave, timeout)) != 0) { i2c_write_reg(sc, I2C_CONTROL_REG, 0x0); if ((error = i2c_recover_bus(sc)) != 0) return (error); error = i2c_start_ll(dev, slave, timeout); } return (error); } static int i2c_stop(device_t dev) { struct i2c_softc *sc; sc = device_get_softc(dev); i2c_write_reg(sc, I2C_CONTROL_REG, I2CCR_MEN); wait_for_busbusy(sc, false); i2c_write_reg(sc, I2C_CONTROL_REG, 0); DEVICE_DEBUGF(sc, 2, "stop 0x%02x\n", sc->slave); return (IIC_NOERR); } static int i2c_reset(device_t dev, u_char speed, u_char addr, u_char *oldadr) { struct i2c_softc *sc; u_int busfreq, div, i, ipgfreq; sc = device_get_softc(dev); DEVICE_DEBUGF(sc, 1, "reset\n"); /* * Look up the divisor that gives the nearest speed that doesn't exceed * the configured value for the bus. */ ipgfreq = imx_ccm_ipg_hz(); busfreq = IICBUS_GET_FREQUENCY(sc->iicbus, speed); div = howmany(ipgfreq, busfreq); for (i = 0; i < nitems(clkdiv_table); i++) { if (clkdiv_table[i].divisor >= div) break; } /* * Calculate roughly how long it will take to transfer a byte (which * requires 9 clock cycles) at the new bus speed. This value is used to * pause() while waiting for transfer-complete. With a 66MHz IPG clock * and the actual i2c bus speeds that leads to, for nominal 100KHz and * 400KHz bus speeds the transfer times are roughly 104uS and 22uS. */ busfreq = ipgfreq / clkdiv_table[i].divisor; sc->byte_time_sbt = SBT_1US * (9000000 / busfreq); /* * Disable the controller (do the reset), and set the new clock divisor. */ i2c_write_reg(sc, I2C_STATUS_REG, 0x0); i2c_write_reg(sc, I2C_CONTROL_REG, 0x0); i2c_write_reg(sc, I2C_FDR_REG, (uint8_t)clkdiv_table[i].regcode); /* * Now that the controller is idle, perform bus recovery. If the bus * isn't hung, this a fairly fast no-op. */ return (i2c_recover_bus(sc)); } static int i2c_read(device_t dev, char *buf, int len, int *read, int last, int delay) { struct i2c_softc *sc; int error, reg; sc = device_get_softc(dev); *read = 0; DEVICE_DEBUGF(sc, 1, "read 0x%02x len %d: ", sc->slave, len); if (len) { if (len == 1) i2c_write_reg(sc, I2C_CONTROL_REG, I2CCR_MEN | I2CCR_MSTA | I2CCR_TXAK); else i2c_write_reg(sc, I2C_CONTROL_REG, I2CCR_MEN | I2CCR_MSTA); /* Dummy read to prime the receiver. */ i2c_write_reg(sc, I2C_STATUS_REG, 0x0); i2c_read_reg(sc, I2C_DATA_REG); } error = 0; *read = 0; while (*read < len) { if ((error = wait_for_xfer(sc, false)) != IIC_NOERR) break; i2c_write_reg(sc, I2C_STATUS_REG, 0x0); if (last) { if (*read == len - 2) { /* NO ACK on last byte */ i2c_write_reg(sc, I2C_CONTROL_REG, I2CCR_MEN | I2CCR_MSTA | I2CCR_TXAK); } else if (*read == len - 1) { /* Transfer done, signal stop. */ i2c_write_reg(sc, I2C_CONTROL_REG, I2CCR_MEN | I2CCR_TXAK); wait_for_busbusy(sc, false); } } reg = i2c_read_reg(sc, I2C_DATA_REG); DEBUGF(sc, 1, "0x%02x ", reg); *buf++ = reg; (*read)++; } DEBUGF(sc, 1, "\n"); return (i2c_error_handler(sc, error)); } static int i2c_write(device_t dev, const char *buf, int len, int *sent, int timeout) { struct i2c_softc *sc; int error; sc = device_get_softc(dev); error = 0; *sent = 0; DEVICE_DEBUGF(sc, 1, "write 0x%02x len %d: ", sc->slave, len); while (*sent < len) { DEBUGF(sc, 1, "0x%02x ", *buf); i2c_write_reg(sc, I2C_STATUS_REG, 0x0); i2c_write_reg(sc, I2C_DATA_REG, *buf++); if ((error = wait_for_xfer(sc, true)) != IIC_NOERR) break; (*sent)++; } DEBUGF(sc, 1, "\n"); return (i2c_error_handler(sc, error)); } Index: head/sys/arm/ti/ti_i2c.c =================================================================== --- head/sys/arm/ti/ti_i2c.c (revision 323552) +++ head/sys/arm/ti/ti_i2c.c (revision 323553) @@ -1,988 +1,983 @@ /*- * Copyright (c) 2011 Ben Gray . * Copyright (c) 2014 Luiz Otavio O Souza . * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. */ /** * Driver for the I2C module on the TI SoC. * * This driver is heavily based on the TWI driver for the AT91 (at91_twi.c). * * CAUTION: The I2Ci registers are limited to 16 bit and 8 bit data accesses, * 32 bit data access is not allowed and can corrupt register content. * * This driver currently doesn't use DMA for the transfer, although I hope to * incorporate that sometime in the future. The idea being that for transaction * larger than a certain size the DMA engine is used, for anything less the * normal interrupt/fifo driven option is used. - * - * - * WARNING: This driver uses mtx_sleep and interrupts to perform transactions, - * which means you can't do a transaction during startup before the interrupts - * have been enabled. Hint - the freebsd function config_intrhook_establish(). */ #include __FBSDID("$FreeBSD$"); #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include "iicbus_if.h" /** * I2C device driver context, a pointer to this is stored in the device * driver structure. */ struct ti_i2c_softc { device_t sc_dev; clk_ident_t clk_id; struct resource* sc_irq_res; struct resource* sc_mem_res; device_t sc_iicbus; void* sc_irq_h; struct mtx sc_mtx; struct iic_msg* sc_buffer; int sc_bus_inuse; int sc_buffer_pos; int sc_error; int sc_fifo_trsh; int sc_timeout; uint16_t sc_con_reg; uint16_t sc_rev; }; struct ti_i2c_clock_config { u_int frequency; /* Bus frequency in Hz */ uint8_t psc; /* Fast/Standard mode prescale divider */ uint8_t scll; /* Fast/Standard mode SCL low time */ uint8_t sclh; /* Fast/Standard mode SCL high time */ uint8_t hsscll; /* High Speed mode SCL low time */ uint8_t hssclh; /* High Speed mode SCL high time */ }; #if defined(SOC_OMAP4) /* * OMAP4 i2c bus clock is 96MHz / ((psc + 1) * (scll + 7 + sclh + 5)). * The prescaler values for 100KHz and 400KHz modes come from the table in the * OMAP4 TRM. The table doesn't list 1MHz; these values should give that speed. */ static struct ti_i2c_clock_config ti_omap4_i2c_clock_configs[] = { { 100000, 23, 13, 15, 0, 0}, { 400000, 9, 5, 7, 0, 0}, { 1000000, 3, 5, 7, 0, 0}, /* { 3200000, 1, 113, 115, 7, 10}, - HS mode */ { 0 /* Table terminator */ } }; #endif #if defined(SOC_TI_AM335X) /* * AM335x i2c bus clock is 48MHZ / ((psc + 1) * (scll + 7 + sclh + 5)) * In all cases we prescale the clock to 24MHz as recommended in the manual. */ static struct ti_i2c_clock_config ti_am335x_i2c_clock_configs[] = { { 100000, 1, 111, 117, 0, 0}, { 400000, 1, 23, 25, 0, 0}, { 1000000, 1, 5, 7, 0, 0}, { 0 /* Table terminator */ } }; #endif /** * Locking macros used throughout the driver */ #define TI_I2C_LOCK(_sc) mtx_lock(&(_sc)->sc_mtx) #define TI_I2C_UNLOCK(_sc) mtx_unlock(&(_sc)->sc_mtx) #define TI_I2C_LOCK_INIT(_sc) \ mtx_init(&_sc->sc_mtx, device_get_nameunit(_sc->sc_dev), \ "ti_i2c", MTX_DEF) #define TI_I2C_LOCK_DESTROY(_sc) mtx_destroy(&_sc->sc_mtx) #define TI_I2C_ASSERT_LOCKED(_sc) mtx_assert(&_sc->sc_mtx, MA_OWNED) #define TI_I2C_ASSERT_UNLOCKED(_sc) mtx_assert(&_sc->sc_mtx, MA_NOTOWNED) #ifdef DEBUG #define ti_i2c_dbg(_sc, fmt, args...) \ device_printf((_sc)->sc_dev, fmt, ##args) #else #define ti_i2c_dbg(_sc, fmt, args...) #endif /** * ti_i2c_read_2 - reads a 16-bit value from one of the I2C registers * @sc: I2C device context * @off: the byte offset within the register bank to read from. * * * LOCKING: * No locking required * * RETURNS: * 16-bit value read from the register. */ static inline uint16_t ti_i2c_read_2(struct ti_i2c_softc *sc, bus_size_t off) { return (bus_read_2(sc->sc_mem_res, off)); } /** * ti_i2c_write_2 - writes a 16-bit value to one of the I2C registers * @sc: I2C device context * @off: the byte offset within the register bank to read from. * @val: the value to write into the register * * LOCKING: * No locking required * * RETURNS: * 16-bit value read from the register. */ static inline void ti_i2c_write_2(struct ti_i2c_softc *sc, bus_size_t off, uint16_t val) { bus_write_2(sc->sc_mem_res, off, val); } static int ti_i2c_transfer_intr(struct ti_i2c_softc* sc, uint16_t status) { int amount, done, i; done = 0; amount = 0; /* Check for the error conditions. */ if (status & I2C_STAT_NACK) { /* No ACK from slave. */ ti_i2c_dbg(sc, "NACK\n"); ti_i2c_write_2(sc, I2C_REG_STATUS, I2C_STAT_NACK); sc->sc_error = ENXIO; } else if (status & I2C_STAT_AL) { /* Arbitration lost. */ ti_i2c_dbg(sc, "Arbitration lost\n"); ti_i2c_write_2(sc, I2C_REG_STATUS, I2C_STAT_AL); sc->sc_error = ENXIO; } /* Check if we have finished. */ if (status & I2C_STAT_ARDY) { /* Register access ready - transaction complete basically. */ ti_i2c_dbg(sc, "ARDY transaction complete\n"); if (sc->sc_error != 0 && sc->sc_buffer->flags & IIC_M_NOSTOP) { ti_i2c_write_2(sc, I2C_REG_CON, sc->sc_con_reg | I2C_CON_STP); } ti_i2c_write_2(sc, I2C_REG_STATUS, I2C_STAT_ARDY | I2C_STAT_RDR | I2C_STAT_RRDY | I2C_STAT_XDR | I2C_STAT_XRDY); return (1); } if (sc->sc_buffer->flags & IIC_M_RD) { /* Read some data. */ if (status & I2C_STAT_RDR) { /* * Receive draining interrupt - last data received. * The set FIFO threshold won't be reached to trigger * RRDY. */ ti_i2c_dbg(sc, "Receive draining interrupt\n"); /* * Drain the FIFO. Read the pending data in the FIFO. */ amount = sc->sc_buffer->len - sc->sc_buffer_pos; } else if (status & I2C_STAT_RRDY) { /* * Receive data ready interrupt - FIFO has reached the * set threshold. */ ti_i2c_dbg(sc, "Receive data ready interrupt\n"); amount = min(sc->sc_fifo_trsh, sc->sc_buffer->len - sc->sc_buffer_pos); } /* Read the bytes from the fifo. */ for (i = 0; i < amount; i++) sc->sc_buffer->buf[sc->sc_buffer_pos++] = (uint8_t)(ti_i2c_read_2(sc, I2C_REG_DATA) & 0xff); if (status & I2C_STAT_RDR) ti_i2c_write_2(sc, I2C_REG_STATUS, I2C_STAT_RDR); if (status & I2C_STAT_RRDY) ti_i2c_write_2(sc, I2C_REG_STATUS, I2C_STAT_RRDY); } else { /* Write some data. */ if (status & I2C_STAT_XDR) { /* * Transmit draining interrupt - FIFO level is below * the set threshold and the amount of data still to * be transferred won't reach the set FIFO threshold. */ ti_i2c_dbg(sc, "Transmit draining interrupt\n"); /* * Drain the TX data. Write the pending data in the * FIFO. */ amount = sc->sc_buffer->len - sc->sc_buffer_pos; } else if (status & I2C_STAT_XRDY) { /* * Transmit data ready interrupt - the FIFO level * is below the set threshold. */ ti_i2c_dbg(sc, "Transmit data ready interrupt\n"); amount = min(sc->sc_fifo_trsh, sc->sc_buffer->len - sc->sc_buffer_pos); } /* Write the bytes from the fifo. */ for (i = 0; i < amount; i++) ti_i2c_write_2(sc, I2C_REG_DATA, sc->sc_buffer->buf[sc->sc_buffer_pos++]); if (status & I2C_STAT_XDR) ti_i2c_write_2(sc, I2C_REG_STATUS, I2C_STAT_XDR); if (status & I2C_STAT_XRDY) ti_i2c_write_2(sc, I2C_REG_STATUS, I2C_STAT_XRDY); } return (done); } /** * ti_i2c_intr - interrupt handler for the I2C module * @dev: i2c device handle * * * * LOCKING: * Called from timer context * * RETURNS: * EH_HANDLED or EH_NOT_HANDLED */ static void ti_i2c_intr(void *arg) { int done; struct ti_i2c_softc *sc; uint16_t events, status; sc = (struct ti_i2c_softc *)arg; TI_I2C_LOCK(sc); status = ti_i2c_read_2(sc, I2C_REG_STATUS); if (status == 0) { TI_I2C_UNLOCK(sc); return; } /* Save enabled interrupts. */ events = ti_i2c_read_2(sc, I2C_REG_IRQENABLE_SET); /* We only care about enabled interrupts. */ status &= events; done = 0; if (sc->sc_buffer != NULL) done = ti_i2c_transfer_intr(sc, status); else { ti_i2c_dbg(sc, "Transfer interrupt without buffer\n"); sc->sc_error = EINVAL; done = 1; } if (done) /* Wakeup the process that started the transaction. */ wakeup(sc); TI_I2C_UNLOCK(sc); } /** * ti_i2c_transfer - called to perform the transfer * @dev: i2c device handle * @msgs: the messages to send/receive * @nmsgs: the number of messages in the msgs array * * * LOCKING: * Internally locked * * RETURNS: * 0 on function succeeded * EINVAL if invalid message is passed as an arg */ static int ti_i2c_transfer(device_t dev, struct iic_msg *msgs, uint32_t nmsgs) { int err, i, repstart, timeout; struct ti_i2c_softc *sc; uint16_t reg; sc = device_get_softc(dev); TI_I2C_LOCK(sc); /* If the controller is busy wait until it is available. */ while (sc->sc_bus_inuse == 1) mtx_sleep(sc, &sc->sc_mtx, 0, "i2cbuswait", 0); /* Now we have control over the I2C controller. */ sc->sc_bus_inuse = 1; err = 0; repstart = 0; for (i = 0; i < nmsgs; i++) { sc->sc_buffer = &msgs[i]; sc->sc_buffer_pos = 0; sc->sc_error = 0; /* Zero byte transfers aren't allowed. */ if (sc->sc_buffer == NULL || sc->sc_buffer->buf == NULL || sc->sc_buffer->len == 0) { err = EINVAL; break; } /* Check if the i2c bus is free. */ if (repstart == 0) { /* * On repeated start we send the START condition while * the bus _is_ busy. */ timeout = 0; while (ti_i2c_read_2(sc, I2C_REG_STATUS_RAW) & I2C_STAT_BB) { if (timeout++ > 100) { err = EBUSY; goto out; } DELAY(1000); } timeout = 0; } else repstart = 0; if (sc->sc_buffer->flags & IIC_M_NOSTOP) repstart = 1; /* Set the slave address. */ ti_i2c_write_2(sc, I2C_REG_SA, msgs[i].slave >> 1); /* Write the data length. */ ti_i2c_write_2(sc, I2C_REG_CNT, sc->sc_buffer->len); /* Clear the RX and the TX FIFO. */ reg = ti_i2c_read_2(sc, I2C_REG_BUF); reg |= I2C_BUF_RXFIFO_CLR | I2C_BUF_TXFIFO_CLR; ti_i2c_write_2(sc, I2C_REG_BUF, reg); reg = sc->sc_con_reg | I2C_CON_STT; if (repstart == 0) reg |= I2C_CON_STP; if ((sc->sc_buffer->flags & IIC_M_RD) == 0) reg |= I2C_CON_TRX; ti_i2c_write_2(sc, I2C_REG_CON, reg); /* Wait for an event. */ err = mtx_sleep(sc, &sc->sc_mtx, 0, "i2ciowait", sc->sc_timeout); if (err == 0) err = sc->sc_error; if (err) break; } out: if (timeout == 0) { while (ti_i2c_read_2(sc, I2C_REG_STATUS_RAW) & I2C_STAT_BB) { if (timeout++ > 100) break; DELAY(1000); } } /* Put the controller in master mode again. */ if ((ti_i2c_read_2(sc, I2C_REG_CON) & I2C_CON_MST) == 0) ti_i2c_write_2(sc, I2C_REG_CON, sc->sc_con_reg); sc->sc_buffer = NULL; sc->sc_bus_inuse = 0; /* Wake up the processes that are waiting for the bus. */ wakeup(sc); TI_I2C_UNLOCK(sc); return (err); } static int ti_i2c_reset(struct ti_i2c_softc *sc, u_char speed) { int timeout; struct ti_i2c_clock_config *clkcfg; u_int busfreq; uint16_t fifo_trsh, reg, scll, sclh; switch (ti_chip()) { #ifdef SOC_OMAP4 case CHIP_OMAP_4: clkcfg = ti_omap4_i2c_clock_configs; break; #endif #ifdef SOC_TI_AM335X case CHIP_AM335X: clkcfg = ti_am335x_i2c_clock_configs; break; #endif default: panic("Unknown TI SoC, unable to reset the i2c"); } /* * If we haven't attached the bus yet, just init at the default slow * speed. This lets us get the hardware initialized enough to attach * the bus which is where the real speed configuration is handled. After * the bus is attached, get the configured speed from it. Search the * configuration table for the best speed we can do that doesn't exceed * the requested speed. */ if (sc->sc_iicbus == NULL) busfreq = 100000; else busfreq = IICBUS_GET_FREQUENCY(sc->sc_iicbus, speed); for (;;) { if (clkcfg[1].frequency == 0 || clkcfg[1].frequency > busfreq) break; clkcfg++; } /* * 23.1.4.3 - HS I2C Software Reset * From OMAP4 TRM at page 4068. * * 1. Ensure that the module is disabled. */ sc->sc_con_reg = 0; ti_i2c_write_2(sc, I2C_REG_CON, sc->sc_con_reg); /* 2. Issue a softreset to the controller. */ bus_write_2(sc->sc_mem_res, I2C_REG_SYSC, I2C_REG_SYSC_SRST); /* * 3. Enable the module. * The I2Ci.I2C_SYSS[0] RDONE bit is asserted only after the module * is enabled by setting the I2Ci.I2C_CON[15] I2C_EN bit to 1. */ ti_i2c_write_2(sc, I2C_REG_CON, I2C_CON_I2C_EN); /* 4. Wait for the software reset to complete. */ timeout = 0; while ((ti_i2c_read_2(sc, I2C_REG_SYSS) & I2C_SYSS_RDONE) == 0) { if (timeout++ > 100) return (EBUSY); DELAY(100); } /* * Disable the I2C controller once again, now that the reset has * finished. */ ti_i2c_write_2(sc, I2C_REG_CON, sc->sc_con_reg); /* * The following sequence is taken from the OMAP4 TRM at page 4077. * * 1. Enable the functional and interface clocks (see Section * 23.1.5.1.1.1.1). Done at ti_i2c_activate(). * * 2. Program the prescaler to obtain an approximately 12MHz internal * sampling clock (I2Ci_INTERNAL_CLK) by programming the * corresponding value in the I2Ci.I2C_PSC[3:0] PSC field. * This value depends on the frequency of the functional clock * (I2Ci_FCLK). Because this frequency is 96MHz, the * I2Ci.I2C_PSC[7:0] PSC field value is 0x7. */ ti_i2c_write_2(sc, I2C_REG_PSC, clkcfg->psc); /* * 3. Program the I2Ci.I2C_SCLL[7:0] SCLL and I2Ci.I2C_SCLH[7:0] SCLH * bit fields to obtain a bit rate of 100 Kbps, 400 Kbps or 1Mbps. * These values depend on the internal sampling clock frequency * (see Table 23-8). */ scll = clkcfg->scll & I2C_SCLL_MASK; sclh = clkcfg->sclh & I2C_SCLH_MASK; /* * 4. (Optional) Program the I2Ci.I2C_SCLL[15:8] HSSCLL and * I2Ci.I2C_SCLH[15:8] HSSCLH fields to obtain a bit rate of * 400K bps or 3.4M bps (for the second phase of HS mode). These * values depend on the internal sampling clock frequency (see * Table 23-8). * * 5. (Optional) If a bit rate of 3.4M bps is used and the bus line * capacitance exceeds 45 pF, (see Section 18.4.8, PAD Functional * Multiplexing and Configuration). */ switch (ti_chip()) { #ifdef SOC_OMAP4 case CHIP_OMAP_4: if ((clkcfg->hsscll + clkcfg->hssclh) > 0) { scll |= clkcfg->hsscll << I2C_HSSCLL_SHIFT; sclh |= clkcfg->hssclh << I2C_HSSCLH_SHIFT; sc->sc_con_reg |= I2C_CON_OPMODE_HS; } break; #endif } /* Write the selected bit rate. */ ti_i2c_write_2(sc, I2C_REG_SCLL, scll); ti_i2c_write_2(sc, I2C_REG_SCLH, sclh); /* * 6. Configure the Own Address of the I2C controller by storing it in * the I2Ci.I2C_OA0 register. Up to four Own Addresses can be * programmed in the I2Ci.I2C_OAi registers (where i = 0, 1, 2, 3) * for each I2C controller. * * Note: For a 10-bit address, set the corresponding expand Own Address * bit in the I2Ci.I2C_CON register. * * Driver currently always in single master mode so ignore this step. */ /* * 7. Set the TX threshold (in transmitter mode) and the RX threshold * (in receiver mode) by setting the I2Ci.I2C_BUF[5:0]XTRSH field to * (TX threshold - 1) and the I2Ci.I2C_BUF[13:8]RTRSH field to (RX * threshold - 1), where the TX and RX thresholds are greater than * or equal to 1. * * The threshold is set to 5 for now. */ fifo_trsh = (sc->sc_fifo_trsh - 1) & I2C_BUF_TRSH_MASK; reg = fifo_trsh | (fifo_trsh << I2C_BUF_RXTRSH_SHIFT); ti_i2c_write_2(sc, I2C_REG_BUF, reg); /* * 8. Take the I2C controller out of reset by setting the * I2Ci.I2C_CON[15] I2C_EN bit to 1. * * 23.1.5.1.1.1.2 - Initialize the I2C Controller * * To initialize the I2C controller, perform the following steps: * * 1. Configure the I2Ci.I2C_CON register: * . For master or slave mode, set the I2Ci.I2C_CON[10] MST bit * (0: slave, 1: master). * . For transmitter or receiver mode, set the I2Ci.I2C_CON[9] TRX * bit (0: receiver, 1: transmitter). */ /* Enable the I2C controller in master mode. */ sc->sc_con_reg |= I2C_CON_I2C_EN | I2C_CON_MST; ti_i2c_write_2(sc, I2C_REG_CON, sc->sc_con_reg); /* * 2. If using an interrupt to transmit/receive data, set the * corresponding bit in the I2Ci.I2C_IE register (the I2Ci.I2C_IE[4] * XRDY_IE bit for the transmit interrupt, the I2Ci.I2C_IE[3] RRDY * bit for the receive interrupt). */ /* Set the interrupts we want to be notified. */ reg = I2C_IE_XDR | /* Transmit draining interrupt. */ I2C_IE_XRDY | /* Transmit Data Ready interrupt. */ I2C_IE_RDR | /* Receive draining interrupt. */ I2C_IE_RRDY | /* Receive Data Ready interrupt. */ I2C_IE_ARDY | /* Register Access Ready interrupt. */ I2C_IE_NACK | /* No Acknowledgment interrupt. */ I2C_IE_AL; /* Arbitration lost interrupt. */ /* Enable the interrupts. */ ti_i2c_write_2(sc, I2C_REG_IRQENABLE_SET, reg); /* * 3. If using DMA to receive/transmit data, set to 1 the corresponding * bit in the I2Ci.I2C_BUF register (the I2Ci.I2C_BUF[15] RDMA_EN * bit for the receive DMA channel, the I2Ci.I2C_BUF[7] XDMA_EN bit * for the transmit DMA channel). * * Not using DMA for now, so ignore this. */ return (0); } static int ti_i2c_iicbus_reset(device_t dev, u_char speed, u_char addr, u_char *oldaddr) { struct ti_i2c_softc *sc; int err; sc = device_get_softc(dev); TI_I2C_LOCK(sc); err = ti_i2c_reset(sc, speed); TI_I2C_UNLOCK(sc); if (err) return (err); return (IIC_ENOADDR); } static int ti_i2c_activate(device_t dev) { int err; struct ti_i2c_softc *sc; sc = (struct ti_i2c_softc*)device_get_softc(dev); /* * 1. Enable the functional and interface clocks (see Section * 23.1.5.1.1.1.1). */ err = ti_prcm_clk_enable(sc->clk_id); if (err) return (err); return (ti_i2c_reset(sc, IIC_UNKNOWN)); } /** * ti_i2c_deactivate - deactivates the controller and releases resources * @dev: i2c device handle * * * * LOCKING: * Assumed called in an atomic context. * * RETURNS: * nothing */ static void ti_i2c_deactivate(device_t dev) { struct ti_i2c_softc *sc = device_get_softc(dev); /* Disable the controller - cancel all transactions. */ ti_i2c_write_2(sc, I2C_REG_IRQENABLE_CLR, 0xffff); ti_i2c_write_2(sc, I2C_REG_STATUS, 0xffff); ti_i2c_write_2(sc, I2C_REG_CON, 0); /* Release the interrupt handler. */ if (sc->sc_irq_h != NULL) { bus_teardown_intr(dev, sc->sc_irq_res, sc->sc_irq_h); sc->sc_irq_h = NULL; } bus_generic_detach(sc->sc_dev); /* Unmap the I2C controller registers. */ if (sc->sc_mem_res != NULL) { bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->sc_mem_res); sc->sc_mem_res = NULL; } /* Release the IRQ resource. */ if (sc->sc_irq_res != NULL) { bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sc_irq_res); sc->sc_irq_res = NULL; } /* Finally disable the functional and interface clocks. */ ti_prcm_clk_disable(sc->clk_id); } static int ti_i2c_sysctl_clk(SYSCTL_HANDLER_ARGS) { int clk, psc, sclh, scll; struct ti_i2c_softc *sc; sc = arg1; TI_I2C_LOCK(sc); /* Get the system prescaler value. */ psc = (int)ti_i2c_read_2(sc, I2C_REG_PSC) + 1; /* Get the bitrate. */ scll = (int)ti_i2c_read_2(sc, I2C_REG_SCLL) & I2C_SCLL_MASK; sclh = (int)ti_i2c_read_2(sc, I2C_REG_SCLH) & I2C_SCLH_MASK; clk = I2C_CLK / psc / (scll + 7 + sclh + 5); TI_I2C_UNLOCK(sc); return (sysctl_handle_int(oidp, &clk, 0, req)); } static int ti_i2c_sysctl_timeout(SYSCTL_HANDLER_ARGS) { struct ti_i2c_softc *sc; unsigned int val; int err; sc = arg1; /* * MTX_DEF lock can't be held while doing uimove in * sysctl_handle_int */ TI_I2C_LOCK(sc); val = sc->sc_timeout; TI_I2C_UNLOCK(sc); err = sysctl_handle_int(oidp, &val, 0, req); /* Write request? */ if ((err == 0) && (req->newptr != NULL)) { TI_I2C_LOCK(sc); sc->sc_timeout = val; TI_I2C_UNLOCK(sc); } return (err); } static int ti_i2c_probe(device_t dev) { if (!ofw_bus_status_okay(dev)) return (ENXIO); if (!ofw_bus_is_compatible(dev, "ti,omap4-i2c")) return (ENXIO); device_set_desc(dev, "TI I2C Controller"); return (0); } static int ti_i2c_attach(device_t dev) { int err, rid; phandle_t node; struct ti_i2c_softc *sc; struct sysctl_ctx_list *ctx; struct sysctl_oid_list *tree; uint16_t fifosz; sc = device_get_softc(dev); sc->sc_dev = dev; /* Get the i2c device id from FDT. */ node = ofw_bus_get_node(dev); /* i2c ti,hwmods bindings is special: it start with index 1 */ sc->clk_id = ti_hwmods_get_clock(dev); if (sc->clk_id == INVALID_CLK_IDENT) { device_printf(dev, "failed to get device id using ti,hwmod\n"); return (ENXIO); } /* Get the memory resource for the register mapping. */ rid = 0; sc->sc_mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, RF_ACTIVE); if (sc->sc_mem_res == NULL) { device_printf(dev, "Cannot map registers.\n"); return (ENXIO); } /* Allocate our IRQ resource. */ rid = 0; sc->sc_irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, RF_ACTIVE | RF_SHAREABLE); if (sc->sc_irq_res == NULL) { bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->sc_mem_res); device_printf(dev, "Cannot allocate interrupt.\n"); return (ENXIO); } TI_I2C_LOCK_INIT(sc); /* First of all, we _must_ activate the H/W. */ err = ti_i2c_activate(dev); if (err) { device_printf(dev, "ti_i2c_activate failed\n"); goto out; } /* Read the version number of the I2C module */ sc->sc_rev = ti_i2c_read_2(sc, I2C_REG_REVNB_HI) & 0xff; /* Get the fifo size. */ fifosz = ti_i2c_read_2(sc, I2C_REG_BUFSTAT); fifosz >>= I2C_BUFSTAT_FIFODEPTH_SHIFT; fifosz &= I2C_BUFSTAT_FIFODEPTH_MASK; device_printf(dev, "I2C revision %d.%d FIFO size: %d bytes\n", sc->sc_rev >> 4, sc->sc_rev & 0xf, 8 << fifosz); /* Set the FIFO threshold to 5 for now. */ sc->sc_fifo_trsh = 5; /* Set I2C bus timeout */ sc->sc_timeout = 5*hz; ctx = device_get_sysctl_ctx(dev); tree = SYSCTL_CHILDREN(device_get_sysctl_tree(dev)); SYSCTL_ADD_PROC(ctx, tree, OID_AUTO, "i2c_clock", CTLFLAG_RD | CTLTYPE_UINT | CTLFLAG_MPSAFE, sc, 0, ti_i2c_sysctl_clk, "IU", "I2C bus clock"); SYSCTL_ADD_PROC(ctx, tree, OID_AUTO, "i2c_timeout", CTLFLAG_RW | CTLTYPE_UINT | CTLFLAG_MPSAFE, sc, 0, ti_i2c_sysctl_timeout, "IU", "I2C bus timeout (in ticks)"); /* Activate the interrupt. */ err = bus_setup_intr(dev, sc->sc_irq_res, INTR_TYPE_MISC | INTR_MPSAFE, NULL, ti_i2c_intr, sc, &sc->sc_irq_h); if (err) goto out; /* Attach the iicbus. */ if ((sc->sc_iicbus = device_add_child(dev, "iicbus", -1)) == NULL) { device_printf(dev, "could not allocate iicbus instance\n"); err = ENXIO; goto out; } - /* Probe and attach the iicbus */ - bus_generic_attach(dev); + /* Probe and attach the iicbus when interrupts are available. */ + config_intrhook_oneshot((ich_func_t)bus_generic_attach, dev); out: if (err) { ti_i2c_deactivate(dev); TI_I2C_LOCK_DESTROY(sc); } return (err); } static int ti_i2c_detach(device_t dev) { struct ti_i2c_softc *sc; int rv; sc = device_get_softc(dev); ti_i2c_deactivate(dev); TI_I2C_LOCK_DESTROY(sc); if (sc->sc_iicbus && (rv = device_delete_child(dev, sc->sc_iicbus)) != 0) return (rv); return (0); } static phandle_t ti_i2c_get_node(device_t bus, device_t dev) { /* Share controller node with iibus device. */ return (ofw_bus_get_node(bus)); } static device_method_t ti_i2c_methods[] = { /* Device interface */ DEVMETHOD(device_probe, ti_i2c_probe), DEVMETHOD(device_attach, ti_i2c_attach), DEVMETHOD(device_detach, ti_i2c_detach), /* Bus interface */ DEVMETHOD(bus_setup_intr, bus_generic_setup_intr), DEVMETHOD(bus_teardown_intr, bus_generic_teardown_intr), DEVMETHOD(bus_alloc_resource, bus_generic_alloc_resource), DEVMETHOD(bus_release_resource, bus_generic_release_resource), DEVMETHOD(bus_activate_resource, bus_generic_activate_resource), DEVMETHOD(bus_deactivate_resource, bus_generic_deactivate_resource), DEVMETHOD(bus_adjust_resource, bus_generic_adjust_resource), DEVMETHOD(bus_set_resource, bus_generic_rl_set_resource), DEVMETHOD(bus_get_resource, bus_generic_rl_get_resource), /* OFW methods */ DEVMETHOD(ofw_bus_get_node, ti_i2c_get_node), /* iicbus interface */ DEVMETHOD(iicbus_callback, iicbus_null_callback), DEVMETHOD(iicbus_reset, ti_i2c_iicbus_reset), DEVMETHOD(iicbus_transfer, ti_i2c_transfer), DEVMETHOD_END }; static driver_t ti_i2c_driver = { "iichb", ti_i2c_methods, sizeof(struct ti_i2c_softc), }; static devclass_t ti_i2c_devclass; DRIVER_MODULE(ti_iic, simplebus, ti_i2c_driver, ti_i2c_devclass, 0, 0); DRIVER_MODULE(iicbus, ti_iic, iicbus_driver, iicbus_devclass, 0, 0); MODULE_DEPEND(ti_iic, ti_prcm, 1, 1, 1); MODULE_DEPEND(ti_iic, iicbus, 1, 1, 1); Index: head/sys/dev/glxiic/glxiic.c =================================================================== --- head/sys/dev/glxiic/glxiic.c (revision 323552) +++ head/sys/dev/glxiic/glxiic.c (revision 323553) @@ -1,1083 +1,1082 @@ /*- * Copyright (c) 2011 Henrik Brix Andersen * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ #include __FBSDID("$FreeBSD$"); /* * AMD Geode LX CS5536 System Management Bus controller. * * Although AMD refers to this device as an SMBus controller, it * really is an I2C controller (It lacks SMBus ALERT# and Alert * Response support). * * The driver is implemented as an interrupt-driven state machine, * supporting both master and slave mode. */ #include #include #include #include #include #include #include #include #ifdef GLXIIC_DEBUG #include #endif #include #include #include #include #include #include #include #include "iicbus_if.h" /* CS5536 PCI-ISA ID. */ #define GLXIIC_CS5536_DEV_ID 0x20901022 /* MSRs. */ #define GLXIIC_MSR_PIC_YSEL_HIGH 0x51400021 /* Bus speeds. */ #define GLXIIC_SLOW 0x0258 /* 10 kHz. */ #define GLXIIC_FAST 0x0078 /* 50 kHz. */ #define GLXIIC_FASTEST 0x003c /* 100 kHz. */ /* Default bus activity timeout in milliseconds. */ #define GLXIIC_DEFAULT_TIMEOUT 35 /* GPIO register offsets. */ #define GLXIIC_GPIOL_OUT_AUX1_SEL 0x10 #define GLXIIC_GPIOL_IN_AUX1_SEL 0x34 /* GPIO 14 (SMB_CLK) and 15 (SMB_DATA) bitmasks. */ #define GLXIIC_GPIO_14_15_ENABLE 0x0000c000 #define GLXIIC_GPIO_14_15_DISABLE 0xc0000000 /* SMB register offsets. */ #define GLXIIC_SMB_SDA 0x00 #define GLXIIC_SMB_STS 0x01 #define GLXIIC_SMB_STS_SLVSTP_BIT (1 << 7) #define GLXIIC_SMB_STS_SDAST_BIT (1 << 6) #define GLXIIC_SMB_STS_BER_BIT (1 << 5) #define GLXIIC_SMB_STS_NEGACK_BIT (1 << 4) #define GLXIIC_SMB_STS_STASTR_BIT (1 << 3) #define GLXIIC_SMB_STS_NMATCH_BIT (1 << 2) #define GLXIIC_SMB_STS_MASTER_BIT (1 << 1) #define GLXIIC_SMB_STS_XMIT_BIT (1 << 0) #define GLXIIC_SMB_CTRL_STS 0x02 #define GLXIIC_SMB_CTRL_STS_TGSCL_BIT (1 << 5) #define GLXIIC_SMB_CTRL_STS_TSDA_BIT (1 << 4) #define GLXIIC_SMB_CTRL_STS_GCMTCH_BIT (1 << 3) #define GLXIIC_SMB_CTRL_STS_MATCH_BIT (1 << 2) #define GLXIIC_SMB_CTRL_STS_BB_BIT (1 << 1) #define GLXIIC_SMB_CTRL_STS_BUSY_BIT (1 << 0) #define GLXIIC_SMB_CTRL1 0x03 #define GLXIIC_SMB_CTRL1_STASTRE_BIT (1 << 7) #define GLXIIC_SMB_CTRL1_NMINTE_BIT (1 << 6) #define GLXIIC_SMB_CTRL1_GCMEN_BIT (1 << 5) #define GLXIIC_SMB_CTRL1_ACK_BIT (1 << 4) #define GLXIIC_SMB_CTRL1_INTEN_BIT (1 << 2) #define GLXIIC_SMB_CTRL1_STOP_BIT (1 << 1) #define GLXIIC_SMB_CTRL1_START_BIT (1 << 0) #define GLXIIC_SMB_ADDR 0x04 #define GLXIIC_SMB_ADDR_SAEN_BIT (1 << 7) #define GLXIIC_SMB_CTRL2 0x05 #define GLXIIC_SMB_CTRL2_EN_BIT (1 << 0) #define GLXIIC_SMB_CTRL3 0x06 typedef enum { GLXIIC_STATE_IDLE, GLXIIC_STATE_SLAVE_TX, GLXIIC_STATE_SLAVE_RX, GLXIIC_STATE_MASTER_ADDR, GLXIIC_STATE_MASTER_TX, GLXIIC_STATE_MASTER_RX, GLXIIC_STATE_MASTER_STOP, GLXIIC_STATE_MAX, } glxiic_state_t; struct glxiic_softc { device_t dev; /* Myself. */ device_t iicbus; /* IIC bus. */ struct mtx mtx; /* Lock. */ glxiic_state_t state; /* Driver state. */ struct callout callout; /* Driver state timeout callout. */ int timeout; /* Driver state timeout (ms). */ int smb_rid; /* SMB controller resource ID. */ struct resource *smb_res; /* SMB controller resource. */ int gpio_rid; /* GPIO resource ID. */ struct resource *gpio_res; /* GPIO resource. */ int irq_rid; /* IRQ resource ID. */ struct resource *irq_res; /* IRQ resource. */ void *irq_handler; /* IRQ handler cookie. */ int old_irq; /* IRQ mapped by board firmware. */ struct iic_msg *msg; /* Current master mode message. */ uint32_t nmsgs; /* Number of messages remaining. */ uint8_t *data; /* Current master mode data byte. */ uint16_t ndata; /* Number of data bytes remaining. */ int error; /* Last master mode error. */ uint8_t addr; /* Own address. */ uint16_t sclfrq; /* Bus frequency. */ }; #ifdef GLXIIC_DEBUG #define GLXIIC_DEBUG_LOG(fmt, args...) \ log(LOG_DEBUG, "%s: " fmt "\n" , __func__ , ## args) #else #define GLXIIC_DEBUG_LOG(fmt, args...) #endif #define GLXIIC_SCLFRQ(n) ((n << 1)) #define GLXIIC_SMBADDR(n) ((n >> 1)) #define GLXIIC_SMB_IRQ_TO_MAP(n) ((n << 16)) #define GLXIIC_MAP_TO_SMB_IRQ(n) ((n >> 16) & 0xf) #define GLXIIC_LOCK(_sc) mtx_lock(&_sc->mtx) #define GLXIIC_UNLOCK(_sc) mtx_unlock(&_sc->mtx) #define GLXIIC_LOCK_INIT(_sc) \ mtx_init(&_sc->mtx, device_get_nameunit(_sc->dev), "glxiic", MTX_DEF) #define GLXIIC_SLEEP(_sc) \ mtx_sleep(_sc, &_sc->mtx, IICPRI, "glxiic", 0) #define GLXIIC_WAKEUP(_sc) wakeup(_sc); #define GLXIIC_LOCK_DESTROY(_sc) mtx_destroy(&_sc->mtx); #define GLXIIC_ASSERT_LOCKED(_sc) mtx_assert(&_sc->mtx, MA_OWNED); typedef int (glxiic_state_callback_t)(struct glxiic_softc *sc, uint8_t status); static glxiic_state_callback_t glxiic_state_idle_callback; static glxiic_state_callback_t glxiic_state_slave_tx_callback; static glxiic_state_callback_t glxiic_state_slave_rx_callback; static glxiic_state_callback_t glxiic_state_master_addr_callback; static glxiic_state_callback_t glxiic_state_master_tx_callback; static glxiic_state_callback_t glxiic_state_master_rx_callback; static glxiic_state_callback_t glxiic_state_master_stop_callback; struct glxiic_state_table_entry { glxiic_state_callback_t *callback; boolean_t master; }; typedef struct glxiic_state_table_entry glxiic_state_table_entry_t; static glxiic_state_table_entry_t glxiic_state_table[GLXIIC_STATE_MAX] = { [GLXIIC_STATE_IDLE] = { .callback = &glxiic_state_idle_callback, .master = FALSE, }, [GLXIIC_STATE_SLAVE_TX] = { .callback = &glxiic_state_slave_tx_callback, .master = FALSE, }, [GLXIIC_STATE_SLAVE_RX] = { .callback = &glxiic_state_slave_rx_callback, .master = FALSE, }, [GLXIIC_STATE_MASTER_ADDR] = { .callback = &glxiic_state_master_addr_callback, .master = TRUE, }, [GLXIIC_STATE_MASTER_TX] = { .callback = &glxiic_state_master_tx_callback, .master = TRUE, }, [GLXIIC_STATE_MASTER_RX] = { .callback = &glxiic_state_master_rx_callback, .master = TRUE, }, [GLXIIC_STATE_MASTER_STOP] = { .callback = &glxiic_state_master_stop_callback, .master = TRUE, }, }; static void glxiic_identify(driver_t *driver, device_t parent); static int glxiic_probe(device_t dev); static int glxiic_attach(device_t dev); static int glxiic_detach(device_t dev); static uint8_t glxiic_read_status_locked(struct glxiic_softc *sc); static void glxiic_stop_locked(struct glxiic_softc *sc); static void glxiic_timeout(void *arg); static void glxiic_start_timeout_locked(struct glxiic_softc *sc); static void glxiic_set_state_locked(struct glxiic_softc *sc, glxiic_state_t state); static int glxiic_handle_slave_match_locked(struct glxiic_softc *sc, uint8_t status); static void glxiic_intr(void *arg); static int glxiic_reset(device_t dev, u_char speed, u_char addr, u_char *oldaddr); static int glxiic_transfer(device_t dev, struct iic_msg *msgs, uint32_t nmsgs); static void glxiic_smb_map_interrupt(int irq); static void glxiic_gpio_enable(struct glxiic_softc *sc); static void glxiic_gpio_disable(struct glxiic_softc *sc); static void glxiic_smb_enable(struct glxiic_softc *sc, uint8_t speed, uint8_t addr); static void glxiic_smb_disable(struct glxiic_softc *sc); static device_method_t glxiic_methods[] = { DEVMETHOD(device_identify, glxiic_identify), DEVMETHOD(device_probe, glxiic_probe), DEVMETHOD(device_attach, glxiic_attach), DEVMETHOD(device_detach, glxiic_detach), DEVMETHOD(iicbus_reset, glxiic_reset), DEVMETHOD(iicbus_transfer, glxiic_transfer), DEVMETHOD(iicbus_callback, iicbus_null_callback), { 0, 0 } }; static driver_t glxiic_driver = { "glxiic", glxiic_methods, sizeof(struct glxiic_softc), }; static devclass_t glxiic_devclass; DRIVER_MODULE(glxiic, isab, glxiic_driver, glxiic_devclass, 0, 0); DRIVER_MODULE(iicbus, glxiic, iicbus_driver, iicbus_devclass, 0, 0); MODULE_DEPEND(glxiic, iicbus, 1, 1, 1); static void glxiic_identify(driver_t *driver, device_t parent) { /* Prevent child from being added more than once. */ if (device_find_child(parent, driver->name, -1) != NULL) return; if (pci_get_devid(parent) == GLXIIC_CS5536_DEV_ID) { if (device_add_child(parent, driver->name, -1) == NULL) device_printf(parent, "Could not add glxiic child\n"); } } static int glxiic_probe(device_t dev) { if (resource_disabled("glxiic", device_get_unit(dev))) return (ENXIO); device_set_desc(dev, "AMD Geode CS5536 SMBus controller"); return (BUS_PROBE_DEFAULT); } static int glxiic_attach(device_t dev) { struct glxiic_softc *sc; struct sysctl_ctx_list *ctx; struct sysctl_oid *tree; int error, irq, unit; uint32_t irq_map; sc = device_get_softc(dev); sc->dev = dev; sc->state = GLXIIC_STATE_IDLE; error = 0; GLXIIC_LOCK_INIT(sc); callout_init_mtx(&sc->callout, &sc->mtx, 0); sc->smb_rid = PCIR_BAR(0); sc->smb_res = bus_alloc_resource_any(dev, SYS_RES_IOPORT, &sc->smb_rid, RF_ACTIVE); if (sc->smb_res == NULL) { device_printf(dev, "Could not allocate SMBus I/O port\n"); error = ENXIO; goto out; } sc->gpio_rid = PCIR_BAR(1); sc->gpio_res = bus_alloc_resource_any(dev, SYS_RES_IOPORT, &sc->gpio_rid, RF_SHAREABLE | RF_ACTIVE); if (sc->gpio_res == NULL) { device_printf(dev, "Could not allocate GPIO I/O port\n"); error = ENXIO; goto out; } /* Ensure the controller is not enabled by firmware. */ glxiic_smb_disable(sc); /* Read the existing IRQ map. */ irq_map = rdmsr(GLXIIC_MSR_PIC_YSEL_HIGH); sc->old_irq = GLXIIC_MAP_TO_SMB_IRQ(irq_map); unit = device_get_unit(dev); if (resource_int_value("glxiic", unit, "irq", &irq) == 0) { if (irq < 1 || irq > 15) { device_printf(dev, "Bad value %d for glxiic.%d.irq\n", irq, unit); error = ENXIO; goto out; } if (bootverbose) device_printf(dev, "Using irq %d set by hint\n", irq); } else if (sc->old_irq != 0) { if (bootverbose) device_printf(dev, "Using irq %d set by firmware\n", irq); irq = sc->old_irq; } else { device_printf(dev, "No irq mapped by firmware"); printf(" and no glxiic.%d.irq hint provided\n", unit); error = ENXIO; goto out; } /* Map the SMBus interrupt to the requested legacy IRQ. */ glxiic_smb_map_interrupt(irq); sc->irq_rid = 0; sc->irq_res = bus_alloc_resource(dev, SYS_RES_IRQ, &sc->irq_rid, irq, irq, 1, RF_SHAREABLE | RF_ACTIVE); if (sc->irq_res == NULL) { device_printf(dev, "Could not allocate IRQ %d\n", irq); error = ENXIO; goto out; } error = bus_setup_intr(dev, sc->irq_res, INTR_TYPE_MISC | INTR_MPSAFE, NULL, glxiic_intr, sc, &(sc->irq_handler)); if (error != 0) { device_printf(dev, "Could not setup IRQ handler\n"); error = ENXIO; goto out; } if ((sc->iicbus = device_add_child(dev, "iicbus", -1)) == NULL) { device_printf(dev, "Could not allocate iicbus instance\n"); error = ENXIO; goto out; } ctx = device_get_sysctl_ctx(dev); tree = device_get_sysctl_tree(dev); sc->timeout = GLXIIC_DEFAULT_TIMEOUT; SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, "timeout", CTLFLAG_RWTUN, &sc->timeout, 0, "activity timeout in ms"); glxiic_gpio_enable(sc); glxiic_smb_enable(sc, IIC_FASTEST, 0); - error = bus_generic_attach(dev); - if (error != 0) { - device_printf(dev, "Could not probe and attach children\n"); - error = ENXIO; - } + /* Probe and attach the iicbus when interrupts are available. */ + config_intrhook_oneshot((ich_func_t)bus_generic_attach, dev); + error = 0; + out: if (error != 0) { callout_drain(&sc->callout); if (sc->iicbus != NULL) device_delete_child(dev, sc->iicbus); if (sc->smb_res != NULL) { glxiic_smb_disable(sc); bus_release_resource(dev, SYS_RES_IOPORT, sc->smb_rid, sc->smb_res); } if (sc->gpio_res != NULL) { glxiic_gpio_disable(sc); bus_release_resource(dev, SYS_RES_IOPORT, sc->gpio_rid, sc->gpio_res); } if (sc->irq_handler != NULL) bus_teardown_intr(dev, sc->irq_res, sc->irq_handler); if (sc->irq_res != NULL) bus_release_resource(dev, SYS_RES_IRQ, sc->irq_rid, sc->irq_res); /* Restore the old SMBus interrupt mapping. */ glxiic_smb_map_interrupt(sc->old_irq); GLXIIC_LOCK_DESTROY(sc); } return (error); } static int glxiic_detach(device_t dev) { struct glxiic_softc *sc; int error; sc = device_get_softc(dev); error = bus_generic_detach(dev); if (error != 0) goto out; if (sc->iicbus != NULL) error = device_delete_child(dev, sc->iicbus); out: callout_drain(&sc->callout); if (sc->smb_res != NULL) { glxiic_smb_disable(sc); bus_release_resource(dev, SYS_RES_IOPORT, sc->smb_rid, sc->smb_res); } if (sc->gpio_res != NULL) { glxiic_gpio_disable(sc); bus_release_resource(dev, SYS_RES_IOPORT, sc->gpio_rid, sc->gpio_res); } if (sc->irq_handler != NULL) bus_teardown_intr(dev, sc->irq_res, sc->irq_handler); if (sc->irq_res != NULL) bus_release_resource(dev, SYS_RES_IRQ, sc->irq_rid, sc->irq_res); /* Restore the old SMBus interrupt mapping. */ glxiic_smb_map_interrupt(sc->old_irq); GLXIIC_LOCK_DESTROY(sc); return (error); } static uint8_t glxiic_read_status_locked(struct glxiic_softc *sc) { uint8_t status; GLXIIC_ASSERT_LOCKED(sc); status = bus_read_1(sc->smb_res, GLXIIC_SMB_STS); /* Clear all status flags except SDAST and STASTR after reading. */ bus_write_1(sc->smb_res, GLXIIC_SMB_STS, (GLXIIC_SMB_STS_SLVSTP_BIT | GLXIIC_SMB_STS_BER_BIT | GLXIIC_SMB_STS_NEGACK_BIT | GLXIIC_SMB_STS_NMATCH_BIT)); return (status); } static void glxiic_stop_locked(struct glxiic_softc *sc) { uint8_t status, ctrl1; GLXIIC_ASSERT_LOCKED(sc); status = glxiic_read_status_locked(sc); ctrl1 = bus_read_1(sc->smb_res, GLXIIC_SMB_CTRL1); bus_write_1(sc->smb_res, GLXIIC_SMB_CTRL1, ctrl1 | GLXIIC_SMB_CTRL1_STOP_BIT); /* * Perform a dummy read of SDA in master receive mode to clear * SDAST if set. */ if ((status & GLXIIC_SMB_STS_XMIT_BIT) == 0 && (status & GLXIIC_SMB_STS_SDAST_BIT) != 0) bus_read_1(sc->smb_res, GLXIIC_SMB_SDA); /* Check stall after start bit and clear if needed */ if ((status & GLXIIC_SMB_STS_STASTR_BIT) != 0) { bus_write_1(sc->smb_res, GLXIIC_SMB_STS, GLXIIC_SMB_STS_STASTR_BIT); } } static void glxiic_timeout(void *arg) { struct glxiic_softc *sc; uint8_t error; sc = (struct glxiic_softc *)arg; GLXIIC_DEBUG_LOG("timeout in state %d", sc->state); if (glxiic_state_table[sc->state].master) { sc->error = IIC_ETIMEOUT; GLXIIC_WAKEUP(sc); } else { error = IIC_ETIMEOUT; iicbus_intr(sc->iicbus, INTR_ERROR, &error); } glxiic_smb_disable(sc); glxiic_smb_enable(sc, IIC_UNKNOWN, sc->addr); glxiic_set_state_locked(sc, GLXIIC_STATE_IDLE); } static void glxiic_start_timeout_locked(struct glxiic_softc *sc) { GLXIIC_ASSERT_LOCKED(sc); callout_reset_sbt(&sc->callout, SBT_1MS * sc->timeout, 0, glxiic_timeout, sc, 0); } static void glxiic_set_state_locked(struct glxiic_softc *sc, glxiic_state_t state) { GLXIIC_ASSERT_LOCKED(sc); if (state == GLXIIC_STATE_IDLE) callout_stop(&sc->callout); else if (sc->timeout > 0) glxiic_start_timeout_locked(sc); sc->state = state; } static int glxiic_handle_slave_match_locked(struct glxiic_softc *sc, uint8_t status) { uint8_t ctrl_sts, addr; GLXIIC_ASSERT_LOCKED(sc); ctrl_sts = bus_read_1(sc->smb_res, GLXIIC_SMB_CTRL_STS); if ((ctrl_sts & GLXIIC_SMB_CTRL_STS_MATCH_BIT) != 0) { if ((status & GLXIIC_SMB_STS_XMIT_BIT) != 0) { addr = sc->addr | LSB; glxiic_set_state_locked(sc, GLXIIC_STATE_SLAVE_TX); } else { addr = sc->addr & ~LSB; glxiic_set_state_locked(sc, GLXIIC_STATE_SLAVE_RX); } iicbus_intr(sc->iicbus, INTR_START, &addr); } else if ((ctrl_sts & GLXIIC_SMB_CTRL_STS_GCMTCH_BIT) != 0) { addr = 0; glxiic_set_state_locked(sc, GLXIIC_STATE_SLAVE_RX); iicbus_intr(sc->iicbus, INTR_GENERAL, &addr); } else { GLXIIC_DEBUG_LOG("unknown slave match"); return (IIC_ESTATUS); } return (IIC_NOERR); } static int glxiic_state_idle_callback(struct glxiic_softc *sc, uint8_t status) { GLXIIC_ASSERT_LOCKED(sc); if ((status & GLXIIC_SMB_STS_BER_BIT) != 0) { GLXIIC_DEBUG_LOG("bus error in idle"); return (IIC_EBUSERR); } if ((status & GLXIIC_SMB_STS_NMATCH_BIT) != 0) { return (glxiic_handle_slave_match_locked(sc, status)); } return (IIC_NOERR); } static int glxiic_state_slave_tx_callback(struct glxiic_softc *sc, uint8_t status) { uint8_t data; GLXIIC_ASSERT_LOCKED(sc); if ((status & GLXIIC_SMB_STS_BER_BIT) != 0) { GLXIIC_DEBUG_LOG("bus error in slave tx"); return (IIC_EBUSERR); } if ((status & GLXIIC_SMB_STS_SLVSTP_BIT) != 0) { iicbus_intr(sc->iicbus, INTR_STOP, NULL); glxiic_set_state_locked(sc, GLXIIC_STATE_IDLE); return (IIC_NOERR); } if ((status & GLXIIC_SMB_STS_NEGACK_BIT) != 0) { iicbus_intr(sc->iicbus, INTR_NOACK, NULL); return (IIC_NOERR); } if ((status & GLXIIC_SMB_STS_NMATCH_BIT) != 0) { /* Handle repeated start in slave mode. */ return (glxiic_handle_slave_match_locked(sc, status)); } if ((status & GLXIIC_SMB_STS_SDAST_BIT) == 0) { GLXIIC_DEBUG_LOG("not awaiting data in slave tx"); return (IIC_ESTATUS); } iicbus_intr(sc->iicbus, INTR_TRANSMIT, &data); bus_write_1(sc->smb_res, GLXIIC_SMB_SDA, data); glxiic_start_timeout_locked(sc); return (IIC_NOERR); } static int glxiic_state_slave_rx_callback(struct glxiic_softc *sc, uint8_t status) { uint8_t data; GLXIIC_ASSERT_LOCKED(sc); if ((status & GLXIIC_SMB_STS_BER_BIT) != 0) { GLXIIC_DEBUG_LOG("bus error in slave rx"); return (IIC_EBUSERR); } if ((status & GLXIIC_SMB_STS_SLVSTP_BIT) != 0) { iicbus_intr(sc->iicbus, INTR_STOP, NULL); glxiic_set_state_locked(sc, GLXIIC_STATE_IDLE); return (IIC_NOERR); } if ((status & GLXIIC_SMB_STS_NMATCH_BIT) != 0) { /* Handle repeated start in slave mode. */ return (glxiic_handle_slave_match_locked(sc, status)); } if ((status & GLXIIC_SMB_STS_SDAST_BIT) == 0) { GLXIIC_DEBUG_LOG("no pending data in slave rx"); return (IIC_ESTATUS); } data = bus_read_1(sc->smb_res, GLXIIC_SMB_SDA); iicbus_intr(sc->iicbus, INTR_RECEIVE, &data); glxiic_start_timeout_locked(sc); return (IIC_NOERR); } static int glxiic_state_master_addr_callback(struct glxiic_softc *sc, uint8_t status) { uint8_t slave; uint8_t ctrl1; GLXIIC_ASSERT_LOCKED(sc); if ((status & GLXIIC_SMB_STS_BER_BIT) != 0) { GLXIIC_DEBUG_LOG("bus error after master start"); return (IIC_EBUSERR); } if ((status & GLXIIC_SMB_STS_MASTER_BIT) == 0) { GLXIIC_DEBUG_LOG("not bus master after master start"); return (IIC_ESTATUS); } if ((status & GLXIIC_SMB_STS_SDAST_BIT) == 0) { GLXIIC_DEBUG_LOG("not awaiting address in master addr"); return (IIC_ESTATUS); } if ((sc->msg->flags & IIC_M_RD) != 0) { slave = sc->msg->slave | LSB; glxiic_set_state_locked(sc, GLXIIC_STATE_MASTER_RX); } else { slave = sc->msg->slave & ~LSB; glxiic_set_state_locked(sc, GLXIIC_STATE_MASTER_TX); } sc->data = sc->msg->buf; sc->ndata = sc->msg->len; /* Handle address-only transfer. */ if (sc->ndata == 0) glxiic_set_state_locked(sc, GLXIIC_STATE_MASTER_STOP); bus_write_1(sc->smb_res, GLXIIC_SMB_SDA, slave); if ((sc->msg->flags & IIC_M_RD) != 0 && sc->ndata == 1) { /* Last byte from slave, set NACK. */ ctrl1 = bus_read_1(sc->smb_res, GLXIIC_SMB_CTRL1); bus_write_1(sc->smb_res, GLXIIC_SMB_CTRL1, ctrl1 | GLXIIC_SMB_CTRL1_ACK_BIT); } return (IIC_NOERR); } static int glxiic_state_master_tx_callback(struct glxiic_softc *sc, uint8_t status) { GLXIIC_ASSERT_LOCKED(sc); if ((status & GLXIIC_SMB_STS_BER_BIT) != 0) { GLXIIC_DEBUG_LOG("bus error in master tx"); return (IIC_EBUSERR); } if ((status & GLXIIC_SMB_STS_MASTER_BIT) == 0) { GLXIIC_DEBUG_LOG("not bus master in master tx"); return (IIC_ESTATUS); } if ((status & GLXIIC_SMB_STS_NEGACK_BIT) != 0) { GLXIIC_DEBUG_LOG("slave nack in master tx"); return (IIC_ENOACK); } if ((status & GLXIIC_SMB_STS_STASTR_BIT) != 0) { bus_write_1(sc->smb_res, GLXIIC_SMB_STS, GLXIIC_SMB_STS_STASTR_BIT); } if ((status & GLXIIC_SMB_STS_SDAST_BIT) == 0) { GLXIIC_DEBUG_LOG("not awaiting data in master tx"); return (IIC_ESTATUS); } bus_write_1(sc->smb_res, GLXIIC_SMB_SDA, *sc->data++); if (--sc->ndata == 0) glxiic_set_state_locked(sc, GLXIIC_STATE_MASTER_STOP); else glxiic_start_timeout_locked(sc); return (IIC_NOERR); } static int glxiic_state_master_rx_callback(struct glxiic_softc *sc, uint8_t status) { uint8_t ctrl1; GLXIIC_ASSERT_LOCKED(sc); if ((status & GLXIIC_SMB_STS_BER_BIT) != 0) { GLXIIC_DEBUG_LOG("bus error in master rx"); return (IIC_EBUSERR); } if ((status & GLXIIC_SMB_STS_MASTER_BIT) == 0) { GLXIIC_DEBUG_LOG("not bus master in master rx"); return (IIC_ESTATUS); } if ((status & GLXIIC_SMB_STS_NEGACK_BIT) != 0) { GLXIIC_DEBUG_LOG("slave nack in rx"); return (IIC_ENOACK); } if ((status & GLXIIC_SMB_STS_STASTR_BIT) != 0) { /* Bus is stalled, clear and wait for data. */ bus_write_1(sc->smb_res, GLXIIC_SMB_STS, GLXIIC_SMB_STS_STASTR_BIT); return (IIC_NOERR); } if ((status & GLXIIC_SMB_STS_SDAST_BIT) == 0) { GLXIIC_DEBUG_LOG("no pending data in master rx"); return (IIC_ESTATUS); } *sc->data++ = bus_read_1(sc->smb_res, GLXIIC_SMB_SDA); if (--sc->ndata == 0) { /* Proceed with stop on reading last byte. */ glxiic_set_state_locked(sc, GLXIIC_STATE_MASTER_STOP); return (glxiic_state_table[sc->state].callback(sc, status)); } if (sc->ndata == 1) { /* Last byte from slave, set NACK. */ ctrl1 = bus_read_1(sc->smb_res, GLXIIC_SMB_CTRL1); bus_write_1(sc->smb_res, GLXIIC_SMB_CTRL1, ctrl1 | GLXIIC_SMB_CTRL1_ACK_BIT); } glxiic_start_timeout_locked(sc); return (IIC_NOERR); } static int glxiic_state_master_stop_callback(struct glxiic_softc *sc, uint8_t status) { uint8_t ctrl1; GLXIIC_ASSERT_LOCKED(sc); if ((status & GLXIIC_SMB_STS_BER_BIT) != 0) { GLXIIC_DEBUG_LOG("bus error in master stop"); return (IIC_EBUSERR); } if ((status & GLXIIC_SMB_STS_MASTER_BIT) == 0) { GLXIIC_DEBUG_LOG("not bus master in master stop"); return (IIC_ESTATUS); } if ((status & GLXIIC_SMB_STS_NEGACK_BIT) != 0) { GLXIIC_DEBUG_LOG("slave nack in master stop"); return (IIC_ENOACK); } if (--sc->nmsgs > 0) { /* Start transfer of next message. */ if ((sc->msg->flags & IIC_M_NOSTOP) == 0) { glxiic_stop_locked(sc); } ctrl1 = bus_read_1(sc->smb_res, GLXIIC_SMB_CTRL1); bus_write_1(sc->smb_res, GLXIIC_SMB_CTRL1, ctrl1 | GLXIIC_SMB_CTRL1_START_BIT); glxiic_set_state_locked(sc, GLXIIC_STATE_MASTER_ADDR); sc->msg++; } else { /* Last message. */ glxiic_stop_locked(sc); glxiic_set_state_locked(sc, GLXIIC_STATE_IDLE); sc->error = IIC_NOERR; GLXIIC_WAKEUP(sc); } return (IIC_NOERR); } static void glxiic_intr(void *arg) { struct glxiic_softc *sc; int error; uint8_t status, data; sc = (struct glxiic_softc *)arg; GLXIIC_LOCK(sc); status = glxiic_read_status_locked(sc); /* Check if this interrupt originated from the SMBus. */ if ((status & ~(GLXIIC_SMB_STS_MASTER_BIT | GLXIIC_SMB_STS_XMIT_BIT)) != 0) { error = glxiic_state_table[sc->state].callback(sc, status); if (error != IIC_NOERR) { if (glxiic_state_table[sc->state].master) { glxiic_stop_locked(sc); glxiic_set_state_locked(sc, GLXIIC_STATE_IDLE); sc->error = error; GLXIIC_WAKEUP(sc); } else { data = error & 0xff; iicbus_intr(sc->iicbus, INTR_ERROR, &data); glxiic_set_state_locked(sc, GLXIIC_STATE_IDLE); } } } GLXIIC_UNLOCK(sc); } static int glxiic_reset(device_t dev, u_char speed, u_char addr, u_char *oldaddr) { struct glxiic_softc *sc; sc = device_get_softc(dev); GLXIIC_LOCK(sc); if (oldaddr != NULL) *oldaddr = sc->addr; sc->addr = addr; /* A disable/enable cycle resets the controller. */ glxiic_smb_disable(sc); glxiic_smb_enable(sc, speed, addr); if (glxiic_state_table[sc->state].master) { sc->error = IIC_ESTATUS; GLXIIC_WAKEUP(sc); } glxiic_set_state_locked(sc, GLXIIC_STATE_IDLE); GLXIIC_UNLOCK(sc); return (IIC_NOERR); } static int glxiic_transfer(device_t dev, struct iic_msg *msgs, uint32_t nmsgs) { struct glxiic_softc *sc; int error; uint8_t ctrl1; sc = device_get_softc(dev); GLXIIC_LOCK(sc); if (sc->state != GLXIIC_STATE_IDLE) { error = IIC_EBUSBSY; goto out; } sc->msg = msgs; sc->nmsgs = nmsgs; glxiic_set_state_locked(sc, GLXIIC_STATE_MASTER_ADDR); /* Set start bit and let glxiic_intr() handle the transfer. */ ctrl1 = bus_read_1(sc->smb_res, GLXIIC_SMB_CTRL1); bus_write_1(sc->smb_res, GLXIIC_SMB_CTRL1, ctrl1 | GLXIIC_SMB_CTRL1_START_BIT); GLXIIC_SLEEP(sc); error = sc->error; out: GLXIIC_UNLOCK(sc); return (error); } static void glxiic_smb_map_interrupt(int irq) { uint32_t irq_map; int old_irq; /* Protect the read-modify-write operation. */ critical_enter(); irq_map = rdmsr(GLXIIC_MSR_PIC_YSEL_HIGH); old_irq = GLXIIC_MAP_TO_SMB_IRQ(irq_map); if (irq != old_irq) { irq_map &= ~GLXIIC_SMB_IRQ_TO_MAP(old_irq); irq_map |= GLXIIC_SMB_IRQ_TO_MAP(irq); wrmsr(GLXIIC_MSR_PIC_YSEL_HIGH, irq_map); } critical_exit(); } static void glxiic_gpio_enable(struct glxiic_softc *sc) { bus_write_4(sc->gpio_res, GLXIIC_GPIOL_IN_AUX1_SEL, GLXIIC_GPIO_14_15_ENABLE); bus_write_4(sc->gpio_res, GLXIIC_GPIOL_OUT_AUX1_SEL, GLXIIC_GPIO_14_15_ENABLE); } static void glxiic_gpio_disable(struct glxiic_softc *sc) { bus_write_4(sc->gpio_res, GLXIIC_GPIOL_OUT_AUX1_SEL, GLXIIC_GPIO_14_15_DISABLE); bus_write_4(sc->gpio_res, GLXIIC_GPIOL_IN_AUX1_SEL, GLXIIC_GPIO_14_15_DISABLE); } static void glxiic_smb_enable(struct glxiic_softc *sc, uint8_t speed, uint8_t addr) { uint8_t ctrl1; ctrl1 = 0; switch (speed) { case IIC_SLOW: sc->sclfrq = GLXIIC_SLOW; break; case IIC_FAST: sc->sclfrq = GLXIIC_FAST; break; case IIC_FASTEST: sc->sclfrq = GLXIIC_FASTEST; break; case IIC_UNKNOWN: default: /* Reuse last frequency. */ break; } /* Set bus speed and enable controller. */ bus_write_2(sc->smb_res, GLXIIC_SMB_CTRL2, GLXIIC_SCLFRQ(sc->sclfrq) | GLXIIC_SMB_CTRL2_EN_BIT); if (addr != 0) { /* Enable new match and global call match interrupts. */ ctrl1 |= GLXIIC_SMB_CTRL1_NMINTE_BIT | GLXIIC_SMB_CTRL1_GCMEN_BIT; bus_write_1(sc->smb_res, GLXIIC_SMB_ADDR, GLXIIC_SMB_ADDR_SAEN_BIT | GLXIIC_SMBADDR(addr)); } else { bus_write_1(sc->smb_res, GLXIIC_SMB_ADDR, 0); } /* Enable stall after start and interrupt. */ bus_write_1(sc->smb_res, GLXIIC_SMB_CTRL1, ctrl1 | GLXIIC_SMB_CTRL1_STASTRE_BIT | GLXIIC_SMB_CTRL1_INTEN_BIT); } static void glxiic_smb_disable(struct glxiic_softc *sc) { uint16_t sclfrq; sclfrq = bus_read_2(sc->smb_res, GLXIIC_SMB_CTRL2); bus_write_2(sc->smb_res, GLXIIC_SMB_CTRL2, sclfrq & ~GLXIIC_SMB_CTRL2_EN_BIT); }