Index: head/sys/dev/ixl/i40e_prototype.h
===================================================================
--- head/sys/dev/ixl/i40e_prototype.h	(revision 320976)
+++ head/sys/dev/ixl/i40e_prototype.h	(revision 320977)
@@ -1,543 +1,541 @@
 /******************************************************************************
 
   Copyright (c) 2013-2015, Intel Corporation 
   All rights reserved.
   
   Redistribution and use in source and binary forms, with or without 
   modification, are permitted provided that the following conditions are met:
   
    1. Redistributions of source code must retain the above copyright notice, 
       this list of conditions and the following disclaimer.
   
    2. Redistributions in binary form must reproduce the above copyright 
       notice, this list of conditions and the following disclaimer in the 
       documentation and/or other materials provided with the distribution.
   
    3. Neither the name of the Intel Corporation nor the names of its 
       contributors may be used to endorse or promote products derived from 
       this software without specific prior written permission.
   
   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 
   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 
   ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 
   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 
   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 
   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 
   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 
   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 
   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
   POSSIBILITY OF SUCH DAMAGE.
 
 ******************************************************************************/
 /*$FreeBSD$*/
 
 #ifndef _I40E_PROTOTYPE_H_
 #define _I40E_PROTOTYPE_H_
 
 #include "i40e_type.h"
 #include "i40e_alloc.h"
 #include "i40e_virtchnl.h"
 
 /* Prototypes for shared code functions that are not in
  * the standard function pointer structures.  These are
  * mostly because they are needed even before the init
  * has happened and will assist in the early SW and FW
  * setup.
  */
 
 /* adminq functions */
 enum i40e_status_code i40e_init_adminq(struct i40e_hw *hw);
 enum i40e_status_code i40e_shutdown_adminq(struct i40e_hw *hw);
 enum i40e_status_code i40e_init_asq(struct i40e_hw *hw);
 enum i40e_status_code i40e_init_arq(struct i40e_hw *hw);
 enum i40e_status_code i40e_alloc_adminq_asq_ring(struct i40e_hw *hw);
 enum i40e_status_code i40e_alloc_adminq_arq_ring(struct i40e_hw *hw);
 enum i40e_status_code i40e_shutdown_asq(struct i40e_hw *hw);
 enum i40e_status_code i40e_shutdown_arq(struct i40e_hw *hw);
 u16 i40e_clean_asq(struct i40e_hw *hw);
 void i40e_free_adminq_asq(struct i40e_hw *hw);
 void i40e_free_adminq_arq(struct i40e_hw *hw);
 enum i40e_status_code i40e_validate_mac_addr(u8 *mac_addr);
 void i40e_adminq_init_ring_data(struct i40e_hw *hw);
 enum i40e_status_code i40e_clean_arq_element(struct i40e_hw *hw,
 					     struct i40e_arq_event_info *e,
 					     u16 *events_pending);
 enum i40e_status_code i40e_asq_send_command(struct i40e_hw *hw,
 				struct i40e_aq_desc *desc,
 				void *buff, /* can be NULL */
 				u16  buff_size,
 				struct i40e_asq_cmd_details *cmd_details);
 bool i40e_asq_done(struct i40e_hw *hw);
 
 /* debug function for adminq */
 void i40e_debug_aq(struct i40e_hw *hw, enum i40e_debug_mask mask,
 		   void *desc, void *buffer, u16 buf_len);
 
 void i40e_idle_aq(struct i40e_hw *hw);
 bool i40e_check_asq_alive(struct i40e_hw *hw);
 enum i40e_status_code i40e_aq_queue_shutdown(struct i40e_hw *hw, bool unloading);
 
 enum i40e_status_code i40e_aq_get_rss_lut(struct i40e_hw *hw, u16 seid,
 					  bool pf_lut, u8 *lut, u16 lut_size);
 enum i40e_status_code i40e_aq_set_rss_lut(struct i40e_hw *hw, u16 seid,
 					  bool pf_lut, u8 *lut, u16 lut_size);
 enum i40e_status_code i40e_aq_get_rss_key(struct i40e_hw *hw,
 				     u16 seid,
 				     struct i40e_aqc_get_set_rss_key_data *key);
 enum i40e_status_code i40e_aq_set_rss_key(struct i40e_hw *hw,
 				     u16 seid,
 				     struct i40e_aqc_get_set_rss_key_data *key);
 const char *i40e_aq_str(struct i40e_hw *hw, enum i40e_admin_queue_err aq_err);
 const char *i40e_stat_str(struct i40e_hw *hw, enum i40e_status_code stat_err);
 
 
 u32 i40e_led_get(struct i40e_hw *hw);
 void i40e_led_set(struct i40e_hw *hw, u32 mode, bool blink);
 enum i40e_status_code i40e_led_set_phy(struct i40e_hw *hw, bool on,
 				       u16 led_addr, u32 mode);
 enum i40e_status_code i40e_led_get_phy(struct i40e_hw *hw, u16 *led_addr,
 				       u16 *val);
 enum i40e_status_code i40e_blink_phy_link_led(struct i40e_hw *hw,
 					      u32 time, u32 interval);
 
 /* admin send queue commands */
 
 enum i40e_status_code i40e_aq_get_firmware_version(struct i40e_hw *hw,
 				u16 *fw_major_version, u16 *fw_minor_version,
 				u32 *fw_build,
 				u16 *api_major_version, u16 *api_minor_version,
 				struct i40e_asq_cmd_details *cmd_details);
 enum i40e_status_code i40e_aq_debug_write_register(struct i40e_hw *hw,
 				u32 reg_addr, u64 reg_val,
 				struct i40e_asq_cmd_details *cmd_details);
 enum i40e_status_code i40e_aq_debug_read_register(struct i40e_hw *hw,
 				u32  reg_addr, u64 *reg_val,
 				struct i40e_asq_cmd_details *cmd_details);
 enum i40e_status_code i40e_aq_set_phy_debug(struct i40e_hw *hw, u8 cmd_flags,
 				struct i40e_asq_cmd_details *cmd_details);
 enum i40e_status_code i40e_aq_set_default_vsi(struct i40e_hw *hw, u16 vsi_id,
 				struct i40e_asq_cmd_details *cmd_details);
 enum i40e_status_code i40e_aq_clear_default_vsi(struct i40e_hw *hw, u16 vsi_id,
 				struct i40e_asq_cmd_details *cmd_details);
 enum i40e_status_code i40e_aq_get_phy_capabilities(struct i40e_hw *hw,
 			bool qualified_modules, bool report_init,
 			struct i40e_aq_get_phy_abilities_resp *abilities,
 			struct i40e_asq_cmd_details *cmd_details);
 enum i40e_status_code i40e_aq_set_phy_config(struct i40e_hw *hw,
 				struct i40e_aq_set_phy_config *config,
 				struct i40e_asq_cmd_details *cmd_details);
 enum i40e_status_code i40e_set_fc(struct i40e_hw *hw, u8 *aq_failures,
 				  bool atomic_reset);
 enum i40e_status_code i40e_aq_set_phy_int_mask(struct i40e_hw *hw, u16 mask,
 				struct i40e_asq_cmd_details *cmd_details);
 enum i40e_status_code i40e_aq_set_mac_config(struct i40e_hw *hw,
 				u16 max_frame_size, bool crc_en, u16 pacing,
 				struct i40e_asq_cmd_details *cmd_details);
 enum i40e_status_code i40e_aq_get_local_advt_reg(struct i40e_hw *hw,
 				u64 *advt_reg,
 				struct i40e_asq_cmd_details *cmd_details);
 enum i40e_status_code i40e_aq_get_partner_advt(struct i40e_hw *hw,
 				u64 *advt_reg,
 				struct i40e_asq_cmd_details *cmd_details);
 enum i40e_status_code i40e_aq_set_lb_modes(struct i40e_hw *hw, u16 lb_modes,
 				struct i40e_asq_cmd_details *cmd_details);
 enum i40e_status_code i40e_aq_clear_pxe_mode(struct i40e_hw *hw,
 			struct i40e_asq_cmd_details *cmd_details);
 enum i40e_status_code i40e_aq_set_link_restart_an(struct i40e_hw *hw,
 		bool enable_link, struct i40e_asq_cmd_details *cmd_details);
 enum i40e_status_code i40e_aq_get_link_info(struct i40e_hw *hw,
 				bool enable_lse, struct i40e_link_status *link,
 				struct i40e_asq_cmd_details *cmd_details);
 enum i40e_status_code i40e_aq_set_local_advt_reg(struct i40e_hw *hw,
 				u64 advt_reg,
 				struct i40e_asq_cmd_details *cmd_details);
 enum i40e_status_code i40e_aq_send_driver_version(struct i40e_hw *hw,
 				struct i40e_driver_version *dv,
 				struct i40e_asq_cmd_details *cmd_details);
 enum i40e_status_code i40e_aq_add_vsi(struct i40e_hw *hw,
 				struct i40e_vsi_context *vsi_ctx,
 				struct i40e_asq_cmd_details *cmd_details);
 enum i40e_status_code i40e_aq_set_vsi_broadcast(struct i40e_hw *hw,
 				u16 vsi_id, bool set_filter,
 				struct i40e_asq_cmd_details *cmd_details);
 enum i40e_status_code i40e_aq_set_vsi_unicast_promiscuous(struct i40e_hw *hw,
 		u16 vsi_id, bool set, struct i40e_asq_cmd_details *cmd_details,
 		bool rx_only_promisc);
 enum i40e_status_code i40e_aq_set_vsi_multicast_promiscuous(struct i40e_hw *hw,
 		u16 vsi_id, bool set, struct i40e_asq_cmd_details *cmd_details);
 enum i40e_status_code i40e_aq_set_vsi_full_promiscuous(struct i40e_hw *hw,
 				u16 seid, bool set,
 				struct i40e_asq_cmd_details *cmd_details);
 enum i40e_status_code i40e_aq_set_vsi_mc_promisc_on_vlan(struct i40e_hw *hw,
 				u16 seid, bool enable, u16 vid,
 				struct i40e_asq_cmd_details *cmd_details);
 enum i40e_status_code i40e_aq_set_vsi_uc_promisc_on_vlan(struct i40e_hw *hw,
 				u16 seid, bool enable, u16 vid,
 				struct i40e_asq_cmd_details *cmd_details);
 enum i40e_status_code i40e_aq_set_vsi_bc_promisc_on_vlan(struct i40e_hw *hw,
 				u16 seid, bool enable, u16 vid,
 				struct i40e_asq_cmd_details *cmd_details);
 enum i40e_status_code i40e_aq_set_vsi_vlan_promisc(struct i40e_hw *hw,
 				u16 seid, bool enable,
 				struct i40e_asq_cmd_details *cmd_details);
 enum i40e_status_code i40e_aq_get_vsi_params(struct i40e_hw *hw,
 				struct i40e_vsi_context *vsi_ctx,
 				struct i40e_asq_cmd_details *cmd_details);
 enum i40e_status_code i40e_aq_update_vsi_params(struct i40e_hw *hw,
 				struct i40e_vsi_context *vsi_ctx,
 				struct i40e_asq_cmd_details *cmd_details);
 enum i40e_status_code i40e_aq_add_veb(struct i40e_hw *hw, u16 uplink_seid,
 				u16 downlink_seid, u8 enabled_tc,
 				bool default_port, u16 *pveb_seid,
 				bool enable_stats,
 				struct i40e_asq_cmd_details *cmd_details);
 enum i40e_status_code i40e_aq_get_veb_parameters(struct i40e_hw *hw,
 				u16 veb_seid, u16 *switch_id, bool *floating,
 				u16 *statistic_index, u16 *vebs_used,
 				u16 *vebs_free,
 				struct i40e_asq_cmd_details *cmd_details);
 enum i40e_status_code i40e_aq_add_macvlan(struct i40e_hw *hw, u16 vsi_id,
 			struct i40e_aqc_add_macvlan_element_data *mv_list,
 			u16 count, struct i40e_asq_cmd_details *cmd_details);
 enum i40e_status_code i40e_aq_remove_macvlan(struct i40e_hw *hw, u16 vsi_id,
 			struct i40e_aqc_remove_macvlan_element_data *mv_list,
 			u16 count, struct i40e_asq_cmd_details *cmd_details);
 enum i40e_status_code i40e_aq_add_mirrorrule(struct i40e_hw *hw, u16 sw_seid,
 			u16 rule_type, u16 dest_vsi, u16 count, __le16 *mr_list,
 			struct i40e_asq_cmd_details *cmd_details,
 			u16 *rule_id, u16 *rules_used, u16 *rules_free);
 enum i40e_status_code i40e_aq_delete_mirrorrule(struct i40e_hw *hw, u16 sw_seid,
 			u16 rule_type, u16 rule_id, u16 count, __le16 *mr_list,
 			struct i40e_asq_cmd_details *cmd_details,
 			u16 *rules_used, u16 *rules_free);
 
 enum i40e_status_code i40e_aq_add_vlan(struct i40e_hw *hw, u16 vsi_id,
 			struct i40e_aqc_add_remove_vlan_element_data *v_list,
 			u8 count, struct i40e_asq_cmd_details *cmd_details);
 enum i40e_status_code i40e_aq_remove_vlan(struct i40e_hw *hw, u16 vsi_id,
 			struct i40e_aqc_add_remove_vlan_element_data *v_list,
 			u8 count, struct i40e_asq_cmd_details *cmd_details);
 enum i40e_status_code i40e_aq_send_msg_to_vf(struct i40e_hw *hw, u16 vfid,
 				u32 v_opcode, u32 v_retval, u8 *msg, u16 msglen,
 				struct i40e_asq_cmd_details *cmd_details);
 enum i40e_status_code i40e_aq_get_switch_config(struct i40e_hw *hw,
 				struct i40e_aqc_get_switch_config_resp *buf,
 				u16 buf_size, u16 *start_seid,
 				struct i40e_asq_cmd_details *cmd_details);
 enum i40e_status_code i40e_aq_set_switch_config(struct i40e_hw *hw,
 				u16 flags, u16 valid_flags,
 				struct i40e_asq_cmd_details *cmd_details);
 enum i40e_status_code i40e_aq_request_resource(struct i40e_hw *hw,
 				enum i40e_aq_resources_ids resource,
 				enum i40e_aq_resource_access_type access,
 				u8 sdp_number, u64 *timeout,
 				struct i40e_asq_cmd_details *cmd_details);
 enum i40e_status_code i40e_aq_release_resource(struct i40e_hw *hw,
 				enum i40e_aq_resources_ids resource,
 				u8 sdp_number,
 				struct i40e_asq_cmd_details *cmd_details);
 enum i40e_status_code i40e_aq_read_nvm(struct i40e_hw *hw, u8 module_pointer,
 				u32 offset, u16 length, void *data,
 				bool last_command,
 				struct i40e_asq_cmd_details *cmd_details);
 enum i40e_status_code i40e_aq_erase_nvm(struct i40e_hw *hw, u8 module_pointer,
 				u32 offset, u16 length, bool last_command,
 				struct i40e_asq_cmd_details *cmd_details);
 enum i40e_status_code i40e_aq_read_nvm_config(struct i40e_hw *hw,
 				u8 cmd_flags, u32 field_id, void *data,
 				u16 buf_size, u16 *element_count,
 				struct i40e_asq_cmd_details *cmd_details);
 enum i40e_status_code i40e_aq_write_nvm_config(struct i40e_hw *hw,
 				u8 cmd_flags, void *data, u16 buf_size,
 				u16 element_count,
 				struct i40e_asq_cmd_details *cmd_details);
 enum i40e_status_code i40e_aq_oem_post_update(struct i40e_hw *hw,
 				void *buff, u16 buff_size,
 				struct i40e_asq_cmd_details *cmd_details);
 enum i40e_status_code i40e_aq_discover_capabilities(struct i40e_hw *hw,
 				void *buff, u16 buff_size, u16 *data_size,
 				enum i40e_admin_queue_opc list_type_opc,
 				struct i40e_asq_cmd_details *cmd_details);
 enum i40e_status_code i40e_aq_update_nvm(struct i40e_hw *hw, u8 module_pointer,
 				u32 offset, u16 length, void *data,
 				bool last_command,
 				struct i40e_asq_cmd_details *cmd_details);
 enum i40e_status_code i40e_aq_get_lldp_mib(struct i40e_hw *hw, u8 bridge_type,
 				u8 mib_type, void *buff, u16 buff_size,
 				u16 *local_len, u16 *remote_len,
 				struct i40e_asq_cmd_details *cmd_details);
 enum i40e_status_code i40e_aq_set_lldp_mib(struct i40e_hw *hw,
 				u8 mib_type, void *buff, u16 buff_size,
 				struct i40e_asq_cmd_details *cmd_details);
 enum i40e_status_code i40e_aq_cfg_lldp_mib_change_event(struct i40e_hw *hw,
 				bool enable_update,
 				struct i40e_asq_cmd_details *cmd_details);
 enum i40e_status_code i40e_aq_add_lldp_tlv(struct i40e_hw *hw, u8 bridge_type,
 				void *buff, u16 buff_size, u16 tlv_len,
 				u16 *mib_len,
 				struct i40e_asq_cmd_details *cmd_details);
 enum i40e_status_code i40e_aq_update_lldp_tlv(struct i40e_hw *hw,
 				u8 bridge_type, void *buff, u16 buff_size,
 				u16 old_len, u16 new_len, u16 offset,
 				u16 *mib_len,
 				struct i40e_asq_cmd_details *cmd_details);
 enum i40e_status_code i40e_aq_delete_lldp_tlv(struct i40e_hw *hw,
 				u8 bridge_type, void *buff, u16 buff_size,
 				u16 tlv_len, u16 *mib_len,
 				struct i40e_asq_cmd_details *cmd_details);
 enum i40e_status_code i40e_aq_stop_lldp(struct i40e_hw *hw, bool shutdown_agent,
 				struct i40e_asq_cmd_details *cmd_details);
 enum i40e_status_code i40e_aq_start_lldp(struct i40e_hw *hw,
 				struct i40e_asq_cmd_details *cmd_details);
 enum i40e_status_code i40e_aq_get_cee_dcb_config(struct i40e_hw *hw,
 				void *buff, u16 buff_size,
 				struct i40e_asq_cmd_details *cmd_details);
 enum i40e_status_code i40e_aq_start_stop_dcbx(struct i40e_hw *hw,
 				bool start_agent,
 				struct i40e_asq_cmd_details *cmd_details);
 enum i40e_status_code i40e_aq_add_udp_tunnel(struct i40e_hw *hw,
 				u16 udp_port, u8 protocol_index,
 				u8 *filter_index,
 				struct i40e_asq_cmd_details *cmd_details);
 enum i40e_status_code i40e_aq_del_udp_tunnel(struct i40e_hw *hw, u8 index,
 				struct i40e_asq_cmd_details *cmd_details);
 enum i40e_status_code i40e_aq_get_switch_resource_alloc(struct i40e_hw *hw,
 			u8 *num_entries,
 			struct i40e_aqc_switch_resource_alloc_element_resp *buf,
 			u16 count,
 			struct i40e_asq_cmd_details *cmd_details);
 enum i40e_status_code i40e_aq_add_pvirt(struct i40e_hw *hw, u16 flags,
 				       u16 mac_seid, u16 vsi_seid,
 				       u16 *ret_seid);
 enum i40e_status_code i40e_aq_add_tag(struct i40e_hw *hw, bool direct_to_queue,
 				u16 vsi_seid, u16 tag, u16 queue_num,
 				u16 *tags_used, u16 *tags_free,
 				struct i40e_asq_cmd_details *cmd_details);
 enum i40e_status_code i40e_aq_remove_tag(struct i40e_hw *hw, u16 vsi_seid,
 				u16 tag, u16 *tags_used, u16 *tags_free,
 				struct i40e_asq_cmd_details *cmd_details);
 enum i40e_status_code i40e_aq_add_mcast_etag(struct i40e_hw *hw, u16 pe_seid,
 				u16 etag, u8 num_tags_in_buf, void *buf,
 				u16 *tags_used, u16 *tags_free,
 				struct i40e_asq_cmd_details *cmd_details);
 enum i40e_status_code i40e_aq_remove_mcast_etag(struct i40e_hw *hw, u16 pe_seid,
 				u16 etag, u16 *tags_used, u16 *tags_free,
 				struct i40e_asq_cmd_details *cmd_details);
 enum i40e_status_code i40e_aq_update_tag(struct i40e_hw *hw, u16 vsi_seid,
 				u16 old_tag, u16 new_tag, u16 *tags_used,
 				u16 *tags_free,
 				struct i40e_asq_cmd_details *cmd_details);
 enum i40e_status_code i40e_aq_add_statistics(struct i40e_hw *hw, u16 seid,
 				u16 vlan_id, u16 *stat_index,
 				struct i40e_asq_cmd_details *cmd_details);
 enum i40e_status_code i40e_aq_remove_statistics(struct i40e_hw *hw, u16 seid,
 				u16 vlan_id, u16 stat_index,
 				struct i40e_asq_cmd_details *cmd_details);
 enum i40e_status_code i40e_aq_set_port_parameters(struct i40e_hw *hw,
 				u16 bad_frame_vsi, bool save_bad_pac,
 				bool pad_short_pac, bool double_vlan,
 				struct i40e_asq_cmd_details *cmd_details);
 enum i40e_status_code i40e_aq_delete_element(struct i40e_hw *hw, u16 seid,
 				struct i40e_asq_cmd_details *cmd_details);
 enum i40e_status_code i40e_aq_mac_address_write(struct i40e_hw *hw,
 				    u16 flags, u8 *mac_addr,
 				    struct i40e_asq_cmd_details *cmd_details);
 enum i40e_status_code i40e_aq_config_vsi_bw_limit(struct i40e_hw *hw,
 				u16 seid, u16 credit, u8 max_credit,
 				struct i40e_asq_cmd_details *cmd_details);
 enum i40e_status_code i40e_aq_dcb_ignore_pfc(struct i40e_hw *hw,
 				u8 tcmap, bool request, u8 *tcmap_ret,
 				struct i40e_asq_cmd_details *cmd_details);
 enum i40e_status_code i40e_aq_config_switch_comp_ets_bw_limit(
 	struct i40e_hw *hw, u16 seid,
 	struct i40e_aqc_configure_switching_comp_ets_bw_limit_data *bw_data,
 	struct i40e_asq_cmd_details *cmd_details);
 enum i40e_status_code i40e_aq_config_vsi_ets_sla_bw_limit(struct i40e_hw *hw,
 			u16 seid,
 			struct i40e_aqc_configure_vsi_ets_sla_bw_data *bw_data,
 			struct i40e_asq_cmd_details *cmd_details);
 enum i40e_status_code i40e_aq_dcb_updated(struct i40e_hw *hw,
 				struct i40e_asq_cmd_details *cmd_details);
 enum i40e_status_code i40e_aq_config_switch_comp_bw_limit(struct i40e_hw *hw,
 				u16 seid, u16 credit, u8 max_bw,
 				struct i40e_asq_cmd_details *cmd_details);
 enum i40e_status_code i40e_aq_config_vsi_tc_bw(struct i40e_hw *hw, u16 seid,
 			struct i40e_aqc_configure_vsi_tc_bw_data *bw_data,
 			struct i40e_asq_cmd_details *cmd_details);
 enum i40e_status_code i40e_aq_query_vsi_bw_config(struct i40e_hw *hw,
 			u16 seid,
 			struct i40e_aqc_query_vsi_bw_config_resp *bw_data,
 			struct i40e_asq_cmd_details *cmd_details);
 enum i40e_status_code i40e_aq_query_vsi_ets_sla_config(struct i40e_hw *hw,
 			u16 seid,
 			struct i40e_aqc_query_vsi_ets_sla_config_resp *bw_data,
 			struct i40e_asq_cmd_details *cmd_details);
 enum i40e_status_code i40e_aq_query_switch_comp_ets_config(struct i40e_hw *hw,
 		u16 seid,
 		struct i40e_aqc_query_switching_comp_ets_config_resp *bw_data,
 		struct i40e_asq_cmd_details *cmd_details);
 enum i40e_status_code i40e_aq_query_port_ets_config(struct i40e_hw *hw,
 		u16 seid,
 		struct i40e_aqc_query_port_ets_config_resp *bw_data,
 		struct i40e_asq_cmd_details *cmd_details);
 enum i40e_status_code i40e_aq_query_switch_comp_bw_config(struct i40e_hw *hw,
 		u16 seid,
 		struct i40e_aqc_query_switching_comp_bw_config_resp *bw_data,
 		struct i40e_asq_cmd_details *cmd_details);
 enum i40e_status_code i40e_aq_resume_port_tx(struct i40e_hw *hw,
 				struct i40e_asq_cmd_details *cmd_details);
 enum i40e_status_code i40e_read_lldp_cfg(struct i40e_hw *hw,
 					struct i40e_lldp_variables *lldp_cfg);
 enum i40e_status_code i40e_aq_add_cloud_filters(struct i40e_hw *hw,
 		u16 vsi,
 		struct i40e_aqc_add_remove_cloud_filters_element_data *filters,
 		u8 filter_count);
 
 enum i40e_status_code i40e_aq_remove_cloud_filters(struct i40e_hw *hw,
 		u16 vsi,
 		struct i40e_aqc_add_remove_cloud_filters_element_data *filters,
 		u8 filter_count);
 enum i40e_status_code i40e_aq_alternate_read(struct i40e_hw *hw,
 				u32 reg_addr0, u32 *reg_val0,
 				u32 reg_addr1, u32 *reg_val1);
 enum i40e_status_code i40e_aq_alternate_read_indirect(struct i40e_hw *hw,
 				u32 addr, u32 dw_count, void *buffer);
 enum i40e_status_code i40e_aq_alternate_write(struct i40e_hw *hw,
 				u32 reg_addr0, u32 reg_val0,
 				u32 reg_addr1, u32 reg_val1);
 enum i40e_status_code i40e_aq_alternate_write_indirect(struct i40e_hw *hw,
 				u32 addr, u32 dw_count, void *buffer);
 enum i40e_status_code i40e_aq_alternate_clear(struct i40e_hw *hw);
 enum i40e_status_code i40e_aq_alternate_write_done(struct i40e_hw *hw,
 				u8 bios_mode, bool *reset_needed);
 enum i40e_status_code i40e_aq_set_oem_mode(struct i40e_hw *hw,
 				u8 oem_mode);
 
 /* i40e_common */
 enum i40e_status_code i40e_init_shared_code(struct i40e_hw *hw);
 enum i40e_status_code i40e_pf_reset(struct i40e_hw *hw);
 void i40e_clear_hw(struct i40e_hw *hw);
 void i40e_clear_pxe_mode(struct i40e_hw *hw);
 enum i40e_status_code i40e_get_link_status(struct i40e_hw *hw, bool *link_up);
 enum i40e_status_code i40e_update_link_info(struct i40e_hw *hw);
 enum i40e_status_code i40e_get_mac_addr(struct i40e_hw *hw, u8 *mac_addr);
 enum i40e_status_code i40e_read_bw_from_alt_ram(struct i40e_hw *hw,
 		u32 *max_bw, u32 *min_bw, bool *min_valid, bool *max_valid);
 enum i40e_status_code i40e_aq_configure_partition_bw(struct i40e_hw *hw,
 			struct i40e_aqc_configure_partition_bw_data *bw_data,
 			struct i40e_asq_cmd_details *cmd_details);
 enum i40e_status_code i40e_get_port_mac_addr(struct i40e_hw *hw, u8 *mac_addr);
 enum i40e_status_code i40e_read_pba_string(struct i40e_hw *hw, u8 *pba_num,
 					    u32 pba_num_size);
 void i40e_pre_tx_queue_cfg(struct i40e_hw *hw, u32 queue, bool enable);
 enum i40e_aq_link_speed i40e_get_link_speed(struct i40e_hw *hw);
 /* prototype for functions used for NVM access */
 enum i40e_status_code i40e_init_nvm(struct i40e_hw *hw);
 enum i40e_status_code i40e_acquire_nvm(struct i40e_hw *hw,
 				      enum i40e_aq_resource_access_type access);
 void i40e_release_nvm(struct i40e_hw *hw);
 enum i40e_status_code i40e_read_nvm_word(struct i40e_hw *hw, u16 offset,
 					 u16 *data);
 enum i40e_status_code i40e_read_nvm_buffer(struct i40e_hw *hw, u16 offset,
 					   u16 *words, u16 *data);
 enum i40e_status_code i40e_write_nvm_aq(struct i40e_hw *hw, u8 module,
 					u32 offset, u16 words, void *data,
 					bool last_command);
 enum i40e_status_code __i40e_read_nvm_word(struct i40e_hw *hw, u16 offset,
 					   u16 *data);
 enum i40e_status_code __i40e_read_nvm_buffer(struct i40e_hw *hw, u16 offset,
 					     u16 *words, u16 *data);
 enum i40e_status_code __i40e_write_nvm_word(struct i40e_hw *hw, u32 offset,
 					  void *data);
 enum i40e_status_code __i40e_write_nvm_buffer(struct i40e_hw *hw, u8 module,
 					    u32 offset, u16 words, void *data);
 enum i40e_status_code i40e_calc_nvm_checksum(struct i40e_hw *hw, u16 *checksum);
 enum i40e_status_code i40e_update_nvm_checksum(struct i40e_hw *hw);
 enum i40e_status_code i40e_validate_nvm_checksum(struct i40e_hw *hw,
 						 u16 *checksum);
 enum i40e_status_code i40e_nvmupd_command(struct i40e_hw *hw,
 					  struct i40e_nvm_access *cmd,
 					  u8 *bytes, int *);
 void i40e_nvmupd_check_wait_event(struct i40e_hw *hw, u16 opcode);
 void i40e_set_pci_config_data(struct i40e_hw *hw, u16 link_status);
 
 enum i40e_status_code i40e_set_mac_type(struct i40e_hw *hw);
 
 extern struct i40e_rx_ptype_decoded i40e_ptype_lookup[];
 
 static INLINE struct i40e_rx_ptype_decoded decode_rx_desc_ptype(u8 ptype)
 {
 	return i40e_ptype_lookup[ptype];
 }
 
 /* prototype for functions used for SW spinlocks */
 void i40e_init_spinlock(struct i40e_spinlock *sp);
 void i40e_acquire_spinlock(struct i40e_spinlock *sp);
 void i40e_release_spinlock(struct i40e_spinlock *sp);
 void i40e_destroy_spinlock(struct i40e_spinlock *sp);
 
 /* i40e_common for VF drivers*/
 void i40e_vf_parse_hw_config(struct i40e_hw *hw,
 			     struct i40e_virtchnl_vf_resource *msg);
 enum i40e_status_code i40e_vf_reset(struct i40e_hw *hw);
 enum i40e_status_code i40e_aq_send_msg_to_pf(struct i40e_hw *hw,
 				enum i40e_virtchnl_ops v_opcode,
 				enum i40e_status_code v_retval,
 				u8 *msg, u16 msglen,
 				struct i40e_asq_cmd_details *cmd_details);
 enum i40e_status_code i40e_set_filter_control(struct i40e_hw *hw,
 				struct i40e_filter_control_settings *settings);
 enum i40e_status_code i40e_aq_add_rem_control_packet_filter(struct i40e_hw *hw,
 				u8 *mac_addr, u16 ethtype, u16 flags,
 				u16 vsi_seid, u16 queue, bool is_add,
 				struct i40e_control_filter_stats *stats,
 				struct i40e_asq_cmd_details *cmd_details);
 enum i40e_status_code i40e_aq_debug_dump(struct i40e_hw *hw, u8 cluster_id,
 				u8 table_id, u32 start_index, u16 buff_size,
 				void *buff, u16 *ret_buff_size,
 				u8 *ret_next_table, u32 *ret_next_index,
 				struct i40e_asq_cmd_details *cmd_details);
 void i40e_add_filter_to_drop_tx_flow_control_frames(struct i40e_hw *hw,
 						    u16 vsi_seid);
 enum i40e_status_code i40e_aq_rx_ctl_read_register(struct i40e_hw *hw,
 				u32 reg_addr, u32 *reg_val,
 				struct i40e_asq_cmd_details *cmd_details);
 u32 i40e_read_rx_ctl(struct i40e_hw *hw, u32 reg_addr);
 enum i40e_status_code i40e_aq_rx_ctl_write_register(struct i40e_hw *hw,
 				u32 reg_addr, u32 reg_val,
 				struct i40e_asq_cmd_details *cmd_details);
 void i40e_write_rx_ctl(struct i40e_hw *hw, u32 reg_addr, u32 reg_val);
 enum i40e_status_code i40e_aq_set_arp_proxy_config(struct i40e_hw *hw,
 			struct i40e_aqc_arp_proxy_data *proxy_config,
 			struct i40e_asq_cmd_details *cmd_details);
 enum i40e_status_code i40e_aq_set_ns_proxy_table_entry(struct i40e_hw *hw,
 			struct i40e_aqc_ns_proxy_data *ns_proxy_table_entry,
 			struct i40e_asq_cmd_details *cmd_details);
 enum i40e_status_code i40e_aq_set_clear_wol_filter(struct i40e_hw *hw,
 			u8 filter_index,
 			struct i40e_aqc_set_wol_filter_data *filter,
 			bool set_filter, bool no_wol_tco,
 			bool filter_valid, bool no_wol_tco_valid,
 			struct i40e_asq_cmd_details *cmd_details);
 enum i40e_status_code i40e_aq_get_wake_event_reason(struct i40e_hw *hw,
 			u16 *wake_reason,
 			struct i40e_asq_cmd_details *cmd_details);
 enum i40e_status_code i40e_aq_clear_all_wol_filters(struct i40e_hw *hw,
 			struct i40e_asq_cmd_details *cmd_details);
 enum i40e_status_code i40e_read_phy_register_clause22(struct i40e_hw *hw,
 					u16 reg, u8 phy_addr, u16 *value);
 enum i40e_status_code i40e_write_phy_register_clause22(struct i40e_hw *hw,
 					u16 reg, u8 phy_addr, u16 value);
 enum i40e_status_code i40e_read_phy_register_clause45(struct i40e_hw *hw,
 				u8 page, u16 reg, u8 phy_addr, u16 *value);
 enum i40e_status_code i40e_write_phy_register_clause45(struct i40e_hw *hw,
 				u8 page, u16 reg, u8 phy_addr, u16 value);
 enum i40e_status_code i40e_read_phy_register(struct i40e_hw *hw,
 				u8 page, u16 reg, u8 phy_addr, u16 *value);
 enum i40e_status_code i40e_write_phy_register(struct i40e_hw *hw,
 				u8 page, u16 reg, u8 phy_addr, u16 value);
 u8 i40e_get_phy_address(struct i40e_hw *hw, u8 dev_num);
-enum i40e_status_code i40e_blink_phy_link_led(struct i40e_hw *hw,
-					      u32 time, u32 interval);
 #endif /* _I40E_PROTOTYPE_H_ */
Index: head/sys/dev/ixl/if_ixlv.c
===================================================================
--- head/sys/dev/ixl/if_ixlv.c	(revision 320976)
+++ head/sys/dev/ixl/if_ixlv.c	(revision 320977)
@@ -1,3104 +1,3104 @@
 /******************************************************************************
 
   Copyright (c) 2013-2015, Intel Corporation 
   All rights reserved.
   
   Redistribution and use in source and binary forms, with or without 
   modification, are permitted provided that the following conditions are met:
   
    1. Redistributions of source code must retain the above copyright notice, 
       this list of conditions and the following disclaimer.
   
    2. Redistributions in binary form must reproduce the above copyright 
       notice, this list of conditions and the following disclaimer in the 
       documentation and/or other materials provided with the distribution.
   
    3. Neither the name of the Intel Corporation nor the names of its 
       contributors may be used to endorse or promote products derived from 
       this software without specific prior written permission.
   
   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 
   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 
   ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 
   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 
   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 
   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 
   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 
   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 
   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
   POSSIBILITY OF SUCH DAMAGE.
 
 ******************************************************************************/
 /*$FreeBSD$*/
 
 #include "ixl.h"
 #include "ixlv.h"
 
 /*********************************************************************
  *  Driver version
  *********************************************************************/
 char ixlv_driver_version[] = "1.4.12-k";
 
 /*********************************************************************
  *  PCI Device ID Table
  *
  *  Used by probe to select devices to load on
  *  Last field stores an index into ixlv_strings
  *  Last entry must be all 0s
  *
  *  { Vendor ID, Device ID, SubVendor ID, SubDevice ID, String Index }
  *********************************************************************/
 
 static ixl_vendor_info_t ixlv_vendor_info_array[] =
 {
 	{I40E_INTEL_VENDOR_ID, I40E_DEV_ID_VF, 0, 0, 0},
 	{I40E_INTEL_VENDOR_ID, I40E_DEV_ID_X722_VF, 0, 0, 0},
 	{I40E_INTEL_VENDOR_ID, I40E_DEV_ID_X722_A0_VF, 0, 0, 0},
 	/* required last entry */
 	{0, 0, 0, 0, 0}
 };
 
 /*********************************************************************
  *  Table of branding strings
  *********************************************************************/
 
 static char    *ixlv_strings[] = {
 	"Intel(R) Ethernet Connection XL710/X722 VF Driver"
 };
 
 
 /*********************************************************************
  *  Function prototypes
  *********************************************************************/
 static int      ixlv_probe(device_t);
 static int      ixlv_attach(device_t);
 static int      ixlv_detach(device_t);
 static int      ixlv_shutdown(device_t);
 static void	ixlv_init_locked(struct ixlv_sc *);
 static int	ixlv_allocate_pci_resources(struct ixlv_sc *);
 static void	ixlv_free_pci_resources(struct ixlv_sc *);
 static int	ixlv_assign_msix(struct ixlv_sc *);
 static int	ixlv_init_msix(struct ixlv_sc *);
 static int	ixlv_init_taskqueue(struct ixlv_sc *);
 static int	ixlv_setup_queues(struct ixlv_sc *);
 static void	ixlv_config_rss(struct ixlv_sc *);
 static void	ixlv_stop(struct ixlv_sc *);
 static void	ixlv_add_multi(struct ixl_vsi *);
 static void	ixlv_del_multi(struct ixl_vsi *);
 static void	ixlv_free_queues(struct ixl_vsi *);
 static int	ixlv_setup_interface(device_t, struct ixlv_sc *);
 static int	ixlv_teardown_adminq_msix(struct ixlv_sc *);
 
 static int	ixlv_media_change(struct ifnet *);
 static void	ixlv_media_status(struct ifnet *, struct ifmediareq *);
 
 static void	ixlv_local_timer(void *);
 
 static int	ixlv_add_mac_filter(struct ixlv_sc *, u8 *, u16);
 static int	ixlv_del_mac_filter(struct ixlv_sc *sc, u8 *macaddr);
 static void	ixlv_init_filters(struct ixlv_sc *);
 static void	ixlv_free_filters(struct ixlv_sc *);
 
 static void	ixlv_msix_que(void *);
 static void	ixlv_msix_adminq(void *);
 static void	ixlv_do_adminq(void *, int);
 static void	ixlv_do_adminq_locked(struct ixlv_sc *sc);
 static void	ixlv_handle_que(void *, int);
 static int	ixlv_reset(struct ixlv_sc *);
 static int	ixlv_reset_complete(struct i40e_hw *);
 static void	ixlv_set_queue_rx_itr(struct ixl_queue *);
 static void	ixlv_set_queue_tx_itr(struct ixl_queue *);
 static void	ixl_init_cmd_complete(struct ixl_vc_cmd *, void *,
 		    enum i40e_status_code);
 static void	ixlv_configure_itr(struct ixlv_sc *);
 
 static void	ixlv_enable_adminq_irq(struct i40e_hw *);
 static void	ixlv_disable_adminq_irq(struct i40e_hw *);
 static void	ixlv_enable_queue_irq(struct i40e_hw *, int);
 static void	ixlv_disable_queue_irq(struct i40e_hw *, int);
 
 static void	ixlv_setup_vlan_filters(struct ixlv_sc *);
 static void	ixlv_register_vlan(void *, struct ifnet *, u16);
 static void	ixlv_unregister_vlan(void *, struct ifnet *, u16);
 
 static void	ixlv_init_hw(struct ixlv_sc *);
 static int	ixlv_setup_vc(struct ixlv_sc *);
 static int	ixlv_vf_config(struct ixlv_sc *);
 
 static void	ixlv_cap_txcsum_tso(struct ixl_vsi *,
 		    struct ifnet *, int);
 
 static void	ixlv_add_sysctls(struct ixlv_sc *);
 #ifdef IXL_DEBUG
 static int 	ixlv_sysctl_qtx_tail_handler(SYSCTL_HANDLER_ARGS);
 static int 	ixlv_sysctl_qrx_tail_handler(SYSCTL_HANDLER_ARGS);
 #endif
 
 /*********************************************************************
  *  FreeBSD Device Interface Entry Points
  *********************************************************************/
 
 static device_method_t ixlv_methods[] = {
 	/* Device interface */
 	DEVMETHOD(device_probe, ixlv_probe),
 	DEVMETHOD(device_attach, ixlv_attach),
 	DEVMETHOD(device_detach, ixlv_detach),
 	DEVMETHOD(device_shutdown, ixlv_shutdown),
 	{0, 0}
 };
 
 static driver_t ixlv_driver = {
 	"ixlv", ixlv_methods, sizeof(struct ixlv_sc),
 };
 
 devclass_t ixlv_devclass;
 DRIVER_MODULE(ixlv, pci, ixlv_driver, ixlv_devclass, 0, 0);
 
 MODULE_DEPEND(ixlv, pci, 1, 1, 1);
 MODULE_DEPEND(ixlv, ether, 1, 1, 1);
 
 /*
 ** TUNEABLE PARAMETERS:
 */
 
 static SYSCTL_NODE(_hw, OID_AUTO, ixlv, CTLFLAG_RD, 0,
                    "IXLV driver parameters");
 
 /*
 ** Number of descriptors per ring:
 **   - TX and RX are the same size
 */
 static int ixlv_ringsz = IXL_DEFAULT_RING;
 TUNABLE_INT("hw.ixlv.ringsz", &ixlv_ringsz);
 SYSCTL_INT(_hw_ixlv, OID_AUTO, ring_size, CTLFLAG_RDTUN,
     &ixlv_ringsz, 0, "Descriptor Ring Size");
 
 /* Set to zero to auto calculate  */
 int ixlv_max_queues = 0;
 TUNABLE_INT("hw.ixlv.max_queues", &ixlv_max_queues);
 SYSCTL_INT(_hw_ixlv, OID_AUTO, max_queues, CTLFLAG_RDTUN,
     &ixlv_max_queues, 0, "Number of Queues");
 
 /*
 ** Number of entries in Tx queue buf_ring.
 ** Increasing this will reduce the number of
 ** errors when transmitting fragmented UDP
 ** packets.
 */
 static int ixlv_txbrsz = DEFAULT_TXBRSZ;
 TUNABLE_INT("hw.ixlv.txbrsz", &ixlv_txbrsz);
 SYSCTL_INT(_hw_ixlv, OID_AUTO, txbr_size, CTLFLAG_RDTUN,
     &ixlv_txbrsz, 0, "TX Buf Ring Size");
 
 /*
 ** Controls for Interrupt Throttling
 **      - true/false for dynamic adjustment
 **      - default values for static ITR
 */
 int ixlv_dynamic_rx_itr = 0;
 TUNABLE_INT("hw.ixlv.dynamic_rx_itr", &ixlv_dynamic_rx_itr);
 SYSCTL_INT(_hw_ixlv, OID_AUTO, dynamic_rx_itr, CTLFLAG_RDTUN,
     &ixlv_dynamic_rx_itr, 0, "Dynamic RX Interrupt Rate");
 
 int ixlv_dynamic_tx_itr = 0;
 TUNABLE_INT("hw.ixlv.dynamic_tx_itr", &ixlv_dynamic_tx_itr);
 SYSCTL_INT(_hw_ixlv, OID_AUTO, dynamic_tx_itr, CTLFLAG_RDTUN,
     &ixlv_dynamic_tx_itr, 0, "Dynamic TX Interrupt Rate");
 
 int ixlv_rx_itr = IXL_ITR_8K;
 TUNABLE_INT("hw.ixlv.rx_itr", &ixlv_rx_itr);
 SYSCTL_INT(_hw_ixlv, OID_AUTO, rx_itr, CTLFLAG_RDTUN,
     &ixlv_rx_itr, 0, "RX Interrupt Rate");
 
 int ixlv_tx_itr = IXL_ITR_4K;
 TUNABLE_INT("hw.ixlv.tx_itr", &ixlv_tx_itr);
 SYSCTL_INT(_hw_ixlv, OID_AUTO, tx_itr, CTLFLAG_RDTUN,
     &ixlv_tx_itr, 0, "TX Interrupt Rate");
 
 /*********************************************************************
  *  Device identification routine
  *
  *  ixlv_probe determines if the driver should be loaded on
  *  the hardware based on PCI vendor/device id of the device.
  *
  *  return BUS_PROBE_DEFAULT on success, positive on failure
  *********************************************************************/
 
 static int
 ixlv_probe(device_t dev)
 {
 	ixl_vendor_info_t *ent;
 
 	u16	pci_vendor_id, pci_device_id;
 	u16	pci_subvendor_id, pci_subdevice_id;
 	char	device_name[256];
 
 #if 0
 	INIT_DEBUGOUT("ixlv_probe: begin");
 #endif
 
 	pci_vendor_id = pci_get_vendor(dev);
 	if (pci_vendor_id != I40E_INTEL_VENDOR_ID)
 		return (ENXIO);
 
 	pci_device_id = pci_get_device(dev);
 	pci_subvendor_id = pci_get_subvendor(dev);
 	pci_subdevice_id = pci_get_subdevice(dev);
 
 	ent = ixlv_vendor_info_array;
 	while (ent->vendor_id != 0) {
 		if ((pci_vendor_id == ent->vendor_id) &&
 		    (pci_device_id == ent->device_id) &&
 
 		    ((pci_subvendor_id == ent->subvendor_id) ||
 		     (ent->subvendor_id == 0)) &&
 
 		    ((pci_subdevice_id == ent->subdevice_id) ||
 		     (ent->subdevice_id == 0))) {
 			sprintf(device_name, "%s, Version - %s",
 				ixlv_strings[ent->index],
 				ixlv_driver_version);
 			device_set_desc_copy(dev, device_name);
 			return (BUS_PROBE_DEFAULT);
 		}
 		ent++;
 	}
 	return (ENXIO);
 }
 
 /*********************************************************************
  *  Device initialization routine
  *
  *  The attach entry point is called when the driver is being loaded.
  *  This routine identifies the type of hardware, allocates all resources
  *  and initializes the hardware.
  *
  *  return 0 on success, positive on failure
  *********************************************************************/
 
 static int
 ixlv_attach(device_t dev)
 {
 	struct ixlv_sc	*sc;
 	struct i40e_hw	*hw;
 	struct ixl_vsi 	*vsi;
 	int            	error = 0;
 
 	INIT_DBG_DEV(dev, "begin");
 
 	/* Allocate, clear, and link in our primary soft structure */
 	sc = device_get_softc(dev);
 	sc->dev = sc->osdep.dev = dev;
 	hw = &sc->hw;
 	vsi = &sc->vsi;
 	vsi->dev = dev;
 
 	/* Initialize hw struct */
 	ixlv_init_hw(sc);
 
 	/* Allocate filter lists */
 	ixlv_init_filters(sc);
 
 	/* Core Lock Init */
 	mtx_init(&sc->mtx, device_get_nameunit(dev),
 	    "IXL SC Lock", MTX_DEF);
 
 	/* Set up the timer callout */
 	callout_init_mtx(&sc->timer, &sc->mtx, 0);
 
 	/* Do PCI setup - map BAR0, etc */
 	if (ixlv_allocate_pci_resources(sc)) {
 		device_printf(dev, "%s: Allocation of PCI resources failed\n",
 		    __func__);
 		error = ENXIO;
 		goto err_early;
 	}
 
 	INIT_DBG_DEV(dev, "Allocated PCI resources and MSIX vectors");
 
 	error = i40e_set_mac_type(hw);
 	if (error) {
 		device_printf(dev, "%s: set_mac_type failed: %d\n",
 		    __func__, error);
 		goto err_pci_res;
 	}
 
 	error = ixlv_reset_complete(hw);
 	if (error) {
 		device_printf(dev, "%s: Device is still being reset\n",
 		    __func__);
 		goto err_pci_res;
 	}
 
 	INIT_DBG_DEV(dev, "VF Device is ready for configuration");
 
 	error = ixlv_setup_vc(sc);
 	if (error) {
 		device_printf(dev, "%s: Error setting up PF comms, %d\n",
 		    __func__, error);
 		goto err_pci_res;
 	}
 
 	INIT_DBG_DEV(dev, "PF API version verified");
 
 	/* Need API version before sending reset message */
 	error = ixlv_reset(sc);
 	if (error) {
 		device_printf(dev, "VF reset failed; reload the driver\n");
 		goto err_aq;
 	}
 
 	INIT_DBG_DEV(dev, "VF reset complete");
 
 	/* Ask for VF config from PF */
 	error = ixlv_vf_config(sc);
 	if (error) {
 		device_printf(dev, "Error getting configuration from PF: %d\n",
 		    error);
 		goto err_aq;
 	}
 
 	device_printf(dev, "VSIs %d, QPs %d, MSIX %d, RSS sizes: key %d lut %d\n",
 	    sc->vf_res->num_vsis,
 	    sc->vf_res->num_queue_pairs,
 	    sc->vf_res->max_vectors,
 	    sc->vf_res->rss_key_size,
 	    sc->vf_res->rss_lut_size);
 #ifdef IXL_DEBUG
 	device_printf(dev, "Offload flags: 0x%b\n",
 	    sc->vf_res->vf_offload_flags, IXLV_PRINTF_VF_OFFLOAD_FLAGS);
 #endif
 
 	/* got VF config message back from PF, now we can parse it */
 	for (int i = 0; i < sc->vf_res->num_vsis; i++) {
 		if (sc->vf_res->vsi_res[i].vsi_type == I40E_VSI_SRIOV)
 			sc->vsi_res = &sc->vf_res->vsi_res[i];
 	}
 	if (!sc->vsi_res) {
 		device_printf(dev, "%s: no LAN VSI found\n", __func__);
 		error = EIO;
 		goto err_res_buf;
 	}
 
 	INIT_DBG_DEV(dev, "Resource Acquisition complete");
 
 	/* If no mac address was assigned just make a random one */
 	if (!ixlv_check_ether_addr(hw->mac.addr)) {
 		u8 addr[ETHER_ADDR_LEN];
 		arc4rand(&addr, sizeof(addr), 0);
 		addr[0] &= 0xFE;
 		addr[0] |= 0x02;
 		bcopy(addr, hw->mac.addr, sizeof(addr));
 	}
 
 	/* Now that the number of queues for this VF is known, set up interrupts */
 	sc->msix = ixlv_init_msix(sc);
 	/* We fail without MSIX support */
 	if (sc->msix == 0) {
 		error = ENXIO;
 		goto err_res_buf;
 	}
 
 	vsi->id = sc->vsi_res->vsi_id;
 	vsi->back = (void *)sc;
 	sc->link_up = TRUE;
 
 	/* This allocates the memory and early settings */
 	if (ixlv_setup_queues(sc) != 0) {
 		device_printf(dev, "%s: setup queues failed!\n",
 		    __func__);
 		error = EIO;
 		goto out;
 	}
 
 	/* Setup the stack interface */
 	if (ixlv_setup_interface(dev, sc) != 0) {
 		device_printf(dev, "%s: setup interface failed!\n",
 		    __func__);
 		error = EIO;
 		goto out;
 	}
 
 	INIT_DBG_DEV(dev, "Queue memory and interface setup");
 
 	/* Do queue interrupt setup */
 	if (ixlv_assign_msix(sc) != 0) {
 		device_printf(dev, "%s: allocating queue interrupts failed!\n",
 		    __func__);
 		error = ENXIO;
 		goto out;
 	}
 
 	/* Start AdminQ taskqueue */
 	ixlv_init_taskqueue(sc);
 
 	/* Initialize stats */
 	bzero(&sc->vsi.eth_stats, sizeof(struct i40e_eth_stats));
 	ixlv_add_sysctls(sc);
 
 	/* Register for VLAN events */
 	vsi->vlan_attach = EVENTHANDLER_REGISTER(vlan_config,
 	    ixlv_register_vlan, vsi, EVENTHANDLER_PRI_FIRST);
 	vsi->vlan_detach = EVENTHANDLER_REGISTER(vlan_unconfig,
 	    ixlv_unregister_vlan, vsi, EVENTHANDLER_PRI_FIRST);
 
 	/* We want AQ enabled early */
 	ixlv_enable_adminq_irq(hw);
 
 	/* Set things up to run init */
 	sc->init_state = IXLV_INIT_READY;
 
 	ixl_vc_init_mgr(sc, &sc->vc_mgr);
 
 	INIT_DBG_DEV(dev, "end");
 	return (error);
 
 out:
 	ixlv_free_queues(vsi);
 err_res_buf:
 	free(sc->vf_res, M_DEVBUF);
 err_aq:
 	i40e_shutdown_adminq(hw);
 err_pci_res:
 	ixlv_free_pci_resources(sc);
 err_early:
 	mtx_destroy(&sc->mtx);
 	ixlv_free_filters(sc);
 	INIT_DBG_DEV(dev, "end: error %d", error);
 	return (error);
 }
 
 /*********************************************************************
  *  Device removal routine
  *
  *  The detach entry point is called when the driver is being removed.
  *  This routine stops the adapter and deallocates all the resources
  *  that were allocated for driver operation.
  *
  *  return 0 on success, positive on failure
  *********************************************************************/
 
 static int
 ixlv_detach(device_t dev)
 {
 	struct ixlv_sc	*sc = device_get_softc(dev);
 	struct ixl_vsi 	*vsi = &sc->vsi;
 	struct i40e_hw	*hw = &sc->hw;
 	enum i40e_status_code	status;
 
 	INIT_DBG_DEV(dev, "begin");
 
 	/* Make sure VLANS are not using driver */
 	if (vsi->ifp->if_vlantrunk != NULL) {
 		if_printf(vsi->ifp, "Vlan in use, detach first\n");
 		return (EBUSY);
 	}
 
 	/* Stop driver */
 	ether_ifdetach(vsi->ifp);
 	if (vsi->ifp->if_drv_flags & IFF_DRV_RUNNING) {
 		mtx_lock(&sc->mtx);	
 		ixlv_stop(sc);
 		mtx_unlock(&sc->mtx);	
 	}
 
 	/* Unregister VLAN events */
 	if (vsi->vlan_attach != NULL)
 		EVENTHANDLER_DEREGISTER(vlan_config, vsi->vlan_attach);
 	if (vsi->vlan_detach != NULL)
 		EVENTHANDLER_DEREGISTER(vlan_unconfig, vsi->vlan_detach);
 
 	/* Drain VC mgr */
 	callout_drain(&sc->vc_mgr.callout);
 
 	ixlv_disable_adminq_irq(hw);
 	ixlv_teardown_adminq_msix(sc);
 	/* Drain admin queue taskqueue */
 	taskqueue_free(sc->tq);
 	status = i40e_shutdown_adminq(&sc->hw);
 	if (status != I40E_SUCCESS) {
 		device_printf(dev,
 		    "i40e_shutdown_adminq() failed with status %s\n",
 		    i40e_stat_str(hw, status));
 	}
 
 	if_free(vsi->ifp);
 	free(sc->vf_res, M_DEVBUF);
 	ixlv_free_pci_resources(sc);
 	ixlv_free_queues(vsi);
 	ixlv_free_filters(sc);
 
 	bus_generic_detach(dev);
 	mtx_destroy(&sc->mtx);
 	INIT_DBG_DEV(dev, "end");
 	return (0);
 }
 
 /*********************************************************************
  *
  *  Shutdown entry point
  *
  **********************************************************************/
 
 static int
 ixlv_shutdown(device_t dev)
 {
 	struct ixlv_sc	*sc = device_get_softc(dev);
 
 	INIT_DBG_DEV(dev, "begin");
 
 	mtx_lock(&sc->mtx);	
 	ixlv_stop(sc);
 	mtx_unlock(&sc->mtx);	
 
 	INIT_DBG_DEV(dev, "end");
 	return (0);
 }
 
 /*
  * Configure TXCSUM(IPV6) and TSO(4/6)
  *	- the hardware handles these together so we
  *	  need to tweak them 
  */
 static void
 ixlv_cap_txcsum_tso(struct ixl_vsi *vsi, struct ifnet *ifp, int mask)
 {
 	/* Enable/disable TXCSUM/TSO4 */
 	if (!(ifp->if_capenable & IFCAP_TXCSUM)
 	    && !(ifp->if_capenable & IFCAP_TSO4)) {
 		if (mask & IFCAP_TXCSUM) {
 			ifp->if_capenable |= IFCAP_TXCSUM;
 			/* enable TXCSUM, restore TSO if previously enabled */
 			if (vsi->flags & IXL_FLAGS_KEEP_TSO4) {
 				vsi->flags &= ~IXL_FLAGS_KEEP_TSO4;
 				ifp->if_capenable |= IFCAP_TSO4;
 			}
 		}
 		else if (mask & IFCAP_TSO4) {
 			ifp->if_capenable |= (IFCAP_TXCSUM | IFCAP_TSO4);
 			vsi->flags &= ~IXL_FLAGS_KEEP_TSO4;
 			if_printf(ifp,
 			    "TSO4 requires txcsum, enabling both...\n");
 		}
 	} else if((ifp->if_capenable & IFCAP_TXCSUM)
 	    && !(ifp->if_capenable & IFCAP_TSO4)) {
 		if (mask & IFCAP_TXCSUM)
 			ifp->if_capenable &= ~IFCAP_TXCSUM;
 		else if (mask & IFCAP_TSO4)
 			ifp->if_capenable |= IFCAP_TSO4;
 	} else if((ifp->if_capenable & IFCAP_TXCSUM)
 	    && (ifp->if_capenable & IFCAP_TSO4)) {
 		if (mask & IFCAP_TXCSUM) {
 			vsi->flags |= IXL_FLAGS_KEEP_TSO4;
 			ifp->if_capenable &= ~(IFCAP_TXCSUM | IFCAP_TSO4);
 			if_printf(ifp, 
 			    "TSO4 requires txcsum, disabling both...\n");
 		} else if (mask & IFCAP_TSO4)
 			ifp->if_capenable &= ~IFCAP_TSO4;
 	}
 
 	/* Enable/disable TXCSUM_IPV6/TSO6 */
 	if (!(ifp->if_capenable & IFCAP_TXCSUM_IPV6)
 	    && !(ifp->if_capenable & IFCAP_TSO6)) {
 		if (mask & IFCAP_TXCSUM_IPV6) {
 			ifp->if_capenable |= IFCAP_TXCSUM_IPV6;
 			if (vsi->flags & IXL_FLAGS_KEEP_TSO6) {
 				vsi->flags &= ~IXL_FLAGS_KEEP_TSO6;
 				ifp->if_capenable |= IFCAP_TSO6;
 			}
 		} else if (mask & IFCAP_TSO6) {
 			ifp->if_capenable |= (IFCAP_TXCSUM_IPV6 | IFCAP_TSO6);
 			vsi->flags &= ~IXL_FLAGS_KEEP_TSO6;
 			if_printf(ifp,
 			    "TSO6 requires txcsum6, enabling both...\n");
 		}
 	} else if((ifp->if_capenable & IFCAP_TXCSUM_IPV6)
 	    && !(ifp->if_capenable & IFCAP_TSO6)) {
 		if (mask & IFCAP_TXCSUM_IPV6)
 			ifp->if_capenable &= ~IFCAP_TXCSUM_IPV6;
 		else if (mask & IFCAP_TSO6)
 			ifp->if_capenable |= IFCAP_TSO6;
 	} else if ((ifp->if_capenable & IFCAP_TXCSUM_IPV6)
 	    && (ifp->if_capenable & IFCAP_TSO6)) {
 		if (mask & IFCAP_TXCSUM_IPV6) {
 			vsi->flags |= IXL_FLAGS_KEEP_TSO6;
 			ifp->if_capenable &= ~(IFCAP_TXCSUM_IPV6 | IFCAP_TSO6);
 			if_printf(ifp,
 			    "TSO6 requires txcsum6, disabling both...\n");
 		} else if (mask & IFCAP_TSO6)
 			ifp->if_capenable &= ~IFCAP_TSO6;
 	}
 }
 
 /*********************************************************************
  *  Ioctl entry point
  *
  *  ixlv_ioctl is called when the user wants to configure the
  *  interface.
  *
  *  return 0 on success, positive on failure
  **********************************************************************/
 
 static int
 ixlv_ioctl(struct ifnet *ifp, u_long command, caddr_t data)
 {
 	struct ixl_vsi		*vsi = ifp->if_softc;
 	struct ixlv_sc	*sc = vsi->back;
 	struct ifreq		*ifr = (struct ifreq *)data;
 #if defined(INET) || defined(INET6)
 	struct ifaddr 		*ifa = (struct ifaddr *)data;
 	bool			avoid_reset = FALSE;
 #endif
 	int             	error = 0;
 
 
 	switch (command) {
 
         case SIOCSIFADDR:
 #ifdef INET
 		if (ifa->ifa_addr->sa_family == AF_INET)
 			avoid_reset = TRUE;
 #endif
 #ifdef INET6
 		if (ifa->ifa_addr->sa_family == AF_INET6)
 			avoid_reset = TRUE;
 #endif
 #if defined(INET) || defined(INET6)
 		/*
 		** Calling init results in link renegotiation,
 		** so we avoid doing it when possible.
 		*/
 		if (avoid_reset) {
 			ifp->if_flags |= IFF_UP;
 			if (!(ifp->if_drv_flags & IFF_DRV_RUNNING))
 				ixlv_init(vsi);
 #ifdef INET
 			if (!(ifp->if_flags & IFF_NOARP))
 				arp_ifinit(ifp, ifa);
 #endif
 		} else
 			error = ether_ioctl(ifp, command, data);
 		break;
 #endif
 	case SIOCSIFMTU:
 		IOCTL_DBG_IF2(ifp, "SIOCSIFMTU (Set Interface MTU)");
 		mtx_lock(&sc->mtx);
 		if (ifr->ifr_mtu > IXL_MAX_FRAME -
 		    ETHER_HDR_LEN - ETHER_CRC_LEN - ETHER_VLAN_ENCAP_LEN) {
 			error = EINVAL;
 			IOCTL_DBG_IF(ifp, "mtu too large");
 		} else {
 			IOCTL_DBG_IF2(ifp, "mtu: %lu -> %d", (u_long)ifp->if_mtu, ifr->ifr_mtu);
 			// ERJ: Interestingly enough, these types don't match
 			ifp->if_mtu = (u_long)ifr->ifr_mtu;
 			vsi->max_frame_size =
 			    ifp->if_mtu + ETHER_HDR_LEN + ETHER_CRC_LEN
 			    + ETHER_VLAN_ENCAP_LEN;
 			if (ifp->if_drv_flags & IFF_DRV_RUNNING)
 				ixlv_init_locked(sc);
 		}
 		mtx_unlock(&sc->mtx);
 		break;
 	case SIOCSIFFLAGS:
 		IOCTL_DBG_IF2(ifp, "SIOCSIFFLAGS (Set Interface Flags)");
 		mtx_lock(&sc->mtx);
 		if (ifp->if_flags & IFF_UP) {
 			if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0)
 				ixlv_init_locked(sc);
 		} else
 			if (ifp->if_drv_flags & IFF_DRV_RUNNING)
 				ixlv_stop(sc);
 		sc->if_flags = ifp->if_flags;
 		mtx_unlock(&sc->mtx);
 		break;
 	case SIOCADDMULTI:
 		IOCTL_DBG_IF2(ifp, "SIOCADDMULTI");
 		if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
 			mtx_lock(&sc->mtx);
 			ixlv_disable_intr(vsi);
 			ixlv_add_multi(vsi);
 			ixlv_enable_intr(vsi);
 			mtx_unlock(&sc->mtx);
 		}
 		break;
 	case SIOCDELMULTI:
 		IOCTL_DBG_IF2(ifp, "SIOCDELMULTI");
 		if (sc->init_state == IXLV_RUNNING) {
 			mtx_lock(&sc->mtx);
 			ixlv_disable_intr(vsi);
 			ixlv_del_multi(vsi);
 			ixlv_enable_intr(vsi);
 			mtx_unlock(&sc->mtx);
 		}
 		break;
 	case SIOCSIFMEDIA:
 	case SIOCGIFMEDIA:
 		IOCTL_DBG_IF2(ifp, "SIOCxIFMEDIA (Get/Set Interface Media)");
 		error = ifmedia_ioctl(ifp, ifr, &sc->media, command);
 		break;
 	case SIOCSIFCAP:
 	{
 		int mask = ifr->ifr_reqcap ^ ifp->if_capenable;
 		IOCTL_DBG_IF2(ifp, "SIOCSIFCAP (Set Capabilities)");
 
 		ixlv_cap_txcsum_tso(vsi, ifp, mask);
 
 		if (mask & IFCAP_RXCSUM)
 			ifp->if_capenable ^= IFCAP_RXCSUM;
 		if (mask & IFCAP_RXCSUM_IPV6)
 			ifp->if_capenable ^= IFCAP_RXCSUM_IPV6;
 		if (mask & IFCAP_LRO)
 			ifp->if_capenable ^= IFCAP_LRO;
 		if (mask & IFCAP_VLAN_HWTAGGING)
 			ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING;
 		if (mask & IFCAP_VLAN_HWFILTER)
 			ifp->if_capenable ^= IFCAP_VLAN_HWFILTER;
 		if (mask & IFCAP_VLAN_HWTSO)
 			ifp->if_capenable ^= IFCAP_VLAN_HWTSO;
 		if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
 			ixlv_init(vsi);
 		}
 		VLAN_CAPABILITIES(ifp);
 
 		break;
 	}
 
 	default:
 		IOCTL_DBG_IF2(ifp, "UNKNOWN (0x%X)", (int)command);
 		error = ether_ioctl(ifp, command, data);
 		break;
 	}
 
 	return (error);
 }
 
 /*
 ** To do a reinit on the VF is unfortunately more complicated
 ** than a physical device, we must have the PF more or less
 ** completely recreate our memory, so many things that were
 ** done only once at attach in traditional drivers now must be
 ** redone at each reinitialization. This function does that
 ** 'prelude' so we can then call the normal locked init code.
 */
 int
 ixlv_reinit_locked(struct ixlv_sc *sc)
 {
 	struct i40e_hw		*hw = &sc->hw;
 	struct ixl_vsi		*vsi = &sc->vsi;
 	struct ifnet		*ifp = vsi->ifp;
 	struct ixlv_mac_filter  *mf, *mf_temp;
 	struct ixlv_vlan_filter	*vf;
 	int			error = 0;
 
 	INIT_DBG_IF(ifp, "begin");
 
 	if (ifp->if_drv_flags & IFF_DRV_RUNNING)
 		ixlv_stop(sc);
 
 	error = ixlv_reset(sc);
 
 	INIT_DBG_IF(ifp, "VF was reset");
 
 	/* set the state in case we went thru RESET */
 	sc->init_state = IXLV_RUNNING;
 
 	/*
 	** Resetting the VF drops all filters from hardware;
 	** we need to mark them to be re-added in init.
 	*/
 	SLIST_FOREACH_SAFE(mf, sc->mac_filters, next, mf_temp) {
 		if (mf->flags & IXL_FILTER_DEL) {
 			SLIST_REMOVE(sc->mac_filters, mf,
 			    ixlv_mac_filter, next);
 			free(mf, M_DEVBUF);
 		} else
 			mf->flags |= IXL_FILTER_ADD;
 	}
 	if (vsi->num_vlans != 0)
 		SLIST_FOREACH(vf, sc->vlan_filters, next)
 			vf->flags = IXL_FILTER_ADD;
 	else { /* clean any stale filters */
 		while (!SLIST_EMPTY(sc->vlan_filters)) {
 			vf = SLIST_FIRST(sc->vlan_filters);
 			SLIST_REMOVE_HEAD(sc->vlan_filters, next);
 			free(vf, M_DEVBUF);
 		}
 	}
 
 	ixlv_enable_adminq_irq(hw);
 	ixl_vc_flush(&sc->vc_mgr);
 
 	INIT_DBG_IF(ifp, "end");
 	return (error);
 }
 
 static void
 ixl_init_cmd_complete(struct ixl_vc_cmd *cmd, void *arg,
 	enum i40e_status_code code)
 {
 	struct ixlv_sc *sc;
 
 	sc = arg;
 
 	/*
 	 * Ignore "Adapter Stopped" message as that happens if an ifconfig down
 	 * happens while a command is in progress, so we don't print an error
 	 * in that case.
 	 */
 	if (code != I40E_SUCCESS && code != I40E_ERR_ADAPTER_STOPPED) {
 		if_printf(sc->vsi.ifp,
 		    "Error %s waiting for PF to complete operation %d\n",
 		    i40e_stat_str(&sc->hw, code), cmd->request);
 	}
 }
 
 static void
 ixlv_init_locked(struct ixlv_sc *sc)
 {
 	struct i40e_hw		*hw = &sc->hw;
 	struct ixl_vsi		*vsi = &sc->vsi;
 	struct ixl_queue	*que = vsi->queues;
 	struct ifnet		*ifp = vsi->ifp;
 	int			 error = 0;
 
 	INIT_DBG_IF(ifp, "begin");
 
 	IXLV_CORE_LOCK_ASSERT(sc);
 
 	/* Do a reinit first if an init has already been done */
 	if ((sc->init_state == IXLV_RUNNING) ||
 	    (sc->init_state == IXLV_RESET_REQUIRED) ||
 	    (sc->init_state == IXLV_RESET_PENDING))
 		error = ixlv_reinit_locked(sc);
 	/* Don't bother with init if we failed reinit */
 	if (error)
 		goto init_done;
 
 	/* Remove existing MAC filter if new MAC addr is set */
 	if (bcmp(IF_LLADDR(ifp), hw->mac.addr, ETHER_ADDR_LEN) != 0) {
 		error = ixlv_del_mac_filter(sc, hw->mac.addr);
 		if (error == 0)
 			ixl_vc_enqueue(&sc->vc_mgr, &sc->del_mac_cmd, 
 			    IXLV_FLAG_AQ_DEL_MAC_FILTER, ixl_init_cmd_complete,
 			    sc);
 	}
 
 	/* Check for an LAA mac address... */
 	bcopy(IF_LLADDR(ifp), hw->mac.addr, ETHER_ADDR_LEN);
 
 	ifp->if_hwassist = 0;
 	if (ifp->if_capenable & IFCAP_TSO)
 		ifp->if_hwassist |= CSUM_TSO;
 	if (ifp->if_capenable & IFCAP_TXCSUM)
 		ifp->if_hwassist |= (CSUM_OFFLOAD_IPV4 & ~CSUM_IP);
 	if (ifp->if_capenable & IFCAP_TXCSUM_IPV6)
 		ifp->if_hwassist |= CSUM_OFFLOAD_IPV6;
 
 	/* Add mac filter for this VF to PF */
 	if (i40e_validate_mac_addr(hw->mac.addr) == I40E_SUCCESS) {
 		error = ixlv_add_mac_filter(sc, hw->mac.addr, 0);
 		if (!error || error == EEXIST)
 			ixl_vc_enqueue(&sc->vc_mgr, &sc->add_mac_cmd,
 			    IXLV_FLAG_AQ_ADD_MAC_FILTER, ixl_init_cmd_complete,
 			    sc);
 	}
 
 	/* Setup vlan's if needed */
 	ixlv_setup_vlan_filters(sc);
 
 	/* Prepare the queues for operation */
 	for (int i = 0; i < vsi->num_queues; i++, que++) {
 		struct  rx_ring	*rxr = &que->rxr;
 
 		ixl_init_tx_ring(que);
 
 		if (vsi->max_frame_size <= MCLBYTES)
 			rxr->mbuf_sz = MCLBYTES;
 		else
 			rxr->mbuf_sz = MJUMPAGESIZE;
 		ixl_init_rx_ring(que);
 	}
 
 	/* Set initial ITR values */
 	ixlv_configure_itr(sc);
 
 	/* Configure queues */
 	ixl_vc_enqueue(&sc->vc_mgr, &sc->config_queues_cmd,
 	    IXLV_FLAG_AQ_CONFIGURE_QUEUES, ixl_init_cmd_complete, sc);
 
 	/* Set up RSS */
 	ixlv_config_rss(sc);
 
 	/* Map vectors */
 	ixl_vc_enqueue(&sc->vc_mgr, &sc->map_vectors_cmd, 
 	    IXLV_FLAG_AQ_MAP_VECTORS, ixl_init_cmd_complete, sc);
 
 	/* Enable queues */
 	ixl_vc_enqueue(&sc->vc_mgr, &sc->enable_queues_cmd,
 	    IXLV_FLAG_AQ_ENABLE_QUEUES, ixl_init_cmd_complete, sc);
 
 	/* Start the local timer */
 	callout_reset(&sc->timer, hz, ixlv_local_timer, sc);
 
 	sc->init_state = IXLV_RUNNING;
 
 init_done:
 	INIT_DBG_IF(ifp, "end");
 	return;
 }
 
 /*
 **  Init entry point for the stack
 */
 void
 ixlv_init(void *arg)
 {
 	struct ixl_vsi *vsi = (struct ixl_vsi *)arg;
 	struct ixlv_sc *sc = vsi->back;
 	int retries = 0;
 
 	/* Prevent init from running again while waiting for AQ calls
 	 * made in init_locked() to complete. */
 	mtx_lock(&sc->mtx);
 	if (sc->init_in_progress) {
 		mtx_unlock(&sc->mtx);
 		return;
 	} else
 		sc->init_in_progress = true;
 
 	ixlv_init_locked(sc);
 	mtx_unlock(&sc->mtx);
 
 	/* Wait for init_locked to finish */
 	while (!(vsi->ifp->if_drv_flags & IFF_DRV_RUNNING)
 	    && ++retries < IXLV_MAX_INIT_WAIT) {
 		i40e_msec_pause(25);
 	}
 	if (retries >= IXLV_MAX_INIT_WAIT) {
 		if_printf(vsi->ifp,
 		    "Init failed to complete in allotted time!\n");
 	}
 
 	mtx_lock(&sc->mtx);
 	sc->init_in_progress = false;
 	mtx_unlock(&sc->mtx);
 }
 
 /*
  * ixlv_attach() helper function; gathers information about
  * the (virtual) hardware for use elsewhere in the driver.
  */
 static void
 ixlv_init_hw(struct ixlv_sc *sc)
 {
 	struct i40e_hw *hw = &sc->hw;
 	device_t dev = sc->dev;
 	
 	/* Save off the information about this board */
 	hw->vendor_id = pci_get_vendor(dev);
 	hw->device_id = pci_get_device(dev);
 	hw->revision_id = pci_read_config(dev, PCIR_REVID, 1);
 	hw->subsystem_vendor_id =
 	    pci_read_config(dev, PCIR_SUBVEND_0, 2);
 	hw->subsystem_device_id =
 	    pci_read_config(dev, PCIR_SUBDEV_0, 2);
 
 	hw->bus.device = pci_get_slot(dev);
 	hw->bus.func = pci_get_function(dev);
 }
 
 /*
  * ixlv_attach() helper function; initalizes the admin queue
  * and attempts to establish contact with the PF by
  * retrying the initial "API version" message several times
  * or until the PF responds.
  */
 static int
 ixlv_setup_vc(struct ixlv_sc *sc)
 {
 	struct i40e_hw *hw = &sc->hw;
 	device_t dev = sc->dev;
 	int error = 0, ret_error = 0, asq_retries = 0;
 	bool send_api_ver_retried = 0;
 
 	/* Need to set these AQ paramters before initializing AQ */
 	hw->aq.num_arq_entries = IXL_AQ_LEN;
 	hw->aq.num_asq_entries = IXL_AQ_LEN;
 	hw->aq.arq_buf_size = IXL_AQ_BUF_SZ;
 	hw->aq.asq_buf_size = IXL_AQ_BUF_SZ;
 
 	for (int i = 0; i < IXLV_AQ_MAX_ERR; i++) {
 		/* Initialize admin queue */
 		error = i40e_init_adminq(hw);
 		if (error) {
 			device_printf(dev, "%s: init_adminq failed: %d\n",
 			    __func__, error);
 			ret_error = 1;
 			continue;
 		}
 
 		INIT_DBG_DEV(dev, "Initialized Admin Queue; starting"
 		    " send_api_ver attempt %d", i+1);
 
 retry_send:
 		/* Send VF's API version */
 		error = ixlv_send_api_ver(sc);
 		if (error) {
 			i40e_shutdown_adminq(hw);
 			ret_error = 2;
 			device_printf(dev, "%s: unable to send api"
 			    " version to PF on attempt %d, error %d\n",
 			    __func__, i+1, error);
 		}
 
 		asq_retries = 0;
 		while (!i40e_asq_done(hw)) {
 			if (++asq_retries > IXLV_AQ_MAX_ERR) {
 				i40e_shutdown_adminq(hw);
 				device_printf(dev, "Admin Queue timeout "
 				    "(waiting for send_api_ver), %d more tries...\n",
 				    IXLV_AQ_MAX_ERR - (i + 1));
 				ret_error = 3;
 				break;
 			} 
 			i40e_msec_pause(10);
 		}
 		if (asq_retries > IXLV_AQ_MAX_ERR)
 			continue;
 
 		INIT_DBG_DEV(dev, "Sent API version message to PF");
 
 		/* Verify that the VF accepts the PF's API version */
 		error = ixlv_verify_api_ver(sc);
 		if (error == ETIMEDOUT) {
 			if (!send_api_ver_retried) {
 				/* Resend message, one more time */
-				send_api_ver_retried++;
+				send_api_ver_retried = true;
 				device_printf(dev,
 				    "%s: Timeout while verifying API version on first"
 				    " try!\n", __func__);
 				goto retry_send;
 			} else {
 				device_printf(dev,
 				    "%s: Timeout while verifying API version on second"
 				    " try!\n", __func__);
 				ret_error = 4;
 				break;
 			}
 		}
 		if (error) {
 			device_printf(dev,
 			    "%s: Unable to verify API version,"
 			    " error %s\n", __func__, i40e_stat_str(hw, error));
 			ret_error = 5;
 		}
 		break;
 	}
 
 	if (ret_error >= 4)
 		i40e_shutdown_adminq(hw);
 	return (ret_error);
 }
 
 /*
  * ixlv_attach() helper function; asks the PF for this VF's
  * configuration, and saves the information if it receives it.
  */
 static int
 ixlv_vf_config(struct ixlv_sc *sc)
 {
 	struct i40e_hw *hw = &sc->hw;
 	device_t dev = sc->dev;
 	int bufsz, error = 0, ret_error = 0;
 	int asq_retries, retried = 0;
 
 retry_config:
 	error = ixlv_send_vf_config_msg(sc);
 	if (error) {
 		device_printf(dev,
 		    "%s: Unable to send VF config request, attempt %d,"
 		    " error %d\n", __func__, retried + 1, error);
 		ret_error = 2;
 	}
 
 	asq_retries = 0;
 	while (!i40e_asq_done(hw)) {
 		if (++asq_retries > IXLV_AQ_MAX_ERR) {
 			device_printf(dev, "%s: Admin Queue timeout "
 			    "(waiting for send_vf_config_msg), attempt %d\n",
 			    __func__, retried + 1);
 			ret_error = 3;
 			goto fail;
 		}
 		i40e_msec_pause(10);
 	}
 
 	INIT_DBG_DEV(dev, "Sent VF config message to PF, attempt %d",
 	    retried + 1);
 
 	if (!sc->vf_res) {
 		bufsz = sizeof(struct i40e_virtchnl_vf_resource) +
 		    (I40E_MAX_VF_VSI * sizeof(struct i40e_virtchnl_vsi_resource));
 		sc->vf_res = malloc(bufsz, M_DEVBUF, M_NOWAIT);
 		if (!sc->vf_res) {
 			device_printf(dev,
 			    "%s: Unable to allocate memory for VF configuration"
 			    " message from PF on attempt %d\n", __func__, retried + 1);
 			ret_error = 1;
 			goto fail;
 		}
 	}
 
 	/* Check for VF config response */
 	error = ixlv_get_vf_config(sc);
 	if (error == ETIMEDOUT) {
 		/* The 1st time we timeout, send the configuration message again */
 		if (!retried) {
 			retried++;
 			goto retry_config;
 		}
 		device_printf(dev,
 		    "%s: ixlv_get_vf_config() timed out waiting for a response\n",
 		    __func__);
 	}
 	if (error) {
 		device_printf(dev,
 		    "%s: Unable to get VF configuration from PF after %d tries!\n",
 		    __func__, retried + 1);
 		ret_error = 4;
 	}
 	goto done;
 
 fail:
 	free(sc->vf_res, M_DEVBUF);
 done:
 	return (ret_error);
 }
 
 /*
  * Allocate MSI/X vectors, setup the AQ vector early
  */
 static int
 ixlv_init_msix(struct ixlv_sc *sc)
 {
 	device_t dev = sc->dev;
 	int rid, want, vectors, queues, available;
 	int auto_max_queues;
 
 	rid = PCIR_BAR(IXL_MSIX_BAR);
 	sc->msix_mem = bus_alloc_resource_any(dev,
 	    SYS_RES_MEMORY, &rid, RF_ACTIVE);
        	if (!sc->msix_mem) {
 		/* May not be enabled */
 		device_printf(sc->dev,
 		    "Unable to map MSIX table\n");
 		goto fail;
 	}
 
 	available = pci_msix_count(dev); 
 	if (available == 0) { /* system has msix disabled */
 		bus_release_resource(dev, SYS_RES_MEMORY,
 		    rid, sc->msix_mem);
 		sc->msix_mem = NULL;
 		goto fail;
 	}
 
 	/* Clamp queues to number of CPUs and # of MSI-X vectors available */
 	auto_max_queues = min(mp_ncpus, available - 1);
 	/* Clamp queues to # assigned to VF by PF */
 	auto_max_queues = min(auto_max_queues, sc->vf_res->num_queue_pairs);
 
 	/* Override with tunable value if tunable is less than autoconfig count */
 	if ((ixlv_max_queues != 0) && (ixlv_max_queues <= auto_max_queues))
 		queues = ixlv_max_queues;
 	/* Use autoconfig amount if that's lower */
 	else if ((ixlv_max_queues != 0) && (ixlv_max_queues > auto_max_queues)) {
 		device_printf(dev, "ixlv_max_queues (%d) is too large, using "
 		    "autoconfig amount (%d)...\n",
 		    ixlv_max_queues, auto_max_queues);
 		queues = auto_max_queues;
 	}
 	/* Limit maximum auto-configured queues to 8 if no user value is set */
 	else
 		queues = min(auto_max_queues, 8);
 
 #ifdef  RSS
 	/* If we're doing RSS, clamp at the number of RSS buckets */
 	if (queues > rss_getnumbuckets())
 		queues = rss_getnumbuckets();
 #endif
 
 	/*
 	** Want one vector (RX/TX pair) per queue
 	** plus an additional for the admin queue.
 	*/
 	want = queues + 1;
 	if (want <= available)	/* Have enough */
 		vectors = want;
 	else {
 		device_printf(sc->dev,
 		    "MSIX Configuration Problem, "
 		    "%d vectors available but %d wanted!\n",
 		    available, want);
 		goto fail;
 	}
 
 #ifdef RSS
 	/*
 	* If we're doing RSS, the number of queues needs to
 	* match the number of RSS buckets that are configured.
 	*
 	* + If there's more queues than RSS buckets, we'll end
 	*   up with queues that get no traffic.
 	*
 	* + If there's more RSS buckets than queues, we'll end
 	*   up having multiple RSS buckets map to the same queue,
 	*   so there'll be some contention.
 	*/
 	if (queues != rss_getnumbuckets()) {
 		device_printf(dev,
 		    "%s: queues (%d) != RSS buckets (%d)"
 		    "; performance will be impacted.\n",
 		     __func__, queues, rss_getnumbuckets());
 	}
 #endif
 
 	if (pci_alloc_msix(dev, &vectors) == 0) {
 		device_printf(sc->dev,
 		    "Using MSIX interrupts with %d vectors\n", vectors);
 		sc->msix = vectors;
 		sc->vsi.num_queues = queues;
 	}
 
 	/* Next we need to setup the vector for the Admin Queue */
 	rid = 1;	/* zero vector + 1 */
 	sc->res = bus_alloc_resource_any(dev, SYS_RES_IRQ,
 	    &rid, RF_SHAREABLE | RF_ACTIVE);
 	if (sc->res == NULL) {
 		device_printf(dev, "Unable to allocate"
 		    " bus resource: AQ interrupt \n");
 		goto fail;
 	}
 	if (bus_setup_intr(dev, sc->res,
 	    INTR_TYPE_NET | INTR_MPSAFE, NULL,
 	    ixlv_msix_adminq, sc, &sc->tag)) {
 		sc->res = NULL;
 		device_printf(dev, "Failed to register AQ handler");
 		goto fail;
 	}
 	bus_describe_intr(dev, sc->res, sc->tag, "adminq");
 
 	return (vectors);
 
 fail:
 	/* The VF driver MUST use MSIX */
 	return (0);
 }
 
 static int
 ixlv_allocate_pci_resources(struct ixlv_sc *sc)
 {
 	int             rid;
 	device_t        dev = sc->dev;
 
 	rid = PCIR_BAR(0);
 	sc->pci_mem = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
 	    &rid, RF_ACTIVE);
 
 	if (!(sc->pci_mem)) {
 		device_printf(dev, "Unable to allocate bus resource: memory\n");
 		return (ENXIO);
 	}
 
 	sc->osdep.mem_bus_space_tag =
 		rman_get_bustag(sc->pci_mem);
 	sc->osdep.mem_bus_space_handle =
 		rman_get_bushandle(sc->pci_mem);
 	sc->osdep.mem_bus_space_size = rman_get_size(sc->pci_mem);
 	sc->osdep.flush_reg = I40E_VFGEN_RSTAT;
 	sc->hw.hw_addr = (u8 *) &sc->osdep.mem_bus_space_handle;
 
 	sc->hw.back = &sc->osdep;
 
 	/*
 	** Explicitly set the guest PCI BUSMASTER capability
 	** and we must rewrite the ENABLE in the MSIX control
 	** register again at this point to cause the host to
 	** successfully initialize us.
 	**
 	** This must be set before accessing any registers.
 	*/
 	{
 		u16 pci_cmd_word;
 		int msix_ctrl;
 		pci_cmd_word = pci_read_config(dev, PCIR_COMMAND, 2);
 		pci_cmd_word |= PCIM_CMD_BUSMASTEREN;
 		pci_write_config(dev, PCIR_COMMAND, pci_cmd_word, 2);
 		pci_find_cap(dev, PCIY_MSIX, &rid);
 		rid += PCIR_MSIX_CTRL;
 		msix_ctrl = pci_read_config(dev, rid, 2);
 		msix_ctrl |= PCIM_MSIXCTRL_MSIX_ENABLE;
 		pci_write_config(dev, rid, msix_ctrl, 2);
 	}
 
 	/* Disable adminq interrupts (just in case) */
 	ixlv_disable_adminq_irq(&sc->hw);
 
 	return (0);
 }
 
 static void
 ixlv_free_pci_resources(struct ixlv_sc *sc)
 {
 	struct ixl_vsi         *vsi = &sc->vsi;
 	struct ixl_queue       *que = vsi->queues;
 	device_t                dev = sc->dev;
 
 	/* We may get here before stations are setup */
 	if (que == NULL)
 		goto early;
 
 	/*
 	**  Release all msix queue resources:
 	*/
 	for (int i = 0; i < vsi->num_queues; i++, que++) {
 		int rid = que->msix + 1;
 		if (que->tag != NULL) {
 			bus_teardown_intr(dev, que->res, que->tag);
 			que->tag = NULL;
 		}
 		if (que->res != NULL) {
 			bus_release_resource(dev, SYS_RES_IRQ, rid, que->res);
 			que->res = NULL;
 		}
 	}
         
 early:
 	pci_release_msi(dev);
 
 	if (sc->msix_mem != NULL)
 		bus_release_resource(dev, SYS_RES_MEMORY,
 		    PCIR_BAR(IXL_MSIX_BAR), sc->msix_mem);
 
 	if (sc->pci_mem != NULL)
 		bus_release_resource(dev, SYS_RES_MEMORY,
 		    PCIR_BAR(0), sc->pci_mem);
 }
 
 /*
  * Create taskqueue and tasklet for Admin Queue interrupts.
  */
 static int
 ixlv_init_taskqueue(struct ixlv_sc *sc)
 {
 	int error = 0;
 
 	TASK_INIT(&sc->aq_irq, 0, ixlv_do_adminq, sc);
 
 	sc->tq = taskqueue_create_fast("ixl_adm", M_NOWAIT,
 	    taskqueue_thread_enqueue, &sc->tq);
 	taskqueue_start_threads(&sc->tq, 1, PI_NET, "%s sc->tq",
 	    device_get_nameunit(sc->dev));
 
 	return (error);
 }
 
 /*********************************************************************
  *
  *  Setup MSIX Interrupt resources and handlers for the VSI queues
  *
  **********************************************************************/
 static int
 ixlv_assign_msix(struct ixlv_sc *sc)
 {
 	device_t	dev = sc->dev;
 	struct 		ixl_vsi *vsi = &sc->vsi;
 	struct 		ixl_queue *que = vsi->queues;
 	struct		tx_ring	 *txr;
 	int 		error, rid, vector = 1;
 #ifdef	RSS
 	cpuset_t	cpu_mask;
 #endif
 
 	for (int i = 0; i < vsi->num_queues; i++, vector++, que++) {
 		int cpu_id = i;
 		rid = vector + 1;
 		txr = &que->txr;
 		que->res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
 		    RF_SHAREABLE | RF_ACTIVE);
 		if (que->res == NULL) {
 			device_printf(dev,"Unable to allocate"
 		    	    " bus resource: que interrupt [%d]\n", vector);
 			return (ENXIO);
 		}
 		/* Set the handler function */
 		error = bus_setup_intr(dev, que->res,
 		    INTR_TYPE_NET | INTR_MPSAFE, NULL,
 		    ixlv_msix_que, que, &que->tag);
 		if (error) {
 			que->res = NULL;
 			device_printf(dev, "Failed to register que handler");
 			return (error);
 		}
 		bus_describe_intr(dev, que->res, que->tag, "que %d", i);
 		/* Bind the vector to a CPU */
 #ifdef RSS
 		cpu_id = rss_getcpu(i % rss_getnumbuckets());
 #endif
 		bus_bind_intr(dev, que->res, cpu_id);
 		que->msix = vector;
 		TASK_INIT(&que->tx_task, 0, ixl_deferred_mq_start, que);
 		TASK_INIT(&que->task, 0, ixlv_handle_que, que);
 		que->tq = taskqueue_create_fast("ixlv_que", M_NOWAIT,
 		    taskqueue_thread_enqueue, &que->tq);
 #ifdef RSS
 		CPU_SETOF(cpu_id, &cpu_mask);
 		taskqueue_start_threads_cpuset(&que->tq, 1, PI_NET,
 		    &cpu_mask, "%s (bucket %d)",
 		    device_get_nameunit(dev), cpu_id);
 #else
                 taskqueue_start_threads(&que->tq, 1, PI_NET,
                     "%s que", device_get_nameunit(dev));
 #endif
 
 	}
 
 	return (0);
 }
 
 /*
 ** Requests a VF reset from the PF.
 **
 ** Requires the VF's Admin Queue to be initialized.
 */
 static int
 ixlv_reset(struct ixlv_sc *sc)
 {
 	struct i40e_hw	*hw = &sc->hw;
 	device_t	dev = sc->dev;
 	int		error = 0;
 
 	/* Ask the PF to reset us if we are initiating */
 	if (sc->init_state != IXLV_RESET_PENDING)
 		ixlv_request_reset(sc);
 
 	i40e_msec_pause(100);
 	error = ixlv_reset_complete(hw);
 	if (error) {
 		device_printf(dev, "%s: VF reset failed\n",
 		    __func__);
 		return (error);
 	}
 
 	error = i40e_shutdown_adminq(hw);
 	if (error) {
 		device_printf(dev, "%s: shutdown_adminq failed: %d\n",
 		    __func__, error);
 		return (error);
 	}
 
 	error = i40e_init_adminq(hw);
 	if (error) {
 		device_printf(dev, "%s: init_adminq failed: %d\n",
 		    __func__, error);
 		return(error);
 	}
 
 	return (0);
 }
 
 static int
 ixlv_reset_complete(struct i40e_hw *hw)
 {
 	u32 reg;
 
 	/* Wait up to ~10 seconds */
 	for (int i = 0; i < 100; i++) {
 		reg = rd32(hw, I40E_VFGEN_RSTAT) &
 		    I40E_VFGEN_RSTAT_VFR_STATE_MASK;
 
                 if ((reg == I40E_VFR_VFACTIVE) ||
 		    (reg == I40E_VFR_COMPLETED))
 			return (0);
 		i40e_msec_pause(100);
 	}
 
 	return (EBUSY);
 }
 
 
 /*********************************************************************
  *
  *  Setup networking device structure and register an interface.
  *
  **********************************************************************/
 static int
 ixlv_setup_interface(device_t dev, struct ixlv_sc *sc)
 {
 	struct ifnet		*ifp;
 	struct ixl_vsi		*vsi = &sc->vsi;
 	struct ixl_queue	*que = vsi->queues;
 
 	INIT_DBG_DEV(dev, "begin");
 
 	ifp = vsi->ifp = if_alloc(IFT_ETHER);
 	if (ifp == NULL) {
 		device_printf(dev, "%s: could not allocate ifnet"
 		    " structure!\n", __func__);
 		return (-1);
 	}
 
 	if_initname(ifp, device_get_name(dev), device_get_unit(dev));
 
 	ifp->if_mtu = ETHERMTU;
 	ifp->if_baudrate = IF_Gbps(40);
 	ifp->if_init = ixlv_init;
 	ifp->if_softc = vsi;
 	ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
 	ifp->if_ioctl = ixlv_ioctl;
 
 #if __FreeBSD_version >= 1100000
 	if_setgetcounterfn(ifp, ixl_get_counter);
 #endif
 
 	ifp->if_transmit = ixl_mq_start;
 
 	ifp->if_qflush = ixl_qflush;
 	ifp->if_snd.ifq_maxlen = que->num_desc - 2;
 
 	ether_ifattach(ifp, sc->hw.mac.addr);
 
 	vsi->max_frame_size =
 	    ifp->if_mtu + ETHER_HDR_LEN + ETHER_CRC_LEN
 	    + ETHER_VLAN_ENCAP_LEN;
 
 	/*
 	 * Tell the upper layer(s) we support long frames.
 	 */
 	ifp->if_hdrlen = sizeof(struct ether_vlan_header);
 
 	ifp->if_capabilities |= IFCAP_HWCSUM;
 	ifp->if_capabilities |= IFCAP_HWCSUM_IPV6;
 	ifp->if_capabilities |= IFCAP_TSO;
 	ifp->if_capabilities |= IFCAP_JUMBO_MTU;
 
 	ifp->if_capabilities |= IFCAP_VLAN_HWTAGGING
 			     |  IFCAP_VLAN_HWTSO
 			     |  IFCAP_VLAN_MTU
 			     |  IFCAP_VLAN_HWCSUM
 			     |  IFCAP_LRO;
 	ifp->if_capenable = ifp->if_capabilities;
 
 	/*
 	** Don't turn this on by default, if vlans are
 	** created on another pseudo device (eg. lagg)
 	** then vlan events are not passed thru, breaking
 	** operation, but with HW FILTER off it works. If
 	** using vlans directly on the ixl driver you can
 	** enable this and get full hardware tag filtering.
 	*/
 	ifp->if_capabilities |= IFCAP_VLAN_HWFILTER;
 
 	/*
 	 * Specify the media types supported by this adapter and register
 	 * callbacks to update media and link information
 	 */
 	ifmedia_init(&sc->media, IFM_IMASK, ixlv_media_change,
 		     ixlv_media_status);
 
 	// JFV Add media types later?
 
 	ifmedia_add(&sc->media, IFM_ETHER | IFM_AUTO, 0, NULL);
 	ifmedia_set(&sc->media, IFM_ETHER | IFM_AUTO);
 
 	INIT_DBG_DEV(dev, "end");
 	return (0);
 }
 
 /*
 ** Allocate and setup the interface queues
 */
 static int
 ixlv_setup_queues(struct ixlv_sc *sc)
 {
 	device_t		dev = sc->dev;
 	struct ixl_vsi		*vsi;
 	struct ixl_queue	*que;
 	struct tx_ring		*txr;
 	struct rx_ring		*rxr;
 	int 			rsize, tsize;
 	int			error = I40E_SUCCESS;
 
 	vsi = &sc->vsi;
 	vsi->back = (void *)sc;
 	vsi->hw = &sc->hw;
 	vsi->num_vlans = 0;
 
 	/* Get memory for the station queues */
 	if (!(vsi->queues =
 		(struct ixl_queue *) malloc(sizeof(struct ixl_queue) *
 		vsi->num_queues, M_DEVBUF, M_NOWAIT | M_ZERO))) {
 			device_printf(dev, "Unable to allocate queue memory\n");
 			error = ENOMEM;
 			goto early;
 	}
 
 	for (int i = 0; i < vsi->num_queues; i++) {
 		que = &vsi->queues[i];
 		que->num_desc = ixlv_ringsz;
 		que->me = i;
 		que->vsi = vsi;
 
 		txr = &que->txr;
 		txr->que = que;
 		txr->tail = I40E_QTX_TAIL1(que->me);
 		/* Initialize the TX lock */
 		snprintf(txr->mtx_name, sizeof(txr->mtx_name), "%s:tx(%d)",
 		    device_get_nameunit(dev), que->me);
 		mtx_init(&txr->mtx, txr->mtx_name, NULL, MTX_DEF);
 		/*
 		** Create the TX descriptor ring, the extra int is
 		** added as the location for HEAD WB.
 		*/
 		tsize = roundup2((que->num_desc *
 		    sizeof(struct i40e_tx_desc)) +
 		    sizeof(u32), DBA_ALIGN);
 		if (i40e_allocate_dma_mem(&sc->hw,
 		    &txr->dma, i40e_mem_reserved, tsize, DBA_ALIGN)) {
 			device_printf(dev,
 			    "Unable to allocate TX Descriptor memory\n");
 			error = ENOMEM;
 			goto fail;
 		}
 		txr->base = (struct i40e_tx_desc *)txr->dma.va;
 		bzero((void *)txr->base, tsize);
 		/* Now allocate transmit soft structs for the ring */
 		if (ixl_allocate_tx_data(que)) {
 			device_printf(dev,
 			    "Critical Failure setting up TX structures\n");
 			error = ENOMEM;
 			goto fail;
 		}
 		/* Allocate a buf ring */
 		txr->br = buf_ring_alloc(ixlv_txbrsz, M_DEVBUF,
 		    M_WAITOK, &txr->mtx);
 		if (txr->br == NULL) {
 			device_printf(dev,
 			    "Critical Failure setting up TX buf ring\n");
 			error = ENOMEM;
 			goto fail;
 		}
 
 		/*
 		 * Next the RX queues...
 		 */ 
 		rsize = roundup2(que->num_desc *
 		    sizeof(union i40e_rx_desc), DBA_ALIGN);
 		rxr = &que->rxr;
 		rxr->que = que;
 		rxr->tail = I40E_QRX_TAIL1(que->me);
 
 		/* Initialize the RX side lock */
 		snprintf(rxr->mtx_name, sizeof(rxr->mtx_name), "%s:rx(%d)",
 		    device_get_nameunit(dev), que->me);
 		mtx_init(&rxr->mtx, rxr->mtx_name, NULL, MTX_DEF);
 
 		if (i40e_allocate_dma_mem(&sc->hw,
 		    &rxr->dma, i40e_mem_reserved, rsize, 4096)) { //JFV - should this be DBA?
 			device_printf(dev,
 			    "Unable to allocate RX Descriptor memory\n");
 			error = ENOMEM;
 			goto fail;
 		}
 		rxr->base = (union i40e_rx_desc *)rxr->dma.va;
 		bzero((void *)rxr->base, rsize);
 
 		/* Allocate receive soft structs for the ring */
 		if (ixl_allocate_rx_data(que)) {
 			device_printf(dev,
 			    "Critical Failure setting up receive structs\n");
 			error = ENOMEM;
 			goto fail;
 		}
 	}
 
 	return (0);
 
 fail:
 	for (int i = 0; i < vsi->num_queues; i++) {
 		que = &vsi->queues[i];
 		rxr = &que->rxr;
 		txr = &que->txr;
 		if (rxr->base)
 			i40e_free_dma_mem(&sc->hw, &rxr->dma);
 		if (txr->base)
 			i40e_free_dma_mem(&sc->hw, &txr->dma);
 	}
 	free(vsi->queues, M_DEVBUF);
 
 early:
 	return (error);
 }
 
 /*
 ** This routine is run via an vlan config EVENT,
 ** it enables us to use the HW Filter table since
 ** we can get the vlan id. This just creates the
 ** entry in the soft version of the VFTA, init will
 ** repopulate the real table.
 */
 static void
 ixlv_register_vlan(void *arg, struct ifnet *ifp, u16 vtag)
 {
 	struct ixl_vsi		*vsi = arg;
 	struct ixlv_sc		*sc = vsi->back;
 	struct ixlv_vlan_filter	*v;
 
 
 	if (ifp->if_softc != arg)   /* Not our event */
 		return;
 
 	if ((vtag == 0) || (vtag > 4095))	/* Invalid */
 		return;
 
 	/* Sanity check - make sure it doesn't already exist */
 	SLIST_FOREACH(v, sc->vlan_filters, next) {
 		if (v->vlan == vtag)
 			return;
 	}
 
 	mtx_lock(&sc->mtx);
 	++vsi->num_vlans;
 	v = malloc(sizeof(struct ixlv_vlan_filter), M_DEVBUF, M_NOWAIT | M_ZERO);
 	SLIST_INSERT_HEAD(sc->vlan_filters, v, next);
 	v->vlan = vtag;
 	v->flags = IXL_FILTER_ADD;
 	ixl_vc_enqueue(&sc->vc_mgr, &sc->add_vlan_cmd,
 	    IXLV_FLAG_AQ_ADD_VLAN_FILTER, ixl_init_cmd_complete, sc);
 	mtx_unlock(&sc->mtx);
 	return;
 }
 
 /*
 ** This routine is run via an vlan
 ** unconfig EVENT, remove our entry
 ** in the soft vfta.
 */
 static void
 ixlv_unregister_vlan(void *arg, struct ifnet *ifp, u16 vtag)
 {
 	struct ixl_vsi		*vsi = arg;
 	struct ixlv_sc		*sc = vsi->back;
 	struct ixlv_vlan_filter	*v;
 	int			i = 0;
 	
 	if (ifp->if_softc != arg)
 		return;
 
 	if ((vtag == 0) || (vtag > 4095))	/* Invalid */
 		return;
 
 	mtx_lock(&sc->mtx);
 	SLIST_FOREACH(v, sc->vlan_filters, next) {
 		if (v->vlan == vtag) {
 			v->flags = IXL_FILTER_DEL;
 			++i;
 			--vsi->num_vlans;
 		}
 	}
 	if (i)
 		ixl_vc_enqueue(&sc->vc_mgr, &sc->del_vlan_cmd,
 		    IXLV_FLAG_AQ_DEL_VLAN_FILTER, ixl_init_cmd_complete, sc);
 	mtx_unlock(&sc->mtx);
 	return;
 }
 
 /*
 ** Get a new filter and add it to the mac filter list.
 */
 static struct ixlv_mac_filter *
 ixlv_get_mac_filter(struct ixlv_sc *sc)
 {
 	struct ixlv_mac_filter	*f;
 
 	f = malloc(sizeof(struct ixlv_mac_filter),
 	    M_DEVBUF, M_NOWAIT | M_ZERO);
 	if (f)
 		SLIST_INSERT_HEAD(sc->mac_filters, f, next);
 
 	return (f);
 }
 
 /*
 ** Find the filter with matching MAC address
 */
 static struct ixlv_mac_filter *
 ixlv_find_mac_filter(struct ixlv_sc *sc, u8 *macaddr)
 {
 	struct ixlv_mac_filter	*f;
 	bool				match = FALSE;
 
 	SLIST_FOREACH(f, sc->mac_filters, next) {
 		if (cmp_etheraddr(f->macaddr, macaddr)) {
 			match = TRUE;
 			break;
 		}
 	}	
 
 	if (!match)
 		f = NULL;
 	return (f);
 }
 
 static int
 ixlv_teardown_adminq_msix(struct ixlv_sc *sc)
 {
 	device_t		dev = sc->dev;
 	int			error = 0;
 
 	if (sc->tag != NULL) {
 		bus_teardown_intr(dev, sc->res, sc->tag);
 		if (error) {
 			device_printf(dev, "bus_teardown_intr() for"
 			    " interrupt 0 failed\n");
 			// return (ENXIO);
 		}
 		sc->tag = NULL;
 	}
 	if (sc->res != NULL) {
 		bus_release_resource(dev, SYS_RES_IRQ, 1, sc->res);
 		if (error) {
 			device_printf(dev, "bus_release_resource() for"
 			    " interrupt 0 failed\n");
 			// return (ENXIO);
 		}
 		sc->res = NULL;
 	}
 
 	return (0);
 
 }
 
 /*
 ** Admin Queue interrupt handler
 */
 static void
 ixlv_msix_adminq(void *arg)
 {
 	struct ixlv_sc	*sc = arg;
 	struct i40e_hw	*hw = &sc->hw;
 	u32		reg, mask;
 
         reg = rd32(hw, I40E_VFINT_ICR01);
         mask = rd32(hw, I40E_VFINT_ICR0_ENA1);
 
         reg = rd32(hw, I40E_VFINT_DYN_CTL01);
         reg |= I40E_VFINT_DYN_CTL01_CLEARPBA_MASK;
         wr32(hw, I40E_VFINT_DYN_CTL01, reg);
 
 	/* schedule task */
 	taskqueue_enqueue(sc->tq, &sc->aq_irq);
 	return;
 }
 
 void
 ixlv_enable_intr(struct ixl_vsi *vsi)
 {
 	struct i40e_hw		*hw = vsi->hw;
 	struct ixl_queue	*que = vsi->queues;
 
 	ixlv_enable_adminq_irq(hw);
 	for (int i = 0; i < vsi->num_queues; i++, que++)
 		ixlv_enable_queue_irq(hw, que->me);
 }
 
 void
 ixlv_disable_intr(struct ixl_vsi *vsi)
 {
         struct i40e_hw          *hw = vsi->hw;
         struct ixl_queue       *que = vsi->queues;
 
 	ixlv_disable_adminq_irq(hw);
 	for (int i = 0; i < vsi->num_queues; i++, que++)
 		ixlv_disable_queue_irq(hw, que->me);
 }
 
 
 static void
 ixlv_disable_adminq_irq(struct i40e_hw *hw)
 {
 	wr32(hw, I40E_VFINT_DYN_CTL01, 0);
 	wr32(hw, I40E_VFINT_ICR0_ENA1, 0);
 	/* flush */
 	rd32(hw, I40E_VFGEN_RSTAT);
 	return;
 }
 
 static void
 ixlv_enable_adminq_irq(struct i40e_hw *hw)
 {
 	wr32(hw, I40E_VFINT_DYN_CTL01,
 	    I40E_VFINT_DYN_CTL01_INTENA_MASK |
 	    I40E_VFINT_DYN_CTL01_ITR_INDX_MASK);
 	wr32(hw, I40E_VFINT_ICR0_ENA1, I40E_VFINT_ICR0_ENA1_ADMINQ_MASK);
 	/* flush */
 	rd32(hw, I40E_VFGEN_RSTAT);
 	return;
 }
 
 static void
 ixlv_enable_queue_irq(struct i40e_hw *hw, int id)
 {
 	u32		reg;
 
 	reg = I40E_VFINT_DYN_CTLN1_INTENA_MASK |
 	    I40E_VFINT_DYN_CTLN1_CLEARPBA_MASK |
 	    I40E_VFINT_DYN_CTLN1_ITR_INDX_MASK;
 	wr32(hw, I40E_VFINT_DYN_CTLN1(id), reg);
 }
 
 static void
 ixlv_disable_queue_irq(struct i40e_hw *hw, int id)
 {
 	wr32(hw, I40E_VFINT_DYN_CTLN1(id),
 	    I40E_VFINT_DYN_CTLN1_ITR_INDX_MASK);
 	rd32(hw, I40E_VFGEN_RSTAT);
 	return;
 }
 
 /*
  * Get initial ITR values from tunable values.
  */
 static void
 ixlv_configure_itr(struct ixlv_sc *sc)
 {
 	struct i40e_hw		*hw = &sc->hw;
 	struct ixl_vsi		*vsi = &sc->vsi;
 	struct ixl_queue	*que = vsi->queues;
 
 	vsi->rx_itr_setting = ixlv_rx_itr;
 	vsi->tx_itr_setting = ixlv_tx_itr;
 
 	for (int i = 0; i < vsi->num_queues; i++, que++) {
 		struct tx_ring	*txr = &que->txr;
 		struct rx_ring 	*rxr = &que->rxr;
 
 		wr32(hw, I40E_VFINT_ITRN1(IXL_RX_ITR, i),
 		    vsi->rx_itr_setting);
 		rxr->itr = vsi->rx_itr_setting;
 		rxr->latency = IXL_AVE_LATENCY;
 
 		wr32(hw, I40E_VFINT_ITRN1(IXL_TX_ITR, i),
 		    vsi->tx_itr_setting);
 		txr->itr = vsi->tx_itr_setting;
 		txr->latency = IXL_AVE_LATENCY;
 	}
 }
 
 /*
 ** Provide a update to the queue RX
 ** interrupt moderation value.
 */
 static void
 ixlv_set_queue_rx_itr(struct ixl_queue *que)
 {
 	struct ixl_vsi	*vsi = que->vsi;
 	struct i40e_hw	*hw = vsi->hw;
 	struct rx_ring	*rxr = &que->rxr;
 	u16		rx_itr;
 	u16		rx_latency = 0;
 	int		rx_bytes;
 
 
 	/* Idle, do nothing */
 	if (rxr->bytes == 0)
 		return;
 
 	if (ixlv_dynamic_rx_itr) {
 		rx_bytes = rxr->bytes/rxr->itr;
 		rx_itr = rxr->itr;
 
 		/* Adjust latency range */
 		switch (rxr->latency) {
 		case IXL_LOW_LATENCY:
 			if (rx_bytes > 10) {
 				rx_latency = IXL_AVE_LATENCY;
 				rx_itr = IXL_ITR_20K;
 			}
 			break;
 		case IXL_AVE_LATENCY:
 			if (rx_bytes > 20) {
 				rx_latency = IXL_BULK_LATENCY;
 				rx_itr = IXL_ITR_8K;
 			} else if (rx_bytes <= 10) {
 				rx_latency = IXL_LOW_LATENCY;
 				rx_itr = IXL_ITR_100K;
 			}
 			break;
 		case IXL_BULK_LATENCY:
 			if (rx_bytes <= 20) {
 				rx_latency = IXL_AVE_LATENCY;
 				rx_itr = IXL_ITR_20K;
 			}
 			break;
        		 }
 
 		rxr->latency = rx_latency;
 
 		if (rx_itr != rxr->itr) {
 			/* do an exponential smoothing */
 			rx_itr = (10 * rx_itr * rxr->itr) /
 			    ((9 * rx_itr) + rxr->itr);
 			rxr->itr = min(rx_itr, IXL_MAX_ITR);
 			wr32(hw, I40E_VFINT_ITRN1(IXL_RX_ITR,
 			    que->me), rxr->itr);
 		}
 	} else { /* We may have have toggled to non-dynamic */
 		if (vsi->rx_itr_setting & IXL_ITR_DYNAMIC)
 			vsi->rx_itr_setting = ixlv_rx_itr;
 		/* Update the hardware if needed */
 		if (rxr->itr != vsi->rx_itr_setting) {
 			rxr->itr = vsi->rx_itr_setting;
 			wr32(hw, I40E_VFINT_ITRN1(IXL_RX_ITR,
 			    que->me), rxr->itr);
 		}
 	}
 	rxr->bytes = 0;
 	rxr->packets = 0;
 	return;
 }
 
 
 /*
 ** Provide a update to the queue TX
 ** interrupt moderation value.
 */
 static void
 ixlv_set_queue_tx_itr(struct ixl_queue *que)
 {
 	struct ixl_vsi	*vsi = que->vsi;
 	struct i40e_hw	*hw = vsi->hw;
 	struct tx_ring	*txr = &que->txr;
 	u16		tx_itr;
 	u16		tx_latency = 0;
 	int		tx_bytes;
 
 
 	/* Idle, do nothing */
 	if (txr->bytes == 0)
 		return;
 
 	if (ixlv_dynamic_tx_itr) {
 		tx_bytes = txr->bytes/txr->itr;
 		tx_itr = txr->itr;
 
 		switch (txr->latency) {
 		case IXL_LOW_LATENCY:
 			if (tx_bytes > 10) {
 				tx_latency = IXL_AVE_LATENCY;
 				tx_itr = IXL_ITR_20K;
 			}
 			break;
 		case IXL_AVE_LATENCY:
 			if (tx_bytes > 20) {
 				tx_latency = IXL_BULK_LATENCY;
 				tx_itr = IXL_ITR_8K;
 			} else if (tx_bytes <= 10) {
 				tx_latency = IXL_LOW_LATENCY;
 				tx_itr = IXL_ITR_100K;
 			}
 			break;
 		case IXL_BULK_LATENCY:
 			if (tx_bytes <= 20) {
 				tx_latency = IXL_AVE_LATENCY;
 				tx_itr = IXL_ITR_20K;
 			}
 			break;
 		}
 
 		txr->latency = tx_latency;
 
 		if (tx_itr != txr->itr) {
        	         /* do an exponential smoothing */
 			tx_itr = (10 * tx_itr * txr->itr) /
 			    ((9 * tx_itr) + txr->itr);
 			txr->itr = min(tx_itr, IXL_MAX_ITR);
 			wr32(hw, I40E_VFINT_ITRN1(IXL_TX_ITR,
 			    que->me), txr->itr);
 		}
 
 	} else { /* We may have have toggled to non-dynamic */
 		if (vsi->tx_itr_setting & IXL_ITR_DYNAMIC)
 			vsi->tx_itr_setting = ixlv_tx_itr;
 		/* Update the hardware if needed */
 		if (txr->itr != vsi->tx_itr_setting) {
 			txr->itr = vsi->tx_itr_setting;
 			wr32(hw, I40E_VFINT_ITRN1(IXL_TX_ITR,
 			    que->me), txr->itr);
 		}
 	}
 	txr->bytes = 0;
 	txr->packets = 0;
 	return;
 }
 
 
 /*
 **
 ** MSIX Interrupt Handlers and Tasklets
 **
 */
 static void
 ixlv_handle_que(void *context, int pending)
 {
 	struct ixl_queue *que = context;
 	struct ixl_vsi *vsi = que->vsi;
 	struct i40e_hw  *hw = vsi->hw;
 	struct tx_ring  *txr = &que->txr;
 	struct ifnet    *ifp = vsi->ifp;
 	bool		more;
 
 	if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
 		more = ixl_rxeof(que, IXL_RX_LIMIT);
 		mtx_lock(&txr->mtx);
 		ixl_txeof(que);
 		if (!drbr_empty(ifp, txr->br))
 			ixl_mq_start_locked(ifp, txr);
 		mtx_unlock(&txr->mtx);
 		if (more) {
 			taskqueue_enqueue(que->tq, &que->task);
 			return;
 		}
 	}
 
 	/* Reenable this interrupt - hmmm */
 	ixlv_enable_queue_irq(hw, que->me);
 	return;
 }
 
 
 /*********************************************************************
  *
  *  MSIX Queue Interrupt Service routine
  *
  **********************************************************************/
 static void
 ixlv_msix_que(void *arg)
 {
 	struct ixl_queue	*que = arg;
 	struct ixl_vsi	*vsi = que->vsi;
 	struct i40e_hw	*hw = vsi->hw;
 	struct tx_ring	*txr = &que->txr;
 	bool		more_tx, more_rx;
 
 	/* Spurious interrupts are ignored */
 	if (!(vsi->ifp->if_drv_flags & IFF_DRV_RUNNING))
 		return;
 
 	++que->irqs;
 
 	more_rx = ixl_rxeof(que, IXL_RX_LIMIT);
 
 	mtx_lock(&txr->mtx);
 	more_tx = ixl_txeof(que);
 	/*
 	** Make certain that if the stack 
 	** has anything queued the task gets
 	** scheduled to handle it.
 	*/
 	if (!drbr_empty(vsi->ifp, txr->br))
 		more_tx = 1;
 	mtx_unlock(&txr->mtx);
 
 	ixlv_set_queue_rx_itr(que);
 	ixlv_set_queue_tx_itr(que);
 
 	if (more_tx || more_rx)
 		taskqueue_enqueue(que->tq, &que->task);
 	else
 		ixlv_enable_queue_irq(hw, que->me);
 
 	return;
 }
 
 
 /*********************************************************************
  *
  *  Media Ioctl callback
  *
  *  This routine is called whenever the user queries the status of
  *  the interface using ifconfig.
  *
  **********************************************************************/
 static void
 ixlv_media_status(struct ifnet * ifp, struct ifmediareq * ifmr)
 {
 	struct ixl_vsi		*vsi = ifp->if_softc;
 	struct ixlv_sc	*sc = vsi->back;
 
 	INIT_DBG_IF(ifp, "begin");
 
 	mtx_lock(&sc->mtx);
 
 	ixlv_update_link_status(sc);
 
 	ifmr->ifm_status = IFM_AVALID;
 	ifmr->ifm_active = IFM_ETHER;
 
 	if (!sc->link_up) {
 		mtx_unlock(&sc->mtx);
 		INIT_DBG_IF(ifp, "end: link not up");
 		return;
 	}
 
 	ifmr->ifm_status |= IFM_ACTIVE;
 	/* Hardware is always full-duplex */
 	ifmr->ifm_active |= IFM_FDX;
 	mtx_unlock(&sc->mtx);
 	INIT_DBG_IF(ifp, "end");
 	return;
 }
 
 /*********************************************************************
  *
  *  Media Ioctl callback
  *
  *  This routine is called when the user changes speed/duplex using
  *  media/mediopt option with ifconfig.
  *
  **********************************************************************/
 static int
 ixlv_media_change(struct ifnet * ifp)
 {
 	struct ixl_vsi *vsi = ifp->if_softc;
 	struct ifmedia *ifm = &vsi->media;
 
 	INIT_DBG_IF(ifp, "begin");
 
 	if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER)
 		return (EINVAL);
 
 	INIT_DBG_IF(ifp, "end");
 	return (0);
 }
 
 
 /*********************************************************************
  *  Multicast Initialization
  *
  *  This routine is called by init to reset a fresh state.
  *
  **********************************************************************/
 
 static void
 ixlv_init_multi(struct ixl_vsi *vsi)
 {
 	struct ixlv_mac_filter *f;
 	struct ixlv_sc	*sc = vsi->back;
 	int			mcnt = 0;
 
 	IOCTL_DBG_IF(vsi->ifp, "begin");
 
 	/* First clear any multicast filters */
 	SLIST_FOREACH(f, sc->mac_filters, next) {
 		if ((f->flags & IXL_FILTER_USED)
 		    && (f->flags & IXL_FILTER_MC)) {
 			f->flags |= IXL_FILTER_DEL;
 			mcnt++;
 		}
 	}
 	if (mcnt > 0)
 		ixl_vc_enqueue(&sc->vc_mgr, &sc->del_multi_cmd,
 		    IXLV_FLAG_AQ_DEL_MAC_FILTER, ixl_init_cmd_complete,
 		    sc);
 
 	IOCTL_DBG_IF(vsi->ifp, "end");
 }
 
 static void
 ixlv_add_multi(struct ixl_vsi *vsi)
 {
 	struct ifmultiaddr	*ifma;
 	struct ifnet		*ifp = vsi->ifp;
 	struct ixlv_sc	*sc = vsi->back;
 	int			mcnt = 0;
 
 	IOCTL_DBG_IF(ifp, "begin");
 
 	if_maddr_rlock(ifp);
 	/*
 	** Get a count, to decide if we
 	** simply use multicast promiscuous.
 	*/
 	TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
 		if (ifma->ifma_addr->sa_family != AF_LINK)
 			continue;
 		mcnt++;
 	}
 	if_maddr_runlock(ifp);
 
 	/* TODO: Remove -- cannot set promiscuous mode in a VF */
 	if (__predict_false(mcnt >= MAX_MULTICAST_ADDR)) {
 		/* delete all multicast filters */
 		ixlv_init_multi(vsi);
 		sc->promiscuous_flags |= I40E_FLAG_VF_MULTICAST_PROMISC;
 		ixl_vc_enqueue(&sc->vc_mgr, &sc->add_multi_cmd,
 		    IXLV_FLAG_AQ_CONFIGURE_PROMISC, ixl_init_cmd_complete,
 		    sc);
 		IOCTL_DEBUGOUT("%s: end: too many filters", __func__);
 		return;
 	}
 
 	mcnt = 0;
 	if_maddr_rlock(ifp);
 	TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
 		if (ifma->ifma_addr->sa_family != AF_LINK)
 			continue;
 		if (!ixlv_add_mac_filter(sc,
 		    (u8*)LLADDR((struct sockaddr_dl *) ifma->ifma_addr),
 		    IXL_FILTER_MC))
 			mcnt++;
 	}
 	if_maddr_runlock(ifp);
 	/*
 	** Notify AQ task that sw filters need to be
 	** added to hw list
 	*/
 	if (mcnt > 0)
 		ixl_vc_enqueue(&sc->vc_mgr, &sc->add_multi_cmd,
 		    IXLV_FLAG_AQ_ADD_MAC_FILTER, ixl_init_cmd_complete,
 		    sc);
 
 	IOCTL_DBG_IF(ifp, "end");
 }
 
 static void
 ixlv_del_multi(struct ixl_vsi *vsi)
 {
 	struct ixlv_mac_filter *f;
 	struct ifmultiaddr	*ifma;
 	struct ifnet		*ifp = vsi->ifp;
 	struct ixlv_sc	*sc = vsi->back;
 	int			mcnt = 0;
 	bool		match = FALSE;
 
 	IOCTL_DBG_IF(ifp, "begin");
 
 	/* Search for removed multicast addresses */
 	if_maddr_rlock(ifp);
 	SLIST_FOREACH(f, sc->mac_filters, next) {
 		if ((f->flags & IXL_FILTER_USED)
 		    && (f->flags & IXL_FILTER_MC)) {
 			/* check if mac address in filter is in sc's list */
 			match = FALSE;
 			TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
 				if (ifma->ifma_addr->sa_family != AF_LINK)
 					continue;
 				u8 *mc_addr =
 				    (u8 *)LLADDR((struct sockaddr_dl *)ifma->ifma_addr);
 				if (cmp_etheraddr(f->macaddr, mc_addr)) {
 					match = TRUE;
 					break;
 				}
 			}
 			/* if this filter is not in the sc's list, remove it */
 			if (match == FALSE && !(f->flags & IXL_FILTER_DEL)) {
 				f->flags |= IXL_FILTER_DEL;
 				mcnt++;
 				IOCTL_DBG_IF(ifp, "marked: " MAC_FORMAT,
 				    MAC_FORMAT_ARGS(f->macaddr));
 			}
 			else if (match == FALSE)
 				IOCTL_DBG_IF(ifp, "exists: " MAC_FORMAT,
 				    MAC_FORMAT_ARGS(f->macaddr));
 		}
 	}
 	if_maddr_runlock(ifp);
 
 	if (mcnt > 0)
 		ixl_vc_enqueue(&sc->vc_mgr, &sc->del_multi_cmd,
 		    IXLV_FLAG_AQ_DEL_MAC_FILTER, ixl_init_cmd_complete,
 		    sc);
 
 	IOCTL_DBG_IF(ifp, "end");
 }
 
 /*********************************************************************
  *  Timer routine
  *
  *  This routine checks for link status,updates statistics,
  *  and runs the watchdog check.
  *
  **********************************************************************/
 
 static void
 ixlv_local_timer(void *arg)
 {
 	struct ixlv_sc	*sc = arg;
 	struct i40e_hw		*hw = &sc->hw;
 	struct ixl_vsi		*vsi = &sc->vsi;
 	struct ixl_queue	*que = vsi->queues;
 	device_t		dev = sc->dev;
 	struct tx_ring		*txr;
 	int			hung = 0;
 	u32			mask, val;
 	s32			timer, new_timer;
 
 	IXLV_CORE_LOCK_ASSERT(sc);
 
 	/* If Reset is in progress just bail */
 	if (sc->init_state == IXLV_RESET_PENDING)
 		return;
 
 	/* Check for when PF triggers a VF reset */
 	val = rd32(hw, I40E_VFGEN_RSTAT) &
 	    I40E_VFGEN_RSTAT_VFR_STATE_MASK;
 
 	if (val != I40E_VFR_VFACTIVE
 	    && val != I40E_VFR_COMPLETED) {
 		DDPRINTF(dev, "reset in progress! (%d)", val);
 		return;
 	}
 
 	ixlv_request_stats(sc);
 
 	/* clean and process any events */
 	taskqueue_enqueue(sc->tq, &sc->aq_irq);
 
 	/*
 	** Check status on the queues for a hang
 	*/
 	mask = (I40E_VFINT_DYN_CTLN1_INTENA_MASK |
 	    I40E_VFINT_DYN_CTLN1_SWINT_TRIG_MASK |
 	    I40E_VFINT_DYN_CTLN1_ITR_INDX_MASK);
 
 	for (int i = 0; i < vsi->num_queues; i++, que++) {
 		txr = &que->txr;
 		timer = atomic_load_acq_32(&txr->watchdog_timer);
 		if (timer > 0) {
 			new_timer = timer - hz;
 			if (new_timer <= 0) {
 				atomic_store_rel_32(&txr->watchdog_timer, -1);
 				device_printf(dev, "WARNING: queue %d "
 				    "appears to be hung!\n", que->me);
 				++hung;
 			} else {
 				/*
 				 * If this fails, that means something in the TX path has updated
 				 * the watchdog, so it means the TX path is still working and
 				 * the watchdog doesn't need to countdown.
 				 */
 				atomic_cmpset_rel_32(&txr->watchdog_timer, timer, new_timer);
 				/* Any queues with outstanding work get a sw irq */
 				wr32(hw, I40E_VFINT_DYN_CTLN1(que->me), mask);
 			}
 		}
 	}
 	/* Reset when a queue shows hung */
 	if (hung)
 		goto hung;
 
 	callout_reset(&sc->timer, hz, ixlv_local_timer, sc);
 	return;
 
 hung:
 	device_printf(dev, "WARNING: Resetting!\n");
 	sc->init_state = IXLV_RESET_REQUIRED;
 	sc->watchdog_events++;
 	ixlv_stop(sc);
 	ixlv_init_locked(sc);
 }
 
 /*
 ** Note: this routine updates the OS on the link state
 **	the real check of the hardware only happens with
 **	a link interrupt.
 */
 void
 ixlv_update_link_status(struct ixlv_sc *sc)
 {
 	struct ixl_vsi		*vsi = &sc->vsi;
 	struct ifnet		*ifp = vsi->ifp;
 
 	if (sc->link_up){ 
 		if (vsi->link_active == FALSE) {
 			if (bootverbose)
 				if_printf(ifp,"Link is Up, %d Gbps\n",
 				    (sc->link_speed == I40E_LINK_SPEED_40GB) ? 40:10);
 			vsi->link_active = TRUE;
 			if_link_state_change(ifp, LINK_STATE_UP);
 		}
 	} else { /* Link down */
 		if (vsi->link_active == TRUE) {
 			if (bootverbose)
 				if_printf(ifp,"Link is Down\n");
 			if_link_state_change(ifp, LINK_STATE_DOWN);
 			vsi->link_active = FALSE;
 		}
 	}
 
 	return;
 }
 
 /*********************************************************************
  *
  *  This routine disables all traffic on the adapter by issuing a
  *  global reset on the MAC and deallocates TX/RX buffers.
  *
  **********************************************************************/
 
 static void
 ixlv_stop(struct ixlv_sc *sc)
 {
 	struct ifnet *ifp;
 	int start;
 
 	ifp = sc->vsi.ifp;
 	INIT_DBG_IF(ifp, "begin");
 
 	IXLV_CORE_LOCK_ASSERT(sc);
 
 	ixl_vc_flush(&sc->vc_mgr);
 	ixlv_disable_queues(sc);
 
 	start = ticks;
 	while ((ifp->if_drv_flags & IFF_DRV_RUNNING) &&
 	    ((ticks - start) < hz/10))
 		ixlv_do_adminq_locked(sc);
 
 	/* Stop the local timer */
 	callout_stop(&sc->timer);
 
 	INIT_DBG_IF(ifp, "end");
 }
 
 
 /*********************************************************************
  *
  *  Free all station queue structs.
  *
  **********************************************************************/
 static void
 ixlv_free_queues(struct ixl_vsi *vsi)
 {
 	struct ixlv_sc	*sc = (struct ixlv_sc *)vsi->back;
 	struct ixl_queue	*que = vsi->queues;
 
 	for (int i = 0; i < vsi->num_queues; i++, que++) {
 		struct tx_ring *txr = &que->txr;
 		struct rx_ring *rxr = &que->rxr;
 	
 		if (!mtx_initialized(&txr->mtx)) /* uninitialized */
 			continue;
 		IXL_TX_LOCK(txr);
 		ixl_free_que_tx(que);
 		if (txr->base)
 			i40e_free_dma_mem(&sc->hw, &txr->dma);
 		IXL_TX_UNLOCK(txr);
 		IXL_TX_LOCK_DESTROY(txr);
 
 		if (!mtx_initialized(&rxr->mtx)) /* uninitialized */
 			continue;
 		IXL_RX_LOCK(rxr);
 		ixl_free_que_rx(que);
 		if (rxr->base)
 			i40e_free_dma_mem(&sc->hw, &rxr->dma);
 		IXL_RX_UNLOCK(rxr);
 		IXL_RX_LOCK_DESTROY(rxr);
 		
 	}
 	free(vsi->queues, M_DEVBUF);
 }
 
 static void
 ixlv_config_rss_reg(struct ixlv_sc *sc)
 {
 	struct i40e_hw	*hw = &sc->hw;
 	struct ixl_vsi	*vsi = &sc->vsi;
 	u32		lut = 0;
 	u64		set_hena = 0, hena;
 	int		i, j, que_id;
 	u32		rss_seed[IXL_RSS_KEY_SIZE_REG];
 #ifdef RSS
 	u32		rss_hash_config;
 #endif
         
 	/* Don't set up RSS if using a single queue */
 	if (vsi->num_queues == 1) {
 		wr32(hw, I40E_VFQF_HENA(0), 0);
 		wr32(hw, I40E_VFQF_HENA(1), 0);
 		ixl_flush(hw);
 		return;
 	}
 
 #ifdef RSS
 	/* Fetch the configured RSS key */
 	rss_getkey((uint8_t *) &rss_seed);
 #else
 	ixl_get_default_rss_key(rss_seed);
 #endif
 
 	/* Fill out hash function seed */
 	for (i = 0; i < IXL_RSS_KEY_SIZE_REG; i++)
                 wr32(hw, I40E_VFQF_HKEY(i), rss_seed[i]);
 
 	/* Enable PCTYPES for RSS: */
 #ifdef RSS
 	rss_hash_config = rss_gethashconfig();
 	if (rss_hash_config & RSS_HASHTYPE_RSS_IPV4)
                 set_hena |= ((u64)1 << I40E_FILTER_PCTYPE_NONF_IPV4_OTHER);
 	if (rss_hash_config & RSS_HASHTYPE_RSS_TCP_IPV4)
                 set_hena |= ((u64)1 << I40E_FILTER_PCTYPE_NONF_IPV4_TCP);
 	if (rss_hash_config & RSS_HASHTYPE_RSS_UDP_IPV4)
                 set_hena |= ((u64)1 << I40E_FILTER_PCTYPE_NONF_IPV4_UDP);
 	if (rss_hash_config & RSS_HASHTYPE_RSS_IPV6)
                 set_hena |= ((u64)1 << I40E_FILTER_PCTYPE_NONF_IPV6_OTHER);
 	if (rss_hash_config & RSS_HASHTYPE_RSS_IPV6_EX)
 		set_hena |= ((u64)1 << I40E_FILTER_PCTYPE_FRAG_IPV6);
 	if (rss_hash_config & RSS_HASHTYPE_RSS_TCP_IPV6)
                 set_hena |= ((u64)1 << I40E_FILTER_PCTYPE_NONF_IPV6_TCP);
         if (rss_hash_config & RSS_HASHTYPE_RSS_UDP_IPV6)
                 set_hena |= ((u64)1 << I40E_FILTER_PCTYPE_NONF_IPV6_UDP);
 #else
 	set_hena = IXL_DEFAULT_RSS_HENA_XL710;
 #endif
 	hena = (u64)rd32(hw, I40E_VFQF_HENA(0)) |
 	    ((u64)rd32(hw, I40E_VFQF_HENA(1)) << 32);
 	hena |= set_hena;
 	wr32(hw, I40E_VFQF_HENA(0), (u32)hena);
 	wr32(hw, I40E_VFQF_HENA(1), (u32)(hena >> 32));
 
 	/* Populate the LUT with max no. of queues in round robin fashion */
 	for (i = 0, j = 0; i < IXL_RSS_VSI_LUT_SIZE; i++, j++) {
                 if (j == vsi->num_queues)
                         j = 0;
 #ifdef RSS
 		/*
 		 * Fetch the RSS bucket id for the given indirection entry.
 		 * Cap it at the number of configured buckets (which is
 		 * num_queues.)
 		 */
 		que_id = rss_get_indirection_to_bucket(i);
 		que_id = que_id % vsi->num_queues;
 #else
 		que_id = j;
 #endif
                 /* lut = 4-byte sliding window of 4 lut entries */
                 lut = (lut << 8) | (que_id & IXL_RSS_VF_LUT_ENTRY_MASK);
                 /* On i = 3, we have 4 entries in lut; write to the register */
                 if ((i & 3) == 3) {
                         wr32(hw, I40E_VFQF_HLUT(i >> 2), lut);
 			DDPRINTF(sc->dev, "HLUT(%2d): %#010x", i, lut);
 		}
         }
 	ixl_flush(hw);
 }
 
 static void
 ixlv_config_rss_pf(struct ixlv_sc *sc)
 {
 	ixl_vc_enqueue(&sc->vc_mgr, &sc->config_rss_key_cmd,
 	    IXLV_FLAG_AQ_CONFIG_RSS_KEY, ixl_init_cmd_complete, sc);
 
 	ixl_vc_enqueue(&sc->vc_mgr, &sc->set_rss_hena_cmd,
 	    IXLV_FLAG_AQ_SET_RSS_HENA, ixl_init_cmd_complete, sc);
 
 	ixl_vc_enqueue(&sc->vc_mgr, &sc->config_rss_lut_cmd,
 	    IXLV_FLAG_AQ_CONFIG_RSS_LUT, ixl_init_cmd_complete, sc);
 }
 
 /*
 ** ixlv_config_rss - setup RSS 
 **
 ** RSS keys and table are cleared on VF reset.
 */
 static void
 ixlv_config_rss(struct ixlv_sc *sc)
 {
 	if (sc->vf_res->vf_offload_flags & I40E_VIRTCHNL_VF_OFFLOAD_RSS_REG) {
 		DDPRINTF(sc->dev, "Setting up RSS using VF registers...");
 		ixlv_config_rss_reg(sc);
 	} else if (sc->vf_res->vf_offload_flags & I40E_VIRTCHNL_VF_OFFLOAD_RSS_PF) {
 		DDPRINTF(sc->dev, "Setting up RSS using messages to PF...");
 		ixlv_config_rss_pf(sc);
 	} else
 		device_printf(sc->dev, "VF does not support RSS capability sent by PF.\n");
 }
 
 /*
 ** This routine refreshes vlan filters, called by init
 ** it scans the filter table and then updates the AQ
 */
 static void
 ixlv_setup_vlan_filters(struct ixlv_sc *sc)
 {
 	struct ixl_vsi			*vsi = &sc->vsi;
 	struct ixlv_vlan_filter	*f;
 	int				cnt = 0;
 
 	if (vsi->num_vlans == 0)
 		return;
 	/*
 	** Scan the filter table for vlan entries,
 	** and if found call for the AQ update.
 	*/
 	SLIST_FOREACH(f, sc->vlan_filters, next)
                 if (f->flags & IXL_FILTER_ADD)
 			cnt++;
 	if (cnt > 0)
 		ixl_vc_enqueue(&sc->vc_mgr, &sc->add_vlan_cmd,
 		    IXLV_FLAG_AQ_ADD_VLAN_FILTER, ixl_init_cmd_complete, sc);
 }
 
 
 /*
 ** This routine adds new MAC filters to the sc's list;
 ** these are later added in hardware by sending a virtual
 ** channel message.
 */
 static int
 ixlv_add_mac_filter(struct ixlv_sc *sc, u8 *macaddr, u16 flags)
 {
 	struct ixlv_mac_filter	*f;
 
 	/* Does one already exist? */
 	f = ixlv_find_mac_filter(sc, macaddr);
 	if (f != NULL) {
 		IDPRINTF(sc->vsi.ifp, "exists: " MAC_FORMAT,
 		    MAC_FORMAT_ARGS(macaddr));
 		return (EEXIST);
 	}
 
 	/* If not, get a new empty filter */
 	f = ixlv_get_mac_filter(sc);
 	if (f == NULL) {
 		if_printf(sc->vsi.ifp, "%s: no filters available!!\n",
 		    __func__);
 		return (ENOMEM);
 	}
 
 	IDPRINTF(sc->vsi.ifp, "marked: " MAC_FORMAT,
 	    MAC_FORMAT_ARGS(macaddr));
 
 	bcopy(macaddr, f->macaddr, ETHER_ADDR_LEN);
 	f->flags |= (IXL_FILTER_ADD | IXL_FILTER_USED);
 	f->flags |= flags;
 	return (0);
 }
 
 /*
 ** Marks a MAC filter for deletion.
 */
 static int
 ixlv_del_mac_filter(struct ixlv_sc *sc, u8 *macaddr)
 {
 	struct ixlv_mac_filter	*f;
 
 	f = ixlv_find_mac_filter(sc, macaddr);
 	if (f == NULL)
 		return (ENOENT);
 
 	f->flags |= IXL_FILTER_DEL;
 	return (0);
 }
 
 /*
 ** Tasklet handler for MSIX Adminq interrupts
 **  - done outside interrupt context since it might sleep
 */
 static void
 ixlv_do_adminq(void *context, int pending)
 {
 	struct ixlv_sc		*sc = context;
 
 	mtx_lock(&sc->mtx);
 	ixlv_do_adminq_locked(sc);
 	mtx_unlock(&sc->mtx);
 	return;
 }
 
 static void
 ixlv_do_adminq_locked(struct ixlv_sc *sc)
 {
 	struct i40e_hw			*hw = &sc->hw;
 	struct i40e_arq_event_info	event;
 	struct i40e_virtchnl_msg	*v_msg;
 	device_t			dev = sc->dev;
 	u16				result = 0;
 	u32				reg, oldreg;
 	i40e_status			ret;
 	bool				aq_error = false;
 
 	IXLV_CORE_LOCK_ASSERT(sc);
 
 	event.buf_len = IXL_AQ_BUF_SZ;
         event.msg_buf = sc->aq_buffer;
 	v_msg = (struct i40e_virtchnl_msg *)&event.desc;
 
 	do {
 		ret = i40e_clean_arq_element(hw, &event, &result);
 		if (ret)
 			break;
 		ixlv_vc_completion(sc, v_msg->v_opcode,
 		    v_msg->v_retval, event.msg_buf, event.msg_len);
 		if (result != 0)
 			bzero(event.msg_buf, IXL_AQ_BUF_SZ);
 	} while (result);
 
 	/* check for Admin queue errors */
 	oldreg = reg = rd32(hw, hw->aq.arq.len);
 	if (reg & I40E_VF_ARQLEN1_ARQVFE_MASK) {
 		device_printf(dev, "ARQ VF Error detected\n");
 		reg &= ~I40E_VF_ARQLEN1_ARQVFE_MASK;
 		aq_error = true;
 	}
 	if (reg & I40E_VF_ARQLEN1_ARQOVFL_MASK) {
 		device_printf(dev, "ARQ Overflow Error detected\n");
 		reg &= ~I40E_VF_ARQLEN1_ARQOVFL_MASK;
 		aq_error = true;
 	}
 	if (reg & I40E_VF_ARQLEN1_ARQCRIT_MASK) {
 		device_printf(dev, "ARQ Critical Error detected\n");
 		reg &= ~I40E_VF_ARQLEN1_ARQCRIT_MASK;
 		aq_error = true;
 	}
 	if (oldreg != reg)
 		wr32(hw, hw->aq.arq.len, reg);
 
 	oldreg = reg = rd32(hw, hw->aq.asq.len);
 	if (reg & I40E_VF_ATQLEN1_ATQVFE_MASK) {
 		device_printf(dev, "ASQ VF Error detected\n");
 		reg &= ~I40E_VF_ATQLEN1_ATQVFE_MASK;
 		aq_error = true;
 	}
 	if (reg & I40E_VF_ATQLEN1_ATQOVFL_MASK) {
 		device_printf(dev, "ASQ Overflow Error detected\n");
 		reg &= ~I40E_VF_ATQLEN1_ATQOVFL_MASK;
 		aq_error = true;
 	}
 	if (reg & I40E_VF_ATQLEN1_ATQCRIT_MASK) {
 		device_printf(dev, "ASQ Critical Error detected\n");
 		reg &= ~I40E_VF_ATQLEN1_ATQCRIT_MASK;
 		aq_error = true;
 	}
 	if (oldreg != reg)
 		wr32(hw, hw->aq.asq.len, reg);
 
 	if (aq_error) {
 		/* Need to reset adapter */
 		device_printf(dev, "WARNING: Resetting!\n");
 		sc->init_state = IXLV_RESET_REQUIRED;
 		ixlv_stop(sc);
 		ixlv_init_locked(sc);
 	}
 	ixlv_enable_adminq_irq(hw);
 }
 
 static void
 ixlv_add_sysctls(struct ixlv_sc *sc)
 {
 	device_t dev = sc->dev;
 	struct ixl_vsi *vsi = &sc->vsi;
 	struct i40e_eth_stats *es = &vsi->eth_stats;
 
 	struct sysctl_ctx_list *ctx = device_get_sysctl_ctx(dev);
 	struct sysctl_oid *tree = device_get_sysctl_tree(dev);
 	struct sysctl_oid_list *child = SYSCTL_CHILDREN(tree);
 
 	struct sysctl_oid *vsi_node, *queue_node;
 	struct sysctl_oid_list *vsi_list, *queue_list;
 
 #define QUEUE_NAME_LEN 32
 	char queue_namebuf[QUEUE_NAME_LEN];
 
 	struct ixl_queue *queues = vsi->queues;
 	struct tx_ring *txr;
 	struct rx_ring *rxr;
 
 	/* Driver statistics sysctls */
 	SYSCTL_ADD_ULONG(ctx, child, OID_AUTO, "watchdog_events",
 			CTLFLAG_RD, &sc->watchdog_events,
 			"Watchdog timeouts");
 	SYSCTL_ADD_ULONG(ctx, child, OID_AUTO, "admin_irq",
 			CTLFLAG_RD, &sc->admin_irq,
 			"Admin Queue IRQ Handled");
 
 	/* VSI statistics sysctls */
 	vsi_node = SYSCTL_ADD_NODE(ctx, child, OID_AUTO, "vsi",
 				   CTLFLAG_RD, NULL, "VSI-specific statistics");
 	vsi_list = SYSCTL_CHILDREN(vsi_node);
 
 	struct ixl_sysctl_info ctls[] =
 	{
 		{&es->rx_bytes, "good_octets_rcvd", "Good Octets Received"},
 		{&es->rx_unicast, "ucast_pkts_rcvd",
 			"Unicast Packets Received"},
 		{&es->rx_multicast, "mcast_pkts_rcvd",
 			"Multicast Packets Received"},
 		{&es->rx_broadcast, "bcast_pkts_rcvd",
 			"Broadcast Packets Received"},
 		{&es->rx_discards, "rx_discards", "Discarded RX packets"},
 		{&es->rx_unknown_protocol, "rx_unknown_proto", "RX unknown protocol packets"},
 		{&es->tx_bytes, "good_octets_txd", "Good Octets Transmitted"},
 		{&es->tx_unicast, "ucast_pkts_txd", "Unicast Packets Transmitted"},
 		{&es->tx_multicast, "mcast_pkts_txd",
 			"Multicast Packets Transmitted"},
 		{&es->tx_broadcast, "bcast_pkts_txd",
 			"Broadcast Packets Transmitted"},
 		{&es->tx_errors, "tx_errors", "TX packet errors"},
 		// end
 		{0,0,0}
 	};
 	struct ixl_sysctl_info *entry = ctls;
 	while (entry->stat != NULL)
 	{
 		SYSCTL_ADD_QUAD(ctx, child, OID_AUTO, entry->name,
 				CTLFLAG_RD, entry->stat,
 				entry->description);
 		entry++;
 	}
 
 	/* Queue sysctls */
 	for (int q = 0; q < vsi->num_queues; q++) {
 		snprintf(queue_namebuf, QUEUE_NAME_LEN, "que%d", q);
 		queue_node = SYSCTL_ADD_NODE(ctx, vsi_list, OID_AUTO, queue_namebuf,
 					     CTLFLAG_RD, NULL, "Queue Name");
 		queue_list = SYSCTL_CHILDREN(queue_node);
 
 		txr = &(queues[q].txr);
 		rxr = &(queues[q].rxr);
 
 		SYSCTL_ADD_QUAD(ctx, queue_list, OID_AUTO, "mbuf_defrag_failed",
 				CTLFLAG_RD, &(queues[q].mbuf_defrag_failed),
 				"m_defrag() failed");
 		SYSCTL_ADD_QUAD(ctx, queue_list, OID_AUTO, "dropped",
 				CTLFLAG_RD, &(queues[q].dropped_pkts),
 				"Driver dropped packets");
 		SYSCTL_ADD_QUAD(ctx, queue_list, OID_AUTO, "irqs",
 				CTLFLAG_RD, &(queues[q].irqs),
 				"irqs on this queue");
 		SYSCTL_ADD_QUAD(ctx, queue_list, OID_AUTO, "tso_tx",
 				CTLFLAG_RD, &(queues[q].tso),
 				"TSO");
 		SYSCTL_ADD_QUAD(ctx, queue_list, OID_AUTO, "tx_dmamap_failed",
 				CTLFLAG_RD, &(queues[q].tx_dmamap_failed),
 				"Driver tx dma failure in xmit");
 		SYSCTL_ADD_QUAD(ctx, queue_list, OID_AUTO, "no_desc_avail",
 				CTLFLAG_RD, &(txr->no_desc),
 				"Queue No Descriptor Available");
 		SYSCTL_ADD_QUAD(ctx, queue_list, OID_AUTO, "tx_packets",
 				CTLFLAG_RD, &(txr->total_packets),
 				"Queue Packets Transmitted");
 		SYSCTL_ADD_QUAD(ctx, queue_list, OID_AUTO, "tx_bytes",
 				CTLFLAG_RD, &(txr->tx_bytes),
 				"Queue Bytes Transmitted");
 		SYSCTL_ADD_QUAD(ctx, queue_list, OID_AUTO, "rx_packets",
 				CTLFLAG_RD, &(rxr->rx_packets),
 				"Queue Packets Received");
 		SYSCTL_ADD_QUAD(ctx, queue_list, OID_AUTO, "rx_bytes",
 				CTLFLAG_RD, &(rxr->rx_bytes),
 				"Queue Bytes Received");
 		SYSCTL_ADD_UINT(ctx, queue_list, OID_AUTO, "rx_itr",
 				CTLFLAG_RD, &(rxr->itr), 0,
 				"Queue Rx ITR Interval");
 		SYSCTL_ADD_UINT(ctx, queue_list, OID_AUTO, "tx_itr",
 				CTLFLAG_RD, &(txr->itr), 0,
 				"Queue Tx ITR Interval");
 
 #ifdef IXL_DEBUG
 		/* Examine queue state */
 		SYSCTL_ADD_PROC(ctx, queue_list, OID_AUTO, "qtx_head", 
 				CTLTYPE_UINT | CTLFLAG_RD, &queues[q],
 				sizeof(struct ixl_queue),
 				ixlv_sysctl_qtx_tail_handler, "IU",
 				"Queue Transmit Descriptor Tail");
 		SYSCTL_ADD_PROC(ctx, queue_list, OID_AUTO, "qrx_head", 
 				CTLTYPE_UINT | CTLFLAG_RD, &queues[q],
 				sizeof(struct ixl_queue),
 				ixlv_sysctl_qrx_tail_handler, "IU",
 				"Queue Receive Descriptor Tail");
 		SYSCTL_ADD_INT(ctx, queue_list, OID_AUTO, "watchdog_timer",
 				CTLFLAG_RD, &(txr.watchdog_timer), 0,
 				"Ticks before watchdog event is triggered");
 #endif
 	}
 }
 
 static void
 ixlv_init_filters(struct ixlv_sc *sc)
 {
 	sc->mac_filters = malloc(sizeof(struct ixlv_mac_filter),
 	    M_DEVBUF, M_NOWAIT | M_ZERO);
 	SLIST_INIT(sc->mac_filters);
 	sc->vlan_filters = malloc(sizeof(struct ixlv_vlan_filter),
 	    M_DEVBUF, M_NOWAIT | M_ZERO);
 	SLIST_INIT(sc->vlan_filters);
 	return;
 }
 
 static void
 ixlv_free_filters(struct ixlv_sc *sc)
 {
 	struct ixlv_mac_filter *f;
 	struct ixlv_vlan_filter *v;
 
 	while (!SLIST_EMPTY(sc->mac_filters)) {
 		f = SLIST_FIRST(sc->mac_filters);
 		SLIST_REMOVE_HEAD(sc->mac_filters, next);
 		free(f, M_DEVBUF);
 	}
 	while (!SLIST_EMPTY(sc->vlan_filters)) {
 		v = SLIST_FIRST(sc->vlan_filters);
 		SLIST_REMOVE_HEAD(sc->vlan_filters, next);
 		free(v, M_DEVBUF);
 	}
 	return;
 }
 
 #ifdef IXL_DEBUG
 /**
  * ixlv_sysctl_qtx_tail_handler
  * Retrieves I40E_QTX_TAIL1 value from hardware
  * for a sysctl.
  */
 static int 
 ixlv_sysctl_qtx_tail_handler(SYSCTL_HANDLER_ARGS)
 {
 	struct ixl_queue *que;
 	int error;
 	u32 val;
 
 	que = ((struct ixl_queue *)oidp->oid_arg1);
 	if (!que) return 0;
 
 	val = rd32(que->vsi->hw, que->txr.tail);
 	error = sysctl_handle_int(oidp, &val, 0, req);
 	if (error || !req->newptr)
 		return error;
 	return (0);
 }
 
 /**
  * ixlv_sysctl_qrx_tail_handler
  * Retrieves I40E_QRX_TAIL1 value from hardware
  * for a sysctl.
  */
 static int 
 ixlv_sysctl_qrx_tail_handler(SYSCTL_HANDLER_ARGS)
 {
 	struct ixl_queue *que;
 	int error;
 	u32 val;
 
 	que = ((struct ixl_queue *)oidp->oid_arg1);
 	if (!que) return 0;
 
 	val = rd32(que->vsi->hw, que->rxr.tail);
 	error = sysctl_handle_int(oidp, &val, 0, req);
 	if (error || !req->newptr)
 		return error;
 	return (0);
 }
 #endif
 
Index: head/sys/dev/ixl/ixl.h
===================================================================
--- head/sys/dev/ixl/ixl.h	(revision 320976)
+++ head/sys/dev/ixl/ixl.h	(revision 320977)
@@ -1,693 +1,692 @@
 /******************************************************************************
 
   Copyright (c) 2013-2015, Intel Corporation 
   All rights reserved.
   
   Redistribution and use in source and binary forms, with or without 
   modification, are permitted provided that the following conditions are met:
   
    1. Redistributions of source code must retain the above copyright notice, 
       this list of conditions and the following disclaimer.
   
    2. Redistributions in binary form must reproduce the above copyright 
       notice, this list of conditions and the following disclaimer in the 
       documentation and/or other materials provided with the distribution.
   
    3. Neither the name of the Intel Corporation nor the names of its 
       contributors may be used to endorse or promote products derived from 
       this software without specific prior written permission.
   
   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 
   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 
   ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 
   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 
   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 
   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 
   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 
   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 
   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
   POSSIBILITY OF SUCH DAMAGE.
 
 ******************************************************************************/
 /*$FreeBSD$*/
 
 
 #ifndef _IXL_H_
 #define _IXL_H_
 
 #include "opt_inet.h"
 #include "opt_inet6.h"
 #include "opt_rss.h"
 #include "opt_ixl.h"
 
 #include <sys/param.h>
 #include <sys/systm.h>
 #include <sys/buf_ring.h>
 #include <sys/mbuf.h>
 #include <sys/protosw.h>
 #include <sys/socket.h>
 #include <sys/malloc.h>
 #include <sys/kernel.h>
 #include <sys/module.h>
 #include <sys/sockio.h>
 #include <sys/eventhandler.h>
 #include <sys/syslog.h>
 
 #include <net/if.h>
 #include <net/if_var.h>
 #include <net/if_arp.h>
 #include <net/bpf.h>
 #include <net/ethernet.h>
 #include <net/if_dl.h>
 #include <net/if_media.h>
 
 #include <net/bpf.h>
 #include <net/if_types.h>
 #include <net/if_vlan_var.h>
 
 #include <netinet/in_systm.h>
 #include <netinet/in.h>
 #include <netinet/if_ether.h>
 #include <netinet/ip.h>
 #include <netinet/ip6.h>
 #include <netinet/tcp.h>
 #include <netinet/tcp_lro.h>
 #include <netinet/udp.h>
 #include <netinet/sctp.h>
 
 #include <machine/in_cksum.h>
 
 #include <sys/bus.h>
 #include <machine/bus.h>
 #include <sys/rman.h>
 #include <machine/resource.h>
 #include <vm/vm.h>
 #include <vm/pmap.h>
 #include <machine/clock.h>
 #include <dev/pci/pcivar.h>
 #include <dev/pci/pcireg.h>
 #include <sys/proc.h>
 #include <sys/sysctl.h>
 #include <sys/endian.h>
 #include <sys/taskqueue.h>
 #include <sys/pcpu.h>
 #include <sys/smp.h>
 #include <sys/sbuf.h>
 #include <machine/smp.h>
 #include <machine/stdarg.h>
 
 #ifdef RSS
 #include <net/rss_config.h>
 #include <netinet/in_rss.h>
 #endif
 
 #include "i40e_type.h"
 #include "i40e_prototype.h"
 
 #define MAC_FORMAT "%02x:%02x:%02x:%02x:%02x:%02x"
 #define MAC_FORMAT_ARGS(mac_addr) \
 	(mac_addr)[0], (mac_addr)[1], (mac_addr)[2], (mac_addr)[3], \
 	(mac_addr)[4], (mac_addr)[5]
 #define ON_OFF_STR(is_set) ((is_set) ? "On" : "Off")
 
 #ifdef IXL_DEBUG
 
 #define _DBG_PRINTF(S, ...)		printf("%s: " S "\n", __func__, ##__VA_ARGS__)
 #define _DEV_DBG_PRINTF(dev, S, ...)	device_printf(dev, "%s: " S "\n", __func__, ##__VA_ARGS__)
 #define _IF_DBG_PRINTF(ifp, S, ...)	if_printf(ifp, "%s: " S "\n", __func__, ##__VA_ARGS__)
 
 /* Defines for printing generic debug information */
 #define DPRINTF(...)			_DBG_PRINTF(__VA_ARGS__)
 #define DDPRINTF(...)			_DEV_DBG_PRINTF(__VA_ARGS__)
 #define IDPRINTF(...)			_IF_DBG_PRINTF(__VA_ARGS__)
 
 /* Defines for printing specific debug information */
 #define DEBUG_INIT  1
 #define DEBUG_IOCTL 1
 #define DEBUG_HW    1
 
 #define INIT_DEBUGOUT(...)		if (DEBUG_INIT) _DBG_PRINTF(__VA_ARGS__)
 #define INIT_DBG_DEV(...)		if (DEBUG_INIT) _DEV_DBG_PRINTF(__VA_ARGS__)
 #define INIT_DBG_IF(...)		if (DEBUG_INIT) _IF_DBG_PRINTF(__VA_ARGS__)
 
 #define IOCTL_DEBUGOUT(...)		if (DEBUG_IOCTL) _DBG_PRINTF(__VA_ARGS__)
 #define IOCTL_DBG_IF2(ifp, S, ...)	if (DEBUG_IOCTL) \
 					    if_printf(ifp, S "\n", ##__VA_ARGS__)
 #define IOCTL_DBG_IF(...)		if (DEBUG_IOCTL) _IF_DBG_PRINTF(__VA_ARGS__)
 
 #define HW_DEBUGOUT(...)		if (DEBUG_HW) _DBG_PRINTF(__VA_ARGS__)
 
 #else /* no IXL_DEBUG */
 #define DEBUG_INIT  0
 #define DEBUG_IOCTL 0
 #define DEBUG_HW    0
 
 #define DPRINTF(...)
 #define DDPRINTF(...)
 #define IDPRINTF(...)
 
 #define INIT_DEBUGOUT(...)
 #define INIT_DBG_DEV(...)
 #define INIT_DBG_IF(...)
 #define IOCTL_DEBUGOUT(...)
 #define IOCTL_DBG_IF2(...)
 #define IOCTL_DBG_IF(...)
 #define HW_DEBUGOUT(...)
 #endif /* IXL_DEBUG */
 
 enum ixl_dbg_mask {
 	IXL_DBG_INFO			= 0x00000001,
 	IXL_DBG_EN_DIS			= 0x00000002,
 	IXL_DBG_AQ			= 0x00000004,
 	IXL_DBG_NVMUPD			= 0x00000008,
 
 	IXL_DBG_IOCTL_KNOWN		= 0x00000010,
 	IXL_DBG_IOCTL_UNKNOWN		= 0x00000020,
 	IXL_DBG_IOCTL_ALL		= 0x00000030,
 
 	I40E_DEBUG_RSS			= 0x00000100,
 
 	IXL_DBG_IOV			= 0x00001000,
 	IXL_DBG_IOV_VC			= 0x00002000,
 
 	IXL_DBG_SWITCH_INFO		= 0x00010000,
 	IXL_DBG_I2C			= 0x00020000,
 
 	IXL_DBG_ALL			= 0xFFFFFFFF
 };
 
 /* Tunables */
 
 /*
  * Ring Descriptors Valid Range: 32-4096 Default Value: 1024 This value is the
  * number of tx/rx descriptors allocated by the driver. Increasing this
  * value allows the driver to queue more operations.
  *
  * Tx descriptors are always 16 bytes, but Rx descriptors can be 32 bytes.
  * The driver currently always uses 32 byte Rx descriptors.
  */
 #define IXL_DEFAULT_RING	1024
 #define IXL_MAX_RING		8160
 #define IXL_MIN_RING		32
 #define IXL_RING_INCREMENT	32
 
 #define IXL_AQ_LEN		256
 #define IXL_AQ_LEN_MAX		1024
 
 /*
 ** Default number of entries in Tx queue buf_ring.
 */
 #define DEFAULT_TXBRSZ		4096
 
 /* Alignment for rings */
 #define DBA_ALIGN		128
 
 /*
  * This is the max watchdog interval, ie. the time that can
  * pass between any two TX clean operations, such only happening
  * when the TX hardware is functioning.
  */
 #define IXL_WATCHDOG		(10 * hz)
 
 /*
  * This parameters control when the driver calls the routine to reclaim
  * transmit descriptors.
  */
 #define IXL_TX_CLEANUP_THRESHOLD	(que->num_desc / 8)
 #define IXL_TX_OP_THRESHOLD		(que->num_desc / 32)
 
 #define MAX_MULTICAST_ADDR	128
 
 #define IXL_MSIX_BAR		3
 #define IXL_ADM_LIMIT		2
 #define IXL_TSO_SIZE		65535
 #define IXL_AQ_BUF_SZ		((u32) 4096)
 #define IXL_RX_HDR		128
 #define IXL_RX_LIMIT		512
 #define IXL_RX_ITR		0
 #define IXL_TX_ITR		1
 #define IXL_ITR_NONE		3
 #define IXL_QUEUE_EOL		0x7FF
 #define IXL_MAX_FRAME		9728
 #define IXL_MAX_TX_SEGS		8
 #define IXL_MAX_TSO_SEGS	128
 #define IXL_SPARSE_CHAIN	6
 #define IXL_QUEUE_HUNG		0x80000000
 #define IXL_MIN_TSO_MSS		64
 
 #define IXL_RSS_KEY_SIZE_REG		13
 #define IXL_RSS_KEY_SIZE		(IXL_RSS_KEY_SIZE_REG * 4)
 #define IXL_RSS_VSI_LUT_SIZE		64	/* X722 -> VSI, X710 -> VF */
 #define IXL_RSS_VSI_LUT_ENTRY_MASK	0x3F
 #define IXL_RSS_VF_LUT_ENTRY_MASK	0xF
 
 #define IXL_VF_MAX_BUFFER	0x3F80
 #define IXL_VF_MAX_HDR_BUFFER	0x840
 #define IXL_VF_MAX_FRAME	0x3FFF
 
 /* ERJ: hardware can support ~2k (SW5+) filters between all functions */
 #define IXL_MAX_FILTERS		256
 #define IXL_MAX_TX_BUSY		10
 
 #define IXL_NVM_VERSION_LO_SHIFT	0
 #define IXL_NVM_VERSION_LO_MASK		(0xff << IXL_NVM_VERSION_LO_SHIFT)
 #define IXL_NVM_VERSION_HI_SHIFT	12
 #define IXL_NVM_VERSION_HI_MASK		(0xf << IXL_NVM_VERSION_HI_SHIFT)
 
 /*
  * Interrupt Moderation parameters
  * Multiply ITR values by 2 for real ITR value
  */
 #define IXL_MAX_ITR		0x0FF0
 #define IXL_ITR_100K		0x0005
 #define IXL_ITR_20K		0x0019
 #define IXL_ITR_8K		0x003E
 #define IXL_ITR_4K		0x007A
 #define IXL_ITR_1K		0x01F4
 #define IXL_ITR_DYNAMIC		0x8000
 #define IXL_LOW_LATENCY		0
 #define IXL_AVE_LATENCY		1
 #define IXL_BULK_LATENCY	2
 
 /* MacVlan Flags */
 #define IXL_FILTER_USED		(u16)(1 << 0)
 #define IXL_FILTER_VLAN		(u16)(1 << 1)
 #define IXL_FILTER_ADD		(u16)(1 << 2)
 #define IXL_FILTER_DEL		(u16)(1 << 3)
 #define IXL_FILTER_MC		(u16)(1 << 4)
 
 /* used in the vlan field of the filter when not a vlan */
 #define IXL_VLAN_ANY		-1
 
 #define CSUM_OFFLOAD_IPV4	(CSUM_IP|CSUM_TCP|CSUM_UDP|CSUM_SCTP)
 #define CSUM_OFFLOAD_IPV6	(CSUM_TCP_IPV6|CSUM_UDP_IPV6|CSUM_SCTP_IPV6)
 #define CSUM_OFFLOAD		(CSUM_OFFLOAD_IPV4|CSUM_OFFLOAD_IPV6|CSUM_TSO)
 
 /* Misc flags for ixl_vsi.flags */
 #define IXL_FLAGS_KEEP_TSO4	(1 << 0)
 #define IXL_FLAGS_KEEP_TSO6	(1 << 1)
 
 #define IXL_VF_RESET_TIMEOUT	100
 
 #define IXL_VSI_DATA_PORT	0x01
 
 #define IXLV_MAX_QUEUES		16
 #define IXL_MAX_VSI_QUEUES	(2 * (I40E_VSILAN_QTABLE_MAX_INDEX + 1))
 
 #define IXL_RX_CTX_BASE_UNITS	128
 #define IXL_TX_CTX_BASE_UNITS	128
 
 #define IXL_VPINT_LNKLSTN_REG(hw, vector, vf_num) \
 	I40E_VPINT_LNKLSTN(((vector) - 1) + \
 	    (((hw)->func_caps.num_msix_vectors_vf - 1) * (vf_num)))
 
 #define IXL_VFINT_DYN_CTLN_REG(hw, vector, vf_num) \
 	I40E_VFINT_DYN_CTLN(((vector) - 1) + \
 	    (((hw)->func_caps.num_msix_vectors_vf - 1) * (vf_num)))
 
 #define IXL_PF_PCI_CIAA_VF_DEVICE_STATUS	0xAA
 
 #define IXL_PF_PCI_CIAD_VF_TRANS_PENDING_MASK	0x20
 
 #define IXL_GLGEN_VFLRSTAT_INDEX(glb_vf)	((glb_vf) / 32)
 #define IXL_GLGEN_VFLRSTAT_MASK(glb_vf)	(1 << ((glb_vf) % 32))
 
 #define IXL_MAX_ITR_IDX		3
 
 #define IXL_END_OF_INTR_LNKLST	0x7FF
 
 #define IXL_DEFAULT_RSS_HENA_BASE (\
 	BIT_ULL(I40E_FILTER_PCTYPE_NONF_IPV4_UDP) |	\
 	BIT_ULL(I40E_FILTER_PCTYPE_NONF_IPV4_TCP) |	\
 	BIT_ULL(I40E_FILTER_PCTYPE_NONF_IPV4_SCTP) |	\
 	BIT_ULL(I40E_FILTER_PCTYPE_NONF_IPV4_OTHER) |	\
 	BIT_ULL(I40E_FILTER_PCTYPE_FRAG_IPV4) |		\
 	BIT_ULL(I40E_FILTER_PCTYPE_NONF_IPV6_UDP) |	\
 	BIT_ULL(I40E_FILTER_PCTYPE_NONF_IPV6_TCP) |	\
 	BIT_ULL(I40E_FILTER_PCTYPE_NONF_IPV6_SCTP) |	\
 	BIT_ULL(I40E_FILTER_PCTYPE_NONF_IPV6_OTHER) |	\
 	BIT_ULL(I40E_FILTER_PCTYPE_FRAG_IPV6) |		\
 	BIT_ULL(I40E_FILTER_PCTYPE_L2_PAYLOAD))
 
 #define IXL_DEFAULT_RSS_HENA_XL710	IXL_DEFAULT_RSS_HENA_BASE
 
 #define IXL_DEFAULT_RSS_HENA_X722 (\
 	IXL_DEFAULT_RSS_HENA_BASE |			\
 	BIT_ULL(I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP) | \
 	BIT_ULL(I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP) | \
 	BIT_ULL(I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP) | \
 	BIT_ULL(I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP) | \
 	BIT_ULL(I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK) | \
 	BIT_ULL(I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK))
 
 #define IXL_TX_LOCK(_sc)                mtx_lock(&(_sc)->mtx)
 #define IXL_TX_UNLOCK(_sc)              mtx_unlock(&(_sc)->mtx)
 #define IXL_TX_LOCK_DESTROY(_sc)        mtx_destroy(&(_sc)->mtx)
 #define IXL_TX_TRYLOCK(_sc)             mtx_trylock(&(_sc)->mtx)
 #define IXL_TX_LOCK_ASSERT(_sc)         mtx_assert(&(_sc)->mtx, MA_OWNED)
 
 #define IXL_RX_LOCK(_sc)                mtx_lock(&(_sc)->mtx)
 #define IXL_RX_UNLOCK(_sc)              mtx_unlock(&(_sc)->mtx)
 #define IXL_RX_LOCK_DESTROY(_sc)        mtx_destroy(&(_sc)->mtx)
 
 /* Pre-11 counter(9) compatibility */
 #if __FreeBSD_version >= 1100036
 #define IXL_SET_IPACKETS(vsi, count)	(vsi)->ipackets = (count)
 #define IXL_SET_IERRORS(vsi, count)	(vsi)->ierrors = (count)
 #define IXL_SET_OPACKETS(vsi, count)	(vsi)->opackets = (count)
 #define IXL_SET_OERRORS(vsi, count)	(vsi)->oerrors = (count)
 #define IXL_SET_COLLISIONS(vsi, count)	/* Do nothing; collisions is always 0. */
 #define IXL_SET_IBYTES(vsi, count)	(vsi)->ibytes = (count)
 #define IXL_SET_OBYTES(vsi, count)	(vsi)->obytes = (count)
 #define IXL_SET_IMCASTS(vsi, count)	(vsi)->imcasts = (count)
 #define IXL_SET_OMCASTS(vsi, count)	(vsi)->omcasts = (count)
 #define IXL_SET_IQDROPS(vsi, count)	(vsi)->iqdrops = (count)
 #define IXL_SET_OQDROPS(vsi, count)	(vsi)->oqdrops = (count)
 #define IXL_SET_NOPROTO(vsi, count)	(vsi)->noproto = (count)
 #else
 #define IXL_SET_IPACKETS(vsi, count)	(vsi)->ifp->if_ipackets = (count)
 #define IXL_SET_IERRORS(vsi, count)	(vsi)->ifp->if_ierrors = (count)
 #define IXL_SET_OPACKETS(vsi, count)	(vsi)->ifp->if_opackets = (count)
 #define IXL_SET_OERRORS(vsi, count)	(vsi)->ifp->if_oerrors = (count)
 #define IXL_SET_COLLISIONS(vsi, count)	(vsi)->ifp->if_collisions = (count)
 #define IXL_SET_IBYTES(vsi, count)	(vsi)->ifp->if_ibytes = (count)
 #define IXL_SET_OBYTES(vsi, count)	(vsi)->ifp->if_obytes = (count)
 #define IXL_SET_IMCASTS(vsi, count)	(vsi)->ifp->if_imcasts = (count)
 #define IXL_SET_OMCASTS(vsi, count)	(vsi)->ifp->if_omcasts = (count)
 #define IXL_SET_IQDROPS(vsi, count)	(vsi)->ifp->if_iqdrops = (count)
 #define IXL_SET_OQDROPS(vsi, odrops)	(vsi)->ifp->if_snd.ifq_drops = (odrops)
 #define IXL_SET_NOPROTO(vsi, count)	(vsi)->noproto = (count)
 #endif
 
 /*
  *****************************************************************************
  * vendor_info_array
  * 
  * This array contains the list of Subvendor/Subdevice IDs on which the driver
  * should load.
  * 
  *****************************************************************************
  */
 typedef struct _ixl_vendor_info_t {
 	unsigned int    vendor_id;
 	unsigned int    device_id;
 	unsigned int    subvendor_id;
 	unsigned int    subdevice_id;
 	unsigned int    index;
 } ixl_vendor_info_t;
 
 
 struct ixl_tx_buf {
 	u32		eop_index;
 	struct mbuf	*m_head;
 	bus_dmamap_t	map;
 	bus_dma_tag_t	tag;
 };
 
 struct ixl_rx_buf {
 	struct mbuf	*m_head;
 	struct mbuf	*m_pack;
 	struct mbuf	*fmp;
 	bus_dmamap_t	hmap;
 	bus_dmamap_t	pmap;
 };
 
 /*
 ** This struct has multiple uses, multicast
 ** addresses, vlans, and mac filters all use it.
 */
 struct ixl_mac_filter {
 	SLIST_ENTRY(ixl_mac_filter) next;
 	u8	macaddr[ETHER_ADDR_LEN];
 	s16	vlan;
 	u16	flags;
 };
 
 /*
  * The Transmit ring control struct
  */
 struct tx_ring {
         struct ixl_queue	*que;
 	struct mtx		mtx;
 	u32			tail;
 	struct i40e_tx_desc	*base;
 	struct i40e_dma_mem	dma;
 	u16			next_avail;
 	u16			next_to_clean;
 	u16			atr_rate;
 	u16			atr_count;
 	u32			itr;
 	u32			latency;
 	struct ixl_tx_buf	*buffers;
 	volatile u16		avail;
 	u32			cmd;
 	bus_dma_tag_t		tx_tag;
 	bus_dma_tag_t		tso_tag;
 	char			mtx_name[16];
 	struct buf_ring		*br;
 	s32			watchdog_timer;
 
 	/* Used for Dynamic ITR calculation */
 	u32			packets;
 	u32 			bytes;
 
 	/* Soft Stats */
 	u64			tx_bytes;
 	u64			no_desc;
 	u64			total_packets;
 };
 
 
 /*
  * The Receive ring control struct
  */
 struct rx_ring {
         struct ixl_queue	*que;
 	struct mtx		mtx;
 	union i40e_rx_desc	*base;
 	struct i40e_dma_mem	dma;
 	struct lro_ctrl		lro;
 	bool			lro_enabled;
 	bool			hdr_split;
 	bool			discard;
         u32			next_refresh;
         u32 			next_check;
 	u32			itr;
 	u32			latency;
 	char			mtx_name[16];
 	struct ixl_rx_buf	*buffers;
 	u32			mbuf_sz;
 	u32			tail;
 	bus_dma_tag_t		htag;
 	bus_dma_tag_t		ptag;
 
 	/* Used for Dynamic ITR calculation */
 	u32			packets;
 	u32 			bytes;
 
 	/* Soft stats */
 	u64			split;
 	u64			rx_packets;
 	u64 			rx_bytes;
 	u64 			desc_errs;
 	u64 			not_done;
 };
 
 /*
 ** Driver queue struct: this is the interrupt container
 **  for the associated tx and rx ring pair.
 */
 struct ixl_queue {
 	struct ixl_vsi		*vsi;
 	u32			me;
 	u32			msix;           /* This queue's MSIX vector */
 	u32			eims;           /* This queue's EIMS bit */
 	struct resource		*res;
 	void			*tag;
 	int			num_desc;	/* both tx and rx */
 	struct tx_ring		txr;
 	struct rx_ring		rxr;
 	struct task		task;
 	struct task		tx_task;
 	struct taskqueue	*tq;
 
 	/* Queue stats */
 	u64			irqs;
 	u64			tso;
 	u64			mbuf_defrag_failed;
 	u64			mbuf_hdr_failed;
 	u64			mbuf_pkt_failed;
 	u64			tx_dmamap_failed;
 	u64			dropped_pkts;
 	u64			mss_too_small;
 };
 
 /*
 ** Virtual Station Interface
 */
 SLIST_HEAD(ixl_ftl_head, ixl_mac_filter);
 struct ixl_vsi {
 	void 			*back;
 	struct ifnet		*ifp;
 	device_t		dev;
 	struct i40e_hw		*hw;
 	struct ifmedia		media;
 	enum i40e_vsi_type	type;
 	int			id;
 	u16			num_queues;
 	u32			rx_itr_setting;
 	u32			tx_itr_setting;
 	u16			max_frame_size;
 
 	struct ixl_queue	*queues;	/* head of queues */
 
 	u16			vsi_num;
 	bool			link_active;
 	u16			seid;
 	u16			uplink_seid;
 	u16			downlink_seid;
 
 	/* MAC/VLAN Filter list */
 	struct ixl_ftl_head	ftl;
 	u16			num_macs;
 
 	/* Contains readylist & stat counter id */
 	struct i40e_aqc_vsi_properties_data info;
 
 	eventhandler_tag 	vlan_attach;
 	eventhandler_tag 	vlan_detach;
 	u16			num_vlans;
 
 	/* Per-VSI stats from hardware */
 	struct i40e_eth_stats	eth_stats;
 	struct i40e_eth_stats	eth_stats_offsets;
 	bool 			stat_offsets_loaded;
 	/* VSI stat counters */
 	u64			ipackets;
 	u64			ierrors;
 	u64			opackets;
 	u64			oerrors;
 	u64			ibytes;
 	u64			obytes;
 	u64			imcasts;
 	u64			omcasts;
 	u64			iqdrops;
 	u64			oqdrops;
 	u64			noproto;
 
 	/* Driver statistics */
 	u64			hw_filters_del;
 	u64			hw_filters_add;
 
 	/* Misc. */
 	u64 			flags;
 	struct sysctl_oid	*vsi_node;
 };
 
 /*
 ** Find the number of unrefreshed RX descriptors
 */
 static inline u16
 ixl_rx_unrefreshed(struct ixl_queue *que)
 {       
         struct rx_ring	*rxr = &que->rxr;
         
 	if (rxr->next_check > rxr->next_refresh)
 		return (rxr->next_check - rxr->next_refresh - 1);
 	else
 		return ((que->num_desc + rxr->next_check) -
 		    rxr->next_refresh - 1);
 }
 
 /*
 ** Find the next available unused filter
 */
 static inline struct ixl_mac_filter *
 ixl_get_filter(struct ixl_vsi *vsi)
 {
 	struct ixl_mac_filter  *f;
 
 	/* create a new empty filter */
 	f = malloc(sizeof(struct ixl_mac_filter),
 	    M_DEVBUF, M_NOWAIT | M_ZERO);
 	if (f)
 		SLIST_INSERT_HEAD(&vsi->ftl, f, next);
 
 	return (f);
 }
 
 /*
 ** Compare two ethernet addresses
 */
 static inline bool
 cmp_etheraddr(const u8 *ea1, const u8 *ea2)
 {       
 	bool cmp = FALSE;
 
 	if ((ea1[0] == ea2[0]) && (ea1[1] == ea2[1]) &&
 	    (ea1[2] == ea2[2]) && (ea1[3] == ea2[3]) &&
 	    (ea1[4] == ea2[4]) && (ea1[5] == ea2[5])) 
 		cmp = TRUE;
 
 	return (cmp);
 }       
 
 /*
  * Return next largest power of 2, unsigned
  *
  * Public domain, from Bit Twiddling Hacks
  */
 static inline u32
 next_power_of_two(u32 n)
 {
 	n--;
 	n |= n >> 1;
 	n |= n >> 2;
 	n |= n >> 4;
 	n |= n >> 8;
 	n |= n >> 16;
 	n++;
 
 	/* Next power of two > 0 is 1 */
 	n += (n == 0);
 
 	return (n);
 }
 
 /*
  * Info for stats sysctls
  */
 struct ixl_sysctl_info {
 	u64	*stat;
 	char	*name;
 	char	*description;
 };
 
-static uint8_t ixl_bcast_addr[ETHER_ADDR_LEN] =
-    {0xff, 0xff, 0xff, 0xff, 0xff, 0xff};
+extern const uint8_t ixl_bcast_addr[ETHER_ADDR_LEN];
 
 /*********************************************************************
  *  TXRX Function prototypes
  *********************************************************************/
 int	ixl_allocate_tx_data(struct ixl_queue *);
 int	ixl_allocate_rx_data(struct ixl_queue *);
 void	ixl_init_tx_ring(struct ixl_queue *);
 int	ixl_init_rx_ring(struct ixl_queue *);
 bool	ixl_rxeof(struct ixl_queue *, int);
 bool	ixl_txeof(struct ixl_queue *);
 void	ixl_free_que_tx(struct ixl_queue *);
 void	ixl_free_que_rx(struct ixl_queue *);
 
 int	ixl_mq_start(struct ifnet *, struct mbuf *);
 int	ixl_mq_start_locked(struct ifnet *, struct tx_ring *);
 void	ixl_deferred_mq_start(void *, int);
 void	ixl_free_vsi(struct ixl_vsi *);
 void	ixl_qflush(struct ifnet *);
 
 /* Common function prototypes between PF/VF driver */
 #if __FreeBSD_version >= 1100000
 uint64_t ixl_get_counter(if_t ifp, ift_counter cnt);
 #endif
 void	ixl_get_default_rss_key(u32 *);
 #endif /* _IXL_H_ */
Index: head/sys/dev/ixl/ixl_pf.h
===================================================================
--- head/sys/dev/ixl/ixl_pf.h	(revision 320976)
+++ head/sys/dev/ixl/ixl_pf.h	(revision 320977)
@@ -1,349 +1,342 @@
 /******************************************************************************
 
   Copyright (c) 2013-2015, Intel Corporation 
   All rights reserved.
   
   Redistribution and use in source and binary forms, with or without 
   modification, are permitted provided that the following conditions are met:
   
    1. Redistributions of source code must retain the above copyright notice, 
       this list of conditions and the following disclaimer.
   
    2. Redistributions in binary form must reproduce the above copyright 
       notice, this list of conditions and the following disclaimer in the 
       documentation and/or other materials provided with the distribution.
   
    3. Neither the name of the Intel Corporation nor the names of its 
       contributors may be used to endorse or promote products derived from 
       this software without specific prior written permission.
   
   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 
   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 
   ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 
   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 
   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 
   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 
   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 
   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 
   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
   POSSIBILITY OF SUCH DAMAGE.
 
 ******************************************************************************/
 /*$FreeBSD$*/
 
 
 #ifndef _IXL_PF_H_
 #define _IXL_PF_H_
 
 #include "ixl.h"
 #include "ixl_pf_qmgr.h"
 
 #define	VF_FLAG_ENABLED			0x01
 #define	VF_FLAG_SET_MAC_CAP		0x02
 #define	VF_FLAG_VLAN_CAP		0x04
 #define	VF_FLAG_PROMISC_CAP		0x08
 #define	VF_FLAG_MAC_ANTI_SPOOF		0x10
 
 #define IXL_PF_STATE_EMPR_RESETTING	(1 << 0)
 
 struct ixl_vf {
 	struct ixl_vsi		vsi;
 	uint32_t		vf_flags;
 
 	uint8_t			mac[ETHER_ADDR_LEN];
 	uint16_t		vf_num;
 	uint32_t		version;
 
 	struct ixl_pf_qtag	qtag;
 	struct sysctl_ctx_list	ctx;
 };
 
 /* Physical controller structure */
 struct ixl_pf {
 	struct i40e_hw		hw;
 	struct i40e_osdep	osdep;
 	device_t		dev;
 	struct ixl_vsi		vsi;
 
 	struct resource		*pci_mem;
 	struct resource		*msix_mem;
 
 	/*
 	 * Interrupt resources: this set is
 	 * either used for legacy, or for Link
 	 * when doing MSIX
 	 */
 	void			*tag;
 	struct resource 	*res;
 
 	struct callout		timer;
 	int			msix;
 #ifdef IXL_IW
 	int			iw_msix;
 	bool			iw_enabled;
 #endif
 	int			if_flags;
 	int			state;
 	bool			init_in_progress;
 	u8			supported_speeds;
 
 	struct ixl_pf_qmgr	qmgr;
 	struct ixl_pf_qtag	qtag;
 
 	/* Tunable values */
 	bool			enable_msix;
 	int			max_queues;
 	int			ringsz;
 	bool			enable_tx_fc_filter;
 	int			dynamic_rx_itr;
 	int			dynamic_tx_itr;
 	int			tx_itr;
 	int			rx_itr;
 
 	struct mtx		pf_mtx;
 
 	u32			qbase;
 	u32 			admvec;
 	struct task     	adminq;
 	struct taskqueue	*tq;
 
 	bool			link_up;
 	u32			link_speed;
 	int			advertised_speed;
 	int			fc; /* link flow ctrl setting */
 	enum ixl_dbg_mask	dbg_mask;
 	bool			has_i2c;
 
 	/* Misc stats maintained by the driver */
 	u64			watchdog_events;
 	u64			admin_irq;
 
 	/* Statistics from hw */
 	struct i40e_hw_port_stats 	stats;
 	struct i40e_hw_port_stats	stats_offsets;
 	bool 				stat_offsets_loaded;
 
 	/* SR-IOV */
 	struct ixl_vf		*vfs;
 	int			num_vfs;
 	uint16_t		veb_seid;
 	struct task		vflr_task;
 	int			vc_debug_lvl;
 };
 
 /*
  * Defines used for NVM update ioctls.
  * This value is used in the Solaris tool, too.
  */
 #define I40E_NVM_ACCESS \
      (((((((('E' << 4) + '1') << 4) + 'K') << 4) + 'G') << 4) | 5)
 
 #define IXL_DEFAULT_PHY_INT_MASK \
      ((~(I40E_AQ_EVENT_LINK_UPDOWN | I40E_AQ_EVENT_MODULE_QUAL_FAIL \
       | I40E_AQ_EVENT_MEDIA_NA)) & 0x3FF)
 
 /*** Sysctl help messages; displayed with "sysctl -d" ***/
 
 #define IXL_SYSCTL_HELP_SET_ADVERTISE	\
 "\nControl advertised link speed.\n"	\
 "Flags:\n"				\
 "\t 0x1 - advertise 100M\n"		\
 "\t 0x2 - advertise 1G\n"		\
 "\t 0x4 - advertise 10G\n"		\
 "\t 0x8 - advertise 20G\n"		\
 "\t0x10 - advertise 25G\n"		\
 "\t0x20 - advertise 40G\n\n"		\
 "Set to 0 to disable link.\n"		\
 "Use \"sysctl -x\" to view flags properly."
 
 #define IXL_SYSCTL_HELP_FC				\
 "\nSet flow control mode using the values below.\n" 	\
 "\t0 - off\n" 						\
 "\t1 - rx pause\n" 					\
 "\t2 - tx pause\n"					\
 "\t3 - tx and rx pause"
 
 #define IXL_SYSCTL_HELP_LINK_STATUS					\
 "\nExecutes a \"Get Link Status\" command on the Admin Queue, and displays" \
 " the response."			\
 
-static char *ixl_fc_string[6] = {
-	"None",
-	"Rx",
-	"Tx",
-	"Full",
-	"Priority",
-	"Default"
-};
+extern const char * const ixl_fc_string[6];
 
-static MALLOC_DEFINE(M_IXL, "ixl", "ixl driver allocations");
+MALLOC_DECLARE(M_IXL);
 
 /*** Functions / Macros ***/
 /* Adjust the level here to 10 or over to print stats messages */
 #define	I40E_VC_DEBUG(p, level, ...)				\
 	do {							\
 		if (level < 10)					\
 			ixl_dbg(p, IXL_DBG_IOV_VC, ##__VA_ARGS__); \
 	} while (0)
 
 #define	i40e_send_vf_nack(pf, vf, op, st) \
 	ixl_send_vf_nack_msg((pf), (vf), (op), (st), __FILE__, __LINE__)
 
 #define IXL_PF_LOCK_INIT(_sc, _name) \
         mtx_init(&(_sc)->pf_mtx, _name, "IXL PF Lock", MTX_DEF)
 #define IXL_PF_LOCK(_sc)              mtx_lock(&(_sc)->pf_mtx)
 #define IXL_PF_UNLOCK(_sc)            mtx_unlock(&(_sc)->pf_mtx)
 #define IXL_PF_LOCK_DESTROY(_sc)      mtx_destroy(&(_sc)->pf_mtx)
 #define IXL_PF_LOCK_ASSERT(_sc)       mtx_assert(&(_sc)->pf_mtx, MA_OWNED)
 
 /* Debug printing */
 #define ixl_dbg(p, m, s, ...)	ixl_debug_core(p, m, s, ##__VA_ARGS__)
 void	ixl_debug_core(struct ixl_pf *, enum ixl_dbg_mask, char *, ...);
 
 /* For stats sysctl naming */
 #define QUEUE_NAME_LEN 32
 
 /* For netmap(4) compatibility */
 #define ixl_disable_intr(vsi)	ixl_disable_rings_intr(vsi)
 
 /*
  * PF-only function declarations
  */
 
 void	ixl_set_busmaster(device_t);
 void	ixl_set_msix_enable(device_t);
 int	ixl_setup_interface(device_t, struct ixl_vsi *);
 void	ixl_print_nvm_cmd(device_t, struct i40e_nvm_access *);
 char *	ixl_aq_speed_to_str(enum i40e_aq_link_speed);
 
 void	ixl_handle_que(void *context, int pending);
 
 void	ixl_init(void *);
 void	ixl_local_timer(void *);
 void	ixl_register_vlan(void *, struct ifnet *, u16);
 void	ixl_unregister_vlan(void *, struct ifnet *, u16);
 void	ixl_intr(void *);
 void	ixl_msix_que(void *);
 void	ixl_msix_adminq(void *);
 void	ixl_do_adminq(void *, int);
 
 int	ixl_res_alloc_cmp(const void *, const void *);
 char *	ixl_switch_res_type_string(u8);
 char *	ixl_switch_element_string(struct sbuf *,
 	    struct i40e_aqc_switch_config_element_resp *);
 void	ixl_add_sysctls_mac_stats(struct sysctl_ctx_list *,
 		    struct sysctl_oid_list *, struct i40e_hw_port_stats *);
 void	ixl_add_sysctls_eth_stats(struct sysctl_ctx_list *,
 		    struct sysctl_oid_list *,
 		    struct i40e_eth_stats *);
 
 void    ixl_media_status(struct ifnet *, struct ifmediareq *);
 int     ixl_media_change(struct ifnet *);
 int     ixl_ioctl(struct ifnet *, u_long, caddr_t);
 
 void	ixl_enable_queue(struct i40e_hw *, int);
 void	ixl_disable_queue(struct i40e_hw *, int);
 void	ixl_enable_intr0(struct i40e_hw *);
 void	ixl_disable_intr0(struct i40e_hw *);
 void	ixl_nvm_version_str(struct i40e_hw *hw, struct sbuf *buf);
 void	ixl_stat_update48(struct i40e_hw *, u32, u32, bool,
 		    u64 *, u64 *);
 void	ixl_stat_update32(struct i40e_hw *, u32, bool,
 		    u64 *, u64 *);
 
 void	ixl_stop(struct ixl_pf *);
 void	ixl_add_vsi_sysctls(struct ixl_pf *pf, struct ixl_vsi *vsi, struct sysctl_ctx_list *ctx, const char *sysctl_name);
 int	ixl_get_hw_capabilities(struct ixl_pf *);
 void	ixl_link_up_msg(struct ixl_pf *);
 void    ixl_update_link_status(struct ixl_pf *);
 int     ixl_allocate_pci_resources(struct ixl_pf *);
 int	ixl_setup_stations(struct ixl_pf *);
 int	ixl_switch_config(struct ixl_pf *);
 void	ixl_stop_locked(struct ixl_pf *);
 int	ixl_teardown_hw_structs(struct ixl_pf *);
 int	ixl_reset(struct ixl_pf *);
 void	ixl_init_locked(struct ixl_pf *);
 void	ixl_set_rss_key(struct ixl_pf *);
 void	ixl_set_rss_pctypes(struct ixl_pf *);
 void	ixl_set_rss_hlut(struct ixl_pf *);
 int	ixl_setup_adminq_msix(struct ixl_pf *);
 int	ixl_setup_adminq_tq(struct ixl_pf *);
 int	ixl_teardown_adminq_msix(struct ixl_pf *);
 void	ixl_configure_intr0_msix(struct ixl_pf *);
 void	ixl_configure_queue_intr_msix(struct ixl_pf *);
 void	ixl_free_adminq_tq(struct ixl_pf *);
 int	ixl_setup_legacy(struct ixl_pf *);
 int	ixl_init_msix(struct ixl_pf *);
 void	ixl_configure_itr(struct ixl_pf *);
 void	ixl_configure_legacy(struct ixl_pf *);
 void	ixl_free_pci_resources(struct ixl_pf *);
 void	ixl_link_event(struct ixl_pf *, struct i40e_arq_event_info *);
 void	ixl_config_rss(struct ixl_pf *);
 int	ixl_set_advertised_speeds(struct ixl_pf *, int);
 void	ixl_get_initial_advertised_speeds(struct ixl_pf *);
 void	ixl_print_nvm_version(struct ixl_pf *pf);
 void	ixl_add_device_sysctls(struct ixl_pf *);
 void	ixl_handle_mdd_event(struct ixl_pf *);
 void	ixl_add_hw_stats(struct ixl_pf *);
 void	ixl_update_stats_counters(struct ixl_pf *);
 void	ixl_pf_reset_stats(struct ixl_pf *);
 void	ixl_get_bus_info(struct ixl_pf *pf);
 int	ixl_aq_get_link_status(struct ixl_pf *,
     struct i40e_aqc_get_link_status *);
 
 int	ixl_handle_nvmupd_cmd(struct ixl_pf *, struct ifdrv *);
 void	ixl_handle_empr_reset(struct ixl_pf *);
 int	ixl_rebuild_hw_structs_after_reset(struct ixl_pf *);
 
 void	ixl_set_queue_rx_itr(struct ixl_queue *);
 void	ixl_set_queue_tx_itr(struct ixl_queue *);
 
-void	ixl_add_filter(struct ixl_vsi *, u8 *, s16 vlan);
-void	ixl_del_filter(struct ixl_vsi *, u8 *, s16 vlan);
+void	ixl_add_filter(struct ixl_vsi *, const u8 *, s16 vlan);
+void	ixl_del_filter(struct ixl_vsi *, const u8 *, s16 vlan);
 void	ixl_reconfigure_filters(struct ixl_vsi *vsi);
 
 int	ixl_disable_rings(struct ixl_vsi *);
 int	ixl_disable_tx_ring(struct ixl_pf *, struct ixl_pf_qtag *, u16);
 int	ixl_disable_rx_ring(struct ixl_pf *, struct ixl_pf_qtag *, u16);
 int	ixl_disable_ring(struct ixl_pf *pf, struct ixl_pf_qtag *, u16);
 
 int	ixl_enable_rings(struct ixl_vsi *);
 int	ixl_enable_tx_ring(struct ixl_pf *, struct ixl_pf_qtag *, u16);
 int	ixl_enable_rx_ring(struct ixl_pf *, struct ixl_pf_qtag *, u16);
 int	ixl_enable_ring(struct ixl_pf *pf, struct ixl_pf_qtag *, u16);
 
 void	ixl_update_eth_stats(struct ixl_vsi *);
 void	ixl_cap_txcsum_tso(struct ixl_vsi *, struct ifnet *, int);
 int	ixl_initialize_vsi(struct ixl_vsi *);
 void	ixl_add_ifmedia(struct ixl_vsi *, u64);
 int	ixl_setup_queue_msix(struct ixl_vsi *);
 int	ixl_setup_queue_tqs(struct ixl_vsi *);
 int	ixl_teardown_queue_msix(struct ixl_vsi *);
 void	ixl_free_queue_tqs(struct ixl_vsi *);
 void	ixl_enable_intr(struct ixl_vsi *);
 void	ixl_disable_rings_intr(struct ixl_vsi *);
 void	ixl_set_promisc(struct ixl_vsi *);
 void	ixl_add_multi(struct ixl_vsi *);
 void	ixl_del_multi(struct ixl_vsi *);
 void	ixl_setup_vlan_filters(struct ixl_vsi *);
 void	ixl_init_filters(struct ixl_vsi *);
 void	ixl_add_hw_filters(struct ixl_vsi *, int, int);
 void	ixl_del_hw_filters(struct ixl_vsi *, int);
 struct ixl_mac_filter *
-		ixl_find_filter(struct ixl_vsi *, u8 *, s16);
+		ixl_find_filter(struct ixl_vsi *, const u8 *, s16);
 void	ixl_add_mc_filter(struct ixl_vsi *, u8 *);
 void	ixl_free_mac_filters(struct ixl_vsi *vsi);
 void	ixl_update_vsi_stats(struct ixl_vsi *);
 void	ixl_vsi_reset_stats(struct ixl_vsi *);
 
 /*
  * I2C Function prototypes
  */
 int	ixl_find_i2c_interface(struct ixl_pf *);
 s32	ixl_read_i2c_byte(struct ixl_pf *pf, u8 byte_offset,
 	    u8 dev_addr, u8 *data);
 s32	ixl_write_i2c_byte(struct ixl_pf *pf, u8 byte_offset,
 	    u8 dev_addr, u8 data);
 
 #endif /* _IXL_PF_H_ */
Index: head/sys/dev/ixl/ixl_pf_main.c
===================================================================
--- head/sys/dev/ixl/ixl_pf_main.c	(revision 320976)
+++ head/sys/dev/ixl/ixl_pf_main.c	(revision 320977)
@@ -1,6076 +1,6090 @@
 /******************************************************************************
 
   Copyright (c) 2013-2015, Intel Corporation 
   All rights reserved.
   
   Redistribution and use in source and binary forms, with or without 
   modification, are permitted provided that the following conditions are met:
   
    1. Redistributions of source code must retain the above copyright notice, 
       this list of conditions and the following disclaimer.
   
    2. Redistributions in binary form must reproduce the above copyright 
       notice, this list of conditions and the following disclaimer in the 
       documentation and/or other materials provided with the distribution.
   
    3. Neither the name of the Intel Corporation nor the names of its 
       contributors may be used to endorse or promote products derived from 
       this software without specific prior written permission.
   
   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 
   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 
   ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 
   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 
   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 
   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 
   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 
   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 
   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
   POSSIBILITY OF SUCH DAMAGE.
 
 ******************************************************************************/
 /*$FreeBSD$*/
 
 
 #include "ixl_pf.h"
 
 #ifdef PCI_IOV
 #include "ixl_pf_iov.h"
 #endif
 
 #ifdef IXL_IW
 #include "ixl_iw.h"
 #include "ixl_iw_int.h"
 #endif
 
 #ifdef DEV_NETMAP
 #include <net/netmap.h>
 #include <sys/selinfo.h>
 #include <dev/netmap/netmap_kern.h>
 #endif /* DEV_NETMAP */
 
 static int	ixl_setup_queue(struct ixl_queue *, struct ixl_pf *, int);
 static u64	ixl_max_aq_speed_to_value(u8);
 static u8	ixl_convert_sysctl_aq_link_speed(u8, bool);
 
 /* Sysctls */
 static int	ixl_set_flowcntl(SYSCTL_HANDLER_ARGS);
 static int	ixl_set_advertise(SYSCTL_HANDLER_ARGS);
 static int	ixl_current_speed(SYSCTL_HANDLER_ARGS);
 static int	ixl_sysctl_show_fw(SYSCTL_HANDLER_ARGS);
 static int	ixl_sysctl_unallocated_queues(SYSCTL_HANDLER_ARGS);
 static int	ixl_sysctl_pf_tx_itr(SYSCTL_HANDLER_ARGS);
 static int	ixl_sysctl_pf_rx_itr(SYSCTL_HANDLER_ARGS);
 
 /* Debug Sysctls */
 static int 	ixl_sysctl_link_status(SYSCTL_HANDLER_ARGS);
 static int	ixl_sysctl_phy_abilities(SYSCTL_HANDLER_ARGS);
 static int	ixl_sysctl_sw_filter_list(SYSCTL_HANDLER_ARGS);
 static int	ixl_sysctl_hw_res_alloc(SYSCTL_HANDLER_ARGS);
 static int	ixl_sysctl_switch_config(SYSCTL_HANDLER_ARGS);
 static int	ixl_sysctl_hkey(SYSCTL_HANDLER_ARGS);
 static int	ixl_sysctl_hena(SYSCTL_HANDLER_ARGS);
 static int	ixl_sysctl_hlut(SYSCTL_HANDLER_ARGS);
 static int	ixl_sysctl_fw_link_management(SYSCTL_HANDLER_ARGS);
 static int	ixl_sysctl_read_i2c_byte(SYSCTL_HANDLER_ARGS);
 static int	ixl_sysctl_write_i2c_byte(SYSCTL_HANDLER_ARGS);
 static int	ixl_sysctl_fec_fc_ability(SYSCTL_HANDLER_ARGS);
 static int	ixl_sysctl_fec_rs_ability(SYSCTL_HANDLER_ARGS);
 static int	ixl_sysctl_fec_fc_request(SYSCTL_HANDLER_ARGS);
 static int	ixl_sysctl_fec_rs_request(SYSCTL_HANDLER_ARGS);
 static int	ixl_sysctl_fec_auto_enable(SYSCTL_HANDLER_ARGS);
 #ifdef IXL_DEBUG
 static int	ixl_sysctl_qtx_tail_handler(SYSCTL_HANDLER_ARGS);
 static int	ixl_sysctl_qrx_tail_handler(SYSCTL_HANDLER_ARGS);
 #endif
 
 #ifdef IXL_IW
 extern int ixl_enable_iwarp;
 #endif
 
+const uint8_t ixl_bcast_addr[ETHER_ADDR_LEN] =
+    {0xff, 0xff, 0xff, 0xff, 0xff, 0xff};
+
+const char * const ixl_fc_string[6] = {
+	"None",
+	"Rx",
+	"Tx",
+	"Full",
+	"Priority",
+	"Default"
+};
+
+MALLOC_DEFINE(M_IXL, "ixl", "ixl driver allocations");
+
 void
 ixl_debug_core(struct ixl_pf *pf, enum ixl_dbg_mask mask, char *fmt, ...)
 {
 	va_list args;
 
 	if (!(mask & pf->dbg_mask))
 		return;
 
 	/* Re-implement device_printf() */
 	device_print_prettyname(pf->dev);
 	va_start(args, fmt);
 	vprintf(fmt, args);
 	va_end(args);
 }
 
 /*
 ** Put the FW, API, NVM, EEtrackID, and OEM version information into a string
 */
 void
 ixl_nvm_version_str(struct i40e_hw *hw, struct sbuf *buf)
 {
 	u8 oem_ver = (u8)(hw->nvm.oem_ver >> 24);
 	u16 oem_build = (u16)((hw->nvm.oem_ver >> 16) & 0xFFFF);
 	u8 oem_patch = (u8)(hw->nvm.oem_ver & 0xFF);
 
 	sbuf_printf(buf,
 	    "fw %d.%d.%05d api %d.%d nvm %x.%02x etid %08x oem %d.%d.%d",
 	    hw->aq.fw_maj_ver, hw->aq.fw_min_ver, hw->aq.fw_build,
 	    hw->aq.api_maj_ver, hw->aq.api_min_ver,
 	    (hw->nvm.version & IXL_NVM_VERSION_HI_MASK) >>
 	    IXL_NVM_VERSION_HI_SHIFT,
 	    (hw->nvm.version & IXL_NVM_VERSION_LO_MASK) >>
 	    IXL_NVM_VERSION_LO_SHIFT,
 	    hw->nvm.eetrack,
 	    oem_ver, oem_build, oem_patch);
 }
 
 void
 ixl_print_nvm_version(struct ixl_pf *pf)
 {
 	struct i40e_hw *hw = &pf->hw;
 	device_t dev = pf->dev;
 	struct sbuf *sbuf;
 
 	sbuf = sbuf_new_auto();
 	ixl_nvm_version_str(hw, sbuf);
 	sbuf_finish(sbuf);
 	device_printf(dev, "%s\n", sbuf_data(sbuf));
 	sbuf_delete(sbuf);
 }
 
 static void
 ixl_configure_tx_itr(struct ixl_pf *pf)
 {
 	struct i40e_hw		*hw = &pf->hw;
 	struct ixl_vsi		*vsi = &pf->vsi;
 	struct ixl_queue	*que = vsi->queues;
 
 	vsi->tx_itr_setting = pf->tx_itr;
 
 	for (int i = 0; i < vsi->num_queues; i++, que++) {
 		struct tx_ring	*txr = &que->txr;
 
 		wr32(hw, I40E_PFINT_ITRN(IXL_TX_ITR, i),
 		    vsi->tx_itr_setting);
 		txr->itr = vsi->tx_itr_setting;
 		txr->latency = IXL_AVE_LATENCY;
 	}
 }
 
 static void
 ixl_configure_rx_itr(struct ixl_pf *pf)
 {
 	struct i40e_hw		*hw = &pf->hw;
 	struct ixl_vsi		*vsi = &pf->vsi;
 	struct ixl_queue	*que = vsi->queues;
 
 	vsi->rx_itr_setting = pf->rx_itr;
 
 	for (int i = 0; i < vsi->num_queues; i++, que++) {
 		struct rx_ring 	*rxr = &que->rxr;
 
 		wr32(hw, I40E_PFINT_ITRN(IXL_RX_ITR, i),
 		    vsi->rx_itr_setting);
 		rxr->itr = vsi->rx_itr_setting;
 		rxr->latency = IXL_AVE_LATENCY;
 	}
 }
 
 /*
  * Write PF ITR values to queue ITR registers.
  */
 void
 ixl_configure_itr(struct ixl_pf *pf)
 {
 	ixl_configure_tx_itr(pf);
 	ixl_configure_rx_itr(pf);
 }
 
 
 /*********************************************************************
  *  Init entry point
  *
  *  This routine is used in two ways. It is used by the stack as
  *  init entry point in network interface structure. It is also used
  *  by the driver as a hw/sw initialization routine to get to a
  *  consistent state.
  *
  *  return 0 on success, positive on failure
  **********************************************************************/
 void
 ixl_init_locked(struct ixl_pf *pf)
 {
 	struct i40e_hw	*hw = &pf->hw;
 	struct ixl_vsi	*vsi = &pf->vsi;
 	struct ifnet	*ifp = vsi->ifp;
 	device_t 	dev = pf->dev;
 	struct i40e_filter_control_settings	filter;
 	u8		tmpaddr[ETHER_ADDR_LEN];
 	int		ret;
 
 	INIT_DEBUGOUT("ixl_init_locked: begin");
 	IXL_PF_LOCK_ASSERT(pf);
 
 	ixl_stop_locked(pf);
 
 	/*
 	 * If the aq is dead here, it probably means something outside of the driver
 	 * did something to the adapter, like a PF reset.
 	 * So rebuild the driver's state here if that occurs.
 	 */
 	if (!i40e_check_asq_alive(&pf->hw)) {
 		device_printf(dev, "Admin Queue is down; resetting...\n");
 		ixl_teardown_hw_structs(pf);
 		ixl_reset(pf);
 	}
 
 	/* Get the latest mac address... User might use a LAA */
 	bcopy(IF_LLADDR(vsi->ifp), tmpaddr,
 	      I40E_ETH_LENGTH_OF_ADDRESS);
 	if (!cmp_etheraddr(hw->mac.addr, tmpaddr) &&
 	    (i40e_validate_mac_addr(tmpaddr) == I40E_SUCCESS)) {
 		ixl_del_filter(vsi, hw->mac.addr, IXL_VLAN_ANY);
 		bcopy(tmpaddr, hw->mac.addr,
 		    I40E_ETH_LENGTH_OF_ADDRESS);
 		ret = i40e_aq_mac_address_write(hw,
 		    I40E_AQC_WRITE_TYPE_LAA_ONLY,
 		    hw->mac.addr, NULL);
 		if (ret) {
 			device_printf(dev, "LLA address"
 			 "change failed!!\n");
 			return;
 		}
 	}
 
 	ixl_add_filter(vsi, hw->mac.addr, IXL_VLAN_ANY);
 
 	/* Set the various hardware offload abilities */
 	ifp->if_hwassist = 0;
 	if (ifp->if_capenable & IFCAP_TSO)
 		ifp->if_hwassist |= CSUM_TSO;
 	if (ifp->if_capenable & IFCAP_TXCSUM)
 		ifp->if_hwassist |= (CSUM_TCP | CSUM_UDP);
 	if (ifp->if_capenable & IFCAP_TXCSUM_IPV6)
 		ifp->if_hwassist |= (CSUM_TCP_IPV6 | CSUM_UDP_IPV6);
 
 	/* Set up the device filtering */
 	bzero(&filter, sizeof(filter));
 	filter.enable_ethtype = TRUE;
 	filter.enable_macvlan = TRUE;
 	filter.enable_fdir = FALSE;
 	filter.hash_lut_size = I40E_HASH_LUT_SIZE_512;
 	if (i40e_set_filter_control(hw, &filter))
 		device_printf(dev, "i40e_set_filter_control() failed\n");
 
 	/* Prepare the VSI: rings, hmc contexts, etc... */
 	if (ixl_initialize_vsi(vsi)) {
 		device_printf(dev, "initialize vsi failed!!\n");
 		return;
 	}
 
 	/* Set up RSS */
 	ixl_config_rss(pf);
 
 	/* Add protocol filters to list */
 	ixl_init_filters(vsi);
 
 	/* Setup vlan's if needed */
 	ixl_setup_vlan_filters(vsi);
 
 	/* Set up MSI/X routing and the ITR settings */
 	if (pf->msix > 1) {
 		ixl_configure_queue_intr_msix(pf);
 		ixl_configure_itr(pf);
 	} else
 		ixl_configure_legacy(pf);
 
 	ixl_enable_rings(vsi);
 
 	i40e_aq_set_default_vsi(hw, vsi->seid, NULL);
 
 	ixl_reconfigure_filters(vsi);
 
 	/* And now turn on interrupts */
 	ixl_enable_intr(vsi);
 
 	/* Get link info */
 	hw->phy.get_link_info = TRUE;
 	i40e_get_link_status(hw, &pf->link_up);
 	ixl_update_link_status(pf);
 
 	/* Start the local timer */
 	callout_reset(&pf->timer, hz, ixl_local_timer, pf);
 
 	/* Now inform the stack we're ready */
 	ifp->if_drv_flags |= IFF_DRV_RUNNING;
 
 #ifdef IXL_IW
 	if (ixl_enable_iwarp && pf->iw_enabled) {
 		ret = ixl_iw_pf_init(pf);
 		if (ret)
 			device_printf(dev,
 			    "initialize iwarp failed, code %d\n", ret);
 	}
 #endif
 
 }
 
 
 /*********************************************************************
  *
  *  Get the hardware capabilities
  *
  **********************************************************************/
 
 int
 ixl_get_hw_capabilities(struct ixl_pf *pf)
 {
 	struct i40e_aqc_list_capabilities_element_resp *buf;
 	struct i40e_hw	*hw = &pf->hw;
 	device_t 	dev = pf->dev;
 	int             error, len;
 	u16		needed;
 	bool		again = TRUE;
 
 	len = 40 * sizeof(struct i40e_aqc_list_capabilities_element_resp);
 retry:
 	if (!(buf = (struct i40e_aqc_list_capabilities_element_resp *)
 	    malloc(len, M_DEVBUF, M_NOWAIT | M_ZERO))) {
 		device_printf(dev, "Unable to allocate cap memory\n");
                 return (ENOMEM);
 	}
 
 	/* This populates the hw struct */
         error = i40e_aq_discover_capabilities(hw, buf, len,
 	    &needed, i40e_aqc_opc_list_func_capabilities, NULL);
 	free(buf, M_DEVBUF);
 	if ((pf->hw.aq.asq_last_status == I40E_AQ_RC_ENOMEM) &&
 	    (again == TRUE)) {
 		/* retry once with a larger buffer */
 		again = FALSE;
 		len = needed;
 		goto retry;
 	} else if (pf->hw.aq.asq_last_status != I40E_AQ_RC_OK) {
 		device_printf(dev, "capability discovery failed: %d\n",
 		    pf->hw.aq.asq_last_status);
 		return (ENODEV);
 	}
 
 	/* Capture this PF's starting queue pair */
 	pf->qbase = hw->func_caps.base_queue;
 
 #ifdef IXL_DEBUG
 	device_printf(dev, "pf_id=%d, num_vfs=%d, msix_pf=%d, "
 	    "msix_vf=%d, fd_g=%d, fd_b=%d, tx_qp=%d rx_qp=%d qbase=%d\n",
 	    hw->pf_id, hw->func_caps.num_vfs,
 	    hw->func_caps.num_msix_vectors,
 	    hw->func_caps.num_msix_vectors_vf,
 	    hw->func_caps.fd_filters_guaranteed,
 	    hw->func_caps.fd_filters_best_effort,
 	    hw->func_caps.num_tx_qp,
 	    hw->func_caps.num_rx_qp,
 	    hw->func_caps.base_queue);
 #endif
 	/* Print a subset of the capability information. */
 	device_printf(dev, "PF-ID[%d]: VFs %d, MSIX %d, VF MSIX %d, QPs %d, %s\n",
 	    hw->pf_id, hw->func_caps.num_vfs, hw->func_caps.num_msix_vectors,
 	    hw->func_caps.num_msix_vectors_vf, hw->func_caps.num_tx_qp,
 	    (hw->func_caps.mdio_port_mode == 2) ? "I2C" :
 	    (hw->func_caps.mdio_port_mode == 1) ? "MDIO dedicated" :
 	    "MDIO shared");
 
 	struct i40e_osdep *osdep = (struct i40e_osdep *)hw->back;
 	osdep->i2c_intfc_num = ixl_find_i2c_interface(pf);
 	if (osdep->i2c_intfc_num != -1)
 		pf->has_i2c = true;
 
 	return (error);
 }
 
 void
 ixl_cap_txcsum_tso(struct ixl_vsi *vsi, struct ifnet *ifp, int mask)
 {
 	device_t 	dev = vsi->dev;
 
 	/* Enable/disable TXCSUM/TSO4 */
 	if (!(ifp->if_capenable & IFCAP_TXCSUM)
 	    && !(ifp->if_capenable & IFCAP_TSO4)) {
 		if (mask & IFCAP_TXCSUM) {
 			ifp->if_capenable |= IFCAP_TXCSUM;
 			/* enable TXCSUM, restore TSO if previously enabled */
 			if (vsi->flags & IXL_FLAGS_KEEP_TSO4) {
 				vsi->flags &= ~IXL_FLAGS_KEEP_TSO4;
 				ifp->if_capenable |= IFCAP_TSO4;
 			}
 		}
 		else if (mask & IFCAP_TSO4) {
 			ifp->if_capenable |= (IFCAP_TXCSUM | IFCAP_TSO4);
 			vsi->flags &= ~IXL_FLAGS_KEEP_TSO4;
 			device_printf(dev,
 			    "TSO4 requires txcsum, enabling both...\n");
 		}
 	} else if((ifp->if_capenable & IFCAP_TXCSUM)
 	    && !(ifp->if_capenable & IFCAP_TSO4)) {
 		if (mask & IFCAP_TXCSUM)
 			ifp->if_capenable &= ~IFCAP_TXCSUM;
 		else if (mask & IFCAP_TSO4)
 			ifp->if_capenable |= IFCAP_TSO4;
 	} else if((ifp->if_capenable & IFCAP_TXCSUM)
 	    && (ifp->if_capenable & IFCAP_TSO4)) {
 		if (mask & IFCAP_TXCSUM) {
 			vsi->flags |= IXL_FLAGS_KEEP_TSO4;
 			ifp->if_capenable &= ~(IFCAP_TXCSUM | IFCAP_TSO4);
 			device_printf(dev, 
 			    "TSO4 requires txcsum, disabling both...\n");
 		} else if (mask & IFCAP_TSO4)
 			ifp->if_capenable &= ~IFCAP_TSO4;
 	}
 
 	/* Enable/disable TXCSUM_IPV6/TSO6 */
 	if (!(ifp->if_capenable & IFCAP_TXCSUM_IPV6)
 	    && !(ifp->if_capenable & IFCAP_TSO6)) {
 		if (mask & IFCAP_TXCSUM_IPV6) {
 			ifp->if_capenable |= IFCAP_TXCSUM_IPV6;
 			if (vsi->flags & IXL_FLAGS_KEEP_TSO6) {
 				vsi->flags &= ~IXL_FLAGS_KEEP_TSO6;
 				ifp->if_capenable |= IFCAP_TSO6;
 			}
 		} else if (mask & IFCAP_TSO6) {
 			ifp->if_capenable |= (IFCAP_TXCSUM_IPV6 | IFCAP_TSO6);
 			vsi->flags &= ~IXL_FLAGS_KEEP_TSO6;
 			device_printf(dev,
 			    "TSO6 requires txcsum6, enabling both...\n");
 		}
 	} else if((ifp->if_capenable & IFCAP_TXCSUM_IPV6)
 	    && !(ifp->if_capenable & IFCAP_TSO6)) {
 		if (mask & IFCAP_TXCSUM_IPV6)
 			ifp->if_capenable &= ~IFCAP_TXCSUM_IPV6;
 		else if (mask & IFCAP_TSO6)
 			ifp->if_capenable |= IFCAP_TSO6;
 	} else if ((ifp->if_capenable & IFCAP_TXCSUM_IPV6)
 	    && (ifp->if_capenable & IFCAP_TSO6)) {
 		if (mask & IFCAP_TXCSUM_IPV6) {
 			vsi->flags |= IXL_FLAGS_KEEP_TSO6;
 			ifp->if_capenable &= ~(IFCAP_TXCSUM_IPV6 | IFCAP_TSO6);
 			device_printf(dev,
 			    "TSO6 requires txcsum6, disabling both...\n");
 		} else if (mask & IFCAP_TSO6)
 			ifp->if_capenable &= ~IFCAP_TSO6;
 	}
 }
 
 /* For the set_advertise sysctl */
 void
 ixl_get_initial_advertised_speeds(struct ixl_pf *pf)
 {
 	struct i40e_hw *hw = &pf->hw;
 	device_t dev = pf->dev;
 	enum i40e_status_code status;
 	struct i40e_aq_get_phy_abilities_resp abilities;
 
 	/* Set initial sysctl values */
 	status = i40e_aq_get_phy_capabilities(hw, FALSE, false, &abilities,
 					      NULL);
 	if (status) {
 		/* Non-fatal error */
 		device_printf(dev, "%s: i40e_aq_get_phy_capabilities() error %d\n",
 		     __func__, status);
 		return;
 	}
 
 	pf->advertised_speed =
 	    ixl_convert_sysctl_aq_link_speed(abilities.link_speed, false);
 }
 
 int
 ixl_teardown_hw_structs(struct ixl_pf *pf)
 {
 	enum i40e_status_code status = 0;
 	struct i40e_hw *hw = &pf->hw;
 	device_t dev = pf->dev;
 
 	/* Shutdown LAN HMC */
 	if (hw->hmc.hmc_obj) {
 		status = i40e_shutdown_lan_hmc(hw);
 		if (status) {
 			device_printf(dev,
 			    "init: LAN HMC shutdown failure; status %d\n", status);
 			goto err_out;
 		}
 	}
 
 	// XXX: This gets called when we know the adminq is inactive;
 	// so we already know it's setup when we get here.
 
 	/* Shutdown admin queue */
 	status = i40e_shutdown_adminq(hw);
 	if (status)
 		device_printf(dev,
 		    "init: Admin Queue shutdown failure; status %d\n", status);
 
 err_out:
 	return (status);
 }
 
 int
 ixl_reset(struct ixl_pf *pf)
 {
 	struct i40e_hw *hw = &pf->hw;
 	device_t dev = pf->dev;
 	u8 set_fc_err_mask;
 	int error = 0;
 
 	// XXX: clear_hw() actually writes to hw registers -- maybe this isn't necessary
 	i40e_clear_hw(hw);
 	error = i40e_pf_reset(hw);
 	if (error) {
 		device_printf(dev, "init: PF reset failure");
 		error = EIO;
 		goto err_out;
 	}
 
 	error = i40e_init_adminq(hw);
 	if (error) {
 		device_printf(dev, "init: Admin queue init failure;"
 		    " status code %d", error);
 		error = EIO;
 		goto err_out;
 	}
 
 	i40e_clear_pxe_mode(hw);
 
 	error = ixl_get_hw_capabilities(pf);
 	if (error) {
 		device_printf(dev, "init: Error retrieving HW capabilities;"
 		    " status code %d\n", error);
 		goto err_out;
 	}
 
 	error = i40e_init_lan_hmc(hw, hw->func_caps.num_tx_qp,
 	    hw->func_caps.num_rx_qp, 0, 0);
 	if (error) {
 		device_printf(dev, "init: LAN HMC init failed; status code %d\n",
 		    error);
 		error = EIO;
 		goto err_out;
 	}
 
 	error = i40e_configure_lan_hmc(hw, I40E_HMC_MODEL_DIRECT_ONLY);
 	if (error) {
 		device_printf(dev, "init: LAN HMC config failed; status code %d\n",
 		    error);
 		error = EIO;
 		goto err_out;
 	}
 
 	// XXX: possible fix for panic, but our failure recovery is still broken
 	error = ixl_switch_config(pf);
 	if (error) {
 		device_printf(dev, "init: ixl_switch_config() failed: %d\n",
 		     error);
 		goto err_out;
 	}
 
 	error = i40e_aq_set_phy_int_mask(hw, IXL_DEFAULT_PHY_INT_MASK,
 	    NULL);
         if (error) {
 		device_printf(dev, "init: i40e_aq_set_phy_mask() failed: err %d,"
 		    " aq_err %d\n", error, hw->aq.asq_last_status);
 		error = EIO;
 		goto err_out;
 	}
 
 	error = i40e_set_fc(hw, &set_fc_err_mask, true);
 	if (error) {
 		device_printf(dev, "init: setting link flow control failed; retcode %d,"
 		    " fc_err_mask 0x%02x\n", error, set_fc_err_mask);
 		goto err_out;
 	}
 
 	// XXX: (Rebuild VSIs?)
 
 	/* Firmware delay workaround */
 	if (((hw->aq.fw_maj_ver == 4) && (hw->aq.fw_min_ver < 33)) ||
 	    (hw->aq.fw_maj_ver < 4)) {
 		i40e_msec_delay(75);
 		error = i40e_aq_set_link_restart_an(hw, TRUE, NULL);
 		if (error) {
 			device_printf(dev, "init: link restart failed, aq_err %d\n",
 			    hw->aq.asq_last_status);
 			goto err_out;
 		}
 	}
 
 
 err_out:
 	return (error);
 }
 
 /*
 ** MSIX Interrupt Handlers and Tasklets
 */
 void
 ixl_handle_que(void *context, int pending)
 {
 	struct ixl_queue *que = context;
 	struct ixl_vsi *vsi = que->vsi;
 	struct i40e_hw  *hw = vsi->hw;
 	struct tx_ring  *txr = &que->txr;
 	struct ifnet    *ifp = vsi->ifp;
 	bool		more;
 
 	if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
 		more = ixl_rxeof(que, IXL_RX_LIMIT);
 		IXL_TX_LOCK(txr);
 		ixl_txeof(que);
 		if (!drbr_empty(ifp, txr->br))
 			ixl_mq_start_locked(ifp, txr);
 		IXL_TX_UNLOCK(txr);
 		if (more) {
 			taskqueue_enqueue(que->tq, &que->task);
 			return;
 		}
 	}
 
 	/* Reenable this interrupt - hmmm */
 	ixl_enable_queue(hw, que->me);
 	return;
 }
 
 
 /*********************************************************************
  *
  *  Legacy Interrupt Service routine
  *
  **********************************************************************/
 void
 ixl_intr(void *arg)
 {
 	struct ixl_pf		*pf = arg;
 	struct i40e_hw		*hw =  &pf->hw;
 	struct ixl_vsi		*vsi = &pf->vsi;
 	struct ixl_queue	*que = vsi->queues;
 	struct ifnet		*ifp = vsi->ifp;
 	struct tx_ring		*txr = &que->txr;
         u32			icr0;
 	bool			more_tx, more_rx;
 
 	pf->admin_irq++;
 
 	/* Protect against spurious interrupts */
 	if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0)
 		return;
 
 	icr0 = rd32(hw, I40E_PFINT_ICR0);
 
 
 #ifdef PCI_IOV
 	if (icr0 & I40E_PFINT_ICR0_VFLR_MASK)
 		taskqueue_enqueue(pf->tq, &pf->vflr_task);
 #endif
 
 	if (icr0 & I40E_PFINT_ICR0_ADMINQ_MASK) {
 		taskqueue_enqueue(pf->tq, &pf->adminq);
 	}
 
 	if (icr0 & I40E_PFINT_ICR0_QUEUE_0_MASK) {
 		++que->irqs;
 
 		more_rx = ixl_rxeof(que, IXL_RX_LIMIT);
 
 		IXL_TX_LOCK(txr);
 		more_tx = ixl_txeof(que);
 		if (!drbr_empty(vsi->ifp, txr->br))
 			more_tx = 1;
 		IXL_TX_UNLOCK(txr);
 	}
 
 	ixl_enable_intr0(hw);
 }
 
 
 /*********************************************************************
  *
  *  MSIX VSI Interrupt Service routine
  *
  **********************************************************************/
 void
 ixl_msix_que(void *arg)
 {
 	struct ixl_queue	*que = arg;
 	struct ixl_vsi	*vsi = que->vsi;
 	struct i40e_hw	*hw = vsi->hw;
 	struct tx_ring	*txr = &que->txr;
 	bool		more_tx, more_rx;
 
 	/* Protect against spurious interrupts */
 	if (!(vsi->ifp->if_drv_flags & IFF_DRV_RUNNING))
 		return;
 
 	++que->irqs;
 
 	more_rx = ixl_rxeof(que, IXL_RX_LIMIT);
 
 	IXL_TX_LOCK(txr);
 	more_tx = ixl_txeof(que);
 	/*
 	** Make certain that if the stack 
 	** has anything queued the task gets
 	** scheduled to handle it.
 	*/
 	if (!drbr_empty(vsi->ifp, txr->br))
 		more_tx = 1;
 	IXL_TX_UNLOCK(txr);
 
 	ixl_set_queue_rx_itr(que);
 	ixl_set_queue_tx_itr(que);
 
 	if (more_tx || more_rx)
 		taskqueue_enqueue(que->tq, &que->task);
 	else
 		ixl_enable_queue(hw, que->me);
 
 	return;
 }
 
 
 /*********************************************************************
  *
  *  MSIX Admin Queue Interrupt Service routine
  *
  **********************************************************************/
 void
 ixl_msix_adminq(void *arg)
 {
 	struct ixl_pf	*pf = arg;
 	struct i40e_hw	*hw = &pf->hw;
 	device_t	dev = pf->dev;
 	u32		reg, mask, rstat_reg;
 	bool		do_task = FALSE;
 
 	++pf->admin_irq;
 
 	reg = rd32(hw, I40E_PFINT_ICR0);
 	mask = rd32(hw, I40E_PFINT_ICR0_ENA);
 
 	/* Check on the cause */
 	if (reg & I40E_PFINT_ICR0_ADMINQ_MASK) {
 		mask &= ~I40E_PFINT_ICR0_ADMINQ_MASK;
 		do_task = TRUE;
 	}
 
 	if (reg & I40E_PFINT_ICR0_MAL_DETECT_MASK) {
 		ixl_handle_mdd_event(pf);
 		mask &= ~I40E_PFINT_ICR0_MAL_DETECT_MASK;
 	}
 
 	if (reg & I40E_PFINT_ICR0_GRST_MASK) {
 		device_printf(dev, "Reset Requested!\n");
 		rstat_reg = rd32(hw, I40E_GLGEN_RSTAT);
 		rstat_reg = (rstat_reg & I40E_GLGEN_RSTAT_RESET_TYPE_MASK)
 		    >> I40E_GLGEN_RSTAT_RESET_TYPE_SHIFT;
 		device_printf(dev, "Reset type: ");
 		switch (rstat_reg) {
 		/* These others might be handled similarly to an EMPR reset */
 		case I40E_RESET_CORER:
 			printf("CORER\n");
 			break;
 		case I40E_RESET_GLOBR:
 			printf("GLOBR\n");
 			break;
 		case I40E_RESET_EMPR:
 			printf("EMPR\n");
 			atomic_set_int(&pf->state, IXL_PF_STATE_EMPR_RESETTING);
 			break;
 		default:
 			printf("POR\n");
 			break;
 		}
 		/* overload admin queue task to check reset progress */
 		do_task = TRUE;
 	}
 
 	if (reg & I40E_PFINT_ICR0_ECC_ERR_MASK) {
 		device_printf(dev, "ECC Error detected!\n");
 	}
 
 	if (reg & I40E_PFINT_ICR0_HMC_ERR_MASK) {
 		reg = rd32(hw, I40E_PFHMC_ERRORINFO);
 		if (reg & I40E_PFHMC_ERRORINFO_ERROR_DETECTED_MASK) {
 			device_printf(dev, "HMC Error detected!\n");
 			device_printf(dev, "INFO 0x%08x\n", reg);
 			reg = rd32(hw, I40E_PFHMC_ERRORDATA);
 			device_printf(dev, "DATA 0x%08x\n", reg);
 			wr32(hw, I40E_PFHMC_ERRORINFO, 0);
 		}
 	}
 
 	if (reg & I40E_PFINT_ICR0_PCI_EXCEPTION_MASK) {
 		device_printf(dev, "PCI Exception detected!\n");
 	}
 
 #ifdef PCI_IOV
 	if (reg & I40E_PFINT_ICR0_VFLR_MASK) {
 		mask &= ~I40E_PFINT_ICR0_ENA_VFLR_MASK;
 		taskqueue_enqueue(pf->tq, &pf->vflr_task);
 	}
 #endif
 
 	if (do_task)
 		taskqueue_enqueue(pf->tq, &pf->adminq);
 	else
 		ixl_enable_intr0(hw);
 }
 
 void
 ixl_set_promisc(struct ixl_vsi *vsi)
 {
 	struct ifnet	*ifp = vsi->ifp;
 	struct i40e_hw	*hw = vsi->hw;
 	int		err, mcnt = 0;
 	bool		uni = FALSE, multi = FALSE;
 
 	if (ifp->if_flags & IFF_ALLMULTI)
                 multi = TRUE;
 	else { /* Need to count the multicast addresses */
 		struct  ifmultiaddr *ifma;
 		if_maddr_rlock(ifp);
 		TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
                         if (ifma->ifma_addr->sa_family != AF_LINK)
                                 continue;
                         if (mcnt == MAX_MULTICAST_ADDR)
                                 break;
                         mcnt++;
 		}
 		if_maddr_runlock(ifp);
 	}
 
 	if (mcnt >= MAX_MULTICAST_ADDR)
                 multi = TRUE;
         if (ifp->if_flags & IFF_PROMISC)
 		uni = TRUE;
 
 	err = i40e_aq_set_vsi_unicast_promiscuous(hw,
 	    vsi->seid, uni, NULL, TRUE);
 	err = i40e_aq_set_vsi_multicast_promiscuous(hw,
 	    vsi->seid, multi, NULL);
 	return;
 }
 
 /*********************************************************************
  * 	Filter Routines
  *
  *	Routines for multicast and vlan filter management.
  *
  *********************************************************************/
 void
 ixl_add_multi(struct ixl_vsi *vsi)
 {
 	struct	ifmultiaddr	*ifma;
 	struct ifnet		*ifp = vsi->ifp;
 	struct i40e_hw		*hw = vsi->hw;
 	int			mcnt = 0, flags;
 
 	IOCTL_DEBUGOUT("ixl_add_multi: begin");
 
 	if_maddr_rlock(ifp);
 	/*
 	** First just get a count, to decide if we
 	** we simply use multicast promiscuous.
 	*/
 	TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
 		if (ifma->ifma_addr->sa_family != AF_LINK)
 			continue;
 		mcnt++;
 	}
 	if_maddr_runlock(ifp);
 
 	if (__predict_false(mcnt >= MAX_MULTICAST_ADDR)) {
 		/* delete existing MC filters */
 		ixl_del_hw_filters(vsi, mcnt);
 		i40e_aq_set_vsi_multicast_promiscuous(hw,
 		    vsi->seid, TRUE, NULL);
 		return;
 	}
 
 	mcnt = 0;
 	if_maddr_rlock(ifp);
 	TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
 		if (ifma->ifma_addr->sa_family != AF_LINK)
 			continue;
 		ixl_add_mc_filter(vsi,
 		    (u8*)LLADDR((struct sockaddr_dl *) ifma->ifma_addr));
 		mcnt++;
 	}
 	if_maddr_runlock(ifp);
 	if (mcnt > 0) {
 		flags = (IXL_FILTER_ADD | IXL_FILTER_USED | IXL_FILTER_MC);
 		ixl_add_hw_filters(vsi, flags, mcnt);
 	}
 
 	IOCTL_DEBUGOUT("ixl_add_multi: end");
 	return;
 }
 
 void
 ixl_del_multi(struct ixl_vsi *vsi)
 {
 	struct ifnet		*ifp = vsi->ifp;
 	struct ifmultiaddr	*ifma;
 	struct ixl_mac_filter	*f;
 	int			mcnt = 0;
 	bool		match = FALSE;
 
 	IOCTL_DEBUGOUT("ixl_del_multi: begin");
 
 	/* Search for removed multicast addresses */
 	if_maddr_rlock(ifp);
 	SLIST_FOREACH(f, &vsi->ftl, next) {
 		if ((f->flags & IXL_FILTER_USED) && (f->flags & IXL_FILTER_MC)) {
 			match = FALSE;
 			TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
 				if (ifma->ifma_addr->sa_family != AF_LINK)
 					continue;
 				u8 *mc_addr = (u8 *)LLADDR((struct sockaddr_dl *)ifma->ifma_addr);
 				if (cmp_etheraddr(f->macaddr, mc_addr)) {
 					match = TRUE;
 					break;
 				}
 			}
 			if (match == FALSE) {
 				f->flags |= IXL_FILTER_DEL;
 				mcnt++;
 			}
 		}
 	}
 	if_maddr_runlock(ifp);
 
 	if (mcnt > 0)
 		ixl_del_hw_filters(vsi, mcnt);
 }
 
 
 /*********************************************************************
  *  Timer routine
  *
  *  This routine checks for link status,updates statistics,
  *  and runs the watchdog check.
  *
  *  Only runs when the driver is configured UP and RUNNING.
  *
  **********************************************************************/
 
 void
 ixl_local_timer(void *arg)
 {
 	struct ixl_pf		*pf = arg;
 	struct i40e_hw		*hw = &pf->hw;
 	struct ixl_vsi		*vsi = &pf->vsi;
 	struct ixl_queue	*que = vsi->queues;
 	device_t		dev = pf->dev;
 	struct tx_ring		*txr;
 	int			hung = 0;
 	u32			mask;
 	s32			timer, new_timer;
 
 	IXL_PF_LOCK_ASSERT(pf);
 
 	/* Fire off the adminq task */
 	taskqueue_enqueue(pf->tq, &pf->adminq);
 
 	/* Update stats */
 	ixl_update_stats_counters(pf);
 
 	/* Check status of the queues */
 	mask = (I40E_PFINT_DYN_CTLN_INTENA_MASK |
 		I40E_PFINT_DYN_CTLN_SWINT_TRIG_MASK |
 		I40E_PFINT_DYN_CTLN_ITR_INDX_MASK);
  
 	for (int i = 0; i < vsi->num_queues; i++, que++) {
 		txr = &que->txr;
 		timer = atomic_load_acq_32(&txr->watchdog_timer);
 		if (timer > 0) {
 			new_timer = timer - hz;
 			if (new_timer <= 0) {
 				atomic_store_rel_32(&txr->watchdog_timer, -1);
 				device_printf(dev, "WARNING: queue %d "
 				    "appears to be hung!\n", que->me);
 				++hung;
 			} else {
 				/*
 				 * If this fails, that means something in the TX path has updated
 				 * the watchdog, so it means the TX path is still working and
 				 * the watchdog doesn't need to countdown.
 				 */
 				atomic_cmpset_rel_32(&txr->watchdog_timer, timer, new_timer);
 				/* Any queues with outstanding work get a sw irq */
 				wr32(hw, I40E_PFINT_DYN_CTLN(que->me), mask);
 			}
 		}
 	}
 	/* Reset when a queue shows hung */
 	if (hung)
 		goto hung;
 
 	callout_reset(&pf->timer, hz, ixl_local_timer, pf);
 	return;
 
 hung:
 	device_printf(dev, "WARNING: Resetting!\n");
 	pf->watchdog_events++;
 	ixl_init_locked(pf);
 }
 
 void
 ixl_link_up_msg(struct ixl_pf *pf)
 {
 	struct i40e_hw *hw = &pf->hw;
 	struct ifnet *ifp = pf->vsi.ifp;
 
 	log(LOG_NOTICE, "%s: Link is up, %s Full Duplex, FEC: %s, Autoneg: %s, Flow Control: %s\n",
 	    ifp->if_xname,
 	    ixl_aq_speed_to_str(hw->phy.link_info.link_speed),
 	    (hw->phy.link_info.fec_info & I40E_AQ_CONFIG_FEC_KR_ENA) ?
 		"Clause 74 BASE-R FEC" : (hw->phy.link_info.fec_info & I40E_AQ_CONFIG_FEC_RS_ENA) ?
 		"Clause 108 RS-FEC" : "None",
 	    (hw->phy.link_info.an_info & I40E_AQ_AN_COMPLETED) ? "True" : "False",
 	    (hw->phy.link_info.an_info & I40E_AQ_LINK_PAUSE_TX &&
 	        hw->phy.link_info.an_info & I40E_AQ_LINK_PAUSE_RX) ?
 		ixl_fc_string[3] : (hw->phy.link_info.an_info & I40E_AQ_LINK_PAUSE_TX) ?
 		ixl_fc_string[2] : (hw->phy.link_info.an_info & I40E_AQ_LINK_PAUSE_RX) ?
 		ixl_fc_string[1] : ixl_fc_string[0]);
 }
 
 /*
 ** Note: this routine updates the OS on the link state
 **	the real check of the hardware only happens with
 **	a link interrupt.
 */
 void
 ixl_update_link_status(struct ixl_pf *pf)
 {
 	struct ixl_vsi		*vsi = &pf->vsi;
 	struct ifnet		*ifp = vsi->ifp;
 	device_t		dev = pf->dev;
 
 	if (pf->link_up) {
 		if (vsi->link_active == FALSE) {
 			vsi->link_active = TRUE;
 			ifp->if_baudrate = ixl_max_aq_speed_to_value(pf->link_speed);
 			if_link_state_change(ifp, LINK_STATE_UP);
 			ixl_link_up_msg(pf);
 		}
 	} else { /* Link down */
 		if (vsi->link_active == TRUE) {
 			if (bootverbose)
 				device_printf(dev, "Link is Down\n");
 			if_link_state_change(ifp, LINK_STATE_DOWN);
 			vsi->link_active = FALSE;
 		}
 	}
 
 	return;
 }
 
 /*********************************************************************
  *
  *  This routine disables all traffic on the adapter by issuing a
  *  global reset on the MAC and deallocates TX/RX buffers.
  *
  **********************************************************************/
 
 void
 ixl_stop_locked(struct ixl_pf *pf)
 {
 	struct ixl_vsi	*vsi = &pf->vsi;
 	struct ifnet	*ifp = vsi->ifp;
 
 	INIT_DEBUGOUT("ixl_stop: begin\n");
 
 	IXL_PF_LOCK_ASSERT(pf);
 
 #ifdef IXL_IW
 	/* Stop iWARP device */
 	if (ixl_enable_iwarp && pf->iw_enabled)
 		ixl_iw_pf_stop(pf);
 #endif
 
 	/* Stop the local timer */
 	callout_stop(&pf->timer);
 
 	ixl_disable_rings_intr(vsi);
 	ixl_disable_rings(vsi);
 
 	/* Tell the stack that the interface is no longer active */
 	ifp->if_drv_flags &= ~(IFF_DRV_RUNNING);
 }
 
 void
 ixl_stop(struct ixl_pf *pf)
 {
 	IXL_PF_LOCK(pf);
 	ixl_stop_locked(pf);
 	IXL_PF_UNLOCK(pf);
 }
 
 /*********************************************************************
  *
  *  Setup MSIX Interrupt resources and handlers for the VSI
  *
  **********************************************************************/
 int
 ixl_setup_legacy(struct ixl_pf *pf)
 {
 	device_t        dev = pf->dev;
 	int 		error, rid = 0;
 
 	if (pf->msix == 1)
 		rid = 1;
 	pf->res = bus_alloc_resource_any(dev, SYS_RES_IRQ,
 	    &rid, RF_SHAREABLE | RF_ACTIVE);
 	if (pf->res == NULL) {
 		device_printf(dev, "bus_alloc_resource_any() for"
 		    " legacy/msi interrupt\n");
 		return (ENXIO);
 	}
 
 	/* Set the handler function */
 	error = bus_setup_intr(dev, pf->res,
 	    INTR_TYPE_NET | INTR_MPSAFE, NULL,
 	    ixl_intr, pf, &pf->tag);
 	if (error) {
 		pf->res = NULL;
 		device_printf(dev, "bus_setup_intr() for legacy/msi"
 		    " interrupt handler failed, error %d\n", error);
 		return (ENXIO);
 	}
 	error = bus_describe_intr(dev, pf->res, pf->tag, "irq");
 	if (error) {
 		/* non-fatal */
 		device_printf(dev, "bus_describe_intr() for Admin Queue"
 		    " interrupt name failed, error %d\n", error);
 	}
 
 	return (0);
 }
 
 int
 ixl_setup_adminq_tq(struct ixl_pf *pf)
 {
 	device_t dev = pf->dev;
 	int error = 0;
 
 	/* Tasklet for Admin Queue interrupts */
 	TASK_INIT(&pf->adminq, 0, ixl_do_adminq, pf);
 #ifdef PCI_IOV
 	/* VFLR Tasklet */
 	TASK_INIT(&pf->vflr_task, 0, ixl_handle_vflr, pf);
 #endif
 	/* Create and start Admin Queue taskqueue */
 	pf->tq = taskqueue_create_fast("ixl_aq", M_NOWAIT,
 	    taskqueue_thread_enqueue, &pf->tq);
 	if (!pf->tq) {
 		device_printf(dev, "taskqueue_create_fast (for AQ) returned NULL!\n");
 		return (ENOMEM);
 	}
 	error = taskqueue_start_threads(&pf->tq, 1, PI_NET, "%s aq",
 	    device_get_nameunit(dev));
 	if (error) {
 		device_printf(dev, "taskqueue_start_threads (for AQ) error: %d\n",
 		    error);
 		taskqueue_free(pf->tq);
 		return (error);
 	}
 	return (0);
 }
 
 int
 ixl_setup_queue_tqs(struct ixl_vsi *vsi)
 {
 	struct ixl_queue *que = vsi->queues;
 	device_t dev = vsi->dev;
 #ifdef  RSS
 	int		cpu_id = 0;
         cpuset_t	cpu_mask;
 #endif
 
 	/* Create queue tasks and start queue taskqueues */
 	for (int i = 0; i < vsi->num_queues; i++, que++) {
 		TASK_INIT(&que->tx_task, 0, ixl_deferred_mq_start, que);
 		TASK_INIT(&que->task, 0, ixl_handle_que, que);
 		que->tq = taskqueue_create_fast("ixl_que", M_NOWAIT,
 		    taskqueue_thread_enqueue, &que->tq);
 #ifdef RSS
 		CPU_SETOF(cpu_id, &cpu_mask);
 		taskqueue_start_threads_cpuset(&que->tq, 1, PI_NET,
 		    &cpu_mask, "%s (bucket %d)",
 		    device_get_nameunit(dev), cpu_id);
 #else
 		taskqueue_start_threads(&que->tq, 1, PI_NET,
 		    "%s (que %d)", device_get_nameunit(dev), que->me);
 #endif
 	}
 
 	return (0);
 }
 
 void
 ixl_free_adminq_tq(struct ixl_pf *pf)
 {
 	if (pf->tq) {
 		taskqueue_free(pf->tq);
 		pf->tq = NULL;
 	}
 }
 
 void
 ixl_free_queue_tqs(struct ixl_vsi *vsi)
 {
 	struct ixl_queue *que = vsi->queues;
 
 	for (int i = 0; i < vsi->num_queues; i++, que++) {
 		if (que->tq) {
 			taskqueue_free(que->tq);
 			que->tq = NULL;
 		}
 	}
 }
 
 int
 ixl_setup_adminq_msix(struct ixl_pf *pf)
 {
 	device_t dev = pf->dev;
 	int rid, error = 0;
 
 	/* Admin IRQ rid is 1, vector is 0 */
 	rid = 1;
 	/* Get interrupt resource from bus */
 	pf->res = bus_alloc_resource_any(dev,
     	    SYS_RES_IRQ, &rid, RF_SHAREABLE | RF_ACTIVE);
 	if (!pf->res) {
 		device_printf(dev, "bus_alloc_resource_any() for Admin Queue"
 		    " interrupt failed [rid=%d]\n", rid);
 		return (ENXIO);
 	}
 	/* Then associate interrupt with handler */
 	error = bus_setup_intr(dev, pf->res,
 	    INTR_TYPE_NET | INTR_MPSAFE, NULL,
 	    ixl_msix_adminq, pf, &pf->tag);
 	if (error) {
 		pf->res = NULL;
 		device_printf(dev, "bus_setup_intr() for Admin Queue"
 		    " interrupt handler failed, error %d\n", error);
 		return (ENXIO);
 	}
 	error = bus_describe_intr(dev, pf->res, pf->tag, "aq");
 	if (error) {
 		/* non-fatal */
 		device_printf(dev, "bus_describe_intr() for Admin Queue"
 		    " interrupt name failed, error %d\n", error);
 	}
 	pf->admvec = 0;
 
 	return (0);
 }
 
 /*
  * Allocate interrupt resources from bus and associate an interrupt handler
  * to those for the VSI's queues.
  */
 int
 ixl_setup_queue_msix(struct ixl_vsi *vsi)
 {
 	device_t	dev = vsi->dev;
 	struct 		ixl_queue *que = vsi->queues;
 	struct		tx_ring	 *txr;
 	int 		error, rid, vector = 1;
 
 	/* Queue interrupt vector numbers start at 1 (adminq intr is 0) */
 	for (int i = 0; i < vsi->num_queues; i++, vector++, que++) {
 		int cpu_id = i;
 		rid = vector + 1;
 		txr = &que->txr;
 		que->res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
 		    RF_SHAREABLE | RF_ACTIVE);
 		if (!que->res) {
 			device_printf(dev, "bus_alloc_resource_any() for"
 			    " Queue %d interrupt failed [rid=%d]\n",
 			    que->me, rid);
 			return (ENXIO);
 		}
 		/* Set the handler function */
 		error = bus_setup_intr(dev, que->res,
 		    INTR_TYPE_NET | INTR_MPSAFE, NULL,
 		    ixl_msix_que, que, &que->tag);
 		if (error) {
 			device_printf(dev, "bus_setup_intr() for Queue %d"
 			    " interrupt handler failed, error %d\n",
 			    que->me, error);
 			bus_release_resource(dev, SYS_RES_IRQ, rid, que->res);
 			return (error);
 		}
 		error = bus_describe_intr(dev, que->res, que->tag, "q%d", i);
 		if (error) {
 			device_printf(dev, "bus_describe_intr() for Queue %d"
 			    " interrupt name failed, error %d\n",
 			    que->me, error);
 		}
 		/* Bind the vector to a CPU */
 #ifdef RSS
 		cpu_id = rss_getcpu(i % rss_getnumbuckets());
 #endif
 		error = bus_bind_intr(dev, que->res, cpu_id);
 		if (error) {
 			device_printf(dev, "bus_bind_intr() for Queue %d"
 			    " to CPU %d failed, error %d\n",
 			    que->me, cpu_id, error);
 		}
 		que->msix = vector;
 	}
 
 	return (0);
 }
 
 /*
  * When used in a virtualized environment PCI BUSMASTER capability may not be set
  * so explicity set it here and rewrite the ENABLE in the MSIX control register
  * at this point to cause the host to successfully initialize us.
  */
 void
 ixl_set_busmaster(device_t dev)
 {
 	u16 pci_cmd_word;
 
 	pci_cmd_word = pci_read_config(dev, PCIR_COMMAND, 2);
 	pci_cmd_word |= PCIM_CMD_BUSMASTEREN;
 	pci_write_config(dev, PCIR_COMMAND, pci_cmd_word, 2);
 }
 
 /*
  * rewrite the ENABLE in the MSIX control register
  * to cause the host to successfully initialize us.
  */
 void
 ixl_set_msix_enable(device_t dev)
 {
 	int msix_ctrl, rid;
 
 	pci_find_cap(dev, PCIY_MSIX, &rid);
 	rid += PCIR_MSIX_CTRL;
 	msix_ctrl = pci_read_config(dev, rid, 2);
 	msix_ctrl |= PCIM_MSIXCTRL_MSIX_ENABLE;
 	pci_write_config(dev, rid, msix_ctrl, 2);
 }
 
 /*
  * Allocate MSI/X vectors from the OS.
  * Returns 0 for legacy, 1 for MSI, >1 for MSIX.
  */
 int
 ixl_init_msix(struct ixl_pf *pf)
 {
 	device_t dev = pf->dev;
 	struct i40e_hw *hw = &pf->hw;
 	int auto_max_queues;
 	int rid, want, vectors, queues, available;
 #ifdef IXL_IW
 	int iw_want, iw_vectors;
 
 	pf->iw_msix = 0;
 #endif
 
 	/* Override by tuneable */
 	if (!pf->enable_msix)
 		goto no_msix;
 
 	/* Ensure proper operation in virtualized environment */
 	ixl_set_busmaster(dev);
 
 	/* First try MSI/X */
 	rid = PCIR_BAR(IXL_MSIX_BAR);
 	pf->msix_mem = bus_alloc_resource_any(dev,
 	    SYS_RES_MEMORY, &rid, RF_ACTIVE);
        	if (!pf->msix_mem) {
 		/* May not be enabled */
 		device_printf(pf->dev,
 		    "Unable to map MSIX table\n");
 		goto no_msix;
 	}
 
 	available = pci_msix_count(dev); 
 	if (available < 2) {
 		/* system has msix disabled (0), or only one vector (1) */
 		bus_release_resource(dev, SYS_RES_MEMORY,
 		    rid, pf->msix_mem);
 		pf->msix_mem = NULL;
 		goto no_msix;
 	}
 
 	/* Clamp max number of queues based on:
 	 * - # of MSI-X vectors available
 	 * - # of cpus available
 	 * - # of queues that can be assigned to the LAN VSI
 	 */
 	auto_max_queues = min(mp_ncpus, available - 1);
 	if (hw->mac.type == I40E_MAC_X722)
 		auto_max_queues = min(auto_max_queues, 128);
 	else
 		auto_max_queues = min(auto_max_queues, 64);
 
 	/* Override with tunable value if tunable is less than autoconfig count */
 	if ((pf->max_queues != 0) && (pf->max_queues <= auto_max_queues))
 		queues = pf->max_queues;
 	/* Use autoconfig amount if that's lower */
 	else if ((pf->max_queues != 0) && (pf->max_queues > auto_max_queues)) {
 		device_printf(dev, "ixl_max_queues (%d) is too large, using "
 		    "autoconfig amount (%d)...\n",
 		    pf->max_queues, auto_max_queues);
 		queues = auto_max_queues;
 	}
 	/* Limit maximum auto-configured queues to 8 if no user value is set */
 	else
 		queues = min(auto_max_queues, 8);
 
 #ifdef  RSS
 	/* If we're doing RSS, clamp at the number of RSS buckets */
 	if (queues > rss_getnumbuckets())
 		queues = rss_getnumbuckets();
 #endif
 
 	/*
 	** Want one vector (RX/TX pair) per queue
 	** plus an additional for the admin queue.
 	*/
 	want = queues + 1;
 	if (want <= available)	/* Have enough */
 		vectors = want;
 	else {
                	device_printf(pf->dev,
 		    "MSIX Configuration Problem, "
 		    "%d vectors available but %d wanted!\n",
 		    available, want);
 		pf->msix_mem = NULL;
 		goto no_msix; /* Will go to Legacy setup */
 	}
 
 #ifdef IXL_IW
 	if (ixl_enable_iwarp) {
 		/* iWARP wants additional vector for CQP */
 		iw_want = mp_ncpus + 1;
 		available -= vectors;
 		if (available > 0) {
 			iw_vectors = (available >= iw_want) ?
 				iw_want : available;
 			vectors += iw_vectors;
 		} else
 			iw_vectors = 0;
 	}
 #endif
 
 	ixl_set_msix_enable(dev);
 	if (pci_alloc_msix(dev, &vectors) == 0) {
                	device_printf(pf->dev,
 		    "Using MSIX interrupts with %d vectors\n", vectors);
 		pf->msix = vectors;
 #ifdef IXL_IW
 		if (ixl_enable_iwarp)
 			pf->iw_msix = iw_vectors;
 #endif
 
 		pf->vsi.num_queues = queues;
 #ifdef RSS
 		/*
 		 * If we're doing RSS, the number of queues needs to
 		 * match the number of RSS buckets that are configured.
 		 *
 		 * + If there's more queues than RSS buckets, we'll end
 		 *   up with queues that get no traffic.
 		 *
 		 * + If there's more RSS buckets than queues, we'll end
 		 *   up having multiple RSS buckets map to the same queue,
 		 *   so there'll be some contention.
 		 */
 		if (queues != rss_getnumbuckets()) {
 			device_printf(dev,
 			    "%s: queues (%d) != RSS buckets (%d)"
 			    "; performance will be impacted.\n",
 			    __func__, queues, rss_getnumbuckets());
 		}
 #endif
 		return (vectors);
 	}
 no_msix:
 	vectors = pci_msi_count(dev);
 	pf->vsi.num_queues = 1;
 	pf->max_queues = 1;
 	if (vectors == 1 && pci_alloc_msi(dev, &vectors) == 0)
 		device_printf(pf->dev, "Using an MSI interrupt\n");
 	else {
 		vectors = 0;
 		device_printf(pf->dev, "Using a Legacy interrupt\n");
 	}
 	return (vectors);
 }
 
 /*
  * Configure admin queue/misc interrupt cause registers in hardware.
  */
 void
 ixl_configure_intr0_msix(struct ixl_pf *pf)
 {
 	struct i40e_hw *hw = &pf->hw;
 	u32 reg;
 
 	/* First set up the adminq - vector 0 */
 	wr32(hw, I40E_PFINT_ICR0_ENA, 0);  /* disable all */
 	rd32(hw, I40E_PFINT_ICR0);         /* read to clear */
 
 	reg = I40E_PFINT_ICR0_ENA_ECC_ERR_MASK |
 	    I40E_PFINT_ICR0_ENA_GRST_MASK |
 	    I40E_PFINT_ICR0_ENA_HMC_ERR_MASK |
 	    I40E_PFINT_ICR0_ENA_ADMINQ_MASK |
 	    I40E_PFINT_ICR0_ENA_MAL_DETECT_MASK |
 	    I40E_PFINT_ICR0_ENA_VFLR_MASK |
 	    I40E_PFINT_ICR0_ENA_PCI_EXCEPTION_MASK;
 	wr32(hw, I40E_PFINT_ICR0_ENA, reg);
 
 	/*
 	 * 0x7FF is the end of the queue list.
 	 * This means we won't use MSI-X vector 0 for a queue interrupt
 	 * in MSIX mode.
 	 */
 	wr32(hw, I40E_PFINT_LNKLST0, 0x7FF);
 	/* Value is in 2 usec units, so 0x3E is 62*2 = 124 usecs. */
 	wr32(hw, I40E_PFINT_ITR0(IXL_RX_ITR), 0x3E);
 
 	wr32(hw, I40E_PFINT_DYN_CTL0,
 	    I40E_PFINT_DYN_CTL0_SW_ITR_INDX_MASK |
 	    I40E_PFINT_DYN_CTL0_INTENA_MSK_MASK);
 
 	wr32(hw, I40E_PFINT_STAT_CTL0, 0);
 }
 
 /*
  * Configure queue interrupt cause registers in hardware.
  */
 void
 ixl_configure_queue_intr_msix(struct ixl_pf *pf)
 {
 	struct i40e_hw	*hw = &pf->hw;
 	struct ixl_vsi *vsi = &pf->vsi;
 	u32		reg;
 	u16		vector = 1;
 
 	for (int i = 0; i < vsi->num_queues; i++, vector++) {
 		wr32(hw, I40E_PFINT_DYN_CTLN(i), 0);
 		/* First queue type is RX / 0 */
 		wr32(hw, I40E_PFINT_LNKLSTN(i), i);
 
 		reg = I40E_QINT_RQCTL_CAUSE_ENA_MASK |
 		(IXL_RX_ITR << I40E_QINT_RQCTL_ITR_INDX_SHIFT) |
 		(vector << I40E_QINT_RQCTL_MSIX_INDX_SHIFT) |
 		(i << I40E_QINT_RQCTL_NEXTQ_INDX_SHIFT) |
 		(I40E_QUEUE_TYPE_TX << I40E_QINT_RQCTL_NEXTQ_TYPE_SHIFT);
 		wr32(hw, I40E_QINT_RQCTL(i), reg);
 
 		reg = I40E_QINT_TQCTL_CAUSE_ENA_MASK |
 		(IXL_TX_ITR << I40E_QINT_TQCTL_ITR_INDX_SHIFT) |
 		(vector << I40E_QINT_TQCTL_MSIX_INDX_SHIFT) |
 		(IXL_QUEUE_EOL << I40E_QINT_TQCTL_NEXTQ_INDX_SHIFT) |
 		(I40E_QUEUE_TYPE_RX << I40E_QINT_TQCTL_NEXTQ_TYPE_SHIFT);
 		wr32(hw, I40E_QINT_TQCTL(i), reg);
 	}
 }
 
 /*
  * Configure for MSI single vector operation 
  */
 void
 ixl_configure_legacy(struct ixl_pf *pf)
 {
 	struct i40e_hw	*hw = &pf->hw;
 	struct ixl_vsi	*vsi = &pf->vsi;
 	struct ixl_queue *que = vsi->queues;
 	struct rx_ring 	*rxr = &que->rxr;
 	struct tx_ring	*txr = &que->txr;
 	u32 reg;
 
 	/* Configure ITR */
 	vsi->tx_itr_setting = pf->tx_itr;
 	wr32(hw, I40E_PFINT_ITR0(IXL_TX_ITR),
 	    vsi->tx_itr_setting);
 	txr->itr = vsi->tx_itr_setting;
 
 	vsi->rx_itr_setting = pf->rx_itr;
 	wr32(hw, I40E_PFINT_ITR0(IXL_RX_ITR),
 	    vsi->rx_itr_setting);
 	rxr->itr = vsi->rx_itr_setting;
 
 	/* Setup "other" causes */
 	reg = I40E_PFINT_ICR0_ENA_ECC_ERR_MASK
 	    | I40E_PFINT_ICR0_ENA_MAL_DETECT_MASK
 	    | I40E_PFINT_ICR0_ENA_GRST_MASK
 	    | I40E_PFINT_ICR0_ENA_PCI_EXCEPTION_MASK
 	    | I40E_PFINT_ICR0_ENA_GPIO_MASK
 	    | I40E_PFINT_ICR0_ENA_LINK_STAT_CHANGE_MASK
 	    | I40E_PFINT_ICR0_ENA_HMC_ERR_MASK
 	    | I40E_PFINT_ICR0_ENA_PE_CRITERR_MASK
 	    | I40E_PFINT_ICR0_ENA_VFLR_MASK
 	    | I40E_PFINT_ICR0_ENA_ADMINQ_MASK
 	    ;
 	wr32(hw, I40E_PFINT_ICR0_ENA, reg);
 
 	/* No ITR for non-queue interrupts */
 	wr32(hw, I40E_PFINT_STAT_CTL0,
 	    IXL_ITR_NONE << I40E_PFINT_STAT_CTL0_OTHER_ITR_INDX_SHIFT);
 
 	/* FIRSTQ_INDX = 0, FIRSTQ_TYPE = 0 (rx) */
 	wr32(hw, I40E_PFINT_LNKLST0, 0);
 
 	/* Associate the queue pair to the vector and enable the q int */
 	reg = I40E_QINT_RQCTL_CAUSE_ENA_MASK
 	    | (IXL_RX_ITR << I40E_QINT_RQCTL_ITR_INDX_SHIFT)
 	    | (I40E_QUEUE_TYPE_TX << I40E_QINT_TQCTL_NEXTQ_TYPE_SHIFT);
 	wr32(hw, I40E_QINT_RQCTL(0), reg);
 
 	reg = I40E_QINT_TQCTL_CAUSE_ENA_MASK
 	    | (IXL_TX_ITR << I40E_QINT_TQCTL_ITR_INDX_SHIFT)
 	    | (IXL_QUEUE_EOL << I40E_QINT_TQCTL_NEXTQ_INDX_SHIFT);
 	wr32(hw, I40E_QINT_TQCTL(0), reg);
 }
 
 int
 ixl_allocate_pci_resources(struct ixl_pf *pf)
 {
 	int             rid;
 	struct i40e_hw *hw = &pf->hw;
 	device_t        dev = pf->dev;
 
 	/* Map BAR0 */
 	rid = PCIR_BAR(0);
 	pf->pci_mem = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
 	    &rid, RF_ACTIVE);
 
 	if (!(pf->pci_mem)) {
 		device_printf(dev, "Unable to allocate bus resource: PCI memory\n");
 		return (ENXIO);
 	}
 
 	/* Save off the PCI information */
 	hw->vendor_id = pci_get_vendor(dev);
 	hw->device_id = pci_get_device(dev);
 	hw->revision_id = pci_read_config(dev, PCIR_REVID, 1);
 	hw->subsystem_vendor_id =
 	    pci_read_config(dev, PCIR_SUBVEND_0, 2);
 	hw->subsystem_device_id =
 	    pci_read_config(dev, PCIR_SUBDEV_0, 2);
 
 	hw->bus.device = pci_get_slot(dev);
 	hw->bus.func = pci_get_function(dev);
 
 	/* Save off register access information */
 	pf->osdep.mem_bus_space_tag =
 		rman_get_bustag(pf->pci_mem);
 	pf->osdep.mem_bus_space_handle =
 		rman_get_bushandle(pf->pci_mem);
 	pf->osdep.mem_bus_space_size = rman_get_size(pf->pci_mem);
 	pf->osdep.flush_reg = I40E_GLGEN_STAT;
 	pf->hw.hw_addr = (u8 *) &pf->osdep.mem_bus_space_handle;
 
 	pf->hw.back = &pf->osdep;
 
 	return (0);
 }
 
 /*
  * Teardown and release the admin queue/misc vector
  * interrupt.
  */
 int
 ixl_teardown_adminq_msix(struct ixl_pf *pf)
 {
 	device_t		dev = pf->dev;
 	int			rid, error = 0;
 
 	if (pf->admvec) /* we are doing MSIX */
 		rid = pf->admvec + 1;
 	else
 		(pf->msix != 0) ? (rid = 1):(rid = 0);
 
 	if (pf->tag != NULL) {
 		bus_teardown_intr(dev, pf->res, pf->tag);
 		if (error) {
 			device_printf(dev, "bus_teardown_intr() for"
 			    " interrupt 0 failed\n");
 			// return (ENXIO);
 		}
 		pf->tag = NULL;
 	}
 	if (pf->res != NULL) {
 		bus_release_resource(dev, SYS_RES_IRQ, rid, pf->res);
 		if (error) {
 			device_printf(dev, "bus_release_resource() for"
 			    " interrupt 0 failed [rid=%d]\n", rid);
 			// return (ENXIO);
 		}
 		pf->res = NULL;
 	}
 
 	return (0);
 }
 
 int
 ixl_teardown_queue_msix(struct ixl_vsi *vsi)
 {
 	struct ixl_pf		*pf = (struct ixl_pf *)vsi->back;
 	struct ixl_queue	*que = vsi->queues;
 	device_t		dev = vsi->dev;
 	int			rid, error = 0;
 
 	/* We may get here before stations are setup */
 	if ((pf->msix < 2) || (que == NULL))
 		return (0);
 
 	/* Release all MSIX queue resources */
 	for (int i = 0; i < vsi->num_queues; i++, que++) {
 		rid = que->msix + 1;
 		if (que->tag != NULL) {
 			error = bus_teardown_intr(dev, que->res, que->tag);
 			if (error) {
 				device_printf(dev, "bus_teardown_intr() for"
 				    " Queue %d interrupt failed\n",
 				    que->me);
 				// return (ENXIO);
 			}
 			que->tag = NULL;
 		}
 		if (que->res != NULL) {
 			error = bus_release_resource(dev, SYS_RES_IRQ, rid, que->res);
 			if (error) {
 				device_printf(dev, "bus_release_resource() for"
 				    " Queue %d interrupt failed [rid=%d]\n",
 				    que->me, rid);
 				// return (ENXIO);
 			}
 			que->res = NULL;
 		}
 	}
 
 	return (0);
 }
 
 void
 ixl_free_pci_resources(struct ixl_pf *pf)
 {
 	device_t		dev = pf->dev;
 	int			memrid;
 
 	ixl_teardown_queue_msix(&pf->vsi);
 	ixl_teardown_adminq_msix(pf);
 
 	if (pf->msix > 0)
 		pci_release_msi(dev);
 	
 	memrid = PCIR_BAR(IXL_MSIX_BAR);
 
 	if (pf->msix_mem != NULL)
 		bus_release_resource(dev, SYS_RES_MEMORY,
 		    memrid, pf->msix_mem);
 
 	if (pf->pci_mem != NULL)
 		bus_release_resource(dev, SYS_RES_MEMORY,
 		    PCIR_BAR(0), pf->pci_mem);
 
 	return;
 }
 
 void
 ixl_add_ifmedia(struct ixl_vsi *vsi, u64 phy_types)
 {
 	/* Display supported media types */
 	if (phy_types & (I40E_CAP_PHY_TYPE_100BASE_TX))
 		ifmedia_add(&vsi->media, IFM_ETHER | IFM_100_TX, 0, NULL);
 
 	if (phy_types & (I40E_CAP_PHY_TYPE_1000BASE_T))
 		ifmedia_add(&vsi->media, IFM_ETHER | IFM_1000_T, 0, NULL);
 	if (phy_types & (I40E_CAP_PHY_TYPE_1000BASE_SX))
 		ifmedia_add(&vsi->media, IFM_ETHER | IFM_1000_SX, 0, NULL);
 	if (phy_types & (I40E_CAP_PHY_TYPE_1000BASE_LX))
 		ifmedia_add(&vsi->media, IFM_ETHER | IFM_1000_LX, 0, NULL);
 
 	if (phy_types & (I40E_CAP_PHY_TYPE_XAUI) ||
 	    phy_types & (I40E_CAP_PHY_TYPE_XFI) ||
 	    phy_types & (I40E_CAP_PHY_TYPE_10GBASE_SFPP_CU))
 		ifmedia_add(&vsi->media, IFM_ETHER | IFM_10G_TWINAX, 0, NULL);
 
 	if (phy_types & (I40E_CAP_PHY_TYPE_10GBASE_SR))
 		ifmedia_add(&vsi->media, IFM_ETHER | IFM_10G_SR, 0, NULL);
 	if (phy_types & (I40E_CAP_PHY_TYPE_10GBASE_LR))
 		ifmedia_add(&vsi->media, IFM_ETHER | IFM_10G_LR, 0, NULL);
 	if (phy_types & (I40E_CAP_PHY_TYPE_10GBASE_T))
 		ifmedia_add(&vsi->media, IFM_ETHER | IFM_10G_T, 0, NULL);
 
 	if (phy_types & (I40E_CAP_PHY_TYPE_40GBASE_CR4) ||
 	    phy_types & (I40E_CAP_PHY_TYPE_40GBASE_CR4_CU) ||
 	    phy_types & (I40E_CAP_PHY_TYPE_40GBASE_AOC) ||
 	    phy_types & (I40E_CAP_PHY_TYPE_XLAUI) ||
 	    phy_types & (I40E_CAP_PHY_TYPE_40GBASE_KR4))
 		ifmedia_add(&vsi->media, IFM_ETHER | IFM_40G_CR4, 0, NULL);
 	if (phy_types & (I40E_CAP_PHY_TYPE_40GBASE_SR4))
 		ifmedia_add(&vsi->media, IFM_ETHER | IFM_40G_SR4, 0, NULL);
 	if (phy_types & (I40E_CAP_PHY_TYPE_40GBASE_LR4))
 		ifmedia_add(&vsi->media, IFM_ETHER | IFM_40G_LR4, 0, NULL);
 
 	if (phy_types & (I40E_CAP_PHY_TYPE_1000BASE_KX))
 		ifmedia_add(&vsi->media, IFM_ETHER | IFM_1000_KX, 0, NULL);
 
 	if (phy_types & (I40E_CAP_PHY_TYPE_10GBASE_CR1_CU)
 	    || phy_types & (I40E_CAP_PHY_TYPE_10GBASE_CR1))
 		ifmedia_add(&vsi->media, IFM_ETHER | IFM_10G_CR1, 0, NULL);
 	if (phy_types & (I40E_CAP_PHY_TYPE_10GBASE_AOC))
 		ifmedia_add(&vsi->media, IFM_ETHER | IFM_10G_TWINAX_LONG, 0, NULL);
 	if (phy_types & (I40E_CAP_PHY_TYPE_SFI))
 		ifmedia_add(&vsi->media, IFM_ETHER | IFM_10G_SFI, 0, NULL);
 	if (phy_types & (I40E_CAP_PHY_TYPE_10GBASE_KX4))
 		ifmedia_add(&vsi->media, IFM_ETHER | IFM_10G_KX4, 0, NULL);
 	if (phy_types & (I40E_CAP_PHY_TYPE_10GBASE_KR))
 		ifmedia_add(&vsi->media, IFM_ETHER | IFM_10G_KR, 0, NULL);
 
 	if (phy_types & (I40E_CAP_PHY_TYPE_20GBASE_KR2))
 		ifmedia_add(&vsi->media, IFM_ETHER | IFM_20G_KR2, 0, NULL);
 
 	if (phy_types & (I40E_CAP_PHY_TYPE_40GBASE_KR4))
 		ifmedia_add(&vsi->media, IFM_ETHER | IFM_40G_KR4, 0, NULL);
 	if (phy_types & (I40E_CAP_PHY_TYPE_XLPPI))
 		ifmedia_add(&vsi->media, IFM_ETHER | IFM_40G_XLPPI, 0, NULL);
 
 	if (phy_types & (I40E_CAP_PHY_TYPE_25GBASE_KR))
 		ifmedia_add(&vsi->media, IFM_ETHER | IFM_25G_KR, 0, NULL);
 	if (phy_types & (I40E_CAP_PHY_TYPE_25GBASE_CR))
 		ifmedia_add(&vsi->media, IFM_ETHER | IFM_25G_CR, 0, NULL);
 	if (phy_types & (I40E_CAP_PHY_TYPE_25GBASE_SR))
 		ifmedia_add(&vsi->media, IFM_ETHER | IFM_25G_SR, 0, NULL);
 	if (phy_types & (I40E_CAP_PHY_TYPE_25GBASE_LR))
 		ifmedia_add(&vsi->media, IFM_ETHER | IFM_UNKNOWN, 0, NULL);
 }
 
 /*********************************************************************
  *
  *  Setup networking device structure and register an interface.
  *
  **********************************************************************/
 int
 ixl_setup_interface(device_t dev, struct ixl_vsi *vsi)
 {
 	struct ixl_pf		*pf = (struct ixl_pf *)vsi->back;
 	struct ifnet		*ifp;
 	struct i40e_hw		*hw = vsi->hw;
 	struct ixl_queue	*que = vsi->queues;
 	struct i40e_aq_get_phy_abilities_resp abilities;
 	enum i40e_status_code aq_error = 0;
 
 	INIT_DEBUGOUT("ixl_setup_interface: begin");
 
 	ifp = vsi->ifp = if_alloc(IFT_ETHER);
 	if (ifp == NULL) {
 		device_printf(dev, "can not allocate ifnet structure\n");
 		return (-1);
 	}
 	if_initname(ifp, device_get_name(dev), device_get_unit(dev));
 	ifp->if_mtu = ETHERMTU;
 	ifp->if_init = ixl_init;
 	ifp->if_softc = vsi;
 	ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
 	ifp->if_ioctl = ixl_ioctl;
 
 #if __FreeBSD_version >= 1100036
 	if_setgetcounterfn(ifp, ixl_get_counter);
 #endif
 
 	ifp->if_transmit = ixl_mq_start;
 
 	ifp->if_qflush = ixl_qflush;
 
 	ifp->if_snd.ifq_maxlen = que->num_desc - 2;
 
 	vsi->max_frame_size =
 	    ifp->if_mtu + ETHER_HDR_LEN + ETHER_CRC_LEN
 	    + ETHER_VLAN_ENCAP_LEN;
 
 	/* Set TSO limits */
 	ifp->if_hw_tsomax = IP_MAXPACKET - (ETHER_HDR_LEN + ETHER_CRC_LEN);
 	ifp->if_hw_tsomaxsegcount = IXL_MAX_TSO_SEGS;
 	ifp->if_hw_tsomaxsegsize = PAGE_SIZE;
 
 	/*
 	 * Tell the upper layer(s) we support long frames.
 	 */
 	ifp->if_hdrlen = sizeof(struct ether_vlan_header);
 
 	ifp->if_capabilities |= IFCAP_HWCSUM;
 	ifp->if_capabilities |= IFCAP_HWCSUM_IPV6;
 	ifp->if_capabilities |= IFCAP_TSO;
 	ifp->if_capabilities |= IFCAP_JUMBO_MTU;
 	ifp->if_capabilities |= IFCAP_LRO;
 
 	/* VLAN capabilties */
 	ifp->if_capabilities |= IFCAP_VLAN_HWTAGGING
 			     |  IFCAP_VLAN_HWTSO
 			     |  IFCAP_VLAN_MTU
 			     |  IFCAP_VLAN_HWCSUM;
 	ifp->if_capenable = ifp->if_capabilities;
 
 	/*
 	** Don't turn this on by default, if vlans are
 	** created on another pseudo device (eg. lagg)
 	** then vlan events are not passed thru, breaking
 	** operation, but with HW FILTER off it works. If
 	** using vlans directly on the ixl driver you can
 	** enable this and get full hardware tag filtering.
 	*/
 	ifp->if_capabilities |= IFCAP_VLAN_HWFILTER;
 
 	/*
 	 * Specify the media types supported by this adapter and register
 	 * callbacks to update media and link information
 	 */
 	ifmedia_init(&vsi->media, IFM_IMASK, ixl_media_change,
 		     ixl_media_status);
 
 	aq_error = i40e_aq_get_phy_capabilities(hw,
 	    FALSE, TRUE, &abilities, NULL);
 	/* May need delay to detect fiber correctly */
 	if (aq_error == I40E_ERR_UNKNOWN_PHY) {
 		i40e_msec_delay(200);
 		aq_error = i40e_aq_get_phy_capabilities(hw, FALSE,
 		    TRUE, &abilities, NULL);
 	}
 	if (aq_error) {
 		if (aq_error == I40E_ERR_UNKNOWN_PHY)
 			device_printf(dev, "Unknown PHY type detected!\n");
 		else
 			device_printf(dev,
 			    "Error getting supported media types, err %d,"
 			    " AQ error %d\n", aq_error, hw->aq.asq_last_status);
 		return (0);
 	}
 	pf->supported_speeds = abilities.link_speed;
 	ifp->if_baudrate = ixl_max_aq_speed_to_value(pf->supported_speeds);
 
 	ixl_add_ifmedia(vsi, hw->phy.phy_types);
 
 	/* Use autoselect media by default */
 	ifmedia_add(&vsi->media, IFM_ETHER | IFM_AUTO, 0, NULL);
 	ifmedia_set(&vsi->media, IFM_ETHER | IFM_AUTO);
 
 	ether_ifattach(ifp, hw->mac.addr);
 
 	return (0);
 }
 
 /*
 ** Run when the Admin Queue gets a link state change interrupt.
 */
 void
 ixl_link_event(struct ixl_pf *pf, struct i40e_arq_event_info *e)
 {
 	struct i40e_hw	*hw = &pf->hw; 
 	device_t dev = pf->dev;
 	struct i40e_aqc_get_link_status *status =
 	    (struct i40e_aqc_get_link_status *)&e->desc.params.raw;
 
 	/* Request link status from adapter */
 	hw->phy.get_link_info = TRUE;
 	i40e_get_link_status(hw, &pf->link_up);
 
 	/* Print out message if an unqualified module is found */
 	if ((status->link_info & I40E_AQ_MEDIA_AVAILABLE) &&
 	    (!(status->an_info & I40E_AQ_QUALIFIED_MODULE)) &&
 	    (!(status->link_info & I40E_AQ_LINK_UP)))
 		device_printf(dev, "Link failed because "
 		    "an unqualified module was detected!\n");
 
 	/* Update OS link info */
 	ixl_update_link_status(pf);
 }
 
 /*********************************************************************
  *
  *  Get Firmware Switch configuration
  *	- this will need to be more robust when more complex
  *	  switch configurations are enabled.
  *
  **********************************************************************/
 int
 ixl_switch_config(struct ixl_pf *pf)
 {
 	struct i40e_hw	*hw = &pf->hw; 
 	struct ixl_vsi	*vsi = &pf->vsi;
 	device_t 	dev = vsi->dev;
 	struct i40e_aqc_get_switch_config_resp *sw_config;
 	u8	aq_buf[I40E_AQ_LARGE_BUF];
 	int	ret;
 	u16	next = 0;
 
 	memset(&aq_buf, 0, sizeof(aq_buf));
 	sw_config = (struct i40e_aqc_get_switch_config_resp *)aq_buf;
 	ret = i40e_aq_get_switch_config(hw, sw_config,
 	    sizeof(aq_buf), &next, NULL);
 	if (ret) {
 		device_printf(dev, "aq_get_switch_config() failed, error %d,"
 		    " aq_error %d\n", ret, pf->hw.aq.asq_last_status);
 		return (ret);
 	}
 	if (pf->dbg_mask & IXL_DBG_SWITCH_INFO) {
 		device_printf(dev,
 		    "Switch config: header reported: %d in structure, %d total\n",
 		    sw_config->header.num_reported, sw_config->header.num_total);
 		for (int i = 0; i < sw_config->header.num_reported; i++) {
 			device_printf(dev,
 			    "-> %d: type=%d seid=%d uplink=%d downlink=%d\n", i,
 			    sw_config->element[i].element_type,
 			    sw_config->element[i].seid,
 			    sw_config->element[i].uplink_seid,
 			    sw_config->element[i].downlink_seid);
 		}
 	}
 	/* Simplified due to a single VSI */
 	vsi->uplink_seid = sw_config->element[0].uplink_seid;
 	vsi->downlink_seid = sw_config->element[0].downlink_seid;
 	vsi->seid = sw_config->element[0].seid;
 	return (ret);
 }
 
 /*********************************************************************
  *
  *  Initialize the VSI:  this handles contexts, which means things
  *  			 like the number of descriptors, buffer size,
  *			 plus we init the rings thru this function.
  *
  **********************************************************************/
 int
 ixl_initialize_vsi(struct ixl_vsi *vsi)
 {
 	struct ixl_pf		*pf = vsi->back;
 	struct ixl_queue	*que = vsi->queues;
 	device_t		dev = vsi->dev;
 	struct i40e_hw		*hw = vsi->hw;
 	struct i40e_vsi_context	ctxt;
 	int 			tc_queues;
 	int			err = 0;
 
 	memset(&ctxt, 0, sizeof(ctxt));
 	ctxt.seid = vsi->seid;
 	if (pf->veb_seid != 0)
 		ctxt.uplink_seid = pf->veb_seid;
 	ctxt.pf_num = hw->pf_id;
 	err = i40e_aq_get_vsi_params(hw, &ctxt, NULL);
 	if (err) {
 		device_printf(dev, "i40e_aq_get_vsi_params() failed, error %d"
 		    " aq_error %d\n", err, hw->aq.asq_last_status);
 		return (err);
 	}
 	ixl_dbg(pf, IXL_DBG_SWITCH_INFO,
 	    "get_vsi_params: seid: %d, uplinkseid: %d, vsi_number: %d, "
 	    "vsis_allocated: %d, vsis_unallocated: %d, flags: 0x%x, "
 	    "pfnum: %d, vfnum: %d, stat idx: %d, enabled: %d\n", ctxt.seid,
 	    ctxt.uplink_seid, ctxt.vsi_number,
 	    ctxt.vsis_allocated, ctxt.vsis_unallocated,
 	    ctxt.flags, ctxt.pf_num, ctxt.vf_num,
 	    ctxt.info.stat_counter_idx, ctxt.info.up_enable_bits);
 	/*
 	** Set the queue and traffic class bits
 	**  - when multiple traffic classes are supported
 	**    this will need to be more robust.
 	*/
 	ctxt.info.valid_sections = I40E_AQ_VSI_PROP_QUEUE_MAP_VALID;
 	ctxt.info.mapping_flags |= I40E_AQ_VSI_QUE_MAP_CONTIG;
 	/* In contig mode, que_mapping[0] is first queue index used by this VSI */
 	ctxt.info.queue_mapping[0] = 0;
 	/*
 	 * This VSI will only use traffic class 0; start traffic class 0's
 	 * queue allocation at queue 0, and assign it 2^tc_queues queues (though
 	 * the driver may not use all of them).
 	 */
 	tc_queues = bsrl(pf->qtag.num_allocated);
 	ctxt.info.tc_mapping[0] = ((0 << I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT)
 	    & I40E_AQ_VSI_TC_QUE_OFFSET_MASK) |
 	    ((tc_queues << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT)
 	    & I40E_AQ_VSI_TC_QUE_NUMBER_MASK);
 
 	/* Set VLAN receive stripping mode */
 	ctxt.info.valid_sections |= I40E_AQ_VSI_PROP_VLAN_VALID;
 	ctxt.info.port_vlan_flags = I40E_AQ_VSI_PVLAN_MODE_ALL;
 	if (vsi->ifp->if_capenable & IFCAP_VLAN_HWTAGGING)
 		ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
 	else
 		ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_EMOD_NOTHING;
 
 #ifdef IXL_IW
 	/* Set TCP Enable for iWARP capable VSI */
 	if (ixl_enable_iwarp && pf->iw_enabled) {
 		ctxt.info.valid_sections |=
 		    htole16(I40E_AQ_VSI_PROP_QUEUE_OPT_VALID);
 		ctxt.info.queueing_opt_flags |= I40E_AQ_VSI_QUE_OPT_TCP_ENA;
 	}
 #endif
 	/* Save VSI number and info for use later */
 	vsi->vsi_num = ctxt.vsi_number;
 	bcopy(&ctxt.info, &vsi->info, sizeof(vsi->info));
 
 	/* Reset VSI statistics */
 	ixl_vsi_reset_stats(vsi);
 	vsi->hw_filters_add = 0;
 	vsi->hw_filters_del = 0;
 
 	ctxt.flags = htole16(I40E_AQ_VSI_TYPE_PF);
 
 	err = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
 	if (err) {
 		device_printf(dev, "i40e_aq_update_vsi_params() failed, error %d,"
 		    " aq_error %d\n", err, hw->aq.asq_last_status);
 		return (err);
 	}
 
 	for (int i = 0; i < vsi->num_queues; i++, que++) {
 		struct tx_ring		*txr = &que->txr;
 		struct rx_ring 		*rxr = &que->rxr;
 		struct i40e_hmc_obj_txq tctx;
 		struct i40e_hmc_obj_rxq rctx;
 		u32			txctl;
 		u16			size;
 
 		/* Setup the HMC TX Context  */
 		size = que->num_desc * sizeof(struct i40e_tx_desc);
 		memset(&tctx, 0, sizeof(struct i40e_hmc_obj_txq));
 		tctx.new_context = 1;
 		tctx.base = (txr->dma.pa/IXL_TX_CTX_BASE_UNITS);
 		tctx.qlen = que->num_desc;
 		tctx.fc_ena = 0;
 		tctx.rdylist = vsi->info.qs_handle[0]; /* index is TC */
 		/* Enable HEAD writeback */
 		tctx.head_wb_ena = 1;
 		tctx.head_wb_addr = txr->dma.pa +
 		    (que->num_desc * sizeof(struct i40e_tx_desc));
 		tctx.rdylist_act = 0;
 		err = i40e_clear_lan_tx_queue_context(hw, i);
 		if (err) {
 			device_printf(dev, "Unable to clear TX context\n");
 			break;
 		}
 		err = i40e_set_lan_tx_queue_context(hw, i, &tctx);
 		if (err) {
 			device_printf(dev, "Unable to set TX context\n");
 			break;
 		}
 		/* Associate the ring with this PF */
 		txctl = I40E_QTX_CTL_PF_QUEUE;
 		txctl |= ((hw->pf_id << I40E_QTX_CTL_PF_INDX_SHIFT) &
 		    I40E_QTX_CTL_PF_INDX_MASK);
 		wr32(hw, I40E_QTX_CTL(i), txctl);
 		ixl_flush(hw);
 
 		/* Do ring (re)init */
 		ixl_init_tx_ring(que);
 
 		/* Next setup the HMC RX Context  */
 		if (vsi->max_frame_size <= MCLBYTES)
 			rxr->mbuf_sz = MCLBYTES;
 		else
 			rxr->mbuf_sz = MJUMPAGESIZE;
 
 		u16 max_rxmax = rxr->mbuf_sz * hw->func_caps.rx_buf_chain_len;
 
 		/* Set up an RX context for the HMC */
 		memset(&rctx, 0, sizeof(struct i40e_hmc_obj_rxq));
 		rctx.dbuff = rxr->mbuf_sz >> I40E_RXQ_CTX_DBUFF_SHIFT;
 		/* ignore header split for now */
 		rctx.hbuff = 0 >> I40E_RXQ_CTX_HBUFF_SHIFT;
 		rctx.rxmax = (vsi->max_frame_size < max_rxmax) ?
 		    vsi->max_frame_size : max_rxmax;
 		rctx.dtype = 0;
 		rctx.dsize = 1;	/* do 32byte descriptors */
 		rctx.hsplit_0 = 0;  /* no HDR split initially */
 		rctx.base = (rxr->dma.pa/IXL_RX_CTX_BASE_UNITS);
 		rctx.qlen = que->num_desc;
 		rctx.tphrdesc_ena = 1;
 		rctx.tphwdesc_ena = 1;
 		rctx.tphdata_ena = 0;
 		rctx.tphhead_ena = 0;
 		rctx.lrxqthresh = 2;
 		rctx.crcstrip = 1;
 		rctx.l2tsel = 1;
 		rctx.showiv = 1;
 		rctx.fc_ena = 0;
 		rctx.prefena = 1;
 
 		err = i40e_clear_lan_rx_queue_context(hw, i);
 		if (err) {
 			device_printf(dev,
 			    "Unable to clear RX context %d\n", i);
 			break;
 		}
 		err = i40e_set_lan_rx_queue_context(hw, i, &rctx);
 		if (err) {
 			device_printf(dev, "Unable to set RX context %d\n", i);
 			break;
 		}
 		err = ixl_init_rx_ring(que);
 		if (err) {
 			device_printf(dev, "Fail in init_rx_ring %d\n", i);
 			break;
 		}
 #ifdef DEV_NETMAP
 		/* preserve queue */
 		if (vsi->ifp->if_capenable & IFCAP_NETMAP) {
 			struct netmap_adapter *na = NA(vsi->ifp);
 			struct netmap_kring *kring = &na->rx_rings[i];
 			int t = na->num_rx_desc - 1 - nm_kr_rxspace(kring);
 			wr32(vsi->hw, I40E_QRX_TAIL(que->me), t);
 		} else
 #endif /* DEV_NETMAP */
 		wr32(vsi->hw, I40E_QRX_TAIL(que->me), que->num_desc - 1);
 	}
 	return (err);
 }
 
 
 /*********************************************************************
  *
  *  Free all VSI structs.
  *
  **********************************************************************/
 void
 ixl_free_vsi(struct ixl_vsi *vsi)
 {
 	struct ixl_pf		*pf = (struct ixl_pf *)vsi->back;
 	struct ixl_queue	*que = vsi->queues;
 
 	/* Free station queues */
 	if (!vsi->queues)
 		goto free_filters;
 
 	for (int i = 0; i < vsi->num_queues; i++, que++) {
 		struct tx_ring *txr = &que->txr;
 		struct rx_ring *rxr = &que->rxr;
 	
 		if (!mtx_initialized(&txr->mtx)) /* uninitialized */
 			continue;
 		IXL_TX_LOCK(txr);
 		ixl_free_que_tx(que);
 		if (txr->base)
 			i40e_free_dma_mem(&pf->hw, &txr->dma);
 		IXL_TX_UNLOCK(txr);
 		IXL_TX_LOCK_DESTROY(txr);
 
 		if (!mtx_initialized(&rxr->mtx)) /* uninitialized */
 			continue;
 		IXL_RX_LOCK(rxr);
 		ixl_free_que_rx(que);
 		if (rxr->base)
 			i40e_free_dma_mem(&pf->hw, &rxr->dma);
 		IXL_RX_UNLOCK(rxr);
 		IXL_RX_LOCK_DESTROY(rxr);
 	}
 	free(vsi->queues, M_DEVBUF);
 
 free_filters:
 	/* Free VSI filter list */
 	ixl_free_mac_filters(vsi);
 }
 
 void
 ixl_free_mac_filters(struct ixl_vsi *vsi)
 {
 	struct ixl_mac_filter *f;
 
 	while (!SLIST_EMPTY(&vsi->ftl)) {
 		f = SLIST_FIRST(&vsi->ftl);
 		SLIST_REMOVE_HEAD(&vsi->ftl, next);
 		free(f, M_DEVBUF);
 	}
 }
 
 /*
  * Fill out fields in queue struct and setup tx/rx memory and structs
  */
 static int
 ixl_setup_queue(struct ixl_queue *que, struct ixl_pf *pf, int index)
 {
 	device_t dev = pf->dev;
 	struct i40e_hw *hw = &pf->hw;
 	struct ixl_vsi *vsi = &pf->vsi;
 	struct tx_ring *txr = &que->txr;
 	struct rx_ring *rxr = &que->rxr;
 	int error = 0;
 	int rsize, tsize;
 
 	que->num_desc = pf->ringsz;
 	que->me = index;
 	que->vsi = vsi;
 
 	txr->que = que;
 	txr->tail = I40E_QTX_TAIL(que->me);
 
 	/* Initialize the TX lock */
 	snprintf(txr->mtx_name, sizeof(txr->mtx_name), "%s:tx(%d)",
 	    device_get_nameunit(dev), que->me);
 	mtx_init(&txr->mtx, txr->mtx_name, NULL, MTX_DEF);
 	/* Create the TX descriptor ring */
 	tsize = roundup2((que->num_desc *
 	    sizeof(struct i40e_tx_desc)) +
 	    sizeof(u32), DBA_ALIGN);
 	if (i40e_allocate_dma_mem(hw,
 	    &txr->dma, i40e_mem_reserved, tsize, DBA_ALIGN)) {
 		device_printf(dev,
 		    "Unable to allocate TX Descriptor memory\n");
 		error = ENOMEM;
 		goto fail;
 	}
 	txr->base = (struct i40e_tx_desc *)txr->dma.va;
 	bzero((void *)txr->base, tsize);
 	/* Now allocate transmit soft structs for the ring */
 	if (ixl_allocate_tx_data(que)) {
 		device_printf(dev,
 		    "Critical Failure setting up TX structures\n");
 		error = ENOMEM;
 		goto fail;
 	}
 	/* Allocate a buf ring */
 	txr->br = buf_ring_alloc(DEFAULT_TXBRSZ, M_DEVBUF,
 	    M_NOWAIT, &txr->mtx);
 	if (txr->br == NULL) {
 		device_printf(dev,
 		    "Critical Failure setting up TX buf ring\n");
 		error = ENOMEM;
 		goto fail;
 	}
 
 	rsize = roundup2(que->num_desc *
 	    sizeof(union i40e_rx_desc), DBA_ALIGN);
 	rxr->que = que;
 	rxr->tail = I40E_QRX_TAIL(que->me);
 
 	/* Initialize the RX side lock */
 	snprintf(rxr->mtx_name, sizeof(rxr->mtx_name), "%s:rx(%d)",
 	    device_get_nameunit(dev), que->me);
 	mtx_init(&rxr->mtx, rxr->mtx_name, NULL, MTX_DEF);
 
 	if (i40e_allocate_dma_mem(hw,
 	    &rxr->dma, i40e_mem_reserved, rsize, 4096)) {
 		device_printf(dev,
 		    "Unable to allocate RX Descriptor memory\n");
 		error = ENOMEM;
 		goto fail;
 	}
 	rxr->base = (union i40e_rx_desc *)rxr->dma.va;
 	bzero((void *)rxr->base, rsize);
 	/* Allocate receive soft structs for the ring*/
 	if (ixl_allocate_rx_data(que)) {
 		device_printf(dev,
 		    "Critical Failure setting up receive structs\n");
 		error = ENOMEM;
 		goto fail;
 	}
 
 	return (0);
 fail:
 	if (rxr->base)
 		i40e_free_dma_mem(&pf->hw, &rxr->dma);
 	if (mtx_initialized(&rxr->mtx))
 		mtx_destroy(&rxr->mtx);
 	if (txr->br) {
 		buf_ring_free(txr->br, M_DEVBUF);
 		txr->br = NULL;
 	}
 	if (txr->base)
 		i40e_free_dma_mem(&pf->hw, &txr->dma);
 	if (mtx_initialized(&txr->mtx))
 		mtx_destroy(&txr->mtx);
 
 	return (error);
 }
 
 /*********************************************************************
  *
  *  Allocate memory for the VSI (virtual station interface) and their
  *  associated queues, rings and the descriptors associated with each,
  *  called only once at attach.
  *
  **********************************************************************/
 int
 ixl_setup_stations(struct ixl_pf *pf)
 {
 	device_t		dev = pf->dev;
 	struct ixl_vsi		*vsi;
 	struct ixl_queue	*que;
 	int			error = 0;
 
 	vsi = &pf->vsi;
 	vsi->back = (void *)pf;
 	vsi->hw = &pf->hw;
 	vsi->id = 0;
 	vsi->num_vlans = 0;
 	vsi->back = pf;
 
 	/* Get memory for the station queues */
         if (!(vsi->queues =
             (struct ixl_queue *) malloc(sizeof(struct ixl_queue) *
             vsi->num_queues, M_DEVBUF, M_NOWAIT | M_ZERO))) {
                 device_printf(dev, "Unable to allocate queue memory\n");
                 error = ENOMEM;
                 return (error);
         }
 
 	/* Then setup each queue */
 	for (int i = 0; i < vsi->num_queues; i++) {
 		que = &vsi->queues[i];
 		error = ixl_setup_queue(que, pf, i);
 		if (error)
 			return (error);
 	}
 
 	return (0);
 }
 
 /*
 ** Provide a update to the queue RX
 ** interrupt moderation value.
 */
 void
 ixl_set_queue_rx_itr(struct ixl_queue *que)
 {
 	struct ixl_vsi	*vsi = que->vsi;
 	struct ixl_pf	*pf = (struct ixl_pf *)vsi->back;
 	struct i40e_hw	*hw = vsi->hw;
 	struct rx_ring	*rxr = &que->rxr;
 	u16		rx_itr;
 	u16		rx_latency = 0;
 	int		rx_bytes;
 
 	/* Idle, do nothing */
 	if (rxr->bytes == 0)
 		return;
 
 	if (pf->dynamic_rx_itr) {
 		rx_bytes = rxr->bytes/rxr->itr;
 		rx_itr = rxr->itr;
 
 		/* Adjust latency range */
 		switch (rxr->latency) {
 		case IXL_LOW_LATENCY:
 			if (rx_bytes > 10) {
 				rx_latency = IXL_AVE_LATENCY;
 				rx_itr = IXL_ITR_20K;
 			}
 			break;
 		case IXL_AVE_LATENCY:
 			if (rx_bytes > 20) {
 				rx_latency = IXL_BULK_LATENCY;
 				rx_itr = IXL_ITR_8K;
 			} else if (rx_bytes <= 10) {
 				rx_latency = IXL_LOW_LATENCY;
 				rx_itr = IXL_ITR_100K;
 			}
 			break;
 		case IXL_BULK_LATENCY:
 			if (rx_bytes <= 20) {
 				rx_latency = IXL_AVE_LATENCY;
 				rx_itr = IXL_ITR_20K;
 			}
 			break;
        		 }
 
 		rxr->latency = rx_latency;
 
 		if (rx_itr != rxr->itr) {
 			/* do an exponential smoothing */
 			rx_itr = (10 * rx_itr * rxr->itr) /
 			    ((9 * rx_itr) + rxr->itr);
 			rxr->itr = min(rx_itr, IXL_MAX_ITR);
 			wr32(hw, I40E_PFINT_ITRN(IXL_RX_ITR,
 			    que->me), rxr->itr);
 		}
 	} else { /* We may have have toggled to non-dynamic */
 		if (vsi->rx_itr_setting & IXL_ITR_DYNAMIC)
 			vsi->rx_itr_setting = pf->rx_itr;
 		/* Update the hardware if needed */
 		if (rxr->itr != vsi->rx_itr_setting) {
 			rxr->itr = vsi->rx_itr_setting;
 			wr32(hw, I40E_PFINT_ITRN(IXL_RX_ITR,
 			    que->me), rxr->itr);
 		}
 	}
 	rxr->bytes = 0;
 	rxr->packets = 0;
 	return;
 }
 
 
 /*
 ** Provide a update to the queue TX
 ** interrupt moderation value.
 */
 void
 ixl_set_queue_tx_itr(struct ixl_queue *que)
 {
 	struct ixl_vsi	*vsi = que->vsi;
 	struct ixl_pf	*pf = (struct ixl_pf *)vsi->back;
 	struct i40e_hw	*hw = vsi->hw;
 	struct tx_ring	*txr = &que->txr;
 	u16		tx_itr;
 	u16		tx_latency = 0;
 	int		tx_bytes;
 
 
 	/* Idle, do nothing */
 	if (txr->bytes == 0)
 		return;
 
 	if (pf->dynamic_tx_itr) {
 		tx_bytes = txr->bytes/txr->itr;
 		tx_itr = txr->itr;
 
 		switch (txr->latency) {
 		case IXL_LOW_LATENCY:
 			if (tx_bytes > 10) {
 				tx_latency = IXL_AVE_LATENCY;
 				tx_itr = IXL_ITR_20K;
 			}
 			break;
 		case IXL_AVE_LATENCY:
 			if (tx_bytes > 20) {
 				tx_latency = IXL_BULK_LATENCY;
 				tx_itr = IXL_ITR_8K;
 			} else if (tx_bytes <= 10) {
 				tx_latency = IXL_LOW_LATENCY;
 				tx_itr = IXL_ITR_100K;
 			}
 			break;
 		case IXL_BULK_LATENCY:
 			if (tx_bytes <= 20) {
 				tx_latency = IXL_AVE_LATENCY;
 				tx_itr = IXL_ITR_20K;
 			}
 			break;
 		}
 
 		txr->latency = tx_latency;
 
 		if (tx_itr != txr->itr) {
        	         /* do an exponential smoothing */
 			tx_itr = (10 * tx_itr * txr->itr) /
 			    ((9 * tx_itr) + txr->itr);
 			txr->itr = min(tx_itr, IXL_MAX_ITR);
 			wr32(hw, I40E_PFINT_ITRN(IXL_TX_ITR,
 			    que->me), txr->itr);
 		}
 
 	} else { /* We may have have toggled to non-dynamic */
 		if (vsi->tx_itr_setting & IXL_ITR_DYNAMIC)
 			vsi->tx_itr_setting = pf->tx_itr;
 		/* Update the hardware if needed */
 		if (txr->itr != vsi->tx_itr_setting) {
 			txr->itr = vsi->tx_itr_setting;
 			wr32(hw, I40E_PFINT_ITRN(IXL_TX_ITR,
 			    que->me), txr->itr);
 		}
 	}
 	txr->bytes = 0;
 	txr->packets = 0;
 	return;
 }
 
 void
 ixl_add_vsi_sysctls(struct ixl_pf *pf, struct ixl_vsi *vsi,
     struct sysctl_ctx_list *ctx, const char *sysctl_name)
 {
 	struct sysctl_oid *tree;
 	struct sysctl_oid_list *child;
 	struct sysctl_oid_list *vsi_list;
 
 	tree = device_get_sysctl_tree(pf->dev);
 	child = SYSCTL_CHILDREN(tree);
 	vsi->vsi_node = SYSCTL_ADD_NODE(ctx, child, OID_AUTO, sysctl_name,
 				   CTLFLAG_RD, NULL, "VSI Number");
 	vsi_list = SYSCTL_CHILDREN(vsi->vsi_node);
 
 	ixl_add_sysctls_eth_stats(ctx, vsi_list, &vsi->eth_stats);
 }
 
 #ifdef IXL_DEBUG
 /**
  * ixl_sysctl_qtx_tail_handler
  * Retrieves I40E_QTX_TAIL value from hardware
  * for a sysctl.
  */
 static int
 ixl_sysctl_qtx_tail_handler(SYSCTL_HANDLER_ARGS)
 {
 	struct ixl_queue *que;
 	int error;
 	u32 val;
 
 	que = ((struct ixl_queue *)oidp->oid_arg1);
 	if (!que) return 0;
 
 	val = rd32(que->vsi->hw, que->txr.tail);
 	error = sysctl_handle_int(oidp, &val, 0, req);
 	if (error || !req->newptr)
 		return error;
 	return (0);
 }
 
 /**
  * ixl_sysctl_qrx_tail_handler
  * Retrieves I40E_QRX_TAIL value from hardware
  * for a sysctl.
  */
 static int
 ixl_sysctl_qrx_tail_handler(SYSCTL_HANDLER_ARGS)
 {
 	struct ixl_queue *que;
 	int error;
 	u32 val;
 
 	que = ((struct ixl_queue *)oidp->oid_arg1);
 	if (!que) return 0;
 
 	val = rd32(que->vsi->hw, que->rxr.tail);
 	error = sysctl_handle_int(oidp, &val, 0, req);
 	if (error || !req->newptr)
 		return error;
 	return (0);
 }
 #endif
 
 /*
  * Used to set the Tx ITR value for all of the PF LAN VSI's queues.
  * Writes to the ITR registers immediately.
  */
 static int
 ixl_sysctl_pf_tx_itr(SYSCTL_HANDLER_ARGS)
 {
 	struct ixl_pf *pf = (struct ixl_pf *)arg1;
 	device_t dev = pf->dev;
 	int error = 0;
 	int requested_tx_itr;
 
 	requested_tx_itr = pf->tx_itr;
 	error = sysctl_handle_int(oidp, &requested_tx_itr, 0, req);
 	if ((error) || (req->newptr == NULL))
 		return (error);
 	if (pf->dynamic_tx_itr) {
 		device_printf(dev,
 		    "Cannot set TX itr value while dynamic TX itr is enabled\n");
 		    return (EINVAL);
 	}
 	if (requested_tx_itr < 0 || requested_tx_itr > IXL_MAX_ITR) {
 		device_printf(dev,
 		    "Invalid TX itr value; value must be between 0 and %d\n",
 		        IXL_MAX_ITR);
 		return (EINVAL);
 	}
 
 	pf->tx_itr = requested_tx_itr;
 	ixl_configure_tx_itr(pf);
 
 	return (error);
 }
 
 /*
  * Used to set the Rx ITR value for all of the PF LAN VSI's queues.
  * Writes to the ITR registers immediately.
  */
 static int
 ixl_sysctl_pf_rx_itr(SYSCTL_HANDLER_ARGS)
 {
 	struct ixl_pf *pf = (struct ixl_pf *)arg1;
 	device_t dev = pf->dev;
 	int error = 0;
 	int requested_rx_itr;
 
 	requested_rx_itr = pf->rx_itr;
 	error = sysctl_handle_int(oidp, &requested_rx_itr, 0, req);
 	if ((error) || (req->newptr == NULL))
 		return (error);
 	if (pf->dynamic_rx_itr) {
 		device_printf(dev,
 		    "Cannot set RX itr value while dynamic RX itr is enabled\n");
 		    return (EINVAL);
 	}
 	if (requested_rx_itr < 0 || requested_rx_itr > IXL_MAX_ITR) {
 		device_printf(dev,
 		    "Invalid RX itr value; value must be between 0 and %d\n",
 		        IXL_MAX_ITR);
 		return (EINVAL);
 	}
 
 	pf->rx_itr = requested_rx_itr;
 	ixl_configure_rx_itr(pf);
 
 	return (error);
 }
 
 void
 ixl_add_hw_stats(struct ixl_pf *pf)
 {
 	device_t dev = pf->dev;
 	struct ixl_vsi *vsi = &pf->vsi;
 	struct ixl_queue *queues = vsi->queues;
 	struct i40e_hw_port_stats *pf_stats = &pf->stats;
 
 	struct sysctl_ctx_list *ctx = device_get_sysctl_ctx(dev);
 	struct sysctl_oid *tree = device_get_sysctl_tree(dev);
 	struct sysctl_oid_list *child = SYSCTL_CHILDREN(tree);
 	struct sysctl_oid_list *vsi_list;
 
 	struct sysctl_oid *queue_node;
 	struct sysctl_oid_list *queue_list;
 
 	struct tx_ring *txr;
 	struct rx_ring *rxr;
 	char queue_namebuf[QUEUE_NAME_LEN];
 
 	/* Driver statistics */
 	SYSCTL_ADD_ULONG(ctx, child, OID_AUTO, "watchdog_events",
 			CTLFLAG_RD, &pf->watchdog_events,
 			"Watchdog timeouts");
 	SYSCTL_ADD_ULONG(ctx, child, OID_AUTO, "admin_irq",
 			CTLFLAG_RD, &pf->admin_irq,
 			"Admin Queue IRQ Handled");
 
 	ixl_add_vsi_sysctls(pf, &pf->vsi, ctx, "pf");
 	vsi_list = SYSCTL_CHILDREN(pf->vsi.vsi_node);
 
 	/* Queue statistics */
 	for (int q = 0; q < vsi->num_queues; q++) {
 		snprintf(queue_namebuf, QUEUE_NAME_LEN, "que%d", q);
 		queue_node = SYSCTL_ADD_NODE(ctx, vsi_list,
 		    OID_AUTO, queue_namebuf, CTLFLAG_RD, NULL, "Queue #");
 		queue_list = SYSCTL_CHILDREN(queue_node);
 
 		txr = &(queues[q].txr);
 		rxr = &(queues[q].rxr);
 
 		SYSCTL_ADD_UQUAD(ctx, queue_list, OID_AUTO, "mbuf_defrag_failed",
 				CTLFLAG_RD, &(queues[q].mbuf_defrag_failed),
 				"m_defrag() failed");
 		SYSCTL_ADD_UQUAD(ctx, queue_list, OID_AUTO, "irqs",
 				CTLFLAG_RD, &(queues[q].irqs),
 				"irqs on this queue");
 		SYSCTL_ADD_UQUAD(ctx, queue_list, OID_AUTO, "tso_tx",
 				CTLFLAG_RD, &(queues[q].tso),
 				"TSO");
 		SYSCTL_ADD_UQUAD(ctx, queue_list, OID_AUTO, "tx_dmamap_failed",
 				CTLFLAG_RD, &(queues[q].tx_dmamap_failed),
 				"Driver tx dma failure in xmit");
 		SYSCTL_ADD_UQUAD(ctx, queue_list, OID_AUTO, "mss_too_small",
 				CTLFLAG_RD, &(queues[q].mss_too_small),
 				"TSO sends with an MSS less than 64");
 		SYSCTL_ADD_UQUAD(ctx, queue_list, OID_AUTO, "no_desc_avail",
 				CTLFLAG_RD, &(txr->no_desc),
 				"Queue No Descriptor Available");
 		SYSCTL_ADD_UQUAD(ctx, queue_list, OID_AUTO, "tx_packets",
 				CTLFLAG_RD, &(txr->total_packets),
 				"Queue Packets Transmitted");
 		SYSCTL_ADD_UQUAD(ctx, queue_list, OID_AUTO, "tx_bytes",
 				CTLFLAG_RD, &(txr->tx_bytes),
 				"Queue Bytes Transmitted");
 		SYSCTL_ADD_UQUAD(ctx, queue_list, OID_AUTO, "rx_packets",
 				CTLFLAG_RD, &(rxr->rx_packets),
 				"Queue Packets Received");
 		SYSCTL_ADD_UQUAD(ctx, queue_list, OID_AUTO, "rx_bytes",
 				CTLFLAG_RD, &(rxr->rx_bytes),
 				"Queue Bytes Received");
 		SYSCTL_ADD_UQUAD(ctx, queue_list, OID_AUTO, "rx_desc_err",
 				CTLFLAG_RD, &(rxr->desc_errs),
 				"Queue Rx Descriptor Errors");
 		SYSCTL_ADD_UINT(ctx, queue_list, OID_AUTO, "rx_itr",
 				CTLFLAG_RD, &(rxr->itr), 0,
 				"Queue Rx ITR Interval");
 		SYSCTL_ADD_UINT(ctx, queue_list, OID_AUTO, "tx_itr",
 				CTLFLAG_RD, &(txr->itr), 0,
 				"Queue Tx ITR Interval");
 #ifdef IXL_DEBUG
 		SYSCTL_ADD_UQUAD(ctx, queue_list, OID_AUTO, "rx_not_done",
 				CTLFLAG_RD, &(rxr->not_done),
 				"Queue Rx Descriptors not Done");
 		SYSCTL_ADD_UINT(ctx, queue_list, OID_AUTO, "rx_next_refresh",
 				CTLFLAG_RD, &(rxr->next_refresh), 0,
 				"Queue Rx Descriptors not Done");
 		SYSCTL_ADD_UINT(ctx, queue_list, OID_AUTO, "rx_next_check",
 				CTLFLAG_RD, &(rxr->next_check), 0,
 				"Queue Rx Descriptors not Done");
 		SYSCTL_ADD_PROC(ctx, queue_list, OID_AUTO, "qtx_tail", 
 				CTLTYPE_UINT | CTLFLAG_RD, &queues[q],
 				sizeof(struct ixl_queue),
 				ixl_sysctl_qtx_tail_handler, "IU",
 				"Queue Transmit Descriptor Tail");
 		SYSCTL_ADD_PROC(ctx, queue_list, OID_AUTO, "qrx_tail", 
 				CTLTYPE_UINT | CTLFLAG_RD, &queues[q],
 				sizeof(struct ixl_queue),
 				ixl_sysctl_qrx_tail_handler, "IU",
 				"Queue Receive Descriptor Tail");
 #endif
 	}
 
 	/* MAC stats */
 	ixl_add_sysctls_mac_stats(ctx, child, pf_stats);
 }
 
 void
 ixl_add_sysctls_eth_stats(struct sysctl_ctx_list *ctx,
 	struct sysctl_oid_list *child,
 	struct i40e_eth_stats *eth_stats)
 {
 	struct ixl_sysctl_info ctls[] =
 	{
 		{&eth_stats->rx_bytes, "good_octets_rcvd", "Good Octets Received"},
 		{&eth_stats->rx_unicast, "ucast_pkts_rcvd",
 			"Unicast Packets Received"},
 		{&eth_stats->rx_multicast, "mcast_pkts_rcvd",
 			"Multicast Packets Received"},
 		{&eth_stats->rx_broadcast, "bcast_pkts_rcvd",
 			"Broadcast Packets Received"},
 		{&eth_stats->rx_discards, "rx_discards", "Discarded RX packets"},
 		{&eth_stats->tx_bytes, "good_octets_txd", "Good Octets Transmitted"},
 		{&eth_stats->tx_unicast, "ucast_pkts_txd", "Unicast Packets Transmitted"},
 		{&eth_stats->tx_multicast, "mcast_pkts_txd",
 			"Multicast Packets Transmitted"},
 		{&eth_stats->tx_broadcast, "bcast_pkts_txd",
 			"Broadcast Packets Transmitted"},
 		// end
 		{0,0,0}
 	};
 
 	struct ixl_sysctl_info *entry = ctls;
 	while (entry->stat != 0)
 	{
 		SYSCTL_ADD_UQUAD(ctx, child, OID_AUTO, entry->name,
 				CTLFLAG_RD, entry->stat,
 				entry->description);
 		entry++;
 	}
 }
 
 void
 ixl_add_sysctls_mac_stats(struct sysctl_ctx_list *ctx,
 	struct sysctl_oid_list *child,
 	struct i40e_hw_port_stats *stats)
 {
 	struct sysctl_oid *stat_node = SYSCTL_ADD_NODE(ctx, child, OID_AUTO, "mac",
 				    CTLFLAG_RD, NULL, "Mac Statistics");
 	struct sysctl_oid_list *stat_list = SYSCTL_CHILDREN(stat_node);
 
 	struct i40e_eth_stats *eth_stats = &stats->eth;
 	ixl_add_sysctls_eth_stats(ctx, stat_list, eth_stats);
 
 	struct ixl_sysctl_info ctls[] = 
 	{
 		{&stats->crc_errors, "crc_errors", "CRC Errors"},
 		{&stats->illegal_bytes, "illegal_bytes", "Illegal Byte Errors"},
 		{&stats->mac_local_faults, "local_faults", "MAC Local Faults"},
 		{&stats->mac_remote_faults, "remote_faults", "MAC Remote Faults"},
 		{&stats->rx_length_errors, "rx_length_errors", "Receive Length Errors"},
 		/* Packet Reception Stats */
 		{&stats->rx_size_64, "rx_frames_64", "64 byte frames received"},
 		{&stats->rx_size_127, "rx_frames_65_127", "65-127 byte frames received"},
 		{&stats->rx_size_255, "rx_frames_128_255", "128-255 byte frames received"},
 		{&stats->rx_size_511, "rx_frames_256_511", "256-511 byte frames received"},
 		{&stats->rx_size_1023, "rx_frames_512_1023", "512-1023 byte frames received"},
 		{&stats->rx_size_1522, "rx_frames_1024_1522", "1024-1522 byte frames received"},
 		{&stats->rx_size_big, "rx_frames_big", "1523-9522 byte frames received"},
 		{&stats->rx_undersize, "rx_undersize", "Undersized packets received"},
 		{&stats->rx_fragments, "rx_fragmented", "Fragmented packets received"},
 		{&stats->rx_oversize, "rx_oversized", "Oversized packets received"},
 		{&stats->rx_jabber, "rx_jabber", "Received Jabber"},
 		{&stats->checksum_error, "checksum_errors", "Checksum Errors"},
 		/* Packet Transmission Stats */
 		{&stats->tx_size_64, "tx_frames_64", "64 byte frames transmitted"},
 		{&stats->tx_size_127, "tx_frames_65_127", "65-127 byte frames transmitted"},
 		{&stats->tx_size_255, "tx_frames_128_255", "128-255 byte frames transmitted"},
 		{&stats->tx_size_511, "tx_frames_256_511", "256-511 byte frames transmitted"},
 		{&stats->tx_size_1023, "tx_frames_512_1023", "512-1023 byte frames transmitted"},
 		{&stats->tx_size_1522, "tx_frames_1024_1522", "1024-1522 byte frames transmitted"},
 		{&stats->tx_size_big, "tx_frames_big", "1523-9522 byte frames transmitted"},
 		/* Flow control */
 		{&stats->link_xon_tx, "xon_txd", "Link XON transmitted"},
 		{&stats->link_xon_rx, "xon_recvd", "Link XON received"},
 		{&stats->link_xoff_tx, "xoff_txd", "Link XOFF transmitted"},
 		{&stats->link_xoff_rx, "xoff_recvd", "Link XOFF received"},
 		/* End */
 		{0,0,0}
 	};
 
 	struct ixl_sysctl_info *entry = ctls;
 	while (entry->stat != 0)
 	{
 		SYSCTL_ADD_UQUAD(ctx, stat_list, OID_AUTO, entry->name,
 				CTLFLAG_RD, entry->stat,
 				entry->description);
 		entry++;
 	}
 }
 
 void
 ixl_set_rss_key(struct ixl_pf *pf)
 {
 	struct i40e_hw *hw = &pf->hw;
 	struct ixl_vsi *vsi = &pf->vsi;
 	device_t	dev = pf->dev;
 	enum i40e_status_code status;
 #ifdef RSS
 	u32		rss_seed[IXL_RSS_KEY_SIZE_REG];
 #else
 	u32             rss_seed[IXL_RSS_KEY_SIZE_REG] = {0x41b01687,
 			    0x183cfd8c, 0xce880440, 0x580cbc3c,
 			    0x35897377, 0x328b25e1, 0x4fa98922,
 			    0xb7d90c14, 0xd5bad70d, 0xcd15a2c1,
 			    0x0, 0x0, 0x0};
 #endif
 
 #ifdef RSS
         /* Fetch the configured RSS key */
         rss_getkey((uint8_t *) &rss_seed);
 #endif
 	/* Fill out hash function seed */
 	if (hw->mac.type == I40E_MAC_X722) {
 		struct i40e_aqc_get_set_rss_key_data key_data;
 		bcopy(rss_seed, key_data.standard_rss_key, 40);
 		status = i40e_aq_set_rss_key(hw, vsi->vsi_num, &key_data);
 		if (status)
 			device_printf(dev, "i40e_aq_set_rss_key status %s, error %s\n",
 			    i40e_stat_str(hw, status), i40e_aq_str(hw, hw->aq.asq_last_status));
 	} else {
 		for (int i = 0; i < IXL_RSS_KEY_SIZE_REG; i++)
 			i40e_write_rx_ctl(hw, I40E_PFQF_HKEY(i), rss_seed[i]);
 	}
 }
 
 /*
  * Configure enabled PCTYPES for RSS.
  */
 void
 ixl_set_rss_pctypes(struct ixl_pf *pf)
 {
 	struct i40e_hw *hw = &pf->hw;
 	u64		set_hena = 0, hena;
 
 #ifdef RSS
 	u32		rss_hash_config;
 
 	rss_hash_config = rss_gethashconfig();
 	if (rss_hash_config & RSS_HASHTYPE_RSS_IPV4)
                 set_hena |= ((u64)1 << I40E_FILTER_PCTYPE_NONF_IPV4_OTHER);
 	if (rss_hash_config & RSS_HASHTYPE_RSS_TCP_IPV4)
                 set_hena |= ((u64)1 << I40E_FILTER_PCTYPE_NONF_IPV4_TCP);
 	if (rss_hash_config & RSS_HASHTYPE_RSS_UDP_IPV4)
                 set_hena |= ((u64)1 << I40E_FILTER_PCTYPE_NONF_IPV4_UDP);
 	if (rss_hash_config & RSS_HASHTYPE_RSS_IPV6)
                 set_hena |= ((u64)1 << I40E_FILTER_PCTYPE_NONF_IPV6_OTHER);
 	if (rss_hash_config & RSS_HASHTYPE_RSS_IPV6_EX)
 		set_hena |= ((u64)1 << I40E_FILTER_PCTYPE_FRAG_IPV6);
 	if (rss_hash_config & RSS_HASHTYPE_RSS_TCP_IPV6)
                 set_hena |= ((u64)1 << I40E_FILTER_PCTYPE_NONF_IPV6_TCP);
         if (rss_hash_config & RSS_HASHTYPE_RSS_UDP_IPV6)
                 set_hena |= ((u64)1 << I40E_FILTER_PCTYPE_NONF_IPV6_UDP);
 #else
 	if (hw->mac.type == I40E_MAC_X722)
 		set_hena = IXL_DEFAULT_RSS_HENA_X722;
 	else
 		set_hena = IXL_DEFAULT_RSS_HENA_XL710;
 #endif
 	hena = (u64)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0)) |
 	    ((u64)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1)) << 32);
 	hena |= set_hena;
 	i40e_write_rx_ctl(hw, I40E_PFQF_HENA(0), (u32)hena);
 	i40e_write_rx_ctl(hw, I40E_PFQF_HENA(1), (u32)(hena >> 32));
 
 }
 
 void
 ixl_set_rss_hlut(struct ixl_pf *pf)
 {
 	struct i40e_hw	*hw = &pf->hw;
 	device_t	dev = pf->dev;
 	struct ixl_vsi *vsi = &pf->vsi;
 	int		i, que_id;
 	int		lut_entry_width;
 	u32		lut = 0;
 	enum i40e_status_code status;
 
 	if (hw->mac.type == I40E_MAC_X722)
 		lut_entry_width = 7;
 	else
 		lut_entry_width = pf->hw.func_caps.rss_table_entry_width;
 
 	/* Populate the LUT with max no. of queues in round robin fashion */
 	u8 hlut_buf[512];
 	for (i = 0; i < pf->hw.func_caps.rss_table_size; i++) {
 #ifdef RSS
 		/*
 		 * Fetch the RSS bucket id for the given indirection entry.
 		 * Cap it at the number of configured buckets (which is
 		 * num_queues.)
 		 */
 		que_id = rss_get_indirection_to_bucket(i);
 		que_id = que_id % vsi->num_queues;
 #else
 		que_id = i % vsi->num_queues;
 #endif
 		lut = (que_id & ((0x1 << lut_entry_width) - 1));
 		hlut_buf[i] = lut;
 	}
 
 	if (hw->mac.type == I40E_MAC_X722) {
 		status = i40e_aq_set_rss_lut(hw, vsi->vsi_num, TRUE, hlut_buf, sizeof(hlut_buf));
 		if (status)
 			device_printf(dev, "i40e_aq_set_rss_lut status %s, error %s\n",
 			    i40e_stat_str(hw, status), i40e_aq_str(hw, hw->aq.asq_last_status));
 	} else {
 		for (i = 0; i < pf->hw.func_caps.rss_table_size >> 2; i++)
 			wr32(hw, I40E_PFQF_HLUT(i), ((u32 *)hlut_buf)[i]);
 		ixl_flush(hw);
 	}
 }
 
 /*
 ** Setup the PF's RSS parameters.
 */
 void
 ixl_config_rss(struct ixl_pf *pf)
 {
 	ixl_set_rss_key(pf);
 	ixl_set_rss_pctypes(pf);
 	ixl_set_rss_hlut(pf);
 }
 
 /*
 ** This routine is run via an vlan config EVENT,
 ** it enables us to use the HW Filter table since
 ** we can get the vlan id. This just creates the
 ** entry in the soft version of the VFTA, init will
 ** repopulate the real table.
 */
 void
 ixl_register_vlan(void *arg, struct ifnet *ifp, u16 vtag)
 {
 	struct ixl_vsi	*vsi = ifp->if_softc;
 	struct i40e_hw	*hw = vsi->hw;
 	struct ixl_pf	*pf = (struct ixl_pf *)vsi->back;
 
 	if (ifp->if_softc !=  arg)   /* Not our event */
 		return;
 
 	if ((vtag == 0) || (vtag > 4095))	/* Invalid */
 		return;
 
 	IXL_PF_LOCK(pf);
 	++vsi->num_vlans;
 	ixl_add_filter(vsi, hw->mac.addr, vtag);
 	IXL_PF_UNLOCK(pf);
 }
 
 /*
 ** This routine is run via an vlan
 ** unconfig EVENT, remove our entry
 ** in the soft vfta.
 */
 void
 ixl_unregister_vlan(void *arg, struct ifnet *ifp, u16 vtag)
 {
 	struct ixl_vsi	*vsi = ifp->if_softc;
 	struct i40e_hw	*hw = vsi->hw;
 	struct ixl_pf	*pf = (struct ixl_pf *)vsi->back;
 
 	if (ifp->if_softc !=  arg)
 		return;
 
 	if ((vtag == 0) || (vtag > 4095))	/* Invalid */
 		return;
 
 	IXL_PF_LOCK(pf);
 	--vsi->num_vlans;
 	ixl_del_filter(vsi, hw->mac.addr, vtag);
 	IXL_PF_UNLOCK(pf);
 }
 
 /*
 ** This routine updates vlan filters, called by init
 ** it scans the filter table and then updates the hw
 ** after a soft reset.
 */
 void
 ixl_setup_vlan_filters(struct ixl_vsi *vsi)
 {
 	struct ixl_mac_filter	*f;
 	int			cnt = 0, flags;
 
 	if (vsi->num_vlans == 0)
 		return;
 	/*
 	** Scan the filter list for vlan entries,
 	** mark them for addition and then call
 	** for the AQ update.
 	*/
 	SLIST_FOREACH(f, &vsi->ftl, next) {
 		if (f->flags & IXL_FILTER_VLAN) {
 			f->flags |=
 			    (IXL_FILTER_ADD |
 			    IXL_FILTER_USED);
 			cnt++;
 		}
 	}
 	if (cnt == 0) {
 		printf("setup vlan: no filters found!\n");
 		return;
 	}
 	flags = IXL_FILTER_VLAN;
 	flags |= (IXL_FILTER_ADD | IXL_FILTER_USED);
 	ixl_add_hw_filters(vsi, flags, cnt);
 	return;
 }
 
 /*
 ** Initialize filter list and add filters that the hardware
 ** needs to know about.
 **
 ** Requires VSI's filter list & seid to be set before calling.
 */
 void
 ixl_init_filters(struct ixl_vsi *vsi)
 {
 	struct ixl_pf *pf = (struct ixl_pf *)vsi->back;
 
 	/* Add broadcast address */
 	ixl_add_filter(vsi, ixl_bcast_addr, IXL_VLAN_ANY);
 
 	/*
 	 * Prevent Tx flow control frames from being sent out by
 	 * non-firmware transmitters.
 	 * This affects every VSI in the PF.
 	 */
 	if (pf->enable_tx_fc_filter)
 		i40e_add_filter_to_drop_tx_flow_control_frames(vsi->hw, vsi->seid);
 }
 
 /*
 ** This routine adds mulicast filters
 */
 void
 ixl_add_mc_filter(struct ixl_vsi *vsi, u8 *macaddr)
 {
 	struct ixl_mac_filter *f;
 
 	/* Does one already exist */
 	f = ixl_find_filter(vsi, macaddr, IXL_VLAN_ANY);
 	if (f != NULL)
 		return;
 
 	f = ixl_get_filter(vsi);
 	if (f == NULL) {
 		printf("WARNING: no filter available!!\n");
 		return;
 	}
 	bcopy(macaddr, f->macaddr, ETHER_ADDR_LEN);
 	f->vlan = IXL_VLAN_ANY;
 	f->flags |= (IXL_FILTER_ADD | IXL_FILTER_USED
 	    | IXL_FILTER_MC);
 
 	return;
 }
 
 void
 ixl_reconfigure_filters(struct ixl_vsi *vsi)
 {
 	ixl_add_hw_filters(vsi, IXL_FILTER_USED, vsi->num_macs);
 }
 
 /*
 ** This routine adds macvlan filters
 */
 void
-ixl_add_filter(struct ixl_vsi *vsi, u8 *macaddr, s16 vlan)
+ixl_add_filter(struct ixl_vsi *vsi, const u8 *macaddr, s16 vlan)
 {
 	struct ixl_mac_filter	*f, *tmp;
 	struct ixl_pf		*pf;
 	device_t		dev;
 
 	DEBUGOUT("ixl_add_filter: begin");
 
 	pf = vsi->back;
 	dev = pf->dev;
 
 	/* Does one already exist */
 	f = ixl_find_filter(vsi, macaddr, vlan);
 	if (f != NULL)
 		return;
 	/*
 	** Is this the first vlan being registered, if so we
 	** need to remove the ANY filter that indicates we are
 	** not in a vlan, and replace that with a 0 filter.
 	*/
 	if ((vlan != IXL_VLAN_ANY) && (vsi->num_vlans == 1)) {
 		tmp = ixl_find_filter(vsi, macaddr, IXL_VLAN_ANY);
 		if (tmp != NULL) {
 			ixl_del_filter(vsi, macaddr, IXL_VLAN_ANY);
 			ixl_add_filter(vsi, macaddr, 0);
 		}
 	}
 
 	f = ixl_get_filter(vsi);
 	if (f == NULL) {
 		device_printf(dev, "WARNING: no filter available!!\n");
 		return;
 	}
 	bcopy(macaddr, f->macaddr, ETHER_ADDR_LEN);
 	f->vlan = vlan;
 	f->flags |= (IXL_FILTER_ADD | IXL_FILTER_USED);
 	if (f->vlan != IXL_VLAN_ANY)
 		f->flags |= IXL_FILTER_VLAN;
 	else
 		vsi->num_macs++;
 
 	ixl_add_hw_filters(vsi, f->flags, 1);
 	return;
 }
 
 void
-ixl_del_filter(struct ixl_vsi *vsi, u8 *macaddr, s16 vlan)
+ixl_del_filter(struct ixl_vsi *vsi, const u8 *macaddr, s16 vlan)
 {
 	struct ixl_mac_filter *f;
 
 	f = ixl_find_filter(vsi, macaddr, vlan);
 	if (f == NULL)
 		return;
 
 	f->flags |= IXL_FILTER_DEL;
 	ixl_del_hw_filters(vsi, 1);
 	vsi->num_macs--;
 
 	/* Check if this is the last vlan removal */
 	if (vlan != IXL_VLAN_ANY && vsi->num_vlans == 0) {
 		/* Switch back to a non-vlan filter */
 		ixl_del_filter(vsi, macaddr, 0);
 		ixl_add_filter(vsi, macaddr, IXL_VLAN_ANY);
 	}
 	return;
 }
 
 /*
 ** Find the filter with both matching mac addr and vlan id
 */
 struct ixl_mac_filter *
-ixl_find_filter(struct ixl_vsi *vsi, u8 *macaddr, s16 vlan)
+ixl_find_filter(struct ixl_vsi *vsi, const u8 *macaddr, s16 vlan)
 {
 	struct ixl_mac_filter	*f;
 	bool			match = FALSE;
 
 	SLIST_FOREACH(f, &vsi->ftl, next) {
 		if (!cmp_etheraddr(f->macaddr, macaddr))
 			continue;
 		if (f->vlan == vlan) {
 			match = TRUE;
 			break;
 		}
 	}	
 
 	if (!match)
 		f = NULL;
 	return (f);
 }
 
 /*
 ** This routine takes additions to the vsi filter
 ** table and creates an Admin Queue call to create
 ** the filters in the hardware.
 */
 void
 ixl_add_hw_filters(struct ixl_vsi *vsi, int flags, int cnt)
 {
 	struct i40e_aqc_add_macvlan_element_data *a, *b;
 	struct ixl_mac_filter	*f;
 	struct ixl_pf		*pf;
 	struct i40e_hw		*hw;
 	device_t		dev;
 	int			err, j = 0;
 
 	pf = vsi->back;
 	dev = pf->dev;
 	hw = &pf->hw;
 	IXL_PF_LOCK_ASSERT(pf);
 
 	a = malloc(sizeof(struct i40e_aqc_add_macvlan_element_data) * cnt,
 	    M_DEVBUF, M_NOWAIT | M_ZERO);
 	if (a == NULL) {
 		device_printf(dev, "add_hw_filters failed to get memory\n");
 		return;
 	}
 
 	/*
 	** Scan the filter list, each time we find one
 	** we add it to the admin queue array and turn off
 	** the add bit.
 	*/
 	SLIST_FOREACH(f, &vsi->ftl, next) {
 		if (f->flags == flags) {
 			b = &a[j]; // a pox on fvl long names :)
 			bcopy(f->macaddr, b->mac_addr, ETHER_ADDR_LEN);
 			if (f->vlan == IXL_VLAN_ANY) {
 				b->vlan_tag = 0;
 				b->flags = I40E_AQC_MACVLAN_ADD_IGNORE_VLAN;
 			} else {
 				b->vlan_tag = f->vlan;
 				b->flags = 0;
 			}
 			b->flags |= I40E_AQC_MACVLAN_ADD_PERFECT_MATCH;
 			f->flags &= ~IXL_FILTER_ADD;
 			j++;
 		}
 		if (j == cnt)
 			break;
 	}
 	if (j > 0) {
 		err = i40e_aq_add_macvlan(hw, vsi->seid, a, j, NULL);
 		if (err) 
 			device_printf(dev, "aq_add_macvlan err %d, "
 			    "aq_error %d\n", err, hw->aq.asq_last_status);
 		else
 			vsi->hw_filters_add += j;
 	}
 	free(a, M_DEVBUF);
 	return;
 }
 
 /*
 ** This routine takes removals in the vsi filter
 ** table and creates an Admin Queue call to delete
 ** the filters in the hardware.
 */
 void
 ixl_del_hw_filters(struct ixl_vsi *vsi, int cnt)
 {
 	struct i40e_aqc_remove_macvlan_element_data *d, *e;
 	struct ixl_pf		*pf;
 	struct i40e_hw		*hw;
 	device_t		dev;
 	struct ixl_mac_filter	*f, *f_temp;
 	int			err, j = 0;
 
 	DEBUGOUT("ixl_del_hw_filters: begin\n");
 
 	pf = vsi->back;
 	hw = &pf->hw;
 	dev = pf->dev;
 
 	d = malloc(sizeof(struct i40e_aqc_remove_macvlan_element_data) * cnt,
 	    M_DEVBUF, M_NOWAIT | M_ZERO);
 	if (d == NULL) {
 		printf("del hw filter failed to get memory\n");
 		return;
 	}
 
 	SLIST_FOREACH_SAFE(f, &vsi->ftl, next, f_temp) {
 		if (f->flags & IXL_FILTER_DEL) {
 			e = &d[j]; // a pox on fvl long names :)
 			bcopy(f->macaddr, e->mac_addr, ETHER_ADDR_LEN);
 			e->vlan_tag = (f->vlan == IXL_VLAN_ANY ? 0 : f->vlan);
 			e->flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH;
 			/* delete entry from vsi list */
 			SLIST_REMOVE(&vsi->ftl, f, ixl_mac_filter, next);
 			free(f, M_DEVBUF);
 			j++;
 		}
 		if (j == cnt)
 			break;
 	}
 	if (j > 0) {
 		err = i40e_aq_remove_macvlan(hw, vsi->seid, d, j, NULL);
 		if (err && hw->aq.asq_last_status != I40E_AQ_RC_ENOENT) {
 			int sc = 0;
 			for (int i = 0; i < j; i++)
 				sc += (!d[i].error_code);
 			vsi->hw_filters_del += sc;
 			device_printf(dev,
 			    "Failed to remove %d/%d filters, aq error %d\n",
 			    j - sc, j, hw->aq.asq_last_status);
 		} else
 			vsi->hw_filters_del += j;
 	}
 	free(d, M_DEVBUF);
 
 	DEBUGOUT("ixl_del_hw_filters: end\n");
 	return;
 }
 
 int
 ixl_enable_tx_ring(struct ixl_pf *pf, struct ixl_pf_qtag *qtag, u16 vsi_qidx)
 {
 	struct i40e_hw	*hw = &pf->hw;
 	int		error = 0;
 	u32		reg;
 	u16		pf_qidx;
 
 	pf_qidx = ixl_pf_qidx_from_vsi_qidx(qtag, vsi_qidx);
 
 	ixl_dbg(pf, IXL_DBG_EN_DIS,
 	    "Enabling PF TX ring %4d / VSI TX ring %4d...\n",
 	    pf_qidx, vsi_qidx);
 
 	i40e_pre_tx_queue_cfg(hw, pf_qidx, TRUE);
 
 	reg = rd32(hw, I40E_QTX_ENA(pf_qidx));
 	reg |= I40E_QTX_ENA_QENA_REQ_MASK |
 	    I40E_QTX_ENA_QENA_STAT_MASK;
 	wr32(hw, I40E_QTX_ENA(pf_qidx), reg);
 	/* Verify the enable took */
 	for (int j = 0; j < 10; j++) {
 		reg = rd32(hw, I40E_QTX_ENA(pf_qidx));
 		if (reg & I40E_QTX_ENA_QENA_STAT_MASK)
 			break;
 		i40e_msec_delay(10);
 	}
 	if ((reg & I40E_QTX_ENA_QENA_STAT_MASK) == 0) {
 		device_printf(pf->dev, "TX queue %d still disabled!\n",
 		    pf_qidx);
 		error = ETIMEDOUT;
 	}
 
 	return (error);
 }
 
 int
 ixl_enable_rx_ring(struct ixl_pf *pf, struct ixl_pf_qtag *qtag, u16 vsi_qidx)
 {
 	struct i40e_hw	*hw = &pf->hw;
 	int		error = 0;
 	u32		reg;
 	u16		pf_qidx;
 
 	pf_qidx = ixl_pf_qidx_from_vsi_qidx(qtag, vsi_qidx);
 
 	ixl_dbg(pf, IXL_DBG_EN_DIS,
 	    "Enabling PF RX ring %4d / VSI RX ring %4d...\n",
 	    pf_qidx, vsi_qidx);
 
 	reg = rd32(hw, I40E_QRX_ENA(pf_qidx));
 	reg |= I40E_QRX_ENA_QENA_REQ_MASK |
 	    I40E_QRX_ENA_QENA_STAT_MASK;
 	wr32(hw, I40E_QRX_ENA(pf_qidx), reg);
 	/* Verify the enable took */
 	for (int j = 0; j < 10; j++) {
 		reg = rd32(hw, I40E_QRX_ENA(pf_qidx));
 		if (reg & I40E_QRX_ENA_QENA_STAT_MASK)
 			break;
 		i40e_msec_delay(10);
 	}
 	if ((reg & I40E_QRX_ENA_QENA_STAT_MASK) == 0) {
 		device_printf(pf->dev, "RX queue %d still disabled!\n",
 		    pf_qidx);
 		error = ETIMEDOUT;
 	}
 
 	return (error);
 }
 
 int
 ixl_enable_ring(struct ixl_pf *pf, struct ixl_pf_qtag *qtag, u16 vsi_qidx)
 {
 	int error = 0;
 
 	error = ixl_enable_tx_ring(pf, qtag, vsi_qidx);
 	/* Called function already prints error message */
 	if (error)
 		return (error);
 	error = ixl_enable_rx_ring(pf, qtag, vsi_qidx);
 	return (error);
 }
 
 /* For PF VSI only */
 int
 ixl_enable_rings(struct ixl_vsi *vsi)
 {
 	struct ixl_pf	*pf = vsi->back;
 	int		error = 0;
 
 	for (int i = 0; i < vsi->num_queues; i++) {
 		error = ixl_enable_ring(pf, &pf->qtag, i);
 		if (error)
 			return (error);
 	}
 
 	return (error);
 }
 
 int
 ixl_disable_tx_ring(struct ixl_pf *pf, struct ixl_pf_qtag *qtag, u16 vsi_qidx)
 {
 	struct i40e_hw	*hw = &pf->hw;
 	int		error = 0;
 	u32		reg;
 	u16		pf_qidx;
 
 	pf_qidx = ixl_pf_qidx_from_vsi_qidx(qtag, vsi_qidx);
 
 	i40e_pre_tx_queue_cfg(hw, pf_qidx, FALSE);
 	i40e_usec_delay(500);
 
 	reg = rd32(hw, I40E_QTX_ENA(pf_qidx));
 	reg &= ~I40E_QTX_ENA_QENA_REQ_MASK;
 	wr32(hw, I40E_QTX_ENA(pf_qidx), reg);
 	/* Verify the disable took */
 	for (int j = 0; j < 10; j++) {
 		reg = rd32(hw, I40E_QTX_ENA(pf_qidx));
 		if (!(reg & I40E_QTX_ENA_QENA_STAT_MASK))
 			break;
 		i40e_msec_delay(10);
 	}
 	if (reg & I40E_QTX_ENA_QENA_STAT_MASK) {
 		device_printf(pf->dev, "TX queue %d still enabled!\n",
 		    pf_qidx);
 		error = ETIMEDOUT;
 	}
 
 	return (error);
 }
 
 int
 ixl_disable_rx_ring(struct ixl_pf *pf, struct ixl_pf_qtag *qtag, u16 vsi_qidx)
 {
 	struct i40e_hw	*hw = &pf->hw;
 	int		error = 0;
 	u32		reg;
 	u16		pf_qidx;
 
 	pf_qidx = ixl_pf_qidx_from_vsi_qidx(qtag, vsi_qidx);
 
 	reg = rd32(hw, I40E_QRX_ENA(pf_qidx));
 	reg &= ~I40E_QRX_ENA_QENA_REQ_MASK;
 	wr32(hw, I40E_QRX_ENA(pf_qidx), reg);
 	/* Verify the disable took */
 	for (int j = 0; j < 10; j++) {
 		reg = rd32(hw, I40E_QRX_ENA(pf_qidx));
 		if (!(reg & I40E_QRX_ENA_QENA_STAT_MASK))
 			break;
 		i40e_msec_delay(10);
 	}
 	if (reg & I40E_QRX_ENA_QENA_STAT_MASK) {
 		device_printf(pf->dev, "RX queue %d still enabled!\n",
 		    pf_qidx);
 		error = ETIMEDOUT;
 	}
 
 	return (error);
 }
 
 int
 ixl_disable_ring(struct ixl_pf *pf, struct ixl_pf_qtag *qtag, u16 vsi_qidx)
 {
 	int error = 0;
 
 	error = ixl_disable_tx_ring(pf, qtag, vsi_qidx);
 	/* Called function already prints error message */
 	if (error)
 		return (error);
 	error = ixl_disable_rx_ring(pf, qtag, vsi_qidx);
 	return (error);
 }
 
 /* For PF VSI only */
 int
 ixl_disable_rings(struct ixl_vsi *vsi)
 {
 	struct ixl_pf	*pf = vsi->back;
 	int		error = 0;
 
 	for (int i = 0; i < vsi->num_queues; i++) {
 		error = ixl_disable_ring(pf, &pf->qtag, i);
 		if (error)
 			return (error);
 	}
 
 	return (error);
 }
 
 /**
  * ixl_handle_mdd_event
  *
  * Called from interrupt handler to identify possibly malicious vfs
  * (But also detects events from the PF, as well)
  **/
 void
 ixl_handle_mdd_event(struct ixl_pf *pf)
 {
 	struct i40e_hw *hw = &pf->hw;
 	device_t dev = pf->dev;
 	bool mdd_detected = false;
 	bool pf_mdd_detected = false;
 	u32 reg;
 
 	/* find what triggered the MDD event */
 	reg = rd32(hw, I40E_GL_MDET_TX);
 	if (reg & I40E_GL_MDET_TX_VALID_MASK) {
 		u8 pf_num = (reg & I40E_GL_MDET_TX_PF_NUM_MASK) >>
 				I40E_GL_MDET_TX_PF_NUM_SHIFT;
 		u8 event = (reg & I40E_GL_MDET_TX_EVENT_MASK) >>
 				I40E_GL_MDET_TX_EVENT_SHIFT;
 		u16 queue = (reg & I40E_GL_MDET_TX_QUEUE_MASK) >>
 				I40E_GL_MDET_TX_QUEUE_SHIFT;
 		device_printf(dev,
 		    "Malicious Driver Detection event %d"
 		    " on TX queue %d, pf number %d\n",
 		    event, queue, pf_num);
 		wr32(hw, I40E_GL_MDET_TX, 0xffffffff);
 		mdd_detected = true;
 	}
 	reg = rd32(hw, I40E_GL_MDET_RX);
 	if (reg & I40E_GL_MDET_RX_VALID_MASK) {
 		u8 pf_num = (reg & I40E_GL_MDET_RX_FUNCTION_MASK) >>
 				I40E_GL_MDET_RX_FUNCTION_SHIFT;
 		u8 event = (reg & I40E_GL_MDET_RX_EVENT_MASK) >>
 				I40E_GL_MDET_RX_EVENT_SHIFT;
 		u16 queue = (reg & I40E_GL_MDET_RX_QUEUE_MASK) >>
 				I40E_GL_MDET_RX_QUEUE_SHIFT;
 		device_printf(dev,
 		    "Malicious Driver Detection event %d"
 		    " on RX queue %d, pf number %d\n",
 		    event, queue, pf_num);
 		wr32(hw, I40E_GL_MDET_RX, 0xffffffff);
 		mdd_detected = true;
 	}
 
 	if (mdd_detected) {
 		reg = rd32(hw, I40E_PF_MDET_TX);
 		if (reg & I40E_PF_MDET_TX_VALID_MASK) {
 			wr32(hw, I40E_PF_MDET_TX, 0xFFFF);
 			device_printf(dev,
 			    "MDD TX event is for this function!");
 			pf_mdd_detected = true;
 		}
 		reg = rd32(hw, I40E_PF_MDET_RX);
 		if (reg & I40E_PF_MDET_RX_VALID_MASK) {
 			wr32(hw, I40E_PF_MDET_RX, 0xFFFF);
 			device_printf(dev,
 			    "MDD RX event is for this function!");
 			pf_mdd_detected = true;
 		}
 	}
 
 	/* re-enable mdd interrupt cause */
 	reg = rd32(hw, I40E_PFINT_ICR0_ENA);
 	reg |= I40E_PFINT_ICR0_ENA_MAL_DETECT_MASK;
 	wr32(hw, I40E_PFINT_ICR0_ENA, reg);
 	ixl_flush(hw);
 }
 
 void
 ixl_enable_intr(struct ixl_vsi *vsi)
 {
 	struct ixl_pf		*pf = (struct ixl_pf *)vsi->back;
 	struct i40e_hw		*hw = vsi->hw;
 	struct ixl_queue	*que = vsi->queues;
 
 	if (pf->msix > 1) {
 		for (int i = 0; i < vsi->num_queues; i++, que++)
 			ixl_enable_queue(hw, que->me);
 	} else
 		ixl_enable_intr0(hw);
 }
 
 void
 ixl_disable_rings_intr(struct ixl_vsi *vsi)
 {
 	struct i40e_hw		*hw = vsi->hw;
 	struct ixl_queue	*que = vsi->queues;
 
 	for (int i = 0; i < vsi->num_queues; i++, que++)
 		ixl_disable_queue(hw, que->me);
 }
 
 void
 ixl_enable_intr0(struct i40e_hw *hw)
 {
 	u32		reg;
 
 	/* Use IXL_ITR_NONE so ITR isn't updated here */
 	reg = I40E_PFINT_DYN_CTL0_INTENA_MASK |
 	    I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
 	    (IXL_ITR_NONE << I40E_PFINT_DYN_CTL0_ITR_INDX_SHIFT);
 	wr32(hw, I40E_PFINT_DYN_CTL0, reg);
 }
 
 void
 ixl_disable_intr0(struct i40e_hw *hw)
 {
 	u32		reg;
 
 	reg = IXL_ITR_NONE << I40E_PFINT_DYN_CTL0_ITR_INDX_SHIFT;
 	wr32(hw, I40E_PFINT_DYN_CTL0, reg);
 	ixl_flush(hw);
 }
 
 void
 ixl_enable_queue(struct i40e_hw *hw, int id)
 {
 	u32		reg;
 
 	reg = I40E_PFINT_DYN_CTLN_INTENA_MASK |
 	    I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
 	    (IXL_ITR_NONE << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT);
 	wr32(hw, I40E_PFINT_DYN_CTLN(id), reg);
 }
 
 void
 ixl_disable_queue(struct i40e_hw *hw, int id)
 {
 	u32		reg;
 
 	reg = IXL_ITR_NONE << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT;
 	wr32(hw, I40E_PFINT_DYN_CTLN(id), reg);
 }
 
 void
 ixl_update_stats_counters(struct ixl_pf *pf)
 {
 	struct i40e_hw	*hw = &pf->hw;
 	struct ixl_vsi	*vsi = &pf->vsi;
 	struct ixl_vf	*vf;
 
 	struct i40e_hw_port_stats *nsd = &pf->stats;
 	struct i40e_hw_port_stats *osd = &pf->stats_offsets;
 
 	/* Update hw stats */
 	ixl_stat_update32(hw, I40E_GLPRT_CRCERRS(hw->port),
 			   pf->stat_offsets_loaded,
 			   &osd->crc_errors, &nsd->crc_errors);
 	ixl_stat_update32(hw, I40E_GLPRT_ILLERRC(hw->port),
 			   pf->stat_offsets_loaded,
 			   &osd->illegal_bytes, &nsd->illegal_bytes);
 	ixl_stat_update48(hw, I40E_GLPRT_GORCH(hw->port),
 			   I40E_GLPRT_GORCL(hw->port),
 			   pf->stat_offsets_loaded,
 			   &osd->eth.rx_bytes, &nsd->eth.rx_bytes);
 	ixl_stat_update48(hw, I40E_GLPRT_GOTCH(hw->port),
 			   I40E_GLPRT_GOTCL(hw->port),
 			   pf->stat_offsets_loaded,
 			   &osd->eth.tx_bytes, &nsd->eth.tx_bytes);
 	ixl_stat_update32(hw, I40E_GLPRT_RDPC(hw->port),
 			   pf->stat_offsets_loaded,
 			   &osd->eth.rx_discards,
 			   &nsd->eth.rx_discards);
 	ixl_stat_update48(hw, I40E_GLPRT_UPRCH(hw->port),
 			   I40E_GLPRT_UPRCL(hw->port),
 			   pf->stat_offsets_loaded,
 			   &osd->eth.rx_unicast,
 			   &nsd->eth.rx_unicast);
 	ixl_stat_update48(hw, I40E_GLPRT_UPTCH(hw->port),
 			   I40E_GLPRT_UPTCL(hw->port),
 			   pf->stat_offsets_loaded,
 			   &osd->eth.tx_unicast,
 			   &nsd->eth.tx_unicast);
 	ixl_stat_update48(hw, I40E_GLPRT_MPRCH(hw->port),
 			   I40E_GLPRT_MPRCL(hw->port),
 			   pf->stat_offsets_loaded,
 			   &osd->eth.rx_multicast,
 			   &nsd->eth.rx_multicast);
 	ixl_stat_update48(hw, I40E_GLPRT_MPTCH(hw->port),
 			   I40E_GLPRT_MPTCL(hw->port),
 			   pf->stat_offsets_loaded,
 			   &osd->eth.tx_multicast,
 			   &nsd->eth.tx_multicast);
 	ixl_stat_update48(hw, I40E_GLPRT_BPRCH(hw->port),
 			   I40E_GLPRT_BPRCL(hw->port),
 			   pf->stat_offsets_loaded,
 			   &osd->eth.rx_broadcast,
 			   &nsd->eth.rx_broadcast);
 	ixl_stat_update48(hw, I40E_GLPRT_BPTCH(hw->port),
 			   I40E_GLPRT_BPTCL(hw->port),
 			   pf->stat_offsets_loaded,
 			   &osd->eth.tx_broadcast,
 			   &nsd->eth.tx_broadcast);
 
 	ixl_stat_update32(hw, I40E_GLPRT_TDOLD(hw->port),
 			   pf->stat_offsets_loaded,
 			   &osd->tx_dropped_link_down,
 			   &nsd->tx_dropped_link_down);
 	ixl_stat_update32(hw, I40E_GLPRT_MLFC(hw->port),
 			   pf->stat_offsets_loaded,
 			   &osd->mac_local_faults,
 			   &nsd->mac_local_faults);
 	ixl_stat_update32(hw, I40E_GLPRT_MRFC(hw->port),
 			   pf->stat_offsets_loaded,
 			   &osd->mac_remote_faults,
 			   &nsd->mac_remote_faults);
 	ixl_stat_update32(hw, I40E_GLPRT_RLEC(hw->port),
 			   pf->stat_offsets_loaded,
 			   &osd->rx_length_errors,
 			   &nsd->rx_length_errors);
 
 	/* Flow control (LFC) stats */
 	ixl_stat_update32(hw, I40E_GLPRT_LXONRXC(hw->port),
 			   pf->stat_offsets_loaded,
 			   &osd->link_xon_rx, &nsd->link_xon_rx);
 	ixl_stat_update32(hw, I40E_GLPRT_LXONTXC(hw->port),
 			   pf->stat_offsets_loaded,
 			   &osd->link_xon_tx, &nsd->link_xon_tx);
 	ixl_stat_update32(hw, I40E_GLPRT_LXOFFRXC(hw->port),
 			   pf->stat_offsets_loaded,
 			   &osd->link_xoff_rx, &nsd->link_xoff_rx);
 	ixl_stat_update32(hw, I40E_GLPRT_LXOFFTXC(hw->port),
 			   pf->stat_offsets_loaded,
 			   &osd->link_xoff_tx, &nsd->link_xoff_tx);
 
 	/* Packet size stats rx */
 	ixl_stat_update48(hw, I40E_GLPRT_PRC64H(hw->port),
 			   I40E_GLPRT_PRC64L(hw->port),
 			   pf->stat_offsets_loaded,
 			   &osd->rx_size_64, &nsd->rx_size_64);
 	ixl_stat_update48(hw, I40E_GLPRT_PRC127H(hw->port),
 			   I40E_GLPRT_PRC127L(hw->port),
 			   pf->stat_offsets_loaded,
 			   &osd->rx_size_127, &nsd->rx_size_127);
 	ixl_stat_update48(hw, I40E_GLPRT_PRC255H(hw->port),
 			   I40E_GLPRT_PRC255L(hw->port),
 			   pf->stat_offsets_loaded,
 			   &osd->rx_size_255, &nsd->rx_size_255);
 	ixl_stat_update48(hw, I40E_GLPRT_PRC511H(hw->port),
 			   I40E_GLPRT_PRC511L(hw->port),
 			   pf->stat_offsets_loaded,
 			   &osd->rx_size_511, &nsd->rx_size_511);
 	ixl_stat_update48(hw, I40E_GLPRT_PRC1023H(hw->port),
 			   I40E_GLPRT_PRC1023L(hw->port),
 			   pf->stat_offsets_loaded,
 			   &osd->rx_size_1023, &nsd->rx_size_1023);
 	ixl_stat_update48(hw, I40E_GLPRT_PRC1522H(hw->port),
 			   I40E_GLPRT_PRC1522L(hw->port),
 			   pf->stat_offsets_loaded,
 			   &osd->rx_size_1522, &nsd->rx_size_1522);
 	ixl_stat_update48(hw, I40E_GLPRT_PRC9522H(hw->port),
 			   I40E_GLPRT_PRC9522L(hw->port),
 			   pf->stat_offsets_loaded,
 			   &osd->rx_size_big, &nsd->rx_size_big);
 
 	/* Packet size stats tx */
 	ixl_stat_update48(hw, I40E_GLPRT_PTC64H(hw->port),
 			   I40E_GLPRT_PTC64L(hw->port),
 			   pf->stat_offsets_loaded,
 			   &osd->tx_size_64, &nsd->tx_size_64);
 	ixl_stat_update48(hw, I40E_GLPRT_PTC127H(hw->port),
 			   I40E_GLPRT_PTC127L(hw->port),
 			   pf->stat_offsets_loaded,
 			   &osd->tx_size_127, &nsd->tx_size_127);
 	ixl_stat_update48(hw, I40E_GLPRT_PTC255H(hw->port),
 			   I40E_GLPRT_PTC255L(hw->port),
 			   pf->stat_offsets_loaded,
 			   &osd->tx_size_255, &nsd->tx_size_255);
 	ixl_stat_update48(hw, I40E_GLPRT_PTC511H(hw->port),
 			   I40E_GLPRT_PTC511L(hw->port),
 			   pf->stat_offsets_loaded,
 			   &osd->tx_size_511, &nsd->tx_size_511);
 	ixl_stat_update48(hw, I40E_GLPRT_PTC1023H(hw->port),
 			   I40E_GLPRT_PTC1023L(hw->port),
 			   pf->stat_offsets_loaded,
 			   &osd->tx_size_1023, &nsd->tx_size_1023);
 	ixl_stat_update48(hw, I40E_GLPRT_PTC1522H(hw->port),
 			   I40E_GLPRT_PTC1522L(hw->port),
 			   pf->stat_offsets_loaded,
 			   &osd->tx_size_1522, &nsd->tx_size_1522);
 	ixl_stat_update48(hw, I40E_GLPRT_PTC9522H(hw->port),
 			   I40E_GLPRT_PTC9522L(hw->port),
 			   pf->stat_offsets_loaded,
 			   &osd->tx_size_big, &nsd->tx_size_big);
 
 	ixl_stat_update32(hw, I40E_GLPRT_RUC(hw->port),
 			   pf->stat_offsets_loaded,
 			   &osd->rx_undersize, &nsd->rx_undersize);
 	ixl_stat_update32(hw, I40E_GLPRT_RFC(hw->port),
 			   pf->stat_offsets_loaded,
 			   &osd->rx_fragments, &nsd->rx_fragments);
 	ixl_stat_update32(hw, I40E_GLPRT_ROC(hw->port),
 			   pf->stat_offsets_loaded,
 			   &osd->rx_oversize, &nsd->rx_oversize);
 	ixl_stat_update32(hw, I40E_GLPRT_RJC(hw->port),
 			   pf->stat_offsets_loaded,
 			   &osd->rx_jabber, &nsd->rx_jabber);
 	pf->stat_offsets_loaded = true;
 	/* End hw stats */
 
 	/* Update vsi stats */
 	ixl_update_vsi_stats(vsi);
 
 	for (int i = 0; i < pf->num_vfs; i++) {
 		vf = &pf->vfs[i];
 		if (vf->vf_flags & VF_FLAG_ENABLED)
 			ixl_update_eth_stats(&pf->vfs[i].vsi);
 	}
 }
 
 int
 ixl_rebuild_hw_structs_after_reset(struct ixl_pf *pf)
 {
 	struct i40e_hw *hw = &pf->hw;
 	struct ixl_vsi *vsi = &pf->vsi;
 	device_t dev = pf->dev;
 	bool is_up = false;
 	int error = 0;
 
 	is_up = !!(vsi->ifp->if_drv_flags & IFF_DRV_RUNNING);
 
 	/* Teardown */
 	if (is_up)
 		ixl_stop(pf);
 	error = i40e_shutdown_lan_hmc(hw);
 	if (error)
 		device_printf(dev,
 		    "Shutdown LAN HMC failed with code %d\n", error);
 	ixl_disable_intr0(hw);
 	ixl_teardown_adminq_msix(pf);
 	error = i40e_shutdown_adminq(hw);
 	if (error)
 		device_printf(dev,
 		    "Shutdown Admin queue failed with code %d\n", error);
 
 	/* Setup */
 	error = i40e_init_adminq(hw);
 	if (error != 0 && error != I40E_ERR_FIRMWARE_API_VERSION) {
 		device_printf(dev, "Unable to initialize Admin Queue, error %d\n",
 		    error);
 	}
 	error = ixl_setup_adminq_msix(pf);
 	if (error) {
 		device_printf(dev, "ixl_setup_adminq_msix error: %d\n",
 		    error);
 	}
 	ixl_configure_intr0_msix(pf);
 	ixl_enable_intr0(hw);
 	error = i40e_init_lan_hmc(hw, hw->func_caps.num_tx_qp,
 	    hw->func_caps.num_rx_qp, 0, 0);
 	if (error) {
 		device_printf(dev, "init_lan_hmc failed: %d\n", error);
 	}
 	error = i40e_configure_lan_hmc(hw, I40E_HMC_MODEL_DIRECT_ONLY);
 	if (error) {
 		device_printf(dev, "configure_lan_hmc failed: %d\n", error);
 	}
 	if (is_up)
 		ixl_init(pf);
 
 	return (0);
 }
 
 void
 ixl_handle_empr_reset(struct ixl_pf *pf)
 {
 	struct i40e_hw *hw = &pf->hw;
 	device_t dev = pf->dev;
 	int count = 0;
 	u32 reg;
 
 	/* Typically finishes within 3-4 seconds */
 	while (count++ < 100) {
 		reg = rd32(hw, I40E_GLGEN_RSTAT)
 		    & I40E_GLGEN_RSTAT_DEVSTATE_MASK;
 		if (reg)
 			i40e_msec_delay(100);
 		else
 			break;
 	}
 	ixl_dbg(pf, IXL_DBG_INFO,
 	    "EMPR reset wait count: %d\n", count);
 
 	device_printf(dev, "Rebuilding driver state...\n");
 	ixl_rebuild_hw_structs_after_reset(pf);
 	device_printf(dev, "Rebuilding driver state done.\n");
 
 	atomic_clear_int(&pf->state, IXL_PF_STATE_EMPR_RESETTING);
 }
 
 /*
 ** Tasklet handler for MSIX Adminq interrupts
 **  - do outside interrupt since it might sleep
 */
 void
 ixl_do_adminq(void *context, int pending)
 {
 	struct ixl_pf			*pf = context;
 	struct i40e_hw			*hw = &pf->hw;
 	struct i40e_arq_event_info	event;
 	i40e_status			ret;
 	device_t			dev = pf->dev;
 	u32				loop = 0;
 	u16				opcode, result;
 
 	if (pf->state & IXL_PF_STATE_EMPR_RESETTING) {
 		/* Flag cleared at end of this function */
 		ixl_handle_empr_reset(pf);
 		return;
 	}
 
 	/* Admin Queue handling */
 	event.buf_len = IXL_AQ_BUF_SZ;
 	event.msg_buf = malloc(event.buf_len,
 	    M_DEVBUF, M_NOWAIT | M_ZERO);
 	if (!event.msg_buf) {
 		device_printf(dev, "%s: Unable to allocate memory for Admin"
 		    " Queue event!\n", __func__);
 		return;
 	}
 
 	IXL_PF_LOCK(pf);
 	/* clean and process any events */
 	do {
 		ret = i40e_clean_arq_element(hw, &event, &result);
 		if (ret)
 			break;
 		opcode = LE16_TO_CPU(event.desc.opcode);
 		ixl_dbg(pf, IXL_DBG_AQ,
 		    "Admin Queue event: %#06x\n", opcode);
 		switch (opcode) {
 		case i40e_aqc_opc_get_link_status:
 			ixl_link_event(pf, &event);
 			break;
 		case i40e_aqc_opc_send_msg_to_pf:
 #ifdef PCI_IOV
 			ixl_handle_vf_msg(pf, &event);
 #endif
 			break;
 		case i40e_aqc_opc_event_lan_overflow:
 		default:
 			break;
 		}
 
 	} while (result && (loop++ < IXL_ADM_LIMIT));
 
 	free(event.msg_buf, M_DEVBUF);
 
 	/*
 	 * If there are still messages to process, reschedule ourselves.
 	 * Otherwise, re-enable our interrupt.
 	 */
 	if (result > 0)
 		taskqueue_enqueue(pf->tq, &pf->adminq);
 	else
 		ixl_enable_intr0(hw);
 
 	IXL_PF_UNLOCK(pf);
 }
 
 /**
  * Update VSI-specific ethernet statistics counters.
  **/
 void
 ixl_update_eth_stats(struct ixl_vsi *vsi)
 {
 	struct ixl_pf *pf = (struct ixl_pf *)vsi->back;
 	struct i40e_hw *hw = &pf->hw;
 	struct i40e_eth_stats *es;
 	struct i40e_eth_stats *oes;
 	struct i40e_hw_port_stats *nsd;
 	u16 stat_idx = vsi->info.stat_counter_idx;
 
 	es = &vsi->eth_stats;
 	oes = &vsi->eth_stats_offsets;
 	nsd = &pf->stats;
 
 	/* Gather up the stats that the hw collects */
 	ixl_stat_update32(hw, I40E_GLV_TEPC(stat_idx),
 			   vsi->stat_offsets_loaded,
 			   &oes->tx_errors, &es->tx_errors);
 	ixl_stat_update32(hw, I40E_GLV_RDPC(stat_idx),
 			   vsi->stat_offsets_loaded,
 			   &oes->rx_discards, &es->rx_discards);
 
 	ixl_stat_update48(hw, I40E_GLV_GORCH(stat_idx),
 			   I40E_GLV_GORCL(stat_idx),
 			   vsi->stat_offsets_loaded,
 			   &oes->rx_bytes, &es->rx_bytes);
 	ixl_stat_update48(hw, I40E_GLV_UPRCH(stat_idx),
 			   I40E_GLV_UPRCL(stat_idx),
 			   vsi->stat_offsets_loaded,
 			   &oes->rx_unicast, &es->rx_unicast);
 	ixl_stat_update48(hw, I40E_GLV_MPRCH(stat_idx),
 			   I40E_GLV_MPRCL(stat_idx),
 			   vsi->stat_offsets_loaded,
 			   &oes->rx_multicast, &es->rx_multicast);
 	ixl_stat_update48(hw, I40E_GLV_BPRCH(stat_idx),
 			   I40E_GLV_BPRCL(stat_idx),
 			   vsi->stat_offsets_loaded,
 			   &oes->rx_broadcast, &es->rx_broadcast);
 
 	ixl_stat_update48(hw, I40E_GLV_GOTCH(stat_idx),
 			   I40E_GLV_GOTCL(stat_idx),
 			   vsi->stat_offsets_loaded,
 			   &oes->tx_bytes, &es->tx_bytes);
 	ixl_stat_update48(hw, I40E_GLV_UPTCH(stat_idx),
 			   I40E_GLV_UPTCL(stat_idx),
 			   vsi->stat_offsets_loaded,
 			   &oes->tx_unicast, &es->tx_unicast);
 	ixl_stat_update48(hw, I40E_GLV_MPTCH(stat_idx),
 			   I40E_GLV_MPTCL(stat_idx),
 			   vsi->stat_offsets_loaded,
 			   &oes->tx_multicast, &es->tx_multicast);
 	ixl_stat_update48(hw, I40E_GLV_BPTCH(stat_idx),
 			   I40E_GLV_BPTCL(stat_idx),
 			   vsi->stat_offsets_loaded,
 			   &oes->tx_broadcast, &es->tx_broadcast);
 	vsi->stat_offsets_loaded = true;
 }
 
 void
 ixl_update_vsi_stats(struct ixl_vsi *vsi)
 {
 	struct ixl_pf		*pf;
 	struct ifnet		*ifp;
 	struct i40e_eth_stats	*es;
 	u64			tx_discards;
 
 	struct i40e_hw_port_stats *nsd;
 
 	pf = vsi->back;
 	ifp = vsi->ifp;
 	es = &vsi->eth_stats;
 	nsd = &pf->stats;
 
 	ixl_update_eth_stats(vsi);
 
 	tx_discards = es->tx_discards + nsd->tx_dropped_link_down;
 	for (int i = 0; i < vsi->num_queues; i++)
 		tx_discards += vsi->queues[i].txr.br->br_drops;
 
 	/* Update ifnet stats */
 	IXL_SET_IPACKETS(vsi, es->rx_unicast +
 	                   es->rx_multicast +
 			   es->rx_broadcast);
 	IXL_SET_OPACKETS(vsi, es->tx_unicast +
 	                   es->tx_multicast +
 			   es->tx_broadcast);
 	IXL_SET_IBYTES(vsi, es->rx_bytes);
 	IXL_SET_OBYTES(vsi, es->tx_bytes);
 	IXL_SET_IMCASTS(vsi, es->rx_multicast);
 	IXL_SET_OMCASTS(vsi, es->tx_multicast);
 
 	IXL_SET_IERRORS(vsi, nsd->crc_errors + nsd->illegal_bytes +
 	    nsd->rx_undersize + nsd->rx_oversize + nsd->rx_fragments +
 	    nsd->rx_jabber);
 	IXL_SET_OERRORS(vsi, es->tx_errors);
 	IXL_SET_IQDROPS(vsi, es->rx_discards + nsd->eth.rx_discards);
 	IXL_SET_OQDROPS(vsi, tx_discards);
 	IXL_SET_NOPROTO(vsi, es->rx_unknown_protocol);
 	IXL_SET_COLLISIONS(vsi, 0);
 }
 
 /**
  * Reset all of the stats for the given pf
  **/
 void
 ixl_pf_reset_stats(struct ixl_pf *pf)
 {
 	bzero(&pf->stats, sizeof(struct i40e_hw_port_stats));
 	bzero(&pf->stats_offsets, sizeof(struct i40e_hw_port_stats));
 	pf->stat_offsets_loaded = false;
 }
 
 /**
  * Resets all stats of the given vsi
  **/
 void
 ixl_vsi_reset_stats(struct ixl_vsi *vsi)
 {
 	bzero(&vsi->eth_stats, sizeof(struct i40e_eth_stats));
 	bzero(&vsi->eth_stats_offsets, sizeof(struct i40e_eth_stats));
 	vsi->stat_offsets_loaded = false;
 }
 
 /**
  * Read and update a 48 bit stat from the hw
  *
  * Since the device stats are not reset at PFReset, they likely will not
  * be zeroed when the driver starts.  We'll save the first values read
  * and use them as offsets to be subtracted from the raw values in order
  * to report stats that count from zero.
  **/
 void
 ixl_stat_update48(struct i40e_hw *hw, u32 hireg, u32 loreg,
 	bool offset_loaded, u64 *offset, u64 *stat)
 {
 	u64 new_data;
 
 #if defined(__FreeBSD__) && (__FreeBSD_version >= 1000000) && defined(__amd64__)
 	new_data = rd64(hw, loreg);
 #else
 	/*
 	 * Use two rd32's instead of one rd64; FreeBSD versions before
 	 * 10 don't support 64-bit bus reads/writes.
 	 */
 	new_data = rd32(hw, loreg);
 	new_data |= ((u64)(rd32(hw, hireg) & 0xFFFF)) << 32;
 #endif
 
 	if (!offset_loaded)
 		*offset = new_data;
 	if (new_data >= *offset)
 		*stat = new_data - *offset;
 	else
 		*stat = (new_data + ((u64)1 << 48)) - *offset;
 	*stat &= 0xFFFFFFFFFFFFULL;
 }
 
 /**
  * Read and update a 32 bit stat from the hw
  **/
 void
 ixl_stat_update32(struct i40e_hw *hw, u32 reg,
 	bool offset_loaded, u64 *offset, u64 *stat)
 {
 	u32 new_data;
 
 	new_data = rd32(hw, reg);
 	if (!offset_loaded)
 		*offset = new_data;
 	if (new_data >= *offset)
 		*stat = (u32)(new_data - *offset);
 	else
 		*stat = (u32)((new_data + ((u64)1 << 32)) - *offset);
 }
 
 void
 ixl_add_device_sysctls(struct ixl_pf *pf)
 {
 	device_t dev = pf->dev;
 	struct i40e_hw *hw = &pf->hw;
 
 	struct sysctl_ctx_list *ctx = device_get_sysctl_ctx(dev);
 	struct sysctl_oid_list *ctx_list =
 	    SYSCTL_CHILDREN(device_get_sysctl_tree(dev));
 
 	struct sysctl_oid *debug_node;
 	struct sysctl_oid_list *debug_list;
 
 	struct sysctl_oid *fec_node;
 	struct sysctl_oid_list *fec_list;
 
 	/* Set up sysctls */
 	SYSCTL_ADD_PROC(ctx, ctx_list,
 	    OID_AUTO, "fc", CTLTYPE_INT | CTLFLAG_RW,
 	    pf, 0, ixl_set_flowcntl, "I", IXL_SYSCTL_HELP_FC);
 
 	SYSCTL_ADD_PROC(ctx, ctx_list,
 	    OID_AUTO, "advertise_speed", CTLTYPE_INT | CTLFLAG_RW,
 	    pf, 0, ixl_set_advertise, "I", IXL_SYSCTL_HELP_SET_ADVERTISE);
 
 	SYSCTL_ADD_PROC(ctx, ctx_list,
 	    OID_AUTO, "current_speed", CTLTYPE_STRING | CTLFLAG_RD,
 	    pf, 0, ixl_current_speed, "A", "Current Port Speed");
 
 	SYSCTL_ADD_PROC(ctx, ctx_list,
 	    OID_AUTO, "fw_version", CTLTYPE_STRING | CTLFLAG_RD,
 	    pf, 0, ixl_sysctl_show_fw, "A", "Firmware version");
 
 	SYSCTL_ADD_PROC(ctx, ctx_list,
 	    OID_AUTO, "unallocated_queues", CTLTYPE_INT | CTLFLAG_RD,
 	    pf, 0, ixl_sysctl_unallocated_queues, "I",
 	    "Queues not allocated to a PF or VF");
 
 	SYSCTL_ADD_PROC(ctx, ctx_list,
 	    OID_AUTO, "tx_itr", CTLTYPE_INT | CTLFLAG_RW,
 	    pf, 0, ixl_sysctl_pf_tx_itr, "I",
 	    "Immediately set TX ITR value for all queues");
 
 	SYSCTL_ADD_PROC(ctx, ctx_list,
 	    OID_AUTO, "rx_itr", CTLTYPE_INT | CTLFLAG_RW,
 	    pf, 0, ixl_sysctl_pf_rx_itr, "I",
 	    "Immediately set RX ITR value for all queues");
 
 	SYSCTL_ADD_INT(ctx, ctx_list,
 	    OID_AUTO, "dynamic_rx_itr", CTLFLAG_RW,
 	    &pf->dynamic_rx_itr, 0, "Enable dynamic RX ITR");
 
 	SYSCTL_ADD_INT(ctx, ctx_list,
 	    OID_AUTO, "dynamic_tx_itr", CTLFLAG_RW,
 	    &pf->dynamic_tx_itr, 0, "Enable dynamic TX ITR");
 
 	/* Add FEC sysctls for 25G adapters */
 	/*
 	 * XXX: These settings can be changed, but that isn't supported,
 	 * so these are read-only for now.
 	 */
 	if (hw->device_id == I40E_DEV_ID_25G_B
 	    || hw->device_id == I40E_DEV_ID_25G_SFP28) {
 		fec_node = SYSCTL_ADD_NODE(ctx, ctx_list,
 		    OID_AUTO, "fec", CTLFLAG_RD, NULL, "FEC Sysctls");
 		fec_list = SYSCTL_CHILDREN(fec_node);
 
 		SYSCTL_ADD_PROC(ctx, fec_list,
 		    OID_AUTO, "fc_ability", CTLTYPE_INT | CTLFLAG_RD,
 		    pf, 0, ixl_sysctl_fec_fc_ability, "I", "FC FEC ability enabled");
 
 		SYSCTL_ADD_PROC(ctx, fec_list,
 		    OID_AUTO, "rs_ability", CTLTYPE_INT | CTLFLAG_RD,
 		    pf, 0, ixl_sysctl_fec_rs_ability, "I", "RS FEC ability enabled");
 
 		SYSCTL_ADD_PROC(ctx, fec_list,
 		    OID_AUTO, "fc_requested", CTLTYPE_INT | CTLFLAG_RD,
 		    pf, 0, ixl_sysctl_fec_fc_request, "I", "FC FEC mode requested on link");
 
 		SYSCTL_ADD_PROC(ctx, fec_list,
 		    OID_AUTO, "rs_requested", CTLTYPE_INT | CTLFLAG_RD,
 		    pf, 0, ixl_sysctl_fec_rs_request, "I", "RS FEC mode requested on link");
 
 		SYSCTL_ADD_PROC(ctx, fec_list,
 		    OID_AUTO, "auto_fec_enabled", CTLTYPE_INT | CTLFLAG_RD,
 		    pf, 0, ixl_sysctl_fec_auto_enable, "I", "Let FW decide FEC ability/request modes");
 	}
 
 	/* Add sysctls meant to print debug information, but don't list them
 	 * in "sysctl -a" output. */
 	debug_node = SYSCTL_ADD_NODE(ctx, ctx_list,
 	    OID_AUTO, "debug", CTLFLAG_RD | CTLFLAG_SKIP, NULL, "Debug Sysctls");
 	debug_list = SYSCTL_CHILDREN(debug_node);
 
 	SYSCTL_ADD_UINT(ctx, debug_list,
 	    OID_AUTO, "shared_debug_mask", CTLFLAG_RW,
 	    &pf->hw.debug_mask, 0, "Shared code debug message level");
 
 	SYSCTL_ADD_UINT(ctx, debug_list,
 	    OID_AUTO, "core_debug_mask", CTLFLAG_RW,
 	    &pf->dbg_mask, 0, "Non-hared code debug message level");
 
 	SYSCTL_ADD_PROC(ctx, debug_list,
 	    OID_AUTO, "link_status", CTLTYPE_STRING | CTLFLAG_RD,
 	    pf, 0, ixl_sysctl_link_status, "A", IXL_SYSCTL_HELP_LINK_STATUS);
 
 	SYSCTL_ADD_PROC(ctx, debug_list,
 	    OID_AUTO, "phy_abilities", CTLTYPE_STRING | CTLFLAG_RD,
 	    pf, 0, ixl_sysctl_phy_abilities, "A", "PHY Abilities");
 
 	SYSCTL_ADD_PROC(ctx, debug_list,
 	    OID_AUTO, "filter_list", CTLTYPE_STRING | CTLFLAG_RD,
 	    pf, 0, ixl_sysctl_sw_filter_list, "A", "SW Filter List");
 
 	SYSCTL_ADD_PROC(ctx, debug_list,
 	    OID_AUTO, "hw_res_alloc", CTLTYPE_STRING | CTLFLAG_RD,
 	    pf, 0, ixl_sysctl_hw_res_alloc, "A", "HW Resource Allocation");
 
 	SYSCTL_ADD_PROC(ctx, debug_list,
 	    OID_AUTO, "switch_config", CTLTYPE_STRING | CTLFLAG_RD,
 	    pf, 0, ixl_sysctl_switch_config, "A", "HW Switch Configuration");
 
 	SYSCTL_ADD_PROC(ctx, debug_list,
 	    OID_AUTO, "rss_key", CTLTYPE_STRING | CTLFLAG_RD,
 	    pf, 0, ixl_sysctl_hkey, "A", "View RSS key");
 
 	SYSCTL_ADD_PROC(ctx, debug_list,
 	    OID_AUTO, "rss_lut", CTLTYPE_STRING | CTLFLAG_RD,
 	    pf, 0, ixl_sysctl_hlut, "A", "View RSS lookup table");
 
 	SYSCTL_ADD_PROC(ctx, debug_list,
 	    OID_AUTO, "rss_hena", CTLTYPE_ULONG | CTLFLAG_RD,
 	    pf, 0, ixl_sysctl_hena, "LU", "View enabled packet types for RSS");
 
 	SYSCTL_ADD_PROC(ctx, debug_list,
 	    OID_AUTO, "disable_fw_link_management", CTLTYPE_INT | CTLFLAG_WR,
 	    pf, 0, ixl_sysctl_fw_link_management, "I", "Disable FW Link Management");
 
 	if (pf->has_i2c) {
 		SYSCTL_ADD_PROC(ctx, debug_list,
 		    OID_AUTO, "read_i2c_byte", CTLTYPE_INT | CTLFLAG_RW,
 		    pf, 0, ixl_sysctl_read_i2c_byte, "I", "Read byte from I2C bus");
 
 		SYSCTL_ADD_PROC(ctx, debug_list,
 		    OID_AUTO, "write_i2c_byte", CTLTYPE_INT | CTLFLAG_RW,
 		    pf, 0, ixl_sysctl_write_i2c_byte, "I", "Write byte to I2C bus");
 	}
 
 #ifdef PCI_IOV
 	SYSCTL_ADD_UINT(ctx, debug_list,
 	    OID_AUTO, "vc_debug_level", CTLFLAG_RW, &pf->vc_debug_lvl,
 	    0, "PF/VF Virtual Channel debug level");
 #endif
 }
 
 /*
  * Primarily for finding out how many queues can be assigned to VFs,
  * at runtime.
  */
 static int
 ixl_sysctl_unallocated_queues(SYSCTL_HANDLER_ARGS)
 {
 	struct ixl_pf *pf = (struct ixl_pf *)arg1;
 	int queues;
 
 	IXL_PF_LOCK(pf);
 	queues = (int)ixl_pf_qmgr_get_num_free(&pf->qmgr);
 	IXL_PF_UNLOCK(pf);
 
 	return sysctl_handle_int(oidp, NULL, queues, req);
 }
 
 /*
 ** Set flow control using sysctl:
 ** 	0 - off
 **	1 - rx pause
 **	2 - tx pause
 **	3 - full
 */
 int
 ixl_set_flowcntl(SYSCTL_HANDLER_ARGS)
 {
 	struct ixl_pf *pf = (struct ixl_pf *)arg1;
 	struct i40e_hw *hw = &pf->hw;
 	device_t dev = pf->dev;
 	int requested_fc, error = 0;
 	enum i40e_status_code aq_error = 0;
 	u8 fc_aq_err = 0;
 
 	/* Get request */
 	requested_fc = pf->fc;
 	error = sysctl_handle_int(oidp, &requested_fc, 0, req);
 	if ((error) || (req->newptr == NULL))
 		return (error);
 	if (requested_fc < 0 || requested_fc > 3) {
 		device_printf(dev,
 		    "Invalid fc mode; valid modes are 0 through 3\n");
 		return (EINVAL);
 	}
 
 	/* Set fc ability for port */
 	hw->fc.requested_mode = requested_fc;
 	aq_error = i40e_set_fc(hw, &fc_aq_err, TRUE);
 	if (aq_error) {
 		device_printf(dev,
 		    "%s: Error setting new fc mode %d; fc_err %#x\n",
 		    __func__, aq_error, fc_aq_err);
 		return (EIO);
 	}
 	pf->fc = requested_fc;
 
 	/* Get new link state */
 	i40e_msec_delay(250);
 	hw->phy.get_link_info = TRUE;
 	i40e_get_link_status(hw, &pf->link_up);
 
 	return (0);
 }
 
 char *
 ixl_aq_speed_to_str(enum i40e_aq_link_speed link_speed)
 {
 	int index;
 
 	char *speeds[] = {
 		"Unknown",
 		"100 Mbps",
 		"1 Gbps",
 		"10 Gbps",
 		"40 Gbps",
 		"20 Gbps",
 		"25 Gbps",
 	};
 
 	switch (link_speed) {
 	case I40E_LINK_SPEED_100MB:
 		index = 1;
 		break;
 	case I40E_LINK_SPEED_1GB:
 		index = 2;
 		break;
 	case I40E_LINK_SPEED_10GB:
 		index = 3;
 		break;
 	case I40E_LINK_SPEED_40GB:
 		index = 4;
 		break;
 	case I40E_LINK_SPEED_20GB:
 		index = 5;
 		break;
 	case I40E_LINK_SPEED_25GB:
 		index = 6;
 		break;
 	case I40E_LINK_SPEED_UNKNOWN:
 	default:
 		index = 0;
 		break;
 	}
 
 	return speeds[index];
 }
 
 int
 ixl_current_speed(SYSCTL_HANDLER_ARGS)
 {
 	struct ixl_pf *pf = (struct ixl_pf *)arg1;
 	struct i40e_hw *hw = &pf->hw;
 	int error = 0;
 
 	ixl_update_link_status(pf);
 
 	error = sysctl_handle_string(oidp,
 	    ixl_aq_speed_to_str(hw->phy.link_info.link_speed),
 	    8, req);
 	return (error);
 }
 
 static u8
 ixl_convert_sysctl_aq_link_speed(u8 speeds, bool to_aq)
 {
 	static u16 speedmap[6] = {
 		(I40E_LINK_SPEED_100MB | (0x1 << 8)),
 		(I40E_LINK_SPEED_1GB   | (0x2 << 8)),
 		(I40E_LINK_SPEED_10GB  | (0x4 << 8)),
 		(I40E_LINK_SPEED_20GB  | (0x8 << 8)),
 		(I40E_LINK_SPEED_25GB  | (0x10 << 8)),
 		(I40E_LINK_SPEED_40GB  | (0x20 << 8))
 	};
 	u8 retval = 0;
 
 	for (int i = 0; i < 6; i++) {
 		if (to_aq)
 			retval |= (speeds & (speedmap[i] >> 8)) ? (speedmap[i] & 0xff) : 0;
 		else
 			retval |= (speeds & speedmap[i]) ? (speedmap[i] >> 8) : 0;
 	}
 
 	return (retval);
 }
 
 int
 ixl_set_advertised_speeds(struct ixl_pf *pf, int speeds)
 {
 	struct i40e_hw *hw = &pf->hw;
 	device_t dev = pf->dev;
 	struct i40e_aq_get_phy_abilities_resp abilities;
 	struct i40e_aq_set_phy_config config;
 	enum i40e_status_code aq_error = 0;
 
 	/* Get current capability information */
 	aq_error = i40e_aq_get_phy_capabilities(hw,
 	    FALSE, FALSE, &abilities, NULL);
 	if (aq_error) {
 		device_printf(dev,
 		    "%s: Error getting phy capabilities %d,"
 		    " aq error: %d\n", __func__, aq_error,
 		    hw->aq.asq_last_status);
 		return (EIO);
 	}
 
 	/* Prepare new config */
 	bzero(&config, sizeof(config));
 	config.link_speed = ixl_convert_sysctl_aq_link_speed(speeds, true);
 	config.phy_type = abilities.phy_type;
 	config.phy_type_ext = abilities.phy_type_ext;
 	config.abilities = abilities.abilities
 	    | I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
 	config.eee_capability = abilities.eee_capability;
 	config.eeer = abilities.eeer_val;
 	config.low_power_ctrl = abilities.d3_lpan;
 
 	/* Do aq command & restart link */
 	aq_error = i40e_aq_set_phy_config(hw, &config, NULL);
 	if (aq_error) {
 		device_printf(dev,
 		    "%s: Error setting new phy config %d,"
 		    " aq error: %d\n", __func__, aq_error,
 		    hw->aq.asq_last_status);
 		return (EIO);
 	}
 
 	return (0);
 }
 
 /*
 ** Control link advertise speed:
 **	Flags:
 **	 0x1 - advertise 100 Mb
 **	 0x2 - advertise 1G
 **	 0x4 - advertise 10G
 **	 0x8 - advertise 20G
 **	0x10 - advertise 25G
 **	0x20 - advertise 40G
 **
 **	Set to 0 to disable link
 */
 int
 ixl_set_advertise(SYSCTL_HANDLER_ARGS)
 {
 	struct ixl_pf *pf = (struct ixl_pf *)arg1;
 	struct i40e_hw *hw = &pf->hw;
 	device_t dev = pf->dev;
 	u8 converted_speeds;
 	int requested_ls = 0;
 	int error = 0;
 
 	/* Read in new mode */
 	requested_ls = pf->advertised_speed;
 	error = sysctl_handle_int(oidp, &requested_ls, 0, req);
 	if ((error) || (req->newptr == NULL))
 		return (error);
 	/* Check if changing speeds is supported */
 	switch (hw->device_id) {
 	case I40E_DEV_ID_25G_B:
 	case I40E_DEV_ID_25G_SFP28:
 		device_printf(dev, "Changing advertised speeds not supported"
 		" on this device.\n");
 		return (EINVAL);
 	}
 	if (requested_ls < 0 || requested_ls > 0xff) {
 	}
 
 	/* Check for valid value */
 	converted_speeds = ixl_convert_sysctl_aq_link_speed((u8)requested_ls, true);
 	if ((converted_speeds | pf->supported_speeds) != pf->supported_speeds) {
 		device_printf(dev, "Invalid advertised speed; "
 		    "valid flags are: 0x%02x\n",
 		    ixl_convert_sysctl_aq_link_speed(pf->supported_speeds, false));
 		return (EINVAL);
 	}
 
 	error = ixl_set_advertised_speeds(pf, requested_ls);
 	if (error)
 		return (error);
 
 	pf->advertised_speed = requested_ls;
 	ixl_update_link_status(pf);
 	return (0);
 }
 
 /*
  * Input: bitmap of enum i40e_aq_link_speed
  */
 static u64
 ixl_max_aq_speed_to_value(u8 link_speeds)
 {
 	if (link_speeds & I40E_LINK_SPEED_40GB)
 		return IF_Gbps(40);
 	if (link_speeds & I40E_LINK_SPEED_25GB)
 		return IF_Gbps(25);
 	if (link_speeds & I40E_LINK_SPEED_20GB)
 		return IF_Gbps(20);
 	if (link_speeds & I40E_LINK_SPEED_10GB)
 		return IF_Gbps(10);
 	if (link_speeds & I40E_LINK_SPEED_1GB)
 		return IF_Gbps(1);
 	if (link_speeds & I40E_LINK_SPEED_100MB)
 		return IF_Mbps(100);
 	else
 		/* Minimum supported link speed */
 		return IF_Mbps(100);
 }
 
 /*
 ** Get the width and transaction speed of
 ** the bus this adapter is plugged into.
 */
 void
 ixl_get_bus_info(struct ixl_pf *pf)
 {
 	struct i40e_hw *hw = &pf->hw;
 	device_t dev = pf->dev;
         u16 link;
         u32 offset, num_ports;
 	u64 max_speed;
 
 	/* Some devices don't use PCIE */
 	if (hw->mac.type == I40E_MAC_X722)
 		return;
 
         /* Read PCI Express Capabilities Link Status Register */
         pci_find_cap(dev, PCIY_EXPRESS, &offset);
         link = pci_read_config(dev, offset + PCIER_LINK_STA, 2);
 
 	/* Fill out hw struct with PCIE info */
 	i40e_set_pci_config_data(hw, link);
 
 	/* Use info to print out bandwidth messages */
         device_printf(dev,"PCI Express Bus: Speed %s %s\n",
             ((hw->bus.speed == i40e_bus_speed_8000) ? "8.0GT/s":
             (hw->bus.speed == i40e_bus_speed_5000) ? "5.0GT/s":
             (hw->bus.speed == i40e_bus_speed_2500) ? "2.5GT/s":"Unknown"),
             (hw->bus.width == i40e_bus_width_pcie_x8) ? "Width x8" :
             (hw->bus.width == i40e_bus_width_pcie_x4) ? "Width x4" :
             (hw->bus.width == i40e_bus_width_pcie_x2) ? "Width x2" :
             (hw->bus.width == i40e_bus_width_pcie_x1) ? "Width x1" :
             ("Unknown"));
 
 	/*
 	 * If adapter is in slot with maximum supported speed,
 	 * no warning message needs to be printed out.
 	 */
 	if (hw->bus.speed >= i40e_bus_speed_8000
 	    && hw->bus.width >= i40e_bus_width_pcie_x8)
 		return;
 
 	num_ports = bitcount32(hw->func_caps.valid_functions);
 	max_speed = ixl_max_aq_speed_to_value(pf->supported_speeds) / 1000000;
 
 	if ((num_ports * max_speed) > hw->bus.speed * hw->bus.width) {
                 device_printf(dev, "PCI-Express bandwidth available"
                     " for this device may be insufficient for"
                     " optimal performance.\n");
                 device_printf(dev, "Please move the device to a different"
 		    " PCI-e link with more lanes and/or higher"
 		    " transfer rate.\n");
         }
 }
 
 static int
 ixl_sysctl_show_fw(SYSCTL_HANDLER_ARGS)
 {
 	struct ixl_pf	*pf = (struct ixl_pf *)arg1;
 	struct i40e_hw	*hw = &pf->hw;
 	struct sbuf	*sbuf;
 
 	sbuf = sbuf_new_for_sysctl(NULL, NULL, 128, req);
 	ixl_nvm_version_str(hw, sbuf);
 	sbuf_finish(sbuf);
 	sbuf_delete(sbuf);
 
 	return 0;
 }
 
 void
 ixl_print_nvm_cmd(device_t dev, struct i40e_nvm_access *nvma)
 {
 	if ((nvma->command == I40E_NVM_READ) &&
 	    ((nvma->config & 0xFF) == 0xF) &&
 	    (((nvma->config & 0xF00) >> 8) == 0xF) &&
 	    (nvma->offset == 0) &&
 	    (nvma->data_size == 1)) {
 		// device_printf(dev, "- Get Driver Status Command\n");
 	}
 	else if (nvma->command == I40E_NVM_READ) {
 	
 	}
 	else {
 		switch (nvma->command) {
 		case 0xB:
 			device_printf(dev, "- command: I40E_NVM_READ\n");
 			break;
 		case 0xC:
 			device_printf(dev, "- command: I40E_NVM_WRITE\n");
 			break;
 		default:
 			device_printf(dev, "- command: unknown 0x%08x\n", nvma->command);
 			break;
 		}
 
 		device_printf(dev, "- config (ptr)  : 0x%02x\n", nvma->config & 0xFF);
 		device_printf(dev, "- config (flags): 0x%01x\n", (nvma->config & 0xF00) >> 8);
 		device_printf(dev, "- offset : 0x%08x\n", nvma->offset);
 		device_printf(dev, "- data_s : 0x%08x\n", nvma->data_size);
 	}
 }
 
 int
 ixl_handle_nvmupd_cmd(struct ixl_pf *pf, struct ifdrv *ifd)
 {
 	struct i40e_hw *hw = &pf->hw;
 	struct i40e_nvm_access *nvma;
 	device_t dev = pf->dev;
 	enum i40e_status_code status = 0;
 	int perrno;
 
 	DEBUGFUNC("ixl_handle_nvmupd_cmd");
 
 	/* Sanity checks */
 	if (ifd->ifd_len < sizeof(struct i40e_nvm_access) ||
 	    ifd->ifd_data == NULL) {
 		device_printf(dev, "%s: incorrect ifdrv length or data pointer\n",
 		    __func__);
 		device_printf(dev, "%s: ifdrv length: %lu, sizeof(struct i40e_nvm_access): %lu\n",
 		    __func__, ifd->ifd_len, sizeof(struct i40e_nvm_access));
 		device_printf(dev, "%s: data pointer: %p\n", __func__,
 		    ifd->ifd_data);
 		return (EINVAL);
 	}
 
 	nvma = (struct i40e_nvm_access *)ifd->ifd_data;
 
 	if (pf->dbg_mask & IXL_DBG_NVMUPD)
 		ixl_print_nvm_cmd(dev, nvma);
 
 	if (pf->state & IXL_PF_STATE_EMPR_RESETTING) {
 		int count = 0;
 		while (count++ < 100) {
 			i40e_msec_delay(100);
 			if (!(pf->state & IXL_PF_STATE_EMPR_RESETTING))
 				break;
 		}
 	}
 
 	if (!(pf->state & IXL_PF_STATE_EMPR_RESETTING)) {
 		IXL_PF_LOCK(pf);
 		status = i40e_nvmupd_command(hw, nvma, nvma->data, &perrno);
 		IXL_PF_UNLOCK(pf);
 	} else {
 		perrno = -EBUSY;
 	}
 
 	if (status)
 		device_printf(dev, "i40e_nvmupd_command status %s, perrno %d\n",
 		    i40e_stat_str(hw, status), perrno);
 
 	/*
 	 * -EPERM is actually ERESTART, which the kernel interprets as it needing
 	 * to run this ioctl again. So use -EACCES for -EPERM instead.
 	 */
 	if (perrno == -EPERM)
 		return (-EACCES);
 	else
 		return (perrno);
 }
 
 /*********************************************************************
  *
  *  Media Ioctl callback
  *
  *  This routine is called whenever the user queries the status of
  *  the interface using ifconfig.
  *
  **********************************************************************/
 void
 ixl_media_status(struct ifnet * ifp, struct ifmediareq * ifmr)
 {
 	struct ixl_vsi	*vsi = ifp->if_softc;
 	struct ixl_pf	*pf = vsi->back;
 	struct i40e_hw  *hw = &pf->hw;
 
 	INIT_DEBUGOUT("ixl_media_status: begin");
 	IXL_PF_LOCK(pf);
 
 	hw->phy.get_link_info = TRUE;
 	i40e_get_link_status(hw, &pf->link_up);
 	ixl_update_link_status(pf);
 
 	ifmr->ifm_status = IFM_AVALID;
 	ifmr->ifm_active = IFM_ETHER;
 
 	if (!pf->link_up) {
 		IXL_PF_UNLOCK(pf);
 		return;
 	}
 
 	ifmr->ifm_status |= IFM_ACTIVE;
 
 	/* Hardware always does full-duplex */
 	ifmr->ifm_active |= IFM_FDX;
 
 	switch (hw->phy.link_info.phy_type) {
 		/* 100 M */
 		case I40E_PHY_TYPE_100BASE_TX:
 			ifmr->ifm_active |= IFM_100_TX;
 			break;
 		/* 1 G */
 		case I40E_PHY_TYPE_1000BASE_T:
 			ifmr->ifm_active |= IFM_1000_T;
 			break;
 		case I40E_PHY_TYPE_1000BASE_SX:
 			ifmr->ifm_active |= IFM_1000_SX;
 			break;
 		case I40E_PHY_TYPE_1000BASE_LX:
 			ifmr->ifm_active |= IFM_1000_LX;
 			break;
 		case I40E_PHY_TYPE_1000BASE_T_OPTICAL:
 			ifmr->ifm_active |= IFM_OTHER;
 			break;
 		/* 10 G */
 		case I40E_PHY_TYPE_10GBASE_SFPP_CU:
 			ifmr->ifm_active |= IFM_10G_TWINAX;
 			break;
 		case I40E_PHY_TYPE_10GBASE_SR:
 			ifmr->ifm_active |= IFM_10G_SR;
 			break;
 		case I40E_PHY_TYPE_10GBASE_LR:
 			ifmr->ifm_active |= IFM_10G_LR;
 			break;
 		case I40E_PHY_TYPE_10GBASE_T:
 			ifmr->ifm_active |= IFM_10G_T;
 			break;
 		case I40E_PHY_TYPE_XAUI:
 		case I40E_PHY_TYPE_XFI:
 		case I40E_PHY_TYPE_10GBASE_AOC:
 			ifmr->ifm_active |= IFM_OTHER;
 			break;
 		/* 25 G */
 		case I40E_PHY_TYPE_25GBASE_KR:
 			ifmr->ifm_active |= IFM_25G_KR;
 			break;
 		case I40E_PHY_TYPE_25GBASE_CR:
 			ifmr->ifm_active |= IFM_25G_CR;
 			break;
 		case I40E_PHY_TYPE_25GBASE_SR:
 			ifmr->ifm_active |= IFM_25G_SR;
 			break;
 		case I40E_PHY_TYPE_25GBASE_LR:
 			ifmr->ifm_active |= IFM_UNKNOWN;
 			break;
 		/* 40 G */
 		case I40E_PHY_TYPE_40GBASE_CR4:
 		case I40E_PHY_TYPE_40GBASE_CR4_CU:
 			ifmr->ifm_active |= IFM_40G_CR4;
 			break;
 		case I40E_PHY_TYPE_40GBASE_SR4:
 			ifmr->ifm_active |= IFM_40G_SR4;
 			break;
 		case I40E_PHY_TYPE_40GBASE_LR4:
 			ifmr->ifm_active |= IFM_40G_LR4;
 			break;
 		case I40E_PHY_TYPE_XLAUI:
 			ifmr->ifm_active |= IFM_OTHER;
 			break;
 		case I40E_PHY_TYPE_1000BASE_KX:
 			ifmr->ifm_active |= IFM_1000_KX;
 			break;
 		case I40E_PHY_TYPE_SGMII:
 			ifmr->ifm_active |= IFM_1000_SGMII;
 			break;
 		/* ERJ: What's the difference between these? */
 		case I40E_PHY_TYPE_10GBASE_CR1_CU:
 		case I40E_PHY_TYPE_10GBASE_CR1:
 			ifmr->ifm_active |= IFM_10G_CR1;
 			break;
 		case I40E_PHY_TYPE_10GBASE_KX4:
 			ifmr->ifm_active |= IFM_10G_KX4;
 			break;
 		case I40E_PHY_TYPE_10GBASE_KR:
 			ifmr->ifm_active |= IFM_10G_KR;
 			break;
 		case I40E_PHY_TYPE_SFI:
 			ifmr->ifm_active |= IFM_10G_SFI;
 			break;
 		/* Our single 20G media type */
 		case I40E_PHY_TYPE_20GBASE_KR2:
 			ifmr->ifm_active |= IFM_20G_KR2;
 			break;
 		case I40E_PHY_TYPE_40GBASE_KR4:
 			ifmr->ifm_active |= IFM_40G_KR4;
 			break;
 		case I40E_PHY_TYPE_XLPPI:
 		case I40E_PHY_TYPE_40GBASE_AOC:
 			ifmr->ifm_active |= IFM_40G_XLPPI;
 			break;
 		/* Unknown to driver */
 		default:
 			ifmr->ifm_active |= IFM_UNKNOWN;
 			break;
 	}
 	/* Report flow control status as well */
 	if (hw->phy.link_info.an_info & I40E_AQ_LINK_PAUSE_TX)
 		ifmr->ifm_active |= IFM_ETH_TXPAUSE;
 	if (hw->phy.link_info.an_info & I40E_AQ_LINK_PAUSE_RX)
 		ifmr->ifm_active |= IFM_ETH_RXPAUSE;
 
 	IXL_PF_UNLOCK(pf);
 }
 
 void
 ixl_init(void *arg)
 {
 	struct ixl_pf *pf = arg;
 
 	IXL_PF_LOCK(pf);
 	ixl_init_locked(pf);
 	IXL_PF_UNLOCK(pf);
 }
 
 /*
  * NOTE: Fortville does not support forcing media speeds. Instead,
  * use the set_advertise sysctl to set the speeds Fortville
  * will advertise or be allowed to operate at.
  */
 int
 ixl_media_change(struct ifnet * ifp)
 {
 	struct ixl_vsi *vsi = ifp->if_softc;
 	struct ifmedia *ifm = &vsi->media;
 
 	INIT_DEBUGOUT("ixl_media_change: begin");
 
 	if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER)
 		return (EINVAL);
 
 	if_printf(ifp, "Use 'advertise_speed' sysctl to change advertised speeds\n");
 
 	return (ENODEV);
 }
 
 /*********************************************************************
  *  Ioctl entry point
  *
  *  ixl_ioctl is called when the user wants to configure the
  *  interface.
  *
  *  return 0 on success, positive on failure
  **********************************************************************/
 
 int
 ixl_ioctl(struct ifnet * ifp, u_long command, caddr_t data)
 {
 	struct ixl_vsi	*vsi = ifp->if_softc;
 	struct ixl_pf	*pf = vsi->back;
 	struct ifreq	*ifr = (struct ifreq *)data;
 	struct ifdrv	*ifd = (struct ifdrv *)data;
 #if defined(INET) || defined(INET6)
 	struct ifaddr *ifa = (struct ifaddr *)data;
 	bool		avoid_reset = FALSE;
 #endif
 	int             error = 0;
 
 	switch (command) {
 
         case SIOCSIFADDR:
 		IOCTL_DEBUGOUT("ioctl: SIOCSIFADDR (Set Interface Address)");
 #ifdef INET
 		if (ifa->ifa_addr->sa_family == AF_INET)
 			avoid_reset = TRUE;
 #endif
 #ifdef INET6
 		if (ifa->ifa_addr->sa_family == AF_INET6)
 			avoid_reset = TRUE;
 #endif
 #if defined(INET) || defined(INET6)
 		/*
 		** Calling init results in link renegotiation,
 		** so we avoid doing it when possible.
 		*/
 		if (avoid_reset) {
 			ifp->if_flags |= IFF_UP;
 			if (!(ifp->if_drv_flags & IFF_DRV_RUNNING))
 				ixl_init(pf);
 #ifdef INET
 			if (!(ifp->if_flags & IFF_NOARP))
 				arp_ifinit(ifp, ifa);
 #endif
 		} else
 			error = ether_ioctl(ifp, command, data);
 		break;
 #endif
 	case SIOCSIFMTU:
 		IOCTL_DEBUGOUT("ioctl: SIOCSIFMTU (Set Interface MTU)");
 		if (ifr->ifr_mtu > IXL_MAX_FRAME -
 		   ETHER_HDR_LEN - ETHER_CRC_LEN - ETHER_VLAN_ENCAP_LEN) {
 			error = EINVAL;
 		} else {
 			IXL_PF_LOCK(pf);
 			ifp->if_mtu = ifr->ifr_mtu;
 			vsi->max_frame_size =
 				ifp->if_mtu + ETHER_HDR_LEN + ETHER_CRC_LEN
 			    + ETHER_VLAN_ENCAP_LEN;
 			if (ifp->if_drv_flags & IFF_DRV_RUNNING)
 				ixl_init_locked(pf);
 			IXL_PF_UNLOCK(pf);
 		}
 		break;
 	case SIOCSIFFLAGS:
 		IOCTL_DEBUGOUT("ioctl: SIOCSIFFLAGS (Set Interface Flags)");
 		IXL_PF_LOCK(pf);
 		if (ifp->if_flags & IFF_UP) {
 			if ((ifp->if_drv_flags & IFF_DRV_RUNNING)) {
 				if ((ifp->if_flags ^ pf->if_flags) &
 				    (IFF_PROMISC | IFF_ALLMULTI)) {
 					ixl_set_promisc(vsi);
 				}
 			} else {
 				IXL_PF_UNLOCK(pf);
 				ixl_init(pf);
 				IXL_PF_LOCK(pf);
 			}
 		} else {
 			if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
 				ixl_stop_locked(pf);
 			}
 		}
 		pf->if_flags = ifp->if_flags;
 		IXL_PF_UNLOCK(pf);
 		break;
 	case SIOCSDRVSPEC:
 	case SIOCGDRVSPEC:
 		IOCTL_DEBUGOUT("ioctl: SIOCxDRVSPEC (Get/Set Driver-specific "
 		    "Info)\n");
 
 		/* NVM update command */
 		if (ifd->ifd_cmd == I40E_NVM_ACCESS)
 			error = ixl_handle_nvmupd_cmd(pf, ifd);
 		else
 			error = EINVAL;
 		break;
 	case SIOCADDMULTI:
 		IOCTL_DEBUGOUT("ioctl: SIOCADDMULTI");
 		if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
 			IXL_PF_LOCK(pf);
 			ixl_disable_rings_intr(vsi);
 			ixl_add_multi(vsi);
 			ixl_enable_intr(vsi);
 			IXL_PF_UNLOCK(pf);
 		}
 		break;
 	case SIOCDELMULTI:
 		IOCTL_DEBUGOUT("ioctl: SIOCDELMULTI");
 		if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
 			IXL_PF_LOCK(pf);
 			ixl_disable_rings_intr(vsi);
 			ixl_del_multi(vsi);
 			ixl_enable_intr(vsi);
 			IXL_PF_UNLOCK(pf);
 		}
 		break;
 	case SIOCSIFMEDIA:
 	case SIOCGIFMEDIA:
 	case SIOCGIFXMEDIA:
 		IOCTL_DEBUGOUT("ioctl: SIOCxIFMEDIA (Get/Set Interface Media)");
 		error = ifmedia_ioctl(ifp, ifr, &vsi->media, command);
 		break;
 	case SIOCSIFCAP:
 	{
 		int mask = ifr->ifr_reqcap ^ ifp->if_capenable;
 		IOCTL_DEBUGOUT("ioctl: SIOCSIFCAP (Set Capabilities)");
 
 		ixl_cap_txcsum_tso(vsi, ifp, mask);
 
 		if (mask & IFCAP_RXCSUM)
 			ifp->if_capenable ^= IFCAP_RXCSUM;
 		if (mask & IFCAP_RXCSUM_IPV6)
 			ifp->if_capenable ^= IFCAP_RXCSUM_IPV6;
 		if (mask & IFCAP_LRO)
 			ifp->if_capenable ^= IFCAP_LRO;
 		if (mask & IFCAP_VLAN_HWTAGGING)
 			ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING;
 		if (mask & IFCAP_VLAN_HWFILTER)
 			ifp->if_capenable ^= IFCAP_VLAN_HWFILTER;
 		if (mask & IFCAP_VLAN_HWTSO)
 			ifp->if_capenable ^= IFCAP_VLAN_HWTSO;
 		if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
 			IXL_PF_LOCK(pf);
 			ixl_init_locked(pf);
 			IXL_PF_UNLOCK(pf);
 		}
 		VLAN_CAPABILITIES(ifp);
 
 		break;
 	}
 #if __FreeBSD_version >= 1003000
 	case SIOCGI2C:
 	{
 		struct ifi2creq i2c;
 		int i;
 
 		IOCTL_DEBUGOUT("ioctl: SIOCGI2C (Get I2C Data)");
 		if (!pf->has_i2c)
 			return (ENOTTY);
 
 		error = copyin(ifr->ifr_data, &i2c, sizeof(i2c));
 		if (error != 0)
 			break;
 		if (i2c.dev_addr != 0xA0 && i2c.dev_addr != 0xA2) {
 			error = EINVAL;
 			break;
 		}
 		if (i2c.len > sizeof(i2c.data)) {
 			error = EINVAL;
 			break;
 		}
 
 		for (i = 0; i < i2c.len; i++)
 			if (ixl_read_i2c_byte(pf, i2c.offset + i,
 			    i2c.dev_addr, &i2c.data[i]))
 				return (EIO);
 
 		error = copyout(&i2c, ifr->ifr_data, sizeof(i2c));
 		break;
 	}
 #endif
 	default:
 		IOCTL_DEBUGOUT("ioctl: UNKNOWN (0x%X)\n", (int)command);
 		error = ether_ioctl(ifp, command, data);
 		break;
 	}
 
 	return (error);
 }
 
 int
 ixl_find_i2c_interface(struct ixl_pf *pf)
 {
 	struct i40e_hw *hw = &pf->hw;
 	bool i2c_en, port_matched;
 	u32 reg;
 
 	for (int i = 0; i < 4; i++) {
 		reg = rd32(hw, I40E_GLGEN_MDIO_I2C_SEL(i));
 		i2c_en = (reg & I40E_GLGEN_MDIO_I2C_SEL_MDIO_I2C_SEL_MASK);
 		port_matched = ((reg & I40E_GLGEN_MDIO_I2C_SEL_PHY_PORT_NUM_MASK)
 		    >> I40E_GLGEN_MDIO_I2C_SEL_PHY_PORT_NUM_SHIFT)
 		    & BIT(hw->port);
 		if (i2c_en && port_matched)
 			return (i);
 	}
 
 	return (-1);
 }
 
 static char *
 ixl_phy_type_string(u32 bit_pos, bool ext)
 {
 	static char * phy_types_str[32] = {
 		"SGMII",
 		"1000BASE-KX",
 		"10GBASE-KX4",
 		"10GBASE-KR",
 		"40GBASE-KR4",
 		"XAUI",
 		"XFI",
 		"SFI",
 		"XLAUI",
 		"XLPPI",
 		"40GBASE-CR4",
 		"10GBASE-CR1",
 		"Reserved (12)",
 		"Reserved (13)",
 		"Reserved (14)",
 		"Reserved (15)",
 		"Reserved (16)",
 		"100BASE-TX",
 		"1000BASE-T",
 		"10GBASE-T",
 		"10GBASE-SR",
 		"10GBASE-LR",
 		"10GBASE-SFP+Cu",
 		"10GBASE-CR1",
 		"40GBASE-CR4",
 		"40GBASE-SR4",
 		"40GBASE-LR4",
 		"1000BASE-SX",
 		"1000BASE-LX",
 		"1000BASE-T Optical",
 		"20GBASE-KR2",
 		"Reserved (31)"
 	};
 	static char * ext_phy_types_str[4] = {
 		"25GBASE-KR",
 		"25GBASE-CR",
 		"25GBASE-SR",
 		"25GBASE-LR"
 	};
 
 	if (ext && bit_pos > 3) return "Invalid_Ext";
 	if (bit_pos > 31) return "Invalid";
 
 	return (ext) ? ext_phy_types_str[bit_pos] : phy_types_str[bit_pos];
 }
 
 int
 ixl_aq_get_link_status(struct ixl_pf *pf, struct i40e_aqc_get_link_status *link_status)
 {
 	device_t dev = pf->dev;
 	struct i40e_hw *hw = &pf->hw;
 	struct i40e_aq_desc desc;
 	enum i40e_status_code status;
 
 	struct i40e_aqc_get_link_status *aq_link_status =
 		(struct i40e_aqc_get_link_status *)&desc.params.raw;
 
 	i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_link_status);
 	link_status->command_flags = CPU_TO_LE16(I40E_AQ_LSE_ENABLE);
 	status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
 	if (status) {
 		device_printf(dev,
 		    "%s: i40e_aqc_opc_get_link_status status %s, aq error %s\n",
 		    __func__, i40e_stat_str(hw, status),
 		    i40e_aq_str(hw, hw->aq.asq_last_status));
 		return (EIO);
 	}
 
 	bcopy(aq_link_status, link_status, sizeof(struct i40e_aqc_get_link_status));
 	return (0);
 }
 
 static char *
 ixl_phy_type_string_ls(u8 val)
 {
 	if (val >= 0x1F)
 		return ixl_phy_type_string(val - 0x1F, true);
 	else
 		return ixl_phy_type_string(val, false);
 }
 
 static int
 ixl_sysctl_link_status(SYSCTL_HANDLER_ARGS)
 {
 	struct ixl_pf *pf = (struct ixl_pf *)arg1;
 	device_t dev = pf->dev;
 	struct sbuf *buf;
 	int error = 0;
 
 	buf = sbuf_new_for_sysctl(NULL, NULL, 128, req);
 	if (!buf) {
 		device_printf(dev, "Could not allocate sbuf for sysctl output.\n");
 		return (ENOMEM);
 	}
 
 	struct i40e_aqc_get_link_status link_status;
 	error = ixl_aq_get_link_status(pf, &link_status);
 	if (error) {
 		sbuf_delete(buf);
 		return (error);
 	}
 
 	/* TODO: Add 25G types */
 	sbuf_printf(buf, "\n"
 	    "PHY Type : 0x%02x<%s>\n"
 	    "Speed    : 0x%02x\n"
 	    "Link info: 0x%02x\n"
 	    "AN info  : 0x%02x\n"
 	    "Ext info : 0x%02x\n"
 	    "Loopback : 0x%02x\n"
 	    "Max Frame: %d\n"
 	    "Config   : 0x%02x\n"
 	    "Power    : 0x%02x",
 	    link_status.phy_type,
 	    ixl_phy_type_string_ls(link_status.phy_type),
 	    link_status.link_speed, 
 	    link_status.link_info,
 	    link_status.an_info,
 	    link_status.ext_info,
 	    link_status.loopback,
 	    link_status.max_frame_size,
 	    link_status.config,
 	    link_status.power_desc);
 
 	error = sbuf_finish(buf);
 	if (error)
 		device_printf(dev, "Error finishing sbuf: %d\n", error);
 
 	sbuf_delete(buf);
 	return (error);
 }
 
 static int
 ixl_sysctl_phy_abilities(SYSCTL_HANDLER_ARGS)
 {
 	struct ixl_pf *pf = (struct ixl_pf *)arg1;
 	struct i40e_hw *hw = &pf->hw;
 	device_t dev = pf->dev;
 	enum i40e_status_code status;
 	struct i40e_aq_get_phy_abilities_resp abilities;
 	struct sbuf *buf;
 	int error = 0;
 
 	buf = sbuf_new_for_sysctl(NULL, NULL, 128, req);
 	if (!buf) {
 		device_printf(dev, "Could not allocate sbuf for sysctl output.\n");
 		return (ENOMEM);
 	}
 
 	status = i40e_aq_get_phy_capabilities(hw,
 	    FALSE, FALSE, &abilities, NULL);
 	if (status) {
 		device_printf(dev,
 		    "%s: i40e_aq_get_phy_capabilities() status %s, aq error %s\n",
 		    __func__, i40e_stat_str(hw, status),
 		    i40e_aq_str(hw, hw->aq.asq_last_status));
 		sbuf_delete(buf);
 		return (EIO);
 	}
 
 	sbuf_printf(buf, "\n"
 	    "PHY Type : %08x",
 	    abilities.phy_type);
 
 	if (abilities.phy_type != 0) {
 		sbuf_printf(buf, "<");
 		for (int i = 0; i < 32; i++)
 			if ((1 << i) & abilities.phy_type)
 				sbuf_printf(buf, "%s,", ixl_phy_type_string(i, false));
 		sbuf_printf(buf, ">\n");
 	}
 
 	sbuf_printf(buf, "PHY Ext  : %02x",
 	    abilities.phy_type_ext);
 
 	if (abilities.phy_type_ext != 0) {
 		sbuf_printf(buf, "<");
 		for (int i = 0; i < 4; i++)
 			if ((1 << i) & abilities.phy_type_ext)
 				sbuf_printf(buf, "%s,", ixl_phy_type_string(i, true));
 		sbuf_printf(buf, ">");
 	}
 	sbuf_printf(buf, "\n");
 
 	sbuf_printf(buf,
 	    "Speed    : %02x\n"
 	    "Abilities: %02x\n"
 	    "EEE cap  : %04x\n"
 	    "EEER reg : %08x\n"
 	    "D3 Lpan  : %02x\n"
 	    "ID       : %02x %02x %02x %02x\n"
 	    "ModType  : %02x %02x %02x\n"
 	    "ModType E: %01x\n"
 	    "FEC Cfg  : %02x\n"
 	    "Ext CC   : %02x",
 	    abilities.link_speed, 
 	    abilities.abilities, abilities.eee_capability,
 	    abilities.eeer_val, abilities.d3_lpan,
 	    abilities.phy_id[0], abilities.phy_id[1],
 	    abilities.phy_id[2], abilities.phy_id[3],
 	    abilities.module_type[0], abilities.module_type[1],
 	    abilities.module_type[2], abilities.phy_type_ext >> 5,
 	    abilities.phy_type_ext & 0x1F,
 	    abilities.ext_comp_code);
 
 	error = sbuf_finish(buf);
 	if (error)
 		device_printf(dev, "Error finishing sbuf: %d\n", error);
 
 	sbuf_delete(buf);
 	return (error);
 }
 
 static int
 ixl_sysctl_sw_filter_list(SYSCTL_HANDLER_ARGS)
 {
 	struct ixl_pf *pf = (struct ixl_pf *)arg1;
 	struct ixl_vsi *vsi = &pf->vsi;
 	struct ixl_mac_filter *f;
 	char *buf, *buf_i;
 
 	int error = 0;
 	int ftl_len = 0;
 	int ftl_counter = 0;
 	int buf_len = 0;
 	int entry_len = 42;
 
 	SLIST_FOREACH(f, &vsi->ftl, next) {
 		ftl_len++;
 	}
 
 	if (ftl_len < 1) {
 		sysctl_handle_string(oidp, "(none)", 6, req);
 		return (0);
 	}
 
 	buf_len = sizeof(char) * (entry_len + 1) * ftl_len + 2;
 	buf = buf_i = malloc(buf_len, M_DEVBUF, M_NOWAIT);
 
 	sprintf(buf_i++, "\n");
 	SLIST_FOREACH(f, &vsi->ftl, next) {
 		sprintf(buf_i,
 		    MAC_FORMAT ", vlan %4d, flags %#06x",
 		    MAC_FORMAT_ARGS(f->macaddr), f->vlan, f->flags);
 		buf_i += entry_len;
 		/* don't print '\n' for last entry */
 		if (++ftl_counter != ftl_len) {
 			sprintf(buf_i, "\n");
 			buf_i++;
 		}
 	}
 
 	error = sysctl_handle_string(oidp, buf, strlen(buf), req);
 	if (error)
 		printf("sysctl error: %d\n", error);
 	free(buf, M_DEVBUF);
 	return error;
 }
 
 #define IXL_SW_RES_SIZE 0x14
 int
 ixl_res_alloc_cmp(const void *a, const void *b)
 {
 	const struct i40e_aqc_switch_resource_alloc_element_resp *one, *two;
 	one = (const struct i40e_aqc_switch_resource_alloc_element_resp *)a;
 	two = (const struct i40e_aqc_switch_resource_alloc_element_resp *)b;
 
 	return ((int)one->resource_type - (int)two->resource_type);
 }
 
 /*
  * Longest string length: 25 
  */
 char *
 ixl_switch_res_type_string(u8 type)
 {
 	static char * ixl_switch_res_type_strings[0x14] = {
 		"VEB",
 		"VSI",
 		"Perfect Match MAC address",
 		"S-tag",
 		"(Reserved)",
 		"Multicast hash entry",
 		"Unicast hash entry",
 		"VLAN",
 		"VSI List entry",
 		"(Reserved)",
 		"VLAN Statistic Pool",
 		"Mirror Rule",
 		"Queue Set",
 		"Inner VLAN Forward filter",
 		"(Reserved)",
 		"Inner MAC",
 		"IP",
 		"GRE/VN1 Key",
 		"VN2 Key",
 		"Tunneling Port"
 	};
 
 	if (type < 0x14)
 		return ixl_switch_res_type_strings[type];
 	else
 		return "(Reserved)";
 }
 
 static int
 ixl_sysctl_hw_res_alloc(SYSCTL_HANDLER_ARGS)
 {
 	struct ixl_pf *pf = (struct ixl_pf *)arg1;
 	struct i40e_hw *hw = &pf->hw;
 	device_t dev = pf->dev;
 	struct sbuf *buf;
 	enum i40e_status_code status;
 	int error = 0;
 
 	u8 num_entries;
 	struct i40e_aqc_switch_resource_alloc_element_resp resp[IXL_SW_RES_SIZE];
 
 	buf = sbuf_new_for_sysctl(NULL, NULL, 128, req);
 	if (!buf) {
 		device_printf(dev, "Could not allocate sbuf for output.\n");
 		return (ENOMEM);
 	}
 
 	bzero(resp, sizeof(resp));
 	status = i40e_aq_get_switch_resource_alloc(hw, &num_entries,
 				resp,
 				IXL_SW_RES_SIZE,
 				NULL);
 	if (status) {
 		device_printf(dev,
 		    "%s: get_switch_resource_alloc() error %s, aq error %s\n",
 		    __func__, i40e_stat_str(hw, status),
 		    i40e_aq_str(hw, hw->aq.asq_last_status));
 		sbuf_delete(buf);
 		return (error);
 	}
 
 	/* Sort entries by type for display */
 	qsort(resp, num_entries,
 	    sizeof(struct i40e_aqc_switch_resource_alloc_element_resp),
 	    &ixl_res_alloc_cmp);
 
 	sbuf_cat(buf, "\n");
 	sbuf_printf(buf, "# of entries: %d\n", num_entries);
 	sbuf_printf(buf,
 	    "                     Type | Guaranteed | Total | Used   | Un-allocated\n"
 	    "                          | (this)     | (all) | (this) | (all)       \n");
 	for (int i = 0; i < num_entries; i++) {
 		sbuf_printf(buf,
 		    "%25s | %10d   %5d   %6d   %12d",
 		    ixl_switch_res_type_string(resp[i].resource_type),
 		    resp[i].guaranteed,
 		    resp[i].total,
 		    resp[i].used,
 		    resp[i].total_unalloced);
 		if (i < num_entries - 1)
 			sbuf_cat(buf, "\n");
 	}
 
 	error = sbuf_finish(buf);
 	if (error)
 		device_printf(dev, "Error finishing sbuf: %d\n", error);
 
 	sbuf_delete(buf);
 	return (error);
 }
 
 /*
 ** Caller must init and delete sbuf; this function will clear and
 ** finish it for caller.
 **
 ** XXX: Cannot use the SEID for this, since there is no longer a 
 ** fixed mapping between SEID and element type.
 */
 char *
 ixl_switch_element_string(struct sbuf *s,
     struct i40e_aqc_switch_config_element_resp *element)
 {
 	sbuf_clear(s);
 
 	switch (element->element_type) {
 	case I40E_AQ_SW_ELEM_TYPE_MAC:
 		sbuf_printf(s, "MAC %3d", element->element_info);
 		break;
 	case I40E_AQ_SW_ELEM_TYPE_PF:
 		sbuf_printf(s, "PF  %3d", element->element_info);
 		break;
 	case I40E_AQ_SW_ELEM_TYPE_VF:
 		sbuf_printf(s, "VF  %3d", element->element_info);
 		break;
 	case I40E_AQ_SW_ELEM_TYPE_EMP:
 		sbuf_cat(s, "EMP");
 		break;
 	case I40E_AQ_SW_ELEM_TYPE_BMC:
 		sbuf_cat(s, "BMC");
 		break;
 	case I40E_AQ_SW_ELEM_TYPE_PV:
 		sbuf_cat(s, "PV");
 		break;
 	case I40E_AQ_SW_ELEM_TYPE_VEB:
 		sbuf_cat(s, "VEB");
 		break;
 	case I40E_AQ_SW_ELEM_TYPE_PA:
 		sbuf_cat(s, "PA");
 		break;
 	case I40E_AQ_SW_ELEM_TYPE_VSI:
 		sbuf_printf(s, "VSI %3d", element->element_info);
 		break;
 	default:
 		sbuf_cat(s, "?");
 		break;
 	}
 
 	sbuf_finish(s);
 	return sbuf_data(s);
 }
 
 static int
 ixl_sysctl_switch_config(SYSCTL_HANDLER_ARGS)
 {
 	struct ixl_pf *pf = (struct ixl_pf *)arg1;
 	struct i40e_hw *hw = &pf->hw;
 	device_t dev = pf->dev;
 	struct sbuf *buf;
 	struct sbuf *nmbuf;
 	enum i40e_status_code status;
 	int error = 0;
 	u16 next = 0;
 	u8 aq_buf[I40E_AQ_LARGE_BUF];
 
 	struct i40e_aqc_get_switch_config_resp *sw_config;
 	sw_config = (struct i40e_aqc_get_switch_config_resp *)aq_buf;
 
 	buf = sbuf_new_for_sysctl(NULL, NULL, 128, req);
 	if (!buf) {
 		device_printf(dev, "Could not allocate sbuf for sysctl output.\n");
 		return (ENOMEM);
 	}
 
 	status = i40e_aq_get_switch_config(hw, sw_config,
 	    sizeof(aq_buf), &next, NULL);
 	if (status) {
 		device_printf(dev,
 		    "%s: aq_get_switch_config() error %s, aq error %s\n",
 		    __func__, i40e_stat_str(hw, status),
 		    i40e_aq_str(hw, hw->aq.asq_last_status));
 		sbuf_delete(buf);
 		return error;
 	}
 	if (next)
 		device_printf(dev, "%s: TODO: get more config with SEID %d\n",
 		    __func__, next);
 
 	nmbuf = sbuf_new_auto();
 	if (!nmbuf) {
 		device_printf(dev, "Could not allocate sbuf for name output.\n");
 		sbuf_delete(buf);
 		return (ENOMEM);
 	}
 
 	sbuf_cat(buf, "\n");
 	/* Assuming <= 255 elements in switch */
 	sbuf_printf(buf, "# of reported elements: %d\n", sw_config->header.num_reported);
 	sbuf_printf(buf, "total # of elements: %d\n", sw_config->header.num_total);
 	/* Exclude:
 	** Revision -- all elements are revision 1 for now
 	*/
 	sbuf_printf(buf,
 	    "SEID (  Name  ) |  Uplink  | Downlink | Conn Type\n"
 	    "                |          |          | (uplink)\n");
 	for (int i = 0; i < sw_config->header.num_reported; i++) {
 		// "%4d (%8s) | %8s   %8s   %#8x",
 		sbuf_printf(buf, "%4d", sw_config->element[i].seid);
 		sbuf_cat(buf, " ");
 		sbuf_printf(buf, "(%8s)", ixl_switch_element_string(nmbuf,
 		    &sw_config->element[i]));
 		sbuf_cat(buf, " | ");
 		sbuf_printf(buf, "%8d", sw_config->element[i].uplink_seid);
 		sbuf_cat(buf, "   ");
 		sbuf_printf(buf, "%8d", sw_config->element[i].downlink_seid);
 		sbuf_cat(buf, "   ");
 		sbuf_printf(buf, "%#8x", sw_config->element[i].connection_type);
 		if (i < sw_config->header.num_reported - 1)
 			sbuf_cat(buf, "\n");
 	}
 	sbuf_delete(nmbuf);
 
 	error = sbuf_finish(buf);
 	if (error)
 		device_printf(dev, "Error finishing sbuf: %d\n", error);
 
 	sbuf_delete(buf);
 
 	return (error);
 }
 
 static int
 ixl_sysctl_hkey(SYSCTL_HANDLER_ARGS)
 {
 	struct ixl_pf *pf = (struct ixl_pf *)arg1;
 	struct i40e_hw *hw = &pf->hw;
 	device_t dev = pf->dev;
 	struct sbuf *buf;
 	int error = 0;
 	enum i40e_status_code status;
 	u32 reg;
 
 	struct i40e_aqc_get_set_rss_key_data key_data;
 
 	buf = sbuf_new_for_sysctl(NULL, NULL, 128, req);
 	if (!buf) {
 		device_printf(dev, "Could not allocate sbuf for output.\n");
 		return (ENOMEM);
 	}
 
 	sbuf_cat(buf, "\n");
 	if (hw->mac.type == I40E_MAC_X722) {
 		bzero(key_data.standard_rss_key, sizeof(key_data.standard_rss_key));
 		status = i40e_aq_get_rss_key(hw, pf->vsi.vsi_num, &key_data);
 		if (status)
 			device_printf(dev, "i40e_aq_get_rss_key status %s, error %s\n",
 			    i40e_stat_str(hw, status), i40e_aq_str(hw, hw->aq.asq_last_status));
 		sbuf_printf(buf, "%40D", (u_char *)key_data.standard_rss_key, "");
 	} else {
 		for (int i = 0; i < IXL_RSS_KEY_SIZE_REG; i++) {
 			reg = i40e_read_rx_ctl(hw, I40E_PFQF_HKEY(i));
 			sbuf_printf(buf, "%4D", (u_char *)&reg, "");
 		}
 	}
 
 	error = sbuf_finish(buf);
 	if (error)
 		device_printf(dev, "Error finishing sbuf: %d\n", error);
 	sbuf_delete(buf);
 
 	return (error);
 }
 
 static int
 ixl_sysctl_hlut(SYSCTL_HANDLER_ARGS)
 {
 	struct ixl_pf *pf = (struct ixl_pf *)arg1;
 	struct i40e_hw *hw = &pf->hw;
 	device_t dev = pf->dev;
 	struct sbuf *buf;
 	int error = 0;
 	enum i40e_status_code status;
 	u8 hlut[512];
 	u32 reg;
 
 	buf = sbuf_new_for_sysctl(NULL, NULL, 128, req);
 	if (!buf) {
 		device_printf(dev, "Could not allocate sbuf for output.\n");
 		return (ENOMEM);
 	}
 
 	sbuf_cat(buf, "\n");
 	if (hw->mac.type == I40E_MAC_X722) {
 		bzero(hlut, sizeof(hlut));
 		status = i40e_aq_get_rss_lut(hw, pf->vsi.vsi_num, TRUE, hlut, sizeof(hlut));
 		if (status)
 			device_printf(dev, "i40e_aq_get_rss_lut status %s, error %s\n",
 			    i40e_stat_str(hw, status), i40e_aq_str(hw, hw->aq.asq_last_status));
 		sbuf_printf(buf, "%512D", (u_char *)hlut, "");
 	} else {
 		for (int i = 0; i < hw->func_caps.rss_table_size >> 2; i++) {
 			reg = rd32(hw, I40E_PFQF_HLUT(i));
 			sbuf_printf(buf, "%4D", (u_char *)&reg, "");
 		}
 	}
 
 	error = sbuf_finish(buf);
 	if (error)
 		device_printf(dev, "Error finishing sbuf: %d\n", error);
 	sbuf_delete(buf);
 
 	return (error);
 }
 
 static int
 ixl_sysctl_hena(SYSCTL_HANDLER_ARGS)
 {
 	struct ixl_pf *pf = (struct ixl_pf *)arg1;
 	struct i40e_hw *hw = &pf->hw;
 	u64 hena;
 
 	hena = (u64)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0)) |
 	    ((u64)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1)) << 32);
 
 	return sysctl_handle_long(oidp, NULL, hena, req);
 }
 
 /*
  * Sysctl to disable firmware's link management
  *
  * 1 - Disable link management on this port
  * 0 - Re-enable link management
  *
  * On normal NVMs, firmware manages link by default.
  */
 static int
 ixl_sysctl_fw_link_management(SYSCTL_HANDLER_ARGS)
 {
 	struct ixl_pf *pf = (struct ixl_pf *)arg1;
 	struct i40e_hw *hw = &pf->hw;
 	device_t dev = pf->dev;
 	int requested_mode = -1;
 	enum i40e_status_code status = 0;
 	int error = 0;
 
 	/* Read in new mode */
 	error = sysctl_handle_int(oidp, &requested_mode, 0, req);
 	if ((error) || (req->newptr == NULL))
 		return (error);
 	/* Check for sane value */
 	if (requested_mode < 0 || requested_mode > 1) {
 		device_printf(dev, "Valid modes are 0 or 1\n");
 		return (EINVAL);
 	}
 
 	/* Set new mode */
 	status = i40e_aq_set_phy_debug(hw, !!(requested_mode) << 4, NULL);
 	if (status) {
 		device_printf(dev,
 		    "%s: Error setting new phy debug mode %s,"
 		    " aq error: %s\n", __func__, i40e_stat_str(hw, status),
 		    i40e_aq_str(hw, hw->aq.asq_last_status));
 		return (EIO);
 	}
 
 	return (0);
 }
 
 /*
  * Sysctl to read a byte from I2C bus.
  *
  * Input: 32-bit value:
  * 	bits 0-7:   device address (0xA0 or 0xA2)
  * 	bits 8-15:  offset (0-255)
  *	bits 16-31: unused
  * Output: 8-bit value read
  */
 static int
 ixl_sysctl_read_i2c_byte(SYSCTL_HANDLER_ARGS)
 {
 	struct ixl_pf *pf = (struct ixl_pf *)arg1;
 	device_t dev = pf->dev;
 	int input = -1, error = 0;
 
 	device_printf(dev, "%s: start\n", __func__);
 
 	u8 dev_addr, offset, output;
 
 	/* Read in I2C read parameters */
 	error = sysctl_handle_int(oidp, &input, 0, req);
 	if ((error) || (req->newptr == NULL))
 		return (error);
 	/* Validate device address */
 	dev_addr = input & 0xFF;
 	if (dev_addr != 0xA0 && dev_addr != 0xA2) {
 		return (EINVAL);
 	}
 	offset = (input >> 8) & 0xFF;
 
 	error = ixl_read_i2c_byte(pf, offset, dev_addr, &output);
 	if (error)
 		return (error);
 
 	device_printf(dev, "%02X\n", output);
 	return (0);
 }
 
 /*
  * Sysctl to write a byte to the I2C bus.
  *
  * Input: 32-bit value:
  * 	bits 0-7:   device address (0xA0 or 0xA2)
  * 	bits 8-15:  offset (0-255)
  *	bits 16-23: value to write
  *	bits 24-31: unused
  * Output: 8-bit value written
  */
 static int
 ixl_sysctl_write_i2c_byte(SYSCTL_HANDLER_ARGS)
 {
 	struct ixl_pf *pf = (struct ixl_pf *)arg1;
 	device_t dev = pf->dev;
 	int input = -1, error = 0;
 
 	u8 dev_addr, offset, value;
 
 	/* Read in I2C write parameters */
 	error = sysctl_handle_int(oidp, &input, 0, req);
 	if ((error) || (req->newptr == NULL))
 		return (error);
 	/* Validate device address */
 	dev_addr = input & 0xFF;
 	if (dev_addr != 0xA0 && dev_addr != 0xA2) {
 		return (EINVAL);
 	}
 	offset = (input >> 8) & 0xFF;
 	value = (input >> 16) & 0xFF;
 
 	error = ixl_write_i2c_byte(pf, offset, dev_addr, value);
 	if (error)
 		return (error);
 
 	device_printf(dev, "%02X written\n", value);
 	return (0);
 }
 
 static int
 ixl_get_fec_config(struct ixl_pf *pf, struct i40e_aq_get_phy_abilities_resp *abilities,
     u8 bit_pos, int *is_set)
 {
 	device_t dev = pf->dev;
 	struct i40e_hw *hw = &pf->hw;
 	enum i40e_status_code status;
 
 	status = i40e_aq_get_phy_capabilities(hw,
 	    FALSE, FALSE, abilities, NULL);
 	if (status) {
 		device_printf(dev,
 		    "%s: i40e_aq_get_phy_capabilities() status %s, aq error %s\n",
 		    __func__, i40e_stat_str(hw, status),
 		    i40e_aq_str(hw, hw->aq.asq_last_status));
 		return (EIO);
 	}
 
 	*is_set = !!(abilities->phy_type_ext & bit_pos);
 	return (0);
 }
 
 static int
 ixl_set_fec_config(struct ixl_pf *pf, struct i40e_aq_get_phy_abilities_resp *abilities,
     u8 bit_pos, int set)
 {
 	device_t dev = pf->dev;
 	struct i40e_hw *hw = &pf->hw;
 	struct i40e_aq_set_phy_config config;
 	enum i40e_status_code status;
 
 	/* Set new PHY config */
 	memset(&config, 0, sizeof(config));
 	config.fec_config = abilities->phy_type_ext & ~(bit_pos);
 	if (set)
 		config.fec_config |= bit_pos;
 	if (config.fec_config != abilities->phy_type_ext) {
 		config.abilities |= I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
 		config.phy_type = abilities->phy_type;
 		config.phy_type_ext = abilities->phy_type_ext;
 		config.link_speed = abilities->link_speed;
 		config.eee_capability = abilities->eee_capability;
 		config.eeer = abilities->eeer_val;
 		config.low_power_ctrl = abilities->d3_lpan;
 		status = i40e_aq_set_phy_config(hw, &config, NULL);
 
 		if (status) {
 			device_printf(dev,
 			    "%s: i40e_aq_set_phy_config() status %s, aq error %s\n",
 			    __func__, i40e_stat_str(hw, status),
 			    i40e_aq_str(hw, hw->aq.asq_last_status));
 			return (EIO);
 		}
 	}
 
 	return (0);
 }
 
 static int
 ixl_sysctl_fec_fc_ability(SYSCTL_HANDLER_ARGS)
 {
 	struct ixl_pf *pf = (struct ixl_pf *)arg1;
 	int mode, error = 0;
 
 	struct i40e_aq_get_phy_abilities_resp abilities;
 	error = ixl_get_fec_config(pf, &abilities, I40E_AQ_SET_FEC_ABILITY_KR, &mode);
 	if (error)
 		return (error);
 	/* Read in new mode */
 	error = sysctl_handle_int(oidp, &mode, 0, req);
 	if ((error) || (req->newptr == NULL))
 		return (error);
 
 	return ixl_set_fec_config(pf, &abilities, I40E_AQ_SET_FEC_ABILITY_KR, !!(mode));
 }
 
 static int
 ixl_sysctl_fec_rs_ability(SYSCTL_HANDLER_ARGS)
 {
 	struct ixl_pf *pf = (struct ixl_pf *)arg1;
 	int mode, error = 0;
 
 	struct i40e_aq_get_phy_abilities_resp abilities;
 	error = ixl_get_fec_config(pf, &abilities, I40E_AQ_SET_FEC_ABILITY_RS, &mode);
 	if (error)
 		return (error);
 	/* Read in new mode */
 	error = sysctl_handle_int(oidp, &mode, 0, req);
 	if ((error) || (req->newptr == NULL))
 		return (error);
 
 	return ixl_set_fec_config(pf, &abilities, I40E_AQ_SET_FEC_ABILITY_RS, !!(mode));
 }
 
 static int
 ixl_sysctl_fec_fc_request(SYSCTL_HANDLER_ARGS)
 {
 	struct ixl_pf *pf = (struct ixl_pf *)arg1;
 	int mode, error = 0;
 
 	struct i40e_aq_get_phy_abilities_resp abilities;
 	error = ixl_get_fec_config(pf, &abilities, I40E_AQ_SET_FEC_REQUEST_KR, &mode);
 	if (error)
 		return (error);
 	/* Read in new mode */
 	error = sysctl_handle_int(oidp, &mode, 0, req);
 	if ((error) || (req->newptr == NULL))
 		return (error);
 
 	return ixl_set_fec_config(pf, &abilities, I40E_AQ_SET_FEC_REQUEST_KR, !!(mode));
 }
 
 static int
 ixl_sysctl_fec_rs_request(SYSCTL_HANDLER_ARGS)
 {
 	struct ixl_pf *pf = (struct ixl_pf *)arg1;
 	int mode, error = 0;
 
 	struct i40e_aq_get_phy_abilities_resp abilities;
 	error = ixl_get_fec_config(pf, &abilities, I40E_AQ_SET_FEC_REQUEST_RS, &mode);
 	if (error)
 		return (error);
 	/* Read in new mode */
 	error = sysctl_handle_int(oidp, &mode, 0, req);
 	if ((error) || (req->newptr == NULL))
 		return (error);
 
 	return ixl_set_fec_config(pf, &abilities, I40E_AQ_SET_FEC_REQUEST_RS, !!(mode));
 }
 
 static int
 ixl_sysctl_fec_auto_enable(SYSCTL_HANDLER_ARGS)
 {
 	struct ixl_pf *pf = (struct ixl_pf *)arg1;
 	int mode, error = 0;
 
 	struct i40e_aq_get_phy_abilities_resp abilities;
 	error = ixl_get_fec_config(pf, &abilities, I40E_AQ_SET_FEC_AUTO, &mode);
 	if (error)
 		return (error);
 	/* Read in new mode */
 	error = sysctl_handle_int(oidp, &mode, 0, req);
 	if ((error) || (req->newptr == NULL))
 		return (error);
 
 	return ixl_set_fec_config(pf, &abilities, I40E_AQ_SET_FEC_AUTO, !!(mode));
 }
 
Index: head/sys/dev/ixl/ixl_txrx.c
===================================================================
--- head/sys/dev/ixl/ixl_txrx.c	(revision 320976)
+++ head/sys/dev/ixl/ixl_txrx.c	(revision 320977)
@@ -1,1854 +1,1852 @@
 /******************************************************************************
 
   Copyright (c) 2013-2015, Intel Corporation 
   All rights reserved.
   
   Redistribution and use in source and binary forms, with or without 
   modification, are permitted provided that the following conditions are met:
   
    1. Redistributions of source code must retain the above copyright notice, 
       this list of conditions and the following disclaimer.
   
    2. Redistributions in binary form must reproduce the above copyright 
       notice, this list of conditions and the following disclaimer in the 
       documentation and/or other materials provided with the distribution.
   
    3. Neither the name of the Intel Corporation nor the names of its 
       contributors may be used to endorse or promote products derived from 
       this software without specific prior written permission.
   
   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 
   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 
   ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 
   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 
   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 
   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 
   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 
   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 
   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
   POSSIBILITY OF SUCH DAMAGE.
 
 ******************************************************************************/
 /*$FreeBSD$*/
 
 /*
 **	IXL driver TX/RX Routines:
 **	    This was seperated to allow usage by
 ** 	    both the PF and VF drivers.
 */
 
 #ifndef IXL_STANDALONE_BUILD
 #include "opt_inet.h"
 #include "opt_inet6.h"
 #include "opt_rss.h"
 #endif
 
 #include "ixl.h"
 
 #ifdef RSS
 #include <net/rss_config.h>
 #endif
 
 /* Local Prototypes */
 static void	ixl_rx_checksum(struct mbuf *, u32, u32, u8);
 static void	ixl_refresh_mbufs(struct ixl_queue *, int);
 static int      ixl_xmit(struct ixl_queue *, struct mbuf **);
 static int	ixl_tx_setup_offload(struct ixl_queue *,
 		    struct mbuf *, u32 *, u32 *);
 static bool	ixl_tso_setup(struct ixl_queue *, struct mbuf *);
 
 static inline void ixl_rx_discard(struct rx_ring *, int);
 static inline void ixl_rx_input(struct rx_ring *, struct ifnet *,
 		    struct mbuf *, u8);
 
 static inline bool ixl_tso_detect_sparse(struct mbuf *mp);
-static int	ixl_tx_setup_offload(struct ixl_queue *que,
-    struct mbuf *mp, u32 *cmd, u32 *off);
 static inline u32 ixl_get_tx_head(struct ixl_queue *que);
 
 #ifdef DEV_NETMAP
 #include <dev/netmap/if_ixl_netmap.h>
 int ixl_rx_miss, ixl_rx_miss_bufs, ixl_crcstrip = 1;
 #endif /* DEV_NETMAP */
 
 /*
  * @key key is saved into this parameter
  */
 void
 ixl_get_default_rss_key(u32 *key)
 {
 	MPASS(key != NULL);
 
 	u32 rss_seed[IXL_RSS_KEY_SIZE_REG] = {0x41b01687,
 	    0x183cfd8c, 0xce880440, 0x580cbc3c,
 	    0x35897377, 0x328b25e1, 0x4fa98922,
 	    0xb7d90c14, 0xd5bad70d, 0xcd15a2c1,
 	    0x0, 0x0, 0x0};
 
 	bcopy(rss_seed, key, IXL_RSS_KEY_SIZE);
 }
 
 /*
 ** Multiqueue Transmit driver
 */
 int
 ixl_mq_start(struct ifnet *ifp, struct mbuf *m)
 {
 	struct ixl_vsi		*vsi = ifp->if_softc;
 	struct ixl_queue	*que;
 	struct tx_ring		*txr;
 	int 			err, i;
 #ifdef RSS
 	u32			bucket_id;
 #endif
 
 	/*
 	** Which queue to use:
 	**
 	** When doing RSS, map it to the same outbound
 	** queue as the incoming flow would be mapped to.
 	** If everything is setup correctly, it should be
 	** the same bucket that the current CPU we're on is.
 	*/
 	if (M_HASHTYPE_GET(m) != M_HASHTYPE_NONE) {
 #ifdef  RSS
 		if (rss_hash2bucket(m->m_pkthdr.flowid,
 		    M_HASHTYPE_GET(m), &bucket_id) == 0) {
 			i = bucket_id % vsi->num_queues;
                 } else
 #endif
                         i = m->m_pkthdr.flowid % vsi->num_queues;
         } else
 		i = curcpu % vsi->num_queues;
 
 	que = &vsi->queues[i];
 	txr = &que->txr;
 
 	err = drbr_enqueue(ifp, txr->br, m);
 	if (err)
 		return (err);
 	if (IXL_TX_TRYLOCK(txr)) {
 		ixl_mq_start_locked(ifp, txr);
 		IXL_TX_UNLOCK(txr);
 	} else
 		taskqueue_enqueue(que->tq, &que->tx_task);
 
 	return (0);
 }
 
 int
 ixl_mq_start_locked(struct ifnet *ifp, struct tx_ring *txr)
 {
 	struct ixl_queue	*que = txr->que;
 	struct ixl_vsi		*vsi = que->vsi;
         struct mbuf		*next;
         int			err = 0;
 
 
 	if (((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) ||
 	    vsi->link_active == 0)
 		return (ENETDOWN);
 
 	/* Process the transmit queue */
 	while ((next = drbr_peek(ifp, txr->br)) != NULL) {
 		if ((err = ixl_xmit(que, &next)) != 0) {
 			if (next == NULL)
 				drbr_advance(ifp, txr->br);
 			else
 				drbr_putback(ifp, txr->br, next);
 			break;
 		}
 		drbr_advance(ifp, txr->br);
 		/* Send a copy of the frame to the BPF listener */
 		ETHER_BPF_MTAP(ifp, next);
 		if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0)
 			break;
 	}
 
 	if (txr->avail < IXL_TX_CLEANUP_THRESHOLD)
 		ixl_txeof(que);
 
 	return (err);
 }
 
 /*
  * Called from a taskqueue to drain queued transmit packets.
  */
 void
 ixl_deferred_mq_start(void *arg, int pending)
 {
 	struct ixl_queue	*que = arg;
         struct tx_ring		*txr = &que->txr;
 	struct ixl_vsi		*vsi = que->vsi;
         struct ifnet		*ifp = vsi->ifp;
         
 	IXL_TX_LOCK(txr);
 	if (!drbr_empty(ifp, txr->br))
 		ixl_mq_start_locked(ifp, txr);
 	IXL_TX_UNLOCK(txr);
 }
 
 /*
 ** Flush all queue ring buffers
 */
 void
 ixl_qflush(struct ifnet *ifp)
 {
 	struct ixl_vsi	*vsi = ifp->if_softc;
 
         for (int i = 0; i < vsi->num_queues; i++) {
 		struct ixl_queue *que = &vsi->queues[i];
 		struct tx_ring	*txr = &que->txr;
 		struct mbuf	*m;
 		IXL_TX_LOCK(txr);
 		while ((m = buf_ring_dequeue_sc(txr->br)) != NULL)
 			m_freem(m);
 		IXL_TX_UNLOCK(txr);
 	}
 	if_qflush(ifp);
 }
 
 /*
 ** Find mbuf chains passed to the driver 
 ** that are 'sparse', using more than 8
 ** mbufs to deliver an mss-size chunk of data
 */
 static inline bool
 ixl_tso_detect_sparse(struct mbuf *mp)
 {
 	struct mbuf	*m;
 	int		num, mss;
 
 	num = 0;
 	mss = mp->m_pkthdr.tso_segsz;
 
 	/* Exclude first mbuf; assume it contains all headers */
 	for (m = mp->m_next; m != NULL; m = m->m_next) {
 		if (m == NULL)
 			break;
 		num++;
 		mss -= m->m_len % mp->m_pkthdr.tso_segsz;
 
 		if (mss < 1) {
 			if (num > IXL_SPARSE_CHAIN)
 				return (true);
 			num = (mss == 0) ? 0 : 1;
 			mss += mp->m_pkthdr.tso_segsz;
 		}
 	}
 
 	return (false);
 }
 
 
 /*********************************************************************
  *
  *  This routine maps the mbufs to tx descriptors, allowing the
  *  TX engine to transmit the packets. 
  *  	- return 0 on success, positive on failure
  *
  **********************************************************************/
 #define IXL_TXD_CMD (I40E_TX_DESC_CMD_EOP | I40E_TX_DESC_CMD_RS)
 
 static int
 ixl_xmit(struct ixl_queue *que, struct mbuf **m_headp)
 {
 	struct ixl_vsi		*vsi = que->vsi;
 	struct i40e_hw		*hw = vsi->hw;
 	struct tx_ring		*txr = &que->txr;
 	struct ixl_tx_buf	*buf;
 	struct i40e_tx_desc	*txd = NULL;
 	struct mbuf		*m_head, *m;
 	int             	i, j, error, nsegs;
 	int			first, last = 0;
 	u16			vtag = 0;
 	u32			cmd, off;
 	bus_dmamap_t		map;
 	bus_dma_tag_t		tag;
 	bus_dma_segment_t	segs[IXL_MAX_TSO_SEGS];
 
 	cmd = off = 0;
 	m_head = *m_headp;
 
         /*
          * Important to capture the first descriptor
          * used because it will contain the index of
          * the one we tell the hardware to report back
          */
         first = txr->next_avail;
 	buf = &txr->buffers[first];
 	map = buf->map;
 	tag = txr->tx_tag;
 
 	if (m_head->m_pkthdr.csum_flags & CSUM_TSO) {
 		/* Use larger mapping for TSO */
 		tag = txr->tso_tag;
 		if (ixl_tso_detect_sparse(m_head)) {
 			m = m_defrag(m_head, M_NOWAIT);
 			if (m == NULL) {
 				m_freem(*m_headp);
 				*m_headp = NULL;
 				return (ENOBUFS);
 			}
 			*m_headp = m;
 		}
 	}
 
 	/*
 	 * Map the packet for DMA.
 	 */
 	error = bus_dmamap_load_mbuf_sg(tag, map,
 	    *m_headp, segs, &nsegs, BUS_DMA_NOWAIT);
 
 	if (error == EFBIG) {
 		struct mbuf *m;
 
 		m = m_defrag(*m_headp, M_NOWAIT);
 		if (m == NULL) {
 			que->mbuf_defrag_failed++;
 			m_freem(*m_headp);
 			*m_headp = NULL;
 			return (ENOBUFS);
 		}
 		*m_headp = m;
 
 		/* Try it again */
 		error = bus_dmamap_load_mbuf_sg(tag, map,
 		    *m_headp, segs, &nsegs, BUS_DMA_NOWAIT);
 
 		if (error != 0) {
 			que->tx_dmamap_failed++;
 			m_freem(*m_headp);
 			*m_headp = NULL;
 			return (error);
 		}
 	} else if (error != 0) {
 		que->tx_dmamap_failed++;
 		m_freem(*m_headp);
 		*m_headp = NULL;
 		return (error);
 	}
 
 	/* Make certain there are enough descriptors */
 	if (nsegs > txr->avail - 2) {
 		txr->no_desc++;
 		error = ENOBUFS;
 		goto xmit_fail;
 	}
 	m_head = *m_headp;
 
 	/* Set up the TSO/CSUM offload */
 	if (m_head->m_pkthdr.csum_flags & CSUM_OFFLOAD) {
 		error = ixl_tx_setup_offload(que, m_head, &cmd, &off);
 		if (error)
 			goto xmit_fail;
 	}
 
 	cmd |= I40E_TX_DESC_CMD_ICRC;
 	/* Grab the VLAN tag */
 	if (m_head->m_flags & M_VLANTAG) {
 		cmd |= I40E_TX_DESC_CMD_IL2TAG1;
 		vtag = htole16(m_head->m_pkthdr.ether_vtag);
 	}
 
 	i = txr->next_avail;
 	for (j = 0; j < nsegs; j++) {
 		bus_size_t seglen;
 
 		buf = &txr->buffers[i];
 		buf->tag = tag; /* Keep track of the type tag */
 		txd = &txr->base[i];
 		seglen = segs[j].ds_len;
 
 		txd->buffer_addr = htole64(segs[j].ds_addr);
 		txd->cmd_type_offset_bsz =
 		    htole64(I40E_TX_DESC_DTYPE_DATA
 		    | ((u64)cmd  << I40E_TXD_QW1_CMD_SHIFT)
 		    | ((u64)off << I40E_TXD_QW1_OFFSET_SHIFT)
 		    | ((u64)seglen  << I40E_TXD_QW1_TX_BUF_SZ_SHIFT)
 		    | ((u64)vtag  << I40E_TXD_QW1_L2TAG1_SHIFT));
 
 		last = i; /* descriptor that will get completion IRQ */
 
 		if (++i == que->num_desc)
 			i = 0;
 
 		buf->m_head = NULL;
 		buf->eop_index = -1;
 	}
 	/* Set the last descriptor for report */
 	txd->cmd_type_offset_bsz |=
 	    htole64(((u64)IXL_TXD_CMD << I40E_TXD_QW1_CMD_SHIFT));
 	txr->avail -= nsegs;
 	txr->next_avail = i;
 
 	buf->m_head = m_head;
 	/* Swap the dma map between the first and last descriptor */
 	txr->buffers[first].map = buf->map;
 	buf->map = map;
 	bus_dmamap_sync(tag, map, BUS_DMASYNC_PREWRITE);
 
         /* Set the index of the descriptor that will be marked done */
         buf = &txr->buffers[first];
 	buf->eop_index = last;
 
         bus_dmamap_sync(txr->dma.tag, txr->dma.map,
             BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
 	/*
 	 * Advance the Transmit Descriptor Tail (Tdt), this tells the
 	 * hardware that this frame is available to transmit.
 	 */
 	++txr->total_packets;
 	wr32(hw, txr->tail, i);
 
 	/* Mark outstanding work */
 	atomic_store_rel_32(&txr->watchdog_timer, IXL_WATCHDOG);
 	return (0);
 
 xmit_fail:
 	bus_dmamap_unload(tag, buf->map);
 	return (error);
 }
 
 
 /*********************************************************************
  *
  *  Allocate memory for tx_buffer structures. The tx_buffer stores all
  *  the information needed to transmit a packet on the wire. This is
  *  called only once at attach, setup is done every reset.
  *
  **********************************************************************/
 int
 ixl_allocate_tx_data(struct ixl_queue *que)
 {
 	struct tx_ring		*txr = &que->txr;
 	struct ixl_vsi		*vsi = que->vsi;
 	device_t		dev = vsi->dev;
 	struct ixl_tx_buf	*buf;
 	int			error = 0;
 
 	/*
 	 * Setup DMA descriptor areas.
 	 */
 	if ((error = bus_dma_tag_create(bus_get_dma_tag(dev),		/* parent */
 			       1, 0,			/* alignment, bounds */
 			       BUS_SPACE_MAXADDR,	/* lowaddr */
 			       BUS_SPACE_MAXADDR,	/* highaddr */
 			       NULL, NULL,		/* filter, filterarg */
 			       IXL_TSO_SIZE,		/* maxsize */
 			       IXL_MAX_TX_SEGS,		/* nsegments */
 			       PAGE_SIZE,		/* maxsegsize */
 			       0,			/* flags */
 			       NULL,			/* lockfunc */
 			       NULL,			/* lockfuncarg */
 			       &txr->tx_tag))) {
 		device_printf(dev,"Unable to allocate TX DMA tag\n");
 		goto fail;
 	}
 
 	/* Make a special tag for TSO */
 	if ((error = bus_dma_tag_create(bus_get_dma_tag(dev),		/* parent */
 			       1, 0,			/* alignment, bounds */
 			       BUS_SPACE_MAXADDR,	/* lowaddr */
 			       BUS_SPACE_MAXADDR,	/* highaddr */
 			       NULL, NULL,		/* filter, filterarg */
 			       IXL_TSO_SIZE,		/* maxsize */
 			       IXL_MAX_TSO_SEGS,	/* nsegments */
 			       PAGE_SIZE,		/* maxsegsize */
 			       0,			/* flags */
 			       NULL,			/* lockfunc */
 			       NULL,			/* lockfuncarg */
 			       &txr->tso_tag))) {
 		device_printf(dev,"Unable to allocate TX TSO DMA tag\n");
 		goto fail;
 	}
 
 	if (!(txr->buffers =
 	    (struct ixl_tx_buf *) malloc(sizeof(struct ixl_tx_buf) *
 	    que->num_desc, M_DEVBUF, M_NOWAIT | M_ZERO))) {
 		device_printf(dev, "Unable to allocate tx_buffer memory\n");
 		error = ENOMEM;
 		goto fail;
 	}
 
         /* Create the descriptor buffer default dma maps */
 	buf = txr->buffers;
 	for (int i = 0; i < que->num_desc; i++, buf++) {
 		buf->tag = txr->tx_tag;
 		error = bus_dmamap_create(buf->tag, 0, &buf->map);
 		if (error != 0) {
 			device_printf(dev, "Unable to create TX DMA map\n");
 			goto fail;
 		}
 	}
 fail:
 	return (error);
 }
 
 
 /*********************************************************************
  *
  *  (Re)Initialize a queue transmit ring.
  *	- called by init, it clears the descriptor ring,
  *	  and frees any stale mbufs 
  *
  **********************************************************************/
 void
 ixl_init_tx_ring(struct ixl_queue *que)
 {
 #ifdef DEV_NETMAP
 	struct netmap_adapter *na = NA(que->vsi->ifp);
 	struct netmap_slot *slot;
 #endif /* DEV_NETMAP */
 	struct tx_ring		*txr = &que->txr;
 	struct ixl_tx_buf	*buf;
 
 	/* Clear the old ring contents */
 	IXL_TX_LOCK(txr);
 
 #ifdef DEV_NETMAP
 	/*
 	 * (under lock): if in netmap mode, do some consistency
 	 * checks and set slot to entry 0 of the netmap ring.
 	 */
 	slot = netmap_reset(na, NR_TX, que->me, 0);
 #endif /* DEV_NETMAP */
 
 	bzero((void *)txr->base,
 	      (sizeof(struct i40e_tx_desc)) * que->num_desc);
 
 	/* Reset indices */
 	txr->next_avail = 0;
 	txr->next_to_clean = 0;
 
 	/* Reset watchdog status */
 	txr->watchdog_timer = 0;
 
 #ifdef IXL_FDIR
 	/* Initialize flow director */
 	txr->atr_rate = ixl_atr_rate;
 	txr->atr_count = 0;
 #endif
 	/* Free any existing tx mbufs. */
         buf = txr->buffers;
 	for (int i = 0; i < que->num_desc; i++, buf++) {
 		if (buf->m_head != NULL) {
 			bus_dmamap_sync(buf->tag, buf->map,
 			    BUS_DMASYNC_POSTWRITE);
 			bus_dmamap_unload(buf->tag, buf->map);
 			m_freem(buf->m_head);
 			buf->m_head = NULL;
 		}
 #ifdef DEV_NETMAP
 		/*
 		 * In netmap mode, set the map for the packet buffer.
 		 * NOTE: Some drivers (not this one) also need to set
 		 * the physical buffer address in the NIC ring.
 		 * netmap_idx_n2k() maps a nic index, i, into the corresponding
 		 * netmap slot index, si
 		 */
 		if (slot) {
 			int si = netmap_idx_n2k(&na->tx_rings[que->me], i);
 			netmap_load_map(na, buf->tag, buf->map, NMB(na, slot + si));
 		}
 #endif /* DEV_NETMAP */
 		/* Clear the EOP index */
 		buf->eop_index = -1;
         }
 
 	/* Set number of descriptors available */
 	txr->avail = que->num_desc;
 
 	bus_dmamap_sync(txr->dma.tag, txr->dma.map,
 	    BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
 	IXL_TX_UNLOCK(txr);
 }
 
 
 /*********************************************************************
  *
  *  Free transmit ring related data structures.
  *
  **********************************************************************/
 void
 ixl_free_que_tx(struct ixl_queue *que)
 {
 	struct tx_ring *txr = &que->txr;
 	struct ixl_tx_buf *buf;
 
 	INIT_DBG_IF(que->vsi->ifp, "queue %d: begin", que->me);
 
 	for (int i = 0; i < que->num_desc; i++) {
 		buf = &txr->buffers[i];
 		if (buf->m_head != NULL) {
 			bus_dmamap_sync(buf->tag, buf->map,
 			    BUS_DMASYNC_POSTWRITE);
 			bus_dmamap_unload(buf->tag,
 			    buf->map);
 			m_freem(buf->m_head);
 			buf->m_head = NULL;
 			if (buf->map != NULL) {
 				bus_dmamap_destroy(buf->tag,
 				    buf->map);
 				buf->map = NULL;
 			}
 		} else if (buf->map != NULL) {
 			bus_dmamap_unload(buf->tag,
 			    buf->map);
 			bus_dmamap_destroy(buf->tag,
 			    buf->map);
 			buf->map = NULL;
 		}
 	}
 	if (txr->br != NULL)
 		buf_ring_free(txr->br, M_DEVBUF);
 	if (txr->buffers != NULL) {
 		free(txr->buffers, M_DEVBUF);
 		txr->buffers = NULL;
 	}
 	if (txr->tx_tag != NULL) {
 		bus_dma_tag_destroy(txr->tx_tag);
 		txr->tx_tag = NULL;
 	}
 	if (txr->tso_tag != NULL) {
 		bus_dma_tag_destroy(txr->tso_tag);
 		txr->tso_tag = NULL;
 	}
 
 	INIT_DBG_IF(que->vsi->ifp, "queue %d: end", que->me);
 	return;
 }
 
 /*********************************************************************
  *
  *  Setup descriptor for hw offloads 
  *
  **********************************************************************/
 
 static int
 ixl_tx_setup_offload(struct ixl_queue *que,
     struct mbuf *mp, u32 *cmd, u32 *off)
 {
 	struct ether_vlan_header	*eh;
 #ifdef INET
 	struct ip			*ip = NULL;
 #endif
 	struct tcphdr			*th = NULL;
 #ifdef INET6
 	struct ip6_hdr			*ip6;
 #endif
 	int				elen, ip_hlen = 0, tcp_hlen;
 	u16				etype;
 	u8				ipproto = 0;
 	bool				tso = FALSE;
 
 	/* Set up the TSO context descriptor if required */
 	if (mp->m_pkthdr.csum_flags & CSUM_TSO) {
 		tso = ixl_tso_setup(que, mp);
 		if (tso)
 			++que->tso;
 		else
 			return (ENXIO);
 	}
 
 	/*
 	 * Determine where frame payload starts.
 	 * Jump over vlan headers if already present,
 	 * helpful for QinQ too.
 	 */
 	eh = mtod(mp, struct ether_vlan_header *);
 	if (eh->evl_encap_proto == htons(ETHERTYPE_VLAN)) {
 		etype = ntohs(eh->evl_proto);
 		elen = ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN;
 	} else {
 		etype = ntohs(eh->evl_encap_proto);
 		elen = ETHER_HDR_LEN;
 	}
 
 	switch (etype) {
 #ifdef INET
 		case ETHERTYPE_IP:
 			ip = (struct ip *)(mp->m_data + elen);
 			ip_hlen = ip->ip_hl << 2;
 			ipproto = ip->ip_p;
 			th = (struct tcphdr *)((caddr_t)ip + ip_hlen);
 			/* The IP checksum must be recalculated with TSO */
 			if (tso)
 				*cmd |= I40E_TX_DESC_CMD_IIPT_IPV4_CSUM;
 			else
 				*cmd |= I40E_TX_DESC_CMD_IIPT_IPV4;
 			break;
 #endif
 #ifdef INET6
 		case ETHERTYPE_IPV6:
 			ip6 = (struct ip6_hdr *)(mp->m_data + elen);
 			ip_hlen = sizeof(struct ip6_hdr);
 			ipproto = ip6->ip6_nxt;
 			th = (struct tcphdr *)((caddr_t)ip6 + ip_hlen);
 			*cmd |= I40E_TX_DESC_CMD_IIPT_IPV6;
 			break;
 #endif
 		default:
 			break;
 	}
 
 	*off |= (elen >> 1) << I40E_TX_DESC_LENGTH_MACLEN_SHIFT;
 	*off |= (ip_hlen >> 2) << I40E_TX_DESC_LENGTH_IPLEN_SHIFT;
 
 	switch (ipproto) {
 		case IPPROTO_TCP:
 			tcp_hlen = th->th_off << 2;
 			if (mp->m_pkthdr.csum_flags & (CSUM_TCP|CSUM_TCP_IPV6)) {
 				*cmd |= I40E_TX_DESC_CMD_L4T_EOFT_TCP;
 				*off |= (tcp_hlen >> 2) <<
 				    I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT;
 			}
 #ifdef IXL_FDIR
 			ixl_atr(que, th, etype);
 #endif
 			break;
 		case IPPROTO_UDP:
 			if (mp->m_pkthdr.csum_flags & (CSUM_UDP|CSUM_UDP_IPV6)) {
 				*cmd |= I40E_TX_DESC_CMD_L4T_EOFT_UDP;
 				*off |= (sizeof(struct udphdr) >> 2) <<
 				    I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT;
 			}
 			break;
 
 		case IPPROTO_SCTP:
 			if (mp->m_pkthdr.csum_flags & (CSUM_SCTP|CSUM_SCTP_IPV6)) {
 				*cmd |= I40E_TX_DESC_CMD_L4T_EOFT_SCTP;
 				*off |= (sizeof(struct sctphdr) >> 2) <<
 				    I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT;
 			}
 			/* Fall Thru */
 		default:
 			break;
 	}
 
         return (0);
 }
 
 
 /**********************************************************************
  *
  *  Setup context for hardware segmentation offload (TSO)
  *
  **********************************************************************/
 static bool
 ixl_tso_setup(struct ixl_queue *que, struct mbuf *mp)
 {
 	struct tx_ring			*txr = &que->txr;
 	struct i40e_tx_context_desc	*TXD;
 	struct ixl_tx_buf		*buf;
 	u32				cmd, mss, type, tsolen;
 	u16				etype;
 	int				idx, elen, ip_hlen, tcp_hlen;
 	struct ether_vlan_header	*eh;
 #ifdef INET
 	struct ip			*ip;
 #endif
 #ifdef INET6
 	struct ip6_hdr			*ip6;
 #endif
 #if defined(INET6) || defined(INET)
 	struct tcphdr			*th;
 #endif
 	u64				type_cmd_tso_mss;
 
 	/*
 	 * Determine where frame payload starts.
 	 * Jump over vlan headers if already present
 	 */
 	eh = mtod(mp, struct ether_vlan_header *);
 	if (eh->evl_encap_proto == htons(ETHERTYPE_VLAN)) {
 		elen = ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN;
 		etype = eh->evl_proto;
 	} else {
 		elen = ETHER_HDR_LEN;
 		etype = eh->evl_encap_proto;
 	}
 
         switch (ntohs(etype)) {
 #ifdef INET6
 	case ETHERTYPE_IPV6:
 		ip6 = (struct ip6_hdr *)(mp->m_data + elen);
 		if (ip6->ip6_nxt != IPPROTO_TCP)
 			return (ENXIO);
 		ip_hlen = sizeof(struct ip6_hdr);
 		th = (struct tcphdr *)((caddr_t)ip6 + ip_hlen);
 		th->th_sum = in6_cksum_pseudo(ip6, 0, IPPROTO_TCP, 0);
 		tcp_hlen = th->th_off << 2;
 		/*
 		 * The corresponding flag is set by the stack in the IPv4
 		 * TSO case, but not in IPv6 (at least in FreeBSD 10.2).
 		 * So, set it here because the rest of the flow requires it.
 		 */
 		mp->m_pkthdr.csum_flags |= CSUM_TCP_IPV6;
 		break;
 #endif
 #ifdef INET
 	case ETHERTYPE_IP:
 		ip = (struct ip *)(mp->m_data + elen);
 		if (ip->ip_p != IPPROTO_TCP)
 			return (ENXIO);
 		ip->ip_sum = 0;
 		ip_hlen = ip->ip_hl << 2;
 		th = (struct tcphdr *)((caddr_t)ip + ip_hlen);
 		th->th_sum = in_pseudo(ip->ip_src.s_addr,
 		    ip->ip_dst.s_addr, htons(IPPROTO_TCP));
 		tcp_hlen = th->th_off << 2;
 		break;
 #endif
 	default:
 		printf("%s: CSUM_TSO but no supported IP version (0x%04x)",
 		    __func__, ntohs(etype));
 		return FALSE;
         }
 
         /* Ensure we have at least the IP+TCP header in the first mbuf. */
         if (mp->m_len < elen + ip_hlen + sizeof(struct tcphdr))
 		return FALSE;
 
 	idx = txr->next_avail;
 	buf = &txr->buffers[idx];
 	TXD = (struct i40e_tx_context_desc *) &txr->base[idx];
 	tsolen = mp->m_pkthdr.len - (elen + ip_hlen + tcp_hlen);
 
 	type = I40E_TX_DESC_DTYPE_CONTEXT;
 	cmd = I40E_TX_CTX_DESC_TSO;
 	/* TSO MSS must not be less than 64 */
 	if (mp->m_pkthdr.tso_segsz < IXL_MIN_TSO_MSS) {
 		que->mss_too_small++;
 		mp->m_pkthdr.tso_segsz = IXL_MIN_TSO_MSS;
 	}
 	mss = mp->m_pkthdr.tso_segsz;
 
 	type_cmd_tso_mss = ((u64)type << I40E_TXD_CTX_QW1_DTYPE_SHIFT) |
 	    ((u64)cmd << I40E_TXD_CTX_QW1_CMD_SHIFT) |
 	    ((u64)tsolen << I40E_TXD_CTX_QW1_TSO_LEN_SHIFT) |
 	    ((u64)mss << I40E_TXD_CTX_QW1_MSS_SHIFT);
 	TXD->type_cmd_tso_mss = htole64(type_cmd_tso_mss);
 
 	TXD->tunneling_params = htole32(0);
 	buf->m_head = NULL;
 	buf->eop_index = -1;
 
 	if (++idx == que->num_desc)
 		idx = 0;
 
 	txr->avail--;
 	txr->next_avail = idx;
 
 	return TRUE;
 }
 
 /*             
 ** ixl_get_tx_head - Retrieve the value from the 
 **    location the HW records its HEAD index
 */
 static inline u32
 ixl_get_tx_head(struct ixl_queue *que)
 {
 	struct tx_ring  *txr = &que->txr;
 	void *head = &txr->base[que->num_desc];
 	return LE32_TO_CPU(*(volatile __le32 *)head);
 }
 
 /**********************************************************************
  *
  *  Examine each tx_buffer in the used queue. If the hardware is done
  *  processing the packet then free associated resources. The
  *  tx_buffer is put back on the free queue.
  *
  **********************************************************************/
 bool
 ixl_txeof(struct ixl_queue *que)
 {
 	struct tx_ring		*txr = &que->txr;
 	u32			first, last, head, done, processed;
 	struct ixl_tx_buf	*buf;
 	struct i40e_tx_desc	*tx_desc, *eop_desc;
 
 
 	mtx_assert(&txr->mtx, MA_OWNED);
 
 #ifdef DEV_NETMAP
 	// XXX todo: implement moderation
 	if (netmap_tx_irq(que->vsi->ifp, que->me))
 		return FALSE;
 #endif /* DEF_NETMAP */
 
 	/* These are not the descriptors you seek, move along :) */
 	if (txr->avail == que->num_desc) {
 		atomic_store_rel_32(&txr->watchdog_timer, 0);
 		return FALSE;
 	}
 
 	processed = 0;
 	first = txr->next_to_clean;
 	buf = &txr->buffers[first];
 	tx_desc = (struct i40e_tx_desc *)&txr->base[first];
 	last = buf->eop_index;
 	if (last == -1)
 		return FALSE;
 	eop_desc = (struct i40e_tx_desc *)&txr->base[last];
 
 	/* Get the Head WB value */
 	head = ixl_get_tx_head(que);
 
 	/*
 	** Get the index of the first descriptor
 	** BEYOND the EOP and call that 'done'.
 	** I do this so the comparison in the
 	** inner while loop below can be simple
 	*/
 	if (++last == que->num_desc) last = 0;
 	done = last;
 
         bus_dmamap_sync(txr->dma.tag, txr->dma.map,
             BUS_DMASYNC_POSTREAD);
 	/*
 	** The HEAD index of the ring is written in a 
 	** defined location, this rather than a done bit
 	** is what is used to keep track of what must be
 	** 'cleaned'.
 	*/
 	while (first != head) {
 		/* We clean the range of the packet */
 		while (first != done) {
 			++txr->avail;
 			++processed;
 
 			if (buf->m_head) {
 				txr->bytes += /* for ITR adjustment */
 				    buf->m_head->m_pkthdr.len;
 				txr->tx_bytes += /* for TX stats */
 				    buf->m_head->m_pkthdr.len;
 				bus_dmamap_sync(buf->tag,
 				    buf->map,
 				    BUS_DMASYNC_POSTWRITE);
 				bus_dmamap_unload(buf->tag,
 				    buf->map);
 				m_freem(buf->m_head);
 				buf->m_head = NULL;
 			}
 			buf->eop_index = -1;
 
 			if (++first == que->num_desc)
 				first = 0;
 
 			buf = &txr->buffers[first];
 			tx_desc = &txr->base[first];
 		}
 		++txr->packets;
 		/* See if there is more work now */
 		last = buf->eop_index;
 		if (last != -1) {
 			eop_desc = &txr->base[last];
 			/* Get next done point */
 			if (++last == que->num_desc) last = 0;
 			done = last;
 		} else
 			break;
 	}
 	bus_dmamap_sync(txr->dma.tag, txr->dma.map,
 	    BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
 
 	txr->next_to_clean = first;
 
 
 	/*
 	 * If there are no pending descriptors, clear the timeout.
 	 */
 	if (txr->avail == que->num_desc) {
 		atomic_store_rel_32(&txr->watchdog_timer, 0);
 		return FALSE;
 	}
 
 	return TRUE;
 }
 
 /*********************************************************************
  *
  *  Refresh mbuf buffers for RX descriptor rings
  *   - now keeps its own state so discards due to resource
  *     exhaustion are unnecessary, if an mbuf cannot be obtained
  *     it just returns, keeping its placeholder, thus it can simply
  *     be recalled to try again.
  *
  **********************************************************************/
 static void
 ixl_refresh_mbufs(struct ixl_queue *que, int limit)
 {
 	struct ixl_vsi		*vsi = que->vsi;
 	struct rx_ring		*rxr = &que->rxr;
 	bus_dma_segment_t	hseg[1];
 	bus_dma_segment_t	pseg[1];
 	struct ixl_rx_buf	*buf;
 	struct mbuf		*mh, *mp;
 	int			i, j, nsegs, error;
 	bool			refreshed = FALSE;
 
 	i = j = rxr->next_refresh;
 	/* Control the loop with one beyond */
 	if (++j == que->num_desc)
 		j = 0;
 
 	while (j != limit) {
 		buf = &rxr->buffers[i];
 		if (rxr->hdr_split == FALSE)
 			goto no_split;
 
 		if (buf->m_head == NULL) {
 			mh = m_gethdr(M_NOWAIT, MT_DATA);
 			if (mh == NULL)
 				goto update;
 		} else
 			mh = buf->m_head;
 
 		mh->m_pkthdr.len = mh->m_len = MHLEN;
 		mh->m_len = MHLEN;
 		mh->m_flags |= M_PKTHDR;
 		/* Get the memory mapping */
 		error = bus_dmamap_load_mbuf_sg(rxr->htag,
 		    buf->hmap, mh, hseg, &nsegs, BUS_DMA_NOWAIT);
 		if (error != 0) {
 			printf("Refresh mbufs: hdr dmamap load"
 			    " failure - %d\n", error);
 			m_free(mh);
 			buf->m_head = NULL;
 			goto update;
 		}
 		buf->m_head = mh;
 		bus_dmamap_sync(rxr->htag, buf->hmap,
 		    BUS_DMASYNC_PREREAD);
 		rxr->base[i].read.hdr_addr =
 		   htole64(hseg[0].ds_addr);
 
 no_split:
 		if (buf->m_pack == NULL) {
 			mp = m_getjcl(M_NOWAIT, MT_DATA,
 			    M_PKTHDR, rxr->mbuf_sz);
 			if (mp == NULL)
 				goto update;
 		} else
 			mp = buf->m_pack;
 
 		mp->m_pkthdr.len = mp->m_len = rxr->mbuf_sz;
 		/* Get the memory mapping */
 		error = bus_dmamap_load_mbuf_sg(rxr->ptag,
 		    buf->pmap, mp, pseg, &nsegs, BUS_DMA_NOWAIT);
 		if (error != 0) {
 			printf("Refresh mbufs: payload dmamap load"
 			    " failure - %d\n", error);
 			m_free(mp);
 			buf->m_pack = NULL;
 			goto update;
 		}
 		buf->m_pack = mp;
 		bus_dmamap_sync(rxr->ptag, buf->pmap,
 		    BUS_DMASYNC_PREREAD);
 		rxr->base[i].read.pkt_addr =
 		   htole64(pseg[0].ds_addr);
 		/* Used only when doing header split */
 		rxr->base[i].read.hdr_addr = 0;
 
 		refreshed = TRUE;
 		/* Next is precalculated */
 		i = j;
 		rxr->next_refresh = i;
 		if (++j == que->num_desc)
 			j = 0;
 	}
 update:
 	if (refreshed) /* Update hardware tail index */
 		wr32(vsi->hw, rxr->tail, rxr->next_refresh);
 	return;
 }
 
 
 /*********************************************************************
  *
  *  Allocate memory for rx_buffer structures. Since we use one
  *  rx_buffer per descriptor, the maximum number of rx_buffer's
  *  that we'll need is equal to the number of receive descriptors
  *  that we've defined.
  *
  **********************************************************************/
 int
 ixl_allocate_rx_data(struct ixl_queue *que)
 {
 	struct rx_ring		*rxr = &que->rxr;
 	struct ixl_vsi		*vsi = que->vsi;
 	device_t 		dev = vsi->dev;
 	struct ixl_rx_buf 	*buf;
 	int             	i, bsize, error;
 
 	bsize = sizeof(struct ixl_rx_buf) * que->num_desc;
 	if (!(rxr->buffers =
 	    (struct ixl_rx_buf *) malloc(bsize,
 	    M_DEVBUF, M_NOWAIT | M_ZERO))) {
 		device_printf(dev, "Unable to allocate rx_buffer memory\n");
 		error = ENOMEM;
 		return (error);
 	}
 
 	if ((error = bus_dma_tag_create(bus_get_dma_tag(dev),	/* parent */
 				   1, 0,	/* alignment, bounds */
 				   BUS_SPACE_MAXADDR,	/* lowaddr */
 				   BUS_SPACE_MAXADDR,	/* highaddr */
 				   NULL, NULL,		/* filter, filterarg */
 				   MSIZE,		/* maxsize */
 				   1,			/* nsegments */
 				   MSIZE,		/* maxsegsize */
 				   0,			/* flags */
 				   NULL,		/* lockfunc */
 				   NULL,		/* lockfuncarg */
 				   &rxr->htag))) {
 		device_printf(dev, "Unable to create RX DMA htag\n");
 		return (error);
 	}
 
 	if ((error = bus_dma_tag_create(bus_get_dma_tag(dev),	/* parent */
 				   1, 0,	/* alignment, bounds */
 				   BUS_SPACE_MAXADDR,	/* lowaddr */
 				   BUS_SPACE_MAXADDR,	/* highaddr */
 				   NULL, NULL,		/* filter, filterarg */
 				   MJUM16BYTES,		/* maxsize */
 				   1,			/* nsegments */
 				   MJUM16BYTES,		/* maxsegsize */
 				   0,			/* flags */
 				   NULL,		/* lockfunc */
 				   NULL,		/* lockfuncarg */
 				   &rxr->ptag))) {
 		device_printf(dev, "Unable to create RX DMA ptag\n");
 		return (error);
 	}
 
 	for (i = 0; i < que->num_desc; i++) {
 		buf = &rxr->buffers[i];
 		error = bus_dmamap_create(rxr->htag,
 		    BUS_DMA_NOWAIT, &buf->hmap);
 		if (error) {
 			device_printf(dev, "Unable to create RX head map\n");
 			break;
 		}
 		error = bus_dmamap_create(rxr->ptag,
 		    BUS_DMA_NOWAIT, &buf->pmap);
 		if (error) {
 			device_printf(dev, "Unable to create RX pkt map\n");
 			break;
 		}
 	}
 
 	return (error);
 }
 
 
 /*********************************************************************
  *
  *  (Re)Initialize the queue receive ring and its buffers.
  *
  **********************************************************************/
 int
 ixl_init_rx_ring(struct ixl_queue *que)
 {
 	struct	rx_ring 	*rxr = &que->rxr;
 	struct ixl_vsi		*vsi = que->vsi;
 #if defined(INET6) || defined(INET)
 	struct ifnet		*ifp = vsi->ifp;
 	struct lro_ctrl		*lro = &rxr->lro;
 #endif
 	struct ixl_rx_buf	*buf;
 	bus_dma_segment_t	pseg[1], hseg[1];
 	int			rsize, nsegs, error = 0;
 #ifdef DEV_NETMAP
 	struct netmap_adapter *na = NA(que->vsi->ifp);
 	struct netmap_slot *slot;
 #endif /* DEV_NETMAP */
 
 	IXL_RX_LOCK(rxr);
 #ifdef DEV_NETMAP
 	/* same as in ixl_init_tx_ring() */
 	slot = netmap_reset(na, NR_RX, que->me, 0);
 #endif /* DEV_NETMAP */
 	/* Clear the ring contents */
 	rsize = roundup2(que->num_desc *
 	    sizeof(union i40e_rx_desc), DBA_ALIGN);
 	bzero((void *)rxr->base, rsize);
 	/* Cleanup any existing buffers */
 	for (int i = 0; i < que->num_desc; i++) {
 		buf = &rxr->buffers[i];
 		if (buf->m_head != NULL) {
 			bus_dmamap_sync(rxr->htag, buf->hmap,
 			    BUS_DMASYNC_POSTREAD);
 			bus_dmamap_unload(rxr->htag, buf->hmap);
 			buf->m_head->m_flags |= M_PKTHDR;
 			m_freem(buf->m_head);
 		}
 		if (buf->m_pack != NULL) {
 			bus_dmamap_sync(rxr->ptag, buf->pmap,
 			    BUS_DMASYNC_POSTREAD);
 			bus_dmamap_unload(rxr->ptag, buf->pmap);
 			buf->m_pack->m_flags |= M_PKTHDR;
 			m_freem(buf->m_pack);
 		}
 		buf->m_head = NULL;
 		buf->m_pack = NULL;
 	}
 
 	/* header split is off */
 	rxr->hdr_split = FALSE;
 
 	/* Now replenish the mbufs */
 	for (int j = 0; j != que->num_desc; ++j) {
 		struct mbuf	*mh, *mp;
 
 		buf = &rxr->buffers[j];
 #ifdef DEV_NETMAP
 		/*
 		 * In netmap mode, fill the map and set the buffer
 		 * address in the NIC ring, considering the offset
 		 * between the netmap and NIC rings (see comment in
 		 * ixgbe_setup_transmit_ring() ). No need to allocate
 		 * an mbuf, so end the block with a continue;
 		 */
 		if (slot) {
 			int sj = netmap_idx_n2k(&na->rx_rings[que->me], j);
 			uint64_t paddr;
 			void *addr;
 
 			addr = PNMB(na, slot + sj, &paddr);
 			netmap_load_map(na, rxr->dma.tag, buf->pmap, addr);
 			/* Update descriptor and the cached value */
 			rxr->base[j].read.pkt_addr = htole64(paddr);
 			rxr->base[j].read.hdr_addr = 0;
 			continue;
 		}
 #endif /* DEV_NETMAP */
 		/*
 		** Don't allocate mbufs if not
 		** doing header split, its wasteful
 		*/ 
 		if (rxr->hdr_split == FALSE)
 			goto skip_head;
 
 		/* First the header */
 		buf->m_head = m_gethdr(M_NOWAIT, MT_DATA);
 		if (buf->m_head == NULL) {
 			error = ENOBUFS;
 			goto fail;
 		}
 		m_adj(buf->m_head, ETHER_ALIGN);
 		mh = buf->m_head;
 		mh->m_len = mh->m_pkthdr.len = MHLEN;
 		mh->m_flags |= M_PKTHDR;
 		/* Get the memory mapping */
 		error = bus_dmamap_load_mbuf_sg(rxr->htag,
 		    buf->hmap, buf->m_head, hseg,
 		    &nsegs, BUS_DMA_NOWAIT);
 		if (error != 0) /* Nothing elegant to do here */
 			goto fail;
 		bus_dmamap_sync(rxr->htag,
 		    buf->hmap, BUS_DMASYNC_PREREAD);
 		/* Update descriptor */
 		rxr->base[j].read.hdr_addr = htole64(hseg[0].ds_addr);
 
 skip_head:
 		/* Now the payload cluster */
 		buf->m_pack = m_getjcl(M_NOWAIT, MT_DATA,
 		    M_PKTHDR, rxr->mbuf_sz);
 		if (buf->m_pack == NULL) {
 			error = ENOBUFS;
                         goto fail;
 		}
 		mp = buf->m_pack;
 		mp->m_pkthdr.len = mp->m_len = rxr->mbuf_sz;
 		/* Get the memory mapping */
 		error = bus_dmamap_load_mbuf_sg(rxr->ptag,
 		    buf->pmap, mp, pseg,
 		    &nsegs, BUS_DMA_NOWAIT);
 		if (error != 0)
                         goto fail;
 		bus_dmamap_sync(rxr->ptag,
 		    buf->pmap, BUS_DMASYNC_PREREAD);
 		/* Update descriptor */
 		rxr->base[j].read.pkt_addr = htole64(pseg[0].ds_addr);
 		rxr->base[j].read.hdr_addr = 0;
 	}
 
 
 	/* Setup our descriptor indices */
 	rxr->next_check = 0;
 	rxr->next_refresh = 0;
 	rxr->lro_enabled = FALSE;
 	rxr->split = 0;
 	rxr->bytes = 0;
 	rxr->discard = FALSE;
 
 	wr32(vsi->hw, rxr->tail, que->num_desc - 1);
 	ixl_flush(vsi->hw);
 
 #if defined(INET6) || defined(INET)
 	/*
 	** Now set up the LRO interface:
 	*/
 	if (ifp->if_capenable & IFCAP_LRO) {
 		int err = tcp_lro_init(lro);
 		if (err) {
 			if_printf(ifp, "queue %d: LRO Initialization failed!\n", que->me);
 			goto fail;
 		}
 		INIT_DBG_IF(ifp, "queue %d: RX Soft LRO Initialized", que->me);
 		rxr->lro_enabled = TRUE;
 		lro->ifp = vsi->ifp;
 	}
 #endif
 
 	bus_dmamap_sync(rxr->dma.tag, rxr->dma.map,
 	    BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
 
 fail:
 	IXL_RX_UNLOCK(rxr);
 	return (error);
 }
 
 
 /*********************************************************************
  *
  *  Free station receive ring data structures
  *
  **********************************************************************/
 void
 ixl_free_que_rx(struct ixl_queue *que)
 {
 	struct rx_ring		*rxr = &que->rxr;
 	struct ixl_rx_buf	*buf;
 
 	INIT_DBG_IF(que->vsi->ifp, "queue %d: begin", que->me);
 
 	/* Cleanup any existing buffers */
 	if (rxr->buffers != NULL) {
 		for (int i = 0; i < que->num_desc; i++) {
 			buf = &rxr->buffers[i];
 			if (buf->m_head != NULL) {
 				bus_dmamap_sync(rxr->htag, buf->hmap,
 				    BUS_DMASYNC_POSTREAD);
 				bus_dmamap_unload(rxr->htag, buf->hmap);
 				buf->m_head->m_flags |= M_PKTHDR;
 				m_freem(buf->m_head);
 			}
 			if (buf->m_pack != NULL) {
 				bus_dmamap_sync(rxr->ptag, buf->pmap,
 				    BUS_DMASYNC_POSTREAD);
 				bus_dmamap_unload(rxr->ptag, buf->pmap);
 				buf->m_pack->m_flags |= M_PKTHDR;
 				m_freem(buf->m_pack);
 			}
 			buf->m_head = NULL;
 			buf->m_pack = NULL;
 			if (buf->hmap != NULL) {
 				bus_dmamap_destroy(rxr->htag, buf->hmap);
 				buf->hmap = NULL;
 			}
 			if (buf->pmap != NULL) {
 				bus_dmamap_destroy(rxr->ptag, buf->pmap);
 				buf->pmap = NULL;
 			}
 		}
 		if (rxr->buffers != NULL) {
 			free(rxr->buffers, M_DEVBUF);
 			rxr->buffers = NULL;
 		}
 	}
 
 	if (rxr->htag != NULL) {
 		bus_dma_tag_destroy(rxr->htag);
 		rxr->htag = NULL;
 	}
 	if (rxr->ptag != NULL) {
 		bus_dma_tag_destroy(rxr->ptag);
 		rxr->ptag = NULL;
 	}
 
 	INIT_DBG_IF(que->vsi->ifp, "queue %d: end", que->me);
 	return;
 }
 
 static inline void
 ixl_rx_input(struct rx_ring *rxr, struct ifnet *ifp, struct mbuf *m, u8 ptype)
 {
 
 #if defined(INET6) || defined(INET)
         /*
          * ATM LRO is only for IPv4/TCP packets and TCP checksum of the packet
          * should be computed by hardware. Also it should not have VLAN tag in
          * ethernet header.
          */
         if (rxr->lro_enabled &&
             (ifp->if_capenable & IFCAP_VLAN_HWTAGGING) != 0 &&
             (m->m_pkthdr.csum_flags & (CSUM_DATA_VALID | CSUM_PSEUDO_HDR)) ==
             (CSUM_DATA_VALID | CSUM_PSEUDO_HDR)) {
                 /*
                  * Send to the stack if:
                  **  - LRO not enabled, or
                  **  - no LRO resources, or
                  **  - lro enqueue fails
                  */
                 if (rxr->lro.lro_cnt != 0)
                         if (tcp_lro_rx(&rxr->lro, m, 0) == 0)
                                 return;
         }
 #endif
 	IXL_RX_UNLOCK(rxr);
         (*ifp->if_input)(ifp, m);
 	IXL_RX_LOCK(rxr);
 }
 
 
 static inline void
 ixl_rx_discard(struct rx_ring *rxr, int i)
 {
 	struct ixl_rx_buf	*rbuf;
 
 	rbuf = &rxr->buffers[i];
 
         if (rbuf->fmp != NULL) {/* Partial chain ? */
 		rbuf->fmp->m_flags |= M_PKTHDR;
                 m_freem(rbuf->fmp);
                 rbuf->fmp = NULL;
 	}
 
 	/*
 	** With advanced descriptors the writeback
 	** clobbers the buffer addrs, so its easier
 	** to just free the existing mbufs and take
 	** the normal refresh path to get new buffers
 	** and mapping.
 	*/
 	if (rbuf->m_head) {
 		m_free(rbuf->m_head);
 		rbuf->m_head = NULL;
 	}
  
 	if (rbuf->m_pack) {
 		m_free(rbuf->m_pack);
 		rbuf->m_pack = NULL;
 	}
 
 	return;
 }
 
 #ifdef RSS
 /*
 ** i40e_ptype_to_hash: parse the packet type
 ** to determine the appropriate hash.
 */
 static inline int
 ixl_ptype_to_hash(u8 ptype)
 {
         struct i40e_rx_ptype_decoded	decoded;
 	u8				ex = 0;
 
 	decoded = decode_rx_desc_ptype(ptype);
 	ex = decoded.outer_frag;
 
 	if (!decoded.known)
 		return M_HASHTYPE_OPAQUE_HASH;
 
 	if (decoded.outer_ip == I40E_RX_PTYPE_OUTER_L2) 
 		return M_HASHTYPE_OPAQUE_HASH;
 
 	/* Note: anything that gets to this point is IP */
         if (decoded.outer_ip_ver == I40E_RX_PTYPE_OUTER_IPV6) { 
 		switch (decoded.inner_prot) {
 			case I40E_RX_PTYPE_INNER_PROT_TCP:
 				if (ex)
 					return M_HASHTYPE_RSS_TCP_IPV6_EX;
 				else
 					return M_HASHTYPE_RSS_TCP_IPV6;
 			case I40E_RX_PTYPE_INNER_PROT_UDP:
 				if (ex)
 					return M_HASHTYPE_RSS_UDP_IPV6_EX;
 				else
 					return M_HASHTYPE_RSS_UDP_IPV6;
 			default:
 				if (ex)
 					return M_HASHTYPE_RSS_IPV6_EX;
 				else
 					return M_HASHTYPE_RSS_IPV6;
 		}
 	}
         if (decoded.outer_ip_ver == I40E_RX_PTYPE_OUTER_IPV4) { 
 		switch (decoded.inner_prot) {
 			case I40E_RX_PTYPE_INNER_PROT_TCP:
 					return M_HASHTYPE_RSS_TCP_IPV4;
 			case I40E_RX_PTYPE_INNER_PROT_UDP:
 				if (ex)
 					return M_HASHTYPE_RSS_UDP_IPV4_EX;
 				else
 					return M_HASHTYPE_RSS_UDP_IPV4;
 			default:
 					return M_HASHTYPE_RSS_IPV4;
 		}
 	}
 	/* We should never get here!! */
 	return M_HASHTYPE_OPAQUE_HASH;
 }
 #endif /* RSS */
 
 /*********************************************************************
  *
  *  This routine executes in interrupt context. It replenishes
  *  the mbufs in the descriptor and sends data which has been
  *  dma'ed into host memory to upper layer.
  *
  *  We loop at most count times if count is > 0, or until done if
  *  count < 0.
  *
  *  Return TRUE for more work, FALSE for all clean.
  *********************************************************************/
 bool
 ixl_rxeof(struct ixl_queue *que, int count)
 {
 	struct ixl_vsi		*vsi = que->vsi;
 	struct rx_ring		*rxr = &que->rxr;
 	struct ifnet		*ifp = vsi->ifp;
 #if defined(INET6) || defined(INET)
 	struct lro_ctrl		*lro = &rxr->lro;
 #endif
 	int			i, nextp, processed = 0;
 	union i40e_rx_desc	*cur;
 	struct ixl_rx_buf	*rbuf, *nbuf;
 
 
 	IXL_RX_LOCK(rxr);
 
 #ifdef DEV_NETMAP
 	if (netmap_rx_irq(ifp, que->me, &count)) {
 		IXL_RX_UNLOCK(rxr);
 		return (FALSE);
 	}
 #endif /* DEV_NETMAP */
 
 	for (i = rxr->next_check; count != 0;) {
 		struct mbuf	*sendmp, *mh, *mp;
 		u32		status, error;
 		u16		hlen, plen, vtag;
 		u64		qword;
 		u8		ptype;
 		bool		eop;
  
 		/* Sync the ring. */
 		bus_dmamap_sync(rxr->dma.tag, rxr->dma.map,
 		    BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
 
 		cur = &rxr->base[i];
 		qword = le64toh(cur->wb.qword1.status_error_len);
 		status = (qword & I40E_RXD_QW1_STATUS_MASK)
 		    >> I40E_RXD_QW1_STATUS_SHIFT;
 		error = (qword & I40E_RXD_QW1_ERROR_MASK)
 		    >> I40E_RXD_QW1_ERROR_SHIFT;
 		plen = (qword & I40E_RXD_QW1_LENGTH_PBUF_MASK)
 		    >> I40E_RXD_QW1_LENGTH_PBUF_SHIFT;
 		hlen = (qword & I40E_RXD_QW1_LENGTH_HBUF_MASK)
 		    >> I40E_RXD_QW1_LENGTH_HBUF_SHIFT;
 		ptype = (qword & I40E_RXD_QW1_PTYPE_MASK)
 		    >> I40E_RXD_QW1_PTYPE_SHIFT;
 
 		if ((status & (1 << I40E_RX_DESC_STATUS_DD_SHIFT)) == 0) {
 			++rxr->not_done;
 			break;
 		}
 		if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0)
 			break;
 
 		count--;
 		sendmp = NULL;
 		nbuf = NULL;
 		cur->wb.qword1.status_error_len = 0;
 		rbuf = &rxr->buffers[i];
 		mh = rbuf->m_head;
 		mp = rbuf->m_pack;
 		eop = (status & (1 << I40E_RX_DESC_STATUS_EOF_SHIFT));
 		if (status & (1 << I40E_RX_DESC_STATUS_L2TAG1P_SHIFT))
 			vtag = le16toh(cur->wb.qword0.lo_dword.l2tag1);
 		else
 			vtag = 0;
 
 		/* Remove device access to the rx buffers. */
 		if (rbuf->m_head != NULL) {
 			bus_dmamap_sync(rxr->htag, rbuf->hmap,
 			    BUS_DMASYNC_POSTREAD);
 			bus_dmamap_unload(rxr->htag, rbuf->hmap);
 		}
 		if (rbuf->m_pack != NULL) {
 			bus_dmamap_sync(rxr->ptag, rbuf->pmap,
 			    BUS_DMASYNC_POSTREAD);
 			bus_dmamap_unload(rxr->ptag, rbuf->pmap);
 		}
 
 		/*
 		** Make sure bad packets are discarded,
 		** note that only EOP descriptor has valid
 		** error results.
 		*/
                 if (eop && (error & (1 << I40E_RX_DESC_ERROR_RXE_SHIFT))) {
 			rxr->desc_errs++;
 			ixl_rx_discard(rxr, i);
 			goto next_desc;
 		}
 
 		/* Prefetch the next buffer */
 		if (!eop) {
 			nextp = i + 1;
 			if (nextp == que->num_desc)
 				nextp = 0;
 			nbuf = &rxr->buffers[nextp];
 			prefetch(nbuf);
 		}
 
 		/*
 		** The header mbuf is ONLY used when header 
 		** split is enabled, otherwise we get normal 
 		** behavior, ie, both header and payload
 		** are DMA'd into the payload buffer.
 		**
 		** Rather than using the fmp/lmp global pointers
 		** we now keep the head of a packet chain in the
 		** buffer struct and pass this along from one
 		** descriptor to the next, until we get EOP.
 		*/
 		if (rxr->hdr_split && (rbuf->fmp == NULL)) {
 			if (hlen > IXL_RX_HDR)
 				hlen = IXL_RX_HDR;
 			mh->m_len = hlen;
 			mh->m_flags |= M_PKTHDR;
 			mh->m_next = NULL;
 			mh->m_pkthdr.len = mh->m_len;
 			/* Null buf pointer so it is refreshed */
 			rbuf->m_head = NULL;
 			/*
 			** Check the payload length, this
 			** could be zero if its a small
 			** packet.
 			*/
 			if (plen > 0) {
 				mp->m_len = plen;
 				mp->m_next = NULL;
 				mp->m_flags &= ~M_PKTHDR;
 				mh->m_next = mp;
 				mh->m_pkthdr.len += mp->m_len;
 				/* Null buf pointer so it is refreshed */
 				rbuf->m_pack = NULL;
 				rxr->split++;
 			}
 			/*
 			** Now create the forward
 			** chain so when complete 
 			** we wont have to.
 			*/
                         if (eop == 0) {
 				/* stash the chain head */
                                 nbuf->fmp = mh;
 				/* Make forward chain */
                                 if (plen)
                                         mp->m_next = nbuf->m_pack;
                                 else
                                         mh->m_next = nbuf->m_pack;
                         } else {
 				/* Singlet, prepare to send */
                                 sendmp = mh;
                                 if (vtag) {
                                         sendmp->m_pkthdr.ether_vtag = vtag;
                                         sendmp->m_flags |= M_VLANTAG;
                                 }
                         }
 		} else {
 			/*
 			** Either no header split, or a
 			** secondary piece of a fragmented
 			** split packet.
 			*/
 			mp->m_len = plen;
 			/*
 			** See if there is a stored head
 			** that determines what we are
 			*/
 			sendmp = rbuf->fmp;
 			rbuf->m_pack = rbuf->fmp = NULL;
 
 			if (sendmp != NULL) /* secondary frag */
 				sendmp->m_pkthdr.len += mp->m_len;
 			else {
 				/* first desc of a non-ps chain */
 				sendmp = mp;
 				sendmp->m_flags |= M_PKTHDR;
 				sendmp->m_pkthdr.len = mp->m_len;
                         }
 			/* Pass the head pointer on */
 			if (eop == 0) {
 				nbuf->fmp = sendmp;
 				sendmp = NULL;
 				mp->m_next = nbuf->m_pack;
 			}
 		}
 		++processed;
 		/* Sending this frame? */
 		if (eop) {
 			sendmp->m_pkthdr.rcvif = ifp;
 			/* gather stats */
 			rxr->rx_packets++;
 			rxr->rx_bytes += sendmp->m_pkthdr.len;
 			/* capture data for dynamic ITR adjustment */
 			rxr->packets++;
 			rxr->bytes += sendmp->m_pkthdr.len;
 			/* Set VLAN tag (field only valid in eop desc) */
 			if (vtag) {
 				sendmp->m_pkthdr.ether_vtag = vtag;
 				sendmp->m_flags |= M_VLANTAG;
 			}
 			if ((ifp->if_capenable & IFCAP_RXCSUM) != 0)
 				ixl_rx_checksum(sendmp, status, error, ptype);
 #ifdef RSS
 			sendmp->m_pkthdr.flowid =
 			    le32toh(cur->wb.qword0.hi_dword.rss);
 			M_HASHTYPE_SET(sendmp, ixl_ptype_to_hash(ptype));
 #else
 			sendmp->m_pkthdr.flowid = que->msix;
 			M_HASHTYPE_SET(sendmp, M_HASHTYPE_OPAQUE);
 #endif
 		}
 next_desc:
 		bus_dmamap_sync(rxr->dma.tag, rxr->dma.map,
 		    BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
 
 		/* Advance our pointers to the next descriptor. */
 		if (++i == que->num_desc)
 			i = 0;
 
 		/* Now send to the stack or do LRO */
 		if (sendmp != NULL) {
 			rxr->next_check = i;
 			ixl_rx_input(rxr, ifp, sendmp, ptype);
 			i = rxr->next_check;
 		}
 
                /* Every 8 descriptors we go to refresh mbufs */
 		if (processed == 8) {
 			ixl_refresh_mbufs(que, i);
 			processed = 0;
 		}
 	}
 
 	/* Refresh any remaining buf structs */
 	if (ixl_rx_unrefreshed(que))
 		ixl_refresh_mbufs(que, i);
 
 	rxr->next_check = i;
 
 #if defined(INET6) || defined(INET)
 	/*
 	 * Flush any outstanding LRO work
 	 */
 #if __FreeBSD_version >= 1100105
 	tcp_lro_flush_all(lro);
 #else
 	struct lro_entry *queued;
 	while ((queued = SLIST_FIRST(&lro->lro_active)) != NULL) {
 		SLIST_REMOVE_HEAD(&lro->lro_active, next);
 		tcp_lro_flush(lro, queued);
 	}
 #endif
 #endif /* defined(INET6) || defined(INET) */
 
 	IXL_RX_UNLOCK(rxr);
 	return (FALSE);
 }
 
 
 /*********************************************************************
  *
  *  Verify that the hardware indicated that the checksum is valid.
  *  Inform the stack about the status of checksum so that stack
  *  doesn't spend time verifying the checksum.
  *
  *********************************************************************/
 static void
 ixl_rx_checksum(struct mbuf * mp, u32 status, u32 error, u8 ptype)
 {
 	struct i40e_rx_ptype_decoded decoded;
 
 	decoded = decode_rx_desc_ptype(ptype);
 
 	/* Errors? */
  	if (error & ((1 << I40E_RX_DESC_ERROR_IPE_SHIFT) |
 	    (1 << I40E_RX_DESC_ERROR_L4E_SHIFT))) {
 		mp->m_pkthdr.csum_flags = 0;
 		return;
 	}
 
 	/* IPv6 with extension headers likely have bad csum */
 	if (decoded.outer_ip == I40E_RX_PTYPE_OUTER_IP &&
 	    decoded.outer_ip_ver == I40E_RX_PTYPE_OUTER_IPV6)
 		if (status &
 		    (1 << I40E_RX_DESC_STATUS_IPV6EXADD_SHIFT)) {
 			mp->m_pkthdr.csum_flags = 0;
 			return;
 		}
 
  
 	/* IP Checksum Good */
 	mp->m_pkthdr.csum_flags = CSUM_IP_CHECKED;
 	mp->m_pkthdr.csum_flags |= CSUM_IP_VALID;
 
 	if (status & (1 << I40E_RX_DESC_STATUS_L3L4P_SHIFT)) {
 		mp->m_pkthdr.csum_flags |= 
 		    (CSUM_DATA_VALID | CSUM_PSEUDO_HDR);
 		mp->m_pkthdr.csum_data |= htons(0xffff);
 	}
 	return;
 }
 
 #if __FreeBSD_version >= 1100000
 uint64_t
 ixl_get_counter(if_t ifp, ift_counter cnt)
 {
 	struct ixl_vsi *vsi;
 
 	vsi = if_getsoftc(ifp);
 
 	switch (cnt) {
 	case IFCOUNTER_IPACKETS:
 		return (vsi->ipackets);
 	case IFCOUNTER_IERRORS:
 		return (vsi->ierrors);
 	case IFCOUNTER_OPACKETS:
 		return (vsi->opackets);
 	case IFCOUNTER_OERRORS:
 		return (vsi->oerrors);
 	case IFCOUNTER_COLLISIONS:
 		/* Collisions are by standard impossible in 40G/10G Ethernet */
 		return (0);
 	case IFCOUNTER_IBYTES:
 		return (vsi->ibytes);
 	case IFCOUNTER_OBYTES:
 		return (vsi->obytes);
 	case IFCOUNTER_IMCASTS:
 		return (vsi->imcasts);
 	case IFCOUNTER_OMCASTS:
 		return (vsi->omcasts);
 	case IFCOUNTER_IQDROPS:
 		return (vsi->iqdrops);
 	case IFCOUNTER_OQDROPS:
 		return (vsi->oqdrops);
 	case IFCOUNTER_NOPROTO:
 		return (vsi->noproto);
 	default:
 		return (if_get_counter_default(ifp, cnt));
 	}
 }
 #endif