Index: head/sys/arm/allwinner/a10_mmc.c =================================================================== --- head/sys/arm/allwinner/a10_mmc.c (revision 320611) +++ head/sys/arm/allwinner/a10_mmc.c (revision 320612) @@ -1,921 +1,922 @@ /*- * Copyright (c) 2013 Alexander Fedorov * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. */ #include __FBSDID("$FreeBSD$"); #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #define A10_MMC_MEMRES 0 #define A10_MMC_IRQRES 1 #define A10_MMC_RESSZ 2 #define A10_MMC_DMA_SEGS ((MAXPHYS / PAGE_SIZE) + 1) #define A10_MMC_DMA_MAX_SIZE 0x2000 #define A10_MMC_DMA_FTRGLEVEL 0x20070008 #define A10_MMC_RESET_RETRY 1000 #define CARD_ID_FREQUENCY 400000 static struct ofw_compat_data compat_data[] = { {"allwinner,sun4i-a10-mmc", 1}, {"allwinner,sun5i-a13-mmc", 1}, {"allwinner,sun7i-a20-mmc", 1}, + {"allwinner,sun50i-a64-mmc", 1}, {NULL, 0} }; struct a10_mmc_softc { device_t a10_dev; clk_t a10_clk_ahb; clk_t a10_clk_mmc; hwreset_t a10_rst_ahb; int a10_bus_busy; int a10_resid; int a10_timeout; struct callout a10_timeoutc; struct mmc_host a10_host; struct mmc_request * a10_req; struct mtx a10_mtx; struct resource * a10_res[A10_MMC_RESSZ]; uint32_t a10_intr; uint32_t a10_intr_wait; void * a10_intrhand; /* Fields required for DMA access. */ bus_addr_t a10_dma_desc_phys; bus_dmamap_t a10_dma_map; bus_dma_tag_t a10_dma_tag; void * a10_dma_desc; bus_dmamap_t a10_dma_buf_map; bus_dma_tag_t a10_dma_buf_tag; int a10_dma_map_err; }; static struct resource_spec a10_mmc_res_spec[] = { { SYS_RES_MEMORY, 0, RF_ACTIVE }, { SYS_RES_IRQ, 0, RF_ACTIVE | RF_SHAREABLE }, { -1, 0, 0 } }; static int a10_mmc_probe(device_t); static int a10_mmc_attach(device_t); static int a10_mmc_detach(device_t); static int a10_mmc_setup_dma(struct a10_mmc_softc *); static int a10_mmc_reset(struct a10_mmc_softc *); static void a10_mmc_intr(void *); static int a10_mmc_update_clock(struct a10_mmc_softc *, uint32_t); static int a10_mmc_update_ios(device_t, device_t); static int a10_mmc_request(device_t, device_t, struct mmc_request *); static int a10_mmc_get_ro(device_t, device_t); static int a10_mmc_acquire_host(device_t, device_t); static int a10_mmc_release_host(device_t, device_t); #define A10_MMC_LOCK(_sc) mtx_lock(&(_sc)->a10_mtx) #define A10_MMC_UNLOCK(_sc) mtx_unlock(&(_sc)->a10_mtx) #define A10_MMC_READ_4(_sc, _reg) \ bus_read_4((_sc)->a10_res[A10_MMC_MEMRES], _reg) #define A10_MMC_WRITE_4(_sc, _reg, _value) \ bus_write_4((_sc)->a10_res[A10_MMC_MEMRES], _reg, _value) static int a10_mmc_probe(device_t dev) { if (!ofw_bus_status_okay(dev)) return (ENXIO); if (ofw_bus_search_compatible(dev, compat_data)->ocd_data == 0) return (ENXIO); device_set_desc(dev, "Allwinner Integrated MMC/SD controller"); return (BUS_PROBE_DEFAULT); } static int a10_mmc_attach(device_t dev) { device_t child; struct a10_mmc_softc *sc; struct sysctl_ctx_list *ctx; struct sysctl_oid_list *tree; uint32_t bus_width; phandle_t node; int error; node = ofw_bus_get_node(dev); sc = device_get_softc(dev); sc->a10_dev = dev; sc->a10_req = NULL; if (bus_alloc_resources(dev, a10_mmc_res_spec, sc->a10_res) != 0) { device_printf(dev, "cannot allocate device resources\n"); return (ENXIO); } if (bus_setup_intr(dev, sc->a10_res[A10_MMC_IRQRES], INTR_TYPE_MISC | INTR_MPSAFE, NULL, a10_mmc_intr, sc, &sc->a10_intrhand)) { bus_release_resources(dev, a10_mmc_res_spec, sc->a10_res); device_printf(dev, "cannot setup interrupt handler\n"); return (ENXIO); } mtx_init(&sc->a10_mtx, device_get_nameunit(sc->a10_dev), "a10_mmc", MTX_DEF); callout_init_mtx(&sc->a10_timeoutc, &sc->a10_mtx, 0); /* De-assert reset */ if (hwreset_get_by_ofw_name(dev, 0, "ahb", &sc->a10_rst_ahb) == 0) { error = hwreset_deassert(sc->a10_rst_ahb); if (error != 0) { device_printf(dev, "cannot de-assert reset\n"); goto fail; } } /* Activate the module clock. */ error = clk_get_by_ofw_name(dev, 0, "ahb", &sc->a10_clk_ahb); if (error != 0) { device_printf(dev, "cannot get ahb clock\n"); goto fail; } error = clk_enable(sc->a10_clk_ahb); if (error != 0) { device_printf(dev, "cannot enable ahb clock\n"); goto fail; } error = clk_get_by_ofw_name(dev, 0, "mmc", &sc->a10_clk_mmc); if (error != 0) { device_printf(dev, "cannot get mmc clock\n"); goto fail; } error = clk_set_freq(sc->a10_clk_mmc, CARD_ID_FREQUENCY, CLK_SET_ROUND_DOWN); if (error != 0) { device_printf(dev, "cannot init mmc clock\n"); goto fail; } error = clk_enable(sc->a10_clk_mmc); if (error != 0) { device_printf(dev, "cannot enable mmc clock\n"); goto fail; } sc->a10_timeout = 10; ctx = device_get_sysctl_ctx(dev); tree = SYSCTL_CHILDREN(device_get_sysctl_tree(dev)); SYSCTL_ADD_INT(ctx, tree, OID_AUTO, "req_timeout", CTLFLAG_RW, &sc->a10_timeout, 0, "Request timeout in seconds"); /* Hardware reset */ A10_MMC_WRITE_4(sc, A10_MMC_HWRST, 1); DELAY(100); A10_MMC_WRITE_4(sc, A10_MMC_HWRST, 0); DELAY(500); /* Soft Reset controller. */ if (a10_mmc_reset(sc) != 0) { device_printf(dev, "cannot reset the controller\n"); goto fail; } if (a10_mmc_setup_dma(sc) != 0) { device_printf(sc->a10_dev, "Couldn't setup DMA!\n"); goto fail; } if (OF_getencprop(node, "bus-width", &bus_width, sizeof(uint32_t)) <= 0) bus_width = 4; sc->a10_host.f_min = 400000; sc->a10_host.f_max = 52000000; sc->a10_host.host_ocr = MMC_OCR_320_330 | MMC_OCR_330_340; sc->a10_host.mode = mode_sd; sc->a10_host.caps = MMC_CAP_HSPEED; if (bus_width >= 4) sc->a10_host.caps |= MMC_CAP_4_BIT_DATA; if (bus_width >= 8) sc->a10_host.caps |= MMC_CAP_8_BIT_DATA; child = device_add_child(dev, "mmc", -1); if (child == NULL) { device_printf(dev, "attaching MMC bus failed!\n"); goto fail; } if (device_probe_and_attach(child) != 0) { device_printf(dev, "attaching MMC child failed!\n"); device_delete_child(dev, child); goto fail; } return (0); fail: callout_drain(&sc->a10_timeoutc); mtx_destroy(&sc->a10_mtx); bus_teardown_intr(dev, sc->a10_res[A10_MMC_IRQRES], sc->a10_intrhand); bus_release_resources(dev, a10_mmc_res_spec, sc->a10_res); return (ENXIO); } static int a10_mmc_detach(device_t dev) { return (EBUSY); } static void a10_dma_desc_cb(void *arg, bus_dma_segment_t *segs, int nsegs, int err) { struct a10_mmc_softc *sc; sc = (struct a10_mmc_softc *)arg; if (err) { sc->a10_dma_map_err = err; return; } sc->a10_dma_desc_phys = segs[0].ds_addr; } static int a10_mmc_setup_dma(struct a10_mmc_softc *sc) { int dma_desc_size, error; /* Allocate the DMA descriptor memory. */ dma_desc_size = sizeof(struct a10_mmc_dma_desc) * A10_MMC_DMA_SEGS; error = bus_dma_tag_create(bus_get_dma_tag(sc->a10_dev), A10_MMC_DMA_ALIGN, 0, BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, dma_desc_size, 1, dma_desc_size, 0, NULL, NULL, &sc->a10_dma_tag); if (error) return (error); error = bus_dmamem_alloc(sc->a10_dma_tag, &sc->a10_dma_desc, BUS_DMA_WAITOK | BUS_DMA_ZERO, &sc->a10_dma_map); if (error) return (error); error = bus_dmamap_load(sc->a10_dma_tag, sc->a10_dma_map, sc->a10_dma_desc, dma_desc_size, a10_dma_desc_cb, sc, 0); if (error) return (error); if (sc->a10_dma_map_err) return (sc->a10_dma_map_err); /* Create the DMA map for data transfers. */ error = bus_dma_tag_create(bus_get_dma_tag(sc->a10_dev), A10_MMC_DMA_ALIGN, 0, BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, A10_MMC_DMA_MAX_SIZE * A10_MMC_DMA_SEGS, A10_MMC_DMA_SEGS, A10_MMC_DMA_MAX_SIZE, BUS_DMA_ALLOCNOW, NULL, NULL, &sc->a10_dma_buf_tag); if (error) return (error); error = bus_dmamap_create(sc->a10_dma_buf_tag, 0, &sc->a10_dma_buf_map); if (error) return (error); return (0); } static void a10_dma_cb(void *arg, bus_dma_segment_t *segs, int nsegs, int err) { int i; struct a10_mmc_dma_desc *dma_desc; struct a10_mmc_softc *sc; sc = (struct a10_mmc_softc *)arg; sc->a10_dma_map_err = err; if (err) return; dma_desc = sc->a10_dma_desc; for (i = 0; i < nsegs; i++) { dma_desc[i].buf_size = segs[i].ds_len; dma_desc[i].buf_addr = segs[i].ds_addr; dma_desc[i].config = A10_MMC_DMA_CONFIG_CH | A10_MMC_DMA_CONFIG_OWN; if (i == 0) dma_desc[i].config |= A10_MMC_DMA_CONFIG_FD; if (i < (nsegs - 1)) { dma_desc[i].config |= A10_MMC_DMA_CONFIG_DIC; dma_desc[i].next = sc->a10_dma_desc_phys + ((i + 1) * sizeof(struct a10_mmc_dma_desc)); } else { dma_desc[i].config |= A10_MMC_DMA_CONFIG_LD | A10_MMC_DMA_CONFIG_ER; dma_desc[i].next = 0; } } } static int a10_mmc_prepare_dma(struct a10_mmc_softc *sc) { bus_dmasync_op_t sync_op; int error; struct mmc_command *cmd; uint32_t val; cmd = sc->a10_req->cmd; if (cmd->data->len > A10_MMC_DMA_MAX_SIZE * A10_MMC_DMA_SEGS) return (EFBIG); error = bus_dmamap_load(sc->a10_dma_buf_tag, sc->a10_dma_buf_map, cmd->data->data, cmd->data->len, a10_dma_cb, sc, 0); if (error) return (error); if (sc->a10_dma_map_err) return (sc->a10_dma_map_err); if (cmd->data->flags & MMC_DATA_WRITE) sync_op = BUS_DMASYNC_PREWRITE; else sync_op = BUS_DMASYNC_PREREAD; bus_dmamap_sync(sc->a10_dma_buf_tag, sc->a10_dma_buf_map, sync_op); bus_dmamap_sync(sc->a10_dma_tag, sc->a10_dma_map, BUS_DMASYNC_PREWRITE); /* Enable DMA */ val = A10_MMC_READ_4(sc, A10_MMC_GCTL); val &= ~A10_MMC_CTRL_FIFO_AC_MOD; val |= A10_MMC_CTRL_DMA_ENB; A10_MMC_WRITE_4(sc, A10_MMC_GCTL, val); /* Reset DMA */ val |= A10_MMC_CTRL_DMA_RST; A10_MMC_WRITE_4(sc, A10_MMC_GCTL, val); A10_MMC_WRITE_4(sc, A10_MMC_DMAC, A10_MMC_DMAC_IDMAC_SOFT_RST); A10_MMC_WRITE_4(sc, A10_MMC_DMAC, A10_MMC_DMAC_IDMAC_IDMA_ON | A10_MMC_DMAC_IDMAC_FIX_BURST); /* Enable RX or TX DMA interrupt */ if (cmd->data->flags & MMC_DATA_WRITE) val |= A10_MMC_IDST_TX_INT; else val |= A10_MMC_IDST_RX_INT; A10_MMC_WRITE_4(sc, A10_MMC_IDIE, val); /* Set DMA descritptor list address */ A10_MMC_WRITE_4(sc, A10_MMC_DLBA, sc->a10_dma_desc_phys); /* FIFO trigger level */ A10_MMC_WRITE_4(sc, A10_MMC_FWLR, A10_MMC_DMA_FTRGLEVEL); return (0); } static int a10_mmc_reset(struct a10_mmc_softc *sc) { int timeout; A10_MMC_WRITE_4(sc, A10_MMC_GCTL, A10_MMC_RESET); timeout = 1000; while (--timeout > 0) { if ((A10_MMC_READ_4(sc, A10_MMC_GCTL) & A10_MMC_RESET) == 0) break; DELAY(100); } if (timeout == 0) return (ETIMEDOUT); /* Set the timeout. */ A10_MMC_WRITE_4(sc, A10_MMC_TMOR, A10_MMC_TMOR_DTO_LMT_SHIFT(A10_MMC_TMOR_DTO_LMT_MASK) | A10_MMC_TMOR_RTO_LMT_SHIFT(A10_MMC_TMOR_RTO_LMT_MASK)); /* Clear pending interrupts. */ A10_MMC_WRITE_4(sc, A10_MMC_RISR, 0xffffffff); A10_MMC_WRITE_4(sc, A10_MMC_IDST, 0xffffffff); /* Unmask interrupts. */ A10_MMC_WRITE_4(sc, A10_MMC_IMKR, A10_MMC_INT_CMD_DONE | A10_MMC_INT_ERR_BIT | A10_MMC_INT_DATA_OVER | A10_MMC_INT_AUTO_STOP_DONE); /* Enable interrupts and AHB access. */ A10_MMC_WRITE_4(sc, A10_MMC_GCTL, A10_MMC_READ_4(sc, A10_MMC_GCTL) | A10_MMC_CTRL_INT_ENB); return (0); } static void a10_mmc_req_done(struct a10_mmc_softc *sc) { struct mmc_command *cmd; struct mmc_request *req; uint32_t val, mask; int retry; cmd = sc->a10_req->cmd; if (cmd->error != MMC_ERR_NONE) { /* Reset the FIFO and DMA engines. */ mask = A10_MMC_CTRL_FIFO_RST | A10_MMC_CTRL_DMA_RST; val = A10_MMC_READ_4(sc, A10_MMC_GCTL); A10_MMC_WRITE_4(sc, A10_MMC_GCTL, val | mask); retry = A10_MMC_RESET_RETRY; while (--retry > 0) { val = A10_MMC_READ_4(sc, A10_MMC_GCTL); if ((val & mask) == 0) break; DELAY(10); } if (retry == 0) device_printf(sc->a10_dev, "timeout resetting DMA/FIFO\n"); a10_mmc_update_clock(sc, 1); } req = sc->a10_req; callout_stop(&sc->a10_timeoutc); sc->a10_req = NULL; sc->a10_intr = 0; sc->a10_resid = 0; sc->a10_dma_map_err = 0; sc->a10_intr_wait = 0; req->done(req); } static void a10_mmc_req_ok(struct a10_mmc_softc *sc) { int timeout; struct mmc_command *cmd; uint32_t status; timeout = 1000; while (--timeout > 0) { status = A10_MMC_READ_4(sc, A10_MMC_STAR); if ((status & A10_MMC_STAR_CARD_BUSY) == 0) break; DELAY(1000); } cmd = sc->a10_req->cmd; if (timeout == 0) { cmd->error = MMC_ERR_FAILED; a10_mmc_req_done(sc); return; } if (cmd->flags & MMC_RSP_PRESENT) { if (cmd->flags & MMC_RSP_136) { cmd->resp[0] = A10_MMC_READ_4(sc, A10_MMC_RESP3); cmd->resp[1] = A10_MMC_READ_4(sc, A10_MMC_RESP2); cmd->resp[2] = A10_MMC_READ_4(sc, A10_MMC_RESP1); cmd->resp[3] = A10_MMC_READ_4(sc, A10_MMC_RESP0); } else cmd->resp[0] = A10_MMC_READ_4(sc, A10_MMC_RESP0); } /* All data has been transferred ? */ if (cmd->data != NULL && (sc->a10_resid << 2) < cmd->data->len) cmd->error = MMC_ERR_FAILED; a10_mmc_req_done(sc); } static void a10_mmc_timeout(void *arg) { struct a10_mmc_softc *sc; sc = (struct a10_mmc_softc *)arg; if (sc->a10_req != NULL) { device_printf(sc->a10_dev, "controller timeout\n"); sc->a10_req->cmd->error = MMC_ERR_TIMEOUT; a10_mmc_req_done(sc); } else device_printf(sc->a10_dev, "Spurious timeout - no active request\n"); } static void a10_mmc_intr(void *arg) { bus_dmasync_op_t sync_op; struct a10_mmc_softc *sc; struct mmc_data *data; uint32_t idst, imask, rint; sc = (struct a10_mmc_softc *)arg; A10_MMC_LOCK(sc); rint = A10_MMC_READ_4(sc, A10_MMC_RISR); idst = A10_MMC_READ_4(sc, A10_MMC_IDST); imask = A10_MMC_READ_4(sc, A10_MMC_IMKR); if (idst == 0 && imask == 0 && rint == 0) { A10_MMC_UNLOCK(sc); return; } #ifdef DEBUG device_printf(sc->a10_dev, "idst: %#x, imask: %#x, rint: %#x\n", idst, imask, rint); #endif if (sc->a10_req == NULL) { device_printf(sc->a10_dev, "Spurious interrupt - no active request, rint: 0x%08X\n", rint); goto end; } if (rint & A10_MMC_INT_ERR_BIT) { device_printf(sc->a10_dev, "error rint: 0x%08X\n", rint); if (rint & A10_MMC_INT_RESP_TIMEOUT) sc->a10_req->cmd->error = MMC_ERR_TIMEOUT; else sc->a10_req->cmd->error = MMC_ERR_FAILED; a10_mmc_req_done(sc); goto end; } if (idst & A10_MMC_IDST_ERROR) { device_printf(sc->a10_dev, "error idst: 0x%08x\n", idst); sc->a10_req->cmd->error = MMC_ERR_FAILED; a10_mmc_req_done(sc); goto end; } sc->a10_intr |= rint; data = sc->a10_req->cmd->data; if (data != NULL && (idst & A10_MMC_IDST_COMPLETE) != 0) { if (data->flags & MMC_DATA_WRITE) sync_op = BUS_DMASYNC_POSTWRITE; else sync_op = BUS_DMASYNC_POSTREAD; bus_dmamap_sync(sc->a10_dma_buf_tag, sc->a10_dma_buf_map, sync_op); bus_dmamap_sync(sc->a10_dma_tag, sc->a10_dma_map, BUS_DMASYNC_POSTWRITE); bus_dmamap_unload(sc->a10_dma_buf_tag, sc->a10_dma_buf_map); sc->a10_resid = data->len >> 2; } if ((sc->a10_intr & sc->a10_intr_wait) == sc->a10_intr_wait) a10_mmc_req_ok(sc); end: A10_MMC_WRITE_4(sc, A10_MMC_IDST, idst); A10_MMC_WRITE_4(sc, A10_MMC_RISR, rint); A10_MMC_UNLOCK(sc); } static int a10_mmc_request(device_t bus, device_t child, struct mmc_request *req) { int blksz; struct a10_mmc_softc *sc; struct mmc_command *cmd; uint32_t cmdreg; int err; sc = device_get_softc(bus); A10_MMC_LOCK(sc); if (sc->a10_req) { A10_MMC_UNLOCK(sc); return (EBUSY); } sc->a10_req = req; cmd = req->cmd; cmdreg = A10_MMC_CMDR_LOAD; if (cmd->opcode == MMC_GO_IDLE_STATE) cmdreg |= A10_MMC_CMDR_SEND_INIT_SEQ; if (cmd->flags & MMC_RSP_PRESENT) cmdreg |= A10_MMC_CMDR_RESP_RCV; if (cmd->flags & MMC_RSP_136) cmdreg |= A10_MMC_CMDR_LONG_RESP; if (cmd->flags & MMC_RSP_CRC) cmdreg |= A10_MMC_CMDR_CHK_RESP_CRC; sc->a10_intr = 0; sc->a10_resid = 0; sc->a10_intr_wait = A10_MMC_INT_CMD_DONE; cmd->error = MMC_ERR_NONE; if (cmd->data != NULL) { sc->a10_intr_wait |= A10_MMC_INT_DATA_OVER; cmdreg |= A10_MMC_CMDR_DATA_TRANS | A10_MMC_CMDR_WAIT_PRE_OVER; if (cmd->data->flags & MMC_DATA_MULTI) { cmdreg |= A10_MMC_CMDR_STOP_CMD_FLAG; sc->a10_intr_wait |= A10_MMC_INT_AUTO_STOP_DONE; } if (cmd->data->flags & MMC_DATA_WRITE) cmdreg |= A10_MMC_CMDR_DIR_WRITE; blksz = min(cmd->data->len, MMC_SECTOR_SIZE); A10_MMC_WRITE_4(sc, A10_MMC_BKSR, blksz); A10_MMC_WRITE_4(sc, A10_MMC_BYCR, cmd->data->len); err = a10_mmc_prepare_dma(sc); if (err != 0) device_printf(sc->a10_dev, "prepare_dma failed: %d\n", err); } A10_MMC_WRITE_4(sc, A10_MMC_CAGR, cmd->arg); A10_MMC_WRITE_4(sc, A10_MMC_CMDR, cmdreg | cmd->opcode); callout_reset(&sc->a10_timeoutc, sc->a10_timeout * hz, a10_mmc_timeout, sc); A10_MMC_UNLOCK(sc); return (0); } static int a10_mmc_read_ivar(device_t bus, device_t child, int which, uintptr_t *result) { struct a10_mmc_softc *sc; sc = device_get_softc(bus); switch (which) { default: return (EINVAL); case MMCBR_IVAR_BUS_MODE: *(int *)result = sc->a10_host.ios.bus_mode; break; case MMCBR_IVAR_BUS_WIDTH: *(int *)result = sc->a10_host.ios.bus_width; break; case MMCBR_IVAR_CHIP_SELECT: *(int *)result = sc->a10_host.ios.chip_select; break; case MMCBR_IVAR_CLOCK: *(int *)result = sc->a10_host.ios.clock; break; case MMCBR_IVAR_F_MIN: *(int *)result = sc->a10_host.f_min; break; case MMCBR_IVAR_F_MAX: *(int *)result = sc->a10_host.f_max; break; case MMCBR_IVAR_HOST_OCR: *(int *)result = sc->a10_host.host_ocr; break; case MMCBR_IVAR_MODE: *(int *)result = sc->a10_host.mode; break; case MMCBR_IVAR_OCR: *(int *)result = sc->a10_host.ocr; break; case MMCBR_IVAR_POWER_MODE: *(int *)result = sc->a10_host.ios.power_mode; break; case MMCBR_IVAR_VDD: *(int *)result = sc->a10_host.ios.vdd; break; case MMCBR_IVAR_CAPS: *(int *)result = sc->a10_host.caps; break; case MMCBR_IVAR_MAX_DATA: *(int *)result = 65535; break; } return (0); } static int a10_mmc_write_ivar(device_t bus, device_t child, int which, uintptr_t value) { struct a10_mmc_softc *sc; sc = device_get_softc(bus); switch (which) { default: return (EINVAL); case MMCBR_IVAR_BUS_MODE: sc->a10_host.ios.bus_mode = value; break; case MMCBR_IVAR_BUS_WIDTH: sc->a10_host.ios.bus_width = value; break; case MMCBR_IVAR_CHIP_SELECT: sc->a10_host.ios.chip_select = value; break; case MMCBR_IVAR_CLOCK: sc->a10_host.ios.clock = value; break; case MMCBR_IVAR_MODE: sc->a10_host.mode = value; break; case MMCBR_IVAR_OCR: sc->a10_host.ocr = value; break; case MMCBR_IVAR_POWER_MODE: sc->a10_host.ios.power_mode = value; break; case MMCBR_IVAR_VDD: sc->a10_host.ios.vdd = value; break; /* These are read-only */ case MMCBR_IVAR_CAPS: case MMCBR_IVAR_HOST_OCR: case MMCBR_IVAR_F_MIN: case MMCBR_IVAR_F_MAX: case MMCBR_IVAR_MAX_DATA: return (EINVAL); } return (0); } static int a10_mmc_update_clock(struct a10_mmc_softc *sc, uint32_t clkon) { uint32_t cmdreg; int retry; uint32_t ckcr; ckcr = A10_MMC_READ_4(sc, A10_MMC_CKCR); ckcr &= ~(A10_MMC_CKCR_CCLK_ENB | A10_MMC_CKCR_CCLK_CTRL); if (clkon) ckcr |= A10_MMC_CKCR_CCLK_ENB; A10_MMC_WRITE_4(sc, A10_MMC_CKCR, ckcr); cmdreg = A10_MMC_CMDR_LOAD | A10_MMC_CMDR_PRG_CLK | A10_MMC_CMDR_WAIT_PRE_OVER; A10_MMC_WRITE_4(sc, A10_MMC_CMDR, cmdreg); retry = 0xfffff; while (--retry > 0) { if ((A10_MMC_READ_4(sc, A10_MMC_CMDR) & A10_MMC_CMDR_LOAD) == 0) { A10_MMC_WRITE_4(sc, A10_MMC_RISR, 0xffffffff); return (0); } DELAY(10); } A10_MMC_WRITE_4(sc, A10_MMC_RISR, 0xffffffff); device_printf(sc->a10_dev, "timeout updating clock\n"); return (ETIMEDOUT); } static int a10_mmc_update_ios(device_t bus, device_t child) { int error; struct a10_mmc_softc *sc; struct mmc_ios *ios; uint32_t ckcr; sc = device_get_softc(bus); ios = &sc->a10_host.ios; /* Set the bus width. */ switch (ios->bus_width) { case bus_width_1: A10_MMC_WRITE_4(sc, A10_MMC_BWDR, A10_MMC_BWDR1); break; case bus_width_4: A10_MMC_WRITE_4(sc, A10_MMC_BWDR, A10_MMC_BWDR4); break; case bus_width_8: A10_MMC_WRITE_4(sc, A10_MMC_BWDR, A10_MMC_BWDR8); break; } if (ios->clock) { /* Disable clock */ error = a10_mmc_update_clock(sc, 0); if (error != 0) return (error); /* Reset the divider. */ ckcr = A10_MMC_READ_4(sc, A10_MMC_CKCR); ckcr &= ~A10_MMC_CKCR_CCLK_DIV; A10_MMC_WRITE_4(sc, A10_MMC_CKCR, ckcr); /* Set the MMC clock. */ error = clk_set_freq(sc->a10_clk_mmc, ios->clock, CLK_SET_ROUND_DOWN); if (error != 0) { device_printf(sc->a10_dev, "failed to set frequency to %u Hz: %d\n", ios->clock, error); return (error); } /* Enable clock. */ error = a10_mmc_update_clock(sc, 1); if (error != 0) return (error); } return (0); } static int a10_mmc_get_ro(device_t bus, device_t child) { return (0); } static int a10_mmc_acquire_host(device_t bus, device_t child) { struct a10_mmc_softc *sc; int error; sc = device_get_softc(bus); A10_MMC_LOCK(sc); while (sc->a10_bus_busy) { error = msleep(sc, &sc->a10_mtx, PCATCH, "mmchw", 0); if (error != 0) { A10_MMC_UNLOCK(sc); return (error); } } sc->a10_bus_busy++; A10_MMC_UNLOCK(sc); return (0); } static int a10_mmc_release_host(device_t bus, device_t child) { struct a10_mmc_softc *sc; sc = device_get_softc(bus); A10_MMC_LOCK(sc); sc->a10_bus_busy--; wakeup(sc); A10_MMC_UNLOCK(sc); return (0); } static device_method_t a10_mmc_methods[] = { /* Device interface */ DEVMETHOD(device_probe, a10_mmc_probe), DEVMETHOD(device_attach, a10_mmc_attach), DEVMETHOD(device_detach, a10_mmc_detach), /* Bus interface */ DEVMETHOD(bus_read_ivar, a10_mmc_read_ivar), DEVMETHOD(bus_write_ivar, a10_mmc_write_ivar), /* MMC bridge interface */ DEVMETHOD(mmcbr_update_ios, a10_mmc_update_ios), DEVMETHOD(mmcbr_request, a10_mmc_request), DEVMETHOD(mmcbr_get_ro, a10_mmc_get_ro), DEVMETHOD(mmcbr_acquire_host, a10_mmc_acquire_host), DEVMETHOD(mmcbr_release_host, a10_mmc_release_host), DEVMETHOD_END }; static devclass_t a10_mmc_devclass; static driver_t a10_mmc_driver = { "a10_mmc", a10_mmc_methods, sizeof(struct a10_mmc_softc), }; DRIVER_MODULE(a10_mmc, simplebus, a10_mmc_driver, a10_mmc_devclass, NULL, NULL); MMC_DECLARE_BRIDGE(a10_mmc); Index: head/sys/arm/allwinner/clkng/aw_ccung.c =================================================================== --- head/sys/arm/allwinner/clkng/aw_ccung.c (revision 320611) +++ head/sys/arm/allwinner/clkng/aw_ccung.c (revision 320612) @@ -1,364 +1,384 @@ /*- * Copyright (c) 2017 Emmanuel Vadot * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. * * $FreeBSD$ */ /* * Allwinner Clock Control Unit */ #include __FBSDID("$FreeBSD$"); #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include +#ifdef __aarch64__ +#include "opt_soc.h" +#endif + #if defined(SOC_ALLWINNER_A31) #include #endif +#if defined(SOC_ALLWINNER_A64) +#include +#endif + #if defined(SOC_ALLWINNER_H3) #include #endif #include "clkdev_if.h" #include "hwreset_if.h" static struct resource_spec aw_ccung_spec[] = { { SYS_RES_MEMORY, 0, RF_ACTIVE }, { -1, 0 } }; #if defined(SOC_ALLWINNER_H3) #define H3_CCU 1 #endif #if defined(SOC_ALLWINNER_A31) #define A31_CCU 2 #endif +#if defined(SOC_ALLWINNER_A64) +#define A64_CCU 2 +#endif + static struct ofw_compat_data compat_data[] = { #if defined(SOC_ALLWINNER_H3) { "allwinner,sun8i-h3-ccu", H3_CCU }, #endif #if defined(SOC_ALLWINNER_A31) { "allwinner,sun6i-a31-ccu", A31_CCU }, #endif +#if defined(SOC_ALLWINNER_A64) + { "allwinner,sun50i-a64-ccu", A64_CCU }, +#endif {NULL, 0 } }; #define CCU_READ4(sc, reg) bus_read_4((sc)->res, (reg)) #define CCU_WRITE4(sc, reg, val) bus_write_4((sc)->res, (reg), (val)) static int aw_ccung_write_4(device_t dev, bus_addr_t addr, uint32_t val) { struct aw_ccung_softc *sc; sc = device_get_softc(dev); CCU_WRITE4(sc, addr, val); return (0); } static int aw_ccung_read_4(device_t dev, bus_addr_t addr, uint32_t *val) { struct aw_ccung_softc *sc; sc = device_get_softc(dev); *val = CCU_READ4(sc, addr); return (0); } static int aw_ccung_modify_4(device_t dev, bus_addr_t addr, uint32_t clr, uint32_t set) { struct aw_ccung_softc *sc; uint32_t reg; sc = device_get_softc(dev); reg = CCU_READ4(sc, addr); reg &= ~clr; reg |= set; CCU_WRITE4(sc, addr, reg); return (0); } static int aw_ccung_reset_assert(device_t dev, intptr_t id, bool reset) { struct aw_ccung_softc *sc; uint32_t val; sc = device_get_softc(dev); if (id >= sc->nresets || sc->resets[id].offset == 0) return (0); mtx_lock(&sc->mtx); val = CCU_READ4(sc, sc->resets[id].offset); if (reset) val &= ~(1 << sc->resets[id].shift); else val |= 1 << sc->resets[id].shift; CCU_WRITE4(sc, sc->resets[id].offset, val); mtx_unlock(&sc->mtx); return (0); } static int aw_ccung_reset_is_asserted(device_t dev, intptr_t id, bool *reset) { struct aw_ccung_softc *sc; uint32_t val; sc = device_get_softc(dev); if (id >= sc->nresets || sc->resets[id].offset == 0) return (0); mtx_lock(&sc->mtx); val = CCU_READ4(sc, sc->resets[id].offset); *reset = (val & (1 << sc->resets[id].shift)) != 0 ? false : true; mtx_unlock(&sc->mtx); return (0); } static void aw_ccung_device_lock(device_t dev) { struct aw_ccung_softc *sc; sc = device_get_softc(dev); mtx_lock(&sc->mtx); } static void aw_ccung_device_unlock(device_t dev) { struct aw_ccung_softc *sc; sc = device_get_softc(dev); mtx_unlock(&sc->mtx); } static int aw_ccung_probe(device_t dev) { if (!ofw_bus_status_okay(dev)) return (ENXIO); if (ofw_bus_search_compatible(dev, compat_data)->ocd_data == 0) return (ENXIO); device_set_desc(dev, "Allwinner Clock Control Unit NG"); return (BUS_PROBE_DEFAULT); } static int aw_ccung_register_gates(struct aw_ccung_softc *sc) { struct clk_gate_def def; int i; for (i = 0; i < sc->ngates; i++) { if (sc->gates[i].name == NULL) continue; memset(&def, 0, sizeof(def)); def.clkdef.id = i; def.clkdef.name = sc->gates[i].name; def.clkdef.parent_names = &sc->gates[i].parent_name; def.clkdef.parent_cnt = 1; def.offset = sc->gates[i].offset; def.shift = sc->gates[i].shift; def.mask = 1; def.on_value = 1; def.off_value = 0; clknode_gate_register(sc->clkdom, &def); } return (0); } static void aw_ccung_init_clocks(struct aw_ccung_softc *sc) { struct clknode *clknode; int i, error; for (i = 0; i < sc->n_clk_init; i++) { clknode = clknode_find_by_name(sc->clk_init[i].name); if (clknode == NULL) { device_printf(sc->dev, "Cannot find clock %s\n", sc->clk_init[i].name); continue; } if (sc->clk_init[i].parent_name != NULL) { if (bootverbose) device_printf(sc->dev, "Setting %s as parent for %s\n", sc->clk_init[i].parent_name, sc->clk_init[i].name); error = clknode_set_parent_by_name(clknode, sc->clk_init[i].parent_name); if (error != 0) { device_printf(sc->dev, "Cannot set parent to %s for %s\n", sc->clk_init[i].parent_name, sc->clk_init[i].name); continue; } } if (sc->clk_init[i].default_freq != 0) { error = clknode_set_freq(clknode, sc->clk_init[i].default_freq, 0 , 0); if (error != 0) { device_printf(sc->dev, - "Cannot set frequency for %s to %llu\n", + "Cannot set frequency for %s to %ju\n", sc->clk_init[i].name, sc->clk_init[i].default_freq); continue; } } if (sc->clk_init[i].enable) { error = clknode_enable(clknode); if (error != 0) { device_printf(sc->dev, "Cannot enable %s\n", sc->clk_init[i].name); continue; } } } } static int aw_ccung_attach(device_t dev) { struct aw_ccung_softc *sc; sc = device_get_softc(dev); sc->dev = dev; if (bus_alloc_resources(dev, aw_ccung_spec, &sc->res) != 0) { device_printf(dev, "cannot allocate resources for device\n"); return (ENXIO); } mtx_init(&sc->mtx, device_get_nameunit(dev), NULL, MTX_DEF); sc->type = ofw_bus_search_compatible(dev, compat_data)->ocd_data; sc->clkdom = clkdom_create(dev); if (sc->clkdom == NULL) panic("Cannot create clkdom\n"); switch (sc->type) { #if defined(SOC_ALLWINNER_H3) case H3_CCU: ccu_h3_register_clocks(sc); break; #endif #if defined(SOC_ALLWINNER_A31) case A31_CCU: ccu_a31_register_clocks(sc); + break; +#endif +#if defined(SOC_ALLWINNER_A64) + case A64_CCU: + ccu_a64_register_clocks(sc); break; #endif } if (sc->gates) aw_ccung_register_gates(sc); if (clkdom_finit(sc->clkdom) != 0) panic("cannot finalize clkdom initialization\n"); clkdom_xlock(sc->clkdom); aw_ccung_init_clocks(sc); clkdom_unlock(sc->clkdom); if (bootverbose) clkdom_dump(sc->clkdom); /* If we have resets, register our self as a reset provider */ if (sc->resets) hwreset_register_ofw_provider(dev); return (0); } static device_method_t aw_ccung_methods[] = { /* Device interface */ DEVMETHOD(device_probe, aw_ccung_probe), DEVMETHOD(device_attach, aw_ccung_attach), /* clkdev interface */ DEVMETHOD(clkdev_write_4, aw_ccung_write_4), DEVMETHOD(clkdev_read_4, aw_ccung_read_4), DEVMETHOD(clkdev_modify_4, aw_ccung_modify_4), DEVMETHOD(clkdev_device_lock, aw_ccung_device_lock), DEVMETHOD(clkdev_device_unlock, aw_ccung_device_unlock), /* Reset interface */ DEVMETHOD(hwreset_assert, aw_ccung_reset_assert), DEVMETHOD(hwreset_is_asserted, aw_ccung_reset_is_asserted), DEVMETHOD_END }; static driver_t aw_ccung_driver = { "aw_ccung", aw_ccung_methods, sizeof(struct aw_ccung_softc), }; static devclass_t aw_ccung_devclass; EARLY_DRIVER_MODULE(aw_ccung, simplebus, aw_ccung_driver, aw_ccung_devclass, 0, 0, BUS_PASS_BUS + BUS_PASS_ORDER_MIDDLE); MODULE_VERSION(aw_ccung, 1); Index: head/sys/arm/allwinner/clkng/ccu_a64.c =================================================================== --- head/sys/arm/allwinner/clkng/ccu_a64.c (nonexistent) +++ head/sys/arm/allwinner/clkng/ccu_a64.c (revision 320612) @@ -0,0 +1,743 @@ +/*- + * Copyright (c) 2017 Emmanuel Vadot + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * $FreeBSD$ + */ + +#include +__FBSDID("$FreeBSD$"); + +#include +#include +#include + +#include +#include +#include + +#include +#include +#include +#include +#include + +#include "ccu_a64.h" + +static struct aw_ccung_reset a64_ccu_resets[] = { + CCU_RESET(A64_RST_USB_PHY0, 0x0cc, 0) + CCU_RESET(A64_RST_USB_PHY1, 0x0cc, 1) + CCU_RESET(A64_RST_USB_HSIC, 0x0cc, 2) + + CCU_RESET(A64_RST_BUS_MIPI_DSI, 0x2c0, 1) + CCU_RESET(A64_RST_BUS_CE, 0x2c0, 5) + CCU_RESET(A64_RST_BUS_DMA, 0x2c0, 6) + CCU_RESET(A64_RST_BUS_MMC0, 0x2c0, 8) + CCU_RESET(A64_RST_BUS_MMC1, 0x2c0, 9) + CCU_RESET(A64_RST_BUS_MMC2, 0x2c0, 10) + CCU_RESET(A64_RST_BUS_NAND, 0x2c0, 13) + CCU_RESET(A64_RST_BUS_DRAM, 0x2c0, 14) + CCU_RESET(A64_RST_BUS_EMAC, 0x2c0, 17) + CCU_RESET(A64_RST_BUS_TS, 0x2c0, 18) + CCU_RESET(A64_RST_BUS_HSTIMER, 0x2c0, 19) + CCU_RESET(A64_RST_BUS_SPI0, 0x2c0, 20) + CCU_RESET(A64_RST_BUS_SPI1, 0x2c0, 21) + CCU_RESET(A64_RST_BUS_OTG, 0x2c0, 23) + CCU_RESET(A64_RST_BUS_EHCI0, 0x2c0, 24) + CCU_RESET(A64_RST_BUS_EHCI1, 0x2c0, 25) + CCU_RESET(A64_RST_BUS_OHCI0, 0x2c0, 26) + CCU_RESET(A64_RST_BUS_OHCI1, 0x2c0, 27) + + CCU_RESET(A64_RST_BUS_VE, 0x2c4, 0) + CCU_RESET(A64_RST_BUS_TCON0, 0x2c4, 3) + CCU_RESET(A64_RST_BUS_TCON1, 0x2c4, 4) + CCU_RESET(A64_RST_BUS_DEINTERLACE, 0x2c4, 5) + CCU_RESET(A64_RST_BUS_CSI, 0x2c4, 8) + CCU_RESET(A64_RST_BUS_HDMI0, 0x2c4, 10) + CCU_RESET(A64_RST_BUS_HDMI1, 0x2c4, 11) + CCU_RESET(A64_RST_BUS_DE, 0x2c4, 12) + CCU_RESET(A64_RST_BUS_GPU, 0x2c4, 20) + CCU_RESET(A64_RST_BUS_MSGBOX, 0x2c4, 21) + CCU_RESET(A64_RST_BUS_SPINLOCK, 0x2c4, 22) + CCU_RESET(A64_RST_BUS_DBG, 0x2c4, 31) + + CCU_RESET(A64_RST_BUS_LVDS, 0x2C8, 31) + + CCU_RESET(A64_RST_BUS_CODEC, 0x2D0, 0) + CCU_RESET(A64_RST_BUS_SPDIF, 0x2D0, 1) + CCU_RESET(A64_RST_BUS_THS, 0x2D0, 8) + CCU_RESET(A64_RST_BUS_I2S0, 0x2D0, 12) + CCU_RESET(A64_RST_BUS_I2S1, 0x2D0, 13) + CCU_RESET(A64_RST_BUS_I2S2, 0x2D0, 14) + + CCU_RESET(A64_RST_BUS_I2C0, 0x2D8, 0) + CCU_RESET(A64_RST_BUS_I2C1, 0x2D8, 1) + CCU_RESET(A64_RST_BUS_I2C2, 0x2D8, 2) + CCU_RESET(A64_RST_BUS_SCR, 0x2D8, 5) + CCU_RESET(A64_RST_BUS_UART0, 0x2D8, 16) + CCU_RESET(A64_RST_BUS_UART1, 0x2D8, 17) + CCU_RESET(A64_RST_BUS_UART2, 0x2D8, 18) + CCU_RESET(A64_RST_BUS_UART3, 0x2D8, 19) + CCU_RESET(A64_RST_BUS_UART4, 0x2D8, 20) +}; + +static struct aw_ccung_gate a64_ccu_gates[] = { + CCU_GATE(A64_CLK_BUS_MIPI_DSI, "bus-mipi-dsi", "ahb1", 0x60, 1) + CCU_GATE(A64_CLK_BUS_CE, "bus-ce", "ahb1", 0x60, 5) + CCU_GATE(A64_CLK_BUS_DMA, "bus-dma", "ahb1", 0x60, 6) + CCU_GATE(A64_CLK_BUS_MMC0, "bus-mmc0", "ahb1", 0x60, 8) + CCU_GATE(A64_CLK_BUS_MMC1, "bus-mmc1", "ahb1", 0x60, 9) + CCU_GATE(A64_CLK_BUS_MMC2, "bus-mmc2", "ahb1", 0x60, 10) + CCU_GATE(A64_CLK_BUS_NAND, "bus-nand", "ahb1", 0x60, 13) + CCU_GATE(A64_CLK_BUS_DRAM, "bus-dram", "ahb1", 0x60, 14) + CCU_GATE(A64_CLK_BUS_EMAC, "bus-emac", "ahb2", 0x60, 16) + CCU_GATE(A64_CLK_BUS_TS, "bus-ts", "ahb1", 0x60, 18) + CCU_GATE(A64_CLK_BUS_HSTIMER, "bus-hstimer", "ahb1", 0x60, 19) + CCU_GATE(A64_CLK_BUS_SPI0, "bus-spi0", "ahb1", 0x60, 20) + CCU_GATE(A64_CLK_BUS_SPI1, "bus-spi1", "ahb1", 0x60, 21) + CCU_GATE(A64_CLK_BUS_OTG, "bus-otg", "ahb1", 0x60, 23) + CCU_GATE(A64_CLK_BUS_EHCI0, "bus-ehci0", "ahb1", 0x60, 24) + CCU_GATE(A64_CLK_BUS_EHCI1, "bus-ehci1", "ahb2", 0x60, 25) + CCU_GATE(A64_CLK_BUS_OHCI0, "bus-ohci0", "ahb1", 0x60, 26) + CCU_GATE(A64_CLK_BUS_OHCI1, "bus-ohci1", "ahb2", 0x60, 27) + + CCU_GATE(A64_CLK_BUS_VE, "bus-ve", "ahb1", 0x64, 0) + CCU_GATE(A64_CLK_BUS_TCON0, "bus-tcon0", "ahb1", 0x64, 3) + CCU_GATE(A64_CLK_BUS_TCON1, "bus-tcon1", "ahb1", 0x64, 4) + CCU_GATE(A64_CLK_BUS_DEINTERLACE, "bus-deinterlace", "ahb1", 0x64, 5) + CCU_GATE(A64_CLK_BUS_CSI, "bus-csi", "ahb1", 0x64, 8) + CCU_GATE(A64_CLK_BUS_HDMI, "bus-hdmi", "ahb1", 0x64, 11) + CCU_GATE(A64_CLK_BUS_DE, "bus-de", "ahb1", 0x64, 12) + CCU_GATE(A64_CLK_BUS_GPU, "bus-gpu", "ahb1", 0x64, 20) + CCU_GATE(A64_CLK_BUS_MSGBOX, "bus-msgbox", "ahb1", 0x64, 21) + CCU_GATE(A64_CLK_BUS_SPINLOCK, "bus-spinlock", "ahb1", 0x64, 22) + + CCU_GATE(A64_CLK_BUS_CODEC, "bus-codec", "apb1", 0x68, 0) + CCU_GATE(A64_CLK_BUS_SPDIF, "bus-spdif", "apb1", 0x68, 1) + CCU_GATE(A64_CLK_BUS_PIO, "bus-pio", "apb1", 0x68, 5) + CCU_GATE(A64_CLK_BUS_THS, "bus-ths", "apb1", 0x68, 8) + CCU_GATE(A64_CLK_BUS_I2S0, "bus-i2s0", "apb1", 0x68, 12) + CCU_GATE(A64_CLK_BUS_I2S1, "bus-i2s1", "apb1", 0x68, 13) + CCU_GATE(A64_CLK_BUS_I2S2, "bus-i2s2", "apb1", 0x68, 14) + + CCU_GATE(A64_CLK_BUS_I2C0, "bus-i2c0", "apb2", 0x6C, 0) + CCU_GATE(A64_CLK_BUS_I2C1, "bus-i2c1", "apb2", 0x6C, 1) + CCU_GATE(A64_CLK_BUS_I2C2, "bus-i2c2", "apb2", 0x6C, 2) + CCU_GATE(A64_CLK_BUS_SCR, "bus-src", "apb2", 0x6C, 5) + CCU_GATE(A64_CLK_BUS_UART0, "bus-uart0", "apb2", 0x6C, 16) + CCU_GATE(A64_CLK_BUS_UART1, "bus-uart1", "apb2", 0x6C, 17) + CCU_GATE(A64_CLK_BUS_UART2, "bus-uart2", "apb2", 0x6C, 18) + CCU_GATE(A64_CLK_BUS_UART3, "bus-uart3", "apb2", 0x6C, 19) + CCU_GATE(A64_CLK_BUS_UART4, "bus-uart4", "apb2", 0x6C, 20) + + CCU_GATE(A64_CLK_BUS_DBG, "bus-dbg", "ahb1", 0x70, 7) + + CCU_GATE(A64_CLK_USB_PHY0, "usb-phy0", "osc24M", 0xcc, 8) + CCU_GATE(A64_CLK_USB_PHY1, "usb-phy1", "osc24M", 0xcc, 9) + CCU_GATE(A64_CLK_USB_HSIC, "usb-hsic", "pll_hsic", 0xcc, 10) + CCU_GATE(A64_CLK_USB_HSIC_12M, "usb-hsic-12M", "osc12M", 0xcc, 11) + CCU_GATE(A64_CLK_USB_OHCI0, "usb-ohci0", "osc12M", 0xcc, 16) + CCU_GATE(A64_CLK_USB_OHCI1, "usb-ohci1", "usb-ohci0", 0xcc, 17) + + CCU_GATE(A64_CLK_DRAM_VE, "dram-ve", "dram", 0x100, 0) + CCU_GATE(A64_CLK_DRAM_CSI, "dram-csi", "dram", 0x100, 1) + CCU_GATE(A64_CLK_DRAM_DEINTERLACE, "dram-deinterlace", "dram", 0x100, 2) + CCU_GATE(A64_CLK_DRAM_TS, "dram-ts", "dram", 0x100, 3) + + CCU_GATE(A64_CLK_CSI_MISC, "csi-misc", "osc24M", 0x130, 31) + + CCU_GATE(A64_CLK_AC_DIG_4X, "ac-dig-4x", "pll_audio-4x", 0x140, 30) + CCU_GATE(A64_CLK_AC_DIG, "ac-dig", "pll_audio", 0x140, 31) + + CCU_GATE(A64_CLK_AVS, "avs", "osc24M", 0x144, 31) + + CCU_GATE(A64_CLK_HDMI_DDC, "hdmi-ddc", "osc24M", 0x154, 31) +}; + +static const char *osc12m_parents[] = {"osc24M"}; +FIXED_CLK(osc12m_clk, + A64_CLK_OSC_12M, /* id */ + "osc12M", /* name */ + osc12m_parents, /* parent */ + 0, /* freq */ + 1, /* mult */ + 2, /* div */ + 0); /* flags */ + +static const char *pll_cpux_parents[] = {"osc24M"}; +NKMP_CLK(pll_cpux_clk, + A64_CLK_PLL_CPUX, /* id */ + "pll_cpux", pll_cpux_parents, /* name, parents */ + 0x00, /* offset */ + 8, 5, 0, 0, /* n factor */ + 4, 2, 0, 0, /* k factor */ + 0, 2, 0, 0, /* m factor */ + 16, 2, 0, AW_CLK_FACTOR_POWER_OF_TWO, /* p factor */ + 31, /* gate */ + 28, 1000, /* lock */ + AW_CLK_HAS_GATE | AW_CLK_HAS_LOCK | AW_CLK_SCALE_CHANGE); /* flags */ + +static const char *pll_audio_parents[] = {"osc24M"}; +NKMP_CLK(pll_audio_clk, + A64_CLK_PLL_AUDIO, /* id */ + "pll_audio", pll_audio_parents, /* name, parents */ + 0x08, /* offset */ + 8, 7, 0, 0, /* n factor */ + 0, 0, 1, AW_CLK_FACTOR_FIXED, /* k factor (fake) */ + 0, 5, 0, 0, /* m factor */ + 16, 4, 0, 0, /* p factor */ + 31, /* gate */ + 28, 1000, /* lock */ + AW_CLK_HAS_GATE | AW_CLK_HAS_LOCK); /* flags */ + +static const char *pll_audio_mult_parents[] = {"pll_audio"}; +FIXED_CLK(pll_audio_2x_clk, + A64_CLK_PLL_AUDIO_2X, /* id */ + "pll_audio-2x", /* name */ + pll_audio_mult_parents, /* parent */ + 0, /* freq */ + 2, /* mult */ + 1, /* div */ + 0); /* flags */ +FIXED_CLK(pll_audio_4x_clk, + A64_CLK_PLL_AUDIO_4X, /* id */ + "pll_audio-4x", /* name */ + pll_audio_mult_parents, /* parent */ + 0, /* freq */ + 4, /* mult */ + 1, /* div */ + 0); /* flags */ +FIXED_CLK(pll_audio_8x_clk, + A64_CLK_PLL_AUDIO_8X, /* id */ + "pll_audio-8x", /* name */ + pll_audio_mult_parents, /* parent */ + 0, /* freq */ + 8, /* mult */ + 1, /* div */ + 0); /* flags */ + +static const char *pll_video0_parents[] = {"osc24M"}; +NM_CLK_WITH_FRAC(pll_video0_clk, + A64_CLK_PLL_VIDEO0, /* id */ + "pll_video0", pll_video0_parents, /* name, parents */ + 0x10, /* offset */ + 8, 7, 0, 0, /* n factor */ + 0, 4, 0, 0, /* m factor */ + 31, 28, 1000, /* gate, lock, lock retries */ + AW_CLK_HAS_LOCK, /* flags */ + 270000000, 297000000, /* freq0, freq1 */ + 24, 25); /* mode sel, freq sel */ + +static const char *pll_ve_parents[] = {"osc24M"}; +NM_CLK_WITH_FRAC(pll_ve_clk, + A64_CLK_PLL_VE, /* id */ + "pll_ve", pll_ve_parents, /* name, parents */ + 0x18, /* offset */ + 8, 7, 0, 0, /* n factor */ + 0, 4, 0, 0, /* m factor */ + 31, 28, 1000, /* gate, lock, lock retries */ + AW_CLK_HAS_LOCK, /* flags */ + 270000000, 297000000, /* freq0, freq1 */ + 24, 25); /* mode sel, freq sel */ + +static const char *pll_ddr0_parents[] = {"osc24M"}; +NKMP_CLK_WITH_UPDATE(pll_ddr0_clk, + A64_CLK_PLL_DDR0, /* id */ + "pll_ddr0", pll_ddr0_parents, /* name, parents */ + 0x20, /* offset */ + 8, 5, 0, 0, /* n factor */ + 4, 2, 0, 0, /* k factor */ + 0, 2, 0, 0, /* m factor */ + 0, 0, 1, AW_CLK_FACTOR_FIXED, /* p factor (fake) */ + 31, /* gate */ + 28, 1000, /* lock */ + 20, /* update */ + AW_CLK_HAS_GATE | AW_CLK_HAS_LOCK); /* flags */ + +static const char *pll_periph0_2x_parents[] = {"osc24M"}; +static const char *pll_periph0_parents[] = {"pll_periph0_2x"}; +NKMP_CLK(pll_periph0_2x_clk, + A64_CLK_PLL_PERIPH0_2X, /* id */ + "pll_periph0_2x", pll_periph0_2x_parents, /* name, parents */ + 0x28, /* offset */ + 8, 5, 0, 0, /* n factor */ + 4, 2, 0, 0, /* k factor */ + 0, 0, 2, AW_CLK_FACTOR_FIXED, /* m factor (fake) */ + 0, 0, 1, AW_CLK_FACTOR_FIXED, /* p factor (fake) */ + 31, /* gate */ + 28, 1000, /* lock */ + AW_CLK_HAS_GATE | AW_CLK_HAS_LOCK); /* flags */ +FIXED_CLK(pll_periph0_clk, + A64_CLK_PLL_PERIPH0, /* id */ + "pll_periph0", /* name */ + pll_periph0_parents, /* parent */ + 0, /* freq */ + 1, /* mult */ + 2, /* div */ + 0); /* flags */ + +static const char *pll_periph1_2x_parents[] = {"osc24M"}; +static const char *pll_periph1_parents[] = {"pll_periph1_2x"}; +NKMP_CLK(pll_periph1_2x_clk, + A64_CLK_PLL_PERIPH1_2X, /* id */ + "pll_periph1_2x", pll_periph1_2x_parents, /* name, parents */ + 0x2C, /* offset */ + 8, 5, 0, 0, /* n factor */ + 4, 2, 0, 0, /* k factor */ + 0, 0, 2, AW_CLK_FACTOR_FIXED, /* m factor (fake) */ + 0, 0, 1, AW_CLK_FACTOR_FIXED, /* p factor (fake) */ + 31, /* gate */ + 28, 1000, /* lock */ + AW_CLK_HAS_GATE | AW_CLK_HAS_LOCK); /* flags */ +FIXED_CLK(pll_periph1_clk, + A64_CLK_PLL_PERIPH1, /* id */ + "pll_periph1", /* name */ + pll_periph1_parents, /* parent */ + 0, /* freq */ + 1, /* mult */ + 2, /* div */ + 0); /* flags */ + +static const char *pll_video1_parents[] = {"osc24M"}; +NM_CLK_WITH_FRAC(pll_video1_clk, + A64_CLK_PLL_VIDEO1, /* id */ + "pll_video1", pll_video1_parents, /* name, parents */ + 0x30, /* offset */ + 8, 7, 0, 0, /* n factor */ + 0, 4, 0, 0, /* m factor */ + 31, 28, 1000, /* gate, lock, lock retries */ + AW_CLK_HAS_LOCK, /* flags */ + 270000000, 297000000, /* freq0, freq1 */ + 24, 25); /* mode sel, freq sel */ + +static const char *pll_gpu_parents[] = {"osc24M"}; +NM_CLK_WITH_FRAC(pll_gpu_clk, + A64_CLK_PLL_GPU, /* id */ + "pll_gpu", pll_gpu_parents, /* name, parents */ + 0x38, /* offset */ + 8, 7, 0, 0, /* n factor */ + 0, 4, 0, 0, /* m factor */ + 31, 28, 1000, /* gate, lock, lock retries */ + AW_CLK_HAS_LOCK, /* flags */ + 270000000, 297000000, /* freq0, freq1 */ + 24, 25); /* mode sel, freq sel */ + +/* PLL MIPI is missing */ + +static const char *pll_hsic_parents[] = {"osc24M"}; +NM_CLK_WITH_FRAC(pll_hsic_clk, + A64_CLK_PLL_HSIC, /* id */ + "pll_hsic", pll_hsic_parents, /* name, parents */ + 0x44, /* offset */ + 8, 7, 0, 0, /* n factor */ + 0, 4, 0, 0, /* m factor */ + 31, 28, 1000, /* gate, lock, lock retries */ + AW_CLK_HAS_LOCK, /* flags */ + 270000000, 297000000, /* freq0, freq1 */ + 24, 25); /* mode sel, freq sel */ + +static const char *pll_de_parents[] = {"osc24M"}; +NM_CLK_WITH_FRAC(pll_de_clk, + A64_CLK_PLL_DE, /* id */ + "pll_de", pll_de_parents, /* name, parents */ + 0x48, /* offset */ + 8, 7, 0, 0, /* n factor */ + 0, 4, 0, 0, /* m factor */ + 31, 28, 1000, /* gate, lock, lock retries */ + AW_CLK_HAS_LOCK, /* flags */ + 270000000, 297000000, /* freq0, freq1 */ + 24, 25); /* mode sel, freq sel */ + +static const char *pll_ddr1_parents[] = {"osc24M"}; +NKMP_CLK_WITH_UPDATE(pll_ddr1_clk, + A64_CLK_PLL_DDR1, /* id */ + "pll_ddr1", pll_ddr1_parents, /* name, parents */ + 0x4C, /* offset */ + 8, 7, 0, 0, /* n factor */ + 0, 0, 1, AW_CLK_FACTOR_FIXED, /* k factor (fake) */ + 0, 2, 0, 0, /* m factor */ + 0, 0, 1, AW_CLK_FACTOR_FIXED, /* p factor (fake) */ + 31, /* gate */ + 28, 1000, /* lock */ + 20, /* update */ + AW_CLK_HAS_GATE | AW_CLK_HAS_LOCK); /* flags */ + +static const char *cpux_parents[] = {"osc32k", "osc24M", "pll_cpux"}; +MUX_CLK(cpux_clk, + A64_CLK_CPUX, /* id */ + "cpux", cpux_parents, /* name, parents */ + 0x50, 16, 2); /* offset, shift, width */ + +static const char *axi_parents[] = {"cpux"}; +DIV_CLK(axi_clk, + A64_CLK_AXI, /* id */ + "axi", axi_parents, /* name, parents */ + 0x50, /* offset */ + 0, 2, /* shift, width */ + 0, NULL); /* flags, div table */ + +static const char *apb_parents[] = {"cpux"}; +DIV_CLK(apb_clk, + A64_CLK_APB, /* id */ + "apb", apb_parents, /* name, parents */ + 0x50, /* offset */ + 8, 2, /* shift, width */ + 0, NULL); /* flags, div table */ + +static const char *ahb1_parents[] = {"osc32k", "osc24M", "axi", "pll_periph0"}; +PREDIV_CLK(ahb1_clk, A64_CLK_AHB1, /* id */ + "ahb1", ahb1_parents, /* name, parents */ + 0x54, /* offset */ + 12, 2, /* mux */ + 4, 2, 0, AW_CLK_FACTOR_POWER_OF_TWO, /* div */ + 6, 2, 0, AW_CLK_FACTOR_HAS_COND, /* prediv */ + 12, 2, 3); /* prediv condition */ + +static const char *apb1_parents[] = {"ahb1"}; +static struct clk_div_table apb1_div_table[] = { + { .value = 0, .divider = 2, }, + { .value = 1, .divider = 2, }, + { .value = 2, .divider = 4, }, + { .value = 3, .divider = 8, }, + { }, +}; +DIV_CLK(apb1_clk, + A64_CLK_APB1, /* id */ + "apb1", apb1_parents, /* name, parents */ + 0x54, /* offset */ + 8, 2, /* shift, width */ + CLK_DIV_WITH_TABLE, /* flags */ + apb1_div_table); /* div table */ + +static const char *apb2_parents[] = {"osc32k", "osc24M", "pll_periph0_2x", "pll_periph0_2x"}; +NM_CLK(apb2_clk, + A64_CLK_APB2, /* id */ + "apb2", apb2_parents, /* name, parents */ + 0x58, /* offset */ + 16, 2, 0, AW_CLK_FACTOR_POWER_OF_TWO, /* n factor */ + 0, 5, 0, 0, /* m factor */ + 24, 2, /* mux */ + 0, /* gate */ + AW_CLK_HAS_MUX); + +static const char *ahb2_parents[] = {"ahb1", "pll_periph0"}; +PREDIV_CLK(ahb2_clk, A64_CLK_AHB2, /* id */ + "ahb2", ahb2_parents, /* name, parents */ + 0x5c, /* offset */ + 0, 2, /* mux */ + 0, 0, 1, AW_CLK_FACTOR_FIXED, /* div */ + 0, 0, 2, AW_CLK_FACTOR_HAS_COND | AW_CLK_FACTOR_FIXED, /* prediv */ + 0, 2, 1); /* prediv condition */ + +static const char *mod_parents[] = {"osc24M", "pll_periph0_2x", "pll_periph1_2x"}; +NM_CLK(nand_clk, + A64_CLK_NAND, "nand", mod_parents, /* id, name, parents */ + 0x80, /* offset */ + 16, 2, 0, AW_CLK_FACTOR_POWER_OF_TWO, /* n factor */ + 0, 4, 0, 0, /* m factor */ + 24, 2, /* mux */ + 31, /* gate */ + AW_CLK_HAS_GATE | AW_CLK_HAS_MUX); /* flags */ + +NM_CLK(mmc0_clk, + A64_CLK_MMC0, "mmc0", mod_parents, /* id, name, parents */ + 0x88, /* offset */ + 16, 2, 0, AW_CLK_FACTOR_POWER_OF_TWO, /* n factor */ + 0, 4, 0, 0, /* m factor */ + 24, 2, /* mux */ + 31, /* gate */ + AW_CLK_HAS_GATE | AW_CLK_HAS_MUX | + AW_CLK_REPARENT); /* flags */ + +NM_CLK(mmc1_clk, + A64_CLK_MMC1, "mmc1", mod_parents, /* id, name, parents */ + 0x8c, /* offset */ + 16, 2, 0, AW_CLK_FACTOR_POWER_OF_TWO, /* n factor */ + 0, 4, 0, 0, /* m factor */ + 24, 2, /* mux */ + 31, /* gate */ + AW_CLK_HAS_GATE | AW_CLK_HAS_MUX | + AW_CLK_REPARENT); /* flags */ + +NM_CLK(mmc2_clk, + A64_CLK_MMC2, "mmc2", mod_parents, /* id, name, parents */ + 0x90, /* offset */ + 16, 2, 0, AW_CLK_FACTOR_POWER_OF_TWO, /* n factor */ + 0, 4, 0, 0, /* m factor */ + 24, 2, /* mux */ + 31, /* gate */ + AW_CLK_HAS_GATE | AW_CLK_HAS_MUX | + AW_CLK_REPARENT); /* flags */ + +static const char *ts_parents[] = {"osc24M", "pll_periph0"}; +NM_CLK(ts_clk, + A64_CLK_TS, "ts", ts_parents, /* id, name, parents */ + 0x98, /* offset */ + 16, 2, 0, AW_CLK_FACTOR_POWER_OF_TWO, /* n factor */ + 0, 4, 0, 0, /* m factor */ + 24, 2, /* mux */ + 31, /* gate */ + AW_CLK_HAS_GATE | AW_CLK_HAS_MUX); /* flags */ + +NM_CLK(ce_clk, + A64_CLK_CE, "ce", mod_parents, /* id, name, parents */ + 0x9C, /* offset */ + 16, 2, 0, AW_CLK_FACTOR_POWER_OF_TWO, /* n factor */ + 0, 4, 0, 0, /* m factor */ + 24, 2, /* mux */ + 31, /* gate */ + AW_CLK_HAS_GATE | AW_CLK_HAS_MUX); /* flags */ + +NM_CLK(spi0_clk, + A64_CLK_SPI0, "spi0", mod_parents, /* id, name, parents */ + 0xA0, /* offset */ + 16, 2, 0, AW_CLK_FACTOR_POWER_OF_TWO, /* n factor */ + 0, 4, 0, 0, /* m factor */ + 24, 2, /* mux */ + 31, /* gate */ + AW_CLK_HAS_GATE | AW_CLK_HAS_MUX | + AW_CLK_REPARENT); /* flags */ + +NM_CLK(spi1_clk, + A64_CLK_SPI1, "spi1", mod_parents, /* id, name, parents */ + 0xA4, /* offset */ + 16, 2, 0, AW_CLK_FACTOR_POWER_OF_TWO, /* n factor */ + 0, 4, 0, 0, /* m factor */ + 24, 2, /* mux */ + 31, /* gate */ + AW_CLK_HAS_GATE | AW_CLK_HAS_MUX | + AW_CLK_REPARENT); /* flags */ + +static const char *i2s_parents[] = {"pll_audio-8x", "pll_audio-4x", "pll_audio-2x", "pll_audio"}; +MUX_CLK(i2s0mux_clk, + 0, "i2s0mux", i2s_parents, /* id, name, parents */ + 0xb0, 16, 2); /* offset, mux shift, mux width */ +MUX_CLK(i2s1mux_clk, + 0, "i2s1mux", i2s_parents, /* id, name, parents */ + 0xb4, 16, 2); /* offset, mux shift, mux width */ +MUX_CLK(i2s2mux_clk, + 0, "i2s2mux", i2s_parents, /* id, name, parents */ + 0xb8, 16, 2); /* offset, mux shift, mux width */ + +static const char *spdif_parents[] = {"pll_audio"}; +NM_CLK(spdif_clk, + A64_CLK_SPDIF, "spdif", spdif_parents, /* id, name, parents */ + 0xC0, /* offset */ + 0, 0, 1, AW_CLK_FACTOR_FIXED, /* n factor (fake); */ + 0, 4, 0, 0, /* m factor */ + 0, 0, /* mux */ + 31, /* gate */ + AW_CLK_HAS_GATE); /* flags */ + +/* USBPHY clk sel */ + +/* DRAM needs update bit */ +static const char *dram_parents[] = {"pll_ddr0", "pll_ddr1"}; +NM_CLK(dram_clk, + A64_CLK_DRAM, "dram", dram_parents, /* id, name, parents */ + 0xF4, /* offset */ + 0, 0, 1, AW_CLK_FACTOR_FIXED, /* n factor (fake) */ + 0, 2, 0, 0, /* m factor */ + 20, 2, /* mux */ + 0, /* gate */ + AW_CLK_HAS_MUX); /* flags */ + +static const char *de_parents[] = {"pll_periph0_2x", "pll_de"}; +NM_CLK(de_clk, + A64_CLK_DE, "de", de_parents, /* id, name, parents */ + 0x104, /* offset */ + 0, 0, 1, AW_CLK_FACTOR_FIXED, /* n factor (fake) */ + 0, 4, 0, 0, /* m factor */ + 24, 2, /* mux */ + 31, /* gate */ + AW_CLK_HAS_MUX | AW_CLK_HAS_GATE); /* flags */ + +/* TCON0/1 Needs mux table */ + +static const char *deinterlace_parents[] = {"pll_periph0", "pll_periph1"}; +NM_CLK(deinterlace_clk, + A64_CLK_DEINTERLACE, "deinterlace", deinterlace_parents, /* id, name, parents */ + 0x124, /* offset */ + 0, 0, 1, AW_CLK_FACTOR_FIXED, /* n factor (fake) */ + 0, 4, 0, 0, /* m factor */ + 24, 2, /* mux */ + 31, /* gate */ + AW_CLK_HAS_MUX | AW_CLK_HAS_GATE); /* flags */ + +static const char *csi_sclk_parents[] = {"pll_periph0", "pll_periph1"}; +NM_CLK(csi_sclk_clk, + A64_CLK_CSI_SCLK, "csi-sclk", csi_sclk_parents, /* id, name, parents */ + 0x134, /* offset */ + 0, 0, 1, AW_CLK_FACTOR_FIXED, /* n factor (fake) */ + 16, 4, 0, 0, /* m factor */ + 24, 2, /* mux */ + 31, /* gate */ + AW_CLK_HAS_MUX | AW_CLK_HAS_GATE); /* flags */ + +static const char *csi_mclk_parents[] = {"osc24M", "pll_video0", "pll_periph1"}; +NM_CLK(csi_mclk_clk, + A64_CLK_CSI_MCLK, "csi-mclk", csi_mclk_parents, /* id, name, parents */ + 0x134, /* offset */ + 0, 0, 1, AW_CLK_FACTOR_FIXED, /* n factor (fake) */ + 0, 4, 0, 0, /* m factor */ + 8, 2, /* mux */ + 15, /* gate */ + AW_CLK_HAS_MUX | AW_CLK_HAS_GATE); /* flags */ + +static const char *ve_parents[] = {"pll_ve"}; +NM_CLK(ve_clk, + A64_CLK_VE, "ve", ve_parents, /* id, name, parents */ + 0x13C, /* offset */ + 16, 3, 0, 0, /* n factor */ + 0, 0, 1, AW_CLK_FACTOR_FIXED, /* m factor (fake) */ + 0, 0, /* mux */ + 31, /* gate */ + AW_CLK_HAS_GATE); /* flags */ + +static const char *hdmi_parents[] = {"pll_video0"}; +NM_CLK(hdmi_clk, + A64_CLK_HDMI, "hdmi", hdmi_parents, /* id, name, parents */ + 0x150, /* offset */ + 0, 0, 1, AW_CLK_FACTOR_FIXED, /* n factor (fake) */ + 0, 4, 0, 0, /* m factor */ + 24, 2, /* mux */ + 31, /* gate */ + AW_CLK_HAS_MUX | AW_CLK_HAS_GATE); /* flags */ + +static const char *mbus_parents[] = {"osc24M", "pll_periph0_2x", "pll_ddr0"}; +NM_CLK(mbus_clk, + A64_CLK_MBUS, "mbus", mbus_parents, /* id, name, parents */ + 0x15C, /* offset */ + 0, 0, 1, AW_CLK_FACTOR_FIXED, /* n factor (fake) */ + 0, 3, 0, 0, /* m factor */ + 24, 2, /* mux */ + 31, /* gate */ + AW_CLK_HAS_MUX | AW_CLK_HAS_GATE); /* flags */ + +static const char *gpu_parents[] = {"pll_gpu"}; +NM_CLK(gpu_clk, + A64_CLK_GPU, "gpu", gpu_parents, /* id, name, parents */ + 0x1A0, /* offset */ + 0, 2, 0, 0, /* n factor */ + 0, 0, 1, AW_CLK_FACTOR_FIXED, /* m factor (fake) */ + 0, 0, /* mux */ + 31, /* gate */ + AW_CLK_HAS_GATE); /* flags */ + +static struct aw_clk_nkmp_def *nkmp_clks[] = { + &pll_cpux_clk, + &pll_audio_clk, + &pll_periph0_2x_clk, + &pll_periph1_2x_clk, + &pll_ddr0_clk, + &pll_ddr1_clk, +}; + +static struct aw_clk_nm_def *nm_clks[] = { + &pll_video0_clk, + &pll_video1_clk, + &pll_ve_clk, + &pll_gpu_clk, + &pll_de_clk, + &pll_hsic_clk, + &apb2_clk, + &nand_clk, + &mmc0_clk, + &mmc1_clk, + &mmc2_clk, + &ts_clk, + &ce_clk, + &spi0_clk, + &spi1_clk, + &spdif_clk, + &dram_clk, + &de_clk, + &deinterlace_clk, + &csi_sclk_clk, + &csi_mclk_clk, + &ve_clk, + &hdmi_clk, + &mbus_clk, + &gpu_clk, +}; + +static struct aw_clk_prediv_mux_def *prediv_mux_clks[] = { + &ahb1_clk, + &ahb2_clk, +}; + +static struct clk_mux_def *mux_clks[] = { + &cpux_clk, + &i2s0mux_clk, + &i2s1mux_clk, + &i2s2mux_clk, +}; + +static struct clk_div_def *div_clks[] = { + &axi_clk, + &apb1_clk, + &apb_clk, +}; + +static struct clk_fixed_def *fixed_factor_clks[] = { + &osc12m_clk, + &pll_periph0_clk, + &pll_periph1_clk, + &pll_audio_2x_clk, + &pll_audio_4x_clk, + &pll_audio_8x_clk, +}; + +static struct aw_clk_init init_clks[] = { + {"ahb1", "pll_periph0", 0, false}, + {"ahb2", "pll_periph0", 0, false}, + {"dram", "pll_ddr", 0, false}, +}; + +void +ccu_a64_register_clocks(struct aw_ccung_softc *sc) +{ + int i; + + sc->resets = a64_ccu_resets; + sc->nresets = nitems(a64_ccu_resets); + sc->gates = a64_ccu_gates; + sc->ngates = nitems(a64_ccu_gates); + sc->clk_init = init_clks; + sc->n_clk_init = nitems(init_clks); + + for (i = 0; i < nitems(nkmp_clks); i++) + aw_clk_nkmp_register(sc->clkdom, nkmp_clks[i]); + for (i = 0; i < nitems(nm_clks); i++) + aw_clk_nm_register(sc->clkdom, nm_clks[i]); + for (i = 0; i < nitems(prediv_mux_clks); i++) + aw_clk_prediv_mux_register(sc->clkdom, prediv_mux_clks[i]); + + for (i = 0; i < nitems(mux_clks); i++) + clknode_mux_register(sc->clkdom, mux_clks[i]); + for (i = 0; i < nitems(div_clks); i++) + clknode_div_register(sc->clkdom, div_clks[i]); + for (i = 0; i < nitems(fixed_factor_clks); i++) + clknode_fixed_register(sc->clkdom, fixed_factor_clks[i]); +} Property changes on: head/sys/arm/allwinner/clkng/ccu_a64.c ___________________________________________________________________ Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:keywords ## -0,0 +1 ## +FreeBSD=%H \ No newline at end of property Added: svn:mime-type ## -0,0 +1 ## +text/plain \ No newline at end of property Index: head/sys/arm/allwinner/clkng/ccu_a64.h =================================================================== --- head/sys/arm/allwinner/clkng/ccu_a64.h (nonexistent) +++ head/sys/arm/allwinner/clkng/ccu_a64.h (revision 320612) @@ -0,0 +1,204 @@ +/*- + * Copyright (c) 2017 Emmanuel Vadot + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * $FreeBSD$ + */ + +#ifndef __CCU_A64_H__ +#define __CCU_A64_H__ + +#define A64_RST_USB_PHY0 0 +#define A64_RST_USB_PHY1 1 +#define A64_RST_USB_HSIC 2 +#define A64_RST_DRAM 3 +#define A64_RST_MBUS 4 +#define A64_RST_BUS_MIPI_DSI 5 +#define A64_RST_BUS_CE 6 +#define A64_RST_BUS_DMA 7 +#define A64_RST_BUS_MMC0 8 +#define A64_RST_BUS_MMC1 9 +#define A64_RST_BUS_MMC2 10 +#define A64_RST_BUS_NAND 11 +#define A64_RST_BUS_DRAM 12 +#define A64_RST_BUS_EMAC 13 +#define A64_RST_BUS_TS 14 +#define A64_RST_BUS_HSTIMER 15 +#define A64_RST_BUS_SPI0 16 +#define A64_RST_BUS_SPI1 17 +#define A64_RST_BUS_OTG 18 +#define A64_RST_BUS_EHCI0 19 +#define A64_RST_BUS_EHCI1 20 +#define A64_RST_BUS_OHCI0 21 +#define A64_RST_BUS_OHCI1 22 +#define A64_RST_BUS_VE 23 +#define A64_RST_BUS_TCON0 24 +#define A64_RST_BUS_TCON1 25 +#define A64_RST_BUS_DEINTERLACE 26 +#define A64_RST_BUS_CSI 27 +#define A64_RST_BUS_HDMI0 28 +#define A64_RST_BUS_HDMI1 29 +#define A64_RST_BUS_DE 30 +#define A64_RST_BUS_GPU 31 +#define A64_RST_BUS_MSGBOX 32 +#define A64_RST_BUS_SPINLOCK 33 +#define A64_RST_BUS_DBG 34 +#define A64_RST_BUS_LVDS 35 +#define A64_RST_BUS_CODEC 36 +#define A64_RST_BUS_SPDIF 37 +#define A64_RST_BUS_THS 38 +#define A64_RST_BUS_I2S0 39 +#define A64_RST_BUS_I2S1 40 +#define A64_RST_BUS_I2S2 41 +#define A64_RST_BUS_I2C0 42 +#define A64_RST_BUS_I2C1 43 +#define A64_RST_BUS_I2C2 44 +#define A64_RST_BUS_SCR 45 +#define A64_RST_BUS_UART0 46 +#define A64_RST_BUS_UART1 47 +#define A64_RST_BUS_UART2 48 +#define A64_RST_BUS_UART3 49 +#define A64_RST_BUS_UART4 50 + +#define A64_CLK_OSC_12M 0 +#define A64_CLK_PLL_CPUX 1 +#define A64_CLK_PLL_AUDIO_BASE 2 +#define A64_CLK_PLL_AUDIO 3 +#define A64_CLK_PLL_AUDIO_2X 4 +#define A64_CLK_PLL_AUDIO_4X 5 +#define A64_CLK_PLL_AUDIO_8X 6 +#define A64_CLK_PLL_VIDEO0 7 +#define A64_CLK_PLL_VIDEO0_2X 8 +#define A64_CLK_PLL_VE 9 +#define A64_CLK_PLL_DDR0 10 +#define A64_CLK_PLL_PERIPH0 11 +#define A64_CLK_PLL_PERIPH0_2X 12 +#define A64_CLK_PLL_PERIPH1 13 +#define A64_CLK_PLL_PERIPH1_2X 14 +#define A64_CLK_PLL_VIDEO1 15 +#define A64_CLK_PLL_GPU 16 +#define A64_CLK_PLL_MIPI 17 +#define A64_CLK_PLL_HSIC 18 +#define A64_CLK_PLL_DE 19 +#define A64_CLK_PLL_DDR1 20 +#define A64_CLK_CPUX 21 +#define A64_CLK_AXI 22 +#define A64_CLK_APB 23 +#define A64_CLK_AHB1 24 +#define A64_CLK_APB1 25 +#define A64_CLK_APB2 26 +#define A64_CLK_AHB2 27 +#define A64_CLK_BUS_MIPI_DSI 28 +#define A64_CLK_BUS_CE 29 +#define A64_CLK_BUS_DMA 30 +#define A64_CLK_BUS_MMC0 31 +#define A64_CLK_BUS_MMC1 32 +#define A64_CLK_BUS_MMC2 33 +#define A64_CLK_BUS_NAND 34 +#define A64_CLK_BUS_DRAM 35 +#define A64_CLK_BUS_EMAC 36 +#define A64_CLK_BUS_TS 37 +#define A64_CLK_BUS_HSTIMER 38 +#define A64_CLK_BUS_SPI0 39 +#define A64_CLK_BUS_SPI1 40 +#define A64_CLK_BUS_OTG 41 +#define A64_CLK_BUS_EHCI0 42 +#define A64_CLK_BUS_EHCI1 43 +#define A64_CLK_BUS_OHCI0 44 +#define A64_CLK_BUS_OHCI1 45 +#define A64_CLK_BUS_VE 46 +#define A64_CLK_BUS_TCON0 47 +#define A64_CLK_BUS_TCON1 48 +#define A64_CLK_BUS_DEINTERLACE 49 +#define A64_CLK_BUS_CSI 50 +#define A64_CLK_BUS_HDMI 51 +#define A64_CLK_BUS_DE 52 +#define A64_CLK_BUS_GPU 53 +#define A64_CLK_BUS_MSGBOX 54 +#define A64_CLK_BUS_SPINLOCK 55 +#define A64_CLK_BUS_CODEC 56 +#define A64_CLK_BUS_SPDIF 57 +#define A64_CLK_BUS_PIO 58 +#define A64_CLK_BUS_THS 59 +#define A64_CLK_BUS_I2S0 60 +#define A64_CLK_BUS_I2S1 61 +#define A64_CLK_BUS_I2S2 62 +#define A64_CLK_BUS_I2C0 63 +#define A64_CLK_BUS_I2C1 64 +#define A64_CLK_BUS_I2C2 65 +#define A64_CLK_BUS_SCR 66 +#define A64_CLK_BUS_UART0 67 +#define A64_CLK_BUS_UART1 68 +#define A64_CLK_BUS_UART2 69 +#define A64_CLK_BUS_UART3 70 +#define A64_CLK_BUS_UART4 71 +#define A64_CLK_BUS_DBG 72 +#define A64_CLK_THS 73 +#define A64_CLK_NAND 74 +#define A64_CLK_MMC0 75 +#define A64_CLK_MMC1 76 +#define A64_CLK_MMC2 77 +#define A64_CLK_TS 78 +#define A64_CLK_CE 79 +#define A64_CLK_SPI0 80 +#define A64_CLK_SPI1 81 +#define A64_CLK_I2S0 82 +#define A64_CLK_I2S1 83 +#define A64_CLK_I2S2 84 +#define A64_CLK_SPDIF 85 +#define A64_CLK_USB_PHY0 86 +#define A64_CLK_USB_PHY1 87 +#define A64_CLK_USB_HSIC 88 +#define A64_CLK_USB_HSIC_12M 89 +#define A64_CLK_USB_OHCI0_12M 90 +#define A64_CLK_USB_OHCI0 91 +#define A64_CLK_USB_OHCI1_12M 92 +#define A64_CLK_USB_OHCI1 93 +#define A64_CLK_DRAM 94 +#define A64_CLK_DRAM_VE 95 +#define A64_CLK_DRAM_CSI 96 +#define A64_CLK_DRAM_DEINTERLACE 97 +#define A64_CLK_DRAM_TS 98 +#define A64_CLK_DE 99 +#define A64_CLK_TCON0 100 +#define A64_CLK_TCON1 101 +#define A64_CLK_DEINTERLACE 102 +#define A64_CLK_CSI_MISC 103 +#define A64_CLK_CSI_SCLK 104 +#define A64_CLK_CSI_MCLK 105 +#define A64_CLK_VE 106 +#define A64_CLK_AC_DIG 107 +#define A64_CLK_AC_DIG_4X 108 +#define A64_CLK_AVS 109 +#define A64_CLK_HDMI 110 +#define A64_CLK_HDMI_DDC 111 + +#define A64_CLK_MBUS 112 + +#define A64_CLK_DSI_DPHY 113 +#define A64_CLK_GPU 114 + +void ccu_a64_register_clocks(struct aw_ccung_softc *sc); + +#endif /* __CCU_A64_H__ */ Property changes on: head/sys/arm/allwinner/clkng/ccu_a64.h ___________________________________________________________________ Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:keywords ## -0,0 +1 ## +FreeBSD=%H \ No newline at end of property Added: svn:mime-type ## -0,0 +1 ## +text/plain \ No newline at end of property Index: head/sys/conf/files.arm64 =================================================================== --- head/sys/conf/files.arm64 (revision 320611) +++ head/sys/conf/files.arm64 (revision 320612) @@ -1,198 +1,204 @@ # $FreeBSD$ cloudabi64_vdso.o optional compat_cloudabi64 \ dependency "$S/contrib/cloudabi/cloudabi_vdso_aarch64.S" \ compile-with "${CC} -x assembler-with-cpp -shared -nostdinc -nostdlib -Wl,-T$S/compat/cloudabi/cloudabi_vdso.lds $S/contrib/cloudabi/cloudabi_vdso_aarch64.S -o ${.TARGET}" \ no-obj no-implicit-rule \ clean "cloudabi64_vdso.o" # cloudabi64_vdso_blob.o optional compat_cloudabi64 \ dependency "cloudabi64_vdso.o" \ compile-with "${OBJCOPY} --input-target binary --output-target elf64-littleaarch64 --binary-architecture aarch64 cloudabi64_vdso.o ${.TARGET}" \ no-implicit-rule \ clean "cloudabi64_vdso_blob.o" # arm/allwinner/a10_ehci.c optional ehci aw_ehci fdt arm/allwinner/a10_gpio.c optional gpio aw_gpio fdt arm/allwinner/a10_mmc.c optional mmc aw_mmc fdt arm/allwinner/a64/a64_padconf.c optional soc_allwinner_a64 fdt arm/allwinner/a64/a64_r_padconf.c optional soc_allwinner_a64 fdt arm/allwinner/aw_ccu.c optional aw_ccu fdt arm/allwinner/aw_nmi.c optional aw_nmi fdt \ compile-with "${NORMAL_C} -I$S/gnu/dts/include" arm/allwinner/aw_reset.c optional aw_ccu fdt arm/allwinner/aw_rsb.c optional aw_rsb fdt arm/allwinner/aw_rtc.c optional aw_rtc fdt arm/allwinner/aw_sid.c optional aw_sid fdt arm/allwinner/aw_thermal.c optional aw_thermal fdt arm/allwinner/aw_usbphy.c optional ehci aw_usbphy fdt arm/allwinner/aw_wdog.c optional aw_wdog fdt arm/allwinner/axp81x.c optional axp81x fdt arm/allwinner/clk/aw_ahbclk.c optional aw_ccu fdt arm/allwinner/clk/aw_apbclk.c optional aw_ccu fdt arm/allwinner/clk/aw_axiclk.c optional aw_ccu fdt arm/allwinner/clk/aw_cpuclk.c optional aw_ccu fdt arm/allwinner/clk/aw_gate.c optional aw_ccu fdt arm/allwinner/clk/aw_modclk.c optional aw_ccu fdt arm/allwinner/clk/aw_pll.c optional aw_ccu fdt \ compile-with "${NORMAL_C} -I$S/gnu/dts/include" arm/allwinner/clk/aw_thsclk.c optional aw_ccu fdt arm/allwinner/clk/aw_usbclk.c optional aw_ccu fdt +arm/allwinner/clkng/aw_ccung.c optional aw_ccu fdt +arm/allwinner/clkng/aw_clk_nkmp.c optional aw_ccu fdt +arm/allwinner/clkng/aw_clk_nm.c optional aw_ccu fdt +arm/allwinner/clkng/aw_clk_prediv_mux.c optional aw_ccu fdt +arm/allwinner/clkng/ccu_a64.c optional aw_ccu fdt + arm/allwinner/if_awg.c optional awg fdt arm/annapurna/alpine/alpine_ccu.c optional al_ccu fdt arm/annapurna/alpine/alpine_nb_service.c optional al_nb_service fdt arm/annapurna/alpine/alpine_pci.c optional al_pci fdt arm/annapurna/alpine/alpine_pci_msix.c optional al_pci fdt arm/annapurna/alpine/alpine_serdes.c optional al_serdes fdt \ no-depend \ compile-with "${CC} -c -o ${.TARGET} ${CFLAGS} -I$S/contrib/alpine-hal -I$S/contrib/alpine-hal/eth ${PROF} ${.IMPSRC}" arm/arm/generic_timer.c standard arm/arm/gic.c standard arm/arm/gic_fdt.c optional fdt arm/arm/pmu.c standard arm/broadcom/bcm2835/bcm2835_audio.c optional sound vchiq fdt \ compile-with "${NORMAL_C} -DUSE_VCHIQ_ARM -D__VCCOREVER__=0x04000000 -I$S/contrib/vchiq" arm/broadcom/bcm2835/bcm2835_bsc.c optional bcm2835_bsc soc_brcm_bcm2837 fdt arm/broadcom/bcm2835/bcm2835_cpufreq.c optional soc_brcm_bcm2837 fdt arm/broadcom/bcm2835/bcm2835_dma.c optional soc_brcm_bcm2837 fdt arm/broadcom/bcm2835/bcm2835_fbd.c optional vt soc_brcm_bcm2837 fdt arm/broadcom/bcm2835/bcm2835_ft5406.c optional evdev bcm2835_ft5406 soc_brcm_bcm2837 fdt arm/broadcom/bcm2835/bcm2835_gpio.c optional gpio soc_brcm_bcm2837 fdt arm/broadcom/bcm2835/bcm2835_intr.c optional soc_brcm_bcm2837 fdt arm/broadcom/bcm2835/bcm2835_mbox.c optional soc_brcm_bcm2837 fdt arm/broadcom/bcm2835/bcm2835_rng.c optional random soc_brcm_bcm2837 fdt arm/broadcom/bcm2835/bcm2835_sdhci.c optional sdhci soc_brcm_bcm2837 fdt arm/broadcom/bcm2835/bcm2835_spi.c optional bcm2835_spi soc_brcm_bcm2837 fdt arm/broadcom/bcm2835/bcm2835_vcio.c optional soc_brcm_bcm2837 fdt arm/broadcom/bcm2835/bcm2835_wdog.c optional soc_brcm_bcm2837 fdt arm/broadcom/bcm2835/bcm2836.c optional soc_brcm_bcm2837 fdt arm/broadcom/bcm2835/bcm283x_dwc_fdt.c optional dwcotg fdt soc_brcm_bcm2837 arm64/acpica/acpi_machdep.c optional acpi arm64/acpica/OsdEnvironment.c optional acpi arm64/acpica/acpi_wakeup.c optional acpi arm64/acpica/pci_cfgreg.c optional acpi pci arm64/arm64/autoconf.c standard arm64/arm64/bus_machdep.c standard arm64/arm64/bus_space_asm.S standard arm64/arm64/busdma_bounce.c standard arm64/arm64/busdma_machdep.c standard arm64/arm64/bzero.S standard arm64/arm64/clock.c standard arm64/arm64/copyinout.S standard arm64/arm64/copystr.c standard arm64/arm64/cpufunc_asm.S standard arm64/arm64/db_disasm.c optional ddb arm64/arm64/db_interface.c optional ddb arm64/arm64/db_trace.c optional ddb arm64/arm64/debug_monitor.c optional ddb arm64/arm64/disassem.c optional ddb arm64/arm64/dump_machdep.c standard arm64/arm64/elf_machdep.c standard arm64/arm64/exception.S standard arm64/arm64/gicv3_its.c optional intrng fdt arm64/arm64/gic_v3.c standard arm64/arm64/gic_v3_fdt.c optional fdt arm64/arm64/identcpu.c standard arm64/arm64/in_cksum.c optional inet | inet6 arm64/arm64/locore.S standard no-obj arm64/arm64/machdep.c standard arm64/arm64/mem.c standard arm64/arm64/memcpy.S standard arm64/arm64/memmove.S standard arm64/arm64/minidump_machdep.c standard arm64/arm64/mp_machdep.c optional smp arm64/arm64/nexus.c standard arm64/arm64/ofw_machdep.c optional fdt arm64/arm64/pmap.c standard arm64/arm64/stack_machdep.c optional ddb | stack arm64/arm64/support.S standard arm64/arm64/swtch.S standard arm64/arm64/sys_machdep.c standard arm64/arm64/trap.c standard arm64/arm64/uio_machdep.c standard arm64/arm64/uma_machdep.c standard arm64/arm64/unwind.c optional ddb | kdtrace_hooks | stack arm64/arm64/vfp.c standard arm64/arm64/vm_machdep.c standard arm64/cavium/thunder_pcie_fdt.c optional soc_cavm_thunderx pci fdt arm64/cavium/thunder_pcie_pem.c optional soc_cavm_thunderx pci arm64/cavium/thunder_pcie_pem_fdt.c optional soc_cavm_thunderx pci fdt arm64/cavium/thunder_pcie_common.c optional soc_cavm_thunderx pci arm64/cloudabi64/cloudabi64_sysvec.c optional compat_cloudabi64 contrib/vchiq/interface/compat/vchi_bsd.c optional vchiq soc_brcm_bcm2837 \ compile-with "${NORMAL_C} -DUSE_VCHIQ_ARM -D__VCCOREVER__=0x04000000 -I$S/contrib/vchiq" contrib/vchiq/interface/vchiq_arm/vchiq_2835_arm.c optional vchiq soc_brcm_bcm2837 \ compile-with "${NORMAL_C} -Wno-unused -DUSE_VCHIQ_ARM -D__VCCOREVER__=0x04000000 -I$S/contrib/vchiq" contrib/vchiq/interface/vchiq_arm/vchiq_arm.c optional vchiq soc_brcm_bcm2837 \ compile-with "${NORMAL_C} -Wno-unused -DUSE_VCHIQ_ARM -D__VCCOREVER__=0x04000000 -I$S/contrib/vchiq" contrib/vchiq/interface/vchiq_arm/vchiq_connected.c optional vchiq soc_brcm_bcm2837 \ compile-with "${NORMAL_C} -DUSE_VCHIQ_ARM -D__VCCOREVER__=0x04000000 -I$S/contrib/vchiq" contrib/vchiq/interface/vchiq_arm/vchiq_core.c optional vchiq soc_brcm_bcm2837 \ compile-with "${NORMAL_C} -DUSE_VCHIQ_ARM -D__VCCOREVER__=0x04000000 -I$S/contrib/vchiq" contrib/vchiq/interface/vchiq_arm/vchiq_kern_lib.c optional vchiq soc_brcm_bcm2837 \ compile-with "${NORMAL_C} -DUSE_VCHIQ_ARM -D__VCCOREVER__=0x04000000 -I$S/contrib/vchiq" contrib/vchiq/interface/vchiq_arm/vchiq_kmod.c optional vchiq soc_brcm_bcm2837 \ compile-with "${NORMAL_C} -DUSE_VCHIQ_ARM -D__VCCOREVER__=0x04000000 -I$S/contrib/vchiq" contrib/vchiq/interface/vchiq_arm/vchiq_shim.c optional vchiq soc_brcm_bcm2837 \ compile-with "${NORMAL_C} -DUSE_VCHIQ_ARM -D__VCCOREVER__=0x04000000 -I$S/contrib/vchiq" contrib/vchiq/interface/vchiq_arm/vchiq_util.c optional vchiq soc_brcm_bcm2837 \ compile-with "${NORMAL_C} -DUSE_VCHIQ_ARM -D__VCCOREVER__=0x04000000 -I$S/contrib/vchiq" crypto/armv8/armv8_crypto.c optional armv8crypto armv8_crypto_wrap.o optional armv8crypto \ dependency "$S/crypto/armv8/armv8_crypto_wrap.c" \ compile-with "${CC} -c ${CFLAGS:C/^-O2$/-O3/:N-nostdinc:N-mgeneral-regs-only} ${WERROR} ${NO_WCAST_QUAL} ${PROF} -march=armv8a+crypto ${.IMPSRC}" \ no-implicit-rule \ clean "armv8_crypto_wrap.o" crypto/blowfish/bf_enc.c optional crypto | ipsec | ipsec_support crypto/des/des_enc.c optional crypto | ipsec | ipsec_support | netsmb dev/acpica/acpi_if.m optional acpi dev/ahci/ahci_generic.c optional ahci dev/axgbe/if_axgbe.c optional axgbe dev/axgbe/xgbe-desc.c optional axgbe dev/axgbe/xgbe-dev.c optional axgbe dev/axgbe/xgbe-drv.c optional axgbe dev/axgbe/xgbe-mdio.c optional axgbe dev/cpufreq/cpufreq_dt.c optional cpufreq fdt dev/hwpmc/hwpmc_arm64.c optional hwpmc dev/hwpmc/hwpmc_arm64_md.c optional hwpmc dev/mbox/mbox_if.m optional soc_brcm_bcm2837 dev/mmc/host/dwmmc.c optional dwmmc fdt dev/mmc/host/dwmmc_hisi.c optional dwmmc fdt soc_hisi_hi6220 dev/ofw/ofw_cpu.c optional fdt dev/ofw/ofwpci.c optional fdt pci dev/pci/pci_host_generic.c optional pci dev/pci/pci_host_generic_fdt.c optional pci fdt dev/psci/psci.c optional psci dev/psci/psci_arm64.S optional psci dev/uart/uart_cpu_arm64.c optional uart dev/uart/uart_dev_pl011.c optional uart pl011 dev/usb/controller/dwc_otg_hisi.c optional dwcotg fdt soc_hisi_hi6220 dev/usb/controller/generic_ehci.c optional ehci acpi dev/usb/controller/generic_ohci.c optional ohci fdt dev/usb/controller/generic_usb_if.m optional ohci fdt dev/vnic/mrml_bridge.c optional vnic fdt dev/vnic/nic_main.c optional vnic pci dev/vnic/nicvf_main.c optional vnic pci pci_iov dev/vnic/nicvf_queues.c optional vnic pci pci_iov dev/vnic/thunder_bgx_fdt.c optional vnic fdt dev/vnic/thunder_bgx.c optional vnic pci dev/vnic/thunder_mdio_fdt.c optional vnic fdt dev/vnic/thunder_mdio.c optional vnic dev/vnic/lmac_if.m optional inet | inet6 | vnic kern/kern_clocksource.c standard kern/msi_if.m optional intrng kern/pic_if.m optional intrng kern/subr_devmap.c standard kern/subr_intr.c optional intrng libkern/bcmp.c standard libkern/ffs.c standard libkern/ffsl.c standard libkern/ffsll.c standard libkern/fls.c standard libkern/flsl.c standard libkern/flsll.c standard libkern/memset.c standard libkern/arm64/crc32c_armv8.S standard cddl/contrib/opensolaris/common/atomic/aarch64/opensolaris_atomic.S optional zfs | dtrace compile-with "${CDDL_C}" cddl/dev/dtrace/aarch64/dtrace_asm.S optional dtrace compile-with "${DTRACE_S}" cddl/dev/dtrace/aarch64/dtrace_subr.c optional dtrace compile-with "${DTRACE_C}" cddl/dev/fbt/aarch64/fbt_isa.c optional dtrace_fbt | dtraceall compile-with "${FBT_C}"