Index: stable/10/lib/libpmc/pmc.haswell.3 =================================================================== --- stable/10/lib/libpmc/pmc.haswell.3 (revision 320105) +++ stable/10/lib/libpmc/pmc.haswell.3 (revision 320106) @@ -1,975 +1,962 @@ .\" Copyright (c) 2013 Hiren Panchasara .\" All rights reserved. .\" .\" Redistribution and use in source and binary forms, with or without .\" modification, are permitted provided that the following conditions .\" are met: .\" 1. Redistributions of source code must retain the above copyright .\" notice, this list of conditions and the following disclaimer. .\" 2. Redistributions in binary form must reproduce the above copyright .\" notice, this list of conditions and the following disclaimer in the .\" documentation and/or other materials provided with the distribution. .\" .\" THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND .\" ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE .\" IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE .\" ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE .\" FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL .\" DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS .\" OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) .\" HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT .\" LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY .\" OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF .\" SUCH DAMAGE. .\" .\" $FreeBSD$ .\" .Dd March 22, 2013 .Dt PMC.HASWELL 3 .Os .Sh NAME .Nm pmc.haswell .Nd measurement events for .Tn Intel .Tn Haswsell family CPUs .Sh LIBRARY .Lb libpmc .Sh SYNOPSIS .In pmc.h .Sh DESCRIPTION .Tn Intel .Tn "Haswell" CPUs contain PMCs conforming to version 2 of the .Tn Intel performance measurement architecture. These CPUs may contain up to two classes of PMCs: .Bl -tag -width "Li PMC_CLASS_IAP" .It Li PMC_CLASS_IAF Fixed-function counters that count only one hardware event per counter. .It Li PMC_CLASS_IAP Programmable counters that may be configured to count one of a defined set of hardware events. .El .Pp The number of PMCs available in each class and their widths need to be determined at run time by calling .Xr pmc_cpuinfo 3 . .Pp Intel Haswell PMCs are documented in .Rs .%B "Intel(R) 64 and IA-32 Architectures Software Developer's Manual" .%T "Combined Volumes: 1, 2A, 2B, 2C, 3A, 3B and 3C" .%N "Order Number: 325462-045US" .%D January 2013 .%Q "Intel Corporation" .Re .Ss HASWELL FIXED FUNCTION PMCS These PMCs and their supported events are documented in .Xr pmc.iaf 3 . .Ss HASWELL PROGRAMMABLE PMCS The programmable PMCs support the following capabilities: .Bl -column "PMC_CAP_INTERRUPT" "Support" .It Em Capability Ta Em Support .It PMC_CAP_CASCADE Ta \&No .It PMC_CAP_EDGE Ta Yes .It PMC_CAP_INTERRUPT Ta Yes .It PMC_CAP_INVERT Ta Yes .It PMC_CAP_READ Ta Yes .It PMC_CAP_PRECISE Ta \&No .It PMC_CAP_SYSTEM Ta Yes .It PMC_CAP_TAGGING Ta \&No .It PMC_CAP_THRESHOLD Ta Yes .It PMC_CAP_USER Ta Yes .It PMC_CAP_WRITE Ta Yes .El .Ss Event Qualifiers Event specifiers for these PMCs support the following common qualifiers: .Bl -tag -width indent .It Li rsp= Ns Ar value Configure the Off-core Response bits. .Bl -tag -width indent .It Li DMND_DATA_RD Counts the number of demand and DCU prefetch data reads of full and partial cachelines as well as demand data page table entry cacheline reads. Does not count L2 data read prefetches or instruction fetches. .It Li REQ_DMND_RFO Counts the number of demand and DCU prefetch reads for ownership (RFO) requests generated by a write to data cacheline. Does not count L2 RFO prefetches. .It Li REQ_DMND_IFETCH Counts the number of demand and DCU prefetch instruction cacheline reads. Does not count L2 code read prefetches. .It Li REQ_WB Counts the number of writeback (modified to exclusive) transactions. .It Li REQ_PF_DATA_RD Counts the number of data cacheline reads generated by L2 prefetchers. .It Li REQ_PF_RFO Counts the number of RFO requests generated by L2 prefetchers. .It Li REQ_PF_IFETCH Counts the number of code reads generated by L2 prefetchers. .It Li REQ_PF_LLC_DATA_RD L2 prefetcher to L3 for loads. .It Li REQ_PF_LLC_RFO RFO requests generated by L2 prefetcher .It Li REQ_PF_LLC_IFETCH L2 prefetcher to L3 for instruction fetches. .It Li REQ_BUS_LOCKS Bus lock and split lock requests. .It Li REQ_STRM_ST Streaming store requests. .It Li REQ_OTHER Any other request that crosses IDI, including I/O. .It Li RES_ANY Catch all value for any response types. .It Li RES_SUPPLIER_NO_SUPP No Supplier Information available. .It Li RES_SUPPLIER_LLC_HITM M-state initial lookup stat in L3. .It Li RES_SUPPLIER_LLC_HITE E-state. .It Li RES_SUPPLIER_LLC_HITS S-state. .It Li RES_SUPPLIER_LLC_HITF F-state. .It Li RES_SUPPLIER_LOCAL Local DRAM Controller. .It Li RES_SNOOP_SNP_NONE No details on snoop-related information. .It Li RES_SNOOP_SNP_NO_NEEDED No snoop was needed to satisfy the request. .It Li RES_SNOOP_SNP_MISS A snoop was needed and it missed all snooped caches: -For LLC Hit, ReslHitl was returned by all cores -For LLC Miss, Rspl was returned by all sockets and data was returned from DRAM. .It Li RES_SNOOP_HIT_NO_FWD A snoop was needed and it hits in at least one snooped cache. Hit denotes a cache-line was valid before snoop effect. This includes: -Snoop Hit w/ Invalidation (LLC Hit, RFO) -Snoop Hit, Left Shared (LLC Hit/Miss, IFetch/Data_RD) -Snoop Hit w/ Invalidation and No Forward (LLC Miss, RFO Hit S) In the LLC Miss case, data is returned from DRAM. .It Li RES_SNOOP_HIT_FWD A snoop was needed and data was forwarded from a remote socket. This includes: -Snoop Forward Clean, Left Shared (LLC Hit/Miss, IFetch/Data_RD/RFT). .It Li RES_SNOOP_HITM A snoop was needed and it HitM-ed in local or remote cache. HitM denotes a cache-line was in modified state before effect as a results of snoop. This includes: -Snoop HitM w/ WB (LLC miss, IFetch/Data_RD) -Snoop Forward Modified w/ Invalidation (LLC Hit/Miss, RFO) -Snoop MtoS (LLC Hit, IFetch/Data_RD). .It Li RES_NON_DRAM Target was non-DRAM system address. This includes MMIO transactions. .El .It Li cmask= Ns Ar value Configure the PMC to increment only if the number of configured events measured in a cycle is greater than or equal to .Ar value . .It Li edge Configure the PMC to count the number of de-asserted to asserted transitions of the conditions expressed by the other qualifiers. If specified, the counter will increment only once whenever a condition becomes true, irrespective of the number of clocks during which the condition remains true. .It Li inv Invert the sense of comparison when the .Dq Li cmask qualifier is present, making the counter increment when the number of events per cycle is less than the value specified by the .Dq Li cmask qualifier. .It Li os Configure the PMC to count events happening at processor privilege level 0. .It Li usr Configure the PMC to count events occurring at privilege levels 1, 2 or 3. .El .Pp If neither of the .Dq Li os or .Dq Li usr qualifiers are specified, the default is to enable both. .Ss Event Specifiers (Programmable PMCs) Haswell programmable PMCs support the following events: .Bl -tag -width indent .It Li LD_BLOCKS.STORE_FORWARD .Pq Event 03H , Umask 02H Loads blocked by overlapping with store buffer that cannot be forwarded. .It Li MISALIGN_MEM_REF.LOADS .Pq Event 05H , Umask 01H Speculative cache-line split load uops dispatched to L1D. .It Li MISALIGN_MEM_REF.STORES .Pq Event 05H , Umask 02H Speculative cache-line split Store-address uops dispatched to L1D. .It Li LD_BLOCKS_PARTIAL.ADDRESS_ALIAS .Pq Event 07H , Umask 01H False dependencies in MOB due to partial compare on address. .It Li DTLB_LOAD_MISSES.MISS_CAUSES_A_WALK .Pq Event 08H , Umask 01H Misses in all TLB levels that cause a page walk of any page size. .It Li DTLB_LOAD_MISSES.WALK_COMPLETED_4K .Pq Event 08H , Umask 02H Completed page walks due to demand load misses that caused 4K page walks in any TLB levels. .It Li DTLB_LOAD_MISSES.WALK_COMPLETED_2M_4K .Pq Event 08H , Umask 02H Completed page walks due to demand load misses that caused 2M/4M page walks in any TLB levels. .It Li DTLB_LOAD_MISSES.WALK_COMPLETED .Pq Event 08H , Umask 0EH Completed page walks in any TLB of any page size due to demand load misses .It Li DTLB_LOAD_MISSES.WALK_DURATION .Pq Event 08H , Umask 10H Cycle PMH is busy with a walk. .It Li DTLB_LOAD_MISSES.STLB_HIT_4K .Pq Event 08H , Umask 20H Load misses that missed DTLB but hit STLB (4K). .It Li DTLB_LOAD_MISSES.STLB_HIT_2M .Pq Event 08H , Umask 40H Load misses that missed DTLB but hit STLB (2M). .It Li DTLB_LOAD_MISSES.STLB_HIT .Pq Event 08H , Umask 60H Number of cache load STLB hits. No page walk. .It Li DTLB_LOAD_MISSES.PDE_CACHE_MISS .Pq Event 08H , Umask 80H DTLB demand load misses with low part of linear-to- physical address translation missed .It Li INT_MISC.RECOVERY_CYCLES .Pq Event 0DH , Umask 03H Cycles waiting to recover after Machine Clears except JEClear. Set Cmask= 1. .It Li UOPS_ISSUED.ANY .Pq Event 0EH , Umask 01H ncrements each cycle the # of Uops issued by the RAT to RS. Set Cmask = 1, Inv = 1, Any= 1to count stalled cycles of this core. .It Li UOPS_ISSUED.FLAGS_MERGE .Pq Event 0EH , Umask 10H Number of flags-merge uops allocated. Such uops adds delay. .It Li UOPS_ISSUED.SLOW_LEA .Pq Event 0EH , Umask 20H Number of slow LEA or similar uops allocated. Such uop has 3 sources (e.g. 2 sources + immediate) regardless if as a result of LEA instruction or not. .It Li UOPS_ISSUED.SiNGLE_MUL .Pq Event 0EH , Umask 40H Number of multiply packed/scalar single precision uops allocated. .It Li L2_RQSTS.DEMAND_DATA_RD_MISS .Pq Event 24H , Umask 21H Demand Data Read requests that missed L2, no rejects. .It Li L2_RQSTS.DEMAND_DATA_RD_HIT .Pq Event 24H , Umask 41H Demand Data Read requests that hit L2 cache. .It Li L2_RQSTS.ALL_DEMAND_DATA_RD .Pq Event 24H , Umask E1H Counts any demand and L1 HW prefetch data load requests to L2. .It Li L2_RQSTS.RFO_HIT .Pq Event 24H , Umask 42H Counts the number of store RFO requests that hit the L2 cache. .It Li L2_RQSTS.RFO_MISS .Pq Event 24H , Umask 22H Counts the number of store RFO requests that miss the L2 cache. .It Li L2_RQSTS.ALL_RFO .Pq Event 24H , Umask E2H Counts all L2 store RFO requests. .It Li L2_RQSTS.CODE_RD_HIT .Pq Event 24H , Umask 44H Number of instruction fetches that hit the L2 cache. .It Li L2_RQSTS.CODE_RD_MISS .Pq Event 24H , Umask 24H Number of instruction fetches that missed the L2 cache. .It Li L2_RQSTS.ALL_DEMAND_MISS .Pq Event 24H , Umask 27H Demand requests that miss L2 cache. .It Li L2_RQSTS.ALL_DEMAND_REFERENCES .Pq Event 24H , Umask E7H Demand requests to L2 cache. .It Li L2_RQSTS.ALL_CODE_RD .Pq Event 24H , Umask E4H Counts all L2 code requests. .It Li L2_RQSTS.L2_PF_HIT .Pq Event 24H , Umask 50H Counts all L2 HW prefetcher requests that hit L2. .It Li L2_RQSTS.L2_PF_MISS .Pq Event 24H , Umask 30H Counts all L2 HW prefetcher requests that missed L2. .It Li L2_RQSTS.ALL_PF .Pq Event 24H , Umask F8H Counts all L2 HW prefetcher requests. .It Li L2_RQSTS.MISS .Pq Event 24H , Umask 3FH All requests that missed L2. .It Li L2_RQSTS.REFERENCES .Pq Event 24H , Umask FFH All requests to L2 cache. .It Li L2_DEMAND_RQSTS.WB_HIT .Pq Event 27H , Umask 50H Not rejected writebacks that hit L2 cache .It Li LONGEST_LAT_CACHE.REFERENCE .Pq Event 2EH , Umask 4FH This event counts requests originating from the core that reference a cache line in the last level cache. .It Li LONGEST_LAT_CACHE.MISS .Pq Event 2EH , Umask 41H This event counts each cache miss condition for references to the last level cache. .It Li CPU_CLK_UNHALTED.THREAD_P .Pq Event 3CH , Umask 00H Counts the number of thread cycles while the thread is not in a halt state. The thread enters the halt state when it is running the HLT instruction. The core frequency may change from time to time due to power or thermal throttling. .It Li CPU_CLK_THREAD_UNHALTED.REF_XCLK .Pq Event 3CH , Umask 01H Increments at the frequency of XCLK (100 MHz) when not halted. .It Li L1D_PEND_MISS.PENDING .Pq Event 48H , Umask 01H Increments the number of outstanding L1D misses every cycle. Set Cmaks = 1 and Edge =1 to count occurrences. .It Li DTLB_STORE_MISSES.MISS_CAUSES_A_WALK .Pq Event 49H , Umask 01H Miss in all TLB levels causes an page walk of any page size (4K/2M/4M/1G). .It Li DTLB_STORE_MISSES.WALK_COMPLETED_4K .Pq Event 49H , Umask 02H Completed page walks due to store misses in one or more TLB levels of 4K page structure. .It Li DTLB_STORE_MISSES.WALK_COMPLETED_2M_4M .Pq Event 49H , Umask 04H Completed page walks due to store misses in one or more TLB levels of 2M/4M page structure. .It Li DTLB_STORE_MISSES.WALK_COMPLETED .Pq Event 49H , Umask 0EH Completed page walks due to store miss in any TLB levels of any page size (4K/2M/4M/1G). .It Li DTLB_STORE_MISSES.WALK_DURATION .Pq Event 49H , Umask 10H Cycles PMH is busy with this walk. .It Li DTLB_STORE_MISSES.STLB_HIT_4K .Pq Event 49H , Umask 20H Store misses that missed DTLB but hit STLB (4K). .It Li DTLB_STORE_MISSES.STLB_HIT_2M .Pq Event 49H , Umask 40H Store misses that missed DTLB but hit STLB (2M). .It Li DTLB_STORE_MISSES.STLB_HIT .Pq Event 49H , Umask 60H Store operations that miss the first TLB level but hit the second and do not cause page walks. .It Li DTLB_STORE_MISSES.PDE_CACHE_MISS .Pq Event 49H , Umask 80H DTLB store misses with low part of linear-to-physical address translation missed. .It Li LOAD_HIT_PRE.SW_PF .Pq Event 4CH , Umask 01H Non-SW-prefetch load dispatches that hit fill buffer allocated for S/W prefetch. .It Li LOAD_HIT_PRE.HW_PF .Pq Event 4CH , Umask 02H Non-SW-prefetch load dispatches that hit fill buffer allocated for H/W prefetch. .It Li L1D.REPLACEMENT .Pq Event 51H , Umask 01H Counts the number of lines brought into the L1 data cache. .It Li MOVE_ELIMINATION.INT_NOT_ELIMINATED .Pq Event 58H , Umask 04H Number of integer Move Elimination candidate uops that were not eliminated. .It Li MOVE_ELIMINATION.SMID_NOT_ELIMINATED .Pq Event 58H , Umask 08H Number of SIMD Move Elimination candidate uops that were not eliminated. .It Li MOVE_ELIMINATION.INT_ELIMINATED .Pq Event 58H , Umask 01H Unhalted core cycles when the thread is in ring 0. .It Li MOVE_ELIMINATION.SMID_ELIMINATED .Pq Event 58H , Umask 02H Number of SIMD Move Elimination candidate uops that were eliminated. .It Li CPL_CYCLES.RING0 .Pq Event 5CH , Umask 02H Unhalted core cycles when the thread is in ring 0. .It Li CPL_CYCLES.RING123 .Pq Event 5CH , Umask 01H Unhalted core cycles when the thread is not in ring 0. .It Li RS_EVENTS.EMPTY_CYCLES .Pq Event 5EH , Umask 01H Cycles the RS is empty for the thread. .It Li OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD .Pq Event 60H , Umask 01H Offcore outstanding Demand Data Read transactions in SQ to uncore. Set Cmask=1 to count cycles. .It Li OFFCORE_REQUESTS_OUTSTANDING.DEMAND_CORE_RD .Pq Event 60H , Umask 02H Offcore outstanding Demand code Read transactions in SQ to uncore. Set Cmask=1 to count cycles. .It Li OFFCORE_REQUESTS_OUTSTANDING.DEMAND_RFO .Pq Event 60H , Umask 04H Offcore outstanding RFO store transactions in SQ to uncore. Set Cmask=1 to count cycles. .It Li OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD .Pq Event 60H , Umask 08H Offcore outstanding cacheable data read transactions in SQ to uncore. Set Cmask=1 to count cycles. .It Li LOCK_CYCLES.SPLIT_LOCK_UC_LOCK_DURATION .Pq Event 63H , Umask 01H Cycles in which the L1D and L2 are locked, due to a UC lock or split lock. .It Li LOCK_CYCLES.CACHE_LOCK_DURATION .Pq Event 63H , Umask 02H Cycles in which the L1D is locked. .It Li IDQ.EMPTY .Pq Event 79H , Umask 02H Counts cycles the IDQ is empty. .It Li IDQ.MITE_UOPS .Pq Event 79H , Umask 04H Increment each cycle # of uops delivered to IDQ from MITE path. Set Cmask = 1 to count cycles. .It Li IDQ.DSB_UOPS .Pq Event 79H , Umask 08H Increment each cycle. # of uops delivered to IDQ from DSB path. Set Cmask = 1 to count cycles. .It Li IDQ.MS_DSB_UOPS .Pq Event 79H , Umask 10H Increment each cycle # of uops delivered to IDQ when MS_busy by DSB. Set Cmask = 1 to count cycles. Add Edge=1 to count # of delivery. .It Li IDQ.MS_MITE_UOPS .Pq Event 79H , Umask 20H ncrement each cycle # of uops delivered to IDQ when MS_busy by MITE. Set Cmask = 1 to count cycles. .It Li IDQ.MS_UOPS .Pq Event 79H , Umask 30H Increment each cycle # of uops delivered to IDQ from MS by either DSB or MITE. Set Cmask = 1 to count cycles. .It Li IDQ.ALL_DSB_CYCLES_ANY_UOPS .Pq Event 79H , Umask 18H Counts cycles DSB is delivered at least one uops. Set Cmask = 1. .It Li IDQ.ALL_DSB_CYCLES_4_UOPS .Pq Event 79H , Umask 18H Counts cycles DSB is delivered four uops. Set Cmask =4. .It Li IDQ.ALL_MITE_CYCLES_ANY_UOPS .Pq Event 79H , Umask 24H Counts cycles MITE is delivered at least one uops. Set Cmask = 1. .It Li IDQ.ALL_MITE_CYCLES_4_UOPS .Pq Event 79H , Umask 24H Counts cycles MITE is delivered four uops. Set Cmask =4. .It Li IDQ.MITE_ALL_UOPS .Pq Event 79H , Umask 3CH # of uops delivered to IDQ from any path. .It Li ICACHE.MISSES .Pq Event 80H , Umask 02H Number of Instruction Cache, Streaming Buffer and Victim Cache Misses. Includes UC accesses. .It Li ITLB_MISSES.MISS_CAUSES_A_WALK .Pq Event 85H , Umask 01H Misses in ITLB that causes a page walk of any page size. .It Li ITLB_MISSES.WALK_COMPLETED_4K .Pq Event 85H , Umask 02H Completed page walks due to misses in ITLB 4K page entries. .It Li TLB_MISSES.WALK_COMPLETED_2M_4M .Pq Event 85H , Umask 04H Completed page walks due to misses in ITLB 2M/4M page entries. .It Li ITLB_MISSES.WALK_COMPLETED .Pq Event 85H , Umask 0EH Completed page walks in ITLB of any page size. .It Li ITLB_MISSES.WALK_DURATION .Pq Event 85H , Umask 10H Cycle PMH is busy with a walk. .It Li ITLB_MISSES.STLB_HIT_4K .Pq Event 85H , Umask 20H ITLB misses that hit STLB (4K). .It Li ITLB_MISSES.STLB_HIT_2M .Pq Event 85H , Umask 40H ITLB misses that hit STLB (2K). .It Li ITLB_MISSES.STLB_HIT .Pq Event 85H , Umask 60H TLB misses that hit STLB. No page walk. .It Li ILD_STALL.LCP .Pq Event 87H , Umask 01H Stalls caused by changing prefix length of the instruction. .It Li ILD_STALL.IQ_FULL .Pq Event 87H , Umask 04H Stall cycles due to IQ is full. -.It Li BR_INST_EXEC.COND -.Pq Event 88H , Umask 01H -Qualify conditional near branch instructions -executed, but not necessarily retired. +.It Li BR_INST_EXEC.NONTAKEN_COND +.Pq Event 88H , Umask 41H +Count conditional near branch instructions that were executed (but not +necessarily retired) and not taken. +.It Li BR_INST_EXEC.TAKEN_COND +.Pq Event 88H , Umask 81H +Count conditional near branch instructions that were executed (but not +necessarily retired) and taken. .It Li BR_INST_EXEC.DIRECT_JMP -.Pq Event 88H , Umask 02H -Qualify all unconditional near branch instructions -excluding calls and indirect branches. +.Pq Event 88H , Umask 82H +Count all unconditional near branch instructions excluding calls and +indirect branches. .It Li BR_INST_EXEC.INDIRECT_JMP_NON_CALL_RET -.Pq Event 88H , Umask 04H -Qualify executed indirect near branch instructions -that are not calls nor returns. +.Pq Event 88H , Umask 84H +Count executed indirect near branch instructions that are not calls nor +returns. .It Li BR_INST_EXEC.RETURN_NEAR -.Pq Event 88H , Umask 08H -Qualify indirect near branches that have a return -mnemonic. +.Pq Event 88H , Umask 88H +Count indirect near branches that have a return mnemonic. .It Li BR_INST_EXEC.DIRECT_NEAR_CALL -.Pq Event 88H , Umask 10H -Qualify unconditional near call branch instructions, -excluding non call branch, executed. +.Pq Event 88H , Umask 90H +Count unconditional near call branch instructions, excluding non call +branch, executed. .It Li BR_INST_EXEC.INDIRECT_NEAR_CALL -.Pq Event 88H , Umask 20H -Qualify indirect near calls, including both register and -memory indirect, executed. -.It Li BR_INST_EXEC.NONTAKEN -.Pq Event 88H , Umask 40H -Qualify non-taken near branches executed. -.It Li BR_INST_EXEC.TAKEN -.Pq Event 88H , Umask 80H -Qualify taken near branches executed. Must combine -with 01H,02H, 04H, 08H, 10H, 20H. +.Pq Event 88H , Umask A0H +Count indirect near calls, including both register and memory indirect, +executed. .It Li BR_INST_EXEC.ALL_BRANCHES .Pq Event 88H , Umask FFH -Counts all near executed branches (not necessarily -retired). -.It Li BR_MISP_EXEC.COND -.Pq Event 89H , Umask 01H -Qualify conditional near branch instructions -mispredicted. +Counts all near executed branches (not necessarily retired). +.It Li BR_MISP_EXEC.NONTAKEN_COND +.Pq Event 89H , Umask 41H +Count conditional near branch instructions mispredicted as nontaken. +.It Li BR_MISP_EXEC.TAKEN_COND +.Pq Event 89H , Umask 81H +Count conditional near branch instructions mispredicted as taken. .It Li BR_MISP_EXEC.INDIRECT_JMP_NON_CALL_RET -.Pq Event 89H , Umask 04H -Qualify mispredicted indirect near branch -instructions that are not calls nor returns. +.Pq Event 89H , Umask 84H +Count mispredicted indirect near branch instructions that are not calls +nor returns. .It Li BR_MISP_EXEC.RETURN_NEAR -.Pq Event 89H , Umask 08H -Qualify mispredicted indirect near branches that -have a return mnemonic. +.Pq Event 89H , Umask 88H +Count mispredicted indirect near branches that have a return mnemonic. .It Li BR_MISP_EXEC.DIRECT_NEAR_CALL -.Pq Event 89H , Umask 10H -Qualify mispredicted unconditional near call branch -instructions, excluding non call branch, executed. +.Pq Event 89H , Umask 90H +Count mispredicted unconditional near call branch instructions, excluding +non call branch, executed. .It Li BR_MISP_EXEC.INDIRECT_NEAR_CALL -.Pq Event 89H , Umask 20H -Qualify mispredicted indirect near calls, including -both register and memory indirect, executed. -.It Li BR_MISP_EXEC.NONTAKEN -.Pq Event 89H , Umask 40H -Qualify mispredicted non-taken near branches -executed. -.It Li BR_MISP_EXEC.TAKEN -.Pq Event 89H , Umask 80H -Qualify mispredicted taken near branches executed. -Must combine with 01H,02H, 04H, 08H, 10H, 20H. +.Pq Event 89H , Umask A0H +Count mispredicted indirect near calls, including both register and memory +indirect, executed. .It Li BR_MISP_EXEC.ALL_BRANCHES .Pq Event 89H , Umask FFH -Counts all near executed branches (not necessarily -retired). +Counts all mispredicted near executed branches (not necessarily retired). .It Li IDQ_UOPS_NOT_DELIVERED.CORE .Pq Event 9CH , Umask 01H Count number of non-delivered uops to RAT per thread. .It Li UOPS_EXECUTED_PORT.PORT_0 .Pq Event A1H , Umask 01H Cycles which a Uop is dispatched on port 0 in this thread. .It Li UOPS_EXECUTED_PORT.PORT_1 .Pq Event A1H , Umask 02H Cycles which a Uop is dispatched on port 1 in this thread. .It Li UOPS_EXECUTED_PORT.PORT_2 .Pq Event A1H , Umask 04H Cycles which a Uop is dispatched on port 2 in this thread. .It Li UOPS_EXECUTED_PORT.PORT_3 .Pq Event A1H , Umask 08H Cycles which a Uop is dispatched on port 3 in this thread. .It Li UOPS_EXECUTED_PORT.PORT_4 .Pq Event A1H , Umask 10H Cycles which a Uop is dispatched on port 4 in this thread. .It Li UOPS_EXECUTED_PORT.PORT_5 .Pq Event A1H , Umask 20H Cycles which a Uop is dispatched on port 5 in this thread. .It Li UOPS_EXECUTED_PORT.PORT_6 .Pq Event A1H , Umask 40H Cycles which a Uop is dispatched on port 6 in this thread. .It Li UOPS_EXECUTED_PORT.PORT_7 .Pq Event A1H , Umask 80H Cycles which a Uop is dispatched on port 7 in this thread. .It Li RESOURCE_STALLS.ANY .Pq Event A2H , Umask 01H Cycles Allocation is stalled due to Resource Related reason. .It Li RESOURCE_STALLS.RS .Pq Event A2H , Umask 04H Cycles stalled due to no eligible RS entry available. .It Li RESOURCE_STALLS.SB .Pq Event A2H , Umask 08H Cycles stalled due to no store buffers available (not including draining form sync). .It Li RESOURCE_STALLS.ROB .Pq Event A2H , Umask 10H Cycles stalled due to re-order buffer full. .It Li CYCLE_ACTIVITY.CYCLES_L2_PENDING .Pq Event A3H , Umask 01H Cycles with pending L2 miss loads. Set Cmask=2 to count cycle. .It Li CYCLE_ACTIVITY.CYCLES_LDM_PENDING .Pq Event A3H , Umask 02H Cycles with pending memory loads. Set Cmask=2 to count cycle. .It Li CYCLE_ACTIVITY.STALLS_L2_PENDING .Pq Event A3H , Umask 05H Number of loads missed L2. .It Li CYCLE_ACTIVITY.CYCLES_L1D_PENDING .Pq Event A3H , Umask 08H Cycles with pending L1 cache miss loads. Set Cmask=8 to count cycle. .It Li ITLB.ITLB_FLUSH .Pq Event AEH , Umask 01H Counts the number of ITLB flushes, includes 4k/2M/4M pages. .It Li OFFCORE_REQUESTS.DEMAND_DATA_RD .Pq Event B0H , Umask 01H Demand data read requests sent to uncore. .It Li OFFCORE_REQUESTS.DEMAND_CODE_RD .Pq Event B0H , Umask 02H Demand code read requests sent to uncore. .It Li OFFCORE_REQUESTS.DEMAND_RFO .Pq Event B0H , Umask 04H Demand RFO read requests sent to uncore, including regular RFOs, locks, ItoM. .It Li OFFCORE_REQUESTS.ALL_DATA_RD .Pq Event B0H , Umask 08H Data read requests sent to uncore (demand and prefetch). .It Li UOPS_EXECUTED.CORE .Pq Event B1H , Umask 02H Counts total number of uops to be executed per-core each cycle. .It Li OFF_CORE_RESPONSE_0 .Pq Event B7H , Umask 01H Requires MSR 01A6H .It Li OFF_CORE_RESPONSE_1 .Pq Event BBH , Umask 01H Requires MSR 01A7H .It Li PAGE_WALKER_LOADS.DTLB_L1 .Pq Event BCH , Umask 11H Number of DTLB page walker loads that hit in the L1+FB. .It Li PAGE_WALKER_LOADS.ITLB_L1 .Pq Event BCH , Umask 21H Number of ITLB page walker loads that hit in the L1+FB. .It Li PAGE_WALKER_LOADS.DTLB_L2 .Pq Event BCH , Umask 12H Number of DTLB page walker loads that hit in the L2. .It Li PAGE_WALKER_LOADS.ITLB_L2 .Pq Event BCH , Umask 22H Number of ITLB page walker loads that hit in the L2. .It Li PAGE_WALKER_LOADS.DTLB_L3 .Pq Event BCH , Umask 14H Number of DTLB page walker loads that hit in the L3. .It Li PAGE_WALKER_LOADS.ITLB_L3 .Pq Event BCH , Umask 24H Number of ITLB page walker loads that hit in the L3. .It Li PAGE_WALKER_LOADS.DTLB_MEMORY .Pq Event BCH , Umask 18H Number of DTLB page walker loads from memory. .It Li PAGE_WALKER_LOADS.ITLB_MEMORY .Pq Event BCH , Umask 28H Number of ITLB page walker loads from memory. .It Li TLB_FLUSH.DTLB_THREAD .Pq Event BDH , Umask 01H DTLB flush attempts of the thread-specific entries. .It Li TLB_FLUSH.STLB_ANY .Pq Event BDH , Umask 20H Count number of STLB flush attempts. .It Li INST_RETIRED.ANY_P .Pq Event C0H , Umask 00H Number of instructions at retirement. .It Li INST_RETIRED.ALL .Pq Event C0H , Umask 01H Precise instruction retired event with HW to reduce effect of PEBS shadow in IP distribution. .It Li OTHER_ASSISTS.AVX_TO_SSE .Pq Event C1H , Umask 08H Number of transitions from AVX-256 to legacy SSE when penalty applicable. .It Li OTHER_ASSISTS.SSE_TO_AVX .Pq Event C1H , Umask 10H Number of transitions from SSE to AVX-256 when penalty applicable. .It Li OTHER_ASSISTS.ANY_WB_ASSIST .Pq Event C1H , Umask 40H Number of microcode assists invoked by HW upon uop writeback. .It Li UOPS_RETIRED.ALL .Pq Event C2H , Umask 01H Counts the number of micro-ops retired, Use cmask=1 and invert to count active cycles or stalled cycles. .It Li UOPS_RETIRED.RETIRE_SLOTS .Pq Event C2H , Umask 02H Counts the number of retirement slots used each cycle. .It Li MACHINE_CLEARS.MEMORY_ORDERING .Pq Event C3H , Umask 02H Counts the number of machine clears due to memory order conflicts. .It Li MACHINE_CLEARS.SMC .Pq Event C3H , Umask 04H Number of self-modifying-code machine clears detected. .It Li MACHINE_CLEARS.MASKMOV .Pq Event C3H , Umask 20H Counts the number of executed AVX masked load operations that refer to an illegal address range with the mask bits set to 0. .It Li BR_INST_RETIRED.ALL_BRANCHES .Pq Event C4H , Umask 00H Branch instructions at retirement. .It Li BR_INST_RETIRED.CONDITIONAL .Pq Event C4H , Umask 01H Counts the number of conditional branch instructions Supports PEBS retired. .It Li BR_INST_RETIRED.NEAR_CALL .Pq Event C4H , Umask 02H Direct and indirect near call instructions retired. .It Li BR_INST_RETIRED.ALL_BRANCHES .Pq Event C4H , Umask 04H Counts the number of branch instructions retired. .It Li BR_INST_RETIRED.NEAR_RETURN .Pq Event C4H , Umask 08H Counts the number of near return instructions retired. .It Li BR_INST_RETIRED.NOT_TAKEN .Pq Event C4H , Umask 10H Counts the number of not taken branch instructions retired. It Li BR_INST_RETIRED.NEAR_TAKEN .Pq Event C4H , Umask 20H Number of near taken branches retired. .It Li BR_INST_RETIRED.FAR_BRANCH .Pq Event C4H , Umask 40H Number of far branches retired. .It Li BR_MISP_RETIRED.ALL_BRANCHES .Pq Event C5H , Umask 00H Mispredicted branch instructions at retirement .It Li BR_MISP_RETIRED.CONDITIONAL .Pq Event C5H , Umask 01H Mispredicted conditional branch instructions retired. .It Li BR_MISP_RETIRED.CONDITIONAL .Pq Event C5H , Umask 04H Mispredicted macro branch instructions retired. .It Li FP_ASSIST.X87_OUTPUT .Pq Event CAH , Umask 02H Number of X87 FP assists due to Output values. .It Li FP_ASSIST.X87_INPUT .Pq Event CAH , Umask 04H Number of X87 FP assists due to input values. .It Li FP_ASSIST.SIMD_OUTPUT .Pq Event CAH , Umask 08H Number of SIMD FP assists due to Output values. .It Li FP_ASSIST.SIMD_INPUT .Pq Event CAH , Umask 10H Number of SIMD FP assists due to input values. .It Li FP_ASSIST.ANY .Pq Event CAH , Umask 1EH Cycles with any input/output SSE* or FP assists. .It Li ROB_MISC_EVENTS.LBR_INSERTS .Pq Event CCH , Umask 20H Count cases of saving new LBR records by hardware. .It Li MEM_TRANS_RETIRED.LOAD_LATENCY .Pq Event CDH , Umask 01H Randomly sampled loads whose latency is above a user defined threshold. A small fraction of the overall loads are sampled due to randomization. .It Li MEM_UOP_RETIRED.LOADS .Pq Event D0H , Umask 01H Qualify retired memory uops that are loads. Combine Supports PEBS and with umask 10H, 20H, 40H, 80H. .It Li MEM_UOP_RETIRED.STORES .Pq Event D0H , Umask 02H Qualify retired memory uops that are stores. Combine with umask 10H, 20H, 40H, 80H. .It Li MEM_UOP_RETIRED.STLB_MISS .Pq Event D0H , Umask 10H Qualify retired memory uops with STLB miss. Must combine with umask 01H, 02H, to produce counts. .It Li MEM_UOP_RETIRED.LOCK .Pq Event D0H , Umask 20H Qualify retired memory uops with lock. Must combine Supports PEBS and with umask 01H, 02H, to produce counts. .It Li MEM_UOP_RETIRED.SPLIT .Pq Event D0H , Umask 40H Qualify retired memory uops with line split. Must combine with umask 01H, 02H, to produce counts. .It Li MEM_UOP_RETIRED.ALL .Pq Event D0H , Umask 80H Qualify any retired memory uops. Must combine with Supports PEBS and umask 01H, 02H, to produce counts. .It Li MEM_LOAD_UOPS_RETIRED.L1_HIT .Pq Event D1H , Umask 01H Retired load uops with L1 cache hits as data sources. .It Li MEM_LOAD_UOPS_RETIRED.L2_HIT .Pq Event D1H , Umask 02H Retired load uops with L2 cache hits as data sources. .It Li MEM_LOAD_UOPS_RETIRED.LLC_HIT .Pq Event D1H , Umask 04H Retired load uops with LLC cache hits as data sources. .It Li MEM_LOAD_UOPS_RETIRED.L2_MISS .Pq Event D1H , Umask 10H Retired load uops missed L2. Unknown data source excluded. .It Li MEM_LOAD_UOPS_RETIRED.HIT_LFB .Pq Event D1H , Umask 40H Retired load uops which data sources were load uops missed L1 but hit FB due to preceding miss to the same cache line with data not ready. .It Li MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_MISS .Pq Event D2H , Umask 01H Retired load uops which data sources were LLC hit and cross-core snoop missed in on-pkg core cache. .It Li MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HIT .Pq Event D2H , Umask 02H Retired load uops which data sources were LLC and cross-core snoop hits in on-pkg core cache. .It Li MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HITM .Pq Event D2H , Umask 04H Retired load uops which data sources were HitM responses from shared LLC. .It Li MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_NONE .Pq Event D2H , Umask 08H Retired load uops which data sources were hits in LLC without snoops required. .It Li MEM_LOAD_UOPS_LLC_MISS_RETIRED.LOCAL_DRAM .Pq Event D3H , Umask 01H Retired load uops which data sources missed LLC but serviced from local dram. .It Li BACLEARS.ANY .Pq Event E6H , Umask 1FH Number of front end re-steers due to BPU misprediction. .It Li L2_TRANS.DEMAND_DATA_RD .Pq Event F0H , Umask 01H Demand Data Read requests that access L2 cache. .It Li L2_TRANS.RFO .Pq Event F0H , Umask 02H RFO requests that access L2 cache. .It Li L2_TRANS.CODE_RD .Pq Event F0H , Umask 04H L2 cache accesses when fetching instructions. .It Li L2_TRANS.ALL_PF .Pq Event F0H , Umask 08H Any MLC or LLC HW prefetch accessing L2, including rejects. .It Li L2_TRANS.L1D_WB .Pq Event F0H , Umask 10H L1D writebacks that access L2 cache. .It Li L2_TRANS.L2_FILL .Pq Event F0H , Umask 20H L2 fill requests that access L2 cache. .It Li L2_TRANS.L2_WB .Pq Event F0H , Umask 40H L2 writebacks that access L2 cache. .It Li L2_TRANS.ALL_REQUESTS .Pq Event F0H , Umask 80H Transactions accessing L2 pipe. .It Li L2_LINES_IN.I .Pq Event F1H , Umask 01H L2 cache lines in I state filling L2. .It Li L2_LINES_IN.S .Pq Event F1H , Umask 02H L2 cache lines in S state filling L2. .It Li L2_LINES_IN.E .Pq Event F1H , Umask 04H L2 cache lines in E state filling L2. .It Li L2_LINES_IN.ALL .Pq Event F1H , Umask 07H L2 cache lines filling L2. .It Li L2_LINES_OUT.DEMAND_CLEAN .Pq Event F2H , Umask 05H Clean L2 cache lines evicted by demand. .It Li L2_LINES_OUT.DEMAND_DIRTY .Pq Event F2H , Umask 06H Dirty L2 cache lines evicted by demand. .El .Sh SEE ALSO .Xr pmc 3 , .Xr pmc.atom 3 , .Xr pmc.core 3 , .Xr pmc.iaf 3 , .Xr pmc.ucf 3 , .Xr pmc.k7 3 , .Xr pmc.k8 3 , .Xr pmc.p4 3 , .Xr pmc.p5 3 , .Xr pmc.p6 3 , .Xr pmc.corei7 3 , .Xr pmc.corei7uc 3 , .Xr pmc.haswelluc 3 , .Xr pmc.ivybridge 3 , .Xr pmc.ivybridgexeon 3 , .Xr pmc.sandybridge 3 , .Xr pmc.sandybridgeuc 3 , .Xr pmc.sandybridgexeon 3 , .Xr pmc.westmere 3 , .Xr pmc.westmereuc 3 , .Xr pmc.soft 3 , .Xr pmc.tsc 3 , .Xr pmc_cpuinfo 3 , .Xr pmclog 3 , .Xr hwpmc 4 .Sh HISTORY The .Nm pmc library first appeared in .Fx 6.0 . .Sh AUTHORS The .Lb libpmc library was written by .An "Joseph Koshy" .Aq jkoshy@FreeBSD.org . The support for the Haswell microarchitecture was written by .An "Hiren Panchasara" .Aq hiren.panchasara@gmail.com . Index: stable/10/lib/libpmc/pmc.haswellxeon.3 =================================================================== --- stable/10/lib/libpmc/pmc.haswellxeon.3 (revision 320105) +++ stable/10/lib/libpmc/pmc.haswellxeon.3 (revision 320106) @@ -1,975 +1,962 @@ .\" .\" Copyright (c) 2013 Hiren Panchasara .\" All rights reserved. .\" .\" Redistribution and use in source and binary forms, with or without .\" modification, are permitted provided that the following conditions .\" are met: .\" 1. Redistributions of source code must retain the above copyright .\" notice, this list of conditions and the following disclaimer. .\" 2. Redistributions in binary form must reproduce the above copyright .\" notice, this list of conditions and the following disclaimer in the .\" documentation and/or other materials provided with the distribution. .\" .\" THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND .\" ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE .\" IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE .\" ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE .\" FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL .\" DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS .\" OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) .\" HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT .\" LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY .\" OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF .\" SUCH DAMAGE. .\" .\" $FreeBSD$ .\" .Dd 21 November, 2014 .Dt PMC.HASWELLXEON 3 .Os .Sh NAME .Nm pmc.haswellxeon .Nd measurement events for .Tn Intel .Tn Haswell Xeon family CPUs .Sh LIBRARY .Lb libpmc .Sh SYNOPSIS .In pmc.h .Sh DESCRIPTION .Tn Intel .Tn "Haswell" CPUs contain PMCs conforming to version 2 of the .Tn Intel performance measurement architecture. These CPUs may contain up to two classes of PMCs: .Bl -tag -width "Li PMC_CLASS_IAP" .It Li PMC_CLASS_IAF Fixed-function counters that count only one hardware event per counter. .It Li PMC_CLASS_IAP Programmable counters that may be configured to count one of a defined set of hardware events. .El .Pp The number of PMCs available in each class and their widths need to be determined at run time by calling .Xr pmc_cpuinfo 3 . .Pp Intel Haswell Xeon PMCs are documented in .Rs .%B "Intel(R) 64 and IA-32 Architectures Software Developer's Manual" .%T "Combined Volumes: 1, 2A, 2B, 2C, 3A, 3B and 3C" .%N "Order Number: 325462-052US" .%D September 2014 .%Q "Intel Corporation" .Re .Ss HASWELL FIXED FUNCTION PMCS These PMCs and their supported events are documented in .Xr pmc.iaf 3 . .Ss HASWELL PROGRAMMABLE PMCS The programmable PMCs support the following capabilities: .Bl -column "PMC_CAP_INTERRUPT" "Support" .It Em Capability Ta Em Support .It PMC_CAP_CASCADE Ta \&No .It PMC_CAP_EDGE Ta Yes .It PMC_CAP_INTERRUPT Ta Yes .It PMC_CAP_INVERT Ta Yes .It PMC_CAP_READ Ta Yes .It PMC_CAP_PRECISE Ta \&No .It PMC_CAP_SYSTEM Ta Yes .It PMC_CAP_TAGGING Ta \&No .It PMC_CAP_THRESHOLD Ta Yes .It PMC_CAP_USER Ta Yes .It PMC_CAP_WRITE Ta Yes .El .Ss Event Qualifiers Event specifiers for these PMCs support the following common qualifiers: .Bl -tag -width indent .It Li rsp= Ns Ar value Configure the Off-core Response bits. .Bl -tag -width indent .It Li DMND_DATA_RD Counts the number of demand and DCU prefetch data reads of full and partial cachelines as well as demand data page table entry cacheline reads. Does not count L2 data read prefetches or instruction fetches. .It Li REQ_DMND_RFO Counts the number of demand and DCU prefetch reads for ownership (RFO) requests generated by a write to data cacheline. Does not count L2 RFO prefetches. .It Li REQ_DMND_IFETCH Counts the number of demand and DCU prefetch instruction cacheline reads. Does not count L2 code read prefetches. .It Li REQ_WB Counts the number of writeback (modified to exclusive) transactions. .It Li REQ_PF_DATA_RD Counts the number of data cacheline reads generated by L2 prefetchers. .It Li REQ_PF_RFO Counts the number of RFO requests generated by L2 prefetchers. .It Li REQ_PF_IFETCH Counts the number of code reads generated by L2 prefetchers. .It Li REQ_PF_LLC_DATA_RD L2 prefetcher to L3 for loads. .It Li REQ_PF_LLC_RFO RFO requests generated by L2 prefetcher .It Li REQ_PF_LLC_IFETCH L2 prefetcher to L3 for instruction fetches. .It Li REQ_BUS_LOCKS Bus lock and split lock requests. .It Li REQ_STRM_ST Streaming store requests. .It Li REQ_OTHER Any other request that crosses IDI, including I/O. .It Li RES_ANY Catch all value for any response types. .It Li RES_SUPPLIER_NO_SUPP No Supplier Information available. .It Li RES_SUPPLIER_LLC_HITM M-state initial lookup stat in L3. .It Li RES_SUPPLIER_LLC_HITE E-state. .It Li RES_SUPPLIER_LLC_HITS S-state. .It Li RES_SUPPLIER_LLC_HITF F-state. .It Li RES_SUPPLIER_LOCAL Local DRAM Controller. .It Li RES_SNOOP_SNP_NONE No details on snoop-related information. .It Li RES_SNOOP_SNP_NO_NEEDED No snoop was needed to satisfy the request. .It Li RES_SNOOP_SNP_MISS A snoop was needed and it missed all snooped caches: -For LLC Hit, ReslHitl was returned by all cores -For LLC Miss, Rspl was returned by all sockets and data was returned from DRAM. .It Li RES_SNOOP_HIT_NO_FWD A snoop was needed and it hits in at least one snooped cache. Hit denotes a cache-line was valid before snoop effect. This includes: -Snoop Hit w/ Invalidation (LLC Hit, RFO) -Snoop Hit, Left Shared (LLC Hit/Miss, IFetch/Data_RD) -Snoop Hit w/ Invalidation and No Forward (LLC Miss, RFO Hit S) In the LLC Miss case, data is returned from DRAM. .It Li RES_SNOOP_HIT_FWD A snoop was needed and data was forwarded from a remote socket. This includes: -Snoop Forward Clean, Left Shared (LLC Hit/Miss, IFetch/Data_RD/RFT). .It Li RES_SNOOP_HITM A snoop was needed and it HitM-ed in local or remote cache. HitM denotes a cache-line was in modified state before effect as a results of snoop. This includes: -Snoop HitM w/ WB (LLC miss, IFetch/Data_RD) -Snoop Forward Modified w/ Invalidation (LLC Hit/Miss, RFO) -Snoop MtoS (LLC Hit, IFetch/Data_RD). .It Li RES_NON_DRAM Target was non-DRAM system address. This includes MMIO transactions. .El .It Li cmask= Ns Ar value Configure the PMC to increment only if the number of configured events measured in a cycle is greater than or equal to .Ar value . .It Li edge Configure the PMC to count the number of de-asserted to asserted transitions of the conditions expressed by the other qualifiers. If specified, the counter will increment only once whenever a condition becomes true, irrespective of the number of clocks during which the condition remains true. .It Li inv Invert the sense of comparison when the .Dq Li cmask qualifier is present, making the counter increment when the number of events per cycle is less than the value specified by the .Dq Li cmask qualifier. .It Li os Configure the PMC to count events happening at processor privilege level 0. .It Li usr Configure the PMC to count events occurring at privilege levels 1, 2 or 3. .El .Pp If neither of the .Dq Li os or .Dq Li usr qualifiers are specified, the default is to enable both. .Ss Event Specifiers (Programmable PMCs) Haswell programmable PMCs support the following events: .Bl -tag -width indent .It Li LD_BLOCKS.STORE_FORWARD .Pq Event 03H , Umask 02H Loads blocked by overlapping with store buffer that cannot be forwarded. .It Li MISALIGN_MEM_REF.LOADS .Pq Event 05H , Umask 01H Speculative cache-line split load uops dispatched to L1D. .It Li MISALIGN_MEM_REF.STORES .Pq Event 05H , Umask 02H Speculative cache-line split Store-address uops dispatched to L1D. .It Li LD_BLOCKS_PARTIAL.ADDRESS_ALIAS .Pq Event 07H , Umask 01H False dependencies in MOB due to partial compare on address. .It Li DTLB_LOAD_MISSES.MISS_CAUSES_A_WALK .Pq Event 08H , Umask 01H Misses in all TLB levels that cause a page walk of any page size. .It Li DTLB_LOAD_MISSES.WALK_COMPLETED_4K .Pq Event 08H , Umask 02H Completed page walks due to demand load misses that caused 4K page walks in any TLB levels. .It Li DTLB_LOAD_MISSES.WALK_COMPLETED_2M_4K .Pq Event 08H , Umask 02H Completed page walks due to demand load misses that caused 2M/4M page walks in any TLB levels. .It Li DTLB_LOAD_MISSES.WALK_COMPLETED .Pq Event 08H , Umask 0EH Completed page walks in any TLB of any page size due to demand load misses .It Li DTLB_LOAD_MISSES.WALK_DURATION .Pq Event 08H , Umask 10H Cycle PMH is busy with a walk. .It Li DTLB_LOAD_MISSES.STLB_HIT_4K .Pq Event 08H , Umask 20H Load misses that missed DTLB but hit STLB (4K). .It Li DTLB_LOAD_MISSES.STLB_HIT_2M .Pq Event 08H , Umask 40H Load misses that missed DTLB but hit STLB (2M). .It Li DTLB_LOAD_MISSES.STLB_HIT .Pq Event 08H , Umask 60H Number of cache load STLB hits. No page walk. .It Li DTLB_LOAD_MISSES.PDE_CACHE_MISS .Pq Event 08H , Umask 80H DTLB demand load misses with low part of linear-to- physical address translation missed .It Li INT_MISC.RECOVERY_CYCLES .Pq Event 0DH , Umask 03H Cycles waiting to recover after Machine Clears except JEClear. Set Cmask= 1. .It Li UOPS_ISSUED.ANY .Pq Event 0EH , Umask 01H ncrements each cycle the # of Uops issued by the RAT to RS. Set Cmask = 1, Inv = 1, Any= 1to count stalled cycles of this core. .It Li UOPS_ISSUED.FLAGS_MERGE .Pq Event 0EH , Umask 10H Number of flags-merge uops allocated. Such uops adds delay. .It Li UOPS_ISSUED.SLOW_LEA .Pq Event 0EH , Umask 20H Number of slow LEA or similar uops allocated. Such uop has 3 sources (e.g. 2 sources + immediate) regardless if as a result of LEA instruction or not. .It Li UOPS_ISSUED.SiNGLE_MUL .Pq Event 0EH , Umask 40H Number of multiply packed/scalar single precision uops allocated. .It Li L2_RQSTS.DEMAND_DATA_RD_MISS .Pq Event 24H , Umask 21H Demand Data Read requests that missed L2, no rejects. .It Li L2_RQSTS.DEMAND_DATA_RD_HIT .Pq Event 24H , Umask 41H Demand Data Read requests that hit L2 cache. .It Li L2_RQSTS.ALL_DEMAND_DATA_RD .Pq Event 24H , Umask E1H Counts any demand and L1 HW prefetch data load requests to L2. .It Li L2_RQSTS.RFO_HIT .Pq Event 24H , Umask 42H Counts the number of store RFO requests that hit the L2 cache. .It Li L2_RQSTS.RFO_MISS .Pq Event 24H , Umask 22H Counts the number of store RFO requests that miss the L2 cache. .It Li L2_RQSTS.ALL_RFO .Pq Event 24H , Umask E2H Counts all L2 store RFO requests. .It Li L2_RQSTS.CODE_RD_HIT .Pq Event 24H , Umask 44H Number of instruction fetches that hit the L2 cache. .It Li L2_RQSTS.CODE_RD_MISS .Pq Event 24H , Umask 24H Number of instruction fetches that missed the L2 cache. .It Li L2_RQSTS.ALL_DEMAND_MISS .Pq Event 24H , Umask 27H Demand requests that miss L2 cache. .It Li L2_RQSTS.ALL_DEMAND_REFERENCES .Pq Event 24H , Umask E7H Demand requests to L2 cache. .It Li L2_RQSTS.ALL_CODE_RD .Pq Event 24H , Umask E4H Counts all L2 code requests. .It Li L2_RQSTS.L2_PF_HIT .Pq Event 24H , Umask 50H Counts all L2 HW prefetcher requests that hit L2. .It Li L2_RQSTS.L2_PF_MISS .Pq Event 24H , Umask 30H Counts all L2 HW prefetcher requests that missed L2. .It Li L2_RQSTS.ALL_PF .Pq Event 24H , Umask F8H Counts all L2 HW prefetcher requests. .It Li L2_RQSTS.MISS .Pq Event 24H , Umask 3FH All requests that missed L2. .It Li L2_RQSTS.REFERENCES .Pq Event 24H , Umask FFH All requests to L2 cache. .It Li L2_DEMAND_RQSTS.WB_HIT .Pq Event 27H , Umask 50H Not rejected writebacks that hit L2 cache .It Li LONGEST_LAT_CACHE.REFERENCE .Pq Event 2EH , Umask 4FH This event counts requests originating from the core that reference a cache line in the last level cache. .It Li LONGEST_LAT_CACHE.MISS .Pq Event 2EH , Umask 41H This event counts each cache miss condition for references to the last level cache. .It Li CPU_CLK_UNHALTED.THREAD_P .Pq Event 3CH , Umask 00H Counts the number of thread cycles while the thread is not in a halt state. The thread enters the halt state when it is running the HLT instruction. The core frequency may change from time to time due to power or thermal throttling. .It Li CPU_CLK_THREAD_UNHALTED.REF_XCLK .Pq Event 3CH , Umask 01H Increments at the frequency of XCLK (100 MHz) when not halted. .It Li L1D_PEND_MISS.PENDING .Pq Event 48H , Umask 01H Increments the number of outstanding L1D misses every cycle. Set Cmaks = 1 and Edge =1 to count occurrences. .It Li DTLB_STORE_MISSES.MISS_CAUSES_A_WALK .Pq Event 49H , Umask 01H Miss in all TLB levels causes an page walk of any page size (4K/2M/4M/1G). .It Li DTLB_STORE_MISSES.WALK_COMPLETED_4K .Pq Event 49H , Umask 02H Completed page walks due to store misses in one or more TLB levels of 4K page structure. .It Li DTLB_STORE_MISSES.WALK_COMPLETED_2M_4M .Pq Event 49H , Umask 04H Completed page walks due to store misses in one or more TLB levels of 2M/4M page structure. .It Li DTLB_STORE_MISSES.WALK_COMPLETED .Pq Event 49H , Umask 0EH Completed page walks due to store miss in any TLB levels of any page size (4K/2M/4M/1G). .It Li DTLB_STORE_MISSES.WALK_DURATION .Pq Event 49H , Umask 10H Cycles PMH is busy with this walk. .It Li DTLB_STORE_MISSES.STLB_HIT_4K .Pq Event 49H , Umask 20H Store misses that missed DTLB but hit STLB (4K). .It Li DTLB_STORE_MISSES.STLB_HIT_2M .Pq Event 49H , Umask 40H Store misses that missed DTLB but hit STLB (2M). .It Li DTLB_STORE_MISSES.STLB_HIT .Pq Event 49H , Umask 60H Store operations that miss the first TLB level but hit the second and do not cause page walks. .It Li DTLB_STORE_MISSES.PDE_CACHE_MISS .Pq Event 49H , Umask 80H DTLB store misses with low part of linear-to-physical address translation missed. .It Li LOAD_HIT_PRE.SW_PF .Pq Event 4CH , Umask 01H Non-SW-prefetch load dispatches that hit fill buffer allocated for S/W prefetch. .It Li LOAD_HIT_PRE.HW_PF .Pq Event 4CH , Umask 02H Non-SW-prefetch load dispatches that hit fill buffer allocated for H/W prefetch. .It Li L1D.REPLACEMENT .Pq Event 51H , Umask 01H Counts the number of lines brought into the L1 data cache. .It Li MOVE_ELIMINATION.INT_NOT_ELIMINATED .Pq Event 58H , Umask 04H Number of integer Move Elimination candidate uops that were not eliminated. .It Li MOVE_ELIMINATION.SMID_NOT_ELIMINATED .Pq Event 58H , Umask 08H Number of SIMD Move Elimination candidate uops that were not eliminated. .It Li MOVE_ELIMINATION.INT_ELIMINATED .Pq Event 58H , Umask 01H Unhalted core cycles when the thread is in ring 0. .It Li MOVE_ELIMINATION.SMID_ELIMINATED .Pq Event 58H , Umask 02H Number of SIMD Move Elimination candidate uops that were eliminated. .It Li CPL_CYCLES.RING0 .Pq Event 5CH , Umask 02H Unhalted core cycles when the thread is in ring 0. .It Li CPL_CYCLES.RING123 .Pq Event 5CH , Umask 01H Unhalted core cycles when the thread is not in ring 0. .It Li RS_EVENTS.EMPTY_CYCLES .Pq Event 5EH , Umask 01H Cycles the RS is empty for the thread. .It Li OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD .Pq Event 60H , Umask 01H Offcore outstanding Demand Data Read transactions in SQ to uncore. Set Cmask=1 to count cycles. .It Li OFFCORE_REQUESTS_OUTSTANDING.DEMAND_CORE_RD .Pq Event 60H , Umask 02H Offcore outstanding Demand code Read transactions in SQ to uncore. Set Cmask=1 to count cycles. .It Li OFFCORE_REQUESTS_OUTSTANDING.DEMAND_RFO .Pq Event 60H , Umask 04H Offcore outstanding RFO store transactions in SQ to uncore. Set Cmask=1 to count cycles. .It Li OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD .Pq Event 60H , Umask 08H Offcore outstanding cacheable data read transactions in SQ to uncore. Set Cmask=1 to count cycles. .It Li LOCK_CYCLES.SPLIT_LOCK_UC_LOCK_DURATION .Pq Event 63H , Umask 01H Cycles in which the L1D and L2 are locked, due to a UC lock or split lock. .It Li LOCK_CYCLES.CACHE_LOCK_DURATION .Pq Event 63H , Umask 02H Cycles in which the L1D is locked. .It Li IDQ.EMPTY .Pq Event 79H , Umask 02H Counts cycles the IDQ is empty. .It Li IDQ.MITE_UOPS .Pq Event 79H , Umask 04H Increment each cycle # of uops delivered to IDQ from MITE path. Set Cmask = 1 to count cycles. .It Li IDQ.DSB_UOPS .Pq Event 79H , Umask 08H Increment each cycle. # of uops delivered to IDQ from DSB path. Set Cmask = 1 to count cycles. .It Li IDQ.MS_DSB_UOPS .Pq Event 79H , Umask 10H Increment each cycle # of uops delivered to IDQ when MS_busy by DSB. Set Cmask = 1 to count cycles. Add Edge=1 to count # of delivery. .It Li IDQ.MS_MITE_UOPS .Pq Event 79H , Umask 20H ncrement each cycle # of uops delivered to IDQ when MS_busy by MITE. Set Cmask = 1 to count cycles. .It Li IDQ.MS_UOPS .Pq Event 79H , Umask 30H Increment each cycle # of uops delivered to IDQ from MS by either DSB or MITE. Set Cmask = 1 to count cycles. .It Li IDQ.ALL_DSB_CYCLES_ANY_UOPS .Pq Event 79H , Umask 18H Counts cycles DSB is delivered at least one uops. Set Cmask = 1. .It Li IDQ.ALL_DSB_CYCLES_4_UOPS .Pq Event 79H , Umask 18H Counts cycles DSB is delivered four uops. Set Cmask =4. .It Li IDQ.ALL_MITE_CYCLES_ANY_UOPS .Pq Event 79H , Umask 24H Counts cycles MITE is delivered at least one uops. Set Cmask = 1. .It Li IDQ.ALL_MITE_CYCLES_4_UOPS .Pq Event 79H , Umask 24H Counts cycles MITE is delivered four uops. Set Cmask =4. .It Li IDQ.MITE_ALL_UOPS .Pq Event 79H , Umask 3CH # of uops delivered to IDQ from any path. .It Li ICACHE.MISSES .Pq Event 80H , Umask 02H Number of Instruction Cache, Streaming Buffer and Victim Cache Misses. Includes UC accesses. .It Li ITLB_MISSES.MISS_CAUSES_A_WALK .Pq Event 85H , Umask 01H Misses in ITLB that causes a page walk of any page size. .It Li ITLB_MISSES.WALK_COMPLETED_4K .Pq Event 85H , Umask 02H Completed page walks due to misses in ITLB 4K page entries. .It Li TLB_MISSES.WALK_COMPLETED_2M_4M .Pq Event 85H , Umask 04H Completed page walks due to misses in ITLB 2M/4M page entries. .It Li ITLB_MISSES.WALK_COMPLETED .Pq Event 85H , Umask 0EH Completed page walks in ITLB of any page size. .It Li ITLB_MISSES.WALK_DURATION .Pq Event 85H , Umask 10H Cycle PMH is busy with a walk. .It Li ITLB_MISSES.STLB_HIT_4K .Pq Event 85H , Umask 20H ITLB misses that hit STLB (4K). .It Li ITLB_MISSES.STLB_HIT_2M .Pq Event 85H , Umask 40H ITLB misses that hit STLB (2K). .It Li ITLB_MISSES.STLB_HIT .Pq Event 85H , Umask 60H TLB misses that hit STLB. No page walk. .It Li ILD_STALL.LCP .Pq Event 87H , Umask 01H Stalls caused by changing prefix length of the instruction. .It Li ILD_STALL.IQ_FULL .Pq Event 87H , Umask 04H Stall cycles due to IQ is full. -.It Li BR_INST_EXEC.COND -.Pq Event 88H , Umask 01H -Qualify conditional near branch instructions -executed, but not necessarily retired. +.It Li BR_INST_EXEC.NONTAKEN_COND +.Pq Event 88H , Umask 41H +Count conditional near branch instructions that were executed (but not +necessarily retired) and not taken. +.It Li BR_INST_EXEC.TAKEN_COND +.Pq Event 88H , Umask 81H +Count conditional near branch instructions that were executed (but not +necessarily retired) and taken. .It Li BR_INST_EXEC.DIRECT_JMP -.Pq Event 88H , Umask 02H -Qualify all unconditional near branch instructions -excluding calls and indirect branches. +.Pq Event 88H , Umask 82H +Count all unconditional near branch instructions excluding calls and +indirect branches. .It Li BR_INST_EXEC.INDIRECT_JMP_NON_CALL_RET -.Pq Event 88H , Umask 04H -Qualify executed indirect near branch instructions -that are not calls nor returns. +.Pq Event 88H , Umask 84H +Count executed indirect near branch instructions that are not calls nor +returns. .It Li BR_INST_EXEC.RETURN_NEAR -.Pq Event 88H , Umask 08H -Qualify indirect near branches that have a return -mnemonic. +.Pq Event 88H , Umask 88H +Count indirect near branches that have a return mnemonic. .It Li BR_INST_EXEC.DIRECT_NEAR_CALL -.Pq Event 88H , Umask 10H -Qualify unconditional near call branch instructions, -excluding non call branch, executed. +.Pq Event 88H , Umask 90H +Count unconditional near call branch instructions, excluding non call +branch, executed. .It Li BR_INST_EXEC.INDIRECT_NEAR_CALL -.Pq Event 88H , Umask 20H -Qualify indirect near calls, including both register and -memory indirect, executed. -.It Li BR_INST_EXEC.NONTAKEN -.Pq Event 88H , Umask 40H -Qualify non-taken near branches executed. -.It Li BR_INST_EXEC.TAKEN -.Pq Event 88H , Umask 80H -Qualify taken near branches executed. Must combine -with 01H,02H, 04H, 08H, 10H, 20H. +.Pq Event 88H , Umask A0H +Count indirect near calls, including both register and memory indirect, +executed. .It Li BR_INST_EXEC.ALL_BRANCHES .Pq Event 88H , Umask FFH -Counts all near executed branches (not necessarily -retired). -.It Li BR_MISP_EXEC.COND -.Pq Event 89H , Umask 01H -Qualify conditional near branch instructions -mispredicted. +Counts all near executed branches (not necessarily retired). +.It Li BR_MISP_EXEC.NONTAKEN_COND +.Pq Event 89H , Umask 41H +Count conditional near branch instructions mispredicted as nontaken. +.It Li BR_MISP_EXEC.TAKEN_COND +.Pq Event 89H , Umask 81H +Count conditional near branch instructions mispredicted as taken. .It Li BR_MISP_EXEC.INDIRECT_JMP_NON_CALL_RET -.Pq Event 89H , Umask 04H -Qualify mispredicted indirect near branch -instructions that are not calls nor returns. +.Pq Event 89H , Umask 84H +Count mispredicted indirect near branch instructions that are not calls +nor returns. .It Li BR_MISP_EXEC.RETURN_NEAR -.Pq Event 89H , Umask 08H -Qualify mispredicted indirect near branches that -have a return mnemonic. +.Pq Event 89H , Umask 88H +Count mispredicted indirect near branches that have a return mnemonic. .It Li BR_MISP_EXEC.DIRECT_NEAR_CALL -.Pq Event 89H , Umask 10H -Qualify mispredicted unconditional near call branch -instructions, excluding non call branch, executed. +.Pq Event 89H , Umask 90H +Count mispredicted unconditional near call branch instructions, excluding +non call branch, executed. .It Li BR_MISP_EXEC.INDIRECT_NEAR_CALL -.Pq Event 89H , Umask 20H -Qualify mispredicted indirect near calls, including -both register and memory indirect, executed. -.It Li BR_MISP_EXEC.NONTAKEN -.Pq Event 89H , Umask 40H -Qualify mispredicted non-taken near branches -executed. -.It Li BR_MISP_EXEC.TAKEN -.Pq Event 89H , Umask 80H -Qualify mispredicted taken near branches executed. -Must combine with 01H,02H, 04H, 08H, 10H, 20H. +.Pq Event 89H , Umask A0H +Count mispredicted indirect near calls, including both register and memory +indirect, executed. .It Li BR_MISP_EXEC.ALL_BRANCHES .Pq Event 89H , Umask FFH -Counts all near executed branches (not necessarily -retired). +Counts all mispredicted near executed branches (not necessarily retired). .It Li IDQ_UOPS_NOT_DELIVERED.CORE .Pq Event 9CH , Umask 01H Count number of non-delivered uops to RAT per thread. .It Li UOPS_EXECUTED_PORT.PORT_0 .Pq Event A1H , Umask 01H Cycles which a Uop is dispatched on port 0 in this thread. .It Li UOPS_EXECUTED_PORT.PORT_1 .Pq Event A1H , Umask 02H Cycles which a Uop is dispatched on port 1 in this thread. .It Li UOPS_EXECUTED_PORT.PORT_2 .Pq Event A1H , Umask 04H Cycles which a Uop is dispatched on port 2 in this thread. .It Li UOPS_EXECUTED_PORT.PORT_3 .Pq Event A1H , Umask 08H Cycles which a Uop is dispatched on port 3 in this thread. .It Li UOPS_EXECUTED_PORT.PORT_4 .Pq Event A1H , Umask 10H Cycles which a Uop is dispatched on port 4 in this thread. .It Li UOPS_EXECUTED_PORT.PORT_5 .Pq Event A1H , Umask 20H Cycles which a Uop is dispatched on port 5 in this thread. .It Li UOPS_EXECUTED_PORT.PORT_6 .Pq Event A1H , Umask 40H Cycles which a Uop is dispatched on port 6 in this thread. .It Li UOPS_EXECUTED_PORT.PORT_7 .Pq Event A1H , Umask 80H Cycles which a Uop is dispatched on port 7 in this thread. .It Li RESOURCE_STALLS.ANY .Pq Event A2H , Umask 01H Cycles Allocation is stalled due to Resource Related reason. .It Li RESOURCE_STALLS.RS .Pq Event A2H , Umask 04H Cycles stalled due to no eligible RS entry available. .It Li RESOURCE_STALLS.SB .Pq Event A2H , Umask 08H Cycles stalled due to no store buffers available (not including draining form sync). .It Li RESOURCE_STALLS.ROB .Pq Event A2H , Umask 10H Cycles stalled due to re-order buffer full. .It Li CYCLE_ACTIVITY.CYCLES_L2_PENDING .Pq Event A3H , Umask 01H Cycles with pending L2 miss loads. Set Cmask=2 to count cycle. .It Li CYCLE_ACTIVITY.CYCLES_LDM_PENDING .Pq Event A3H , Umask 02H Cycles with pending memory loads. Set Cmask=2 to count cycle. .It Li CYCLE_ACTIVITY.STALLS_L2_PENDING .Pq Event A3H , Umask 05H Number of loads missed L2. .It Li CYCLE_ACTIVITY.CYCLES_L1D_PENDING .Pq Event A3H , Umask 08H Cycles with pending L1 cache miss loads. Set Cmask=8 to count cycle. .It Li ITLB.ITLB_FLUSH .Pq Event AEH , Umask 01H Counts the number of ITLB flushes, includes 4k/2M/4M pages. .It Li OFFCORE_REQUESTS.DEMAND_DATA_RD .Pq Event B0H , Umask 01H Demand data read requests sent to uncore. .It Li OFFCORE_REQUESTS.DEMAND_CODE_RD .Pq Event B0H , Umask 02H Demand code read requests sent to uncore. .It Li OFFCORE_REQUESTS.DEMAND_RFO .Pq Event B0H , Umask 04H Demand RFO read requests sent to uncore, including regular RFOs, locks, ItoM. .It Li OFFCORE_REQUESTS.ALL_DATA_RD .Pq Event B0H , Umask 08H Data read requests sent to uncore (demand and prefetch). .It Li UOPS_EXECUTED.CORE .Pq Event B1H , Umask 02H Counts total number of uops to be executed per-core each cycle. .It Li OFF_CORE_RESPONSE_0 .Pq Event B7H , Umask 01H Requires MSR 01A6H .It Li OFF_CORE_RESPONSE_1 .Pq Event BBH , Umask 01H Requires MSR 01A7H .It Li PAGE_WALKER_LOADS.DTLB_L1 .Pq Event BCH , Umask 11H Number of DTLB page walker loads that hit in the L1+FB. .It Li PAGE_WALKER_LOADS.ITLB_L1 .Pq Event BCH , Umask 21H Number of ITLB page walker loads that hit in the L1+FB. .It Li PAGE_WALKER_LOADS.DTLB_L2 .Pq Event BCH , Umask 12H Number of DTLB page walker loads that hit in the L2. .It Li PAGE_WALKER_LOADS.ITLB_L2 .Pq Event BCH , Umask 22H Number of ITLB page walker loads that hit in the L2. .It Li PAGE_WALKER_LOADS.DTLB_L3 .Pq Event BCH , Umask 14H Number of DTLB page walker loads that hit in the L3. .It Li PAGE_WALKER_LOADS.ITLB_L3 .Pq Event BCH , Umask 24H Number of ITLB page walker loads that hit in the L3. .It Li PAGE_WALKER_LOADS.DTLB_MEMORY .Pq Event BCH , Umask 18H Number of DTLB page walker loads from memory. .It Li PAGE_WALKER_LOADS.ITLB_MEMORY .Pq Event BCH , Umask 28H Number of ITLB page walker loads from memory. .It Li TLB_FLUSH.DTLB_THREAD .Pq Event BDH , Umask 01H DTLB flush attempts of the thread-specific entries. .It Li TLB_FLUSH.STLB_ANY .Pq Event BDH , Umask 20H Count number of STLB flush attempts. .It Li INST_RETIRED.ANY_P .Pq Event C0H , Umask 00H Number of instructions at retirement. .It Li INST_RETIRED.ALL .Pq Event C0H , Umask 01H Precise instruction retired event with HW to reduce effect of PEBS shadow in IP distribution. .It Li OTHER_ASSISTS.AVX_TO_SSE .Pq Event C1H , Umask 08H Number of transitions from AVX-256 to legacy SSE when penalty applicable. .It Li OTHER_ASSISTS.SSE_TO_AVX .Pq Event C1H , Umask 10H Number of transitions from SSE to AVX-256 when penalty applicable. .It Li OTHER_ASSISTS.ANY_WB_ASSIST .Pq Event C1H , Umask 40H Number of microcode assists invoked by HW upon uop writeback. .It Li UOPS_RETIRED.ALL .Pq Event C2H , Umask 01H Counts the number of micro-ops retired, Use cmask=1 and invert to count active cycles or stalled cycles. .It Li UOPS_RETIRED.RETIRE_SLOTS .Pq Event C2H , Umask 02H Counts the number of retirement slots used each cycle. .It Li MACHINE_CLEARS.MEMORY_ORDERING .Pq Event C3H , Umask 02H Counts the number of machine clears due to memory order conflicts. .It Li MACHINE_CLEARS.SMC .Pq Event C3H , Umask 04H Number of self-modifying-code machine clears detected. .It Li MACHINE_CLEARS.MASKMOV .Pq Event C3H , Umask 20H Counts the number of executed AVX masked load operations that refer to an illegal address range with the mask bits set to 0. .It Li BR_INST_RETIRED.ALL_BRANCHES .Pq Event C4H , Umask 00H Branch instructions at retirement. .It Li BR_INST_RETIRED.CONDITIONAL .Pq Event C4H , Umask 01H Counts the number of conditional branch instructions Supports PEBS retired. .It Li BR_INST_RETIRED.NEAR_CALL .Pq Event C4H , Umask 02H Direct and indirect near call instructions retired. .It Li BR_INST_RETIRED.ALL_BRANCHES .Pq Event C4H , Umask 04H Counts the number of branch instructions retired. .It Li BR_INST_RETIRED.NEAR_RETURN .Pq Event C4H , Umask 08H Counts the number of near return instructions retired. .It Li BR_INST_RETIRED.NOT_TAKEN .Pq Event C4H , Umask 10H Counts the number of not taken branch instructions retired. It Li BR_INST_RETIRED.NEAR_TAKEN .Pq Event C4H , Umask 20H Number of near taken branches retired. .It Li BR_INST_RETIRED.FAR_BRANCH .Pq Event C4H , Umask 40H Number of far branches retired. .It Li BR_MISP_RETIRED.ALL_BRANCHES .Pq Event C5H , Umask 00H Mispredicted branch instructions at retirement .It Li BR_MISP_RETIRED.CONDITIONAL .Pq Event C5H , Umask 01H Mispredicted conditional branch instructions retired. .It Li BR_MISP_RETIRED.CONDITIONAL .Pq Event C5H , Umask 04H Mispredicted macro branch instructions retired. .It Li FP_ASSIST.X87_OUTPUT .Pq Event CAH , Umask 02H Number of X87 FP assists due to Output values. .It Li FP_ASSIST.X87_INPUT .Pq Event CAH , Umask 04H Number of X87 FP assists due to input values. .It Li FP_ASSIST.SIMD_OUTPUT .Pq Event CAH , Umask 08H Number of SIMD FP assists due to Output values. .It Li FP_ASSIST.SIMD_INPUT .Pq Event CAH , Umask 10H Number of SIMD FP assists due to input values. .It Li FP_ASSIST.ANY .Pq Event CAH , Umask 1EH Cycles with any input/output SSE* or FP assists. .It Li ROB_MISC_EVENTS.LBR_INSERTS .Pq Event CCH , Umask 20H Count cases of saving new LBR records by hardware. .It Li MEM_TRANS_RETIRED.LOAD_LATENCY .Pq Event CDH , Umask 01H Randomly sampled loads whose latency is above a user defined threshold. A small fraction of the overall loads are sampled due to randomization. .It Li MEM_UOP_RETIRED.LOADS .Pq Event D0H , Umask 01H Qualify retired memory uops that are loads. Combine Supports PEBS and with umask 10H, 20H, 40H, 80H. .It Li MEM_UOP_RETIRED.STORES .Pq Event D0H , Umask 02H Qualify retired memory uops that are stores. Combine with umask 10H, 20H, 40H, 80H. .It Li MEM_UOP_RETIRED.STLB_MISS .Pq Event D0H , Umask 10H Qualify retired memory uops with STLB miss. Must combine with umask 01H, 02H, to produce counts. .It Li MEM_UOP_RETIRED.LOCK .Pq Event D0H , Umask 20H Qualify retired memory uops with lock. Must combine Supports PEBS and with umask 01H, 02H, to produce counts. .It Li MEM_UOP_RETIRED.SPLIT .Pq Event D0H , Umask 40H Qualify retired memory uops with line split. Must combine with umask 01H, 02H, to produce counts. .It Li MEM_UOP_RETIRED.ALL .Pq Event D0H , Umask 80H Qualify any retired memory uops. Must combine with Supports PEBS and umask 01H, 02H, to produce counts. .It Li MEM_LOAD_UOPS_RETIRED.L1_HIT .Pq Event D1H , Umask 01H Retired load uops with L1 cache hits as data sources. .It Li MEM_LOAD_UOPS_RETIRED.L2_HIT .Pq Event D1H , Umask 02H Retired load uops with L2 cache hits as data sources. .It Li MEM_LOAD_UOPS_RETIRED.LLC_HIT .Pq Event D1H , Umask 04H Retired load uops with LLC cache hits as data sources. .It Li MEM_LOAD_UOPS_RETIRED.L2_MISS .Pq Event D1H , Umask 10H Retired load uops missed L2. Unknown data source excluded. .It Li MEM_LOAD_UOPS_RETIRED.HIT_LFB .Pq Event D1H , Umask 40H Retired load uops which data sources were load uops missed L1 but hit FB due to preceding miss to the same cache line with data not ready. .It Li MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_MISS .Pq Event D2H , Umask 01H Retired load uops which data sources were LLC hit and cross-core snoop missed in on-pkg core cache. .It Li MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HIT .Pq Event D2H , Umask 02H Retired load uops which data sources were LLC and cross-core snoop hits in on-pkg core cache. .It Li MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HITM .Pq Event D2H , Umask 04H Retired load uops which data sources were HitM responses from shared LLC. .It Li MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_NONE .Pq Event D2H , Umask 08H Retired load uops which data sources were hits in LLC without snoops required. .It Li MEM_LOAD_UOPS_LLC_MISS_RETIRED.LOCAL_DRAM .Pq Event D3H , Umask 01H Retired load uops which data sources missed LLC but serviced from local dram. .It Li BACLEARS.ANY .Pq Event E6H , Umask 1FH Number of front end re-steers due to BPU misprediction. .It Li L2_TRANS.DEMAND_DATA_RD .Pq Event F0H , Umask 01H Demand Data Read requests that access L2 cache. .It Li L2_TRANS.RFO .Pq Event F0H , Umask 02H RFO requests that access L2 cache. .It Li L2_TRANS.CODE_RD .Pq Event F0H , Umask 04H L2 cache accesses when fetching instructions. .It Li L2_TRANS.ALL_PF .Pq Event F0H , Umask 08H Any MLC or LLC HW prefetch accessing L2, including rejects. .It Li L2_TRANS.L1D_WB .Pq Event F0H , Umask 10H L1D writebacks that access L2 cache. .It Li L2_TRANS.L2_FILL .Pq Event F0H , Umask 20H L2 fill requests that access L2 cache. .It Li L2_TRANS.L2_WB .Pq Event F0H , Umask 40H L2 writebacks that access L2 cache. .It Li L2_TRANS.ALL_REQUESTS .Pq Event F0H , Umask 80H Transactions accessing L2 pipe. .It Li L2_LINES_IN.I .Pq Event F1H , Umask 01H L2 cache lines in I state filling L2. .It Li L2_LINES_IN.S .Pq Event F1H , Umask 02H L2 cache lines in S state filling L2. .It Li L2_LINES_IN.E .Pq Event F1H , Umask 04H L2 cache lines in E state filling L2. .It Li L2_LINES_IN.ALL .Pq Event F1H , Umask 07H L2 cache lines filling L2. .It Li L2_LINES_OUT.DEMAND_CLEAN .Pq Event F2H , Umask 05H Clean L2 cache lines evicted by demand. .It Li L2_LINES_OUT.DEMAND_DIRTY .Pq Event F2H , Umask 06H Dirty L2 cache lines evicted by demand. .El .Sh SEE ALSO .Xr pmc 3 , .Xr pmc.atom 3 , .Xr pmc.core 3 , .Xr pmc.iaf 3 , .Xr pmc.ucf 3 , .Xr pmc.k7 3 , .Xr pmc.k8 3 , .Xr pmc.p4 3 , .Xr pmc.p5 3 , .Xr pmc.p6 3 , .Xr pmc.corei7 3 , .Xr pmc.corei7uc 3 , .Xr pmc.haswell 3 , .Xr pmc.haswelluc 3 , .Xr pmc.ivybridge 3 , .Xr pmc.ivybridgexeon 3 , .Xr pmc.sandybridge 3 , .Xr pmc.sandybridgeuc 3 , .Xr pmc.sandybridgexeon 3 , .Xr pmc.westmere 3 , .Xr pmc.westmereuc 3 , .Xr pmc.soft 3 , .Xr pmc.tsc 3 , .Xr pmc_cpuinfo 3 , .Xr pmclog 3 , .Xr hwpmc 4 .Sh HISTORY Support for the Haswell Xeon microarchitecture first appeared in .Fx 10.2 . .Sh AUTHORS The .Lb libpmc library was written by .An "Joseph Koshy" .Aq jkoshy@FreeBSD.org . The support for the Haswell Xeon microarchitecture was written by .An "Randall Stewart" .Aq rrs@FreeBSD.org . Index: stable/10/lib/libpmc/pmc.ivybridge.3 =================================================================== --- stable/10/lib/libpmc/pmc.ivybridge.3 (revision 320105) +++ stable/10/lib/libpmc/pmc.ivybridge.3 (revision 320106) @@ -1,881 +1,861 @@ .\" Copyright (c) 2012 Fabien Thomas. All rights reserved. .\" .\" Redistribution and use in source and binary forms, with or without .\" modification, are permitted provided that the following conditions .\" are met: .\" 1. Redistributions of source code must retain the above copyright .\" notice, this list of conditions and the following disclaimer. .\" 2. Redistributions in binary form must reproduce the above copyright .\" notice, this list of conditions and the following disclaimer in the .\" documentation and/or other materials provided with the distribution. .\" .\" THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND .\" ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE .\" IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE .\" ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE .\" FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL .\" DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS .\" OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) .\" HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT .\" LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY .\" OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF .\" SUCH DAMAGE. .\" .\" $FreeBSD$ .\" .Dd October 19, 2012 .Dt PMC.IVYBRIDGE 3 .Os .Sh NAME .Nm pmc.ivybridge .Nd measurement events for .Tn Intel .Tn Ivy Bridge family CPUs .Sh LIBRARY .Lb libpmc .Sh SYNOPSIS .In pmc.h .Sh DESCRIPTION .Tn Intel .Tn "Ivy Bridge" CPUs contain PMCs conforming to version 2 of the .Tn Intel performance measurement architecture. These CPUs may contain up to three classes of PMCs: .Bl -tag -width "Li PMC_CLASS_IAP" .It Li PMC_CLASS_IAF Fixed-function counters that count only one hardware event per counter. .It Li PMC_CLASS_IAP Programmable counters that may be configured to count one of a defined set of hardware events. .El .Pp The number of PMCs available in each class and their widths need to be determined at run time by calling .Xr pmc_cpuinfo 3 . .Pp Intel Ivy Bridge PMCs are documented in .Rs .%B "Intel(R) 64 and IA-32 Architectures Software Developer's Manual" .%T "Volume 3B: System Programming Guide, Part 2" .%N "Order Number: 253669-043US" .%D May 2012 .%Q "Intel Corporation" .Re .Ss IVYBRIDGE FIXED FUNCTION PMCS These PMCs and their supported events are documented in .Xr pmc.iaf 3 . .Ss IVYBRIDGE PROGRAMMABLE PMCS The programmable PMCs support the following capabilities: .Bl -column "PMC_CAP_INTERRUPT" "Support" .It Em Capability Ta Em Support .It PMC_CAP_CASCADE Ta \&No .It PMC_CAP_EDGE Ta Yes .It PMC_CAP_INTERRUPT Ta Yes .It PMC_CAP_INVERT Ta Yes .It PMC_CAP_READ Ta Yes .It PMC_CAP_PRECISE Ta \&No .It PMC_CAP_SYSTEM Ta Yes .It PMC_CAP_TAGGING Ta \&No .It PMC_CAP_THRESHOLD Ta Yes .It PMC_CAP_USER Ta Yes .It PMC_CAP_WRITE Ta Yes .El .Ss Event Qualifiers Event specifiers for these PMCs support the following common qualifiers: .Bl -tag -width indent .It Li rsp= Ns Ar value Configure the Off-core Response bits. .Bl -tag -width indent .It Li REQ_DMND_DATA_RD Counts the number of demand and DCU prefetch data reads of full and partial cachelines as well as demand data page table entry cacheline reads. Does not count L2 data read prefetches or instruction fetches. .It Li REQ_DMND_RFO Counts the number of demand and DCU prefetch reads for ownership (RFO) requests generated by a write to data cacheline. Does not count L2 RFO prefetches. .It Li REQ_DMND_IFETCH Counts the number of demand and DCU prefetch instruction cacheline reads. Does not count L2 code read prefetches. .It Li REQ_WB Counts the number of writeback (modified to exclusive) transactions. .It Li REQ_PF_DATA_RD Counts the number of data cacheline reads generated by L2 prefetchers. .It Li REQ_PF_RFO Counts the number of RFO requests generated by L2 prefetchers. .It Li REQ_PF_IFETCH Counts the number of code reads generated by L2 prefetchers. .It Li REQ_PF_LLC_DATA_RD L2 prefetcher to L3 for loads. .It Li REQ_PF_LLC_RFO RFO requests generated by L2 prefetcher .It Li REQ_PF_LLC_IFETCH L2 prefetcher to L3 for instruction fetches. .It Li REQ_BUS_LOCKS Bus lock and split lock requests. .It Li REQ_STRM_ST Streaming store requests. .It Li REQ_OTHER Any other request that crosses IDI, including I/O. .It Li RES_ANY Catch all value for any response types. .It Li RES_SUPPLIER_NO_SUPP No Supplier Information available. .It Li RES_SUPPLIER_LLC_HITM M-state initial lookup stat in L3. .It Li RES_SUPPLIER_LLC_HITE E-state. .It Li RES_SUPPLIER_LLC_HITS S-state. .It Li RES_SUPPLIER_LLC_HITF F-state. .It Li RES_SUPPLIER_LOCAL Local DRAM Controller. .It Li RES_SNOOP_SNP_NONE No details on snoop-related information. .It Li RES_SNOOP_SNP_NO_NEEDED No snoop was needed to satisfy the request. .It Li RES_SNOOP_SNP_MISS A snoop was needed and it missed all snooped caches: -For LLC Hit, ReslHitl was returned by all cores -For LLC Miss, Rspl was returned by all sockets and data was returned from DRAM. .It Li RES_SNOOP_HIT_NO_FWD A snoop was needed and it hits in at least one snooped cache. Hit denotes a cache-line was valid before snoop effect. This includes: -Snoop Hit w/ Invalidation (LLC Hit, RFO) -Snoop Hit, Left Shared (LLC Hit/Miss, IFetch/Data_RD) -Snoop Hit w/ Invalidation and No Forward (LLC Miss, RFO Hit S) In the LLC Miss case, data is returned from DRAM. .It Li RES_SNOOP_HIT_FWD A snoop was needed and data was forwarded from a remote socket. This includes: -Snoop Forward Clean, Left Shared (LLC Hit/Miss, IFetch/Data_RD/RFT). .It Li RES_SNOOP_HITM A snoop was needed and it HitM-ed in local or remote cache. HitM denotes a cache-line was in modified state before effect as a results of snoop. This includes: -Snoop HitM w/ WB (LLC miss, IFetch/Data_RD) -Snoop Forward Modified w/ Invalidation (LLC Hit/Miss, RFO) -Snoop MtoS (LLC Hit, IFetch/Data_RD). .It Li RES_NON_DRAM Target was non-DRAM system address. This includes MMIO transactions. .El .It Li cmask= Ns Ar value Configure the PMC to increment only if the number of configured events measured in a cycle is greater than or equal to .Ar value . .It Li edge Configure the PMC to count the number of de-asserted to asserted transitions of the conditions expressed by the other qualifiers. If specified, the counter will increment only once whenever a condition becomes true, irrespective of the number of clocks during which the condition remains true. .It Li inv Invert the sense of comparison when the .Dq Li cmask qualifier is present, making the counter increment when the number of events per cycle is less than the value specified by the .Dq Li cmask qualifier. .It Li os Configure the PMC to count events happening at processor privilege level 0. .It Li usr Configure the PMC to count events occurring at privilege levels 1, 2 or 3. .El .Pp If neither of the .Dq Li os or .Dq Li usr qualifiers are specified, the default is to enable both. .Ss Event Specifiers (Programmable PMCs) Ivy Bridge programmable PMCs support the following events: .Bl -tag -width indent .It Li LD_BLOCKS.STORE_FORWARD .Pq Event 03H , Umask 02H loads blocked by overlapping with store buffer that cannot be forwarded . .It Li MISALIGN_MEM_REF.LOADS .Pq Event 05H , Umask 01H Speculative cache-line split load uops dispatched to L1D. .It Li MISALIGN_MEM_REF.STORES .Pq Event 05H , Umask 02H Speculative cache-line split Store- address uops dispatched to L1D. .It Li LD_BLOCKS_PARTIAL.ADDRESS_ALIAS .Pq Event 07H , Umask 01H False dependencies in MOB due to partial compare on address. .It Li DTLB_LOAD_MISSES.DEMAND_LD_MISS_CAUSES_A_WALK .Pq Event 08H , Umask 81H Misses in all TLB levels that cause a page walk of any page size from demand loads. .It Li DTLB_LOAD_MISSES.DEMAND_LD_WALK_COMPLETED .Pq Event 08H , Umask 82H Misses in all TLB levels that caused page walk completed of any size by demand loads. .It Li DTLB_LOAD_MISSES.DEMAND_LD_WALK_DURATION .Pq Event 08H , Umask 84H Cycle PMH is busy with a walk due to demand loads. .It Li UOPS_ISSUED.ANY .Pq Event 0EH , Umask 01H Increments each cycle the # of Uops issued by the RAT to RS. Set Cmask = 1, Inv = 1to count stalled cycles. Set Cmask = 1, Inv = 1, Any= 1to count stalled cycles of this core. .It Li UOPS_ISSUED.FLAGS_MERGE .Pq Event 0EH , Umask 10H Number of flags-merge uops allocated. Such uops adds delay. .It Li UOPS_ISSUED.SLOW_LEA .Pq Event 0EH , Umask 20H Number of slow LEA or similar uops allocated. Such uop has 3 sources (e.g. 2 sources + immediate) regardless if as a result of LEA instruction or not. .It Li UOPS_ISSUED.SINGLE_MUL .Pq Event 0EH , Umask 40H Number of multiply packed/scalar single precision uops allocated. .It Li ARITH.FPU_DIV_ACTIVE .Pq Event 14H , Umask 01H Cycles that the divider is active, includes INT and FP. Set 'edge =1, cmask=1' to count the number of divides. .It Li L2_RQSTS.DEMAND_DATA_RD_HIT .Pq Event 24H , Umask 01H Demand Data Read requests that hit L2 cache. .It Li L2_RQSTS.ALL_DEMAND_DATA_RD .Pq Event 24H , Umask 03H Counts any demand and L1 HW prefetch data load requests to L2. .It Li L2_RQSTS.RFO_HITS .Pq Event 24H , Umask 04H Counts the number of store RFO requests that hit the L2 cache. .It Li L2_RQSTS.RFO_MISS .Pq Event 24H , Umask 08H Counts the number of store RFO requests that miss the L2 cache. .It Li L2_RQSTS.ALL_RFO .Pq Event 24H , Umask 0CH Counts all L2 store RFO requests. .It Li L2_RQSTS.CODE_RD_HIT .Pq Event 24H , Umask 10H Number of instruction fetches that hit the L2 cache. .It Li L2_RQSTS.CODE_RD_MISS .Pq Event 24H , Umask 20H Number of instruction fetches that missed the L2 cache. .It Li L2_RQSTS.ALL_CODE_RD .Pq Event 24H , Umask 30H Counts all L2 code requests. .It Li L2_RQSTS.PF_HIT .Pq Event 24H , Umask 40H Counts all L2 HW prefetcher requests that hit L2. .It Li L2_RQSTS.PF_MISS .Pq Event 24H , Umask 80H Counts all L2 HW prefetcher requests that missed L2. .It Li L2_RQSTS.ALL_PF .Pq Event 24H , Umask C0H Counts all L2 HW prefetcher requests. .It Li L2_STORE_LOCK_RQSTS.MISS .Pq Event 27H , Umask 01H RFOs that miss cache lines. .It Li L2_STORE_LOCK_RQSTS.HIT_M .Pq Event 27H , Umask 08H RFOs that hit cache lines in M state. .It Li L2_STORE_LOCK_RQSTS.ALL .Pq Event 27H , Umask 0FH RFOs that access cache lines in any state. .It Li L2_L1D_WB_RQSTS.MISS .Pq Event 28H , Umask 01H Not rejected writebacks that missed LLC. .It Li L2_L1D_WB_RQSTS.HIT_E .Pq Event 28H , Umask 04H Not rejected writebacks from L1D to L2 cache lines in E state. .It Li L2_L1D_WB_RQSTS.HIT_M .Pq Event 28H , Umask 08H Not rejected writebacks from L1D to L2 cache lines in M state. .It Li L2_L1D_WB_RQSTS.ALL .Pq Event 28H , Umask 0FH Not rejected writebacks from L1D to L2 cache lines in any state. .It Li LONGEST_LAT_CACHE.REFERENCE .Pq Event 2EH , Umask 4FH This event counts requests originating from the core that reference a cache line in the last level cache. .It Li LONGEST_LAT_CACHE.MISS .Pq Event 2EH , Umask 41H This event counts each cache miss condition for references to the last level cache. .It Li CPU_CLK_UNHALTED.THREAD_P .Pq Event 3CH , Umask 00H Counts the number of thread cycles while the thread is not in a halt state. The thread enters the halt state when it is running the HLT instruction. The core frequency may change from time to time due to power or thermal throttling. .It Li CPU_CLK_THREAD_UNHALTED.REF_XCLK .Pq Event 3CH , Umask 01H Increments at the frequency of XCLK (100 MHz) when not halted. .It Li L1D_PEND_MISS.PENDING .Pq Event 48H , Umask 01H Increments the number of outstanding L1D misses every cycle. Set Cmaks = 1 and Edge =1 to count occurrences. Counter 2 only. Set Cmask = 1 to count cycles. .It Li DTLB_STORE_MISSES.MISS_CAUSES_A_WALK .Pq Event 49H , Umask 01H Miss in all TLB levels causes an page walk of any page size (4K/2M/4M/1G). .It Li DTLB_STORE_MISSES.WALK_COMPLETED .Pq Event 49H , Umask 02H Miss in all TLB levels causes a page walk that completes of any page size (4K/2M/4M/1G). .It Li DTLB_STORE_MISSES.WALK_DURATION .Pq Event 49H , Umask 04H Cycles PMH is busy with this walk. .It Li DTLB_STORE_MISSES.STLB_HIT .Pq Event 49H , Umask 10H Store operations that miss the first TLB level but hit the second and do not cause page walks. .It Li LOAD_HIT_PRE.SW_PF .Pq Event 4CH , Umask 01H Non-SW-prefetch load dispatches that hit fill buffer allocated for S/W prefetch. .It Li LOAD_HIT_PRE.HW_PF .Pq Event 4CH , Umask 02H Non-SW-prefetch load dispatches that hit fill buffer allocated for H/W prefetch. .It Li L1D.REPLACEMENT .Pq Event 51H , Umask 01H Counts the number of lines brought into the L1 data cache. .It Li MOVE_ELIMINATION.INT_NOT_ELIMINATED .Pq Event 58H , Umask 01H Number of integer Move Elimination candidate uops that were not eliminated. .It Li MOVE_ELIMINATION.SIMD_NOT_ELIMINATED .Pq Event 58H , Umask 02H Number of SIMD Move Elimination candidate uops that were not eliminated. .It Li MOVE_ELIMINATION.INT_ELIMINATED .Pq Event 58H , Umask 04H Number of integer Move Elimination candidate uops that were eliminated. .It Li MOVE_ELIMINATION.SIMD_ELIMINATED .Pq Event 58H , Umask 08H Number of SIMD Move Elimination candidate uops that were eliminated. .It Li CPL_CYCLES.RING0 .Pq Event 5CH , Umask 01H Unhalted core cycles when the thread is in ring 0. Use Edge to count transition. .It Li CPL_CYCLES.RING123 .Pq Event 5CH , Umask 02H Unhalted core cycles when the thread is not in ring 0. .It Li RS_EVENTS.EMPTY_CYCLES .Pq Event 5EH , Umask 01H Cycles the RS is empty for the thread. .It Li TLB_ACCESS.LOAD_STLB_HIT .Pq Event 5FH , Umask 01H Counts load operations that missed 1st level DTLB but hit the 2nd level. .It Li OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD .Pq Event 60H , Umask 01H Offcore outstanding Demand Data Read transactions in SQ to uncore. Set Cmask=1 to count cycles. .It Li OFFCORE_REQUESTS_OUTSTANDING.DEMAND_CODE_RD .Pq Event 60H , Umask 02H Offcore outstanding Demand Code Read transactions in SQ to uncore. Set Cmask=1 to count cycles. .It Li OFFCORE_REQUESTS_OUTSTANDING.DEMAND_RFO .Pq Event 60H , Umask 04H Offcore outstanding RFO store transactions in SQ to uncore. Set Cmask=1 to count cycles. .It Li OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD .Pq Event 60H , Umask 08H Offcore outstanding cacheable data read transactions in SQ to uncore. Set Cmask=1 to count cycles. .It Li LOCK_CYCLES.SPLIT_LOCK_UC_LOCK_DURATION .Pq Event 63H , Umask 01H Cycles in which the L1D and L2 are locked, due to a UC lock or split lock. .It Li LOCK_CYCLES.CACHE_LOCK_DURATION .Pq Event 63H , Umask 02H Cycles in which the L1D is locked. .It Li IDQ.EMPTY .Pq Event 79H , Umask 02H Counts cycles the IDQ is empty. .It Li IDQ.MITE_UOPS .Pq Event 79H , Umask 04H Increment each cycle # of uops delivered to IDQ from MITE path. Can combine Umask 04H and 20H. Set Cmask = 1 to count cycles. .It Li IDQ.DSB_UOPS .Pq Event 79H , Umask 08H Increment each cycle. # of uops delivered to IDQ from DSB path. Can combine Umask 08H and 10H Set Cmask = 1 to count cycles. .It Li IDQ.MS_DSB_UOPS .Pq Event 79H , Umask 10H Increment each cycle # of uops delivered to IDQ when MS_busy by DSB. Set Cmask = 1 to count cycles. Add Edge=1 to count # of delivery. Can combine Umask 04H, 08H. .It Li IDQ.MS_MITE_UOPS .Pq Event 79H , Umask 20H Increment each cycle # of uops delivered to IDQ when MS_busy by MITE. Set Cmask = 1 to count cycles. Can combine Umask 04H, 08H. .It Li IDQ.MS_UOPS .Pq Event 79H , Umask 30H Increment each cycle # of uops delivered to IDQ from MS by either DSB or MITE. Set Cmask = 1 to count cycles. Can combine Umask 04H, 08H. .It Li IDQ.ALL_DSB_CYCLES_ANY_UOPS .Pq Event 79H , Umask 18H Counts cycles DSB is delivered at least one uops. Set Cmask = 1. .It Li IDQ.ALL_DSB_CYCLES_4_UOPS .Pq Event 79H , Umask 18H Counts cycles DSB is delivered four uops. Set Cmask = 4. .It Li IDQ.ALL_MITE_CYCLES_ANY_UOPS .Pq Event 79H , Umask 24H Counts cycles MITE is delivered at least one uops. Set Cmask = 1. .It Li IDQ.ALL_MITE_CYCLES_4_UOPS .Pq Event 79H , Umask 24H Counts cycles MITE is delivered four uops. Set Cmask = 4. .It Li IDQ.MITE_ALL_UOPS .Pq Event 79H , Umask 3CH # of uops delivered to IDQ from any path. .It Li ICACHE.MISSES .Pq Event 80H , Umask 02H Number of Instruction Cache, Streaming Buffer and Victim Cache Misses. Includes UC accesses. .It Li ITLB_MISSES.MISS_CAUSES_A_WALK .Pq Event 85H , Umask 01H Misses in all ITLB levels that cause page walks. .It Li ITLB_MISSES.WALK_COMPLETED .Pq Event 85H , Umask 02H Misses in all ITLB levels that cause completed page walks. .It Li ITLB_MISSES.WALK_DURATION .Pq Event 85H , Umask 04H Cycle PMH is busy with a walk. .It Li ITLB_MISSES.STLB_HIT .Pq Event 85H , Umask 10H Number of cache load STLB hits. No page walk. .It Li ILD_STALL.LCP .Pq Event 87H , Umask 01H Stalls caused by changing prefix length of the instruction. .It Li ILD_STALL.IQ_FULL .Pq Event 87H , Umask 04H Stall cycles due to IQ is full. -.It Li BR_INST_EXEC.COND -.Pq Event 88H , Umask 01H -Qualify conditional near branch instructions executed, but not necessarily -retired. -Must combine with umask 40H, 80H. +.It Li BR_INST_EXEC.NONTAKEN_COND +.Pq Event 88H , Umask 41H +Count conditional near branch instructions that were executed (but not +necessarily retired) and not taken. +.It Li BR_INST_EXEC.TAKEN_COND +.Pq Event 88H , Umask 81H +Count conditional near branch instructions that were executed (but not +necessarily retired) and taken. .It Li BR_INST_EXEC.DIRECT_JMP -.Pq Event 88H , Umask 02H -Qualify all unconditional near branch instructions excluding calls and +.Pq Event 88H , Umask 82H +Count all unconditional near branch instructions excluding calls and indirect branches. -Must combine with umask 80H. .It Li BR_INST_EXEC.INDIRECT_JMP_NON_CALL_RET -.Pq Event 88H , Umask 04H -Qualify executed indirect near branch instructions that are not calls nor +.Pq Event 88H , Umask 84H +Count executed indirect near branch instructions that are not calls nor returns. -Must combine with umask 80H. .It Li BR_INST_EXEC.RETURN_NEAR -.Pq Event 88H , Umask 08H -Qualify indirect near branches that have a return mnemonic. -Must combine with umask 80H. +.Pq Event 88H , Umask 88H +Count indirect near branches that have a return mnemonic. .It Li BR_INST_EXEC.DIRECT_NEAR_CALL -.Pq Event 88H , Umask 10H -Qualify unconditional near call branch instructions, excluding non call +.Pq Event 88H , Umask 90H +Count unconditional near call branch instructions, excluding non call branch, executed. -Must combine with umask 80H. .It Li BR_INST_EXEC.INDIRECT_NEAR_CALL -.Pq Event 88H , Umask 20H -Qualify indirect near calls, including both register and memory indirect, +.Pq Event 88H , Umask A0H +Count indirect near calls, including both register and memory indirect, executed. -Must combine with umask 80H. -.It Li BR_INST_EXEC.NONTAKEN -.Pq Event 88H , Umask 40H -Qualify non-taken near branches executed. -Applicable to umask 01H only. -.It Li BR_INST_EXEC.TAKEN -.Pq Event 88H , Umask 80H -Qualify taken near branches executed. Must combine with 01H,02H, 04H, 08H, -10H, 20H. .It Li BR_INST_EXEC.ALL_BRANCHES .Pq Event 88H , Umask FFH Counts all near executed branches (not necessarily retired). -.It Li BR_MISP_EXEC.COND -.Pq Event 89H , Umask 01H -Qualify conditional near branch instructions mispredicted. -Must combine with umask 40H, 80H. +.It Li BR_MISP_EXEC.NONTAKEN_COND +.Pq Event 89H , Umask 41H +Count conditional near branch instructions mispredicted as nontaken. +.It Li BR_MISP_EXEC.TAKEN_COND +.Pq Event 89H , Umask 81H +Count conditional near branch instructions mispredicted as taken. .It Li BR_MISP_EXEC.INDIRECT_JMP_NON_CALL_RET -.Pq Event 89H , Umask 04H -Qualify mispredicted indirect near branch instructions that are not calls +.Pq Event 89H , Umask 84H +Count mispredicted indirect near branch instructions that are not calls nor returns. -Must combine with umask 80H. .It Li BR_MISP_EXEC.RETURN_NEAR -.Pq Event 89H , Umask 08H -Qualify mispredicted indirect near branches that have a return mnemonic. -Must combine with umask 80H. +.Pq Event 89H , Umask 88H +Count mispredicted indirect near branches that have a return mnemonic. .It Li BR_MISP_EXEC.DIRECT_NEAR_CALL -.Pq Event 89H , Umask 10H -Qualify mispredicted unconditional near call branch instructions, excluding +.Pq Event 89H , Umask 90H +Count mispredicted unconditional near call branch instructions, excluding non call branch, executed. -Must combine with umask 80H. .It Li BR_MISP_EXEC.INDIRECT_NEAR_CALL -.Pq Event 89H , Umask 20H -Qualify mispredicted indirect near calls, including both register and memory +.Pq Event 89H , Umask A0H +Count mispredicted indirect near calls, including both register and memory indirect, executed. -Must combine with umask 80H. -.It Li BR_MISP_EXEC.NONTAKEN -.Pq Event 89H , Umask 40H -Qualify mispredicted non-taken near branches executed. -Applicable to umask 01H only. -.It Li BR_MISP_EXEC.TAKEN -.Pq Event 89H , Umask 80H -Qualify mispredicted taken near branches executed. Must combine with -01H,02H, 04H, 08H, 10H, 20H. .It Li BR_MISP_EXEC.ALL_BRANCHES .Pq Event 89H , Umask FFH -Counts all near executed branches (not necessarily retired). +Counts all mispredicted near executed branches (not necessarily retired). .It Li IDQ_UOPS_NOT_DELIVERED.CORE .Pq Event 9CH , Umask 01H Count number of non-delivered uops to RAT per thread. Use Cmask to qualify uop b/w. .It Li UOPS_DISPATCHED_PORT.PORT_0 .Pq Event A1H , Umask 01H Cycles which a Uop is dispatched on port 0. .It Li UOPS_DISPATCHED_PORT.PORT_1 .Pq Event A1H , Umask 02H Cycles which a Uop is dispatched on port 1. .It Li UOPS_DISPATCHED_PORT.PORT_2_LD .Pq Event A1H , Umask 04H Cycles which a load uop is dispatched on port 2. .It Li UOPS_DISPATCHED_PORT.PORT_2_STA .Pq Event A1H , Umask 08H Cycles which a store address uop is dispatched on port 2. .It Li UOPS_DISPATCHED_PORT.PORT_2 .Pq Event A1H , Umask 0CH Cycles which a Uop is dispatched on port 2. .It Li UOPS_DISPATCHED_PORT.PORT_3_LD .Pq Event A1H , Umask 10H Cycles which a load uop is dispatched on port 3. .It Li UOPS_DISPATCHED_PORT.PORT_3_STA .Pq Event A1H , Umask 20H Cycles which a store address uop is dispatched on port 3. .It Li UOPS_DISPATCHED_PORT.PORT_3 .Pq Event A1H , Umask 30H Cycles which a Uop is dispatched on port 3. .It Li UOPS_DISPATCHED_PORT.PORT_4 .Pq Event A1H , Umask 40H Cycles which a Uop is dispatched on port 4. .It Li UOPS_DISPATCHED_PORT.PORT_5 .Pq Event A1H , Umask 80H Cycles which a Uop is dispatched on port 5. .It Li RESOURCE_STALLS.ANY .Pq Event A2H , Umask 01H Cycles Allocation is stalled due to Resource Related reason. .It Li RESOURCE_STALLS.RS .Pq Event A2H , Umask 04H Cycles stalled due to no eligible RS entry available. .It Li RESOURCE_STALLS.SB .Pq Event A2H , Umask 08H Cycles stalled due to no store buffers available. (not including draining form sync). .It Li RESOURCE_STALLS.ROB .Pq Event A2H , Umask 10H Cycles stalled due to re-order buffer full. .It Li DSB2MITE_SWITCHES.COUNT .Pq Event ABH , Umask 01H Number of DSB to MITE switches. .It Li DSB2MITE_SWITCHES.PENALTY_CYCLES .Pq Event ABH , Umask 02H Cycles DSB to MITE switches caused delay. .It Li DSB_FILL.EXCEED_DSB_LINES .Pq Event ACH , Umask 08H DSB Fill encountered > 3 DSB lines. .It Li ITLB.ITLB_FLUSH .Pq Event AEH , Umask 01H Counts the number of ITLB flushes, includes 4k/2M/4M pages. .It Li OFFCORE_REQUESTS.DEMAND_DATA_RD .Pq Event B0H , Umask 01H Demand data read requests sent to uncore. .It Li OFFCORE_REQUESTS.DEMAND_CODE_RD .Pq Event B0H , Umask 02H Demand code read requests sent to uncore. .It Li OFFCORE_REQUESTS.DEMAND_RFO .Pq Event B0H , Umask 04H Demand RFO read requests sent to uncore, including regular RFOs, locks, ItoM. .It Li OFFCORE_REQUESTS.ALL_DATA_RD .Pq Event B0H , Umask 08H Data read requests sent to uncore (demand and prefetch). .It Li UOPS_EXECUTED.THREAD .Pq Event B1H , Umask 01H Counts total number of uops to be executed per-thread each cycle. Set Cmask = 1, INV =1 to count stall cycles. .It Li UOPS_EXECUTED.CORE .Pq Event B1H , Umask 02H Counts total number of uops to be executed per-core each cycle. Do not need to set ANY. .It Li OFF_CORE_RESPONSE_0 .Pq Event B7H , Umask 01H Off-core Response Performance Monitoring. PMC0 only. Requires programming MSR 01A6H. .It Li OFF_CORE_RESPONSE_1 .Pq Event BBH , Umask 01H Off-core Response Performance Monitoring. PMC3 only. Requires programming MSR 01A7H. .It Li TLB_FLUSH.DTLB_THREAD .Pq Event BDH , Umask 01H DTLB flush attempts of the thread- specific entries. .It Li TLB_FLUSH.STLB_ANY .Pq Event BDH , Umask 20H Count number of STLB flush attempts. .It Li INST_RETIRED.ANY_P .Pq Event C0H , Umask 00H Number of instructions at retirement. .It Li INST_RETIRED.ALL .Pq Event C0H , Umask 01H Precise instruction retired event with HW to reduce effect of PEBS shadow in IP distribution. PMC1 only. Must quiesce other PMCs. .It Li OTHER_ASSISTS.AVX_STORE .Pq Event C1H , Umask 08H Number of assists associated with 256-bit AVX store operations. .It Li OTHER_ASSISTS.AVX_TO_SSE .Pq Event C1H , Umask 10H Number of transitions from AVX- 256 to legacy SSE when penalty applicable. .It Li OTHER_ASSISTS.SSE_TO_AVX .Pq Event C1H , Umask 20H Number of transitions from SSE to AVX-256 when penalty applicable. .It Li UOPS_RETIRED.ALL .Pq Event C2H , Umask 01H Counts the number of micro-ops retired, Use cmask=1 and invert to count active cycles or stalled cycles. Supports PEBS, use Any=1 for core granular. .It Li UOPS_RETIRED.RETIRE_SLOTS .Pq Event C2H , Umask 02H Counts the number of retirement slots used each cycle. .It Li MACHINE_CLEARS.MEMORY_ORDERING .Pq Event C3H , Umask 02H Counts the number of machine clears due to memory order conflicts. .It Li MACHINE_CLEARS.SMC .Pq Event C3H , Umask 04H Number of self-modifying-code machine clears detected. .It Li MACHINE_CLEARS.MASKMOV .Pq Event C3H , Umask 20H Counts the number of executed AVX masked load operations that refer to an illegal address range with the mask bits set to 0. .It Li BR_INST_RETIRED.ALL_BRANCHES .Pq Event C4H , Umask 00H Branch instructions at retirement. .It Li BR_INST_RETIRED.CONDITIONAL .Pq Event C4H , Umask 01H Counts the number of conditional branch instructions retired. Supports PEBS. .It Li BR_INST_RETIRED.NEAR_CALL .Pq Event C4H , Umask 02H Direct and indirect near call instructions retired. .It Li BR_INST_RETIRED.ALL_BRANCHES .Pq Event C4H , Umask 04H Counts the number of branch instructions retired. .It Li BR_INST_RETIRED.NEAR_RETURN .Pq Event C4H , Umask 08H Counts the number of near return instructions retired. .It Li BR_INST_RETIRED.NOT_TAKEN .Pq Event C4H , Umask 10H Counts the number of not taken branch instructions retired. .It Li BR_INST_RETIRED.NEAR_TAKEN .Pq Event C4H , Umask 20H Number of near taken branches retired. .It Li BR_INST_RETIRED.FAR_BRANCH .Pq Event C4H , Umask 40H Number of far branches retired. .It Li BR_MISP_RETIRED.ALL_BRANCHES .Pq Event C5H , Umask 00H Mispredicted branch instructions at retirement. .It Li BR_MISP_RETIRED.CONDITIONAL .Pq Event C5H , Umask 01H Mispredicted conditional branch instructions retired. Supports PEBS. .It Li BR_MISP_RETIRED.NEAR_CALL .Pq Event C5H , Umask 02H Direct and indirect mispredicted near call instructions retired. .It Li BR_MISP_RETIRED.ALL_BRANCHES .Pq Event C5H , Umask 04H Mispredicted macro branch instructions retired. .It Li BR_MISP_RETIRED.NOT_TAKEN .Pq Event C5H , Umask 10H Mispredicted not taken branch instructions retired. .It Li BR_MISP_RETIRED.TAKEN .Pq Event C5H , Umask 20H Mispredicted taken branch instructions retired. .It Li FP_ASSIST.X87_OUTPUT .Pq Event CAH , Umask 02H Number of X87 FP assists due to Output values. .It Li FP_ASSIST.X87_INPUT .Pq Event CAH , Umask 04H Number of X87 FP assists due to input values. .It Li FP_ASSIST.SIMD_OUTPUT .Pq Event CAH , Umask 08H Number of SIMD FP assists due to Output values. .It Li FP_ASSIST.SIMD_INPUT .Pq Event CAH , Umask 10H Number of SIMD FP assists due to input values. .It Li FP_ASSIST.ANY .Pq Event CAH , Umask 1EH Cycles with any input/output SSE* or FP assists. .It Li ROB_MISC_EVENTS.LBR_INSERTS .Pq Event CCH , Umask 20H Count cases of saving new LBR records by hardware. .It Li MEM_TRANS_RETIRED.LOAD_LATENCY .Pq Event CDH , Umask 01H Sample loads with specified latency threshold. PMC3 only. Specify threshold in MSR 0x3F6. .It Li MEM_TRANS_RETIRED.PRECISE_STORE .Pq Event CDH , Umask 02H Sample stores and collect precise store operation via PEBS record. PMC3 only. .It Li MEM_UOP_RETIRED.LOADS .Pq Event D0H , Umask 01H Qualify retired memory uops that are loads. Combine with umask 10H, 20H, 40H, 80H. Supports PEBS. .It Li MEM_UOP_RETIRED.STORES .Pq Event D0H , Umask 02H Qualify retired memory uops that are stores. Combine with umask 10H, 20H, 40H, 80H. .It Li MEM_UOP_RETIRED.STLB_MISS .Pq Event D0H , Umask 10H Qualify retired memory uops with STLB miss. Must combine with umask 01H, 02H, to produce counts. .It Li MEM_UOP_RETIRED.LOCK .Pq Event D0H , Umask 20H Qualify retired memory uops with lock. Must combine with umask 01H, 02H, to produce counts. .It Li MEM_UOP_RETIRED.SPLIT .Pq Event D0H , Umask 40H Qualify retired memory uops with line split. Must combine with umask 01H, 02H, to produce counts. .It Li MEM_UOP_RETIRED.ALL .Pq Event D0H , Umask 80H Qualify any retired memory uops. Must combine with umask 01H, 02H, to produce counts. .It Li MEM_LOAD_UOPS_RETIRED.L1_HIT .Pq Event D1H , Umask 01H Retired load uops with L1 cache hits as data sources. Supports PEBS. .It Li MEM_LOAD_UOPS_RETIRED.L2_HIT .Pq Event D1H , Umask 02H Retired load uops with L2 cache hits as data sources. .It Li MEM_LOAD_UOPS_RETIRED.LLC_HIT .Pq Event D1H , Umask 04H Retired load uops with LLC cache hits as data sources. .It Li MEM_LOAD_UOPS_RETIRED.HIT_LFB .Pq Event D1H , Umask 40H Retired load uops which data sources were load uops missed L1 but hit FB due to preceding miss to the same cache line with data not ready. .It Li MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_MISS .Pq Event D2H , Umask 01H Retired load uops which data sources were LLC hit and cross-core snoop missed in on-pkg core cache. Supports PEBS. .It Li MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HIT .Pq Event D2H , Umask 02H Retired load uops which data sources were LLC and cross-core snoop hits in on-pkg core cache. Supports PEBS. .It Li MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HITM .Pq Event D2H , Umask 04H Retired load uops which data sources were HitM responses from shared LLC. .It Li MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_NONE .Pq Event D2H , Umask 08H Retired load uops which data sources were hits in LLC without snoops required. .It Li MEM_LOAD_UOPS_LLC_MISS_RETIRED.LOCAL_DRAM .Pq Event D3H , Umask 01H Retired load uops which data sources missed LLC but serviced from local dram. Supports PEBS. .It Li L2_TRANS.DEMAND_DATA_RD .Pq Event F0H , Umask 01H Demand Data Read requests that access L2 cache. .It Li L2_TRANS.RFO .Pq Event F0H , Umask 02H RFO requests that access L2 cache. .It Li L2_TRANS.CODE_RD .Pq Event F0H , Umask 04H L2 cache accesses when fetching instructions. .It Li L2_TRANS.ALL_PF .Pq Event F0H , Umask 08H Any MLC or LLC HW prefetch accessing L2, including rejects. .It Li L2_TRANS.L1D_WB .Pq Event F0H , Umask 10H L1D writebacks that access L2 cache. .It Li L2_TRANS.L2_FILL .Pq Event F0H , Umask 20H L2 fill requests that access L2 cache. .It Li L2_TRANS.L2_WB .Pq Event F0H , Umask 40H L2 writebacks that access L2 cache. .It Li L2_TRANS.ALL_REQUESTS .Pq Event F0H , Umask 80H Transactions accessing L2 pipe. .It Li L2_LINES_IN.I .Pq Event F1H , Umask 01H L2 cache lines in I state filling L2. Counting does not cover rejects. .It Li L2_LINES_IN.S .Pq Event F1H , Umask 02H L2 cache lines in S state filling L2. Counting does not cover rejects. .It Li L2_LINES_IN.E .Pq Event F1H , Umask 04H L2 cache lines in E state filling L2. Counting does not cover rejects. .It Li L2_LINES_IN.ALL .Pq Event F1H , Umask 07H L2 cache lines filling L2. Counting does not cover rejects. .It Li L2_LINES_OUT.DEMAND_CLEAN .Pq Event F2H , Umask 01H Clean L2 cache lines evicted by demand. .It Li L2_LINES_OUT.DEMAND_DIRTY .Pq Event F2H , Umask 02H Dirty L2 cache lines evicted by demand. .It Li L2_LINES_OUT.PF_CLEAN .Pq Event F2H , Umask 04H Clean L2 cache lines evicted by the MLC prefetcher. .It Li L2_LINES_OUT.PF_DIRTY .Pq Event F2H , Umask 08H Dirty L2 cache lines evicted by the MLC prefetcher. .El .Sh SEE ALSO .Xr pmc 3 , .Xr pmc.atom 3 , .Xr pmc.core 3 , .Xr pmc.iaf 3 , .Xr pmc.ucf 3 , .Xr pmc.k7 3 , .Xr pmc.k8 3 , .Xr pmc.p4 3 , .Xr pmc.p5 3 , .Xr pmc.p6 3 , .Xr pmc.corei7 3 , .Xr pmc.corei7uc 3 , .Xr pmc.ivybridgexeon 3 , .Xr pmc.sandybridge 3 , .Xr pmc.sandybridgeuc 3 , .Xr pmc.sandybridgexeon 3 , .Xr pmc.westmere 3 , .Xr pmc.westmereuc 3 , .Xr pmc.soft 3 , .Xr pmc.tsc 3 , .Xr pmc_cpuinfo 3 , .Xr pmclog 3 , .Xr hwpmc 4 .Sh HISTORY The .Nm pmc library first appeared in .Fx 6.0 . .Sh AUTHORS The .Lb libpmc library was written by .An "Joseph Koshy" .Aq jkoshy@FreeBSD.org . The support for the Ivy Bridge microarchitecture was written by .An "Fabien Thomas" .Aq fabient@FreeBSD.org . Index: stable/10/lib/libpmc/pmc.ivybridgexeon.3 =================================================================== --- stable/10/lib/libpmc/pmc.ivybridgexeon.3 (revision 320105) +++ stable/10/lib/libpmc/pmc.ivybridgexeon.3 (revision 320106) @@ -1,911 +1,891 @@ .\" Copyright (c) 2013 Hiren Panchasara .\" All rights reserved. .\" .\" Redistribution and use in source and binary forms, with or without .\" modification, are permitted provided that the following conditions .\" are met: .\" 1. Redistributions of source code must retain the above copyright .\" notice, this list of conditions and the following disclaimer. .\" 2. Redistributions in binary form must reproduce the above copyright .\" notice, this list of conditions and the following disclaimer in the .\" documentation and/or other materials provided with the distribution. .\" .\" THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND .\" ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE .\" IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE .\" ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE .\" FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL .\" DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS .\" OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) .\" HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT .\" LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY .\" OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF .\" SUCH DAMAGE. .\" .\" $FreeBSD$ .\" .Dd Jan 25, 2013 .Dt PMC.IVYBRIDGEXEON 3 .Os .Sh NAME .Nm pmc.ivybridgexeon .Nd measurement events for .Tn Intel .Tn Ivy Bridge Xeon family CPUs .Sh LIBRARY .Lb libpmc .Sh SYNOPSIS .In pmc.h .Sh DESCRIPTION .Tn Intel .Tn "Ivy Bridge Xeon" CPUs contain PMCs conforming to version 2 of the .Tn Intel performance measurement architecture. These CPUs may contain up to three classes of PMCs: .Bl -tag -width "Li PMC_CLASS_IAP" .It Li PMC_CLASS_IAF Fixed-function counters that count only one hardware event per counter. .It Li PMC_CLASS_IAP Programmable counters that may be configured to count one of a defined set of hardware events. .El .Pp The number of PMCs available in each class and their widths need to be determined at run time by calling .Xr pmc_cpuinfo 3 . .Pp Intel Ivy Bridge Xeon PMCs are documented in .Rs .%B "Intel(R) 64 and IA-32 Architectures Software Developer's Manual" .%N "Order Number: 325462-045US" .%D January 2013 .%Q "Intel Corporation" .Re .Ss IVYBRIDGE FIXED FUNCTION PMCS These PMCs and their supported events are documented in .Xr pmc.iaf 3 . .Ss IVYBRIDGE PROGRAMMABLE PMCS The programmable PMCs support the following capabilities: .Bl -column "PMC_CAP_INTERRUPT" "Support" .It Em Capability Ta Em Support .It PMC_CAP_CASCADE Ta \&No .It PMC_CAP_EDGE Ta Yes .It PMC_CAP_INTERRUPT Ta Yes .It PMC_CAP_INVERT Ta Yes .It PMC_CAP_READ Ta Yes .It PMC_CAP_PRECISE Ta \&No .It PMC_CAP_SYSTEM Ta Yes .It PMC_CAP_TAGGING Ta \&No .It PMC_CAP_THRESHOLD Ta Yes .It PMC_CAP_USER Ta Yes .It PMC_CAP_WRITE Ta Yes .El .Ss Event Qualifiers Event specifiers for these PMCs support the following common qualifiers: .Bl -tag -width indent .It Li rsp= Ns Ar value Configure the Off-core Response bits. .Bl -tag -width indent .It Li REQ_DMND_DATA_RD Counts the number of demand and DCU prefetch data reads of full and partial cachelines as well as demand data page table entry cacheline reads. Does not count L2 data read prefetches or instruction fetches. .It Li REQ_DMND_RFO Counts the number of demand and DCU prefetch reads for ownership (RFO) requests generated by a write to data cacheline. Does not count L2 RFO prefetches. .It Li REQ_DMND_IFETCH Counts the number of demand and DCU prefetch instruction cacheline reads. Does not count L2 code read prefetches. .It Li REQ_WB Counts the number of writeback (modified to exclusive) transactions. .It Li REQ_PF_DATA_RD Counts the number of data cacheline reads generated by L2 prefetchers. .It Li REQ_PF_RFO Counts the number of RFO requests generated by L2 prefetchers. .It Li REQ_PF_IFETCH Counts the number of code reads generated by L2 prefetchers. .It Li REQ_PF_LLC_DATA_RD L2 prefetcher to L3 for loads. .It Li REQ_PF_LLC_RFO RFO requests generated by L2 prefetcher .It Li REQ_PF_LLC_IFETCH L2 prefetcher to L3 for instruction fetches. .It Li REQ_BUS_LOCKS Bus lock and split lock requests. .It Li REQ_STRM_ST Streaming store requests. .It Li REQ_OTHER Any other request that crosses IDI, including I/O. .It Li RES_ANY Catch all value for any response types. .It Li RES_SUPPLIER_NO_SUPP No Supplier Information available. .It Li RES_SUPPLIER_LLC_HITM M-state initial lookup stat in L3. .It Li RES_SUPPLIER_LLC_HITE E-state. .It Li RES_SUPPLIER_LLC_HITS S-state. .It Li RES_SUPPLIER_LLC_HITF F-state. .It Li RES_SUPPLIER_LOCAL Local DRAM Controller. .It Li RES_SNOOP_SNP_NONE No details on snoop-related information. .It Li RES_SNOOP_SNP_NO_NEEDED No snoop was needed to satisfy the request. .It Li RES_SNOOP_SNP_MISS A snoop was needed and it missed all snooped caches: -For LLC Hit, ReslHitl was returned by all cores -For LLC Miss, Rspl was returned by all sockets and data was returned from DRAM. .It Li RES_SNOOP_HIT_NO_FWD A snoop was needed and it hits in at least one snooped cache. Hit denotes a cache-line was valid before snoop effect. This includes: -Snoop Hit w/ Invalidation (LLC Hit, RFO) -Snoop Hit, Left Shared (LLC Hit/Miss, IFetch/Data_RD) -Snoop Hit w/ Invalidation and No Forward (LLC Miss, RFO Hit S) In the LLC Miss case, data is returned from DRAM. .It Li RES_SNOOP_HIT_FWD A snoop was needed and data was forwarded from a remote socket. This includes: -Snoop Forward Clean, Left Shared (LLC Hit/Miss, IFetch/Data_RD/RFT). .It Li RES_SNOOP_HITM A snoop was needed and it HitM-ed in local or remote cache. HitM denotes a cache-line was in modified state before effect as a results of snoop. This includes: -Snoop HitM w/ WB (LLC miss, IFetch/Data_RD) -Snoop Forward Modified w/ Invalidation (LLC Hit/Miss, RFO) -Snoop MtoS (LLC Hit, IFetch/Data_RD). .It Li RES_NON_DRAM Target was non-DRAM system address. This includes MMIO transactions. .El .It Li cmask= Ns Ar value Configure the PMC to increment only if the number of configured events measured in a cycle is greater than or equal to .Ar value . .It Li edge Configure the PMC to count the number of de-asserted to asserted transitions of the conditions expressed by the other qualifiers. If specified, the counter will increment only once whenever a condition becomes true, irrespective of the number of clocks during which the condition remains true. .It Li inv Invert the sense of comparison when the .Dq Li cmask qualifier is present, making the counter increment when the number of events per cycle is less than the value specified by the .Dq Li cmask qualifier. .It Li os Configure the PMC to count events happening at processor privilege level 0. .It Li usr Configure the PMC to count events occurring at privilege levels 1, 2 or 3. .El .Pp If neither of the .Dq Li os or .Dq Li usr qualifiers are specified, the default is to enable both. .Ss Event Specifiers (Programmable PMCs) Ivy Bridge programmable PMCs support the following events: .Bl -tag -width indent .It Li LD_BLOCKS.STORE_FORWARD .Pq Event 03H , Umask 02H loads blocked by overlapping with store buffer that cannot be forwarded . .It Li MISALIGN_MEM_REF.LOADS .Pq Event 05H , Umask 01H Speculative cache-line split load uops dispatched to L1D. .It Li MISALIGN_MEM_REF.STORES .Pq Event 05H , Umask 02H Speculative cache-line split Store- address uops dispatched to L1D. .It Li LD_BLOCKS_PARTIAL.ADDRESS_ALIAS .Pq Event 07H , Umask 01H False dependencies in MOB due to partial compare on address. .It Li DTLB_LOAD_MISSES.DEMAND_LD_MISS_CAUSES_A_WALK .Pq Event 08H , Umask 81H Misses in all TLB levels that cause a page walk of any page size from demand loads. .It Li DTLB_LOAD_MISSES.DEMAND_LD_WALK_COMPLETED .Pq Event 08H , Umask 82H Misses in all TLB levels that caused page walk completed of any size by demand loads. .It Li DTLB_LOAD_MISSES.DEMAND_LD_WALK_DURATION .Pq Event 08H , Umask 84H Cycle PMH is busy with a walk due to demand loads. .It Li UOPS_ISSUED.ANY .Pq Event 0EH , Umask 01H Increments each cycle the # of Uops issued by the RAT to RS. Set Cmask = 1, Inv = 1to count stalled cycles. Set Cmask = 1, Inv = 1, Any= 1to count stalled cycles of this core. .It Li UOPS_ISSUED.FLAGS_MERGE .Pq Event 0EH , Umask 10H Number of flags-merge uops allocated. Such uops adds delay. .It Li UOPS_ISSUED.SLOW_LEA .Pq Event 0EH , Umask 20H Number of slow LEA or similar uops allocated. Such uop has 3 sources (e.g. 2 sources + immediate) regardless if as a result of LEA instruction or not. .It Li UOPS_ISSUED.SINGLE_MUL .Pq Event 0EH , Umask 40H Number of multiply packed/scalar single precision uops allocated. .It Li ARITH.FPU_DIV_ACTIVE .Pq Event 14H , Umask 01H Cycles that the divider is active, includes INT and FP. Set 'edge =1, cmask=1' to count the number of divides. .It Li L2_RQSTS.DEMAND_DATA_RD_HIT .Pq Event 24H , Umask 01H Demand Data Read requests that hit L2 cache. .It Li L2_RQSTS.ALL_DEMAND_DATA_RD .Pq Event 24H , Umask 03H Counts any demand and L1 HW prefetch data load requests to L2. .It Li L2_RQSTS.RFO_HITS .Pq Event 24H , Umask 04H Counts the number of store RFO requests that hit the L2 cache. .It Li L2_RQSTS.RFO_MISS .Pq Event 24H , Umask 08H Counts the number of store RFO requests that miss the L2 cache. .It Li L2_RQSTS.ALL_RFO .Pq Event 24H , Umask 0CH Counts all L2 store RFO requests. .It Li L2_RQSTS.CODE_RD_HIT .Pq Event 24H , Umask 10H Number of instruction fetches that hit the L2 cache. .It Li L2_RQSTS.CODE_RD_MISS .Pq Event 24H , Umask 20H Number of instruction fetches that missed the L2 cache. .It Li L2_RQSTS.ALL_CODE_RD .Pq Event 24H , Umask 30H Counts all L2 code requests. .It Li L2_RQSTS.PF_HIT .Pq Event 24H , Umask 40H Counts all L2 HW prefetcher requests that hit L2. .It Li L2_RQSTS.PF_MISS .Pq Event 24H , Umask 80H Counts all L2 HW prefetcher requests that missed L2. .It Li L2_RQSTS.ALL_PF .Pq Event 24H , Umask C0H Counts all L2 HW prefetcher requests. .It Li L2_STORE_LOCK_RQSTS.MISS .Pq Event 27H , Umask 01H RFOs that miss cache lines. .It Li L2_STORE_LOCK_RQSTS.HIT_M .Pq Event 27H , Umask 08H RFOs that hit cache lines in M state. .It Li L2_STORE_LOCK_RQSTS.ALL .Pq Event 27H , Umask 0FH RFOs that access cache lines in any state. .It Li L2_L1D_WB_RQSTS.MISS .Pq Event 28H , Umask 01H Not rejected writebacks that missed LLC. .It Li L2_L1D_WB_RQSTS.HIT_E .Pq Event 28H , Umask 04H Not rejected writebacks from L1D to L2 cache lines in E state. .It Li L2_L1D_WB_RQSTS.HIT_M .Pq Event 28H , Umask 08H Not rejected writebacks from L1D to L2 cache lines in M state. .It Li L2_L1D_WB_RQSTS.ALL .Pq Event 28H , Umask 0FH Not rejected writebacks from L1D to L2 cache lines in any state. .It Li LONGEST_LAT_CACHE.REFERENCE .Pq Event 2EH , Umask 4FH This event counts requests originating from the core that reference a cache line in the last level cache. .It Li LONGEST_LAT_CACHE.MISS .Pq Event 2EH , Umask 41H This event counts each cache miss condition for references to the last level cache. .It Li CPU_CLK_UNHALTED.THREAD_P .Pq Event 3CH , Umask 00H Counts the number of thread cycles while the thread is not in a halt state. The thread enters the halt state when it is running the HLT instruction. The core frequency may change from time to time due to power or thermal throttling. .It Li CPU_CLK_THREAD_UNHALTED.REF_XCLK .Pq Event 3CH , Umask 01H Increments at the frequency of XCLK (100 MHz) when not halted. .It Li L1D_PEND_MISS.PENDING .Pq Event 48H , Umask 01H Increments the number of outstanding L1D misses every cycle. Set Cmaks = 1 and Edge =1 to count occurrences. Counter 2 only. Set Cmask = 1 to count cycles. .It Li DTLB_STORE_MISSES.MISS_CAUSES_A_WALK .Pq Event 49H , Umask 01H Miss in all TLB levels causes an page walk of any page size (4K/2M/4M/1G). .It Li DTLB_STORE_MISSES.WALK_COMPLETED .Pq Event 49H , Umask 02H Miss in all TLB levels causes a page walk that completes of any page size (4K/2M/4M/1G). .It Li DTLB_STORE_MISSES.WALK_DURATION .Pq Event 49H , Umask 04H Cycles PMH is busy with this walk. .It Li DTLB_STORE_MISSES.STLB_HIT .Pq Event 49H , Umask 10H Store operations that miss the first TLB level but hit the second and do not cause page walks. .It Li LOAD_HIT_PRE.SW_PF .Pq Event 4CH , Umask 01H Non-SW-prefetch load dispatches that hit fill buffer allocated for S/W prefetch. .It Li LOAD_HIT_PRE.HW_PF .Pq Event 4CH , Umask 02H Non-SW-prefetch load dispatches that hit fill buffer allocated for H/W prefetch. .It Li L1D.REPLACEMENT .Pq Event 51H , Umask 01H Counts the number of lines brought into the L1 data cache. .It Li MOVE_ELIMINATION.INT_NOT_ELIMINATED .Pq Event 58H , Umask 01H Number of integer Move Elimination candidate uops that were not eliminated. .It Li MOVE_ELIMINATION.SIMD_NOT_ELIMINATED .Pq Event 58H , Umask 02H Number of SIMD Move Elimination candidate uops that were not eliminated. .It Li MOVE_ELIMINATION.INT_ELIMINATED .Pq Event 58H , Umask 04H Number of integer Move Elimination candidate uops that were eliminated. .It Li MOVE_ELIMINATION.SIMD_ELIMINATED .Pq Event 58H , Umask 08H Number of SIMD Move Elimination candidate uops that were eliminated. .It Li CPL_CYCLES.RING0 .Pq Event 5CH , Umask 01H Unhalted core cycles when the thread is in ring 0. Use Edge to count transition. .It Li CPL_CYCLES.RING123 .Pq Event 5CH , Umask 02H Unhalted core cycles when the thread is not in ring 0. .It Li RS_EVENTS.EMPTY_CYCLES .Pq Event 5EH , Umask 01H Cycles the RS is empty for the thread. .It Li DTLB_LOAD_MISSES.STLB_HIT .Pq Event 5FH , Umask 04H Counts load operations that missed 1st level DTLB but hit the 2nd level. .It Li OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD .Pq Event 60H , Umask 01H Offcore outstanding Demand Data Read transactions in SQ to uncore. Set Cmask=1 to count cycles. .It Li OFFCORE_REQUESTS_OUTSTANDING.DEMAND_CODE_RD .Pq Event 60H , Umask 02H Offcore outstanding Demand Code Read transactions in SQ to uncore. Set Cmask=1 to count cycles. .It Li OFFCORE_REQUESTS_OUTSTANDING.DEMAND_RFO .Pq Event 60H , Umask 04H Offcore outstanding RFO store transactions in SQ to uncore. Set Cmask=1 to count cycles. .It Li OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD .Pq Event 60H , Umask 08H Offcore outstanding cacheable data read transactions in SQ to uncore. Set Cmask=1 to count cycles. .It Li LOCK_CYCLES.SPLIT_LOCK_UC_LOCK_DURATION .Pq Event 63H , Umask 01H Cycles in which the L1D and L2 are locked, due to a UC lock or split lock. .It Li LOCK_CYCLES.CACHE_LOCK_DURATION .Pq Event 63H , Umask 02H Cycles in which the L1D is locked. .It Li IDQ.EMPTY .Pq Event 79H , Umask 02H Counts cycles the IDQ is empty. .It Li IDQ.MITE_UOPS .Pq Event 79H , Umask 04H Increment each cycle # of uops delivered to IDQ from MITE path. Can combine Umask 04H and 20H. Set Cmask = 1 to count cycles. .It Li IDQ.DSB_UOPS .Pq Event 79H , Umask 08H Increment each cycle. # of uops delivered to IDQ from DSB path. Can combine Umask 08H and 10H Set Cmask = 1 to count cycles. .It Li IDQ.MS_DSB_UOPS .Pq Event 79H , Umask 10H Increment each cycle # of uops delivered to IDQ when MS_busy by DSB. Set Cmask = 1 to count cycles. Add Edge=1 to count # of delivery. Can combine Umask 04H, 08H. .It Li IDQ.MS_MITE_UOPS .Pq Event 79H , Umask 20H Increment each cycle # of uops delivered to IDQ when MS_busy by MITE. Set Cmask = 1 to count cycles. Can combine Umask 04H, 08H. .It Li IDQ.MS_UOPS .Pq Event 79H , Umask 30H Increment each cycle # of uops delivered to IDQ from MS by either DSB or MITE. Set Cmask = 1 to count cycles. Can combine Umask 04H, 08H. .It Li IDQ.ALL_DSB_CYCLES_ANY_UOPS .Pq Event 79H , Umask 18H Counts cycles DSB is delivered at least one uops. Set Cmask = 1. .It Li IDQ.ALL_DSB_CYCLES_4_UOPS .Pq Event 79H , Umask 18H Counts cycles DSB is delivered four uops. Set Cmask = 4. .It Li IDQ.ALL_MITE_CYCLES_ANY_UOPS .Pq Event 79H , Umask 24H Counts cycles MITE is delivered at least one uops. Set Cmask = 1. .It Li IDQ.ALL_MITE_CYCLES_4_UOPS .Pq Event 79H , Umask 24H Counts cycles MITE is delivered four uops. Set Cmask = 4. .It Li IDQ.MITE_ALL_UOPS .Pq Event 79H , Umask 3CH # of uops delivered to IDQ from any path. .It Li ICACHE.MISSES .Pq Event 80H , Umask 02H Number of Instruction Cache, Streaming Buffer and Victim Cache Misses. Includes UC accesses. .It Li ITLB_MISSES.MISS_CAUSES_A_WALK .Pq Event 85H , Umask 01H Misses in all ITLB levels that cause page walks. .It Li ITLB_MISSES.WALK_COMPLETED .Pq Event 85H , Umask 02H Misses in all ITLB levels that cause completed page walks. .It Li ITLB_MISSES.WALK_DURATION .Pq Event 85H , Umask 04H Cycle PMH is busy with a walk. .It Li ITLB_MISSES.STLB_HIT .Pq Event 85H , Umask 10H Number of cache load STLB hits. No page walk. .It Li ILD_STALL.LCP .Pq Event 87H , Umask 01H Stalls caused by changing prefix length of the instruction. .It Li ILD_STALL.IQ_FULL .Pq Event 87H , Umask 04H Stall cycles due to IQ is full. -.It Li BR_INST_EXEC.COND -.Pq Event 88H , Umask 01H -Qualify conditional near branch instructions executed, but not necessarily -retired. -Must combine with umask 40H, 80H. +.It Li BR_INST_EXEC.NONTAKEN_COND +.Pq Event 88H , Umask 41H +Count conditional near branch instructions that were executed (but not +necessarily retired) and not taken. +.It Li BR_INST_EXEC.TAKEN_COND +.Pq Event 88H , Umask 81H +Count conditional near branch instructions that were executed (but not +necessarily retired) and taken. .It Li BR_INST_EXEC.DIRECT_JMP -.Pq Event 88H , Umask 02H -Qualify all unconditional near branch instructions excluding calls and +.Pq Event 88H , Umask 82H +Count all unconditional near branch instructions excluding calls and indirect branches. -Must combine with umask 80H. .It Li BR_INST_EXEC.INDIRECT_JMP_NON_CALL_RET -.Pq Event 88H , Umask 04H -Qualify executed indirect near branch instructions that are not calls nor +.Pq Event 88H , Umask 84H +Count executed indirect near branch instructions that are not calls nor returns. -Must combine with umask 80H. .It Li BR_INST_EXEC.RETURN_NEAR -.Pq Event 88H , Umask 08H -Qualify indirect near branches that have a return mnemonic. -Must combine with umask 80H. +.Pq Event 88H , Umask 88H +Count indirect near branches that have a return mnemonic. .It Li BR_INST_EXEC.DIRECT_NEAR_CALL -.Pq Event 88H , Umask 10H -Qualify unconditional near call branch instructions, excluding non call +.Pq Event 88H , Umask 90H +Count unconditional near call branch instructions, excluding non call branch, executed. -Must combine with umask 80H. .It Li BR_INST_EXEC.INDIRECT_NEAR_CALL -.Pq Event 88H , Umask 20H -Qualify indirect near calls, including both register and memory indirect, +.Pq Event 88H , Umask A0H +Count indirect near calls, including both register and memory indirect, executed. -Must combine with umask 80H. -.It Li BR_INST_EXEC.NONTAKEN -.Pq Event 88H , Umask 40H -Qualify non-taken near branches executed. -Applicable to umask 01H only. -.It Li BR_INST_EXEC.TAKEN -.Pq Event 88H , Umask 80H -Qualify taken near branches executed. Must combine with 01H,02H, 04H, 08H, -10H, 20H. .It Li BR_INST_EXEC.ALL_BRANCHES .Pq Event 88H , Umask FFH Counts all near executed branches (not necessarily retired). -.It Li BR_MISP_EXEC.COND -.Pq Event 89H , Umask 01H -Qualify conditional near branch instructions mispredicted. -Must combine with umask 40H, 80H. +.It Li BR_MISP_EXEC.NONTAKEN_COND +.Pq Event 89H , Umask 41H +Count conditional near branch instructions mispredicted as nontaken. +.It Li BR_MISP_EXEC.TAKEN_COND +.Pq Event 89H , Umask 81H +Count conditional near branch instructions mispredicted as taken. .It Li BR_MISP_EXEC.INDIRECT_JMP_NON_CALL_RET -.Pq Event 89H , Umask 04H -Qualify mispredicted indirect near branch instructions that are not calls +.Pq Event 89H , Umask 84H +Count mispredicted indirect near branch instructions that are not calls nor returns. -Must combine with umask 80H. .It Li BR_MISP_EXEC.RETURN_NEAR -.Pq Event 89H , Umask 08H -Qualify mispredicted indirect near branches that have a return mnemonic. -Must combine with umask 80H. +.Pq Event 89H , Umask 88H +Count mispredicted indirect near branches that have a return mnemonic. .It Li BR_MISP_EXEC.DIRECT_NEAR_CALL -.Pq Event 89H , Umask 10H -Qualify mispredicted unconditional near call branch instructions, excluding +.Pq Event 89H , Umask 90H +Count mispredicted unconditional near call branch instructions, excluding non call branch, executed. -Must combine with umask 80H. .It Li BR_MISP_EXEC.INDIRECT_NEAR_CALL -.Pq Event 89H , Umask 20H -Qualify mispredicted indirect near calls, including both register and memory +.Pq Event 89H , Umask A0H +Count mispredicted indirect near calls, including both register and memory indirect, executed. -Must combine with umask 80H. -.It Li BR_MISP_EXEC.NONTAKEN -.Pq Event 89H , Umask 40H -Qualify mispredicted non-taken near branches executed. -Applicable to umask 01H only. -.It Li BR_MISP_EXEC.TAKEN -.Pq Event 89H , Umask 80H -Qualify mispredicted taken near branches executed. Must combine with -01H,02H, 04H, 08H, 10H, 20H. .It Li BR_MISP_EXEC.ALL_BRANCHES .Pq Event 89H , Umask FFH -Counts all near executed branches (not necessarily retired). +Counts all mispredicted near executed branches (not necessarily retired). .It Li IDQ_UOPS_NOT_DELIVERED.CORE .Pq Event 9CH , Umask 01H Count number of non-delivered uops to RAT per thread. Use Cmask to qualify uop b/w. .It Li UOPS_DISPATCHED_PORT.PORT_0 .Pq Event A1H , Umask 01H Cycles which a Uop is dispatched on port 0. .It Li UOPS_DISPATCHED_PORT.PORT_1 .Pq Event A1H , Umask 02H Cycles which a Uop is dispatched on port 1. .It Li UOPS_DISPATCHED_PORT.PORT_2_LD .Pq Event A1H , Umask 04H Cycles which a load uop is dispatched on port 2. .It Li UOPS_DISPATCHED_PORT.PORT_2_STA .Pq Event A1H , Umask 08H Cycles which a store address uop is dispatched on port 2. .It Li UOPS_DISPATCHED_PORT.PORT_2 .Pq Event A1H , Umask 0CH Cycles which a Uop is dispatched on port 2. .It Li UOPS_DISPATCHED_PORT.PORT_3_LD .Pq Event A1H , Umask 10H Cycles which a load uop is dispatched on port 3. .It Li UOPS_DISPATCHED_PORT.PORT_3_STA .Pq Event A1H , Umask 20H Cycles which a store address uop is dispatched on port 3. .It Li UOPS_DISPATCHED_PORT.PORT_3 .Pq Event A1H , Umask 30H Cycles which a Uop is dispatched on port 3. .It Li UOPS_DISPATCHED_PORT.PORT_4 .Pq Event A1H , Umask 40H Cycles which a Uop is dispatched on port 4. .It Li UOPS_DISPATCHED_PORT.PORT_5 .Pq Event A1H , Umask 80H Cycles which a Uop is dispatched on port 5. .It Li RESOURCE_STALLS.ANY .Pq Event A2H , Umask 01H Cycles Allocation is stalled due to Resource Related reason. .It Li RESOURCE_STALLS.RS .Pq Event A2H , Umask 04H Cycles stalled due to no eligible RS entry available. .It Li RESOURCE_STALLS.SB .Pq Event A2H , Umask 08H Cycles stalled due to no store buffers available. (not including draining form sync). .It Li RESOURCE_STALLS.ROB .Pq Event A2H , Umask 10H Cycles stalled due to re-order buffer full. .It Li CYCLE_ACTIVITY.CYCLES_L2_PENDING .Pq Event A3H , Umask 01H Cycles with pending L2 miss loads. Set AnyThread to count per core. .It Li CYCLE_ACTIVITY.CYCLES_LDM_PENDING .Pq Event A3H , Umask 02H Cycles with pending memory loads. Set AnyThread to count per core. .It Li CYCLE_ACTIVITY.CYCLES_NO_EXECUTE .Pq Event A3H , Umask 04H Cycles of dispatch stalls. Set AnyThread to count per core. .It Li CYCLE_ACTIVITY.CYCLES_L1D_PENDING .Pq Event A3H , Umask 08H Cycles with pending L1 cache miss loads. Set AnyThread to count per core. .It Li DSB2MITE_SWITCHES.COUNT .Pq Event ABH , Umask 01H Number of DSB to MITE switches. .It Li DSB2MITE_SWITCHES.PENALTY_CYCLES .Pq Event ABH , Umask 02H Cycles DSB to MITE switches caused delay. .It Li DSB_FILL.EXCEED_DSB_LINES .Pq Event ACH , Umask 08H DSB Fill encountered > 3 DSB lines. .It Li ITLB.ITLB_FLUSH .Pq Event AEH , Umask 01H Counts the number of ITLB flushes, includes 4k/2M/4M pages. .It Li OFFCORE_REQUESTS.DEMAND_DATA_RD .Pq Event B0H , Umask 01H Demand data read requests sent to uncore. .It Li OFFCORE_REQUESTS.DEMAND_CODE_RD .Pq Event B0H , Umask 02H Demand code read requests sent to uncore. .It Li OFFCORE_REQUESTS.DEMAND_RFO .Pq Event B0H , Umask 04H Demand RFO read requests sent to uncore, including regular RFOs, locks, ItoM. .It Li OFFCORE_REQUESTS.ALL_DATA_RD .Pq Event B0H , Umask 08H Data read requests sent to uncore (demand and prefetch). .It Li UOPS_EXECUTED.THREAD .Pq Event B1H , Umask 01H Counts total number of uops to be executed per-thread each cycle. Set Cmask = 1, INV =1 to count stall cycles. .It Li UOPS_EXECUTED.CORE .Pq Event B1H , Umask 02H Counts total number of uops to be executed per-core each cycle. Do not need to set ANY. .It Li OFF_CORE_RESPONSE_0 .Pq Event B7H , Umask 01H Off-core Response Performance Monitoring. PMC0 only. Requires programming MSR 01A6H. .It Li OFF_CORE_RESPONSE_1 .Pq Event BBH , Umask 01H Off-core Response Performance Monitoring. PMC3 only. Requires programming MSR 01A7H. .It Li TLB_FLUSH.DTLB_THREAD .Pq Event BDH , Umask 01H DTLB flush attempts of the thread- specific entries. .It Li TLB_FLUSH.STLB_ANY .Pq Event BDH , Umask 20H Count number of STLB flush attempts. .It Li INST_RETIRED.ANY_P .Pq Event C0H , Umask 00H Number of instructions at retirement. .It Li INST_RETIRED.ALL .Pq Event C0H , Umask 01H Precise instruction retired event with HW to reduce effect of PEBS shadow in IP distribution. PMC1 only. Must quiesce other PMCs. .It Li OTHER_ASSISTS.AVX_STORE .Pq Event C1H , Umask 08H Number of assists associated with 256-bit AVX store operations. .It Li OTHER_ASSISTS.AVX_TO_SSE .Pq Event C1H , Umask 10H Number of transitions from AVX- 256 to legacy SSE when penalty applicable. .It Li OTHER_ASSISTS.SSE_TO_AVX .Pq Event C1H , Umask 20H Number of transitions from SSE to AVX-256 when penalty applicable. .It Li UOPS_RETIRED.ALL .Pq Event C2H , Umask 01H Counts the number of micro-ops retired, Use cmask=1 and invert to count active cycles or stalled cycles. Supports PEBS, use Any=1 for core granular. .It Li UOPS_RETIRED.RETIRE_SLOTS .Pq Event C2H , Umask 02H Counts the number of retirement slots used each cycle. .It Li MACHINE_CLEARS.MEMORY_ORDERING .Pq Event C3H , Umask 02H Counts the number of machine clears due to memory order conflicts. .It Li MACHINE_CLEARS.SMC .Pq Event C3H , Umask 04H Number of self-modifying-code machine clears detected. .It Li MACHINE_CLEARS.MASKMOV .Pq Event C3H , Umask 20H Counts the number of executed AVX masked load operations that refer to an illegal address range with the mask bits set to 0. .It Li BR_INST_RETIRED.ALL_BRANCHES .Pq Event C4H , Umask 00H Branch instructions at retirement. .It Li BR_INST_RETIRED.CONDITIONAL .Pq Event C4H , Umask 01H Counts the number of conditional branch instructions retired. Supports PEBS. .It Li BR_INST_RETIRED.NEAR_CALL .Pq Event C4H , Umask 02H Direct and indirect near call instructions retired. .It Li BR_INST_RETIRED.ALL_BRANCHES .Pq Event C4H , Umask 04H Counts the number of branch instructions retired. .It Li BR_INST_RETIRED.NEAR_RETURN .Pq Event C4H , Umask 08H Counts the number of near return instructions retired. .It Li BR_INST_RETIRED.NOT_TAKEN .Pq Event C4H , Umask 10H Counts the number of not taken branch instructions retired. .It Li BR_INST_RETIRED.NEAR_TAKEN .Pq Event C4H , Umask 20H Number of near taken branches retired. .It Li BR_INST_RETIRED.FAR_BRANCH .Pq Event C4H , Umask 40H Number of far branches retired. .It Li BR_MISP_RETIRED.ALL_BRANCHES .Pq Event C5H , Umask 00H Mispredicted branch instructions at retirement. .It Li BR_MISP_RETIRED.CONDITIONAL .Pq Event C5H , Umask 01H Mispredicted conditional branch instructions retired. Supports PEBS. .It Li BR_MISP_RETIRED.NEAR_CALL .Pq Event C5H , Umask 02H Direct and indirect mispredicted near call instructions retired. .It Li BR_MISP_RETIRED.ALL_BRANCHES .Pq Event C5H , Umask 04H Mispredicted macro branch instructions retired. .It Li BR_MISP_RETIRED.NOT_TAKEN .Pq Event C5H , Umask 10H Mispredicted not taken branch instructions retired. .It Li BR_MISP_RETIRED.TAKEN .Pq Event C5H , Umask 20H Mispredicted taken branch instructions retired. .It Li FP_ASSIST.X87_OUTPUT .Pq Event CAH , Umask 02H Number of X87 FP assists due to Output values. .It Li FP_ASSIST.X87_INPUT .Pq Event CAH , Umask 04H Number of X87 FP assists due to input values. .It Li FP_ASSIST.SIMD_OUTPUT .Pq Event CAH , Umask 08H Number of SIMD FP assists due to Output values. .It Li FP_ASSIST.SIMD_INPUT .Pq Event CAH , Umask 10H Number of SIMD FP assists due to input values. .It Li FP_ASSIST.ANY .Pq Event CAH , Umask 1EH Cycles with any input/output SSE* or FP assists. .It Li ROB_MISC_EVENTS.LBR_INSERTS .Pq Event CCH , Umask 20H Count cases of saving new LBR records by hardware. .It Li MEM_TRANS_RETIRED.LOAD_LATENCY .Pq Event CDH , Umask 01H Sample loads with specified latency threshold. PMC3 only. Specify threshold in MSR 0x3F6. .It Li MEM_TRANS_RETIRED.PRECISE_STORE .Pq Event CDH , Umask 02H Sample stores and collect precise store operation via PEBS record. PMC3 only. .It Li MEM_UOP_RETIRED.LOADS .Pq Event D0H , Umask 01H Qualify retired memory uops that are loads. Combine with umask 10H, 20H, 40H, 80H. Supports PEBS. .It Li MEM_UOP_RETIRED.STORES .Pq Event D0H , Umask 02H Qualify retired memory uops that are stores. Combine with umask 10H, 20H, 40H, 80H. .It Li MEM_UOP_RETIRED.STLB_MISS .Pq Event D0H , Umask 10H Qualify retired memory uops with STLB miss. Must combine with umask 01H, 02H, to produce counts. .It Li MEM_UOP_RETIRED.LOCK .Pq Event D0H , Umask 20H Qualify retired memory uops with lock. Must combine with umask 01H, 02H, to produce counts. .It Li MEM_UOP_RETIRED.SPLIT .Pq Event D0H , Umask 40H Qualify retired memory uops with line split. Must combine with umask 01H, 02H, to produce counts. .It Li MEM_UOP_RETIRED.ALL .Pq Event D0H , Umask 80H Qualify any retired memory uops. Must combine with umask 01H, 02H, to produce counts. .It Li MEM_LOAD_UOPS_RETIRED.L1_HIT .Pq Event D1H , Umask 01H Retired load uops with L1 cache hits as data sources. Supports PEBS. .It Li MEM_LOAD_UOPS_RETIRED.L2_HIT .Pq Event D1H , Umask 02H Retired load uops with L2 cache hits as data sources. .It Li MEM_LOAD_UOPS_RETIRED.LLC_HIT .Pq Event D1H , Umask 04H Retired load uops whose data source was LLC hit with no snoop required. .It Li MEM_LOAD_UOPS_RETIRED.LLC_MISS .Pq Event D1H , Umask 20H Retired load uops whose data source is LLC miss. .It Li MEM_LOAD_UOPS_RETIRED.HIT_LFB .Pq Event D1H , Umask 40H Retired load uops which data sources were load uops missed L1 but hit FB due to preceding miss to the same cache line with data not ready. .It Li MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_MISS .Pq Event D2H , Umask 01H Retired load uops which data sources were LLC hit and cross-core snoop missed in on-pkg core cache. Supports PEBS. .It Li MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HIT .Pq Event D2H , Umask 02H Retired load uops which data sources were LLC and cross-core snoop hits in on-pkg core cache. Supports PEBS. .It Li MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HITM .Pq Event D2H , Umask 04H Retired load uops which data sources were HitM responses from shared LLC. .It Li MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_NONE .Pq Event D2H , Umask 08H Retired load uops which data sources were hits in LLC without snoops required. .It Li MEM_LOAD_UOPS_LLC_MISS_RETIRED.LOCAL_DRAM .Pq Event D3H , Umask 01H Retired load uops which data sources missed LLC but serviced from local dram. Supports PEBS. .It Li MEM_LOAD_UOPS_LLC_MISS_RETIRED.REMOTE_DRAM .Pq Event D3H , Umask 04H Retired load uops whose data source was remote DRAM. .It Li MEM_LOAD_UOPS_LLC_MISS_RETIRED.REMOTE_HITM .Pq Event D3H , Umask 10H Retired load uops whose data source was remote HITM. .It Li MEM_LOAD_UOPS_LLC_MISS_RETIRED.REMOTE_FWD .Pq Event D3H , Umask 20H Retired load uops whose data source was forwards from a remote cache. .It Li BACLEARS.ANY .Pq Event E6H , Umask 1FH Number of front end re-steers due to BPU misprediction. .It Li L2_TRANS.DEMAND_DATA_RD .Pq Event F0H , Umask 01H Demand Data Read requests that access L2 cache. .It Li L2_TRANS.RFO .Pq Event F0H , Umask 02H RFO requests that access L2 cache. .It Li L2_TRANS.CODE_RD .Pq Event F0H , Umask 04H L2 cache accesses when fetching instructions. .It Li L2_TRANS.ALL_PF .Pq Event F0H , Umask 08H Any MLC or LLC HW prefetch accessing L2, including rejects. .It Li L2_TRANS.L1D_WB .Pq Event F0H , Umask 10H L1D writebacks that access L2 cache. .It Li L2_TRANS.L2_FILL .Pq Event F0H , Umask 20H L2 fill requests that access L2 cache. .It Li L2_TRANS.L2_WB .Pq Event F0H , Umask 40H L2 writebacks that access L2 cache. .It Li L2_TRANS.ALL_REQUESTS .Pq Event F0H , Umask 80H Transactions accessing L2 pipe. .It Li L2_LINES_IN.I .Pq Event F1H , Umask 01H L2 cache lines in I state filling L2. Counting does not cover rejects. .It Li L2_LINES_IN.S .Pq Event F1H , Umask 02H L2 cache lines in S state filling L2. Counting does not cover rejects. .It Li L2_LINES_IN.E .Pq Event F1H , Umask 04H L2 cache lines in E state filling L2. Counting does not cover rejects. .It Li L2_LINES_IN.ALL .Pq Event F1H , Umask 07H L2 cache lines filling L2. Counting does not cover rejects. .It Li L2_LINES_OUT.DEMAND_CLEAN .Pq Event F2H , Umask 01H Clean L2 cache lines evicted by demand. .It Li L2_LINES_OUT.DEMAND_DIRTY .Pq Event F2H , Umask 02H Dirty L2 cache lines evicted by demand. .It Li L2_LINES_OUT.PF_CLEAN .Pq Event F2H , Umask 04H Clean L2 cache lines evicted by the MLC prefetcher. .It Li L2_LINES_OUT.PF_DIRTY .Pq Event F2H , Umask 08H Dirty L2 cache lines evicted by the MLC prefetcher. .It Li L2_LINES_OUT.DIRTY_ALL .Pq Event F2H , Umask 0AH Dirty L2 cache lines filling the L2. .El .Sh SEE ALSO .Xr pmc 3 , .Xr pmc.atom 3 , .Xr pmc.core 3 , .Xr pmc.iaf 3 , .Xr pmc.ucf 3 , .Xr pmc.k7 3 , .Xr pmc.k8 3 , .Xr pmc.p4 3 , .Xr pmc.p5 3 , .Xr pmc.p6 3 , .Xr pmc.corei7 3 , .Xr pmc.corei7uc 3 , .Xr pmc.ivybridge 3 , .Xr pmc.sandybridge 3 , .Xr pmc.sandybridgeuc 3 , .Xr pmc.sandybridgexeon 3 , .Xr pmc.westmere 3 , .Xr pmc.westmereuc 3 , .Xr pmc.soft 3 , .Xr pmc.tsc 3 , .Xr pmc_cpuinfo 3 , .Xr pmclog 3 , .Xr hwpmc 4 .Sh HISTORY The .Nm pmc library first appeared in .Fx 6.0 . .Sh AUTHORS The .Lb libpmc library was written by .An "Joseph Koshy" .Aq jkoshy@FreeBSD.org . The support for the Ivy Bridge Xeon microarchitecture was written by .An "Hiren Panchasara" .Aq hiren.panchasara@gmail.com . Index: stable/10/lib/libpmc/pmc.sandybridge.3 =================================================================== --- stable/10/lib/libpmc/pmc.sandybridge.3 (revision 320105) +++ stable/10/lib/libpmc/pmc.sandybridge.3 (revision 320106) @@ -1,960 +1,940 @@ .\" Copyright (c) 2012 Davide Italiano .\" All rights reserved. .\" .\" Redistribution and use in source and binary forms, with or without .\" modification, are permitted provided that the following conditions .\" are met: .\" 1. Redistributions of source code must retain the above copyright .\" notice, this list of conditions and the following disclaimer. .\" 2. Redistributions in binary form must reproduce the above copyright .\" notice, this list of conditions and the following disclaimer in the .\" documentation and/or other materials provided with the distribution. .\" .\" THIS SOFTWARE IS PROVIDED BY THE AUTHORS AND CONTRIBUTORS ``AS IS'' AND .\" ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE .\" IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE .\" ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHORS OR CONTRIBUTORS BE LIABLE .\" FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL .\" DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS .\" OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) .\" HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT .\" LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY .\" OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF .\" SUCH DAMAGE. .\" .\" $FreeBSD$ .\" .Dd October 19, 2012 .Dt PMC.SANDYBRIDGE 3 .Os .Sh NAME .Nm pmc.sandybridge .Nd measurement events for .Tn Intel .Tn Sandy Bridge family CPUs .Sh LIBRARY .Lb libpmc .Sh SYNOPSIS .In pmc.h .Sh DESCRIPTION .Tn Intel .Tn "Sandy Bridge" CPUs contain PMCs conforming to the version 3 of the .Tn Intel performance measurement architecture. These CPUs may contain up to three classes of PMCs: .Bl -tag -width "Li PMC_CLASS_IAP" .It Li PMC_CLASS_IAF Fixed-function counters that count only one hardware event per counter. .It Li PMC_CLASS_IAP Programmable counters that may be configured to count one of a defined set of hardware events. .It Li PMC_CLASS_TSC These PMCs are documented in .Xr pmc.tsc 3 . .El .Pp The number of PMCs available in each class and their widths need to be determined at run time by calling .Xr pmc_cpuinfo 3 . .Pp Intel Sandy Bridge PMCs are documented in .Rs .%B "Intel(R) 64 and IA-32 Architectures Software Developers Manual" .%T "Volume 3B: System Programming Guide, Part 2" .%N "Order Number: 253669-039US" .%D May 2011 .%Q "Intel Corporation" .Re .Ss SANDY BRIDGE FIXED FUNCTION PMCS These PMCs and their supported events are documented in .Xr pmc.iaf 3 . .Ss SANDY BRIDGE PROGRAMMABLE PMCS The programmable PMCs support the following capabilities: .Bl -column "PMC_CAP_INTERRUPT" "Support" .It Em Capability Ta Em Support .It PMC_CAP_CASCADE Ta \&No .It PMC_CAP_EDGE Ta Yes .It PMC_CAP_INTERRUPT Ta Yes .It PMC_CAP_INVERT Ta Yes .It PMC_CAP_READ Ta Yes .It PMC_CAP_PRECISE Ta \&No .It PMC_CAP_SYSTEM Ta Yes .It PMC_CAP_TAGGING Ta \&No .It PMC_CAP_THRESHOLD Ta Yes .It PMC_CAP_USER Ta Yes .It PMC_CAP_WRITE Ta Yes .El .Ss Event Qualifiers Event specifiers for these PMCs support the following common qualifiers: .Bl -tag -width indent .It Li rsp= Ns Ar value Configure the Off-core Response bits. .Bl -tag -width indent .It Li REQ_DMND_DATA_RD Counts the number of demand and DCU prefetch data reads of full and partial cachelines as well as demand data page table entry cacheline reads. Does not count L2 data read prefetches or instruction fetches. .It Li REQ_DMND_RFO Counts the number of demand and DCU prefetch reads for ownership (RFO) requests generated by a write to data cacheline. Does not count L2 RFO prefetches. .It Li REQ_DMND_IFETCH Counts the number of demand and DCU prefetch instruction cacheline reads. Does not count L2 code read prefetches. .It Li REQ_WB Counts the number of writeback (modified to exclusive) transactions. .It Li REQ_PF_DATA_RD Counts the number of data cacheline reads generated by L2 prefetchers. .It Li REQ_PF_RFO Counts the number of RFO requests generated by L2 prefetchers. .It Li REQ_PF_IFETCH Counts the number of code reads generated by L2 prefetchers. .It Li REQ_PF_LLC_DATA_RD L2 prefetcher to L3 for loads. .It Li REQ_PF_LLC_RFO RFO requests generated by L2 prefetcher .It Li REQ_PF_LLC_IFETCH L2 prefetcher to L3 for instruction fetches. .It Li REQ_BUS_LOCKS Bus lock and split lock requests. .It Li REQ_STRM_ST Streaming store requests. .It Li REQ_OTHER Any other request that crosses IDI, including I/O. .It Li RES_ANY Catch all value for any response types. .It Li RES_SUPPLIER_NO_SUPP No Supplier Information available. .It Li RES_SUPPLIER_LLC_HITM M-state initial lookup stat in L3. .It Li RES_SUPPLIER_LLC_HITE E-state. .It Li RES_SUPPLIER_LLC_HITS S-state. .It Li RES_SUPPLIER_LLC_HITF F-state. .It Li RES_SUPPLIER_LOCAL Local DRAM Controller. .It Li RES_SNOOP_SNP_NONE No details on snoop-related information. .It Li RES_SNOOP_SNP_NO_NEEDED No snoop was needed to satisfy the request. .It Li RES_SNOOP_SNP_MISS A snoop was needed and it missed all snooped caches: -For LLC Hit, ReslHitl was returned by all cores -For LLC Miss, Rspl was returned by all sockets and data was returned from DRAM. .It Li RES_SNOOP_HIT_NO_FWD A snoop was needed and it hits in at least one snooped cache. Hit denotes a cache-line was valid before snoop effect. This includes: -Snoop Hit w/ Invalidation (LLC Hit, RFO) -Snoop Hit, Left Shared (LLC Hit/Miss, IFetch/Data_RD) -Snoop Hit w/ Invalidation and No Forward (LLC Miss, RFO Hit S) In the LLC Miss case, data is returned from DRAM. .It Li RES_SNOOP_HIT_FWD A snoop was needed and data was forwarded from a remote socket. This includes: -Snoop Forward Clean, Left Shared (LLC Hit/Miss, IFetch/Data_RD/RFT). .It Li RES_SNOOP_HITM A snoop was needed and it HitM-ed in local or remote cache. HitM denotes a cache-line was in modified state before effect as a results of snoop. This includes: -Snoop HitM w/ WB (LLC miss, IFetch/Data_RD) -Snoop Forward Modified w/ Invalidation (LLC Hit/Miss, RFO) -Snoop MtoS (LLC Hit, IFetch/Data_RD). .It Li RES_NON_DRAM Target was non-DRAM system address. This includes MMIO transactions. .El .It Li cmask= Ns Ar value Configure the PMC to increment only if the number of configured events measured in a cycle is greater than or equal to .Ar value . .It Li edge Configure the PMC to count the number of de-asserted to asserted transitions of the conditions expressed by the other qualifiers. If specified, the counter will increment only once whenever a condition becomes true, irrespective of the number of clocks during which the condition remains true. .It Li inv Invert the sense of comparison when the .Dq Li cmask qualifier is present, making the counter increment when the number of events per cycle is less than the value specified by the .Dq Li cmask qualifier. .It Li os Configure the PMC to count events happening at processor privilege level 0. .It Li usr Configure the PMC to count events occurring at privilege levels 1, 2 or 3. .El .Pp If neither of the .Dq Li os or .Dq Li usr qualifiers are specified, the default is to enable both. .Ss Event Specifiers (Programmable PMCs) Sandy Bridge programmable PMCs support the following events: .Bl -tag -width indent .It Li LD_BLOCKS.DATA_UNKNOWN .Pq EVENT_03H, Umask 01H Blocked loads due to store buffer blocks with unknown data. .It Li LD_BLOCKS.STORE_FORWARD .Pq Event 03H, Umask 02H Loads blocked by overlapping with store buffer that cannot be forwarded. .It Li LD_BLOCKS.NO_SR .Pq Event 03H, Umask 08H # of Split loads blocked due to resource not available. .It Li LD_BLOCKS.ALL_BLOCK .Pq EVENT_03H, Umask 10H Number of cases where any load is blocked but has no DCU miss. .It Li MISALIGN_MEM_REF.LOADS .Pq Event 05H, Umask 01H Speculative cache-line split load uops dispatched to L1D. .It Li MISALIGN_MEM_REF.STORES .Pq Event 05H, Umask 02H Speculative cache-line split Store-address uops dispatched to L1D. .It Li LD_BLOCKS_PARTIAL.ADDRESS_ALIAS .Pq Event 07H, Umask 01H False dependencies in MOB due to partial compare on address. .It Li LD_BLOCKS_PARTIAL.ALL_STA_BLOCK .Pq Event 07H, Umask 08H The number of times that load operations are temporarily blocked because of older stores, with addresses that are not yet known. A load operation may incur more than one block of this type. .It LI DTLB_LOAD_MISSES.MISS_CAUSES_A_WALK .Pq Event 08H, Umask 01H Misses in all TLB levels that cause a page walk of any page size. .It Li DTLB_LOAD_MISSES.WALK_COMPLETED .Pq Event 08H, Umask 02H Misses in all TLB levels that caused page walk completed of any size. .It Li DTLB_LOAD_MISSES.WALK_DURATION .Pq Event 08H, Umask 04H Cycle PMH is busy with a walk. .It Li DTLB_LOAD_MISSES.STLB_HIT .Pq Event 08H, Umask 10H Number of cache load STLB hits. No page walk. .It Li INT_MISC.RECOVERY_CYCLES .Pq Event 0DH, Umask 03H Cycles waiting to recover after Machine Clears or JEClear. Set Cmask = 1. Set Edge to count occurrences .It Li INT_MISC.RAT_STALL_CYCLES .Pq Event 0DH, Umask 40H Cycles RAT external stall is sent to IDQ for this thread. .It Li UOPS_ISSUED.ANY .Pq Event 0EH, Umask 01H Increments each cycle the # of Uops issued by the RAT to RS. Set Cmask = 1, Inv = 1, Any= 1 to count stalled cycles of this core. Set Cmask = 1, Inv = 1 to count stalled cycles .It Li FP_COMP_OPS_EXE.X87 .Pq Event 10H, Umask 01H Counts number of X87 uops executed. .It Li FP_COMP_OPS_EXE.SSE_FP_PACKED_DOUBLE .Pq Event 10H, Umask 10H Counts number of SSE* double precision FP packed uops executed. .It Li FP_COMP_OPS_EXE.SSE_FP_SCALAR_SINGLE .Pq Event 10H, Umask 20H Counts number of SSE* single precision FP scalar uops executed. .It Li FP_COMP_OPS_EXE.SSE_PACKED_SINGLE .Pq Event 10H, Umask 40H Counts number of SSE* single precision FP packed uops executed. .It LiFP_COMP_OPS_EXE.SSE_SCALAR_DOUBLE .Pq Event 10H, Umask 80H Counts number of SSE* double precision FP scalar uops executed. .It Li SIMD_FP_256.PACKED_SINGLE .Pq Event 11H, Umask 01H Counts 256-bit packed single-precision floating-point instructions. .It Li SIMD_FP_256.PACKED_DOUBLE .Pq Event 11H, Umask 02H Counts 256-bit packed double-precision floating-point instructions. .It Li ARITH.FPU_DIV_ACTIVE .Pq Event 14H, Umask 01H Cycles that the divider is active, includes INT and FP. Set 'edge =1, cmask=1' to count the number of divides. .It Li INSTS_WRITTEN_TO_IQ.INSTS .Pq Event 17H, Umask 01H Counts the number of instructions written into the IQ every cycle. .It Li L2_RQSTS.DEMAND_DATA_RD_HIT .Pq Event 24H, Umask 01H Demand Data Read requests that hit L2 cache. .It Li L2_RQSTS.ALL_DEMAND_DATA_RD .Pq Event 24H, Umask 03H Counts any demand and L1 HW prefetch data load requests to L2. .It Li L2_RQSTS.RFO_HITS .Pq Event 24H, Umask 04H Counts the number of store RFO requests that hit the L2 cache. .It Li L2_RQSTS.RFO_MISS .Pq Event 24H, Umask 08H Counts the number of store RFO requests that miss the L2 cache. .It Li L2_RQSTS.ALL_RFO .Pq Event 24H, Umask 0CH Counts all L2 store RFO requests. .It Li L2_RQSTS.CODE_RD_HIT .Pq Event 24H, Umask 10H Number of instruction fetches that hit the L2 cache. .It Li L2_RQSTS.CODE_RD_MISS .Pq Event 24H, Umask 20H Number of instruction fetches that missed the L2 cache. .It Li L2_RQSTS.ALL_CODE_RD .Pq Event 24H, Umask 30H Counts all L2 code requests. .It Li L2_RQSTS.PF_HIT .Pq Event 24H, Umask 40H Requests from L2 Hardware prefetcher that hit L2. .It Li L2_RQSTS.PF_MISS .Pq Event 24H, Umask 80H Requests from L2 Hardware prefetcher that missed L2. .It Li L2_RQSTS.ALL_PF .Pq Event 24H, Umask C0H Any requests from L2 Hardware prefetchers. .It Li L2_STORE_LOCK_RQSTS.MISS .Pq Event 27H, Umask 01H RFOs that miss cache lines. .It Li L2_STORE_LOCK_RQSTS.HIT_E .Pq Event 27H, Umask 04H RFOs that hit cache lines in E state. .It Li L2_STORE_LOCK_RQSTS.HIT_M .Pq EVENT_27H, Umask 08H RFOs that hit cache lines in M state. .It Li L2_STORE_LOCK_RQSTS.ALL .Pq EVENT_27H, Umask 0FH RFOs that access cache lines in any state. .It Li L2_L1D_WB_RQSTS.HIT_E .Pq Event 28H, Umask 04H Not rejected writebacks from L1D to L2 cache lines in E state. .It Li L2_L1D_WB_RQSTS.HIT_M .Pq Event 28H, Umask 08H Not rejected writebacks from L1D to L2 cache lines in M state. .It Li LONGEST_LAT_CACHE.REFERENCE .Pq Event 2EH, Umask 4FH This event counts requests originating from the core that reference a cache line in the last level cache. .It Li LONGEST_LAT_CACHE.MISS .Pq Event 2EH, Umask 41H This event counts each cache miss condition for references to the last level cache. .It Li CPU_CLK_UNHALTED.THREAD_P .Pq Event 3CH, Umask 00H Counts the number of thread cycles while the thread is not in a halt state. The thread enters the halt state when it is running the HLT instruction. The core frequency may change from time to time due to power or thermal throttling. .It Li CPU_CLK_THREAD_UNHALTED.REF_XCLK .Pq Event 3CH, Umask 01H Increments at the frequency of XCLK (100 MHz) when not halted. .It Li L1D_PEND_MISS.PENDING .Pq Event 48H, Umask 01H Increments the number of outstanding L1D misses every cycle. Set Cmask = 1 and Edge =1 to count occurrences. Counter 2 only; Set Cmask = 1 to count cycles. .It Li DTLB_STORE_MISSES.MISS_CAUSES_A_WALK .Pq Event 49H, Umask 01H Miss in all TLB levels causes an page walk of any page size (4K/2M/4M/1G). .It Li DTLB_STORE_MISSES.WALK_COMPLETED .Pq Event 49H, Umask 02H Miss in all TLB levels causes a page walk that completes of any page size (4K/2M/4M/1G). .It Li DTLB_STORE_MISSES.WALK_DURATION .Pq Event 49H, Umask 04H Cycles PMH is busy with this walk. .It Li DTLB_STORE_MISSES.STLB_HIT .Pq Event 49H, Umask 10H Store operations that miss the first TLB level but hit the second and do not cause page walks. .It Li LOAD_HIT_PRE.SW_PF .Pq Event 4CH, Umask 01H Not SW-prefetch load dispatches that hit fill buffer allocated for S/W prefetch. .It Li LOAD_HIT_PER.HW_PF .Pq Event 4CH, Umask 02H Not SW-prefetch load dispatches that hit fill buffer allocated for H/W prefetch. .It Li HW_PRE_REQ.DL1_MISS .Pq Event 4EH, Umask 02H Hardware Prefetch requests that miss the L1D cache. A request is being counted each time it access the cache & miss it, including if a block is applicable or if hit the Fill Buffer for example. This accounts for both L1 streamer and IP-based (IPP) HW prefetchers. .It Li L1D.REPLACEMENT .Pq Event 51H, Umask 01H Counts the number of lines brought into the L1 data cache. .It Li L1D.ALLOCATED_IN_M .Pq Event 51H, Umask 02H Counts the number of allocations of modified L1D cache lines. .It Li L1D.EVICTION .Pq Event 51H, Umask 04H Counts the number of modified lines evicted from the L1 data cache due to replacement. .It Li L1D.ALL_M_REPLACEMENT .Pq Event 51H, Umask 08H Cache lines in M state evicted out of L1D due to Snoop HitM or dirty line replacement. .It Li PARTIAL_RAT_STALLS.FLAGS_MERGE_UOP .Pq Event 59H, Umask 20H Increments the number of flags-merge uops in flight each cycle. Set Cmask = 1 to count cycles. .It Li PARTIAL_RAT_STALLS.SLOW_LEA_WINDOW .Pq Event 59H, Umask 40H Cycles with at least one slow LEA uop allocated. .It Li PARTIAL_RAT_STALLS.MUL_SINGLE_UOP .Pq Event 59H, Umask 80H Number of Multiply packed/scalar single precision uops allocated. .It Li RESOURCE_STALLS2.ALL_FL_EMPTY .Pq Event 5BH, Umask 0CH Cycles stalled due to free list empty. .It Li RESOURCE_STALLS2.ALL_PRF_CONTROL .Pq Event 5BH, Umask 0FH Cycles stalled due to control structures full for physical registers. .It Li RESOURCE_STALLS2.BOB_FULL .Pq Event 5BH, Umask 40H Cycles Allocator is stalled due to Branch Order Buffer. .It Li RESOURCE_STALLS2.OOO_RSRC .Pq Event 5BH, Umask 4FH Cycles stalled due to out of order resources full. .It Li CPL_CYCLES.RING0 .Pq Event 5CH, Umask 01H Unhalted core cycles when the thread is in ring 0. Use Edge to count transition .It Li CPL_CYCLES.RING123 .Pq Event 5CH, Umask 02H Unhalted core cycles when the thread is not in ring 0. .It Li RS_EVENTS.EMPTY_CYCLES .Pq Event 5EH, Umask 01H Cycles the RS is empty for the thread. .It Li OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD .Pq Event 60H, Umask 01H Offcore outstanding Demand Data Read transactions in SQ to uncore. Set Cmask=1 to count cycles. .It Li OFFCORE_REQUESTS_OUTSTANDING.DEMAND_RFO .Pq Event 60H, Umask 04H Offcore outstanding RFO store transactions in SQ to uncore. Set Cmask=1 to count cycles. .It Li OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD .Pq Event 60H, Umask 08H Offcore outstanding cacheable data read transactions in SQ to uncore. Set Cmask=1 to count cycles. .It Li LOCK_CYCLES.SPLIT_LOCK_UC_LOCK_DURATION .Pq Event 63H, Umask 01H Cycles in which the L1D and L2 are locked, due to a UC lock or split lock. .It Li LOCK_CYCLES.CACHE_LOCK_DURATION .Pq Event 63H, Umask 02H Cycles in which the L1D is locked. .It Li IDQ.EMPTY .Pq Event 79H, Umask 02H Counts cycles the IDQ is empty. .It Li IQD.MITE_UOPS .Pq Event 79H, Umask 04H Increment each cycle # of uops delivered to IDQ from MITE path. Set Cmask = 1 to count cycles. Can combine Umask 04H and 20H .It Li IDQ.DSB_UOPS .Pq Event 79H, Umask 08H Increment each cycle. # of uops delivered to IDQ from DSB path. Set Cmask = 1 to count cycles. Can combine Umask 08H and 10H .It Li IDQ.MS_DSB_UOPS .Pq Event 79H, Umask 10H Increment each cycle # of uops delivered to IDQ when MS busy by DSB. Set Cmask = 1 to count cycles MS is busy. Set Cmask=1 and Edge=1 to count MS activations. Can combine Umask 08H and 10H .It Li IDQ.MS_MITE_UOPS .Pq Event 79H, Umask 20H Increment each cycle # of uops delivered to IDQ when MS is busy by MITE. Set Cmask = 1 to count cycles. Can combine Umask 04H and 20H .It Li IDQ.MS_UOPS .Pq Event 79H, Umask 30H Increment each cycle # of uops delivered to IDQ from MS by either DSB or MITE. Set Cmask = 1 to count cycles. Can combine Umask 04H, 08H and 30H .It Li ICACHE.MISSES .Pq Event 80H, Umask 02H Number of Instruction Cache, Streaming Buffer and Victim Cache Misses. Includes UC accesses. .It Li ITLB_MISSES.MISS_CAUSES_A_WALK .Pq Event 85H, Umask 01H Misses in all ITLB levels that cause page walks. .It Li ITLB_MISSES.WALK_COMPLETED .Pq Event 85H, Umask 02H Misses in all ITLB levels that cause completed page walks. .It Li ITLB_MISSES.WALK_DURATION .Pq Event 85H, Umask 04H Cycle PMH is busy with a walk. .It Li ITLB_MISSES.STLB_HIT .Pq Event 85H, Umask 10H Number of cache load STLB hits. No page walk. .It Li ILD_STALL.LCP .Pq Event 87H, Umask 01H Stalls caused by changing prefix length of the instruction. .It Li ILD_STALL.IQ_FULL .Pq Event 87H, Umask 04H Stall cycles due to IQ is full. -.It Li BR_INST_EXEC.COND -.Pq Event 88H, Umask 01H -Qualify conditional near branch instructions executed, but not necessarily -retired. -Must combine with umask 40H, 80H +.It Li BR_INST_EXEC.NONTAKEN_COND +.Pq Event 88H , Umask 41H +Count conditional near branch instructions that were executed (but not +necessarily retired) and not taken. +.It Li BR_INST_EXEC.TAKEN_COND +.Pq Event 88H , Umask 81H +Count conditional near branch instructions that were executed (but not +necessarily retired) and taken. .It Li BR_INST_EXEC.DIRECT_JMP -.Pq Event 88H, Umask 02H -Qualify all unconditional near branch instructions excluding calls and indirect -branches. -Must combine with umask 80H +.Pq Event 88H , Umask 82H +Count all unconditional near branch instructions excluding calls and +indirect branches. .It Li BR_INST_EXEC.INDIRECT_JMP_NON_CALL_RET -.Pq Event 88H, Umask 04H -Qualify executed indirect near branch instructions that are not calls nor +.Pq Event 88H , Umask 84H +Count executed indirect near branch instructions that are not calls nor returns. -Must combine with umask 80H .It Li BR_INST_EXEC.RETURN_NEAR -.Pq Event 88H, Umask 08H -Qualify indirect near branches that have a return mnemonic. -Must combine with umask 80H +.Pq Event 88H , Umask 88H +Count indirect near branches that have a return mnemonic. .It Li BR_INST_EXEC.DIRECT_NEAR_CALL -.Pq Event 88H, Umask 10H -Qualify unconditional near call branch instructions, excluding non call branch, -executed. -Must combine with umask 80H +.Pq Event 88H , Umask 90H +Count unconditional near call branch instructions, excluding non call +branch, executed. .It Li BR_INST_EXEC.INDIRECT_NEAR_CALL -.Pq Event 88H, Umask 20H -Qualify indirect near calls, including both register and memory indirect, +.Pq Event 88H , Umask A0H +Count indirect near calls, including both register and memory indirect, executed. -Must combine with umask 80H -.It Li BR_INST_EXEC.NONTAKEN -.Pq Event 88H, Umask 40H -Qualify non-taken near branches executed. -Applicable to umask 01H only -.It Li BR_INST_EXEC.TAKEN -.Pq Event 88H, Umask 80H -Qualify taken near branches executed. -Must combine with 01H,02H, 04H, 08H, 10H, 20H -.It Li BR_INST_EXE.ALL_BRANCHES -.Pq Event 88H, Umask FFH +.It Li BR_INST_EXEC.ALL_BRANCHES +.Pq Event 88H , Umask FFH Counts all near executed branches (not necessarily retired). -.It Li BR_MISP_EXEC.COND -.Pq Event 89H, Umask 01H -Qualify conditional near branch instructions mispredicted. -Must combine with umask 40H, 80H +.It Li BR_MISP_EXEC.NONTAKEN_COND +.Pq Event 89H , Umask 41H +Count conditional near branch instructions mispredicted as nontaken. +.It Li BR_MISP_EXEC.TAKEN_COND +.Pq Event 89H , Umask 81H +Count conditional near branch instructions mispredicted as taken. .It Li BR_MISP_EXEC.INDIRECT_JMP_NON_CALL_RET -.Pq Event 89H, Umask 04H -Qualify mispredicted indirect near branch instructions that are not calls nor -returns. -Must combine with umask 80H +.Pq Event 89H , Umask 84H +Count mispredicted indirect near branch instructions that are not calls +nor returns. .It Li BR_MISP_EXEC.RETURN_NEAR -.Pq Event 89H, Umask 08H -Qualify mispredicted indirect near branches that have a return mnemonic. -Must combine with umask 80H +.Pq Event 89H , Umask 88H +Count mispredicted indirect near branches that have a return mnemonic. .It Li BR_MISP_EXEC.DIRECT_NEAR_CALL -.Pq Event 89H, Umask 10H -Qualify mispredicted unconditional near call branch instructions, excluding non -call branch, executed. -Must combine with umask 80H +.Pq Event 89H , Umask 90H +Count mispredicted unconditional near call branch instructions, excluding +non call branch, executed. .It Li BR_MISP_EXEC.INDIRECT_NEAR_CALL -.Pq Event 89H, Umask 20H -Qualify mispredicted indirect near calls, including both register and memory +.Pq Event 89H , Umask A0H +Count mispredicted indirect near calls, including both register and memory indirect, executed. -Must combine with umask 80H -.It Li BR_MISP_EXEC.NONTAKEN -.Pq Event 89H, Umask 40H -Qualify mispredicted non-taken near branches executed. -Applicable to umask 01H only -.It Li BR_MISP_EXEC.TAKEN -.Pq Event 89H, Umask 80H -Qualify mispredicted taken near branches executed. -Must combine with 01H,02H, 04H, 08H, 10H, 20H .It Li BR_MISP_EXEC.ALL_BRANCHES -.Pq Event 89H, Umask FFH -Counts all near executed branches (not necessarily retired). +.Pq Event 89H , Umask FFH +Counts all mispredicted near executed branches (not necessarily retired). .It Li IDQ_UOPS_NOT_DELIVERED.CORE .Pq Event 9CH, Umask 01H Count number of non-delivered uops to RAT per thread. Use Cmask to qualify uop b/w .It Li UOPS_DISPATCHED_PORT.PORT_0 .Pq Event A1H, Umask 01H Cycles which a Uop is dispatched on port 0. .It Li UOPS_DISPATCHED_PORT.PORT_1 .Pq Event A1H, Umask 02H Cycles which a Uop is dispatched on port 1. .It Li UOPS_DISPATCHED_PORT.PORT_2_LD .Pq Event A1H, Umask 04H Cycles which a load uop is dispatched on port 2. .It Li UOPS_DISPATCHED_PORT.PORT_2_STA .Pq Event A1H, Umask 08H Cycles which a store address uop is dispatched on port 2. .It Li UOPS_DISPATCHED_PORT.PORT_2 .Pq Event A1H, Umask 0CH Cycles which a Uop is dispatched on port 2. .It Li UOPS_DISPATCHED_PORT.PORT_3_LD .Pq Event A1H, Umask 10H Cycles which a load uop is dispatched on port 3. .It Li UOPS_DISPATCHED_PORT.PORT_3_STA .Pq Event A1H, Umask 20H Cycles which a store address uop is dispatched on port 3. .It Li UOPS_DISPATCHED_PORT.PORT_3 .Pq Event A1H, Umask 30H .Pq Cycles which a Uop is dispatched on port 3. .It Li UOPS_DISPATCHED_PORT.PORT_4 .Pq Event A1H, Umask 40H Cycles which a Uop is dispatched on port 4. .It Li UOPS_DISPATCHED_PORT.PORT_5 .Pq Event A1H, Umask 80H Cycles which a Uop is dispatched on port 5. .It Li RESOURCE_STALLS.ANY .Pq Event A2H, Umask 01H Cycles Allocation is stalled due to Resource Related reason. .It Li RESOURCE_STALLS.LB .Pq Event A2H, Umask 02H Counts the cycles of stall due to lack of load buffers. .It Li RESOURCE_STALLS.LB .Pq Event A2H, Umask 04H Cycles stalled due to no eligible RS entry available. .It Li RESOURCE_STALLS.SB .Pq Event A2H, Umask 08H Cycles stalled due to no store buffers available. (not including draining form sync) .It Li RESOURCE_STALLS.ROB .Pq Event A2H, Umask 10H Cycles stalled due to re-order buffer full. .It Li RESOURCE_STALLS.FCSW .Pq Event A2H, Umask 20H Cycles stalled due to writing the FPU control word. .It Li RESOURCE_STALLS.MXCSR .Pq Event A2H, Umask 40H Cycles stalled due to the MXCSR register rename occurring to close to a previous MXCSR rename. .It Li RESOURCE_STALLS.OTHER .Pq Event A2H, Umask 80H Cycles stalled while execution was stalled due to other resource issues. .It Li DSB2MITE_SWITCHES.COUNT .Pq Event ABH, Umask 01H Number of DSB to MITE switches. .It Li DSB2MITE_SWITCHES.PENALTY_CYCLES .Pq Event ABH, Umask 02H Cycles DSB to MITE switches caused delay. .It Li DSB_FILL.OTHER_CANCEL .Pq Event ACH, Umask 02H Cases of cancelling valid DSB fill not because of exceeding way limit. .It Li DSB_FILL.EXCEED_DSB_LINES .Pq Event ACH, Umask 08H DSB Fill encountered > 3 DSB lines. .It Li DSB_FILL.ALL_CANCEL .Pq Event ACH, Umask 0AH Cases of cancelling valid Decode Stream Buffer (DSB) fill not because of exceeding way limit. .It Li ITLB.ITLB_FLUSH .Pq Event AEH, Umask 01H Counts the number of ITLB flushes, includes 4k/2M/4M pages. .It Li OFFCORE_REQUESTS.DEMAND_DATA_RD .Pq Event B0H, Umask 01H Demand data read requests sent to uncore. .It Li OFFCORE_REQUESTS.DEMAND_RFO .Pq Event B0H, Umask 04H Demand RFO read requests sent to uncore, including regular RFOs, locks, ItoM. .It Li OFFCORE_REQUESTS.ALL_DATA_RD .Pq Event B0H, Umask 08H Data read requests sent to uncore (demand and prefetch). .It Li UOPS_DISPATCHED.THREAD .Pq Event B1H, Umask 01H Counts total number of uops to be dispatched per-thread each cycle. Set Cmask = 1, INV =1 to count stall cycles. .It Li UOPS_DISPATCHED.CORE .Pq Event B1H, Umask 02H Counts total number of uops to be dispatched per-core each cycle. Do not need to set ANY .It Li OFFCORE_REQUESTS_BUFFER.SQ_FULL .Pq Event B2H, Umask 01H Offcore requests buffer cannot take more entries for this thread core. .It Li AGU_BYPASS_CANCEL.COUNT .Pq Event B6H, Umask 01H Counts executed load operations with all the following traits: 1. addressing of the format [base + offset], 2. the offset is between 1 and 2047, 3. the address specified in the base register is in one page and the address [base+offset] is in another page. .It Li OFF_CORE_RESPONSE_0 .Pq Event B7H, Umask 01H Off-core Response Performance Monitoring; PMC0 only. Requires programming MSR 01A6H .It Li OFF_CORE_RESPONSE_1 .Pq Event BBH, Umask 01H Off-core Response Performance Monitoring. PMC3 only. Requires programming MSR 01A7H .It Li TLB_FLUSH.DTLB_THREAD .Pq Event BDH, Umask 01H DTLB flush attempts of the thread-specific entries. .It Li TLB_FLUSH.STLB_ANY .Pq Event BDH, Umask 20H Count number of STLB flush attempts. .It Li L1D_BLOCKS.BANK_CONFLICT_CYCLES .Pq Event BFH, Umask 05H Cycles when dispatched loads are cancelled due to L1D bank conflicts with other load ports. cmask=1 .It Li INST_RETIRED.ANY_P .Pq Event C0H, Umask 00H Number of instructions at retirement. .It Li INST_RETIRED.PREC_DIST .Pq Event C0H, Umask 01H Precise instruction retired event with HW to reduce effect of PEBS shadow in IP distribution PMC1 only; Must quiesce other PMCs. .It Li INST_RETIRED.X87 .Pq Event C0H, Umask 02H X87 instruction retired event. .It Li OTHER_ASSISTS.ITLB_MISS_RETIRED .Pq Event C1H, Umask 02H Instructions that experienced an ITLB miss. .It Li OTHER_ASSISTS.AVX_STORE .Pq Event C1H, Umask 08H Number of assists associated with 256-bit AVX store operations. .It Li OTHER_ASSISTS.AVX_TO_SSE .Pq Event C1H, Umask 10H Number of transitions from AVX256 to legacy SSE when penalty applicable. .It Li OTHER_ASSISTS.SSE_TO_AVX .Pq Event C1H, Umask 20H Number of transitions from SSE to AVX-256 when penalty applicable. .It Li UOPS_RETIRED.ALL .Pq Event C2H, Umask 01H Counts the number of micro-ops retired. Use cmask=1 and invert to count active cycles or stalled cycles. .It Li UOPS_RETIRED.RETIRE_SLOTS .Pq Event C2H, Umask 02H Counts the number of retirement slots used each cycle. .It Li MACHINE_CLEARS.MEMORY_ORDERING .Pq Event C3H, Umask 02H Counts the number of machine clears due to memory order conflicts. .It Li MACHINE_CLEARS.SMC .Pq Event C3H, Umask 04H Counts the number of times that a program writes to a code section. .It Li MACHINE_CLEARS.MASKMOV .Pq Event C3H, Umask 20H Counts the number of executed AVX masked load operations that refer to an illegal address range with the mask bits set to 0. .It Li BR_INST_RETIRED.ALL_BRANCH .Pq Event C4H, Umask 00H Branch instructions at retirement. .It Li BR_INST_RETIRED.CONDITIONAL .Pq Event C4H, Umask 01H Counts the number of conditional branch instructions retired. .It Li BR_INST_RETIRED.NEAR_CALL .Pq Event C4H, Umask 02H Direct and indirect near call instructions retired. .It Li BR_INST_RETIRED.ALL_BRANCHES .Pq Event C4H, Umask 04H Counts the number of branch instructions retired. .It Li BR_INST_RETIRED.NEAR_RETURN .Pq Event C4H, Umask 08H Counts the number of near return instructions retired. .It Li BR_INST_RETIRED.NOT_TAKEN .Pq Event C4H, Umask 10H Counts the number of not taken branch instructions retired. .It Li BR_INST_RETIRED.NEAR_TAKEN .Pq Event C4H, Umask 20H Number of near taken branches retired. .It Li BR_INST_RETIRED.FAR_BRANCH .Pq Event C4H, Umask 40H Number of far branches retired. .It Li BR_MISP_RETIRED.ALL_BRANCHES .Pq Event C5H, Umask 00H Mispredicted branch instructions at retirement. .It Li BR_MISP_RETIRED.CONDITIONAL .Pq Event C5H, Umask 01H Mispredicted conditional branch instructions retired. .It Li BR_MISP_RETIRED.NEAR_CALL .Pq Event C5H, Umask 02H Direct and indirect mispredicted near call instructions retired. .It Li BR_MISP_RETIRED.ALL_BRANCH .Pq Event C5H, Umask 04H Mispredicted macro branch instructions retired. .It Li BR_MISP_RETIRED.NOT_TAKEN .Pq Event C5H, Umask 10H Mispredicted not taken branch instructions retired. .It Li BR_MISP_RETIRED.TAKEN .Pq Event C5H, Umask 20H Mispredicted taken branch instructions retired. .It Li FP_ASSIST.X87_OUTPUT .Pq Event CAH, Umask 02H Number of X87 assists due to output value. .It Li FP_ASSIST.X87_INPUT .Pq Event CAH, Umask 04H Number of X87 assists due to input value. .It Li FP_ASSIST.SIMD_OUTPUT .Pq Event CAH, Umask 08H Number of SIMD FP assists due to Output values. .It Li FP_ASSIST.SIMD_INPUT .Pq Event CAH, Umask 10H Number of SIMD FP assists due to input values. .It Li FP_ASSIST.ANY .Pq Event CAH, Umask 1EH Cycles with any input/output SSE* or FP assists. .It Li ROB_MISC_EVENTS.LBR_INSERTS .Pq Event CCH, Umask 20H Count cases of saving new LBR records by hardware. .It Li MEM_TRANS_RETIRED.LOAD_LATENCY .Pq Event CDH, Umask 01H Sample loads with specified latency threshold. PMC3 only. Specify threshold in MSR 0x3F6. .It Li MEM_TRANS_RETIRED.PRECISE_STORE .Pq Event CDH, Umask 02H Sample stores and collect precise store operation via PEBS record. PMC3 only. .It Li MEM_UOP_RETIRED.LOADS .Pq Event D0H, Umask 01H Qualify retired memory uops that are loads. Combine with umask 10H, 20H, 40H, 80H. .It Li MEM_UOP_RETIRED.STORES .Pq Event D0H, Umask 02H Qualify retired memory uops that are stores. Combine with umask 10H, 20H, 40H, 80H. .It Li MEM_UOP_RETIRED.STLB_MISS .Pq Event D0H, Umask 10H Qualify retired memory uops with STLB miss. Must combine with umask 01H, 02H, to produce counts. .It Li MEM_UOP_RETIRED.LOCK .Pq Event D0H, Umask 20H Qualify retired memory uops with lock. Must combine with umask 01H, 02H, to produce counts. .It Li MEM_UOP_RETIRED.SPLIT .Pq Event D0H, Umask 40H Qualify retired memory uops with line split. Must combine with umask 01H, 02H, to produce counts. .It Li MEM_UOP_RETIRED_ALL .Pq Event D0H, Umask 80H Qualify any retired memory uops. Must combine with umask 01H, 02H, to produce counts. .It Li MEM_LOAD_UOPS_RETIRED.L1_HIT .Pq Event D1H, Umask 01H Retired load uops with L1 cache hits as data sources. Must combine with umask 01H, 02H, to produce counts. .It Li MEM_LOAD_UOPS_RETIRED.L2_HIT .Pq Event D1H, Umask 02H Retired load uops with L2 cache hits as data sources. .It Li MEM_LOAD_UOPS_RETIRED.LLC_HIT .Pq Event D1H, Umask 04H Retired load uops which data sources were data hits in LLC without snoops required. .It Li MEM_LOAD_UOPS_RETIRED.HIT_LFB .Pq Event D1H, Umask 40H Retired load uops which data sources were load uops missed L1 but hit FB due to preceding miss to the same cache line with data not ready. .It Li MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_MISS .Pq Event D2H, Umask 01H Retired load uops which data sources were LLC hit and cross-core snoop missed in on-pkg core cache. .It Li MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HIT .Pq Event D2H, Umask 02H Retired load uops which data sources were LLC and cross-core snoop hits in on-pkg core cache. .It Li MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HITM .Pq Event D2H, Umask 04H Retired load uops which data sources were HitM responses from shared LLC. .It Li MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_NONE .Pq Event D2H, Umask 08H Retired load uops which data sources were hits in LLC without snoops required. .It Li MEM_LOAD_UOPS_LLC_HIT_RETIRED.LLC_MISS .Pq Event D4H, Umask 02H Retired load uops with unknown information as data source in cache serviced the load. .It Li L2_TRANS.DEMAND_DATA_RD .Pq Event F0H, Umask 01H Demand Data Read requests that access L2 cache. .It Li L2_TRANS.RF0 .Pq Event F0H, Umask 02H RFO requests that access L2 cache. .It Li L2_TRANS.CODE_RD .Pq Event F0H, Umask 04H L2 cache accesses when fetching instructions. .It Li L2_TRANS.ALL_PF .Pq Event F0H, Umask 08H L2 or LLC HW prefetches that access L2 cache. .It Li L2_TRANS.L1D_WB .Pq Event F0H, Umask 10H L1D writebacks that access L2 cache. .It Li L2_TRANS.L2_FILL .Pq Event F0H, Umask 20H L2 fill requests that access L2 cache. .It Li L2_TRANS.L2_WB .Pq Event F0H, Umask 40H L2 writebacks that access L2 cache. .It Li L2_TRANS.ALL_REQUESTS .Pq Event F0H, Umask 80H Transactions accessing L2 pipe. .It Li L2_LINES_IN.I .Pq Event F1H, Umask 01H L2 cache lines in I state filling L2. Counting does not cover rejects. .It Li L2_LINES_IN.S .Pq Event F1H, Umask 02H L2 cache lines in S state filling L2. Counting does not cover rejects. .It Li L2_LINES_IN.E .Pq Event F1H, Umask 04H L2 cache lines in E state filling L2. Counting does not cover rejects. .It Li L2_LINES-IN.ALL .Pq Event F1H, Umask 07H L2 cache lines filling L2. Counting does not cover rejects. .It Li L2_LINES_OUT.DEMAND_CLEAN .Pq Event F2H, Umask 01H Clean L2 cache lines evicted by demand. .It Li L2_LINES_OUT.DEMAND_DIRTY .Pq Event F2H, Umask 02H Dirty L2 cache lines evicted by demand. .It Li L2_LINES_OUT.PF_CLEAN .Pq Event F2H, Umask 04H Clean L2 cache lines evicted by L2 prefetch. .It Li L2_LINES_OUT.PF_DIRTY .Pq Event F2H, Umask 08H Dirty L2 cache lines evicted by L2 prefetch. .It Li L2_LINES_OUT.DIRTY_ALL .Pq Event F2H, Umask 0AH Dirty L2 cache lines filling the L2. Counting does not cover rejects. .It Li SQ_MISC.SPLIT_LOCK .Pq Event F4H, Umask 10H Split locks in SQ. .El .Sh SEE ALSO .Xr pmc 3 , .Xr pmc.atom 3 , .Xr pmc.core 3 , .Xr pmc.corei7 3 , .Xr pmc.corei7uc 3 , .Xr pmc.iaf 3 , .Xr pmc.ivybridge 3 , .Xr pmc.ivybridgexeon 3 , .Xr pmc.k7 3 , .Xr pmc.k8 3 , .Xr pmc.p4 3 , .Xr pmc.p5 3 , .Xr pmc.p6 3 , .Xr pmc.sandybridgeuc 3 , .Xr pmc.sandybridgexeon 3 , .Xr pmc.soft 3 , .Xr pmc.tsc 3 , .Xr pmc.ucf 3 , .Xr pmc.westmere 3 , .Xr pmc.westmereuc 3 , .Xr pmc_cpuinfo 3 , .Xr pmclog 3 , .Xr hwpmc 4 .Sh HISTORY The .Nm pmc library first appeared in .Fx 6.0 . .Sh AUTHORS The .Lb libpmc library was written by .An "Joseph Koshy" .Aq jkoshy@FreeBSD.org. The support for the Sandy Bridge microarchitecture was written by .An "Davide Italiano" .Aq davide@FreeBSD.org . Index: stable/10/lib/libpmc/pmc.sandybridgexeon.3 =================================================================== --- stable/10/lib/libpmc/pmc.sandybridgexeon.3 (revision 320105) +++ stable/10/lib/libpmc/pmc.sandybridgexeon.3 (revision 320106) @@ -1,1024 +1,1011 @@ .\" Copyright (c) 2012 Hiren Panchasara .\" All rights reserved. .\" .\" Redistribution and use in source and binary forms, with or without .\" modification, are permitted provided that the following conditions .\" are met: .\" 1. Redistributions of source code must retain the above copyright .\" notice, this list of conditions and the following disclaimer. .\" 2. Redistributions in binary form must reproduce the above copyright .\" notice, this list of conditions and the following disclaimer in the .\" documentation and/or other materials provided with the distribution. .\" .\" THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND .\" ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE .\" IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE .\" ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE .\" FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL .\" DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS .\" OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) .\" HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT .\" LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY .\" OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF .\" SUCH DAMAGE. .\" .\" $FreeBSD$ .\" .Dd October 18, 2012 .Dt PMC.SANDYBRIDGEXEON 3 .Os .Sh NAME .Nm pmc.sandybridgexeon .Nd measurement events for .Tn Intel .Tn Sandy Bridge Xeon family CPUs .Sh LIBRARY .Lb libpmc .Sh SYNOPSIS .In pmc.h .Sh DESCRIPTION .Tn Intel .Tn "Sandy Bridge Xeon" CPUs contain PMCs conforming to version 2 of the .Tn Intel performance measurement architecture. These CPUs may contain up to two classes of PMCs: .Bl -tag -width "Li PMC_CLASS_IAP" .It Li PMC_CLASS_IAF Fixed-function counters that count only one hardware event per counter. .It Li PMC_CLASS_IAP Programmable counters that may be configured to count one of a defined set of hardware events. .El .Pp The number of PMCs available in each class and their widths need to be determined at run time by calling .Xr pmc_cpuinfo 3 . .Pp Intel Sandy Bridge Xeon PMCs are documented in .Rs .%B "Intel(R) 64 and IA-32 Architectures Software Developer's Manual" .%T "Volume 3B: System Programming Guide, Part 2" .%N "Order Number: 253669-043US" .%D August 2012 .%Q "Intel Corporation" .Re .Ss SANDYBRIDGE XEON FIXED FUNCTION PMCS These PMCs and their supported events are documented in .Xr pmc.iaf 3 . .Ss SANDYBRIDGE XEON PROGRAMMABLE PMCS The programmable PMCs support the following capabilities: .Bl -column "PMC_CAP_INTERRUPT" "Support" .It Em Capability Ta Em Support .It PMC_CAP_CASCADE Ta \&No .It PMC_CAP_EDGE Ta Yes .It PMC_CAP_INTERRUPT Ta Yes .It PMC_CAP_INVERT Ta Yes .It PMC_CAP_READ Ta Yes .It PMC_CAP_PRECISE Ta \&No .It PMC_CAP_SYSTEM Ta Yes .It PMC_CAP_TAGGING Ta \&No .It PMC_CAP_THRESHOLD Ta Yes .It PMC_CAP_USER Ta Yes .It PMC_CAP_WRITE Ta Yes .El .Ss Event Qualifiers Event specifiers for these PMCs support the following common qualifiers: .Bl -tag -width indent .It Li rsp= Ns Ar value Configure the Off-core Response bits. .Bl -tag -width indent .It Li REQ_DMND_DATA_RD Counts the number of demand and DCU prefetch data reads of full and partial cachelines as well as demand data page table entry cacheline reads. Does not count L2 data read prefetches or instruction fetches. .It Li REQ_DMND_RFO Counts the number of demand and DCU prefetch reads for ownership (RFO) requests generated by a write to data cacheline. Does not count L2 RFO prefetches. .It Li REQ_DMND_IFETCH Counts the number of demand and DCU prefetch instruction cacheline reads. Does not count L2 code read prefetches. .It Li REQ_WB Counts the number of writeback (modified to exclusive) transactions. .It Li REQ_PF_DATA_RD Counts the number of data cacheline reads generated by L2 prefetchers. .It Li REQ_PF_RFO Counts the number of RFO requests generated by L2 prefetchers. .It Li REQ_PF_IFETCH Counts the number of code reads generated by L2 prefetchers. .It Li REQ_PF_LLC_DATA_RD L2 prefetcher to L3 for loads. .It Li REQ_PF_LLC_RFO RFO requests generated by L2 prefetcher .It Li REQ_PF_LLC_IFETCH L2 prefetcher to L3 for instruction fetches. .It Li REQ_BUS_LOCKS Bus lock and split lock requests. .It Li REQ_STRM_ST Streaming store requests. .It Li REQ_OTHER Any other request that crosses IDI, including I/O. .It Li RES_ANY Catch all value for any response types. .It Li RES_SUPPLIER_NO_SUPP No Supplier Information available. .It Li RES_SUPPLIER_LLC_HITM M-state initial lookup stat in L3. .It Li RES_SUPPLIER_LLC_HITE E-state. .It Li RES_SUPPLIER_LLC_HITS S-state. .It Li RES_SUPPLIER_LLC_HITF F-state. .It Li RES_SUPPLIER_LOCAL Local DRAM Controller. .It Li RES_SNOOP_SNP_NONE No details on snoop-related information. .It Li RES_SNOOP_SNP_NO_NEEDED No snoop was needed to satisfy the request. .It Li RES_SNOOP_SNP_MISS A snoop was needed and it missed all snooped caches: -For LLC Hit, ReslHitl was returned by all cores -For LLC Miss, Rspl was returned by all sockets and data was returned from DRAM. .It Li RES_SNOOP_HIT_NO_FWD A snoop was needed and it hits in at least one snooped cache. Hit denotes a cache-line was valid before snoop effect. This includes: -Snoop Hit w/ Invalidation (LLC Hit, RFO) -Snoop Hit, Left Shared (LLC Hit/Miss, IFetch/Data_RD) -Snoop Hit w/ Invalidation and No Forward (LLC Miss, RFO Hit S) In the LLC Miss case, data is returned from DRAM. .It Li RES_SNOOP_HIT_FWD A snoop was needed and data was forwarded from a remote socket. This includes: -Snoop Forward Clean, Left Shared (LLC Hit/Miss, IFetch/Data_RD/RFT). .It Li RES_SNOOP_HITM A snoop was needed and it HitM-ed in local or remote cache. HitM denotes a cache-line was in modified state before effect as a results of snoop. This includes: -Snoop HitM w/ WB (LLC miss, IFetch/Data_RD) -Snoop Forward Modified w/ Invalidation (LLC Hit/Miss, RFO) -Snoop MtoS (LLC Hit, IFetch/Data_RD). .It Li RES_NON_DRAM Target was non-DRAM system address. This includes MMIO transactions. .El .It Li cmask= Ns Ar value Configure the PMC to increment only if the number of configured events measured in a cycle is greater than or equal to .Ar value . .It Li edge Configure the PMC to count the number of de-asserted to asserted transitions of the conditions expressed by the other qualifiers. If specified, the counter will increment only once whenever a condition becomes true, irrespective of the number of clocks during which the condition remains true. .It Li inv Invert the sense of comparison when the .Dq Li cmask qualifier is present, making the counter increment when the number of events per cycle is less than the value specified by the .Dq Li cmask qualifier. .It Li os Configure the PMC to count events happening at processor privilege level 0. .It Li usr Configure the PMC to count events occurring at privilege levels 1, 2 or 3. .El .Pp If neither of the .Dq Li os or .Dq Li usr qualifiers are specified, the default is to enable both. .Ss Event Specifiers (Programmable PMCs) Sandy Bridge Xeon programmable PMCs support the following events: .Bl -tag -width indent .It Li LD_BLOCKS.DATA_UNKNOWN .Pq Event 03H , Umask 01H blocked loads due to store buffer blocks with unknown data. .It Li LD_BLOCKS.STORE_FORWARD .Pq Event 03H , Umask 02H loads blocked by overlapping with store buffer that cannot be forwarded . .It Li LD_BLOCKS.NO_SR .Pq Event 03H , Umask 08H # of Split loads blocked due to resource not available. .It Li LD_BLOCKS.ALL_BLOCK .Pq Event 03H , Umask 10H Number of cases where any load is blocked but has no DCU miss. .It Li MISALIGN_MEM_REF.LOADS .Pq Event 05H , Umask 01H Speculative cache-line split load uops dispatched to L1D. .It Li MISALIGN_MEM_REF.STORES .Pq Event 05H , Umask 02H Speculative cache-line split Store- address uops dispatched to L1D. .It Li LD_BLOCKS_PARTIAL.ADDRESS_ALIAS .Pq Event 07H , Umask 01H False dependencies in MOB due to partial compare on address. .It Li LD_BLOCKS_PARTIAL.ALL_STALL_BLOCK .Pq Event 07H , Umask 08H The number of times that load operations are temporarily blocked because of older stores, with addresses that are not yet known. A load operation may incur more than one block of this type. .It Li TLB_LOAD_MISSES.MISS_CAUSES_A_WALK .Pq Event 08H , Umask 01H Misses in all TLB levels that cause a page walk of any page size. .It Li TLB_LOAD_MISSES.WALK_COMPLETED .Pq Event 08H , Umask 02H Misses in all TLB levels that caused page walk completed of any size. .It Li DTLB_LOAD_MISSES.WALK_DURATION .Pq Event 08H , Umask 04H Cycle PMH is busy with a walk. .It Li DTLB_LOAD_MISSES.STLB_HIT .Pq Event 08H , Umask 10H Number of cache load STLB hits. No page walk. .It Li INT_MISC.RECOVERY_CYCLES .Pq Event 0DH , Umask 03H Cycles waiting to recover after Machine Clears or EClear. Set Cmask= 1. .It Li INT_MISC.RAT_STALL_CYCLES .Pq Event 0DH , Umask 40H Cycles RAT external stall is sent to IDQ for this thread. .It Li UOPS_ISSUED.ANY .Pq Event 0EH , Umask 01H Increments each cycle the # of Uops issued by the RAT to RS. Set Cmask = 1, Inv = 1, Any= 1to count stalled cycles of this core. .It Li FP_COMP_OPS_EXE.X87 .Pq Event 10H , Umask 01H Counts number of X87 uops executed. .It Li FP_COMP_OPS_EXE.SSE_FP_PACKED_DOUBLE .Pq Event 10H , Umask 10H Counts number of SSE* double precision FP packed uops executed. .It Li FP_COMP_OPS_EXE.SSE_FP_SCALAR_SINGLE .Pq Event 10H , Umask 20H Counts number of SSE* single precision FP scalar uops executed. .It Li FP_COMP_OPS_EXE.SSE_PACKED_SINGLE .Pq Event 10H , Umask 40H Counts number of SSE* single precision FP packed uops executed. .It Li FP_COMP_OPS_EXE.SSE_SCALAR_DOUBLE .Pq Event 10H , Umask 80H Counts number of SSE* double precision FP scalar uops executed. .It Li SIMD_FP_256.PACKED_SINGLE .Pq Event 11H , Umask 01H Counts 256-bit packed single-precision floating- point instructions. .It Li SIMD_FP_256.PACKED_DOUBLE .Pq Event 11H , Umask 02H Counts 256-bit packed double-precision floating- point instructions. .It Li ARITH.FPU_DIV_ACTIVE .Pq Event 14H , Umask 01H Cycles that the divider is active, includes INT and FP. Set 'edge =1, cmask=1' to count the number of divides. .It Li INSTS_WRITTEN_TO_IQ.INSTS .Pq Event 17H , Umask 01H Counts the number of instructions written into the IQ every cycle. .It Li L2_RQSTS.DEMAND_DATA_RD_HIT .Pq Event 24H , Umask 01H Demand Data Read requests that hit L2 cache. .It Li L2_RQSTS.ALL_DEMAND_DATA_RD .Pq Event 24H , Umask 03H Counts any demand and L1 HW prefetch data load requests to L2. .It Li L2_RQSTS.RFO_HITS .Pq Event 24H , Umask 04H Counts the number of store RFO requests that hit the L2 cache. .It Li L2_RQSTS.RFO_MISS .Pq Event 24H , Umask 08H Counts the number of store RFO requests that miss the L2 cache. .It Li L2_RQSTS.ALL_RFO .Pq Event 24H , Umask 0CH Counts all L2 store RFO requests. .It Li L2_RQSTS.CODE_RD_HIT .Pq Event 24H , Umask 10H Number of instruction fetches that hit the L2 cache. .It Li L2_RQSTS.CODE_RD_MISS .Pq Event 24H , Umask 20H Number of instruction fetches that missed the L2 cache. .It Li L2_RQSTS.ALL_CODE_RD .Pq Event 24H , Umask 30H Counts all L2 code requests. .It Li L2_RQSTS.PF_HIT .Pq Event 24H , Umask 40H Requests from L2 Hardware prefetcher that hit L2. .It Li L2_RQSTS.PF_MISS .Pq Event 24H , Umask 80H Requests from L2 Hardware prefetcher that missed L2. .It Li L2_RQSTS.ALL_PF .Pq Event 24H , Umask C0H Any requests from L2 Hardware prefetchers. .It Li L2_STORE_LOCK_RQSTS.MISS .Pq Event 27H , Umask 01H ROs that miss cache lines. .It Li L2_STORE_LOCK_RQSTS.HIT_E .Pq Event 27H , Umask 04H RFOs that hit cache lines in E state. .It Li L2_STORE_LOCK_RQSTS.HIT_M .Pq Event 27H , Umask 08H RFOs that hit cache lines in M state. .It Li L2_STORE_LOCK_RQSTS.ALL .Pq Event 27H , Umask 0FH RFOs that access cache lines in any state. .It Li L2_L1D_WB_RQSTS.MISS .Pq Event 28H , Umask 01H Not rejected writebacks from L1D to L2 cache lines that missed L2. .It Li L2_L1D_WB_RQSTS.HIT_S .Pq Event 28H , Umask 02H Not rejected writebacks from L1D to L2 cache lines in S state. .It Li L2_L1D_WB_RQSTS.HIT_E .Pq Event 28H , Umask 04H Not rejected writebacks from L1D to L2 cache lines in E state. .It Li L2_L1D_WB_RQSTS.HIT_M .Pq Event 28H , Umask 08H Not rejected writebacks from L1D to L2 cache lines in M state. .It Li L2_L1D_WB_RQSTS.ALL .Pq Event 28H , Umask 0FH Not rejected writebacks from L1D to L2 cache. .It Li LONGEST_LAT_CACHE.REFERENCE .Pq Event 2EH , Umask 4FH This event counts requests originating from the core that reference a cache line in the last level cache. .It Li LONGEST_LAT_CACHE.MISS .Pq Event 2EH , Umask 41H This event counts each cache miss condition for references to the last level cache. .It Li CPU_CLK_UNHALTED.THREAD_P .Pq Event 3CH , Umask 00H Counts the number of thread cycles while the thread is not in a halt state. The thread enters the halt state when it is running the HLT instruction. The core frequency may change from time to time due to power or thermal throttling. .It Li CPU_CLK_THREAD_UNHALTED.REF_XCLK .Pq Event 3CH , Umask 01H Increments at the frequency of XCLK (100 MHz) when not halted. .It Li L1D_PEND_MISS.PENDING .Pq Event 48H , Umask 01H Increments the number of outstanding L1D misses every cycle. Set Cmaks = 1 and Edge =1 to count occurrences. .It Li DTLB_STORE_MISSES.MISS_CAUSES_A_WALK .Pq Event 49H , Umask 01H Miss in all TLB levels causes an page walk of any page size (4K/2M/4M/1G). .It Li DTLB_STORE_MISSES.WALK_COMPLETED .Pq Event 49H , Umask 02H Miss in all TLB levels causes a page walk that completes of any page size (4K/2M/4M/1G). .It Li DTLB_STORE_MISSES.WALK_DURATION .Pq Event 49H , Umask 04H Cycles PMH is busy with this walk. .It Li DTLB_STORE_MISSES.STLB_HIT .Pq Event 49H , Umask 10H Store operations that miss the first TLB level but hit the second and do not cause page walks. .It Li LOAD_HIT_PRE.SW_PF .Pq Event 4CH , Umask 01H Not SW-prefetch load dispatches that hit fill buffer allocated for S/W prefetch. .It Li LOAD_HIT_PER.HW_PF .Pq Event 4CH , Umask 02H Not SW-prefetch load dispatches that hit fill buffer allocated for H/W prefetch. .It Li HW_PRE_REQ.DL1_MISS .Pq Event 4EH , Umask 02H Hardware Prefetch requests that miss the L1D cache. A request is being counted each time it access the cache & miss it, including if a block is applicable or if hit the Fill Buffer for example. .It Li L1D.REPLACEMENT .Pq Event 51H , Umask 01H Counts the number of lines brought into the L1 data cache. .It Li L1D.ALLOCATED_IN_M .Pq Event 51H , Umask 02H Counts the number of allocations of modified L1D cache lines. .It Li L1D.EVICTION .Pq Event 51H , Umask 04H Counts the number of modified lines evicted from the L1 data cache due to replacement. .It Li L1D.ALL_M_REPLACEMENT .Pq Event 51H , Umask 08H Cache lines in M state evicted out of L1D due to Snoop HitM or dirty line replacement. .It Li PARTIAL_RAT_STALLS.FLAGS_MERGE_UOP .Pq Event 59H , Umask 0CH Increments the number of flags-merge uops in flight each cycle. Set Cmask = 1 to count cycles. .It Li PARTIAL_RAT_STALLS.SLOW_LEA_WINDOW .Pq Event 59H , Umask 0FH Cycles with at least one slow LEA uop allocated. .It Li PARTIAL_RAT_STALLS.MUL_SINGLE_UOP .Pq Event 59H , Umask 40H Number of Multiply packed/scalar single precision uops allocated. .It Li RESOURCE_STALLS2.ALL_FL_EMPTY .Pq Event 5BH , Umask 0CH Cycles stalled due to free list empty. .It Li RESOURCE_STALLS2.ALL_PRF_CONTROL .Pq Event 5BH , Umask 0FH Cycles stalled due to control structures full for physical registers. .It Li RESOURCE_STALLS2.BOB_FULL .Pq Event 5BH , Umask 40H Cycles Allocator is stalled due Branch Order Buffer. .It Li RESOURCE_STALLS2.OOO_RSRC .Pq Event 5BH , Umask 4FH Cycles stalled due to out of order resources full. .It Li CPL_CYCLES.RING0 .Pq Event 5CH , Umask 01H Unhalted core cycles when the thread is in ring 0. .It Li CPL_CYCLES.RING123 .Pq Event 5CH , Umask 02H Unhalted core cycles when the thread is not in ring 0. .It Li RS_EVENTS.EMPTY_CYCLES .Pq Event 5EH , Umask 01H Cycles the RS is empty for the thread. .It Li OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD .Pq Event 60H , Umask 01H Offcore outstanding Demand Data Read transactions in SQ to uncore. Set Cmask=1 to count cycles. .It Li OFFCORE_REQUESTS_OUTSTANDING.DEMAND_RFO .Pq Event 60H , Umask 04H Offcore outstanding RFO store transactions in SQ to uncore. Set Cmask=1 to count cycles. .It Li OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD .Pq Event 60H , Umask 08H Offcore outstanding cacheable data read transactions in SQ to uncore. Set Cmask=1 to count cycles. .It Li LOCK_CYCLES.SPLIT_LOCK_UC_LOCK_DURATION .Pq Event 63H , Umask 01H Cycles in which the L1D and L2 are locked, due to a UC lock or split lock. .It Li LOCK_CYCLES.CACHE_LOCK_DURATION .Pq Event 63H , Umask 02H Cycles in which the L1D is locked. .It Li IDQ.EMPTY .Pq Event 79H , Umask 02H Counts cycles the IDQ is empty. .It Li IDQ.MITE_UOPS .Pq Event 79H , Umask 04H Increment each cycle # of uops delivered to IDQ from MITE path. Set Cmask = 1 to count cycles. .It Li IDQ.DSB_UOPS .Pq Event 79H , Umask 08H Increment each cycle. # of uops delivered to IDQ from DSB path. Set Cmask = 1 to count cycles. .It Li IDQ.MS_DSB_UOPS .Pq Event 79H , Umask 10H Increment each cycle # of uops delivered to IDQ when MS busy by DSB. Set Cmask = 1 to count cycles MS is busy. Set Cmask=1 and Edge =1 to count MS activations. .It Li IDQ.MS_MITE_UOPS .Pq Event 79H , Umask 20H Increment each cycle # of uops delivered to IDQ when MS is busy by MITE. Set Cmask = 1 to count cycles. .It Li IDQ.MS_UOPS .Pq Event 79H , Umask 30H Increment each cycle # of uops delivered to IDQ from MS by either DSB or MITE. Set Cmask = 1 to count cycles. .It Li ICACHE.MISSES .Pq Event 80H , Umask 02H Number of Instruction Cache, Streaming Buffer and Victim Cache Misses. Includes UC accesses. .It Li ITLB_MISSES.MISS_CAUSES_A_WALK .Pq Event 85H , Umask 01H Misses in all ITLB levels that cause page walks. .It Li ITLB_MISSES.WALK_COMPLETED .Pq Event 85H , Umask 02H Misses in all ITLB levels that cause completed page walks. .It Li ITLB_MISSES.WALK_DURATION .Pq Event 85H , Umask 04H Cycle PMH is busy with a walk. .It Li ITLB_MISSES.STLB_HIT .Pq Event 85H , Umask 10H Number of cache load STLB hits. No page walk. .It Li ILD_STALL.LCP .Pq Event 87H , Umask 01H Stalls caused by changing prefix length of the instruction. .It Li ILD_STALL.IQ_FULL .Pq Event 87H , Umask 04H Stall cycles due to IQ is full. -.It Li BR_INST_EXEC.COND -.Pq Event 88H , Umask 01H -Qualify conditional near branch instructions -executed, but not necessarily retired. +.It Li BR_INST_EXEC.NONTAKEN_COND +.Pq Event 88H , Umask 41H +Count conditional near branch instructions that were executed (but not +necessarily retired) and not taken. +.It Li BR_INST_EXEC.TAKEN_COND +.Pq Event 88H , Umask 81H +Count conditional near branch instructions that were executed (but not +necessarily retired) and taken. .It Li BR_INST_EXEC.DIRECT_JMP -.Pq Event 88H , Umask 02H -Qualify all unconditional near branch instructions -excluding calls and indirect branches. +.Pq Event 88H , Umask 82H +Count all unconditional near branch instructions excluding calls and +indirect branches. .It Li BR_INST_EXEC.INDIRECT_JMP_NON_CALL_RET -.Pq Event 88H , Umask 04H -Qualify executed indirect near branch instructions -that are not calls nor returns. +.Pq Event 88H , Umask 84H +Count executed indirect near branch instructions that are not calls nor +returns. .It Li BR_INST_EXEC.RETURN_NEAR -.Pq Event 88H , Umask 08H -Qualify indirect near branches that have a return -mnemonic. +.Pq Event 88H , Umask 88H +Count indirect near branches that have a return mnemonic. .It Li BR_INST_EXEC.DIRECT_NEAR_CALL -.Pq Event 88H , Umask 10H -Qualify unconditional near call branch instructions, -excluding non call branch, executed. +.Pq Event 88H , Umask 90H +Count unconditional near call branch instructions, excluding non call +branch, executed. .It Li BR_INST_EXEC.INDIRECT_NEAR_CALL -.Pq Event 88H , Umask 20H -Qualify indirect near calls, including both register -and memory indirect, executed. -.It Li BR_INST_EXEC.NONTAKEN -.Pq Event 88H , Umask 40H -Qualify non-taken near branches executed. -.It Li BR_INST_EXEC.TAKEN -.Pq Event 88H , Umask 80H -Qualify taken near branches executed. Must -combine with 01H,02H, 04H, 08H, 10H, 20H. -.It Li BR_INST_EXE.ALL_BRANCHES +.Pq Event 88H , Umask A0H +Count indirect near calls, including both register and memory indirect, +executed. +.It Li BR_INST_EXEC.ALL_BRANCHES .Pq Event 88H , Umask FFH -Counts all near executed branches (not necessarily -retired). -.It Li BR_MISP_EXEC.COND -.Pq Event 89H , Umask 01H -Qualify conditional near branch instructions -mispredicted. +Counts all near executed branches (not necessarily retired). +.It Li BR_MISP_EXEC.NONTAKEN_COND +.Pq Event 89H , Umask 41H +Count conditional near branch instructions mispredicted as nontaken. +.It Li BR_MISP_EXEC.TAKEN_COND +.Pq Event 89H , Umask 81H +Count conditional near branch instructions mispredicted as taken. .It Li BR_MISP_EXEC.INDIRECT_JMP_NON_CALL_RET -.Pq Event 89H , Umask 04H -Qualify mispredicted indirect near branch -instructions that are not calls nor returns. +.Pq Event 89H , Umask 84H +Count mispredicted indirect near branch instructions that are not calls +nor returns. .It Li BR_MISP_EXEC.RETURN_NEAR -.Pq Event 89H , Umask 08H -Qualify mispredicted indirect near branches that -have a return mnemonic. +.Pq Event 89H , Umask 88H +Count mispredicted indirect near branches that have a return mnemonic. .It Li BR_MISP_EXEC.DIRECT_NEAR_CALL -.Pq Event 89H , Umask 10H -Qualify mispredicted unconditional near call branch -instructions, excluding non call branch, executed. +.Pq Event 89H , Umask 90H +Count mispredicted unconditional near call branch instructions, excluding +non call branch, executed. .It Li BR_MISP_EXEC.INDIRECT_NEAR_CALL -.Pq Event 89H , Umask 20H -Qualify mispredicted indirect near calls, including -both register and memory indirect, executed. -.It Li BR_MISP_EXEC.NONTAKEN -.Pq Event 89H , Umask 40H -Qualify mispredicted non-taken near branches -executed,. -.It Li BR_MISP_EXEC.TAKEN -.Pq Event 89H , Umask 80H -Qualify mispredicted taken near branches executed. -Must combine with 01H,02H, 04H, 08H, 10H, 20H +.Pq Event 89H , Umask A0H +Count mispredicted indirect near calls, including both register and memory +indirect, executed. .It Li BR_MISP_EXEC.ALL_BRANCHES .Pq Event 89H , Umask FFH -Counts all near executed branches (not necessarily -retired). +Counts all mispredicted near executed branches (not necessarily retired). .It Li IDQ_UOPS_NOT_DELIVERED.CORE .Pq Event 9CH , Umask 01H Count number of non-delivered uops to RAT per thread. .It Li UOPS_DISPATCHED_PORT.PORT_0 .Pq Event A1H , Umask 01H Cycles which a Uop is dispatched on port 0. .It Li UOPS_DISPATCHED_PORT.PORT_1 .Pq Event A1H , Umask 02H Cycles which a Uop is dispatched on port 1. .It Li UOPS_DISPATCHED_PORT.PORT_2_LD .Pq Event A1H , Umask 04H Cycles which a load uop is dispatched on port 2. .It Li UOPS_DISPATCHED_PORT.PORT_2_STA .Pq Event A1H , Umask 08H Cycles which a store address uop is dispatched on port 2. .It Li UOPS_DISPATCHED_PORT.PORT_2 .Pq Event A1H , Umask 0CH Cycles which a Uop is dispatched on port 2. .It Li UOPS_DISPATCHED_PORT.PORT_3_LD .Pq Event A1H , Umask 10H Cycles which a load uop is dispatched on port 3. .It Li UOPS_DISPATCHED_PORT.PORT_3_STA .Pq Event A1H , Umask 20H Cycles which a store address uop is dispatched on port 3. .It Li UOPS_DISPATCHED_PORT.PORT_3 .Pq Event A1H , Umask 30H Cycles which a Uop is dispatched on port 3. .It Li UOPS_DISPATCHED_PORT.PORT_4 .Pq Event A1H , Umask 40H Cycles which a Uop is dispatched on port 4. .It Li UOPS_DISPATCHED_PORT.PORT_5 .Pq Event A1H , Umask 80H Cycles which a Uop is dispatched on port 5. .It Li RESOURCE_STALLS.ANY .Pq Event A2H , Umask 01H Cycles Allocation is stalled due to Resource Related reason. .It Li RESOURCE_STALLS.LB .Pq Event A2H , Umask 01H Counts the cycles of stall due to lack of load buffers. .It Li RESOURCE_STALLS.RS .Pq Event A2H , Umask 04H Cycles stalled due to no eligible RS entry available. .It Li RESOURCE_STALLS.SB .Pq Event A2H , Umask 08H Cycles stalled due to no store buffers available. (not including draining form sync). .It Li RESOURCE_STALLS.ROB .Pq Event A2H , Umask 10H Cycles stalled due to re-order buffer full. .It Li RESOURCE_STALLS.FCSW .Pq Event A2H , Umask 20H Cycles stalled due to writing the FPU control word. .It Li RESOURCE_STALLS.MXCSR .Pq Event A2H , Umask 40H Cycles stalled due to the MXCSR register rename occurring to close to a previous MXCSR rename. .It Li RESOURCE_STALLS.OTHER .Pq Event A2H , Umask 80H Cycles stalled while execution was stalled due to other resource issues. .It Li CYCLE_ACTIVITY.CYCLES_L2_PENDING .Pq Event A3H , Umask 01H Cycles with pending L2 miss loads. Set AnyThread to count per core. .It Li CYCLE_ACTIVITY.CYCLES_L1D_PENDING .Pq Event A3H , Umask 02H Cycles with pending L1 cache miss loads.Set AnyThread to count per core. .It Li CYCLE_ACTIVITY.CYCLES_NO_DISPATCH .Pq Event A3H , Umask 04H Cycles of dispatch stalls. Set AnyThread to count per core. .It Li DSB2MITE_SWITCHES.COUNT .Pq Event ABH , Umask 01H Number of DSB to MITE switches. .It Li DSB2MITE_SWITCHES.PENALTY_CYCLES .Pq Event ABH , Umask 02H Cycles DSB to MITE switches caused delay. .It Li DSB_FILL.OTHER_CANCEL .Pq Event ACH , Umask 02H Cases of cancelling valid DSB fill not because of exceeding way limit. .It Li DSB_FILL.EXCEED_DSB_LINES .Pq Event ACH , Umask 08H DSB Fill encountered > 3 DSB lines. .It Li DSB_FILL.ALL_CANCEL .Pq Event ACH , Umask 0AH Cases of cancelling valid Decode Stream Buffer (DSB) fill not because of exceeding way limit. .It Li ITLB.ITLB_FLUSH .Pq Event AEH , Umask 01H Counts the number of ITLB flushes, includes 4k/2M/4M pages. .It Li OFFCORE_REQUESTS.DEMAND_DATA_RD .Pq Event B0H , Umask 01H Demand data read requests sent to uncore. .It Li OFFCORE_REQUESTS.DEMAND_RFO .Pq Event B0H , Umask 04H Demand RFO read requests sent to uncore, including regular RFOs, locks, ItoM. .It Li OFFCORE_REQUESTS.ALL_DATA_RD .Pq Event B0H , Umask 08H Data read requests sent to uncore (demand and prefetch). .It Li UOPS_DISPATCHED.THREAD .Pq Event B1H , Umask 01H Counts total number of uops to be dispatched per- thread each cycle. Set Cmask = 1, INV =1 to count stall cycles. .It Li UOPS_DISPATCHED.CORE .Pq Event B1H , Umask 02H Counts total number of uops to be dispatched per- core each cycle. .It Li OFFCORE_REQUESTS_BUFFER.SQ_FULL .Pq Event B2H , Umask 01H Offcore requests buffer cannot take more entries for this thread core. .It Li AGU_BYPASS_CANCEL.COUNT .Pq Event B6H , Umask 01H Counts executed load operations with all the following traits: 1. addressing of the format [base + offset], 2. the offset is between 1 and 2047, 3. the address specified in the base register is in one page and the address [base+offset] is in another page. .It Li OFF_CORE_RESPONSE_0 .Pq Event B7H , Umask 01H (Event B7H, Umask 01H) Off-core Response Performance Monitoring; PMC0 only. Requires programming MSR 01A6H .It Li OFF_CORE_RESPONSE_1 .Pq Event BBH , Umask 01H (Event BBH, Umask 01H) Off-core Response Performance Monitoring; PMC3 only. Requires programming MSR 01A7H .It Li TLB_FLUSH.DTLB_THREAD .Pq Event BDH , Umask 01H DTLB flush attempts of the thread-specific entries. .It Li TLB_FLUSH.STLB_ANY .Pq Event BDH , Umask 20H Count number of STLB flush attempts. .It Li L1D_BLOCKS.BANK_CONFLICT_CYCLES .Pq Event BFH , Umask 05H Cycles when dispatched loads are cancelled due to L1D bank conflicts with other load ports. .It Li INST_RETIRED.ANY_P .Pq Event C0H , Umask 00H Number of instructions at retirement. .It Li INST_RETIRED.ALL .Pq Event C0H , Umask 01H Precise instruction retired event with HW to reduce effect of PEBS shadow in IP distribution. .It Li OTHER_ASSISTS.ITLB_MISS_RETIRED .Pq Event C1H , Umask 02H Instructions that experienced an ITLB miss. .It Li OTHER_ASSISTS.AVX_STORE .Pq Event C1H , Umask 08H Number of assists associated with 256-bit AVX store operations. .It Li OTHER_ASSISTS.AVX_TO_SSE .Pq Event C1H , Umask 10H Number of transitions from AVX-256 to legacy SSE when penalty applicable. .It Li OTHER_ASSISTS.SSE_TO_AVX .Pq Event C1H , Umask 20H Number of transitions from SSE to AVX-256 when penalty applicable. .It Li UOPS_RETIRED.ALL .Pq Event C2H , Umask 01H Counts the number of micro-ops retired, Use cmask=1 and invert to count active cycles or stalled cycles. .It Li UOPS_RETIRED.RETIRE_SLOTS .Pq Event C2H , Umask 02H Counts the number of retirement slots used each cycle. .It Li MACHINE_CLEARS.MEMORY_ORDERING .Pq Event C3H , Umask 02H Counts the number of machine clears due to memory order conflicts. .It Li MACHINE_CLEARS.SMC .Pq Event C3H , Umask 04H Counts the number of times that a program writes to a code section. .It Li MACHINE_CLEARS.MASKMOV .Pq Event C3H , Umask 20H Counts the number of executed AVX masked load operations that refer to an illegal address range with the mask bits set to 0. .It Li BR_INST_RETIRED.ALL_BRANCH .Pq Event C4H , Umask 00H Branch instructions at retirement. .It Li BR_INST_RETIRED.CONDITIONAL .Pq Event C4H , Umask 01H Counts the number of conditional branch instructions retired. .It Li BR_INST_RETIRED.NEAR_CALL .Pq Event C4H , Umask 02H Direct and indirect near call instructions retired. .It Li BR_INST_RETIRED.ALL_BRANCHES .Pq Event C4H , Umask 04H Counts the number of branch instructions retired. .It Li BR_INST_RETIRED.NEAR_RETURN .Pq Event C4H , Umask 08H Counts the number of near return instructions retired. .It Li BR_INST_RETIRED.NOT_TAKEN .Pq Event C4H , Umask 10H Counts the number of not taken branch instructions retired. .It Li BR_INST_RETIRED.NEAR_TAKEN .Pq Event C4H , Umask 20H Number of near taken branches retired. .It Li BR_INST_RETIRED.FAR_BRANCH .Pq Event C4H , Umask 40H Number of far branches retired. .It Li BR_MISP_RETIRED.ALL_BRANCHES .Pq Event C5H , Umask 00H Mispredicted branch instructions at retirement. .It Li BR_MISP_RETIRED.CONDITIONAL .Pq Event C5H , Umask 01H Mispredicted conditional branch instructions retired. .It Li BR_MISP_RETIRED.NEAR_CALL .Pq Event C5H , Umask 02H Direct and indirect mispredicted near call instructions retired. .It Li BR_MISP_RETIRED.ALL_BRANCHES .Pq Event C5H , Umask 04H Mispredicted macro branch instructions retired. .It Li BR_MISP_RETIRED.NOT_TAKEN .Pq Event C5H , Umask 10H Mispredicted not taken branch instructions retired. .It Li BR_MISP_RETIRED.TAKEN .Pq Event C5H , Umask 20H Mispredicted taken branch instructions retired. .It Li FP_ASSIST.X87_OUTPUT .Pq Event CAH , Umask 02H Number of X87 assists due to output value. .It Li FP_ASSIST.X87_INPUT .Pq Event CAH , Umask 04H Number of X87 assists due to input value. .It Li FP_ASSIST.SIMD_OUTPUT .Pq Event CAH , Umask 08H Number of SIMD FP assists due to output values. .It Li FP_ASSIST.SIMD_INPUT .Pq Event CAH , Umask 10H Number of SIMD FP assists due to input values. .It Li FP_ASSIST.ANY 1EH .Pq Event CAH , Umask Cycles with any input/output SSE* or FP assists. .It Li ROB_MISC_EVENTS.LBR_INSERTS .Pq Event CCH , Umask 20H Count cases of saving new LBR records by hardware. .It Li MEM_TRANS_RETIRED.LOAD_LATENCY .Pq Event CDH , Umask 01H Sample loads with specified latency threshold. PMC3 only. .It Li MEM_TRANS_RETIRED.PRECISE_STORE .Pq Event CDH , Umask 02H Sample stores and collect precise store operation via PEBS record. PMC3 only. .It Li MEM_UOP_RETIRED.LOADS .Pq Event D0H , Umask 10H Qualify retired memory uops that are loads. Combine with umask 10H, 20H, 40H, 80H. .It Li MEM_UOP_RETIRED.STORES .Pq Event D0H , Umask 02H Qualify retired memory uops that are stores. Combine with umask 10H, 20H, 40H, 80H. .It Li MEM_UOP_RETIRED.STLB_MISS .Pq Event D0H , Umask Qualify retired memory uops with STLB miss. Must combine with umask 01H, 02H, to produce counts. .It Li MEM_UOP_RETIRED.LOCK .Pq Event D0H , Umask Qualify retired memory uops with lock. Must combine with umask 01H, 02H, to produce counts. .It Li MEM_UOP_RETIRED.SPLIT .Pq Event D0H , Umask Qualify retired memory uops with line split. Must combine with umask 01H, 02H, to produce counts. .It Li MEM_UOP_RETIRED_ALL .Pq Event D0H , Umask Qualify any retired memory uops. Must combine with umask 01H, 02H, to produce counts. .It Li MEM_LOAD_UOPS_RETIRED.L1_HIT .Pq Event D1H , Umask 01H Retired load uops with L1 cache hits as data sources. .It Li MEM_LOAD_UOPS_RETIRED.L2_HIT .Pq Event D1H , Umask 02H Retired load uops with L2 cache hits as data sources. .It Li MEM_LOAD_UOPS_RETIRED.LLC_HIT .Pq Event D1H , Umask 04H Retired load uops which data sources were data hits in LLC without snoops required. .It Li MEM_LOAD_UOPS_RETIRED.LLC_MISS .Pq Event D1H , Umask 20H Retired load uops which data sources were data missed LLC (excluding unknown data source). .It Li MEM_LOAD_UOPS_RETIRED.HIT_LFB .Pq Event D1H , Umask 40H Retired load uops which data sources were load uops missed L1 but hit FB due to preceding miss to the same cache line with data not ready. .It Li MEM_LOAD_UOPS_MISC_RETIRED.LLC_MISS .Pq Event D4H , Umask 02H Retired load uops with unknown information as data source in cache serviced the load. .It Li BACLEARS.ANY .Pq Event E6H , Umask 01H Counts the number of times the front end is re- steered, mainly when the BPU cannot provide a correct prediction and this is corrected by other branch handling mechanisms at the front end. .It Li L2_TRANS.DEMAND_DATA_RD .Pq Event F0H , Umask 01H Demand Data Read requests that access L2 cache. .It Li L2_TRANS.RFO .Pq Event F0H , Umask 02H RFO requests that access L2 cache. .It Li L2_TRANS.CODE_RD .Pq Event F0H , Umask 04H L2 cache accesses when fetching instructions. .It Li L2_TRANS.ALL_PF .Pq Event F0H , Umask 08H L2 or LLC HW prefetches that access L2 cache. .It Li L2_TRANS.L1D_WB .Pq Event F0H , Umask 10H L1D writebacks that access L2 cache. .It Li L2_TRANS.L2_FILL .Pq Event F0H , Umask 20H L2 fill requests that access L2 cache. .It Li L2_TRANS.L2_WB .Pq Event F0H , Umask 40H L2 writebacks that access L2 cache. .It Li L2_TRANS.ALL_REQUESTS .Pq Event F0H , Umask 80H Transactions accessing L2 pipe. .It Li L2_LINES_IN.I .Pq Event F1H , Umask 01H L2 cache lines in I state filling L2. .It Li L2_LINES_IN.S .Pq Event F1H , Umask 02H L2 cache lines in S state filling L2. .It Li L2_LINES_IN.E .Pq Event F1H , Umask 04H L2 cache lines in E state filling L2. .It Li L2_LINES-IN.ALL .Pq Event F1H , Umask 07H L2 cache lines filling L2. .It Li L2_LINES_OUT.DEMAND_CLEAN .Pq Event F2H , Umask 01H Clean L2 cache lines evicted by demand. .It Li L2_LINES_OUT.DEMAND_DIRTY .Pq Event F2H , Umask 02H Dirty L2 cache lines evicted by demand. .It Li L2_LINES_OUT.PF_CLEAN .Pq Event F2H , Umask 04H Clean L2 cache lines evicted by L2 prefetch. .It Li L2_LINES_OUT.PF_DIRTY .Pq Event F2H , Umask 08H Dirty L2 cache lines evicted by L2 prefetch. .It Li L2_LINES_OUT.DIRTY_ALL .Pq Event F2H , Umask 0AH Dirty L2 cache lines filling the L2. .It Li SQ_MISC.SPLIT_LOCK .Pq Event F4H , Umask 10H Split locks in SQ. .El .Sh SEE ALSO .Xr pmc 3 , .Xr pmc.atom 3 , .Xr pmc.core 3 , .Xr pmc.iaf 3 , .Xr pmc.ucf 3 , .Xr pmc.k7 3 , .Xr pmc.k8 3 , .Xr pmc.p4 3 , .Xr pmc.p5 3 , .Xr pmc.p6 3 , .Xr pmc.corei7 3 , .Xr pmc.corei7uc 3 , .Xr pmc.ivybridge 3 , .Xr pmc.ivybridgexeon 3 , .Xr pmc.sandybridge 3 , .Xr pmc.sandybridgeuc 3 , .Xr pmc.westmere 3 , .Xr pmc.westmereuc 3 , .Xr pmc.soft 3 , .Xr pmc.tsc 3 , .Xr pmc_cpuinfo 3 , .Xr pmclog 3 , .Xr hwpmc 4 .Sh HISTORY The .Nm pmc library first appeared in .Fx 6.0 . .Sh AUTHORS The .Lb libpmc library was written by .An "Joseph Koshy" .Aq jkoshy@FreeBSD.org . The support for the Sandy Bridge Xeon microarchitecture was written by .An "Hiren Panchasara" .Aq hiren.panchasara@gmail.com . Index: stable/10/sys/dev/hwpmc/hwpmc_core.c =================================================================== --- stable/10/sys/dev/hwpmc/hwpmc_core.c (revision 320105) +++ stable/10/sys/dev/hwpmc/hwpmc_core.c (revision 320106) @@ -1,2818 +1,2829 @@ /*- * Copyright (c) 2008 Joseph Koshy * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. */ /* * Intel Core PMCs. */ #include __FBSDID("$FreeBSD$"); #include #include #include #include #include #include #if (__FreeBSD_version >= 1100000) #include #else #include #endif #include #include #include #include #define CORE_CPUID_REQUEST 0xA #define CORE_CPUID_REQUEST_SIZE 0x4 #define CORE_CPUID_EAX 0x0 #define CORE_CPUID_EBX 0x1 #define CORE_CPUID_ECX 0x2 #define CORE_CPUID_EDX 0x3 #define IAF_PMC_CAPS \ (PMC_CAP_READ | PMC_CAP_WRITE | PMC_CAP_INTERRUPT | \ PMC_CAP_USER | PMC_CAP_SYSTEM) #define IAF_RI_TO_MSR(RI) ((RI) + (1 << 30)) #define IAP_PMC_CAPS (PMC_CAP_INTERRUPT | PMC_CAP_USER | PMC_CAP_SYSTEM | \ PMC_CAP_EDGE | PMC_CAP_THRESHOLD | PMC_CAP_READ | PMC_CAP_WRITE | \ PMC_CAP_INVERT | PMC_CAP_QUALIFIER | PMC_CAP_PRECISE) #define EV_IS_NOTARCH 0 #define EV_IS_ARCH_SUPP 1 #define EV_IS_ARCH_NOTSUPP -1 /* * "Architectural" events defined by Intel. The values of these * symbols correspond to positions in the bitmask returned by * the CPUID.0AH instruction. */ enum core_arch_events { CORE_AE_BRANCH_INSTRUCTION_RETIRED = 5, CORE_AE_BRANCH_MISSES_RETIRED = 6, CORE_AE_INSTRUCTION_RETIRED = 1, CORE_AE_LLC_MISSES = 4, CORE_AE_LLC_REFERENCE = 3, CORE_AE_UNHALTED_REFERENCE_CYCLES = 2, CORE_AE_UNHALTED_CORE_CYCLES = 0 }; static enum pmc_cputype core_cputype; struct core_cpu { volatile uint32_t pc_resync; volatile uint32_t pc_iafctrl; /* Fixed function control. */ volatile uint64_t pc_globalctrl; /* Global control register. */ struct pmc_hw pc_corepmcs[]; }; static struct core_cpu **core_pcpu; static uint32_t core_architectural_events; static uint64_t core_pmcmask; static int core_iaf_ri; /* relative index of fixed counters */ static int core_iaf_width; static int core_iaf_npmc; static int core_iap_width; static int core_iap_npmc; static int core_pcpu_noop(struct pmc_mdep *md, int cpu) { (void) md; (void) cpu; return (0); } static int core_pcpu_init(struct pmc_mdep *md, int cpu) { struct pmc_cpu *pc; struct core_cpu *cc; struct pmc_hw *phw; int core_ri, n, npmc; KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), ("[iaf,%d] insane cpu number %d", __LINE__, cpu)); PMCDBG1(MDP,INI,1,"core-init cpu=%d", cpu); core_ri = md->pmd_classdep[PMC_MDEP_CLASS_INDEX_IAP].pcd_ri; npmc = md->pmd_classdep[PMC_MDEP_CLASS_INDEX_IAP].pcd_num; if (core_cputype != PMC_CPU_INTEL_CORE) npmc += md->pmd_classdep[PMC_MDEP_CLASS_INDEX_IAF].pcd_num; cc = malloc(sizeof(struct core_cpu) + npmc * sizeof(struct pmc_hw), M_PMC, M_WAITOK | M_ZERO); core_pcpu[cpu] = cc; pc = pmc_pcpu[cpu]; KASSERT(pc != NULL && cc != NULL, ("[core,%d] NULL per-cpu structures cpu=%d", __LINE__, cpu)); for (n = 0, phw = cc->pc_corepmcs; n < npmc; n++, phw++) { phw->phw_state = PMC_PHW_FLAG_IS_ENABLED | PMC_PHW_CPU_TO_STATE(cpu) | PMC_PHW_INDEX_TO_STATE(n + core_ri); phw->phw_pmc = NULL; pc->pc_hwpmcs[n + core_ri] = phw; } return (0); } static int core_pcpu_fini(struct pmc_mdep *md, int cpu) { int core_ri, n, npmc; struct pmc_cpu *pc; struct core_cpu *cc; uint64_t msr = 0; KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), ("[core,%d] insane cpu number (%d)", __LINE__, cpu)); PMCDBG1(MDP,INI,1,"core-pcpu-fini cpu=%d", cpu); if ((cc = core_pcpu[cpu]) == NULL) return (0); core_pcpu[cpu] = NULL; pc = pmc_pcpu[cpu]; KASSERT(pc != NULL, ("[core,%d] NULL per-cpu %d state", __LINE__, cpu)); npmc = md->pmd_classdep[PMC_MDEP_CLASS_INDEX_IAP].pcd_num; core_ri = md->pmd_classdep[PMC_MDEP_CLASS_INDEX_IAP].pcd_ri; for (n = 0; n < npmc; n++) { msr = rdmsr(IAP_EVSEL0 + n) & ~IAP_EVSEL_MASK; wrmsr(IAP_EVSEL0 + n, msr); } if (core_cputype != PMC_CPU_INTEL_CORE) { msr = rdmsr(IAF_CTRL) & ~IAF_CTRL_MASK; wrmsr(IAF_CTRL, msr); npmc += md->pmd_classdep[PMC_MDEP_CLASS_INDEX_IAF].pcd_num; } for (n = 0; n < npmc; n++) pc->pc_hwpmcs[n + core_ri] = NULL; free(cc, M_PMC); return (0); } /* * Fixed function counters. */ static pmc_value_t iaf_perfctr_value_to_reload_count(pmc_value_t v) { /* If the PMC has overflowed, return a reload count of zero. */ if ((v & (1ULL << (core_iaf_width - 1))) == 0) return (0); v &= (1ULL << core_iaf_width) - 1; return (1ULL << core_iaf_width) - v; } static pmc_value_t iaf_reload_count_to_perfctr_value(pmc_value_t rlc) { return (1ULL << core_iaf_width) - rlc; } static int iaf_allocate_pmc(int cpu, int ri, struct pmc *pm, const struct pmc_op_pmcallocate *a) { enum pmc_event ev; uint32_t caps, flags, validflags; KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), ("[core,%d] illegal CPU %d", __LINE__, cpu)); PMCDBG2(MDP,ALL,1, "iaf-allocate ri=%d reqcaps=0x%x", ri, pm->pm_caps); if (ri < 0 || ri > core_iaf_npmc) return (EINVAL); caps = a->pm_caps; if (a->pm_class != PMC_CLASS_IAF || (caps & IAF_PMC_CAPS) != caps) return (EINVAL); ev = pm->pm_event; if (ev < PMC_EV_IAF_FIRST || ev > PMC_EV_IAF_LAST) return (EINVAL); if (ev == PMC_EV_IAF_INSTR_RETIRED_ANY && ri != 0) return (EINVAL); if (ev == PMC_EV_IAF_CPU_CLK_UNHALTED_CORE && ri != 1) return (EINVAL); if (ev == PMC_EV_IAF_CPU_CLK_UNHALTED_REF && ri != 2) return (EINVAL); flags = a->pm_md.pm_iaf.pm_iaf_flags; validflags = IAF_MASK; if (core_cputype != PMC_CPU_INTEL_ATOM && core_cputype != PMC_CPU_INTEL_ATOM_SILVERMONT) validflags &= ~IAF_ANY; if ((flags & ~validflags) != 0) return (EINVAL); if (caps & PMC_CAP_INTERRUPT) flags |= IAF_PMI; if (caps & PMC_CAP_SYSTEM) flags |= IAF_OS; if (caps & PMC_CAP_USER) flags |= IAF_USR; if ((caps & (PMC_CAP_USER | PMC_CAP_SYSTEM)) == 0) flags |= (IAF_OS | IAF_USR); pm->pm_md.pm_iaf.pm_iaf_ctrl = (flags << (ri * 4)); PMCDBG1(MDP,ALL,2, "iaf-allocate config=0x%jx", (uintmax_t) pm->pm_md.pm_iaf.pm_iaf_ctrl); return (0); } static int iaf_config_pmc(int cpu, int ri, struct pmc *pm) { KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), ("[core,%d] illegal CPU %d", __LINE__, cpu)); KASSERT(ri >= 0 && ri < core_iaf_npmc, ("[core,%d] illegal row-index %d", __LINE__, ri)); PMCDBG3(MDP,CFG,1, "iaf-config cpu=%d ri=%d pm=%p", cpu, ri, pm); KASSERT(core_pcpu[cpu] != NULL, ("[core,%d] null per-cpu %d", __LINE__, cpu)); core_pcpu[cpu]->pc_corepmcs[ri + core_iaf_ri].phw_pmc = pm; return (0); } static int iaf_describe(int cpu, int ri, struct pmc_info *pi, struct pmc **ppmc) { int error; struct pmc_hw *phw; char iaf_name[PMC_NAME_MAX]; phw = &core_pcpu[cpu]->pc_corepmcs[ri + core_iaf_ri]; (void) snprintf(iaf_name, sizeof(iaf_name), "IAF-%d", ri); if ((error = copystr(iaf_name, pi->pm_name, PMC_NAME_MAX, NULL)) != 0) return (error); pi->pm_class = PMC_CLASS_IAF; if (phw->phw_state & PMC_PHW_FLAG_IS_ENABLED) { pi->pm_enabled = TRUE; *ppmc = phw->phw_pmc; } else { pi->pm_enabled = FALSE; *ppmc = NULL; } return (0); } static int iaf_get_config(int cpu, int ri, struct pmc **ppm) { *ppm = core_pcpu[cpu]->pc_corepmcs[ri + core_iaf_ri].phw_pmc; return (0); } static int iaf_get_msr(int ri, uint32_t *msr) { KASSERT(ri >= 0 && ri < core_iaf_npmc, ("[iaf,%d] ri %d out of range", __LINE__, ri)); *msr = IAF_RI_TO_MSR(ri); return (0); } static int iaf_read_pmc(int cpu, int ri, pmc_value_t *v) { struct pmc *pm; pmc_value_t tmp; KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), ("[core,%d] illegal cpu value %d", __LINE__, cpu)); KASSERT(ri >= 0 && ri < core_iaf_npmc, ("[core,%d] illegal row-index %d", __LINE__, ri)); pm = core_pcpu[cpu]->pc_corepmcs[ri + core_iaf_ri].phw_pmc; KASSERT(pm, ("[core,%d] cpu %d ri %d(%d) pmc not configured", __LINE__, cpu, ri, ri + core_iaf_ri)); tmp = rdpmc(IAF_RI_TO_MSR(ri)); if (PMC_IS_SAMPLING_MODE(PMC_TO_MODE(pm))) *v = iaf_perfctr_value_to_reload_count(tmp); else *v = tmp & ((1ULL << core_iaf_width) - 1); PMCDBG4(MDP,REA,1, "iaf-read cpu=%d ri=%d msr=0x%x -> v=%jx", cpu, ri, IAF_RI_TO_MSR(ri), *v); return (0); } static int iaf_release_pmc(int cpu, int ri, struct pmc *pmc) { PMCDBG3(MDP,REL,1, "iaf-release cpu=%d ri=%d pm=%p", cpu, ri, pmc); KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), ("[core,%d] illegal CPU value %d", __LINE__, cpu)); KASSERT(ri >= 0 && ri < core_iaf_npmc, ("[core,%d] illegal row-index %d", __LINE__, ri)); KASSERT(core_pcpu[cpu]->pc_corepmcs[ri + core_iaf_ri].phw_pmc == NULL, ("[core,%d] PHW pmc non-NULL", __LINE__)); return (0); } static int iaf_start_pmc(int cpu, int ri) { struct pmc *pm; struct core_cpu *iafc; uint64_t msr = 0; KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), ("[core,%d] illegal CPU value %d", __LINE__, cpu)); KASSERT(ri >= 0 && ri < core_iaf_npmc, ("[core,%d] illegal row-index %d", __LINE__, ri)); PMCDBG2(MDP,STA,1,"iaf-start cpu=%d ri=%d", cpu, ri); iafc = core_pcpu[cpu]; pm = iafc->pc_corepmcs[ri + core_iaf_ri].phw_pmc; iafc->pc_iafctrl |= pm->pm_md.pm_iaf.pm_iaf_ctrl; msr = rdmsr(IAF_CTRL) & ~IAF_CTRL_MASK; wrmsr(IAF_CTRL, msr | (iafc->pc_iafctrl & IAF_CTRL_MASK)); do { iafc->pc_resync = 0; iafc->pc_globalctrl |= (1ULL << (ri + IAF_OFFSET)); msr = rdmsr(IA_GLOBAL_CTRL) & ~IAF_GLOBAL_CTRL_MASK; wrmsr(IA_GLOBAL_CTRL, msr | (iafc->pc_globalctrl & IAF_GLOBAL_CTRL_MASK)); } while (iafc->pc_resync != 0); PMCDBG4(MDP,STA,1,"iafctrl=%x(%x) globalctrl=%jx(%jx)", iafc->pc_iafctrl, (uint32_t) rdmsr(IAF_CTRL), iafc->pc_globalctrl, rdmsr(IA_GLOBAL_CTRL)); return (0); } static int iaf_stop_pmc(int cpu, int ri) { uint32_t fc; struct core_cpu *iafc; uint64_t msr = 0; PMCDBG2(MDP,STO,1,"iaf-stop cpu=%d ri=%d", cpu, ri); iafc = core_pcpu[cpu]; KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), ("[core,%d] illegal CPU value %d", __LINE__, cpu)); KASSERT(ri >= 0 && ri < core_iaf_npmc, ("[core,%d] illegal row-index %d", __LINE__, ri)); fc = (IAF_MASK << (ri * 4)); if (core_cputype != PMC_CPU_INTEL_ATOM && core_cputype != PMC_CPU_INTEL_ATOM_SILVERMONT) fc &= ~IAF_ANY; iafc->pc_iafctrl &= ~fc; PMCDBG1(MDP,STO,1,"iaf-stop iafctrl=%x", iafc->pc_iafctrl); msr = rdmsr(IAF_CTRL) & ~IAF_CTRL_MASK; wrmsr(IAF_CTRL, msr | (iafc->pc_iafctrl & IAF_CTRL_MASK)); do { iafc->pc_resync = 0; iafc->pc_globalctrl &= ~(1ULL << (ri + IAF_OFFSET)); msr = rdmsr(IA_GLOBAL_CTRL) & ~IAF_GLOBAL_CTRL_MASK; wrmsr(IA_GLOBAL_CTRL, msr | (iafc->pc_globalctrl & IAF_GLOBAL_CTRL_MASK)); } while (iafc->pc_resync != 0); PMCDBG4(MDP,STO,1,"iafctrl=%x(%x) globalctrl=%jx(%jx)", iafc->pc_iafctrl, (uint32_t) rdmsr(IAF_CTRL), iafc->pc_globalctrl, rdmsr(IA_GLOBAL_CTRL)); return (0); } static int iaf_write_pmc(int cpu, int ri, pmc_value_t v) { struct core_cpu *cc; struct pmc *pm; uint64_t msr; KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), ("[core,%d] illegal cpu value %d", __LINE__, cpu)); KASSERT(ri >= 0 && ri < core_iaf_npmc, ("[core,%d] illegal row-index %d", __LINE__, ri)); cc = core_pcpu[cpu]; pm = cc->pc_corepmcs[ri + core_iaf_ri].phw_pmc; KASSERT(pm, ("[core,%d] cpu %d ri %d pmc not configured", __LINE__, cpu, ri)); if (PMC_IS_SAMPLING_MODE(PMC_TO_MODE(pm))) v = iaf_reload_count_to_perfctr_value(v); /* Turn off fixed counters */ msr = rdmsr(IAF_CTRL) & ~IAF_CTRL_MASK; wrmsr(IAF_CTRL, msr); wrmsr(IAF_CTR0 + ri, v & ((1ULL << core_iaf_width) - 1)); /* Turn on fixed counters */ msr = rdmsr(IAF_CTRL) & ~IAF_CTRL_MASK; wrmsr(IAF_CTRL, msr | (cc->pc_iafctrl & IAF_CTRL_MASK)); PMCDBG6(MDP,WRI,1, "iaf-write cpu=%d ri=%d msr=0x%x v=%jx iafctrl=%jx " "pmc=%jx", cpu, ri, IAF_RI_TO_MSR(ri), v, (uintmax_t) rdmsr(IAF_CTRL), (uintmax_t) rdpmc(IAF_RI_TO_MSR(ri))); return (0); } static void iaf_initialize(struct pmc_mdep *md, int maxcpu, int npmc, int pmcwidth) { struct pmc_classdep *pcd; KASSERT(md != NULL, ("[iaf,%d] md is NULL", __LINE__)); PMCDBG0(MDP,INI,1, "iaf-initialize"); pcd = &md->pmd_classdep[PMC_MDEP_CLASS_INDEX_IAF]; pcd->pcd_caps = IAF_PMC_CAPS; pcd->pcd_class = PMC_CLASS_IAF; pcd->pcd_num = npmc; pcd->pcd_ri = md->pmd_npmc; pcd->pcd_width = pmcwidth; pcd->pcd_allocate_pmc = iaf_allocate_pmc; pcd->pcd_config_pmc = iaf_config_pmc; pcd->pcd_describe = iaf_describe; pcd->pcd_get_config = iaf_get_config; pcd->pcd_get_msr = iaf_get_msr; pcd->pcd_pcpu_fini = core_pcpu_noop; pcd->pcd_pcpu_init = core_pcpu_noop; pcd->pcd_read_pmc = iaf_read_pmc; pcd->pcd_release_pmc = iaf_release_pmc; pcd->pcd_start_pmc = iaf_start_pmc; pcd->pcd_stop_pmc = iaf_stop_pmc; pcd->pcd_write_pmc = iaf_write_pmc; md->pmd_npmc += npmc; } /* * Intel programmable PMCs. */ /* * Event descriptor tables. * * For each event id, we track: * * 1. The CPUs that the event is valid for. * * 2. If the event uses a fixed UMASK, the value of the umask field. * If the event doesn't use a fixed UMASK, a mask of legal bits * to check against. */ struct iap_event_descr { enum pmc_event iap_ev; unsigned char iap_evcode; unsigned char iap_umask; unsigned int iap_flags; }; #define IAP_F_CC (1 << 0) /* CPU: Core */ #define IAP_F_CC2 (1 << 1) /* CPU: Core2 family */ #define IAP_F_CC2E (1 << 2) /* CPU: Core2 Extreme only */ #define IAP_F_CA (1 << 3) /* CPU: Atom */ #define IAP_F_I7 (1 << 4) /* CPU: Core i7 */ #define IAP_F_I7O (1 << 4) /* CPU: Core i7 (old) */ #define IAP_F_WM (1 << 5) /* CPU: Westmere */ #define IAP_F_SB (1 << 6) /* CPU: Sandy Bridge */ #define IAP_F_IB (1 << 7) /* CPU: Ivy Bridge */ #define IAP_F_SBX (1 << 8) /* CPU: Sandy Bridge Xeon */ #define IAP_F_IBX (1 << 9) /* CPU: Ivy Bridge Xeon */ #define IAP_F_HW (1 << 10) /* CPU: Haswell */ #define IAP_F_CAS (1 << 11) /* CPU: Atom Silvermont */ #define IAP_F_HWX (1 << 12) /* CPU: Haswell Xeon */ #define IAP_F_BW (1 << 13) /* CPU: Broadwell */ #define IAP_F_FM (1 << 14) /* Fixed mask */ #define IAP_F_ALLCPUSCORE2 \ (IAP_F_CC | IAP_F_CC2 | IAP_F_CC2E | IAP_F_CA) /* Sub fields of UMASK that this event supports. */ #define IAP_M_CORE (1 << 0) /* Core specificity */ #define IAP_M_AGENT (1 << 1) /* Agent specificity */ #define IAP_M_PREFETCH (1 << 2) /* Prefetch */ #define IAP_M_MESI (1 << 3) /* MESI */ #define IAP_M_SNOOPRESPONSE (1 << 4) /* Snoop response */ #define IAP_M_SNOOPTYPE (1 << 5) /* Snoop type */ #define IAP_M_TRANSITION (1 << 6) /* Transition */ #define IAP_F_CORE (0x3 << 14) /* Core specificity */ #define IAP_F_AGENT (0x1 << 13) /* Agent specificity */ #define IAP_F_PREFETCH (0x3 << 12) /* Prefetch */ #define IAP_F_MESI (0xF << 8) /* MESI */ #define IAP_F_SNOOPRESPONSE (0xB << 8) /* Snoop response */ #define IAP_F_SNOOPTYPE (0x3 << 8) /* Snoop type */ #define IAP_F_TRANSITION (0x1 << 12) /* Transition */ #define IAP_PREFETCH_RESERVED (0x2 << 12) #define IAP_CORE_THIS (0x1 << 14) #define IAP_CORE_ALL (0x3 << 14) #define IAP_F_CMASK 0xFF000000 static struct iap_event_descr iap_events[] = { #undef IAPDESCR #define IAPDESCR(N,EV,UM,FLAGS) { \ .iap_ev = PMC_EV_IAP_EVENT_##N, \ .iap_evcode = (EV), \ .iap_umask = (UM), \ .iap_flags = (FLAGS) \ } IAPDESCR(02H_01H, 0x02, 0x01, IAP_F_FM | IAP_F_I7O), IAPDESCR(02H_81H, 0x02, 0x81, IAP_F_FM | IAP_F_CA), IAPDESCR(03H_00H, 0x03, 0x00, IAP_F_FM | IAP_F_CC), IAPDESCR(03H_01H, 0x03, 0x01, IAP_F_FM | IAP_F_I7O | IAP_F_SB | IAP_F_SBX | IAP_F_CAS), IAPDESCR(03H_02H, 0x03, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | IAP_F_WM | IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_CAS | IAP_F_HWX), IAPDESCR(03H_04H, 0x03, 0x04, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | IAP_F_I7O | IAP_F_CAS), IAPDESCR(03H_08H, 0x03, 0x08, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | IAP_F_SB | IAP_F_SBX | IAP_F_CAS | IAP_F_IB | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), IAPDESCR(03H_10H, 0x03, 0x10, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | IAP_F_SB | IAP_F_SBX | IAP_F_CAS), IAPDESCR(03H_20H, 0x03, 0x20, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | IAP_F_CAS), IAPDESCR(03H_40H, 0x03, 0x40, IAP_F_CAS), IAPDESCR(03H_80H, 0x03, 0x80, IAP_F_CAS), IAPDESCR(04H_00H, 0x04, 0x00, IAP_F_FM | IAP_F_CC | IAP_F_CAS), IAPDESCR(04H_01H, 0x04, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | IAP_F_I7O | IAP_F_CAS), IAPDESCR(04H_02H, 0x04, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | IAP_F_CAS), IAPDESCR(04H_04H, 0x04, 0x04, IAP_F_CAS), IAPDESCR(04H_07H, 0x04, 0x07, IAP_F_FM | IAP_F_I7 | IAP_F_WM), IAPDESCR(04H_08H, 0x04, 0x08, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | IAP_F_CAS), IAPDESCR(04H_10H, 0x04, 0x10, IAP_F_CAS), IAPDESCR(04H_20H, 0x04, 0x20, IAP_F_CAS), IAPDESCR(04H_40H, 0x04, 0x40, IAP_F_CAS), IAPDESCR(04H_80H, 0x04, 0x80, IAP_F_CAS), IAPDESCR(05H_00H, 0x05, 0x00, IAP_F_FM | IAP_F_CC), IAPDESCR(05H_01H, 0x05, 0x01, IAP_F_FM | IAP_F_I7O | IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_CAS | IAP_F_HWX), IAPDESCR(05H_02H, 0x05, 0x02, IAP_F_FM | IAP_F_I7O | IAP_F_WM | IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_CAS | IAP_F_HWX), IAPDESCR(05H_03H, 0x05, 0x03, IAP_F_FM | IAP_F_I7O | IAP_F_CAS), IAPDESCR(06H_00H, 0x06, 0x00, IAP_F_FM | IAP_F_CC | IAP_F_CC2 | IAP_F_CC2E | IAP_F_CA), IAPDESCR(06H_01H, 0x06, 0x01, IAP_F_FM | IAP_F_I7O), IAPDESCR(06H_02H, 0x06, 0x02, IAP_F_FM | IAP_F_I7O), IAPDESCR(06H_04H, 0x06, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM), IAPDESCR(06H_08H, 0x06, 0x08, IAP_F_FM | IAP_F_I7 | IAP_F_WM), IAPDESCR(06H_0FH, 0x06, 0x0F, IAP_F_FM | IAP_F_I7O), IAPDESCR(07H_00H, 0x07, 0x00, IAP_F_FM | IAP_F_CC | IAP_F_CC2), IAPDESCR(07H_01H, 0x07, 0x01, IAP_F_FM | IAP_F_ALLCPUSCORE2 | IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), IAPDESCR(07H_02H, 0x07, 0x02, IAP_F_FM | IAP_F_ALLCPUSCORE2), IAPDESCR(07H_03H, 0x07, 0x03, IAP_F_FM | IAP_F_ALLCPUSCORE2), IAPDESCR(07H_06H, 0x07, 0x06, IAP_F_FM | IAP_F_CA), IAPDESCR(07H_08H, 0x07, 0x08, IAP_F_FM | IAP_F_CA | IAP_F_SB | IAP_F_SBX), IAPDESCR(08H_01H, 0x08, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_SBX | IAP_F_HW | IAP_F_HWX), IAPDESCR(08H_02H, 0x08, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_SBX | IAP_F_HW | IAP_F_HWX), IAPDESCR(08H_04H, 0x08, 0x04, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | IAP_F_WM | IAP_F_SB | IAP_F_SBX | IAP_F_HW | IAP_F_HWX), IAPDESCR(08H_05H, 0x08, 0x05, IAP_F_FM | IAP_F_CA), IAPDESCR(08H_06H, 0x08, 0x06, IAP_F_FM | IAP_F_CA), IAPDESCR(08H_07H, 0x08, 0x07, IAP_F_FM | IAP_F_CA), IAPDESCR(08H_08H, 0x08, 0x08, IAP_F_FM | IAP_F_CA | IAP_F_CC2), IAPDESCR(08H_09H, 0x08, 0x09, IAP_F_FM | IAP_F_CA), IAPDESCR(08H_0EH, 0x08, 0x0E, IAP_F_FM | IAP_F_HW | IAP_F_HWX), IAPDESCR(08H_10H, 0x08, 0x10, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_SBX | IAP_F_HW | IAP_F_HWX), IAPDESCR(08H_20H, 0x08, 0x20, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_HW | IAP_F_HWX), IAPDESCR(08H_40H, 0x08, 0x40, IAP_F_FM | IAP_F_I7O | IAP_F_HW | IAP_F_HWX), IAPDESCR(08H_60H, 0x08, 0x60, IAP_F_FM | IAP_F_HW | IAP_F_HWX), IAPDESCR(08H_80H, 0x08, 0x80, IAP_F_FM | IAP_F_I7 | IAP_F_HW | IAP_F_HWX), IAPDESCR(08H_81H, 0x08, 0x81, IAP_F_FM | IAP_F_IB | IAP_F_IBX), IAPDESCR(08H_82H, 0x08, 0x82, IAP_F_FM | IAP_F_IB | IAP_F_IBX), IAPDESCR(08H_84H, 0x08, 0x84, IAP_F_FM | IAP_F_IB | IAP_F_IBX), IAPDESCR(08H_88H, 0x08, 0x88, IAP_F_IB | IAP_F_IBX), IAPDESCR(09H_01H, 0x09, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | IAP_F_I7O), IAPDESCR(09H_02H, 0x09, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | IAP_F_I7O), IAPDESCR(09H_04H, 0x09, 0x04, IAP_F_FM | IAP_F_I7O), IAPDESCR(09H_08H, 0x09, 0x08, IAP_F_FM | IAP_F_I7O), IAPDESCR(0BH_01H, 0x0B, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM), IAPDESCR(0BH_02H, 0x0B, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM), IAPDESCR(0BH_10H, 0x0B, 0x10, IAP_F_FM | IAP_F_I7 | IAP_F_WM), IAPDESCR(0CH_01H, 0x0C, 0x01, IAP_F_FM | IAP_F_CC2 | IAP_F_I7 | IAP_F_WM), IAPDESCR(0CH_02H, 0x0C, 0x02, IAP_F_FM | IAP_F_CC2), IAPDESCR(0CH_03H, 0x0C, 0x03, IAP_F_FM | IAP_F_CA), IAPDESCR(0DH_03H, 0x0D, 0x03, IAP_F_FM | IAP_F_SB | IAP_F_SBX | IAP_F_HW | IAP_F_IB | IAP_F_IBX | IAP_F_HWX), IAPDESCR(0DH_40H, 0x0D, 0x40, IAP_F_FM | IAP_F_SB | IAP_F_SBX), IAPDESCR(0EH_01H, 0x0E, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), IAPDESCR(0EH_02H, 0x0E, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM), IAPDESCR(0EH_10H, 0x0E, 0x10, IAP_F_FM | IAP_F_IB | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), IAPDESCR(0EH_20H, 0x0E, 0x20, IAP_F_FM | IAP_F_IB | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), IAPDESCR(0EH_40H, 0x0E, 0x40, IAP_F_FM | IAP_F_IB | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), IAPDESCR(0FH_01H, 0x0F, 0x01, IAP_F_FM | IAP_F_I7), IAPDESCR(0FH_02H, 0x0F, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM), IAPDESCR(0FH_08H, 0x0F, 0x08, IAP_F_FM | IAP_F_I7 | IAP_F_WM), IAPDESCR(0FH_10H, 0x0F, 0x10, IAP_F_FM | IAP_F_I7 | IAP_F_WM), IAPDESCR(0FH_20H, 0x0F, 0x20, IAP_F_FM | IAP_F_I7 | IAP_F_WM), IAPDESCR(0FH_80H, 0x0F, 0x80, IAP_F_FM | IAP_F_I7 | IAP_F_WM), IAPDESCR(10H_00H, 0x10, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), IAPDESCR(10H_01H, 0x10, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_SBX | IAP_F_IB | IAP_F_IBX ), IAPDESCR(10H_02H, 0x10, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM), IAPDESCR(10H_04H, 0x10, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM), IAPDESCR(10H_08H, 0x10, 0x08, IAP_F_FM | IAP_F_I7 | IAP_F_WM), IAPDESCR(10H_10H, 0x10, 0x10, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_SBX | IAP_F_IB | IAP_F_IBX), IAPDESCR(10H_20H, 0x10, 0x20, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_SBX | IAP_F_IB | IAP_F_IBX), IAPDESCR(10H_40H, 0x10, 0x40, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_SBX | IAP_F_IB | IAP_F_IBX), IAPDESCR(10H_80H, 0x10, 0x80, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_SBX | IAP_F_IB | IAP_F_IBX), IAPDESCR(10H_81H, 0x10, 0x81, IAP_F_FM | IAP_F_CA), IAPDESCR(11H_00H, 0x11, 0x00, IAP_F_FM | IAP_F_CC | IAP_F_CC2), IAPDESCR(11H_01H, 0x11, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_SB | IAP_F_SBX | IAP_F_IB | IAP_F_IBX), IAPDESCR(11H_02H, 0x11, 0x02, IAP_F_FM | IAP_F_SB | IAP_F_SBX | IAP_F_IB | IAP_F_IBX), IAPDESCR(11H_81H, 0x11, 0x81, IAP_F_FM | IAP_F_CA), IAPDESCR(12H_00H, 0x12, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), IAPDESCR(12H_01H, 0x12, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_I7 | IAP_F_WM), IAPDESCR(12H_02H, 0x12, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM), IAPDESCR(12H_04H, 0x12, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM), IAPDESCR(12H_08H, 0x12, 0x08, IAP_F_FM | IAP_F_I7 | IAP_F_WM), IAPDESCR(12H_10H, 0x12, 0x10, IAP_F_FM | IAP_F_I7 | IAP_F_WM), IAPDESCR(12H_20H, 0x12, 0x20, IAP_F_FM | IAP_F_I7 | IAP_F_WM), IAPDESCR(12H_40H, 0x12, 0x40, IAP_F_FM | IAP_F_I7 | IAP_F_WM), IAPDESCR(12H_81H, 0x12, 0x81, IAP_F_FM | IAP_F_CA), IAPDESCR(13H_00H, 0x13, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), IAPDESCR(13H_01H, 0x13, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_I7 | IAP_F_WM), IAPDESCR(13H_02H, 0x13, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM), IAPDESCR(13H_04H, 0x13, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM), IAPDESCR(13H_07H, 0x13, 0x07, IAP_F_FM | IAP_F_I7 | IAP_F_WM), IAPDESCR(13H_81H, 0x13, 0x81, IAP_F_FM | IAP_F_CA), IAPDESCR(14H_00H, 0x14, 0x00, IAP_F_FM | IAP_F_CC | IAP_F_CC2), IAPDESCR(14H_01H, 0x14, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX), IAPDESCR(14H_02H, 0x14, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM), IAPDESCR(17H_01H, 0x17, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_SBX), IAPDESCR(18H_00H, 0x18, 0x00, IAP_F_FM | IAP_F_CA | IAP_F_CC2), IAPDESCR(18H_01H, 0x18, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM), IAPDESCR(19H_00H, 0x19, 0x00, IAP_F_FM | IAP_F_CA | IAP_F_CC2), IAPDESCR(19H_01H, 0x19, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | IAP_F_I7 | IAP_F_WM), IAPDESCR(19H_02H, 0x19, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2), IAPDESCR(1DH_01H, 0x1D, 0x01, IAP_F_FM | IAP_F_I7O), IAPDESCR(1DH_02H, 0x1D, 0x02, IAP_F_FM | IAP_F_I7O), IAPDESCR(1DH_04H, 0x1D, 0x04, IAP_F_FM | IAP_F_I7O), IAPDESCR(1EH_01H, 0x1E, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM), IAPDESCR(20H_01H, 0x20, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM), IAPDESCR(21H, 0x21, IAP_M_CORE, IAP_F_ALLCPUSCORE2), IAPDESCR(22H, 0x22, IAP_M_CORE, IAP_F_CC2), IAPDESCR(23H, 0x23, IAP_M_CORE, IAP_F_ALLCPUSCORE2), IAPDESCR(24H, 0x24, IAP_M_CORE | IAP_M_PREFETCH, IAP_F_ALLCPUSCORE2), IAPDESCR(24H_01H, 0x24, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX), IAPDESCR(24H_02H, 0x24, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM), IAPDESCR(24H_03H, 0x24, 0x03, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX), IAPDESCR(24H_04H, 0x24, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX), IAPDESCR(24H_08H, 0x24, 0x08, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX), IAPDESCR(24H_0CH, 0x24, 0x0C, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX), IAPDESCR(24H_10H, 0x24, 0x10, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX), IAPDESCR(24H_20H, 0x24, 0x20, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX), IAPDESCR(24H_21H, 0x24, 0x21, IAP_F_FM | IAP_F_HW | IAP_F_HWX), IAPDESCR(24H_22H, 0x24, 0x22, IAP_F_FM | IAP_F_HW | IAP_F_HWX), IAPDESCR(24H_24H, 0x24, 0x24, IAP_F_FM | IAP_F_HW | IAP_F_HWX), IAPDESCR(24H_27H, 0x24, 0x27, IAP_F_FM | IAP_F_HW | IAP_F_HWX), IAPDESCR(24H_30H, 0x24, 0x30, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), IAPDESCR(24H_40H, 0x24, 0x40, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX), IAPDESCR(24H_41H, 0x24, 0x41, IAP_F_FM | IAP_F_HW | IAP_F_HWX), IAPDESCR(24H_42H, 0x24, 0x42, IAP_F_FM | IAP_F_HW | IAP_F_HWX), IAPDESCR(24H_44H, 0x24, 0x44, IAP_F_FM | IAP_F_HW | IAP_F_HWX), IAPDESCR(24H_50H, 0x24, 0x50, IAP_F_FM | IAP_F_HW | IAP_F_HWX), IAPDESCR(24H_80H, 0x24, 0x80, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX), IAPDESCR(24H_C0H, 0x24, 0xC0, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX), IAPDESCR(24H_E1H, 0x24, 0xE1, IAP_F_FM | IAP_F_HW | IAP_F_HWX), IAPDESCR(24H_E2H, 0x24, 0xE2, IAP_F_FM | IAP_F_HW | IAP_F_HWX), IAPDESCR(24H_E4H, 0x24, 0xE4, IAP_F_FM | IAP_F_HW | IAP_F_HWX), IAPDESCR(24H_E7H, 0x24, 0xE7, IAP_F_FM | IAP_F_HW | IAP_F_HWX), IAPDESCR(24H_AAH, 0x24, 0xAA, IAP_F_FM | IAP_F_I7 | IAP_F_WM), IAPDESCR(24H_F8H, 0x24, 0xF8, IAP_F_FM | IAP_F_HW | IAP_F_HWX), IAPDESCR(24H_3FH, 0x24, 0x3F, IAP_F_FM | IAP_F_HW | IAP_F_HWX), IAPDESCR(24H_FFH, 0x24, 0xFF, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_HW | IAP_F_HWX), IAPDESCR(25H, 0x25, IAP_M_CORE, IAP_F_ALLCPUSCORE2), IAPDESCR(26H, 0x26, IAP_M_CORE | IAP_M_PREFETCH, IAP_F_ALLCPUSCORE2), IAPDESCR(26H_01H, 0x26, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM), IAPDESCR(26H_02H, 0x26, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM), IAPDESCR(26H_04H, 0x26, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM), IAPDESCR(26H_08H, 0x26, 0x08, IAP_F_FM | IAP_F_I7 | IAP_F_WM), IAPDESCR(26H_0FH, 0x26, 0x0F, IAP_F_FM | IAP_F_I7 | IAP_F_WM), IAPDESCR(26H_10H, 0x26, 0x10, IAP_F_FM | IAP_F_I7 | IAP_F_WM), IAPDESCR(26H_20H, 0x26, 0x20, IAP_F_FM | IAP_F_I7 | IAP_F_WM), IAPDESCR(26H_40H, 0x26, 0x40, IAP_F_FM | IAP_F_I7 | IAP_F_WM), IAPDESCR(26H_80H, 0x26, 0x80, IAP_F_FM | IAP_F_I7 | IAP_F_WM), IAPDESCR(26H_F0H, 0x26, 0xF0, IAP_F_FM | IAP_F_I7 | IAP_F_WM), IAPDESCR(26H_FFH, 0x26, 0xFF, IAP_F_FM | IAP_F_I7 | IAP_F_WM), IAPDESCR(27H, 0x27, IAP_M_CORE | IAP_M_PREFETCH, IAP_F_ALLCPUSCORE2), IAPDESCR(27H_01H, 0x27, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX), IAPDESCR(27H_02H, 0x27, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM), IAPDESCR(27H_04H, 0x27, 0x04, IAP_F_FM | IAP_F_I7O | IAP_F_SB | IAP_F_SBX), IAPDESCR(27H_08H, 0x27, 0x08, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX), IAPDESCR(27H_0EH, 0x27, 0x0E, IAP_F_FM | IAP_F_I7 | IAP_F_WM), IAPDESCR(27H_0FH, 0x27, 0x0F, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX), IAPDESCR(27H_10H, 0x27, 0x10, IAP_F_FM | IAP_F_I7 | IAP_F_WM), IAPDESCR(27H_20H, 0x27, 0x20, IAP_F_FM | IAP_F_I7 | IAP_F_WM), IAPDESCR(27H_40H, 0x27, 0x40, IAP_F_FM | IAP_F_I7 | IAP_F_WM), IAPDESCR(27H_50H, 0x27, 0x50, IAP_F_FM | IAP_F_HW | IAP_F_HWX), IAPDESCR(27H_80H, 0x27, 0x80, IAP_F_FM | IAP_F_I7 | IAP_F_WM), IAPDESCR(27H_E0H, 0x27, 0xE0, IAP_F_FM | IAP_F_I7 | IAP_F_WM), IAPDESCR(27H_F0H, 0x27, 0xF0, IAP_F_FM | IAP_F_I7 | IAP_F_WM), IAPDESCR(28H, 0x28, IAP_M_CORE | IAP_M_MESI, IAP_F_ALLCPUSCORE2), IAPDESCR(28H_01H, 0x28, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_IB | IAP_F_SBX | IAP_F_IBX), IAPDESCR(28H_02H, 0x28, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SBX), IAPDESCR(28H_04H, 0x28, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX), IAPDESCR(28H_08H, 0x28, 0x08, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX), IAPDESCR(28H_0FH, 0x28, 0x0F, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_IB | IAP_F_SBX | IAP_F_IBX), IAPDESCR(29H, 0x29, IAP_M_CORE | IAP_M_MESI, IAP_F_CC), IAPDESCR(29H, 0x29, IAP_M_CORE | IAP_M_MESI | IAP_M_PREFETCH, IAP_F_CA | IAP_F_CC2), IAPDESCR(2AH, 0x2A, IAP_M_CORE | IAP_M_MESI, IAP_F_ALLCPUSCORE2), IAPDESCR(2BH, 0x2B, IAP_M_CORE | IAP_M_MESI, IAP_F_CA | IAP_F_CC2), IAPDESCR(2EH, 0x2E, IAP_M_CORE | IAP_M_MESI | IAP_M_PREFETCH, IAP_F_ALLCPUSCORE2), IAPDESCR(2EH_01H, 0x2E, 0x01, IAP_F_FM | IAP_F_WM), IAPDESCR(2EH_02H, 0x2E, 0x02, IAP_F_FM | IAP_F_WM), IAPDESCR(2EH_41H, 0x2E, 0x41, IAP_F_FM | IAP_F_ALLCPUSCORE2 | IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_CAS | IAP_F_HWX), IAPDESCR(2EH_4FH, 0x2E, 0x4F, IAP_F_FM | IAP_F_ALLCPUSCORE2 | IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_CAS | IAP_F_HWX), IAPDESCR(30H, 0x30, IAP_M_CORE | IAP_M_MESI | IAP_M_PREFETCH, IAP_F_ALLCPUSCORE2), IAPDESCR(30H_00H, 0x30, 0x00, IAP_F_CAS), IAPDESCR(31H_00H, 0x31, 0x00, IAP_F_CAS), IAPDESCR(32H, 0x32, IAP_M_CORE | IAP_M_MESI | IAP_M_PREFETCH, IAP_F_CC), IAPDESCR(32H, 0x32, IAP_M_CORE, IAP_F_CA | IAP_F_CC2), IAPDESCR(3AH, 0x3A, IAP_M_TRANSITION, IAP_F_CC), IAPDESCR(3AH_00H, 0x3A, 0x00, IAP_F_FM | IAP_F_CA | IAP_F_CC2), IAPDESCR(3BH_C0H, 0x3B, 0xC0, IAP_F_FM | IAP_F_ALLCPUSCORE2), IAPDESCR(3CH_00H, 0x3C, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2 | IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_CAS | IAP_F_HWX), IAPDESCR(3CH_01H, 0x3C, 0x01, IAP_F_FM | IAP_F_ALLCPUSCORE2 | IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_CAS | IAP_F_HWX), IAPDESCR(3CH_02H, 0x3C, 0x02, IAP_F_FM | IAP_F_ALLCPUSCORE2), IAPDESCR(3DH_01H, 0x3D, 0x01, IAP_F_FM | IAP_F_I7O), IAPDESCR(40H, 0x40, IAP_M_MESI, IAP_F_CC | IAP_F_CC2), IAPDESCR(40H_01H, 0x40, 0x01, IAP_F_FM | IAP_F_I7), IAPDESCR(40H_02H, 0x40, 0x02, IAP_F_FM | IAP_F_I7), IAPDESCR(40H_04H, 0x40, 0x04, IAP_F_FM | IAP_F_I7), IAPDESCR(40H_08H, 0x40, 0x08, IAP_F_FM | IAP_F_I7), IAPDESCR(40H_0FH, 0x40, 0x0F, IAP_F_FM | IAP_F_I7), IAPDESCR(40H_21H, 0x40, 0x21, IAP_F_FM | IAP_F_CA), IAPDESCR(41H, 0x41, IAP_M_MESI, IAP_F_CC | IAP_F_CC2), IAPDESCR(41H_01H, 0x41, 0x01, IAP_F_FM | IAP_F_I7O), IAPDESCR(41H_02H, 0x41, 0x02, IAP_F_FM | IAP_F_I7), IAPDESCR(41H_04H, 0x41, 0x04, IAP_F_FM | IAP_F_I7), IAPDESCR(41H_08H, 0x41, 0x08, IAP_F_FM | IAP_F_I7), IAPDESCR(41H_0FH, 0x41, 0x0F, IAP_F_FM | IAP_F_I7O), IAPDESCR(41H_22H, 0x41, 0x22, IAP_F_FM | IAP_F_CA), IAPDESCR(42H, 0x42, IAP_M_MESI, IAP_F_ALLCPUSCORE2), IAPDESCR(42H_01H, 0x42, 0x01, IAP_F_FM | IAP_F_I7), IAPDESCR(42H_02H, 0x42, 0x02, IAP_F_FM | IAP_F_I7), IAPDESCR(42H_04H, 0x42, 0x04, IAP_F_FM | IAP_F_I7), IAPDESCR(42H_08H, 0x42, 0x08, IAP_F_FM | IAP_F_I7), IAPDESCR(42H_10H, 0x42, 0x10, IAP_F_FM | IAP_F_CA | IAP_F_CC2), IAPDESCR(43H_01H, 0x43, 0x01, IAP_F_FM | IAP_F_ALLCPUSCORE2 | IAP_F_I7), IAPDESCR(43H_02H, 0x43, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | IAP_F_I7), IAPDESCR(44H_02H, 0x44, 0x02, IAP_F_FM | IAP_F_CC), IAPDESCR(45H_0FH, 0x45, 0x0F, IAP_F_FM | IAP_F_ALLCPUSCORE2), IAPDESCR(46H_00H, 0x46, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), IAPDESCR(47H_00H, 0x47, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), IAPDESCR(48H_00H, 0x48, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), IAPDESCR(48H_01H, 0x48, 0x01, IAP_F_FM | IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), IAPDESCR(48H_02H, 0x48, 0x02, IAP_F_FM | IAP_F_I7O), IAPDESCR(49H_00H, 0x49, 0x00, IAP_F_FM | IAP_F_CC), IAPDESCR(49H_01H, 0x49, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), IAPDESCR(49H_02H, 0x49, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), IAPDESCR(49H_04H, 0x49, 0x04, IAP_F_FM | IAP_F_WM | IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), IAPDESCR(49H_0EH, 0x49, 0x0E, IAP_F_FM | IAP_F_HW | IAP_F_HWX), IAPDESCR(49H_10H, 0x49, 0x10, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), IAPDESCR(49H_20H, 0x49, 0x20, IAP_F_FM | IAP_F_I7 | IAP_F_HW | IAP_F_HWX), IAPDESCR(49H_40H, 0x49, 0x40, IAP_F_FM | IAP_F_I7O | IAP_F_HW | IAP_F_HWX), IAPDESCR(49H_60H, 0x49, 0x60, IAP_F_FM | IAP_F_HW | IAP_F_HWX), IAPDESCR(49H_80H, 0x49, 0x80, IAP_F_FM | IAP_F_WM | IAP_F_I7 | IAP_F_HW | IAP_F_HWX), IAPDESCR(4BH_00H, 0x4B, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), IAPDESCR(4BH_01H, 0x4B, 0x01, IAP_F_FM | IAP_F_ALLCPUSCORE2 | IAP_F_I7O), IAPDESCR(4BH_02H, 0x4B, 0x02, IAP_F_FM | IAP_F_ALLCPUSCORE2), IAPDESCR(4BH_03H, 0x4B, 0x03, IAP_F_FM | IAP_F_CC), IAPDESCR(4BH_08H, 0x4B, 0x08, IAP_F_FM | IAP_F_I7O), IAPDESCR(4CH_00H, 0x4C, 0x00, IAP_F_FM | IAP_F_CA | IAP_F_CC2), IAPDESCR(4CH_01H, 0x4C, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), IAPDESCR(4CH_02H, 0x4C, 0x02, IAP_F_FM | IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), IAPDESCR(4DH_01H, 0x4D, 0x01, IAP_F_FM | IAP_F_I7O), IAPDESCR(4EH_01H, 0x4E, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM), IAPDESCR(4EH_02H, 0x4E, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_SBX), IAPDESCR(4EH_04H, 0x4E, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM), IAPDESCR(4EH_10H, 0x4E, 0x10, IAP_F_FM | IAP_F_CA | IAP_F_CC2), IAPDESCR(4FH_00H, 0x4F, 0x00, IAP_F_FM | IAP_F_CC), IAPDESCR(4FH_02H, 0x4F, 0x02, IAP_F_FM | IAP_F_I7O), IAPDESCR(4FH_04H, 0x4F, 0x04, IAP_F_FM | IAP_F_I7O), IAPDESCR(4FH_08H, 0x4F, 0x08, IAP_F_FM | IAP_F_I7O), IAPDESCR(4FH_10H, 0x4F, 0x10, IAP_F_FM | IAP_F_WM), IAPDESCR(51H_01H, 0x51, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), IAPDESCR(51H_02H, 0x51, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_SBX), IAPDESCR(51H_04H, 0x51, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_SBX), IAPDESCR(51H_08H, 0x51, 0x08, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_SBX), IAPDESCR(52H_01H, 0x52, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM), IAPDESCR(53H_01H, 0x53, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM), IAPDESCR(58H_01H, 0x58, 0x01, IAP_F_FM | IAP_F_IB | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), IAPDESCR(58H_02H, 0x58, 0x02, IAP_F_FM | IAP_F_IB | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), IAPDESCR(58H_04H, 0x58, 0x04, IAP_F_FM | IAP_F_IB | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), IAPDESCR(58H_08H, 0x58, 0x08, IAP_F_FM | IAP_F_IB | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), IAPDESCR(59H_20H, 0x59, 0x20, IAP_F_FM | IAP_F_SB | IAP_F_SBX), IAPDESCR(59H_40H, 0x59, 0x40, IAP_F_FM | IAP_F_SB | IAP_F_SBX), IAPDESCR(59H_80H, 0x59, 0x80, IAP_F_FM | IAP_F_SB | IAP_F_SBX), IAPDESCR(5BH_0CH, 0x5B, 0x0C, IAP_F_FM | IAP_F_SB | IAP_F_SBX), IAPDESCR(5BH_0FH, 0x5B, 0x0F, IAP_F_FM | IAP_F_SB | IAP_F_SBX), IAPDESCR(5BH_40H, 0x5B, 0x40, IAP_F_FM | IAP_F_SB | IAP_F_SBX), IAPDESCR(5BH_4FH, 0x5B, 0x4F, IAP_F_FM | IAP_F_SB | IAP_F_SBX), IAPDESCR(5CH_01H, 0x5C, 0x01, IAP_F_FM | IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), IAPDESCR(5CH_02H, 0x5C, 0x02, IAP_F_FM | IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), IAPDESCR(5EH_01H, 0x5E, 0x01, IAP_F_FM | IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), IAPDESCR(5FH_01H, 0x5F, 0x01, IAP_F_FM | IAP_F_IB ), /* IB not in manual */ IAPDESCR(5FH_04H, 0x5F, 0x04, IAP_F_IBX | IAP_F_IB), IAPDESCR(60H, 0x60, IAP_M_AGENT | IAP_M_CORE, IAP_F_ALLCPUSCORE2), IAPDESCR(60H_01H, 0x60, 0x01, IAP_F_FM | IAP_F_WM | IAP_F_I7O | IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), IAPDESCR(60H_02H, 0x60, 0x02, IAP_F_FM | IAP_F_WM | IAP_F_I7O | IAP_F_IB | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), IAPDESCR(60H_04H, 0x60, 0x04, IAP_F_FM | IAP_F_WM | IAP_F_I7O | IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), IAPDESCR(60H_08H, 0x60, 0x08, IAP_F_FM | IAP_F_WM | IAP_F_I7O | IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), IAPDESCR(61H, 0x61, IAP_M_AGENT, IAP_F_CA | IAP_F_CC2), IAPDESCR(61H_00H, 0x61, 0x00, IAP_F_FM | IAP_F_CC), IAPDESCR(62H, 0x62, IAP_M_AGENT, IAP_F_ALLCPUSCORE2), IAPDESCR(62H_00H, 0x62, 0x00, IAP_F_FM | IAP_F_CC), IAPDESCR(63H, 0x63, IAP_M_AGENT | IAP_M_CORE, IAP_F_CA | IAP_F_CC2), IAPDESCR(63H, 0x63, IAP_M_CORE, IAP_F_CC), IAPDESCR(63H_01H, 0x63, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), IAPDESCR(63H_02H, 0x63, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), IAPDESCR(64H, 0x64, IAP_M_CORE, IAP_F_CA | IAP_F_CC2), IAPDESCR(64H_40H, 0x64, 0x40, IAP_F_FM | IAP_F_CC), IAPDESCR(65H, 0x65, IAP_M_AGENT | IAP_M_CORE, IAP_F_CA | IAP_F_CC2), IAPDESCR(65H, 0x65, IAP_M_CORE, IAP_F_CC), IAPDESCR(66H, 0x66, IAP_M_AGENT | IAP_M_CORE, IAP_F_ALLCPUSCORE2), IAPDESCR(67H, 0x67, IAP_M_AGENT | IAP_M_CORE, IAP_F_CA | IAP_F_CC2), IAPDESCR(67H, 0x67, IAP_M_AGENT, IAP_F_CC), IAPDESCR(68H, 0x68, IAP_M_AGENT | IAP_M_CORE, IAP_F_ALLCPUSCORE2), IAPDESCR(69H, 0x69, IAP_M_AGENT | IAP_M_CORE, IAP_F_ALLCPUSCORE2), IAPDESCR(6AH, 0x6A, IAP_M_AGENT | IAP_M_CORE, IAP_F_ALLCPUSCORE2), IAPDESCR(6BH, 0x6B, IAP_M_AGENT | IAP_M_CORE, IAP_F_ALLCPUSCORE2), IAPDESCR(6CH, 0x6C, IAP_M_AGENT | IAP_M_CORE, IAP_F_ALLCPUSCORE2), IAPDESCR(6CH_01H, 0x6C, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM), IAPDESCR(6DH, 0x6D, IAP_M_AGENT | IAP_M_CORE, IAP_F_CA | IAP_F_CC2), IAPDESCR(6DH, 0x6D, IAP_M_CORE, IAP_F_CC), IAPDESCR(6EH, 0x6E, IAP_M_AGENT | IAP_M_CORE, IAP_F_CA | IAP_F_CC2), IAPDESCR(6EH, 0x6E, IAP_M_CORE, IAP_F_CC), IAPDESCR(6FH, 0x6F, IAP_M_AGENT | IAP_M_CORE, IAP_F_CA | IAP_F_CC2), IAPDESCR(6FH, 0x6F, IAP_M_CORE, IAP_F_CC), IAPDESCR(70H, 0x70, IAP_M_AGENT | IAP_M_CORE, IAP_F_CA | IAP_F_CC2), IAPDESCR(70H, 0x70, IAP_M_CORE, IAP_F_CC), IAPDESCR(77H, 0x77, IAP_M_AGENT | IAP_M_SNOOPRESPONSE, IAP_F_CA | IAP_F_CC2), IAPDESCR(77H, 0x77, IAP_M_AGENT | IAP_M_MESI, IAP_F_CC), IAPDESCR(78H, 0x78, IAP_M_CORE, IAP_F_CC), IAPDESCR(78H, 0x78, IAP_M_CORE | IAP_M_SNOOPTYPE, IAP_F_CA | IAP_F_CC2), IAPDESCR(79H_02H, 0x79, 0x02, IAP_F_FM | IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), IAPDESCR(79H_04H, 0x79, 0x04, IAP_F_FM | IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), IAPDESCR(79H_08H, 0x79, 0x08, IAP_F_FM | IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), IAPDESCR(79H_10H, 0x79, 0x10, IAP_F_FM | IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), IAPDESCR(79H_18H, 0x79, 0x18, IAP_F_FM | IAP_F_IB | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), IAPDESCR(79H_20H, 0x79, 0x20, IAP_F_FM | IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), IAPDESCR(79H_24H, 0x79, 0x24, IAP_F_FM | IAP_F_IB | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), IAPDESCR(79H_30H, 0x79, 0x30, IAP_F_FM | IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), IAPDESCR(79H_18H, 0x79, 0x18, IAP_F_FM | IAP_F_IB | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), IAPDESCR(7AH, 0x7A, IAP_M_AGENT, IAP_F_CA | IAP_F_CC2), IAPDESCR(7BH, 0x7B, IAP_M_AGENT, IAP_F_CA | IAP_F_CC2), IAPDESCR(7DH, 0x7D, IAP_M_CORE, IAP_F_ALLCPUSCORE2), IAPDESCR(7EH, 0x7E, IAP_M_AGENT | IAP_M_CORE, IAP_F_CA | IAP_F_CC2), IAPDESCR(7EH_00H, 0x7E, 0x00, IAP_F_FM | IAP_F_CC), IAPDESCR(7FH, 0x7F, IAP_M_CORE, IAP_F_CA | IAP_F_CC2), IAPDESCR(80H_00H, 0x80, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), IAPDESCR(80H_01H, 0x80, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_CAS), IAPDESCR(80H_02H, 0x80, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_CAS | IAP_F_HWX), IAPDESCR(80H_03H, 0x80, 0x03, IAP_F_FM | IAP_F_CA | IAP_F_I7 | IAP_F_WM | IAP_F_CAS), IAPDESCR(80H_04H, 0x80, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_IB | IAP_F_IBX), IAPDESCR(81H_00H, 0x81, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), IAPDESCR(81H_01H, 0x81, 0x01, IAP_F_FM | IAP_F_I7O), IAPDESCR(81H_02H, 0x81, 0x02, IAP_F_FM | IAP_F_I7O), IAPDESCR(82H_01H, 0x82, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM), IAPDESCR(82H_02H, 0x82, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2), IAPDESCR(82H_04H, 0x82, 0x04, IAP_F_FM | IAP_F_CA), IAPDESCR(82H_10H, 0x82, 0x10, IAP_F_FM | IAP_F_CA | IAP_F_CC2), IAPDESCR(82H_12H, 0x82, 0x12, IAP_F_FM | IAP_F_CC2), IAPDESCR(82H_40H, 0x82, 0x40, IAP_F_FM | IAP_F_CC2), IAPDESCR(83H_01H, 0x83, 0x01, IAP_F_FM | IAP_F_I7O), IAPDESCR(83H_02H, 0x83, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2), IAPDESCR(85H_00H, 0x85, 0x00, IAP_F_FM | IAP_F_CC), IAPDESCR(85H_01H, 0x85, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), IAPDESCR(85H_02H, 0x85, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), IAPDESCR(85H_04H, 0x85, 0x04, IAP_F_FM | IAP_F_WM | IAP_F_I7O | IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), IAPDESCR(85H_0EH, 0x85, 0x0E, IAP_F_FM | IAP_F_HW | IAP_F_HWX), IAPDESCR(85H_10H, 0x85, 0x10, IAP_F_FM | IAP_F_I7O | IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), IAPDESCR(85H_20H, 0x85, 0x20, IAP_F_FM | IAP_F_I7O | IAP_F_HW | IAP_F_HWX), IAPDESCR(85H_40H, 0x85, 0x40, IAP_F_FM | IAP_F_I7O | IAP_F_HW | IAP_F_HWX), IAPDESCR(85H_60H, 0x85, 0x60, IAP_F_FM | IAP_F_HW | IAP_F_HWX), IAPDESCR(85H_80H, 0x85, 0x80, IAP_F_FM | IAP_F_WM | IAP_F_I7O), IAPDESCR(86H_00H, 0x86, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), IAPDESCR(87H_00H, 0x87, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), IAPDESCR(87H_01H, 0x87, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), IAPDESCR(87H_02H, 0x87, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM), IAPDESCR(87H_04H, 0x87, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), IAPDESCR(87H_08H, 0x87, 0x08, IAP_F_FM | IAP_F_I7 | IAP_F_WM), IAPDESCR(87H_0FH, 0x87, 0x0F, IAP_F_FM | IAP_F_I7 | IAP_F_WM), IAPDESCR(88H_00H, 0x88, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), - IAPDESCR(88H_01H, 0x88, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM | - IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), - IAPDESCR(88H_02H, 0x88, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM | - IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), - IAPDESCR(88H_04H, 0x88, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM | - IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), + IAPDESCR(88H_01H, 0x88, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM), + IAPDESCR(88H_02H, 0x88, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM), + IAPDESCR(88H_04H, 0x88, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM), IAPDESCR(88H_07H, 0x88, 0x07, IAP_F_FM | IAP_F_I7 | IAP_F_WM), - IAPDESCR(88H_08H, 0x88, 0x08, IAP_F_FM | IAP_F_I7 | IAP_F_WM | - IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), - IAPDESCR(88H_10H, 0x88, 0x10, IAP_F_FM | IAP_F_I7 | IAP_F_WM | - IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), - IAPDESCR(88H_20H, 0x88, 0x20, IAP_F_FM | IAP_F_I7 | IAP_F_WM | - IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), + IAPDESCR(88H_08H, 0x88, 0x08, IAP_F_FM | IAP_F_I7 | IAP_F_WM), + IAPDESCR(88H_10H, 0x88, 0x10, IAP_F_FM | IAP_F_I7 | IAP_F_WM), + IAPDESCR(88H_20H, 0x88, 0x20, IAP_F_FM | IAP_F_I7 | IAP_F_WM), IAPDESCR(88H_30H, 0x88, 0x30, IAP_F_FM | IAP_F_I7 | IAP_F_WM), - IAPDESCR(88H_40H, 0x88, 0x40, IAP_F_FM | IAP_F_I7 | IAP_F_WM | - IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), + IAPDESCR(88H_40H, 0x88, 0x40, IAP_F_FM | IAP_F_I7 | IAP_F_WM), IAPDESCR(88H_7FH, 0x88, 0x7F, IAP_F_FM | IAP_F_I7 | IAP_F_WM), - IAPDESCR(88H_80H, 0x88, 0x80, IAP_F_FM | IAP_F_SB | IAP_F_IB | + IAPDESCR(88H_41H, 0x88, 0x41, IAP_F_FM | IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), + IAPDESCR(88H_81H, 0x88, 0x81, IAP_F_FM | IAP_F_SB | IAP_F_IB | + IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), + IAPDESCR(88H_82H, 0x88, 0x82, IAP_F_FM | IAP_F_SB | IAP_F_IB | + IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), + IAPDESCR(88H_84H, 0x88, 0x84, IAP_F_FM | IAP_F_SB | IAP_F_IB | + IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), + IAPDESCR(88H_88H, 0x88, 0x88, IAP_F_FM | IAP_F_SB | IAP_F_IB | + IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), + IAPDESCR(88H_90H, 0x88, 0x90, IAP_F_FM | IAP_F_SB | IAP_F_IB | + IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), + IAPDESCR(88H_A0H, 0x88, 0xA0, IAP_F_FM | IAP_F_SB | IAP_F_IB | + IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), IAPDESCR(88H_FFH, 0x88, 0xFF, IAP_F_FM | IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), IAPDESCR(89H_00H, 0x89, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), - IAPDESCR(89H_01H, 0x89, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM | - IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), + IAPDESCR(89H_01H, 0x89, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM), IAPDESCR(89H_02H, 0x89, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM), - IAPDESCR(89H_04H, 0x89, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM | - IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), + IAPDESCR(89H_04H, 0x89, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM), IAPDESCR(89H_07H, 0x89, 0x07, IAP_F_FM | IAP_F_I7 | IAP_F_WM), - IAPDESCR(89H_08H, 0x89, 0x08, IAP_F_FM | IAP_F_I7 | IAP_F_WM | - IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), - IAPDESCR(89H_10H, 0x89, 0x10, IAP_F_FM | IAP_F_I7 | IAP_F_WM | - IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), - IAPDESCR(89H_20H, 0x89, 0x20, IAP_F_FM | IAP_F_I7 | IAP_F_WM | - IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), + IAPDESCR(89H_08H, 0x89, 0x08, IAP_F_FM | IAP_F_I7 | IAP_F_WM), + IAPDESCR(89H_10H, 0x89, 0x10, IAP_F_FM | IAP_F_I7 | IAP_F_WM), + IAPDESCR(89H_20H, 0x89, 0x20, IAP_F_FM | IAP_F_I7 | IAP_F_WM), IAPDESCR(89H_30H, 0x89, 0x30, IAP_F_FM | IAP_F_I7 | IAP_F_WM), - IAPDESCR(89H_40H, 0x89, 0x40, IAP_F_FM | IAP_F_I7 | IAP_F_WM | - IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), + IAPDESCR(89H_40H, 0x89, 0x40, IAP_F_FM | IAP_F_I7 | IAP_F_WM), IAPDESCR(89H_7FH, 0x89, 0x7F, IAP_F_FM | IAP_F_I7 | IAP_F_WM), - IAPDESCR(89H_80H, 0x89, 0x80, IAP_F_FM | IAP_F_SB | IAP_F_IB | + IAPDESCR(89H_41H, 0x89, 0x41, IAP_F_FM | IAP_F_SB | IAP_F_IB | + IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), + IAPDESCR(89H_81H, 0x89, 0x81, IAP_F_FM | IAP_F_SB | IAP_F_IB | + IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), + IAPDESCR(89H_82H, 0x89, 0x82, IAP_F_FM | IAP_F_SB | IAP_F_IB | + IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), + IAPDESCR(89H_84H, 0x89, 0x84, IAP_F_FM | IAP_F_SB | IAP_F_IB | + IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), + IAPDESCR(89H_88H, 0x89, 0x88, IAP_F_FM | IAP_F_SB | IAP_F_IB | + IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), + IAPDESCR(89H_90H, 0x89, 0x90, IAP_F_FM | IAP_F_SB | IAP_F_IB | + IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), + IAPDESCR(89H_A0H, 0x89, 0xA0, IAP_F_FM | IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), IAPDESCR(89H_FFH, 0x89, 0xFF, IAP_F_FM | IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), IAPDESCR(8AH_00H, 0x8A, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), IAPDESCR(8BH_00H, 0x8B, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), IAPDESCR(8CH_00H, 0x8C, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), IAPDESCR(8DH_00H, 0x8D, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), IAPDESCR(8EH_00H, 0x8E, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), IAPDESCR(8FH_00H, 0x8F, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), IAPDESCR(90H_00H, 0x90, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), IAPDESCR(91H_00H, 0x91, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), IAPDESCR(92H_00H, 0x92, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), IAPDESCR(93H_00H, 0x93, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), IAPDESCR(94H_00H, 0x94, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), IAPDESCR(97H_00H, 0x97, 0x00, IAP_F_FM | IAP_F_CA | IAP_F_CC2), IAPDESCR(98H_00H, 0x98, 0x00, IAP_F_FM | IAP_F_CA | IAP_F_CC2), IAPDESCR(9CH_01H, 0x9C, 0x01, IAP_F_FM | IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), IAPDESCR(A0H_00H, 0xA0, 0x00, IAP_F_FM | IAP_F_CA | IAP_F_CC2), IAPDESCR(A1H_01H, 0xA1, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), IAPDESCR(A1H_02H, 0xA1, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), IAPDESCR(A1H_04H, 0xA1, 0x04, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | /* No desc in IB for this*/ IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), IAPDESCR(A1H_08H, 0xA1, 0x08, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | /* No desc in IB for this*/ IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), IAPDESCR(A1H_0CH, 0xA1, 0x0C, IAP_F_IB | IAP_F_IBX), IAPDESCR(A1H_10H, 0xA1, 0x10, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | /* No desc in IB for this*/ IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), IAPDESCR(A1H_20H, 0xA1, 0x20, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | /* No desc in IB for this*/ IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), IAPDESCR(A1H_30H, 0xA1, 0x30, IAP_F_FM | IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX), IAPDESCR(A1H_40H, 0xA1, 0x40, IAP_F_FM | IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), IAPDESCR(A1H_80H, 0xA1, 0x80, IAP_F_FM | IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), IAPDESCR(A2H_00H, 0xA2, 0x00, IAP_F_FM | IAP_F_CC), IAPDESCR(A2H_01H, 0xA2, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), IAPDESCR(A2H_02H, 0xA2, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_SBX), IAPDESCR(A2H_04H, 0xA2, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), IAPDESCR(A2H_08H, 0xA2, 0x08, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), IAPDESCR(A2H_10H, 0xA2, 0x10, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), IAPDESCR(A2H_20H, 0xA2, 0x20, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_SBX), IAPDESCR(A2H_40H, 0xA2, 0x40, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_SBX), IAPDESCR(A2H_80H, 0xA2, 0x80, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_SBX), IAPDESCR(A3H_01H, 0xA3, 0x01, IAP_F_FM | IAP_F_SBX | IAP_F_IBX | IAP_F_IB | IAP_F_HW | IAP_F_HWX), IAPDESCR(A3H_02H, 0xA3, 0x02, IAP_F_FM | IAP_F_SBX | IAP_F_IBX | IAP_F_IB | IAP_F_HW | IAP_F_HWX), IAPDESCR(A3H_04H, 0xA3, 0x04, IAP_F_FM | IAP_F_SBX | IAP_F_IBX | IAP_F_IB), IAPDESCR(A3H_05H, 0xA3, 0x05, IAP_F_FM | IAP_F_HW | IAP_F_HWX), IAPDESCR(A3H_08H, 0xA3, 0x08, IAP_F_FM | IAP_F_IBX | IAP_F_HW | IAP_F_IB | IAP_F_HWX), IAPDESCR(A3H_0CH, 0xA3, 0x08, IAP_F_FM | IAP_F_HW | IAP_F_HWX), IAPDESCR(A6H_01H, 0xA6, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM), IAPDESCR(A7H_01H, 0xA7, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM), IAPDESCR(A8H_01H, 0xA8, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_IBX | IAP_F_IB |IAP_F_SB | IAP_F_SBX | IAP_F_HW | IAP_F_HWX), IAPDESCR(AAH_01H, 0xAA, 0x01, IAP_F_FM | IAP_F_CC2), IAPDESCR(AAH_02H, 0xAA, 0x02, IAP_F_FM | IAP_F_CA), IAPDESCR(AAH_03H, 0xAA, 0x03, IAP_F_FM | IAP_F_CA), IAPDESCR(AAH_08H, 0xAA, 0x08, IAP_F_FM | IAP_F_CC2), IAPDESCR(ABH_01H, 0xAB, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX), IAPDESCR(ABH_02H, 0xAB, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX), IAPDESCR(ACH_02H, 0xAC, 0x02, IAP_F_FM | IAP_F_SB | IAP_F_SBX), IAPDESCR(ACH_08H, 0xAC, 0x08, IAP_F_FM | IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX), IAPDESCR(ACH_0AH, 0xAC, 0x0A, IAP_F_FM | IAP_F_SB | IAP_F_SBX), IAPDESCR(AEH_01H, 0xAE, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), IAPDESCR(B0H_00H, 0xB0, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), IAPDESCR(B0H_01H, 0xB0, 0x01, IAP_F_FM | IAP_F_WM | IAP_F_I7O | IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), IAPDESCR(B0H_02H, 0xB0, 0x02, IAP_F_FM | IAP_F_WM | IAP_F_I7O | IAP_F_IB | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), IAPDESCR(B0H_04H, 0xB0, 0x04, IAP_F_FM | IAP_F_WM | IAP_F_I7O | IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), IAPDESCR(B0H_08H, 0xB0, 0x08, IAP_F_FM | IAP_F_WM | IAP_F_I7O | IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), IAPDESCR(B0H_10H, 0xB0, 0x10, IAP_F_FM | IAP_F_WM | IAP_F_I7O), IAPDESCR(B0H_20H, 0xB0, 0x20, IAP_F_FM | IAP_F_I7O), IAPDESCR(B0H_40H, 0xB0, 0x40, IAP_F_FM | IAP_F_I7 | IAP_F_WM), IAPDESCR(B0H_80H, 0xB0, 0x80, IAP_F_FM | IAP_F_CA | IAP_F_WM | IAP_F_I7O), IAPDESCR(B1H_00H, 0xB1, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), IAPDESCR(B1H_01H, 0xB1, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX), IAPDESCR(B1H_02H, 0xB1, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), IAPDESCR(B1H_04H, 0xB1, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM), IAPDESCR(B1H_08H, 0xB1, 0x08, IAP_F_FM | IAP_F_I7 | IAP_F_WM), IAPDESCR(B1H_10H, 0xB1, 0x10, IAP_F_FM | IAP_F_I7 | IAP_F_WM), IAPDESCR(B1H_1FH, 0xB1, 0x1F, IAP_F_FM | IAP_F_I7 | IAP_F_WM), IAPDESCR(B1H_20H, 0xB1, 0x20, IAP_F_FM | IAP_F_I7 | IAP_F_WM), IAPDESCR(B1H_3FH, 0xB1, 0x3F, IAP_F_FM | IAP_F_I7 | IAP_F_WM), IAPDESCR(B1H_40H, 0xB1, 0x40, IAP_F_FM | IAP_F_I7 | IAP_F_WM), IAPDESCR(B1H_80H, 0xB1, 0x80, IAP_F_FM | IAP_F_CA | IAP_F_I7 | IAP_F_WM), IAPDESCR(B2H_01H, 0xB2, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_SBX), IAPDESCR(B3H_01H, 0xB3, 0x01, IAP_F_FM | IAP_F_ALLCPUSCORE2 | IAP_F_WM | IAP_F_I7O), IAPDESCR(B3H_02H, 0xB3, 0x02, IAP_F_FM | IAP_F_ALLCPUSCORE2 | IAP_F_WM | IAP_F_I7O), IAPDESCR(B3H_04H, 0xB3, 0x04, IAP_F_FM | IAP_F_ALLCPUSCORE2 | IAP_F_WM | IAP_F_I7O), IAPDESCR(B3H_08H, 0xB3, 0x08, IAP_F_FM | IAP_F_ALLCPUSCORE2), IAPDESCR(B3H_10H, 0xB3, 0x10, IAP_F_FM | IAP_F_ALLCPUSCORE2), IAPDESCR(B3H_20H, 0xB3, 0x20, IAP_F_FM | IAP_F_ALLCPUSCORE2), IAPDESCR(B3H_81H, 0xB3, 0x81, IAP_F_FM | IAP_F_CA), IAPDESCR(B3H_82H, 0xB3, 0x82, IAP_F_FM | IAP_F_CA), IAPDESCR(B3H_84H, 0xB3, 0x84, IAP_F_FM | IAP_F_CA), IAPDESCR(B3H_88H, 0xB3, 0x88, IAP_F_FM | IAP_F_CA), IAPDESCR(B3H_90H, 0xB3, 0x90, IAP_F_FM | IAP_F_CA), IAPDESCR(B3H_A0H, 0xB3, 0xA0, IAP_F_FM | IAP_F_CA), IAPDESCR(B4H_01H, 0xB4, 0x01, IAP_F_FM | IAP_F_WM), IAPDESCR(B4H_02H, 0xB4, 0x02, IAP_F_FM | IAP_F_WM), IAPDESCR(B4H_04H, 0xB4, 0x04, IAP_F_FM | IAP_F_WM), IAPDESCR(B6H_01H, 0xB6, 0x01, IAP_F_FM | IAP_F_SB | IAP_F_SBX), IAPDESCR(B6H_04H, 0xB6, 0x04, IAP_F_CAS), IAPDESCR(B7H_01H, 0xB7, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_CAS | IAP_F_HWX), IAPDESCR(B7H_02H, 0xB7, 0x02, IAP_F_CAS), IAPDESCR(B8H_01H, 0xB8, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM), IAPDESCR(B8H_02H, 0xB8, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM), IAPDESCR(B8H_04H, 0xB8, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM), IAPDESCR(BAH_01H, 0xBA, 0x01, IAP_F_FM | IAP_F_I7O), IAPDESCR(BAH_02H, 0xBA, 0x02, IAP_F_FM | IAP_F_I7O), IAPDESCR(BBH_01H, 0xBB, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), IAPDESCR(BCH_11H, 0xBC, 0x11, IAP_F_FM | IAP_F_HW | IAP_F_HWX), IAPDESCR(BCH_12H, 0xBC, 0x12, IAP_F_FM | IAP_F_HW | IAP_F_HWX), IAPDESCR(BCH_14H, 0xBC, 0x14, IAP_F_FM | IAP_F_HW | IAP_F_HWX), IAPDESCR(BCH_18H, 0xBC, 0x18, IAP_F_FM | IAP_F_HW | IAP_F_HWX), IAPDESCR(BCH_21H, 0xBC, 0x21, IAP_F_FM | IAP_F_HW | IAP_F_HWX), IAPDESCR(BCH_22H, 0xBC, 0x22, IAP_F_FM | IAP_F_HW | IAP_F_HWX), IAPDESCR(BCH_24H, 0xBC, 0x24, IAP_F_FM | IAP_F_HW | IAP_F_HWX), IAPDESCR(BCH_28H, 0xBC, 0x28, IAP_F_FM | IAP_F_HW | IAP_F_HWX), IAPDESCR(BDH_01H, 0xBD, 0x01, IAP_F_FM | IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), IAPDESCR(BDH_20H, 0xBD, 0x20, IAP_F_FM | IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), IAPDESCR(BFH_05H, 0xBF, 0x05, IAP_F_FM | IAP_F_SB | IAP_F_SBX), IAPDESCR(C0H_00H, 0xC0, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2 | IAP_F_WM | IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_CAS | IAP_F_HWX), IAPDESCR(C0H_01H, 0xC0, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), IAPDESCR(C0H_02H, 0xC0, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | IAP_F_I7 | IAP_F_WM | IAP_F_SB), IAPDESCR(C0H_04H, 0xC0, 0x04, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | IAP_F_I7 | IAP_F_WM), IAPDESCR(C0H_08H, 0xC0, 0x08, IAP_F_FM | IAP_F_CC2E), IAPDESCR(C1H_00H, 0xC1, 0x00, IAP_F_FM | IAP_F_CC), IAPDESCR(C1H_01H, 0xC1, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2), IAPDESCR(C1H_02H, 0xC1, 0x02, IAP_F_FM | IAP_F_SB | IAP_F_SBX), IAPDESCR(C1H_08H, 0xC1, 0x08, IAP_F_FM | IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), IAPDESCR(C1H_10H, 0xC1, 0x10, IAP_F_FM | IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), IAPDESCR(C1H_20H, 0xC1, 0x20, IAP_F_FM | IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX), IAPDESCR(C1H_40H, 0xC1, 0x40, IAP_F_FM | IAP_F_HW | IAP_F_HWX), IAPDESCR(C1H_80H, 0xC1, 0x80, IAP_F_IB | IAP_F_IBX), IAPDESCR(C1H_FEH, 0xC1, 0xFE, IAP_F_FM | IAP_F_CA | IAP_F_CC2), IAPDESCR(C2H_00H, 0xC2, 0x00, IAP_F_FM | IAP_F_CC), IAPDESCR(C2H_01H, 0xC2, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_CAS | IAP_F_HWX), IAPDESCR(C2H_02H, 0xC2, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), IAPDESCR(C2H_04H, 0xC2, 0x04, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | IAP_F_I7 | IAP_F_WM), IAPDESCR(C2H_07H, 0xC2, 0x07, IAP_F_FM | IAP_F_CA | IAP_F_CC2), IAPDESCR(C2H_08H, 0xC2, 0x08, IAP_F_FM | IAP_F_CA | IAP_F_CC2), IAPDESCR(C2H_0FH, 0xC2, 0x0F, IAP_F_FM | IAP_F_CC2), IAPDESCR(C2H_10H, 0xC2, 0x10, IAP_F_FM | IAP_F_CA | IAP_F_CAS), IAPDESCR(C3H_00H, 0xC3, 0x00, IAP_F_FM | IAP_F_CC), IAPDESCR(C3H_01H, 0xC3, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | IAP_F_I7 | IAP_F_WM | IAP_F_CAS), IAPDESCR(C3H_02H, 0xC3, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_CAS | IAP_F_HWX), IAPDESCR(C3H_04H, 0xC3, 0x04, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_CAS | IAP_F_HWX), IAPDESCR(C3H_08H, 0xC3, 0x08, IAP_F_CAS), IAPDESCR(C3H_10H, 0xC3, 0x10, IAP_F_FM | IAP_F_I7O), IAPDESCR(C3H_20H, 0xC3, 0x20, IAP_F_FM | IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), IAPDESCR(C4H_00H, 0xC4, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2 | IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_CAS | IAP_F_HWX), IAPDESCR(C4H_01H, 0xC4, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), IAPDESCR(C4H_02H, 0xC4, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), IAPDESCR(C4H_04H, 0xC4, 0x04, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), IAPDESCR(C4H_08H, 0xC4, 0x08, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), IAPDESCR(C4H_0CH, 0xC4, 0x0C, IAP_F_FM | IAP_F_CA | IAP_F_CC2), IAPDESCR(C4H_0FH, 0xC4, 0x0F, IAP_F_FM | IAP_F_CA), IAPDESCR(C4H_10H, 0xC4, 0x10, IAP_F_FM | IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), IAPDESCR(C4H_20H, 0xC4, 0x20, IAP_F_FM | IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), IAPDESCR(C4H_40H, 0xC4, 0x40, IAP_F_FM | IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), IAPDESCR(C4H_7EH, 0xC4, 0x7E, IAP_F_CAS), IAPDESCR(C4H_BFH, 0xC4, 0xBF, IAP_F_CAS), IAPDESCR(C4H_EBH, 0xC4, 0xEB, IAP_F_CAS), IAPDESCR(C4H_F7H, 0xC4, 0xF7, IAP_F_CAS), IAPDESCR(C4H_F9H, 0xC4, 0xF9, IAP_F_CAS), IAPDESCR(C4H_FBH, 0xC4, 0xFB, IAP_F_CAS), IAPDESCR(C4H_FDH, 0xC4, 0xFD, IAP_F_CAS), IAPDESCR(C4H_FEH, 0xC4, 0xFE, IAP_F_CAS), IAPDESCR(C5H_00H, 0xC5, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2 | IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_CAS | IAP_F_HWX), IAPDESCR(C5H_01H, 0xC5, 0x01, IAP_F_FM | IAP_F_WM | IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), IAPDESCR(C5H_02H, 0xC5, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX), IAPDESCR(C5H_04H, 0xC5, 0x04, IAP_F_FM | IAP_F_WM | IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), IAPDESCR(C5H_10H, 0xC5, 0x10, IAP_F_FM | IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX), IAPDESCR(C5H_20H, 0xC5, 0x20, IAP_F_FM | IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), IAPDESCR(C5H_7EH, 0xC5, 0x7E, IAP_F_CAS), IAPDESCR(C5H_BFH, 0xC5, 0xBF, IAP_F_CAS), IAPDESCR(C5H_EBH, 0xC5, 0xEB, IAP_F_CAS), IAPDESCR(C5H_F7H, 0xC5, 0xF7, IAP_F_CAS), IAPDESCR(C5H_F9H, 0xC5, 0xF9, IAP_F_CAS), IAPDESCR(C5H_FBH, 0xC5, 0xFB, IAP_F_CAS), IAPDESCR(C5H_FDH, 0xC5, 0xFD, IAP_F_CAS), IAPDESCR(C5H_FEH, 0xC5, 0xFE, IAP_F_CAS), IAPDESCR(C6H_00H, 0xC6, 0x00, IAP_F_FM | IAP_F_CC), IAPDESCR(C6H_01H, 0xC6, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2), IAPDESCR(C6H_02H, 0xC6, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2), IAPDESCR(C7H_00H, 0xC7, 0x00, IAP_F_FM | IAP_F_CC), IAPDESCR(C7H_01H, 0xC7, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | IAP_F_I7 | IAP_F_WM), IAPDESCR(C7H_02H, 0xC7, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | IAP_F_I7 | IAP_F_WM), IAPDESCR(C7H_04H, 0xC7, 0x04, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | IAP_F_I7 | IAP_F_WM), IAPDESCR(C7H_08H, 0xC7, 0x08, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | IAP_F_I7 | IAP_F_WM), IAPDESCR(C7H_10H, 0xC7, 0x10, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | IAP_F_I7 | IAP_F_WM), IAPDESCR(C7H_1FH, 0xC7, 0x1F, IAP_F_FM | IAP_F_CA | IAP_F_CC2), IAPDESCR(C8H_00H, 0xC8, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), IAPDESCR(C8H_20H, 0xC8, 0x20, IAP_F_FM | IAP_F_I7 | IAP_F_WM), IAPDESCR(C9H_00H, 0xC9, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), IAPDESCR(CAH_00H, 0xCA, 0x00, IAP_F_FM | IAP_F_CC), IAPDESCR(CAH_01H, 0xCA, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | IAP_F_CAS), IAPDESCR(CAH_02H, 0xCA, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), IAPDESCR(CAH_04H, 0xCA, 0x04, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), IAPDESCR(CAH_08H, 0xCA, 0x08, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), IAPDESCR(CAH_10H, 0xCA, 0x10, IAP_F_FM | IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), IAPDESCR(CAH_1EH, 0xCA, 0x1E, IAP_F_FM | IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), IAPDESCR(CAH_20H, 0xCA, 0x20, IAP_F_CAS), IAPDESCR(CAH_3FH, 0xCA, 0x3F, IAP_F_CAS), IAPDESCR(CAH_50H, 0xCA, 0x50, IAP_F_CAS), IAPDESCR(CBH_01H, 0xCB, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | IAP_F_I7 | IAP_F_WM | IAP_F_CAS), IAPDESCR(CBH_02H, 0xCB, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | IAP_F_I7 | IAP_F_WM), IAPDESCR(CBH_04H, 0xCB, 0x04, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | IAP_F_I7 | IAP_F_WM), IAPDESCR(CBH_08H, 0xCB, 0x08, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | IAP_F_I7 | IAP_F_WM), IAPDESCR(CBH_10H, 0xCB, 0x10, IAP_F_FM | IAP_F_CC2 | IAP_F_I7 | IAP_F_WM), IAPDESCR(CBH_1FH, 0xCB, 0x1F, IAP_F_CAS), IAPDESCR(CBH_40H, 0xCB, 0x40, IAP_F_FM | IAP_F_I7 | IAP_F_WM), IAPDESCR(CBH_80H, 0xCB, 0x80, IAP_F_FM | IAP_F_I7 | IAP_F_WM), IAPDESCR(CCH_00H, 0xCC, 0x00, IAP_F_FM | IAP_F_CC), IAPDESCR(CCH_01H, 0xCC, 0x01, IAP_F_FM | IAP_F_ALLCPUSCORE2 | IAP_F_I7 | IAP_F_WM), IAPDESCR(CCH_02H, 0xCC, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | IAP_F_I7 | IAP_F_WM), IAPDESCR(CCH_03H, 0xCC, 0x03, IAP_F_FM | IAP_F_I7 | IAP_F_WM), IAPDESCR(CCH_20H, 0xCC, 0x20, IAP_F_FM | IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), IAPDESCR(CDH_00H, 0xCD, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), IAPDESCR(CDH_01H, 0xCD, 0x01, IAP_F_FM | IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_CAS | IAP_F_HWX), IAPDESCR(CDH_02H, 0xCD, 0x02, IAP_F_FM | IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX), IAPDESCR(CEH_00H, 0xCE, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), IAPDESCR(CFH_00H, 0xCF, 0x00, IAP_F_FM | IAP_F_CA | IAP_F_CC2), /* Sandy Bridge / Sandy Bridge Xeon - 11, 12, 21, 41, 42, 81, 82 */ IAPDESCR(D0H_00H, 0xD0, 0x00, IAP_F_FM | IAP_F_CC), IAPDESCR(D0H_01H, 0xD0, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_IB | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), IAPDESCR(D0H_02H, 0xD0, 0x02, IAP_F_FM | IAP_F_IB | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), IAPDESCR(D0H_10H, 0xD0, 0x10, IAP_F_FM | IAP_F_IB | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), IAPDESCR(D0H_11H, 0xD0, 0x11, IAP_F_FM | IAP_F_SB | IAP_F_SBX), IAPDESCR(D0H_12H, 0xD0, 0x12, IAP_F_FM | IAP_F_SB | IAP_F_SBX), IAPDESCR(D0H_20H, 0xD0, 0x20, IAP_F_FM | IAP_F_IB | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), IAPDESCR(D0H_21H, 0xD0, 0x21, IAP_F_FM | IAP_F_SB | IAP_F_SBX), IAPDESCR(D0H_40H, 0xD0, 0x40, IAP_F_FM | IAP_F_IB | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), IAPDESCR(D0H_41H, 0xD0, 0x41, IAP_F_FM | IAP_F_SB | IAP_F_SBX | IAP_F_IB | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), /* Not in spec but in linux and Vtune guide */ IAPDESCR(D0H_42H, 0xD0, 0x42, IAP_F_FM | IAP_F_SB | IAP_F_SBX | IAP_F_IB | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), /* Not in spec but in linux and Vtune guide */ IAPDESCR(D0H_80H, 0xD0, 0x80, IAP_F_FM | IAP_F_IB | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), IAPDESCR(D0H_81H, 0xD0, 0x81, IAP_F_FM | IAP_F_SB | IAP_F_SBX | IAP_F_IB | IAP_F_IBX), /* Not in spec but in linux and Vtune guide */ IAPDESCR(D0H_82H, 0xD0, 0x82, IAP_F_FM | IAP_F_SB | IAP_F_SBX | IAP_F_IB | IAP_F_IBX), /* Not in spec but in linux and Vtune guide */ IAPDESCR(D1H_01H, 0xD1, 0x01, IAP_F_FM | IAP_F_WM | IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), IAPDESCR(D1H_02H, 0xD1, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), IAPDESCR(D1H_04H, 0xD1, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), IAPDESCR(D1H_08H, 0xD1, 0x08, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_IB | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), IAPDESCR(D1H_10H, 0xD1, 0x10, IAP_F_HW | IAP_F_IB | IAP_F_IBX | IAP_F_HWX), IAPDESCR(D1H_20H, 0xD1, 0x20, IAP_F_FM | IAP_F_SBX | IAP_F_IBX | IAP_F_IB | IAP_F_HW | IAP_F_HWX), IAPDESCR(D1H_40H, 0xD1, 0x40, IAP_F_FM | IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), IAPDESCR(D2H_01H, 0xD2, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_SBX | IAP_F_IB | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), IAPDESCR(D2H_02H, 0xD2, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_SBX | IAP_F_IB | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), IAPDESCR(D2H_04H, 0xD2, 0x04, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_SBX | IAP_F_IB | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), IAPDESCR(D2H_08H, 0xD2, 0x08, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_SBX | IAP_F_IB | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), IAPDESCR(D2H_0FH, 0xD2, 0x0F, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_SBX | IAP_F_IB | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), IAPDESCR(D2H_10H, 0xD2, 0x10, IAP_F_FM | IAP_F_CC2E), IAPDESCR(D3H_01H, 0xD3, 0x01, IAP_F_FM | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), IAPDESCR(D3H_03H, 0xD0, 0x3, IAP_F_IBX ), IAPDESCR(D3H_04H, 0xD3, 0x04, IAP_F_FM | IAP_F_SBX | IAP_F_IBX), /* Not defined for IBX */ IAPDESCR(D3H_0CH, 0xD0, 0x0, IAP_F_IBX ), IAPDESCR(D3H_10H, 0xD3, 0x10, IAP_F_IBX ), IAPDESCR(D3H_20H, 0xD3, 0x20, IAP_F_IBX ), IAPDESCR(D4H_01H, 0xD4, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | IAP_F_I7 | IAP_F_WM), IAPDESCR(D4H_02H, 0xD4, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | IAP_F_SB | IAP_F_SBX), IAPDESCR(D4H_04H, 0xD4, 0x04, IAP_F_FM | IAP_F_CA | IAP_F_CC2), IAPDESCR(D4H_08H, 0xD4, 0x08, IAP_F_FM | IAP_F_CA | IAP_F_CC2), IAPDESCR(D4H_0FH, 0xD4, 0x0F, IAP_F_FM | IAP_F_CA | IAP_F_CC2), IAPDESCR(D5H_01H, 0xD5, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2 | IAP_F_I7 | IAP_F_WM), IAPDESCR(D5H_02H, 0xD5, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2), IAPDESCR(D5H_04H, 0xD5, 0x04, IAP_F_FM | IAP_F_CA | IAP_F_CC2), IAPDESCR(D5H_08H, 0xD5, 0x08, IAP_F_FM | IAP_F_CA | IAP_F_CC2), IAPDESCR(D5H_0FH, 0xD5, 0x0F, IAP_F_FM | IAP_F_CA | IAP_F_CC2), IAPDESCR(D7H_00H, 0xD7, 0x00, IAP_F_FM | IAP_F_CC), IAPDESCR(D8H_00H, 0xD8, 0x00, IAP_F_FM | IAP_F_CC), IAPDESCR(D8H_01H, 0xD8, 0x01, IAP_F_FM | IAP_F_CC), IAPDESCR(D8H_02H, 0xD8, 0x02, IAP_F_FM | IAP_F_CC), IAPDESCR(D8H_03H, 0xD8, 0x03, IAP_F_FM | IAP_F_CC), IAPDESCR(D8H_04H, 0xD8, 0x04, IAP_F_FM | IAP_F_CC), IAPDESCR(D9H_00H, 0xD9, 0x00, IAP_F_FM | IAP_F_CC), IAPDESCR(D9H_01H, 0xD9, 0x01, IAP_F_FM | IAP_F_CC), IAPDESCR(D9H_02H, 0xD9, 0x02, IAP_F_FM | IAP_F_CC), IAPDESCR(D9H_03H, 0xD9, 0x03, IAP_F_FM | IAP_F_CC), IAPDESCR(DAH_00H, 0xDA, 0x00, IAP_F_FM | IAP_F_CC), IAPDESCR(DAH_01H, 0xDA, 0x01, IAP_F_FM | IAP_F_CC), IAPDESCR(DAH_02H, 0xDA, 0x02, IAP_F_FM | IAP_F_CC), IAPDESCR(DBH_00H, 0xDB, 0x00, IAP_F_FM | IAP_F_CC), IAPDESCR(DBH_01H, 0xDB, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM), IAPDESCR(DCH_01H, 0xDC, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_CC2), IAPDESCR(DCH_02H, 0xDC, 0x02, IAP_F_FM | IAP_F_CA | IAP_F_CC2), IAPDESCR(DCH_04H, 0xDC, 0x04, IAP_F_FM | IAP_F_CA | IAP_F_CC2), IAPDESCR(DCH_08H, 0xDC, 0x08, IAP_F_FM | IAP_F_CA | IAP_F_CC2), IAPDESCR(DCH_10H, 0xDC, 0x10, IAP_F_FM | IAP_F_CA | IAP_F_CC2), IAPDESCR(DCH_1FH, 0xDC, 0x1F, IAP_F_FM | IAP_F_CA | IAP_F_CC2), IAPDESCR(E0H_00H, 0xE0, 0x00, IAP_F_FM | IAP_F_CC | IAP_F_CC2), IAPDESCR(E0H_01H, 0xE0, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_I7 | IAP_F_WM), IAPDESCR(E2H_00H, 0xE2, 0x00, IAP_F_FM | IAP_F_CC), IAPDESCR(E4H_00H, 0xE4, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), IAPDESCR(E4H_01H, 0xE4, 0x01, IAP_F_FM | IAP_F_I7O), IAPDESCR(E5H_01H, 0xE5, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM), IAPDESCR(E6H_00H, 0xE6, 0x00, IAP_F_FM | IAP_F_CC | IAP_F_CC2), IAPDESCR(E6H_01H, 0xE6, 0x01, IAP_F_FM | IAP_F_CA | IAP_F_I7 | IAP_F_WM | IAP_F_SBX | IAP_F_CAS), IAPDESCR(E6H_02H, 0xE6, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM), IAPDESCR(E6H_08H, 0xE6, 0x08, IAP_F_CAS), IAPDESCR(E6H_10H, 0xE6, 0x10, IAP_F_CAS), IAPDESCR(E6H_1FH, 0xE6, 0x1F, IAP_F_FM | IAP_F_IB | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), IAPDESCR(E7H_01H, 0xE7, 0x01, IAP_F_CAS), IAPDESCR(E8H_01H, 0xE8, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM), IAPDESCR(E8H_02H, 0xE8, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM), IAPDESCR(E8H_03H, 0xE8, 0x03, IAP_F_FM | IAP_F_I7O), IAPDESCR(ECH_01H, 0xEC, 0x01, IAP_F_FM | IAP_F_WM), IAPDESCR(F0H_00H, 0xF0, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), IAPDESCR(F0H_01H, 0xF0, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), IAPDESCR(F0H_02H, 0xF0, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), IAPDESCR(F0H_04H, 0xF0, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), IAPDESCR(F0H_08H, 0xF0, 0x08, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), IAPDESCR(F0H_10H, 0xF0, 0x10, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), IAPDESCR(F0H_20H, 0xF0, 0x20, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), IAPDESCR(F0H_40H, 0xF0, 0x40, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), IAPDESCR(F0H_80H, 0xF0, 0x80, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), IAPDESCR(F1H_01H, 0xF1, 0x01, IAP_F_FM | IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), IAPDESCR(F1H_02H, 0xF1, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), IAPDESCR(F1H_04H, 0xF1, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), IAPDESCR(F1H_07H, 0xF1, 0x07, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX | IAP_F_HW | IAP_F_HWX), IAPDESCR(F2H_01H, 0xF2, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX), IAPDESCR(F2H_02H, 0xF2, 0x02, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX), IAPDESCR(F2H_04H, 0xF2, 0x04, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX), IAPDESCR(F2H_05H, 0xF2, 0x05, IAP_F_FM | IAP_F_HW | IAP_F_HWX), IAPDESCR(F2H_06H, 0xF2, 0x06, IAP_F_FM | IAP_F_HW | IAP_F_HWX), IAPDESCR(F2H_08H, 0xF2, 0x08, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_IB | IAP_F_SBX | IAP_F_IBX), IAPDESCR(F2H_0AH, 0xF2, 0x0A, IAP_F_FM | IAP_F_SB | IAP_F_SBX | IAP_F_IBX), IAPDESCR(F2H_0FH, 0xF2, 0x0F, IAP_F_FM | IAP_F_I7 | IAP_F_WM), IAPDESCR(F3H_01H, 0xF3, 0x01, IAP_F_FM | IAP_F_I7O), IAPDESCR(F3H_02H, 0xF3, 0x02, IAP_F_FM | IAP_F_I7O), IAPDESCR(F3H_04H, 0xF3, 0x04, IAP_F_FM | IAP_F_I7O), IAPDESCR(F3H_08H, 0xF3, 0x08, IAP_F_FM | IAP_F_I7O), IAPDESCR(F3H_10H, 0xF3, 0x10, IAP_F_FM | IAP_F_I7O), IAPDESCR(F3H_20H, 0xF3, 0x20, IAP_F_FM | IAP_F_I7O), IAPDESCR(F4H_01H, 0xF4, 0x01, IAP_F_FM | IAP_F_I7O), IAPDESCR(F4H_02H, 0xF4, 0x02, IAP_F_FM | IAP_F_I7O), IAPDESCR(F4H_04H, 0xF4, 0x04, IAP_F_FM | IAP_F_WM | IAP_F_I7O), IAPDESCR(F4H_08H, 0xF4, 0x08, IAP_F_FM | IAP_F_I7O), IAPDESCR(F4H_10H, 0xF4, 0x10, IAP_F_FM | IAP_F_I7 | IAP_F_WM | IAP_F_SB | IAP_F_SBX), IAPDESCR(F6H_01H, 0xF6, 0x01, IAP_F_FM | IAP_F_I7 | IAP_F_WM), IAPDESCR(F7H_01H, 0xF7, 0x01, IAP_F_FM | IAP_F_WM | IAP_F_I7), IAPDESCR(F7H_02H, 0xF7, 0x02, IAP_F_FM | IAP_F_WM | IAP_F_I7), IAPDESCR(F7H_04H, 0xF7, 0x04, IAP_F_FM | IAP_F_WM | IAP_F_I7), IAPDESCR(F8H_00H, 0xF8, 0x00, IAP_F_FM | IAP_F_ALLCPUSCORE2), IAPDESCR(F8H_01H, 0xF8, 0x01, IAP_F_FM | IAP_F_I7O), IAPDESCR(FDH_01H, 0xFD, 0x01, IAP_F_FM | IAP_F_WM | IAP_F_I7), IAPDESCR(FDH_02H, 0xFD, 0x02, IAP_F_FM | IAP_F_WM | IAP_F_I7), IAPDESCR(FDH_04H, 0xFD, 0x04, IAP_F_FM | IAP_F_WM | IAP_F_I7), IAPDESCR(FDH_08H, 0xFD, 0x08, IAP_F_FM | IAP_F_WM | IAP_F_I7), IAPDESCR(FDH_10H, 0xFD, 0x10, IAP_F_FM | IAP_F_WM | IAP_F_I7), IAPDESCR(FDH_20H, 0xFD, 0x20, IAP_F_FM | IAP_F_WM | IAP_F_I7), IAPDESCR(FDH_40H, 0xFD, 0x40, IAP_F_FM | IAP_F_WM | IAP_F_I7), }; static const int niap_events = sizeof(iap_events) / sizeof(iap_events[0]); static pmc_value_t iap_perfctr_value_to_reload_count(pmc_value_t v) { /* If the PMC has overflowed, return a reload count of zero. */ if ((v & (1ULL << (core_iap_width - 1))) == 0) return (0); v &= (1ULL << core_iap_width) - 1; return (1ULL << core_iap_width) - v; } static pmc_value_t iap_reload_count_to_perfctr_value(pmc_value_t rlc) { return (1ULL << core_iap_width) - rlc; } static int iap_pmc_has_overflowed(int ri) { uint64_t v; /* * We treat a Core (i.e., Intel architecture v1) PMC as has * having overflowed if its MSB is zero. */ v = rdpmc(ri); return ((v & (1ULL << (core_iap_width - 1))) == 0); } /* * Check an event against the set of supported architectural events. * * If the event is not architectural EV_IS_NOTARCH is returned. * If the event is architectural and supported on this CPU, the correct * event+umask mapping is returned in map, and EV_IS_ARCH_SUPP is returned. * Otherwise, the function returns EV_IS_ARCH_NOTSUPP. */ static int iap_is_event_architectural(enum pmc_event pe, enum pmc_event *map) { enum core_arch_events ae; switch (pe) { case PMC_EV_IAP_ARCH_UNH_COR_CYC: ae = CORE_AE_UNHALTED_CORE_CYCLES; *map = PMC_EV_IAP_EVENT_3CH_00H; break; case PMC_EV_IAP_ARCH_INS_RET: ae = CORE_AE_INSTRUCTION_RETIRED; *map = PMC_EV_IAP_EVENT_C0H_00H; break; case PMC_EV_IAP_ARCH_UNH_REF_CYC: ae = CORE_AE_UNHALTED_REFERENCE_CYCLES; *map = PMC_EV_IAP_EVENT_3CH_01H; break; case PMC_EV_IAP_ARCH_LLC_REF: ae = CORE_AE_LLC_REFERENCE; *map = PMC_EV_IAP_EVENT_2EH_4FH; break; case PMC_EV_IAP_ARCH_LLC_MIS: ae = CORE_AE_LLC_MISSES; *map = PMC_EV_IAP_EVENT_2EH_41H; break; case PMC_EV_IAP_ARCH_BR_INS_RET: ae = CORE_AE_BRANCH_INSTRUCTION_RETIRED; *map = PMC_EV_IAP_EVENT_C4H_00H; break; case PMC_EV_IAP_ARCH_BR_MIS_RET: ae = CORE_AE_BRANCH_MISSES_RETIRED; *map = PMC_EV_IAP_EVENT_C5H_00H; break; default: /* Non architectural event. */ return (EV_IS_NOTARCH); } return (((core_architectural_events & (1 << ae)) == 0) ? EV_IS_ARCH_NOTSUPP : EV_IS_ARCH_SUPP); } static int iap_event_corei7_ok_on_counter(enum pmc_event pe, int ri) { uint32_t mask; switch (pe) { /* * Events valid only on counter 0, 1. */ case PMC_EV_IAP_EVENT_40H_01H: case PMC_EV_IAP_EVENT_40H_02H: case PMC_EV_IAP_EVENT_40H_04H: case PMC_EV_IAP_EVENT_40H_08H: case PMC_EV_IAP_EVENT_40H_0FH: case PMC_EV_IAP_EVENT_41H_02H: case PMC_EV_IAP_EVENT_41H_04H: case PMC_EV_IAP_EVENT_41H_08H: case PMC_EV_IAP_EVENT_42H_01H: case PMC_EV_IAP_EVENT_42H_02H: case PMC_EV_IAP_EVENT_42H_04H: case PMC_EV_IAP_EVENT_42H_08H: case PMC_EV_IAP_EVENT_43H_01H: case PMC_EV_IAP_EVENT_43H_02H: case PMC_EV_IAP_EVENT_51H_01H: case PMC_EV_IAP_EVENT_51H_02H: case PMC_EV_IAP_EVENT_51H_04H: case PMC_EV_IAP_EVENT_51H_08H: case PMC_EV_IAP_EVENT_63H_01H: case PMC_EV_IAP_EVENT_63H_02H: mask = 0x3; break; default: mask = ~0; /* Any row index is ok. */ } return (mask & (1 << ri)); } static int iap_event_westmere_ok_on_counter(enum pmc_event pe, int ri) { uint32_t mask; switch (pe) { /* * Events valid only on counter 0. */ case PMC_EV_IAP_EVENT_60H_01H: case PMC_EV_IAP_EVENT_60H_02H: case PMC_EV_IAP_EVENT_60H_04H: case PMC_EV_IAP_EVENT_60H_08H: case PMC_EV_IAP_EVENT_B3H_01H: case PMC_EV_IAP_EVENT_B3H_02H: case PMC_EV_IAP_EVENT_B3H_04H: mask = 0x1; break; /* * Events valid only on counter 0, 1. */ case PMC_EV_IAP_EVENT_4CH_01H: case PMC_EV_IAP_EVENT_4EH_01H: case PMC_EV_IAP_EVENT_4EH_02H: case PMC_EV_IAP_EVENT_4EH_04H: case PMC_EV_IAP_EVENT_51H_01H: case PMC_EV_IAP_EVENT_51H_02H: case PMC_EV_IAP_EVENT_51H_04H: case PMC_EV_IAP_EVENT_51H_08H: case PMC_EV_IAP_EVENT_63H_01H: case PMC_EV_IAP_EVENT_63H_02H: mask = 0x3; break; default: mask = ~0; /* Any row index is ok. */ } return (mask & (1 << ri)); } static int iap_event_sb_sbx_ib_ibx_ok_on_counter(enum pmc_event pe, int ri) { uint32_t mask; switch (pe) { /* Events valid only on counter 0. */ case PMC_EV_IAP_EVENT_B7H_01H: mask = 0x1; break; /* Events valid only on counter 1. */ case PMC_EV_IAP_EVENT_C0H_01H: mask = 0x2; break; /* Events valid only on counter 2. */ case PMC_EV_IAP_EVENT_48H_01H: case PMC_EV_IAP_EVENT_A2H_02H: case PMC_EV_IAP_EVENT_A3H_08H: mask = 0x4; break; /* Events valid only on counter 3. */ case PMC_EV_IAP_EVENT_BBH_01H: case PMC_EV_IAP_EVENT_CDH_01H: case PMC_EV_IAP_EVENT_CDH_02H: mask = 0x8; break; default: mask = ~0; /* Any row index is ok. */ } return (mask & (1 << ri)); } static int iap_event_ok_on_counter(enum pmc_event pe, int ri) { uint32_t mask; switch (pe) { /* * Events valid only on counter 0. */ case PMC_EV_IAP_EVENT_10H_00H: case PMC_EV_IAP_EVENT_14H_00H: case PMC_EV_IAP_EVENT_18H_00H: case PMC_EV_IAP_EVENT_B3H_01H: case PMC_EV_IAP_EVENT_B3H_02H: case PMC_EV_IAP_EVENT_B3H_04H: case PMC_EV_IAP_EVENT_C1H_00H: case PMC_EV_IAP_EVENT_CBH_01H: case PMC_EV_IAP_EVENT_CBH_02H: mask = (1 << 0); break; /* * Events valid only on counter 1. */ case PMC_EV_IAP_EVENT_11H_00H: case PMC_EV_IAP_EVENT_12H_00H: case PMC_EV_IAP_EVENT_13H_00H: mask = (1 << 1); break; default: mask = ~0; /* Any row index is ok. */ } return (mask & (1 << ri)); } static int iap_allocate_pmc(int cpu, int ri, struct pmc *pm, const struct pmc_op_pmcallocate *a) { int arch, n, model; enum pmc_event ev, map; struct iap_event_descr *ie; uint32_t c, caps, config, cpuflag, evsel, mask; KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), ("[core,%d] illegal CPU %d", __LINE__, cpu)); KASSERT(ri >= 0 && ri < core_iap_npmc, ("[core,%d] illegal row-index value %d", __LINE__, ri)); /* check requested capabilities */ caps = a->pm_caps; if ((IAP_PMC_CAPS & caps) != caps) return (EPERM); map = 0; /* XXX: silent GCC warning */ arch = iap_is_event_architectural(pm->pm_event, &map); if (arch == EV_IS_ARCH_NOTSUPP) return (EOPNOTSUPP); else if (arch == EV_IS_ARCH_SUPP) ev = map; else ev = pm->pm_event; /* * A small number of events are not supported in all the * processors based on a given microarchitecture. */ if (ev == PMC_EV_IAP_EVENT_0FH_01H || ev == PMC_EV_IAP_EVENT_0FH_80H) { model = ((cpu_id & 0xF0000) >> 12) | ((cpu_id & 0xF0) >> 4); if (core_cputype == PMC_CPU_INTEL_COREI7 && model != 0x2E) return (EINVAL); } switch (core_cputype) { case PMC_CPU_INTEL_COREI7: case PMC_CPU_INTEL_NEHALEM_EX: if (iap_event_corei7_ok_on_counter(ev, ri) == 0) return (EINVAL); break; case PMC_CPU_INTEL_BROADWELL: case PMC_CPU_INTEL_SANDYBRIDGE: case PMC_CPU_INTEL_SANDYBRIDGE_XEON: case PMC_CPU_INTEL_IVYBRIDGE: case PMC_CPU_INTEL_IVYBRIDGE_XEON: case PMC_CPU_INTEL_HASWELL: case PMC_CPU_INTEL_HASWELL_XEON: if (iap_event_sb_sbx_ib_ibx_ok_on_counter(ev, ri) == 0) return (EINVAL); break; case PMC_CPU_INTEL_WESTMERE: case PMC_CPU_INTEL_WESTMERE_EX: if (iap_event_westmere_ok_on_counter(ev, ri) == 0) return (EINVAL); break; default: if (iap_event_ok_on_counter(ev, ri) == 0) return (EINVAL); } /* * Look for an event descriptor with matching CPU and event id * fields. */ switch (core_cputype) { default: case PMC_CPU_INTEL_ATOM: cpuflag = IAP_F_CA; break; case PMC_CPU_INTEL_ATOM_SILVERMONT: cpuflag = IAP_F_CAS; break; case PMC_CPU_INTEL_BROADWELL: cpuflag = IAP_F_BW; break; case PMC_CPU_INTEL_CORE: cpuflag = IAP_F_CC; break; case PMC_CPU_INTEL_CORE2: cpuflag = IAP_F_CC2; break; case PMC_CPU_INTEL_CORE2EXTREME: cpuflag = IAP_F_CC2 | IAP_F_CC2E; break; case PMC_CPU_INTEL_COREI7: cpuflag = IAP_F_I7; break; case PMC_CPU_INTEL_HASWELL: cpuflag = IAP_F_HW; break; case PMC_CPU_INTEL_HASWELL_XEON: cpuflag = IAP_F_HWX; break; case PMC_CPU_INTEL_IVYBRIDGE: cpuflag = IAP_F_IB; break; case PMC_CPU_INTEL_IVYBRIDGE_XEON: cpuflag = IAP_F_IBX; break; case PMC_CPU_INTEL_SANDYBRIDGE: cpuflag = IAP_F_SB; break; case PMC_CPU_INTEL_SANDYBRIDGE_XEON: cpuflag = IAP_F_SBX; break; case PMC_CPU_INTEL_WESTMERE: cpuflag = IAP_F_WM; break; } for (n = 0, ie = iap_events; n < niap_events; n++, ie++) if (ie->iap_ev == ev && ie->iap_flags & cpuflag) break; if (n == niap_events) return (EINVAL); /* * A matching event descriptor has been found, so start * assembling the contents of the event select register. */ evsel = ie->iap_evcode; config = a->pm_md.pm_iap.pm_iap_config & ~IAP_F_CMASK; /* * If the event uses a fixed umask value, reject any umask * bits set by the user. */ if (ie->iap_flags & IAP_F_FM) { if (IAP_UMASK(config) != 0) return (EINVAL); evsel |= (ie->iap_umask << 8); } else { /* * Otherwise, the UMASK value needs to be taken from * the MD fields of the allocation request. Reject * requests that specify reserved bits. */ mask = 0; if (ie->iap_umask & IAP_M_CORE) { if ((c = (config & IAP_F_CORE)) != IAP_CORE_ALL && c != IAP_CORE_THIS) return (EINVAL); mask |= IAP_F_CORE; } if (ie->iap_umask & IAP_M_AGENT) mask |= IAP_F_AGENT; if (ie->iap_umask & IAP_M_PREFETCH) { if ((c = (config & IAP_F_PREFETCH)) == IAP_PREFETCH_RESERVED) return (EINVAL); mask |= IAP_F_PREFETCH; } if (ie->iap_umask & IAP_M_MESI) mask |= IAP_F_MESI; if (ie->iap_umask & IAP_M_SNOOPRESPONSE) mask |= IAP_F_SNOOPRESPONSE; if (ie->iap_umask & IAP_M_SNOOPTYPE) mask |= IAP_F_SNOOPTYPE; if (ie->iap_umask & IAP_M_TRANSITION) mask |= IAP_F_TRANSITION; /* * If bits outside of the allowed set of umask bits * are set, reject the request. */ if (config & ~mask) return (EINVAL); evsel |= (config & mask); } /* * Only Atom and SandyBridge CPUs support the 'ANY' qualifier. */ if (core_cputype == PMC_CPU_INTEL_ATOM || core_cputype == PMC_CPU_INTEL_ATOM_SILVERMONT || core_cputype == PMC_CPU_INTEL_SANDYBRIDGE || core_cputype == PMC_CPU_INTEL_SANDYBRIDGE_XEON) evsel |= (config & IAP_ANY); else if (config & IAP_ANY) return (EINVAL); /* * Check offcore response configuration. */ if (a->pm_md.pm_iap.pm_iap_rsp != 0) { if (ev != PMC_EV_IAP_EVENT_B7H_01H && ev != PMC_EV_IAP_EVENT_BBH_01H) return (EINVAL); if (core_cputype == PMC_CPU_INTEL_COREI7 && ev == PMC_EV_IAP_EVENT_BBH_01H) return (EINVAL); if ((core_cputype == PMC_CPU_INTEL_COREI7 || core_cputype == PMC_CPU_INTEL_WESTMERE || core_cputype == PMC_CPU_INTEL_NEHALEM_EX || core_cputype == PMC_CPU_INTEL_WESTMERE_EX) && a->pm_md.pm_iap.pm_iap_rsp & ~IA_OFFCORE_RSP_MASK_I7WM) return (EINVAL); else if ((core_cputype == PMC_CPU_INTEL_SANDYBRIDGE || core_cputype == PMC_CPU_INTEL_SANDYBRIDGE_XEON || core_cputype == PMC_CPU_INTEL_IVYBRIDGE || core_cputype == PMC_CPU_INTEL_IVYBRIDGE_XEON) && a->pm_md.pm_iap.pm_iap_rsp & ~IA_OFFCORE_RSP_MASK_SBIB) return (EINVAL); pm->pm_md.pm_iap.pm_iap_rsp = a->pm_md.pm_iap.pm_iap_rsp; } if (caps & PMC_CAP_THRESHOLD) evsel |= (a->pm_md.pm_iap.pm_iap_config & IAP_F_CMASK); if (caps & PMC_CAP_USER) evsel |= IAP_USR; if (caps & PMC_CAP_SYSTEM) evsel |= IAP_OS; if ((caps & (PMC_CAP_USER | PMC_CAP_SYSTEM)) == 0) evsel |= (IAP_OS | IAP_USR); if (caps & PMC_CAP_EDGE) evsel |= IAP_EDGE; if (caps & PMC_CAP_INVERT) evsel |= IAP_INV; if (caps & PMC_CAP_INTERRUPT) evsel |= IAP_INT; pm->pm_md.pm_iap.pm_iap_evsel = evsel; return (0); } static int iap_config_pmc(int cpu, int ri, struct pmc *pm) { KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), ("[core,%d] illegal CPU %d", __LINE__, cpu)); KASSERT(ri >= 0 && ri < core_iap_npmc, ("[core,%d] illegal row-index %d", __LINE__, ri)); PMCDBG3(MDP,CFG,1, "iap-config cpu=%d ri=%d pm=%p", cpu, ri, pm); KASSERT(core_pcpu[cpu] != NULL, ("[core,%d] null per-cpu %d", __LINE__, cpu)); core_pcpu[cpu]->pc_corepmcs[ri].phw_pmc = pm; return (0); } static int iap_describe(int cpu, int ri, struct pmc_info *pi, struct pmc **ppmc) { int error; struct pmc_hw *phw; char iap_name[PMC_NAME_MAX]; phw = &core_pcpu[cpu]->pc_corepmcs[ri]; (void) snprintf(iap_name, sizeof(iap_name), "IAP-%d", ri); if ((error = copystr(iap_name, pi->pm_name, PMC_NAME_MAX, NULL)) != 0) return (error); pi->pm_class = PMC_CLASS_IAP; if (phw->phw_state & PMC_PHW_FLAG_IS_ENABLED) { pi->pm_enabled = TRUE; *ppmc = phw->phw_pmc; } else { pi->pm_enabled = FALSE; *ppmc = NULL; } return (0); } static int iap_get_config(int cpu, int ri, struct pmc **ppm) { *ppm = core_pcpu[cpu]->pc_corepmcs[ri].phw_pmc; return (0); } static int iap_get_msr(int ri, uint32_t *msr) { KASSERT(ri >= 0 && ri < core_iap_npmc, ("[iap,%d] ri %d out of range", __LINE__, ri)); *msr = ri; return (0); } static int iap_read_pmc(int cpu, int ri, pmc_value_t *v) { struct pmc *pm; pmc_value_t tmp; KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), ("[core,%d] illegal cpu value %d", __LINE__, cpu)); KASSERT(ri >= 0 && ri < core_iap_npmc, ("[core,%d] illegal row-index %d", __LINE__, ri)); pm = core_pcpu[cpu]->pc_corepmcs[ri].phw_pmc; KASSERT(pm, ("[core,%d] cpu %d ri %d pmc not configured", __LINE__, cpu, ri)); tmp = rdpmc(ri); if (PMC_IS_SAMPLING_MODE(PMC_TO_MODE(pm))) *v = iap_perfctr_value_to_reload_count(tmp); else *v = tmp & ((1ULL << core_iap_width) - 1); PMCDBG4(MDP,REA,1, "iap-read cpu=%d ri=%d msr=0x%x -> v=%jx", cpu, ri, ri, *v); return (0); } static int iap_release_pmc(int cpu, int ri, struct pmc *pm) { (void) pm; PMCDBG3(MDP,REL,1, "iap-release cpu=%d ri=%d pm=%p", cpu, ri, pm); KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), ("[core,%d] illegal CPU value %d", __LINE__, cpu)); KASSERT(ri >= 0 && ri < core_iap_npmc, ("[core,%d] illegal row-index %d", __LINE__, ri)); KASSERT(core_pcpu[cpu]->pc_corepmcs[ri].phw_pmc == NULL, ("[core,%d] PHW pmc non-NULL", __LINE__)); return (0); } static int iap_start_pmc(int cpu, int ri) { struct pmc *pm; uint32_t evsel; struct core_cpu *cc; KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), ("[core,%d] illegal CPU value %d", __LINE__, cpu)); KASSERT(ri >= 0 && ri < core_iap_npmc, ("[core,%d] illegal row-index %d", __LINE__, ri)); cc = core_pcpu[cpu]; pm = cc->pc_corepmcs[ri].phw_pmc; KASSERT(pm, ("[core,%d] starting cpu%d,ri%d with no pmc configured", __LINE__, cpu, ri)); PMCDBG2(MDP,STA,1, "iap-start cpu=%d ri=%d", cpu, ri); evsel = pm->pm_md.pm_iap.pm_iap_evsel; PMCDBG4(MDP,STA,2, "iap-start/2 cpu=%d ri=%d evselmsr=0x%x evsel=0x%x", cpu, ri, IAP_EVSEL0 + ri, evsel); /* Event specific configuration. */ switch (pm->pm_event) { case PMC_EV_IAP_EVENT_B7H_01H: wrmsr(IA_OFFCORE_RSP0, pm->pm_md.pm_iap.pm_iap_rsp); break; case PMC_EV_IAP_EVENT_BBH_01H: wrmsr(IA_OFFCORE_RSP1, pm->pm_md.pm_iap.pm_iap_rsp); break; default: break; } wrmsr(IAP_EVSEL0 + ri, evsel | IAP_EN); if (core_cputype == PMC_CPU_INTEL_CORE) return (0); do { cc->pc_resync = 0; cc->pc_globalctrl |= (1ULL << ri); wrmsr(IA_GLOBAL_CTRL, cc->pc_globalctrl); } while (cc->pc_resync != 0); return (0); } static int iap_stop_pmc(int cpu, int ri) { struct pmc *pm; struct core_cpu *cc; uint64_t msr; KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), ("[core,%d] illegal cpu value %d", __LINE__, cpu)); KASSERT(ri >= 0 && ri < core_iap_npmc, ("[core,%d] illegal row index %d", __LINE__, ri)); cc = core_pcpu[cpu]; pm = cc->pc_corepmcs[ri].phw_pmc; KASSERT(pm, ("[core,%d] cpu%d ri%d no configured PMC to stop", __LINE__, cpu, ri)); PMCDBG2(MDP,STO,1, "iap-stop cpu=%d ri=%d", cpu, ri); msr = rdmsr(IAP_EVSEL0 + ri) & ~IAP_EVSEL_MASK; wrmsr(IAP_EVSEL0 + ri, msr); /* stop hw */ if (core_cputype == PMC_CPU_INTEL_CORE) return (0); msr = 0; do { cc->pc_resync = 0; cc->pc_globalctrl &= ~(1ULL << ri); msr = rdmsr(IA_GLOBAL_CTRL) & ~IA_GLOBAL_CTRL_MASK; wrmsr(IA_GLOBAL_CTRL, cc->pc_globalctrl); } while (cc->pc_resync != 0); return (0); } static int iap_write_pmc(int cpu, int ri, pmc_value_t v) { struct pmc *pm; struct core_cpu *cc; KASSERT(cpu >= 0 && cpu < pmc_cpu_max(), ("[core,%d] illegal cpu value %d", __LINE__, cpu)); KASSERT(ri >= 0 && ri < core_iap_npmc, ("[core,%d] illegal row index %d", __LINE__, ri)); cc = core_pcpu[cpu]; pm = cc->pc_corepmcs[ri].phw_pmc; KASSERT(pm, ("[core,%d] cpu%d ri%d no configured PMC to stop", __LINE__, cpu, ri)); PMCDBG4(MDP,WRI,1, "iap-write cpu=%d ri=%d msr=0x%x v=%jx", cpu, ri, IAP_PMC0 + ri, v); if (PMC_IS_SAMPLING_MODE(PMC_TO_MODE(pm))) v = iap_reload_count_to_perfctr_value(v); /* * Write the new value to the counter. The counter will be in * a stopped state when the pcd_write() entry point is called. */ wrmsr(IAP_PMC0 + ri, v & ((1ULL << core_iap_width) - 1)); return (0); } static void iap_initialize(struct pmc_mdep *md, int maxcpu, int npmc, int pmcwidth, int flags) { struct pmc_classdep *pcd; KASSERT(md != NULL, ("[iap,%d] md is NULL", __LINE__)); PMCDBG0(MDP,INI,1, "iap-initialize"); /* Remember the set of architectural events supported. */ core_architectural_events = ~flags; pcd = &md->pmd_classdep[PMC_MDEP_CLASS_INDEX_IAP]; pcd->pcd_caps = IAP_PMC_CAPS; pcd->pcd_class = PMC_CLASS_IAP; pcd->pcd_num = npmc; pcd->pcd_ri = md->pmd_npmc; pcd->pcd_width = pmcwidth; pcd->pcd_allocate_pmc = iap_allocate_pmc; pcd->pcd_config_pmc = iap_config_pmc; pcd->pcd_describe = iap_describe; pcd->pcd_get_config = iap_get_config; pcd->pcd_get_msr = iap_get_msr; pcd->pcd_pcpu_fini = core_pcpu_fini; pcd->pcd_pcpu_init = core_pcpu_init; pcd->pcd_read_pmc = iap_read_pmc; pcd->pcd_release_pmc = iap_release_pmc; pcd->pcd_start_pmc = iap_start_pmc; pcd->pcd_stop_pmc = iap_stop_pmc; pcd->pcd_write_pmc = iap_write_pmc; md->pmd_npmc += npmc; } static int core_intr(int cpu, struct trapframe *tf) { pmc_value_t v; struct pmc *pm; struct core_cpu *cc; int error, found_interrupt, ri; uint64_t msr; PMCDBG3(MDP,INT, 1, "cpu=%d tf=0x%p um=%d", cpu, (void *) tf, TRAPF_USERMODE(tf)); found_interrupt = 0; cc = core_pcpu[cpu]; for (ri = 0; ri < core_iap_npmc; ri++) { if ((pm = cc->pc_corepmcs[ri].phw_pmc) == NULL || !PMC_IS_SAMPLING_MODE(PMC_TO_MODE(pm))) continue; if (!iap_pmc_has_overflowed(ri)) continue; found_interrupt = 1; if (pm->pm_state != PMC_STATE_RUNNING) continue; error = pmc_process_interrupt(cpu, PMC_HR, pm, tf, TRAPF_USERMODE(tf)); v = pm->pm_sc.pm_reloadcount; v = iap_reload_count_to_perfctr_value(v); /* * Stop the counter, reload it but only restart it if * the PMC is not stalled. */ msr = rdmsr(IAP_EVSEL0 + ri) & ~IAP_EVSEL_MASK; wrmsr(IAP_EVSEL0 + ri, msr); wrmsr(IAP_PMC0 + ri, v); if (error) continue; wrmsr(IAP_EVSEL0 + ri, msr | (pm->pm_md.pm_iap.pm_iap_evsel | IAP_EN)); } if (found_interrupt) lapic_reenable_pmc(); atomic_add_int(found_interrupt ? &pmc_stats.pm_intr_processed : &pmc_stats.pm_intr_ignored, 1); return (found_interrupt); } static int core2_intr(int cpu, struct trapframe *tf) { int error, found_interrupt, n; uint64_t flag, intrstatus, intrenable, msr; struct pmc *pm; struct core_cpu *cc; pmc_value_t v; PMCDBG3(MDP,INT, 1, "cpu=%d tf=0x%p um=%d", cpu, (void *) tf, TRAPF_USERMODE(tf)); /* * The IA_GLOBAL_STATUS (MSR 0x38E) register indicates which * PMCs have a pending PMI interrupt. We take a 'snapshot' of * the current set of interrupting PMCs and process these * after stopping them. */ intrstatus = rdmsr(IA_GLOBAL_STATUS); intrenable = intrstatus & core_pmcmask; PMCDBG2(MDP,INT, 1, "cpu=%d intrstatus=%jx", cpu, (uintmax_t) intrstatus); found_interrupt = 0; cc = core_pcpu[cpu]; KASSERT(cc != NULL, ("[core,%d] null pcpu", __LINE__)); cc->pc_globalctrl &= ~intrenable; cc->pc_resync = 1; /* MSRs now potentially out of sync. */ /* * Stop PMCs and clear overflow status bits. */ msr = rdmsr(IA_GLOBAL_CTRL) & ~IA_GLOBAL_CTRL_MASK; wrmsr(IA_GLOBAL_CTRL, msr); wrmsr(IA_GLOBAL_OVF_CTRL, intrenable | IA_GLOBAL_STATUS_FLAG_OVFBUF | IA_GLOBAL_STATUS_FLAG_CONDCHG); /* * Look for interrupts from fixed function PMCs. */ for (n = 0, flag = (1ULL << IAF_OFFSET); n < core_iaf_npmc; n++, flag <<= 1) { if ((intrstatus & flag) == 0) continue; found_interrupt = 1; pm = cc->pc_corepmcs[n + core_iaf_ri].phw_pmc; if (pm == NULL || pm->pm_state != PMC_STATE_RUNNING || !PMC_IS_SAMPLING_MODE(PMC_TO_MODE(pm))) continue; error = pmc_process_interrupt(cpu, PMC_HR, pm, tf, TRAPF_USERMODE(tf)); if (error) intrenable &= ~flag; v = iaf_reload_count_to_perfctr_value(pm->pm_sc.pm_reloadcount); /* Reload sampling count. */ wrmsr(IAF_CTR0 + n, v); PMCDBG4(MDP,INT, 1, "iaf-intr cpu=%d error=%d v=%jx(%jx)", cpu, error, (uintmax_t) v, (uintmax_t) rdpmc(IAF_RI_TO_MSR(n))); } /* * Process interrupts from the programmable counters. */ for (n = 0, flag = 1; n < core_iap_npmc; n++, flag <<= 1) { if ((intrstatus & flag) == 0) continue; found_interrupt = 1; pm = cc->pc_corepmcs[n].phw_pmc; if (pm == NULL || pm->pm_state != PMC_STATE_RUNNING || !PMC_IS_SAMPLING_MODE(PMC_TO_MODE(pm))) continue; error = pmc_process_interrupt(cpu, PMC_HR, pm, tf, TRAPF_USERMODE(tf)); if (error) intrenable &= ~flag; v = iap_reload_count_to_perfctr_value(pm->pm_sc.pm_reloadcount); PMCDBG3(MDP,INT, 1, "iap-intr cpu=%d error=%d v=%jx", cpu, error, (uintmax_t) v); /* Reload sampling count. */ wrmsr(IAP_PMC0 + n, v); } /* * Reenable all non-stalled PMCs. */ PMCDBG2(MDP,INT, 1, "cpu=%d intrenable=%jx", cpu, (uintmax_t) intrenable); cc->pc_globalctrl |= intrenable; wrmsr(IA_GLOBAL_CTRL, cc->pc_globalctrl & IA_GLOBAL_CTRL_MASK); PMCDBG5(MDP,INT, 1, "cpu=%d fixedctrl=%jx globalctrl=%jx status=%jx " "ovf=%jx", cpu, (uintmax_t) rdmsr(IAF_CTRL), (uintmax_t) rdmsr(IA_GLOBAL_CTRL), (uintmax_t) rdmsr(IA_GLOBAL_STATUS), (uintmax_t) rdmsr(IA_GLOBAL_OVF_CTRL)); if (found_interrupt) lapic_reenable_pmc(); atomic_add_int(found_interrupt ? &pmc_stats.pm_intr_processed : &pmc_stats.pm_intr_ignored, 1); return (found_interrupt); } int pmc_core_initialize(struct pmc_mdep *md, int maxcpu, int version_override) { int cpuid[CORE_CPUID_REQUEST_SIZE]; int ipa_version, flags, nflags; do_cpuid(CORE_CPUID_REQUEST, cpuid); ipa_version = (version_override > 0) ? version_override : cpuid[CORE_CPUID_EAX] & 0xFF; core_cputype = md->pmd_cputype; PMCDBG3(MDP,INI,1,"core-init cputype=%d ncpu=%d ipa-version=%d", core_cputype, maxcpu, ipa_version); if (ipa_version < 1 || ipa_version > 3 || (core_cputype != PMC_CPU_INTEL_CORE && ipa_version == 1)) { /* Unknown PMC architecture. */ printf("hwpc_core: unknown PMC architecture: %d\n", ipa_version); return (EPROGMISMATCH); } core_pmcmask = 0; /* * Initialize programmable counters. */ core_iap_npmc = (cpuid[CORE_CPUID_EAX] >> 8) & 0xFF; core_iap_width = (cpuid[CORE_CPUID_EAX] >> 16) & 0xFF; core_pmcmask |= ((1ULL << core_iap_npmc) - 1); nflags = (cpuid[CORE_CPUID_EAX] >> 24) & 0xFF; flags = cpuid[CORE_CPUID_EBX] & ((1 << nflags) - 1); iap_initialize(md, maxcpu, core_iap_npmc, core_iap_width, flags); /* * Initialize fixed function counters, if present. */ if (core_cputype != PMC_CPU_INTEL_CORE) { core_iaf_ri = core_iap_npmc; core_iaf_npmc = cpuid[CORE_CPUID_EDX] & 0x1F; core_iaf_width = (cpuid[CORE_CPUID_EDX] >> 5) & 0xFF; iaf_initialize(md, maxcpu, core_iaf_npmc, core_iaf_width); core_pmcmask |= ((1ULL << core_iaf_npmc) - 1) << IAF_OFFSET; } PMCDBG2(MDP,INI,1,"core-init pmcmask=0x%jx iafri=%d", core_pmcmask, core_iaf_ri); core_pcpu = malloc(sizeof(struct core_cpu **) * maxcpu, M_PMC, M_ZERO | M_WAITOK); /* * Choose the appropriate interrupt handler. */ if (ipa_version == 1) md->pmd_intr = core_intr; else md->pmd_intr = core2_intr; md->pmd_pcpu_fini = NULL; md->pmd_pcpu_init = NULL; return (0); } void pmc_core_finalize(struct pmc_mdep *md) { PMCDBG0(MDP,INI,1, "core-finalize"); free(core_pcpu, M_PMC); core_pcpu = NULL; } Index: stable/10/sys/dev/hwpmc/pmc_events.h =================================================================== --- stable/10/sys/dev/hwpmc/pmc_events.h (revision 320105) +++ stable/10/sys/dev/hwpmc/pmc_events.h (revision 320106) @@ -1,5270 +1,5272 @@ /*- * Copyright (c) 2005 Joseph Koshy * All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. * * $FreeBSD$ */ #ifndef _DEV_HWPMC_PMC_EVENTS_H_ #define _DEV_HWPMC_PMC_EVENTS_H_ /* * Note: Documentation on adding events can be found both in * the source tree at src/share/doc/papers/hwpmc/hwpmc.ms * as well as on-line at: * * http://wiki.freebsd.org/PmcTools/PmcHardwareHowTo * * Please refer to those resources before you attempt to modify * this file or the hwpmc driver/subsystem. */ /* * PMC event codes. * * __PMC_EV(CLASS, SYMBOLIC-NAME) * */ /* * AMD K7 Events, from "The AMD Athlon(tm) Processor x86 Code * Optimization Guide" [Doc#22007K, Feb 2002] */ #define __PMC_EV_K7() \ __PMC_EV(K7, DC_ACCESSES) \ __PMC_EV(K7, DC_MISSES) \ __PMC_EV(K7, DC_REFILLS_FROM_L2) \ __PMC_EV(K7, DC_REFILLS_FROM_SYSTEM) \ __PMC_EV(K7, DC_WRITEBACKS) \ __PMC_EV(K7, L1_DTLB_MISS_AND_L2_DTLB_HITS) \ __PMC_EV(K7, L1_AND_L2_DTLB_MISSES) \ __PMC_EV(K7, MISALIGNED_REFERENCES) \ __PMC_EV(K7, IC_FETCHES) \ __PMC_EV(K7, IC_MISSES) \ __PMC_EV(K7, L1_ITLB_MISSES) \ __PMC_EV(K7, L1_L2_ITLB_MISSES) \ __PMC_EV(K7, RETIRED_INSTRUCTIONS) \ __PMC_EV(K7, RETIRED_OPS) \ __PMC_EV(K7, RETIRED_BRANCHES) \ __PMC_EV(K7, RETIRED_BRANCHES_MISPREDICTED) \ __PMC_EV(K7, RETIRED_TAKEN_BRANCHES) \ __PMC_EV(K7, RETIRED_TAKEN_BRANCHES_MISPREDICTED) \ __PMC_EV(K7, RETIRED_FAR_CONTROL_TRANSFERS) \ __PMC_EV(K7, RETIRED_RESYNC_BRANCHES) \ __PMC_EV(K7, INTERRUPTS_MASKED_CYCLES) \ __PMC_EV(K7, INTERRUPTS_MASKED_WHILE_PENDING_CYCLES) \ __PMC_EV(K7, HARDWARE_INTERRUPTS) #define PMC_EV_K7_FIRST PMC_EV_K7_DC_ACCESSES #define PMC_EV_K7_LAST PMC_EV_K7_HARDWARE_INTERRUPTS /* * Intel P4 Events, from "IA-32 Intel(r) Architecture Software * Developer's Manual, Volume 3: System Programming Guide" [245472-012] */ #define __PMC_EV_P4() \ __PMC_EV(P4, TC_DELIVER_MODE) \ __PMC_EV(P4, BPU_FETCH_REQUEST) \ __PMC_EV(P4, ITLB_REFERENCE) \ __PMC_EV(P4, MEMORY_CANCEL) \ __PMC_EV(P4, MEMORY_COMPLETE) \ __PMC_EV(P4, LOAD_PORT_REPLAY) \ __PMC_EV(P4, STORE_PORT_REPLAY) \ __PMC_EV(P4, MOB_LOAD_REPLAY) \ __PMC_EV(P4, PAGE_WALK_TYPE) \ __PMC_EV(P4, BSQ_CACHE_REFERENCE) \ __PMC_EV(P4, IOQ_ALLOCATION) \ __PMC_EV(P4, IOQ_ACTIVE_ENTRIES) \ __PMC_EV(P4, FSB_DATA_ACTIVITY) \ __PMC_EV(P4, BSQ_ALLOCATION) \ __PMC_EV(P4, BSQ_ACTIVE_ENTRIES) \ __PMC_EV(P4, SSE_INPUT_ASSIST) \ __PMC_EV(P4, PACKED_SP_UOP) \ __PMC_EV(P4, PACKED_DP_UOP) \ __PMC_EV(P4, SCALAR_SP_UOP) \ __PMC_EV(P4, SCALAR_DP_UOP) \ __PMC_EV(P4, 64BIT_MMX_UOP) \ __PMC_EV(P4, 128BIT_MMX_UOP) \ __PMC_EV(P4, X87_FP_UOP) \ __PMC_EV(P4, X87_SIMD_MOVES_UOP) \ __PMC_EV(P4, GLOBAL_POWER_EVENTS) \ __PMC_EV(P4, TC_MS_XFER) \ __PMC_EV(P4, UOP_QUEUE_WRITES) \ __PMC_EV(P4, RETIRED_MISPRED_BRANCH_TYPE) \ __PMC_EV(P4, RETIRED_BRANCH_TYPE) \ __PMC_EV(P4, RESOURCE_STALL) \ __PMC_EV(P4, WC_BUFFER) \ __PMC_EV(P4, B2B_CYCLES) \ __PMC_EV(P4, BNR) \ __PMC_EV(P4, SNOOP) \ __PMC_EV(P4, RESPONSE) \ __PMC_EV(P4, FRONT_END_EVENT) \ __PMC_EV(P4, EXECUTION_EVENT) \ __PMC_EV(P4, REPLAY_EVENT) \ __PMC_EV(P4, INSTR_RETIRED) \ __PMC_EV(P4, UOPS_RETIRED) \ __PMC_EV(P4, UOP_TYPE) \ __PMC_EV(P4, BRANCH_RETIRED) \ __PMC_EV(P4, MISPRED_BRANCH_RETIRED) \ __PMC_EV(P4, X87_ASSIST) \ __PMC_EV(P4, MACHINE_CLEAR) #define PMC_EV_P4_FIRST PMC_EV_P4_TC_DELIVER_MODE #define PMC_EV_P4_LAST PMC_EV_P4_MACHINE_CLEAR /* Intel Pentium Pro, P-II, P-III and Pentium-M style events */ #define __PMC_EV_P6() \ __PMC_EV(P6, DATA_MEM_REFS) \ __PMC_EV(P6, DCU_LINES_IN) \ __PMC_EV(P6, DCU_M_LINES_IN) \ __PMC_EV(P6, DCU_M_LINES_OUT) \ __PMC_EV(P6, DCU_MISS_OUTSTANDING) \ __PMC_EV(P6, IFU_FETCH) \ __PMC_EV(P6, IFU_FETCH_MISS) \ __PMC_EV(P6, ITLB_MISS) \ __PMC_EV(P6, IFU_MEM_STALL) \ __PMC_EV(P6, ILD_STALL) \ __PMC_EV(P6, L2_IFETCH) \ __PMC_EV(P6, L2_LD) \ __PMC_EV(P6, L2_ST) \ __PMC_EV(P6, L2_LINES_IN) \ __PMC_EV(P6, L2_LINES_OUT) \ __PMC_EV(P6, L2_M_LINES_INM) \ __PMC_EV(P6, L2_M_LINES_OUTM) \ __PMC_EV(P6, L2_RQSTS) \ __PMC_EV(P6, L2_ADS) \ __PMC_EV(P6, L2_DBUS_BUSY) \ __PMC_EV(P6, L2_DBUS_BUSY_RD) \ __PMC_EV(P6, BUS_DRDY_CLOCKS) \ __PMC_EV(P6, BUS_LOCK_CLOCKS) \ __PMC_EV(P6, BUS_REQ_OUTSTANDING) \ __PMC_EV(P6, BUS_TRAN_BRD) \ __PMC_EV(P6, BUS_TRAN_RFO) \ __PMC_EV(P6, BUS_TRANS_WB) \ __PMC_EV(P6, BUS_TRAN_IFETCH) \ __PMC_EV(P6, BUS_TRAN_INVAL) \ __PMC_EV(P6, BUS_TRAN_PWR) \ __PMC_EV(P6, BUS_TRANS_P) \ __PMC_EV(P6, BUS_TRANS_IO) \ __PMC_EV(P6, BUS_TRAN_DEF) \ __PMC_EV(P6, BUS_TRAN_BURST) \ __PMC_EV(P6, BUS_TRAN_ANY) \ __PMC_EV(P6, BUS_TRAN_MEM) \ __PMC_EV(P6, BUS_DATA_RCV) \ __PMC_EV(P6, BUS_BNR_DRV) \ __PMC_EV(P6, BUS_HIT_DRV) \ __PMC_EV(P6, BUS_HITM_DRV) \ __PMC_EV(P6, BUS_SNOOP_STALL) \ __PMC_EV(P6, FLOPS) \ __PMC_EV(P6, FP_COMPS_OPS_EXE) \ __PMC_EV(P6, FP_ASSIST) \ __PMC_EV(P6, MUL) \ __PMC_EV(P6, DIV) \ __PMC_EV(P6, CYCLES_DIV_BUSY) \ __PMC_EV(P6, LD_BLOCKS) \ __PMC_EV(P6, SB_DRAINS) \ __PMC_EV(P6, MISALIGN_MEM_REF) \ __PMC_EV(P6, EMON_KNI_PREF_DISPATCHED) \ __PMC_EV(P6, EMON_KNI_PREF_MISS) \ __PMC_EV(P6, INST_RETIRED) \ __PMC_EV(P6, UOPS_RETIRED) \ __PMC_EV(P6, INST_DECODED) \ __PMC_EV(P6, EMON_KNI_INST_RETIRED) \ __PMC_EV(P6, EMON_KNI_COMP_INST_RET) \ __PMC_EV(P6, HW_INT_RX) \ __PMC_EV(P6, CYCLES_INT_MASKED) \ __PMC_EV(P6, CYCLES_INT_PENDING_AND_MASKED) \ __PMC_EV(P6, BR_INST_RETIRED) \ __PMC_EV(P6, BR_MISS_PRED_RETIRED) \ __PMC_EV(P6, BR_TAKEN_RETIRED) \ __PMC_EV(P6, BR_MISS_PRED_TAKEN_RET) \ __PMC_EV(P6, BR_INST_DECODED) \ __PMC_EV(P6, BTB_MISSES) \ __PMC_EV(P6, BR_BOGUS) \ __PMC_EV(P6, BACLEARS) \ __PMC_EV(P6, RESOURCE_STALLS) \ __PMC_EV(P6, PARTIAL_RAT_STALLS) \ __PMC_EV(P6, SEGMENT_REG_LOADS) \ __PMC_EV(P6, CPU_CLK_UNHALTED) \ __PMC_EV(P6, MMX_INSTR_EXEC) \ __PMC_EV(P6, MMX_SAT_INSTR_EXEC) \ __PMC_EV(P6, MMX_UOPS_EXEC) \ __PMC_EV(P6, MMX_INSTR_TYPE_EXEC) \ __PMC_EV(P6, FP_MMX_TRANS) \ __PMC_EV(P6, MMX_ASSIST) \ __PMC_EV(P6, MMX_INSTR_RET) \ __PMC_EV(P6, SEG_RENAME_STALLS) \ __PMC_EV(P6, SEG_REG_RENAMES) \ __PMC_EV(P6, RET_SEG_RENAMES) \ __PMC_EV(P6, EMON_EST_TRANS) \ __PMC_EV(P6, EMON_THERMAL_TRIP) \ __PMC_EV(P6, BR_INST_EXEC) \ __PMC_EV(P6, BR_MISSP_EXEC) \ __PMC_EV(P6, BR_BAC_MISSP_EXEC) \ __PMC_EV(P6, BR_CND_EXEC) \ __PMC_EV(P6, BR_CND_MISSP_EXEC) \ __PMC_EV(P6, BR_IND_EXEC) \ __PMC_EV(P6, BR_IND_MISSP_EXEC) \ __PMC_EV(P6, BR_RET_EXEC) \ __PMC_EV(P6, BR_RET_MISSP_EXEC) \ __PMC_EV(P6, BR_RET_BAC_MISSP_EXEC) \ __PMC_EV(P6, BR_CALL_EXEC) \ __PMC_EV(P6, BR_CALL_MISSP_EXEC) \ __PMC_EV(P6, BR_IND_CALL_EXEC) \ __PMC_EV(P6, EMON_SIMD_INSTR_RETIRED) \ __PMC_EV(P6, EMON_SYNCH_UOPS) \ __PMC_EV(P6, EMON_ESP_UOPS) \ __PMC_EV(P6, EMON_FUSED_UOPS_RET) \ __PMC_EV(P6, EMON_UNFUSION) \ __PMC_EV(P6, EMON_PREF_RQSTS_UP) \ __PMC_EV(P6, EMON_PREF_RQSTS_DN) \ __PMC_EV(P6, EMON_SSE_SSE2_INST_RETIRED) \ __PMC_EV(P6, EMON_SSE_SSE2_COMP_INST_RETIRED) #define PMC_EV_P6_FIRST PMC_EV_P6_DATA_MEM_REFS #define PMC_EV_P6_LAST PMC_EV_P6_EMON_SSE_SSE2_COMP_INST_RETIRED /* AMD K8 PMCs */ #define __PMC_EV_K8() \ __PMC_EV(K8, FP_DISPATCHED_FPU_OPS) \ __PMC_EV(K8, FP_CYCLES_WITH_NO_FPU_OPS_RETIRED) \ __PMC_EV(K8, FP_DISPATCHED_FPU_FAST_FLAG_OPS) \ __PMC_EV(K8, LS_SEGMENT_REGISTER_LOAD) \ __PMC_EV(K8, LS_MICROARCHITECTURAL_RESYNC_BY_SELF_MODIFYING_CODE) \ __PMC_EV(K8, LS_MICROARCHITECTURAL_RESYNC_BY_SNOOP) \ __PMC_EV(K8, LS_BUFFER2_FULL) \ __PMC_EV(K8, LS_LOCKED_OPERATION) \ __PMC_EV(K8, LS_MICROARCHITECTURAL_LATE_CANCEL) \ __PMC_EV(K8, LS_RETIRED_CFLUSH_INSTRUCTIONS) \ __PMC_EV(K8, LS_RETIRED_CPUID_INSTRUCTIONS) \ __PMC_EV(K8, DC_ACCESS) \ __PMC_EV(K8, DC_MISS) \ __PMC_EV(K8, DC_REFILL_FROM_L2) \ __PMC_EV(K8, DC_REFILL_FROM_SYSTEM) \ __PMC_EV(K8, DC_COPYBACK) \ __PMC_EV(K8, DC_L1_DTLB_MISS_AND_L2_DTLB_HIT) \ __PMC_EV(K8, DC_L1_DTLB_MISS_AND_L2_DTLB_MISS) \ __PMC_EV(K8, DC_MISALIGNED_DATA_REFERENCE) \ __PMC_EV(K8, DC_MICROARCHITECTURAL_LATE_CANCEL) \ __PMC_EV(K8, DC_MICROARCHITECTURAL_EARLY_CANCEL) \ __PMC_EV(K8, DC_ONE_BIT_ECC_ERROR) \ __PMC_EV(K8, DC_DISPATCHED_PREFETCH_INSTRUCTIONS) \ __PMC_EV(K8, DC_DCACHE_ACCESSES_BY_LOCKS) \ __PMC_EV(K8, BU_CPU_CLK_UNHALTED) \ __PMC_EV(K8, BU_INTERNAL_L2_REQUEST) \ __PMC_EV(K8, BU_FILL_REQUEST_L2_MISS) \ __PMC_EV(K8, BU_FILL_INTO_L2) \ __PMC_EV(K8, IC_FETCH) \ __PMC_EV(K8, IC_MISS) \ __PMC_EV(K8, IC_REFILL_FROM_L2) \ __PMC_EV(K8, IC_REFILL_FROM_SYSTEM) \ __PMC_EV(K8, IC_L1_ITLB_MISS_AND_L2_ITLB_HIT) \ __PMC_EV(K8, IC_L1_ITLB_MISS_AND_L2_ITLB_MISS) \ __PMC_EV(K8, IC_MICROARCHITECTURAL_RESYNC_BY_SNOOP) \ __PMC_EV(K8, IC_INSTRUCTION_FETCH_STALL) \ __PMC_EV(K8, IC_RETURN_STACK_HIT) \ __PMC_EV(K8, IC_RETURN_STACK_OVERFLOW) \ __PMC_EV(K8, FR_RETIRED_X86_INSTRUCTIONS) \ __PMC_EV(K8, FR_RETIRED_UOPS) \ __PMC_EV(K8, FR_RETIRED_BRANCHES) \ __PMC_EV(K8, FR_RETIRED_BRANCHES_MISPREDICTED) \ __PMC_EV(K8, FR_RETIRED_TAKEN_BRANCHES) \ __PMC_EV(K8, FR_RETIRED_TAKEN_BRANCHES_MISPREDICTED) \ __PMC_EV(K8, FR_RETIRED_FAR_CONTROL_TRANSFERS) \ __PMC_EV(K8, FR_RETIRED_RESYNCS) \ __PMC_EV(K8, FR_RETIRED_NEAR_RETURNS) \ __PMC_EV(K8, FR_RETIRED_NEAR_RETURNS_MISPREDICTED) \ __PMC_EV(K8, FR_RETIRED_TAKEN_BRANCHES_MISPREDICTED_BY_ADDR_MISCOMPARE) \ __PMC_EV(K8, FR_RETIRED_FPU_INSTRUCTIONS) \ __PMC_EV(K8, FR_RETIRED_FASTPATH_DOUBLE_OP_INSTRUCTIONS) \ __PMC_EV(K8, FR_INTERRUPTS_MASKED_CYCLES) \ __PMC_EV(K8, FR_INTERRUPTS_MASKED_WHILE_PENDING_CYCLES) \ __PMC_EV(K8, FR_TAKEN_HARDWARE_INTERRUPTS) \ __PMC_EV(K8, FR_DECODER_EMPTY) \ __PMC_EV(K8, FR_DISPATCH_STALLS) \ __PMC_EV(K8, FR_DISPATCH_STALL_FROM_BRANCH_ABORT_TO_RETIRE) \ __PMC_EV(K8, FR_DISPATCH_STALL_FOR_SERIALIZATION) \ __PMC_EV(K8, FR_DISPATCH_STALL_FOR_SEGMENT_LOAD) \ __PMC_EV(K8, FR_DISPATCH_STALL_WHEN_REORDER_BUFFER_IS_FULL) \ __PMC_EV(K8, FR_DISPATCH_STALL_WHEN_RESERVATION_STATIONS_ARE_FULL) \ __PMC_EV(K8, FR_DISPATCH_STALL_WHEN_FPU_IS_FULL) \ __PMC_EV(K8, FR_DISPATCH_STALL_WHEN_LS_IS_FULL) \ __PMC_EV(K8, FR_DISPATCH_STALL_WHEN_WAITING_FOR_ALL_TO_BE_QUIET) \ __PMC_EV(K8, FR_DISPATCH_STALL_WHEN_FAR_XFER_OR_RESYNC_BRANCH_PENDING) \ __PMC_EV(K8, FR_FPU_EXCEPTIONS) \ __PMC_EV(K8, FR_NUMBER_OF_BREAKPOINTS_FOR_DR0) \ __PMC_EV(K8, FR_NUMBER_OF_BREAKPOINTS_FOR_DR1) \ __PMC_EV(K8, FR_NUMBER_OF_BREAKPOINTS_FOR_DR2) \ __PMC_EV(K8, FR_NUMBER_OF_BREAKPOINTS_FOR_DR3) \ __PMC_EV(K8, NB_MEMORY_CONTROLLER_PAGE_ACCESS_EVENT) \ __PMC_EV(K8, NB_MEMORY_CONTROLLER_PAGE_TABLE_OVERFLOW) \ __PMC_EV(K8, NB_MEMORY_CONTROLLER_DRAM_COMMAND_SLOTS_MISSED) \ __PMC_EV(K8, NB_MEMORY_CONTROLLER_TURNAROUND) \ __PMC_EV(K8, NB_MEMORY_CONTROLLER_BYPASS_SATURATION) \ __PMC_EV(K8, NB_SIZED_COMMANDS) \ __PMC_EV(K8, NB_PROBE_RESULT) \ __PMC_EV(K8, NB_HT_BUS0_BANDWIDTH) \ __PMC_EV(K8, NB_HT_BUS1_BANDWIDTH) \ __PMC_EV(K8, NB_HT_BUS2_BANDWIDTH) #define PMC_EV_K8_FIRST PMC_EV_K8_FP_DISPATCHED_FPU_OPS #define PMC_EV_K8_LAST PMC_EV_K8_NB_HT_BUS2_BANDWIDTH /* * Intel Pentium and Pentium MMX events, from the "Intel 64 and IA-32 * Architectures Software Developer's Manual, Volume 3B: System Programming * Guide, Part 2, August 2007". */ #define __PMC_EV_P5() \ __PMC_EV(P5, DATA_READ) \ __PMC_EV(P5, DATA_WRITE) \ __PMC_EV(P5, DATA_TLB_MISS) \ __PMC_EV(P5, DATA_READ_MISS) \ __PMC_EV(P5, DATA_WRITE_MISS) \ __PMC_EV(P5, WRITE_HIT_TO_M_OR_E_STATE_LINES) \ __PMC_EV(P5, DATA_CACHE_LINES_WRITTEN_BACK) \ __PMC_EV(P5, EXTERNAL_SNOOPS) \ __PMC_EV(P5, EXTERNAL_DATA_CACHE_SNOOP_HITS) \ __PMC_EV(P5, MEMORY_ACCESSES_IN_BOTH_PIPES) \ __PMC_EV(P5, BANK_CONFLICTS) \ __PMC_EV(P5, MISALIGNED_DATA_OR_IO_REFERENCES) \ __PMC_EV(P5, CODE_READ) \ __PMC_EV(P5, CODE_TLB_MISS) \ __PMC_EV(P5, CODE_CACHE_MISS) \ __PMC_EV(P5, ANY_SEGMENT_REGISTER_LOADED) \ __PMC_EV(P5, BRANCHES) \ __PMC_EV(P5, BTB_HITS) \ __PMC_EV(P5, TAKEN_BRANCH_OR_BTB_HIT) \ __PMC_EV(P5, PIPELINE_FLUSHES) \ __PMC_EV(P5, INSTRUCTIONS_EXECUTED) \ __PMC_EV(P5, INSTRUCTIONS_EXECUTED_V_PIPE) \ __PMC_EV(P5, BUS_CYCLE_DURATION) \ __PMC_EV(P5, WRITE_BUFFER_FULL_STALL_DURATION) \ __PMC_EV(P5, WAITING_FOR_DATA_MEMORY_READ_STALL_DURATION) \ __PMC_EV(P5, STALL_ON_WRITE_TO_AN_E_OR_M_STATE_LINE) \ __PMC_EV(P5, LOCKED_BUS_CYCLE) \ __PMC_EV(P5, IO_READ_OR_WRITE_CYCLE) \ __PMC_EV(P5, NONCACHEABLE_MEMORY_READS) \ __PMC_EV(P5, PIPELINE_AGI_STALLS) \ __PMC_EV(P5, FLOPS) \ __PMC_EV(P5, BREAKPOINT_MATCH_ON_DR0_REGISTER) \ __PMC_EV(P5, BREAKPOINT_MATCH_ON_DR1_REGISTER) \ __PMC_EV(P5, BREAKPOINT_MATCH_ON_DR2_REGISTER) \ __PMC_EV(P5, BREAKPOINT_MATCH_ON_DR3_REGISTER) \ __PMC_EV(P5, HARDWARE_INTERRUPTS) \ __PMC_EV(P5, DATA_READ_OR_WRITE) \ __PMC_EV(P5, DATA_READ_MISS_OR_WRITE_MISS) \ __PMC_EV(P5, BUS_OWNERSHIP_LATENCY) \ __PMC_EV(P5, BUS_OWNERSHIP_TRANSFERS) \ __PMC_EV(P5, MMX_INSTRUCTIONS_EXECUTED_U_PIPE) \ __PMC_EV(P5, MMX_INSTRUCTIONS_EXECUTED_V_PIPE) \ __PMC_EV(P5, CACHE_M_LINE_SHARING) \ __PMC_EV(P5, CACHE_LINE_SHARING) \ __PMC_EV(P5, EMMS_INSTRUCTIONS_EXECUTED) \ __PMC_EV(P5, TRANSITIONS_BETWEEN_MMX_AND_FP_INSTRUCTIONS) \ __PMC_EV(P5, BUS_UTILIZATION_DUE_TO_PROCESSOR_ACTIVITY) \ __PMC_EV(P5, WRITES_TO_NONCACHEABLE_MEMORY) \ __PMC_EV(P5, SATURATING_MMX_INSTRUCTIONS_EXECUTED) \ __PMC_EV(P5, SATURATIONS_PERFORMED) \ __PMC_EV(P5, NUMBER_OF_CYCLES_NOT_IN_HALT_STATE) \ __PMC_EV(P5, DATA_CACHE_TLB_MISS_STALL_DURATION) \ __PMC_EV(P5, MMX_INSTRUCTION_DATA_READS) \ __PMC_EV(P5, MMX_INSTRUCTION_DATA_READ_MISSES) \ __PMC_EV(P5, FLOATING_POINT_STALLS_DURATION) \ __PMC_EV(P5, TAKEN_BRANCHES) \ __PMC_EV(P5, D1_STARVATION_AND_FIFO_IS_EMPTY) \ __PMC_EV(P5, D1_STARVATION_AND_ONLY_ONE_INSTRUCTION_IN_FIFO) \ __PMC_EV(P5, MMX_INSTRUCTION_DATA_WRITES) \ __PMC_EV(P5, MMX_INSTRUCTION_DATA_WRITE_MISSES) \ __PMC_EV(P5, PIPELINE_FLUSHES_DUE_TO_WRONG_BRANCH_PREDICTIONS) \ __PMC_EV(P5, \ PIPELINE_FLUSHES_DUE_TO_WRONG_BRANCH_PREDICTIONS_RESOLVED_IN_WB_STAGE) \ __PMC_EV(P5, MISALIGNED_DATA_MEMORY_REFERENCE_ON_MMX_INSTRUCTIONS) \ __PMC_EV(P5, PIPELINE_STALL_FOR_MMX_INSTRUCTION_DATA_MEMORY_READS) \ __PMC_EV(P5, MISPREDICTED_OR_UNPREDICTED_RETURNS) \ __PMC_EV(P5, PREDICTED_RETURNS) \ __PMC_EV(P5, MMX_MULTIPLY_UNIT_INTERLOCK) \ __PMC_EV(P5, MOVD_MOVQ_STORE_STALL_DUE_TO_PREVIOUS_MMX_OPERATION) \ __PMC_EV(P5, RETURNS) \ __PMC_EV(P5, BTB_FALSE_ENTRIES) \ __PMC_EV(P5, BTB_MISS_PREDICTION_ON_NOT_TAKEN_BRANCH) \ __PMC_EV(P5, \ FULL_WRITE_BUFFER_STALL_DURATION_WHILE_EXECUTING_MMX_INSTRUCTIONS) \ __PMC_EV(P5, STALL_ON_MMX_INSTRUCTION_WRITE_TO_E_OR_M_STATE_LINE) #define PMC_EV_P5_FIRST PMC_EV_P5_DATA_READ #define PMC_EV_P5_LAST \ PMC_EV_P5_STALL_ON_MMX_INSTRUCTION_WRITE_TO_E_OR_M_STATE_LINE /* * Events supported by Intel architectural fixed function counters, * from the "Intel 64 and IA-32 Architectures Software Developer's * Manual Volume 3B: System Programming Guide, Part 2", July 2008. */ #define __PMC_EV_IAF() \ __PMC_EV(IAF, INSTR_RETIRED_ANY) \ __PMC_EV(IAF, CPU_CLK_UNHALTED_CORE) \ __PMC_EV(IAF, CPU_CLK_UNHALTED_REF) #define PMC_EV_IAF_FIRST PMC_EV_IAF_INSTR_RETIRED_ANY #define PMC_EV_IAF_LAST PMC_EV_IAF_CPU_CLK_UNHALTED_REF #define __PMC_EV_ALIAS_IAF() \ __PMC_EV_ALIAS("instruction-retired", IAF_INSTR_RETIRED_ANY) \ __PMC_EV_ALIAS("unhalted-core-cycles", IAF_CPU_CLK_UNHALTED_CORE) \ __PMC_EV_ALIAS("unhalted-reference-cycles", IAF_CPU_CLK_UNHALTED_REF) /* * Events supported by programmable function counters present in * Intel Atom, Core and Core2 CPUs, from the "Intel 64 and IA-32 * Architectures Software Developer's Manual Volume 3B: System Programming * Guide, Part 2", July 2008. * * These PMCs select events with a combination of an event code and * unit mask. Quirks that need to be taken care of include: * - The set of (event code, umask) combinations supported by a processor * varies according to the processor model. * - A given (event code, umask) combination need not measure the same * hardware event in all processor models. * - Event names in vendor documentation for an (event code, umask) pair * may vary according to the CPU model. * - Identically named events can map to different (event code, umask) * pairs on different CPUs. * - New (event code, umask) combinations continue to be added as CPUs * evolve. The interface between hwpmc(4) and libpmc(3) needs to be * robust with respect to ABI changes. * * The IAP_EVENT_* symbols below define the ABI between userland and kernel. * New (event code, * umask) combinations used in new CPUs would be added * to the end of the list. Vendor names for events are mapped to IAP_EVENT_* * symbols using aliases. The final disambiguation of semantics based on * the CPU model happens inside hwpmc(4). */ #define __PMC_EV_IAP() \ __PMC_EV(IAP, ARCH_BR_INS_RET) \ __PMC_EV(IAP, ARCH_BR_MIS_RET) \ __PMC_EV(IAP, ARCH_INS_RET) \ __PMC_EV(IAP, ARCH_LLC_MIS) \ __PMC_EV(IAP, ARCH_LLC_REF) \ __PMC_EV(IAP, ARCH_UNH_REF_CYC) \ __PMC_EV(IAP, ARCH_UNH_COR_CYC) \ __PMC_EV(IAP, EVENT_02H_01H) \ __PMC_EV(IAP, EVENT_02H_81H) \ __PMC_EV(IAP, EVENT_03H_00H) \ __PMC_EV(IAP, EVENT_03H_01H) \ __PMC_EV(IAP, EVENT_03H_02H) \ __PMC_EV(IAP, EVENT_03H_04H) \ __PMC_EV(IAP, EVENT_03H_08H) \ __PMC_EV(IAP, EVENT_03H_10H) \ __PMC_EV(IAP, EVENT_03H_20H) \ __PMC_EV(IAP, EVENT_03H_40H) \ __PMC_EV(IAP, EVENT_03H_80H) \ __PMC_EV(IAP, EVENT_04H_00H) \ __PMC_EV(IAP, EVENT_04H_01H) \ __PMC_EV(IAP, EVENT_04H_02H) \ __PMC_EV(IAP, EVENT_04H_04H) \ __PMC_EV(IAP, EVENT_04H_07H) \ __PMC_EV(IAP, EVENT_04H_08H) \ __PMC_EV(IAP, EVENT_04H_10H) \ __PMC_EV(IAP, EVENT_04H_20H) \ __PMC_EV(IAP, EVENT_04H_40H) \ __PMC_EV(IAP, EVENT_04H_80H) \ __PMC_EV(IAP, EVENT_05H_00H) \ __PMC_EV(IAP, EVENT_05H_01H) \ __PMC_EV(IAP, EVENT_05H_02H) \ __PMC_EV(IAP, EVENT_05H_03H) \ __PMC_EV(IAP, EVENT_06H_00H) \ __PMC_EV(IAP, EVENT_06H_01H) \ __PMC_EV(IAP, EVENT_06H_02H) \ __PMC_EV(IAP, EVENT_06H_04H) \ __PMC_EV(IAP, EVENT_06H_08H) \ __PMC_EV(IAP, EVENT_06H_0FH) \ __PMC_EV(IAP, EVENT_07H_00H) \ __PMC_EV(IAP, EVENT_07H_01H) \ __PMC_EV(IAP, EVENT_07H_02H) \ __PMC_EV(IAP, EVENT_07H_03H) \ __PMC_EV(IAP, EVENT_07H_06H) \ __PMC_EV(IAP, EVENT_07H_08H) \ __PMC_EV(IAP, EVENT_08H_01H) \ __PMC_EV(IAP, EVENT_08H_02H) \ __PMC_EV(IAP, EVENT_08H_04H) \ __PMC_EV(IAP, EVENT_08H_05H) \ __PMC_EV(IAP, EVENT_08H_06H) \ __PMC_EV(IAP, EVENT_08H_07H) \ __PMC_EV(IAP, EVENT_08H_08H) \ __PMC_EV(IAP, EVENT_08H_09H) \ __PMC_EV(IAP, EVENT_08H_0EH) \ __PMC_EV(IAP, EVENT_08H_10H) \ __PMC_EV(IAP, EVENT_08H_20H) \ __PMC_EV(IAP, EVENT_08H_40H) \ __PMC_EV(IAP, EVENT_08H_60H) \ __PMC_EV(IAP, EVENT_08H_80H) \ __PMC_EV(IAP, EVENT_08H_81H) \ __PMC_EV(IAP, EVENT_08H_82H) \ __PMC_EV(IAP, EVENT_08H_84H) \ __PMC_EV(IAP, EVENT_08H_88H) \ __PMC_EV(IAP, EVENT_09H_01H) \ __PMC_EV(IAP, EVENT_09H_02H) \ __PMC_EV(IAP, EVENT_09H_04H) \ __PMC_EV(IAP, EVENT_09H_08H) \ __PMC_EV(IAP, EVENT_0BH_01H) \ __PMC_EV(IAP, EVENT_0BH_02H) \ __PMC_EV(IAP, EVENT_0BH_10H) \ __PMC_EV(IAP, EVENT_0CH_01H) \ __PMC_EV(IAP, EVENT_0CH_02H) \ __PMC_EV(IAP, EVENT_0CH_03H) \ __PMC_EV(IAP, EVENT_0DH_03H) \ __PMC_EV(IAP, EVENT_0DH_40H) \ __PMC_EV(IAP, EVENT_0EH_01H) \ __PMC_EV(IAP, EVENT_0EH_02H) \ __PMC_EV(IAP, EVENT_0EH_10H) \ __PMC_EV(IAP, EVENT_0EH_20H) \ __PMC_EV(IAP, EVENT_0EH_40H) \ __PMC_EV(IAP, EVENT_0FH_01H) \ __PMC_EV(IAP, EVENT_0FH_02H) \ __PMC_EV(IAP, EVENT_0FH_08H) \ __PMC_EV(IAP, EVENT_0FH_10H) \ __PMC_EV(IAP, EVENT_0FH_20H) \ __PMC_EV(IAP, EVENT_0FH_80H) \ __PMC_EV(IAP, EVENT_10H_00H) \ __PMC_EV(IAP, EVENT_10H_01H) \ __PMC_EV(IAP, EVENT_10H_02H) \ __PMC_EV(IAP, EVENT_10H_04H) \ __PMC_EV(IAP, EVENT_10H_08H) \ __PMC_EV(IAP, EVENT_10H_10H) \ __PMC_EV(IAP, EVENT_10H_20H) \ __PMC_EV(IAP, EVENT_10H_40H) \ __PMC_EV(IAP, EVENT_10H_80H) \ __PMC_EV(IAP, EVENT_10H_81H) \ __PMC_EV(IAP, EVENT_11H_00H) \ __PMC_EV(IAP, EVENT_11H_01H) \ __PMC_EV(IAP, EVENT_11H_02H) \ __PMC_EV(IAP, EVENT_11H_81H) \ __PMC_EV(IAP, EVENT_12H_00H) \ __PMC_EV(IAP, EVENT_12H_01H) \ __PMC_EV(IAP, EVENT_12H_02H) \ __PMC_EV(IAP, EVENT_12H_04H) \ __PMC_EV(IAP, EVENT_12H_08H) \ __PMC_EV(IAP, EVENT_12H_10H) \ __PMC_EV(IAP, EVENT_12H_20H) \ __PMC_EV(IAP, EVENT_12H_40H) \ __PMC_EV(IAP, EVENT_12H_81H) \ __PMC_EV(IAP, EVENT_13H_00H) \ __PMC_EV(IAP, EVENT_13H_01H) \ __PMC_EV(IAP, EVENT_13H_02H) \ __PMC_EV(IAP, EVENT_13H_04H) \ __PMC_EV(IAP, EVENT_13H_07H) \ __PMC_EV(IAP, EVENT_13H_81H) \ __PMC_EV(IAP, EVENT_14H_00H) \ __PMC_EV(IAP, EVENT_14H_01H) \ __PMC_EV(IAP, EVENT_14H_02H) \ __PMC_EV(IAP, EVENT_17H_01H) \ __PMC_EV(IAP, EVENT_18H_00H) \ __PMC_EV(IAP, EVENT_18H_01H) \ __PMC_EV(IAP, EVENT_19H_00H) \ __PMC_EV(IAP, EVENT_19H_01H) \ __PMC_EV(IAP, EVENT_19H_02H) \ __PMC_EV(IAP, EVENT_1DH_01H) \ __PMC_EV(IAP, EVENT_1DH_02H) \ __PMC_EV(IAP, EVENT_1DH_04H) \ __PMC_EV(IAP, EVENT_1EH_01H) \ __PMC_EV(IAP, EVENT_20H_01H) \ __PMC_EV(IAP, EVENT_21H) \ __PMC_EV(IAP, EVENT_22H) \ __PMC_EV(IAP, EVENT_22H_01H) \ __PMC_EV(IAP, EVENT_22H_02H) \ __PMC_EV(IAP, EVENT_22H_04H) \ __PMC_EV(IAP, EVENT_22H_08H) \ __PMC_EV(IAP, EVENT_22H_10H) \ __PMC_EV(IAP, EVENT_22H_20H) \ __PMC_EV(IAP, EVENT_22H_40H) \ __PMC_EV(IAP, EVENT_22H_80H) \ __PMC_EV(IAP, EVENT_23H) \ __PMC_EV(IAP, EVENT_24H) \ __PMC_EV(IAP, EVENT_24H_01H) \ __PMC_EV(IAP, EVENT_24H_02H) \ __PMC_EV(IAP, EVENT_24H_03H) \ __PMC_EV(IAP, EVENT_24H_04H) \ __PMC_EV(IAP, EVENT_24H_08H) \ __PMC_EV(IAP, EVENT_24H_0CH) \ __PMC_EV(IAP, EVENT_24H_10H) \ __PMC_EV(IAP, EVENT_24H_20H) \ __PMC_EV(IAP, EVENT_24H_21H) \ __PMC_EV(IAP, EVENT_24H_22H) \ __PMC_EV(IAP, EVENT_24H_24H) \ __PMC_EV(IAP, EVENT_24H_27H) \ __PMC_EV(IAP, EVENT_24H_30H) \ __PMC_EV(IAP, EVENT_24H_40H) \ __PMC_EV(IAP, EVENT_24H_41H) \ __PMC_EV(IAP, EVENT_24H_42H) \ __PMC_EV(IAP, EVENT_24H_44H) \ __PMC_EV(IAP, EVENT_24H_50H) \ __PMC_EV(IAP, EVENT_24H_80H) \ __PMC_EV(IAP, EVENT_24H_AAH) \ __PMC_EV(IAP, EVENT_24H_3FH) \ __PMC_EV(IAP, EVENT_24H_BFH) \ __PMC_EV(IAP, EVENT_24H_C0H) \ __PMC_EV(IAP, EVENT_24H_E1H) \ __PMC_EV(IAP, EVENT_24H_E2H) \ __PMC_EV(IAP, EVENT_24H_E4H) \ __PMC_EV(IAP, EVENT_24H_E7H) \ __PMC_EV(IAP, EVENT_24H_F8H) \ __PMC_EV(IAP, EVENT_24H_FFH) \ __PMC_EV(IAP, EVENT_25H) \ __PMC_EV(IAP, EVENT_26H) \ __PMC_EV(IAP, EVENT_26H_01H) \ __PMC_EV(IAP, EVENT_26H_02H) \ __PMC_EV(IAP, EVENT_26H_04H) \ __PMC_EV(IAP, EVENT_26H_08H) \ __PMC_EV(IAP, EVENT_26H_0FH) \ __PMC_EV(IAP, EVENT_26H_10H) \ __PMC_EV(IAP, EVENT_26H_20H) \ __PMC_EV(IAP, EVENT_26H_40H) \ __PMC_EV(IAP, EVENT_26H_80H) \ __PMC_EV(IAP, EVENT_26H_F0H) \ __PMC_EV(IAP, EVENT_26H_FFH) \ __PMC_EV(IAP, EVENT_27H) \ __PMC_EV(IAP, EVENT_27H_01H) \ __PMC_EV(IAP, EVENT_27H_02H) \ __PMC_EV(IAP, EVENT_27H_04H) \ __PMC_EV(IAP, EVENT_27H_08H) \ __PMC_EV(IAP, EVENT_27H_0EH) \ __PMC_EV(IAP, EVENT_27H_0FH) \ __PMC_EV(IAP, EVENT_27H_10H) \ __PMC_EV(IAP, EVENT_27H_20H) \ __PMC_EV(IAP, EVENT_27H_40H) \ __PMC_EV(IAP, EVENT_27H_50H) \ __PMC_EV(IAP, EVENT_27H_80H) \ __PMC_EV(IAP, EVENT_27H_E0H) \ __PMC_EV(IAP, EVENT_27H_F0H) \ __PMC_EV(IAP, EVENT_28H) \ __PMC_EV(IAP, EVENT_28H_01H) \ __PMC_EV(IAP, EVENT_28H_02H) \ __PMC_EV(IAP, EVENT_28H_04H) \ __PMC_EV(IAP, EVENT_28H_08H) \ __PMC_EV(IAP, EVENT_28H_0FH) \ __PMC_EV(IAP, EVENT_29H) \ __PMC_EV(IAP, EVENT_2AH) \ __PMC_EV(IAP, EVENT_2BH) \ __PMC_EV(IAP, EVENT_2EH) \ __PMC_EV(IAP, EVENT_2EH_01H) \ __PMC_EV(IAP, EVENT_2EH_02H) \ __PMC_EV(IAP, EVENT_2EH_41H) \ __PMC_EV(IAP, EVENT_2EH_4FH) \ __PMC_EV(IAP, EVENT_30H) \ __PMC_EV(IAP, EVENT_30H_00H) \ __PMC_EV(IAP, EVENT_31H_00H) \ __PMC_EV(IAP, EVENT_32H) \ __PMC_EV(IAP, EVENT_3AH) \ __PMC_EV(IAP, EVENT_3AH_00H) \ __PMC_EV(IAP, EVENT_3BH_C0H) \ __PMC_EV(IAP, EVENT_3CH_00H) \ __PMC_EV(IAP, EVENT_3CH_01H) \ __PMC_EV(IAP, EVENT_3CH_02H) \ __PMC_EV(IAP, EVENT_3DH_01H) \ __PMC_EV(IAP, EVENT_40H) \ __PMC_EV(IAP, EVENT_40H_01H) \ __PMC_EV(IAP, EVENT_40H_02H) \ __PMC_EV(IAP, EVENT_40H_04H) \ __PMC_EV(IAP, EVENT_40H_08H) \ __PMC_EV(IAP, EVENT_40H_0FH) \ __PMC_EV(IAP, EVENT_40H_21H) \ __PMC_EV(IAP, EVENT_41H) \ __PMC_EV(IAP, EVENT_41H_01H) \ __PMC_EV(IAP, EVENT_41H_02H) \ __PMC_EV(IAP, EVENT_41H_04H) \ __PMC_EV(IAP, EVENT_41H_08H) \ __PMC_EV(IAP, EVENT_41H_0FH) \ __PMC_EV(IAP, EVENT_41H_22H) \ __PMC_EV(IAP, EVENT_42H) \ __PMC_EV(IAP, EVENT_42H_01H) \ __PMC_EV(IAP, EVENT_42H_02H) \ __PMC_EV(IAP, EVENT_42H_04H) \ __PMC_EV(IAP, EVENT_42H_08H) \ __PMC_EV(IAP, EVENT_42H_10H) \ __PMC_EV(IAP, EVENT_43H_01H) \ __PMC_EV(IAP, EVENT_43H_02H) \ __PMC_EV(IAP, EVENT_44H_02H) \ __PMC_EV(IAP, EVENT_45H_0FH) \ __PMC_EV(IAP, EVENT_46H_00H) \ __PMC_EV(IAP, EVENT_47H_00H) \ __PMC_EV(IAP, EVENT_48H_00H) \ __PMC_EV(IAP, EVENT_48H_01H) \ __PMC_EV(IAP, EVENT_48H_02H) \ __PMC_EV(IAP, EVENT_49H_00H) \ __PMC_EV(IAP, EVENT_49H_0EH) \ __PMC_EV(IAP, EVENT_49H_01H) \ __PMC_EV(IAP, EVENT_49H_02H) \ __PMC_EV(IAP, EVENT_49H_04H) \ __PMC_EV(IAP, EVENT_49H_10H) \ __PMC_EV(IAP, EVENT_49H_20H) \ __PMC_EV(IAP, EVENT_49H_40H) \ __PMC_EV(IAP, EVENT_49H_60H) \ __PMC_EV(IAP, EVENT_49H_80H) \ __PMC_EV(IAP, EVENT_4BH_00H) \ __PMC_EV(IAP, EVENT_4BH_01H) \ __PMC_EV(IAP, EVENT_4BH_02H) \ __PMC_EV(IAP, EVENT_4BH_03H) \ __PMC_EV(IAP, EVENT_4BH_08H) \ __PMC_EV(IAP, EVENT_4CH_00H) \ __PMC_EV(IAP, EVENT_4CH_01H) \ __PMC_EV(IAP, EVENT_4CH_02H) \ __PMC_EV(IAP, EVENT_4DH_01H) \ __PMC_EV(IAP, EVENT_4EH_01H) \ __PMC_EV(IAP, EVENT_4EH_02H) \ __PMC_EV(IAP, EVENT_4EH_04H) \ __PMC_EV(IAP, EVENT_4EH_10H) \ __PMC_EV(IAP, EVENT_4FH_00H) \ __PMC_EV(IAP, EVENT_4FH_02H) \ __PMC_EV(IAP, EVENT_4FH_04H) \ __PMC_EV(IAP, EVENT_4FH_08H) \ __PMC_EV(IAP, EVENT_4FH_10H) \ __PMC_EV(IAP, EVENT_51H_01H) \ __PMC_EV(IAP, EVENT_51H_02H) \ __PMC_EV(IAP, EVENT_51H_04H) \ __PMC_EV(IAP, EVENT_51H_08H) \ __PMC_EV(IAP, EVENT_52H_01H) \ __PMC_EV(IAP, EVENT_53H_01H) \ __PMC_EV(IAP, EVENT_58H_01H) \ __PMC_EV(IAP, EVENT_58H_02H) \ __PMC_EV(IAP, EVENT_58H_04H) \ __PMC_EV(IAP, EVENT_58H_08H) \ __PMC_EV(IAP, EVENT_59H_20H) \ __PMC_EV(IAP, EVENT_59H_40H) \ __PMC_EV(IAP, EVENT_59H_80H) \ __PMC_EV(IAP, EVENT_5BH_0CH) \ __PMC_EV(IAP, EVENT_5BH_0FH) \ __PMC_EV(IAP, EVENT_5BH_40H) \ __PMC_EV(IAP, EVENT_5BH_4FH) \ __PMC_EV(IAP, EVENT_5CH_01H) \ __PMC_EV(IAP, EVENT_5CH_02H) \ __PMC_EV(IAP, EVENT_5EH_01H) \ __PMC_EV(IAP, EVENT_5FH_01H) \ __PMC_EV(IAP, EVENT_5FH_04H) \ __PMC_EV(IAP, EVENT_60H) \ __PMC_EV(IAP, EVENT_60H_01H) \ __PMC_EV(IAP, EVENT_60H_02H) \ __PMC_EV(IAP, EVENT_60H_04H) \ __PMC_EV(IAP, EVENT_60H_08H) \ __PMC_EV(IAP, EVENT_61H) \ __PMC_EV(IAP, EVENT_61H_00H) \ __PMC_EV(IAP, EVENT_62H) \ __PMC_EV(IAP, EVENT_62H_00H) \ __PMC_EV(IAP, EVENT_63H) \ __PMC_EV(IAP, EVENT_63H_01H) \ __PMC_EV(IAP, EVENT_63H_02H) \ __PMC_EV(IAP, EVENT_64H) \ __PMC_EV(IAP, EVENT_64H_40H) \ __PMC_EV(IAP, EVENT_65H) \ __PMC_EV(IAP, EVENT_66H) \ __PMC_EV(IAP, EVENT_67H) \ __PMC_EV(IAP, EVENT_68H) \ __PMC_EV(IAP, EVENT_69H) \ __PMC_EV(IAP, EVENT_6AH) \ __PMC_EV(IAP, EVENT_6BH) \ __PMC_EV(IAP, EVENT_6CH) \ __PMC_EV(IAP, EVENT_6CH_01H) \ __PMC_EV(IAP, EVENT_6DH) \ __PMC_EV(IAP, EVENT_6EH) \ __PMC_EV(IAP, EVENT_6FH) \ __PMC_EV(IAP, EVENT_70H) \ __PMC_EV(IAP, EVENT_77H) \ __PMC_EV(IAP, EVENT_78H) \ __PMC_EV(IAP, EVENT_79H_02H) \ __PMC_EV(IAP, EVENT_79H_04H) \ __PMC_EV(IAP, EVENT_79H_08H) \ __PMC_EV(IAP, EVENT_79H_10H) \ __PMC_EV(IAP, EVENT_79H_20H) \ __PMC_EV(IAP, EVENT_79H_30H) \ __PMC_EV(IAP, EVENT_79H_18H) \ __PMC_EV(IAP, EVENT_79H_24H) \ __PMC_EV(IAP, EVENT_79H_3CH) \ __PMC_EV(IAP, EVENT_7AH) \ __PMC_EV(IAP, EVENT_7BH) \ __PMC_EV(IAP, EVENT_7DH) \ __PMC_EV(IAP, EVENT_7EH) \ __PMC_EV(IAP, EVENT_7EH_00H) \ __PMC_EV(IAP, EVENT_7FH) \ __PMC_EV(IAP, EVENT_80H_00H) \ __PMC_EV(IAP, EVENT_80H_01H) \ __PMC_EV(IAP, EVENT_80H_02H) \ __PMC_EV(IAP, EVENT_80H_03H) \ __PMC_EV(IAP, EVENT_80H_04H) \ __PMC_EV(IAP, EVENT_80H_10H) \ __PMC_EV(IAP, EVENT_81H_00H) \ __PMC_EV(IAP, EVENT_81H_01H) \ __PMC_EV(IAP, EVENT_81H_02H) \ __PMC_EV(IAP, EVENT_82H_01H) \ __PMC_EV(IAP, EVENT_82H_02H) \ __PMC_EV(IAP, EVENT_82H_04H) \ __PMC_EV(IAP, EVENT_82H_10H) \ __PMC_EV(IAP, EVENT_82H_12H) \ __PMC_EV(IAP, EVENT_82H_40H) \ __PMC_EV(IAP, EVENT_83H_01H) \ __PMC_EV(IAP, EVENT_83H_02H) \ __PMC_EV(IAP, EVENT_85H_00H) \ __PMC_EV(IAP, EVENT_85H_01H) \ __PMC_EV(IAP, EVENT_85H_02H) \ __PMC_EV(IAP, EVENT_85H_04H) \ __PMC_EV(IAP, EVENT_85H_0EH) \ __PMC_EV(IAP, EVENT_85H_10H) \ __PMC_EV(IAP, EVENT_85H_20H) \ __PMC_EV(IAP, EVENT_85H_40H) \ __PMC_EV(IAP, EVENT_85H_60H) \ __PMC_EV(IAP, EVENT_85H_80H) \ __PMC_EV(IAP, EVENT_86H_00H) \ __PMC_EV(IAP, EVENT_87H_00H) \ __PMC_EV(IAP, EVENT_87H_01H) \ __PMC_EV(IAP, EVENT_87H_02H) \ __PMC_EV(IAP, EVENT_87H_04H) \ __PMC_EV(IAP, EVENT_87H_08H) \ __PMC_EV(IAP, EVENT_87H_0FH) \ __PMC_EV(IAP, EVENT_88H_00H) \ __PMC_EV(IAP, EVENT_88H_01H) \ __PMC_EV(IAP, EVENT_88H_02H) \ __PMC_EV(IAP, EVENT_88H_04H) \ __PMC_EV(IAP, EVENT_88H_07H) \ __PMC_EV(IAP, EVENT_88H_08H) \ __PMC_EV(IAP, EVENT_88H_10H) \ __PMC_EV(IAP, EVENT_88H_20H) \ __PMC_EV(IAP, EVENT_88H_30H) \ __PMC_EV(IAP, EVENT_88H_40H) \ +__PMC_EV(IAP, EVENT_88H_41H) \ __PMC_EV(IAP, EVENT_88H_80H) \ +__PMC_EV(IAP, EVENT_88H_81H) \ +__PMC_EV(IAP, EVENT_88H_82H) \ +__PMC_EV(IAP, EVENT_88H_84H) \ +__PMC_EV(IAP, EVENT_88H_88H) \ +__PMC_EV(IAP, EVENT_88H_90H) \ +__PMC_EV(IAP, EVENT_88H_A0H) \ __PMC_EV(IAP, EVENT_88H_7FH) \ __PMC_EV(IAP, EVENT_88H_FFH) \ __PMC_EV(IAP, EVENT_89H_00H) \ __PMC_EV(IAP, EVENT_89H_01H) \ __PMC_EV(IAP, EVENT_89H_02H) \ __PMC_EV(IAP, EVENT_89H_04H) \ __PMC_EV(IAP, EVENT_89H_07H) \ __PMC_EV(IAP, EVENT_89H_08H) \ __PMC_EV(IAP, EVENT_89H_10H) \ __PMC_EV(IAP, EVENT_89H_20H) \ __PMC_EV(IAP, EVENT_89H_30H) \ __PMC_EV(IAP, EVENT_89H_40H) \ +__PMC_EV(IAP, EVENT_89H_41H) \ __PMC_EV(IAP, EVENT_89H_80H) \ +__PMC_EV(IAP, EVENT_89H_81H) \ +__PMC_EV(IAP, EVENT_89H_82H) \ +__PMC_EV(IAP, EVENT_89H_84H) \ +__PMC_EV(IAP, EVENT_89H_88H) \ +__PMC_EV(IAP, EVENT_89H_90H) \ +__PMC_EV(IAP, EVENT_89H_A0H) \ __PMC_EV(IAP, EVENT_89H_7FH) \ __PMC_EV(IAP, EVENT_89H_FFH) \ __PMC_EV(IAP, EVENT_8AH_00H) \ __PMC_EV(IAP, EVENT_8BH_00H) \ __PMC_EV(IAP, EVENT_8CH_00H) \ __PMC_EV(IAP, EVENT_8DH_00H) \ __PMC_EV(IAP, EVENT_8EH_00H) \ __PMC_EV(IAP, EVENT_8FH_00H) \ __PMC_EV(IAP, EVENT_90H_00H) \ __PMC_EV(IAP, EVENT_91H_00H) \ __PMC_EV(IAP, EVENT_92H_00H) \ __PMC_EV(IAP, EVENT_93H_00H) \ __PMC_EV(IAP, EVENT_94H_00H) \ __PMC_EV(IAP, EVENT_97H_00H) \ __PMC_EV(IAP, EVENT_98H_00H) \ __PMC_EV(IAP, EVENT_9CH_01H) \ __PMC_EV(IAP, EVENT_A0H_00H) \ __PMC_EV(IAP, EVENT_A1H_01H) \ __PMC_EV(IAP, EVENT_A1H_02H) \ __PMC_EV(IAP, EVENT_A1H_04H) \ __PMC_EV(IAP, EVENT_A1H_08H) \ __PMC_EV(IAP, EVENT_A1H_0CH) \ __PMC_EV(IAP, EVENT_A1H_10H) \ __PMC_EV(IAP, EVENT_A1H_20H) \ __PMC_EV(IAP, EVENT_A1H_30H) \ __PMC_EV(IAP, EVENT_A1H_40H) \ __PMC_EV(IAP, EVENT_A1H_80H) \ __PMC_EV(IAP, EVENT_A2H_00H) \ __PMC_EV(IAP, EVENT_A2H_01H) \ __PMC_EV(IAP, EVENT_A2H_02H) \ __PMC_EV(IAP, EVENT_A2H_04H) \ __PMC_EV(IAP, EVENT_A2H_08H) \ __PMC_EV(IAP, EVENT_A2H_10H) \ __PMC_EV(IAP, EVENT_A2H_20H) \ __PMC_EV(IAP, EVENT_A2H_40H) \ __PMC_EV(IAP, EVENT_A2H_80H) \ __PMC_EV(IAP, EVENT_A3H_01H) \ __PMC_EV(IAP, EVENT_A3H_02H) \ __PMC_EV(IAP, EVENT_A3H_04H) \ __PMC_EV(IAP, EVENT_A3H_05H) \ __PMC_EV(IAP, EVENT_A3H_08H) \ __PMC_EV(IAP, EVENT_A3H_0CH) \ __PMC_EV(IAP, EVENT_A6H_01H) \ __PMC_EV(IAP, EVENT_A7H_01H) \ __PMC_EV(IAP, EVENT_A8H_01H) \ __PMC_EV(IAP, EVENT_AAH_01H) \ __PMC_EV(IAP, EVENT_AAH_02H) \ __PMC_EV(IAP, EVENT_AAH_03H) \ __PMC_EV(IAP, EVENT_AAH_08H) \ __PMC_EV(IAP, EVENT_ABH_01H) \ __PMC_EV(IAP, EVENT_ABH_02H) \ __PMC_EV(IAP, EVENT_ACH_02H) \ __PMC_EV(IAP, EVENT_ACH_08H) \ __PMC_EV(IAP, EVENT_ACH_0AH) \ __PMC_EV(IAP, EVENT_AEH_01H) \ __PMC_EV(IAP, EVENT_B0H_00H) \ __PMC_EV(IAP, EVENT_B0H_01H) \ __PMC_EV(IAP, EVENT_B0H_02H) \ __PMC_EV(IAP, EVENT_B0H_04H) \ __PMC_EV(IAP, EVENT_B0H_08H) \ __PMC_EV(IAP, EVENT_B0H_10H) \ __PMC_EV(IAP, EVENT_B0H_20H) \ __PMC_EV(IAP, EVENT_B0H_40H) \ __PMC_EV(IAP, EVENT_B0H_80H) \ __PMC_EV(IAP, EVENT_B1H_00H) \ __PMC_EV(IAP, EVENT_B1H_01H) \ __PMC_EV(IAP, EVENT_B1H_02H) \ __PMC_EV(IAP, EVENT_B1H_04H) \ __PMC_EV(IAP, EVENT_B1H_08H) \ __PMC_EV(IAP, EVENT_B1H_10H) \ __PMC_EV(IAP, EVENT_B1H_1FH) \ __PMC_EV(IAP, EVENT_B1H_20H) \ __PMC_EV(IAP, EVENT_B1H_3FH) \ __PMC_EV(IAP, EVENT_B1H_40H) \ __PMC_EV(IAP, EVENT_B1H_80H) \ __PMC_EV(IAP, EVENT_B2H_01H) \ __PMC_EV(IAP, EVENT_B3H_01H) \ __PMC_EV(IAP, EVENT_B3H_02H) \ __PMC_EV(IAP, EVENT_B3H_04H) \ __PMC_EV(IAP, EVENT_B3H_08H) \ __PMC_EV(IAP, EVENT_B3H_10H) \ __PMC_EV(IAP, EVENT_B3H_20H) \ __PMC_EV(IAP, EVENT_B3H_81H) \ __PMC_EV(IAP, EVENT_B3H_82H) \ __PMC_EV(IAP, EVENT_B3H_84H) \ __PMC_EV(IAP, EVENT_B3H_88H) \ __PMC_EV(IAP, EVENT_B3H_90H) \ __PMC_EV(IAP, EVENT_B3H_A0H) \ __PMC_EV(IAP, EVENT_B4H_01H) \ __PMC_EV(IAP, EVENT_B4H_02H) \ __PMC_EV(IAP, EVENT_B4H_04H) \ __PMC_EV(IAP, EVENT_B6H_01H) \ __PMC_EV(IAP, EVENT_B6H_04H) \ __PMC_EV(IAP, EVENT_B7H_01H) \ __PMC_EV(IAP, EVENT_B7H_02H) \ __PMC_EV(IAP, EVENT_B8H_01H) \ __PMC_EV(IAP, EVENT_B8H_02H) \ __PMC_EV(IAP, EVENT_B8H_04H) \ __PMC_EV(IAP, EVENT_BAH_01H) \ __PMC_EV(IAP, EVENT_BAH_02H) \ __PMC_EV(IAP, EVENT_BBH_01H) \ __PMC_EV(IAP, EVENT_BCH_11H) \ __PMC_EV(IAP, EVENT_BCH_12H) \ __PMC_EV(IAP, EVENT_BCH_14H) \ __PMC_EV(IAP, EVENT_BCH_18H) \ __PMC_EV(IAP, EVENT_BCH_21H) \ __PMC_EV(IAP, EVENT_BCH_22H) \ __PMC_EV(IAP, EVENT_BCH_24H) \ __PMC_EV(IAP, EVENT_BCH_28H) \ __PMC_EV(IAP, EVENT_BDH_01H) \ __PMC_EV(IAP, EVENT_BDH_20H) \ __PMC_EV(IAP, EVENT_BFH_05H) \ __PMC_EV(IAP, EVENT_C0H_00H) \ __PMC_EV(IAP, EVENT_C0H_01H) \ __PMC_EV(IAP, EVENT_C0H_02H) \ __PMC_EV(IAP, EVENT_C0H_04H) \ __PMC_EV(IAP, EVENT_C0H_08H) \ __PMC_EV(IAP, EVENT_C1H_00H) \ __PMC_EV(IAP, EVENT_C1H_01H) \ __PMC_EV(IAP, EVENT_C1H_02H) \ __PMC_EV(IAP, EVENT_C1H_08H) \ __PMC_EV(IAP, EVENT_C1H_10H) \ __PMC_EV(IAP, EVENT_C1H_20H) \ __PMC_EV(IAP, EVENT_C1H_40H) \ __PMC_EV(IAP, EVENT_C1H_80H) \ __PMC_EV(IAP, EVENT_C1H_FEH) \ __PMC_EV(IAP, EVENT_C2H_00H) \ __PMC_EV(IAP, EVENT_C2H_01H) \ __PMC_EV(IAP, EVENT_C2H_02H) \ __PMC_EV(IAP, EVENT_C2H_04H) \ __PMC_EV(IAP, EVENT_C2H_07H) \ __PMC_EV(IAP, EVENT_C2H_08H) \ __PMC_EV(IAP, EVENT_C2H_0FH) \ __PMC_EV(IAP, EVENT_C2H_10H) \ __PMC_EV(IAP, EVENT_C3H_00H) \ __PMC_EV(IAP, EVENT_C3H_01H) \ __PMC_EV(IAP, EVENT_C3H_02H) \ __PMC_EV(IAP, EVENT_C3H_04H) \ __PMC_EV(IAP, EVENT_C3H_08H) \ __PMC_EV(IAP, EVENT_C3H_10H) \ __PMC_EV(IAP, EVENT_C3H_20H) \ __PMC_EV(IAP, EVENT_C4H_00H) \ __PMC_EV(IAP, EVENT_C4H_01H) \ __PMC_EV(IAP, EVENT_C4H_02H) \ __PMC_EV(IAP, EVENT_C4H_04H) \ __PMC_EV(IAP, EVENT_C4H_08H) \ __PMC_EV(IAP, EVENT_C4H_0CH) \ __PMC_EV(IAP, EVENT_C4H_0FH) \ __PMC_EV(IAP, EVENT_C4H_10H) \ __PMC_EV(IAP, EVENT_C4H_20H) \ __PMC_EV(IAP, EVENT_C4H_40H) \ __PMC_EV(IAP, EVENT_C4H_7EH) \ __PMC_EV(IAP, EVENT_C4H_BFH) \ __PMC_EV(IAP, EVENT_C4H_EBH) \ __PMC_EV(IAP, EVENT_C4H_F7H) \ __PMC_EV(IAP, EVENT_C4H_F9H) \ __PMC_EV(IAP, EVENT_C4H_FBH) \ __PMC_EV(IAP, EVENT_C4H_FDH) \ __PMC_EV(IAP, EVENT_C4H_FEH) \ __PMC_EV(IAP, EVENT_C5H_00H) \ __PMC_EV(IAP, EVENT_C5H_01H) \ __PMC_EV(IAP, EVENT_C5H_02H) \ __PMC_EV(IAP, EVENT_C5H_04H) \ __PMC_EV(IAP, EVENT_C5H_10H) \ __PMC_EV(IAP, EVENT_C5H_20H) \ __PMC_EV(IAP, EVENT_C5H_7EH) \ __PMC_EV(IAP, EVENT_C5H_BFH) \ __PMC_EV(IAP, EVENT_C5H_EBH) \ __PMC_EV(IAP, EVENT_C5H_F7H) \ __PMC_EV(IAP, EVENT_C5H_F9H) \ __PMC_EV(IAP, EVENT_C5H_FBH) \ __PMC_EV(IAP, EVENT_C5H_FDH) \ __PMC_EV(IAP, EVENT_C5H_FEH) \ __PMC_EV(IAP, EVENT_C6H_00H) \ __PMC_EV(IAP, EVENT_C6H_01H) \ __PMC_EV(IAP, EVENT_C6H_02H) \ __PMC_EV(IAP, EVENT_C7H_00H) \ __PMC_EV(IAP, EVENT_C7H_01H) \ __PMC_EV(IAP, EVENT_C7H_02H) \ __PMC_EV(IAP, EVENT_C7H_04H) \ __PMC_EV(IAP, EVENT_C7H_08H) \ __PMC_EV(IAP, EVENT_C7H_10H) \ __PMC_EV(IAP, EVENT_C7H_1FH) \ __PMC_EV(IAP, EVENT_C8H_00H) \ __PMC_EV(IAP, EVENT_C8H_20H) \ __PMC_EV(IAP, EVENT_C9H_00H) \ __PMC_EV(IAP, EVENT_CAH_00H) \ __PMC_EV(IAP, EVENT_CAH_01H) \ __PMC_EV(IAP, EVENT_CAH_02H) \ __PMC_EV(IAP, EVENT_CAH_04H) \ __PMC_EV(IAP, EVENT_CAH_08H) \ __PMC_EV(IAP, EVENT_CAH_10H) \ __PMC_EV(IAP, EVENT_CAH_20H) \ __PMC_EV(IAP, EVENT_CAH_1EH) \ __PMC_EV(IAP, EVENT_CAH_3FH) \ __PMC_EV(IAP, EVENT_CAH_50H) \ __PMC_EV(IAP, EVENT_CBH_01H) \ __PMC_EV(IAP, EVENT_CBH_02H) \ __PMC_EV(IAP, EVENT_CBH_04H) \ __PMC_EV(IAP, EVENT_CBH_08H) \ __PMC_EV(IAP, EVENT_CBH_10H) \ __PMC_EV(IAP, EVENT_CBH_1FH) \ __PMC_EV(IAP, EVENT_CBH_40H) \ __PMC_EV(IAP, EVENT_CBH_80H) \ __PMC_EV(IAP, EVENT_CCH_00H) \ __PMC_EV(IAP, EVENT_CCH_01H) \ __PMC_EV(IAP, EVENT_CCH_02H) \ __PMC_EV(IAP, EVENT_CCH_03H) \ __PMC_EV(IAP, EVENT_CCH_20H) \ __PMC_EV(IAP, EVENT_CDH_00H) \ __PMC_EV(IAP, EVENT_CDH_01H) \ __PMC_EV(IAP, EVENT_CDH_02H) \ __PMC_EV(IAP, EVENT_CEH_00H) \ __PMC_EV(IAP, EVENT_CFH_00H) \ __PMC_EV(IAP, EVENT_D0H_00H) \ __PMC_EV(IAP, EVENT_D0H_01H) \ __PMC_EV(IAP, EVENT_D0H_02H) \ __PMC_EV(IAP, EVENT_D0H_10H) \ __PMC_EV(IAP, EVENT_D0H_11H) \ __PMC_EV(IAP, EVENT_D0H_12H) \ __PMC_EV(IAP, EVENT_D0H_20H) \ __PMC_EV(IAP, EVENT_D0H_21H) \ __PMC_EV(IAP, EVENT_D0H_40H) \ __PMC_EV(IAP, EVENT_D0H_41H) \ __PMC_EV(IAP, EVENT_D0H_42H) \ __PMC_EV(IAP, EVENT_D0H_80H) \ __PMC_EV(IAP, EVENT_D0H_81H) \ __PMC_EV(IAP, EVENT_D0H_82H) \ __PMC_EV(IAP, EVENT_D1H_01H) \ __PMC_EV(IAP, EVENT_D1H_02H) \ __PMC_EV(IAP, EVENT_D1H_04H) \ __PMC_EV(IAP, EVENT_D1H_08H) \ __PMC_EV(IAP, EVENT_D1H_10H) \ __PMC_EV(IAP, EVENT_D1H_20H) \ __PMC_EV(IAP, EVENT_D1H_40H) \ __PMC_EV(IAP, EVENT_D2H_01H) \ __PMC_EV(IAP, EVENT_D2H_02H) \ __PMC_EV(IAP, EVENT_D2H_04H) \ __PMC_EV(IAP, EVENT_D2H_08H) \ __PMC_EV(IAP, EVENT_D2H_0FH) \ __PMC_EV(IAP, EVENT_D2H_10H) \ __PMC_EV(IAP, EVENT_D3H_01H) \ __PMC_EV(IAP, EVENT_D3H_03H) \ __PMC_EV(IAP, EVENT_D3H_04H) \ __PMC_EV(IAP, EVENT_D3H_0CH) \ __PMC_EV(IAP, EVENT_D3H_10H) \ __PMC_EV(IAP, EVENT_D3H_20H) \ __PMC_EV(IAP, EVENT_D4H_01H) \ __PMC_EV(IAP, EVENT_D4H_02H) \ __PMC_EV(IAP, EVENT_D4H_04H) \ __PMC_EV(IAP, EVENT_D4H_08H) \ __PMC_EV(IAP, EVENT_D4H_0FH) \ __PMC_EV(IAP, EVENT_D5H_01H) \ __PMC_EV(IAP, EVENT_D5H_02H) \ __PMC_EV(IAP, EVENT_D5H_04H) \ __PMC_EV(IAP, EVENT_D5H_08H) \ __PMC_EV(IAP, EVENT_D5H_0FH) \ __PMC_EV(IAP, EVENT_D7H_00H) \ __PMC_EV(IAP, EVENT_D8H_00H) \ __PMC_EV(IAP, EVENT_D8H_01H) \ __PMC_EV(IAP, EVENT_D8H_02H) \ __PMC_EV(IAP, EVENT_D8H_03H) \ __PMC_EV(IAP, EVENT_D8H_04H) \ __PMC_EV(IAP, EVENT_D9H_00H) \ __PMC_EV(IAP, EVENT_D9H_01H) \ __PMC_EV(IAP, EVENT_D9H_02H) \ __PMC_EV(IAP, EVENT_D9H_03H) \ __PMC_EV(IAP, EVENT_DAH_00H) \ __PMC_EV(IAP, EVENT_DAH_01H) \ __PMC_EV(IAP, EVENT_DAH_02H) \ __PMC_EV(IAP, EVENT_DBH_00H) \ __PMC_EV(IAP, EVENT_DBH_01H) \ __PMC_EV(IAP, EVENT_DCH_01H) \ __PMC_EV(IAP, EVENT_DCH_02H) \ __PMC_EV(IAP, EVENT_DCH_04H) \ __PMC_EV(IAP, EVENT_DCH_08H) \ __PMC_EV(IAP, EVENT_DCH_10H) \ __PMC_EV(IAP, EVENT_DCH_1FH) \ __PMC_EV(IAP, EVENT_E0H_00H) \ __PMC_EV(IAP, EVENT_E0H_01H) \ __PMC_EV(IAP, EVENT_E2H_00H) \ __PMC_EV(IAP, EVENT_E4H_00H) \ __PMC_EV(IAP, EVENT_E4H_01H) \ __PMC_EV(IAP, EVENT_E5H_01H) \ __PMC_EV(IAP, EVENT_E6H_00H) \ __PMC_EV(IAP, EVENT_E6H_01H) \ __PMC_EV(IAP, EVENT_E6H_02H) \ __PMC_EV(IAP, EVENT_E6H_08H) \ __PMC_EV(IAP, EVENT_E6H_10H) \ __PMC_EV(IAP, EVENT_E6H_1FH) \ __PMC_EV(IAP, EVENT_E7H_01H) \ __PMC_EV(IAP, EVENT_E8H_01H) \ __PMC_EV(IAP, EVENT_E8H_02H) \ __PMC_EV(IAP, EVENT_E8H_03H) \ __PMC_EV(IAP, EVENT_ECH_01H) \ __PMC_EV(IAP, EVENT_F0H_00H) \ __PMC_EV(IAP, EVENT_F0H_01H) \ __PMC_EV(IAP, EVENT_F0H_02H) \ __PMC_EV(IAP, EVENT_F0H_04H) \ __PMC_EV(IAP, EVENT_F0H_08H) \ __PMC_EV(IAP, EVENT_F0H_10H) \ __PMC_EV(IAP, EVENT_F0H_20H) \ __PMC_EV(IAP, EVENT_F0H_40H) \ __PMC_EV(IAP, EVENT_F0H_80H) \ __PMC_EV(IAP, EVENT_F1H_01H) \ __PMC_EV(IAP, EVENT_F1H_02H) \ __PMC_EV(IAP, EVENT_F1H_04H) \ __PMC_EV(IAP, EVENT_F1H_07H) \ __PMC_EV(IAP, EVENT_F2H_01H) \ __PMC_EV(IAP, EVENT_F2H_02H) \ __PMC_EV(IAP, EVENT_F2H_04H) \ __PMC_EV(IAP, EVENT_F2H_05H) \ __PMC_EV(IAP, EVENT_F2H_06H) \ __PMC_EV(IAP, EVENT_F2H_08H) \ __PMC_EV(IAP, EVENT_F2H_0AH) \ __PMC_EV(IAP, EVENT_F2H_0FH) \ __PMC_EV(IAP, EVENT_F3H_01H) \ __PMC_EV(IAP, EVENT_F3H_02H) \ __PMC_EV(IAP, EVENT_F3H_04H) \ __PMC_EV(IAP, EVENT_F3H_08H) \ __PMC_EV(IAP, EVENT_F3H_10H) \ __PMC_EV(IAP, EVENT_F3H_20H) \ __PMC_EV(IAP, EVENT_F4H_01H) \ __PMC_EV(IAP, EVENT_F4H_02H) \ __PMC_EV(IAP, EVENT_F4H_04H) \ __PMC_EV(IAP, EVENT_F4H_08H) \ __PMC_EV(IAP, EVENT_F4H_10H) \ __PMC_EV(IAP, EVENT_F6H_01H) \ __PMC_EV(IAP, EVENT_F7H_01H) \ __PMC_EV(IAP, EVENT_F7H_02H) \ __PMC_EV(IAP, EVENT_F7H_04H) \ __PMC_EV(IAP, EVENT_F8H_00H) \ __PMC_EV(IAP, EVENT_F8H_01H) \ __PMC_EV(IAP, EVENT_FDH_01H) \ __PMC_EV(IAP, EVENT_FDH_02H) \ __PMC_EV(IAP, EVENT_FDH_04H) \ __PMC_EV(IAP, EVENT_FDH_08H) \ __PMC_EV(IAP, EVENT_FDH_10H) \ __PMC_EV(IAP, EVENT_FDH_20H) \ __PMC_EV(IAP, EVENT_FDH_40H) #define PMC_EV_IAP_FIRST PMC_EV_IAP_ARCH_BR_INS_RET #define PMC_EV_IAP_LAST PMC_EV_IAP_EVENT_FDH_40H /* * Map "architectural" event names to event ids. */ #define __PMC_EV_ALIAS_INTEL_ARCHITECTURAL() \ __PMC_EV_ALIAS("branch-instruction-retired", IAP_ARCH_BR_INS_RET) \ __PMC_EV_ALIAS("branch-misses-retired", IAP_ARCH_BR_MIS_RET) \ __PMC_EV_ALIAS("instruction-retired", IAP_ARCH_INS_RET) \ __PMC_EV_ALIAS("llc-misses", IAP_ARCH_LLC_MIS) \ __PMC_EV_ALIAS("llc-reference", IAP_ARCH_LLC_REF) \ __PMC_EV_ALIAS("unhalted-reference-cycles", IAP_ARCH_UNH_REF_CYC) \ __PMC_EV_ALIAS("unhalted-core-cycles", IAP_ARCH_UNH_COR_CYC) /* * Aliases for Atom PMCs. */ #define __PMC_EV_ALIAS_ATOM() \ __PMC_EV_ALIAS_INTEL_ARCHITECTURAL() \ __PMC_EV_ALIAS("BACLEARS", IAP_EVENT_E6H_01H) \ __PMC_EV_ALIAS("BOGUS_BR", IAP_EVENT_E4H_00H) \ __PMC_EV_ALIAS("BR_BAC_MISSP_EXEC", IAP_EVENT_8AH_00H) \ __PMC_EV_ALIAS("BR_CALL_EXEC", IAP_EVENT_92H_00H) \ __PMC_EV_ALIAS("BR_CALL_MISSP_EXEC", IAP_EVENT_93H_00H) \ __PMC_EV_ALIAS("BR_CND_EXEC", IAP_EVENT_8BH_00H) \ __PMC_EV_ALIAS("BR_CND_MISSP_EXEC", IAP_EVENT_8CH_00H) \ __PMC_EV_ALIAS("BR_IND_CALL_EXEC", IAP_EVENT_94H_00H) \ __PMC_EV_ALIAS("BR_IND_EXEC", IAP_EVENT_8DH_00H) \ __PMC_EV_ALIAS("BR_IND_MISSP_EXEC", IAP_EVENT_8EH_00H) \ __PMC_EV_ALIAS("BR_INST_DECODED", IAP_EVENT_E0H_01H) \ __PMC_EV_ALIAS("BR_INST_EXEC", IAP_EVENT_88H_00H) \ __PMC_EV_ALIAS("BR_INST_RETIRED.ANY", IAP_EVENT_C4H_00H) \ __PMC_EV_ALIAS("BR_INST_RETIRED.ANY1", IAP_EVENT_C4H_0FH) \ __PMC_EV_ALIAS("BR_INST_RETIRED.MISPRED", IAP_EVENT_C5H_00H) \ __PMC_EV_ALIAS("BR_INST_RETIRED.MISPRED_NOT_TAKEN", \ IAP_EVENT_C4H_02H) \ __PMC_EV_ALIAS("BR_INST_RETIRED.MISPRED_TAKEN", IAP_EVENT_C4H_08H) \ __PMC_EV_ALIAS("BR_INST_RETIRED.PRED_NOT_TAKEN", IAP_EVENT_C4H_01H) \ __PMC_EV_ALIAS("BR_INST_RETIRED.PRED_TAKEN", IAP_EVENT_C4H_04H) \ __PMC_EV_ALIAS("BR_INST_RETIRED.TAKEN", IAP_EVENT_C4H_0CH) \ __PMC_EV_ALIAS("BR_MISSP_EXEC", IAP_EVENT_89H_00H) \ __PMC_EV_ALIAS("BR_RET_BAC_MISSP_EXEC", IAP_EVENT_91H_00H) \ __PMC_EV_ALIAS("BR_RET_EXEC", IAP_EVENT_8FH_00H) \ __PMC_EV_ALIAS("BR_RET_MISSP_EXEC", IAP_EVENT_90H_00H) \ __PMC_EV_ALIAS("BR_TKN_BUBBLE_1", IAP_EVENT_97H_00H) \ __PMC_EV_ALIAS("BR_TKN_BUBBLE_2", IAP_EVENT_98H_00H) \ __PMC_EV_ALIAS("BUSQ_EMPTY", IAP_EVENT_7DH) \ __PMC_EV_ALIAS("BUS_BNR_DRV", IAP_EVENT_61H) \ __PMC_EV_ALIAS("BUS_DATA_RCV", IAP_EVENT_64H) \ __PMC_EV_ALIAS("BUS_DRDY_CLOCKS", IAP_EVENT_62H) \ __PMC_EV_ALIAS("BUS_HITM_DRV", IAP_EVENT_7BH) \ __PMC_EV_ALIAS("BUS_HIT_DRV", IAP_EVENT_7AH) \ __PMC_EV_ALIAS("BUS_IO_WAIT", IAP_EVENT_7FH) \ __PMC_EV_ALIAS("BUS_LOCK_CLOCKS", IAP_EVENT_63H) \ __PMC_EV_ALIAS("BUS_REQUEST_OUTSTANDING", IAP_EVENT_60H) \ __PMC_EV_ALIAS("BUS_TRANS_ANY", IAP_EVENT_70H) \ __PMC_EV_ALIAS("BUS_TRANS_BRD", IAP_EVENT_65H) \ __PMC_EV_ALIAS("BUS_TRANS_BURST", IAP_EVENT_6EH) \ __PMC_EV_ALIAS("BUS_TRANS_DEF", IAP_EVENT_6DH) \ __PMC_EV_ALIAS("BUS_TRANS_IFETCH", IAP_EVENT_68H) \ __PMC_EV_ALIAS("BUS_TRANS_INVAL", IAP_EVENT_69H) \ __PMC_EV_ALIAS("BUS_TRANS_IO", IAP_EVENT_6CH) \ __PMC_EV_ALIAS("BUS_TRANS_MEM", IAP_EVENT_6FH) \ __PMC_EV_ALIAS("BUS_TRANS_P", IAP_EVENT_6BH) \ __PMC_EV_ALIAS("BUS_TRANS_PWR", IAP_EVENT_6AH) \ __PMC_EV_ALIAS("BUS_TRANS_RFO", IAP_EVENT_66H) \ __PMC_EV_ALIAS("BUS_TRANS_WB", IAP_EVENT_67H) \ __PMC_EV_ALIAS("CMP_SNOOP", IAP_EVENT_78H) \ __PMC_EV_ALIAS("CPU_CLK_UNHALTED.BUS", IAP_EVENT_3CH_01H) \ __PMC_EV_ALIAS("CPU_CLK_UNHALTED.CORE_P", IAP_EVENT_3CH_00H) \ __PMC_EV_ALIAS("CPU_CLK_UNHALTED.NO_OTHER", IAP_EVENT_3CH_02H) \ __PMC_EV_ALIAS("CYCLES_DIV_BUSY", IAP_EVENT_14H_01H) \ __PMC_EV_ALIAS("CYCLES_INT_MASKED.CYCLES_INT_MASKED", \ IAP_EVENT_C6H_01H) \ __PMC_EV_ALIAS("CYCLES_INT_MASKED.CYCLES_INT_PENDING_AND_MASKED", \ IAP_EVENT_C6H_02H) \ __PMC_EV_ALIAS("CYCLES_L1I_MEM_STALLED", IAP_EVENT_86H_00H) \ __PMC_EV_ALIAS("DATA_TLB_MISSES.DTLB_MISS", IAP_EVENT_08H_07H) \ __PMC_EV_ALIAS("DATA_TLB_MISSES.DTLB_MISS_LD", IAP_EVENT_08H_05H) \ __PMC_EV_ALIAS("DATA_TLB_MISSES.DTLB_MISS_ST", IAP_EVENT_08H_06H) \ __PMC_EV_ALIAS("DATA_TLB_MISSES.UTLB_MISS_LD", IAP_EVENT_08H_09H) \ __PMC_EV_ALIAS("DELAYED_BYPASS.FP", IAP_EVENT_19H_00H) \ __PMC_EV_ALIAS("DELAYED_BYPASS.LOAD", IAP_EVENT_19H_01H) \ __PMC_EV_ALIAS("DELAYED_BYPASS.SIMD", IAP_EVENT_19H_02H) \ __PMC_EV_ALIAS("DIV", IAP_EVENT_13H_00H) \ __PMC_EV_ALIAS("DIV.AR", IAP_EVENT_13H_81H) \ __PMC_EV_ALIAS("DIV.S", IAP_EVENT_13H_01H) \ __PMC_EV_ALIAS("DTLB_MISSES.ANY", IAP_EVENT_08H_01H) \ __PMC_EV_ALIAS("DTLB_MISSES.L0_MISS_LD", IAP_EVENT_08H_04H) \ __PMC_EV_ALIAS("DTLB_MISSES.MISS_LD", IAP_EVENT_08H_02H) \ __PMC_EV_ALIAS("DTLB_MISSES.MISS_ST", IAP_EVENT_08H_08H) \ __PMC_EV_ALIAS("EIST_TRANS", IAP_EVENT_3AH_00H) \ __PMC_EV_ALIAS("ESP.ADDITIONS", IAP_EVENT_ABH_02H) \ __PMC_EV_ALIAS("ESP.SYNCH", IAP_EVENT_ABH_01H) \ __PMC_EV_ALIAS("EXT_SNOOP", IAP_EVENT_77H) \ __PMC_EV_ALIAS("FP_ASSIST", IAP_EVENT_11H_01H) \ __PMC_EV_ALIAS("FP_ASSIST.AR", IAP_EVENT_11H_81H) \ __PMC_EV_ALIAS("FP_COMP_OPS_EXE", IAP_EVENT_10H_00H) \ __PMC_EV_ALIAS("FP_MMX_TRANS_TO_FP", IAP_EVENT_CCH_02H) \ __PMC_EV_ALIAS("FP_MMX_TRANS_TO_MMX", IAP_EVENT_CCH_01H) \ __PMC_EV_ALIAS("HW_INT_RCV", IAP_EVENT_C8H_00H) \ __PMC_EV_ALIAS("ICACHE.ACCESSES", IAP_EVENT_80H_03H) \ __PMC_EV_ALIAS("ICACHE.MISSES", IAP_EVENT_80H_02H) \ __PMC_EV_ALIAS("IDLE_DURING_DIV", IAP_EVENT_18H_00H) \ __PMC_EV_ALIAS("ILD_STALL", IAP_EVENT_87H_00H) \ __PMC_EV_ALIAS("INST_QUEUE.FULL", IAP_EVENT_83H_02H) \ __PMC_EV_ALIAS("INST_RETIRED.ANY_P", IAP_EVENT_C0H_00H) \ __PMC_EV_ALIAS("INST_RETIRED.LOADS", IAP_EVENT_C0H_01H) \ __PMC_EV_ALIAS("INST_RETIRED.OTHER", IAP_EVENT_C0H_04H) \ __PMC_EV_ALIAS("INST_RETIRED.STORES", IAP_EVENT_C0H_02H) \ __PMC_EV_ALIAS("ITLB.FLUSH", IAP_EVENT_82H_04H) \ __PMC_EV_ALIAS("ITLB.LARGE_MISS", IAP_EVENT_82H_10H) \ __PMC_EV_ALIAS("ITLB.MISSES", IAP_EVENT_82H_02H) \ __PMC_EV_ALIAS("ITLB.SMALL_MISS", IAP_EVENT_82H_02H) \ __PMC_EV_ALIAS("ITLB_MISS_RETIRED", IAP_EVENT_C9H_00H) \ __PMC_EV_ALIAS("L1D_ALL_CACHE_REF", IAP_EVENT_43H_02H) \ __PMC_EV_ALIAS("L1D_ALL_REF", IAP_EVENT_43H_01H) \ __PMC_EV_ALIAS("L1D_CACHE.LD", IAP_EVENT_40H_21H) \ __PMC_EV_ALIAS("L1D_CACHE.ST", IAP_EVENT_41H_22H) \ __PMC_EV_ALIAS("L1D_CACHE_LOCK", IAP_EVENT_42H) \ __PMC_EV_ALIAS("L1D_CACHE_LOCK_DURATION", IAP_EVENT_42H_10H) \ __PMC_EV_ALIAS("L1D_M_EVICT", IAP_EVENT_47H_00H) \ __PMC_EV_ALIAS("L1D_M_REPL", IAP_EVENT_46H_00H) \ __PMC_EV_ALIAS("L1D_PEND_MISS", IAP_EVENT_48H_00H) \ __PMC_EV_ALIAS("L1D_PREFETCH.REQUESTS", IAP_EVENT_4EH_10H) \ __PMC_EV_ALIAS("L1D_REPL", IAP_EVENT_45H_0FH) \ __PMC_EV_ALIAS("L1D_SPLIT.LOADS", IAP_EVENT_49H_01H) \ __PMC_EV_ALIAS("L1D_SPLIT.STORES", IAP_EVENT_49H_02H) \ __PMC_EV_ALIAS("L1I_MISSES", IAP_EVENT_81H_00H) \ __PMC_EV_ALIAS("L1I_READS", IAP_EVENT_80H_00H) \ __PMC_EV_ALIAS("L2_ADS", IAP_EVENT_21H) \ __PMC_EV_ALIAS("L2_DBUS_BUSY_RD", IAP_EVENT_23H) \ __PMC_EV_ALIAS("L2_IFETCH", IAP_EVENT_28H) \ __PMC_EV_ALIAS("L2_LD", IAP_EVENT_29H) \ __PMC_EV_ALIAS("L2_LINES_IN", IAP_EVENT_24H) \ __PMC_EV_ALIAS("L2_LINES_OUT", IAP_EVENT_26H) \ __PMC_EV_ALIAS("L2_LOCK", IAP_EVENT_2BH) \ __PMC_EV_ALIAS("L2_M_LINES_IN", IAP_EVENT_25H) \ __PMC_EV_ALIAS("L2_M_LINES_OUT", IAP_EVENT_27H) \ __PMC_EV_ALIAS("L2_NO_REQ", IAP_EVENT_32H) \ __PMC_EV_ALIAS("L2_REJECT_BUSQ", IAP_EVENT_30H) \ __PMC_EV_ALIAS("L2_RQSTS", IAP_EVENT_2EH) \ __PMC_EV_ALIAS("L2_RQSTS.SELF.DEMAND.I_STATE", IAP_EVENT_2EH_41H) \ __PMC_EV_ALIAS("L2_RQSTS.SELF.DEMAND.MESI", IAP_EVENT_2EH_4FH) \ __PMC_EV_ALIAS("L2_ST", IAP_EVENT_2AH) \ __PMC_EV_ALIAS("LOAD_BLOCK.L1D", IAP_EVENT_03H_20H) \ __PMC_EV_ALIAS("LOAD_BLOCK.OVERLAP_STORE", IAP_EVENT_03H_08H) \ __PMC_EV_ALIAS("LOAD_BLOCK.STA", IAP_EVENT_03H_02H) \ __PMC_EV_ALIAS("LOAD_BLOCK.STD", IAP_EVENT_03H_04H) \ __PMC_EV_ALIAS("LOAD_BLOCK.UNTIL_RETIRE", IAP_EVENT_03H_10H) \ __PMC_EV_ALIAS("LOAD_HIT_PRE", IAP_EVENT_4CH_00H) \ __PMC_EV_ALIAS("MACHINE_CLEARS.SMC", IAP_EVENT_C3H_01H) \ __PMC_EV_ALIAS("MACHINE_NUKES.MEM_ORDER", IAP_EVENT_C3H_04H) \ __PMC_EV_ALIAS("MACRO_INSTS.ALL_DECODED", IAP_EVENT_AAH_03H) \ __PMC_EV_ALIAS("MACRO_INSTS.CISC_DECODED", IAP_EVENT_AAH_02H) \ __PMC_EV_ALIAS("MEMORY_DISAMBIGUATION.RESET", IAP_EVENT_09H_01H) \ __PMC_EV_ALIAS("MEMORY_DISAMBIGUATION.SUCCESS", IAP_EVENT_09H_02H) \ __PMC_EV_ALIAS("MEM_LOAD_RETIRED.DTLB_MISS", IAP_EVENT_CBH_04H) \ __PMC_EV_ALIAS("MEM_LOAD_RETIRED.L2_HIT", IAP_EVENT_CBH_01H) \ __PMC_EV_ALIAS("MEM_LOAD_RETIRED.L2_LINE_MISS", IAP_EVENT_CBH_08H) \ __PMC_EV_ALIAS("MEM_LOAD_RETIRED.L2_MISS", IAP_EVENT_CBH_02H) \ __PMC_EV_ALIAS("MUL", IAP_EVENT_12H_00H) \ __PMC_EV_ALIAS("MUL.AR", IAP_EVENT_12H_81H) \ __PMC_EV_ALIAS("MUL.S", IAP_EVENT_12H_01H) \ __PMC_EV_ALIAS("PAGE_WALKS.CYCLES", IAP_EVENT_0CH_03H) \ __PMC_EV_ALIAS("PAGE_WALKS.WALKS", IAP_EVENT_0CH_03H) \ __PMC_EV_ALIAS("PREFETCH.PREFETCHNTA", IAP_EVENT_07H_08H) \ __PMC_EV_ALIAS("PREFETCH.PREFETCHT0", IAP_EVENT_07H_01H) \ __PMC_EV_ALIAS("PREFETCH.SW_L2", IAP_EVENT_07H_06H) \ __PMC_EV_ALIAS("PREF_RQSTS_DN", IAP_EVENT_F8H_00H) \ __PMC_EV_ALIAS("PREF_RQSTS_UP", IAP_EVENT_F0H_00H) \ __PMC_EV_ALIAS("RAT_STALLS.ANY", IAP_EVENT_D2H_0FH) \ __PMC_EV_ALIAS("RAT_STALLS.FLAGS", IAP_EVENT_D2H_04H) \ __PMC_EV_ALIAS("RAT_STALLS.FPSW", IAP_EVENT_D2H_08H) \ __PMC_EV_ALIAS("RAT_STALLS.PARTIAL_CYCLES", IAP_EVENT_D2H_02H) \ __PMC_EV_ALIAS("RAT_STALLS.ROB_READ_PORT", IAP_EVENT_D2H_01H) \ __PMC_EV_ALIAS("RESOURCE_STALLS.ANY", IAP_EVENT_DCH_1FH) \ __PMC_EV_ALIAS("RESOURCE_STALLS.BR_MISS_CLEAR", IAP_EVENT_DCH_10H) \ __PMC_EV_ALIAS("RESOURCE_STALLS.FPCW", IAP_EVENT_DCH_08H) \ __PMC_EV_ALIAS("RESOURCE_STALLS.LD_ST", IAP_EVENT_DCH_04H) \ __PMC_EV_ALIAS("RESOURCE_STALLS.ROB_FULL", IAP_EVENT_DCH_01H) \ __PMC_EV_ALIAS("RESOURCE_STALLS.RS_FULL", IAP_EVENT_DCH_02H) \ __PMC_EV_ALIAS("RS_UOPS_DISPATCHED", IAP_EVENT_A0H_00H) \ __PMC_EV_ALIAS("RS_UOPS_DISPATCHED.PORT0", IAP_EVENT_A1H_01H) \ __PMC_EV_ALIAS("RS_UOPS_DISPATCHED.PORT1", IAP_EVENT_A1H_02H) \ __PMC_EV_ALIAS("RS_UOPS_DISPATCHED.PORT2", IAP_EVENT_A1H_04H) \ __PMC_EV_ALIAS("RS_UOPS_DISPATCHED.PORT3", IAP_EVENT_A1H_08H) \ __PMC_EV_ALIAS("RS_UOPS_DISPATCHED.PORT4", IAP_EVENT_A1H_10H) \ __PMC_EV_ALIAS("RS_UOPS_DISPATCHED.PORT5", IAP_EVENT_A1H_20H) \ __PMC_EV_ALIAS("SB_DRAIN_CYCLES", IAP_EVENT_04H_01H) \ __PMC_EV_ALIAS("SEGMENT_REG_LOADS.ANY", IAP_EVENT_06H_00H) \ __PMC_EV_ALIAS("SEG_REG_RENAMES.ANY", IAP_EVENT_D5H_0FH) \ __PMC_EV_ALIAS("SEG_REG_RENAMES.DS", IAP_EVENT_D5H_02H) \ __PMC_EV_ALIAS("SEG_REG_RENAMES.ES", IAP_EVENT_D5H_01H) \ __PMC_EV_ALIAS("SEG_REG_RENAMES.FS", IAP_EVENT_D5H_04H) \ __PMC_EV_ALIAS("SEG_REG_RENAMES.GS", IAP_EVENT_D5H_08H) \ __PMC_EV_ALIAS("SEG_RENAME_STALLS.ANY", IAP_EVENT_D4H_0FH) \ __PMC_EV_ALIAS("SEG_RENAME_STALLS.DS", IAP_EVENT_D4H_02H) \ __PMC_EV_ALIAS("SEG_RENAME_STALLS.ES", IAP_EVENT_D4H_01H) \ __PMC_EV_ALIAS("SEG_RENAME_STALLS.FS", IAP_EVENT_D4H_04H) \ __PMC_EV_ALIAS("SEG_RENAME_STALLS.GS", IAP_EVENT_D4H_08H) \ __PMC_EV_ALIAS("SIMD_ASSIST", IAP_EVENT_CDH_00H) \ __PMC_EV_ALIAS("SIMD_COMP_INST_RETIRED.PACKED_DOUBLE", \ IAP_EVENT_CAH_04H) \ __PMC_EV_ALIAS("SIMD_COMP_INST_RETIRED.PACKED_SINGLE", \ IAP_EVENT_CAH_01H) \ __PMC_EV_ALIAS("SIMD_COMP_INST_RETIRED.SCALAR_DOUBLE", \ IAP_EVENT_CAH_08H) \ __PMC_EV_ALIAS("SIMD_COMP_INST_RETIRED.SCALAR_SINGLE", \ IAP_EVENT_CAH_02H) \ __PMC_EV_ALIAS("SIMD_INSTR_RETIRED", IAP_EVENT_CEH_00H) \ __PMC_EV_ALIAS("SIMD_INST_RETIRED.ANY", IAP_EVENT_C7H_1FH) \ __PMC_EV_ALIAS("SIMD_INST_RETIRED.PACKED_DOUBLE", IAP_EVENT_C7H_04H) \ __PMC_EV_ALIAS("SIMD_INST_RETIRED.PACKED_SINGLE", IAP_EVENT_C7H_01H) \ __PMC_EV_ALIAS("SIMD_INST_RETIRED.SCALAR_DOUBLE", IAP_EVENT_C7H_08H) \ __PMC_EV_ALIAS("SIMD_INST_RETIRED.SCALAR_SINGLE", IAP_EVENT_C7H_02H) \ __PMC_EV_ALIAS("SIMD_INST_RETIRED.VECTOR", IAP_EVENT_C7H_10H) \ __PMC_EV_ALIAS("SIMD_SAT_INSTR_RETIRED", IAP_EVENT_CFH_00H) \ __PMC_EV_ALIAS("SIMD_SAT_UOP_EXEC.AR", IAP_EVENT_B1H_80H) \ __PMC_EV_ALIAS("SIMD_SAT_UOP_EXEC.S", IAP_EVENT_B1H_00H) \ __PMC_EV_ALIAS("SIMD_UOPS_EXEC.AR", IAP_EVENT_B0H_80H) \ __PMC_EV_ALIAS("SIMD_UOPS_EXEC.S", IAP_EVENT_B0H_00H) \ __PMC_EV_ALIAS("SIMD_UOP_TYPE_EXEC.ARITHMETIC.AR", IAP_EVENT_B3H_A0H) \ __PMC_EV_ALIAS("SIMD_UOP_TYPE_EXEC.ARITHMETIC.S", IAP_EVENT_B3H_20H) \ __PMC_EV_ALIAS("SIMD_UOP_TYPE_EXEC.LOGICAL.AR", IAP_EVENT_B3H_90H) \ __PMC_EV_ALIAS("SIMD_UOP_TYPE_EXEC.LOGICAL.S", IAP_EVENT_B3H_10H) \ __PMC_EV_ALIAS("SIMD_UOP_TYPE_EXEC.MUL.AR", IAP_EVENT_B3H_81H) \ __PMC_EV_ALIAS("SIMD_UOP_TYPE_EXEC.MUL.S", IAP_EVENT_B3H_01H) \ __PMC_EV_ALIAS("SIMD_UOP_TYPE_EXEC.PACK.AR", IAP_EVENT_B3H_84H) \ __PMC_EV_ALIAS("SIMD_UOP_TYPE_EXEC.PACK.S", IAP_EVENT_B3H_04H) \ __PMC_EV_ALIAS("SIMD_UOP_TYPE_EXEC.SHIFT.AR", IAP_EVENT_B3H_82H) \ __PMC_EV_ALIAS("SIMD_UOP_TYPE_EXEC.SHIFT.S", IAP_EVENT_B3H_02H) \ __PMC_EV_ALIAS("SIMD_UOP_TYPE_EXEC.UNPACK.AR", IAP_EVENT_B3H_88H) \ __PMC_EV_ALIAS("SIMD_UOP_TYPE_EXEC.UNPACK.S", IAP_EVENT_B3H_08H) \ __PMC_EV_ALIAS("SNOOP_STALL_DRV", IAP_EVENT_7EH) \ __PMC_EV_ALIAS("SSE_PRE_EXEC.L2", IAP_EVENT_07H_02H) \ __PMC_EV_ALIAS("SSE_PRE_EXEC.STORES", IAP_EVENT_07H_03H) \ __PMC_EV_ALIAS("SSE_PRE_MISS.L1", IAP_EVENT_4BH_01H) \ __PMC_EV_ALIAS("SSE_PRE_MISS.L2", IAP_EVENT_4BH_02H) \ __PMC_EV_ALIAS("SSE_PRE_MISS.NTA", IAP_EVENT_4BH_00H) \ __PMC_EV_ALIAS("STORE_BLOCK.ORDER", IAP_EVENT_04H_02H) \ __PMC_EV_ALIAS("STORE_BLOCK.SNOOP", IAP_EVENT_04H_08H) \ __PMC_EV_ALIAS("STORE_FORWARDS.GOOD", IAP_EVENT_02H_81H) \ __PMC_EV_ALIAS("THERMAL_TRIP", IAP_EVENT_3BH_C0H) \ __PMC_EV_ALIAS("UOPS_RETIRED.ANY", IAP_EVENT_C2H_10H) \ __PMC_EV_ALIAS("UOPS_RETIRED.FUSED", IAP_EVENT_C2H_07H) \ __PMC_EV_ALIAS("UOPS_RETIRED.LD_IND_BR", IAP_EVENT_C2H_01H) \ __PMC_EV_ALIAS("UOPS_RETIRED.MACRO_FUSION", IAP_EVENT_C2H_04H) \ __PMC_EV_ALIAS("UOPS_RETIRED.NON_FUSED", IAP_EVENT_C2H_08H) \ __PMC_EV_ALIAS("UOPS_RETIRED.STD_STA", IAP_EVENT_C2H_02H) \ __PMC_EV_ALIAS("X87_COMP_OPS_EXE.ANY.AR", IAP_EVENT_10H_81H) \ __PMC_EV_ALIAS("X87_COMP_OPS_EXE.ANY.S", IAP_EVENT_10H_01H) \ __PMC_EV_ALIAS("X87_OPS_RETIRED.ANY", IAP_EVENT_C1H_FEH) \ __PMC_EV_ALIAS("X87_OPS_RETIRED.FXCH", IAP_EVENT_C1H_01H) /* * Aliases for Atom Silvermont PMCs. */ #define __PMC_EV_ALIAS_ATOM_SILVERMONT() \ __PMC_EV_ALIAS_INTEL_ARCHITECTURAL() \ __PMC_EV_ALIAS("REHABQ.LD_BLOCK_ST_FORWARD", IAP_EVENT_03H_01H) \ __PMC_EV_ALIAS("REHABQ.LD_BLOCK_STD_NOTREADY", IAP_EVENT_03H_02H) \ __PMC_EV_ALIAS("REHABQ.ST_SPLITS", IAP_EVENT_03H_04H) \ __PMC_EV_ALIAS("REHABQ.LD_SPLITS", IAP_EVENT_03H_08H) \ __PMC_EV_ALIAS("REHABQ.LOCK", IAP_EVENT_03H_10H) \ __PMC_EV_ALIAS("REHABQ.STA_FULL", IAP_EVENT_03H_20H) \ __PMC_EV_ALIAS("REHABQ.ANY_LD", IAP_EVENT_03H_40H) \ __PMC_EV_ALIAS("REHABQ.ANY_ST", IAP_EVENT_03H_80H) \ __PMC_EV_ALIAS("MEM_UOPS_RETIRED.L1_MISS_LOADS", IAP_EVENT_04H_01H) \ __PMC_EV_ALIAS("MEM_UOPS_RETIRED.L2_HIT_LOADS", IAP_EVENT_04H_02H) \ __PMC_EV_ALIAS("MEM_UOPS_RETIRED.L2_MISS_LOADS", IAP_EVENT_04H_04H) \ __PMC_EV_ALIAS("MEM_UOPS_RETIRED.DTLB_MISS_LOADS", IAP_EVENT_04H_08H) \ __PMC_EV_ALIAS("MEM_UOPS_RETIRED.UTLB_MISS", IAP_EVENT_04H_10H) \ __PMC_EV_ALIAS("MEM_UOPS_RETIRED.HITM", IAP_EVENT_04H_20H) \ __PMC_EV_ALIAS("MEM_UOPS_RETIRED.ALL_LOADS", IAP_EVENT_04H_40H) \ __PMC_EV_ALIAS("MEM_UOP_RETIRED.ALL_STORES", IAP_EVENT_04H_80H) \ __PMC_EV_ALIAS("PAGE_WALKS.D_SIDE_CYCLES", IAP_EVENT_05H_01H) \ __PMC_EV_ALIAS("PAGE_WALKS.I_SIDE_CYCLES", IAP_EVENT_05H_02H) \ __PMC_EV_ALIAS("PAGE_WALKS.WALKS", IAP_EVENT_05H_03H) \ __PMC_EV_ALIAS("LONGEST_LAT_CACHE.MISS", IAP_EVENT_2EH_41H) \ __PMC_EV_ALIAS("LONGEST_LAT_CACHE.REFERENCE", IAP_EVENT_2EH_4FH) \ __PMC_EV_ALIAS("L2_REJECT_XQ.ALL", IAP_EVENT_30H_00H) \ __PMC_EV_ALIAS("CORE_REJECT_L2Q.ALL", IAP_EVENT_31H_00H) \ __PMC_EV_ALIAS("CPU_CLK_UNHALTED.CORE_P", IAP_EVENT_3CH_00H) \ __PMC_EV_ALIAS("CPU_CLK_UNHALTED.REF_P", IAP_EVENT_3CH_01H) \ __PMC_EV_ALIAS("ICACHE.HIT", IAP_EVENT_80H_01H) \ __PMC_EV_ALIAS("ICACHE.MISSES", IAP_EVENT_80H_02H) \ __PMC_EV_ALIAS("ICACHE.ACCESSES", IAP_EVENT_80H_03H) \ __PMC_EV_ALIAS("NIP_STALL.ICACHE_MISS", IAP_EVENT_B6H_04H) \ __PMC_EV_ALIAS("OFFCORE_RESPONSE_0", IAP_EVENT_B7H_01H) \ __PMC_EV_ALIAS("OFFCORE_RESPONSE_1", IAP_EVENT_B7H_02H) \ __PMC_EV_ALIAS("INST_RETIRED.ANY_P", IAP_EVENT_C0H_00H) \ __PMC_EV_ALIAS("UOPS_RETIRED.MS", IAP_EVENT_C2H_01H) \ __PMC_EV_ALIAS("UOPS_RETIRED.ALL", IAP_EVENT_C2H_10H) \ __PMC_EV_ALIAS("MACHINE_CLEARS.SMC", IAP_EVENT_C3H_01H) \ __PMC_EV_ALIAS("MACHINE_CLEARS.MEMORY_ORDERING", IAP_EVENT_C3H_02H) \ __PMC_EV_ALIAS("MACHINE_CLEARS.FP_ASSIST", IAP_EVENT_C3H_04H) \ __PMC_EV_ALIAS("MACHINE_CLEARS.ALL", IAP_EVENT_C3H_08H) \ __PMC_EV_ALIAS("BR_INST_RETIRED.ALL_BRANCHES", IAP_EVENT_C4H_00H) \ __PMC_EV_ALIAS("BR_INST_RETIRED.JCC", IAP_EVENT_C4H_7EH) \ __PMC_EV_ALIAS("BR_INST_RETIRED.FAR_BRANCH", IAP_EVENT_C4H_BFH) \ __PMC_EV_ALIAS("BR_INST_RETIRED.NON_RETURN_IND", IAP_EVENT_C4H_EBH) \ __PMC_EV_ALIAS("BR_INST_RETIRED.RETURN", IAP_EVENT_C4H_F7H) \ __PMC_EV_ALIAS("BR_INST_RETIRED.CALL", IAP_EVENT_C4H_F9H) \ __PMC_EV_ALIAS("BR_INST_RETIRED.IND_CALL", IAP_EVENT_C4H_FBH) \ __PMC_EV_ALIAS("BR_INST_RETIRED.REL_CALL", IAP_EVENT_C4H_FDH) \ __PMC_EV_ALIAS("BR_INST_RETIRED.TAKEN_JCC", IAP_EVENT_C4H_FEH) \ __PMC_EV_ALIAS("BR_MISP_RETIRED.ALL_BRANCHES", IAP_EVENT_C5H_00H) \ __PMC_EV_ALIAS("BR_MISP_RETIRED.JCC", IAP_EVENT_C5H_7EH) \ __PMC_EV_ALIAS("BR_MISP_RETIRED.FAR", IAP_EVENT_C5H_BFH) \ __PMC_EV_ALIAS("BR_MISP_RETIRED.NON_RETURN_IND", IAP_EVENT_C5H_EBH) \ __PMC_EV_ALIAS("BR_MISP_RETIRED.RETURN", IAP_EVENT_C5H_F7H) \ __PMC_EV_ALIAS("BR_MISP_RETIRED.CALL", IAP_EVENT_C5H_F9H) \ __PMC_EV_ALIAS("BR_MISP_RETIRED.IND_CALL", IAP_EVENT_C5H_FBH) \ __PMC_EV_ALIAS("BR_MISP_RETIRED.REL_CALL", IAP_EVENT_C5H_FDH) \ __PMC_EV_ALIAS("BR_MISP_RETIRED.TAKEN_JCC", IAP_EVENT_C5H_FEH) \ __PMC_EV_ALIAS("NO_ALLOC_CYCLES.ROB_FULL", IAP_EVENT_CAH_01H) \ __PMC_EV_ALIAS("NO_ALLOC_CYCLES.RAT_STALL", IAP_EVENT_CAH_20H) \ __PMC_EV_ALIAS("NO_ALLOC_CYCLES.ALL", IAP_EVENT_CAH_3FH) \ __PMC_EV_ALIAS("NO_ALLOC_CYCLES.NOT_DELIVERED", IAP_EVENT_CAH_50H) \ __PMC_EV_ALIAS("RS_FULL_STALL.MEC", IAP_EVENT_CBH_01H) \ __PMC_EV_ALIAS("RS_FULL_STALL.ALL", IAP_EVENT_CBH_1FH) \ __PMC_EV_ALIAS("CYCLES_DIV_BUSY.ANY", IAP_EVENT_CDH_01H) \ __PMC_EV_ALIAS("BACLEARS.ALL", IAP_EVENT_E6H_01H) \ __PMC_EV_ALIAS("BACLEARS.RETURN", IAP_EVENT_E6H_08H) \ __PMC_EV_ALIAS("BACLEARS.COND", IAP_EVENT_E6H_10H) \ __PMC_EV_ALIAS("MS_DECODED.MS_ENTRY", IAP_EVENT_E7H_01H) /* * Aliases for Broadwell PMC events. */ #define __PMC_EV_ALIAS_BROADWELL() \ __PMC_EV_ALIAS_INTEL_ARCHITECTURAL() /* * Aliases for Core PMC events. */ #define __PMC_EV_ALIAS_CORE() \ __PMC_EV_ALIAS_INTEL_ARCHITECTURAL() \ __PMC_EV_ALIAS("BAClears", IAP_EVENT_E6H_00H) \ __PMC_EV_ALIAS("BTB_Misses", IAP_EVENT_E2H_00H) \ __PMC_EV_ALIAS("Br_BAC_Missp_Exec", IAP_EVENT_8AH_00H) \ __PMC_EV_ALIAS("Br_Bogus", IAP_EVENT_E4H_00H) \ __PMC_EV_ALIAS("Br_Call_Exec", IAP_EVENT_92H_00H) \ __PMC_EV_ALIAS("Br_Call_Missp_Exec", IAP_EVENT_93H_00H) \ __PMC_EV_ALIAS("Br_Cnd_Exec", IAP_EVENT_8BH_00H) \ __PMC_EV_ALIAS("Br_Cnd_Missp_Exec", IAP_EVENT_8CH_00H) \ __PMC_EV_ALIAS("Br_Ind_Call_Exec", IAP_EVENT_94H_00H) \ __PMC_EV_ALIAS("Br_Ind_Exec", IAP_EVENT_8DH_00H) \ __PMC_EV_ALIAS("Br_Ind_Missp_Exec", IAP_EVENT_8EH_00H) \ __PMC_EV_ALIAS("Br_Inst_Exec", IAP_EVENT_88H_00H) \ __PMC_EV_ALIAS("Br_Instr_Decoded", IAP_EVENT_E0H_00H) \ __PMC_EV_ALIAS("Br_Instr_Ret", IAP_EVENT_C4H_00H) \ __PMC_EV_ALIAS("Br_MisPred_Ret", IAP_EVENT_C5H_00H) \ __PMC_EV_ALIAS("Br_MisPred_Taken_Ret", IAP_EVENT_CAH_00H) \ __PMC_EV_ALIAS("Br_Missp_Exec", IAP_EVENT_89H_00H) \ __PMC_EV_ALIAS("Br_Ret_BAC_Missp_Exec", IAP_EVENT_91H_00H) \ __PMC_EV_ALIAS("Br_Ret_Exec", IAP_EVENT_8FH_00H) \ __PMC_EV_ALIAS("Br_Ret_Missp_Exec", IAP_EVENT_90H_00H) \ __PMC_EV_ALIAS("Br_Taken_Ret", IAP_EVENT_C9H_00H) \ __PMC_EV_ALIAS("Bus_BNR_Clocks", IAP_EVENT_61H_00H) \ __PMC_EV_ALIAS("Bus_DRDY_Clocks", IAP_EVENT_62H_00H) \ __PMC_EV_ALIAS("Bus_Data_Rcv", IAP_EVENT_64H_40H) \ __PMC_EV_ALIAS("Bus_Locks_Clocks", IAP_EVENT_63H) \ __PMC_EV_ALIAS("Bus_Not_In_Use", IAP_EVENT_7DH) \ __PMC_EV_ALIAS("Bus_Req_Outstanding", IAP_EVENT_60H) \ __PMC_EV_ALIAS("Bus_Snoop_Stall", IAP_EVENT_7EH_00H) \ __PMC_EV_ALIAS("Bus_Snoops", IAP_EVENT_77H) \ __PMC_EV_ALIAS("Bus_Trans_Any", IAP_EVENT_70H) \ __PMC_EV_ALIAS("Bus_Trans_Brd", IAP_EVENT_65H) \ __PMC_EV_ALIAS("Bus_Trans_Burst", IAP_EVENT_6EH) \ __PMC_EV_ALIAS("Bus_Trans_Def", IAP_EVENT_6DH) \ __PMC_EV_ALIAS("Bus_Trans_IO", IAP_EVENT_6CH) \ __PMC_EV_ALIAS("Bus_Trans_Ifetch", IAP_EVENT_68H) \ __PMC_EV_ALIAS("Bus_Trans_Inval", IAP_EVENT_69H) \ __PMC_EV_ALIAS("Bus_Trans_Mem", IAP_EVENT_6FH) \ __PMC_EV_ALIAS("Bus_Trans_P", IAP_EVENT_6BH) \ __PMC_EV_ALIAS("Bus_Trans_Pwr", IAP_EVENT_6AH) \ __PMC_EV_ALIAS("Bus_Trans_RFO", IAP_EVENT_66H) \ __PMC_EV_ALIAS("Bus_Trans_WB", IAP_EVENT_67H) \ __PMC_EV_ALIAS("Cycles_Div_Busy", IAP_EVENT_14H_00H) \ __PMC_EV_ALIAS("Cycles_Int_Masked", IAP_EVENT_C6H_00H) \ __PMC_EV_ALIAS("Cycles_Int_Pending_Masked", IAP_EVENT_C7H_00H) \ __PMC_EV_ALIAS("DCU_Snoop_To_Share", IAP_EVENT_78H) \ __PMC_EV_ALIAS("DCache_Cache_LD", IAP_EVENT_40H) \ __PMC_EV_ALIAS("DCache_Cache_Lock", IAP_EVENT_42H) \ __PMC_EV_ALIAS("DCache_Cache_ST", IAP_EVENT_41H) \ __PMC_EV_ALIAS("DCache_M_Evict", IAP_EVENT_47H_00H) \ __PMC_EV_ALIAS("DCache_M_Repl", IAP_EVENT_46H_00H) \ __PMC_EV_ALIAS("DCache_Pend_Miss", IAP_EVENT_48H_00H) \ __PMC_EV_ALIAS("DCache_Repl", IAP_EVENT_45H_0FH) \ __PMC_EV_ALIAS("Data_Mem_Cache_Ref", IAP_EVENT_44H_02H) \ __PMC_EV_ALIAS("Data_Mem_Ref", IAP_EVENT_43H_01H) \ __PMC_EV_ALIAS("Dbus_Busy", IAP_EVENT_22H) \ __PMC_EV_ALIAS("Dbus_Busy_Rd", IAP_EVENT_23H) \ __PMC_EV_ALIAS("Div", IAP_EVENT_13H_00H) \ __PMC_EV_ALIAS("Dtlb_Miss", IAP_EVENT_49H_00H) \ __PMC_EV_ALIAS("ESP_Uops", IAP_EVENT_D7H_00H) \ __PMC_EV_ALIAS("EST_Trans", IAP_EVENT_3AH) \ __PMC_EV_ALIAS("FP_Assist", IAP_EVENT_11H_00H) \ __PMC_EV_ALIAS("FP_Comp_Instr_Ret", IAP_EVENT_C1H_00H) \ __PMC_EV_ALIAS("FP_Comps_Op_Exe", IAP_EVENT_10H_00H) \ __PMC_EV_ALIAS("FP_MMX_Trans", IAP_EVENT_CCH_01H) \ __PMC_EV_ALIAS("Fused_Ld_Uops_Ret", IAP_EVENT_DAH_01H) \ __PMC_EV_ALIAS("Fused_St_Uops_Ret", IAP_EVENT_DAH_02H) \ __PMC_EV_ALIAS("Fused_Uops_Ret", IAP_EVENT_DAH_00H) \ __PMC_EV_ALIAS("HW_Int_Rx", IAP_EVENT_C8H_00H) \ __PMC_EV_ALIAS("ICache_Misses", IAP_EVENT_81H_00H) \ __PMC_EV_ALIAS("ICache_Reads", IAP_EVENT_80H_00H) \ __PMC_EV_ALIAS("IFU_Mem_Stall", IAP_EVENT_86H_00H) \ __PMC_EV_ALIAS("ILD_Stall", IAP_EVENT_87H_00H) \ __PMC_EV_ALIAS("ITLB_Misses", IAP_EVENT_85H_00H) \ __PMC_EV_ALIAS("Instr_Decoded", IAP_EVENT_D0H_00H) \ __PMC_EV_ALIAS("Instr_Ret", IAP_EVENT_C0H_00H) \ __PMC_EV_ALIAS("L1_Pref_Req", IAP_EVENT_4FH_00H) \ __PMC_EV_ALIAS("L2_ADS", IAP_EVENT_21H) \ __PMC_EV_ALIAS("L2_IFetch", IAP_EVENT_28H) \ __PMC_EV_ALIAS("L2_LD", IAP_EVENT_29H) \ __PMC_EV_ALIAS("L2_Lines_In", IAP_EVENT_24H) \ __PMC_EV_ALIAS("L2_Lines_Out", IAP_EVENT_26H) \ __PMC_EV_ALIAS("L2_M_Lines_In", IAP_EVENT_25H) \ __PMC_EV_ALIAS("L2_M_Lines_Out", IAP_EVENT_27H) \ __PMC_EV_ALIAS("L2_No_Request_Cycles", IAP_EVENT_32H) \ __PMC_EV_ALIAS("L2_Reject_Cycles", IAP_EVENT_30H) \ __PMC_EV_ALIAS("L2_Rqsts", IAP_EVENT_2EH) \ __PMC_EV_ALIAS("L2_ST", IAP_EVENT_2AH) \ __PMC_EV_ALIAS("LD_Blocks", IAP_EVENT_03H_00H) \ __PMC_EV_ALIAS("LLC_Misses", IAP_EVENT_2EH_41H) \ __PMC_EV_ALIAS("LLC_Reference", IAP_EVENT_2EH_4FH) \ __PMC_EV_ALIAS("MMX_Assist", IAP_EVENT_CDH_00H) \ __PMC_EV_ALIAS("MMX_FP_Trans", IAP_EVENT_CCH_00H) \ __PMC_EV_ALIAS("MMX_Instr_Exec", IAP_EVENT_B0H_00H) \ __PMC_EV_ALIAS("MMX_Instr_Ret", IAP_EVENT_CEH_00H) \ __PMC_EV_ALIAS("Misalign_Mem_Ref", IAP_EVENT_05H_00H) \ __PMC_EV_ALIAS("Mul", IAP_EVENT_12H_00H) \ __PMC_EV_ALIAS("NonHlt_Ref_Cycles", IAP_EVENT_3CH_01H) \ __PMC_EV_ALIAS("Pref_Rqsts_Dn", IAP_EVENT_F8H_00H) \ __PMC_EV_ALIAS("Pref_Rqsts_Up", IAP_EVENT_F0H_00H) \ __PMC_EV_ALIAS("Resource_Stall", IAP_EVENT_A2H_00H) \ __PMC_EV_ALIAS("SD_Drains", IAP_EVENT_04H_00H) \ __PMC_EV_ALIAS("SIMD_FP_DP_P_Comp_Ret", IAP_EVENT_D9H_02H) \ __PMC_EV_ALIAS("SIMD_FP_DP_P_Ret", IAP_EVENT_D8H_02H) \ __PMC_EV_ALIAS("SIMD_FP_DP_S_Comp_Ret", IAP_EVENT_D9H_03H) \ __PMC_EV_ALIAS("SIMD_FP_DP_S_Ret", IAP_EVENT_D8H_03H) \ __PMC_EV_ALIAS("SIMD_FP_SP_P_Comp_Ret", IAP_EVENT_D9H_00H) \ __PMC_EV_ALIAS("SIMD_FP_SP_Ret", IAP_EVENT_D8H_00H) \ __PMC_EV_ALIAS("SIMD_FP_SP_S_Comp_Ret", IAP_EVENT_D9H_01H) \ __PMC_EV_ALIAS("SIMD_FP_SP_S_Ret", IAP_EVENT_D8H_01H) \ __PMC_EV_ALIAS("SIMD_Int_128_Ret", IAP_EVENT_D8H_04H) \ __PMC_EV_ALIAS("SIMD_Int_Pari_Exec", IAP_EVENT_B3H_20H) \ __PMC_EV_ALIAS("SIMD_Int_Pck_Exec", IAP_EVENT_B3H_04H) \ __PMC_EV_ALIAS("SIMD_Int_Plog_Exec", IAP_EVENT_B3H_10H) \ __PMC_EV_ALIAS("SIMD_Int_Pmul_Exec", IAP_EVENT_B3H_01H) \ __PMC_EV_ALIAS("SIMD_Int_Psft_Exec", IAP_EVENT_B3H_02H) \ __PMC_EV_ALIAS("SIMD_Int_Sat_Exec", IAP_EVENT_B1H_00H) \ __PMC_EV_ALIAS("SIMD_Int_Upck_Exec", IAP_EVENT_B3H_08H) \ __PMC_EV_ALIAS("SMC_Detected", IAP_EVENT_C3H_00H) \ __PMC_EV_ALIAS("SSE_NTStores_Miss", IAP_EVENT_4BH_03H) \ __PMC_EV_ALIAS("SSE_NTStores_Ret", IAP_EVENT_07H_03H) \ __PMC_EV_ALIAS("SSE_PrefNta_Miss", IAP_EVENT_4BH_00H) \ __PMC_EV_ALIAS("SSE_PrefNta_Ret", IAP_EVENT_07H_00H) \ __PMC_EV_ALIAS("SSE_PrefT1_Miss", IAP_EVENT_4BH_01H) \ __PMC_EV_ALIAS("SSE_PrefT1_Ret", IAP_EVENT_07H_01H) \ __PMC_EV_ALIAS("SSE_PrefT2_Miss", IAP_EVENT_4BH_02H) \ __PMC_EV_ALIAS("SSE_PrefT2_Ret", IAP_EVENT_07H_02H) \ __PMC_EV_ALIAS("Seg_Reg_Loads", IAP_EVENT_06H_00H) \ __PMC_EV_ALIAS("Serial_Execution_Cycles", IAP_EVENT_3CH_02H) \ __PMC_EV_ALIAS("Thermal_Trip", IAP_EVENT_3BH_C0H) \ __PMC_EV_ALIAS("Unfusion", IAP_EVENT_DBH_00H) \ __PMC_EV_ALIAS("Unhalted_Core_Cycles", IAP_EVENT_3CH_00H) \ __PMC_EV_ALIAS("Uops_Ret", IAP_EVENT_C2H_00H) /* * Aliases for Core2 PMC events. */ #define __PMC_EV_ALIAS_CORE2() \ __PMC_EV_ALIAS_INTEL_ARCHITECTURAL() \ __PMC_EV_ALIAS("BACLEARS", IAP_EVENT_E6H_00H) \ __PMC_EV_ALIAS("BOGUS_BR", IAP_EVENT_E4H_00H) \ __PMC_EV_ALIAS("BR_BAC_MISSP_EXEC", IAP_EVENT_8AH_00H) \ __PMC_EV_ALIAS("BR_CALL_EXEC", IAP_EVENT_92H_00H) \ __PMC_EV_ALIAS("BR_CALL_MISSP_EXEC", IAP_EVENT_93H_00H) \ __PMC_EV_ALIAS("BR_CND_EXEC", IAP_EVENT_8BH_00H) \ __PMC_EV_ALIAS("BR_CND_MISSP_EXEC", IAP_EVENT_8CH_00H) \ __PMC_EV_ALIAS("BR_IND_CALL_EXEC", IAP_EVENT_94H_00H) \ __PMC_EV_ALIAS("BR_IND_EXEC", IAP_EVENT_8DH_00H) \ __PMC_EV_ALIAS("BR_IND_MISSP_EXEC", IAP_EVENT_8EH_00H) \ __PMC_EV_ALIAS("BR_INST_DECODED", IAP_EVENT_E0H_00H) \ __PMC_EV_ALIAS("BR_INST_EXEC", IAP_EVENT_88H_00H) \ __PMC_EV_ALIAS("BR_INST_RETIRED.ANY", IAP_EVENT_C4H_00H) \ __PMC_EV_ALIAS("BR_INST_RETIRED.MISPRED", IAP_EVENT_C5H_00H) \ __PMC_EV_ALIAS("BR_INST_RETIRED.MISPRED_NOT_TAKEN", \ IAP_EVENT_C4H_02H) \ __PMC_EV_ALIAS("BR_INST_RETIRED.MISPRED_TAKEN", \ IAP_EVENT_C4H_08H) \ __PMC_EV_ALIAS("BR_INST_RETIRED.PRED_NOT_TAKEN", \ IAP_EVENT_C4H_01H) \ __PMC_EV_ALIAS("BR_INST_RETIRED.PRED_TAKEN", \ IAP_EVENT_C4H_04H) \ __PMC_EV_ALIAS("BR_INST_RETIRED.TAKEN", IAP_EVENT_C4H_0CH) \ __PMC_EV_ALIAS("BR_MISSP_EXEC", IAP_EVENT_89H_00H) \ __PMC_EV_ALIAS("BR_RET_BAC_MISSP_EXEC", IAP_EVENT_91H_00H) \ __PMC_EV_ALIAS("BR_RET_EXEC", IAP_EVENT_8FH_00H) \ __PMC_EV_ALIAS("BR_RET_MISSP_EXEC", IAP_EVENT_90H_00H) \ __PMC_EV_ALIAS("BR_TKN_BUBBLE_1", IAP_EVENT_97H_00H) \ __PMC_EV_ALIAS("BR_TKN_BUBBLE_2", IAP_EVENT_98H_00H) \ __PMC_EV_ALIAS("BUSQ_EMPTY", IAP_EVENT_7DH) \ __PMC_EV_ALIAS("BUS_BNR_DRV", IAP_EVENT_61H) \ __PMC_EV_ALIAS("BUS_DATA_RCV", IAP_EVENT_64H) \ __PMC_EV_ALIAS("BUS_DRDY_CLOCKS", IAP_EVENT_62H) \ __PMC_EV_ALIAS("BUS_HITM_DRV", IAP_EVENT_7BH) \ __PMC_EV_ALIAS("BUS_HIT_DRV", IAP_EVENT_7AH) \ __PMC_EV_ALIAS("BUS_IO_WAIT", IAP_EVENT_7FH) \ __PMC_EV_ALIAS("BUS_LOCK_CLOCKS", IAP_EVENT_63H) \ __PMC_EV_ALIAS("BUS_REQUEST_OUTSTANDING", \ IAP_EVENT_60H) \ __PMC_EV_ALIAS("BUS_TRANS_ANY", IAP_EVENT_70H) \ __PMC_EV_ALIAS("BUS_TRANS_BRD", IAP_EVENT_65H) \ __PMC_EV_ALIAS("BUS_TRANS_BURST", IAP_EVENT_6EH) \ __PMC_EV_ALIAS("BUS_TRANS_DEF", IAP_EVENT_6DH) \ __PMC_EV_ALIAS("BUS_TRANS_IFETCH", IAP_EVENT_68H) \ __PMC_EV_ALIAS("BUS_TRANS_INVAL", IAP_EVENT_69H) \ __PMC_EV_ALIAS("BUS_TRANS_IO", IAP_EVENT_6CH) \ __PMC_EV_ALIAS("BUS_TRANS_MEM", IAP_EVENT_6FH) \ __PMC_EV_ALIAS("BUS_TRANS_P", IAP_EVENT_6BH) \ __PMC_EV_ALIAS("BUS_TRANS_PWR", IAP_EVENT_6AH) \ __PMC_EV_ALIAS("BUS_TRANS_RFO", IAP_EVENT_66H) \ __PMC_EV_ALIAS("BUS_TRANS_WB", IAP_EVENT_67H) \ __PMC_EV_ALIAS("CMP_SNOOP", IAP_EVENT_78H) \ __PMC_EV_ALIAS("CPU_CLK_UNHALTED.BUS", IAP_EVENT_3CH_01H) \ __PMC_EV_ALIAS("CPU_CLK_UNHALTED.CORE_P", \ IAP_EVENT_3CH_00H) \ __PMC_EV_ALIAS("CPU_CLK_UNHALTED.NO_OTHER", \ IAP_EVENT_3CH_02H) \ __PMC_EV_ALIAS("CYCLES_DIV_BUSY", IAP_EVENT_14H_00H) \ __PMC_EV_ALIAS("CYCLES_INT_MASKED", IAP_EVENT_C6H_01H) \ __PMC_EV_ALIAS("CYCLES_INT_PENDING_AND_MASKED", \ IAP_EVENT_C6H_02H) \ __PMC_EV_ALIAS("CYCLES_L1I_MEM_STALLED", IAP_EVENT_86H_00H) \ __PMC_EV_ALIAS("DELAYED_BYPASS.FP", IAP_EVENT_19H_00H) \ __PMC_EV_ALIAS("DELAYED_BYPASS.LOAD", IAP_EVENT_19H_01H) \ __PMC_EV_ALIAS("DELAYED_BYPASS.SIMD", IAP_EVENT_19H_02H) \ __PMC_EV_ALIAS("DIV", IAP_EVENT_13H_00H) \ __PMC_EV_ALIAS("DTLB_MISSES.ANY", IAP_EVENT_08H_01H) \ __PMC_EV_ALIAS("DTLB_MISSES.L0_MISS_LD", IAP_EVENT_08H_04H) \ __PMC_EV_ALIAS("DTLB_MISSES.MISS_LD", IAP_EVENT_08H_02H) \ __PMC_EV_ALIAS("DTLB_MISSES.MISS_ST", IAP_EVENT_08H_08H) \ __PMC_EV_ALIAS("EIST_TRANS", IAP_EVENT_3AH_00H) \ __PMC_EV_ALIAS("ESP.ADDITIONS", IAP_EVENT_ABH_02H) \ __PMC_EV_ALIAS("ESP.SYNCH", IAP_EVENT_ABH_01H) \ __PMC_EV_ALIAS("EXT_SNOOP", IAP_EVENT_77H) \ __PMC_EV_ALIAS("FP_ASSIST", IAP_EVENT_11H_00H) \ __PMC_EV_ALIAS("FP_COMP_OPS_EXE", IAP_EVENT_10H_00H) \ __PMC_EV_ALIAS("FP_MMX_TRANS_TO_FP", IAP_EVENT_CCH_02H) \ __PMC_EV_ALIAS("FP_MMX_TRANS_TO_MMX", IAP_EVENT_CCH_01H) \ __PMC_EV_ALIAS("HW_INT_RCV", IAP_EVENT_C8H_00H) \ __PMC_EV_ALIAS("IDLE_DURING_DIV", IAP_EVENT_18H_00H) \ __PMC_EV_ALIAS("ILD_STALL", IAP_EVENT_87H_00H) \ __PMC_EV_ALIAS("INST_QUEUE.FULL", IAP_EVENT_83H_02H) \ __PMC_EV_ALIAS("INST_RETIRED.ANY_P", IAP_EVENT_C0H_00H) \ __PMC_EV_ALIAS("INST_RETIRED.LOADS", IAP_EVENT_C0H_01H) \ __PMC_EV_ALIAS("INST_RETIRED.OTHER", IAP_EVENT_C0H_04H) \ __PMC_EV_ALIAS("INST_RETIRED.STORES", IAP_EVENT_C0H_02H) \ __PMC_EV_ALIAS("INST_RETIRED.VM_H", IAP_EVENT_C0H_08H) \ __PMC_EV_ALIAS("ITLB.FLUSH", IAP_EVENT_82H_40H) \ __PMC_EV_ALIAS("ITLB.LARGE_MISS", IAP_EVENT_82H_10H) \ __PMC_EV_ALIAS("ITLB.MISSES", IAP_EVENT_82H_12H) \ __PMC_EV_ALIAS("ITLB.SMALL_MISS", IAP_EVENT_82H_02H) \ __PMC_EV_ALIAS("ITLB_MISS_RETIRED", IAP_EVENT_C9H_00H) \ __PMC_EV_ALIAS("L1D_ALL_CACHE_REF", IAP_EVENT_43H_02H) \ __PMC_EV_ALIAS("L1D_ALL_REF", IAP_EVENT_43H_01H) \ __PMC_EV_ALIAS("L1D_CACHE_LD", IAP_EVENT_40H) \ __PMC_EV_ALIAS("L1D_CACHE_LOCK", IAP_EVENT_42H) \ __PMC_EV_ALIAS("L1D_CACHE_LOCK_DURATION", IAP_EVENT_42H_10H) \ __PMC_EV_ALIAS("L1D_CACHE_ST", IAP_EVENT_41H) \ __PMC_EV_ALIAS("L1D_M_EVICT", IAP_EVENT_47H_00H) \ __PMC_EV_ALIAS("L1D_M_REPL", IAP_EVENT_46H_00H) \ __PMC_EV_ALIAS("L1D_PEND_MISS", IAP_EVENT_48H_00H) \ __PMC_EV_ALIAS("L1D_PREFETCH.REQUESTS", IAP_EVENT_4EH_10H) \ __PMC_EV_ALIAS("L1D_REPL", IAP_EVENT_45H_0FH) \ __PMC_EV_ALIAS("L1D_SPLIT.LOADS", IAP_EVENT_49H_01H) \ __PMC_EV_ALIAS("L1D_SPLIT.STORES", IAP_EVENT_49H_02H) \ __PMC_EV_ALIAS("L1I_MISSES", IAP_EVENT_81H_00H) \ __PMC_EV_ALIAS("L1I_READS", IAP_EVENT_80H_00H) \ __PMC_EV_ALIAS("L2_ADS", IAP_EVENT_21H) \ __PMC_EV_ALIAS("L2_DBUS_BUSY_RD", IAP_EVENT_23H) \ __PMC_EV_ALIAS("L2_IFETCH", IAP_EVENT_28H) \ __PMC_EV_ALIAS("L2_LD", IAP_EVENT_29H) \ __PMC_EV_ALIAS("L2_LINES_IN", IAP_EVENT_24H) \ __PMC_EV_ALIAS("L2_LINES_OUT", IAP_EVENT_26H) \ __PMC_EV_ALIAS("L2_LOCK", IAP_EVENT_2BH) \ __PMC_EV_ALIAS("L2_M_LINES_IN", IAP_EVENT_25H) \ __PMC_EV_ALIAS("L2_M_LINES_OUT", IAP_EVENT_27H) \ __PMC_EV_ALIAS("L2_NO_REQ", IAP_EVENT_32H) \ __PMC_EV_ALIAS("L2_REJECT_BUSQ", IAP_EVENT_30H) \ __PMC_EV_ALIAS("L2_RQSTS", IAP_EVENT_2EH) \ __PMC_EV_ALIAS("L2_RQSTS.SELF.DEMAND.I_STATE", \ IAP_EVENT_2EH_41H) \ __PMC_EV_ALIAS("L2_RQSTS.SELF.DEMAND.MESI", \ IAP_EVENT_2EH_4FH) \ __PMC_EV_ALIAS("L2_ST", IAP_EVENT_2AH) \ __PMC_EV_ALIAS("LOAD_BLOCK.L1D", IAP_EVENT_03H_20H) \ __PMC_EV_ALIAS("LOAD_BLOCK.OVERLAP_STORE", \ IAP_EVENT_03H_08H) \ __PMC_EV_ALIAS("LOAD_BLOCK.STA", IAP_EVENT_03H_02H) \ __PMC_EV_ALIAS("LOAD_BLOCK.STD", IAP_EVENT_03H_04H) \ __PMC_EV_ALIAS("LOAD_BLOCK.UNTIL_RETIRE", IAP_EVENT_03H_10H) \ __PMC_EV_ALIAS("LOAD_HIT_PRE", IAP_EVENT_4CH_00H) \ __PMC_EV_ALIAS("MACHINE_NUKES.MEM_ORDER", IAP_EVENT_C3H_04H) \ __PMC_EV_ALIAS("MACHINE_NUKES.SMC", IAP_EVENT_C3H_01H) \ __PMC_EV_ALIAS("MACRO_INSTS.CISC_DECODED", IAP_EVENT_AAH_08H) \ __PMC_EV_ALIAS("MACRO_INSTS.DECODED", IAP_EVENT_AAH_01H) \ __PMC_EV_ALIAS("MEMORY_DISAMBIGUATION.RESET", \ IAP_EVENT_09H_01H) \ __PMC_EV_ALIAS("MEMORY_DISAMBIGUATION.SUCCESS", \ IAP_EVENT_09H_02H) \ __PMC_EV_ALIAS("MEM_LOAD_RETIRED.DTLB_MISS", \ IAP_EVENT_CBH_10H) \ __PMC_EV_ALIAS("MEM_LOAD_RETIRED.L1D_LINE_MISS", \ IAP_EVENT_CBH_02H) \ __PMC_EV_ALIAS("MEM_LOAD_RETIRED.L1D_MISS", \ IAP_EVENT_CBH_01H) \ __PMC_EV_ALIAS("MEM_LOAD_RETIRED.L2_LINE_MISS", \ IAP_EVENT_CBH_08H) \ __PMC_EV_ALIAS("MEM_LOAD_RETIRED.L2_MISS", \ IAP_EVENT_CBH_04H) \ __PMC_EV_ALIAS("MUL", IAP_EVENT_12H_00H) \ __PMC_EV_ALIAS("PAGE_WALKS.COUNT", IAP_EVENT_0CH_01H) \ __PMC_EV_ALIAS("PAGE_WALKS.CYCLES", IAP_EVENT_0CH_02H) \ __PMC_EV_ALIAS("PREF_RQSTS_DN", IAP_EVENT_F8H_00H) \ __PMC_EV_ALIAS("PREF_RQSTS_UP", IAP_EVENT_F0H_00H) \ __PMC_EV_ALIAS("RAT_STALLS.ANY", IAP_EVENT_D2H_0FH) \ __PMC_EV_ALIAS("RAT_STALLS.FLAGS", IAP_EVENT_D2H_04H) \ __PMC_EV_ALIAS("RAT_STALLS.FPSW", IAP_EVENT_D2H_08H) \ __PMC_EV_ALIAS("RAT_STALLS.OTHER_SERIALIZATION_STALLS", \ IAP_EVENT_D2H_10H) \ __PMC_EV_ALIAS("RAT_STALLS.PARTIAL_CYCLES", \ IAP_EVENT_D2H_02H) \ __PMC_EV_ALIAS("RAT_STALLS.ROB_READ_PORT", \ IAP_EVENT_D2H_01H) \ __PMC_EV_ALIAS("RESOURCE_STALLS.ANY", IAP_EVENT_DCH_1FH) \ __PMC_EV_ALIAS("RESOURCE_STALLS.BR_MISS_CLEAR", \ IAP_EVENT_DCH_10H) \ __PMC_EV_ALIAS("RESOURCE_STALLS.FPCW", IAP_EVENT_DCH_08H) \ __PMC_EV_ALIAS("RESOURCE_STALLS.LD_ST", IAP_EVENT_DCH_04H) \ __PMC_EV_ALIAS("RESOURCE_STALLS.ROB_FULL", \ IAP_EVENT_DCH_01H) \ __PMC_EV_ALIAS("RESOURCE_STALLS.RS_FULL", IAP_EVENT_DCH_02H) \ __PMC_EV_ALIAS("RS_UOPS_DISPATCHED", IAP_EVENT_A0H_00H) \ __PMC_EV_ALIAS("RS_UOPS_DISPATCHED.PORT0", IAP_EVENT_A1H_01H) \ __PMC_EV_ALIAS("RS_UOPS_DISPATCHED.PORT1", IAP_EVENT_A1H_02H) \ __PMC_EV_ALIAS("RS_UOPS_DISPATCHED.PORT2", IAP_EVENT_A1H_04H) \ __PMC_EV_ALIAS("RS_UOPS_DISPATCHED.PORT3", IAP_EVENT_A1H_08H) \ __PMC_EV_ALIAS("RS_UOPS_DISPATCHED.PORT4", IAP_EVENT_A1H_10H) \ __PMC_EV_ALIAS("RS_UOPS_DISPATCHED.PORT5", IAP_EVENT_A1H_20H) \ __PMC_EV_ALIAS("SB_DRAIN_CYCLES", IAP_EVENT_04H_01H) \ __PMC_EV_ALIAS("SEGMENT_REG_LOADS", IAP_EVENT_06H_00H) \ __PMC_EV_ALIAS("SEG_REG_RENAMES.ANY", IAP_EVENT_D5H_0FH) \ __PMC_EV_ALIAS("SEG_REG_RENAMES.DS", IAP_EVENT_D5H_02H) \ __PMC_EV_ALIAS("SEG_REG_RENAMES.ES", IAP_EVENT_D5H_01H) \ __PMC_EV_ALIAS("SEG_REG_RENAMES.FS", IAP_EVENT_D5H_04H) \ __PMC_EV_ALIAS("SEG_REG_RENAMES.GS", IAP_EVENT_D5H_08H) \ __PMC_EV_ALIAS("SEG_RENAME_STALLS.ANY", IAP_EVENT_D4H_0FH) \ __PMC_EV_ALIAS("SEG_RENAME_STALLS.DS", IAP_EVENT_D4H_02H) \ __PMC_EV_ALIAS("SEG_RENAME_STALLS.ES", IAP_EVENT_D4H_01H) \ __PMC_EV_ALIAS("SEG_RENAME_STALLS.FS", IAP_EVENT_D4H_04H) \ __PMC_EV_ALIAS("SEG_RENAME_STALLS.GS", IAP_EVENT_D4H_08H) \ __PMC_EV_ALIAS("SIMD_ASSIST", IAP_EVENT_CDH_00H) \ __PMC_EV_ALIAS("SIMD_COMP_INST_RETIRED.PACKED_DOUBLE", \ IAP_EVENT_CAH_04H) \ __PMC_EV_ALIAS("SIMD_COMP_INST_RETIRED.PACKED_SINGLE", \ IAP_EVENT_CAH_01H) \ __PMC_EV_ALIAS("SIMD_COMP_INST_RETIRED.SCALAR_DOUBLE", \ IAP_EVENT_CAH_08H) \ __PMC_EV_ALIAS("SIMD_COMP_INST_RETIRED.SCALAR_SINGLE", \ IAP_EVENT_CAH_02H) \ __PMC_EV_ALIAS("SIMD_INSTR_RETIRED", IAP_EVENT_CEH_00H) \ __PMC_EV_ALIAS("SIMD_INST_RETIRED.ANY", IAP_EVENT_C7H_1FH) \ __PMC_EV_ALIAS("SIMD_INST_RETIRED.PACKED_DOUBLE", \ IAP_EVENT_C7H_04H) \ __PMC_EV_ALIAS("SIMD_INST_RETIRED.PACKED_SINGLE", \ IAP_EVENT_C7H_01H) \ __PMC_EV_ALIAS("SIMD_INST_RETIRED.SCALAR_DOUBLE", \ IAP_EVENT_C7H_08H) \ __PMC_EV_ALIAS("SIMD_INST_RETIRED.SCALAR_SINGLE", \ IAP_EVENT_C7H_02H) \ __PMC_EV_ALIAS("SIMD_INST_RETIRED.VECTOR", IAP_EVENT_C7H_10H) \ __PMC_EV_ALIAS("SIMD_SAT_INSTR_RETIRED", IAP_EVENT_CFH_00H) \ __PMC_EV_ALIAS("SIMD_SAT_UOP_EXEC", IAP_EVENT_B1H_00H) \ __PMC_EV_ALIAS("SIMD_UOPS_EXEC", IAP_EVENT_B0H_00H) \ __PMC_EV_ALIAS("SIMD_UOP_TYPE_EXEC.ARITHMETIC", IAP_EVENT_B3H_20H) \ __PMC_EV_ALIAS("SIMD_UOP_TYPE_EXEC.LOGICAL", IAP_EVENT_B3H_10H) \ __PMC_EV_ALIAS("SIMD_UOP_TYPE_EXEC.MUL", IAP_EVENT_B3H_01H) \ __PMC_EV_ALIAS("SIMD_UOP_TYPE_EXEC.PACK", IAP_EVENT_B3H_04H) \ __PMC_EV_ALIAS("SIMD_UOP_TYPE_EXEC.SHIFT", IAP_EVENT_B3H_02H) \ __PMC_EV_ALIAS("SIMD_UOP_TYPE_EXEC.UNPACK", IAP_EVENT_B3H_08H) \ __PMC_EV_ALIAS("SNOOP_STALL_DRV", IAP_EVENT_7EH) \ __PMC_EV_ALIAS("SSE_PRE_EXEC.L1", IAP_EVENT_07H_01H) \ __PMC_EV_ALIAS("SSE_PRE_EXEC.L2", IAP_EVENT_07H_02H) \ __PMC_EV_ALIAS("SSE_PRE_EXEC.NTA", IAP_EVENT_07H_00H) \ __PMC_EV_ALIAS("SSE_PRE_EXEC.STORES", IAP_EVENT_07H_03H) \ __PMC_EV_ALIAS("SSE_PRE_MISS.L1", IAP_EVENT_4BH_01H) \ __PMC_EV_ALIAS("SSE_PRE_MISS.L2", IAP_EVENT_4BH_02H) \ __PMC_EV_ALIAS("SSE_PRE_MISS.NTA", IAP_EVENT_4BH_00H) \ __PMC_EV_ALIAS("STORE_BLOCK.ORDER", IAP_EVENT_04H_02H) \ __PMC_EV_ALIAS("STORE_BLOCK.SNOOP", IAP_EVENT_04H_08H) \ __PMC_EV_ALIAS("THERMAL_TRIP", IAP_EVENT_3BH_C0H) \ __PMC_EV_ALIAS("UOPS_RETIRED.ANY", IAP_EVENT_C2H_0FH) \ __PMC_EV_ALIAS("UOPS_RETIRED.FUSED", IAP_EVENT_C2H_07H) \ __PMC_EV_ALIAS("UOPS_RETIRED.LD_IND_BR", IAP_EVENT_C2H_01H) \ __PMC_EV_ALIAS("UOPS_RETIRED.MACRO_FUSION", IAP_EVENT_C2H_04H) \ __PMC_EV_ALIAS("UOPS_RETIRED.NON_FUSED", IAP_EVENT_C2H_08H) \ __PMC_EV_ALIAS("UOPS_RETIRED.STD_STA", IAP_EVENT_C2H_02H) \ __PMC_EV_ALIAS("X87_OPS_RETIRED.ANY", IAP_EVENT_C1H_FEH) \ __PMC_EV_ALIAS("X87_OPS_RETIRED.FXCH", IAP_EVENT_C1H_01H) /* * Core i7 and Xeon 5500 events removed between 253669-031US June 2009 * and 253669-040US October 2011. */ #define __PMC_EV_ALIAS_COREI7_OLD() \ __PMC_EV_ALIAS("SB_FORWARD.ANY", IAP_EVENT_02H_01H) \ __PMC_EV_ALIAS("LOAD_BLOCK.STD", IAP_EVENT_03H_01H) \ __PMC_EV_ALIAS("LOAD_BLOCK.ADDRESS_OFFSET", IAP_EVENT_03H_04H) \ __PMC_EV_ALIAS("SB_DRAIN.CYCLES", IAP_EVENT_04H_01H) \ __PMC_EV_ALIAS("MISALIGN_MEM_REF.LOAD", IAP_EVENT_05H_01H) \ __PMC_EV_ALIAS("MISALIGN_MEM_REF.STORE", IAP_EVENT_05H_02H) \ __PMC_EV_ALIAS("MISALIGN_MEM_REF.ANY", IAP_EVENT_05H_03H) \ __PMC_EV_ALIAS("STORE_BLOCKS.NOT_STA", IAP_EVENT_06H_01H) \ __PMC_EV_ALIAS("STORE_BLOCKS.STA", IAP_EVENT_06H_02H) \ __PMC_EV_ALIAS("STORE_BLOCKS.ANY", IAP_EVENT_06H_0FH) \ __PMC_EV_ALIAS("DTLB_LOAD_MISSES.PDP_MISS", IAP_EVENT_08H_40H) \ __PMC_EV_ALIAS("MEMORY_DISAMBIGURATION.RESET", IAP_EVENT_09H_01H) \ __PMC_EV_ALIAS("MEMORY_DISAMBIGURATION.SUCCESS", IAP_EVENT_09H_02H) \ __PMC_EV_ALIAS("MEMORY_DISAMBIGURATION.WATCHDOG", IAP_EVENT_09H_04H) \ __PMC_EV_ALIAS("MEMORY_DISAMBIGURATION.WATCH_CYCLES", IAP_EVENT_09H_08H)\ __PMC_EV_ALIAS("HW_INT.RCV", IAP_EVENT_1DH_01H) \ __PMC_EV_ALIAS("HW_INT.CYCLES_MASKED", IAP_EVENT_1DH_02H) \ __PMC_EV_ALIAS("HW_INT.CYCLES_PENDING_AND_MASKED", IAP_EVENT_1DH_04H) \ __PMC_EV_ALIAS("L2_WRITE.RFO.E_STATE", IAP_EVENT_27H_04H) \ __PMC_EV_ALIAS("UOPS_DECODED.DEC0", IAP_EVENT_3DH_01H) \ __PMC_EV_ALIAS("L1D_CACHE_ST.I_STATE", IAP_EVENT_41H_01H) \ __PMC_EV_ALIAS("L1D_CACHE_ST.MESI", IAP_EVENT_41H_0FH) \ __PMC_EV_ALIAS("L1D_PEND_MISS.LOAD_BUFFERS_FULL", IAP_EVENT_48H_02H) \ __PMC_EV_ALIAS("DTLB_MISSES.PDP_MISS", IAP_EVENT_49H_40H) \ __PMC_EV_ALIAS("SSE_MEM_EXEC.NTA", IAP_EVENT_4BH_01H) \ __PMC_EV_ALIAS("SSE_MEM_EXEC.STREAMING_STORES", IAP_EVENT_4BH_08H) \ __PMC_EV_ALIAS("SFENCE_CYCLES", IAP_EVENT_4DH_01H) \ __PMC_EV_ALIAS("EPT.EPDE_MISS", IAP_EVENT_4FH_02H) \ __PMC_EV_ALIAS("EPT.EPDPE_HIT", IAP_EVENT_4FH_04H) \ __PMC_EV_ALIAS("EPT.EPDPE_MISS", IAP_EVENT_4FH_08H) \ __PMC_EV_ALIAS("OFFCORE_REQUESTS_OUTSTANDING.DEMAND.READ_DATA", \ IAP_EVENT_60H_01H) \ __PMC_EV_ALIAS("OFFCORE_REQUESTS_OUTSTANDING.DEMAND.READ_CODE", \ IAP_EVENT_60H_02H) \ __PMC_EV_ALIAS("OFFCORE_REQUESTS_OUTSTANDING.DEMAND.RFO", \ IAP_EVENT_60H_04H) \ __PMC_EV_ALIAS("OFFCORE_REQUESTS_OUTSTANDING.ANY.READ", \ IAP_EVENT_60H_08H) \ __PMC_EV_ALIAS("IFU_IVC.FULL", IAP_EVENT_81H_01H) \ __PMC_EV_ALIAS("IFU_IVC.L1I_EVICTION", IAP_EVENT_81H_02H) \ __PMC_EV_ALIAS("L1I_OPPORTUNISTIC_HITS", IAP_EVENT_83H_01H) \ __PMC_EV_ALIAS("ITLB_MISSES.WALK_CYCLES", IAP_EVENT_85H_04H) \ __PMC_EV_ALIAS("ITLB_MISSES.PMH_BUSY_CYCLES", IAP_EVENT_85H_04H) \ __PMC_EV_ALIAS("ITLB_MISSES.STLB_HIT", IAP_EVENT_85H_10H) \ __PMC_EV_ALIAS("ITLB_MISSES.PDE_MISS", IAP_EVENT_85H_20H) \ __PMC_EV_ALIAS("ITLB_MISSES.PDP_MISS", IAP_EVENT_85H_40H) \ __PMC_EV_ALIAS("ITLB_MISSES.LARGE_WALK_COMPLETED", IAP_EVENT_85H_80H) \ __PMC_EV_ALIAS("OFFCORE_REQUESTS.DEMAND.READ_DATA", IAP_EVENT_B0H_01H) \ __PMC_EV_ALIAS("OFFCORE_REQUESTS.DEMAND.READ_CODE", IAP_EVENT_B0H_02H) \ __PMC_EV_ALIAS("OFFCORE_REQUESTS.DEMAND.RFO", IAP_EVENT_B0H_04H) \ __PMC_EV_ALIAS("OFFCORE_REQUESTS.ANY.READ", IAP_EVENT_B0H_08H) \ __PMC_EV_ALIAS("OFFCORE_REQUESTS.ANY.RFO", IAP_EVENT_B0H_10H) \ __PMC_EV_ALIAS("OFFCORE_REQUESTS.UNCACHED_MEM", IAP_EVENT_B0H_20H) \ __PMC_EV_ALIAS("OFFCORE_REQUESTS.ANY", IAP_EVENT_B0H_80H) \ __PMC_EV_ALIAS("SNOOPQ_REQUESTS_OUTSTANDING.DATA", IAP_EVENT_B3H_01H) \ __PMC_EV_ALIAS("SNOOPQ_REQUESTS_OUTSTANDING.INVALIDATE", \ IAP_EVENT_B3H_02H) \ __PMC_EV_ALIAS("SNOOPQ_REQUESTS_OUTSTANDING.CODE", IAP_EVENT_B3H_04H) \ __PMC_EV_ALIAS("PIC_ACCESSES.TPR_READS", IAP_EVENT_BAH_01H) \ __PMC_EV_ALIAS("PIC_ACCESSES.TPR_WRITES", IAP_EVENT_BAH_02H) \ __PMC_EV_ALIAS("MACHINE_CLEARS.FUSION_ASSIST", IAP_EVENT_C3H_10H) \ __PMC_EV_ALIAS("BOGUS_BR", IAP_EVENT_E4H_01H) \ __PMC_EV_ALIAS("BPU_CLEARS.ANY", IAP_EVENT_E8H_03H) \ __PMC_EV_ALIAS("L2_HW_PREFETCH.HIT", IAP_EVENT_F3H_01H) \ __PMC_EV_ALIAS("L2_HW_PREFETCH.ALLOC", IAP_EVENT_F3H_02H) \ __PMC_EV_ALIAS("L2_HW_PREFETCH.DATA_TRIGGER", IAP_EVENT_F3H_04H) \ __PMC_EV_ALIAS("L2_HW_PREFETCH.CODE_TRIGGER", IAP_EVENT_F3H_08H) \ __PMC_EV_ALIAS("L2_HW_PREFETCH.DCA_TRIGGER", IAP_EVENT_F3H_10H) \ __PMC_EV_ALIAS("L2_HW_PREFETCH.KICK_START", IAP_EVENT_F3H_20H) \ __PMC_EV_ALIAS("SQ_MISC.PROMOTION", IAP_EVENT_F4H_01H) \ __PMC_EV_ALIAS("SQ_MISC.PROMOTION_POST_GO", IAP_EVENT_F4H_02H) \ __PMC_EV_ALIAS("SQ_MISC.LRU_HINTS", IAP_EVENT_F4H_04H) \ __PMC_EV_ALIAS("SQ_MISC.FILL_DROPPED", IAP_EVENT_F4H_08H) \ __PMC_EV_ALIAS("SEGMENT_REG_LOADS", IAP_EVENT_F8H_01H) /* * Aliases for Core i7 and Xeon 5500 PMC events (253669-033US December 2009) */ #define __PMC_EV_ALIAS_COREI7() \ __PMC_EV_ALIAS_INTEL_ARCHITECTURAL() \ __PMC_EV_ALIAS("SB_DRAIN.ANY", IAP_EVENT_04H_07H) \ __PMC_EV_ALIAS("STORE_BLOCKS.AT_RET", IAP_EVENT_06H_04H) \ __PMC_EV_ALIAS("STORE_BLOCKS.L1D_BLOCK", IAP_EVENT_06H_08H) \ __PMC_EV_ALIAS("PARTIAL_ADDRESS_ALIAS", IAP_EVENT_07H_01H) \ __PMC_EV_ALIAS("DTLB_LOAD_MISSES.ANY", IAP_EVENT_08H_01H) \ __PMC_EV_ALIAS("DTLB_LOAD_MISSES.WALK_COMPLETED", IAP_EVENT_08H_02H) \ __PMC_EV_ALIAS("DTLB_LOAD_MISSES.STLB_HIT", IAP_EVENT_08H_10H) \ __PMC_EV_ALIAS("DTLB_LOAD_MISSES.PDE_MISS", IAP_EVENT_08H_20H) \ __PMC_EV_ALIAS("DTLB_LOAD_MISSES.LARGE_WALK_COMPLETED", \ IAP_EVENT_08H_80H) \ __PMC_EV_ALIAS("MEM_INST_RETIRED.LOADS", IAP_EVENT_0BH_01H) \ __PMC_EV_ALIAS("MEM_INST_RETIRED.STORES", IAP_EVENT_0BH_02H) \ __PMC_EV_ALIAS("MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD", \ IAP_EVENT_0BH_10H) \ __PMC_EV_ALIAS("MEM_STORE_RETIRED.DTLB_MISS", IAP_EVENT_0CH_01H) \ __PMC_EV_ALIAS("UOPS_ISSUED.ANY", IAP_EVENT_0EH_01H) \ __PMC_EV_ALIAS("UOPS_ISSUED.STALLED_CYCLES", IAP_EVENT_0EH_01H) \ __PMC_EV_ALIAS("UOPS_ISSUED.FUSED", IAP_EVENT_0EH_02H) \ __PMC_EV_ALIAS("MEM_UNCORE_RETIRED.L3_DATA_MISS_UNKNOWN", \ IAP_EVENT_0FH_01H) \ __PMC_EV_ALIAS("MEM_UNCORE_RETIRED.OTHER_CORE_L2_HITM", \ IAP_EVENT_0FH_02H) \ __PMC_EV_ALIAS("MEM_UNCORE_RETIRED.REMOTE_CACHE_LOCAL_HOME_HIT", \ IAP_EVENT_0FH_08H) \ __PMC_EV_ALIAS("MEM_UNCORE_RETIRED.REMOTE_DRAM", \ IAP_EVENT_0FH_10H) \ __PMC_EV_ALIAS("MEM_UNCORE_RETIRED.LOCAL_DRAM", IAP_EVENT_0FH_20H) \ __PMC_EV_ALIAS("MEM_UNCORE_RETIRED.UNCACHEABLE", IAP_EVENT_0FH_80H) \ __PMC_EV_ALIAS("FP_COMP_OPS_EXE.X87", IAP_EVENT_10H_01H) \ __PMC_EV_ALIAS("FP_COMP_OPS_EXE.MMX", IAP_EVENT_10H_02H) \ __PMC_EV_ALIAS("FP_COMP_OPS_EXE.SSE_FP", IAP_EVENT_10H_04H) \ __PMC_EV_ALIAS("FP_COMP_OPS_EXE.SSE2_INTEGER", IAP_EVENT_10H_08H) \ __PMC_EV_ALIAS("FP_COMP_OPS_EXE.SSE_FP_PACKED", IAP_EVENT_10H_10H) \ __PMC_EV_ALIAS("FP_COMP_OPS_EXE.SSE_FP_SCALAR", IAP_EVENT_10H_20H) \ __PMC_EV_ALIAS("FP_COMP_OPS_EXE.SSE_SINGLE_PRECISION", \ IAP_EVENT_10H_40H) \ __PMC_EV_ALIAS("FP_COMP_OPS_EXE.SSE_DOUBLE_PRECISION", \ IAP_EVENT_10H_80H) \ __PMC_EV_ALIAS("SIMD_INT_128.PACKED_MPY", IAP_EVENT_12H_01H) \ __PMC_EV_ALIAS("SIMD_INT_128.PACKED_SHIFT", IAP_EVENT_12H_02H) \ __PMC_EV_ALIAS("SIMD_INT_128.PACK", IAP_EVENT_12H_04H) \ __PMC_EV_ALIAS("SIMD_INT_128.UNPACK", IAP_EVENT_12H_08H) \ __PMC_EV_ALIAS("SIMD_INT_128.PACKED_LOGICAL", IAP_EVENT_12H_10H) \ __PMC_EV_ALIAS("SIMD_INT_128.PACKED_ARITH", IAP_EVENT_12H_20H) \ __PMC_EV_ALIAS("SIMD_INT_128.SHUFFLE_MOVE", IAP_EVENT_12H_40H) \ __PMC_EV_ALIAS("LOAD_DISPATCH.RS", IAP_EVENT_13H_01H) \ __PMC_EV_ALIAS("LOAD_DISPATCH.RS_DELAYED", IAP_EVENT_13H_02H) \ __PMC_EV_ALIAS("LOAD_DISPATCH.MOB", IAP_EVENT_13H_04H) \ __PMC_EV_ALIAS("LOAD_DISPATCH.ANY", IAP_EVENT_13H_07H) \ __PMC_EV_ALIAS("ARITH.CYCLES_DIV_BUSY", IAP_EVENT_14H_01H) \ __PMC_EV_ALIAS("ARITH.MUL", IAP_EVENT_14H_02H) \ __PMC_EV_ALIAS("INST_QUEUE_WRITES", IAP_EVENT_17H_01H) \ __PMC_EV_ALIAS("INST_DECODED.DEC0", IAP_EVENT_18H_01H) \ __PMC_EV_ALIAS("TWO_UOP_INSTS_DECODED", IAP_EVENT_19H_01H) \ __PMC_EV_ALIAS("INST_QUEUE_WRITE_CYCLES", IAP_EVENT_1EH_01H) \ __PMC_EV_ALIAS("LSD_OVERFLOW", IAP_EVENT_20H_01H) \ __PMC_EV_ALIAS("L2_RQSTS.LD_HIT", IAP_EVENT_24H_01H) \ __PMC_EV_ALIAS("L2_RQSTS.LD_MISS", IAP_EVENT_24H_02H) \ __PMC_EV_ALIAS("L2_RQSTS.LOADS", IAP_EVENT_24H_03H) \ __PMC_EV_ALIAS("L2_RQSTS.RFO_HIT", IAP_EVENT_24H_04H) \ __PMC_EV_ALIAS("L2_RQSTS.RFO_MISS", IAP_EVENT_24H_08H) \ __PMC_EV_ALIAS("L2_RQSTS.RFOS", IAP_EVENT_24H_0CH) \ __PMC_EV_ALIAS("L2_RQSTS.IFETCH_HIT", IAP_EVENT_24H_10H) \ __PMC_EV_ALIAS("L2_RQSTS.IFETCH_MISS", IAP_EVENT_24H_20H) \ __PMC_EV_ALIAS("L2_RQSTS.IFETCHES", IAP_EVENT_24H_30H) \ __PMC_EV_ALIAS("L2_RQSTS.PREFETCH_HIT", IAP_EVENT_24H_40H) \ __PMC_EV_ALIAS("L2_RQSTS.PREFETCH_MISS", IAP_EVENT_24H_80H) \ __PMC_EV_ALIAS("L2_RQSTS.PREFETCHES", IAP_EVENT_24H_C0H) \ __PMC_EV_ALIAS("L2_RQSTS.MISS", IAP_EVENT_24H_AAH) \ __PMC_EV_ALIAS("L2_RQSTS.REFERENCES", IAP_EVENT_24H_FFH) \ __PMC_EV_ALIAS("L2_DATA_RQSTS.DEMAND.I_STATE", IAP_EVENT_26H_01H) \ __PMC_EV_ALIAS("L2_DATA_RQSTS.DEMAND.S_STATE", IAP_EVENT_26H_02H) \ __PMC_EV_ALIAS("L2_DATA_RQSTS.DEMAND.E_STATE", IAP_EVENT_26H_04H) \ __PMC_EV_ALIAS("L2_DATA_RQSTS.DEMAND.M_STATE", IAP_EVENT_26H_08H) \ __PMC_EV_ALIAS("L2_DATA_RQSTS.DEMAND.MESI", IAP_EVENT_26H_0FH) \ __PMC_EV_ALIAS("L2_DATA_RQSTS.PREFETCH.I_STATE", IAP_EVENT_26H_10H) \ __PMC_EV_ALIAS("L2_DATA_RQSTS.PREFETCH.S_STATE", IAP_EVENT_26H_20H) \ __PMC_EV_ALIAS("L2_DATA_RQSTS.PREFETCH.E_STATE", IAP_EVENT_26H_40H) \ __PMC_EV_ALIAS("L2_DATA_RQSTS.PREFETCH.M_STATE", IAP_EVENT_26H_80H) \ __PMC_EV_ALIAS("L2_DATA_RQSTS.PREFETCH.MESI", IAP_EVENT_26H_F0H) \ __PMC_EV_ALIAS("L2_DATA_RQSTS.ANY", IAP_EVENT_26H_FFH) \ __PMC_EV_ALIAS("L2_WRITE.RFO.I_STATE", IAP_EVENT_27H_01H) \ __PMC_EV_ALIAS("L2_WRITE.RFO.S_STATE", IAP_EVENT_27H_02H) \ __PMC_EV_ALIAS("L2_WRITE.RFO.M_STATE", IAP_EVENT_27H_08H) \ __PMC_EV_ALIAS("L2_WRITE.RFO.HIT", IAP_EVENT_27H_0EH) \ __PMC_EV_ALIAS("L2_WRITE.RFO.MESI", IAP_EVENT_27H_0FH) \ __PMC_EV_ALIAS("L2_WRITE.LOCK.I_STATE", IAP_EVENT_27H_10H) \ __PMC_EV_ALIAS("L2_WRITE.LOCK.S_STATE", IAP_EVENT_27H_20H) \ __PMC_EV_ALIAS("L2_WRITE.LOCK.E_STATE", IAP_EVENT_27H_40H) \ __PMC_EV_ALIAS("L2_WRITE.LOCK.M_STATE", IAP_EVENT_27H_80H) \ __PMC_EV_ALIAS("L2_WRITE.LOCK.HIT", IAP_EVENT_27H_E0H) \ __PMC_EV_ALIAS("L2_WRITE.LOCK.MESI", IAP_EVENT_27H_F0H) \ __PMC_EV_ALIAS("L1D_WB_L2.I_STATE", IAP_EVENT_28H_01H) \ __PMC_EV_ALIAS("L1D_WB_L2.S_STATE", IAP_EVENT_28H_02H) \ __PMC_EV_ALIAS("L1D_WB_L2.E_STATE", IAP_EVENT_28H_04H) \ __PMC_EV_ALIAS("L1D_WB_L2.M_STATE", IAP_EVENT_28H_08H) \ __PMC_EV_ALIAS("L1D_WB_L2.MESI", IAP_EVENT_28H_0FH) \ __PMC_EV_ALIAS("L3_LAT_CACHE.REFERENCE", IAP_EVENT_2EH_4FH) \ __PMC_EV_ALIAS("L3_LAT_CACHE.MISS", IAP_EVENT_2EH_41H) \ __PMC_EV_ALIAS("CPU_CLK_UNHALTED.THREAD_P", IAP_EVENT_3CH_00H) \ __PMC_EV_ALIAS("CPU_CLK_UNHALTED.REF_P", IAP_EVENT_3CH_01H) \ __PMC_EV_ALIAS("L1D_CACHE_LD.I_STATE", IAP_EVENT_40H_01H) \ __PMC_EV_ALIAS("L1D_CACHE_LD.S_STATE", IAP_EVENT_40H_02H) \ __PMC_EV_ALIAS("L1D_CACHE_LD.E_STATE", IAP_EVENT_40H_04H) \ __PMC_EV_ALIAS("L1D_CACHE_LD.M_STATE", IAP_EVENT_40H_08H) \ __PMC_EV_ALIAS("L1D_CACHE_LD.MESI", IAP_EVENT_40H_0FH) \ __PMC_EV_ALIAS("L1D_CACHE_ST.S_STATE", IAP_EVENT_41H_02H) \ __PMC_EV_ALIAS("L1D_CACHE_ST.E_STATE", IAP_EVENT_41H_04H) \ __PMC_EV_ALIAS("L1D_CACHE_ST.M_STATE", IAP_EVENT_41H_08H) \ __PMC_EV_ALIAS("L1D_CACHE_LOCK.HIT", IAP_EVENT_42H_01H) \ __PMC_EV_ALIAS("L1D_CACHE_LOCK.S_STATE", IAP_EVENT_42H_02H) \ __PMC_EV_ALIAS("L1D_CACHE_LOCK.E_STATE", IAP_EVENT_42H_04H) \ __PMC_EV_ALIAS("L1D_CACHE_LOCK.M_STATE", IAP_EVENT_42H_08H) \ __PMC_EV_ALIAS("L1D_ALL_REF.ANY", IAP_EVENT_43H_01H) \ __PMC_EV_ALIAS("L1D_ALL_REF.CACHEABLE", IAP_EVENT_43H_02H) \ __PMC_EV_ALIAS("DTLB_MISSES.ANY", IAP_EVENT_49H_01H) \ __PMC_EV_ALIAS("DTLB_MISSES.WALK_COMPLETED", IAP_EVENT_49H_02H) \ __PMC_EV_ALIAS("DTLB_MISSES.STLB_HIT", IAP_EVENT_49H_10H) \ __PMC_EV_ALIAS("DTLB_MISSES.PDE_MISS", IAP_EVENT_49H_20H) \ __PMC_EV_ALIAS("DTLB_MISSES.LARGE_WALK_COMPLETED", IAP_EVENT_49H_80H) \ __PMC_EV_ALIAS("LOAD_HIT_PRE", IAP_EVENT_4CH_01H) \ __PMC_EV_ALIAS("L1D_PREFETCH.REQUESTS", IAP_EVENT_4EH_01H) \ __PMC_EV_ALIAS("L1D_PREFETCH.MISS", IAP_EVENT_4EH_02H) \ __PMC_EV_ALIAS("L1D_PREFETCH.TRIGGERS", IAP_EVENT_4EH_04H) \ __PMC_EV_ALIAS("L1D.REPL", IAP_EVENT_51H_01H) \ __PMC_EV_ALIAS("L1D.M_REPL", IAP_EVENT_51H_02H) \ __PMC_EV_ALIAS("L1D.M_EVICT", IAP_EVENT_51H_04H) \ __PMC_EV_ALIAS("L1D.M_SNOOP_EVICT", IAP_EVENT_51H_08H) \ __PMC_EV_ALIAS("L1D_CACHE_PREFETCH_LOCK_FB_HIT", IAP_EVENT_52H_01H) \ __PMC_EV_ALIAS("L1D_CACHE_LOCK_FB_HIT", IAP_EVENT_53H_01H) \ __PMC_EV_ALIAS("CACHE_LOCK_CYCLES.L1D_L2", IAP_EVENT_63H_01H) \ __PMC_EV_ALIAS("CACHE_LOCK_CYCLES.L1D", IAP_EVENT_63H_02H) \ __PMC_EV_ALIAS("IO_TRANSACTIONS", IAP_EVENT_6CH_01H) \ __PMC_EV_ALIAS("L1I.HITS", IAP_EVENT_80H_01H) \ __PMC_EV_ALIAS("L1I.MISSES", IAP_EVENT_80H_02H) \ __PMC_EV_ALIAS("L1I.READS", IAP_EVENT_80H_03H) \ __PMC_EV_ALIAS("L1I.CYCLES_STALLED", IAP_EVENT_80H_04H) \ __PMC_EV_ALIAS("LARGE_ITLB.HIT", IAP_EVENT_82H_01H) \ __PMC_EV_ALIAS("ITLB_MISSES.ANY", IAP_EVENT_85H_01H) \ __PMC_EV_ALIAS("ITLB_MISSES.WALK_COMPLETED", IAP_EVENT_85H_02H) \ __PMC_EV_ALIAS("ILD_STALL.LCP", IAP_EVENT_87H_01H) \ __PMC_EV_ALIAS("ILD_STALL.MRU", IAP_EVENT_87H_02H) \ __PMC_EV_ALIAS("ILD_STALL.IQ_FULL", IAP_EVENT_87H_04H) \ __PMC_EV_ALIAS("ILD_STALL.REGEN", IAP_EVENT_87H_08H) \ __PMC_EV_ALIAS("ILD_STALL.ANY", IAP_EVENT_87H_0FH) \ __PMC_EV_ALIAS("BR_INST_EXEC.COND", IAP_EVENT_88H_01H) \ __PMC_EV_ALIAS("BR_INST_EXEC.DIRECT", IAP_EVENT_88H_02H) \ __PMC_EV_ALIAS("BR_INST_EXEC.INDIRECT_NON_CALL", IAP_EVENT_88H_04H) \ __PMC_EV_ALIAS("BR_INST_EXEC.NON_CALLS", IAP_EVENT_88H_07H) \ __PMC_EV_ALIAS("BR_INST_EXEC.RETURN_NEAR", IAP_EVENT_88H_08H) \ __PMC_EV_ALIAS("BR_INST_EXEC.DIRECT_NEAR_CALL", IAP_EVENT_88H_10H) \ __PMC_EV_ALIAS("BR_INST_EXEC.INDIRECT_NEAR_CALL", IAP_EVENT_88H_20H) \ __PMC_EV_ALIAS("BR_INST_EXEC.NEAR_CALLS", IAP_EVENT_88H_30H) \ __PMC_EV_ALIAS("BR_INST_EXEC.TAKEN", IAP_EVENT_88H_40H) \ __PMC_EV_ALIAS("BR_INST_EXEC.ANY", IAP_EVENT_88H_7FH) \ __PMC_EV_ALIAS("BR_MISP_EXEC.COND", IAP_EVENT_89H_01H) \ __PMC_EV_ALIAS("BR_MISP_EXEC.DIRECT", IAP_EVENT_89H_02H) \ __PMC_EV_ALIAS("BR_MISP_EXEC.INDIRECT_NON_CALL", IAP_EVENT_89H_04H) \ __PMC_EV_ALIAS("BR_MISP_EXEC.NON_CALLS", IAP_EVENT_89H_07H) \ __PMC_EV_ALIAS("BR_MISP_EXEC.RETURN_NEAR", IAP_EVENT_89H_08H) \ __PMC_EV_ALIAS("BR_MISP_EXEC.DIRECT_NEAR_CALL", IAP_EVENT_89H_10H) \ __PMC_EV_ALIAS("BR_MISP_EXEC.INDIRECT_NEAR_CALL", IAP_EVENT_89H_20H) \ __PMC_EV_ALIAS("BR_MISP_EXEC.NEAR_CALLS", IAP_EVENT_89H_30H) \ __PMC_EV_ALIAS("BR_MISP_EXEC.TAKEN", IAP_EVENT_89H_40H) \ __PMC_EV_ALIAS("BR_MISP_EXEC.ANY", IAP_EVENT_89H_7FH) \ __PMC_EV_ALIAS("RESOURCE_STALLS.ANY", IAP_EVENT_A2H_01H) \ __PMC_EV_ALIAS("RESOURCE_STALLS.LOAD", IAP_EVENT_A2H_02H) \ __PMC_EV_ALIAS("RESOURCE_STALLS.RS_FULL", IAP_EVENT_A2H_04H) \ __PMC_EV_ALIAS("RESOURCE_STALLS.STORE", IAP_EVENT_A2H_08H) \ __PMC_EV_ALIAS("RESOURCE_STALLS.ROB_FULL", IAP_EVENT_A2H_10H) \ __PMC_EV_ALIAS("RESOURCE_STALLS.FPCW", IAP_EVENT_A2H_20H) \ __PMC_EV_ALIAS("RESOURCE_STALLS.MXCSR", IAP_EVENT_A2H_40H) \ __PMC_EV_ALIAS("RESOURCE_STALLS.OTHER", IAP_EVENT_A2H_80H) \ __PMC_EV_ALIAS("MACRO_INSTS.FUSIONS_DECODED", IAP_EVENT_A6H_01H) \ __PMC_EV_ALIAS("BACLEAR_FORCE_IQ", IAP_EVENT_A7H_01H) \ __PMC_EV_ALIAS("LSD.UOPS", IAP_EVENT_A8H_01H) \ __PMC_EV_ALIAS("ITLB_FLUSH", IAP_EVENT_AEH_01H) \ __PMC_EV_ALIAS("OFFCORE_REQUESTS.L1D_WRITEBACK", IAP_EVENT_B0H_40H) \ __PMC_EV_ALIAS("UOPS_EXECUTED.PORT0", IAP_EVENT_B1H_01H) \ __PMC_EV_ALIAS("UOPS_EXECUTED.PORT1", IAP_EVENT_B1H_02H) \ __PMC_EV_ALIAS("UOPS_EXECUTED.PORT2_CORE", IAP_EVENT_B1H_04H) \ __PMC_EV_ALIAS("UOPS_EXECUTED.PORT3_CORE", IAP_EVENT_B1H_08H) \ __PMC_EV_ALIAS("UOPS_EXECUTED.PORT4_CORE", IAP_EVENT_B1H_10H) \ __PMC_EV_ALIAS("UOPS_EXECUTED.CORE_ACTIVE_CYCLES_NO_PORT5", \ IAP_EVENT_B1H_1FH) \ __PMC_EV_ALIAS("UOPS_EXECUTED.PORT5", IAP_EVENT_B1H_20H) \ __PMC_EV_ALIAS("UOPS_EXECUTED.CORE_ACTIVE_CYCLES", IAP_EVENT_B1H_3FH) \ __PMC_EV_ALIAS("UOPS_EXECUTED.PORT015", IAP_EVENT_B1H_40H) \ __PMC_EV_ALIAS("UOPS_EXECUTED.PORT234", IAP_EVENT_B1H_80H) \ __PMC_EV_ALIAS("OFFCORE_REQUESTS_SQ_FULL", IAP_EVENT_B2H_01H) \ __PMC_EV_ALIAS("OFF_CORE_RESPONSE_0", IAP_EVENT_B7H_01H) \ __PMC_EV_ALIAS("SNOOP_RESPONSE.HIT", IAP_EVENT_B8H_01H) \ __PMC_EV_ALIAS("SNOOP_RESPONSE.HITE", IAP_EVENT_B8H_02H) \ __PMC_EV_ALIAS("SNOOP_RESPONSE.HITM", IAP_EVENT_B8H_04H) \ __PMC_EV_ALIAS("OFF_CORE_RESPONSE_1", IAP_EVENT_BBH_01H) \ __PMC_EV_ALIAS("INST_RETIRED.ANY_P", IAP_EVENT_C0H_01H) \ __PMC_EV_ALIAS("INST_RETIRED.X87", IAP_EVENT_C0H_02H) \ __PMC_EV_ALIAS("INST_RETIRED.MMX", IAP_EVENT_C0H_04H) \ __PMC_EV_ALIAS("UOPS_RETIRED.ANY", IAP_EVENT_C2H_01H) \ __PMC_EV_ALIAS("UOPS_RETIRED.RETIRE_SLOTS", IAP_EVENT_C2H_02H) \ __PMC_EV_ALIAS("UOPS_RETIRED.MACRO_FUSED", IAP_EVENT_C2H_04H) \ __PMC_EV_ALIAS("MACHINE_CLEARS.CYCLES", IAP_EVENT_C3H_01H) \ __PMC_EV_ALIAS("MACHINE_CLEARS.MEM_ORDER", IAP_EVENT_C3H_02H) \ __PMC_EV_ALIAS("MACHINE_CLEARS.SMC", IAP_EVENT_C3H_04H) \ __PMC_EV_ALIAS("BR_INST_RETIRED.ALL_BRANCHES", IAP_EVENT_C4H_00H) \ __PMC_EV_ALIAS("BR_INST_RETIRED.CONDITIONAL", IAP_EVENT_C4H_01H) \ __PMC_EV_ALIAS("BR_INST_RETIRED.NEAR_CALL", IAP_EVENT_C4H_02H) \ __PMC_EV_ALIAS("BR_INST_RETIRED.ALL_BRANCHES", IAP_EVENT_C4H_04H) \ __PMC_EV_ALIAS("BR_MISP_RETIRED.ALL_BRANCHES", IAP_EVENT_C5H_00H) \ __PMC_EV_ALIAS("BR_MISP_RETIRED.NEAR_CALL", IAP_EVENT_C5H_02H) \ __PMC_EV_ALIAS("SSEX_UOPS_RETIRED.PACKED_SINGLE", IAP_EVENT_C7H_01H) \ __PMC_EV_ALIAS("SSEX_UOPS_RETIRED.SCALAR_SINGLE", IAP_EVENT_C7H_02H) \ __PMC_EV_ALIAS("SSEX_UOPS_RETIRED.PACKED_DOUBLE", IAP_EVENT_C7H_04H) \ __PMC_EV_ALIAS("SSEX_UOPS_RETIRED.SCALAR_DOUBLE", IAP_EVENT_C7H_08H) \ __PMC_EV_ALIAS("SSEX_UOPS_RETIRED.VECTOR_INTEGER", IAP_EVENT_C7H_10H) \ __PMC_EV_ALIAS("ITLB_MISS_RETIRED", IAP_EVENT_C8H_20H) \ __PMC_EV_ALIAS("MEM_LOAD_RETIRED.L1D_HIT", IAP_EVENT_CBH_01H) \ __PMC_EV_ALIAS("MEM_LOAD_RETIRED.L2_HIT", IAP_EVENT_CBH_02H) \ __PMC_EV_ALIAS("MEM_LOAD_RETIRED.L3_UNSHARED_HIT", IAP_EVENT_CBH_04H) \ __PMC_EV_ALIAS("MEM_LOAD_RETIRED.OTHER_CORE_L2_HIT_HITM", \ IAP_EVENT_CBH_08H) \ __PMC_EV_ALIAS("MEM_LOAD_RETIRED.L3_MISS", IAP_EVENT_CBH_10H) \ __PMC_EV_ALIAS("MEM_LOAD_RETIRED.HIT_LFB", IAP_EVENT_CBH_40H) \ __PMC_EV_ALIAS("MEM_LOAD_RETIRED.DTLB_MISS", IAP_EVENT_CBH_80H) \ __PMC_EV_ALIAS("FP_MMX_TRANS.TO_FP", IAP_EVENT_CCH_01H) \ __PMC_EV_ALIAS("FP_MMX_TRANS.TO_MMX", IAP_EVENT_CCH_02H) \ __PMC_EV_ALIAS("FP_MMX_TRANS.ANY", IAP_EVENT_CCH_03H) \ __PMC_EV_ALIAS("MACRO_INSTS.DECODED", IAP_EVENT_D0H_01H) \ __PMC_EV_ALIAS("UOPS_DECODED.MS", IAP_EVENT_D1H_02H) \ __PMC_EV_ALIAS("UOPS_DECODED.ESP_FOLDING", IAP_EVENT_D1H_04H) \ __PMC_EV_ALIAS("UOPS_DECODED.ESP_SYNC", IAP_EVENT_D1H_08H) \ __PMC_EV_ALIAS("RAT_STALLS.FLAGS", IAP_EVENT_D2H_01H) \ __PMC_EV_ALIAS("RAT_STALLS.REGISTERS", IAP_EVENT_D2H_02H) \ __PMC_EV_ALIAS("RAT_STALLS.ROB_READ_PORT", IAP_EVENT_D2H_04H) \ __PMC_EV_ALIAS("RAT_STALLS.SCOREBOARD", IAP_EVENT_D2H_08H) \ __PMC_EV_ALIAS("RAT_STALLS.ANY", IAP_EVENT_D2H_0FH) \ __PMC_EV_ALIAS("SEG_RENAME_STALLS", IAP_EVENT_D4H_01H) \ __PMC_EV_ALIAS("ES_REG_RENAMES", IAP_EVENT_D5H_01H) \ __PMC_EV_ALIAS("UOP_UNFUSION", IAP_EVENT_DBH_01H) \ __PMC_EV_ALIAS("BR_INST_DECODED", IAP_EVENT_E0H_01H) \ __PMC_EV_ALIAS("BPU_MISSED_CALL_RET", IAP_EVENT_E5H_01H) \ __PMC_EV_ALIAS("BACLEAR.CLEAR", IAP_EVENT_E6H_01H) \ __PMC_EV_ALIAS("BACLEAR.BAD_TARGET", IAP_EVENT_E6H_02H) \ __PMC_EV_ALIAS("BPU_CLEARS.EARLY", IAP_EVENT_E8H_01H) \ __PMC_EV_ALIAS("BPU_CLEARS.LATE", IAP_EVENT_E8H_02H) \ __PMC_EV_ALIAS("L2_TRANSACTIONS.LOAD", IAP_EVENT_F0H_01H) \ __PMC_EV_ALIAS("L2_TRANSACTIONS.RFO", IAP_EVENT_F0H_02H) \ __PMC_EV_ALIAS("L2_TRANSACTIONS.IFETCH", IAP_EVENT_F0H_04H) \ __PMC_EV_ALIAS("L2_TRANSACTIONS.PREFETCH", IAP_EVENT_F0H_08H) \ __PMC_EV_ALIAS("L2_TRANSACTIONS.L1D_WB", IAP_EVENT_F0H_10H) \ __PMC_EV_ALIAS("L2_TRANSACTIONS.FILL", IAP_EVENT_F0H_20H) \ __PMC_EV_ALIAS("L2_TRANSACTIONS.WB", IAP_EVENT_F0H_40H) \ __PMC_EV_ALIAS("L2_TRANSACTIONS.ANY", IAP_EVENT_F0H_80H) \ __PMC_EV_ALIAS("L2_LINES_IN.S_STATE", IAP_EVENT_F1H_02H) \ __PMC_EV_ALIAS("L2_LINES_IN.E_STATE", IAP_EVENT_F1H_04H) \ __PMC_EV_ALIAS("L2_LINES_IN.ANY", IAP_EVENT_F1H_07H) \ __PMC_EV_ALIAS("L2_LINES_OUT.DEMAND_CLEAN", IAP_EVENT_F2H_01H) \ __PMC_EV_ALIAS("L2_LINES_OUT.DEMAND_DIRTY", IAP_EVENT_F2H_02H) \ __PMC_EV_ALIAS("L2_LINES_OUT.PREFETCH_CLEAN", IAP_EVENT_F2H_04H) \ __PMC_EV_ALIAS("L2_LINES_OUT.PREFETCH_DIRTY", IAP_EVENT_F2H_08H) \ __PMC_EV_ALIAS("L2_LINES_OUT.ANY", IAP_EVENT_F2H_0FH) \ __PMC_EV_ALIAS("SQ_MISC.SPLIT_LOCK", IAP_EVENT_F4H_10H) \ __PMC_EV_ALIAS("SQ_FULL_STALL_CYCLES", IAP_EVENT_F6H_01H) \ __PMC_EV_ALIAS("FP_ASSIST.ALL", IAP_EVENT_F7H_01H) \ __PMC_EV_ALIAS("FP_ASSIST.OUTPUT", IAP_EVENT_F7H_02H) \ __PMC_EV_ALIAS("FP_ASSIST.INPUT", IAP_EVENT_F7H_04H) \ __PMC_EV_ALIAS("SIMD_INT_64.PACKED_MPY", IAP_EVENT_FDH_01H) \ __PMC_EV_ALIAS("SIMD_INT_64.PACKED_SHIFT", IAP_EVENT_FDH_02H) \ __PMC_EV_ALIAS("SIMD_INT_64.PACK", IAP_EVENT_FDH_04H) \ __PMC_EV_ALIAS("SIMD_INT_64.UNPACK", IAP_EVENT_FDH_08H) \ __PMC_EV_ALIAS("SIMD_INT_64.PACKED_LOGICAL", IAP_EVENT_FDH_10H) \ __PMC_EV_ALIAS("SIMD_INT_64.PACKED_ARITH", IAP_EVENT_FDH_20H) \ __PMC_EV_ALIAS("SIMD_INT_64.SHUFFLE_MOVE", IAP_EVENT_FDH_40H) \ __PMC_EV_ALIAS_COREI7_OLD() /* * Aliases for Westmere PMC events (253669-033US December 2009) */ #define __PMC_EV_ALIAS_WESTMERE() \ __PMC_EV_ALIAS_INTEL_ARCHITECTURAL() \ __PMC_EV_ALIAS("LOAD_BLOCK.OVERLAP_STORE", IAP_EVENT_03H_02H) \ __PMC_EV_ALIAS("SB_DRAIN.ANY", IAP_EVENT_04H_07H) \ __PMC_EV_ALIAS("MISALIGN_MEMORY.STORE", IAP_EVENT_05H_02H) \ __PMC_EV_ALIAS("STORE_BLOCKS.AT_RET", IAP_EVENT_06H_04H) \ __PMC_EV_ALIAS("STORE_BLOCKS.L1D_BLOCK", IAP_EVENT_06H_08H) \ __PMC_EV_ALIAS("PARTIAL_ADDRESS_ALIAS", IAP_EVENT_07H_01H) \ __PMC_EV_ALIAS("DTLB_LOAD_MISSES.ANY", IAP_EVENT_08H_01H) \ __PMC_EV_ALIAS("DTLB_LOAD_MISSES.WALK_COMPLETED", IAP_EVENT_08H_02H) \ __PMC_EV_ALIAS("DTLB_LOAD_MISSES.WALK_CYCLES", IAP_EVENT_08H_04H) \ __PMC_EV_ALIAS("DTLB_LOAD_MISSES.STLB_HIT", IAP_EVENT_08H_10H) \ __PMC_EV_ALIAS("DTLB_LOAD_MISSES.PDE_MISS", IAP_EVENT_08H_20H) \ __PMC_EV_ALIAS("MEM_INST_RETIRED.LOADS", IAP_EVENT_0BH_01H) \ __PMC_EV_ALIAS("MEM_INST_RETIRED.STORES", IAP_EVENT_0BH_02H) \ __PMC_EV_ALIAS("MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD", \ IAP_EVENT_0BH_10H) \ __PMC_EV_ALIAS("MEM_STORE_RETIRED.DTLB_MISS", IAP_EVENT_0CH_01H) \ __PMC_EV_ALIAS("UOPS_ISSUED.ANY", IAP_EVENT_0EH_01H) \ __PMC_EV_ALIAS("UOPS_ISSUED.STALLED_CYCLES", IAP_EVENT_0EH_01H) \ __PMC_EV_ALIAS("UOPS_ISSUED.FUSED", IAP_EVENT_0EH_02H) \ __PMC_EV_ALIAS("MEM_UNCORE_RETIRED.LOCAL_HITM", IAP_EVENT_0FH_02H) \ __PMC_EV_ALIAS("MEM_UNCORE_RETIRED.LOCAL_DRAM_AND_REMOTE_CACHE_HIT", \ IAP_EVENT_0FH_08H) \ __PMC_EV_ALIAS("MEM_UNCORE_RETIRED.LOCAL_DRAM", IAP_EVENT_0FH_10H) \ __PMC_EV_ALIAS("MEM_UNCORE_RETIRED.REMOTE_DRAM", IAP_EVENT_0FH_20H) \ __PMC_EV_ALIAS("MEM_UNCORE_RETIRED.UNCACHEABLE", IAP_EVENT_0FH_80H) \ __PMC_EV_ALIAS("FP_COMP_OPS_EXE.X87", IAP_EVENT_10H_01H) \ __PMC_EV_ALIAS("FP_COMP_OPS_EXE.MMX", IAP_EVENT_10H_02H) \ __PMC_EV_ALIAS("FP_COMP_OPS_EXE.SSE_FP", IAP_EVENT_10H_04H) \ __PMC_EV_ALIAS("FP_COMP_OPS_EXE.SSE2_INTEGER", IAP_EVENT_10H_08H) \ __PMC_EV_ALIAS("FP_COMP_OPS_EXE.SSE_FP_PACKED", IAP_EVENT_10H_10H) \ __PMC_EV_ALIAS("FP_COMP_OPS_EXE.SSE_FP_SCALAR", IAP_EVENT_10H_20H) \ __PMC_EV_ALIAS("FP_COMP_OPS_EXE.SSE_SINGLE_PRECISION", \ IAP_EVENT_10H_40H) \ __PMC_EV_ALIAS("FP_COMP_OPS_EXE.SSE_DOUBLE_PRECISION", \ IAP_EVENT_10H_80H) \ __PMC_EV_ALIAS("SIMD_INT_128.PACKED_MPY", IAP_EVENT_12H_01H) \ __PMC_EV_ALIAS("SIMD_INT_128.PACKED_SHIFT", IAP_EVENT_12H_02H) \ __PMC_EV_ALIAS("SIMD_INT_128.PACK", IAP_EVENT_12H_04H) \ __PMC_EV_ALIAS("SIMD_INT_128.UNPACK", IAP_EVENT_12H_08H) \ __PMC_EV_ALIAS("SIMD_INT_128.PACKED_LOGICAL", IAP_EVENT_12H_10H) \ __PMC_EV_ALIAS("SIMD_INT_128.PACKED_ARITH", IAP_EVENT_12H_20H) \ __PMC_EV_ALIAS("SIMD_INT_128.SHUFFLE_MOVE", IAP_EVENT_12H_40H) \ __PMC_EV_ALIAS("LOAD_DISPATCH.RS", IAP_EVENT_13H_01H) \ __PMC_EV_ALIAS("LOAD_DISPATCH.RS_DELAYED", IAP_EVENT_13H_02H) \ __PMC_EV_ALIAS("LOAD_DISPATCH.MOB", IAP_EVENT_13H_04H) \ __PMC_EV_ALIAS("LOAD_DISPATCH.ANY", IAP_EVENT_13H_07H) \ __PMC_EV_ALIAS("ARITH.CYCLES_DIV_BUSY", IAP_EVENT_14H_01H) \ __PMC_EV_ALIAS("ARITH.MUL", IAP_EVENT_14H_02H) \ __PMC_EV_ALIAS("INST_QUEUE_WRITES", IAP_EVENT_17H_01H) \ __PMC_EV_ALIAS("INST_DECODED.DEC0", IAP_EVENT_18H_01H) \ __PMC_EV_ALIAS("TWO_UOP_INSTS_DECODED", IAP_EVENT_19H_01H) \ __PMC_EV_ALIAS("INST_QUEUE_WRITE_CYCLES", IAP_EVENT_1EH_01H) \ __PMC_EV_ALIAS("LSD_OVERFLOW", IAP_EVENT_20H_01H) \ __PMC_EV_ALIAS("L2_RQSTS.LD_HIT", IAP_EVENT_24H_01H) \ __PMC_EV_ALIAS("L2_RQSTS.LD_MISS", IAP_EVENT_24H_02H) \ __PMC_EV_ALIAS("L2_RQSTS.LOADS", IAP_EVENT_24H_03H) \ __PMC_EV_ALIAS("L2_RQSTS.RFO_HIT", IAP_EVENT_24H_04H) \ __PMC_EV_ALIAS("L2_RQSTS.RFO_MISS", IAP_EVENT_24H_08H) \ __PMC_EV_ALIAS("L2_RQSTS.RFOS", IAP_EVENT_24H_0CH) \ __PMC_EV_ALIAS("L2_RQSTS.IFETCH_HIT", IAP_EVENT_24H_10H) \ __PMC_EV_ALIAS("L2_RQSTS.IFETCH_MISS", IAP_EVENT_24H_20H) \ __PMC_EV_ALIAS("L2_RQSTS.IFETCHES", IAP_EVENT_24H_30H) \ __PMC_EV_ALIAS("L2_RQSTS.PREFETCH_HIT", IAP_EVENT_24H_40H) \ __PMC_EV_ALIAS("L2_RQSTS.PREFETCH_MISS", IAP_EVENT_24H_80H) \ __PMC_EV_ALIAS("L2_RQSTS.PREFETCHES", IAP_EVENT_24H_C0H) \ __PMC_EV_ALIAS("L2_RQSTS.MISS", IAP_EVENT_24H_AAH) \ __PMC_EV_ALIAS("L2_RQSTS.REFERENCES", IAP_EVENT_24H_FFH) \ __PMC_EV_ALIAS("L2_DATA_RQSTS.DEMAND.I_STATE", IAP_EVENT_26H_01H) \ __PMC_EV_ALIAS("L2_DATA_RQSTS.DEMAND.S_STATE", IAP_EVENT_26H_02H) \ __PMC_EV_ALIAS("L2_DATA_RQSTS.DEMAND.E_STATE", IAP_EVENT_26H_04H) \ __PMC_EV_ALIAS("L2_DATA_RQSTS.DEMAND.M_STATE", IAP_EVENT_26H_08H) \ __PMC_EV_ALIAS("L2_DATA_RQSTS.DEMAND.MESI", IAP_EVENT_26H_0FH) \ __PMC_EV_ALIAS("L2_DATA_RQSTS.PREFETCH.I_STATE", IAP_EVENT_26H_10H) \ __PMC_EV_ALIAS("L2_DATA_RQSTS.PREFETCH.S_STATE", IAP_EVENT_26H_20H) \ __PMC_EV_ALIAS("L2_DATA_RQSTS.PREFETCH.E_STATE", IAP_EVENT_26H_40H) \ __PMC_EV_ALIAS("L2_DATA_RQSTS.PREFETCH.M_STATE", IAP_EVENT_26H_80H) \ __PMC_EV_ALIAS("L2_DATA_RQSTS.PREFETCH.MESI", IAP_EVENT_26H_F0H) \ __PMC_EV_ALIAS("L2_DATA_RQSTS.ANY", IAP_EVENT_26H_FFH) \ __PMC_EV_ALIAS("L2_WRITE.RFO.I_STATE", IAP_EVENT_27H_01H) \ __PMC_EV_ALIAS("L2_WRITE.RFO.S_STATE", IAP_EVENT_27H_02H) \ __PMC_EV_ALIAS("L2_WRITE.RFO.M_STATE", IAP_EVENT_27H_08H) \ __PMC_EV_ALIAS("L2_WRITE.RFO.HIT", IAP_EVENT_27H_0EH) \ __PMC_EV_ALIAS("L2_WRITE.RFO.MESI", IAP_EVENT_27H_0FH) \ __PMC_EV_ALIAS("L2_WRITE.LOCK.I_STATE", IAP_EVENT_27H_10H) \ __PMC_EV_ALIAS("L2_WRITE.LOCK.S_STATE", IAP_EVENT_27H_20H) \ __PMC_EV_ALIAS("L2_WRITE.LOCK.E_STATE", IAP_EVENT_27H_40H) \ __PMC_EV_ALIAS("L2_WRITE.LOCK.M_STATE", IAP_EVENT_27H_80H) \ __PMC_EV_ALIAS("L2_WRITE.LOCK.HIT", IAP_EVENT_27H_E0H) \ __PMC_EV_ALIAS("L2_WRITE.LOCK.MESI", IAP_EVENT_27H_F0H) \ __PMC_EV_ALIAS("L1D_WB_L2.I_STATE", IAP_EVENT_28H_01H) \ __PMC_EV_ALIAS("L1D_WB_L2.S_STATE", IAP_EVENT_28H_02H) \ __PMC_EV_ALIAS("L1D_WB_L2.E_STATE", IAP_EVENT_28H_04H) \ __PMC_EV_ALIAS("L1D_WB_L2.M_STATE", IAP_EVENT_28H_08H) \ __PMC_EV_ALIAS("L1D_WB_L2.MESI", IAP_EVENT_28H_0FH) \ __PMC_EV_ALIAS("L3_LAT_CACHE.REFERENCE", IAP_EVENT_2EH_02H) \ __PMC_EV_ALIAS("L3_LAT_CACHE.MISS", IAP_EVENT_2EH_01H) \ __PMC_EV_ALIAS("CPU_CLK_UNHALTED.THREAD_P", IAP_EVENT_3CH_00H) \ __PMC_EV_ALIAS("CPU_CLK_UNHALTED.REF_P", IAP_EVENT_3CH_01H) \ __PMC_EV_ALIAS("DTLB_MISSES.ANY", IAP_EVENT_49H_01H) \ __PMC_EV_ALIAS("DTLB_MISSES.WALK_COMPLETED", IAP_EVENT_49H_02H) \ __PMC_EV_ALIAS("DTLB_MISSES.WALK_CYCLES", IAP_EVENT_49H_04H) \ __PMC_EV_ALIAS("DTLB_MISSES.STLB_HIT", IAP_EVENT_49H_10H) \ __PMC_EV_ALIAS("DTLB_MISSES.LARGE_WALK_COMPLETED", IAP_EVENT_49H_80H) \ __PMC_EV_ALIAS("LOAD_HIT_PRE", IAP_EVENT_4CH_01H) \ __PMC_EV_ALIAS("L1D_PREFETCH.REQUESTS", IAP_EVENT_4EH_01H) \ __PMC_EV_ALIAS("L1D_PREFETCH.MISS", IAP_EVENT_4EH_02H) \ __PMC_EV_ALIAS("L1D_PREFETCH.TRIGGERS", IAP_EVENT_4EH_04H) \ __PMC_EV_ALIAS("EPT.WALK_CYCLES", IAP_EVENT_4FH_10H) \ __PMC_EV_ALIAS("L1D.REPL", IAP_EVENT_51H_01H) \ __PMC_EV_ALIAS("L1D.M_REPL", IAP_EVENT_51H_02H) \ __PMC_EV_ALIAS("L1D.M_EVICT", IAP_EVENT_51H_04H) \ __PMC_EV_ALIAS("L1D.M_SNOOP_EVICT", IAP_EVENT_51H_08H) \ __PMC_EV_ALIAS("L1D_CACHE_PREFETCH_LOCK_FB_HIT", IAP_EVENT_52H_01H) \ __PMC_EV_ALIAS("L1D_CACHE_LOCK_FB_HIT", IAP_EVENT_53H_01H) \ __PMC_EV_ALIAS("OFFCORE_REQUESTS_OUTSTANDING.DEMAND.READ_DATA", \ IAP_EVENT_60H_01H) \ __PMC_EV_ALIAS("OFFCORE_REQUESTS_OUTSTANDING.DEMAND.READ_CODE", \ IAP_EVENT_60H_02H) \ __PMC_EV_ALIAS("OFFCORE_REQUESTS_OUTSTANDING.DEMAND.RFO", \ IAP_EVENT_60H_04H) \ __PMC_EV_ALIAS("OFFCORE_REQUESTS_OUTSTANDING.ANY.READ", \ IAP_EVENT_60H_08H) \ __PMC_EV_ALIAS("CACHE_LOCK_CYCLES.L1D_L2", IAP_EVENT_63H_01H) \ __PMC_EV_ALIAS("CACHE_LOCK_CYCLES.L1D", IAP_EVENT_63H_02H) \ __PMC_EV_ALIAS("IO_TRANSACTIONS", IAP_EVENT_6CH_01H) \ __PMC_EV_ALIAS("L1I.HITS", IAP_EVENT_80H_01H) \ __PMC_EV_ALIAS("L1I.MISSES", IAP_EVENT_80H_02H) \ __PMC_EV_ALIAS("L1I.READS", IAP_EVENT_80H_03H) \ __PMC_EV_ALIAS("L1I.CYCLES_STALLED", IAP_EVENT_80H_04H) \ __PMC_EV_ALIAS("LARGE_ITLB.HIT", IAP_EVENT_82H_01H) \ __PMC_EV_ALIAS("ITLB_MISSES.ANY", IAP_EVENT_85H_01H) \ __PMC_EV_ALIAS("ITLB_MISSES.WALK_COMPLETED", IAP_EVENT_85H_02H) \ __PMC_EV_ALIAS("ITLB_MISSES.WALK_CYCLES", IAP_EVENT_85H_04H) \ __PMC_EV_ALIAS("ITLB_MISSES.LARGE_WALK_COMPLETED", IAP_EVENT_85H_80H) \ __PMC_EV_ALIAS("ILD_STALL.LCP", IAP_EVENT_87H_01H) \ __PMC_EV_ALIAS("ILD_STALL.MRU", IAP_EVENT_87H_02H) \ __PMC_EV_ALIAS("ILD_STALL.IQ_FULL", IAP_EVENT_87H_04H) \ __PMC_EV_ALIAS("ILD_STALL.REGEN", IAP_EVENT_87H_08H) \ __PMC_EV_ALIAS("ILD_STALL.ANY", IAP_EVENT_87H_0FH) \ __PMC_EV_ALIAS("BR_INST_EXEC.COND", IAP_EVENT_88H_01H) \ __PMC_EV_ALIAS("BR_INST_EXEC.DIRECT", IAP_EVENT_88H_02H) \ __PMC_EV_ALIAS("BR_INST_EXEC.INDIRECT_NON_CALL", IAP_EVENT_88H_04H) \ __PMC_EV_ALIAS("BR_INST_EXEC.NON_CALLS", IAP_EVENT_88H_07H) \ __PMC_EV_ALIAS("BR_INST_EXEC.RETURN_NEAR", IAP_EVENT_88H_08H) \ __PMC_EV_ALIAS("BR_INST_EXEC.DIRECT_NEAR_CALL", IAP_EVENT_88H_10H) \ __PMC_EV_ALIAS("BR_INST_EXEC.INDIRECT_NEAR_CALL", IAP_EVENT_88H_20H) \ __PMC_EV_ALIAS("BR_INST_EXEC.NEAR_CALLS", IAP_EVENT_88H_30H) \ __PMC_EV_ALIAS("BR_INST_EXEC.TAKEN", IAP_EVENT_88H_40H) \ __PMC_EV_ALIAS("BR_INST_EXEC.ANY", IAP_EVENT_88H_7FH) \ __PMC_EV_ALIAS("BR_MISP_EXEC.COND", IAP_EVENT_89H_01H) \ __PMC_EV_ALIAS("BR_MISP_EXEC.DIRECT", IAP_EVENT_89H_02H) \ __PMC_EV_ALIAS("BR_MISP_EXEC.INDIRECT_NON_CALL", IAP_EVENT_89H_04H) \ __PMC_EV_ALIAS("BR_MISP_EXEC.NON_CALLS", IAP_EVENT_89H_07H) \ __PMC_EV_ALIAS("BR_MISP_EXEC.RETURN_NEAR", IAP_EVENT_89H_08H) \ __PMC_EV_ALIAS("BR_MISP_EXEC.DIRECT_NEAR_CALL", IAP_EVENT_89H_10H) \ __PMC_EV_ALIAS("BR_MISP_EXEC.INDIRECT_NEAR_CALL", IAP_EVENT_89H_20H) \ __PMC_EV_ALIAS("BR_MISP_EXEC.NEAR_CALLS", IAP_EVENT_89H_30H) \ __PMC_EV_ALIAS("BR_MISP_EXEC.TAKEN", IAP_EVENT_89H_40H) \ __PMC_EV_ALIAS("BR_MISP_EXEC.ANY", IAP_EVENT_89H_7FH) \ __PMC_EV_ALIAS("RESOURCE_STALLS.ANY", IAP_EVENT_A2H_01H) \ __PMC_EV_ALIAS("RESOURCE_STALLS.LOAD", IAP_EVENT_A2H_02H) \ __PMC_EV_ALIAS("RESOURCE_STALLS.RS_FULL", IAP_EVENT_A2H_04H) \ __PMC_EV_ALIAS("RESOURCE_STALLS.STORE", IAP_EVENT_A2H_08H) \ __PMC_EV_ALIAS("RESOURCE_STALLS.ROB_FULL", IAP_EVENT_A2H_10H) \ __PMC_EV_ALIAS("RESOURCE_STALLS.FPCW", IAP_EVENT_A2H_20H) \ __PMC_EV_ALIAS("RESOURCE_STALLS.MXCSR", IAP_EVENT_A2H_40H) \ __PMC_EV_ALIAS("RESOURCE_STALLS.OTHER", IAP_EVENT_A2H_80H) \ __PMC_EV_ALIAS("MACRO_INSTS.FUSIONS_DECODED", IAP_EVENT_A6H_01H) \ __PMC_EV_ALIAS("BACLEAR_FORCE_IQ", IAP_EVENT_A7H_01H) \ __PMC_EV_ALIAS("LSD.UOPS", IAP_EVENT_A8H_01H) \ __PMC_EV_ALIAS("ITLB_FLUSH", IAP_EVENT_AEH_01H) \ __PMC_EV_ALIAS("OFFCORE_REQUESTS.DEMAND.READ_DATA", IAP_EVENT_B0H_01H) \ __PMC_EV_ALIAS("OFFCORE_REQUESTS.DEMAND.READ_CODE", IAP_EVENT_B0H_02H) \ __PMC_EV_ALIAS("OFFCORE_REQUESTS.DEMAND.RFO", IAP_EVENT_B0H_04H) \ __PMC_EV_ALIAS("OFFCORE_REQUESTS.ANY.READ", IAP_EVENT_B0H_08H) \ __PMC_EV_ALIAS("OFFCORE_REQUESTS.ANY.RFO", IAP_EVENT_B0H_10H) \ __PMC_EV_ALIAS("OFFCORE_REQUESTS.L1D_WRITEBACK", IAP_EVENT_B0H_40H) \ __PMC_EV_ALIAS("OFFCORE_REQUESTS.ANY", IAP_EVENT_B0H_80H) \ __PMC_EV_ALIAS("UOPS_EXECUTED.PORT0", IAP_EVENT_B1H_01H) \ __PMC_EV_ALIAS("UOPS_EXECUTED.PORT1", IAP_EVENT_B1H_02H) \ __PMC_EV_ALIAS("UOPS_EXECUTED.PORT2_CORE", IAP_EVENT_B1H_04H) \ __PMC_EV_ALIAS("UOPS_EXECUTED.PORT3_CORE", IAP_EVENT_B1H_08H) \ __PMC_EV_ALIAS("UOPS_EXECUTED.PORT4_CORE", IAP_EVENT_B1H_10H) \ __PMC_EV_ALIAS("UOPS_EXECUTED.CORE_ACTIVE_CYCLES_NO_PORT5", \ IAP_EVENT_B1H_1FH) \ __PMC_EV_ALIAS("UOPS_EXECUTED.PORT5", IAP_EVENT_B1H_20H) \ __PMC_EV_ALIAS("UOPS_EXECUTED.CORE_ACTIVE_CYCLES", IAP_EVENT_B1H_3FH) \ __PMC_EV_ALIAS("UOPS_EXECUTED.PORT015", IAP_EVENT_B1H_40H) \ __PMC_EV_ALIAS("UOPS_EXECUTED.PORT234", IAP_EVENT_B1H_80H) \ __PMC_EV_ALIAS("OFFCORE_REQUESTS_SQ_FULL", IAP_EVENT_B2H_01H) \ __PMC_EV_ALIAS("SNOOPQ_REQUESTS_OUTSTANDING.DATA", IAP_EVENT_B3H_01H) \ __PMC_EV_ALIAS("SNOOPQ_REQUESTS_OUTSTANDING.INVALIDATE", \ IAP_EVENT_B3H_02H) \ __PMC_EV_ALIAS("SNOOPQ_REQUESTS_OUTSTANDING.CODE", IAP_EVENT_B3H_04H) \ __PMC_EV_ALIAS("SNOOPQ_REQUESTS.CODE", IAP_EVENT_B4H_01H) \ __PMC_EV_ALIAS("SNOOPQ_REQUESTS.DATA", IAP_EVENT_B4H_02H) \ __PMC_EV_ALIAS("SNOOPQ_REQUESTS.INVALIDATE", IAP_EVENT_B4H_04H) \ __PMC_EV_ALIAS("OFF_CORE_RESPONSE_0", IAP_EVENT_B7H_01H) \ __PMC_EV_ALIAS("SNOOP_RESPONSE.HIT", IAP_EVENT_B8H_01H) \ __PMC_EV_ALIAS("SNOOP_RESPONSE.HITE", IAP_EVENT_B8H_02H) \ __PMC_EV_ALIAS("SNOOP_RESPONSE.HITM", IAP_EVENT_B8H_04H) \ __PMC_EV_ALIAS("OFF_CORE_RESPONSE_1", IAP_EVENT_BBH_01H) \ __PMC_EV_ALIAS("INST_RETIRED.ANY_P", IAP_EVENT_C0H_01H) \ __PMC_EV_ALIAS("INST_RETIRED.X87", IAP_EVENT_C0H_02H) \ __PMC_EV_ALIAS("INST_RETIRED.MMX", IAP_EVENT_C0H_04H) \ __PMC_EV_ALIAS("UOPS_RETIRED.ANY", IAP_EVENT_C2H_01H) \ __PMC_EV_ALIAS("UOPS_RETIRED.RETIRE_SLOTS", IAP_EVENT_C2H_02H) \ __PMC_EV_ALIAS("UOPS_RETIRED.MACRO_FUSED", IAP_EVENT_C2H_04H) \ __PMC_EV_ALIAS("MACHINE_CLEARS.CYCLES", IAP_EVENT_C3H_01H) \ __PMC_EV_ALIAS("MACHINE_CLEARS.MEM_ORDER", IAP_EVENT_C3H_02H) \ __PMC_EV_ALIAS("MACHINE_CLEARS.SMC", IAP_EVENT_C3H_04H) \ __PMC_EV_ALIAS("BR_INST_RETIRED.ANY_P", IAP_EVENT_C4H_00H) \ __PMC_EV_ALIAS("BR_INST_RETIRED.CONDITIONAL", IAP_EVENT_C4H_01H) \ __PMC_EV_ALIAS("BR_INST_RETIRED.NEAR_CALL", IAP_EVENT_C4H_02H) \ __PMC_EV_ALIAS("BR_INST_RETIRED.ALL_BRANCHES", IAP_EVENT_C4H_04H) \ __PMC_EV_ALIAS("BR_MISP_RETIRED.ANY_P", IAP_EVENT_C5H_00H) \ __PMC_EV_ALIAS("BR_MISP_RETIRED.CONDITIONAL", IAP_EVENT_C5H_01H) \ __PMC_EV_ALIAS("BR_MISP_RETIRED.NEAR_CALL", IAP_EVENT_C5H_02H) \ __PMC_EV_ALIAS("BR_MISP_RETIRED.ALL_BRANCHES", IAP_EVENT_C5H_04H) \ __PMC_EV_ALIAS("SSEX_UOPS_RETIRED.PACKED_SINGLE", IAP_EVENT_C7H_01H) \ __PMC_EV_ALIAS("SSEX_UOPS_RETIRED.SCALAR_SINGLE", IAP_EVENT_C7H_02H) \ __PMC_EV_ALIAS("SSEX_UOPS_RETIRED.PACKED_DOUBLE", IAP_EVENT_C7H_04H) \ __PMC_EV_ALIAS("SSEX_UOPS_RETIRED.SCALAR_DOUBLE", IAP_EVENT_C7H_08H) \ __PMC_EV_ALIAS("SSEX_UOPS_RETIRED.VECTOR_INTEGER", IAP_EVENT_C7H_10H) \ __PMC_EV_ALIAS("ITLB_MISS_RETIRED", IAP_EVENT_C8H_20H) \ __PMC_EV_ALIAS("MEM_LOAD_RETIRED.L1D_HIT", IAP_EVENT_CBH_01H) \ __PMC_EV_ALIAS("MEM_LOAD_RETIRED.L2_HIT", IAP_EVENT_CBH_02H) \ __PMC_EV_ALIAS("MEM_LOAD_RETIRED.L3_UNSHARED_HIT", IAP_EVENT_CBH_04H) \ __PMC_EV_ALIAS("MEM_LOAD_RETIRED.OTHER_CORE_L2_HIT_HITM", \ IAP_EVENT_CBH_08H) \ __PMC_EV_ALIAS("MEM_LOAD_RETIRED.L3_MISS", IAP_EVENT_CBH_10H) \ __PMC_EV_ALIAS("MEM_LOAD_RETIRED.HIT_LFB", IAP_EVENT_CBH_40H) \ __PMC_EV_ALIAS("MEM_LOAD_RETIRED.DTLB_MISS", IAP_EVENT_CBH_80H) \ __PMC_EV_ALIAS("FP_MMX_TRANS.TO_FP", IAP_EVENT_CCH_01H) \ __PMC_EV_ALIAS("FP_MMX_TRANS.TO_MMX", IAP_EVENT_CCH_02H) \ __PMC_EV_ALIAS("FP_MMX_TRANS.ANY", IAP_EVENT_CCH_03H) \ __PMC_EV_ALIAS("MACRO_INSTS.DECODED", IAP_EVENT_D0H_01H) \ __PMC_EV_ALIAS("UOPS_DECODED.STALL_CYCLES", IAP_EVENT_D1H_01H) \ __PMC_EV_ALIAS("UOPS_DECODED.MS", IAP_EVENT_D1H_02H) \ __PMC_EV_ALIAS("UOPS_DECODED.ESP_FOLDING", IAP_EVENT_D1H_04H) \ __PMC_EV_ALIAS("UOPS_DECODED.ESP_SYNC", IAP_EVENT_D1H_08H) \ __PMC_EV_ALIAS("RAT_STALLS.FLAGS", IAP_EVENT_D2H_01H) \ __PMC_EV_ALIAS("RAT_STALLS.REGISTERS", IAP_EVENT_D2H_02H) \ __PMC_EV_ALIAS("RAT_STALLS.ROB_READ_PORT", IAP_EVENT_D2H_04H) \ __PMC_EV_ALIAS("RAT_STALLS.SCOREBOARD", IAP_EVENT_D2H_08H) \ __PMC_EV_ALIAS("RAT_STALLS.ANY", IAP_EVENT_D2H_0FH) \ __PMC_EV_ALIAS("SEG_RENAME_STALLS", IAP_EVENT_D4H_01H) \ __PMC_EV_ALIAS("ES_REG_RENAMES", IAP_EVENT_D5H_01H) \ __PMC_EV_ALIAS("UOP_UNFUSION", IAP_EVENT_DBH_01H) \ __PMC_EV_ALIAS("BR_INST_DECODED", IAP_EVENT_E0H_01H) \ __PMC_EV_ALIAS("BPU_MISSED_CALL_RET", IAP_EVENT_E5H_01H) \ __PMC_EV_ALIAS("BACLEAR.CLEAR", IAP_EVENT_E6H_01H) \ __PMC_EV_ALIAS("BACLEAR.BAD_TARGET", IAP_EVENT_E6H_02H) \ __PMC_EV_ALIAS("BPU_CLEARS.EARLY", IAP_EVENT_E8H_01H) \ __PMC_EV_ALIAS("BPU_CLEARS.LATE", IAP_EVENT_E8H_02H) \ __PMC_EV_ALIAS("THREAD_ACTIVE", IAP_EVENT_ECH_01H) \ __PMC_EV_ALIAS("L2_TRANSACTIONS.LOAD", IAP_EVENT_F0H_01H) \ __PMC_EV_ALIAS("L2_TRANSACTIONS.RFO", IAP_EVENT_F0H_02H) \ __PMC_EV_ALIAS("L2_TRANSACTIONS.IFETCH", IAP_EVENT_F0H_04H) \ __PMC_EV_ALIAS("L2_TRANSACTIONS.PREFETCH", IAP_EVENT_F0H_08H) \ __PMC_EV_ALIAS("L2_TRANSACTIONS.L1D_WB", IAP_EVENT_F0H_10H) \ __PMC_EV_ALIAS("L2_TRANSACTIONS.FILL", IAP_EVENT_F0H_20H) \ __PMC_EV_ALIAS("L2_TRANSACTIONS.WB", IAP_EVENT_F0H_40H) \ __PMC_EV_ALIAS("L2_TRANSACTIONS.ANY", IAP_EVENT_F0H_80H) \ __PMC_EV_ALIAS("L2_LINES_IN.S_STATE", IAP_EVENT_F1H_02H) \ __PMC_EV_ALIAS("L2_LINES_IN.E_STATE", IAP_EVENT_F1H_04H) \ __PMC_EV_ALIAS("L2_LINES_IN.ANY", IAP_EVENT_F1H_07H) \ __PMC_EV_ALIAS("L2_LINES_OUT.DEMAND_CLEAN", IAP_EVENT_F2H_01H) \ __PMC_EV_ALIAS("L2_LINES_OUT.DEMAND_DIRTY", IAP_EVENT_F2H_02H) \ __PMC_EV_ALIAS("L2_LINES_OUT.PREFETCH_CLEAN", IAP_EVENT_F2H_04H) \ __PMC_EV_ALIAS("L2_LINES_OUT.PREFETCH_DIRTY", IAP_EVENT_F2H_08H) \ __PMC_EV_ALIAS("L2_LINES_OUT.ANY", IAP_EVENT_F2H_0FH) \ __PMC_EV_ALIAS("SQ_MISC.LRU_HINTS", IAP_EVENT_F4H_04H) \ __PMC_EV_ALIAS("SQ_MISC.SPLIT_LOCK", IAP_EVENT_F4H_10H) \ __PMC_EV_ALIAS("SQ_FULL_STALL_CYCLES", IAP_EVENT_F6H_01H) \ __PMC_EV_ALIAS("FP_ASSIST.ALL", IAP_EVENT_F7H_01H) \ __PMC_EV_ALIAS("FP_ASSIST.OUTPUT", IAP_EVENT_F7H_02H) \ __PMC_EV_ALIAS("FP_ASSIST.INPUT", IAP_EVENT_F7H_04H) \ __PMC_EV_ALIAS("SIMD_INT_64.PACKED_MPY", IAP_EVENT_FDH_01H) \ __PMC_EV_ALIAS("SIMD_INT_64.PACKED_SHIFT", IAP_EVENT_FDH_02H) \ __PMC_EV_ALIAS("SIMD_INT_64.PACK", IAP_EVENT_FDH_04H) \ __PMC_EV_ALIAS("SIMD_INT_64.UNPACK", IAP_EVENT_FDH_08H) \ __PMC_EV_ALIAS("SIMD_INT_64.PACKED_LOGICAL", IAP_EVENT_FDH_10H) \ __PMC_EV_ALIAS("SIMD_INT_64.PACKED_ARITH", IAP_EVENT_FDH_20H) \ __PMC_EV_ALIAS("SIMD_INT_64.SHUFFLE_MOVE", IAP_EVENT_FDH_40H) /* * Aliases for Haswell core PMC events */ #define __PMC_EV_ALIAS_HASWELL_XEON() \ __PMC_EV_ALIAS("LD_BLOCKS.STORE_FORWARD", IAP_EVENT_03H_02H) \ __PMC_EV_ALIAS("LD_BLOCKS.NO_SR", IAP_EVENT_03H_08H) \ __PMC_EV_ALIAS("MISALIGN_MEM_REF.LOADS", IAP_EVENT_05H_01H) \ __PMC_EV_ALIAS("MISALIGN_MEM_REF.STORES", IAP_EVENT_05H_02H) \ __PMC_EV_ALIAS("LD_BLOCKS_PARTIAL.ADDRESS_ALIAS", IAP_EVENT_07H_01H) \ __PMC_EV_ALIAS("DTLB_LOAD_MISSES.MISS_CAUSES_A_WALK", IAP_EVENT_08H_01H)\ __PMC_EV_ALIAS("DTLB_LOAD_MISSES.WALK_COMPLETED_4K", IAP_EVENT_08H_02H) \ __PMC_EV_ALIAS("DTLB_LOAD_MISSES.WALK_COMPLETED_2M_4M", \ IAP_EVENT_08H_04H) \ __PMC_EV_ALIAS("DTLB_LOAD_MISSES.WALK_COMPLETED", IAP_EVENT_08H_0EH) \ __PMC_EV_ALIAS("DTLB_LOAD_MISSES.WALK_DURATION", IAP_EVENT_08H_10H) \ __PMC_EV_ALIAS("DTLB_LOAD_MISSES.STLB_HIT_4K", IAP_EVENT_08H_20H) \ __PMC_EV_ALIAS("DTLB_LOAD_MISSES.STLB_HIT_2M", IAP_EVENT_08H_40H) \ __PMC_EV_ALIAS("DTLB_LOAD_MISSES.STLB_HIT", IAP_EVENT_08H_60H) \ __PMC_EV_ALIAS("DTLB_LOAD_MISSES.PDE_CACHE_MISS", IAP_EVENT_08H_80H) \ __PMC_EV_ALIAS("INT_MISC.RECOVERY_CYCLES", IAP_EVENT_0DH_03H) \ __PMC_EV_ALIAS("UOPS_ISSUED.ANY", IAP_EVENT_0EH_01H) \ __PMC_EV_ALIAS("UOPS_ISSUED.FLAGS_MERGE", IAP_EVENT_0EH_10H) \ __PMC_EV_ALIAS("UOPS_ISSUED.SLOW_LEA", IAP_EVENT_0EH_20H) \ __PMC_EV_ALIAS("UOPS_ISSUED.SINGLE_MUL", IAP_EVENT_0EH_40H) \ __PMC_EV_ALIAS("L2_RQSTS.DEMAND_DATA_RD_MISS", IAP_EVENT_24H_21H) \ __PMC_EV_ALIAS("L2_RQSTS.DEMAND_DATA_RD_HIT", IAP_EVENT_24H_41H) \ __PMC_EV_ALIAS("L2_RQSTS.ALL_DEMAND_DATA_RD", IAP_EVENT_24H_E1H) \ __PMC_EV_ALIAS("L2_RQSTS.RFO_HIT", IAP_EVENT_24H_42H) \ __PMC_EV_ALIAS("L2_RQSTS.RFO_MISS", IAP_EVENT_24H_22H) \ __PMC_EV_ALIAS("L2_RQSTS.ALL_RFO", IAP_EVENT_24H_E2H) \ __PMC_EV_ALIAS("L2_RQSTS.CODE_RD_HIT", IAP_EVENT_24H_44H) \ __PMC_EV_ALIAS("L2_RQSTS.CODE_RD_MISS", IAP_EVENT_24H_24H) \ __PMC_EV_ALIAS("L2_RQSTS.ALL_DEMAND_MISS", IAP_EVENT_24H_27H) \ __PMC_EV_ALIAS("L2_RQSTS.ALL_DEMAND_REFERENCES", IAP_EVENT_24H_E7H) \ __PMC_EV_ALIAS("L2_RQSTS.ALL_CODE_RD", IAP_EVENT_24H_E4H) \ __PMC_EV_ALIAS("L2_RQSTS.L2_PF_HIT", IAP_EVENT_24H_50H) \ __PMC_EV_ALIAS("L2_RQSTS.L2_PF_MISS", IAP_EVENT_24H_30H) \ __PMC_EV_ALIAS("L2_RQSTS.ALL_PF", IAP_EVENT_24H_F8H) \ __PMC_EV_ALIAS("L2_RQSTS.MISS", IAP_EVENT_24H_3FH) \ __PMC_EV_ALIAS("L2_RQSTS.REFERENCES", IAP_EVENT_24H_FFH) \ __PMC_EV_ALIAS("L2_DEMAND_RQSTS.WB_HIT", IAP_EVENT_27H_50H) \ __PMC_EV_ALIAS("LONGEST_LAT_CACHE.REFERENCE", IAP_EVENT_2EH_4FH) \ __PMC_EV_ALIAS("LONGEST_LAT_CACHE.MISS", IAP_EVENT_2EH_41H) \ __PMC_EV_ALIAS("CPU_CLK_UNHALTED.THREAD_P", IAP_EVENT_3CH_00H) \ __PMC_EV_ALIAS("CPU_CLK_THREAD_UNHALTED.REF_XCLK", IAP_EVENT_3CH_01H) \ __PMC_EV_ALIAS("L1D_PEND_MISS.PENDING", IAP_EVENT_48H_01H) \ __PMC_EV_ALIAS("DTLB_STORE_MISSES.MISS_CAUSES_A_WALK", \ IAP_EVENT_49H_01H) \ __PMC_EV_ALIAS("DTLB_STORE_MISSES.WALK_COMPLETED_4K", \ IAP_EVENT_49H_02H) \ __PMC_EV_ALIAS("DTLB_STORE_MISSES.WALK_COMPLETED_2M_4M", \ IAP_EVENT_49H_04H) \ __PMC_EV_ALIAS("DTLB_STORE_MISSES.WALK_COMPLETED", IAP_EVENT_49H_0EH) \ __PMC_EV_ALIAS("DTLB_STORE_MISSES.WALK_DURATION", IAP_EVENT_49H_10H) \ __PMC_EV_ALIAS("DTLB_STORE_MISSES.STLB_HIT_4K", IAP_EVENT_49H_20H) \ __PMC_EV_ALIAS("DTLB_STORE_MISSES.STLB_HIT_2M", IAP_EVENT_49H_40H) \ __PMC_EV_ALIAS("DTLB_STORE_MISSES.STLB_HIT", IAP_EVENT_49H_60H) \ __PMC_EV_ALIAS("DTLB_STORE_MISSES.PDE_CACHE_MISS", IAP_EVENT_49H_80H) \ __PMC_EV_ALIAS("LOAD_HIT_PRE.SW_PF", IAP_EVENT_4CH_01H) \ __PMC_EV_ALIAS("LOAD_HIT_PRE.HW_PF", IAP_EVENT_4CH_02H) \ __PMC_EV_ALIAS("L1D.REPLACEMENT", IAP_EVENT_51H_01H) \ __PMC_EV_ALIAS("MOVE_ELIMINATION.INT_NOT_ELIMINATED", \ IAP_EVENT_58H_04H) \ __PMC_EV_ALIAS("MOVE_ELIMINATION.SMID_NOT_ELIMINATED", \ IAP_EVENT_58H_08H) \ __PMC_EV_ALIAS("MOVE_ELIMINATION.INT_ELIMINATED", IAP_EVENT_58H_01H) \ __PMC_EV_ALIAS("MOVE_ELIMINATION.SMID_ELIMINATED", IAP_EVENT_58H_02H) \ __PMC_EV_ALIAS("CPL_CYCLES.RING0", IAP_EVENT_5CH_01H) \ __PMC_EV_ALIAS("CPL_CYCLES.RING123", IAP_EVENT_5CH_02H) \ __PMC_EV_ALIAS("RS_EVENTS.EMPTY_CYCLES", IAP_EVENT_5EH_01H) \ __PMC_EV_ALIAS("OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD", \ IAP_EVENT_60H_01H) \ __PMC_EV_ALIAS("OFFCORE_REQUESTS_OUTSTANDING.DEMAND_CORE_RD", \ IAP_EVENT_60H_02H) \ __PMC_EV_ALIAS("OFFCORE_REQUESTS_OUTSTANDING.DEMAND_RFO", \ IAP_EVENT_60H_04H) \ __PMC_EV_ALIAS("OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD", \ IAP_EVENT_60H_08H) \ __PMC_EV_ALIAS("LOCK_CYCLES.SPLIT_LOCK_UC_LOCK_DURATION", \ IAP_EVENT_63H_01H) \ __PMC_EV_ALIAS("LOCK_CYCLES.CACHE_LOCK_DURATION", IAP_EVENT_63H_02H) \ __PMC_EV_ALIAS("IDQ.EMPTY", IAP_EVENT_79H_02H) \ __PMC_EV_ALIAS("IDQ.MITE_UOPS", IAP_EVENT_79H_04H) \ __PMC_EV_ALIAS("IDQ.DSB_UOPS", IAP_EVENT_79H_08H) \ __PMC_EV_ALIAS("IDQ.MS_DSB_UOPS", IAP_EVENT_79H_10H) \ __PMC_EV_ALIAS("IDQ.MS_MITE_UOPS", IAP_EVENT_79H_20H) \ __PMC_EV_ALIAS("IDQ.MS_UOPS", IAP_EVENT_79H_30H) \ __PMC_EV_ALIAS("IDQ.ALL_DSB_CYCLES_ANY_UOPS", IAP_EVENT_79H_18H) \ __PMC_EV_ALIAS("IDQ.ALL_DSB_CYCLES_4_UOPS", IAP_EVENT_79H_18H) \ __PMC_EV_ALIAS("IDQ.ALL_MITE_CYCLES_ANY_UOPS", IAP_EVENT_79H_24H) \ __PMC_EV_ALIAS("IDQ.ALL_MITE_CYCLES_4_UOPS", IAP_EVENT_79H_24H) \ __PMC_EV_ALIAS("IDQ.MITE_ALL_UOPS", IAP_EVENT_79H_3CH) \ __PMC_EV_ALIAS("ICACHE.MISSES", IAP_EVENT_80H_02H) \ __PMC_EV_ALIAS("ITLB_MISSES.MISS_CAUSES_A_WALK", IAP_EVENT_85H_01H) \ __PMC_EV_ALIAS("ITLB_MISSES.WALK_COMPLETED_4K", IAP_EVENT_85H_02H) \ __PMC_EV_ALIAS("TLB_MISSES.WALK_COMPLETED_2M_4M", IAP_EVENT_85H_04H) \ __PMC_EV_ALIAS("ITLB_MISSES.WALK_COMPLETED", IAP_EVENT_85H_0EH) \ __PMC_EV_ALIAS("ITLB_MISSES.WALK_DURATION", IAP_EVENT_85H_10H) \ __PMC_EV_ALIAS("ITLB_MISSES.STLB_HIT_4K", IAP_EVENT_85H_20H) \ __PMC_EV_ALIAS("ITLB_MISSES.STLB_HIT_2M", IAP_EVENT_85H_40H) \ __PMC_EV_ALIAS("ITLB_MISSES.STLB_HIT", IAP_EVENT_85H_60H) \ __PMC_EV_ALIAS("ILD_STALL.LCP", IAP_EVENT_87H_01H) \ __PMC_EV_ALIAS("ILD_STALL.IQ_FULL", IAP_EVENT_87H_04H) \ -__PMC_EV_ALIAS("BR_INST_EXEC.COND", IAP_EVENT_88H_01H) \ -__PMC_EV_ALIAS("BR_INST_EXEC.DIRECT_JMP", IAP_EVENT_88H_02H) \ +__PMC_EV_ALIAS("BR_INST_EXEC.NONTAKEN_COND", IAP_EVENT_88H_41H) \ +__PMC_EV_ALIAS("BR_INST_EXEC.TAKEN_COND", IAP_EVENT_88H_81H) \ +__PMC_EV_ALIAS("BR_INST_EXEC.DIRECT_JMP", IAP_EVENT_88H_82H) \ __PMC_EV_ALIAS("BR_INST_EXEC.INDIRECT_JMP_NON_CALL_RET", \ - IAP_EVENT_88H_04H) \ -__PMC_EV_ALIAS("BR_INST_EXEC.RETURN_NEAR", IAP_EVENT_88H_08H) \ -__PMC_EV_ALIAS("BR_INST_EXEC.DIRECT_NEAR_CALL", IAP_EVENT_88H_10H) \ -__PMC_EV_ALIAS("BR_INST_EXEC.INDIRECT_NEAR_CALL", IAP_EVENT_88H_20H) \ -__PMC_EV_ALIAS("BR_INST_EXEC.NONTAKEN", IAP_EVENT_88H_40H) \ -__PMC_EV_ALIAS("BR_INST_EXEC.TAKEN", IAP_EVENT_88H_80H) \ + IAP_EVENT_88H_84H) \ +__PMC_EV_ALIAS("BR_INST_EXEC.RETURN_NEAR", IAP_EVENT_88H_88H) \ +__PMC_EV_ALIAS("BR_INST_EXEC.DIRECT_NEAR_CALL", IAP_EVENT_88H_90H) \ +__PMC_EV_ALIAS("BR_INST_EXEC.INDIRECT_NEAR_CALL", IAP_EVENT_88H_A0H) \ __PMC_EV_ALIAS("BR_INST_EXEC.ALL_BRANCHES", IAP_EVENT_88H_FFH) \ -__PMC_EV_ALIAS("BR_MISP_EXEC.COND", IAP_EVENT_89H_01H) \ +__PMC_EV_ALIAS("BR_MISP_EXEC.NONTAKEN_COND", IAP_EVENT_89H_41H) \ +__PMC_EV_ALIAS("BR_MISP_EXEC.TAKEN_COND", IAP_EVENT_89H_81H) \ __PMC_EV_ALIAS("BR_MISP_EXEC.INDIRECT_JMP_NON_CALL_RET", \ - IAP_EVENT_89H_04H) \ -__PMC_EV_ALIAS("BR_MISP_EXEC.RETURN_NEAR", IAP_EVENT_89H_08H) \ -__PMC_EV_ALIAS("BR_MISP_EXEC.DIRECT_NEAR_CALL", IAP_EVENT_89H_10H) \ -__PMC_EV_ALIAS("BR_MISP_EXEC.INDIRECT_NEAR_CALL", IAP_EVENT_89H_20H) \ -__PMC_EV_ALIAS("BR_MISP_EXEC.NONTAKEN", IAP_EVENT_89H_40H) \ -__PMC_EV_ALIAS("BR_MISP_EXEC.TAKEN", IAP_EVENT_89H_80H) \ + IAP_EVENT_89H_84H) \ +__PMC_EV_ALIAS("BR_MISP_EXEC.RETURN_NEAR", IAP_EVENT_89H_88H) \ +__PMC_EV_ALIAS("BR_MISP_EXEC.DIRECT_NEAR_CALL", IAP_EVENT_89H_90H) \ +__PMC_EV_ALIAS("BR_MISP_EXEC.INDIRECT_NEAR_CALL", IAP_EVENT_89H_A0H) \ __PMC_EV_ALIAS("BR_MISP_EXEC.ALL_BRANCHES", IAP_EVENT_89H_FFH) \ __PMC_EV_ALIAS("IDQ_UOPS_NOT_DELIVERED.CORE", IAP_EVENT_9CH_01H) \ __PMC_EV_ALIAS("UOPS_EXECUTED_PORT.PORT_0", IAP_EVENT_A1H_01H) \ __PMC_EV_ALIAS("UOPS_EXECUTED_PORT.PORT_1", IAP_EVENT_A1H_02H) \ __PMC_EV_ALIAS("UOPS_EXECUTED_PORT.PORT_2", IAP_EVENT_A1H_04H) \ __PMC_EV_ALIAS("UOPS_EXECUTED_PORT.PORT_3", IAP_EVENT_A1H_08H) \ __PMC_EV_ALIAS("UOPS_EXECUTED_PORT.PORT_4", IAP_EVENT_A1H_10H) \ __PMC_EV_ALIAS("UOPS_EXECUTED_PORT.PORT_5", IAP_EVENT_A1H_20H) \ __PMC_EV_ALIAS("UOPS_EXECUTED_PORT.PORT_6", IAP_EVENT_A1H_40H) \ __PMC_EV_ALIAS("UOPS_EXECUTED_PORT.PORT_7", IAP_EVENT_A1H_80H) \ __PMC_EV_ALIAS("RESOURCE_STALLS.ANY", IAP_EVENT_A2H_01H) \ __PMC_EV_ALIAS("RESOURCE_STALLS.RS", IAP_EVENT_A2H_04H) \ __PMC_EV_ALIAS("RESOURCE_STALLS.SB", IAP_EVENT_A2H_08H) \ __PMC_EV_ALIAS("RESOURCE_STALLS.ROB", IAP_EVENT_A2H_10H) \ __PMC_EV_ALIAS("CYCLE_ACTIVITY.CYCLES_L2_PENDING", IAP_EVENT_A3H_01H) \ __PMC_EV_ALIAS("CYCLE_ACTIVITY.CYCLES_LDM_PENDING", IAP_EVENT_A3H_02H) \ __PMC_EV_ALIAS("CYCLE_ACTIVITY.STALLS_L2_PENDING", IAP_EVENT_A3H_05H) \ __PMC_EV_ALIAS("CYCLE_ACTIVITY.CYCLES_L1D_PENDING", IAP_EVENT_A3H_08H) \ __PMC_EV_ALIAS("CYCLE_ACTIVITY.STALLS_L1D_PENDING", IAP_EVENT_A3H_0CH) \ __PMC_EV_ALIAS("LSD.UOPS", IAP_EVENT_A8H_01H) \ __PMC_EV_ALIAS("ITLB.ITLB_FLUSH", IAP_EVENT_AEH_01H) \ __PMC_EV_ALIAS("OFFCORE_REQUESTS.DEMAND_DATA_RD", IAP_EVENT_B0H_01H) \ __PMC_EV_ALIAS("OFFCORE_REQUESTS.DEMAND_CODE_RD", IAP_EVENT_B0H_02H) \ __PMC_EV_ALIAS("OFFCORE_REQUESTS.DEMAND_RFO", IAP_EVENT_B0H_04H) \ __PMC_EV_ALIAS("OFFCORE_REQUESTS.ALL_DATA_RD", IAP_EVENT_B0H_08H) \ __PMC_EV_ALIAS("UOPS_EXECUTED.CORE", IAP_EVENT_B1H_02H) \ __PMC_EV_ALIAS("OFF_CORE_RESPONSE_0", IAP_EVENT_B7H_01H) \ __PMC_EV_ALIAS("OFF_CORE_RESPONSE_1", IAP_EVENT_BBH_01H) \ __PMC_EV_ALIAS("PAGE_WALKER_LOADS.DTLB_L1", IAP_EVENT_BCH_11H) \ __PMC_EV_ALIAS("PAGE_WALKER_LOADS.ITLB_L1", IAP_EVENT_BCH_21H) \ __PMC_EV_ALIAS("PAGE_WALKER_LOADS.DTLB_L2", IAP_EVENT_BCH_12H) \ __PMC_EV_ALIAS("PAGE_WALKER_LOADS.ITLB_L2", IAP_EVENT_BCH_22H) \ __PMC_EV_ALIAS("PAGE_WALKER_LOADS.DTLB_L3", IAP_EVENT_BCH_14H) \ __PMC_EV_ALIAS("PAGE_WALKER_LOADS.ITLB_L3", IAP_EVENT_BCH_24H) \ __PMC_EV_ALIAS("PAGE_WALKER_LOADS.DTLB_MEMORY", IAP_EVENT_BCH_18H) \ __PMC_EV_ALIAS("PAGE_WALKER_LOADS.ITLB_MEMORY", IAP_EVENT_BCH_28H) \ __PMC_EV_ALIAS("TLB_FLUSH.DTLB_THREAD", IAP_EVENT_BDH_01H) \ __PMC_EV_ALIAS("TLB_FLUSH.STLB_ANY", IAP_EVENT_BDH_20H) \ __PMC_EV_ALIAS("INST_RETIRED.ANY_P", IAP_EVENT_C0H_00H) \ __PMC_EV_ALIAS("INST_RETIRED.PREC_DIST", IAP_EVENT_C0H_01H) \ __PMC_EV_ALIAS("OTHER_ASSISTS.AVX_TO_SSE", IAP_EVENT_C1H_08H) \ __PMC_EV_ALIAS("OTHER_ASSISTS.SSE_TO_AVX", IAP_EVENT_C1H_10H) \ __PMC_EV_ALIAS("OTHER_ASSISTS.ANY_WB_ASSIST", IAP_EVENT_C1H_40H) \ __PMC_EV_ALIAS("UOPS_RETIRED.ALL", IAP_EVENT_C2H_01H) \ __PMC_EV_ALIAS("UOPS_RETIRED.RETIRE_SLOTS", IAP_EVENT_C2H_02H) \ __PMC_EV_ALIAS("MACHINE_CLEARS.MEMORY_ORDERING", IAP_EVENT_C3H_02H) \ __PMC_EV_ALIAS("MACHINE_CLEARS.SMC", IAP_EVENT_C3H_04H) \ __PMC_EV_ALIAS("MACHINE_CLEARS.MASKMOV", IAP_EVENT_C3H_20H) \ __PMC_EV_ALIAS("BR_INST_RETIRED.ALL_BRANCHES", IAP_EVENT_C4H_00H) \ __PMC_EV_ALIAS("BR_INST_RETIRED.CONDITIONAL", IAP_EVENT_C4H_01H) \ __PMC_EV_ALIAS("BR_INST_RETIRED.NEAR_CALL", IAP_EVENT_C4H_02H) \ __PMC_EV_ALIAS("BR_INST_RETIRED.ALL_BRANCHES", IAP_EVENT_C4H_04H) \ __PMC_EV_ALIAS("BR_INST_RETIRED.NEAR_RETURN", IAP_EVENT_C4H_08H) \ __PMC_EV_ALIAS("BR_INST_RETIRED.NOT_TAKEN", IAP_EVENT_C4H_10H) \ __PMC_EV_ALIAS("BR_INST_RETIRED.NEAR_TAKEN", IAP_EVENT_C4H_20H) \ __PMC_EV_ALIAS("BR_INST_RETIRED.FAR_BRANCH", IAP_EVENT_C4H_40H) \ __PMC_EV_ALIAS("BR_MISP_RETIRED.ALL_BRANCHES", IAP_EVENT_C5H_00H) \ __PMC_EV_ALIAS("BR_MISP_RETIRED.CONDITIONAL", IAP_EVENT_C5H_01H) \ __PMC_EV_ALIAS("BR_MISP_RETIRED.CONDITIONAL", IAP_EVENT_C5H_04H) \ __PMC_EV_ALIAS("BR_MISP_RETIRED.NEAR_TAKEN", IAP_EVENT_C5H_20H) \ __PMC_EV_ALIAS("FP_ASSIST.X87_OUTPUT", IAP_EVENT_CAH_02H) \ __PMC_EV_ALIAS("FP_ASSIST.X87_INPUT", IAP_EVENT_CAH_04H) \ __PMC_EV_ALIAS("FP_ASSIST.SIMD_OUTPUT", IAP_EVENT_CAH_08H) \ __PMC_EV_ALIAS("FP_ASSIST.SIMD_INPUT", IAP_EVENT_CAH_10H) \ __PMC_EV_ALIAS("FP_ASSIST.ANY", IAP_EVENT_CAH_1EH) \ __PMC_EV_ALIAS("ROB_MISC_EVENTS.LBR_INSERTS", IAP_EVENT_CCH_20H) \ __PMC_EV_ALIAS("MEM_TRANS_RETIRED.LOAD_LATENCY", IAP_EVENT_CDH_01H) \ __PMC_EV_ALIAS("MEM_UOP_RETIRED.LOADS", IAP_EVENT_D0H_01H) \ __PMC_EV_ALIAS("MEM_UOP_RETIRED.STORES", IAP_EVENT_D0H_02H) \ __PMC_EV_ALIAS("MEM_UOP_RETIRED.STLB_MISS", IAP_EVENT_D0H_10H) \ __PMC_EV_ALIAS("MEM_UOP_RETIRED.LOCK", IAP_EVENT_D0H_20H) \ __PMC_EV_ALIAS("MEM_UOP_RETIRED.SPLIT", IAP_EVENT_D0H_40H) \ __PMC_EV_ALIAS("MEM_UOP_RETIRED.SPLIT_LOADS", IAP_EVENT_D0H_41H) \ __PMC_EV_ALIAS("MEM_UOP_RETIRED.SPLIT_STORES", IAP_EVENT_D0H_42H) \ __PMC_EV_ALIAS("MEM_UOP_RETIRED.ALL", IAP_EVENT_D0H_80H) \ __PMC_EV_ALIAS("MEM_LOAD_UOPS_RETIRED.L1_HIT", IAP_EVENT_D1H_01H) \ __PMC_EV_ALIAS("MEM_LOAD_UOPS_RETIRED.L2_HIT", IAP_EVENT_D1H_02H) \ __PMC_EV_ALIAS("MEM_LOAD_UOPS_RETIRED.LLC_HIT", IAP_EVENT_D1H_04H) \ __PMC_EV_ALIAS("MEM_LOAD_UOPS_RETIRED.L1_MISS", IAP_EVENT_D1H_08H) \ __PMC_EV_ALIAS("MEM_LOAD_UOPS_RETIRED.L2_MISS", IAP_EVENT_D1H_10H) \ __PMC_EV_ALIAS("MEM_LOAD_UOPS_RETIRED.L3_MISS", IAP_EVENT_D1H_20H) \ __PMC_EV_ALIAS("MEM_LOAD_UOPS_RETIRED.HIT_LFB", IAP_EVENT_D1H_40H) \ __PMC_EV_ALIAS("MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_MISS", \ IAP_EVENT_D2H_01H) \ __PMC_EV_ALIAS("MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HIT", \ IAP_EVENT_D2H_02H) \ __PMC_EV_ALIAS("MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HITM", \ IAP_EVENT_D2H_04H) \ __PMC_EV_ALIAS("MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_NONE", \ IAP_EVENT_D2H_08H) \ __PMC_EV_ALIAS("MEM_LOAD_UOPS_LLC_HIT_RETIRED.ALL", \ IAP_EVENT_D2H_0FH) \ __PMC_EV_ALIAS("MEM_LOAD_UOPS_LLC_MISS_RETIRED.LOCAL_DRAM", \ IAP_EVENT_D3H_01H) \ __PMC_EV_ALIAS("BACLEARS.ANY", IAP_EVENT_E6H_1FH) \ __PMC_EV_ALIAS("L2_TRANS.DEMAND_DATA_RD", IAP_EVENT_F0H_01H) \ __PMC_EV_ALIAS("L2_TRANS.RFO", IAP_EVENT_F0H_02H) \ __PMC_EV_ALIAS("L2_TRANS.CODE_RD", IAP_EVENT_F0H_04H) \ __PMC_EV_ALIAS("L2_TRANS.ALL_PF", IAP_EVENT_F0H_08H) \ __PMC_EV_ALIAS("L2_TRANS.L1D_WB", IAP_EVENT_F0H_10H) \ __PMC_EV_ALIAS("L2_TRANS.L2_FILL", IAP_EVENT_F0H_20H) \ __PMC_EV_ALIAS("L2_TRANS.L2_WB", IAP_EVENT_F0H_40H) \ __PMC_EV_ALIAS("L2_TRANS.ALL_REQUESTS", IAP_EVENT_F0H_80H) \ __PMC_EV_ALIAS("L2_LINES_IN.I", IAP_EVENT_F1H_01H) \ __PMC_EV_ALIAS("L2_LINES_IN.S", IAP_EVENT_F1H_02H) \ __PMC_EV_ALIAS("L2_LINES_IN.E", IAP_EVENT_F1H_04H) \ __PMC_EV_ALIAS("L2_LINES_IN.ALL", IAP_EVENT_F1H_07H) \ __PMC_EV_ALIAS("L2_LINES_OUT.DEMAND_CLEAN", IAP_EVENT_F2H_05H) \ __PMC_EV_ALIAS("L2_LINES_OUT.DEMAND_DIRTY", IAP_EVENT_F2H_06H) #define __PMC_EV_ALIAS_HASWELL() \ __PMC_EV_ALIAS("LD_BLOCKS.STORE_FORWARD", IAP_EVENT_03H_02H) \ __PMC_EV_ALIAS("LD_BLOCKS.NO_SR", IAP_EVENT_03H_08H) \ __PMC_EV_ALIAS("MISALIGN_MEM_REF.LOADS", IAP_EVENT_05H_01H) \ __PMC_EV_ALIAS("MISALIGN_MEM_REF.STORES", IAP_EVENT_05H_02H) \ __PMC_EV_ALIAS("LD_BLOCKS_PARTIAL.ADDRESS_ALIAS", IAP_EVENT_07H_01H) \ __PMC_EV_ALIAS("DTLB_LOAD_MISSES.MISS_CAUSES_A_WALK", IAP_EVENT_08H_01H)\ __PMC_EV_ALIAS("DTLB_LOAD_MISSES.WALK_COMPLETED_4K", IAP_EVENT_08H_02H) \ __PMC_EV_ALIAS("DTLB_LOAD_MISSES.WALK_COMPLETED_2M_4M", \ IAP_EVENT_08H_04H) \ __PMC_EV_ALIAS("DTLB_LOAD_MISSES.WALK_COMPLETED", IAP_EVENT_08H_0EH) \ __PMC_EV_ALIAS("DTLB_LOAD_MISSES.WALK_DURATION", IAP_EVENT_08H_10H) \ __PMC_EV_ALIAS("DTLB_LOAD_MISSES.STLB_HIT_4K", IAP_EVENT_08H_20H) \ __PMC_EV_ALIAS("DTLB_LOAD_MISSES.STLB_HIT_2M", IAP_EVENT_08H_40H) \ __PMC_EV_ALIAS("DTLB_LOAD_MISSES.STLB_HIT", IAP_EVENT_08H_60H) \ __PMC_EV_ALIAS("DTLB_LOAD_MISSES.PDE_CACHE_MISS", IAP_EVENT_08H_80H) \ __PMC_EV_ALIAS("INT_MISC.RECOVERY_CYCLES", IAP_EVENT_0DH_03H) \ __PMC_EV_ALIAS("UOPS_ISSUED.ANY", IAP_EVENT_0EH_01H) \ __PMC_EV_ALIAS("UOPS_ISSUED.FLAGS_MERGE", IAP_EVENT_0EH_10H) \ __PMC_EV_ALIAS("UOPS_ISSUED.SLOW_LEA", IAP_EVENT_0EH_20H) \ __PMC_EV_ALIAS("UOPS_ISSUED.SINGLE_MUL", IAP_EVENT_0EH_40H) \ __PMC_EV_ALIAS("L2_RQSTS.DEMAND_DATA_RD_MISS", IAP_EVENT_24H_21H) \ __PMC_EV_ALIAS("L2_RQSTS.DEMAND_DATA_RD_HIT", IAP_EVENT_24H_41H) \ __PMC_EV_ALIAS("L2_RQSTS.ALL_DEMAND_DATA_RD", IAP_EVENT_24H_E1H) \ __PMC_EV_ALIAS("L2_RQSTS.RFO_HIT", IAP_EVENT_24H_42H) \ __PMC_EV_ALIAS("L2_RQSTS.RFO_MISS", IAP_EVENT_24H_22H) \ __PMC_EV_ALIAS("L2_RQSTS.ALL_RFO", IAP_EVENT_24H_E2H) \ __PMC_EV_ALIAS("L2_RQSTS.CODE_RD_HIT", IAP_EVENT_24H_44H) \ __PMC_EV_ALIAS("L2_RQSTS.CODE_RD_MISS", IAP_EVENT_24H_24H) \ __PMC_EV_ALIAS("L2_RQSTS.ALL_DEMAND_MISS", IAP_EVENT_24H_27H) \ __PMC_EV_ALIAS("L2_RQSTS.ALL_DEMAND_REFERENCES", IAP_EVENT_24H_E7H) \ __PMC_EV_ALIAS("L2_RQSTS.ALL_CODE_RD", IAP_EVENT_24H_E4H) \ __PMC_EV_ALIAS("L2_RQSTS.L2_PF_HIT", IAP_EVENT_24H_50H) \ __PMC_EV_ALIAS("L2_RQSTS.L2_PF_MISS", IAP_EVENT_24H_30H) \ __PMC_EV_ALIAS("L2_RQSTS.ALL_PF", IAP_EVENT_24H_F8H) \ __PMC_EV_ALIAS("L2_RQSTS.MISS", IAP_EVENT_24H_3FH) \ __PMC_EV_ALIAS("L2_RQSTS.REFERENCES", IAP_EVENT_24H_FFH) \ __PMC_EV_ALIAS("L2_DEMAND_RQSTS.WB_HIT", IAP_EVENT_27H_50H) \ __PMC_EV_ALIAS("LONGEST_LAT_CACHE.REFERENCE", IAP_EVENT_2EH_4FH) \ __PMC_EV_ALIAS("LONGEST_LAT_CACHE.MISS", IAP_EVENT_2EH_41H) \ __PMC_EV_ALIAS("CPU_CLK_UNHALTED.THREAD_P", IAP_EVENT_3CH_00H) \ __PMC_EV_ALIAS("CPU_CLK_THREAD_UNHALTED.REF_XCLK", IAP_EVENT_3CH_01H) \ __PMC_EV_ALIAS("L1D_PEND_MISS.PENDING", IAP_EVENT_48H_01H) \ __PMC_EV_ALIAS("DTLB_STORE_MISSES.MISS_CAUSES_A_WALK", \ IAP_EVENT_49H_01H) \ __PMC_EV_ALIAS("DTLB_STORE_MISSES.WALK_COMPLETED_4K", \ IAP_EVENT_49H_02H) \ __PMC_EV_ALIAS("DTLB_STORE_MISSES.WALK_COMPLETED_2M_4M", \ IAP_EVENT_49H_04H) \ __PMC_EV_ALIAS("DTLB_STORE_MISSES.WALK_COMPLETED", IAP_EVENT_49H_0EH) \ __PMC_EV_ALIAS("DTLB_STORE_MISSES.WALK_DURATION", IAP_EVENT_49H_10H) \ __PMC_EV_ALIAS("DTLB_STORE_MISSES.STLB_HIT_4K", IAP_EVENT_49H_20H) \ __PMC_EV_ALIAS("DTLB_STORE_MISSES.STLB_HIT_2M", IAP_EVENT_49H_40H) \ __PMC_EV_ALIAS("DTLB_STORE_MISSES.STLB_HIT", IAP_EVENT_49H_60H) \ __PMC_EV_ALIAS("DTLB_STORE_MISSES.PDE_CACHE_MISS", IAP_EVENT_49H_80H) \ __PMC_EV_ALIAS("LOAD_HIT_PRE.SW_PF", IAP_EVENT_4CH_01H) \ __PMC_EV_ALIAS("LOAD_HIT_PRE.HW_PF", IAP_EVENT_4CH_02H) \ __PMC_EV_ALIAS("L1D.REPLACEMENT", IAP_EVENT_51H_01H) \ __PMC_EV_ALIAS("MOVE_ELIMINATION.INT_NOT_ELIMINATED", \ IAP_EVENT_58H_04H) \ __PMC_EV_ALIAS("MOVE_ELIMINATION.SMID_NOT_ELIMINATED", \ IAP_EVENT_58H_08H) \ __PMC_EV_ALIAS("MOVE_ELIMINATION.INT_ELIMINATED", IAP_EVENT_58H_01H) \ __PMC_EV_ALIAS("MOVE_ELIMINATION.SMID_ELIMINATED", IAP_EVENT_58H_02H) \ __PMC_EV_ALIAS("CPL_CYCLES.RING0", IAP_EVENT_5CH_01H) \ __PMC_EV_ALIAS("CPL_CYCLES.RING123", IAP_EVENT_5CH_02H) \ __PMC_EV_ALIAS("RS_EVENTS.EMPTY_CYCLES", IAP_EVENT_5EH_01H) \ __PMC_EV_ALIAS("OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD", \ IAP_EVENT_60H_01H) \ __PMC_EV_ALIAS("OFFCORE_REQUESTS_OUTSTANDING.DEMAND_CORE_RD", \ IAP_EVENT_60H_02H) \ __PMC_EV_ALIAS("OFFCORE_REQUESTS_OUTSTANDING.DEMAND_RFO", \ IAP_EVENT_60H_04H) \ __PMC_EV_ALIAS("OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD", \ IAP_EVENT_60H_08H) \ __PMC_EV_ALIAS("LOCK_CYCLES.SPLIT_LOCK_UC_LOCK_DURATION", \ IAP_EVENT_63H_01H) \ __PMC_EV_ALIAS("LOCK_CYCLES.CACHE_LOCK_DURATION", IAP_EVENT_63H_02H) \ __PMC_EV_ALIAS("IDQ.EMPTY", IAP_EVENT_79H_02H) \ __PMC_EV_ALIAS("IDQ.MITE_UOPS", IAP_EVENT_79H_04H) \ __PMC_EV_ALIAS("IDQ.DSB_UOPS", IAP_EVENT_79H_08H) \ __PMC_EV_ALIAS("IDQ.MS_DSB_UOPS", IAP_EVENT_79H_10H) \ __PMC_EV_ALIAS("IDQ.MS_MITE_UOPS", IAP_EVENT_79H_20H) \ __PMC_EV_ALIAS("IDQ.MS_UOPS", IAP_EVENT_79H_30H) \ __PMC_EV_ALIAS("IDQ.ALL_DSB_CYCLES_ANY_UOPS", IAP_EVENT_79H_18H) \ __PMC_EV_ALIAS("IDQ.ALL_DSB_CYCLES_4_UOPS", IAP_EVENT_79H_18H) \ __PMC_EV_ALIAS("IDQ.ALL_MITE_CYCLES_ANY_UOPS", IAP_EVENT_79H_24H) \ __PMC_EV_ALIAS("IDQ.ALL_MITE_CYCLES_4_UOPS", IAP_EVENT_79H_24H) \ __PMC_EV_ALIAS("IDQ.MITE_ALL_UOPS", IAP_EVENT_79H_3CH) \ __PMC_EV_ALIAS("ICACHE.MISSES", IAP_EVENT_80H_02H) \ __PMC_EV_ALIAS("ITLB_MISSES.MISS_CAUSES_A_WALK", IAP_EVENT_85H_01H) \ __PMC_EV_ALIAS("ITLB_MISSES.WALK_COMPLETED_4K", IAP_EVENT_85H_02H) \ __PMC_EV_ALIAS("TLB_MISSES.WALK_COMPLETED_2M_4M", IAP_EVENT_85H_04H) \ __PMC_EV_ALIAS("ITLB_MISSES.WALK_COMPLETED", IAP_EVENT_85H_0EH) \ __PMC_EV_ALIAS("ITLB_MISSES.WALK_DURATION", IAP_EVENT_85H_10H) \ __PMC_EV_ALIAS("ITLB_MISSES.STLB_HIT_4K", IAP_EVENT_85H_20H) \ __PMC_EV_ALIAS("ITLB_MISSES.STLB_HIT_2M", IAP_EVENT_85H_40H) \ __PMC_EV_ALIAS("ITLB_MISSES.STLB_HIT", IAP_EVENT_85H_60H) \ __PMC_EV_ALIAS("ILD_STALL.LCP", IAP_EVENT_87H_01H) \ __PMC_EV_ALIAS("ILD_STALL.IQ_FULL", IAP_EVENT_87H_04H) \ -__PMC_EV_ALIAS("BR_INST_EXEC.COND", IAP_EVENT_88H_01H) \ -__PMC_EV_ALIAS("BR_INST_EXEC.DIRECT_JMP", IAP_EVENT_88H_02H) \ +__PMC_EV_ALIAS("BR_INST_EXEC.NONTAKEN_COND", IAP_EVENT_88H_41H) \ +__PMC_EV_ALIAS("BR_INST_EXEC.TAKEN_COND", IAP_EVENT_88H_81H) \ +__PMC_EV_ALIAS("BR_INST_EXEC.DIRECT_JMP", IAP_EVENT_88H_82H) \ __PMC_EV_ALIAS("BR_INST_EXEC.INDIRECT_JMP_NON_CALL_RET", \ - IAP_EVENT_88H_04H) \ -__PMC_EV_ALIAS("BR_INST_EXEC.RETURN_NEAR", IAP_EVENT_88H_08H) \ -__PMC_EV_ALIAS("BR_INST_EXEC.DIRECT_NEAR_CALL", IAP_EVENT_88H_10H) \ -__PMC_EV_ALIAS("BR_INST_EXEC.INDIRECT_NEAR_CALL", IAP_EVENT_88H_20H) \ -__PMC_EV_ALIAS("BR_INST_EXEC.NONTAKEN", IAP_EVENT_88H_40H) \ -__PMC_EV_ALIAS("BR_INST_EXEC.TAKEN", IAP_EVENT_88H_80H) \ + IAP_EVENT_88H_84H) \ +__PMC_EV_ALIAS("BR_INST_EXEC.RETURN_NEAR", IAP_EVENT_88H_88H) \ +__PMC_EV_ALIAS("BR_INST_EXEC.DIRECT_NEAR_CALL", IAP_EVENT_88H_90H) \ +__PMC_EV_ALIAS("BR_INST_EXEC.INDIRECT_NEAR_CALL", IAP_EVENT_88H_A0H) \ __PMC_EV_ALIAS("BR_INST_EXEC.ALL_BRANCHES", IAP_EVENT_88H_FFH) \ -__PMC_EV_ALIAS("BR_MISP_EXEC.COND", IAP_EVENT_89H_01H) \ +__PMC_EV_ALIAS("BR_MISP_EXEC.NONTAKEN_COND", IAP_EVENT_89H_41H) \ +__PMC_EV_ALIAS("BR_MISP_EXEC.TAKEN_COND", IAP_EVENT_89H_81H) \ __PMC_EV_ALIAS("BR_MISP_EXEC.INDIRECT_JMP_NON_CALL_RET", \ - IAP_EVENT_89H_04H) \ -__PMC_EV_ALIAS("BR_MISP_EXEC.RETURN_NEAR", IAP_EVENT_89H_08H) \ -__PMC_EV_ALIAS("BR_MISP_EXEC.DIRECT_NEAR_CALL", IAP_EVENT_89H_10H) \ -__PMC_EV_ALIAS("BR_MISP_EXEC.INDIRECT_NEAR_CALL", IAP_EVENT_89H_20H) \ -__PMC_EV_ALIAS("BR_MISP_EXEC.NONTAKEN", IAP_EVENT_89H_40H) \ -__PMC_EV_ALIAS("BR_MISP_EXEC.TAKEN", IAP_EVENT_89H_80H) \ + IAP_EVENT_89H_84H) \ +__PMC_EV_ALIAS("BR_MISP_EXEC.RETURN_NEAR", IAP_EVENT_89H_88H) \ +__PMC_EV_ALIAS("BR_MISP_EXEC.DIRECT_NEAR_CALL", IAP_EVENT_89H_90H) \ +__PMC_EV_ALIAS("BR_MISP_EXEC.INDIRECT_NEAR_CALL", IAP_EVENT_89H_A0H) \ __PMC_EV_ALIAS("BR_MISP_EXEC.ALL_BRANCHES", IAP_EVENT_89H_FFH) \ __PMC_EV_ALIAS("IDQ_UOPS_NOT_DELIVERED.CORE", IAP_EVENT_9CH_01H) \ __PMC_EV_ALIAS("UOPS_EXECUTED_PORT.PORT_0", IAP_EVENT_A1H_01H) \ __PMC_EV_ALIAS("UOPS_EXECUTED_PORT.PORT_1", IAP_EVENT_A1H_02H) \ __PMC_EV_ALIAS("UOPS_EXECUTED_PORT.PORT_2", IAP_EVENT_A1H_04H) \ __PMC_EV_ALIAS("UOPS_EXECUTED_PORT.PORT_3", IAP_EVENT_A1H_08H) \ __PMC_EV_ALIAS("UOPS_EXECUTED_PORT.PORT_4", IAP_EVENT_A1H_10H) \ __PMC_EV_ALIAS("UOPS_EXECUTED_PORT.PORT_5", IAP_EVENT_A1H_20H) \ __PMC_EV_ALIAS("UOPS_EXECUTED_PORT.PORT_6", IAP_EVENT_A1H_40H) \ __PMC_EV_ALIAS("UOPS_EXECUTED_PORT.PORT_7", IAP_EVENT_A1H_80H) \ __PMC_EV_ALIAS("RESOURCE_STALLS.ANY", IAP_EVENT_A2H_01H) \ __PMC_EV_ALIAS("RESOURCE_STALLS.RS", IAP_EVENT_A2H_04H) \ __PMC_EV_ALIAS("RESOURCE_STALLS.SB", IAP_EVENT_A2H_08H) \ __PMC_EV_ALIAS("RESOURCE_STALLS.ROB", IAP_EVENT_A2H_10H) \ __PMC_EV_ALIAS("CYCLE_ACTIVITY.CYCLES_L2_PENDING", IAP_EVENT_A3H_01H) \ __PMC_EV_ALIAS("CYCLE_ACTIVITY.CYCLES_LDM_PENDING", IAP_EVENT_A3H_02H) \ __PMC_EV_ALIAS("CYCLE_ACTIVITY.STALLS_L2_PENDING", IAP_EVENT_A3H_05H) \ __PMC_EV_ALIAS("CYCLE_ACTIVITY.CYCLES_L1D_PENDING", IAP_EVENT_A3H_08H) \ __PMC_EV_ALIAS("CYCLE_ACTIVITY.STALLS_L1D_PENDING", IAP_EVENT_A3H_0CH) \ __PMC_EV_ALIAS("LSD.UOPS", IAP_EVENT_A8H_01H) \ __PMC_EV_ALIAS("ITLB.ITLB_FLUSH", IAP_EVENT_AEH_01H) \ __PMC_EV_ALIAS("OFFCORE_REQUESTS.DEMAND_DATA_RD", IAP_EVENT_B0H_01H) \ __PMC_EV_ALIAS("OFFCORE_REQUESTS.DEMAND_CODE_RD", IAP_EVENT_B0H_02H) \ __PMC_EV_ALIAS("OFFCORE_REQUESTS.DEMAND_RFO", IAP_EVENT_B0H_04H) \ __PMC_EV_ALIAS("OFFCORE_REQUESTS.ALL_DATA_RD", IAP_EVENT_B0H_08H) \ __PMC_EV_ALIAS("UOPS_EXECUTED.CORE", IAP_EVENT_B1H_02H) \ __PMC_EV_ALIAS("OFF_CORE_RESPONSE_0", IAP_EVENT_B7H_01H) \ __PMC_EV_ALIAS("OFF_CORE_RESPONSE_1", IAP_EVENT_BBH_01H) \ __PMC_EV_ALIAS("PAGE_WALKER_LOADS.DTLB_L1", IAP_EVENT_BCH_11H) \ __PMC_EV_ALIAS("PAGE_WALKER_LOADS.ITLB_L1", IAP_EVENT_BCH_21H) \ __PMC_EV_ALIAS("PAGE_WALKER_LOADS.DTLB_L2", IAP_EVENT_BCH_12H) \ __PMC_EV_ALIAS("PAGE_WALKER_LOADS.ITLB_L2", IAP_EVENT_BCH_22H) \ __PMC_EV_ALIAS("PAGE_WALKER_LOADS.DTLB_L3", IAP_EVENT_BCH_14H) \ __PMC_EV_ALIAS("PAGE_WALKER_LOADS.ITLB_L3", IAP_EVENT_BCH_24H) \ __PMC_EV_ALIAS("PAGE_WALKER_LOADS.DTLB_MEMORY", IAP_EVENT_BCH_18H) \ __PMC_EV_ALIAS("PAGE_WALKER_LOADS.ITLB_MEMORY", IAP_EVENT_BCH_28H) \ __PMC_EV_ALIAS("TLB_FLUSH.DTLB_THREAD", IAP_EVENT_BDH_01H) \ __PMC_EV_ALIAS("TLB_FLUSH.STLB_ANY", IAP_EVENT_BDH_20H) \ __PMC_EV_ALIAS("INST_RETIRED.ANY_P", IAP_EVENT_C0H_00H) \ __PMC_EV_ALIAS("INST_RETIRED.PREC_DIST", IAP_EVENT_C0H_01H) \ __PMC_EV_ALIAS("OTHER_ASSISTS.AVX_TO_SSE", IAP_EVENT_C1H_08H) \ __PMC_EV_ALIAS("OTHER_ASSISTS.SSE_TO_AVX", IAP_EVENT_C1H_10H) \ __PMC_EV_ALIAS("OTHER_ASSISTS.ANY_WB_ASSIST", IAP_EVENT_C1H_40H) \ __PMC_EV_ALIAS("UOPS_RETIRED.ALL", IAP_EVENT_C2H_01H) \ __PMC_EV_ALIAS("UOPS_RETIRED.RETIRE_SLOTS", IAP_EVENT_C2H_02H) \ __PMC_EV_ALIAS("MACHINE_CLEARS.MEMORY_ORDERING", IAP_EVENT_C3H_02H) \ __PMC_EV_ALIAS("MACHINE_CLEARS.SMC", IAP_EVENT_C3H_04H) \ __PMC_EV_ALIAS("MACHINE_CLEARS.MASKMOV", IAP_EVENT_C3H_20H) \ __PMC_EV_ALIAS("BR_INST_RETIRED.ALL_BRANCHES", IAP_EVENT_C4H_00H) \ __PMC_EV_ALIAS("BR_INST_RETIRED.CONDITIONAL", IAP_EVENT_C4H_01H) \ __PMC_EV_ALIAS("BR_INST_RETIRED.NEAR_CALL", IAP_EVENT_C4H_02H) \ __PMC_EV_ALIAS("BR_INST_RETIRED.ALL_BRANCHES", IAP_EVENT_C4H_04H) \ __PMC_EV_ALIAS("BR_INST_RETIRED.NEAR_RETURN", IAP_EVENT_C4H_08H) \ __PMC_EV_ALIAS("BR_INST_RETIRED.NOT_TAKEN", IAP_EVENT_C4H_10H) \ __PMC_EV_ALIAS("BR_INST_RETIRED.NEAR_TAKEN", IAP_EVENT_C4H_20H) \ __PMC_EV_ALIAS("BR_INST_RETIRED.FAR_BRANCH", IAP_EVENT_C4H_40H) \ __PMC_EV_ALIAS("BR_MISP_RETIRED.ALL_BRANCHES", IAP_EVENT_C5H_00H) \ __PMC_EV_ALIAS("BR_MISP_RETIRED.CONDITIONAL", IAP_EVENT_C5H_01H) \ __PMC_EV_ALIAS("BR_MISP_RETIRED.CONDITIONAL", IAP_EVENT_C5H_04H) \ __PMC_EV_ALIAS("BR_MISP_RETIRED.NEAR_TAKEN", IAP_EVENT_C5H_20H) \ __PMC_EV_ALIAS("FP_ASSIST.X87_OUTPUT", IAP_EVENT_CAH_02H) \ __PMC_EV_ALIAS("FP_ASSIST.X87_INPUT", IAP_EVENT_CAH_04H) \ __PMC_EV_ALIAS("FP_ASSIST.SIMD_OUTPUT", IAP_EVENT_CAH_08H) \ __PMC_EV_ALIAS("FP_ASSIST.SIMD_INPUT", IAP_EVENT_CAH_10H) \ __PMC_EV_ALIAS("FP_ASSIST.ANY", IAP_EVENT_CAH_1EH) \ __PMC_EV_ALIAS("ROB_MISC_EVENTS.LBR_INSERTS", IAP_EVENT_CCH_20H) \ __PMC_EV_ALIAS("MEM_TRANS_RETIRED.LOAD_LATENCY", IAP_EVENT_CDH_01H) \ __PMC_EV_ALIAS("MEM_UOP_RETIRED.LOADS", IAP_EVENT_D0H_01H) \ __PMC_EV_ALIAS("MEM_UOP_RETIRED.STORES", IAP_EVENT_D0H_02H) \ __PMC_EV_ALIAS("MEM_UOP_RETIRED.STLB_MISS", IAP_EVENT_D0H_10H) \ __PMC_EV_ALIAS("MEM_UOP_RETIRED.LOCK", IAP_EVENT_D0H_20H) \ __PMC_EV_ALIAS("MEM_UOP_RETIRED.SPLIT", IAP_EVENT_D0H_40H) \ __PMC_EV_ALIAS("MEM_UOP_RETIRED.SPLIT_LOADS", IAP_EVENT_D0H_41H) \ __PMC_EV_ALIAS("MEM_UOP_RETIRED.SPLIT_STORES", IAP_EVENT_D0H_42H) \ __PMC_EV_ALIAS("MEM_UOP_RETIRED.ALL", IAP_EVENT_D0H_80H) \ __PMC_EV_ALIAS("MEM_LOAD_UOPS_RETIRED.L1_HIT", IAP_EVENT_D1H_01H) \ __PMC_EV_ALIAS("MEM_LOAD_UOPS_RETIRED.L2_HIT", IAP_EVENT_D1H_02H) \ __PMC_EV_ALIAS("MEM_LOAD_UOPS_RETIRED.LLC_HIT", IAP_EVENT_D1H_04H) \ __PMC_EV_ALIAS("MEM_LOAD_UOPS_RETIRED.L1_MISS", IAP_EVENT_D1H_08H) \ __PMC_EV_ALIAS("MEM_LOAD_UOPS_RETIRED.L2_MISS", IAP_EVENT_D1H_10H) \ __PMC_EV_ALIAS("MEM_LOAD_UOPS_RETIRED.L3_MISS", IAP_EVENT_D1H_20H) \ __PMC_EV_ALIAS("MEM_LOAD_UOPS_RETIRED.HIT_LFB", IAP_EVENT_D1H_40H) \ __PMC_EV_ALIAS("MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_MISS", \ IAP_EVENT_D2H_01H) \ __PMC_EV_ALIAS("MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HIT", \ IAP_EVENT_D2H_02H) \ __PMC_EV_ALIAS("MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HITM", \ IAP_EVENT_D2H_04H) \ __PMC_EV_ALIAS("MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_NONE", \ IAP_EVENT_D2H_08H) \ __PMC_EV_ALIAS("MEM_LOAD_UOPS_LLC_HIT_RETIRED.ALL", \ IAP_EVENT_D2H_0FH) \ __PMC_EV_ALIAS("MEM_LOAD_UOPS_LLC_MISS_RETIRED.LOCAL_DRAM", \ IAP_EVENT_D3H_01H) \ __PMC_EV_ALIAS("BACLEARS.ANY", IAP_EVENT_E6H_1FH) \ __PMC_EV_ALIAS("L2_TRANS.DEMAND_DATA_RD", IAP_EVENT_F0H_01H) \ __PMC_EV_ALIAS("L2_TRANS.RFO", IAP_EVENT_F0H_02H) \ __PMC_EV_ALIAS("L2_TRANS.CODE_RD", IAP_EVENT_F0H_04H) \ __PMC_EV_ALIAS("L2_TRANS.ALL_PF", IAP_EVENT_F0H_08H) \ __PMC_EV_ALIAS("L2_TRANS.L1D_WB", IAP_EVENT_F0H_10H) \ __PMC_EV_ALIAS("L2_TRANS.L2_FILL", IAP_EVENT_F0H_20H) \ __PMC_EV_ALIAS("L2_TRANS.L2_WB", IAP_EVENT_F0H_40H) \ __PMC_EV_ALIAS("L2_TRANS.ALL_REQUESTS", IAP_EVENT_F0H_80H) \ __PMC_EV_ALIAS("L2_LINES_IN.I", IAP_EVENT_F1H_01H) \ __PMC_EV_ALIAS("L2_LINES_IN.S", IAP_EVENT_F1H_02H) \ __PMC_EV_ALIAS("L2_LINES_IN.E", IAP_EVENT_F1H_04H) \ __PMC_EV_ALIAS("L2_LINES_IN.ALL", IAP_EVENT_F1H_07H) \ __PMC_EV_ALIAS("L2_LINES_OUT.DEMAND_CLEAN", IAP_EVENT_F2H_05H) \ __PMC_EV_ALIAS("L2_LINES_OUT.DEMAND_DIRTY", IAP_EVENT_F2H_06H) #define __PMC_EV_ALIAS_IVYBRIDGE() \ __PMC_EV_ALIAS("LD_BLOCKS.STORE_FORWARD", IAP_EVENT_03H_02H) \ __PMC_EV_ALIAS("LD_BLOCKS.NO_SR", IAP_EVENT_03H_08H) \ __PMC_EV_ALIAS("MISALIGN_MEM_REF.LOADS", IAP_EVENT_05H_01H) \ __PMC_EV_ALIAS("MISALIGN_MEM_REF.STORES", IAP_EVENT_05H_02H) \ __PMC_EV_ALIAS("LD_BLOCKS_PARTIAL.ADDRESS_ALIAS", IAP_EVENT_07H_01H) \ __PMC_EV_ALIAS("INT_MISC.RECOVERY_CYCLES", IAP_EVENT_0DH_03H) \ __PMC_EV_ALIAS("DTLB_LOAD_MISSES.MISS_CAUSES_A_WALK", IAP_EVENT_08H_81H)\ __PMC_EV_ALIAS("DTLB_LOAD_MISSES.WALK_COMPLETED", IAP_EVENT_08H_82H) \ __PMC_EV_ALIAS("DTLB_LOAD_MISSES.WALK_DURATION", IAP_EVENT_08H_84H) \ __PMC_EV_ALIAS("DTLB_LOAD_MISSES.LARGE_PG_WALK_DURATION", \ IAP_EVENT_08H_88H) \ __PMC_EV_ALIAS("UOPS_ISSUED.ANY", IAP_EVENT_0EH_01H) \ __PMC_EV_ALIAS("UOPS_ISSUED.FLAGS_MERGE", IAP_EVENT_0EH_10H) \ __PMC_EV_ALIAS("UOPS_ISSUED.SLOW_LEA", IAP_EVENT_0EH_20H) \ __PMC_EV_ALIAS("UOPS_ISSUED.SINGLE_MUL", IAP_EVENT_0EH_40H) \ __PMC_EV_ALIAS("FP_COMP_OPS_EXE.X87", IAP_EVENT_10H_01H) \ __PMC_EV_ALIAS("FP_COMP_OPS_EXE.SSE_FP_PACKED_DOUBLE", \ IAP_EVENT_10H_10H) \ __PMC_EV_ALIAS("FP_COMP_OPS_EXE.SSE_FP_SCALAR_SINGLE", \ IAP_EVENT_10H_20H) \ __PMC_EV_ALIAS("FP_COMP_OPS_EXE.SSE_PACKED_SINGLE", IAP_EVENT_10H_40H) \ __PMC_EV_ALIAS("FP_COMP_OPS_EXE.SSE_SCALAR_DOUBLE", IAP_EVENT_10H_80H) \ __PMC_EV_ALIAS("SIMD_FP_256.PACKED_SINGLE", IAP_EVENT_11H_01H) \ __PMC_EV_ALIAS("SIMD_FP_256.PACKED_DOUBLE", IAP_EVENT_11H_02H) \ __PMC_EV_ALIAS("ARITH.FPU_DIV_ACTIVE", IAP_EVENT_14H_01H) \ __PMC_EV_ALIAS("L2_RQSTS.DEMAND_DATA_RD_HIT", IAP_EVENT_24H_01H) \ __PMC_EV_ALIAS("L2_RQSTS.ALL_DEMAND_DATA_RD", IAP_EVENT_24H_03H) \ __PMC_EV_ALIAS("L2_RQSTS.RFO_HITS", IAP_EVENT_24H_04H) \ __PMC_EV_ALIAS("L2_RQSTS.RFO_MISS", IAP_EVENT_24H_08H) \ __PMC_EV_ALIAS("L2_RQSTS.ALL_RFO", IAP_EVENT_24H_0CH) \ __PMC_EV_ALIAS("L2_RQSTS.CODE_RD_HIT", IAP_EVENT_24H_10H) \ __PMC_EV_ALIAS("L2_RQSTS.CODE_RD_MISS", IAP_EVENT_24H_20H) \ __PMC_EV_ALIAS("L2_RQSTS.ALL_CODE_RD", IAP_EVENT_24H_30H) \ __PMC_EV_ALIAS("L2_RQSTS.PF_HIT", IAP_EVENT_24H_40H) \ __PMC_EV_ALIAS("L2_RQSTS.PF_MISS", IAP_EVENT_24H_80H) \ __PMC_EV_ALIAS("L2_RQSTS.ALL_PF", IAP_EVENT_24H_C0H) \ __PMC_EV_ALIAS("L2_STORE_LOCK_RQSTS.MISS", IAP_EVENT_27H_01H) \ __PMC_EV_ALIAS("L2_STORE_LOCK_RQSTS.HIT_M", IAP_EVENT_27H_08H) \ __PMC_EV_ALIAS("L2_STORE_LOCK_RQSTS.ALL", IAP_EVENT_27H_0FH) \ __PMC_EV_ALIAS("L2_L1D_WB_RQSTS.MISS", IAP_EVENT_28H_01H) \ __PMC_EV_ALIAS("L2_L1D_WB_RQSTS.HIT_E", IAP_EVENT_28H_04H) \ __PMC_EV_ALIAS("L2_L1D_WB_RQSTS.HIT_M", IAP_EVENT_28H_08H) \ __PMC_EV_ALIAS("L2_L1D_WB_RQSTS.ALL", IAP_EVENT_28H_0FH) \ __PMC_EV_ALIAS("LONGEST_LAT_CACHE.REFERENCE", IAP_EVENT_2EH_4FH) \ __PMC_EV_ALIAS("LONGEST_LAT_CACHE.MISS", IAP_EVENT_2EH_41H) \ __PMC_EV_ALIAS("CPU_CLK_UNHALTED.THREAD_P", IAP_EVENT_3CH_00H) \ __PMC_EV_ALIAS("CPU_CLK_THREAD_UNHALTED.REF_XCLK", IAP_EVENT_3CH_01H) \ __PMC_EV_ALIAS("L1D_PEND_MISS.PENDING", IAP_EVENT_48H_01H) \ __PMC_EV_ALIAS("DTLB_STORE_MISSES.MISS_CAUSES_A_WALK", \ IAP_EVENT_49H_01H) \ __PMC_EV_ALIAS("DTLB_STORE_MISSES.WALK_COMPLETED", IAP_EVENT_49H_02H) \ __PMC_EV_ALIAS("DTLB_STORE_MISSES.WALK_DURATION", IAP_EVENT_49H_04H) \ __PMC_EV_ALIAS("DTLB_STORE_MISSES.STLB_HIT", IAP_EVENT_49H_10H) \ __PMC_EV_ALIAS("LOAD_HIT_PRE.SW_PF", IAP_EVENT_4CH_01H) \ __PMC_EV_ALIAS("LOAD_HIT_PRE.HW_PF", IAP_EVENT_4CH_02H) \ __PMC_EV_ALIAS("L1D.REPLACEMENT", IAP_EVENT_51H_01H) \ __PMC_EV_ALIAS("MOVE_ELIMINATION.INT_NOT_ELIMINATED", \ IAP_EVENT_58H_01H) \ __PMC_EV_ALIAS("MOVE_ELIMINATION.SIMD_NOT_ELIMINATED", \ IAP_EVENT_58H_02H) \ __PMC_EV_ALIAS("MOVE_ELIMINATION.INT_ELIMINATED", IAP_EVENT_58H_04H) \ __PMC_EV_ALIAS("MOVE_ELIMINATION.SIMD_ELIMINATED", IAP_EVENT_58H_08H) \ __PMC_EV_ALIAS("CPL_CYCLES.RING0", IAP_EVENT_5CH_01H) \ __PMC_EV_ALIAS("CPL_CYCLES.RING123", IAP_EVENT_5CH_02H) \ __PMC_EV_ALIAS("RS_EVENTS.EMPTY_CYCLES", IAP_EVENT_5EH_01H) \ __PMC_EV_ALIAS("DTLB_LOAD_MISSES.STLB_HIT", IAP_EVENT_5FH_04H) \ __PMC_EV_ALIAS("OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD", \ IAP_EVENT_60H_01H) \ __PMC_EV_ALIAS("OFFCORE_REQUESTS_OUTSTANDING.DEMAND_CODE_RD", \ IAP_EVENT_60H_02H) \ __PMC_EV_ALIAS("OFFCORE_REQUESTS_OUTSTANDING.DEMAND_RFO", \ IAP_EVENT_60H_04H) \ __PMC_EV_ALIAS("OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD", \ IAP_EVENT_60H_08H) \ __PMC_EV_ALIAS("LOCK_CYCLES.SPLIT_LOCK_UC_LOCK_DURATION", \ IAP_EVENT_63H_01H) \ __PMC_EV_ALIAS("LOCK_CYCLES.CACHE_LOCK_DURATION", IAP_EVENT_63H_02H) \ __PMC_EV_ALIAS("IDQ.EMPTY", IAP_EVENT_79H_02H) \ __PMC_EV_ALIAS("IDQ.MITE_UOPS", IAP_EVENT_79H_04H) \ __PMC_EV_ALIAS("IDQ.DSB_UOPS", IAP_EVENT_79H_08H) \ __PMC_EV_ALIAS("IDQ.MS_DSB_UOPS", IAP_EVENT_79H_10H) \ __PMC_EV_ALIAS("IDQ.MS_MITE_UOPS", IAP_EVENT_79H_20H) \ __PMC_EV_ALIAS("IDQ.MS_UOPS", IAP_EVENT_79H_30H) \ __PMC_EV_ALIAS("IDQ.ALL_DSB_CYCLES_ANY_UOPS", IAP_EVENT_79H_18H) \ __PMC_EV_ALIAS("IDQ.ALL_DSB_CYCLES_4_UOPS", IAP_EVENT_79H_18H) \ __PMC_EV_ALIAS("IDQ.ALL_MITE_CYCLES_ANY_UOPS", IAP_EVENT_79H_24H) \ __PMC_EV_ALIAS("IDQ.ALL_MITE_CYCLES_4_UOPS", IAP_EVENT_79H_24H) \ __PMC_EV_ALIAS("IDQ.MITE_ALL_UOPS", IAP_EVENT_79H_3CH) \ __PMC_EV_ALIAS("ICACHE.MISSES", IAP_EVENT_80H_02H) \ __PMC_EV_ALIAS("ICACHE.IFETCH_STALL", IAP_EVENT_80H_04H) \ __PMC_EV_ALIAS("ITLB_MISSES.MISS_CAUSES_A_WALK", IAP_EVENT_85H_01H) \ __PMC_EV_ALIAS("ITLB_MISSES.WALK_COMPLETED", IAP_EVENT_85H_02H) \ __PMC_EV_ALIAS("ITLB_MISSES.WALK_DURATION", IAP_EVENT_85H_04H) \ __PMC_EV_ALIAS("ITLB_MISSES.STLB_HIT", IAP_EVENT_85H_10H) \ __PMC_EV_ALIAS("ILD_STALL.LCP", IAP_EVENT_87H_01H) \ __PMC_EV_ALIAS("ILD_STALL.IQ_FULL", IAP_EVENT_87H_04H) \ -__PMC_EV_ALIAS("BR_INST_EXEC.COND", IAP_EVENT_88H_01H) \ -__PMC_EV_ALIAS("BR_INST_EXEC.DIRECT_JMP", IAP_EVENT_88H_02H) \ +__PMC_EV_ALIAS("BR_INST_EXEC.NONTAKEN_COND", IAP_EVENT_88H_41H) \ +__PMC_EV_ALIAS("BR_INST_EXEC.TAKEN_COND", IAP_EVENT_88H_81H) \ +__PMC_EV_ALIAS("BR_INST_EXEC.DIRECT_JMP", IAP_EVENT_88H_82H) \ __PMC_EV_ALIAS("BR_INST_EXEC.INDIRECT_JMP_NON_CALL_RET", \ - IAP_EVENT_88H_04H) \ -__PMC_EV_ALIAS("BR_INST_EXEC.RETURN_NEAR", IAP_EVENT_88H_08H) \ -__PMC_EV_ALIAS("BR_INST_EXEC.DIRECT_NEAR_CALL", IAP_EVENT_88H_10H) \ -__PMC_EV_ALIAS("BR_INST_EXEC.INDIRECT_NEAR_CALL", IAP_EVENT_88H_20H) \ -__PMC_EV_ALIAS("BR_INST_EXEC.NONTAKEN", IAP_EVENT_88H_40H) \ -__PMC_EV_ALIAS("BR_INST_EXEC.TAKEN", IAP_EVENT_88H_80H) \ + IAP_EVENT_88H_84H) \ +__PMC_EV_ALIAS("BR_INST_EXEC.RETURN_NEAR", IAP_EVENT_88H_88H) \ +__PMC_EV_ALIAS("BR_INST_EXEC.DIRECT_NEAR_CALL", IAP_EVENT_88H_90H) \ +__PMC_EV_ALIAS("BR_INST_EXEC.INDIRECT_NEAR_CALL", IAP_EVENT_88H_A0H) \ __PMC_EV_ALIAS("BR_INST_EXEC.ALL_BRANCHES", IAP_EVENT_88H_FFH) \ -__PMC_EV_ALIAS("BR_MISP_EXEC.COND", IAP_EVENT_89H_01H) \ +__PMC_EV_ALIAS("BR_MISP_EXEC.NONTAKEN_COND", IAP_EVENT_89H_41H) \ +__PMC_EV_ALIAS("BR_MISP_EXEC.TAKEN_COND", IAP_EVENT_89H_81H) \ __PMC_EV_ALIAS("BR_MISP_EXEC.INDIRECT_JMP_NON_CALL_RET", \ - IAP_EVENT_89H_04H) \ -__PMC_EV_ALIAS("BR_MISP_EXEC.RETURN_NEAR", IAP_EVENT_89H_08H) \ -__PMC_EV_ALIAS("BR_MISP_EXEC.DIRECT_NEAR_CALL", IAP_EVENT_89H_10H) \ -__PMC_EV_ALIAS("BR_MISP_EXEC.INDIRECT_NEAR_CALL", IAP_EVENT_89H_20H) \ -__PMC_EV_ALIAS("BR_MISP_EXEC.NONTAKEN", IAP_EVENT_89H_40H) \ -__PMC_EV_ALIAS("BR_MISP_EXEC.TAKEN", IAP_EVENT_89H_80H) \ + IAP_EVENT_89H_84H) \ +__PMC_EV_ALIAS("BR_MISP_EXEC.RETURN_NEAR", IAP_EVENT_89H_88H) \ +__PMC_EV_ALIAS("BR_MISP_EXEC.DIRECT_NEAR_CALL", IAP_EVENT_89H_90H) \ +__PMC_EV_ALIAS("BR_MISP_EXEC.INDIRECT_NEAR_CALL", IAP_EVENT_89H_A0H) \ __PMC_EV_ALIAS("BR_MISP_EXEC.ALL_BRANCHES", IAP_EVENT_89H_FFH) \ __PMC_EV_ALIAS("IDQ_UOPS_NOT_DELIVERED.CORE", IAP_EVENT_9CH_01H) \ __PMC_EV_ALIAS("UOPS_DISPATCHED_PORT.PORT_0", IAP_EVENT_A1H_01H) \ __PMC_EV_ALIAS("UOPS_DISPATCHED_PORT.PORT_1", IAP_EVENT_A1H_02H) \ __PMC_EV_ALIAS("UOPS_DISPATCHED_PORT.PORT_2_LD", IAP_EVENT_A1H_04H) \ __PMC_EV_ALIAS("UOPS_DISPATCHED_PORT.PORT_2_STA", IAP_EVENT_A1H_08H) \ __PMC_EV_ALIAS("UOPS_DISPATCHED_PORT.PORT_2", IAP_EVENT_A1H_0CH) \ __PMC_EV_ALIAS("UOPS_DISPATCHED_PORT.PORT_3_LD", IAP_EVENT_A1H_10H) \ __PMC_EV_ALIAS("UOPS_DISPATCHED_PORT.PORT_3_STA", IAP_EVENT_A1H_20H) \ __PMC_EV_ALIAS("UOPS_DISPATCHED_PORT.PORT_3", IAP_EVENT_A1H_30H) \ __PMC_EV_ALIAS("UOPS_DISPATCHED_PORT.PORT_4", IAP_EVENT_A1H_40H) \ __PMC_EV_ALIAS("UOPS_DISPATCHED_PORT.PORT_5", IAP_EVENT_A1H_80H) \ __PMC_EV_ALIAS("RESOURCE_STALLS.ANY", IAP_EVENT_A2H_01H) \ __PMC_EV_ALIAS("RESOURCE_STALLS.RS", IAP_EVENT_A2H_04H) \ __PMC_EV_ALIAS("RESOURCE_STALLS.SB", IAP_EVENT_A2H_08H) \ __PMC_EV_ALIAS("RESOURCE_STALLS.ROB", IAP_EVENT_A2H_10H) \ __PMC_EV_ALIAS("CYCLE_ACTIVITY.CYCLES_L2_PENDING", IAP_EVENT_A3H_01H) \ __PMC_EV_ALIAS("CYCLE_ACTIVITY.CYCLES_LDM_PENDING", IAP_EVENT_A3H_02H) \ __PMC_EV_ALIAS("CYCLE_ACTIVITY.CYCLES_NO_EXECUTE", IAP_EVENT_A3H_04H) \ __PMC_EV_ALIAS("CYCLE_ACTIVITY.CYCLES_L1D_PENDING", IAP_EVENT_A3H_08H) \ __PMC_EV_ALIAS("LSD.UOPS", IAP_EVENT_A8H_01H) \ __PMC_EV_ALIAS("DSB2MITE_SWITCHES.COUNT", IAP_EVENT_ABH_01H) \ __PMC_EV_ALIAS("DSB2MITE_SWITCHES.PENALTY_CYCLES", IAP_EVENT_ABH_02H) \ __PMC_EV_ALIAS("DSB_FILL.EXCEED_DSB_LINES", IAP_EVENT_ACH_08H) \ __PMC_EV_ALIAS("ITLB.ITLB_FLUSH", IAP_EVENT_AEH_01H) \ __PMC_EV_ALIAS("OFFCORE_REQUESTS.DEMAND_DATA_RD", IAP_EVENT_B0H_01H) \ __PMC_EV_ALIAS("OFFCORE_REQUESTS.DEMAND_CODE_RD", IAP_EVENT_B0H_02H) \ __PMC_EV_ALIAS("OFFCORE_REQUESTS.DEMAND_RFO", IAP_EVENT_B0H_04H) \ __PMC_EV_ALIAS("OFFCORE_REQUESTS.ALL_DATA_RD", IAP_EVENT_B0H_08H) \ __PMC_EV_ALIAS("UOPS_EXECUTED.THREAD", IAP_EVENT_B1H_01H) \ __PMC_EV_ALIAS("UOPS_EXECUTED.CORE", IAP_EVENT_B1H_02H) \ __PMC_EV_ALIAS("OFF_CORE_RESPONSE_0", IAP_EVENT_B7H_01H) \ __PMC_EV_ALIAS("OFF_CORE_RESPONSE_1", IAP_EVENT_BBH_01H) \ __PMC_EV_ALIAS("TLB_FLUSH.DTLB_THREAD", IAP_EVENT_BDH_01H) \ __PMC_EV_ALIAS("TLB_FLUSH.STLB_ANY", IAP_EVENT_BDH_20H) \ __PMC_EV_ALIAS("INST_RETIRED.ANY_P", IAP_EVENT_C0H_00H) \ __PMC_EV_ALIAS("INST_RETIRED.ALL", IAP_EVENT_C0H_01H) \ __PMC_EV_ALIAS("OTHER_ASSISTS.AVX_STORE", IAP_EVENT_C1H_08H) \ __PMC_EV_ALIAS("OTHER_ASSISTS.AVX_TO_SSE", IAP_EVENT_C1H_10H) \ __PMC_EV_ALIAS("OTHER_ASSISTS.SSE_TO_AVX", IAP_EVENT_C1H_20H) \ __PMC_EV_ALIAS("OTHER_ASSISTS.WB", IAP_EVENT_C1H_80H) \ __PMC_EV_ALIAS("UOPS_RETIRED.ALL", IAP_EVENT_C2H_01H) \ __PMC_EV_ALIAS("UOPS_RETIRED.RETIRE_SLOTS", IAP_EVENT_C2H_02H) \ __PMC_EV_ALIAS("MACHINE_CLEARS.MEMORY_ORDERING", IAP_EVENT_C3H_02H) \ __PMC_EV_ALIAS("MACHINE_CLEARS.SMC", IAP_EVENT_C3H_04H) \ __PMC_EV_ALIAS("MACHINE_CLEARS.MASKMOV", IAP_EVENT_C3H_20H) \ __PMC_EV_ALIAS("BR_INST_RETIRED.ALL_BRANCHES", IAP_EVENT_C4H_00H) \ __PMC_EV_ALIAS("BR_INST_RETIRED.CONDITIONAL", IAP_EVENT_C4H_01H) \ __PMC_EV_ALIAS("BR_INST_RETIRED.NEAR_CALL", IAP_EVENT_C4H_02H) \ __PMC_EV_ALIAS("BR_INST_RETIRED.ALL_BRANCHES", IAP_EVENT_C4H_04H) \ __PMC_EV_ALIAS("BR_INST_RETIRED.NEAR_RETURN", IAP_EVENT_C4H_08H) \ __PMC_EV_ALIAS("BR_INST_RETIRED.NOT_TAKEN", IAP_EVENT_C4H_10H) \ __PMC_EV_ALIAS("BR_INST_RETIRED.NEAR_TAKEN", IAP_EVENT_C4H_20H) \ __PMC_EV_ALIAS("BR_INST_RETIRED.FAR_BRANCH", IAP_EVENT_C4H_40H) \ __PMC_EV_ALIAS("BR_MISP_RETIRED.ALL_BRANCHES", IAP_EVENT_C5H_00H) \ __PMC_EV_ALIAS("BR_MISP_RETIRED.CONDITIONAL", IAP_EVENT_C5H_01H) \ __PMC_EV_ALIAS("BR_MISP_RETIRED.NEAR_CALL", IAP_EVENT_C5H_02H) \ __PMC_EV_ALIAS("BR_MISP_RETIRED.ALL_BRANCHES", IAP_EVENT_C5H_04H) \ __PMC_EV_ALIAS("BR_MISP_RETIRED.NOT_TAKEN", IAP_EVENT_C5H_10H) \ __PMC_EV_ALIAS("BR_MISP_RETIRED.TAKEN", IAP_EVENT_C5H_20H) \ __PMC_EV_ALIAS("FP_ASSIST.X87_OUTPUT", IAP_EVENT_CAH_02H) \ __PMC_EV_ALIAS("FP_ASSIST.X87_INPUT", IAP_EVENT_CAH_04H) \ __PMC_EV_ALIAS("FP_ASSIST.SIMD_OUTPUT", IAP_EVENT_CAH_08H) \ __PMC_EV_ALIAS("FP_ASSIST.SIMD_INPUT", IAP_EVENT_CAH_10H) \ __PMC_EV_ALIAS("FP_ASSIST.ANY", IAP_EVENT_CAH_1EH) \ __PMC_EV_ALIAS("ROB_MISC_EVENTS.LBR_INSERTS", IAP_EVENT_CCH_20H) \ __PMC_EV_ALIAS("MEM_TRANS_RETIRED.LOAD_LATENCY", IAP_EVENT_CDH_01H) \ __PMC_EV_ALIAS("MEM_TRANS_RETIRED.PRECISE_STORE", IAP_EVENT_CDH_02H) \ __PMC_EV_ALIAS("MEM_UOP_RETIRED.LOADS", IAP_EVENT_D0H_01H) \ __PMC_EV_ALIAS("MEM_UOP_RETIRED.STORES", IAP_EVENT_D0H_02H) \ __PMC_EV_ALIAS("MEM_UOP_RETIRED.STLB_MISS", IAP_EVENT_D0H_10H) \ __PMC_EV_ALIAS("MEM_UOP_RETIRED.LOCK", IAP_EVENT_D0H_20H) \ __PMC_EV_ALIAS("MEM_UOP_RETIRED.SPLIT", IAP_EVENT_D0H_40H) \ __PMC_EV_ALIAS("MEM_UOP_RETIRED.SPLIT_STORES", IAP_EVENT_D0H_42H) \ __PMC_EV_ALIAS("MEM_UOP_RETIRED.ALL", IAP_EVENT_D0H_80H) \ __PMC_EV_ALIAS("MEM_UOP_RETIRED.ALL_LOADS", IAP_EVENT_D0H_81H) \ __PMC_EV_ALIAS("MEM_UOP_RETIRED.ALL_STORES", IAP_EVENT_D0H_82H) \ __PMC_EV_ALIAS("MEM_LOAD_UOPS_RETIRED.L1_HIT", IAP_EVENT_D1H_01H) \ __PMC_EV_ALIAS("MEM_LOAD_UOPS_RETIRED.L2_HIT", IAP_EVENT_D1H_02H) \ __PMC_EV_ALIAS("MEM_LOAD_UOPS_RETIRED.LLC_HIT", IAP_EVENT_D1H_04H) \ __PMC_EV_ALIAS("MEM_LOAD_UOPS_RETIRED.L1_MISS", IAP_EVENT_D1H_08H) \ __PMC_EV_ALIAS("MEM_LOAD_UOPS_RETIRED.L2_MISS", IAP_EVENT_D1H_10H) \ __PMC_EV_ALIAS("MEM_LOAD_UOPS_RETIRED.LLC_MISS", IAP_EVENT_D1H_20H) \ __PMC_EV_ALIAS("MEM_LOAD_UOPS_RETIRED.HIT_LFB", IAP_EVENT_D1H_40H) \ __PMC_EV_ALIAS("MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_MISS", \ IAP_EVENT_D2H_01H) \ __PMC_EV_ALIAS("MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HIT", \ IAP_EVENT_D2H_02H) \ __PMC_EV_ALIAS("MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HITM", \ IAP_EVENT_D2H_04H) \ __PMC_EV_ALIAS("MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_NONE", \ IAP_EVENT_D2H_08H) \ __PMC_EV_ALIAS("MEM_LOAD_UOPS_LLC_HIT_RETIRED.ALL", \ IAP_EVENT_D2H_0FH) \ __PMC_EV_ALIAS("MEM_LOAD_UOPS_LLC_MISS_RETIRED.LOCAL_DRAM", \ IAP_EVENT_D3H_01H) \ __PMC_EV_ALIAS("BACLEARS.ANY", IAP_EVENT_E6H_1FH) \ __PMC_EV_ALIAS("L2_TRANS.DEMAND_DATA_RD", IAP_EVENT_F0H_01H) \ __PMC_EV_ALIAS("L2_TRANS.RFO", IAP_EVENT_F0H_02H) \ __PMC_EV_ALIAS("L2_TRANS.CODE_RD", IAP_EVENT_F0H_04H) \ __PMC_EV_ALIAS("L2_TRANS.ALL_PF", IAP_EVENT_F0H_08H) \ __PMC_EV_ALIAS("L2_TRANS.L1D_WB", IAP_EVENT_F0H_10H) \ __PMC_EV_ALIAS("L2_TRANS.L2_FILL", IAP_EVENT_F0H_20H) \ __PMC_EV_ALIAS("L2_TRANS.L2_WB", IAP_EVENT_F0H_40H) \ __PMC_EV_ALIAS("L2_TRANS.ALL_REQUESTS", IAP_EVENT_F0H_80H) \ __PMC_EV_ALIAS("L2_LINES_IN.I", IAP_EVENT_F1H_01H) \ __PMC_EV_ALIAS("L2_LINES_IN.S", IAP_EVENT_F1H_02H) \ __PMC_EV_ALIAS("L2_LINES_IN.E", IAP_EVENT_F1H_04H) \ __PMC_EV_ALIAS("L2_LINES_IN.ALL", IAP_EVENT_F1H_07H) \ __PMC_EV_ALIAS("L2_LINES_OUT.DEMAND_CLEAN", IAP_EVENT_F2H_01H) \ __PMC_EV_ALIAS("L2_LINES_OUT.DEMAND_DIRTY", IAP_EVENT_F2H_02H) \ __PMC_EV_ALIAS("L2_LINES_OUT.PF_CLEAN", IAP_EVENT_F2H_04H) \ __PMC_EV_ALIAS("L2_LINES_OUT.PF_DIRTY", IAP_EVENT_F2H_08H) /* * Aliases for Ivy Bridge Xeon PMC events (325462-045US January 2013) */ #define __PMC_EV_ALIAS_IVYBRIDGE_XEON() \ __PMC_EV_ALIAS("LD_BLOCKS.STORE_FORWARD", IAP_EVENT_03H_02H) \ __PMC_EV_ALIAS("LD_BLOCKS.NO_SR", IAP_EVENT_03H_08H) \ __PMC_EV_ALIAS("MISALIGN_MEM_REF.LOADS", IAP_EVENT_05H_01H) \ __PMC_EV_ALIAS("MISALIGN_MEM_REF.STORES", IAP_EVENT_05H_02H) \ __PMC_EV_ALIAS("LD_BLOCKS_PARTIAL.ADDRESS_ALIAS", IAP_EVENT_07H_01H) \ __PMC_EV_ALIAS("INT_MISC.RECOVERY_CYCLES", IAP_EVENT_0DH_03H) \ __PMC_EV_ALIAS("DTLB_LOAD_MISSES.MISS_CAUSES_A_WALK", IAP_EVENT_08H_81H)\ __PMC_EV_ALIAS("DTLB_LOAD_MISSES.WALK_COMPLETED", IAP_EVENT_08H_82H) \ __PMC_EV_ALIAS("DTLB_LOAD_MISSES.WALK_DURATION", IAP_EVENT_08H_84H) \ __PMC_EV_ALIAS("DTLB_LOAD_MISSES.LARGE_PG_WALK_DURATION", \ IAP_EVENT_08H_88H) \ __PMC_EV_ALIAS("UOPS_ISSUED.ANY", IAP_EVENT_0EH_01H) \ __PMC_EV_ALIAS("UOPS_ISSUED.FLAGS_MERGE", IAP_EVENT_0EH_10H) \ __PMC_EV_ALIAS("UOPS_ISSUED.SLOW_LEA", IAP_EVENT_0EH_20H) \ __PMC_EV_ALIAS("UOPS_ISSUED.SINGLE_MUL", IAP_EVENT_0EH_40H) \ __PMC_EV_ALIAS("FP_COMP_OPS_EXE.X87", IAP_EVENT_10H_01H) \ __PMC_EV_ALIAS("FP_COMP_OPS_EXE.SSE_FP_PACKED_DOUBLE", \ IAP_EVENT_10H_10H) \ __PMC_EV_ALIAS("FP_COMP_OPS_EXE.SSE_FP_SCALAR_SINGLE", \ IAP_EVENT_10H_20H) \ __PMC_EV_ALIAS("FP_COMP_OPS_EXE.SSE_PACKED_SINGLE", IAP_EVENT_10H_40H) \ __PMC_EV_ALIAS("FP_COMP_OPS_EXE.SSE_SCALAR_DOUBLE", IAP_EVENT_10H_80H) \ __PMC_EV_ALIAS("SIMD_FP_256.PACKED_SINGLE", IAP_EVENT_11H_01H) \ __PMC_EV_ALIAS("SIMD_FP_256.PACKED_DOUBLE", IAP_EVENT_11H_02H) \ __PMC_EV_ALIAS("ARITH.FPU_DIV_ACTIVE", IAP_EVENT_14H_01H) \ __PMC_EV_ALIAS("L2_RQSTS.DEMAND_DATA_RD_HIT", IAP_EVENT_24H_01H) \ __PMC_EV_ALIAS("L2_RQSTS.ALL_DEMAND_DATA_RD", IAP_EVENT_24H_03H) \ __PMC_EV_ALIAS("L2_RQSTS.RFO_HITS", IAP_EVENT_24H_04H) \ __PMC_EV_ALIAS("L2_RQSTS.RFO_MISS", IAP_EVENT_24H_08H) \ __PMC_EV_ALIAS("L2_RQSTS.ALL_RFO", IAP_EVENT_24H_0CH) \ __PMC_EV_ALIAS("L2_RQSTS.CODE_RD_HIT", IAP_EVENT_24H_10H) \ __PMC_EV_ALIAS("L2_RQSTS.CODE_RD_MISS", IAP_EVENT_24H_20H) \ __PMC_EV_ALIAS("L2_RQSTS.ALL_CODE_RD", IAP_EVENT_24H_30H) \ __PMC_EV_ALIAS("L2_RQSTS.PF_HIT", IAP_EVENT_24H_40H) \ __PMC_EV_ALIAS("L2_RQSTS.PF_MISS", IAP_EVENT_24H_80H) \ __PMC_EV_ALIAS("L2_RQSTS.ALL_PF", IAP_EVENT_24H_C0H) \ __PMC_EV_ALIAS("L2_STORE_LOCK_RQSTS.MISS", IAP_EVENT_27H_01H) \ __PMC_EV_ALIAS("L2_STORE_LOCK_RQSTS.HIT_M", IAP_EVENT_27H_08H) \ __PMC_EV_ALIAS("L2_STORE_LOCK_RQSTS.ALL", IAP_EVENT_27H_0FH) \ __PMC_EV_ALIAS("L2_L1D_WB_RQSTS.MISS", IAP_EVENT_28H_01H) \ __PMC_EV_ALIAS("L2_L1D_WB_RQSTS.HIT_E", IAP_EVENT_28H_04H) \ __PMC_EV_ALIAS("L2_L1D_WB_RQSTS.HIT_M", IAP_EVENT_28H_08H) \ __PMC_EV_ALIAS("L2_L1D_WB_RQSTS.ALL", IAP_EVENT_28H_0FH) \ __PMC_EV_ALIAS("LONGEST_LAT_CACHE.REFERENCE", IAP_EVENT_2EH_4FH) \ __PMC_EV_ALIAS("LONGEST_LAT_CACHE.MISS", IAP_EVENT_2EH_41H) \ __PMC_EV_ALIAS("CPU_CLK_UNHALTED.THREAD_P", IAP_EVENT_3CH_00H) \ __PMC_EV_ALIAS("CPU_CLK_THREAD_UNHALTED.REF_XCLK", IAP_EVENT_3CH_01H) \ __PMC_EV_ALIAS("L1D_PEND_MISS.PENDING", IAP_EVENT_48H_01H) \ __PMC_EV_ALIAS("DTLB_STORE_MISSES.MISS_CAUSES_A_WALK", \ IAP_EVENT_49H_01H) \ __PMC_EV_ALIAS("DTLB_STORE_MISSES.WALK_COMPLETED", IAP_EVENT_49H_02H) \ __PMC_EV_ALIAS("DTLB_STORE_MISSES.WALK_DURATION", IAP_EVENT_49H_04H) \ __PMC_EV_ALIAS("DTLB_STORE_MISSES.STLB_HIT", IAP_EVENT_49H_10H) \ __PMC_EV_ALIAS("LOAD_HIT_PRE.SW_PF", IAP_EVENT_4CH_01H) \ __PMC_EV_ALIAS("LOAD_HIT_PRE.HW_PF", IAP_EVENT_4CH_02H) \ __PMC_EV_ALIAS("L1D.REPLACEMENT", IAP_EVENT_51H_01H) \ __PMC_EV_ALIAS("MOVE_ELIMINATION.INT_NOT_ELIMINATED", IAP_EVENT_58H_01H)\ __PMC_EV_ALIAS("MOVE_ELIMINATION.SIMD_NOT_ELIMINATED", \ IAP_EVENT_58H_02H) \ __PMC_EV_ALIAS("MOVE_ELIMINATION.INT_ELIMINATED", IAP_EVENT_58H_04H) \ __PMC_EV_ALIAS("MOVE_ELIMINATION.SIMD_ELIMINATED", IAP_EVENT_58H_08H) \ __PMC_EV_ALIAS("CPL_CYCLES.RING0", IAP_EVENT_5CH_01H) \ __PMC_EV_ALIAS("CPL_CYCLES.RING123", IAP_EVENT_5CH_02H) \ __PMC_EV_ALIAS("RS_EVENTS.EMPTY_CYCLES", IAP_EVENT_5EH_01H) \ __PMC_EV_ALIAS("DTLB_LOAD_MISSES.STLB_HIT", IAP_EVENT_5FH_04H) \ __PMC_EV_ALIAS("OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD", \ IAP_EVENT_60H_01H) \ __PMC_EV_ALIAS("OFFCORE_REQUESTS_OUTSTANDING.DEMAND_CODE_RD", \ IAP_EVENT_60H_02H) \ __PMC_EV_ALIAS("OFFCORE_REQUESTS_OUTSTANDING.DEMAND_RFO", \ IAP_EVENT_60H_04H) \ __PMC_EV_ALIAS("OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD", \ IAP_EVENT_60H_08H) \ __PMC_EV_ALIAS("LOCK_CYCLES.SPLIT_LOCK_UC_LOCK_DURATION", \ IAP_EVENT_63H_01H) \ __PMC_EV_ALIAS("LOCK_CYCLES.CACHE_LOCK_DURATION", IAP_EVENT_63H_02H) \ __PMC_EV_ALIAS("IDQ.EMPTY", IAP_EVENT_79H_02H) \ __PMC_EV_ALIAS("IDQ.MITE_UOPS", IAP_EVENT_79H_04H) \ __PMC_EV_ALIAS("IDQ.DSB_UOPS", IAP_EVENT_79H_08H) \ __PMC_EV_ALIAS("IDQ.MS_DSB_UOPS", IAP_EVENT_79H_10H) \ __PMC_EV_ALIAS("IDQ.MS_MITE_UOPS", IAP_EVENT_79H_20H) \ __PMC_EV_ALIAS("IDQ.MS_UOPS", IAP_EVENT_79H_30H) \ __PMC_EV_ALIAS("IDQ.ALL_DSB_CYCLES_ANY_UOPS", IAP_EVENT_79H_18H) \ __PMC_EV_ALIAS("IDQ.ALL_DSB_CYCLES_4_UOPS", IAP_EVENT_79H_18H) \ __PMC_EV_ALIAS("IDQ.ALL_MITE_CYCLES_ANY_UOPS", IAP_EVENT_79H_24H) \ __PMC_EV_ALIAS("IDQ.ALL_MITE_CYCLES_4_UOPS", IAP_EVENT_79H_24H) \ __PMC_EV_ALIAS("IDQ.MITE_ALL_UOPS", IAP_EVENT_79H_3CH) \ __PMC_EV_ALIAS("ICACHE.MISSES", IAP_EVENT_80H_02H) \ __PMC_EV_ALIAS("ICACHE.IFETCH_STALL", IAP_EVENT_80H_04H) \ __PMC_EV_ALIAS("ITLB_MISSES.MISS_CAUSES_A_WALK", IAP_EVENT_85H_01H) \ __PMC_EV_ALIAS("ITLB_MISSES.WALK_COMPLETED", IAP_EVENT_85H_02H) \ __PMC_EV_ALIAS("ITLB_MISSES.WALK_DURATION", IAP_EVENT_85H_04H) \ __PMC_EV_ALIAS("ITLB_MISSES.STLB_HIT", IAP_EVENT_85H_10H) \ __PMC_EV_ALIAS("ILD_STALL.LCP", IAP_EVENT_87H_01H) \ __PMC_EV_ALIAS("ILD_STALL.IQ_FULL", IAP_EVENT_87H_04H) \ -__PMC_EV_ALIAS("BR_INST_EXEC.COND", IAP_EVENT_88H_01H) \ -__PMC_EV_ALIAS("BR_INST_EXEC.DIRECT_JMP", IAP_EVENT_88H_02H) \ +__PMC_EV_ALIAS("BR_INST_EXEC.NONTAKEN_COND", IAP_EVENT_88H_41H) \ +__PMC_EV_ALIAS("BR_INST_EXEC.TAKEN_COND", IAP_EVENT_88H_81H) \ +__PMC_EV_ALIAS("BR_INST_EXEC.DIRECT_JMP", IAP_EVENT_88H_82H) \ __PMC_EV_ALIAS("BR_INST_EXEC.INDIRECT_JMP_NON_CALL_RET", \ - IAP_EVENT_88H_04H) \ -__PMC_EV_ALIAS("BR_INST_EXEC.RETURN_NEAR", IAP_EVENT_88H_08H) \ -__PMC_EV_ALIAS("BR_INST_EXEC.DIRECT_NEAR_CALL", IAP_EVENT_88H_10H) \ -__PMC_EV_ALIAS("BR_INST_EXEC.INDIRECT_NEAR_CALL", IAP_EVENT_88H_20H) \ -__PMC_EV_ALIAS("BR_INST_EXEC.NONTAKEN", IAP_EVENT_88H_40H) \ -__PMC_EV_ALIAS("BR_INST_EXEC.TAKEN", IAP_EVENT_88H_80H) \ + IAP_EVENT_88H_84H) \ +__PMC_EV_ALIAS("BR_INST_EXEC.RETURN_NEAR", IAP_EVENT_88H_88H) \ +__PMC_EV_ALIAS("BR_INST_EXEC.DIRECT_NEAR_CALL", IAP_EVENT_88H_90H) \ +__PMC_EV_ALIAS("BR_INST_EXEC.INDIRECT_NEAR_CALL", IAP_EVENT_88H_A0H) \ __PMC_EV_ALIAS("BR_INST_EXEC.ALL_BRANCHES", IAP_EVENT_88H_FFH) \ -__PMC_EV_ALIAS("BR_MISP_EXEC.COND", IAP_EVENT_89H_01H) \ +__PMC_EV_ALIAS("BR_MISP_EXEC.NONTAKEN_COND", IAP_EVENT_89H_41H) \ +__PMC_EV_ALIAS("BR_MISP_EXEC.TAKEN_COND", IAP_EVENT_89H_81H) \ __PMC_EV_ALIAS("BR_MISP_EXEC.INDIRECT_JMP_NON_CALL_RET", \ - IAP_EVENT_89H_04H) \ -__PMC_EV_ALIAS("BR_MISP_EXEC.RETURN_NEAR", IAP_EVENT_89H_08H) \ -__PMC_EV_ALIAS("BR_MISP_EXEC.DIRECT_NEAR_CALL", IAP_EVENT_89H_10H) \ -__PMC_EV_ALIAS("BR_MISP_EXEC.INDIRECT_NEAR_CALL", IAP_EVENT_89H_20H) \ -__PMC_EV_ALIAS("BR_MISP_EXEC.NONTAKEN", IAP_EVENT_89H_40H) \ -__PMC_EV_ALIAS("BR_MISP_EXEC.TAKEN", IAP_EVENT_89H_80H) \ + IAP_EVENT_89H_84H) \ +__PMC_EV_ALIAS("BR_MISP_EXEC.RETURN_NEAR", IAP_EVENT_89H_88H) \ +__PMC_EV_ALIAS("BR_MISP_EXEC.DIRECT_NEAR_CALL", IAP_EVENT_89H_90H) \ +__PMC_EV_ALIAS("BR_MISP_EXEC.INDIRECT_NEAR_CALL", IAP_EVENT_89H_A0H) \ __PMC_EV_ALIAS("BR_MISP_EXEC.ALL_BRANCHES", IAP_EVENT_89H_FFH) \ __PMC_EV_ALIAS("IDQ_UOPS_NOT_DELIVERED.CORE", IAP_EVENT_9CH_01H) \ __PMC_EV_ALIAS("UOPS_DISPATCHED_PORT.PORT_0", IAP_EVENT_A1H_01H) \ __PMC_EV_ALIAS("UOPS_DISPATCHED_PORT.PORT_1", IAP_EVENT_A1H_02H) \ __PMC_EV_ALIAS("UOPS_DISPATCHED_PORT.PORT_2_LD", IAP_EVENT_A1H_04H) \ __PMC_EV_ALIAS("UOPS_DISPATCHED_PORT.PORT_2_STA", IAP_EVENT_A1H_08H) \ __PMC_EV_ALIAS("UOPS_DISPATCHED_PORT.PORT_2", IAP_EVENT_A1H_0CH) \ __PMC_EV_ALIAS("UOPS_DISPATCHED_PORT.PORT_3_LD", IAP_EVENT_A1H_10H) \ __PMC_EV_ALIAS("UOPS_DISPATCHED_PORT.PORT_3_STA", IAP_EVENT_A1H_20H) \ __PMC_EV_ALIAS("UOPS_DISPATCHED_PORT.PORT_3", IAP_EVENT_A1H_30H) \ __PMC_EV_ALIAS("UOPS_DISPATCHED_PORT.PORT_4", IAP_EVENT_A1H_40H) \ __PMC_EV_ALIAS("UOPS_DISPATCHED_PORT.PORT_5", IAP_EVENT_A1H_80H) \ __PMC_EV_ALIAS("RESOURCE_STALLS.ANY", IAP_EVENT_A2H_01H) \ __PMC_EV_ALIAS("RESOURCE_STALLS.RS", IAP_EVENT_A2H_04H) \ __PMC_EV_ALIAS("RESOURCE_STALLS.SB", IAP_EVENT_A2H_08H) \ __PMC_EV_ALIAS("RESOURCE_STALLS.ROB", IAP_EVENT_A2H_10H) \ __PMC_EV_ALIAS("CYCLE_ACTIVITY.CYCLES_L2_PENDING", IAP_EVENT_A3H_01H) \ __PMC_EV_ALIAS("CYCLE_ACTIVITY.CYCLES_LDM_PENDING", IAP_EVENT_A3H_02H) \ __PMC_EV_ALIAS("CYCLE_ACTIVITY.CYCLES_NO_EXECUTE", IAP_EVENT_A3H_04H) \ __PMC_EV_ALIAS("CYCLE_ACTIVITY.CYCLES_L1D_PENDING", IAP_EVENT_A3H_08H) \ __PMC_EV_ALIAS("LSD.UOPS", IAP_EVENT_A8H_01H) \ __PMC_EV_ALIAS("DSB2MITE_SWITCHES.COUNT", IAP_EVENT_ABH_01H) \ __PMC_EV_ALIAS("DSB2MITE_SWITCHES.PENALTY_CYCLES", IAP_EVENT_ABH_02H) \ __PMC_EV_ALIAS("DSB_FILL.EXCEED_DSB_LINES", IAP_EVENT_ACH_08H) \ __PMC_EV_ALIAS("ITLB.ITLB_FLUSH", IAP_EVENT_AEH_01H) \ __PMC_EV_ALIAS("OFFCORE_REQUESTS.DEMAND_DATA_RD", IAP_EVENT_B0H_01H) \ __PMC_EV_ALIAS("OFFCORE_REQUESTS.DEMAND_CODE_RD", IAP_EVENT_B0H_02H) \ __PMC_EV_ALIAS("OFFCORE_REQUESTS.DEMAND_RFO", IAP_EVENT_B0H_04H) \ __PMC_EV_ALIAS("OFFCORE_REQUESTS.ALL_DATA_RD", IAP_EVENT_B0H_08H) \ __PMC_EV_ALIAS("UOPS_EXECUTED.THREAD", IAP_EVENT_B1H_01H) \ __PMC_EV_ALIAS("UOPS_EXECUTED.CORE", IAP_EVENT_B1H_02H) \ __PMC_EV_ALIAS("OFF_CORE_RESPONSE_0", IAP_EVENT_B7H_01H) \ __PMC_EV_ALIAS("OFF_CORE_RESPONSE_1", IAP_EVENT_BBH_01H) \ __PMC_EV_ALIAS("TLB_FLUSH.DTLB_THREAD", IAP_EVENT_BDH_01H) \ __PMC_EV_ALIAS("TLB_FLUSH.STLB_ANY", IAP_EVENT_BDH_20H) \ __PMC_EV_ALIAS("INST_RETIRED.ANY_P", IAP_EVENT_C0H_00H) \ __PMC_EV_ALIAS("INST_RETIRED.ALL", IAP_EVENT_C0H_01H) \ __PMC_EV_ALIAS("OTHER_ASSISTS.AVX_STORE", IAP_EVENT_C1H_08H) \ __PMC_EV_ALIAS("OTHER_ASSISTS.AVX_TO_SSE", IAP_EVENT_C1H_10H) \ __PMC_EV_ALIAS("OTHER_ASSISTS.SSE_TO_AVX", IAP_EVENT_C1H_20H) \ __PMC_EV_ALIAS("OTHER_ASSISTS.WB", IAP_EVENT_C1H_80H) \ __PMC_EV_ALIAS("UOPS_RETIRED.ALL", IAP_EVENT_C2H_01H) \ __PMC_EV_ALIAS("UOPS_RETIRED.RETIRE_SLOTS", IAP_EVENT_C2H_02H) \ __PMC_EV_ALIAS("MACHINE_CLEARS.MEMORY_ORDERING", IAP_EVENT_C3H_02H) \ __PMC_EV_ALIAS("MACHINE_CLEARS.SMC", IAP_EVENT_C3H_04H) \ __PMC_EV_ALIAS("MACHINE_CLEARS.MASKMOV", IAP_EVENT_C3H_20H) \ __PMC_EV_ALIAS("BR_INST_RETIRED.ALL_BRANCHES", IAP_EVENT_C4H_00H) \ __PMC_EV_ALIAS("BR_INST_RETIRED.CONDITIONAL", IAP_EVENT_C4H_01H) \ __PMC_EV_ALIAS("BR_INST_RETIRED.NEAR_CALL", IAP_EVENT_C4H_02H) \ __PMC_EV_ALIAS("BR_INST_RETIRED.ALL_BRANCHES", IAP_EVENT_C4H_04H) \ __PMC_EV_ALIAS("BR_INST_RETIRED.NEAR_RETURN", IAP_EVENT_C4H_08H) \ __PMC_EV_ALIAS("BR_INST_RETIRED.NOT_TAKEN", IAP_EVENT_C4H_10H) \ __PMC_EV_ALIAS("BR_INST_RETIRED.NEAR_TAKEN", IAP_EVENT_C4H_20H) \ __PMC_EV_ALIAS("BR_INST_RETIRED.FAR_BRANCH", IAP_EVENT_C4H_40H) \ __PMC_EV_ALIAS("BR_MISP_RETIRED.ALL_BRANCHES", IAP_EVENT_C5H_00H) \ __PMC_EV_ALIAS("BR_MISP_RETIRED.CONDITIONAL", IAP_EVENT_C5H_01H) \ __PMC_EV_ALIAS("BR_MISP_RETIRED.NEAR_CALL", IAP_EVENT_C5H_02H) \ __PMC_EV_ALIAS("BR_MISP_RETIRED.ALL_BRANCHES", IAP_EVENT_C5H_04H) \ __PMC_EV_ALIAS("BR_MISP_RETIRED.NOT_TAKEN", IAP_EVENT_C5H_10H) \ __PMC_EV_ALIAS("BR_MISP_RETIRED.TAKEN", IAP_EVENT_C5H_20H) \ __PMC_EV_ALIAS("FP_ASSIST.X87_OUTPUT", IAP_EVENT_CAH_02H) \ __PMC_EV_ALIAS("FP_ASSIST.X87_INPUT", IAP_EVENT_CAH_04H) \ __PMC_EV_ALIAS("FP_ASSIST.SIMD_OUTPUT", IAP_EVENT_CAH_08H) \ __PMC_EV_ALIAS("FP_ASSIST.SIMD_INPUT", IAP_EVENT_CAH_10H) \ __PMC_EV_ALIAS("FP_ASSIST.ANY", IAP_EVENT_CAH_1EH) \ __PMC_EV_ALIAS("ROB_MISC_EVENTS.LBR_INSERTS", IAP_EVENT_CCH_20H) \ __PMC_EV_ALIAS("MEM_TRANS_RETIRED.LOAD_LATENCY", IAP_EVENT_CDH_01H) \ __PMC_EV_ALIAS("MEM_TRANS_RETIRED.PRECISE_STORE", IAP_EVENT_CDH_02H) \ __PMC_EV_ALIAS("MEM_UOP_RETIRED.LOADS", IAP_EVENT_D0H_01H) \ __PMC_EV_ALIAS("MEM_UOP_RETIRED.STORES", IAP_EVENT_D0H_02H) \ __PMC_EV_ALIAS("MEM_UOP_RETIRED.STLB_MISS", IAP_EVENT_D0H_10H) \ __PMC_EV_ALIAS("MEM_UOP_RETIRED.LOCK", IAP_EVENT_D0H_20H) \ __PMC_EV_ALIAS("MEM_UOP_RETIRED.SPLIT", IAP_EVENT_D0H_40H) \ __PMC_EV_ALIAS("MEM_UOP_RETIRED.SPLIT_STORES", IAP_EVENT_D0H_42H) \ __PMC_EV_ALIAS("MEM_UOP_RETIRED.ALL", IAP_EVENT_D0H_80H) \ __PMC_EV_ALIAS("MEM_UOP_RETIRED.ALL_LOADS", IAP_EVENT_D0H_81H) \ __PMC_EV_ALIAS("MEM_UOP_RETIRED.ALL_STORES", IAP_EVENT_D0H_82H) \ __PMC_EV_ALIAS("MEM_LOAD_UOPS_RETIRED.L1_HIT", IAP_EVENT_D1H_01H) \ __PMC_EV_ALIAS("MEM_LOAD_UOPS_RETIRED.L2_HIT", IAP_EVENT_D1H_02H) \ __PMC_EV_ALIAS("MEM_LOAD_UOPS_RETIRED.LLC_HIT", IAP_EVENT_D1H_04H) \ __PMC_EV_ALIAS("MEM_LOAD_UOPS_RETIRED.L1_MISS", IAP_EVENT_D1H_08H) \ __PMC_EV_ALIAS("MEM_LOAD_UOPS_RETIRED.L2_MISS", IAP_EVENT_D1H_10H) \ __PMC_EV_ALIAS("MEM_LOAD_UOPS_RETIRED.LLC_MISS", IAP_EVENT_D1H_20H) \ __PMC_EV_ALIAS("MEM_LOAD_UOPS_RETIRED.HIT_LFB", IAP_EVENT_D1H_40H) \ __PMC_EV_ALIAS("MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_MISS", \ IAP_EVENT_D2H_01H) \ __PMC_EV_ALIAS("MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HIT", \ IAP_EVENT_D2H_02H) \ __PMC_EV_ALIAS("MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HITM", \ IAP_EVENT_D2H_04H) \ __PMC_EV_ALIAS("MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_NONE", \ IAP_EVENT_D2H_08H) \ __PMC_EV_ALIAS("MEM_LOAD_UOPS_LLC_MISS_RETIRED.LOCAL_DRAM", \ IAP_EVENT_D3H_01H) \ __PMC_EV_ALIAS("MEM_LOAD_UOPS_LLC_MISS_RETIRED.LOCAL_DRAM", \ IAP_EVENT_D3H_03H) \ __PMC_EV_ALIAS("MEM_LOAD_UOPS_LLC_MISS_RETIRED.REMOTE_DRAM", \ IAP_EVENT_D3H_0CH) \ __PMC_EV_ALIAS("MEM_LOAD_UOPS_LLC_MISS_RETIRED.REMOTE_HITM", \ IAP_EVENT_D3H_10H) \ __PMC_EV_ALIAS("MEM_LOAD_UOPS_LLC_MISS_RETIRED.REMOTE_FWD", \ IAP_EVENT_D3H_20H) \ __PMC_EV_ALIAS("BACLEARS.ANY", IAP_EVENT_E6H_1FH) \ __PMC_EV_ALIAS("L2_TRANS.DEMAND_DATA_RD", IAP_EVENT_F0H_01H) \ __PMC_EV_ALIAS("L2_TRANS.RFO", IAP_EVENT_F0H_02H) \ __PMC_EV_ALIAS("L2_TRANS.CODE_RD", IAP_EVENT_F0H_04H) \ __PMC_EV_ALIAS("L2_TRANS.ALL_PF", IAP_EVENT_F0H_08H) \ __PMC_EV_ALIAS("L2_TRANS.L1D_WB", IAP_EVENT_F0H_10H) \ __PMC_EV_ALIAS("L2_TRANS.L2_FILL", IAP_EVENT_F0H_20H) \ __PMC_EV_ALIAS("L2_TRANS.L2_WB", IAP_EVENT_F0H_40H) \ __PMC_EV_ALIAS("L2_TRANS.ALL_REQUESTS", IAP_EVENT_F0H_80H) \ __PMC_EV_ALIAS("L2_LINES_IN.I", IAP_EVENT_F1H_01H) \ __PMC_EV_ALIAS("L2_LINES_IN.S", IAP_EVENT_F1H_02H) \ __PMC_EV_ALIAS("L2_LINES_IN.E", IAP_EVENT_F1H_04H) \ __PMC_EV_ALIAS("L2_LINES_IN.ALL", IAP_EVENT_F1H_07H) \ __PMC_EV_ALIAS("L2_LINES_OUT.DEMAND_CLEAN", IAP_EVENT_F2H_01H) \ __PMC_EV_ALIAS("L2_LINES_OUT.DEMAND_DIRTY", IAP_EVENT_F2H_02H) \ __PMC_EV_ALIAS("L2_LINES_OUT.PF_CLEAN", IAP_EVENT_F2H_04H) \ __PMC_EV_ALIAS("L2_LINES_OUT.PF_DIRTY", IAP_EVENT_F2H_08H) \ __PMC_EV_ALIAS("L2_LINES_OUT.DIRTY_ALL", IAP_EVENT_F2H_0AH) /* * Aliases for Sandy Bridge PMC events (253669-039US May 2011) */ #define __PMC_EV_ALIAS_SANDYBRIDGE() \ __PMC_EV_ALIAS_INTEL_ARCHITECTURAL() \ __PMC_EV_ALIAS("LD_BLOCKS.DATA_UNKNOWN", IAP_EVENT_03H_01H) \ __PMC_EV_ALIAS("LD_BLOCKS.STORE_FORWARD", IAP_EVENT_03H_02H) \ __PMC_EV_ALIAS("LD_BLOCKS.NO_SR", IAP_EVENT_03H_08H) \ __PMC_EV_ALIAS("LD_BLOCKS.ALL_BLOCK", IAP_EVENT_03H_10H) \ __PMC_EV_ALIAS("MISALIGN_MEM_REF.LOADS", IAP_EVENT_05H_01H) \ __PMC_EV_ALIAS("MISALIGN_MEM_REF.STORES", IAP_EVENT_05H_02H) \ __PMC_EV_ALIAS("LD_BLOCKS_PARTIAL.ADDRESS_ALIAS", IAP_EVENT_07H_01H) \ __PMC_EV_ALIAS("LD_BLOCKS_PARTIAL.ALL_STA_BLOCK", IAP_EVENT_07H_08H) \ __PMC_EV_ALIAS("DTLB_LOAD_MISSES.MISS_CAUSES_A_WALK", IAP_EVENT_08H_01H)\ __PMC_EV_ALIAS("DTLB_LOAD_MISSES.WALK_COMPLETED", IAP_EVENT_08H_02H) \ __PMC_EV_ALIAS("DTLB_LOAD_MISSES.WALK_DURATION", IAP_EVENT_08H_04H) \ __PMC_EV_ALIAS("DTLB_LOAD_MISSES.STLB_HIT", IAP_EVENT_08H_10H) \ __PMC_EV_ALIAS("INT_MISC.RECOVERY_CYCLES", IAP_EVENT_0DH_03H) \ __PMC_EV_ALIAS("INT_MISC.RAT_STALL_CYCLES", IAP_EVENT_0DH_40H) \ __PMC_EV_ALIAS("UOPS_ISSUED.ANY", IAP_EVENT_0EH_01H) \ __PMC_EV_ALIAS("FP_COMP_OPS_EXE.X87", IAP_EVENT_10H_01H) \ __PMC_EV_ALIAS("FP_COMP_OPS_EXE.SSE_FP_PACKED_DOUBLE", \ IAP_EVENT_10H_10H) \ __PMC_EV_ALIAS("FP_COMP_OPS_EXE.SSE_FP_SCALAR_SINGLE", \ IAP_EVENT_10H_20H) \ __PMC_EV_ALIAS("FP_COMP_OPS_EXE.SSE_PACKED_SINGLE", IAP_EVENT_10H_40H) \ __PMC_EV_ALIAS("FP_COMP_OPS_EXE.SSE_SCALAR_DOUBLE", IAP_EVENT_10H_80H) \ __PMC_EV_ALIAS("SIMD_FP_256.PACKED_SINGLE", IAP_EVENT_11H_01H) \ __PMC_EV_ALIAS("SIMD_FP_256.PACKED_DOUBLE", IAP_EVENT_11H_02H) \ __PMC_EV_ALIAS("ARITH.FPU_DIV_ACTIVE", IAP_EVENT_14H_01H) \ __PMC_EV_ALIAS("INSTS_WRITTEN_TO_IQ.INSTS", IAP_EVENT_17H_01H) \ __PMC_EV_ALIAS("L2_RQSTS.DEMAND_DATA_RD_HIT", IAP_EVENT_24H_01H) \ __PMC_EV_ALIAS("L2_RQSTS.ALL_DEMAND_DATA_RD", IAP_EVENT_24H_03H) \ __PMC_EV_ALIAS("L2_RQSTS.RFO_HITS", IAP_EVENT_24H_04H) \ __PMC_EV_ALIAS("L2_RQSTS.RFO_MISS", IAP_EVENT_24H_08H) \ __PMC_EV_ALIAS("L2_RQSTS.ALL_RFO", IAP_EVENT_24H_0CH) \ __PMC_EV_ALIAS("L2_RQSTS.CODE_RD_HIT", IAP_EVENT_24H_10H) \ __PMC_EV_ALIAS("L2_RQSTS.CODE_RD_MISS", IAP_EVENT_24H_20H) \ __PMC_EV_ALIAS("L2_RQSTS.ALL_CODE_RD", IAP_EVENT_24H_30H) \ __PMC_EV_ALIAS("L2_RQSTS.PF_HIT", IAP_EVENT_24H_40H) \ __PMC_EV_ALIAS("L2_RQSTS.PF_MISS", IAP_EVENT_24H_80H) \ __PMC_EV_ALIAS("L2_RQSTS.ALL_PF", IAP_EVENT_24H_C0H) \ __PMC_EV_ALIAS("L2_STORE_LOCK_RQSTS.MISS", IAP_EVENT_27H_01H) \ __PMC_EV_ALIAS("L2_STORE_LOCK_RQSTS.HIT_E", IAP_EVENT_27H_04H) \ __PMC_EV_ALIAS("L2_STORE_LOCK_RQSTS.HIT_M", IAP_EVENT_27H_08H) \ __PMC_EV_ALIAS("L2_STORE_LOCK_RQSTS.ALL", IAP_EVENT_27H_0FH) \ __PMC_EV_ALIAS("L2_L1D_WB_RQSTS.HIT_E", IAP_EVENT_28H_04H) \ __PMC_EV_ALIAS("L2_L1D_WB_RQSTS.HIT_M", IAP_EVENT_28H_08H) \ __PMC_EV_ALIAS("LONGEST_LAT_CACHE.REFERENCE", IAP_EVENT_2EH_4FH) \ __PMC_EV_ALIAS("LONGEST_LAT_CACHE.MISS", IAP_EVENT_2EH_41H) \ __PMC_EV_ALIAS("CPU_CLK_UNHALTED.THREAD_P", IAP_EVENT_3CH_00H) \ __PMC_EV_ALIAS("CPU_CLK_THREAD_UNHALTED.REF_XCLK", IAP_EVENT_3CH_01H) \ __PMC_EV_ALIAS("L1D_PEND_MISS.PENDING", IAP_EVENT_48H_01H) \ __PMC_EV_ALIAS("DTLB_STORE_MISSES.MISS_CAUSES_A_WALK", \ IAP_EVENT_49H_01H) \ __PMC_EV_ALIAS("DTLB_STORE_MISSES.WALK_COMPLETED", IAP_EVENT_49H_02H) \ __PMC_EV_ALIAS("DTLB_STORE_MISSES.WALK_DURATION", IAP_EVENT_49H_04H) \ __PMC_EV_ALIAS("DTLB_STORE_MISSES.STLB_HIT", IAP_EVENT_49H_10H) \ __PMC_EV_ALIAS("LOAD_HIT_PRE.SW_PF", IAP_EVENT_4CH_01H) \ __PMC_EV_ALIAS("LOAD_HIT_PRE.HW_PF", IAP_EVENT_4CH_02H) \ __PMC_EV_ALIAS("HW_PRE_REQ.DL1_MISS", IAP_EVENT_4EH_02H) \ __PMC_EV_ALIAS("L1D.REPLACEMENT", IAP_EVENT_51H_01H) \ __PMC_EV_ALIAS("L1D.ALLOCATED_IN_M", IAP_EVENT_51H_02H) \ __PMC_EV_ALIAS("L1D.EVICTION", IAP_EVENT_51H_04H) \ __PMC_EV_ALIAS("L1D.ALL_M_REPLACEMENT", IAP_EVENT_51H_08H) \ __PMC_EV_ALIAS("PARTIAL_RAT_STALLS.FLAGS_MERGE_UOP", IAP_EVENT_59H_20H) \ __PMC_EV_ALIAS("PARTIAL_RAT_STALLS.SLOW_LEA_WINDOW", IAP_EVENT_59H_40H) \ __PMC_EV_ALIAS("PARTIAL_RAT_STALLS.MUL_SINGLE_UOP", IAP_EVENT_59H_80H) \ __PMC_EV_ALIAS("RESOURCE_STALLS2.ALL_FL_EMPTY", IAP_EVENT_5BH_0CH) \ __PMC_EV_ALIAS("RESOURCE_STALLS2.ALL_PRF_CONTROL", IAP_EVENT_5BH_0FH) \ __PMC_EV_ALIAS("RESOURCE_STALLS2.BOB_FULL", IAP_EVENT_5BH_40H) \ __PMC_EV_ALIAS("RESOURCE_STALLS2.OOO_RSRC", IAP_EVENT_5BH_4FH) \ __PMC_EV_ALIAS("CPL_CYCLES.RING0", IAP_EVENT_5CH_01H) \ __PMC_EV_ALIAS("CPL_CYCLES.RING123", IAP_EVENT_5CH_02H) \ __PMC_EV_ALIAS("RS_EVENTS.EMPTY_CYCLES", IAP_EVENT_5EH_01H) \ __PMC_EV_ALIAS("OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD", \ IAP_EVENT_60H_01H) \ __PMC_EV_ALIAS("OFFCORE_REQUESTS_OUTSTANDING.DEMAND_RFO", \ IAP_EVENT_60H_04H) \ __PMC_EV_ALIAS("OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD", \ IAP_EVENT_60H_08H) \ __PMC_EV_ALIAS("LOCK_CYCLES.SPLIT_LOCK_UC_LOCK_DURATION", \ IAP_EVENT_63H_01H) \ __PMC_EV_ALIAS("LOCK_CYCLES.CACHE_LOCK_DURATION", IAP_EVENT_63H_02H) \ __PMC_EV_ALIAS("IDQ.EMPTY", IAP_EVENT_79H_02H) \ __PMC_EV_ALIAS("IDQ.MITE_UOPS", IAP_EVENT_79H_04H) \ __PMC_EV_ALIAS("IDQ.DSB_UOPS", IAP_EVENT_79H_08H) \ __PMC_EV_ALIAS("IDQ.MS_DSB_UOPS", IAP_EVENT_79H_10H) \ __PMC_EV_ALIAS("IDQ.MS_MITE_UOPS", IAP_EVENT_79H_20H) \ __PMC_EV_ALIAS("IDQ.MS_UOPS", IAP_EVENT_79H_30H) \ __PMC_EV_ALIAS("ICACHE.MISSES", IAP_EVENT_80H_02H) \ __PMC_EV_ALIAS("ITLB_MISSES.MISS_CAUSES_A_WALK", IAP_EVENT_85H_01H) \ __PMC_EV_ALIAS("ITLB_MISSES.WALK_COMPLETED", IAP_EVENT_85H_02H) \ __PMC_EV_ALIAS("ITLB_MISSES.WALK_DURATION", IAP_EVENT_85H_04H) \ __PMC_EV_ALIAS("ITLB_MISSES.STLB_HIT", IAP_EVENT_85H_10H) \ __PMC_EV_ALIAS("ILD_STALL.LCP", IAP_EVENT_87H_01H) \ __PMC_EV_ALIAS("ILD_STALL.IQ_FULL", IAP_EVENT_87H_04H) \ -__PMC_EV_ALIAS("BR_INST_EXEC.COND", IAP_EVENT_88H_01H) \ -__PMC_EV_ALIAS("BR_INST_EXEC.DIRECT_JMP", IAP_EVENT_88H_02H) \ +__PMC_EV_ALIAS("BR_INST_EXEC.NONTAKEN_COND", IAP_EVENT_88H_41H) \ +__PMC_EV_ALIAS("BR_INST_EXEC.TAKEN_COND", IAP_EVENT_88H_81H) \ +__PMC_EV_ALIAS("BR_INST_EXEC.DIRECT_JMP", IAP_EVENT_88H_82H) \ __PMC_EV_ALIAS("BR_INST_EXEC.INDIRECT_JMP_NON_CALL_RET", \ - IAP_EVENT_88H_04H) \ -__PMC_EV_ALIAS("BR_INST_EXEC.RETURN_NEAR", IAP_EVENT_88H_08H) \ -__PMC_EV_ALIAS("BR_INST_EXEC.DIRECT_NEAR_CALL", IAP_EVENT_88H_10H) \ -__PMC_EV_ALIAS("BR_INST_EXEC.INDIRECT_NEAR_CALL", IAP_EVENT_88H_20H) \ -__PMC_EV_ALIAS("BR_INST_EXEC.NONTAKEN", IAP_EVENT_88H_40H) \ -__PMC_EV_ALIAS("BR_INST_EXEC.TAKEN", IAP_EVENT_88H_80H) \ -__PMC_EV_ALIAS("BR_INST_EXE.ALL_BRANCHES", IAP_EVENT_88H_FFH) \ -__PMC_EV_ALIAS("BR_MISP_EXEC.COND", IAP_EVENT_89H_01H) \ + IAP_EVENT_88H_84H) \ +__PMC_EV_ALIAS("BR_INST_EXEC.RETURN_NEAR", IAP_EVENT_88H_88H) \ +__PMC_EV_ALIAS("BR_INST_EXEC.DIRECT_NEAR_CALL", IAP_EVENT_88H_90H) \ +__PMC_EV_ALIAS("BR_INST_EXEC.INDIRECT_NEAR_CALL", IAP_EVENT_88H_A0H) \ +__PMC_EV_ALIAS("BR_INST_EXEC.ALL_BRANCHES", IAP_EVENT_88H_FFH) \ +__PMC_EV_ALIAS("BR_MISP_EXEC.NONTAKEN_COND", IAP_EVENT_89H_41H) \ +__PMC_EV_ALIAS("BR_MISP_EXEC.TAKEN_COND", IAP_EVENT_89H_81H) \ __PMC_EV_ALIAS("BR_MISP_EXEC.INDIRECT_JMP_NON_CALL_RET", \ - IAP_EVENT_89H_04H) \ -__PMC_EV_ALIAS("BR_MISP_EXEC.RETURN_NEAR", IAP_EVENT_89H_08H) \ -__PMC_EV_ALIAS("BR_MISP_EXEC.DIRECT_NEAR_CALL", IAP_EVENT_89H_10H) \ -__PMC_EV_ALIAS("BR_MISP_EXEC.INDIRECT_NEAR_CALL", IAP_EVENT_89H_20H) \ -__PMC_EV_ALIAS("BR_MISP_EXEC.NONTAKEN", IAP_EVENT_89H_40H) \ -__PMC_EV_ALIAS("BR_MISP_EXEC.TAKEN", IAP_EVENT_89H_80H) \ + IAP_EVENT_89H_84H) \ +__PMC_EV_ALIAS("BR_MISP_EXEC.RETURN_NEAR", IAP_EVENT_89H_88H) \ +__PMC_EV_ALIAS("BR_MISP_EXEC.DIRECT_NEAR_CALL", IAP_EVENT_89H_90H) \ +__PMC_EV_ALIAS("BR_MISP_EXEC.INDIRECT_NEAR_CALL", IAP_EVENT_89H_A0H) \ __PMC_EV_ALIAS("BR_MISP_EXEC.ALL_BRANCHES", IAP_EVENT_89H_FFH) \ __PMC_EV_ALIAS("IDQ_UOPS_NOT_DELIVERED.CORE", IAP_EVENT_9CH_01H) \ __PMC_EV_ALIAS("UOPS_DISPATCHED_PORT.PORT_0", IAP_EVENT_A1H_01H) \ __PMC_EV_ALIAS("UOPS_DISPATCHED_PORT.PORT_1", IAP_EVENT_A1H_02H) \ __PMC_EV_ALIAS("UOPS_DISPATCHED_PORT.PORT_2_LD", IAP_EVENT_A1H_04H) \ __PMC_EV_ALIAS("UOPS_DISPATCHED_PORT.PORT_2_STA", IAP_EVENT_A1H_08H) \ __PMC_EV_ALIAS("UOPS_DISPATCHED_PORT.PORT_2", IAP_EVENT_A1H_0CH) \ __PMC_EV_ALIAS("UOPS_DISPATCHED_PORT.PORT_3_LD", IAP_EVENT_A1H_10H) \ __PMC_EV_ALIAS("UOPS_DISPATCHED_PORT.PORT_3_STA", IAP_EVENT_A1H_20H) \ __PMC_EV_ALIAS("UOPS_DISPATCHED_PORT.PORT_3", IAP_EVENT_A1H_30H) \ __PMC_EV_ALIAS("UOPS_DISPATCHED_PORT.PORT_4", IAP_EVENT_A1H_40H) \ __PMC_EV_ALIAS("UOPS_DISPATCHED_PORT.PORT_5", IAP_EVENT_A1H_80H) \ __PMC_EV_ALIAS("RESOURCE_STALLS.ANY", IAP_EVENT_A2H_01H) \ __PMC_EV_ALIAS("RESOURCE_STALLS.LB", IAP_EVENT_A2H_04H) \ __PMC_EV_ALIAS("RESOURCE_STALLS.SB", IAP_EVENT_A2H_08H) \ __PMC_EV_ALIAS("RESOURCE_STALLS.ROB", IAP_EVENT_A2H_10H) \ __PMC_EV_ALIAS("RESOURCE_STALLS.FCSW", IAP_EVENT_A2H_20H) \ __PMC_EV_ALIAS("RESOURCE_STALLS.MXCSR", IAP_EVENT_A2H_40H) \ __PMC_EV_ALIAS("RESOURCE_STALLS.OTHER", IAP_EVENT_A2H_80H) \ __PMC_EV_ALIAS("LSD.UOPS", IAP_EVENT_A8H_01H) \ __PMC_EV_ALIAS("DSB2MITE_SWITCHES.COUNT", IAP_EVENT_ABH_01H) \ __PMC_EV_ALIAS("DSB2MITE_SWITCHES.PENALTY_CYCLES", IAP_EVENT_ABH_02H) \ __PMC_EV_ALIAS("DSB_FILL.OTHER_CANCEL", IAP_EVENT_ACH_02H) \ __PMC_EV_ALIAS("DSB_FILL.EXCEED_DSB_LINES", IAP_EVENT_ACH_08H) \ __PMC_EV_ALIAS("DSB_FILL.ALL_CANCEL", IAP_EVENT_ACH_0AH) \ __PMC_EV_ALIAS("ITLB.ITLB_FLUSH", IAP_EVENT_AEH_01H) \ __PMC_EV_ALIAS("OFFCORE_REQUESTS.DEMAND_DATA_RD", IAP_EVENT_B0H_01H) \ __PMC_EV_ALIAS("OFFCORE_REQUESTS.DEMAND_RFO", IAP_EVENT_B0H_04H) \ __PMC_EV_ALIAS("OFFCORE_REQUESTS.ALL_DATA_RD", IAP_EVENT_B0H_08H) \ __PMC_EV_ALIAS("UOPS_DISPATCHED.THREAD", IAP_EVENT_B1H_01H) \ __PMC_EV_ALIAS("UOPS_DISPATCHED.CORE", IAP_EVENT_B1H_02H) \ __PMC_EV_ALIAS("OFFCORE_REQUESTS_BUFFER.SQ_FULL", IAP_EVENT_B2H_01H) \ __PMC_EV_ALIAS("AGU_BYPASS_CANCEL.COUNT", IAP_EVENT_B6H_01H) \ __PMC_EV_ALIAS("OFF_CORE_RESPONSE_0", IAP_EVENT_B7H_01H) \ __PMC_EV_ALIAS("OFF_CORE_RESPONSE_1", IAP_EVENT_BBH_01H) \ __PMC_EV_ALIAS("TLB_FLUSH.DTLB_THREAD", IAP_EVENT_BDH_01H) \ __PMC_EV_ALIAS("TLB_FLUSH.STLB_ANY", IAP_EVENT_BDH_20H) \ __PMC_EV_ALIAS("L1D_BLOCKS.BANK_CONFLICT_CYCLES", IAP_EVENT_BFH_05H) \ __PMC_EV_ALIAS("INST_RETIRED.ANY_P", IAP_EVENT_C0H_00H) \ __PMC_EV_ALIAS("INST_RETIRED.PREC_DIST", IAP_EVENT_C0H_01H) \ __PMC_EV_ALIAS("INST_RETIRED.X87", IAP_EVENT_C0H_02H) \ __PMC_EV_ALIAS("OTHER_ASSISTS.ITLB_MISS_RETIRED", IAP_EVENT_C1H_02H) \ __PMC_EV_ALIAS("OTHER_ASSISTS.AVX_STORE", IAP_EVENT_C1H_08H) \ __PMC_EV_ALIAS("OTHER_ASSISTS.AVX_TO_SSE", IAP_EVENT_C1H_10H) \ __PMC_EV_ALIAS("OTHER_ASSISTS.SSE_TO_AVX", IAP_EVENT_C1H_20H) \ __PMC_EV_ALIAS("UOPS_RETIRED.ALL", IAP_EVENT_C2H_01H) \ __PMC_EV_ALIAS("UOPS_RETIRED.RETIRE_SLOTS", IAP_EVENT_C2H_02H) \ __PMC_EV_ALIAS("MACHINE_CLEARS.MEMORY_ORDERING", IAP_EVENT_C3H_02H) \ __PMC_EV_ALIAS("MACHINE_CLEARS.SMC", IAP_EVENT_C3H_04H) \ __PMC_EV_ALIAS("MACHINE_CLEARS.MASKMOV", IAP_EVENT_C3H_20H) \ __PMC_EV_ALIAS("BR_INST_RETIRED.ALL_BRANCH", IAP_EVENT_C4H_00H) \ __PMC_EV_ALIAS("BR_INST_RETIRED.CONDITIONAL", IAP_EVENT_C4H_01H) \ __PMC_EV_ALIAS("BR_INST_RETIRED.NEAR_CALL", IAP_EVENT_C4H_02H) \ __PMC_EV_ALIAS("BR_INST_RETIRED.ALL_BRANCHES", IAP_EVENT_C4H_04H) \ __PMC_EV_ALIAS("BR_INST_RETIRED.NEAR_RETURN", IAP_EVENT_C4H_08H) \ __PMC_EV_ALIAS("BR_INST_RETIRED.NOT_TAKEN", IAP_EVENT_C4H_10H) \ __PMC_EV_ALIAS("BR_INST_RETIRED.NEAR_TAKEN", IAP_EVENT_C4H_20H) \ __PMC_EV_ALIAS("BR_INST_RETIRED.FAR_BRANCH", IAP_EVENT_C4H_40H) \ __PMC_EV_ALIAS("BR_MISP_RETIRED.ALL_BRANCHES", IAP_EVENT_C5H_00H) \ __PMC_EV_ALIAS("BR_MISP_RETIRED.CONDITIONAL", IAP_EVENT_C5H_01H) \ __PMC_EV_ALIAS("BR_MISP_RETIRED.NEAR_CALL", IAP_EVENT_C5H_02H) \ __PMC_EV_ALIAS("BR_MISP_RETIRED.ALL_BRANCHES_PS", IAP_EVENT_C5H_04H) \ __PMC_EV_ALIAS("BR_MISP_RETIRED.NOT_TAKEN", IAP_EVENT_C5H_10H) \ __PMC_EV_ALIAS("BR_MISP_RETIRED.TAKEN", IAP_EVENT_C5H_20H) \ __PMC_EV_ALIAS("FP_ASSIST.X87_OUTPUT", IAP_EVENT_CAH_02H) \ __PMC_EV_ALIAS("FP_ASSIST.X87_INPUT", IAP_EVENT_CAH_04H) \ __PMC_EV_ALIAS("FP_ASSIST.SIMD_OUTPUT", IAP_EVENT_CAH_08H) \ __PMC_EV_ALIAS("FP_ASSIST.SIMD_INPUT", IAP_EVENT_CAH_10H) \ __PMC_EV_ALIAS("FP_ASSIST.ANY", IAP_EVENT_CAH_1EH) \ __PMC_EV_ALIAS("ROB_MISC_EVENTS.LBR_INSERTS", IAP_EVENT_CCH_20H) \ __PMC_EV_ALIAS("MEM_TRANS_RETIRED.LOAD_LATENCY", IAP_EVENT_CDH_01H) \ __PMC_EV_ALIAS("MEM_TRANS_RETIRED.PRECISE_STORE", IAP_EVENT_CDH_02H) \ __PMC_EV_ALIAS("MEM_UOP_RETIRED.STLB_MISS_LOADS", IAP_EVENT_D0H_11H) \ __PMC_EV_ALIAS("MEM_UOP_RETIRED.STLB_MISS_STORES", IAP_EVENT_D0H_12H) \ __PMC_EV_ALIAS("MEM_UOP_RETIRED.LOCK_LOADS", IAP_EVENT_D0H_21H) \ __PMC_EV_ALIAS("MEM_UOP_RETIRED.SPLIT_LOADS", IAP_EVENT_D0H_41H) \ __PMC_EV_ALIAS("MEM_UOP_RETIRED.SPLIT_STORES", IAP_EVENT_D0H_42H) \ __PMC_EV_ALIAS("MEM_UOP_RETIRED.ALL_LOADS", IAP_EVENT_D0H_81H) \ __PMC_EV_ALIAS("MEM_UOP_RETIRED.ALL_STORES", IAP_EVENT_D0H_82H) \ __PMC_EV_ALIAS("MEM_LOAD_UOPS_RETIRED.L1_HIT", IAP_EVENT_D1H_01H) \ __PMC_EV_ALIAS("MEM_LOAD_UOPS_RETIRED.L2_HIT", IAP_EVENT_D1H_02H) \ __PMC_EV_ALIAS("MEM_LOAD_UOPS_RETIRED.LLC_HIT", IAP_EVENT_D1H_04H) \ __PMC_EV_ALIAS("MEM_LOAD_UOPS_RETIRED.HIT_LFB", IAP_EVENT_D1H_40H) \ __PMC_EV_ALIAS("MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_MISS", \ IAP_EVENT_D2H_01H) \ __PMC_EV_ALIAS("MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HIT", \ IAP_EVENT_D2H_02H) \ __PMC_EV_ALIAS("MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HITM", \ IAP_EVENT_D2H_04H) \ __PMC_EV_ALIAS("MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_NONE", \ IAP_EVENT_D2H_08H) \ __PMC_EV_ALIAS("MEM_LOAD_UOPS_MISC_RETIRED.LLC_MISS", \ IAP_EVENT_D4H_02H) \ __PMC_EV_ALIAS("L2_TRANS.DEMAND_DATA_RD", IAP_EVENT_F0H_01H) \ __PMC_EV_ALIAS("L2_TRANS.RFO", IAP_EVENT_F0H_02H) \ __PMC_EV_ALIAS("L2_TRANS.CODE_RD", IAP_EVENT_F0H_04H) \ __PMC_EV_ALIAS("L2_TRANS.ALL_PF", IAP_EVENT_F0H_08H) \ __PMC_EV_ALIAS("L2_TRANS.L1D_WB", IAP_EVENT_F0H_10H) \ __PMC_EV_ALIAS("L2_TRANS.L2_FILL", IAP_EVENT_F0H_20H) \ __PMC_EV_ALIAS("L2_TRANS.L2_WB", IAP_EVENT_F0H_40H) \ __PMC_EV_ALIAS("L2_TRANS.ALL_REQUESTS", IAP_EVENT_F0H_80H) \ __PMC_EV_ALIAS("L2_LINES_IN.I", IAP_EVENT_F1H_01H) \ __PMC_EV_ALIAS("L2_LINES_IN.S", IAP_EVENT_F1H_02H) \ __PMC_EV_ALIAS("L2_LINES_IN.E", IAP_EVENT_F1H_04H) \ __PMC_EV_ALIAS("L2_LINES_IN.ALL", IAP_EVENT_F1H_07H) \ __PMC_EV_ALIAS("L2_LINES_OUT.DEMAND_CLEAN", IAP_EVENT_F2H_01H) \ __PMC_EV_ALIAS("L2_LINES_OUT.DEMAND_DIRTY", IAP_EVENT_F2H_02H) \ __PMC_EV_ALIAS("L2_LINES_OUT.PF_CLEAN", IAP_EVENT_F2H_04H) \ __PMC_EV_ALIAS("L2_LINES_OUT.PF_DIRTY", IAP_EVENT_F2H_08H) \ __PMC_EV_ALIAS("L2_LINES_OUT.DIRTY_ALL", IAP_EVENT_F2H_0AH) \ __PMC_EV_ALIAS("SQ_MISC.SPLIT_LOCK", IAP_EVENT_F4H_10H) /* * Aliases for Sandy Bridge Xeon PMC events (253669-044US August 2012) */ #define __PMC_EV_ALIAS_SANDYBRIDGE_XEON() \ __PMC_EV_ALIAS_INTEL_ARCHITECTURAL() \ __PMC_EV_ALIAS("LD_BLOCKS.DATA_UNKNOWN", IAP_EVENT_03H_01H) \ __PMC_EV_ALIAS("LD_BLOCKS.STORE_FORWARD", IAP_EVENT_03H_02H) \ __PMC_EV_ALIAS("LD_BLOCKS.NO_SR", IAP_EVENT_03H_08H) \ __PMC_EV_ALIAS("LD_BLOCKS.ALL_BLOCK", IAP_EVENT_03H_10H) \ __PMC_EV_ALIAS("MISALIGN_MEM_REF.LOADS", IAP_EVENT_05H_01H) \ __PMC_EV_ALIAS("MISALIGN_MEM_REF.STORES", IAP_EVENT_05H_02H) \ __PMC_EV_ALIAS("LD_BLOCKS_PARTIAL.ADDRESS_ALIAS", IAP_EVENT_07H_01H) \ __PMC_EV_ALIAS("LD_BLOCKS_PARTIAL.ALL_STA_BLOCK", IAP_EVENT_07H_08H) \ __PMC_EV_ALIAS("DTLB_LOAD_MISSES.MISS_CAUSES_A_WALK", IAP_EVENT_08H_01H)\ __PMC_EV_ALIAS("DTLB_LOAD_MISSES.WALK_COMPLETED", IAP_EVENT_08H_02H) \ __PMC_EV_ALIAS("DTLB_LOAD_MISSES.WALK_DURATION", IAP_EVENT_08H_04H) \ __PMC_EV_ALIAS("DTLB_LOAD_MISSES.STLB_HIT", IAP_EVENT_08H_10H) \ __PMC_EV_ALIAS("INT_MISC.RECOVERY_CYCLES", IAP_EVENT_0DH_03H) \ __PMC_EV_ALIAS("INT_MISC.RAT_STALL_CYCLES", IAP_EVENT_0DH_40H) \ __PMC_EV_ALIAS("UOPS_ISSUED.ANY", IAP_EVENT_0EH_01H) \ __PMC_EV_ALIAS("FP_COMP_OPS_EXE.X87", IAP_EVENT_10H_01H) \ __PMC_EV_ALIAS("FP_COMP_OPS_EXE.SSE_FP_PACKED_DOUBLE", \ IAP_EVENT_10H_10H) \ __PMC_EV_ALIAS("FP_COMP_OPS_EXE.SSE_FP_SCALAR_SINGLE", \ IAP_EVENT_10H_20H) \ __PMC_EV_ALIAS("FP_COMP_OPS_EXE.SSE_PACKED_SINGLE", IAP_EVENT_10H_40H) \ __PMC_EV_ALIAS("FP_COMP_OPS_EXE.SSE_SCALAR_DOUBLE", IAP_EVENT_10H_80H) \ __PMC_EV_ALIAS("SIMD_FP_256.PACKED_SINGLE", IAP_EVENT_11H_01H) \ __PMC_EV_ALIAS("SIMD_FP_256.PACKED_DOUBLE", IAP_EVENT_11H_02H) \ __PMC_EV_ALIAS("ARITH.FPU_DIV_ACTIVE", IAP_EVENT_14H_01H) \ __PMC_EV_ALIAS("INSTS_WRITTEN_TO_IQ.INSTS", IAP_EVENT_17H_01H) \ __PMC_EV_ALIAS("L2_RQSTS.DEMAND_DATA_RD_HIT", IAP_EVENT_24H_01H) \ __PMC_EV_ALIAS("L2_RQSTS.ALL_DEMAND_DATA_RD", IAP_EVENT_24H_03H) \ __PMC_EV_ALIAS("L2_RQSTS.RFO_HITS", IAP_EVENT_24H_04H) \ __PMC_EV_ALIAS("L2_RQSTS.RFO_MISS", IAP_EVENT_24H_08H) \ __PMC_EV_ALIAS("L2_RQSTS.ALL_RFO", IAP_EVENT_24H_0CH) \ __PMC_EV_ALIAS("L2_RQSTS.CODE_RD_HIT", IAP_EVENT_24H_10H) \ __PMC_EV_ALIAS("L2_RQSTS.CODE_RD_MISS", IAP_EVENT_24H_20H) \ __PMC_EV_ALIAS("L2_RQSTS.ALL_CODE_RD", IAP_EVENT_24H_30H) \ __PMC_EV_ALIAS("L2_RQSTS.PF_HIT", IAP_EVENT_24H_40H) \ __PMC_EV_ALIAS("L2_RQSTS.PF_MISS", IAP_EVENT_24H_80H) \ __PMC_EV_ALIAS("L2_RQSTS.ALL_PF", IAP_EVENT_24H_C0H) \ __PMC_EV_ALIAS("L2_STORE_LOCK_RQSTS.MISS", IAP_EVENT_27H_01H) \ __PMC_EV_ALIAS("L2_STORE_LOCK_RQSTS.HIT_E", IAP_EVENT_27H_04H) \ __PMC_EV_ALIAS("L2_STORE_LOCK_RQSTS.HIT_M", IAP_EVENT_27H_08H) \ __PMC_EV_ALIAS("L2_STORE_LOCK_RQSTS.ALL", IAP_EVENT_27H_0FH) \ __PMC_EV_ALIAS("L2_L1D_WB_RQSTS.MISS", IAP_EVENT_28H_01H) \ __PMC_EV_ALIAS("L2_L1D_WB_RQSTS.HIT_S", IAP_EVENT_28H_02H) \ __PMC_EV_ALIAS("L2_L1D_WB_RQSTS.HIT_E", IAP_EVENT_28H_04H) \ __PMC_EV_ALIAS("L2_L1D_WB_RQSTS.HIT_M", IAP_EVENT_28H_08H) \ __PMC_EV_ALIAS("L2_L1D_WB_RQSTS.ALL", IAP_EVENT_28H_0FH) \ __PMC_EV_ALIAS("LONGEST_LAT_CACHE.REFERENCE", IAP_EVENT_2EH_4FH) \ __PMC_EV_ALIAS("LONGEST_LAT_CACHE.MISS", IAP_EVENT_2EH_41H) \ __PMC_EV_ALIAS("CPU_CLK_UNHALTED.THREAD_P", IAP_EVENT_3CH_00H) \ __PMC_EV_ALIAS("CPU_CLK_THREAD_UNHALTED.REF_XCLK", IAP_EVENT_3CH_01H) \ __PMC_EV_ALIAS("L1D_PEND_MISS.PENDING", IAP_EVENT_48H_01H) \ __PMC_EV_ALIAS("DTLB_STORE_MISSES.MISS_CAUSES_A_WALK", \ IAP_EVENT_49H_01H) \ __PMC_EV_ALIAS("DTLB_STORE_MISSES.WALK_COMPLETED", IAP_EVENT_49H_02H) \ __PMC_EV_ALIAS("DTLB_STORE_MISSES.WALK_DURATION", IAP_EVENT_49H_04H) \ __PMC_EV_ALIAS("DTLB_STORE_MISSES.STLB_HIT", IAP_EVENT_49H_10H) \ __PMC_EV_ALIAS("LOAD_HIT_PRE.SW_PF", IAP_EVENT_4CH_01H) \ __PMC_EV_ALIAS("LOAD_HIT_PRE.HW_PF", IAP_EVENT_4CH_02H) \ __PMC_EV_ALIAS("HW_PRE_REQ.DL1_MISS", IAP_EVENT_4EH_02H) \ __PMC_EV_ALIAS("L1D.REPLACEMENT", IAP_EVENT_51H_01H) \ __PMC_EV_ALIAS("L1D.ALLOCATED_IN_M", IAP_EVENT_51H_02H) \ __PMC_EV_ALIAS("L1D.EVICTION", IAP_EVENT_51H_04H) \ __PMC_EV_ALIAS("L1D.ALL_M_REPLACEMENT", IAP_EVENT_51H_08H) \ __PMC_EV_ALIAS("PARTIAL_RAT_STALLS.FLAGS_MERGE_UOP", IAP_EVENT_59H_20H) \ __PMC_EV_ALIAS("PARTIAL_RAT_STALLS.SLOW_LEA_WINDOW", IAP_EVENT_59H_40H) \ __PMC_EV_ALIAS("PARTIAL_RAT_STALLS.MUL_SINGLE_UOP", IAP_EVENT_59H_80H) \ __PMC_EV_ALIAS("RESOURCE_STALLS2.ALL_FL_EMPTY", IAP_EVENT_5BH_0CH) \ __PMC_EV_ALIAS("RESOURCE_STALLS2.ALL_PRF_CONTROL", IAP_EVENT_5BH_0FH) \ __PMC_EV_ALIAS("RESOURCE_STALLS2.BOB_FULL", IAP_EVENT_5BH_40H) \ __PMC_EV_ALIAS("RESOURCE_STALLS2.OOO_RSRC", IAP_EVENT_5BH_4FH) \ __PMC_EV_ALIAS("CPL_CYCLES.RING0", IAP_EVENT_5CH_01H) \ __PMC_EV_ALIAS("CPL_CYCLES.RING123", IAP_EVENT_5CH_02H) \ __PMC_EV_ALIAS("RS_EVENTS.EMPTY_CYCLES", IAP_EVENT_5EH_01H) \ __PMC_EV_ALIAS("OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD", \ IAP_EVENT_60H_01H) \ __PMC_EV_ALIAS("OFFCORE_REQUESTS_OUTSTANDING.DEMAND_RFO", \ IAP_EVENT_60H_04H) \ __PMC_EV_ALIAS("OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD", \ IAP_EVENT_60H_08H) \ __PMC_EV_ALIAS("LOCK_CYCLES.SPLIT_LOCK_UC_LOCK_DURATION", \ IAP_EVENT_63H_01H) \ __PMC_EV_ALIAS("LOCK_CYCLES.CACHE_LOCK_DURATION", IAP_EVENT_63H_02H) \ __PMC_EV_ALIAS("IDQ.EMPTY", IAP_EVENT_79H_02H) \ __PMC_EV_ALIAS("IDQ.MITE_UOPS", IAP_EVENT_79H_04H) \ __PMC_EV_ALIAS("IDQ.DSB_UOPS", IAP_EVENT_79H_08H) \ __PMC_EV_ALIAS("IDQ.MS_DSB_UOPS", IAP_EVENT_79H_10H) \ __PMC_EV_ALIAS("IDQ.MS_MITE_UOPS", IAP_EVENT_79H_20H) \ __PMC_EV_ALIAS("IDQ.MS_UOPS", IAP_EVENT_79H_30H) \ __PMC_EV_ALIAS("ICACHE.MISSES", IAP_EVENT_80H_02H) \ __PMC_EV_ALIAS("ITLB_MISSES.MISS_CAUSES_A_WALK", IAP_EVENT_85H_01H) \ __PMC_EV_ALIAS("ITLB_MISSES.WALK_COMPLETED", IAP_EVENT_85H_02H) \ __PMC_EV_ALIAS("ITLB_MISSES.WALK_DURATION", IAP_EVENT_85H_04H) \ __PMC_EV_ALIAS("ITLB_MISSES.STLB_HIT", IAP_EVENT_85H_10H) \ __PMC_EV_ALIAS("ILD_STALL.LCP", IAP_EVENT_87H_01H) \ __PMC_EV_ALIAS("ILD_STALL.IQ_FULL", IAP_EVENT_87H_04H) \ -__PMC_EV_ALIAS("BR_INST_EXEC.COND", IAP_EVENT_88H_01H) \ -__PMC_EV_ALIAS("BR_INST_EXEC.DIRECT_JMP", IAP_EVENT_88H_02H) \ +__PMC_EV_ALIAS("BR_INST_EXEC.NONTAKEN_COND", IAP_EVENT_88H_41H) \ +__PMC_EV_ALIAS("BR_INST_EXEC.TAKEN_COND", IAP_EVENT_88H_81H) \ +__PMC_EV_ALIAS("BR_INST_EXEC.DIRECT_JMP", IAP_EVENT_88H_82H) \ __PMC_EV_ALIAS("BR_INST_EXEC.INDIRECT_JMP_NON_CALL_RET", \ - IAP_EVENT_88H_04H) \ -__PMC_EV_ALIAS("BR_INST_EXEC.RETURN_NEAR", IAP_EVENT_88H_08H) \ -__PMC_EV_ALIAS("BR_INST_EXEC.DIRECT_NEAR_CALL", IAP_EVENT_88H_10H) \ -__PMC_EV_ALIAS("BR_INST_EXEC.INDIRECT_NEAR_CALL", IAP_EVENT_88H_20H) \ -__PMC_EV_ALIAS("BR_INST_EXEC.NONTAKEN", IAP_EVENT_88H_40H) \ -__PMC_EV_ALIAS("BR_INST_EXEC.TAKEN", IAP_EVENT_88H_80H) \ -__PMC_EV_ALIAS("BR_INST_EXE.ALL_BRANCHES", IAP_EVENT_88H_FFH) \ -__PMC_EV_ALIAS("BR_MISP_EXEC.COND", IAP_EVENT_89H_01H) \ + IAP_EVENT_88H_84H) \ +__PMC_EV_ALIAS("BR_INST_EXEC.RETURN_NEAR", IAP_EVENT_88H_88H) \ +__PMC_EV_ALIAS("BR_INST_EXEC.DIRECT_NEAR_CALL", IAP_EVENT_88H_90H) \ +__PMC_EV_ALIAS("BR_INST_EXEC.INDIRECT_NEAR_CALL", IAP_EVENT_88H_A0H) \ +__PMC_EV_ALIAS("BR_INST_EXEC.ALL_BRANCHES", IAP_EVENT_88H_FFH) \ +__PMC_EV_ALIAS("BR_MISP_EXEC.NONTAKEN_COND", IAP_EVENT_89H_41H) \ +__PMC_EV_ALIAS("BR_MISP_EXEC.TAKEN_COND", IAP_EVENT_89H_81H) \ __PMC_EV_ALIAS("BR_MISP_EXEC.INDIRECT_JMP_NON_CALL_RET", \ - IAP_EVENT_89H_04H) \ -__PMC_EV_ALIAS("BR_MISP_EXEC.RETURN_NEAR", IAP_EVENT_89H_08H) \ -__PMC_EV_ALIAS("BR_MISP_EXEC.DIRECT_NEAR_CALL", IAP_EVENT_89H_10H) \ -__PMC_EV_ALIAS("BR_MISP_EXEC.INDIRECT_NEAR_CALL", IAP_EVENT_89H_20H) \ -__PMC_EV_ALIAS("BR_MISP_EXEC.NONTAKEN", IAP_EVENT_89H_40H) \ -__PMC_EV_ALIAS("BR_MISP_EXEC.TAKEN", IAP_EVENT_89H_80H) \ -__PMC_EV_ALIAS("BR_MISP_EXEC.ALL_BRANCHES", IAP_EVENT_89H_FFH) \ + IAP_EVENT_89H_84H) \ +__PMC_EV_ALIAS("BR_MISP_EXEC.RETURN_NEAR", IAP_EVENT_89H_88H) \ +__PMC_EV_ALIAS("BR_MISP_EXEC.DIRECT_NEAR_CALL", IAP_EVENT_89H_90H) \ +__PMC_EV_ALIAS("BR_MISP_EXEC.INDIRECT_NEAR_CALL", IAP_EVENT_89H_A0H) \ +__PMC_EV_ALIAS("BR_MISP_EXEC.ALL_BRANCHES", IAP_EVENT_89H_FFH) \ __PMC_EV_ALIAS("IDQ_UOPS_NOT_DELIVERED.CORE", IAP_EVENT_9CH_01H) \ __PMC_EV_ALIAS("UOPS_DISPATCHED_PORT.PORT_0", IAP_EVENT_A1H_01H) \ __PMC_EV_ALIAS("UOPS_DISPATCHED_PORT.PORT_1", IAP_EVENT_A1H_02H) \ __PMC_EV_ALIAS("UOPS_DISPATCHED_PORT.PORT_2_LD", IAP_EVENT_A1H_04H) \ __PMC_EV_ALIAS("UOPS_DISPATCHED_PORT.PORT_2_STA", IAP_EVENT_A1H_08H) \ __PMC_EV_ALIAS("UOPS_DISPATCHED_PORT.PORT_2", IAP_EVENT_A1H_0CH) \ __PMC_EV_ALIAS("UOPS_DISPATCHED_PORT.PORT_3_LD", IAP_EVENT_A1H_10H) \ __PMC_EV_ALIAS("UOPS_DISPATCHED_PORT.PORT_3_STA", IAP_EVENT_A1H_20H) \ __PMC_EV_ALIAS("UOPS_DISPATCHED_PORT.PORT_3", IAP_EVENT_A1H_30H) \ __PMC_EV_ALIAS("UOPS_DISPATCHED_PORT.PORT_4", IAP_EVENT_A1H_40H) \ __PMC_EV_ALIAS("UOPS_DISPATCHED_PORT.PORT_5", IAP_EVENT_A1H_80H) \ __PMC_EV_ALIAS("RESOURCE_STALLS.ANY", IAP_EVENT_A2H_01H) \ __PMC_EV_ALIAS("RESOURCE_STALLS.LB", IAP_EVENT_A2H_02H) \ __PMC_EV_ALIAS("RESOURCE_STALLS.RS", IAP_EVENT_A2H_04H) \ __PMC_EV_ALIAS("RESOURCE_STALLS.SB", IAP_EVENT_A2H_08H) \ __PMC_EV_ALIAS("RESOURCE_STALLS.ROB", IAP_EVENT_A2H_10H) \ __PMC_EV_ALIAS("RESOURCE_STALLS.FCSW", IAP_EVENT_A2H_20H) \ __PMC_EV_ALIAS("RESOURCE_STALLS.MXCSR", IAP_EVENT_A2H_40H) \ __PMC_EV_ALIAS("RESOURCE_STALLS.OTHER", IAP_EVENT_A2H_80H) \ __PMC_EV_ALIAS("CYCLE_ACTIVITY.CYCLES_L2_PENDING", IAP_EVENT_A3H_01H) \ __PMC_EV_ALIAS("CYCLE_ACTIVITY.CYCLES_L1D_PENDING", IAP_EVENT_A3H_02H) \ __PMC_EV_ALIAS("CYCLE_ACTIVITY.CYCLES_NO_DISPATCH", IAP_EVENT_A3H_04H) \ __PMC_EV_ALIAS("LSD.UOPS", IAP_EVENT_A8H_01H) \ __PMC_EV_ALIAS("DSB2MITE_SWITCHES.COUNT", IAP_EVENT_ABH_01H) \ __PMC_EV_ALIAS("DSB2MITE_SWITCHES.PENALTY_CYCLES", IAP_EVENT_ABH_02H) \ __PMC_EV_ALIAS("DSB_FILL.OTHER_CANCEL", IAP_EVENT_ACH_02H) \ __PMC_EV_ALIAS("DSB_FILL.EXCEED_DSB_LINES", IAP_EVENT_ACH_08H) \ __PMC_EV_ALIAS("DSB_FILL.ALL_CANCEL", IAP_EVENT_ACH_0AH) \ __PMC_EV_ALIAS("ITLB.ITLB_FLUSH", IAP_EVENT_AEH_01H) \ __PMC_EV_ALIAS("OFFCORE_REQUESTS.DEMAND_DATA_RD", IAP_EVENT_B0H_01H) \ __PMC_EV_ALIAS("OFFCORE_REQUESTS.DEMAND_RFO", IAP_EVENT_B0H_04H) \ __PMC_EV_ALIAS("OFFCORE_REQUESTS.ALL_DATA_RD", IAP_EVENT_B0H_08H) \ __PMC_EV_ALIAS("UOPS_DISPATCHED.THREAD", IAP_EVENT_B1H_01H) \ __PMC_EV_ALIAS("UOPS_DISPATCHED.CORE", IAP_EVENT_B1H_02H) \ __PMC_EV_ALIAS("OFFCORE_REQUESTS_BUFFER.SQ_FULL", IAP_EVENT_B2H_01H) \ __PMC_EV_ALIAS("AGU_BYPASS_CANCEL.COUNT", IAP_EVENT_B6H_01H) \ __PMC_EV_ALIAS("OFF_CORE_RESPONSE_0", IAP_EVENT_B7H_01H) \ __PMC_EV_ALIAS("OFF_CORE_RESPONSE_1", IAP_EVENT_BBH_01H) \ __PMC_EV_ALIAS("TLB_FLUSH.DTLB_THREAD", IAP_EVENT_BDH_01H) \ __PMC_EV_ALIAS("TLB_FLUSH.STLB_ANY", IAP_EVENT_BDH_20H) \ __PMC_EV_ALIAS("L1D_BLOCKS.BANK_CONFLICT_CYCLES", IAP_EVENT_BFH_05H) \ __PMC_EV_ALIAS("INST_RETIRED.ANY_P", IAP_EVENT_C0H_00H) \ __PMC_EV_ALIAS("INST_RETIRED.ALL", IAP_EVENT_C0H_01H) \ __PMC_EV_ALIAS("OTHER_ASSISTS.ITLB_MISS_RETIRED", IAP_EVENT_C1H_02H) \ __PMC_EV_ALIAS("OTHER_ASSISTS.AVX_STORE", IAP_EVENT_C1H_08H) \ __PMC_EV_ALIAS("OTHER_ASSISTS.AVX_TO_SSE", IAP_EVENT_C1H_10H) \ __PMC_EV_ALIAS("OTHER_ASSISTS.SSE_TO_AVX", IAP_EVENT_C1H_20H) \ __PMC_EV_ALIAS("UOPS_RETIRED.ALL", IAP_EVENT_C2H_01H) \ __PMC_EV_ALIAS("UOPS_RETIRED.RETIRE_SLOTS", IAP_EVENT_C2H_02H) \ __PMC_EV_ALIAS("MACHINE_CLEARS.MEMORY_ORDERING", IAP_EVENT_C3H_02H) \ __PMC_EV_ALIAS("MACHINE_CLEARS.SMC", IAP_EVENT_C3H_04H) \ __PMC_EV_ALIAS("MACHINE_CLEARS.MASKMOV", IAP_EVENT_C3H_20H) \ __PMC_EV_ALIAS("BR_INST_RETIRED.ALL_BRANCH", IAP_EVENT_C4H_00H) \ __PMC_EV_ALIAS("BR_INST_RETIRED.CONDITIONAL", IAP_EVENT_C4H_01H) \ __PMC_EV_ALIAS("BR_INST_RETIRED.NEAR_CALL", IAP_EVENT_C4H_02H) \ __PMC_EV_ALIAS("BR_INST_RETIRED.ALL_BRANCHES", IAP_EVENT_C4H_04H) \ __PMC_EV_ALIAS("BR_INST_RETIRED.NEAR_RETURN", IAP_EVENT_C4H_08H) \ __PMC_EV_ALIAS("BR_INST_RETIRED.NOT_TAKEN", IAP_EVENT_C4H_10H) \ __PMC_EV_ALIAS("BR_INST_RETIRED.NEAR_TAKEN", IAP_EVENT_C4H_20H) \ __PMC_EV_ALIAS("BR_INST_RETIRED.FAR_BRANCH", IAP_EVENT_C4H_40H) \ __PMC_EV_ALIAS("BR_MISP_RETIRED.ALL_BRANCHES", IAP_EVENT_C5H_00H) \ __PMC_EV_ALIAS("BR_MISP_RETIRED.CONDITIONAL", IAP_EVENT_C5H_01H) \ __PMC_EV_ALIAS("BR_MISP_RETIRED.NEAR_CALL", IAP_EVENT_C5H_02H) \ __PMC_EV_ALIAS("BR_MISP_RETIRED.ALL_BRANCHES_PS", IAP_EVENT_C5H_04H) \ __PMC_EV_ALIAS("BR_MISP_RETIRED.NOT_TAKEN", IAP_EVENT_C5H_10H) \ __PMC_EV_ALIAS("BR_MISP_RETIRED.TAKEN", IAP_EVENT_C5H_20H) \ __PMC_EV_ALIAS("FP_ASSIST.X87_OUTPUT", IAP_EVENT_CAH_02H) \ __PMC_EV_ALIAS("FP_ASSIST.X87_INPUT", IAP_EVENT_CAH_04H) \ __PMC_EV_ALIAS("FP_ASSIST.SIMD_OUTPUT", IAP_EVENT_CAH_08H) \ __PMC_EV_ALIAS("FP_ASSIST.SIMD_INPUT", IAP_EVENT_CAH_10H) \ __PMC_EV_ALIAS("FP_ASSIST.ANY", IAP_EVENT_CAH_1EH) \ __PMC_EV_ALIAS("ROB_MISC_EVENTS.LBR_INSERTS", IAP_EVENT_CCH_20H) \ __PMC_EV_ALIAS("MEM_TRANS_RETIRED.LOAD_LATENCY", IAP_EVENT_CDH_01H) \ __PMC_EV_ALIAS("MEM_TRANS_RETIRED.PRECISE_STORE", IAP_EVENT_CDH_02H) \ __PMC_EV_ALIAS("MEM_UOP_RETIRED.STLB_MISS_LOADS", IAP_EVENT_D0H_11H) \ __PMC_EV_ALIAS("MEM_UOP_RETIRED.STLB_MISS_STORES", IAP_EVENT_D0H_12H) \ __PMC_EV_ALIAS("MEM_UOP_RETIRED.LOCK_LOADS", IAP_EVENT_D0H_21H) \ __PMC_EV_ALIAS("MEM_UOP_RETIRED.SPLIT_LOADS", IAP_EVENT_D0H_41H) \ __PMC_EV_ALIAS("MEM_UOP_RETIRED.SPLIT_STORES", IAP_EVENT_D0H_42H) \ __PMC_EV_ALIAS("MEM_UOP_RETIRED.ALL_LOADS", IAP_EVENT_D0H_81H) \ __PMC_EV_ALIAS("MEM_UOP_RETIRED.ALL_STORES", IAP_EVENT_D0H_82H) \ __PMC_EV_ALIAS("MEM_LOAD_UOPS_RETIRED.L1_HIT", IAP_EVENT_D1H_01H) \ __PMC_EV_ALIAS("MEM_LOAD_UOPS_RETIRED.L2_HIT", IAP_EVENT_D1H_02H) \ __PMC_EV_ALIAS("MEM_LOAD_UOPS_RETIRED.LLC_HIT", IAP_EVENT_D1H_04H) \ __PMC_EV_ALIAS("MEM_LOAD_UOPS_RETIRED.LLC_MISS", IAP_EVENT_D1H_20H) \ __PMC_EV_ALIAS("MEM_LOAD_UOPS_RETIRED.HIT_LFB", IAP_EVENT_D1H_40H) \ __PMC_EV_ALIAS("MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_MISS", \ IAP_EVENT_D2H_01H) \ __PMC_EV_ALIAS("MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HIT", \ IAP_EVENT_D2H_02H) \ __PMC_EV_ALIAS("MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HITM", \ IAP_EVENT_D2H_04H) \ __PMC_EV_ALIAS("MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_NONE", \ IAP_EVENT_D2H_08H) \ __PMC_EV_ALIAS("MEM_LOAD_UOPS_LLC_HIT_RETIRED.ALL", \ IAP_EVENT_D2H_0FH) \ __PMC_EV_ALIAS("MEM_LOAD_UOPS_LLC_MISS_RETIRED.LOCAL_DRAM", \ IAP_EVENT_D3H_01H) \ __PMC_EV_ALIAS("MEM_LOAD_UOPS_LLC_MISS_RETIRED.REMOTE_DRAM", \ IAP_EVENT_D3H_04H) \ __PMC_EV_ALIAS("MEM_LOAD_UOPS_MISC_RETIRED.LLC_MISS", \ IAP_EVENT_D4H_02H) \ __PMC_EV_ALIAS("BACLEARS.ANY", IAP_EVENT_E6H_01H) \ __PMC_EV_ALIAS("L2_TRANS.DEMAND_DATA_RD", IAP_EVENT_F0H_01H) \ __PMC_EV_ALIAS("L2_TRANS.RFO", IAP_EVENT_F0H_02H) \ __PMC_EV_ALIAS("L2_TRANS.CODE_RD", IAP_EVENT_F0H_04H) \ __PMC_EV_ALIAS("L2_TRANS.ALL_PF", IAP_EVENT_F0H_08H) \ __PMC_EV_ALIAS("L2_TRANS.L1D_WB", IAP_EVENT_F0H_10H) \ __PMC_EV_ALIAS("L2_TRANS.L2_FILL", IAP_EVENT_F0H_20H) \ __PMC_EV_ALIAS("L2_TRANS.L2_WB", IAP_EVENT_F0H_40H) \ __PMC_EV_ALIAS("L2_TRANS.ALL_REQUESTS", IAP_EVENT_F0H_80H) \ __PMC_EV_ALIAS("L2_LINES_IN.I", IAP_EVENT_F1H_01H) \ __PMC_EV_ALIAS("L2_LINES_IN.S", IAP_EVENT_F1H_02H) \ __PMC_EV_ALIAS("L2_LINES_IN.E", IAP_EVENT_F1H_04H) \ __PMC_EV_ALIAS("L2_LINES_IN.ALL", IAP_EVENT_F1H_07H) \ __PMC_EV_ALIAS("L2_LINES_OUT.DEMAND_CLEAN", IAP_EVENT_F2H_01H) \ __PMC_EV_ALIAS("L2_LINES_OUT.DEMAND_DIRTY", IAP_EVENT_F2H_02H) \ __PMC_EV_ALIAS("L2_LINES_OUT.PF_CLEAN", IAP_EVENT_F2H_04H) \ __PMC_EV_ALIAS("L2_LINES_OUT.PF_DIRTY", IAP_EVENT_F2H_08H) \ __PMC_EV_ALIAS("L2_LINES_OUT.DIRTY_ALL", IAP_EVENT_F2H_0AH) \ __PMC_EV_ALIAS("SQ_MISC.SPLIT_LOCK", IAP_EVENT_F4H_10H) /* timestamp counters. */ #define __PMC_EV_TSC() \ __PMC_EV(TSC, TSC) #define PMC_EV_TSC_FIRST PMC_EV_TSC_TSC #define PMC_EV_TSC_LAST PMC_EV_TSC_TSC /* * Software events are dynamicaly defined. */ #define PMC_EV_DYN_COUNT 0x1000 #define PMC_EV_SOFT_FIRST 0x20000 #define PMC_EV_SOFT_LAST (PMC_EV_SOFT_FIRST + PMC_EV_DYN_COUNT - 1) #define __PMC_EV_UCF() \ __PMC_EV(UCF, UCLOCK) #define PMC_EV_UCF_FIRST PMC_EV_UCF_UCLOCK #define PMC_EV_UCF_LAST PMC_EV_UCF_UCLOCK #define __PMC_EV_UCP() \ __PMC_EV(UCP, EVENT_00H_01H) \ __PMC_EV(UCP, EVENT_00H_02H) \ __PMC_EV(UCP, EVENT_00H_04H) \ __PMC_EV(UCP, EVENT_01H_01H) \ __PMC_EV(UCP, EVENT_01H_02H) \ __PMC_EV(UCP, EVENT_01H_04H) \ __PMC_EV(UCP, EVENT_02H_01H) \ __PMC_EV(UCP, EVENT_03H_01H) \ __PMC_EV(UCP, EVENT_03H_02H) \ __PMC_EV(UCP, EVENT_03H_04H) \ __PMC_EV(UCP, EVENT_03H_08H) \ __PMC_EV(UCP, EVENT_03H_10H) \ __PMC_EV(UCP, EVENT_03H_20H) \ __PMC_EV(UCP, EVENT_03H_40H) \ __PMC_EV(UCP, EVENT_04H_01H) \ __PMC_EV(UCP, EVENT_04H_02H) \ __PMC_EV(UCP, EVENT_04H_04H) \ __PMC_EV(UCP, EVENT_04H_08H) \ __PMC_EV(UCP, EVENT_04H_10H) \ __PMC_EV(UCP, EVENT_05H_01H) \ __PMC_EV(UCP, EVENT_05H_02H) \ __PMC_EV(UCP, EVENT_05H_04H) \ __PMC_EV(UCP, EVENT_06H_01H) \ __PMC_EV(UCP, EVENT_06H_02H) \ __PMC_EV(UCP, EVENT_06H_04H) \ __PMC_EV(UCP, EVENT_06H_08H) \ __PMC_EV(UCP, EVENT_06H_10H) \ __PMC_EV(UCP, EVENT_06H_20H) \ __PMC_EV(UCP, EVENT_07H_01H) \ __PMC_EV(UCP, EVENT_07H_02H) \ __PMC_EV(UCP, EVENT_07H_04H) \ __PMC_EV(UCP, EVENT_07H_08H) \ __PMC_EV(UCP, EVENT_07H_10H) \ __PMC_EV(UCP, EVENT_07H_20H) \ __PMC_EV(UCP, EVENT_07H_24H) \ __PMC_EV(UCP, EVENT_08H_01H) \ __PMC_EV(UCP, EVENT_08H_02H) \ __PMC_EV(UCP, EVENT_08H_04H) \ __PMC_EV(UCP, EVENT_08H_03H) \ __PMC_EV(UCP, EVENT_09H_01H) \ __PMC_EV(UCP, EVENT_09H_02H) \ __PMC_EV(UCP, EVENT_09H_04H) \ __PMC_EV(UCP, EVENT_09H_03H) \ __PMC_EV(UCP, EVENT_0AH_01H) \ __PMC_EV(UCP, EVENT_0AH_02H) \ __PMC_EV(UCP, EVENT_0AH_04H) \ __PMC_EV(UCP, EVENT_0AH_08H) \ __PMC_EV(UCP, EVENT_0AH_0FH) \ __PMC_EV(UCP, EVENT_0BH_01H) \ __PMC_EV(UCP, EVENT_0BH_02H) \ __PMC_EV(UCP, EVENT_0BH_04H) \ __PMC_EV(UCP, EVENT_0BH_08H) \ __PMC_EV(UCP, EVENT_0BH_10H) \ __PMC_EV(UCP, EVENT_0BH_1FH) \ __PMC_EV(UCP, EVENT_0CH_01H) \ __PMC_EV(UCP, EVENT_0CH_02H) \ __PMC_EV(UCP, EVENT_0CH_04H_E) \ __PMC_EV(UCP, EVENT_0CH_04H_F) \ __PMC_EV(UCP, EVENT_0CH_04H_M) \ __PMC_EV(UCP, EVENT_0CH_04H_S) \ __PMC_EV(UCP, EVENT_0CH_08H_E) \ __PMC_EV(UCP, EVENT_0CH_08H_F) \ __PMC_EV(UCP, EVENT_0CH_08H_M) \ __PMC_EV(UCP, EVENT_0CH_08H_S) \ __PMC_EV(UCP, EVENT_20H_01H) \ __PMC_EV(UCP, EVENT_20H_02H) \ __PMC_EV(UCP, EVENT_20H_04H) \ __PMC_EV(UCP, EVENT_20H_08H) \ __PMC_EV(UCP, EVENT_20H_10H) \ __PMC_EV(UCP, EVENT_20H_20H) \ __PMC_EV(UCP, EVENT_21H_01H) \ __PMC_EV(UCP, EVENT_21H_02H) \ __PMC_EV(UCP, EVENT_21H_04H) \ __PMC_EV(UCP, EVENT_22H_01H) \ __PMC_EV(UCP, EVENT_22H_02H) \ __PMC_EV(UCP, EVENT_22H_04H) \ __PMC_EV(UCP, EVENT_22H_08H) \ __PMC_EV(UCP, EVENT_22H_10H) \ __PMC_EV(UCP, EVENT_22H_20H) \ __PMC_EV(UCP, EVENT_22H_40H) \ __PMC_EV(UCP, EVENT_22H_80H) \ __PMC_EV(UCP, EVENT_23H_01H) \ __PMC_EV(UCP, EVENT_23H_02H) \ __PMC_EV(UCP, EVENT_23H_04H) \ __PMC_EV(UCP, EVENT_24H_02H) \ __PMC_EV(UCP, EVENT_24H_04H) \ __PMC_EV(UCP, EVENT_25H_01H) \ __PMC_EV(UCP, EVENT_25H_02H) \ __PMC_EV(UCP, EVENT_25H_04H) \ __PMC_EV(UCP, EVENT_26H_01H) \ __PMC_EV(UCP, EVENT_27H_01H) \ __PMC_EV(UCP, EVENT_27H_02H) \ __PMC_EV(UCP, EVENT_27H_04H) \ __PMC_EV(UCP, EVENT_27H_08H) \ __PMC_EV(UCP, EVENT_27H_10H) \ __PMC_EV(UCP, EVENT_27H_20H) \ __PMC_EV(UCP, EVENT_28H_01H) \ __PMC_EV(UCP, EVENT_28H_02H) \ __PMC_EV(UCP, EVENT_28H_04H) \ __PMC_EV(UCP, EVENT_28H_08H) \ __PMC_EV(UCP, EVENT_28H_10H) \ __PMC_EV(UCP, EVENT_28H_20H) \ __PMC_EV(UCP, EVENT_29H_01H) \ __PMC_EV(UCP, EVENT_29H_02H) \ __PMC_EV(UCP, EVENT_29H_04H) \ __PMC_EV(UCP, EVENT_29H_08H) \ __PMC_EV(UCP, EVENT_29H_10H) \ __PMC_EV(UCP, EVENT_29H_20H) \ __PMC_EV(UCP, EVENT_2AH_01H) \ __PMC_EV(UCP, EVENT_2AH_02H) \ __PMC_EV(UCP, EVENT_2AH_04H) \ __PMC_EV(UCP, EVENT_2AH_07H) \ __PMC_EV(UCP, EVENT_2BH_01H) \ __PMC_EV(UCP, EVENT_2BH_02H) \ __PMC_EV(UCP, EVENT_2BH_04H) \ __PMC_EV(UCP, EVENT_2BH_07H) \ __PMC_EV(UCP, EVENT_2CH_01H) \ __PMC_EV(UCP, EVENT_2CH_02H) \ __PMC_EV(UCP, EVENT_2CH_04H) \ __PMC_EV(UCP, EVENT_2CH_07H) \ __PMC_EV(UCP, EVENT_2DH_01H) \ __PMC_EV(UCP, EVENT_2DH_02H) \ __PMC_EV(UCP, EVENT_2DH_04H) \ __PMC_EV(UCP, EVENT_2DH_07H) \ __PMC_EV(UCP, EVENT_2EH_01H) \ __PMC_EV(UCP, EVENT_2EH_02H) \ __PMC_EV(UCP, EVENT_2EH_04H) \ __PMC_EV(UCP, EVENT_2EH_07H) \ __PMC_EV(UCP, EVENT_2FH_01H) \ __PMC_EV(UCP, EVENT_2FH_02H) \ __PMC_EV(UCP, EVENT_2FH_04H) \ __PMC_EV(UCP, EVENT_2FH_07H) \ __PMC_EV(UCP, EVENT_2FH_08H) \ __PMC_EV(UCP, EVENT_2FH_10H) \ __PMC_EV(UCP, EVENT_2FH_20H) \ __PMC_EV(UCP, EVENT_2FH_38H) \ __PMC_EV(UCP, EVENT_30H_01H) \ __PMC_EV(UCP, EVENT_30H_02H) \ __PMC_EV(UCP, EVENT_30H_04H) \ __PMC_EV(UCP, EVENT_30H_07H) \ __PMC_EV(UCP, EVENT_31H_01H) \ __PMC_EV(UCP, EVENT_31H_02H) \ __PMC_EV(UCP, EVENT_31H_04H) \ __PMC_EV(UCP, EVENT_31H_07H) \ __PMC_EV(UCP, EVENT_32H_01H) \ __PMC_EV(UCP, EVENT_32H_02H) \ __PMC_EV(UCP, EVENT_32H_04H) \ __PMC_EV(UCP, EVENT_32H_07H) \ __PMC_EV(UCP, EVENT_33H_01H) \ __PMC_EV(UCP, EVENT_33H_02H) \ __PMC_EV(UCP, EVENT_33H_04H) \ __PMC_EV(UCP, EVENT_33H_07H) \ __PMC_EV(UCP, EVENT_34H_01H) \ __PMC_EV(UCP, EVENT_34H_02H) \ __PMC_EV(UCP, EVENT_34H_04H) \ __PMC_EV(UCP, EVENT_34H_06H) \ __PMC_EV(UCP, EVENT_34H_08H) \ __PMC_EV(UCP, EVENT_34H_10H) \ __PMC_EV(UCP, EVENT_34H_20H) \ __PMC_EV(UCP, EVENT_34H_40H) \ __PMC_EV(UCP, EVENT_34H_80H) \ __PMC_EV(UCP, EVENT_35H_01H) \ __PMC_EV(UCP, EVENT_35H_02H) \ __PMC_EV(UCP, EVENT_35H_04H) \ __PMC_EV(UCP, EVENT_40H_01H) \ __PMC_EV(UCP, EVENT_40H_02H) \ __PMC_EV(UCP, EVENT_40H_04H) \ __PMC_EV(UCP, EVENT_40H_08H) \ __PMC_EV(UCP, EVENT_40H_10H) \ __PMC_EV(UCP, EVENT_40H_20H) \ __PMC_EV(UCP, EVENT_40H_07H) \ __PMC_EV(UCP, EVENT_40H_38H) \ __PMC_EV(UCP, EVENT_41H_01H) \ __PMC_EV(UCP, EVENT_41H_02H) \ __PMC_EV(UCP, EVENT_41H_04H) \ __PMC_EV(UCP, EVENT_41H_08H) \ __PMC_EV(UCP, EVENT_41H_10H) \ __PMC_EV(UCP, EVENT_41H_20H) \ __PMC_EV(UCP, EVENT_41H_07H) \ __PMC_EV(UCP, EVENT_41H_38H) \ __PMC_EV(UCP, EVENT_42H_01H) \ __PMC_EV(UCP, EVENT_42H_02H) \ __PMC_EV(UCP, EVENT_42H_04H) \ __PMC_EV(UCP, EVENT_42H_08H) \ __PMC_EV(UCP, EVENT_43H_01H) \ __PMC_EV(UCP, EVENT_43H_02H) \ __PMC_EV(UCP, EVENT_60H_01H) \ __PMC_EV(UCP, EVENT_60H_02H) \ __PMC_EV(UCP, EVENT_60H_04H) \ __PMC_EV(UCP, EVENT_61H_01H) \ __PMC_EV(UCP, EVENT_61H_02H) \ __PMC_EV(UCP, EVENT_61H_04H) \ __PMC_EV(UCP, EVENT_62H_01H) \ __PMC_EV(UCP, EVENT_62H_02H) \ __PMC_EV(UCP, EVENT_62H_04H) \ __PMC_EV(UCP, EVENT_63H_01H) \ __PMC_EV(UCP, EVENT_63H_02H) \ __PMC_EV(UCP, EVENT_63H_04H) \ __PMC_EV(UCP, EVENT_63H_08H) \ __PMC_EV(UCP, EVENT_63H_10H) \ __PMC_EV(UCP, EVENT_63H_20H) \ __PMC_EV(UCP, EVENT_64H_01H) \ __PMC_EV(UCP, EVENT_64H_02H) \ __PMC_EV(UCP, EVENT_64H_04H) \ __PMC_EV(UCP, EVENT_64H_08H) \ __PMC_EV(UCP, EVENT_64H_10H) \ __PMC_EV(UCP, EVENT_64H_20H) \ __PMC_EV(UCP, EVENT_65H_01H) \ __PMC_EV(UCP, EVENT_65H_02H) \ __PMC_EV(UCP, EVENT_65H_04H) \ __PMC_EV(UCP, EVENT_66H_01H) \ __PMC_EV(UCP, EVENT_66H_02H) \ __PMC_EV(UCP, EVENT_66H_04H) \ __PMC_EV(UCP, EVENT_67H_01H) \ __PMC_EV(UCP, EVENT_80H_01H) \ __PMC_EV(UCP, EVENT_80H_02H) \ __PMC_EV(UCP, EVENT_80H_04H) \ __PMC_EV(UCP, EVENT_80H_08H) \ __PMC_EV(UCP, EVENT_81H_01H) \ __PMC_EV(UCP, EVENT_81H_02H) \ __PMC_EV(UCP, EVENT_81H_04H) \ __PMC_EV(UCP, EVENT_81H_08H) \ __PMC_EV(UCP, EVENT_81H_20H) \ __PMC_EV(UCP, EVENT_81H_80H) \ __PMC_EV(UCP, EVENT_82H_01H) \ __PMC_EV(UCP, EVENT_83H_01H) \ __PMC_EV(UCP, EVENT_83H_02H) \ __PMC_EV(UCP, EVENT_83H_04H) \ __PMC_EV(UCP, EVENT_83H_08H) \ __PMC_EV(UCP, EVENT_84H_01H) \ __PMC_EV(UCP, EVENT_84H_02H) \ __PMC_EV(UCP, EVENT_84H_04H) \ __PMC_EV(UCP, EVENT_84H_08H) \ __PMC_EV(UCP, EVENT_85H_02H) \ __PMC_EV(UCP, EVENT_86H_01H) #define PMC_EV_UCP_FIRST PMC_EV_UCP_EVENT_00H_01H #define PMC_EV_UCP_LAST PMC_EV_UCP_EVENT_86H_01H /* * Aliases for Broadwell uncore PMC events */ #define __PMC_EV_ALIAS_BROADWELLUC() #define __PMC_EV_ALIAS_COREI7UC() \ __PMC_EV_ALIAS("GQ_CYCLES_FULL.READ_TRACKER", UCP_EVENT_00H_01H) \ __PMC_EV_ALIAS("GQ_CYCLES_FULL.WRITE_TRACKER", UCP_EVENT_00H_02H) \ __PMC_EV_ALIAS("GQ_CYCLES_FULL.PEER_PROBE_TRACKER", UCP_EVENT_00H_04H) \ __PMC_EV_ALIAS("GQ_CYCLES_NOT_EMPTY.READ_TRACKER", UCP_EVENT_01H_01H) \ __PMC_EV_ALIAS("GQ_CYCLES_NOT_EMPTY.WRITE_TRACKER", UCP_EVENT_01H_02H) \ __PMC_EV_ALIAS("GQ_CYCLES_NOT_EMPTY.PEER_PROBE_TRACKER", \ UCP_EVENT_01H_04H) \ __PMC_EV_ALIAS("GQ_ALLOC.READ_TRACKER", UCP_EVENT_03H_01H) \ __PMC_EV_ALIAS("GQ_ALLOC.RT_L3_MISS", UCP_EVENT_03H_02H) \ __PMC_EV_ALIAS("GQ_ALLOC.RT_TO_L3_RESP", UCP_EVENT_03H_04H) \ __PMC_EV_ALIAS("GQ_ALLOC.RT_TO_RTID_ACQUIRED", UCP_EVENT_03H_08H) \ __PMC_EV_ALIAS("GQ_ALLOC.WT_TO_RTID_ACQUIRED", UCP_EVENT_03H_10H) \ __PMC_EV_ALIAS("GQ_ALLOC.WRITE_TRACKER", UCP_EVENT_03H_20H) \ __PMC_EV_ALIAS("GQ_ALLOC.PEER_PROBE_TRACKER", UCP_EVENT_03H_40H) \ __PMC_EV_ALIAS("GQ_DATA.FROM_QPI", UCP_EVENT_04H_01H) \ __PMC_EV_ALIAS("GQ_DATA.FROM_QMC", UCP_EVENT_04H_02H) \ __PMC_EV_ALIAS("GQ_DATA.FROM_L3", UCP_EVENT_04H_04H) \ __PMC_EV_ALIAS("GQ_DATA.FROM_CORES_02", UCP_EVENT_04H_08H) \ __PMC_EV_ALIAS("GQ_DATA.FROM_CORES_13", UCP_EVENT_04H_10H) \ __PMC_EV_ALIAS("GQ_DATA.TO_QPI_QMC", UCP_EVENT_05H_01H) \ __PMC_EV_ALIAS("GQ_DATA.TO_L3", UCP_EVENT_05H_02H) \ __PMC_EV_ALIAS("GQ_DATA.TO_CORES", UCP_EVENT_05H_04H) \ __PMC_EV_ALIAS("SNP_RESP_TO_LOCAL_HOME.I_STATE", UCP_EVENT_06H_01H) \ __PMC_EV_ALIAS("SNP_RESP_TO_LOCAL_HOME.S_STATE", UCP_EVENT_06H_02H) \ __PMC_EV_ALIAS("SNP_RESP_TO_LOCAL_HOME.FWD_S_STATE", UCP_EVENT_06H_04H) \ __PMC_EV_ALIAS("SNP_RESP_TO_LOCAL_HOME.FWD_I_STATE", UCP_EVENT_06H_08H) \ __PMC_EV_ALIAS("SNP_RESP_TO_LOCAL_HOME.CONFLICT", UCP_EVENT_06H_10H) \ __PMC_EV_ALIAS("SNP_RESP_TO_LOCAL_HOME.WB", UCP_EVENT_06H_20H) \ __PMC_EV_ALIAS("SNP_RESP_TO_REMOTE_HOME.I_STATE", UCP_EVENT_07H_01H) \ __PMC_EV_ALIAS("SNP_RESP_TO_REMOTE_HOME.S_STATE", UCP_EVENT_07H_02H) \ __PMC_EV_ALIAS("SNP_RESP_TO_REMOTE_HOME.FWD_S_STATE", UCP_EVENT_07H_04H)\ __PMC_EV_ALIAS("SNP_RESP_TO_REMOTE_HOME.FWD_I_STATE", UCP_EVENT_07H_08H)\ __PMC_EV_ALIAS("SNP_RESP_TO_REMOTE_HOME.CONFLICT", UCP_EVENT_07H_10H) \ __PMC_EV_ALIAS("SNP_RESP_TO_REMOTE_HOME.WB", UCP_EVENT_07H_20H) \ __PMC_EV_ALIAS("SNP_RESP_TO_REMOTE_HOME.HITM", UCP_EVENT_07H_24H) \ __PMC_EV_ALIAS("L3_HITS.READ", UCP_EVENT_08H_01H) \ __PMC_EV_ALIAS("L3_HITS.WRITE", UCP_EVENT_08H_02H) \ __PMC_EV_ALIAS("L3_HITS.PROBE", UCP_EVENT_08H_04H) \ __PMC_EV_ALIAS("L3_HITS.ANY", UCP_EVENT_08H_03H) \ __PMC_EV_ALIAS("L3_MISS.READ", UCP_EVENT_09H_01H) \ __PMC_EV_ALIAS("L3_MISS.WRITE", UCP_EVENT_09H_02H) \ __PMC_EV_ALIAS("L3_MISS.PROBE", UCP_EVENT_09H_04H) \ __PMC_EV_ALIAS("L3_MISS.ANY", UCP_EVENT_09H_03H) \ __PMC_EV_ALIAS("L3_LINES_IN.M_STATE", UCP_EVENT_0AH_01H) \ __PMC_EV_ALIAS("L3_LINES_IN.E_STATE", UCP_EVENT_0AH_02H) \ __PMC_EV_ALIAS("L3_LINES_IN.S_STATE", UCP_EVENT_0AH_04H) \ __PMC_EV_ALIAS("L3_LINES_IN.F_STATE", UCP_EVENT_0AH_08H) \ __PMC_EV_ALIAS("L3_LINES_IN.ANY", UCP_EVENT_0AH_0FH) \ __PMC_EV_ALIAS("L3_LINES_OUT.M_STATE", UCP_EVENT_0BH_01H) \ __PMC_EV_ALIAS("L3_LINES_OUT.E_STATE", UCP_EVENT_0BH_02H) \ __PMC_EV_ALIAS("L3_LINES_OUT.S_STATE", UCP_EVENT_0BH_04H) \ __PMC_EV_ALIAS("L3_LINES_OUT.I_STATE", UCP_EVENT_0BH_08H) \ __PMC_EV_ALIAS("L3_LINES_OUT.F_STATE", UCP_EVENT_0BH_10H) \ __PMC_EV_ALIAS("L3_LINES_OUT.ANY", UCP_EVENT_0BH_1FH) \ __PMC_EV_ALIAS("QHL_REQUESTS.IOH_READS", UCP_EVENT_20H_01H) \ __PMC_EV_ALIAS("QHL_REQUESTS.IOH_WRITES", UCP_EVENT_20H_02H) \ __PMC_EV_ALIAS("QHL_REQUESTS.REMOTE_READS", UCP_EVENT_20H_04H) \ __PMC_EV_ALIAS("QHL_REQUESTS.REMOTE_WRITES", UCP_EVENT_20H_08H) \ __PMC_EV_ALIAS("QHL_REQUESTS.LOCAL_READS", UCP_EVENT_20H_10H) \ __PMC_EV_ALIAS("QHL_REQUESTS.LOCAL_WRITES", UCP_EVENT_20H_20H) \ __PMC_EV_ALIAS("QHL_CYCLES_FULL.IOH", UCP_EVENT_21H_01H) \ __PMC_EV_ALIAS("QHL_CYCLES_FULL.REMOTE", UCP_EVENT_21H_02H) \ __PMC_EV_ALIAS("QHL_CYCLES_FULL.LOCAL", UCP_EVENT_21H_04H) \ __PMC_EV_ALIAS("QHL_CYCLES_NOT_EMPTY.IOH", UCP_EVENT_22H_01H) \ __PMC_EV_ALIAS("QHL_CYCLES_NOT_EMPTY.REMOTE", UCP_EVENT_22H_02H) \ __PMC_EV_ALIAS("QHL_CYCLES_NOT_EMPTY.LOCAL", UCP_EVENT_22H_04H) \ __PMC_EV_ALIAS("QHL_OCCUPANCY.IOH", UCP_EVENT_23H_01H) \ __PMC_EV_ALIAS("QHL_OCCUPANCY.REMOTE", UCP_EVENT_23H_02H) \ __PMC_EV_ALIAS("QHL_OCCUPANCY.LOCAL", UCP_EVENT_23H_04H) \ __PMC_EV_ALIAS("QHL_ADDRESS_CONFLICTS.2WAY", UCP_EVENT_24H_02H) \ __PMC_EV_ALIAS("QHL_ADDRESS_CONFLICTS.3WAY", UCP_EVENT_24H_04H) \ __PMC_EV_ALIAS("QHL_CONFLICT_CYCLES.IOH", UCP_EVENT_25H_01H) \ __PMC_EV_ALIAS("QHL_CONFLICT_CYCLES.REMOTE", UCP_EVENT_25H_02H) \ __PMC_EV_ALIAS("QHL_CONFLICT_CYCLES.LOCAL", UCP_EVENT_25H_04H) \ __PMC_EV_ALIAS("QHL_TO_QMC_BYPASS", UCP_EVENT_26H_01H) \ __PMC_EV_ALIAS("QMC_NORMAL_FULL.READ.CH0", UCP_EVENT_27H_01H) \ __PMC_EV_ALIAS("QMC_NORMAL_FULL.READ.CH1", UCP_EVENT_27H_02H) \ __PMC_EV_ALIAS("QMC_NORMAL_FULL.READ.CH2", UCP_EVENT_27H_04H) \ __PMC_EV_ALIAS("QMC_NORMAL_FULL.WRITE.CH0", UCP_EVENT_27H_08H) \ __PMC_EV_ALIAS("QMC_NORMAL_FULL.WRITE.CH1", UCP_EVENT_27H_10H) \ __PMC_EV_ALIAS("QMC_NORMAL_FULL.WRITE.CH2", UCP_EVENT_27H_20H) \ __PMC_EV_ALIAS("QMC_ISOC_FULL.READ.CH0", UCP_EVENT_28H_01H) \ __PMC_EV_ALIAS("QMC_ISOC_FULL.READ.CH1", UCP_EVENT_28H_02H) \ __PMC_EV_ALIAS("QMC_ISOC_FULL.READ.CH2", UCP_EVENT_28H_04H) \ __PMC_EV_ALIAS("QMC_ISOC_FULL.WRITE.CH0", UCP_EVENT_28H_08H) \ __PMC_EV_ALIAS("QMC_ISOC_FULL.WRITE.CH1", UCP_EVENT_28H_10H) \ __PMC_EV_ALIAS("QMC_ISOC_FULL.WRITE.CH2", UCP_EVENT_28H_20H) \ __PMC_EV_ALIAS("QMC_BUSY.READ.CH0", UCP_EVENT_29H_01H) \ __PMC_EV_ALIAS("QMC_BUSY.READ.CH1", UCP_EVENT_29H_02H) \ __PMC_EV_ALIAS("QMC_BUSY.READ.CH2", UCP_EVENT_29H_04H) \ __PMC_EV_ALIAS("QMC_BUSY.WRITE.CH0", UCP_EVENT_29H_08H) \ __PMC_EV_ALIAS("QMC_BUSY.WRITE.CH1", UCP_EVENT_29H_10H) \ __PMC_EV_ALIAS("QMC_BUSY.WRITE.CH2", UCP_EVENT_29H_20H) \ __PMC_EV_ALIAS("QMC_OCCUPANCY.CH0", UCP_EVENT_2AH_01H) \ __PMC_EV_ALIAS("QMC_OCCUPANCY.CH1", UCP_EVENT_2AH_02H) \ __PMC_EV_ALIAS("QMC_OCCUPANCY.CH2", UCP_EVENT_2AH_04H) \ __PMC_EV_ALIAS("QMC_ISSOC_OCCUPANCY.CH0", UCP_EVENT_2BH_01H) \ __PMC_EV_ALIAS("QMC_ISSOC_OCCUPANCY.CH1", UCP_EVENT_2BH_02H) \ __PMC_EV_ALIAS("QMC_ISSOC_OCCUPANCY.CH2", UCP_EVENT_2BH_04H) \ __PMC_EV_ALIAS("QMC_ISSOC_READS.ANY", UCP_EVENT_2BH_07H) \ __PMC_EV_ALIAS("QMC_NORMAL_READS.CH0", UCP_EVENT_2CH_01H) \ __PMC_EV_ALIAS("QMC_NORMAL_READS.CH1", UCP_EVENT_2CH_02H) \ __PMC_EV_ALIAS("QMC_NORMAL_READS.CH2", UCP_EVENT_2CH_04H) \ __PMC_EV_ALIAS("QMC_NORMAL_READS.ANY", UCP_EVENT_2CH_07H) \ __PMC_EV_ALIAS("QMC_HIGH_PRIORITY_READS.CH0", UCP_EVENT_2DH_01H) \ __PMC_EV_ALIAS("QMC_HIGH_PRIORITY_READS.CH1", UCP_EVENT_2DH_02H) \ __PMC_EV_ALIAS("QMC_HIGH_PRIORITY_READS.CH2", UCP_EVENT_2DH_04H) \ __PMC_EV_ALIAS("QMC_HIGH_PRIORITY_READS.ANY", UCP_EVENT_2DH_07H) \ __PMC_EV_ALIAS("QMC_CRITICAL_PRIORITY_READS.CH0", UCP_EVENT_2EH_01H) \ __PMC_EV_ALIAS("QMC_CRITICAL_PRIORITY_READS.CH1", UCP_EVENT_2EH_02H) \ __PMC_EV_ALIAS("QMC_CRITICAL_PRIORITY_READS.CH2", UCP_EVENT_2EH_04H) \ __PMC_EV_ALIAS("QMC_CRITICAL_PRIORITY_READS.ANY", UCP_EVENT_2EH_07H) \ __PMC_EV_ALIAS("QMC_WRITES.FULL.CH0", UCP_EVENT_2FH_01H) \ __PMC_EV_ALIAS("QMC_WRITES.FULL.CH1", UCP_EVENT_2FH_02H) \ __PMC_EV_ALIAS("QMC_WRITES.FULL.CH2", UCP_EVENT_2FH_04H) \ __PMC_EV_ALIAS("QMC_WRITES.FULL.ANY", UCP_EVENT_2FH_07H) \ __PMC_EV_ALIAS("QMC_WRITES.PARTIAL.CH0", UCP_EVENT_2FH_08H) \ __PMC_EV_ALIAS("QMC_WRITES.PARTIAL.CH1", UCP_EVENT_2FH_10H) \ __PMC_EV_ALIAS("QMC_WRITES.PARTIAL.CH2", UCP_EVENT_2FH_20H) \ __PMC_EV_ALIAS("QMC_WRITES.PARTIAL.ANY", UCP_EVENT_2FH_38H) \ __PMC_EV_ALIAS("QMC_CANCEL.CH0", UCP_EVENT_30H_01H) \ __PMC_EV_ALIAS("QMC_CANCEL.CH1", UCP_EVENT_30H_02H) \ __PMC_EV_ALIAS("QMC_CANCEL.CH2", UCP_EVENT_30H_04H) \ __PMC_EV_ALIAS("QMC_CANCEL.ANY", UCP_EVENT_30H_07H) \ __PMC_EV_ALIAS("QMC_PRIORITY_UPDATES.CH0", UCP_EVENT_31H_01H) \ __PMC_EV_ALIAS("QMC_PRIORITY_UPDATES.CH1", UCP_EVENT_31H_02H) \ __PMC_EV_ALIAS("QMC_PRIORITY_UPDATES.CH2", UCP_EVENT_31H_04H) \ __PMC_EV_ALIAS("QMC_PRIORITY_UPDATES.ANY", UCP_EVENT_31H_07H) \ __PMC_EV_ALIAS("QHL_FRC_ACK_CNFLTS.LOCAL", UCP_EVENT_33H_04H) \ __PMC_EV_ALIAS("QPI_TX_STALLED_SINGLE_FLIT.HOME.LINK_0", \ UCP_EVENT_40H_01H) \ __PMC_EV_ALIAS("QPI_TX_STALLED_SINGLE_FLIT.SNOOP.LINK_0", \ UCP_EVENT_40H_02H) \ __PMC_EV_ALIAS("QPI_TX_STALLED_SINGLE_FLIT.NDR.LINK_0", \ UCP_EVENT_40H_04H) \ __PMC_EV_ALIAS("QPI_TX_STALLED_SINGLE_FLIT.HOME.LINK_1", \ UCP_EVENT_40H_08H) \ __PMC_EV_ALIAS("QPI_TX_STALLED_SINGLE_FLIT.SNOOP.LINK_1", \ UCP_EVENT_40H_10H) \ __PMC_EV_ALIAS("QPI_TX_STALLED_SINGLE_FLIT.NDR.LINK_1", \ UCP_EVENT_40H_20H) \ __PMC_EV_ALIAS("QPI_TX_STALLED_SINGLE_FLIT.LINK_0", UCP_EVENT_40H_07H) \ __PMC_EV_ALIAS("QPI_TX_STALLED_SINGLE_FLIT.LINK_1", UCP_EVENT_40H_38H) \ __PMC_EV_ALIAS("QPI_TX_STALLED_MULTI_FLIT.DRS.LINK_0", \ UCP_EVENT_41H_01H) \ __PMC_EV_ALIAS("QPI_TX_STALLED_MULTI_FLIT.NCB.LINK_0", \ UCP_EVENT_41H_02H) \ __PMC_EV_ALIAS("QPI_TX_STALLED_MULTI_FLIT.NCS.LINK_0", \ UCP_EVENT_41H_04H) \ __PMC_EV_ALIAS("QPI_TX_STALLED_MULTI_FLIT.DRS.LINK_1", \ UCP_EVENT_41H_08H) \ __PMC_EV_ALIAS("QPI_TX_STALLED_MULTI_FLIT.NCB.LINK_1", \ UCP_EVENT_41H_10H) \ __PMC_EV_ALIAS("QPI_TX_STALLED_MULTI_FLIT.NCS.LINK_1", \ UCP_EVENT_41H_20H) \ __PMC_EV_ALIAS("QPI_TX_STALLED_MULTI_FLIT.LINK_0", UCP_EVENT_41H_07H) \ __PMC_EV_ALIAS("QPI_TX_STALLED_MULTI_FLIT.LINK_1", UCP_EVENT_41H_38H) \ __PMC_EV_ALIAS("QPI_TX_HEADER.BUSY.LINK_0", UCP_EVENT_42H_02H) \ __PMC_EV_ALIAS("QPI_TX_HEADER.BUSY.LINK_1", UCP_EVENT_42H_08H) \ __PMC_EV_ALIAS("QPI_RX_NO_PPT_CREDIT.STALLS.LINK_0", UCP_EVENT_43H_01H) \ __PMC_EV_ALIAS("QPI_RX_NO_PPT_CREDIT.STALLS.LINK_1", UCP_EVENT_43H_02H) \ __PMC_EV_ALIAS("DRAM_OPEN.CH0", UCP_EVENT_60H_01H) \ __PMC_EV_ALIAS("DRAM_OPEN.CH1", UCP_EVENT_60H_02H) \ __PMC_EV_ALIAS("DRAM_OPEN.CH2", UCP_EVENT_60H_04H) \ __PMC_EV_ALIAS("DRAM_PAGE_CLOSE.CH0", UCP_EVENT_61H_01H) \ __PMC_EV_ALIAS("DRAM_PAGE_CLOSE.CH1", UCP_EVENT_61H_02H) \ __PMC_EV_ALIAS("DRAM_PAGE_CLOSE.CH2", UCP_EVENT_61H_04H) \ __PMC_EV_ALIAS("DRAM_PAGE_MISS.CH0", UCP_EVENT_62H_01H) \ __PMC_EV_ALIAS("DRAM_PAGE_MISS.CH1", UCP_EVENT_62H_02H) \ __PMC_EV_ALIAS("DRAM_PAGE_MISS.CH2", UCP_EVENT_62H_04H) \ __PMC_EV_ALIAS("DRAM_READ_CAS.CH0", UCP_EVENT_63H_01H) \ __PMC_EV_ALIAS("DRAM_READ_CAS.AUTOPRE_CH0", UCP_EVENT_63H_02H) \ __PMC_EV_ALIAS("DRAM_READ_CAS.CH1", UCP_EVENT_63H_04H) \ __PMC_EV_ALIAS("DRAM_READ_CAS.AUTOPRE_CH1", UCP_EVENT_63H_08H) \ __PMC_EV_ALIAS("DRAM_READ_CAS.CH2", UCP_EVENT_63H_10H) \ __PMC_EV_ALIAS("DRAM_READ_CAS.AUTOPRE_CH2", UCP_EVENT_63H_20H) \ __PMC_EV_ALIAS("DRAM_WRITE_CAS.CH0", UCP_EVENT_64H_01H) \ __PMC_EV_ALIAS("DRAM_WRITE_CAS.AUTOPRE_CH0", UCP_EVENT_64H_02H) \ __PMC_EV_ALIAS("DRAM_WRITE_CAS.CH1", UCP_EVENT_64H_04H) \ __PMC_EV_ALIAS("DRAM_WRITE_CAS.AUTOPRE_CH1", UCP_EVENT_64H_08H) \ __PMC_EV_ALIAS("DRAM_WRITE_CAS.CH2", UCP_EVENT_64H_10H) \ __PMC_EV_ALIAS("DRAM_WRITE_CAS.AUTOPRE_CH2", UCP_EVENT_64H_20H) \ __PMC_EV_ALIAS("DRAM_REFRESH.CH0", UCP_EVENT_65H_01H) \ __PMC_EV_ALIAS("DRAM_REFRESH.CH1", UCP_EVENT_65H_02H) \ __PMC_EV_ALIAS("DRAM_REFRESH.CH2", UCP_EVENT_65H_04H) \ __PMC_EV_ALIAS("DRAM_PRE_ALL.CH0", UCP_EVENT_66H_01H) \ __PMC_EV_ALIAS("DRAM_PRE_ALL.CH1", UCP_EVENT_66H_02H) \ __PMC_EV_ALIAS("DRAM_PRE_ALL.CH2", UCP_EVENT_66H_04H) /* * Aliases for Haswell uncore PMC events */ #define __PMC_EV_ALIAS_HASWELLUC() \ __PMC_EV_ALIAS("UNC_CBO_XSNP_RESPONSE.MISS", UCP_EVENT_22H_01H) \ __PMC_EV_ALIAS("UNC_CBO_XSNP_RESPONSE.INVAL", UCP_EVENT_22H_02H) \ __PMC_EV_ALIAS("UNC_CBO_XSNP_RESPONSE.HIT", UCP_EVENT_22H_04H) \ __PMC_EV_ALIAS("UNC_CBO_XSNP_RESPONSE.HITM", UCP_EVENT_22H_08H) \ __PMC_EV_ALIAS("UNC_CBO_XSNP_RESPONSE.INVAL_M", UCP_EVENT_22H_10H) \ __PMC_EV_ALIAS("UNC_CBO_XSNP_RESPONSE.EXTERNAL_FILTER", \ UCP_EVENT_22H_20H) \ __PMC_EV_ALIAS("UNC_CBO_XSNP_RESPONSE.XCORE_FILTER", UCP_EVENT_22H_40H) \ __PMC_EV_ALIAS("UNC_CBO_XSNP_RESPONSE.EVICTION_FILTER", \ UCP_EVENT_22H_80H) \ __PMC_EV_ALIAS("UNC_CBO_CACHE_LOOKUP.M", UCP_EVENT_34H_01H) \ __PMC_EV_ALIAS("UNC_CBO_CACHE_LOOKUP.ES", UCP_EVENT_34H_06H) \ __PMC_EV_ALIAS("UNC_CBO_CACHE_LOOKUP.I", UCP_EVENT_34H_08H) \ __PMC_EV_ALIAS("UNC_CBO_CACHE_LOOKUP.READ_FILTER", UCP_EVENT_34H_10H) \ __PMC_EV_ALIAS("UNC_CBO_CACHE_LOOKUP.WRITE_FILTER", UCP_EVENT_34H_20H) \ __PMC_EV_ALIAS("UNC_CBO_CACHE_LOOKUP.EXTSNP_FILTER", UCP_EVENT_34H_40H) \ __PMC_EV_ALIAS("UNC_CBO_CACHE_LOOKUP.ANY_REQUEST_FILTER", \ UCP_EVENT_34H_80H) \ __PMC_EV_ALIAS("UNC_ARB_TRK_OCCUPANCY.ALL", UCP_EVENT_80H_01H) \ __PMC_EV_ALIAS("UNC_ARB_TRK_REQUEST.ALL", UCP_EVENT_81H_01H) \ __PMC_EV_ALIAS("UNC_ARB_TRK_REQUEST.WRITES", UCP_EVENT_81H_20H) \ __PMC_EV_ALIAS("UNC_ARB_TRK_REQUEST.EVICTIONS", UCP_EVENT_81H_80H) \ __PMC_EV_ALIAS("UNC_ARB_COH_TRK_OCCUPANCY.ALL", UCP_EVENT_83H_01H) \ __PMC_EV_ALIAS("UNC_ARB_COH_TRK_REQUEST.ALL", UCP_EVENT_84H_01H) #define __PMC_EV_ALIAS_WESTMEREUC() \ __PMC_EV_ALIAS("GQ_CYCLES_FULL.READ_TRACKER", UCP_EVENT_00H_01H) \ __PMC_EV_ALIAS("GQ_CYCLES_FULL.WRITE_TRACKER", UCP_EVENT_00H_02H) \ __PMC_EV_ALIAS("GQ_CYCLES_FULL.PEER_PROBE_TRACKER", UCP_EVENT_00H_04H) \ __PMC_EV_ALIAS("GQ_CYCLES_NOT_EMPTY.READ_TRACKER", UCP_EVENT_01H_01H) \ __PMC_EV_ALIAS("GQ_CYCLES_NOT_EMPTY.WRITE_TRACKER", UCP_EVENT_01H_02H) \ __PMC_EV_ALIAS("GQ_CYCLES_NOT_EMPTY.PEER_PROBE_TRACKER", \ UCP_EVENT_01H_04H) \ __PMC_EV_ALIAS("GQ_OCCUPANCY.READ_TRACKER", UCP_EVENT_02H_01H) \ __PMC_EV_ALIAS("GQ_ALLOC.READ_TRACKER", UCP_EVENT_03H_01H) \ __PMC_EV_ALIAS("GQ_ALLOC.RT_L3_MISS", UCP_EVENT_03H_02H) \ __PMC_EV_ALIAS("GQ_ALLOC.RT_TO_L3_RESP", UCP_EVENT_03H_04H) \ __PMC_EV_ALIAS("GQ_ALLOC.RT_TO_RTID_ACQUIRED", UCP_EVENT_03H_08H) \ __PMC_EV_ALIAS("GQ_ALLOC.WT_TO_RTID_ACQUIRED", UCP_EVENT_03H_10H) \ __PMC_EV_ALIAS("GQ_ALLOC.WRITE_TRACKER", UCP_EVENT_03H_20H) \ __PMC_EV_ALIAS("GQ_ALLOC.PEER_PROBE_TRACKER", UCP_EVENT_03H_40H) \ __PMC_EV_ALIAS("GQ_DATA.FROM_QPI", UCP_EVENT_04H_01H) \ __PMC_EV_ALIAS("GQ_DATA.FROM_QMC", UCP_EVENT_04H_02H) \ __PMC_EV_ALIAS("GQ_DATA.FROM_L3", UCP_EVENT_04H_04H) \ __PMC_EV_ALIAS("GQ_DATA.FROM_CORES_02", UCP_EVENT_04H_08H) \ __PMC_EV_ALIAS("GQ_DATA.FROM_CORES_13", UCP_EVENT_04H_10H) \ __PMC_EV_ALIAS("GQ_DATA.TO_QPI_QMC", UCP_EVENT_05H_01H) \ __PMC_EV_ALIAS("GQ_DATA.TO_L3", UCP_EVENT_05H_02H) \ __PMC_EV_ALIAS("GQ_DATA.TO_CORES", UCP_EVENT_05H_04H) \ __PMC_EV_ALIAS("SNP_RESP_TO_LOCAL_HOME.I_STATE", UCP_EVENT_06H_01H) \ __PMC_EV_ALIAS("SNP_RESP_TO_LOCAL_HOME.S_STATE", UCP_EVENT_06H_02H) \ __PMC_EV_ALIAS("SNP_RESP_TO_LOCAL_HOME.FWD_S_STATE", UCP_EVENT_06H_04H) \ __PMC_EV_ALIAS("SNP_RESP_TO_LOCAL_HOME.FWD_I_STATE", UCP_EVENT_06H_08H) \ __PMC_EV_ALIAS("SNP_RESP_TO_LOCAL_HOME.CONFLICT", UCP_EVENT_06H_10H) \ __PMC_EV_ALIAS("SNP_RESP_TO_LOCAL_HOME.WB", UCP_EVENT_06H_20H) \ __PMC_EV_ALIAS("SNP_RESP_TO_REMOTE_HOME.I_STATE", UCP_EVENT_07H_01H) \ __PMC_EV_ALIAS("SNP_RESP_TO_REMOTE_HOME.S_STATE", UCP_EVENT_07H_02H) \ __PMC_EV_ALIAS("SNP_RESP_TO_REMOTE_HOME.FWD_S_STATE", UCP_EVENT_07H_04H)\ __PMC_EV_ALIAS("SNP_RESP_TO_REMOTE_HOME.FWD_I_STATE", UCP_EVENT_07H_08H)\ __PMC_EV_ALIAS("SNP_RESP_TO_REMOTE_HOME.CONFLICT", UCP_EVENT_07H_10H) \ __PMC_EV_ALIAS("SNP_RESP_TO_REMOTE_HOME.WB", UCP_EVENT_07H_20H) \ __PMC_EV_ALIAS("SNP_RESP_TO_REMOTE_HOME.HITM", UCP_EVENT_07H_24H) \ __PMC_EV_ALIAS("L3_HITS.READ", UCP_EVENT_08H_01H) \ __PMC_EV_ALIAS("L3_HITS.WRITE", UCP_EVENT_08H_02H) \ __PMC_EV_ALIAS("L3_HITS.PROBE", UCP_EVENT_08H_04H) \ __PMC_EV_ALIAS("L3_HITS.ANY", UCP_EVENT_08H_03H) \ __PMC_EV_ALIAS("L3_MISS.READ", UCP_EVENT_09H_01H) \ __PMC_EV_ALIAS("L3_MISS.WRITE", UCP_EVENT_09H_02H) \ __PMC_EV_ALIAS("L3_MISS.PROBE", UCP_EVENT_09H_04H) \ __PMC_EV_ALIAS("L3_MISS.ANY", UCP_EVENT_09H_03H) \ __PMC_EV_ALIAS("L3_LINES_IN.M_STATE", UCP_EVENT_0AH_01H) \ __PMC_EV_ALIAS("L3_LINES_IN.E_STATE", UCP_EVENT_0AH_02H) \ __PMC_EV_ALIAS("L3_LINES_IN.S_STATE", UCP_EVENT_0AH_04H) \ __PMC_EV_ALIAS("L3_LINES_IN.F_STATE", UCP_EVENT_0AH_08H) \ __PMC_EV_ALIAS("L3_LINES_IN.ANY", UCP_EVENT_0AH_0FH) \ __PMC_EV_ALIAS("L3_LINES_OUT.M_STATE", UCP_EVENT_0BH_01H) \ __PMC_EV_ALIAS("L3_LINES_OUT.E_STATE", UCP_EVENT_0BH_02H) \ __PMC_EV_ALIAS("L3_LINES_OUT.S_STATE", UCP_EVENT_0BH_04H) \ __PMC_EV_ALIAS("L3_LINES_OUT.I_STATE", UCP_EVENT_0BH_08H) \ __PMC_EV_ALIAS("L3_LINES_OUT.F_STATE", UCP_EVENT_0BH_10H) \ __PMC_EV_ALIAS("L3_LINES_OUT.ANY", UCP_EVENT_0BH_1FH) \ __PMC_EV_ALIAS("GQ_SNOOP.GOTO_S", UCP_EVENT_0CH_01H) \ __PMC_EV_ALIAS("GQ_SNOOP.GOTO_I", UCP_EVENT_0CH_02H) \ __PMC_EV_ALIAS("GQ_SNOOP.GOTO_S_HIT_E", UCP_EVENT_0CH_04H_E) \ __PMC_EV_ALIAS("GQ_SNOOP.GOTO_S_HIT_F", UCP_EVENT_0CH_04H_F) \ __PMC_EV_ALIAS("GQ_SNOOP.GOTO_S_HIT_M", UCP_EVENT_0CH_04H_M) \ __PMC_EV_ALIAS("GQ_SNOOP.GOTO_S_HIT_S", UCP_EVENT_0CH_04H_S) \ __PMC_EV_ALIAS("GQ_SNOOP.GOTO_I_HIT_E", UCP_EVENT_0CH_08H_E) \ __PMC_EV_ALIAS("GQ_SNOOP.GOTO_I_HIT_F", UCP_EVENT_0CH_08H_F) \ __PMC_EV_ALIAS("GQ_SNOOP.GOTO_I_HIT_M", UCP_EVENT_0CH_08H_M) \ __PMC_EV_ALIAS("GQ_SNOOP.GOTO_I_HIT_S", UCP_EVENT_0CH_08H_S) \ __PMC_EV_ALIAS("QHL_REQUESTS.IOH_READS", UCP_EVENT_20H_01H) \ __PMC_EV_ALIAS("QHL_REQUESTS.IOH_WRITES", UCP_EVENT_20H_02H) \ __PMC_EV_ALIAS("QHL_REQUESTS.REMOTE_READS", UCP_EVENT_20H_04H) \ __PMC_EV_ALIAS("QHL_REQUESTS.REMOTE_WRITES", UCP_EVENT_20H_08H) \ __PMC_EV_ALIAS("QHL_REQUESTS.LOCAL_READS", UCP_EVENT_20H_10H) \ __PMC_EV_ALIAS("QHL_REQUESTS.LOCAL_WRITES", UCP_EVENT_20H_20H) \ __PMC_EV_ALIAS("QHL_CYCLES_FULL.IOH", UCP_EVENT_21H_01H) \ __PMC_EV_ALIAS("QHL_CYCLES_FULL.REMOTE", UCP_EVENT_21H_02H) \ __PMC_EV_ALIAS("QHL_CYCLES_FULL.LOCAL", UCP_EVENT_21H_04H) \ __PMC_EV_ALIAS("QHL_CYCLES_NOT_EMPTY.IOH", UCP_EVENT_22H_01H) \ __PMC_EV_ALIAS("QHL_CYCLES_NOT_EMPTY.REMOTE", UCP_EVENT_22H_02H) \ __PMC_EV_ALIAS("QHL_CYCLES_NOT_EMPTY.LOCAL", UCP_EVENT_22H_04H) \ __PMC_EV_ALIAS("QHL_OCCUPANCY.IOH", UCP_EVENT_23H_01H) \ __PMC_EV_ALIAS("QHL_OCCUPANCY.REMOTE", UCP_EVENT_23H_02H) \ __PMC_EV_ALIAS("QHL_OCCUPANCY.LOCAL", UCP_EVENT_23H_04H) \ __PMC_EV_ALIAS("QHL_ADDRESS_CONFLICTS.2WAY", UCP_EVENT_24H_02H) \ __PMC_EV_ALIAS("QHL_ADDRESS_CONFLICTS.3WAY", UCP_EVENT_24H_04H) \ __PMC_EV_ALIAS("QHL_CONFLICT_CYCLES.IOH", UCP_EVENT_25H_01H) \ __PMC_EV_ALIAS("QHL_CONFLICT_CYCLES.REMOTE", UCP_EVENT_25H_02H) \ __PMC_EV_ALIAS("QHL_CONFLICT_CYCLES.LOCAL", UCP_EVENT_25H_04H) \ __PMC_EV_ALIAS("QHL_TO_QMC_BYPASS", UCP_EVENT_26H_01H) \ __PMC_EV_ALIAS("QMC_ISOC_FULL.READ.CH0", UCP_EVENT_28H_01H) \ __PMC_EV_ALIAS("QMC_ISOC_FULL.READ.CH1", UCP_EVENT_28H_02H) \ __PMC_EV_ALIAS("QMC_ISOC_FULL.READ.CH2", UCP_EVENT_28H_04H) \ __PMC_EV_ALIAS("QMC_ISOC_FULL.WRITE.CH0", UCP_EVENT_28H_08H) \ __PMC_EV_ALIAS("QMC_ISOC_FULL.WRITE.CH1", UCP_EVENT_28H_10H) \ __PMC_EV_ALIAS("QMC_ISOC_FULL.WRITE.CH2", UCP_EVENT_28H_20H) \ __PMC_EV_ALIAS("QMC_BUSY.READ.CH0", UCP_EVENT_29H_01H) \ __PMC_EV_ALIAS("QMC_BUSY.READ.CH1", UCP_EVENT_29H_02H) \ __PMC_EV_ALIAS("QMC_BUSY.READ.CH2", UCP_EVENT_29H_04H) \ __PMC_EV_ALIAS("QMC_BUSY.WRITE.CH0", UCP_EVENT_29H_08H) \ __PMC_EV_ALIAS("QMC_BUSY.WRITE.CH1", UCP_EVENT_29H_10H) \ __PMC_EV_ALIAS("QMC_BUSY.WRITE.CH2", UCP_EVENT_29H_20H) \ __PMC_EV_ALIAS("QMC_OCCUPANCY.CH0", UCP_EVENT_2AH_01H) \ __PMC_EV_ALIAS("QMC_OCCUPANCY.CH1", UCP_EVENT_2AH_02H) \ __PMC_EV_ALIAS("QMC_OCCUPANCY.CH2", UCP_EVENT_2AH_04H) \ __PMC_EV_ALIAS("QMC_OCCUPANCY.ANY", UCP_EVENT_2AH_07H) \ __PMC_EV_ALIAS("QMC_ISSOC_OCCUPANCY.CH0", UCP_EVENT_2BH_01H) \ __PMC_EV_ALIAS("QMC_ISSOC_OCCUPANCY.CH1", UCP_EVENT_2BH_02H) \ __PMC_EV_ALIAS("QMC_ISSOC_OCCUPANCY.CH2", UCP_EVENT_2BH_04H) \ __PMC_EV_ALIAS("QMC_ISSOC_READS.ANY", UCP_EVENT_2BH_07H) \ __PMC_EV_ALIAS("QMC_NORMAL_READS.CH0", UCP_EVENT_2CH_01H) \ __PMC_EV_ALIAS("QMC_NORMAL_READS.CH1", UCP_EVENT_2CH_02H) \ __PMC_EV_ALIAS("QMC_NORMAL_READS.CH2", UCP_EVENT_2CH_04H) \ __PMC_EV_ALIAS("QMC_NORMAL_READS.ANY", UCP_EVENT_2CH_07H) \ __PMC_EV_ALIAS("QMC_HIGH_PRIORITY_READS.CH0", UCP_EVENT_2DH_01H) \ __PMC_EV_ALIAS("QMC_HIGH_PRIORITY_READS.CH1", UCP_EVENT_2DH_02H) \ __PMC_EV_ALIAS("QMC_HIGH_PRIORITY_READS.CH2", UCP_EVENT_2DH_04H) \ __PMC_EV_ALIAS("QMC_HIGH_PRIORITY_READS.ANY", UCP_EVENT_2DH_07H) \ __PMC_EV_ALIAS("QMC_CRITICAL_PRIORITY_READS.CH0", UCP_EVENT_2EH_01H) \ __PMC_EV_ALIAS("QMC_CRITICAL_PRIORITY_READS.CH1", UCP_EVENT_2EH_02H) \ __PMC_EV_ALIAS("QMC_CRITICAL_PRIORITY_READS.CH2", UCP_EVENT_2EH_04H) \ __PMC_EV_ALIAS("QMC_CRITICAL_PRIORITY_READS.ANY", UCP_EVENT_2EH_07H) \ __PMC_EV_ALIAS("QMC_WRITES.FULL.CH0", UCP_EVENT_2FH_01H) \ __PMC_EV_ALIAS("QMC_WRITES.FULL.CH1", UCP_EVENT_2FH_02H) \ __PMC_EV_ALIAS("QMC_WRITES.FULL.CH2", UCP_EVENT_2FH_04H) \ __PMC_EV_ALIAS("QMC_WRITES.FULL.ANY", UCP_EVENT_2FH_07H) \ __PMC_EV_ALIAS("QMC_WRITES.PARTIAL.CH0", UCP_EVENT_2FH_08H) \ __PMC_EV_ALIAS("QMC_WRITES.PARTIAL.CH1", UCP_EVENT_2FH_10H) \ __PMC_EV_ALIAS("QMC_WRITES.PARTIAL.CH2", UCP_EVENT_2FH_20H) \ __PMC_EV_ALIAS("QMC_WRITES.PARTIAL.ANY", UCP_EVENT_2FH_38H) \ __PMC_EV_ALIAS("QMC_CANCEL.CH0", UCP_EVENT_30H_01H) \ __PMC_EV_ALIAS("QMC_CANCEL.CH1", UCP_EVENT_30H_02H) \ __PMC_EV_ALIAS("QMC_CANCEL.CH2", UCP_EVENT_30H_04H) \ __PMC_EV_ALIAS("QMC_CANCEL.ANY", UCP_EVENT_30H_07H) \ __PMC_EV_ALIAS("QMC_PRIORITY_UPDATES.CH0", UCP_EVENT_31H_01H) \ __PMC_EV_ALIAS("QMC_PRIORITY_UPDATES.CH1", UCP_EVENT_31H_02H) \ __PMC_EV_ALIAS("QMC_PRIORITY_UPDATES.CH2", UCP_EVENT_31H_04H) \ __PMC_EV_ALIAS("QMC_PRIORITY_UPDATES.ANY", UCP_EVENT_31H_07H) \ __PMC_EV_ALIAS("IMC_RETRY.CH0", UCP_EVENT_32H_01H) \ __PMC_EV_ALIAS("IMC_RETRY.CH1", UCP_EVENT_32H_02H) \ __PMC_EV_ALIAS("IMC_RETRY.CH2", UCP_EVENT_32H_04H) \ __PMC_EV_ALIAS("IMC_RETRY.ANY", UCP_EVENT_32H_07H) \ __PMC_EV_ALIAS("QHL_FRC_ACK_CNFLTS.IOH", UCP_EVENT_33H_01H) \ __PMC_EV_ALIAS("QHL_FRC_ACK_CNFLTS.REMOTE", UCP_EVENT_33H_02H) \ __PMC_EV_ALIAS("QHL_FRC_ACK_CNFLTS.LOCAL", UCP_EVENT_33H_04H) \ __PMC_EV_ALIAS("QHL_FRC_ACK_CNFLTS.ANY", UCP_EVENT_33H_07H) \ __PMC_EV_ALIAS("QHL_SLEEPS.IOH_ORDER", UCP_EVENT_34H_01H) \ __PMC_EV_ALIAS("QHL_SLEEPS.REMOTE_ORDER", UCP_EVENT_34H_02H) \ __PMC_EV_ALIAS("QHL_SLEEPS.LOCAL_ORDER", UCP_EVENT_34H_04H) \ __PMC_EV_ALIAS("QHL_SLEEPS.IOH_CONFLICT", UCP_EVENT_34H_08H) \ __PMC_EV_ALIAS("QHL_SLEEPS.REMOTE_CONFLICT", UCP_EVENT_34H_10H) \ __PMC_EV_ALIAS("QHL_SLEEPS.LOCAL_CONFLICT", UCP_EVENT_34H_20H) \ __PMC_EV_ALIAS("ADDR_OPCODE_MATCH.IOH", UCP_EVENT_35H_01H) \ __PMC_EV_ALIAS("ADDR_OPCODE_MATCH.REMOTE", UCP_EVENT_35H_02H) \ __PMC_EV_ALIAS("ADDR_OPCODE_MATCH.LOCAL", UCP_EVENT_35H_04H) \ __PMC_EV_ALIAS("QPI_TX_STALLED_SINGLE_FLIT.HOME.LINK_0", \ UCP_EVENT_40H_01H) \ __PMC_EV_ALIAS("QPI_TX_STALLED_SINGLE_FLIT.SNOOP.LINK_0", \ UCP_EVENT_40H_02H) \ __PMC_EV_ALIAS("QPI_TX_STALLED_SINGLE_FLIT.NDR.LINK_0", \ UCP_EVENT_40H_04H) \ __PMC_EV_ALIAS("QPI_TX_STALLED_SINGLE_FLIT.HOME.LINK_1", \ UCP_EVENT_40H_08H) \ __PMC_EV_ALIAS("QPI_TX_STALLED_SINGLE_FLIT.SNOOP.LINK_1", \ UCP_EVENT_40H_10H) \ __PMC_EV_ALIAS("QPI_TX_STALLED_SINGLE_FLIT.NDR.LINK_1", \ UCP_EVENT_40H_20H) \ __PMC_EV_ALIAS("QPI_TX_STALLED_SINGLE_FLIT.LINK_0", UCP_EVENT_40H_07H) \ __PMC_EV_ALIAS("QPI_TX_STALLED_SINGLE_FLIT.LINK_1", UCP_EVENT_40H_38H) \ __PMC_EV_ALIAS("QPI_TX_STALLED_MULTI_FLIT.DRS.LINK_0", \ UCP_EVENT_41H_01H) \ __PMC_EV_ALIAS("QPI_TX_STALLED_MULTI_FLIT.NCB.LINK_0", \ UCP_EVENT_41H_02H) \ __PMC_EV_ALIAS("QPI_TX_STALLED_MULTI_FLIT.NCS.LINK_0", \ UCP_EVENT_41H_04H) \ __PMC_EV_ALIAS("QPI_TX_STALLED_MULTI_FLIT.DRS.LINK_1", \ UCP_EVENT_41H_08H) \ __PMC_EV_ALIAS("QPI_TX_STALLED_MULTI_FLIT.NCB.LINK_1", \ UCP_EVENT_41H_10H) \ __PMC_EV_ALIAS("QPI_TX_STALLED_MULTI_FLIT.NCS.LINK_1", \ UCP_EVENT_41H_20H) \ __PMC_EV_ALIAS("QPI_TX_STALLED_MULTI_FLIT.LINK_0", UCP_EVENT_41H_07H) \ __PMC_EV_ALIAS("QPI_TX_STALLED_MULTI_FLIT.LINK_1", UCP_EVENT_41H_38H) \ __PMC_EV_ALIAS("QPI_TX_HEADER.FULL.LINK_0", UCP_EVENT_42H_01H) \ __PMC_EV_ALIAS("QPI_TX_HEADER.BUSY.LINK_0", UCP_EVENT_42H_02H) \ __PMC_EV_ALIAS("QPI_TX_HEADER.FULL.LINK_1", UCP_EVENT_42H_04H) \ __PMC_EV_ALIAS("QPI_TX_HEADER.BUSY.LINK_1", UCP_EVENT_42H_08H) \ __PMC_EV_ALIAS("QPI_RX_NO_PPT_CREDIT.STALLS.LINK_0", UCP_EVENT_43H_01H) \ __PMC_EV_ALIAS("QPI_RX_NO_PPT_CREDIT.STALLS.LINK_1", UCP_EVENT_43H_02H) \ __PMC_EV_ALIAS("DRAM_OPEN.CH0", UCP_EVENT_60H_01H) \ __PMC_EV_ALIAS("DRAM_OPEN.CH1", UCP_EVENT_60H_02H) \ __PMC_EV_ALIAS("DRAM_OPEN.CH2", UCP_EVENT_60H_04H) \ __PMC_EV_ALIAS("DRAM_PAGE_CLOSE.CH0", UCP_EVENT_61H_01H) \ __PMC_EV_ALIAS("DRAM_PAGE_CLOSE.CH1", UCP_EVENT_61H_02H) \ __PMC_EV_ALIAS("DRAM_PAGE_CLOSE.CH2", UCP_EVENT_61H_04H) \ __PMC_EV_ALIAS("DRAM_PAGE_MISS.CH0", UCP_EVENT_62H_01H) \ __PMC_EV_ALIAS("DRAM_PAGE_MISS.CH1", UCP_EVENT_62H_02H) \ __PMC_EV_ALIAS("DRAM_PAGE_MISS.CH2", UCP_EVENT_62H_04H) \ __PMC_EV_ALIAS("DRAM_READ_CAS.CH0", UCP_EVENT_63H_01H) \ __PMC_EV_ALIAS("DRAM_READ_CAS.AUTOPRE_CH0", UCP_EVENT_63H_02H) \ __PMC_EV_ALIAS("DRAM_READ_CAS.CH1", UCP_EVENT_63H_04H) \ __PMC_EV_ALIAS("DRAM_READ_CAS.AUTOPRE_CH1", UCP_EVENT_63H_08H) \ __PMC_EV_ALIAS("DRAM_READ_CAS.CH2", UCP_EVENT_63H_10H) \ __PMC_EV_ALIAS("DRAM_READ_CAS.AUTOPRE_CH2", UCP_EVENT_63H_20H) \ __PMC_EV_ALIAS("DRAM_WRITE_CAS.CH0", UCP_EVENT_64H_01H) \ __PMC_EV_ALIAS("DRAM_WRITE_CAS.AUTOPRE_CH0", UCP_EVENT_64H_02H) \ __PMC_EV_ALIAS("DRAM_WRITE_CAS.CH1", UCP_EVENT_64H_04H) \ __PMC_EV_ALIAS("DRAM_WRITE_CAS.AUTOPRE_CH1", UCP_EVENT_64H_08H) \ __PMC_EV_ALIAS("DRAM_WRITE_CAS.CH2", UCP_EVENT_64H_10H) \ __PMC_EV_ALIAS("DRAM_WRITE_CAS.AUTOPRE_CH2", UCP_EVENT_64H_20H) \ __PMC_EV_ALIAS("DRAM_REFRESH.CH0", UCP_EVENT_65H_01H) \ __PMC_EV_ALIAS("DRAM_REFRESH.CH1", UCP_EVENT_65H_02H) \ __PMC_EV_ALIAS("DRAM_REFRESH.CH2", UCP_EVENT_65H_04H) \ __PMC_EV_ALIAS("DRAM_PRE_ALL.CH0", UCP_EVENT_66H_01H) \ __PMC_EV_ALIAS("DRAM_PRE_ALL.CH1", UCP_EVENT_66H_02H) \ __PMC_EV_ALIAS("DRAM_PRE_ALL.CH2", UCP_EVENT_66H_04H) \ __PMC_EV_ALIAS("DRAM_THERMAL_THROTTLED", UCP_EVENT_67H_01H) \ __PMC_EV_ALIAS("THERMAL_THROTTLING_TEMP.CORE_0", UCP_EVENT_80H_01H) \ __PMC_EV_ALIAS("THERMAL_THROTTLING_TEMP.CORE_1", UCP_EVENT_80H_02H) \ __PMC_EV_ALIAS("THERMAL_THROTTLING_TEMP.CORE_2", UCP_EVENT_80H_04H) \ __PMC_EV_ALIAS("THERMAL_THROTTLING_TEMP.CORE_3", UCP_EVENT_80H_08H) \ __PMC_EV_ALIAS("THERMAL_THROTTLED_TEMP.CORE_0", UCP_EVENT_81H_01H) \ __PMC_EV_ALIAS("THERMAL_THROTTLED_TEMP.CORE_1", UCP_EVENT_81H_02H) \ __PMC_EV_ALIAS("THERMAL_THROTTLED_TEMP.CORE_2", UCP_EVENT_81H_04H) \ __PMC_EV_ALIAS("THERMAL_THROTTLED_TEMP.CORE_3", UCP_EVENT_81H_08H) \ __PMC_EV_ALIAS("PROCHOT_ASSERTION", UCP_EVENT_82H_01H) \ __PMC_EV_ALIAS("THERMAL_THROTTLING_PROCHOT.CORE_0", UCP_EVENT_83H_01H) \ __PMC_EV_ALIAS("THERMAL_THROTTLING_PROCHOT.CORE_1", UCP_EVENT_83H_02H) \ __PMC_EV_ALIAS("THERMAL_THROTTLING_PROCHOT.CORE_2", UCP_EVENT_83H_04H) \ __PMC_EV_ALIAS("THERMAL_THROTTLING_PROCHOT.CORE_3", UCP_EVENT_83H_08H) \ __PMC_EV_ALIAS("TURBO_MODE.CORE_0", UCP_EVENT_84H_01H) \ __PMC_EV_ALIAS("TURBO_MODE.CORE_1", UCP_EVENT_84H_02H) \ __PMC_EV_ALIAS("TURBO_MODE.CORE_2", UCP_EVENT_84H_04H) \ __PMC_EV_ALIAS("TURBO_MODE.CORE_3", UCP_EVENT_84H_08H) \ __PMC_EV_ALIAS("CYCLES_UNHALTED_L3_FLL_ENABLE", UCP_EVENT_85H_02H) \ __PMC_EV_ALIAS("CYCLES_UNHALTED_L3_FLL_DISABLE", UCP_EVENT_86H_01H) #define __PMC_EV_ALIAS_SANDYBRIDGEUC() \ __PMC_EV_ALIAS("CB0_XSNP_RESPONSE.RSPIHITI", UCP_EVENT_22H_01H) \ __PMC_EV_ALIAS("CB0_XSNP_RESPONSE.RSPIHITFSE", UCP_EVENT_22H_02H) \ __PMC_EV_ALIAS("CB0_XSNP_RESPONSE.RSPSHITFSE", UCP_EVENT_22H_04H) \ __PMC_EV_ALIAS("CB0_XSNP_RESPONSE.RSPSFWDM", UCP_EVENT_22H_08H) \ __PMC_EV_ALIAS("CB0_XSNP_RESPONSE.AND_EXTERNAL", UCP_EVENT_22H_20H) \ __PMC_EV_ALIAS("CB0_XSNP_RESPONSE.AND_XCORE", UCP_EVENT_22H_40H) \ __PMC_EV_ALIAS("CB0_XSNP_RESPONSE_AND_XCORE2", UCP_EVENT_22H_80H) \ __PMC_EV_ALIAS("CB0_CACHE_LOOKUP.M", UCP_EVENT_34H_01H) \ __PMC_EV_ALIAS("CB0_CACHE_LOOKUP.E", UCP_EVENT_34H_02H) \ __PMC_EV_ALIAS("CB0_CACHE_LOOKUP.S", UCP_EVENT_34H_04H) \ __PMC_EV_ALIAS("CB0_CACHE_LOOKUP.I", UCP_EVENT_34H_08H) \ __PMC_EV_ALIAS("CB0_CACHE_LOOKUP.AND_READ", UCP_EVENT_34H_10H) \ __PMC_EV_ALIAS("CB0_CACHE_LOOKUP_AND_READ2", UCP_EVENT_34H_20H) \ __PMC_EV_ALIAS("CB0_CACHE_LOOKUP.AND_EXTSNP", UCP_EVENT_34H_40H) \ __PMC_EV_ALIAS("CB0_CACHE_LOOKUP.AND_ANY", UCP_EVENT_34H_80H) \ __PMC_EV_ALIAS("IMPH_CB0_TRK_OCCUPANCY.ALL", UCP_EVENT_80H_01H) \ __PMC_EV_ALIAS("IMPH_CB0_TRK_REQUEST.ALL", UCP_EVENT_81H_01H) \ __PMC_EV_ALIAS("IMPH_CB0_TRK_REQUEST.WRITES", UCP_EVENT_81H_20H) \ __PMC_EV_ALIAS("IMPH_CB0_TRK_REQUEST.EVICTIONS", UCP_EVENT_81H_80H) \ __PMC_EV_ALIAS("IMPH_C0H_TRK_OCCUPANCY.ALL", UCP_EVENT_83H_01H) \ __PMC_EV_ALIAS("IMPC_C0H_TRK_REQUEST.ALL", UCP_EVENT_84H_01H) /* * Intel XScale events from: * * Intel XScale Core Developer's Manual * January, 2004, #27347302 * * 3rd Generation Intel XScale Microarchitecture * Developer's Manual * May 2007, #31628302 * * First 14 events are for 1st and 2nd Generation Intel XScale cores. The * remaining are available only on 3rd Generation Intel XScale cores. */ #define __PMC_EV_XSCALE() \ __PMC_EV(XSCALE, IC_FETCH) \ __PMC_EV(XSCALE, IC_MISS) \ __PMC_EV(XSCALE, DATA_DEPENDENCY_STALLED) \ __PMC_EV(XSCALE, ITLB_MISS) \ __PMC_EV(XSCALE, DTLB_MISS) \ __PMC_EV(XSCALE, BRANCH_RETIRED) \ __PMC_EV(XSCALE, BRANCH_MISPRED) \ __PMC_EV(XSCALE, INSTR_RETIRED) \ __PMC_EV(XSCALE, DC_FULL_CYCLE) \ __PMC_EV(XSCALE, DC_FULL_CONTIG) \ __PMC_EV(XSCALE, DC_ACCESS) \ __PMC_EV(XSCALE, DC_MISS) \ __PMC_EV(XSCALE, DC_WRITEBACK) \ __PMC_EV(XSCALE, PC_CHANGE) \ __PMC_EV(XSCALE, BRANCH_RETIRED_ALL) \ __PMC_EV(XSCALE, INSTR_CYCLE) \ __PMC_EV(XSCALE, CP_STALL) \ __PMC_EV(XSCALE, PC_CHANGE_ALL) \ __PMC_EV(XSCALE, PIPELINE_FLUSH) \ __PMC_EV(XSCALE, BACKEND_STALL) \ __PMC_EV(XSCALE, MULTIPLIER_USE) \ __PMC_EV(XSCALE, MULTIPLIER_STALLED) \ __PMC_EV(XSCALE, DATA_CACHE_STALLED) \ __PMC_EV(XSCALE, L2_CACHE_REQ) \ __PMC_EV(XSCALE, L2_CACHE_MISS) \ __PMC_EV(XSCALE, ADDRESS_BUS_TRANS) \ __PMC_EV(XSCALE, SELF_ADDRESS_BUS_TRANS) \ __PMC_EV(XSCALE, DATA_BUS_TRANS) #define PMC_EV_XSCALE_FIRST PMC_EV_XSCALE_IC_FETCH #define PMC_EV_XSCALE_LAST PMC_EV_XSCALE_DATA_BUS_TRANS /* * MIPS Events from "Programming the MIPS32 24K Core Family", * Document Number: MD00355 Revision 04.63 December 19, 2008 * These events are kept in the order found in Table 7.4. * For counters which are different between the left hand * column (0/2) and the right hand column (1/3) the left * hand is given first, e.g. BRANCH_COMPLETED and BRANCH_MISPRED * in the definition below. */ #define __PMC_EV_MIPS24K() \ __PMC_EV(MIPS24K, CYCLE) \ __PMC_EV(MIPS24K, INSTR_EXECUTED) \ __PMC_EV(MIPS24K, BRANCH_COMPLETED) \ __PMC_EV(MIPS24K, BRANCH_MISPRED) \ __PMC_EV(MIPS24K, RETURN) \ __PMC_EV(MIPS24K, RETURN_MISPRED) \ __PMC_EV(MIPS24K, RETURN_NOT_31) \ __PMC_EV(MIPS24K, RETURN_NOTPRED) \ __PMC_EV(MIPS24K, ITLB_ACCESS) \ __PMC_EV(MIPS24K, ITLB_MISS) \ __PMC_EV(MIPS24K, DTLB_ACCESS) \ __PMC_EV(MIPS24K, DTLB_MISS) \ __PMC_EV(MIPS24K, JTLB_IACCESS) \ __PMC_EV(MIPS24K, JTLB_IMISS) \ __PMC_EV(MIPS24K, JTLB_DACCESS) \ __PMC_EV(MIPS24K, JTLB_DMISS) \ __PMC_EV(MIPS24K, IC_FETCH) \ __PMC_EV(MIPS24K, IC_MISS) \ __PMC_EV(MIPS24K, DC_LOADSTORE) \ __PMC_EV(MIPS24K, DC_WRITEBACK) \ __PMC_EV(MIPS24K, DC_MISS) \ __PMC_EV(MIPS24K, STORE_MISS) \ __PMC_EV(MIPS24K, LOAD_MISS) \ __PMC_EV(MIPS24K, INTEGER_COMPLETED) \ __PMC_EV(MIPS24K, FP_COMPLETED) \ __PMC_EV(MIPS24K, LOAD_COMPLETED) \ __PMC_EV(MIPS24K, STORE_COMPLETED) \ __PMC_EV(MIPS24K, BARRIER_COMPLETED) \ __PMC_EV(MIPS24K, MIPS16_COMPLETED) \ __PMC_EV(MIPS24K, NOP_COMPLETED) \ __PMC_EV(MIPS24K, INTEGER_MULDIV_COMPLETED)\ __PMC_EV(MIPS24K, RF_STALL) \ __PMC_EV(MIPS24K, INSTR_REFETCH) \ __PMC_EV(MIPS24K, STORE_COND_COMPLETED) \ __PMC_EV(MIPS24K, STORE_COND_FAILED) \ __PMC_EV(MIPS24K, ICACHE_REQUESTS) \ __PMC_EV(MIPS24K, ICACHE_HIT) \ __PMC_EV(MIPS24K, L2_WRITEBACK) \ __PMC_EV(MIPS24K, L2_ACCESS) \ __PMC_EV(MIPS24K, L2_MISS) \ __PMC_EV(MIPS24K, L2_ERR_CORRECTED) \ __PMC_EV(MIPS24K, EXCEPTIONS) \ __PMC_EV(MIPS24K, RF_CYCLES_STALLED) \ __PMC_EV(MIPS24K, IFU_CYCLES_STALLED) \ __PMC_EV(MIPS24K, ALU_CYCLES_STALLED) \ __PMC_EV(MIPS24K, UNCACHED_LOAD) \ __PMC_EV(MIPS24K, UNCACHED_STORE) \ __PMC_EV(MIPS24K, CP2_REG_TO_REG_COMPLETED)\ __PMC_EV(MIPS24K, MFTC_COMPLETED) \ __PMC_EV(MIPS24K, IC_BLOCKED_CYCLES) \ __PMC_EV(MIPS24K, DC_BLOCKED_CYCLES) \ __PMC_EV(MIPS24K, L2_IMISS_STALL_CYCLES) \ __PMC_EV(MIPS24K, L2_DMISS_STALL_CYCLES) \ __PMC_EV(MIPS24K, DMISS_CYCLES) \ __PMC_EV(MIPS24K, L2_MISS_CYCLES) \ __PMC_EV(MIPS24K, UNCACHED_BLOCK_CYCLES) \ __PMC_EV(MIPS24K, MDU_STALL_CYCLES) \ __PMC_EV(MIPS24K, FPU_STALL_CYCLES) \ __PMC_EV(MIPS24K, CP2_STALL_CYCLES) \ __PMC_EV(MIPS24K, COREXTEND_STALL_CYCLES) \ __PMC_EV(MIPS24K, ISPRAM_STALL_CYCLES) \ __PMC_EV(MIPS24K, DSPRAM_STALL_CYCLES) \ __PMC_EV(MIPS24K, CACHE_STALL_CYCLES) \ __PMC_EV(MIPS24K, LOAD_TO_USE_STALLS) \ __PMC_EV(MIPS24K, BASE_MISPRED_STALLS) \ __PMC_EV(MIPS24K, CPO_READ_STALLS) \ __PMC_EV(MIPS24K, BRANCH_MISPRED_CYCLES) \ __PMC_EV(MIPS24K, IFETCH_BUFFER_FULL) \ __PMC_EV(MIPS24K, FETCH_BUFFER_ALLOCATED) \ __PMC_EV(MIPS24K, EJTAG_ITRIGGER) \ __PMC_EV(MIPS24K, EJTAG_DTRIGGER) \ __PMC_EV(MIPS24K, FSB_LT_QUARTER) \ __PMC_EV(MIPS24K, FSB_QUARTER_TO_HALF) \ __PMC_EV(MIPS24K, FSB_GT_HALF) \ __PMC_EV(MIPS24K, FSB_FULL_PIPELINE_STALLS)\ __PMC_EV(MIPS24K, LDQ_LT_QUARTER) \ __PMC_EV(MIPS24K, LDQ_QUARTER_TO_HALF) \ __PMC_EV(MIPS24K, LDQ_GT_HALF) \ __PMC_EV(MIPS24K, LDQ_FULL_PIPELINE_STALLS)\ __PMC_EV(MIPS24K, WBB_LT_QUARTER) \ __PMC_EV(MIPS24K, WBB_QUARTER_TO_HALF) \ __PMC_EV(MIPS24K, WBB_GT_HALF) \ __PMC_EV(MIPS24K, WBB_FULL_PIPELINE_STALLS) \ __PMC_EV(MIPS24K, REQUEST_LATENCY) \ __PMC_EV(MIPS24K, REQUEST_COUNT) #define PMC_EV_MIPS24K_FIRST PMC_EV_MIPS24K_CYCLE #define PMC_EV_MIPS24K_LAST PMC_EV_MIPS24K_WBB_FULL_PIPELINE_STALLS /* * Cavium Octeon counters. Obtained from cvmx-core.h */ #define __PMC_EV_OCTEON() \ __PMC_EV(OCTEON, CLK) \ __PMC_EV(OCTEON, ISSUE) \ __PMC_EV(OCTEON, RET) \ __PMC_EV(OCTEON, NISSUE) \ __PMC_EV(OCTEON, SISSUE) \ __PMC_EV(OCTEON, DISSUE) \ __PMC_EV(OCTEON, IFI) \ __PMC_EV(OCTEON, BR) \ __PMC_EV(OCTEON, BRMIS) \ __PMC_EV(OCTEON, J) \ __PMC_EV(OCTEON, JMIS) \ __PMC_EV(OCTEON, REPLAY) \ __PMC_EV(OCTEON, IUNA) \ __PMC_EV(OCTEON, TRAP) \ __PMC_EV(OCTEON, UULOAD) \ __PMC_EV(OCTEON, UUSTORE) \ __PMC_EV(OCTEON, ULOAD) \ __PMC_EV(OCTEON, USTORE) \ __PMC_EV(OCTEON, EC) \ __PMC_EV(OCTEON, MC) \ __PMC_EV(OCTEON, CC) \ __PMC_EV(OCTEON, CSRC) \ __PMC_EV(OCTEON, CFETCH) \ __PMC_EV(OCTEON, CPREF) \ __PMC_EV(OCTEON, ICA) \ __PMC_EV(OCTEON, II) \ __PMC_EV(OCTEON, IP) \ __PMC_EV(OCTEON, CIMISS) \ __PMC_EV(OCTEON, WBUF) \ __PMC_EV(OCTEON, WDAT) \ __PMC_EV(OCTEON, WBUFLD) \ __PMC_EV(OCTEON, WBUFFL) \ __PMC_EV(OCTEON, WBUFTR) \ __PMC_EV(OCTEON, BADD) \ __PMC_EV(OCTEON, BADDL2) \ __PMC_EV(OCTEON, BFILL) \ __PMC_EV(OCTEON, DDIDS) \ __PMC_EV(OCTEON, IDIDS) \ __PMC_EV(OCTEON, DIDNA) \ __PMC_EV(OCTEON, LDS) \ __PMC_EV(OCTEON, LMLDS) \ __PMC_EV(OCTEON, IOLDS) \ __PMC_EV(OCTEON, DMLDS) \ __PMC_EV(OCTEON, STS) \ __PMC_EV(OCTEON, LMSTS) \ __PMC_EV(OCTEON, IOSTS) \ __PMC_EV(OCTEON, IOBDMA) \ __PMC_EV(OCTEON, DTLB) \ __PMC_EV(OCTEON, DTLBAD) \ __PMC_EV(OCTEON, ITLB) \ __PMC_EV(OCTEON, SYNC) \ __PMC_EV(OCTEON, SYNCIOB) \ __PMC_EV(OCTEON, SYNCW) #define PMC_EV_OCTEON_FIRST PMC_EV_OCTEON_CLK #define PMC_EV_OCTEON_LAST PMC_EV_OCTEON_SYNCW #define __PMC_EV_PPC7450() \ __PMC_EV(PPC7450, CYCLE) \ __PMC_EV(PPC7450, INSTR_COMPLETED) \ __PMC_EV(PPC7450, TLB_BIT_TRANSITIONS) \ __PMC_EV(PPC7450, INSTR_DISPATCHED) \ __PMC_EV(PPC7450, PMON_EXCEPT) \ __PMC_EV(PPC7450, PMON_SIG) \ __PMC_EV(PPC7450, VPU_INSTR_COMPLETED) \ __PMC_EV(PPC7450, VFPU_INSTR_COMPLETED) \ __PMC_EV(PPC7450, VIU1_INSTR_COMPLETED) \ __PMC_EV(PPC7450, VIU2_INSTR_COMPLETED) \ __PMC_EV(PPC7450, MTVSCR_INSTR_COMPLETED) \ __PMC_EV(PPC7450, MTVRSAVE_INSTR_COMPLETED) \ __PMC_EV(PPC7450, VPU_INSTR_WAIT_CYCLES) \ __PMC_EV(PPC7450, VFPU_INSTR_WAIT_CYCLES) \ __PMC_EV(PPC7450, VIU1_INSTR_WAIT_CYCLES) \ __PMC_EV(PPC7450, VIU2_INSTR_WAIT_CYCLES) \ __PMC_EV(PPC7450, MFVSCR_SYNC_CYCLES) \ __PMC_EV(PPC7450, VSCR_SAT_SET) \ __PMC_EV(PPC7450, STORE_INSTR_COMPLETED) \ __PMC_EV(PPC7450, L1_INSTR_CACHE_MISSES) \ __PMC_EV(PPC7450, L1_DATA_SNOOPS) \ __PMC_EV(PPC7450, UNRESOLVED_BRANCHES) \ __PMC_EV(PPC7450, SPEC_BUFFER_CYCLES) \ __PMC_EV(PPC7450, BRANCH_UNIT_STALL_CYCLES) \ __PMC_EV(PPC7450, TRUE_BRANCH_TARGET_HITS) \ __PMC_EV(PPC7450, BRANCH_LINK_STAC_PREDICTED) \ __PMC_EV(PPC7450, GPR_ISSUE_QUEUE_DISPATCHES) \ __PMC_EV(PPC7450, CYCLES_THREE_INSTR_DISPATCHED) \ __PMC_EV(PPC7450, THRESHOLD_INSTR_QUEUE_ENTRIES_CYCLES) \ __PMC_EV(PPC7450, THRESHOLD_VEC_INSTR_QUEUE_ENTRIES_CYCLES) \ __PMC_EV(PPC7450, CYCLES_NO_COMPLETED_INSTRS) \ __PMC_EV(PPC7450, IU2_INSTR_COMPLETED) \ __PMC_EV(PPC7450, BRANCHES_COMPLETED) \ __PMC_EV(PPC7450, EIEIO_INSTR_COMPLETED) \ __PMC_EV(PPC7450, MTSPR_INSTR_COMPLETED) \ __PMC_EV(PPC7450, SC_INSTR_COMPLETED) \ __PMC_EV(PPC7450, LS_LM_COMPLETED) \ __PMC_EV(PPC7450, ITLB_HW_TABLE_SEARCH_CYCLES) \ __PMC_EV(PPC7450, DTLB_HW_SEARCH_CYCLES_OVER_THRESHOLD) \ __PMC_EV(PPC7450, L1_INSTR_CACHE_ACCESSES) \ __PMC_EV(PPC7450, INSTR_BKPT_MATCHES) \ __PMC_EV(PPC7450, L1_DATA_CACHE_LOAD_MISS_CYCLES_OVER_THRESHOLD)\ __PMC_EV(PPC7450, L1_DATA_SNOOP_HIT_ON_MODIFIED) \ __PMC_EV(PPC7450, LOAD_MISS_ALIAS) \ __PMC_EV(PPC7450, LOAD_MISS_ALIAS_ON_TOUCH) \ __PMC_EV(PPC7450, TOUCH_ALIAS) \ __PMC_EV(PPC7450, L1_DATA_SNOOP_HIT_CASTOUT_QUEUE) \ __PMC_EV(PPC7450, L1_DATA_SNOOP_HIT_CASTOUT) \ __PMC_EV(PPC7450, L1_DATA_SNOOP_HITS) \ __PMC_EV(PPC7450, WRITE_THROUGH_STORES) \ __PMC_EV(PPC7450, CACHE_INHIBITED_STORES) \ __PMC_EV(PPC7450, L1_DATA_LOAD_HIT) \ __PMC_EV(PPC7450, L1_DATA_TOUCH_HIT) \ __PMC_EV(PPC7450, L1_DATA_STORE_HIT) \ __PMC_EV(PPC7450, L1_DATA_TOTAL_HITS) \ __PMC_EV(PPC7450, DST_INSTR_DISPATCHED) \ __PMC_EV(PPC7450, REFRESHED_DSTS) \ __PMC_EV(PPC7450, SUCCESSFUL_DST_TABLE_SEARCHES) \ __PMC_EV(PPC7450, DSS_INSTR_COMPLETED) \ __PMC_EV(PPC7450, DST_STREAM_0_CACHE_LINE_FETCHES) \ __PMC_EV(PPC7450, VTQ_SUSPENDS_DUE_TO_CTX_CHANGE) \ __PMC_EV(PPC7450, VTQ_LINE_FETCH_HIT) \ __PMC_EV(PPC7450, VEC_LOAD_INSTR_COMPLETED) \ __PMC_EV(PPC7450, FP_STORE_INSTR_COMPLETED_IN_LSU) \ __PMC_EV(PPC7450, FPU_RENORMALIZATION) \ __PMC_EV(PPC7450, FPU_DENORMALIZATION) \ __PMC_EV(PPC7450, FP_STORE_CAUSES_STALL_IN_LSU) \ __PMC_EV(PPC7450, LD_ST_TRUE_ALIAS_STALL) \ __PMC_EV(PPC7450, LSU_INDEXED_ALIAS_STALL) \ __PMC_EV(PPC7450, LSU_ALIAS_VS_FSQ_WB0_WB1) \ __PMC_EV(PPC7450, LSU_ALIAS_VS_CSQ) \ __PMC_EV(PPC7450, LSU_LOAD_HIT_LINE_ALIAS_VS_CSQ0) \ __PMC_EV(PPC7450, LSU_LOAD_MISS_LINE_ALIAS_VS_CSQ0) \ __PMC_EV(PPC7450, LSU_TOUCH_LINE_ALIAS_VS_FSQ_WB0_WB1) \ __PMC_EV(PPC7450, LSU_TOUCH_ALIAS_VS_CSQ) \ __PMC_EV(PPC7450, LSU_LMQ_FULL_STALL) \ __PMC_EV(PPC7450, FP_LOAD_INSTR_COMPLETED_IN_LSU) \ __PMC_EV(PPC7450, FP_LOAD_SINGLE_INSTR_COMPLETED_IN_LSU) \ __PMC_EV(PPC7450, FP_LOAD_DOUBLE_COMPLETED_IN_LSU) \ __PMC_EV(PPC7450, LSU_RA_LATCH_STALL) \ __PMC_EV(PPC7450, LSU_LOAD_VS_STORE_QUEUE_ALIAS_STALL) \ __PMC_EV(PPC7450, LSU_LMQ_INDEX_ALIAS) \ __PMC_EV(PPC7450, LSU_STORE_QUEUE_INDEX_ALIAS) \ __PMC_EV(PPC7450, LSU_CSQ_FORWARDING) \ __PMC_EV(PPC7450, LSU_MISALIGNED_LOAD_FINISH) \ __PMC_EV(PPC7450, LSU_MISALIGN_STORE_COMPLETED) \ __PMC_EV(PPC7450, LSU_MISALIGN_STALL) \ __PMC_EV(PPC7450, FP_ONE_QUARTER_FPSCR_RENAMES_BUSY) \ __PMC_EV(PPC7450, FP_ONE_HALF_FPSCR_RENAMES_BUSY) \ __PMC_EV(PPC7450, FP_THREE_QUARTERS_FPSCR_RENAMES_BUSY) \ __PMC_EV(PPC7450, FP_ALL_FPSCR_RENAMES_BUSY) \ __PMC_EV(PPC7450, FP_DENORMALIZED_RESULT) \ __PMC_EV(PPC7450, L1_DATA_TOTAL_MISSES) \ __PMC_EV(PPC7450, DISPATCHES_TO_FPR_ISSUE_QUEUE) \ __PMC_EV(PPC7450, LSU_INSTR_COMPLETED) \ __PMC_EV(PPC7450, LOAD_INSTR_COMPLETED) \ __PMC_EV(PPC7450, SS_SM_INSTR_COMPLETED) \ __PMC_EV(PPC7450, TLBIE_INSTR_COMPLETED) \ __PMC_EV(PPC7450, LWARX_INSTR_COMPLETED) \ __PMC_EV(PPC7450, MFSPR_INSTR_COMPLETED) \ __PMC_EV(PPC7450, REFETCH_SERIALIZATION) \ __PMC_EV(PPC7450, COMPLETION_QUEUE_ENTRIES_OVER_THRESHOLD) \ __PMC_EV(PPC7450, CYCLES_ONE_INSTR_DISPATCHED) \ __PMC_EV(PPC7450, CYCLES_TWO_INSTR_COMPLETED) \ __PMC_EV(PPC7450, ITLB_NON_SPECULATIVE_MISSES) \ __PMC_EV(PPC7450, CYCLES_WAITING_FROM_L1_INSTR_CACHE_MISS) \ __PMC_EV(PPC7450, L1_DATA_LOAD_ACCESS_MISS) \ __PMC_EV(PPC7450, L1_DATA_TOUCH_MISS) \ __PMC_EV(PPC7450, L1_DATA_STORE_MISS) \ __PMC_EV(PPC7450, L1_DATA_TOUCH_MISS_CYCLES) \ __PMC_EV(PPC7450, L1_DATA_CYCLES_USED) \ __PMC_EV(PPC7450, DST_STREAM_1_CACHE_LINE_FETCHES) \ __PMC_EV(PPC7450, VTQ_STREAM_CANCELED_PREMATURELY) \ __PMC_EV(PPC7450, VTQ_RESUMES_DUE_TO_CTX_CHANGE) \ __PMC_EV(PPC7450, VTQ_LINE_FETCH_MISS) \ __PMC_EV(PPC7450, VTQ_LINE_FETCH) \ __PMC_EV(PPC7450, TLBIE_SNOOPS) \ __PMC_EV(PPC7450, L1_INSTR_CACHE_RELOADS) \ __PMC_EV(PPC7450, L1_DATA_CACHE_RELOADS) \ __PMC_EV(PPC7450, L1_DATA_CACHE_CASTOUTS_TO_L2) \ __PMC_EV(PPC7450, STORE_MERGE_GATHER) \ __PMC_EV(PPC7450, CACHEABLE_STORE_MERGE_TO_32_BYTES) \ __PMC_EV(PPC7450, DATA_BKPT_MATCHES) \ __PMC_EV(PPC7450, FALL_THROUGH_BRANCHES_PROCESSED) \ __PMC_EV(PPC7450, \ FIRST_SPECULATIVE_BRANCH_BUFFER_RESOLVED_CORRECTLY) \ __PMC_EV(PPC7450, SECOND_SPECULATION_BUFFER_ACTIVE) \ __PMC_EV(PPC7450, BPU_STALL_ON_LR_DEPENDENCY) \ __PMC_EV(PPC7450, BTIC_MISS) \ __PMC_EV(PPC7450, BRANCH_LINK_STACK_CORRECTLY_RESOLVED) \ __PMC_EV(PPC7450, FPR_ISSUE_STALLED) \ __PMC_EV(PPC7450, SWITCHES_BETWEEN_PRIV_USER) \ __PMC_EV(PPC7450, LSU_COMPLETES_FP_STORE_SINGLE) \ __PMC_EV(PPC7450, VR_ISSUE_QUEUE_DISPATCHES) \ __PMC_EV(PPC7450, VR_STALLS) \ __PMC_EV(PPC7450, GPR_RENAME_BUFFER_ENTRIES_OVER_THRESHOLD) \ __PMC_EV(PPC7450, FPR_ISSUE_QUEUE_ENTRIES) \ __PMC_EV(PPC7450, FPU_INSTR_COMPLETED) \ __PMC_EV(PPC7450, STWCX_INSTR_COMPLETED) \ __PMC_EV(PPC7450, LS_LM_INSTR_PIECES) \ __PMC_EV(PPC7450, ITLB_HW_SEARCH_CYCLES_OVER_THRESHOLD) \ __PMC_EV(PPC7450, DTLB_MISSES) \ __PMC_EV(PPC7450, CANCELLED_L1_INSTR_CACHE_MISSES) \ __PMC_EV(PPC7450, L1_DATA_CACHE_OP_HIT) \ __PMC_EV(PPC7450, L1_DATA_LOAD_MISS_CYCLES) \ __PMC_EV(PPC7450, L1_DATA_PUSHES) \ __PMC_EV(PPC7450, L1_DATA_TOTAL_MISS) \ __PMC_EV(PPC7450, VT2_FETCHES) \ __PMC_EV(PPC7450, TAKEN_BRANCHES_PROCESSED) \ __PMC_EV(PPC7450, BRANCH_FLUSHES) \ __PMC_EV(PPC7450, \ SECOND_SPECULATIVE_BRANCH_BUFFER_RESOLVED_CORRECTLY) \ __PMC_EV(PPC7450, THIRD_SPECULATION_BUFFER_ACTIVE) \ __PMC_EV(PPC7450, BRANCH_UNIT_STALL_ON_CTR_DEPENDENCY) \ __PMC_EV(PPC7450, FAST_BTIC_HIT) \ __PMC_EV(PPC7450, BRANCH_LINK_STACK_MISPREDICTED) \ __PMC_EV(PPC7450, CYCLES_THREE_INSTR_COMPLETED) \ __PMC_EV(PPC7450, CYCLES_NO_INSTR_DISPATCHED) \ __PMC_EV(PPC7450, GPR_ISSUE_QUEUE_ENTRIES_OVER_THRESHOLD) \ __PMC_EV(PPC7450, GPR_ISSUE_QUEUE_STALLED) \ __PMC_EV(PPC7450, IU1_INSTR_COMPLETED) \ __PMC_EV(PPC7450, DSSALL_INSTR_COMPLETED) \ __PMC_EV(PPC7450, TLBSYNC_INSTR_COMPLETED) \ __PMC_EV(PPC7450, SYNC_INSTR_COMPLETED) \ __PMC_EV(PPC7450, SS_SM_INSTR_PIECES) \ __PMC_EV(PPC7450, DTLB_HW_SEARCH_CYCLES) \ __PMC_EV(PPC7450, SNOOP_RETRIES) \ __PMC_EV(PPC7450, SUCCESSFUL_STWCX) \ __PMC_EV(PPC7450, DST_STREAM_3_CACHE_LINE_FETCHES) \ __PMC_EV(PPC7450, \ THIRD_SPECULATIVE_BRANCH_BUFFER_RESOLVED_CORRECTLY) \ __PMC_EV(PPC7450, MISPREDICTED_BRANCHES) \ __PMC_EV(PPC7450, FOLDED_BRANCHES) \ __PMC_EV(PPC7450, FP_STORE_DOUBLE_COMPLETES_IN_LSU) \ __PMC_EV(PPC7450, L2_CACHE_HITS) \ __PMC_EV(PPC7450, L3_CACHE_HITS) \ __PMC_EV(PPC7450, L2_INSTR_CACHE_MISSES) \ __PMC_EV(PPC7450, L3_INSTR_CACHE_MISSES) \ __PMC_EV(PPC7450, L2_DATA_CACHE_MISSES) \ __PMC_EV(PPC7450, L3_DATA_CACHE_MISSES) \ __PMC_EV(PPC7450, L2_LOAD_HITS) \ __PMC_EV(PPC7450, L2_STORE_HITS) \ __PMC_EV(PPC7450, L3_LOAD_HITS) \ __PMC_EV(PPC7450, L3_STORE_HITS) \ __PMC_EV(PPC7450, L2_TOUCH_HITS) \ __PMC_EV(PPC7450, L3_TOUCH_HITS) \ __PMC_EV(PPC7450, SNOOP_MODIFIED) \ __PMC_EV(PPC7450, SNOOP_VALID) \ __PMC_EV(PPC7450, INTERVENTION) \ __PMC_EV(PPC7450, L2_CACHE_MISSES) \ __PMC_EV(PPC7450, L3_CACHE_MISSES) \ __PMC_EV(PPC7450, L2_CACHE_CASTOUTS) \ __PMC_EV(PPC7450, L3_CACHE_CASTOUTS) \ __PMC_EV(PPC7450, L2SQ_FULL_CYCLES) \ __PMC_EV(PPC7450, L3SQ_FULL_CYCLES) \ __PMC_EV(PPC7450, RAQ_FULL_CYCLES) \ __PMC_EV(PPC7450, WAQ_FULL_CYCLES) \ __PMC_EV(PPC7450, L1_EXTERNAL_INTERVENTIONS) \ __PMC_EV(PPC7450, L2_EXTERNAL_INTERVENTIONS) \ __PMC_EV(PPC7450, L3_EXTERNAL_INTERVENTIONS) \ __PMC_EV(PPC7450, EXTERNAL_INTERVENTIONS) \ __PMC_EV(PPC7450, EXTERNAL_PUSHES) \ __PMC_EV(PPC7450, EXTERNAL_SNOOP_RETRY) \ __PMC_EV(PPC7450, DTQ_FULL_CYCLES) \ __PMC_EV(PPC7450, BUS_RETRY) \ __PMC_EV(PPC7450, L2_VALID_REQUEST) \ __PMC_EV(PPC7450, BORDQ_FULL) \ __PMC_EV(PPC7450, BUS_TAS_FOR_READS) \ __PMC_EV(PPC7450, BUS_TAS_FOR_WRITES) \ __PMC_EV(PPC7450, BUS_READS_NOT_RETRIED) \ __PMC_EV(PPC7450, BUS_WRITES_NOT_RETRIED) \ __PMC_EV(PPC7450, BUS_READS_WRITES_NOT_RETRIED) \ __PMC_EV(PPC7450, BUS_RETRY_DUE_TO_L1_RETRY) \ __PMC_EV(PPC7450, BUS_RETRY_DUE_TO_PREVIOUS_ADJACENT) \ __PMC_EV(PPC7450, BUS_RETRY_DUE_TO_COLLISION) \ __PMC_EV(PPC7450, BUS_RETRY_DUE_TO_INTERVENTION_ORDERING) \ __PMC_EV(PPC7450, SNOOP_REQUESTS) \ __PMC_EV(PPC7450, PREFETCH_ENGINE_REQUEST) \ __PMC_EV(PPC7450, PREFETCH_ENGINE_COLLISION_VS_LOAD) \ __PMC_EV(PPC7450, PREFETCH_ENGINE_COLLISION_VS_STORE) \ __PMC_EV(PPC7450, PREFETCH_ENGINE_COLLISION_VS_INSTR_FETCH) \ __PMC_EV(PPC7450, \ PREFETCH_ENGINE_COLLISION_VS_LOAD_STORE_INSTR_FETCH) \ __PMC_EV(PPC7450, PREFETCH_ENGINE_FULL) #define PMC_EV_PPC7450_FIRST PMC_EV_PPC7450_CYCLE #define PMC_EV_PPC7450_LAST PMC_EV_PPC7450_PREFETCH_ENGINE_FULL #define __PMC_EV_PPC970() \ __PMC_EV(PPC970, INSTR_COMPLETED) \ __PMC_EV(PPC970, MARKED_GROUP_DISPATCH) \ __PMC_EV(PPC970, MARKED_STORE_COMPLETED) \ __PMC_EV(PPC970, GCT_EMPTY) \ __PMC_EV(PPC970, RUN_CYCLES) \ __PMC_EV(PPC970, OVERFLOW) \ __PMC_EV(PPC970, CYCLES) \ __PMC_EV(PPC970, THRESHOLD_TIMEOUT) \ __PMC_EV(PPC970, GROUP_DISPATCH) \ __PMC_EV(PPC970, BR_MARKED_INSTR_FINISH) \ __PMC_EV(PPC970, GCT_EMPTY_BY_SRQ_FULL) \ __PMC_EV(PPC970, STOP_COMPLETION) \ __PMC_EV(PPC970, LSU_EMPTY) \ __PMC_EV(PPC970, MARKED_STORE_WITH_INTR) \ __PMC_EV(PPC970, CYCLES_IN_SUPER) \ __PMC_EV(PPC970, VPU_MARKED_INSTR_COMPLETED) \ __PMC_EV(PPC970, FXU0_IDLE_FXU1_BUSY) \ __PMC_EV(PPC970, SRQ_EMPTY) \ __PMC_EV(PPC970, MARKED_GROUP_COMPLETED) \ __PMC_EV(PPC970, CR_MARKED_INSTR_FINISH) \ __PMC_EV(PPC970, DISPATCH_SUCCESS) \ __PMC_EV(PPC970, FXU0_IDLE_FXU1_IDLE) \ __PMC_EV(PPC970, ONE_PLUS_INSTR_COMPLETED) \ __PMC_EV(PPC970, GROUP_MARKED_IDU) \ __PMC_EV(PPC970, MARKED_GROUP_COMPLETE_TIMEOUT) \ __PMC_EV(PPC970, FXU0_BUSY_FXU1_BUSY) \ __PMC_EV(PPC970, MARKED_STORE_SENT_TO_STS) \ __PMC_EV(PPC970, FXU_MARKED_INSTR_FINISHED) \ __PMC_EV(PPC970, MARKED_GROUP_ISSUED) \ __PMC_EV(PPC970, FXU0_BUSY_FXU1_IDLE) \ __PMC_EV(PPC970, GROUP_COMPLETED) \ __PMC_EV(PPC970, FPU_MARKED_INSTR_COMPLETED) \ __PMC_EV(PPC970, MARKED_INSTR_FINISH_ANY_UNIT) \ __PMC_EV(PPC970, EXTERNAL_INTERRUPT) \ __PMC_EV(PPC970, GROUP_DISPATCH_REJECT) \ __PMC_EV(PPC970, LSU_MARKED_INSTR_FINISH) \ __PMC_EV(PPC970, TIMEBASE_EVENT) \ __PMC_EV(PPC970, LSU_COMPLETION_STALL) \ __PMC_EV(PPC970, FXU_COMPLETION_STALL) \ __PMC_EV(PPC970, DCACHE_MISS_COMPLETION_STALL) \ __PMC_EV(PPC970, FPU_COMPLETION_STALL) \ __PMC_EV(PPC970, FXU_LONG_INSTR_COMPLETION_STALL) \ __PMC_EV(PPC970, REJECT_COMPLETION_STALL) \ __PMC_EV(PPC970, FPU_LONG_INSTR_COMPLETION_STALL) \ __PMC_EV(PPC970, GCT_EMPTY_BY_ICACHE_MISS) \ __PMC_EV(PPC970, REJECT_COMPLETION_STALL_ERAT_MISS) \ __PMC_EV(PPC970, GCT_EMPTY_BY_BRANCH_MISS_PREDICT) \ __PMC_EV(PPC970, BUS_HIGH) \ __PMC_EV(PPC970, BUS_LOW) \ __PMC_EV(PPC970, ADDER) #define PMC_EV_PPC970_FIRST PMC_EV_PPC970_INSTR_COMPLETED #define PMC_EV_PPC970_LAST PMC_EV_PPC970_ADDER /* * All known PMC events. * * PMC event numbers are allocated sparsely to allow new PMC events to * be added to a PMC class without breaking ABI compatibility. The * current allocation scheme is: * * START #EVENTS DESCRIPTION * 0 0x1000 Reserved * 0x1000 0x0001 TSC * 0x2000 0x0080 AMD K7 events * 0x2080 0x0100 AMD K8 events * 0x10000 0x0080 INTEL architectural fixed-function events * 0x10080 0x0F80 INTEL architectural programmable events * 0x11000 0x0080 INTEL Pentium 4 events * 0x11080 0x0080 INTEL Pentium MMX events * 0x11100 0x0100 INTEL Pentium Pro/P-II/P-III/Pentium-M events * 0x11200 0x00FF INTEL XScale events * 0x11300 0x00FF MIPS 24K events * 0x20000 0x1000 Software events */ #define __PMC_EVENTS() \ __PMC_EV_BLOCK(TSC, 0x01000) \ __PMC_EV_TSC() \ __PMC_EV_BLOCK(K7, 0x2000) \ __PMC_EV_K7() \ __PMC_EV_BLOCK(K8, 0x2080) \ __PMC_EV_K8() \ __PMC_EV_BLOCK(IAF, 0x10000) \ __PMC_EV_IAF() \ __PMC_EV_BLOCK(IAP, 0x10080) \ __PMC_EV_IAP() \ __PMC_EV_BLOCK(P4, 0x11000) \ __PMC_EV_P4() \ __PMC_EV_BLOCK(P5, 0x11080) \ __PMC_EV_P5() \ __PMC_EV_BLOCK(P6, 0x11100) \ __PMC_EV_P6() \ __PMC_EV_BLOCK(XSCALE, 0x11200) \ __PMC_EV_XSCALE() \ __PMC_EV_BLOCK(MIPS24K, 0x11300) \ __PMC_EV_MIPS24K() \ __PMC_EV_BLOCK(OCTEON, 0x11400) \ __PMC_EV_OCTEON() \ __PMC_EV_BLOCK(UCF, 0x12000) \ __PMC_EV_UCF() \ __PMC_EV_BLOCK(UCP, 0x12080) \ __PMC_EV_UCP() \ __PMC_EV_BLOCK(PPC7450, 0x13000) \ __PMC_EV_PPC7450() \ __PMC_EV_BLOCK(PPC970, 0x13100) \ __PMC_EV_PPC970() \ #define PMC_EVENT_FIRST PMC_EV_TSC_TSC #define PMC_EVENT_LAST PMC_EV_SOFT_LAST #endif /* _DEV_HWPMC_PMC_EVENTS_H_ */ Index: stable/10 =================================================================== --- stable/10 (revision 320105) +++ stable/10 (revision 320106) Property changes on: stable/10 ___________________________________________________________________ Modified: svn:mergeinfo ## -0,0 +0,1 ## Merged /head:r279832